diff --git "a/application/gui.exe - \345\277\253\346\215\267\346\226\271\345\274\217.lnk" "b/application/\345\244\232\345\252\222\344\275\223\350\247\206\351\242\221\345\244\204\347\220\206\351\255\224\347\233\222\344\270\212\344\275\215\346\234\272.lnk" similarity index 100% rename from "application/gui.exe - \345\277\253\346\215\267\346\226\271\345\274\217.lnk" rename to "application/\345\244\232\345\252\222\344\275\223\350\247\206\351\242\221\345\244\204\347\220\206\351\255\224\347\233\222\344\270\212\344\275\215\346\234\272.lnk" diff --git a/bitstream files/multimedia_video_processor_1080p.sfc b/bitstream files/multimedia_video_processor_1080p.sfc new file mode 100644 index 0000000..5ea85b2 Binary files /dev/null and b/bitstream files/multimedia_video_processor_1080p.sfc differ diff --git a/bitstream files/rotate_freq_led_display.sbit b/bitstream files/rotate_freq_led_display.sbit new file mode 100644 index 0000000..83bc0fe Binary files /dev/null and b/bitstream files/rotate_freq_led_display.sbit differ diff --git "a/doc/\346\250\241\345\235\227/adjust_color/adjust_color.html" "b/doc/\346\250\241\345\235\227/adjust_color/adjust_color.html" new file mode 100644 index 0000000..9e95c8a --- /dev/null +++ "b/doc/\346\250\241\345\235\227/adjust_color/adjust_color.html" @@ -0,0 +1,1227 @@ + + + + + + TerosHDL + + + +
+ +
+

Entity: adjust_color

Diagram

clk resetn signed [8:0] h_s_data signed [8:0] s_s_data signed [8:0] v_s_data [23:0] pixel_s_data pixel_s_valid [23:0] res_m_data res_m_valid +

Ports

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Port nameDirectionTypeDescription
clkinput时钟
resetninput复位
h_s_datainputsigned [8:0]色相调整值
s_s_datainputsigned [8:0]饱和度调整值
v_s_datainputsigned [8:0]明度调整值
pixel_s_datainput[23:0]输入像素点-RGB
pixel_s_validinput输入有效信号
res_m_dataoutput[23:0]输出像素点
res_m_validoutput输出有效信号

Signals

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameTypeDescription
raw_h_datawire [7:0]
raw_s_datawire [7:0]
raw_v_datawire [7:0]
modified_h_datawire [7:0]
modified_s_datawire [7:0]
modified_v_datawire [7:0]
raw_hsv_validwire
modified_hsv_validwire

Instantiations

+





+
+ + \ No newline at end of file diff --git "a/doc/\346\250\241\345\235\227/eth/eth_udp.html" "b/doc/\346\250\241\345\235\227/eth/eth_udp.html" new file mode 100644 index 0000000..c3af5f6 --- /dev/null +++ "b/doc/\346\250\241\345\235\227/eth/eth_udp.html" @@ -0,0 +1,1560 @@ + + + + + + TerosHDL + + + +
+ +
+

Entity: eth_udp

Diagram

BOARD_MAC BOARD_IP BOARD_PORT DES_MAC DES_IP DES_PORT IDELAY_VALUE clk resetn eth_rxc eth_rx_ctl [3:0] eth_rxd udp_rx_m_data_tready [ 7:0] udp_tx_s_data udp_tx_s_valid udp_tx_s_start [15:0] udp_tx_s_tsize udp_tx_s_last eth_txc eth_tx_ctl [3:0] eth_txd gmii_clk udp_rx_pkt_start udp_rx_pkt_done udp_rx_pkt_en [ 7 : 0] udp_rx_pkt_data [15 : 0] udp_rx_pkt_dest_port [15 : 0] udp_rx_pkt_byte_num [ 7:0] udp_rx_m_data_tdata udp_rx_m_data_tlast udp_rx_m_data_tvalid [15:0] udp_rx_m_data_tsize [ 5:0] udp_rx_m_cached_pkt_num +

Generics

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Generic nameTypeValueDescription
BOARD_MAC48'h00_11_22_33_44_55
BOARD_IP{8'd192, 8'd168, 8'd10, 8'd10}
BOARD_PORT16'd1234
DES_MAC48'hff_ff_ff_ff_ff_ff
DES_IP{8'd192, 8'd168, 8'd10, 8'd102}
DES_PORT16'd1234
IDELAY_VALUE0
+

Ports

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Port nameDirectionTypeDescription
clkinput系统时钟
resetninput系统复位信号,低电平有效
eth_rxcinputRGMII接收数据时钟
eth_rx_ctlinputRGMII输入数据有效信号
eth_rxdinput[3:0]RGMII输入数据
eth_txcoutputRGMII发送数据时钟
eth_tx_ctloutputRGMII输出数据有效信号
eth_txdoutput[3:0]RGMII输出数据
gmii_clkoutputGMII接收时钟
udp_rx_pkt_startoutput以太网单包数据接收开始信号
udp_rx_pkt_doneoutput以太网单包数据接收完成信号
udp_rx_pkt_enoutput以太网接收的数据使能信号
udp_rx_pkt_dataoutput[ 7 : 0]以太网接收的数据
udp_rx_pkt_dest_portoutput[15 : 0]以太网接收目的地端口
udp_rx_pkt_byte_numoutput[15 : 0]以太网接收的有效字节数 单位:byte
udp_rx_m_data_tdataoutput[ 7:0]待接受数据 数据
udp_rx_m_data_tlastoutput待接受数据 结束传输
udp_rx_m_data_tvalidoutput待接受数据 有效信号
udp_rx_m_data_treadyinput待接受数据 准备信号
udp_rx_m_data_tsizeoutput[15:0]待接受数据 数据量
udp_rx_m_cached_pkt_numoutput[ 5:0]待接受数据 已缓存数据包数量
udp_tx_s_datainput[ 7:0]待发送数据 数据
udp_tx_s_validinput待发送数据 有效信号
udp_tx_s_startinput待发送数据 开始传输
udp_tx_s_tsizeinput[15:0]待发送数据 数据量
udp_tx_s_lastinput待发送数据 结束传输

Signals

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameTypeDescription
gmii_rxd_validwire
gmii_rxd_datawire [ 7:0]
gmii_txd_validwire
gmii_txd_datawire [ 7:0]
arp_gmii_tx_enwire
arp_gmii_txdwire [ 7:0]
arp_rx_donewire
arp_rx_typewire
src_macwire [47:0]
src_ipwire [31:0]
arp_tx_enwire
arp_tx_typewire
des_macwire [47:0]
des_ipwire [31:0]
arp_tx_donewire
icmp_gmii_tx_enwire
icmp_gmii_txdwire [ 7:0]
icmp_rec_pkt_donewire
icmp_rec_enwire
icmp_rec_datawire [ 7:0]
icmp_rec_byte_numwire [15:0]
icmp_tx_byte_numwire [15:0]
icmp_tx_donewire
icmp_tx_reqwire
icmp_tx_datawire [ 7:0]
icmp_tx_start_enwire
udp_gmii_tx_enwire
udp_gmii_txdwire [ 7:0]
tx_byte_numwire [15:0]
udp_tx_donewire
udp_tx_reqwire
udp_tx_datawire [ 7:0]
tx_start_enwire
rec_datawire [ 7:0]
rec_enwire
tx_reqwire
tx_datawire [ 7:0]
default_tx_buffer_wr_enreg
default_tx_buffer_startreg
default_tx_buffer_donereg

Processes

Type: always

Type: always

Type: always

Instantiations

+





+
+ + \ No newline at end of file diff --git "a/doc/\346\250\241\345\235\227/hdmi/hdmi_in_top.html" "b/doc/\346\250\241\345\235\227/hdmi/hdmi_in_top.html" new file mode 100644 index 0000000..ff4c491 --- /dev/null +++ "b/doc/\346\250\241\345\235\227/hdmi/hdmi_in_top.html" @@ -0,0 +1,1376 @@ + + + + + + TerosHDL + + + +
+ +
+

Entity: hdmi_in_top

Diagram

IMAGE_W IMAGE_H IMAGE_SIZE clk rst [7:0] r_in [7:0] g_in [7:0] b_in vs_in hs_in de_in [15:0] hdmi_data hdmi_data_valid hdmi_vs_out +

Generics

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Generic nameTypeValueDescription
IMAGE_W1280
IMAGE_H720
IMAGE_SIZE11
+

Ports

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Port nameDirectionTypeDescription
clkinput时钟
rstinput复位
r_ininput[7:0]像素点Red通道
g_ininput[7:0]像素点Green通道
b_ininput[7:0]像素点Blue通道
vs_ininput垂直同步信号
hs_ininput水平同步信号
de_ininput数据有效信号
hdmi_dataoutput[15:0]HDMI输出数据
hdmi_data_validoutputHDMI输出有效信号
hdmi_vs_outoutputHDMI输出输出垂直同步

Signals

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameTypeDescription
r_in0reg [7:0]
g_in0reg [7:0]
b_in0reg [7:0]
r_in1reg [7:0]
g_in1reg [7:0]
b_in1reg [7:0]
r_in2reg [7:0]
g_in2reg [7:0]
b_in2reg [7:0]
r_in3reg [7:0]
g_in3reg [7:0]
b_in3reg [7:0]
vs_in0reg
hs_in0reg
de_in0reg
vs_in1reg
hs_in1reg
de_in1reg
vs_in2reg
hs_in2reg
de_in2reg
hdmi_in_enreg
EXTRACTwire [1:0]
hs_cntreg [1:0]
hdmi_data_valid0reg
de_cntreg [1:0]
cnt_hs0reg [12:0]
cnt_hs1reg [12:0]

Processes

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

+





+
+ + \ No newline at end of file diff --git "a/doc/\346\250\241\345\235\227/hdmi/sync_vg.html" "b/doc/\346\250\241\345\235\227/hdmi/sync_vg.html" new file mode 100644 index 0000000..1d1737f --- /dev/null +++ "b/doc/\346\250\241\345\235\227/hdmi/sync_vg.html" @@ -0,0 +1,1417 @@ + + + + + + TerosHDL + + + +
+ +
+

Entity: sync_vg

Diagram

X_BITS Y_BITS HDMI_1080P_EN V_TOTAL V_FP V_BP V_SYNC V_ACT H_TOTAL H_FP H_BP H_SYNC H_ACT HV_OFFSET clk rst [1:0] rd_mode [15:0] ddr_image_data ddr_rd_en vs_out hs_out de_re [15:0] hdmi_image_data [11:0] pos_x [11:0] pos_y +

Generics

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Generic nameTypeValueDescription
X_BITS12
Y_BITS12
HDMI_1080P_EN0
V_TOTAL12'd1125
V_FP12'd4
V_BP12'd36
V_SYNC12'd5
V_ACT12'd1080
H_TOTAL12'd2200
H_FP12'd88
H_BP12'd148
H_SYNC12'd44
H_ACT12'd1920
HV_OFFSET12'd0
+

Ports

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Port nameDirectionTypeDescription
clkinput时钟
rstinput复位
rd_modeinput[1:0]读取模式
ddr_rd_enoutput读取请求
ddr_image_datainput[15:0]读取数据
vs_outoutput垂直同步
hs_outoutput水平同步
de_reoutput数据有效
hdmi_image_dataoutput[15:0]输出像素点RGB数据
pos_xoutput[11:0]像素点对应的X坐标
pos_youtput[11:0]像素点对应的Y坐标

Signals

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameTypeDescription
h_countreg [X_BITS-1:0]
v_countreg [Y_BITS-1:0]
vs_out0reg
vs_out1reg
vs_out2reg
vs_out3reg
hs_out0reg
hs_out1reg
hs_out2reg
hs_out3reg
de_re0reg
de_re1reg
zero_valid0reg
zero_valid1reg
pixel_show_en0reg
pixel_show_en1reg
rd_mode0reg [1:0]
hdmi_image_data0reg [15:0]
hdmi_image_data1reg [15:0]
de_re2reg
de_re3reg

Processes

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

+





+
+ + \ No newline at end of file diff --git "a/doc/\346\250\241\345\235\227/image_filiter/image_filiter.html" "b/doc/\346\250\241\345\235\227/image_filiter/image_filiter.html" new file mode 100644 index 0000000..86e8e46 --- /dev/null +++ "b/doc/\346\250\241\345\235\227/image_filiter/image_filiter.html" @@ -0,0 +1,1259 @@ + + + + + + + TerosHDL + + + +
+ +
+

Entity: image_filiter

Diagram

reg [10:0] IMAGE_WIDTH reg [10:0] IMAGE_HEIGHT integer PIXEL_DATA_WIDTH integer R_DATA_WIDTH integer G_DATA_WIDTH integer B_DATA_WIDTH integer TH clk resetn [2:0] mode [PIXEL_DATA_WIDTH-1:0] s_pixel_data s_pixel_valid rst_busy [PIXEL_DATA_WIDTH-1:0] m_filtered_data m_filtered_valid +

Generics

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Generic nameTypeValueDescription
IMAGE_WIDTHreg [10:0]1280
IMAGE_HEIGHTreg [10:0]360
PIXEL_DATA_WIDTHinteger16
R_DATA_WIDTHinteger5
G_DATA_WIDTHinteger6
B_DATA_WIDTHinteger5
THinteger5
+

Ports

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Port nameDirectionTypeDescription
clkinput时钟
resetninput复位
rst_busyoutputFIFO初始化忙信号
modeinput[2:0]滤波模式
s_pixel_datainput[PIXEL_DATA_WIDTH-1:0]输入像素点
s_pixel_validinput输入像素点有效信号
m_filtered_dataoutput[PIXEL_DATA_WIDTH-1:0]输出像素点
m_filtered_validoutput输出像素点有效信号

Signals

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameTypeDescription
multiline_pixel_datawire [3*PIXEL_DATA_WIDTH-1:0]
pixel_validwire
matrix_datawire [9*PIXEL_DATA_WIDTH-1:0]3x3像素点矩阵
matrix_validwire3x3像素点矩阵有效信号

Instantiations

Description
+ 输入三行数据流,输出3x3矩阵

Description
+ 对矩阵滤波

+





+
+ + \ No newline at end of file diff --git "a/doc/\346\250\241\345\235\227/image_filiter/multiline_buffer.html" "b/doc/\346\250\241\345\235\227/image_filiter/multiline_buffer.html" new file mode 100644 index 0000000..2dbc885 --- /dev/null +++ "b/doc/\346\250\241\345\235\227/image_filiter/multiline_buffer.html" @@ -0,0 +1,1298 @@ + + + + + + + TerosHDL + + + +
+ +
+

Entity: multiline_buffer

Diagram

reg [10:0] IMAGE_WIDTH reg [10:0] IMAGE_HEIGHT integer PIXEL_DATA_WIDTH integer LINES_NUM clk resetn [PIXEL_DATA_WIDTH-1:0] s_pixel_data s_pixel_valid rst_busy [(LINES_NUM)\*PIXEL_DATA_WIDTH-1:0] m_multiline_pixel_data m_pixel_valid +

Generics

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Generic nameTypeValueDescription
IMAGE_WIDTHreg [10:0]1920图像宽度
IMAGE_HEIGHTreg [10:0]1080图像高度
PIXEL_DATA_WIDTHinteger16像素宽度
LINES_NUMinteger3行数
+

Ports

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Port nameDirectionTypeDescription
clkinput时钟
resetninput复位
rst_busyoutputFIFO复位忙信号
s_pixel_datainput[PIXEL_DATA_WIDTH-1:0]输入数据
s_pixel_validinput输入有效信号
m_multiline_pixel_dataoutput[(LINES_NUM)*PIXEL_DATA_WIDTH-1:0]输出列向量
m_pixel_validoutput输出有效信号

Signals

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameTypeDescription
hor_cntreg [ 10:0]
ver_cntreg [ 10:0]
tail_ver_cntreg [ 5:0]
tail_hor_cntreg [ 10:0]
srstreg
dinreg [(LINES_NUM-1)*FifoWidth-1:0]
doutwire [(LINES_NUM-1)*FifoWidth-1:0]
rd_enreg [ LINES_NUM-2:0]
wr_enreg [ LINES_NUM-2:0]
fullwire [ LINES_NUM-2:0]
emptywire [ LINES_NUM-2:0]
rst_s1reg
+

Constants

+ + + + + + + + + + + + + + + + + +
NameTypeValueDescription
FifoWidth24

Processes

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

+





+
+ + \ No newline at end of file diff --git "a/doc/\346\250\241\345\235\227/others/param_cell_unsigned.html" "b/doc/\346\250\241\345\235\227/others/param_cell_unsigned.html" new file mode 100644 index 0000000..194fa7e --- /dev/null +++ "b/doc/\346\250\241\345\235\227/others/param_cell_unsigned.html" @@ -0,0 +1,1293 @@ + + + + + + TerosHDL + + + +
+ +
+

Entity: param_cell_unsigned

Diagram

integer CLK_FREQ integer PARAM_WIDTH integer PRESSED_TRIG_CYCLE_MS integer DEFAULT_VALUE integer RANGE_MIN integer RANGE_MAX clk resetn clk_ms restore selected load_valid [PARAM_WIDTH-1:0] load_data akey_up akey_down [PARAM_WIDTH-1:0] value +

Generics

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Generic nameTypeValueDescription
CLK_FREQinteger50_000000
PARAM_WIDTHinteger3
PRESSED_TRIG_CYCLE_MSinteger100
DEFAULT_VALUEinteger0
RANGE_MINinteger0
RANGE_MAXinteger1
+

Ports

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Port nameDirectionTypeDescription
clkinput
resetninput
clk_msinput
restoreinput
selectedinput
load_validinput
load_datainput[PARAM_WIDTH-1:0]
akey_upinput
akey_downinput
valueoutput[PARAM_WIDTH-1:0]

Signals

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameTypeDescription
pressed_upwire
pressed_downwire
changed_upwire
changed_downwire
plusereg
cntreg [11:0]
clk_ms_ff0reg
clk_ms_ff1reg
pluse_msreg

Processes

Type: always

Type: always

Type: always

Type: always

Instantiations

+





+
+ + \ No newline at end of file diff --git "a/doc/\346\250\241\345\235\227/others/param_manager.html" "b/doc/\346\250\241\345\235\227/others/param_manager.html" new file mode 100644 index 0000000..4e749fb --- /dev/null +++ "b/doc/\346\250\241\345\235\227/others/param_manager.html" @@ -0,0 +1,1741 @@ + + + + + + TerosHDL + + + +
+ +
+

Entity: param_manager

Diagram

integer CLK_FREQ clk resetn akey_left akey_right akey_up akey_down akey_restore [199:0] mem [ 24:0] mem_flags [3:0] index [2:0] filiter1_mode [2:0] filiter2_mode [9:0] zoom [7:0] rotate [10:0] osd_startX [10:0] os_startY [10:0] osd_char_width [10:0] osd_char_height [9:0] rotate_A wire signed [11:0] offsetX wire signed [11:0] offsetY wire signed [8:0] modify_H wire signed [8:0] modify_S wire signed [8:0] modify_V +

Generics

+ + + + + + + + + + + + + + + + + +
Generic nameTypeValueDescription
CLK_FREQinteger50_000000
+

Ports

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Port nameDirectionTypeDescription
clkinput时钟
resetninput复位
akey_leftinput按键-左
akey_rightinput按键-右
akey_upinput按键-上
akey_downinput按键-下
akey_restoreinput按键—恢复
meminput[199:0]带加载参数
mem_flagsinput[ 24:0]参数变化标志
indexoutput[3:0]参数序号
filiter1_modeoutput[2:0]滤波器1 模式
filiter2_modeoutput[2:0]滤波器2 模式
zoomoutput[9:0]双线性插值缩放系数
rotateoutput[7:0]旋转系数
osd_startXoutput[10:0]OSD起始X坐标
os_startYoutput[10:0]OSD起始Y坐标
osd_char_widthoutput[10:0]OSD字符宽度
osd_char_heightoutput[10:0]文本行距
rotate_Aoutput[9:0]缩放系数2
offsetXoutputwire signed [11:0]图像偏移X
offsetYoutputwire signed [11:0]图像偏移Y
modify_Houtputwire signed [8:0]色相偏移
modify_Soutputwire signed [8:0]饱和度偏移
modify_Voutputwire signed [8:0]亮度偏移

Signals

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameTypeDescription
clk_msreg
ms_cntreg [29:0]
pressed_leftwire
pressed_rightwire
pressed_restorewire
changed_leftwire
changed_rightwire
changed_restorewire
selectedreg [ParamNum-1:0]
filiter1_mode_flags_ff0reg
filiter1_mode_flags_ff1reg
filiter1_mode_loadreg
filiter2_mode_flags_ff0reg
filiter2_mode_flags_ff1reg
filiter2_mode_loadreg
zoom_flags_ff0reg
zoom_flags_ff1reg
zoom_flags_ff2reg
zoom_flags_ff3reg
zoom_loadreg
rotate_flags_ff0reg
rotate_flags_ff1reg
rotate_loadreg
osd_startX_flags_ff0reg
osd_startX_flags_ff1reg
osd_startX_flags_ff2reg
osd_startX_flags_ff3reg
osd_startX_loadreg
osd_startY_flags_ff0reg
osd_startY_flags_ff1reg
osd_startY_flags_ff2reg
osd_startY_flags_ff3reg
osd_startY_loadreg
osd_char_width_flags_ff0reg
osd_char_width_flags_ff1reg
osd_char_width_flags_ff2reg
osd_char_width_flags_ff3reg
osd_char_width_loadreg
osd_char_height_flags_ff0reg
osd_char_height_flags_ff1reg
osd_char_height_flags_ff2reg
osd_char_height_flags_ff3reg
osd_char_height_loadreg
rotate_A_flags_ff0reg
rotate_A_flags_ff1reg
rotate_A_flags_ff2reg
rotate_A_flags_ff3reg
rotate_A_loadreg
offsetX_flags_ff0reg
offsetX_flags_ff1reg
offsetX_flags_ff2reg
offsetX_flags_ff3reg
offsetX_loadreg
offsetY_flags_ff0reg
offsetY_flags_ff1reg
offsetY_flags_ff2reg
offsetY_flags_ff3reg
offsetY_loadreg
modify_H_flags_ff0reg
modify_H_flags_ff1reg
modify_H_flags_ff2reg
modify_H_flags_ff3reg
modify_H_loadreg
modify_S_flags_ff0reg
modify_S_flags_ff1reg
modify_S_flags_ff2reg
modify_S_flags_ff3reg
modify_S_loadreg
modify_V_flags_ff0reg
modify_V_flags_ff1reg
modify_V_flags_ff2reg
modify_V_flags_ff3reg
modify_V_loadreg
+

Constants

+ + + + + + + + + + + + + + + + + +
NameTypeValueDescription
ParamNum14

Processes

Type: always

Type: always

Description
+ 按键控制当前选择的参数序号

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Instantiations

+





+
+ + \ No newline at end of file diff --git "a/doc/\346\250\241\345\235\227/ov5640/ov5640.html" "b/doc/\346\250\241\345\235\227/ov5640/ov5640.html" new file mode 100644 index 0000000..4713d6d --- /dev/null +++ "b/doc/\346\250\241\345\235\227/ov5640/ov5640.html" @@ -0,0 +1,1438 @@ + + + + + + TerosHDL + + + +
+ +
+

Entity: ov5640

Diagram

IMAGE_SIZE IMAGE_W IMAGE_H clk_50M clk_25M rst cmos1_vsync cmos1_href cmos1_pclk [7:0] cmos1_data cmos2_vsync cmos2_href cmos2_pclk [7:0] cmos2_data [7:0] shift_w signed [7:0] shift_h wr_clk wr_rst cmos1_scl cmos1_sda cmos1_reset cmos2_scl cmos2_sda cmos2_reset data_vs data_out_valid [15:0] data_out +

Generics

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Generic nameTypeValueDescription
IMAGE_SIZE11
IMAGE_W1280
IMAGE_H720
+

Ports

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Port nameDirectionTypeDescription
clk_50Minput50M时钟
clk_25Minput20M时钟
rstinput复位信号
cmos1_sclinoutCMOS1 IIC_SCL信号
cmos1_sdainoutCMOS1 IIC_SDA信号
cmos1_vsyncinputCMOS1 垂直同步信号
cmos1_hrefinputCMOS1 数据有效信号
cmos1_pclkinputCMOS1 像素时钟
cmos1_datainput[7:0]CMOS1 数据
cmos1_resetoutputCMOS1 复位
cmos2_sclinoutCMOS2 IIC_SCL信号
cmos2_sdainoutCMOS2 IIC_SDA信号
cmos2_vsyncinputCMOS2 垂直同步信号
cmos2_hrefinputCMOS2 数据有效信号
cmos2_pclkinputCMOS2 像素时钟
cmos2_datainput[7:0]CMOS2 数据
cmos2_resetoutputCMOS2 复位
shift_winput[7:0]图像拼接移位 横向
shift_hinputsigned [7:0]图像拼接移位 纵向
wr_clkinput数据输出 时钟
wr_rstinput数据输出 复位
data_vsoutput数据输出 垂直同步信号
data_out_validoutput视频输出 有效信号
data_outoutput[15:0]数据输出 数据

Signals

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameTypeDescription
cmos_init_donewire [1:0]
initial_enwire
cmos1_d_d0reg [7:0]
cmos1_d_d1reg [7:0]
cmos1_href_d0reg
cmos1_href_d1reg
cmos1_vsync_d0reg
cmos1_vsync_d1reg
cmos1_d_16bitwire [15:0]
cmos1_href_16bitwire
cmos2_d_16bitwire [15:0]
cmos2_href_16bitwire
cmos1_vsync0wire
cmos2_vsync0wire
pclk1wire
pclk2wire
cmos1_pclk_bufgwire
cmos1_pclk0 = ~cmos1_pclkwire
cmos2_d_d0reg [7:0]
cmos2_d_d1reg [7:0]
cmos2_href_d0reg
cmos2_href_d1reg
cmos2_vsync_d0reg
cmos2_vsync_d1reg

Processes

Type: always

Type: always

Instantiations

+





+
+ + \ No newline at end of file diff --git "a/doc/\346\250\241\345\235\227/rotate/rotate_image.html" "b/doc/\346\250\241\345\235\227/rotate/rotate_image.html" new file mode 100644 index 0000000..20f0915 --- /dev/null +++ "b/doc/\346\250\241\345\235\227/rotate/rotate_image.html" @@ -0,0 +1,1804 @@ + + + + + + + TerosHDL + + + +
+ +
+

Entity: rotate_image

Diagram

IMAGE_SIZE MIN_NUM IMAGE_W IMAGE_H clk rst [7:0] rotate_angle [9:0] rotate_amplitude wire signed [11:0] offsetX wire signed [11:0] offsetY rotate_en ddr_data_in_valid [15:0] ddr_data_in rd_ddr_addr_valid [32-1:0] rd_ddr_addr data_out_valid [15:0] data_out +

Generics

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Generic nameTypeValueDescription
IMAGE_SIZE11
MIN_NUM1280
IMAGE_W1280
IMAGE_H720
+

Ports

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Port nameDirectionTypeDescription
clkinput时钟
rstinput复位
rotate_angleinput[7:0]旋转角度
rotate_amplitudeinput[9:0]幅值
offsetXinputwire signed [11:0]位移X
offsetYinputwire signed [11:0]位移Y
rotate_eninput使能
ddr_data_in_validinput读取数据-有效
ddr_data_ininput[15:0]读取数据-数据
rd_ddr_addr_validoutput读取地址-有效
rd_ddr_addroutput[32-1:0]读取地址-数据
data_out_validoutput输出数据-有效
data_outoutput[15:0]输出数据-数据

Signals

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameTypeDescription
rotate_stareg [ 2:0]
rd_addrreg [ 7:0]
doutawire [17:0]
cos_datawire [8:0]
sin_datawire [8:0]
cos_data_multedwire [19:0]
sin_data_multedwire [19:0]
cos_data0wire [12:0]
sin_data0wire [12:0]
image_w_add_addrreg signed [IMAGE_SIZE+14-1:0]
image_h_add_addrreg signed [IMAGE_SIZE+14-1:0]
signed_zoomwire [10:0]
offsetX_ffreg signed [11:0]
offsetY_ffreg signed [11:0]
centerXreg signed [11:0]
centerYreg signed [11:0]
cnt_wreg signed [IMAGE_SIZE-1:0]
cnt_hreg signed [IMAGE_SIZE-1:0]
wr_countwire [11:0]
addr_fifo_emptywire
mult_p0[3:0]wire [IMAGE_SIZE+13-1:0]
w_mult_addreg signed [IMAGE_SIZE+14-1:0]
h_mult_addreg signed [IMAGE_SIZE+14-1:0]
image_w_valid0reg [5:0]
image_w_validwire
image_w_add0reg [IMAGE_SIZE+15-1:0]
image_h_add0reg [IMAGE_SIZE+15-1:0]
image_w_blank_validreg
image_h_blank_validreg
image_blank_validreg
rd_ddr_addr_valid1reg
rd_ddr_addwire
image_w_add1reg [IMAGE_SIZE+4-1:0]
image_w_add2reg [IMAGE_SIZE+4-1:0]
image_h_add1reg [IMAGE_SIZE+4-1:0]
image_h_add2reg [IMAGE_SIZE+4-1:0]
dinwire [3:0]
doutwire [3:0]
wr_enwire
emptywire
fullwire
addr_fifo_rd_enwire
addr_fifo_validreg
ddr_data_in_valid0reg
ddr_data_in0reg [15:0]
image_datawire [15:0]
data_emptywire
data_rd_enwire
fifo_data_validreg
rd_stareg [2:0]
rd_sta_s2reg
fifo_blank_valid = dout[0]wire
data_out2reg [15:0]
data_out_valid0wire
data_out_valid1reg
data_out_valid2reg
data_blank_out_validreg
cnt_numreg [15:0]
+

Constants

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameTypeValueDescription
IDLE3'b001
WAIT3'b010
CNT3'b100
S03'b001
S13'b010
S23'b100

Processes

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Instantiations

State machines

+ + + + + +state transitions + + +cluster_rotate_sta + +rotate_sta + + + + +IDLE + +IDLE + + + + +IDLE->IDLE + + +not (rotate_en & addr_fifo_empty)    + + + +WAIT + +WAIT + + + + +IDLE->WAIT + + +rotate_en & addr_fifo_empty    + + + +WAIT->WAIT + + +not (wr_count < (2047 - MIN_NUM))    + + + +CNT + +CNT + + + + +WAIT->CNT + + +wr_count < (2047 - MIN_NUM)    + + + +CNT->IDLE + + +cnt_h >= (IMAGE_H / 2 - 1)    +cnt_w >= (IMAGE_W / 2 - 1)    + + + +CNT->WAIT + + +not (cnt_w >= (IMAGE_W / 2 - 1))    + + + +
+ + + + + +state transitions + + +cluster_rd_sta + +rd_sta + + + + +S0 + +S0 + + + + +S0->S0 + + +not (~addr_fifo_empty)    + + + +S1 + +S1 + + + + +S0->S1 + + +~addr_fifo_empty    + + + +S1->S0 + + +addr_fifo_empty    + + + +S1->S1 + + +not ((~fifo_blank_valid) & (data_empty))    +not (addr_fifo_empty)    + + + +S2 + +S2 + + + + +S1->S2 + + +(~fifo_blank_valid) & (data_empty)    + + + +S2->S0 + + +addr_fifo_empty    +~data_empty    + + + +S2->S1 + + +not (~data_empty)    + + + +
+





+
+ + \ No newline at end of file diff --git "a/doc/\346\250\241\345\235\227/zoom/zoom_image_v1.html" "b/doc/\346\250\241\345\235\227/zoom/zoom_image_v1.html" new file mode 100644 index 0000000..91a3cd9 --- /dev/null +++ "b/doc/\346\250\241\345\235\227/zoom/zoom_image_v1.html" @@ -0,0 +1,2452 @@ + + + + + + TerosHDL + + + +
+ +
+

Entity: zoom_image_v1

Diagram

IMAGE_SIZE FRA_WIDTH IMAGE_W IMAGE_H clk rst zoom_en hdmi_out_en data_half_en fifo_full [3+FRA_WIDTH-1:0] zoom_num data_in_valid [15:0] data_in data_out_valid [15:0] data_out imag_addr_valid [IMAGE_SIZE-1:0] imag_addr zoom_done +

Generics

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Generic nameTypeValueDescription
IMAGE_SIZE11
FRA_WIDTH7
IMAGE_W1920
IMAGE_H1080
+

Ports

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Port nameDirectionTypeDescription
clkinput时钟
rstinput复位
zoom_eninput缩放使能
hdmi_out_eninputHDMI输出使能
data_half_eninput数据减半使能
fifo_fullinput输出端FIFO 满信号
zoom_numinput[3+FRA_WIDTH-1:0]缩放系数
data_in_validinput数据输入-有效
data_ininput[15:0]数据输入-数据
data_out_validoutput数据输出-有效
data_outoutput[15:0]数据输出-数据
imag_addr_validoutput数据读取地址-有效
imag_addroutput[IMAGE_SIZE-1:0]数据读取地址-地址
zoom_doneoutput一帧画面缩放完成

Signals

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameTypeDescription
zoom_stareg [6:0]
cnt_wreg signed [IMAGE_SIZE-1:0]
cnt_hreg signed [IMAGE_SIZE-1:0]
mult_cnt_hreg signed [IMAGE_SIZE-1:0]
judge_cnt_hreg signed [IMAGE_SIZE+3-1:0]
judge_cnt_h_validreg
ram_idlereg
no_need_rd_ddrreg
no_one_need_rd_ddrreg
record_ram[0:3]reg
delay_cntreg [2:0]
param_delayreg [3:0]
cnt_record_ramreg [2:0]
record_ram_validreg
data_in0reg [15:0]
data_in1reg [15:0]
data_in2reg [15:0]
data_in3reg [15:0]
coe_validreg [6:0]
data_in_valid0reg
data_in_valid1reg
data_in_valid2reg
data_in_valid3reg
rd_one_ramreg
fifo_full0reg
mult_wwire [IMAGE_SIZE+FRA_WIDTH+3-1:0]
mult_hwire [IMAGE_SIZE+FRA_WIDTH+3-1:0]
store_mult_hreg signed [IMAGE_SIZE+3-1:0]
store_mult_h0reg signed [IMAGE_SIZE+3-1:0]
ram_idle0reg
ram_idle1reg
zoom_sta_paramreg
ram_chreg [1:0]
zoom_num0reg [3+FRA_WIDTH-1:0]
wr_ram_donereg
wr_addr0reg [IMAGE_SIZE - 1:0]
wr_addr1reg [IMAGE_SIZE - 1:0]
wr_addr2reg [IMAGE_SIZE - 1:0]
wr_addr3reg [IMAGE_SIZE - 1:0]
rd_addrreg [IMAGE_SIZE - 1:0]
rd_addr0reg [IMAGE_SIZE - 1:0]
rd_addr1reg [IMAGE_SIZE - 1:0]
rd_addr2reg [IMAGE_SIZE - 1:0]
rd_addr3reg [IMAGE_SIZE - 1:0]
doutb0wire [15:0]
doutb0_0wire [15:0]
doutb1wire [15:0]
doutb1_0wire [15:0]
doutb2wire [15:0]
doutb2_0wire [15:0]
doutb3wire [15:0]
doutb3_0wire [15:0]
ram_stareg [3:0]
data_half_validreg
data_half_valid0reg
data_half_valid1reg
imag_addr_valid0reg
imag_addr_valid1reg
imag_addr0reg signed [IMAGE_SIZE+FRA_WIDTH-1:0]
mult_h1wire [IMAGE_SIZE-1:0]
mult_h2wire [IMAGE_SIZE+3-1:0]
store_addr_add_onewire [IMAGE_SIZE+3-1:0]
store_addrreg signed [IMAGE_SIZE+3-1:0]
mult_h0reg signed [IMAGE_SIZE+3-1:0]
zoom_sta_param0reg
zoom_sta_param1reg
addr_stareg [4:0]
data_half_en0reg
imag_addr1reg signed [IMAGE_SIZE-1:0]
add_imag_addr = IMAGE_H / 2wire [IMAGE_SIZE-1:0]
image_w0reg signed [IMAGE_SIZE+FRA_WIDTH+3-1:0]
image_w1reg signed [IMAGE_SIZE+FRA_WIDTH+3-1:0]
image_w2reg signed [IMAGE_SIZE+FRA_WIDTH+3-1:0]
image_h0reg signed [IMAGE_SIZE+FRA_WIDTH+3-1:0]
image_h1reg signed [IMAGE_SIZE+FRA_WIDTH+3-1:0]
image_h2reg signed [IMAGE_SIZE+FRA_WIDTH+3-1:0]
image_w2_unsignedwire [IMAGE_SIZE+FRA_WIDTH+3-1:0]
image_h2_unsignedwire [IMAGE_SIZE+FRA_WIDTH+3-1:0]
zoom_num1reg [IMAGE_SIZE+FRA_WIDTH+3-1:0]
add_image_wwire [IMAGE_SIZE+FRA_WIDTH+3-1:0]
add_image_hwire [IMAGE_SIZE+FRA_WIDTH+3-1:0]
ram_ch0reg [1:0]
ram_ch1reg [1:0]
ram_ch2reg [1:0]
rd_datareg [16*2-1:0]
rd_data0reg [16*2-1:0]
rd_data_0reg [16*2-1:0]
rd_data0_0reg [16*2-1:0]
image_w2_coereg [6:0]
image_w2_coe0reg [6:0]
image_w2_coe1reg [6:0]
image_w2_coe2reg [6:0]
image_w2_coe3reg [6:0]
image_h2_coereg [6:0]
image_h2_coe0reg [6:0]
image_h2_coe1reg [6:0]
image_h2_coe2reg [6:0]
coe0reg [7:0]
coe1reg [7:0]
coe2reg [7:0]
coe3reg [7:0]
coe0_0reg [7:0]
coe1_0reg [7:0]
coe2_0reg [7:0]
coe3_0reg [7:0]
image_valid[7:0]reg [2:0]
image_w_validreg [1:0]
image_h_validreg [1:0]
image_blank_validreg
coe_mult_p0wire [15:0]
coe_mult_p1wire [15:0]
coe_mult_p0_0wire [15:0]
coe_mult_p1_0wire [15:0]
mult_image0 [5:0]wire [14:0]
mult_image0_0[5:0]wire [14:0]
mult_image1 [2:0]reg [15:0]
mult_image2 [2:0]reg [15:0]
mult_image1_0[2:0]reg [15:0]
data_out0wire [15:0]
data_out1reg [15:0]
data_out_valid1reg
data_out2reg [15:0]
data_out_valid2reg
hdmi_out_en0reg
cnt_wwreg [IMAGE_SIZE-1:0]
cnt_hhreg [IMAGE_SIZE-1:0]
hdmi_out_en1reg
+

Constants

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
NameTypeValueDescription
IDLE7'b000_0001
JUDGE7'b000_0010
PARAM7'b000_0100
WAIT07'b000_1000
WAIT17'b001_0000
ZOOM7'b010_0000
BLANK7'b100_0000
FraWidthPower1 << FRA_WIDTH
MultDelay1

Processes

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Type: always

Instantiations

State machines

+ + + + + +state transitions + + +cluster_zoom_sta + +zoom_sta + + + + +IDLE + +IDLE + + + + +IDLE->IDLE + + +not (zoom_en)    + + + +JUDGE + +JUDGE + + + + +IDLE->JUDGE + + +zoom_en    + + + +JUDGE->JUDGE + + +not (judge_cnt_h_valid)    +not (fifo_full0)    +delay_cnt == MultDelay + 3    + + + +JUDGE->JUDGE + + +not (delay_cnt == MultDelay + 3)    + + + +PARAM + +PARAM + + + + +JUDGE->PARAM + + +judge_cnt_h_valid    +delay_cnt == MultDelay + 3    + + + +BLANK + +BLANK + + + + +JUDGE->BLANK + + +fifo_full0    +delay_cnt == MultDelay + 3    + + + +WAIT0 + +WAIT0 + + + + +PARAM->WAIT0 + + +not (ram_idle)    + + + +WAIT1 + +WAIT1 + + + + +PARAM->WAIT1 + + +ram_idle    + + + +WAIT0->PARAM + + +record_ram_valid    + + + +WAIT0->WAIT0 + + +not (record_ram_valid)    + + + +WAIT1->WAIT1 + + +not (record_ram_valid && fifo_full0)    + + + +ZOOM + +ZOOM + + + + +WAIT1->ZOOM + + +record_ram_valid && fifo_full0    + + + +ZOOM->IDLE + + +cnt_h == (IMAGE_H / 2 - 1)    +(cnt_w == (IMAGE_W / 2 - 1))    + + + +ZOOM->JUDGE + + +not (cnt_h == (IMAGE_H / 2 - 1))    +(cnt_w == (IMAGE_W / 2 - 1))    + + + +ZOOM->ZOOM + + +not ((cnt_w == (IMAGE_W / 2 - 1)))    + + + +BLANK->IDLE + + +cnt_h == (IMAGE_H / 2 - 1)    +(cnt_w == (IMAGE_W / 2) - 1)    + + + +BLANK->JUDGE + + +not (cnt_h == (IMAGE_H / 2 - 1))    +(cnt_w == (IMAGE_W / 2) - 1)    + + + +BLANK->BLANK + + +not ((cnt_w == (IMAGE_W / 2) - 1))    + + + +
+ + + + + +state transitions + + +cluster_ram_sta + +ram_sta + + + + +4'b0001 + +4'b0001 + + + + +4'b0001->4'b0001 + + +not (((wr_addr0 == IMAGE_W - 1) || (data_half_valid && (wr_addr0 == IMAGE_W / 2 - 1))) &&    +(data_in_valid0))    + + + +4'b0010 + +4'b0010 + + + + +4'b0001->4'b0010 + + +((wr_addr0 == IMAGE_W - 1) || (data_half_valid && (wr_addr0 == IMAGE_W / 2 - 1))) &&    +(data_in_valid0)    + + + +4'b0010->4'b0010 + + +not (((wr_addr1 == IMAGE_W - 1) || (data_half_valid && (wr_addr1 == IMAGE_W / 2 - 1))) &&    +(data_in_valid0))    + + + +4'b0100 + +4'b0100 + + + + +4'b0010->4'b0100 + + +((wr_addr1 == IMAGE_W - 1) || (data_half_valid && (wr_addr1 == IMAGE_W / 2 - 1))) &&    +(data_in_valid0)    + + + +4'b0100->4'b0100 + + +not (((wr_addr2 == IMAGE_W - 1) || (data_half_valid && (wr_addr2 == IMAGE_W / 2 - 1))) &&    +(data_in_valid0))    + + + +4'b1000 + +4'b1000 + + + + +4'b0100->4'b1000 + + +((wr_addr2 == IMAGE_W - 1) || (data_half_valid && (wr_addr2 == IMAGE_W / 2 - 1))) &&    +(data_in_valid0)    + + + +4'b1000->4'b0001 + + +((wr_addr3 == IMAGE_W - 1) || (data_half_valid && (wr_addr3 == IMAGE_W / 2 - 1))) &&    +(data_in_valid0)    + + + +4'b1000->4'b1000 + + +not (((wr_addr3 == IMAGE_W - 1) || (data_half_valid && (wr_addr3 == IMAGE_W / 2 - 1))) &&    +(data_in_valid0))    + + + +
+ + + + + +state transitions + + +cluster_addr_sta + +addr_sta + + + + +'d1 + +'d1 + + + + +'d1->'d1 + + +not ((mult_h2 < (IMAGE_H / 2) && (zoom_sta_param1)))    + + + +'d2 + +'d2 + + + + +'d1->'d2 + + +(mult_h2 < (IMAGE_H / 2) && (zoom_sta_param1))    + + + +'d2->'d1 + + +not ((mult_h2 != store_addr) | (~ram_idle))    + + + +'d4 + +'d4 + + + + +'d2->'d4 + + +(mult_h2 != store_addr) | (~ram_idle)    + + + +'d8 + +'d8 + + + + +'d4->'d8 + + +not (mult_h2 == (store_addr_add_one))    + + + +'d16 + +'d16 + + + + +'d4->'d16 + + +mult_h2 == (store_addr_add_one)    + + + +'d8->'d1 + + + + + + +'d16->'d1 + + +wr_ram_done    + + + +'d16->'d16 + + +not (wr_ram_done)    + + + +
+





+
+ + \ No newline at end of file diff --git a/project/compile/cmr.db b/project/compile/cmr.db index ddbe5f4..c2aad20 100644 --- a/project/compile/cmr.db +++ b/project/compile/cmr.db @@ -413,9 +413,9 @@ RAM(GB) - 0h:0m:25s - 0h:0m:25s - 0h:1m:10s + 0h:0m:26s + 0h:0m:26s + 0h:1m:13s 328 WINDOWS 10 x86_64 Intel(R) Core(TM) i7-9750H CPU @ 2.60GHz @@ -869,7 +869,7 @@ Verilog-0001: Analyzing file D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/ov5640.v - Verilog-0002: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/ov5640.v(line number: 23)] Analyzing module ov5640 (library work) + Verilog-0002: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/ov5640.v(line number: 3)] Analyzing module ov5640 (library work) Verilog-0001: Analyzing file D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/power_on_delay.v @@ -4817,7 +4817,7 @@ CLK_FREQ = 32'b00000111011100110101100101000000 - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 78)] Elaborating instance key_debounce_key_left + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 102)] Elaborating instance key_debounce_key_left Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/key_debounce.v(line number: 1)] Elaborating module key_debounce @@ -4829,7 +4829,7 @@ KEY_RELEASED_VALUE = 1'b1 - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 90)] Elaborating instance key_debounce_key_right + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 114)] Elaborating instance key_debounce_key_right Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/key_debounce.v(line number: 1)] Elaborating module key_debounce @@ -4841,7 +4841,7 @@ KEY_RELEASED_VALUE = 1'b1 - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 102)] Elaborating instance key_debounce_key_restore + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 126)] Elaborating instance key_debounce_key_restore Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/key_debounce.v(line number: 1)] Elaborating module key_debounce @@ -4853,7 +4853,7 @@ KEY_RELEASED_VALUE = 1'b1 - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 171)] Elaborating instance param_filiter1_mode + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 195)] Elaborating instance param_filiter1_mode Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_cell_unsigned_loop.v(line number: 1)] Elaborating module param_cell_unsigned_loop @@ -4892,7 +4892,7 @@ KEY_RELEASED_VALUE = 1'b1 - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 203)] Elaborating instance param_filiter2_mode + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 227)] Elaborating instance param_filiter2_mode Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_cell_unsigned_loop.v(line number: 1)] Elaborating module param_cell_unsigned_loop @@ -4907,7 +4907,7 @@ RANGE_MAX = 32'b00000000000000000000000000000100 - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 238)] Elaborating instance param_zoom + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 262)] Elaborating instance param_zoom Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_cell_unsigned.v(line number: 1)] Elaborating module param_cell_unsigned @@ -4946,7 +4946,7 @@ KEY_RELEASED_VALUE = 1'b1 - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 271)] Elaborating instance param_rotate + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 295)] Elaborating instance param_rotate Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_cell_unsigned_loop.v(line number: 1)] Elaborating module param_cell_unsigned_loop @@ -4985,7 +4985,7 @@ KEY_RELEASED_VALUE = 1'b1 - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 308)] Elaborating instance param_osd_startX + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 332)] Elaborating instance param_osd_startX Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_cell_unsigned.v(line number: 1)] Elaborating module param_cell_unsigned @@ -5024,7 +5024,7 @@ KEY_RELEASED_VALUE = 1'b1 - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 344)] Elaborating instance param_osd_startY + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 368)] Elaborating instance param_osd_startY Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_cell_unsigned.v(line number: 1)] Elaborating module param_cell_unsigned @@ -5063,7 +5063,7 @@ KEY_RELEASED_VALUE = 1'b1 - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 380)] Elaborating instance param_osd_char_width + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 404)] Elaborating instance param_osd_char_width Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_cell_unsigned.v(line number: 1)] Elaborating module param_cell_unsigned @@ -5102,7 +5102,7 @@ KEY_RELEASED_VALUE = 1'b1 - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 417)] Elaborating instance param_osd_char_height + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 441)] Elaborating instance param_osd_char_height Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_cell_unsigned.v(line number: 1)] Elaborating module param_cell_unsigned @@ -5141,7 +5141,7 @@ KEY_RELEASED_VALUE = 1'b1 - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 453)] Elaborating instance param_rotate_A + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 477)] Elaborating instance param_rotate_A Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_cell_unsigned.v(line number: 1)] Elaborating module param_cell_unsigned @@ -5156,7 +5156,7 @@ RANGE_MAX = 32'b00000000000000000000001111111111 - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 489)] Elaborating instance param_offsetX + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 513)] Elaborating instance param_offsetX Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_cell_signed.v(line number: 1)] Elaborating module param_cell_signed @@ -5195,7 +5195,7 @@ KEY_RELEASED_VALUE = 1'b1 - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 524)] Elaborating instance param_offsetY + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 548)] Elaborating instance param_offsetY Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_cell_signed.v(line number: 1)] Elaborating module param_cell_signed @@ -5234,7 +5234,7 @@ KEY_RELEASED_VALUE = 1'b1 - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 561)] Elaborating instance param_modify_H + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 585)] Elaborating instance param_modify_H Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_cell_signed_loop.v(line number: 1)] Elaborating module param_cell_signed_loop @@ -5273,7 +5273,7 @@ KEY_RELEASED_VALUE = 1'b1 - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 598)] Elaborating instance param_modify_S + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 622)] Elaborating instance param_modify_S Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_cell_signed.v(line number: 1)] Elaborating module param_cell_signed @@ -5312,7 +5312,7 @@ KEY_RELEASED_VALUE = 1'b1 - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 635)] Elaborating instance param_modify_V + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_manager.v(line number: 659)] Elaborating instance param_modify_V Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/others/param_cell_signed.v(line number: 1)] Elaborating module param_cell_signed @@ -5330,7 +5330,7 @@ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 507)] Elaborating instance u_ov5640 - Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/ov5640.v(line number: 23)] Elaborating module ov5640 + Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/ov5640.v(line number: 3)] Elaborating module ov5640 Module instance {multimedia_video_processor/u_ov5640} parameter value: @@ -5339,13 +5339,13 @@ IMAGE_H = 32'b00000000000000000000001011010000 - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/ov5640.v(line number: 62)] Elaborating instance power_on_delay_inst + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/ov5640.v(line number: 43)] Elaborating instance power_on_delay_inst Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/power_on_delay.v(line number: 22)] Elaborating module power_on_delay - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/ov5640.v(line number: 71)] Elaborating instance coms1_reg_config + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/ov5640.v(line number: 52)] Elaborating instance coms1_reg_config Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/reg_config.v(line number: 22)] Elaborating module reg_config @@ -5363,25 +5363,25 @@ Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/reg_config.v(line number: 69)] Elaborating instance U_CLKBUFG_CLK_20K - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/ov5640.v(line number: 83)] Elaborating instance coms2_reg_config + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/ov5640.v(line number: 64)] Elaborating instance coms2_reg_config Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/reg_config.v(line number: 22)] Elaborating module reg_config - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/ov5640.v(line number: 148)] Elaborating instance cmos1_8_16bit + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/ov5640.v(line number: 129)] Elaborating instance cmos1_8_16bit Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/cmos_8_16bit.v(line number: 24)] Elaborating module cmos_8_16bit - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/ov5640.v(line number: 161)] Elaborating instance cmos2_8_16bit + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/ov5640.v(line number: 142)] Elaborating instance cmos2_8_16bit Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/cmos_8_16bit.v(line number: 24)] Elaborating module cmos_8_16bit - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/ov5640.v(line number: 201)] Elaborating instance u_mix_image + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/ov5640.v(line number: 182)] Elaborating instance u_mix_image Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ov5640/mix_image.v(line number: 23)] Elaborating module mix_image @@ -6005,7 +6005,7 @@ TH = 32'b00000000000000000000000000000100 - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 637)] Elaborating instance u_rotate_image + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 638)] Elaborating instance u_rotate_image Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_image.v(line number: 23)] Elaborating module rotate_image @@ -6018,7 +6018,7 @@ IMAGE_H = 32'b00000000000000000000001011010000 - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_image.v(line number: 99)] Elaborating instance u_rotate_rom + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_image.v(line number: 102)] Elaborating instance u_rotate_rom Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/project/ipcore/rotate_rom/rotate_rom.v(line number: 16)] Elaborating module rotate_rom @@ -6109,7 +6109,7 @@ Verilog-2023: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/project/ipcore/rotate_rom/rtl/ipml_rom_v1_5_rotate_rom.v(line number: 69)] Give initial value 0 for the no drive pin wr_byte_en in module instance multimedia_video_processor/u_rotate_image/u_rotate_rom/U_ipml_rom_rotate_rom.U_ipml_spram_rotate_rom - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_image.v(line number: 110)] Elaborating instance u_rotate_mult_zoom0 + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_image.v(line number: 113)] Elaborating instance u_rotate_mult_zoom0 Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_mult0.v(line number: 23)] Elaborating module rotate_mult0 @@ -6120,7 +6120,7 @@ WIDT_B = 32'b00000000000000000000000000001011 - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_image.v(line number: 119)] Elaborating instance u_rotate_mult_zoom1 + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_image.v(line number: 122)] Elaborating instance u_rotate_mult_zoom1 Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_mult0.v(line number: 23)] Elaborating module rotate_mult0 @@ -6131,7 +6131,7 @@ WIDT_B = 32'b00000000000000000000000000001011 - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_image.v(line number: 187)] Elaborating instance u_rotate_mult0 + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_image.v(line number: 190)] Elaborating instance u_rotate_mult0 Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_mult0.v(line number: 23)] Elaborating module rotate_mult0 @@ -6142,7 +6142,7 @@ WIDT_B = 32'b00000000000000000000000000001101 - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_image.v(line number: 196)] Elaborating instance u_rotate_mult1 + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_image.v(line number: 199)] Elaborating instance u_rotate_mult1 Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_mult0.v(line number: 23)] Elaborating module rotate_mult0 @@ -6153,7 +6153,7 @@ WIDT_B = 32'b00000000000000000000000000001101 - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_image.v(line number: 205)] Elaborating instance u_rotate_mult2 + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_image.v(line number: 208)] Elaborating instance u_rotate_mult2 Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_mult0.v(line number: 23)] Elaborating module rotate_mult0 @@ -6164,7 +6164,7 @@ WIDT_B = 32'b00000000000000000000000000001101 - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_image.v(line number: 214)] Elaborating instance u_rotate_mult3 + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_image.v(line number: 217)] Elaborating instance u_rotate_mult3 Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_mult0.v(line number: 23)] Elaborating module rotate_mult0 @@ -6175,7 +6175,7 @@ WIDT_B = 32'b00000000000000000000000000001101 - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_image.v(line number: 318)] Elaborating instance u_store_addr + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_image.v(line number: 321)] Elaborating instance u_store_addr Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/project/ipcore/store_addr/store_addr.v(line number: 16)] Elaborating module store_addr @@ -6357,7 +6357,7 @@ c_ALMOST_EMPTY_NUM = 32'b00000000000000000000000000000100 - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_image.v(line number: 358)] Elaborating instance u_store_image_data + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/rotate/rotate_image.v(line number: 361)] Elaborating instance u_store_image_data Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/project/ipcore/store_image_data/store_image_data.v(line number: 16)] Elaborating module store_image_data @@ -6488,7 +6488,7 @@ Verilog-2039: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/project/ipcore/image_in_fifo/rtl/ipml_fifo_ctrl_v1_3.v(line number: 317)] Repeat multiplier in concatenation evaluates to 0 - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 685)] Elaborating instance u_zoom_image + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 687)] Elaborating instance u_zoom_image Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 23)] Elaborating module zoom_image_v1 @@ -6778,7 +6778,7 @@ Verilog-2019: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 434)] Width mismatch between port rd_addr and signal bound to it for instantiated module zoom_ram - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 756)] Elaborating instance mult_fra0 + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 751)] Elaborating instance mult_fra0 Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/mult_fra.v(line number: 23)] Elaborating module mult_fra0 @@ -6789,7 +6789,7 @@ WIDT_B = 32'b00000000000000000000000000001000 - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 762)] Elaborating instance mult_fra1 + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 757)] Elaborating instance mult_fra1 Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/mult_fra.v(line number: 23)] Elaborating module mult_fra0 @@ -6800,7 +6800,7 @@ WIDT_B = 32'b00000000000000000000000000001000 - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 768)] Elaborating instance mult_fra0_0 + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 763)] Elaborating instance mult_fra0_0 Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/mult_fra.v(line number: 23)] Elaborating module mult_fra0 @@ -6811,7 +6811,7 @@ WIDT_B = 32'b00000000000000000000000000001000 - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 774)] Elaborating instance mult_fra1_0 + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 769)] Elaborating instance mult_fra1_0 Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/mult_fra.v(line number: 23)] Elaborating module mult_fra0 @@ -6822,7 +6822,7 @@ WIDT_B = 32'b00000000000000000000000000001000 - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 784)] Elaborating instance mult_image_r0 + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 779)] Elaborating instance mult_image_r0 Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/mult_image.v(line number: 23)] Elaborating module mult_image_ip @@ -6833,7 +6833,7 @@ WIDT_B = 32'b00000000000000000000000000000110 - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 790)] Elaborating instance mult_image_r1 + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 785)] Elaborating instance mult_image_r1 Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/mult_image.v(line number: 23)] Elaborating module mult_image_ip @@ -6844,7 +6844,7 @@ WIDT_B = 32'b00000000000000000000000000000110 - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 796)] Elaborating instance mult_image_g0 + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 791)] Elaborating instance mult_image_g0 Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/mult_image.v(line number: 23)] Elaborating module mult_image_ip @@ -6855,7 +6855,7 @@ WIDT_B = 32'b00000000000000000000000000000110 - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 802)] Elaborating instance mult_image_g1 + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 797)] Elaborating instance mult_image_g1 Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/mult_image.v(line number: 23)] Elaborating module mult_image_ip @@ -6866,7 +6866,7 @@ WIDT_B = 32'b00000000000000000000000000000110 - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 808)] Elaborating instance mult_image_b0 + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 803)] Elaborating instance mult_image_b0 Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/mult_image.v(line number: 23)] Elaborating module mult_image_ip @@ -6877,7 +6877,7 @@ WIDT_B = 32'b00000000000000000000000000000110 - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 814)] Elaborating instance mult_image_b1 + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 809)] Elaborating instance mult_image_b1 Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/mult_image.v(line number: 23)] Elaborating module mult_image_ip @@ -6888,7 +6888,7 @@ WIDT_B = 32'b00000000000000000000000000000110 - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 821)] Elaborating instance mult_image_r0_0 + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 816)] Elaborating instance mult_image_r0_0 Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/mult_image.v(line number: 23)] Elaborating module mult_image_ip @@ -6899,7 +6899,7 @@ WIDT_B = 32'b00000000000000000000000000000110 - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 827)] Elaborating instance mult_image_r1_0 + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 822)] Elaborating instance mult_image_r1_0 Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/mult_image.v(line number: 23)] Elaborating module mult_image_ip @@ -6910,7 +6910,7 @@ WIDT_B = 32'b00000000000000000000000000000110 - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 833)] Elaborating instance mult_image_g0_0 + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 828)] Elaborating instance mult_image_g0_0 Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/mult_image.v(line number: 23)] Elaborating module mult_image_ip @@ -6921,7 +6921,7 @@ WIDT_B = 32'b00000000000000000000000000000110 - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 839)] Elaborating instance mult_image_g1_0 + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 834)] Elaborating instance mult_image_g1_0 Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/mult_image.v(line number: 23)] Elaborating module mult_image_ip @@ -6932,7 +6932,7 @@ WIDT_B = 32'b00000000000000000000000000000110 - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 845)] Elaborating instance mult_image_b0_0 + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 840)] Elaborating instance mult_image_b0_0 Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/mult_image.v(line number: 23)] Elaborating module mult_image_ip @@ -6943,7 +6943,7 @@ WIDT_B = 32'b00000000000000000000000000000110 - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 851)] Elaborating instance mult_image_b1_0 + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/zoom_image_v1.v(line number: 846)] Elaborating instance mult_image_b1_0 Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/zoom/mult_image.v(line number: 23)] Elaborating module mult_image_ip @@ -6954,7 +6954,7 @@ WIDT_B = 32'b00000000000000000000000000000110 - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 702)] Elaborating instance u_zoom_hdmi_fifo + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 704)] Elaborating instance u_zoom_hdmi_fifo Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/project/ipcore/zoom_hdmi_fifo/zoom_hdmi_fifo.v(line number: 16)] Elaborating module zoom_hdmi_fifo @@ -8768,10 +8768,10 @@ Verilog-2039: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/project/ipcore/image_in_fifo/rtl/ipml_fifo_ctrl_v1_3.v(line number: 196)] Repeat multiplier in concatenation evaluates to 0 - Verilog-2019: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 702)] Width mismatch between port wr_water_level and signal bound to it for instantiated module zoom_hdmi_fifo + Verilog-2019: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 704)] Width mismatch between port wr_water_level and signal bound to it for instantiated module zoom_hdmi_fifo - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 741)] Elaborating instance u_sync_vg + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 743)] Elaborating instance u_sync_vg Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/hdmi/hdmi_out/sync_vg.v(line number: 35)] Elaborating module sync_vg @@ -8794,10 +8794,10 @@ HV_OFFSET = 12'b000000000000 - Verilog-2019: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 730)] Width mismatch between port rd_mode and signal bound to it for instantiated module sync_vg + Verilog-2019: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 732)] Width mismatch between port rd_mode and signal bound to it for instantiated module sync_vg - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 779)] Elaborating instance udp_osd_inst + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 781)] Elaborating instance udp_osd_inst Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/udp_osd/udp_osd.v(line number: 3)] Elaborating module udp_osd @@ -9598,13 +9598,13 @@ Verilog-2036: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/udp_osd/udp_osd.v(line number: 123)] Net udp_tx_m_last connected to input port of module instance multimedia_video_processor/udp_osd_inst.eth_udp_inst has no driver, tie it to 0 - Verilog-2019: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 772)] Width mismatch between port cfg_end_posX and signal bound to it for instantiated module udp_osd + Verilog-2019: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 774)] Width mismatch between port cfg_end_posX and signal bound to it for instantiated module udp_osd - Verilog-2019: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 772)] Width mismatch between port cfg_end_posY and signal bound to it for instantiated module udp_osd + Verilog-2019: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 774)] Width mismatch between port cfg_end_posY and signal bound to it for instantiated module udp_osd - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 823)] Elaborating instance adjust_color_wrapper_inst + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 825)] Elaborating instance adjust_color_wrapper_inst Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/adjust_color/adjust_color_wrapper.v(line number: 1)] Elaborating module adjust_color_wrapper @@ -9978,7 +9978,7 @@ Verilog-2019: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/adjust_color/adjust_color_wrapper.v(line number: 29)] Width mismatch between port pixel_s_valid and signal bound to it for instantiated module adjust_color - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 854)] Elaborating instance u_ddr_addr_ctr + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 856)] Elaborating instance u_ddr_addr_ctr Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ddr/addr_ctrl/ddr_addr_ctr.v(line number: 1)] Elaborating module ddr_addr_ctr @@ -10333,19 +10333,19 @@ WIDTH = 32'b00000000000000000000000000000101 - Verilog-2019: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 847)] Width mismatch between port shift_h and signal bound to it for instantiated module ddr_addr_ctr + Verilog-2019: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 849)] Width mismatch between port shift_h and signal bound to it for instantiated module ddr_addr_ctr - Verilog-2019: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 847)] Width mismatch between port rd1_mode and signal bound to it for instantiated module ddr_addr_ctr + Verilog-2019: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 849)] Width mismatch between port rd1_mode and signal bound to it for instantiated module ddr_addr_ctr - Verilog-2019: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 847)] Width mismatch between port rd2_vs and signal bound to it for instantiated module ddr_addr_ctr + Verilog-2019: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 849)] Width mismatch between port rd2_vs and signal bound to it for instantiated module ddr_addr_ctr - Verilog-2019: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 847)] Width mismatch between port hdmi_out_mode and signal bound to it for instantiated module ddr_addr_ctr + Verilog-2019: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 849)] Width mismatch between port hdmi_out_mode and signal bound to it for instantiated module ddr_addr_ctr - Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 935)] Elaborating instance u_axi_ddr_top + Verilog-0004: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 937)] Elaborating instance u_axi_ddr_top Verilog-0003: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/ddr/rd_wr_ctrl/axi_ddr_top.v(line number: 7)] Elaborating module axi_ddr_top @@ -17279,16 +17279,16 @@ Verilog-2039: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/project/ipcore/image_in_fifo/rtl/ipml_fifo_ctrl_v1_3.v(line number: 196)] Repeat multiplier in concatenation evaluates to 0 - Verilog-2036: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 854)] Net sift_done connected to input port of module instance multimedia_video_processor.u_ddr_addr_ctr has no driver, tie it to 0 + Verilog-2036: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 856)] Net sift_done connected to input port of module instance multimedia_video_processor.u_ddr_addr_ctr has no driver, tie it to 0 - Verilog-2036: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 935)] Net wr2_data_in_valid connected to input port of module instance multimedia_video_processor.u_axi_ddr_top has no driver, tie it to 0 + Verilog-2036: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 937)] Net wr2_data_in_valid connected to input port of module instance multimedia_video_processor.u_axi_ddr_top has no driver, tie it to 0 - Verilog-2036: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 935)] Net wr2_data_in connected to input port of module instance multimedia_video_processor.u_axi_ddr_top has no driver, tie it to 0 + Verilog-2036: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 937)] Net wr2_data_in connected to input port of module instance multimedia_video_processor.u_axi_ddr_top has no driver, tie it to 0 - Verilog-2021: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 1000)] Net hdmi_out_en in multimedia_video_processor(original module multimedia_video_processor) does not have a driver, tie it to 0 + Verilog-2021: [D:/Project/FPGA_Project/Pango/multimedia_video_processor/sources/designs/multimedia_video_processor.v(line number: 1002)] Net hdmi_out_en in multimedia_video_processor(original module multimedia_video_processor) does not have a driver, tie it to 0 Loop was found during constant probe. @@ -20452,6 +20452,12 @@ Loop was found during constant probe. + + Loop was found during constant probe. + + + Loop was found during constant probe. + diff --git a/project/compile/formal.pvf b/project/compile/formal.pvf index 9460f4a..daacedb 100644 --- a/project/compile/formal.pvf +++ b/project/compile/formal.pvf @@ -3,7 +3,7 @@ #Application name: pds_shell.exe #OS: Windows 10 10.0.19045 #Hostname: OMEN-WSH -Generated by Fabric Compiler (version 2022.2-SP1-Lite build 132640) at Sat Nov 11 17:52:08 2023 +Generated by Fabric Compiler (version 2022.2-SP1-Lite build 132640) at Wed Nov 15 19:33:20 2023 # pvf -action compile pvf_reg_constant clk_cnt[31] 0 diff --git a/project/compile/multimedia_video_processor.cmr b/project/compile/multimedia_video_processor.cmr index a80d019..0e59223 100644 --- a/project/compile/multimedia_video_processor.cmr +++ b/project/compile/multimedia_video_processor.cmr @@ -1,4 +1,4 @@ -Generated by Fabric Compiler ( version 2022.2-SP1-Lite ) at Sat Nov 11 17:52:08 2023 +Generated by Fabric Compiler ( version 2022.2-SP1-Lite ) at Wed Nov 15 19:33:20 2023 Inputs and Outputs : @@ -112,6 +112,6 @@ Inputs and Outputs : Flow Command: compile -include_path {D:/Project/FPGA_Project/Pango/multimedia_video_processor/project} -top_module multimedia_video_processor Peak memory: 328 MB -Total CPU time to compile completion : 0h:0m:25s -Process Total CPU time to compile completion : 0h:0m:25s -Total real time to compile completion : 0h:1m:10s +Total CPU time to compile completion : 0h:0m:26s +Process Total CPU time to compile completion : 0h:0m:26s +Total real time to compile completion : 0h:1m:13s diff --git a/project/compile/multimedia_video_processor_comp.adf b/project/compile/multimedia_video_processor_comp.adf index 2055747..7226788 100644 Binary files a/project/compile/multimedia_video_processor_comp.adf and b/project/compile/multimedia_video_processor_comp.adf differ diff --git a/project/compile/parse_design/screen.pds b/project/compile/parse_design/screen.pds index e5c8238..891faff 100644 --- a/project/compile/parse_design/screen.pds +++ b/project/compile/parse_design/screen.pds @@ -1,5 +1,5 @@ (_flow fab_demo "2022.2-SP1-Lite" - (_comment "Generated by Fabric Compiler (version on 2022.2-SP1-Lite) at Sat Nov 11 17:52:15 2023") + (_comment "Generated by Fabric Compiler (version on 2022.2-SP1-Lite) at Wed Nov 15 19:33:28 2023") (_version "1.0.9") (_status "initial") (_project diff --git a/project/constraint_check/constraint_check.ccr b/project/constraint_check/constraint_check.ccr index f7d86a1..85dc965 100644 --- a/project/constraint_check/constraint_check.ccr +++ b/project/constraint_check/constraint_check.ccr @@ -1,4 +1,4 @@ -##### Written on 2023/11/11 17:52:59 ############################### +##### Written on 2023/11/15 19:34:13 ############################### ##### INFO ################################################## diff --git a/project/device_map/dmr.db b/project/device_map/dmr.db index 90d45cf..b40157c 100644 --- a/project/device_map/dmr.db +++ b/project/device_map/dmr.db @@ -2855,7 +2855,7 @@ u_sys_pll/u_pll_e3 clkbufg_1 ntclkbufg_1 - 2826 + 2824 CLKOUT1 @@ -2865,38 +2865,45 @@ 1757 - CLKOUT4 - u_sys_pll/u_pll_e3 + CLKOUT0 + U_HDMI_PLL/u_pll_e3 clkbufg_3 ntclkbufg_3 + 844 + + + CLKOUT4 + u_sys_pll/u_pll_e3 + clkbufg_4 + ntclkbufg_4 256 O hdmi_in_clk_ibuf - clkbufg_4 - ntclkbufg_4 + clkbufg_5 + ntclkbufg_5 173 O cmos1_pclk_ibuf - clkbufg_5 - ntclkbufg_5 + clkbufg_6 + ntclkbufg_6 126 O cmos2_pclk_ibuf - clkbufg_6 - ntclkbufg_6 + clkbufg_7 + ntclkbufg_7 126 CLKOUT3 u_sys_pll/u_pll_e3 - clkbufg_7 - ntclkbufg_7 + clkbufg_8 + ntclkbufg_8 26 @@ -2987,9 +2994,9 @@ 6 - u_ddr_addr_ctr/N73 - u_ddr_addr_ctr/N73_5 - 22 + u_ddr_addr_ctr/N76 + u_ddr_addr_ctr/N76_5 + 20 u_ddr_rst/N0 @@ -3022,8 +3029,8 @@ 6 - u_rotate_image/N316 - u_rotate_image/N316 + u_rotate_image/N365 + u_rotate_image/N365 16 @@ -3338,7 +3345,7 @@ udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[10:0]_or - udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[10:0]_or_7 + udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[10:0]_or_4 10 @@ -3406,7 +3413,7 @@ ntclkbufg_1 clkbufg_1 - 2826 + 2824 sync_vg_100m @@ -3444,9 +3451,9 @@ 989 - zoom_clk - u_sys_pll/u_pll_e3 - 851 + ntclkbufg_3 + clkbufg_3 + 844 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/calib_done @@ -3464,8 +3471,8 @@ 260 - ntclkbufg_3 - clkbufg_3 + ntclkbufg_4 + clkbufg_4 256 @@ -3475,8 +3482,8 @@ udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N319 - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N319_3 - 203 + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N319_2 + 201 zoom_rst @@ -3484,18 +3491,18 @@ 181 - ntclkbufg_4 - clkbufg_4 + ntclkbufg_5 + clkbufg_5 173 - image_filiter_inst2/pixel_valid - image_filiter_inst2/multiline_buffer_inst/m_pixel_valid + image_filiter_inst/pixel_valid + image_filiter_inst/multiline_buffer_inst/m_pixel_valid 149 - image_filiter_inst/pixel_valid - image_filiter_inst/multiline_buffer_inst/m_pixel_valid + image_filiter_inst2/pixel_valid + image_filiter_inst2/multiline_buffer_inst/m_pixel_valid 149 @@ -3504,25 +3511,25 @@ 131 - ntclkbufg_5 - clkbufg_5 + ntclkbufg_6 + clkbufg_6 126 - ntclkbufg_6 - clkbufg_6 + ntclkbufg_7 + clkbufg_7 126 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_start + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N466_4 + 123 + image_filiter_inst/multiline_buffer_inst/srst image_filiter_inst/multiline_buffer_inst/srst 120 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_start - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_5 - 114 - ms72xx_ctl/iic_dri_rx/N0_1 ms72xx_ctl/iic_dri_rx/N0_1 @@ -3574,13 +3581,13 @@ 71 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r [1] - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[1] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r [3] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[3] 69 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r [3] - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[3] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r [0] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[0] 69 @@ -3589,10 +3596,15 @@ 69 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r [0] - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[0] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r [1] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[1] 69 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calibration_d + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calibration_d + 65 + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1090 udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1090 @@ -3609,18 +3621,18 @@ 65 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calibration_d - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calibration_d - 65 + u_axi_ddr_top/switch_data0 [2] + u_axi_ddr_top/switch_data0[2] + 64 - u_zoom_image/ram_ch2 [1] - u_zoom_image/ram_ch2[1] + u_axi_ddr_top/switch_data0 [3] + u_axi_ddr_top/switch_data0[3] 64 - u_axi_ddr_top/switch_data0 [2] - u_axi_ddr_top/switch_data0[2] + u_zoom_image/ram_ch2 [0] + u_zoom_image/ram_ch2[0] 64 @@ -3629,59 +3641,44 @@ 64 - u_axi_ddr_top/switch_data0 [3] - u_axi_ddr_top/switch_data0[3] - 64 - - - u_zoom_image/ram_ch2 [0] - u_zoom_image/ram_ch2[0] + u_zoom_image/ram_ch2 [1] + u_zoom_image/ram_ch2[1] 64 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/gatecal_start u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/gatecal_start - 63 + 61 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24127 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23906 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_198_5 56 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N10 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N10 - 54 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N14 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N14 54 - udp_osd_inst/eth_udp_inst/gmii_rxd_valid - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_rxd_valid + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N10 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N10 54 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wr u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N252 - 53 + 52 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [17] - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[17] + udp_osd_inst/eth_udp_inst/gmii_rxd_valid + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_rxd_valid 52 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wr u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N216 - 52 - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [16] - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[16] - 50 + 51 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/rptr @@ -3694,48 +3691,43 @@ 49 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/gate_move_en - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/gate_move_en - 48 - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N96019 - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_56 + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N602 + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N602_3 48 - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N769 - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N769 + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N26342 + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_32 48 - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1125 - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1125 + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N817 + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N817_3 48 - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N973 - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N249_2 + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N639 + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N639 48 - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N26342 - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_32 + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1125 + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1125 48 - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N639 - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N639 + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N769 + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N769 48 - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N602 - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N602_3 + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N973 + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N455_10 48 - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N817 - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N817_3 + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N97586 + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_55 48 @@ -3743,6 +3735,11 @@ adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/valid_ff[2] 47 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/gate_move_en + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/gate_move_en + 47 + u_rotate_image/rotate_sta_reg [0] u_rotate_image/rotate_sta_reg[0] @@ -3753,16 +3750,6 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[15] 46 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [15] - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[15] - 46 - - - u_zoom_image/zoom_sta_reg [0] - u_zoom_image/zoom_sta_reg[0] - 45 - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/rdy_t [2] adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/rdy @@ -3774,14 +3761,9 @@ 45 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N119 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N119 - 44 - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [0] - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[0] - 44 + u_zoom_image/zoom_sta_reg [0] + u_zoom_image/zoom_sta_reg[0] + 45 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/init_start @@ -3789,8 +3771,8 @@ 44 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N126 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N126 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/rd_addr [0] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[0] 44 @@ -3799,34 +3781,29 @@ 44 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/rd_addr [0] - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[0] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [0] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[0] 44 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/rd_addr [0] - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[0] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N126 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N126 44 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [0] - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[0] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N119 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N119 44 - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/rdy_t [11] - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/rdy - 43 - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [1] - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1] - 43 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/rd_addr [0] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[0] + 44 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [2] - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[2] - 43 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [0] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[0] + 44 adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/rdy_t [3] @@ -3834,23 +3811,23 @@ 43 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [1] - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [1] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1] 43 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N104 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N104 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/rd_addr [2] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[2] 43 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/rd_addr [1] - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[1] + adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/rdy_t [11] + adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/rdy 43 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/rd_addr [2] - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[2] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [2] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[2] 43 @@ -3858,6 +3835,11 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[2] 43 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [1] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1] + 43 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/rd_addr [2] u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[2] @@ -3869,13 +3851,23 @@ 43 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N198 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N198 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/rd_addr [1] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[1] + 43 + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N104 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N104 + 43 + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N193 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N193 42 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N54 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N54_3 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N198 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N198 42 @@ -3884,9 +3876,14 @@ 42 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N193 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N193 - 42 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr [26] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[26] + 41 + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N54 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N54_3 + 41 u_zoom_image/data_in_valid0 @@ -3894,8 +3891,18 @@ 41 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/rd_addr [3] - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.raddr_msb + u_axi_ddr_top/rd_sta [0] + u_axi_ddr_top/rd_sta_reg[0] + 41 + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [3] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.waddr_msb + 41 + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_en_real + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/N1 41 @@ -3920,13 +3927,13 @@ FF - 13620 + 13618 64200 22 LUT - 13929 + 13927 42800 33 @@ -4010,9 +4017,9 @@ USCM - 13 + 14 30 - 44 + 47 HSST @@ -4062,10 +4069,10 @@ RAM(GB) - 0h:0m:28s - 0h:0m:30s - 0h:0m:30s - 557 + 0h:0m:31s + 0h:0m:32s + 0h:0m:33s + 556 WINDOWS 10 x86_64 Intel(R) Core(TM) i7-9750H CPU @ 2.60GHz 32 @@ -4713,25 +4720,28 @@ The instance clkbufg_2(GTP_CLKBUFG) has been inserted on the net nt_pix_clk in design, driver pin CLKOUT1(instance U_HDMI_PLL/u_pll_e3) -> load pin CLK(instance adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N11). - DeviceMap-2011: The net zoom_clk has both clock instance u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg(GTP_CLKBUFG) loader and other clock pin loader. + The instance clkbufg_3(GTP_CLKBUFG) has been inserted on the net zoom_clk in design, driver pin CLKOUT0(instance U_HDMI_PLL/u_pll_e3) -> load pin CLK(instance u_axi_ddr_top/u_axi_rd_connect/rd1_data_valid0). - The instance clkbufg_3(GTP_CLKBUFG) has been inserted on the net clk_10m in design, driver pin CLKOUT4(instance u_sys_pll/u_pll_e3) -> load pin CLK(instance ms72xx_ctl/iic_dri_rx/busy). + The instance clkbufg_4(GTP_CLKBUFG) has been inserted on the net clk_10m in design, driver pin CLKOUT4(instance u_sys_pll/u_pll_e3) -> load pin CLK(instance ms72xx_ctl/iic_dri_rx/busy). - The instance clkbufg_4(GTP_CLKBUFG) has been inserted on the net nt_hdmi_in_clk in design, driver pin O(instance hdmi_in_clk_ibuf) -> load pin CLK(instance u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull). + The instance clkbufg_5(GTP_CLKBUFG) has been inserted on the net nt_hdmi_in_clk in design, driver pin O(instance hdmi_in_clk_ibuf) -> load pin CLK(instance u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull). - The instance clkbufg_5(GTP_CLKBUFG) has been inserted on the net nt_cmos1_pclk in design, driver pin O(instance cmos1_pclk_ibuf) -> load pin CLK(instance u_ov5640/cmos1_8_16bit/de_cnt). + The instance clkbufg_6(GTP_CLKBUFG) has been inserted on the net nt_cmos1_pclk in design, driver pin O(instance cmos1_pclk_ibuf) -> load pin CLK(instance u_ov5640/cmos1_8_16bit/de_cnt). - The instance clkbufg_6(GTP_CLKBUFG) has been inserted on the net nt_cmos2_pclk in design, driver pin O(instance cmos2_pclk_ibuf) -> load pin CLK(instance u_ov5640/cmos2_8_16bit/de_cnt). + The instance clkbufg_7(GTP_CLKBUFG) has been inserted on the net nt_cmos2_pclk in design, driver pin O(instance cmos2_pclk_ibuf) -> load pin CLK(instance u_ov5640/cmos2_8_16bit/de_cnt). - The instance clkbufg_7(GTP_CLKBUFG) has been inserted on the net clk_25m in design, driver pin CLKOUT3(instance u_sys_pll/u_pll_e3) -> load pin CLK(instance u_ov5640/coms1_reg_config/clk_20k_regdiv). + The instance clkbufg_8(GTP_CLKBUFG) has been inserted on the net clk_25m in design, driver pin CLKOUT3(instance u_sys_pll/u_pll_e3) -> load pin CLK(instance u_ov5640/coms1_reg_config/clk_20k_regdiv). - DeviceMap-4006: Insert a inst clkgate_8(GTP_IOCLKBUF) before u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV(GTP_IOCLKDIV). + DeviceMap-2011: The net ddr_clk has both clock instance u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg(GTP_CLKBUFG) loader and other clock pin loader. + + + DeviceMap-4006: Insert a inst clkgate_9(GTP_IOCLKBUF) before u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV(GTP_IOCLKDIV). Infer CARRY group, base inst: N15_0_1/gateop, insts:13. @@ -4763,9 +4773,6 @@ Infer CARRY group, base inst: u_axi_ddr_top/N550_1.fsub_0/gateop, insts:9. - - Infer CARRY group, base inst: u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N2_1/gateop, insts:5. - Infer CARRY group, base inst: u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N9_1/gateop, insts:5. @@ -4788,19 +4795,16 @@ Infer CARRY group, base inst: u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N9_1/gateop, insts:6. - Infer CARRY group, base inst: u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N19.lt_0/gateop, insts:3. - - - Infer CARRY group, base inst: u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N24_1.fsub_1/gateop, insts:6. + Infer CARRY group, base inst: u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N16.eq_0/gateop, insts:3. - Infer CARRY group, base inst: u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N30.fsub_1/gateop, insts:6. + Infer CARRY group, base inst: u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N36.eq_0/gateop, insts:3. Infer CARRY group, base inst: u_axi_ddr_top/N866_6_0/gateop, insts:22. - Infer CARRY group, base inst: u_ddr_addr_ctr/N7_1_1/gateop, insts:21. + Infer CARRY group, base inst: u_ddr_addr_ctr/N7_1_1/gateop, insts:19. Infer CARRY group, base inst: u_rotate_image/N14_1.fsub_1/gateop, insts:11. @@ -4911,7 +4915,7 @@ Infer CARRY group, base inst: udp_wr_mem_inst/N17_1_0/gateop, insts:8. - Infer CARRY group, base inst: udp_wr_mem_inst/N30_1.fsub_0/gateop, insts:8. + Infer CARRY group, base inst: udp_wr_mem_inst/N30_1.fsub_1/gateop, insts:7. Infer CARRY group, base inst: image_filiter_inst/hybrid_filter_inst/N99.fsub_1/gateop, insts:5. @@ -4958,9 +4962,6 @@ Infer CARRY group, base inst: ms72xx_ctl/iic_dri_rx/N136.lt_0/gateop, insts:2. - - Infer CARRY group, base inst: u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N16.eq_0/gateop, insts:3. - Infer CARRY group, base inst: ms72xx_ctl/iic_dri_tx/N136.lt_0/gateop, insts:2. @@ -5522,9 +5523,6 @@ Infer CARRY group, base inst: u_ov5640/coms1_reg_config/u1/N36_1_1/gateop, insts:5. - - Infer CARRY group, base inst: u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N36.eq_0/gateop, insts:3. - Infer CARRY group, base inst: u_ov5640/coms2_reg_config/u1/N36_1_1/gateop, insts:5. @@ -5924,9 +5922,6 @@ Infer CARRY group, base inst: udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N185_1_1/gateop, insts:5. - - Infer CARRY group, base inst: u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N36.eq_0/gateop, insts:3. - Infer CARRY group, base inst: udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N168_1.fsub_1/gateop, insts:13. @@ -5987,6 +5982,9 @@ Infer CARRY group, base inst: udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_5_1/gateop, insts:32. + + Infer CARRY group, base inst: u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N2_1/gateop, insts:5. + Infer CARRY group, base inst: udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3870_1/gateop, insts:32. @@ -6552,10 +6550,10 @@ Infer CARRY group, base inst: udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N170.eq_0/gateop, insts:6. - Infer CARRY group, base inst: u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N81_1_0/gateop, insts:6. + Infer CARRY group, base inst: u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N81_1_1/gateop, insts:5. - Infer CARRY group, base inst: u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N389_8.fsub_1/gateop, insts:5. + Infer CARRY group, base inst: u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N389_8.fsub_0/gateop, insts:6. Infer CARRY group, base inst: u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N81_1_0/gateop, insts:6. @@ -6590,6 +6588,18 @@ Infer CARRY group, base inst: u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N9_1/gateop, insts:5. + + Infer CARRY group, base inst: u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N19.lt_0/gateop, insts:3. + + + Infer CARRY group, base inst: u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N24_1.fsub_1/gateop, insts:6. + + + Infer CARRY group, base inst: u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N30.fsub_1/gateop, insts:6. + + + Infer CARRY group, base inst: u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N36.eq_0/gateop, insts:3. + Infer CARRY group, base inst: u_rotate_image/u_rotate_mult1/N2/gopapm, insts:2. diff --git a/project/device_map/formal.pvf b/project/device_map/formal.pvf index bb320b5..a48e8e3 100644 --- a/project/device_map/formal.pvf +++ b/project/device_map/formal.pvf @@ -3,6 +3,54 @@ #Application name: pds_shell.exe #OS: Windows 10 10.0.19045 #Hostname: OMEN-WSH +Generated by Fabric Compiler (version 2022.2-SP1-Lite build 132640) at Wed Nov 15 19:36:29 2023 +#Build: Fabric Compiler 2022.2-SP1-Lite, Build 132640, Aug 18 15:12 2023 +#Install: D:\Program_Files\PDS_2022.2-SP1-Lite\bin +#Application name: pds_shell.exe +#OS: Windows 10 10.0.19045 +#Hostname: OMEN-WSH +Generated by Fabric Compiler (version 2022.2-SP1-Lite build 132640) at Wed Nov 15 19:22:37 2023 +#Build: Fabric Compiler 2022.2-SP1-Lite, Build 132640, Aug 18 15:12 2023 +#Install: D:\Program_Files\PDS_2022.2-SP1-Lite\bin +#Application name: pds_shell.exe +#OS: Windows 10 10.0.19045 +#Hostname: OMEN-WSH +Generated by Fabric Compiler (version 2022.2-SP1-Lite build 132640) at Wed Nov 15 15:07:18 2023 +#Build: Fabric Compiler 2022.2-SP1-Lite, Build 132640, Aug 18 15:12 2023 +#Install: D:\Program_Files\PDS_2022.2-SP1-Lite\bin +#Application name: pds_shell.exe +#OS: Windows 10 10.0.19045 +#Hostname: OMEN-WSH +Generated by Fabric Compiler (version 2022.2-SP1-Lite build 132640) at Wed Nov 15 14:37:15 2023 +#Build: Fabric Compiler 2022.2-SP1-Lite, Build 132640, Aug 18 15:12 2023 +#Install: D:\Program_Files\PDS_2022.2-SP1-Lite\bin +#Application name: pds_shell.exe +#OS: Windows 10 10.0.19045 +#Hostname: OMEN-WSH +Generated by Fabric Compiler (version 2022.2-SP1-Lite build 132640) at Wed Nov 15 14:19:21 2023 +#Build: Fabric Compiler 2022.2-SP1-Lite, Build 132640, Aug 18 15:12 2023 +#Install: D:\Program_Files\PDS_2022.2-SP1-Lite\bin +#Application name: pds_shell.exe +#OS: Windows 10 10.0.19045 +#Hostname: OMEN-WSH +Generated by Fabric Compiler (version 2022.2-SP1-Lite build 132640) at Wed Nov 15 14:07:38 2023 +#Build: Fabric Compiler 2022.2-SP1-Lite, Build 132640, Aug 18 15:12 2023 +#Install: D:\Program_Files\PDS_2022.2-SP1-Lite\bin +#Application name: pds_shell.exe +#OS: Windows 10 10.0.19045 +#Hostname: OMEN-WSH +Generated by Fabric Compiler (version 2022.2-SP1-Lite build 132640) at Wed Nov 15 13:48:28 2023 +#Build: Fabric Compiler 2022.2-SP1-Lite, Build 132640, Aug 18 15:12 2023 +#Install: D:\Program_Files\PDS_2022.2-SP1-Lite\bin +#Application name: pds_shell.exe +#OS: Windows 10 10.0.19045 +#Hostname: OMEN-WSH +Generated by Fabric Compiler (version 2022.2-SP1-Lite build 132640) at Wed Nov 15 10:39:06 2023 +#Build: Fabric Compiler 2022.2-SP1-Lite, Build 132640, Aug 18 15:12 2023 +#Install: D:\Program_Files\PDS_2022.2-SP1-Lite\bin +#Application name: pds_shell.exe +#OS: Windows 10 10.0.19045 +#Hostname: OMEN-WSH Generated by Fabric Compiler (version 2022.2-SP1-Lite build 132640) at Sat Nov 11 17:55:12 2023 #Build: Fabric Compiler 2022.2-SP1-Lite, Build 132640, Aug 18 15:12 2023 #Install: D:\Program_Files\PDS_2022.2-SP1-Lite\bin diff --git a/project/device_map/multimedia_video_processor.dmr b/project/device_map/multimedia_video_processor.dmr index 8d742e2..babb69d 100644 --- a/project/device_map/multimedia_video_processor.dmr +++ b/project/device_map/multimedia_video_processor.dmr @@ -1,4 +1,4 @@ -Generated by Fabric Compiler ( version 2022.2-SP1-Lite ) at Sat Nov 11 17:55:11 2023 +Generated by Fabric Compiler ( version 2022.2-SP1-Lite ) at Wed Nov 15 19:36:27 2023 Timing Constraint: ------------------------------------------------------- @@ -569,13 +569,14 @@ Clock Signal: | Q | u_ov5640/coms2_reg_config/clk_20k_regdiv | u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K | u_ov5640/coms2_reg_config/clock_20k | 25 | CLKOUT | udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay | udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT | gmii_clk | 1988 | CLKDIVOUT | u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV | clkbufg_0 | ntclkbufg_0 | 5817 -| CLKOUT0 | u_sys_pll/u_pll_e3 | clkbufg_1 | ntclkbufg_1 | 2826 +| CLKOUT0 | u_sys_pll/u_pll_e3 | clkbufg_1 | ntclkbufg_1 | 2824 | CLKOUT1 | U_HDMI_PLL/u_pll_e3 | clkbufg_2 | ntclkbufg_2 | 1757 -| CLKOUT4 | u_sys_pll/u_pll_e3 | clkbufg_3 | ntclkbufg_3 | 256 -| O | hdmi_in_clk_ibuf | clkbufg_4 | ntclkbufg_4 | 173 -| O | cmos1_pclk_ibuf | clkbufg_5 | ntclkbufg_5 | 126 -| O | cmos2_pclk_ibuf | clkbufg_6 | ntclkbufg_6 | 126 -| CLKOUT3 | u_sys_pll/u_pll_e3 | clkbufg_7 | ntclkbufg_7 | 26 +| CLKOUT0 | U_HDMI_PLL/u_pll_e3 | clkbufg_3 | ntclkbufg_3 | 844 +| CLKOUT4 | u_sys_pll/u_pll_e3 | clkbufg_4 | ntclkbufg_4 | 256 +| O | hdmi_in_clk_ibuf | clkbufg_5 | ntclkbufg_5 | 173 +| O | cmos1_pclk_ibuf | clkbufg_6 | ntclkbufg_6 | 126 +| O | cmos2_pclk_ibuf | clkbufg_7 | ntclkbufg_7 | 126 +| CLKOUT3 | u_sys_pll/u_pll_e3 | clkbufg_8 | ntclkbufg_8 | 26 +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -599,14 +600,14 @@ Reset Signal: | u_axi_ddr_top/N878 | u_axi_ddr_top/N878 | 16 | u_axi_ddr_top/N889 | u_axi_ddr_top/N889 | 16 | u_axi_rst/N0 | u_axi_rst/N0 | 6 -| u_ddr_addr_ctr/N73 | u_ddr_addr_ctr/N73_5 | 22 +| u_ddr_addr_ctr/N76 | u_ddr_addr_ctr/N76_5 | 20 | u_ddr_rst/N0 | u_ddr_rst/N0 | 3 | u_hdm_in_rst/N0 | u_hdm_in_rst/N0 | 3 | u_hdmi_in_top/N55 | u_hdmi_in_top/N55 | 2 | wr1_rst | u_hdm_in_rst/rst | 5 | u_hdmi_in_top/vs_in1 | u_hdmi_in_top/vs_in1 | 2 | u_hdmi_rst/N0 | u_hdmi_rst/N0 | 6 -| u_rotate_image/N316 | u_rotate_image/N316 | 16 +| u_rotate_image/N365 | u_rotate_image/N365 | 16 | u_sync_vg/h_count[11:0]_or | u_sync_vg/h_count[11:0]_or | 12 | u_sync_vg/pixel_show_en1 | u_sync_vg/pixel_show_en1 | 16 | u_zoom_image/zoom_sta_reg [0] | u_zoom_image/zoom_sta_reg[0] | 8 @@ -669,7 +670,7 @@ Reset Signal: | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_rst | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_dll_rst_sync/sig_async_r2[0] | 1 | u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_pll_rst | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_rst | 2 | udp_osd_inst/char_osd_inst/char_buf_reader_inst/N861 | udp_osd_inst/char_osd_inst/char_buf_reader_inst/N861 | 11 -| udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[10:0]_or | udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[10:0]_or_7 | 10 +| udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[10:0]_or | udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[10:0]_or_4 | 10 | udp_osd_inst/char_osd_inst/char_next | udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2 | 6 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/N0 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/N0 | 2275 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/N0 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/N0 | 22 @@ -702,7 +703,7 @@ CE Signal: | u_axi_ddr_top/N867 | u_axi_ddr_top/N867 | 25 | u_axi_ddr_top/N855 | u_axi_ddr_top/N855_inv | 5 | u_hdmi_in_top/N3 | u_hdmi_in_top/N3 | 2 -| u_rotate_image/N302 | u_rotate_image/N302 | 13 +| u_rotate_image/N350 | u_rotate_image/N350 | 13 | N139_0 | N139_0 | 15 | u_rotate_image/rotate_sta_reg [0] | u_rotate_image/rotate_sta_reg[0] | 32 | u_sync_vg/N145 | u_sync_vg/N145_5 | 11 @@ -750,7 +751,7 @@ CE Signal: | udp_wr_mem_inst/N723 | udp_wr_mem_inst/N723 | 16 | camera_valid | u_ov5640/u_mix_image/data_out_valid1 | 11 | image_filiter_inst/multiline_buffer_inst/N272 | image_filiter_inst/multiline_buffer_inst/N272 | 6 -| image_filiter_inst/multiline_buffer_inst/N21 | image_filiter_inst/multiline_buffer_inst/N176_3 | 9 +| image_filiter_inst/multiline_buffer_inst/N21 | image_filiter_inst/multiline_buffer_inst/N236_3 | 9 | image_filiter_inst/pixel_valid | image_filiter_inst/multiline_buffer_inst/m_pixel_valid | 144 | temp_v | image_filiter_inst/hybrid_filter_inst/m_result_valid | 11 | image_filiter_inst2/multiline_buffer_inst/N272 | image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[10:0]_or_1 | 6 @@ -784,9 +785,9 @@ CE Signal: | param_manager_inst/param_filiter1_mode/N116 | param_manager_inst/param_filiter1_mode/N116 | 72 | param_manager_inst/param_filiter1_mode/N153 | param_manager_inst/param_filiter1_mode/N153 | 3 | param_manager_inst/param_filiter2_mode/N153 | param_manager_inst/param_filiter2_mode/N153 | 3 -| param_manager_inst/param_modify_H/N150 | param_manager_inst/param_modify_H/N150_1 | 9 -| param_manager_inst/param_modify_S/N150 | param_manager_inst/param_modify_S/N150_1 | 9 -| param_manager_inst/param_modify_V/N150 | param_manager_inst/param_modify_V/N150_1 | 9 +| param_manager_inst/param_modify_H/N150 | param_manager_inst/param_modify_H/N150_3 | 9 +| param_manager_inst/param_modify_S/N150 | param_manager_inst/param_modify_S/N150_3 | 9 +| param_manager_inst/param_modify_V/N150 | param_manager_inst/param_modify_V/N150_3 | 9 | param_manager_inst/param_offsetX/N150 | param_manager_inst/param_offsetX/N150_1 | 12 | param_manager_inst/param_offsetY/N150 | param_manager_inst/param_offsetY/N150_1 | 12 | param_manager_inst/param_osd_char_height/N148 | param_manager_inst/param_osd_char_height/N148_4 | 11 @@ -863,7 +864,7 @@ CE Signal: | udp_osd_inst/char_osd_inst/char_buf_reader_inst/N711 | udp_osd_inst/char_osd_inst/char_buf_reader_inst/N711_2 | 11 | udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786 | udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786 | 6 | udp_osd_inst/char_osd_inst/char_buf_reader_inst/N848 | udp_osd_inst/char_osd_inst/char_buf_reader_inst/N848 | 11 -| udp_osd_inst/char_osd_inst/char_buf_reader_inst/N873 | udp_osd_inst/char_osd_inst/char_buf_reader_inst/N873_1 | 5 +| udp_osd_inst/char_osd_inst/char_buf_reader_inst/N873 | udp_osd_inst/char_osd_inst/char_buf_reader_inst/N873_3 | 5 | udp_osd_inst/char_osd_inst/char_buf_reader_inst/N862 | udp_osd_inst/char_osd_inst/char_buf_reader_inst/N862 | 11 | udp_osd_inst/char_osd_inst/char_buf_reader_inst/N858 | udp_osd_inst/char_osd_inst/char_buf_reader_inst/N883_2 | 8 | udp_osd_inst/char_osd_inst/char_buf_reader_inst/N883 | udp_osd_inst/char_osd_inst/char_buf_reader_inst/N883_6 | 8 @@ -882,8 +883,8 @@ CE Signal: | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N457 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N457_1 | 15 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N532 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N532_1 | 15 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N240 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N240_5 | 8 -| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N219 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N219 | 9 -| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_done | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[7:0]_3 | 3 +| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N219 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N219_2 | 9 +| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_done | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N12_4 | 3 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N1814 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N1814 | 8 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/N18 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/N18 | 3 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N2053 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N2053 | 14 @@ -918,19 +919,19 @@ CE Signal: | u_rotate_image/N164_1 | u_rotate_image/N164_1 | 12 | u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N0_1 | u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N0_1 | 12 | u_rotate_image/addr_fifo_rd_en | u_rotate_image/N181_1 | 1 -| u_rotate_image/N339_2 | u_rotate_image/N169_1 | 11 +| u_rotate_image/N395_2 | u_rotate_image/N169_1 | 11 | u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N0_1 | u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N0_1 | 11 | u_rotate_image/N170 | u_rotate_image/N170_5 | 1 -| udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N319 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N319_3 | 81 +| udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N319 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N319_2 | 81 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N563 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N563_4 | 5 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N706 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N706 | 32 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N639 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N639 | 48 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N1057 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N1057_5 | 8 -| udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N866 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N866_5 | 8 +| udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N866 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N866_2 | 8 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N847 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N847 | 8 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N834 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N834 | 32 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N769 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N769 | 48 -| udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N932 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N291_8 | 2 +| udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N932 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N291_16 | 2 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N832 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N832 | 80 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N765 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N289_1 | 6 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N781 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N781_1 | 5 @@ -944,9 +945,9 @@ CE Signal: | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1170 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1170 | 16 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1057 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1057_3 | 8 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N943 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N943 | 8 -| udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N963 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N438_1_or[0]_8 | 24 +| udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N963 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N943_1 | 24 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1082 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1082 | 8 -| udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1269 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N518_1 | 8 +| udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1269 | udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N310_1_or[0]_9 | 8 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1014 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1014 | 8 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N956 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N956 | 8 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N905 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N905 | 4 @@ -961,7 +962,7 @@ CE Signal: | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1094 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1094_3 | 16 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1125 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1125 | 48 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1036 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1036_9_5 | 8 -| udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N973 | udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N249_2 | 48 +| udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N973 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N455_10 | 48 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N969 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1066_4 | 16 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1731 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1731 | 16 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N2622 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N2622_2 | 32 @@ -972,14 +973,14 @@ CE Signal: | udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N588 | udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N588_4 | 5 | udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N748 | udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N748 | 16 | udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N757 | udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N757 | 24 -| udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N665 | udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N665_6 | 24 +| udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N665 | udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N665_7 | 24 | udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N602 | udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N602_3 | 48 | udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N859 | udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N859_3 | 8 | udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839 | udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839 | 16 -| udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N697 | udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N697_2 | 8 +| udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N697 | udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N697_5 | 8 | udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N630 | udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N630_3 | 8 -| udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N878 | udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N878_2 | 8 -| udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N710 | udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N710_3 | 8 +| udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N878 | udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N878_4 | 8 +| udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N710 | udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N710_4 | 8 | N64_0 | N64_0 | 2 | image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N9_1 | image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N9_1 | 12 | image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N0_1 | image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N0_1 | 12 @@ -998,7 +999,7 @@ CE Signal: | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N752 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N752_10 | 18 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N685 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N685 | 18 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg [2] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[2] | 3 -| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43 | 19 +| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43_3 | 19 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N281 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N281 | 22 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N317 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N317 | 15 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N252 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N252 | 2 @@ -1024,9 +1025,9 @@ CE Signal: | u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N9_1 | u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N9_1 | 11 | u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N0_1 | u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N0_1 | 11 | u_axi_ddr_top/u_axi_rd_connect/rid_en | u_axi_ddr_top/u_axi_rd_connect/rd_sta_reg[1] | 1 -| N241_0 | N241_0 | 12 +| N242_0 | N242_0 | 12 | u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N0_1 | u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N0_1 | 10 -| u_axi_ddr_top/u_axi_rd_connect/N78_1_rnmt | N245_0 | 14 +| u_axi_ddr_top/u_axi_rd_connect/N78_1_rnmt | N246_0 | 14 | u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N0_1 | u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N0_1 | 10 | u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N0_1 | u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N0_1 | 10 | u_axi_ddr_top/u_axi_rd_connect/rd_ddr_en | u_axi_ddr_top/u_axi_rd_connect/rd_sta_reg[2] | 8 @@ -1056,7 +1057,7 @@ CE Signal: | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N359 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N359 | 5 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N377 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N377 | 8 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N439 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N439 | 8 -| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N449 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_4 | 6 +| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N449 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_377 | 6 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N466 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N466 | 4 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N136 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N136_7 | 8 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N456 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N456 | 13 @@ -1068,9 +1069,9 @@ CE Signal: | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N359 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N359 | 5 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N377 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N377 | 8 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N439 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N439 | 8 -| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N449 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_313 | 6 +| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N449 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_4 | 6 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N466 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N466 | 4 -| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N136 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N136_4 | 8 +| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N136 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N136_7 | 8 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N598 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_6 | 10 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N607 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N607 | 8 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N610 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N610 | 8 @@ -1079,7 +1080,7 @@ CE Signal: | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N359 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N359 | 5 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N377 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N377 | 8 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N439 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N439 | 8 -| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N449 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_378 | 6 +| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N449 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_4 | 6 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N466 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N466 | 4 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N136 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N136_4 | 8 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N598 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_6 | 10 @@ -1090,7 +1091,7 @@ CE Signal: | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N359 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N359 | 5 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N377 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N377 | 8 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N439 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N439 | 8 -| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N449 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_10 | 6 +| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N449 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_378 | 6 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N466 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N466 | 4 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N136 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N136_4 | 8 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N598 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_6 | 10 @@ -1107,7 +1108,7 @@ CE Signal: | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N327 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N327 | 6 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/gate_check | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gate_check | 6 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/gatecal_start | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/gatecal_start | 12 -| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N139 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N139 | 6 +| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N431 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N431_1 | 6 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N538 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N538_5 | 3 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N327 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N327 | 6 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/gate_check | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gate_check | 6 @@ -1120,9 +1121,9 @@ CE Signal: | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N327 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N327 | 6 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/gate_check | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gate_check | 6 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N139 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N139 | 6 -| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/N19 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/N19_3 | 4 +| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/N19 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/N19_5 | 4 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[1].mcdq_tfaw/N19 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[1].mcdq_tfaw/N19_3 | 4 -| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/N19 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/N19_3 | 4 +| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/N19 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/N19_5 | 4 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N7_1 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N7_1 | 5 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/N0_1 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/N0_1 | 5 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N7_1 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N7_1 | 5 @@ -1139,7 +1140,7 @@ Other High Fanout Signal: | Net_Name | Driver | Fanout +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | ntclkbufg_0 | clkbufg_0 | 5817 -| ntclkbufg_1 | clkbufg_1 | 2826 +| ntclkbufg_1 | clkbufg_1 | 2824 | sync_vg_100m | sync_vg_100m | 2548 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/N0 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/N0 | 2275 | gmii_clk | udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT | 1988 @@ -1147,22 +1148,22 @@ Other High Fanout Signal: | ntclkbufg_2 | clkbufg_2 | 1757 | rd3_rst | u_clk50m_rst/rst | 1674 | u_axi_ddr_top/rst | u_axi_ddr_top/rst0 | 989 -| zoom_clk | u_sys_pll/u_pll_e3 | 851 +| ntclkbufg_3 | clkbufg_3 | 844 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/calib_done | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/calib_done | 575 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/data_out [0] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/data_out[0] | 261 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/data_out [1] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/data_out[1] | 260 -| ntclkbufg_3 | clkbufg_3 | 256 +| ntclkbufg_4 | clkbufg_4 | 256 | rd2_rst | u_hdmi_rst/rst | 219 -| udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N319 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N319_3 | 203 +| udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N319 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N319_2 | 201 | zoom_rst | u_zoom_rst/rst | 181 -| ntclkbufg_4 | clkbufg_4 | 173 -| image_filiter_inst2/pixel_valid | image_filiter_inst2/multiline_buffer_inst/m_pixel_valid | 149 +| ntclkbufg_5 | clkbufg_5 | 173 | image_filiter_inst/pixel_valid | image_filiter_inst/multiline_buffer_inst/m_pixel_valid | 149 +| image_filiter_inst2/pixel_valid | image_filiter_inst2/multiline_buffer_inst/m_pixel_valid | 149 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_wvld_m | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_wvld_m | 131 -| ntclkbufg_5 | clkbufg_5 | 126 | ntclkbufg_6 | clkbufg_6 | 126 +| ntclkbufg_7 | clkbufg_7 | 126 +| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_start | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N466_4 | 123 | image_filiter_inst/multiline_buffer_inst/srst | image_filiter_inst/multiline_buffer_inst/srst | 120 -| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_start | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_5 | 114 | ms72xx_ctl/iic_dri_rx/N0_1 | ms72xx_ctl/iic_dri_rx/N0_1 | 110 | u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_dqs_rst | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_dqs_rst | 106 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_act | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N208 | 104 @@ -1173,71 +1174,71 @@ Other High Fanout Signal: | u_ov5640/coms1_reg_config/N4 | u_ov5640/coms1_reg_config/N4 | 72 | param_manager_inst/param_filiter1_mode/N116 | param_manager_inst/param_filiter1_mode/N116 | 72 | u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin | u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg | 71 -| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r [1] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[1] | 69 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r [3] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[3] | 69 -| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r [2] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[2] | 69 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r [0] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[0] | 69 +| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r [2] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[2] | 69 +| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r [1] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[1] | 69 +| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calibration_d | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calibration_d | 65 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1090 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1090 | 65 | u_axi_ddr_top/u_axi_wr_connect/N235 | u_axi_ddr_top/u_axi_wr_connect/N235_3 | 65 | u_axi_ddr_top/u_axi_wr_connect/N471 | u_axi_ddr_top/u_axi_wr_connect/N471_4 | 65 -| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calibration_d | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calibration_d | 65 -| u_zoom_image/ram_ch2 [1] | u_zoom_image/ram_ch2[1] | 64 | u_axi_ddr_top/switch_data0 [2] | u_axi_ddr_top/switch_data0[2] | 64 -| u_axi_ddr_top/u_axi_wr_connect/N473 | u_axi_ddr_top/u_axi_wr_connect/N473_3 | 64 | u_axi_ddr_top/switch_data0 [3] | u_axi_ddr_top/switch_data0[3] | 64 | u_zoom_image/ram_ch2 [0] | u_zoom_image/ram_ch2[0] | 64 -| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/gatecal_start | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/gatecal_start | 63 -| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24127 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_198_5 | 56 -| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N10 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N10 | 54 +| u_axi_ddr_top/u_axi_wr_connect/N473 | u_axi_ddr_top/u_axi_wr_connect/N473_3 | 64 +| u_zoom_image/ram_ch2 [1] | u_zoom_image/ram_ch2[1] | 64 +| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/gatecal_start | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/gatecal_start | 61 +| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23906 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_198_5 | 56 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N14 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N14 | 54 -| udp_osd_inst/eth_udp_inst/gmii_rxd_valid | udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_rxd_valid | 54 -| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wr | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N252 | 53 -| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [17] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[17] | 52 -| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wr | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N216 | 52 -| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [16] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[16] | 50 +| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N10 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N10 | 54 +| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wr | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N252 | 52 +| udp_osd_inst/eth_udp_inst/gmii_rxd_valid | udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_rxd_valid | 52 +| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wr | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N216 | 51 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/rptr | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/rptr | 49 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N958 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N958_2 | 49 -| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/gate_move_en | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/gate_move_en | 48 -| udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N96019 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_56 | 48 -| udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N769 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N769 | 48 -| udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1125 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1125 | 48 -| udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N973 | udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N249_2 | 48 -| udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N26342 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_32 | 48 -| udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N639 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N639 | 48 | udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N602 | udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N602_3 | 48 +| udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N26342 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_32 | 48 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N817 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N817_3 | 48 +| udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N639 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N639 | 48 +| udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1125 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1125 | 48 +| udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N769 | udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N769 | 48 +| udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N973 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N455_10 | 48 +| udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N97586 | udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_55 | 48 | adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/valid_ff [2] | adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/valid_ff[2] | 47 +| u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/gate_move_en | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/gate_move_en | 47 | u_rotate_image/rotate_sta_reg [0] | u_rotate_image/rotate_sta_reg[0] | 46 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/phy_addr [15] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[15] | 46 -| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [15] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[15] | 46 -| u_zoom_image/zoom_sta_reg [0] | u_zoom_image/zoom_sta_reg[0] | 45 | adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/rdy_t [2] | adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/rdy | 45 | adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/rdy_t [12] | adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/rdy | 45 -| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N119 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N119 | 44 -| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [0] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[0] | 44 +| u_zoom_image/zoom_sta_reg [0] | u_zoom_image/zoom_sta_reg[0] | 45 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/init_start | u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/init_start | 44 -| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N126 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N126 | 44 -| udp_osd_inst/char_osd_inst/char_buf_reader_inst/N15 | udp_osd_inst/char_osd_inst/char_buf_reader_inst/N15 | 44 -| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/rd_addr [0] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[0] | 44 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/rd_addr [0] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[0] | 44 +| udp_osd_inst/char_osd_inst/char_buf_reader_inst/N15 | udp_osd_inst/char_osd_inst/char_buf_reader_inst/N15 | 44 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [0] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[0] | 44 -| adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/rdy_t [11] | adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/rdy | 43 -| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [1] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1] | 43 -| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [2] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[2] | 43 +| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N126 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N126 | 44 +| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N119 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N119 | 44 +| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/rd_addr [0] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[0] | 44 +| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [0] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[0] | 44 | adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/rdy_t [3] | adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/rdy | 43 -| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [1] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1] | 43 -| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N104 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N104 | 43 -| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/rd_addr [1] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[1] | 43 +| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [1] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1] | 43 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/rd_addr [2] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[2] | 43 +| adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/rdy_t [11] | adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/rdy | 43 +| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [2] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[2] | 43 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [2] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[2] | 43 +| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [1] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1] | 43 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/rd_addr [2] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[2] | 43 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/rd_addr [1] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[1] | 43 +| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/rd_addr [1] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[1] | 43 +| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N104 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N104 | 43 +| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N193 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N193 | 42 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N198 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N198 | 42 -| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N54 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N54_3 | 42 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N197 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N197 | 42 -| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N193 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N193 | 42 +| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr [26] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[26] | 41 +| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N54 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N54_3 | 41 | u_zoom_image/data_in_valid0 | u_zoom_image/data_in_valid0 | 41 -| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/rd_addr [3] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.raddr_msb | 41 +| u_axi_ddr_top/rd_sta [0] | u_axi_ddr_top/rd_sta_reg[0] | 41 +| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [3] | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.waddr_msb | 41 +| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_en_real | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/N1 | 41 +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -1249,8 +1250,8 @@ Device Utilization Summary: +-------------------------------------------------------------------------+ | APM | 23.5 | 84 | 28 | IOCKDLY | 1 | 40 | 3 -| FF | 13620 | 64200 | 22 -| LUT | 13929 | 42800 | 33 +| FF | 13618 | 64200 | 22 +| LUT | 13927 | 42800 | 33 | Distributed RAM | 88 | 17000 | 1 | DLL | 2 | 10 | 20 | DQSL | 8 | 18 | 45 @@ -1264,7 +1265,7 @@ Device Utilization Summary: | RCKB | 0 | 24 | 0 | SCANCHAIN | 0 | 2 | 0 | START | 0 | 1 | 0 -| USCM | 13 | 30 | 44 +| USCM | 14 | 30 | 47 | HSST | 0 | 1 | 0 | OSC | 0 | 1 | 0 | CRYSTAL | 0 | 2 | 0 @@ -1276,7 +1277,7 @@ Device Utilization Summary: Virtual IO Port Info: NULL Device mapping done. -Total device mapping takes 4.22 sec. +Total device mapping takes 5.19 sec. Inputs and Outputs : @@ -1292,7 +1293,7 @@ Inputs and Outputs : Flow Command: dev_map -Peak memory: 557 MB -Total CPU time to dev_map completion : 0h:0m:28s -Process Total CPU time to dev_map completion : 0h:0m:30s -Total real time to dev_map completion : 0h:0m:30s +Peak memory: 556 MB +Total CPU time to dev_map completion : 0h:0m:31s +Process Total CPU time to dev_map completion : 0h:0m:32s +Total real time to dev_map completion : 0h:0m:33s diff --git a/project/device_map/multimedia_video_processor_map.adf b/project/device_map/multimedia_video_processor_map.adf index bfed5cd..8be51c2 100644 Binary files a/project/device_map/multimedia_video_processor_map.adf and b/project/device_map/multimedia_video_processor_map.adf differ diff --git a/project/device_map/psd_ddr_top.pcf b/project/device_map/psd_ddr_top.pcf index d3a56b9..1d28b2e 100644 --- a/project/device_map/psd_ddr_top.pcf +++ b/project/device_map/psd_ddr_top.pcf @@ -1,4 +1,4 @@ -#Generated by Fabric Compiler ( version 2022.2-SP1-Lite ) at Sat Nov 11 17:55:22 2023 +#Generated by Fabric Compiler ( version 2022.2-SP1-Lite ) at Wed Nov 15 19:36:40 2023 def_port {cmos1_scl} LOC=Y11 VCCIO=3.3 IOSTANDARD=LVCMOS33 DRIVE=8 SLEW=SLOW NONE=TRUE def_port {cmos1_sda} LOC=Y13 VCCIO=3.3 IOSTANDARD=LVCMOS33 DRIVE=8 SLEW=SLOW NONE=TRUE diff --git a/project/generate_bitstream/bgr.db b/project/generate_bitstream/bgr.db index c571564..19e371a 100644 --- a/project/generate_bitstream/bgr.db +++ b/project/generate_bitstream/bgr.db @@ -11,10 +11,10 @@ RAM(GB) - 0h:0m:37s - 0h:0m:37s - 0h:0m:38s - 927 + 0h:0m:41s + 0h:0m:41s + 0h:0m:41s + 926 WINDOWS 10 x86_64 Intel(R) Core(TM) i7-9750H CPU @ 2.60GHz 32 diff --git a/project/generate_bitstream/multimedia_video_processor.bgr b/project/generate_bitstream/multimedia_video_processor.bgr index 6599e9d..01688ba 100644 --- a/project/generate_bitstream/multimedia_video_processor.bgr +++ b/project/generate_bitstream/multimedia_video_processor.bgr @@ -1,9 +1,9 @@ -Generated by Fabric Compiler ( version 2022.2-SP1-Lite ) at Sat Nov 11 17:59:01 2023 +Generated by Fabric Compiler ( version 2022.2-SP1-Lite ) at Wed Nov 15 19:40:41 2023 Start Generating Programming File... -Reading design from DB takes 4.125000 sec. +Reading design from DB takes 4.390625 sec. The bitstream file is "D:/Project/FPGA_Project/Pango/multimedia_video_processor/project/generate_bitstream/multimedia_video_processor.sbit" -Generate programming file takes 26.937500 sec. +Generate programming file takes 29.625000 sec. Generating Programming File done. Inputs and Outputs : @@ -19,7 +19,7 @@ Inputs and Outputs : Flow Command: gen_bit_stream -Peak memory: 927 MB -Total CPU time to gen_bit_stream completion : 0h:0m:37s -Process Total CPU time to gen_bit_stream completion : 0h:0m:37s -Total real time to gen_bit_stream completion : 0h:0m:38s +Peak memory: 926 MB +Total CPU time to gen_bit_stream completion : 0h:0m:41s +Process Total CPU time to gen_bit_stream completion : 0h:0m:41s +Total real time to gen_bit_stream completion : 0h:0m:41s diff --git a/project/generate_bitstream/multimedia_video_processor.sbit b/project/generate_bitstream/multimedia_video_processor.sbit index 1864f14..8811f53 100644 Binary files a/project/generate_bitstream/multimedia_video_processor.sbit and b/project/generate_bitstream/multimedia_video_processor.sbit differ diff --git a/project/generate_bitstream/multimedia_video_processor.smsk b/project/generate_bitstream/multimedia_video_processor.smsk index b11390f..60b6aa6 100644 Binary files a/project/generate_bitstream/multimedia_video_processor.smsk and b/project/generate_bitstream/multimedia_video_processor.smsk differ diff --git a/project/impl.tcl b/project/impl.tcl index f6e39f8..9e7668c 100644 --- a/project/impl.tcl +++ b/project/impl.tcl @@ -101,3 +101,61 @@ dev_map pnr -fix_hold_violation report_timing gen_bit_stream +set_arch -family Logos -device PGL50H -speedgrade -6 -package FBG484 +compile -top_module multimedia_video_processor +set_arch -family Logos -device PGL50H -speedgrade -6 -package FBG484 +compile -top_module multimedia_video_processor +synthesize -ads -frequency {100} -selected_syn_tool_opt 2 +dev_map +pnr -fix_hold_violation +report_timing +gen_bit_stream +set_arch -family Logos -device PGL50H -speedgrade -6 -package FBG484 +compile -top_module multimedia_video_processor +synthesize -ads -frequency {100} -selected_syn_tool_opt 2 +dev_map +pnr -fix_hold_violation +report_timing +gen_bit_stream +set_arch -family Logos -device PGL50H -speedgrade -6 -package FBG484 +compile -top_module multimedia_video_processor +synthesize -ads -frequency {100} -selected_syn_tool_opt 2 +dev_map +pnr -fix_hold_violation +report_timing +gen_bit_stream +set_arch -family Logos -device PGL50H -speedgrade -6 -package FBG484 +compile -top_module multimedia_video_processor +synthesize -ads -frequency {100} -selected_syn_tool_opt 2 +dev_map +pnr -fix_hold_violation +report_timing +gen_bit_stream +set_arch -family Logos -device PGL50H -speedgrade -6 -package FBG484 +compile -top_module multimedia_video_processor +synthesize -ads -frequency {100} -selected_syn_tool_opt 2 +dev_map +pnr -fix_hold_violation +report_timing +gen_bit_stream +set_arch -family Logos -device PGL50H -speedgrade -6 -package FBG484 +compile -top_module multimedia_video_processor +synthesize -ads -frequency {100} -selected_syn_tool_opt 2 +dev_map +pnr -fix_hold_violation +report_timing +gen_bit_stream +set_arch -family Logos -device PGL50H -speedgrade -6 -package FBG484 +compile -top_module multimedia_video_processor +synthesize -ads -frequency {100} -selected_syn_tool_opt 2 +dev_map +pnr -fix_hold_violation +report_timing +gen_bit_stream +set_arch -family Logos -device PGL50H -speedgrade -6 -package FBG484 +compile -top_module multimedia_video_processor +synthesize -ads -frequency {100} -selected_syn_tool_opt 2 +dev_map +pnr -fix_hold_violation +report_timing +gen_bit_stream diff --git a/project/multimedia_video_processor.pds b/project/multimedia_video_processor.pds index 521fccf..f4187f0 100644 --- a/project/multimedia_video_processor.pds +++ b/project/multimedia_video_processor.pds @@ -1,5 +1,5 @@ (_flow fab_demo "2022.2-SP1-Lite" - (_comment "Generated by Fabric Compiler (version on 2022.2-SP1-Lite) at Sat Nov 11 17:59:26 2023") + (_comment "Generated by Fabric Compiler (version on 2022.2-SP1-Lite) at Wed Nov 15 19:41:09 2023") (_version "1.0.9") (_status "initial") (_project @@ -21,7 +21,7 @@ (_input (_file "../sources/designs/multimedia_video_processor.v" + "multimedia_video_processor" (_format verilog) - (_timespec "2023-11-11T17:50:53") + (_timespec "2023-11-15T19:32:44") ) (_file "../sources/designs/udp_osd/char_osd/char_buf_reader.v" (_format verilog) @@ -33,7 +33,7 @@ ) (_file "../sources/designs/udp_osd/char_osd/char_osd.v" (_format verilog) - (_timespec "2023-10-22T13:28:44") + (_timespec "2023-11-14T18:21:34") ) (_file "../sources/designs/udp_osd/char_osd/char_pic_rom.v" (_format verilog) @@ -65,7 +65,7 @@ ) (_file "../sources/designs/udp_osd/eth_udp/eth_udp.v" (_format verilog) - (_timespec "2023-11-08T14:35:25") + (_timespec "2023-11-14T18:06:57") ) (_file "../sources/designs/udp_osd/eth_udp/icmp/icmp.v" (_format verilog) @@ -121,7 +121,7 @@ ) (_file "../sources/designs/image_filiter/image_filiter.v" (_format verilog) - (_timespec "2023-11-05T17:01:17") + (_timespec "2023-11-14T11:20:48") ) (_file "../sources/designs/image_filiter/median_finder9.v" (_format verilog) @@ -129,7 +129,7 @@ ) (_file "../sources/designs/image_filiter/multiline_buffer.v" (_format verilog) - (_timespec "2023-11-06T18:55:59") + (_timespec "2023-11-14T11:36:55") ) (_file "../sources/designs/image_filiter/sort_3.v" (_format verilog) @@ -137,7 +137,7 @@ ) (_file "../sources/designs/image_filiter/vector_to_matrix.v" (_format verilog) - (_timespec "2023-11-06T18:56:26") + (_timespec "2023-11-14T11:52:33") ) (_file "../sources/designs/others/key_debounce.v" (_format verilog) @@ -145,7 +145,7 @@ ) (_file "../sources/designs/others/param_manager.v" (_format verilog) - (_timespec "2023-11-11T17:22:27") + (_timespec "2023-11-15T10:35:11") ) (_file "../sources/designs/others/udp_wr_mem.v" (_format verilog) @@ -153,7 +153,7 @@ ) (_file "../sources/designs/adjust_color/adjust_color.v" (_format verilog) - (_timespec "2023-11-10T14:46:20") + (_timespec "2023-11-14T23:57:44") ) (_file "../sources/designs/adjust_color/adjust_color_wrapper.v" (_format verilog) @@ -185,7 +185,7 @@ ) (_file "../sources/designs/others/param_cell_signed_loop.v" (_format verilog) - (_timespec "2023-11-10T15:35:23") + (_timespec "2023-11-13T13:23:08") ) (_file "../sources/designs/others/param_cell_unsigned.v" (_format verilog) @@ -201,7 +201,7 @@ ) (_file "../sources/designs/ddr/addr_ctrl/ddr_addr_ctr.v" (_format verilog) - (_timespec "2023-11-11T12:21:50") + (_timespec "2023-11-15T14:33:30") ) (_file "../sources/designs/ddr/addr_ctrl/rd0_addr_ctr.v" (_format verilog) @@ -221,7 +221,7 @@ ) (_file "../sources/designs/ddr/addr_ctrl/wr0_addr_ctr.v" (_format verilog) - (_timespec "2023-11-11T12:21:56") + (_timespec "2023-11-12T21:42:35") ) (_file "../sources/designs/ddr/addr_ctrl/wr1_addr_ctr.v" (_format verilog) @@ -249,7 +249,7 @@ ) (_file "../sources/designs/hdmi/hdmi_out/sync_vg.v" (_format verilog) - (_timespec "2023-11-11T12:22:10") + (_timespec "2023-11-15T10:28:46") ) (_file "../sources/designs/hdmi/ms72xx_ctrl/iic_dri.v" (_format verilog) @@ -277,11 +277,11 @@ ) (_file "../sources/designs/ov5640/mix_image.v" (_format verilog) - (_timespec "2023-11-11T12:23:05") + (_timespec "2023-11-13T20:58:00") ) (_file "../sources/designs/ov5640/ov5640.v" (_format verilog) - (_timespec "2023-11-11T13:00:25") + (_timespec "2023-11-13T23:26:58") ) (_file "../sources/designs/ov5640/power_on_delay.v" (_format verilog) @@ -297,7 +297,7 @@ ) (_file "../sources/designs/rotate/rotate_image.v" (_format verilog) - (_timespec "2023-11-11T16:05:07") + (_timespec "2023-11-15T15:01:39") ) (_file "../sources/designs/rotate/rotate_mult0.v" (_format verilog) @@ -317,11 +317,11 @@ ) (_file "../sources/designs/zoom/zoom_image_v1.v" (_format verilog) - (_timespec "2023-11-11T16:30:42") + (_timespec "2023-11-14T16:38:20") ) (_file "../sources/designs/hdmi/hdmi_in/hdmi_in_top.v" (_format verilog) - (_timespec "2023-11-11T12:22:10") + (_timespec "2023-11-14T11:14:09") ) ) ) @@ -848,17 +848,17 @@ (_db_output (_file "compile/multimedia_video_processor_comp.adf" (_format adif) - (_timespec "2023-11-11T17:52:48") + (_timespec "2023-11-15T19:34:03") ) ) (_output (_file "compile/multimedia_video_processor.cmr" (_format verilog) - (_timespec "2023-11-11T17:52:49") + (_timespec "2023-11-15T19:34:03") ) (_file "compile/cmr.db" (_format text) - (_timespec "2023-11-11T17:52:49") + (_timespec "2023-11-15T19:34:03") ) ) ) @@ -874,25 +874,25 @@ (_db_output (_file "synthesize/multimedia_video_processor_syn.adf" (_format adif) - (_timespec "2023-11-11T17:54:39") + (_timespec "2023-11-15T19:35:56") ) ) (_output (_file "synthesize/multimedia_video_processor_syn.vm" (_format structural_verilog) - (_timespec "2023-11-11T17:54:44") + (_timespec "2023-11-15T19:35:59") ) (_file "synthesize/multimedia_video_processor_controlsets.txt" (_format text) - (_timespec "2023-11-11T17:54:12") + (_timespec "2023-11-15T19:35:28") ) (_file "synthesize/snr.db" (_format text) - (_timespec "2023-11-11T17:54:49") + (_timespec "2023-11-15T19:36:04") ) (_file "synthesize/multimedia_video_processor.snr" (_format text) - (_timespec "2023-11-11T17:54:48") + (_timespec "2023-11-15T19:36:03") ) ) ) @@ -913,21 +913,21 @@ (_db_output (_file "device_map/multimedia_video_processor_map.adf" (_format adif) - (_timespec "2023-11-11T17:55:22") + (_timespec "2023-11-15T19:36:40") ) ) (_output (_file "device_map/multimedia_video_processor_dmr.prt" (_format text) - (_timespec "2023-11-11T17:55:09") + (_timespec "2023-11-15T19:36:26") ) (_file "device_map/multimedia_video_processor.dmr" (_format text) - (_timespec "2023-11-11T17:55:22") + (_timespec "2023-11-15T19:36:40") ) (_file "device_map/dmr.db" (_format text) - (_timespec "2023-11-11T17:55:22") + (_timespec "2023-11-15T19:36:40") ) ) ) @@ -936,7 +936,7 @@ (_input (_file "device_map/psd_ddr_top.pcf" (_format pcf) - (_timespec "2023-11-11T17:55:22") + (_timespec "2023-11-15T19:36:40") ) ) ) @@ -946,7 +946,7 @@ (_file "kkk.rcf" (_option target_file (_switch ON)) (_format rcf) - (_timespec "2023-11-11T16:19:45") + (_timespec "") ) ) ) @@ -958,33 +958,33 @@ (_db_output (_file "place_route/multimedia_video_processor_pnr.adf" (_format adif) - (_timespec "2023-11-11T17:58:10") + (_timespec "2023-11-15T19:39:47") ) ) (_output (_file "place_route/clock_utilization.txt" (_format text) - (_timespec "2023-11-11T17:57:51") + (_timespec "2023-11-15T19:39:27") ) (_file "place_route/multimedia_video_processor_plc.adf" (_format adif) - (_timespec "2023-11-11T17:56:43") + (_timespec "2023-11-15T19:38:00") ) (_file "place_route/multimedia_video_processor.prr" (_format text) - (_timespec "2023-11-11T17:58:11") + (_timespec "2023-11-15T19:39:48") ) (_file "place_route/multimedia_video_processor_prr.prt" (_format text) - (_timespec "2023-11-11T17:57:51") + (_timespec "2023-11-15T19:39:27") ) (_file "place_route/multimedia_video_processor_pnr.netlist" (_format text) - (_timespec "2023-11-11T17:58:11") + (_timespec "2023-11-15T19:39:48") ) (_file "place_route/prr.db" (_format text) - (_timespec "2023-11-11T17:58:11") + (_timespec "2023-11-15T19:39:48") ) ) ) @@ -1000,17 +1000,17 @@ (_db_output (_file "report_timing/multimedia_video_processor_rtp.adf" (_format adif) - (_timespec "2023-11-11T17:58:38") + (_timespec "2023-11-15T19:40:16") ) ) (_output (_file "report_timing/multimedia_video_processor.rtr" (_format text) - (_timespec "2023-11-11T17:58:40") + (_timespec "2023-11-15T19:40:19") ) (_file "report_timing/rtr.db" (_format text) - (_timespec "2023-11-11T17:58:41") + (_timespec "2023-11-15T19:40:19") ) ) ) @@ -1034,19 +1034,19 @@ (_output (_file "generate_bitstream/multimedia_video_processor.sbit" (_format text) - (_timespec "2023-11-11T17:59:23") + (_timespec "2023-11-15T19:41:06") ) (_file "generate_bitstream/multimedia_video_processor.smsk" (_format text) - (_timespec "2023-11-11T17:59:24") + (_timespec "2023-11-15T19:41:07") ) (_file "generate_bitstream/bgr.db" (_format text) - (_timespec "2023-11-11T17:59:25") + (_timespec "2023-11-15T19:41:08") ) (_file "generate_bitstream/multimedia_video_processor.bgr" (_format text) - (_timespec "2023-11-11T17:59:24") + (_timespec "2023-11-15T19:41:07") ) ) ) diff --git a/project/multiseed_summary.csv b/project/multiseed_summary.csv index b4f115b..15791f5 100644 --- a/project/multiseed_summary.csv +++ b/project/multiseed_summary.csv @@ -3,23 +3,23 @@ project name,multimedia_video_processor.pds Single Seed: Seed,State,Convergence,Setup(Slow),Setup(Fast),Hold(Slow),Hold(Fast),Recovery(Slow),Recovery(Fast),Removal(Slow),Removal(Fast),PBM-GP,PBM-PreGP,PBM-PostGP,LP,Total Placement Cpu Time,Detailed routing,Total Routing Cpu Time,Wire Length After Post-GP,Wire Length After LP,Wire Length After DP,Routing Arc Length,Worst Slack After GP Timing,Worst Slack After LP Timing,Worst Slack Before RP,Worst Slack Before DP,Worst Slack After DP,Worst Slack After Placement,Worst Slack After TA By Preroute,TNS After DP,TNS Before Route,Setup(Slow) Total Failing TNS,Setup(Slow) Total Failing Endpoints,Hold(Slow) Total Failing THS,Hold(Slow) Total Failing Endpoints -single,OK,Fail,-0.788,0.707,0.149,0.106,1.103,2.157,0.554,0.418,NA,NA,NA,1.64,44.78,30.09,49.84,121211,154129,154129,215189,NA,NA,-1259,NA,NA,-1259,NA,NA,-36829,-18.651,44,0.000,0 -Pass Rate/Convergence Rate,100.00%,0.00% +single,OK,OK,1.026,1.834,0.157,0.075,1.149,2.160,0.555,0.452,NA,NA,NA,1.70,42.31,37.05,64.98,129229,158300,158329,212372,NA,NA,556,NA,NA,1339,NA,NA,0,0.000,0,0.000,0 +Pass Rate/Convergence Rate,100.00%,100.00% Synthesize: control_set,504 Synthesize Performance Summary: slack category,Synthesize Setup WNS,Synthesize Setup TNS,Synthesize Recovery WNS,Synthesize Recovery TNS -slack value,0.130,0.000,1.564,0.000 -Synthesize Process Cpu Time,0h:1m:39s +slack value,1.064,0.000,1.564,0.000 +Synthesize Process Cpu Time,0h:1m:43s Device Map: Device Map Resource Usage Summary: Logic Utilization,LUT,FF,DRM,APM,Distributed RAM,HSSTHP,USCM,HCKB,RCKB -Used,13929,13620,98.5,23.5,88,NA,13,NA,0 +Used,13927,13618,98.5,23.5,88,NA,14,NA,0 Available,42800,64200,134,84,17000,NA,30,NA,24 -Utilization(%),33%,22%,74%,28%,1%,NA,44%,NA,0% -Device Map Process Cpu Time,0h:0m:30s +Utilization(%),33%,22%,74%,28%,1%,NA,47%,NA,0% +Device Map Process Cpu Time,0h:0m:32s Project Configurations: top module,multimedia_video_processor diff --git a/project/place_route/clock_utilization.txt b/project/place_route/clock_utilization.txt index a43b4be..3ae07a6 100644 --- a/project/place_route/clock_utilization.txt +++ b/project/place_route/clock_utilization.txt @@ -23,17 +23,18 @@ Global Clock Buffer Constraint Details: +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Source Name | Source Pin | Source-Buffer Net | Buffer Input Pin | Buffer Name | Buffer Output Pin | Buffer-Load Net | Clock Region Of Buffer Site | Buffer Site | IO Load Clock Region | Non-IO Load Clock Region | Clock Loads | Non-Clock Loads +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -| u_sys_pll/u_pll_e3/goppll | CLKOUT0 | rd3_clk | CLK | clkbufg_1/gopclkbufg | CLKOUT | ntclkbufg_1 | --- | --- | --- | --- | 2517 | 0 -| udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0 | CLKOUT | udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf | CLK | udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg | CLKOUT | gmii_clk | --- | --- | (36,158,90,91) | --- | 1861 | 0 -| u_sys_pll/u_pll_e3/goppll | CLKOUT4 | clk_10m | CLK | clkbufg_3/gopclkbufg | CLKOUT | ntclkbufg_3 | --- | --- | --- | --- | 235 | 0 -| hdmi_in_clk_ibuf/opit_1 | INCK | _N37 | CLK | clkbufg_4/gopclkbufg | CLKOUT | ntclkbufg_4 | --- | --- | --- | --- | 167 | 0 -| cmos1_pclk_ibuf/opit_1 | INCK | _N64 | CLK | clkbufg_5/gopclkbufg | CLKOUT | ntclkbufg_5 | --- | --- | --- | --- | 118 | 0 -| u_sys_pll/u_pll_e3/goppll | CLKOUT1 | zoom_clk | CLK | u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg | CLKOUT | u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin | --- | --- | --- | (79,79,43,47) | 68 | 0 -| u_sys_pll/u_pll_e3/goppll | CLKOUT3 | clk_25m | CLK | clkbufg_7/gopclkbufg | CLKOUT | ntclkbufg_7 | --- | --- | --- | --- | 26 | 0 +| u_sys_pll/u_pll_e3/goppll | CLKOUT0 | rd3_clk | CLK | clkbufg_1/gopclkbufg | CLKOUT | ntclkbufg_1 | --- | --- | --- | --- | 2516 | 0 +| udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0 | CLKOUT | udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf | CLK | udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg | CLKOUT | gmii_clk | --- | --- | (36,158,90,91) | --- | 1862 | 0 +| u_sys_pll/u_pll_e3/goppll | CLKOUT4 | clk_10m | CLK | clkbufg_4/gopclkbufg | CLKOUT | ntclkbufg_4 | --- | --- | --- | --- | 235 | 0 +| hdmi_in_clk_ibuf/opit_1 | INCK | _N37 | CLK | clkbufg_5/gopclkbufg | CLKOUT | ntclkbufg_5 | --- | --- | --- | --- | 167 | 0 +| cmos1_pclk_ibuf/opit_1 | INCK | _N64 | CLK | clkbufg_6/gopclkbufg | CLKOUT | ntclkbufg_6 | --- | --- | --- | --- | 118 | 0 +| u_sys_pll/u_pll_e3/goppll | CLKOUT1 | ddr_clk | CLK | u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg | CLKOUT | u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin | --- | --- | --- | (79,79,43,47) | 71 | 0 +| u_sys_pll/u_pll_e3/goppll | CLKOUT3 | clk_25m | CLK | clkbufg_8/gopclkbufg | CLKOUT | ntclkbufg_8 | --- | --- | --- | --- | 26 | 0 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll | CLKOUT1 | u_axi_ddr_top/I_ipsxb_ddr_top/ioclk_gate_clk_pll | CLK | u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg_gate/gopclkbufg | CLKOUT | u_axi_ddr_top/I_ipsxb_ddr_top/ioclk_gate_clk | --- | --- | --- | (74,74,46,46) | 1 | 0 -| u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv | CLKDIV | u_axi_ddr_top/clk | CLK | clkbufg_0/gopclkbufg | CLKOUT | ntclkbufg_0 | --- | --- | (0,4,4,89) | (4,4,7,84) | 5464 | 0 | U_HDMI_PLL/u_pll_e3/goppll | CLKOUT1 | nt_pix_clk | CLK | clkbufg_2/gopclkbufg | CLKOUT | ntclkbufg_2 | --- | --- | --- | --- | 1635 | 0 -| cmos2_pclk_ibuf/opit_1 | OUT | nt_cmos2_pclk | CLK | clkbufg_6/gopclkbufg | CLKOUT | ntclkbufg_6 | --- | --- | --- | --- | 118 | 0 +| u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv | CLKDIV | u_axi_ddr_top/clk | CLK | clkbufg_0/gopclkbufg | CLKOUT | ntclkbufg_0 | --- | --- | (0,4,4,89) | (4,4,7,84) | 5464 | 0 +| U_HDMI_PLL/u_pll_e3/goppll | CLKOUT0 | zoom_clk | CLK | clkbufg_3/gopclkbufg | CLKOUT | ntclkbufg_3 | --- | --- | --- | --- | 750 | 0 +| cmos2_pclk_ibuf/opit_1 | OUT | nt_cmos2_pclk | CLK | clkbufg_7/gopclkbufg | CLKOUT | ntclkbufg_7 | --- | --- | --- | --- | 118 | 0 | u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv | Q | u_ov5640/coms1_reg_config/clk_20k_regdiv | CLK | u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg | CLKOUT | u_ov5640/coms1_reg_config/clock_20k | --- | --- | --- | --- | 19 | 0 | u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv | Q | u_ov5640/coms2_reg_config/clk_20k_regdiv | CLK | u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg | CLKOUT | u_ov5640/coms2_reg_config/clock_20k | --- | --- | --- | --- | 19 | 0 +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -47,11 +48,12 @@ Global Clock Source Constraint Details: | u_sys_pll/u_pll_e3/goppll | CLKOUT4 | clk_10m | (X0,Y0) | PLL_158_55 | 1 | 0 | hdmi_in_clk_ibuf/opit_1 | INCK | _N37 | (X1,Y0) | IOL_163_6 | 1 | 0 | cmos1_pclk_ibuf/opit_1 | INCK | _N64 | (X1,Y0) | IOL_171_6 | 1 | 0 -| u_sys_pll/u_pll_e3/goppll | CLKOUT1 | zoom_clk | (X0,Y0) | PLL_158_55 | 1 | 759 +| u_sys_pll/u_pll_e3/goppll | CLKOUT1 | ddr_clk | (X0,Y0) | PLL_158_55 | 1 | 6 | u_sys_pll/u_pll_e3/goppll | CLKOUT3 | clk_25m | (X0,Y0) | PLL_158_55 | 1 | 0 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll | CLKOUT1 | u_axi_ddr_top/I_ipsxb_ddr_top/ioclk_gate_clk_pll | (X0,Y1) | PLL_158_199 | 1 | 0 -| u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv | CLKDIV | u_axi_ddr_top/clk | --- | --- | 1 | 0 | U_HDMI_PLL/u_pll_e3/goppll | CLKOUT1 | nt_pix_clk | --- | --- | 1 | 1 +| u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv | CLKDIV | u_axi_ddr_top/clk | --- | --- | 1 | 0 +| U_HDMI_PLL/u_pll_e3/goppll | CLKOUT0 | zoom_clk | --- | --- | 1 | 0 | cmos2_pclk_ibuf/opit_1 | OUT | nt_cmos2_pclk | (X0,Y0) | IOL_39_6 | 1 | 0 | u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv | Q | u_ov5640/coms1_reg_config/clk_20k_regdiv | --- | --- | 1 | 2 | u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv | Q | u_ov5640/coms2_reg_config/clk_20k_regdiv | --- | --- | 1 | 2 @@ -64,7 +66,7 @@ IO Clock Buffer Constraint Details: | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll | CLKOUT0_WL | clkout0_wl_0 | CLK | u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate | OUT | u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] | --- | --- | (0,4,32,59) | (4,4,37,54) | 28 | 0 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll | CLKOUT0_WL | clkout0_wl_0 | CLK | u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate | OUT | u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] | --- | --- | (0,4,62,84) | (4,4,67,84) | 11 | 0 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_1/u_pll_e3/goppll | CLKOUT0_WL | clkout0_wl_1 | CLK | u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_2/gopclkgate | OUT | u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [2] | --- | --- | (4,4,7,24) | (4,4,7,24) | 2 | 0 -| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll | CLKOUT0_WL | clkout0_wl_0 | CLK | clkgate_8/gopclkgate | OUT | ntclkgate_0 | --- | --- | --- | --- | 0 | 1 +| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll | CLKOUT0_WL | clkout0_wl_0 | CLK | clkgate_9/gopclkgate | OUT | ntclkgate_0 | --- | --- | --- | --- | 0 | 1 +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ IO Clock Source Constraint Details: @@ -79,19 +81,20 @@ Device Cell Placement Summary for Global Clock Buffer: +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Source Name | Source Pin | Source-Buffer Net | Buffer Input Pin | Buffer Name | Buffer Output Pin | Buffer-Load Net | Buffer Site | IO Load Clock Region | Non-IO Load Clock Region | Clock Loads | Non-Clock Loads +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -| u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv | CLKDIV | u_axi_ddr_top/clk | CLK | clkbufg_0/gopclkbufg | CLKOUT | ntclkbufg_0 | USCM_84_116 | (0,2,4,89) | (4,70,3,84) | 5464 | 0 -| u_sys_pll/u_pll_e3/goppll | CLKOUT0 | rd3_clk | CLK | clkbufg_1/gopclkbufg | CLKOUT | ntclkbufg_1 | USCM_84_108 | --- | (23,102,2,53) | 2517 | 0 -| U_HDMI_PLL/u_pll_e3/goppll | CLKOUT1 | nt_pix_clk | CLK | clkbufg_2/gopclkbufg | CLKOUT | ntclkbufg_2 | USCM_84_117 | --- | (74,152,8,88) | 1635 | 0 -| u_sys_pll/u_pll_e3/goppll | CLKOUT4 | clk_10m | CLK | clkbufg_3/gopclkbufg | CLKOUT | ntclkbufg_3 | USCM_84_110 | --- | (70,120,13,38) | 235 | 0 -| hdmi_in_clk_ibuf/opit_1 | INCK | _N37 | CLK | clkbufg_4/gopclkbufg | CLKOUT | ntclkbufg_4 | USCM_84_111 | --- | (28,96,8,28) | 167 | 0 -| cmos1_pclk_ibuf/opit_1 | INCK | _N64 | CLK | clkbufg_5/gopclkbufg | CLKOUT | ntclkbufg_5 | USCM_84_112 | --- | (66,76,2,10) | 118 | 0 -| cmos2_pclk_ibuf/opit_1 | OUT | nt_cmos2_pclk | CLK | clkbufg_6/gopclkbufg | CLKOUT | ntclkbufg_6 | USCM_84_118 | --- | (63,78,3,15) | 118 | 0 -| u_sys_pll/u_pll_e3/goppll | CLKOUT3 | clk_25m | CLK | clkbufg_7/gopclkbufg | CLKOUT | ntclkbufg_7 | USCM_84_114 | --- | (90,92,3,6) | 26 | 0 -| u_sys_pll/u_pll_e3/goppll | CLKOUT1 | zoom_clk | CLK | u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg | CLKOUT | u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin | USCM_84_113 | --- | (7,100,36,47) | 68 | 0 +| u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv | CLKDIV | u_axi_ddr_top/clk | CLK | clkbufg_0/gopclkbufg | CLKOUT | ntclkbufg_0 | USCM_84_116 | (0,2,4,89) | (4,81,4,84) | 5464 | 0 +| u_sys_pll/u_pll_e3/goppll | CLKOUT0 | rd3_clk | CLK | clkbufg_1/gopclkbufg | CLKOUT | ntclkbufg_1 | USCM_84_108 | --- | (25,102,5,88) | 2516 | 0 +| U_HDMI_PLL/u_pll_e3/goppll | CLKOUT1 | nt_pix_clk | CLK | clkbufg_2/gopclkbufg | CLKOUT | ntclkbufg_2 | USCM_84_117 | --- | (74,150,3,74) | 1635 | 0 +| U_HDMI_PLL/u_pll_e3/goppll | CLKOUT0 | zoom_clk | CLK | clkbufg_3/gopclkbufg | CLKOUT | ntclkbufg_3 | USCM_84_118 | --- | (56,150,3,78) | 750 | 0 +| u_sys_pll/u_pll_e3/goppll | CLKOUT4 | clk_10m | CLK | clkbufg_4/gopclkbufg | CLKOUT | ntclkbufg_4 | USCM_84_110 | --- | (42,133,43,80) | 235 | 0 +| hdmi_in_clk_ibuf/opit_1 | INCK | _N37 | CLK | clkbufg_5/gopclkbufg | CLKOUT | ntclkbufg_5 | USCM_84_111 | --- | (39,77,4,33) | 167 | 0 +| cmos1_pclk_ibuf/opit_1 | INCK | _N64 | CLK | clkbufg_6/gopclkbufg | CLKOUT | ntclkbufg_6 | USCM_84_112 | --- | (64,76,3,15) | 118 | 0 +| cmos2_pclk_ibuf/opit_1 | OUT | nt_cmos2_pclk | CLK | clkbufg_7/gopclkbufg | CLKOUT | ntclkbufg_7 | USCM_84_119 | --- | (39,74,2,10) | 118 | 0 +| u_sys_pll/u_pll_e3/goppll | CLKOUT3 | clk_25m | CLK | clkbufg_8/gopclkbufg | CLKOUT | ntclkbufg_8 | USCM_84_114 | --- | (59,61,2,4) | 26 | 0 +| u_sys_pll/u_pll_e3/goppll | CLKOUT1 | ddr_clk | CLK | u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg | CLKOUT | u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin | USCM_84_113 | --- | (7,86,43,61) | 71 | 0 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll | CLKOUT1 | u_axi_ddr_top/I_ipsxb_ddr_top/ioclk_gate_clk_pll | CLK | u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg_gate/gopclkbufg | CLKOUT | u_axi_ddr_top/I_ipsxb_ddr_top/ioclk_gate_clk | USCM_84_115 | --- | (74,74,46,46) | 1 | 0 -| u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv | Q | u_ov5640/coms1_reg_config/clk_20k_regdiv | CLK | u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg | CLKOUT | u_ov5640/coms1_reg_config/clock_20k | USCM_84_119 | --- | (83,91,3,5) | 19 | 0 -| u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv | Q | u_ov5640/coms2_reg_config/clk_20k_regdiv | CLK | u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg | CLKOUT | u_ov5640/coms2_reg_config/clock_20k | USCM_84_120 | --- | (85,90,6,9) | 19 | 0 -| udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0 | CLKOUT | udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf | CLK | udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg | CLKOUT | gmii_clk | USCM_84_109 | (36,158,90,91) | (76,125,27,64) | 1861 | 0 +| u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv | Q | u_ov5640/coms1_reg_config/clk_20k_regdiv | CLK | u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg | CLKOUT | u_ov5640/coms1_reg_config/clock_20k | USCM_84_120 | --- | (66,72,2,4) | 19 | 0 +| u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv | Q | u_ov5640/coms2_reg_config/clk_20k_regdiv | CLK | u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg | CLKOUT | u_ov5640/coms2_reg_config/clock_20k | USCM_84_121 | --- | (40,46,3,4) | 19 | 0 +| udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0 | CLKOUT | udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf | CLK | udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg | CLKOUT | gmii_clk | USCM_84_109 | (36,158,90,91) | (75,134,47,85) | 1862 | 0 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ Device Cell Placement Summary for Global Clock Source: @@ -101,15 +104,16 @@ Device Cell Placement Summary for Global Clock Source: | u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv | CLKDIV | u_axi_ddr_top/clk | IOCKDIV_6_323 | 1 | 0 | u_sys_pll/u_pll_e3/goppll | CLKOUT0 | rd3_clk | PLL_158_55 | 1 | 1 | U_HDMI_PLL/u_pll_e3/goppll | CLKOUT1 | nt_pix_clk | PLL_158_303 | 1 | 1 +| U_HDMI_PLL/u_pll_e3/goppll | CLKOUT0 | zoom_clk | PLL_158_303 | 1 | 0 | u_sys_pll/u_pll_e3/goppll | CLKOUT4 | clk_10m | PLL_158_55 | 1 | 0 | hdmi_in_clk_ibuf/opit_1 | INCK | _N37 | IOL_163_6 | 1 | 0 | cmos1_pclk_ibuf/opit_1 | INCK | _N64 | IOL_171_6 | 1 | 0 | cmos2_pclk_ibuf/opit_1 | OUT | nt_cmos2_pclk | IOL_39_6 | 1 | 0 | u_sys_pll/u_pll_e3/goppll | CLKOUT3 | clk_25m | PLL_158_55 | 1 | 0 -| u_sys_pll/u_pll_e3/goppll | CLKOUT1 | zoom_clk | PLL_158_55 | 1 | 759 +| u_sys_pll/u_pll_e3/goppll | CLKOUT1 | ddr_clk | PLL_158_55 | 1 | 6 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll | CLKOUT1 | u_axi_ddr_top/I_ipsxb_ddr_top/ioclk_gate_clk_pll | PLL_158_199 | 1 | 0 -| u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv | Q | u_ov5640/coms1_reg_config/clk_20k_regdiv | CLMA_182_12 | 1 | 2 -| u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv | Q | u_ov5640/coms2_reg_config/clk_20k_regdiv | CLMA_182_25 | 1 | 2 +| u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv | Q | u_ov5640/coms1_reg_config/clk_20k_regdiv | CLMS_122_9 | 1 | 2 +| u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv | Q | u_ov5640/coms2_reg_config/clk_20k_regdiv | CLMA_122_12 | 1 | 2 | udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0 | CLKOUT | udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf | IOCKDLY_237_367 | 1 | 0 +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -117,7 +121,7 @@ Device Cell Placement Summary for IO Clock Buffer: +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Source Name | Source Pin | Source-Buffer Net | Buffer Input Pin | Buffer Name | Buffer Output Pin | Buffer-Load Net | Buffer Site | IO Load Clock Region | Non-IO Load Clock Region | Clock Loads | Non-Clock Loads +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll | CLKOUT0_WL | clkout0_wl_0 | CLK | clkgate_8/gopclkgate | OUT | ntclkgate_0 | IOCKGATE_6_322 | --- | (5,5,77,77) | 0 | 1 +| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll | CLKOUT0_WL | clkout0_wl_0 | CLK | clkgate_9/gopclkgate | OUT | ntclkgate_0 | IOCKGATE_6_322 | --- | (5,5,77,77) | 0 | 1 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll | CLKOUT0_WL | clkout0_wl_0 | CLK | u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate | OUT | u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] | IOCKGATE_6_312 | (0,2,62,70) | (4,4,67,84) | 11 | 0 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll | CLKOUT0_WL | clkout0_wl_0 | CLK | u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate | OUT | u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] | IOCKGATE_6_188 | (0,2,32,59) | (4,5,37,54) | 28 | 0 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_1/u_pll_e3/goppll | CLKOUT0_WL | clkout0_wl_1 | CLK | u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_2/gopclkgate | OUT | u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [2] | IOCKGATE_6_64 | --- | (4,4,7,24) | 2 | 0 diff --git a/project/place_route/multimedia_video_processor.prr b/project/place_route/multimedia_video_processor.prr index dac8d5a..6f60925 100644 --- a/project/place_route/multimedia_video_processor.prr +++ b/project/place_route/multimedia_video_processor.prr @@ -1,23 +1,23 @@ -Generated by Fabric Compiler ( version 2022.2-SP1-Lite ) at Sat Nov 11 17:55:39 2023 +Generated by Fabric Compiler ( version 2022.2-SP1-Lite ) at Wed Nov 15 19:36:57 2023 In normal mode(fast, normal, performance). Placement started. Placement done. -Total placement takes 44.78 sec. +Total placement takes 42.31 sec. Routing started. -Building routing graph takes 2.20 sec. -Processing design graph takes 1.97 sec. -Total nets for routing : 27066. -Global routing takes 5.95 sec. -Detailed routing takes 30.09 sec. -Hold Violation Fix in router takes 4.84 sec. -Finish routing takes 1.48 sec. -Hold violation fix takes 2.00 sec. +Building routing graph takes 2.25 sec. +Processing design graph takes 2.03 sec. +Total nets for routing : 27114. +Global routing takes 8.94 sec. +Detailed routing takes 37.05 sec. +Hold Violation Fix in router takes 9.83 sec. +Finish routing takes 1.53 sec. +Hold violation fix takes 2.09 sec. Cleanup routing takes 0.02 sec. Routing done. -Total routing takes 49.84 sec. +Total routing takes 64.98 sec. IO Port Info: +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -212,21 +212,21 @@ Device Utilization Summary : +---------------------------------------------------------------------------+ | Use of APM | 23.5 | 84 | 28 | Use of BKCL | 4 | 4 | 100 -| Use of CLMA | 2694 | 6450 | 42 -| FF | 8356 | 38700 | 22 -| LUT | 8529 | 25800 | 34 -| LUT-FF pairs | 3368 | 25800 | 14 -| Use of CLMS | 1700 | 4250 | 40 -| FF | 5264 | 25500 | 21 -| LUT | 5415 | 17000 | 32 -| LUT-FF pairs | 2199 | 17000 | 13 +| Use of CLMA | 2666 | 6450 | 42 +| FF | 8349 | 38700 | 22 +| LUT | 8468 | 25800 | 33 +| LUT-FF pairs | 3365 | 25800 | 14 +| Use of CLMS | 1728 | 4250 | 41 +| FF | 5269 | 25500 | 21 +| LUT | 5482 | 17000 | 33 +| LUT-FF pairs | 2194 | 17000 | 13 | Distributed RAM | 88 | 17000 | 1 | Use of CRYSTAL | 0 | 2 | 0 | Use of DLL | 2 | 10 | 20 | Use of DQSL | 8 | 18 | 45 | Use of DRM | 98.5 | 134 | 74 | Use of FUSECODE | 0 | 1 | 0 -| Use of HARD0N1 | 1334 | 6672 | 20 +| Use of HARD0N1 | 1340 | 6672 | 21 | Use of HSST | 0 | 1 | 0 | Use of IO | 180 | 296 | 61 | IOBD | 32 | 64 | 50 @@ -254,7 +254,7 @@ Device Utilization Summary : | Use of SCANCHAIN | 0 | 2 | 0 | Use of START | 1 | 1 | 100 | Use of UDID | 0 | 1 | 0 -| Use of USCM | 16 | 30 | 54 +| Use of USCM | 17 | 30 | 57 | USCM dataused | 0 | 30 | 0 | Use of USCMMUX_TEST | 0 | 30 | 0 | Use of VCKBMUX_TEST | 0 | 12 | 0 @@ -265,18 +265,19 @@ Global Clock Info: | GClk Inst | Site Of GClk Inst | GClk Fanout Net | Clock Loads | Non_Clock Loads | Driver Inst | Driver Pin | Site Of Driver Inst +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | clkbufg_0/gopclkbufg | USCM_84_116 | ntclkbufg_0 | 5446 | 0 | u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv | CLKDIV | IOCKDIV_6_323 -| clkbufg_1/gopclkbufg | USCM_84_108 | ntclkbufg_1 | 2506 | 0 | u_sys_pll/u_pll_e3/goppll | CLKOUT0 | PLL_158_55 +| clkbufg_1/gopclkbufg | USCM_84_108 | ntclkbufg_1 | 2505 | 0 | u_sys_pll/u_pll_e3/goppll | CLKOUT0 | PLL_158_55 | clkbufg_2/gopclkbufg | USCM_84_117 | ntclkbufg_2 | 1633 | 0 | U_HDMI_PLL/u_pll_e3/goppll | CLKOUT1 | PLL_158_303 -| clkbufg_3/gopclkbufg | USCM_84_110 | ntclkbufg_3 | 233 | 0 | u_sys_pll/u_pll_e3/goppll | CLKOUT4 | PLL_158_55 -| clkbufg_4/gopclkbufg | USCM_84_111 | ntclkbufg_4 | 167 | 0 | hdmi_in_clk_ibuf/opit_1 | INCK | IOL_163_6 -| clkbufg_5/gopclkbufg | USCM_84_112 | ntclkbufg_5 | 118 | 0 | cmos1_pclk_ibuf/opit_1 | INCK | IOL_171_6 -| clkbufg_6/gopclkbufg | USCM_84_118 | ntclkbufg_6 | 118 | 0 | cmos2_pclk_ibuf/opit_1 | OUT | IOL_39_6 -| clkbufg_7/gopclkbufg | USCM_84_114 | ntclkbufg_7 | 26 | 0 | u_sys_pll/u_pll_e3/goppll | CLKOUT3 | PLL_158_55 -| u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg | USCM_84_113 | u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin | 68 | 0 | u_sys_pll/u_pll_e3/goppll | CLKOUT1 | PLL_158_55 +| clkbufg_3/gopclkbufg | USCM_84_118 | ntclkbufg_3 | 733 | 0 | U_HDMI_PLL/u_pll_e3/goppll | CLKOUT0 | PLL_158_303 +| clkbufg_4/gopclkbufg | USCM_84_110 | ntclkbufg_4 | 233 | 0 | u_sys_pll/u_pll_e3/goppll | CLKOUT4 | PLL_158_55 +| clkbufg_5/gopclkbufg | USCM_84_111 | ntclkbufg_5 | 167 | 0 | hdmi_in_clk_ibuf/opit_1 | INCK | IOL_163_6 +| clkbufg_6/gopclkbufg | USCM_84_112 | ntclkbufg_6 | 118 | 0 | cmos1_pclk_ibuf/opit_1 | INCK | IOL_171_6 +| clkbufg_7/gopclkbufg | USCM_84_119 | ntclkbufg_7 | 118 | 0 | cmos2_pclk_ibuf/opit_1 | OUT | IOL_39_6 +| clkbufg_8/gopclkbufg | USCM_84_114 | ntclkbufg_8 | 26 | 0 | u_sys_pll/u_pll_e3/goppll | CLKOUT3 | PLL_158_55 +| u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg | USCM_84_113 | u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin | 71 | 0 | u_sys_pll/u_pll_e3/goppll | CLKOUT1 | PLL_158_55 | u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg_gate/gopclkbufg | USCM_84_115 | u_axi_ddr_top/I_ipsxb_ddr_top/ioclk_gate_clk | 1 | 0 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll | CLKOUT1 | PLL_158_199 -| u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg | USCM_84_119 | u_ov5640/coms1_reg_config/clock_20k | 18 | 0 | u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv | Q | CLMA_182_12 -| u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg | USCM_84_120 | u_ov5640/coms2_reg_config/clock_20k | 18 | 0 | u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv | Q | CLMA_182_25 -| udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg | USCM_84_109 | gmii_clk | 1860 | 0 | udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0 | CLKOUT | IOCKDLY_237_367 +| u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg | USCM_84_120 | u_ov5640/coms1_reg_config/clock_20k | 18 | 0 | u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv | Q | CLMS_122_9 +| u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg | USCM_84_121 | u_ov5640/coms2_reg_config/clock_20k | 18 | 0 | u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv | Q | CLMA_122_12 +| udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg | USCM_84_109 | gmii_clk | 1861 | 0 | udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0 | CLKOUT | IOCKDLY_237_367 +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ PLL Clock Info: @@ -284,23 +285,24 @@ PLL Clock Info: | Pll Inst | Site Of Pll Inst | Pin | Net Of Pin | Clock Loads | Non_Clock Loads | Driver(Load) Inst | Driver(Load) Pin | Site Of Driver(Load) Inst +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | U_HDMI_PLL/u_pll_e3/goppll | PLL_158_303 | CLKFB | U_HDMI_PLL/u_pll_e3/ntCLKFB | - | - | U_HDMI_PLL/u_pll_e3/goppll | CLK_INT_FB | PLL_158_303 -| U_HDMI_PLL/u_pll_e3/goppll | PLL_158_303 | CLKIN1 | ntR3907 | - | - | USCMROUTE_0 | CLKOUT | USCM_84_154 -| U_HDMI_PLL/u_pll_e3/goppll | PLL_158_303 | CLKIN2 | ntR2156 | - | - | GND_1215 | Z | HARD0N1_156_305 +| U_HDMI_PLL/u_pll_e3/goppll | PLL_158_303 | CLKIN1 | ntR3950 | - | - | USCMROUTE_0 | CLKOUT | USCM_84_154 +| U_HDMI_PLL/u_pll_e3/goppll | PLL_158_303 | CLKIN2 | ntR2187 | - | - | GND_1222 | Z | HARD0N1_156_305 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll | PLL_158_199 | CLKFB | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/ntCLKFB | - | - | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll | CLK_INT_FB | PLL_158_199 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll | PLL_158_199 | CLKIN1 | u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin | - | - | u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg | CLKOUT | USCM_84_113 -| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll | PLL_158_199 | CLKIN2 | ntR2589 | - | - | GND_482 | Z | HARD0N1_156_197 +| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll | PLL_158_199 | CLKIN2 | ntR2620 | - | - | GND_465 | Z | HARD0N1_156_197 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_1/u_pll_e3/goppll | PLL_158_179 | CLKFB | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_1/u_pll_e3/ntCLKFB | - | - | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_1/u_pll_e3/goppll | CLK_INT_FB | PLL_158_179 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_1/u_pll_e3/goppll | PLL_158_179 | CLKIN1 | u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin | - | - | u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg | CLKOUT | USCM_84_113 -| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_1/u_pll_e3/goppll | PLL_158_179 | CLKIN2 | ntR2593 | - | - | GND_1216 | Z | HARD0N1_156_181 +| u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_1/u_pll_e3/goppll | PLL_158_179 | CLKIN2 | ntR2624 | - | - | GND_1220 | Z | HARD0N1_156_181 | u_sys_pll/u_pll_e3/goppll | PLL_158_55 | CLKFB | u_sys_pll/u_pll_e3/ntCLKFB | - | - | u_sys_pll/u_pll_e3/goppll | CLK_INT_FB | PLL_158_55 | u_sys_pll/u_pll_e3/goppll | PLL_158_55 | CLKIN1 | _N69 | - | - | clk_ibuf/opit_1 | INCK | IOL_327_210 -| u_sys_pll/u_pll_e3/goppll | PLL_158_55 | CLKIN2 | ntR2973 | - | - | GND_1214 | Z | HARD0N1_156_57 +| u_sys_pll/u_pll_e3/goppll | PLL_158_55 | CLKIN2 | ntR3004 | - | - | GND_1221 | Z | HARD0N1_156_57 +| U_HDMI_PLL/u_pll_e3/goppll | PLL_158_303 | CLKOUT0 | zoom_clk | 733 | 0 | ... | ... | ... | U_HDMI_PLL/u_pll_e3/goppll | PLL_158_303 | CLKOUT1 | nt_pix_clk | 1633 | 1 | ... | ... | ... | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll | PLL_158_199 | CLKOUT0_WL | clkout0_wl_0 | 5447 | 0 | ... | ... | ... | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll | PLL_158_199 | CLKOUT1 | u_axi_ddr_top/I_ipsxb_ddr_top/ioclk_gate_clk_pll | 1 | 0 | u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg_gate/gopclkbufg | CLK | USCM_84_115 | u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_1/u_pll_e3/goppll | PLL_158_179 | CLKOUT0_WL | clkout0_wl_1 | 2 | 0 | ... | ... | ... -| u_sys_pll/u_pll_e3/goppll | PLL_158_55 | CLKOUT0 | rd3_clk | 2507 | 0 | ... | ... | ... -| u_sys_pll/u_pll_e3/goppll | PLL_158_55 | CLKOUT1 | zoom_clk | 810 | 0 | ... | ... | ... +| u_sys_pll/u_pll_e3/goppll | PLL_158_55 | CLKOUT0 | rd3_clk | 2506 | 0 | ... | ... | ... +| u_sys_pll/u_pll_e3/goppll | PLL_158_55 | CLKOUT1 | ddr_clk | 77 | 0 | ... | ... | ... | u_sys_pll/u_pll_e3/goppll | PLL_158_55 | CLKOUT3 | clk_25m | 26 | 0 | ... | ... | ... | u_sys_pll/u_pll_e3/goppll | PLL_158_55 | CLKOUT4 | clk_10m | 233 | 0 | ... | ... | ... +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -310,11 +312,11 @@ Device Utilization Summary Of Each Module: +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Module Inst Name | LUT | FF | Distributed RAM | APM | DRM | CRYSTAL | DLL | DQSL | FUSECODE | HSST | IO | IOCKDIV | IOCKDLY | IOCKGATE | IPAL | OSC | PCIE | PLL | RCKB | RESCAL | SCANCHAIN | START | UDID | USCM +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -| multimedia_video_processor | 13929 | 13620 | 88 | 23.5 | 98.5 | 0 | 2 | 8 | 0 | 0 | 180 | 1 | 1 | 4 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 16 +| multimedia_video_processor | 13927 | 13618 | 88 | 23.5 | 98.5 | 0 | 2 | 8 | 0 | 0 | 180 | 1 | 1 | 4 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 17 | + U_HDMI_PLL | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 -| + adjust_color_wrapper_inst | 1127 | 1096 | 0 | 1.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + adjust_color_inst | 1127 | 1018 | 0 | 1.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + convert_hsv2rgb_inst | 69 | 81 | 0 | 1.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + adjust_color_wrapper_inst | 1128 | 1096 | 0 | 1.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + adjust_color_inst | 1128 | 1018 | 0 | 1.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + convert_hsv2rgb_inst | 70 | 81 | 0 | 1.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + convert_rgb2hsv_inst | 1006 | 883 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + divider_inst_h | 415 | 268 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + g_sqrt_stepx[1].u_divider_step | 36 | 23 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 @@ -375,8 +377,8 @@ Device Utilization Summary Of Each Module: | + U_ipml_fifo_ctrl | 61 | 26 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + U_ipml_sdpram | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + vector_to_matrix_inst | 32 | 145 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + image_filiter_inst2 | 946 | 856 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + hybrid_filter_inst | 727 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + image_filiter_inst2 | 945 | 856 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + hybrid_filter_inst | 726 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + gaussian_conv_b | 56 | 83 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + gaussian_conv_g | 65 | 98 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + gaussian_conv_r | 56 | 83 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 @@ -402,35 +404,35 @@ Device Utilization Summary Of Each Module: | + U_ipml_fifo_ctrl | 61 | 26 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + U_ipml_sdpram | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + vector_to_matrix_inst | 32 | 145 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + ms72xx_ctl | 333 | 236 | 0 | 0 | 1.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + iic_dri_rx | 80 | 61 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + iic_dri_tx | 65 | 56 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + ms72xx_ctl | 332 | 236 | 0 | 0 | 1.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + iic_dri_rx | 81 | 61 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + iic_dri_tx | 64 | 56 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + ms7200_ctl | 100 | 54 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + ms7210_ctl | 88 | 62 | 0 | 0 | 0.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + param_manager_inst | 666 | 354 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + ms7210_ctl | 87 | 62 | 0 | 0 | 0.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + param_manager_inst | 672 | 354 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + key_debounce_key_left | 16 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + key_debounce_key_restore | 13 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + key_debounce_key_right | 14 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + param_filiter1_mode | 67 | 34 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + param_filiter1_mode | 69 | 34 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + key_debounce_inst1 | 14 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + key_debounce_inst2 | 14 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + param_filiter2_mode | 8 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + param_modify_H | 51 | 22 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + param_modify_S | 28 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + param_modify_V | 28 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + param_offsetX | 56 | 25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + param_modify_H | 52 | 22 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + param_modify_S | 30 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + param_modify_V | 29 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + param_offsetX | 54 | 25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + param_offsetY | 33 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + param_osd_char_height | 57 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + param_osd_char_width | 32 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + param_osd_char_height | 55 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + param_osd_char_width | 33 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + param_osd_startX | 55 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + param_osd_startY | 32 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + param_rotate | 47 | 21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + param_rotate_A | 33 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + param_rotate | 49 | 21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + param_rotate_A | 34 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + param_zoom | 33 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + u_axi_ddr_top | 5792 | 6000 | 88 | 0 | 30.5 | 0 | 1 | 8 | 0 | 0 | 70 | 1 | 0 | 3 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2 -| + I_ipsxb_ddr_top | 4006 | 4123 | 88 | 0 | 0 | 0 | 1 | 8 | 0 | 0 | 70 | 1 | 0 | 3 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2 +| + u_axi_ddr_top | 5801 | 6000 | 88 | 0 | 30.5 | 0 | 1 | 8 | 0 | 0 | 70 | 1 | 0 | 3 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2 +| + I_ipsxb_ddr_top | 4015 | 4123 | 88 | 0 | 0 | 0 | 1 | 8 | 0 | 0 | 70 | 1 | 0 | 3 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2 | + u_ddrp_rstn_sync | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + u_ddrphy_top | 2351 | 2360 | 0 | 0 | 0 | 0 | 1 | 8 | 0 | 0 | 70 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + u_ddrphy_top | 2363 | 2360 | 0 | 0 | 0 | 0 | 1 | 8 | 0 | 0 | 70 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + ddrphy_calib_top | 323 | 236 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + calib_mux | 23 | 23 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + ddrphy_init | 136 | 92 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 @@ -440,41 +442,41 @@ Device Utilization Summary Of Each Module: | + upcal | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + ddrphy_dfi | 311 | 613 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + ddrphy_dll_update_ctrl | 11 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + ddrphy_info | 98 | 60 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + ddrphy_reset_ctrl | 77 | 60 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + ddrphy_pll_lock_debounce | 44 | 22 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + ddrphy_info | 101 | 60 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + ddrphy_reset_ctrl | 86 | 60 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + ddrphy_pll_lock_debounce | 45 | 22 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_ddrphy_rstn_sync | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_dll_rst_sync | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + ddrphy_slice_top | 1526 | 1371 | 0 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 70 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + i_dqs_group[0].u_ddrphy_data_slice | 478 | 308 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + i_dqs_group[0].u_ddrphy_data_slice | 479 | 308 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + data_slice_dqs_gate_cal | 147 | 69 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + dqs_gate_coarse_cal | 97 | 34 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + gatecal | 50 | 35 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + data_slice_wrlvl | 108 | 76 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + data_slice_wrlvl | 106 | 76 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + dqs_rddata_align | 45 | 74 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + dqsi_rdel_cal | 169 | 84 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + dqsi_rdel_cal | 172 | 84 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + wdata_path_adj | 9 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + i_dqs_group[1].u_ddrphy_data_slice | 332 | 262 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + i_dqs_group[1].u_ddrphy_data_slice | 336 | 262 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + data_slice_dqs_gate_cal | 83 | 61 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + dqs_gate_coarse_cal | 34 | 26 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + gatecal | 49 | 35 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + data_slice_wrlvl | 102 | 68 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + dqs_rddata_align | 44 | 74 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + data_slice_wrlvl | 105 | 68 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + dqs_rddata_align | 45 | 74 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + dqsi_rdel_cal | 98 | 59 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + wdata_path_adj | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + i_dqs_group[2].u_ddrphy_data_slice | 338 | 262 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + data_slice_dqs_gate_cal | 81 | 61 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + i_dqs_group[2].u_ddrphy_data_slice | 334 | 262 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + data_slice_dqs_gate_cal | 82 | 61 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + dqs_gate_coarse_cal | 34 | 26 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + gatecal | 47 | 35 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + data_slice_wrlvl | 107 | 68 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + gatecal | 48 | 35 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + data_slice_wrlvl | 106 | 68 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + dqs_rddata_align | 44 | 74 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + dqsi_rdel_cal | 101 | 59 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + dqsi_rdel_cal | 97 | 59 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + wdata_path_adj | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + i_dqs_group[3].u_ddrphy_data_slice | 341 | 262 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + i_dqs_group[3].u_ddrphy_data_slice | 340 | 262 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + data_slice_dqs_gate_cal | 82 | 61 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + dqs_gate_coarse_cal | 34 | 26 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + gatecal | 48 | 35 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + data_slice_wrlvl | 103 | 68 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + data_slice_wrlvl | 102 | 68 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + dqs_rddata_align | 44 | 74 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + dqsi_rdel_cal | 107 | 59 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + wdata_path_adj | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 @@ -482,15 +484,15 @@ Device Utilization Summary Of Each Module: | + u_logic_rstn_sync | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_slice_rddata_align | 5 | 260 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + ddrphy_training_ctrl | 5 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + u_ipsxb_ddrc_top | 1654 | 1761 | 88 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + u_ipsxb_ddrc_top | 1651 | 1761 | 88 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + mcdq_calib_delay | 0 | 46 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + mcdq_cfg_apb | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + mcdq_dcd_top | 179 | 158 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + mcdq_dcd_top | 178 | 158 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + mcdq_dcd_bm | 128 | 80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + mcdq_dcd_rowaddr | 17 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + mcdq_dcd_sm | 51 | 78 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + mcdq_dcp_top | 854 | 626 | 82 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + mcdq_dcp_back_ctrl | 545 | 406 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + mcdq_dcd_rowaddr | 12 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + mcdq_dcd_sm | 50 | 78 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + mcdq_dcp_top | 852 | 626 | 82 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + mcdq_dcp_back_ctrl | 543 | 406 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + PRE_PASS_LOOP[0].timing_pre_pass | 21 | 13 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + PRE_PASS_LOOP[1].timing_pre_pass | 21 | 13 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + PRE_PASS_LOOP[2].timing_pre_pass | 21 | 13 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 @@ -507,7 +509,7 @@ Device Utilization Summary Of Each Module: | + TRC_LOOP[5].trc_timing | 4 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + TRC_LOOP[6].trc_timing | 4 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + TRC_LOOP[7].trc_timing | 4 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + TRDA2ACT_LOOP[0].trda2act_timing | 8 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + TRDA2ACT_LOOP[0].trda2act_timing | 7 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + TRDA2ACT_LOOP[1].trda2act_timing | 7 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + TRDA2ACT_LOOP[2].trda2act_timing | 7 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + TRDA2ACT_LOOP[3].trda2act_timing | 7 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 @@ -523,15 +525,15 @@ Device Utilization Summary Of Each Module: | + TWRA2ACT_LOOP[5].twra2act_timing | 9 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + TWRA2ACT_LOOP[6].twra2act_timing | 9 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + TWRA2ACT_LOOP[7].twra2act_timing | 9 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + mcdq_timing_rd_pass | 11 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + mcdq_timing_rd_pass | 10 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + tfaw_timing | 26 | 18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + TFAW_LOOP[0].mcdq_tfaw | 7 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + TFAW_LOOP[1].mcdq_tfaw | 7 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + TFAW_LOOP[2].mcdq_tfaw | 7 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + timing_act_pass | 27 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + timing_prea_pass | 15 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + timing_prea_pass | 16 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + timing_ref_pass | 19 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + timing_wr_pass | 9 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + timing_wr_pass | 8 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + mcdq_dcp_buf | 244 | 159 | 82 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + A_ipsxb_distributed_fifo | 83 | 15 | 41 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_ipsxb_distributed_fifo_distributed_fifo_v1_0 | 83 | 15 | 41 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 @@ -551,7 +553,7 @@ Device Utilization Summary Of Each Module: | + u_ipsxb_distributed_fifo_ctr | 31 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + mcdq_ui_axi | 218 | 345 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + mcdq_reg_fifo2 | 96 | 71 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + u_user_cmd_fifo | 41 | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + u_user_cmd_fifo | 42 | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + mcdq_wdatapath | 288 | 475 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + ipsxb_distributed_fifo | 27 | 14 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_ipsxb_distributed_fifo_distributed_fifo_v1_0 | 27 | 14 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 @@ -612,7 +614,7 @@ Device Utilization Summary Of Each Module: | + U_ipml_sdpram | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_axi_rst | 2 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_clk50m_rst | 1 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + u_ddr_addr_ctr | 280 | 434 | 0 | 0 | 0.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + u_ddr_addr_ctr | 277 | 432 | 0 | 0 | 0.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_rd0_addr_ctr | 38 | 43 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_rd1_addr_ctr | 77 | 95 | 0 | 0 | 0.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_rd1_ddr_addr_fifo1 | 42 | 20 | 0 | 0 | 0.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 @@ -630,13 +632,13 @@ Device Utilization Summary Of Each Module: | + u_hdm_in_rst | 2 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_hdmi_in_top | 9 | 79 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_hdmi_rst | 2 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + u_ov5640 | 453 | 504 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 +| + u_ov5640 | 455 | 504 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | + cmos1_8_16bit | 3 | 47 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + cmos2_8_16bit | 3 | 47 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + coms1_reg_config | 61 | 36 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | + u1 | 29 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + coms2_reg_config | 61 | 36 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 -| + u1 | 29 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + coms2_reg_config | 63 | 36 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 +| + u1 | 31 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + power_on_delay_inst | 41 | 37 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_mix_image | 284 | 261 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_mix_fifo1 | 86 | 90 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 @@ -667,9 +669,9 @@ Device Utilization Summary Of Each Module: | + U_ipml_sdpram | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_sync_vg | 91 | 90 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_sys_pll | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 -| + u_zoom_hdmi_fifo | 166 | 139 | 0 | 0 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + U_ipml_fifo_zoom_hdmi_fifo | 166 | 139 | 0 | 0 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + U_ipml_fifo_ctrl | 165 | 138 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + u_zoom_hdmi_fifo | 148 | 139 | 0 | 0 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + U_ipml_fifo_zoom_hdmi_fifo | 148 | 139 | 0 | 0 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + U_ipml_fifo_ctrl | 147 | 138 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + U_ipml_sdpram | 1 | 1 | 0 | 0 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_zoom_image | 430 | 509 | 0 | 16 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + mult_fra0 | 0 | 0 | 0 | 0.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 @@ -707,41 +709,41 @@ Device Utilization Summary Of Each Module: | + zoom_ram3_0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + U_ipml_sdpram_zoom_ram | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_zoom_rst | 1 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + udp_osd_inst | 2209 | 1831 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 11 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 +| + udp_osd_inst | 2212 | 1831 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 11 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | + char_buf_writer_inst | 93 | 56 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + char_osd_inst | 262 | 215 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + char_buf_reader_inst | 175 | 129 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + char_pic_rom_inst | 42 | 47 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + char_buf_reader_inst | 176 | 129 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + char_pic_rom_inst | 41 | 47 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + ascii_char_rom_inst | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + U_ipml_rom_ascii_char_rom | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + U_ipml_spram_ascii_char_rom | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + pixels_shifter_inst | 45 | 39 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + char_ram | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + U_ipml_sdpram_async_ram2048x8_2clk | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + eth_udp_inst | 1818 | 1541 | 0 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 11 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 +| + eth_udp_inst | 1821 | 1541 | 0 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 11 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | + icmp_async_fifo_2048x8b | 97 | 98 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + U_ipml_fifo_async_fifo_2048x8 | 97 | 98 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + U_ipml_fifo_ctrl | 97 | 98 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + U_ipml_sdpram | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + u_arp | 423 | 424 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + u_arp_rx | 215 | 278 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + u_arp | 422 | 424 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + u_arp_rx | 214 | 278 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_arp_tx | 154 | 114 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_crc32_d8 | 54 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_eth_ctrl | 12 | 22 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_gmii_to_rgmii | 0 | 9 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 11 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 -| + u_icmp | 927 | 628 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + u_icmp | 929 | 628 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_crc32_d8 | 55 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_icmp_rx | 288 | 284 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + u_icmp_tx | 584 | 312 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + u_udp | 161 | 185 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + u_udp_rx | 161 | 185 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + u_icmp_tx | 586 | 312 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + u_udp | 163 | 185 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + u_udp_rx | 163 | 185 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + udp_receive_buffer_inst | 193 | 175 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + udp_rx_done_cdc | 3 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + udp_rx_fifo | 107 | 98 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + U_ipml_fifo_async_fifo_2048x8 | 107 | 98 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + U_ipml_fifo_ctrl | 107 | 98 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + U_ipml_sdpram | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + udp_wr_mem_inst | 105 | 190 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + udp_wr_mem_inst | 106 | 190 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -763,7 +765,7 @@ Inputs and Outputs : Flow Command: pnr -fix_hold_violation -Peak memory: 1,902 MB -Total CPU time to pnr completion : 0h:2m:39s -Process Total CPU time to pnr completion : 0h:4m:9s -Total real time to pnr completion : 0h:2m:46s +Peak memory: 1,901 MB +Total CPU time to pnr completion : 0h:2m:59s +Process Total CPU time to pnr completion : 0h:4m:43s +Total real time to pnr completion : 0h:3m:5s diff --git a/project/place_route/multimedia_video_processor_plc.adf b/project/place_route/multimedia_video_processor_plc.adf index d0f2560..66e85ca 100644 Binary files a/project/place_route/multimedia_video_processor_plc.adf and b/project/place_route/multimedia_video_processor_plc.adf differ diff --git a/project/place_route/multimedia_video_processor_pnr.adf b/project/place_route/multimedia_video_processor_pnr.adf index dcffcaf..98ab1c0 100644 Binary files a/project/place_route/multimedia_video_processor_pnr.adf and b/project/place_route/multimedia_video_processor_pnr.adf differ diff --git a/project/place_route/multimedia_video_processor_pnr.netlist b/project/place_route/multimedia_video_processor_pnr.netlist index 2e1b8a1..6395a53 100644 --- a/project/place_route/multimedia_video_processor_pnr.netlist +++ b/project/place_route/multimedia_video_processor_pnr.netlist @@ -246,33 +246,36 @@ L3;1 L4;1 Inst -N24_mux18_3/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -sync_vg_100m/opit_0_inv_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[15]/opit_0_AQ_perm;gopAQ Pin CEOUT;2 +Cout;2 Q;2 RSOUT;2 -Z;2 +Y;2 CE;1 CLK;1 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 +RS;1 + +Inst +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[10]/gateop_perm;gopLUT5 +Pin +Z;2 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -N298_9/gateop_perm;gopLUT5 +N104_mux11_11/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -282,7 +285,7 @@ L3;1 L4;1 Inst -N298_11/gateop_perm;gopLUT5 +N299_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -292,7 +295,7 @@ L3;1 L4;1 Inst -N298_12/gateop_perm;gopLUT5 +N299_12/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -402,20 +405,23 @@ I13;1 I14;1 Inst -N108_0.fsub_11/gateop;gopA +u_ddr_addr_ctr/u_wr1_addr_ctr/wr_addr_valid0/opit_0_L5Q_perm;gopL5Q Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 Inst -N328_9/gateop_perm;gopLUT5 +N119_mux11_11/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -425,7 +431,7 @@ L3;1 L4;1 Inst -N328_11/gateop_perm;gopLUT5 +N329_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -435,7 +441,7 @@ L3;1 L4;1 Inst -N328_10/gateop_perm;gopLUT5 +N329_10/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -564,7 +570,7 @@ Z;2 I;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N106_8/gateop_perm;gopLUT5 +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_24/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -574,7 +580,7 @@ L3;1 L4;1 Inst -N285_10/gateop_perm;gopLUT5 +N286_10/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -584,17 +590,23 @@ L3;1 L4;1 Inst -N285_11/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/dividend_kp[7]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -rstn_1ms[0]/opit_0_inv_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/med[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -610,7 +622,7 @@ L4;1 RS;1 Inst -vs_down_delay_cnt[7]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/rd1_addr_start_fall/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -626,20 +638,7 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/N161.lt_2/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -vs_down_delay_cnt[10]/opit_0_L5Q_perm;gopL5Q +u_ddr_addr_ctr/u_wr0_addr_ctr/wr_sta_reg[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -655,7 +654,7 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/N104_40/gateop_perm;gopLUT5 +u_ov5640/coms1_reg_config/u1/N256_2_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -665,7 +664,17 @@ L3;1 L4;1 Inst -vs_down_delay_cnt[0]/opit_0_L5Q_perm;gopL5Q +N329_11/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +wr0_vs/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -681,14 +690,20 @@ L4;1 RS;1 Inst -N119_mux11_9/gateop_perm;gopLUT5 +vs_down_delay_cnt[7]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst U_HDMI_PLL/u_pll_e3/goppll;gopPLL @@ -863,16 +878,6 @@ RATIOM[6];1 RST;1 RSTODIV;1 -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N241_4_4/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - Inst adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N11/gopapm;gopAPM2 Pin @@ -1057,7 +1062,7 @@ Z[22];1 Z[23];1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N19_mux2_2/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N155_18/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -1067,7 +1072,7 @@ L3;1 L4;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N205_43[6]/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N53_mux2_inv/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -1077,20 +1082,14 @@ L3;1 L4;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N204[4]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N135/gopapm;gopAPM @@ -1426,7 +1425,7 @@ Z[46];1 Z[47];1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -1442,7 +1441,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N205_43[0]/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N204[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -1452,23 +1451,17 @@ L3;1 L4;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N205_43[1]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N205_43[1]/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N205_43[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -1478,7 +1471,7 @@ L3;1 L4;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N204[4]/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N205_43[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -1488,7 +1481,7 @@ L3;1 L4;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N19_inv_1/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N205_43[6]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -1598,23 +1591,17 @@ I13;1 I14;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N205_43[3]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N204[0]/gateop_perm;gopLUT5 +param_manager_inst/param_offsetX/N102_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -1624,14 +1611,36 @@ L3;1 L4;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N205_43[3]/gateop_perm;gopLUT5 +param_manager_inst/key_debounce_key_left/pluse_ms/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 + +Inst +adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/n_ff1[1]/opit_0_L5Q_perm;gopL5Q +Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N205_43[4]/gateop_perm;gopLUT5 @@ -1644,7 +1653,7 @@ L3;1 L4;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N205_51/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N205_45/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -1654,23 +1663,17 @@ L3;1 L4;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/n_ff1[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N204[3]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_filiter1_mode/cnt[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -2526,20 +2529,14 @@ D;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/n_ff1[2]/opit_0_L5Q_perm;gopL5Q @@ -2558,20 +2555,14 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/key_debounce_key_restore/N20_mux4_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/n_ff2[0]/opit_0;gopQ @@ -2936,7 +2927,7 @@ I13;1 I14;1 Inst -param_manager_inst/param_modify_S/N63_mux8_7/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/N133_inv/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -2946,30 +2937,30 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[9]/gateop_perm;gopLUT5 +param_manager_inst/param_modify_V/value[1]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_sync_vg/hdmi_image_data0[13]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/N153_6/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/N153_12/gateop_perm;gopLUT5 @@ -2982,7 +2973,7 @@ L3;1 L4;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/med[5]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/rgb_out[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -3402,20 +3393,7 @@ I13;1 I14;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/N20.fsub_8/gateop;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -3431,7 +3409,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/dividend_kp[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -3447,7 +3425,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/dividend_kp[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/dividend_kp[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -3463,7 +3441,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -3479,7 +3457,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -3495,7 +3473,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/dividend_kp[8]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -3511,7 +3489,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/dividend_kp[8]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -3527,7 +3505,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -3543,7 +3521,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -3575,7 +3553,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -3591,7 +3569,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -3607,7 +3585,20 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/N20.fsub_8/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + +Inst +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -3623,7 +3614,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -3650,7 +3641,7 @@ D;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -3666,7 +3657,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -3682,7 +3673,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/key_debounce_key_right/pressed/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -3698,7 +3689,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -3714,7 +3705,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -3730,7 +3721,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -3746,23 +3737,26 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/remainder[7]/opit_0_AQ_perm;gopAQ Pin CEOUT;2 +Cout;2 Q;2 RSOUT;2 -Z;2 +Y;2 CE;1 CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -3911,7 +3905,7 @@ I13;1 I14;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -3927,7 +3921,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/dividend_kp[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/dividend_kp[8]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -3943,7 +3937,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/dividend_kp[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -3959,7 +3953,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/dividend_kp[8]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/dividend_kp[8]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -3975,7 +3969,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/dividend_kp[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -3991,7 +3985,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/dividend_kp[8]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -4023,7 +4017,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -4039,7 +4033,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -4055,7 +4049,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -4071,7 +4065,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -4087,7 +4081,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -4103,7 +4097,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[6]/opit_0_L5Q;gopL5Q Pin CEOUT;2 Q;2 @@ -4119,7 +4113,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/dividend_kp[11]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -4146,7 +4140,7 @@ D;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -4162,7 +4156,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -4178,7 +4172,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -4194,7 +4188,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -4210,20 +4204,14 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N204[0]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q @@ -4242,20 +4230,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/N20.fsub_8/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -4270,6 +4245,16 @@ L3;1 L4;1 RS;1 +Inst +adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N204[2]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + Inst adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/N6.lt_0/gateop_A2;gopA2 Pin @@ -4404,20 +4389,14 @@ I13;1 I14;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[10]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N205_13/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/dividend_kp[5]/opit_0_L5Q_perm;gopL5Q @@ -4436,7 +4415,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/dividend_kp[8]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/dividend_kp[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -4452,7 +4431,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/dividend_kp[8]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -4468,7 +4447,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -4484,7 +4463,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -4500,7 +4479,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -4516,7 +4495,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -4548,7 +4527,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -4564,7 +4543,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/dividend_kp[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -4580,7 +4559,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -4596,7 +4575,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -4639,7 +4618,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -4655,7 +4634,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -4671,7 +4650,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[8]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -4719,7 +4698,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -4735,20 +4714,17 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/N20.fsub_8/gateop_perm;gopA Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/N6.lt_0/gateop_A2;gopA2 @@ -4884,7 +4860,7 @@ I13;1 I14;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -4900,7 +4876,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/dividend_kp[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/dividend_kp[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -4916,7 +4892,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/dividend_kp[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/dividend_kp[10]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -4932,7 +4908,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -4948,7 +4924,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -4993,7 +4969,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -5009,7 +4985,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -5025,7 +5001,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/modified_h_data[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -5041,23 +5017,17 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_filiter1_mode/N102_8/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -5100,20 +5070,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/N20.fsub_8/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -5129,7 +5086,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/dividend_kp[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/remainder[2]/opit_0_L5Q;gopL5Q Pin CEOUT;2 Q;2 @@ -5145,7 +5102,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -5161,7 +5118,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -5177,7 +5134,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -5193,7 +5150,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/dividend_kp[7]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_modify_H/cnt[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -5208,6 +5165,19 @@ L3;1 L4;1 RS;1 +Inst +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/N20.fsub_8/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + Inst adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/N6.lt_0/gateop_A2;gopA2 Pin @@ -5249,17 +5219,20 @@ I13;1 I14;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/N6.lt_4/gateop;gopA +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 Inst adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/N20.fsub_0/gateop_A2;gopA2 @@ -5342,7 +5315,7 @@ I13;1 I14;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/modified_v_data[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -5358,7 +5331,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -5374,7 +5347,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -5422,7 +5395,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -5438,7 +5411,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -5454,7 +5427,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -5486,7 +5459,7 @@ L4;1 RS;1 Inst -u_sync_vg/hdmi_image_data0[11]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -5502,7 +5475,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -5518,20 +5491,17 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/N6.lt_4/gateop_perm;gopA Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/rdy/opit_0;gopQ @@ -5577,7 +5547,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -5593,7 +5563,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/remainder[3]/opit_0_L5Q;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -5609,7 +5579,20 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/N20.fsub_8/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + +Inst +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -5625,7 +5608,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/remainder[6]/opit_0_L5Q;gopL5Q Pin CEOUT;2 Q;2 @@ -5641,7 +5624,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -5656,19 +5639,6 @@ L3;1 L4;1 RS;1 -Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/N20.fsub_8/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - Inst adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/N6.lt_0/gateop_A2;gopA2 Pin @@ -5803,7 +5773,7 @@ I13;1 I14;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/dividend_kp[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -5819,7 +5789,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -5835,7 +5805,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -5851,7 +5821,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -5867,7 +5837,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -5883,7 +5853,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -5899,7 +5869,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -5915,7 +5885,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -5931,7 +5901,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/dividend_kp[8]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -5963,7 +5933,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -5979,7 +5949,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -6006,7 +5976,7 @@ D;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/dividend_kp[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -6022,20 +5992,23 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/N6.lt_4/gateop_perm;gopA +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -6051,7 +6024,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -6067,7 +6040,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/dividend_kp[8]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -6096,7 +6069,7 @@ I3;1 I4;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -6112,20 +6085,14 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/N133_7/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/N6.lt_0/gateop_A2;gopA2 @@ -6168,20 +6135,17 @@ I13;1 I14;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/N6.lt_4/gateop;gopA Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/N20.fsub_0/gateop_A2;gopA2 @@ -6264,7 +6228,7 @@ I13;1 I14;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -6280,7 +6244,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -6296,7 +6260,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -6328,7 +6292,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -6344,7 +6308,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -6360,7 +6324,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -6376,7 +6340,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -6392,20 +6356,14 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/key_debounce_key_left/N47_13/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q @@ -6424,7 +6382,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -6440,7 +6398,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[7].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -6467,7 +6425,7 @@ D;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -6483,7 +6441,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/quotient[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -6499,7 +6457,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -6515,7 +6473,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/key_debounce_key_left/cnt[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -6531,7 +6489,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -6547,7 +6505,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -6563,7 +6521,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -6579,20 +6537,14 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/key_debounce_key_left/N87/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N6.lt_0/gateop_A2;gopA2 @@ -6728,7 +6680,7 @@ I13;1 I14;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -6744,7 +6696,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -6760,7 +6712,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -6776,7 +6728,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -6792,7 +6744,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -6808,7 +6760,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -6824,7 +6776,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -6840,23 +6792,17 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_modify_H/N63_mux6/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -6888,7 +6834,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/quotient[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[15].u_divider_step/quotient[8]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -6904,7 +6850,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/quotient[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -6931,7 +6877,7 @@ D;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -6947,7 +6893,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/quotient[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -6963,7 +6909,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/quotient[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -6979,7 +6925,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/remainder[3]/opit_0_L5Q;gopL5Q Pin CEOUT;2 Q;2 @@ -6995,7 +6941,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -7011,7 +6957,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -7027,7 +6973,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -7192,7 +7138,7 @@ I13;1 I14;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -7208,7 +7154,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -7224,7 +7170,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/divisor_kp[2]/opit_0_L5Q;gopL5Q Pin CEOUT;2 Q;2 @@ -7240,7 +7186,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -7272,7 +7218,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -7288,7 +7234,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -7304,7 +7250,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -7320,7 +7266,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[15].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -7336,7 +7282,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/quotient[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -7352,7 +7298,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/quotient[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -7368,7 +7314,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/quotient[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -7384,7 +7330,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[7].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -7411,7 +7357,7 @@ D;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -7427,7 +7373,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -7443,7 +7389,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/quotient[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -7459,7 +7405,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -7491,7 +7437,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/n_ff1[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -7507,7 +7453,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -7523,7 +7469,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/quotient[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -7720,7 +7666,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -7736,7 +7682,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -7784,7 +7730,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -7800,7 +7746,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -7816,7 +7762,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -7832,7 +7778,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -7848,7 +7794,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/quotient[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -7864,7 +7810,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/quotient[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -7880,7 +7826,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -7907,7 +7853,7 @@ D;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -7923,7 +7869,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -7939,7 +7885,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -7955,7 +7901,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -8003,7 +7949,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_zoom/value[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -8019,14 +7965,20 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N204[1]/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N6.lt_0/gateop_A2;gopA2 @@ -8162,7 +8114,7 @@ I13;1 I14;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -8178,7 +8130,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/divisor_kp[1]/opit_0_L5Q;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -8194,7 +8146,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -8210,7 +8162,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -8226,7 +8178,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -8242,20 +8194,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/N6.lt_4/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -8271,7 +8210,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -8287,7 +8226,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -8303,7 +8242,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -8319,7 +8258,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -8335,7 +8274,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -8351,7 +8290,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -8367,7 +8306,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -8383,7 +8322,17 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[7]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_filiter1_mode/key_debounce_inst1/N20_mux4_1/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[15].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -8410,7 +8359,7 @@ D;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -8426,23 +8375,17 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q +udp_wr_mem_inst/N364/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -8458,17 +8401,23 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7200_ctl/N2076/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -8484,7 +8433,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -8500,7 +8449,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N204[2]/gateop_perm;gopLUT5 +u_zoom_image/N322_11/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -8510,14 +8459,20 @@ L3;1 L4;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N204[3]/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/quotient[3]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/N6.lt_0/gateop_A2;gopA2 @@ -8560,7 +8515,20 @@ I13;1 I14;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/N6.lt_4/gateop;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + +Inst +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -8576,23 +8544,17 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_zoom/N63_mux9_8/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/quotient[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -8608,7 +8570,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[6]/opit_0_inv_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -8624,7 +8586,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -8640,17 +8602,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N155_18/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/quotient[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -8666,7 +8618,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -8682,17 +8634,23 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[15].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/N6_mux7_8/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/N6_mux7_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -8702,7 +8660,7 @@ L3;1 L4;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/dividend_kp[11]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -8754,7 +8712,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/med[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -8770,7 +8728,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/dividend_kp[8]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/dividend_kp[11]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -8786,23 +8744,26 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/dividend_kp[9]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[7]/opit_0_AQ_perm;gopAQ Pin CEOUT;2 +Cout;2 Q;2 RSOUT;2 -Z;2 +Y;2 CE;1 CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/dividend_kp[10]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/dividend_kp[8]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -8818,7 +8779,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -8834,7 +8795,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/remainder[0]/opit_0_L5Q_perm;gopL5Q +u_zoom_image/data_out_valid1/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -8850,7 +8811,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/dividend_kp[8]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -8866,7 +8827,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -8882,7 +8843,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/dividend_kp[8]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/remainder[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -8898,7 +8859,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -8930,7 +8891,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -8946,23 +8907,17 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/key_debounce_key_right/N20_mux2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/dividend_kp[8]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/key_debounce_key_right/cnt[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -8989,7 +8944,7 @@ D;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -9086,23 +9041,14 @@ I14;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/remainder[7]/opit_0_AQ;gopAQ +param_manager_inst/key_debounce_key_right/N47_6/gateop_perm;gopLUT5 Pin -CEOUT;2 -Cout;2 -Q;2 -RSOUT;2 -Y;2 -CE;1 -CLK;1 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 -RS;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/N6.lt_0/gateop_A2;gopA2 @@ -9238,7 +9184,7 @@ I13;1 I14;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -9254,7 +9200,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -9270,7 +9216,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -9286,7 +9232,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/dividend_kp[8]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/dividend_kp[10]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -9302,7 +9248,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/dividend_kp[11]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/dividend_kp[13]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -9318,7 +9264,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/dividend_kp[12]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -9334,7 +9280,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/dividend_kp[10]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -9366,7 +9312,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/dividend_kp[11]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -9382,20 +9328,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/N20.fsub_8/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -9411,7 +9344,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/divisor_kp[3]/opit_0_L5Q;gopL5Q Pin CEOUT;2 Q;2 @@ -9427,7 +9360,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -9443,7 +9376,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -9459,7 +9392,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -9475,7 +9408,17 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q +u_sync_vg/N126/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -9491,7 +9434,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -9507,7 +9450,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -9539,7 +9482,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[5].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -9555,7 +9498,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -9571,20 +9514,23 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/N20.fsub_8/gateop_perm;gopA +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -9733,7 +9679,7 @@ I13;1 I14;1 Inst -u_sync_vg/hdmi_image_data0[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -9749,7 +9695,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/dividend_kp[10]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/dividend_kp[12]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -9765,20 +9711,23 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/N20.fsub_8/gateop_perm;gopA +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/dividend_kp[10]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -9794,7 +9743,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -9810,14 +9759,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/N25_mux5/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q @@ -9852,7 +9807,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -9884,7 +9839,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -9900,7 +9855,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -9916,7 +9871,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -9932,7 +9887,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/dividend_kp[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -9948,20 +9903,23 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/N20.fsub_8/gateop_perm;gopA +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -9977,7 +9935,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -10009,7 +9967,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/dividend_kp[11]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -10025,7 +9983,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/remainder[5]/opit_0_L5Q;gopL5Q Pin CEOUT;2 Q;2 @@ -10041,7 +9999,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/remainder[6]/opit_0_L5Q;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -10057,7 +10015,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -10206,7 +10164,7 @@ I13;1 I14;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -10222,7 +10180,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/dividend_kp[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -10238,7 +10196,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/dividend_kp[10]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -10254,7 +10212,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/dividend_kp[10]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -10270,7 +10228,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -10318,23 +10276,20 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/N20.fsub_8/gateop_perm;gopA Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/dividend_kp[12]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -10350,7 +10305,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -10366,7 +10321,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -10382,7 +10337,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -10398,7 +10353,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/dividend_kp[13]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -10430,7 +10385,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -10446,7 +10401,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -10478,7 +10433,20 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/N20.fsub_8/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + +Inst +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/dividend_kp[12]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -10494,7 +10462,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -10510,20 +10478,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/N20.fsub_8/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -10672,7 +10627,7 @@ I13;1 I14;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -10688,7 +10643,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/dividend_kp[8]/opit_0_L5Q;gopL5Q Pin CEOUT;2 Q;2 @@ -10704,7 +10659,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -10720,7 +10675,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -10768,17 +10723,23 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/N6_mux7_8/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -10794,7 +10755,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -10810,7 +10771,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -10826,7 +10787,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/dividend_kp[11]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -10842,7 +10803,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/dividend_kp[11]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/dividend_kp[8]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -10858,7 +10819,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -10874,7 +10835,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -10890,7 +10851,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -10906,7 +10867,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -10922,7 +10883,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -10954,7 +10915,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/dividend_kp[10]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -10970,14 +10931,20 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/N6_mux7_7/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/N6.lt_0/gateop_A2;gopA2 @@ -11113,23 +11080,20 @@ I13;1 I14;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/dividend_kp[9]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/N20.fsub_8/gateop;gopA Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/dividend_kp[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -11145,7 +11109,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -11161,7 +11125,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -11177,7 +11141,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -11193,7 +11157,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -11225,7 +11189,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/dividend_kp[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -11241,7 +11205,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -11257,20 +11221,23 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/N20.fsub_8/gateop_perm;gopA +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -11302,7 +11269,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -11318,7 +11285,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -11334,7 +11301,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -11350,7 +11317,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -11366,7 +11333,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -11382,7 +11349,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -11398,7 +11365,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/med[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -11547,7 +11514,20 @@ I13;1 I14;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/N20.fsub_8/gateop;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + +Inst +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -11563,7 +11543,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -11579,23 +11559,17 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q +u_zoom_image/N306_11/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -11611,20 +11585,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[7].u_divider_step/N20.fsub_8/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -11640,7 +11601,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -11656,7 +11617,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/med[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -11672,7 +11633,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/flags[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -11704,7 +11665,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -11720,7 +11681,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -11736,7 +11697,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[7].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -11800,7 +11761,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/quotient[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -11816,7 +11777,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[7].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -11965,7 +11926,7 @@ I13;1 I14;1 Inst -udp_osd_inst/rgb_out[16]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[7].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -11981,7 +11942,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[7].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -12013,7 +11974,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[7].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -12029,7 +11990,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[7].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -12061,7 +12022,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[7].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -12077,7 +12038,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[7].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[7].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -12109,7 +12070,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/quotient[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -12157,7 +12118,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[7].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -12205,7 +12166,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[7].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[7].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -12221,20 +12182,23 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N6.lt_4/gateop_perm;gopA +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[5].u_divider_step/dividend_kp[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -12290,20 +12254,17 @@ I13;1 I14;1 Inst -udp_osd_inst/rgb_out[10]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N6.lt_4/gateop;gopA Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N20_1.fsub_0/gateop_A2;gopA2 @@ -12386,7 +12347,7 @@ I13;1 I14;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -12402,7 +12363,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -12418,7 +12379,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -12434,7 +12395,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[7].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -12450,7 +12411,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -12482,7 +12443,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -12498,7 +12459,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -12514,7 +12475,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -12530,7 +12491,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -12546,7 +12507,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[7].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -12562,7 +12523,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -12578,7 +12539,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -12594,7 +12555,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -12610,7 +12571,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -12626,7 +12587,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -12642,7 +12603,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/dividend_kp[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -12658,7 +12619,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -12807,7 +12768,7 @@ I13;1 I14;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -12823,7 +12784,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -12855,7 +12816,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[7].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -12871,7 +12832,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -12887,7 +12848,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -12903,7 +12864,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -12935,7 +12896,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -12951,7 +12912,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/quotient[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -12967,7 +12928,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -12983,7 +12944,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -13015,7 +12976,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -13031,7 +12992,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[7].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -13047,7 +13008,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -13063,7 +13024,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q +u_zoom_image/wr_addr2[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -13079,7 +13040,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -13095,7 +13056,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[7].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -13244,7 +13205,7 @@ I13;1 I14;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -13260,7 +13221,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -13276,7 +13237,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -13292,7 +13253,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/divisor_kp[3]/opit_0_L5Q;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -13308,7 +13269,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -13324,7 +13285,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/divisor_kp[5]/opit_0_L5Q;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -13372,7 +13333,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -13388,7 +13349,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -13420,7 +13381,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/quotient[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -13436,7 +13397,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -13452,7 +13413,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -13468,7 +13429,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -13484,7 +13445,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -13516,7 +13477,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -13532,7 +13493,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -13548,7 +13509,7 @@ L4;1 RS;1 Inst -u_sync_vg/hdmi_image_data0[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -13713,7 +13674,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -13729,7 +13690,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -13745,7 +13706,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q +u_zoom_image/ram_sta_reg[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -13777,7 +13738,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -13793,7 +13754,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -13809,7 +13770,7 @@ L4;1 RS;1 Inst -u_sync_vg/pixel_show_en1/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -13825,7 +13786,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -13841,7 +13802,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -13857,7 +13818,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/quotient[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/quotient[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -13873,17 +13834,23 @@ L4;1 RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_21/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[6].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/quotient[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -13899,7 +13866,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -13915,7 +13882,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -13931,7 +13898,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -13947,7 +13914,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -13963,7 +13930,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -13979,7 +13946,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -13995,7 +13962,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/remainder[6]/opit_0_L5Q;gopL5Q Pin CEOUT;2 Q;2 @@ -14011,7 +13978,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -14160,7 +14127,7 @@ I13;1 I14;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -14176,7 +14143,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -14192,7 +14159,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -14208,7 +14175,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -14224,7 +14191,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -14240,7 +14207,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -14256,7 +14223,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/quotient[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -14272,7 +14239,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -14288,7 +14255,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -14304,7 +14271,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -14320,7 +14287,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/quotient[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/quotient[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -14336,17 +14303,23 @@ L4;1 RS;1 Inst -N162_mux3/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/quotient[4]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -14362,14 +14335,20 @@ L4;1 RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/rdy/opit_0;gopQ @@ -14383,7 +14362,7 @@ D;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -14399,7 +14378,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -14431,7 +14410,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -14447,7 +14426,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -14463,7 +14442,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -14479,7 +14458,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/offsetY_load/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -14495,7 +14474,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -14644,7 +14623,7 @@ I13;1 I14;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -14660,7 +14639,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -14676,17 +14655,23 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N53_mux2_inv/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -14702,7 +14687,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -14718,7 +14703,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -14734,7 +14719,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -14766,7 +14751,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -14782,7 +14767,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -14798,7 +14783,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/quotient[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -14814,7 +14799,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/quotient[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -14830,7 +14815,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/quotient[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -14846,7 +14831,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/quotient[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/quotient[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -14862,7 +14847,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/quotient[6]/opit_0_L5Q;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -14889,7 +14874,7 @@ D;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -14905,7 +14890,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -14921,7 +14906,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -14937,7 +14922,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -15001,20 +14986,14 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_offsetX/N149/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/N6.lt_0/gateop_A2;gopA2 @@ -15057,20 +15036,17 @@ I13;1 I14;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/N6.lt_4/gateop;gopA Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/N20_1.fsub_0/gateop_A2;gopA2 @@ -15153,7 +15129,7 @@ I13;1 I14;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -15169,7 +15145,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -15185,7 +15161,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -15201,7 +15177,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -15217,7 +15193,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -15233,7 +15209,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/remainder[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -15249,7 +15225,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -15265,7 +15241,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/quotient[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -15281,23 +15257,17 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_modify_V/N139_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[15].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/quotient[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -15313,7 +15283,7 @@ L4;1 RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -15329,23 +15299,17 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/quotient[4]/opit_0_L5Q_perm;gopL5Q +udp_wr_mem_inst/N344/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/quotient[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/quotient[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -15361,7 +15325,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[15].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -15393,14 +15357,20 @@ L4;1 RS;1 Inst -u_sync_vg/N126/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/s_m_data[4]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/rdy/opit_0;gopQ @@ -15414,7 +15384,7 @@ D;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -15430,7 +15400,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_offsetX/value[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -15446,7 +15416,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -15462,7 +15432,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -15478,7 +15448,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/remainder[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/remainder[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -15494,7 +15464,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -15510,7 +15480,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -15526,7 +15496,7 @@ L4;1 RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/offsetX_load/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -15595,7 +15565,7 @@ I3;1 I4;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[15].u_divider_step/quotient[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[15].u_divider_step/quotient[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -15611,7 +15581,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/quotient[5]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[15].u_divider_step/quotient[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -15627,7 +15597,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[15].u_divider_step/quotient[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[15].u_divider_step/quotient[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -15643,7 +15613,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/quotient[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[15].u_divider_step/quotient[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -15659,7 +15629,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[15].u_divider_step/quotient[5]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/index[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -15675,23 +15645,17 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[15].u_divider_step/quotient[6]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_filiter1_mode/key_debounce_inst1/N47_7/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[15].u_divider_step/quotient[8]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[15].u_divider_step/quotient[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -15707,17 +15671,23 @@ L4;1 RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N126_12/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[3]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N126_10/gateop_perm;gopLUT5 +param_manager_inst/param_filiter1_mode/key_debounce_inst1/N20_mux2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -15727,36 +15697,24 @@ L3;1 L4;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/N6_mux7_8/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/rgb_out[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/N6_mux7_7/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/N20.fsub_0/gateop_A2;gopA2 @@ -15779,7 +15737,7 @@ I13;1 I14;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/dividend_kp[10]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/dividend_kp[9]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -15795,7 +15753,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/dividend_kp[10]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/dividend_kp[13]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -15811,17 +15769,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/N153_6/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/dividend_kp[12]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/dividend_kp[11]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -15837,7 +15785,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/dividend_kp[13]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/flags[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -15869,7 +15817,20 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/N20.fsub_8/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + +Inst +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[10]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -15885,7 +15846,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -15901,7 +15862,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[8]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -15917,7 +15878,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/dividend_kp[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -15933,7 +15894,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -15949,7 +15910,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -15965,7 +15926,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/dividend_kp[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -15981,7 +15942,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/divisor_kp[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -15997,7 +15958,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/N20.fsub_8/gateop_perm;gopA +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/N20.fsub_8/gateop_perm;gopA Pin Cout;2 Y;2 @@ -16010,14 +15971,20 @@ I3;1 I4;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/N6_mux7_7/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[2]/opit_0_A2Q21;gopA2Q2 @@ -16101,22 +16068,19 @@ I14;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[7]/opit_0_AQ;gopAQ +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 -Cout;2 Q;2 RSOUT;2 -Y;2 +Z;2 CE;1 CLK;1 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 RS;1 Inst @@ -16224,7 +16188,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/flags[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/med[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -16240,14 +16204,20 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/N140_7/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/med[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/flags_d0[0]/opit_0;gopQ @@ -17417,7 +17387,7 @@ D;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/med[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/flags[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -17433,7 +17403,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/med[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/dividend_kp[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -17449,7 +17419,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/med[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/med[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -17465,39 +17435,27 @@ L4;1 RS;1 Inst -udp_osd_inst/rgb_out[13]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/N140_7/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/med[6]/opit_0_L5Q_perm;gopL5Q +N286_9/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/med[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -17513,7 +17471,7 @@ L4;1 RS;1 Inst -udp_osd_inst/rgb_out[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/med[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -17529,7 +17487,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -17752,7 +17710,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/s_m_data[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/s_m_data[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -17784,20 +17742,14 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/s_m_data[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/N76_7/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/s_m_data[5]/opit_0_L5Q_perm;gopL5Q @@ -17816,7 +17768,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/s_m_data[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/s_m_data[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -17848,7 +17800,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[15].u_divider_step/quotient[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/s_m_data[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -19393,7 +19345,7 @@ D;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/N76_inv/gateop_perm;gopLUT5 +param_manager_inst/param_modify_S/N139_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -19403,7 +19355,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_2/gateop_perm;gopLUT5 +param_manager_inst/param_modify_V/N76_mux8_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -19413,23 +19365,17 @@ L3;1 L4;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[15].u_divider_step/quotient[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/N76_inv/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/N76_7/gateop_perm;gopLUT5 +param_manager_inst/param_modify_S/N63_mux8_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -19656,7 +19602,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 +param_manager_inst/param_modify_H/N102_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -19666,7 +19612,7 @@ L3;1 L4;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/modified_s_data[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/modified_s_data[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -19698,7 +19644,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/modified_s_data[6]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/modified_s_data[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -19714,7 +19660,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/modified_s_data[4]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/modified_s_data[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -19746,7 +19692,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/modified_s_data[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/modified_s_data[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -19762,7 +19708,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/modified_v_data[4]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_filiter1_mode/key_debounce_inst2/change/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -19778,23 +19724,17 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/quotient[0]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_modify_H/N156_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/modified_v_data[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/modified_v_data[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -19842,7 +19782,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/modified_s_data[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/modified_v_data[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -19858,7 +19798,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/modified_v_data[5]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_filiter1_mode/cnt[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -19906,7 +19846,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/modified_s_data[3]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_osd_char_height/cnt[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -21797,7 +21737,13 @@ CLKOUT;2 CLK;1 Inst -clkgate_8/gopclkgate;gopCLKGATE +clkbufg_8/gopclkbufg;gopCLKBUFG +Pin +CLKOUT;2 +CLK;1 + +Inst +clkgate_9/gopclkgate;gopCLKGATE Pin OUT;2 CLK;1 @@ -23005,14 +22951,20 @@ L3;1 L4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N17/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst image_filiter_inst/hybrid_filter_inst/N99.fsub_1/gateop_A2;gopA2 @@ -23055,7 +23007,20 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N15.lt_2/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + +Inst +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -23071,20 +23036,17 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/N39.lt_2/gateop_perm;gopA +param_manager_inst/param_filiter1_mode/N153/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst -param_manager_inst/param_modify_S/N148_2/gateop_perm;gopLUT5 +param_manager_inst/param_filiter2_mode/N152_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -23094,7 +23056,7 @@ L3;1 L4;1 Inst -image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/N39_0_ac5/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -23104,7 +23066,7 @@ L3;1 L4;1 Inst -image_filiter_inst/hybrid_filter_inst/N134_72/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N104_40/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -23174,7 +23136,7 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/N162_72/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N17/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -23184,7 +23146,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/N162_76/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -23194,7 +23156,7 @@ L3;1 L4;1 Inst -image_filiter_inst/hybrid_filter_inst/N162_76/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -23203,6 +23165,19 @@ L2;1 L3;1 L4;1 +Inst +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N4.lt_2/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + Inst image_filiter_inst/hybrid_filter_inst/N155.fsub_1/gateop_A2;gopA2 Pin @@ -23244,27 +23219,7 @@ I13;1 I14;1 Inst -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[0]/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/N39_0_ac4/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -23274,17 +23229,20 @@ L3;1 L4;1 Inst -udp_wr_mem_inst/N424/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N5.lt_2/gateop_perm;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/N39_0_maj3/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/N176_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -23294,7 +23252,7 @@ L3;1 L4;1 Inst -image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/N39_0_ac5/gateop;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[7]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -23304,7 +23262,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_filiter1_mode/N102_11/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/N39_0_maj3/gateop;gopLUT5 Pin Z;2 L0;1 @@ -24591,7 +24549,7 @@ I4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N15.lt_2/gateop_perm;gopA +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N8.lt_2/gateop_perm;gopA Pin Cout;2 Y;2 @@ -24604,20 +24562,17 @@ I3;1 I4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N4.lt_2/gateop_perm;gopA +image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/N39_0_ac6/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst -u_hdm_in_rst/N0/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N68_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -24627,17 +24582,14 @@ L3;1 L4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N5.lt_2/gateop_perm;gopA +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N68_7/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/N47_1_1/gateop_A2;gopA2 @@ -25032,14 +24984,23 @@ I14;1 RS;1 Inst -u_ddr_addr_ctr/u_rd1_addr_ctr/N259/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/m_result_data[5]/opit_0_AQ;gopAQ Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +CEOUT;2 +Cout;2 +Q;2 +RSOUT;2 +Y;2 +CE;1 +CLK;1 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 +RS;1 Inst image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][0][0]/opit_0;gopQ @@ -26124,7 +26085,7 @@ I14;1 RS;1 Inst -u_ddr_addr_ctr/u_rd1_addr_ctr/N56/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/N39_0_maj3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -26134,17 +26095,20 @@ L3;1 L4;1 Inst -image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/N39_0_maj3/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N5.lt_2/gateop_perm;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N12[0]/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/N39_0_ac5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -27462,17 +27426,20 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/N155.lt_2/gateop_perm;gopA +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 Inst image_filiter_inst/hybrid_filter_inst/median_finder9_b/N37.lt_0/gateop_A2;gopA2 @@ -27495,17 +27462,20 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/N35.lt_2/gateop_perm;gopA +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 Inst image_filiter_inst/hybrid_filter_inst/median_finder9_b/N39.lt_0/gateop_A2;gopA2 @@ -27528,20 +27498,14 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q +u_ov5640/coms1_reg_config/N8_mux4_5/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst image_filiter_inst/hybrid_filter_inst/median_finder9_b/N83.lt_0/gateop_A2;gopA2 @@ -27564,7 +27528,7 @@ I13;1 I14;1 Inst -clk_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -27600,7 +27564,7 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -27636,17 +27600,20 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N68_10_1/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_b/N87.lt_2/gateop;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/N83.lt_2/gateop_perm;gopA +image_filiter_inst/hybrid_filter_inst/median_finder9_b/N155.lt_2/gateop_perm;gopA Pin Cout;2 Y;2 @@ -27679,7 +27646,7 @@ I13;1 I14;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N55_11_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -27709,17 +27676,14 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/N161.lt_2/gateop_perm;gopA +image_filiter_inst/hybrid_filter_inst/N146_mux2_3/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst image_filiter_inst/hybrid_filter_inst/median_finder9_b/N111.lt_0/gateop_A2;gopA2 @@ -27742,17 +27706,14 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/N107.lt_2/gateop_perm;gopA +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N55_9/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst image_filiter_inst/hybrid_filter_inst/median_finder9_b/N155.lt_0/gateop_A2;gopA2 @@ -27775,7 +27736,7 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/N188_40/gateop_perm;gopLUT5 +u_ov5640/coms1_reg_config/N12/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -27805,7 +27766,7 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/N167.lt_2/gateop_perm;gopA +image_filiter_inst/hybrid_filter_inst/median_finder9_b/N39.lt_2/gateop_perm;gopA Pin Cout;2 Y;2 @@ -27838,36 +27799,24 @@ I13;1 I14;1 Inst -u_ov5640/cmos1_8_16bit/de_cnt/opit_0_L5Q_perm;gopL5Q +u_hdmi_in_top/N3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_ov5640/u_mix_image/cnt0_w[8]/opit_0_L5Q_perm;gopL5Q +N104_mux11_9/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N4.lt_0/gateop_A2;gopA2 @@ -27890,14 +27839,17 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N17/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_b/N109.lt_2/gateop_perm;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N5.lt_0/gateop_A2;gopA2 @@ -27920,14 +27872,17 @@ I13;1 I14;1 Inst -u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/N155.fsub_5/gateop_perm;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N8.lt_0/gateop_A2;gopA2 @@ -27950,14 +27905,17 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N55_7/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_b/N111.lt_2/gateop_perm;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N15.lt_0/gateop_A2;gopA2 @@ -27980,59 +27938,30 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N68_14_1/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q -Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 - -Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N55_11_1/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N4.lt_2/gateop_perm;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N17/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N8.lt_2/gateop_perm;gopA +image_filiter_inst/hybrid_filter_inst/median_finder9_b/N167.lt_2/gateop_perm;gopA Pin Cout;2 Y;2 @@ -28045,7 +27974,7 @@ I3;1 I4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N8.lt_2/gateop_perm;gopA +image_filiter_inst/hybrid_filter_inst/median_finder9_b/N107.lt_2/gateop_perm;gopA Pin Cout;2 Y;2 @@ -28057,6 +27986,32 @@ I2;1 I3;1 I4;1 +Inst +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N68_14_1/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q +Pin +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 + Inst image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[0]/opit_0_MUX4TO1Q;gopMUX4TO1Q Pin @@ -28175,23 +28130,7 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q -Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 - -Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -28217,7 +28156,7 @@ L3;1 L4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -28233,7 +28172,7 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -28249,7 +28188,7 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -28265,7 +28204,7 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N5.lt_2/gateop_perm;gopA +image_filiter_inst/hybrid_filter_inst/median_finder9_b/N37.lt_2/gateop_perm;gopA Pin Cout;2 Y;2 @@ -28278,7 +28217,20 @@ I3;1 I4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N8.lt_2/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + +Inst +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -28314,7 +28266,7 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N68_14_1/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[5]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -28344,7 +28296,7 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N17/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -28374,17 +28326,20 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N4.lt_2/gateop_perm;gopA +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 Inst image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N15.lt_0/gateop_A2;gopA2 @@ -28407,39 +28362,30 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N5.lt_2/gateop_perm;gopA Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N55_9/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N55_11_1/gateop_perm;gopLUT5 +u_ov5640/power_on_delay_inst/N15_mux15_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -28449,23 +28395,30 @@ L3;1 L4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N15.lt_2/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + +Inst +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N68_7/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/rd1_data_valid0/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -28480,16 +28433,6 @@ L3;1 L4;1 RS;1 -Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N402_78/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - Inst image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[0]/opit_0_MUX4TO1Q;gopMUX4TO1Q Pin @@ -28576,20 +28519,7 @@ S0;1 S1;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/N87.lt_2/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -28637,7 +28567,7 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N15.lt_2/gateop_perm;gopA +image_filiter_inst/hybrid_filter_inst/median_finder9_b/N161.lt_2/gateop_perm;gopA Pin Cout;2 Y;2 @@ -28649,6 +28579,16 @@ I2;1 I3;1 I4;1 +Inst +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N68_1/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + Inst image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q Pin @@ -28666,17 +28606,23 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N55_9/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_ioclk_gate/opit_0_inv_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -28692,7 +28638,7 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/N104_40/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N17/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -28702,20 +28648,17 @@ L3;1 L4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_b/N35.lt_2/gateop_perm;gopA Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N4.lt_0/gateop_A2;gopA2 @@ -28738,20 +28681,17 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N15.lt_2/gateop_perm;gopA Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N5.lt_0/gateop_A2;gopA2 @@ -28774,14 +28714,20 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N55_9/gateop_perm;gopLUT5 +image_filiter_inst/vector_to_matrix_inst/mat[0][2][0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N8.lt_0/gateop_A2;gopA2 @@ -28804,20 +28750,14 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N55_9/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N15.lt_0/gateop_A2;gopA2 @@ -28840,17 +28780,7 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N68_7/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N17/gateop;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N17/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -28860,7 +28790,7 @@ L3;1 L4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N4.lt_2/gateop_perm;gopA +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N8.lt_2/gateop_perm;gopA Pin Cout;2 Y;2 @@ -28873,7 +28803,7 @@ I3;1 I4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -28889,17 +28819,20 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N68_14_1/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N4.lt_2/gateop_perm;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N5.lt_2/gateop_perm;gopA +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N15.lt_2/gateop_perm;gopA Pin Cout;2 Y;2 @@ -28911,6 +28844,22 @@ I2;1 I3;1 I4;1 +Inst +image_filiter_inst/vector_to_matrix_inst/mat[0][0][3]/opit_0_L5Q_perm;gopL5Q +Pin +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 + Inst image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[0]/opit_0_MUX4TO1Q;gopMUX4TO1Q Pin @@ -28997,7 +28946,7 @@ S0;1 S1;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -29013,7 +28962,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[38]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -29029,7 +28978,7 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -29045,20 +28994,7 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N15.lt_2/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -29074,7 +29010,7 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -29090,7 +29026,20 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_b/N83.lt_2/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + +Inst +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -29106,7 +29055,7 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/N37.lt_2/gateop_perm;gopA +image_filiter_inst/hybrid_filter_inst/median_finder9_b/N85.lt_2/gateop_perm;gopA Pin Cout;2 Y;2 @@ -29119,30 +29068,36 @@ I3;1 I4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/N39.lt_2/gateop_perm;gopA +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/N85.lt_2/gateop_perm;gopA +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 Inst image_filiter_inst/hybrid_filter_inst/median_finder9_b/max[0]/opit_0;gopQ @@ -29785,7 +29740,7 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -29821,7 +29776,7 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/N37.lt_2/gateop;gopA +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N155.lt_2/gateop_perm;gopA Pin Cout;2 Y;2 @@ -29887,7 +29842,7 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/N188_40/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N55_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -29917,20 +29872,17 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_g/N85.lt_2/gateop;gopA Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst image_filiter_inst/hybrid_filter_inst/median_finder9_g/N87.lt_0/gateop_A2;gopA2 @@ -29953,23 +29905,20 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_g/N87.lt_2/gateop;gopA Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/N85.lt_2/gateop_perm;gopA +image_filiter_inst/hybrid_filter_inst/median_finder9_g/N83.lt_2/gateop_perm;gopA Pin Cout;2 Y;2 @@ -30002,14 +29951,20 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/N114_mux5_4/gateop_perm;gopLUT5 +image_filiter_inst/vector_to_matrix_inst/mat[0][0][8]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst image_filiter_inst/hybrid_filter_inst/median_finder9_g/N109.lt_0/gateop_A2;gopA2 @@ -30032,14 +29987,17 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/N39_0_ac5/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N4.lt_2/gateop_perm;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst image_filiter_inst/hybrid_filter_inst/median_finder9_g/N111.lt_0/gateop_A2;gopA2 @@ -30062,20 +30020,17 @@ I13;1 I14;1 Inst -image_filiter_inst/vector_to_matrix_inst/mat[0][2][15]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_g/N111.lt_2/gateop;gopA Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst image_filiter_inst/hybrid_filter_inst/median_finder9_g/N155.lt_0/gateop_A2;gopA2 @@ -30098,7 +30053,7 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/N167.lt_2/gateop_perm;gopA +image_filiter_inst/hybrid_filter_inst/median_finder9_g/N161.lt_2/gateop_perm;gopA Pin Cout;2 Y;2 @@ -30131,20 +30086,14 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/N114_mux5_4/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst image_filiter_inst/hybrid_filter_inst/median_finder9_g/N167.lt_0/gateop_A2;gopA2 @@ -30167,23 +30116,20 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_g/N35.lt_2/gateop_perm;gopA Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N68_10_1/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/N118_mux3_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -30213,20 +30159,14 @@ I13;1 I14;1 Inst -image_filiter_inst/vector_to_matrix_inst/mat[0][0][5]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N55_9/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N5.lt_0/gateop_A2;gopA2 @@ -30249,7 +30189,7 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N4.lt_2/gateop_perm;gopA +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N5.lt_2/gateop;gopA Pin Cout;2 Y;2 @@ -30282,14 +30222,20 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N55_11_1/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N15.lt_0/gateop_A2;gopA2 @@ -30312,23 +30258,17 @@ I13;1 I14;1 Inst -image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_b/N104_40/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N55_9/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N55_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -30338,23 +30278,20 @@ L3;1 L4;1 Inst -image_filiter_inst/vector_to_matrix_inst/mat[0][0][6]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N15.lt_2/gateop_perm;gopA Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N68_10_1/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_b/N188_40/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -30364,7 +30301,7 @@ L3;1 L4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N68_14_1/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N68_10_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -30492,20 +30429,7 @@ S0;1 S1;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N5.lt_2/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -30521,7 +30445,7 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -30537,17 +30461,23 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/N118_mux3_4/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[5]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -30563,7 +30493,7 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -30594,6 +30524,16 @@ L3;1 L4;1 RS;1 +Inst +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N55_11_1/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + Inst image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[5]/opit_0_L5Q_perm;gopL5Q Pin @@ -30611,33 +30551,17 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/N107.lt_2/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N15.lt_2/gateop_perm;gopA +image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/N39_0_maj3/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -30665,6 +30589,19 @@ I2;1 I3;1 I4;1 +Inst +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N4.lt_2/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + Inst image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N4.lt_0/gateop_A2;gopA2 Pin @@ -30686,20 +30623,14 @@ I13;1 I14;1 Inst -u_ddr_addr_ctr/u_rd1_addr_ctr/rd1_sta_reg[0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N55_9/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N5.lt_0/gateop_A2;gopA2 @@ -30722,7 +30653,7 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/N109.lt_2/gateop_perm;gopA +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N5.lt_2/gateop;gopA Pin Cout;2 Y;2 @@ -30755,7 +30686,7 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/N39_0_maj3/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/N134_78/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -30785,7 +30716,7 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/N39_0_ac6/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -30795,7 +30726,7 @@ L3;1 L4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N17/gateop;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N55_11_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -30805,7 +30736,7 @@ L3;1 L4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N55_11_1/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/N39_0_ac4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -30815,7 +30746,17 @@ L3;1 L4;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N5.lt_2/gateop_perm;gopA +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N68_7/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N8.lt_2/gateop_perm;gopA Pin Cout;2 Y;2 @@ -30828,30 +30769,17 @@ I3;1 I4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N68_14_1/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N4.lt_2/gateop_perm;gopA Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[0]/opit_0_MUX4TO1Q;gopMUX4TO1Q @@ -30972,20 +30900,14 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N68_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q @@ -31004,7 +30926,7 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -31020,7 +30942,7 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[5]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -31036,20 +30958,14 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[5]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/N134_72/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q @@ -31068,7 +30984,20 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N15.lt_2/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + +Inst +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -31084,17 +31013,23 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N55_9/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -31110,27 +31045,20 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N8.lt_2/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/N39_0_ac4/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N4.lt_0/gateop_A2;gopA2 @@ -31153,14 +31081,20 @@ I13;1 I14;1 Inst -u_axi_ddr_top/N866_2_and[32][0]_1/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[5]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N5.lt_0/gateop_A2;gopA2 @@ -31183,14 +31117,20 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N55_9/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[5]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N8.lt_0/gateop_A2;gopA2 @@ -31213,20 +31153,14 @@ I13;1 I14;1 Inst -u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_image_fram_cnt1[0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N68_14_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N15.lt_0/gateop_A2;gopA2 @@ -31249,53 +31183,49 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N15.lt_2/gateop;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N17/gateop;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N8.lt_2/gateop_perm;gopA +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N55_9/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N68_10_1/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_image_fram_cnt1[1]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -31311,7 +31241,17 @@ L4;1 RS;1 Inst -u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/data_vary0/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N17/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +image_filiter_inst/vector_to_matrix_inst/mat[0][0][9]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -31429,23 +31369,17 @@ S0;1 S1;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N68_10_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -31477,7 +31411,7 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[5]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -31493,33 +31427,43 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_g/N104_40/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_ddr_addr_ctr/u_rd1_addr_ctr/N16/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N15.lt_2/gateop_perm;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_g/N109.lt_2/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + +Inst +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -31535,7 +31479,7 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -31551,26 +31495,7 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/m_result_data[5]/opit_0_AQ_perm;gopAQ -Pin -CEOUT;2 -Cout;2 -Q;2 -RSOUT;2 -Y;2 -CE;1 -CLK;1 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 -RS;1 - -Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -31586,7 +31511,7 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[5]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/vector_to_matrix_inst/mat[0][0][7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -31602,7 +31527,7 @@ L4;1 RS;1 Inst -u_ddr_addr_ctr/u_rd1_addr_ctr/rd_vs_rise0/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -32382,7 +32307,7 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/N161.lt_2/gateop_perm;gopA +image_filiter_inst/hybrid_filter_inst/median_finder9_r/N39.lt_2/gateop_perm;gopA Pin Cout;2 Y;2 @@ -32415,14 +32340,20 @@ I13;1 I14;1 Inst -param_manager_inst/param_offsetX/N63_mux6_7/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst image_filiter_inst/hybrid_filter_inst/median_finder9_r/N39.lt_0/gateop_A2;gopA2 @@ -32445,14 +32376,20 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N55_9/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst image_filiter_inst/hybrid_filter_inst/median_finder9_r/N83.lt_0/gateop_A2;gopA2 @@ -32475,17 +32412,20 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/N155.lt_2/gateop_perm;gopA +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 Inst image_filiter_inst/hybrid_filter_inst/median_finder9_r/N85.lt_0/gateop_A2;gopA2 @@ -32541,17 +32481,20 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/N86_mux4_3/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_r/N85.lt_2/gateop_perm;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/N104_40/gateop;gopLUT5 +image_filiter_inst/hybrid_filter_inst/N106_72/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -32614,7 +32557,7 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -32650,14 +32593,20 @@ I13;1 I14;1 Inst -param_manager_inst/param_modify_S/N156_1/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst image_filiter_inst/hybrid_filter_inst/median_finder9_r/N155.lt_0/gateop_A2;gopA2 @@ -32680,7 +32629,7 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/pll_lock_d[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -32716,17 +32665,20 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N15.lt_2/gateop_perm;gopA +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_b_neg/opit_0_inv_L5Q_perm;gopL5Q Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 Inst image_filiter_inst/hybrid_filter_inst/median_finder9_r/N167.lt_0/gateop_A2;gopA2 @@ -32749,30 +32701,27 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_r/N104_40/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/N188_40/gateop;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N8.lt_2/gateop_perm;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N4.lt_0/gateop_A2;gopA2 @@ -32795,20 +32744,14 @@ I13;1 I14;1 Inst -image_filiter_inst/vector_to_matrix_inst/mat[0][0][11]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N68_14_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N5.lt_0/gateop_A2;gopA2 @@ -32831,14 +32774,20 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N55_11_1/gateop_perm;gopLUT5 +image_filiter_inst/vector_to_matrix_inst/mat[0][0][12]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N8.lt_0/gateop_A2;gopA2 @@ -32861,7 +32810,7 @@ I13;1 I14;1 Inst -image_filiter_inst/vector_to_matrix_inst/mat[0][2][11]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -32897,81 +32846,60 @@ I13;1 I14;1 Inst -image_filiter_inst/vector_to_matrix_inst/mat[0][0][13]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N55_11_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N55_9/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N5.lt_2/gateop_perm;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N68_10_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N55_9/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N17/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_rotate_image/rotate_sta_reg[2]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/vector_to_matrix_inst/mat[0][0][13]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -33072,23 +33000,20 @@ S0;1 S1;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N15.lt_2/gateop_perm;gopA Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -33120,7 +33045,7 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -33136,7 +33061,20 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N4.lt_2/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + +Inst +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -33152,7 +33090,7 @@ L4;1 RS;1 Inst -u_rotate_image/rotate_sta_reg[0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -33168,36 +33106,17 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/N86_mux4_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/N37.lt_2/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -u_rotate_image/rotate_sta_reg[1]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -33213,7 +33132,7 @@ L4;1 RS;1 Inst -u_rotate_image/N57_mux6_2/gateop_perm;gopLUT5 +u_rotate_image/N144_mux4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -33243,7 +33162,7 @@ I13;1 I14;1 Inst -u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N55_11_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -33303,14 +33222,17 @@ I13;1 I14;1 Inst -u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N4.lt_2/gateop_perm;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N15.lt_0/gateop_A2;gopA2 @@ -33333,20 +33255,17 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N5.lt_2/gateop_perm;gopA +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N17/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N55_11_1/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N68_10_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -33356,20 +33275,17 @@ L3;1 L4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N4.lt_2/gateop_perm;gopA +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N17/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst -image_filiter_inst/hybrid_filter_inst/N99.fsub_5/gateop_perm;gopA +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N5.lt_2/gateop_perm;gopA Pin Cout;2 Y;2 @@ -33392,7 +33308,7 @@ L3;1 L4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -33493,20 +33409,17 @@ S0;1 S1;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_r/N167.lt_2/gateop_perm;gopA Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q @@ -33525,7 +33438,7 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -33541,7 +33454,7 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -33557,7 +33470,7 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N15.lt_2/gateop_perm;gopA +image_filiter_inst/hybrid_filter_inst/median_finder9_r/N87.lt_2/gateop_perm;gopA Pin Cout;2 Y;2 @@ -33570,17 +33483,23 @@ I3;1 I4;1 Inst -u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -33596,14 +33515,20 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/N106_76/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q @@ -33622,7 +33547,7 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N5.lt_2/gateop_perm;gopA +image_filiter_inst/hybrid_filter_inst/median_finder9_r/N37.lt_2/gateop_perm;gopA Pin Cout;2 Y;2 @@ -33655,7 +33580,7 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N17/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N55_11_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -33685,14 +33610,20 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/N39_0_ac4/gateop_perm;gopLUT5 +image_filiter_inst/vector_to_matrix_inst/mat[0][0][11]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N8.lt_0/gateop_A2;gopA2 @@ -33715,14 +33646,17 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N55_11_1/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N5.lt_2/gateop_perm;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N15.lt_0/gateop_A2;gopA2 @@ -33745,7 +33679,7 @@ I13;1 I14;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N55_9/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N68_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -33755,33 +33689,17 @@ L3;1 L4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/N109.lt_2/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N4.lt_2/gateop_perm;gopA +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N55_9/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -33797,7 +33715,7 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N68_10_1/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N68_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -33807,14 +33725,33 @@ L3;1 L4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N68_10_1/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 + +Inst +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N4.lt_2/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/max[0]/opit_0_MUX4TO1Q;gopMUX4TO1Q @@ -33902,7 +33839,7 @@ S0;1 S1;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/vector_to_matrix_inst/mat[0][2][14]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -33918,7 +33855,20 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N8.lt_2/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + +Inst +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -33950,23 +33900,20 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/opit_0_L5Q;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_r/N107.lt_2/gateop_perm;gopA Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -33982,33 +33929,7 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N8.lt_2/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/N167.lt_2/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -34040,7 +33961,20 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/N87.lt_2/gateop_perm;gopA +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N15.lt_2/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + +Inst +image_filiter_inst/hybrid_filter_inst/median_finder9_r/N109.lt_2/gateop_perm;gopA Pin Cout;2 Y;2 @@ -35713,17 +35647,7 @@ I13;1 I14;1 Inst -image_filiter_inst/multiline_buffer_inst/N93_mux7_14/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_rotate_image/N52_mux6_6/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/N271/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -35733,7 +35657,7 @@ L3;1 L4;1 Inst -image_filiter_inst/multiline_buffer_inst/N48/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/N199_mux5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -35743,7 +35667,7 @@ L3;1 L4;1 Inst -image_filiter_inst/multiline_buffer_inst/N271/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/N229_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -35753,7 +35677,7 @@ L3;1 L4;1 Inst -u_rotate_image/N52_mux6_7/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/N269_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -35763,17 +35687,23 @@ L3;1 L4;1 Inst -image_filiter_inst/multiline_buffer_inst/N216/gateop_perm;gopLUT5 +image_filiter_inst2/vector_to_matrix_inst/mat[0][0][0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -image_filiter_inst/multiline_buffer_inst/N176_15/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/N236_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -35783,7 +35713,7 @@ L3;1 L4;1 Inst -image_filiter_inst/multiline_buffer_inst/N176_12/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/N176_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -35793,7 +35723,7 @@ L3;1 L4;1 Inst -image_filiter_inst/multiline_buffer_inst/N236_4/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/N189[1]_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -35803,7 +35733,7 @@ L3;1 L4;1 Inst -image_filiter_inst/multiline_buffer_inst/N179_mux8_9/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -35813,7 +35743,7 @@ L3;1 L4;1 Inst -image_filiter_inst/multiline_buffer_inst/ver_cnt[0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/multiline_buffer_inst/ver_cnt[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -35829,17 +35759,23 @@ L4;1 RS;1 Inst -image_filiter_inst/multiline_buffer_inst/N199_mux5/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/tail_ver_cnt[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -image_filiter_inst/multiline_buffer_inst/N236_3/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/N142_mux4_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -35849,23 +35785,17 @@ L3;1 L4;1 Inst -image_filiter_inst/multiline_buffer_inst/m_pixel_valid/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N55_11_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/N229_11/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -35875,17 +35805,23 @@ L3;1 L4;1 Inst -image_filiter_inst/multiline_buffer_inst/N229_11/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/hor_cnt[10]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -image_filiter_inst/multiline_buffer_inst/hor_cnt[0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/multiline_buffer_inst/ver_cnt[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -35901,7 +35837,7 @@ L4;1 RS;1 Inst -image_filiter_inst/multiline_buffer_inst/N272/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/N236_11/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -35911,7 +35847,7 @@ L3;1 L4;1 Inst -image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/N39_0_ac5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -35921,7 +35857,7 @@ L3;1 L4;1 Inst -image_filiter_inst/multiline_buffer_inst/N269_5/gateop;gopLUT5 +image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -35931,7 +35867,7 @@ L3;1 L4;1 Inst -image_filiter_inst/multiline_buffer_inst/N189[1]_4/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/N272/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -35941,23 +35877,30 @@ L3;1 L4;1 Inst -image_filiter_inst/multiline_buffer_inst/ver_cnt[3]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[0]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N35.lt_2/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + +Inst +image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -35967,7 +35910,7 @@ L3;1 L4;1 Inst -image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -35977,23 +35920,17 @@ L3;1 L4;1 Inst -image_filiter_inst/multiline_buffer_inst/hor_cnt[8]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst/multiline_buffer_inst/N229_8/gateop_perm;gopLUT5 +u_axi_ddr_top/N928_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -36003,7 +35940,7 @@ L3;1 L4;1 Inst -image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -36023,7 +35960,7 @@ L3;1 L4;1 Inst -image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -36033,7 +35970,7 @@ L3;1 L4;1 Inst -image_filiter_inst/multiline_buffer_inst/N229_9/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -36053,7 +35990,7 @@ L3;1 L4;1 Inst -image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[11]/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -36063,7 +36000,7 @@ L3;1 L4;1 Inst -image_filiter_inst/multiline_buffer_inst/N176_2/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[11]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -36073,7 +36010,7 @@ L3;1 L4;1 Inst -image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[11]/gateop_perm;gopLUT5 +u_axi_ddr_top/N866_2_and[25][0]_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -36093,7 +36030,7 @@ L3;1 L4;1 Inst -image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[2]/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[3]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -36103,7 +36040,7 @@ L3;1 L4;1 Inst -image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[3]/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -36113,7 +36050,7 @@ L3;1 L4;1 Inst -image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[8]/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[11]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -36123,17 +36060,23 @@ L3;1 L4;1 Inst -image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[5]/gateop_perm;gopLUT5 +u_ov5640/power_on_delay_inst/cnt2[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[6]/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[7]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -36143,7 +36086,7 @@ L3;1 L4;1 Inst -image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[7]/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[8]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -36153,20 +36096,14 @@ L3;1 L4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[6]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[9]/gateop_perm;gopLUT5 @@ -36189,23 +36126,17 @@ L3;1 L4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/N743_8/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst/vector_to_matrix_inst/mat[0][0][2]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -36509,14 +36440,20 @@ I14;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N17/gateop_perm;gopLUT5 +u_axi_ddr_top/cnt1_times[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21;gopA2Q2 @@ -37159,7 +37096,7 @@ WR_EOP;1 WR_ERR;1 Inst -image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -37169,7 +37106,7 @@ L3;1 L4;1 Inst -image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -37179,7 +37116,7 @@ L3;1 L4;1 Inst -image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[5]/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -37189,17 +37126,20 @@ L3;1 L4;1 Inst -image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N83.lt_2/gateop_perm;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -37219,17 +37159,23 @@ L3;1 L4;1 Inst -image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 +image_filiter_inst/vector_to_matrix_inst/mat[0][0][1]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[7]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -37239,7 +37185,7 @@ L3;1 L4;1 Inst -image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -37249,7 +37195,7 @@ L3;1 L4;1 Inst -image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[11]/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[9]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -37259,23 +37205,17 @@ L3;1 L4;1 Inst -image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[11]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -ms72xx_ctl/ms7210_ctl/N539/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/N122_11/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -37285,7 +37225,7 @@ L3;1 L4;1 Inst -image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[2]/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -37295,17 +37235,23 @@ L3;1 L4;1 Inst -image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[3]/gateop_perm;gopLUT5 +image_filiter_inst2/vector_to_matrix_inst/mat[0][2][5]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -37315,17 +37261,20 @@ L3;1 L4;1 Inst -image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[4]/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N87.lt_2/gateop_perm;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[6]/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[5]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -37335,7 +37284,7 @@ L3;1 L4;1 Inst -image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[7]/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -37345,37 +37294,55 @@ L3;1 L4;1 Inst -param_manager_inst/param_osd_startY/N76_mux7_5/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5 +image_filiter_inst/vector_to_matrix_inst/mat[0][0][0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[10]/gateop_perm;gopLUT5 +image_filiter_inst2/vector_to_matrix_inst/mat[0][2][9]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[11]/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[10]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -37385,7 +37352,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_offsetY/N63_mux5_3/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[11]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -37395,14 +37362,20 @@ L3;1 L4;1 Inst -param_manager_inst/param_offsetY/N63_mux3/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/m_pixel_valid/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N21.eq_0/gateop_A2;gopA2 @@ -37693,20 +37666,14 @@ I14;1 RS;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_y[0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[8]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21;gopA2Q2 @@ -38349,14 +38316,20 @@ WR_EOP;1 WR_ERR;1 Inst -image_filiter_inst/multiline_buffer_inst/N176_3/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/hor_cnt[8]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst image_filiter_inst/multiline_buffer_inst/hor_cnt[2]/opit_0_A2Q21;gopA2Q2 @@ -38466,20 +38439,14 @@ I14;1 RS;1 Inst -image_filiter_inst/multiline_buffer_inst/hor_cnt[10]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/multiline_buffer_inst/N93_mux7_13/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst image_filiter_inst/multiline_buffer_inst/hor_cnt[9]/opit_0_A2Q0;gopA2Q0 @@ -38508,17 +38475,23 @@ I14;1 RS;1 Inst -image_filiter_inst/multiline_buffer_inst/N122_2/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_rotate_image/rotate_sta_fsm[2:0]_9_2/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/N236_10/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -38668,7 +38641,7 @@ I14;1 RS;1 Inst -image_filiter_inst2/multiline_buffer_inst/N269_3/gateop_perm;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/N271/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -38788,7 +38761,7 @@ I14;1 RS;1 Inst -param_manager_inst/param_offsetX/N63_mux6_5/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/N48/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -38798,14 +38771,20 @@ L3;1 L4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N68_14_1/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/ver_cnt[5]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst image_filiter_inst/multiline_buffer_inst/ver_cnt[2]/opit_0_A2Q21;gopA2Q2 @@ -38835,20 +38814,14 @@ I14;1 RS;1 Inst -image_filiter_inst/multiline_buffer_inst/ver_cnt[5]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/multiline_buffer_inst/N122_10/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst image_filiter_inst/multiline_buffer_inst/ver_cnt[4]/opit_0_A2Q1;gopA2Q1 @@ -38935,23 +38908,17 @@ I14;1 RS;1 Inst -image_filiter_inst/vector_to_matrix_inst/mat[0][0][4]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/multiline_buffer_inst/N53_mux5_8/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst/vector_to_matrix_inst/mat[0][2][0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/vector_to_matrix_inst/mat[0][2][1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -38967,7 +38934,7 @@ L4;1 RS;1 Inst -image_filiter_inst/vector_to_matrix_inst/mat[0][0][3]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/vector_to_matrix_inst/mat[0][0][2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -38983,7 +38950,7 @@ L4;1 RS;1 Inst -image_filiter_inst/vector_to_matrix_inst/mat[0][0][12]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/vector_to_matrix_inst/mat[0][2][2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -38999,7 +38966,7 @@ L4;1 RS;1 Inst -image_filiter_inst/vector_to_matrix_inst/mat[0][2][2]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/vector_to_matrix_inst/mat[0][0][4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -39015,7 +38982,7 @@ L4;1 RS;1 Inst -image_filiter_inst/vector_to_matrix_inst/mat[0][0][0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/vector_to_matrix_inst/mat[0][2][3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -39031,7 +38998,7 @@ L4;1 RS;1 Inst -image_filiter_inst/vector_to_matrix_inst/mat[0][0][10]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/vector_to_matrix_inst/mat[0][0][6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -39047,7 +39014,7 @@ L4;1 RS;1 Inst -image_filiter_inst/vector_to_matrix_inst/mat[0][0][7]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/vector_to_matrix_inst/mat[0][2][5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -39063,7 +39030,7 @@ L4;1 RS;1 Inst -image_filiter_inst/vector_to_matrix_inst/mat[0][2][5]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/vector_to_matrix_inst/mat[0][2][7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -39079,23 +39046,17 @@ L4;1 RS;1 Inst -image_filiter_inst/vector_to_matrix_inst/mat[0][2][8]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N17/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst/vector_to_matrix_inst/mat[0][0][14]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/vector_to_matrix_inst/mat[0][2][8]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -39111,7 +39072,7 @@ L4;1 RS;1 Inst -image_filiter_inst/vector_to_matrix_inst/mat[0][0][8]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/vector_to_matrix_inst/mat[0][2][10]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -39127,17 +39088,23 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N68_1/gateop_perm;gopLUT5 +image_filiter_inst/vector_to_matrix_inst/mat[0][2][11]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -image_filiter_inst/vector_to_matrix_inst/mat[0][2][12]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/vector_to_matrix_inst/mat[0][0][10]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -39153,20 +39120,7 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N15.lt_2/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -image_filiter_inst/vector_to_matrix_inst/mat[0][0][15]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/vector_to_matrix_inst/mat[0][0][14]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -39182,7 +39136,7 @@ L4;1 RS;1 Inst -image_filiter_inst/vector_to_matrix_inst/mat[0][2][14]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/vector_to_matrix_inst/mat[0][0][15]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -39197,6 +39151,19 @@ L3;1 L4;1 RS;1 +Inst +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N8.lt_2/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + Inst image_filiter_inst/vector_to_matrix_inst/mat[0][1][0]/opit_0;gopQ Pin @@ -39374,20 +39341,27 @@ D;1 RS;1 Inst -image_filiter_inst/vector_to_matrix_inst/mat[0][2][1]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N5.lt_2/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + +Inst +image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/N39_0_ac4/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst image_filiter_inst/vector_to_matrix_inst/mat[0][2][4]/opit_0_L5Q_perm;gopL5Q @@ -39406,49 +39380,24 @@ L4;1 RS;1 Inst -image_filiter_inst/vector_to_matrix_inst/mat[0][2][3]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N55_7/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N5.lt_2/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/multiline_buffer_inst/N216/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst image_filiter_inst/vector_to_matrix_inst/mat[0][2][6]/opit_0_L5Q_perm;gopL5Q @@ -39467,33 +39416,24 @@ L4;1 RS;1 Inst -image_filiter_inst/vector_to_matrix_inst/mat[0][2][7]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[0]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N5.lt_2/gateop_perm;gopA +image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/N39_0_ac5/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst image_filiter_inst/vector_to_matrix_inst/mat[0][2][9]/opit_0_L5Q_perm;gopL5Q @@ -39512,7 +39452,7 @@ L4;1 RS;1 Inst -image_filiter_inst/vector_to_matrix_inst/mat[0][2][10]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -39528,20 +39468,17 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/N111.lt_2/gateop_perm;gopA +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N68_1/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/vector_to_matrix_inst/mat[0][2][12]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -39573,30 +39510,23 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N15.lt_2/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N68_10_1/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[5]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -image_filiter_inst/vector_to_matrix_inst/mat[0][0][9]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/vector_to_matrix_inst/mat[0][2][15]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -39611,6 +39541,19 @@ L3;1 L4;1 RS;1 +Inst +image_filiter_inst/hybrid_filter_inst/median_finder9_g/N107.lt_2/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + Inst image_filiter_inst/vector_to_matrix_inst/mat[1][0][0]/opit_0;gopQ Pin @@ -40679,20 +40622,17 @@ D;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N15.lt_2/gateop_perm;gopA +image_filiter_inst2/hybrid_filter_inst/N90_mux2_3/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N17/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N104_40/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -40742,7 +40682,7 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N35.lt_2/gateop_perm;gopA +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N167.lt_2/gateop_perm;gopA Pin Cout;2 Y;2 @@ -40755,34 +40695,20 @@ I3;1 I4;1 Inst -image_filiter_inst2/hybrid_filter_inst/N106_78/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -image_filiter_inst2/hybrid_filter_inst/N162_72/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_zoom_image/N709_8/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/cnt_times[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst image_filiter_inst2/hybrid_filter_inst/N134_72/gateop_perm;gopLUT5 @@ -40795,14 +40721,20 @@ L3;1 L4;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N68_10_1/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst image_filiter_inst2/hybrid_filter_inst/N127.fsub_1/gateop_A2;gopA2 @@ -40865,20 +40797,7 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N5.lt_2/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -u_ddr_addr_ctr/N69_6/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/N162_72/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -40888,20 +40807,40 @@ L3;1 L4;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N12[4]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 + +Inst +image_filiter_inst2/hybrid_filter_inst/N155.fsub_5/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + +Inst +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N107.lt_2/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst image_filiter_inst2/hybrid_filter_inst/N155.fsub_1/gateop_A2;gopA2 @@ -40944,33 +40883,30 @@ I13;1 I14;1 Inst -u_ddr_addr_ctr/N69_18/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N111.lt_2/gateop_perm;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N17/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/N39_0_ac5/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/N39_0_maj3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -40980,7 +40916,7 @@ L3;1 L4;1 Inst -image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/N39_0_maj3/gateop_perm;gopLUT5 +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -40990,20 +40926,14 @@ L3;1 L4;1 Inst -u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[16]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/N39_0_ac5/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/N47_1_1/gateop_A2;gopA2 @@ -42283,7 +42213,7 @@ I4;1 RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N12[6]/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/N39_0_maj3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -42293,7 +42223,17 @@ L3;1 L4;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N8.lt_2/gateop_perm;gopA +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N188_40/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N155.lt_2/gateop_perm;gopA Pin Cout;2 Y;2 @@ -42306,24 +42246,17 @@ I3;1 I4;1 Inst -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/N39_0_maj3/gateop;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N161.lt_2/gateop_perm;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/N47_1_1/gateop_A2;gopA2 @@ -43829,7 +43762,7 @@ L3;1 L4;1 Inst -image_filiter_inst2/vector_to_matrix_inst/mat[0][0][13]/opit_0_L5Q_perm;gopL5Q +u_rotate_image/image_h_blank_valid/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -43845,20 +43778,14 @@ L4;1 RS;1 Inst -image_filiter_inst2/vector_to_matrix_inst/mat[0][2][13]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/N39_0_ac5/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/N47_1_1/gateop_A2;gopA2 @@ -45169,14 +45096,20 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N104_40/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N37.lt_0/gateop_A2;gopA2 @@ -45199,17 +45132,20 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N35.lt_2/gateop_perm;gopA +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N39.lt_0/gateop_A2;gopA2 @@ -45268,20 +45204,14 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N104_40/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N85.lt_0/gateop_A2;gopA2 @@ -45304,7 +45234,7 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N39.lt_2/gateop_perm;gopA +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N83.lt_2/gateop_perm;gopA Pin Cout;2 Y;2 @@ -45337,36 +45267,27 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q +u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[11]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N87.lt_2/gateop_perm;gopA Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N107.lt_0/gateop_A2;gopA2 @@ -45389,20 +45310,17 @@ I13;1 I14;1 Inst -image_filiter_inst2/vector_to_matrix_inst/mat[0][0][0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N39.lt_2/gateop_perm;gopA Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N109.lt_0/gateop_A2;gopA2 @@ -45425,20 +45343,14 @@ I13;1 I14;1 Inst -image_filiter_inst2/vector_to_matrix_inst/mat[0][0][2]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N17/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N111.lt_0/gateop_A2;gopA2 @@ -45461,7 +45373,7 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -45497,20 +45409,17 @@ I13;1 I14;1 Inst -image_filiter_inst2/vector_to_matrix_inst/mat[0][2][10]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N85.lt_2/gateop_perm;gopA Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N161.lt_0/gateop_A2;gopA2 @@ -45533,17 +45442,14 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N155.lt_2/gateop_perm;gopA +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N17/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N167.lt_0/gateop_A2;gopA2 @@ -45566,20 +45472,23 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N167.lt_2/gateop;gopA +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/N155.fsub_5/gateop_perm;gopA +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N8.lt_2/gateop_perm;gopA Pin Cout;2 Y;2 @@ -45612,20 +45521,14 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N17/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N5.lt_0/gateop_A2;gopA2 @@ -45648,14 +45551,17 @@ I13;1 I14;1 Inst -N119_mux11_11/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N4.lt_2/gateop_perm;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N8.lt_0/gateop_A2;gopA2 @@ -45678,14 +45584,20 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N55_7/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N15.lt_0/gateop_A2;gopA2 @@ -45708,20 +45620,14 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/N39_0_ac4/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N55_9/gateop_perm;gopLUT5 @@ -45734,17 +45640,23 @@ L3;1 L4;1 Inst -u_ddr_addr_ctr/u_wr3_addr_ctr/N1/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N68_1/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N68_10_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -45754,7 +45666,7 @@ L3;1 L4;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N68_7/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N68_14_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -45764,7 +45676,7 @@ L3;1 L4;1 Inst -u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[10]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -45865,20 +45777,7 @@ S0;1 S1;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N8.lt_2/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -45910,7 +45809,17 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -45926,56 +45835,71 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N8.lt_2/gateop_perm;gopA +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N15.lt_2/gateop_perm;gopA +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N5.lt_2/gateop_perm;gopA +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N55_11_1/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N4.lt_2/gateop_perm;gopA +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N4.lt_2/gateop_perm;gopA Pin Cout;2 Y;2 @@ -45988,14 +45912,17 @@ I3;1 I4;1 Inst -image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/N39_0_ac4/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N109.lt_2/gateop_perm;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N4.lt_0/gateop_A2;gopA2 @@ -46018,7 +45945,7 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/multiline_buffer_inst/hor_cnt[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -46054,14 +45981,20 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N55_9/gateop_perm;gopLUT5 +image_filiter_inst2/vector_to_matrix_inst/mat[0][0][2]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N8.lt_0/gateop_A2;gopA2 @@ -46084,17 +46017,14 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N4.lt_2/gateop_perm;gopA +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N15.lt_0/gateop_A2;gopA2 @@ -46117,7 +46047,7 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/vector_to_matrix_inst/mat[0][2][1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -46133,39 +46063,27 @@ L4;1 RS;1 Inst -u_ddr_addr_ctr/u_wr3_addr_ctr/delay_cnt[0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N68_10_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N55_11_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N68_10_1/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N68_14_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -46175,7 +46093,7 @@ L3;1 L4;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N68_14_1/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N55_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -46185,14 +46103,20 @@ L3;1 L4;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N17/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[0]/opit_0_MUX4TO1Q;gopMUX4TO1Q @@ -46280,7 +46204,7 @@ S0;1 S1;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -46296,7 +46220,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -46312,20 +46236,23 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N87.lt_2/gateop_perm;gopA +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N109.lt_2/gateop_perm;gopA +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N15.lt_2/gateop_perm;gopA Pin Cout;2 Y;2 @@ -46338,20 +46265,23 @@ I3;1 I4;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N15.lt_2/gateop_perm;gopA +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -46367,7 +46297,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -46399,7 +46329,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -46415,7 +46345,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N83.lt_2/gateop_perm;gopA +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N5.lt_2/gateop_perm;gopA Pin Cout;2 Y;2 @@ -46448,20 +46378,17 @@ I13;1 I14;1 Inst -vs_down_delay_cnt[1]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N5.lt_2/gateop_perm;gopA Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N5.lt_0/gateop_A2;gopA2 @@ -46484,14 +46411,20 @@ I13;1 I14;1 Inst -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/hor_cnt[8]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N8.lt_0/gateop_A2;gopA2 @@ -46514,20 +46447,14 @@ I13;1 I14;1 Inst -u_ov5640/u_mix_image/rd_vs_rise/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N68_14_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N15.lt_0/gateop_A2;gopA2 @@ -46550,7 +46477,7 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N68_14_1/gateop_perm;gopLUT5 +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N24_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -46580,39 +46507,33 @@ L3;1 L4;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N5.lt_2/gateop_perm;gopA Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N15.lt_2/gateop_perm;gopA Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -u_ov5640/u_mix_image/N339_9/gateop_perm;gopLUT5 +u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N12[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -46707,7 +46628,7 @@ S0;1 S1;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -46723,36 +46644,17 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N4.lt_2/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N85[1]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -46768,7 +46670,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/vector_to_matrix_inst/mat[0][0][3]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -46784,7 +46686,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -46800,7 +46702,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -46816,23 +46718,20 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N4.lt_2/gateop_perm;gopA Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N5.lt_2/gateop_perm;gopA +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N8.lt_2/gateop_perm;gopA Pin Cout;2 Y;2 @@ -46845,7 +46744,23 @@ I3;1 I4;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N17/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q +Pin +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 + +Inst +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N55_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -47495,7 +47410,7 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N37.lt_2/gateop_perm;gopA +image_filiter_inst/hybrid_filter_inst/median_finder9_g/N37.lt_2/gateop_perm;gopA Pin Cout;2 Y;2 @@ -47528,7 +47443,7 @@ I13;1 I14;1 Inst -image_filiter_inst2/vector_to_matrix_inst/mat[0][0][7]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -47564,7 +47479,7 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -47600,17 +47515,14 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N85.lt_2/gateop_perm;gopA +image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[6]/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N85.lt_0/gateop_A2;gopA2 @@ -47633,14 +47545,20 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N104_40/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N87.lt_0/gateop_A2;gopA2 @@ -47663,7 +47581,7 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/vector_to_matrix_inst/mat[0][0][5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -47679,7 +47597,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/vector_to_matrix_inst/mat[0][0][5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -47715,20 +47633,53 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N107.lt_2/gateop;gopA +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N55_7/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N109.lt_0/gateop_A2;gopA2 Pin Cout;2 -Y;2 +Y0;2 +Y1;2 Cin;1 -I0;1 I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +I1X;1 +I00;1 +I01;1 +I02;1 +I03;1 +I04;1 +I10;1 +I11;1 +I12;1 +I13;1 +I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N109.lt_0/gateop_A2;gopA2 +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q +Pin +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 + +Inst +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N111.lt_0/gateop_A2;gopA2 Pin Cout;2 Y0;2 @@ -47748,7 +47699,7 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N39.lt_2/gateop_perm;gopA +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N107.lt_2/gateop_perm;gopA Pin Cout;2 Y;2 @@ -47761,7 +47712,7 @@ I3;1 I4;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N111.lt_0/gateop_A2;gopA2 +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N155.lt_0/gateop_A2;gopA2 Pin Cout;2 Y0;2 @@ -47781,23 +47732,17 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N155.lt_0/gateop_A2;gopA2 +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N161.lt_0/gateop_A2;gopA2 Pin Cout;2 Y0;2 @@ -47817,7 +47762,7 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N167.lt_2/gateop_perm;gopA +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N161.lt_2/gateop;gopA Pin Cout;2 Y;2 @@ -47830,7 +47775,7 @@ I3;1 I4;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N161.lt_0/gateop_A2;gopA2 +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N167.lt_0/gateop_A2;gopA2 Pin Cout;2 Y0;2 @@ -47850,53 +47795,20 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q -Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 - -Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N167.lt_0/gateop_A2;gopA2 +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N37.lt_2/gateop_perm;gopA Pin Cout;2 -Y0;2 -Y1;2 +Y;2 Cin;1 +I0;1 I0X;1 -I1X;1 -I00;1 -I01;1 -I02;1 -I03;1 -I04;1 -I10;1 -I11;1 -I12;1 -I13;1 -I14;1 - -Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N188_40/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N161.lt_2/gateop_perm;gopA +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N35.lt_2/gateop_perm;gopA Pin Cout;2 Y;2 @@ -47929,7 +47841,7 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N15.lt_2/gateop_perm;gopA +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N8.lt_2/gateop_perm;gopA Pin Cout;2 Y;2 @@ -47962,17 +47874,20 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N5.lt_2/gateop_perm;gopA +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N8.lt_0/gateop_A2;gopA2 @@ -47995,14 +47910,20 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N17/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N15.lt_0/gateop_A2;gopA2 @@ -48025,20 +47946,7 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N15.lt_2/gateop;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -image_filiter_inst2/vector_to_matrix_inst/mat[0][0][6]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -48054,7 +47962,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N55_11_1/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N68_10_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -48064,14 +47972,20 @@ L3;1 L4;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N68_10_1/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[5]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N68_14_1/gateop_perm;gopLUT5 @@ -48084,7 +47998,7 @@ L3;1 L4;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -48099,6 +48013,19 @@ L3;1 L4;1 RS;1 +Inst +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N4.lt_2/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[0]/opit_0_MUX4TO1Q;gopMUX4TO1Q Pin @@ -48218,7 +48145,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -48234,7 +48161,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -48250,14 +48177,20 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N55_9/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q @@ -48276,7 +48209,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -48292,7 +48225,17 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[5]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N68_10_1/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -48308,20 +48251,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N35.lt_2/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -48337,7 +48267,17 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[3]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -48353,7 +48293,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/vector_to_matrix_inst/mat[0][0][5]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -48368,19 +48308,6 @@ L3;1 L4;1 RS;1 -Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N161.lt_2/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N4.lt_0/gateop_A2;gopA2 Pin @@ -48402,20 +48329,14 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/N142_mux4_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N5.lt_0/gateop_A2;gopA2 @@ -48438,14 +48359,20 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N68_10_1/gateop_perm;gopLUT5 +image_filiter_inst2/vector_to_matrix_inst/mat[0][0][7]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N8.lt_0/gateop_A2;gopA2 @@ -48468,17 +48395,20 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N5.lt_2/gateop_perm;gopA +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N15.lt_0/gateop_A2;gopA2 @@ -48501,33 +48431,23 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N4.lt_2/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N111.lt_2/gateop_perm;gopA +image_filiter_inst2/vector_to_matrix_inst/mat[0][2][7]/opit_0_L5Q_perm;gopL5Q Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N55_11_1/gateop_perm;gopLUT5 +image_filiter_inst/multiline_buffer_inst/N229_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -48537,7 +48457,7 @@ L3;1 L4;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/vector_to_matrix_inst/mat[0][0][6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -48553,7 +48473,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N68_14_1/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/N146_mux2_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -48563,7 +48483,7 @@ L3;1 L4;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N55_9/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N68_14_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -48572,6 +48492,19 @@ L2;1 L3;1 L4;1 +Inst +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N15.lt_2/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[0]/opit_0_MUX4TO1Q;gopMUX4TO1Q Pin @@ -48675,23 +48608,7 @@ S0;1 S1;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q -Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 - -Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -48707,7 +48624,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -48733,7 +48650,7 @@ L3;1 L4;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -48749,7 +48666,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[5]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -48765,20 +48682,30 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N8.lt_2/gateop_perm;gopA Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + +Inst +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N15.lt_2/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q @@ -48797,7 +48724,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -48813,7 +48740,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -48829,36 +48756,27 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[5]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[1]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N4.lt_2/gateop_perm;gopA Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N4.lt_0/gateop_A2;gopA2 @@ -48881,14 +48799,17 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/N39_0_ac5/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N8.lt_2/gateop_perm;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N5.lt_0/gateop_A2;gopA2 @@ -48911,20 +48832,14 @@ I13;1 I14;1 Inst -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N55_11_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N8.lt_0/gateop_A2;gopA2 @@ -48947,7 +48862,7 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N68_14_1/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/N39_0_ac6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -48990,17 +48905,7 @@ I3;1 I4;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N55_9/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N55_11_1/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/N39_0_ac5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -49010,7 +48915,7 @@ L3;1 L4;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N5.lt_2/gateop_perm;gopA +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N15.lt_2/gateop_perm;gopA Pin Cout;2 Y;2 @@ -49023,7 +48928,7 @@ I3;1 I4;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N17/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N68_10_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -49033,20 +48938,27 @@ L3;1 L4;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N68_14_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 + +Inst +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N167.lt_2/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[0]/opit_0_MUX4TO1Q;gopMUX4TO1Q @@ -49151,7 +49063,7 @@ S0;1 S1;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -49167,7 +49079,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -49183,36 +49095,17 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/N39_0_ac4/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N8.lt_2/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N15.lt_2/gateop_perm;gopA +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N85.lt_2/gateop_perm;gopA Pin Cout;2 Y;2 @@ -49225,7 +49118,7 @@ I3;1 I4;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N109.lt_2/gateop_perm;gopA +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N8.lt_2/gateop_perm;gopA Pin Cout;2 Y;2 @@ -49238,7 +49131,7 @@ I3;1 I4;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -49254,23 +49147,17 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N55_9/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -49286,7 +49173,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N8.lt_2/gateop_perm;gopA +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N5.lt_2/gateop_perm;gopA Pin Cout;2 Y;2 @@ -49299,7 +49186,7 @@ I3;1 I4;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[5]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -49315,17 +49202,36 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N4.lt_2/gateop_perm;gopA +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 + +Inst +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q +Pin +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max[0]/opit_0;gopQ @@ -50092,20 +49998,14 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/N86_mux4_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N37.lt_0/gateop_A2;gopA2 @@ -50128,20 +50028,17 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N107.lt_2/gateop_perm;gopA Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N39.lt_0/gateop_A2;gopA2 @@ -50164,7 +50061,7 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -50200,17 +50097,20 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N15.lt_2/gateop_perm;gopA +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N85.lt_0/gateop_A2;gopA2 @@ -50233,14 +50133,20 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N104_40/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N87.lt_0/gateop_A2;gopA2 @@ -50263,7 +50169,7 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -50279,7 +50185,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N4.lt_2/gateop_perm;gopA +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N155.lt_2/gateop_perm;gopA Pin Cout;2 Y;2 @@ -50312,7 +50218,7 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N85.lt_2/gateop_perm;gopA +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N111.lt_2/gateop_perm;gopA Pin Cout;2 Y;2 @@ -50345,7 +50251,7 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N83.lt_2/gateop_perm;gopA +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N37.lt_2/gateop_perm;gopA Pin Cout;2 Y;2 @@ -50378,17 +50284,14 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N155.lt_2/gateop_perm;gopA +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N68_10_1/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N155.lt_0/gateop_A2;gopA2 @@ -50411,17 +50314,14 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N37.lt_2/gateop_perm;gopA +u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N12[0]/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N161.lt_0/gateop_A2;gopA2 @@ -50444,20 +50344,14 @@ I13;1 I14;1 Inst -u_axi_ddr_top/rd_ddr_idle/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N188_40/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N167.lt_0/gateop_A2;gopA2 @@ -50480,30 +50374,30 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N111.lt_2/gateop_perm;gopA +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N167.lt_2/gateop_perm;gopA +image_filiter_inst2/hybrid_filter_inst/N106_72/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N4.lt_0/gateop_A2;gopA2 @@ -50526,7 +50420,7 @@ I13;1 I14;1 Inst -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[5]/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N68_10_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -50556,14 +50450,17 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N55_11_1/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N8.lt_2/gateop_perm;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N8.lt_0/gateop_A2;gopA2 @@ -50586,14 +50483,17 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N17/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_g/N155.lt_2/gateop_perm;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N15.lt_0/gateop_A2;gopA2 @@ -50616,7 +50516,7 @@ I13;1 I14;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -50632,7 +50532,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N55_9/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -50642,7 +50542,7 @@ L3;1 L4;1 Inst -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -50652,23 +50552,17 @@ L3;1 L4;1 Inst -image_filiter_inst2/vector_to_matrix_inst/mat[0][0][11]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N68_14_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N68_14_1/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N17/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -50678,14 +50572,20 @@ L3;1 L4;1 Inst -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[1]/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/max[0]/opit_0_MUX4TO1Q;gopMUX4TO1Q @@ -50789,7 +50689,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -50805,14 +50705,20 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N68_7/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q @@ -50831,17 +50737,20 @@ L4;1 RS;1 Inst -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[7]/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N4.lt_2/gateop_perm;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -50857,23 +50766,17 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N55_11_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N8.lt_2/gateop_perm;gopA +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N83.lt_2/gateop_perm;gopA Pin Cout;2 Y;2 @@ -50886,36 +50789,27 @@ I3;1 I4;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N87.lt_2/gateop_perm;gopA Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N4.lt_0/gateop_A2;gopA2 @@ -50938,7 +50832,7 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N15.lt_2/gateop_perm;gopA +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N15.lt_2/gateop_perm;gopA Pin Cout;2 Y;2 @@ -50971,14 +50865,20 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N68_14_1/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N8.lt_0/gateop_A2;gopA2 @@ -51001,7 +50901,7 @@ I13;1 I14;1 Inst -image_filiter_inst2/vector_to_matrix_inst/mat[0][2][5]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -51037,36 +50937,17 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N8.lt_2/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N55_9/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N55_11_1/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N68_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -51076,23 +50957,17 @@ L3;1 L4;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N17/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N4.lt_2/gateop_perm;gopA +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N4.lt_2/gateop_perm;gopA Pin Cout;2 Y;2 @@ -51105,7 +50980,7 @@ I3;1 I4;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -51120,6 +50995,19 @@ L3;1 L4;1 RS;1 +Inst +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N5.lt_2/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/max[0]/opit_0_MUX4TO1Q;gopMUX4TO1Q Pin @@ -51206,17 +51094,7 @@ S0;1 S1;1 Inst -image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/N39_0_ac4/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -51232,7 +51110,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -51248,7 +51126,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -51264,27 +51142,33 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N188_40/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N8.lt_2/gateop_perm;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/N39_0_ac5/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N15.lt_2/gateop_perm;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -51300,7 +51184,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N55_9/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N17/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -51310,23 +51194,30 @@ L3;1 L4;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N109.lt_2/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + +Inst +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N55_7/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -51362,17 +51253,20 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N4.lt_2/gateop;gopA +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N5.lt_0/gateop_A2;gopA2 @@ -51395,20 +51289,17 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N5.lt_2/gateop;gopA Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N8.lt_0/gateop_A2;gopA2 @@ -51431,7 +51322,7 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N55_11_1/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N55_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -51461,17 +51352,23 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N55_9/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_2/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N55_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -51481,7 +51378,7 @@ L3;1 L4;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N68_10_1/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N55_11_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -51491,7 +51388,7 @@ L3;1 L4;1 Inst -u_clk50m_rst/rst/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -51507,30 +51404,30 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N68_14_1/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N85.lt_2/gateop_perm;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N5.lt_2/gateop_perm;gopA Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/max[0]/opit_0_MUX4TO1Q;gopMUX4TO1Q @@ -51618,7 +51515,7 @@ S0;1 S1;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -51634,7 +51531,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -51650,7 +51547,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N87.lt_2/gateop_perm;gopA +image_filiter_inst/hybrid_filter_inst/median_finder9_g/N167.lt_2/gateop_perm;gopA Pin Cout;2 Y;2 @@ -51663,20 +51560,23 @@ I3;1 I4;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N5.lt_2/gateop_perm;gopA +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/pll_lock_d[0]/opit_0_inv_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -51708,7 +51608,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -51724,7 +51624,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -51740,7 +51640,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -51756,17 +51656,14 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N39.lt_2/gateop_perm;gopA +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N68_14_1/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max[0]/opit_0;gopQ @@ -53429,7 +53326,7 @@ I13;1 I14;1 Inst -u_ddr_addr_ctr/u_rd3_addr_ctr/rd_image_cnt[0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/multiline_buffer_inst/ver_cnt[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -53445,7 +53342,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[11]/gateop_perm;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/N93_mux7_12/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -53455,23 +53352,17 @@ L3;1 L4;1 Inst -image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/multiline_buffer_inst/N96_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst2/multiline_buffer_inst/N189[1]_1/gateop_perm;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/N269_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -53481,7 +53372,7 @@ L3;1 L4;1 Inst -image_filiter_inst2/multiline_buffer_inst/N176_3/gateop_perm;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/N189[1]_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -53491,7 +53382,7 @@ L3;1 L4;1 Inst -image_filiter_inst2/multiline_buffer_inst/N176_15/gateop_perm;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/N179_mux8_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -53501,7 +53392,7 @@ L3;1 L4;1 Inst -image_filiter_inst2/multiline_buffer_inst/N179_mux8_9/gateop_perm;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/N176_15/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -53511,23 +53402,17 @@ L3;1 L4;1 Inst -image_filiter_inst2/multiline_buffer_inst/ver_cnt[3]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/multiline_buffer_inst/N229_8/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N17/gateop_perm;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/N216/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -53537,7 +53422,7 @@ L3;1 L4;1 Inst -image_filiter_inst2/multiline_buffer_inst/N189[1]_8/gateop_perm;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -53547,7 +53432,7 @@ L3;1 L4;1 Inst -image_filiter_inst2/multiline_buffer_inst/N199_mux5/gateop_perm;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/N93_mux7_14/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -53557,37 +53442,55 @@ L3;1 L4;1 Inst -image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[10:0]_or_1/gateop_perm;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -image_filiter_inst2/multiline_buffer_inst/N271/gateop_perm;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/m_pixel_valid/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/N236_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -53607,7 +53510,7 @@ L3;1 L4;1 Inst -u_ddr_addr_ctr/N69_14/gateop_perm;gopLUT5 +u_ov5640/coms2_reg_config/N26_mux2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -53617,24 +53520,36 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/ver_cnt[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5 +u_ov5640/coms2_reg_config/u1/cyc_count[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[10:0]_or_3/gateop_perm;gopLUT5 @@ -53647,7 +53562,7 @@ L3;1 L4;1 Inst -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -53657,7 +53572,7 @@ L3;1 L4;1 Inst -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -53667,24 +53582,33 @@ L3;1 L4;1 Inst -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N15.lt_2/gateop_perm;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5 +image_filiter_inst2/vector_to_matrix_inst/mat[0][0][3]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 @@ -53697,7 +53621,7 @@ L3;1 L4;1 Inst -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[2]/gateop_perm;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -53707,7 +53631,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q_perm;gopL5Q +image_filiter_inst2/vector_to_matrix_inst/mat[0][2][3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -53723,7 +53647,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/N176_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -53743,7 +53667,7 @@ L3;1 L4;1 Inst -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[9]/gateop_perm;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -53763,7 +53687,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/N117_mux7_7/gateop_perm;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[8]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -53783,7 +53707,7 @@ L3;1 L4;1 Inst -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[0]/gateop_perm;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -53793,7 +53717,7 @@ L3;1 L4;1 Inst -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -53803,7 +53727,7 @@ L3;1 L4;1 Inst -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[4]/gateop_perm;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[5]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -53823,23 +53747,17 @@ L3;1 L4;1 Inst -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[1]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[8]/gateop_perm;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -53849,7 +53767,7 @@ L3;1 L4;1 Inst -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/N924_10/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -53859,14 +53777,20 @@ L3;1 L4;1 Inst -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[9]/gateop_perm;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[10]/gateop_perm;gopLUT5 @@ -53889,7 +53813,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/N189[1]_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -54187,20 +54111,14 @@ I14;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[6]/opit_0_inv_L5Q_perm;gopL5Q +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[9]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21;gopA2Q2 @@ -54853,39 +54771,27 @@ L3;1 L4;1 Inst -image_filiter_inst2/multiline_buffer_inst/hor_cnt[8]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst2/vector_to_matrix_inst/mat[0][0][14]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 +u_ov5640/coms2_reg_config/u1/N267_21/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -54895,7 +54801,7 @@ L3;1 L4;1 Inst -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -54905,27 +54811,39 @@ L3;1 L4;1 Inst -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5 +u_ov5640/coms2_reg_config/reg_index[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[4]/gateop_perm;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[0]/gateop_perm;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -54945,23 +54863,17 @@ L3;1 L4;1 Inst -image_filiter_inst2/multiline_buffer_inst/m_pixel_valid/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst2/multiline_buffer_inst/N199_mux5_8/gateop_perm;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[11]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -54971,23 +54883,17 @@ L3;1 L4;1 Inst -image_filiter_inst2/vector_to_matrix_inst/mat[0][2][2]/opit_0_L5Q_perm;gopL5Q +u_ov5640/coms2_reg_config/u1/N146_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[2]/gateop_perm;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -54997,7 +54903,7 @@ L3;1 L4;1 Inst -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -55007,7 +54913,7 @@ L3;1 L4;1 Inst -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[3]/gateop_perm;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -55017,7 +54923,7 @@ L3;1 L4;1 Inst -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[7]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -55027,7 +54933,7 @@ L3;1 L4;1 Inst -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[6]/gateop_perm;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[5]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -55037,23 +54943,17 @@ L3;1 L4;1 Inst -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[6]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[7]/gateop_perm;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[8]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -55063,23 +54963,17 @@ L3;1 L4;1 Inst -image_filiter_inst2/multiline_buffer_inst/hor_cnt[0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[11]/gateop_perm;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[9]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -55099,7 +54993,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/N117_mux7_6/gateop_perm;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[11]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -55109,7 +55003,7 @@ L3;1 L4;1 Inst -image_filiter_inst2/multiline_buffer_inst/N216/gateop_perm;gopLUT5 +u_ov5640/coms2_reg_config/u1/N8_mux3_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -55407,7 +55301,7 @@ I14;1 RS;1 Inst -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[8]/gateop_perm;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -56057,7 +55951,7 @@ WR_EOP;1 WR_ERR;1 Inst -image_filiter_inst2/multiline_buffer_inst/N93_mux7_14/gateop_perm;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/N229_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -56216,7 +56110,7 @@ I14;1 RS;1 Inst -image_filiter_inst2/multiline_buffer_inst/N176_2/gateop_perm;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -56226,7 +56120,7 @@ L3;1 L4;1 Inst -image_filiter_inst2/multiline_buffer_inst/N96_3/gateop_perm;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/N199_mux5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -56236,23 +56130,172 @@ L3;1 L4;1 Inst -image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[0]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[2]/opit_0_A2Q21;gopA2Q2 Pin CEOUT;2 -Q;2 +Cout;2 +Q0;2 +Q1;2 RSOUT;2 -Z;2 +Y0;2 +Y1;2 +CE;1 +CLK;1 +Cin;1 +I0X;1 +I1X;1 +I00;1 +I01;1 +I02;1 +I03;1 +I04;1 +I10;1 +I11;1 +I12;1 +I13;1 +I14;1 +RS;1 + +Inst +image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[4]/opit_0_A2Q21;gopA2Q2 +Pin +CEOUT;2 +Cout;2 +Q0;2 +Q1;2 +RSOUT;2 +Y0;2 +Y1;2 +CE;1 +CLK;1 +Cin;1 +I0X;1 +I1X;1 +I00;1 +I01;1 +I02;1 +I03;1 +I04;1 +I10;1 +I11;1 +I12;1 +I13;1 +I14;1 +RS;1 + +Inst +image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[6]/opit_0_A2Q21;gopA2Q2 +Pin +CEOUT;2 +Cout;2 +Q0;2 +Q1;2 +RSOUT;2 +Y0;2 +Y1;2 CE;1 CLK;1 +Cin;1 +I0X;1 +I1X;1 +I00;1 +I01;1 +I02;1 +I03;1 +I04;1 +I10;1 +I11;1 +I12;1 +I13;1 +I14;1 +RS;1 + +Inst +image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[8]/opit_0_A2Q21;gopA2Q2 +Pin +CEOUT;2 +Cout;2 +Q0;2 +Q1;2 +RSOUT;2 +Y0;2 +Y1;2 +CE;1 +CLK;1 +Cin;1 +I0X;1 +I1X;1 +I00;1 +I01;1 +I02;1 +I03;1 +I04;1 +I10;1 +I11;1 +I12;1 +I13;1 +I14;1 +RS;1 + +Inst +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5 +Pin +Z;2 L0;1 L1;1 L2;1 L3;1 L4;1 + +Inst +image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[10]/opit_0_A2Q21;gopA2Q2 +Pin +CEOUT;2 +Cout;2 +Q0;2 +Q1;2 +RSOUT;2 +Y0;2 +Y1;2 +CE;1 +CLK;1 +Cin;1 +I0X;1 +I1X;1 +I00;1 +I01;1 +I02;1 +I03;1 +I04;1 +I10;1 +I11;1 +I12;1 +I13;1 +I14;1 RS;1 Inst -image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[2]/opit_0_A2Q21;gopA2Q2 +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[3]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[2]/opit_0_A2Q21;gopA2Q2 Pin CEOUT;2 Cout;2 @@ -56279,104 +56322,7 @@ I14;1 RS;1 Inst -image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[4]/opit_0_A2Q21;gopA2Q2 -Pin -CEOUT;2 -Cout;2 -Q0;2 -Q1;2 -RSOUT;2 -Y0;2 -Y1;2 -CE;1 -CLK;1 -Cin;1 -I0X;1 -I1X;1 -I00;1 -I01;1 -I02;1 -I03;1 -I04;1 -I10;1 -I11;1 -I12;1 -I13;1 -I14;1 -RS;1 - -Inst -image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[6]/opit_0_A2Q21;gopA2Q2 -Pin -CEOUT;2 -Cout;2 -Q0;2 -Q1;2 -RSOUT;2 -Y0;2 -Y1;2 -CE;1 -CLK;1 -Cin;1 -I0X;1 -I1X;1 -I00;1 -I01;1 -I02;1 -I03;1 -I04;1 -I10;1 -I11;1 -I12;1 -I13;1 -I14;1 -RS;1 - -Inst -image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[8]/opit_0_A2Q21;gopA2Q2 -Pin -CEOUT;2 -Cout;2 -Q0;2 -Q1;2 -RSOUT;2 -Y0;2 -Y1;2 -CE;1 -CLK;1 -Cin;1 -I0X;1 -I1X;1 -I00;1 -I01;1 -I02;1 -I03;1 -I04;1 -I10;1 -I11;1 -I12;1 -I13;1 -I14;1 -RS;1 - -Inst -u_axi_ddr_top/u_axi_rd_connect/rd0_fifo_empty0/opit_0_L5Q_perm;gopL5Q -Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 - -Inst -image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[10]/opit_0_A2Q21;gopA2Q2 +image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[4]/opit_0_A2Q21;gopA2Q2 Pin CEOUT;2 Cout;2 @@ -56403,7 +56349,7 @@ I14;1 RS;1 Inst -image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[5]/opit_0_AQ_perm;gopAQ +image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[5]/opit_0_AQ;gopAQ Pin CEOUT;2 Cout;2 @@ -56422,77 +56368,7 @@ I4;1 RS;1 Inst -image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[2]/opit_0_A2Q21;gopA2Q2 -Pin -CEOUT;2 -Cout;2 -Q0;2 -Q1;2 -RSOUT;2 -Y0;2 -Y1;2 -CE;1 -CLK;1 -Cin;1 -I0X;1 -I1X;1 -I00;1 -I01;1 -I02;1 -I03;1 -I04;1 -I10;1 -I11;1 -I12;1 -I13;1 -I14;1 -RS;1 - -Inst -image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[4]/opit_0_A2Q21;gopA2Q2 -Pin -CEOUT;2 -Cout;2 -Q0;2 -Q1;2 -RSOUT;2 -Y0;2 -Y1;2 -CE;1 -CLK;1 -Cin;1 -I0X;1 -I1X;1 -I00;1 -I01;1 -I02;1 -I03;1 -I04;1 -I10;1 -I11;1 -I12;1 -I13;1 -I14;1 -RS;1 - -Inst -u_axi_ddr_top/u_axi_rd_connect/rd1_fifo_full0/opit_0_L5Q_perm;gopL5Q -Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 - -Inst -image_filiter_inst2/multiline_buffer_inst/ver_cnt[5]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/multiline_buffer_inst/ver_cnt[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -56535,14 +56411,20 @@ I14;1 RS;1 Inst -image_filiter_inst2/multiline_buffer_inst/N236_4/gateop_perm;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/ver_cnt[5]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst image_filiter_inst2/multiline_buffer_inst/ver_cnt[4]/opit_0_A2Q1;gopA2Q1 @@ -56571,7 +56453,7 @@ I14;1 RS;1 Inst -image_filiter_inst2/multiline_buffer_inst/ver_cnt[6]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/multiline_buffer_inst/ver_cnt[8]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -56587,20 +56469,14 @@ L4;1 RS;1 Inst -image_filiter_inst2/multiline_buffer_inst/ver_cnt[8]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[10:0]_or_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst image_filiter_inst2/multiline_buffer_inst/ver_cnt[7]/opit_0_A2Q0;gopA2Q0 @@ -56639,23 +56515,17 @@ L3;1 L4;1 Inst -image_filiter_inst2/vector_to_matrix_inst/mat[0][0][1]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/multiline_buffer_inst/N176_2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst2/vector_to_matrix_inst/mat[0][2][0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/vector_to_matrix_inst/mat[0][0][4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -56671,20 +56541,17 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N111.lt_2/gateop_perm;gopA +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst -image_filiter_inst2/vector_to_matrix_inst/mat[0][2][3]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/vector_to_matrix_inst/mat[0][0][1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -56700,7 +56567,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/vector_to_matrix_inst/mat[0][2][4]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/vector_to_matrix_inst/mat[0][2][0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -56748,7 +56615,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/vector_to_matrix_inst/mat[0][0][10]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/multiline_buffer_inst/hor_cnt[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -56764,7 +56631,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/vector_to_matrix_inst/mat[0][2][8]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/vector_to_matrix_inst/mat[0][0][10]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -56780,17 +56647,20 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/N55_9/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N37.lt_2/gateop_perm;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -image_filiter_inst2/vector_to_matrix_inst/mat[0][2][6]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/vector_to_matrix_inst/mat[0][2][8]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -56806,7 +56676,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/vector_to_matrix_inst/mat[0][0][12]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/vector_to_matrix_inst/mat[0][0][13]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -56822,7 +56692,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/vector_to_matrix_inst/mat[0][0][15]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/vector_to_matrix_inst/mat[0][0][14]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -56838,17 +56708,23 @@ L4;1 RS;1 Inst -u_axi_rst/N0/gateop_perm;gopLUT5 +image_filiter_inst2/vector_to_matrix_inst/mat[0][2][13]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -image_filiter_inst2/vector_to_matrix_inst/mat[0][2][14]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/vector_to_matrix_inst/mat[0][0][15]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -56864,20 +56740,14 @@ L4;1 RS;1 Inst -image_filiter_inst2/vector_to_matrix_inst/mat[0][2][11]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst image_filiter_inst2/vector_to_matrix_inst/mat[0][1][0]/opit_0;gopQ @@ -57056,7 +56926,7 @@ D;1 RS;1 Inst -image_filiter_inst2/vector_to_matrix_inst/mat[0][2][1]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/vector_to_matrix_inst/mat[0][2][2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -57072,39 +56942,27 @@ L4;1 RS;1 Inst -u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[8]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/multiline_buffer_inst/N176_12/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst2/multiline_buffer_inst/ver_cnt[0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst2/vector_to_matrix_inst/mat[0][0][4]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/vector_to_matrix_inst/mat[0][2][4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -57120,7 +56978,7 @@ L4;1 RS;1 Inst -N119_mux11_12/gateop_perm;gopLUT5 +image_filiter_inst2/multiline_buffer_inst/N53_mux5_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -57130,17 +56988,23 @@ L3;1 L4;1 Inst -image_filiter_inst2/hybrid_filter_inst/N146_mux2_3/gateop_perm;gopLUT5 +image_filiter_inst2/vector_to_matrix_inst/mat[0][2][6]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -image_filiter_inst2/vector_to_matrix_inst/mat[0][2][7]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/vector_to_matrix_inst/mat[0][2][10]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -57156,52 +57020,37 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[5]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N55_9/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst2/vector_to_matrix_inst/mat[0][2][9]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/multiline_buffer_inst/N93_mux7_11/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N37.lt_2/gateop_perm;gopA +image_filiter_inst/multiline_buffer_inst/N236_3/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N85.lt_2/gateop_perm;gopA +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N5.lt_2/gateop_perm;gopA Pin Cout;2 Y;2 @@ -57214,23 +57063,17 @@ I3;1 I4;1 Inst -image_filiter_inst2/vector_to_matrix_inst/mat[0][2][12]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N188_40/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst2/vector_to_matrix_inst/mat[0][2][15]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/vector_to_matrix_inst/mat[0][2][14]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -57246,7 +57089,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/multiline_buffer_inst/N176_12/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -57256,17 +57099,23 @@ L3;1 L4;1 Inst -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[5]/gateop_perm;gopLUT5 +image_filiter_inst2/vector_to_matrix_inst/mat[0][2][15]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -58704,7 +58553,7 @@ MIPI_IN;1 TS;1 Inst -ms72xx_ctl/iic_dri_rx/state_fsm[2:0]_7_2/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_rx/N357_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -58714,7 +58563,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/iic_dri_rx/N313_7/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_rx/N315_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -58724,7 +58573,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/ms7200_ctl/N40_6/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_rx/state_fsm[2:0]_7_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -58776,17 +58625,7 @@ I13;1 I14;1 Inst -ms72xx_ctl/iic_dri_rx/N499_inv/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -ms72xx_ctl/iic_dri_rx/state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/iic_dri_rx/trans_bit[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -58802,7 +58641,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/iic_dri_rx/N315_5/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_rx/N310_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -58812,7 +58651,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/iic_dri_tx/scl_out/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/iic_dri_rx/fre_cnt[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -58828,23 +58667,17 @@ L4;1 RS;1 Inst -ms72xx_ctl/iic_dri_rx/fre_cnt[1]/opit_0_L5Q_perm;gopL5Q +u_zoom_image/N530_mux7_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -ms72xx_ctl/iic_dri_tx/N345_2/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_rx/N434/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -58854,7 +58687,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/iic_dri_rx/twr_cnt[0]/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/iic_dri_rx/scl_out/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -58870,17 +58703,23 @@ L4;1 RS;1 Inst -ms72xx_ctl/iic_dri_rx/N460/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[7].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -ms72xx_ctl/iic_dri_rx/N434/gateop;gopLUT5 +ms72xx_ctl/iic_dri_rx/state_fsm[2:0]_53/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -58890,17 +58729,23 @@ L3;1 L4;1 Inst -ms72xx_ctl/iic_dri_rx/N461_8_and[3][3]/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_tx/scl_out/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -ms72xx_ctl/iic_dri_rx/N498_2/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_rx/N461_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -58920,7 +58765,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/ms7200_ctl/dri_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -58936,23 +58781,17 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/iic_dri_rx/N461_8_or[1][3]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -ms72xx_ctl/iic_dri_rx/N461_8_or[4][3]/gateop_perm;gopLUT5 +ms72xx_ctl/ms7200_ctl/N2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -58962,7 +58801,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/ms7200_ctl/N1845_3/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_rx/N461_8_or[2][3]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -58972,7 +58811,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/ms7200_ctl/N2/gateop_perm;gopLUT5 +ms72xx_ctl/ms7200_ctl/N2053_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -58982,7 +58821,23 @@ L3;1 L4;1 Inst -param_manager_inst/param_modify_H/N63_mux5_5/gateop_perm;gopLUT5 +ms72xx_ctl/ms7200_ctl/addr[2]/opit_0_inv_L5Q_perm;gopL5Q +Pin +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 + +Inst +ms72xx_ctl/iic_dri_rx/N461_11/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -58992,7 +58847,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/iic_dri_rx/state_fsm[2:0]_39_3/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_rx/N498_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -59032,6 +58887,16 @@ L2;1 L3;1 L4;1 +Inst +ms72xx_ctl/iic_dri_tx/N168_mux3_1/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + Inst ms72xx_ctl/iic_dri_rx/state_fsm[2:0]_31/gateop_perm;gopLUT5 Pin @@ -59043,7 +58908,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/iic_dri_rx/state_fsm[2:0]_53/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_rx/state_fsm[2:0]_71/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -59053,39 +58918,27 @@ L3;1 L4;1 Inst -ms72xx_ctl/iic_dri_rx/busy/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/iic_dri_rx/N504/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -ms72xx_ctl/iic_dri_rx/trans_bit[0]/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/ms7200_ctl/N40_8/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -ms72xx_ctl/iic_dri_rx/byte_over/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/iic_dri_rx/trans_en/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -59205,7 +59058,7 @@ D;1 RS;1 Inst -ms72xx_ctl/iic_dri_rx/fre_cnt[2]/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/iic_dri_rx/fre_cnt[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -59221,7 +59074,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/iic_dri_tx/twr_cnt[0]/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/iic_dri_rx/fre_cnt[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -59237,20 +59090,14 @@ L4;1 RS;1 Inst -ms72xx_ctl/iic_dri_rx/fre_cnt[3]/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/ms7200_ctl/N40_6/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst ms72xx_ctl/iic_dri_rx/fre_cnt[4]/opit_0_L5Q_perm;gopL5Q @@ -59269,7 +59116,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/iic_dri_rx/N345_2/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_rx/N165_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -59400,14 +59247,20 @@ D;1 RS;1 Inst -ms72xx_ctl/iic_dri_rx/N165_1/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_rx/fre_cnt[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst ms72xx_ctl/iic_dri_rx/sda_out/opit_0_MUX4TO1Q;gopMUX4TO1Q @@ -59427,7 +59280,7 @@ S0;1 S1;1 Inst -ms72xx_ctl/iic_dri_rx/send_data[3]/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/iic_dri_rx/send_data[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -59459,7 +59312,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/iic_dri_rx/send_data[4]/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/iic_dri_rx/send_data[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -59506,16 +59359,6 @@ L3;1 L4;1 RS;1 -Inst -ms72xx_ctl/iic_dri_rx/N461_8_and[5][3]/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - Inst ms72xx_ctl/iic_dri_rx/send_data[7]/opit_0_L5Q_perm;gopL5Q Pin @@ -59533,23 +59376,17 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/ms7200_ctl/N1359/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -ms72xx_ctl/iic_dri_rx/trans_en/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -59565,7 +59402,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/iic_dri_rx/N461_8_or[2][3]/gateop_perm;gopLUT5 +u_zoom_image/N715_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -59575,7 +59412,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/iic_dri_rx/N357_2/gateop_perm;gopLUT5 +ms72xx_ctl/ms7200_ctl/N24_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -59585,7 +59422,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/iic_dri_rx/state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/iic_dri_rx/state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -59601,23 +59438,17 @@ L4;1 RS;1 Inst -param_manager_inst/param_modify_H/value[0]/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/iic_dri_rx/N80_0/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -ms72xx_ctl/iic_dri_rx/state_fsm[2:0]_71/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_rx/twr_en_ce_mux/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -59627,17 +59458,23 @@ L3;1 L4;1 Inst -ms72xx_ctl/iic_dri_tx/N461_5/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_rx/trans_byte_max[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -ms72xx_ctl/iic_dri_rx/N461_9/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_tx/N504/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -59647,7 +59484,17 @@ L3;1 L4;1 Inst -ms72xx_ctl/iic_dri_rx/state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/iic_dri_rx/N39/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +ms72xx_ctl/iic_dri_rx/state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -59680,14 +59527,20 @@ S0;1 S1;1 Inst -ms72xx_ctl/iic_dri_rx/N461_5/gateop_perm;gopLUT5 +ms72xx_ctl/ms7200_ctl/iic_trig/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst ms72xx_ctl/iic_dri_rx/state_reg[3]/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q @@ -59707,14 +59560,20 @@ S0;1 S1;1 Inst -ms72xx_ctl/iic_dri_rx/N461_11/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_rx/send_data[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst ms72xx_ctl/iic_dri_rx/state_reg[5]/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q @@ -59783,20 +59642,14 @@ L4;1 RS;1 Inst -ms72xx_ctl/iic_dri_rx/trans_byte_max[0]/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/iic_dri_rx/state_fsm[2:0]_39_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst ms72xx_ctl/iic_dri_rx/trans_byte[1]/opit_0_L5Q_perm;gopL5Q @@ -59847,30 +59700,30 @@ L4;1 RS;1 Inst -ms72xx_ctl/iic_dri_rx/twr_en/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/iic_dri_rx/N345_2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -ms72xx_ctl/iic_dri_rx/twr_en_ce_mux/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_rx/byte_over/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst ms72xx_ctl/iic_dri_rx/trans_byte_max[2]/opit_0;gopQ @@ -59884,7 +59737,7 @@ D;1 RS;1 Inst -ms72xx_ctl/iic_dri_rx/trans_byte[0]/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/iic_dri_rx/twr_en/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -59948,30 +59801,39 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_done_cdc/out/opit_0_L5Q_perm;gopL5Q +u_zoom_image/mult_image2[1][12]/opit_0_AQ_perm;gopAQ Pin CEOUT;2 +Cout;2 Q;2 RSOUT;2 -Z;2 +Y;2 CE;1 CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 RS;1 Inst -param_manager_inst/param_modify_H/N151_19/gateop_perm;gopLUT5 +ms72xx_ctl/ms7200_ctl/freq_ensure/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst ms72xx_ctl/iic_dri_tx/state_fsm[2:0]_70/gateop_perm;gopLUT5 @@ -60006,7 +59868,7 @@ D;1 RS;1 Inst -ms72xx_ctl/iic_dri_tx/N80_0/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_tx/N165_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -60016,7 +59878,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/iic_dri_tx/N499_inv/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N622_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -60066,7 +59928,7 @@ I13;1 I14;1 Inst -ms72xx_ctl/iic_dri_tx/N460/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_tx/N461_11/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -60076,30 +59938,30 @@ L3;1 L4;1 Inst -ms72xx_ctl/ms7210_ctl/iic_trig/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/iic_dri_tx/N499_inv/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -ms72xx_ctl/iic_dri_tx/N461_9/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_tx/byte_over/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst ms72xx_ctl/iic_dri_tx/twr_en_ce_mux/gateop_perm;gopLUT5 @@ -60112,7 +59974,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/iic_dri_tx/state_fsm[2:0]_71/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N983_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -60122,7 +59984,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/iic_dri_tx/N504/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_tx/N461_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -60143,20 +60005,14 @@ S0;1 S1;1 Inst -ms72xx_ctl/ms7210_ctl/addr[0]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/iic_dri_tx/N461_5/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst ms72xx_ctl/iic_dri_tx/N461_8_or[2]_2/gateop;gopMUX4TO1 @@ -60181,7 +60037,7 @@ S0;1 S1;1 Inst -ms72xx_ctl/iic_dri_tx/N461_11/gateop_perm;gopLUT5 +ms72xx_ctl/ms7210_ctl/N539/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -60191,7 +60047,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_rotate_A/N154/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_rx/N493_and[0][4]_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -60201,30 +60057,30 @@ L3;1 L4;1 Inst -ms72xx_ctl/iic_dri_tx/N493_or[0]_3/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_tx/state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -ms72xx_ctl/iic_dri_tx/state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/ms7210_ctl/N14_8/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst ms72xx_ctl/iic_dri_tx/N493_or[0]_5/gateop;gopMUX4TO1 @@ -60238,7 +60094,7 @@ S0;1 S1;1 Inst -ms72xx_ctl/iic_dri_tx/trans_bit[0]/opit_0_L5Q_perm;gopL5Q +u_zoom_image/image_h0[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -60254,7 +60110,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/iic_dri_tx/state_fsm[2:0]_39_3/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_tx/state_fsm[2:0]_7_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -60264,7 +60120,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/iic_dri_tx/start_en/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/iic_dri_tx/trans_en/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -60280,14 +60136,20 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7210_ctl/N2/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_tx/start_en/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst ms72xx_ctl/iic_dri_tx/data_out[0]/opit_0;gopQ @@ -60499,7 +60361,7 @@ D;1 RS;1 Inst -ms72xx_ctl/iic_dri_rx/fre_cnt[0]/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/iic_dri_rx/busy/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -60532,7 +60394,7 @@ S0;1 S1;1 Inst -ms72xx_ctl/iic_dri_tx/send_data[2]/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/iic_dri_tx/send_data[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -60548,7 +60410,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/iic_dri_tx/send_data[5]/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/iic_dri_tx/send_data[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -60580,7 +60442,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/iic_dri_tx/send_data[4]/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/ms7210_ctl/addr[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -60596,7 +60458,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7210_ctl/addr[3]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/iic_dri_tx/send_data[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -60644,7 +60506,7 @@ L4;1 RS;1 Inst -u_sync_vg/N28_mux8_5/gateop_perm;gopLUT5 +ms72xx_ctl/ms7210_ctl/N589/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -60654,7 +60516,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/iic_dri_tx/trans_en/opit_0_L5Q_perm;gopL5Q +u_zoom_image/imag_addr0[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -60670,33 +60532,17 @@ L4;1 RS;1 Inst -ms72xx_ctl/iic_dri_tx/state_fsm[2:0]_10/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -ms72xx_ctl/iic_dri_tx/trans_byte[0]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N59_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -param_manager_inst/param_rotate_A/value[0]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -60712,7 +60558,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/iic_dri_tx/N168_mux3_1/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_tx/state_fsm[2:0]_39_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -60722,39 +60568,30 @@ L3;1 L4;1 Inst -param_manager_inst/param_rotate_A/value[5]/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/iic_dri_tx/state_fsm[2:0]_53/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -param_manager_inst/param_modify_H/value[1]/opit_0_L5Q_perm;gopL5Q +u_zoom_image/N383.eq_6/gateop_perm;gopA Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -ms72xx_ctl/iic_dri_tx/trans_byte_max[0]/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/iic_dri_rx/trans_byte[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -60770,7 +60607,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/iic_dri_tx/state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/iic_dri_tx/twr_cnt[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -60803,20 +60640,14 @@ S0;1 S1;1 Inst -ms72xx_ctl/iic_dri_tx/state_reg[2]/opit_0_inv_L5Q;gopL5Q +ms72xx_ctl/iic_dri_tx/state_fsm[2:0]_10/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst ms72xx_ctl/iic_dri_tx/state_reg[3]/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q @@ -60836,7 +60667,7 @@ S0;1 S1;1 Inst -ms72xx_ctl/iic_dri_tx/N39/gateop_perm;gopLUT5 +ms72xx_ctl/ms7210_ctl/N2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -60912,7 +60743,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/iic_dri_tx/state_fsm[2:0]_31/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N620/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -60922,7 +60753,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/iic_dri_tx/trans_byte[2]/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/iic_dri_tx/trans_byte[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -60938,7 +60769,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/iic_dri_tx/trans_byte[1]/opit_0_L5Q;gopL5Q +ms72xx_ctl/iic_dri_tx/trans_byte[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -60970,7 +60801,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_rotate_A/value[3]/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/iic_dri_tx/state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -60986,14 +60817,20 @@ L4;1 RS;1 Inst -ms72xx_ctl/iic_dri_rx/state_fsm[2:0]_70/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_tx/trans_byte_max[0]/opit_0_L5Q;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst ms72xx_ctl/iic_dri_tx/trans_byte_max[2]/opit_0;gopQ @@ -61071,7 +60908,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/iic_dri_rx/N316_3/gateop_perm;gopLUT5 +u_zoom_image/N857_8[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -61081,7 +60918,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_rotate_A/N156_19/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_tx/N345_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -61091,14 +60928,22 @@ L3;1 L4;1 Inst -ms72xx_ctl/iic_dri_tx/N489_1/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N219_63[7]_2_muxf6_perm;gopLUT6 Pin +Y0;2 +Y1;2 Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +A0;1 +A1;1 +A2;1 +A3;1 +A4;1 +B0;1 +B1;1 +B2;1 +B3;1 +B4;1 +M;1 Inst ms72xx_ctl/iic_dri_tx/w_r_1d/opit_0_inv;gopQ @@ -61123,7 +60968,7 @@ D;1 RS;1 Inst -ms72xx_ctl/ms7200_ctl/N2082_1/gateop_perm;gopLUT5 +ms72xx_ctl/ms7200_ctl/N8_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -61143,7 +60988,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/ms7200_ctl/N40_9/gateop_perm;gopLUT5 +ms72xx_ctl/ms7200_ctl/N1877/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -61153,7 +60998,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/ms7200_ctl/N24_4/gateop_perm;gopLUT5 +ms72xx_ctl/ms7200_ctl/N63_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -61163,7 +61008,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/ms7200_ctl/N63_5/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_rx/state_fsm[2:0]_10/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -61173,7 +61018,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/iic_dri_rx/state_fsm[2:0]_10/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_rx/N499_inv/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -61183,17 +61028,23 @@ L3;1 L4;1 Inst -ms72xx_ctl/ms7200_ctl/N8_5/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_rx/twr_cnt[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -ms72xx_ctl/iic_dri_rx/N39/gateop_perm;gopLUT5 +ms72xx_ctl/ms7200_ctl/N1797/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -61203,7 +61054,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/ms7200_ctl/N1797/gateop_perm;gopLUT5 +ms72xx_ctl/ms7200_ctl/N40_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -61532,7 +61383,7 @@ WR_EOP;1 WR_ERR;1 Inst -ms72xx_ctl/ms7200_ctl/N1844_2/gateop_perm;gopLUT5 +ms72xx_ctl/ms7200_ctl/N1844_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -61542,17 +61393,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/ms7200_ctl/N1366_6/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -ms72xx_ctl/ms7200_ctl/N1872_5/gateop_perm;gopLUT5 +ms72xx_ctl/ms7200_ctl/N2082_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -61562,7 +61403,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/ms7200_ctl/N1844_5_2/gateop_perm;gopLUT5 +ms72xx_ctl/ms7200_ctl/N1366_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -61572,7 +61413,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/iic_dri_rx/N461_8_or[1][3]/gateop_perm;gopLUT5 +ms72xx_ctl/ms7200_ctl/N1872_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -61582,7 +61423,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/ms7200_ctl/N1895/gateop_perm;gopLUT5 +ms72xx_ctl/ms7200_ctl/N1845_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -61592,7 +61433,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/ms7200_ctl/N1872_7/gateop_perm;gopLUT5 +ms72xx_ctl/ms7200_ctl/N2031/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -61602,17 +61443,23 @@ L3;1 L4;1 Inst -ms72xx_ctl/ms7200_ctl/N2053_1/gateop_perm;gopLUT5 +ms72xx_ctl/ms7200_ctl/dri_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -ms72xx_ctl/ms7200_ctl/N1844_7_or[1]_3/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -61622,7 +61469,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/ms7200_ctl/N1845_1/gateop_perm;gopLUT5 +u_zoom_image/N306_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -61632,71 +61479,47 @@ L3;1 L4;1 Inst -ms72xx_ctl/ms7210_ctl/state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/ms7200_ctl/N1879_9/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -ms72xx_ctl/ms7200_ctl/freq_ensure/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/ms7200_ctl/N1954_1_or[0]_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -ms72xx_ctl/iic_dri_rx/send_data[0]/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/ms7210_ctl/N537_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/ms7200_ctl/N1879_11/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -ms72xx_ctl/ms7200_ctl/N1879_5/gateop_perm;gopLUT5 +ms72xx_ctl/ms7200_ctl/N1953/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -61716,27 +61539,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/ms7200_ctl/N1989_1_or[6]_1/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -ms72xx_ctl/ms7200_ctl/N1844_5_1/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -ms72xx_ctl/ms7200_ctl/N2031/gateop_perm;gopLUT5 +ms72xx_ctl/ms7210_ctl/N580/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -61746,7 +61549,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_rotate_A/N148_5/gateop_perm;gopLUT5 +ms72xx_ctl/ms7200_ctl/N1955/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -61756,7 +61559,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/ms7200_ctl/N1955/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_rx/N461_8_and[3][3]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -61766,7 +61569,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/ms7200_ctl/dri_cnt[8:0]_130/gateop_perm;gopLUT5 +ms72xx_ctl/ms7200_ctl/dri_cnt[8:0]_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -61776,7 +61579,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/ms7200_ctl/N1954_1_or[10]_3/gateop_perm;gopLUT5 +ms72xx_ctl/ms7200_ctl/N1989_1_or[4]_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -61786,17 +61589,23 @@ L3;1 L4;1 Inst -ms72xx_ctl/ms7200_ctl/N1989_1_or[0]_4/gateop_perm;gopLUT5 +ms72xx_ctl/ms7200_ctl/addr[8]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -ms72xx_ctl/ms7200_ctl/cmd_index[0]/opit_0_inv_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -61812,17 +61621,23 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7200_ctl/N2071_1/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -ms72xx_ctl/ms7200_ctl/N1844_7_or[1]_2_2/gateop_perm;gopLUT5 +ms72xx_ctl/ms7200_ctl/N1989_1_or[0]_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -61832,23 +61647,17 @@ L3;1 L4;1 Inst -ms72xx_ctl/ms7200_ctl/addr[6]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/iic_dri_rx/N460/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -ms72xx_ctl/ms7200_ctl/N2085/gateop_perm;gopLUT5 +ms72xx_ctl/ms7200_ctl/dri_cnt[8:0]_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -61858,7 +61667,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5 +ms72xx_ctl/ms7200_ctl/N2076/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -61868,39 +61677,27 @@ L3;1 L4;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/ms7200_ctl/N2085/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -ms72xx_ctl/ms7200_ctl/addr[1]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/iic_dri_rx/N461_8_and[5][3]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -ms72xx_ctl/ms7200_ctl/iic_trig/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/ms7200_ctl/addr[6]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -61916,7 +61713,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7200_ctl/N1954_1_or[0]_6/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[5]_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -61926,7 +61723,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/ms7200_ctl/data_in[0]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/ms7200_ctl/addr[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -61942,7 +61739,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7200_ctl/addr[2]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/ms7200_ctl/addr[9]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -61958,7 +61755,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7200_ctl/addr[4]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/ms7200_ctl/addr[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -61974,7 +61771,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7200_ctl/addr[5]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/ms7200_ctl/addr[7]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -61990,7 +61787,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7200_ctl/addr[13]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/ms7200_ctl/addr[5]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -62006,7 +61803,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7200_ctl/addr[7]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/ms7200_ctl/addr[12]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -62022,7 +61819,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7200_ctl/addr[12]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/ms7200_ctl/data_in[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -62054,7 +61851,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7200_ctl/addr[9]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/ms7200_ctl/data_in[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -62070,7 +61867,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7200_ctl/data_in[2]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/ms7200_ctl/addr[13]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -62086,7 +61883,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7200_ctl/data_in[1]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/ms7200_ctl/cmd_index[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -62102,7 +61899,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/iic_dri_rx/send_data[1]/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/ms7200_ctl/data_in[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -62129,7 +61926,7 @@ D;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N81/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_20/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -62265,23 +62062,17 @@ I4;1 RS;1 Inst -ms72xx_ctl/ms7200_ctl/data_in[3]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/ms7200_ctl/N2071_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -ms72xx_ctl/ms7200_ctl/data_in[4]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/ms7200_ctl/data_in[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -62313,7 +62104,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7200_ctl/data_in[5]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/ms7200_ctl/data_in[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -62329,7 +62120,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7200_ctl/addr[3]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/ms7200_ctl/data_in[5]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -62345,17 +62136,23 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5 +ms72xx_ctl/ms7200_ctl/addr[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -ms72xx_ctl/ms7200_ctl/addr[0]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/ms7200_ctl/addr[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -62371,7 +62168,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7200_ctl/N1953/gateop_perm;gopLUT5 +ms72xx_ctl/ms7200_ctl/N1954_1_or[0]_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -62381,7 +62178,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/ms7200_ctl/dri_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/ms7200_ctl/dri_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -62397,7 +62194,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7200_ctl/dri_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/ms7200_ctl/dri_cnt[5]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -62413,7 +62210,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7200_ctl/dri_cnt[8]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/ms7200_ctl/dri_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -62429,7 +62226,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -62445,7 +62242,17 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7200_ctl/dri_cnt[5]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/ms7200_ctl/N8_3/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +ms72xx_ctl/ms7200_ctl/dri_cnt[6]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -62461,7 +62268,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7200_ctl/dri_cnt[6]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/ms7200_ctl/dri_cnt[7]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -62477,7 +62284,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7200_ctl/dri_cnt[7]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/ms7200_ctl/dri_cnt[8]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -62503,23 +62310,40 @@ L3;1 L4;1 Inst -ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/ms7200_ctl/dri_cnt[8:0]_116_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -ms72xx_ctl/ms7200_ctl/addr[8]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/ms7200_ctl/dri_cnt[8:0]_168/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[7].u_divider_step/N20.fsub_8/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + +Inst +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -62535,7 +62359,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7200_ctl/N2083/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_rx/N165_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -62611,39 +62435,27 @@ D;1 RS;1 Inst -ms72xx_ctl/ms7200_ctl/state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/iic_dri_rx/N461_9/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -ms72xx_ctl/ms7200_ctl/state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/iic_dri_rx/N489_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -param_manager_inst/param_modify_H/N149/gateop_perm;gopLUT5 +u_zoom_image/N234_0/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -62653,7 +62465,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/ms7200_ctl/state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/ms7200_ctl/state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -62685,17 +62497,23 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7200_ctl/N1359_1/gateop_perm;gopLUT5 +ms72xx_ctl/ms7200_ctl/state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -ms72xx_ctl/ms7200_ctl/init_over/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/iic_dri_rx/send_data[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -62728,17 +62546,7 @@ S0;1 S1;1 Inst -ms72xx_ctl/iic_dri_tx/N461_8_or[1][2]/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -ms72xx_ctl/ms7210_ctl/N14_8/gateop_perm;gopLUT5 +ms72xx_ctl/ms7210_ctl/N527/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -62748,7 +62556,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/iic_dri_tx/state_fsm[2:0]_7_2/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -62758,7 +62566,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/ms7210_ctl/N537_1/gateop_perm;gopLUT5 +ms72xx_ctl/ms7210_ctl/N14_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -62768,7 +62576,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/ms7210_ctl/N390_3/gateop_perm;gopLUT5 +ms72xx_ctl/ms7210_ctl/N559_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -62778,7 +62586,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/ms7210_ctl/N382_3/gateop_perm;gopLUT5 +ms72xx_ctl/ms7210_ctl/N124_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -62788,7 +62596,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/iic_dri_tx/N165_5/gateop_perm;gopLUT5 +ms72xx_ctl/ms7210_ctl/N556_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -62912,7 +62720,7 @@ WEA;1 WEB;1 Inst -ms72xx_ctl/ms7210_ctl/N405_9/gateop_perm;gopLUT5 +ms72xx_ctl/ms7210_ctl/N390_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -62922,7 +62730,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/ms7210_ctl/N527/gateop_perm;gopLUT5 +ms72xx_ctl/ms7210_ctl/N405_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -62942,7 +62750,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/ms7210_ctl/N403_18/gateop_perm;gopLUT5 +u_zoom_image/N919/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -62962,7 +62770,7 @@ L3;1 L4;1 Inst -param_manager_inst/offsetY_load/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/ms7210_ctl/delay_cnt[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -62988,33 +62796,33 @@ L3;1 L4;1 Inst -ms72xx_ctl/ms7210_ctl/delay_cnt[0]/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/ms7210_ctl/N403_18/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -ms72xx_ctl/ms7210_ctl/N556_1/gateop_perm;gopLUT5 +ms72xx_ctl/ms7210_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -ms72xx_ctl/ms7210_ctl/dri_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/ms7210_ctl/iic_trig/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -63030,33 +62838,33 @@ L4;1 RS;1 Inst -u_sync_vg/N184_14/gateop_perm;gopLUT5 +ms72xx_ctl/ms7210_ctl/state_reg[5]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_rotate_image/image_h_blank_valid/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/ms7210_ctl/N586/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -ms72xx_ctl/ms7210_ctl/dri_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_zoom_image/imag_addr1[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -63082,7 +62890,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/ms7210_ctl/N586/gateop_perm;gopLUT5 +ms72xx_ctl/ms7210_ctl/N62_ac2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -63092,7 +62900,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/ms7210_ctl/N589/gateop_perm;gopLUT5 +ms72xx_ctl/ms7210_ctl/N36/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -63102,33 +62910,33 @@ L3;1 L4;1 Inst -ms72xx_ctl/ms7210_ctl/N591/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_tx/trans_byte[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -ms72xx_ctl/ms7210_ctl/addr[2]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/ms7210_ctl/N591/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -ms72xx_ctl/ms7210_ctl/N580/gateop_perm;gopLUT5 +ms72xx_ctl/ms7200_ctl/N1879_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -63138,7 +62946,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/ms7210_ctl/addr[5]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/ms7210_ctl/addr[8]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -63154,7 +62962,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7210_ctl/addr[4]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/ms7210_ctl/addr[5]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -63170,7 +62978,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7210_ctl/addr[8]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/ms7210_ctl/data_in[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -63186,7 +62994,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7210_ctl/addr[9]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/ms7210_ctl/data_in[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -63202,7 +63010,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7210_ctl/data_in[0]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/ms7210_ctl/addr[9]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -63218,7 +63026,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7210_ctl/addr[7]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/ms7210_ctl/addr[6]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -63234,7 +63042,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7210_ctl/addr[11]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/ms7210_ctl/addr[7]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -63250,20 +63058,14 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7210_ctl/data_in[6]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/ms7200_ctl/N1918/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst ms72xx_ctl/ms7210_ctl/addr[10]/opit_0_inv_L5Q_perm;gopL5Q @@ -63282,7 +63084,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7210_ctl/data_in[1]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/ms7210_ctl/data_in[6]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -63298,7 +63100,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7210_ctl/data_in[2]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/ms7210_ctl/addr[11]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -63314,20 +63116,14 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7210_ctl/data_in[5]/opit_0_inv_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1109/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst ms72xx_ctl/ms7210_ctl/busy_1d/opit_0;gopQ @@ -63341,7 +63137,7 @@ D;1 RS;1 Inst -udp_wr_mem_inst/N538_16/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[5]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -63431,7 +63227,7 @@ I14;1 RS;1 Inst -ms72xx_ctl/ms7210_ctl/data_in[4]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/ms7210_ctl/data_in[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -63463,7 +63259,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7210_ctl/addr[1]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/ms7210_ctl/data_in[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -63479,7 +63275,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/iic_dri_tx/send_data[1]/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/ms7210_ctl/init_over/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -63495,7 +63291,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/iic_dri_tx/send_data[0]/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/ms7210_ctl/data_in[5]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -63511,7 +63307,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7210_ctl/data_in[7]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/ms7210_ctl/state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -63527,7 +63323,7 @@ L4;1 RS;1 Inst -param_manager_inst/selected[8]/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/ms7210_ctl/data_in[7]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -63543,20 +63339,14 @@ L4;1 RS;1 Inst -udp_wr_mem_inst/state_reg[1]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N455_7/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst ms72xx_ctl/ms7210_ctl/N403_10/gateop_perm;gopLUT5 @@ -63858,7 +63648,7 @@ I4;1 RS;1 Inst -ms72xx_ctl/ms7210_ctl/dri_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/ms7210_ctl/dri_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -63874,14 +63664,20 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7200_ctl/N1844_7_or[1]_5/gateop_perm;gopLUT5 +ms72xx_ctl/ms7210_ctl/dri_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst ms72xx_ctl/ms7210_ctl/dri_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q @@ -63900,7 +63696,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7210_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q +u_zoom_image/imag_addr0[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -63916,23 +63712,17 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7210_ctl/state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q +u_zoom_image/ram_sta_fsm[3:0]_7/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -ms72xx_ctl/iic_dri_tx/N165_1/gateop_perm;gopLUT5 +ms72xx_ctl/ms7210_ctl/N403_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -63942,20 +63732,14 @@ L3;1 L4;1 Inst -u_sync_vg/h_count[0]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[9]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst ms72xx_ctl/ms7210_ctl/state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q @@ -63974,7 +63758,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7210_ctl/state_reg[5]/opit_0_inv_L5Q_perm;gopL5Q +ms72xx_ctl/ms7210_ctl/state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -64006,14 +63790,20 @@ L4;1 RS;1 Inst -u_sync_vg/N184_13/gateop_perm;gopLUT5 +ms72xx_ctl/ms7210_ctl/dri_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst ms72xx_ctl/ms7210_ctl/w_r/opit_0_inv_L5Q_perm;gopL5Q @@ -64032,20 +63822,14 @@ L4;1 RS;1 Inst -ms72xx_ctl/iic_dri_tx/byte_over/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/ms7210_ctl/N382_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst ms72xx_ctl/rstn/opit_0;gopQ @@ -64091,7 +63875,7 @@ L3;1 L4;1 Inst -param_manager_inst/N314_26/gateop_perm;gopLUT5 +param_manager_inst/N314_24/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -64101,7 +63885,7 @@ L3;1 L4;1 Inst -param_manager_inst/N314_24/gateop_perm;gopLUT5 +param_manager_inst/N314_28/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -64111,14 +63895,20 @@ L3;1 L4;1 Inst -param_manager_inst/N335/gateop_perm;gopLUT5 +u_sync_vg/hdmi_image_data0[9]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst param_manager_inst/N344/gateop_perm;gopLUT5 @@ -64131,7 +63921,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_17_10/gateop_perm;gopLUT5 +param_manager_inst/param_zoom/N63_mux9_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -64141,7 +63931,7 @@ L3;1 L4;1 Inst -param_manager_inst/key_debounce_key_left/pluse_ms/opit_0_L5Q_perm;gopL5Q +param_manager_inst/ms_cnt[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -64157,7 +63947,7 @@ L4;1 RS;1 Inst -param_manager_inst/N314_28/gateop_perm;gopLUT5 +param_manager_inst/N314_26/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -64167,20 +63957,24 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/real_add_cnt[1]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/N9_mux11/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +param_manager_inst/N335/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst param_manager_inst/clk_ms/opit_0_L5Q_perm;gopL5Q @@ -64199,7 +63993,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[6]/gateop_perm;gopLUT5 +param_manager_inst/param_filiter1_mode/N157_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -64209,27 +64003,20 @@ L3;1 L4;1 Inst -param_manager_inst/N345/gateop_perm;gopLUT5 +param_manager_inst/key_debounce_key_left/change/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 - -Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N361.eq_8/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +RS;1 Inst param_manager_inst/N9_mux15_4/gateop_perm;gopLUT5 @@ -64302,7 +64089,7 @@ D;1 RS;1 Inst -param_manager_inst/param_filiter1_mode/pluse/opit_0_L5Q_perm;gopL5Q +param_manager_inst/rotate_load/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -64318,7 +64105,7 @@ L4;1 RS;1 Inst -param_manager_inst/index[0]/opit_0_L5Q;gopL5Q +param_manager_inst/index[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -64366,7 +64153,7 @@ L4;1 RS;1 Inst -param_manager_inst/key_debounce_key_left/N20_mux2/gateop_perm;gopLUT5 +param_manager_inst/param_zoom/N148_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -64376,7 +64163,7 @@ L3;1 L4;1 Inst -u_zoom_image/N135_mux9_4/gateop_perm;gopLUT5 +param_manager_inst/key_debounce_key_left/N20_mux4_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -64386,7 +64173,7 @@ L3;1 L4;1 Inst -param_manager_inst/key_debounce_key_left/N47_12/gateop_perm;gopLUT5 +param_manager_inst/key_debounce_key_left/N89_5[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -64396,7 +64183,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_osd_startX/N102_8/gateop_perm;gopLUT5 +param_manager_inst/param_osd_startX/N102_10/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -64406,7 +64193,7 @@ L3;1 L4;1 Inst -param_manager_inst/key_debounce_key_left/N89_5[2]/gateop_perm;gopLUT5 +param_manager_inst/key_debounce_key_left/N88/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -64416,7 +64203,7 @@ L3;1 L4;1 Inst -param_manager_inst/key_debounce_key_left/N20_mux4_1/gateop_perm;gopLUT5 +param_manager_inst/param_modify_V/N63_mux8_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -64426,7 +64213,7 @@ L3;1 L4;1 Inst -param_manager_inst/key_debounce_key_left/N88/gateop_perm;gopLUT5 +param_manager_inst/key_debounce_key_left/N47_12/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -64436,23 +64223,17 @@ L3;1 L4;1 Inst -param_manager_inst/key_debounce_key_left/cnt[1]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_modify_V/N140/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -param_manager_inst/key_debounce_key_left/change/opit_0_L5Q_perm;gopL5Q +param_manager_inst/key_debounce_key_left/cnt[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -64468,20 +64249,14 @@ L4;1 RS;1 Inst -param_manager_inst/key_debounce_key_left/cnt[0]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_modify_H/N151_19/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst param_manager_inst/key_debounce_key_left/clk_ms_ff0/opit_0;gopQ @@ -64506,7 +64281,7 @@ D;1 RS;1 Inst -param_manager_inst/key_debounce_key_left/cnt[2]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/key_debounce_key_left/cnt[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -64522,14 +64297,20 @@ L4;1 RS;1 Inst -u_zoom_image/N858_inv/gateop_perm;gopLUT5 +param_manager_inst/key_debounce_key_left/cnt[2]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst param_manager_inst/key_debounce_key_left/cnt[3]/opit_0_L5Q_perm;gopL5Q @@ -64548,36 +64329,24 @@ L4;1 RS;1 Inst -param_manager_inst/key_debounce_key_left/cnt[4]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/key_debounce_key_left/N20_mux2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -param_manager_inst/index[1]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/N345/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst param_manager_inst/key_debounce_key_left/key_ff0/opit_0;gopQ @@ -64602,7 +64371,7 @@ D;1 RS;1 Inst -param_manager_inst/N9_mux11/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N19_mux2_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -64612,17 +64381,23 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N748/gateop_perm;gopLUT5 +param_manager_inst/modify_V_load/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/key_debounce_key_restore/N47_7/gateop_perm;gopLUT5 +param_manager_inst/key_debounce_key_restore/N87/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -64642,7 +64417,7 @@ L3;1 L4;1 Inst -param_manager_inst/key_debounce_key_restore/N87/gateop_perm;gopLUT5 +param_manager_inst/key_debounce_key_restore/N47_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -64662,49 +64437,43 @@ L3;1 L4;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/key_debounce_key_restore/N88/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N102_7/gateop_perm;gopLUT5 +param_manager_inst/key_debounce_key_restore/cnt[3]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/key_debounce_key_restore/cnt[0]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/pixels_shifter_inst/N135/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[5]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/key_debounce_key_restore/cnt[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -64736,7 +64505,7 @@ L4;1 RS;1 Inst -param_manager_inst/key_debounce_key_restore/cnt[3]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/key_debounce_key_restore/cnt[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -64752,23 +64521,17 @@ L4;1 RS;1 Inst -param_manager_inst/key_debounce_key_restore/cnt[4]/opit_0_L5Q_perm;gopL5Q +u_sync_vg/N184_13/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -param_manager_inst/key_debounce_key_restore/N20_mux4_1/gateop_perm;gopLUT5 +udp_osd_inst/N69_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -64800,17 +64563,23 @@ D;1 RS;1 Inst -param_manager_inst/key_debounce_key_right/N87/gateop_perm;gopLUT5 +param_manager_inst/osd_startY_load/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/key_debounce_key_right/N47_6/gateop_perm;gopLUT5 +param_manager_inst/key_debounce_key_right/N20_mux4_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -64820,30 +64589,30 @@ L3;1 L4;1 Inst -param_manager_inst/key_debounce_key_right/N47_7/gateop_perm;gopLUT5 +rstn_1ms[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/key_debounce_key_restore/cnt[1]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/key_debounce_key_right/N47_7/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst param_manager_inst/key_debounce_key_right/N89_5[2]/gateop_perm;gopLUT5 @@ -64866,7 +64635,7 @@ L3;1 L4;1 Inst -param_manager_inst/key_debounce_key_right/pressed/opit_0_L5Q_perm;gopL5Q +param_manager_inst/key_debounce_key_right/change/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -64882,7 +64651,7 @@ L4;1 RS;1 Inst -param_manager_inst/key_debounce_key_right/cnt[4]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/key_debounce_key_right/cnt[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -64898,14 +64667,20 @@ L4;1 RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_14/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/n_ff1[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst param_manager_inst/key_debounce_key_right/cnt[1]/opit_0_L5Q_perm;gopL5Q @@ -64924,7 +64699,7 @@ L4;1 RS;1 Inst -param_manager_inst/key_debounce_key_right/cnt[2]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/key_debounce_key_right/cnt[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -64940,33 +64715,33 @@ L4;1 RS;1 Inst -param_manager_inst/key_debounce_key_right/cnt[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N19_inv_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -param_manager_inst/key_debounce_key_right/N20_mux2/gateop_perm;gopLUT5 +param_manager_inst/key_debounce_key_right/cnt[4]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/key_debounce_key_restore/pressed/opit_0_L5Q_perm;gopL5Q +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/addr_bus_rd_ce[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -65004,7 +64779,7 @@ D;1 RS;1 Inst -param_manager_inst/key_debounce_key_restore/N20_mux2/gateop_perm;gopLUT5 +param_manager_inst/key_debounce_key_right/N87/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -65058,20 +64833,14 @@ D;1 RS;1 Inst -param_manager_inst/modify_V_load/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_filiter1_mode/key_debounce_inst2/N20_mux2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst param_manager_inst/modify_S_flags_ff0/opit_0;gopQ @@ -65118,7 +64887,7 @@ D;1 RS;1 Inst -param_manager_inst/param_rotate/N102_11/gateop_perm;gopLUT5 +param_manager_inst/param_modify_S/N63_mux8_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -65172,7 +64941,7 @@ D;1 RS;1 Inst -param_manager_inst/param_filiter1_mode/N152_6/gateop_perm;gopLUT5 +param_manager_inst/param_modify_V/N151_19/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -65182,7 +64951,7 @@ L3;1 L4;1 Inst -param_manager_inst/N9_mux4_3/gateop_perm;gopLUT5 +param_manager_inst/N9_mux9_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -65452,14 +65221,20 @@ D;1 RS;1 Inst -param_manager_inst/param_offsetX/N72/gateop_perm;gopLUT5 +udp_wr_mem_inst/flags[16]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst param_manager_inst/offsetY_flags_ff0/opit_0;gopQ @@ -65506,20 +65281,14 @@ D;1 RS;1 Inst -param_manager_inst/param_offsetX/value[0]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_modify_S/N148_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst param_manager_inst/osd_char_height_flags_ff0/opit_0;gopQ @@ -65566,14 +65335,20 @@ D;1 RS;1 Inst -param_manager_inst/param_offsetX/N156_1/gateop_perm;gopLUT5 +param_manager_inst/osd_char_width_load/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst param_manager_inst/osd_char_width_flags_ff0/opit_0;gopQ @@ -65620,7 +65395,7 @@ D;1 RS;1 Inst -param_manager_inst/param_osd_char_width/N63_mux10_4/gateop_perm;gopLUT5 +param_manager_inst/param_osd_char_width/N148_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -65674,14 +65449,20 @@ D;1 RS;1 Inst -param_manager_inst/param_offsetX/N148_3/gateop_perm;gopLUT5 +param_manager_inst/param_filiter1_mode/key_debounce_inst2/pressed/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst param_manager_inst/osd_startY_flags_ff0/opit_0;gopQ @@ -65728,7 +65509,7 @@ D;1 RS;1 Inst -param_manager_inst/param_osd_startY/N149_49/gateop_perm;gopLUT5 +param_manager_inst/param_osd_startY/N156_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -65851,7 +65632,7 @@ I3;1 I4;1 Inst -param_manager_inst/param_filiter1_mode/cnt[5]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_start_i_ff/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -65867,7 +65648,23 @@ L4;1 RS;1 Inst -param_manager_inst/N33_mux3_1/gateop_perm;gopLUT5 +param_manager_inst/param_filiter1_mode/cnt[7]/opit_0_L5Q_perm;gopL5Q +Pin +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 + +Inst +param_manager_inst/param_filiter1_mode/N116/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -65893,7 +65690,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_modify_H/cnt[5]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_offsetX/cnt[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -65909,23 +65706,17 @@ L4;1 RS;1 Inst -param_manager_inst/selected[4]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_filiter1_mode/N161_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -param_manager_inst/param_filiter1_mode/cnt[2]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_osd_startY/value[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -65941,17 +65732,23 @@ L4;1 RS;1 Inst -param_manager_inst/param_filiter2_mode/N153/gateop_perm;gopLUT5 +param_manager_inst/param_filiter1_mode/value[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_filiter1_mode/N153/gateop_perm;gopLUT5 +param_manager_inst/param_filiter1_mode/N153_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -65961,17 +65758,23 @@ L3;1 L4;1 Inst -param_manager_inst/param_modify_V/N150_1/gateop_perm;gopLUT5 +param_manager_inst/selected[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_filiter1_mode/N153_1/gateop_perm;gopLUT5 +param_manager_inst/param_filiter2_mode/N153/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -65981,23 +65784,17 @@ L3;1 L4;1 Inst -udp_wr_mem_inst/flags[0]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_rotate_A/N156_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_fsm[6:0]_34/gateop_perm;gopLUT5 +param_manager_inst/param_rotate/N102_11/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -66007,7 +65804,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_filiter1_mode/cnt[0]/opit_0_L5Q;gopL5Q +param_manager_inst/param_filiter1_mode/cnt[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -66039,7 +65836,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_filiter1_mode/cnt[1]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_offsetX/cnt[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -66055,7 +65852,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_filiter1_mode/cnt[4]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_modify_H/cnt[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -66071,33 +65868,26 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_16_10/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -param_manager_inst/param_filiter1_mode/cnt[6]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_modify_H/cnt[11]/opit_0_AQ_perm;gopAQ Pin CEOUT;2 +Cout;2 Q;2 RSOUT;2 -Z;2 +Y;2 CE;1 CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 RS;1 Inst -param_manager_inst/param_filiter1_mode/cnt[7]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_filiter1_mode/cnt[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -66139,24 +65929,31 @@ L3;1 L4;1 Inst -param_manager_inst/param_osd_char_height/cnt[11]/opit_0_AQ_perm;gopAQ +param_manager_inst/param_filiter1_mode/cnt[9]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 -Cout;2 Q;2 RSOUT;2 -Y;2 +Z;2 CE;1 CLK;1 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 RS;1 +Inst +param_manager_inst/param_filiter1_mode/N122/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + Inst param_manager_inst/param_filiter1_mode/cnt[11]/opit_0_L5Q_perm;gopL5Q Pin @@ -66174,7 +65971,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_16_5/gateop_perm;gopLUT5 +param_manager_inst/param_osd_startY/N76_mux7_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -66184,26 +65981,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_rotate/cnt[11]/opit_0_AQ_perm;gopAQ -Pin -CEOUT;2 -Cout;2 -Q;2 -RSOUT;2 -Y;2 -CE;1 -CLK;1 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 -RS;1 - -Inst -param_manager_inst/param_filiter1_mode/key_debounce_inst1/N47_6/gateop_perm;gopLUT5 +param_manager_inst/param_filiter1_mode/key_debounce_inst1/N88/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -66213,7 +65991,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_filiter1_mode/key_debounce_inst1/N47_7/gateop_perm;gopLUT5 +param_manager_inst/param_filiter1_mode/key_debounce_inst1/N47_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -66223,7 +66001,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_filiter1_mode/key_debounce_inst1/cnt[4]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_filiter1_mode/key_debounce_inst1/cnt[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -66239,39 +66017,27 @@ L4;1 RS;1 Inst -param_manager_inst/param_filiter1_mode/key_debounce_inst1/change/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_filiter1_mode/key_debounce_inst1/N87/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -param_manager_inst/param_filiter1_mode/key_debounce_inst2/pressed/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_filiter1_mode/key_debounce_inst1/N89_5[2]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -param_manager_inst/param_filiter1_mode/key_debounce_inst1/pressed/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_modify_H/value[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -66287,7 +66053,7 @@ L4;1 RS;1 Inst -u_zoom_image/cnt_h[1]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_filiter1_mode/key_debounce_inst1/cnt[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -66303,7 +66069,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_filiter1_mode/key_debounce_inst1/cnt[1]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/selected[12]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -66319,7 +66085,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_filiter1_mode/key_debounce_inst1/cnt[2]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_filiter1_mode/key_debounce_inst1/cnt[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -66351,7 +66117,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_filiter1_mode/key_debounce_inst1/N20_mux4_1/gateop_perm;gopLUT5 +param_manager_inst/param_modify_S/N76_mux8_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -66361,7 +66127,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[0]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_filiter1_mode/key_debounce_inst1/cnt[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -66376,6 +66142,16 @@ L3;1 L4;1 RS;1 +Inst +param_manager_inst/param_modify_H/N63_mux5_5/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + Inst param_manager_inst/param_filiter1_mode/key_debounce_inst1/key_ff0/opit_0;gopQ Pin @@ -66399,7 +66175,7 @@ D;1 RS;1 Inst -param_manager_inst/param_rotate/N102_12/gateop_perm;gopLUT5 +param_manager_inst/param_modify_S/N154/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -66409,7 +66185,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_filiter1_mode/key_debounce_inst2/N20_mux4_1/gateop_perm;gopLUT5 +param_manager_inst/param_filiter1_mode/key_debounce_inst2/N47_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -66419,7 +66195,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_filiter1_mode/key_debounce_inst2/N87/gateop_perm;gopLUT5 +param_manager_inst/param_osd_startX/N102_11/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -66429,7 +66205,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_filiter1_mode/key_debounce_inst2/N47_7/gateop_perm;gopLUT5 +param_manager_inst/param_filiter1_mode/key_debounce_inst2/N87/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -66439,7 +66215,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_filiter1_mode/key_debounce_inst2/cnt[3]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_filiter1_mode/key_debounce_inst2/cnt[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -66455,7 +66231,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_filiter1_mode/key_debounce_inst2/N89_5[2]/gateop_perm;gopLUT5 +param_manager_inst/param_filiter1_mode/key_debounce_inst2/N88/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -66465,23 +66241,17 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_filiter1_mode/key_debounce_inst2/N89_5[2]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -param_manager_inst/param_filiter1_mode/key_debounce_inst2/N88/gateop_perm;gopLUT5 +udp_wr_mem_inst/N204/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -66491,14 +66261,20 @@ L3;1 L4;1 Inst -param_manager_inst/param_filiter1_mode/key_debounce_inst2/N47_6/gateop_perm;gopLUT5 +param_manager_inst/param_osd_startX/pluse/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst param_manager_inst/param_filiter1_mode/key_debounce_inst2/cnt[1]/opit_0_L5Q_perm;gopL5Q @@ -66533,7 +66309,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_filiter1_mode/key_debounce_inst2/cnt[4]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_filiter1_mode/key_debounce_inst2/cnt[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -66549,7 +66325,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[3]/gateop_perm;gopLUT5 +param_manager_inst/param_filiter1_mode/key_debounce_inst2/N47_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -66559,7 +66335,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5 +param_manager_inst/param_modify_H/N72/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -66591,7 +66367,7 @@ D;1 RS;1 Inst -param_manager_inst/param_modify_H/N102_10/gateop_perm;gopLUT5 +udp_wr_mem_inst/N244/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -66601,31 +66377,30 @@ L3;1 L4;1 Inst -param_manager_inst/param_filiter2_mode/N152_1/gateop_perm;gopLUT5 +param_manager_inst/param_osd_char_height/pluse/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_filiter1_mode/value[0]/opit_0_MUX4TO1Q;gopMUX4TO1Q +image_filiter_inst/hybrid_filter_inst/N106_90/gateop_perm;gopLUT5 Pin -CEOUT;2 -F;2 -Q;2 -RSOUT;2 -CE;1 -CLK;1 -I0;1 -I1;1 -I2;1 -I3;1 -RS;1 -S0;1 -S1;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst param_manager_inst/param_filiter1_mode/value[1]/opit_0_MUX4TO1Q;gopMUX4TO1Q @@ -66644,6 +66419,16 @@ RS;1 S0;1 S1;1 +Inst +u_zoom_image/N238_0/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + Inst param_manager_inst/param_filiter1_mode/value[2]/opit_0_MUX4TO1Q;gopMUX4TO1Q Pin @@ -66682,7 +66467,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_modify_H/N102_8/gateop_perm;gopLUT5 +param_manager_inst/param_rotate/N72/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -66692,7 +66477,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_filiter1_mode/N122/gateop_perm;gopLUT5 +param_manager_inst/param_filiter1_mode/N152_5_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -66702,7 +66487,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_osd_char_height/N102_11/gateop_perm;gopLUT5 +param_manager_inst/param_modify_V/N142/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -66783,7 +66568,7 @@ I13;1 I14;1 Inst -param_manager_inst/param_modify_H/N63_mux5_6/gateop_perm;gopLUT5 +param_manager_inst/param_modify_H/N76_mux5_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -66793,7 +66578,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_modify_H/N76_mux5_5/gateop_perm;gopLUT5 +param_manager_inst/param_modify_H/N154/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -66803,39 +66588,27 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_osd_startX/N153_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[3]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_modify_H/N76_mux6/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N10/gateop_perm;gopLUT5 +param_manager_inst/param_modify_H/N156_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -66845,17 +66618,23 @@ L3;1 L4;1 Inst -param_manager_inst/param_modify_H/N76_mux8_3/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/modified_v_data[1]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_modify_H/N154_2/gateop_perm;gopLUT5 +param_manager_inst/param_modify_H/N120/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -66865,42 +66644,27 @@ L3;1 L4;1 Inst -param_manager_inst/param_modify_H/pluse/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_osd_startY/N139/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -param_manager_inst/param_modify_H/cnt[11]/opit_0_AQ_perm;gopAQ +param_manager_inst/param_offsetX/N122/gateop_perm;gopLUT5 Pin -CEOUT;2 -Cout;2 -Q;2 -RSOUT;2 -Y;2 -CE;1 -CLK;1 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 -RS;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst -param_manager_inst/ms_cnt[0]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_modify_H/pluse/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -66916,7 +66680,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_modify_H/N122/gateop_perm;gopLUT5 +param_manager_inst/param_offsetX/N63_mux11_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -66926,23 +66690,17 @@ L3;1 L4;1 Inst -param_manager_inst/param_filiter1_mode/key_debounce_inst2/change/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_offsetY/N154_2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -param_manager_inst/param_modify_H/N150_1/gateop_perm;gopLUT5 +udp_wr_mem_inst/N424/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -66952,7 +66710,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_modify_V/N151_19/gateop_perm;gopLUT5 +param_manager_inst/param_rotate/N153_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -67042,7 +66800,7 @@ I13;1 I14;1 Inst -udp_wr_mem_inst/flags[19]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/selected[13]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -67058,17 +66816,33 @@ L4;1 RS;1 Inst -param_manager_inst/param_modify_H/N156_1/gateop_perm;gopLUT5 +param_manager_inst/param_modify_H/value[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_modify_V/value[4]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_osd_startX/N148_5/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +param_manager_inst/param_filiter1_mode/key_debounce_inst1/change/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -67084,7 +66858,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_modify_H/cnt[3]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_modify_H/cnt[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -67126,7 +66900,7 @@ I14;1 RS;1 Inst -param_manager_inst/param_modify_H/cnt[2]/opit_0_L5Q;gopL5Q +param_manager_inst/param_modify_H/cnt[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -67158,17 +66932,23 @@ L4;1 RS;1 Inst -param_manager_inst/param_filiter1_mode/key_debounce_inst1/N20_mux2/gateop_perm;gopLUT5 +param_manager_inst/param_filiter1_mode/cnt[4]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_rotate/cnt[2]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_offsetX/cnt[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -67264,7 +67044,7 @@ I14;1 RS;1 Inst -param_manager_inst/param_filiter1_mode/key_debounce_inst1/N88/gateop_perm;gopLUT5 +param_manager_inst/param_modify_H/N102_10/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -67274,7 +67054,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_modify_S/N150_1/gateop_perm;gopLUT5 +param_manager_inst/param_modify_V/N63_mux8_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -67284,23 +67064,17 @@ L3;1 L4;1 Inst -param_manager_inst/param_modify_H/value[2]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_modify_S/N151_32/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -ms72xx_ctl/ms7200_ctl/state_reg[0]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_modify_H/value[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -67348,7 +67122,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_modify_H/value[5]/opit_0_L5Q_perm;gopL5Q +udp_wr_mem_inst/flags[20]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -67412,7 +67186,27 @@ L4;1 RS;1 Inst -param_manager_inst/param_modify_S/value[2]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_modify_S/N76_mux8_8/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +param_manager_inst/param_modify_S/N151_19/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +param_manager_inst/param_modify_S/value[8]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -67428,7 +67222,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_modify_S/N76_mux8_9/gateop_perm;gopLUT5 +param_manager_inst/param_modify_S/N140/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -67438,7 +67232,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_modify_S/N76_mux8_8/gateop_perm;gopLUT5 +param_manager_inst/param_modify_S/N142/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -67448,39 +67242,27 @@ L3;1 L4;1 Inst -param_manager_inst/param_modify_S/value[6]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_rotate_A/N148_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/s_m_data[2]/opit_0_L5Q_perm;gopL5Q +udp_wr_mem_inst/N484/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -param_manager_inst/param_modify_S/N149/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/N46_mux9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -67490,7 +67272,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_modify_V/N149/gateop_perm;gopLUT5 +param_manager_inst/param_offsetY/N150_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -67500,7 +67282,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_modify_S/N151_19/gateop_perm;gopLUT5 +param_manager_inst/param_modify_S/N150_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -67510,14 +67292,20 @@ L3;1 L4;1 Inst -param_manager_inst/param_filiter1_mode/N116/gateop_perm;gopLUT5 +udp_wr_mem_inst/flags[21]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst param_manager_inst/param_modify_S/N151_10_1/gateop_A2;gopA2 @@ -67600,7 +67388,7 @@ I13;1 I14;1 Inst -udp_wr_mem_inst/flags[21]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_modify_S/value[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -67616,7 +67404,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/N133_7/gateop_perm;gopLUT5 +param_manager_inst/param_modify_H/N149/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -67626,17 +67414,39 @@ L3;1 L4;1 Inst -param_manager_inst/param_offsetX/N63_mux11_4/gateop_perm;gopLUT5 +param_manager_inst/zoom_load/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_modify_S/value[1]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_modify_S/value[5]/opit_0_L5Q_perm;gopL5Q +Pin +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 + +Inst +param_manager_inst/param_modify_S/value[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -67684,7 +67494,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_modify_S/value[8]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_modify_S/value[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -67700,7 +67510,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_modify_S/value[5]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_modify_S/value[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -67732,17 +67542,23 @@ L4;1 RS;1 Inst -param_manager_inst/param_modify_H/N120/gateop_perm;gopLUT5 +param_manager_inst/rotate_A_load/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_modify_H/N102_9/gateop_perm;gopLUT5 +param_manager_inst/param_rotate_A/N142/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -67752,23 +67568,17 @@ L3;1 L4;1 Inst -param_manager_inst/param_modify_H/cnt[0]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_modify_V/N76_mux8_8/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N10_cpy/gateop_perm;gopLUT5 +param_manager_inst/param_osd_startX/N102_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -67778,7 +67588,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_modify_V/value[2]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_modify_V/value[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -67794,17 +67604,23 @@ L4;1 RS;1 Inst -param_manager_inst/param_modify_V/N76_mux8_9/gateop_perm;gopLUT5 +param_manager_inst/param_osd_char_height/cnt[2]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_modify_S/N63_mux8_6/gateop_perm;gopLUT5 +param_manager_inst/param_offsetX/N72/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -67814,7 +67630,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_offsetY/N76_mux8_3/gateop_perm;gopLUT5 +param_manager_inst/param_modify_V/N150_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -67824,23 +67640,17 @@ L3;1 L4;1 Inst -param_manager_inst/selected[0]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_modify_V/N149/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -param_manager_inst/param_filiter2_mode/N152_6/gateop_perm;gopLUT5 +param_manager_inst/param_modify_V/N154/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -67850,20 +67660,14 @@ L3;1 L4;1 Inst -param_manager_inst/selected[11]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_modify_H/N150_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst param_manager_inst/param_modify_V/N151_10_1/gateop_A2;gopA2 @@ -67946,7 +67750,7 @@ I13;1 I14;1 Inst -param_manager_inst/param_modify_V/N154/gateop_perm;gopLUT5 +udp_wr_mem_inst/N504/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -67956,23 +67760,17 @@ L3;1 L4;1 Inst -udp_wr_mem_inst/flags[23]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_filiter1_mode/N119/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -param_manager_inst/param_filiter1_mode/N102_8/gateop_perm;gopLUT5 +param_manager_inst/param_osd_startY/N148_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -67982,23 +67780,17 @@ L3;1 L4;1 Inst -param_manager_inst/param_modify_V/value[1]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_filiter2_mode/N157_2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -param_manager_inst/param_modify_V/value[5]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_modify_V/value[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -68030,7 +67822,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_modify_V/value[6]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_modify_V/value[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -68046,17 +67838,23 @@ L4;1 RS;1 Inst -param_manager_inst/param_modify_S/N154/gateop_perm;gopLUT5 +param_manager_inst/param_modify_V/value[5]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_modify_V/value[8]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_modify_V/value[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -68088,7 +67886,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_filiter1_mode/key_debounce_inst2/cnt[0]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_modify_V/value[8]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -68104,20 +67902,14 @@ L4;1 RS;1 Inst -param_manager_inst/param_modify_S/value[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/N58_mux9/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst param_manager_inst/param_offsetX/N26_1.fsub_1/gateop_A2;gopA2 @@ -68160,23 +67952,17 @@ I13;1 I14;1 Inst -u_rotate_image/cnt_w[0]/opit_0_inv_L5Q_perm;gopL5Q +param_manager_inst/param_offsetX/N63_mux6_7/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_rotate_image/cnt_h[0]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_offsetX/value[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -68192,27 +67978,39 @@ L4;1 RS;1 Inst -param_manager_inst/param_offsetX/N154_2/gateop_perm;gopLUT5 +param_manager_inst/param_offsetX/value[7]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_modify_V/N156_1/gateop_perm;gopLUT5 +udp_wr_mem_inst/flags[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_modify_V/N148_1/gateop_perm;gopLUT5 +param_manager_inst/param_offsetY/N76_mux8_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -68222,7 +68020,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_offsetX/N102_12/gateop_perm;gopLUT5 +param_manager_inst/param_offsetX/N102_11/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -68232,7 +68030,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_offsetX/N122/gateop_perm;gopLUT5 +param_manager_inst/param_offsetX/N102_12/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -68242,17 +68040,23 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_16_18/gateop_perm;gopLUT5 +param_manager_inst/key_debounce_key_restore/cnt[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_filiter1_mode/cnt[9]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_offsetX/cnt[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -68268,7 +68072,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N308_7/gateop_perm;gopLUT5 +param_manager_inst/param_osd_char_width/N153/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -68278,7 +68082,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[0]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_offsetY/value[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -68294,17 +68098,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_offsetX/N150_1/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -param_manager_inst/param_osd_char_height/N76_mux8_1/gateop_perm;gopLUT5 +param_manager_inst/param_offsetX/N151_19/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -68414,40 +68208,39 @@ I13;1 I14;1 Inst -param_manager_inst/param_offsetX/N151_19/gateop_perm;gopLUT5 +param_manager_inst/param_offsetX/value[8]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_osd_char_height/N149_28/gateop_perm;gopLUT5 +udp_wr_mem_inst/flags[15]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/N35.lt_2/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -param_manager_inst/param_osd_char_height/N148_4/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N257_13_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -68457,7 +68250,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_offsetX/cnt[1]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_filiter1_mode/cnt[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -68473,23 +68266,17 @@ L4;1 RS;1 Inst -param_manager_inst/param_offsetX/cnt[3]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_filiter1_mode/N102_11/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -param_manager_inst/param_osd_char_height/cnt[0]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_offsetX/cnt[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -68505,20 +68292,14 @@ L4;1 RS;1 Inst -param_manager_inst/param_osd_char_height/cnt[2]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_modify_H/N102_9/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst param_manager_inst/param_offsetX/cnt[11]/opit_0_AQ_perm;gopAQ @@ -68621,7 +68402,7 @@ I14;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_15/gateop_perm;gopLUT5 +param_manager_inst/param_osd_startY/N63_mux10_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -68631,36 +68412,24 @@ L3;1 L4;1 Inst -param_manager_inst/param_osd_char_height/pluse/opit_0_L5Q_perm;gopL5Q +udp_wr_mem_inst/N84/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -param_manager_inst/param_offsetX/value[1]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_offsetX/N150_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst param_manager_inst/param_offsetX/value[2]/opit_0_L5Q_perm;gopL5Q @@ -68695,20 +68464,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_offsetX/N151_10_11/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -param_manager_inst/param_offsetX/value[5]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_offsetX/value[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -68724,23 +68480,17 @@ L4;1 RS;1 Inst -param_manager_inst/param_offsetX/value[6]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_offsetX/N63_mux6_5/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -param_manager_inst/param_offsetX/value[7]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_offsetX/value[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -68756,7 +68506,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_osd_char_height/value[1]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_offsetX/value[10]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -68788,49 +68538,43 @@ L4;1 RS;1 Inst -param_manager_inst/param_offsetX/value[10]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_modify_H/N139_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -param_manager_inst/param_offsetX/value[11]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N163_mux2_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -param_manager_inst/param_offsetX/N149/gateop_perm;gopLUT5 +param_manager_inst/param_offsetX/value[11]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_offsetY/N76_mux6_4/gateop_perm;gopLUT5 +u_rotate_image/N131_mux1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -68840,7 +68584,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_offsetY/N63_mux9_5/gateop_perm;gopLUT5 +param_manager_inst/param_offsetY/N63_mux5_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -68850,23 +68594,17 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_y[4]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_offsetY/N63_mux9_5/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -param_manager_inst/param_offsetY/N151_10_11/gateop_perm;gopA +param_manager_inst/param_rotate/N155_8_7/gateop_perm;gopA Pin Cout;2 Y;2 @@ -68879,7 +68617,7 @@ I3;1 I4;1 Inst -param_manager_inst/param_osd_startY/N63_mux10_7/gateop_perm;gopLUT5 +u_rotate_image/N131_mux9_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -68889,7 +68627,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_offsetY/N149/gateop_perm;gopLUT5 +param_manager_inst/param_offsetY/N76_mux6_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -68899,20 +68637,14 @@ L3;1 L4;1 Inst -udp_wr_mem_inst/flags[17]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_osd_char_height/N148_4/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst param_manager_inst/param_offsetY/N151_19/gateop_perm;gopLUT5 @@ -68924,6 +68656,22 @@ L2;1 L3;1 L4;1 +Inst +param_manager_inst/selected[9]/opit_0_L5Q_perm;gopL5Q +Pin +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 + Inst param_manager_inst/param_offsetY/N151_10_1/gateop_A2;gopA2 Pin @@ -69025,7 +68773,20 @@ I13;1 I14;1 Inst -param_manager_inst/param_osd_startY/value[4]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_offsetY/N151_10_11/gateop;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + +Inst +udp_wr_mem_inst/flags[18]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -69041,17 +68802,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_offsetY/N154_2/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -param_manager_inst/param_offsetX/value[4]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_rotate/value[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -69067,7 +68818,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_offsetY/value[1]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_offsetY/value[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -69083,7 +68834,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_offsetY/value[3]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_offsetY/value[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -69099,7 +68850,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_offsetY/value[8]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_offsetY/value[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -69115,23 +68866,17 @@ L4;1 RS;1 Inst -param_manager_inst/param_offsetY/value[4]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_offsetY/N63_mux3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -param_manager_inst/param_offsetY/value[5]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_offsetY/value[10]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -69147,7 +68892,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_offsetY/value[6]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_offsetY/value[8]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -69179,7 +68924,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_offsetY/value[11]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_offsetY/value[9]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -69195,7 +68940,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_offsetY/value[9]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_offsetY/value[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -69211,7 +68956,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_offsetY/value[10]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_offsetY/value[11]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -69227,17 +68972,23 @@ L4;1 RS;1 Inst -param_manager_inst/param_offsetY/N148_1/gateop_perm;gopLUT5 +param_manager_inst/param_offsetY/value[6]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_offsetY/value[2]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_rotate/value[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -69313,17 +69064,7 @@ I13;1 I14;1 Inst -param_manager_inst/param_osd_char_height/N76_mux4_3/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -param_manager_inst/osd_char_width_load/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_osd_char_height/value[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -69339,23 +69080,17 @@ L4;1 RS;1 Inst -param_manager_inst/param_offsetX/value[8]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_osd_char_height/N76_mux4_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -param_manager_inst/param_osd_char_height/N138/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/pixels_shifter_inst/N18_mux7_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -69365,7 +69100,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_osd_char_height/value[6]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_rotate/cnt[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -69381,7 +69116,17 @@ L4;1 RS;1 Inst -udp_wr_mem_inst/flags[15]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_osd_char_height/N154_2/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_y[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -69397,7 +69142,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_osd_char_height/N122/gateop_perm;gopLUT5 +param_manager_inst/param_osd_char_height/N102_11/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -69407,7 +69152,7 @@ L3;1 L4;1 Inst -image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/N39_0_ac4/gateop_perm;gopLUT5 +param_manager_inst/param_osd_char_height/N102_12/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -69417,23 +69162,17 @@ L3;1 L4;1 Inst -param_manager_inst/param_osd_char_height/cnt[4]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_osd_char_height/N122/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -param_manager_inst/param_osd_char_height/N102_12/gateop_perm;gopLUT5 +param_manager_inst/param_modify_V/N156_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -69443,7 +69182,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_osd_char_width/N156_1/gateop_perm;gopLUT5 +param_manager_inst/param_osd_char_height/N149_28/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -69453,7 +69192,7 @@ L3;1 L4;1 Inst -param_manager_inst/selected[5]/opit_0_L5Q_perm;gopL5Q +udp_wr_mem_inst/flags[11]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -69468,16 +69207,6 @@ L3;1 L4;1 RS;1 -Inst -param_manager_inst/param_osd_char_height/N72/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - Inst param_manager_inst/param_osd_char_height/N149_8_1/gateop_A2;gopA2 Pin @@ -69579,17 +69308,7 @@ I13;1 I14;1 Inst -param_manager_inst/param_osd_char_height/N154_2/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -udp_wr_mem_inst/N264/gateop_perm;gopLUT5 +param_manager_inst/param_osd_char_height/N153/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -69599,17 +69318,23 @@ L3;1 L4;1 Inst -param_manager_inst/param_rotate_A/N156_1/gateop_perm;gopLUT5 +param_manager_inst/param_osd_char_height/value[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_osd_char_width/N148_4/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/pixels_shifter_inst/N9_mux7_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -69635,7 +69360,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_osd_char_height/cnt[3]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_osd_char_height/cnt[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -69651,39 +69376,54 @@ L4;1 RS;1 Inst -param_manager_inst/param_offsetX/N102_9/gateop_perm;gopLUT5 +param_manager_inst/param_osd_char_height/cnt[3]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_osd_char_height/N102_9/gateop_perm;gopLUT5 +param_manager_inst/param_osd_startX/cnt[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_osd_char_height/cnt[5]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_osd_char_height/cnt[11]/opit_0_AQ_perm;gopAQ Pin CEOUT;2 +Cout;2 Q;2 RSOUT;2 -Z;2 +Y;2 CE;1 CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 RS;1 Inst @@ -69703,14 +69443,20 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_15/gateop_perm;gopLUT5 +param_manager_inst/param_osd_startX/cnt[2]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst param_manager_inst/param_osd_char_height/cnt[8]/opit_0_A2Q21;gopA2Q2 @@ -69767,7 +69513,7 @@ I14;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_16_22/gateop_perm;gopLUT5 +param_manager_inst/param_osd_char_height/N102_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -69777,7 +69523,7 @@ L3;1 L4;1 Inst -param_manager_inst/selected[1]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/selected[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -69793,20 +69539,14 @@ L4;1 RS;1 Inst -param_manager_inst/param_osd_char_height/value[4]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_osd_char_height/N63_mux10_4/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst param_manager_inst/param_osd_char_height/value[2]/opit_0_L5Q_perm;gopL5Q @@ -69841,17 +69581,23 @@ L4;1 RS;1 Inst -udp_wr_mem_inst/N344/gateop_perm;gopLUT5 +param_manager_inst/param_osd_char_height/value[4]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_osd_char_height/value[5]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_y[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -69867,7 +69613,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_osd_char_height/value[8]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_osd_char_height/value[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -69883,7 +69629,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_osd_char_height/value[7]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_osd_char_height/value[8]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -69915,20 +69661,14 @@ L4;1 RS;1 Inst -param_manager_inst/osd_char_height_load/opit_0_L5Q_perm;gopL5Q +u_sync_vg/N138_mux4/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst param_manager_inst/param_osd_char_height/value[10]/opit_0_L5Q_perm;gopL5Q @@ -69947,33 +69687,33 @@ L4;1 RS;1 Inst -param_manager_inst/param_osd_char_height/N153/gateop_perm;gopLUT5 +u_sync_vg/pos_x[3]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_x[0]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_osd_char_width/N76_mux4_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -param_manager_inst/param_osd_char_width/N76_mux4_3/gateop_perm;gopLUT5 +param_manager_inst/param_osd_char_width/N63_mux10_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -69983,7 +69723,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_osd_char_width/N149_28/gateop_perm;gopLUT5 +param_manager_inst/param_osd_startX/N63_mux10_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -69993,14 +69733,20 @@ L3;1 L4;1 Inst -param_manager_inst/param_osd_char_width/N76_mux9_2/gateop_perm;gopLUT5 +param_manager_inst/param_osd_char_width/value[5]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst param_manager_inst/param_osd_char_width/N76_mux9_4/gateop_perm;gopLUT5 @@ -70013,7 +69759,7 @@ L3;1 L4;1 Inst -udp_wr_mem_inst/flags[10]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_osd_char_width/value[9]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -70029,7 +69775,17 @@ L4;1 RS;1 Inst -param_manager_inst/param_rotate_A/N139_1/gateop_perm;gopLUT5 +param_manager_inst/param_osd_char_width/N149_28/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +param_manager_inst/param_offsetX/N148_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -70139,17 +69895,23 @@ I13;1 I14;1 Inst -param_manager_inst/param_osd_char_width/N153/gateop_perm;gopLUT5 +param_manager_inst/param_osd_char_width/value[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_wr_mem_inst/N64/gateop_perm;gopLUT5 +param_manager_inst/param_osd_char_width/N156_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -70159,23 +69921,17 @@ L3;1 L4;1 Inst -param_manager_inst/param_osd_char_width/value[7]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_osd_char_width/N139/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -param_manager_inst/param_filiter1_mode/N152_5_3/gateop_perm;gopLUT5 +param_manager_inst/param_rotate_A/N139_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -70185,7 +69941,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_osd_char_width/value[5]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_osd_char_width/value[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -70233,7 +69989,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_osd_char_width/value[4]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_osd_char_width/value[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -70249,20 +70005,17 @@ L4;1 RS;1 Inst -param_manager_inst/param_osd_char_width/value[9]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N483_11/gateop_perm;gopA Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst param_manager_inst/param_osd_char_width/value[6]/opit_0_L5Q_perm;gopL5Q @@ -70297,7 +70050,7 @@ L4;1 RS;1 Inst -udp_wr_mem_inst/N144/gateop_perm;gopLUT5 +param_manager_inst/param_osd_char_width/N63_mux10_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -70307,33 +70060,33 @@ L3;1 L4;1 Inst -param_manager_inst/param_osd_char_width/N63_mux10_8/gateop_perm;gopLUT5 +param_manager_inst/param_osd_char_width/value[10]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_osd_char_width/value[10]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N416_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -param_manager_inst/param_offsetX/cnt[0]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_x[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -70389,17 +70142,23 @@ I13;1 I14;1 Inst -param_manager_inst/param_rotate/N152_1/gateop_perm;gopLUT5 +param_manager_inst/param_osd_startX/value[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_osd_startX/N76_mux8_4/gateop_perm;gopLUT5 +param_manager_inst/param_osd_startX/N76_mux4_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -70409,39 +70168,27 @@ L3;1 L4;1 Inst -param_manager_inst/param_osd_startX/value[3]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_osd_startX/N76_mux8_4/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -param_manager_inst/param_osd_startX/pluse/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N591_14_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -param_manager_inst/param_osd_startX/cnt[3]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_osd_char_height/cnt[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -70457,7 +70204,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N70_ac2/gateop_perm;gopLUT5 +param_manager_inst/param_osd_startX/N122/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -70467,7 +70214,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_osd_startX/N102_11/gateop;gopLUT5 +param_manager_inst/param_rotate/N102_12/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -70477,17 +70224,23 @@ L3;1 L4;1 Inst -param_manager_inst/param_osd_startX/N102_10/gateop_perm;gopLUT5 +udp_wr_mem_inst/flags[12]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_osd_startX/N153_1/gateop_perm;gopLUT5 +param_manager_inst/param_osd_startX/N149_38/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -70497,20 +70250,14 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt[0]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_osd_startX/N156_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst param_manager_inst/param_osd_startX/N149_10_1/gateop_A2;gopA2 @@ -70613,7 +70360,7 @@ I13;1 I14;1 Inst -param_manager_inst/param_osd_startX/N149_49/gateop_perm;gopLUT5 +param_manager_inst/param_osd_startX/N149_43_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -70623,7 +70370,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_osd_startX/N154/gateop_perm;gopLUT5 +param_manager_inst/param_osd_startX/N149_49/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -70633,7 +70380,7 @@ L3;1 L4;1 Inst -udp_wr_mem_inst/flags[5]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_osd_startX/value[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -70649,7 +70396,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_osd_startX/N156_3/gateop_perm;gopLUT5 +param_manager_inst/param_osd_startX/N154/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -70659,7 +70406,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N308_32/gateop_perm;gopLUT5 +param_manager_inst/param_osd_char_width/N76_mux9_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -70669,7 +70416,17 @@ L3;1 L4;1 Inst -udp_wr_mem_inst/flags[6]/opit_0_L5Q_perm;gopL5Q +udp_wr_mem_inst/N144/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +param_manager_inst/param_osd_startX/cnt[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -70685,7 +70442,17 @@ L4;1 RS;1 Inst -param_manager_inst/param_osd_startX/cnt[1]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_modify_H/N122/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +param_manager_inst/param_osd_startX/cnt[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -70717,33 +70484,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_osd_startX/cnt[2]/opit_0_L5Q;gopL5Q -Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 - -Inst -param_manager_inst/param_osd_startX/N122/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -param_manager_inst/param_zoom/value[6]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_osd_startX/cnt[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -70858,17 +70599,23 @@ I14;1 RS;1 Inst -param_manager_inst/N30/gateop_perm;gopLUT5 +param_manager_inst/param_rotate/cnt[2]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/selected[3]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/selected[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -70884,7 +70631,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_osd_startX/value[1]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_osd_startX/value[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -70900,7 +70647,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_osd_startX/value[6]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_osd_startX/value[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -70916,17 +70663,20 @@ L4;1 RS;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N483_11/gateop_perm;gopA +param_manager_inst/param_osd_startX/value[9]/opit_0_L5Q_perm;gopL5Q Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 Inst param_manager_inst/param_osd_startX/value[4]/opit_0_L5Q_perm;gopL5Q @@ -70945,7 +70695,7 @@ L4;1 RS;1 Inst -udp_wr_mem_inst/N244/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N374/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -70955,7 +70705,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_osd_startX/value[7]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_osd_startX/value[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -70971,7 +70721,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_osd_startX/value[8]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_osd_startX/value[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -70987,7 +70737,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_osd_startX/value[9]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_osd_startX/value[8]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -71003,7 +70753,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_osd_startX/N63_mux10_8/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N432_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -71029,49 +70779,53 @@ L4;1 RS;1 Inst -param_manager_inst/param_osd_char_width/N154/gateop_perm;gopLUT5 +param_manager_inst/param_osd_startX/value[5]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_osd_startY/value[7]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/key_debounce_key_restore/N20_mux2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -param_manager_inst/selected[10]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_osd_char_height/N76_mux8_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_y[8]/opit_0_L5Q_perm;gopL5Q +u_sync_vg/N50_mux2_7/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +param_manager_inst/param_osd_startY/value[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -71087,7 +70841,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_osd_startY/N76_mux7_4/gateop_perm;gopLUT5 +param_manager_inst/param_osd_startY/N149_38/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -71097,27 +70851,20 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N522_11/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -param_manager_inst/param_osd_startY/N156_6/gateop_perm;gopLUT5 +udp_wr_mem_inst/flags[7]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst param_manager_inst/param_osd_startY/N149_10_1/gateop_A2;gopA2 @@ -71220,7 +70967,7 @@ I13;1 I14;1 Inst -udp_osd_inst/char_osd_inst/pixels_shifter_inst/N18_mux7_6/gateop_perm;gopLUT5 +param_manager_inst/param_osd_startY/N154/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -71230,7 +70977,7 @@ L3;1 L4;1 Inst -udp_osd_inst/N69_8/gateop_perm;gopLUT5 +param_manager_inst/param_osd_startY/N149_49/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -71240,17 +70987,23 @@ L3;1 L4;1 Inst -param_manager_inst/param_osd_startY/N154/gateop_perm;gopLUT5 +param_manager_inst/param_osd_startY/value[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_x[1]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/key_debounce_key_restore/pressed/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -71266,7 +71019,7 @@ L4;1 RS;1 Inst -udp_wr_mem_inst/N364/gateop_perm;gopLUT5 +param_manager_inst/param_osd_startY/N149_43_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -71276,7 +71029,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_osd_startY/value[3]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_osd_startY/value[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -71308,17 +71061,23 @@ L4;1 RS;1 Inst -udp_osd_inst/char_osd_inst/pixels_shifter_inst/N23_mux7_3/gateop_perm;gopLUT5 +param_manager_inst/param_osd_startY/value[4]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_osd_startY/value[5]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_osd_startY/value[9]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -71334,17 +71093,23 @@ L4;1 RS;1 Inst -param_manager_inst/param_modify_V/N139_1/gateop_perm;gopLUT5 +param_manager_inst/param_osd_startY/value[6]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_osd_startY/value[6]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_osd_startY/value[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -71360,7 +71125,7 @@ L4;1 RS;1 Inst -udp_wr_mem_inst/N184/gateop_perm;gopLUT5 +param_manager_inst/param_osd_startY/N76_mux7_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -71386,7 +71151,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_osd_startY/value[9]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_y[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -71418,20 +71183,14 @@ L4;1 RS;1 Inst -param_manager_inst/osd_startY_load/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_osd_startY/N63_mux10_7/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst param_manager_inst/param_rotate/N26_1.fsub_1/gateop_A2;gopA2 @@ -71474,7 +71233,7 @@ I13;1 I14;1 Inst -udp_osd_inst/eth_udp_inst/N72_24/gateop_perm;gopLUT5 +param_manager_inst/param_rotate/N63_mux7_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -71484,7 +71243,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_rotate/N63_mux7_8/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N422_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -71494,7 +71253,7 @@ L3;1 L4;1 Inst -udp_wr_mem_inst/N124/gateop_perm;gopLUT5 +udp_wr_mem_inst/N64/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -71504,27 +71263,39 @@ L3;1 L4;1 Inst -u_zoom_image/N715_7/gateop_perm;gopLUT5 +param_manager_inst/param_rotate/cnt[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_rotate/N122/gateop_perm;gopLUT5 +param_manager_inst/param_rotate/cnt[5]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_zoom_image/N857_8[1]/gateop_perm;gopLUT5 +param_manager_inst/param_osd_char_height/N72/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -71534,7 +71305,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_rotate/N102_9/gateop_perm;gopLUT5 +param_manager_inst/param_rotate/N122/gateop;gopLUT5 Pin Z;2 L0;1 @@ -71544,7 +71315,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_rotate/value[7:0]_e_1/gateop_perm;gopLUT5 +param_manager_inst/param_rotate/N152_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -71554,17 +71325,23 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/pixels_shifter_inst/N18_mux10/gateop_perm;gopLUT5 +param_manager_inst/selected[1]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_rotate/N152_5_10/gateop_perm;gopLUT5 +param_manager_inst/param_rotate/N152_5_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -71574,7 +71351,17 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/pixels_shifter_inst/N9_mux7_6/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N402_58/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +udp_wr_mem_inst/N524_10/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -71644,14 +71431,20 @@ I13;1 I14;1 Inst -param_manager_inst/param_osd_startX/N63_mux10_7/gateop_perm;gopLUT5 +param_manager_inst/param_rotate/value[5]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst param_manager_inst/param_rotate/value[7:0]_e/gateop_perm;gopLUT5 @@ -71680,7 +71473,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_rotate/cnt[4]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_rotate/cnt[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -71696,7 +71489,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_rotate/cnt[6]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_filiter1_mode/pluse/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -71738,52 +71531,43 @@ I14;1 RS;1 Inst -param_manager_inst/param_rotate/cnt[5]/opit_0_L5Q_perm;gopL5Q +udp_wr_mem_inst/N184/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_zoom_image/cnt_w[0]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_rotate/cnt[11]/opit_0_AQ_perm;gopAQ Pin CEOUT;2 +Cout;2 Q;2 RSOUT;2 -Z;2 +Y;2 CE;1 CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 RS;1 Inst -param_manager_inst/param_filiter1_mode/key_debounce_inst1/cnt[0]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_filiter1_mode/key_debounce_inst2/N20_mux4_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst param_manager_inst/param_rotate/cnt[8]/opit_0_A2Q21;gopA2Q2 @@ -71840,17 +71624,23 @@ I14;1 RS;1 Inst -param_manager_inst/N9_mux9_4/gateop_perm;gopLUT5 +param_manager_inst/osd_char_height_load/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_zoom/N149_49/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_16_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -71876,20 +71666,14 @@ L4;1 RS;1 Inst -param_manager_inst/param_rotate/value[2]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_rotate/value[7:0]_5/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst param_manager_inst/param_rotate/value[3]/opit_0_L5Q_perm;gopL5Q @@ -71908,7 +71692,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_rotate/value[5]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_rotate/value[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -71924,21 +71708,40 @@ L4;1 RS;1 Inst -param_manager_inst/param_rotate/value[4]/opit_0_MUX4TO1Q;gopMUX4TO1Q +param_manager_inst/param_rotate/value[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 -F;2 Q;2 RSOUT;2 +Z;2 CE;1 CLK;1 -I0;1 -I1;1 -I2;1 -I3;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 RS;1 -S0;1 -S1;1 + +Inst +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N310_7_3/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +param_manager_inst/param_rotate/N152_5_8/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst param_manager_inst/param_rotate/value[7]/opit_0_L5Q_perm;gopL5Q @@ -71957,24 +71760,17 @@ L4;1 RS;1 Inst -param_manager_inst/param_rotate/value[6]/opit_0_MUX4TO1Q;gopMUX4TO1Q +param_manager_inst/param_rotate/value[7:0]_e_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -F;2 -Q;2 -RSOUT;2 -CE;1 -CLK;1 -I0;1 -I1;1 -I2;1 -I3;1 -RS;1 -S0;1 -S1;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[5]/opit_0_L5Q_perm;gopL5Q +udp_wr_mem_inst/flags[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -71990,7 +71786,7 @@ L4;1 RS;1 Inst -udp_wr_mem_inst/N164/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_35/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -72000,17 +71796,23 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/N72_16/gateop_perm;gopLUT5 +param_manager_inst/param_rotate_A/value[4]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_rotate_A/N63_mux9_9/gateop_perm;gopLUT5 +param_manager_inst/param_rotate_A/N154/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -72020,7 +71822,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/ms7210_ctl/N14_6/gateop_perm;gopLUT5 +param_manager_inst/param_osd_char_height/N63_mux10_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -72030,36 +71832,24 @@ L3;1 L4;1 Inst -param_manager_inst/param_offsetX/cnt[2]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_rotate_A/N149_38/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_done_cdc/out_ack/opit_0_L5Q_perm;gopL5Q +udp_wr_mem_inst/N164/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst param_manager_inst/param_zoom/N156_1/gateop_perm;gopLUT5 @@ -72165,7 +71955,7 @@ I3;1 I4;1 Inst -param_manager_inst/param_rotate_A/N149_49/gateop_perm;gopLUT5 +param_manager_inst/param_rotate_A/N149_43_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -72185,7 +71975,7 @@ L3;1 L4;1 Inst -udp_wr_mem_inst/N324/gateop_perm;gopLUT5 +param_manager_inst/param_rotate_A/N156_23/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -72195,7 +71985,7 @@ L3;1 L4;1 Inst -udp_wr_mem_inst/N304/gateop_perm;gopLUT5 +param_manager_inst/param_rotate_A/N156_20/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -72205,17 +71995,23 @@ L3;1 L4;1 Inst -param_manager_inst/param_filiter1_mode/N152_1/gateop_perm;gopLUT5 +udp_wr_mem_inst/flags[3]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_rotate_A/N156_21/gateop_perm;gopLUT5 +param_manager_inst/param_rotate_A/N156_26/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -72225,17 +72021,23 @@ L3;1 L4;1 Inst -ms72xx_ctl/iic_dri_tx/state_fsm[2:0]_53/gateop_perm;gopLUT5 +param_manager_inst/selected[8]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_rotate_A/N156_25/gateop_perm;gopLUT5 +udp_wr_mem_inst/N304/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -72245,7 +72047,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_done_cdc/in_req/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_rotate_A/value[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -72261,7 +72063,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_rotate_A/value[1]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_rotate_A/value[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -72309,7 +72111,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_rotate_A/value[4]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_rotate_A/value[9]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -72325,7 +72127,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_rotate_A/value[6]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_rotate_A/value[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -72341,7 +72143,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_rotate_A/value[8]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_rotate_A/value[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -72357,17 +72159,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_rotate_A/N149_38/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -param_manager_inst/param_rotate_A/N149_43_1/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N119_33/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -72377,7 +72169,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_rotate_A/value[9]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_rotate_A/value[8]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -72393,7 +72185,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7200_ctl/N1918/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_16_14/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -72403,7 +72195,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_zoom/N156_19/gateop_perm;gopLUT5 +param_manager_inst/param_rotate_A/N63_mux9_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -72413,7 +72205,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_zoom/N148_1/gateop_perm;gopLUT5 +param_manager_inst/param_zoom/N156_20/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -72423,7 +72215,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_zoom/N148_5/gateop_perm;gopLUT5 +param_manager_inst/param_zoom/N149_38/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -72433,17 +72225,23 @@ L3;1 L4;1 Inst -param_manager_inst/param_zoom/N149_43_1/gateop_perm;gopLUT5 +udp_wr_mem_inst/flags[2]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_wr_mem_inst/N484/gateop_perm;gopLUT5 +param_manager_inst/param_zoom/N148_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -72452,6 +72250,19 @@ L2;1 L3;1 L4;1 +Inst +param_manager_inst/param_zoom/N149_10_9/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + Inst param_manager_inst/param_zoom/N149_10_1/gateop_A2;gopA2 Pin @@ -72533,17 +72344,23 @@ I13;1 I14;1 Inst -param_manager_inst/param_zoom/N154/gateop_perm;gopLUT5 +param_manager_inst/param_zoom/value[5]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_zoom/N149_38/gateop;gopLUT5 +param_manager_inst/param_zoom/N156_22/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -72553,7 +72370,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_zoom/N156_25/gateop_perm;gopLUT5 +param_manager_inst/param_zoom/N149_49/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -72563,7 +72380,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_zoom/N156_22/gateop_perm;gopLUT5 +param_manager_inst/param_zoom/N154/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -72573,7 +72390,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_zoom/N156_21/gateop_perm;gopLUT5 +param_manager_inst/param_zoom/N156_23/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -72583,7 +72400,17 @@ L3;1 L4;1 Inst -udp_wr_mem_inst/flags[14]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_rotate_A/N149_49/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +param_manager_inst/param_zoom/value[8]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -72599,7 +72426,7 @@ L4;1 RS;1 Inst -u_zoom_image/N227_1_sum1_2/gateop_perm;gopLUT5 +param_manager_inst/param_zoom/N156_26/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -72609,7 +72436,7 @@ L3;1 L4;1 Inst -param_manager_inst/key_debounce_key_left/N87/gateop_perm;gopLUT5 +param_manager_inst/param_zoom/N142/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -72635,17 +72462,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/N106_91/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -param_manager_inst/param_zoom/value[1]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_zoom/value[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -72661,7 +72478,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_zoom/value[2]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_zoom/value[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -72677,7 +72494,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_zoom/value[5]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_zoom/value[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -72709,30 +72526,30 @@ L4;1 RS;1 Inst -udp_wr_mem_inst/N727/gateop_perm;gopLUT5 +param_manager_inst/param_zoom/value[1]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_rotate/pluse/opit_0_L5Q_perm;gopL5Q +param_manager_inst/N30/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst param_manager_inst/param_zoom/value[7]/opit_0_L5Q_perm;gopL5Q @@ -72751,7 +72568,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_zoom/value[8]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_zoom/value[9]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -72767,36 +72584,24 @@ L4;1 RS;1 Inst -param_manager_inst/param_zoom/value[9]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/N33_mux3_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -param_manager_inst/key_debounce_key_left/pressed/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_zoom/N149_43_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst param_manager_inst/rotate_A_flags_ff0/opit_0;gopQ @@ -72843,7 +72648,7 @@ D;1 RS;1 Inst -udp_wr_mem_inst/N549_21/gateop_perm;gopLUT5 +udp_wr_mem_inst/N444/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -72885,23 +72690,17 @@ L3;1 L4;1 Inst -param_manager_inst/selected[7]/opit_0_L5Q_perm;gopL5Q +udp_wr_mem_inst/N384/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -param_manager_inst/selected[6]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/selected[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -72917,7 +72716,7 @@ L4;1 RS;1 Inst -u_zoom_image/N850_inv/gateop_perm;gopLUT5 +udp_wr_mem_inst/N524_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -72927,7 +72726,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_osd_startX/N149_38/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_16_28/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -72937,27 +72736,39 @@ L3;1 L4;1 Inst -param_manager_inst/param_filiter1_mode/N161_1/gateop_perm;gopLUT5 +param_manager_inst/selected[11]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_wr_mem_inst/N384/gateop_perm;gopLUT5 +param_manager_inst/selected[6]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_offsetX/N102_11/gateop_perm;gopLUT5 +param_manager_inst/param_offsetY/N148_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -72967,33 +72778,33 @@ L3;1 L4;1 Inst -param_manager_inst/selected[9]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N308_15_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_sync_vg/N59_mux6/gateop_perm;gopLUT5 +param_manager_inst/selected[7]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/selected[10]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -73009,7 +72820,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_osd_char_height/N63_mux4/gateop_perm;gopLUT5 +param_manager_inst/param_offsetY/N149/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -73019,7 +72830,7 @@ L3;1 L4;1 Inst -param_manager_inst/selected[13]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/osd_startX_load/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -73035,7 +72846,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_osd_startX/cnt[0]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_modify_H/value[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -73051,14 +72862,20 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/N106_91/gateop_perm;gopLUT5 +param_manager_inst/key_debounce_key_left/pressed/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst param_manager_inst/zoom_flags_ff0/opit_0;gopQ @@ -73105,7 +72922,7 @@ D;1 RS;1 Inst -udp_wr_mem_inst/N104/gateop_perm;gopLUT5 +param_manager_inst/param_modify_S/N149/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -73579,7 +73396,7 @@ I4;1 RS;1 Inst -u_ov5640/u_mix_image/N311_8/gateop_perm;gopLUT5 +N24_mux18_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -73610,7 +73427,7 @@ IN;1 MI;1 Inst -ms72xx_ctl/ms7200_ctl/N1879_7/gateop_perm;gopLUT5 +param_manager_inst/N9_mux4_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -73649,20 +73466,14 @@ IN;1 MI;1 Inst -image_filiter_inst/multiline_buffer_inst/tail_ver_cnt[0]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[4]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv;gopCLKDIV @@ -73693,7 +73504,7 @@ CLK;1 DIN;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N466/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N12_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -73836,7 +73647,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[5]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[7]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -73868,7 +73679,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[7]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -73884,7 +73695,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[8]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[14]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -73900,7 +73711,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[13]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[9]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -73949,7 +73760,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[12]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[12]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -73965,7 +73776,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[9]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[13]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -73981,7 +73792,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[14]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[8]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -74014,14 +73825,20 @@ S0;1 S1;1 Inst -u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N12[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit_pass/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_cas_n/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q @@ -74074,7 +73891,7 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_dqs_resp_r/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_dqs_req/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -74124,23 +73941,14 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[15]/opit_0_inv_AQ_perm;gopAQ +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N277_13/gateop_perm;gopLUT5 Pin -CEOUT;2 -Cout;2 -Q;2 -RSOUT;2 -Y;2 -CE;1 -CLK;1 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 -RS;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N175_8[0]/gateop;gopMUX4TO1 @@ -74308,7 +74116,7 @@ S0;1 S1;1 Inst -u_axi_ddr_top/u_axi_rd_connect/N1_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N282_6_inv/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -74318,7 +74126,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N233_5/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N309_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -74328,7 +74136,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N274/gateop_perm;gopLUT5 +u_axi_ddr_top/N93_mux8_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -74338,7 +74146,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N282_6_inv/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N277_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -74348,7 +74156,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N194_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N466/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -74358,55 +74166,37 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_pwron_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N271_16/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[30]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[6]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[89]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/N6/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_13[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_10[2]_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -74416,7 +74206,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N228_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_12[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -74426,7 +74216,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N277_13/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N277_16/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -74436,17 +74226,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N277_16/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/fifo_vld/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -74462,7 +74258,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_10[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_4[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -74472,7 +74268,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_12[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_7[2]_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -74492,7 +74288,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N277_9/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N0/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -74502,7 +74298,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_4[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_13[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -74512,7 +74308,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -74528,7 +74324,107 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tmrd_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit[9]/opit_0_inv_AQ_perm;gopAQ +Pin +CEOUT;2 +Cout;2 +Q;2 +RSOUT;2 +Y;2 +CE;1 +CLK;1 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 +RS;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[2]/opit_0_inv_A2Q21;gopA2Q2 +Pin +CEOUT;2 +Cout;2 +Q0;2 +Q1;2 +RSOUT;2 +Y0;2 +Y1;2 +CE;1 +CLK;1 +Cin;1 +I0X;1 +I1X;1 +I00;1 +I01;1 +I02;1 +I03;1 +I04;1 +I10;1 +I11;1 +I12;1 +I13;1 +I14;1 +RS;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[4]/opit_0_inv_A2Q21;gopA2Q2 +Pin +CEOUT;2 +Cout;2 +Q0;2 +Q1;2 +RSOUT;2 +Y0;2 +Y1;2 +CE;1 +CLK;1 +Cin;1 +I0X;1 +I1X;1 +I00;1 +I01;1 +I02;1 +I03;1 +I04;1 +I10;1 +I11;1 +I12;1 +I13;1 +I14;1 +RS;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[6]/opit_0_inv_A2Q21;gopA2Q2 +Pin +CEOUT;2 +Cout;2 +Q0;2 +Q1;2 +RSOUT;2 +Y0;2 +Y1;2 +CE;1 +CLK;1 +Cin;1 +I0X;1 +I1X;1 +I00;1 +I01;1 +I02;1 +I03;1 +I04;1 +I10;1 +I11;1 +I12;1 +I13;1 +I14;1 +RS;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tmod_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -74544,7 +74440,39 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[2]/opit_0_inv_A2Q21;gopA2Q2 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[0]/opit_0_inv_L5Q_perm;gopL5Q +Pin +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[7]/opit_0_inv_L5Q_perm;gopL5Q +Pin +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[2]/opit_0_inv_A2Q21;gopA2Q2 Pin CEOUT;2 Cout;2 @@ -74571,7 +74499,7 @@ I14;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[4]/opit_0_inv_A2Q21;gopA2Q2 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[4]/opit_0_inv_A2Q21;gopA2Q2 Pin CEOUT;2 Cout;2 @@ -74598,136 +74526,7 @@ I14;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[6]/opit_0_inv_A2Q21;gopA2Q2 -Pin -CEOUT;2 -Cout;2 -Q0;2 -Q1;2 -RSOUT;2 -Y0;2 -Y1;2 -CE;1 -CLK;1 -Cin;1 -I0X;1 -I1X;1 -I00;1 -I01;1 -I02;1 -I03;1 -I04;1 -I10;1 -I11;1 -I12;1 -I13;1 -I14;1 -RS;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tmod_pass/opit_0_inv_L5Q_perm;gopL5Q -Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[0]/opit_0_inv_L5Q_perm;gopL5Q -Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q -Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[2]/opit_0_inv_A2Q21;gopA2Q2 -Pin -CEOUT;2 -Cout;2 -Q0;2 -Q1;2 -RSOUT;2 -Y0;2 -Y1;2 -CE;1 -CLK;1 -Cin;1 -I0X;1 -I1X;1 -I00;1 -I01;1 -I02;1 -I03;1 -I04;1 -I10;1 -I11;1 -I12;1 -I13;1 -I14;1 -RS;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[4]/opit_0_inv_A2Q21;gopA2Q2 -Pin -CEOUT;2 -Cout;2 -Q0;2 -Q1;2 -RSOUT;2 -Y0;2 -Y1;2 -CE;1 -CLK;1 -Cin;1 -I0X;1 -I1X;1 -I00;1 -I01;1 -I02;1 -I03;1 -I04;1 -I10;1 -I11;1 -I12;1 -I13;1 -I14;1 -RS;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[6]/opit_0_inv_A2Q21;gopA2Q2 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[6]/opit_0_inv_A2Q21;gopA2Q2 Pin CEOUT;2 Cout;2 @@ -74862,7 +74661,7 @@ I14;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[88]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[7]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -74878,19 +74677,22 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[0]/opit_0_inv_L5Q;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[15]/opit_0_inv_AQ_perm;gopAQ Pin CEOUT;2 +Cout;2 Q;2 RSOUT;2 -Z;2 +Y;2 CE;1 CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 RS;1 Inst @@ -75083,7 +74885,7 @@ I14;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/N124_6/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/N113_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -75093,7 +74895,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_18/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N274/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -75103,17 +74905,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_8[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_txpr_pass/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -75129,7 +74937,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -75253,27 +75061,39 @@ I14;1 RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/N1_2_cpy/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[8]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N291_17/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[1]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -75289,7 +75109,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -75321,7 +75141,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_ba[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[5]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -75353,7 +75173,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[134]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -75369,7 +75189,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[6]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -75385,20 +75205,14 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[6]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N307_9/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[8]/opit_0_inv_L5Q_perm;gopL5Q @@ -75417,7 +75231,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[13]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[8]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -75433,7 +75247,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_done/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[5]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -75481,7 +75295,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -75497,7 +75311,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[14]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -75513,23 +75327,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_13[2]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -75545,7 +75353,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata_en[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_cs_n/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -75572,7 +75380,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_done/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -75604,7 +75412,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_7[2]_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -75625,39 +75433,24 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cke_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_12[0]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit[9]/opit_0_inv_AQ_perm;gopAQ +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_10[0]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Cout;2 -Q;2 -RSOUT;2 -Y;2 -CE;1 -CLK;1 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 -RS;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_8[1]/gateop;gopMUX4TO1 @@ -75671,7 +75464,7 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_10[2]_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -75681,7 +75474,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N309_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_11[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -75691,23 +75484,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/mr_load_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[1]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_12[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_8[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -75717,7 +75504,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_13[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_13[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -75727,7 +75514,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_11[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -75737,30 +75524,39 @@ L3;1 L4;1 Inst -u_axi_ddr_top/axi_fifo_full0/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[15]/opit_0_inv_AQ_perm;gopAQ Pin CEOUT;2 +Cout;2 Q;2 RSOUT;2 -Z;2 +Y;2 CE;1 CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N530_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_rst/opit_0_inv;gopQ @@ -75774,7 +75570,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[5]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cas_n_d[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -75790,7 +75586,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -75806,7 +75602,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/init_start/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -75822,7 +75618,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[8]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[7]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -75838,23 +75634,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[6]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N285/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[6]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -75870,7 +75660,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[7]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -75886,7 +75676,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N235_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N232_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -75912,7 +75702,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N9/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N235_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -75965,7 +75755,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_cs_n/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_ba[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -76036,7 +75826,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_done/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -76084,14 +75874,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N277_5/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/wrlvl_start/opit_0_inv_L5Q_perm;gopL5Q @@ -76110,23 +75906,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[7]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N194_4/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/N141_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/N176_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -76136,23 +75926,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cnt_tmod_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N124_8/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/dbg_wrlvl_or[1]_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/dbg_wrlvl_or[0]_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -76162,7 +75946,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/dbg_wrlvl_or[0]_8/gateop_perm;gopLUT5 +u_axi_ddr_top/wr_sta_fsm[3:0]_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -76172,22 +75956,19 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[7]/opit_0_inv_AQ_perm;gopAQ +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cnt_tmod_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 -Cout;2 Q;2 RSOUT;2 -Y;2 +Z;2 CE;1 CLK;1 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 RS;1 Inst @@ -76288,14 +76069,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/upcal/N84_10[1]_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ras_n_d[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cnt_twldqsen_pass/opit_0_inv;gopQ @@ -76329,27 +76116,39 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N296/gateop_perm;gopLUT5 +u_axi_ddr_top/cnt_wr_num[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N758_44_5/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_odt/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[9]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[6]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -76365,7 +76164,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[6]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -76381,7 +76180,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[6]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -76397,17 +76196,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[3]_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/mr_load_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[5]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -76423,7 +76228,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[5]/opit_0_inv_L5Q;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[5]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -76439,23 +76244,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N334_5/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[7]/opit_0_inv_L5Q;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[96]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -76471,7 +76270,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[8]/opit_0_inv_L5Q;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[9]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -76487,7 +76286,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[11]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[6]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -76503,7 +76302,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cs_n_d[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[6]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -76535,7 +76334,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[12]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[41]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -76551,7 +76350,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_odt/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_dqs_resp_r/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -76567,7 +76366,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_address[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_cas_n/opit_0_inv_L5Q;gopL5Q Pin CEOUT;2 Q;2 @@ -76594,7 +76393,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_odt/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -76610,7 +76409,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_odt_d[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -76626,7 +76425,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt_trfc_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -76642,7 +76441,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -76658,7 +76457,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N758_79/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N395_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -76700,20 +76499,14 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/N141_2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[5]/opit_0_inv_L5Q_perm;gopL5Q @@ -76732,27 +76525,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/N176_1/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N10_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/wr_enable/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_done/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -76768,7 +76557,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N781_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/N124_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -76778,7 +76567,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N671/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N313_mux16_25/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -76788,7 +76577,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N813_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N530_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -76798,7 +76587,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N313_mux16_25/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N530_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -76808,7 +76597,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N370_2_or[0]_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N542_10/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -76818,7 +76607,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N542_6/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N758_44_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -76828,17 +76617,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_1_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt_trfc_pass/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en_inv/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N819_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -76848,17 +76643,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N3[11]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_done/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N542_9/gateop_perm;gopLUT5 +u_axi_ddr_top/N180_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -76868,7 +76669,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N12[7]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N542_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -76878,17 +76679,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N679_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[168]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N679_8/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N752_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -76898,23 +76705,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_ras_n/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/N38_12/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N760_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N286_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -76924,7 +76725,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N136_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N671/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -76934,7 +76735,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N758_44_inv/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N679_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -76944,7 +76745,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N752_10/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N758_44_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -76954,7 +76755,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/ddrphy_rst_ack_r[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -76970,7 +76771,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_fsm[4:0]_5/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N758_78/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -76980,7 +76781,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N813_7/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N685/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -76990,7 +76791,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N144_ac2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/upcal/N84_10[1]_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -77000,7 +76801,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_fsm[4:0]_34/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/upcal/N84_10[2]_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -77010,17 +76811,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N813_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/ref_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N118_17/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N758_44_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -77030,44 +76837,43 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_540_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_success/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[8]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N758_45_2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N758_68/gateop;gopMUX4TO1 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N265_11/gateop_perm;gopLUT5 Pin -F;2 -I0;1 -I1;1 -I2;1 -I3;1 -S0;1 -S1;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/upcal/N84_10[2]_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N781_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -77077,7 +76883,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N359/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N813_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -77103,17 +76909,34 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N758_44_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N760_1/gateop;gopMUX4TO1 +Pin +F;2 +I0;1 +I1;1 +I2;1 +I3;1 +S0;1 +S1;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_dqs_training_rstn/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[15:0]_622_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N205_1_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -77123,7 +76946,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N1814/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N813_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -77133,7 +76956,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/N18/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N813_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -77143,40 +76966,55 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[17]/opit_0_inv_AQ_perm;gopAQ Pin CEOUT;2 +Cout;2 Q;2 RSOUT;2 -Z;2 +Y;2 CE;1 CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N819_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N66_ac2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[1]/opit_0_inv_L5Q_perm;gopL5Q @@ -77195,7 +77033,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N685/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N313_mux16_21/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -77420,7 +77258,7 @@ I14;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N286_13/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N202_79/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -77430,7 +77268,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rddata_cal/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_ras_n/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -77446,14 +77284,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N286_9/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/gatecal_start/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/ddrphy_rst_ack_r[1]/opit_0_inv;gopQ @@ -77478,23 +77322,17 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/gatecal_start/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_fsm[4:0]_34/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N257_64/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_74/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -77504,7 +77342,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/reinit_adj_rdel/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[209]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -77520,7 +77358,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_ba[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_address[10]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -77547,7 +77385,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_cs_n/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_ba[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -77579,7 +77417,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cas_n_d[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_cs_n/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -77595,7 +77433,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_done/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rddata_cal/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -77611,14 +77449,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N440_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_odt/opit_0_inv;gopQ @@ -77632,7 +77476,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N313_mux16_29/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N752_10/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -77642,17 +77486,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[0]_5/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/training_error_d[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N257_44/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N118_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -77662,7 +77512,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[13]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -77678,7 +77528,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_65/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_6[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -77688,7 +77538,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -77715,7 +77565,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[6]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[13]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -77742,7 +77592,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[12]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[10]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -77785,7 +77635,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[10]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[8]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -77817,7 +77667,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[11]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/gate_move_en/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -77833,7 +77683,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/gate_move_en/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[12]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -77849,17 +77699,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N674_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[16]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N813_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N679_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -77896,20 +77752,14 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[16]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N674_2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[17]/opit_0_inv_L5Q_perm;gopL5Q @@ -77928,7 +77778,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_76/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N118_24/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -77938,39 +77788,27 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdel_calibration/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N758_44_inv/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_address[10]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N238/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[106]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[32]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -77986,7 +77824,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[160]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[64]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -78002,7 +77840,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata_en[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[102]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -78018,17 +77856,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N409/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[35]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[36]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[160]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -78044,7 +77888,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata_en[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_odt_d[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -78086,7 +77930,7 @@ I14;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[100]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[32]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -78102,7 +77946,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[164]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[40]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -78118,7 +77962,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/wr_enable/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[175]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -78134,7 +77978,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_en[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_en[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -78161,7 +78005,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N758_45_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N679_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -78187,7 +78031,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N257_68/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N286_10/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -78229,7 +78073,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N257_60/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N813_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -78239,33 +78083,33 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_72/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[147]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_en[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/dbg_wrlvl_or[1]_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N213_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N10_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -78275,17 +78119,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_313/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_cas_n/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N55_mux6/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N286_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -78295,23 +78145,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/dqs_rst_training_high_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[5]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N232_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -78332,17 +78176,20 @@ D;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N8.lt_2/gateop_perm;gopA +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_ioclk_gate/opit_0_inv_L5Q_perm;gopL5Q Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[0]/opit_0_inv;gopQ @@ -78653,7 +78500,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[30]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[9]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -78669,17 +78516,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N457_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[7]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[6]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[14]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -78695,7 +78548,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[33]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -78711,7 +78564,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[41]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[13]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -78727,7 +78580,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[7]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -78743,33 +78596,33 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N457_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[16]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[10]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[3]_2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[6]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -78785,7 +78638,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[13]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -78801,23 +78654,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N2048_2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[12]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[14]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -78833,7 +78680,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[31]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -78849,7 +78696,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[14]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[11]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -78865,7 +78712,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[6]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -78881,7 +78728,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_cmd_act/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[35]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -78897,7 +78744,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[33]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[32]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -78913,7 +78760,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_cmd_accepted_l/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -78929,7 +78776,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[36]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[40]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -78945,20 +78792,14 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[35]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N50[3]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[37]/opit_0_inv_L5Q_perm;gopL5Q @@ -78993,7 +78834,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[38]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[19]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -79009,7 +78850,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_l[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[8]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -79041,24 +78882,36 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N543_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[2]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N524_7/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[7]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba[0]/opit_0_inv;gopQ @@ -79127,23 +78980,17 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cs_n_d[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/N167_5/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N233_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -79153,20 +79000,14 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[7]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N1025_1_2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[8]/opit_0_inv_L5Q_perm;gopL5Q @@ -79185,7 +79026,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_cwl_3[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N544_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -79195,20 +79036,14 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_ba[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N12[1]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cas_n[0]/opit_0_inv;gopQ @@ -79233,7 +79068,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ras_n_d[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cs_n_d[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -79249,7 +79084,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_we_n_d[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cs_n_d[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -79276,7 +79111,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[108]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -79314,19 +79149,22 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_we_n_d[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[7]/opit_0_inv_AQ_perm;gopAQ Pin CEOUT;2 +Cout;2 Q;2 RSOUT;2 -Z;2 +Y;2 CE;1 CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 RS;1 Inst @@ -79384,20 +79222,14 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_odt/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N286_13/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ras_n[0]/opit_0_inv;gopQ @@ -79422,17 +79254,23 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_we_n_d[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_we_n_d[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -79470,7 +79308,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_cas_n/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cas_n_d[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -79486,14 +79324,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N12[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_cke/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[0]/opit_0_inv;gopQ @@ -82312,7 +82156,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[35]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -82328,7 +82172,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[97]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[103]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -82344,7 +82188,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[71]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[7]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -82360,7 +82204,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[68]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[131]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -82376,7 +82220,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[34]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[5]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -82392,17 +82236,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N165/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[132]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[70]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -82418,7 +82268,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[65]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[130]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -82434,7 +82284,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[72]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[12]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -82450,7 +82300,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[237]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[13]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -82466,7 +82316,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[12]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[136]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -82482,7 +82332,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[205]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[75]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -82498,7 +82348,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[204]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[72]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -82514,17 +82364,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N252/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[73]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[75]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[78]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -82540,7 +82396,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[207]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -82556,7 +82412,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[17]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[144]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -82572,7 +82428,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[20]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[145]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -82588,7 +82444,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[145]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[82]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -82604,7 +82460,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[23]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[85]/opit_0_inv_L5Q_perm;gopL5Q +Pin +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[21]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -82635,6 +82507,22 @@ L3;1 L4;1 RS;1 +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[86]/opit_0_inv_L5Q_perm;gopL5Q +Pin +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 + Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[83]/opit_0_inv_L5Q_perm;gopL5Q Pin @@ -82652,7 +82540,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[150]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[89]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -82668,7 +82556,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[85]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[95]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -82684,7 +82572,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[25]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[27]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -82700,7 +82588,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[222]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[157]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -82716,7 +82604,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[28]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[29]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -82732,7 +82620,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[95]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[221]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -82748,7 +82636,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[158]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[179]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -82780,7 +82668,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[31]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[160]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -82796,7 +82684,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[159]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[227]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -82812,7 +82700,55 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[160]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[98]/opit_0_inv_L5Q_perm;gopL5Q +Pin +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[38]/opit_0_inv_L5Q_perm;gopL5Q +Pin +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[106]/opit_0_inv_L5Q_perm;gopL5Q +Pin +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[128]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -82844,7 +82780,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[98]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -82860,7 +82796,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[96]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[168]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -82876,7 +82812,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[42]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[74]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -82892,7 +82828,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[99]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[100]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -82908,7 +82844,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[129]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[45]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -82924,7 +82860,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[166]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[108]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -82940,7 +82876,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[104]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[46]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -82972,7 +82908,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[234]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[204]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -82988,7 +82924,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[45]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[60]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83004,7 +82940,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[168]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/adj_rdel_done/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83020,23 +82956,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[169]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3402/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[74]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[55]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83052,7 +82982,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[76]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[53]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83068,7 +82998,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[112]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[116]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83084,7 +83014,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[240]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[120]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83100,7 +83030,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[53]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[56]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83116,7 +83046,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[55]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[244]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83132,7 +83062,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[54]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[59]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83148,23 +83078,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[180]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N17[3]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[178]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[63]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83180,7 +83104,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[179]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[121]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83196,7 +83120,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[58]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[62]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83212,7 +83136,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[126]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[189]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83228,7 +83152,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[188]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[185]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83244,7 +83168,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[63]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[66]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83260,7 +83184,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[122]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[69]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83276,7 +83200,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[123]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[71]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83292,7 +83216,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[125]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[70]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83308,7 +83232,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[253]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[129]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83324,7 +83248,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[68]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[192]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83340,7 +83264,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[194]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[198]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83356,7 +83280,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[128]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[196]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83372,7 +83296,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[195]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[76]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83388,17 +83312,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N124_1/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[131]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[201]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83414,7 +83328,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[134]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[138]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83430,7 +83344,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[193]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[139]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83446,7 +83360,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[111]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[9]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83462,7 +83376,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[77]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[137]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83478,7 +83392,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[137]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[142]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83494,23 +83408,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[78]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/N14[2]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[109]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[81]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83526,7 +83434,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[142]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[18]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83542,7 +83450,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[206]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[210]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83558,7 +83466,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[143]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[87]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83574,17 +83482,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N136_1/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[208]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83600,7 +83498,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[86]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[151]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83616,7 +83514,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[87]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[150]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83632,7 +83530,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[144]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83648,7 +83546,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[215]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[90]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83664,7 +83562,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[210]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[91]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83680,7 +83578,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[147]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[92]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83696,23 +83594,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[223]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N167.eq_4/gateop_perm;gopA Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[217]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[156]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83728,17 +83623,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/N55_mux6/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[93]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[217]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83754,7 +83639,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[216]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[155]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83770,7 +83655,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[221]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[122]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83786,17 +83671,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N232_1/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[153]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_ba[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83812,7 +83687,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[161]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83828,7 +83703,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[225]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[162]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83844,7 +83719,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[101]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83860,7 +83735,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[101]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[228]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83876,7 +83751,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[228]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[163]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83892,7 +83767,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[167]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[229]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83908,7 +83783,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[103]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[166]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83924,7 +83799,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[230]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[171]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83940,7 +83815,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[105]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[110]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83956,7 +83831,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[6]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[164]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83972,7 +83847,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[170]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[47]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -83988,7 +83863,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[171]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[172]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84004,17 +83879,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N417[0]_14/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[136]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[169]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84030,7 +83895,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[235]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[111]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84046,7 +83911,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[174]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[233]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84062,7 +83927,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[241]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[113]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84078,23 +83943,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[114]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_542_2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[115]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[246]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84110,7 +83969,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[242]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[117]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84126,7 +83985,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[117]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[241]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84142,7 +84001,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[118]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[184]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84174,7 +84033,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[124]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84190,7 +84049,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[248]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[180]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84206,7 +84065,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[127]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[251]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84222,7 +84081,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[124]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[188]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84238,7 +84097,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_done_flag/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[187]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84254,7 +84113,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[252]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[222]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84270,7 +84129,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[183]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[126]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84286,7 +84145,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[127]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84302,7 +84161,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[191]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[253]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84318,23 +84177,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[132]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N173_9/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[165]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[135]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84350,7 +84203,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[192]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84366,23 +84219,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[197]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N334_6/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[229]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[133]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84398,7 +84245,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[135]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[99]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84414,7 +84261,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[198]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[195]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84430,23 +84277,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_check_done/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N173_8/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[9]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[200]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84462,7 +84303,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[200]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[205]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84510,23 +84351,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[202]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_fsm[4:0]_5/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[201]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[143]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84542,7 +84377,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[207]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[206]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84558,23 +84393,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N334_5/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[148]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84590,7 +84419,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[146]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_rdel_done/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84606,23 +84435,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_resp/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N451_and[0][2]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[16]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[208]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84638,7 +84461,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[213]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[212]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84654,7 +84477,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[151]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84670,7 +84493,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[52]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[214]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84686,23 +84509,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[211]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N417[0]_15/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[153]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84718,7 +84535,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[155]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[186]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84734,7 +84551,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[156]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[158]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84750,17 +84567,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N205_1_5/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[216]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[157]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[26]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84776,7 +84599,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[94]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[159]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84792,7 +84615,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N144_ac2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3376/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -84802,7 +84625,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[219]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[95]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84818,7 +84641,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[161]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[224]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84834,7 +84657,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[163]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[225]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84850,7 +84673,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[224]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[226]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84866,7 +84689,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[96]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[165]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84882,7 +84705,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_en[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[170]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84898,7 +84721,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[231]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N228_10/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[167]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84914,7 +84747,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[227]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84930,17 +84763,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N307_12/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[232]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[232]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[237]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84956,7 +84795,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N564_25/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N475/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -84966,7 +84805,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[172]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[173]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84982,7 +84821,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[175]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[236]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -84998,7 +84837,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[44]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[174]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -85014,17 +84853,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N286_10/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[13]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -85040,7 +84869,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[200]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_en[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -85056,17 +84885,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_316/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[183]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[181]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[249]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -85082,7 +84917,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[182]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[181]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -85098,7 +84933,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_vld/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[219]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -85114,7 +84949,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_vld/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[182]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -85130,7 +84965,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[243]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[250]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -85146,7 +84981,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[178]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[241]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -85162,7 +84997,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[251]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[248]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -85178,7 +85013,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[186]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[245]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -85194,7 +85029,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[2]_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -85204,23 +85039,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[250]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3410/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[189]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[191]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -85236,7 +85065,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -85268,7 +85097,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[255]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[123]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -85284,33 +85113,33 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[249]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N446_0_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[15:0]_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[197]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[199]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[194]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -85326,23 +85155,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[196]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en_inv/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N136_7/gateop_perm;gopLUT5 +u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -85352,7 +85175,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -85368,17 +85191,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N307_10/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[193]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[192]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[199]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -85394,7 +85223,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[37]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[64]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -85410,7 +85239,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[73]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[202]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -85426,55 +85255,37 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[203]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N286_13/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[233]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N66_ac1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[14]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N136_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_start_rst/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_resp/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -85490,7 +85301,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_move_done/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/dq_rising/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -85506,7 +85317,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N633_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N359/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -85516,7 +85327,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N637_10/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N466_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -85526,7 +85337,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[209]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[211]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -85542,39 +85353,27 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/dq_rising/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N13_4/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[214]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N417[0]_15/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[212]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[84]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -85590,23 +85389,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[209]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N247_1_1_or[0]_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[18]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/dq_rising/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -85622,7 +85415,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3423/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_check_done/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -85638,17 +85441,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N645_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[218]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[218]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[220]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -85664,17 +85473,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N271_13/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[88]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[220]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[252]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -85690,7 +85505,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N194_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N614_1_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -85700,7 +85515,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[222]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[223]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -85716,7 +85531,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[90]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[94]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -85732,7 +85547,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[223]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[31]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -85748,17 +85563,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/N55_mux6/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[226]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[34]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -85774,7 +85579,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[162]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[229]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -85790,7 +85595,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_resp/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[128]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -85806,7 +85611,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[230]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[230]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -85822,7 +85627,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_en[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[234]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -85838,7 +85643,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[38]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -85854,17 +85659,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N173_9/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[231]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[227]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[97]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -85880,17 +85691,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N334_6/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[235]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[46]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -85906,14 +85723,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N165/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[44]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[238]/opit_0_inv_L5Q_perm;gopL5Q @@ -85932,7 +85755,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ck_check_done/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata_en[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -85948,7 +85771,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_start_rst/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -85980,23 +85803,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[74]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N386/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[245]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[242]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -86012,7 +85829,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[244]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[116]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -86028,7 +85845,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[243]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -86044,7 +85861,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[246]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[247]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -86060,23 +85877,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[49]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N538/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[247]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[52]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -86092,23 +85903,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[113]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N279_7/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[114]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[247]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -86124,7 +85929,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_vld/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[24]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -86140,17 +85945,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N205_1_5/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[255]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[93]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -86166,17 +85977,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N151_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[176]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[27]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[88]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -86192,23 +86009,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[254]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N247_1_1_or[0]_4/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[187]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -86224,23 +86035,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[123]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N610/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[128]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[5]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -86256,17 +86061,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_en[2]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[234]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_en[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -86282,20 +86093,14 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/N14[3]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask[0]/opit_0_inv;gopQ @@ -86331,7 +86136,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[24]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[8]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -86347,7 +86152,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[24]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -86363,7 +86168,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[5]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -86379,14 +86184,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_11/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[1]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/N95_4/gateop;gopMUX4TO1 @@ -86400,20 +86211,14 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N465_2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[2]/opit_0_inv_L5Q_perm;gopL5Q @@ -86476,7 +86281,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/N38_12/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N124_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -86556,23 +86361,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N542_9/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[5]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -86588,7 +86387,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[3]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -86598,7 +86397,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[5]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[135]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -86613,6 +86412,16 @@ L3;1 L4;1 RS;1 +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[0]_3/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[2]/gateop_perm;gopLUT5 Pin @@ -86624,7 +86433,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N12[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N457_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -86634,7 +86443,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[15:0]_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N382_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -86644,23 +86453,27 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[130]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N532_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[128]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[15:0]_5/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[198]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -86676,7 +86489,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N63/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N382_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -86686,7 +86499,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[10]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N457_3/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[6]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -86702,7 +86525,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[15:0]_1268/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N307_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -86712,23 +86535,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N532_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[64]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[5]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -86744,7 +86561,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wdin_en_dly[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cke_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -86760,23 +86577,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[171]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N271_5/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N232_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_cwl_3[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -86786,7 +86597,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N439/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -86836,7 +86647,7 @@ I13;1 I14;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_bank[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_cas_n/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -86961,7 +86772,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[14]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[8]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -86977,7 +86788,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[6]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87009,7 +86820,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[5]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[7]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87025,7 +86836,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[7]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[6]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87041,23 +86852,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[8]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N12[9]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[5]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[67]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87073,7 +86878,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[12]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[10]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87089,7 +86894,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[11]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[13]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87105,7 +86910,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[14]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87121,17 +86926,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N25_1/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[8]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[12]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87147,7 +86942,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[9]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87163,17 +86958,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N66_ac1/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87189,23 +86974,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[9]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[15:0]_416_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87221,7 +87000,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[6]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[8]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87237,7 +87016,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87253,7 +87032,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[7]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[5]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87269,7 +87048,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87285,7 +87064,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[8]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[7]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87317,7 +87096,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[195]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[11]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87333,7 +87112,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[11]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[5]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87349,7 +87128,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[5]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[9]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87365,7 +87144,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[12]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[13]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87381,7 +87160,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[12]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[64]/opit_0_inv_L5Q_perm;gopL5Q +Pin +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[12]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87413,17 +87208,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N307_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[9]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[9]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87439,7 +87240,27 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[7]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[15:0]_1285/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N124_1/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87455,7 +87276,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[11]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[8]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87471,7 +87292,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[14]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[5]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87487,7 +87308,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[6]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[12]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87503,7 +87324,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[6]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87519,7 +87350,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[5]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[7]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87535,7 +87366,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[10]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87551,7 +87382,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[8]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87567,17 +87398,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N173_8/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[9]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[10]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[13]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87593,7 +87430,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[13]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[11]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87609,7 +87446,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[23]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87625,7 +87462,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[12]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N1286_4/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87641,7 +87488,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[13]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87657,7 +87504,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87673,37 +87520,55 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N359/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[38]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N265_11/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[8]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N752_8/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[10]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87719,7 +87584,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[9]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[7]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87735,7 +87610,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[14]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[11]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87751,7 +87626,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[6]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N417[0]_15/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[9]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87767,7 +87652,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[3]/opit_0_inv_L5Q;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[13]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87783,7 +87668,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[7]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87799,7 +87684,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[7]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[12]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87815,7 +87700,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[8]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[14]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87831,7 +87716,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[10]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[14]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87847,7 +87732,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[12]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N307_3/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[11]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87863,7 +87758,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[11]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[13]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87879,7 +87774,80 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[0]_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N29_1_1/gateop_A2;gopA2 +Pin +Cout;2 +Y0;2 +Y1;2 +Cin;1 +I0X;1 +I1X;1 +I00;1 +I01;1 +I02;1 +I03;1 +I04;1 +I10;1 +I11;1 +I12;1 +I13;1 +I14;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N29_1_3/gateop_A2;gopA2 +Pin +Cout;2 +Y0;2 +Y1;2 +Cin;1 +I0X;1 +I1X;1 +I00;1 +I01;1 +I02;1 +I03;1 +I04;1 +I10;1 +I11;1 +I12;1 +I13;1 +I14;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N29_1_5/gateop_A2;gopA2 +Pin +Cout;2 +Y0;2 +Y1;2 +Cin;1 +I0X;1 +I1X;1 +I00;1 +I01;1 +I02;1 +I03;1 +I04;1 +I10;1 +I11;1 +I12;1 +I13;1 +I14;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N29_1_7/gateop;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_fsm[3:0]_101/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -87889,7 +87857,47 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[13]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N240_5/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_113/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N241_6_3/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_fsm[3:0]_104/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87905,7 +87913,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87921,7 +87929,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[9]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87937,7 +87945,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[198]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[6]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87953,7 +87961,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[102]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87969,7 +87977,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[4]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_fsm[3:0]_1_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -87979,7 +87987,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_dll_rst_rg/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[7]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -87995,17 +88003,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_fsm[3:0]_65_3/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_fsm[3:0]_34_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_136/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -88015,117 +88013,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[7]/opit_0_inv_AQ_perm;gopAQ -Pin -CEOUT;2 -Cout;2 -Q;2 -RSOUT;2 -Y;2 -CE;1 -CLK;1 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 -RS;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[2]/opit_0_inv_A2Q21;gopA2Q2 -Pin -CEOUT;2 -Cout;2 -Q0;2 -Q1;2 -RSOUT;2 -Y0;2 -Y1;2 -CE;1 -CLK;1 -Cin;1 -I0X;1 -I1X;1 -I00;1 -I01;1 -I02;1 -I03;1 -I04;1 -I10;1 -I11;1 -I12;1 -I13;1 -I14;1 -RS;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[4]/opit_0_inv_A2Q21;gopA2Q2 -Pin -CEOUT;2 -Cout;2 -Q0;2 -Q1;2 -RSOUT;2 -Y0;2 -Y1;2 -CE;1 -CLK;1 -Cin;1 -I0X;1 -I1X;1 -I00;1 -I01;1 -I02;1 -I03;1 -I04;1 -I10;1 -I11;1 -I12;1 -I13;1 -I14;1 -RS;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[6]/opit_0_inv_A2Q21;gopA2Q2 -Pin -CEOUT;2 -Cout;2 -Q0;2 -Q1;2 -RSOUT;2 -Y0;2 -Y1;2 -CE;1 -CLK;1 -Cin;1 -I0X;1 -I1X;1 -I00;1 -I01;1 -I02;1 -I03;1 -I04;1 -I10;1 -I11;1 -I12;1 -I13;1 -I14;1 -RS;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_fsm[3:0]_1_4/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_b_neg/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_dll_rst_rg/opit_0_inv_L5Q;gopL5Q Pin CEOUT;2 Q;2 @@ -88152,20 +88040,14 @@ D;1 RS;1 Inst -rstn_5s/opit_0_inv_L5Q_perm;gopL5Q +u_rotate_image/N52_mux6_6/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N11_1_1/gateop_A2;gopA2 @@ -88348,7 +88230,20 @@ I13;1 I14;1 Inst -u_axi_ddr_top/s_axi_rdata0[87]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_r/N161.lt_2/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[12]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -88364,7 +88259,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_111/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N68_14_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -88374,7 +88269,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N57_12_or[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_36_cpy/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -88384,7 +88279,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_7/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -88394,7 +88289,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/rd_ddr_valid/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -88410,7 +88305,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -88426,7 +88321,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -88442,7 +88337,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[5]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -88458,7 +88353,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[5]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[6]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -88474,7 +88369,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[7]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[9]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -88490,7 +88385,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[8]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -88506,7 +88401,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[8]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[7]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -88522,7 +88417,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[6]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -88538,7 +88433,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[12]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -88570,7 +88465,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[14]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[11]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -88586,7 +88481,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[11]/opit_0_inv_L5Q;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[13]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -88602,7 +88497,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[9]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[8]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -88618,7 +88513,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[14]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -88634,7 +88529,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[18]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -88682,24 +88577,33 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[8]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[18]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_15/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N39.lt_2/gateop_perm;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_b_ff/opit_0_inv;gopQ @@ -88713,23 +88617,17 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_deb_pre/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_36/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_29/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -88816,17 +88714,23 @@ D;1 RS;1 Inst -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_33/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -88847,7 +88751,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_fsm[3:0]_106/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_fsm[3:0]_1_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -88857,7 +88761,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_fsm[3:0]_105/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_62/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -88867,7 +88771,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_fsm[3:0]_101/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N22_10[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -88877,23 +88781,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_129/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N84/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N55/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -88903,7 +88801,7 @@ L3;1 L4;1 Inst -_N18115_inv/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_fsm[3:0]_106/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -88913,7 +88811,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[5]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N202_39/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -88923,7 +88821,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[5]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -88939,7 +88837,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[5]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -88987,23 +88885,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[8]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_fsm[3:0]_65_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[13]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[6]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -89019,7 +88911,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[7]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[8]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -89035,23 +88927,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N118_17/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N219/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N84/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -89061,7 +88947,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N295_mux2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/N14[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -89148,23 +89034,17 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N313_mux16_29/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[33]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -89180,7 +89060,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_move_done/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[212]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -89196,27 +89076,52 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N21_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N167.eq_4/gateop_perm;gopA Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q +Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_6[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N301/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N34_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -89226,17 +89131,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_14[3]/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[96]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_5[2]_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/N4_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -89246,7 +89157,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_129/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_9[2]_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -89256,7 +89167,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_4[1]_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_6[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -89339,7 +89250,7 @@ I3;1 I4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N257_75/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N279_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -89381,7 +89292,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N249/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[1]_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -89391,7 +89302,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[5]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -89407,7 +89318,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -89439,7 +89350,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[6]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -89455,7 +89366,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[8]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[5]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -89471,39 +89382,27 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[6]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N417[0]_14/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[7]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[7:0]_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en_inv/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/N18/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -89513,7 +89412,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -89528,16 +89427,6 @@ L3;1 L4;1 RS;1 -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N286_9/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_ddc_ca/opit_0;gopDQS_DDC Pin @@ -89775,17 +89664,7 @@ WL_STEP[6];1 WL_STEP[7];1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N205_1_5/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N265_11/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_82/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -89795,17 +89674,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N63/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[96]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_115/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N213_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -89815,7 +89700,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -89831,7 +89716,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -89847,7 +89732,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -89863,7 +89748,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_vld/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -89879,7 +89764,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[2]_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N813_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -89889,7 +89774,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_137_5/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N370_2_or[0]_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -89899,7 +89784,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_137_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -89909,7 +89794,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[3]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_159_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -89919,7 +89804,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[80]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -89935,23 +89820,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_198_5/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_198_5/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N22/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -89961,7 +89840,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[3]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -89971,17 +89850,33 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_14[3]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[3]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_105/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_comb_r[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -89997,7 +89892,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -90013,17 +89908,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[6]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[219]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -90039,7 +89940,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N213_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[10]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -90049,39 +89950,27 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[121]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_14[3]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[251]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_4[1]_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[13]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[14]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -90091,23 +89980,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[15]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[15]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_5[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -90117,7 +90000,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[91]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -90573,20 +90456,14 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_113_5/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q @@ -90673,23 +90550,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[13]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -90705,20 +90576,14 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_5[2]_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[0]/opit_0_inv;gopQ @@ -90820,7 +90685,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_9[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/N161_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -90846,7 +90711,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_159_5/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_5[2]_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -90856,7 +90721,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[7]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_14[3]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -90866,7 +90731,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_103/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_78/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -90903,17 +90768,23 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N446_0_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[2]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -90973,7 +90844,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N57_12_or[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N301/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -90983,7 +90854,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_fsm[2:0]_36/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_9[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -91015,7 +90886,7 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N306_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_5[2]_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -91025,7 +90896,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N118_20/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_14[3]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -91086,7 +90957,68 @@ S10;1 S11;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_error/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_14[3]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_9[2]_2/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_9[0]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_7[0]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_7[2]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_7[1]/gateop;gopMUX4TO1 +Pin +F;2 +I0;1 +I1;1 +I2;1 +I3;1 +S0;1 +S1;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_adj_done/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -91102,7 +91034,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_109/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N138/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -91112,94 +91044,33 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_83/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_7[0]/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_131/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_7[1]/gateop;gopMUX4TO1 -Pin -F;2 -I0;1 -I1;1 -I2;1 -I3;1 -S0;1 -S1;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_9[2]_2/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N118_9/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N466/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N118_20/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N55/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_7[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -91209,7 +91080,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N81_1_0/gateop_A2;gopA2 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N81_1_1/gateop_A2;gopA2 Pin Cout;2 Y0;2 @@ -91229,7 +91100,7 @@ I13;1 I14;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N81_1_2/gateop_A2;gopA2 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N81_1_3/gateop_A2;gopA2 Pin Cout;2 Y0;2 @@ -91249,27 +91120,20 @@ I13;1 I14;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N81_1_4/gateop_A2;gopA2 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N81_1_5/gateop;gopA Pin Cout;2 -Y0;2 -Y1;2 +Y;2 Cin;1 +I0;1 I0X;1 -I1X;1 -I00;1 -I01;1 -I02;1 -I03;1 -I04;1 -I10;1 -I11;1 -I12;1 -I13;1 -I14;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_111/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N22_10[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -91279,7 +91143,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N55/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N57_12_or[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -91289,7 +91153,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N124_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N301/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -91299,7 +91163,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N607/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N431_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -91309,18 +91173,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N328_10/gateop;gopMUX4TO1 -Pin -F;2 -I0;1 -I1;1 -I2;1 -I3;1 -S0;1 -S1;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -91335,6 +91188,16 @@ L3;1 L4;1 RS;1 +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N55/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q Pin @@ -91368,7 +91231,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N610/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_fsm[2:0]_36/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -91389,17 +91252,23 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N564_25/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -91415,7 +91284,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gate_check/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -91431,7 +91300,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/dqs_gate_check_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -91458,7 +91327,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[119]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -91474,7 +91343,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_cal_error/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -91490,23 +91359,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N538_5/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/dqs_gate_check_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -91538,14 +91401,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_7[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[1]/opit_0_inv_L5Q_perm;gopL5Q @@ -91564,7 +91433,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -91596,14 +91465,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3383/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_cal_error/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[5]/opit_0_inv_L5Q_perm;gopL5Q @@ -91622,14 +91497,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N610/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[0]/opit_0_inv;gopQ @@ -91730,7 +91611,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -91746,22 +91627,27 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N247_1_1_or[0]_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[4]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[2]/opit_0_inv_A2Q21;gopA2Q2 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[1]/opit_0_inv_A2Q1;gopA2Q1 Pin CEOUT;2 Cout;2 -Q0;2 -Q1;2 +Q;2 RSOUT;2 Y0;2 Y1;2 @@ -91783,7 +91669,7 @@ I14;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[4]/opit_0_inv_A2Q21;gopA2Q2 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[3]/opit_0_inv_A2Q21;gopA2Q2 Pin CEOUT;2 Cout;2 @@ -91810,36 +91696,50 @@ I14;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[5]/opit_0_inv_AQ;gopAQ +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[5]/opit_0_inv_A2Q21;gopA2Q2 Pin CEOUT;2 Cout;2 -Q;2 +Q0;2 +Q1;2 RSOUT;2 -Y;2 +Y0;2 +Y1;2 CE;1 CLK;1 Cin;1 -I0;1 I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +I1X;1 +I00;1 +I01;1 +I02;1 +I03;1 +I04;1 +I10;1 +I11;1 +I12;1 +I13;1 +I14;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N466/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[6]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_1_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N296/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -91849,7 +91749,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N334_5/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N409/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -91859,39 +91759,38 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[225]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N194_4/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[6]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N359/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[66]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N72/gateop;gopMUX4TO1 +Pin +F;2 +I0;1 +I1;1 +I2;1 +I3;1 +S0;1 +S1;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -91907,7 +91806,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N386/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N124_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -91917,7 +91816,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N439/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N165/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -91927,23 +91826,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[133]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_4[1]_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N66_ac2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N136_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -91953,7 +91846,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -91969,33 +91862,33 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N439/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N173_9/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[37]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -92011,7 +91904,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N334_6/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/N14[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -92021,7 +91914,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_check_done/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -92037,39 +91930,27 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[132]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_4/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_5/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N417[0]_14/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N279_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -92079,7 +91960,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/N18[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N417[0]_14/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -92089,27 +91970,58 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N286_13/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N395_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/opit_0_inv_AQ_perm;gopAQ +Pin +CEOUT;2 +Cout;2 +Q;2 +RSOUT;2 +Y;2 +CE;1 +CLK;1 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 +RS;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[236]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/N18[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N286_10/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -92119,7 +92031,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[5]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -92135,17 +92047,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[0]_5/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[1]_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/N18[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -92166,17 +92084,23 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N228_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[7:0]_388/gateop_perm;gopLUT5 +u_axi_ddr_top/N129/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -92186,7 +92110,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/N14[3]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/wdata_path_adj/N18[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -92212,17 +92136,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_7/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[65]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_check_done/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -92238,7 +92168,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N271_9/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[238]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -92253,17 +92193,6 @@ L3;1 L4;1 RS;1 -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N475_1/gateop;gopMUX4TO1 -Pin -F;2 -I0;1 -I1;1 -I2;1 -I3;1 -S0;1 -S1;1 - Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/dq_rising/opit_0_inv_L5Q_perm;gopL5Q Pin @@ -92369,23 +92298,14 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/opit_0_inv_AQ_perm;gopAQ +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N249/gateop_perm;gopLUT5 Pin -CEOUT;2 -Cout;2 -Q;2 -RSOUT;2 -Y;2 -CE;1 -CLK;1 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 -RS;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[2]/opit_0_inv_A2Q21;gopA2Q2 @@ -92469,7 +92389,7 @@ I14;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -92485,21 +92405,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt[0]/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 -F;2 Q;2 RSOUT;2 +Z;2 CE;1 CLK;1 -I0;1 -I1;1 -I2;1 -I3;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 RS;1 -S0;1 -S1;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt[2]/opit_0_inv_L5Q_perm;gopL5Q @@ -92518,7 +92437,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -92534,7 +92453,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt[3]/opit_0_inv_L5Q;gopL5Q Pin CEOUT;2 Q;2 @@ -92550,14 +92469,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N124_8/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[42]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ddrphy_gatei/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q @@ -92577,40 +92502,46 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[7:0]_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N124_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/N18[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[1]/opit_0_inv_A2Q1;gopA2Q1 @@ -92820,7 +92751,7 @@ I14;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N439/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N279_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -92846,14 +92777,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/wdata_path_adj/N18[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q @@ -92872,7 +92809,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_resp/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -92888,7 +92825,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[6]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -92904,7 +92841,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[5]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[6]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -92920,17 +92857,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N279_8/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[104]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata_en[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -92962,7 +92905,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -92978,7 +92921,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -92994,23 +92937,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/N21[0]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[5]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -93026,20 +92963,14 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[67]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N151_4/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_flag/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q @@ -93059,20 +92990,14 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_377/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[1]/opit_0_inv_L5Q_perm;gopL5Q @@ -93091,7 +93016,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -93107,7 +93032,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/N18[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -93165,47 +93090,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N307_11/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N17[3]/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N165/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N12[9]/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N232_5/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N228_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -93215,7 +93100,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N417[0]_15/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N66_ac1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -93236,23 +93121,17 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N386/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_done_flag/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -93268,7 +93147,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N286_10/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en_inv/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -93305,7 +93184,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[6]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -93369,20 +93248,14 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[6]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N165/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm;gopL5Q @@ -93401,7 +93274,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -93881,27 +93754,7 @@ MI;1 T;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N249/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N139/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N118_9/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_fsm[2:0]_39_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -93911,7 +93764,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N118_13/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_6[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -93931,17 +93784,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_107/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[6]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N451_and[0][2]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N202_51/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -93951,7 +93810,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_92/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N202_35/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -93961,7 +93820,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/s_axi_rdata0[3]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[34]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -93977,7 +93836,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N257_56/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N202_43/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -93987,23 +93846,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/adj_rdel_done/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_70/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_6/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_117/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -94013,23 +93866,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/dqs_gate_check_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_94/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_96/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_125/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -94039,7 +93886,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/s_axi_rdata0[1]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -94055,7 +93902,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_99/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N758_76/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -94065,7 +93912,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N118_20/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_97/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -94075,7 +93922,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N257_69/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_109/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -94085,7 +93932,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N257_52/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_121/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -94095,17 +93942,43 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N257_48/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_vld/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[129]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_130/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N219_2/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -94121,27 +93994,39 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_119/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[38]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_123/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[32]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[132]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[230]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -94157,7 +94042,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N16_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_137/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -94167,7 +94052,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_84/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_90/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -94177,7 +94062,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_64/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_66/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -94187,7 +94072,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N621_1_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N194_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -94197,7 +94082,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/N161_5/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N55/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -94207,7 +94092,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_542_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N202_55/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -94217,57 +94102,87 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N637_6/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[133]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N257_76/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_vld/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/N14[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[134]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_88/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[35]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_fsm[2:0]_39_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -94299,7 +94214,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[85]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_check_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -94331,7 +94246,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_check_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -94347,20 +94262,14 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N21_2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q @@ -94379,17 +94288,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N669_74_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3453/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N21_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -95103,20 +95018,14 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_cal_vld/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/N18/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rdvalid_r1/opit_0_inv;gopQ @@ -95130,17 +95039,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N67_1_sum3/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N14/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N694_inv/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -95150,7 +95049,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -95166,20 +95065,27 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[24]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N108.eq_4/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N28_1.fsub_0/gateop_A2;gopA2 @@ -95242,7 +95148,7 @@ I13;1 I14;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[6]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -95444,20 +95350,14 @@ I13;1 I14;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N384_5/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N85_1/gateop_A2;gopA2 @@ -95580,20 +95480,14 @@ I13;1 I14;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3384/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N167.eq_0/gateop_A2;gopA2 @@ -95636,23 +95530,17 @@ I13;1 I14;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N247_1_1_or[0]_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N451_and[0][2]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_540_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -95662,39 +95550,27 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[10]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N694_inv/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_rdel_done/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[1]_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_542_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_544/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -95704,17 +95580,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N683_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_dqs_training_rstn/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_inc_dec_n/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -95730,7 +95612,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N417[0]_15/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N446_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -95740,7 +95622,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N451_or[0]_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -95750,7 +95632,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en_inv/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -95760,23 +95642,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N683_2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[202]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -95825,7 +95701,7 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[73]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[146]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -95841,7 +95717,27 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_6/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_4/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_move_done/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -95857,7 +95753,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[5]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -95873,7 +95769,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N279_8/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N621_1_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -95883,7 +95779,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N13_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N286_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -95893,23 +95789,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_done_flag/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3387/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[139]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -95925,7 +95815,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3422/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N669_74_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -95935,17 +95825,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_542_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[218]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[11]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -95971,113 +95867,27 @@ L3;1 L4;1 Inst -u_axi_ddr_top/s_axi_rdata0[69]/opit_0_L5Q_perm;gopL5Q -Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N694_inv/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[0]/opit_0_inv_L5Q_perm;gopL5Q -Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[0]/opit_0_inv_L5Q_perm;gopL5Q -Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[85]/opit_0_inv_L5Q_perm;gopL5Q -Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N701_7/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_adj_done/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N17[0]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N446_0_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3393/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -96087,7 +95897,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[217]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -96103,17 +95913,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_6/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/s_axi_rdata0[109]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -96129,7 +95929,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -96177,20 +95977,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N28_1.fsub_6/gateop_perm;gopA Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[0]/opit_0_inv_L5Q_perm;gopL5Q @@ -96209,23 +96006,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[0]/opit_0_inv_L5Q_perm;gopL5Q -Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_done/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -96368,20 +96149,17 @@ I14;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N108.eq_4/gateop_perm;gopA +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3396/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[5]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -96397,7 +96175,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -96413,7 +96191,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[36]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -96429,7 +96207,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[21]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[6]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -96445,14 +96223,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N334_5/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[5]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[7]/opit_0_inv_L5Q_perm;gopL5Q @@ -96471,7 +96255,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -96487,23 +96271,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N17[2]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_542_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N607/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -96620,7 +96398,7 @@ I14;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -96636,7 +96414,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -96652,7 +96430,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_inc_dec_n/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -96668,7 +96446,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[5]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -96684,20 +96462,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N108.eq_4/gateop_perm;gopA +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[6]/opit_0_inv_L5Q_perm;gopL5Q Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[6]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[89]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -96713,17 +96494,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N167.eq_4/gateop_perm;gopA +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[4]/opit_0_inv_L5Q_perm;gopL5Q Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[7]/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q @@ -96743,17 +96527,23 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N247_1_1_or[0]_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[11]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_done/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -96797,7 +96587,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -96845,14 +96635,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N570/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N108.eq_4/gateop_perm;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[0]/opit_0_inv;gopQ @@ -96899,14 +96692,20 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N446_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[146]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/reinit_adj_rdel_d/opit_0_inv;gopQ @@ -96920,7 +96719,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_544/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N247_1_1_or[0]_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -97037,7 +96836,7 @@ I14;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/N14[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N451_and[0][2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -97047,23 +96846,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/s_axi_rdata0[67]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_542_4/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/N14[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3385/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -97073,7 +96866,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3446/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3394/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -97083,7 +96876,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N570/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N621_1_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -97093,7 +96886,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_540_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N247_1_1_or[0]_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -97103,7 +96896,102 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_6/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3390/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N167.eq_4/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N621_1_2/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N570/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3395/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[253]/opit_0_inv_L5Q_perm;gopL5Q +Pin +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3399/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[61]/opit_0_inv_L5Q_perm;gopL5Q +Pin +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_865/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -97129,7 +97017,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[6]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -97172,7 +97060,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[10]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[5]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -97188,7 +97076,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[6]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[9]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -97231,7 +97119,17 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[9]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N247_1_1_or[0]_4/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[10]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -97247,7 +97145,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N637_7/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N614_1_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -97257,7 +97155,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N295_mux2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N252/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -97266,19 +97164,6 @@ L2;1 L3;1 L4;1 -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N167.eq_4/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[1]/opit_0_inv_A2Q21;gopA2Q2 Pin @@ -97565,7 +97450,7 @@ T[3];1 TCLK;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_68/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N136_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -97575,7 +97460,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_80/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N279_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -97585,20 +97470,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N28_1.fsub_6/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -97614,7 +97486,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/wdata_path_adj/N18[3]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[8]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -97630,7 +97512,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[36]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -97656,7 +97538,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[8]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_done_flag/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -97672,7 +97554,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[97]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -97742,16 +97624,6 @@ CLK;1 D;1 RS;1 -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N165/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N213_3/gateop_perm;gopLUT5 Pin @@ -97763,7 +97635,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N228_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/wdata_path_adj/N21[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -97773,7 +97645,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -97789,7 +97661,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N63/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N144_ac2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -97799,7 +97671,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -97815,7 +97687,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -97831,7 +97703,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -97847,20 +97719,24 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[176]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N205_1_5/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N172_86/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q @@ -97947,7 +97823,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -97979,7 +97855,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -98094,7 +97970,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N144_ac2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -98120,7 +97996,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[5]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N118_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -98130,7 +98006,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_5[2]_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N202_47/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -98140,7 +98016,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[51]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -98166,7 +98042,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N327/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_9[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -98198,30 +98074,30 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N118_5/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N34_3/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[129]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_13[3]/gateop;gopMUX4TO1 @@ -98275,7 +98151,7 @@ S10;1 S11;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_14[3]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N118_13/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -98285,23 +98161,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_7[2]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_125/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_fsm[2:0]_36/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -98321,7 +98191,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_cal_error/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -98348,7 +98218,7 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N139/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_9[2]_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -98358,23 +98228,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/dqs_gate_check_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N34_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_6[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N327/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -98444,23 +98308,17 @@ I13;1 I14;1 Inst -u_axi_ddr_top/s_axi_rdata0[14]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[5]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -98487,20 +98345,14 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_5[0]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N328_7/gateop;gopMUX4TO1 @@ -98573,7 +98425,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -98600,7 +98452,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_cal_error/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -98616,7 +98468,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_error/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -98675,17 +98527,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_121/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -98701,7 +98543,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[1]/opit_0_inv_L5Q;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -98717,7 +98559,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_adj_done/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -98733,7 +98575,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N139/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N55/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -98743,17 +98585,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_69/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -98769,7 +98617,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[5]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -98785,7 +98633,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -98801,7 +98649,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[5]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -98817,7 +98665,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -98833,7 +98681,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_5[2]_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N294_1/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N538_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -98925,7 +98783,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N118_24/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N17_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -98935,7 +98793,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -98951,7 +98809,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -99040,7 +98898,7 @@ I4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N279_6/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N63/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -99050,7 +98908,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N758_44_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N1814/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -99060,7 +98918,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N124_8/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N124_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -99070,23 +98928,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N296/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_fsm[4:0]_9/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N228_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -99096,17 +98948,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N124_6/gateop_perm;gopLUT5 +u_axi_ddr_top/wr_sta_reg[3]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gate_check/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[77]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -99122,7 +98980,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N151_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_378/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -99132,17 +98990,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N17[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt[3]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/N113_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N228_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -99152,17 +99016,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N334_5/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/wdata_path_adj/N18[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N173_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -99172,7 +99042,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[33]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -99188,33 +99058,33 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N265_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[79]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[174]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N286_13/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[136]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -99230,7 +99100,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[47]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[200]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -99246,7 +99116,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[6]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -99262,7 +99132,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[203]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -99278,7 +99148,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N386/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N395_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -99288,7 +99158,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N530_7/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N359/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -99298,46 +99168,40 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[108]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N466/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[104]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_1_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N118_5/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_done_flag/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N377/gateop;gopMUX4TO1 @@ -99351,33 +99215,43 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N395_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[109]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/ref_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N334_6/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/dq_rising/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N439/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ck_check_done/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -99393,7 +99267,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[15]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -99409,24 +99283,36 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/wdata_path_adj/N18[3]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[15]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N542_10/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[5]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N475_1/gateop;gopMUX4TO1 @@ -99440,20 +99326,14 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_4/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/opit_0_inv_AQ_perm;gopAQ @@ -99556,26 +99436,7 @@ I14;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[17]/opit_0_inv_AQ_perm;gopAQ -Pin -CEOUT;2 -Cout;2 -Q;2 -RSOUT;2 -Y;2 -CE;1 -CLK;1 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 -RS;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[8]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -99591,17 +99452,24 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_and[1][4]_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt[0]/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +CEOUT;2 +F;2 +Q;2 +RSOUT;2 +CE;1 +CLK;1 +I0;1 +I1;1 +I2;1 +I3;1 +RS;1 +S0;1 +S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -99633,7 +99501,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[40]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -99648,6 +99516,16 @@ L3;1 L4;1 RS;1 +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N228_1/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ddrphy_gatei/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q Pin @@ -99666,34 +99544,52 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/wdata_path_adj/N21[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[203]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/wdata_path_adj/N18[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt[1]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[1]/opit_0_inv_A2Q1;gopA2Q1 @@ -99903,20 +99799,14 @@ I14;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N173_8/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q @@ -99935,7 +99825,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[8]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -99951,7 +99841,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_resp/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[6]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -99967,7 +99857,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -99983,7 +99873,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -100015,7 +99905,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N247_1_1_or[0]_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[2]_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -100025,17 +99915,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N607/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -100051,7 +99947,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -100067,17 +99963,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_382/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[3]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[215]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -100109,7 +100011,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_cke/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -100142,20 +100044,14 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N334_6/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[1]/opit_0_inv_L5Q_perm;gopL5Q @@ -100190,20 +100086,14 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N417[0]_15/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[1]/opit_0_inv_L5Q_perm;gopL5Q @@ -100254,17 +100144,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N813_6/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[79]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -100280,7 +100176,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[163]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -100295,6 +100191,26 @@ L3;1 L4;1 RS;1 +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/N18[2]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N151_2/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs/opit_0_inv;gopQ Pin @@ -100307,7 +100223,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[110]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q;gopL5Q Pin CEOUT;2 Q;2 @@ -100323,7 +100239,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/N18/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/wdata_path_adj/N18[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -100333,7 +100249,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[138]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -100408,7 +100324,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -100472,20 +100388,14 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[0]_5/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO;gopIOMDDRDEL @@ -100952,7 +100862,7 @@ MI;1 T;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N202_41/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N144_ac2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -100962,7 +100872,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N202_53/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_fsm[2:0]_39_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -100972,7 +100882,57 @@ L3;1 L4;1 Inst -u_axi_ddr_top/s_axi_rdata0[10]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N202_75/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N202_40/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N202_64/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N202_83/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N144_ac2/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdel_calibration/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -100988,7 +100948,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[8]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N194_4/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/s_axi_rdata0[40]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -101004,17 +100974,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N202_45/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[110]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N202_57/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_95/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -101024,17 +101000,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N124_6/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N202_49/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N165/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -101044,7 +101026,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N538_5/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_98/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -101054,7 +101036,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_7[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N202_44/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -101064,7 +101046,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_101/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_63/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -101074,17 +101056,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_81/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[8]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N202_34/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N202_68/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -101094,17 +101082,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N118_20/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[137]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N202_46/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N202_65/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -101114,7 +101108,27 @@ L3;1 L4;1 Inst -u_axi_ddr_top/s_axi_rdata0[50]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N202_56/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N202_60/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/s_axi_rdata0[109]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -101130,7 +101144,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N202_37/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N395_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -101140,17 +101154,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N21_2/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[138]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N538_5/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N202_48/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -101160,7 +101180,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_113/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N202_91/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -101170,7 +101190,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_133/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N202_95/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -101180,23 +101200,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/s_axi_rdata0[47]/opit_0_L5Q_perm;gopL5Q -Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N118_13/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N118_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -101206,7 +101210,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N205_1_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -101216,23 +101220,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/s_axi_rdata0[79]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_79/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N22_10[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_71/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -101242,23 +101240,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N202_87/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[208]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -101274,37 +101266,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N118_17/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N12[8]/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N34_3/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N118_9/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N205_1_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -101314,7 +101276,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/s_axi_rdata0[145]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -101330,17 +101292,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N118_13/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N21_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N538_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -101350,7 +101302,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -101366,17 +101318,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N12[2]/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -101408,23 +101350,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N17_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_check_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_adj_done/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -101440,24 +101376,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_fsm[2:0]_39_2/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_9[2]_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_adj_done/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[0]/opit_0_inv;gopQ @@ -102164,7 +102096,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_89/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[1]_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -102305,20 +102237,17 @@ I13;1 I14;1 Inst -u_axi_ddr_top/s_axi_rdata0[39]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N108.eq_4/gateop;gopA Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N167.eq_0/gateop_A2;gopA2 @@ -102361,20 +102290,7 @@ I13;1 I14;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N167.eq_4/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N621_1_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_542_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -102384,7 +102300,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N446_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N247_1_1_or[0]_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -102394,7 +102310,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N384_5/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/wdata_path_adj/N21[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -102404,7 +102320,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/s_axi_rdata0[131]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[78]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -102420,7 +102336,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N564_25/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N118_13/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -102430,7 +102346,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N451_or[0]_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N598_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -102440,14 +102356,20 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[210]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N564_20_3/gateop;gopMUX4TO1 @@ -102483,7 +102405,17 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[5]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_2/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/adj_rdel_done/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -102499,7 +102431,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[108]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[22]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -102515,17 +102447,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N694_inv/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[4]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -102541,7 +102479,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N15_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N694_inv/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -102551,23 +102489,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/s_axi_rdata0[0]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N610/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N621_1_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N386/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -102577,23 +102509,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_sync/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_86/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N637_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_542_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -102603,17 +102529,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N614_1_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[163]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -102629,7 +102561,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3448/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N564_25/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -102766,7 +102698,7 @@ I4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_544/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_540_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -102883,7 +102815,7 @@ I14;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_move_done/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -102916,7 +102848,7 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -102932,7 +102864,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -102948,7 +102880,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N669_42/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -102958,14 +102890,20 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N295_mux2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/adj_rdel_done/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[0]/opit_0_inv;gopQ @@ -103012,7 +102950,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -103028,7 +102966,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N451_and[0][2]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N614_1_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -103145,55 +103083,37 @@ I14;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_542_4/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/init_adj_rdel/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_544/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_comb_r[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N446_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3419/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -103203,7 +103123,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_542_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N645_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -103213,7 +103133,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -103229,7 +103149,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[8]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -103256,7 +103176,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[11]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -103272,14 +103192,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N614_1_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[5]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[6]/opit_0_inv_L5Q_perm;gopL5Q @@ -103298,7 +103224,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[8]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[9]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -103325,7 +103251,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[9]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[10]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -103341,7 +103267,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N607/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -103351,33 +103277,24 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[11]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N570/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N167.eq_4/gateop_perm;gopA +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N16_4/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[1]/opit_0_inv_A2Q21;gopA2Q2 @@ -103665,7 +103582,7 @@ T[3];1 TCLK;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N279_6/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/wdata_path_adj/N18[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -103675,7 +103592,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[228]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata_en[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -103691,7 +103608,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[7]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -103707,7 +103624,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata_en[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -103723,17 +103640,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N17[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/record_data_valid/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N205_1_5/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N213_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -103743,17 +103666,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[12]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/ddrphy_rst_ack_r[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -103769,14 +103698,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_5[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[1]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[1]/opit_0_inv_L5Q_perm;gopL5Q @@ -103811,7 +103746,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -103827,23 +103762,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[240]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N202_52/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[112]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_vld/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -103943,20 +103872,14 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_5[2]_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[0]/opit_0_inv_L5Q_perm;gopL5Q @@ -103975,20 +103898,14 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/N31_0_2_2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[0]/opit_0_inv;gopQ @@ -104090,14 +104007,20 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N328_10/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[2]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[1]/opit_0_inv_L5Q_perm;gopL5Q @@ -104132,7 +104055,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[8]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_9[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -104142,33 +104065,33 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N194_4/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[44]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N24_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_9[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_9[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -104200,30 +104123,30 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_5[2]_1/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/ddr_fifo_full0/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N22_10[2]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_13[3]/gateop;gopMUX4TO1 @@ -104277,7 +104200,7 @@ S10;1 S11;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[9]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_5[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -104287,17 +104210,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_7[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_cal_error/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N327/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N139/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -104307,7 +104236,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_9[2]_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_7[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -104317,14 +104246,20 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_7[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_7[1]/gateop;gopMUX4TO1 @@ -104338,7 +104273,7 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_9[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N306_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -104348,30 +104283,30 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N55/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[149]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[127]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N22_10[2]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N81_1_0/gateop_A2;gopA2 @@ -104434,7 +104369,38 @@ I13;1 I14;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N118_9/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N327/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N301_1/gateop;gopMUX4TO1 +Pin +F;2 +I0;1 +I1;1 +I2;1 +I3;1 +S0;1 +S1;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -104450,7 +104416,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N301_2/gateop;gopMUX4TO1 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N328_10/gateop;gopMUX4TO1 Pin F;2 I0;1 @@ -104461,7 +104427,7 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N265_10/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_fsm[2:0]_36/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -104471,17 +104437,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_5[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[22]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -104497,23 +104469,28 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N538_5/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r/opit_0_inv;gopQ +Pin +CEOUT;2 +Q;2 +RSOUT;2 +CE;1 +CLK;1 +D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_error/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -104529,38 +104506,39 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N24_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r/opit_0_inv;gopQ +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 RSOUT;2 +Z;2 CE;1 CLK;1 -D;1 -RS;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_6[0]/gateop_perm;gopLUT5 -Pin -Z;2 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_error/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -104576,7 +104554,18 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass_d/opit_0_inv;gopQ +Pin +CEOUT;2 +Q;2 +RSOUT;2 +CE;1 +CLK;1 +D;1 +RS;1 + +Inst +u_axi_ddr_top/s_axi_rdata0[214]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -104608,44 +104597,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass_d/opit_0_inv;gopQ -Pin -CEOUT;2 -Q;2 -RSOUT;2 -CE;1 -CLK;1 -D;1 -RS;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N70_1/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_9[2]_2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N20_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N57_12_or[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -104655,7 +104617,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -104671,23 +104633,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_cal_error/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N70_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -104703,31 +104659,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[0]/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 -F;2 Q;2 RSOUT;2 +Z;2 CE;1 CLK;1 -I0;1 -I1;1 -I2;1 -I3;1 -RS;1 -S0;1 -S1;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[4]/gateop_perm;gopLUT5 -Pin -Z;2 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[3]/opit_0_inv_L5Q_perm;gopL5Q @@ -104746,20 +104691,14 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/N7_4/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[5]/opit_0_inv_L5Q_perm;gopL5Q @@ -104778,7 +104717,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_4[1]_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N34_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -104886,7 +104825,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N34_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N57_12_or[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -104896,23 +104835,14 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[5]/opit_0_inv_AQ_perm;gopAQ +u_axi_ddr_top/u_axi_rd_connect/N32_mux8_9/gateop_perm;gopLUT5 Pin -CEOUT;2 -Cout;2 -Q;2 -RSOUT;2 -Y;2 -CE;1 -CLK;1 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 -RS;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[2]/opit_0_inv_A2Q21;gopA2Q2 @@ -104969,43 +104899,68 @@ I14;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[5]/opit_0_inv_AQ;gopAQ Pin CEOUT;2 +Cout;2 Q;2 RSOUT;2 -Z;2 +Y;2 CE;1 CLK;1 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 +RS;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N296/gateop_perm;gopLUT5 +Pin +Z;2 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N124_1/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[143]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_fsm[2:0]_13/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[46]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N279_6/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N63/gateop;gopLUT5 Pin Z;2 L0;1 @@ -105015,7 +104970,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N359/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N173_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -105025,23 +104980,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N124_7/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N228_11/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N173_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -105051,7 +105000,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N57_12_or[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N173_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -105061,7 +105010,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N334_5/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N439/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -105071,7 +105020,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N359/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N124_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -105081,7 +105030,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_1_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N173_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -105091,7 +105040,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[16]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -105107,7 +105056,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[204]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -105123,17 +105072,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N296/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_85/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N265_10/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -105143,7 +105082,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N296/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/wdata_path_adj/N18[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -105153,23 +105092,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N279_8/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_error/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -105185,7 +105118,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N279_8/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N286_9/gateop;gopLUT5 Pin Z;2 L0;1 @@ -105195,27 +105128,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N334_6/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N286_10/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N232_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N386/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -105225,7 +105138,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N417[0]_15/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_350/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -105235,27 +105148,39 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[0]_5/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_done_flag/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N417[0]_15/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N173_8/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N466/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -105265,7 +105190,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_1_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_83/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -105286,7 +105211,7 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N439/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_fsm[4:0]_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -105296,20 +105221,14 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_done_flag/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[2]_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/wdata_path_adj/N18[0]/gateop_perm;gopLUT5 @@ -105322,7 +105241,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[208]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -105338,7 +105257,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -105354,14 +105273,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N228_9/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N475_1/gateop;gopMUX4TO1 @@ -105375,7 +105300,7 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -105491,20 +105416,14 @@ I14;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N228_9/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt[0]/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q @@ -105523,22 +105442,6 @@ RS;1 S0;1 S1;1 -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt[2]/opit_0_inv_L5Q_perm;gopL5Q -Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 - Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt[3]/opit_0_inv_L5Q_perm;gopL5Q Pin @@ -105556,7 +105459,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N124_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_381/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -105566,7 +105469,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt[4]/opit_0_inv_L5Q_perm;gopL5Q +Pin +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[19]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -105599,17 +105518,23 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[1]_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -105625,7 +105550,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en_inv/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/wdata_path_adj/N18[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -105742,22 +105667,19 @@ I14;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/opit_0_inv_AQ_perm;gopAQ +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[17]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 -Cout;2 Q;2 RSOUT;2 -Y;2 +Z;2 CE;1 CLK;1 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 RS;1 Inst @@ -105842,23 +105764,26 @@ I14;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[113]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/opit_0_inv_AQ;gopAQ Pin CEOUT;2 +Cout;2 Q;2 RSOUT;2 -Z;2 +Y;2 CE;1 CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -105874,7 +105799,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N561[5]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N439/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -105884,7 +105809,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[116]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -105900,7 +105825,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[6]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -105916,39 +105841,27 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[5]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/wdata_path_adj/N18[3]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en_inv/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N395_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N334_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -105958,7 +105871,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[6]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -105974,7 +105887,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_resp/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -106006,20 +105919,14 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/wdata_path_adj/N18[3]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[3]/opit_0_inv_L5Q_perm;gopL5Q @@ -106070,20 +105977,14 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_check_done/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N334_5/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_flag/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q @@ -106103,14 +106004,20 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/wdata_path_adj/N21[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[1]/opit_0_inv_L5Q_perm;gopL5Q @@ -106145,14 +106052,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N417[0]_14/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[84]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[1]/opit_0_inv_L5Q_perm;gopL5Q @@ -106203,7 +106116,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[48]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_1_3/gateop;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[23]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -106219,17 +106142,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N151_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[164]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/N21[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_and[1][4]_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -106239,23 +106168,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[236]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_335/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[81]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -106282,7 +106205,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[213]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -106298,36 +106221,24 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[19]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/wdata_path_adj/N18[0]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[82]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N334_5/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_error/opit_0_inv;gopQ @@ -106341,7 +106252,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -106357,7 +106268,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[1]/opit_0_inv_L5Q;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[5]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -106373,7 +106284,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[2]/opit_0_inv_L5Q;gopL5Q Pin CEOUT;2 Q;2 @@ -106405,7 +106316,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -106437,7 +106348,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -106453,7 +106364,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[149]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -106933,17 +106844,23 @@ MI;1 T;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_73/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_9[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_fsm[2:0]_39_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -106963,23 +106880,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/s_axi_rdata0[82]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_75/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_9[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_79/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -106989,7 +106900,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N118_24/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_67/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -106999,7 +106910,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/s_axi_rdata0[111]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/dqs_gate_check_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -107015,53 +106926,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N118_5/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_92/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_91/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/s_axi_rdata0[20]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_83/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[178]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[86]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -107077,7 +106952,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_119/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_111/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -107087,7 +106962,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/s_axi_rdata0[19]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[145]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -107103,7 +106978,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N34_3/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/N32_mux8_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -107113,7 +106988,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_123/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N118_24/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -107123,7 +106998,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N607/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N118_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -107133,7 +107008,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/s_axi_rdata0[16]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[180]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -107149,7 +107024,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[48]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N202_50/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/s_axi_rdata0[52]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -107165,7 +107050,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_138/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N202_58/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -107175,33 +107060,33 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_9[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[55]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[46]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N12[2]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_127/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_115/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -107211,7 +107096,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/ddr_fifo_full0/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[18]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -107227,7 +107112,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_77/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N202_54/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -107237,7 +107122,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_67/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_122/gateop;gopLUT5 Pin Z;2 L0;1 @@ -107247,7 +107132,27 @@ L3;1 L4;1 Inst -u_axi_ddr_top/s_axi_rdata0[44]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/s_axi_rdata0[53]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -107263,17 +107168,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_79/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/dqs_gate_check_pass/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N202_38/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_91/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -107283,7 +107194,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N202_54/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N202_62/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -107293,7 +107204,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_93/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N202_70/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -107303,7 +107214,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_378/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -107313,7 +107224,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/s_axi_rdata0[54]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[49]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -107329,7 +107240,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N21_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_119/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -107339,7 +107250,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -107371,14 +107282,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N18_4/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[83]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q @@ -107397,7 +107314,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_check_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -107413,7 +107330,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_adj_done/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -107429,7 +107346,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[16]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -107445,30 +107362,30 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N17_7/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gate_check/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gate_check/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N57_12_or[1]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[0]/opit_0_inv;gopQ @@ -108175,7 +108092,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/wdata_path_adj/N18[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N607/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -108316,7 +108233,7 @@ I13;1 I14;1 Inst -u_axi_ddr_top/s_axi_rdata0[34]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[248]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -108372,7 +108289,7 @@ I13;1 I14;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3452/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_540_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -108382,7 +108299,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/wdata_path_adj/N18[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N446_0_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -108392,65 +108309,63 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[125]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[102]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N249/gateop;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/adj_rdel_done/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_542_4/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N564_25/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N621_1_2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3447/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -108493,43 +108408,62 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/wdata_path_adj/N18[3]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3458/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N108.eq_4/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N607/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[32]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[120]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -108545,7 +108479,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[38]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -108561,7 +108495,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -108577,17 +108511,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_99/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N55/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N694_inv/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -108597,7 +108537,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N614_1_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3418/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -108607,7 +108547,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/s_axi_rdata0[149]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -108623,106 +108563,80 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N621_1_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[9]/opit_0_inv_AQ_perm;gopAQ Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +CEOUT;2 +Cout;2 +Q;2 +RSOUT;2 +Y;2 +CE;1 +CLK;1 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_move_done/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[2]/opit_0_inv_A2Q21;gopA2Q2 Pin CEOUT;2 -Q;2 +Cout;2 +Q0;2 +Q1;2 RSOUT;2 -Z;2 +Y0;2 +Y1;2 CE;1 CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cin;1 +I0X;1 +I1X;1 +I00;1 +I01;1 +I02;1 +I03;1 +I04;1 +I10;1 +I11;1 +I12;1 +I13;1 +I14;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[9]/opit_0_inv_AQ_perm;gopAQ +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[4]/opit_0_inv_A2Q21;gopA2Q2 Pin CEOUT;2 Cout;2 -Q;2 +Q0;2 +Q1;2 RSOUT;2 -Y;2 +Y0;2 +Y1;2 CE;1 CLK;1 Cin;1 -I0;1 I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +I1X;1 +I00;1 +I01;1 +I02;1 +I03;1 +I04;1 +I10;1 +I11;1 +I12;1 +I13;1 +I14;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[2]/opit_0_inv_A2Q21;gopA2Q2 -Pin -CEOUT;2 -Cout;2 -Q0;2 -Q1;2 -RSOUT;2 -Y0;2 -Y1;2 -CE;1 -CLK;1 -Cin;1 -I0X;1 -I1X;1 -I00;1 -I01;1 -I02;1 -I03;1 -I04;1 -I10;1 -I11;1 -I12;1 -I13;1 -I14;1 -RS;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[4]/opit_0_inv_A2Q21;gopA2Q2 -Pin -CEOUT;2 -Cout;2 -Q0;2 -Q1;2 -RSOUT;2 -Y0;2 -Y1;2 -CE;1 -CLK;1 -Cin;1 -I0X;1 -I1X;1 -I00;1 -I01;1 -I02;1 -I03;1 -I04;1 -I10;1 -I11;1 -I12;1 -I13;1 -I14;1 -RS;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[5]/opit_0_inv_A2Q20;gopA2Q2 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[6]/opit_0_inv_A2Q21;gopA2Q2 Pin CEOUT;2 Cout;2 @@ -108776,36 +108690,24 @@ I14;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N279_6/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gate_check/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_114/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[1]/opit_0_inv_A2Q1;gopA2Q1 @@ -108861,7 +108763,7 @@ I14;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[5]/opit_0_inv_A2Q21;gopA2Q2 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[4]/opit_0_inv_A2Q20;gopA2Q2 Pin CEOUT;2 Cout;2 @@ -108915,7 +108817,7 @@ I14;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_done/opit_0_inv_L5Q;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[112]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -108948,7 +108850,7 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_sync/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -108964,7 +108866,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_sync/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -108980,17 +108882,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_542_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_move_done/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N247_1_1_or[0]_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -109044,7 +108952,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N247_1_1_or[0]_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N451_and[0][2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -109054,7 +108962,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_540_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N417[0]_14/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -109170,16 +109078,6 @@ I13;1 I14;1 RS;1 -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_4/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_544/gateop_perm;gopLUT5 Pin @@ -109191,43 +109089,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_542_4/gateop;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/s_axi_rdata0[37]/opit_0_L5Q_perm;gopL5Q -Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3426/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N610/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N570/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -109237,23 +109099,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[206]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N614_1_4/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[5]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -109269,7 +109125,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[9]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -109285,7 +109141,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[8]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -109312,7 +109168,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[8]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[11]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -109360,7 +109216,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[10]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[9]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -109387,7 +109243,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[11]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[10]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -109403,40 +109259,46 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N249/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_done/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N564_25/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[254]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3420/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[1]/opit_0_inv_A2Q21;gopA2Q2 @@ -109724,7 +109586,7 @@ T[3];1 TCLK;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/wdata_path_adj/N18[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N151_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -109734,23 +109596,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/wdata_path_adj/N21[0]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/wdata_path_adj/N18[3]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/wdata_path_adj/N18[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -109760,7 +109616,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N295_mux2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N279_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -109770,7 +109626,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N173_9/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/wdata_path_adj/N18[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -109780,7 +109636,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[216]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -109796,7 +109652,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N213_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N66_ac1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -109806,23 +109662,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[95]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N213_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[0]_5/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N118_13/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -109832,24 +109682,36 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N271_16/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[4]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[1]_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[2]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/opit_0_inv_L5Q_perm;gopL5Q @@ -109868,7 +109730,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_vld/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -109884,20 +109746,14 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[26]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_75/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q @@ -109968,7 +109824,7 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -110000,17 +109856,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_4[1]_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[1]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r1[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -110141,7 +110003,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -110157,23 +110019,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_4[1]_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[14]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_9[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -110183,26 +110039,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[15]/opit_0_inv_AQ_perm;gopAQ +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N202_72/gateop_perm;gopLUT5 Pin -CEOUT;2 -Cout;2 -Q;2 -RSOUT;2 -Y;2 -CE;1 -CLK;1 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 -RS;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_9[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_9[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -110212,7 +110059,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N301/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_9[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -110244,23 +110091,17 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N301/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_adj_done/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -110327,23 +110168,17 @@ S10;1 S11;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_5[0]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_7[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N241_4_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -110363,7 +110198,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N118_13/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_7[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -110373,14 +110208,20 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N294_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[7]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_7[1]/gateop;gopMUX4TO1 @@ -110394,7 +110235,7 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_adj_done/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -110410,17 +110251,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N22_10[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[98]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[100]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -110496,23 +110343,17 @@ I13;1 I14;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_fsm[2:0]_36/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_9[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N327/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -110533,14 +110374,20 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N57_12_or[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N328_10/gateop;gopMUX4TO1 @@ -110554,7 +110401,7 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gate_check/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -110602,14 +110449,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_fsm[2:0]_36/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r/opit_0_inv;gopQ @@ -110623,7 +110476,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_error/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -110639,7 +110492,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_error/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_fsm[4:0]_64/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -110655,7 +110518,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_7[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N18_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -110665,34 +110528,34 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass_d/opit_0_inv;gopQ Pin CEOUT;2 Q;2 RSOUT;2 -Z;2 CE;1 CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass_d/opit_0_inv;gopQ +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 RSOUT;2 +Z;2 CE;1 CLK;1 -D;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N538_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_7[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -110702,7 +110565,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -110718,14 +110581,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_4[1]_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q @@ -110744,17 +110613,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N118_20/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_6[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N21_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -110764,17 +110623,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_71/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[1]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -110806,14 +110671,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_14[3]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_error/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[5]/opit_0_inv_L5Q_perm;gopL5Q @@ -110832,7 +110703,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -110930,7 +110801,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -110946,17 +110817,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N327/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[2]/opit_0_inv_L5Q;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N570[6]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N306_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -111039,7 +110916,7 @@ I4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N286_10/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[0]_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -111049,20 +110926,14 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[152]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N296/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[2]_3/gateop_perm;gopLUT5 @@ -111075,7 +110946,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[29]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -111091,7 +110962,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[30]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -111107,18 +110978,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N72/gateop;gopMUX4TO1 -Pin -F;2 -I0;1 -I1;1 -I2;1 -I3;1 -S0;1 -S1;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N232_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N136_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -111128,7 +110988,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -111144,7 +111004,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N417[0]_14/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N232_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -111154,7 +111014,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N173_8/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N359/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -111164,7 +111024,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N173_9/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N466/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -111174,7 +111034,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N136_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N286_13/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -111184,7 +111044,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[250]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[238]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -111200,17 +111060,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[1]_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[1]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[177]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -111226,33 +111092,33 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_1_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N22_10[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[1]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/cnt[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -111268,7 +111134,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N286_13/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N286_10/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -111278,53 +111144,65 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[252]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N395_2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N279_7/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[222]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N395_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_sync/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N386/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[72]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -111340,7 +111218,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N475/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N610/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -111361,7 +111239,7 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en_inv/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N446_0_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -111371,7 +111249,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_cal_vld/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -111387,7 +111265,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N296/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N84_ac1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -111397,7 +111275,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -111413,23 +111291,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[121]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N14/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[117]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[203]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -111445,20 +111317,15 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[56]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N475_1/gateop;gopMUX4TO1 Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +F;2 +I0;1 +I1;1 +I2;1 +I3;1 +S0;1 +S1;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/dq_rising/opit_0_inv_L5Q_perm;gopL5Q @@ -111577,30 +111444,31 @@ I14;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[94]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N15_4/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_1_6/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt[0]/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +CEOUT;2 +F;2 +Q;2 +RSOUT;2 +CE;1 +CLK;1 +I0;1 +I1;1 +I2;1 +I3;1 +RS;1 +S0;1 +S1;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt[2]/opit_0_inv_L5Q_perm;gopL5Q @@ -111635,36 +111503,24 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N165/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[61]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[1]_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ddrphy_gatei/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q @@ -111684,7 +111540,7 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -111700,17 +111556,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N124_8/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_done_flag/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[60]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[114]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -111833,14 +111695,23 @@ I14;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N279_6/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/opit_0_inv_AQ_perm;gopAQ Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +CEOUT;2 +Cout;2 +Q;2 +RSOUT;2 +Y;2 +CE;1 +CLK;1 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[2]/opit_0_inv_A2Q21;gopA2Q2 @@ -111924,22 +111795,19 @@ I14;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/opit_0_inv_AQ;gopAQ +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 -Cout;2 Q;2 RSOUT;2 -Y;2 +Z;2 CE;1 CLK;1 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 RS;1 Inst @@ -111959,7 +111827,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[57]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -111975,23 +111843,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[6]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N136_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[5]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -112007,17 +111869,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/wdata_path_adj/N21[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[5]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_resp/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -112033,24 +111901,36 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N14/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N265_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_resp/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[2]/opit_0_inv_L5Q_perm;gopL5Q @@ -112069,7 +111949,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -112085,7 +111965,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -112101,7 +111981,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/reinit_adj_rdel/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -112117,17 +111997,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N136_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[215]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -112160,7 +112046,7 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -112176,33 +112062,33 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_10/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[1]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N564_25/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N286_13/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N417[0]_14/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -112260,7 +112146,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[249]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -112276,24 +112162,36 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N144_ac2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[11]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N286_9/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[80]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs/opit_0_inv;gopQ @@ -112307,7 +112205,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[184]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -112323,7 +112221,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -112339,20 +112237,14 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[185]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_fsm[2:0]_13/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_error/opit_0_inv;gopQ @@ -112366,7 +112258,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[5]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -112382,7 +112274,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -112398,7 +112290,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[5]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -112430,7 +112322,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -112478,7 +112370,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[24]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[240]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -112958,37 +112850,55 @@ MI;1 T;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N202_54/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gate_check/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_fsm[2:0]_35/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[21]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N202_42/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[91]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[153]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[26]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -113004,7 +112914,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N202_38/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N202_52/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -113014,7 +112924,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N118_24/gateop_perm;gopLUT5 +u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -113024,23 +112934,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/dqs_gate_check_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N202_40/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_92/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N118_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -113050,7 +112954,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_123/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_122/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -113060,7 +112964,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_75/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N202_48/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -113070,7 +112974,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_131/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_78/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -113080,7 +112984,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_87/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_110/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -113090,23 +112994,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/s_axi_rdata0[62]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_106/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_98/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_90/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -113116,7 +113014,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_79/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N610/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -113126,7 +113024,27 @@ L3;1 L4;1 Inst -u_axi_ddr_top/s_axi_rdata0[31]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_102/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_98/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/s_axi_rdata0[59]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -113142,27 +113060,39 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_119/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_135/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_134/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -113172,7 +113102,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_111/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N295_mux2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -113182,17 +113112,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_115/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[61]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N24_10/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_126/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -113212,7 +113148,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_103/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_137/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -113222,17 +113158,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_138/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/N25_mux6/gateop_perm;gopLUT5 +u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -113242,27 +113168,39 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_107/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[62]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N24_2/gateop_perm;gopLUT5 +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[93]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[57]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -113278,7 +113216,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N202_50/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N202_56/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -113288,23 +113226,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/s_axi_rdata0[24]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_97/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[124]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[127]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -113320,27 +113252,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N202_34/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_99/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[56]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[152]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -113356,7 +113284,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -113372,7 +113300,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -113388,7 +113316,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -113436,17 +113364,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_127/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_check_pass/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_check_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[169]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -113462,14 +113396,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N21_2/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[117]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[0]/opit_0_inv;gopQ @@ -114176,14 +114116,20 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N301/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rdvalid_r1/opit_0_inv;gopQ @@ -114317,7 +114263,7 @@ I13;1 I14;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[211]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[152]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -114373,39 +114319,27 @@ I13;1 I14;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[144]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N456/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/adj_rdel_done/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N451_and[0][2]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N249/gateop;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -114415,7 +114349,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_865/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3414/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -114425,7 +114359,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -114441,14 +114375,36 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N614_1_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[57]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[50]/opit_0_inv_L5Q_perm;gopL5Q +Pin +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N564_20_3/gateop;gopMUX4TO1 @@ -114494,7 +114450,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_6/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N607/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -114504,17 +114460,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N446_0_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N669_42/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -114524,7 +114486,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[5]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[49]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -114540,23 +114502,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3409/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_5[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3419/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -114566,7 +114522,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_cal_error/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[178]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -114582,33 +114538,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N598_5/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N633_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3454/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3417/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -114618,7 +114558,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -114634,14 +114574,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N694_inv/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_done/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[9]/opit_0_inv_AQ_perm;gopAQ @@ -114771,7 +114717,7 @@ I14;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_540_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3413/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -114781,7 +114727,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_544/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_542_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -114898,7 +114844,7 @@ I14;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_move_done/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -114947,7 +114893,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_move_done/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -114979,20 +114925,14 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N249/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[0]/opit_0_inv;gopQ @@ -115039,7 +114979,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_113_5/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N17[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -115049,7 +114989,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N451_and[0][2]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_540_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -115166,33 +115106,33 @@ I14;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[210]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N295_mux2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N694_inv/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[177]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3457/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_544/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -115202,7 +115142,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[54]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -115218,17 +115158,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N327/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[79]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -115244,7 +115190,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -115260,7 +115206,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3449/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N67_1_sum3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -115270,37 +115216,52 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3385/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[5]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3386/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[125]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N265_10/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N167.eq_4/gateop_perm;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_done/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[48]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -115316,7 +115277,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[224]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[240]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -115332,17 +115293,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/wdata_path_adj/N18[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[253]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -115358,7 +115325,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -115385,7 +115352,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[8]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[11]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -115460,7 +115427,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[11]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[8]/opit_0_inv_L5Q;gopL5Q Pin CEOUT;2 Q;2 @@ -115476,7 +115443,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r1[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -115492,17 +115459,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[58]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[25]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -115803,7 +115776,7 @@ T[3];1 TCLK;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[213]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -115819,33 +115792,33 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N22_10[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[51]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N232_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -115861,7 +115834,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -116798,20 +116771,14 @@ T[3];1 TCLK;1 Inst -u_axi_ddr_top/s_axi_rdata0[235]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/N1_2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[0]/opit_0_inv;gopQ @@ -119630,7 +119597,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -119646,7 +119613,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -119662,7 +119629,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[104]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -119678,7 +119645,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -119694,17 +119661,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3:0]_5/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[10]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_success/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/dqs_rst_training_high_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -119720,7 +119693,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3424/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N118_17/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -119806,20 +119779,14 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/training_error_d[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N118_20/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[0]/opit_0_inv;gopQ @@ -120339,33 +120306,24 @@ D;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N107.lt_2/gateop_perm;gopA +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N33_mux7/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[12]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N172/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N37_1_1/gateop_A2;gopA2 @@ -120488,7 +120446,7 @@ I13;1 I14;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/N28/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_36/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -120498,23 +120456,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[0]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_11/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N253_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -120524,20 +120476,14 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_valid_0/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N267_or[0]_5/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N201/gateop;gopMUX4TO1 @@ -120562,7 +120508,7 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_28/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N267_or[0]_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -120572,7 +120518,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[5]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N267_or[0]_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -120582,7 +120528,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N80/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N35_19/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -120592,33 +120538,33 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N253_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[8]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[7]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N69_0_ac5/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_fsm[2:0]_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -120628,7 +120574,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_28/gateop;gopLUT5 Pin Z;2 L0;1 @@ -120638,7 +120584,27 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[17]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[1]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[0]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[15]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -120654,7 +120620,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_new_valid/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[6]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -120670,7 +120646,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[7]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -120680,7 +120656,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[19]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[16]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -120696,7 +120672,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N282/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[8]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -120706,7 +120682,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N50[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -120716,7 +120692,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_cmd[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[13]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[17]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -120732,7 +120718,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N417_14/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N26_mux3_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -120742,7 +120728,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N50[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N262/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -120752,23 +120738,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[26]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[11]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_new_valid/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -120784,23 +120764,27 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[39]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[3]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N414_3/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -120832,7 +120816,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[6]/opit_0_inv_L5Q_perm;gopL5Q +u_rotate_image/image_blank_valid/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -120848,17 +120832,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_33/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[9]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[7]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/r_init/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -120874,7 +120864,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_id[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[7]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -120890,7 +120880,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[9]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_len[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -120906,7 +120896,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[8]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_write/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -120922,17 +120912,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg_46/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[10]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[1]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_len[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -120980,7 +120976,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N35_20/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[14]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -121245,7 +121241,7 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_id[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_id[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -121261,7 +121257,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_id[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_id[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -121277,7 +121273,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_write/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_id[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -121293,17 +121289,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N10/gateop_perm;gopLUT5 +u_axi_ddr_top/rd_ddr_idle/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_len[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[13]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -121336,7 +121338,7 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N35_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -121413,30 +121415,30 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N33_mux5_5/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[14]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_id[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N254/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/N8_4/gateop;gopMUX4TO1 @@ -121472,72 +121474,7 @@ S0;1 S1;1 Inst -u_axi_ddr_top/N792_4/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[0]/opit_0_inv_L5Q_perm;gopL5Q -Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_rempty/opit_0_inv_AQ_perm;gopAQ -Pin -CEOUT;2 -Cout;2 -Q;2 -RSOUT;2 -Y;2 -CE;1 -CLK;1 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 -RS;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/ND1[1]_4/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N35_19/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N417_27/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N317/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -121563,7 +121500,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -121579,7 +121516,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -121595,7 +121532,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[7]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[5]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -121611,7 +121548,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[5]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[6]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -121627,7 +121564,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[6]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[7]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -121643,7 +121580,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N172/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N20/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -121653,7 +121590,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/ND1[1]_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N80/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -121663,7 +121600,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_req/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_cmd_ready/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -121711,7 +121648,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -121727,7 +121664,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[9]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[5]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -121743,20 +121680,14 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N33_mux5_5/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[6]/opit_0_inv_L5Q_perm;gopL5Q @@ -121775,7 +121706,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[7]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[8]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -121791,7 +121722,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[8]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[9]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -121807,14 +121738,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N33_mux7/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[12]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[10]/opit_0_inv_L5Q_perm;gopL5Q @@ -121849,7 +121786,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[5]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_req/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -121865,20 +121802,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N109.lt_2/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_cmd_ready/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[7]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -121894,7 +121818,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[14]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_valid_0/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -121910,7 +121834,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[15]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[8]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -121926,7 +121850,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[27]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[19]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -121942,17 +121866,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/N473_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[18]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[18]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[22]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -121968,17 +121898,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N62/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[21]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[20]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[25]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -121994,17 +121930,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/N182_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[20]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[21]/opit_0_inv_L5Q;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[27]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -122052,23 +121994,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[25]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[4]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[26]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -122084,7 +122020,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[7]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[12]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_wfull/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -122100,7 +122046,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N317/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -122110,7 +122056,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.raddr_msb/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_tworw/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -122126,7 +122072,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N258_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N410/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -122209,30 +122155,30 @@ I3;1 I4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[9]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N35_20/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N491_0/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N371/gateop;gopMUX4TO1 @@ -122246,23 +122192,7 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[0]/opit_0_inv_L5Q_perm;gopL5Q -Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N417_23/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N417_14/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -122272,17 +122202,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N416/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N458_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N418/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -122292,7 +122228,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N414_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N417_23/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -122302,27 +122238,39 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N458/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[3]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N414_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[39]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[8]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -122338,7 +122286,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/ND1[2]_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[9:0]_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -122348,27 +122296,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N57/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N54[2]/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[8]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -122378,20 +122306,14 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/cnt[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N26_mux3_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/cnt[3]/opit_0_inv_L6Q_perm;gopL6Q @@ -122433,7 +122355,7 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N418/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N39_mux3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -122475,7 +122397,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -122485,7 +122407,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[6]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -122517,7 +122439,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[6]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[7]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -122533,7 +122455,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N54[3]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N458_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -122543,7 +122465,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[8]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[9]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -122559,23 +122481,27 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[9]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[0]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[6]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/N1/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N50[6]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -122826,32 +122752,35 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[12]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[4]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_rempty/opit_0_inv_AQ_perm;gopAQ +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.waddr_msb/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 -Cout;2 Q;2 RSOUT;2 -Y;2 +Z;2 CE;1 CLK;1 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 RS;1 Inst @@ -122899,7 +122828,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_done/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -123223,7 +123152,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/rw_diff/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_done/opit_0_inv_L5Q;gopL5Q Pin CEOUT;2 Q;2 @@ -123239,7 +123168,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.raddr_msb/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -123255,23 +123184,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[9]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -123303,7 +123226,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N281/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg_2_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -123313,7 +123236,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N270/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N57/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -123323,30 +123246,40 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[5]/opit_0_inv;gopQ +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 RSOUT;2 +Z;2 CE;1 CLK;1 -D;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N491_0/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[5]/opit_0_inv;gopQ +Pin +CEOUT;2 +Q;2 +RSOUT;2 +CE;1 +CLK;1 +D;1 RS;1 Inst @@ -123361,17 +123294,25 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/N50_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N136_1_or[0]_1_9_muxf6_perm;gopLUT6 Pin +Y0;2 +Y1;2 Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +A0;1 +A1;1 +A2;1 +A3;1 +A4;1 +B0;1 +B1;1 +B2;1 +B3;1 +B4;1 +M;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[4].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -123398,7 +123339,7 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N244_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/N148_1_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -123408,14 +123349,20 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/N14_mux2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N216/gateop_perm;gopLUT5 @@ -123428,7 +123375,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N252/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N248/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -123438,7 +123385,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N224_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N220_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -123448,23 +123395,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N224_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N47/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/N59_mux4_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -123474,7 +123415,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N276_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/N1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -123484,7 +123425,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N232_8/gateop_perm;gopLUT5 +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N24_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -123494,17 +123435,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/N31_0_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N244/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1205/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -123514,17 +123461,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1169/gateop_perm;gopLUT5 +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N0/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N5[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -123534,7 +123487,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[38]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_l[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -123550,7 +123503,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N248/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N8_mux3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -123560,7 +123513,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N208/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N244_4_cpy/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -123570,7 +123523,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/cmd_accepted_m_8/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/cmd_accepted_m_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -123602,7 +123555,7 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N71_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_62/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -123612,7 +123565,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N589[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N91_0_2_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -123622,7 +123575,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N8_mux3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N598[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -123632,7 +123585,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N607[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/N55_mux6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -123642,7 +123595,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/N35[2]_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N616[3]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -123682,59 +123635,59 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N652[7]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N55_mux6/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/N31_0_2_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[0].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/N55_mux6/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/N91_0_2_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/N55_mux6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -123744,23 +123697,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/N117_mux7_7/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/N69_mux6/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/N55_mux6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -123770,23 +123717,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/N55_mux6_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/N91_0_2_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/N25_mux6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -123858,17 +123799,23 @@ S10;1 S11;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/N106_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[15]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/N50_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/N25_mux6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -123878,7 +123825,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/N50_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1202/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -123888,23 +123835,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/N25_mux6/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/N55_mux6_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N534[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -123914,7 +123855,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/N50_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1206/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -123924,7 +123865,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/N50_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/N25_mux6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -123934,23 +123875,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/N25_mux6/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/N31_0_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/N50_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -123960,7 +123895,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N55_mux6_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N91_9[4]_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -123980,7 +123915,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/N50_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N61_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -123990,23 +123925,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N99_2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N91_0_2_3/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -124016,17 +123945,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N99_2/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/N59_mux2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/N91_9[0]_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -124036,20 +123971,14 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/N117_mux7_6/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q @@ -124068,7 +123997,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -124084,7 +124013,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -124100,7 +124029,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -124132,7 +124061,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -124148,7 +124077,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -124180,7 +124109,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N61_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N589[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -124206,20 +124135,14 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N59_mux2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm;gopL5Q @@ -124238,7 +124161,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -124254,7 +124177,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/N55_mux6/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/N91_9[4]_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -124264,7 +124187,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/N69_mux6/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/N91_0_2_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -124294,17 +124217,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/N91_0_2_3/gateop_perm;gopLUT5 +u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[19]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -124320,7 +124249,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/N25_mux6/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N50_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -124330,17 +124259,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_0_10/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -124356,7 +124291,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -124388,7 +124323,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -124404,7 +124339,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -124420,7 +124355,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -124468,23 +124403,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N525[1]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -124500,7 +124429,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -124516,23 +124445,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/N55_mux6/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -124548,7 +124471,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[0].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[3].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -124584,7 +124507,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/N99_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/N69_mux6_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -124604,23 +124527,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/N99_2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/N25_mux5/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N607[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -124630,7 +124547,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -124662,7 +124579,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -124678,7 +124595,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -124710,7 +124627,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -124726,7 +124643,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -124742,7 +124659,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -124758,7 +124675,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -124774,7 +124691,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -124790,7 +124707,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -124806,7 +124723,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -124822,7 +124739,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -124838,7 +124755,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/N25_mux5/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1203/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -124848,7 +124765,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/N25_mux5/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/N69_mux6_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -124858,14 +124775,20 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/N59_mux2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/N61_3/gateop_perm;gopLUT5 @@ -124888,23 +124811,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/N99_2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/N99_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/N91_0_2_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -124914,7 +124831,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -124930,7 +124847,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -124946,7 +124863,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -124962,7 +124879,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -124994,23 +124911,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/N59_mux2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q;gopL5Q Pin CEOUT;2 Q;2 @@ -125026,7 +124937,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -125042,7 +124953,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[1].mcdq_tfaw/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -125058,7 +124969,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -125074,7 +124985,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -125106,7 +125017,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -125122,27 +125033,39 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1202/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N616[3]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/N59_mux2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/N61_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -125152,20 +125075,14 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/N69_mux6/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/N99_2/gateop_perm;gopLUT5 @@ -125178,17 +125095,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/N61_3/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -125214,17 +125121,36 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/N25_mux5/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N158.eq_4/gateop_perm;gopA Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm;gopL5Q +Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/N69_mux6/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/N59_mux2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -125234,7 +125160,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[2].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -125250,7 +125176,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -125266,7 +125192,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -125282,7 +125208,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -125298,7 +125224,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -125314,7 +125240,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -125330,7 +125256,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -125362,23 +125288,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N552[4]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -125394,17 +125314,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/N55_mux6/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -125420,25 +125330,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N136_1_or[0]_1_9_muxf6_perm;gopLUT6 -Pin -Y0;2 -Y1;2 -Z;2 -A0;1 -A1;1 -A2;1 -A3;1 -A4;1 -B0;1 -B1;1 -B2;1 -B3;1 -B4;1 -M;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/N50_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/N55_mux6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -125448,7 +125340,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1203/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/N59_mux2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -125458,7 +125350,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/N91_0_2_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/N69_mux6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -125468,7 +125360,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/N61_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/N91_0_2_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -125478,7 +125370,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N50_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/N61_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -125488,7 +125380,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/fifo3_data_full/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -125504,7 +125396,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -125520,7 +125412,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/N50_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/N99_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -125530,7 +125422,27 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/N31_0_2_2/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -125546,14 +125458,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1204/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm;gopL5Q @@ -125572,7 +125490,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[6].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -125588,7 +125506,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -125604,7 +125522,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -125636,7 +125554,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -125652,7 +125570,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -125668,7 +125586,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -125684,23 +125602,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[1]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -125716,7 +125628,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/N99_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N561[5]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -125726,7 +125638,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/N50_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/N25_mux5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -125746,17 +125658,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/N61_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/N99_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/N61_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -125766,7 +125684,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/N91_0_2_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/N99_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -125776,7 +125694,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N534[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/N59_mux2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -125786,7 +125704,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/N69_mux6_1/gateop_perm;gopLUT5 +u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -125796,7 +125714,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm;gopL5Q +u_rotate_image/data_out_valid2/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -125828,7 +125746,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -125844,17 +125762,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1206/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -125870,7 +125794,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -125886,7 +125810,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -125902,7 +125826,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -125918,7 +125842,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[3].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -125934,20 +125858,14 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N570[6]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm;gopL5Q @@ -125966,7 +125884,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -125982,33 +125900,33 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/N50_4/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1205/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/N55_mux6_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/N31_0_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -126018,7 +125936,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/N59_mux2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/N69_mux6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -126028,23 +125946,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/N99_2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/N69_mux6/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/N55_mux6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -126054,7 +125966,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/N55_mux6/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/N25_mux6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -126064,27 +125976,39 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/N99_2/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[16]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/N7/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -126100,7 +126024,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/N25_mux5/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/N473_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -126110,14 +126034,20 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/N91_9[4]_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm;gopL5Q @@ -126136,17 +126066,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1199/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -126162,7 +126098,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -126194,23 +126130,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/N91_0_2_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -126226,17 +126156,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/N59_mux2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -126252,7 +126188,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -126268,14 +126204,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N652[7]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[0].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q @@ -126326,7 +126268,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[6].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -126390,7 +126332,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -126406,7 +126348,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[2].trc_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[2].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -126422,7 +126364,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[2].trc_timing/timing_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[2].trc_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -126438,7 +126380,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[2].trc_timing/timing_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -126454,23 +126396,25 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N136_1_or[0]_1_8_muxf6_perm;gopLUT6 Pin -CEOUT;2 -Q;2 -RSOUT;2 +Y0;2 +Y1;2 Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +A0;1 +A1;1 +A2;1 +A3;1 +A4;1 +B0;1 +B1;1 +B2;1 +B3;1 +B4;1 +M;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[3].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[7].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -126486,7 +126430,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[3].trc_timing/timing_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[3].trc_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -126502,7 +126446,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[3].trc_timing/timing_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -126518,20 +126462,14 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/N50_4/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[4].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q @@ -126582,17 +126520,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/N25_mux5/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[5].trc_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[5].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -126608,7 +126552,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[5].trc_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[5].trc_timing/timing_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -126624,7 +126568,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[5].trc_timing/timing_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[6].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -126640,17 +126584,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[1].mcdq_tfaw/N12_mux4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[6].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -126698,7 +126648,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[1].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -126762,7 +126712,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -126788,20 +126738,14 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/N50_4/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q @@ -126819,22 +126763,6 @@ L3;1 L4;1 RS;1 -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[2].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q -Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 - Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q Pin @@ -126852,7 +126780,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -126884,7 +126812,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -126910,7 +126838,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -126926,20 +126854,14 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/N59_mux2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q @@ -126958,7 +126880,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -126990,20 +126912,14 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/N25_mux5/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/N31_0_2_2/gateop_perm;gopLUT5 @@ -127016,7 +126932,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[3].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -127032,23 +126948,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/N50_4/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[3].trc_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -127096,23 +127006,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/N25_mux5/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N29/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/N31_0_2_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -127122,7 +127026,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N5[1]/gateop_perm;gopLUT5 +u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -127132,7 +127036,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -127164,7 +127068,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -127180,17 +127084,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N598[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N525[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/N469_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -127200,17 +127110,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/N31_0_2_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/N43_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/N25_mux5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -127220,25 +127136,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N136_1_or[0]_1_8_muxf6_perm;gopLUT6 -Pin -Y0;2 -Y1;2 -Z;2 -A0;1 -A1;1 -A2;1 -A3;1 -A4;1 -B0;1 -B1;1 -B2;1 -B3;1 -B4;1 -M;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -127254,7 +127152,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -127270,7 +127168,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -127286,43 +127184,49 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/N55_mux6/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/N31_0_2_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[5].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[4].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/N31_0_2_2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1200/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/N25_mux5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -127332,17 +127236,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1201/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -127357,6 +127267,16 @@ L3;1 L4;1 RS;1 +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/N31_0_2_2/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q Pin @@ -127374,7 +127294,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N552[4]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/N50_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -127394,7 +127314,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/N59_mux2/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/N471_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -127404,20 +127324,14 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/N25_mux5/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q @@ -127468,7 +127382,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -127494,17 +127408,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/N31_0_2_2/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/axi_data_valid0/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -127520,7 +127440,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -127536,20 +127456,14 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/N91_9[4]_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q @@ -127568,7 +127482,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[7].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -127594,23 +127508,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/N31_0_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -127626,7 +127534,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -127642,7 +127550,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -127674,7 +127582,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -127690,33 +127598,33 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/N25_mux6/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/N25_mux6/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/N31_0_2_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/N31_0_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -127726,27 +127634,39 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/N31_0_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/N25_mux6/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -127762,7 +127682,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -127778,7 +127698,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -127794,7 +127714,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -127826,7 +127746,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.raddr_msb/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -127842,7 +127762,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/N31_0_2_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/N25_mux6_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -127852,17 +127772,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/N25_mux6/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/N25_mux6_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/N50/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -127872,7 +127798,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -127888,7 +127814,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -127904,7 +127830,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -127920,7 +127846,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -127936,7 +127862,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/cmd_act_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -127952,20 +127878,14 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1199/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/N31_0_2_2/gateop_perm;gopLUT5 @@ -127978,7 +127898,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N232_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/N31_0_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -127988,7 +127908,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -128004,7 +127924,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N240_6/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/N31_0_2_2/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/N50_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -128030,7 +127960,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -128062,7 +127992,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -128078,7 +128008,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/N59_mux2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/N31_0_2_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -128088,7 +128018,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/N25_mux6_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N579[7]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -128098,7 +128028,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N232_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/N91_9[4]_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -128108,7 +128038,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/N91_9[4]_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1204/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -128118,7 +128048,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -128134,7 +128064,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -128150,20 +128080,14 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/N59_mux2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q @@ -128182,7 +128106,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -128198,17 +128122,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/N25_mux6/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/N31_0_2_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/N31_0_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -128218,7 +128132,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/N31_0_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[9]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -128228,7 +128142,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/N25_mux6/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -128254,7 +128168,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -128302,7 +128216,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -128318,7 +128232,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/N25_mux6/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[8]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -128328,20 +128242,14 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[12]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/N31_0_2_2/gateop_perm;gopLUT5 @@ -128354,23 +128262,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[11]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -128386,7 +128288,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -128402,17 +128304,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/N25_mux6_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -128428,7 +128336,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_wfull/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -128444,23 +128352,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N13_mux3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/N31_0_2_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/N31_0_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -128470,17 +128372,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/N31_0_3/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[19]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/cmd_act_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[18]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -128496,7 +128404,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -128528,7 +128436,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -128576,14 +128484,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/N27_mux6/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[17]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[1]/opit_0_inv;gopQ @@ -129068,23 +128982,17 @@ S10;1 S11;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[9]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/cmd_accepted_m_8/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/cmd_accepted_m_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_47_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -129105,7 +129013,7 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -129121,14 +129029,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N197/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_cmd_accepted_m/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/N106/gateop_perm;gopLUT5 @@ -129151,17 +129065,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/N27_mux2/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/N55_mux6/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/N52_mux5_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -129188,7 +129092,7 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_cmd_accepted_l/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -129221,7 +129125,7 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -129237,7 +129141,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -129253,7 +129157,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -129269,7 +129173,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -129285,23 +129189,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_cmd_accepted_m/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/N14_mux2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_l[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -129317,20 +129215,14 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[0]/opit_0_inv;gopQ @@ -129729,7 +129621,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -129745,7 +129637,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[5]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -129761,7 +129653,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[40]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -129777,7 +129669,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[18]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[38]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -129793,7 +129685,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[15]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[14]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -129809,7 +129701,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[11]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[20]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -129825,7 +129717,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[20]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -129841,23 +129733,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[14]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N54[0]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[16]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[10]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -129873,7 +129759,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[12]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[24]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -129889,7 +129775,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[19]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[13]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -129905,7 +129791,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[13]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[19]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -129921,7 +129807,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[35]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[30]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -129937,7 +129823,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[27]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[18]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -129953,7 +129839,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[30]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[16]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -129969,7 +129855,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[33]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[17]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -129985,23 +129871,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[25]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N210/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[27]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -130033,7 +129913,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[21]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[23]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -130065,7 +129945,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[19]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[26]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -130081,7 +129961,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[36]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[29]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -130097,7 +129977,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[29]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[25]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -130113,7 +129993,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[26]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[12]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -130129,17 +130009,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N531_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[15]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[29]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[14]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -130155,7 +130041,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[9]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[30]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -130171,7 +130057,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[31]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[6]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -130187,7 +130073,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[15]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -130219,7 +130105,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[6]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[35]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -130235,7 +130121,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[34]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -130251,23 +130137,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_m[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N149_5/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_l[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[36]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -130283,7 +130163,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[8]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[31]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -130299,7 +130179,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[42]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[39]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -130315,7 +130195,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[40]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -130331,7 +130211,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[41]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_valid/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -130347,7 +130227,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_valid/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[42]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -130363,7 +130243,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N10/gateop_perm;gopLUT5 +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N106_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -130373,7 +130253,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N220_8/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N208/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -130383,7 +130263,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/N12_mux4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/N12_mux4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -130393,23 +130273,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[1].mcdq_tfaw/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/N19_5/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/N19_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N516[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -130419,24 +130293,36 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/N12_mux4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N543[3]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[1].mcdq_tfaw/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q @@ -130487,7 +130373,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N124_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/N43_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -130507,7 +130393,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -130587,7 +130473,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[2]_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/N35[2]_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -130597,30 +130483,27 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[13]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[1]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N13_mux6_2/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N8.lt_2/gateop_perm;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/cnt_pass/opit_0_inv_L5Q_perm;gopL5Q @@ -130687,7 +130570,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[15:0]_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/N19_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -130713,7 +130596,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N173_8/gateop_perm;gopLUT5 +u_ddr_addr_ctr/u_rd3_addr_ctr/N34_mux3_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -130723,23 +130606,20 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N15.lt_2/gateop_perm;gopA Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_8_sum3_6/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_0_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -130749,7 +130629,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/N19_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N45_mux6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -130809,27 +130689,7 @@ I13;1 I14;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_47_1/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_0_8/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -130845,33 +130705,36 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[39]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/N1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_50[3]_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[7]/opit_0_inv_AQ_perm;gopAQ Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +CEOUT;2 +Cout;2 +Q;2 +RSOUT;2 +Y;2 +CE;1 +CLK;1 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N45_mux6/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_51/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -130903,7 +130766,7 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N244_4_cpy/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_50[3]_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -130913,7 +130776,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/N25_mux5/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_4[1]_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -130923,30 +130786,50 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_54/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N244/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_63/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_0_10/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q @@ -130981,23 +130864,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/N27_mux6/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N7_mux6_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N225_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -131056,7 +130933,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N221/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_8_sum3_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -131066,7 +130943,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/N59_mux4_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/N27_mux2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -131076,7 +130953,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/rd3_data_en0/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -131092,36 +130969,34 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[32]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N7_mux6_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N276_3/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N220_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt0[1]/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q @@ -131141,7 +131016,7 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt0[2]/opit_0_inv_L5Q;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -131157,7 +131032,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -131173,30 +131048,39 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_rempty/opit_0_inv_AQ_perm;gopAQ Pin CEOUT;2 +Cout;2 Q;2 RSOUT;2 -Z;2 +Y;2 CE;1 CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm;gopL5Q @@ -131215,7 +131099,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.raddr_msb/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -131231,7 +131115,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/rd_poll/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -131279,7 +131163,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N119/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N221/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -131289,7 +131173,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N13_mux3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N15/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -131299,14 +131183,20 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N22/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N27_mux6/gateop_perm;gopLUT5 @@ -131319,7 +131209,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N27_mux3_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N35_mux4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -131329,7 +131219,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N35_mux4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N50_12_maj1_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -131339,20 +131229,14 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N29/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N50_10[3]/gateop_perm;gopLUT5 @@ -131365,7 +131249,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N15/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N50_15[3]_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -131391,17 +131275,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N50_12_maj1_1/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -131417,7 +131291,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -131433,7 +131307,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N220_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N13_mux6_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -131443,23 +131317,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[2]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -131475,7 +131343,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[5]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -131491,7 +131359,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[6]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[5]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -131507,7 +131375,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[6]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -131523,7 +131391,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N50_15[0]_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N27_mux3_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -131533,7 +131401,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N212/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -131543,17 +131411,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/N98/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/N27_mux6_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/N106_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -131563,14 +131437,20 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N210/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/cmd_wr_pass/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q @@ -131606,17 +131486,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/N50/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.waddr_msb/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -131632,23 +131518,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/N31_0_2_2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/N1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N50[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -132396,7 +132276,7 @@ WD;1 WE;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/N1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -132416,7 +132296,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N26_mux3_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -132426,17 +132306,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N42/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/rw_diff/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -132446,7 +132332,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -132456,17 +132342,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[4]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[5]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[24]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -132502,7 +132394,7 @@ I13;1 I14;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.waddr_msb/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.raddr_msb/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -132578,7 +132470,7 @@ I13;1 I14;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[4]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -132668,19 +132560,22 @@ I13;1 I14;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_wfull/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_rempty/opit_0_inv_AQ_perm;gopAQ Pin CEOUT;2 +Cout;2 Q;2 RSOUT;2 -Z;2 +Y;2 CE;1 CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 RS;1 Inst @@ -132774,17 +132669,23 @@ S0;1 S1;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[4]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_wfull/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.waddr_msb/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[8]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -132800,20 +132701,14 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[7]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[2]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21;gopA2Q2 @@ -133637,7 +133532,7 @@ WD;1 WE;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -133647,23 +133542,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.raddr_msb/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[2]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N4_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -133673,14 +133562,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N26_mux3_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_rempty/opit_0_inv_AQ_perm;gopAQ Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +CEOUT;2 +Cout;2 +Q;2 +RSOUT;2 +Y;2 +CE;1 +CLK;1 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[1]/gateop_perm;gopLUT5 @@ -133693,7 +133591,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N126/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -133703,7 +133601,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[2]/gateop;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N4_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -133713,7 +133611,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/rd3_data_en0/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -133749,14 +133647,20 @@ I13;1 I14;1 Inst -u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N24_1.fsub_1/gateop_A2;gopA2 @@ -133819,20 +133723,17 @@ I13;1 I14;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/poll/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N19.lt_2/gateop_perm;gopA Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N30.fsub_1/gateop_A2;gopA2 @@ -133915,22 +133816,19 @@ I13;1 I14;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_rempty/opit_0_inv_AQ_perm;gopAQ +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[9]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 -Cout;2 Q;2 RSOUT;2 -Y;2 +Z;2 CE;1 CLK;1 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 RS;1 Inst @@ -134024,34 +133922,52 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[4]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.waddr_msb/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[4]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[3]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21;gopA2Q2 @@ -134127,7 +134043,7 @@ I4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/N1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N25_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -134137,20 +134053,14 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N30_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[2]/opit_0_inv_L5Q_perm;gopL5Q @@ -134169,33 +134079,33 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N10_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[41]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[5]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N10_2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[10]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N42/gateop;gopLUT5 Pin Z;2 L0;1 @@ -134205,20 +134115,14 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[26]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N119/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N46_1_1/gateop_A2;gopA2 @@ -134281,7 +134185,7 @@ I13;1 I14;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N50[6]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N458/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -134291,7 +134195,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N54[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N50[1]/gateop;gopLUT5 Pin Z;2 L0;1 @@ -134301,7 +134205,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N50[2]/gateop;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N54[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -134311,7 +134215,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N50[3]/gateop;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N54[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -134321,7 +134225,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N50[5]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N54[3]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -134331,17 +134235,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N54[4]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[9]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N54[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N54[6]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -134351,39 +134261,27 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[22]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N126/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[62]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N54[2]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N274/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N54[5]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -134393,7 +134291,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N54[6]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N50[5]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -134403,17 +134301,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N54[5]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[9]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/wr_sta_reg[0]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[7]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -134429,43 +134333,49 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[9]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[5]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[13]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[3]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/ctrl_back_rdy/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N193/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[20]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_b_valid/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -134481,23 +134391,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[17]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N197/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_b_valid/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -134530,14 +134434,20 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N30_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/poll/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[1]/opit_0_inv;gopQ @@ -135442,7 +135352,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/rd_poll/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -135458,7 +135368,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[10]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -135485,7 +135395,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[39]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -135501,7 +135411,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[34]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -135517,7 +135427,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[38]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[40]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -135533,7 +135443,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[18]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[33]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -135549,7 +135459,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[21]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[21]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -135565,7 +135475,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[25]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[7]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -135581,7 +135491,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[19]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -135597,7 +135507,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[10]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[15]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -135613,7 +135523,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[12]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[10]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -135629,7 +135539,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[14]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[11]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -135645,7 +135555,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[7]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[13]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -135661,7 +135571,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[13]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[22]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -135677,7 +135587,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[16]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -135709,7 +135619,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[30]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[16]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -135725,7 +135635,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[5]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[17]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -135741,7 +135651,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[26]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_cmd[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -135757,7 +135667,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[20]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -135773,7 +135683,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[31]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[23]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -135789,7 +135699,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[42]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[21]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -135805,7 +135715,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[28]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[32]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -135821,7 +135731,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[33]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[24]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -135837,7 +135747,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[24]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[26]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -135853,7 +135763,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[36]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[25]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -135869,7 +135779,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[29]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[12]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -135885,7 +135795,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[7]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[29]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -135901,7 +135811,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[22]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[28]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -135917,7 +135827,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[6]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[30]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -135933,7 +135843,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[32]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[5]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -135949,7 +135859,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[31]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[18]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -135965,23 +135875,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[40]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N524_7/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -135997,7 +135901,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[34]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[38]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136029,7 +135933,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[9]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[36]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136045,23 +135949,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[23]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N2070_2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[39]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_valid/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136093,23 +135991,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N85[0]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[42]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136125,7 +136017,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_valid/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[5]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136141,7 +136033,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N193/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N10/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -136151,7 +136043,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[5]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N526_2/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136167,17 +136069,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N1792_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_l[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N232_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N545_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -136187,7 +136095,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[9]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136203,7 +136111,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[10]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136219,7 +136127,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[6]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[13]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136235,7 +136143,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[17]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[12]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136251,7 +136159,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[9]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[6]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136267,7 +136175,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[11]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136283,7 +136191,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[10]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[7]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136299,7 +136207,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[5]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136315,7 +136223,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_l[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136331,7 +136239,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[194]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136347,7 +136255,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[33]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136363,7 +136271,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[8]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136379,7 +136287,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[14]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136395,7 +136303,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[13]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[14]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136411,7 +136319,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[9]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136427,7 +136335,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[24]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136443,7 +136351,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[12]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136459,7 +136367,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[6]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[12]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136475,7 +136383,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[15]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[34]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136491,7 +136399,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[11]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[6]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136507,7 +136415,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[8]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[15:0]_3/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[21]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136523,7 +136441,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_l[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136539,7 +136457,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[17]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[15:0]_1161/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[10]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136555,7 +136483,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_l[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136571,7 +136499,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_m[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_l[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136587,17 +136515,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/N100_6/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_m[2]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_l[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_m[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136613,17 +136547,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N530_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_l[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_m[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136639,7 +136579,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136655,7 +136595,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N1025_1_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N544_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -136665,7 +136605,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[34]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[6]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136681,7 +136621,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136697,7 +136637,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[6]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mc3q_wdp_dcp/r_wvld[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136713,7 +136653,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_wvld_l/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/N100_6/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[7]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136729,7 +136679,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_wvld_l/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136745,27 +136695,39 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N2193_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[3]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N2048_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[2]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[7]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136781,17 +136743,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/N148_1_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[6]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[6]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_wvld_m/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136807,7 +136775,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[7]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136823,17 +136791,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N544_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_l[1]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136849,7 +136823,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_m[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136865,7 +136839,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[7]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_m[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136881,17 +136855,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/N238_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_m[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_l[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136907,7 +136887,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_m[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136939,7 +136919,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_m[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136955,7 +136935,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_m[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_m[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136971,7 +136951,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_ba[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -136987,7 +136967,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rvld/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_m[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -137003,7 +136983,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rvld/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -137019,23 +136999,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N291_17/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/N171_7/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N244_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -137045,7 +137019,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N285/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/N171_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -137055,55 +137029,27 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_wvld_m/opit_0_inv_L5Q_perm;gopL5Q -Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_l[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N532_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N531_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N549_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N2051/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -137113,39 +137059,27 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_cs_n[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N1792_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N2053/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N2070_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N1796/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -137155,7 +137089,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N2051/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N547_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -137165,7 +137099,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N2053/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N749/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -137175,7 +137109,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_ras_n[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -137191,17 +137125,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N545_1/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N1025_1_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N549_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -137211,7 +137135,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/N93_mux8_5/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N771_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -137221,7 +137145,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[40]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_we_n[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -137237,47 +137161,39 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N2207_1/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/N129/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N771_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[10]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N749/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[1]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N543_6/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N761_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -137287,17 +137203,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N761_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_bank[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N547_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N2207_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -137307,17 +137229,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N1286_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_odt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_ras_n[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[17]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -137333,17 +137261,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N544_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_cas_n[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N307_10/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -137353,7 +137287,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[22]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_ras_n[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -137369,23 +137303,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_bank[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N543_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N1796/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N2193_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -137395,7 +137323,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_m[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -137421,17 +137349,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N532_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[2]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N149_5/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N530_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -137441,7 +137375,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N754/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/N238_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -137451,23 +137385,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_cs_n[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N754/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -137483,7 +137411,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[13]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -137499,7 +137427,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[12]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -137515,7 +137443,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[7]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[9]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -137531,7 +137459,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[5]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[6]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -137547,7 +137475,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[6]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[7]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -137563,7 +137491,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[11]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -137595,7 +137523,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N526_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N307_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -137605,7 +137533,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[11]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[31]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -137621,39 +137549,27 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_cas_n[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N543_2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[12]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[15:0]_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[13]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -137685,7 +137601,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[11]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -137701,7 +137617,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[16]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[19]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -137717,7 +137633,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[18]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[23]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -137733,7 +137649,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[7]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[18]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -137749,7 +137665,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[24]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[26]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -137781,7 +137697,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[21]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[24]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -137797,7 +137713,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[23]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[22]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -137813,7 +137729,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[26]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[8]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -137829,7 +137745,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[5]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -137845,7 +137761,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[6]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -137878,7 +137794,7 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N543_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N1025_1_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -137920,7 +137836,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[7]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_ba[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -137968,23 +137884,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[10]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N12[0]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_ras_n[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_cs_n[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -138000,7 +137910,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_we_n[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_cs_n[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -138016,7 +137926,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_we_n[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_odt_reg[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -138032,7 +137942,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_odt_reg[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_we_n[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -138048,7 +137958,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_odt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_odt[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -138081,7 +137991,7 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -138097,7 +138007,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_cas_n[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[10]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -138113,30 +138023,30 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/N167_5/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cas_n_d[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[0]/opit_0_inv;gopQ @@ -138557,23 +138467,17 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_odt[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N297_mux4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/N543_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -138661,7 +138565,7 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/N1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -138670,25 +138574,6 @@ L2;1 L3;1 L4;1 -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[7]/opit_0_inv_AQ_perm;gopAQ -Pin -CEOUT;2 -Cout;2 -Q;2 -RSOUT;2 -Y;2 -CE;1 -CLK;1 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 -RS;1 - Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.raddr_msb/opit_0_inv_L5Q_perm;gopL5Q Pin @@ -138705,6 +138590,19 @@ L3;1 L4;1 RS;1 +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N16.eq_2/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_0/ram32x1dp;gopRAM16X1D Pin @@ -138777,6 +138675,16 @@ WCLK;1 WD;1 WE;1 +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[1]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[2]/gateop_perm;gopLUT5 Pin @@ -138798,7 +138706,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -138808,7 +138716,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N16.eq_2/gateop_perm;gopA +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[5]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N36.eq_2/gateop_perm;gopA Pin Cout;2 Y;2 @@ -138821,23 +138739,7 @@ I3;1 I4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[10]/opit_0_inv_L5Q_perm;gopL5Q -Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N277_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -138847,7 +138749,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[3]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -138857,7 +138759,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_wfull/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -138873,39 +138775,47 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_txpr_pass/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[7]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/fifo_vld/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N16.eq_0/gateop_A2;gopA2 +Pin +Cout;2 +Y0;2 +Y1;2 +Cin;1 +I0X;1 +I1X;1 +I00;1 +I01;1 +I02;1 +I03;1 +I04;1 +I10;1 +I11;1 +I12;1 +I13;1 +I14;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N136_7/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N16.eq_0/gateop_A2;gopA2 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N36.eq_0/gateop_A2;gopA2 Pin Cout;2 Y0;2 @@ -138925,7 +138835,7 @@ I13;1 I14;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[5]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[5]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -138935,11 +138845,27 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N36.eq_0/gateop_A2;gopA2 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N271_13/gateop_perm;gopLUT5 Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[1]/opit_0_inv_A2Q21;gopA2Q2 +Pin +CEOUT;2 Cout;2 +Q0;2 +Q1;2 +RSOUT;2 Y0;2 Y1;2 +CE;1 +CLK;1 Cin;1 I0X;1 I1X;1 @@ -138953,22 +138879,75 @@ I11;1 I12;1 I13;1 I14;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N36.eq_2/gateop;gopA +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[3]/opit_0_inv_A2Q21;gopA2Q2 Pin +CEOUT;2 Cout;2 -Y;2 +Q0;2 +Q1;2 +RSOUT;2 +Y0;2 +Y1;2 +CE;1 +CLK;1 Cin;1 -I0;1 I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +I1X;1 +I00;1 +I01;1 +I02;1 +I03;1 +I04;1 +I10;1 +I11;1 +I12;1 +I13;1 +I14;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_wfull/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[5]/opit_0_inv_A2Q21;gopA2Q2 +Pin +CEOUT;2 +Cout;2 +Q0;2 +Q1;2 +RSOUT;2 +Y0;2 +Y1;2 +CE;1 +CLK;1 +Cin;1 +I0X;1 +I1X;1 +I00;1 +I01;1 +I02;1 +I03;1 +I04;1 +I10;1 +I11;1 +I12;1 +I13;1 +I14;1 +RS;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_rempty/opit_0_inv;gopQ +Pin +CEOUT;2 +Q;2 +RSOUT;2 +CE;1 +CLK;1 +D;1 +RS;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.waddr_msb/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -138984,119 +138963,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[1]/opit_0_inv_A2Q21;gopA2Q2 -Pin -CEOUT;2 -Cout;2 -Q0;2 -Q1;2 -RSOUT;2 -Y0;2 -Y1;2 -CE;1 -CLK;1 -Cin;1 -I0X;1 -I1X;1 -I00;1 -I01;1 -I02;1 -I03;1 -I04;1 -I10;1 -I11;1 -I12;1 -I13;1 -I14;1 -RS;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[3]/opit_0_inv_A2Q21;gopA2Q2 -Pin -CEOUT;2 -Cout;2 -Q0;2 -Q1;2 -RSOUT;2 -Y0;2 -Y1;2 -CE;1 -CLK;1 -Cin;1 -I0X;1 -I1X;1 -I00;1 -I01;1 -I02;1 -I03;1 -I04;1 -I10;1 -I11;1 -I12;1 -I13;1 -I14;1 -RS;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[5]/opit_0_inv_A2Q21;gopA2Q2 -Pin -CEOUT;2 -Cout;2 -Q0;2 -Q1;2 -RSOUT;2 -Y0;2 -Y1;2 -CE;1 -CLK;1 -Cin;1 -I0X;1 -I1X;1 -I00;1 -I01;1 -I02;1 -I03;1 -I04;1 -I10;1 -I11;1 -I12;1 -I13;1 -I14;1 -RS;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_rempty/opit_0_inv;gopQ -Pin -CEOUT;2 -Q;2 -RSOUT;2 -CE;1 -CLK;1 -D;1 -RS;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[3]/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[5]/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21;gopA2Q2 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[0]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21;gopA2Q2 Pin CEOUT;2 Cout;2 @@ -139221,33 +139098,33 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N10/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[37]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/s_axi_arid[3]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_24/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N63/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N228/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -139268,7 +139145,7 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N228/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N54_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -139278,7 +139155,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_27/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N266/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -139288,7 +139165,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_32/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N278/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -139418,7 +139295,7 @@ I13;1 I14;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_id[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -139444,7 +139321,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/N147/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N282/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -139454,7 +139331,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N266/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[10]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -139464,23 +139341,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[0]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N270/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N278/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N274/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -139490,23 +139361,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[10]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N69_0_ac5/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_36/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N10/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -139516,14 +139381,20 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/ND1[1]_1/gateop_perm;gopLUT5 +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/column_addr_end_1_2/gateop_A2;gopA2 @@ -139586,20 +139457,14 @@ I13;1 I14;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_len[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_13/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N14/gateop_perm;gopLUT5 @@ -139612,17 +139477,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/N261_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_12/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_len[3:0]_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -139632,7 +139503,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/N256_5/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_16/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -139642,7 +139513,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/next_len[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -139658,27 +139529,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_len[3:0]_4/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_19/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[13]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/rd1_cnt_num[0]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[15]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -139694,23 +139561,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[11]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/N866_2_or[4]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_28/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_20/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -139720,7 +139581,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[15]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[19]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -139736,7 +139597,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_24/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_22/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -139746,7 +139607,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/N244/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_25/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -139756,23 +139617,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/s_axi_araddr[18]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_27/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N12[4]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[37:0]_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -139782,33 +139637,33 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[16]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_29/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_29/gateop_perm;gopLUT5 +u_axi_ddr_top/N412_mux15_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -139818,7 +139673,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[10]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/rd_sta_reg[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -139834,17 +139689,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_34/gateop_perm;gopLUT5 +u_axi_ddr_top/rd1_ddr_done0/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N85[9]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -139854,23 +139715,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_32/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N35_2/gateop_perm;gopLUT5 +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N85[6]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -139880,33 +139735,33 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N12[5]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[31]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/record_araddr_valid/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/N147/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[6]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_araddr[24]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -139922,7 +139777,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/rptr/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[9]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -139938,7 +139793,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[5]/opit_0_inv_L5Q;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[23]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -139970,7 +139825,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_data_in_valid_0/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -139980,7 +139835,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[13]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[8]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -140012,7 +139867,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_araddr[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -140028,17 +139883,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/N400_mux15_5/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[5]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[27]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[12]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -140054,7 +139915,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[20]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[13]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -140070,7 +139931,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[16]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[14]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -140086,43 +139947,49 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[18]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_34/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N84_ac1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[16]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/N412_mux15_8/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[25]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[19]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[30]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -140154,7 +140021,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[29]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[20]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -140170,17 +140037,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_21/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_araddr[13]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[23]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[32]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -140212,7 +140085,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[31]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[27]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -140228,7 +140101,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[28]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[26]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -140244,7 +140117,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[35]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[34]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -140260,7 +140133,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[32]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[29]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -140276,7 +140149,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[30]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[28]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -140292,7 +140165,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_28/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/s_axi_araddr[17]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -140308,7 +140191,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[34]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[31]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -140324,14 +140207,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N69_0_ac4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[35]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[33]/opit_0_inv_L5Q_perm;gopL5Q @@ -140350,7 +140239,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_21/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -140360,7 +140249,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[8]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_araddr[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -140376,14 +140265,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[12]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[37]/opit_0_inv;gopQ @@ -140397,7 +140292,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[7]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[6]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -140413,7 +140308,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[5]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[23]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -140429,7 +140324,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_valid_0/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[7]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -140445,17 +140340,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[9]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[9]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[8]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -140471,7 +140372,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[13]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[10]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -140487,7 +140388,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[37]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[11]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -140503,23 +140404,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_len[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[14]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_arid[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -140535,7 +140430,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[27]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[15]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -140551,7 +140446,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[20]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[14]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -140567,7 +140462,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[16]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -140583,7 +140478,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[18]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[17]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -140599,7 +140494,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[17]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[21]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -140615,14 +140510,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_17/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[30]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[19]/opit_0_inv_L5Q_perm;gopL5Q @@ -140641,7 +140542,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[25]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[20]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -140657,7 +140558,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[29]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[33]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -140673,7 +140574,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[23]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[22]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -140689,7 +140590,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[30]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[26]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -140705,7 +140606,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[26]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[27]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -140721,7 +140622,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[31]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[25]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -140737,30 +140638,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_13/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[29]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N24.eq_4/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[28]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[24]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -140776,7 +140670,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[33]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[28]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -140792,23 +140686,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[8]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[2]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[32]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[34]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -140824,23 +140712,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[35]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_17/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[34]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[32]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -140856,7 +140738,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[12]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[35]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -140872,7 +140754,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[12]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_araddr[9]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -140888,7 +140770,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_26/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -140898,17 +140780,33 @@ L3;1 L4;1 Inst -u_axi_ddr_top/N412_mux15_7/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[18]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N19_3/gateop_perm;gopLUT5 +u_axi_ddr_top/N440/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/N589/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -141016,20 +140914,14 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/double_wr/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N63/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][0]/opit_0_inv;gopQ @@ -142352,7 +142244,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[13]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -142368,7 +142260,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[5]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -142384,23 +142276,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N24_6/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[6]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_len[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -142432,14 +142318,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[14]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[6]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[7]/opit_0_inv_L5Q_perm;gopL5Q @@ -142458,7 +142350,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_araddr[19]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[5]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -142743,46 +142635,33 @@ I14;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[4]/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/wptr/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[27]/opit_0_inv_AQ;gopAQ Pin CEOUT;2 +Cout;2 Q;2 RSOUT;2 -Z;2 +Y;2 CE;1 CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[5]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N24_4/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_id[1]/opit_0_inv_L5Q_perm;gopL5Q @@ -142801,17 +142680,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[3]/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_id[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_id[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -142827,23 +142696,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_write/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/N296_8/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[14]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_write/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -142859,7 +142722,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_len[1]/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_len[0]/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q Pin CEOUT;2 F;2 @@ -142876,7 +142739,7 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_len[2]/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_len[1]/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q Pin CEOUT;2 F;2 @@ -142893,7 +142756,7 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_id[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/double_wr/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -142908,6 +142771,16 @@ L3;1 L4;1 RS;1 +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N10/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_len[3]/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q Pin @@ -142926,7 +142799,7 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[6]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -142942,23 +142815,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/fifo0_data_full/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/N867/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N14/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -142968,23 +142835,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[5]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N262/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N62/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -142994,7 +142855,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/ND1[1]_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N69_0_ac4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -143004,36 +142865,34 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/r_init/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N281/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_tworw/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N35_18/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N335_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[0]/opit_0_inv;gopQ @@ -143443,14 +143302,20 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N35_18/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[40]/opit_0_inv_MUX8TO1Q;gopMUX8TO1Q @@ -144412,17 +144277,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[1]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N416/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -144432,7 +144303,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -144464,20 +144335,14 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mc3q_wdp_dcp/r_wvld[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[0]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_0/ram16x1d;gopRAM16X1D @@ -144516,7 +144381,7 @@ WD;1 WE;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/N55_mux6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -144526,7 +144391,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N225_6/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -144536,7 +144401,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/N6/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -144546,7 +144411,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N240_5/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/N25_mux6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -144566,7 +144431,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[4]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -144576,7 +144441,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_wfull/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -144592,14 +144457,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/N7_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N36.eq_0/gateop_A2;gopA2 @@ -144705,23 +144576,17 @@ I4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.waddr_msb/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[1]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/N25_mux6_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -144731,7 +144596,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -144825,17 +144690,23 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/ctrl_back_rdy/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[193]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[194]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -144851,7 +144722,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[197]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[192]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -144867,7 +144738,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[130]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[195]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -144883,7 +144754,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[65]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[131]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -144899,7 +144770,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[66]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[197]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -144915,7 +144786,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[135]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[132]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -144931,23 +144802,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[70]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N12[2]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[67]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[130]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -144963,7 +144828,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[204]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[202]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -144979,7 +144844,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[203]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[204]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -144995,7 +144860,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[76]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[74]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -145011,7 +144876,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[77]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[207]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -145027,7 +144892,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[72]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[137]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -145043,7 +144908,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[75]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[141]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -145059,7 +144924,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[78]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[75]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -145075,7 +144940,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[79]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[139]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -145091,7 +144956,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[84]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[211]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -145123,23 +144988,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[212]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3386/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[213]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[144]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -145155,7 +145014,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[145]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[82]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -145171,7 +145030,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[83]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[20]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -145203,7 +145062,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[210]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[85]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -145235,7 +145094,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[218]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[93]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -145251,7 +145110,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[222]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[221]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -145283,7 +145142,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[155]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[223]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -145315,7 +145174,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[92]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[156]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -145331,7 +145190,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[89]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[155]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -145347,7 +145206,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[160]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[226]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -145363,7 +145222,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[229]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[103]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -145379,7 +145238,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[96]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[98]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -145395,7 +145254,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[97]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[102]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -145427,7 +145286,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[161]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[160]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -145491,7 +145350,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[235]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[169]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -145523,7 +145382,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[237]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[171]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -145539,7 +145398,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[238]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[172]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -145555,7 +145414,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[173]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wdin_en_dly[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -145571,7 +145430,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[172]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[175]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -145587,7 +145446,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[109]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[107]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -145603,7 +145462,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[241]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[179]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -145619,7 +145478,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[247]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[242]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -145635,7 +145494,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[244]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[243]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -145651,7 +145510,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[245]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[176]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -145667,7 +145526,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[246]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[245]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -145683,7 +145542,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[179]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[246]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -145715,7 +145574,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[181]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[250]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -145731,7 +145590,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[120]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[252]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -145747,7 +145606,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[254]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[249]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -145763,7 +145622,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[122]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[117]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -145779,7 +145638,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[253]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[255]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -145795,7 +145654,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[186]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[184]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -145811,7 +145670,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[187]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[254]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -145827,7 +145686,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[255]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[187]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -147289,7 +147148,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata_en[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[104]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -147316,7 +147175,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[24]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -147332,7 +147191,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N17[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[0]_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -148046,7 +147905,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[71]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[65]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148062,7 +147921,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[131]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[198]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148078,7 +147937,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[194]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[68]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148110,7 +147969,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[192]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[194]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148126,7 +147985,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[196]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[70]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148142,7 +148001,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[134]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[71]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148158,7 +148017,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[99]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[67]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148174,7 +148033,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[140]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[76]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148190,7 +148049,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[136]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[77]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148222,7 +148081,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[142]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[203]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148238,7 +148097,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[137]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[200]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148254,7 +148113,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[201]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[143]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148270,7 +148129,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[206]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[142]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148286,7 +148145,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[143]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[207]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148302,7 +148161,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[208]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[83]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148318,7 +148177,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[82]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[145]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148334,7 +148193,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[215]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[148]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148350,7 +148209,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[149]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[208]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148366,7 +148225,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[148]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[87]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148382,7 +148241,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[87]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[151]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148414,7 +148273,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[149]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[212]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148446,7 +148305,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[216]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[91]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148462,7 +148321,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[91]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[92]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148478,7 +148337,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[218]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[152]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148494,7 +148353,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[93]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[220]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148510,23 +148369,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[158]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N50[2]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[152]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_en/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148542,7 +148395,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[153]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148558,7 +148411,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[98]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[224]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148574,7 +148427,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[163]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[99]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148590,7 +148443,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[162]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[226]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148622,7 +148475,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[164]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[162]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148638,7 +148491,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[102]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[227]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148654,7 +148507,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[230]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[165]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148670,7 +148523,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[227]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[161]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148686,7 +148539,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[168]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[173]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148702,7 +148555,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[107]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[111]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148734,7 +148587,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[233]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[108]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148750,7 +148603,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[105]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[235]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148766,7 +148619,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[237]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[110]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148782,7 +148635,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[111]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[237]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148798,7 +148651,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[175]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[233]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148814,7 +148667,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[116]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[114]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148830,7 +148683,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[242]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[115]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148846,7 +148699,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[115]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[118]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148862,7 +148715,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[118]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[241]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148878,7 +148731,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[240]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[183]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148894,7 +148747,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[243]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[188]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148926,7 +148779,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[124]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148942,7 +148795,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[125]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148958,7 +148811,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[190]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[123]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -148974,7 +148827,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[188]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[186]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149006,7 +148859,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[184]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[118]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149022,7 +148875,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[253]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[126]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149038,7 +148891,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[249]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[189]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149054,7 +148907,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[191]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[248]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149086,7 +148939,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[133]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[134]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149102,7 +148955,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N382_1/gateop_perm;gopLUT5 +u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N3[11]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -149112,7 +148965,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[193]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[199]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149128,7 +148981,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[64]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[133]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149144,7 +148997,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[7]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[230]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149160,7 +149013,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[198]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N25.eq_4/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[196]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149176,17 +149042,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[15:0]_3/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[141]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[72]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149202,7 +149058,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[139]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[140]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149218,7 +149074,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[202]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[201]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149234,7 +149090,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[205]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[14]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149250,17 +149106,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N610/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[206]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[200]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[201]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149276,23 +149138,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[203]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_91/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[207]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[11]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149324,7 +149180,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[146]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[209]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149340,7 +149196,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[22]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[149]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149356,7 +149212,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[151]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[148]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149372,7 +149228,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[212]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[210]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149388,20 +149244,14 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[84]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N446_0_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[214]/opit_0_inv_L5Q_perm;gopL5Q @@ -149420,7 +149270,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[208]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[213]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149436,7 +149286,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[153]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[34]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149452,7 +149302,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[223]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[222]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149484,7 +149334,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[156]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N258_3/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[158]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149500,7 +149360,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[221]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[216]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149532,7 +149392,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[220]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[219]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149548,17 +149408,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/N48/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[225]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[224]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[231]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149574,7 +149440,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[165]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[228]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149590,7 +149456,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[64]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[33]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149606,7 +149472,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[225]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[234]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149622,7 +149488,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[228]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[230]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149638,7 +149504,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[226]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[167]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149654,7 +149520,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[167]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[227]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149670,7 +149536,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[224]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_address[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149686,7 +149552,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[169]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[236]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149702,7 +149568,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[232]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[234]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149718,7 +149584,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[234]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[174]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149734,7 +149600,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[173]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[239]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149750,7 +149616,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[236]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[43]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149766,17 +149632,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N313_mux16_21/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[232]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[110]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[235]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149792,23 +149664,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[238]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_542_2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[177]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[178]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149824,7 +149690,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[241]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[28]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149840,7 +149706,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[182]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[181]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149856,7 +149722,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[183]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[122]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149872,7 +149738,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[243]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[182]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149888,7 +149754,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[59]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[30]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149904,7 +149770,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[242]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[244]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149920,17 +149786,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[11]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[115]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[248]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[191]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149946,27 +149818,39 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N286_9/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[250]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N271_5/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[190]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[189]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[113]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149982,7 +149866,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[250]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[249]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -149998,7 +149882,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[126]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[251]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -150014,7 +149898,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[255]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N247_1_1_or[0]_3/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[193]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -150030,7 +149924,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[254]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[197]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -150062,7 +149956,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[196]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[68]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -150078,7 +149972,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[197]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -150094,23 +149988,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[199]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[2]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[69]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[199]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -150126,7 +150014,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[66]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -150142,7 +150030,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[199]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[202]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -150158,14 +150046,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N532_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[205]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[205]/opit_0_inv_L5Q_perm;gopL5Q @@ -150184,7 +150078,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[207]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[206]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -150200,7 +150094,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[204]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[73]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -150216,20 +150110,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N108.eq_4/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N538/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N286_10/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -150239,52 +150120,27 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[201]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N249/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N108.eq_4/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[0]_5/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[209]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[211]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -150300,23 +150156,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N295_mux2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[211]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[214]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -150332,7 +150182,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[213]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[209]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -150348,7 +150198,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[215]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[215]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -150364,7 +150214,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[214]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/init_adj_rdel/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -150380,7 +150230,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[50]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_done/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -150396,7 +150246,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N564_25/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -150406,7 +150256,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[219]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[218]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -150422,7 +150272,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/N61_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N50[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -150432,7 +150282,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[217]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[222]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -150447,16 +150297,6 @@ L3;1 L4;1 RS;1 -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N579[7]/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[221]/opit_0_inv_L5Q_perm;gopL5Q Pin @@ -150474,7 +150314,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[88]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[216]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -150490,27 +150330,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N59_mux2/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N516[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N19.lt_2/gateop_perm;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[226]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[223]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -150526,7 +150359,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[32]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[219]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -150542,7 +150375,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[224]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_pwron_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -150574,7 +150407,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[32]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[228]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -150590,7 +150423,27 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[231]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[15:0]_418_3/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N265_11/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[224]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -150606,7 +150459,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[103]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[225]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -150622,17 +150475,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[15:0]_1278/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[224]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[239]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[105]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -150648,7 +150507,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[235]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[239]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -150664,7 +150523,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[236]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[232]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -150680,17 +150539,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N194_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[105]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[232]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[109]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -150706,7 +150571,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[239]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[238]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -150722,7 +150587,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[43]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[41]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -150738,7 +150603,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[41]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -150754,7 +150619,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[244]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[242]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -150770,7 +150635,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[245]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[243]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -150802,17 +150667,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N386/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[244]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[176]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[245]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -150828,14 +150699,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N466/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[240]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[247]/opit_0_inv_L5Q_perm;gopL5Q @@ -150854,7 +150731,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[62]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[112]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -150870,7 +150747,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[252]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[51]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -150902,17 +150779,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N271_9/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[252]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[248]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[255]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -150928,7 +150811,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[92]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[94]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -150944,7 +150827,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[124]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[254]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -150960,17 +150843,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[10]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[121]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[120]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[177]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -150997,7 +150886,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_cas_n/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[237]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -151370,14 +151259,20 @@ RST;1 RSTODIV;1 Inst -u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/axi_fifo_full0/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/N104.lt_0/gateop_A2;gopA2 @@ -151433,23 +151328,17 @@ I3;1 I4;1 Inst -u_axi_ddr_top/record_data_valid/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N373_1_or[0][2]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[4]/opit_0_L5Q_perm;gopL5Q +u_rotate_image/rd_ddr_addr_valid1/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -151465,23 +151354,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/cnt_wr_num[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N297_mux4/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/wr_sta_fsm[3:0]_3/gateop_perm;gopLUT5 +u_axi_ddr_top/N792_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -151491,17 +151374,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_16/gateop_perm;gopLUT5 +u_axi_ddr_top/rd_importance/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -151517,7 +151406,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[3]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/fifo1_data_full/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -151533,7 +151422,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N24_2/gateop_perm;gopLUT5 +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -151543,7 +151432,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N18/gateop_perm;gopLUT5 +u_axi_ddr_top/N878/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -151553,7 +151442,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/N412_mux15_10/gateop_perm;gopLUT5 +u_axi_ddr_top/N866_2_or[13]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -151563,17 +151452,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/N867/gateop_perm;gopLUT5 +u_axi_ddr_top/record_addr_valid/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/N866_2_or[5]/gateop_perm;gopLUT5 +u_axi_ddr_top/N866_2_or[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -151583,7 +151478,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/N866_2_or[13]/gateop_perm;gopLUT5 +u_axi_ddr_top/N412_mux15_12/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -151593,23 +151488,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/rd0_ddr_done0/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/N866_2_or[7]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/N448_6/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N18/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -151619,7 +151508,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/N132/gateop_perm;gopLUT5 +u_axi_ddr_top/N855_inv/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -151639,7 +151528,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/N928_8/gateop_perm;gopLUT5 +u_axi_ddr_top/N928_10/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -151649,7 +151538,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/delay_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/delay_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -151665,7 +151554,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/rd1_ddr_done0/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/rptr/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -151681,20 +151570,14 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[0]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/N866_2_and[26][0]_1/gateop_perm;gopLUT5 @@ -151707,7 +151590,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/N866_2_or[7]/gateop_perm;gopLUT5 +u_axi_ddr_top/N866_2_and[28][0]_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -151717,7 +151600,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/N866_2_and[27][0]_1/gateop_perm;gopLUT5 +u_axi_ddr_top/rd0_done_cnt[2:0]_e/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -151727,7 +151610,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/N866_2_and[28][0]_1/gateop_perm;gopLUT5 +u_axi_ddr_top/N866_2_or[5]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -151737,7 +151620,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/N866_2_and[30][0]_1/gateop_perm;gopLUT5 +u_axi_ddr_top/N866_2_and[31][0]_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -151747,7 +151630,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/N866_2_and[35][0]_1/gateop_perm;gopLUT5 +u_axi_ddr_top/N866_2_and[32][0]_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -151757,14 +151640,20 @@ L3;1 L4;1 Inst -u_axi_ddr_top/N866_2_and[31][0]_1/gateop_perm;gopLUT5 +u_axi_ddr_top/rd0_done_cnt[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/N866_2_and[33][0]_1/gateop_perm;gopLUT5 @@ -151777,7 +151666,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/N866_2_and[29][0]_1/gateop_perm;gopLUT5 +u_axi_ddr_top/N866_2_or[10]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -151787,7 +151676,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/N866_2_or[11]/gateop_perm;gopLUT5 +u_axi_ddr_top/N866_2_and[36][0]_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -151797,23 +151686,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/rd1_done_cnt[0]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/N866_2_and[35][0]_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/N866_2_and[36][0]_1/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/N574_9[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -151823,17 +151706,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/N866_2_and[37][0]_1/gateop_perm;gopLUT5 +u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[8]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/N866_2_and[34][0]_1/gateop_perm;gopLUT5 +u_axi_ddr_top/N866_2_or[15]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -151843,39 +151732,27 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/ptr/opit_0_inv_L5Q_perm;gopL5Q +u_ddr_addr_ctr/u_rd0_addr_ctr/N20_8/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/delay_cnt1[0]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/N866_2_or[2]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/rd0_done_cnt[2:0]_e/gateop_perm;gopLUT5 +u_axi_ddr_top/N866_2_or[3]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -151885,23 +151762,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/rd0_done_cnt[0]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/N866_2_or[14]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/N882/gateop_perm;gopLUT5 +u_axi_ddr_top/N866_2_or[6]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -151911,7 +151782,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/N871/gateop_perm;gopLUT5 +u_axi_ddr_top/N866_2_or[8]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -151921,17 +151792,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/N866_2_or[8]/gateop_perm;gopLUT5 +u_axi_ddr_top/rd0_cnt_num[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/rd0_addr_start_fall/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/rd1_cnt_num[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -151957,7 +151834,7 @@ L3;1 L4;1 Inst -u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[8]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/rd0_ddr_done0/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -151973,7 +151850,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/N866_2_or[14]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/N249_13/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -151983,55 +151860,37 @@ L3;1 L4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N4.lt_2/gateop_perm;gopA +u_axi_ddr_top/N866_2_or[12]/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst -u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[27]/opit_0_AQ_perm;gopAQ +u_axi_ddr_top/N871/gateop_perm;gopLUT5 Pin -CEOUT;2 -Cout;2 -Q;2 -RSOUT;2 -Y;2 -CE;1 -CLK;1 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 -RS;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst -u_axi_ddr_top/rd_sta_reg[4]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/N866_2_and[37][0]_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/N866_2_or[15]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/N574_3_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -152041,20 +151900,14 @@ L3;1 L4;1 Inst -u_axi_ddr_top/record_addr_valid/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/N889/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/N866_6_0/gateop_A2;gopA2 @@ -152277,7 +152130,7 @@ I13;1 I14;1 Inst -u_axi_ddr_top/N889/gateop_perm;gopLUT5 +u_axi_ddr_top/N863_0_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -152287,7 +152140,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/N866_2_or[10]/gateop_perm;gopLUT5 +u_axi_ddr_top/N882/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -152297,7 +152150,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N12[9]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/N574_9[6]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -152307,23 +152160,17 @@ L3;1 L4;1 Inst -u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_done_rise/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/N264_13/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/N863_0_4/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/N264_14/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -152343,7 +152190,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[0]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/rd0_time_permit/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -152359,49 +152206,43 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[0]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/N866_2_and[29][0]_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_rotate_image/rd_sta_reg[2]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/N928_8/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/N928_10/gateop_perm;gopLUT5 +u_axi_ddr_top/rd1_time_permit/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/rd1_time_permit/opit_0_L5Q_perm;gopL5Q +u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_done_rise/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -152559,7 +152400,7 @@ I14;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/N264_8/gateop_perm;gopLUT5 +u_axi_ddr_top/N866_2_and[27][0]_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -152695,7 +152536,7 @@ I14;1 RS;1 Inst -u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N12[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/N866_2_and[24][0]_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -152737,7 +152578,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.waddr_msb/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N53_4_or[2]_3/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/delay_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -152753,7 +152604,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/delay_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/delay_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -152769,7 +152620,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/delay_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/delay_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -152785,20 +152636,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N161.lt_2/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -u_axi_ddr_top/delay_cnt[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/delay_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -152814,7 +152652,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N188_40/gateop_perm;gopLUT5 +u_axi_ddr_top/N296_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -152824,14 +152662,20 @@ L3;1 L4;1 Inst -u_axi_ddr_top/N866_2_or[6]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/rx3_addr_valid/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/rd0_addr_start_valid0/opit_0;gopQ @@ -152856,7 +152700,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/N400_mux15_6/gateop_perm;gopLUT5 +u_axi_ddr_top/N866_2_or[11]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -153074,23 +152918,17 @@ I4;1 RS;1 Inst -u_axi_ddr_top/rx_rd0_addr_valid/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/N400_mux15_6/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_done1/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/rx_rd0_addr_valid/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -153798,7 +153636,7 @@ L4;1 RS;1 Inst -u_ddr_addr_ctr/u_rd0_addr_ctr/N152_inv/gateop_perm;gopLUT5 +u_axi_ddr_top/N866_2_and[30][0]_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -153808,7 +153646,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/N866_2_or[12]/gateop_perm;gopLUT5 +u_axi_ddr_top/N866_2_and[38][1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -153818,7 +153656,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/N733_8/gateop_perm;gopLUT5 +u_axi_ddr_top/N412_mux15_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -153828,20 +153666,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/rd1_addr_start_fall/opit_0_L5Q;gopL5Q +N108_0.fsub_11/gateop_perm;gopA Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst u_axi_ddr_top/rd1_addr_start_valid0/opit_0;gopQ @@ -153866,14 +153701,20 @@ D;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/N249_12/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_araddr[10]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/rd1_cnt_num[2]/opit_0_A2Q21;gopA2Q2 @@ -154084,7 +153925,7 @@ I4;1 RS;1 Inst -u_axi_ddr_top/rd_all_full/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/record_araddr_valid/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -154100,7 +153941,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/ddr3_valid_fall0/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -154686,20 +154527,17 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N155.lt_2/gateop_perm;gopA +u_ddr_addr_ctr/u_wr3_addr_ctr/N108/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst -u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N12[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/N294_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -154709,20 +154547,14 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[8]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[3]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/rd3_data_en1/opit_0;gopQ @@ -154747,7 +154579,7 @@ D;1 RS;1 Inst -u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N24_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -155413,7 +155245,7 @@ S20;1 S21;1 Inst -u_axi_ddr_top/rx_rd1_addr_valid/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -155429,7 +155261,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/wr_sta_reg[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -155445,14 +155277,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/axi_addr_valid0/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/rd_sta0_reg0/opit_0;gopQ @@ -155499,7 +155337,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[7]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/rd_sta_reg[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -155547,7 +155385,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/rd_sta_reg[6]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/rd_sta_reg[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -155563,27 +155401,39 @@ L4;1 RS;1 Inst -u_axi_ddr_top/N855_inv/gateop_perm;gopLUT5 +u_axi_ddr_top/rx_rd1_addr_valid/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[37:0]_1/gateop_perm;gopLUT5 +u_axi_ddr_top/rd_sta_reg[7]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[1]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/rd_all_full/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -155610,37 +155460,55 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_next_state_13[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tmrd_pass/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/ptr/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/N87/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[4]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N406_3[0]_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -155661,39 +155529,27 @@ D;1 RS;1 Inst -u_axi_ddr_top/rd_sta_reg[1]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/N249_14/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/N598/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/s_axi_araddr[11]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_araddr[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -155709,7 +155565,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_araddr[17]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_araddr[18]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -155725,7 +155581,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_araddr[9]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[5]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -155758,7 +155614,7 @@ S0;1 S1;1 Inst -u_axi_ddr_top/s_axi_araddr[12]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_araddr[11]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -155790,23 +155646,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_araddr[13]/opit_0_L5Q_perm;gopL5Q -Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 - -Inst -u_axi_ddr_top/s_axi_araddr[14]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_araddr[12]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -155822,7 +155662,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/N412_mux15_12/gateop_perm;gopLUT5 +u_axi_ddr_top/N412_mux15_10/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -155832,7 +155672,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[3]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_araddr[14]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -155848,7 +155688,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_araddr[20]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_araddr[26]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -155864,7 +155704,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_araddr[24]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_araddr[16]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -155880,7 +155720,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_araddr[21]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_araddr[19]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -155896,7 +155736,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_araddr[29]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_araddr[20]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -155912,7 +155752,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_araddr[22]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_araddr[21]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -155928,17 +155768,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/N575/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/s_axi_araddr[28]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[22]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -155970,7 +155800,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_araddr[27]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_araddr[28]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -155986,7 +155816,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_araddr[25]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_araddr[22]/opit_0_L5Q;gopL5Q Pin CEOUT;2 Q;2 @@ -156002,7 +155832,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_araddr[26]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156018,7 +155848,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[22]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_araddr[25]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156034,36 +155864,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_20/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_araddr[29]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[27]/opit_0_inv_AQ_perm;gopAQ -Pin -CEOUT;2 -Cout;2 -Q;2 -RSOUT;2 -Y;2 -CE;1 -CLK;1 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[22]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_araddr[27]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156079,56 +155896,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_arid[0]/opit_0;gopQ -Pin -CEOUT;2 -Q;2 -RSOUT;2 -CE;1 -CLK;1 -D;1 -RS;1 - -Inst -u_axi_ddr_top/s_axi_arid[1]/opit_0;gopQ -Pin -CEOUT;2 -Q;2 -RSOUT;2 -CE;1 -CLK;1 -D;1 -RS;1 - -Inst -u_axi_ddr_top/s_axi_arid[2]/opit_0;gopQ -Pin -CEOUT;2 -Q;2 -RSOUT;2 -CE;1 -CLK;1 -D;1 -RS;1 - -Inst -u_axi_ddr_top/s_axi_arlen[0]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_18/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N54_3/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_23/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -156138,7 +155916,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/s_axi_rdata0[64]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[18]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156154,55 +155932,40 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[133]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_arid[0]/opit_0;gopQ Pin CEOUT;2 Q;2 RSOUT;2 -Z;2 CE;1 CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +D;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[7]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_arid[1]/opit_0;gopQ Pin CEOUT;2 Q;2 RSOUT;2 -Z;2 CE;1 CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +D;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[97]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_arid[2]/opit_0;gopQ Pin CEOUT;2 Q;2 RSOUT;2 -Z;2 CE;1 CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +D;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[5]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_arlen[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156218,7 +155981,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[197]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_id[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156234,7 +155997,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[21]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156266,7 +156029,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[15]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156282,7 +156045,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[12]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156298,7 +156061,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[104]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[68]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156314,7 +156077,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[72]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156330,7 +156093,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[139]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[132]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156346,7 +156109,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[77]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[71]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156362,7 +156125,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[73]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[10]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156378,7 +156141,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[136]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[14]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156394,7 +156157,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[182]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[11]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156410,7 +156173,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[18]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[75]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156426,7 +156189,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[49]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[74]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156442,7 +156205,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[42]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[15]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156458,7 +156221,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[86]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[78]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156474,7 +156237,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[117]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[73]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156490,17 +156253,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_fsm[2:0]_36/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/s_axi_rdata0[55]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[22]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156516,7 +156269,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[30]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[19]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156532,7 +156285,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[27]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[20]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156548,7 +156301,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[59]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[81]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156564,7 +156317,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[89]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[82]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156580,7 +156333,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[92]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[23]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156596,7 +156349,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[95]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[85]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156612,7 +156365,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[255]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[247]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156644,7 +156397,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[89]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156660,7 +156413,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[229]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[90]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156676,7 +156429,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[35]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[155]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156692,7 +156445,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[162]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_70/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/s_axi_rdata0[31]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156708,7 +156471,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[101]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[157]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156724,7 +156487,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[167]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[94]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156740,7 +156503,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[100]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[37]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156756,7 +156519,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[103]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[102]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156772,7 +156535,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[41]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[99]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156788,7 +156551,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[146]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[36]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156804,17 +156567,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_135/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[161]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[112]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[160]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156830,7 +156599,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[234]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[39]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156846,7 +156615,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[83]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[166]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156862,7 +156631,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[171]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[45]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156878,7 +156647,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[110]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[42]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156894,7 +156663,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[80]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[170]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156910,7 +156679,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[81]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[107]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156926,7 +156695,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[246]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[105]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156942,7 +156711,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[147]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[173]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156958,7 +156727,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[148]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[136]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156974,7 +156743,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[134]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[200]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -156990,7 +156759,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[113]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[112]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157006,7 +156775,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[183]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[113]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157022,7 +156791,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[248]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[114]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157038,7 +156807,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[58]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[178]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157054,7 +156823,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[185]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[244]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157070,7 +156839,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[251]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[243]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157086,7 +156855,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[187]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[182]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157102,7 +156871,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[184]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[115]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157118,7 +156887,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[63]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[184]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157134,7 +156903,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[190]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[121]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157150,7 +156919,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[96]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[60]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157166,7 +156935,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[68]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[188]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157182,7 +156951,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[194]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[250]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157198,7 +156967,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[98]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[190]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157214,7 +156983,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[70]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[63]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157230,7 +156999,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[165]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[189]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157246,7 +157015,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[130]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[65]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157262,7 +157031,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[135]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[69]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157278,7 +157047,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[75]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[67]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157294,7 +157063,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[207]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[5]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157310,7 +157079,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[76]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_fsm[3:0]_34_2/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/s_axi_rdata0[70]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157326,7 +157105,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[200]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157342,7 +157121,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[138]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[128]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157358,7 +157137,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[141]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[77]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157374,7 +157153,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[142]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[76]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157390,7 +157169,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[140]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[142]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157406,7 +157185,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[176]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[12]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157422,7 +157201,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N202_50/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N265_10/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -157432,23 +157211,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/s_axi_rdata0[84]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N151_2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[115]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[79]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157464,7 +157237,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[177]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_check_done/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157480,7 +157253,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[151]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[80]/opit_0_L5Q;gopL5Q Pin CEOUT;2 Q;2 @@ -157496,27 +157269,39 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_103/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[84]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_71/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[48]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[191]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[144]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157532,23 +157317,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[91]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_63/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[122]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[87]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157564,7 +157343,27 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[26]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N118_17/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/s_axi_rdata0[125]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157580,7 +157379,37 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[154]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N118_20/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_66/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N202_44/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/s_axi_rdata0[93]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157596,7 +157425,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[152]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[156]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157612,7 +157441,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[94]/opit_0_L5Q;gopL5Q +u_axi_ddr_top/s_axi_rdata0[95]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157628,7 +157457,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[61]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[28]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157644,27 +157473,39 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N538_5/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[97]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_542_2/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[225]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[99]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[101]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157680,17 +157521,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N637_5/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[162]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[160]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[164]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157706,7 +157553,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[225]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[103]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157722,7 +157569,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[164]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[163]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157738,7 +157585,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[231]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[165]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157754,7 +157601,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[11]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[106]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157770,7 +157617,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[106]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[171]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157786,7 +157633,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[107]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[43]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157802,7 +157649,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[210]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[172]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157818,7 +157665,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[172]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[168]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157834,7 +157681,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[128]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_67/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/s_axi_rdata0[111]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157850,7 +157707,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[174]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[108]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157866,7 +157723,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[176]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157898,7 +157755,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[114]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[118]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157914,17 +157771,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_90/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/s_axi_rdata0[237]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[179]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157940,7 +157787,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[144]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[177]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157956,7 +157803,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[236]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[119]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -157972,23 +157819,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[169]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N55_9/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[213]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[181]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158004,7 +157845,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[123]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[122]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158020,7 +157861,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[137]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[185]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158036,7 +157877,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[249]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[123]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158052,7 +157893,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[216]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[248]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158068,7 +157909,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[156]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[120]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158100,7 +157941,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[158]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[124]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158116,7 +157957,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[159]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[254]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158132,23 +157973,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[6]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_6[0]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[71]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[131]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158164,7 +157999,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[2]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[135]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158180,17 +158015,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N598_1_4/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[193]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[193]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[196]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158206,7 +158047,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[195]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[130]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158222,7 +158063,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[181]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[195]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158238,7 +158079,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[199]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[192]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158254,17 +158095,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N52_9[2]_2/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[47]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[155]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[139]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158280,7 +158127,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[202]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[140]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158296,7 +158143,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[203]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[201]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158312,7 +158159,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[143]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[141]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158328,20 +158175,14 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[205]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_87/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/s_axi_rdata0[204]/opit_0_L5Q_perm;gopL5Q @@ -158360,7 +158201,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[78]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[202]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158376,7 +158217,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[118]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[17]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158392,7 +158233,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[150]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[147]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158408,7 +158249,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[168]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[208]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158424,23 +158265,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[179]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_107/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[170]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[211]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158456,7 +158291,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[175]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[150]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158472,7 +158307,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[214]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[151]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158488,7 +158323,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[247]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[215]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158504,17 +158339,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_67/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[153]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[217]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[25]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158530,7 +158371,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[218]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[216]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158546,7 +158387,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[201]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[219]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158578,7 +158419,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[221]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[158]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158594,7 +158435,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[222]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[159]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158610,7 +158451,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N118_17/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_130/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -158620,17 +158461,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/wdata_path_adj/N18[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[229]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[161]/opit_0_L5Q;gopL5Q +u_axi_ddr_top/s_axi_rdata0[224]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158646,7 +158493,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[36]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[226]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158662,7 +158509,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[166]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[227]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158678,7 +158525,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[230]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[228]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158694,7 +158541,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[231]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158710,7 +158557,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[226]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[167]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158726,17 +158573,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N570/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[105]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[174]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158752,7 +158605,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[232]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[233]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158768,7 +158621,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[180]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[234]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158784,7 +158637,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[173]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[235]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158800,7 +158653,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[192]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[236]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158816,7 +158669,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[212]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[237]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158832,7 +158685,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[238]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[175]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158848,7 +158701,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[239]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N124_5/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/s_axi_rdata0[240]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158864,7 +158727,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_107/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N202_63/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -158874,7 +158737,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/s_axi_rdata0[240]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[241]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158890,23 +158753,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[241]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N202_46/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[211]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[51]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158922,7 +158779,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[43]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[183]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158938,7 +158795,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[245]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[246]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158954,7 +158811,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[242]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_103/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/s_axi_rdata0[186]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158970,7 +158837,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[198]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[249]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -158986,7 +158853,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[250]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[187]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -159002,7 +158869,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[186]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[58]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -159018,7 +158885,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[60]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[251]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -159034,7 +158901,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[188]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[191]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -159066,7 +158933,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_82/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -159076,7 +158943,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/s_axi_rdata0[254]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[199]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -159092,7 +158959,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[56]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[194]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -159108,7 +158975,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[53]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -159124,7 +158991,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[196]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[197]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -159140,27 +159007,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N570/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N446_0_3/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[64]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[65]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[198]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -159176,37 +159039,55 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N701_7/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_fsm[2:0]_39_2/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[5]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/N4_4/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[232]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[9]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[207]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -159222,17 +159103,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[205]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[157]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[13]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -159248,7 +159135,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[74]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -159280,7 +159167,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[120]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -159296,7 +159183,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[13]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[9]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -159312,7 +159199,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[223]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[209]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -159328,7 +159215,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[209]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[210]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -159344,27 +159231,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped_5[0]/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N118_5/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_105/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_71/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -159374,17 +159241,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N118_17/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[212]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[215]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[213]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -159400,17 +159273,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_fsm[4:0]_64/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[146]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_98/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N118_13/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -159420,7 +159299,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/s_axi_rdata0[29]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[148]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -159436,7 +159315,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[219]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[217]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -159452,7 +159331,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[90]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[218]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -159468,23 +159347,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[25]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N118_24/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[28]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[221]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -159500,7 +159373,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N202_46/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N118_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -159510,17 +159383,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N118_5/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[29]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[125]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[223]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -159536,7 +159415,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N456/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N295_mux2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -159546,23 +159425,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/s_axi_rdata0[227]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N21_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[228]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gate_check/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -159578,23 +159451,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N20_4/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[10]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[41]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -159610,7 +159477,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_done/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/N1_2_cpy/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/dqs_gate_check_pass/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -159626,7 +159503,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[4]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -159642,7 +159519,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_fsm[3:0]_3377/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_fsm[2:0]_35/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -159652,7 +159529,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/s_axi_rdata0[233]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[239]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -159668,39 +159545,27 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[40]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_99/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[244]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_95/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[23]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[27]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -159716,7 +159581,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[45]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[92]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -159732,7 +159597,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_115/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N63/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -159742,7 +159607,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_97/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N66_ac2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -159752,7 +159617,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/s_axi_rdata0[243]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -159768,7 +159633,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_117/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N202_66/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -159778,7 +159643,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/s_axi_rdata0[17]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[242]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -159794,27 +159659,39 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N172_75/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[54]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N564_35/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[245]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[52]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[154]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -159840,17 +159717,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N172_136/gateop_perm;gopLUT5 +u_axi_ddr_top/s_axi_rdata0[24]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_fsm[2:0]_36/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N118_20/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -159860,7 +159743,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N85[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N202_36/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -159870,39 +159753,27 @@ L3;1 L4;1 Inst -u_axi_ddr_top/s_axi_rdata0[57]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N118_17/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[252]/opit_0_L5Q_perm;gopL5Q +u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[252]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -159918,23 +159789,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/s_axi_rdata0[189]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_74/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[255]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -159950,7 +159815,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_118/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -159960,7 +159825,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N172_83/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N570/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -163066,27 +162931,39 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N85[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N85[3]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -163102,7 +162979,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -163118,7 +162995,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N85[6]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N85[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -163128,7 +163005,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -163144,7 +163021,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -163160,17 +163037,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N85[10]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[11]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[11]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_valid_0/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -163186,20 +163069,14 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N85[8]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0;gopQ @@ -163496,7 +163373,7 @@ I14;1 RS;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -163528,7 +163405,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -163544,7 +163421,27 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -163576,7 +163473,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -163592,7 +163489,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -163608,17 +163505,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -163634,7 +163521,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/next_len[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -163650,17 +163537,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -163808,7 +163685,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N24_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -163818,7 +163695,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N24_6/gateop_perm;gopLUT5 +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -163828,7 +163705,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -163838,27 +163715,39 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N24_8/gateop_perm;gopLUT5 +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -163868,17 +163757,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[6]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -163914,17 +163809,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[4]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N24_4/gateop_perm;gopLUT5 +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N106_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -163934,23 +163835,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_11/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N85[4]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N24_10/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -163960,23 +163855,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N85[0]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N106_5/gateop_perm;gopLUT5 +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N106_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -163986,7 +163875,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[5]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N85[7]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -164006,7 +163895,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -164022,17 +163911,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N106_3/gateop_perm;gopLUT5 +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N106_1/gateop_perm;gopLUT5 +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N85[5]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -164042,17 +163937,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N85[7]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[17]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N85[8]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_35/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -164062,7 +163963,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106/gateop_perm;gopLUT5 +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N85[10]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -164072,7 +163973,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N85[9]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_12/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -164082,43 +163983,49 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_2/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[11]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N106_5/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N151_2/gateop_perm;gopLUT5 +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N106_7/gateop_perm;gopLUT5 +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N24_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -164128,7 +164035,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N106_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -164138,7 +164045,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -164154,7 +164061,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N24_2/gateop_perm;gopLUT5 +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N151_2/gateop;gopLUT5 Pin Z;2 L0;1 @@ -165484,7 +165391,7 @@ WR_EOP;1 WR_ERR;1 Inst -u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N12[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -165494,7 +165401,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_31/gateop_perm;gopLUT5 +u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -165504,23 +165411,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/cnt_times[0]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N3[3]/gateop;gopLUT5 +u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -165530,7 +165431,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -165540,20 +165441,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N21.eq_4/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_19/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -165563,7 +165451,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_22/gateop_perm;gopLUT5 +u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -165573,7 +165461,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -165583,36 +165471,24 @@ L3;1 L4;1 Inst -u_axi_ddr_top/s_axi_araddr[7]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[21]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_33/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N12[3]/gateop_perm;gopLUT5 @@ -165625,7 +165501,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/N448_7/gateop_perm;gopLUT5 +u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N12[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -165635,23 +165511,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/rd_sta_reg[0]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N12[6]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N12[6]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N12[5]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -165661,7 +165531,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N12[7]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_30/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -165671,39 +165541,43 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[25]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N12[7]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/s_axi_araddr[6]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N21.eq_4/gateop_perm;gopA Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N12[8]/gateop;gopLUT5 +u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N24.eq_4/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + +Inst +u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N12[9]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -165713,14 +165587,20 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/N574_3_3/gateop_perm;gopLUT5 +u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N21.eq_0/gateop_A2;gopA2 @@ -165763,20 +165643,14 @@ I13;1 I14;1 Inst -u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_31/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N24.eq_0/gateop_A2;gopA2 @@ -165819,7 +165693,7 @@ I13;1 I14;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_25/gateop_perm;gopLUT5 +u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N12[8]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -165975,7 +165849,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_30/gateop_perm;gopLUT5 +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N85[3]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -166359,7 +166233,7 @@ WR_EOP;1 WR_ERR;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N21_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -166369,7 +166243,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[33]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -166401,7 +166275,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/N32_mux8_9/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -166411,7 +166285,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -166437,36 +166311,24 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/cnt_times[0]/opit_0_inv_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/N55_7/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[9]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5 @@ -166479,17 +166341,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/N85/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/rd0_fifo_empty0/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N85[1]/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/N134_78/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -166599,20 +166467,14 @@ I4;1 RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/rd_ddr_valid/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[3]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/u_axi_rd_connect/rd0_fifo_full0/opit_0_L5Q_perm;gopL5Q @@ -166631,17 +166493,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_ov5640/u_mix_image/cnt1_w[8]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/rd1_data_valid0/opit_0_L5Q;gopL5Q Pin CEOUT;2 Q;2 @@ -166657,24 +166525,36 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N34_6/gateop_perm;gopLUT5 +u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[19]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N12[1]/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/u_axi_rd_connect/rd_sta_reg[1]/opit_0_L5Q_perm;gopL5Q @@ -166725,7 +166605,7 @@ L4;1 RS;1 Inst -u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[0]/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/N114_mux5_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -166789,17 +166669,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_fsm[3:0]_1_7/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/N45_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -166819,30 +166689,23 @@ L3;1 L4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/N111.lt_2/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N3[3]/gateop;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N12[4]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -166852,7 +166715,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/vector_to_matrix_inst/mat[0][0][12]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -166878,7 +166741,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N3[7]/gateop;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_g/N188_40/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -166888,20 +166751,7 @@ L3;1 L4;1 Inst -image_filiter_inst/hybrid_filter_inst/N155.fsub_5/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -image_filiter_inst/hybrid_filter_inst/N146_mux2_3/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -166911,37 +166761,68 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N12[9]/gateop_perm;gopLUT5 +image_filiter_inst2/vector_to_matrix_inst/mat[0][2][12]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N12[1]/gateop_perm;gopLUT5 +image_filiter_inst2/vector_to_matrix_inst/mat[0][0][11]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N12[2]/gateop_perm;gopLUT5 +image_filiter_inst2/vector_to_matrix_inst/mat[0][2][11]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N12[3]/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N39.lt_2/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + +Inst +u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N12[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -166951,7 +166832,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N12[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -166961,7 +166842,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N12[5]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N12[3]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -166971,7 +166852,7 @@ L3;1 L4;1 Inst -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[3]_1/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -166981,7 +166862,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N12[7]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N12[5]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -166991,7 +166872,7 @@ L3;1 L4;1 Inst -image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/N39_0_ac6/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N12[6]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -167001,7 +166882,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N12[10]/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/N118_mux3_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -167021,100 +166902,44 @@ L3;1 L4;1 Inst -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N12[9]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N24.eq_0/gateop_A2;gopA2 -Pin -Cout;2 -Y0;2 -Y1;2 -Cin;1 -I0X;1 -I1X;1 -I00;1 -I01;1 -I02;1 -I03;1 -I04;1 -I10;1 -I11;1 -I12;1 -I13;1 -I14;1 - -Inst -u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N24.eq_2/gateop_A2;gopA2 +u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N12[10]/gateop_perm;gopLUT5 Pin -Cout;2 -Y0;2 -Y1;2 -Cin;1 -I0X;1 -I1X;1 -I00;1 -I01;1 -I02;1 -I03;1 -I04;1 -I10;1 -I11;1 -I12;1 -I13;1 -I14;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21;gopA2Q2 +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N167.lt_2/gateop_perm;gopA Pin -CEOUT;2 Cout;2 -Q0;2 -Q1;2 -RSOUT;2 -Y0;2 -Y1;2 -CE;1 -CLK;1 +Y;2 Cin;1 +I0;1 I0X;1 -I1X;1 -I00;1 -I01;1 -I02;1 -I03;1 -I04;1 -I10;1 -I11;1 -I12;1 -I13;1 -I14;1 -RS;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21;gopA2Q2 +u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N24.eq_0/gateop_A2;gopA2 Pin -CEOUT;2 Cout;2 -Q0;2 -Q1;2 -RSOUT;2 Y0;2 Y1;2 -CE;1 -CLK;1 Cin;1 I0X;1 I1X;1 @@ -167128,20 +166953,13 @@ I11;1 I12;1 I13;1 I14;1 -RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21;gopA2Q2 +u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N24.eq_2/gateop_A2;gopA2 Pin -CEOUT;2 Cout;2 -Q0;2 -Q1;2 -RSOUT;2 Y0;2 Y1;2 -CE;1 -CLK;1 Cin;1 I0X;1 I1X;1 @@ -167155,10 +166973,9 @@ I11;1 I12;1 I13;1 I14;1 -RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21;gopA2Q2 +u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21;gopA2Q2 Pin CEOUT;2 Cout;2 @@ -167185,7 +167002,88 @@ I14;1 RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/opit_0_inv_A2Q21;gopA2Q2 +u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21;gopA2Q2 +Pin +CEOUT;2 +Cout;2 +Q0;2 +Q1;2 +RSOUT;2 +Y0;2 +Y1;2 +CE;1 +CLK;1 +Cin;1 +I0X;1 +I1X;1 +I00;1 +I01;1 +I02;1 +I03;1 +I04;1 +I10;1 +I11;1 +I12;1 +I13;1 +I14;1 +RS;1 + +Inst +u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21;gopA2Q2 +Pin +CEOUT;2 +Cout;2 +Q0;2 +Q1;2 +RSOUT;2 +Y0;2 +Y1;2 +CE;1 +CLK;1 +Cin;1 +I0X;1 +I1X;1 +I00;1 +I01;1 +I02;1 +I03;1 +I04;1 +I10;1 +I11;1 +I12;1 +I13;1 +I14;1 +RS;1 + +Inst +u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21;gopA2Q2 +Pin +CEOUT;2 +Cout;2 +Q0;2 +Q1;2 +RSOUT;2 +Y0;2 +Y1;2 +CE;1 +CLK;1 +Cin;1 +I0X;1 +I1X;1 +I00;1 +I01;1 +I02;1 +I03;1 +I04;1 +I10;1 +I11;1 +I12;1 +I13;1 +I14;1 +RS;1 + +Inst +u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/opit_0_inv_A2Q21;gopA2Q2 Pin CEOUT;2 Cout;2 @@ -167257,7 +167155,7 @@ I14;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/N142_mux4_3/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N12[7]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -167771,33 +167669,33 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N106_8/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[2]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[6]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -167807,20 +167705,14 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N106_8/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q @@ -167839,14 +167731,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N34_4/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[11]/opit_0_L5Q_perm;gopL5Q @@ -167865,7 +167763,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N106_4/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N34_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -168152,17 +168050,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -168178,7 +168082,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -168220,7 +168124,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -168236,30 +168140,27 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_r/N35.lt_2/gateop_perm;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N287_5/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0;gopQ @@ -168382,7 +168283,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -168392,7 +168293,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N34_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -168402,7 +168303,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N34_8/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -168412,7 +168313,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -168428,7 +168329,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N34_2/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N106_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -168454,27 +168365,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N158.eq_4/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N34_3/gateop_perm;gopLUT5 @@ -168487,17 +168391,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[7]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N106_2/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N106_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -168507,7 +168417,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N34_7/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N34_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -168517,7 +168427,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -168527,17 +168437,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N34_6/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[3]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[5]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -168547,7 +168463,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[3]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -168557,7 +168473,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[7]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N106_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -168567,23 +168483,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[7]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N106_6/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[6]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -168593,23 +168503,20 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N8.lt_2/gateop_perm;gopA Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N17_1/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N34_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -168629,7 +168536,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N12[4]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[10]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -168639,33 +168546,30 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/N45_8/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N4.lt_2/gateop_perm;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/rd_sta_reg[0]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[10]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[8]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -168675,23 +168579,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N34_6/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -168747,7 +168645,7 @@ I13;1 I14;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N287_5/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -168797,20 +168695,17 @@ I13;1 I14;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/N99.fsub_5/gateop_perm;gopA Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0;gopQ @@ -169194,20 +169089,14 @@ I14;1 RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N34_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/opit_0_inv_A2Q21;gopA2Q2 @@ -169372,7 +169261,7 @@ I14;1 RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -169404,7 +169293,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[3]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -169436,7 +169335,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[6]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -169446,7 +169345,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -169462,7 +169361,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -169477,16 +169376,6 @@ L3;1 L4;1 RS;1 -Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[9]/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - Inst u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[11]/opit_0_L5Q_perm;gopL5Q Pin @@ -169504,7 +169393,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -169759,7 +169648,7 @@ I14;1 RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -169775,7 +169664,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -169791,23 +169680,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -169823,17 +169706,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N106_6/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N106_8/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -169843,14 +169732,20 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[5]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm;gopL5Q @@ -169885,14 +169780,23 @@ L4;1 RS;1 Inst -u_rotate_image/N44_mux7_7/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[10]/opit_0_inv_AQ_perm;gopAQ Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +CEOUT;2 +Cout;2 +Q;2 +RSOUT;2 +Y;2 +CE;1 +CLK;1 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 +RS;1 Inst u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0;gopQ @@ -170025,39 +169929,27 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N106_6/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -170067,7 +169959,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -170077,17 +169969,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N34_8/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N106_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -170097,7 +169995,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N106_2/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N287_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -170107,7 +170005,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N34_3/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N34_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -170117,7 +170015,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N34_4/gateop_perm;gopLUT5 +u_ov5640/coms1_reg_config/u1/N256_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -170127,17 +170025,14 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N158.eq_4/gateop_perm;gopA +u_ov5640/coms1_reg_config/N1193_3/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N34_7/gateop_perm;gopLUT5 @@ -170150,7 +170045,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N34_2/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N34_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -170160,7 +170055,7 @@ L3;1 L4;1 Inst -u_ddr_addr_ctr/u_rd3_addr_ctr/rd_image_cnt[1]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -170186,7 +170081,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[3]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -170196,7 +170091,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[8]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[5]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -170206,7 +170101,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -170222,7 +170117,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[6]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -170232,7 +170127,7 @@ L3;1 L4;1 Inst -u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[7]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -170242,7 +170137,7 @@ L3;1 L4;1 Inst -u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[8]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -170262,7 +170157,7 @@ L3;1 L4;1 Inst -u_rotate_image/N44_mux7_8/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N106_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -170272,7 +170167,7 @@ L3;1 L4;1 Inst -u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[3]_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -170282,17 +170177,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N106_4/gateop_perm;gopLUT5 +u_ov5640/coms1_reg_config/reg_index[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -170308,7 +170209,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[4]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N106_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -170318,7 +170219,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -170374,7 +170275,7 @@ I13;1 I14;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N287_5/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N34_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -170504,20 +170405,14 @@ I13;1 I14;1 Inst -u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr2[12]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/N85/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0;gopQ @@ -171255,7 +171150,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -171265,7 +171160,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -171275,7 +171170,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N12[5]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -171295,7 +171190,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N22.eq_4/gateop_perm;gopA +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N5.lt_2/gateop_perm;gopA Pin Cout;2 Y;2 @@ -171308,7 +171203,7 @@ I3;1 I4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N3[6]/gateop;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N202_38/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -171318,7 +171213,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/s_axi_rdata0[121]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/s_axi_rdata0[50]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -171334,7 +171229,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N118_9/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N12[8]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -171344,23 +171239,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N12[6]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N12[11]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N12[10]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -171380,7 +171269,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N12[6]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N12[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -171390,17 +171279,20 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N12[5]/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N109.lt_2/gateop_perm;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/N32_mux8_8/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N12[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -171420,14 +171312,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N22.eq_4/gateop_perm;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N12[9]/gateop_perm;gopLUT5 @@ -171440,7 +171335,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N24_10/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N12[11]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -171450,30 +171345,27 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N12[10]/gateop;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N111.lt_2/gateop_perm;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N17/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N22.eq_0/gateop_A2;gopA2 @@ -171516,7 +171408,7 @@ I13;1 I14;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -171765,14 +171657,20 @@ I14;1 RS;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21;gopA2Q2 @@ -173956,7 +173854,7 @@ WR_EOP;1 WR_ERR;1 Inst -u_axi_ddr_top/u_axi_wr_connect/N576_inv/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/N244/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -173966,7 +173864,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/N196_4/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/N448_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -173986,23 +173884,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/s_axi_araddr[16]/opit_0_L5Q_perm;gopL5Q -Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 - -Inst -u_axi_ddr_top/u_axi_wr_connect/N294_8/gateop_perm;gopLUT5 +u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -174012,7 +173894,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/N574_9[11]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/N249_12/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -174022,7 +173904,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/N574_9[6]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/N574_9[10]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -174032,17 +173914,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/N294_13/gateop_perm;gopLUT5 +u_axi_ddr_top/rd0_ddr_done1/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/N469_4/gateop_perm;gopLUT5 +u_axi_ddr_top/N866_2_and[34][0]_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -174052,7 +173940,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/N598/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/N565/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -174062,7 +173950,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/N264_13/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/N574_9[8]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -174072,7 +173960,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/N264_14/gateop_perm;gopLUT5 +u_axi_ddr_top/N261_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -174098,7 +173986,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/N574_9[7]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/N264_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -174108,7 +173996,26 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/N574_9[10]/gateop_perm;gopLUT5 +u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[27]/opit_0_AQ_perm;gopAQ +Pin +CEOUT;2 +Cout;2 +Q;2 +RSOUT;2 +Y;2 +CE;1 +CLK;1 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 +RS;1 + +Inst +u_axi_ddr_top/u_axi_wr_connect/N574_9[19]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -174128,17 +174035,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/N574_9[19]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_35/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/N448_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -174148,7 +174061,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[26]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -174174,75 +174087,79 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/N565/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[5].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/N61_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_addr_valid0/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/rd_sta_reg[7]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[11]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/N256_5/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr2[12]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -174258,7 +174175,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/N592/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/N574_9[5]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -174268,7 +174185,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/N574_9[5]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/N574_9[7]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -174278,7 +174195,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_done0/opit_0_L5Q_perm;gopL5Q +u_ddr_addr_ctr/u_rd0_addr_ctr/rd0_sta_reg[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -174294,7 +174211,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/N574_9[8]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/N574_9[20]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -174304,7 +174221,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/N574_9[12]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/N574_9[9]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -174314,7 +174231,7 @@ L3;1 L4;1 Inst -u_ddr_addr_ctr/u_wr1_addr_ctr/image_fram_cnt1[4]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -174330,7 +174247,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_18/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/N575/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -174340,23 +174257,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/rx0_addr_valid/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/N574_9[12]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/s_axi_araddr[5]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_done1/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -174372,27 +174283,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/N866_2_or[4]/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/u_axi_wr_connect/N249_13/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/rx0_addr_valid/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_ddr_addr_ctr/u_rd0_addr_ctr/N20_8/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/N592/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -174468,23 +174375,17 @@ S0;1 S1;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[15]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/N196_4/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[24]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/cnt_times[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -174500,17 +174401,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/N610/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[1].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/s_axi_araddr[10]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/rx1_addr_valid/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -174526,14 +174433,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/N249_8/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/delay_cnt3[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/u_axi_wr_connect/axi_addr0[0]/opit_0_MUX4TO1Q;gopMUX4TO1Q @@ -174838,7 +174751,17 @@ I4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_valid0/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -174854,7 +174777,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[51]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -174870,7 +174793,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[16]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -174886,7 +174809,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[3]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -174902,7 +174825,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[19]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -174918,7 +174841,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[18]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -174934,7 +174857,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[23]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -174950,7 +174873,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[22]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[20]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -174966,7 +174889,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[7]/opit_0_L5Q;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[9]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -174982,7 +174905,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[28]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[62]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -174998,7 +174921,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[9]/opit_0_L5Q;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[11]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175014,7 +174937,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[11]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[13]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175030,7 +174953,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[40]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[15]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175046,7 +174969,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[13]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[14]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175062,7 +174985,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[42]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/N99.fsub_5/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + +Inst +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[59]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175078,7 +175014,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[15]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[49]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175094,7 +175030,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[56]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[34]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175110,7 +175046,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[20]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[36]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175126,7 +175062,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[35]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[21]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175142,7 +175078,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[32]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[22]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175174,7 +175110,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[39]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[23]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175190,7 +175126,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[34]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[32]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175206,7 +175142,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[25]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175222,7 +175158,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[6]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[27]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175238,7 +175174,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[25]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[29]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175254,7 +175190,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[27]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[61]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175270,7 +175206,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[31]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[30]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175286,7 +175222,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[30]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[57]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175302,7 +175238,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[44]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[31]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175318,7 +175254,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[45]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[58]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175334,7 +175270,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[10]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[42]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175350,7 +175286,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[8]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[35]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175366,7 +175302,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[50]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[54]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175382,17 +175318,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N254/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[55]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[37]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175408,7 +175350,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[36]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[52]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175424,7 +175366,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[53]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[39]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175440,7 +175382,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[37]/opit_0_L5Q;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[48]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175456,7 +175398,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[48]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[41]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175472,7 +175414,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[38]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[44]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175488,7 +175430,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[41]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[43]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175504,7 +175446,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[14]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[46]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175520,7 +175462,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[43]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[45]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175536,7 +175478,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[10]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[26]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175552,7 +175494,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[58]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[47]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175568,7 +175510,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[46]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[40]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175584,7 +175526,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[47]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[51]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175600,7 +175542,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[8]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[50]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175616,7 +175558,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[49]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[53]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175632,23 +175574,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[54]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[1]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[21]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[38]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175664,7 +175600,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[2]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175680,7 +175616,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[52]/opit_0_L5Q;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[55]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175696,39 +175632,27 @@ L4;1 RS;1 Inst -u_axi_ddr_top/delay_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[6]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[8]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[17]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[60]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175744,7 +175668,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[57]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[12]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175760,17 +175684,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/wr_sta_fsm[3:0]_7/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N35.lt_2/gateop_perm;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[59]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_deb_pre/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175786,7 +175713,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[60]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[28]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175802,7 +175729,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[61]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[63]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175818,7 +175745,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[12]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[10]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175834,7 +175761,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[63]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -175850,34 +175777,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N50[4]/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_26/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[2].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/u_axi_wr_connect/cnt_times[2]/opit_0_A2Q21;gopA2Q2 @@ -175988,7 +175901,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/ddr3_valid_fall0/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_done0/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -176015,7 +175928,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/N574_9[20]/gateop_perm;gopLUT5 +u_ddr_addr_ctr/u_wr0_addr_ctr/N7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -176078,7 +175991,7 @@ L4;1 RS;1 Inst -u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[0]/opit_0_L5Q_perm;gopL5Q +u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[10]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -176109,6 +176022,16 @@ L3;1 L4;1 RS;1 +Inst +u_axi_ddr_top/u_axi_wr_connect/delay_cnt1[2:0]_e/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + Inst u_axi_ddr_top/u_axi_wr_connect/delay_cnt1[2]/opit_0_L5Q_perm;gopL5Q Pin @@ -176126,7 +176049,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/ddr1_valid_fall0/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -176142,7 +176065,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/rd0_ddr_done1/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/delay_cnt3[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -176158,7 +176081,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/delay_cnt3[1]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/delay_cnt3[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -176174,7 +176097,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/delay_cnt3[2:0]_e/gateop_perm;gopLUT5 +u_ddr_addr_ctr/u_wr3_addr_ctr/N1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -176184,7 +176107,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/delay_cnt3[2]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/rd0_addr_start_fall/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -176200,17 +176123,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/N249_14/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_5/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -176220,7 +176133,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_14/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -176230,7 +176143,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/N440/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -176402,7 +176315,7 @@ I14;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -176434,23 +176347,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[8]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[6]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -176508,7 +176415,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N34_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -176518,23 +176425,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_6/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -176816,14 +176717,20 @@ I14;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_6/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm;gopL5Q @@ -176842,20 +176749,14 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm;gopL5Q @@ -176874,7 +176775,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -176890,17 +176791,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -176932,7 +176839,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -177062,7 +176969,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/N14/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -177072,7 +176979,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -177082,7 +176989,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[4]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -177092,23 +176999,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/rd_importance/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_8/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_4/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -177134,7 +177035,7 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/N86_mux4_3/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -177144,14 +177045,20 @@ L3;1 L4;1 Inst -image_filiter_inst2/hybrid_filter_inst/N90_mux2_3/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/rd_sta_reg[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5 @@ -177164,33 +177071,23 @@ L3;1 L4;1 Inst -image_filiter_inst2/hybrid_filter_inst/N99.fsub_5/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N5.lt_2/gateop_perm;gopA +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[0]/opit_0_inv_L5Q_perm;gopL5Q Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[6]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -177200,7 +177097,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_8/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N301/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -177210,30 +177107,30 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[2]/gateop_perm;gopLUT5 @@ -177246,7 +177143,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_8/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -177256,23 +177153,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[5]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -177282,23 +177173,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[7]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[7]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N327/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -177308,7 +177193,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_cal_error/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -177324,23 +177209,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/dfi_init_complete/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N139/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_6/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N323_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -177350,7 +177229,7 @@ L3;1 L4;1 Inst -image_filiter_inst2/hybrid_filter_inst/N106_72/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -177360,17 +177239,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_3/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[56]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_4/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -177393,27 +177278,39 @@ I3;1 I4;1 Inst -image_filiter_inst2/hybrid_filter_inst/N114_mux5_4/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[24]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_7/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_1/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -177423,7 +177320,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_2/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q +Pin +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 + +Inst +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_8/gateop;gopLUT5 Pin Z;2 L0;1 @@ -177533,14 +177446,20 @@ I13;1 I14;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N323_5/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N323_5.fsub_1/gateop_A2;gopA2 @@ -177583,14 +177502,17 @@ I13;1 I14;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N17/gateop_perm;gopLUT5 +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N161.lt_2/gateop_perm;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[5]/opit_0_A2Q1;gopA2Q1 @@ -178382,7 +178304,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -178565,7 +178487,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -178581,20 +178503,14 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_12/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm;gopL5Q @@ -178613,23 +178529,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[8]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -178645,34 +178555,52 @@ L4;1 RS;1 Inst -u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[11]/gateop_perm;gopLUT5 +u_rotate_image/addr_fifo_valid/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/opit_0;gopQ @@ -178947,7 +178875,7 @@ I14;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -178979,17 +178907,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_16/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -179021,14 +178955,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/N471_4/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm;gopL5Q @@ -179047,7 +178987,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -179063,7 +179003,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N39_mux3/gateop_perm;gopLUT5 +u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -179073,7 +179013,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5 +u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -179203,7 +179143,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N318_30[3]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -179213,7 +179153,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -179233,7 +179173,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[7]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_10/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -179243,7 +179183,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/N258/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -179253,33 +179193,33 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_12/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[3]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[16]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N404/gateop_perm;gopLUT5 +u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -179289,7 +179229,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_2/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/N132/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -179309,17 +179249,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_10/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N410/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_14/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -179329,7 +179275,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_16/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -179345,7 +179301,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -179355,7 +179311,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_2/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -179375,23 +179331,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[6]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[4]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N96_2/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[5]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -179401,7 +179351,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[6]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -179411,7 +179361,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[5]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -179421,7 +179371,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[7]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -179431,7 +179381,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[8]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -179441,17 +179391,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_4/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_1/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -179461,7 +179417,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/rd3_data_valid0/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -179477,7 +179433,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N323_5/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -179487,17 +179443,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_3/gateop_perm;gopLUT5 +u_rotate_image/rd_sta_reg[2]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_5/gateop_perm;gopLUT5 +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N24_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -179507,7 +179469,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[6]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -179517,7 +179479,7 @@ L3;1 L4;1 Inst -u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[7]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -179537,23 +179499,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/fifo1_data_full/opit_0_L5Q_perm;gopL5Q -Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 - -Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N75[7]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -179663,14 +179609,17 @@ I13;1 I14;1 Inst -u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[4]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N161.eq_4/gateop;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N323_5.fsub_1/gateop_A2;gopA2 @@ -179713,7 +179662,7 @@ I13;1 I14;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5 +u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -180512,7 +180461,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -180679,7 +180628,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -180695,7 +180644,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -180711,17 +180660,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[3]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[4]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -180747,20 +180702,14 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q @@ -180779,23 +180728,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[4]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_3/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[8]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -181076,6 +181019,16 @@ I13;1 I14;1 RS;1 +Inst +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + Inst u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm;gopL5Q Pin @@ -181093,17 +181046,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -181119,7 +181078,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N85[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -181129,7 +181088,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -181145,23 +181104,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -181177,7 +181130,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -181187,7 +181140,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -181202,16 +181155,6 @@ L3;1 L4;1 RS;1 -Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - Inst u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0;gopQ Pin @@ -181323,7 +181266,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -181333,7 +181276,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N75[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -181343,7 +181286,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -181353,7 +181296,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_2/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -181363,17 +181306,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -181383,7 +181332,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_8/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -181399,27 +181358,39 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/fifo0_data_full/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[8]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -181429,17 +181400,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_6/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -181455,7 +181432,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_8/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -181465,7 +181442,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -181481,7 +181458,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -181491,7 +181468,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[3]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -181501,7 +181478,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[6]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[5]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -181511,7 +181488,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -181527,7 +181504,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[7]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[6]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -181537,7 +181514,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[7]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -181547,20 +181524,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N161.eq_4/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -u_axi_ddr_top/N296_8/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_25/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -181570,7 +181534,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_7/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N323_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -181580,7 +181544,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_6/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -181590,7 +181554,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N323_5/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -181600,33 +181564,30 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/fifo3_data_full/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_1/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_r/N155.lt_2/gateop_perm;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_5/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/median_finder9_r/N188_40/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -181636,20 +181597,14 @@ L3;1 L4;1 Inst -u_rotate_image/addr_fifo_valid/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_6/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_7/gateop_perm;gopLUT5 @@ -181662,7 +181617,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_8/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -181672,14 +181627,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_4/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N161.eq_4/gateop_perm;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_0/gateop_A2;gopA2 @@ -181782,7 +181740,7 @@ I13;1 I14;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -181838,7 +181796,7 @@ I13;1 I14;1 Inst -u_axi_ddr_top/N589/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -182720,7 +182678,7 @@ S0;1 S1;1 Inst -u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[4]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -182753,27 +182711,23 @@ S0;1 S1;1 Inst -u_axi_ddr_top/u_axi_wr_connect/N258/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N35_23/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[4]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -182789,7 +182743,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/N87/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -182799,23 +182753,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[17]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/N576_inv/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/rx3_addr_valid/opit_0_L5Q_perm;gopL5Q +u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[8]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -182847,7 +182795,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/cnt0_times[0]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_done0/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -182862,6 +182810,16 @@ L3;1 L4;1 RS;1 +Inst +u_axi_ddr_top/u_axi_wr_connect/N249_8/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + Inst u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[2]/opit_0_A2Q21;gopA2Q2 Pin @@ -183071,7 +183029,7 @@ I4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/delay_cnt0[0]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_done0/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -183087,7 +183045,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_done0/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_done1/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -183301,14 +183259,20 @@ D;1 RS;1 Inst -u_axi_ddr_top/N878/gateop_perm;gopLUT5 +u_axi_ddr_top/rd_sta_reg[1]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[2]/opit_0_A2Q21;gopA2Q2 @@ -183519,30 +183483,30 @@ I4;1 RS;1 Inst -u_axi_ddr_top/N866_2_or[3]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/delay_cnt1[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_done1/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/N264_12/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr0[13]/opit_0;gopQ @@ -183743,7 +183707,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/N264_12/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/N610/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -183961,17 +183925,23 @@ I4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/N574_9[9]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/delay_cnt0[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/N294_12/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/N574_7_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -184139,14 +184109,20 @@ I14;1 RS;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/opit_0_inv_A2Q21;gopA2Q2 @@ -184311,17 +184287,23 @@ I14;1 RS;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -184331,20 +184313,14 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N85[2]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm;gopL5Q @@ -184379,7 +184355,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -184395,17 +184371,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N85[6]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -184421,7 +184403,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N85[6]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -184463,14 +184445,20 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/r_cnt_pass/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0;gopQ @@ -184783,7 +184771,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -184815,7 +184803,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N85[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -184825,20 +184813,14 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N85[5]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm;gopL5Q @@ -184857,17 +184839,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -184899,7 +184887,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -184915,7 +184903,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -184931,20 +184919,14 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0;gopQ @@ -185079,7 +185061,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N3[0]/gateop;gopLUT5 Pin Z;2 L0;1 @@ -185089,17 +185071,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N85[7]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -185109,49 +185097,43 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N24_8/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N85[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -185161,7 +185143,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N24_6/gateop_perm;gopLUT5 +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -185171,23 +185153,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N106_4/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N240_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -185197,7 +185173,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N85[10]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N24_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -185207,7 +185183,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N24_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N232_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -185217,7 +185193,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N24_6/gateop_perm;gopLUT5 +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N75[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -185227,7 +185203,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N24_8/gateop_perm;gopLUT5 +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N24_10/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -185237,7 +185213,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -185253,7 +185229,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N85[3]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N75[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -185263,7 +185239,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N85[4]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N85[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -185273,7 +185249,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_4/gateop_perm;gopLUT5 +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N85[3]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -185283,7 +185259,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N106_6/gateop_perm;gopLUT5 +u_axi_ddr_top/wr_sta_fsm[3:0]_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -185293,23 +185269,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N106_10/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N85[5]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N106_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -185319,52 +185289,34 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1169/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N85[7]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N85[10]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N85[9]/gateop_perm;gopLUT5 @@ -185377,7 +185329,7 @@ L3;1 L4;1 Inst -u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N252/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -185387,7 +185339,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N85[8]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N106_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -185397,7 +185349,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N106_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N212/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -185407,56 +185359,56 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N85[8]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N106_8/gateop_perm;gopLUT5 +u_axi_ddr_top/wr_sta_reg[1]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N106_10/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[1]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N167.eq_0/gateop_A2;gopA2 @@ -185948,7 +185900,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -186099,37 +186051,55 @@ I14;1 RS;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N75[4]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N106_2/gateop_perm;gopLUT5 +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N75[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N96_6/gateop_perm;gopLUT5 +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N75[3]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -186139,7 +186109,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -186171,7 +186141,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -186187,43 +186157,40 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N75[8]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N75[5]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N150.eq_4/gateop_perm;gopA +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N232_1/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0;gopQ @@ -186471,7 +186438,7 @@ I14;1 RS;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -186487,7 +186454,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -186503,30 +186470,30 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N75[1]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q @@ -186545,23 +186512,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -186577,20 +186538,14 @@ L4;1 RS;1 Inst -u_axi_ddr_top/rd3_data_valid0/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm;gopL5Q @@ -186609,14 +186564,20 @@ L4;1 RS;1 Inst -u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0;gopQ @@ -186729,7 +186690,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N96_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -186739,7 +186700,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N75[6]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -186749,7 +186710,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N24_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -186759,7 +186720,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -186769,23 +186730,30 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N24_7/gateop_perm;gopLUT5 +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N147.eq_4/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + +Inst +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -186795,7 +186763,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N96_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -186805,23 +186773,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N96_2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N24_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -186831,7 +186793,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N276_5/gateop_perm;gopLUT5 +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N24_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -186841,30 +186803,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N24_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N147.eq_4/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N24_3/gateop_perm;gopLUT5 +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N154_mux6_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -186884,7 +186839,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -186894,7 +186849,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N75[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N75[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -186904,7 +186859,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N75[3]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N96_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -186914,17 +186869,36 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N106_6/gateop_perm;gopLUT5 +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N150.eq_4/gateop_perm;gopA Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + +Inst +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q +Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N75[5]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -186934,7 +186908,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N75[6]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N232_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -186944,7 +186918,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -186960,7 +186934,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N75[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N75[8]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -186970,7 +186944,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N96_4/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1201/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -186980,7 +186954,7 @@ L3;1 L4;1 Inst -u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[6]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1200/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -186990,23 +186964,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N276_5/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -187022,30 +186990,14 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N96_8/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N75[7]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N147.eq_0/gateop_A2;gopA2 @@ -187088,14 +187040,20 @@ I13;1 I14;1 Inst -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N154_mux6_6/gateop_perm;gopLUT5 +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N150.eq_0/gateop_A2;gopA2 @@ -187138,17 +187096,23 @@ I13;1 I14;1 Inst -u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/N296_9/gateop_perm;gopLUT5 +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -187178,20 +187142,14 @@ I13;1 I14;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N543[3]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0;gopQ @@ -187636,7 +187594,7 @@ WEA;1 WEB;1 Inst -u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -187646,23 +187604,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N12[4]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -187682,27 +187634,39 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[193]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[192]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N12[5]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N12[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -187712,14 +187676,20 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[3]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5 @@ -187732,46 +187702,33 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_dqs_req/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N25.eq_4/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N12[3]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[5]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_ba[1]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_cas_n[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -187787,7 +187744,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_cas_n/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_bank[3]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -187803,7 +187760,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N373_1_or[0][2]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N12[3]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -187813,27 +187770,39 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[128]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N406_3[0]_1/gateop_perm;gopLUT5 +u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N12[7]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -187853,7 +187822,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/init_start/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[10]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -187869,7 +187838,23 @@ L4;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_ba[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[196]/opit_0_inv_L5Q_perm;gopL5Q +Pin +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 + +Inst +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[96]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -187985,7 +187970,7 @@ I13;1 I14;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N758_77/gateop_perm;gopLUT5 +u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -188152,7 +188137,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N238/gateop_perm;gopLUT5 +u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N12[5]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -190371,17 +190356,23 @@ WR_EOP;1 WR_ERR;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/N1/gateop_perm;gopLUT5 +u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/N180_5/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N144_ac2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -190402,7 +190393,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/wr_sta_reg[1]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/wr_sta_reg[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -190418,7 +190409,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/wr_sta_reg[2]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_cmd_act/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -190434,23 +190425,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/wr_sta_reg[3]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[0]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/N48/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -190476,7 +190461,7 @@ L4;1 RS;1 Inst -u_ddr_addr_ctr/N73_5/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_16_10/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -190508,7 +190493,7 @@ D;1 RS;1 Inst -image_filiter_inst2/multiline_buffer_inst/N229_8/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_16_26/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -190540,7 +190525,7 @@ D;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/N142_mux4_3/gateop_perm;gopLUT5 +u_ddr_addr_ctr/N72_16/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -190550,7 +190535,7 @@ L3;1 L4;1 Inst -u_ddr_addr_ctr/N69_10/gateop_perm;gopLUT5 +u_ddr_addr_ctr/N76_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -190560,7 +190545,7 @@ L3;1 L4;1 Inst -u_ddr_addr_ctr/vs_30hz/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/gmii_txd_valid/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -190592,30 +190577,23 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_b/N107.lt_2/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -u_ddr_addr_ctr/N69_2/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cnt[3]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -image_filiter_inst2/multiline_buffer_inst/N93_mux7_12/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N619_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -190868,34 +190846,7 @@ I14;1 RS;1 Inst -u_ddr_addr_ctr/clk_cnt[20]/opit_0_A2Q21;gopA2Q2 -Pin -CEOUT;2 -Cout;2 -Q0;2 -Q1;2 -RSOUT;2 -Y0;2 -Y1;2 -CE;1 -CLK;1 -Cin;1 -I0X;1 -I1X;1 -I00;1 -I01;1 -I02;1 -I03;1 -I04;1 -I10;1 -I11;1 -I12;1 -I13;1 -I14;1 -RS;1 - -Inst -u_ddr_addr_ctr/clk_cnt[21]/opit_0_AQ;gopAQ +u_ddr_addr_ctr/clk_cnt[19]/opit_0_AQ;gopAQ Pin CEOUT;2 Cout;2 @@ -190925,7 +190876,7 @@ D;1 RS;1 Inst -u_ddr_addr_ctr/u_rd0_addr_ctr/N20_9/gateop_perm;gopLUT5 +u_ddr_addr_ctr/u_rd0_addr_ctr/N152_inv/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -190945,7 +190896,7 @@ L3;1 L4;1 Inst -u_hdm_in_rst/rst/opit_0_L5Q_perm;gopL5Q +u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -190977,20 +190928,14 @@ L4;1 RS;1 Inst -u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_vary0/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[1].mcdq_tfaw/N12_mux4/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_ddr_addr_ctr/u_rd0_addr_ctr/image_perimt0/opit_0;gopQ @@ -191047,23 +190992,17 @@ L4;1 RS;1 Inst -u_ddr_addr_ctr/vs_15hz/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/N294_12/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/N866_2_and[24][0]_1/gateop_perm;gopLUT5 +u_axi_ddr_top/N400_mux15_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -191316,7 +191255,7 @@ I14;1 RS;1 Inst -u_rotate_image/N131_mux1/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/N574_9[11]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -191348,7 +191287,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/N866_2_and[38][1]/gateop_perm;gopLUT5 +u_ddr_addr_ctr/u_rd0_addr_ctr/N20_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -191358,42 +191297,54 @@ L3;1 L4;1 Inst -u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[0]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_wr_connect/N294_13/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[7]/opit_0_AQ_perm;gopAQ +u_hdmi_in_top/N46/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[2]/opit_0_A2Q21;gopA2Q2 Pin CEOUT;2 Cout;2 -Q;2 +Q0;2 +Q1;2 RSOUT;2 -Y;2 +Y0;2 +Y1;2 CE;1 CLK;1 Cin;1 -I0;1 I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +I1X;1 +I00;1 +I01;1 +I02;1 +I03;1 +I04;1 +I10;1 +I11;1 +I12;1 +I13;1 +I14;1 RS;1 Inst -u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[2]/opit_0_A2Q21;gopA2Q2 +u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[4]/opit_0_A2Q21;gopA2Q2 Pin CEOUT;2 Cout;2 @@ -191420,7 +191371,7 @@ I14;1 RS;1 Inst -u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[4]/opit_0_A2Q21;gopA2Q2 +u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[6]/opit_0_A2Q21;gopA2Q2 Pin CEOUT;2 Cout;2 @@ -191447,42 +191398,24 @@ I14;1 RS;1 Inst -u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[6]/opit_0_A2Q21;gopA2Q2 +u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[7]/opit_0_AQ;gopAQ Pin CEOUT;2 Cout;2 -Q0;2 -Q1;2 +Q;2 RSOUT;2 -Y0;2 -Y1;2 +Y;2 CE;1 CLK;1 Cin;1 +I0;1 I0X;1 -I1X;1 -I00;1 -I01;1 -I02;1 -I03;1 -I04;1 -I10;1 -I11;1 -I12;1 -I13;1 -I14;1 +I1;1 +I2;1 +I3;1 +I4;1 RS;1 -Inst -u_axi_ddr_top/N866_2_and[25][0]_1/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - Inst u_ddr_addr_ctr/u_rd0_addr_ctr/wr_image_cnt0[0]/opit_0;gopQ Pin @@ -191539,7 +191472,7 @@ D;1 RS;1 Inst -u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_valid1/opit_0_L5Q_perm;gopL5Q +u_ddr_addr_ctr/u_rd1_addr_ctr/delay_cnt[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -191555,7 +191488,7 @@ L4;1 RS;1 Inst -u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 +u_ddr_addr_ctr/u_rd1_addr_ctr/N16/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -191565,36 +191498,33 @@ L3;1 L4;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[5]/opit_0_L5Q_perm;gopL5Q +u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_AQ_perm;gopAQ Pin CEOUT;2 +Cout;2 Q;2 RSOUT;2 -Z;2 +Y;2 CE;1 CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 RS;1 Inst -u_ddr_addr_ctr/u_rd1_addr_ctr/delay_cnt[0]/opit_0_L5Q_perm;gopL5Q +u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N12[3]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_valid0/opit_0_inv_L5Q_perm;gopL5Q @@ -191645,14 +191575,20 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N68_10_1/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/rd_sta_reg[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_ddr_addr_ctr/u_rd1_addr_ctr/gen_start_addr3[19]/opit_0;gopQ @@ -192006,17 +191942,14 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N15.lt_2/gateop_perm;gopA +u_rotate_image/rotate_sta_fsm[2:0]_1/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst u_ddr_addr_ctr/u_rd1_addr_ctr/rd3_image_cnt[0]/opit_0;gopQ @@ -192232,17 +192165,20 @@ L4;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N83.lt_2/gateop_perm;gopA +vs_down_delay_cnt[1]/opit_0_L5Q_perm;gopL5Q Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 Inst u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_done0/opit_0;gopQ @@ -192278,30 +192214,24 @@ D;1 RS;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/N8.lt_2/gateop_perm;gopA +u_ov5640/u_mix_image/N417/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/N87.lt_2/gateop_perm;gopA +u_ov5640/u_mix_image/rd_sta_fsm[4:0]_5/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst u_ddr_addr_ctr/u_rd1_addr_ctr/rd_vs0/opit_0;gopQ @@ -192326,7 +192256,7 @@ D;1 RS;1 Inst -u_ddr_addr_ctr/u_rd1_addr_ctr/N206/gateop_perm;gopLUT5 +u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -192336,7 +192266,7 @@ L3;1 L4;1 Inst -u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5 +u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -192346,43 +192276,34 @@ L3;1 L4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/N4.lt_2/gateop_perm;gopA +u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/N109.lt_2/gateop_perm;gopA +u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N8.lt_2/gateop_perm;gopA +u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N12[8]/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5 @@ -192395,7 +192316,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5 +u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -192405,7 +192326,7 @@ L3;1 L4;1 Inst -u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N3[6]/gateop;gopLUT5 +u_ddr_addr_ctr/u_rd1_addr_ctr/N206/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -192415,7 +192336,7 @@ L3;1 L4;1 Inst -u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N12[4]/gateop_perm;gopLUT5 +u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -192425,7 +192346,7 @@ L3;1 L4;1 Inst -u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N12[6]/gateop_perm;gopLUT5 +u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N12[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -192435,7 +192356,7 @@ L3;1 L4;1 Inst -u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N12[1]/gateop_perm;gopLUT5 +u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N12[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -192445,7 +192366,7 @@ L3;1 L4;1 Inst -u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N12[2]/gateop_perm;gopLUT5 +u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N12[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -192455,7 +192376,7 @@ L3;1 L4;1 Inst -u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N12[3]/gateop_perm;gopLUT5 +u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N12[5]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -192465,7 +192386,7 @@ L3;1 L4;1 Inst -u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N12[5]/gateop_perm;gopLUT5 +u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -192475,26 +192396,23 @@ L3;1 L4;1 Inst -u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_AQ_perm;gopAQ +u_ov5640/u_mix_image/data_out1[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 -Cout;2 Q;2 RSOUT;2 -Y;2 +Z;2 CE;1 CLK;1 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N12[0]/gateop_perm;gopLUT5 +u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N12[7]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -192504,7 +192422,7 @@ L3;1 L4;1 Inst -u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N12[7]/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/N427/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -192514,7 +192432,7 @@ L3;1 L4;1 Inst -u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 +u_ddr_addr_ctr/u_rd1_addr_ctr/N259/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -192524,14 +192442,20 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5 +u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_valid1/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N24.eq_0/gateop_A2;gopA2 @@ -192717,7 +192641,7 @@ L4;1 RS;1 Inst -u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N12[8]/gateop_perm;gopLUT5 +u_ddr_addr_ctr/u_rd1_addr_ctr/N271_inv/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -193120,17 +193044,23 @@ D;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N55_11_1/gateop_perm;gopLUT5 +u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_image_fram_cnt1[1]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/rd1_ddr_done1/opit_0_L5Q_perm;gopL5Q +u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_image_fram_cnt1[0]/opit_0_L5Q;gopL5Q Pin CEOUT;2 Q;2 @@ -193162,7 +193092,7 @@ L4;1 RS;1 Inst -u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[19]/opit_0_L5Q_perm;gopL5Q +u_hdmi_in_top/hs_cnt[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -193188,7 +193118,7 @@ L3;1 L4;1 Inst -image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[0]/gateop_perm;gopLUT5 +u_ddr_addr_ctr/u_rd3_addr_ctr/N44_mux4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -193208,17 +193138,14 @@ L3;1 L4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/N35.lt_2/gateop_perm;gopA +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/N12_mux4/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst u_ddr_addr_ctr/u_rd3_addr_ctr/N56_1_1/gateop_A2;gopA2 @@ -193779,20 +193706,14 @@ D;1 RS;1 Inst -u_rotate_image/image_blank_valid/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/N69_mux6/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr2[21]/opit_0;gopQ @@ -194591,20 +194512,23 @@ L4;1 RS;1 Inst -u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/N0.eq_2/gateop_perm;gopA +u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[18]/opit_0_L5Q_perm;gopL5Q Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 Inst -u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[11]/opit_0_L5Q_perm;gopL5Q +u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[14]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -194652,7 +194576,7 @@ L4;1 RS;1 Inst -u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[14]/opit_0_L5Q_perm;gopL5Q +u_ddr_addr_ctr/u_rd3_addr_ctr/rd_vs_rise0/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -194668,7 +194592,7 @@ L4;1 RS;1 Inst -u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[18]/opit_0_L5Q_perm;gopL5Q +u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[15]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -194684,7 +194608,7 @@ L4;1 RS;1 Inst -u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[21]/opit_0_L5Q_perm;gopL5Q +u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[16]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -194716,7 +194640,7 @@ L4;1 RS;1 Inst -u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[19]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -194732,7 +194656,7 @@ L4;1 RS;1 Inst -u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[15]/opit_0_L5Q_perm;gopL5Q +u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[22]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -194764,17 +194688,23 @@ L4;1 RS;1 Inst -u_ddr_addr_ctr/u_wr0_addr_ctr/N130_inv/gateop_perm;gopLUT5 +u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[21]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[22]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -194790,7 +194720,7 @@ L4;1 RS;1 Inst -u_ddr_addr_ctr/u_wr0_addr_ctr/N7/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/N25_mux5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -195159,7 +195089,7 @@ D;1 RS;1 Inst -u_ddr_addr_ctr/u_rd3_addr_ctr/rd_image_cnt[2]/opit_0_L5Q_perm;gopL5Q +u_ddr_addr_ctr/u_rd3_addr_ctr/rd_image_cnt[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -195175,7 +195105,7 @@ L4;1 RS;1 Inst -u_ddr_addr_ctr/u_rd3_addr_ctr/rd_vs_rise0/opit_0_L5Q_perm;gopL5Q +u_ddr_addr_ctr/u_rd3_addr_ctr/rd_image_cnt[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -195223,7 +195153,7 @@ L4;1 RS;1 Inst -u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_vary0/opit_0_L5Q_perm;gopL5Q +u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[11]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -195261,7 +195191,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/delay_cnt3[0]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -195297,7 +195227,7 @@ I13;1 I14;1 Inst -u_ddr_addr_ctr/u_rd0_addr_ctr/image_perimt/opit_0_L5Q_perm;gopL5Q +u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_vary0/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -195478,7 +195408,7 @@ D;1 RS;1 Inst -u_ddr_addr_ctr/u_wr0_addr_ctr/image_fram_cnt0[1]/opit_0_L5Q_perm;gopL5Q +u_ddr_addr_ctr/u_rd3_addr_ctr/rd_image_cnt[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -195549,17 +195479,23 @@ D;1 RS;1 Inst -u_ddr_addr_ctr/u_wr0_addr_ctr/N108/gateop_perm;gopLUT5 +u_ddr_addr_ctr/u_wr1_addr_ctr/image_fram_cnt1[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_ddr_addr_ctr/u_wr0_addr_ctr/wr_sta_reg[0]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/rd1_ddr_done1/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -195575,7 +195511,7 @@ L4;1 RS;1 Inst -u_ddr_addr_ctr/u_wr0_addr_ctr/wr_addr_valid0/opit_0_L5Q_perm;gopL5Q +u_ddr_addr_ctr/u_wr3_addr_ctr/wr_addr_valid0/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -195639,23 +195575,17 @@ L4;1 RS;1 Inst -u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[0]/opit_0_L5Q_perm;gopL5Q +u_ddr_addr_ctr/u_wr1_addr_ctr/N7/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_ddr_addr_ctr/u_wr0_addr_ctr/image_fram_cnt0[2]/opit_0_L5Q_perm;gopL5Q +u_ddr_addr_ctr/u_wr0_addr_ctr/image_fram_cnt0[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -195671,17 +195601,23 @@ L4;1 RS;1 Inst -u_ddr_addr_ctr/u_wr1_addr_ctr/N132/gateop_perm;gopLUT5 +u_ddr_addr_ctr/u_wr0_addr_ctr/image_fram_cnt0[3]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_ddr_addr_ctr/u_wr0_addr_ctr/image_fram_cnt0[3]/opit_0_L5Q_perm;gopL5Q +u_ddr_addr_ctr/u_rd0_addr_ctr/image_perimt/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -195713,7 +195649,7 @@ L4;1 RS;1 Inst -u_ddr_addr_ctr/u_wr0_addr_ctr/delay_cnt[0]/opit_0_L5Q_perm;gopL5Q +u_ddr_addr_ctr/u_wr1_addr_ctr/image_fram_cnt1[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -195729,14 +195665,20 @@ L4;1 RS;1 Inst -u_ddr_addr_ctr/u_wr1_addr_ctr/N7/gateop_perm;gopLUT5 +u_ddr_addr_ctr/u_wr0_addr_ctr/wr_sta_reg[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_ddr_addr_ctr/u_wr0_addr_ctr/wr_ddr_addr0[19]/opit_0;gopQ @@ -195827,7 +195769,7 @@ D;1 RS;1 Inst -u_ddr_addr_ctr/u_wr0_addr_ctr/wr_sta_reg[1]/opit_0_L5Q_perm;gopL5Q +u_ddr_addr_ctr/u_wr0_addr_ctr/wr_sta_reg[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -195843,7 +195785,7 @@ L4;1 RS;1 Inst -u_ddr_addr_ctr/u_wr0_addr_ctr/wr_sta_reg[2]/opit_0_L5Q_perm;gopL5Q +vs_pos_delay_cnt[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -195908,7 +195850,7 @@ D;1 RS;1 Inst -u_ddr_addr_ctr/u_wr0_addr_ctr/image_fram_cnt0[0]/opit_0_L5Q_perm;gopL5Q +u_ddr_addr_ctr/u_wr0_addr_ctr/image_fram_cnt0[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -195924,17 +195866,36 @@ L4;1 RS;1 Inst -u_ddr_addr_ctr/u_wr1_addr_ctr/N130_inv/gateop_perm;gopLUT5 +u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/N0.eq_2/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + +Inst +u_axi_ddr_top/u_axi_rd_connect/rd1_fifo_full0/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_ddr_addr_ctr/u_wr1_addr_ctr/wr_addr_valid0/opit_0_L5Q_perm;gopL5Q +u_ddr_addr_ctr/u_wr0_addr_ctr/image_fram_cnt0[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -195950,20 +195911,7 @@ L4;1 RS;1 Inst -u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/N0.eq_2/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[1]/opit_0_L5Q_perm;gopL5Q +u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[0]/opit_0_L5Q;gopL5Q Pin CEOUT;2 Q;2 @@ -196011,23 +195959,17 @@ L4;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_done0/opit_0_L5Q_perm;gopL5Q +u_ddr_addr_ctr/u_wr1_addr_ctr/N130_inv/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_ddr_addr_ctr/u_wr1_addr_ctr/image_fram_cnt1[0]/opit_0_L5Q;gopL5Q +u_ddr_addr_ctr/u_wr1_addr_ctr/image_fram_cnt1[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -196075,7 +196017,7 @@ L4;1 RS;1 Inst -u_axi_ddr_top/N866_2_or[1]/gateop_perm;gopLUT5 +u_ddr_addr_ctr/u_wr1_addr_ctr/N132/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -196085,20 +196027,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/rx1_addr_valid/opit_0_L5Q_perm;gopL5Q +u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/N0.eq_2/gateop_perm;gopA Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/N0.eq_0/gateop_A2;gopA2 @@ -196121,7 +196060,7 @@ I13;1 I14;1 Inst -u_ddr_addr_ctr/u_wr1_addr_ctr/image_fram_cnt1[1]/opit_0_L5Q_perm;gopL5Q +u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_vary0/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -196357,17 +196296,23 @@ D;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/N574_7_1/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[1].mcdq_tfaw/timing_cnt[1]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_ddr_addr_ctr/u_wr3_addr_ctr/wr_sta_fsm[1:0]_16/gateop_perm;gopLUT5 +N104_mux11_12/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -196546,7 +196491,7 @@ D;1 RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/delay_cnt1[2:0]_e/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/N39_0_ac4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -196556,23 +196501,17 @@ L3;1 L4;1 Inst -u_ddr_addr_ctr/u_wr3_addr_ctr/wr_addr_valid0/opit_0_L5Q_perm;gopL5Q +u_ddr_addr_ctr/u_wr3_addr_ctr/N103/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_ddr_addr_ctr/u_wr3_addr_ctr/image_fram_cnt0[0]/opit_0_L5Q_perm;gopL5Q +u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -196588,20 +196527,14 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/opit_0_L5Q_perm;gopL5Q +u_ddr_addr_ctr/u_wr3_addr_ctr/wr_sta_fsm[1:0]_16/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_ddr_addr_ctr/u_wr3_addr_ctr/delay_cnt[1]/opit_0_L5Q_perm;gopL5Q @@ -196652,14 +196585,20 @@ L4;1 RS;1 Inst -u_ddr_addr_ctr/u_wr3_addr_ctr/N108/gateop_perm;gopLUT5 +u_ddr_addr_ctr/u_wr0_addr_ctr/delay_cnt[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_ddr_addr_ctr/u_wr3_addr_ctr/image_fram_cnt0[1]/opit_0_L5Q_perm;gopL5Q @@ -196694,7 +196633,7 @@ L4;1 RS;1 Inst -u_ddr_addr_ctr/u_rd0_addr_ctr/rd0_sta_reg[0]/opit_0_L5Q_perm;gopL5Q +u_ddr_addr_ctr/u_wr3_addr_ctr/delay_cnt[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -196792,7 +196731,7 @@ D;1 RS;1 Inst -u_ddr_addr_ctr/u_wr3_addr_ctr/N103/gateop_perm;gopLUT5 +u_ddr_addr_ctr/u_wr0_addr_ctr/N130_inv/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -196834,14 +196773,20 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N68_14_1/gateop_perm;gopLUT5 +u_ddr_addr_ctr/vs_15hz/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_ddr_addr_ctr/u_wr3_addr_ctr/wr_vs0/opit_0;gopQ @@ -196877,7 +196822,7 @@ D;1 RS;1 Inst -u_ddr_addr_ctr/u_wr3_addr_ctr/wr_sta_reg[0]/opit_0_L5Q_perm;gopL5Q +u_ddr_addr_ctr/u_wr0_addr_ctr/wr_addr_valid0/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -196893,20 +196838,23 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N5.lt_2/gateop_perm;gopA +u_axi_ddr_top/u_axi_wr_connect/ddr1_valid_fall0/opit_0_L5Q_perm;gopL5Q Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 Inst -image_filiter_inst2/multiline_buffer_inst/N229_9/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1039_26[0]_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -196916,7 +196864,7 @@ L3;1 L4;1 Inst -udp_wr_mem_inst/N464/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N436_11_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -196948,7 +196896,7 @@ D;1 RS;1 Inst -u_ddr_addr_ctr/u_rd1_addr_ctr/N271_inv/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N195_40/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -196958,7 +196906,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/N866_2_or[2]/gateop_perm;gopLUT5 +u_ov5640/coms1_reg_config/u1/N25[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -196990,23 +196938,17 @@ D;1 RS;1 Inst -image_filiter_inst/vector_to_matrix_inst/mat[0][0][1]/opit_0_L5Q_perm;gopL5Q +N299_11/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5 +u_hdmi_in_top/N55/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -197268,7 +197210,7 @@ L4;1 RS;1 Inst -image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/delay_cnt3[2:0]_e/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -197575,7 +197517,7 @@ D;1 RS;1 Inst -u_hdmi_in_top/N55/gateop_perm;gopLUT5 +u_ddr_addr_ctr/u_wr0_addr_ctr/N108/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -197585,27 +197527,36 @@ L3;1 L4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/N83.lt_2/gateop_perm;gopA +vs_pos_delay_cnt[1]/opit_0_L5Q_perm;gopL5Q Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 Inst -u_hdmi_in_top/N46/gateop_perm;gopLUT5 +u_ddr_addr_ctr/u_wr3_addr_ctr/wr_sta_reg[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_hdmi_in_top/hs_cnt[1]/opit_0_L5Q;gopL5Q @@ -197910,23 +197861,17 @@ D;1 RS;1 Inst -u_hdmi_rst/rst/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N183/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_sync_vg/N50_mux2_7/gateop_perm;gopLUT5 +param_manager_inst/param_offsetX/N154_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -198228,14 +198173,20 @@ L4;1 RS;1 Inst -u_ov5640/u_mix_image/N1/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/cnt0_h[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_ov5640/cmos1_8_16bit/pdata_i0[0]/opit_0;gopQ @@ -198744,7 +198695,7 @@ D;1 RS;1 Inst -u_ov5640/cmos2_8_16bit/de_cnt/opit_0_L5Q;gopL5Q +u_ov5640/cmos2_8_16bit/image_data_valid0/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -199496,7 +199447,7 @@ D;1 RS;1 Inst -u_ov5640/coms1_reg_config/N26_mux2/gateop_perm;gopLUT5 +u_ov5640/coms1_reg_config/N8_mux7_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -199506,7 +199457,7 @@ L3;1 L4;1 Inst -u_ov5640/coms2_reg_config/N12/gateop_perm;gopLUT5 +u_ov5640/coms1_reg_config/N8_mux10/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -199516,7 +199467,7 @@ L3;1 L4;1 Inst -u_ov5640/coms2_reg_config/N8_mux4_5/gateop_perm;gopLUT5 +u_ov5640/coms1_reg_config/N1114[0]_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -199626,7 +199577,7 @@ I13;1 I14;1 Inst -u_ov5640/coms1_reg_config/N1114[0]_1/gateop_perm;gopLUT5 +u_ov5640/coms2_reg_config/N1114[0]_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -199636,23 +199587,17 @@ L3;1 L4;1 Inst -u_ov5640/coms1_reg_config/reg_index[0]/opit_0_inv_L5Q_perm;gopL5Q +u_ov5640/coms1_reg_config/N26_mux6_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_ov5640/coms1_reg_config/u1/N267_21/gateop_perm;gopLUT5 +u_ov5640/coms1_reg_config/u1/N8_mux3_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -199662,30 +199607,30 @@ L3;1 L4;1 Inst -u_ov5640/coms1_reg_config/N8_mux7_3/gateop_perm;gopLUT5 +u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/data_vary0/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_ov5640/coms1_reg_config/u1/cyc_count[0]/opit_0_inv_L5Q_perm;gopL5Q +u_ov5640/coms1_reg_config/u1/N239/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_ov5640/coms1_reg_config/N1169/gateop_perm;gopLUT5 @@ -199698,7 +199643,7 @@ L3;1 L4;1 Inst -u_ov5640/coms1_reg_config/N1193_3/gateop_perm;gopLUT5 +u_ov5640/coms1_reg_config/u1/N267_35/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -199708,7 +199653,7 @@ L3;1 L4;1 Inst -u_ov5640/coms2_reg_config/u1/N25[0]/gateop_perm;gopLUT5 +u_ov5640/coms1_reg_config/u1/N267_21/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -200155,7 +200100,7 @@ WR_EOP;1 WR_ERR;1 Inst -u_ov5640/coms1_reg_config/N12/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -200273,7 +200218,7 @@ I14;1 RS;1 Inst -u_ov5640/coms1_reg_config/u1/tr_end/opit_0_inv_L5Q_perm;gopL5Q +u_ov5640/coms1_reg_config/u1/sclk/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -200289,7 +200234,7 @@ L4;1 RS;1 Inst -u_ov5640/coms1_reg_config/u1/N25[0]/gateop_perm;gopLUT5 +u_ov5640/coms1_reg_config/N1134_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -200309,7 +200254,7 @@ L3;1 L4;1 Inst -u_ov5640/coms1_reg_config/u1/N256_2_2/gateop_perm;gopLUT5 +u_ov5640/coms1_reg_config/u1/N195_inv/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -200319,7 +200264,7 @@ L3;1 L4;1 Inst -u_ov5640/coms1_reg_config/u1/N256_4/gateop_perm;gopLUT5 +u_ov5640/coms1_reg_config/u1/N256_2_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -200339,7 +200284,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_offsetY/N150_1/gateop_perm;gopLUT5 +u_ov5640/coms1_reg_config/u1/N256_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -200349,7 +200294,7 @@ L3;1 L4;1 Inst -u_ov5640/coms1_reg_config/u1/N256_3/gateop_perm;gopLUT5 +u_ov5640/coms1_reg_config/N1134/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -200359,7 +200304,7 @@ L3;1 L4;1 Inst -u_ov5640/coms1_reg_config/u1/sclk/opit_0_inv_L5Q_perm;gopL5Q +u_ov5640/coms1_reg_config/reg_conf_done_reg/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -200375,14 +200320,20 @@ L4;1 RS;1 Inst -u_ov5640/coms1_reg_config/N1134/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/cnt0_w[8]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_ov5640/coms1_reg_config/u1/N262_46_3/gateop;gopMUX4TO1 @@ -200396,14 +200347,20 @@ S0;1 S1;1 Inst -u_ov5640/coms2_reg_config/u1/N195_inv/gateop_perm;gopLUT5 +u_ov5640/coms1_reg_config/u1/tr_end/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_ov5640/coms1_reg_config/u1/N267_18_muxf7;gopMUX16TO1 @@ -200441,14 +200398,20 @@ S20;1 S21;1 Inst -u_ov5640/coms1_reg_config/N1134_1/gateop_perm;gopLUT5 +u_ov5640/coms1_reg_config/u1/cyc_count[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_ov5640/coms1_reg_config/u1/N267_24/gateop;gopMUX4TO1 @@ -200473,20 +200436,14 @@ S0;1 S1;1 Inst -u_ov5640/coms1_reg_config/reg_conf_done_reg/opit_0_inv_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_ov5640/coms1_reg_config/u1/N267_36/gateop;gopMUX4TO1 @@ -200573,14 +200530,20 @@ I14;1 RS;1 Inst -u_ov5640/coms2_reg_config/u1/N146_8/gateop_perm;gopLUT5 +u_ov5640/cmos1_8_16bit/de_cnt/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q @@ -200600,7 +200563,7 @@ S0;1 S1;1 Inst -u_ov5640/power_on_delay_inst/N15_mux15_4/gateop_perm;gopLUT5 +u_ov5640/coms1_reg_config/N26_mux2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -200610,14 +200573,20 @@ L3;1 L4;1 Inst -u_ov5640/coms2_reg_config/u1/N8_mux3_1/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/image1_en/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_ov5640/coms2_reg_config/N8_mux7_3/gateop_perm;gopLUT5 @@ -200640,7 +200609,7 @@ L3;1 L4;1 Inst -u_ov5640/coms2_reg_config/N1114[0]_1/gateop_perm;gopLUT5 +u_ov5640/coms2_reg_config/N12/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -200750,7 +200719,7 @@ I13;1 I14;1 Inst -u_ov5640/coms2_reg_config/reg_index[0]/opit_0_inv_L5Q_perm;gopL5Q +u_hdmi_in_top/hdmi_in_en/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -200776,7 +200745,7 @@ L3;1 L4;1 Inst -u_ov5640/coms2_reg_config/N1134/gateop_perm;gopLUT5 +u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N12[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -200786,23 +200755,17 @@ L3;1 L4;1 Inst -udp_osd_inst/char_buf_writer_inst/ram_addr[0]/opit_0_L5Q_perm;gopL5Q +u_ov5640/coms2_reg_config/N8_mux4_5/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_ov5640/coms2_reg_config/N1134_1/gateop_perm;gopLUT5 +u_ov5640/coms2_reg_config/u1/N195_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -200812,23 +200775,17 @@ L3;1 L4;1 Inst -u_ov5640/coms2_reg_config/reg_conf_done_reg/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_ov5640/coms2_reg_config/N1193_3/gateop_perm;gopLUT5 +u_ov5640/coms2_reg_config/N1169/gateop;gopLUT5 Pin Z;2 L0;1 @@ -200838,7 +200795,7 @@ L3;1 L4;1 Inst -u_ov5640/coms2_reg_config/u1/cyc_count[0]/opit_0_inv_L5Q_perm;gopL5Q +u_ov5640/coms2_reg_config/reg_conf_done_reg/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -201036,14 +200993,20 @@ D;1 RS;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_30/gateop_perm;gopLUT5 +u_ov5640/coms2_reg_config/start/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_ov5640/coms2_reg_config/reg_data/iGopDrm;gopDRM @@ -201285,20 +201248,14 @@ WR_EOP;1 WR_ERR;1 Inst -udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[1]/opit_0_L5Q_perm;gopL5Q +u_ov5640/coms2_reg_config/u1/N267_6/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_ov5640/coms2_reg_config/reg_index[2]/opit_0_inv_A2Q21;gopA2Q2 @@ -201409,7 +201366,7 @@ I14;1 RS;1 Inst -u_ov5640/coms2_reg_config/u1/sclk/opit_0_inv_L5Q_perm;gopL5Q +u_ov5640/coms2_reg_config/u1/tr_end/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -201425,7 +201382,7 @@ L4;1 RS;1 Inst -u_ov5640/coms2_reg_config/u1/N187_3/gateop_perm;gopLUT5 +u_ov5640/coms2_reg_config/u1/N25[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -201435,23 +201392,17 @@ L3;1 L4;1 Inst -u_ov5640/coms2_reg_config/start/opit_0_inv_L5Q_perm;gopL5Q +u_ov5640/coms2_reg_config/u1/N195_inv/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_ov5640/coms2_reg_config/u1/N256_2_3/gateop_perm;gopLUT5 +u_ov5640/coms2_reg_config/u1/N146_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -201461,7 +201412,7 @@ L3;1 L4;1 Inst -u_ov5640/coms2_reg_config/u1/N267_21/gateop_perm;gopLUT5 +u_ov5640/coms2_reg_config/u1/N267_35/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -201471,7 +201422,7 @@ L3;1 L4;1 Inst -u_ov5640/coms2_reg_config/u1/N195_1/gateop_perm;gopLUT5 +u_ov5640/coms2_reg_config/u1/N256_2_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -201481,7 +201432,7 @@ L3;1 L4;1 Inst -u_ov5640/coms2_reg_config/u1/N262_46_3/gateop_perm;gopLUT5 +u_ov5640/coms2_reg_config/u1/N256_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -201491,7 +201442,39 @@ L3;1 L4;1 Inst -u_ov5640/power_on_delay_inst/cnt2[0]/opit_0_L5Q_perm;gopL5Q +u_ov5640/coms2_reg_config/u1/N256_1_3/gateop;gopMUX4TO1 +Pin +F;2 +I0;1 +I1;1 +I2;1 +I3;1 +S0;1 +S1;1 + +Inst +u_ov5640/coms2_reg_config/u1/N262_47/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_ov5640/coms2_reg_config/u1/N256_3/gateop;gopMUX4TO1 +Pin +F;2 +I0;1 +I1;1 +I2;1 +I3;1 +S0;1 +S1;1 + +Inst +u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -201507,38 +201490,49 @@ L4;1 RS;1 Inst -u_ov5640/coms2_reg_config/u1/N256_9/gateop_perm;gopLUT5 +u_axi_ddr_top/cnt0_times[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_ov5640/coms2_reg_config/N1169/gateop_perm;gopLUT5 +u_ov5640/cmos2_8_16bit/de_cnt/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_ov5640/coms2_reg_config/u1/N262_46_2/gateop;gopMUX4TO1 +u_ov5640/coms2_reg_config/u1/N267_9/gateop_perm;gopLUT5 Pin -F;2 -I0;1 -I1;1 -I2;1 -I3;1 -S0;1 -S1;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst -u_ov5640/coms2_reg_config/N26_mux2/gateop_perm;gopLUT5 +u_ov5640/coms2_reg_config/N1193_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -201548,42 +201542,29 @@ L3;1 L4;1 Inst -u_ov5640/coms2_reg_config/u1/N267_18_muxf7;gopMUX16TO1 +u_ov5640/coms2_reg_config/u1/N267_13/gateop;gopMUX4TO1 Pin F;2 -Fother;2 -L6OUTA;2 -L6OUTB;2 I0;1 I1;1 I2;1 I3;1 -I4;1 -I5;1 -I6;1 -I7;1 -I8;1 -I9;1 -I10;1 -I11;1 -I12;1 -I13;1 -I14;1 -I15;1 -S3;1 -S00;1 -S01;1 -S02;1 -S03;1 -S10;1 -S11;1 -S12;1 -S13;1 -S20;1 -S21;1 +S0;1 +S1;1 Inst -u_ov5640/coms2_reg_config/u1/N267_35/gateop_perm;gopLUT5 +u_ov5640/coms2_reg_config/u1/N267_16/gateop;gopMUX4TO1 +Pin +F;2 +I0;1 +I1;1 +I2;1 +I3;1 +S0;1 +S1;1 + +Inst +u_ov5640/coms2_reg_config/N1134_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -201615,7 +201596,7 @@ S0;1 S1;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N581_21/gateop_perm;gopLUT5 +u_ov5640/coms2_reg_config/u1/N256_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -201625,34 +201606,34 @@ L3;1 L4;1 Inst -u_ov5640/coms2_reg_config/u1/N267_36/gateop;gopMUX4TO1 +u_ov5640/coms2_reg_config/u1/N267_37_muxf6;gopMUX8TO1 Pin F;2 +Y0;2 +Y1;2 I0;1 I1;1 I2;1 I3;1 -S0;1 -S1;1 +I4;1 +I5;1 +I6;1 +I7;1 +S2;1 +S00;1 +S01;1 +S10;1 +S11;1 Inst -u_ov5640/coms2_reg_config/u1/cyc_count[5]/opit_0_inv_AQ_perm;gopAQ +u_axi_ddr_top/N733_8/gateop_perm;gopLUT5 Pin -CEOUT;2 -Cout;2 -Q;2 -RSOUT;2 -Y;2 -CE;1 -CLK;1 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 -RS;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst u_ov5640/coms2_reg_config/u1/cyc_count[2]/opit_0_inv_A2Q21;gopA2Q2 @@ -201709,40 +201690,26 @@ I14;1 RS;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[0]/opit_0_L5Q_perm;gopL5Q -Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 - -Inst -u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q;gopMUX4TO1Q +u_ov5640/coms2_reg_config/u1/cyc_count[5]/opit_0_inv_AQ;gopAQ Pin CEOUT;2 -F;2 +Cout;2 Q;2 RSOUT;2 +Y;2 CE;1 CLK;1 +Cin;1 I0;1 +I0X;1 I1;1 I2;1 I3;1 +I4;1 RS;1 -S0;1 -S1;1 Inst -u_ov5640/coms2_reg_config/u1/tr_end/opit_0_inv_L5Q_perm;gopL5Q +u_ov5640/coms2_reg_config/u1/sclk/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -201758,7 +201725,17 @@ L4;1 RS;1 Inst -u_ov5640/coms2_reg_config/u1/N185/gateop_perm;gopLUT5 +u_ov5640/coms2_reg_config/N1134/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N12[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -201804,7 +201781,7 @@ L4;1 RS;1 Inst -u_ov5640/power_on_delay_inst/camera_pwnd_reg/opit_0_L5Q_perm;gopL5Q +u_ov5640/power_on_delay_inst/cnt1[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -201820,17 +201797,23 @@ L4;1 RS;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_11_or[0][0]/gateop_perm;gopLUT5 +u_ddr_addr_ctr/u_wr3_addr_ctr/image_fram_cnt0[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_ov5640/power_on_delay_inst/cnt1[0]/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/rd1_done_cnt[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -201846,14 +201829,20 @@ L4;1 RS;1 Inst -u_ov5640/power_on_delay_inst/N15_mux15_12/gateop_perm;gopLUT5 +u_ov5640/power_on_delay_inst/camera_pwnd_reg/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_ov5640/power_on_delay_inst/cnt1[2]/opit_0_inv_A2Q21;gopA2Q2 @@ -202099,7 +202088,7 @@ I14;1 RS;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N785_2/gateop_perm;gopLUT5 +u_ov5640/power_on_delay_inst/N15_mux15_12/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -202333,7 +202322,7 @@ L4;1 RS;1 Inst -u_ov5640/u_mix_image/N315_9/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/N315_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -202343,7 +202332,7 @@ L3;1 L4;1 Inst -u_ov5640/u_mix_image/N311_9/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N101_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -202353,14 +202342,20 @@ L3;1 L4;1 Inst -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N24_11/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_ov5640/u_mix_image/image2_en/opit_0_L5Q_perm;gopL5Q @@ -202379,7 +202374,7 @@ L4;1 RS;1 Inst -u_ov5640/u_mix_image/N82/gateop;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -202389,33 +202384,33 @@ L3;1 L4;1 Inst -u_ov5640/u_mix_image/N329_17/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/rd_h[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_ov5640/u_mix_image/rd_w[0]/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/N123_17/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_ov5640/u_mix_image/rd_h[0]/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/rd_sta_reg[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -202531,20 +202526,14 @@ I13;1 I14;1 Inst -u_ov5640/u_mix_image/cnt0_h[0]/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/N1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_ov5640/u_mix_image/N311_11/gateop_perm;gopLUT5 @@ -202557,23 +202546,17 @@ L3;1 L4;1 Inst -u_ov5640/u_mix_image/image1_en/opit_0_L5Q_perm;gopL5Q +N119_mux11_9/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_ov5640/u_mix_image/N315_11/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/N78_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -202583,7 +202566,7 @@ L3;1 L4;1 Inst -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/N315_11/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -202593,17 +202576,23 @@ L3;1 L4;1 Inst -u_ov5640/u_mix_image/N78_4/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/cnt1_w[8]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[4]/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/N329_16/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -202613,27 +202602,39 @@ L3;1 L4;1 Inst -u_ov5640/u_mix_image/N329_18/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/data_out1[2]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_ov5640/u_mix_image/N365_8/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/rd_w[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_ov5640/u_mix_image/N339_11/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/N339_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -202643,23 +202644,17 @@ L3;1 L4;1 Inst -vs_pos_delay_cnt[1]/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/N339_11/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_ov5640/u_mix_image/N123_7/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/N329_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -202669,7 +202664,7 @@ L3;1 L4;1 Inst -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[7]/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/N365_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -202679,7 +202674,7 @@ L3;1 L4;1 Inst -u_ov5640/u_mix_image/N427/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/N367_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -202689,17 +202684,23 @@ L3;1 L4;1 Inst -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[0]/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/data_out_valid0/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_ov5640/u_mix_image/N123_6/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/N329_17/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -202709,7 +202710,7 @@ L3;1 L4;1 Inst -u_ov5640/u_mix_image/N329_4/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/N339_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -202719,7 +202720,7 @@ L3;1 L4;1 Inst -u_ov5640/u_mix_image/N315_8/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N101_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -202729,7 +202730,7 @@ L3;1 L4;1 Inst -u_ov5640/u_mix_image/N64_4/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/N311_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -202888,36 +202889,24 @@ I14;1 RS;1 Inst -u_ov5640/cmos2_8_16bit/image_data_valid0/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N101_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/N31/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_ov5640/u_mix_image/cnt1_w[0]/opit_0_L5Q;gopL5Q @@ -203085,36 +203074,14 @@ I14;1 RS;1 Inst -image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[0]/opit_0_L5Q_perm;gopL5Q -Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 - -Inst -u_ov5640/u_mix_image/data_out1[1]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_ov5640/u_mix_image/data_out1[4]/opit_0_L5Q_perm;gopL5Q @@ -203133,23 +203100,7 @@ L4;1 RS;1 Inst -u_ov5640/u_mix_image/data_out1[3]/opit_0_L5Q_perm;gopL5Q -Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 - -Inst -u_ov5640/u_mix_image/data_out1[9]/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/data_out1[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -203165,7 +203116,7 @@ L4;1 RS;1 Inst -u_ov5640/u_mix_image/data_out1[13]/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/data_out1[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -203181,7 +203132,7 @@ L4;1 RS;1 Inst -u_ov5640/u_mix_image/data_out1[6]/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/data_out1[9]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -203213,7 +203164,7 @@ L4;1 RS;1 Inst -u_ov5640/u_mix_image/data_out1[14]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -203245,7 +203196,7 @@ L4;1 RS;1 Inst -u_ov5640/u_mix_image/data_out1[12]/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/data_out1[8]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -203261,7 +203212,7 @@ L4;1 RS;1 Inst -u_ov5640/u_mix_image/data_out1[11]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -203277,7 +203228,7 @@ L4;1 RS;1 Inst -u_ov5640/u_mix_image/data_out1[15]/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/data_out1[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -203293,7 +203244,7 @@ L4;1 RS;1 Inst -u_ov5640/u_mix_image/data_out1[8]/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/data_out1[15]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -203309,7 +203260,7 @@ L4;1 RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/data_out1[12]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -203325,27 +203276,39 @@ L4;1 RS;1 Inst -u_ddr_addr_ctr/u_rd3_addr_ctr/N34_mux3_3/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/data_out1[13]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_ov5640/u_mix_image/N365_1/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/data_out1[14]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/N365_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -203355,18 +203318,33 @@ L3;1 L4;1 Inst -u_ov5640/u_mix_image/data_out_valid1/opit_0;gopQ +u_ov5640/u_mix_image/data_out1[11]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 RSOUT;2 +Z;2 CE;1 CLK;1 -D;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 RS;1 Inst -u_ov5640/u_mix_image/data_vs/opit_0;gopQ +u_ov5640/u_mix_image/N123_14/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_ov5640/u_mix_image/data_out_valid1/opit_0;gopQ Pin CEOUT;2 Q;2 @@ -203377,26 +203355,18 @@ D;1 RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[10]/opit_0_inv_AQ_perm;gopAQ +u_ov5640/u_mix_image/data_vs/opit_0;gopQ Pin CEOUT;2 -Cout;2 Q;2 RSOUT;2 -Y;2 CE;1 CLK;1 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +D;1 RS;1 Inst -u_ov5640/u_mix_image/N31/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -203406,7 +203376,17 @@ L3;1 L4;1 Inst -u_ov5640/u_mix_image/rd_sta_reg[4]/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/N315_9/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_ov5640/u_mix_image/data_out1[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -203612,14 +203592,20 @@ D;1 RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N101_3/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/rd_w[1]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_ov5640/u_mix_image/rd_sta_reg[1]/opit_0_L5Q_perm;gopL5Q @@ -203654,7 +203640,7 @@ L4;1 RS;1 Inst -u_ov5640/u_mix_image/rd_sta_reg[3]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/dfi_init_complete/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -203670,17 +203656,23 @@ L4;1 RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[8]/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/rd_sta_reg[4]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -N104_mux11_11/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N85[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -203723,14 +203715,20 @@ D;1 RS;1 Inst -u_ov5640/u_mix_image/N123_9/gateop_perm;gopLUT5 +vs_down_delay_cnt[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_ov5640/u_mix_image/rd_w[5]/opit_0_L5Q_perm;gopL5Q @@ -203797,14 +203795,20 @@ L4;1 RS;1 Inst -u_ddr_addr_ctr/u_rd3_addr_ctr/N44_mux4/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/rd_w[7]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_ov5640/u_mix_image/rd_w[6]/opit_0_L5Q_perm;gopL5Q @@ -203823,7 +203827,7 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -203887,7 +203891,7 @@ L4;1 RS;1 Inst -u_ov5640/u_mix_image/N367_3/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/N123_15/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -203923,7 +203927,7 @@ I14;1 RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -204109,20 +204113,14 @@ L4;1 RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q @@ -204141,50 +204139,62 @@ L4;1 RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[4]/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[6]/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N101_5/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q @@ -204235,20 +204245,14 @@ L4;1 RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[7]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0;gopQ @@ -204526,14 +204530,36 @@ I4;1 RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm;gopL5Q +Pin +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 + +Inst +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5 @@ -204546,7 +204572,7 @@ L3;1 L4;1 Inst -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -204562,7 +204588,7 @@ L4;1 RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -204578,7 +204604,7 @@ L4;1 RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -204594,7 +204620,7 @@ L4;1 RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N101_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -204604,7 +204630,7 @@ L3;1 L4;1 Inst -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -204620,33 +204646,14 @@ L4;1 RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N157.eq_4/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N101_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm;gopL5Q @@ -204665,7 +204672,7 @@ L4;1 RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N24_1/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -204796,7 +204803,7 @@ D;1 RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/N68/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -204806,7 +204813,7 @@ L3;1 L4;1 Inst -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -204816,23 +204823,17 @@ L3;1 L4;1 Inst -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[3]_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N24_15/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -204842,7 +204843,7 @@ L3;1 L4;1 Inst -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -204852,7 +204853,7 @@ L3;1 L4;1 Inst -u_ov5640/u_mix_image/N339_8/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N24_15/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -204862,33 +204863,33 @@ L3;1 L4;1 Inst -u_ov5640/u_mix_image/N68/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_ov5640/u_mix_image/rd_w[1]/opit_0_L5Q_perm;gopL5Q +u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N12[6]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N24_3/gateop_perm;gopLUT5 +u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N12[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -204898,23 +204899,17 @@ L3;1 L4;1 Inst -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N24_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_ov5640/u_mix_image/N417/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N24_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -204924,7 +204919,7 @@ L3;1 L4;1 Inst -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N101_1/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N34_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -204934,7 +204929,7 @@ L3;1 L4;1 Inst -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N101_9/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N24_17/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -204944,17 +204939,23 @@ L3;1 L4;1 Inst -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N24_17/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/rd_vs_rise/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -204970,7 +204971,7 @@ L4;1 RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[1]/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N101_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -205000,7 +205001,7 @@ L3;1 L4;1 Inst -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[9]/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -205010,7 +205011,7 @@ L3;1 L4;1 Inst -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[5]/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[6]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -205020,7 +205021,7 @@ L3;1 L4;1 Inst -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -205036,7 +205037,7 @@ L4;1 RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[7]/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[8]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -205046,33 +205047,33 @@ L3;1 L4;1 Inst -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[9]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N101_7/gateop_perm;gopLUT5 +u_ddr_addr_ctr/u_rd1_addr_ctr/rd_vs_rise0/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[2]/gateop_perm;gopLUT5 +u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -205082,23 +205083,17 @@ L3;1 L4;1 Inst -u_ov5640/u_mix_image/rd_w[7]/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_ov5640/u_mix_image/data_out_valid0/opit_0_inv_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -205114,23 +205109,17 @@ L4;1 RS;1 Inst -u_ov5640/u_mix_image/rd_sta_reg[0]/opit_0_L5Q_perm;gopL5Q +u_ddr_addr_ctr/u_rd1_addr_ctr/N56/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_ov5640/u_mix_image/rd_sta_fsm[4:0]_5/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N101_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -205140,20 +205129,14 @@ L3;1 L4;1 Inst -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N101_5/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N157.eq_0/gateop_A2;gopA2 @@ -205196,20 +205179,14 @@ I13;1 I14;1 Inst -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N160.eq_0/gateop_A2;gopA2 @@ -205759,20 +205736,14 @@ I14;1 RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[7]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/opit_0_inv_A2Q21;gopA2Q2 @@ -205910,14 +205881,23 @@ I14;1 RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[6]/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[10]/opit_0_inv_AQ;gopAQ Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +CEOUT;2 +Cout;2 +Q;2 +RSOUT;2 +Y;2 +CE;1 +CLK;1 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 +RS;1 Inst u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm;gopL5Q @@ -205952,20 +205932,14 @@ L4;1 RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[1]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm;gopL5Q @@ -206000,7 +205974,7 @@ L4;1 RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[5]/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -206026,27 +206000,39 @@ L4;1 RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[8]/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[9]/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -206062,20 +206048,14 @@ L4;1 RS;1 Inst -u_ov5640/u_mix_image/data_out1[5]/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0;gopQ @@ -206334,7 +206314,7 @@ I14;1 RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N101_5/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[6]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -206344,14 +206324,20 @@ L3;1 L4;1 Inst -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm;gopL5Q @@ -206370,7 +206356,7 @@ L4;1 RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[3]/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -206396,33 +206382,33 @@ L4;1 RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[4]/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -206432,30 +206418,30 @@ L3;1 L4;1 Inst -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[0]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm;gopL5Q @@ -206474,14 +206460,17 @@ L4;1 RS;1 Inst -image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N157.eq_4/gateop_perm;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0;gopQ @@ -206605,7 +206594,7 @@ D;1 RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[3]_1/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -206634,6 +206623,68 @@ L2;1 L3;1 L4;1 +Inst +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[4]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[5]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q +Pin +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 + +Inst +u_ov5640/u_mix_image/N82/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q +Pin +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 + Inst u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N39_7/gateop_perm;gopLUT5 Pin @@ -206645,17 +206696,23 @@ L3;1 L4;1 Inst -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N54_1/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N54_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -206681,27 +206738,7 @@ L4;1 RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N54_7/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -image_filiter_inst/multiline_buffer_inst/N93_mux7_12/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N54_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -206711,7 +206748,7 @@ L3;1 L4;1 Inst -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -206727,7 +206764,7 @@ L4;1 RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -206742,26 +206779,6 @@ L3;1 L4;1 RS;1 -Inst -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N54_3/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N101_1/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - Inst u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N157.eq_4/gateop_perm;gopA Pin @@ -206776,17 +206793,7 @@ I3;1 I4;1 Inst -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[1]/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_ov5640/u_mix_image/data_out1[2]/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -206802,23 +206809,17 @@ L4;1 RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[3]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N101_9/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N101_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -206828,7 +206829,7 @@ L3;1 L4;1 Inst -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[5]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -206838,26 +206839,7 @@ L3;1 L4;1 Inst -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[10]/opit_0_inv_AQ_perm;gopAQ -Pin -CEOUT;2 -Cout;2 -Q;2 -RSOUT;2 -Y;2 -CE;1 -CLK;1 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 -RS;1 - -Inst -u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm;gopL5Q +u_ddr_addr_ctr/u_rd1_addr_ctr/rd1_sta_reg[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -206873,23 +206855,17 @@ L4;1 RS;1 Inst -u_ov5640/u_mix_image/data_out1[0]/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[1]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N101_7/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[8]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -206899,7 +206875,7 @@ L3;1 L4;1 Inst -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N101_3/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N80[9]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -206909,7 +206885,7 @@ L3;1 L4;1 Inst -u_hdmi_in_top/N3/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N54_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -206919,7 +206895,7 @@ L3;1 L4;1 Inst -u_hdmi_in_top/hs_cnt[0]/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -206935,39 +206911,37 @@ L4;1 RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N24_11/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N101_9/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm;gopL5Q +u_ov5640/u_mix_image/N64_4/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -207023,14 +206997,20 @@ I13;1 I14;1 Inst -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5 +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N160.eq_0/gateop_A2;gopA2 @@ -207554,23 +207534,17 @@ WR_EOP;1 WR_ERR;1 Inst -u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm;gopL5Q +u_rotate_image/N44_mux7_8/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_axi_ddr_top/u_axi_wr_connect/N574_9[4]/gateop_perm;gopLUT5 +u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -207580,7 +207554,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/N924_10/gateop_perm;gopLUT5 +u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[8]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -207590,17 +207564,23 @@ L3;1 L4;1 Inst -u_rotate_image/N52_mux10_3/gateop_perm;gopLUT5 +rstn_5s/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_rotate_image/N57_mux4_3/gateop_perm;gopLUT5 +u_rotate_image/N344_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -207610,7 +207590,7 @@ L3;1 L4;1 Inst -u_rotate_image/N296_8/gateop_perm;gopLUT5 +u_rotate_image/N344_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -207620,7 +207600,7 @@ L3;1 L4;1 Inst -u_rotate_image/N296_7/gateop_perm;gopLUT5 +u_rotate_image/N57_mux6_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -207640,20 +207620,7 @@ L3;1 L4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/N8.lt_2/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -u_rotate_image/image_w_blank_valid/opit_0_L5Q_perm;gopL5Q +u_rotate_image/cnt_w[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -207668,6 +207635,16 @@ L3;1 L4;1 RS;1 +Inst +u_hdm_in_rst/N0/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + Inst u_rotate_image/N131_mux9_6/gateop_perm;gopLUT5 Pin @@ -207679,7 +207656,7 @@ L3;1 L4;1 Inst -image_filiter_inst2/hybrid_filter_inst/N118_mux3_4/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N186/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -207689,39 +207666,27 @@ L3;1 L4;1 Inst -param_manager_inst/param_offsetY/value[0]/opit_0_L5Q_perm;gopL5Q +image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/N39_0_ac4/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_zoom_rst/rst/opit_0_L5Q_perm;gopL5Q +u_rotate_image/N144_mux13_7/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_sync_vg/vs_out0/opit_0_L5Q_perm;gopL5Q +image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -207737,23 +207702,17 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/opit_0_L5Q_perm;gopL5Q +u_rotate_image/N344_8/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_rotate_image/N296_9/gateop_perm;gopLUT5 +u_rotate_image/N350/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -207763,17 +207722,23 @@ L3;1 L4;1 Inst -u_rotate_image/N302/gateop_perm;gopLUT5 +clk_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_osd_char_height/N63_mux10_6/gateop_perm;gopLUT5 +u_rotate_image/N52_mux10_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -208129,17 +208094,14 @@ I4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/N107.lt_2/gateop_perm;gopA +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_16_18/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst u_rotate_image/cnt_h[2]/opit_0_A2Q21;gopA2Q2 @@ -208277,7 +208239,7 @@ I14;1 RS;1 Inst -param_manager_inst/param_offsetX/N76_mux4_5/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_17_18/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -208598,7 +208560,7 @@ D;1 RS;1 Inst -u_rotate_image/data_out_valid2/opit_0_L5Q_perm;gopL5Q +u_rotate_image/fifo_data_valid/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -208614,7 +208576,7 @@ L4;1 RS;1 Inst -u_rotate_image/fifo_data_valid/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -208833,20 +208795,14 @@ L4;1 RS;1 Inst -u_axi_ddr_top/rd0_cnt_num[0]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/N182_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_rotate_image/image_h_add0[7]/opit_0_A2Q1;gopA2Q1 @@ -209492,7 +209448,7 @@ D;1 RS;1 Inst -udp_osd_inst/char_osd_inst/pixels_shifter_inst/N23_mux3_4/gateop_perm;gopLUT5 +u_rotate_image/N144_mux13_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -210145,7 +210101,7 @@ D;1 RS;1 Inst -u_rotate_image/N131_mux9_5/gateop_perm;gopLUT5 +param_manager_inst/param_offsetX/N76_mux4_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -210562,20 +210518,14 @@ D;1 RS;1 Inst -u_axi_ddr_top/rd0_time_permit/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/N19_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_rotate_image/rd_sta_reg[0]/opit_0_MUX4TO1Q;gopMUX4TO1Q @@ -210612,7 +210562,7 @@ S0;1 S1;1 Inst -u_axi_ddr_top/N743_8/gateop_perm;gopLUT5 +u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -210622,7 +210572,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N323_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -210632,63 +210582,72 @@ L3;1 L4;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N8.lt_2/gateop_perm;gopA +u_rotate_image/rotate_sta_fsm[2:0]_9_2/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst -u_rotate_image/rotate_sta_fsm[2:0]_1/gateop_perm;gopLUT5 +u_rotate_image/rotate_sta_reg[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N17/gateop_perm;gopLUT5 +u_rotate_image/rotate_sta_reg[1]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/N85.lt_2/gateop_perm;gopA +u_rotate_image/rotate_sta_reg[2]/opit_0_L5Q_perm;gopL5Q Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N4.lt_2/gateop_perm;gopA +u_rotate_image/N52_mux6_7/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst u_rotate_image/u_rotate_mult0/N2/gopapm;gopAPM @@ -212803,7 +212762,7 @@ WEA;1 WEB;1 Inst -u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5 +u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -212813,7 +212772,7 @@ L3;1 L4;1 Inst -u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5 +u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -212823,7 +212782,7 @@ L3;1 L4;1 Inst -u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5 +u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -212833,7 +212792,7 @@ L3;1 L4;1 Inst -u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[1]/gateop_perm;gopLUT5 +u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -212843,7 +212802,7 @@ L3;1 L4;1 Inst -u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5 +u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -212853,23 +212812,17 @@ L3;1 L4;1 Inst -u_rotate_image/rd_ddr_addr_valid1/opit_0_L5Q_perm;gopL5Q +u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[1]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 +u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -212879,7 +212832,7 @@ L3;1 L4;1 Inst -u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N267_or[0]_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -212899,7 +212852,7 @@ L3;1 L4;1 Inst -u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N3[11]/gateop_perm;gopLUT5 +u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -212909,7 +212862,7 @@ L3;1 L4;1 Inst -u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[8]/gateop_perm;gopLUT5 +u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N3[11]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -212919,7 +212872,7 @@ L3;1 L4;1 Inst -u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[11]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/N28/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -212929,7 +212882,7 @@ L3;1 L4;1 Inst -u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[3]/gateop_perm;gopLUT5 +u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[5]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -212939,7 +212892,7 @@ L3;1 L4;1 Inst -u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[4]/gateop_perm;gopLUT5 +u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[7]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -212949,7 +212902,7 @@ L3;1 L4;1 Inst -u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5 +u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[3]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -212959,7 +212912,7 @@ L3;1 L4;1 Inst -u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[5]/gateop_perm;gopLUT5 +u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -212979,7 +212932,7 @@ L3;1 L4;1 Inst -u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[7]/gateop_perm;gopLUT5 +u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -212989,7 +212942,7 @@ L3;1 L4;1 Inst -u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 +u_rotate_image/N44_mux7_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -212999,14 +212952,20 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N85[5]/gateop_perm;gopLUT5 +u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[9]/gateop_perm;gopLUT5 @@ -213029,30 +212988,30 @@ L3;1 L4;1 Inst -u_axi_ddr_top/N928_7/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/wptr/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/cnt1_times[0]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_0/gateop_A2;gopA2 @@ -213812,7 +213771,7 @@ L3;1 L4;1 Inst -u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 +u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[3]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -213822,7 +213781,7 @@ L3;1 L4;1 Inst -u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5 +u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[9]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -213832,20 +213791,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N19.lt_2/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5 +u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -213855,23 +213801,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_wfull/opit_0_inv_L5Q_perm;gopL5Q +u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5 +u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -213881,7 +213821,7 @@ L3;1 L4;1 Inst -u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5 +u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -213891,17 +213831,23 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N3[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[1]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N10[0]/gateop_perm;gopLUT5 +u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[8]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -213911,7 +213857,7 @@ L3;1 L4;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_en/opit_0_inv_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -213927,7 +213873,7 @@ L4;1 RS;1 Inst -u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[2]/gateop_perm;gopLUT5 +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/N25_mux5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -213937,7 +213883,7 @@ L3;1 L4;1 Inst -u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[5]/gateop_perm;gopLUT5 +u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[0]/gateop;gopLUT5 Pin Z;2 L0;1 @@ -213947,7 +213893,7 @@ L3;1 L4;1 Inst -u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[3]/gateop_perm;gopLUT5 +u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -213957,7 +213903,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm;gopL5Q +u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[5]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -213973,7 +213929,7 @@ L4;1 RS;1 Inst -u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[8]/gateop_perm;gopLUT5 +u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[7]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -213983,7 +213939,7 @@ L3;1 L4;1 Inst -u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[10]/gateop_perm;gopLUT5 +u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[6]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -213993,20 +213949,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N161.eq_4/gateop_perm;gopA +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/N59_mux2/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -214022,7 +213975,7 @@ L4;1 RS;1 Inst -u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[9]/gateop_perm;gopLUT5 +u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[10]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -214032,23 +213985,17 @@ L3;1 L4;1 Inst -u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/N55_mux6/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -214284,17 +214231,14 @@ I14;1 RS;1 Inst -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N19.lt_2/gateop_perm;gopA +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/N91_0_2_3/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21;gopA2Q2 @@ -214690,7 +214634,7 @@ WR_EOP;1 WR_ERR;1 Inst -u_sync_vg/N56_mux5_2/gateop_perm;gopLUT5 +u_sync_vg/N3_mux10/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -214700,7 +214644,7 @@ L3;1 L4;1 Inst -u_sync_vg/N178_6/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/pixels_shifter_inst/N9_mux7_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -214750,27 +214694,36 @@ I13;1 I14;1 Inst -u_sync_vg/N54/gateop_perm;gopLUT5 +u_sync_vg/N23_1_9/gateop;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -u_sync_vg/N56_mux8_1/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_x[8]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_sync_vg/N56_mux6/gateop_perm;gopLUT5 +u_sync_vg/N50_mux2_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -214780,7 +214733,7 @@ L3;1 L4;1 Inst -u_sync_vg/v_count[2]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -214796,17 +214749,7 @@ L4;1 RS;1 Inst -u_sync_vg/N28_mux8_2/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_sync_vg/N50_mux4/gateop_perm;gopLUT5 +u_sync_vg/N50_mux3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -214816,7 +214759,7 @@ L3;1 L4;1 Inst -u_sync_vg/N50_mux9_7/gateop_perm;gopLUT5 +u_sync_vg/N56_mux6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -214826,7 +214769,7 @@ L3;1 L4;1 Inst -u_sync_vg/N50_mux2_3/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/pixels_shifter_inst/N137/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -214836,7 +214779,7 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/gateop_perm;gopLUT5 +u_sync_vg/N54/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -214846,7 +214789,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/ms7210_ctl/init_over/opit_0_inv_L5Q_perm;gopL5Q +u_sync_vg/pos_y[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -214862,7 +214805,7 @@ L4;1 RS;1 Inst -u_sync_vg/h_count[11:0]_or/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N873_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -214872,23 +214815,17 @@ L3;1 L4;1 Inst -u_sync_vg/hs_out0/opit_0_L5Q_perm;gopL5Q +u_sync_vg/N178_6/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_sync_vg/N3_mux10/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/pixels_shifter_inst/N23_mux3_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -214898,7 +214835,7 @@ L3;1 L4;1 Inst -udp_wr_mem_inst/N524_1/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/pixels_shifter_inst/N23_mux7_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -214908,34 +214845,65 @@ L3;1 L4;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[6]/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/dividend_kp[7]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_sync_vg/N145_5/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/pixels_shifter_inst/m_pixel_posX[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_sync_vg/N3_mux6_4/gateop_perm;gopLUT5 +u_sync_vg/v_count[1]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 + +Inst +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N522_11/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst u_sync_vg/N178_7/gateop_perm;gopLUT5 @@ -214948,17 +214916,23 @@ L3;1 L4;1 Inst -u_sync_vg/N178_9/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/row_cnt[1]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_rotate/N63_mux7_7/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/pixels_shifter_inst/s_ready_d_d[0]_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -214968,17 +214942,23 @@ L3;1 L4;1 Inst -ms72xx_ctl/ms7210_ctl/N36/gateop_perm;gopLUT5 +u_sync_vg/vs_out0/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -ms72xx_ctl/ms7210_ctl/N559_6/gateop_perm;gopLUT5 +udp_osd_inst/N69_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -215038,20 +215018,14 @@ D;1 RS;1 Inst -param_manager_inst/param_rotate/value[0]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N820_36[4]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_sync_vg/h_count[2]/opit_0_A2Q21;gopA2Q2 @@ -215189,14 +215163,23 @@ I14;1 RS;1 Inst -udp_osd_inst/char_osd_inst/pixels_shifter_inst/N9_mux7_7/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/pixels_shifter_inst/m_pixel_posX[10]/opit_0_AQ_perm;gopAQ Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +CEOUT;2 +Cout;2 +Q;2 +RSOUT;2 +Y;2 +CE;1 +CLK;1 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 +RS;1 Inst u_sync_vg/h_count[11]/opit_0_AQ;gopAQ @@ -215218,7 +215201,7 @@ I4;1 RS;1 Inst -u_sync_vg/hdmi_image_data0[5]/opit_0_L5Q_perm;gopL5Q +u_sync_vg/hdmi_image_data0[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -215234,7 +215217,7 @@ L4;1 RS;1 Inst -u_sync_vg/hdmi_image_data0[4]/opit_0_L5Q_perm;gopL5Q +u_sync_vg/hdmi_image_data0[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -215250,7 +215233,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/dividend_kp[12]/opit_0_L5Q_perm;gopL5Q +u_sync_vg/hdmi_image_data0[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -215266,7 +215249,7 @@ L4;1 RS;1 Inst -u_sync_vg/hdmi_image_data0[7]/opit_0_L5Q_perm;gopL5Q +u_sync_vg/hdmi_image_data0[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -215282,7 +215265,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q +u_sync_vg/hdmi_image_data0[13]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -215298,7 +215281,7 @@ L4;1 RS;1 Inst -u_sync_vg/hdmi_image_data0[12]/opit_0_L5Q_perm;gopL5Q +u_sync_vg/hdmi_image_data0[14]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -215314,23 +215297,17 @@ L4;1 RS;1 Inst -u_sync_vg/hdmi_image_data0[8]/opit_0_L5Q_perm;gopL5Q +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_18/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_sync_vg/hdmi_image_data0[2]/opit_0_L5Q_perm;gopL5Q +u_sync_vg/hdmi_image_data0[11]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -215346,7 +215323,7 @@ L4;1 RS;1 Inst -u_sync_vg/hdmi_image_data0[10]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/rgb_out[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -215362,7 +215339,7 @@ L4;1 RS;1 Inst -u_sync_vg/hdmi_image_data0[6]/opit_0_L5Q_perm;gopL5Q +u_sync_vg/hdmi_image_data0[15]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -215378,23 +215355,17 @@ L4;1 RS;1 Inst -u_sync_vg/hdmi_image_data0[14]/opit_0_L5Q_perm;gopL5Q +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_29/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_sync_vg/hdmi_image_data0[15]/opit_0_L5Q_perm;gopL5Q +u_sync_vg/hdmi_image_data0[12]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -215410,7 +215381,7 @@ L4;1 RS;1 Inst -param_manager_inst/key_debounce_key_right/cnt[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/med[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -215426,7 +215397,7 @@ L4;1 RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/addr_bus_rd_ce[0]/opit_0_L5Q_perm;gopL5Q +u_sync_vg/hdmi_image_data0[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -215442,7 +215413,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[7]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -215458,7 +215429,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[7]/opit_0_L5Q_perm;gopL5Q +u_sync_vg/hdmi_image_data0[8]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -215650,20 +215621,14 @@ D;1 RS;1 Inst -ms72xx_ctl/ms7210_ctl/addr[6]/opit_0_inv_L5Q_perm;gopL5Q +u_sync_vg/N178_9/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_sync_vg/hs_out1/opit_0;gopQ @@ -215710,20 +215675,14 @@ D;1 RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm;gopL5Q +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[12]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_sync_vg/pos_x[0]/opit_0;gopQ @@ -215759,20 +215718,14 @@ D;1 RS;1 Inst -param_manager_inst/rotate_load/opit_0_L5Q_perm;gopL5Q +u_sync_vg/N3_mux6_4/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_sync_vg/pos_x[5]/opit_0_A2Q21;gopA2Q2 @@ -215875,7 +215828,7 @@ I4;1 RS;1 Inst -u_sync_vg/pos_y[0]/opit_0_L5Q;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -216053,7 +216006,7 @@ L4;1 RS;1 Inst -u_sync_vg/v_count[7]/opit_0_L5Q_perm;gopL5Q +u_sync_vg/v_count[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -216069,7 +216022,7 @@ L4;1 RS;1 Inst -u_sync_vg/v_count[5]/opit_0_L5Q_perm;gopL5Q +u_sync_vg/v_count[9]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -216127,30 +216080,30 @@ L4;1 RS;1 Inst -u_rotate_image/N144_mux13_7/gateop_perm;gopLUT5 +u_sync_vg/v_count[7]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_sync_vg/v_count[9]/opit_0_L5Q_perm;gopL5Q +u_sync_vg/N50_mux9_8/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_sync_vg/v_count[8]/opit_0_A2Q1;gopA2Q1 @@ -216179,7 +216132,7 @@ I14;1 RS;1 Inst -u_sync_vg/v_count[1]/opit_0_L5Q_perm;gopL5Q +u_sync_vg/v_count[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -216195,14 +216148,20 @@ L4;1 RS;1 Inst -udp_osd_inst/N69_5/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/pixels_shifter_inst/m_pixel_valid/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_sync_vg/vs_out1/opit_0;gopQ @@ -216437,25 +216396,19 @@ I14;1 RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[10]/opit_0_L6Q_perm;gopL6Q +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[15]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 RSOUT;2 Z;2 -A0;1 -A1;1 -A2;1 -A3;1 -A4;1 -B0;1 -B1;1 -B2;1 -B3;1 -B4;1 CE;1 CLK;1 -M;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 RS;1 Inst @@ -216675,14 +216628,20 @@ I14;1 RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_22/gateop_perm;gopLUT5 +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm;gopL5Q @@ -216701,7 +216660,7 @@ L4;1 RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm;gopL5Q +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -216717,14 +216676,20 @@ L4;1 RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_30/gateop_perm;gopLUT5 +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[13]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm;gopL5Q @@ -216743,17 +216708,23 @@ L4;1 RS;1 Inst -param_manager_inst/key_debounce_key_right/N20_mux4_1/gateop_perm;gopLUT5 +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm;gopL5Q +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -216769,7 +216740,7 @@ L4;1 RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -216785,7 +216756,7 @@ L4;1 RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5 +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N126_22/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -216811,7 +216782,7 @@ L4;1 RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[14]/opit_0_L5Q_perm;gopL5Q +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[11]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -216827,7 +216798,7 @@ L4;1 RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[12]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -216843,30 +216814,30 @@ L4;1 RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[13]/opit_0_L5Q_perm;gopL5Q +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[14]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[12]/gateop_perm;gopLUT5 +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[14]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[15]/opit_0_L5Q_perm;gopL5Q @@ -216885,7 +216856,7 @@ L4;1 RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5 +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N126_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -217287,7 +217258,7 @@ I14;1 RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm;gopL5Q +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -217303,7 +217274,7 @@ L4;1 RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm;gopL5Q +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -217319,14 +217290,20 @@ L4;1 RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5 +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm;gopL5Q @@ -217345,7 +217322,7 @@ L4;1 RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm;gopL5Q +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -217377,7 +217354,7 @@ L4;1 RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[7]/gateop_perm;gopLUT5 +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -217403,14 +217380,20 @@ L4;1 RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5 +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm;gopL5Q @@ -217445,14 +217428,20 @@ L4;1 RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N126_7/gateop_perm;gopLUT5 +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[12]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[13]/opit_0_L5Q_perm;gopL5Q @@ -217487,36 +217476,24 @@ L4;1 RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[15]/opit_0_L5Q_perm;gopL5Q +N286_11/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[11]/opit_0_L5Q_perm;gopL5Q +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N126_2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0;gopQ @@ -217695,7 +217672,23 @@ D;1 RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm;gopL5Q +Pin +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 + +Inst +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -217715,7 +217708,7 @@ L3;1 L4;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5 +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -217725,7 +217718,17 @@ L3;1 L4;1 Inst -ms72xx_ctl/ms7200_ctl/dri_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +zoom_fifo_full/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -217741,7 +217744,7 @@ L4;1 RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[2]/gateop_perm;gopLUT5 +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -217751,7 +217754,7 @@ L3;1 L4;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_3/gateop_perm;gopLUT5 +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -217761,7 +217764,7 @@ L3;1 L4;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -217771,7 +217774,7 @@ L3;1 L4;1 Inst -u_zoom_image/data_out_valid1/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/dividend_kp[10]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -217787,7 +217790,7 @@ L4;1 RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_20/gateop_perm;gopLUT5 +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[11]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -217797,23 +217800,27 @@ L3;1 L4;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm;gopL5Q +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[14]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/med[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -217829,20 +217836,7 @@ L4;1 RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_13/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[12]/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/N6_mux7_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -217852,7 +217846,7 @@ L3;1 L4;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[14]/gateop_perm;gopLUT5 +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -217862,23 +217856,17 @@ L3;1 L4;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[12]/opit_0_L5Q_perm;gopL5Q +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_16/gateop_perm;gopLUT5 +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_26/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -217888,7 +217876,7 @@ L3;1 L4;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_18/gateop_perm;gopLUT5 +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_20/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -217898,7 +217886,7 @@ L3;1 L4;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_32/gateop_perm;gopLUT5 +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[10]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -217908,7 +217896,7 @@ L3;1 L4;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_26/gateop_perm;gopLUT5 +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[13]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -217918,23 +217906,17 @@ L3;1 L4;1 Inst -zoom_fifo_full/opit_0_L5Q_perm;gopL5Q +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[12]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[10]/gateop_perm;gopLUT5 +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[8]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -217944,7 +217926,7 @@ L3;1 L4;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[5]/gateop_perm;gopLUT5 +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_30/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -217954,7 +217936,7 @@ L3;1 L4;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_24/gateop_perm;gopLUT5 +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_28/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -217964,7 +217946,7 @@ L3;1 L4;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[0]/gateop_perm;gopLUT5 +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N126_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -217974,23 +217956,17 @@ L3;1 L4;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_32/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_29/gateop_perm;gopLUT5 +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N126_24/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -218000,7 +217976,7 @@ L3;1 L4;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_28/gateop_perm;gopLUT5 +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[3]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -218010,51 +217986,27 @@ L3;1 L4;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[6]/opit_0_L6Q_perm;gopL6Q +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_16/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -A0;1 -A1;1 -A2;1 -A3;1 -A4;1 -B0;1 -B1;1 -B2;1 -B3;1 -B4;1 -CE;1 -CLK;1 -M;1 -RS;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[5]/opit_0_L6Q_perm;gopL6Q +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[2]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -A0;1 -A1;1 -A2;1 -A3;1 -A4;1 -B0;1 -B1;1 -B2;1 -B3;1 -B4;1 -CE;1 -CLK;1 -M;1 -RS;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_9/gateop_perm;gopLUT5 +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N126_12/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -218064,33 +218016,33 @@ L3;1 L4;1 Inst -param_manager_inst/key_debounce_key_right/change/opit_0_L5Q_perm;gopL5Q +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[4]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[1]/gateop_perm;gopLUT5 +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[3]/gateop_perm;gopLUT5 +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[7]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -218100,7 +218052,7 @@ L3;1 L4;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[11]/gateop_perm;gopLUT5 +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_22/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -218110,17 +218062,23 @@ L3;1 L4;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[4]/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5 +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[11]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -218130,17 +218088,23 @@ L3;1 L4;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[11]/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm;gopL5Q +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -218156,7 +218120,7 @@ L4;1 RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/dividend_kp[8]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -218182,75 +218146,26 @@ L3;1 L4;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[9]/opit_0_L6Q_perm;gopL6Q -Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -A0;1 -A1;1 -A2;1 -A3;1 -A4;1 -B0;1 -B1;1 -B2;1 -B3;1 -B4;1 -CE;1 -CLK;1 -M;1 -RS;1 - -Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[12]/opit_0_AQ_perm;gopAQ Pin CEOUT;2 +Cout;2 Q;2 RSOUT;2 -Z;2 +Y;2 CE;1 CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[13]/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[14]/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[1]_1/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N126_4/gateop_perm;gopLUT5 +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N126_16/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -218260,17 +218175,23 @@ L3;1 L4;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[13]/gateop_perm;gopLUT5 +u_sync_vg/hdmi_image_data0[1]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N126_2/gateop_perm;gopLUT5 +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N126_14/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -218280,24 +218201,36 @@ L3;1 L4;1 Inst -param_manager_inst/param_filiter1_mode/key_debounce_inst2/N20_mux2/gateop_perm;gopLUT5 +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N126_14/gateop_perm;gopLUT5 +u_sync_vg/pixel_show_en1/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N126_20/gateop_perm;gopLUT5 @@ -218310,7 +218243,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[1].u_divider_step/dividend_kp[11]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -218326,7 +218259,7 @@ L4;1 RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N126_22/gateop_perm;gopLUT5 +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N126_25/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -218336,24 +218269,36 @@ L3;1 L4;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[8]/gateop_perm;gopLUT5 +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N126_16/gateop_perm;gopLUT5 +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[12]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.eq_0/gateop_A2;gopA2 @@ -218535,108 +218480,6 @@ I12;1 I13;1 I14;1 -Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_5/gateop_A2;gopA2 -Pin -Cout;2 -Y0;2 -Y1;2 -Cin;1 -I0X;1 -I1X;1 -I00;1 -I01;1 -I02;1 -I03;1 -I04;1 -I10;1 -I11;1 -I12;1 -I13;1 -I14;1 - -Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_7/gateop_A2;gopA2 -Pin -Cout;2 -Y0;2 -Y1;2 -Cin;1 -I0X;1 -I1X;1 -I00;1 -I01;1 -I02;1 -I03;1 -I04;1 -I10;1 -I11;1 -I12;1 -I13;1 -I14;1 - -Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_9/gateop_A2;gopA2 -Pin -Cout;2 -Y0;2 -Y1;2 -Cin;1 -I0X;1 -I1X;1 -I00;1 -I01;1 -I02;1 -I03;1 -I04;1 -I10;1 -I11;1 -I12;1 -I13;1 -I14;1 - -Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_11/gateop_A2;gopA2 -Pin -Cout;2 -Y0;2 -Y1;2 -Cin;1 -I0X;1 -I1X;1 -I00;1 -I01;1 -I02;1 -I03;1 -I04;1 -I10;1 -I11;1 -I12;1 -I13;1 -I14;1 - -Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[12]/opit_0_L6Q_perm;gopL6Q -Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -A0;1 -A1;1 -A2;1 -A3;1 -A4;1 -B0;1 -B1;1 -B2;1 -B3;1 -B4;1 -CE;1 -CLK;1 -M;1 -RS;1 - Inst u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0;gopQ Pin @@ -218814,120 +218657,127 @@ D;1 RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[7]/opit_0_L6Q_perm;gopL6Q +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[5]/opit_0_A2Q1;gopA2Q1 Pin CEOUT;2 +Cout;2 Q;2 RSOUT;2 -Z;2 -A0;1 -A1;1 -A2;1 -A3;1 -A4;1 -B0;1 -B1;1 -B2;1 -B3;1 -B4;1 +Y0;2 +Y1;2 CE;1 CLK;1 -M;1 +Cin;1 +I0X;1 +I1X;1 +I00;1 +I01;1 +I02;1 +I03;1 +I04;1 +I10;1 +I11;1 +I12;1 +I13;1 +I14;1 RS;1 Inst -param_manager_inst/key_debounce_key_restore/N88/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_27/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[8]/opit_0_L6Q;gopL6Q +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[7]/opit_0_A2Q21;gopA2Q2 Pin CEOUT;2 -Q;2 +Cout;2 +Q0;2 +Q1;2 RSOUT;2 -Z;2 -A0;1 -A1;1 -A2;1 -A3;1 -A4;1 -B0;1 -B1;1 -B2;1 -B3;1 -B4;1 +Y0;2 +Y1;2 CE;1 CLK;1 -M;1 +Cin;1 +I0X;1 +I1X;1 +I00;1 +I01;1 +I02;1 +I03;1 +I04;1 +I10;1 +I11;1 +I12;1 +I13;1 +I14;1 RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[11]/opit_0_L6Q_perm;gopL6Q +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[9]/opit_0_A2Q21;gopA2Q2 Pin CEOUT;2 -Q;2 +Cout;2 +Q0;2 +Q1;2 RSOUT;2 -Z;2 -A0;1 -A1;1 -A2;1 -A3;1 -A4;1 -B0;1 -B1;1 -B2;1 -B3;1 -B4;1 +Y0;2 +Y1;2 CE;1 CLK;1 -M;1 +Cin;1 +I0X;1 +I1X;1 +I00;1 +I01;1 +I02;1 +I03;1 +I04;1 +I10;1 +I11;1 +I12;1 +I13;1 +I14;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[2]/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[0]/gateop_perm;gopLUT5 +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[11]/opit_0_A2Q21;gopA2Q2 Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +CEOUT;2 +Cout;2 +Q0;2 +Q1;2 +RSOUT;2 +Y0;2 +Y1;2 +CE;1 +CLK;1 +Cin;1 +I0X;1 +I1X;1 +I00;1 +I01;1 +I02;1 +I03;1 +I04;1 +I10;1 +I11;1 +I12;1 +I13;1 +I14;1 +RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_2/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/dividend_kp[9]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[0]/opit_0;gopQ @@ -226754,20 +226604,14 @@ WR_EOP;1 WR_ERR;1 Inst -u_sync_vg/hdmi_image_data0[9]/opit_0_L5Q_perm;gopL5Q +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[13]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_zoom_image/N78_1_1/gateop_A2;gopA2 @@ -226890,23 +226734,17 @@ I13;1 I14;1 Inst -u_zoom_image/delay_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q +u_zoom_image/N131_mux8/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_zoom_image/N143_5/gateop_perm;gopLUT5 +u_zoom_image/N857_8[7]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -226916,7 +226754,7 @@ L3;1 L4;1 Inst -u_zoom_image/N731/gateop_perm;gopLUT5 +u_zoom_image/N135_mux9_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -226926,7 +226764,7 @@ L3;1 L4;1 Inst -u_zoom_image/N368_mux4/gateop_perm;gopLUT5 +u_zoom_image/N131_mux12_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -226936,7 +226774,7 @@ L3;1 L4;1 Inst -u_zoom_image/zoom_sta_fsm[6:0]_35_2/gateop_perm;gopLUT5 +u_zoom_image/N143_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -226946,7 +226784,7 @@ L3;1 L4;1 Inst -u_zoom_image/N131_mux4_3/gateop_perm;gopLUT5 +u_zoom_image/zoom_sta_fsm[6:0]_61/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -226956,17 +226794,23 @@ L3;1 L4;1 Inst -u_zoom_image/N204_1_sum1_7/gateop_perm;gopLUT5 +u_zoom_image/ram_ch[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_zoom_image/N368_mux9_4/gateop_perm;gopLUT5 +u_zoom_image/N198/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -226976,23 +226820,17 @@ L3;1 L4;1 Inst -u_zoom_image/no_need_rd_ddr/opit_0_inv_L5Q_perm;gopL5Q +u_zoom_image/N227_2_ab0/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_zoom_image/record_ram_valid/opit_0_L5Q_perm;gopL5Q +u_zoom_image/cnt_record_ram[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -227008,20 +226846,14 @@ L4;1 RS;1 Inst -u_zoom_image/cnt_record_ram[0]/opit_0_L5Q_perm;gopL5Q +u_zoom_image/ram_sta_fsm[3:0]_4/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_zoom_image/N227_2_sum2_4/gateop;gopMUX4TO1 @@ -227035,7 +226867,7 @@ S0;1 S1;1 Inst -u_zoom_image/N891/gateop_perm;gopLUT5 +u_zoom_image/N274_12/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -227045,7 +226877,7 @@ L3;1 L4;1 Inst -u_zoom_image/N238_0/gateop_perm;gopLUT5 +u_zoom_image/N290_10/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -227055,7 +226887,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[20]/opit_0_L5Q_perm;gopL5Q +u_zoom_image/cnt_w[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -227071,14 +226903,20 @@ L4;1 RS;1 Inst -u_zoom_image/N274_12/gateop_perm;gopLUT5 +udp_wr_mem_inst/flags[17]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_zoom_image/N244_1_1/gateop_A2;gopA2 @@ -227181,7 +227019,7 @@ I13;1 I14;1 Inst -u_zoom_image/wr_addr3[0]/opit_0_inv_L5Q_perm;gopL5Q +u_zoom_image/rd_addr[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -227197,17 +227035,23 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N961/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_zoom_image/ram_sta_fsm[3:0]_4/gateop_perm;gopLUT5 +u_zoom_image/ram_sta_fsm[3:0]_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -227217,7 +227061,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[1]/gateop_perm;gopLUT5 +u_zoom_image/N290_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -227227,17 +227071,23 @@ L3;1 L4;1 Inst -u_zoom_image/N290_10/gateop_perm;gopLUT5 +param_manager_inst/param_offsetX/value[1]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_zoom_image/ram_sta_fsm[3:0]_7/gateop_perm;gopLUT5 +u_zoom_image/N290_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -227247,17 +227097,23 @@ L3;1 L4;1 Inst -u_zoom_image/N306_11/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[5].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[3]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[6].u_divider_step/dividend_kp[8]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -227273,7 +227129,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N78/gateop_perm;gopLUT5 +u_zoom_image/N306_12/gateop;gopLUT5 Pin Z;2 L0;1 @@ -227283,7 +227139,7 @@ L3;1 L4;1 Inst -u_zoom_image/N322_12/gateop_perm;gopLUT5 +udp_wr_mem_inst/N549_25/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -227293,27 +227149,30 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N328_1.fsub_15/gateop_perm;gopA +u_zoom_image/N322_12/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst -u_zoom_image/N322_11/gateop_perm;gopLUT5 +udp_wr_mem_inst/data_count[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_zoom_image/N361_1_1/gateop_A2;gopA2 @@ -227449,7 +227308,7 @@ I3;1 I4;1 Inst -u_zoom_image/N131_mux12_5/gateop_perm;gopLUT5 +u_zoom_image/N370/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -227459,30 +227318,27 @@ L3;1 L4;1 Inst -u_zoom_image/N370/gateop_perm;gopLUT5 +u_zoom_image/N375.eq_6/gateop_perm;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -u_zoom_image/addr_sta_reg[4]/opit_0_L5Q_perm;gopL5Q +u_zoom_image/N368_mux9_4/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_zoom_image/N375.eq_0/gateop_A2;gopA2 @@ -227545,20 +227401,14 @@ I13;1 I14;1 Inst -u_zoom_image/imag_addr0[6]/opit_0_L5Q_perm;gopL5Q +u_zoom_image/N204_1_sum1_7/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_zoom_image/N383.eq_0/gateop_A2;gopA2 @@ -227621,17 +227471,20 @@ I13;1 I14;1 Inst -u_zoom_image/N383.eq_6/gateop;gopA +u_zoom_image/no_need_rd_ddr/opit_0_inv_L5Q_perm;gopL5Q Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 Inst u_zoom_image/N387_2_1/gateop_A2;gopA2 @@ -227727,17 +227580,23 @@ I3;1 I4;1 Inst -u_zoom_image/N322_9/gateop_perm;gopLUT5 +u_zoom_image/image_w_valid[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_zoom_image/N530_mux7_3/gateop_perm;gopLUT5 +u_zoom_image/N530_mux12_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -227747,30 +227606,30 @@ L3;1 L4;1 Inst -u_zoom_image/N530_mux12_3/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_zoom_image/rd_addr[0]/opit_0_L5Q_perm;gopL5Q +u_zoom_image/N709_11/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_zoom_image/N566_1.fsub_1/gateop_A2;gopA2 @@ -228099,7 +227958,7 @@ I13;1 I14;1 Inst -u_zoom_image/cnt_w[1]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -228115,33 +227974,33 @@ L4;1 RS;1 Inst -u_zoom_image/N709_11/gateop_perm;gopLUT5 +u_zoom_image/image_valid[0][0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_zoom_image/cnt_h[2]/opit_0_L5Q_perm;gopL5Q +u_zoom_image/N843/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_zoom_image/N857_8[3]/gateop_perm;gopLUT5 +u_zoom_image/N857_8[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -228151,7 +228010,7 @@ L3;1 L4;1 Inst -u_zoom_image/N857_8[7]/gateop_perm;gopLUT5 +u_zoom_image/N857_8[5]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -228161,7 +228020,7 @@ L3;1 L4;1 Inst -u_zoom_image/N857_8[6]/gateop_perm;gopLUT5 +u_zoom_image/N857_8[8]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -228171,7 +228030,7 @@ L3;1 L4;1 Inst -u_zoom_image/ram_ch[0]/opit_0_inv_L5Q_perm;gopL5Q +u_zoom_image/delay_cnt[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -228187,17 +228046,23 @@ L4;1 RS;1 Inst -u_zoom_image/zoom_sta_fsm[6:0]_9/gateop_perm;gopLUT5 +u_zoom_image/image_h_valid[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_zoom_image/zoom_sta_reg[3]/opit_0_L5Q_perm;gopL5Q +u_zoom_image/zoom_sta_reg[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -228213,7 +228078,7 @@ L4;1 RS;1 Inst -u_zoom_image/N857_8[2]/gateop_perm;gopLUT5 +u_zoom_image/N135_mux4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -228223,7 +228088,7 @@ L3;1 L4;1 Inst -u_zoom_image/N715_10/gateop_perm;gopLUT5 +u_zoom_image/N857_8[3]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -228233,7 +228098,7 @@ L3;1 L4;1 Inst -u_zoom_image/coe_valid[0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -228259,17 +228124,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_filiter1_mode/key_debounce_inst1/N89_5[2]/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_zoom_image/image_h0[6]/opit_0_L5Q_perm;gopL5Q +u_zoom_image/cnt_h[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -228285,7 +228140,7 @@ L4;1 RS;1 Inst -u_zoom_image/N857_8[8]/gateop_perm;gopLUT5 +u_zoom_image/N857_8[6]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -228295,7 +228150,7 @@ L3;1 L4;1 Inst -u_zoom_image/N857_8[9]/gateop_perm;gopLUT5 +u_zoom_image/N715_11/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -228305,7 +228160,7 @@ L3;1 L4;1 Inst -u_zoom_image/zoom_sta_reg[2]/opit_0_L5Q_perm;gopL5Q +u_zoom_image/cnt_h[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -228321,7 +228176,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[2]/gateop_perm;gopLUT5 +u_zoom_image/N857_8[9]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -228331,7 +228186,7 @@ L3;1 L4;1 Inst -u_zoom_image/cnt_h[7]/opit_0_L5Q_perm;gopL5Q +u_zoom_image/cnt_h[10]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -228347,17 +228202,7 @@ L4;1 RS;1 Inst -u_zoom_image/N843/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_zoom_image/wr_addr1[0]/opit_0_inv_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -228373,7 +228218,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N175_34/gateop_perm;gopLUT5 +u_zoom_image/zoom_sta_fsm[6:0]_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -228383,7 +228228,7 @@ L3;1 L4;1 Inst -u_zoom_image/addr_sta_reg[1]/opit_0_L5Q_perm;gopL5Q +u_zoom_image/wr_addr0[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -228399,7 +228244,7 @@ L4;1 RS;1 Inst -u_zoom_image/addr_sta_reg[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -228415,7 +228260,7 @@ L4;1 RS;1 Inst -u_zoom_image/addr_sta_reg[3]/opit_0_L5Q_perm;gopL5Q +u_zoom_image/addr_sta_reg[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -228431,27 +228276,39 @@ L4;1 RS;1 Inst -u_zoom_image/N198/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[12].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_zoom_image/N227_1_ab0/gateop_perm;gopLUT5 +u_zoom_image/addr_sta_reg[4]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_zoom_image/cnt_h[0]/opit_0_L5Q;gopL5Q +u_zoom_image/addr_sta_reg[3]/opit_0_L5Q;gopL5Q Pin CEOUT;2 Q;2 @@ -228467,7 +228324,17 @@ L4;1 RS;1 Inst -u_zoom_image/cnt_h[3]/opit_0_L5Q_perm;gopL5Q +u_zoom_image/N227_1_ab0/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_zoom_image/cnt_h[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -228483,7 +228350,7 @@ L4;1 RS;1 Inst -u_zoom_image/cnt_h[5]/opit_0_L5Q_perm;gopL5Q +u_zoom_image/cnt_h[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -228515,7 +228382,7 @@ L4;1 RS;1 Inst -u_zoom_image/cnt_h[10]/opit_0_L5Q_perm;gopL5Q +u_zoom_image/cnt_h[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -228531,23 +228398,17 @@ L4;1 RS;1 Inst -u_zoom_image/cnt_h[6]/opit_0_L5Q_perm;gopL5Q +u_zoom_image/N131_mux4_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_zoom_image/cnt_h[8]/opit_0_L5Q_perm;gopL5Q +u_zoom_image/cnt_h[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -228563,7 +228424,7 @@ L4;1 RS;1 Inst -u_zoom_image/cnt_h[9]/opit_0_L5Q_perm;gopL5Q +u_zoom_image/cnt_h[8]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -228579,7 +228440,7 @@ L4;1 RS;1 Inst -u_zoom_image/N274_9/gateop_perm;gopLUT5 +u_zoom_image/N715_10/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -228589,7 +228450,7 @@ L3;1 L4;1 Inst -u_zoom_image/image_h_valid[0]/opit_0_inv_L5Q_perm;gopL5Q +u_zoom_image/cnt_h[9]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -228604,6 +228465,16 @@ L3;1 L4;1 RS;1 +Inst +u_zoom_image/N731/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + Inst u_zoom_image/N857_8[10]/gateop_perm;gopLUT5 Pin @@ -228647,7 +228518,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_9/gateop_perm;gopLUT5 +u_zoom_image/N891/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -228657,33 +228528,33 @@ L3;1 L4;1 Inst -u_zoom_image/cnt_w[2]/opit_0_L5Q_perm;gopL5Q +u_zoom_image/N709_9/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_zoom_image/N709_9/gateop_perm;gopLUT5 +u_zoom_image/cnt_w[2]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_filiter1_mode/key_debounce_inst1/N87/gateop_perm;gopLUT5 +u_zoom_image/N515_mux1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -228801,7 +228672,7 @@ I14;1 RS;1 Inst -u_zoom_image/zoom_sta_reg[0]/opit_0_L5Q_perm;gopL5Q +u_zoom_image/image_valid[0][1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -229389,7 +229260,7 @@ D;1 RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/rgb_out[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -229448,14 +229319,20 @@ L4;1 RS;1 Inst -u_zoom_image/N135_mux4/gateop_perm;gopLUT5 +u_zoom_image/zoom_sta_reg[1]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_zoom_image/fifo_full0/opit_0;gopQ @@ -229501,14 +229378,20 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N703_1/gateop_perm;gopLUT5 +u_zoom_image/imag_addr0[5]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_zoom_image/imag_addr0[4]/opit_0_L5Q_perm;gopL5Q @@ -229527,7 +229410,7 @@ L4;1 RS;1 Inst -u_zoom_image/imag_addr0[5]/opit_0_L5Q_perm;gopL5Q +u_zoom_image/imag_addr0[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -229543,17 +229426,23 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[1]/gateop_perm;gopLUT5 +u_zoom_image/imag_addr0[8]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[0]/opit_0_L5Q_perm;gopL5Q +u_zoom_image/addr_sta_reg[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -229569,7 +229458,7 @@ L4;1 RS;1 Inst -u_zoom_image/imag_addr0[8]/opit_0_L5Q_perm;gopL5Q +u_zoom_image/imag_addr0[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -229601,14 +229490,20 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N357_4/gateop_perm;gopLUT5 +u_zoom_image/addr_sta_reg[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_zoom_image/imag_addr1[0]/opit_0;gopQ @@ -229644,7 +229539,7 @@ D;1 RS;1 Inst -u_zoom_image/imag_addr_valid0/opit_0_L5Q_perm;gopL5Q +u_zoom_image/wr_addr1[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -229741,14 +229636,20 @@ I14;1 RS;1 Inst -u_zoom_image/N919/gateop_perm;gopLUT5 +u_zoom_image/imag_addr_valid0/opit_0_L5Q;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_zoom_image/imag_addr_valid1/opit_0;gopQ @@ -229828,7 +229729,7 @@ D;1 RS;1 Inst -u_zoom_image/ram_idle/opit_0_L5Q_perm;gopL5Q +u_zoom_image/cnt_h[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -230800,7 +230701,7 @@ L4;1 RS;1 Inst -u_zoom_image/image_w_valid[0]/opit_0_inv_L5Q_perm;gopL5Q +u_zoom_image/cnt_w[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -230816,30 +230717,30 @@ L4;1 RS;1 Inst -u_zoom_image/image_valid[0][1]/opit_0_L5Q_perm;gopL5Q +u_zoom_image/N709_8/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -u_zoom_image/N515_mux1/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_zoom_image/image_valid[1][0]/opit_0;gopQ @@ -231653,7 +231554,7 @@ L4;1 RS;1 Inst -u_zoom_image/image_valid[0][0]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -232886,7 +232787,7 @@ I14;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N282/gateop_perm;gopLUT5 +u_zoom_image/N857_8[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -236988,20 +236889,14 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_en/opit_0_L5Q_perm;gopL5Q +u_zoom_image/N227_1_sum1_2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_zoom_image/ram_ch0[0]/opit_0;gopQ @@ -237086,20 +236981,14 @@ L4;1 RS;1 Inst -u_zoom_image/addr_sta_reg[0]/opit_0_L5Q_perm;gopL5Q +u_zoom_image/N858_inv/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_zoom_image/rd_one_ram/opit_0_L5Q_perm;gopL5Q @@ -237140,7 +237029,7 @@ D;1 RS;1 Inst -u_zoom_image/ram_sta_reg[2]/opit_0_L5Q_perm;gopL5Q +u_zoom_image/ram_sta_reg[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -237156,7 +237045,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[2]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -237188,29 +237077,23 @@ L4;1 RS;1 Inst -u_zoom_image/wr_ram_done/opit_0_L6Q_perm;gopL6Q +u_zoom_image/wr_ram_done/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 RSOUT;2 Z;2 -A0;1 -A1;1 -A2;1 -A3;1 -A4;1 -B0;1 -B1;1 -B2;1 -B3;1 -B4;1 CE;1 CLK;1 -M;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 RS;1 Inst -u_zoom_image/ram_sta_reg[3]/opit_0_L5Q_perm;gopL5Q +u_zoom_image/ram_sta_reg[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -237226,14 +237109,36 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[1]/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 + +Inst +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q +Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_zoom_image/rd_addr0[0]/opit_0;gopQ @@ -237346,7 +237251,7 @@ D;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N831_8/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N402_66/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -237520,7 +237425,7 @@ I14;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux3/gateop_perm;gopLUT5 +u_zoom_image/N274_11/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -238618,17 +238523,23 @@ S0;1 S1;1 Inst -u_zoom_image/N530_mux3_4/gateop_perm;gopLUT5 +u_zoom_image/record_ram_valid/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_zoom_image/N290_9/gateop_perm;gopLUT5 +u_zoom_image/N850_inv/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -239502,23 +239413,14 @@ Z[46];1 Z[47];1 Inst -u_zoom_image/mult_image2[1][12]/opit_0_AQ_perm;gopAQ +u_zoom_image/N232_0/gateop_perm;gopLUT5 Pin -CEOUT;2 -Cout;2 -Q;2 -RSOUT;2 -Y;2 -CE;1 -CLK;1 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 -RS;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst u_zoom_image/wr_addr0[2]/opit_0_A2Q21;gopA2Q2 @@ -239656,44 +239558,47 @@ I14;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N140_27/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_zoom_image/wr_addr1[2]/opit_0_inv_A2Q21;gopA2Q2 +param_manager_inst/param_offsetX/N151_10_11/gateop_perm;gopA Pin -CEOUT;2 Cout;2 -Q0;2 -Q1;2 -RSOUT;2 -Y0;2 -Y1;2 -CE;1 -CLK;1 +Y;2 Cin;1 +I0;1 I0X;1 -I1X;1 -I00;1 -I01;1 -I02;1 -I03;1 -I04;1 -I10;1 -I11;1 -I12;1 -I13;1 -I14;1 -RS;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -u_zoom_image/wr_addr1[4]/opit_0_inv_A2Q21;gopA2Q2 +u_zoom_image/wr_addr1[2]/opit_0_inv_A2Q21;gopA2Q2 +Pin +CEOUT;2 +Cout;2 +Q0;2 +Q1;2 +RSOUT;2 +Y0;2 +Y1;2 +CE;1 +CLK;1 +Cin;1 +I0X;1 +I1X;1 +I00;1 +I01;1 +I02;1 +I03;1 +I04;1 +I10;1 +I11;1 +I12;1 +I13;1 +I14;1 +RS;1 + +Inst +u_zoom_image/wr_addr1[4]/opit_0_inv_A2Q21;gopA2Q2 Pin CEOUT;2 Cout;2 @@ -239801,14 +239706,20 @@ I14;1 RS;1 Inst -u_ov5640/coms1_reg_config/u1/N256_2_4/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_zoom_image/wr_addr2[2]/opit_0_inv_A2Q21;gopA2Q2 @@ -239946,20 +239857,14 @@ I14;1 RS;1 Inst -u_zoom_image/ram_sta_reg[0]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N52/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst u_zoom_image/wr_addr3[2]/opit_0_inv_A2Q21;gopA2Q2 @@ -240097,14 +240002,20 @@ I14;1 RS;1 Inst -u_zoom_image/N274_11/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst u_zoom_image/zoom_num0[1]/opit_0;gopQ @@ -244129,27 +244040,39 @@ WR_EOP;1 WR_ERR;1 Inst -u_zoom_image/N715_11/gateop_perm;gopLUT5 +u_zoom_image/ram_idle/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_zoom_image/zoom_sta_fsm[6:0]_61/gateop_perm;gopLUT5 +u_zoom_image/coe_valid[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_zoom_image/N131_mux8/gateop_perm;gopLUT5 +u_zoom_image/zoom_sta_fsm[6:0]_35_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -244192,7 +244115,7 @@ D;1 RS;1 Inst -u_zoom_image/zoom_sta_reg[1]/opit_0_L5Q_perm;gopL5Q +u_zoom_image/zoom_sta_reg[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -244208,7 +244131,7 @@ L4;1 RS;1 Inst -u_zoom_image/zoom_sta_reg[4]/opit_0_L5Q_perm;gopL5Q +u_zoom_image/zoom_sta_reg[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -244224,17 +244147,23 @@ L4;1 RS;1 Inst -u_zoom_image/N227_2_ab0/gateop_perm;gopLUT5 +u_zoom_image/zoom_sta_reg[3]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_zoom_image/zoom_sta_reg[5]/opit_0_L5Q_perm;gopL5Q +u_zoom_image/zoom_sta_reg[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -244250,7 +244179,7 @@ L4;1 RS;1 Inst -u_zoom_image/zoom_sta_reg[6]/opit_0_L5Q_perm;gopL5Q +u_zoom_image/zoom_sta_reg[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -244266,7 +244195,7 @@ L4;1 RS;1 Inst -u_zoom_image/N857_8[0]/gateop_perm;gopLUT5 +u_zoom_image/N274_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -244276,7 +244205,7 @@ L3;1 L4;1 Inst -u_zoom_image/N857_8[5]/gateop_perm;gopLUT5 +u_zoom_image/N236_0/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -244286,7 +244215,7 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/pixels_shifter_inst/N6/gateop_perm;gopLUT5 +u_hdmi_rst/N0/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -244498,23 +244427,17 @@ I13;1 I14;1 Inst -udp_osd_inst/char_osd_inst/pixels_shifter_inst/m_pixel_valid/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/char_osd_inst/pixels_shifter_inst/N9_mux10/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/pixels_shifter_inst/N6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -244764,17 +244687,14 @@ I13;1 I14;1 Inst -udp_osd_inst/char_buf_writer_inst/N16.eq_8/gateop;gopA +udp_osd_inst/char_buf_writer_inst/N138_24/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst udp_osd_inst/char_buf_writer_inst/N87_1_0/gateop_A2;gopA2 @@ -244877,17 +244797,23 @@ I13;1 I14;1 Inst -udp_osd_inst/char_buf_writer_inst/N222/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[24]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/char_buf_writer_inst/N138_20/gateop_perm;gopLUT5 +udp_osd_inst/char_buf_writer_inst/N179_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -244907,7 +244833,7 @@ L3;1 L4;1 Inst -udp_osd_inst/char_buf_writer_inst/N138_26/gateop_perm;gopLUT5 +udp_osd_inst/char_buf_writer_inst/cnt[15:0]_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -244927,23 +244853,17 @@ L3;1 L4;1 Inst -udp_osd_inst/char_buf_writer_inst/udp_rx_s_data_tready/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1039_24[0]_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/char_buf_writer_inst/N230/gateop_perm;gopLUT5 +udp_osd_inst/char_buf_writer_inst/N170/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -244953,17 +244873,23 @@ L3;1 L4;1 Inst -udp_osd_inst/char_buf_writer_inst/N206_15/gateop_perm;gopLUT5 +udp_osd_inst/char_buf_writer_inst/cnt[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N120_3/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N296_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -244973,7 +244899,7 @@ L3;1 L4;1 Inst -udp_osd_inst/char_buf_writer_inst/N206_2/gateop_perm;gopLUT5 +udp_osd_inst/char_buf_writer_inst/N206_15/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -244983,14 +244909,20 @@ L3;1 L4;1 Inst -udp_osd_inst/char_buf_writer_inst/N179_5/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[6]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst udp_osd_inst/char_buf_writer_inst/N206_14_4/gateop;gopMUX4TO1 @@ -245014,39 +244946,27 @@ L3;1 L4;1 Inst -udp_osd_inst/char_buf_writer_inst/ram_din[1]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N75_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/char_buf_writer_inst/ram_addr[8]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N590_8/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/char_buf_writer_inst/cnt[0]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_buf_writer_inst/state_reg[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -245062,14 +244982,23 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N296_1/gateop_perm;gopLUT5 +udp_osd_inst/char_buf_writer_inst/cnt[15]/opit_0_AQ_perm;gopAQ Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +CEOUT;2 +Cout;2 +Q;2 +RSOUT;2 +Y;2 +CE;1 +CLK;1 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 +RS;1 Inst udp_osd_inst/char_buf_writer_inst/ram_din[0]/opit_0_L5Q_perm;gopL5Q @@ -245276,39 +245205,24 @@ I14;1 RS;1 Inst -udp_osd_inst/char_buf_writer_inst/cnt[15]/opit_0_AQ_perm;gopAQ +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N263/gateop_perm;gopLUT5 Pin -CEOUT;2 -Cout;2 -Q;2 -RSOUT;2 -Y;2 -CE;1 -CLK;1 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 -RS;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst -udp_osd_inst/char_buf_writer_inst/ram_din[5]/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/ms7200_ctl/N8_7/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst udp_osd_inst/char_buf_writer_inst/data_size[0]/opit_0;gopQ @@ -245487,7 +245401,7 @@ D;1 RS;1 Inst -udp_osd_inst/char_buf_writer_inst/ram_addr[1]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_buf_writer_inst/ram_addr[8]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -245535,7 +245449,7 @@ L4;1 RS;1 Inst -udp_osd_inst/char_buf_writer_inst/ram_addr[4]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_buf_writer_inst/ram_addr[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -245567,7 +245481,7 @@ L4;1 RS;1 Inst -udp_osd_inst/char_buf_writer_inst/ram_addr[6]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_buf_writer_inst/ram_addr[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -245583,7 +245497,7 @@ L4;1 RS;1 Inst -udp_osd_inst/char_buf_writer_inst/ram_addr[7]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_buf_writer_inst/ram_addr[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -245599,17 +245513,23 @@ L4;1 RS;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786/gateop_perm;gopLUT5 +udp_osd_inst/char_buf_writer_inst/ram_addr[9]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/char_buf_writer_inst/ram_addr[9]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_buf_writer_inst/ram_addr[10]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -245625,7 +245545,7 @@ L4;1 RS;1 Inst -udp_osd_inst/char_buf_writer_inst/ram_addr[10]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -245641,7 +245561,7 @@ L4;1 RS;1 Inst -udp_osd_inst/char_osd_inst/pixels_shifter_inst/N114_8/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N39_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -245651,7 +245571,7 @@ L3;1 L4;1 Inst -udp_osd_inst/char_buf_writer_inst/ram_din[2]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_buf_writer_inst/ram_din[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -245699,7 +245619,20 @@ L4;1 RS;1 Inst -udp_osd_inst/char_buf_writer_inst/ram_din[6]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_buf_writer_inst/N16.eq_8/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + +Inst +udp_osd_inst/char_buf_writer_inst/ram_din[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -245715,27 +245648,23 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7210_ctl/N124_5/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N140_25/gateop_perm;gopLUT5 +udp_osd_inst/char_buf_writer_inst/ram_din[7]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/char_buf_writer_inst/ram_din[7]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[12]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -245751,14 +245680,20 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7210_ctl/N62_sum3/gateop_perm;gopLUT5 +udp_osd_inst/char_buf_writer_inst/ram_din[6]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst udp_osd_inst/char_buf_writer_inst/ram_wen/opit_0_MUX4TO1Q;gopMUX4TO1Q @@ -245810,7 +245745,7 @@ L4;1 RS;1 Inst -udp_osd_inst/char_buf_writer_inst/N206_1/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N148_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -245820,7 +245755,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/iic_dri_tx/busy/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/change_to_read/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -245836,7 +245771,7 @@ L4;1 RS;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_11_and[10][0]/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N79/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -245926,14 +245861,20 @@ I13;1 I14;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_fsm[3:0]_3/gateop_perm;gopLUT5 +u_sync_vg/hdmi_image_data0[10]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst udp_osd_inst/char_osd_inst/char_buf_reader_inst/N72_1.fsub_1/gateop_A2;gopA2 @@ -246176,7 +246117,7 @@ I13;1 I14;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N358_5/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_fsm[3:0]_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -246186,7 +246127,7 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N97/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_fsm[3:0]_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -246196,20 +246137,14 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_valid/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N593/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst udp_osd_inst/char_osd_inst/char_buf_reader_inst/N228_1_1/gateop_A2;gopA2 @@ -246392,7 +246327,7 @@ I13;1 I14;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/row_cnt[0]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_valid/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -246408,23 +246343,17 @@ L4;1 RS;1 Inst -udp_osd_inst/char_osd_inst/pixels_shifter_inst/pixels_data[7]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N102_8/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N709_1/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N589_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -246534,7 +246463,7 @@ I13;1 I14;1 Inst -param_manager_inst/param_osd_startX/value[5]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_x[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -246650,7 +246579,7 @@ I13;1 I14;1 Inst -param_manager_inst/param_osd_startY/N148_5/gateop_perm;gopLUT5 +u_sync_vg/N56_mux5_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -246660,7 +246589,7 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N785_7_or[1]_3/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_fsm[3:0]_10/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -246670,7 +246599,7 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N581_23/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N861/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -246680,7 +246609,7 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N590_3/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -246690,7 +246619,7 @@ L3;1 L4;1 Inst -image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N3[1]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N229_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -246700,7 +246629,7 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N589_7/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N589_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -246710,7 +246639,7 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N590_9/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N590_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -246720,7 +246649,7 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N590_8/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_fsm[3:0]_52/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -246730,20 +246659,17 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N60.lt_6/gateop_perm;gopA +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N581_24/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N784_0/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_pic_rom_inst/N11_mux6_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -246753,7 +246679,7 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_fsm[3:0]_13_2/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N785_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -246763,7 +246689,7 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N832/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N785_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -246773,7 +246699,7 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N839/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_29/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -246783,7 +246709,7 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N709_5/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N186_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -246793,7 +246719,7 @@ L3;1 L4;1 Inst -image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[1]/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N358_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -246803,7 +246729,7 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N711_2/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N838_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -246813,7 +246739,7 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[10:0]_or_1/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N842/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -246823,23 +246749,17 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_reg[0]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N883_2/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N873_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -246849,7 +246769,7 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N785_7_or[3]_2/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N785_7_or[1]_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -246859,7 +246779,7 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_fsm[3:0]_10/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N785_7_or[3]_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -246869,7 +246789,7 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N564_2/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N597/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -246879,7 +246799,7 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N843_2/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N784_0/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -246889,7 +246809,7 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_29/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -246899,7 +246819,7 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N478/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N243_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -246909,7 +246829,7 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_fsm[3:0]_35/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N785_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -246919,7 +246839,7 @@ L3;1 L4;1 Inst -image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[9]/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N848/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -246929,7 +246849,7 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[1]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[8]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -246945,7 +246865,27 @@ L4;1 RS;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_15_2/gateop;gopMUX4TO1 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_11_or[0][0]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N883_2/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_15_3/gateop;gopMUX4TO1 Pin F;2 I0;1 @@ -246956,7 +246896,7 @@ S0;1 S1;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N883_6/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_30/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -246966,7 +246906,7 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/pixels_shifter_inst/pixels_data[0]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -246982,17 +246922,7 @@ L4;1 RS;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N683_7/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_fsm[3:0]_23_2/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_fsm[3:0]_13_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -247002,14 +246932,20 @@ L3;1 L4;1 Inst -u_rotate_image/N144_mux4/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[10]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst udp_osd_inst/char_osd_inst/char_buf_reader_inst/N862/gateop;gopMUX4TO1 @@ -247023,18 +246959,17 @@ S0;1 S1;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N873_1/gateop;gopMUX4TO1 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N564_2/gateop_perm;gopLUT5 Pin -F;2 -I0;1 -I1;1 -I2;1 -I3;1 -S0;1 -S1;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_15_3/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N684/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -247044,7 +246979,17 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N15/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N883_6/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N581_22/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -247263,7 +247208,7 @@ D;1 RS;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_x[2]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_x[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -247279,7 +247224,7 @@ L4;1 RS;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_x[3]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_x[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -247295,7 +247240,7 @@ L4;1 RS;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_x[5]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_x[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -247311,23 +247256,17 @@ L4;1 RS;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_x[4]/opit_0_L5Q_perm;gopL5Q +u_sync_vg/h_count[11:0]_or/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_x[8]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_x[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -247343,7 +247282,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_osd_char_width/value[0]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_x[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -247359,7 +247298,7 @@ L4;1 RS;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_x[7]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_x[10]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -247375,23 +247314,17 @@ L4;1 RS;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_x[9]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/pixels_shifter_inst/N18_mux7_7/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_x[6]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_x[9]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -247407,23 +247340,17 @@ L4;1 RS;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_x[10]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/pixels_shifter_inst/N18_mux10/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_wr_mem_inst/N44/gateop_perm;gopLUT5 +u_sync_vg/N28_mux8_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -247433,7 +247360,7 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_y[1]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_y[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -247449,7 +247376,7 @@ L4;1 RS;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_y[2]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_y[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -247465,7 +247392,7 @@ L4;1 RS;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_y[3]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_y[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -247480,16 +247407,6 @@ L3;1 L4;1 RS;1 -Inst -param_manager_inst/param_osd_startY/N63_mux10_6/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - Inst udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_y[5]/opit_0_L5Q_perm;gopL5Q Pin @@ -247507,7 +247424,7 @@ L4;1 RS;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_y[6]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_y[9]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -247539,17 +247456,23 @@ L4;1 RS;1 Inst -param_manager_inst/param_osd_startY/N139/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_y[10]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_y[9]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_y[8]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -247565,23 +247488,17 @@ L4;1 RS;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_y[10]/opit_0_L5Q_perm;gopL5Q +u_sync_vg/N145_5/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -param_manager_inst/param_osd_char_height/N139_1/gateop_perm;gopLUT5 +u_sync_vg/N59_mux6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -247591,7 +247508,7 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/char_pic_rom_inst/m_row_pixels_valid/opit_0_L5Q_perm;gopL5Q +u_sync_vg/hs_out0/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -247606,6 +247523,16 @@ L3;1 L4;1 RS;1 +Inst +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N464_2/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + Inst udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_width[0]/opit_0;gopQ Pin @@ -247806,17 +247733,23 @@ I14;1 RS;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N593/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[2]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[2]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -247832,7 +247765,7 @@ L4;1 RS;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[6]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -247864,7 +247797,7 @@ L4;1 RS;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[4]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -247880,17 +247813,7 @@ L4;1 RS;1 Inst -image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[8]/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[8]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -247922,20 +247845,27 @@ L4;1 RS;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[5]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 + +Inst +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N60.lt_6/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[9]/opit_0_L5Q_perm;gopL5Q @@ -247954,7 +247884,7 @@ L4;1 RS;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[10]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -247970,7 +247900,7 @@ L4;1 RS;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N861/gateop_perm;gopLUT5 +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -247980,7 +247910,7 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_fsm[3:0]_49/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N84_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -248038,7 +247968,7 @@ L4;1 RS;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N79/gateop_perm;gopLUT5 +u_sync_vg/N50_mux2_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -248411,27 +248341,23 @@ D;1 RS;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N597/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N589_5/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_reg[1]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_fsm[3:0]_13_3/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_fsm[3:0]_62/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -248441,7 +248367,7 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N848/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_11_and[10][0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -248451,7 +248377,7 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_fsm[3:0]_33_2/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_fsm[3:0]_23_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -248461,7 +248387,7 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_reg[4]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -248477,17 +248403,23 @@ L4;1 RS;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N379/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[3]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N79_cpy/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N843_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -248497,20 +248429,14 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_reg[1]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N102_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_reg[2]/opit_0_L5Q_perm;gopL5Q @@ -248545,7 +248471,7 @@ L4;1 RS;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[0]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_reg[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -248561,20 +248487,14 @@ L4;1 RS;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/row_cnt[1]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N679_2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst udp_osd_inst/char_osd_inst/char_buf_reader_inst/str_len[0]/opit_0;gopQ @@ -248763,24 +248683,36 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/char_pic_rom_inst/N58_maj7/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[4]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[10:0]_or_5/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[1]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/gateop_perm;gopLUT5 @@ -248793,20 +248725,14 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/pixels_shifter_inst/pix_cnt[0]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/pixels_shifter_inst/N122/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst udp_osd_inst/char_osd_inst/char_pic_rom_inst/N58_sum6/gateop_perm;gopLUT5 @@ -248819,7 +248745,7 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/char_pic_rom_inst/N6_mux4_5/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[10:0]_or_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -249343,7 +249269,7 @@ I4;1 RS;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N588_5/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N100/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -249499,7 +249425,7 @@ I14;1 RS;1 Inst -udp_osd_inst/char_osd_inst/char_pic_rom_inst/N11_mux6_1/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[10:0]_or_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -249617,17 +249543,7 @@ I14;1 RS;1 Inst -image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[0]/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[10:0]_or_7/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N206_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -249637,7 +249553,7 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N785_5/gateop_perm;gopLUT5 +udp_osd_inst/char_buf_writer_inst/N206_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -249699,17 +249615,7 @@ D;1 RS;1 Inst -udp_osd_inst/char_osd_inst/pixels_shifter_inst/N135/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -udp_osd_inst/char_osd_inst/pixels_shifter_inst/N18_mux7_7/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/pixels_shifter_inst/N114_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -249719,7 +249625,7 @@ L3;1 L4;1 Inst -u_sync_vg/pos_x[3]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_osd_char_height/value[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -249735,20 +249641,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_rotate/N155_8_7/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -udp_wr_mem_inst/N204/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/pixels_shifter_inst/N9_mux10/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -249758,7 +249651,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_osd_startX/value[0]/opit_0_L5Q_perm;gopL5Q +u_sync_vg/h_count[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -249774,7 +249667,7 @@ L4;1 RS;1 Inst -udp_osd_inst/char_osd_inst/pixels_shifter_inst/m_pixel_posX[0]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/char_buf_reader_inst/char_pos_x[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -249790,7 +249683,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_osd_startY/value[0]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cur_state_reg[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -249806,7 +249699,7 @@ L4;1 RS;1 Inst -udp_osd_inst/char_osd_inst/pixels_shifter_inst/s_ready_d_d[0]_4/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N327_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -249816,7 +249709,7 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/pixels_shifter_inst/N122/gateop_perm;gopLUT5 +u_sync_vg/N138_mux7_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -249826,7 +249719,7 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/pixels_shifter_inst/N114_11/gateop_perm;gopLUT5 +u_sync_vg/N53_mux7_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -249836,7 +249729,7 @@ L3;1 L4;1 Inst -u_rotate_image/N144_mux13_6/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_pic_rom_inst/N41/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -249846,7 +249739,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_osd_startY/value[1]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/pixels_shifter_inst/pix_cnt[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -249862,42 +249755,71 @@ L4;1 RS;1 Inst -udp_osd_inst/char_osd_inst/pixels_shifter_inst/N137/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_sync_vg/N138_mux4/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_pic_rom_inst/m_row_pixels_valid/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/char_osd_inst/pixels_shifter_inst/m_pixel_posX[10]/opit_0_AQ_perm;gopAQ +udp_osd_inst/char_osd_inst/pixels_shifter_inst/N114_11/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +u_sync_vg/N184_14/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +param_manager_inst/param_osd_char_height/value[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 -Cout;2 Q;2 RSOUT;2 -Y;2 +Z;2 CE;1 CLK;1 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 RS;1 Inst @@ -250035,7 +249957,7 @@ I14;1 RS;1 Inst -param_manager_inst/param_osd_startX/N76_mux4_3/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N415/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -250166,7 +250088,7 @@ D;1 RS;1 Inst -u_hdmi_rst/N0/gateop_perm;gopLUT5 +u_sync_vg/N50_mux4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -250249,14 +250171,20 @@ I14;1 RS;1 Inst -u_sync_vg/N53_mux7_4/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst udp_osd_inst/char_osd_inst/pixels_shifter_inst/pixels_data[1]/opit_0_L5Q_perm;gopL5Q @@ -250275,7 +250203,7 @@ L4;1 RS;1 Inst -udp_osd_inst/char_osd_inst/pixels_shifter_inst/pixels_data[4]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/pixels_shifter_inst/pixels_data[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -250291,7 +250219,7 @@ L4;1 RS;1 Inst -udp_osd_inst/char_osd_inst/pixels_shifter_inst/pixels_data[3]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/pixels_shifter_inst/pixels_data[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -250307,7 +250235,7 @@ L4;1 RS;1 Inst -udp_osd_inst/char_osd_inst/pixels_shifter_inst/pixels_data[6]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/pixels_shifter_inst/pixels_data[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -250339,7 +250267,7 @@ L4;1 RS;1 Inst -udp_osd_inst/char_osd_inst/pixels_shifter_inst/pixels_data[2]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/pixels_shifter_inst/pixels_data[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -250355,23 +250283,17 @@ L4;1 RS;1 Inst -udp_osd_inst/char_osd_inst/pixels_shifter_inst/pixels_data[8]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/char_pic_rom_inst/N58_maj7/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/char_osd_inst/char_pic_rom_inst/N41/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_pic_rom_inst/N6_mux4_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -250381,7 +250303,7 @@ L3;1 L4;1 Inst -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N684/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N75_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -250408,14 +250330,20 @@ S0;1 S1;1 Inst -param_manager_inst/param_osd_startY/N149_43_1/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/row_cnt[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst udp_osd_inst/char_ram/U_ipml_sdpram_async_ram2048x8_2clk/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm;gopDRM @@ -250668,7 +250596,7 @@ D;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/N72_17/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/N72_19/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -250678,7 +250606,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N697_2/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N409_12/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -250688,7 +250616,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N630_3/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N10/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -250698,7 +250626,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N710_3/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_6[7]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -250744,7 +250672,7 @@ I14;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q;gopL5Q Pin CEOUT;2 Q;2 @@ -250938,7 +250866,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[5]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[6]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -250948,7 +250876,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -250964,7 +250892,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -250980,7 +250908,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -250996,17 +250924,23 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[4]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -251022,7 +250956,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[5]_1/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_12/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -251032,7 +250966,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -251048,7 +250982,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -251080,7 +251014,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[8]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[9]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -251384,23 +251318,17 @@ I14;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N106_12/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -251416,7 +251344,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[1]_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -251426,7 +251354,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -251442,20 +251370,14 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N106_6/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm;gopL5Q @@ -251490,7 +251412,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N613_3/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -251516,7 +251438,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -251532,23 +251454,20 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/N20.fsub_8/gateop_perm;gopA Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_4/gateop_perm;gopLUT5 +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_16_cpy/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -251690,7 +251609,7 @@ D;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -251700,27 +251619,39 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_20/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -251730,7 +251661,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -251740,7 +251671,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_2/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N106_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -251750,7 +251681,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N367/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -251760,7 +251691,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_14/gateop_perm;gopLUT5 +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -251770,7 +251701,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N106_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -251780,23 +251711,17 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm;gopL5Q +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N105[6]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_12/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -251806,7 +251731,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -251816,7 +251741,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N983_9/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[10]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -251826,7 +251751,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1039_22[0]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_16/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -251836,7 +251761,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_16/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -251856,7 +251781,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[8]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -251866,20 +251791,14 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[2]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[1]/gateop_perm;gopLUT5 @@ -251892,20 +251811,14 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_14/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[3]/gateop_perm;gopLUT5 @@ -251918,23 +251831,17 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N106_10/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[6]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[5]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -251954,57 +251861,87 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N106_2/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[9]/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/remainder[3]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[10]/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N106_4/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N263/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N106_6/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -252014,17 +251951,23 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N148_2/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N106_12/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N106_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -252034,7 +251977,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N106_10/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -252054,7 +251997,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[10]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -252070,14 +252013,20 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N192_4/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167.eq_0/gateop_A2;gopA2 @@ -252683,17 +252632,23 @@ WR_EOP;1 WR_ERR;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N129_41/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[12]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N127_1_2/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N312_1_or[0]_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -252714,7 +252669,7 @@ S0;1 S1;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N706/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N312_1_or[0]_2_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -252724,7 +252679,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N462_23/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N114_27/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -252734,7 +252689,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N195_28/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -252744,7 +252699,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N114_26/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[6]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -252754,7 +252709,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N114_24/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N847/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -252764,23 +252719,17 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[9]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N462_25/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_64_cpy/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N60_mux3_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -252790,7 +252739,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N127_1_3/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N866_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -252800,7 +252749,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N639/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N403_64/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -252810,7 +252759,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N289_7/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N630_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -252820,20 +252769,17 @@ L3;1 L4;1 Inst -u_zoom_image/N375.eq_6/gateop_perm;gopA +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N466_9/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N769/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N402_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -252843,7 +252789,27 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N366_5/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N462_24/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N219_36[0]_2/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N563_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -252873,17 +252839,7 @@ S10;1 S11;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N943/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N310_18/gateop;gopMUX4TO1 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N310_16/gateop;gopMUX4TO1 Pin F;2 I0;1 @@ -252894,7 +252850,7 @@ S0;1 S1;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N766_3/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_51/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -252904,7 +252860,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N195_40/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N1057_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -252914,18 +252870,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N312_1_or[0]_7/gateop;gopMUX4TO1 -Pin -F;2 -I0;1 -I1;1 -I2;1 -I3;1 -S0;1 -S1;1 - -Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N119_47/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N402_78/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -252946,7 +252891,7 @@ S0;1 S1;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N834/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N566_14_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -252956,7 +252901,18 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N563_4/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N366_1/gateop;gopMUX4TO1 +Pin +F;2 +I0;1 +I1;1 +I2;1 +I3;1 +S0;1 +S1;1 + +Inst +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N114_25/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -252966,7 +252922,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N766_1/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N195_56/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -252976,7 +252932,7 @@ L3;1 L4;1 Inst -u_ov5640/coms1_reg_config/u1/N267_35/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N402_62/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -252996,7 +252952,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N403_50/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N402_52/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -253016,20 +252972,14 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[45]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N403_42/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N403_46/gateop_perm;gopLUT5 @@ -253042,20 +252992,14 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[9]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N403_50/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N403_54/gateop_perm;gopLUT5 @@ -253088,17 +253032,23 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N403_64/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[12]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N402_70/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N403_58/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -253108,7 +253058,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[19]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[43]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -253124,17 +253074,7 @@ L4;1 RS;1 Inst -u_ov5640/coms1_reg_config/u1/N195_inv/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_zoom_image/wr_addr2[0]/opit_0_inv_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -253150,7 +253090,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N403_58/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_59/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -253160,17 +253100,23 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N403_69/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[34]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N402_74/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_55/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -253180,7 +253126,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[24]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[25]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -253196,7 +253142,7 @@ L4;1 RS;1 Inst -image_filiter_inst/multiline_buffer_inst/N53_mux5_8/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N639/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -253206,7 +253152,23 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N422_4/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[31]/opit_0_L5Q_perm;gopL5Q +Pin +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 + +Inst +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N462_23/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -253227,7 +253189,7 @@ S0;1 S1;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N566_14_2/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_39/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -253237,7 +253199,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_48/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_63/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -253247,7 +253209,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_44/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N127_1_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -253257,7 +253219,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N114_23/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N409_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -253267,17 +253229,23 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_52/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[19]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -253293,46 +253261,33 @@ L4;1 RS;1 Inst -udp_osd_inst/char_buf_writer_inst/N87_1_10/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_64/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[28]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[12]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N58_ac2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N308_31/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N462_28/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -253342,7 +253297,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N847/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N619_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -253352,7 +253307,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1082/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N566_14_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -253362,17 +253317,23 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N462_28/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/arp_rx_type/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[5]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N635_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -253382,7 +253343,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N58_ac2/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N436_31/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -253392,7 +253353,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N566_14_3/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N563_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -253402,7 +253363,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N630_4/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N436_30/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -253428,7 +253389,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1090/gateop_perm;gopLUT5 +param_manager_inst/param_rotate/N63_mux7_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -253438,7 +253399,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N402_52/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N357_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -253448,7 +253409,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N374/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N78/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -253458,7 +253419,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N1057_5/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N831_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -253468,17 +253429,23 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N516/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[29]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N866_5/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N710_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -253488,7 +253455,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/arp_rx_type/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[8]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -253504,7 +253471,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/arp_rx_done/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -253520,17 +253487,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_40/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N186/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N409_16/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -253540,7 +253497,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N72_mux3_3/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N577_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -253550,24 +253507,42 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N584_4/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[4]/opit_0_L6Q_perm;gopL6Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +A0;1 +A1;1 +A2;1 +A3;1 +A4;1 +B0;1 +B1;1 +B2;1 +B3;1 +B4;1 +CE;1 +CLK;1 +M;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N82_mux3_1/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[27]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst udp_osd_inst/eth_udp_inst/u_eth_ctrl/arp_rx_flag/opit_0_L5Q_perm;gopL5Q @@ -253586,7 +253561,7 @@ L4;1 RS;1 Inst -u_zoom_image/rd_addr0[10:0]_inv/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N406/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -253596,7 +253571,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt[1]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -253612,7 +253587,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt[2]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[12]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -253660,23 +253635,17 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[11]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N706/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[1]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/error_en/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -253692,17 +253661,23 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N312_1_or[0]_2_2/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[2]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[2]/opit_0_L5Q;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -253718,45 +253693,27 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[4]/opit_0_L6Q_perm;gopL6Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N364/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -A0;1 -A1;1 -A2;1 -A3;1 -A4;1 -B0;1 -B1;1 -B2;1 -B3;1 -B4;1 -CE;1 -CLK;1 -M;1 -RS;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[36]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N366_5/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[5]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -253772,7 +253729,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[3]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[11]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -253788,7 +253745,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[4]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[2]/opit_0_L5Q;gopL5Q Pin CEOUT;2 Q;2 @@ -253804,23 +253761,17 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[11]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_43/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[6]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[4]/opit_0_L5Q;gopL5Q Pin CEOUT;2 Q;2 @@ -253836,7 +253787,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[7]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[5]/opit_0_L5Q;gopL5Q Pin CEOUT;2 Q;2 @@ -253852,7 +253803,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[31]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[6]/opit_0_L5Q;gopL5Q Pin CEOUT;2 Q;2 @@ -253868,7 +253819,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[29]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[10]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -253895,7 +253846,7 @@ D;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[17]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[19]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -253922,7 +253873,7 @@ D;1 RS;1 Inst -u_ov5640/coms1_reg_config/N8_mux4_5/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_47/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -253987,7 +253938,7 @@ D;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[19]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[17]/opit_0_L5Q;gopL5Q Pin CEOUT;2 Q;2 @@ -254014,7 +253965,7 @@ D;1 RS;1 Inst -u_ov5640/coms1_reg_config/N26_mux6_3/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N409_32/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -254101,20 +254052,14 @@ D;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[27]/opit_0_L5Q;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N82_mux3_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[28]/opit_0;gopQ @@ -254128,14 +254073,20 @@ D;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_36/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[31]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[30]/opit_0;gopQ @@ -254149,14 +254100,20 @@ D;1 RS;1 Inst -u_zoom_image/N236_0/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[9]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[0]/opit_0;gopQ @@ -254247,7 +254204,7 @@ D;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[10]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[14]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -254263,17 +254220,23 @@ L4;1 RS;1 Inst -u_ov5640/coms1_reg_config/u1/N239/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[11]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[12]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -254289,7 +254252,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[13]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[19]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -254305,17 +254268,23 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N402_47/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[13]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[16]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[32]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -254331,7 +254300,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[14]/opit_0_L5Q;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[15]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -254347,7 +254316,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[15]/opit_0_L5Q;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[16]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -254363,14 +254332,20 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N402_62/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[9]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[20]/opit_0_L5Q_perm;gopL5Q @@ -254389,7 +254364,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[22]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[26]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -254405,7 +254380,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[23]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[22]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -254437,7 +254412,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[25]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[23]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -254453,39 +254428,27 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[33]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N402_47/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[31]/opit_0_L5Q_perm;gopL5Q +u_zoom_image/N322_9/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[28]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[24]/opit_0_L5Q;gopL5Q Pin CEOUT;2 Q;2 @@ -254501,17 +254464,23 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N402_49/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[29]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[30]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[27]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -254527,7 +254496,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[27]/opit_0_L5Q;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[30]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -254543,7 +254512,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[29]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[33]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -254559,7 +254528,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[32]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[37]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -254575,7 +254544,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[34]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[17]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -254591,7 +254560,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[37]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[38]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -254607,14 +254576,20 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N402_66/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[8]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[35]/opit_0_L5Q_perm;gopL5Q @@ -254633,17 +254608,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7210_ctl/N403_5/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[26]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[39]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -254659,7 +254624,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[40]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[36]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -254675,7 +254640,7 @@ L4;1 RS;1 Inst -u_ov5640/coms1_reg_config/u1/N8_mux3_1/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N402_49/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -254685,7 +254650,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[39]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[40]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -254701,7 +254666,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[42]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[45]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -254733,23 +254698,17 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[44]/opit_0_L5Q_perm;gopL5Q +u_zoom_image/rd_addr0[10:0]_inv/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[43]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[42]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -254781,7 +254740,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[17]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[44]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -254813,7 +254772,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N403_42/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N402_70/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -254823,7 +254782,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[47]/opit_0_L5Q;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[47]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -254838,6 +254797,16 @@ L3;1 L4;1 RS;1 +Inst +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N127_1_3/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + Inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/error_en/opit_0_MUX4TO1Q;gopMUX4TO1Q Pin @@ -255577,7 +255546,7 @@ D;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[16]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[10]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -255593,7 +255562,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[15]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[16]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -255609,7 +255578,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[18]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[14]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -255625,7 +255594,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[19]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[20]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -255641,7 +255610,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[20]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[19]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -255657,17 +255626,23 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[8]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[21]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[22]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[18]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -255683,7 +255658,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[17]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[23]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -255699,7 +255674,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[24]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[17]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -255715,7 +255690,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[31]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[24]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -255731,7 +255706,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[26]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[22]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -255747,7 +255722,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[21]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[25]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -255763,23 +255738,17 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[28]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[0]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[27]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[29]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -255795,7 +255764,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[30]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[26]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -255811,7 +255780,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[25]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[27]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -255827,17 +255796,23 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N409_4/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[29]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[28]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -255853,7 +255828,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N409_12/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N409_24/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -255863,27 +255838,39 @@ L3;1 L4;1 Inst -u_zoom_image/N232_0/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[30]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N409_28/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[11]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[9]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[31]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -255899,30 +255886,30 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_56/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_zoom_image/wr_addr0[0]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N409_8/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[0]/opit_0;gopQ @@ -256541,7 +256528,7 @@ D;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[16]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[18]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -256557,7 +256544,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[17]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[20]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -256573,7 +256560,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[18]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[13]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -256589,7 +256576,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[12]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[19]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -256605,7 +256592,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[34]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[24]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -256621,7 +256608,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[14]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[16]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -256637,7 +256624,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[40]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[22]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -256669,7 +256656,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[24]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[21]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -256685,7 +256672,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[41]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[35]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -256749,7 +256736,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[29]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[42]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -256781,7 +256768,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[31]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[38]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -256813,7 +256800,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[25]/opit_0_L5Q;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[33]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -256829,7 +256816,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[33]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[34]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -256845,23 +256832,17 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[35]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N175_50/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[36]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[44]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -256877,7 +256858,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[37]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[31]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -256893,7 +256874,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[38]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[46]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -256925,17 +256906,23 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_32/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[40]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/data_cnt[0]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[37]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -256951,7 +256938,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[42]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[15]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -256967,7 +256954,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[43]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[36]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -256983,7 +256970,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[44]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[43]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -256999,7 +256986,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[45]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[41]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -257031,17 +257018,23 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N409_32/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[45]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[46]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[17]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -257057,7 +257050,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/iic_dri_rx/N489_1/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_6[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -257067,39 +257060,27 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/gmii_txd_data[7]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N219_63[2]_4/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[20]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_48/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N102_2/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_32/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -257109,7 +257090,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_6[6]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N604_13/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -257119,23 +257100,17 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[22]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/N72_25/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N832/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[7]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -257178,17 +257153,23 @@ I3;1 I4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N820_36[6]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[12]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -ms72xx_ctl/iic_dri_rx/N165_5/gateop_perm;gopLUT5 +udp_osd_inst/char_buf_writer_inst/N138_26/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -257279,20 +257260,14 @@ S0;1 S1;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/data_cnt[3]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/N72_26_cpy/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N219_63[2]_7_muxf6;gopMUX8TO1 @@ -257315,7 +257290,7 @@ S10;1 S11;1 Inst -ms72xx_ctl/ms7200_ctl/N40_8/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_24/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -257476,7 +257451,7 @@ S0;1 S1;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N219_63[2]_4/gateop_perm;gopLUT5 +u_zoom_image/N530_mux3_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -257530,7 +257505,17 @@ S0;1 S1;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N291_8/gateop;gopMUX4TO1 +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N39_1/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N291_12/gateop;gopMUX4TO1 Pin F;2 I0;1 @@ -257541,7 +257526,7 @@ S0;1 S1;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N291_12/gateop;gopMUX4TO1 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N291_14/gateop;gopMUX4TO1 Pin F;2 I0;1 @@ -257552,7 +257537,7 @@ S0;1 S1;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N291_14/gateop;gopMUX4TO1 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N291_16/gateop;gopMUX4TO1 Pin F;2 I0;1 @@ -257563,7 +257548,7 @@ S0;1 S1;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_44/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N817_2_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -257573,17 +257558,23 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N219_36[0]_2/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[29]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_20/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_16[6]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -257593,7 +257584,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_40/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_10[5]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -257603,23 +257594,17 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[11]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_10[0]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_39/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_44/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -257629,7 +257614,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_16[2]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_36/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -257639,7 +257624,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_16/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_40/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -257649,7 +257634,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N219_36[1]_2/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N327/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -257659,7 +257644,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_48/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_6[6]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -257669,7 +257654,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N820_36[5]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N832/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -257679,7 +257664,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1125/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N140_29/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -257689,23 +257674,27 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[12]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_12/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N409_24/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N943_1/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N409_20/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -257715,7 +257704,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N611_13/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_55/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -257725,22 +257714,19 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][31]/opit_0_AQ_perm;gopAQ +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[15]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 -Cout;2 Q;2 RSOUT;2 -Y;2 +Z;2 CE;1 CLK;1 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 RS;1 Inst @@ -257754,7 +257740,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N409_20/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N409_28/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -257764,48 +257750,30 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[14]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_17_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 - -Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N219_63[7]_2_muxf6_perm;gopLUT6 -Pin -Y0;2 -Y1;2 -Z;2 -A0;1 -A1;1 -A2;1 -A3;1 -A4;1 -B0;1 -B1;1 -B2;1 -B3;1 -B4;1 -M;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N421_3/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N411_6/gateop;gopMUX4TO1 @@ -257819,7 +257787,7 @@ S0;1 S1;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N427_3/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N291_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -257829,20 +257797,14 @@ L3;1 L4;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N419_5/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N416_7/gateop;gopMUX4TO1 @@ -257866,7 +257828,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N415/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N427_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -257886,7 +257848,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N415_1/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N817_1_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -257896,7 +257858,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N832_1/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N820_36[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -257906,7 +257868,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N820_36[0]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N420_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -257916,17 +257878,23 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N817_2_3/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/crc_en/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/crc_en/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -257942,7 +257910,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[5]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -257958,7 +257926,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7200_ctl/N8_7/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N781_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -257968,7 +257936,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/ms7200_ctl/N1877/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N820_36[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -257978,7 +257946,7 @@ L3;1 L4;1 Inst -N285_9/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N820_36[5]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -257988,7 +257956,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N199_1/gateop_perm;gopLUT5 +udp_osd_inst/char_buf_writer_inst/N230/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -257998,7 +257966,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N220_3/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N820_48[7]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -258008,7 +257976,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N219_63[2]_9/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N140_27/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -258018,7 +257986,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N781_1/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N189_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -258214,14 +258182,20 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N102_7/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N820_50[0]/gateop;gopMUX4TO1 @@ -258400,36 +258374,14 @@ S0;1 S1;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[9]/opit_0_L5Q_perm;gopL5Q -Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 - -Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/divisor_kp[1]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1125/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[7][0]/opit_0;gopQ @@ -259334,7 +259286,7 @@ D;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[1]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -259350,20 +259302,14 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[2]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[5:0]_89/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[3]/opit_0_L5Q_perm;gopL5Q @@ -259382,7 +259328,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[1]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -259435,7 +259381,7 @@ S0;1 S1;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N206_5/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N820_36[3]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -259445,7 +259391,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[5:0]_89/gateop;gopMUX4TO1 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[5:0]_85/gateop;gopMUX4TO1 Pin F;2 I0;1 @@ -259456,7 +259402,7 @@ S0;1 S1;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N411_1/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N418/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -259466,7 +259412,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N419_5/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N102_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -259487,17 +259433,23 @@ D;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N236_5/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cur_state_reg[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cur_state_reg[1]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/gmii_txd_valid/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -259529,7 +259481,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_eth_ctrl/arp_tx_en/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -259561,7 +259513,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/gmii_txd_valid/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cur_state_reg[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -259609,7 +259561,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/data_cnt[4]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/data_cnt[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -259625,7 +259577,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N249_6/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N219_36[1]_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -259635,7 +259587,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/iic_dri_rx/N80_0/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_10[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -259764,30 +259716,30 @@ S0;1 S1;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N820_36[2]/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/pixels_shifter_inst/pixels_data[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[0]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N236_5/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/skip_en/opit_0_MUX4TO1Q;gopMUX4TO1Q @@ -259856,6 +259808,16 @@ CLK;1 D;1 RS;1 +Inst +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N263/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + Inst udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N148_2/gateop_perm;gopLUT5 Pin @@ -259867,7 +259829,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N84_1/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N229_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -259877,7 +259839,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N263/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N199_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -259887,23 +259849,27 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[20]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N229_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[2]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N183_4/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[10]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -259919,7 +259885,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N248_5/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N74/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -259929,7 +259895,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N183_4/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N15/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -259939,7 +259905,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N243_2/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N192_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -259949,7 +259915,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N229_6/gateop_perm;gopLUT5 +udp_osd_inst/char_buf_writer_inst/N206_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -259959,7 +259925,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N192_4/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N248_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -259969,7 +259935,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N206_2/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N206_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -259979,7 +259945,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[6]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -259995,17 +259961,23 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N75_1/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/pixels_shifter_inst/pixels_data[8]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N820_36[1]/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N478/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -260015,7 +259987,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N211_1/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N111_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -260025,7 +259997,17 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[4]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N588_5/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[20]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -260041,7 +260023,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N229_7/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N339_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -260051,7 +260033,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N189_1/gateop_perm;gopLUT5 +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N589_5_cpy/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -260061,7 +260043,7 @@ L3;1 L4;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/remainder[1]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/gmii_txd_data[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -260077,17 +260059,23 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N229_1/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[8]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[0]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[9]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -260103,17 +260091,23 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N39_1/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[11]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[8]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -260129,7 +260123,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[3]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[12]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -260145,7 +260139,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[9]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[27]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -260161,7 +260155,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[25]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[13]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -260177,7 +260171,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[12]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[15]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -260193,7 +260187,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[13]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[16]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -260225,7 +260219,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[15]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[14]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -260241,7 +260235,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[22]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[18]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -260257,7 +260251,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[10]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[19]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -260273,7 +260267,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[18]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[21]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -260289,7 +260283,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[19]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[22]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -260305,7 +260299,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[16]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[23]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -260321,7 +260315,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[14]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[24]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -260337,7 +260331,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[26]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[25]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -260353,7 +260347,17 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[31]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N711_2/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -260369,7 +260373,17 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[24]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N820_36[6]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[29]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -260385,17 +260399,23 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N186_1/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[26]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[7]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[31]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -260411,7 +260431,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[21]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -260427,7 +260447,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[28]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/pixels_shifter_inst/pixels_data[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -260443,7 +260463,17 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[29]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N683_7/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[28]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -260475,7 +260505,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[23]/opit_0_L5Q;gopL5Q +udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_reg[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -260491,7 +260521,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7200_ctl/dri_cnt[3]/opit_0_inv_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -260507,7 +260537,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[27]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -260523,17 +260553,33 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N820_48[7]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_en/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[11]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N421_3/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -260549,37 +260595,55 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7200_ctl/N8_3/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_valid/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N3_1/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[5]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_eth_ctrl/protocol_sw_reg[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[5]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_buf_writer_inst/ram_addr[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -260595,7 +260659,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -260611,7 +260675,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_eth_ctrl/protocol_sw_reg[0]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -260627,7 +260691,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[5:0]_93/gateop_perm;gopLUT5 +N163_mux3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -260637,113 +260701,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[2]/opit_0_L5Q_perm;gopL5Q -Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 - -Inst -udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[7]/opit_0_L5Q_perm;gopL5Q -Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 - -Inst -udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[4]/opit_0_L5Q_perm;gopL5Q -Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 - -Inst -udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_valid/opit_0_L5Q_perm;gopL5Q -Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 - -Inst -udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[6]/opit_0_L5Q_perm;gopL5Q -Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 - -Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cur_state_reg[0]/opit_0_L5Q_perm;gopL5Q -Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 - -Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N817_1_4/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N75_1/gateop_perm;gopLUT5 +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_14/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -260764,20 +260722,14 @@ D;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[19]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N832/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[0]/opit_0;gopQ @@ -261367,14 +261319,46 @@ MI;1 T;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N229_7/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[3]/opit_0_L5Q_perm;gopL5Q +Pin +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 + +Inst +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N189_2/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[1]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N220_3/gateop_perm;gopLUT5 @@ -261387,7 +261371,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N820_36[3]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N183_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -261397,7 +261381,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N84_1/gateop;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N206_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -261407,23 +261391,17 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[5]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N192_4/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N186_1/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_rx/N461_8_or[4][3]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -261433,17 +261411,23 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N199_1/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[4]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N39_1/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N192_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -261453,7 +261437,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N229_6/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N248_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -261463,7 +261447,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cur_state_reg[3]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[22]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -261479,7 +261463,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1039_22[4]/gateop_perm;gopLUT5 +ms72xx_ctl/ms7200_ctl/N1872_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -261489,20 +261473,24 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[1]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_buf_writer_inst/N222/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +ms72xx_ctl/ms7200_ctl/N2083/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N236_5/gateop_perm;gopLUT5 @@ -261515,7 +261503,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N229_1/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N229_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -261525,39 +261513,27 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[0]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N229_7/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[4]/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/ms7200_ctl/N1954_1_or[1]_6/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[0]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -261573,7 +261549,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N102_2/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N171_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -261583,7 +261559,17 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N248_5/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N189_1/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1039_22[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -261609,17 +261595,23 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N418/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[9]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[3]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[17]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -261635,7 +261627,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[9]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[8]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -261651,7 +261643,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[13]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[19]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -261667,7 +261659,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[2]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[10]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -261683,7 +261675,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[6]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[14]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -261699,7 +261691,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[8]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[15]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -261715,7 +261707,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[14]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[11]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -261731,33 +261723,33 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[24]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N199_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N183_4/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[18]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[23]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[16]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -261773,7 +261765,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[11]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[13]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -261789,7 +261781,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[17]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[26]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -261805,7 +261797,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[18]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[30]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -261821,7 +261813,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[16]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[23]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -261837,7 +261829,20 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[20]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_buf_writer_inst/N87_1_10/gateop_perm;gopA +Pin +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 + +Inst +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[25]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -261869,7 +261874,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[22]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[20]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -261885,7 +261890,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[15]/opit_0_L5Q;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[28]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -261901,7 +261906,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N243_2/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1039_22[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -261911,7 +261916,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N111_1/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N102_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -261921,39 +261926,27 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[19]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N229_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[26]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N243_2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[25]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[27]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -261985,55 +261978,37 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[30]/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/ms7200_ctl/N1359_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[31]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N186_2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[27]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N102_2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[28]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[31]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -262049,7 +262024,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[3]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/char_buf_writer_inst/ram_addr[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -262065,7 +262040,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N420_6/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N806_14_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -262075,7 +262050,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N189_1/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N100/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -262085,23 +262060,17 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[1]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N834/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N3_1/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N578_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -262111,7 +262080,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N206_1/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_16_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -262121,7 +262090,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1261/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_16_30/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -262131,7 +262100,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1213_3/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_17_10/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -262141,7 +262110,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N114_19/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1261/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -262151,7 +262120,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N129_33/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_16_22/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -262161,7 +262130,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N129_44/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N838/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -262181,37 +262150,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_16_30/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N129_47/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_17_18/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_17_14/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_16_33/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -262221,7 +262160,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_16_33/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_17_33/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -262231,7 +262170,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N402_58/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_17_22/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -262241,7 +262180,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_17_6/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_17_29/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -262251,7 +262190,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_17_33/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_15/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -262261,7 +262200,7 @@ L3;1 L4;1 Inst -u_zoom_image/N306_9/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N129_41/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -262271,7 +262210,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_17_22/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[5]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -262281,7 +262220,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N100/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_17_26/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -262291,7 +262230,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N563_3/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1130_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -262301,7 +262240,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_17_26/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N436_67/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -262311,7 +262250,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_17_29/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_17_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -262321,7 +262260,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_16_18/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N436_18_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -262331,7 +262270,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N129_37/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N129_47/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -262351,7 +262290,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N129_49/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N129_37/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -262361,7 +262300,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N82_mux3/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N518_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -262371,7 +262310,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N310_1_or[0]_8/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1309_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -262381,7 +262320,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_16_26/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N438_1_or[0]_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -262391,7 +262330,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N956/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N199_maj3_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -262401,17 +262340,23 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N438_1_or[0]_4/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_done_cdc/out_ack/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1079_1/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N195_44/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -262421,7 +262366,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N175_38/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N578_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -262431,7 +262376,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N195_36/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N195_47/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -262441,17 +262386,23 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N195_47/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N406/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N516/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -262461,7 +262412,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N195_56/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N232_and[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -262471,7 +262422,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N195_51/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N195_32/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -262481,7 +262432,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[0]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -262497,27 +262448,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N230_9_3/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N199_maj3_1/gateop;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_zoom_image/N306_12/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N579_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -262547,27 +262478,20 @@ I13;1 I14;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N905/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N806_14_3/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N216.eq_2/gateop;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N183/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N803_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -262577,7 +262501,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N573/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N199_sum5_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -262827,14 +262751,17 @@ I13;1 I14;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[2]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N361.eq_8/gateop;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N372_1/gateop_A2;gopA2 @@ -263557,7 +263484,7 @@ I13;1 I14;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N438_1_or[0]_2_2/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N619_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -263567,7 +263494,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N518_5/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N573_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -263577,18 +263504,17 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N436_18_3/gateop;gopMUX4TO1 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N438_1_or[0]_8/gateop_perm;gopLUT5 Pin -F;2 -I0;1 -I1;1 -I2;1 -I3;1 -S0;1 -S1;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N518_1/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N438_1_or[0]_2_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -263629,7 +263555,7 @@ S0;1 S1;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[2]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -263645,17 +263571,39 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N438_1_or[0]_8/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[11]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N436_70/gateop;gopMUX4TO1 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[1]/opit_0_L5Q_perm;gopL5Q +Pin +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 + +Inst +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N436_68/gateop;gopMUX4TO1 Pin F;2 I0;1 @@ -263666,7 +263614,7 @@ S0;1 S1;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N257_13_2/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1304/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -263676,7 +263624,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N129_29/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N577_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -263686,17 +263634,23 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N620_2/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N438_1_or[0]_13/gateop;gopMUX4TO1 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N511_3/gateop;gopMUX4TO1 Pin F;2 I0;1 @@ -263707,7 +263661,7 @@ S0;1 S1;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N571_5/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N817_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -263717,18 +263671,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N511_3/gateop;gopMUX4TO1 -Pin -F;2 -I0;1 -I1;1 -I2;1 -I3;1 -S0;1 -S1;1 - -Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N578_7/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_fsm[6:0]_38/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -263738,39 +263681,27 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[2]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N795_2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/error_en/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N308_31/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_fsm[6:0]_46/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_fsm[6:0]_33/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -263780,7 +263711,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N806_5/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N956/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -263790,7 +263721,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N578_1/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N571_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -263800,7 +263731,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N310_7_3/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N82_mux3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -263810,7 +263741,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N579_4/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1213_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -263820,7 +263751,18 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N892_3/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N579_1/gateop;gopMUX4TO1 +Pin +F;2 +I0;1 +I1;1 +I2;1 +I3;1 +S0;1 +S1;1 + +Inst +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N602_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -263830,7 +263772,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1326_3/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N905/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -263851,7 +263793,7 @@ S0;1 S1;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N619_8/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_3[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -263861,7 +263803,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N436_15_3/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_3[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -263871,7 +263813,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N795_2/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -263892,33 +263834,17 @@ S0;1 S1;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N803_4/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[5]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N620_2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1309_5/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N892_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -263928,17 +263854,23 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N199_sum5_4/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt[2]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N817_1/gateop;gopMUX4TO1 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N806_14_3/gateop;gopMUX4TO1 Pin F;2 I0;1 @@ -263949,7 +263881,7 @@ S0;1 S1;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1304/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N195_36/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -263959,7 +263891,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1170/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N710_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -263969,7 +263901,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N312_1_or[0]_3/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1082/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -263979,23 +263911,17 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[9]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N129_29/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1014/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N195_51/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -264005,7 +263931,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N436_11_3/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1057_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -264015,7 +263941,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1057_3/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N769/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -264025,23 +263951,38 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[0]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N114_21/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[0]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[2]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1014_2/gateop;gopMUX4TO1 +Pin +F;2 +I0;1 +I1;1 +I2;1 +I3;1 +S0;1 +S1;1 + +Inst +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -264057,7 +263998,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N195_32/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -264067,7 +264008,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1127_3/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1170/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -264077,7 +264018,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1294/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[6]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -264087,7 +264028,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N119_33/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[9]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -264097,7 +264038,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1130_5/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1294/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -264107,17 +264048,23 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N462_25/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_data_d0[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N310_16/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -264127,7 +264074,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N577_3/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N436_15_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -264137,7 +264084,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N195_44/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1014/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -264147,23 +264094,17 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt[2]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[0]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N710_1/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1265/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -264173,7 +264114,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N232_and[0]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N129_44/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -264182,19 +264123,6 @@ L2;1 L3;1 L4;1 -Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N216.eq_2/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - Inst udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt[1]/opit_0_L5Q_perm;gopL5Q Pin @@ -264228,7 +264156,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N838/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N129_33/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -264254,7 +264182,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N602_4/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N129_49/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -264264,7 +264192,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N436_69/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[8]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -264274,30 +264202,30 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[1]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[0]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N438_1_or[0]_14/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[1]/opit_0_L5Q;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[3]/opit_0_L5Q_perm;gopL5Q @@ -264316,7 +264244,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[4]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -264332,7 +264260,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt[0]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -264348,7 +264276,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[6]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_pkt_done/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -264364,7 +264292,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_pkt_done/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -265172,14 +265100,20 @@ D;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N80_ac2/gateop_perm;gopLUT5 +u_ddr_rst/rst/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/eth_type[8]/opit_0;gopQ @@ -265292,14 +265226,20 @@ D;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[4]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[2]/opit_0_L5Q;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[4]/opit_0_A2Q21;gopA2Q2 @@ -265659,23 +265599,14 @@ D;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[15]/opit_0_AQ_perm;gopAQ +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[3]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Cout;2 -Q;2 -RSOUT;2 -Y;2 -CE;1 -CLK;1 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 -RS;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[2]/opit_0_A2Q21;gopA2Q2 @@ -265867,7 +265798,7 @@ I14;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[0]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[6]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -265925,7 +265856,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[7]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[17]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -265989,20 +265920,14 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[16]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N353_ac2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[0]/opit_0;gopQ @@ -266577,7 +266502,7 @@ D;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[2]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_pkt_done/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -266593,7 +266518,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N635_1/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1090/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -266955,7 +266880,7 @@ D;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[1]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -266971,7 +266896,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[2]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -266987,7 +266912,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[3]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -267003,7 +266928,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_data_d0[0]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -267019,7 +266944,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[5]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -267050,6 +266975,64 @@ L3;1 L4;1 RS;1 +Inst +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[8]/opit_0_L5Q_perm;gopL5Q +Pin +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 + +Inst +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[10]/opit_0_L5Q_perm;gopL5Q +Pin +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 + +Inst +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[9]/opit_0_L5Q_perm;gopL5Q +Pin +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 + +Inst +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N80_ac2/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + Inst udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[11]/opit_0_L5Q_perm;gopL5Q Pin @@ -267067,7 +267050,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[8]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[14]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -267099,43 +267082,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[10]/opit_0_L5Q_perm;gopL5Q -Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 - -Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_60/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_sync_vg/N50_mux3/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[14]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[18]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -267167,7 +267114,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[2]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[12]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -267183,7 +267130,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_data_d0[4]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[22]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -267199,7 +267146,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[17]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[21]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -267215,7 +267162,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[18]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[19]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -267231,7 +267178,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[23]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_data_d0[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -267247,7 +267194,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[1]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[24]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -267263,7 +267210,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[21]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[25]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -267279,7 +267226,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[22]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[23]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -267295,7 +267242,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_56/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[13]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -267305,23 +267252,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[24]/opit_0_L5Q_perm;gopL5Q -Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 - -Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[25]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[26]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -267337,7 +267268,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[26]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[20]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -267433,7 +267364,7 @@ L4;1 RS;1 Inst -u_ov5640/coms1_reg_config/N8_mux10/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[6]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -267636,7 +267567,7 @@ D;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[1]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -267646,7 +267577,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_12/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_11/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -267656,7 +267587,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[0]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[14]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -267666,7 +267597,7 @@ L3;1 L4;1 Inst -u_zoom_image/N290_8/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[10]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -267676,7 +267607,7 @@ L3;1 L4;1 Inst -u_zoom_image/N234_0/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -267686,7 +267617,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_11/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[15]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -267696,7 +267627,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[4]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[3]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -267716,7 +267647,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[5]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[8]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -267726,7 +267657,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[12]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[9]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -267736,7 +267667,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[8]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[15]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -267746,7 +267677,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N353_ac2/gateop_perm;gopLUT5 +u_axi_rst/N0/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -267756,7 +267687,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[15]/gateop_perm;gopLUT5 +u_rotate_image/N57_mux4_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -267766,7 +267697,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[10]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[12]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -267776,7 +267707,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[11]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[14]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -267786,27 +267717,39 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[14]/gateop_perm;gopLUT5 +u_rotate_image/cnt_h[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[9]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_bit_sel[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N15/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[15]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -267816,7 +267759,23 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_17_3/gateop_perm;gopLUT5 +u_clk50m_rst/rst/opit_0_L5Q_perm;gopL5Q +Pin +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 + +Inst +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N367/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -267826,7 +267785,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1094_3/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N455_32/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -267836,7 +267795,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N594_4/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N164_sum3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -267846,7 +267805,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N612_8/gateop_perm;gopLUT5 +u_ddr_addr_ctr/N72_12/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -267856,7 +267815,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1039_22[3]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_16[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -267866,7 +267825,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_10[5]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -267876,7 +267835,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_6[7]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1039_28_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -267886,7 +267845,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_16[7]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_53/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -267896,7 +267855,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N610/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_10[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -267906,7 +267865,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_8/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_10[3]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -267916,7 +267875,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_10[4]/gateop_perm;gopLUT5 +udp_osd_inst/char_buf_writer_inst/N165/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -267926,7 +267885,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N820_36[4]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_20/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -267936,7 +267895,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_10[1]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_28/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -268019,14 +267978,20 @@ S10;1 S11;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_12/gateop_perm;gopLUT5 +udp_osd_inst/char_buf_writer_inst/udp_rx_s_data_tready/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_16[3]_muxf6;gopMUX8TO1 @@ -268089,7 +268054,7 @@ S10;1 S11;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_36/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_16/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -268099,7 +268064,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_28/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N192/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -268109,7 +268074,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_32/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -268119,23 +268084,17 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[15]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[6]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[6]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -268145,17 +268104,23 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1731/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][16]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[3]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -268165,7 +268130,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[9]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[8]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -268175,7 +268140,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[8]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -268185,7 +268150,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_3[2]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[9]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -268195,7 +268160,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[5]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[5]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -268205,7 +268170,7 @@ L3;1 L4;1 Inst -udp_osd_inst/char_buf_writer_inst/N170/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[13]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -268215,7 +268180,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[10]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[5]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -268235,7 +268200,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[0]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[5]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -268245,7 +268210,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[2]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[13]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -268255,7 +268220,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_3[3]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[14]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -268265,27 +268230,39 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[15]/gateop_perm;gopLUT5 +ms72xx_ctl/ms7210_ctl/addr[1]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[15]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][13]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[12]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -268295,7 +268272,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N612_1/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -268305,7 +268282,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N409_16/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[9]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -268455,14 +268432,17 @@ I13;1 I14;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N937_2/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N328_1.fsub_15/gateop;gopA Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cout;2 +Y;2 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 Inst udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N329.lt_0/gateop_A2;gopA2 @@ -268865,23 +268845,17 @@ I13;1 I14;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/real_add_cnt[0]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[12]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N455_34/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1094_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -269111,23 +269085,17 @@ I13;1 I14;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[21]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N455_10/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N919_7_or[0]_3/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N455_22/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -269137,36 +269105,34 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[0]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[11]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_bit_sel[0]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[9]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N613_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N455_75_muxf6;gopMUX8TO1 @@ -269211,7 +269177,23 @@ S0;1 S1;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N604_4/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[2]/opit_0_L5Q_perm;gopL5Q +Pin +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 + +Inst +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -269221,7 +269203,57 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[13]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N604_12/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N604_14/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N135_6/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1036_9_5/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[12]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -269237,17 +269269,34 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N603/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N609_5/gateop;gopMUX4TO1 Pin +F;2 +I0;1 +I1;1 +I2;1 +I3;1 +S0;1 +S1;1 + +Inst +ms72xx_ctl/iic_dri_tx/state_reg[2]/opit_0_inv_L5Q_perm;gopL5Q +Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N609_6/gateop;gopMUX4TO1 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N611_5/gateop;gopMUX4TO1 Pin F;2 I0;1 @@ -269258,7 +269307,7 @@ S0;1 S1;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1039_26[0]_1/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_rx/state_fsm[2:0]_70/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -269268,7 +269317,7 @@ L3;1 L4;1 Inst -ms72xx_ctl/iic_dri_rx/N72/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N915/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -269278,7 +269327,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N611_14/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N259_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -269288,23 +269337,17 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/change_to_read/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/iic_dri_tx/N39/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N611_9/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_18/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -269314,7 +269357,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N611_17/gateop;gopMUX4TO1 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N623_3/gateop;gopMUX4TO1 Pin F;2 I0;1 @@ -269325,7 +269368,7 @@ S0;1 S1;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N958_2/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_tx/N80_0/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -269335,7 +269378,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_6[2]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N940/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -269345,7 +269388,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N622_3/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1066_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -269355,7 +269398,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N620/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[10]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -269365,7 +269408,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1036_9_5/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[15]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -269375,7 +269418,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N191_1/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N2622_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -269385,18 +269428,17 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N623_3/gateop;gopMUX4TO1 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N310_1_or[0]_9/gateop_perm;gopLUT5 Pin -F;2 -I0;1 -I1;1 -I2;1 -I3;1 -S0;1 -S1;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N919_8/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[3]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -269406,7 +269448,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N191_2/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -269416,7 +269458,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_10[0]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[7]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -269426,7 +269468,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N940/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -269436,7 +269478,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_53/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N703_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -269446,7 +269488,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[3]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_3[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -269456,17 +269498,23 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[4]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/trig_tx_en/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[6]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -269476,7 +269524,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[14]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_16/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -269486,17 +269534,23 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[5]/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_tx/send_data[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[7]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1731/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -269506,7 +269560,17 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][0]/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/iic_dri_tx/N461_8_or[1][2]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[6]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -269522,7 +269586,37 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[11]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[13]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N114_5/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_3[3]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -269538,7 +269632,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[9]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N114_24/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -269548,7 +269642,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[13]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_3[16]/gateop;gopLUT5 Pin Z;2 L0;1 @@ -269558,7 +269652,23 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[11]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[1]/opit_0_L5Q_perm;gopL5Q +Pin +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 + +Inst +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[15]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -269568,7 +269678,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[12]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[7]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -269578,7 +269688,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[13]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[3]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -269588,7 +269698,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[14]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -269598,7 +269708,7 @@ L3;1 L4;1 Inst -udp_osd_inst/char_buf_writer_inst/N138/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1127_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -269608,7 +269718,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_3[0]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1014_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -269618,17 +269728,23 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_3[1]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][13]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_3[16]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_12/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -269638,7 +269754,17 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][5]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[10]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -269654,7 +269780,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[10]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[6]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -269664,7 +269790,7 @@ L3;1 L4;1 Inst -udp_osd_inst/char_buf_writer_inst/cnt[15:0]_6/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[11]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -269674,7 +269800,43 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[8]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[2]/opit_0_L5Q_perm;gopL5Q +Pin +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 + +Inst +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[12]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[14]/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[16]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -269700,23 +269862,17 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][2]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[2]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[9]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_17_14/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -269726,7 +269882,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][4]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -269742,57 +269898,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[4]/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[10]/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[6]/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[12]/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[9]/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[1]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -269802,27 +269908,39 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[0]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[5]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[11]/gateop_perm;gopLUT5 +sync_vg_100m/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][8]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -269838,7 +269956,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[2]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N665_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -269848,7 +269966,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[12]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[10]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -269868,148 +269986,27 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[13]/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[3]/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[4]/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -u_sync_vg/N23_1_9/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[8]/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[6]/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[7]/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[5]/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[4]/opit_0_L5Q_perm;gopL5Q -Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 - -Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[10]/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -udp_osd_inst/char_buf_writer_inst/state_reg[0]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[7]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][7]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[8]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][13]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -270025,17 +270022,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[15]/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[14]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -270045,7 +270032,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N249_2/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[1]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -270055,23 +270042,17 @@ L3;1 L4;1 Inst -udp_osd_inst/char_buf_writer_inst/cnt[1]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[11]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1066_7/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_tx/N165_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -270081,7 +270062,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N164_sum3/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_rx/N316_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -270459,7 +270440,7 @@ S0;1 S1;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1039_22[2]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1039_22[5]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -270469,33 +270450,33 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/crc_en/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1039_22[3]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1039_22[6]/gateop_perm;gopLUT5 +ms72xx_ctl/ms7200_ctl/state_reg[1]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1039_28_4/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1039_22[4]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -270505,7 +270486,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1039_24[0]_1/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1039_22[6]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -270515,7 +270496,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1039_22[1]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1039_22[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -270525,7 +270506,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1039_22[5]/gateop_perm;gopLUT5 +ms72xx_ctl/ms7200_ctl/N1895/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -270535,20 +270516,14 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_eth_ctrl/arp_tx_en/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N173_6/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1039_24[7]_2/gateop;gopMUX4TO1 @@ -270562,7 +270537,7 @@ S0;1 S1;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_24/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1066_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -270572,7 +270547,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_10[3]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N282/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -270582,7 +270557,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cnt[2]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -270609,7 +270584,7 @@ S0;1 S1;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N619_2/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N81/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -270619,53 +270594,65 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N455_22/gateop_perm;gopLUT5 +u_zoom_rst/rst/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N455_32/gateop_perm;gopLUT5 +ms72xx_ctl/ms7200_ctl/state_reg[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[10]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_39/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[2]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[10]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -270681,7 +270668,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N2622_2/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N10_cpy/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -270691,7 +270678,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][16]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/real_add_cnt[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -272691,7 +272678,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cnt[3]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cnt[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -272707,46 +272694,40 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N164_sum2/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cnt[4]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cnt[4]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N260_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[8]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N919_8/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/crc_clr/opit_0;gopQ @@ -272760,7 +272741,7 @@ D;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/gmii_txd_valid/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_done_t/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -272776,7 +272757,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[6]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -272792,7 +272773,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[2]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -272808,7 +272789,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/trig_tx_en/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -272840,23 +272821,17 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[5]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N609_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_req/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/iic_dri_tx/trans_bit[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -272872,30 +272847,30 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[7]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N919_7_or[3]_4/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1066_2/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[7]/opit_0_L5Q;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[15]/opit_0_AQ_perm;gopAQ @@ -273106,7 +273081,7 @@ I14;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[13]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_16_14/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -273780,7 +273755,7 @@ S0;1 S1;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_done_t/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_req/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -273972,20 +273947,14 @@ D;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[23]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[3]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][18]/opit_0_A2Q21;gopA2Q2 @@ -274177,14 +274146,23 @@ I14;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N409_8/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][31]/opit_0_AQ;gopAQ Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +CEOUT;2 +Cout;2 +Q;2 +RSOUT;2 +Y;2 +CE;1 +CLK;1 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 +RS;1 Inst udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][1]/opit_0_L5Q_perm;gopL5Q @@ -274203,7 +274181,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][2]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -274219,7 +274197,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][3]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -274251,23 +274229,17 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][6]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[12]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][8]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -274283,7 +274255,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[13]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][12]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -274299,7 +274271,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][12]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][7]/opit_0_L5Q;gopL5Q Pin CEOUT;2 Q;2 @@ -274347,17 +274319,23 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[7]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][11]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][11]/opit_0_L5Q;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -274373,7 +274351,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][15]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][14]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -274389,7 +274367,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][14]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][15]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -274405,24 +274383,36 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_48[13]/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_tx/send_data[4]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_3[8]/gateop_perm;gopLUT5 +ms72xx_ctl/ms7210_ctl/addr[3]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][0]/opit_0;gopQ @@ -274793,7 +274783,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][1]/opit_0_L5Q;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -274809,17 +274799,23 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[3]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][3]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][3]/opit_0_L5Q;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -274835,23 +274831,17 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][7]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[7]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][5]/opit_0_L5Q;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -274867,7 +274857,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][6]/opit_0_L5Q;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -274883,17 +274873,23 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[14]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][10]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][9]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][8]/opit_0_L5Q;gopL5Q Pin CEOUT;2 Q;2 @@ -274909,7 +274905,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][10]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][11]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -274925,7 +274921,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][11]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][9]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -274957,7 +274953,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][13]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][15]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -274973,17 +274969,23 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[15]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][14]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][14]/opit_0_L5Q;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/real_add_cnt[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -274999,7 +275001,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][15]/opit_0_L5Q;gopL5Q +u_hdmi_rst/rst/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -275367,14 +275369,20 @@ D;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1109/gateop_perm;gopLUT5 +ms72xx_ctl/ms7210_ctl/addr[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/real_add_cnt[2]/opit_0_L5Q_perm;gopL5Q @@ -275425,20 +275433,14 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[1]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N961/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/skip_en/opit_0_MUX4TO1Q;gopMUX4TO1Q @@ -275513,14 +275515,20 @@ D;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[0]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][8]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[4]/opit_0_A2Q21;gopA2Q2 @@ -275704,7 +275712,7 @@ I4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N455_7/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N338_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -275714,20 +275722,14 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[3]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[13]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_bit_sel[1]/opit_0_MUX4TO1Q;gopMUX4TO1Q @@ -275901,23 +275903,17 @@ D;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[12]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N173_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cnt[0]/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/iic_dri_tx/busy/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -275933,7 +275929,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N460/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N591_14_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -275943,7 +275939,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N364/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N127_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -275953,18 +275949,17 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N90/gateop;gopMUX4TO1 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839/gateop_perm;gopLUT5 Pin -F;2 -I0;1 -I1;1 -I2;1 -I3;1 -S0;1 -S1;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_16_14/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_16_30/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -275974,7 +275969,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N119_41/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_17_33/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -275984,14 +275979,20 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_17_10/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[3]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_17_14/gateop_perm;gopLUT5 @@ -276004,17 +276005,23 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_17_18/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[1]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_16_33/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_17_18/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -276024,7 +276031,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_17_26/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_16_33/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -276034,7 +276041,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_17_6/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_17_29/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -276044,7 +276051,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_17_29/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_16_18/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -276054,7 +276061,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_17_22/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N119_41/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -276064,7 +276071,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N52/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_17_26/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -276074,7 +276081,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N119_37/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N119_47/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -276084,7 +276091,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_17_33/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_17_22/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -276094,7 +276101,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_16_26/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_16_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -276104,7 +276111,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_16_22/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N119_37/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -276114,7 +276121,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N123_16_14/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_17_10/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -276124,7 +276131,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N436_22/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N403_69/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -276134,7 +276141,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_16_28/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_15/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -276144,7 +276151,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N319_3/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N630_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -276154,7 +276161,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N308_15_3/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N119_44/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -276164,7 +276171,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N119_44/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N602_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -276174,7 +276181,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_16_30/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_17_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -276184,7 +276191,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_16_5/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N119_49/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -276194,14 +276201,20 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N119_29/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_pkt_start/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N310_1_or[0]_2_3/gateop_perm;gopLUT5 @@ -276214,7 +276227,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1014_1/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N431/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -276234,7 +276247,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N175_46/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N665_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -276244,7 +276257,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N175_50/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N175_46/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -276254,7 +276267,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N175_30/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N308_65/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -276264,24 +276277,36 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N462_24/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_cnt[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N591_14_2/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[1]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_1/gateop_A2;gopA2 @@ -276528,17 +276553,7 @@ S0;1 S1;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N432_3/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N859_3/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N119_29/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -276548,14 +276563,20 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N191_and[0]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[4]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N308_18_3/gateop;gopMUX4TO1 @@ -276569,23 +276590,17 @@ S0;1 S1;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt[3]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N433/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[8]/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/ms7210_ctl/addr[4]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -276601,23 +276616,17 @@ L4;1 RS;1 Inst -param_manager_inst/osd_startX_load/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N195_28/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N308_68/gateop;gopMUX4TO1 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N308_70/gateop;gopMUX4TO1 Pin F;2 I0;1 @@ -276628,7 +276637,7 @@ S0;1 S1;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N308_69/gateop;gopMUX4TO1 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N308_71/gateop;gopMUX4TO1 Pin F;2 I0;1 @@ -276639,7 +276648,7 @@ S0;1 S1;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N308_70/gateop;gopMUX4TO1 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N308_72/gateop;gopMUX4TO1 Pin F;2 I0;1 @@ -276650,20 +276659,14 @@ S0;1 S1;1 Inst -u_zoom_image/imag_addr0[0]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N308_24/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N310_1_or[0]_5/gateop;gopMUX4TO1 @@ -276677,7 +276680,7 @@ S0;1 S1;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N310_1_or[0]_7/gateop;gopMUX4TO1 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N310_1_or[0]_8/gateop;gopMUX4TO1 Pin F;2 I0;1 @@ -276688,17 +276691,7 @@ S0;1 S1;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N619_6/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - -Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N114_4/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N697_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -276708,7 +276701,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N665_6/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N434_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -276729,18 +276722,23 @@ S0;1 S1;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N429_4/gateop;gopMUX4TO1 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_done_cdc/out/opit_0_L5Q_perm;gopL5Q Pin -F;2 -I0;1 -I1;1 -I2;1 -I3;1 -S0;1 -S1;1 +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N588_4/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N584_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -276750,7 +276748,17 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N602_3/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N308_11_3/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N460/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -276760,7 +276768,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N289_1/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N70_ac2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -276781,7 +276789,7 @@ S0;1 S1;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N308_24/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N588_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -276791,23 +276799,17 @@ L3;1 L4;1 Inst -u_zoom_image/imag_addr0[2]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N175_30/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N308_11_3/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N889/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -276817,18 +276819,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N591_14_3/gateop;gopMUX4TO1 -Pin -F;2 -I0;1 -I1;1 -I2;1 -I3;1 -S0;1 -S1;1 - -Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N889/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N820_36[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -276838,7 +276829,7 @@ L3;1 L4;1 Inst -param_manager_inst/selected[12]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -276854,7 +276845,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N60_mux3_5/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N697_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -276864,7 +276855,7 @@ L3;1 L4;1 Inst -u_zoom_image/imag_addr1[3]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_done_cdc/in_req/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -276880,7 +276871,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_osd_startX/cnt[5]/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/ms7210_ctl/cmd_index[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -276896,7 +276887,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N402_1/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N219_63[2]_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -276906,7 +276897,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N878_2/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N859_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -276916,7 +276907,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N421/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -276926,18 +276917,17 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N757/gateop;gopMUX4TO1 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N748/gateop_perm;gopLUT5 Pin -F;2 -I0;1 -I1;1 -I2;1 -I3;1 -S0;1 -S1;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst -param_manager_inst/key_debounce_key_left/N47_13/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N943/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -276947,7 +276937,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N434_4/gateop_perm;gopLUT5 +udp_wr_mem_inst/N549_29/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -276957,17 +276947,34 @@ L3;1 L4;1 Inst -param_manager_inst/key_debounce_key_left/N47_1/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[9]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N119_49/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N757/gateop;gopMUX4TO1 +Pin +F;2 +I0;1 +I1;1 +I2;1 +I3;1 +S0;1 +S1;1 + +Inst +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N878_4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -276977,7 +276984,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt[1]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -276993,7 +277000,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt[2]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[8]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -277009,17 +277016,23 @@ L4;1 RS;1 Inst -param_manager_inst/param_offsetX/N139_3/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt[1]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt[4]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -277035,7 +277048,7 @@ L4;1 RS;1 Inst -u_zoom_image/imag_addr0[1]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -277051,17 +277064,23 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_16_10/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt[3]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[1]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -277077,7 +277096,27 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[3]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N175_34/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N72_mux3/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -277093,7 +277132,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[4]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -277109,7 +277148,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/error_en/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -277125,7 +277164,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[6]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/error_en/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -277141,7 +277180,17 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_en/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N575_1/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -277157,14 +277206,20 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1123_3/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_en/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[0]/opit_0;gopQ @@ -277200,7 +277255,7 @@ D;1 RS;1 Inst -udp_wr_mem_inst/N44_11/gateop_perm;gopLUT5 +udp_wr_mem_inst/N549_33/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -277580,20 +277635,14 @@ I14;1 RS;1 Inst -param_manager_inst/param_rotate/cnt[0]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N289_6/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[0]/opit_0;gopQ @@ -278388,7 +278437,7 @@ D;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N436_66/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N191_and[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -278486,7 +278535,7 @@ D;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[2]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[9]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -278518,7 +278567,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[5]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -278534,7 +278583,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[4]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[7]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -278550,7 +278599,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[6]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -278566,7 +278615,7 @@ L4;1 RS;1 Inst -udp_wr_mem_inst/flags[22]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -278582,7 +278631,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[9]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[8]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -278598,7 +278647,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[8]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[2]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -278614,7 +278663,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[10]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[9]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -278630,17 +278679,23 @@ L4;1 RS;1 Inst -udp_wr_mem_inst/N504/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[10]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[13]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[11]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -278656,7 +278711,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[12]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[10]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -278672,7 +278727,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[14]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[13]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -278688,7 +278743,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[11]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[14]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -278720,20 +278775,14 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_cnt[0]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N766_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_data[0]/opit_0;gopQ @@ -278824,39 +278873,27 @@ D;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_pkt_done/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N127_4/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_pkt_start/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/N72_18/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N866_7/gateop_perm;gopLUT5 +udp_wr_mem_inst/N549_21/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -279323,17 +279360,23 @@ S0;1 S1;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[1]_1/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[10]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[2]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -279343,7 +279386,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[1]/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_tx/state_fsm[2:0]_31/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -279353,7 +279396,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N135_7/gateop_perm;gopLUT5 +u_ddr_addr_ctr/N72_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -279363,7 +279406,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N327/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N140_25/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -279383,27 +279426,39 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N140_29/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/rd_cnt[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_rotate_A/N63_mux9_8/gateop_perm;gopLUT5 +udp_osd_inst/char_buf_writer_inst/cnt[1]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N173_3/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N321/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -279413,7 +279468,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N321/gateop_perm;gopLUT5 +udp_osd_inst/char_buf_writer_inst/N138/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -279423,7 +279478,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N173_6/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N135_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -279433,7 +279488,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/rd_cnt[0]/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/ms7200_ctl/init_over/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -279449,17 +279504,23 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N915/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/pkt_num[0]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N260_1/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N249_6/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -279469,20 +279530,15 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt[0]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N192_1/gateop;gopMUX4TO1 Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 +F;2 +I0;1 +I1;1 +I2;1 +I3;1 +S0;1 +S1;1 Inst udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N249_1/gateop;gopMUX4TO1 @@ -279496,27 +279552,39 @@ S0;1 S1;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N964_2[7]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/fifo_rd_num_en/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N260_3/gateop_perm;gopLUT5 +u_ddr_addr_ctr/vs_30hz/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -ms72xx_ctl/iic_dri_rx/N504/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N455_34/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -279526,7 +279594,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_16[6]/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_rx/N313_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -279536,28 +279604,23 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N259_2/gateop_perm;gopLUT5 +udp_osd_inst/char_buf_writer_inst/ram_din[2]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N281_7[0]_1/gateop;gopMUX4TO1 -Pin -F;2 -I0;1 -I1;1 -I2;1 -I3;1 -S0;1 -S1;1 - -Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt[1]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -279573,7 +279636,7 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7210_ctl/N62_sum4/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N338_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -279583,7 +279646,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/fifo_rd_num_en/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[25]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -279599,23 +279662,27 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/pkt_num[0]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N612_10/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -ms72xx_ctl/iic_dri_rx/N310_7/gateop_perm;gopLUT5 +udp_osd_inst/char_buf_writer_inst/N138_20/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N220_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -279641,33 +279708,30 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N611_12/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt[1]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt[15]/opit_0_AQ_perm;gopAQ +ms72xx_ctl/iic_dri_rx/N72/gateop_perm;gopLUT5 Pin -CEOUT;2 -Cout;2 -Q;2 -RSOUT;2 -Y;2 -CE;1 -CLK;1 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 -RS;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt[2]/opit_0_A2Q1;gopA2Q1 @@ -279858,19 +279922,22 @@ I14;1 RS;1 Inst -ms72xx_ctl/iic_dri_rx/scl_out/opit_0_inv_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt[15]/opit_0_AQ;gopAQ Pin CEOUT;2 +Cout;2 Q;2 RSOUT;2 -Z;2 +Y;2 CE;1 CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 +Cin;1 +I0;1 +I0X;1 +I1;1 +I2;1 +I3;1 +I4;1 RS;1 Inst @@ -280051,24 +280118,36 @@ I14;1 RS;1 Inst -udp_osd_inst/char_buf_writer_inst/N189_1/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/crc_en/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/char_buf_writer_inst/N138_24/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_rx/state_reg[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/rd_cnt[1]/opit_0_A2Q1;gopA2Q1 @@ -280286,7 +280365,7 @@ I14;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N192/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N120_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -280521,7 +280600,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N135_6/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N604_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -280531,7 +280610,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_rotate_A/N148_1/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N175_38/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -280563,7 +280642,7 @@ D;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[0]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/data_cnt[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -280579,7 +280658,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[7]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/data_cnt[4]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -280643,17 +280722,23 @@ I14;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[5]_1/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_14/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N594_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -280824,7 +280909,7 @@ I14;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -280840,30 +280925,30 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[3]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_4/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm;gopL5Q @@ -280882,7 +280967,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[4]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_8[3]_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -280892,7 +280977,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -280908,7 +280993,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -280924,23 +281009,17 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N106_9/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -280956,33 +281035,33 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_12/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[11]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[11]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N958_2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -param_manager_inst/param_modify_V/N63_mux8_6/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[8]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -281124,24 +281203,36 @@ D;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[0]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[4]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[2]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_L5Q_perm;gopL5Q @@ -281176,7 +281267,17 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N937_2/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -281192,7 +281293,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[8]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -281208,7 +281309,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[14]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -281218,7 +281319,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[8]/opit_0_inv_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[10]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -281234,7 +281335,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -281250,59 +281351,40 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[10]/opit_0_inv_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N604_16/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/N6.lt_4/gateop_perm;gopA -Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 - -Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/divisor_kp[2]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N603/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[0]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_MUX4TO1Q;gopMUX4TO1Q @@ -281474,7 +281556,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[7]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -281729,17 +281811,23 @@ I3;1 I4;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[8]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[13]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_modify_H/N76_mux8_2/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[3]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -281749,23 +281837,27 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N943_2[10]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/modified_h_data[6]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[5]_1/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[14]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -281781,7 +281873,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N106_8/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N282_32/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -281791,23 +281883,17 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[1]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_20/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[3]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -281817,23 +281903,17 @@ L3;1 L4;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[13].u_divider_step/remainder[0]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[8]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N205_43[2]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_20/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -281843,7 +281923,7 @@ L3;1 L4;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/N58_mux9/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_12/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -281853,7 +281933,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_4/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_tx/N489_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -281863,23 +281943,17 @@ L3;1 L4;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/modified_v_data[0]/opit_0_L5Q_perm;gopL5Q +u_zoom_image/N368_mux4/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/N133_inv/gateop_perm;gopLUT5 +u_ddr_addr_ctr/N72_17/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -281889,7 +281963,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N106_4/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[8]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -281899,7 +281973,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_16/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[1]_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -281909,7 +281983,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_18/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N106_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -281919,36 +281993,24 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N164_sum2/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[2]/opit_0_inv_L5Q_perm;gopL5Q +udp_wr_mem_inst/N538_16/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[6]/gateop_perm;gopLUT5 @@ -281961,7 +282023,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[2]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[2]/gateop;gopLUT5 Pin Z;2 L0;1 @@ -281971,20 +282033,14 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[0]/opit_0_inv_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/N72_26/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[5]/gateop_perm;gopLUT5 @@ -281997,7 +282053,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[7]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N15/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -282007,7 +282063,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N24_14/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -282017,33 +282073,33 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/opit_0_inv_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N106_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N106_6/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N106_2/gateop_perm;gopLUT5 +ms72xx_ctl/iic_dri_tx/N460/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -282053,7 +282109,7 @@ L3;1 L4;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/N46_mux9/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N106_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -282063,23 +282119,17 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_start_i_ff/opit_0_L5Q_perm;gopL5Q +ms72xx_ctl/iic_dri_tx/N493_or[0]_3/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -param_manager_inst/param_modify_V/N76_mux8_8/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[9]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -282089,23 +282139,17 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N106_7/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N106_10/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N610/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -282115,7 +282159,7 @@ L3;1 L4;1 Inst -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cnt[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -282130,16 +282174,6 @@ L3;1 L4;1 RS;1 -Inst -param_manager_inst/param_modify_H/N63_mux8_2/gateop_perm;gopLUT5 -Pin -Z;2 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 - Inst udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167.eq_0/gateop_A2;gopA2 Pin @@ -282744,7 +282778,7 @@ WR_EOP;1 WR_ERR;1 Inst -param_manager_inst/param_modify_V/N63_mux8_7/gateop_perm;gopLUT5 +udp_wr_mem_inst/N695_8/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -282765,55 +282799,7 @@ D;1 RS;1 Inst -udp_osd_inst/rgb_out[1]/opit_0_L5Q_perm;gopL5Q -Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 - -Inst -udp_osd_inst/rgb_out[9]/opit_0_L5Q_perm;gopL5Q -Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 - -Inst -udp_osd_inst/rgb_out[4]/opit_0_L5Q_perm;gopL5Q -Pin -CEOUT;2 -Q;2 -RSOUT;2 -Z;2 -CE;1 -CLK;1 -L0;1 -L1;1 -L2;1 -L3;1 -L4;1 -RS;1 - -Inst -udp_osd_inst/rgb_out[17]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/rgb_out[16]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -282845,7 +282831,7 @@ L4;1 RS;1 Inst -udp_osd_inst/rgb_out[11]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/rgb_out[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -282861,7 +282847,7 @@ L4;1 RS;1 Inst -udp_osd_inst/rgb_out[12]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/rgb_out[19]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -282877,7 +282863,7 @@ L4;1 RS;1 Inst -udp_osd_inst/rgb_out[20]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/rgb_out[9]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -282893,7 +282879,7 @@ L4;1 RS;1 Inst -u_sync_vg/hdmi_image_data0[1]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/rgb_out[13]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -282909,7 +282895,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[4]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/rgb_out[11]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -282925,7 +282911,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/remainder[2]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/rgb_out[17]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -282941,7 +282927,7 @@ L4;1 RS;1 Inst -udp_osd_inst/rgb_out[18]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/rgb_out[12]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -282957,7 +282943,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[4].u_divider_step/divisor_kp[0]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/rgb_out[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -282973,7 +282959,7 @@ L4;1 RS;1 Inst -udp_osd_inst/rgb_out[19]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/rgb_out[18]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -282989,7 +282975,7 @@ L4;1 RS;1 Inst -udp_osd_inst/rgb_out[3]/opit_0_L5Q_perm;gopL5Q +u_sync_vg/hdmi_image_data0[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -283005,7 +282991,7 @@ L4;1 RS;1 Inst -adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[7].u_divider_step/remainder[7]/opit_0_L5Q_perm;gopL5Q +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[0]/opit_0_inv_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -283021,28 +283007,23 @@ L4;1 RS;1 Inst -udp_osd_inst/vs_out/opit_0;gopQ +u_sync_vg/hdmi_image_data0[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 RSOUT;2 +Z;2 CE;1 CLK;1 -D;1 -RS;1 - -Inst -udp_wr_mem_inst/N224/gateop_perm;gopLUT5 -Pin -Z;2 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_zoom/value[3]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/rgb_out[20]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -283058,7 +283039,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_offsetX/pluse/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/rgb_out[10]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -283074,23 +283055,48 @@ L4;1 RS;1 Inst -udp_wr_mem_inst/flags[3]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/vs_out/opit_0;gopQ Pin CEOUT;2 Q;2 RSOUT;2 -Z;2 CE;1 CLK;1 +D;1 +RS;1 + +Inst +udp_wr_mem_inst/N30_1.fsub_1/gateop_A2;gopA2 +Pin +Cout;2 +Y0;2 +Y1;2 +Cin;1 +I0X;1 +I1X;1 +I00;1 +I01;1 +I02;1 +I03;1 +I04;1 +I10;1 +I11;1 +I12;1 +I13;1 +I14;1 + +Inst +udp_wr_mem_inst/N404/gateop_perm;gopLUT5 +Pin +Z;2 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_wr_mem_inst/N695_8/gateop_perm;gopLUT5 +udp_wr_mem_inst/N324/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -283100,39 +283106,27 @@ L3;1 L4;1 Inst -udp_wr_mem_inst/flags[4]/opit_0_L5Q_perm;gopL5Q +udp_wr_mem_inst/N124/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -param_manager_inst/param_offsetX/cnt[4]/opit_0_L5Q_perm;gopL5Q +udp_wr_mem_inst/N104/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -param_manager_inst/param_osd_startX/N148_5/gateop_perm;gopLUT5 +udp_wr_mem_inst/N44_11/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -283142,7 +283136,17 @@ L3;1 L4;1 Inst -udp_wr_mem_inst/flags[7]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_rotate/N152_1/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +udp_wr_mem_inst/flags[6]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -283158,7 +283162,7 @@ L4;1 RS;1 Inst -udp_wr_mem_inst/flags[8]/opit_0_L5Q_perm;gopL5Q +udp_wr_mem_inst/flags[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -283174,7 +283178,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_filiter1_mode/N119/gateop_perm;gopLUT5 +udp_wr_mem_inst/N264/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -283184,7 +283188,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_rotate/N152_5_9/gateop_perm;gopLUT5 +udp_wr_mem_inst/N224/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -283204,23 +283208,17 @@ L3;1 L4;1 Inst -udp_wr_mem_inst/flags[12]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_osd_char_width/N63_mux10_7/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_wr_mem_inst/N524_4/gateop_perm;gopLUT5 +param_manager_inst/param_osd_char_width/N154_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -283230,17 +283228,23 @@ L3;1 L4;1 Inst -udp_wr_mem_inst/N524_2/gateop_perm;gopLUT5 +udp_wr_mem_inst/flags[10]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_osd_char_height/value[0]/opit_0_L5Q_perm;gopL5Q +udp_wr_mem_inst/flags[13]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -283256,23 +283260,17 @@ L4;1 RS;1 Inst -param_manager_inst/param_osd_char_width/value[1]/opit_0_L5Q_perm;gopL5Q +udp_wr_mem_inst/N727/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_wr_mem_inst/N404/gateop_perm;gopLUT5 +udp_wr_mem_inst/N44/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -283282,23 +283280,17 @@ L3;1 L4;1 Inst -param_manager_inst/param_osd_startX/value[2]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_filiter1_mode/N152_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_wr_mem_inst/N444/gateop_perm;gopLUT5 +image_filiter_inst/hybrid_filter_inst/N106_91/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -283308,33 +283300,33 @@ L3;1 L4;1 Inst -udp_wr_mem_inst/index[0]/opit_0_L5Q_perm;gopL5Q +udp_wr_mem_inst/N695_6/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_wr_mem_inst/N549_29/gateop_perm;gopLUT5 +udp_wr_mem_inst/flags[19]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_zoom/N63_mux9_9/gateop_perm;gopLUT5 +udp_wr_mem_inst/N464/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -283344,7 +283336,7 @@ L3;1 L4;1 Inst -udp_wr_mem_inst/N549_25/gateop_perm;gopLUT5 +param_manager_inst/param_rotate_A/N148_5/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -283354,17 +283346,23 @@ L3;1 L4;1 Inst -udp_wr_mem_inst/N524_3/gateop_perm;gopLUT5 +udp_wr_mem_inst/flags[22]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_wr_mem_inst/flags[13]/opit_0_L5Q_perm;gopL5Q +udp_wr_mem_inst/flags[24]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -283380,7 +283378,7 @@ L4;1 RS;1 Inst -udp_wr_mem_inst/N84/gateop_perm;gopLUT5 +udp_wr_mem_inst/N524_2/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -283390,7 +283388,7 @@ L3;1 L4;1 Inst -udp_wr_mem_inst/N524_10/gateop_perm;gopLUT5 +udp_wr_mem_inst/N524_3/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -283400,7 +283398,7 @@ L3;1 L4;1 Inst -udp_wr_mem_inst/pkt_data_cnt[0]/opit_0_L5Q_perm;gopL5Q +udp_wr_mem_inst/index[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -283416,7 +283414,7 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/N72_24_cpy/gateop_perm;gopLUT5 +udp_wr_mem_inst/N524_1/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -283426,7 +283424,7 @@ L3;1 L4;1 Inst -udp_wr_mem_inst/flags[2]/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_filiter1_mode/key_debounce_inst2/cnt[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -283442,23 +283440,17 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[1]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N267_16[7]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_wr_mem_inst/N549_33/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[0]/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -283468,17 +283460,23 @@ L3;1 L4;1 Inst -udp_wr_mem_inst/N723/gateop_perm;gopLUT5 +u_zoom_image/wr_addr3[0]/opit_0_inv_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -u_ddr_rst/rst/opit_0_inv_L5Q_perm;gopL5Q +udp_wr_mem_inst/pkt_data_cnt[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -283494,7 +283492,7 @@ L4;1 RS;1 Inst -udp_wr_mem_inst/data_count[0]/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/arp_rx_done/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -283510,7 +283508,17 @@ L4;1 RS;1 Inst -ms72xx_ctl/ms7210_ctl/cmd_index[0]/opit_0_inv_L5Q_perm;gopL5Q +udp_wr_mem_inst/N723/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +udp_wr_mem_inst/data_count[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -283526,7 +283534,7 @@ L4;1 RS;1 Inst -param_manager_inst/param_zoom/N139_1/gateop_perm;gopLUT5 +udp_wr_mem_inst/N730/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -283536,7 +283544,7 @@ L3;1 L4;1 Inst -udp_wr_mem_inst/N730/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N90/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -283546,7 +283554,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_zoom/value[0]/opit_0_L5Q_perm;gopL5Q +udp_wr_mem_inst/flags[14]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -283562,49 +283570,62 @@ L4;1 RS;1 Inst -param_manager_inst/zoom_load/opit_0_L5Q_perm;gopL5Q +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_16_26/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -udp_wr_mem_inst/data_count[1]/opit_0_A2Q1;gopA2Q1 +udp_wr_mem_inst/data_count[7]/opit_0_AQ_perm;gopAQ Pin CEOUT;2 Cout;2 Q;2 RSOUT;2 -Y0;2 -Y1;2 +Y;2 CE;1 CLK;1 Cin;1 +I0;1 I0X;1 -I1X;1 -I00;1 -I01;1 -I02;1 -I03;1 -I04;1 -I10;1 -I11;1 -I12;1 -I13;1 -I14;1 +I1;1 +I2;1 +I3;1 +I4;1 RS;1 Inst -udp_wr_mem_inst/data_count[3]/opit_0_A2Q21;gopA2Q2 +udp_wr_mem_inst/data_count[2]/opit_0_L5Q_perm;gopL5Q +Pin +CEOUT;2 +Q;2 +RSOUT;2 +Z;2 +CE;1 +CLK;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 +RS;1 + +Inst +param_manager_inst/param_filiter1_mode/N59/gateop_perm;gopLUT5 +Pin +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 + +Inst +udp_wr_mem_inst/data_count[4]/opit_0_A2Q21;gopA2Q2 Pin CEOUT;2 Cout;2 @@ -283631,7 +283652,7 @@ I14;1 RS;1 Inst -udp_wr_mem_inst/data_count[5]/opit_0_A2Q21;gopA2Q2 +udp_wr_mem_inst/data_count[6]/opit_0_A2Q21;gopA2Q2 Pin CEOUT;2 Cout;2 @@ -283658,47 +283679,30 @@ I14;1 RS;1 Inst -udp_wr_mem_inst/data_count[7]/opit_0_A2Q21;gopA2Q2 +udp_wr_mem_inst/state_reg[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 -Cout;2 -Q0;2 -Q1;2 +Q;2 RSOUT;2 -Y0;2 -Y1;2 +Z;2 CE;1 CLK;1 -Cin;1 -I0X;1 -I1X;1 -I00;1 -I01;1 -I02;1 -I03;1 -I04;1 -I10;1 -I11;1 -I12;1 -I13;1 -I14;1 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 RS;1 Inst -param_manager_inst/filiter1_mode_load/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_filiter1_mode/value[2:0]_5/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst udp_wr_mem_inst/flags[1]/opit_0_L5Q;gopL5Q @@ -283717,27 +283721,39 @@ L4;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/N72_23/gateop_perm;gopLUT5 +param_manager_inst/param_offsetX/pluse/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_zoom/N63_mux9_8/gateop_perm;gopLUT5 +param_manager_inst/param_filiter1_mode/key_debounce_inst1/pressed/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_rotate/N58/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N402_74/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -283747,7 +283763,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_osd_startX/N139/gateop_perm;gopLUT5 +param_manager_inst/param_osd_startX/N63_mux10_7/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -283757,7 +283773,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_osd_startX/N149_43_1/gateop_perm;gopLUT5 +param_manager_inst/param_osd_startX/N139/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -283767,7 +283783,7 @@ L3;1 L4;1 Inst -param_manager_inst/param_osd_startY/N149_38/gateop_perm;gopLUT5 +param_manager_inst/param_osd_char_height/N63_mux4/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -283777,14 +283793,20 @@ L3;1 L4;1 Inst -param_manager_inst/param_rotate/N152_5_6/gateop_perm;gopLUT5 +udp_wr_mem_inst/flags[8]/opit_0_L5Q;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst udp_wr_mem_inst/flags[9]/opit_0_L5Q;gopL5Q @@ -283803,33 +283825,33 @@ L4;1 RS;1 Inst -param_manager_inst/param_osd_char_height/N156_1/gateop_perm;gopLUT5 +param_manager_inst/param_osd_char_width/value[1]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_wr_mem_inst/flags[11]/opit_0_L5Q;gopL5Q +param_manager_inst/key_debounce_key_left/N47_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -param_manager_inst/param_osd_char_width/N63_mux3/gateop_perm;gopLUT5 +param_manager_inst/param_osd_char_height/N138/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -283839,7 +283861,7 @@ L3;1 L4;1 Inst -image_filiter_inst/hybrid_filter_inst/N162_89/gateop_perm;gopLUT5 +param_manager_inst/param_rotate_A/N63_mux9_9/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -283849,7 +283871,7 @@ L3;1 L4;1 Inst -param_manager_inst/rotate_A_load/opit_0_L5Q_perm;gopL5Q +param_manager_inst/param_rotate_A/value[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -283865,7 +283887,7 @@ L4;1 RS;1 Inst -param_manager_inst/offsetX_load/opit_0_L5Q_perm;gopL5Q +u_rotate_image/image_w_blank_valid/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -283881,7 +283903,7 @@ L4;1 RS;1 Inst -udp_wr_mem_inst/flags[16]/opit_0_L5Q;gopL5Q +param_manager_inst/param_offsetY/value[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -283897,30 +283919,30 @@ L4;1 RS;1 Inst -param_manager_inst/param_osd_char_height/N63_mux10_4/gateop_perm;gopLUT5 +param_manager_inst/filiter1_mode_load/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -udp_wr_mem_inst/flags[18]/opit_0_L5Q;gopL5Q +param_manager_inst/param_modify_H/N148_1/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst param_manager_inst/modify_H_load/opit_0_L5Q_perm;gopL5Q @@ -283939,7 +283961,7 @@ L4;1 RS;1 Inst -udp_wr_mem_inst/flags[20]/opit_0_L5Q;gopL5Q +adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/modified_s_data[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -283971,17 +283993,23 @@ L4;1 RS;1 Inst -param_manager_inst/param_modify_S/N139_2/gateop_perm;gopLUT5 +adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/modified_s_data[1]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -param_manager_inst/param_modify_V/value[0]/opit_0_L5Q_perm;gopL5Q +udp_wr_mem_inst/flags[23]/opit_0_L5Q;gopL5Q Pin CEOUT;2 Q;2 @@ -283997,30 +284025,30 @@ L4;1 RS;1 Inst -udp_wr_mem_inst/flags[24]/opit_0_L5Q;gopL5Q +param_manager_inst/param_rotate/N102_9/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -param_manager_inst/param_modify_H/N72/gateop_perm;gopLUT5 +param_manager_inst/param_rotate/pluse/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst udp_wr_mem_inst/index[1]/opit_0_A2Q1;gopA2Q1 @@ -285549,17 +285577,14 @@ D;1 RS;1 Inst -param_manager_inst/param_zoom/N149_10_9/gateop_perm;gopA +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N697_5/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst udp_wr_mem_inst/pkt_data_cnt[1]/opit_0_A2Q1;gopA2Q1 @@ -285810,7 +285835,7 @@ L4;1 RS;1 Inst -udp_wr_mem_inst/N695_6/gateop_perm;gopLUT5 +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N113_16_22/gateop_perm;gopLUT5 Pin Z;2 L0;1 @@ -285933,7 +285958,7 @@ L4;1 RS;1 Inst -vs_down_delay_cnt[11]/opit_0_L5Q_perm;gopL5Q +vs_pos_delay_cnt[3]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -285949,7 +285974,7 @@ L4;1 RS;1 Inst -vs_pos_delay_cnt[6]/opit_0_L5Q_perm;gopL5Q +vs_down_delay_cnt[10]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -285965,7 +285990,7 @@ L4;1 RS;1 Inst -vs_pos_delay_cnt[5]/opit_0_L5Q_perm;gopL5Q +vs_pos_delay_cnt[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -285981,7 +286006,7 @@ L4;1 RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/N87.lt_2/gateop_perm;gopA +u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/N158.eq_4/gateop_perm;gopA Pin Cout;2 Y;2 @@ -285994,7 +286019,7 @@ I3;1 I4;1 Inst -vs_pos_delay_cnt[0]/opit_0_L5Q_perm;gopL5Q +vs_down_delay_cnt[11]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -286010,7 +286035,7 @@ L4;1 RS;1 Inst -wr0_vs/opit_0_L5Q_perm;gopL5Q +vs_pos_delay_cnt[9]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -286065,7 +286090,7 @@ IN;1 MI;1 Inst -vs_pos_delay_cnt[9]/opit_0_L5Q_perm;gopL5Q +vs_pos_delay_cnt[8]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -286097,7 +286122,7 @@ L4;1 RS;1 Inst -vs_pos_delay_cnt[3]/opit_0_L5Q_perm;gopL5Q +vs_pos_delay_cnt[5]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -286129,14 +286154,20 @@ L4;1 RS;1 Inst -N104_mux11_9/gateop_perm;gopLUT5 +vs_down_delay_cnt[8]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst vs_pos_delay_cnt[7]/opit_0_L5Q_perm;gopL5Q @@ -286155,7 +286186,7 @@ L4;1 RS;1 Inst -vs_down_delay_cnt[8]/opit_0_L5Q_perm;gopL5Q +u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[0]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -286171,7 +286202,7 @@ L4;1 RS;1 Inst -vs_pos_delay_cnt[10]/opit_0_L5Q_perm;gopL5Q +u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[1]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -286187,17 +286218,23 @@ L4;1 RS;1 Inst -N104_mux11_12/gateop_perm;gopLUT5 +vs_pos_delay_cnt[10]/opit_0_L5Q_perm;gopL5Q Pin +CEOUT;2 +Q;2 +RSOUT;2 Z;2 +CE;1 +CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 +RS;1 Inst -vs_pos_delay_cnt[11]/opit_0_L5Q_perm;gopL5Q +u_hdm_in_rst/rst/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -286213,7 +286250,7 @@ L4;1 RS;1 Inst -vs_pos_delay_cnt[8]/opit_0_L5Q_perm;gopL5Q +vs_pos_delay_cnt[11]/opit_0_L5Q_perm;gopL5Q Pin CEOUT;2 Q;2 @@ -286229,33 +286266,24 @@ L4;1 RS;1 Inst -u_hdmi_in_top/hdmi_in_en/opit_0_L5Q_perm;gopL5Q +N119_mux11_12/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst -image_filiter_inst/hybrid_filter_inst/median_finder9_g/N155.lt_2/gateop_perm;gopA +u_ov5640/u_mix_image/N311_8/gateop_perm;gopLUT5 Pin -Cout;2 -Y;2 -Cin;1 -I0;1 -I0X;1 -I1;1 -I2;1 -I3;1 -I4;1 +Z;2 +L0;1 +L1;1 +L2;1 +L3;1 +L4;1 Inst zoom_ff0[0]/opit_0;gopQ @@ -286588,20 +286616,14 @@ D;1 RS;1 Inst -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm;gopL5Q +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[10]/gateop_perm;gopLUT5 Pin -CEOUT;2 -Q;2 -RSOUT;2 Z;2 -CE;1 -CLK;1 L0;1 L1;1 L2;1 L3;1 L4;1 -RS;1 Inst zoom_vs_out0/opit_0;gopQ @@ -289210,6 +289232,16 @@ VCC_516;gopVCC Pin Z;2 +Inst +VCC_517;gopVCC +Pin +Z;2 + +Inst +VCC_518;gopVCC +Pin +Z;2 + Inst GND_0;gopGND Pin @@ -295360,6 +295392,36 @@ GND_1229;gopGND Pin Z;2 +Inst +GND_1230;gopGND +Pin +Z;2 + +Inst +GND_1231;gopGND +Pin +Z;2 + +Inst +GND_1232;gopGND +Pin +Z;2 + +Inst +GND_1233;gopGND +Pin +Z;2 + +Inst +GND_1234;gopGND +Pin +Z;2 + +Inst +GND_1235;gopGND +Pin +Z;2 + Inst CLKROUTE_0;gopCLKROUTE Pin @@ -295402,6 +295464,34 @@ Z;2 L7in;1 M;1 +Inst +CLKROUTE_6;gopCLKROUTE +Pin +Z;2 +L7in;1 +M;1 + +Inst +CLKROUTE_7;gopCLKROUTE +Pin +Z;2 +L7in;1 +M;1 + +Inst +CLKROUTE_8;gopCLKROUTE +Pin +Z;2 +L7in;1 +M;1 + +Inst +CLKROUTE_9;gopCLKROUTE +Pin +Z;2 +L7in;1 +M;1 + Inst USCMROUTE_0;gopCLKBUFG Pin @@ -295425,7 +295515,7 @@ N24; N104; N119; N139_0; -N298; +N299; U_HDMI_PLL/u_pll_e3/ntCLKFB; _N0; _N1; @@ -295506,14 +295596,14 @@ _N75; _N76; _N77; _N78; -_N79; -_N84; +_N83; +_N87; _N88; _N89; _N90; _N91; _N92; -_N93; +_N94; _N95; _N96; _N97; @@ -295522,24 +295612,18 @@ _N99; _N100; _N101; _N102; -_N103; +_N104; _N105; -_N2195; -_N2203; -_N2209; -_N2277; -_N17116; -_N17118; -_N17120; -_N17122; -_N17124; -_N17126; +_N2197; +_N2205; +_N2211; +_N2279; +_N17128; _N17130; _N17132; _N17134; _N17136; _N17138; -_N17140; _N17142; _N17144; _N17146; @@ -295548,288 +295632,292 @@ _N17150; _N17152; _N17154; _N17156; -_N18115; -_N81412_3; -_N81412_5; -_N81413_3; -_N81413_5; -_N81414_3; -_N81414_5; -_N81415_3; -_N81415_5; -_N97085; -_N97297; -_N97340; -_N103547; -_N103551; -_N103709; -_N103711; -_N103720; -_N103722; -_N103731; -_N103733; -_N103742; -_N103743; -_N103744; -_N103920; -_N103957; -_N103958; -_N103959; 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adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/_N13437; adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/_N13439; -adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/_N13444; +adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/_N13441; adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/_N13446; adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/_N13448; adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/_N13450; -adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/_N107220; +adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/_N13452; +adjust_color_wrapper_inst/adjust_color_inst/hsv_modify_inst/_N108042; axi_rst; b_in_ibuf[3]/ntD; b_in_ibuf[4]/ntD; @@ -295892,6 +295980,7 @@ cmos2_scl_iobuf/ntO; cmos2_scl_iobuf/ntT; cmos2_vsync; cmos2_vsync_ibuf/ntD; +ddr_clk; ddr_rst; de_in; de_in_ibuf/ntD; @@ -295944,85 +296033,85 @@ image_filiter_inst/hybrid_filter_inst/N114; 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+image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/_N20942; +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/_N25569; +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/_N25573; +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/_N96605; image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/N17; -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/_N20794; -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/_N25634; -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/_N25638; -image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/_N95820; +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/_N25589; +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/_N25609; +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/_N25613; +image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/_N96597; image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N35; image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N37; image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N39; @@ -296342,35 +296431,35 @@ image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N111; image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N155; image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N161; image_filiter_inst2/hybrid_filter_inst/median_finder9_r/N167; -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/_N102782_1; -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/_N102783_1; +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/_N103574_1; +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/_N103576_1; image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N4; image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N5; image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N8; image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N15; image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/N17; -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/_N17944; -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/_N25797; -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/_N25819; -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/_N95911; +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/_N25752; +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/_N26026; +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/_N26030; +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/_N96725; image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N4; image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N5; image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N8; image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N15; image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/N17; -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/_N22385; -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/_N22389; -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/_N26062; -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/_N95967; +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/_N17953; +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/_N17961; +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/_N25211; +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/_N96760; image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N4; image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N5; image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N8; image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N15; image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/N17; -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/_N20433; -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/_N20437; -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/_N25357; -image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/_N95892; +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/_N20027; +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/_N20031; +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/_N25461; +image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/_N96724; image_filiter_inst2/matrix_valid; image_filiter_inst2/multiline_buffer_inst/N21; image_filiter_inst2/multiline_buffer_inst/N48; @@ -296383,50 +296472,50 @@ image_filiter_inst2/multiline_buffer_inst/N216_inv; image_filiter_inst2/multiline_buffer_inst/N229; image_filiter_inst2/multiline_buffer_inst/N271; image_filiter_inst2/multiline_buffer_inst/N272; -image_filiter_inst2/multiline_buffer_inst/_N13617; -image_filiter_inst2/multiline_buffer_inst/_N13619; -image_filiter_inst2/multiline_buffer_inst/_N13621; -image_filiter_inst2/multiline_buffer_inst/_N13623; -image_filiter_inst2/multiline_buffer_inst/_N13635; -image_filiter_inst2/multiline_buffer_inst/_N13637; -image_filiter_inst2/multiline_buffer_inst/_N13639; -image_filiter_inst2/multiline_buffer_inst/_N13641; -image_filiter_inst2/multiline_buffer_inst/_N15738; -image_filiter_inst2/multiline_buffer_inst/_N15740; -image_filiter_inst2/multiline_buffer_inst/_N15742; -image_filiter_inst2/multiline_buffer_inst/_N15960; -image_filiter_inst2/multiline_buffer_inst/_N15962; -image_filiter_inst2/multiline_buffer_inst/_N84159; -image_filiter_inst2/multiline_buffer_inst/_N97104; -image_filiter_inst2/multiline_buffer_inst/_N98270; -image_filiter_inst2/multiline_buffer_inst/_N103753; -image_filiter_inst2/multiline_buffer_inst/_N103754; -image_filiter_inst2/multiline_buffer_inst/_N103759; -image_filiter_inst2/multiline_buffer_inst/_N103916; +image_filiter_inst2/multiline_buffer_inst/_N13614; +image_filiter_inst2/multiline_buffer_inst/_N13616; +image_filiter_inst2/multiline_buffer_inst/_N13618; +image_filiter_inst2/multiline_buffer_inst/_N13620; +image_filiter_inst2/multiline_buffer_inst/_N13625; +image_filiter_inst2/multiline_buffer_inst/_N13627; +image_filiter_inst2/multiline_buffer_inst/_N13629; +image_filiter_inst2/multiline_buffer_inst/_N13631; +image_filiter_inst2/multiline_buffer_inst/_N15983; +image_filiter_inst2/multiline_buffer_inst/_N15985; +image_filiter_inst2/multiline_buffer_inst/_N15987; +image_filiter_inst2/multiline_buffer_inst/_N15992; +image_filiter_inst2/multiline_buffer_inst/_N15994; +image_filiter_inst2/multiline_buffer_inst/_N84996; +image_filiter_inst2/multiline_buffer_inst/_N97883; +image_filiter_inst2/multiline_buffer_inst/_N101318; +image_filiter_inst2/multiline_buffer_inst/_N104576; +image_filiter_inst2/multiline_buffer_inst/_N104577; +image_filiter_inst2/multiline_buffer_inst/_N104582; +image_filiter_inst2/multiline_buffer_inst/_N104740; image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N21; -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13396; image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13398; image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13400; image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13402; image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13404; -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13409; +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13406; image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13411; image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13413; image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13415; image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13417; +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13419; image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/rempty; image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/wfull; image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N21; -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N16358; -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N16360; -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N16362; -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N16364; -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N16366; -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N16371; -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N16373; -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N16375; -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N16377; -image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N16379; +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N16529; +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N16531; +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N16533; +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N16535; +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N16537; +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N16542; +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N16544; +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N16546; +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N16548; +image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N16550; image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/rempty; image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/wfull; image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[10:0]_or; @@ -296484,8 +296573,9 @@ ms72xx_ctl.iic_sda_tri/ntT; ms72xx_ctl.iic_tx_sda_tri/ntI; ms72xx_ctl.iic_tx_sda_tri/ntO; ms72xx_ctl.iic_tx_sda_tri/ntT; -ms72xx_ctl/_N95852; -ms72xx_ctl/_N96143; +ms72xx_ctl/_N96626; +ms72xx_ctl/_N96633; +ms72xx_ctl/_N96740; ms72xx_ctl/busy_rx; ms72xx_ctl/busy_tx; ms72xx_ctl/byte_over_rx; @@ -296502,26 +296592,26 @@ ms72xx_ctl/iic_dri_rx/_N9; ms72xx_ctl/iic_dri_rx/_N17985; ms72xx_ctl/iic_dri_rx/_N17986; ms72xx_ctl/iic_dri_rx/_N17987; -ms72xx_ctl/iic_dri_rx/_N19828; -ms72xx_ctl/iic_dri_rx/_N19831; -ms72xx_ctl/iic_dri_rx/_N29346; -ms72xx_ctl/iic_dri_rx/_N29348; +ms72xx_ctl/iic_dri_rx/_N19775; +ms72xx_ctl/iic_dri_rx/_N19778; +ms72xx_ctl/iic_dri_rx/_N29321; +ms72xx_ctl/iic_dri_rx/_N29323; ms72xx_ctl/iic_dri_rx/_N30788; ms72xx_ctl/iic_dri_rx/_N30794; ms72xx_ctl/iic_dri_rx/_N30799; ms72xx_ctl/iic_dri_rx/_N30805; ms72xx_ctl/iic_dri_rx/_N30810; -ms72xx_ctl/iic_dri_rx/_N81582; -ms72xx_ctl/iic_dri_rx/_N81586; -ms72xx_ctl/iic_dri_rx/_N81608; -ms72xx_ctl/iic_dri_rx/_N95846; -ms72xx_ctl/iic_dri_rx/_N96754; -ms72xx_ctl/iic_dri_rx/_N102144_2; -ms72xx_ctl/iic_dri_rx/_N103288; -ms72xx_ctl/iic_dri_rx/_N103986; -ms72xx_ctl/iic_dri_rx/_N104016; -ms72xx_ctl/iic_dri_rx/_N104046; -ms72xx_ctl/iic_dri_rx/_N104065; +ms72xx_ctl/iic_dri_rx/_N82353; +ms72xx_ctl/iic_dri_rx/_N82357; +ms72xx_ctl/iic_dri_rx/_N82374; +ms72xx_ctl/iic_dri_rx/_N96619; +ms72xx_ctl/iic_dri_rx/_N97518; +ms72xx_ctl/iic_dri_rx/_N102965_2; +ms72xx_ctl/iic_dri_rx/_N104100; +ms72xx_ctl/iic_dri_rx/_N104811; +ms72xx_ctl/iic_dri_rx/_N104841; +ms72xx_ctl/iic_dri_rx/_N104871; +ms72xx_ctl/iic_dri_rx/_N104890; ms72xx_ctl/iic_dri_rx/dsu; ms72xx_ctl/iic_dri_rx/full_cycle; ms72xx_ctl/iic_dri_rx/half_cycle; @@ -296548,19 +296638,18 @@ ms72xx_ctl/iic_dri_tx/_N17994; ms72xx_ctl/iic_dri_tx/_N17995; ms72xx_ctl/iic_dri_tx/_N17996; ms72xx_ctl/iic_dri_tx/_N30831; -ms72xx_ctl/iic_dri_tx/_N81617; -ms72xx_ctl/iic_dri_tx/_N81621; -ms72xx_ctl/iic_dri_tx/_N81641; -ms72xx_ctl/iic_dri_tx/_N95847; -ms72xx_ctl/iic_dri_tx/_N96238; -ms72xx_ctl/iic_dri_tx/_N103294; -ms72xx_ctl/iic_dri_tx/_N104381; -ms72xx_ctl/iic_dri_tx/_N104416; -ms72xx_ctl/iic_dri_tx/_N104421; -ms72xx_ctl/iic_dri_tx/_N104427; -ms72xx_ctl/iic_dri_tx/_N104432; -ms72xx_ctl/iic_dri_tx/_N104434; -ms72xx_ctl/iic_dri_tx/_N104463; +ms72xx_ctl/iic_dri_tx/_N82383; +ms72xx_ctl/iic_dri_tx/_N82387; +ms72xx_ctl/iic_dri_tx/_N82418; +ms72xx_ctl/iic_dri_tx/_N96620; +ms72xx_ctl/iic_dri_tx/_N104106; +ms72xx_ctl/iic_dri_tx/_N105220; +ms72xx_ctl/iic_dri_tx/_N105255; +ms72xx_ctl/iic_dri_tx/_N105260; +ms72xx_ctl/iic_dri_tx/_N105266; +ms72xx_ctl/iic_dri_tx/_N105271; +ms72xx_ctl/iic_dri_tx/_N105273; +ms72xx_ctl/iic_dri_tx/_N105300; ms72xx_ctl/iic_dri_tx/pluse_1d; ms72xx_ctl/iic_dri_tx/pluse_2d; ms72xx_ctl/iic_dri_tx/pluse_3d; @@ -296575,6 +296664,7 @@ ms72xx_ctl/iic_trig_tx; ms72xx_ctl/ms7200_ctl/N8; ms72xx_ctl/ms7200_ctl/N261; ms72xx_ctl/ms7200_ctl/N1321; +ms72xx_ctl/ms7200_ctl/N1359; ms72xx_ctl/ms7200_ctl/N1366; ms72xx_ctl/ms7200_ctl/N1386; ms72xx_ctl/ms7200_ctl/N1388; @@ -296582,6 +296672,7 @@ ms72xx_ctl/ms7200_ctl/N1415; ms72xx_ctl/ms7200_ctl/N1797; ms72xx_ctl/ms7200_ctl/N1845; ms72xx_ctl/ms7200_ctl/N1872; +ms72xx_ctl/ms7200_ctl/N1873; ms72xx_ctl/ms7200_ctl/N1879; ms72xx_ctl/ms7200_ctl/N1895; ms72xx_ctl/ms7200_ctl/N1918; @@ -296592,33 +296683,31 @@ ms72xx_ctl/ms7200_ctl/N2070; ms72xx_ctl/ms7200_ctl/N2076; ms72xx_ctl/ms7200_ctl/N2083; ms72xx_ctl/ms7200_ctl/N2085; -ms72xx_ctl/ms7200_ctl/_N13805; -ms72xx_ctl/ms7200_ctl/_N13807; -ms72xx_ctl/ms7200_ctl/_N13809; +ms72xx_ctl/ms7200_ctl/_N13823; +ms72xx_ctl/ms7200_ctl/_N13825; +ms72xx_ctl/ms7200_ctl/_N13827; ms72xx_ctl/ms7200_ctl/_N17171; ms72xx_ctl/ms7200_ctl/_N17173; ms72xx_ctl/ms7200_ctl/_N17175; ms72xx_ctl/ms7200_ctl/_N17177; -ms72xx_ctl/ms7200_ctl/_N18000; -ms72xx_ctl/ms7200_ctl/_N18002; -ms72xx_ctl/ms7200_ctl/_N84747; -ms72xx_ctl/ms7200_ctl/_N95810; -ms72xx_ctl/ms7200_ctl/_N95853; -ms72xx_ctl/ms7200_ctl/_N95857; -ms72xx_ctl/ms7200_ctl/_N95866; -ms72xx_ctl/ms7200_ctl/_N96041; -ms72xx_ctl/ms7200_ctl/_N96431; -ms72xx_ctl/ms7200_ctl/_N96695; -ms72xx_ctl/ms7200_ctl/_N100381; -ms72xx_ctl/ms7200_ctl/_N103976; -ms72xx_ctl/ms7200_ctl/_N103981; -ms72xx_ctl/ms7200_ctl/_N104002; -ms72xx_ctl/ms7200_ctl/_N104013; -ms72xx_ctl/ms7200_ctl/_N104061; -ms72xx_ctl/ms7200_ctl/_N104063; -ms72xx_ctl/ms7200_ctl/_N104071; -ms72xx_ctl/ms7200_ctl/_N104076; -ms72xx_ctl/ms7200_ctl/_N104081; +ms72xx_ctl/ms7200_ctl/_N96603; +ms72xx_ctl/ms7200_ctl/_N96627; +ms72xx_ctl/ms7200_ctl/_N96632; +ms72xx_ctl/ms7200_ctl/_N96696; +ms72xx_ctl/ms7200_ctl/_N96761; +ms72xx_ctl/ms7200_ctl/_N97453; +ms72xx_ctl/ms7200_ctl/_N104787; +ms72xx_ctl/ms7200_ctl/_N104790; +ms72xx_ctl/ms7200_ctl/_N104793; +ms72xx_ctl/ms7200_ctl/_N104806; +ms72xx_ctl/ms7200_ctl/_N104827; +ms72xx_ctl/ms7200_ctl/_N104838; +ms72xx_ctl/ms7200_ctl/_N104861; +ms72xx_ctl/ms7200_ctl/_N104886; +ms72xx_ctl/ms7200_ctl/_N104888; +ms72xx_ctl/ms7200_ctl/_N104896; +ms72xx_ctl/ms7200_ctl/_N104901; +ms72xx_ctl/ms7200_ctl/_N104906; ms72xx_ctl/ms7200_ctl/busy_1d; ms72xx_ctl/ms7200_ctl/busy_falling; ms72xx_ctl/ms7200_ctl/freq_ensure; @@ -296634,8 +296723,9 @@ ms72xx_ctl/ms7210_ctl/N580; ms72xx_ctl/ms7210_ctl/N586; ms72xx_ctl/ms7210_ctl/N589; ms72xx_ctl/ms7210_ctl/N591; -ms72xx_ctl/ms7210_ctl/_N13830; -ms72xx_ctl/ms7210_ctl/_N13832; +ms72xx_ctl/ms7210_ctl/_N2723; +ms72xx_ctl/ms7210_ctl/_N14011; +ms72xx_ctl/ms7210_ctl/_N14013; ms72xx_ctl/ms7210_ctl/_N17181; ms72xx_ctl/ms7210_ctl/_N17183; ms72xx_ctl/ms7210_ctl/_N17185; @@ -296646,15 +296736,15 @@ ms72xx_ctl/ms7210_ctl/_N17193; ms72xx_ctl/ms7210_ctl/_N17195; ms72xx_ctl/ms7210_ctl/_N17197; ms72xx_ctl/ms7210_ctl/_N17199; -ms72xx_ctl/ms7210_ctl/_N95867; -ms72xx_ctl/ms7210_ctl/_N104392; -ms72xx_ctl/ms7210_ctl/_N104397; -ms72xx_ctl/ms7210_ctl/_N104401; -ms72xx_ctl/ms7210_ctl/_N104405; -ms72xx_ctl/ms7210_ctl/_N104406; -ms72xx_ctl/ms7210_ctl/_N104446; -ms72xx_ctl/ms7210_ctl/_N104448; -ms72xx_ctl/ms7210_ctl/_N104459; +ms72xx_ctl/ms7210_ctl/_N96642; +ms72xx_ctl/ms7210_ctl/_N105231; +ms72xx_ctl/ms7210_ctl/_N105236; +ms72xx_ctl/ms7210_ctl/_N105240; +ms72xx_ctl/ms7210_ctl/_N105244; +ms72xx_ctl/ms7210_ctl/_N105245; +ms72xx_ctl/ms7210_ctl/_N105283; +ms72xx_ctl/ms7210_ctl/_N105285; +ms72xx_ctl/ms7210_ctl/_N105296; ms72xx_ctl/ms7210_ctl/busy_1d; ms72xx_ctl/ms7210_ctl/busy_falling; ms72xx_ctl/rstn; @@ -296791,6 +296881,7 @@ ntclkbufg_4; ntclkbufg_5; ntclkbufg_6; ntclkbufg_7; +ntclkbufg_8; ntclkgate_0; param_manager_inst/N30; param_manager_inst/N33; @@ -296798,25 +296889,28 @@ param_manager_inst/N314; param_manager_inst/N335; param_manager_inst/N344; param_manager_inst/N345; -param_manager_inst/_N2742; -param_manager_inst/_N2756; -param_manager_inst/_N3647; -param_manager_inst/_N3793; -param_manager_inst/_N13814; -param_manager_inst/_N13816; -param_manager_inst/_N13818; -param_manager_inst/_N13820; -param_manager_inst/_N13822; -param_manager_inst/_N13824; -param_manager_inst/_N13826; -param_manager_inst/_N96763; -param_manager_inst/_N104340; -param_manager_inst/_N104342; -param_manager_inst/_N104344; -param_manager_inst/_N104351; -param_manager_inst/_N104501; -param_manager_inst/_N107262; -param_manager_inst/_N107263; +param_manager_inst/_N2738; +param_manager_inst/_N2752; +param_manager_inst/_N3230; +param_manager_inst/_N3669; +param_manager_inst/_N3811; +param_manager_inst/_N13832; +param_manager_inst/_N13834; +param_manager_inst/_N13836; +param_manager_inst/_N13838; +param_manager_inst/_N13840; +param_manager_inst/_N13842; +param_manager_inst/_N13844; +param_manager_inst/_N97529; +param_manager_inst/_N105179; +param_manager_inst/_N105181; +param_manager_inst/_N105183; +param_manager_inst/_N105190; +param_manager_inst/_N105338; +param_manager_inst/_N108087; +param_manager_inst/_N108088; +param_manager_inst/_N108109; +param_manager_inst/_N108110; param_manager_inst/changed_left; param_manager_inst/changed_right; param_manager_inst/clk_ms; @@ -296830,9 +296924,9 @@ param_manager_inst/key_debounce_key_left/N20; param_manager_inst/key_debounce_key_left/N47; param_manager_inst/key_debounce_key_left/N87; param_manager_inst/key_debounce_key_left/N88; -param_manager_inst/key_debounce_key_left/_N2843; +param_manager_inst/key_debounce_key_left/_N2839; param_manager_inst/key_debounce_key_left/_N26996; -param_manager_inst/key_debounce_key_left/_N104367; +param_manager_inst/key_debounce_key_left/_N105206; param_manager_inst/key_debounce_key_left/clk_ms_ff0; param_manager_inst/key_debounce_key_left/clk_ms_ff1; param_manager_inst/key_debounce_key_left/key_ff0; @@ -296842,18 +296936,18 @@ param_manager_inst/key_debounce_key_restore/N20; param_manager_inst/key_debounce_key_restore/N47; param_manager_inst/key_debounce_key_restore/N87; param_manager_inst/key_debounce_key_restore/N88; -param_manager_inst/key_debounce_key_restore/_N2892; +param_manager_inst/key_debounce_key_restore/_N2888; param_manager_inst/key_debounce_key_restore/_N27008; -param_manager_inst/key_debounce_key_restore/_N104374; +param_manager_inst/key_debounce_key_restore/_N105213; param_manager_inst/key_debounce_key_restore/key_ff0; param_manager_inst/key_debounce_key_restore/key_ff1; param_manager_inst/key_debounce_key_right/N20; param_manager_inst/key_debounce_key_right/N47; param_manager_inst/key_debounce_key_right/N87; param_manager_inst/key_debounce_key_right/N88; -param_manager_inst/key_debounce_key_right/_N2941; +param_manager_inst/key_debounce_key_right/_N2937; param_manager_inst/key_debounce_key_right/_N27020; -param_manager_inst/key_debounce_key_right/_N104359; +param_manager_inst/key_debounce_key_right/_N105198; param_manager_inst/key_debounce_key_right/key_ff0; param_manager_inst/key_debounce_key_right/key_ff1; param_manager_inst/modify_H_flags_ff0; @@ -296901,6 +296995,7 @@ param_manager_inst/osd_startY_flags_ff1; param_manager_inst/osd_startY_flags_ff2; param_manager_inst/osd_startY_flags_ff3; param_manager_inst/osd_startY_load; +param_manager_inst/param_filiter1_mode/N59; param_manager_inst/param_filiter1_mode/N102; param_manager_inst/param_filiter1_mode/N111; param_manager_inst/param_filiter1_mode/N116; @@ -296911,27 +297006,28 @@ param_manager_inst/param_filiter1_mode/N149; param_manager_inst/param_filiter1_mode/N152; param_manager_inst/param_filiter1_mode/N153; param_manager_inst/param_filiter1_mode/N161; -param_manager_inst/param_filiter1_mode/_N81667; -param_manager_inst/param_filiter1_mode/_N105304; -param_manager_inst/param_filiter1_mode/_N105307; +param_manager_inst/param_filiter1_mode/_N37753; +param_manager_inst/param_filiter1_mode/_N82454; +param_manager_inst/param_filiter1_mode/_N106117; +param_manager_inst/param_filiter1_mode/_N106120; param_manager_inst/param_filiter1_mode/changed_down; param_manager_inst/param_filiter1_mode/changed_up; param_manager_inst/param_filiter1_mode/key_debounce_inst1/N20; param_manager_inst/param_filiter1_mode/key_debounce_inst1/N47; param_manager_inst/param_filiter1_mode/key_debounce_inst1/N87; param_manager_inst/param_filiter1_mode/key_debounce_inst1/N88; -param_manager_inst/param_filiter1_mode/key_debounce_inst1/_N3006; +param_manager_inst/param_filiter1_mode/key_debounce_inst1/_N3002; param_manager_inst/param_filiter1_mode/key_debounce_inst1/_N27038; -param_manager_inst/param_filiter1_mode/key_debounce_inst1/_N104474; +param_manager_inst/param_filiter1_mode/key_debounce_inst1/_N105311; param_manager_inst/param_filiter1_mode/key_debounce_inst1/key_ff0; param_manager_inst/param_filiter1_mode/key_debounce_inst1/key_ff1; param_manager_inst/param_filiter1_mode/key_debounce_inst2/N20; param_manager_inst/param_filiter1_mode/key_debounce_inst2/N47; param_manager_inst/param_filiter1_mode/key_debounce_inst2/N87; param_manager_inst/param_filiter1_mode/key_debounce_inst2/N88; -param_manager_inst/param_filiter1_mode/key_debounce_inst2/_N3055; +param_manager_inst/param_filiter1_mode/key_debounce_inst2/_N3051; param_manager_inst/param_filiter1_mode/key_debounce_inst2/_N27050; -param_manager_inst/param_filiter1_mode/key_debounce_inst2/_N104491; +param_manager_inst/param_filiter1_mode/key_debounce_inst2/_N105328; param_manager_inst/param_filiter1_mode/key_debounce_inst2/key_ff0; param_manager_inst/param_filiter1_mode/key_debounce_inst2/key_ff1; param_manager_inst/param_filiter1_mode/pluse; @@ -296941,9 +297037,8 @@ param_manager_inst/param_filiter2_mode/N140; param_manager_inst/param_filiter2_mode/N149; param_manager_inst/param_filiter2_mode/N152; param_manager_inst/param_filiter2_mode/N153; -param_manager_inst/param_filiter2_mode/_N81678; +param_manager_inst/param_filiter2_mode/_N82459; param_manager_inst/param_modify_H/N72; -param_manager_inst/param_modify_H/N76; param_manager_inst/param_modify_H/N120; param_manager_inst/param_modify_H/N122; param_manager_inst/param_modify_H/N140; @@ -296952,46 +297047,45 @@ param_manager_inst/param_modify_H/N150; param_manager_inst/param_modify_H/N153; param_manager_inst/param_modify_H/N154; param_manager_inst/param_modify_H/_N3248; -param_manager_inst/param_modify_H/_N13934; -param_manager_inst/param_modify_H/_N13936; -param_manager_inst/param_modify_H/_N13938; +param_manager_inst/param_modify_H/_N13885; +param_manager_inst/param_modify_H/_N13887; +param_manager_inst/param_modify_H/_N13889; param_manager_inst/param_modify_H/_N27073_inv; -param_manager_inst/param_modify_H/_N29675; -param_manager_inst/param_modify_H/_N29678; -param_manager_inst/param_modify_H/_N29681; -param_manager_inst/param_modify_H/_N29684; -param_manager_inst/param_modify_H/_N104546; -param_manager_inst/param_modify_H/_N104547; -param_manager_inst/param_modify_H/_N104548; -param_manager_inst/param_modify_H/_N107227; -param_manager_inst/param_modify_H/_N107229; -param_manager_inst/param_modify_H/_N107234; -param_manager_inst/param_modify_H/_N107236; +param_manager_inst/param_modify_H/_N29625; +param_manager_inst/param_modify_H/_N29628; +param_manager_inst/param_modify_H/_N29631; +param_manager_inst/param_modify_H/_N29634; +param_manager_inst/param_modify_H/_N105381; +param_manager_inst/param_modify_H/_N105382; +param_manager_inst/param_modify_H/_N105383; +param_manager_inst/param_modify_H/_N108049; +param_manager_inst/param_modify_H/_N108056; +param_manager_inst/param_modify_H/_N108060; param_manager_inst/param_modify_H/pluse; param_manager_inst/param_modify_S/N76; param_manager_inst/param_modify_S/N140; +param_manager_inst/param_modify_S/N142; param_manager_inst/param_modify_S/N149; param_manager_inst/param_modify_S/N150; param_manager_inst/param_modify_S/N153; param_manager_inst/param_modify_S/N154; -param_manager_inst/param_modify_S/_N13943; -param_manager_inst/param_modify_S/_N13945; -param_manager_inst/param_modify_S/_N13947; +param_manager_inst/param_modify_S/_N13894; +param_manager_inst/param_modify_S/_N13896; +param_manager_inst/param_modify_S/_N13898; param_manager_inst/param_modify_S/_N27116_inv; -param_manager_inst/param_modify_S/_N107281; -param_manager_inst/param_modify_S/_N107282; -param_manager_inst/param_modify_S/_N107290; +param_manager_inst/param_modify_S/_N108118; param_manager_inst/param_modify_V/N76; param_manager_inst/param_modify_V/N140; +param_manager_inst/param_modify_V/N142; param_manager_inst/param_modify_V/N149; param_manager_inst/param_modify_V/N150; param_manager_inst/param_modify_V/N153; param_manager_inst/param_modify_V/N154; -param_manager_inst/param_modify_V/_N14021; -param_manager_inst/param_modify_V/_N14023; -param_manager_inst/param_modify_V/_N14025; +param_manager_inst/param_modify_V/_N13963; +param_manager_inst/param_modify_V/_N13965; +param_manager_inst/param_modify_V/_N13967; param_manager_inst/param_modify_V/_N27159_inv; -param_manager_inst/param_modify_V/_N107271; +param_manager_inst/param_modify_V/_N108096; param_manager_inst/param_offsetX/N72; param_manager_inst/param_offsetX/N76; param_manager_inst/param_offsetX/N102; @@ -297001,16 +297095,16 @@ param_manager_inst/param_offsetX/N149; param_manager_inst/param_offsetX/N150; param_manager_inst/param_offsetX/N153; param_manager_inst/param_offsetX/N154; -param_manager_inst/param_offsetX/_N15152; -param_manager_inst/param_offsetX/_N15154; -param_manager_inst/param_offsetX/_N15156; -param_manager_inst/param_offsetX/_N15158; -param_manager_inst/param_offsetX/_N15160; +param_manager_inst/param_offsetX/_N15357; +param_manager_inst/param_offsetX/_N15359; +param_manager_inst/param_offsetX/_N15361; +param_manager_inst/param_offsetX/_N15363; +param_manager_inst/param_offsetX/_N15365; param_manager_inst/param_offsetX/_N27202_inv; -param_manager_inst/param_offsetX/_N29719; -param_manager_inst/param_offsetX/_N104483; -param_manager_inst/param_offsetX/_N104485; -param_manager_inst/param_offsetX/_N104496; +param_manager_inst/param_offsetX/_N29694; +param_manager_inst/param_offsetX/_N105320; +param_manager_inst/param_offsetX/_N105322; +param_manager_inst/param_offsetX/_N105333; param_manager_inst/param_offsetX/pluse; param_manager_inst/param_offsetY/N76; param_manager_inst/param_offsetY/N140; @@ -297018,15 +297112,15 @@ param_manager_inst/param_offsetY/N149; param_manager_inst/param_offsetY/N150; param_manager_inst/param_offsetY/N153; param_manager_inst/param_offsetY/N154; -param_manager_inst/param_offsetY/_N3781; -param_manager_inst/param_offsetY/_N3785; -param_manager_inst/param_offsetY/_N15248; -param_manager_inst/param_offsetY/_N15250; -param_manager_inst/param_offsetY/_N15252; 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+param_manager_inst/param_zoom/_N105526; +param_manager_inst/param_zoom/_N105527; param_manager_inst/pressed_left; param_manager_inst/pressed_restore; param_manager_inst/pressed_right; @@ -297234,51 +297330,51 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/calib_odt; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/calib_ras_n; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/calib_rst; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/calib_we_n; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/_N97037; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/_N105439; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/_N97806; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/_N106213; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N9; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N169; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/N233; 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-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N19659; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N19660; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N19661; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N19662; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N19663; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N19664; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N19665; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N19666; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N19667; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N19600; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N19601; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N19602; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N19603; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N19604; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N19605; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N19606; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N19607; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N19608; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N19609; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N19610; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N19611; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N19612; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N19613; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N19614; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N27699; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N27704; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N27705; @@ -297288,19 +297384,19 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N27713; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N27715; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N27717; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N27719; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N81834; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N97036; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N103565; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N103569; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N103573; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N103576; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N103595; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N103599; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N103603; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N103606; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N103614; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N103626; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N103627; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N82622; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N97805; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N104377; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N104381; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N104385; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N104388; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N104407; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N104411; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N104415; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N104418; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N104426; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N104438; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/_N104439; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cke_pass; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_pwron_pass; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tmod_pass; @@ -297308,19 +297404,19 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tmrd u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_txpr_pass; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit_pass; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/mr_load_done; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/_N96030; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/_N96815; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_rst_rreq; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/N124; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/N140; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/N176; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/_N21; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/_N16316; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/_N16318; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/_N16320; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/_N96032; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/_N103632; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/_N106835; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/_N106841; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/_N17010; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/_N17012; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/_N17014; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/_N96819; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/_N104444; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/_N107664; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/_N107670; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cnt_tmod_pass; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cnt_twldqsen_pass; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_dqs_resp_r; @@ -297344,45 +297440,45 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/N813; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N265; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N294; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N303; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N14284; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N14286; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N14288; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N14290; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N14292; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N14294; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N14296; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N14298; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N14300; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N14302; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N14304; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N14306; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N14308; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N14310; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N14312; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N18095_inv; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N22258; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N29921; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N95983; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N95994; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N96039; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N96040; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N96049; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N96053; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N96797; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N97033; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N97144; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N97145; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N105426; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N105430; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N106546; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N106549; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N106550; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N106551; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N106574; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N106577; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N106578; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N106581; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N106583; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N106584; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N106586; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N106588; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N106592; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N106598; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N106607; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N108364; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N22198; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N29896; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N96759; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N96828; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N96830; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N96833; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N96838; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N96842; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N97576; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N97803; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N97917; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N97918; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N106361; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N106365; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N107364; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N107367; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N107368; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N107369; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N107392; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N107395; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N107396; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N107399; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N107401; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N107402; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N107404; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N107406; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N107410; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N107416; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N107425; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/_N109250; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt_trfc_pass; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_success; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/ref_cnt_done; @@ -297410,47 +297506,53 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N307; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N382; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N457; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N532; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14574; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14576; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14579; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14581; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14532; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14534; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14537; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14539; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N28526; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N55657; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N56412; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N57216; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N58869; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N59500; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N82045; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N96265; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N97065; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N97066; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N105455; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N137_rnmt; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N53495; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N55147; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N56942; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N58045; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N58048; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N82844; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N82848; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N82855; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N82859; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N97038; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N97836; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N97837; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N106264; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N219; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N240; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N0; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N14543; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N14545; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N14547; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N97086; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N106342; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N106347; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N106349; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N106378; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N14524; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N14526; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N14528; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N84886; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N97845; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N97846; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N107160; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N107164; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N107167; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N107173; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/_N107196; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_dll_rst_rg; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N14586; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N14588; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N14590; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N14592; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N14594; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N14596; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N14598; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N14600; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N106328; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N106332; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N106336; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N106339; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N14544; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N14546; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N14548; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N14550; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N14552; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N14554; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N14556; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N14558; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107146; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107150; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107154; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107157; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107157_cpy; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_b_ff; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_b_neg; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_rst_n_rg; @@ -297459,129 +297561,122 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d2; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/N1814; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N15390; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N15392; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N15394; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N83022; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N83332; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N95825; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96106; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96107; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96109; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96110; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96120; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96124; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96158; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96160; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96167; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96271; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96272; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96274; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96318; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96883; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N15904; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N15906; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N15908; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N25006; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N59860; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N84178; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96676; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96884; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96886; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96885; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96887; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96913; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N105278; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N105949; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N106218; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N106288; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N106303; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N106624; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96888; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96898; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96900; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96902; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96937; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96939; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N96942; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N97033; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N97080; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N97478; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N97660; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/_N97662; 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+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24142; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24143; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24144; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24145; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24146; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24147; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24148; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24149; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24150; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24174; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24196; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24197; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24198; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24199; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24200; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24201; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24202; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24203; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24204; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24205; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24206; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24207; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24208; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24209; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24210; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24211; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24212; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24245; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24246; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24247; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24248; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24249; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24250; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24251; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24252; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24253; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24254; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24255; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24256; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24257; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24258; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24259; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24260; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24309; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24310; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24313; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24314; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24317; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24318; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24321; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24322; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24357; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24358; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24359; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24360; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24361; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24362; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24363; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24364; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24365; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24366; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24367; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24368; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24369; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24370; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24371; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24372; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N95788; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N96702; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N139; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24151; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N96568; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N97460; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N138; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N301; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N327; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N431; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N538; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N15882; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N15884; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22668; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22669; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22670; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22671; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N25192; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N25195; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N25196; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N25197; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N82115; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N96583; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N16437; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N16439; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N25001; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N25004; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N25005; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N82919; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_n; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass_d; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N56; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N63; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N72; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N136; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N165; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N173; @@ -297599,35 +297694,32 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddr u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N466; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N475; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N6; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N12; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N15; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N22; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N5513; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N14037; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N14039; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N14041; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N14621; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N14623; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N14625; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N17021; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N17023; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N17025; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N22696; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N62891; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N105908; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N105909; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N105917; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N105928; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N105929; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N105932; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N105937; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N105945; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N105962; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N105979; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N5539; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N14577; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N14579; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N14581; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N17029; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N17031; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N17033; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N17072; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N17074; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N17076; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N22668; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N106728; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N106729; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N106737; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N106746; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N106747; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N106750; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N106755; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N106763; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N106782; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/_N106799; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/dq_rising; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_done_flag; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_flag; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_pass; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ddrphy_gatei; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ddrphy_read_valid; @@ -297659,39 +297751,39 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddr u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_gate_vld; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/N118; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N16; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N97659; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N97664; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N105840; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N105844; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N105848; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N105852; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N105856; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N105860; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N105864; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N105868; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N105872; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N105875; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N105985; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N105989; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N105993; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N105997; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106001; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106012; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106016; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106020; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106024; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106028; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106032; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106036; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106037; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106043; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106047; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106068; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106072; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106076; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106080; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106083; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106087; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N98457; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N98462; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106662; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106666; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/_N106670; 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-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N82515; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N95827; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N96189; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N13792; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N13794; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22906; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22907; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22908; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22909; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22910; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23666; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23669; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23670; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23671; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N83337; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N96678; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N96953; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_n; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass_d; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N14; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N56; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N63; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N136; @@ -297825,33 +297920,35 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddr u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N466; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N475; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N6; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N10; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N12; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N15; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N22; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N5611; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N5601; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N14669; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N14671; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N14673; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N14706; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N14708; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N14710; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N14712; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N14714; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N15010; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N15012; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N15014; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N16024; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N16026; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N16028; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N23001; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N63902; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N106180; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N106181; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N106189; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N106200; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N106201; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N106207; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N106215; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N106229; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N106246; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N15526; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N15528; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N15530; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N22935; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N64885; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N107000; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N107001; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N107009; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N107020; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N107021; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N107024; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N107029; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N107037; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N107055; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/_N107072; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/dq_rising; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_done_flag; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_flag; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_pass; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/ddrphy_gatei; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/ddrphy_read_valid; @@ -297884,40 +297981,40 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddr u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/N118; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N11; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N16; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N97687; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N97690; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N105732; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N105736; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N105740; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N105744; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N105748; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N105752; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N105756; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N105757; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N105760; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N105765; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N105767; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N105787; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N105791; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N105795; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N105799; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N105802; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N105806; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106100; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106104; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106108; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106112; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106116; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106124; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106128; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106132; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106136; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106140; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106144; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106148; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106152; 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+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106968; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106972; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106976; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N106979; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_del; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N446; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N570; @@ -297927,35 +298024,35 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddr 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+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N14696; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N14698; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N14700; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N14702; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N14978; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N14980; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N14982; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N17097; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N17099; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N17101; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N30302; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N84168; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N88361; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N106076; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N106104; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N106106; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N106984; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N106985; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N106988; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N107347; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N107379; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_sync; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/gate_check; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/ioclk_dm; @@ -297973,33 +298070,34 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddr u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/wrlvl_dqs_en; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N194_inv; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N213; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N5777; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23364; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23366; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23369; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23371; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23380; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23382; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23399; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N95790; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N96699; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N5767; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23521; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23523; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23526; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23528; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23537; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23539; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23556; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N96570; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N97454; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N139; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N301; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N327; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N538; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N17029; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N17031; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22242; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22245; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22246; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22247; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23275; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23276; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23277; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23278; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23279; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N82905; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N96023; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N17045; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N17047; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22182; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22185; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22186; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22187; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23183; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23184; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23185; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23186; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23187; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N83739; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N96948; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N97026; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_n; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass_d; @@ -298024,27 +298122,29 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddr u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N12; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N15; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N22; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N14061; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N14063; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N14065; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N14770; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N14772; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N14774; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N16991; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N16993; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N16995; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N23286; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N64933; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N105253; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N105261; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N106260; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N106261; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N106267; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N106274; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N106275; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N106283; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N106301; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N106700; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N5686; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N14728; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N14730; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N14732; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N16954; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N16956; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N16958; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N17063; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N17065; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N17067; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N23194; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N65978; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N106060; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N106061; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N106069; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N107086; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N107087; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N107090; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N107095; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N107103; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N107107; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N107120; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/_N107512; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/dq_rising; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_done_flag; @@ -298078,40 +298178,42 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddr u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_gate_check_pass; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_gate_vld; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N118; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N11; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N16; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N97684; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N97688; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N105612; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N105616; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N105620; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N105624; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N105628; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N105639; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N105643; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N105647; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N105651; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N105655; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N105659; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N105663; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N105664; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N105670; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N105674; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N105696; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N105700; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N105704; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N105708; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N105711; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N105715; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106636; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106640; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106644; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106648; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106652; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106656; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106660; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106664; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106668; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106671; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N98454; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N98466; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106440; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106444; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106448; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106452; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106456; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106460; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106464; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106465; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106468; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106475; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106479; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106483; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106487; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106491; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106496; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106498; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106518; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106522; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106526; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106530; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106533; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N106537; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N107448; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N107452; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N107456; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N107460; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N107464; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N107468; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N107472; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N107476; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N107480; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N107483; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_del; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N446; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N570; @@ -298121,38 +298223,35 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddr u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N610; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N679; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N694_inv; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N5735; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N14778; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N14780; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N14782; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N14784; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N14788; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N14790; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N14792; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N14805; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N14807; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N14809; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N14811; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N15017; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N15019; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N15021; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N15934; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N15936; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N15938; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N30276; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N83291; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N88151; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N106513; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N106524; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N106558; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N106611; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N106614; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N106616; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N106626; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N106628; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N106676; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N106677; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N106680; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N5725; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N14736; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N14738; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N14740; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N14742; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N14746; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N14748; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N14750; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N14761; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N14763; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N14765; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N14767; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N15081; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N15083; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N15085; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N17105; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N17107; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N17109; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N30395; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N84859; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N88943; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N107331; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N107342; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N107376; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N107438; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N107440; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N107488; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N107489; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N107492; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_sync; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/gate_check; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/ioclk_dm; @@ -298170,45 +298269,47 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddr u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/wrlvl_dqs_en; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N194_inv; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N213; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N5851; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23998; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24000; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24003; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24005; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24014; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24016; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24033; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N95791; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N96708; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N5877; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23777; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23779; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23782; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23784; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23793; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23795; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23812; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N96571; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N97476; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N139; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N301; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N327; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N538; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N16084; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N16086; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22684; 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-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23677; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N83280; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N96259; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N96322; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N15002; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N15004; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22628; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22631; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22632; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N22633; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23590; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23591; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23592; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23593; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N23594; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N84115; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N97084; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/_N97098; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_n; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass_d; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N14; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N56; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N72; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N63; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N136; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N165; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N173; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N228; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N286; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N296; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N334; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N359; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N377; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N386; @@ -298217,33 +298318,31 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddr u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N466; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N475; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N6; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N12; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N15; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N22; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N5801; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N13890; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N13892; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N13894; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N14829; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N14831; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N14833; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N15920; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N15922; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N15924; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N23837; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N65991; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N105242; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N105247; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N106316; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N106361; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N106362; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N106370; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N106371; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N106796; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N106804; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N106805; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N106810; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N106813; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N106818; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N5839; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N14714; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N14716; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N14718; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N14793; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N14795; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N14797; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N17037; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N17039; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N17041; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N23628; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N67087; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N106050; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N107179; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N107180; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N107188; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N107189; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N107615; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N107623; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N107624; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N107633; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/_N107647; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/dq_rising; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_done_flag; @@ -298278,39 +298377,39 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddr u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_gate_vld; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N118; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/N315; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N84566; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N97685; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N97689; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N105487; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N105491; 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-u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N105584; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N105588; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N105592; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N105595; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N105599; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N106398; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N106402; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N106406; 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+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N106404; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N106408; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N106412; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N106416; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N106419; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N106423; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N107216; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N107220; 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+u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N107260; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N107264; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N107268; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N107272; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/_N107275; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_del; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N446; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N570; @@ -298320,43 +298419,43 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddr u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N610; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N679; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N694_inv; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N5820; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N14837; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N5858; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N14810; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N14812; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N14814; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N14816; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N14820; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N14822; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N14824; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N14839; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N14841; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N14843; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N14847; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N14849; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N14851; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N14865; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N14867; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N14869; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N14871; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N15480; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N15482; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N15484; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N15762; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N15764; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N15766; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N30323; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N83434; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N83645; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N88729; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N105284; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N105285; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N105286; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N105287; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N106461; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N106462; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N106465; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N106480; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N106482; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N106485; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N106495; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N106496; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N106499; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N106510; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N106555; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N14845; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N16279; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N16281; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N16283; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N16961; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N16963; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N16965; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N30422; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N84280; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N84865; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N89521; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N107279; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N107280; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N107283; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N107298; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N107300; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N107303; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N107313; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N107314; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N107317; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N107328; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N107373; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N107431; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N107432; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N107433; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N107434; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_sync; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/gate_check; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ioclk_dm; @@ -298460,8 +298559,8 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/buffer_almost_full; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/dcd_wr_en; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/dcd_wr_tworw; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/ddrc_init_done; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/_N96029; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/_N96341; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/_N97165; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/_N97168; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/dec_done; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/dec_new_row; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/dec_new_valid; @@ -298477,36 +298576,36 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N252; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N281; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N304; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N317; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N6205; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N13492; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N13494; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N13496; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N13498; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N13500; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24498; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24507; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24508; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24509; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24510; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24511; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24512; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24513; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24514; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24515; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24516; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24517; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24518; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24519; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24520; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24521; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24867; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24870; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N105211; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N6298; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N15891; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N15893; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N15895; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N15897; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N15899; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24218; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24227; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24228; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24229; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24230; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24231; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24232; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24233; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24234; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24235; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24236; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24237; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24238; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24239; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24240; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24241; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24587; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N24590; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N96998; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N96999; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N97000; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N97001; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/_N106247; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/N28; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/_N96290; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/_N96291; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/_N96292; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/_N96293; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/r_init; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_req; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/rowaddr_check_diff; @@ -298514,21 +298613,20 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N39; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N89; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N258; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N371; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N404; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N410; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N416; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N418; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N458; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N461; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N491; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/_N15216; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/_N15218; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/_N15220; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/_N24960; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/_N24969; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/_N84037; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/_N95818; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/_N96157; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/_N15257; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/_N15259; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/_N15261; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/_N24686; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/_N24695; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/_N84823; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/_N96670; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/_N107589; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/rw_diff; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/back_valid; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/ctrl_back_rdy; @@ -298548,123 +298646,122 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/P u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N61; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N69; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/_N3_inv_1; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/_N6888; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/_N104959; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/_N104965; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/_N6961; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/_N105977; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/_N105983; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/cmd_wr; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/N55; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/N61; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/N69; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/_N3_inv_1; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/_N7000; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/_N104895; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/_N104901; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/_N7073; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/_N105913; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/_N105919; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/cmd_wr; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/N55; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/N61; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/N69; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/_N3_inv_1; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/_N7112; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/_N104927; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/_N104933; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/_N7185; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/_N105945; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/_N105951; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/cmd_wr; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/N55; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/N61; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/N69; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/_N3_inv_1; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/_N7224; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/_N104863; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/_N104869; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/_N7297; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/_N105881; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/_N105887; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/cmd_wr; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/N55; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/N61; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/N69; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/_N3_inv_1; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/_N7336; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/_N104943; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/_N104949; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/_N7409; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/_N105961; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/_N105967; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/cmd_wr; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/N55; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/N61; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/N69; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/_N3_inv_1; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/_N7448; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/_N104879; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/_N104885; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/_N7521; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/_N105897; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/_N105903; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/cmd_wr; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/N55; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/N61; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/N69; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/_N3_inv_1; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/_N7560; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/_N104911; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/_N104917; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/_N7633; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/_N105929; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/_N105935; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/cmd_wr; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/N55; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/N61; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/N69; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/_N3_inv_1; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/_N7672; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/_N104847; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/_N104853; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/_N7745; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/_N105865; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/_N105871; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/cmd_wr; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/N7; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/N25; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/_N104755; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/_N105799; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/N25; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/_N104747; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/_N105791; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/N25; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/_N104751; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/_N105795; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/N25; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/_N104743; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/_N105787; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/N25; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/_N104753; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/_N105797; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/N25; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/_N104745; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/_N105789; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/N25; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/_N104749; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/_N105793; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/N25; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/_N104741; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/_N105785; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/N7; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/N25; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/_N104787; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/_N105831; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/N7; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/N25; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/_N104771; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/_N105815; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/N7; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/N25; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/_N104779; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/_N105823; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/N7; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/N25; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/_N104763; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/_N105807; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/N7; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/N25; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/_N104783; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/_N105827; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/N7; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/N25; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/_N104767; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/_N105811; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/N7; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/N25; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/_N104775; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/_N105819; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/N7; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/N25; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/_N104757; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N24995; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N25010; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N25035; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N25040; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N25041; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N84089; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N96409; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N96411; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N96414; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N96417; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N96417_cpy; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N96772; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N102308_2; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N102308_3; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N104834; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N104986; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/_N105801; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N24721; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N24736; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N24761; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N24766; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N24767; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N84881; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N97171; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N97173; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N97176; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N97179; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N97179_cpy; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N97564; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N103547_2; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N103547_3; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N105852; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N106004; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_valid_d1; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/cmd_accepted_l; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/cmd_act_pass; @@ -298705,21 +298802,21 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/t u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/N12; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/N19; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/r_cnt_pass; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/_N104805; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/_N105849; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N31; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N45; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N47; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N3; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N6430; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N15659; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N17324; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N17326; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N25124; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N25139; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N96430; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N103199_2; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N104968; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N104973; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N6513; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N15350; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N17302; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N17304; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N24930; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N24945; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N97061; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N97072; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N103967_2; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N105986; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N105991; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/cmd_pre; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/N50; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/N55; @@ -298730,41 +298827,40 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/t u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N27; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N29; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/N35_inv_1; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/_N6672; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/_N15265; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/_N22538; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/_N96352; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/_N96653; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/_N97011; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/_N6745; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/_N15294; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/_N22394; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/_N96730; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/_N97405; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/_N97780; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/N14; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/N27; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/N98; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/N106; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/full; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N16; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N19; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N26; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/_N15089; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/_N15091; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/_N15095; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/_N15097; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/_N15118; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/_N15120; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/_N15124; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/_N15126; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_en_real; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/full; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N16; 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u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_en_real; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N119; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N126; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N193; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N197; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N198; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/_N15643; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/_N15645; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/_N15565; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/_N15567; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/buffer_almost_full_a; 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+u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/_N15242; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/_N15244; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/_N103130_2; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/axi_arvalid; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/double_wr; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N10; @@ -298870,6 +298965,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/N14; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_valid_0; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_valid_1; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/rptr; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_data_in_ready; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_data_in_valid; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_write; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/ptr; @@ -298882,10 +298978,10 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/wptr; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/full; u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/N16; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/_N15026; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/_N15028; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/_N15032; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/_N15034; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/_N15009; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/_N15011; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/_N15015; 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-u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/_N14555; -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/_N14557; -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/_N14693; -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/_N14695; -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/_N14697; -u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/_N14699; +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/_N14505; +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/_N14507; +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/_N14509; +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/_N14511; +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/_N14652; +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/_N14654; +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/_N14656; +u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/_N14658; u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wfull; u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/N22; +u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/_N15021; +u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/_N15023; +u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/_N15025; +u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/_N15027; +u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/_N15029; +u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/_N15034; +u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/_N15036; u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/_N15038; u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/_N15040; -u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/_N15042; -u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/_N15044; -u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/_N15046; -u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/_N15051; -u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/_N15053; -u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/_N15055; -u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/_N15057; u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/wfull; u_axi_ddr_top/wdata_empty; u_axi_ddr_top/wr3_en; @@ -299278,39 +299374,37 @@ u_axi_rst/rst0; u_axi_rst/rst1; u_clk50m_rst/rst0; u_clk50m_rst/rst1; -u_ddr_addr_ctr/N69; -u_ddr_addr_ctr/N73; -u_ddr_addr_ctr/_N13646; -u_ddr_addr_ctr/_N13648; -u_ddr_addr_ctr/_N13650; -u_ddr_addr_ctr/_N13652; -u_ddr_addr_ctr/_N13654; -u_ddr_addr_ctr/_N13656; -u_ddr_addr_ctr/_N13658; -u_ddr_addr_ctr/_N13660; -u_ddr_addr_ctr/_N13662; -u_ddr_addr_ctr/_N13664; -u_ddr_addr_ctr/_N103666; -u_ddr_addr_ctr/_N103670; -u_ddr_addr_ctr/_N103674; -u_ddr_addr_ctr/_N103678; -u_ddr_addr_ctr/_N103682; +u_ddr_addr_ctr/N72; +u_ddr_addr_ctr/N76; +u_ddr_addr_ctr/_N15998; +u_ddr_addr_ctr/_N16000; +u_ddr_addr_ctr/_N16002; +u_ddr_addr_ctr/_N16004; +u_ddr_addr_ctr/_N16006; +u_ddr_addr_ctr/_N16008; +u_ddr_addr_ctr/_N16010; +u_ddr_addr_ctr/_N16012; +u_ddr_addr_ctr/_N16014; +u_ddr_addr_ctr/_N104489; +u_ddr_addr_ctr/_N104493; +u_ddr_addr_ctr/_N104497; +u_ddr_addr_ctr/_N104498; u_ddr_addr_ctr/rd1_vs0; u_ddr_addr_ctr/u_rd0_addr_ctr/N131; u_ddr_addr_ctr/u_rd0_addr_ctr/N152; -u_ddr_addr_ctr/u_rd0_addr_ctr/_N13668; -u_ddr_addr_ctr/u_rd0_addr_ctr/_N13670; -u_ddr_addr_ctr/u_rd0_addr_ctr/_N13672; -u_ddr_addr_ctr/u_rd0_addr_ctr/_N13676; -u_ddr_addr_ctr/u_rd0_addr_ctr/_N13678; -u_ddr_addr_ctr/u_rd0_addr_ctr/_N13680; -u_ddr_addr_ctr/u_rd0_addr_ctr/_N13682; -u_ddr_addr_ctr/u_rd0_addr_ctr/_N13684; -u_ddr_addr_ctr/u_rd0_addr_ctr/_N13686; -u_ddr_addr_ctr/u_rd0_addr_ctr/_N13688; -u_ddr_addr_ctr/u_rd0_addr_ctr/_N13690; -u_ddr_addr_ctr/u_rd0_addr_ctr/_N13692; -u_ddr_addr_ctr/u_rd0_addr_ctr/_N104723; +u_ddr_addr_ctr/u_rd0_addr_ctr/_N13636; +u_ddr_addr_ctr/u_rd0_addr_ctr/_N13638; +u_ddr_addr_ctr/u_rd0_addr_ctr/_N13640; +u_ddr_addr_ctr/u_rd0_addr_ctr/_N13644; +u_ddr_addr_ctr/u_rd0_addr_ctr/_N13646; +u_ddr_addr_ctr/u_rd0_addr_ctr/_N13648; +u_ddr_addr_ctr/u_rd0_addr_ctr/_N13650; +u_ddr_addr_ctr/u_rd0_addr_ctr/_N13652; +u_ddr_addr_ctr/u_rd0_addr_ctr/_N13654; +u_ddr_addr_ctr/u_rd0_addr_ctr/_N13656; +u_ddr_addr_ctr/u_rd0_addr_ctr/_N13658; +u_ddr_addr_ctr/u_rd0_addr_ctr/_N13660; +u_ddr_addr_ctr/u_rd0_addr_ctr/_N105736; u_ddr_addr_ctr/u_rd0_addr_ctr/image_perimt; u_ddr_addr_ctr/u_rd0_addr_ctr/image_perimt0; u_ddr_addr_ctr/u_rd0_addr_ctr/image_perimt1; @@ -299320,11 +299414,11 @@ u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_done_rise; u_ddr_addr_ctr/u_rd1_addr_ctr/N16; u_ddr_addr_ctr/u_rd1_addr_ctr/N259; u_ddr_addr_ctr/u_rd1_addr_ctr/N271; -u_ddr_addr_ctr/u_rd1_addr_ctr/_N16092; -u_ddr_addr_ctr/u_rd1_addr_ctr/_N16094; -u_ddr_addr_ctr/u_rd1_addr_ctr/_N16096; -u_ddr_addr_ctr/u_rd1_addr_ctr/_N16098; -u_ddr_addr_ctr/u_rd1_addr_ctr/_N16100; +u_ddr_addr_ctr/u_rd1_addr_ctr/_N16071; +u_ddr_addr_ctr/u_rd1_addr_ctr/_N16073; +u_ddr_addr_ctr/u_rd1_addr_ctr/_N16075; +u_ddr_addr_ctr/u_rd1_addr_ctr/_N16077; +u_ddr_addr_ctr/u_rd1_addr_ctr/_N16079; u_ddr_addr_ctr/u_rd1_addr_ctr/empty; u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_done0; u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_done1; @@ -299336,40 +299430,40 @@ u_ddr_addr_ctr/u_rd1_addr_ctr/rd_vs0; u_ddr_addr_ctr/u_rd1_addr_ctr/rd_vs1; u_ddr_addr_ctr/u_rd1_addr_ctr/rd_vs_rise0; u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/N21; -u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/_N16177; -u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/_N16179; -u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/_N16181; -u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/_N16183; -u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/_N16187; -u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/_N16189; -u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/_N16191; -u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/_N16193; +u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/_N16139; +u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/_N16141; +u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/_N16143; +u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/_N16145; +u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/_N16149; +u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/_N16151; +u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/_N16153; +u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/_N16155; u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/wfull; u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/N0; u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/data_vary0; u_ddr_addr_ctr/u_rd3_addr_ctr/N34; u_ddr_addr_ctr/u_rd3_addr_ctr/N44; -u_ddr_addr_ctr/u_rd3_addr_ctr/_N9428; -u_ddr_addr_ctr/u_rd3_addr_ctr/_N9446; -u_ddr_addr_ctr/u_rd3_addr_ctr/_N14442; -u_ddr_addr_ctr/u_rd3_addr_ctr/_N14444; -u_ddr_addr_ctr/u_rd3_addr_ctr/_N14446; -u_ddr_addr_ctr/u_rd3_addr_ctr/_N14448; -u_ddr_addr_ctr/u_rd3_addr_ctr/_N14450; -u_ddr_addr_ctr/u_rd3_addr_ctr/_N14452; -u_ddr_addr_ctr/u_rd3_addr_ctr/_N14454; -u_ddr_addr_ctr/u_rd3_addr_ctr/_N16156; -u_ddr_addr_ctr/u_rd3_addr_ctr/_N16158; -u_ddr_addr_ctr/u_rd3_addr_ctr/_N16160; -u_ddr_addr_ctr/u_rd3_addr_ctr/_N16162; -u_ddr_addr_ctr/u_rd3_addr_ctr/_N16164; -u_ddr_addr_ctr/u_rd3_addr_ctr/_N16209; -u_ddr_addr_ctr/u_rd3_addr_ctr/_N16211; -u_ddr_addr_ctr/u_rd3_addr_ctr/_N16213; -u_ddr_addr_ctr/u_rd3_addr_ctr/_N16215; -u_ddr_addr_ctr/u_rd3_addr_ctr/_N16217; -u_ddr_addr_ctr/u_rd3_addr_ctr/_N16219; -u_ddr_addr_ctr/u_rd3_addr_ctr/_N16221; +u_ddr_addr_ctr/u_rd3_addr_ctr/_N9458; +u_ddr_addr_ctr/u_rd3_addr_ctr/_N9476; +u_ddr_addr_ctr/u_rd3_addr_ctr/_N15090; +u_ddr_addr_ctr/u_rd3_addr_ctr/_N15092; +u_ddr_addr_ctr/u_rd3_addr_ctr/_N15094; +u_ddr_addr_ctr/u_rd3_addr_ctr/_N15096; +u_ddr_addr_ctr/u_rd3_addr_ctr/_N15098; +u_ddr_addr_ctr/u_rd3_addr_ctr/_N15100; +u_ddr_addr_ctr/u_rd3_addr_ctr/_N15102; +u_ddr_addr_ctr/u_rd3_addr_ctr/_N16118; +u_ddr_addr_ctr/u_rd3_addr_ctr/_N16120; +u_ddr_addr_ctr/u_rd3_addr_ctr/_N16122; +u_ddr_addr_ctr/u_rd3_addr_ctr/_N16124; +u_ddr_addr_ctr/u_rd3_addr_ctr/_N16126; +u_ddr_addr_ctr/u_rd3_addr_ctr/_N16159; +u_ddr_addr_ctr/u_rd3_addr_ctr/_N16161; +u_ddr_addr_ctr/u_rd3_addr_ctr/_N16163; +u_ddr_addr_ctr/u_rd3_addr_ctr/_N16165; +u_ddr_addr_ctr/u_rd3_addr_ctr/_N16167; +u_ddr_addr_ctr/u_rd3_addr_ctr/_N16169; +u_ddr_addr_ctr/u_rd3_addr_ctr/_N16171; u_ddr_addr_ctr/u_rd3_addr_ctr/rd_ddr_valid0; u_ddr_addr_ctr/u_rd3_addr_ctr/rd_ddr_valid1; u_ddr_addr_ctr/u_rd3_addr_ctr/rd_ddr_valid2; @@ -299404,7 +299498,7 @@ u_ddr_addr_ctr/u_wr1_addr_ctr/wr_vs_flag; u_ddr_addr_ctr/u_wr3_addr_ctr/N73; u_ddr_addr_ctr/u_wr3_addr_ctr/N103; u_ddr_addr_ctr/u_wr3_addr_ctr/N108; -u_ddr_addr_ctr/u_wr3_addr_ctr/_N84166; +u_ddr_addr_ctr/u_wr3_addr_ctr/_N85000; u_ddr_addr_ctr/u_wr3_addr_ctr/wr_ddr_done0; u_ddr_addr_ctr/u_wr3_addr_ctr/wr_ddr_done1; u_ddr_addr_ctr/u_wr3_addr_ctr/wr_ddr_done2; @@ -299467,18 +299561,18 @@ u_ov5640/coms1_reg_config/N12; u_ov5640/coms1_reg_config/N1134; u_ov5640/coms1_reg_config/N1169; u_ov5640/coms1_reg_config/N1193; -u_ov5640/coms1_reg_config/_N9664; -u_ov5640/coms1_reg_config/_N9682; -u_ov5640/coms1_reg_config/_N9690; -u_ov5640/coms1_reg_config/_N16246; -u_ov5640/coms1_reg_config/_N16248; -u_ov5640/coms1_reg_config/_N16250; -u_ov5640/coms1_reg_config/_N16252; -u_ov5640/coms1_reg_config/_N16384; -u_ov5640/coms1_reg_config/_N16386; -u_ov5640/coms1_reg_config/_N16388; -u_ov5640/coms1_reg_config/_N96528; -u_ov5640/coms1_reg_config/_N106873; +u_ov5640/coms1_reg_config/_N9677; +u_ov5640/coms1_reg_config/_N9695; +u_ov5640/coms1_reg_config/_N9703; +u_ov5640/coms1_reg_config/_N16268; +u_ov5640/coms1_reg_config/_N16270; +u_ov5640/coms1_reg_config/_N16272; +u_ov5640/coms1_reg_config/_N16274; +u_ov5640/coms1_reg_config/_N16288; +u_ov5640/coms1_reg_config/_N16290; +u_ov5640/coms1_reg_config/_N16292; +u_ov5640/coms1_reg_config/_N97285; +u_ov5640/coms1_reg_config/_N107702; u_ov5640/coms1_reg_config/clk_20k_regdiv; u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite; u_ov5640/coms1_reg_config/clock_20k; @@ -299486,22 +299580,22 @@ u_ov5640/coms1_reg_config/start; u_ov5640/coms1_reg_config/tr_end; u_ov5640/coms1_reg_config/u1/N195; u_ov5640/coms1_reg_config/u1/N239; -u_ov5640/coms1_reg_config/u1/_N16393; -u_ov5640/coms1_reg_config/u1/_N16395; -u_ov5640/coms1_reg_config/u1/_N25450; -u_ov5640/coms1_reg_config/u1/_N25453; -u_ov5640/coms1_reg_config/u1/_N25456; -u_ov5640/coms1_reg_config/u1/_N25461; -u_ov5640/coms1_reg_config/u1/_N25467; -u_ov5640/coms1_reg_config/u1/_N25468; -u_ov5640/coms1_reg_config/u1/_N84271; -u_ov5640/coms1_reg_config/u1/_N95900; -u_ov5640/coms1_reg_config/u1/_N95931; -u_ov5640/coms1_reg_config/u1/_N96534; -u_ov5640/coms1_reg_config/u1/_N96769; -u_ov5640/coms1_reg_config/u1/_N98079; -u_ov5640/coms1_reg_config/u1/_N103821; -u_ov5640/coms1_reg_config/u1/_N106880; +u_ov5640/coms1_reg_config/u1/_N16297; +u_ov5640/coms1_reg_config/u1/_N16299; +u_ov5640/coms1_reg_config/u1/_N25300; +u_ov5640/coms1_reg_config/u1/_N25303; +u_ov5640/coms1_reg_config/u1/_N25306; +u_ov5640/coms1_reg_config/u1/_N25311; +u_ov5640/coms1_reg_config/u1/_N25317; +u_ov5640/coms1_reg_config/u1/_N25318; +u_ov5640/coms1_reg_config/u1/_N85071; +u_ov5640/coms1_reg_config/u1/_N96805; +u_ov5640/coms1_reg_config/u1/_N97112; +u_ov5640/coms1_reg_config/u1/_N97234; +u_ov5640/coms1_reg_config/u1/_N97669; +u_ov5640/coms1_reg_config/u1/_N99985; +u_ov5640/coms1_reg_config/u1/_N104644; +u_ov5640/coms1_reg_config/u1/_N107709; u_ov5640/coms1_reg_config/u1/reg_sdat_rnmt; u_ov5640/coms1_reg_config/u1/sclk; u_ov5640/coms2_reg_config/N8; @@ -299509,62 +299603,66 @@ u_ov5640/coms2_reg_config/N12; u_ov5640/coms2_reg_config/N1134; u_ov5640/coms2_reg_config/N1169; u_ov5640/coms2_reg_config/N1193; -u_ov5640/coms2_reg_config/_N9736; -u_ov5640/coms2_reg_config/_N9754; -u_ov5640/coms2_reg_config/_N9762; -u_ov5640/coms2_reg_config/_N16399; -u_ov5640/coms2_reg_config/_N16401; -u_ov5640/coms2_reg_config/_N16403; -u_ov5640/coms2_reg_config/_N16405; -u_ov5640/coms2_reg_config/_N16411; -u_ov5640/coms2_reg_config/_N16413; -u_ov5640/coms2_reg_config/_N16415; -u_ov5640/coms2_reg_config/_N96531; -u_ov5640/coms2_reg_config/_N103874; +u_ov5640/coms2_reg_config/_N9749; +u_ov5640/coms2_reg_config/_N9767; +u_ov5640/coms2_reg_config/_N9775; +u_ov5640/coms2_reg_config/_N16303; +u_ov5640/coms2_reg_config/_N16305; +u_ov5640/coms2_reg_config/_N16307; +u_ov5640/coms2_reg_config/_N16309; +u_ov5640/coms2_reg_config/_N16315; +u_ov5640/coms2_reg_config/_N16317; +u_ov5640/coms2_reg_config/_N16319; +u_ov5640/coms2_reg_config/_N97290; +u_ov5640/coms2_reg_config/_N104698; u_ov5640/coms2_reg_config/clk_20k_regdiv; u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite; u_ov5640/coms2_reg_config/clock_20k; u_ov5640/coms2_reg_config/start; u_ov5640/coms2_reg_config/tr_end; -u_ov5640/coms2_reg_config/u1/N146; -u_ov5640/coms2_reg_config/u1/N185; -u_ov5640/coms2_reg_config/u1/N187; u_ov5640/coms2_reg_config/u1/N195; -u_ov5640/coms2_reg_config/u1/_N16420; -u_ov5640/coms2_reg_config/u1/_N16422; -u_ov5640/coms2_reg_config/u1/_N25893; -u_ov5640/coms2_reg_config/u1/_N25896; -u_ov5640/coms2_reg_config/u1/_N25899; -u_ov5640/coms2_reg_config/u1/_N25904; -u_ov5640/coms2_reg_config/u1/_N25910; -u_ov5640/coms2_reg_config/u1/_N25911; -u_ov5640/coms2_reg_config/u1/_N84324; -u_ov5640/coms2_reg_config/u1/_N96487; -u_ov5640/coms2_reg_config/u1/_N96610; -u_ov5640/coms2_reg_config/u1/_N96977; -u_ov5640/coms2_reg_config/u1/_N106895; -u_ov5640/coms2_reg_config/u1/_N106896; +u_ov5640/coms2_reg_config/u1/N239; +u_ov5640/coms2_reg_config/u1/N256; +u_ov5640/coms2_reg_config/u1/N267; +u_ov5640/coms2_reg_config/u1/_N16324; +u_ov5640/coms2_reg_config/u1/_N16326; +u_ov5640/coms2_reg_config/u1/_N25830; +u_ov5640/coms2_reg_config/u1/_N25833; +u_ov5640/coms2_reg_config/u1/_N25837; +u_ov5640/coms2_reg_config/u1/_N25840; +u_ov5640/coms2_reg_config/u1/_N25845; +u_ov5640/coms2_reg_config/u1/_N25848; +u_ov5640/coms2_reg_config/u1/_N25853; +u_ov5640/coms2_reg_config/u1/_N25859; +u_ov5640/coms2_reg_config/u1/_N85124; +u_ov5640/coms2_reg_config/u1/_N87597; +u_ov5640/coms2_reg_config/u1/_N97064; +u_ov5640/coms2_reg_config/u1/_N97132; +u_ov5640/coms2_reg_config/u1/_N97333; +u_ov5640/coms2_reg_config/u1/_N97590; +u_ov5640/coms2_reg_config/u1/_N97699; +u_ov5640/coms2_reg_config/u1/_N104685; u_ov5640/coms2_reg_config/u1/reg_sdat_rnmt; u_ov5640/coms2_reg_config/u1/sclk; u_ov5640/power_on_delay_inst/N15; -u_ov5640/power_on_delay_inst/_N13709; -u_ov5640/power_on_delay_inst/_N13711; -u_ov5640/power_on_delay_inst/_N13713; -u_ov5640/power_on_delay_inst/_N13715; -u_ov5640/power_on_delay_inst/_N13717; -u_ov5640/power_on_delay_inst/_N13719; -u_ov5640/power_on_delay_inst/_N13721; -u_ov5640/power_on_delay_inst/_N13723; -u_ov5640/power_on_delay_inst/_N16426; -u_ov5640/power_on_delay_inst/_N16428; -u_ov5640/power_on_delay_inst/_N16430; -u_ov5640/power_on_delay_inst/_N16432; -u_ov5640/power_on_delay_inst/_N16434; -u_ov5640/power_on_delay_inst/_N16436; -u_ov5640/power_on_delay_inst/_N16438; -u_ov5640/power_on_delay_inst/_N106851; -u_ov5640/power_on_delay_inst/_N106855; -u_ov5640/power_on_delay_inst/_N106859; +u_ov5640/power_on_delay_inst/_N13678; +u_ov5640/power_on_delay_inst/_N13680; +u_ov5640/power_on_delay_inst/_N13682; +u_ov5640/power_on_delay_inst/_N13684; +u_ov5640/power_on_delay_inst/_N13686; +u_ov5640/power_on_delay_inst/_N13688; +u_ov5640/power_on_delay_inst/_N13690; +u_ov5640/power_on_delay_inst/_N13692; +u_ov5640/power_on_delay_inst/_N16330; +u_ov5640/power_on_delay_inst/_N16332; +u_ov5640/power_on_delay_inst/_N16334; +u_ov5640/power_on_delay_inst/_N16336; +u_ov5640/power_on_delay_inst/_N16338; +u_ov5640/power_on_delay_inst/_N16340; +u_ov5640/power_on_delay_inst/_N16342; +u_ov5640/power_on_delay_inst/_N107680; +u_ov5640/power_on_delay_inst/_N107684; +u_ov5640/power_on_delay_inst/_N107688; u_ov5640/power_on_delay_inst/camera_pwnd; u_ov5640/u_mix_image/N311; u_ov5640/u_mix_image/N315; @@ -299575,33 +299673,33 @@ u_ov5640/u_mix_image/N415; u_ov5640/u_mix_image/N417; u_ov5640/u_mix_image/N427; u_ov5640/u_mix_image/_N4; -u_ov5640/u_mix_image/_N13728; -u_ov5640/u_mix_image/_N13730; -u_ov5640/u_mix_image/_N13732; -u_ov5640/u_mix_image/_N13734; -u_ov5640/u_mix_image/_N16442; -u_ov5640/u_mix_image/_N16444; -u_ov5640/u_mix_image/_N16446; -u_ov5640/u_mix_image/_N16448; -u_ov5640/u_mix_image/_N16476; -u_ov5640/u_mix_image/_N16478; -u_ov5640/u_mix_image/_N16480; -u_ov5640/u_mix_image/_N16482; -u_ov5640/u_mix_image/_N16498; -u_ov5640/u_mix_image/_N16500; -u_ov5640/u_mix_image/_N16502; -u_ov5640/u_mix_image/_N16504; -u_ov5640/u_mix_image/_N96537; -u_ov5640/u_mix_image/_N96993; -u_ov5640/u_mix_image/_N103792; -u_ov5640/u_mix_image/_N103793; -u_ov5640/u_mix_image/_N103802; -u_ov5640/u_mix_image/_N103803; -u_ov5640/u_mix_image/_N103812; -u_ov5640/u_mix_image/_N103813; -u_ov5640/u_mix_image/_N103845; -u_ov5640/u_mix_image/_N103853; -u_ov5640/u_mix_image/_N103854; +u_ov5640/u_mix_image/_N13697; +u_ov5640/u_mix_image/_N13699; +u_ov5640/u_mix_image/_N13701; +u_ov5640/u_mix_image/_N13703; +u_ov5640/u_mix_image/_N16346; +u_ov5640/u_mix_image/_N16348; +u_ov5640/u_mix_image/_N16350; +u_ov5640/u_mix_image/_N16352; +u_ov5640/u_mix_image/_N16380; +u_ov5640/u_mix_image/_N16382; +u_ov5640/u_mix_image/_N16384; +u_ov5640/u_mix_image/_N16386; +u_ov5640/u_mix_image/_N16402; +u_ov5640/u_mix_image/_N16404; +u_ov5640/u_mix_image/_N16406; +u_ov5640/u_mix_image/_N16408; +u_ov5640/u_mix_image/_N97291; +u_ov5640/u_mix_image/_N97559; +u_ov5640/u_mix_image/_N104615; +u_ov5640/u_mix_image/_N104616; +u_ov5640/u_mix_image/_N104625; +u_ov5640/u_mix_image/_N104626; +u_ov5640/u_mix_image/_N104635; +u_ov5640/u_mix_image/_N104636; +u_ov5640/u_mix_image/_N104668; +u_ov5640/u_mix_image/_N104676; +u_ov5640/u_mix_image/_N104677; u_ov5640/u_mix_image/cmos1_vsync_rise; u_ov5640/u_mix_image/cmos2_vsync_rise; u_ov5640/u_mix_image/data_out_valid0; @@ -299615,44 +299713,42 @@ u_ov5640/u_mix_image/rd_vs0; u_ov5640/u_mix_image/rd_vs1; u_ov5640/u_mix_image/rd_vs2; u_ov5640/u_mix_image/rd_vs_rise; -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16509; -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16511; -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16513; -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16515; -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16517; -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16521; -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16523; -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16525; -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16527; -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16529; -u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N108362; +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16413; +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16415; +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16417; +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16419; +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16421; +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16425; +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16427; +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16429; +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16431; +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16433; +u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N109247; u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wfull; -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16453; -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16455; -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16457; -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16459; -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16461; -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16533; -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16535; -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16537; -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16539; -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16541; -u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N108363; +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16357; +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16359; +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16361; +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16363; +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16365; +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16443; +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16445; +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16447; +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16449; +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16451; +u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N109248; u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wfull; u_ov5640/u_mix_image/wr1_en; u_ov5640/u_mix_image/wr2_en; u_rotate_image/N52; u_rotate_image/N170; -u_rotate_image/N302; +u_rotate_image/N350; u_rotate_image/_N17; -u_rotate_image/_N9883; -u_rotate_image/_N9905; -u_rotate_image/_N9923; -u_rotate_image/_N9933; -u_rotate_image/_N9939; -u_rotate_image/_N9967; -u_rotate_image/_N12915; -u_rotate_image/_N12916; +u_rotate_image/_N9918; +u_rotate_image/_N9940; +u_rotate_image/_N9958; +u_rotate_image/_N9968; +u_rotate_image/_N9974; +u_rotate_image/_N10002; u_rotate_image/_N12917; u_rotate_image/_N12918; u_rotate_image/_N12919; @@ -299701,43 +299797,45 @@ u_rotate_image/_N12961; u_rotate_image/_N12962; u_rotate_image/_N12963; u_rotate_image/_N12964; -u_rotate_image/_N16225; -u_rotate_image/_N16227; -u_rotate_image/_N16229; -u_rotate_image/_N16231; -u_rotate_image/_N16233; -u_rotate_image/_N16235; -u_rotate_image/_N16237; -u_rotate_image/_N16239; -u_rotate_image/_N16241; -u_rotate_image/_N16545; -u_rotate_image/_N16547; -u_rotate_image/_N16549; -u_rotate_image/_N16551; -u_rotate_image/_N16572; -u_rotate_image/_N16574; -u_rotate_image/_N16576; -u_rotate_image/_N16578; -u_rotate_image/_N16592; -u_rotate_image/_N16594; -u_rotate_image/_N16596; -u_rotate_image/_N16598; -u_rotate_image/_N16600; -u_rotate_image/_N16602; -u_rotate_image/_N16604; -u_rotate_image/_N16606; -u_rotate_image/_N16608; -u_rotate_image/_N104107; -u_rotate_image/_N104578; -u_rotate_image/_N104579; -u_rotate_image/_N104610; -u_rotate_image/_N104611; -u_rotate_image/_N104621; -u_rotate_image/_N104622; -u_rotate_image/_N104623; -u_rotate_image/_N104630; -u_rotate_image/_N104632; -u_rotate_image/_N104639; +u_rotate_image/_N12965; +u_rotate_image/_N12966; +u_rotate_image/_N16175; +u_rotate_image/_N16177; +u_rotate_image/_N16179; +u_rotate_image/_N16181; +u_rotate_image/_N16183; +u_rotate_image/_N16185; +u_rotate_image/_N16187; +u_rotate_image/_N16189; +u_rotate_image/_N16191; +u_rotate_image/_N16455; +u_rotate_image/_N16457; +u_rotate_image/_N16459; +u_rotate_image/_N16461; +u_rotate_image/_N16477; +u_rotate_image/_N16479; +u_rotate_image/_N16481; +u_rotate_image/_N16483; +u_rotate_image/_N16497; +u_rotate_image/_N16499; +u_rotate_image/_N16501; +u_rotate_image/_N16503; +u_rotate_image/_N16505; +u_rotate_image/_N16507; +u_rotate_image/_N16509; +u_rotate_image/_N16511; +u_rotate_image/_N16513; +u_rotate_image/_N104946; +u_rotate_image/_N105413; +u_rotate_image/_N105414; +u_rotate_image/_N105445; +u_rotate_image/_N105446; +u_rotate_image/_N105456; +u_rotate_image/_N105457; +u_rotate_image/_N105458; +u_rotate_image/_N105465; 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u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wfull; -u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16650; -u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16652; -u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16654; -u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16656; -u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16658; -u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16662; -u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16664; -u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16666; -u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16668; -u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16670; 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u_sync_vg/N54; u_sync_vg/N61; u_sync_vg/N145; u_sync_vg/N178; u_sync_vg/N185; -u_sync_vg/_N10003; -u_sync_vg/_N10011; u_sync_vg/_N10039; -u_sync_vg/_N10041; -u_sync_vg/_N10071; -u_sync_vg/_N10093; -u_sync_vg/_N10113; -u_sync_vg/_N10145; -u_sync_vg/_N16583; -u_sync_vg/_N16585; -u_sync_vg/_N16587; -u_sync_vg/_N16589; -u_sync_vg/_N16674; -u_sync_vg/_N16676; -u_sync_vg/_N16678; -u_sync_vg/_N16680; -u_sync_vg/_N16682; -u_sync_vg/_N96762; -u_sync_vg/_N97008; -u_sync_vg/_N97010; -u_sync_vg/_N97018; -u_sync_vg/_N97211; -u_sync_vg/_N105053; -u_sync_vg/_N105054; -u_sync_vg/_N105066; -u_sync_vg/_N105067; -u_sync_vg/_N105074; -u_sync_vg/_N107935; +u_sync_vg/_N10047; +u_sync_vg/_N10075; +u_sync_vg/_N10077; +u_sync_vg/_N10107; +u_sync_vg/_N10129; +u_sync_vg/_N10149; +u_sync_vg/_N10165; +u_sync_vg/_N16488; +u_sync_vg/_N16490; +u_sync_vg/_N16492; +u_sync_vg/_N16494; +u_sync_vg/_N16613; +u_sync_vg/_N16615; +u_sync_vg/_N16617; +u_sync_vg/_N16619; +u_sync_vg/_N16621; +u_sync_vg/_N97573; +u_sync_vg/_N97773; +u_sync_vg/_N97778; +u_sync_vg/_N97979; +u_sync_vg/_N105600; +u_sync_vg/_N105601; +u_sync_vg/_N105613; +u_sync_vg/_N105614; +u_sync_vg/_N105622; +u_sync_vg/_N105624; +u_sync_vg/_N108767; u_sync_vg/de_re0; u_sync_vg/de_re1; u_sync_vg/de_re2; @@ -299820,26 +299918,26 @@ u_sync_vg/vs_out1; u_sync_vg/vs_out2; u_sys_pll/u_pll_e3/ntCLKFB; u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207; -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16324; -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16326; -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16328; -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16330; -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16332; -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16334; -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16336; -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16341; -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16343; -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16345; -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16347; -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16349; -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16351; -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16353; -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N108007; -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N108010; -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N108011; -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N108384; +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16234; +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16236; +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16238; +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16240; +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16242; +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16244; +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16246; +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16251; +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16253; +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16255; +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16257; +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16259; +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16261; +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16263; +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N108841; +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N109268; +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N109269; u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/rempty; u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wfull; +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr[11]_cpy; u_zoom_image/N198; u_zoom_image/N232; u_zoom_image/N234; @@ -299854,20 +299952,19 @@ u_zoom_image/N850; u_zoom_image/N858; u_zoom_image/N891; u_zoom_image/N919; +u_zoom_image/_N23; u_zoom_image/_N25; u_zoom_image/_N28; u_zoom_image/_N43; -u_zoom_image/_N10185; -u_zoom_image/_N10193; -u_zoom_image/_N10201; +u_zoom_image/_N10205; u_zoom_image/_N10213; -u_zoom_image/_N10250; -u_zoom_image/_N10267; -u_zoom_image/_N10283; -u_zoom_image/_N10299; -u_zoom_image/_N10307; -u_zoom_image/_N12965; -u_zoom_image/_N12966; +u_zoom_image/_N10221; +u_zoom_image/_N10233; +u_zoom_image/_N10270; +u_zoom_image/_N10287; +u_zoom_image/_N10303; +u_zoom_image/_N10319; +u_zoom_image/_N10327; u_zoom_image/_N12967; u_zoom_image/_N12968; u_zoom_image/_N12969; @@ -300080,116 +300177,118 @@ u_zoom_image/_N13175; u_zoom_image/_N13176; u_zoom_image/_N13177; u_zoom_image/_N13178; -u_zoom_image/_N13739; +u_zoom_image/_N13179; +u_zoom_image/_N13180; +u_zoom_image/_N13708; +u_zoom_image/_N13710; +u_zoom_image/_N13712; +u_zoom_image/_N13714; +u_zoom_image/_N13719; +u_zoom_image/_N13721; +u_zoom_image/_N13723; +u_zoom_image/_N13725; +u_zoom_image/_N13730; +u_zoom_image/_N13732; +u_zoom_image/_N13734; +u_zoom_image/_N13736; u_zoom_image/_N13741; u_zoom_image/_N13743; u_zoom_image/_N13745; -u_zoom_image/_N13750; +u_zoom_image/_N13747; u_zoom_image/_N13752; u_zoom_image/_N13754; u_zoom_image/_N13756; -u_zoom_image/_N13761; +u_zoom_image/_N13758; u_zoom_image/_N13763; u_zoom_image/_N13765; u_zoom_image/_N13767; -u_zoom_image/_N13772; +u_zoom_image/_N13769; u_zoom_image/_N13774; u_zoom_image/_N13776; u_zoom_image/_N13778; -u_zoom_image/_N13783; -u_zoom_image/_N13785; -u_zoom_image/_N13787; -u_zoom_image/_N13789; -u_zoom_image/_N13794; -u_zoom_image/_N13796; -u_zoom_image/_N13798; -u_zoom_image/_N13800; -u_zoom_image/_N14629; -u_zoom_image/_N14631; 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udp_osd_inst/char_osd_inst/char_buf_reader_inst/N711; @@ -300265,7 +300364,7 @@ udp_osd_inst/char_osd_inst/char_buf_reader_inst/N714; udp_osd_inst/char_osd_inst/char_buf_reader_inst/N784; udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786; udp_osd_inst/char_osd_inst/char_buf_reader_inst/N832; -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N839; +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N842; udp_osd_inst/char_osd_inst/char_buf_reader_inst/N843; udp_osd_inst/char_osd_inst/char_buf_reader_inst/N848; udp_osd_inst/char_osd_inst/char_buf_reader_inst/N858; @@ -300273,70 +300372,73 @@ udp_osd_inst/char_osd_inst/char_buf_reader_inst/N861; udp_osd_inst/char_osd_inst/char_buf_reader_inst/N862; udp_osd_inst/char_osd_inst/char_buf_reader_inst/N873; udp_osd_inst/char_osd_inst/char_buf_reader_inst/N883; +udp_osd_inst/char_osd_inst/char_buf_reader_inst/N907[6]_cpy; udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N0; udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N2; 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udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N18389; +udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N18392; +udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N18403; udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N18404; udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N18405; -udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N30325; -udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N30374; -udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N81460; -udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N82884; -udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N82900; -udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N96372; -udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N96517; -udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N96518; -udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N96555; -udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N96929; -udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N97090; -udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N97174; 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-udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N107115; -udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N107125; -udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N107126; -udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N107175; -udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N107176; +udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N10417; +udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N10425; +udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N16745; +udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N16747; +udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N16750; +udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N16752; +udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N16754; +udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N16756; +udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N16758; +udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N100778; +udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N107938; +udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N107948; +udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N107949; +udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N107997; +udp_osd_inst/char_osd_inst/pixels_shifter_inst/_N107998; udp_osd_inst/char_osd_inst/pixels_shifter_inst/s_ready_d; udp_osd_inst/char_osd_inst/row_pixels_ready; udp_osd_inst/char_osd_inst/row_pixels_valid; udp_osd_inst/eth_udp_inst/N72; udp_osd_inst/eth_udp_inst/N72_cpy; -udp_osd_inst/eth_udp_inst/_N84201; -udp_osd_inst/eth_udp_inst/_N95844; -udp_osd_inst/eth_udp_inst/_N95913; -udp_osd_inst/eth_udp_inst/_N95922; -udp_osd_inst/eth_udp_inst/_N95923; -udp_osd_inst/eth_udp_inst/_N95925; -udp_osd_inst/eth_udp_inst/_N95955; -udp_osd_inst/eth_udp_inst/_N95958; -udp_osd_inst/eth_udp_inst/_N96003; -udp_osd_inst/eth_udp_inst/_N96007; -udp_osd_inst/eth_udp_inst/_N96072; -udp_osd_inst/eth_udp_inst/_N96085; -udp_osd_inst/eth_udp_inst/_N96096; -udp_osd_inst/eth_udp_inst/_N96358; -udp_osd_inst/eth_udp_inst/_N96385; -udp_osd_inst/eth_udp_inst/_N96556; -udp_osd_inst/eth_udp_inst/_N96693; -udp_osd_inst/eth_udp_inst/_N96774; -udp_osd_inst/eth_udp_inst/_N96775; -udp_osd_inst/eth_udp_inst/_N96776; -udp_osd_inst/eth_udp_inst/_N96780; -udp_osd_inst/eth_udp_inst/_N97006; -udp_osd_inst/eth_udp_inst/_N97022; -udp_osd_inst/eth_udp_inst/_N97473; -udp_osd_inst/eth_udp_inst/_N98508; -udp_osd_inst/eth_udp_inst/_N104315; -udp_osd_inst/eth_udp_inst/_N106910; -udp_osd_inst/eth_udp_inst/_N106911; -udp_osd_inst/eth_udp_inst/_N106920; -udp_osd_inst/eth_udp_inst/_N107965; -udp_osd_inst/eth_udp_inst/_N108056; +udp_osd_inst/eth_udp_inst/_N82337; +udp_osd_inst/eth_udp_inst/_N82491; +udp_osd_inst/eth_udp_inst/_N96653; +udp_osd_inst/eth_udp_inst/_N96654; +udp_osd_inst/eth_udp_inst/_N96657; +udp_osd_inst/eth_udp_inst/_N96703; +udp_osd_inst/eth_udp_inst/_N96734; +udp_osd_inst/eth_udp_inst/_N96787; +udp_osd_inst/eth_udp_inst/_N97121; +udp_osd_inst/eth_udp_inst/_N97122; +udp_osd_inst/eth_udp_inst/_N97125; +udp_osd_inst/eth_udp_inst/_N97265; +udp_osd_inst/eth_udp_inst/_N97327; +udp_osd_inst/eth_udp_inst/_N97338; +udp_osd_inst/eth_udp_inst/_N97341; +udp_osd_inst/eth_udp_inst/_N97535; +udp_osd_inst/eth_udp_inst/_N97539; +udp_osd_inst/eth_udp_inst/_N97540; +udp_osd_inst/eth_udp_inst/_N97542; +udp_osd_inst/eth_udp_inst/_N97554; +udp_osd_inst/eth_udp_inst/_N97887; +udp_osd_inst/eth_udp_inst/_N98258; +udp_osd_inst/eth_udp_inst/_N100572; +udp_osd_inst/eth_udp_inst/_N105154; +udp_osd_inst/eth_udp_inst/_N107734; +udp_osd_inst/eth_udp_inst/_N107735; +udp_osd_inst/eth_udp_inst/_N107744; +udp_osd_inst/eth_udp_inst/_N108899; udp_osd_inst/eth_udp_inst/arp_gmii_tx_en; udp_osd_inst/eth_udp_inst/arp_rx_done; udp_osd_inst/eth_udp_inst/arp_rx_type; @@ -300405,18 +300504,18 @@ udp_osd_inst/eth_udp_inst/arp_tx_en; udp_osd_inst/eth_udp_inst/gmii_rxd_valid; udp_osd_inst/eth_udp_inst/gmii_txd_valid; udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167; -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N14259; -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N14261; -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N14263; -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N14265; -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N14267; -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N15113; -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N15115; -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N15117; -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N15119; -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N15121; -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N108365; -udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N108366; +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N15142; +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N15144; +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N15146; +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N15148; +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N15150; +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N15155; +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N15157; +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N15159; +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N15161; +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N15163; +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N109266; +udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N109267; udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rempty; udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wfull; udp_osd_inst/eth_udp_inst/icmp_gmii_tx_en; @@ -300424,10 +300523,10 @@ udp_osd_inst/eth_udp_inst/icmp_rec_en; udp_osd_inst/eth_udp_inst/icmp_tx_start_en; udp_osd_inst/eth_udp_inst/rec_en; udp_osd_inst/eth_udp_inst/tx_req; -udp_osd_inst/eth_udp_inst/u_arp/_N96069; -udp_osd_inst/eth_udp_inst/u_arp/_N96846; -udp_osd_inst/eth_udp_inst/u_arp/_N97055; -udp_osd_inst/eth_udp_inst/u_arp/_N97057; +udp_osd_inst/eth_udp_inst/u_arp/_N96855; +udp_osd_inst/eth_udp_inst/u_arp/_N97621; +udp_osd_inst/eth_udp_inst/u_arp/_N97817; +udp_osd_inst/eth_udp_inst/u_arp/_N97819; udp_osd_inst/eth_udp_inst/u_arp/crc_en; udp_osd_inst/eth_udp_inst/u_arp/tx_done; udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N52; @@ -300443,7 +300542,6 @@ udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N406; udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N419; udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N422; udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_cpy; udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N559; udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N563; udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N639; @@ -300453,55 +300551,57 @@ udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N834; udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N847; udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N866; udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N1057; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N4998; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N5481; udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N18413; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N22378; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N23306; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N23312; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N83294; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N96226; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N96803; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N97436; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N97485; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107311; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107315; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107316; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107326; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107330; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107334; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107338; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107342; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107346; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107350; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107358; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107371; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107373; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107375; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107382; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107386; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107390; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107394; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107398; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107402; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107404; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107409; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107416; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107420; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107424; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107428; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107432; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107436; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107438; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107443; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107445; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107453; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107457; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107462; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107475; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107476; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N107477; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108081; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108082; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N24272; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N25486; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N25492; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N84898; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N97222; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N97717; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N98228; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N98265; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108141; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108144; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108145; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108155; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108159; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108163; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108167; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108171; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108175; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108179; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108187; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108200; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108202; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108204; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108211; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108215; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108219; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108223; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108227; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108231; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108233; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108238; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108245; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108249; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108253; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108257; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108261; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108265; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108267; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108272; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108274; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108282; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108286; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108291; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108304; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108305; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108306; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108892; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108893; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108916; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108917; udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/error_en; udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/skip_en; udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_inv; @@ -300519,106 +300619,106 @@ udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N781; udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N817; udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N832; udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N932; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N13921; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N13923; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N19981; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N19983; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20887; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20888; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20889; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20890; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20891; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20892; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20893; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20935; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20936; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20937; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20938; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20939; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20940; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20941; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20942; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20943; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20944; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20945; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20946; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20947; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20948; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20949; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20950; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20990; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20998; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20999; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N21000; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N21001; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N21002; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N21003; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N21004; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N21005; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N21014; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N21023; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N21024; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N21025; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N21026; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N21027; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N21028; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N21029; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N21038; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N38191; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N38289; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N38293; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N95832; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N95890; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N96002; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N96575; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N96700; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N96749; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N96807; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N103144_2; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N103145_2; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N103184_4; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N103184_7; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N103184_9; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N103189_2; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N103189_7; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N103189_10; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N107660; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N107726; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N107730; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N107734; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N107738; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N107742; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N107746; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N107750; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N107761; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N107765; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N107769; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N107773; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N107777; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N107781; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N107785; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N107789; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N107792; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N107793; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N107797; -udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N107854; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N13857; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N13859; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N19886; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N19888; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20645; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20646; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20647; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20648; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20649; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20650; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20651; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20693; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20694; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20695; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20696; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20697; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20698; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20699; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20700; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20701; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20702; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20703; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20704; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20705; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20706; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20707; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20708; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20748; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20756; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20757; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20758; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20759; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20760; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20761; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20762; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20763; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20772; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20781; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20782; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20783; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20784; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20785; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20786; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20787; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N20796; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N35876; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N35967; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N35971; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N96621; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N96652; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N97102; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N97318; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N97521; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N97524; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N97789; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N103974_2; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N103975_2; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N104012_4; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N104012_7; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N104012_9; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N104017_2; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N104017_7; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N104017_10; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N108492; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N108558; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N108562; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N108566; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N108570; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N108574; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N108578; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N108582; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N108593; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N108597; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N108601; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N108605; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N108609; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N108613; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N108617; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N108621; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N108624; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N108625; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N108629; +udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/_N108686; udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/skip_en; udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/tx_done_t; udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/tx_en_d0; udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/tx_en_d1; udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/tx_en_d2; udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/N263; -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/_N95977; -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/_N96081; -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/_N96842; -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/_N96843; -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/_N97028; -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/_N97029; -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/_N97058; -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/_N107804; -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/_N107806; -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/_N107809; -udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/_N107811; +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/_N96853; +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/_N96856; +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/_N97617; +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/_N97618; +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/_N97812; +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/_N97813; +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/_N97820; +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/_N108636; +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/_N108638; +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/_N108641; +udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/_N108643; udp_osd_inst/eth_udp_inst/u_eth_ctrl/arp_rx_flag; udp_osd_inst/eth_udp_inst/u_eth_ctrl/icmp_tx_req_d0; udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gtp_outbuft1/ntO; @@ -300639,24 +300739,24 @@ udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_tx_data[2].gtp_outbuft1/ntT; udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_tx_data[3].gtp_outbuft1/ntO; udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_tx_data[3].gtp_outbuft1/ntT; udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/u_rgmii_rx_ctl_ibuf/ntD; -udp_osd_inst/eth_udp_inst/u_icmp/_N96067; -udp_osd_inst/eth_udp_inst/u_icmp/_N97048; -udp_osd_inst/eth_udp_inst/u_icmp/_N97050; +udp_osd_inst/eth_udp_inst/u_icmp/_N96861; +udp_osd_inst/eth_udp_inst/u_icmp/_N97827; +udp_osd_inst/eth_udp_inst/u_icmp/_N97829; udp_osd_inst/eth_udp_inst/u_icmp/crc_en; udp_osd_inst/eth_udp_inst/u_icmp/tx_done; udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/N263; -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N96065; -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N96068; -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N96836; -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N96837; -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N96840; -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N97043; -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N97044; -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N97051; -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N107881; -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N107883; -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N107886; -udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N107888; +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N96859; +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N96862; +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N97627; +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N97628; +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N97631; +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N97822; +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N97823; +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N97830; +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N108713; +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N108715; +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N108718; +udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/_N108720; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N82; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N100; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N129; @@ -300664,6 +300764,7 @@ udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N183; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N195; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N361; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N397; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N421; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N456; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N511; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N516; @@ -300695,36 +300796,36 @@ udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1127; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1170; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1213; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1261; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1265; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1269; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1294; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1304; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1309; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1326; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N5391; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N5466; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N5329; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N5465; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N10697; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14324; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14326; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14328; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14330; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14332; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14334; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14336; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14338; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14340; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14342; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14344; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14346; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14348; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14350; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14352; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N13799; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N13801; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N13803; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N13805; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N13807; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N13809; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N13811; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14329; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14331; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14333; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14335; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14337; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14339; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14341; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14343; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14345; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14347; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14349; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14351; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14353; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14355; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14357; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14359; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14361; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14363; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14365; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14367; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14369; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14371; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14373; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14375; @@ -300733,65 +300834,62 @@ udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14379; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14381; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14383; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14385; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N17056; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N17058; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N17060; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N17062; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N17064; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N17066; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N17068; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14387; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14389; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14391; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14393; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14395; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14397; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N14399; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N18460; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N18470; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N18475; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N18479; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N22164; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N22175; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N22178; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N22180; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N29955; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N81758; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N81987; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N95975; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N96999; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N100419; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107503; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107507; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107511; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107515; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107518; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107522; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107540; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107549; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107553; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107557; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107561; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107565; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107569; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107572; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107576; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107581; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107586; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107590; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107594; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107598; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107602; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107604; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107606; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107609; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107614; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107618; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107622; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107626; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107629; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107632; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107635; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107647; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107652; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N107657; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108059; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108064; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108067; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108068; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N22650; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N22664; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N22666; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N29901; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N84087; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N84941; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N96834; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N97775; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N103649_2; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108335; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108339; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108343; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108347; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108350; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108354; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108360; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108372; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108381; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108385; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108389; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108393; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108397; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108401; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108404; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108408; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108413; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108418; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108422; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108426; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108430; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108434; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108436; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108438; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108441; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108446; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108450; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108454; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108458; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108461; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108464; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108467; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108479; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108484; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108489; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108894; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108902; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/_N108903; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/error_en; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/skip_en; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3; @@ -300826,50 +300924,76 @@ udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1731; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N2622; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N2624; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3084; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N10425; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N10498; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15297; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15299; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N10439; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N10512; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15301; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15303; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15305; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15307; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15309; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15311; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15313; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15315; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15317; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N15319; 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+udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16782; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16784; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16786; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16788; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16790; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16795; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16797; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16799; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16801; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16803; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16805; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16807; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16812; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16814; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16816; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16818; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16820; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16822; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16824; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16826; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16828; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16833; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16835; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16837; @@ -300880,71 +301004,45 @@ udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16845; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16847; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16849; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16851; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16856; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16858; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16860; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16862; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16864; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16853; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16855; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16857; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16859; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16861; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16866; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16868; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16873; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16875; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16877; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16879; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16881; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16883; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16885; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16887; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16889; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16870; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16872; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16874; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16876; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16878; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16880; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16884; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16886; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16888; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16890; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16892; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16894; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16896; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16898; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16900; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16902; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16904; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16906; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16908; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16910; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16912; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16914; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16916; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16918; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16920; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16922; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16927; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16929; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16931; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16933; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16935; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16937; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16939; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16941; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16945; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16947; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16949; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16951; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16953; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16955; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16957; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16959; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16964; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16966; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16968; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16970; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16972; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16974; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16976; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16978; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16980; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16924; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16926; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N16928; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N18495; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N25971; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N25975; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N25976; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N26001; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N26002; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N26004; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N26005; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N26006; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N25935; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N25939; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N25940; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N25965; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N25966; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N25968; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N25969; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N25970; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N26327; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N26342; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N26389; @@ -300988,40 +301086,44 @@ udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N26744; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N26745; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N26746; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N26747; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N84470; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N95801; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N96019; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N96367; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N96573; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N96731; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N102344_2; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N102547_2; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N102854_2; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N106906; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N106909; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N107683; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N107685; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N107696; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N107698; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N107862; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N108072; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N108075; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N108076; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N108095; -udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N108106; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N85270; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N96582; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N97305; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N97455; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N97509; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N97586; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N97693; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N103457_2; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N103555_2; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N103556_2; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N107730; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N107733; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N108515; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N108517; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N108528; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N108530; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N108694; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N108907; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N108910; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N108911; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N108930; +udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N108941; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/skip_en; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/start_en_d0; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/start_en_d1; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/start_en_d2; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/trig_tx_en; udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_done_t; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N72; udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N90; udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N119; udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N175; udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N323; udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N374; udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N376; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N431; udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N432; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N433; udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N434; udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N460; udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N580; @@ -301039,59 +301141,60 @@ udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839; udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N859; udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N878; udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N889; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N10578; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N16556; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N16558; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N16560; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N16562; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N16564; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N16566; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N16568; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N10592; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N16102; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N16104; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N16106; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N16108; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N16110; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N16112; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N16114; udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N18510; udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N26584; udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N26589; udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N26601; udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N26602; udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N30726; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N81655; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N84440; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N84443; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N84536; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N96777; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N96779; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104125; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104141; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104145; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104149; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104153; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104157; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104172; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104176; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104180; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104184; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104188; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104192; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104195; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104199; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104204; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104209; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104213; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104217; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104221; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104225; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104227; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104229; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104232; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104237; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104241; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104245; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104249; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104252; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104255; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104267; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104270; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N107971; -udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N107972; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N85237; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N85240; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N85340; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N96655; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N97357; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N97541; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N97553; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104964; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104980; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104984; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104988; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104992; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N104996; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105011; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105015; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105019; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105023; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105027; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105031; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105034; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105038; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105044; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105047; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105052; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105056; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105060; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105064; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105066; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105068; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105071; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105076; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105080; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105084; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105088; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105091; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105094; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105106; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N105109; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N108801; +udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/_N108802; udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/error_en; udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/skip_en; udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N120; @@ -301103,21 +301206,21 @@ udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N282; udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N296; udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N321; udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N327; -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N14103; -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N14105; -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N14107; -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N14109; -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N14111; -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N14113; -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N14115; -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N15501; -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N15503; -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N97495; -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N106928; -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N106933; -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N106935; -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N106939; -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N108115; +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N13922; +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N13924; +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N13926; +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N13928; +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N13930; +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N13932; +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N13934; +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N17122; +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N17124; +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N98274; +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N107752; +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N107757; +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N107759; +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N107763; +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N108952; udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/change_to_read; udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/fifo_empty; udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/fifo_rd_data_en; @@ -301127,6 +301230,7 @@ udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/fifo_wr_en; udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/fifo_wr_en_cpy; udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/pkt_rd_done; udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/pkt_wr_done; +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/recv_m_data_tlast; udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_done_cdc/in_req; udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_done_cdc/in_req_sync0; udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_done_cdc/in_req_sync1; @@ -301134,25 +301238,24 @@ udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_done_cdc/out_ack; udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_done_cdc/out_ack_sync0; udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_done_cdc/out_ack_sync1; udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167; -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N14997; -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N14999; -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N15001; -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N15003; -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N15005; -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N17160; -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N17162; -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N17164; -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N17166; -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N17168; -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N108382; -udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N108383; +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N13665; +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N13667; +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N13669; +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N13671; +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N13673; +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N17080; +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N17082; +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N17084; +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N17086; +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N17088; +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N109270; +udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N109271; udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wfull; udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_start_i_ff; udp_osd_inst/eth_udp_inst/udp_rx_pkt_done; udp_osd_inst/m_pixel_data; udp_osd_inst/m_pixel_valid; udp_osd_inst/ram_wen; -udp_osd_inst/udp_rx_data_tlast; udp_osd_inst/udp_rx_data_tready; udp_osd_inst/udp_rx_data_tvalid; udp_rx_pkt_en; @@ -301185,19 +301288,19 @@ udp_wr_mem_inst/N524; udp_wr_mem_inst/N723; udp_wr_mem_inst/N727; udp_wr_mem_inst/N730; -udp_wr_mem_inst/_N15067; -udp_wr_mem_inst/_N15069; -udp_wr_mem_inst/_N15071; -udp_wr_mem_inst/_N97138; -udp_wr_mem_inst/_N97274; -udp_wr_mem_inst/_N97275; -udp_wr_mem_inst/_N97276; -udp_wr_mem_inst/_N97277; -udp_wr_mem_inst/_N104284; -udp_wr_mem_inst/_N104290; -udp_wr_mem_inst/_N104294; -udp_wr_mem_inst/_N104298; -udp_wr_mem_inst/_N104323; +udp_wr_mem_inst/_N13814; +udp_wr_mem_inst/_N13816; +udp_wr_mem_inst/_N13818; +udp_wr_mem_inst/_N97909; +udp_wr_mem_inst/_N98046; +udp_wr_mem_inst/_N98047; +udp_wr_mem_inst/_N98048; +udp_wr_mem_inst/_N98049; +udp_wr_mem_inst/_N105123; +udp_wr_mem_inst/_N105129; +udp_wr_mem_inst/_N105133; +udp_wr_mem_inst/_N105137; +udp_wr_mem_inst/_N105162; vs_in; vs_in_ibuf/ntD; vs_osd; @@ -301232,34 +301335,32 @@ N123_0.co [4]; N123_0.co [6]; N123_0.co [8]; N123_0.co [10]; -N332[1]; -N332[2]; -N332[3]; -N332[4]; -N332[5]; -N332[6]; -N332[7]; -N332[8]; -N332[9]; -N332[10]; -N332[11]; -N334[1]; -N334[2]; -N334[3]; -N334[4]; -N334[5]; -N334[6]; -N334[7]; -N334[8]; -N334[9]; -N334[10]; -N334[11]; +N333[1]; +N333[2]; +N333[3]; +N333[4]; +N333[5]; +N333[6]; +N333[7]; +N333[8]; +N333[9]; +N333[10]; +N333[11]; +N335[1]; +N335[2]; +N335[3]; +N335[4]; +N335[5]; +N335[6]; +N335[7]; +N335[8]; +N335[9]; +N335[10]; +N335[11]; adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N132.co [2]; adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N132.co [4]; adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N132.co [6]; -adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N199 [0]; adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N199 [1]; -adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N201 [2]; adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N204 [0]; adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N204 [1]; adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N204 [2]; @@ -301367,6 +301468,7 @@ adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/nb0 [4]; adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/nb0 [5]; adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/nb0 [6]; adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/nb0 [7]; +adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/nb1 [7]; adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/N7.co [2]; adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/N15.co [2]; adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/N23.co [2]; @@ -305326,8 +305428,6 @@ ms72xx_ctl/ms7200_ctl/state_n [1]; ms72xx_ctl/ms7200_ctl/state_n [2]; ms72xx_ctl/ms7200_ctl/state_n [4]; ms72xx_ctl/ms7200_ctl/state_n [5]; -ms72xx_ctl/ms7210_ctl/N62 [3]; -ms72xx_ctl/ms7210_ctl/N62 [4]; ms72xx_ctl/ms7210_ctl/N612 [0]; ms72xx_ctl/ms7210_ctl/N612 [1]; ms72xx_ctl/ms7210_ctl/cmd_iic [0]; @@ -306977,6 +307077,13 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [0]; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [1]; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [2]; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [3]; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N29 [1]; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N29 [2]; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N29 [3]; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N29 [4]; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N29 [5]; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N29 [6]; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N29 [7]; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N262 [13]; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt [0]; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt [1]; @@ -307409,8 +307516,12 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddr u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_en_slipped [3]; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N22 [2]; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N81 [1]; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N389_8.co [2]; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N389_8.co [4]; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N81 [2]; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N81 [3]; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N81 [4]; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N81 [5]; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N389_8.co [1]; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N389_8.co [3]; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N567 [6]; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt [0]; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt [1]; @@ -308202,7 +308313,6 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddr u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_gate_ctrl [1]; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_gate_ctrl [2]; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_gate_ctrl [3]; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/N328 [2]; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_next_state [0]; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_next_state [1]; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_next_state [2]; @@ -308856,7 +308966,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wclk_ca [0]; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wclk_ca [1]; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wclk_ca [2]; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wclk_ca [3]; -u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_flag_tmp [1]; +u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_flag_tmp [0]; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_flag_tmp [2]; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_flag_tmp [3]; u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_dqs_resp_tmp [0]; @@ -314337,8 +314447,6 @@ u_ddr_addr_ctr/clk_cnt [16]; u_ddr_addr_ctr/clk_cnt [17]; u_ddr_addr_ctr/clk_cnt [18]; u_ddr_addr_ctr/clk_cnt [19]; -u_ddr_addr_ctr/clk_cnt [20]; -u_ddr_addr_ctr/clk_cnt [21]; u_ddr_addr_ctr/u_rd0_addr_ctr/N157 [2]; u_ddr_addr_ctr/u_rd0_addr_ctr/rd0_sta_reg [0]; u_ddr_addr_ctr/u_rd0_addr_ctr/rd0_sta_reg [1]; @@ -315419,29 +315527,29 @@ u_rotate_image/N17_1.co [4]; u_rotate_image/N17_1.co [6]; u_rotate_image/N17_1.co [8]; u_rotate_image/N17_1.co [10]; -u_rotate_image/N290 [0]; -u_rotate_image/N290 [1]; -u_rotate_image/N290 [2]; -u_rotate_image/N290 [3]; -u_rotate_image/N290 [4]; -u_rotate_image/N290 [5]; -u_rotate_image/N290 [6]; -u_rotate_image/N290 [7]; -u_rotate_image/N290 [8]; -u_rotate_image/N290 [9]; -u_rotate_image/N290 [10]; -u_rotate_image/N301 [0]; -u_rotate_image/N301 [1]; -u_rotate_image/N301 [2]; -u_rotate_image/N301 [3]; -u_rotate_image/N301 [4]; -u_rotate_image/N301 [5]; -u_rotate_image/N301 [6]; -u_rotate_image/N301 [7]; -u_rotate_image/N301 [8]; -u_rotate_image/N301 [9]; -u_rotate_image/N301 [10]; -u_rotate_image/N340 [2]; +u_rotate_image/N338 [0]; +u_rotate_image/N338 [1]; +u_rotate_image/N338 [2]; +u_rotate_image/N338 [3]; +u_rotate_image/N338 [4]; +u_rotate_image/N338 [5]; +u_rotate_image/N338 [6]; +u_rotate_image/N338 [7]; +u_rotate_image/N338 [8]; +u_rotate_image/N338 [9]; +u_rotate_image/N338 [10]; +u_rotate_image/N349 [0]; +u_rotate_image/N349 [1]; +u_rotate_image/N349 [2]; +u_rotate_image/N349 [3]; +u_rotate_image/N349 [4]; +u_rotate_image/N349 [5]; +u_rotate_image/N349 [6]; +u_rotate_image/N349 [7]; +u_rotate_image/N349 [8]; +u_rotate_image/N349 [9]; +u_rotate_image/N349 [10]; +u_rotate_image/N396 [2]; u_rotate_image/centerX [0]; u_rotate_image/centerX [1]; u_rotate_image/centerX [2]; @@ -316031,14 +316139,6 @@ u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [6]; u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [8]; u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [10]; u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [12]; -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/nb6 [5]; -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/nb6 [6]; -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/nb6 [7]; -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/nb6 [8]; -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/nb6 [9]; -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/nb6 [10]; -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/nb6 [11]; -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/nb6 [12]; u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/rbin [15]; u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/rptr [0]; u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/rptr [1]; @@ -316061,7 +316161,6 @@ u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/rrptr [1]; u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/rrptr [2]; u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/rrptr [3]; u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/rrptr [4]; -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/rrptr [5]; u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/rrptr [6]; u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/rrptr [7]; u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/rrptr [8]; @@ -316073,7 +316172,7 @@ u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/rrptr [14]; u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/rrptr [15]; u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/rwptr [1]; u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/rwptr [3]; -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/rwptr [5]; +u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/rwptr [4]; u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/rwptr [6]; u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/rwptr [7]; u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/rwptr [8]; @@ -316135,7 +316234,6 @@ u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr [2]; u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr [3]; u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr [4]; u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr [5]; -u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr [6]; u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr [7]; u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr [8]; u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr [9]; @@ -317310,7 +317408,6 @@ udp_osd_inst/char_osd_inst/char_buf_reader_inst/N900 [9]; udp_osd_inst/char_osd_inst/char_buf_reader_inst/N900 [10]; udp_osd_inst/char_osd_inst/char_buf_reader_inst/N902 [1]; udp_osd_inst/char_osd_inst/char_buf_reader_inst/N902 [2]; -udp_osd_inst/char_osd_inst/char_buf_reader_inst/N907 [2]; udp_osd_inst/char_osd_inst/char_buf_reader_inst/N907 [4]; udp_osd_inst/char_osd_inst/char_buf_reader_inst/N907 [5]; udp_osd_inst/char_osd_inst/char_buf_reader_inst/N907 [6]; @@ -319707,9 +319804,11 @@ udp_wr_mem_inst/N4_1.co [7]; udp_wr_mem_inst/N4_1.co [9]; udp_wr_mem_inst/N4_1.co [11]; udp_wr_mem_inst/N4_1.co [13]; -udp_wr_mem_inst/N30_1.co [1]; -udp_wr_mem_inst/N30_1.co [3]; -udp_wr_mem_inst/N30_1.co [5]; +udp_wr_mem_inst/N30_1.co [2]; +udp_wr_mem_inst/N30_1.co [4]; +udp_wr_mem_inst/N30_1.co [6]; +udp_wr_mem_inst/N784 [1]; +udp_wr_mem_inst/N784 [2]; udp_wr_mem_inst/N790 [2]; udp_wr_mem_inst/N790 [3]; udp_wr_mem_inst/N790 [4]; @@ -323808,6 +323907,49 @@ ntR3906; ntR3907; ntR3908; ntR3909; +ntR3910; +ntR3911; +ntR3912; +ntR3913; +ntR3914; +ntR3915; +ntR3916; +ntR3917; +ntR3918; +ntR3919; +ntR3920; +ntR3921; +ntR3922; +ntR3923; +ntR3924; +ntR3925; +ntR3926; +ntR3927; +ntR3928; +ntR3929; +ntR3930; +ntR3931; +ntR3932; +ntR3933; +ntR3934; +ntR3935; +ntR3936; +ntR3937; +ntR3938; +ntR3939; +ntR3940; +ntR3941; +ntR3942; +ntR3943; +ntR3944; +ntR3945; +ntR3946; +ntR3947; +ntR3948; +ntR3949; +ntR3950; +ntR3951; +ntR3952; Clock clk;1000 diff --git a/project/place_route/multimedia_video_processor_timing_summary_after_hold_fix.txt b/project/place_route/multimedia_video_processor_timing_summary_after_hold_fix.txt index 1c14e55..88fafeb 100644 --- a/project/place_route/multimedia_video_processor_timing_summary_after_hold_fix.txt +++ b/project/place_route/multimedia_video_processor_timing_summary_after_hold_fix.txt @@ -1,21 +1,22 @@ -Design Summary : Some Constraints Violated. +Design Summary : All Constraints Met. Setup Summary(Slow Corner): **************************************************************************************************** TNS Failing TNS Total Launch Clock Capture Clock WNS(ns) TNS(ns) Endpoints Endpoints ---------------------------------------------------------------------------------------------------- - cmos1_pclk cmos1_pclk 5.710 0.000 0 251 - cmos2_pclk cmos2_pclk 4.328 0.000 0 251 - hdmi_in_clk hdmi_in_clk 1.168 0.000 0 311 - eth_rxc eth_rxc 1.145 0.000 0 5907 - clk_50m clk_50m 10.898 0.000 0 9498 - clk_200m clk_200m -0.762 -17.604 44 3769 - clk_25m clk_25m 35.453 0.000 0 30 - clk_10m clk_10m 94.284 0.000 0 1099 - clk_720p60Hz clk_720p60Hz 5.528 0.000 0 4786 - clk_20k clk_20k 49995.068 0.000 0 181 - ddrphy_clkin ddrphy_clkin 0.480 0.000 0 18193 + cmos1_pclk cmos1_pclk 5.348 0.000 0 251 + cmos2_pclk cmos2_pclk 4.387 0.000 0 251 + hdmi_in_clk hdmi_in_clk 1.866 0.000 0 311 + eth_rxc eth_rxc 1.165 0.000 0 5918 + clk_50m clk_50m 10.408 0.000 0 9493 + clk_200m clk_200m 1.141 0.000 0 258 + clk_25m clk_25m 35.531 0.000 0 30 + clk_10m clk_10m 94.646 0.000 0 1092 + clk_1080p60Hz clk_1080p60Hz 1.098 0.000 0 3524 + clk_720p60Hz clk_720p60Hz 6.064 0.000 0 4786 + clk_20k clk_20k 49994.640 0.000 0 177 + ddrphy_clkin ddrphy_clkin 2.548 0.000 0 18286 ioclk0 ioclk0 1.692 0.000 0 24 ioclk1 ioclk1 1.692 0.000 0 72 ==================================================================================================== @@ -25,17 +26,18 @@ Hold Summary(Slow Corner): THS Failing THS Total Launch Clock Capture Clock WHS(ns) THS(ns) Endpoints Endpoints ---------------------------------------------------------------------------------------------------- - cmos1_pclk cmos1_pclk 0.185 0.000 0 251 - cmos2_pclk cmos2_pclk 0.412 0.000 0 251 - hdmi_in_clk hdmi_in_clk 0.187 0.000 0 311 - eth_rxc eth_rxc 0.377 0.000 0 5907 - clk_50m clk_50m 0.176 0.000 0 9498 - clk_200m clk_200m 0.239 0.000 0 3769 - clk_25m clk_25m 0.573 0.000 0 30 - clk_10m clk_10m 0.311 0.000 0 1099 - clk_720p60Hz clk_720p60Hz 0.312 0.000 0 4786 - clk_20k clk_20k 0.356 0.000 0 181 - ddrphy_clkin ddrphy_clkin 0.143 0.000 0 18193 + cmos1_pclk cmos1_pclk 0.171 0.000 0 251 + cmos2_pclk cmos2_pclk 0.406 0.000 0 251 + hdmi_in_clk hdmi_in_clk 0.185 0.000 0 311 + eth_rxc eth_rxc 0.145 0.000 0 5918 + clk_50m clk_50m 0.188 0.000 0 9493 + clk_200m clk_200m 0.311 0.000 0 258 + clk_25m clk_25m 0.549 0.000 0 30 + clk_10m clk_10m 0.286 0.000 0 1092 + clk_1080p60Hz clk_1080p60Hz 0.209 0.000 0 3524 + clk_720p60Hz clk_720p60Hz 0.313 0.000 0 4786 + clk_20k clk_20k 0.356 0.000 0 177 + ddrphy_clkin ddrphy_clkin 0.151 0.000 0 18286 ioclk0 ioclk0 0.450 0.000 0 24 ioclk1 ioclk1 0.450 0.000 0 72 ==================================================================================================== @@ -45,11 +47,12 @@ Recovery Summary(Slow Corner): TNS Failing TNS Total Launch Clock Capture Clock WNS(ns) TNS(ns) Endpoints Endpoints ---------------------------------------------------------------------------------------------------- - clk_50m clk_50m 16.117 0.000 0 192 - clk_200m clk_200m 1.199 0.000 0 175 - clk_10m clk_10m 97.806 0.000 0 1 - clk_720p60Hz clk_720p60Hz 8.661 0.000 0 717 - ddrphy_clkin ddrphy_clkin 5.561 0.000 0 2569 + clk_50m clk_50m 15.838 0.000 0 192 + clk_200m clk_200m 1.238 0.000 0 69 + clk_10m clk_10m 97.807 0.000 0 1 + clk_1080p60Hz clk_1080p60Hz 3.317 0.000 0 106 + clk_720p60Hz clk_720p60Hz 9.028 0.000 0 717 + ddrphy_clkin ddrphy_clkin 5.761 0.000 0 2569 ==================================================================================================== Removal Summary(Slow Corner): @@ -57,11 +60,12 @@ Removal Summary(Slow Corner): THS Failing THS Total Launch Clock Capture Clock WHS(ns) THS(ns) Endpoints Endpoints ---------------------------------------------------------------------------------------------------- - clk_50m clk_50m 0.533 0.000 0 192 - clk_200m clk_200m 0.548 0.000 0 175 - clk_10m clk_10m 1.299 0.000 0 1 - clk_720p60Hz clk_720p60Hz 1.206 0.000 0 717 - ddrphy_clkin ddrphy_clkin 0.751 0.000 0 2569 + clk_50m clk_50m 0.592 0.000 0 192 + clk_200m clk_200m 0.546 0.000 0 69 + clk_10m clk_10m 1.253 0.000 0 1 + clk_1080p60Hz clk_1080p60Hz 1.201 0.000 0 106 + clk_720p60Hz clk_720p60Hz 0.940 0.000 0 717 + ddrphy_clkin ddrphy_clkin 0.616 0.000 0 2569 ==================================================================================================== Minimum Pulse Width Summary(Slow Corner): @@ -76,17 +80,18 @@ Setup Summary(Fast Corner): TNS Failing TNS Total Launch Clock Capture Clock WNS(ns) TNS(ns) Endpoints Endpoints ---------------------------------------------------------------------------------------------------- - cmos1_pclk cmos1_pclk 6.782 0.000 0 251 - cmos2_pclk cmos2_pclk 6.122 0.000 0 251 - hdmi_in_clk hdmi_in_clk 2.649 0.000 0 311 - eth_rxc eth_rxc 3.058 0.000 0 5907 - clk_50m clk_50m 13.447 0.000 0 9498 - clk_200m clk_200m 0.729 0.000 0 3769 - clk_25m clk_25m 36.750 0.000 0 30 - clk_10m clk_10m 95.958 0.000 0 1099 - clk_720p60Hz clk_720p60Hz 7.912 0.000 0 4786 - clk_20k clk_20k 49996.415 0.000 0 181 - ddrphy_clkin ddrphy_clkin 3.338 0.000 0 18193 + cmos1_pclk cmos1_pclk 6.465 0.000 0 251 + cmos2_pclk cmos2_pclk 5.887 0.000 0 251 + hdmi_in_clk hdmi_in_clk 3.174 0.000 0 311 + eth_rxc eth_rxc 3.107 0.000 0 5918 + clk_50m clk_50m 13.002 0.000 0 9493 + clk_200m clk_200m 2.144 0.000 0 258 + clk_25m clk_25m 36.816 0.000 0 30 + clk_10m clk_10m 96.197 0.000 0 1092 + clk_1080p60Hz clk_1080p60Hz 2.501 0.000 0 3524 + clk_720p60Hz clk_720p60Hz 8.248 0.000 0 4786 + clk_20k clk_20k 49996.134 0.000 0 177 + ddrphy_clkin ddrphy_clkin 4.710 0.000 0 18286 ioclk0 ioclk0 1.834 0.000 0 24 ioclk1 ioclk1 1.834 0.000 0 72 ==================================================================================================== @@ -96,17 +101,18 @@ Hold Summary(Fast Corner): THS Failing THS Total Launch Clock Capture Clock WHS(ns) THS(ns) Endpoints Endpoints ---------------------------------------------------------------------------------------------------- - cmos1_pclk cmos1_pclk 0.101 0.000 0 251 + cmos1_pclk cmos1_pclk 0.100 0.000 0 251 cmos2_pclk cmos2_pclk 0.250 0.000 0 251 - hdmi_in_clk hdmi_in_clk 0.101 0.000 0 311 - eth_rxc eth_rxc 0.250 0.000 0 5907 - clk_50m clk_50m 0.135 0.000 0 9498 - clk_200m clk_200m 0.191 0.000 0 3769 - clk_25m clk_25m 0.403 0.000 0 30 - clk_10m clk_10m 0.230 0.000 0 1099 + hdmi_in_clk hdmi_in_clk 0.102 0.000 0 311 + eth_rxc eth_rxc 0.064 0.000 0 5918 + clk_50m clk_50m 0.132 0.000 0 9493 + clk_200m clk_200m 0.239 0.000 0 258 + clk_25m clk_25m 0.387 0.000 0 30 + clk_10m clk_10m 0.231 0.000 0 1092 + clk_1080p60Hz clk_1080p60Hz 0.155 0.000 0 3524 clk_720p60Hz clk_720p60Hz 0.251 0.000 0 4786 - clk_20k clk_20k 0.253 0.000 0 181 - ddrphy_clkin ddrphy_clkin 0.105 0.000 0 18193 + clk_20k clk_20k 0.253 0.000 0 177 + ddrphy_clkin ddrphy_clkin 0.100 0.000 0 18286 ioclk0 ioclk0 0.383 0.000 0 24 ioclk1 ioclk1 0.383 0.000 0 72 ==================================================================================================== @@ -116,11 +122,12 @@ Recovery Summary(Fast Corner): TNS Failing TNS Total Launch Clock Capture Clock WNS(ns) TNS(ns) Endpoints Endpoints ---------------------------------------------------------------------------------------------------- - clk_50m clk_50m 17.156 0.000 0 192 - clk_200m clk_200m 2.227 0.000 0 175 - clk_10m clk_10m 98.368 0.000 0 1 - clk_720p60Hz clk_720p60Hz 9.978 0.000 0 717 - ddrphy_clkin ddrphy_clkin 6.834 0.000 0 2569 + clk_50m clk_50m 17.011 0.000 0 192 + clk_200m clk_200m 2.226 0.000 0 69 + clk_10m clk_10m 98.389 0.000 0 1 + clk_1080p60Hz clk_1080p60Hz 4.325 0.000 0 106 + clk_720p60Hz clk_720p60Hz 10.187 0.000 0 717 + ddrphy_clkin ddrphy_clkin 6.941 0.000 0 2569 ==================================================================================================== Removal Summary(Fast Corner): @@ -128,11 +135,12 @@ Removal Summary(Fast Corner): THS Failing THS Total Launch Clock Capture Clock WHS(ns) THS(ns) Endpoints Endpoints ---------------------------------------------------------------------------------------------------- - clk_50m clk_50m 0.400 0.000 0 192 - clk_200m clk_200m 0.447 0.000 0 175 - clk_10m clk_10m 0.907 0.000 0 1 - clk_720p60Hz clk_720p60Hz 0.824 0.000 0 717 - ddrphy_clkin ddrphy_clkin 0.533 0.000 0 2569 + clk_50m clk_50m 0.439 0.000 0 192 + clk_200m clk_200m 0.445 0.000 0 69 + clk_10m clk_10m 0.866 0.000 0 1 + clk_1080p60Hz clk_1080p60Hz 0.825 0.000 0 106 + clk_720p60Hz clk_720p60Hz 0.687 0.000 0 717 + ddrphy_clkin ddrphy_clkin 0.460 0.000 0 2569 ==================================================================================================== Minimum Pulse Width Summary(Fast Corner): diff --git a/project/place_route/prr.db b/project/place_route/prr.db index a4d5220..27f80da 100644 --- a/project/place_route/prr.db +++ b/project/place_route/prr.db @@ -6499,48 +6499,48 @@ Use of CLMA - 2694 + 2666 6450 42 FF - 8356 + 8349 38700 22 LUT - 8529 + 8468 25800 - 34 + 33 LUT-FF pairs - 3368 + 3365 25800 14 Use of CLMS - 1700 + 1728 4250 - 40 + 41 FF - 5264 + 5269 25500 21 LUT - 5415 + 5482 17000 - 32 + 33 LUT-FF pairs - 2199 + 2194 17000 13 @@ -6583,9 +6583,9 @@ Use of HARD0N1 - 1334 + 1340 6672 - 20 + 21 Use of HSST @@ -6751,9 +6751,9 @@ Use of USCM - 16 + 17 30 - 54 + 57 USCM dataused 0 @@ -6804,8 +6804,8 @@ multimedia_video_processor - 13929 - 13620 + 13927 + 13618 88 23.5 98.5 @@ -6827,7 +6827,7 @@ 0 0 0 - 16 + 17 U_HDMI_PLL 0 @@ -6857,7 +6857,7 @@ adjust_color_wrapper_inst - 1127 + 1128 1096 0 1.5 @@ -6883,7 +6883,7 @@ 0 adjust_color_inst - 1127 + 1128 1018 0 1.5 @@ -6909,7 +6909,7 @@ 0 convert_hsv2rgb_inst - 69 + 70 81 0 1.5 @@ -8558,7 +8558,7 @@ image_filiter_inst2 - 946 + 945 856 0 0 @@ -8584,7 +8584,7 @@ 0 hybrid_filter_inst - 727 + 726 621 0 0 @@ -9287,7 +9287,7 @@ ms72xx_ctl - 333 + 332 236 0 0 @@ -9313,7 +9313,7 @@ 0 iic_dri_rx - 80 + 81 61 0 0 @@ -9340,7 +9340,7 @@ iic_dri_tx - 65 + 64 56 0 0 @@ -9394,7 +9394,7 @@ ms7210_ctl - 88 + 87 62 0 0 @@ -9422,7 +9422,7 @@ param_manager_inst - 666 + 672 354 0 0 @@ -9529,7 +9529,7 @@ param_filiter1_mode - 67 + 69 34 0 0 @@ -9637,7 +9637,7 @@ param_modify_H - 51 + 52 22 0 0 @@ -9664,7 +9664,7 @@ param_modify_S - 28 + 30 9 0 0 @@ -9691,7 +9691,7 @@ param_modify_V - 28 + 29 9 0 0 @@ -9718,7 +9718,7 @@ param_offsetX - 56 + 54 25 0 0 @@ -9772,7 +9772,7 @@ param_osd_char_height - 57 + 55 24 0 0 @@ -9799,7 +9799,7 @@ param_osd_char_width - 32 + 33 11 0 0 @@ -9880,7 +9880,7 @@ param_rotate - 47 + 49 21 0 0 @@ -9907,7 +9907,7 @@ param_rotate_A - 33 + 34 10 0 0 @@ -9962,7 +9962,7 @@ u_axi_ddr_top - 5792 + 5801 6000 88 0 @@ -9988,7 +9988,7 @@ 2 I_ipsxb_ddr_top - 4006 + 4015 4123 88 0 @@ -10041,7 +10041,7 @@ u_ddrphy_top - 2351 + 2363 2360 0 0 @@ -10310,7 +10310,7 @@ ddrphy_info - 98 + 101 60 0 0 @@ -10337,7 +10337,7 @@ ddrphy_reset_ctrl - 77 + 86 60 0 0 @@ -10363,7 +10363,7 @@ 0 ddrphy_pll_lock_debounce - 44 + 45 22 0 0 @@ -10471,7 +10471,7 @@ 0 i_dqs_group[0].u_ddrphy_data_slice - 478 + 479 308 0 0 @@ -10578,7 +10578,7 @@ data_slice_wrlvl - 108 + 106 76 0 0 @@ -10632,7 +10632,7 @@ dqsi_rdel_cal - 169 + 172 84 0 0 @@ -10687,7 +10687,7 @@ i_dqs_group[1].u_ddrphy_data_slice - 332 + 336 262 0 0 @@ -10794,7 +10794,7 @@ data_slice_wrlvl - 102 + 105 68 0 0 @@ -10821,7 +10821,7 @@ dqs_rddata_align - 44 + 45 74 0 0 @@ -10903,7 +10903,7 @@ i_dqs_group[2].u_ddrphy_data_slice - 338 + 334 262 0 0 @@ -10929,7 +10929,7 @@ 0 data_slice_dqs_gate_cal - 81 + 82 61 0 0 @@ -10982,7 +10982,7 @@ gatecal - 47 + 48 35 0 0 @@ -11010,7 +11010,7 @@ data_slice_wrlvl - 107 + 106 68 0 0 @@ -11064,7 +11064,7 @@ dqsi_rdel_cal - 101 + 97 59 0 0 @@ -11119,7 +11119,7 @@ i_dqs_group[3].u_ddrphy_data_slice - 341 + 340 262 0 0 @@ -11226,7 +11226,7 @@ data_slice_wrlvl - 103 + 102 68 0 0 @@ -11445,7 +11445,7 @@ u_ipsxb_ddrc_top - 1654 + 1651 1761 88 0 @@ -11525,7 +11525,7 @@ mcdq_dcd_top - 179 + 178 158 0 0 @@ -11577,7 +11577,7 @@ 0 mcdq_dcd_rowaddr - 17 + 12 8 0 0 @@ -11605,7 +11605,7 @@ mcdq_dcd_sm - 51 + 50 78 0 0 @@ -11633,7 +11633,7 @@ mcdq_dcp_top - 854 + 852 626 82 0 @@ -11659,7 +11659,7 @@ 0 mcdq_dcp_back_ctrl - 545 + 543 406 0 0 @@ -12117,7 +12117,7 @@ TRDA2ACT_LOOP[0].trda2act_timing - 8 + 7 5 0 0 @@ -12549,7 +12549,7 @@ mcdq_timing_rd_pass - 11 + 10 7 0 0 @@ -12711,7 +12711,7 @@ timing_prea_pass - 15 + 16 12 0 0 @@ -12765,7 +12765,7 @@ timing_wr_pass - 9 + 8 5 0 0 @@ -13306,7 +13306,7 @@ u_user_cmd_fifo - 41 + 42 110 0 0 @@ -14957,8 +14957,8 @@ u_ddr_addr_ctr - 280 - 434 + 277 + 432 0 0 0.5 @@ -15443,7 +15443,7 @@ u_ov5640 - 453 + 455 504 0 0 @@ -15577,7 +15577,7 @@ coms2_reg_config - 61 + 63 36 0 0 @@ -15603,7 +15603,7 @@ 1 u1 - 29 + 31 9 0 0 @@ -16442,7 +16442,7 @@ u_zoom_hdmi_fifo - 166 + 148 139 0 0 @@ -16468,7 +16468,7 @@ 0 U_ipml_fifo_zoom_hdmi_fifo - 166 + 148 139 0 0 @@ -16494,7 +16494,7 @@ 0 U_ipml_fifo_ctrl - 165 + 147 138 0 0 @@ -17522,7 +17522,7 @@ udp_osd_inst - 2209 + 2212 1831 0 0 @@ -17601,7 +17601,7 @@ 0 char_buf_reader_inst - 175 + 176 129 0 0 @@ -17628,7 +17628,7 @@ char_pic_rom_inst - 42 + 41 47 0 0 @@ -17818,7 +17818,7 @@ eth_udp_inst - 1818 + 1821 1541 0 0 @@ -17952,7 +17952,7 @@ u_arp - 423 + 422 424 0 0 @@ -17978,7 +17978,7 @@ 0 u_arp_rx - 215 + 214 278 0 0 @@ -18114,7 +18114,7 @@ u_icmp - 927 + 929 628 0 0 @@ -18194,7 +18194,7 @@ u_icmp_tx - 584 + 586 312 0 0 @@ -18222,7 +18222,7 @@ u_udp - 161 + 163 185 0 0 @@ -18248,7 +18248,7 @@ 0 u_udp_rx - 161 + 163 185 0 0 @@ -18440,7 +18440,7 @@ udp_wr_mem_inst - 105 + 106 190 0 0 @@ -18478,10 +18478,10 @@ RAM(GB) - 0h:2m:39s - 0h:4m:9s - 0h:2m:46s - 1,902 + 0h:2m:59s + 0h:4m:43s + 0h:3m:5s + 1,901 WINDOWS 10 x86_64 Intel(R) Core(TM) i7-9750H CPU @ 2.60GHz 32 @@ -18634,16 +18634,13 @@ Process macros using "Greedy". - Design net nt_eth_rxc is routed by general path. - - - Route-2036: The clock path from eth_rxc_ibuf/opit_1:OUT to udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/clk_dll/gopdll:CLK is routed by SRB. + Place-2001: The file D:/Project/FPGA_Project/Pango/multimedia_video_processor/project/kkk.rcf can't be opened. - Design net nt_cmos2_pclk is routed by general path. + Design net nt_eth_rxc is routed by general path. - Route-2036: The clock path from cmos2_pclk_ibuf/opit_1:OUT to clkbufg_6/gopclkbufg:CLK is routed by SRB. + Route-2036: The clock path from eth_rxc_ibuf/opit_1:OUT to udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/clk_dll/gopdll:CLK is routed by SRB. Design net u_ov5640/coms2_reg_config/clk_20k_regdiv is routed by general path. @@ -18657,6 +18654,18 @@ Route-2036: The clock path from u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv:Q to u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg:CLK is routed by SRB. + + Design net nt_cmos2_pclk is routed by general path. + + + Route-2036: The clock path from cmos2_pclk_ibuf/opit_1:OUT to clkbufg_7/gopclkbufg:CLK is routed by SRB. + + + Timing-4105: The worst slack of endpoint udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][6]/opit_0/D of clock eth_rxc is 75ps(fast corner), but required hold violation threshold is 200ps. + + + STA-3017: There are 1 clock cross SRB paths do not meet the required hold violation threshold(200ps). + @@ -18947,7 +18956,7 @@ clkbufg_1/gopclkbufg USCM_84_108 ntclkbufg_1 - 2506 + 2505 0 u_sys_pll/u_pll_e3/goppll CLKOUT0 @@ -18965,8 +18974,18 @@ clkbufg_3/gopclkbufg - USCM_84_110 + USCM_84_118 ntclkbufg_3 + 733 + 0 + U_HDMI_PLL/u_pll_e3/goppll + CLKOUT0 + PLL_158_303 + + + clkbufg_4/gopclkbufg + USCM_84_110 + ntclkbufg_4 233 0 u_sys_pll/u_pll_e3/goppll @@ -18974,9 +18993,9 @@ PLL_158_55 - clkbufg_4/gopclkbufg + clkbufg_5/gopclkbufg USCM_84_111 - ntclkbufg_4 + ntclkbufg_5 167 0 hdmi_in_clk_ibuf/opit_1 @@ -18984,9 +19003,9 @@ IOL_163_6 - clkbufg_5/gopclkbufg + clkbufg_6/gopclkbufg USCM_84_112 - ntclkbufg_5 + ntclkbufg_6 118 0 cmos1_pclk_ibuf/opit_1 @@ -18994,9 +19013,9 @@ IOL_171_6 - clkbufg_6/gopclkbufg - USCM_84_118 - ntclkbufg_6 + clkbufg_7/gopclkbufg + USCM_84_119 + ntclkbufg_7 118 0 cmos2_pclk_ibuf/opit_1 @@ -19004,9 +19023,9 @@ IOL_39_6 - clkbufg_7/gopclkbufg + clkbufg_8/gopclkbufg USCM_84_114 - ntclkbufg_7 + ntclkbufg_8 26 0 u_sys_pll/u_pll_e3/goppll @@ -19017,7 +19036,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg USCM_84_113 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - 68 + 71 0 u_sys_pll/u_pll_e3/goppll CLKOUT1 @@ -19035,29 +19054,29 @@ u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg - USCM_84_119 + USCM_84_120 u_ov5640/coms1_reg_config/clock_20k 18 0 u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv Q - CLMA_182_12 + CLMS_122_9 u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg - USCM_84_120 + USCM_84_121 u_ov5640/coms2_reg_config/clock_20k 18 0 u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv Q - CLMA_182_25 + CLMA_122_12 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg USCM_84_109 gmii_clk - 1860 + 1861 0 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0 CLKOUT @@ -19094,7 +19113,7 @@ U_HDMI_PLL/u_pll_e3/goppll PLL_158_303 CLKIN1 - ntR3907 + ntR3950 - - USCMROUTE_0 @@ -19105,10 +19124,10 @@ U_HDMI_PLL/u_pll_e3/goppll PLL_158_303 CLKIN2 - ntR2156 + ntR2187 - - - GND_1215 + GND_1222 Z HARD0N1_156_305 @@ -19138,10 +19157,10 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll PLL_158_199 CLKIN2 - ntR2589 + ntR2620 - - - GND_482 + GND_465 Z HARD0N1_156_197 @@ -19171,10 +19190,10 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_1/u_pll_e3/goppll PLL_158_179 CLKIN2 - ntR2593 + ntR2624 - - - GND_1216 + GND_1220 Z HARD0N1_156_181 @@ -19204,13 +19223,24 @@ u_sys_pll/u_pll_e3/goppll PLL_158_55 CLKIN2 - ntR2973 + ntR3004 - - - GND_1214 + GND_1221 Z HARD0N1_156_57 + + U_HDMI_PLL/u_pll_e3/goppll + PLL_158_303 + CLKOUT0 + zoom_clk + 733 + 0 + ... + ... + ... + U_HDMI_PLL/u_pll_e3/goppll PLL_158_303 @@ -19260,7 +19290,7 @@ PLL_158_55 CLKOUT0 rd3_clk - 2507 + 2506 0 ... ... @@ -19270,8 +19300,8 @@ u_sys_pll/u_pll_e3/goppll PLL_158_55 CLKOUT1 - zoom_clk - 810 + ddr_clk + 77 0 ... ... diff --git a/project/report_timing/multimedia_video_processor.rtr b/project/report_timing/multimedia_video_processor.rtr index 3eae1d4..033bfee 100644 --- a/project/report_timing/multimedia_video_processor.rtr +++ b/project/report_timing/multimedia_video_processor.rtr @@ -1,7 +1,7 @@ ---------------------------------------------------------------------------------------------------- | Tool Version : Fabric Compiler (version 2022.2-SP1-Lite ) -| Date : Sat Nov 11 17:58:35 2023 +| Date : Wed Nov 15 19:40:13 2023 | Design : multimedia_video_processor | Device : PGL50H | Speed Grade : -6 @@ -20,8 +20,8 @@ Timing analysis mode : multi corner Clock Period Waveform Type Loads Loads Sources ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ clk 20.000 {0 10} Declared 0 7 {clk} - clk_50m 20.000 {0 10} Generated (clk) 2517 0 {u_sys_pll/u_pll_e3/goppll/CLKOUT0} - clk_200m 5.000 {0 2.5} Generated (clk) 825 5 {u_sys_pll/u_pll_e3/goppll/CLKOUT1} + clk_50m 20.000 {0 10} Generated (clk) 2516 0 {u_sys_pll/u_pll_e3/goppll/CLKOUT0} + clk_200m 5.000 {0 2.5} Generated (clk) 75 5 {u_sys_pll/u_pll_e3/goppll/CLKOUT1} ddrphy_clkin 10.000 {0 5} Generated (clk_200m) 5464 0 {u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV} ioclk0 2.500 {0 1.25} Generated (clk_200m) 11 0 {u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT} ioclk1 2.500 {0 1.25} Generated (clk_200m) 27 1 {u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT} @@ -31,12 +31,12 @@ Timing analysis mode : multi corner clk_25m 40.000 {0 20} Generated (clk) 26 2 {u_sys_pll/u_pll_e3/goppll/CLKOUT3} clk_20k 50000.000 {0 25000} Generated (clk_25m) 38 0 {u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT} clk_10m 100.000 {0 50} Generated (clk) 235 0 {u_sys_pll/u_pll_e3/goppll/CLKOUT4} - clk_1080p60Hz 6.737 {0 3.368} Generated (clk) 0 0 {U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0} + clk_1080p60Hz 6.737 {0 3.368} Generated (clk) 750 0 {U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0} clk_720p60Hz 13.474 {0 6.736} Generated (clk) 1635 1 {U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1} cmos1_pclk 11.900 {0 5.95} Declared 118 0 {cmos1_pclk} cmos2_pclk 11.900 {0 5.95} Declared 118 0 {cmos2_pclk} hdmi_in_clk 6.666 {0 3.333} Declared 167 0 {hdmi_in_clk} - eth_rxc 8.000 {0 4} Declared 1861 1 {eth_rxc} + eth_rxc 8.000 {0 4} Declared 1862 1 {eth_rxc} ============================================================================================================================================================================================================================== Clock Groups: @@ -66,39 +66,41 @@ Timing analysis mode : multi corner Requested Estimated Requested Estimated Clock Frequency Frequency Period Period Slack ---------------------------------------------------------------------------------------------------- - cmos1_pclk 84.034 MHz 161.186 MHz 11.900 6.204 5.696 - cmos2_pclk 84.034 MHz 131.423 MHz 11.900 7.609 4.291 - hdmi_in_clk 150.015 MHz 180.636 MHz 6.666 5.536 1.130 - eth_rxc 125.000 MHz 144.446 MHz 8.000 6.923 1.077 - clk_50m 50.000 MHz 109.349 MHz 20.000 9.145 10.855 - clk_200m 200.000 MHz 172.771 MHz 5.000 5.788 -0.788 - clk_25m 25.000 MHz 218.293 MHz 40.000 4.581 35.419 - clk_10m 10.000 MHz 171.644 MHz 100.000 5.826 94.174 - clk_720p60Hz 74.219 MHz 124.635 MHz 13.474 8.023 5.450 - clk_20k 0.020 MHz 201.939 MHz 50000.000 4.952 49995.048 - ddrphy_clkin 100.000 MHz 103.605 MHz 10.000 9.652 0.348 + cmos1_pclk 84.034 MHz 151.630 MHz 11.900 6.595 5.305 + cmos2_pclk 84.034 MHz 132.398 MHz 11.900 7.553 4.347 + hdmi_in_clk 150.015 MHz 207.168 MHz 6.666 4.827 1.839 + eth_rxc 125.000 MHz 143.390 MHz 8.000 6.974 1.026 + clk_50m 50.000 MHz 103.670 MHz 20.000 9.646 10.354 + clk_200m 200.000 MHz 257.798 MHz 5.000 3.879 1.121 + clk_25m 25.000 MHz 222.272 MHz 40.000 4.499 35.501 + clk_10m 10.000 MHz 184.775 MHz 100.000 5.412 94.588 + clk_1080p60Hz 148.438 MHz 176.875 MHz 6.737 5.654 1.083 + clk_720p60Hz 74.219 MHz 133.594 MHz 13.474 7.485 5.988 + clk_20k 0.020 MHz 185.563 MHz 50000.000 5.389 49994.611 + ddrphy_clkin 100.000 MHz 132.837 MHz 10.000 7.528 2.472 ioclk0 400.000 MHz 1237.624 MHz 2.500 0.808 1.692 ioclk1 400.000 MHz 1237.624 MHz 2.500 0.808 1.692 ==================================================================================================== -Design Summary : Some Constraints Violated. +Design Summary : All Constraints Met. Setup Summary(Slow Corner): **************************************************************************************************** TNS Failing TNS Total Launch Clock Capture Clock WNS(ns) TNS(ns) Endpoints Endpoints ---------------------------------------------------------------------------------------------------- - cmos1_pclk cmos1_pclk 5.696 0.000 0 251 - cmos2_pclk cmos2_pclk 4.291 0.000 0 251 - hdmi_in_clk hdmi_in_clk 1.130 0.000 0 311 - eth_rxc eth_rxc 1.077 0.000 0 5907 - clk_50m clk_50m 10.855 0.000 0 9498 - clk_200m clk_200m -0.788 -18.651 44 3769 - clk_25m clk_25m 35.419 0.000 0 30 - clk_10m clk_10m 94.174 0.000 0 1099 - clk_720p60Hz clk_720p60Hz 5.450 0.000 0 4786 - clk_20k clk_20k 49995.048 0.000 0 181 - ddrphy_clkin ddrphy_clkin 0.348 0.000 0 18193 + cmos1_pclk cmos1_pclk 5.305 0.000 0 251 + cmos2_pclk cmos2_pclk 4.347 0.000 0 251 + hdmi_in_clk hdmi_in_clk 1.839 0.000 0 311 + eth_rxc eth_rxc 1.026 0.000 0 5918 + clk_50m clk_50m 10.354 0.000 0 9493 + clk_200m clk_200m 1.121 0.000 0 258 + clk_25m clk_25m 35.501 0.000 0 30 + clk_10m clk_10m 94.588 0.000 0 1092 + clk_1080p60Hz clk_1080p60Hz 1.083 0.000 0 3524 + clk_720p60Hz clk_720p60Hz 5.988 0.000 0 4786 + clk_20k clk_20k 49994.611 0.000 0 177 + ddrphy_clkin ddrphy_clkin 2.472 0.000 0 18286 ioclk0 ioclk0 1.692 0.000 0 24 ioclk1 ioclk1 1.692 0.000 0 72 ==================================================================================================== @@ -108,17 +110,18 @@ Hold Summary(Slow Corner): THS Failing THS Total Launch Clock Capture Clock WHS(ns) THS(ns) Endpoints Endpoints ---------------------------------------------------------------------------------------------------- - cmos1_pclk cmos1_pclk 0.199 0.000 0 251 - cmos2_pclk cmos2_pclk 0.415 0.000 0 251 - hdmi_in_clk hdmi_in_clk 0.191 0.000 0 311 - eth_rxc eth_rxc 0.381 0.000 0 5907 - clk_50m clk_50m 0.182 0.000 0 9498 - clk_200m clk_200m 0.241 0.000 0 3769 - clk_25m clk_25m 0.575 0.000 0 30 - clk_10m clk_10m 0.314 0.000 0 1099 - clk_720p60Hz clk_720p60Hz 0.313 0.000 0 4786 - clk_20k clk_20k 0.376 0.000 0 181 - ddrphy_clkin ddrphy_clkin 0.149 0.000 0 18193 + cmos1_pclk cmos1_pclk 0.175 0.000 0 251 + cmos2_pclk cmos2_pclk 0.407 0.000 0 251 + hdmi_in_clk hdmi_in_clk 0.189 0.000 0 311 + eth_rxc eth_rxc 0.157 0.000 0 5918 + clk_50m clk_50m 0.201 0.000 0 9493 + clk_200m clk_200m 0.315 0.000 0 258 + clk_25m clk_25m 0.550 0.000 0 30 + clk_10m clk_10m 0.287 0.000 0 1092 + clk_1080p60Hz clk_1080p60Hz 0.212 0.000 0 3524 + clk_720p60Hz clk_720p60Hz 0.314 0.000 0 4786 + clk_20k clk_20k 0.372 0.000 0 177 + ddrphy_clkin ddrphy_clkin 0.161 0.000 0 18286 ioclk0 ioclk0 0.450 0.000 0 24 ioclk1 ioclk1 0.450 0.000 0 72 ==================================================================================================== @@ -128,11 +131,12 @@ Recovery Summary(Slow Corner): TNS Failing TNS Total Launch Clock Capture Clock WNS(ns) TNS(ns) Endpoints Endpoints ---------------------------------------------------------------------------------------------------- - clk_50m clk_50m 16.039 0.000 0 192 - clk_200m clk_200m 1.103 0.000 0 175 - clk_10m clk_10m 97.793 0.000 0 1 - clk_720p60Hz clk_720p60Hz 8.580 0.000 0 717 - ddrphy_clkin ddrphy_clkin 5.474 0.000 0 2569 + clk_50m clk_50m 15.776 0.000 0 192 + clk_200m clk_200m 1.149 0.000 0 69 + clk_10m clk_10m 97.797 0.000 0 1 + clk_1080p60Hz clk_1080p60Hz 3.268 0.000 0 106 + clk_720p60Hz clk_720p60Hz 8.940 0.000 0 717 + ddrphy_clkin ddrphy_clkin 5.676 0.000 0 2569 ==================================================================================================== Removal Summary(Slow Corner): @@ -140,11 +144,12 @@ Removal Summary(Slow Corner): THS Failing THS Total Launch Clock Capture Clock WHS(ns) THS(ns) Endpoints Endpoints ---------------------------------------------------------------------------------------------------- - clk_50m clk_50m 0.555 0.000 0 192 - clk_200m clk_200m 0.554 0.000 0 175 - clk_10m clk_10m 1.312 0.000 0 1 - clk_720p60Hz clk_720p60Hz 1.244 0.000 0 717 - ddrphy_clkin ddrphy_clkin 0.779 0.000 0 2569 + clk_50m clk_50m 0.610 0.000 0 192 + clk_200m clk_200m 0.555 0.000 0 69 + clk_10m clk_10m 1.263 0.000 0 1 + clk_1080p60Hz clk_1080p60Hz 1.249 0.000 0 106 + clk_720p60Hz clk_720p60Hz 0.984 0.000 0 717 + ddrphy_clkin ddrphy_clkin 0.637 0.000 0 2569 ==================================================================================================== Minimum Pulse Width Summary(Slow Corner): @@ -155,11 +160,12 @@ Minimum Pulse Width Summary(Slow Corner): cmos1_pclk 5.052 0.000 0 118 cmos2_pclk 5.052 0.000 0 118 hdmi_in_clk 2.435 0.000 0 167 - eth_rxc 2.483 0.000 0 1861 - clk_50m 8.862 0.000 0 2517 - clk_200m 1.362 0.000 0 825 - clk_25m 19.580 0.000 0 26 + eth_rxc 2.483 0.000 0 1862 + clk_50m 8.862 0.000 0 2516 + clk_200m 1.880 0.000 0 75 + clk_25m 19.380 0.000 0 26 clk_10m 49.102 0.000 0 235 + clk_1080p60Hz 2.230 0.000 0 750 clk_720p60Hz 5.598 0.000 0 1635 clk_20k 24999.102 0.000 0 38 ddrphy_clkin 3.100 0.000 0 5464 @@ -174,17 +180,18 @@ Setup Summary(Fast Corner): TNS Failing TNS Total Launch Clock Capture Clock WNS(ns) TNS(ns) Endpoints Endpoints ---------------------------------------------------------------------------------------------------- - cmos1_pclk cmos1_pclk 6.761 0.000 0 251 - cmos2_pclk cmos2_pclk 6.092 0.000 0 251 - hdmi_in_clk hdmi_in_clk 2.618 0.000 0 311 - eth_rxc eth_rxc 3.025 0.000 0 5907 - clk_50m clk_50m 13.413 0.000 0 9498 - clk_200m clk_200m 0.707 0.000 0 3769 - clk_25m clk_25m 36.725 0.000 0 30 - clk_10m clk_10m 95.894 0.000 0 1099 - clk_720p60Hz clk_720p60Hz 7.848 0.000 0 4786 - clk_20k clk_20k 49996.400 0.000 0 181 - ddrphy_clkin ddrphy_clkin 3.245 0.000 0 18193 + cmos1_pclk cmos1_pclk 6.435 0.000 0 251 + cmos2_pclk cmos2_pclk 5.869 0.000 0 251 + hdmi_in_clk hdmi_in_clk 3.150 0.000 0 311 + eth_rxc eth_rxc 3.051 0.000 0 5918 + clk_50m clk_50m 12.954 0.000 0 9493 + clk_200m clk_200m 2.129 0.000 0 258 + clk_25m clk_25m 36.784 0.000 0 30 + clk_10m clk_10m 96.148 0.000 0 1092 + clk_1080p60Hz clk_1080p60Hz 2.488 0.000 0 3524 + clk_720p60Hz clk_720p60Hz 8.191 0.000 0 4786 + clk_20k clk_20k 49996.111 0.000 0 177 + ddrphy_clkin ddrphy_clkin 4.645 0.000 0 18286 ioclk0 ioclk0 1.834 0.000 0 24 ioclk1 ioclk1 1.834 0.000 0 72 ==================================================================================================== @@ -194,17 +201,18 @@ Hold Summary(Fast Corner): THS Failing THS Total Launch Clock Capture Clock WHS(ns) THS(ns) Endpoints Endpoints ---------------------------------------------------------------------------------------------------- - cmos1_pclk cmos1_pclk 0.108 0.000 0 251 - cmos2_pclk cmos2_pclk 0.254 0.000 0 251 - hdmi_in_clk hdmi_in_clk 0.106 0.000 0 311 - eth_rxc eth_rxc 0.252 0.000 0 5907 - clk_50m clk_50m 0.139 0.000 0 9498 - clk_200m clk_200m 0.196 0.000 0 3769 - clk_25m clk_25m 0.406 0.000 0 30 - clk_10m clk_10m 0.232 0.000 0 1099 - clk_720p60Hz clk_720p60Hz 0.251 0.000 0 4786 - clk_20k clk_20k 0.269 0.000 0 181 - ddrphy_clkin ddrphy_clkin 0.111 0.000 0 18193 + cmos1_pclk cmos1_pclk 0.104 0.000 0 251 + cmos2_pclk cmos2_pclk 0.250 0.000 0 251 + hdmi_in_clk hdmi_in_clk 0.103 0.000 0 311 + eth_rxc eth_rxc 0.075 0.000 0 5918 + clk_50m clk_50m 0.143 0.000 0 9493 + clk_200m clk_200m 0.242 0.000 0 258 + clk_25m clk_25m 0.388 0.000 0 30 + clk_10m clk_10m 0.232 0.000 0 1092 + clk_1080p60Hz clk_1080p60Hz 0.160 0.000 0 3524 + clk_720p60Hz clk_720p60Hz 0.252 0.000 0 4786 + clk_20k clk_20k 0.273 0.000 0 177 + ddrphy_clkin ddrphy_clkin 0.115 0.000 0 18286 ioclk0 ioclk0 0.383 0.000 0 24 ioclk1 ioclk1 0.383 0.000 0 72 ==================================================================================================== @@ -214,11 +222,12 @@ Recovery Summary(Fast Corner): TNS Failing TNS Total Launch Clock Capture Clock WNS(ns) TNS(ns) Endpoints Endpoints ---------------------------------------------------------------------------------------------------- - clk_50m clk_50m 17.096 0.000 0 192 - clk_200m clk_200m 2.157 0.000 0 175 - clk_10m clk_10m 98.359 0.000 0 1 - clk_720p60Hz clk_720p60Hz 9.915 0.000 0 717 - ddrphy_clkin ddrphy_clkin 6.770 0.000 0 2569 + clk_50m clk_50m 16.962 0.000 0 192 + clk_200m clk_200m 2.160 0.000 0 69 + clk_10m clk_10m 98.381 0.000 0 1 + clk_1080p60Hz clk_1080p60Hz 4.288 0.000 0 106 + clk_720p60Hz clk_720p60Hz 10.123 0.000 0 717 + ddrphy_clkin ddrphy_clkin 6.879 0.000 0 2569 ==================================================================================================== Removal Summary(Fast Corner): @@ -226,11 +235,12 @@ Removal Summary(Fast Corner): THS Failing THS Total Launch Clock Capture Clock WHS(ns) THS(ns) Endpoints Endpoints ---------------------------------------------------------------------------------------------------- - clk_50m clk_50m 0.418 0.000 0 192 - clk_200m clk_200m 0.452 0.000 0 175 - clk_10m clk_10m 0.915 0.000 0 1 - clk_720p60Hz clk_720p60Hz 0.851 0.000 0 717 - ddrphy_clkin ddrphy_clkin 0.555 0.000 0 2569 + clk_50m clk_50m 0.454 0.000 0 192 + clk_200m clk_200m 0.452 0.000 0 69 + clk_10m clk_10m 0.873 0.000 0 1 + clk_1080p60Hz clk_1080p60Hz 0.860 0.000 0 106 + clk_720p60Hz clk_720p60Hz 0.722 0.000 0 717 + ddrphy_clkin ddrphy_clkin 0.482 0.000 0 2569 ==================================================================================================== Minimum Pulse Width Summary(Fast Corner): @@ -241,11 +251,12 @@ Minimum Pulse Width Summary(Fast Corner): cmos1_pclk 5.232 0.000 0 118 cmos2_pclk 5.232 0.000 0 118 hdmi_in_clk 2.615 0.000 0 167 - eth_rxc 2.787 0.000 0 1861 - clk_50m 9.090 0.000 0 2517 - clk_200m 1.590 0.000 0 825 - clk_25m 19.664 0.000 0 26 + eth_rxc 2.787 0.000 0 1862 + clk_50m 9.090 0.000 0 2516 + clk_200m 2.004 0.000 0 75 + clk_25m 19.504 0.000 0 26 clk_10m 49.282 0.000 0 235 + clk_1080p60Hz 2.458 0.000 0 750 clk_720p60Hz 5.826 0.000 0 1635 clk_20k 24999.282 0.000 0 38 ddrphy_clkin 3.480 0.000 0 5464 @@ -259,8 +270,8 @@ Slow Corner **************************************************************************************************** ==================================================================================================== -Startpoint : cmos1_data[5] (port) -Endpoint : u_ov5640/cmos1_d_d0[5]/opit_0/D +Startpoint : cmos1_href (port) +Endpoint : u_ov5640/cmos1_href_d0/opit_0/D Path Group : cmos1_pclk Path Type : max (slow corner) Path Class : sequential timing path @@ -273,20 +284,18 @@ Clock Skew : 5.188 (Capture Clock Delay - Launch Clock Delay + Clock Pessim ---------------------------------------------------------------------------------------------------- Clock cmos1_pclk (rising edge) 0.000 0.000 r - Input external delay 1.000 1.000 r + Input external delay 1.000 1.000 f - AB11 0.000 1.000 r cmos1_data[5] (port) - net (fanout=1) 0.077 1.077 cmos1_data[5] - IOBS_TB_156_0/DIN td 2.166 3.243 r cmos1_data_ibuf[5]/opit_0/O - net (fanout=1) 0.000 3.243 cmos1_data_ibuf[5]/ntD - IOL_159_5/RX_DATA_DD td 0.126 3.369 r cmos1_data_ibuf[5]/opit_1/OUT - net (fanout=1) 2.329 5.698 nt_cmos1_data[5] - CLMS_322_9/Y6CD td 0.149 5.847 r CLKROUTE_0/Z - net (fanout=1) 5.216 11.063 ntR3901 - CLMS_146_9/M0 r u_ov5640/cmos1_d_d0[5]/opit_0/D + AB10 0.000 1.000 f cmos1_href (port) + net (fanout=1) 0.063 1.063 cmos1_href + IOBR_TB_148_0/DIN td 1.367 2.430 f cmos1_href_ibuf/opit_0/O + net (fanout=1) 0.000 2.430 cmos1_href_ibuf/ntD + IOL_151_5/RX_DATA_DD td 0.127 2.557 f cmos1_href_ibuf/opit_1/OUT + net (fanout=1) 8.888 11.445 nt_cmos1_href + CLMA_150_12/M1 f u_ov5640/cmos1_href_d0/opit_0/D - Data arrival time 11.063 Logic Levels: 3 - Logic: 2.441ns(24.257%), Route: 7.622ns(75.743%) + Data arrival time 11.445 Logic Levels: 2 + Logic: 1.494ns(14.303%), Route: 8.951ns(85.697%) ---------------------------------------------------------------------------------------------------- Clock cmos1_pclk (rising edge) 11.900 11.900 r @@ -296,26 +305,26 @@ Clock Skew : 5.188 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.000 13.023 cmos1_pclk_ibuf/ntD IOL_171_6/INCK td 0.048 13.071 r cmos1_pclk_ibuf/opit_1/INCK net (fanout=1) 2.486 15.557 _N64 - USCM_84_112/CLK_USCM td 0.000 15.557 r clkbufg_5/gopclkbufg/CLKOUT - net (fanout=118) 1.531 17.088 ntclkbufg_5 - CLMS_146_9/CLK r u_ov5640/cmos1_d_d0[5]/opit_0/CLK + USCM_84_112/CLK_USCM td 0.000 15.557 r clkbufg_6/gopclkbufg/CLKOUT + net (fanout=118) 1.531 17.088 ntclkbufg_6 + CLMA_150_12/CLK r u_ov5640/cmos1_href_d0/opit_0/CLK clock pessimism 0.000 17.088 clock uncertainty -0.250 16.838 - Setup time -0.079 16.759 + Setup time -0.088 16.750 - Data required time 16.759 + Data required time 16.750 ---------------------------------------------------------------------------------------------------- - Data required time 16.759 - Data arrival time 11.063 + Data required time 16.750 + Data arrival time 11.445 ---------------------------------------------------------------------------------------------------- - Slack (MET) 5.696 + Slack (MET) 5.305 ==================================================================================================== ==================================================================================================== -Startpoint : cmos1_data[4] (port) -Endpoint : u_ov5640/cmos1_d_d0[4]/opit_0/D +Startpoint : cmos1_data[6] (port) +Endpoint : u_ov5640/cmos1_d_d0[6]/opit_0/D Path Group : cmos1_pclk Path Type : max (slow corner) Path Class : sequential timing path @@ -330,16 +339,16 @@ Clock Skew : 5.188 (Capture Clock Delay - Launch Clock Delay + Clock Pessim Clock cmos1_pclk (rising edge) 0.000 0.000 r Input external delay 1.000 1.000 r - W11 0.000 1.000 r cmos1_data[4] (port) - net (fanout=1) 0.041 1.041 cmos1_data[4] - IOBS_TB_132_0/DIN td 2.166 3.207 r cmos1_data_ibuf[4]/opit_0/O - net (fanout=1) 0.000 3.207 cmos1_data_ibuf[4]/ntD - IOL_135_5/RX_DATA_DD td 0.126 3.333 r cmos1_data_ibuf[4]/opit_1/OUT - net (fanout=1) 7.830 11.163 nt_cmos1_data[4] - CLMS_134_13/AD r u_ov5640/cmos1_d_d0[4]/opit_0/D + AA10 0.000 1.000 r cmos1_data[6] (port) + net (fanout=1) 0.080 1.080 cmos1_data[6] + IOBD_149_0/DIN td 2.166 3.246 r cmos1_data_ibuf[6]/opit_0/O + net (fanout=1) 0.000 3.246 cmos1_data_ibuf[6]/ntD + IOL_151_6/RX_DATA_DD td 0.126 3.372 r cmos1_data_ibuf[6]/opit_1/OUT + net (fanout=1) 7.463 10.835 nt_cmos1_data[6] + CLMS_150_41/M1 r u_ov5640/cmos1_d_d0[6]/opit_0/D - Data arrival time 11.163 Logic Levels: 2 - Logic: 2.292ns(22.552%), Route: 7.871ns(77.448%) + Data arrival time 10.835 Logic Levels: 2 + Logic: 2.292ns(23.305%), Route: 7.543ns(76.695%) ---------------------------------------------------------------------------------------------------- Clock cmos1_pclk (rising edge) 11.900 11.900 r @@ -349,26 +358,26 @@ Clock Skew : 5.188 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.000 13.023 cmos1_pclk_ibuf/ntD IOL_171_6/INCK td 0.048 13.071 r cmos1_pclk_ibuf/opit_1/INCK net (fanout=1) 2.486 15.557 _N64 - USCM_84_112/CLK_USCM td 0.000 15.557 r clkbufg_5/gopclkbufg/CLKOUT - net (fanout=118) 1.531 17.088 ntclkbufg_5 - CLMS_134_13/CLK r u_ov5640/cmos1_d_d0[4]/opit_0/CLK + USCM_84_112/CLK_USCM td 0.000 15.557 r clkbufg_6/gopclkbufg/CLKOUT + net (fanout=118) 1.531 17.088 ntclkbufg_6 + CLMS_150_41/CLK r u_ov5640/cmos1_d_d0[6]/opit_0/CLK clock pessimism 0.000 17.088 clock uncertainty -0.250 16.838 - Setup time 0.029 16.867 + Setup time -0.079 16.759 - Data required time 16.867 + Data required time 16.759 ---------------------------------------------------------------------------------------------------- - Data required time 16.867 - Data arrival time 11.163 + Data required time 16.759 + Data arrival time 10.835 ---------------------------------------------------------------------------------------------------- - Slack (MET) 5.704 + Slack (MET) 5.924 ==================================================================================================== ==================================================================================================== -Startpoint : cmos1_href (port) -Endpoint : u_ov5640/cmos1_href_d0/opit_0/D +Startpoint : cmos1_data[0] (port) +Endpoint : u_ov5640/cmos1_d_d0[0]/opit_0/D Path Group : cmos1_pclk Path Type : max (slow corner) Path Class : sequential timing path @@ -381,18 +390,18 @@ Clock Skew : 5.188 (Capture Clock Delay - Launch Clock Delay + Clock Pessim ---------------------------------------------------------------------------------------------------- Clock cmos1_pclk (rising edge) 0.000 0.000 r - Input external delay 1.000 1.000 f + Input external delay 1.000 1.000 r - AB10 0.000 1.000 f cmos1_href (port) - net (fanout=1) 0.063 1.063 cmos1_href - IOBR_TB_148_0/DIN td 1.367 2.430 f cmos1_href_ibuf/opit_0/O - net (fanout=1) 0.000 2.430 cmos1_href_ibuf/ntD - IOL_151_5/RX_DATA_DD td 0.127 2.557 f cmos1_href_ibuf/opit_1/OUT - net (fanout=1) 8.583 11.140 nt_cmos1_href - CLMS_146_9/AD f u_ov5640/cmos1_href_d0/opit_0/D + V11 0.000 1.000 r cmos1_data[0] (port) + net (fanout=1) 0.053 1.053 cmos1_data[0] + IOBD_133_0/DIN td 2.166 3.219 r cmos1_data_ibuf[0]/opit_0/O + net (fanout=1) 0.000 3.219 cmos1_data_ibuf[0]/ntD + IOL_135_6/RX_DATA_DD td 0.126 3.345 r cmos1_data_ibuf[0]/opit_1/OUT + net (fanout=1) 7.485 10.830 nt_cmos1_data[0] + CLMS_134_45/CD r u_ov5640/cmos1_d_d0[0]/opit_0/D - Data arrival time 11.140 Logic Levels: 2 - Logic: 1.494ns(14.734%), Route: 8.646ns(85.266%) + Data arrival time 10.830 Logic Levels: 2 + Logic: 2.292ns(23.316%), Route: 7.538ns(76.684%) ---------------------------------------------------------------------------------------------------- Clock cmos1_pclk (rising edge) 11.900 11.900 r @@ -402,9 +411,9 @@ Clock Skew : 5.188 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.000 13.023 cmos1_pclk_ibuf/ntD IOL_171_6/INCK td 0.048 13.071 r cmos1_pclk_ibuf/opit_1/INCK net (fanout=1) 2.486 15.557 _N64 - USCM_84_112/CLK_USCM td 0.000 15.557 r clkbufg_5/gopclkbufg/CLKOUT - net (fanout=118) 1.531 17.088 ntclkbufg_5 - CLMS_146_9/CLK r u_ov5640/cmos1_href_d0/opit_0/CLK + USCM_84_112/CLK_USCM td 0.000 15.557 r clkbufg_6/gopclkbufg/CLKOUT + net (fanout=118) 1.531 17.088 ntclkbufg_6 + CLMS_134_45/CLK r u_ov5640/cmos1_d_d0[0]/opit_0/CLK clock pessimism 0.000 17.088 clock uncertainty -0.250 16.838 @@ -413,22 +422,22 @@ Clock Skew : 5.188 (Capture Clock Delay - Launch Clock Delay + Clock Pessim Data required time 16.867 ---------------------------------------------------------------------------------------------------- Data required time 16.867 - Data arrival time 11.140 + Data arrival time 10.830 ---------------------------------------------------------------------------------------------------- - Slack (MET) 5.727 + Slack (MET) 6.037 ==================================================================================================== ==================================================================================================== -Startpoint : u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK +Startpoint : u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK Endpoint : u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/L0 Path Group : cmos1_pclk Path Type : min (slow corner) Path Class : sequential timing path -Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) +Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) Capture Clock Delay : 5.521 Launch Clock Delay : 5.188 - Clock Pessimism Removal : -0.333 + Clock Pessimism Removal : -0.304 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -440,16 +449,16 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.000 1.123 cmos1_pclk_ibuf/ntD IOL_171_6/INCK td 0.048 1.171 r cmos1_pclk_ibuf/opit_1/INCK net (fanout=1) 2.486 3.657 _N64 - USCM_84_112/CLK_USCM td 0.000 3.657 r clkbufg_5/gopclkbufg/CLKOUT - net (fanout=118) 1.531 5.188 ntclkbufg_5 - CLMA_138_36/CLK r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK + USCM_84_112/CLK_USCM td 0.000 3.657 r clkbufg_6/gopclkbufg/CLKOUT + net (fanout=118) 1.531 5.188 ntclkbufg_6 + CLMA_138_60/CLK r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK - CLMA_138_36/Q3 tco 0.221 5.409 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/Q - net (fanout=24) 0.098 5.507 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wfull - CLMA_138_36/B0 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/L0 + CLMA_138_60/Q0 tco 0.222 5.410 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/Q0 + net (fanout=5) 0.088 5.498 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/wr_addr [8] + CLMA_138_61/A0 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/L0 - Data arrival time 5.507 Logic Levels: 0 - Logic: 0.221ns(69.279%), Route: 0.098ns(30.721%) + Data arrival time 5.498 Logic Levels: 0 + Logic: 0.222ns(71.613%), Route: 0.088ns(28.387%) ---------------------------------------------------------------------------------------------------- Clock cmos1_pclk (rising edge) 0.000 0.000 r @@ -459,33 +468,33 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.000 1.330 cmos1_pclk_ibuf/ntD IOL_171_6/INCK td 0.076 1.406 r cmos1_pclk_ibuf/opit_1/INCK net (fanout=1) 2.530 3.936 _N64 - USCM_84_112/CLK_USCM td 0.000 3.936 r clkbufg_5/gopclkbufg/CLKOUT - net (fanout=118) 1.585 5.521 ntclkbufg_5 - CLMA_138_36/CLK r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/CLK - clock pessimism -0.333 5.188 - clock uncertainty 0.200 5.388 + USCM_84_112/CLK_USCM td 0.000 3.936 r clkbufg_6/gopclkbufg/CLKOUT + net (fanout=118) 1.585 5.521 ntclkbufg_6 + CLMA_138_61/CLK r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/CLK + clock pessimism -0.304 5.217 + clock uncertainty 0.200 5.417 - Hold time -0.080 5.308 + Hold time -0.094 5.323 - Data required time 5.308 + Data required time 5.323 ---------------------------------------------------------------------------------------------------- - Data required time 5.308 - Data arrival time 5.507 + Data required time 5.323 + Data arrival time 5.498 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.199 + Slack (MET) 0.175 ==================================================================================================== ==================================================================================================== -Startpoint : u_ov5640/u_mix_image/cnt0_h[0]/opit_0_L5Q_perm/CLK -Endpoint : u_ov5640/u_mix_image/cnt0_h[0]/opit_0_L5Q_perm/L0 +Startpoint : u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK +Endpoint : u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/L0 Path Group : cmos1_pclk Path Type : min (slow corner) Path Class : sequential timing path -Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) +Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) Capture Clock Delay : 5.521 Launch Clock Delay : 5.188 - Clock Pessimism Removal : -0.333 + Clock Pessimism Removal : -0.304 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -497,16 +506,16 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.000 1.123 cmos1_pclk_ibuf/ntD IOL_171_6/INCK td 0.048 1.171 r cmos1_pclk_ibuf/opit_1/INCK net (fanout=1) 2.486 3.657 _N64 - USCM_84_112/CLK_USCM td 0.000 3.657 r clkbufg_5/gopclkbufg/CLKOUT - net (fanout=118) 1.531 5.188 ntclkbufg_5 - CLMA_154_28/CLK r u_ov5640/u_mix_image/cnt0_h[0]/opit_0_L5Q_perm/CLK + USCM_84_112/CLK_USCM td 0.000 3.657 r clkbufg_6/gopclkbufg/CLKOUT + net (fanout=118) 1.531 5.188 ntclkbufg_6 + CLMA_138_56/CLK r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK - CLMA_154_28/Q0 tco 0.222 5.410 f u_ov5640/u_mix_image/cnt0_h[0]/opit_0_L5Q_perm/Q - net (fanout=2) 0.085 5.495 u_ov5640/u_mix_image/cnt0_h [0] - CLMA_154_28/A0 f u_ov5640/u_mix_image/cnt0_h[0]/opit_0_L5Q_perm/L0 + CLMA_138_56/Q1 tco 0.224 5.412 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/Q1 + net (fanout=5) 0.089 5.501 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/wr_addr [5] + CLMA_138_57/C0 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/L0 - Data arrival time 5.495 Logic Levels: 0 - Logic: 0.222ns(72.313%), Route: 0.085ns(27.687%) + Data arrival time 5.501 Logic Levels: 0 + Logic: 0.224ns(71.565%), Route: 0.089ns(28.435%) ---------------------------------------------------------------------------------------------------- Clock cmos1_pclk (rising edge) 0.000 0.000 r @@ -516,33 +525,33 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.000 1.330 cmos1_pclk_ibuf/ntD IOL_171_6/INCK td 0.076 1.406 r cmos1_pclk_ibuf/opit_1/INCK net (fanout=1) 2.530 3.936 _N64 - USCM_84_112/CLK_USCM td 0.000 3.936 r clkbufg_5/gopclkbufg/CLKOUT - net (fanout=118) 1.585 5.521 ntclkbufg_5 - CLMA_154_28/CLK r u_ov5640/u_mix_image/cnt0_h[0]/opit_0_L5Q_perm/CLK - clock pessimism -0.333 5.188 - clock uncertainty 0.200 5.388 + USCM_84_112/CLK_USCM td 0.000 3.936 r clkbufg_6/gopclkbufg/CLKOUT + net (fanout=118) 1.585 5.521 ntclkbufg_6 + CLMA_138_57/CLK r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/CLK + clock pessimism -0.304 5.217 + clock uncertainty 0.200 5.417 - Hold time -0.094 5.294 + Hold time -0.093 5.324 - Data required time 5.294 + Data required time 5.324 ---------------------------------------------------------------------------------------------------- - Data required time 5.294 - Data arrival time 5.495 + Data required time 5.324 + Data arrival time 5.501 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.201 + Slack (MET) 0.177 ==================================================================================================== ==================================================================================================== -Startpoint : u_ov5640/u_mix_image/image1_en/opit_0_L5Q_perm/CLK -Endpoint : u_ov5640/u_mix_image/image1_en/opit_0_L5Q_perm/L0 +Startpoint : u_ov5640/cmos1_8_16bit/pdata_i2[4]/opit_0/CLK +Endpoint : u_ov5640/cmos1_8_16bit/image_data0[12]/opit_0/D Path Group : cmos1_pclk Path Type : min (slow corner) Path Class : sequential timing path -Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) +Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) Capture Clock Delay : 5.521 Launch Clock Delay : 5.188 - Clock Pessimism Removal : -0.333 + Clock Pessimism Removal : -0.304 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -554,16 +563,16 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.000 1.123 cmos1_pclk_ibuf/ntD IOL_171_6/INCK td 0.048 1.171 r cmos1_pclk_ibuf/opit_1/INCK net (fanout=1) 2.486 3.657 _N64 - USCM_84_112/CLK_USCM td 0.000 3.657 r clkbufg_5/gopclkbufg/CLKOUT - net (fanout=118) 1.531 5.188 ntclkbufg_5 - CLMA_150_28/CLK r u_ov5640/u_mix_image/image1_en/opit_0_L5Q_perm/CLK + USCM_84_112/CLK_USCM td 0.000 3.657 r clkbufg_6/gopclkbufg/CLKOUT + net (fanout=118) 1.531 5.188 ntclkbufg_6 + CLMA_138_44/CLK r u_ov5640/cmos1_8_16bit/pdata_i2[4]/opit_0/CLK - CLMA_150_28/Q0 tco 0.222 5.410 f u_ov5640/u_mix_image/image1_en/opit_0_L5Q_perm/Q - net (fanout=2) 0.085 5.495 u_ov5640/u_mix_image/image1_en - CLMA_150_28/A0 f u_ov5640/u_mix_image/image1_en/opit_0_L5Q_perm/L0 + CLMA_138_44/Y0 tco 0.284 5.472 f u_ov5640/cmos1_8_16bit/pdata_i2[4]/opit_0/Q + net (fanout=1) 0.191 5.663 u_ov5640/cmos1_8_16bit/pdata_i2 [4] + CLMA_138_45/AD f u_ov5640/cmos1_8_16bit/image_data0[12]/opit_0/D - Data arrival time 5.495 Logic Levels: 0 - Logic: 0.222ns(72.313%), Route: 0.085ns(27.687%) + Data arrival time 5.663 Logic Levels: 0 + Logic: 0.284ns(59.789%), Route: 0.191ns(40.211%) ---------------------------------------------------------------------------------------------------- Clock cmos1_pclk (rising edge) 0.000 0.000 r @@ -573,31 +582,31 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.000 1.330 cmos1_pclk_ibuf/ntD IOL_171_6/INCK td 0.076 1.406 r cmos1_pclk_ibuf/opit_1/INCK net (fanout=1) 2.530 3.936 _N64 - USCM_84_112/CLK_USCM td 0.000 3.936 r clkbufg_5/gopclkbufg/CLKOUT - net (fanout=118) 1.585 5.521 ntclkbufg_5 - CLMA_150_28/CLK r u_ov5640/u_mix_image/image1_en/opit_0_L5Q_perm/CLK - clock pessimism -0.333 5.188 - clock uncertainty 0.200 5.388 + USCM_84_112/CLK_USCM td 0.000 3.936 r clkbufg_6/gopclkbufg/CLKOUT + net (fanout=118) 1.585 5.521 ntclkbufg_6 + CLMA_138_45/CLK r u_ov5640/cmos1_8_16bit/image_data0[12]/opit_0/CLK + clock pessimism -0.304 5.217 + clock uncertainty 0.200 5.417 - Hold time -0.094 5.294 + Hold time 0.053 5.470 - Data required time 5.294 + Data required time 5.470 ---------------------------------------------------------------------------------------------------- - Data required time 5.294 - Data arrival time 5.495 + Data required time 5.470 + Data arrival time 5.663 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.201 + Slack (MET) 0.193 ==================================================================================================== ==================================================================================================== -Startpoint : cmos2_data[7] (port) -Endpoint : u_ov5640/cmos2_d_d0[7]/opit_0/D +Startpoint : cmos2_data[6] (port) +Endpoint : u_ov5640/cmos2_d_d0[6]/opit_0/D Path Group : cmos2_pclk Path Type : max (slow corner) Path Class : sequential timing path -Clock Skew : 5.551 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.551 +Clock Skew : 5.548 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 5.548 Launch Clock Delay : 0.000 Clock Pessimism Removal : 0.000 @@ -605,18 +614,18 @@ Clock Skew : 5.551 (Capture Clock Delay - Launch Clock Delay + Clock Pessim ---------------------------------------------------------------------------------------------------- Clock cmos2_pclk (rising edge) 0.000 0.000 r - Input external delay 1.000 1.000 r + Input external delay 1.000 1.000 f - AB9 0.000 1.000 r cmos2_data[7] (port) - net (fanout=1) 0.080 1.080 cmos2_data[7] - IOBS_TB_128_0/DIN td 2.166 3.246 r cmos2_data_ibuf[7]/opit_0/O - net (fanout=1) 0.000 3.246 cmos2_data_ibuf[7]/ntD - IOL_131_5/RX_DATA_DD td 0.126 3.372 r cmos2_data_ibuf[7]/opit_1/OUT - net (fanout=1) 9.459 12.831 nt_cmos2_data[7] - CLMS_130_37/M2 r u_ov5640/cmos2_d_d0[7]/opit_0/D + Y9 0.000 1.000 f cmos2_data[6] (port) + net (fanout=1) 0.078 1.078 cmos2_data[6] + IOBD_129_0/DIN td 1.513 2.591 f cmos2_data_ibuf[6]/opit_0/O + net (fanout=1) 0.000 2.591 cmos2_data_ibuf[6]/ntD + IOL_131_6/RX_DATA_DD td 0.127 2.718 f cmos2_data_ibuf[6]/opit_1/OUT + net (fanout=1) 10.045 12.763 nt_cmos2_data[6] + CLMA_138_8/M1 f u_ov5640/cmos2_d_d0[6]/opit_0/D - Data arrival time 12.831 Logic Levels: 2 - Logic: 2.292ns(19.373%), Route: 9.539ns(80.627%) + Data arrival time 12.763 Logic Levels: 2 + Logic: 1.640ns(13.942%), Route: 10.123ns(86.058%) ---------------------------------------------------------------------------------------------------- Clock cmos2_pclk (rising edge) 11.900 11.900 r @@ -625,32 +634,32 @@ Clock Skew : 5.551 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOBD_37_0/DIN td 1.047 13.018 r cmos2_pclk_ibuf/opit_0/O net (fanout=1) 0.000 13.018 cmos2_pclk_ibuf/ntD IOL_39_6/RX_DATA_DD td 0.082 13.100 r cmos2_pclk_ibuf/opit_1/OUT - net (fanout=1) 2.820 15.920 nt_cmos2_pclk - USCM_84_118/CLK_USCM td 0.000 15.920 r clkbufg_6/gopclkbufg/CLKOUT - net (fanout=118) 1.531 17.451 ntclkbufg_6 - CLMS_130_37/CLK r u_ov5640/cmos2_d_d0[7]/opit_0/CLK - clock pessimism 0.000 17.451 - clock uncertainty -0.250 17.201 + net (fanout=1) 2.817 15.917 nt_cmos2_pclk + USCM_84_119/CLK_USCM td 0.000 15.917 r clkbufg_7/gopclkbufg/CLKOUT + net (fanout=118) 1.531 17.448 ntclkbufg_7 + CLMA_138_8/CLK r u_ov5640/cmos2_d_d0[6]/opit_0/CLK + clock pessimism 0.000 17.448 + clock uncertainty -0.250 17.198 - Setup time -0.079 17.122 + Setup time -0.088 17.110 - Data required time 17.122 + Data required time 17.110 ---------------------------------------------------------------------------------------------------- - Data required time 17.122 - Data arrival time 12.831 + Data required time 17.110 + Data arrival time 12.763 ---------------------------------------------------------------------------------------------------- - Slack (MET) 4.291 + Slack (MET) 4.347 ==================================================================================================== ==================================================================================================== -Startpoint : cmos2_data[2] (port) -Endpoint : u_ov5640/cmos2_d_d0[2]/opit_0/D +Startpoint : cmos2_data[5] (port) +Endpoint : u_ov5640/cmos2_d_d0[5]/opit_0/D Path Group : cmos2_pclk Path Type : max (slow corner) Path Class : sequential timing path -Clock Skew : 5.551 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.551 +Clock Skew : 5.548 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 5.548 Launch Clock Delay : 0.000 Clock Pessimism Removal : 0.000 @@ -658,18 +667,20 @@ Clock Skew : 5.551 (Capture Clock Delay - Launch Clock Delay + Clock Pessim ---------------------------------------------------------------------------------------------------- Clock cmos2_pclk (rising edge) 0.000 0.000 r - Input external delay 1.000 1.000 r + Input external delay 1.000 1.000 f - T8 0.000 1.000 r cmos2_data[2] (port) - net (fanout=1) 0.057 1.057 cmos2_data[2] - IOBD_61_0/DIN td 2.166 3.223 r cmos2_data_ibuf[2]/opit_0/O - net (fanout=1) 0.000 3.223 cmos2_data_ibuf[2]/ntD - IOL_63_6/RX_DATA_DD td 0.126 3.349 r cmos2_data_ibuf[2]/opit_1/OUT - net (fanout=1) 8.903 12.252 nt_cmos2_data[2] - CLMA_134_40/M3 r u_ov5640/cmos2_d_d0[2]/opit_0/D + AB8 0.000 1.000 f cmos2_data[5] (port) + net (fanout=1) 0.084 1.084 cmos2_data[5] + IOBS_TB_116_0/DIN td 1.513 2.597 f cmos2_data_ibuf[5]/opit_0/O + net (fanout=1) 0.000 2.597 cmos2_data_ibuf[5]/ntD + IOL_119_5/RX_DATA_DD td 0.127 2.724 f cmos2_data_ibuf[5]/opit_1/OUT + net (fanout=1) 1.531 4.255 nt_cmos2_data[5] + CLMS_198_49/Y6CD td 0.134 4.389 f CLKROUTE_0/Z + net (fanout=1) 8.355 12.744 ntR3940 + CLMA_138_8/M0 f u_ov5640/cmos2_d_d0[5]/opit_0/D - Data arrival time 12.252 Logic Levels: 2 - Logic: 2.292ns(20.370%), Route: 8.960ns(79.630%) + Data arrival time 12.744 Logic Levels: 3 + Logic: 1.774ns(15.106%), Route: 9.970ns(84.894%) ---------------------------------------------------------------------------------------------------- Clock cmos2_pclk (rising edge) 11.900 11.900 r @@ -678,32 +689,32 @@ Clock Skew : 5.551 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOBD_37_0/DIN td 1.047 13.018 r cmos2_pclk_ibuf/opit_0/O net (fanout=1) 0.000 13.018 cmos2_pclk_ibuf/ntD IOL_39_6/RX_DATA_DD td 0.082 13.100 r cmos2_pclk_ibuf/opit_1/OUT - net (fanout=1) 2.820 15.920 nt_cmos2_pclk - USCM_84_118/CLK_USCM td 0.000 15.920 r clkbufg_6/gopclkbufg/CLKOUT - net (fanout=118) 1.531 17.451 ntclkbufg_6 - CLMA_134_40/CLK r u_ov5640/cmos2_d_d0[2]/opit_0/CLK - clock pessimism 0.000 17.451 - clock uncertainty -0.250 17.201 + net (fanout=1) 2.817 15.917 nt_cmos2_pclk + USCM_84_119/CLK_USCM td 0.000 15.917 r clkbufg_7/gopclkbufg/CLKOUT + net (fanout=118) 1.531 17.448 ntclkbufg_7 + CLMA_138_8/CLK r u_ov5640/cmos2_d_d0[5]/opit_0/CLK + clock pessimism 0.000 17.448 + clock uncertainty -0.250 17.198 - Setup time -0.079 17.122 + Setup time -0.088 17.110 - Data required time 17.122 + Data required time 17.110 ---------------------------------------------------------------------------------------------------- - Data required time 17.122 - Data arrival time 12.252 + Data required time 17.110 + Data arrival time 12.744 ---------------------------------------------------------------------------------------------------- - Slack (MET) 4.870 + Slack (MET) 4.366 ==================================================================================================== ==================================================================================================== -Startpoint : cmos2_data[5] (port) -Endpoint : u_ov5640/cmos2_d_d0[5]/opit_0/D +Startpoint : cmos2_href (port) +Endpoint : u_ov5640/cmos2_href_d0/opit_0/D Path Group : cmos2_pclk Path Type : max (slow corner) Path Class : sequential timing path -Clock Skew : 5.551 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.551 +Clock Skew : 5.595 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 5.595 Launch Clock Delay : 0.000 Clock Pessimism Removal : 0.000 @@ -713,16 +724,20 @@ Clock Skew : 5.551 (Capture Clock Delay - Launch Clock Delay + Clock Pessim Clock cmos2_pclk (rising edge) 0.000 0.000 r Input external delay 1.000 1.000 f - AB8 0.000 1.000 f cmos2_data[5] (port) - net (fanout=1) 0.084 1.084 cmos2_data[5] - IOBS_TB_116_0/DIN td 1.513 2.597 f cmos2_data_ibuf[5]/opit_0/O - net (fanout=1) 0.000 2.597 cmos2_data_ibuf[5]/ntD - IOL_119_5/RX_DATA_DD td 0.127 2.724 f cmos2_data_ibuf[5]/opit_1/OUT - net (fanout=1) 9.489 12.213 nt_cmos2_data[5] - CLMA_134_40/M0 f u_ov5640/cmos2_d_d0[5]/opit_0/D + AB5 0.000 1.000 f cmos2_href (port) + net (fanout=1) 0.093 1.093 cmos2_href + IOBS_TB_32_0/DIN td 1.367 2.460 f cmos2_href_ibuf/opit_0/O + net (fanout=1) 0.000 2.460 cmos2_href_ibuf/ntD + IOL_35_5/RX_DATA_DD td 0.127 2.587 f cmos2_href_ibuf/opit_1/OUT + net (fanout=1) 0.780 3.367 nt_cmos2_href + CLMA_18_12/Y6AB td 0.132 3.499 f CLKROUTE_2/Z + net (fanout=1) 4.461 7.960 ntR3942 + CLMA_18_80/Y6CD td 0.134 8.094 f CLKROUTE_1/Z + net (fanout=1) 4.777 12.871 ntR3941 + CLMS_78_21/CD f u_ov5640/cmos2_href_d0/opit_0/D - Data arrival time 12.213 Logic Levels: 2 - Logic: 1.640ns(14.626%), Route: 9.573ns(85.374%) + Data arrival time 12.871 Logic Levels: 4 + Logic: 1.760ns(14.826%), Route: 10.111ns(85.174%) ---------------------------------------------------------------------------------------------------- Clock cmos2_pclk (rising edge) 11.900 11.900 r @@ -731,34 +746,34 @@ Clock Skew : 5.551 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOBD_37_0/DIN td 1.047 13.018 r cmos2_pclk_ibuf/opit_0/O net (fanout=1) 0.000 13.018 cmos2_pclk_ibuf/ntD IOL_39_6/RX_DATA_DD td 0.082 13.100 r cmos2_pclk_ibuf/opit_1/OUT - net (fanout=1) 2.820 15.920 nt_cmos2_pclk - USCM_84_118/CLK_USCM td 0.000 15.920 r clkbufg_6/gopclkbufg/CLKOUT - net (fanout=118) 1.531 17.451 ntclkbufg_6 - CLMA_134_40/CLK r u_ov5640/cmos2_d_d0[5]/opit_0/CLK - clock pessimism 0.000 17.451 - clock uncertainty -0.250 17.201 + net (fanout=1) 2.817 15.917 nt_cmos2_pclk + USCM_84_119/CLK_USCM td 0.000 15.917 r clkbufg_7/gopclkbufg/CLKOUT + net (fanout=118) 1.578 17.495 ntclkbufg_7 + CLMS_78_21/CLK r u_ov5640/cmos2_href_d0/opit_0/CLK + clock pessimism 0.000 17.495 + clock uncertainty -0.250 17.245 - Setup time -0.088 17.113 + Setup time 0.029 17.274 - Data required time 17.113 + Data required time 17.274 ---------------------------------------------------------------------------------------------------- - Data required time 17.113 - Data arrival time 12.213 + Data required time 17.274 + Data arrival time 12.871 ---------------------------------------------------------------------------------------------------- - Slack (MET) 4.900 + Slack (MET) 4.403 ==================================================================================================== ==================================================================================================== -Startpoint : u_ov5640/cmos2_8_16bit/image_data_valid0/opit_0_L5Q_perm/CLK -Endpoint : u_ov5640/u_mix_image/cnt1_w[0]/opit_0_L5Q/CE +Startpoint : u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/CLK +Endpoint : u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L3 Path Group : cmos2_pclk Path Type : min (slow corner) Path Class : sequential timing path -Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 6.202 - Launch Clock Delay : 5.551 - Clock Pessimism Removal : -0.615 +Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 6.200 + Launch Clock Delay : 5.548 + Clock Pessimism Removal : -0.652 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -769,17 +784,17 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOBD_37_0/DIN td 1.047 1.118 r cmos2_pclk_ibuf/opit_0/O net (fanout=1) 0.000 1.118 cmos2_pclk_ibuf/ntD IOL_39_6/RX_DATA_DD td 0.082 1.200 r cmos2_pclk_ibuf/opit_1/OUT - net (fanout=1) 2.820 4.020 nt_cmos2_pclk - USCM_84_118/CLK_USCM td 0.000 4.020 r clkbufg_6/gopclkbufg/CLKOUT - net (fanout=118) 1.531 5.551 ntclkbufg_6 - CLMS_150_41/CLK r u_ov5640/cmos2_8_16bit/image_data_valid0/opit_0_L5Q_perm/CLK + net (fanout=1) 2.817 4.017 nt_cmos2_pclk + USCM_84_119/CLK_USCM td 0.000 4.017 r clkbufg_7/gopclkbufg/CLKOUT + net (fanout=118) 1.531 5.548 ntclkbufg_7 + CLMA_138_41/CLK r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/CLK - CLMS_150_41/Q0 tco 0.222 5.773 f u_ov5640/cmos2_8_16bit/image_data_valid0/opit_0_L5Q_perm/Q - net (fanout=5) 0.209 5.982 u_ov5640/cmos2_href_16bit - CLMA_154_37/CE f u_ov5640/u_mix_image/cnt1_w[0]/opit_0_L5Q/CE + CLMA_138_41/Y2 tco 0.284 5.832 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/Q + net (fanout=3) 0.085 5.917 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2 [10] + CLMA_138_41/A3 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L3 - Data arrival time 5.982 Logic Levels: 0 - Logic: 0.222ns(51.508%), Route: 0.209ns(48.492%) + Data arrival time 5.917 Logic Levels: 0 + Logic: 0.284ns(76.965%), Route: 0.085ns(23.035%) ---------------------------------------------------------------------------------------------------- Clock cmos2_pclk (rising edge) 0.000 0.000 r @@ -788,34 +803,34 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOBD_37_0/DIN td 1.254 1.325 r cmos2_pclk_ibuf/opit_0/O net (fanout=1) 0.000 1.325 cmos2_pclk_ibuf/ntD IOL_39_6/RX_DATA_DD td 0.126 1.451 r cmos2_pclk_ibuf/opit_1/OUT - net (fanout=1) 3.166 4.617 nt_cmos2_pclk - USCM_84_118/CLK_USCM td 0.000 4.617 r clkbufg_6/gopclkbufg/CLKOUT - net (fanout=118) 1.585 6.202 ntclkbufg_6 - CLMA_154_37/CLK r u_ov5640/u_mix_image/cnt1_w[0]/opit_0_L5Q/CLK - clock pessimism -0.615 5.587 - clock uncertainty 0.200 5.787 + net (fanout=1) 3.164 4.615 nt_cmos2_pclk + USCM_84_119/CLK_USCM td 0.000 4.615 r clkbufg_7/gopclkbufg/CLKOUT + net (fanout=118) 1.585 6.200 ntclkbufg_7 + CLMA_138_41/CLK r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK + clock pessimism -0.652 5.548 + clock uncertainty 0.200 5.748 - Hold time -0.220 5.567 + Hold time -0.238 5.510 - Data required time 5.567 + Data required time 5.510 ---------------------------------------------------------------------------------------------------- - Data required time 5.567 - Data arrival time 5.982 + Data required time 5.510 + Data arrival time 5.917 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.415 + Slack (MET) 0.407 ==================================================================================================== ==================================================================================================== -Startpoint : u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK -Endpoint : u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/L2 +Startpoint : u_ov5640/cmos2_8_16bit/image_data_valid0/opit_0_L5Q_perm/CLK +Endpoint : u_ov5640/u_mix_image/cnt1_w[2]/opit_0_A2Q21/CE Path Group : cmos2_pclk Path Type : min (slow corner) Path Class : sequential timing path Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 6.202 - Launch Clock Delay : 5.551 - Clock Pessimism Removal : -0.622 + Capture Clock Delay : 6.200 + Launch Clock Delay : 5.548 + Clock Pessimism Removal : -0.623 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -826,17 +841,17 @@ Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOBD_37_0/DIN td 1.047 1.118 r cmos2_pclk_ibuf/opit_0/O net (fanout=1) 0.000 1.118 cmos2_pclk_ibuf/ntD IOL_39_6/RX_DATA_DD td 0.082 1.200 r cmos2_pclk_ibuf/opit_1/OUT - net (fanout=1) 2.820 4.020 nt_cmos2_pclk - USCM_84_118/CLK_USCM td 0.000 4.020 r clkbufg_6/gopclkbufg/CLKOUT - net (fanout=118) 1.531 5.551 ntclkbufg_6 - CLMA_150_52/CLK r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK + net (fanout=1) 2.817 4.017 nt_cmos2_pclk + USCM_84_119/CLK_USCM td 0.000 4.017 r clkbufg_7/gopclkbufg/CLKOUT + net (fanout=118) 1.531 5.548 ntclkbufg_7 + CLMA_90_20/CLK r u_ov5640/cmos2_8_16bit/image_data_valid0/opit_0_L5Q_perm/CLK - CLMA_150_52/Q3 tco 0.221 5.772 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/Q1 - net (fanout=5) 0.192 5.964 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/wr_addr [7] - CLMS_150_53/C2 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/L2 + CLMA_90_20/Q2 tco 0.224 5.772 f u_ov5640/cmos2_8_16bit/image_data_valid0/opit_0_L5Q_perm/Q + net (fanout=5) 0.210 5.982 u_ov5640/cmos2_href_16bit + CLMA_90_24/CE f u_ov5640/u_mix_image/cnt1_w[2]/opit_0_A2Q21/CE - Data arrival time 5.964 Logic Levels: 0 - Logic: 0.221ns(53.511%), Route: 0.192ns(46.489%) + Data arrival time 5.982 Logic Levels: 0 + Logic: 0.224ns(51.613%), Route: 0.210ns(48.387%) ---------------------------------------------------------------------------------------------------- Clock cmos2_pclk (rising edge) 0.000 0.000 r @@ -845,34 +860,34 @@ Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOBD_37_0/DIN td 1.254 1.325 r cmos2_pclk_ibuf/opit_0/O net (fanout=1) 0.000 1.325 cmos2_pclk_ibuf/ntD IOL_39_6/RX_DATA_DD td 0.126 1.451 r cmos2_pclk_ibuf/opit_1/OUT - net (fanout=1) 3.166 4.617 nt_cmos2_pclk - USCM_84_118/CLK_USCM td 0.000 4.617 r clkbufg_6/gopclkbufg/CLKOUT - net (fanout=118) 1.585 6.202 ntclkbufg_6 - CLMS_150_53/CLK r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/CLK - clock pessimism -0.622 5.580 - clock uncertainty 0.200 5.780 + net (fanout=1) 3.164 4.615 nt_cmos2_pclk + USCM_84_119/CLK_USCM td 0.000 4.615 r clkbufg_7/gopclkbufg/CLKOUT + net (fanout=118) 1.585 6.200 ntclkbufg_7 + CLMA_90_24/CLK r u_ov5640/u_mix_image/cnt1_w[2]/opit_0_A2Q21/CLK + clock pessimism -0.623 5.577 + clock uncertainty 0.200 5.777 - Hold time -0.235 5.545 + Hold time -0.220 5.557 - Data required time 5.545 + Data required time 5.557 ---------------------------------------------------------------------------------------------------- - Data required time 5.545 - Data arrival time 5.964 + Data required time 5.557 + Data arrival time 5.982 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.419 + Slack (MET) 0.425 ==================================================================================================== ==================================================================================================== -Startpoint : u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK -Endpoint : u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm/L2 +Startpoint : u_ov5640/cmos2_8_16bit/image_data_valid0/opit_0_L5Q_perm/CLK +Endpoint : u_ov5640/u_mix_image/cnt1_w[4]/opit_0_A2Q21/CE Path Group : cmos2_pclk Path Type : min (slow corner) Path Class : sequential timing path Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 6.202 - Launch Clock Delay : 5.551 - Clock Pessimism Removal : -0.622 + Capture Clock Delay : 6.200 + Launch Clock Delay : 5.548 + Clock Pessimism Removal : -0.623 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -883,17 +898,17 @@ Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOBD_37_0/DIN td 1.047 1.118 r cmos2_pclk_ibuf/opit_0/O net (fanout=1) 0.000 1.118 cmos2_pclk_ibuf/ntD IOL_39_6/RX_DATA_DD td 0.082 1.200 r cmos2_pclk_ibuf/opit_1/OUT - net (fanout=1) 2.820 4.020 nt_cmos2_pclk - USCM_84_118/CLK_USCM td 0.000 4.020 r clkbufg_6/gopclkbufg/CLKOUT - net (fanout=118) 1.531 5.551 ntclkbufg_6 - CLMA_150_48/CLK r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK + net (fanout=1) 2.817 4.017 nt_cmos2_pclk + USCM_84_119/CLK_USCM td 0.000 4.017 r clkbufg_7/gopclkbufg/CLKOUT + net (fanout=118) 1.531 5.548 ntclkbufg_7 + CLMA_90_20/CLK r u_ov5640/cmos2_8_16bit/image_data_valid0/opit_0_L5Q_perm/CLK - CLMA_150_48/Q1 tco 0.224 5.775 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Q1 - net (fanout=5) 0.194 5.969 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/wr_addr [1] - CLMS_150_49/A2 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm/L2 + CLMA_90_20/Q2 tco 0.224 5.772 f u_ov5640/cmos2_8_16bit/image_data_valid0/opit_0_L5Q_perm/Q + net (fanout=5) 0.210 5.982 u_ov5640/cmos2_href_16bit + CLMA_90_24/CE f u_ov5640/u_mix_image/cnt1_w[4]/opit_0_A2Q21/CE - Data arrival time 5.969 Logic Levels: 0 - Logic: 0.224ns(53.589%), Route: 0.194ns(46.411%) + Data arrival time 5.982 Logic Levels: 0 + Logic: 0.224ns(51.613%), Route: 0.210ns(48.387%) ---------------------------------------------------------------------------------------------------- Clock cmos2_pclk (rising edge) 0.000 0.000 r @@ -902,21 +917,21 @@ Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOBD_37_0/DIN td 1.254 1.325 r cmos2_pclk_ibuf/opit_0/O net (fanout=1) 0.000 1.325 cmos2_pclk_ibuf/ntD IOL_39_6/RX_DATA_DD td 0.126 1.451 r cmos2_pclk_ibuf/opit_1/OUT - net (fanout=1) 3.166 4.617 nt_cmos2_pclk - USCM_84_118/CLK_USCM td 0.000 4.617 r clkbufg_6/gopclkbufg/CLKOUT - net (fanout=118) 1.585 6.202 ntclkbufg_6 - CLMS_150_49/CLK r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm/CLK - clock pessimism -0.622 5.580 - clock uncertainty 0.200 5.780 + net (fanout=1) 3.164 4.615 nt_cmos2_pclk + USCM_84_119/CLK_USCM td 0.000 4.615 r clkbufg_7/gopclkbufg/CLKOUT + net (fanout=118) 1.585 6.200 ntclkbufg_7 + CLMA_90_24/CLK r u_ov5640/u_mix_image/cnt1_w[4]/opit_0_A2Q21/CLK + clock pessimism -0.623 5.577 + clock uncertainty 0.200 5.777 - Hold time -0.235 5.545 + Hold time -0.220 5.557 - Data required time 5.545 + Data required time 5.557 ---------------------------------------------------------------------------------------------------- - Data required time 5.545 - Data arrival time 5.969 + Data required time 5.557 + Data arrival time 5.982 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.424 + Slack (MET) 0.425 ==================================================================================================== ==================================================================================================== @@ -941,28 +956,28 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi net (fanout=1) 0.000 2.244 hdmi_in_clk_ibuf/ntD IOL_163_6/INCK td 0.076 2.320 r hdmi_in_clk_ibuf/opit_1/INCK net (fanout=1) 2.530 4.850 _N37 - USCM_84_111/CLK_USCM td 0.000 4.850 r clkbufg_4/gopclkbufg/CLKOUT - net (fanout=167) 1.585 6.435 ntclkbufg_4 - CLMA_146_68/CLK r u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK - - CLMA_146_68/Q0 tco 0.287 6.722 f u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/Q - net (fanout=4) 1.542 8.264 wr1_data_in_valid - td 0.288 8.552 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Cout - net (fanout=1) 0.000 8.552 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16001 - CLMA_70_96/Y3 td 0.501 9.053 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/Y1 - net (fanout=3) 0.417 9.470 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2 [3] - CLMA_66_88/Y2 td 0.487 9.957 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm/Z - net (fanout=1) 0.455 10.412 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wwptr [3] - td 0.474 10.886 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_0/gateop_A2/Cout - net (fanout=1) 0.000 10.886 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.co [2] - CLMA_66_100/COUT td 0.058 10.944 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_2/gateop_A2/Cout - net (fanout=1) 0.000 10.944 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.co [6] - CLMA_66_104/Y1 td 0.498 11.442 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_4/gateop_A2/Y1 - net (fanout=1) 0.120 11.562 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158 - CLMA_66_104/C4 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L4 - - Data arrival time 11.562 Logic Levels: 4 - Logic: 2.593ns(50.575%), Route: 2.534ns(49.425%) + USCM_84_111/CLK_USCM td 0.000 4.850 r clkbufg_5/gopclkbufg/CLKOUT + net (fanout=167) 1.585 6.435 ntclkbufg_5 + CLMA_110_85/CLK r u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK + + CLMA_110_85/Q0 tco 0.289 6.724 r u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/Q + net (fanout=4) 0.769 7.493 wr1_data_in_valid + td 0.288 7.781 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Cout + net (fanout=1) 0.000 7.781 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15959 + CLMA_90_101/COUT td 0.058 7.839 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/Cout + net (fanout=1) 0.000 7.839 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15961 + CLMA_90_105/Y1 td 0.498 8.337 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/Y1 + net (fanout=3) 0.658 8.995 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2 [5] + CLMS_74_105/Y3 td 0.210 9.205 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[5]_1/gateop_perm/Z + net (fanout=1) 0.517 9.722 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N109251 + CLMA_90_100/COUT td 0.511 10.233 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_2/gateop_A2/Cout + net (fanout=1) 0.000 10.233 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.co [6] + CLMA_90_104/Y1 td 0.498 10.731 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_4/gateop_A2/Y1 + net (fanout=1) 0.122 10.853 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158 + CLMA_90_104/C4 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L4 + + Data arrival time 10.853 Logic Levels: 5 + Logic: 2.352ns(53.237%), Route: 2.066ns(46.763%) ---------------------------------------------------------------------------------------------------- Clock hdmi_in_clk (rising edge) 6.666 6.666 r @@ -972,9 +987,9 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi net (fanout=1) 0.000 8.552 hdmi_in_clk_ibuf/ntD IOL_163_6/INCK td 0.048 8.600 r hdmi_in_clk_ibuf/opit_1/INCK net (fanout=1) 2.486 11.086 _N37 - USCM_84_111/CLK_USCM td 0.000 11.086 r clkbufg_4/gopclkbufg/CLKOUT - net (fanout=167) 1.531 12.617 ntclkbufg_4 - CLMA_66_104/CLK r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK + USCM_84_111/CLK_USCM td 0.000 11.086 r clkbufg_5/gopclkbufg/CLKOUT + net (fanout=167) 1.531 12.617 ntclkbufg_5 + CLMA_90_104/CLK r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK clock pessimism 0.448 13.065 clock uncertainty -0.250 12.815 @@ -983,15 +998,15 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi Data required time 12.692 ---------------------------------------------------------------------------------------------------- Data required time 12.692 - Data arrival time 11.562 + Data arrival time 10.853 ---------------------------------------------------------------------------------------------------- - Slack (MET) 1.130 + Slack (MET) 1.839 ==================================================================================================== ==================================================================================================== Startpoint : u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK -Endpoint : u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L0 +Endpoint : u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/L2 Path Group : hdmi_in_clk Path Type : max (slow corner) Path Class : sequential timing path @@ -1010,28 +1025,24 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi net (fanout=1) 0.000 2.244 hdmi_in_clk_ibuf/ntD IOL_163_6/INCK td 0.076 2.320 r hdmi_in_clk_ibuf/opit_1/INCK net (fanout=1) 2.530 4.850 _N37 - USCM_84_111/CLK_USCM td 0.000 4.850 r clkbufg_4/gopclkbufg/CLKOUT - net (fanout=167) 1.585 6.435 ntclkbufg_4 - CLMA_146_68/CLK r u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK - - CLMA_146_68/Q0 tco 0.287 6.722 f u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/Q - net (fanout=4) 1.542 8.264 wr1_data_in_valid - td 0.288 8.552 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Cout - net (fanout=1) 0.000 8.552 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16001 - CLMA_70_96/COUT td 0.058 8.610 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/Cout - net (fanout=1) 0.000 8.610 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16003 - td 0.058 8.668 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/Cout - net (fanout=1) 0.000 8.668 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16005 - CLMA_70_100/COUT td 0.058 8.726 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/Cout - net (fanout=1) 0.000 8.726 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16007 - td 0.058 8.784 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/Cout - net (fanout=1) 0.000 8.784 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16009 - CLMA_70_104/Y3 td 0.501 9.285 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_A2Q21/Y1 - net (fanout=3) 0.413 9.698 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2 [11] - CLMA_66_104/C0 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L0 - - Data arrival time 9.698 Logic Levels: 3 - Logic: 1.308ns(40.086%), Route: 1.955ns(59.914%) + USCM_84_111/CLK_USCM td 0.000 4.850 r clkbufg_5/gopclkbufg/CLKOUT + net (fanout=167) 1.585 6.435 ntclkbufg_5 + CLMA_110_85/CLK r u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK + + CLMA_110_85/Q0 tco 0.289 6.724 r u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/Q + net (fanout=4) 0.769 7.493 wr1_data_in_valid + td 0.288 7.781 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Cout + net (fanout=1) 0.000 7.781 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15959 + CLMA_90_101/COUT td 0.058 7.839 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/Cout + net (fanout=1) 0.000 7.839 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15961 + td 0.058 7.897 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/Cout + net (fanout=1) 0.000 7.897 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15963 + CLMA_90_105/Y2 td 0.271 8.168 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/Y0 + net (fanout=3) 0.734 8.902 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2 [6] + CLMA_90_104/D2 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/L2 + + Data arrival time 8.902 Logic Levels: 2 + Logic: 0.964ns(39.076%), Route: 1.503ns(60.924%) ---------------------------------------------------------------------------------------------------- Clock hdmi_in_clk (rising edge) 6.666 6.666 r @@ -1041,26 +1052,26 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi net (fanout=1) 0.000 8.552 hdmi_in_clk_ibuf/ntD IOL_163_6/INCK td 0.048 8.600 r hdmi_in_clk_ibuf/opit_1/INCK net (fanout=1) 2.486 11.086 _N37 - USCM_84_111/CLK_USCM td 0.000 11.086 r clkbufg_4/gopclkbufg/CLKOUT - net (fanout=167) 1.531 12.617 ntclkbufg_4 - CLMA_66_104/CLK r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK + USCM_84_111/CLK_USCM td 0.000 11.086 r clkbufg_5/gopclkbufg/CLKOUT + net (fanout=167) 1.531 12.617 ntclkbufg_5 + CLMA_90_104/CLK r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK clock pessimism 0.448 13.065 clock uncertainty -0.250 12.815 - Setup time -0.196 12.619 + Setup time -0.368 12.447 - Data required time 12.619 + Data required time 12.447 ---------------------------------------------------------------------------------------------------- - Data required time 12.619 - Data arrival time 9.698 + Data required time 12.447 + Data arrival time 8.902 ---------------------------------------------------------------------------------------------------- - Slack (MET) 2.921 + Slack (MET) 3.545 ==================================================================================================== ==================================================================================================== Startpoint : u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK -Endpoint : u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm/L4 +Endpoint : u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L1 Path Group : hdmi_in_clk Path Type : max (slow corner) Path Class : sequential timing path @@ -1079,28 +1090,28 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi net (fanout=1) 0.000 2.244 hdmi_in_clk_ibuf/ntD IOL_163_6/INCK td 0.076 2.320 r hdmi_in_clk_ibuf/opit_1/INCK net (fanout=1) 2.530 4.850 _N37 - USCM_84_111/CLK_USCM td 0.000 4.850 r clkbufg_4/gopclkbufg/CLKOUT - net (fanout=167) 1.585 6.435 ntclkbufg_4 - CLMA_146_68/CLK r u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK - - CLMA_146_68/Q0 tco 0.287 6.722 f u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/Q - net (fanout=4) 1.542 8.264 wr1_data_in_valid - td 0.288 8.552 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Cout - net (fanout=1) 0.000 8.552 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16001 - CLMA_70_96/COUT td 0.058 8.610 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/Cout - net (fanout=1) 0.000 8.610 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16003 - td 0.058 8.668 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/Cout - net (fanout=1) 0.000 8.668 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16005 - CLMA_70_100/COUT td 0.058 8.726 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/Cout - net (fanout=1) 0.000 8.726 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16007 - td 0.058 8.784 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/Cout - net (fanout=1) 0.000 8.784 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16009 - CLMA_70_104/Y3 td 0.501 9.285 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_A2Q21/Y1 - net (fanout=3) 0.413 9.698 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2 [11] - CLMS_66_105/C4 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm/L4 - - Data arrival time 9.698 Logic Levels: 3 - Logic: 1.308ns(40.086%), Route: 1.955ns(59.914%) + USCM_84_111/CLK_USCM td 0.000 4.850 r clkbufg_5/gopclkbufg/CLKOUT + net (fanout=167) 1.585 6.435 ntclkbufg_5 + CLMA_110_85/CLK r u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK + + CLMA_110_85/Q0 tco 0.289 6.724 r u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/Q + net (fanout=4) 0.769 7.493 wr1_data_in_valid + td 0.288 7.781 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Cout + net (fanout=1) 0.000 7.781 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15959 + CLMA_90_101/COUT td 0.058 7.839 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/Cout + net (fanout=1) 0.000 7.839 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15961 + td 0.058 7.897 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/Cout + net (fanout=1) 0.000 7.897 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15963 + CLMA_90_105/COUT td 0.058 7.955 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/Cout + net (fanout=1) 0.000 7.955 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15965 + td 0.058 8.013 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/Cout + net (fanout=1) 0.000 8.013 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15967 + CLMA_90_109/Y3 td 0.501 8.514 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_A2Q21/Y1 + net (fanout=3) 0.410 8.924 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2 [11] + CLMA_90_104/C1 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L1 + + Data arrival time 8.924 Logic Levels: 3 + Logic: 1.310ns(52.632%), Route: 1.179ns(47.368%) ---------------------------------------------------------------------------------------------------- Clock hdmi_in_clk (rising edge) 6.666 6.666 r @@ -1110,26 +1121,26 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi net (fanout=1) 0.000 8.552 hdmi_in_clk_ibuf/ntD IOL_163_6/INCK td 0.048 8.600 r hdmi_in_clk_ibuf/opit_1/INCK net (fanout=1) 2.486 11.086 _N37 - USCM_84_111/CLK_USCM td 0.000 11.086 r clkbufg_4/gopclkbufg/CLKOUT - net (fanout=167) 1.531 12.617 ntclkbufg_4 - CLMS_66_105/CLK r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm/CLK + USCM_84_111/CLK_USCM td 0.000 11.086 r clkbufg_5/gopclkbufg/CLKOUT + net (fanout=167) 1.531 12.617 ntclkbufg_5 + CLMA_90_104/CLK r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK clock pessimism 0.448 13.065 clock uncertainty -0.250 12.815 - Setup time -0.123 12.692 + Setup time -0.234 12.581 - Data required time 12.692 + Data required time 12.581 ---------------------------------------------------------------------------------------------------- - Data required time 12.692 - Data arrival time 9.698 + Data required time 12.581 + Data arrival time 8.924 ---------------------------------------------------------------------------------------------------- - Slack (MET) 2.994 + Slack (MET) 3.657 ==================================================================================================== ==================================================================================================== -Startpoint : u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[2]/opit_0_L5Q_perm/CLK -Endpoint : u_ddr_addr_ctr/u_wr1_addr_ctr/wr_vs_flag/opit_0_L5Q_perm/L0 +Startpoint : u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[2]/opit_0_L5Q_perm/CLK +Endpoint : u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[3]/opit_0_L5Q_perm/L0 Path Group : hdmi_in_clk Path Type : min (slow corner) Path Class : sequential timing path @@ -1148,16 +1159,16 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.000 1.886 hdmi_in_clk_ibuf/ntD IOL_163_6/INCK td 0.048 1.934 r hdmi_in_clk_ibuf/opit_1/INCK net (fanout=1) 2.486 4.420 _N37 - USCM_84_111/CLK_USCM td 0.000 4.420 r clkbufg_4/gopclkbufg/CLKOUT - net (fanout=167) 1.531 5.951 ntclkbufg_4 - CLMA_110_85/CLK r u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[2]/opit_0_L5Q_perm/CLK + USCM_84_111/CLK_USCM td 0.000 4.420 r clkbufg_5/gopclkbufg/CLKOUT + net (fanout=167) 1.531 5.951 ntclkbufg_5 + CLMA_122_92/CLK r u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[2]/opit_0_L5Q_perm/CLK - CLMA_110_85/Q2 tco 0.224 6.175 f u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[2]/opit_0_L5Q_perm/Q - net (fanout=5) 0.088 6.263 u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg [2] - CLMA_110_85/D0 f u_ddr_addr_ctr/u_wr1_addr_ctr/wr_vs_flag/opit_0_L5Q_perm/L0 + CLMA_122_92/Q2 tco 0.224 6.175 f u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[2]/opit_0_L5Q_perm/Q + net (fanout=3) 0.086 6.261 u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt [2] + CLMA_122_92/D0 f u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[3]/opit_0_L5Q_perm/L0 - Data arrival time 6.263 Logic Levels: 0 - Logic: 0.224ns(71.795%), Route: 0.088ns(28.205%) + Data arrival time 6.261 Logic Levels: 0 + Logic: 0.224ns(72.258%), Route: 0.086ns(27.742%) ---------------------------------------------------------------------------------------------------- Clock hdmi_in_clk (rising edge) 0.000 0.000 r @@ -1167,9 +1178,9 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.000 2.244 hdmi_in_clk_ibuf/ntD IOL_163_6/INCK td 0.076 2.320 r hdmi_in_clk_ibuf/opit_1/INCK net (fanout=1) 2.530 4.850 _N37 - USCM_84_111/CLK_USCM td 0.000 4.850 r clkbufg_4/gopclkbufg/CLKOUT - net (fanout=167) 1.585 6.435 ntclkbufg_4 - CLMA_110_85/CLK r u_ddr_addr_ctr/u_wr1_addr_ctr/wr_vs_flag/opit_0_L5Q_perm/CLK + USCM_84_111/CLK_USCM td 0.000 4.850 r clkbufg_5/gopclkbufg/CLKOUT + net (fanout=167) 1.585 6.435 ntclkbufg_5 + CLMA_122_92/CLK r u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[3]/opit_0_L5Q_perm/CLK clock pessimism -0.484 5.951 clock uncertainty 0.200 6.151 @@ -1178,22 +1189,22 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim Data required time 6.072 ---------------------------------------------------------------------------------------------------- Data required time 6.072 - Data arrival time 6.263 + Data arrival time 6.261 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.191 + Slack (MET) 0.189 ==================================================================================================== ==================================================================================================== -Startpoint : u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK -Endpoint : u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm/L0 +Startpoint : u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK +Endpoint : u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/L1 Path Group : hdmi_in_clk Path Type : min (slow corner) Path Class : sequential timing path -Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) +Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) Capture Clock Delay : 6.435 Launch Clock Delay : 5.951 - Clock Pessimism Removal : -0.484 + Clock Pessimism Removal : -0.455 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -1205,16 +1216,16 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.000 1.886 hdmi_in_clk_ibuf/ntD IOL_163_6/INCK td 0.048 1.934 r hdmi_in_clk_ibuf/opit_1/INCK net (fanout=1) 2.486 4.420 _N37 - USCM_84_111/CLK_USCM td 0.000 4.420 r clkbufg_4/gopclkbufg/CLKOUT - net (fanout=167) 1.531 5.951 ntclkbufg_4 - CLMA_66_104/CLK r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK + USCM_84_111/CLK_USCM td 0.000 4.420 r clkbufg_5/gopclkbufg/CLKOUT + net (fanout=167) 1.531 5.951 ntclkbufg_5 + CLMA_90_105/CLK r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK - CLMA_66_104/Q2 tco 0.224 6.175 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/Q - net (fanout=24) 0.100 6.275 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wfull - CLMA_66_104/D0 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm/L0 + CLMA_90_105/Q1 tco 0.224 6.175 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/Q1 + net (fanout=6) 0.089 6.264 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/wr_addr [5] + CLMA_90_104/D1 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/L1 - Data arrival time 6.275 Logic Levels: 0 - Logic: 0.224ns(69.136%), Route: 0.100ns(30.864%) + Data arrival time 6.264 Logic Levels: 0 + Logic: 0.224ns(71.565%), Route: 0.089ns(28.435%) ---------------------------------------------------------------------------------------------------- Clock hdmi_in_clk (rising edge) 0.000 0.000 r @@ -1224,26 +1235,26 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.000 2.244 hdmi_in_clk_ibuf/ntD IOL_163_6/INCK td 0.076 2.320 r hdmi_in_clk_ibuf/opit_1/INCK net (fanout=1) 2.530 4.850 _N37 - USCM_84_111/CLK_USCM td 0.000 4.850 r clkbufg_4/gopclkbufg/CLKOUT - net (fanout=167) 1.585 6.435 ntclkbufg_4 - CLMA_66_104/CLK r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm/CLK - clock pessimism -0.484 5.951 - clock uncertainty 0.200 6.151 + USCM_84_111/CLK_USCM td 0.000 4.850 r clkbufg_5/gopclkbufg/CLKOUT + net (fanout=167) 1.585 6.435 ntclkbufg_5 + CLMA_90_104/CLK r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK + clock pessimism -0.455 5.980 + clock uncertainty 0.200 6.180 - Hold time -0.079 6.072 + Hold time -0.106 6.074 - Data required time 6.072 + Data required time 6.074 ---------------------------------------------------------------------------------------------------- - Data required time 6.072 - Data arrival time 6.275 + Data required time 6.074 + Data arrival time 6.264 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.203 + Slack (MET) 0.190 ==================================================================================================== ==================================================================================================== -Startpoint : u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[0]/opit_0_L5Q_perm/CLK -Endpoint : u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[0]/opit_0_L5Q_perm/L0 +Startpoint : u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[2]/opit_0_L5Q_perm/CLK +Endpoint : u_ddr_addr_ctr/u_wr1_addr_ctr/wr_vs_flag/opit_0_L5Q_perm/L0 Path Group : hdmi_in_clk Path Type : min (slow corner) Path Class : sequential timing path @@ -1262,16 +1273,16 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.000 1.886 hdmi_in_clk_ibuf/ntD IOL_163_6/INCK td 0.048 1.934 r hdmi_in_clk_ibuf/opit_1/INCK net (fanout=1) 2.486 4.420 _N37 - USCM_84_111/CLK_USCM td 0.000 4.420 r clkbufg_4/gopclkbufg/CLKOUT - net (fanout=167) 1.531 5.951 ntclkbufg_4 - CLMA_110_85/CLK r u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[0]/opit_0_L5Q_perm/CLK + USCM_84_111/CLK_USCM td 0.000 4.420 r clkbufg_5/gopclkbufg/CLKOUT + net (fanout=167) 1.531 5.951 ntclkbufg_5 + CLMS_118_93/CLK r u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[2]/opit_0_L5Q_perm/CLK - CLMA_110_85/Q0 tco 0.222 6.173 f u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[0]/opit_0_L5Q_perm/Q - net (fanout=13) 0.090 6.263 u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg [0] - CLMA_110_85/A0 f u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[0]/opit_0_L5Q_perm/L0 + CLMS_118_93/Q2 tco 0.224 6.175 f u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[2]/opit_0_L5Q_perm/Q + net (fanout=5) 0.089 6.264 u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg [2] + CLMS_118_93/D0 f u_ddr_addr_ctr/u_wr1_addr_ctr/wr_vs_flag/opit_0_L5Q_perm/L0 - Data arrival time 6.263 Logic Levels: 0 - Logic: 0.222ns(71.154%), Route: 0.090ns(28.846%) + Data arrival time 6.264 Logic Levels: 0 + Logic: 0.224ns(71.565%), Route: 0.089ns(28.435%) ---------------------------------------------------------------------------------------------------- Clock hdmi_in_clk (rising edge) 0.000 0.000 r @@ -1281,33 +1292,33 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.000 2.244 hdmi_in_clk_ibuf/ntD IOL_163_6/INCK td 0.076 2.320 r hdmi_in_clk_ibuf/opit_1/INCK net (fanout=1) 2.530 4.850 _N37 - USCM_84_111/CLK_USCM td 0.000 4.850 r clkbufg_4/gopclkbufg/CLKOUT - net (fanout=167) 1.585 6.435 ntclkbufg_4 - CLMA_110_85/CLK r u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[0]/opit_0_L5Q_perm/CLK + USCM_84_111/CLK_USCM td 0.000 4.850 r clkbufg_5/gopclkbufg/CLKOUT + net (fanout=167) 1.585 6.435 ntclkbufg_5 + CLMS_118_93/CLK r u_ddr_addr_ctr/u_wr1_addr_ctr/wr_vs_flag/opit_0_L5Q_perm/CLK clock pessimism -0.484 5.951 clock uncertainty 0.200 6.151 - Hold time -0.094 6.057 + Hold time -0.079 6.072 - Data required time 6.057 + Data required time 6.072 ---------------------------------------------------------------------------------------------------- - Data required time 6.057 - Data arrival time 6.263 + Data required time 6.072 + Data arrival time 6.264 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.206 + Slack (MET) 0.192 ==================================================================================================== ==================================================================================================== -Startpoint : udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/CLK -Endpoint : udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[0]/opit_0_L5Q_perm/CE +Startpoint : udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/CLK +Endpoint : udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[4]/opit_0/D Path Group : eth_rxc Path Type : max (slow corner) Path Class : sequential timing path -Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 8.446 - Launch Clock Delay : 10.030 - Clock Pessimism Removal : 1.548 +Clock Skew : -0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 8.567 + Launch Clock Delay : 10.153 + Clock Pessimism Removal : 1.557 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -1322,35 +1333,27 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi IOCKDLY_237_367/CLK_OUT td 3.812 5.846 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT net (fanout=1) 2.599 8.445 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf USCM_84_109/CLK_USCM td 0.000 8.445 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - net (fanout=1861) 1.585 10.030 gmii_clk - CLMA_202_140/CLK r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/CLK - - CLMA_202_140/Q2 tco 0.290 10.320 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/Q - net (fanout=2) 0.494 10.814 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num [2] - td 0.474 11.288 f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_1/gateop_A2/Cout - net (fanout=1) 0.000 11.288 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [2] - CLMA_214_140/COUT td 0.058 11.346 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_3/gateop_A2/Cout - net (fanout=1) 0.000 11.346 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [4] - td 0.058 11.404 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_5/gateop_A2/Cout - net (fanout=1) 0.000 11.404 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [6] - CLMA_214_144/COUT td 0.058 11.462 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_7/gateop_A2/Cout - net (fanout=1) 0.000 11.462 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [8] - td 0.058 11.520 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_9/gateop_A2/Cout - net (fanout=1) 0.000 11.520 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [10] - CLMA_214_148/COUT td 0.058 11.578 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_11/gateop_A2/Cout - net (fanout=1) 0.000 11.578 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [12] - CLMA_214_152/Y0 td 0.269 11.847 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_13/gateop_A2/Y0 - net (fanout=1) 0.713 12.560 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276 [13] - CLMA_210_141/Y3 td 0.612 13.172 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N277.eq_6/gateop_A2/Y1 - net (fanout=18) 0.777 13.949 _N79 - CLMS_186_153/Y2 td 0.487 14.436 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_pkt_done/opit_0_L5Q_perm/Z - net (fanout=1) 0.502 14.938 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N323 - CLMA_194_160/Y1 td 0.316 15.254 f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839/gateop_perm/Z - net (fanout=16) 0.796 16.050 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839 - CLMA_214_136/CE f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[0]/opit_0_L5Q_perm/CE - - Data arrival time 16.050 Logic Levels: 7 - Logic: 2.738ns(45.482%), Route: 3.282ns(54.518%) + net (fanout=1862) 1.708 10.153 gmii_clk + CLMA_194_261/CLK r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/CLK + + CLMA_194_261/Q0 tco 0.289 10.442 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/Q + net (fanout=2) 0.817 11.259 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t [0] + CLMA_182_241/Y1 td 0.288 11.547 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_39/gateop_perm/Z + net (fanout=1) 0.698 12.245 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108159 + CLMA_190_252/Y3 td 0.210 12.455 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_59/gateop_perm/Z + net (fanout=1) 0.559 13.014 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108179 + CLMA_190_240/Y2 td 0.210 13.224 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_63/gateop_perm/Z + net (fanout=2) 0.934 14.158 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446 + CLMA_210_265/Y3 td 0.210 14.368 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N289_6/gateop_perm/Z + net (fanout=6) 0.490 14.858 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108187 + CLMA_198_264/Y3 td 0.210 15.068 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/arp_rx_done/opit_0_L5Q_perm/Z + net (fanout=187) 0.763 15.831 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N319 + CLMA_194_264/Y0 td 0.196 16.027 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[4]/opit_0_L5Q/Z + net (fanout=3) 0.733 16.760 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N642 [4] + CLMA_194_257/M1 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[4]/opit_0/D + + Data arrival time 16.760 Logic Levels: 6 + Logic: 1.613ns(24.414%), Route: 4.994ns(75.586%) ---------------------------------------------------------------------------------------------------- Clock eth_rxc (rising edge) 8.000 8.000 r @@ -1363,32 +1366,32 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi IOCKDLY_237_367/CLK_OUT td 2.574 12.362 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT net (fanout=1) 2.553 14.915 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf USCM_84_109/CLK_USCM td 0.000 14.915 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - net (fanout=1861) 1.531 16.446 gmii_clk - CLMA_214_136/CLK r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[0]/opit_0_L5Q_perm/CLK - clock pessimism 1.548 17.994 - clock uncertainty -0.250 17.744 + net (fanout=1862) 1.652 16.567 gmii_clk + CLMA_194_257/CLK r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[4]/opit_0/CLK + clock pessimism 1.557 18.124 + clock uncertainty -0.250 17.874 - Setup time -0.617 17.127 + Setup time -0.088 17.786 - Data required time 17.127 + Data required time 17.786 ---------------------------------------------------------------------------------------------------- - Data required time 17.127 - Data arrival time 16.050 + Data required time 17.786 + Data arrival time 16.760 ---------------------------------------------------------------------------------------------------- - Slack (MET) 1.077 + Slack (MET) 1.026 ==================================================================================================== ==================================================================================================== -Startpoint : udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/CLK -Endpoint : udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[2]/opit_0_L5Q_perm/CE +Startpoint : udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/CLK +Endpoint : udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[14]/opit_0/CE Path Group : eth_rxc Path Type : max (slow corner) Path Class : sequential timing path Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 8.446 - Launch Clock Delay : 10.030 - Clock Pessimism Removal : 1.548 + Capture Clock Delay : 8.567 + Launch Clock Delay : 10.153 + Clock Pessimism Removal : 1.550 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -1403,35 +1406,29 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi IOCKDLY_237_367/CLK_OUT td 3.812 5.846 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT net (fanout=1) 2.599 8.445 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf USCM_84_109/CLK_USCM td 0.000 8.445 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - net (fanout=1861) 1.585 10.030 gmii_clk - CLMA_202_140/CLK r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/CLK - - CLMA_202_140/Q2 tco 0.290 10.320 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/Q - net (fanout=2) 0.494 10.814 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num [2] - td 0.474 11.288 f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_1/gateop_A2/Cout - net (fanout=1) 0.000 11.288 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [2] - CLMA_214_140/COUT td 0.058 11.346 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_3/gateop_A2/Cout - net (fanout=1) 0.000 11.346 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [4] - td 0.058 11.404 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_5/gateop_A2/Cout - net (fanout=1) 0.000 11.404 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [6] - CLMA_214_144/COUT td 0.058 11.462 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_7/gateop_A2/Cout - net (fanout=1) 0.000 11.462 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [8] - td 0.058 11.520 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_9/gateop_A2/Cout - net (fanout=1) 0.000 11.520 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [10] - CLMA_214_148/COUT td 0.058 11.578 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_11/gateop_A2/Cout - net (fanout=1) 0.000 11.578 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [12] - CLMA_214_152/Y0 td 0.269 11.847 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_13/gateop_A2/Y0 - net (fanout=1) 0.713 12.560 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276 [13] - CLMA_210_141/Y3 td 0.612 13.172 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N277.eq_6/gateop_A2/Y1 - net (fanout=18) 0.777 13.949 _N79 - CLMS_186_153/Y2 td 0.487 14.436 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_pkt_done/opit_0_L5Q_perm/Z - net (fanout=1) 0.502 14.938 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N323 - CLMA_194_160/Y1 td 0.316 15.254 f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839/gateop_perm/Z - net (fanout=16) 0.796 16.050 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839 - CLMA_214_136/CE f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[2]/opit_0_L5Q_perm/CE - - Data arrival time 16.050 Logic Levels: 7 - Logic: 2.738ns(45.482%), Route: 3.282ns(54.518%) + net (fanout=1862) 1.708 10.153 gmii_clk + CLMA_194_261/CLK r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/CLK + + CLMA_194_261/Q0 tco 0.289 10.442 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/Q + net (fanout=2) 0.817 11.259 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t [0] + CLMA_182_241/Y1 td 0.288 11.547 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_39/gateop_perm/Z + net (fanout=1) 0.698 12.245 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108159 + CLMA_190_252/Y3 td 0.210 12.455 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_59/gateop_perm/Z + net (fanout=1) 0.559 13.014 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108179 + CLMA_190_240/Y2 td 0.210 13.224 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_63/gateop_perm/Z + net (fanout=2) 0.934 14.158 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446 + CLMA_210_265/Y3 td 0.210 14.368 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N289_6/gateop_perm/Z + net (fanout=6) 0.490 14.858 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108187 + CLMA_198_264/Y3 td 0.210 15.068 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/arp_rx_done/opit_0_L5Q_perm/Z + net (fanout=187) 0.672 15.740 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N319 + CLMA_202_272/CECO td 0.184 15.924 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[47]/opit_0/CEOUT + net (fanout=1) 0.000 15.924 ntR2081 + CLMA_202_276/CECO td 0.184 16.108 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[42]/opit_0/CEOUT + net (fanout=6) 0.000 16.108 ntR2080 + CLMA_202_280/CECI r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[14]/opit_0/CE + + Data arrival time 16.108 Logic Levels: 7 + Logic: 1.785ns(29.975%), Route: 4.170ns(70.025%) ---------------------------------------------------------------------------------------------------- Clock eth_rxc (rising edge) 8.000 8.000 r @@ -1444,32 +1441,32 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi IOCKDLY_237_367/CLK_OUT td 2.574 12.362 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT net (fanout=1) 2.553 14.915 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf USCM_84_109/CLK_USCM td 0.000 14.915 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - net (fanout=1861) 1.531 16.446 gmii_clk - CLMA_214_136/CLK r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[2]/opit_0_L5Q_perm/CLK - clock pessimism 1.548 17.994 - clock uncertainty -0.250 17.744 + net (fanout=1862) 1.652 16.567 gmii_clk + CLMA_202_280/CLK r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[14]/opit_0/CLK + clock pessimism 1.550 18.117 + clock uncertainty -0.250 17.867 - Setup time -0.617 17.127 + Setup time -0.729 17.138 - Data required time 17.127 + Data required time 17.138 ---------------------------------------------------------------------------------------------------- - Data required time 17.127 - Data arrival time 16.050 + Data required time 17.138 + Data arrival time 16.108 ---------------------------------------------------------------------------------------------------- - Slack (MET) 1.077 + Slack (MET) 1.030 ==================================================================================================== ==================================================================================================== -Startpoint : udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/CLK -Endpoint : udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[5]/opit_0_L5Q_perm/CE +Startpoint : udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/CLK +Endpoint : udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[22]/opit_0/CE Path Group : eth_rxc Path Type : max (slow corner) Path Class : sequential timing path Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 8.446 - Launch Clock Delay : 10.030 - Clock Pessimism Removal : 1.548 + Capture Clock Delay : 8.567 + Launch Clock Delay : 10.153 + Clock Pessimism Removal : 1.550 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -1484,35 +1481,29 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi IOCKDLY_237_367/CLK_OUT td 3.812 5.846 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT net (fanout=1) 2.599 8.445 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf USCM_84_109/CLK_USCM td 0.000 8.445 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - net (fanout=1861) 1.585 10.030 gmii_clk - CLMA_202_140/CLK r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/CLK - - CLMA_202_140/Q2 tco 0.290 10.320 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/Q - net (fanout=2) 0.494 10.814 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num [2] - td 0.474 11.288 f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_1/gateop_A2/Cout - net (fanout=1) 0.000 11.288 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [2] - CLMA_214_140/COUT td 0.058 11.346 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_3/gateop_A2/Cout - net (fanout=1) 0.000 11.346 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [4] - td 0.058 11.404 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_5/gateop_A2/Cout - net (fanout=1) 0.000 11.404 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [6] - CLMA_214_144/COUT td 0.058 11.462 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_7/gateop_A2/Cout - net (fanout=1) 0.000 11.462 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [8] - td 0.058 11.520 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_9/gateop_A2/Cout - net (fanout=1) 0.000 11.520 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [10] - CLMA_214_148/COUT td 0.058 11.578 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_11/gateop_A2/Cout - net (fanout=1) 0.000 11.578 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [12] - CLMA_214_152/Y0 td 0.269 11.847 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_13/gateop_A2/Y0 - net (fanout=1) 0.713 12.560 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276 [13] - CLMA_210_141/Y3 td 0.612 13.172 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N277.eq_6/gateop_A2/Y1 - net (fanout=18) 0.777 13.949 _N79 - CLMS_186_153/Y2 td 0.487 14.436 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_pkt_done/opit_0_L5Q_perm/Z - net (fanout=1) 0.502 14.938 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N323 - CLMA_194_160/Y1 td 0.316 15.254 f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839/gateop_perm/Z - net (fanout=16) 0.796 16.050 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839 - CLMA_214_136/CE f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[5]/opit_0_L5Q_perm/CE - - Data arrival time 16.050 Logic Levels: 7 - Logic: 2.738ns(45.482%), Route: 3.282ns(54.518%) + net (fanout=1862) 1.708 10.153 gmii_clk + CLMA_194_261/CLK r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/CLK + + CLMA_194_261/Q0 tco 0.289 10.442 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/Q + net (fanout=2) 0.817 11.259 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t [0] + CLMA_182_241/Y1 td 0.288 11.547 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_39/gateop_perm/Z + net (fanout=1) 0.698 12.245 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108159 + CLMA_190_252/Y3 td 0.210 12.455 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_59/gateop_perm/Z + net (fanout=1) 0.559 13.014 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108179 + CLMA_190_240/Y2 td 0.210 13.224 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_63/gateop_perm/Z + net (fanout=2) 0.934 14.158 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446 + CLMA_210_265/Y3 td 0.210 14.368 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N289_6/gateop_perm/Z + net (fanout=6) 0.490 14.858 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108187 + CLMA_198_264/Y3 td 0.210 15.068 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/arp_rx_done/opit_0_L5Q_perm/Z + net (fanout=187) 0.672 15.740 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N319 + CLMA_202_272/CECO td 0.184 15.924 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[47]/opit_0/CEOUT + net (fanout=1) 0.000 15.924 ntR2081 + CLMA_202_276/CECO td 0.184 16.108 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[42]/opit_0/CEOUT + net (fanout=6) 0.000 16.108 ntR2080 + CLMA_202_280/CECI r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[22]/opit_0/CE + + Data arrival time 16.108 Logic Levels: 7 + Logic: 1.785ns(29.975%), Route: 4.170ns(70.025%) ---------------------------------------------------------------------------------------------------- Clock eth_rxc (rising edge) 8.000 8.000 r @@ -1525,32 +1516,32 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi IOCKDLY_237_367/CLK_OUT td 2.574 12.362 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT net (fanout=1) 2.553 14.915 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf USCM_84_109/CLK_USCM td 0.000 14.915 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - net (fanout=1861) 1.531 16.446 gmii_clk - CLMA_214_136/CLK r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[5]/opit_0_L5Q_perm/CLK - clock pessimism 1.548 17.994 - clock uncertainty -0.250 17.744 + net (fanout=1862) 1.652 16.567 gmii_clk + CLMA_202_280/CLK r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[22]/opit_0/CLK + clock pessimism 1.550 18.117 + clock uncertainty -0.250 17.867 - Setup time -0.617 17.127 + Setup time -0.729 17.138 - Data required time 17.127 + Data required time 17.138 ---------------------------------------------------------------------------------------------------- - Data required time 17.127 - Data arrival time 16.050 + Data required time 17.138 + Data arrival time 16.108 ---------------------------------------------------------------------------------------------------- - Slack (MET) 1.077 + Slack (MET) 1.030 ==================================================================================================== ==================================================================================================== -Startpoint : udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[3]/opit_0_L5Q_perm/CLK -Endpoint : udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[4]/opit_0_L6Q_perm/A3 +Startpoint : udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[30]/opit_0/CLK +Endpoint : udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][6]/opit_0/D Path Group : eth_rxc Path Type : min (slow corner) Path Class : sequential timing path -Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 10.030 - Launch Clock Delay : 8.446 - Clock Pessimism Removal : -1.584 +Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 10.153 + Launch Clock Delay : 8.567 + Clock Pessimism Removal : -1.550 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -1565,15 +1556,15 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOCKDLY_237_367/CLK_OUT td 2.574 4.362 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT net (fanout=1) 2.553 6.915 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf USCM_84_109/CLK_USCM td 0.000 6.915 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - net (fanout=1861) 1.531 8.446 gmii_clk - CLMS_162_225/CLK r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[3]/opit_0_L5Q_perm/CLK + net (fanout=1862) 1.652 8.567 gmii_clk + CLMA_194_288/CLK r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[30]/opit_0/CLK - CLMS_162_225/Q2 tco 0.224 8.670 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[3]/opit_0_L5Q_perm/Q - net (fanout=5) 0.088 8.758 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg [3] - CLMS_162_225/A3 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[4]/opit_0_L6Q_perm/A3 + CLMA_194_288/Q0 tco 0.222 8.789 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[30]/opit_0/Q + net (fanout=3) 0.224 9.013 udp_osd_inst/eth_udp_inst/des_ip [30] + CLMA_198_288/AD f udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][6]/opit_0/D - Data arrival time 8.758 Logic Levels: 0 - Logic: 0.224ns(71.795%), Route: 0.088ns(28.205%) + Data arrival time 9.013 Logic Levels: 0 + Logic: 0.222ns(49.776%), Route: 0.224ns(50.224%) ---------------------------------------------------------------------------------------------------- Clock eth_rxc (rising edge) 0.000 0.000 r @@ -1586,25 +1577,25 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOCKDLY_237_367/CLK_OUT td 3.812 5.846 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT net (fanout=1) 2.599 8.445 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf USCM_84_109/CLK_USCM td 0.000 8.445 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - net (fanout=1861) 1.585 10.030 gmii_clk - CLMS_162_225/CLK r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[4]/opit_0_L6Q_perm/CLK - clock pessimism -1.584 8.446 - clock uncertainty 0.200 8.646 + net (fanout=1862) 1.708 10.153 gmii_clk + CLMA_198_288/CLK r udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][6]/opit_0/CLK + clock pessimism -1.550 8.603 + clock uncertainty 0.200 8.803 - Hold time -0.269 8.377 + Hold time 0.053 8.856 - Data required time 8.377 + Data required time 8.856 ---------------------------------------------------------------------------------------------------- - Data required time 8.377 - Data arrival time 8.758 + Data required time 8.856 + Data arrival time 9.013 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.381 + Slack (MET) 0.157 ==================================================================================================== ==================================================================================================== -Startpoint : udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[12]/opit_0/CLK -Endpoint : udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[14]/opit_0_A2Q21/Cin +Startpoint : param_manager_inst/param_offsetX/cnt[3]/opit_0_L5Q_perm/CLK +Endpoint : param_manager_inst/param_offsetX/cnt[6]/opit_0_A2Q21/Cin Path Group : eth_rxc Path Type : min (slow corner) Path Class : sequential timing path @@ -1626,17 +1617,17 @@ Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOCKDLY_237_367/CLK_OUT td 2.574 4.362 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT net (fanout=1) 2.553 6.915 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf USCM_84_109/CLK_USCM td 0.000 6.915 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - net (fanout=1861) 1.531 8.446 gmii_clk - CLMS_186_213/CLK r udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[12]/opit_0/CLK + net (fanout=1862) 1.531 8.446 gmii_clk + CLMA_250_212/CLK r param_manager_inst/param_offsetX/cnt[3]/opit_0_L5Q_perm/CLK - CLMS_186_213/Q3 tco 0.221 8.667 f udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[12]/opit_0/Q - net (fanout=2) 0.187 8.854 udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length [12] - td 0.136 8.990 f udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[12]/opit_0_A2Q21/Cout - net (fanout=1) 0.000 8.990 udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N168_1.co [10] - f udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[14]/opit_0_A2Q21/Cin + CLMA_250_212/Q3 tco 0.221 8.667 f param_manager_inst/param_offsetX/cnt[3]/opit_0_L5Q_perm/Q + net (fanout=3) 0.188 8.855 param_manager_inst/param_offsetX/cnt [3] + CLMA_250_213/COUT td 0.118 8.973 r param_manager_inst/param_offsetX/N26_1.fsub_3/gateop_A2/Cout + net (fanout=1) 0.000 8.973 param_manager_inst/param_offsetX/N26_1.co [4] + CLMA_250_217/CIN r param_manager_inst/param_offsetX/cnt[6]/opit_0_A2Q21/Cin - Data arrival time 8.990 Logic Levels: 0 - Logic: 0.357ns(65.625%), Route: 0.187ns(34.375%) + Data arrival time 8.973 Logic Levels: 1 + Logic: 0.339ns(64.326%), Route: 0.188ns(35.674%) ---------------------------------------------------------------------------------------------------- Clock eth_rxc (rising edge) 0.000 0.000 r @@ -1649,32 +1640,32 @@ Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOCKDLY_237_367/CLK_OUT td 3.812 5.846 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT net (fanout=1) 2.599 8.445 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf USCM_84_109/CLK_USCM td 0.000 8.445 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - net (fanout=1861) 1.585 10.030 gmii_clk - CLMA_186_212/CLK r udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[14]/opit_0_A2Q21/CLK + net (fanout=1862) 1.585 10.030 gmii_clk + CLMA_250_217/CLK r param_manager_inst/param_offsetX/cnt[6]/opit_0_A2Q21/CLK clock pessimism -1.555 8.475 clock uncertainty 0.200 8.675 - Hold time -0.071 8.604 + Hold time -0.085 8.590 - Data required time 8.604 + Data required time 8.590 ---------------------------------------------------------------------------------------------------- - Data required time 8.604 - Data arrival time 8.990 + Data required time 8.590 + Data arrival time 8.973 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.386 + Slack (MET) 0.383 ==================================================================================================== ==================================================================================================== -Startpoint : param_manager_inst/modify_H_flags_ff1/opit_0/CLK -Endpoint : param_manager_inst/modify_H_load/opit_0_L5Q_perm/L2 +Startpoint : udp_wr_mem_inst/data_count[1]/opit_0_L5Q_perm/CLK +Endpoint : udp_wr_mem_inst/data_count[4]/opit_0_A2Q21/Cin Path Group : eth_rxc Path Type : min (slow corner) Path Class : sequential timing path -Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) +Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) Capture Clock Delay : 10.030 Launch Clock Delay : 8.446 - Clock Pessimism Removal : -1.584 + Clock Pessimism Removal : -1.555 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -1689,15 +1680,17 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOCKDLY_237_367/CLK_OUT td 2.574 4.362 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT net (fanout=1) 2.553 6.915 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf USCM_84_109/CLK_USCM td 0.000 6.915 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - net (fanout=1861) 1.531 8.446 gmii_clk - CLMS_214_137/CLK r param_manager_inst/modify_H_flags_ff1/opit_0/CLK + net (fanout=1862) 1.531 8.446 gmii_clk + CLMA_198_224/CLK r udp_wr_mem_inst/data_count[1]/opit_0_L5Q_perm/CLK - CLMS_214_137/Y2 tco 0.284 8.730 f param_manager_inst/modify_H_flags_ff1/opit_0/Q - net (fanout=1) 0.086 8.816 param_manager_inst/modify_H_flags_ff1 - CLMS_214_137/B2 f param_manager_inst/modify_H_load/opit_0_L5Q_perm/L2 + CLMA_198_224/Q0 tco 0.222 8.668 f udp_wr_mem_inst/data_count[1]/opit_0_L5Q_perm/Q + net (fanout=3) 0.086 8.754 udp_wr_mem_inst/data_count [1] + td 0.236 8.990 r udp_wr_mem_inst/N30_1.fsub_1/gateop_A2/Cout + net (fanout=1) 0.000 8.990 udp_wr_mem_inst/N30_1.co [2] + r udp_wr_mem_inst/data_count[4]/opit_0_A2Q21/Cin - Data arrival time 8.816 Logic Levels: 0 - Logic: 0.284ns(76.757%), Route: 0.086ns(23.243%) + Data arrival time 8.990 Logic Levels: 0 + Logic: 0.458ns(84.191%), Route: 0.086ns(15.809%) ---------------------------------------------------------------------------------------------------- Clock eth_rxc (rising edge) 0.000 0.000 r @@ -1710,19 +1703,19 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOCKDLY_237_367/CLK_OUT td 3.812 5.846 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT net (fanout=1) 2.599 8.445 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf USCM_84_109/CLK_USCM td 0.000 8.445 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - net (fanout=1861) 1.585 10.030 gmii_clk - CLMS_214_137/CLK r param_manager_inst/modify_H_load/opit_0_L5Q_perm/CLK - clock pessimism -1.584 8.446 - clock uncertainty 0.200 8.646 + net (fanout=1862) 1.585 10.030 gmii_clk + CLMS_198_225/CLK r udp_wr_mem_inst/data_count[4]/opit_0_A2Q21/CLK + clock pessimism -1.555 8.475 + clock uncertainty 0.200 8.675 - Hold time -0.221 8.425 + Hold time -0.082 8.593 - Data required time 8.425 + Data required time 8.593 ---------------------------------------------------------------------------------------------------- - Data required time 8.425 - Data arrival time 8.816 + Data required time 8.593 + Data arrival time 8.990 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.391 + Slack (MET) 0.397 ==================================================================================================== ==================================================================================================== @@ -1732,9 +1725,9 @@ Endpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctr Path Group : clk_50m Path Type : max (slow corner) Path Class : sequential timing path -Clock Skew : -0.093 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.378 - Launch Clock Delay : 5.930 +Clock Skew : -0.058 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 5.392 + Launch Clock Delay : 5.909 Clock Pessimism Removal : 0.459 Location Delay Type Incr Path Logical Resource @@ -1750,29 +1743,29 @@ Clock Skew : -0.093 (Capture Clock Delay - Launch Clock Delay + Clock Pessi PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 1.078 4.288 rd3_clk USCM_84_108/CLK_USCM td 0.000 4.288 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 1.642 5.930 ntclkbufg_1 - DRM_82_4/CLKB[0] r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB - - DRM_82_4/QB0[0] tco 2.307 8.237 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/DOB[0] - net (fanout=6) 1.382 9.619 u_rotate_image/dout [0] - CLMS_74_73/Y1 td 0.197 9.816 f u_rotate_image/addr_fifo_valid/opit_0_L5Q_perm/Z - net (fanout=3) 1.147 10.963 u_rotate_image/addr_fifo_rd_en - td 0.288 11.251 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/Cout - net (fanout=1) 0.000 11.251 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16637 - CLMS_78_9/Y3 td 0.501 11.752 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/Y1 - net (fanout=1) 0.401 12.153 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11 [3] - CLMS_74_13/Y3 td 0.210 12.363 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[3]/gateop_perm/Z - net (fanout=3) 0.766 13.129 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/rrptr [3] - td 0.477 13.606 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_0/gateop_A2/Cout - net (fanout=1) 0.000 13.606 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.co [2] - CLMA_90_20/COUT td 0.058 13.664 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_2/gateop_A2/Cout - net (fanout=1) 0.000 13.664 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.co [6] - CLMA_90_24/Y1 td 0.498 14.162 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_4/gateop_A2/Y1 - net (fanout=1) 0.547 14.709 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21 - CLMA_94_16/C4 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/L4 - - Data arrival time 14.709 Logic Levels: 5 - Logic: 4.536ns(51.669%), Route: 4.243ns(48.331%) + net (fanout=2516) 1.621 5.909 ntclkbufg_1 + DRM_54_24/CLKB[0] r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB + + DRM_54_24/QB0[0] tco 2.307 8.216 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/DOB[0] + net (fanout=6) 1.422 9.638 u_rotate_image/dout [0] + CLMS_74_117/Y1 td 0.466 10.104 f u_rotate_image/addr_fifo_valid/opit_0_L5Q_perm/Z + net (fanout=3) 1.540 11.644 u_rotate_image/addr_fifo_rd_en + td 0.288 11.932 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/Cout + net (fanout=1) 0.000 11.932 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16576 + CLMS_50_33/COUT td 0.058 11.990 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/Cout + net (fanout=1) 0.000 11.990 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16578 + CLMS_50_37/Y1 td 0.498 12.488 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/Y1 + net (fanout=1) 0.527 13.015 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11 [5] + CLMA_58_29/Y1 td 0.468 13.483 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[5]/gateop_perm/Z + net (fanout=3) 0.612 14.095 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/rrptr [5] + CLMA_58_36/COUT td 0.511 14.606 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_2/gateop_A2/Cout + net (fanout=1) 0.000 14.606 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.co [6] + CLMA_58_40/Y1 td 0.498 15.104 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_4/gateop_A2/Y1 + net (fanout=1) 0.120 15.224 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21 + CLMA_58_40/C4 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/L4 + + Data arrival time 15.224 Logic Levels: 6 + Logic: 5.094ns(54.686%), Route: 4.221ns(45.314%) ---------------------------------------------------------------------------------------------------- Clock clk_50m (rising edge) 20.000 20.000 r @@ -1785,31 +1778,31 @@ Clock Skew : -0.093 (Capture Clock Delay - Launch Clock Delay + Clock Pessi PLL_158_55/CLK_OUT0 td 0.100 22.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 1.059 23.847 rd3_clk USCM_84_108/CLK_USCM td 0.000 23.847 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 1.531 25.378 ntclkbufg_1 - CLMA_94_16/CLK r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK - clock pessimism 0.459 25.837 - clock uncertainty -0.150 25.687 + net (fanout=2516) 1.545 25.392 ntclkbufg_1 + CLMA_58_40/CLK r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK + clock pessimism 0.459 25.851 + clock uncertainty -0.150 25.701 - Setup time -0.123 25.564 + Setup time -0.123 25.578 - Data required time 25.564 + Data required time 25.578 ---------------------------------------------------------------------------------------------------- - Data required time 25.564 - Data arrival time 14.709 + Data required time 25.578 + Data arrival time 15.224 ---------------------------------------------------------------------------------------------------- - Slack (MET) 10.855 + Slack (MET) 10.354 ==================================================================================================== ==================================================================================================== Startpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB -Endpoint : u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/L4 +Endpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/Cin Path Group : clk_50m Path Type : max (slow corner) Path Class : sequential timing path -Clock Skew : -0.093 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.378 - Launch Clock Delay : 5.930 +Clock Skew : -0.061 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 5.389 + Launch Clock Delay : 5.909 Clock Pessimism Removal : 0.459 Location Delay Type Incr Path Logical Resource @@ -1825,29 +1818,27 @@ Clock Skew : -0.093 (Capture Clock Delay - Launch Clock Delay + Clock Pessi PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 1.078 4.288 rd3_clk USCM_84_108/CLK_USCM td 0.000 4.288 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 1.642 5.930 ntclkbufg_1 - DRM_82_4/CLKB[0] r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB - - DRM_82_4/QB0[0] tco 2.307 8.237 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/DOB[0] - net (fanout=6) 1.130 9.367 u_rotate_image/dout [0] - CLMS_74_73/Y3 td 0.465 9.832 f u_rotate_image/fifo_data_valid/opit_0_L5Q_perm/Z - net (fanout=3) 0.774 10.606 u_rotate_image/N170 - td 0.288 10.894 f u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/Cout - net (fanout=1) 0.000 10.894 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16662 - CLMA_58_92/Y3 td 0.501 11.395 r u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/Y1 - net (fanout=1) 0.268 11.663 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11 [3] - CLMA_58_89/Y3 td 0.459 12.122 r u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[3]/gateop_perm/Z - net (fanout=1) 0.735 12.857 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/rrptr [3] - td 0.477 13.334 f u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N24.eq_0/gateop_A2/Cout - net (fanout=1) 0.000 13.334 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N24.co [2] - CLMS_50_93/COUT td 0.058 13.392 r u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N24.eq_2/gateop_A2/Cout - net (fanout=1) 0.000 13.392 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N24.co [6] - CLMS_50_97/Y0 td 0.159 13.551 r u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/Y0 - net (fanout=1) 0.257 13.808 _N70 - CLMS_50_97/C4 r u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/L4 - - Data arrival time 13.808 Logic Levels: 5 - Logic: 4.714ns(59.838%), Route: 3.164ns(40.162%) + net (fanout=2516) 1.621 5.909 ntclkbufg_1 + DRM_54_24/CLKB[0] r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB + + DRM_54_24/QB0[0] tco 2.307 8.216 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/DOB[0] + net (fanout=6) 1.422 9.638 u_rotate_image/dout [0] + CLMS_74_117/Y1 td 0.466 10.104 f u_rotate_image/addr_fifo_valid/opit_0_L5Q_perm/Z + net (fanout=3) 1.540 11.644 u_rotate_image/addr_fifo_rd_en + td 0.288 11.932 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/Cout + net (fanout=1) 0.000 11.932 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16576 + CLMS_50_33/COUT td 0.058 11.990 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/Cout + net (fanout=1) 0.000 11.990 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16578 + CLMS_50_37/Y1 td 0.498 12.488 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/Y1 + net (fanout=1) 0.527 13.015 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11 [5] + CLMA_58_29/Y1 td 0.468 13.483 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[5]/gateop_perm/Z + net (fanout=3) 0.405 13.888 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/rrptr [5] + CLMA_62_32/COUT td 0.511 14.399 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N24.eq_2/gateop_A2/Cout + net (fanout=1) 0.000 14.399 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N24.co [6] + CLMA_62_36/CIN r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/Cin + + Data arrival time 14.399 Logic Levels: 5 + Logic: 4.596ns(54.134%), Route: 3.894ns(45.866%) ---------------------------------------------------------------------------------------------------- Clock clk_50m (rising edge) 20.000 20.000 r @@ -1860,32 +1851,32 @@ Clock Skew : -0.093 (Capture Clock Delay - Launch Clock Delay + Clock Pessi PLL_158_55/CLK_OUT0 td 0.100 22.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 1.059 23.847 rd3_clk USCM_84_108/CLK_USCM td 0.000 23.847 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 1.531 25.378 ntclkbufg_1 - CLMS_50_97/CLK r u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK - clock pessimism 0.459 25.837 - clock uncertainty -0.150 25.687 + net (fanout=2516) 1.542 25.389 ntclkbufg_1 + CLMA_62_36/CLK r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/CLK + clock pessimism 0.459 25.848 + clock uncertainty -0.150 25.698 - Setup time -0.123 25.564 + Setup time -0.357 25.341 - Data required time 25.564 + Data required time 25.341 ---------------------------------------------------------------------------------------------------- - Data required time 25.564 - Data arrival time 13.808 + Data required time 25.341 + Data arrival time 14.399 ---------------------------------------------------------------------------------------------------- - Slack (MET) 11.756 + Slack (MET) 10.942 ==================================================================================================== ==================================================================================================== -Startpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB -Endpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/Cin +Startpoint : image_filiter_inst/multiline_buffer_inst/hor_cnt[4]/opit_0_A2Q21/CLK +Endpoint : image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/L4 Path Group : clk_50m Path Type : max (slow corner) Path Class : sequential timing path -Clock Skew : -0.093 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.378 - Launch Clock Delay : 5.930 - Clock Pessimism Removal : 0.459 +Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 5.499 + Launch Clock Delay : 5.996 + Clock Pessimism Removal : 0.461 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -1900,29 +1891,37 @@ Clock Skew : -0.093 (Capture Clock Delay - Launch Clock Delay + Clock Pessi PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 1.078 4.288 rd3_clk USCM_84_108/CLK_USCM td 0.000 4.288 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 1.642 5.930 ntclkbufg_1 - DRM_82_4/CLKB[0] r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB - - DRM_82_4/QB0[0] tco 2.307 8.237 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/DOB[0] - net (fanout=6) 1.382 9.619 u_rotate_image/dout [0] - CLMS_74_73/Y1 td 0.197 9.816 f u_rotate_image/addr_fifo_valid/opit_0_L5Q_perm/Z - net (fanout=3) 1.147 10.963 u_rotate_image/addr_fifo_rd_en - td 0.288 11.251 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/Cout - net (fanout=1) 0.000 11.251 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16637 - CLMS_78_9/COUT td 0.058 11.309 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/Cout - net (fanout=1) 0.000 11.309 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16639 - td 0.058 11.367 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/Cout - net (fanout=1) 0.000 11.367 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16641 - CLMS_78_13/Y3 td 0.501 11.868 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/Y1 - net (fanout=1) 0.395 12.263 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11 [7] - CLMS_74_13/Y1 td 0.212 12.475 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[7]/gateop_perm/Z - net (fanout=3) 0.492 12.967 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/rrptr [7] - CLMA_94_12/COUT td 0.515 13.482 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N24.eq_2/gateop_A2/Cout - net (fanout=1) 0.000 13.482 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N24.co [6] - CLMA_94_16/CIN r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/Cin - - Data arrival time 13.482 Logic Levels: 5 - Logic: 4.136ns(54.767%), Route: 3.416ns(45.233%) + net (fanout=2516) 1.708 5.996 ntclkbufg_1 + CLMA_78_280/CLK r image_filiter_inst/multiline_buffer_inst/hor_cnt[4]/opit_0_A2Q21/CLK + + CLMA_78_280/Q2 tco 0.290 6.286 r image_filiter_inst/multiline_buffer_inst/hor_cnt[4]/opit_0_A2Q21/Q0 + net (fanout=2) 0.417 6.703 image_filiter_inst/multiline_buffer_inst/hor_cnt [3] + CLMA_74_280/Y1 td 0.460 7.163 r image_filiter_inst/multiline_buffer_inst/N229_8/gateop_perm/Z + net (fanout=1) 0.407 7.570 image_filiter_inst/multiline_buffer_inst/_N104607 + CLMS_78_285/Y2 td 0.286 7.856 r image_filiter_inst/multiline_buffer_inst/N229_11/gateop_perm/Z + net (fanout=5) 0.525 8.381 image_filiter_inst/multiline_buffer_inst/N229 + CLMS_94_289/Y2 td 0.487 8.868 r image_filiter_inst/multiline_buffer_inst/N176_7/gateop_perm/Z + net (fanout=1) 0.403 9.271 image_filiter_inst/multiline_buffer_inst/N176 + CLMA_90_284/Y2 td 0.478 9.749 r image_filiter_inst/multiline_buffer_inst/N189[1]_4/gateop_perm/Z + net (fanout=4) 0.839 10.588 image_filiter_inst/multiline_buffer_inst/rd_en [1] + td 0.234 10.822 f image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/Cout + net (fanout=1) 0.000 10.822 image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N14178 + CLMS_78_269/COUT td 0.058 10.880 r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/Cout + net (fanout=1) 0.000 10.880 image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N14180 + td 0.058 10.938 r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/Cout + net (fanout=1) 0.000 10.938 image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N14182 + CLMS_78_273/Y3 td 0.501 11.439 r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/Y1 + net (fanout=1) 0.519 11.958 image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11 [7] + CLMS_94_273/Y3 td 0.465 12.423 f image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[7]/gateop_perm/Z + net (fanout=2) 0.847 13.270 image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/rrptr [7] + CLMA_90_276/COUT td 0.515 13.785 r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N21.eq_2/gateop_A2/Cout + net (fanout=1) 0.000 13.785 image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N21.co [6] + CLMA_90_280/Y1 td 0.498 14.283 r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N21.eq_4/gateop_A2/Y1 + net (fanout=1) 0.447 14.730 image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N21 + CLMA_90_272/C4 r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/L4 + + Data arrival time 14.730 Logic Levels: 9 + Logic: 4.330ns(49.576%), Route: 4.404ns(50.424%) ---------------------------------------------------------------------------------------------------- Clock clk_50m (rising edge) 20.000 20.000 r @@ -1935,30 +1934,30 @@ Clock Skew : -0.093 (Capture Clock Delay - Launch Clock Delay + Clock Pessi PLL_158_55/CLK_OUT0 td 0.100 22.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 1.059 23.847 rd3_clk USCM_84_108/CLK_USCM td 0.000 23.847 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 1.531 25.378 ntclkbufg_1 - CLMA_94_16/CLK r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/CLK - clock pessimism 0.459 25.837 - clock uncertainty -0.150 25.687 + net (fanout=2516) 1.652 25.499 ntclkbufg_1 + CLMA_90_272/CLK r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK + clock pessimism 0.461 25.960 + clock uncertainty -0.150 25.810 - Setup time -0.357 25.330 + Setup time -0.123 25.687 - Data required time 25.330 + Data required time 25.687 ---------------------------------------------------------------------------------------------------- - Data required time 25.330 - Data arrival time 13.482 + Data required time 25.687 + Data arrival time 14.730 ---------------------------------------------------------------------------------------------------- - Slack (MET) 11.848 + Slack (MET) 10.957 ==================================================================================================== ==================================================================================================== -Startpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK -Endpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[8] +Startpoint : u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK +Endpoint : u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[10] Path Group : clk_50m Path Type : min (slow corner) Path Class : sequential timing path -Clock Skew : 0.088 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.925 +Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 5.873 Launch Clock Delay : 5.378 Clock Pessimism Removal : -0.459 @@ -1975,15 +1974,15 @@ Clock Skew : 0.088 (Capture Clock Delay - Launch Clock Delay + Clock Pessim PLL_158_55/CLK_OUT0 td 0.100 2.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 1.059 3.847 rd3_clk USCM_84_108/CLK_USCM td 0.000 3.847 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 1.531 5.378 ntclkbufg_1 - CLMA_90_12/CLK r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK + net (fanout=2516) 1.531 5.378 ntclkbufg_1 + CLMS_50_117/CLK r u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK - CLMA_90_12/Q2 tco 0.224 5.602 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/Q0 - net (fanout=3) 0.256 5.858 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/wr_addr [6] - DRM_82_4/ADA0[8] f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[8] + CLMS_50_117/Q0 tco 0.222 5.600 f u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/Q0 + net (fanout=5) 0.225 5.825 u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/wr_addr [8] + DRM_54_108/ADA0[10] f u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[10] - Data arrival time 5.858 Logic Levels: 0 - Logic: 0.224ns(46.667%), Route: 0.256ns(53.333%) + Data arrival time 5.825 Logic Levels: 0 + Logic: 0.222ns(49.664%), Route: 0.225ns(50.336%) ---------------------------------------------------------------------------------------------------- Clock clk_50m (rising edge) 0.000 0.000 r @@ -1996,31 +1995,31 @@ Clock Skew : 0.088 (Capture Clock Delay - Launch Clock Delay + Clock Pessim PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 1.078 4.288 rd3_clk USCM_84_108/CLK_USCM td 0.000 4.288 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 1.637 5.925 ntclkbufg_1 - DRM_82_4/CLKA[0] r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKA - clock pessimism -0.459 5.466 - clock uncertainty 0.000 5.466 + net (fanout=2516) 1.585 5.873 ntclkbufg_1 + DRM_54_108/CLKA[0] r u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKA + clock pessimism -0.459 5.414 + clock uncertainty 0.000 5.414 - Hold time 0.210 5.676 + Hold time 0.210 5.624 - Data required time 5.676 + Data required time 5.624 ---------------------------------------------------------------------------------------------------- - Data required time 5.676 - Data arrival time 5.858 + Data required time 5.624 + Data arrival time 5.825 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.182 + Slack (MET) 0.201 ==================================================================================================== ==================================================================================================== -Startpoint : u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK -Endpoint : u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/D +Startpoint : u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK +Endpoint : u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/D Path Group : clk_50m Path Type : min (slow corner) Path Class : sequential timing path -Clock Skew : 0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.899 - Launch Clock Delay : 5.403 +Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 5.873 + Launch Clock Delay : 5.378 Clock Pessimism Removal : -0.466 Location Delay Type Incr Path Logical Resource @@ -2036,15 +2035,15 @@ Clock Skew : 0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessim PLL_158_55/CLK_OUT0 td 0.100 2.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 1.059 3.847 rd3_clk USCM_84_108/CLK_USCM td 0.000 3.847 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 1.556 5.403 ntclkbufg_1 - CLMA_58_88/CLK r u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK + net (fanout=2516) 1.531 5.378 ntclkbufg_1 + CLMA_58_108/CLK r u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK - CLMA_58_88/Q3 tco 0.221 5.624 f u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/Q - net (fanout=1) 0.084 5.708 u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr1 [8] - CLMA_58_89/AD f u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/D + CLMA_58_108/Q2 tco 0.224 5.602 f u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/Q + net (fanout=1) 0.084 5.686 u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr1 [2] + CLMA_58_109/CD f u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/D - Data arrival time 5.708 Logic Levels: 0 - Logic: 0.221ns(72.459%), Route: 0.084ns(27.541%) + Data arrival time 5.686 Logic Levels: 0 + Logic: 0.224ns(72.727%), Route: 0.084ns(27.273%) ---------------------------------------------------------------------------------------------------- Clock clk_50m (rising edge) 0.000 0.000 r @@ -2057,32 +2056,32 @@ Clock Skew : 0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessim PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 1.078 4.288 rd3_clk USCM_84_108/CLK_USCM td 0.000 4.288 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 1.611 5.899 ntclkbufg_1 - CLMA_58_89/CLK r u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/CLK - clock pessimism -0.466 5.433 - clock uncertainty 0.000 5.433 + net (fanout=2516) 1.585 5.873 ntclkbufg_1 + CLMA_58_109/CLK r u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK + clock pessimism -0.466 5.407 + clock uncertainty 0.000 5.407 - Hold time 0.053 5.486 + Hold time 0.053 5.460 - Data required time 5.486 + Data required time 5.460 ---------------------------------------------------------------------------------------------------- - Data required time 5.486 - Data arrival time 5.708 + Data required time 5.460 + Data arrival time 5.686 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.222 + Slack (MET) 0.226 ==================================================================================================== ==================================================================================================== -Startpoint : image_filiter_inst2/hybrid_filter_inst/pixel_ff[27]/opit_0/CLK -Endpoint : image_filiter_inst2/hybrid_filter_inst/pixel_ff[43]/opit_0/D +Startpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK +Endpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[2] Path Group : clk_50m Path Type : min (slow corner) Path Class : sequential timing path -Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.873 - Launch Clock Delay : 5.378 - Clock Pessimism Removal : -0.495 +Clock Skew : 0.023 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 5.903 + Launch Clock Delay : 5.421 + Clock Pessimism Removal : -0.459 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -2097,15 +2096,15 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim PLL_158_55/CLK_OUT0 td 0.100 2.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 1.059 3.847 rd3_clk USCM_84_108/CLK_USCM td 0.000 3.847 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 1.531 5.378 ntclkbufg_1 - CLMA_98_148/CLK r image_filiter_inst2/hybrid_filter_inst/pixel_ff[27]/opit_0/CLK + net (fanout=2516) 1.574 5.421 ntclkbufg_1 + CLMA_50_32/CLK r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK - CLMA_98_148/Q3 tco 0.221 5.599 f image_filiter_inst2/hybrid_filter_inst/pixel_ff[27]/opit_0/Q - net (fanout=1) 0.084 5.683 image_filiter_inst2/hybrid_filter_inst/pixel_ff [27] - CLMA_98_148/AD f image_filiter_inst2/hybrid_filter_inst/pixel_ff[43]/opit_0/D + CLMA_50_32/Q0 tco 0.222 5.643 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Q0 + net (fanout=4) 0.218 5.861 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/wr_addr [0] + DRM_54_24/ADA0[2] f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[2] - Data arrival time 5.683 Logic Levels: 0 - Logic: 0.221ns(72.459%), Route: 0.084ns(27.541%) + Data arrival time 5.861 Logic Levels: 0 + Logic: 0.222ns(50.455%), Route: 0.218ns(49.545%) ---------------------------------------------------------------------------------------------------- Clock clk_50m (rising edge) 0.000 0.000 r @@ -2118,32 +2117,32 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 1.078 4.288 rd3_clk USCM_84_108/CLK_USCM td 0.000 4.288 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 1.585 5.873 ntclkbufg_1 - CLMA_98_148/CLK r image_filiter_inst2/hybrid_filter_inst/pixel_ff[43]/opit_0/CLK - clock pessimism -0.495 5.378 - clock uncertainty 0.000 5.378 + net (fanout=2516) 1.615 5.903 ntclkbufg_1 + DRM_54_24/CLKA[0] r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKA + clock pessimism -0.459 5.444 + clock uncertainty 0.000 5.444 - Hold time 0.053 5.431 + Hold time 0.186 5.630 - Data required time 5.431 + Data required time 5.630 ---------------------------------------------------------------------------------------------------- - Data required time 5.431 - Data arrival time 5.683 + Data required time 5.630 + Data arrival time 5.861 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.252 + Slack (MET) 0.231 ==================================================================================================== ==================================================================================================== -Startpoint : u_zoom_image/data_out_valid2/opit_0/CLK -Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[9]/opit_0_L6Q_perm/B3 +Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CE Path Group : clk_200m Path Type : max (slow corner) Path Class : sequential timing path -Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) +Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) Capture Clock Delay : 5.374 Launch Clock Delay : 5.867 - Clock Pessimism Removal : 0.439 + Clock Pessimism Removal : 0.493 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -2156,31 +2155,27 @@ Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessi IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.078 4.282 zoom_clk - USCM_84_122/CLK_USCM td 0.000 4.282 r USCMROUTE_2/CLKOUT - net (fanout=759) 1.585 5.867 ntR3909 - CLMA_242_124/CLK r u_zoom_image/data_out_valid2/opit_0/CLK - - CLMA_242_124/Q0 tco 0.289 6.156 r u_zoom_image/data_out_valid2/opit_0/Q - net (fanout=34) 0.630 6.786 zoom_data_out_valid - td 0.288 7.074 f u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Cout - net (fanout=1) 0.000 7.074 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16324 - CLMA_242_96/COUT td 0.058 7.132 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/Cout - net (fanout=1) 0.000 7.132 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16326 - CLMA_242_100/Y1 td 0.475 7.607 f u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/Y1 - net (fanout=3) 1.345 8.952 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N2 [5] - CLMA_246_176/Y2 td 0.210 9.162 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm/Z - net (fanout=3) 0.417 9.579 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wwptr [5] - td 0.474 10.053 f u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_5/gateop_A2/Cout - net (fanout=1) 0.000 10.053 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [6] - CLMS_242_169/COUT td 0.058 10.111 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_7/gateop_A2/Cout - net (fanout=1) 0.000 10.111 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [8] - CLMS_242_173/Y1 td 0.498 10.609 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_9/gateop_A2/Y1 - net (fanout=2) 0.416 11.025 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/nb6 [9] - CLMA_246_180/D3 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[9]/opit_0_L6Q_perm/B3 - - Data arrival time 11.025 Logic Levels: 5 - Logic: 2.350ns(45.560%), Route: 2.808ns(54.440%) + net (fanout=2) 1.078 4.282 ddr_clk + USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + net (fanout=71) 1.585 5.867 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + CLMA_90_197/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK + + CLMA_90_197/Q1 tco 0.291 6.158 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/Q + net (fanout=2) 0.408 6.566 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt [15] + CLMS_94_197/Y0 td 0.487 7.053 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_33/gateop_perm/Z + net (fanout=2) 0.123 7.176 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107154 + CLMA_94_196/Y2 td 0.478 7.654 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_36/gateop_perm/Z + net (fanout=1) 0.120 7.774 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107157 + CLMA_94_196/Y3 td 0.287 8.061 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43_3/gateop_perm/Z + net (fanout=11) 0.438 8.499 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43 + CLMA_90_185/CECO td 0.184 8.683 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[8]/opit_0_inv_L5Q_perm/CEOUT + net (fanout=4) 0.000 8.683 ntR1851 + CLMA_90_193/CECO td 0.184 8.867 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[11]/opit_0_inv_L5Q_perm/CEOUT + net (fanout=4) 0.000 8.867 ntR1850 + CLMA_90_197/CECI r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CE + + Data arrival time 8.867 Logic Levels: 5 + Logic: 1.911ns(63.700%), Route: 1.089ns(36.300%) ---------------------------------------------------------------------------------------------------- Clock clk_200m (rising edge) 5.000 5.000 r @@ -2191,34 +2186,34 @@ Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessi IOL_327_210/INCK td 0.048 6.930 r clk_ibuf/opit_1/INCK net (fanout=1) 0.758 7.688 _N69 PLL_158_55/CLK_OUT1 td 0.096 7.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.059 8.843 zoom_clk - USCM_84_122/CLK_USCM td 0.000 8.843 r USCMROUTE_2/CLKOUT - net (fanout=759) 1.531 10.374 ntR3909 - CLMA_246_180/CLK r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[9]/opit_0_L6Q_perm/CLK - clock pessimism 0.439 10.813 - clock uncertainty -0.150 10.663 + net (fanout=2) 1.059 8.843 ddr_clk + USCM_84_113/CLK_USCM td 0.000 8.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + net (fanout=71) 1.531 10.374 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + CLMA_90_197/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK + clock pessimism 0.493 10.867 + clock uncertainty -0.150 10.717 - Setup time -0.426 10.237 + Setup time -0.729 9.988 - Data required time 10.237 + Data required time 9.988 ---------------------------------------------------------------------------------------------------- - Data required time 10.237 - Data arrival time 11.025 + Data required time 9.988 + Data arrival time 8.867 ---------------------------------------------------------------------------------------------------- - Slack (VIOLATED) -0.788 + Slack (MET) 1.121 ==================================================================================================== ==================================================================================================== -Startpoint : u_zoom_image/mult_fra0_0/N2/gopapm/CLK -Endpoint : u_zoom_image/mult_image_r0_0/N2/gopapm/X[0] +Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[16]/opit_0_inv_L5Q_perm/CE Path Group : clk_200m Path Type : max (slow corner) Path Class : sequential timing path -Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.495 +Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 5.374 Launch Clock Delay : 5.867 - Clock Pessimism Removal : 0.439 + Clock Pessimism Removal : 0.493 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -2231,17 +2226,27 @@ Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.078 4.282 zoom_clk - USCM_84_122/CLK_USCM td 0.000 4.282 r USCMROUTE_2/CLKOUT - net (fanout=759) 1.585 5.867 ntR3909 - APM_206_140/CLK r u_zoom_image/mult_fra0_0/N2/gopapm/CLK - - APM_206_140/P[31] tco 1.067 6.934 f u_zoom_image/mult_fra0_0/N2/gopapm/P[7] - net (fanout=3) 2.395 9.329 u_zoom_image/coe_mult_p0_0 [7] - APM_206_328/X[0] f u_zoom_image/mult_image_r0_0/N2/gopapm/X[0] - - Data arrival time 9.329 Logic Levels: 0 - Logic: 1.067ns(30.820%), Route: 2.395ns(69.180%) + net (fanout=2) 1.078 4.282 ddr_clk + USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + net (fanout=71) 1.585 5.867 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + CLMA_90_197/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK + + CLMA_90_197/Q1 tco 0.291 6.158 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/Q + net (fanout=2) 0.408 6.566 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt [15] + CLMS_94_197/Y0 td 0.487 7.053 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_33/gateop_perm/Z + net (fanout=2) 0.123 7.176 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107154 + CLMA_94_196/Y2 td 0.478 7.654 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_36/gateop_perm/Z + net (fanout=1) 0.120 7.774 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107157 + CLMA_94_196/Y3 td 0.287 8.061 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43_3/gateop_perm/Z + net (fanout=11) 0.438 8.499 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43 + CLMA_90_185/CECO td 0.184 8.683 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[8]/opit_0_inv_L5Q_perm/CEOUT + net (fanout=4) 0.000 8.683 ntR1851 + CLMA_90_193/CECO td 0.184 8.867 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[11]/opit_0_inv_L5Q_perm/CEOUT + net (fanout=4) 0.000 8.867 ntR1850 + CLMA_90_197/CECI r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[16]/opit_0_inv_L5Q_perm/CE + + Data arrival time 8.867 Logic Levels: 5 + Logic: 1.911ns(63.700%), Route: 1.089ns(36.300%) ---------------------------------------------------------------------------------------------------- Clock clk_200m (rising edge) 5.000 5.000 r @@ -2252,34 +2257,34 @@ Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.048 6.930 r clk_ibuf/opit_1/INCK net (fanout=1) 0.758 7.688 _N69 PLL_158_55/CLK_OUT1 td 0.096 7.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.059 8.843 zoom_clk - USCM_84_122/CLK_USCM td 0.000 8.843 r USCMROUTE_2/CLKOUT - net (fanout=759) 1.652 10.495 ntR3909 - APM_206_328/CLK r u_zoom_image/mult_image_r0_0/N2/gopapm/CLK - clock pessimism 0.439 10.934 - clock uncertainty -0.150 10.784 + net (fanout=2) 1.059 8.843 ddr_clk + USCM_84_113/CLK_USCM td 0.000 8.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + net (fanout=71) 1.531 10.374 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + CLMA_90_197/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[16]/opit_0_inv_L5Q_perm/CLK + clock pessimism 0.493 10.867 + clock uncertainty -0.150 10.717 - Setup time -2.243 8.541 + Setup time -0.729 9.988 - Data required time 8.541 + Data required time 9.988 ---------------------------------------------------------------------------------------------------- - Data required time 8.541 - Data arrival time 9.329 + Data required time 9.988 + Data arrival time 8.867 ---------------------------------------------------------------------------------------------------- - Slack (VIOLATED) -0.788 + Slack (MET) 1.121 ==================================================================================================== ==================================================================================================== -Startpoint : u_zoom_image/mult_fra0_0/N2/gopapm/CLK -Endpoint : u_zoom_image/mult_image_r0_0/N2/gopapm/X[3] +Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[17]/opit_0_inv_L5Q_perm/CE Path Group : clk_200m Path Type : max (slow corner) Path Class : sequential timing path -Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.495 +Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 5.374 Launch Clock Delay : 5.867 - Clock Pessimism Removal : 0.439 + Clock Pessimism Removal : 0.493 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -2292,17 +2297,27 @@ Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.078 4.282 zoom_clk - USCM_84_122/CLK_USCM td 0.000 4.282 r USCMROUTE_2/CLKOUT - net (fanout=759) 1.585 5.867 ntR3909 - APM_206_140/CLK r u_zoom_image/mult_fra0_0/N2/gopapm/CLK - - APM_206_140/P[34] tco 1.067 6.934 f u_zoom_image/mult_fra0_0/N2/gopapm/P[10] - net (fanout=3) 2.347 9.281 u_zoom_image/coe_mult_p0_0 [10] - APM_206_328/X[3] f u_zoom_image/mult_image_r0_0/N2/gopapm/X[3] - - Data arrival time 9.281 Logic Levels: 0 - Logic: 1.067ns(31.254%), Route: 2.347ns(68.746%) + net (fanout=2) 1.078 4.282 ddr_clk + USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + net (fanout=71) 1.585 5.867 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + CLMA_90_197/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK + + CLMA_90_197/Q1 tco 0.291 6.158 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/Q + net (fanout=2) 0.408 6.566 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt [15] + CLMS_94_197/Y0 td 0.487 7.053 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_33/gateop_perm/Z + net (fanout=2) 0.123 7.176 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107154 + CLMA_94_196/Y2 td 0.478 7.654 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_36/gateop_perm/Z + net (fanout=1) 0.120 7.774 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107157 + CLMA_94_196/Y3 td 0.287 8.061 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43_3/gateop_perm/Z + net (fanout=11) 0.438 8.499 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43 + CLMA_90_185/CECO td 0.184 8.683 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[8]/opit_0_inv_L5Q_perm/CEOUT + net (fanout=4) 0.000 8.683 ntR1851 + CLMA_90_193/CECO td 0.184 8.867 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[11]/opit_0_inv_L5Q_perm/CEOUT + net (fanout=4) 0.000 8.867 ntR1850 + CLMA_90_197/CECI r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[17]/opit_0_inv_L5Q_perm/CE + + Data arrival time 8.867 Logic Levels: 5 + Logic: 1.911ns(63.700%), Route: 1.089ns(36.300%) ---------------------------------------------------------------------------------------------------- Clock clk_200m (rising edge) 5.000 5.000 r @@ -2313,34 +2328,34 @@ Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.048 6.930 r clk_ibuf/opit_1/INCK net (fanout=1) 0.758 7.688 _N69 PLL_158_55/CLK_OUT1 td 0.096 7.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.059 8.843 zoom_clk - USCM_84_122/CLK_USCM td 0.000 8.843 r USCMROUTE_2/CLKOUT - net (fanout=759) 1.652 10.495 ntR3909 - APM_206_328/CLK r u_zoom_image/mult_image_r0_0/N2/gopapm/CLK - clock pessimism 0.439 10.934 - clock uncertainty -0.150 10.784 + net (fanout=2) 1.059 8.843 ddr_clk + USCM_84_113/CLK_USCM td 0.000 8.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + net (fanout=71) 1.531 10.374 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + CLMA_90_197/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[17]/opit_0_inv_L5Q_perm/CLK + clock pessimism 0.493 10.867 + clock uncertainty -0.150 10.717 - Setup time -2.243 8.541 + Setup time -0.729 9.988 - Data required time 8.541 + Data required time 9.988 ---------------------------------------------------------------------------------------------------- - Data required time 8.541 - Data arrival time 9.281 + Data required time 9.988 + Data arrival time 8.867 ---------------------------------------------------------------------------------------------------- - Slack (VIOLATED) -0.740 + Slack (MET) 1.121 ==================================================================================================== ==================================================================================================== -Startpoint : u_zoom_image/mult_image_g0/N2/gopapm/CLK -Endpoint : u_zoom_image/mult_image_g1/N2/gopapm/PI[0] +Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/pll_lock_d[1]/opit_0_inv/CLK +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_b_ff/opit_0_inv/D Path Group : clk_200m Path Type : min (slow corner) Path Class : sequential timing path -Clock Skew : 0.177 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.990 +Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 5.867 Launch Clock Delay : 5.374 - Clock Pessimism Removal : -0.439 + Clock Pessimism Removal : -0.464 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -2353,17 +2368,17 @@ Clock Skew : 0.177 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK net (fanout=1) 0.758 2.688 _N69 PLL_158_55/CLK_OUT1 td 0.096 2.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.059 3.843 zoom_clk - USCM_84_122/CLK_USCM td 0.000 3.843 r USCMROUTE_2/CLKOUT - net (fanout=759) 1.531 5.374 ntR3909 - APM_206_240/CLK r u_zoom_image/mult_image_g0/N2/gopapm/CLK + net (fanout=2) 1.059 3.843 ddr_clk + USCM_84_113/CLK_USCM td 0.000 3.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + net (fanout=71) 1.531 5.374 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + CLMS_94_193/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/pll_lock_d[1]/opit_0_inv/CLK - APM_206_240/PO[0] tco 0.297 5.671 r u_zoom_image/mult_image_g0/N2/gopapm/PO[0] - net (fanout=1) 0.000 5.671 u_zoom_image/mult_image0[2] [0] - APM_206_252/PI[0] r u_zoom_image/mult_image_g1/N2/gopapm/PI[0] + CLMS_94_193/Q0 tco 0.226 5.600 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/pll_lock_d[1]/opit_0_inv/Q + net (fanout=3) 0.104 5.704 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/pll_lock_d [1] + CLMA_94_192/M0 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_b_ff/opit_0_inv/D - Data arrival time 5.671 Logic Levels: 0 - Logic: 0.297ns(100.000%), Route: 0.000ns(0.000%) + Data arrival time 5.704 Logic Levels: 0 + Logic: 0.226ns(68.485%), Route: 0.104ns(31.515%) ---------------------------------------------------------------------------------------------------- Clock clk_200m (rising edge) 0.000 0.000 r @@ -2374,34 +2389,34 @@ Clock Skew : 0.177 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.078 4.282 zoom_clk - USCM_84_122/CLK_USCM td 0.000 4.282 r USCMROUTE_2/CLKOUT - net (fanout=759) 1.708 5.990 ntR3909 - APM_206_252/CLK r u_zoom_image/mult_image_g1/N2/gopapm/CLK - clock pessimism -0.439 5.551 - clock uncertainty 0.000 5.551 + net (fanout=2) 1.078 4.282 ddr_clk + USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + net (fanout=71) 1.585 5.867 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + CLMA_94_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_b_ff/opit_0_inv/CLK + clock pessimism -0.464 5.403 + clock uncertainty 0.000 5.403 - Hold time -0.121 5.430 + Hold time -0.014 5.389 - Data required time 5.430 + Data required time 5.389 ---------------------------------------------------------------------------------------------------- - Data required time 5.430 - Data arrival time 5.671 + Data required time 5.389 + Data arrival time 5.704 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.241 + Slack (MET) 0.315 ==================================================================================================== ==================================================================================================== -Startpoint : u_zoom_image/mult_image_g0/N2/gopapm/CLK -Endpoint : u_zoom_image/mult_image_g1/N2/gopapm/PI[1] +Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]/opit_0_inv_L5Q_perm/CLK +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]/opit_0_inv_L5Q_perm/L4 Path Group : clk_200m Path Type : min (slow corner) Path Class : sequential timing path -Clock Skew : 0.177 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.990 +Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 5.867 Launch Clock Delay : 5.374 - Clock Pessimism Removal : -0.439 + Clock Pessimism Removal : -0.493 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -2414,17 +2429,17 @@ Clock Skew : 0.177 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK net (fanout=1) 0.758 2.688 _N69 PLL_158_55/CLK_OUT1 td 0.096 2.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.059 3.843 zoom_clk - USCM_84_122/CLK_USCM td 0.000 3.843 r USCMROUTE_2/CLKOUT - net (fanout=759) 1.531 5.374 ntR3909 - APM_206_240/CLK r u_zoom_image/mult_image_g0/N2/gopapm/CLK + net (fanout=2) 1.059 3.843 ddr_clk + USCM_84_113/CLK_USCM td 0.000 3.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + net (fanout=71) 1.531 5.374 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + CLMS_38_185/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]/opit_0_inv_L5Q_perm/CLK - APM_206_240/PO[1] tco 0.297 5.671 r u_zoom_image/mult_image_g0/N2/gopapm/PO[1] - net (fanout=1) 0.000 5.671 u_zoom_image/mult_image0[2] [1] - APM_206_252/PI[1] r u_zoom_image/mult_image_g1/N2/gopapm/PI[1] + CLMS_38_185/Q3 tco 0.221 5.595 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]/opit_0_inv_L5Q_perm/Q + net (fanout=3) 0.087 5.682 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg [4] + CLMS_38_185/D4 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]/opit_0_inv_L5Q_perm/L4 - Data arrival time 5.671 Logic Levels: 0 - Logic: 0.297ns(100.000%), Route: 0.000ns(0.000%) + Data arrival time 5.682 Logic Levels: 0 + Logic: 0.221ns(71.753%), Route: 0.087ns(28.247%) ---------------------------------------------------------------------------------------------------- Clock clk_200m (rising edge) 0.000 0.000 r @@ -2435,34 +2450,34 @@ Clock Skew : 0.177 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.078 4.282 zoom_clk - USCM_84_122/CLK_USCM td 0.000 4.282 r USCMROUTE_2/CLKOUT - net (fanout=759) 1.708 5.990 ntR3909 - APM_206_252/CLK r u_zoom_image/mult_image_g1/N2/gopapm/CLK - clock pessimism -0.439 5.551 - clock uncertainty 0.000 5.551 + net (fanout=2) 1.078 4.282 ddr_clk + USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + net (fanout=71) 1.585 5.867 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + CLMS_38_185/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]/opit_0_inv_L5Q_perm/CLK + clock pessimism -0.493 5.374 + clock uncertainty 0.000 5.374 - Hold time -0.121 5.430 + Hold time -0.034 5.340 - Data required time 5.430 + Data required time 5.340 ---------------------------------------------------------------------------------------------------- - Data required time 5.430 - Data arrival time 5.671 + Data required time 5.340 + Data arrival time 5.682 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.241 + Slack (MET) 0.342 ==================================================================================================== ==================================================================================================== -Startpoint : u_zoom_image/mult_image_g0/N2/gopapm/CLK -Endpoint : u_zoom_image/mult_image_g1/N2/gopapm/PI[2] +Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[2]/opit_0_inv_L5Q_perm/CLK +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[3]/opit_0_inv_L5Q_perm/L4 Path Group : clk_200m Path Type : min (slow corner) Path Class : sequential timing path -Clock Skew : 0.177 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.990 +Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 5.867 Launch Clock Delay : 5.374 - Clock Pessimism Removal : -0.439 + Clock Pessimism Removal : -0.493 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -2475,17 +2490,17 @@ Clock Skew : 0.177 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK net (fanout=1) 0.758 2.688 _N69 PLL_158_55/CLK_OUT1 td 0.096 2.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.059 3.843 zoom_clk - USCM_84_122/CLK_USCM td 0.000 3.843 r USCMROUTE_2/CLKOUT - net (fanout=759) 1.531 5.374 ntR3909 - APM_206_240/CLK r u_zoom_image/mult_image_g0/N2/gopapm/CLK + net (fanout=2) 1.059 3.843 ddr_clk + USCM_84_113/CLK_USCM td 0.000 3.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + net (fanout=71) 1.531 5.374 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + CLMS_38_185/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[2]/opit_0_inv_L5Q_perm/CLK - APM_206_240/PO[2] tco 0.297 5.671 r u_zoom_image/mult_image_g0/N2/gopapm/PO[2] - net (fanout=1) 0.000 5.671 u_zoom_image/mult_image0[2] [2] - APM_206_252/PI[2] r u_zoom_image/mult_image_g1/N2/gopapm/PI[2] + CLMS_38_185/Q0 tco 0.222 5.596 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[2]/opit_0_inv_L5Q_perm/Q + net (fanout=4) 0.087 5.683 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg [2] + CLMS_38_185/B4 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[3]/opit_0_inv_L5Q_perm/L4 - Data arrival time 5.671 Logic Levels: 0 - Logic: 0.297ns(100.000%), Route: 0.000ns(0.000%) + Data arrival time 5.683 Logic Levels: 0 + Logic: 0.222ns(71.845%), Route: 0.087ns(28.155%) ---------------------------------------------------------------------------------------------------- Clock clk_200m (rising edge) 0.000 0.000 r @@ -2496,34 +2511,34 @@ Clock Skew : 0.177 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.078 4.282 zoom_clk - USCM_84_122/CLK_USCM td 0.000 4.282 r USCMROUTE_2/CLKOUT - net (fanout=759) 1.708 5.990 ntR3909 - APM_206_252/CLK r u_zoom_image/mult_image_g1/N2/gopapm/CLK - clock pessimism -0.439 5.551 - clock uncertainty 0.000 5.551 + net (fanout=2) 1.078 4.282 ddr_clk + USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + net (fanout=71) 1.585 5.867 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + CLMS_38_185/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[3]/opit_0_inv_L5Q_perm/CLK + clock pessimism -0.493 5.374 + clock uncertainty 0.000 5.374 - Hold time -0.121 5.430 + Hold time -0.035 5.339 - Data required time 5.430 + Data required time 5.339 ---------------------------------------------------------------------------------------------------- - Data required time 5.430 - Data arrival time 5.671 + Data required time 5.339 + Data arrival time 5.683 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.241 + Slack (MET) 0.344 ==================================================================================================== ==================================================================================================== -Startpoint : u_ov5640/coms1_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK -Endpoint : u_ov5640/coms1_reg_config/clock_20k_cnt[8]/opit_0_inv/D +Startpoint : u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK +Endpoint : u_ov5640/coms2_reg_config/clock_20k_cnt[10]/opit_0_inv/D Path Group : clk_25m Path Type : max (slow corner) Path Class : sequential timing path -Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) +Clock Skew : -0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) Capture Clock Delay : 5.383 Launch Clock Delay : 5.877 - Clock Pessimism Removal : 0.494 + Clock Pessimism Removal : 0.465 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -2537,26 +2552,26 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT3 td 0.111 3.214 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 net (fanout=1) 1.078 4.292 clk_25m - USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 1.585 5.877 ntclkbufg_7 - CLMA_182_17/CLK r u_ov5640/coms1_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK - - CLMA_182_17/Q0 tco 0.289 6.166 r u_ov5640/coms1_reg_config/clock_20k_cnt[0]/opit_0_inv/Q - net (fanout=4) 0.557 6.723 u_ov5640/coms1_reg_config/clock_20k_cnt [0] - CLMA_182_13/Y2 td 0.487 7.210 r u_ov5640/coms1_reg_config/N8_mux4_5/gateop_perm/Z - net (fanout=1) 0.403 7.613 u_ov5640/coms1_reg_config/_N9664 - CLMA_186_16/Y0 td 0.210 7.823 r u_ov5640/coms1_reg_config/N8_mux10/gateop_perm/Z - net (fanout=13) 0.777 8.600 u_ov5640/coms1_reg_config/N8 - CLMA_182_12/COUT td 0.507 9.107 r u_ov5640/coms1_reg_config/N11_2_3/gateop_A2/Cout - net (fanout=1) 0.000 9.107 u_ov5640/coms1_reg_config/_N16248 - td 0.058 9.165 r u_ov5640/coms1_reg_config/N11_2_5/gateop_A2/Cout - net (fanout=1) 0.000 9.165 u_ov5640/coms1_reg_config/_N16250 - CLMA_182_16/Y3 td 0.501 9.666 r u_ov5640/coms1_reg_config/N11_2_7/gateop_A2/Y1 - net (fanout=1) 0.563 10.229 u_ov5640/coms1_reg_config/N1114 [8] - CLMA_182_17/M2 r u_ov5640/coms1_reg_config/clock_20k_cnt[8]/opit_0_inv/D - - Data arrival time 10.229 Logic Levels: 4 - Logic: 2.052ns(47.151%), Route: 2.300ns(52.849%) + USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 1.585 5.877 ntclkbufg_8 + CLMS_122_13/CLK r u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK + + CLMS_122_13/Q1 tco 0.291 6.168 r u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/Q + net (fanout=4) 0.406 6.574 u_ov5640/coms2_reg_config/clock_20k_cnt [0] + CLMA_122_16/Y3 td 0.468 7.042 r u_ov5640/coms2_reg_config/N8_mux4_5/gateop_perm/Z + net (fanout=1) 0.560 7.602 u_ov5640/coms2_reg_config/_N9749 + CLMA_122_16/Y2 td 0.210 7.812 r u_ov5640/coms2_reg_config/N8_mux10/gateop_perm/Z + net (fanout=13) 0.569 8.381 u_ov5640/coms2_reg_config/N8 + td 0.477 8.858 f u_ov5640/coms2_reg_config/N11_2_5/gateop_A2/Cout + net (fanout=1) 0.000 8.858 u_ov5640/coms2_reg_config/_N16307 + CLMS_122_17/COUT td 0.058 8.916 r u_ov5640/coms2_reg_config/N11_2_7/gateop_A2/Cout + net (fanout=1) 0.000 8.916 u_ov5640/coms2_reg_config/_N16309 + CLMS_122_21/Y1 td 0.498 9.414 r u_ov5640/coms2_reg_config/N11_2_9/gateop_A2/Y1 + net (fanout=1) 0.704 10.118 u_ov5640/coms2_reg_config/N1114 [10] + CLMS_122_17/M3 r u_ov5640/coms2_reg_config/clock_20k_cnt[10]/opit_0_inv/D + + Data arrival time 10.118 Logic Levels: 4 + Logic: 2.002ns(47.206%), Route: 2.239ns(52.794%) ---------------------------------------------------------------------------------------------------- Clock clk_25m (rising edge) 40.000 40.000 r @@ -2568,26 +2583,26 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.758 42.688 _N69 PLL_158_55/CLK_OUT3 td 0.105 42.793 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 net (fanout=1) 1.059 43.852 clk_25m - USCM_84_114/CLK_USCM td 0.000 43.852 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 1.531 45.383 ntclkbufg_7 - CLMA_182_17/CLK r u_ov5640/coms1_reg_config/clock_20k_cnt[8]/opit_0_inv/CLK - clock pessimism 0.494 45.877 - clock uncertainty -0.150 45.727 + USCM_84_114/CLK_USCM td 0.000 43.852 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 1.531 45.383 ntclkbufg_8 + CLMS_122_17/CLK r u_ov5640/coms2_reg_config/clock_20k_cnt[10]/opit_0_inv/CLK + clock pessimism 0.465 45.848 + clock uncertainty -0.150 45.698 - Setup time -0.079 45.648 + Setup time -0.079 45.619 - Data required time 45.648 + Data required time 45.619 ---------------------------------------------------------------------------------------------------- - Data required time 45.648 - Data arrival time 10.229 + Data required time 45.619 + Data arrival time 10.118 ---------------------------------------------------------------------------------------------------- - Slack (MET) 35.419 + Slack (MET) 35.501 ==================================================================================================== ==================================================================================================== Startpoint : u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK -Endpoint : u_ov5640/coms2_reg_config/clock_20k_cnt[6]/opit_0_inv/D +Endpoint : u_ov5640/coms2_reg_config/clock_20k_cnt[8]/opit_0_inv/D Path Group : clk_25m Path Type : max (slow corner) Path Class : sequential timing path @@ -2608,26 +2623,24 @@ Clock Skew : -0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessi net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT3 td 0.111 3.214 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 net (fanout=1) 1.078 4.292 clk_25m - USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 1.585 5.877 ntclkbufg_7 - CLMA_182_21/CLK r u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK - - CLMA_182_21/Q2 tco 0.290 6.167 r u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/Q - net (fanout=4) 0.548 6.715 u_ov5640/coms2_reg_config/clock_20k_cnt [0] - CLMA_186_16/Y1 td 0.468 7.183 r u_ov5640/coms2_reg_config/N8_mux4_5/gateop_perm/Z - net (fanout=1) 0.398 7.581 u_ov5640/coms2_reg_config/_N9736 - CLMA_186_20/Y1 td 0.304 7.885 r u_ov5640/coms2_reg_config/N8_mux10/gateop_perm/Z - net (fanout=13) 0.644 8.529 u_ov5640/coms2_reg_config/N8 - td 0.477 9.006 f u_ov5640/coms2_reg_config/N11_2_1/gateop_A2/Cout - net (fanout=1) 0.000 9.006 u_ov5640/coms2_reg_config/_N16399 - CLMA_182_21/COUT td 0.058 9.064 r u_ov5640/coms2_reg_config/N11_2_3/gateop_A2/Cout - net (fanout=1) 0.000 9.064 u_ov5640/coms2_reg_config/_N16401 - CLMA_182_25/Y1 td 0.498 9.562 r u_ov5640/coms2_reg_config/N11_2_5/gateop_A2/Y1 - net (fanout=1) 0.622 10.184 u_ov5640/coms2_reg_config/N1114 [6] - CLMA_182_20/M1 r u_ov5640/coms2_reg_config/clock_20k_cnt[6]/opit_0_inv/D - - Data arrival time 10.184 Logic Levels: 4 - Logic: 2.095ns(48.642%), Route: 2.212ns(51.358%) + USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 1.585 5.877 ntclkbufg_8 + CLMS_122_13/CLK r u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK + + CLMS_122_13/Q1 tco 0.291 6.168 r u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/Q + net (fanout=4) 0.406 6.574 u_ov5640/coms2_reg_config/clock_20k_cnt [0] + CLMA_122_16/Y3 td 0.468 7.042 r u_ov5640/coms2_reg_config/N8_mux4_5/gateop_perm/Z + net (fanout=1) 0.560 7.602 u_ov5640/coms2_reg_config/_N9749 + CLMA_122_16/Y2 td 0.210 7.812 r u_ov5640/coms2_reg_config/N8_mux10/gateop_perm/Z + net (fanout=13) 0.569 8.381 u_ov5640/coms2_reg_config/N8 + td 0.477 8.858 f u_ov5640/coms2_reg_config/N11_2_5/gateop_A2/Cout + net (fanout=1) 0.000 8.858 u_ov5640/coms2_reg_config/_N16307 + CLMS_122_17/Y3 td 0.501 9.359 r u_ov5640/coms2_reg_config/N11_2_7/gateop_A2/Y1 + net (fanout=1) 0.747 10.106 u_ov5640/coms2_reg_config/N1114 [8] + CLMS_122_17/M2 r u_ov5640/coms2_reg_config/clock_20k_cnt[8]/opit_0_inv/D + + Data arrival time 10.106 Logic Levels: 3 + Logic: 1.947ns(46.039%), Route: 2.282ns(53.961%) ---------------------------------------------------------------------------------------------------- Clock clk_25m (rising edge) 40.000 40.000 r @@ -2639,9 +2652,9 @@ Clock Skew : -0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessi net (fanout=1) 0.758 42.688 _N69 PLL_158_55/CLK_OUT3 td 0.105 42.793 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 net (fanout=1) 1.059 43.852 clk_25m - USCM_84_114/CLK_USCM td 0.000 43.852 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 1.531 45.383 ntclkbufg_7 - CLMA_182_20/CLK r u_ov5640/coms2_reg_config/clock_20k_cnt[6]/opit_0_inv/CLK + USCM_84_114/CLK_USCM td 0.000 43.852 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 1.531 45.383 ntclkbufg_8 + CLMS_122_17/CLK r u_ov5640/coms2_reg_config/clock_20k_cnt[8]/opit_0_inv/CLK clock pessimism 0.465 45.848 clock uncertainty -0.150 45.698 @@ -2650,15 +2663,15 @@ Clock Skew : -0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessi Data required time 45.619 ---------------------------------------------------------------------------------------------------- Data required time 45.619 - Data arrival time 10.184 + Data arrival time 10.106 ---------------------------------------------------------------------------------------------------- - Slack (MET) 35.435 + Slack (MET) 35.513 ==================================================================================================== ==================================================================================================== -Startpoint : u_ov5640/coms1_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK -Endpoint : u_ov5640/coms1_reg_config/clock_20k_cnt[4]/opit_0_inv/D +Startpoint : u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK +Endpoint : u_ov5640/coms2_reg_config/clock_20k_cnt[9]/opit_0_inv/D Path Group : clk_25m Path Type : max (slow corner) Path Class : sequential timing path @@ -2679,24 +2692,26 @@ Clock Skew : -0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessi net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT3 td 0.111 3.214 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 net (fanout=1) 1.078 4.292 clk_25m - USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 1.585 5.877 ntclkbufg_7 - CLMA_182_17/CLK r u_ov5640/coms1_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK - - CLMA_182_17/Q0 tco 0.289 6.166 r u_ov5640/coms1_reg_config/clock_20k_cnt[0]/opit_0_inv/Q - net (fanout=4) 0.557 6.723 u_ov5640/coms1_reg_config/clock_20k_cnt [0] - CLMA_182_13/Y2 td 0.487 7.210 r u_ov5640/coms1_reg_config/N8_mux4_5/gateop_perm/Z - net (fanout=1) 0.403 7.613 u_ov5640/coms1_reg_config/_N9664 - CLMA_186_16/Y0 td 0.210 7.823 r u_ov5640/coms1_reg_config/N8_mux10/gateop_perm/Z - net (fanout=13) 0.598 8.421 u_ov5640/coms1_reg_config/N8 - td 0.477 8.898 f u_ov5640/coms1_reg_config/N11_2_1/gateop_A2/Cout - net (fanout=1) 0.000 8.898 u_ov5640/coms1_reg_config/_N16246 - CLMA_182_12/Y3 td 0.501 9.399 r u_ov5640/coms1_reg_config/N11_2_3/gateop_A2/Y1 - net (fanout=1) 0.770 10.169 u_ov5640/coms1_reg_config/N1114 [4] - CLMA_182_16/M0 r u_ov5640/coms1_reg_config/clock_20k_cnt[4]/opit_0_inv/D - - Data arrival time 10.169 Logic Levels: 3 - Logic: 1.964ns(45.760%), Route: 2.328ns(54.240%) + USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 1.585 5.877 ntclkbufg_8 + CLMS_122_13/CLK r u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK + + CLMS_122_13/Q1 tco 0.291 6.168 r u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/Q + net (fanout=4) 0.406 6.574 u_ov5640/coms2_reg_config/clock_20k_cnt [0] + CLMA_122_16/Y3 td 0.468 7.042 r u_ov5640/coms2_reg_config/N8_mux4_5/gateop_perm/Z + net (fanout=1) 0.560 7.602 u_ov5640/coms2_reg_config/_N9749 + CLMA_122_16/Y2 td 0.210 7.812 r u_ov5640/coms2_reg_config/N8_mux10/gateop_perm/Z + net (fanout=13) 0.569 8.381 u_ov5640/coms2_reg_config/N8 + td 0.477 8.858 f u_ov5640/coms2_reg_config/N11_2_5/gateop_A2/Cout + net (fanout=1) 0.000 8.858 u_ov5640/coms2_reg_config/_N16307 + CLMS_122_17/COUT td 0.058 8.916 r u_ov5640/coms2_reg_config/N11_2_7/gateop_A2/Cout + net (fanout=1) 0.000 8.916 u_ov5640/coms2_reg_config/_N16309 + CLMS_122_21/Y0 td 0.267 9.183 f u_ov5640/coms2_reg_config/N11_2_9/gateop_A2/Y0 + net (fanout=1) 0.710 9.893 u_ov5640/coms2_reg_config/N1114 [9] + CLMS_122_17/M1 f u_ov5640/coms2_reg_config/clock_20k_cnt[9]/opit_0_inv/D + + Data arrival time 9.893 Logic Levels: 4 + Logic: 1.771ns(44.099%), Route: 2.245ns(55.901%) ---------------------------------------------------------------------------------------------------- Clock clk_25m (rising edge) 40.000 40.000 r @@ -2708,20 +2723,20 @@ Clock Skew : -0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessi net (fanout=1) 0.758 42.688 _N69 PLL_158_55/CLK_OUT3 td 0.105 42.793 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 net (fanout=1) 1.059 43.852 clk_25m - USCM_84_114/CLK_USCM td 0.000 43.852 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 1.531 45.383 ntclkbufg_7 - CLMA_182_16/CLK r u_ov5640/coms1_reg_config/clock_20k_cnt[4]/opit_0_inv/CLK + USCM_84_114/CLK_USCM td 0.000 43.852 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 1.531 45.383 ntclkbufg_8 + CLMS_122_17/CLK r u_ov5640/coms2_reg_config/clock_20k_cnt[9]/opit_0_inv/CLK clock pessimism 0.465 45.848 clock uncertainty -0.150 45.698 - Setup time -0.079 45.619 + Setup time -0.088 45.610 - Data required time 45.619 + Data required time 45.610 ---------------------------------------------------------------------------------------------------- - Data required time 45.619 - Data arrival time 10.169 + Data required time 45.610 + Data arrival time 9.893 ---------------------------------------------------------------------------------------------------- - Slack (MET) 35.450 + Slack (MET) 35.717 ==================================================================================================== ==================================================================================================== @@ -2748,16 +2763,16 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.758 2.688 _N69 PLL_158_55/CLK_OUT3 td 0.105 2.793 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 net (fanout=1) 1.059 3.852 clk_25m - USCM_84_114/CLK_USCM td 0.000 3.852 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 1.531 5.383 ntclkbufg_7 - CLMA_182_12/CLK r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK + USCM_84_114/CLK_USCM td 0.000 3.852 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 1.531 5.383 ntclkbufg_8 + CLMS_122_9/CLK r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK - CLMA_182_12/Q1 tco 0.229 5.612 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q - net (fanout=3) 0.332 5.944 u_ov5640/coms1_reg_config/clk_20k_regdiv - CLMA_182_12/M0 r u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/D + CLMS_122_9/Q1 tco 0.224 5.607 f u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q + net (fanout=3) 0.302 5.909 u_ov5640/coms1_reg_config/clk_20k_regdiv + CLMS_122_9/M0 f u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/D - Data arrival time 5.944 Logic Levels: 0 - Logic: 0.229ns(40.820%), Route: 0.332ns(59.180%) + Data arrival time 5.909 Logic Levels: 0 + Logic: 0.224ns(42.586%), Route: 0.302ns(57.414%) ---------------------------------------------------------------------------------------------------- Clock clk_25m (rising edge) 0.000 0.000 r @@ -2769,20 +2784,20 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT3 td 0.111 3.214 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 net (fanout=1) 1.078 4.292 clk_25m - USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 1.585 5.877 ntclkbufg_7 - CLMA_182_12/CLK r u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/CLK + USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 1.585 5.877 ntclkbufg_8 + CLMS_122_9/CLK r u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/CLK clock pessimism -0.494 5.383 clock uncertainty 0.000 5.383 - Hold time -0.014 5.369 + Hold time -0.024 5.359 - Data required time 5.369 + Data required time 5.359 ---------------------------------------------------------------------------------------------------- - Data required time 5.369 - Data arrival time 5.944 + Data required time 5.359 + Data arrival time 5.909 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.575 + Slack (MET) 0.550 ==================================================================================================== ==================================================================================================== @@ -2809,16 +2824,16 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.758 2.688 _N69 PLL_158_55/CLK_OUT3 td 0.105 2.793 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 net (fanout=1) 1.059 3.852 clk_25m - USCM_84_114/CLK_USCM td 0.000 3.852 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 1.531 5.383 ntclkbufg_7 - CLMA_182_25/CLK r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/CLK + USCM_84_114/CLK_USCM td 0.000 3.852 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 1.531 5.383 ntclkbufg_8 + CLMA_122_12/CLK r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/CLK - CLMA_182_25/Q1 tco 0.229 5.612 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q - net (fanout=3) 0.468 6.080 u_ov5640/coms2_reg_config/clk_20k_regdiv - CLMA_182_25/M0 r u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite/opit_0_inv/D + CLMA_122_12/Q1 tco 0.229 5.612 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q + net (fanout=3) 0.338 5.950 u_ov5640/coms2_reg_config/clk_20k_regdiv + CLMA_122_12/M0 r u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite/opit_0_inv/D - Data arrival time 6.080 Logic Levels: 0 - Logic: 0.229ns(32.855%), Route: 0.468ns(67.145%) + Data arrival time 5.950 Logic Levels: 0 + Logic: 0.229ns(40.388%), Route: 0.338ns(59.612%) ---------------------------------------------------------------------------------------------------- Clock clk_25m (rising edge) 0.000 0.000 r @@ -2830,9 +2845,9 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT3 td 0.111 3.214 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 net (fanout=1) 1.078 4.292 clk_25m - USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 1.585 5.877 ntclkbufg_7 - CLMA_182_25/CLK r u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite/opit_0_inv/CLK + USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 1.585 5.877 ntclkbufg_8 + CLMA_122_12/CLK r u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite/opit_0_inv/CLK clock pessimism -0.494 5.383 clock uncertainty 0.000 5.383 @@ -2841,15 +2856,15 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim Data required time 5.369 ---------------------------------------------------------------------------------------------------- Data required time 5.369 - Data arrival time 6.080 + Data arrival time 5.950 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.711 + Slack (MET) 0.581 ==================================================================================================== ==================================================================================================== -Startpoint : u_ov5640/coms1_reg_config/clock_20k_cnt[5]/opit_0_inv/CLK -Endpoint : u_ov5640/coms1_reg_config/clock_20k_cnt[5]/opit_0_inv/D +Startpoint : u_ov5640/coms1_reg_config/clock_20k_cnt[1]/opit_0_inv/CLK +Endpoint : u_ov5640/coms1_reg_config/clock_20k_cnt[1]/opit_0_inv/D Path Group : clk_25m Path Type : min (slow corner) Path Class : sequential timing path @@ -2870,18 +2885,18 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.758 2.688 _N69 PLL_158_55/CLK_OUT3 td 0.105 2.793 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 net (fanout=1) 1.059 3.852 clk_25m - USCM_84_114/CLK_USCM td 0.000 3.852 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 1.531 5.383 ntclkbufg_7 - CLMA_182_17/CLK r u_ov5640/coms1_reg_config/clock_20k_cnt[5]/opit_0_inv/CLK + USCM_84_114/CLK_USCM td 0.000 3.852 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 1.531 5.383 ntclkbufg_8 + CLMS_118_13/CLK r u_ov5640/coms1_reg_config/clock_20k_cnt[1]/opit_0_inv/CLK - CLMA_182_17/Y0 tco 0.284 5.667 f u_ov5640/coms1_reg_config/clock_20k_cnt[5]/opit_0_inv/Q - net (fanout=2) 0.086 5.753 u_ov5640/coms1_reg_config/clock_20k_cnt [5] - CLMA_182_16/Y0 td 0.232 5.985 f u_ov5640/coms1_reg_config/N11_2_5/gateop_A2/Y0 - net (fanout=1) 0.193 6.178 u_ov5640/coms1_reg_config/N1114 [5] - CLMA_182_17/AD f u_ov5640/coms1_reg_config/clock_20k_cnt[5]/opit_0_inv/D + CLMS_118_13/Q0 tco 0.222 5.605 f u_ov5640/coms1_reg_config/clock_20k_cnt[1]/opit_0_inv/Q + net (fanout=3) 0.086 5.691 u_ov5640/coms1_reg_config/clock_20k_cnt [1] + CLMS_118_13/Y0 td 0.229 5.920 r u_ov5640/coms1_reg_config/N11_2_1/gateop_A2/Y0 + net (fanout=1) 0.104 6.024 u_ov5640/coms1_reg_config/N1114 [1] + CLMS_118_13/M0 r u_ov5640/coms1_reg_config/clock_20k_cnt[1]/opit_0_inv/D - Data arrival time 6.178 Logic Levels: 1 - Logic: 0.516ns(64.906%), Route: 0.279ns(35.094%) + Data arrival time 6.024 Logic Levels: 1 + Logic: 0.451ns(70.359%), Route: 0.190ns(29.641%) ---------------------------------------------------------------------------------------------------- Clock clk_25m (rising edge) 0.000 0.000 r @@ -2893,33 +2908,33 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT3 td 0.111 3.214 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 net (fanout=1) 1.078 4.292 clk_25m - USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 1.585 5.877 ntclkbufg_7 - CLMA_182_17/CLK r u_ov5640/coms1_reg_config/clock_20k_cnt[5]/opit_0_inv/CLK + USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 1.585 5.877 ntclkbufg_8 + CLMS_118_13/CLK r u_ov5640/coms1_reg_config/clock_20k_cnt[1]/opit_0_inv/CLK clock pessimism -0.494 5.383 clock uncertainty 0.000 5.383 - Hold time 0.053 5.436 + Hold time -0.014 5.369 - Data required time 5.436 + Data required time 5.369 ---------------------------------------------------------------------------------------------------- - Data required time 5.436 - Data arrival time 6.178 + Data required time 5.369 + Data arrival time 6.024 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.742 + Slack (MET) 0.655 ==================================================================================================== ==================================================================================================== Startpoint : ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK -Endpoint : ms72xx_ctl/ms7200_ctl/freq_ensure/opit_0_L5Q_perm/L4 +Endpoint : ms72xx_ctl/ms7200_ctl/addr[0]/opit_0_inv_L5Q_perm/CE Path Group : clk_10m Path Type : max (slow corner) Path Class : sequential timing path Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.378 - Launch Clock Delay : 5.873 - Clock Pessimism Removal : 0.459 + Capture Clock Delay : 5.499 + Launch Clock Delay : 5.996 + Clock Pessimism Removal : 0.461 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -2933,28 +2948,28 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT4 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 net (fanout=1) 1.078 4.288 clk_10m - USCM_84_110/CLK_USCM td 0.000 4.288 r clkbufg_3/gopclkbufg/CLKOUT - net (fanout=235) 1.585 5.873 ntclkbufg_3 - CLMS_242_113/CLK r ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK - - CLMS_242_113/Q3 tco 0.288 6.161 r ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/Q - net (fanout=3) 0.420 6.581 ms72xx_ctl/ms7200_ctl/dri_cnt [4] - CLMS_246_113/Y2 td 0.487 7.068 r ms72xx_ctl/ms7200_ctl/N8_3/gateop_perm/Z - net (fanout=1) 0.120 7.188 ms72xx_ctl/ms7200_ctl/_N95853 - CLMS_246_113/Y0 td 0.210 7.398 r ms72xx_ctl/ms7200_ctl/N1872_5/gateop_perm/Z - net (fanout=6) 0.421 7.819 ms72xx_ctl/ms7200_ctl/_N95857 - CLMS_242_117/Y1 td 0.304 8.123 r ms72xx_ctl/ms7200_ctl/N2053_1/gateop_perm/Z - net (fanout=15) 0.790 8.913 ms72xx_ctl/ms7200_ctl/N261 - CLMA_226_104/Y1 td 0.212 9.125 r ms72xx_ctl/ms7200_ctl/N40_9/gateop_perm/Z - net (fanout=4) 0.550 9.675 ms72xx_ctl/ms7200_ctl/N2093 [4] - CLMA_230_108/Y0 td 0.210 9.885 r ms72xx_ctl/ms7200_ctl/state_reg[1]/opit_0_inv_L5Q_perm/Z - net (fanout=2) 0.608 10.493 ms72xx_ctl/ms7200_ctl/state_n [1] - CLMS_226_105/Y0 td 0.487 10.980 r ms72xx_ctl/ms7200_ctl/N1797/gateop_perm/Z - net (fanout=1) 0.412 11.392 ms72xx_ctl/ms7200_ctl/N1797 - CLMA_230_105/A4 r ms72xx_ctl/ms7200_ctl/freq_ensure/opit_0_L5Q_perm/L4 - - Data arrival time 11.392 Logic Levels: 6 - Logic: 2.198ns(39.826%), Route: 3.321ns(60.174%) + USCM_84_110/CLK_USCM td 0.000 4.288 r clkbufg_4/gopclkbufg/CLKOUT + net (fanout=235) 1.708 5.996 ntclkbufg_4 + CLMS_218_329/CLK r ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK + + CLMS_218_329/Q2 tco 0.290 6.286 r ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/Q + net (fanout=3) 0.271 6.557 ms72xx_ctl/ms7200_ctl/dri_cnt [4] + CLMS_218_333/Y3 td 0.459 7.016 r ms72xx_ctl/ms7200_ctl/N8_3/gateop_perm/Z + net (fanout=1) 0.257 7.273 ms72xx_ctl/ms7200_ctl/_N96627 + CLMS_218_333/Y0 td 0.210 7.483 r ms72xx_ctl/ms7200_ctl/N1872_5/gateop_perm/Z + net (fanout=6) 0.412 7.895 ms72xx_ctl/ms7200_ctl/_N96632 + CLMS_222_329/Y0 td 0.210 8.105 r ms72xx_ctl/ms7200_ctl/N2053_1/gateop_perm/Z + net (fanout=15) 0.564 8.669 ms72xx_ctl/ms7200_ctl/N261 + CLMS_214_321/Y0 td 0.320 8.989 r ms72xx_ctl/ms7200_ctl/N40_9/gateop_perm/Z + net (fanout=4) 0.548 9.537 ms72xx_ctl/ms7200_ctl/N2093 [4] + CLMA_222_324/Y1 td 0.212 9.749 r ms72xx_ctl/ms7200_ctl/N1955/gateop_perm/Z + net (fanout=12) 0.560 10.309 ms72xx_ctl/ms7200_ctl/N1955 + CLMA_230_324/CECO td 0.184 10.493 r ms72xx_ctl/ms7200_ctl/data_in[5]/opit_0_inv_L5Q_perm/CEOUT + net (fanout=4) 0.000 10.493 ntR1800 + CLMA_230_328/CECI r ms72xx_ctl/ms7200_ctl/addr[0]/opit_0_inv_L5Q_perm/CE + + Data arrival time 10.493 Logic Levels: 6 + Logic: 1.885ns(41.917%), Route: 2.612ns(58.083%) ---------------------------------------------------------------------------------------------------- Clock clk_10m (rising edge) 100.000 100.000 r @@ -2966,33 +2981,33 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi net (fanout=1) 0.758 102.688 _N69 PLL_158_55/CLK_OUT4 td 0.100 102.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 net (fanout=1) 1.059 103.847 clk_10m - USCM_84_110/CLK_USCM td 0.000 103.847 r clkbufg_3/gopclkbufg/CLKOUT - net (fanout=235) 1.531 105.378 ntclkbufg_3 - CLMA_230_105/CLK r ms72xx_ctl/ms7200_ctl/freq_ensure/opit_0_L5Q_perm/CLK - clock pessimism 0.459 105.837 - clock uncertainty -0.150 105.687 + USCM_84_110/CLK_USCM td 0.000 103.847 r clkbufg_4/gopclkbufg/CLKOUT + net (fanout=235) 1.652 105.499 ntclkbufg_4 + CLMA_230_328/CLK r ms72xx_ctl/ms7200_ctl/addr[0]/opit_0_inv_L5Q_perm/CLK + clock pessimism 0.461 105.960 + clock uncertainty -0.150 105.810 - Setup time -0.121 105.566 + Setup time -0.729 105.081 - Data required time 105.566 + Data required time 105.081 ---------------------------------------------------------------------------------------------------- - Data required time 105.566 - Data arrival time 11.392 + Data required time 105.081 + Data arrival time 10.493 ---------------------------------------------------------------------------------------------------- - Slack (MET) 94.174 + Slack (MET) 94.588 ==================================================================================================== ==================================================================================================== Startpoint : ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK -Endpoint : ms72xx_ctl/ms7200_ctl/freq_rec_2d[16]/opit_0/CE +Endpoint : ms72xx_ctl/ms7200_ctl/addr[4]/opit_0_inv_L5Q_perm/CE Path Group : clk_10m Path Type : max (slow corner) Path Class : sequential timing path Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.378 - Launch Clock Delay : 5.873 - Clock Pessimism Removal : 0.459 + Capture Clock Delay : 5.499 + Launch Clock Delay : 5.996 + Clock Pessimism Removal : 0.461 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -3006,28 +3021,28 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT4 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 net (fanout=1) 1.078 4.288 clk_10m - USCM_84_110/CLK_USCM td 0.000 4.288 r clkbufg_3/gopclkbufg/CLKOUT - net (fanout=235) 1.585 5.873 ntclkbufg_3 - CLMS_242_113/CLK r ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK - - CLMS_242_113/Q3 tco 0.288 6.161 r ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/Q - net (fanout=3) 0.420 6.581 ms72xx_ctl/ms7200_ctl/dri_cnt [4] - CLMS_246_113/Y2 td 0.487 7.068 r ms72xx_ctl/ms7200_ctl/N8_3/gateop_perm/Z - net (fanout=1) 0.120 7.188 ms72xx_ctl/ms7200_ctl/_N95853 - CLMS_246_113/Y0 td 0.210 7.398 r ms72xx_ctl/ms7200_ctl/N1872_5/gateop_perm/Z - net (fanout=6) 0.421 7.819 ms72xx_ctl/ms7200_ctl/_N95857 - CLMS_242_117/Y1 td 0.304 8.123 r ms72xx_ctl/ms7200_ctl/N2053_1/gateop_perm/Z - net (fanout=15) 0.790 8.913 ms72xx_ctl/ms7200_ctl/N261 - CLMA_226_104/Y1 td 0.212 9.125 r ms72xx_ctl/ms7200_ctl/N40_9/gateop_perm/Z - net (fanout=4) 0.550 9.675 ms72xx_ctl/ms7200_ctl/N2093 [4] - CLMA_230_108/Y0 td 0.210 9.885 r ms72xx_ctl/ms7200_ctl/state_reg[1]/opit_0_inv_L5Q_perm/Z - net (fanout=2) 0.656 10.541 ms72xx_ctl/ms7200_ctl/state_n [1] - CLMS_226_105/Y1 td 0.197 10.738 f ms72xx_ctl/ms7200_ctl/N8_7/gateop_perm/Z - net (fanout=3) 0.102 10.840 ms72xx_ctl/ms7200_ctl/N8 - CLMS_226_105/CE f ms72xx_ctl/ms7200_ctl/freq_rec_2d[16]/opit_0/CE - - Data arrival time 10.840 Logic Levels: 6 - Logic: 1.908ns(38.414%), Route: 3.059ns(61.586%) + USCM_84_110/CLK_USCM td 0.000 4.288 r clkbufg_4/gopclkbufg/CLKOUT + net (fanout=235) 1.708 5.996 ntclkbufg_4 + CLMS_218_329/CLK r ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK + + CLMS_218_329/Q2 tco 0.290 6.286 r ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/Q + net (fanout=3) 0.271 6.557 ms72xx_ctl/ms7200_ctl/dri_cnt [4] + CLMS_218_333/Y3 td 0.459 7.016 r ms72xx_ctl/ms7200_ctl/N8_3/gateop_perm/Z + net (fanout=1) 0.257 7.273 ms72xx_ctl/ms7200_ctl/_N96627 + CLMS_218_333/Y0 td 0.210 7.483 r ms72xx_ctl/ms7200_ctl/N1872_5/gateop_perm/Z + net (fanout=6) 0.412 7.895 ms72xx_ctl/ms7200_ctl/_N96632 + CLMS_222_329/Y0 td 0.210 8.105 r ms72xx_ctl/ms7200_ctl/N2053_1/gateop_perm/Z + net (fanout=15) 0.564 8.669 ms72xx_ctl/ms7200_ctl/N261 + CLMS_214_321/Y0 td 0.320 8.989 r ms72xx_ctl/ms7200_ctl/N40_9/gateop_perm/Z + net (fanout=4) 0.548 9.537 ms72xx_ctl/ms7200_ctl/N2093 [4] + CLMA_222_324/Y1 td 0.212 9.749 r ms72xx_ctl/ms7200_ctl/N1955/gateop_perm/Z + net (fanout=12) 0.560 10.309 ms72xx_ctl/ms7200_ctl/N1955 + CLMA_230_324/CECO td 0.184 10.493 r ms72xx_ctl/ms7200_ctl/data_in[5]/opit_0_inv_L5Q_perm/CEOUT + net (fanout=4) 0.000 10.493 ntR1800 + CLMA_230_328/CECI r ms72xx_ctl/ms7200_ctl/addr[4]/opit_0_inv_L5Q_perm/CE + + Data arrival time 10.493 Logic Levels: 6 + Logic: 1.885ns(41.917%), Route: 2.612ns(58.083%) ---------------------------------------------------------------------------------------------------- Clock clk_10m (rising edge) 100.000 100.000 r @@ -3039,33 +3054,33 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi net (fanout=1) 0.758 102.688 _N69 PLL_158_55/CLK_OUT4 td 0.100 102.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 net (fanout=1) 1.059 103.847 clk_10m - USCM_84_110/CLK_USCM td 0.000 103.847 r clkbufg_3/gopclkbufg/CLKOUT - net (fanout=235) 1.531 105.378 ntclkbufg_3 - CLMS_226_105/CLK r ms72xx_ctl/ms7200_ctl/freq_rec_2d[16]/opit_0/CLK - clock pessimism 0.459 105.837 - clock uncertainty -0.150 105.687 + USCM_84_110/CLK_USCM td 0.000 103.847 r clkbufg_4/gopclkbufg/CLKOUT + net (fanout=235) 1.652 105.499 ntclkbufg_4 + CLMA_230_328/CLK r ms72xx_ctl/ms7200_ctl/addr[4]/opit_0_inv_L5Q_perm/CLK + clock pessimism 0.461 105.960 + clock uncertainty -0.150 105.810 - Setup time -0.617 105.070 + Setup time -0.729 105.081 - Data required time 105.070 + Data required time 105.081 ---------------------------------------------------------------------------------------------------- - Data required time 105.070 - Data arrival time 10.840 + Data required time 105.081 + Data arrival time 10.493 ---------------------------------------------------------------------------------------------------- - Slack (MET) 94.230 + Slack (MET) 94.588 ==================================================================================================== ==================================================================================================== Startpoint : ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK -Endpoint : ms72xx_ctl/ms7200_ctl/freq_rec_2d[17]/opit_0/CE +Endpoint : ms72xx_ctl/ms7200_ctl/addr[5]/opit_0_inv_L5Q_perm/CE Path Group : clk_10m Path Type : max (slow corner) Path Class : sequential timing path Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.378 - Launch Clock Delay : 5.873 - Clock Pessimism Removal : 0.459 + Capture Clock Delay : 5.499 + Launch Clock Delay : 5.996 + Clock Pessimism Removal : 0.461 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -3079,28 +3094,28 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT4 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 net (fanout=1) 1.078 4.288 clk_10m - USCM_84_110/CLK_USCM td 0.000 4.288 r clkbufg_3/gopclkbufg/CLKOUT - net (fanout=235) 1.585 5.873 ntclkbufg_3 - CLMS_242_113/CLK r ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK - - CLMS_242_113/Q3 tco 0.288 6.161 r ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/Q - net (fanout=3) 0.420 6.581 ms72xx_ctl/ms7200_ctl/dri_cnt [4] - CLMS_246_113/Y2 td 0.487 7.068 r ms72xx_ctl/ms7200_ctl/N8_3/gateop_perm/Z - net (fanout=1) 0.120 7.188 ms72xx_ctl/ms7200_ctl/_N95853 - CLMS_246_113/Y0 td 0.210 7.398 r ms72xx_ctl/ms7200_ctl/N1872_5/gateop_perm/Z - net (fanout=6) 0.421 7.819 ms72xx_ctl/ms7200_ctl/_N95857 - CLMS_242_117/Y1 td 0.304 8.123 r ms72xx_ctl/ms7200_ctl/N2053_1/gateop_perm/Z - net (fanout=15) 0.790 8.913 ms72xx_ctl/ms7200_ctl/N261 - CLMA_226_104/Y1 td 0.212 9.125 r ms72xx_ctl/ms7200_ctl/N40_9/gateop_perm/Z - net (fanout=4) 0.550 9.675 ms72xx_ctl/ms7200_ctl/N2093 [4] - CLMA_230_108/Y0 td 0.210 9.885 r ms72xx_ctl/ms7200_ctl/state_reg[1]/opit_0_inv_L5Q_perm/Z - net (fanout=2) 0.656 10.541 ms72xx_ctl/ms7200_ctl/state_n [1] - CLMS_226_105/Y1 td 0.197 10.738 f ms72xx_ctl/ms7200_ctl/N8_7/gateop_perm/Z - net (fanout=3) 0.102 10.840 ms72xx_ctl/ms7200_ctl/N8 - CLMS_226_105/CE f ms72xx_ctl/ms7200_ctl/freq_rec_2d[17]/opit_0/CE - - Data arrival time 10.840 Logic Levels: 6 - Logic: 1.908ns(38.414%), Route: 3.059ns(61.586%) + USCM_84_110/CLK_USCM td 0.000 4.288 r clkbufg_4/gopclkbufg/CLKOUT + net (fanout=235) 1.708 5.996 ntclkbufg_4 + CLMS_218_329/CLK r ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK + + CLMS_218_329/Q2 tco 0.290 6.286 r ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/Q + net (fanout=3) 0.271 6.557 ms72xx_ctl/ms7200_ctl/dri_cnt [4] + CLMS_218_333/Y3 td 0.459 7.016 r ms72xx_ctl/ms7200_ctl/N8_3/gateop_perm/Z + net (fanout=1) 0.257 7.273 ms72xx_ctl/ms7200_ctl/_N96627 + CLMS_218_333/Y0 td 0.210 7.483 r ms72xx_ctl/ms7200_ctl/N1872_5/gateop_perm/Z + net (fanout=6) 0.412 7.895 ms72xx_ctl/ms7200_ctl/_N96632 + CLMS_222_329/Y0 td 0.210 8.105 r ms72xx_ctl/ms7200_ctl/N2053_1/gateop_perm/Z + net (fanout=15) 0.564 8.669 ms72xx_ctl/ms7200_ctl/N261 + CLMS_214_321/Y0 td 0.320 8.989 r ms72xx_ctl/ms7200_ctl/N40_9/gateop_perm/Z + net (fanout=4) 0.548 9.537 ms72xx_ctl/ms7200_ctl/N2093 [4] + CLMA_222_324/Y1 td 0.212 9.749 r ms72xx_ctl/ms7200_ctl/N1955/gateop_perm/Z + net (fanout=12) 0.560 10.309 ms72xx_ctl/ms7200_ctl/N1955 + CLMA_230_324/CECO td 0.184 10.493 r ms72xx_ctl/ms7200_ctl/data_in[5]/opit_0_inv_L5Q_perm/CEOUT + net (fanout=4) 0.000 10.493 ntR1800 + CLMA_230_328/CECI r ms72xx_ctl/ms7200_ctl/addr[5]/opit_0_inv_L5Q_perm/CE + + Data arrival time 10.493 Logic Levels: 6 + Logic: 1.885ns(41.917%), Route: 2.612ns(58.083%) ---------------------------------------------------------------------------------------------------- Clock clk_10m (rising edge) 100.000 100.000 r @@ -3112,33 +3127,33 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi net (fanout=1) 0.758 102.688 _N69 PLL_158_55/CLK_OUT4 td 0.100 102.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 net (fanout=1) 1.059 103.847 clk_10m - USCM_84_110/CLK_USCM td 0.000 103.847 r clkbufg_3/gopclkbufg/CLKOUT - net (fanout=235) 1.531 105.378 ntclkbufg_3 - CLMS_226_105/CLK r ms72xx_ctl/ms7200_ctl/freq_rec_2d[17]/opit_0/CLK - clock pessimism 0.459 105.837 - clock uncertainty -0.150 105.687 + USCM_84_110/CLK_USCM td 0.000 103.847 r clkbufg_4/gopclkbufg/CLKOUT + net (fanout=235) 1.652 105.499 ntclkbufg_4 + CLMA_230_328/CLK r ms72xx_ctl/ms7200_ctl/addr[5]/opit_0_inv_L5Q_perm/CLK + clock pessimism 0.461 105.960 + clock uncertainty -0.150 105.810 - Setup time -0.617 105.070 + Setup time -0.729 105.081 - Data required time 105.070 + Data required time 105.081 ---------------------------------------------------------------------------------------------------- - Data required time 105.070 - Data arrival time 10.840 + Data required time 105.081 + Data arrival time 10.493 ---------------------------------------------------------------------------------------------------- - Slack (MET) 94.230 + Slack (MET) 94.588 ==================================================================================================== ==================================================================================================== -Startpoint : ms72xx_ctl/iic_dri_tx/receiv_data[1]/opit_0_inv/CLK -Endpoint : ms72xx_ctl/iic_dri_tx/data_out[1]/opit_0/D +Startpoint : ms72xx_ctl/iic_dri_tx/receiv_data[5]/opit_0_inv/CLK +Endpoint : ms72xx_ctl/iic_dri_tx/data_out[5]/opit_0/D Path Group : clk_10m Path Type : min (slow corner) Path Class : sequential timing path Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.873 - Launch Clock Delay : 5.378 - Clock Pessimism Removal : -0.466 + Capture Clock Delay : 5.996 + Launch Clock Delay : 5.499 + Clock Pessimism Removal : -0.468 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -3152,16 +3167,16 @@ Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.758 2.688 _N69 PLL_158_55/CLK_OUT4 td 0.100 2.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 net (fanout=1) 1.059 3.847 clk_10m - USCM_84_110/CLK_USCM td 0.000 3.847 r clkbufg_3/gopclkbufg/CLKOUT - net (fanout=235) 1.531 5.378 ntclkbufg_3 - CLMS_202_113/CLK r ms72xx_ctl/iic_dri_tx/receiv_data[1]/opit_0_inv/CLK + USCM_84_110/CLK_USCM td 0.000 3.847 r clkbufg_4/gopclkbufg/CLKOUT + net (fanout=235) 1.652 5.499 ntclkbufg_4 + CLMA_194_305/CLK r ms72xx_ctl/iic_dri_tx/receiv_data[5]/opit_0_inv/CLK - CLMS_202_113/Q0 tco 0.226 5.604 r ms72xx_ctl/iic_dri_tx/receiv_data[1]/opit_0_inv/Q - net (fanout=2) 0.103 5.707 ms72xx_ctl/iic_dri_tx/receiv_data [1] - CLMA_202_112/M0 r ms72xx_ctl/iic_dri_tx/data_out[1]/opit_0/D + CLMA_194_305/Y2 tco 0.284 5.783 f ms72xx_ctl/iic_dri_tx/receiv_data[5]/opit_0_inv/Q + net (fanout=2) 0.085 5.868 ms72xx_ctl/iic_dri_tx/receiv_data [5] + CLMA_194_304/CD f ms72xx_ctl/iic_dri_tx/data_out[5]/opit_0/D - Data arrival time 5.707 Logic Levels: 0 - Logic: 0.226ns(68.693%), Route: 0.103ns(31.307%) + Data arrival time 5.868 Logic Levels: 0 + Logic: 0.284ns(76.965%), Route: 0.085ns(23.035%) ---------------------------------------------------------------------------------------------------- Clock clk_10m (rising edge) 0.000 0.000 r @@ -3173,33 +3188,33 @@ Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT4 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 net (fanout=1) 1.078 4.288 clk_10m - USCM_84_110/CLK_USCM td 0.000 4.288 r clkbufg_3/gopclkbufg/CLKOUT - net (fanout=235) 1.585 5.873 ntclkbufg_3 - CLMA_202_112/CLK r ms72xx_ctl/iic_dri_tx/data_out[1]/opit_0/CLK - clock pessimism -0.466 5.407 - clock uncertainty 0.000 5.407 + USCM_84_110/CLK_USCM td 0.000 4.288 r clkbufg_4/gopclkbufg/CLKOUT + net (fanout=235) 1.708 5.996 ntclkbufg_4 + CLMA_194_304/CLK r ms72xx_ctl/iic_dri_tx/data_out[5]/opit_0/CLK + clock pessimism -0.468 5.528 + clock uncertainty 0.000 5.528 - Hold time -0.014 5.393 + Hold time 0.053 5.581 - Data required time 5.393 + Data required time 5.581 ---------------------------------------------------------------------------------------------------- - Data required time 5.393 - Data arrival time 5.707 + Data required time 5.581 + Data arrival time 5.868 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.314 + Slack (MET) 0.287 ==================================================================================================== ==================================================================================================== -Startpoint : ms72xx_ctl/ms7200_ctl/cmd_index[5]/opit_0_inv_A2Q21/CLK -Endpoint : ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/ADB0[9] +Startpoint : ms72xx_ctl/iic_dri_tx/receiv_data[1]/opit_0_inv/CLK +Endpoint : ms72xx_ctl/iic_dri_tx/data_out[1]/opit_0/D Path Group : clk_10m Path Type : min (slow corner) Path Class : sequential timing path -Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.873 - Launch Clock Delay : 5.378 - Clock Pessimism Removal : -0.459 +Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 5.996 + Launch Clock Delay : 5.499 + Clock Pessimism Removal : -0.468 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -3213,16 +3228,16 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.758 2.688 _N69 PLL_158_55/CLK_OUT4 td 0.100 2.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 net (fanout=1) 1.059 3.847 clk_10m - USCM_84_110/CLK_USCM td 0.000 3.847 r clkbufg_3/gopclkbufg/CLKOUT - net (fanout=235) 1.531 5.378 ntclkbufg_3 - CLMA_230_117/CLK r ms72xx_ctl/ms7200_ctl/cmd_index[5]/opit_0_inv_A2Q21/CLK + USCM_84_110/CLK_USCM td 0.000 3.847 r clkbufg_4/gopclkbufg/CLKOUT + net (fanout=235) 1.652 5.499 ntclkbufg_4 + CLMA_194_305/CLK r ms72xx_ctl/iic_dri_tx/receiv_data[1]/opit_0_inv/CLK - CLMA_230_117/Q0 tco 0.226 5.604 r ms72xx_ctl/ms7200_ctl/cmd_index[5]/opit_0_inv_A2Q21/Q0 - net (fanout=3) 0.220 5.824 ms72xx_ctl/ms7200_ctl/cmd_index [4] - DRM_234_108/ADB0[9] r ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/ADB0[9] + CLMA_194_305/Q0 tco 0.226 5.725 r ms72xx_ctl/iic_dri_tx/receiv_data[1]/opit_0_inv/Q + net (fanout=2) 0.103 5.828 ms72xx_ctl/iic_dri_tx/receiv_data [1] + CLMA_194_304/M0 r ms72xx_ctl/iic_dri_tx/data_out[1]/opit_0/D - Data arrival time 5.824 Logic Levels: 0 - Logic: 0.226ns(50.673%), Route: 0.220ns(49.327%) + Data arrival time 5.828 Logic Levels: 0 + Logic: 0.226ns(68.693%), Route: 0.103ns(31.307%) ---------------------------------------------------------------------------------------------------- Clock clk_10m (rising edge) 0.000 0.000 r @@ -3234,33 +3249,33 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT4 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 net (fanout=1) 1.078 4.288 clk_10m - USCM_84_110/CLK_USCM td 0.000 4.288 r clkbufg_3/gopclkbufg/CLKOUT - net (fanout=235) 1.585 5.873 ntclkbufg_3 - DRM_234_108/CLKB[0] r ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKB[0] - clock pessimism -0.459 5.414 - clock uncertainty 0.000 5.414 + USCM_84_110/CLK_USCM td 0.000 4.288 r clkbufg_4/gopclkbufg/CLKOUT + net (fanout=235) 1.708 5.996 ntclkbufg_4 + CLMA_194_304/CLK r ms72xx_ctl/iic_dri_tx/data_out[1]/opit_0/CLK + clock pessimism -0.468 5.528 + clock uncertainty 0.000 5.528 - Hold time 0.079 5.493 + Hold time -0.014 5.514 - Data required time 5.493 + Data required time 5.514 ---------------------------------------------------------------------------------------------------- - Data required time 5.493 - Data arrival time 5.824 + Data required time 5.514 + Data arrival time 5.828 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.331 + Slack (MET) 0.314 ==================================================================================================== ==================================================================================================== -Startpoint : ms72xx_ctl/ms7200_ctl/cmd_index[5]/opit_0_inv_A2Q21/CLK -Endpoint : ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/ADA0[9] +Startpoint : ms72xx_ctl/iic_dri_tx/receiv_data[7]/opit_0_inv/CLK +Endpoint : ms72xx_ctl/iic_dri_tx/data_out[7]/opit_0/D Path Group : clk_10m Path Type : min (slow corner) Path Class : sequential timing path -Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.873 - Launch Clock Delay : 5.378 - Clock Pessimism Removal : -0.459 +Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 5.996 + Launch Clock Delay : 5.499 + Clock Pessimism Removal : -0.468 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -3274,16 +3289,16 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.758 2.688 _N69 PLL_158_55/CLK_OUT4 td 0.100 2.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 net (fanout=1) 1.059 3.847 clk_10m - USCM_84_110/CLK_USCM td 0.000 3.847 r clkbufg_3/gopclkbufg/CLKOUT - net (fanout=235) 1.531 5.378 ntclkbufg_3 - CLMA_230_117/CLK r ms72xx_ctl/ms7200_ctl/cmd_index[5]/opit_0_inv_A2Q21/CLK + USCM_84_110/CLK_USCM td 0.000 3.847 r clkbufg_4/gopclkbufg/CLKOUT + net (fanout=235) 1.652 5.499 ntclkbufg_4 + CLMA_194_305/CLK r ms72xx_ctl/iic_dri_tx/receiv_data[7]/opit_0_inv/CLK - CLMA_230_117/Q0 tco 0.222 5.600 f ms72xx_ctl/ms7200_ctl/cmd_index[5]/opit_0_inv_A2Q21/Q0 - net (fanout=3) 0.315 5.915 ms72xx_ctl/ms7200_ctl/cmd_index [4] - DRM_234_108/ADA0[9] f ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/ADA0[9] + CLMA_194_305/Q2 tco 0.224 5.723 f ms72xx_ctl/iic_dri_tx/receiv_data[7]/opit_0_inv/Q + net (fanout=1) 0.192 5.915 ms72xx_ctl/iic_dri_tx/receiv_data [7] + CLMA_194_304/AD f ms72xx_ctl/iic_dri_tx/data_out[7]/opit_0/D Data arrival time 5.915 Logic Levels: 0 - Logic: 0.222ns(41.341%), Route: 0.315ns(58.659%) + Logic: 0.224ns(53.846%), Route: 0.192ns(46.154%) ---------------------------------------------------------------------------------------------------- Clock clk_10m (rising edge) 0.000 0.000 r @@ -3295,38 +3310,38 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT4 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 net (fanout=1) 1.078 4.288 clk_10m - USCM_84_110/CLK_USCM td 0.000 4.288 r clkbufg_3/gopclkbufg/CLKOUT - net (fanout=235) 1.585 5.873 ntclkbufg_3 - DRM_234_108/CLKA[0] r ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKA[0] - clock pessimism -0.459 5.414 - clock uncertainty 0.000 5.414 + USCM_84_110/CLK_USCM td 0.000 4.288 r clkbufg_4/gopclkbufg/CLKOUT + net (fanout=235) 1.708 5.996 ntclkbufg_4 + CLMA_194_304/CLK r ms72xx_ctl/iic_dri_tx/data_out[7]/opit_0/CLK + clock pessimism -0.468 5.528 + clock uncertainty 0.000 5.528 - Hold time 0.161 5.575 + Hold time 0.053 5.581 - Data required time 5.575 + Data required time 5.581 ---------------------------------------------------------------------------------------------------- - Data required time 5.575 + Data required time 5.581 Data arrival time 5.915 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.340 + Slack (MET) 0.334 ==================================================================================================== ==================================================================================================== -Startpoint : u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK -Endpoint : udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[0]/opit_0_L5Q_perm/CE -Path Group : clk_720p60Hz +Startpoint : u_zoom_image/mult_fra1_0/N2/gopapm/CLK +Endpoint : u_zoom_image/mult_image_g1_0/N2/gopapm/X[3] +Path Group : clk_1080p60Hz Path Type : max (slow corner) Path Class : sequential timing path -Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 8.831 - Launch Clock Delay : 9.434 - Clock Pessimism Removal : 0.567 +Clock Skew : -0.177 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 8.835 + Launch Clock Delay : 9.563 + Clock Pessimism Removal : 0.551 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_720p60Hz (rising edge) 0.000 0.000 r + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 2.166 2.240 r clk_ibuf/opit_0/O @@ -3336,79 +3351,406 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 1.078 4.288 rd3_clk USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.861 6.149 ntR3907 - PLL_158_303/CLK_OUT1 td 0.101 6.250 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.599 7.849 nt_pix_clk - USCM_84_117/CLK_USCM td 0.000 7.849 r clkbufg_2/gopclkbufg/CLKOUT - net (fanout=1635) 1.585 9.434 ntclkbufg_2 - CLMS_186_117/CLK r u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK - - CLMS_186_117/Q2 tco 0.290 9.724 r u_sync_vg/pos_y[8]/opit_0_A2Q21/Q0 - net (fanout=1) 0.857 10.581 pos_y[7] - CLMA_186_116/COUT td 0.515 11.096 r udp_osd_inst/N29.eq_2/gateop_A2/Cout - net (fanout=1) 0.000 11.096 udp_osd_inst/N29.co [6] - CLMA_186_120/Y1 td 0.498 11.594 r udp_osd_inst/N29.eq_4/gateop_A2/Y1 - net (fanout=5) 0.410 12.004 udp_osd_inst/N29 - CLMA_190_120/Y3 td 0.287 12.291 r udp_osd_inst/N69_5/gateop_perm/Z - net (fanout=2) 0.551 12.842 udp_osd_inst/char_osd_inst/pixels_shifter_inst/N64 - CLMA_186_112/Y1 td 0.212 13.054 r udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/gateop_perm/Z - net (fanout=2) 0.401 13.455 udp_osd_inst/char_osd_inst/row_pixels_ready - CLMA_186_108/Y2 td 0.210 13.665 r udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/gateop_perm/Z - net (fanout=6) 0.587 14.252 udp_osd_inst/char_osd_inst/char_next - CLMA_182_88/Y3 td 0.210 14.462 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N79/gateop_perm/Z - net (fanout=1) 0.253 14.715 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N79 - CLMA_182_88/Y2 td 0.210 14.925 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N358_5/gateop_perm/Z - net (fanout=3) 0.548 15.473 udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N96518 - CLMA_186_80/Y0 td 0.341 15.814 f udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786/gateop_perm/Z - net (fanout=1) 0.540 16.354 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786 - CLMA_182_73/CECO td 0.170 16.524 f udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[4]/opit_0_A2Q21/CEOUT - net (fanout=4) 0.000 16.524 ntR2038 - CLMA_182_77/CECI f udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[0]/opit_0_L5Q_perm/CE - - Data arrival time 16.524 Logic Levels: 9 - Logic: 2.943ns(41.509%), Route: 4.147ns(58.491%) + net (fanout=1) 1.861 6.149 ntR3950 + PLL_158_303/CLK_OUT0 td 0.107 6.256 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 1.599 7.855 zoom_clk + USCM_84_118/CLK_USCM td 0.000 7.855 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 1.708 9.563 ntclkbufg_3 + APM_206_264/CLK r u_zoom_image/mult_fra1_0/N2/gopapm/CLK + + APM_206_264/P[34] tco 1.067 10.630 f u_zoom_image/mult_fra1_0/N2/gopapm/P[10] + net (fanout=3) 2.016 12.646 u_zoom_image/coe_mult_p1_0 [10] + APM_206_140/X[3] f u_zoom_image/mult_image_g1_0/N2/gopapm/X[3] + + Data arrival time 12.646 Logic Levels: 0 + Logic: 1.067ns(34.609%), Route: 2.016ns(65.391%) ---------------------------------------------------------------------------------------------------- - Clock clk_720p60Hz (rising edge) 13.473 13.473 r - P20 0.000 13.473 r clk (port) - net (fanout=1) 0.074 13.547 clk - IOBS_LR_328_209/DIN td 1.808 15.355 r clk_ibuf/opit_0/O - net (fanout=1) 0.000 15.355 clk_ibuf/ntD - IOL_327_210/INCK td 0.048 15.403 r clk_ibuf/opit_1/INCK - net (fanout=1) 0.758 16.161 _N69 - PLL_158_55/CLK_OUT0 td 0.100 16.261 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 - net (fanout=2) 1.059 17.320 rd3_clk - USCM_84_154/CLK_USCM td 0.000 17.320 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.786 19.106 ntR3907 - PLL_158_303/CLK_OUT1 td 0.096 19.202 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.571 20.773 nt_pix_clk - USCM_84_117/CLK_USCM td 0.000 20.773 r clkbufg_2/gopclkbufg/CLKOUT - net (fanout=1635) 1.531 22.304 ntclkbufg_2 - CLMA_182_77/CLK r udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[0]/opit_0_L5Q_perm/CLK - clock pessimism 0.567 22.871 - clock uncertainty -0.150 22.721 + Clock clk_1080p60Hz (rising edge) 6.736 6.736 r + P20 0.000 6.736 r clk (port) + net (fanout=1) 0.074 6.810 clk + IOBS_LR_328_209/DIN td 1.808 8.618 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 8.618 clk_ibuf/ntD + IOL_327_210/INCK td 0.048 8.666 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.758 9.424 _N69 + PLL_158_55/CLK_OUT0 td 0.100 9.524 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 1.059 10.583 rd3_clk + USCM_84_154/CLK_USCM td 0.000 10.583 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.786 12.369 ntR3950 + PLL_158_303/CLK_OUT0 td 0.100 12.469 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 1.571 14.040 zoom_clk + USCM_84_118/CLK_USCM td 0.000 14.040 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 1.531 15.571 ntclkbufg_3 + APM_206_140/CLK r u_zoom_image/mult_image_g1_0/N2/gopapm/CLK + clock pessimism 0.551 16.122 + clock uncertainty -0.150 15.972 - Setup time -0.747 21.974 + Setup time -2.243 13.729 - Data required time 21.974 + Data required time 13.729 ---------------------------------------------------------------------------------------------------- - Data required time 21.974 - Data arrival time 16.524 + Data required time 13.729 + Data arrival time 12.646 ---------------------------------------------------------------------------------------------------- - Slack (MET) 5.450 + Slack (MET) 1.083 ==================================================================================================== ==================================================================================================== -Startpoint : u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK -Endpoint : udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[1]/opit_0_L5Q_perm/CE +Startpoint : u_zoom_image/mult_fra1_0/N2/gopapm/CLK +Endpoint : u_zoom_image/mult_image_g1_0/N2/gopapm/X[0] +Path Group : clk_1080p60Hz +Path Type : max (slow corner) +Path Class : sequential timing path +Clock Skew : -0.177 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 8.835 + Launch Clock Delay : 9.563 + Clock Pessimism Removal : 0.551 + + Location Delay Type Incr Path Logical Resource +---------------------------------------------------------------------------------------------------- + + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r + P20 0.000 0.000 r clk (port) + net (fanout=1) 0.074 0.074 clk + IOBS_LR_328_209/DIN td 2.166 2.240 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 2.240 clk_ibuf/ntD + IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.787 3.103 _N69 + PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 1.078 4.288 rd3_clk + USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.861 6.149 ntR3950 + PLL_158_303/CLK_OUT0 td 0.107 6.256 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 1.599 7.855 zoom_clk + USCM_84_118/CLK_USCM td 0.000 7.855 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 1.708 9.563 ntclkbufg_3 + APM_206_264/CLK r u_zoom_image/mult_fra1_0/N2/gopapm/CLK + + APM_206_264/P[31] tco 1.067 10.630 f u_zoom_image/mult_fra1_0/N2/gopapm/P[7] + net (fanout=3) 2.000 12.630 u_zoom_image/coe_mult_p1_0 [7] + APM_206_140/X[0] f u_zoom_image/mult_image_g1_0/N2/gopapm/X[0] + + Data arrival time 12.630 Logic Levels: 0 + Logic: 1.067ns(34.790%), Route: 2.000ns(65.210%) +---------------------------------------------------------------------------------------------------- + + Clock clk_1080p60Hz (rising edge) 6.736 6.736 r + P20 0.000 6.736 r clk (port) + net (fanout=1) 0.074 6.810 clk + IOBS_LR_328_209/DIN td 1.808 8.618 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 8.618 clk_ibuf/ntD + IOL_327_210/INCK td 0.048 8.666 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.758 9.424 _N69 + PLL_158_55/CLK_OUT0 td 0.100 9.524 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 1.059 10.583 rd3_clk + USCM_84_154/CLK_USCM td 0.000 10.583 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.786 12.369 ntR3950 + PLL_158_303/CLK_OUT0 td 0.100 12.469 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 1.571 14.040 zoom_clk + USCM_84_118/CLK_USCM td 0.000 14.040 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 1.531 15.571 ntclkbufg_3 + APM_206_140/CLK r u_zoom_image/mult_image_g1_0/N2/gopapm/CLK + clock pessimism 0.551 16.122 + clock uncertainty -0.150 15.972 + + Setup time -2.243 13.729 + + Data required time 13.729 +---------------------------------------------------------------------------------------------------- + Data required time 13.729 + Data arrival time 12.630 +---------------------------------------------------------------------------------------------------- + Slack (MET) 1.099 +==================================================================================================== + +==================================================================================================== + +Startpoint : u_zoom_image/mult_fra0_0/N2/gopapm/CLK +Endpoint : u_zoom_image/mult_image_g0_0/N2/gopapm/X[1] +Path Group : clk_1080p60Hz +Path Type : max (slow corner) +Path Class : sequential timing path +Clock Skew : -0.177 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 8.835 + Launch Clock Delay : 9.563 + Clock Pessimism Removal : 0.551 + + Location Delay Type Incr Path Logical Resource +---------------------------------------------------------------------------------------------------- + + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r + P20 0.000 0.000 r clk (port) + net (fanout=1) 0.074 0.074 clk + IOBS_LR_328_209/DIN td 2.166 2.240 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 2.240 clk_ibuf/ntD + IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.787 3.103 _N69 + PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 1.078 4.288 rd3_clk + USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.861 6.149 ntR3950 + PLL_158_303/CLK_OUT0 td 0.107 6.256 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 1.599 7.855 zoom_clk + USCM_84_118/CLK_USCM td 0.000 7.855 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 1.708 9.563 ntclkbufg_3 + APM_206_264/CLK r u_zoom_image/mult_fra0_0/N2/gopapm/CLK + + APM_206_264/P[8] tco 1.067 10.630 f u_zoom_image/mult_fra0_0/N2/gopapm/P[8] + net (fanout=3) 1.968 12.598 u_zoom_image/coe_mult_p0_0 [8] + APM_206_128/X[1] f u_zoom_image/mult_image_g0_0/N2/gopapm/X[1] + + Data arrival time 12.598 Logic Levels: 0 + Logic: 1.067ns(35.157%), Route: 1.968ns(64.843%) +---------------------------------------------------------------------------------------------------- + + Clock clk_1080p60Hz (rising edge) 6.736 6.736 r + P20 0.000 6.736 r clk (port) + net (fanout=1) 0.074 6.810 clk + IOBS_LR_328_209/DIN td 1.808 8.618 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 8.618 clk_ibuf/ntD + IOL_327_210/INCK td 0.048 8.666 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.758 9.424 _N69 + PLL_158_55/CLK_OUT0 td 0.100 9.524 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 1.059 10.583 rd3_clk + USCM_84_154/CLK_USCM td 0.000 10.583 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.786 12.369 ntR3950 + PLL_158_303/CLK_OUT0 td 0.100 12.469 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 1.571 14.040 zoom_clk + USCM_84_118/CLK_USCM td 0.000 14.040 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 1.531 15.571 ntclkbufg_3 + APM_206_128/CLK r u_zoom_image/mult_image_g0_0/N2/gopapm/CLK + clock pessimism 0.551 16.122 + clock uncertainty -0.150 15.972 + + Setup time -2.243 13.729 + + Data required time 13.729 +---------------------------------------------------------------------------------------------------- + Data required time 13.729 + Data arrival time 12.598 +---------------------------------------------------------------------------------------------------- + Slack (MET) 1.131 +==================================================================================================== + +==================================================================================================== + +Startpoint : u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK +Endpoint : u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[7] +Path Group : clk_1080p60Hz +Path Type : min (slow corner) +Path Class : sequential timing path +Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 9.440 + Launch Clock Delay : 8.835 + Clock Pessimism Removal : -0.569 + + Location Delay Type Incr Path Logical Resource +---------------------------------------------------------------------------------------------------- + + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r + P20 0.000 0.000 r clk (port) + net (fanout=1) 0.074 0.074 clk + IOBS_LR_328_209/DIN td 1.808 1.882 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 1.882 clk_ibuf/ntD + IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.758 2.688 _N69 + PLL_158_55/CLK_OUT0 td 0.100 2.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 1.059 3.847 rd3_clk + USCM_84_154/CLK_USCM td 0.000 3.847 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.786 5.633 ntR3950 + PLL_158_303/CLK_OUT0 td 0.100 5.733 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 1.571 7.304 zoom_clk + USCM_84_118/CLK_USCM td 0.000 7.304 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 1.531 8.835 ntclkbufg_3 + CLMA_146_76/CLK r u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK + + CLMA_146_76/Q2 tco 0.224 9.059 f u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/Q0 + net (fanout=3) 0.234 9.293 u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/wr_addr [2] + DRM_142_68/ADA0[7] f u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[7] + + Data arrival time 9.293 Logic Levels: 0 + Logic: 0.224ns(48.908%), Route: 0.234ns(51.092%) +---------------------------------------------------------------------------------------------------- + + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r + P20 0.000 0.000 r clk (port) + net (fanout=1) 0.074 0.074 clk + IOBS_LR_328_209/DIN td 2.166 2.240 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 2.240 clk_ibuf/ntD + IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.787 3.103 _N69 + PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 1.078 4.288 rd3_clk + USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.861 6.149 ntR3950 + PLL_158_303/CLK_OUT0 td 0.107 6.256 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 1.599 7.855 zoom_clk + USCM_84_118/CLK_USCM td 0.000 7.855 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 1.585 9.440 ntclkbufg_3 + DRM_142_68/CLKA[0] r u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKA + clock pessimism -0.569 8.871 + clock uncertainty 0.000 8.871 + + Hold time 0.210 9.081 + + Data required time 9.081 +---------------------------------------------------------------------------------------------------- + Data required time 9.081 + Data arrival time 9.293 +---------------------------------------------------------------------------------------------------- + Slack (MET) 0.212 +==================================================================================================== + +==================================================================================================== + +Startpoint : u_zoom_image/wr_addr1[2]/opit_0_inv_A2Q21/CLK +Endpoint : u_zoom_image/zoom_ram1_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/ADA0[5] +Path Group : clk_1080p60Hz +Path Type : min (slow corner) +Path Class : sequential timing path +Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 9.440 + Launch Clock Delay : 8.835 + Clock Pessimism Removal : -0.569 + + Location Delay Type Incr Path Logical Resource +---------------------------------------------------------------------------------------------------- + + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r + P20 0.000 0.000 r clk (port) + net (fanout=1) 0.074 0.074 clk + IOBS_LR_328_209/DIN td 1.808 1.882 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 1.882 clk_ibuf/ntD + IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.758 2.688 _N69 + PLL_158_55/CLK_OUT0 td 0.100 2.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 1.059 3.847 rd3_clk + USCM_84_154/CLK_USCM td 0.000 3.847 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.786 5.633 ntR3950 + PLL_158_303/CLK_OUT0 td 0.100 5.733 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 1.571 7.304 zoom_clk + USCM_84_118/CLK_USCM td 0.000 7.304 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 1.531 8.835 ntclkbufg_3 + CLMS_174_177/CLK r u_zoom_image/wr_addr1[2]/opit_0_inv_A2Q21/CLK + + CLMS_174_177/Q1 tco 0.224 9.059 f u_zoom_image/wr_addr1[2]/opit_0_inv_A2Q21/Q1 + net (fanout=6) 0.221 9.280 u_zoom_image/wr_addr1 [2] + DRM_178_168/ADA0[5] f u_zoom_image/zoom_ram1_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/ADA0[5] + + Data arrival time 9.280 Logic Levels: 0 + Logic: 0.224ns(50.337%), Route: 0.221ns(49.663%) +---------------------------------------------------------------------------------------------------- + + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r + P20 0.000 0.000 r clk (port) + net (fanout=1) 0.074 0.074 clk + IOBS_LR_328_209/DIN td 2.166 2.240 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 2.240 clk_ibuf/ntD + IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.787 3.103 _N69 + PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 1.078 4.288 rd3_clk + USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.861 6.149 ntR3950 + PLL_158_303/CLK_OUT0 td 0.107 6.256 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 1.599 7.855 zoom_clk + USCM_84_118/CLK_USCM td 0.000 7.855 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 1.585 9.440 ntclkbufg_3 + DRM_178_168/CLKA[0] r u_zoom_image/zoom_ram1_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] + clock pessimism -0.569 8.871 + clock uncertainty 0.000 8.871 + + Hold time 0.161 9.032 + + Data required time 9.032 +---------------------------------------------------------------------------------------------------- + Data required time 9.032 + Data arrival time 9.280 +---------------------------------------------------------------------------------------------------- + Slack (MET) 0.248 +==================================================================================================== + +==================================================================================================== + +Startpoint : u_zoom_image/image_valid[2][1]/opit_0/CLK +Endpoint : u_zoom_image/image_valid[3][1]/opit_0/D +Path Group : clk_1080p60Hz +Path Type : min (slow corner) +Path Class : sequential timing path +Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 9.440 + Launch Clock Delay : 8.835 + Clock Pessimism Removal : -0.605 + + Location Delay Type Incr Path Logical Resource +---------------------------------------------------------------------------------------------------- + + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r + P20 0.000 0.000 r clk (port) + net (fanout=1) 0.074 0.074 clk + IOBS_LR_328_209/DIN td 1.808 1.882 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 1.882 clk_ibuf/ntD + IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.758 2.688 _N69 + PLL_158_55/CLK_OUT0 td 0.100 2.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 1.059 3.847 rd3_clk + USCM_84_154/CLK_USCM td 0.000 3.847 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.786 5.633 ntR3950 + PLL_158_303/CLK_OUT0 td 0.100 5.733 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 1.571 7.304 zoom_clk + USCM_84_118/CLK_USCM td 0.000 7.304 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 1.531 8.835 ntclkbufg_3 + CLMA_210_153/CLK r u_zoom_image/image_valid[2][1]/opit_0/CLK + + CLMA_210_153/Q3 tco 0.221 9.056 f u_zoom_image/image_valid[2][1]/opit_0/Q + net (fanout=1) 0.084 9.140 u_zoom_image/image_valid[2] [1] + CLMA_210_153/AD f u_zoom_image/image_valid[3][1]/opit_0/D + + Data arrival time 9.140 Logic Levels: 0 + Logic: 0.221ns(72.459%), Route: 0.084ns(27.541%) +---------------------------------------------------------------------------------------------------- + + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r + P20 0.000 0.000 r clk (port) + net (fanout=1) 0.074 0.074 clk + IOBS_LR_328_209/DIN td 2.166 2.240 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 2.240 clk_ibuf/ntD + IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.787 3.103 _N69 + PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 1.078 4.288 rd3_clk + USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.861 6.149 ntR3950 + PLL_158_303/CLK_OUT0 td 0.107 6.256 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 1.599 7.855 zoom_clk + USCM_84_118/CLK_USCM td 0.000 7.855 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 1.585 9.440 ntclkbufg_3 + CLMA_210_153/CLK r u_zoom_image/image_valid[3][1]/opit_0/CLK + clock pessimism -0.605 8.835 + clock uncertainty 0.000 8.835 + + Hold time 0.053 8.888 + + Data required time 8.888 +---------------------------------------------------------------------------------------------------- + Data required time 8.888 + Data arrival time 9.140 +---------------------------------------------------------------------------------------------------- + Slack (MET) 0.252 +==================================================================================================== + +==================================================================================================== + +Startpoint : udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/rd_cnt[5]/opit_0_A2Q21/CLK +Endpoint : udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0_A2Q1/Cin Path Group : clk_720p60Hz Path Type : max (slow corner) Path Class : sequential timing path Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 8.831 - Launch Clock Delay : 9.434 - Clock Pessimism Removal : 0.567 + Capture Clock Delay : 8.952 + Launch Clock Delay : 9.557 + Clock Pessimism Removal : 0.569 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -3423,37 +3765,35 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 1.078 4.288 rd3_clk USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.861 6.149 ntR3907 + net (fanout=1) 1.861 6.149 ntR3950 PLL_158_303/CLK_OUT1 td 0.101 6.250 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 net (fanout=2) 1.599 7.849 nt_pix_clk USCM_84_117/CLK_USCM td 0.000 7.849 r clkbufg_2/gopclkbufg/CLKOUT - net (fanout=1635) 1.585 9.434 ntclkbufg_2 - CLMS_186_117/CLK r u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK - - CLMS_186_117/Q2 tco 0.290 9.724 r u_sync_vg/pos_y[8]/opit_0_A2Q21/Q0 - net (fanout=1) 0.857 10.581 pos_y[7] - CLMA_186_116/COUT td 0.515 11.096 r udp_osd_inst/N29.eq_2/gateop_A2/Cout - net (fanout=1) 0.000 11.096 udp_osd_inst/N29.co [6] - CLMA_186_120/Y1 td 0.498 11.594 r udp_osd_inst/N29.eq_4/gateop_A2/Y1 - net (fanout=5) 0.410 12.004 udp_osd_inst/N29 - CLMA_190_120/Y3 td 0.287 12.291 r udp_osd_inst/N69_5/gateop_perm/Z - net (fanout=2) 0.551 12.842 udp_osd_inst/char_osd_inst/pixels_shifter_inst/N64 - CLMA_186_112/Y1 td 0.212 13.054 r udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/gateop_perm/Z - net (fanout=2) 0.401 13.455 udp_osd_inst/char_osd_inst/row_pixels_ready - CLMA_186_108/Y2 td 0.210 13.665 r udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/gateop_perm/Z - net (fanout=6) 0.587 14.252 udp_osd_inst/char_osd_inst/char_next - CLMA_182_88/Y3 td 0.210 14.462 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N79/gateop_perm/Z - net (fanout=1) 0.253 14.715 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N79 - CLMA_182_88/Y2 td 0.210 14.925 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N358_5/gateop_perm/Z - net (fanout=3) 0.548 15.473 udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N96518 - CLMA_186_80/Y0 td 0.341 15.814 f udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786/gateop_perm/Z - net (fanout=1) 0.540 16.354 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786 - CLMA_182_73/CECO td 0.170 16.524 f udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[4]/opit_0_A2Q21/CEOUT - net (fanout=4) 0.000 16.524 ntR2038 - CLMA_182_77/CECI f udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[1]/opit_0_L5Q_perm/CE - - Data arrival time 16.524 Logic Levels: 9 - Logic: 2.943ns(41.509%), Route: 4.147ns(58.491%) + net (fanout=1635) 1.708 9.557 ntclkbufg_2 + CLMA_214_292/CLK r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/rd_cnt[5]/opit_0_A2Q21/CLK + + CLMA_214_292/Q1 tco 0.291 9.848 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/rd_cnt[5]/opit_0_A2Q21/Q1 + net (fanout=3) 0.549 10.397 udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/rd_cnt [5] + CLMA_218_284/Y1 td 0.304 10.701 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N140_20/gateop_perm/Z + net (fanout=1) 0.736 11.437 udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N107752 + CLMA_214_280/Y1 td 0.468 11.905 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N140_29/gateop_perm/Z + net (fanout=3) 0.268 12.173 udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N98274 + CLMA_214_284/Y1 td 0.212 12.385 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N135_7/gateop_perm/Z + net (fanout=15) 0.990 13.375 udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/fifo_rd_data_en + td 0.474 13.849 f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/opit_0_inv_A2Q1/Cout + net (fanout=1) 0.000 13.849 udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N13665 + CLMS_186_277/COUT td 0.058 13.907 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/opit_0_inv_A2Q21/Cout + net (fanout=1) 0.000 13.907 udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N13667 + CLMS_186_281/Y1 td 0.498 14.405 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/opit_0_inv_A2Q21/Y1 + net (fanout=3) 0.461 14.866 udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N84 [5] + CLMA_186_292/Y2 td 0.478 15.344 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[5]/gateop_perm/Z + net (fanout=1) 0.644 15.988 udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rrptr [5] + CLMS_190_285/COUT td 0.511 16.499 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N170.eq_2/gateop_A2/Cout + net (fanout=1) 0.000 16.499 udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N170.co [6] + CLMS_190_289/CIN r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0_A2Q1/Cin + + Data arrival time 16.499 Logic Levels: 7 + Logic: 3.294ns(47.450%), Route: 3.648ns(52.550%) ---------------------------------------------------------------------------------------------------- Clock clk_720p60Hz (rising edge) 13.473 13.473 r @@ -3466,36 +3806,36 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi PLL_158_55/CLK_OUT0 td 0.100 16.261 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 1.059 17.320 rd3_clk USCM_84_154/CLK_USCM td 0.000 17.320 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.786 19.106 ntR3907 + net (fanout=1) 1.786 19.106 ntR3950 PLL_158_303/CLK_OUT1 td 0.096 19.202 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 net (fanout=2) 1.571 20.773 nt_pix_clk USCM_84_117/CLK_USCM td 0.000 20.773 r clkbufg_2/gopclkbufg/CLKOUT - net (fanout=1635) 1.531 22.304 ntclkbufg_2 - CLMA_182_77/CLK r udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[1]/opit_0_L5Q_perm/CLK - clock pessimism 0.567 22.871 - clock uncertainty -0.150 22.721 + net (fanout=1635) 1.652 22.425 ntclkbufg_2 + CLMS_190_289/CLK r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0_A2Q1/CLK + clock pessimism 0.569 22.994 + clock uncertainty -0.150 22.844 - Setup time -0.747 21.974 + Setup time -0.357 22.487 - Data required time 21.974 + Data required time 22.487 ---------------------------------------------------------------------------------------------------- - Data required time 21.974 - Data arrival time 16.524 + Data required time 22.487 + Data arrival time 16.499 ---------------------------------------------------------------------------------------------------- - Slack (MET) 5.450 + Slack (MET) 5.988 ==================================================================================================== ==================================================================================================== -Startpoint : u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK -Endpoint : udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[2]/opit_0_L5Q_perm/CE +Startpoint : u_sync_vg/pos_x[2]/opit_0/CLK +Endpoint : udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[0]/opit_0_L5Q_perm/CE Path Group : clk_720p60Hz Path Type : max (slow corner) Path Class : sequential timing path Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 8.831 - Launch Clock Delay : 9.434 - Clock Pessimism Removal : 0.567 + Capture Clock Delay : 8.952 + Launch Clock Delay : 9.557 + Clock Pessimism Removal : 0.569 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -3510,37 +3850,128 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 1.078 4.288 rd3_clk USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.861 6.149 ntR3907 + net (fanout=1) 1.861 6.149 ntR3950 PLL_158_303/CLK_OUT1 td 0.101 6.250 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 net (fanout=2) 1.599 7.849 nt_pix_clk USCM_84_117/CLK_USCM td 0.000 7.849 r clkbufg_2/gopclkbufg/CLKOUT - net (fanout=1635) 1.585 9.434 ntclkbufg_2 - CLMS_186_117/CLK r u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK - - CLMS_186_117/Q2 tco 0.290 9.724 r u_sync_vg/pos_y[8]/opit_0_A2Q21/Q0 - net (fanout=1) 0.857 10.581 pos_y[7] - CLMA_186_116/COUT td 0.515 11.096 r udp_osd_inst/N29.eq_2/gateop_A2/Cout - net (fanout=1) 0.000 11.096 udp_osd_inst/N29.co [6] - CLMA_186_120/Y1 td 0.498 11.594 r udp_osd_inst/N29.eq_4/gateop_A2/Y1 - net (fanout=5) 0.410 12.004 udp_osd_inst/N29 - CLMA_190_120/Y3 td 0.287 12.291 r udp_osd_inst/N69_5/gateop_perm/Z - net (fanout=2) 0.551 12.842 udp_osd_inst/char_osd_inst/pixels_shifter_inst/N64 - CLMA_186_112/Y1 td 0.212 13.054 r udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/gateop_perm/Z - net (fanout=2) 0.401 13.455 udp_osd_inst/char_osd_inst/row_pixels_ready - CLMA_186_108/Y2 td 0.210 13.665 r udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/gateop_perm/Z - net (fanout=6) 0.587 14.252 udp_osd_inst/char_osd_inst/char_next - CLMA_182_88/Y3 td 0.210 14.462 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N79/gateop_perm/Z - net (fanout=1) 0.253 14.715 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N79 - CLMA_182_88/Y2 td 0.210 14.925 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N358_5/gateop_perm/Z - net (fanout=3) 0.548 15.473 udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N96518 - CLMA_186_80/Y0 td 0.341 15.814 f udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786/gateop_perm/Z - net (fanout=1) 0.540 16.354 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786 - CLMA_182_73/CECO td 0.170 16.524 f udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[4]/opit_0_A2Q21/CEOUT - net (fanout=4) 0.000 16.524 ntR2038 - CLMA_182_77/CECI f udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[2]/opit_0_L5Q_perm/CE - - Data arrival time 16.524 Logic Levels: 9 - Logic: 2.943ns(41.509%), Route: 4.147ns(58.491%) + net (fanout=1635) 1.708 9.557 ntclkbufg_2 + CLMA_242_252/CLK r u_sync_vg/pos_x[2]/opit_0/CLK + + CLMA_242_252/Q0 tco 0.289 9.846 r u_sync_vg/pos_x[2]/opit_0/Q + net (fanout=2) 0.770 10.616 pos_x[2] + td 0.326 10.942 f udp_osd_inst/N26.lt_0/gateop_A2/Cout + net (fanout=1) 0.000 10.942 udp_osd_inst/N26.co [2] + CLMA_230_244/COUT td 0.058 11.000 r udp_osd_inst/N26.lt_2/gateop_A2/Cout + net (fanout=1) 0.000 11.000 udp_osd_inst/N26.co [6] + CLMA_230_248/Y1 td 0.498 11.498 r udp_osd_inst/N26.lt_4/gateop_A2/Y1 + net (fanout=4) 0.645 12.143 udp_osd_inst/N26 + CLMA_250_257/Y2 td 0.210 12.353 r udp_osd_inst/N69_5/gateop_perm/Z + net (fanout=2) 0.257 12.610 udp_osd_inst/char_osd_inst/pixels_shifter_inst/N64 + CLMA_250_257/Y3 td 0.210 12.820 r udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/gateop_perm/Z + net (fanout=2) 0.401 13.221 udp_osd_inst/char_osd_inst/row_pixels_ready + CLMA_250_261/Y1 td 0.212 13.433 r udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/gateop_perm/Z + net (fanout=12) 0.631 14.064 udp_osd_inst/char_osd_inst/char_next + CLMA_246_284/Y2 td 0.210 14.274 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N74/gateop_perm/Z + net (fanout=1) 0.253 14.527 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N74 + CLMA_246_284/Y1 td 0.212 14.739 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_fsm[3:0]_62/gateop_perm/Z + net (fanout=3) 0.403 15.142 udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N97126 + CLMA_250_284/Y0 td 0.210 15.352 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786/gateop_perm/Z + net (fanout=1) 0.395 15.747 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786 + CLMA_254_288/CECO td 0.184 15.931 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[4]/opit_0_A2Q21/CEOUT + net (fanout=4) 0.000 15.931 ntR2066 + CLMA_254_292/CECI r udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[0]/opit_0_L5Q_perm/CE + + Data arrival time 15.931 Logic Levels: 9 + Logic: 2.619ns(41.089%), Route: 3.755ns(58.911%) +---------------------------------------------------------------------------------------------------- + + Clock clk_720p60Hz (rising edge) 13.473 13.473 r + P20 0.000 13.473 r clk (port) + net (fanout=1) 0.074 13.547 clk + IOBS_LR_328_209/DIN td 1.808 15.355 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 15.355 clk_ibuf/ntD + IOL_327_210/INCK td 0.048 15.403 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.758 16.161 _N69 + PLL_158_55/CLK_OUT0 td 0.100 16.261 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 1.059 17.320 rd3_clk + USCM_84_154/CLK_USCM td 0.000 17.320 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.786 19.106 ntR3950 + PLL_158_303/CLK_OUT1 td 0.096 19.202 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + net (fanout=2) 1.571 20.773 nt_pix_clk + USCM_84_117/CLK_USCM td 0.000 20.773 r clkbufg_2/gopclkbufg/CLKOUT + net (fanout=1635) 1.652 22.425 ntclkbufg_2 + CLMA_254_292/CLK r udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[0]/opit_0_L5Q_perm/CLK + clock pessimism 0.569 22.994 + clock uncertainty -0.150 22.844 + + Setup time -0.729 22.115 + + Data required time 22.115 +---------------------------------------------------------------------------------------------------- + Data required time 22.115 + Data arrival time 15.931 +---------------------------------------------------------------------------------------------------- + Slack (MET) 6.184 +==================================================================================================== + +==================================================================================================== + +Startpoint : u_sync_vg/pos_x[2]/opit_0/CLK +Endpoint : udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[1]/opit_0_L5Q_perm/CE +Path Group : clk_720p60Hz +Path Type : max (slow corner) +Path Class : sequential timing path +Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 8.952 + Launch Clock Delay : 9.557 + Clock Pessimism Removal : 0.569 + + Location Delay Type Incr Path Logical Resource +---------------------------------------------------------------------------------------------------- + + Clock clk_720p60Hz (rising edge) 0.000 0.000 r + P20 0.000 0.000 r clk (port) + net (fanout=1) 0.074 0.074 clk + IOBS_LR_328_209/DIN td 2.166 2.240 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 2.240 clk_ibuf/ntD + IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.787 3.103 _N69 + PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 1.078 4.288 rd3_clk + USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.861 6.149 ntR3950 + PLL_158_303/CLK_OUT1 td 0.101 6.250 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + net (fanout=2) 1.599 7.849 nt_pix_clk + USCM_84_117/CLK_USCM td 0.000 7.849 r clkbufg_2/gopclkbufg/CLKOUT + net (fanout=1635) 1.708 9.557 ntclkbufg_2 + CLMA_242_252/CLK r u_sync_vg/pos_x[2]/opit_0/CLK + + CLMA_242_252/Q0 tco 0.289 9.846 r u_sync_vg/pos_x[2]/opit_0/Q + net (fanout=2) 0.770 10.616 pos_x[2] + td 0.326 10.942 f udp_osd_inst/N26.lt_0/gateop_A2/Cout + net (fanout=1) 0.000 10.942 udp_osd_inst/N26.co [2] + CLMA_230_244/COUT td 0.058 11.000 r udp_osd_inst/N26.lt_2/gateop_A2/Cout + net (fanout=1) 0.000 11.000 udp_osd_inst/N26.co [6] + CLMA_230_248/Y1 td 0.498 11.498 r udp_osd_inst/N26.lt_4/gateop_A2/Y1 + net (fanout=4) 0.645 12.143 udp_osd_inst/N26 + CLMA_250_257/Y2 td 0.210 12.353 r udp_osd_inst/N69_5/gateop_perm/Z + net (fanout=2) 0.257 12.610 udp_osd_inst/char_osd_inst/pixels_shifter_inst/N64 + CLMA_250_257/Y3 td 0.210 12.820 r udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/gateop_perm/Z + net (fanout=2) 0.401 13.221 udp_osd_inst/char_osd_inst/row_pixels_ready + CLMA_250_261/Y1 td 0.212 13.433 r udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/gateop_perm/Z + net (fanout=12) 0.631 14.064 udp_osd_inst/char_osd_inst/char_next + CLMA_246_284/Y2 td 0.210 14.274 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N74/gateop_perm/Z + net (fanout=1) 0.253 14.527 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N74 + CLMA_246_284/Y1 td 0.212 14.739 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_fsm[3:0]_62/gateop_perm/Z + net (fanout=3) 0.403 15.142 udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N97126 + CLMA_250_284/Y0 td 0.210 15.352 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786/gateop_perm/Z + net (fanout=1) 0.395 15.747 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786 + CLMA_254_288/CECO td 0.184 15.931 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[4]/opit_0_A2Q21/CEOUT + net (fanout=4) 0.000 15.931 ntR2066 + CLMA_254_292/CECI r udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[1]/opit_0_L5Q_perm/CE + + Data arrival time 15.931 Logic Levels: 9 + Logic: 2.619ns(41.089%), Route: 3.755ns(58.911%) ---------------------------------------------------------------------------------------------------- Clock clk_720p60Hz (rising edge) 13.473 13.473 r @@ -3553,29 +3984,29 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi PLL_158_55/CLK_OUT0 td 0.100 16.261 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 1.059 17.320 rd3_clk USCM_84_154/CLK_USCM td 0.000 17.320 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.786 19.106 ntR3907 + net (fanout=1) 1.786 19.106 ntR3950 PLL_158_303/CLK_OUT1 td 0.096 19.202 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 net (fanout=2) 1.571 20.773 nt_pix_clk USCM_84_117/CLK_USCM td 0.000 20.773 r clkbufg_2/gopclkbufg/CLKOUT - net (fanout=1635) 1.531 22.304 ntclkbufg_2 - CLMA_182_77/CLK r udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[2]/opit_0_L5Q_perm/CLK - clock pessimism 0.567 22.871 - clock uncertainty -0.150 22.721 + net (fanout=1635) 1.652 22.425 ntclkbufg_2 + CLMA_254_292/CLK r udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[1]/opit_0_L5Q_perm/CLK + clock pessimism 0.569 22.994 + clock uncertainty -0.150 22.844 - Setup time -0.747 21.974 + Setup time -0.729 22.115 - Data required time 21.974 + Data required time 22.115 ---------------------------------------------------------------------------------------------------- - Data required time 21.974 - Data arrival time 16.524 + Data required time 22.115 + Data arrival time 15.931 ---------------------------------------------------------------------------------------------------- - Slack (MET) 5.450 + Slack (MET) 6.184 ==================================================================================================== ==================================================================================================== -Startpoint : adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/quotient[1]/opit_0_L5Q_perm/CLK -Endpoint : adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/quotient[2]/opit_0_L5Q_perm/L4 +Startpoint : adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm/CLK +Endpoint : adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm/L4 Path Group : clk_720p60Hz Path Type : min (slow corner) Path Class : sequential timing path @@ -3597,16 +4028,16 @@ Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessim PLL_158_55/CLK_OUT0 td 0.100 2.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 1.059 3.847 rd3_clk USCM_84_154/CLK_USCM td 0.000 3.847 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.786 5.633 ntR3907 + net (fanout=1) 1.786 5.633 ntR3950 PLL_158_303/CLK_OUT1 td 0.096 5.729 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 net (fanout=2) 1.571 7.300 nt_pix_clk USCM_84_117/CLK_USCM td 0.000 7.300 r clkbufg_2/gopclkbufg/CLKOUT net (fanout=1635) 1.531 8.831 ntclkbufg_2 - CLMA_266_132/CLK r adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/quotient[1]/opit_0_L5Q_perm/CLK + CLMA_250_177/CLK r adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm/CLK - CLMA_266_132/Q1 tco 0.224 9.055 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/quotient[1]/opit_0_L5Q_perm/Q - net (fanout=1) 0.084 9.139 adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/quotient_t[4] [1] - CLMS_266_133/C4 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/quotient[2]/opit_0_L5Q_perm/L4 + CLMA_250_177/Q2 tco 0.224 9.055 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm/Q + net (fanout=1) 0.084 9.139 adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/dividend_t[13] [9] + CLMA_250_176/A4 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm/L4 Data arrival time 9.139 Logic Levels: 0 Logic: 0.224ns(72.727%), Route: 0.084ns(27.273%) @@ -3622,36 +4053,36 @@ Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessim PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 1.078 4.288 rd3_clk USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.861 6.149 ntR3907 + net (fanout=1) 1.861 6.149 ntR3950 PLL_158_303/CLK_OUT1 td 0.101 6.250 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 net (fanout=2) 1.599 7.849 nt_pix_clk USCM_84_117/CLK_USCM td 0.000 7.849 r clkbufg_2/gopclkbufg/CLKOUT net (fanout=1635) 1.585 9.434 ntclkbufg_2 - CLMS_266_133/CLK r adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/quotient[2]/opit_0_L5Q_perm/CLK + CLMA_250_176/CLK r adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm/CLK clock pessimism -0.574 8.860 clock uncertainty 0.000 8.860 - Hold time -0.034 8.826 + Hold time -0.035 8.825 - Data required time 8.826 + Data required time 8.825 ---------------------------------------------------------------------------------------------------- - Data required time 8.826 + Data required time 8.825 Data arrival time 9.139 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.313 + Slack (MET) 0.314 ==================================================================================================== ==================================================================================================== -Startpoint : adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[3]/opit_0_L5Q_perm/CLK -Endpoint : adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[4]/opit_0_L5Q_perm/L4 +Startpoint : udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[3]/opit_0_A2Q21/CLK +Endpoint : udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr[4]/opit_0_A2Q21/I04 Path Group : clk_720p60Hz Path Type : min (slow corner) Path Class : sequential timing path Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 9.434 - Launch Clock Delay : 8.831 - Clock Pessimism Removal : -0.574 + Capture Clock Delay : 9.557 + Launch Clock Delay : 8.952 + Clock Pessimism Removal : -0.576 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -3666,19 +4097,19 @@ Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessim PLL_158_55/CLK_OUT0 td 0.100 2.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 1.059 3.847 rd3_clk USCM_84_154/CLK_USCM td 0.000 3.847 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.786 5.633 ntR3907 + net (fanout=1) 1.786 5.633 ntR3950 PLL_158_303/CLK_OUT1 td 0.096 5.729 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 net (fanout=2) 1.571 7.300 nt_pix_clk USCM_84_117/CLK_USCM td 0.000 7.300 r clkbufg_2/gopclkbufg/CLKOUT - net (fanout=1635) 1.531 8.831 ntclkbufg_2 - CLMA_262_132/CLK r adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[3]/opit_0_L5Q_perm/CLK + net (fanout=1635) 1.652 8.952 ntclkbufg_2 + CLMA_230_280/CLK r udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[3]/opit_0_A2Q21/CLK - CLMA_262_132/Q2 tco 0.224 9.055 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[3]/opit_0_L5Q_perm/Q - net (fanout=1) 0.084 9.139 adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/quotient_t[1] [3] - CLMS_262_133/A4 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[4]/opit_0_L5Q_perm/L4 + CLMA_230_280/Q1 tco 0.224 9.176 f udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[3]/opit_0_A2Q21/Q1 + net (fanout=2) 0.085 9.261 udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d [3] + CLMA_230_281/C4 f udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr[4]/opit_0_A2Q21/I04 - Data arrival time 9.139 Logic Levels: 0 - Logic: 0.224ns(72.727%), Route: 0.084ns(27.273%) + Data arrival time 9.261 Logic Levels: 0 + Logic: 0.224ns(72.492%), Route: 0.085ns(27.508%) ---------------------------------------------------------------------------------------------------- Clock clk_720p60Hz (rising edge) 0.000 0.000 r @@ -3691,36 +4122,36 @@ Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessim PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 1.078 4.288 rd3_clk USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.861 6.149 ntR3907 + net (fanout=1) 1.861 6.149 ntR3950 PLL_158_303/CLK_OUT1 td 0.101 6.250 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 net (fanout=2) 1.599 7.849 nt_pix_clk USCM_84_117/CLK_USCM td 0.000 7.849 r clkbufg_2/gopclkbufg/CLKOUT - net (fanout=1635) 1.585 9.434 ntclkbufg_2 - CLMS_262_133/CLK r adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[4]/opit_0_L5Q_perm/CLK - clock pessimism -0.574 8.860 - clock uncertainty 0.000 8.860 + net (fanout=1635) 1.708 9.557 ntclkbufg_2 + CLMA_230_281/CLK r udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr[4]/opit_0_A2Q21/CLK + clock pessimism -0.576 8.981 + clock uncertainty 0.000 8.981 - Hold time -0.035 8.825 + Hold time -0.034 8.947 - Data required time 8.825 + Data required time 8.947 ---------------------------------------------------------------------------------------------------- - Data required time 8.825 - Data arrival time 9.139 + Data required time 8.947 + Data arrival time 9.261 ---------------------------------------------------------------------------------------------------- Slack (MET) 0.314 ==================================================================================================== ==================================================================================================== -Startpoint : udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[3]/opit_0_A2Q21/CLK -Endpoint : udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr[4]/opit_0_A2Q21/I04 +Startpoint : u_sync_vg/v_count[3]/opit_0_L5Q_perm/CLK +Endpoint : u_sync_vg/pos_y[4]/opit_0_A2Q21/I04 Path Group : clk_720p60Hz Path Type : min (slow corner) Path Class : sequential timing path Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 9.434 - Launch Clock Delay : 8.831 - Clock Pessimism Removal : -0.574 + Capture Clock Delay : 9.557 + Launch Clock Delay : 8.952 + Clock Pessimism Removal : -0.576 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -3735,19 +4166,19 @@ Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessim PLL_158_55/CLK_OUT0 td 0.100 2.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 1.059 3.847 rd3_clk USCM_84_154/CLK_USCM td 0.000 3.847 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.786 5.633 ntR3907 + net (fanout=1) 1.786 5.633 ntR3950 PLL_158_303/CLK_OUT1 td 0.096 5.729 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 net (fanout=2) 1.571 7.300 nt_pix_clk USCM_84_117/CLK_USCM td 0.000 7.300 r clkbufg_2/gopclkbufg/CLKOUT - net (fanout=1635) 1.531 8.831 ntclkbufg_2 - CLMA_174_52/CLK r udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[3]/opit_0_A2Q21/CLK + net (fanout=1635) 1.652 8.952 ntclkbufg_2 + CLMS_246_253/CLK r u_sync_vg/v_count[3]/opit_0_L5Q_perm/CLK - CLMA_174_52/Q1 tco 0.224 9.055 f udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[3]/opit_0_A2Q21/Q1 - net (fanout=2) 0.085 9.140 udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d [3] - CLMS_174_53/C4 f udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr[4]/opit_0_A2Q21/I04 + CLMS_246_253/Q1 tco 0.224 9.176 f u_sync_vg/v_count[3]/opit_0_L5Q_perm/Q + net (fanout=7) 0.089 9.265 u_sync_vg/v_count [3] + CLMA_246_252/C4 f u_sync_vg/pos_y[4]/opit_0_A2Q21/I04 - Data arrival time 9.140 Logic Levels: 0 - Logic: 0.224ns(72.492%), Route: 0.085ns(27.508%) + Data arrival time 9.265 Logic Levels: 0 + Logic: 0.224ns(71.565%), Route: 0.089ns(28.435%) ---------------------------------------------------------------------------------------------------- Clock clk_720p60Hz (rising edge) 0.000 0.000 r @@ -3760,36 +4191,36 @@ Clock Skew : 0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessim PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 1.078 4.288 rd3_clk USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.861 6.149 ntR3907 + net (fanout=1) 1.861 6.149 ntR3950 PLL_158_303/CLK_OUT1 td 0.101 6.250 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 net (fanout=2) 1.599 7.849 nt_pix_clk USCM_84_117/CLK_USCM td 0.000 7.849 r clkbufg_2/gopclkbufg/CLKOUT - net (fanout=1635) 1.585 9.434 ntclkbufg_2 - CLMS_174_53/CLK r udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr[4]/opit_0_A2Q21/CLK - clock pessimism -0.574 8.860 - clock uncertainty 0.000 8.860 + net (fanout=1635) 1.708 9.557 ntclkbufg_2 + CLMA_246_252/CLK r u_sync_vg/pos_y[4]/opit_0_A2Q21/CLK + clock pessimism -0.576 8.981 + clock uncertainty 0.000 8.981 - Hold time -0.034 8.826 + Hold time -0.034 8.947 - Data required time 8.826 + Data required time 8.947 ---------------------------------------------------------------------------------------------------- - Data required time 8.826 - Data arrival time 9.140 + Data required time 8.947 + Data arrival time 9.265 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.314 + Slack (MET) 0.318 ==================================================================================================== ==================================================================================================== -Startpoint : u_ov5640/coms2_reg_config/reg_data/iGopDrm/CLKB[0] -Endpoint : u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I0 +Startpoint : u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0] +Endpoint : u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I0 Path Group : clk_20k Path Type : max (slow corner) Path Class : sequential timing path Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 9.014 - Launch Clock Delay : 9.812 - Clock Pessimism Removal : 0.762 + Capture Clock Delay : 9.367 + Launch Clock Delay : 10.251 + Clock Pessimism Removal : 0.848 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -3803,26 +4234,26 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT3 td 0.111 3.214 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 net (fanout=1) 1.078 4.292 clk_25m - USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 1.585 5.877 ntclkbufg_7 - CLMA_182_25/Q1 tco 0.291 6.168 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q - net (fanout=3) 2.059 8.227 u_ov5640/coms2_reg_config/clk_20k_regdiv - USCM_84_120/CLK_USCM td 0.000 8.227 r u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - net (fanout=19) 1.585 9.812 u_ov5640/coms2_reg_config/clock_20k - DRM_178_24/CLKB[0] r u_ov5640/coms2_reg_config/reg_data/iGopDrm/CLKB[0] - - DRM_178_24/QB0[5] tco 2.286 12.098 r u_ov5640/coms2_reg_config/reg_data/iGopDrm/QB0[5] - net (fanout=1) 0.543 12.641 u_ov5640/coms2_reg_config/i2c_data [21] - CLMA_174_32/Y3 td 0.459 13.100 r u_ov5640/coms2_reg_config/u1/N267_29/gateop/F - net (fanout=1) 0.407 13.507 u_ov5640/coms2_reg_config/u1/_N25904 - CLMS_174_29/Y2 td 0.210 13.717 r u_ov5640/coms2_reg_config/u1/N267_35/gateop_perm/Z - net (fanout=1) 0.259 13.976 u_ov5640/coms2_reg_config/u1/_N25910 - CLMS_174_29/Y1 td 0.274 14.250 r u_ov5640/coms2_reg_config/u1/N267_36/gateop/F - net (fanout=1) 0.263 14.513 u_ov5640/coms2_reg_config/u1/_N25911 - CLMS_174_25/DD r u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I0 - - Data arrival time 14.513 Logic Levels: 3 - Logic: 3.229ns(68.688%), Route: 1.472ns(31.312%) + USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 1.585 5.877 ntclkbufg_8 + CLMS_122_9/Q1 tco 0.291 6.168 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q + net (fanout=3) 2.498 8.666 u_ov5640/coms1_reg_config/clk_20k_regdiv + USCM_84_120/CLK_USCM td 0.000 8.666 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + net (fanout=19) 1.585 10.251 u_ov5640/coms1_reg_config/clock_20k + DRM_142_4/CLKB[0] r u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0] + + DRM_142_4/QB0[6] tco 2.286 12.537 r u_ov5640/coms1_reg_config/reg_data/iGopDrm/QB0[6] + net (fanout=1) 0.573 13.110 u_ov5640/coms1_reg_config/i2c_data [22] + CLMA_146_12/Y1 td 0.460 13.570 r u_ov5640/coms1_reg_config/u1/N267_29/gateop/F + net (fanout=1) 0.580 14.150 u_ov5640/coms1_reg_config/u1/_N25311 + CLMA_138_16/Y0 td 0.210 14.360 r u_ov5640/coms1_reg_config/u1/N267_35/gateop_perm/Z + net (fanout=1) 0.256 14.616 u_ov5640/coms1_reg_config/u1/_N25317 + CLMA_138_16/Y2 td 0.295 14.911 r u_ov5640/coms1_reg_config/u1/N267_36/gateop/F + net (fanout=1) 0.447 15.358 u_ov5640/coms1_reg_config/u1/_N25318 + CLMA_138_9/AD r u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I0 + + Data arrival time 15.358 Logic Levels: 3 + Logic: 3.251ns(63.658%), Route: 1.856ns(36.342%) ---------------------------------------------------------------------------------------------------- Clock clk_20k (rising edge) 50000.000 50000.000 r @@ -3834,36 +4265,36 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi net (fanout=1) 0.758 50002.688 _N69 PLL_158_55/CLK_OUT3 td 0.105 50002.793 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 net (fanout=1) 1.059 50003.852 clk_25m - USCM_84_114/CLK_USCM td 0.000 50003.852 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 1.531 50005.383 ntclkbufg_7 - CLMA_182_25/Q1 tco 0.229 50005.612 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q - net (fanout=3) 1.871 50007.483 u_ov5640/coms2_reg_config/clk_20k_regdiv - USCM_84_120/CLK_USCM td 0.000 50007.483 r u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - net (fanout=19) 1.531 50009.014 u_ov5640/coms2_reg_config/clock_20k - CLMS_174_25/CLK r u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/CLK - clock pessimism 0.762 50009.776 - clock uncertainty -0.050 50009.726 + USCM_84_114/CLK_USCM td 0.000 50003.852 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 1.531 50005.383 ntclkbufg_8 + CLMS_122_9/Q1 tco 0.229 50005.612 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q + net (fanout=3) 2.224 50007.836 u_ov5640/coms1_reg_config/clk_20k_regdiv + USCM_84_120/CLK_USCM td 0.000 50007.836 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + net (fanout=19) 1.531 50009.367 u_ov5640/coms1_reg_config/clock_20k + CLMA_138_9/CLK r u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/CLK + clock pessimism 0.848 50010.215 + clock uncertainty -0.050 50010.165 - Setup time -0.165 50009.561 + Setup time -0.196 50009.969 - Data required time 50009.561 + Data required time 50009.969 ---------------------------------------------------------------------------------------------------- - Data required time 50009.561 - Data arrival time 14.513 + Data required time 50009.969 + Data arrival time 15.358 ---------------------------------------------------------------------------------------------------- - Slack (MET) 49995.048 + Slack (MET) 49994.611 ==================================================================================================== ==================================================================================================== -Startpoint : u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0] -Endpoint : u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I0 +Startpoint : u_ov5640/coms2_reg_config/reg_data/iGopDrm/CLKB[0] +Endpoint : u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_L5Q_perm/L4 Path Group : clk_20k Path Type : max (slow corner) Path Class : sequential timing path -Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 9.247 - Launch Clock Delay : 10.099 +Clock Skew : -0.093 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 9.258 + Launch Clock Delay : 10.167 Clock Pessimism Removal : 0.816 Location Delay Type Incr Path Logical Resource @@ -3878,26 +4309,26 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT3 td 0.111 3.214 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 net (fanout=1) 1.078 4.292 clk_25m - USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 1.585 5.877 ntclkbufg_7 - CLMA_182_12/Q1 tco 0.291 6.168 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q - net (fanout=3) 2.346 8.514 u_ov5640/coms1_reg_config/clk_20k_regdiv - USCM_84_119/CLK_USCM td 0.000 8.514 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - net (fanout=19) 1.585 10.099 u_ov5640/coms1_reg_config/clock_20k - DRM_178_4/CLKB[0] r u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0] - - DRM_178_4/QB0[6] tco 2.307 12.406 f u_ov5640/coms1_reg_config/reg_data/iGopDrm/QB0[6] - net (fanout=1) 0.619 13.025 u_ov5640/coms1_reg_config/i2c_data [22] - CLMS_174_9/Y2 td 0.478 13.503 r u_ov5640/coms1_reg_config/u1/N267_29/gateop/F - net (fanout=1) 0.119 13.622 u_ov5640/coms1_reg_config/u1/_N25461 - CLMA_174_8/Y0 td 0.210 13.832 r u_ov5640/coms1_reg_config/u1/N267_35/gateop_perm/Z - net (fanout=1) 0.120 13.952 u_ov5640/coms1_reg_config/u1/_N25467 - CLMA_174_8/Y1 td 0.274 14.226 r u_ov5640/coms1_reg_config/u1/N267_36/gateop/F - net (fanout=1) 0.444 14.670 u_ov5640/coms1_reg_config/u1/_N25468 - CLMA_174_16/DD r u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I0 - - Data arrival time 14.670 Logic Levels: 3 - Logic: 3.269ns(71.516%), Route: 1.302ns(28.484%) + USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 1.585 5.877 ntclkbufg_8 + CLMA_122_12/Q1 tco 0.291 6.168 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q + net (fanout=3) 2.357 8.525 u_ov5640/coms2_reg_config/clk_20k_regdiv + USCM_84_121/CLK_USCM td 0.000 8.525 r u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + net (fanout=19) 1.642 10.167 u_ov5640/coms2_reg_config/clock_20k + DRM_82_4/CLKB[0] r u_ov5640/coms2_reg_config/reg_data/iGopDrm/CLKB[0] + + DRM_82_4/QB0[5] tco 2.286 12.453 r u_ov5640/coms2_reg_config/reg_data/iGopDrm/QB0[5] + net (fanout=1) 0.501 12.954 u_ov5640/coms2_reg_config/i2c_data [21] + CLMS_78_9/Y1 td 0.460 13.414 r u_ov5640/coms2_reg_config/u1/N267_29/gateop/F + net (fanout=1) 0.612 14.026 u_ov5640/coms2_reg_config/u1/_N25853 + CLMA_90_12/Y2 td 0.210 14.236 r u_ov5640/coms2_reg_config/u1/N267_35/gateop_perm/Z + net (fanout=1) 0.257 14.493 u_ov5640/coms2_reg_config/u1/_N25859 + CLMA_90_12/Y6AB td 0.259 14.752 r u_ov5640/coms2_reg_config/u1/N267_37_muxf6/F + net (fanout=1) 0.258 15.010 u_ov5640/coms2_reg_config/u1/N267 + CLMA_90_13/A4 r u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_L5Q_perm/L4 + + Data arrival time 15.010 Logic Levels: 3 + Logic: 3.215ns(66.384%), Route: 1.628ns(33.616%) ---------------------------------------------------------------------------------------------------- Clock clk_20k (rising edge) 50000.000 50000.000 r @@ -3909,37 +4340,37 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi net (fanout=1) 0.758 50002.688 _N69 PLL_158_55/CLK_OUT3 td 0.105 50002.793 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 net (fanout=1) 1.059 50003.852 clk_25m - USCM_84_114/CLK_USCM td 0.000 50003.852 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 1.531 50005.383 ntclkbufg_7 - CLMA_182_12/Q1 tco 0.229 50005.612 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q - net (fanout=3) 2.104 50007.716 u_ov5640/coms1_reg_config/clk_20k_regdiv - USCM_84_119/CLK_USCM td 0.000 50007.716 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - net (fanout=19) 1.531 50009.247 u_ov5640/coms1_reg_config/clock_20k - CLMA_174_16/CLK r u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/CLK - clock pessimism 0.816 50010.063 - clock uncertainty -0.050 50010.013 + USCM_84_114/CLK_USCM td 0.000 50003.852 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 1.531 50005.383 ntclkbufg_8 + CLMA_122_12/Q1 tco 0.229 50005.612 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q + net (fanout=3) 2.115 50007.727 u_ov5640/coms2_reg_config/clk_20k_regdiv + USCM_84_121/CLK_USCM td 0.000 50007.727 r u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + net (fanout=19) 1.531 50009.258 u_ov5640/coms2_reg_config/clock_20k + CLMA_90_13/CLK r u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_L5Q_perm/CLK + clock pessimism 0.816 50010.074 + clock uncertainty -0.050 50010.024 - Setup time -0.165 50009.848 + Setup time -0.121 50009.903 - Data required time 50009.848 + Data required time 50009.903 ---------------------------------------------------------------------------------------------------- - Data required time 50009.848 - Data arrival time 14.670 + Data required time 50009.903 + Data arrival time 15.010 ---------------------------------------------------------------------------------------------------- - Slack (MET) 49995.178 + Slack (MET) 49994.893 ==================================================================================================== ==================================================================================================== -Startpoint : u_ov5640/coms1_reg_config/reg_index[2]/opit_0_inv_A2Q21/CLK -Endpoint : u_ov5640/coms1_reg_config/reg_index[6]/opit_0_inv_A2Q21/CE +Startpoint : u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0] +Endpoint : u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I3 Path Group : clk_20k Path Type : max (slow corner) Path Class : sequential timing path -Clock Skew : -0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 9.247 - Launch Clock Delay : 10.099 - Clock Pessimism Removal : 0.823 +Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 9.367 + Launch Clock Delay : 10.251 + Clock Pessimism Removal : 0.848 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -3953,30 +4384,22 @@ Clock Skew : -0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessi net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT3 td 0.111 3.214 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 net (fanout=1) 1.078 4.292 clk_25m - USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 1.585 5.877 ntclkbufg_7 - CLMA_182_12/Q1 tco 0.291 6.168 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q - net (fanout=3) 2.346 8.514 u_ov5640/coms1_reg_config/clk_20k_regdiv - USCM_84_119/CLK_USCM td 0.000 8.514 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - net (fanout=19) 1.585 10.099 u_ov5640/coms1_reg_config/clock_20k - CLMS_174_13/CLK r u_ov5640/coms1_reg_config/reg_index[2]/opit_0_inv_A2Q21/CLK - - CLMS_174_13/Q0 tco 0.289 10.388 r u_ov5640/coms1_reg_config/reg_index[2]/opit_0_inv_A2Q21/Q0 - net (fanout=5) 0.475 10.863 u_ov5640/coms1_reg_config/reg_index [1] - CLMA_182_13/Y1 td 0.304 11.167 r u_ov5640/coms1_reg_config/N26_mux2/gateop_perm/Z - net (fanout=1) 0.730 11.897 u_ov5640/coms1_reg_config/_N9682 - CLMS_174_9/Y3 td 0.210 12.107 r u_ov5640/coms1_reg_config/N26_mux6_3/gateop_perm/Z - net (fanout=2) 0.557 12.664 u_ov5640/coms1_reg_config/_N9690 - CLMS_174_21/Y2 td 0.210 12.874 r u_ov5640/coms1_reg_config/N1134_1/gateop_perm/Z - net (fanout=4) 0.123 12.997 u_ov5640/coms1_reg_config/_N96528 - CLMS_174_21/Y0 td 0.487 13.484 r u_ov5640/coms1_reg_config/N1169/gateop_perm/Z - net (fanout=3) 0.413 13.897 u_ov5640/coms1_reg_config/N1169 - CLMS_174_13/CECO td 0.184 14.081 r u_ov5640/coms1_reg_config/reg_index[4]/opit_0_inv_A2Q21/CEOUT - net (fanout=2) 0.000 14.081 ntR1983 - CLMS_174_17/CECI r u_ov5640/coms1_reg_config/reg_index[6]/opit_0_inv_A2Q21/CE - - Data arrival time 14.081 Logic Levels: 5 - Logic: 1.684ns(42.290%), Route: 2.298ns(57.710%) + USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 1.585 5.877 ntclkbufg_8 + CLMS_122_9/Q1 tco 0.291 6.168 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q + net (fanout=3) 2.498 8.666 u_ov5640/coms1_reg_config/clk_20k_regdiv + USCM_84_120/CLK_USCM td 0.000 8.666 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + net (fanout=19) 1.585 10.251 u_ov5640/coms1_reg_config/clock_20k + DRM_142_4/CLKB[0] r u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0] + + DRM_142_4/QA0[9] tco 2.331 12.582 r u_ov5640/coms1_reg_config/reg_data/iGopDrm/QA0[9] + net (fanout=1) 0.664 13.246 u_ov5640/coms1_reg_config/i2c_data [8] + CLMA_146_8/Y1 td 0.603 13.849 r u_ov5640/coms1_reg_config/u1/N267_18_muxf7/F + net (fanout=1) 0.585 14.434 u_ov5640/coms1_reg_config/u1/_N25300 + CLMA_138_9/A0 r u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I3 + + Data arrival time 14.434 Logic Levels: 1 + Logic: 2.934ns(70.141%), Route: 1.249ns(29.859%) ---------------------------------------------------------------------------------------------------- Clock clk_20k (rising edge) 50000.000 50000.000 r @@ -3988,37 +4411,37 @@ Clock Skew : -0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessi net (fanout=1) 0.758 50002.688 _N69 PLL_158_55/CLK_OUT3 td 0.105 50002.793 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 net (fanout=1) 1.059 50003.852 clk_25m - USCM_84_114/CLK_USCM td 0.000 50003.852 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 1.531 50005.383 ntclkbufg_7 - CLMA_182_12/Q1 tco 0.229 50005.612 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q - net (fanout=3) 2.104 50007.716 u_ov5640/coms1_reg_config/clk_20k_regdiv - USCM_84_119/CLK_USCM td 0.000 50007.716 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - net (fanout=19) 1.531 50009.247 u_ov5640/coms1_reg_config/clock_20k - CLMS_174_17/CLK r u_ov5640/coms1_reg_config/reg_index[6]/opit_0_inv_A2Q21/CLK - clock pessimism 0.823 50010.070 - clock uncertainty -0.050 50010.020 + USCM_84_114/CLK_USCM td 0.000 50003.852 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 1.531 50005.383 ntclkbufg_8 + CLMS_122_9/Q1 tco 0.229 50005.612 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q + net (fanout=3) 2.224 50007.836 u_ov5640/coms1_reg_config/clk_20k_regdiv + USCM_84_120/CLK_USCM td 0.000 50007.836 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + net (fanout=19) 1.531 50009.367 u_ov5640/coms1_reg_config/clock_20k + CLMA_138_9/CLK r u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/CLK + clock pessimism 0.848 50010.215 + clock uncertainty -0.050 50010.165 - Setup time -0.729 50009.291 + Setup time -0.194 50009.971 - Data required time 50009.291 + Data required time 50009.971 ---------------------------------------------------------------------------------------------------- - Data required time 50009.291 - Data arrival time 14.081 + Data required time 50009.971 + Data arrival time 14.434 ---------------------------------------------------------------------------------------------------- - Slack (MET) 49995.210 + Slack (MET) 49995.537 ==================================================================================================== ==================================================================================================== -Startpoint : u_ov5640/coms1_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK -Endpoint : u_ov5640/coms1_reg_config/reg_data/iGopDrm/ADA0[5] +Startpoint : u_ov5640/coms2_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK +Endpoint : u_ov5640/coms2_reg_config/reg_index[2]/opit_0_inv_A2Q21/I00 Path Group : clk_20k Path Type : min (slow corner) Path Class : sequential timing path -Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 10.099 - Launch Clock Delay : 9.247 - Clock Pessimism Removal : -0.816 +Clock Skew : 0.031 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 10.147 + Launch Clock Delay : 9.293 + Clock Pessimism Removal : -0.823 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -4032,20 +4455,20 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.758 2.688 _N69 PLL_158_55/CLK_OUT3 td 0.105 2.793 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 net (fanout=1) 1.059 3.852 clk_25m - USCM_84_114/CLK_USCM td 0.000 3.852 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 1.531 5.383 ntclkbufg_7 - CLMA_182_12/Q1 tco 0.229 5.612 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q - net (fanout=3) 2.104 7.716 u_ov5640/coms1_reg_config/clk_20k_regdiv - USCM_84_119/CLK_USCM td 0.000 7.716 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - net (fanout=19) 1.531 9.247 u_ov5640/coms1_reg_config/clock_20k - CLMA_182_13/CLK r u_ov5640/coms1_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK + USCM_84_114/CLK_USCM td 0.000 3.852 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 1.531 5.383 ntclkbufg_8 + CLMA_122_12/Q1 tco 0.229 5.612 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q + net (fanout=3) 2.115 7.727 u_ov5640/coms2_reg_config/clk_20k_regdiv + USCM_84_121/CLK_USCM td 0.000 7.727 r u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + net (fanout=19) 1.566 9.293 u_ov5640/coms2_reg_config/clock_20k + CLMA_78_12/CLK r u_ov5640/coms2_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK - CLMA_182_13/Q0 tco 0.222 9.469 f u_ov5640/coms1_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/Q - net (fanout=6) 0.351 9.820 u_ov5640/coms1_reg_config/reg_index [0] - DRM_178_4/ADA0[5] f u_ov5640/coms1_reg_config/reg_data/iGopDrm/ADA0[5] + CLMA_78_12/Q0 tco 0.222 9.515 f u_ov5640/coms2_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/Q + net (fanout=6) 0.087 9.602 u_ov5640/coms2_reg_config/reg_index [0] + CLMS_78_13/A0 f u_ov5640/coms2_reg_config/reg_index[2]/opit_0_inv_A2Q21/I00 - Data arrival time 9.820 Logic Levels: 0 - Logic: 0.222ns(38.743%), Route: 0.351ns(61.257%) + Data arrival time 9.602 Logic Levels: 0 + Logic: 0.222ns(71.845%), Route: 0.087ns(28.155%) ---------------------------------------------------------------------------------------------------- Clock clk_20k (rising edge) 0.000 0.000 r @@ -4057,37 +4480,37 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT3 td 0.111 3.214 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 net (fanout=1) 1.078 4.292 clk_25m - USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 1.585 5.877 ntclkbufg_7 - CLMA_182_12/Q1 tco 0.291 6.168 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q - net (fanout=3) 2.346 8.514 u_ov5640/coms1_reg_config/clk_20k_regdiv - USCM_84_119/CLK_USCM td 0.000 8.514 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - net (fanout=19) 1.585 10.099 u_ov5640/coms1_reg_config/clock_20k - DRM_178_4/CLKA[0] r u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKA[0] - clock pessimism -0.816 9.283 - clock uncertainty 0.000 9.283 + USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 1.585 5.877 ntclkbufg_8 + CLMA_122_12/Q1 tco 0.291 6.168 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q + net (fanout=3) 2.357 8.525 u_ov5640/coms2_reg_config/clk_20k_regdiv + USCM_84_121/CLK_USCM td 0.000 8.525 r u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + net (fanout=19) 1.622 10.147 u_ov5640/coms2_reg_config/clock_20k + CLMS_78_13/CLK r u_ov5640/coms2_reg_config/reg_index[2]/opit_0_inv_A2Q21/CLK + clock pessimism -0.823 9.324 + clock uncertainty 0.000 9.324 - Hold time 0.161 9.444 + Hold time -0.094 9.230 - Data required time 9.444 + Data required time 9.230 ---------------------------------------------------------------------------------------------------- - Data required time 9.444 - Data arrival time 9.820 + Data required time 9.230 + Data arrival time 9.602 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.376 + Slack (MET) 0.372 ==================================================================================================== ==================================================================================================== -Startpoint : u_ov5640/coms2_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK -Endpoint : u_ov5640/coms2_reg_config/reg_data/iGopDrm/ADA0[5] +Startpoint : u_ov5640/coms1_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK +Endpoint : u_ov5640/coms1_reg_config/reg_data/iGopDrm/ADA0[5] Path Group : clk_20k Path Type : min (slow corner) Path Class : sequential timing path Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 9.812 - Launch Clock Delay : 9.014 - Clock Pessimism Removal : -0.762 + Capture Clock Delay : 10.251 + Launch Clock Delay : 9.367 + Clock Pessimism Removal : -0.848 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -4101,20 +4524,20 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.758 2.688 _N69 PLL_158_55/CLK_OUT3 td 0.105 2.793 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 net (fanout=1) 1.059 3.852 clk_25m - USCM_84_114/CLK_USCM td 0.000 3.852 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 1.531 5.383 ntclkbufg_7 - CLMA_182_25/Q1 tco 0.229 5.612 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q - net (fanout=3) 1.871 7.483 u_ov5640/coms2_reg_config/clk_20k_regdiv - USCM_84_120/CLK_USCM td 0.000 7.483 r u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - net (fanout=19) 1.531 9.014 u_ov5640/coms2_reg_config/clock_20k - CLMA_182_32/CLK r u_ov5640/coms2_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK + USCM_84_114/CLK_USCM td 0.000 3.852 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 1.531 5.383 ntclkbufg_8 + CLMS_122_9/Q1 tco 0.229 5.612 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q + net (fanout=3) 2.224 7.836 u_ov5640/coms1_reg_config/clk_20k_regdiv + USCM_84_120/CLK_USCM td 0.000 7.836 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + net (fanout=19) 1.531 9.367 u_ov5640/coms1_reg_config/clock_20k + CLMA_146_12/CLK r u_ov5640/coms1_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK - CLMA_182_32/Q0 tco 0.222 9.236 f u_ov5640/coms2_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/Q - net (fanout=6) 0.353 9.589 u_ov5640/coms2_reg_config/reg_index [0] - DRM_178_24/ADA0[5] f u_ov5640/coms2_reg_config/reg_data/iGopDrm/ADA0[5] + CLMA_146_12/Q0 tco 0.222 9.589 f u_ov5640/coms1_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/Q + net (fanout=6) 0.359 9.948 u_ov5640/coms1_reg_config/reg_index [0] + DRM_142_4/ADA0[5] f u_ov5640/coms1_reg_config/reg_data/iGopDrm/ADA0[5] - Data arrival time 9.589 Logic Levels: 0 - Logic: 0.222ns(38.609%), Route: 0.353ns(61.391%) + Data arrival time 9.948 Logic Levels: 0 + Logic: 0.222ns(38.210%), Route: 0.359ns(61.790%) ---------------------------------------------------------------------------------------------------- Clock clk_20k (rising edge) 0.000 0.000 r @@ -4126,37 +4549,37 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT3 td 0.111 3.214 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 net (fanout=1) 1.078 4.292 clk_25m - USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 1.585 5.877 ntclkbufg_7 - CLMA_182_25/Q1 tco 0.291 6.168 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q - net (fanout=3) 2.059 8.227 u_ov5640/coms2_reg_config/clk_20k_regdiv - USCM_84_120/CLK_USCM td 0.000 8.227 r u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - net (fanout=19) 1.585 9.812 u_ov5640/coms2_reg_config/clock_20k - DRM_178_24/CLKA[0] r u_ov5640/coms2_reg_config/reg_data/iGopDrm/CLKA[0] - clock pessimism -0.762 9.050 - clock uncertainty 0.000 9.050 + USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 1.585 5.877 ntclkbufg_8 + CLMS_122_9/Q1 tco 0.291 6.168 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q + net (fanout=3) 2.498 8.666 u_ov5640/coms1_reg_config/clk_20k_regdiv + USCM_84_120/CLK_USCM td 0.000 8.666 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + net (fanout=19) 1.585 10.251 u_ov5640/coms1_reg_config/clock_20k + DRM_142_4/CLKA[0] r u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKA[0] + clock pessimism -0.848 9.403 + clock uncertainty 0.000 9.403 - Hold time 0.161 9.211 + Hold time 0.161 9.564 - Data required time 9.211 + Data required time 9.564 ---------------------------------------------------------------------------------------------------- - Data required time 9.211 - Data arrival time 9.589 + Data required time 9.564 + Data arrival time 9.948 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.378 + Slack (MET) 0.384 ==================================================================================================== ==================================================================================================== -Startpoint : u_ov5640/coms2_reg_config/u1/sclk/opit_0_inv_L5Q_perm/CLK -Endpoint : u_ov5640/coms2_reg_config/u1/sclk/opit_0_inv_L5Q_perm/L0 +Startpoint : u_ov5640/coms1_reg_config/u1/tr_end/opit_0_inv_L5Q_perm/CLK +Endpoint : u_ov5640/coms1_reg_config/u1/tr_end/opit_0_inv_L5Q_perm/L0 Path Group : clk_20k Path Type : min (slow corner) Path Class : sequential timing path Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 9.812 - Launch Clock Delay : 9.014 - Clock Pessimism Removal : -0.798 + Capture Clock Delay : 10.251 + Launch Clock Delay : 9.367 + Clock Pessimism Removal : -0.884 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -4170,20 +4593,20 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.758 2.688 _N69 PLL_158_55/CLK_OUT3 td 0.105 2.793 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 net (fanout=1) 1.059 3.852 clk_25m - USCM_84_114/CLK_USCM td 0.000 3.852 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 1.531 5.383 ntclkbufg_7 - CLMA_182_25/Q1 tco 0.229 5.612 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q - net (fanout=3) 1.871 7.483 u_ov5640/coms2_reg_config/clk_20k_regdiv - USCM_84_120/CLK_USCM td 0.000 7.483 r u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - net (fanout=19) 1.531 9.014 u_ov5640/coms2_reg_config/clock_20k - CLMS_174_25/CLK r u_ov5640/coms2_reg_config/u1/sclk/opit_0_inv_L5Q_perm/CLK + USCM_84_114/CLK_USCM td 0.000 3.852 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 1.531 5.383 ntclkbufg_8 + CLMS_122_9/Q1 tco 0.229 5.612 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q + net (fanout=3) 2.224 7.836 u_ov5640/coms1_reg_config/clk_20k_regdiv + USCM_84_120/CLK_USCM td 0.000 7.836 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + net (fanout=19) 1.531 9.367 u_ov5640/coms1_reg_config/clock_20k + CLMA_134_12/CLK r u_ov5640/coms1_reg_config/u1/tr_end/opit_0_inv_L5Q_perm/CLK - CLMS_174_25/Q0 tco 0.222 9.236 f u_ov5640/coms2_reg_config/u1/sclk/opit_0_inv_L5Q_perm/Q - net (fanout=2) 0.085 9.321 u_ov5640/coms2_reg_config/u1/sclk - CLMS_174_25/A0 f u_ov5640/coms2_reg_config/u1/sclk/opit_0_inv_L5Q_perm/L0 + CLMA_134_12/Q0 tco 0.222 9.589 f u_ov5640/coms1_reg_config/u1/tr_end/opit_0_inv_L5Q_perm/Q + net (fanout=3) 0.086 9.675 u_ov5640/coms1_reg_config/tr_end + CLMA_134_12/A0 f u_ov5640/coms1_reg_config/u1/tr_end/opit_0_inv_L5Q_perm/L0 - Data arrival time 9.321 Logic Levels: 0 - Logic: 0.222ns(72.313%), Route: 0.085ns(27.687%) + Data arrival time 9.675 Logic Levels: 0 + Logic: 0.222ns(72.078%), Route: 0.086ns(27.922%) ---------------------------------------------------------------------------------------------------- Clock clk_20k (rising edge) 0.000 0.000 r @@ -4195,37 +4618,37 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT3 td 0.111 3.214 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 net (fanout=1) 1.078 4.292 clk_25m - USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 1.585 5.877 ntclkbufg_7 - CLMA_182_25/Q1 tco 0.291 6.168 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q - net (fanout=3) 2.059 8.227 u_ov5640/coms2_reg_config/clk_20k_regdiv - USCM_84_120/CLK_USCM td 0.000 8.227 r u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - net (fanout=19) 1.585 9.812 u_ov5640/coms2_reg_config/clock_20k - CLMS_174_25/CLK r u_ov5640/coms2_reg_config/u1/sclk/opit_0_inv_L5Q_perm/CLK - clock pessimism -0.798 9.014 - clock uncertainty 0.000 9.014 + USCM_84_114/CLK_USCM td 0.000 4.292 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 1.585 5.877 ntclkbufg_8 + CLMS_122_9/Q1 tco 0.291 6.168 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q + net (fanout=3) 2.498 8.666 u_ov5640/coms1_reg_config/clk_20k_regdiv + USCM_84_120/CLK_USCM td 0.000 8.666 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + net (fanout=19) 1.585 10.251 u_ov5640/coms1_reg_config/clock_20k + CLMA_134_12/CLK r u_ov5640/coms1_reg_config/u1/tr_end/opit_0_inv_L5Q_perm/CLK + clock pessimism -0.884 9.367 + clock uncertainty 0.000 9.367 - Hold time -0.094 8.920 + Hold time -0.094 9.273 - Data required time 8.920 + Data required time 9.273 ---------------------------------------------------------------------------------------------------- - Data required time 8.920 - Data arrival time 9.321 + Data required time 9.273 + Data arrival time 9.675 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.401 + Slack (MET) 0.402 ==================================================================================================== ==================================================================================================== -Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[6]/opit_0_inv_L5Q_perm/CLK -Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/S0 +Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/S0 Path Group : ddrphy_clkin Path Type : max (slow corner) Path Class : sequential timing path -Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) +Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) Capture Clock Delay : 10.665 Launch Clock Delay : 11.394 - Clock Pessimism Removal : 0.675 + Clock Pessimism Removal : 0.693 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -4238,41 +4661,41 @@ Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessi IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.078 4.282 zoom_clk + net (fanout=2) 1.078 4.282 ddr_clk USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.121 7.270 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 7.618 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 2.191 9.809 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 9.809 r clkbufg_0/gopclkbufg/CLKOUT net (fanout=5464) 1.585 11.394 ntclkbufg_0 - CLMA_22_124/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[6]/opit_0_inv_L5Q_perm/CLK - - CLMA_22_124/Q2 tco 0.289 11.683 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[6]/opit_0_inv_L5Q_perm/Q - net (fanout=5) 1.236 12.919 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mr0_ddr3 [6] - CLMA_30_168/Y3 td 0.210 13.129 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/gateop_perm/Z - net (fanout=2) 0.407 13.536 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_cl [1] - td 0.477 14.013 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_1/gateop_A2/Cout - net (fanout=1) 0.000 14.013 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.co [2] - CLMA_34_168/Y2 td 0.271 14.284 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_3/gateop_A2/Y0 - net (fanout=1) 0.554 14.838 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [2] - CLMA_30_160/Y3 td 0.210 15.048 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[2]/gateop_perm/Z - net (fanout=4) 0.690 15.738 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al [2] - CLMA_30_172/COUT td 0.502 16.240 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_3/gateop_A2/Cout - net (fanout=1) 0.000 16.240 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14576 - CLMA_30_176/Y0 td 0.269 16.509 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_5/gateop/Y - net (fanout=4) 1.536 18.045 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mc_rl [4] - CLMA_30_248/Y0 td 0.487 18.532 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_159_5/gateop_perm/Z - net (fanout=40) 0.995 19.527 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24196 - CLMS_38_245/Y1 td 0.468 19.995 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_170[2]/gateop/F - net (fanout=1) 0.470 20.465 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24359 - CLMS_22_245/D3 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/S0 - - Data arrival time 20.465 Logic Levels: 7 - Logic: 3.183ns(35.090%), Route: 5.888ns(64.910%) + CLMS_10_133/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK + + CLMS_10_133/Q2 tco 0.290 11.684 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/Q + net (fanout=5) 0.687 12.371 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mr0_ddr3 [2] + CLMS_18_149/Y1 td 0.288 12.659 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/gateop_perm/Z + net (fanout=2) 0.402 13.061 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_cl [1] + td 0.477 13.538 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_1/gateop_A2/Cout + net (fanout=1) 0.000 13.538 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.co [2] + CLMS_18_145/Y3 td 0.501 14.039 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_3/gateop_A2/Y1 + net (fanout=1) 0.661 14.700 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [3] + CLMS_46_145/Y1 td 0.304 15.004 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[3]/gateop_perm/Z + net (fanout=4) 0.406 15.410 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al [3] + CLMA_50_144/COUT td 0.507 15.917 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_3/gateop_A2/Cout + net (fanout=1) 0.000 15.917 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14534 + CLMA_50_148/Y0 td 0.269 16.186 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_5/gateop/Y + net (fanout=4) 0.267 16.453 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mc_rl [4] + CLMS_46_149/Y0 td 0.285 16.738 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_159_5/gateop_perm/Z + net (fanout=40) 0.720 17.458 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23975 + CLMA_62_164/Y2 td 0.478 17.936 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_170[12]/gateop/F + net (fanout=1) 0.402 18.338 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24148 + CLMA_58_161/C3 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/S0 + + Data arrival time 18.338 Logic Levels: 7 + Logic: 3.399ns(48.949%), Route: 3.545ns(51.051%) ---------------------------------------------------------------------------------------------------- Clock ddrphy_clkin (rising edge) 10.000 10.000 r @@ -4283,42 +4706,42 @@ Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessi IOL_327_210/INCK td 0.048 11.930 r clk_ibuf/opit_1/INCK net (fanout=1) 0.758 12.688 _N69 PLL_158_55/CLK_OUT1 td 0.096 12.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.059 13.843 zoom_clk + net (fanout=2) 1.059 13.843 ddr_clk USCM_84_113/CLK_USCM td 0.000 13.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.665 15.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.665 15.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.123 15.631 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.102 16.733 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.249 16.982 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.249 16.982 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 16.982 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 16.982 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 2.152 19.134 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 19.134 r clkbufg_0/gopclkbufg/CLKOUT net (fanout=5464) 1.531 20.665 ntclkbufg_0 - CLMS_22_245/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/CLK - clock pessimism 0.675 21.340 - clock uncertainty -0.150 21.190 + CLMA_58_161/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/CLK + clock pessimism 0.693 21.358 + clock uncertainty -0.150 21.208 - Setup time -0.377 20.813 + Setup time -0.398 20.810 - Data required time 20.813 + Data required time 20.810 ---------------------------------------------------------------------------------------------------- - Data required time 20.813 - Data arrival time 20.465 + Data required time 20.810 + Data arrival time 18.338 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.348 + Slack (MET) 2.472 ==================================================================================================== ==================================================================================================== -Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[6]/opit_0_inv_L5Q_perm/CLK -Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/S0 +Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[3]/opit_0_inv_MUX4TO1Q/I2 Path Group : ddrphy_clkin Path Type : max (slow corner) Path Class : sequential timing path -Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 10.786 +Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 10.665 Launch Clock Delay : 11.394 - Clock Pessimism Removal : 0.675 + Clock Pessimism Removal : 0.693 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -4331,41 +4754,41 @@ Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.078 4.282 zoom_clk + net (fanout=2) 1.078 4.282 ddr_clk USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.121 7.270 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 7.618 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 2.191 9.809 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 9.809 r clkbufg_0/gopclkbufg/CLKOUT net (fanout=5464) 1.585 11.394 ntclkbufg_0 - CLMA_22_124/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[6]/opit_0_inv_L5Q_perm/CLK - - CLMA_22_124/Q2 tco 0.289 11.683 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[6]/opit_0_inv_L5Q_perm/Q - net (fanout=5) 1.236 12.919 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mr0_ddr3 [6] - CLMA_30_168/Y3 td 0.210 13.129 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/gateop_perm/Z - net (fanout=2) 0.407 13.536 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_cl [1] - td 0.477 14.013 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_1/gateop_A2/Cout - net (fanout=1) 0.000 14.013 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.co [2] - CLMA_34_168/Y2 td 0.271 14.284 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_3/gateop_A2/Y0 - net (fanout=1) 0.554 14.838 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [2] - CLMA_30_160/Y3 td 0.210 15.048 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[2]/gateop_perm/Z - net (fanout=4) 0.690 15.738 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al [2] - CLMA_30_172/COUT td 0.502 16.240 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_3/gateop_A2/Cout - net (fanout=1) 0.000 16.240 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14576 - CLMA_30_176/Y0 td 0.269 16.509 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_5/gateop/Y - net (fanout=4) 1.536 18.045 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mc_rl [4] - CLMA_30_248/Y0 td 0.493 18.538 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_159_5/gateop_perm/Z - net (fanout=40) 0.749 19.287 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24196 - CLMA_34_268/Y3 td 0.468 19.755 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_170[10]/gateop/F - net (fanout=1) 0.768 20.523 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24367 - CLMS_22_265/B3 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/S0 - - Data arrival time 20.523 Logic Levels: 7 - Logic: 3.189ns(34.933%), Route: 5.940ns(65.067%) + CLMS_10_133/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK + + CLMS_10_133/Q2 tco 0.290 11.684 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/Q + net (fanout=5) 0.687 12.371 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mr0_ddr3 [2] + CLMS_18_149/Y1 td 0.288 12.659 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/gateop_perm/Z + net (fanout=2) 0.402 13.061 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_cl [1] + td 0.477 13.538 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_1/gateop_A2/Cout + net (fanout=1) 0.000 13.538 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.co [2] + CLMS_18_145/Y3 td 0.501 14.039 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_3/gateop_A2/Y1 + net (fanout=1) 0.661 14.700 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [3] + CLMS_46_145/Y1 td 0.304 15.004 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[3]/gateop_perm/Z + net (fanout=4) 0.406 15.410 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al [3] + CLMA_50_144/COUT td 0.507 15.917 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_3/gateop_A2/Cout + net (fanout=1) 0.000 15.917 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14534 + CLMA_50_148/Y0 td 0.269 16.186 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_5/gateop/Y + net (fanout=4) 0.406 16.592 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mc_rl [4] + CLMS_46_145/Y0 td 0.285 16.877 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_198_5/gateop_perm/Z + net (fanout=56) 0.635 17.512 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23906 + CLMS_50_157/Y2 td 0.210 17.722 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[15]/gateop_perm/Z + net (fanout=1) 0.581 18.303 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23991 + CLMA_58_156/C2 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[3]/opit_0_inv_MUX4TO1Q/I2 + + Data arrival time 18.303 Logic Levels: 7 + Logic: 3.131ns(45.318%), Route: 3.778ns(54.682%) ---------------------------------------------------------------------------------------------------- Clock ddrphy_clkin (rising edge) 10.000 10.000 r @@ -4376,42 +4799,42 @@ Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.048 11.930 r clk_ibuf/opit_1/INCK net (fanout=1) 0.758 12.688 _N69 PLL_158_55/CLK_OUT1 td 0.096 12.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.059 13.843 zoom_clk + net (fanout=2) 1.059 13.843 ddr_clk USCM_84_113/CLK_USCM td 0.000 13.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.665 15.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.665 15.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.123 15.631 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.102 16.733 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.249 16.982 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.249 16.982 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 16.982 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 16.982 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 2.152 19.134 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 19.134 r clkbufg_0/gopclkbufg/CLKOUT - net (fanout=5464) 1.652 20.786 ntclkbufg_0 - CLMS_22_265/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/CLK - clock pessimism 0.675 21.461 - clock uncertainty -0.150 21.311 + net (fanout=5464) 1.531 20.665 ntclkbufg_0 + CLMA_58_156/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[3]/opit_0_inv_MUX4TO1Q/CLK + clock pessimism 0.693 21.358 + clock uncertainty -0.150 21.208 - Setup time -0.377 20.934 + Setup time -0.391 20.817 - Data required time 20.934 + Data required time 20.817 ---------------------------------------------------------------------------------------------------- - Data required time 20.934 - Data arrival time 20.523 + Data required time 20.817 + Data arrival time 18.303 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.411 + Slack (MET) 2.514 ==================================================================================================== ==================================================================================================== -Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[6]/opit_0_inv_L5Q_perm/CLK -Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/S0 +Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/I2 Path Group : ddrphy_clkin Path Type : max (slow corner) Path Class : sequential timing path -Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) +Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) Capture Clock Delay : 10.665 Launch Clock Delay : 11.394 - Clock Pessimism Removal : 0.675 + Clock Pessimism Removal : 0.693 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -4424,41 +4847,41 @@ Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessi IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.078 4.282 zoom_clk + net (fanout=2) 1.078 4.282 ddr_clk USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.121 7.270 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 7.618 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 2.191 9.809 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 9.809 r clkbufg_0/gopclkbufg/CLKOUT net (fanout=5464) 1.585 11.394 ntclkbufg_0 - CLMA_22_124/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[6]/opit_0_inv_L5Q_perm/CLK - - CLMA_22_124/Q2 tco 0.289 11.683 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[6]/opit_0_inv_L5Q_perm/Q - net (fanout=5) 1.236 12.919 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mr0_ddr3 [6] - CLMA_30_168/Y3 td 0.210 13.129 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/gateop_perm/Z - net (fanout=2) 0.407 13.536 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_cl [1] - td 0.477 14.013 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_1/gateop_A2/Cout - net (fanout=1) 0.000 14.013 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.co [2] - CLMA_34_168/Y2 td 0.271 14.284 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_3/gateop_A2/Y0 - net (fanout=1) 0.554 14.838 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [2] - CLMA_30_160/Y3 td 0.210 15.048 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[2]/gateop_perm/Z - net (fanout=4) 0.690 15.738 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al [2] - CLMA_30_172/COUT td 0.502 16.240 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_3/gateop_A2/Cout - net (fanout=1) 0.000 16.240 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14576 - CLMA_30_176/Y0 td 0.269 16.509 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_5/gateop/Y - net (fanout=4) 1.536 18.045 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mc_rl [4] - CLMA_30_248/Y0 td 0.493 18.538 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_159_5/gateop_perm/Z - net (fanout=40) 0.731 19.269 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24196 - CLMA_30_248/Y1 td 0.468 19.737 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_170[0]/gateop/F - net (fanout=1) 0.638 20.375 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24357 - CLMS_22_245/A3 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/S0 - - Data arrival time 20.375 Logic Levels: 7 - Logic: 3.189ns(35.508%), Route: 5.792ns(64.492%) + CLMS_10_133/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK + + CLMS_10_133/Q2 tco 0.290 11.684 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/Q + net (fanout=5) 0.687 12.371 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mr0_ddr3 [2] + CLMS_18_149/Y1 td 0.288 12.659 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/gateop_perm/Z + net (fanout=2) 0.402 13.061 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_cl [1] + td 0.477 13.538 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_1/gateop_A2/Cout + net (fanout=1) 0.000 13.538 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.co [2] + CLMS_18_145/Y3 td 0.501 14.039 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_3/gateop_A2/Y1 + net (fanout=1) 0.661 14.700 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [3] + CLMS_46_145/Y1 td 0.304 15.004 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[3]/gateop_perm/Z + net (fanout=4) 0.406 15.410 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al [3] + CLMA_50_144/COUT td 0.507 15.917 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_3/gateop_A2/Cout + net (fanout=1) 0.000 15.917 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14534 + CLMA_50_148/Y0 td 0.269 16.186 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_5/gateop/Y + net (fanout=4) 0.406 16.592 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mc_rl [4] + CLMS_46_145/Y0 td 0.294 16.886 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_198_5/gateop_perm/Z + net (fanout=56) 0.643 17.529 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23906 + CLMA_62_160/Y3 td 0.210 17.739 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[14]/gateop_perm/Z + net (fanout=1) 0.554 18.293 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23990 + CLMA_58_161/A2 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/I2 + + Data arrival time 18.293 Logic Levels: 7 + Logic: 3.140ns(45.514%), Route: 3.759ns(54.486%) ---------------------------------------------------------------------------------------------------- Clock ddrphy_clkin (rising edge) 10.000 10.000 r @@ -4469,42 +4892,42 @@ Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessi IOL_327_210/INCK td 0.048 11.930 r clk_ibuf/opit_1/INCK net (fanout=1) 0.758 12.688 _N69 PLL_158_55/CLK_OUT1 td 0.096 12.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.059 13.843 zoom_clk + net (fanout=2) 1.059 13.843 ddr_clk USCM_84_113/CLK_USCM td 0.000 13.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.665 15.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.665 15.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.123 15.631 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.102 16.733 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.249 16.982 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.249 16.982 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 16.982 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 16.982 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 2.152 19.134 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 19.134 r clkbufg_0/gopclkbufg/CLKOUT net (fanout=5464) 1.531 20.665 ntclkbufg_0 - CLMS_22_245/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/CLK - clock pessimism 0.675 21.340 - clock uncertainty -0.150 21.190 + CLMA_58_161/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/CLK + clock pessimism 0.693 21.358 + clock uncertainty -0.150 21.208 - Setup time -0.397 20.793 + Setup time -0.388 20.820 - Data required time 20.793 + Data required time 20.820 ---------------------------------------------------------------------------------------------------- - Data required time 20.793 - Data arrival time 20.375 + Data required time 20.820 + Data arrival time 18.293 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.418 + Slack (MET) 2.527 ==================================================================================================== ==================================================================================================== -Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[22]/opit_0_inv/CLK -Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_27/ram16x1d/WD +Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[16]/opit_0_inv/CLK +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_21/ram16x1d/WD Path Group : ddrphy_clkin Path Type : min (slow corner) Path Class : sequential timing path -Clock Skew : 0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) +Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) Capture Clock Delay : 11.394 Launch Clock Delay : 10.665 - Clock Pessimism Removal : -0.675 + Clock Pessimism Removal : -0.693 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -4517,25 +4940,25 @@ Clock Skew : 0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK net (fanout=1) 0.758 2.688 _N69 PLL_158_55/CLK_OUT1 td 0.096 2.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.059 3.843 zoom_clk + net (fanout=2) 1.059 3.843 ddr_clk USCM_84_113/CLK_USCM td 0.000 3.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.123 5.631 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.102 6.733 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.249 6.982 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.249 6.982 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 6.982 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 6.982 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 2.152 9.134 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 9.134 r clkbufg_0/gopclkbufg/CLKOUT net (fanout=5464) 1.531 10.665 ntclkbufg_0 - CLMA_58_124/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[22]/opit_0_inv/CLK + CLMA_50_96/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[16]/opit_0_inv/CLK - CLMA_58_124/Q0 tco 0.222 10.887 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[22]/opit_0_inv/Q - net (fanout=2) 0.361 11.248 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/dcd_wr_addr [22] - CLMS_50_129/DD f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_27/ram16x1d/WD + CLMA_50_96/Q0 tco 0.222 10.887 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[16]/opit_0_inv/Q + net (fanout=2) 0.355 11.242 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/dcd_wr_addr [16] + CLMS_34_97/AD f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_21/ram16x1d/WD - Data arrival time 11.248 Logic Levels: 0 - Logic: 0.222ns(38.079%), Route: 0.361ns(61.921%) + Data arrival time 11.242 Logic Levels: 0 + Logic: 0.222ns(38.475%), Route: 0.355ns(61.525%) ---------------------------------------------------------------------------------------------------- Clock ddrphy_clkin (rising edge) 0.000 0.000 r @@ -4546,41 +4969,41 @@ Clock Skew : 0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.078 4.282 zoom_clk + net (fanout=2) 1.078 4.282 ddr_clk USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.121 7.270 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 7.618 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 2.191 9.809 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 9.809 r clkbufg_0/gopclkbufg/CLKOUT net (fanout=5464) 1.585 11.394 ntclkbufg_0 - CLMS_50_129/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_27/ram16x1d/WCLK - clock pessimism -0.675 10.719 - clock uncertainty 0.000 10.719 + CLMS_34_97/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_21/ram16x1d/WCLK + clock pessimism -0.693 10.701 + clock uncertainty 0.000 10.701 - Hold time 0.380 11.099 + Hold time 0.380 11.081 - Data required time 11.099 + Data required time 11.081 ---------------------------------------------------------------------------------------------------- - Data required time 11.099 - Data arrival time 11.248 + Data required time 11.081 + Data arrival time 11.242 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.149 + Slack (MET) 0.161 ==================================================================================================== ==================================================================================================== -Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK -Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_0/ram32x1dp/WADM0 +Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[12]/opit_0_inv/CLK +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_17/ram16x1d/WD Path Group : ddrphy_clkin Path Type : min (slow corner) Path Class : sequential timing path -Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 11.394 - Launch Clock Delay : 10.665 +Clock Skew : 0.022 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 11.436 + Launch Clock Delay : 10.721 Clock Pessimism Removal : -0.693 Location Delay Type Incr Path Logical Resource @@ -4594,25 +5017,25 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK net (fanout=1) 0.758 2.688 _N69 PLL_158_55/CLK_OUT1 td 0.096 2.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.059 3.843 zoom_clk + net (fanout=2) 1.059 3.843 ddr_clk USCM_84_113/CLK_USCM td 0.000 3.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.123 5.631 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.102 6.733 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.249 6.982 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.249 6.982 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 6.982 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 6.982 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 2.152 9.134 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 9.134 r clkbufg_0/gopclkbufg/CLKOUT - net (fanout=5464) 1.531 10.665 ntclkbufg_0 - CLMA_58_144/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK + net (fanout=5464) 1.587 10.721 ntclkbufg_0 + CLMS_42_85/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[12]/opit_0_inv/CLK - CLMA_58_144/Q0 tco 0.222 10.887 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/Q0 - net (fanout=7) 0.356 11.243 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [0] - CLMS_62_145/M0 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_0/ram32x1dp/WADM0 + CLMS_42_85/Q1 tco 0.224 10.945 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[12]/opit_0_inv/Q + net (fanout=2) 0.342 11.287 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/dcd_wr_addr [12] + CLMS_38_81/DD f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_17/ram16x1d/WD - Data arrival time 11.243 Logic Levels: 0 - Logic: 0.222ns(38.408%), Route: 0.356ns(61.592%) + Data arrival time 11.287 Logic Levels: 0 + Logic: 0.224ns(39.576%), Route: 0.342ns(60.424%) ---------------------------------------------------------------------------------------------------- Clock ddrphy_clkin (rising edge) 0.000 0.000 r @@ -4623,41 +5046,41 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.078 4.282 zoom_clk + net (fanout=2) 1.078 4.282 ddr_clk USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.121 7.270 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 7.618 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 2.191 9.809 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 9.809 r clkbufg_0/gopclkbufg/CLKOUT - net (fanout=5464) 1.585 11.394 ntclkbufg_0 - CLMS_62_145/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_0/ram32x1dp/WCLK - clock pessimism -0.693 10.701 - clock uncertainty 0.000 10.701 + net (fanout=5464) 1.627 11.436 ntclkbufg_0 + CLMS_38_81/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_17/ram16x1d/WCLK + clock pessimism -0.693 10.743 + clock uncertainty 0.000 10.743 - Hold time 0.380 11.081 + Hold time 0.380 11.123 - Data required time 11.081 + Data required time 11.123 ---------------------------------------------------------------------------------------------------- - Data required time 11.081 - Data arrival time 11.243 + Data required time 11.123 + Data arrival time 11.287 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.162 + Slack (MET) 0.164 ==================================================================================================== ==================================================================================================== -Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK -Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram32x1dp/WADM0 +Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_15/ram16x1d/WADM0 Path Group : ddrphy_clkin Path Type : min (slow corner) Path Class : sequential timing path -Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 11.394 - Launch Clock Delay : 10.665 +Clock Skew : 0.062 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 11.446 + Launch Clock Delay : 10.691 Clock Pessimism Removal : -0.693 Location Delay Type Incr Path Logical Resource @@ -4671,25 +5094,25 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK net (fanout=1) 0.758 2.688 _N69 PLL_158_55/CLK_OUT1 td 0.096 2.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.059 3.843 zoom_clk + net (fanout=2) 1.059 3.843 ddr_clk USCM_84_113/CLK_USCM td 0.000 3.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.123 5.631 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.102 6.733 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.249 6.982 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.249 6.982 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 6.982 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 6.982 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 2.152 9.134 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 9.134 r clkbufg_0/gopclkbufg/CLKOUT - net (fanout=5464) 1.531 10.665 ntclkbufg_0 - CLMA_58_144/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK + net (fanout=5464) 1.557 10.691 ntclkbufg_0 + CLMA_34_76/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK - CLMA_58_144/Q0 tco 0.222 10.887 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/Q0 - net (fanout=7) 0.356 11.243 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [0] - CLMS_62_145/M0 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram32x1dp/WADM0 + CLMA_34_76/Q0 tco 0.222 10.913 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/Q0 + net (fanout=44) 0.392 11.305 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [0] + CLMS_42_81/M0 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_15/ram16x1d/WADM0 - Data arrival time 11.243 Logic Levels: 0 - Logic: 0.222ns(38.408%), Route: 0.356ns(61.592%) + Data arrival time 11.305 Logic Levels: 0 + Logic: 0.222ns(36.156%), Route: 0.392ns(63.844%) ---------------------------------------------------------------------------------------------------- Clock ddrphy_clkin (rising edge) 0.000 0.000 r @@ -4700,29 +5123,29 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.078 4.282 zoom_clk + net (fanout=2) 1.078 4.282 ddr_clk USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.121 7.270 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 7.618 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 2.191 9.809 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 9.809 r clkbufg_0/gopclkbufg/CLKOUT - net (fanout=5464) 1.585 11.394 ntclkbufg_0 - CLMS_62_145/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram32x1dp/WCLK - clock pessimism -0.693 10.701 - clock uncertainty 0.000 10.701 + net (fanout=5464) 1.637 11.446 ntclkbufg_0 + CLMS_42_81/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_15/ram16x1d/WCLK + clock pessimism -0.693 10.753 + clock uncertainty 0.000 10.753 - Hold time 0.380 11.081 + Hold time 0.380 11.133 - Data required time 11.081 + Data required time 11.133 ---------------------------------------------------------------------------------------------------- - Data required time 11.081 - Data arrival time 11.243 + Data required time 11.133 + Data arrival time 11.305 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.162 + Slack (MET) 0.172 ==================================================================================================== ==================================================================================================== @@ -4748,9 +5171,9 @@ Clock Skew : 0.006 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.078 4.282 zoom_clk + net (fanout=2) 1.078 4.282 ddr_clk USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.121 7.270 clkout0_wl_0 IOCKGATE_6_312/OUT td 0.348 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT @@ -4773,9 +5196,9 @@ Clock Skew : 0.006 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.048 4.430 r clk_ibuf/opit_1/INCK net (fanout=1) 0.758 5.188 _N69 PLL_158_55/CLK_OUT1 td 0.096 5.284 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.059 6.343 zoom_clk + net (fanout=2) 1.059 6.343 ddr_clk USCM_84_113/CLK_USCM td 0.000 6.343 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.665 8.008 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.665 8.008 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.123 8.131 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.102 9.233 clkout0_wl_0 IOCKGATE_6_312/OUT td 0.249 9.482 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT @@ -4817,9 +5240,9 @@ Clock Skew : 0.006 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.078 4.282 zoom_clk + net (fanout=2) 1.078 4.282 ddr_clk USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.121 7.270 clkout0_wl_0 IOCKGATE_6_312/OUT td 0.348 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT @@ -4842,9 +5265,9 @@ Clock Skew : 0.006 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.048 4.430 r clk_ibuf/opit_1/INCK net (fanout=1) 0.758 5.188 _N69 PLL_158_55/CLK_OUT1 td 0.096 5.284 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.059 6.343 zoom_clk + net (fanout=2) 1.059 6.343 ddr_clk USCM_84_113/CLK_USCM td 0.000 6.343 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.665 8.008 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.665 8.008 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.123 8.131 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.102 9.233 clkout0_wl_0 IOCKGATE_6_312/OUT td 0.249 9.482 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT @@ -4886,9 +5309,9 @@ Clock Skew : 0.006 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.078 4.282 zoom_clk + net (fanout=2) 1.078 4.282 ddr_clk USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.121 7.270 clkout0_wl_0 IOCKGATE_6_312/OUT td 0.348 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT @@ -4911,9 +5334,9 @@ Clock Skew : 0.006 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.048 4.430 r clk_ibuf/opit_1/INCK net (fanout=1) 0.758 5.188 _N69 PLL_158_55/CLK_OUT1 td 0.096 5.284 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.059 6.343 zoom_clk + net (fanout=2) 1.059 6.343 ddr_clk USCM_84_113/CLK_USCM td 0.000 6.343 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.665 8.008 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.665 8.008 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.123 8.131 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.102 9.233 clkout0_wl_0 IOCKGATE_6_312/OUT td 0.249 9.482 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT @@ -4955,9 +5378,9 @@ Clock Skew : 0.035 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK net (fanout=1) 0.758 2.688 _N69 PLL_158_55/CLK_OUT1 td 0.096 2.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.059 3.843 zoom_clk + net (fanout=2) 1.059 3.843 ddr_clk USCM_84_113/CLK_USCM td 0.000 3.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.123 5.631 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.102 6.733 clkout0_wl_0 IOCKGATE_6_312/OUT td 0.249 6.982 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT @@ -4980,9 +5403,9 @@ Clock Skew : 0.035 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.078 4.282 zoom_clk + net (fanout=2) 1.078 4.282 ddr_clk USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.121 7.270 clkout0_wl_0 IOCKGATE_6_312/OUT td 0.348 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT @@ -5024,9 +5447,9 @@ Clock Skew : 0.035 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK net (fanout=1) 0.758 2.688 _N69 PLL_158_55/CLK_OUT1 td 0.096 2.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.059 3.843 zoom_clk + net (fanout=2) 1.059 3.843 ddr_clk USCM_84_113/CLK_USCM td 0.000 3.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.123 5.631 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.102 6.733 clkout0_wl_0 IOCKGATE_6_312/OUT td 0.249 6.982 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT @@ -5049,9 +5472,9 @@ Clock Skew : 0.035 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.078 4.282 zoom_clk + net (fanout=2) 1.078 4.282 ddr_clk USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.121 7.270 clkout0_wl_0 IOCKGATE_6_312/OUT td 0.348 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT @@ -5093,9 +5516,9 @@ Clock Skew : 0.035 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK net (fanout=1) 0.758 2.688 _N69 PLL_158_55/CLK_OUT1 td 0.096 2.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.059 3.843 zoom_clk + net (fanout=2) 1.059 3.843 ddr_clk USCM_84_113/CLK_USCM td 0.000 3.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.123 5.631 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.102 6.733 clkout0_wl_0 IOCKGATE_6_312/OUT td 0.249 6.982 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT @@ -5118,9 +5541,9 @@ Clock Skew : 0.035 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.078 4.282 zoom_clk + net (fanout=2) 1.078 4.282 ddr_clk USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.121 7.270 clkout0_wl_0 IOCKGATE_6_312/OUT td 0.348 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT @@ -5162,9 +5585,9 @@ Clock Skew : 0.006 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.078 4.282 zoom_clk + net (fanout=2) 1.078 4.282 ddr_clk USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.121 7.270 clkout0_wl_0 IOCKGATE_6_188/OUT td 0.348 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT @@ -5187,9 +5610,9 @@ Clock Skew : 0.006 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.048 4.430 r clk_ibuf/opit_1/INCK net (fanout=1) 0.758 5.188 _N69 PLL_158_55/CLK_OUT1 td 0.096 5.284 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.059 6.343 zoom_clk + net (fanout=2) 1.059 6.343 ddr_clk USCM_84_113/CLK_USCM td 0.000 6.343 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.665 8.008 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.665 8.008 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.123 8.131 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.102 9.233 clkout0_wl_0 IOCKGATE_6_188/OUT td 0.249 9.482 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT @@ -5231,9 +5654,9 @@ Clock Skew : 0.006 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.078 4.282 zoom_clk + net (fanout=2) 1.078 4.282 ddr_clk USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.121 7.270 clkout0_wl_0 IOCKGATE_6_188/OUT td 0.348 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT @@ -5256,9 +5679,9 @@ Clock Skew : 0.006 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.048 4.430 r clk_ibuf/opit_1/INCK net (fanout=1) 0.758 5.188 _N69 PLL_158_55/CLK_OUT1 td 0.096 5.284 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.059 6.343 zoom_clk + net (fanout=2) 1.059 6.343 ddr_clk USCM_84_113/CLK_USCM td 0.000 6.343 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.665 8.008 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.665 8.008 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.123 8.131 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.102 9.233 clkout0_wl_0 IOCKGATE_6_188/OUT td 0.249 9.482 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT @@ -5300,9 +5723,9 @@ Clock Skew : 0.006 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.078 4.282 zoom_clk + net (fanout=2) 1.078 4.282 ddr_clk USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.121 7.270 clkout0_wl_0 IOCKGATE_6_188/OUT td 0.348 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT @@ -5325,9 +5748,9 @@ Clock Skew : 0.006 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.048 4.430 r clk_ibuf/opit_1/INCK net (fanout=1) 0.758 5.188 _N69 PLL_158_55/CLK_OUT1 td 0.096 5.284 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.059 6.343 zoom_clk + net (fanout=2) 1.059 6.343 ddr_clk USCM_84_113/CLK_USCM td 0.000 6.343 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.665 8.008 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.665 8.008 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.123 8.131 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.102 9.233 clkout0_wl_0 IOCKGATE_6_188/OUT td 0.249 9.482 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT @@ -5369,9 +5792,9 @@ Clock Skew : 0.035 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK net (fanout=1) 0.758 2.688 _N69 PLL_158_55/CLK_OUT1 td 0.096 2.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.059 3.843 zoom_clk + net (fanout=2) 1.059 3.843 ddr_clk USCM_84_113/CLK_USCM td 0.000 3.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.123 5.631 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.102 6.733 clkout0_wl_0 IOCKGATE_6_188/OUT td 0.249 6.982 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT @@ -5394,9 +5817,9 @@ Clock Skew : 0.035 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.078 4.282 zoom_clk + net (fanout=2) 1.078 4.282 ddr_clk USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.121 7.270 clkout0_wl_0 IOCKGATE_6_188/OUT td 0.348 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT @@ -5438,9 +5861,9 @@ Clock Skew : 0.035 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK net (fanout=1) 0.758 2.688 _N69 PLL_158_55/CLK_OUT1 td 0.096 2.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.059 3.843 zoom_clk + net (fanout=2) 1.059 3.843 ddr_clk USCM_84_113/CLK_USCM td 0.000 3.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.123 5.631 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.102 6.733 clkout0_wl_0 IOCKGATE_6_188/OUT td 0.249 6.982 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT @@ -5463,9 +5886,9 @@ Clock Skew : 0.035 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.078 4.282 zoom_clk + net (fanout=2) 1.078 4.282 ddr_clk USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.121 7.270 clkout0_wl_0 IOCKGATE_6_188/OUT td 0.348 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT @@ -5507,9 +5930,9 @@ Clock Skew : 0.035 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK net (fanout=1) 0.758 2.688 _N69 PLL_158_55/CLK_OUT1 td 0.096 2.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.059 3.843 zoom_clk + net (fanout=2) 1.059 3.843 ddr_clk USCM_84_113/CLK_USCM td 0.000 3.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.123 5.631 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.102 6.733 clkout0_wl_0 IOCKGATE_6_188/OUT td 0.249 6.982 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT @@ -5532,9 +5955,9 @@ Clock Skew : 0.035 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.078 4.282 zoom_clk + net (fanout=2) 1.078 4.282 ddr_clk USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.121 7.270 clkout0_wl_0 IOCKGATE_6_188/OUT td 0.348 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT @@ -5556,12 +5979,12 @@ Clock Skew : 0.035 (Capture Clock Delay - Launch Clock Delay + Clock Pessim ==================================================================================================== Startpoint : u_clk50m_rst/rst/opit_0_L5Q_perm/CLK -Endpoint : u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/RS +Endpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/RS Path Group : clk_50m Path Type : max (slow corner) Path Class : async timing path -Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.378 +Clock Skew : -0.040 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 5.392 Launch Clock Delay : 5.873 Clock Pessimism Removal : 0.441 @@ -5578,29 +6001,15 @@ Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessi PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 1.078 4.288 rd3_clk USCM_84_108/CLK_USCM td 0.000 4.288 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 1.585 5.873 ntclkbufg_1 - CLMS_94_177/CLK r u_clk50m_rst/rst/opit_0_L5Q_perm/CLK - - CLMS_94_177/Q0 tco 0.287 6.160 f u_clk50m_rst/rst/opit_0_L5Q_perm/Q - net (fanout=573) 2.441 8.601 rd3_rst - CLMS_146_37/RSCO td 0.147 8.748 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/RSOUT - net (fanout=4) 0.000 8.748 ntR414 - CLMS_146_41/RSCO td 0.147 8.895 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/RSOUT - net (fanout=4) 0.000 8.895 ntR413 - CLMS_146_45/RSCO td 0.147 9.042 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/RSOUT - net (fanout=3) 0.000 9.042 ntR412 - CLMS_146_49/RSCO td 0.147 9.189 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/RSOUT - net (fanout=2) 0.000 9.189 ntR411 - CLMS_146_53/RSCO td 0.147 9.336 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/RSOUT - net (fanout=4) 0.000 9.336 ntR410 - CLMS_146_57/RSCO td 0.147 9.483 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/RSOUT - net (fanout=6) 0.000 9.483 ntR409 - CLMS_146_61/RSCO td 0.147 9.630 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/RSOUT - net (fanout=5) 0.000 9.630 ntR408 - CLMS_146_69/RSCI f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/RS - - Data arrival time 9.630 Logic Levels: 7 - Logic: 1.316ns(35.028%), Route: 2.441ns(64.972%) + net (fanout=2516) 1.585 5.873 ntclkbufg_1 + CLMS_158_237/CLK r u_clk50m_rst/rst/opit_0_L5Q_perm/CLK + + CLMS_158_237/Q0 tco 0.287 6.160 f u_clk50m_rst/rst/opit_0_L5Q_perm/Q + net (fanout=589) 3.130 9.290 rd3_rst + CLMA_58_40/RS f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/RS + + Data arrival time 9.290 Logic Levels: 0 + Logic: 0.287ns(8.399%), Route: 3.130ns(91.601%) ---------------------------------------------------------------------------------------------------- Clock clk_50m (rising edge) 20.000 20.000 r @@ -5613,30 +6022,30 @@ Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessi PLL_158_55/CLK_OUT0 td 0.100 22.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 1.059 23.847 rd3_clk USCM_84_108/CLK_USCM td 0.000 23.847 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 1.531 25.378 ntclkbufg_1 - CLMS_146_69/CLK r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/CLK - clock pessimism 0.441 25.819 - clock uncertainty -0.150 25.669 + net (fanout=2516) 1.545 25.392 ntclkbufg_1 + CLMA_58_40/CLK r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK + clock pessimism 0.441 25.833 + clock uncertainty -0.150 25.683 - Recovery time 0.000 25.669 + Recovery time -0.617 25.066 - Data required time 25.669 + Data required time 25.066 ---------------------------------------------------------------------------------------------------- - Data required time 25.669 - Data arrival time 9.630 + Data required time 25.066 + Data arrival time 9.290 ---------------------------------------------------------------------------------------------------- - Slack (MET) 16.039 + Slack (MET) 15.776 ==================================================================================================== ==================================================================================================== Startpoint : u_clk50m_rst/rst/opit_0_L5Q_perm/CLK -Endpoint : u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/RS +Endpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[1]/opit_0_A2Q21/RS Path Group : clk_50m Path Type : max (slow corner) Path Class : async timing path -Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.378 +Clock Skew : -0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 5.403 Launch Clock Delay : 5.873 Clock Pessimism Removal : 0.441 @@ -5653,29 +6062,15 @@ Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessi PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 1.078 4.288 rd3_clk USCM_84_108/CLK_USCM td 0.000 4.288 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 1.585 5.873 ntclkbufg_1 - CLMS_94_177/CLK r u_clk50m_rst/rst/opit_0_L5Q_perm/CLK - - CLMS_94_177/Q0 tco 0.287 6.160 f u_clk50m_rst/rst/opit_0_L5Q_perm/Q - net (fanout=573) 2.441 8.601 rd3_rst - CLMS_146_37/RSCO td 0.147 8.748 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/RSOUT - net (fanout=4) 0.000 8.748 ntR414 - CLMS_146_41/RSCO td 0.147 8.895 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/RSOUT - net (fanout=4) 0.000 8.895 ntR413 - CLMS_146_45/RSCO td 0.147 9.042 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/RSOUT - net (fanout=3) 0.000 9.042 ntR412 - CLMS_146_49/RSCO td 0.147 9.189 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/RSOUT - net (fanout=2) 0.000 9.189 ntR411 - CLMS_146_53/RSCO td 0.147 9.336 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/RSOUT - net (fanout=4) 0.000 9.336 ntR410 - CLMS_146_57/RSCO td 0.147 9.483 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/RSOUT - net (fanout=6) 0.000 9.483 ntR409 - CLMS_146_61/RSCO td 0.147 9.630 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/RSOUT - net (fanout=5) 0.000 9.630 ntR408 - CLMS_146_69/RSCI f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/RS - - Data arrival time 9.630 Logic Levels: 7 - Logic: 1.316ns(35.028%), Route: 2.441ns(64.972%) + net (fanout=2516) 1.585 5.873 ntclkbufg_1 + CLMS_158_237/CLK r u_clk50m_rst/rst/opit_0_L5Q_perm/CLK + + CLMS_158_237/Q0 tco 0.287 6.160 f u_clk50m_rst/rst/opit_0_L5Q_perm/Q + net (fanout=589) 2.965 9.125 rd3_rst + CLMA_58_33/RS f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[1]/opit_0_A2Q21/RS + + Data arrival time 9.125 Logic Levels: 0 + Logic: 0.287ns(8.825%), Route: 2.965ns(91.175%) ---------------------------------------------------------------------------------------------------- Clock clk_50m (rising edge) 20.000 20.000 r @@ -5688,30 +6083,30 @@ Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessi PLL_158_55/CLK_OUT0 td 0.100 22.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 1.059 23.847 rd3_clk USCM_84_108/CLK_USCM td 0.000 23.847 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 1.531 25.378 ntclkbufg_1 - CLMS_146_69/CLK r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/CLK - clock pessimism 0.441 25.819 - clock uncertainty -0.150 25.669 + net (fanout=2516) 1.556 25.403 ntclkbufg_1 + CLMA_58_33/CLK r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[1]/opit_0_A2Q21/CLK + clock pessimism 0.441 25.844 + clock uncertainty -0.150 25.694 - Recovery time 0.000 25.669 + Recovery time -0.617 25.077 - Data required time 25.669 + Data required time 25.077 ---------------------------------------------------------------------------------------------------- - Data required time 25.669 - Data arrival time 9.630 + Data required time 25.077 + Data arrival time 9.125 ---------------------------------------------------------------------------------------------------- - Slack (MET) 16.039 + Slack (MET) 15.952 ==================================================================================================== ==================================================================================================== Startpoint : u_clk50m_rst/rst/opit_0_L5Q_perm/CLK -Endpoint : u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/opit_0/RS +Endpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[3]/opit_0_A2Q21/RS Path Group : clk_50m Path Type : max (slow corner) Path Class : async timing path -Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.378 +Clock Skew : -0.029 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 5.403 Launch Clock Delay : 5.873 Clock Pessimism Removal : 0.441 @@ -5728,29 +6123,15 @@ Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessi PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 1.078 4.288 rd3_clk USCM_84_108/CLK_USCM td 0.000 4.288 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 1.585 5.873 ntclkbufg_1 - CLMS_94_177/CLK r u_clk50m_rst/rst/opit_0_L5Q_perm/CLK - - CLMS_94_177/Q0 tco 0.287 6.160 f u_clk50m_rst/rst/opit_0_L5Q_perm/Q - net (fanout=573) 2.441 8.601 rd3_rst - CLMS_146_37/RSCO td 0.147 8.748 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/RSOUT - net (fanout=4) 0.000 8.748 ntR414 - CLMS_146_41/RSCO td 0.147 8.895 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/RSOUT - net (fanout=4) 0.000 8.895 ntR413 - CLMS_146_45/RSCO td 0.147 9.042 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/RSOUT - net (fanout=3) 0.000 9.042 ntR412 - CLMS_146_49/RSCO td 0.147 9.189 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/RSOUT - net (fanout=2) 0.000 9.189 ntR411 - CLMS_146_53/RSCO td 0.147 9.336 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/RSOUT - net (fanout=4) 0.000 9.336 ntR410 - CLMS_146_57/RSCO td 0.147 9.483 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/RSOUT - net (fanout=6) 0.000 9.483 ntR409 - CLMS_146_61/RSCO td 0.147 9.630 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/RSOUT - net (fanout=5) 0.000 9.630 ntR408 - CLMS_146_69/RSCI f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/opit_0/RS - - Data arrival time 9.630 Logic Levels: 7 - Logic: 1.316ns(35.028%), Route: 2.441ns(64.972%) + net (fanout=2516) 1.585 5.873 ntclkbufg_1 + CLMS_158_237/CLK r u_clk50m_rst/rst/opit_0_L5Q_perm/CLK + + CLMS_158_237/Q0 tco 0.287 6.160 f u_clk50m_rst/rst/opit_0_L5Q_perm/Q + net (fanout=589) 2.965 9.125 rd3_rst + CLMA_58_33/RS f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[3]/opit_0_A2Q21/RS + + Data arrival time 9.125 Logic Levels: 0 + Logic: 0.287ns(8.825%), Route: 2.965ns(91.175%) ---------------------------------------------------------------------------------------------------- Clock clk_50m (rising edge) 20.000 20.000 r @@ -5763,32 +6144,32 @@ Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessi PLL_158_55/CLK_OUT0 td 0.100 22.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 1.059 23.847 rd3_clk USCM_84_108/CLK_USCM td 0.000 23.847 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 1.531 25.378 ntclkbufg_1 - CLMS_146_69/CLK r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/opit_0/CLK - clock pessimism 0.441 25.819 - clock uncertainty -0.150 25.669 + net (fanout=2516) 1.556 25.403 ntclkbufg_1 + CLMA_58_33/CLK r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[3]/opit_0_A2Q21/CLK + clock pessimism 0.441 25.844 + clock uncertainty -0.150 25.694 - Recovery time 0.000 25.669 + Recovery time -0.617 25.077 - Data required time 25.669 + Data required time 25.077 ---------------------------------------------------------------------------------------------------- - Data required time 25.669 - Data arrival time 9.630 + Data required time 25.077 + Data arrival time 9.125 ---------------------------------------------------------------------------------------------------- - Slack (MET) 16.039 + Slack (MET) 15.952 ==================================================================================================== ==================================================================================================== Startpoint : image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK -Endpoint : image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0] +Endpoint : image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0] Path Group : clk_50m Path Type : min (slow corner) Path Class : async timing path Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.873 - Launch Clock Delay : 5.378 - Clock Pessimism Removal : -0.459 + Capture Clock Delay : 5.996 + Launch Clock Delay : 5.499 + Clock Pessimism Removal : -0.461 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -5803,15 +6184,15 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim PLL_158_55/CLK_OUT0 td 0.100 2.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 1.059 3.847 rd3_clk USCM_84_108/CLK_USCM td 0.000 3.847 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 1.531 5.378 ntclkbufg_1 - CLMS_134_93/CLK r image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK + net (fanout=2516) 1.652 5.499 ntclkbufg_1 + CLMS_98_321/CLK r image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK - CLMS_134_93/Q0 tco 0.222 5.600 f image_filiter_inst/multiline_buffer_inst/srst/opit_0/Q - net (fanout=37) 0.347 5.947 image_filiter_inst/multiline_buffer_inst/srst - DRM_142_88/RSTB[0] f image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0] + CLMS_98_321/Q0 tco 0.222 5.721 f image_filiter_inst/multiline_buffer_inst/srst/opit_0/Q + net (fanout=40) 0.402 6.123 image_filiter_inst/multiline_buffer_inst/srst + DRM_82_316/RSTB[0] f image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0] - Data arrival time 5.947 Logic Levels: 0 - Logic: 0.222ns(39.016%), Route: 0.347ns(60.984%) + Data arrival time 6.123 Logic Levels: 0 + Logic: 0.222ns(35.577%), Route: 0.402ns(64.423%) ---------------------------------------------------------------------------------------------------- Clock clk_50m (rising edge) 0.000 0.000 r @@ -5824,32 +6205,32 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 1.078 4.288 rd3_clk USCM_84_108/CLK_USCM td 0.000 4.288 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 1.585 5.873 ntclkbufg_1 - DRM_142_88/CLKB[0] r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] - clock pessimism -0.459 5.414 - clock uncertainty 0.000 5.414 + net (fanout=2516) 1.708 5.996 ntclkbufg_1 + DRM_82_316/CLKB[0] r image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] + clock pessimism -0.461 5.535 + clock uncertainty 0.000 5.535 - Removal time -0.022 5.392 + Removal time -0.022 5.513 - Data required time 5.392 + Data required time 5.513 ---------------------------------------------------------------------------------------------------- - Data required time 5.392 - Data arrival time 5.947 + Data required time 5.513 + Data arrival time 6.123 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.555 + Slack (MET) 0.610 ==================================================================================================== ==================================================================================================== Startpoint : image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK -Endpoint : image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTA[0] +Endpoint : image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/RS Path Group : clk_50m Path Type : min (slow corner) Path Class : async timing path Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.873 - Launch Clock Delay : 5.378 - Clock Pessimism Removal : -0.459 + Capture Clock Delay : 5.996 + Launch Clock Delay : 5.499 + Clock Pessimism Removal : -0.461 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -5864,15 +6245,17 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim PLL_158_55/CLK_OUT0 td 0.100 2.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 1.059 3.847 rd3_clk USCM_84_108/CLK_USCM td 0.000 3.847 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 1.531 5.378 ntclkbufg_1 - CLMS_134_93/CLK r image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK + net (fanout=2516) 1.652 5.499 ntclkbufg_1 + CLMS_98_321/CLK r image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK - CLMS_134_93/Q0 tco 0.222 5.600 f image_filiter_inst/multiline_buffer_inst/srst/opit_0/Q - net (fanout=37) 0.347 5.947 image_filiter_inst/multiline_buffer_inst/srst - DRM_142_88/RSTA[0] f image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTA[0] + CLMS_98_321/Q0 tco 0.222 5.721 f image_filiter_inst/multiline_buffer_inst/srst/opit_0/Q + net (fanout=40) 0.318 6.039 image_filiter_inst/multiline_buffer_inst/srst + CLMS_102_325/RSCO td 0.115 6.154 f image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/RSOUT + net (fanout=2) 0.000 6.154 ntR19 + CLMS_102_329/RSCI f image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/RS - Data arrival time 5.947 Logic Levels: 0 - Logic: 0.222ns(39.016%), Route: 0.347ns(60.984%) + Data arrival time 6.154 Logic Levels: 1 + Logic: 0.337ns(51.450%), Route: 0.318ns(48.550%) ---------------------------------------------------------------------------------------------------- Clock clk_50m (rising edge) 0.000 0.000 r @@ -5885,32 +6268,32 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 1.078 4.288 rd3_clk USCM_84_108/CLK_USCM td 0.000 4.288 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 1.585 5.873 ntclkbufg_1 - DRM_142_88/CLKA[0] r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] - clock pessimism -0.459 5.414 - clock uncertainty 0.000 5.414 + net (fanout=2516) 1.708 5.996 ntclkbufg_1 + CLMS_102_329/CLK r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK + clock pessimism -0.461 5.535 + clock uncertainty 0.000 5.535 - Removal time -0.046 5.368 + Removal time 0.000 5.535 - Data required time 5.368 + Data required time 5.535 ---------------------------------------------------------------------------------------------------- - Data required time 5.368 - Data arrival time 5.947 + Data required time 5.535 + Data arrival time 6.154 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.579 + Slack (MET) 0.619 ==================================================================================================== ==================================================================================================== Startpoint : image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK -Endpoint : image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/RS +Endpoint : image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/RS Path Group : clk_50m Path Type : min (slow corner) Path Class : async timing path Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.873 - Launch Clock Delay : 5.378 - Clock Pessimism Removal : -0.459 + Capture Clock Delay : 5.996 + Launch Clock Delay : 5.499 + Clock Pessimism Removal : -0.461 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -5925,17 +6308,17 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim PLL_158_55/CLK_OUT0 td 0.100 2.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 1.059 3.847 rd3_clk USCM_84_108/CLK_USCM td 0.000 3.847 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 1.531 5.378 ntclkbufg_1 - CLMS_134_93/CLK r image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK + net (fanout=2516) 1.652 5.499 ntclkbufg_1 + CLMS_98_321/CLK r image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK - CLMS_134_93/Q0 tco 0.226 5.604 r image_filiter_inst/multiline_buffer_inst/srst/opit_0/Q - net (fanout=37) 0.465 6.069 image_filiter_inst/multiline_buffer_inst/srst - CLMA_138_81/RSCO td 0.105 6.174 r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/RSOUT - net (fanout=2) 0.000 6.174 ntR38 - CLMA_138_85/RSCI r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/RS + CLMS_98_321/Q0 tco 0.222 5.721 f image_filiter_inst/multiline_buffer_inst/srst/opit_0/Q + net (fanout=40) 0.318 6.039 image_filiter_inst/multiline_buffer_inst/srst + CLMS_102_325/RSCO td 0.115 6.154 f image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/RSOUT + net (fanout=2) 0.000 6.154 ntR19 + CLMS_102_329/RSCI f image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/RS - Data arrival time 6.174 Logic Levels: 1 - Logic: 0.331ns(41.583%), Route: 0.465ns(58.417%) + Data arrival time 6.154 Logic Levels: 1 + Logic: 0.337ns(51.450%), Route: 0.318ns(48.550%) ---------------------------------------------------------------------------------------------------- Clock clk_50m (rising edge) 0.000 0.000 r @@ -5948,31 +6331,31 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 1.078 4.288 rd3_clk USCM_84_108/CLK_USCM td 0.000 4.288 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 1.585 5.873 ntclkbufg_1 - CLMA_138_85/CLK r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK - clock pessimism -0.459 5.414 - clock uncertainty 0.000 5.414 + net (fanout=2516) 1.708 5.996 ntclkbufg_1 + CLMS_102_329/CLK r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK + clock pessimism -0.461 5.535 + clock uncertainty 0.000 5.535 - Removal time 0.000 5.414 + Removal time 0.000 5.535 - Data required time 5.414 + Data required time 5.535 ---------------------------------------------------------------------------------------------------- - Data required time 5.414 - Data arrival time 6.174 + Data required time 5.535 + Data arrival time 6.154 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.760 + Slack (MET) 0.619 ==================================================================================================== ==================================================================================================== Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK -Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d1/opit_0_inv/RS +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_dqs_rst/opit_0_inv/RS Path Group : clk_200m Path Type : max (slow corner) Path Class : async timing path -Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) +Clock Skew : -0.177 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) Capture Clock Delay : 5.374 - Launch Clock Delay : 5.867 + Launch Clock Delay : 5.990 Clock Pessimism Removal : 0.439 Location Delay Type Incr Path Logical Resource @@ -5986,17 +6369,17 @@ Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessi IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.078 4.282 zoom_clk + net (fanout=2) 1.078 4.282 ddr_clk USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.585 5.867 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - CLMA_202_148/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK + net (fanout=71) 1.708 5.990 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + CLMA_174_252/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK - CLMA_202_148/Q1 tco 0.289 6.156 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/Q - net (fanout=686) 2.787 8.943 u_axi_ddr_top/I_ipsxb_ddr_top/ddr_rstn - CLMS_10_193/RS f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d1/opit_0_inv/RS + CLMA_174_252/Q1 tco 0.289 6.279 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/Q + net (fanout=687) 2.618 8.897 u_axi_ddr_top/I_ipsxb_ddr_top/ddr_rstn + CLMS_10_193/RS f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_dqs_rst/opit_0_inv/RS - Data arrival time 8.943 Logic Levels: 0 - Logic: 0.289ns(9.395%), Route: 2.787ns(90.605%) + Data arrival time 8.897 Logic Levels: 0 + Logic: 0.289ns(9.942%), Route: 2.618ns(90.058%) ---------------------------------------------------------------------------------------------------- Clock clk_200m (rising edge) 5.000 5.000 r @@ -6007,10 +6390,10 @@ Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessi IOL_327_210/INCK td 0.048 6.930 r clk_ibuf/opit_1/INCK net (fanout=1) 0.758 7.688 _N69 PLL_158_55/CLK_OUT1 td 0.096 7.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.059 8.843 zoom_clk + net (fanout=2) 1.059 8.843 ddr_clk USCM_84_113/CLK_USCM td 0.000 8.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.531 10.374 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - CLMS_10_193/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d1/opit_0_inv/CLK + net (fanout=71) 1.531 10.374 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + CLMS_10_193/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_dqs_rst/opit_0_inv/CLK clock pessimism 0.439 10.813 clock uncertainty -0.150 10.663 @@ -6019,21 +6402,21 @@ Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessi Data required time 10.046 ---------------------------------------------------------------------------------------------------- Data required time 10.046 - Data arrival time 8.943 + Data arrival time 8.897 ---------------------------------------------------------------------------------------------------- - Slack (MET) 1.103 + Slack (MET) 1.149 ==================================================================================================== ==================================================================================================== Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK -Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d2/opit_0_inv/RS +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d1/opit_0_inv/RS Path Group : clk_200m Path Type : max (slow corner) Path Class : async timing path -Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) +Clock Skew : -0.177 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) Capture Clock Delay : 5.374 - Launch Clock Delay : 5.867 + Launch Clock Delay : 5.990 Clock Pessimism Removal : 0.439 Location Delay Type Incr Path Logical Resource @@ -6047,17 +6430,17 @@ Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessi IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.078 4.282 zoom_clk + net (fanout=2) 1.078 4.282 ddr_clk USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.585 5.867 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - CLMA_202_148/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK + net (fanout=71) 1.708 5.990 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + CLMA_174_252/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK - CLMA_202_148/Q1 tco 0.289 6.156 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/Q - net (fanout=686) 2.787 8.943 u_axi_ddr_top/I_ipsxb_ddr_top/ddr_rstn - CLMS_10_193/RS f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d2/opit_0_inv/RS + CLMA_174_252/Q1 tco 0.289 6.279 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/Q + net (fanout=687) 2.274 8.553 u_axi_ddr_top/I_ipsxb_ddr_top/ddr_rstn + CLMA_30_184/RS f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d1/opit_0_inv/RS - Data arrival time 8.943 Logic Levels: 0 - Logic: 0.289ns(9.395%), Route: 2.787ns(90.605%) + Data arrival time 8.553 Logic Levels: 0 + Logic: 0.289ns(11.276%), Route: 2.274ns(88.724%) ---------------------------------------------------------------------------------------------------- Clock clk_200m (rising edge) 5.000 5.000 r @@ -6068,10 +6451,10 @@ Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessi IOL_327_210/INCK td 0.048 6.930 r clk_ibuf/opit_1/INCK net (fanout=1) 0.758 7.688 _N69 PLL_158_55/CLK_OUT1 td 0.096 7.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.059 8.843 zoom_clk + net (fanout=2) 1.059 8.843 ddr_clk USCM_84_113/CLK_USCM td 0.000 8.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.531 10.374 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - CLMS_10_193/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d2/opit_0_inv/CLK + net (fanout=71) 1.531 10.374 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + CLMA_30_184/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d1/opit_0_inv/CLK clock pessimism 0.439 10.813 clock uncertainty -0.150 10.663 @@ -6080,21 +6463,21 @@ Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessi Data required time 10.046 ---------------------------------------------------------------------------------------------------- Data required time 10.046 - Data arrival time 8.943 + Data arrival time 8.553 ---------------------------------------------------------------------------------------------------- - Slack (MET) 1.103 + Slack (MET) 1.493 ==================================================================================================== ==================================================================================================== -Startpoint : u_zoom_rst/rst/opit_0_L5Q_perm/CLK -Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[8].U_GTP_DRM18K/iGopDrm/RSTA[0] +Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d2/opit_0_inv/RS Path Group : clk_200m Path Type : max (slow corner) Path Class : async timing path -Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.495 - Launch Clock Delay : 5.867 +Clock Skew : -0.177 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 5.374 + Launch Clock Delay : 5.990 Clock Pessimism Removal : 0.439 Location Delay Type Incr Path Logical Resource @@ -6108,17 +6491,17 @@ Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.078 4.282 zoom_clk - USCM_84_122/CLK_USCM td 0.000 4.282 r USCMROUTE_2/CLKOUT - net (fanout=759) 1.585 5.867 ntR3909 - CLMS_186_125/CLK r u_zoom_rst/rst/opit_0_L5Q_perm/CLK + net (fanout=2) 1.078 4.282 ddr_clk + USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + net (fanout=71) 1.708 5.990 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + CLMA_174_252/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK - CLMS_186_125/Q0 tco 0.287 6.154 f u_zoom_rst/rst/opit_0_L5Q_perm/Q - net (fanout=131) 3.324 9.478 zoom_rst - DRM_278_356/RSTA[0] f u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[8].U_GTP_DRM18K/iGopDrm/RSTA[0] + CLMA_174_252/Q1 tco 0.289 6.279 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/Q + net (fanout=687) 2.274 8.553 u_axi_ddr_top/I_ipsxb_ddr_top/ddr_rstn + CLMA_30_184/RS f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d2/opit_0_inv/RS - Data arrival time 9.478 Logic Levels: 0 - Logic: 0.287ns(7.948%), Route: 3.324ns(92.052%) + Data arrival time 8.553 Logic Levels: 0 + Logic: 0.289ns(11.276%), Route: 2.274ns(88.724%) ---------------------------------------------------------------------------------------------------- Clock clk_200m (rising edge) 5.000 5.000 r @@ -6129,21 +6512,21 @@ Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.048 6.930 r clk_ibuf/opit_1/INCK net (fanout=1) 0.758 7.688 _N69 PLL_158_55/CLK_OUT1 td 0.096 7.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.059 8.843 zoom_clk - USCM_84_122/CLK_USCM td 0.000 8.843 r USCMROUTE_2/CLKOUT - net (fanout=759) 1.652 10.495 ntR3909 - DRM_278_356/CLKA[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[8].U_GTP_DRM18K/iGopDrm/CLKA[0] - clock pessimism 0.439 10.934 - clock uncertainty -0.150 10.784 + net (fanout=2) 1.059 8.843 ddr_clk + USCM_84_113/CLK_USCM td 0.000 8.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + net (fanout=71) 1.531 10.374 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + CLMA_30_184/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d2/opit_0_inv/CLK + clock pessimism 0.439 10.813 + clock uncertainty -0.150 10.663 - Recovery time -0.115 10.669 + Recovery time -0.617 10.046 - Data required time 10.669 + Data required time 10.046 ---------------------------------------------------------------------------------------------------- - Data required time 10.669 - Data arrival time 9.478 + Data required time 10.046 + Data arrival time 8.553 ---------------------------------------------------------------------------------------------------- - Slack (MET) 1.191 + Slack (MET) 1.493 ==================================================================================================== ==================================================================================================== @@ -6153,9 +6536,9 @@ Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/opi Path Group : clk_200m Path Type : min (slow corner) Path Class : async timing path -Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.867 - Launch Clock Delay : 5.374 +Clock Skew : 0.069 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 5.990 + Launch Clock Delay : 5.495 Clock Pessimism Removal : -0.426 Location Delay Type Incr Path Logical Resource @@ -6169,17 +6552,17 @@ Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK net (fanout=1) 0.758 2.688 _N69 PLL_158_55/CLK_OUT1 td 0.096 2.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.059 3.843 zoom_clk - USCM_84_122/CLK_USCM td 0.000 3.843 r USCMROUTE_2/CLKOUT - net (fanout=759) 1.531 5.374 ntR3909 - CLMS_202_149/CLK r u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK + net (fanout=2) 1.059 3.843 ddr_clk + USCM_84_153/CLK_USCM td 0.000 3.843 r USCMROUTE_2/CLKOUT + net (fanout=6) 1.652 5.495 ntR3952 + CLMS_174_253/CLK r u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK - CLMS_202_149/Q0 tco 0.222 5.596 f u_ddr_rst/rst/opit_0_inv_L5Q_perm/Q - net (fanout=2) 0.179 5.775 ddr_rst - CLMA_202_148/RS f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/opit_0/RS + CLMS_174_253/Q0 tco 0.222 5.717 f u_ddr_rst/rst/opit_0_inv_L5Q_perm/Q + net (fanout=2) 0.182 5.899 ddr_rst + CLMA_174_252/RS f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/opit_0/RS - Data arrival time 5.775 Logic Levels: 0 - Logic: 0.222ns(55.362%), Route: 0.179ns(44.638%) + Data arrival time 5.899 Logic Levels: 0 + Logic: 0.222ns(54.950%), Route: 0.182ns(45.050%) ---------------------------------------------------------------------------------------------------- Clock clk_200m (rising edge) 0.000 0.000 r @@ -6190,21 +6573,21 @@ Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.078 4.282 zoom_clk + net (fanout=2) 1.078 4.282 ddr_clk USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.585 5.867 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - CLMA_202_148/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/opit_0/CLK - clock pessimism -0.426 5.441 - clock uncertainty 0.000 5.441 + net (fanout=71) 1.708 5.990 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + CLMA_174_252/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/opit_0/CLK + clock pessimism -0.426 5.564 + clock uncertainty 0.000 5.564 - Removal time -0.220 5.221 + Removal time -0.220 5.344 - Data required time 5.221 + Data required time 5.344 ---------------------------------------------------------------------------------------------------- - Data required time 5.221 - Data arrival time 5.775 + Data required time 5.344 + Data arrival time 5.899 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.554 + Slack (MET) 0.555 ==================================================================================================== ==================================================================================================== @@ -6214,9 +6597,9 @@ Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opi Path Group : clk_200m Path Type : min (slow corner) Path Class : async timing path -Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.867 - Launch Clock Delay : 5.374 +Clock Skew : 0.069 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 5.990 + Launch Clock Delay : 5.495 Clock Pessimism Removal : -0.426 Location Delay Type Incr Path Logical Resource @@ -6230,17 +6613,17 @@ Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK net (fanout=1) 0.758 2.688 _N69 PLL_158_55/CLK_OUT1 td 0.096 2.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.059 3.843 zoom_clk - USCM_84_122/CLK_USCM td 0.000 3.843 r USCMROUTE_2/CLKOUT - net (fanout=759) 1.531 5.374 ntR3909 - CLMS_202_149/CLK r u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK + net (fanout=2) 1.059 3.843 ddr_clk + USCM_84_153/CLK_USCM td 0.000 3.843 r USCMROUTE_2/CLKOUT + net (fanout=6) 1.652 5.495 ntR3952 + CLMS_174_253/CLK r u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK - CLMS_202_149/Q0 tco 0.222 5.596 f u_ddr_rst/rst/opit_0_inv_L5Q_perm/Q - net (fanout=2) 0.179 5.775 ddr_rst - CLMA_202_148/RS f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/RS + CLMS_174_253/Q0 tco 0.222 5.717 f u_ddr_rst/rst/opit_0_inv_L5Q_perm/Q + net (fanout=2) 0.182 5.899 ddr_rst + CLMA_174_252/RS f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/RS - Data arrival time 5.775 Logic Levels: 0 - Logic: 0.222ns(55.362%), Route: 0.179ns(44.638%) + Data arrival time 5.899 Logic Levels: 0 + Logic: 0.222ns(54.950%), Route: 0.182ns(45.050%) ---------------------------------------------------------------------------------------------------- Clock clk_200m (rising edge) 0.000 0.000 r @@ -6251,27 +6634,27 @@ Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.078 4.282 zoom_clk + net (fanout=2) 1.078 4.282 ddr_clk USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.585 5.867 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - CLMA_202_148/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK - clock pessimism -0.426 5.441 - clock uncertainty 0.000 5.441 + net (fanout=71) 1.708 5.990 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + CLMA_174_252/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK + clock pessimism -0.426 5.564 + clock uncertainty 0.000 5.564 - Removal time -0.220 5.221 + Removal time -0.220 5.344 - Data required time 5.221 + Data required time 5.344 ---------------------------------------------------------------------------------------------------- - Data required time 5.221 - Data arrival time 5.775 + Data required time 5.344 + Data arrival time 5.899 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.554 + Slack (MET) 0.555 ==================================================================================================== ==================================================================================================== -Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q_perm/CLK -Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[0]/opit_0_inv/RS +Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q/CLK +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/training_error_d[1]/opit_0_inv/RS Path Group : clk_200m Path Type : min (slow corner) Path Class : async timing path @@ -6291,19 +6674,17 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK net (fanout=1) 0.758 2.688 _N69 PLL_158_55/CLK_OUT1 td 0.096 2.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.059 3.843 zoom_clk + net (fanout=2) 1.059 3.843 ddr_clk USCM_84_113/CLK_USCM td 0.000 3.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.531 5.374 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - CLMS_78_181/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q_perm/CLK + net (fanout=71) 1.531 5.374 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + CLMA_58_184/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q/CLK - CLMS_78_181/Q0 tco 0.222 5.596 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q_perm/Q - net (fanout=14) 0.443 6.039 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/logic_rstn - CLMS_62_181/RSCO td 0.105 6.144 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/pll_lock_d[1]/opit_0_inv/RSOUT - net (fanout=4) 0.000 6.144 ntR1581 - CLMS_62_185/RSCI r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[0]/opit_0_inv/RS + CLMA_58_184/Q0 tco 0.222 5.596 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q/Q + net (fanout=22) 0.485 6.081 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/logic_rstn + CLMA_50_196/RS f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/training_error_d[1]/opit_0_inv/RS - Data arrival time 6.144 Logic Levels: 1 - Logic: 0.327ns(42.468%), Route: 0.443ns(57.532%) + Data arrival time 6.081 Logic Levels: 0 + Logic: 0.222ns(31.400%), Route: 0.485ns(68.600%) ---------------------------------------------------------------------------------------------------- Clock clk_200m (rising edge) 0.000 0.000 r @@ -6314,21 +6695,21 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.078 4.282 zoom_clk + net (fanout=2) 1.078 4.282 ddr_clk USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.585 5.867 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - CLMS_62_185/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[0]/opit_0_inv/CLK + net (fanout=71) 1.585 5.867 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + CLMA_50_196/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/training_error_d[1]/opit_0_inv/CLK clock pessimism -0.457 5.410 clock uncertainty 0.000 5.410 - Removal time 0.000 5.410 + Removal time -0.220 5.190 - Data required time 5.410 + Data required time 5.190 ---------------------------------------------------------------------------------------------------- - Data required time 5.410 - Data arrival time 6.144 + Data required time 5.190 + Data arrival time 6.081 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.734 + Slack (MET) 0.891 ==================================================================================================== ==================================================================================================== @@ -6338,10 +6719,10 @@ Endpoint : ms72xx_ctl/rstn_temp1/opit_0_inv/RS Path Group : clk_10m Path Type : max (slow corner) Path Class : async timing path -Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.378 +Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 5.499 Launch Clock Delay : 5.873 - Clock Pessimism Removal : 0.459 + Clock Pessimism Removal : 0.441 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -6355,16 +6736,16 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT4 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 net (fanout=1) 1.078 4.288 clk_10m - USCM_84_110/CLK_USCM td 0.000 4.288 r clkbufg_3/gopclkbufg/CLKOUT - net (fanout=235) 1.585 5.873 ntclkbufg_3 - CLMA_230_69/CLK r rstn_out1/opit_0_inv/CLK + USCM_84_110/CLK_USCM td 0.000 4.288 r clkbufg_4/gopclkbufg/CLKOUT + net (fanout=235) 1.585 5.873 ntclkbufg_4 + CLMS_270_193/CLK r rstn_out1/opit_0_inv/CLK - CLMA_230_69/Q3 tco 0.286 6.159 f rstn_out1/opit_0_inv/Q - net (fanout=3) 1.118 7.277 nt_eth_rstn - CLMA_246_120/RS f ms72xx_ctl/rstn_temp1/opit_0_inv/RS + CLMS_270_193/Q3 tco 0.286 6.159 f rstn_out1/opit_0_inv/Q + net (fanout=3) 1.217 7.376 nt_eth_rstn + CLMA_262_268/RS f ms72xx_ctl/rstn_temp1/opit_0_inv/RS - Data arrival time 7.277 Logic Levels: 0 - Logic: 0.286ns(20.370%), Route: 1.118ns(79.630%) + Data arrival time 7.376 Logic Levels: 0 + Logic: 0.286ns(19.029%), Route: 1.217ns(80.971%) ---------------------------------------------------------------------------------------------------- Clock clk_10m (rising edge) 100.000 100.000 r @@ -6376,20 +6757,20 @@ Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessi net (fanout=1) 0.758 102.688 _N69 PLL_158_55/CLK_OUT4 td 0.100 102.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 net (fanout=1) 1.059 103.847 clk_10m - USCM_84_110/CLK_USCM td 0.000 103.847 r clkbufg_3/gopclkbufg/CLKOUT - net (fanout=235) 1.531 105.378 ntclkbufg_3 - CLMA_246_120/CLK r ms72xx_ctl/rstn_temp1/opit_0_inv/CLK - clock pessimism 0.459 105.837 - clock uncertainty -0.150 105.687 + USCM_84_110/CLK_USCM td 0.000 103.847 r clkbufg_4/gopclkbufg/CLKOUT + net (fanout=235) 1.652 105.499 ntclkbufg_4 + CLMA_262_268/CLK r ms72xx_ctl/rstn_temp1/opit_0_inv/CLK + clock pessimism 0.441 105.940 + clock uncertainty -0.150 105.790 - Recovery time -0.617 105.070 + Recovery time -0.617 105.173 - Data required time 105.070 + Data required time 105.173 ---------------------------------------------------------------------------------------------------- - Data required time 105.070 - Data arrival time 7.277 + Data required time 105.173 + Data arrival time 7.376 ---------------------------------------------------------------------------------------------------- - Slack (MET) 97.793 + Slack (MET) 97.797 ==================================================================================================== ==================================================================================================== @@ -6399,10 +6780,10 @@ Endpoint : ms72xx_ctl/rstn_temp1/opit_0_inv/RS Path Group : clk_10m Path Type : min (slow corner) Path Class : async timing path -Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.873 +Clock Skew : 0.177 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 5.996 Launch Clock Delay : 5.378 - Clock Pessimism Removal : -0.459 + Clock Pessimism Removal : -0.441 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -6416,16 +6797,16 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.758 2.688 _N69 PLL_158_55/CLK_OUT4 td 0.100 2.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 net (fanout=1) 1.059 3.847 clk_10m - USCM_84_110/CLK_USCM td 0.000 3.847 r clkbufg_3/gopclkbufg/CLKOUT - net (fanout=235) 1.531 5.378 ntclkbufg_3 - CLMA_230_69/CLK r rstn_out1/opit_0_inv/CLK + USCM_84_110/CLK_USCM td 0.000 3.847 r clkbufg_4/gopclkbufg/CLKOUT + net (fanout=235) 1.531 5.378 ntclkbufg_4 + CLMS_270_193/CLK r rstn_out1/opit_0_inv/CLK - CLMA_230_69/Q3 tco 0.226 5.604 r rstn_out1/opit_0_inv/Q - net (fanout=3) 0.896 6.500 nt_eth_rstn - CLMA_246_120/RS r ms72xx_ctl/rstn_temp1/opit_0_inv/RS + CLMS_270_193/Q3 tco 0.226 5.604 r rstn_out1/opit_0_inv/Q + net (fanout=3) 0.988 6.592 nt_eth_rstn + CLMA_262_268/RS r ms72xx_ctl/rstn_temp1/opit_0_inv/RS - Data arrival time 6.500 Logic Levels: 0 - Logic: 0.226ns(20.143%), Route: 0.896ns(79.857%) + Data arrival time 6.592 Logic Levels: 0 + Logic: 0.226ns(18.616%), Route: 0.988ns(81.384%) ---------------------------------------------------------------------------------------------------- Clock clk_10m (rising edge) 0.000 0.000 r @@ -6437,38 +6818,38 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT4 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 net (fanout=1) 1.078 4.288 clk_10m - USCM_84_110/CLK_USCM td 0.000 4.288 r clkbufg_3/gopclkbufg/CLKOUT - net (fanout=235) 1.585 5.873 ntclkbufg_3 - CLMA_246_120/CLK r ms72xx_ctl/rstn_temp1/opit_0_inv/CLK - clock pessimism -0.459 5.414 - clock uncertainty 0.000 5.414 + USCM_84_110/CLK_USCM td 0.000 4.288 r clkbufg_4/gopclkbufg/CLKOUT + net (fanout=235) 1.708 5.996 ntclkbufg_4 + CLMA_262_268/CLK r ms72xx_ctl/rstn_temp1/opit_0_inv/CLK + clock pessimism -0.441 5.555 + clock uncertainty 0.000 5.555 - Removal time -0.226 5.188 + Removal time -0.226 5.329 - Data required time 5.188 + Data required time 5.329 ---------------------------------------------------------------------------------------------------- - Data required time 5.188 - Data arrival time 6.500 + Data required time 5.329 + Data arrival time 6.592 ---------------------------------------------------------------------------------------------------- - Slack (MET) 1.312 + Slack (MET) 1.263 ==================================================================================================== ==================================================================================================== -Startpoint : sync_vg_100m/opit_0_inv_L5Q_perm/CLK -Endpoint : adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[4]/opit_0_L5Q_perm/RS -Path Group : clk_720p60Hz +Startpoint : u_zoom_rst/rst/opit_0_L5Q_perm/CLK +Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/RSTA[0] +Path Group : clk_1080p60Hz Path Type : max (slow corner) Path Class : async timing path -Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 8.831 - Launch Clock Delay : 9.434 - Clock Pessimism Removal : 0.549 +Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 8.956 + Launch Clock Delay : 9.440 + Clock Pessimism Removal : 0.551 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_720p60Hz (rising edge) 0.000 0.000 r + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 2.166 2.240 r clk_ibuf/opit_0/O @@ -6478,86 +6859,66 @@ Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessi PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 1.078 4.288 rd3_clk USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.861 6.149 ntR3907 - PLL_158_303/CLK_OUT1 td 0.101 6.250 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.599 7.849 nt_pix_clk - USCM_84_117/CLK_USCM td 0.000 7.849 r clkbufg_2/gopclkbufg/CLKOUT - net (fanout=1635) 1.585 9.434 ntclkbufg_2 - CLMS_150_245/CLK r sync_vg_100m/opit_0_inv_L5Q_perm/CLK - - CLMS_150_245/Q0 tco 0.287 9.721 f sync_vg_100m/opit_0_inv_L5Q_perm/Q - net (fanout=1066) 2.932 12.653 sync_vg_100m - CLMA_294_132/RSCO td 0.147 12.800 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/remainder[3]/opit_0_L5Q_perm/RSOUT - net (fanout=4) 0.000 12.800 ntR491 - CLMA_294_136/RSCO td 0.147 12.947 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm/RSOUT - net (fanout=4) 0.000 12.947 ntR490 - CLMA_294_140/RSCO td 0.147 13.094 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[2]/opit_0_L5Q_perm/RSOUT - net (fanout=1) 0.000 13.094 ntR489 - CLMA_294_144/RSCO td 0.147 13.241 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/remainder[2]/opit_0_A2Q21/RSOUT - net (fanout=2) 0.000 13.241 ntR488 - CLMA_294_148/RSCO td 0.147 13.388 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/remainder[6]/opit_0_A2Q21/RSOUT - net (fanout=4) 0.000 13.388 ntR487 - CLMA_294_152/RSCO td 0.147 13.535 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm/RSOUT - net (fanout=4) 0.000 13.535 ntR486 - CLMA_294_156/RSCO td 0.147 13.682 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/dividend_kp[11]/opit_0_L5Q_perm/RSOUT - net (fanout=4) 0.000 13.682 ntR485 - CLMA_294_160/RSCO td 0.147 13.829 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[2]/opit_0_L5Q_perm/RSOUT - net (fanout=2) 0.000 13.829 ntR484 - CLMA_294_164/RSCO td 0.147 13.976 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[2]/opit_0_A2Q21/RSOUT - net (fanout=2) 0.000 13.976 ntR483 - CLMA_294_168/RSCO td 0.147 14.123 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[6]/opit_0_A2Q21/RSOUT - net (fanout=4) 0.000 14.123 ntR482 - CLMA_294_172/RSCI f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[4]/opit_0_L5Q_perm/RS - - Data arrival time 14.123 Logic Levels: 10 - Logic: 1.757ns(37.471%), Route: 2.932ns(62.529%) + net (fanout=1) 1.861 6.149 ntR3950 + PLL_158_303/CLK_OUT0 td 0.107 6.256 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 1.599 7.855 zoom_clk + USCM_84_118/CLK_USCM td 0.000 7.855 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 1.585 9.440 ntclkbufg_3 + CLMA_170_124/CLK r u_zoom_rst/rst/opit_0_L5Q_perm/CLK + + CLMA_170_124/Q0 tco 0.287 9.727 f u_zoom_rst/rst/opit_0_L5Q_perm/Q + net (fanout=114) 2.983 12.710 zoom_rst + DRM_306_252/RSTA[0] f u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/RSTA[0] + + Data arrival time 12.710 Logic Levels: 0 + Logic: 0.287ns(8.777%), Route: 2.983ns(91.223%) ---------------------------------------------------------------------------------------------------- - Clock clk_720p60Hz (rising edge) 13.473 13.473 r - P20 0.000 13.473 r clk (port) - net (fanout=1) 0.074 13.547 clk - IOBS_LR_328_209/DIN td 1.808 15.355 r clk_ibuf/opit_0/O - net (fanout=1) 0.000 15.355 clk_ibuf/ntD - IOL_327_210/INCK td 0.048 15.403 r clk_ibuf/opit_1/INCK - net (fanout=1) 0.758 16.161 _N69 - PLL_158_55/CLK_OUT0 td 0.100 16.261 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 - net (fanout=2) 1.059 17.320 rd3_clk - USCM_84_154/CLK_USCM td 0.000 17.320 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.786 19.106 ntR3907 - PLL_158_303/CLK_OUT1 td 0.096 19.202 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.571 20.773 nt_pix_clk - USCM_84_117/CLK_USCM td 0.000 20.773 r clkbufg_2/gopclkbufg/CLKOUT - net (fanout=1635) 1.531 22.304 ntclkbufg_2 - CLMA_294_172/CLK r adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[4]/opit_0_L5Q_perm/CLK - clock pessimism 0.549 22.853 - clock uncertainty -0.150 22.703 + Clock clk_1080p60Hz (rising edge) 6.736 6.736 r + P20 0.000 6.736 r clk (port) + net (fanout=1) 0.074 6.810 clk + IOBS_LR_328_209/DIN td 1.808 8.618 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 8.618 clk_ibuf/ntD + IOL_327_210/INCK td 0.048 8.666 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.758 9.424 _N69 + PLL_158_55/CLK_OUT0 td 0.100 9.524 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 1.059 10.583 rd3_clk + USCM_84_154/CLK_USCM td 0.000 10.583 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.786 12.369 ntR3950 + PLL_158_303/CLK_OUT0 td 0.100 12.469 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 1.571 14.040 zoom_clk + USCM_84_118/CLK_USCM td 0.000 14.040 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 1.652 15.692 ntclkbufg_3 + DRM_306_252/CLKA[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/CLKA[0] + clock pessimism 0.551 16.243 + clock uncertainty -0.150 16.093 - Recovery time 0.000 22.703 + Recovery time -0.115 15.978 - Data required time 22.703 + Data required time 15.978 ---------------------------------------------------------------------------------------------------- - Data required time 22.703 - Data arrival time 14.123 + Data required time 15.978 + Data arrival time 12.710 ---------------------------------------------------------------------------------------------------- - Slack (MET) 8.580 + Slack (MET) 3.268 ==================================================================================================== ==================================================================================================== -Startpoint : sync_vg_100m/opit_0_inv_L5Q_perm/CLK -Endpoint : adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[6]/opit_0_L5Q_perm/RS -Path Group : clk_720p60Hz +Startpoint : u_zoom_rst/rst/opit_0_L5Q_perm/CLK +Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/RSTA[0] +Path Group : clk_1080p60Hz Path Type : max (slow corner) Path Class : async timing path -Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 8.831 - Launch Clock Delay : 9.434 - Clock Pessimism Removal : 0.549 +Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 8.956 + Launch Clock Delay : 9.440 + Clock Pessimism Removal : 0.551 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_720p60Hz (rising edge) 0.000 0.000 r + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 2.166 2.240 r clk_ibuf/opit_0/O @@ -6567,86 +6928,66 @@ Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessi PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 1.078 4.288 rd3_clk USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.861 6.149 ntR3907 - PLL_158_303/CLK_OUT1 td 0.101 6.250 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.599 7.849 nt_pix_clk - USCM_84_117/CLK_USCM td 0.000 7.849 r clkbufg_2/gopclkbufg/CLKOUT - net (fanout=1635) 1.585 9.434 ntclkbufg_2 - CLMS_150_245/CLK r sync_vg_100m/opit_0_inv_L5Q_perm/CLK - - CLMS_150_245/Q0 tco 0.287 9.721 f sync_vg_100m/opit_0_inv_L5Q_perm/Q - net (fanout=1066) 2.932 12.653 sync_vg_100m - CLMA_294_132/RSCO td 0.147 12.800 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/remainder[3]/opit_0_L5Q_perm/RSOUT - net (fanout=4) 0.000 12.800 ntR491 - CLMA_294_136/RSCO td 0.147 12.947 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm/RSOUT - net (fanout=4) 0.000 12.947 ntR490 - CLMA_294_140/RSCO td 0.147 13.094 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[2]/opit_0_L5Q_perm/RSOUT - net (fanout=1) 0.000 13.094 ntR489 - CLMA_294_144/RSCO td 0.147 13.241 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/remainder[2]/opit_0_A2Q21/RSOUT - net (fanout=2) 0.000 13.241 ntR488 - CLMA_294_148/RSCO td 0.147 13.388 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/remainder[6]/opit_0_A2Q21/RSOUT - net (fanout=4) 0.000 13.388 ntR487 - CLMA_294_152/RSCO td 0.147 13.535 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm/RSOUT - net (fanout=4) 0.000 13.535 ntR486 - CLMA_294_156/RSCO td 0.147 13.682 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/dividend_kp[11]/opit_0_L5Q_perm/RSOUT - net (fanout=4) 0.000 13.682 ntR485 - CLMA_294_160/RSCO td 0.147 13.829 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[2]/opit_0_L5Q_perm/RSOUT - net (fanout=2) 0.000 13.829 ntR484 - CLMA_294_164/RSCO td 0.147 13.976 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[2]/opit_0_A2Q21/RSOUT - net (fanout=2) 0.000 13.976 ntR483 - CLMA_294_168/RSCO td 0.147 14.123 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[6]/opit_0_A2Q21/RSOUT - net (fanout=4) 0.000 14.123 ntR482 - CLMA_294_172/RSCI f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[6]/opit_0_L5Q_perm/RS - - Data arrival time 14.123 Logic Levels: 10 - Logic: 1.757ns(37.471%), Route: 2.932ns(62.529%) + net (fanout=1) 1.861 6.149 ntR3950 + PLL_158_303/CLK_OUT0 td 0.107 6.256 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 1.599 7.855 zoom_clk + USCM_84_118/CLK_USCM td 0.000 7.855 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 1.585 9.440 ntclkbufg_3 + CLMA_170_124/CLK r u_zoom_rst/rst/opit_0_L5Q_perm/CLK + + CLMA_170_124/Q0 tco 0.287 9.727 f u_zoom_rst/rst/opit_0_L5Q_perm/Q + net (fanout=114) 2.931 12.658 zoom_rst + DRM_306_292/RSTA[0] f u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/RSTA[0] + + Data arrival time 12.658 Logic Levels: 0 + Logic: 0.287ns(8.919%), Route: 2.931ns(91.081%) ---------------------------------------------------------------------------------------------------- - Clock clk_720p60Hz (rising edge) 13.473 13.473 r - P20 0.000 13.473 r clk (port) - net (fanout=1) 0.074 13.547 clk - IOBS_LR_328_209/DIN td 1.808 15.355 r clk_ibuf/opit_0/O - net (fanout=1) 0.000 15.355 clk_ibuf/ntD - IOL_327_210/INCK td 0.048 15.403 r clk_ibuf/opit_1/INCK - net (fanout=1) 0.758 16.161 _N69 - PLL_158_55/CLK_OUT0 td 0.100 16.261 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 - net (fanout=2) 1.059 17.320 rd3_clk - USCM_84_154/CLK_USCM td 0.000 17.320 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.786 19.106 ntR3907 - PLL_158_303/CLK_OUT1 td 0.096 19.202 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.571 20.773 nt_pix_clk - USCM_84_117/CLK_USCM td 0.000 20.773 r clkbufg_2/gopclkbufg/CLKOUT - net (fanout=1635) 1.531 22.304 ntclkbufg_2 - CLMA_294_172/CLK r adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[6]/opit_0_L5Q_perm/CLK - clock pessimism 0.549 22.853 - clock uncertainty -0.150 22.703 + Clock clk_1080p60Hz (rising edge) 6.736 6.736 r + P20 0.000 6.736 r clk (port) + net (fanout=1) 0.074 6.810 clk + IOBS_LR_328_209/DIN td 1.808 8.618 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 8.618 clk_ibuf/ntD + IOL_327_210/INCK td 0.048 8.666 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.758 9.424 _N69 + PLL_158_55/CLK_OUT0 td 0.100 9.524 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 1.059 10.583 rd3_clk + USCM_84_154/CLK_USCM td 0.000 10.583 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.786 12.369 ntR3950 + PLL_158_303/CLK_OUT0 td 0.100 12.469 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 1.571 14.040 zoom_clk + USCM_84_118/CLK_USCM td 0.000 14.040 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 1.652 15.692 ntclkbufg_3 + DRM_306_292/CLKA[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/CLKA[0] + clock pessimism 0.551 16.243 + clock uncertainty -0.150 16.093 - Recovery time 0.000 22.703 + Recovery time -0.115 15.978 - Data required time 22.703 + Data required time 15.978 ---------------------------------------------------------------------------------------------------- - Data required time 22.703 - Data arrival time 14.123 + Data required time 15.978 + Data arrival time 12.658 ---------------------------------------------------------------------------------------------------- - Slack (MET) 8.580 + Slack (MET) 3.320 ==================================================================================================== ==================================================================================================== -Startpoint : sync_vg_100m/opit_0_inv_L5Q_perm/CLK -Endpoint : adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[7]/opit_0_L5Q_perm/RS -Path Group : clk_720p60Hz +Startpoint : u_zoom_rst/rst/opit_0_L5Q_perm/CLK +Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[4].U_GTP_DRM18K/iGopDrm/RSTA[0] +Path Group : clk_1080p60Hz Path Type : max (slow corner) Path Class : async timing path -Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 8.831 - Launch Clock Delay : 9.434 - Clock Pessimism Removal : 0.549 +Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 8.956 + Launch Clock Delay : 9.440 + Clock Pessimism Removal : 0.551 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_720p60Hz (rising edge) 0.000 0.000 r + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 2.166 2.240 r clk_ibuf/opit_0/O @@ -6656,86 +6997,66 @@ Clock Skew : -0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessi PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 1.078 4.288 rd3_clk USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.861 6.149 ntR3907 - PLL_158_303/CLK_OUT1 td 0.101 6.250 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.599 7.849 nt_pix_clk - USCM_84_117/CLK_USCM td 0.000 7.849 r clkbufg_2/gopclkbufg/CLKOUT - net (fanout=1635) 1.585 9.434 ntclkbufg_2 - CLMS_150_245/CLK r sync_vg_100m/opit_0_inv_L5Q_perm/CLK - - CLMS_150_245/Q0 tco 0.287 9.721 f sync_vg_100m/opit_0_inv_L5Q_perm/Q - net (fanout=1066) 2.932 12.653 sync_vg_100m - CLMA_294_132/RSCO td 0.147 12.800 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/remainder[3]/opit_0_L5Q_perm/RSOUT - net (fanout=4) 0.000 12.800 ntR491 - CLMA_294_136/RSCO td 0.147 12.947 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm/RSOUT - net (fanout=4) 0.000 12.947 ntR490 - CLMA_294_140/RSCO td 0.147 13.094 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[2]/opit_0_L5Q_perm/RSOUT - net (fanout=1) 0.000 13.094 ntR489 - CLMA_294_144/RSCO td 0.147 13.241 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/remainder[2]/opit_0_A2Q21/RSOUT - net (fanout=2) 0.000 13.241 ntR488 - CLMA_294_148/RSCO td 0.147 13.388 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/remainder[6]/opit_0_A2Q21/RSOUT - net (fanout=4) 0.000 13.388 ntR487 - CLMA_294_152/RSCO td 0.147 13.535 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm/RSOUT - net (fanout=4) 0.000 13.535 ntR486 - CLMA_294_156/RSCO td 0.147 13.682 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/dividend_kp[11]/opit_0_L5Q_perm/RSOUT - net (fanout=4) 0.000 13.682 ntR485 - CLMA_294_160/RSCO td 0.147 13.829 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[2]/opit_0_L5Q_perm/RSOUT - net (fanout=2) 0.000 13.829 ntR484 - CLMA_294_164/RSCO td 0.147 13.976 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[2]/opit_0_A2Q21/RSOUT - net (fanout=2) 0.000 13.976 ntR483 - CLMA_294_168/RSCO td 0.147 14.123 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[6]/opit_0_A2Q21/RSOUT - net (fanout=4) 0.000 14.123 ntR482 - CLMA_294_172/RSCI f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[7]/opit_0_L5Q_perm/RS - - Data arrival time 14.123 Logic Levels: 10 - Logic: 1.757ns(37.471%), Route: 2.932ns(62.529%) + net (fanout=1) 1.861 6.149 ntR3950 + PLL_158_303/CLK_OUT0 td 0.107 6.256 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 1.599 7.855 zoom_clk + USCM_84_118/CLK_USCM td 0.000 7.855 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 1.585 9.440 ntclkbufg_3 + CLMA_170_124/CLK r u_zoom_rst/rst/opit_0_L5Q_perm/CLK + + CLMA_170_124/Q0 tco 0.287 9.727 f u_zoom_rst/rst/opit_0_L5Q_perm/Q + net (fanout=114) 2.828 12.555 zoom_rst + DRM_306_272/RSTA[0] f u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[4].U_GTP_DRM18K/iGopDrm/RSTA[0] + + Data arrival time 12.555 Logic Levels: 0 + Logic: 0.287ns(9.213%), Route: 2.828ns(90.787%) ---------------------------------------------------------------------------------------------------- - Clock clk_720p60Hz (rising edge) 13.473 13.473 r - P20 0.000 13.473 r clk (port) - net (fanout=1) 0.074 13.547 clk - IOBS_LR_328_209/DIN td 1.808 15.355 r clk_ibuf/opit_0/O - net (fanout=1) 0.000 15.355 clk_ibuf/ntD - IOL_327_210/INCK td 0.048 15.403 r clk_ibuf/opit_1/INCK - net (fanout=1) 0.758 16.161 _N69 - PLL_158_55/CLK_OUT0 td 0.100 16.261 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 - net (fanout=2) 1.059 17.320 rd3_clk - USCM_84_154/CLK_USCM td 0.000 17.320 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.786 19.106 ntR3907 - PLL_158_303/CLK_OUT1 td 0.096 19.202 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.571 20.773 nt_pix_clk - USCM_84_117/CLK_USCM td 0.000 20.773 r clkbufg_2/gopclkbufg/CLKOUT - net (fanout=1635) 1.531 22.304 ntclkbufg_2 - CLMA_294_172/CLK r adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[7]/opit_0_L5Q_perm/CLK - clock pessimism 0.549 22.853 - clock uncertainty -0.150 22.703 + Clock clk_1080p60Hz (rising edge) 6.736 6.736 r + P20 0.000 6.736 r clk (port) + net (fanout=1) 0.074 6.810 clk + IOBS_LR_328_209/DIN td 1.808 8.618 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 8.618 clk_ibuf/ntD + IOL_327_210/INCK td 0.048 8.666 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.758 9.424 _N69 + PLL_158_55/CLK_OUT0 td 0.100 9.524 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 1.059 10.583 rd3_clk + USCM_84_154/CLK_USCM td 0.000 10.583 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.786 12.369 ntR3950 + PLL_158_303/CLK_OUT0 td 0.100 12.469 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 1.571 14.040 zoom_clk + USCM_84_118/CLK_USCM td 0.000 14.040 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 1.652 15.692 ntclkbufg_3 + DRM_306_272/CLKA[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[4].U_GTP_DRM18K/iGopDrm/CLKA[0] + clock pessimism 0.551 16.243 + clock uncertainty -0.150 16.093 - Recovery time 0.000 22.703 + Recovery time -0.115 15.978 - Data required time 22.703 + Data required time 15.978 ---------------------------------------------------------------------------------------------------- - Data required time 22.703 - Data arrival time 14.123 + Data required time 15.978 + Data arrival time 12.555 ---------------------------------------------------------------------------------------------------- - Slack (MET) 8.580 + Slack (MET) 3.423 ==================================================================================================== ==================================================================================================== -Startpoint : u_hdmi_rst/rst/opit_0_L5Q_perm/CLK -Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[12].U_GTP_DRM18K/iGopDrm/RSTB[0] -Path Group : clk_720p60Hz +Startpoint : u_zoom_rst/rst/opit_0_L5Q_perm/CLK +Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[6].U_GTP_DRM18K/iGopDrm/RSTA[0] +Path Group : clk_1080p60Hz Path Type : min (slow corner) Path Class : async timing path -Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 9.434 - Launch Clock Delay : 8.831 - Clock Pessimism Removal : -0.567 +Clock Skew : 0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 9.440 + Launch Clock Delay : 8.835 + Clock Pessimism Removal : -0.551 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_720p60Hz (rising edge) 0.000 0.000 r + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.808 1.882 r clk_ibuf/opit_0/O @@ -6745,22 +7066,22 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim PLL_158_55/CLK_OUT0 td 0.100 2.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 1.059 3.847 rd3_clk USCM_84_154/CLK_USCM td 0.000 3.847 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.786 5.633 ntR3907 - PLL_158_303/CLK_OUT1 td 0.096 5.729 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.571 7.300 nt_pix_clk - USCM_84_117/CLK_USCM td 0.000 7.300 r clkbufg_2/gopclkbufg/CLKOUT - net (fanout=1635) 1.531 8.831 ntclkbufg_2 - CLMA_190_124/CLK r u_hdmi_rst/rst/opit_0_L5Q_perm/CLK + net (fanout=1) 1.786 5.633 ntR3950 + PLL_158_303/CLK_OUT0 td 0.100 5.733 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 1.571 7.304 zoom_clk + USCM_84_118/CLK_USCM td 0.000 7.304 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 1.531 8.835 ntclkbufg_3 + CLMA_170_124/CLK r u_zoom_rst/rst/opit_0_L5Q_perm/CLK - CLMA_190_124/Q0 tco 0.226 9.057 r u_hdmi_rst/rst/opit_0_L5Q_perm/Q - net (fanout=163) 0.977 10.034 rd2_rst - DRM_234_88/RSTB[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[12].U_GTP_DRM18K/iGopDrm/RSTB[0] + CLMA_170_124/Q0 tco 0.226 9.061 r u_zoom_rst/rst/opit_0_L5Q_perm/Q + net (fanout=114) 1.004 10.065 zoom_rst + DRM_234_128/RSTA[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[6].U_GTP_DRM18K/iGopDrm/RSTA[0] - Data arrival time 10.034 Logic Levels: 0 - Logic: 0.226ns(18.786%), Route: 0.977ns(81.214%) + Data arrival time 10.065 Logic Levels: 0 + Logic: 0.226ns(18.374%), Route: 1.004ns(81.626%) ---------------------------------------------------------------------------------------------------- - Clock clk_720p60Hz (rising edge) 0.000 0.000 r + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 2.166 2.240 r clk_ibuf/opit_0/O @@ -6770,41 +7091,41 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 1.078 4.288 rd3_clk USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.861 6.149 ntR3907 - PLL_158_303/CLK_OUT1 td 0.101 6.250 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.599 7.849 nt_pix_clk - USCM_84_117/CLK_USCM td 0.000 7.849 r clkbufg_2/gopclkbufg/CLKOUT - net (fanout=1635) 1.585 9.434 ntclkbufg_2 - DRM_234_88/CLKB[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[12].U_GTP_DRM18K/iGopDrm/CLKB[0] - clock pessimism -0.567 8.867 - clock uncertainty 0.000 8.867 + net (fanout=1) 1.861 6.149 ntR3950 + PLL_158_303/CLK_OUT0 td 0.107 6.256 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 1.599 7.855 zoom_clk + USCM_84_118/CLK_USCM td 0.000 7.855 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 1.585 9.440 ntclkbufg_3 + DRM_234_128/CLKA[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[6].U_GTP_DRM18K/iGopDrm/CLKA[0] + clock pessimism -0.551 8.889 + clock uncertainty 0.000 8.889 - Removal time -0.077 8.790 + Removal time -0.073 8.816 - Data required time 8.790 + Data required time 8.816 ---------------------------------------------------------------------------------------------------- - Data required time 8.790 - Data arrival time 10.034 + Data required time 8.816 + Data arrival time 10.065 ---------------------------------------------------------------------------------------------------- - Slack (MET) 1.244 + Slack (MET) 1.249 ==================================================================================================== ==================================================================================================== -Startpoint : u_hdmi_rst/rst/opit_0_L5Q_perm/CLK -Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0] -Path Group : clk_720p60Hz +Startpoint : u_zoom_rst/rst/opit_0_L5Q_perm/CLK +Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/RSTA[0] +Path Group : clk_1080p60Hz Path Type : min (slow corner) Path Class : async timing path -Clock Skew : 0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 9.434 - Launch Clock Delay : 8.831 - Clock Pessimism Removal : -0.549 +Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 9.440 + Launch Clock Delay : 8.835 + Clock Pessimism Removal : -0.569 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_720p60Hz (rising edge) 0.000 0.000 r + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.808 1.882 r clk_ibuf/opit_0/O @@ -6814,22 +7135,22 @@ Clock Skew : 0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessim PLL_158_55/CLK_OUT0 td 0.100 2.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 1.059 3.847 rd3_clk USCM_84_154/CLK_USCM td 0.000 3.847 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.786 5.633 ntR3907 - PLL_158_303/CLK_OUT1 td 0.096 5.729 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.571 7.300 nt_pix_clk - USCM_84_117/CLK_USCM td 0.000 7.300 r clkbufg_2/gopclkbufg/CLKOUT - net (fanout=1635) 1.531 8.831 ntclkbufg_2 - CLMA_190_124/CLK r u_hdmi_rst/rst/opit_0_L5Q_perm/CLK + net (fanout=1) 1.786 5.633 ntR3950 + PLL_158_303/CLK_OUT0 td 0.100 5.733 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 1.571 7.304 zoom_clk + USCM_84_118/CLK_USCM td 0.000 7.304 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 1.531 8.835 ntclkbufg_3 + CLMA_170_124/CLK r u_zoom_rst/rst/opit_0_L5Q_perm/CLK - CLMA_190_124/Q0 tco 0.226 9.057 r u_hdmi_rst/rst/opit_0_L5Q_perm/Q - net (fanout=163) 1.106 10.163 rd2_rst - DRM_234_148/RSTB[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0] + CLMA_170_124/Q0 tco 0.226 9.061 r u_zoom_rst/rst/opit_0_L5Q_perm/Q + net (fanout=114) 1.040 10.101 zoom_rst + DRM_234_88/RSTA[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/RSTA[0] - Data arrival time 10.163 Logic Levels: 0 - Logic: 0.226ns(16.967%), Route: 1.106ns(83.033%) + Data arrival time 10.101 Logic Levels: 0 + Logic: 0.226ns(17.852%), Route: 1.040ns(82.148%) ---------------------------------------------------------------------------------------------------- - Clock clk_720p60Hz (rising edge) 0.000 0.000 r + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 2.166 2.240 r clk_ibuf/opit_0/O @@ -6839,41 +7160,41 @@ Clock Skew : 0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessim PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 1.078 4.288 rd3_clk USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.861 6.149 ntR3907 - PLL_158_303/CLK_OUT1 td 0.101 6.250 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.599 7.849 nt_pix_clk - USCM_84_117/CLK_USCM td 0.000 7.849 r clkbufg_2/gopclkbufg/CLKOUT - net (fanout=1635) 1.585 9.434 ntclkbufg_2 - DRM_234_148/CLKB[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] - clock pessimism -0.549 8.885 - clock uncertainty 0.000 8.885 + net (fanout=1) 1.861 6.149 ntR3950 + PLL_158_303/CLK_OUT0 td 0.107 6.256 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 1.599 7.855 zoom_clk + USCM_84_118/CLK_USCM td 0.000 7.855 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 1.585 9.440 ntclkbufg_3 + DRM_234_88/CLKA[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] + clock pessimism -0.569 8.871 + clock uncertainty 0.000 8.871 - Removal time -0.077 8.808 + Removal time -0.073 8.798 - Data required time 8.808 + Data required time 8.798 ---------------------------------------------------------------------------------------------------- - Data required time 8.808 - Data arrival time 10.163 + Data required time 8.798 + Data arrival time 10.101 ---------------------------------------------------------------------------------------------------- - Slack (MET) 1.355 + Slack (MET) 1.303 ==================================================================================================== ==================================================================================================== -Startpoint : u_hdmi_rst/rst/opit_0_L5Q_perm/CLK -Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[15]/opit_0/RS -Path Group : clk_720p60Hz +Startpoint : u_zoom_rst/rst/opit_0_L5Q_perm/CLK +Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[7].U_GTP_DRM18K/iGopDrm/RSTA[0] +Path Group : clk_1080p60Hz Path Type : min (slow corner) Path Class : async timing path -Clock Skew : 0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 9.434 - Launch Clock Delay : 8.831 - Clock Pessimism Removal : -0.549 +Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 9.440 + Launch Clock Delay : 8.835 + Clock Pessimism Removal : -0.569 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_720p60Hz (rising edge) 0.000 0.000 r + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.808 1.882 r clk_ibuf/opit_0/O @@ -6883,22 +7204,22 @@ Clock Skew : 0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessim PLL_158_55/CLK_OUT0 td 0.100 2.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 1.059 3.847 rd3_clk USCM_84_154/CLK_USCM td 0.000 3.847 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.786 5.633 ntR3907 - PLL_158_303/CLK_OUT1 td 0.096 5.729 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.571 7.300 nt_pix_clk - USCM_84_117/CLK_USCM td 0.000 7.300 r clkbufg_2/gopclkbufg/CLKOUT - net (fanout=1635) 1.531 8.831 ntclkbufg_2 - CLMA_190_124/CLK r u_hdmi_rst/rst/opit_0_L5Q_perm/CLK + net (fanout=1) 1.786 5.633 ntR3950 + PLL_158_303/CLK_OUT0 td 0.100 5.733 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 1.571 7.304 zoom_clk + USCM_84_118/CLK_USCM td 0.000 7.304 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 1.531 8.835 ntclkbufg_3 + CLMA_170_124/CLK r u_zoom_rst/rst/opit_0_L5Q_perm/CLK - CLMA_190_124/Q0 tco 0.226 9.057 r u_hdmi_rst/rst/opit_0_L5Q_perm/Q - net (fanout=163) 0.979 10.036 rd2_rst - CLMS_226_173/RS r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[15]/opit_0/RS + CLMA_170_124/Q0 tco 0.226 9.061 r u_zoom_rst/rst/opit_0_L5Q_perm/Q + net (fanout=114) 1.120 10.181 zoom_rst + DRM_234_108/RSTA[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[7].U_GTP_DRM18K/iGopDrm/RSTA[0] - Data arrival time 10.036 Logic Levels: 0 - Logic: 0.226ns(18.755%), Route: 0.979ns(81.245%) + Data arrival time 10.181 Logic Levels: 0 + Logic: 0.226ns(16.790%), Route: 1.120ns(83.210%) ---------------------------------------------------------------------------------------------------- - Clock clk_720p60Hz (rising edge) 0.000 0.000 r + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 2.166 2.240 r clk_ibuf/opit_0/O @@ -6908,36 +7229,546 @@ Clock Skew : 0.054 (Capture Clock Delay - Launch Clock Delay + Clock Pessim PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 1.078 4.288 rd3_clk USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.861 6.149 ntR3907 - PLL_158_303/CLK_OUT1 td 0.101 6.250 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.599 7.849 nt_pix_clk - USCM_84_117/CLK_USCM td 0.000 7.849 r clkbufg_2/gopclkbufg/CLKOUT - net (fanout=1635) 1.585 9.434 ntclkbufg_2 - CLMS_226_173/CLK r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[15]/opit_0/CLK - clock pessimism -0.549 8.885 - clock uncertainty 0.000 8.885 + net (fanout=1) 1.861 6.149 ntR3950 + PLL_158_303/CLK_OUT0 td 0.107 6.256 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 1.599 7.855 zoom_clk + USCM_84_118/CLK_USCM td 0.000 7.855 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 1.585 9.440 ntclkbufg_3 + DRM_234_108/CLKA[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[7].U_GTP_DRM18K/iGopDrm/CLKA[0] + clock pessimism -0.569 8.871 + clock uncertainty 0.000 8.871 - Removal time -0.226 8.659 + Removal time -0.073 8.798 - Data required time 8.659 + Data required time 8.798 ---------------------------------------------------------------------------------------------------- - Data required time 8.659 - Data arrival time 10.036 + Data required time 8.798 + Data arrival time 10.181 ---------------------------------------------------------------------------------------------------- - Slack (MET) 1.377 + Slack (MET) 1.383 ==================================================================================================== ==================================================================================================== -Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK -Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[24]/opit_0_inv/RS -Path Group : ddrphy_clkin +Startpoint : sync_vg_100m/opit_0_inv_L5Q_perm/CLK +Endpoint : udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0/RS +Path Group : clk_720p60Hz Path Type : max (slow corner) Path Class : async timing path -Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 10.786 - Launch Clock Delay : 11.394 - Clock Pessimism Removal : 0.675 +Clock Skew : -0.056 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 8.952 + Launch Clock Delay : 9.557 + Clock Pessimism Removal : 0.549 + + Location Delay Type Incr Path Logical Resource +---------------------------------------------------------------------------------------------------- + + Clock clk_720p60Hz (rising edge) 0.000 0.000 r + P20 0.000 0.000 r clk (port) + net (fanout=1) 0.074 0.074 clk + IOBS_LR_328_209/DIN td 2.166 2.240 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 2.240 clk_ibuf/ntD + IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.787 3.103 _N69 + PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 1.078 4.288 rd3_clk + USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.861 6.149 ntR3950 + PLL_158_303/CLK_OUT1 td 0.101 6.250 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + net (fanout=2) 1.599 7.849 nt_pix_clk + USCM_84_117/CLK_USCM td 0.000 7.849 r clkbufg_2/gopclkbufg/CLKOUT + net (fanout=1635) 1.708 9.557 ntclkbufg_2 + CLMA_150_276/CLK r sync_vg_100m/opit_0_inv_L5Q_perm/CLK + + CLMA_150_276/Q0 tco 0.287 9.844 f sync_vg_100m/opit_0_inv_L5Q_perm/Q + net (fanout=911) 1.982 11.826 sync_vg_100m + CLMA_190_240/RSCO td 0.147 11.973 f udp_wr_mem_inst/mem[39]/opit_0/RSOUT + net (fanout=3) 0.000 11.973 ntR687 + CLMA_190_244/RSCO td 0.147 12.120 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[4]/opit_0/RSOUT + net (fanout=4) 0.000 12.120 ntR686 + CLMA_190_248/RSCO td 0.147 12.267 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[40]/opit_0_L5Q_perm/RSOUT + net (fanout=2) 0.000 12.267 ntR685 + CLMA_190_252/RSCO td 0.147 12.414 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[7]/opit_0/RSOUT + net (fanout=6) 0.000 12.414 ntR684 + CLMA_190_256/RSCO td 0.147 12.561 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[7]/opit_0/RSOUT + net (fanout=5) 0.000 12.561 ntR683 + CLMA_190_260/RSCO td 0.147 12.708 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[27]/opit_0_L5Q_perm/RSOUT + net (fanout=6) 0.000 12.708 ntR682 + CLMA_190_264/RSCO td 0.147 12.855 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[22]/opit_0/RSOUT + net (fanout=4) 0.000 12.855 ntR681 + CLMA_190_268/RSCO td 0.147 13.002 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[30]/opit_0_L5Q_perm/RSOUT + net (fanout=4) 0.000 13.002 ntR680 + CLMA_190_272/RSCO td 0.147 13.149 f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[4]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=4) 0.000 13.149 ntR679 + CLMA_190_276/RSCO td 0.147 13.296 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[23]/opit_0/RSOUT + net (fanout=4) 0.000 13.296 ntR678 + CLMA_190_280/RSCO td 0.147 13.443 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][1]/opit_0/RSOUT + net (fanout=4) 0.000 13.443 ntR677 + CLMA_190_284/RSCO td 0.147 13.590 f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/RSOUT + net (fanout=6) 0.000 13.590 ntR676 + CLMA_190_288/RSCO td 0.147 13.737 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[29]/opit_0/RSOUT + net (fanout=1) 0.000 13.737 ntR675 + CLMA_190_292/RSCO td 0.147 13.884 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][1]/opit_0/RSOUT + net (fanout=6) 0.000 13.884 ntR674 + CLMA_190_296/RSCI f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0/RS + + Data arrival time 13.884 Logic Levels: 14 + Logic: 2.345ns(54.195%), Route: 1.982ns(45.805%) +---------------------------------------------------------------------------------------------------- + + Clock clk_720p60Hz (rising edge) 13.473 13.473 r + P20 0.000 13.473 r clk (port) + net (fanout=1) 0.074 13.547 clk + IOBS_LR_328_209/DIN td 1.808 15.355 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 15.355 clk_ibuf/ntD + IOL_327_210/INCK td 0.048 15.403 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.758 16.161 _N69 + PLL_158_55/CLK_OUT0 td 0.100 16.261 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 1.059 17.320 rd3_clk + USCM_84_154/CLK_USCM td 0.000 17.320 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.786 19.106 ntR3950 + PLL_158_303/CLK_OUT1 td 0.096 19.202 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + net (fanout=2) 1.571 20.773 nt_pix_clk + USCM_84_117/CLK_USCM td 0.000 20.773 r clkbufg_2/gopclkbufg/CLKOUT + net (fanout=1635) 1.652 22.425 ntclkbufg_2 + CLMA_190_296/CLK r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0/CLK + clock pessimism 0.549 22.974 + clock uncertainty -0.150 22.824 + + Recovery time 0.000 22.824 + + Data required time 22.824 +---------------------------------------------------------------------------------------------------- + Data required time 22.824 + Data arrival time 13.884 +---------------------------------------------------------------------------------------------------- + Slack (MET) 8.940 +==================================================================================================== + +==================================================================================================== + +Startpoint : sync_vg_100m/opit_0_inv_L5Q_perm/CLK +Endpoint : udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/opit_0/RS +Path Group : clk_720p60Hz +Path Type : max (slow corner) +Path Class : async timing path +Clock Skew : -0.056 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 8.952 + Launch Clock Delay : 9.557 + Clock Pessimism Removal : 0.549 + + Location Delay Type Incr Path Logical Resource +---------------------------------------------------------------------------------------------------- + + Clock clk_720p60Hz (rising edge) 0.000 0.000 r + P20 0.000 0.000 r clk (port) + net (fanout=1) 0.074 0.074 clk + IOBS_LR_328_209/DIN td 2.166 2.240 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 2.240 clk_ibuf/ntD + IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.787 3.103 _N69 + PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 1.078 4.288 rd3_clk + USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.861 6.149 ntR3950 + PLL_158_303/CLK_OUT1 td 0.101 6.250 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + net (fanout=2) 1.599 7.849 nt_pix_clk + USCM_84_117/CLK_USCM td 0.000 7.849 r clkbufg_2/gopclkbufg/CLKOUT + net (fanout=1635) 1.708 9.557 ntclkbufg_2 + CLMA_150_276/CLK r sync_vg_100m/opit_0_inv_L5Q_perm/CLK + + CLMA_150_276/Q0 tco 0.287 9.844 f sync_vg_100m/opit_0_inv_L5Q_perm/Q + net (fanout=911) 1.982 11.826 sync_vg_100m + CLMA_190_240/RSCO td 0.147 11.973 f udp_wr_mem_inst/mem[39]/opit_0/RSOUT + net (fanout=3) 0.000 11.973 ntR687 + CLMA_190_244/RSCO td 0.147 12.120 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[4]/opit_0/RSOUT + net (fanout=4) 0.000 12.120 ntR686 + CLMA_190_248/RSCO td 0.147 12.267 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[40]/opit_0_L5Q_perm/RSOUT + net (fanout=2) 0.000 12.267 ntR685 + CLMA_190_252/RSCO td 0.147 12.414 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[7]/opit_0/RSOUT + net (fanout=6) 0.000 12.414 ntR684 + CLMA_190_256/RSCO td 0.147 12.561 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[7]/opit_0/RSOUT + net (fanout=5) 0.000 12.561 ntR683 + CLMA_190_260/RSCO td 0.147 12.708 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[27]/opit_0_L5Q_perm/RSOUT + net (fanout=6) 0.000 12.708 ntR682 + CLMA_190_264/RSCO td 0.147 12.855 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[22]/opit_0/RSOUT + net (fanout=4) 0.000 12.855 ntR681 + CLMA_190_268/RSCO td 0.147 13.002 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[30]/opit_0_L5Q_perm/RSOUT + net (fanout=4) 0.000 13.002 ntR680 + CLMA_190_272/RSCO td 0.147 13.149 f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[4]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=4) 0.000 13.149 ntR679 + CLMA_190_276/RSCO td 0.147 13.296 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[23]/opit_0/RSOUT + net (fanout=4) 0.000 13.296 ntR678 + CLMA_190_280/RSCO td 0.147 13.443 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][1]/opit_0/RSOUT + net (fanout=4) 0.000 13.443 ntR677 + CLMA_190_284/RSCO td 0.147 13.590 f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/RSOUT + net (fanout=6) 0.000 13.590 ntR676 + CLMA_190_288/RSCO td 0.147 13.737 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[29]/opit_0/RSOUT + net (fanout=1) 0.000 13.737 ntR675 + CLMA_190_292/RSCO td 0.147 13.884 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][1]/opit_0/RSOUT + net (fanout=6) 0.000 13.884 ntR674 + CLMA_190_296/RSCI f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/opit_0/RS + + Data arrival time 13.884 Logic Levels: 14 + Logic: 2.345ns(54.195%), Route: 1.982ns(45.805%) +---------------------------------------------------------------------------------------------------- + + Clock clk_720p60Hz (rising edge) 13.473 13.473 r + P20 0.000 13.473 r clk (port) + net (fanout=1) 0.074 13.547 clk + IOBS_LR_328_209/DIN td 1.808 15.355 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 15.355 clk_ibuf/ntD + IOL_327_210/INCK td 0.048 15.403 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.758 16.161 _N69 + PLL_158_55/CLK_OUT0 td 0.100 16.261 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 1.059 17.320 rd3_clk + USCM_84_154/CLK_USCM td 0.000 17.320 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.786 19.106 ntR3950 + PLL_158_303/CLK_OUT1 td 0.096 19.202 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + net (fanout=2) 1.571 20.773 nt_pix_clk + USCM_84_117/CLK_USCM td 0.000 20.773 r clkbufg_2/gopclkbufg/CLKOUT + net (fanout=1635) 1.652 22.425 ntclkbufg_2 + CLMA_190_296/CLK r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/opit_0/CLK + clock pessimism 0.549 22.974 + clock uncertainty -0.150 22.824 + + Recovery time 0.000 22.824 + + Data required time 22.824 +---------------------------------------------------------------------------------------------------- + Data required time 22.824 + Data arrival time 13.884 +---------------------------------------------------------------------------------------------------- + Slack (MET) 8.940 +==================================================================================================== + +==================================================================================================== + +Startpoint : sync_vg_100m/opit_0_inv_L5Q_perm/CLK +Endpoint : udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/RS +Path Group : clk_720p60Hz +Path Type : max (slow corner) +Path Class : async timing path +Clock Skew : -0.056 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 8.952 + Launch Clock Delay : 9.557 + Clock Pessimism Removal : 0.549 + + Location Delay Type Incr Path Logical Resource +---------------------------------------------------------------------------------------------------- + + Clock clk_720p60Hz (rising edge) 0.000 0.000 r + P20 0.000 0.000 r clk (port) + net (fanout=1) 0.074 0.074 clk + IOBS_LR_328_209/DIN td 2.166 2.240 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 2.240 clk_ibuf/ntD + IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.787 3.103 _N69 + PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 1.078 4.288 rd3_clk + USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.861 6.149 ntR3950 + PLL_158_303/CLK_OUT1 td 0.101 6.250 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + net (fanout=2) 1.599 7.849 nt_pix_clk + USCM_84_117/CLK_USCM td 0.000 7.849 r clkbufg_2/gopclkbufg/CLKOUT + net (fanout=1635) 1.708 9.557 ntclkbufg_2 + CLMA_150_276/CLK r sync_vg_100m/opit_0_inv_L5Q_perm/CLK + + CLMA_150_276/Q0 tco 0.287 9.844 f sync_vg_100m/opit_0_inv_L5Q_perm/Q + net (fanout=911) 1.982 11.826 sync_vg_100m + CLMA_190_240/RSCO td 0.147 11.973 f udp_wr_mem_inst/mem[39]/opit_0/RSOUT + net (fanout=3) 0.000 11.973 ntR687 + CLMA_190_244/RSCO td 0.147 12.120 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[4]/opit_0/RSOUT + net (fanout=4) 0.000 12.120 ntR686 + CLMA_190_248/RSCO td 0.147 12.267 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[40]/opit_0_L5Q_perm/RSOUT + net (fanout=2) 0.000 12.267 ntR685 + CLMA_190_252/RSCO td 0.147 12.414 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[7]/opit_0/RSOUT + net (fanout=6) 0.000 12.414 ntR684 + CLMA_190_256/RSCO td 0.147 12.561 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[7]/opit_0/RSOUT + net (fanout=5) 0.000 12.561 ntR683 + CLMA_190_260/RSCO td 0.147 12.708 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[27]/opit_0_L5Q_perm/RSOUT + net (fanout=6) 0.000 12.708 ntR682 + CLMA_190_264/RSCO td 0.147 12.855 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[22]/opit_0/RSOUT + net (fanout=4) 0.000 12.855 ntR681 + CLMA_190_268/RSCO td 0.147 13.002 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[30]/opit_0_L5Q_perm/RSOUT + net (fanout=4) 0.000 13.002 ntR680 + CLMA_190_272/RSCO td 0.147 13.149 f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[4]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=4) 0.000 13.149 ntR679 + CLMA_190_276/RSCO td 0.147 13.296 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[23]/opit_0/RSOUT + net (fanout=4) 0.000 13.296 ntR678 + CLMA_190_280/RSCO td 0.147 13.443 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][1]/opit_0/RSOUT + net (fanout=4) 0.000 13.443 ntR677 + CLMA_190_284/RSCO td 0.147 13.590 f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/RSOUT + net (fanout=6) 0.000 13.590 ntR676 + CLMA_190_288/RSCO td 0.147 13.737 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[29]/opit_0/RSOUT + net (fanout=1) 0.000 13.737 ntR675 + CLMA_190_292/RSCO td 0.147 13.884 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][1]/opit_0/RSOUT + net (fanout=6) 0.000 13.884 ntR674 + CLMA_190_296/RSCI f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/RS + + Data arrival time 13.884 Logic Levels: 14 + Logic: 2.345ns(54.195%), Route: 1.982ns(45.805%) +---------------------------------------------------------------------------------------------------- + + Clock clk_720p60Hz (rising edge) 13.473 13.473 r + P20 0.000 13.473 r clk (port) + net (fanout=1) 0.074 13.547 clk + IOBS_LR_328_209/DIN td 1.808 15.355 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 15.355 clk_ibuf/ntD + IOL_327_210/INCK td 0.048 15.403 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.758 16.161 _N69 + PLL_158_55/CLK_OUT0 td 0.100 16.261 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 1.059 17.320 rd3_clk + USCM_84_154/CLK_USCM td 0.000 17.320 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.786 19.106 ntR3950 + PLL_158_303/CLK_OUT1 td 0.096 19.202 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + net (fanout=2) 1.571 20.773 nt_pix_clk + USCM_84_117/CLK_USCM td 0.000 20.773 r clkbufg_2/gopclkbufg/CLKOUT + net (fanout=1635) 1.652 22.425 ntclkbufg_2 + CLMA_190_296/CLK r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/CLK + clock pessimism 0.549 22.974 + clock uncertainty -0.150 22.824 + + Recovery time 0.000 22.824 + + Data required time 22.824 +---------------------------------------------------------------------------------------------------- + Data required time 22.824 + Data arrival time 13.884 +---------------------------------------------------------------------------------------------------- + Slack (MET) 8.940 +==================================================================================================== + +==================================================================================================== + +Startpoint : sync_vg_100m/opit_0_inv_L5Q_perm/CLK +Endpoint : udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0] +Path Group : clk_720p60Hz +Path Type : min (slow corner) +Path Class : async timing path +Clock Skew : 0.056 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 9.557 + Launch Clock Delay : 8.952 + Clock Pessimism Removal : -0.549 + + Location Delay Type Incr Path Logical Resource +---------------------------------------------------------------------------------------------------- + + Clock clk_720p60Hz (rising edge) 0.000 0.000 r + P20 0.000 0.000 r clk (port) + net (fanout=1) 0.074 0.074 clk + IOBS_LR_328_209/DIN td 1.808 1.882 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 1.882 clk_ibuf/ntD + IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.758 2.688 _N69 + PLL_158_55/CLK_OUT0 td 0.100 2.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 1.059 3.847 rd3_clk + USCM_84_154/CLK_USCM td 0.000 3.847 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.786 5.633 ntR3950 + PLL_158_303/CLK_OUT1 td 0.096 5.729 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + net (fanout=2) 1.571 7.300 nt_pix_clk + USCM_84_117/CLK_USCM td 0.000 7.300 r clkbufg_2/gopclkbufg/CLKOUT + net (fanout=1635) 1.652 8.952 ntclkbufg_2 + CLMA_150_276/CLK r sync_vg_100m/opit_0_inv_L5Q_perm/CLK + + CLMA_150_276/Q0 tco 0.222 9.174 f sync_vg_100m/opit_0_inv_L5Q_perm/Q + net (fanout=911) 0.796 9.970 sync_vg_100m + DRM_178_272/RSTB[0] f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0] + + Data arrival time 9.970 Logic Levels: 0 + Logic: 0.222ns(21.807%), Route: 0.796ns(78.193%) +---------------------------------------------------------------------------------------------------- + + Clock clk_720p60Hz (rising edge) 0.000 0.000 r + P20 0.000 0.000 r clk (port) + net (fanout=1) 0.074 0.074 clk + IOBS_LR_328_209/DIN td 2.166 2.240 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 2.240 clk_ibuf/ntD + IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.787 3.103 _N69 + PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 1.078 4.288 rd3_clk + USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.861 6.149 ntR3950 + PLL_158_303/CLK_OUT1 td 0.101 6.250 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + net (fanout=2) 1.599 7.849 nt_pix_clk + USCM_84_117/CLK_USCM td 0.000 7.849 r clkbufg_2/gopclkbufg/CLKOUT + net (fanout=1635) 1.708 9.557 ntclkbufg_2 + DRM_178_272/CLKB[0] r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] + clock pessimism -0.549 9.008 + clock uncertainty 0.000 9.008 + + Removal time -0.022 8.986 + + Data required time 8.986 +---------------------------------------------------------------------------------------------------- + Data required time 8.986 + Data arrival time 9.970 +---------------------------------------------------------------------------------------------------- + Slack (MET) 0.984 +==================================================================================================== + +==================================================================================================== + +Startpoint : sync_vg_100m/opit_0_inv_L5Q_perm/CLK +Endpoint : udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/RS +Path Group : clk_720p60Hz +Path Type : min (slow corner) +Path Class : async timing path +Clock Skew : 0.056 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 9.557 + Launch Clock Delay : 8.952 + Clock Pessimism Removal : -0.549 + + Location Delay Type Incr Path Logical Resource +---------------------------------------------------------------------------------------------------- + + Clock clk_720p60Hz (rising edge) 0.000 0.000 r + P20 0.000 0.000 r clk (port) + net (fanout=1) 0.074 0.074 clk + IOBS_LR_328_209/DIN td 1.808 1.882 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 1.882 clk_ibuf/ntD + IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.758 2.688 _N69 + PLL_158_55/CLK_OUT0 td 0.100 2.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 1.059 3.847 rd3_clk + USCM_84_154/CLK_USCM td 0.000 3.847 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.786 5.633 ntR3950 + PLL_158_303/CLK_OUT1 td 0.096 5.729 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + net (fanout=2) 1.571 7.300 nt_pix_clk + USCM_84_117/CLK_USCM td 0.000 7.300 r clkbufg_2/gopclkbufg/CLKOUT + net (fanout=1635) 1.652 8.952 ntclkbufg_2 + CLMA_150_276/CLK r sync_vg_100m/opit_0_inv_L5Q_perm/CLK + + CLMA_150_276/Q0 tco 0.226 9.178 r sync_vg_100m/opit_0_inv_L5Q_perm/Q + net (fanout=911) 0.801 9.979 sync_vg_100m + CLMA_182_281/RSCO td 0.105 10.084 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=3) 0.000 10.084 ntR691 + CLMA_182_285/RSCO td 0.105 10.189 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[10]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=4) 0.000 10.189 ntR690 + CLMA_182_289/RSCO td 0.105 10.294 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/RSOUT + net (fanout=5) 0.000 10.294 ntR689 + CLMA_182_293/RSCI r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/RS + + Data arrival time 10.294 Logic Levels: 3 + Logic: 0.541ns(40.313%), Route: 0.801ns(59.687%) +---------------------------------------------------------------------------------------------------- + + Clock clk_720p60Hz (rising edge) 0.000 0.000 r + P20 0.000 0.000 r clk (port) + net (fanout=1) 0.074 0.074 clk + IOBS_LR_328_209/DIN td 2.166 2.240 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 2.240 clk_ibuf/ntD + IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.787 3.103 _N69 + PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 1.078 4.288 rd3_clk + USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.861 6.149 ntR3950 + PLL_158_303/CLK_OUT1 td 0.101 6.250 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + net (fanout=2) 1.599 7.849 nt_pix_clk + USCM_84_117/CLK_USCM td 0.000 7.849 r clkbufg_2/gopclkbufg/CLKOUT + net (fanout=1635) 1.708 9.557 ntclkbufg_2 + CLMA_182_293/CLK r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/CLK + clock pessimism -0.549 9.008 + clock uncertainty 0.000 9.008 + + Removal time 0.000 9.008 + + Data required time 9.008 +---------------------------------------------------------------------------------------------------- + Data required time 9.008 + Data arrival time 10.294 +---------------------------------------------------------------------------------------------------- + Slack (MET) 1.286 +==================================================================================================== + +==================================================================================================== + +Startpoint : sync_vg_100m/opit_0_inv_L5Q_perm/CLK +Endpoint : udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm/RS +Path Group : clk_720p60Hz +Path Type : min (slow corner) +Path Class : async timing path +Clock Skew : 0.056 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 9.557 + Launch Clock Delay : 8.952 + Clock Pessimism Removal : -0.549 + + Location Delay Type Incr Path Logical Resource +---------------------------------------------------------------------------------------------------- + + Clock clk_720p60Hz (rising edge) 0.000 0.000 r + P20 0.000 0.000 r clk (port) + net (fanout=1) 0.074 0.074 clk + IOBS_LR_328_209/DIN td 1.808 1.882 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 1.882 clk_ibuf/ntD + IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.758 2.688 _N69 + PLL_158_55/CLK_OUT0 td 0.100 2.788 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 1.059 3.847 rd3_clk + USCM_84_154/CLK_USCM td 0.000 3.847 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.786 5.633 ntR3950 + PLL_158_303/CLK_OUT1 td 0.096 5.729 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + net (fanout=2) 1.571 7.300 nt_pix_clk + USCM_84_117/CLK_USCM td 0.000 7.300 r clkbufg_2/gopclkbufg/CLKOUT + net (fanout=1635) 1.652 8.952 ntclkbufg_2 + CLMA_150_276/CLK r sync_vg_100m/opit_0_inv_L5Q_perm/CLK + + CLMA_150_276/Q0 tco 0.226 9.178 r sync_vg_100m/opit_0_inv_L5Q_perm/Q + net (fanout=911) 0.801 9.979 sync_vg_100m + CLMA_182_281/RSCO td 0.105 10.084 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=3) 0.000 10.084 ntR691 + CLMA_182_285/RSCO td 0.105 10.189 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[10]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=4) 0.000 10.189 ntR690 + CLMA_182_289/RSCO td 0.105 10.294 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/RSOUT + net (fanout=5) 0.000 10.294 ntR689 + CLMA_182_293/RSCI r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm/RS + + Data arrival time 10.294 Logic Levels: 3 + Logic: 0.541ns(40.313%), Route: 0.801ns(59.687%) +---------------------------------------------------------------------------------------------------- + + Clock clk_720p60Hz (rising edge) 0.000 0.000 r + P20 0.000 0.000 r clk (port) + net (fanout=1) 0.074 0.074 clk + IOBS_LR_328_209/DIN td 2.166 2.240 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 2.240 clk_ibuf/ntD + IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.787 3.103 _N69 + PLL_158_55/CLK_OUT0 td 0.107 3.210 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 1.078 4.288 rd3_clk + USCM_84_154/CLK_USCM td 0.000 4.288 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.861 6.149 ntR3950 + PLL_158_303/CLK_OUT1 td 0.101 6.250 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + net (fanout=2) 1.599 7.849 nt_pix_clk + USCM_84_117/CLK_USCM td 0.000 7.849 r clkbufg_2/gopclkbufg/CLKOUT + net (fanout=1635) 1.708 9.557 ntclkbufg_2 + CLMA_182_293/CLK r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm/CLK + clock pessimism -0.549 9.008 + clock uncertainty 0.000 9.008 + + Removal time 0.000 9.008 + + Data required time 9.008 +---------------------------------------------------------------------------------------------------- + Data required time 9.008 + Data arrival time 10.294 +---------------------------------------------------------------------------------------------------- + Slack (MET) 1.286 +==================================================================================================== + +==================================================================================================== + +Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/opit_0_inv_L5Q_perm/RS +Path Group : ddrphy_clkin +Path Type : max (slow corner) +Path Class : async timing path +Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 10.665 + Launch Clock Delay : 11.394 + Clock Pessimism Removal : 0.693 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -6950,59 +7781,57 @@ Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.078 4.282 zoom_clk + net (fanout=2) 1.078 4.282 ddr_clk USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.121 7.270 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 7.618 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 2.191 9.809 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 9.809 r clkbufg_0/gopclkbufg/CLKOUT net (fanout=5464) 1.585 11.394 ntclkbufg_0 - CLMA_70_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK - - CLMA_70_192/Q0 tco 0.289 11.683 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q - net (fanout=619) 1.655 13.338 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n - CLMA_10_224/RSCO td 0.147 13.485 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=4) 0.000 13.485 ntR1395 - CLMA_10_228/RSCO td 0.147 13.632 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[4]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=4) 0.000 13.632 ntR1394 - CLMA_10_232/RSCO td 0.147 13.779 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=4) 0.000 13.779 ntR1393 - CLMA_10_236/RSCO td 0.147 13.926 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[2]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=6) 0.000 13.926 ntR1392 - CLMA_10_240/RSCO td 0.147 14.073 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[246]/opit_0_inv/RSOUT - net (fanout=4) 0.000 14.073 ntR1391 - CLMA_10_244/RSCO td 0.147 14.220 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q_perm/RSOUT - net (fanout=2) 0.000 14.220 ntR1390 - CLMA_10_248/RSCO td 0.147 14.367 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[4]/opit_0_inv_A2Q21/RSOUT - net (fanout=3) 0.000 14.367 ntR1389 - CLMA_10_252/RSCO td 0.147 14.514 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/opit_0_inv_AQ_perm/RSOUT - net (fanout=4) 0.000 14.514 ntR1388 - CLMA_10_256/RSCO td 0.147 14.661 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=2) 0.000 14.661 ntR1387 - CLMA_10_260/RSCO td 0.147 14.808 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=2) 0.000 14.808 ntR1386 - CLMA_10_264/RSCO td 0.147 14.955 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[4]/opit_0_inv_A2Q21/RSOUT - net (fanout=3) 0.000 14.955 ntR1385 - CLMA_10_268/RSCO td 0.147 15.102 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/opit_0_inv_AQ/RSOUT - net (fanout=3) 0.000 15.102 ntR1384 - CLMA_10_272/RSCO td 0.147 15.249 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs/opit_0_inv/RSOUT - net (fanout=2) 0.000 15.249 ntR1383 - CLMA_10_276/RSCO td 0.147 15.396 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[3]/opit_0_inv_A2Q21/RSOUT - net (fanout=2) 0.000 15.396 ntR1382 - CLMA_10_280/RSCO td 0.147 15.543 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[7]/opit_0_inv_A2Q21/RSOUT - net (fanout=4) 0.000 15.543 ntR1381 - CLMA_10_284/RSCO td 0.147 15.690 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=4) 0.000 15.690 ntR1380 - CLMA_10_288/RSCO td 0.147 15.837 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[223]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=6) 0.000 15.837 ntR1379 - CLMA_10_292/RSCI f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[24]/opit_0_inv/RS - - Data arrival time 15.837 Logic Levels: 17 - Logic: 2.788ns(62.750%), Route: 1.655ns(37.250%) + CLMA_46_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK + + CLMA_46_192/Q0 tco 0.289 11.683 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q + net (fanout=729) 1.497 13.180 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n + CLMA_34_148/RSCO td 0.147 13.327 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[2]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=4) 0.000 13.327 ntR882 + CLMA_34_152/RSCO td 0.147 13.474 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[5]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=4) 0.000 13.474 ntR881 + CLMA_34_156/RSCO td 0.147 13.621 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_we_n_d[0]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=4) 0.000 13.621 ntR880 + CLMA_34_160/RSCO td 0.147 13.768 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cs_n_d[0]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=2) 0.000 13.768 ntR879 + CLMA_34_164/RSCO td 0.147 13.915 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[4]/opit_0_inv_A2Q21/RSOUT + net (fanout=3) 0.000 13.915 ntR878 + CLMA_34_168/RSCO td 0.147 14.062 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[0]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=6) 0.000 14.062 ntR877 + CLMA_34_172/RSCO td 0.147 14.209 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_r[1]/opit_0_inv/RSOUT + net (fanout=5) 0.000 14.209 ntR876 + CLMA_34_176/RSCO td 0.147 14.356 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=2) 0.000 14.356 ntR875 + CLMA_34_180/RSCO td 0.147 14.503 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[4]/opit_0_inv_A2Q21/RSOUT + net (fanout=2) 0.000 14.503 ntR874 + CLMA_34_184/RSCO td 0.147 14.650 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[8]/opit_0_inv_A2Q21/RSOUT + net (fanout=2) 0.000 14.650 ntR873 + CLMA_34_192/RSCO td 0.147 14.797 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[12]/opit_0_inv_A2Q21/RSOUT + net (fanout=2) 0.000 14.797 ntR872 + CLMA_34_196/RSCO td 0.147 14.944 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[16]/opit_0_inv_A2Q21/RSOUT + net (fanout=1) 0.000 14.944 ntR871 + CLMA_34_200/RSCO td 0.147 15.091 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[17]/opit_0_inv_AQ_perm/RSOUT + net (fanout=6) 0.000 15.091 ntR870 + CLMA_34_204/RSCO td 0.147 15.238 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[1]/opit_0_inv/RSOUT + net (fanout=5) 0.000 15.238 ntR869 + CLMA_34_208/RSCO td 0.147 15.385 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[238]/opit_0_inv/RSOUT + net (fanout=5) 0.000 15.385 ntR868 + CLMA_34_212/RSCO td 0.147 15.532 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[86]/opit_0_inv/RSOUT + net (fanout=5) 0.000 15.532 ntR867 + CLMA_34_216/RSCI f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/opit_0_inv_L5Q_perm/RS + + Data arrival time 15.532 Logic Levels: 16 + Logic: 2.641ns(63.823%), Route: 1.497ns(36.177%) ---------------------------------------------------------------------------------------------------- Clock ddrphy_clkin (rising edge) 10.000 10.000 r @@ -7013,42 +7842,42 @@ Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.048 11.930 r clk_ibuf/opit_1/INCK net (fanout=1) 0.758 12.688 _N69 PLL_158_55/CLK_OUT1 td 0.096 12.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.059 13.843 zoom_clk + net (fanout=2) 1.059 13.843 ddr_clk USCM_84_113/CLK_USCM td 0.000 13.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.665 15.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.665 15.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.123 15.631 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.102 16.733 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.249 16.982 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.249 16.982 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 16.982 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 16.982 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 2.152 19.134 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 19.134 r clkbufg_0/gopclkbufg/CLKOUT - net (fanout=5464) 1.652 20.786 ntclkbufg_0 - CLMA_10_292/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[24]/opit_0_inv/CLK - clock pessimism 0.675 21.461 - clock uncertainty -0.150 21.311 + net (fanout=5464) 1.531 20.665 ntclkbufg_0 + CLMA_34_216/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/opit_0_inv_L5Q_perm/CLK + clock pessimism 0.693 21.358 + clock uncertainty -0.150 21.208 - Recovery time 0.000 21.311 + Recovery time 0.000 21.208 - Data required time 21.311 + Data required time 21.208 ---------------------------------------------------------------------------------------------------- - Data required time 21.311 - Data arrival time 15.837 + Data required time 21.208 + Data arrival time 15.532 ---------------------------------------------------------------------------------------------------- - Slack (MET) 5.474 + Slack (MET) 5.676 ==================================================================================================== ==================================================================================================== Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK -Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[58]/opit_0_inv/RS +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[110]/opit_0_inv/RS Path Group : ddrphy_clkin Path Type : max (slow corner) Path Class : async timing path -Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 10.786 +Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 10.665 Launch Clock Delay : 11.394 - Clock Pessimism Removal : 0.675 + Clock Pessimism Removal : 0.693 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -7061,59 +7890,57 @@ Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.078 4.282 zoom_clk + net (fanout=2) 1.078 4.282 ddr_clk USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.121 7.270 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 7.618 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 2.191 9.809 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 9.809 r clkbufg_0/gopclkbufg/CLKOUT net (fanout=5464) 1.585 11.394 ntclkbufg_0 - CLMA_70_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK - - CLMA_70_192/Q0 tco 0.289 11.683 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q - net (fanout=619) 1.655 13.338 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n - CLMA_10_224/RSCO td 0.147 13.485 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=4) 0.000 13.485 ntR1395 - CLMA_10_228/RSCO td 0.147 13.632 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[4]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=4) 0.000 13.632 ntR1394 - CLMA_10_232/RSCO td 0.147 13.779 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=4) 0.000 13.779 ntR1393 - CLMA_10_236/RSCO td 0.147 13.926 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[2]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=6) 0.000 13.926 ntR1392 - CLMA_10_240/RSCO td 0.147 14.073 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[246]/opit_0_inv/RSOUT - net (fanout=4) 0.000 14.073 ntR1391 - CLMA_10_244/RSCO td 0.147 14.220 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q_perm/RSOUT - net (fanout=2) 0.000 14.220 ntR1390 - CLMA_10_248/RSCO td 0.147 14.367 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[4]/opit_0_inv_A2Q21/RSOUT - net (fanout=3) 0.000 14.367 ntR1389 - CLMA_10_252/RSCO td 0.147 14.514 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/opit_0_inv_AQ_perm/RSOUT - net (fanout=4) 0.000 14.514 ntR1388 - CLMA_10_256/RSCO td 0.147 14.661 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=2) 0.000 14.661 ntR1387 - CLMA_10_260/RSCO td 0.147 14.808 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=2) 0.000 14.808 ntR1386 - CLMA_10_264/RSCO td 0.147 14.955 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[4]/opit_0_inv_A2Q21/RSOUT - net (fanout=3) 0.000 14.955 ntR1385 - CLMA_10_268/RSCO td 0.147 15.102 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/opit_0_inv_AQ/RSOUT - net (fanout=3) 0.000 15.102 ntR1384 - CLMA_10_272/RSCO td 0.147 15.249 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs/opit_0_inv/RSOUT - net (fanout=2) 0.000 15.249 ntR1383 - CLMA_10_276/RSCO td 0.147 15.396 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[3]/opit_0_inv_A2Q21/RSOUT - net (fanout=2) 0.000 15.396 ntR1382 - CLMA_10_280/RSCO td 0.147 15.543 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[7]/opit_0_inv_A2Q21/RSOUT - net (fanout=4) 0.000 15.543 ntR1381 - CLMA_10_284/RSCO td 0.147 15.690 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=4) 0.000 15.690 ntR1380 - CLMA_10_288/RSCO td 0.147 15.837 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[223]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=6) 0.000 15.837 ntR1379 - CLMA_10_292/RSCI f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[58]/opit_0_inv/RS - - Data arrival time 15.837 Logic Levels: 17 - Logic: 2.788ns(62.750%), Route: 1.655ns(37.250%) + CLMA_46_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK + + CLMA_46_192/Q0 tco 0.289 11.683 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q + net (fanout=729) 1.497 13.180 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n + CLMA_34_148/RSCO td 0.147 13.327 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[2]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=4) 0.000 13.327 ntR882 + CLMA_34_152/RSCO td 0.147 13.474 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[5]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=4) 0.000 13.474 ntR881 + CLMA_34_156/RSCO td 0.147 13.621 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_we_n_d[0]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=4) 0.000 13.621 ntR880 + CLMA_34_160/RSCO td 0.147 13.768 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cs_n_d[0]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=2) 0.000 13.768 ntR879 + CLMA_34_164/RSCO td 0.147 13.915 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[4]/opit_0_inv_A2Q21/RSOUT + net (fanout=3) 0.000 13.915 ntR878 + CLMA_34_168/RSCO td 0.147 14.062 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[0]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=6) 0.000 14.062 ntR877 + CLMA_34_172/RSCO td 0.147 14.209 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_r[1]/opit_0_inv/RSOUT + net (fanout=5) 0.000 14.209 ntR876 + CLMA_34_176/RSCO td 0.147 14.356 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=2) 0.000 14.356 ntR875 + CLMA_34_180/RSCO td 0.147 14.503 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[4]/opit_0_inv_A2Q21/RSOUT + net (fanout=2) 0.000 14.503 ntR874 + CLMA_34_184/RSCO td 0.147 14.650 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[8]/opit_0_inv_A2Q21/RSOUT + net (fanout=2) 0.000 14.650 ntR873 + CLMA_34_192/RSCO td 0.147 14.797 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[12]/opit_0_inv_A2Q21/RSOUT + net (fanout=2) 0.000 14.797 ntR872 + CLMA_34_196/RSCO td 0.147 14.944 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[16]/opit_0_inv_A2Q21/RSOUT + net (fanout=1) 0.000 14.944 ntR871 + CLMA_34_200/RSCO td 0.147 15.091 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[17]/opit_0_inv_AQ_perm/RSOUT + net (fanout=6) 0.000 15.091 ntR870 + CLMA_34_204/RSCO td 0.147 15.238 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[1]/opit_0_inv/RSOUT + net (fanout=5) 0.000 15.238 ntR869 + CLMA_34_208/RSCO td 0.147 15.385 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[238]/opit_0_inv/RSOUT + net (fanout=5) 0.000 15.385 ntR868 + CLMA_34_212/RSCO td 0.147 15.532 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[86]/opit_0_inv/RSOUT + net (fanout=5) 0.000 15.532 ntR867 + CLMA_34_216/RSCI f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[110]/opit_0_inv/RS + + Data arrival time 15.532 Logic Levels: 16 + Logic: 2.641ns(63.823%), Route: 1.497ns(36.177%) ---------------------------------------------------------------------------------------------------- Clock ddrphy_clkin (rising edge) 10.000 10.000 r @@ -7124,42 +7951,42 @@ Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.048 11.930 r clk_ibuf/opit_1/INCK net (fanout=1) 0.758 12.688 _N69 PLL_158_55/CLK_OUT1 td 0.096 12.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.059 13.843 zoom_clk + net (fanout=2) 1.059 13.843 ddr_clk USCM_84_113/CLK_USCM td 0.000 13.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.665 15.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.665 15.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.123 15.631 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.102 16.733 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.249 16.982 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.249 16.982 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 16.982 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 16.982 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 2.152 19.134 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 19.134 r clkbufg_0/gopclkbufg/CLKOUT - net (fanout=5464) 1.652 20.786 ntclkbufg_0 - CLMA_10_292/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[58]/opit_0_inv/CLK - clock pessimism 0.675 21.461 - clock uncertainty -0.150 21.311 + net (fanout=5464) 1.531 20.665 ntclkbufg_0 + CLMA_34_216/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[110]/opit_0_inv/CLK + clock pessimism 0.693 21.358 + clock uncertainty -0.150 21.208 - Recovery time 0.000 21.311 + Recovery time 0.000 21.208 - Data required time 21.311 + Data required time 21.208 ---------------------------------------------------------------------------------------------------- - Data required time 21.311 - Data arrival time 15.837 + Data required time 21.208 + Data arrival time 15.532 ---------------------------------------------------------------------------------------------------- - Slack (MET) 5.474 + Slack (MET) 5.676 ==================================================================================================== ==================================================================================================== Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK -Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[60]/opit_0_inv/RS +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[116]/opit_0_inv/RS Path Group : ddrphy_clkin Path Type : max (slow corner) Path Class : async timing path -Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 10.786 +Clock Skew : -0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 10.665 Launch Clock Delay : 11.394 - Clock Pessimism Removal : 0.675 + Clock Pessimism Removal : 0.693 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -7172,59 +7999,57 @@ Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.078 4.282 zoom_clk + net (fanout=2) 1.078 4.282 ddr_clk USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.121 7.270 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 7.618 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 2.191 9.809 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 9.809 r clkbufg_0/gopclkbufg/CLKOUT net (fanout=5464) 1.585 11.394 ntclkbufg_0 - CLMA_70_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK - - CLMA_70_192/Q0 tco 0.289 11.683 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q - net (fanout=619) 1.655 13.338 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n - CLMA_10_224/RSCO td 0.147 13.485 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=4) 0.000 13.485 ntR1395 - CLMA_10_228/RSCO td 0.147 13.632 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[4]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=4) 0.000 13.632 ntR1394 - CLMA_10_232/RSCO td 0.147 13.779 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=4) 0.000 13.779 ntR1393 - CLMA_10_236/RSCO td 0.147 13.926 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[2]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=6) 0.000 13.926 ntR1392 - CLMA_10_240/RSCO td 0.147 14.073 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[246]/opit_0_inv/RSOUT - net (fanout=4) 0.000 14.073 ntR1391 - CLMA_10_244/RSCO td 0.147 14.220 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q_perm/RSOUT - net (fanout=2) 0.000 14.220 ntR1390 - CLMA_10_248/RSCO td 0.147 14.367 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[4]/opit_0_inv_A2Q21/RSOUT - net (fanout=3) 0.000 14.367 ntR1389 - CLMA_10_252/RSCO td 0.147 14.514 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/opit_0_inv_AQ_perm/RSOUT - net (fanout=4) 0.000 14.514 ntR1388 - CLMA_10_256/RSCO td 0.147 14.661 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=2) 0.000 14.661 ntR1387 - CLMA_10_260/RSCO td 0.147 14.808 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=2) 0.000 14.808 ntR1386 - CLMA_10_264/RSCO td 0.147 14.955 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[4]/opit_0_inv_A2Q21/RSOUT - net (fanout=3) 0.000 14.955 ntR1385 - CLMA_10_268/RSCO td 0.147 15.102 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/opit_0_inv_AQ/RSOUT - net (fanout=3) 0.000 15.102 ntR1384 - CLMA_10_272/RSCO td 0.147 15.249 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs/opit_0_inv/RSOUT - net (fanout=2) 0.000 15.249 ntR1383 - CLMA_10_276/RSCO td 0.147 15.396 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[3]/opit_0_inv_A2Q21/RSOUT - net (fanout=2) 0.000 15.396 ntR1382 - CLMA_10_280/RSCO td 0.147 15.543 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[7]/opit_0_inv_A2Q21/RSOUT - net (fanout=4) 0.000 15.543 ntR1381 - CLMA_10_284/RSCO td 0.147 15.690 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=4) 0.000 15.690 ntR1380 - CLMA_10_288/RSCO td 0.147 15.837 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[223]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=6) 0.000 15.837 ntR1379 - CLMA_10_292/RSCI f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[60]/opit_0_inv/RS - - Data arrival time 15.837 Logic Levels: 17 - Logic: 2.788ns(62.750%), Route: 1.655ns(37.250%) + CLMA_46_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK + + CLMA_46_192/Q0 tco 0.289 11.683 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q + net (fanout=729) 1.497 13.180 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n + CLMA_34_148/RSCO td 0.147 13.327 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[2]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=4) 0.000 13.327 ntR882 + CLMA_34_152/RSCO td 0.147 13.474 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[5]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=4) 0.000 13.474 ntR881 + CLMA_34_156/RSCO td 0.147 13.621 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_we_n_d[0]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=4) 0.000 13.621 ntR880 + CLMA_34_160/RSCO td 0.147 13.768 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cs_n_d[0]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=2) 0.000 13.768 ntR879 + CLMA_34_164/RSCO td 0.147 13.915 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[4]/opit_0_inv_A2Q21/RSOUT + net (fanout=3) 0.000 13.915 ntR878 + CLMA_34_168/RSCO td 0.147 14.062 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[0]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=6) 0.000 14.062 ntR877 + CLMA_34_172/RSCO td 0.147 14.209 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_r[1]/opit_0_inv/RSOUT + net (fanout=5) 0.000 14.209 ntR876 + CLMA_34_176/RSCO td 0.147 14.356 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=2) 0.000 14.356 ntR875 + CLMA_34_180/RSCO td 0.147 14.503 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[4]/opit_0_inv_A2Q21/RSOUT + net (fanout=2) 0.000 14.503 ntR874 + CLMA_34_184/RSCO td 0.147 14.650 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[8]/opit_0_inv_A2Q21/RSOUT + net (fanout=2) 0.000 14.650 ntR873 + CLMA_34_192/RSCO td 0.147 14.797 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[12]/opit_0_inv_A2Q21/RSOUT + net (fanout=2) 0.000 14.797 ntR872 + CLMA_34_196/RSCO td 0.147 14.944 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[16]/opit_0_inv_A2Q21/RSOUT + net (fanout=1) 0.000 14.944 ntR871 + CLMA_34_200/RSCO td 0.147 15.091 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[17]/opit_0_inv_AQ_perm/RSOUT + net (fanout=6) 0.000 15.091 ntR870 + CLMA_34_204/RSCO td 0.147 15.238 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[1]/opit_0_inv/RSOUT + net (fanout=5) 0.000 15.238 ntR869 + CLMA_34_208/RSCO td 0.147 15.385 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[238]/opit_0_inv/RSOUT + net (fanout=5) 0.000 15.385 ntR868 + CLMA_34_212/RSCO td 0.147 15.532 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[86]/opit_0_inv/RSOUT + net (fanout=5) 0.000 15.532 ntR867 + CLMA_34_216/RSCI f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[116]/opit_0_inv/RS + + Data arrival time 15.532 Logic Levels: 16 + Logic: 2.641ns(63.823%), Route: 1.497ns(36.177%) ---------------------------------------------------------------------------------------------------- Clock ddrphy_clkin (rising edge) 10.000 10.000 r @@ -7235,35 +8060,35 @@ Clock Skew : 0.067 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.048 11.930 r clk_ibuf/opit_1/INCK net (fanout=1) 0.758 12.688 _N69 PLL_158_55/CLK_OUT1 td 0.096 12.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.059 13.843 zoom_clk + net (fanout=2) 1.059 13.843 ddr_clk USCM_84_113/CLK_USCM td 0.000 13.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.665 15.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.665 15.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.123 15.631 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.102 16.733 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.249 16.982 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.249 16.982 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 16.982 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 16.982 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 2.152 19.134 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 19.134 r clkbufg_0/gopclkbufg/CLKOUT - net (fanout=5464) 1.652 20.786 ntclkbufg_0 - CLMA_10_292/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[60]/opit_0_inv/CLK - clock pessimism 0.675 21.461 - clock uncertainty -0.150 21.311 + net (fanout=5464) 1.531 20.665 ntclkbufg_0 + CLMA_34_216/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[116]/opit_0_inv/CLK + clock pessimism 0.693 21.358 + clock uncertainty -0.150 21.208 - Recovery time 0.000 21.311 + Recovery time 0.000 21.208 - Data required time 21.311 + Data required time 21.208 ---------------------------------------------------------------------------------------------------- - Data required time 21.311 - Data arrival time 15.837 + Data required time 21.208 + Data arrival time 15.532 ---------------------------------------------------------------------------------------------------- - Slack (MET) 5.474 + Slack (MET) 5.676 ==================================================================================================== ==================================================================================================== Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK -Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[151]/opit_0_inv/RS +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[6]/opit_0_inv_L5Q_perm/RS Path Group : ddrphy_clkin Path Type : min (slow corner) Path Class : async timing path @@ -7283,27 +8108,27 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK net (fanout=1) 0.758 2.688 _N69 PLL_158_55/CLK_OUT1 td 0.096 2.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.059 3.843 zoom_clk + net (fanout=2) 1.059 3.843 ddr_clk USCM_84_113/CLK_USCM td 0.000 3.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.123 5.631 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.102 6.733 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.249 6.982 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.249 6.982 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 6.982 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 6.982 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 2.152 9.134 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 9.134 r clkbufg_0/gopclkbufg/CLKOUT net (fanout=5464) 1.531 10.665 ntclkbufg_0 - CLMA_70_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK + CLMA_46_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK - CLMA_70_192/Q0 tco 0.222 10.887 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q - net (fanout=619) 0.488 11.375 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n - CLMA_66_212/RSCO td 0.105 11.480 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[37]/opit_0_inv/RSOUT - net (fanout=4) 0.000 11.480 ntR1484 - CLMA_66_216/RSCI r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[151]/opit_0_inv/RS + CLMA_46_192/Q0 tco 0.222 10.887 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q + net (fanout=729) 0.346 11.233 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n + CLMA_38_192/RSCO td 0.105 11.338 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[57]/opit_0_inv/RSOUT + net (fanout=4) 0.000 11.338 ntR984 + CLMA_38_196/RSCI r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[6]/opit_0_inv_L5Q_perm/RS - Data arrival time 11.480 Logic Levels: 1 - Logic: 0.327ns(40.123%), Route: 0.488ns(59.877%) + Data arrival time 11.338 Logic Levels: 1 + Logic: 0.327ns(48.588%), Route: 0.346ns(51.412%) ---------------------------------------------------------------------------------------------------- Clock ddrphy_clkin (rising edge) 0.000 0.000 r @@ -7314,18 +8139,18 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.078 4.282 zoom_clk + net (fanout=2) 1.078 4.282 ddr_clk USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.121 7.270 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 7.618 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 2.191 9.809 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 9.809 r clkbufg_0/gopclkbufg/CLKOUT net (fanout=5464) 1.585 11.394 ntclkbufg_0 - CLMA_66_216/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[151]/opit_0_inv/CLK + CLMA_38_196/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[6]/opit_0_inv_L5Q_perm/CLK clock pessimism -0.693 10.701 clock uncertainty 0.000 10.701 @@ -7334,15 +8159,15 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim Data required time 10.701 ---------------------------------------------------------------------------------------------------- Data required time 10.701 - Data arrival time 11.480 + Data arrival time 11.338 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.779 + Slack (MET) 0.637 ==================================================================================================== ==================================================================================================== Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK -Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[2]/opit_0_inv/RS +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[7]/opit_0_inv_L5Q_perm/RS Path Group : ddrphy_clkin Path Type : min (slow corner) Path Class : async timing path @@ -7362,27 +8187,27 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK net (fanout=1) 0.758 2.688 _N69 PLL_158_55/CLK_OUT1 td 0.096 2.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.059 3.843 zoom_clk + net (fanout=2) 1.059 3.843 ddr_clk USCM_84_113/CLK_USCM td 0.000 3.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.123 5.631 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.102 6.733 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.249 6.982 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.249 6.982 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 6.982 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 6.982 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 2.152 9.134 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 9.134 r clkbufg_0/gopclkbufg/CLKOUT net (fanout=5464) 1.531 10.665 ntclkbufg_0 - CLMA_70_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK + CLMA_46_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK - CLMA_70_192/Q0 tco 0.222 10.887 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q - net (fanout=619) 0.488 11.375 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n - CLMA_66_212/RSCO td 0.105 11.480 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[37]/opit_0_inv/RSOUT - net (fanout=4) 0.000 11.480 ntR1484 - CLMA_66_216/RSCI r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[2]/opit_0_inv/RS + CLMA_46_192/Q0 tco 0.222 10.887 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q + net (fanout=729) 0.346 11.233 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n + CLMA_38_192/RSCO td 0.105 11.338 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[57]/opit_0_inv/RSOUT + net (fanout=4) 0.000 11.338 ntR984 + CLMA_38_196/RSCI r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[7]/opit_0_inv_L5Q_perm/RS - Data arrival time 11.480 Logic Levels: 1 - Logic: 0.327ns(40.123%), Route: 0.488ns(59.877%) + Data arrival time 11.338 Logic Levels: 1 + Logic: 0.327ns(48.588%), Route: 0.346ns(51.412%) ---------------------------------------------------------------------------------------------------- Clock ddrphy_clkin (rising edge) 0.000 0.000 r @@ -7393,18 +8218,18 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.078 4.282 zoom_clk + net (fanout=2) 1.078 4.282 ddr_clk USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.121 7.270 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 7.618 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 2.191 9.809 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 9.809 r clkbufg_0/gopclkbufg/CLKOUT net (fanout=5464) 1.585 11.394 ntclkbufg_0 - CLMA_66_216/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[2]/opit_0_inv/CLK + CLMA_38_196/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[7]/opit_0_inv_L5Q_perm/CLK clock pessimism -0.693 10.701 clock uncertainty 0.000 10.701 @@ -7413,15 +8238,15 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim Data required time 10.701 ---------------------------------------------------------------------------------------------------- Data required time 10.701 - Data arrival time 11.480 + Data arrival time 11.338 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.779 + Slack (MET) 0.637 ==================================================================================================== ==================================================================================================== Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK -Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[3]/opit_0_inv/RS +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[8]/opit_0_inv_L5Q_perm/RS Path Group : ddrphy_clkin Path Type : min (slow corner) Path Class : async timing path @@ -7441,27 +8266,27 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.048 1.930 r clk_ibuf/opit_1/INCK net (fanout=1) 0.758 2.688 _N69 PLL_158_55/CLK_OUT1 td 0.096 2.784 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.059 3.843 zoom_clk + net (fanout=2) 1.059 3.843 ddr_clk USCM_84_113/CLK_USCM td 0.000 3.843 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.665 5.508 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.123 5.631 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.102 6.733 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.249 6.982 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.249 6.982 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 6.982 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 6.982 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 2.152 9.134 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 9.134 r clkbufg_0/gopclkbufg/CLKOUT net (fanout=5464) 1.531 10.665 ntclkbufg_0 - CLMA_70_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK + CLMA_46_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK - CLMA_70_192/Q0 tco 0.222 10.887 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q - net (fanout=619) 0.488 11.375 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n - CLMA_66_212/RSCO td 0.105 11.480 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[37]/opit_0_inv/RSOUT - net (fanout=4) 0.000 11.480 ntR1484 - CLMA_66_216/RSCI r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[3]/opit_0_inv/RS + CLMA_46_192/Q0 tco 0.222 10.887 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q + net (fanout=729) 0.346 11.233 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n + CLMA_38_192/RSCO td 0.105 11.338 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[57]/opit_0_inv/RSOUT + net (fanout=4) 0.000 11.338 ntR984 + CLMA_38_196/RSCI r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[8]/opit_0_inv_L5Q_perm/RS - Data arrival time 11.480 Logic Levels: 1 - Logic: 0.327ns(40.123%), Route: 0.488ns(59.877%) + Data arrival time 11.338 Logic Levels: 1 + Logic: 0.327ns(48.588%), Route: 0.346ns(51.412%) ---------------------------------------------------------------------------------------------------- Clock ddrphy_clkin (rising edge) 0.000 0.000 r @@ -7472,18 +8297,18 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.078 4.282 zoom_clk + net (fanout=2) 1.078 4.282 ddr_clk USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.121 7.270 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 7.618 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 2.191 9.809 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 9.809 r clkbufg_0/gopclkbufg/CLKOUT net (fanout=5464) 1.585 11.394 ntclkbufg_0 - CLMA_66_216/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[3]/opit_0_inv/CLK + CLMA_38_196/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[8]/opit_0_inv_L5Q_perm/CLK clock pessimism -0.693 10.701 clock uncertainty 0.000 10.701 @@ -7492,14 +8317,14 @@ Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessim Data required time 10.701 ---------------------------------------------------------------------------------------------------- Data required time 10.701 - Data arrival time 11.480 + Data arrival time 11.338 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.779 + Slack (MET) 0.637 ==================================================================================================== ==================================================================================================== -Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/calib_done/opit_0_inv_MUX4TO1Q/CLK +Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_rst/opit_0_inv/CLK Endpoint : mem_rst_n (port) Path Group : **default** Path Type : max (slow corner) @@ -7516,37 +8341,37 @@ Path Class : combinational timing path IOL_327_210/INCK td 0.076 2.316 r clk_ibuf/opit_1/INCK net (fanout=1) 0.787 3.103 _N69 PLL_158_55/CLK_OUT1 td 0.101 3.204 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 1.078 4.282 zoom_clk + net (fanout=2) 1.078 4.282 ddr_clk USCM_84_113/CLK_USCM td 0.000 4.282 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.738 6.020 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.129 6.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 1.121 7.270 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.348 7.618 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 7.618 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 7.618 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 2.191 9.809 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 9.809 r clkbufg_0/gopclkbufg/CLKOUT net (fanout=5464) 1.585 11.394 ntclkbufg_0 - CLMS_46_173/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/calib_done/opit_0_inv_MUX4TO1Q/CLK - - CLMS_46_173/Q1 tco 0.289 11.683 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/calib_done/opit_0_inv_MUX4TO1Q/Q - net (fanout=575) 2.425 14.108 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/calib_done - CLMS_18_317/Y0 td 0.196 14.304 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/N48/gateop_perm/Z - net (fanout=1) 1.113 15.417 nt_mem_rst_n - IOL_7_369/DO td 0.139 15.556 f mem_rst_n_obuf/opit_1/O - net (fanout=1) 0.000 15.556 mem_rst_n_obuf/ntO - IOBS_LR_0_368/PAD td 3.903 19.459 f mem_rst_n_obuf/opit_0/O - net (fanout=1) 0.096 19.555 mem_rst_n + CLMA_46_156/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_rst/opit_0_inv/CLK + + CLMA_46_156/Q0 tco 0.289 11.683 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_rst/opit_0_inv/Q + net (fanout=1) 0.760 12.443 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/calib_rst + CLMS_34_173/Y3 td 0.197 12.640 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/N48/gateop_perm/Z + net (fanout=1) 2.439 15.079 nt_mem_rst_n + IOL_7_369/DO td 0.139 15.218 f mem_rst_n_obuf/opit_1/O + net (fanout=1) 0.000 15.218 mem_rst_n_obuf/ntO + IOBS_LR_0_368/PAD td 3.903 19.121 f mem_rst_n_obuf/opit_0/O + net (fanout=1) 0.096 19.217 mem_rst_n C1 f mem_rst_n (port) - Data arrival time 19.555 Logic Levels: 3 - Logic: 4.527ns(55.471%), Route: 3.634ns(44.529%) + Data arrival time 19.217 Logic Levels: 3 + Logic: 4.528ns(57.881%), Route: 3.295ns(42.119%) ==================================================================================================== ==================================================================================================== -Startpoint : param_manager_inst/index[1]/opit_0_L5Q_perm/CLK -Endpoint : led[2] (port) +Startpoint : param_manager_inst/index[0]/opit_0_L5Q_perm/CLK +Endpoint : led[1] (port) Path Group : **default** Path Type : max (slow corner) Path Class : combinational timing path @@ -7564,25 +8389,25 @@ Path Class : combinational timing path IOCKDLY_237_367/CLK_OUT td 3.812 5.846 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT net (fanout=1) 2.599 8.445 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf USCM_84_109/CLK_USCM td 0.000 8.445 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - net (fanout=1861) 1.585 10.030 gmii_clk - CLMA_194_168/CLK r param_manager_inst/index[1]/opit_0_L5Q_perm/CLK - - CLMA_194_168/Q3 tco 0.286 10.316 f param_manager_inst/index[1]/opit_0_L5Q_perm/Q - net (fanout=19) 3.743 14.059 nt_led[2] - IOL_19_373/DO td 0.139 14.198 f led_obuf[2]/opit_1/O - net (fanout=1) 0.000 14.198 led_obuf[2]/ntO - IOBS_TB_17_376/PAD td 3.853 18.051 f led_obuf[2]/opit_0/O - net (fanout=1) 0.107 18.158 led[2] - A2 f led[2] (port) + net (fanout=1862) 1.585 10.030 gmii_clk + CLMA_210_205/CLK r param_manager_inst/index[0]/opit_0_L5Q_perm/CLK - Data arrival time 18.158 Logic Levels: 2 - Logic: 4.278ns(52.633%), Route: 3.850ns(47.367%) + CLMA_210_205/Q0 tco 0.287 10.317 f param_manager_inst/index[0]/opit_0_L5Q_perm/Q + net (fanout=20) 3.794 14.111 nt_led[1] + IOL_19_374/DO td 0.139 14.250 f led_obuf[1]/opit_1/O + net (fanout=1) 0.000 14.250 led_obuf[1]/ntO + IOBD_16_376/PAD td 3.853 18.103 f led_obuf[1]/opit_0/O + net (fanout=1) 0.109 18.212 led[1] + B2 f led[1] (port) + + Data arrival time 18.212 Logic Levels: 2 + Logic: 4.279ns(52.298%), Route: 3.903ns(47.702%) ==================================================================================================== ==================================================================================================== -Startpoint : param_manager_inst/index[3]/opit_0_L5Q_perm/CLK -Endpoint : led[4] (port) +Startpoint : param_manager_inst/index[1]/opit_0_L5Q_perm/CLK +Endpoint : led[2] (port) Path Group : **default** Path Type : max (slow corner) Path Class : combinational timing path @@ -7600,19 +8425,19 @@ Path Class : combinational timing path IOCKDLY_237_367/CLK_OUT td 3.812 5.846 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT net (fanout=1) 2.599 8.445 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf USCM_84_109/CLK_USCM td 0.000 8.445 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - net (fanout=1861) 1.585 10.030 gmii_clk - CLMA_194_168/CLK r param_manager_inst/index[3]/opit_0_L5Q_perm/CLK - - CLMA_194_168/Q1 tco 0.289 10.319 f param_manager_inst/index[3]/opit_0_L5Q_perm/Q - net (fanout=18) 3.675 13.994 nt_led[4] - IOL_35_373/DO td 0.139 14.133 f led_obuf[4]/opit_1/O - net (fanout=1) 0.000 14.133 led_obuf[4]/ntO - IOBS_TB_33_376/PAD td 3.853 17.986 f led_obuf[4]/opit_0/O - net (fanout=1) 0.087 18.073 led[4] - A3 f led[4] (port) + net (fanout=1862) 1.585 10.030 gmii_clk + CLMA_210_205/CLK r param_manager_inst/index[1]/opit_0_L5Q_perm/CLK + + CLMA_210_205/Q3 tco 0.286 10.316 f param_manager_inst/index[1]/opit_0_L5Q_perm/Q + net (fanout=19) 3.663 13.979 nt_led[2] + IOL_19_373/DO td 0.139 14.118 f led_obuf[2]/opit_1/O + net (fanout=1) 0.000 14.118 led_obuf[2]/ntO + IOBS_TB_17_376/PAD td 3.853 17.971 f led_obuf[2]/opit_0/O + net (fanout=1) 0.107 18.078 led[2] + A2 f led[2] (port) - Data arrival time 18.073 Logic Levels: 2 - Logic: 4.281ns(53.226%), Route: 3.762ns(46.774%) + Data arrival time 18.078 Logic Levels: 2 + Logic: 4.278ns(53.156%), Route: 3.770ns(46.844%) ==================================================================================================== ==================================================================================================== @@ -7685,35 +8510,35 @@ Path Class : combinational timing path **************************************************************************************************** Slack Actual Width Require Width Type Location Pin ---------------------------------------------------------------------------------------------------- - 5.052 5.950 0.898 Low Pulse Width DRM_142_24/CLKA[0] u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] - 5.052 5.950 0.898 High Pulse Width DRM_142_24/CLKA[0] u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] - 5.330 5.950 0.620 High Pulse Width CLMS_146_9/CLK u_ov5640/cmos1_8_16bit/de_in0/opit_0/CLK + 5.052 5.950 0.898 Low Pulse Width DRM_142_44/CLKA[0] u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] + 5.052 5.950 0.898 High Pulse Width DRM_142_44/CLKA[0] u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] + 5.330 5.950 0.620 Low Pulse Width CLMS_134_25/CLK u_ov5640/cmos1_8_16bit/de_cnt/opit_0_L5Q_perm/CLK ==================================================================================================== {cmos2_pclk} Minimum Pulse Width : **************************************************************************************************** Slack Actual Width Require Width Type Location Pin ---------------------------------------------------------------------------------------------------- - 5.052 5.950 0.898 Low Pulse Width DRM_142_44/CLKA[0] u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] - 5.052 5.950 0.898 High Pulse Width DRM_142_44/CLKA[0] u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] - 5.330 5.950 0.620 Low Pulse Width CLMS_150_41/CLK u_ov5640/cmos2_8_16bit/de_cnt/opit_0_L5Q/CLK + 5.052 5.950 0.898 Low Pulse Width DRM_142_24/CLKA[0] u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] + 5.052 5.950 0.898 High Pulse Width DRM_142_24/CLKA[0] u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] + 5.330 5.950 0.620 High Pulse Width CLMS_74_17/CLK u_ov5640/cmos2_8_16bit/de_in0/opit_0/CLK ==================================================================================================== {hdmi_in_clk} Minimum Pulse Width : **************************************************************************************************** Slack Actual Width Require Width Type Location Pin ---------------------------------------------------------------------------------------------------- - 2.435 3.333 0.898 Low Pulse Width DRM_82_108/CLKA[0] u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] - 2.435 3.333 0.898 High Pulse Width DRM_82_108/CLKA[0] u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] - 2.435 3.333 0.898 High Pulse Width DRM_54_108/CLKA[0] u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] + 2.435 3.333 0.898 Low Pulse Width DRM_82_128/CLKA[0] u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] + 2.435 3.333 0.898 High Pulse Width DRM_82_128/CLKA[0] u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] + 2.435 3.333 0.898 Low Pulse Width DRM_82_88/CLKA[0] u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] ==================================================================================================== {eth_rxc} Minimum Pulse Width : **************************************************************************************************** Slack Actual Width Require Width Type Location Pin ---------------------------------------------------------------------------------------------------- - 2.483 4.000 1.517 High Pulse Width IOL_71_373/CLK_SYS udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_ctl_in/gateigddr_IOL/SYSCLK 2.483 4.000 1.517 Low Pulse Width IOL_71_373/CLK_SYS udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_ctl_in/gateigddr_IOL/SYSCLK + 2.483 4.000 1.517 High Pulse Width IOL_71_373/CLK_SYS udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_ctl_in/gateigddr_IOL/SYSCLK 2.483 4.000 1.517 Low Pulse Width IOL_311_374/CLK_SYS udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gtp_outbuft1/opit_1_IOL/SYSCLK ==================================================================================================== @@ -7721,63 +8546,72 @@ Path Class : combinational timing path **************************************************************************************************** Slack Actual Width Require Width Type Location Pin ---------------------------------------------------------------------------------------------------- - 8.862 10.000 1.138 High Pulse Width APM_106_116/CLK u_rotate_image/u_rotate_mult0/N2/gopapm/CLK - 8.862 10.000 1.138 Low Pulse Width APM_106_116/CLK u_rotate_image/u_rotate_mult0/N2/gopapm/CLK - 8.862 10.000 1.138 High Pulse Width APM_106_104/CLK u_rotate_image/u_rotate_mult1/N2/gopapm/CLK + 8.862 10.000 1.138 Low Pulse Width APM_206_228/CLK u_rotate_image/u_rotate_mult0/N2/gopapm/CLK + 8.862 10.000 1.138 High Pulse Width APM_206_228/CLK u_rotate_image/u_rotate_mult0/N2/gopapm/CLK + 8.862 10.000 1.138 High Pulse Width APM_206_216/CLK u_rotate_image/u_rotate_mult1/N2/gopapm/CLK ==================================================================================================== {clk_200m} Minimum Pulse Width : **************************************************************************************************** Slack Actual Width Require Width Type Location Pin ---------------------------------------------------------------------------------------------------- - 1.362 2.500 1.138 Low Pulse Width APM_206_228/CLK u_zoom_image/mult_fra0/N2/gopapm/CLK - 1.362 2.500 1.138 High Pulse Width APM_206_228/CLK u_zoom_image/mult_fra0/N2/gopapm/CLK - 1.362 2.500 1.138 Low Pulse Width APM_206_140/CLK u_zoom_image/mult_fra0_0/N2/gopapm/CLK + 1.880 2.500 0.620 Low Pulse Width CLMS_34_181/CLK u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[0]/opit_0_inv_L5Q_perm/CLK + 1.880 2.500 0.620 High Pulse Width CLMS_34_181/CLK u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[0]/opit_0_inv_L5Q_perm/CLK + 1.880 2.500 0.620 High Pulse Width CLMS_34_193/CLK u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[1]/opit_0_inv_L5Q_perm/CLK ==================================================================================================== {clk_25m} Minimum Pulse Width : **************************************************************************************************** Slack Actual Width Require Width Type Location Pin ---------------------------------------------------------------------------------------------------- - 19.580 20.000 0.420 High Pulse Width CLMA_182_12/CLK u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK - 19.580 20.000 0.420 Low Pulse Width CLMA_182_12/CLK u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK - 19.580 20.000 0.420 High Pulse Width CLMA_182_12/CLK u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/CLK + 19.380 20.000 0.620 High Pulse Width CLMS_122_9/CLK u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK + 19.380 20.000 0.620 Low Pulse Width CLMS_122_9/CLK u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK + 19.380 20.000 0.620 High Pulse Width CLMS_122_9/CLK u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/CLK ==================================================================================================== {clk_10m} Minimum Pulse Width : **************************************************************************************************** Slack Actual Width Require Width Type Location Pin ---------------------------------------------------------------------------------------------------- - 49.102 50.000 0.898 Low Pulse Width DRM_234_108/CLKA[0] ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKA[0] - 49.102 50.000 0.898 High Pulse Width DRM_234_108/CLKA[0] ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKA[0] - 49.102 50.000 0.898 Low Pulse Width DRM_234_108/CLKB[0] ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKB[0] + 49.102 50.000 0.898 Low Pulse Width DRM_234_316/CLKA[0] ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKA[0] + 49.102 50.000 0.898 High Pulse Width DRM_234_316/CLKA[0] ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKA[0] + 49.102 50.000 0.898 Low Pulse Width DRM_234_316/CLKB[0] ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKB[0] +==================================================================================================== + +{clk_1080p60Hz} Minimum Pulse Width : +**************************************************************************************************** + Slack Actual Width Require Width Type Location Pin +---------------------------------------------------------------------------------------------------- + 2.230 3.368 1.138 High Pulse Width APM_206_28/CLK u_zoom_image/mult_fra0/N2/gopapm/CLK + 2.230 3.368 1.138 Low Pulse Width APM_206_28/CLK u_zoom_image/mult_fra0/N2/gopapm/CLK + 2.230 3.368 1.138 High Pulse Width APM_206_264/CLK u_zoom_image/mult_fra0_0/N2/gopapm/CLK ==================================================================================================== {clk_720p60Hz} Minimum Pulse Width : **************************************************************************************************** Slack Actual Width Require Width Type Location Pin ---------------------------------------------------------------------------------------------------- - 5.598 6.736 1.138 High Pulse Width APM_258_140/CLK adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N11/gopapm/CLK - 5.598 6.736 1.138 High Pulse Width APM_258_128/CLK adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N135/gopapm/CLK - 5.599 6.737 1.138 Low Pulse Width APM_258_140/CLK adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N11/gopapm/CLK + 5.598 6.736 1.138 High Pulse Width APM_258_216/CLK adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N11/gopapm/CLK + 5.598 6.736 1.138 High Pulse Width APM_258_204/CLK adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N135/gopapm/CLK + 5.599 6.737 1.138 Low Pulse Width APM_258_216/CLK adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N11/gopapm/CLK ==================================================================================================== {clk_20k} Minimum Pulse Width : **************************************************************************************************** Slack Actual Width Require Width Type Location Pin ---------------------------------------------------------------------------------------------------- - 24999.102 25000.000 0.898 Low Pulse Width DRM_178_4/CLKA[0] u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKA[0] - 24999.102 25000.000 0.898 High Pulse Width DRM_178_4/CLKA[0] u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKA[0] - 24999.102 25000.000 0.898 Low Pulse Width DRM_178_4/CLKB[0] u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0] + 24999.102 25000.000 0.898 Low Pulse Width DRM_142_4/CLKA[0] u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKA[0] + 24999.102 25000.000 0.898 High Pulse Width DRM_142_4/CLKA[0] u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKA[0] + 24999.102 25000.000 0.898 Low Pulse Width DRM_142_4/CLKB[0] u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0] ==================================================================================================== {ddrphy_clkin} Minimum Pulse Width : **************************************************************************************************** Slack Actual Width Require Width Type Location Pin ---------------------------------------------------------------------------------------------------- - 3.100 5.000 1.900 High Pulse Width CLMS_38_109/CLK u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram16x1d/WCLK - 3.100 5.000 1.900 Low Pulse Width CLMS_38_109/CLK u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram16x1d/WCLK - 3.100 5.000 1.900 High Pulse Width CLMS_34_113/CLK u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_2/ram16x1d/WCLK + 3.100 5.000 1.900 Low Pulse Width CLMS_38_101/CLK u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram16x1d/WCLK + 3.100 5.000 1.900 High Pulse Width CLMS_38_101/CLK u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram16x1d/WCLK + 3.100 5.000 1.900 Low Pulse Width CLMS_42_101/CLK u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_2/ram16x1d/WCLK ==================================================================================================== {ioclk0} Minimum Pulse Width : @@ -7820,8 +8654,8 @@ Fast Corner **************************************************************************************************** ==================================================================================================== -Startpoint : cmos1_data[4] (port) -Endpoint : u_ov5640/cmos1_d_d0[4]/opit_0/D +Startpoint : cmos1_href (port) +Endpoint : u_ov5640/cmos1_href_d0/opit_0/D Path Group : cmos1_pclk Path Type : max (fast corner) Path Class : sequential timing path @@ -7836,16 +8670,16 @@ Clock Skew : 3.172 (Capture Clock Delay - Launch Clock Delay + Clock Pessim Clock cmos1_pclk (rising edge) 0.000 0.000 r Input external delay 1.000 1.000 f - W11 0.000 1.000 f cmos1_data[4] (port) - net (fanout=1) 0.041 1.041 cmos1_data[4] - IOBS_TB_132_0/DIN td 1.049 2.090 f cmos1_data_ibuf[4]/opit_0/O - net (fanout=1) 0.000 2.090 cmos1_data_ibuf[4]/ntD - IOL_135_5/RX_DATA_DD td 0.097 2.187 f cmos1_data_ibuf[4]/opit_1/OUT - net (fanout=1) 5.898 8.085 nt_cmos1_data[4] - CLMS_134_13/AD f u_ov5640/cmos1_d_d0[4]/opit_0/D + AB10 0.000 1.000 f cmos1_href (port) + net (fanout=1) 0.063 1.063 cmos1_href + IOBR_TB_148_0/DIN td 0.918 1.981 f cmos1_href_ibuf/opit_0/O + net (fanout=1) 0.000 1.981 cmos1_href_ibuf/ntD + IOL_151_5/RX_DATA_DD td 0.097 2.078 f cmos1_href_ibuf/opit_1/OUT + net (fanout=1) 6.241 8.319 nt_cmos1_href + CLMA_150_12/M1 f u_ov5640/cmos1_href_d0/opit_0/D - Data arrival time 8.085 Logic Levels: 2 - Logic: 1.146ns(16.175%), Route: 5.939ns(83.825%) + Data arrival time 8.319 Logic Levels: 2 + Logic: 1.015ns(13.868%), Route: 6.304ns(86.132%) ---------------------------------------------------------------------------------------------------- Clock cmos1_pclk (rising edge) 11.900 11.900 r @@ -7855,26 +8689,26 @@ Clock Skew : 3.172 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.000 12.711 cmos1_pclk_ibuf/ntD IOL_171_6/INCK td 0.038 12.749 r cmos1_pclk_ibuf/opit_1/INCK net (fanout=1) 1.428 14.177 _N64 - USCM_84_112/CLK_USCM td 0.000 14.177 r clkbufg_5/gopclkbufg/CLKOUT - net (fanout=118) 0.895 15.072 ntclkbufg_5 - CLMS_134_13/CLK r u_ov5640/cmos1_d_d0[4]/opit_0/CLK + USCM_84_112/CLK_USCM td 0.000 14.177 r clkbufg_6/gopclkbufg/CLKOUT + net (fanout=118) 0.895 15.072 ntclkbufg_6 + CLMA_150_12/CLK r u_ov5640/cmos1_href_d0/opit_0/CLK clock pessimism 0.000 15.072 clock uncertainty -0.250 14.822 - Setup time 0.024 14.846 + Setup time -0.068 14.754 - Data required time 14.846 + Data required time 14.754 ---------------------------------------------------------------------------------------------------- - Data required time 14.846 - Data arrival time 8.085 + Data required time 14.754 + Data arrival time 8.319 ---------------------------------------------------------------------------------------------------- - Slack (MET) 6.761 + Slack (MET) 6.435 ==================================================================================================== ==================================================================================================== -Startpoint : cmos1_href (port) -Endpoint : u_ov5640/cmos1_href_d0/opit_0/D +Startpoint : cmos1_data[0] (port) +Endpoint : u_ov5640/cmos1_d_d0[0]/opit_0/D Path Group : cmos1_pclk Path Type : max (fast corner) Path Class : sequential timing path @@ -7889,16 +8723,16 @@ Clock Skew : 3.172 (Capture Clock Delay - Launch Clock Delay + Clock Pessim Clock cmos1_pclk (rising edge) 0.000 0.000 r Input external delay 1.000 1.000 f - AB10 0.000 1.000 f cmos1_href (port) - net (fanout=1) 0.063 1.063 cmos1_href - IOBR_TB_148_0/DIN td 0.918 1.981 f cmos1_href_ibuf/opit_0/O - net (fanout=1) 0.000 1.981 cmos1_href_ibuf/ntD - IOL_151_5/RX_DATA_DD td 0.097 2.078 f cmos1_href_ibuf/opit_1/OUT - net (fanout=1) 5.930 8.008 nt_cmos1_href - CLMS_146_9/AD f u_ov5640/cmos1_href_d0/opit_0/D + V11 0.000 1.000 f cmos1_data[0] (port) + net (fanout=1) 0.053 1.053 cmos1_data[0] + IOBD_133_0/DIN td 1.049 2.102 f cmos1_data_ibuf[0]/opit_0/O + net (fanout=1) 0.000 2.102 cmos1_data_ibuf[0]/ntD + IOL_135_6/RX_DATA_DD td 0.097 2.199 f cmos1_data_ibuf[0]/opit_1/OUT + net (fanout=1) 5.534 7.733 nt_cmos1_data[0] + CLMS_134_45/CD f u_ov5640/cmos1_d_d0[0]/opit_0/D - Data arrival time 8.008 Logic Levels: 2 - Logic: 1.015ns(14.483%), Route: 5.993ns(85.517%) + Data arrival time 7.733 Logic Levels: 2 + Logic: 1.146ns(17.021%), Route: 5.587ns(82.979%) ---------------------------------------------------------------------------------------------------- Clock cmos1_pclk (rising edge) 11.900 11.900 r @@ -7908,9 +8742,9 @@ Clock Skew : 3.172 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.000 12.711 cmos1_pclk_ibuf/ntD IOL_171_6/INCK td 0.038 12.749 r cmos1_pclk_ibuf/opit_1/INCK net (fanout=1) 1.428 14.177 _N64 - USCM_84_112/CLK_USCM td 0.000 14.177 r clkbufg_5/gopclkbufg/CLKOUT - net (fanout=118) 0.895 15.072 ntclkbufg_5 - CLMS_146_9/CLK r u_ov5640/cmos1_href_d0/opit_0/CLK + USCM_84_112/CLK_USCM td 0.000 14.177 r clkbufg_6/gopclkbufg/CLKOUT + net (fanout=118) 0.895 15.072 ntclkbufg_6 + CLMS_134_45/CLK r u_ov5640/cmos1_d_d0[0]/opit_0/CLK clock pessimism 0.000 15.072 clock uncertainty -0.250 14.822 @@ -7919,15 +8753,15 @@ Clock Skew : 3.172 (Capture Clock Delay - Launch Clock Delay + Clock Pessim Data required time 14.846 ---------------------------------------------------------------------------------------------------- Data required time 14.846 - Data arrival time 8.008 + Data arrival time 7.733 ---------------------------------------------------------------------------------------------------- - Slack (MET) 6.838 + Slack (MET) 7.113 ==================================================================================================== ==================================================================================================== -Startpoint : cmos1_data[5] (port) -Endpoint : u_ov5640/cmos1_d_d0[5]/opit_0/D +Startpoint : cmos1_data[6] (port) +Endpoint : u_ov5640/cmos1_d_d0[6]/opit_0/D Path Group : cmos1_pclk Path Type : max (fast corner) Path Class : sequential timing path @@ -7942,18 +8776,16 @@ Clock Skew : 3.172 (Capture Clock Delay - Launch Clock Delay + Clock Pessim Clock cmos1_pclk (rising edge) 0.000 0.000 r Input external delay 1.000 1.000 f - AB11 0.000 1.000 f cmos1_data[5] (port) - net (fanout=1) 0.077 1.077 cmos1_data[5] - IOBS_TB_156_0/DIN td 1.049 2.126 f cmos1_data_ibuf[5]/opit_0/O - net (fanout=1) 0.000 2.126 cmos1_data_ibuf[5]/ntD - IOL_159_5/RX_DATA_DD td 0.097 2.223 f cmos1_data_ibuf[5]/opit_1/OUT - net (fanout=1) 1.648 3.871 nt_cmos1_data[5] - CLMS_322_9/Y6CD td 0.103 3.974 f CLKROUTE_0/Z - net (fanout=1) 3.866 7.840 ntR3901 - CLMS_146_9/M0 f u_ov5640/cmos1_d_d0[5]/opit_0/D + AA10 0.000 1.000 f cmos1_data[6] (port) + net (fanout=1) 0.080 1.080 cmos1_data[6] + IOBD_149_0/DIN td 1.049 2.129 f cmos1_data_ibuf[6]/opit_0/O + net (fanout=1) 0.000 2.129 cmos1_data_ibuf[6]/ntD + IOL_151_6/RX_DATA_DD td 0.097 2.226 f cmos1_data_ibuf[6]/opit_1/OUT + net (fanout=1) 5.291 7.517 nt_cmos1_data[6] + CLMS_150_41/M1 f u_ov5640/cmos1_d_d0[6]/opit_0/D - Data arrival time 7.840 Logic Levels: 3 - Logic: 1.249ns(18.260%), Route: 5.591ns(81.740%) + Data arrival time 7.517 Logic Levels: 2 + Logic: 1.146ns(17.585%), Route: 5.371ns(82.415%) ---------------------------------------------------------------------------------------------------- Clock cmos1_pclk (rising edge) 11.900 11.900 r @@ -7963,9 +8795,9 @@ Clock Skew : 3.172 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.000 12.711 cmos1_pclk_ibuf/ntD IOL_171_6/INCK td 0.038 12.749 r cmos1_pclk_ibuf/opit_1/INCK net (fanout=1) 1.428 14.177 _N64 - USCM_84_112/CLK_USCM td 0.000 14.177 r clkbufg_5/gopclkbufg/CLKOUT - net (fanout=118) 0.895 15.072 ntclkbufg_5 - CLMS_146_9/CLK r u_ov5640/cmos1_d_d0[5]/opit_0/CLK + USCM_84_112/CLK_USCM td 0.000 14.177 r clkbufg_6/gopclkbufg/CLKOUT + net (fanout=118) 0.895 15.072 ntclkbufg_6 + CLMS_150_41/CLK r u_ov5640/cmos1_d_d0[6]/opit_0/CLK clock pessimism 0.000 15.072 clock uncertainty -0.250 14.822 @@ -7974,22 +8806,22 @@ Clock Skew : 3.172 (Capture Clock Delay - Launch Clock Delay + Clock Pessim Data required time 14.754 ---------------------------------------------------------------------------------------------------- Data required time 14.754 - Data arrival time 7.840 + Data arrival time 7.517 ---------------------------------------------------------------------------------------------------- - Slack (MET) 6.914 + Slack (MET) 7.237 ==================================================================================================== ==================================================================================================== -Startpoint : u_ov5640/cmos1_8_16bit/image_data0[5]/opit_0/CLK -Endpoint : u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/DA0[5] +Startpoint : u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK +Endpoint : u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/L0 Path Group : cmos1_pclk Path Type : min (fast corner) Path Class : sequential timing path -Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) +Clock Skew : 0.015 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) Capture Clock Delay : 3.375 Launch Clock Delay : 3.172 - Clock Pessimism Removal : -0.184 + Clock Pessimism Removal : -0.188 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -8001,16 +8833,16 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.000 0.811 cmos1_pclk_ibuf/ntD IOL_171_6/INCK td 0.038 0.849 r cmos1_pclk_ibuf/opit_1/INCK net (fanout=1) 1.428 2.277 _N64 - USCM_84_112/CLK_USCM td 0.000 2.277 r clkbufg_5/gopclkbufg/CLKOUT - net (fanout=118) 0.895 3.172 ntclkbufg_5 - CLMS_146_33/CLK r u_ov5640/cmos1_8_16bit/image_data0[5]/opit_0/CLK + USCM_84_112/CLK_USCM td 0.000 2.277 r clkbufg_6/gopclkbufg/CLKOUT + net (fanout=118) 0.895 3.172 ntclkbufg_6 + CLMA_138_56/CLK r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK - CLMS_146_33/Q2 tco 0.180 3.352 f u_ov5640/cmos1_8_16bit/image_data0[5]/opit_0/Q - net (fanout=1) 0.266 3.618 u_ov5640/cmos1_d_16bit [5] - DRM_142_24/DA0[5] f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/DA0[5] + CLMA_138_56/Q1 tco 0.180 3.352 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/Q1 + net (fanout=5) 0.062 3.414 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/wr_addr [5] + CLMA_138_57/C0 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/L0 - Data arrival time 3.618 Logic Levels: 0 - Logic: 0.180ns(40.359%), Route: 0.266ns(59.641%) + Data arrival time 3.414 Logic Levels: 0 + Logic: 0.180ns(74.380%), Route: 0.062ns(25.620%) ---------------------------------------------------------------------------------------------------- Clock cmos1_pclk (rising edge) 0.000 0.000 r @@ -8020,33 +8852,33 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.000 0.937 cmos1_pclk_ibuf/ntD IOL_171_6/INCK td 0.058 0.995 r cmos1_pclk_ibuf/opit_1/INCK net (fanout=1) 1.455 2.450 _N64 - USCM_84_112/CLK_USCM td 0.000 2.450 r clkbufg_5/gopclkbufg/CLKOUT - net (fanout=118) 0.925 3.375 ntclkbufg_5 - DRM_142_24/CLKA[0] r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] - clock pessimism -0.184 3.191 - clock uncertainty 0.200 3.391 + USCM_84_112/CLK_USCM td 0.000 2.450 r clkbufg_6/gopclkbufg/CLKOUT + net (fanout=118) 0.925 3.375 ntclkbufg_6 + CLMA_138_57/CLK r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/CLK + clock pessimism -0.188 3.187 + clock uncertainty 0.200 3.387 - Hold time 0.119 3.510 + Hold time -0.077 3.310 - Data required time 3.510 + Data required time 3.310 ---------------------------------------------------------------------------------------------------- - Data required time 3.510 - Data arrival time 3.618 + Data required time 3.310 + Data arrival time 3.414 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.108 + Slack (MET) 0.104 ==================================================================================================== ==================================================================================================== -Startpoint : u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/opit_0/CLK -Endpoint : u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/D +Startpoint : u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK +Endpoint : u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/L0 Path Group : cmos1_pclk Path Type : min (fast corner) Path Class : sequential timing path -Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) +Clock Skew : 0.015 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) Capture Clock Delay : 3.375 Launch Clock Delay : 3.172 - Clock Pessimism Removal : -0.184 + Clock Pessimism Removal : -0.188 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -8058,16 +8890,16 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.000 0.811 cmos1_pclk_ibuf/ntD IOL_171_6/INCK td 0.038 0.849 r cmos1_pclk_ibuf/opit_1/INCK net (fanout=1) 1.428 2.277 _N64 - USCM_84_112/CLK_USCM td 0.000 2.277 r clkbufg_5/gopclkbufg/CLKOUT - net (fanout=118) 0.895 3.172 ntclkbufg_5 - CLMA_138_24/CLK r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/opit_0/CLK + USCM_84_112/CLK_USCM td 0.000 2.277 r clkbufg_6/gopclkbufg/CLKOUT + net (fanout=118) 0.895 3.172 ntclkbufg_6 + CLMA_138_60/CLK r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK - CLMA_138_24/Q0 tco 0.182 3.354 r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/opit_0/Q - net (fanout=1) 0.136 3.490 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr1 [1] - CLMA_134_28/M2 r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/D + CLMA_138_60/Q0 tco 0.179 3.351 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/Q0 + net (fanout=5) 0.062 3.413 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/wr_addr [8] + CLMA_138_61/A0 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/L0 - Data arrival time 3.490 Logic Levels: 0 - Logic: 0.182ns(57.233%), Route: 0.136ns(42.767%) + Data arrival time 3.413 Logic Levels: 0 + Logic: 0.179ns(74.274%), Route: 0.062ns(25.726%) ---------------------------------------------------------------------------------------------------- Clock cmos1_pclk (rising edge) 0.000 0.000 r @@ -8077,26 +8909,26 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.000 0.937 cmos1_pclk_ibuf/ntD IOL_171_6/INCK td 0.058 0.995 r cmos1_pclk_ibuf/opit_1/INCK net (fanout=1) 1.455 2.450 _N64 - USCM_84_112/CLK_USCM td 0.000 2.450 r clkbufg_5/gopclkbufg/CLKOUT - net (fanout=118) 0.925 3.375 ntclkbufg_5 - CLMA_134_28/CLK r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/CLK - clock pessimism -0.184 3.191 - clock uncertainty 0.200 3.391 + USCM_84_112/CLK_USCM td 0.000 2.450 r clkbufg_6/gopclkbufg/CLKOUT + net (fanout=118) 0.925 3.375 ntclkbufg_6 + CLMA_138_61/CLK r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/CLK + clock pessimism -0.188 3.187 + clock uncertainty 0.200 3.387 - Hold time -0.011 3.380 + Hold time -0.078 3.309 - Data required time 3.380 + Data required time 3.309 ---------------------------------------------------------------------------------------------------- - Data required time 3.380 - Data arrival time 3.490 + Data required time 3.309 + Data arrival time 3.413 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.110 + Slack (MET) 0.104 ==================================================================================================== ==================================================================================================== -Startpoint : u_ov5640/cmos1_8_16bit/pdata_i2[0]/opit_0/CLK -Endpoint : u_ov5640/cmos1_8_16bit/image_data0[8]/opit_0/D +Startpoint : u_ov5640/cmos1_8_16bit/pdata_i2[4]/opit_0/CLK +Endpoint : u_ov5640/cmos1_8_16bit/image_data0[12]/opit_0/D Path Group : cmos1_pclk Path Type : min (fast corner) Path Class : sequential timing path @@ -8115,16 +8947,16 @@ Clock Skew : 0.015 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.000 0.811 cmos1_pclk_ibuf/ntD IOL_171_6/INCK td 0.038 0.849 r cmos1_pclk_ibuf/opit_1/INCK net (fanout=1) 1.428 2.277 _N64 - USCM_84_112/CLK_USCM td 0.000 2.277 r clkbufg_5/gopclkbufg/CLKOUT - net (fanout=118) 0.895 3.172 ntclkbufg_5 - CLMA_138_25/CLK r u_ov5640/cmos1_8_16bit/pdata_i2[0]/opit_0/CLK + USCM_84_112/CLK_USCM td 0.000 2.277 r clkbufg_6/gopclkbufg/CLKOUT + net (fanout=118) 0.895 3.172 ntclkbufg_6 + CLMA_138_44/CLK r u_ov5640/cmos1_8_16bit/pdata_i2[4]/opit_0/CLK - CLMA_138_25/Q3 tco 0.182 3.354 r u_ov5640/cmos1_8_16bit/pdata_i2[0]/opit_0/Q - net (fanout=1) 0.133 3.487 u_ov5640/cmos1_8_16bit/pdata_i2 [0] - CLMA_138_29/M1 r u_ov5640/cmos1_8_16bit/image_data0[8]/opit_0/D + CLMA_138_44/Y0 tco 0.228 3.400 f u_ov5640/cmos1_8_16bit/pdata_i2[4]/opit_0/Q + net (fanout=1) 0.135 3.535 u_ov5640/cmos1_8_16bit/pdata_i2 [4] + CLMA_138_45/AD f u_ov5640/cmos1_8_16bit/image_data0[12]/opit_0/D - Data arrival time 3.487 Logic Levels: 0 - Logic: 0.182ns(57.778%), Route: 0.133ns(42.222%) + Data arrival time 3.535 Logic Levels: 0 + Logic: 0.228ns(62.810%), Route: 0.135ns(37.190%) ---------------------------------------------------------------------------------------------------- Clock cmos1_pclk (rising edge) 0.000 0.000 r @@ -8134,31 +8966,31 @@ Clock Skew : 0.015 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.000 0.937 cmos1_pclk_ibuf/ntD IOL_171_6/INCK td 0.058 0.995 r cmos1_pclk_ibuf/opit_1/INCK net (fanout=1) 1.455 2.450 _N64 - USCM_84_112/CLK_USCM td 0.000 2.450 r clkbufg_5/gopclkbufg/CLKOUT - net (fanout=118) 0.925 3.375 ntclkbufg_5 - CLMA_138_29/CLK r u_ov5640/cmos1_8_16bit/image_data0[8]/opit_0/CLK + USCM_84_112/CLK_USCM td 0.000 2.450 r clkbufg_6/gopclkbufg/CLKOUT + net (fanout=118) 0.925 3.375 ntclkbufg_6 + CLMA_138_45/CLK r u_ov5640/cmos1_8_16bit/image_data0[12]/opit_0/CLK clock pessimism -0.188 3.187 clock uncertainty 0.200 3.387 - Hold time -0.011 3.376 + Hold time 0.040 3.427 - Data required time 3.376 + Data required time 3.427 ---------------------------------------------------------------------------------------------------- - Data required time 3.376 - Data arrival time 3.487 + Data required time 3.427 + Data arrival time 3.535 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.111 + Slack (MET) 0.108 ==================================================================================================== ==================================================================================================== -Startpoint : cmos2_data[7] (port) -Endpoint : u_ov5640/cmos2_d_d0[7]/opit_0/D +Startpoint : cmos2_data[6] (port) +Endpoint : u_ov5640/cmos2_d_d0[6]/opit_0/D Path Group : cmos2_pclk Path Type : max (fast corner) Path Class : sequential timing path -Clock Skew : 3.512 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 3.512 +Clock Skew : 3.511 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 3.511 Launch Clock Delay : 0.000 Clock Pessimism Removal : 0.000 @@ -8168,16 +9000,16 @@ Clock Skew : 3.512 (Capture Clock Delay - Launch Clock Delay + Clock Pessim Clock cmos2_pclk (rising edge) 0.000 0.000 r Input external delay 1.000 1.000 f - AB9 0.000 1.000 f cmos2_data[7] (port) - net (fanout=1) 0.080 1.080 cmos2_data[7] - IOBS_TB_128_0/DIN td 1.049 2.129 f cmos2_data_ibuf[7]/opit_0/O - net (fanout=1) 0.000 2.129 cmos2_data_ibuf[7]/ntD - IOL_131_5/RX_DATA_DD td 0.097 2.226 f cmos2_data_ibuf[7]/opit_1/OUT - net (fanout=1) 6.776 9.002 nt_cmos2_data[7] - CLMS_130_37/M2 f u_ov5640/cmos2_d_d0[7]/opit_0/D + Y9 0.000 1.000 f cmos2_data[6] (port) + net (fanout=1) 0.078 1.078 cmos2_data[6] + IOBD_129_0/DIN td 1.049 2.127 f cmos2_data_ibuf[6]/opit_0/O + net (fanout=1) 0.000 2.127 cmos2_data_ibuf[6]/ntD + IOL_131_6/RX_DATA_DD td 0.097 2.224 f cmos2_data_ibuf[6]/opit_1/OUT + net (fanout=1) 7.000 9.224 nt_cmos2_data[6] + CLMA_138_8/M1 f u_ov5640/cmos2_d_d0[6]/opit_0/D - Data arrival time 9.002 Logic Levels: 2 - Logic: 1.146ns(14.321%), Route: 6.856ns(85.679%) + Data arrival time 9.224 Logic Levels: 2 + Logic: 1.146ns(13.935%), Route: 7.078ns(86.065%) ---------------------------------------------------------------------------------------------------- Clock cmos2_pclk (rising edge) 11.900 11.900 r @@ -8186,21 +9018,21 @@ Clock Skew : 3.512 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOBD_37_0/DIN td 0.735 12.706 r cmos2_pclk_ibuf/opit_0/O net (fanout=1) 0.000 12.706 cmos2_pclk_ibuf/ntD IOL_39_6/RX_DATA_DD td 0.066 12.772 r cmos2_pclk_ibuf/opit_1/OUT - net (fanout=1) 1.745 14.517 nt_cmos2_pclk - USCM_84_118/CLK_USCM td 0.000 14.517 r clkbufg_6/gopclkbufg/CLKOUT - net (fanout=118) 0.895 15.412 ntclkbufg_6 - CLMS_130_37/CLK r u_ov5640/cmos2_d_d0[7]/opit_0/CLK - clock pessimism 0.000 15.412 - clock uncertainty -0.250 15.162 + net (fanout=1) 1.744 14.516 nt_cmos2_pclk + USCM_84_119/CLK_USCM td 0.000 14.516 r clkbufg_7/gopclkbufg/CLKOUT + net (fanout=118) 0.895 15.411 ntclkbufg_7 + CLMA_138_8/CLK r u_ov5640/cmos2_d_d0[6]/opit_0/CLK + clock pessimism 0.000 15.411 + clock uncertainty -0.250 15.161 - Setup time -0.068 15.094 + Setup time -0.068 15.093 - Data required time 15.094 + Data required time 15.093 ---------------------------------------------------------------------------------------------------- - Data required time 15.094 - Data arrival time 9.002 + Data required time 15.093 + Data arrival time 9.224 ---------------------------------------------------------------------------------------------------- - Slack (MET) 6.092 + Slack (MET) 5.869 ==================================================================================================== ==================================================================================================== @@ -8210,8 +9042,8 @@ Endpoint : u_ov5640/cmos2_d_d0[5]/opit_0/D Path Group : cmos2_pclk Path Type : max (fast corner) Path Class : sequential timing path -Clock Skew : 3.512 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 3.512 +Clock Skew : 3.511 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 3.511 Launch Clock Delay : 0.000 Clock Pessimism Removal : 0.000 @@ -8226,11 +9058,13 @@ Clock Skew : 3.512 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOBS_TB_116_0/DIN td 1.049 2.133 f cmos2_data_ibuf[5]/opit_0/O net (fanout=1) 0.000 2.133 cmos2_data_ibuf[5]/ntD IOL_119_5/RX_DATA_DD td 0.097 2.230 f cmos2_data_ibuf[5]/opit_1/OUT - net (fanout=1) 6.531 8.761 nt_cmos2_data[5] - CLMA_134_40/M0 f u_ov5640/cmos2_d_d0[5]/opit_0/D + net (fanout=1) 1.068 3.298 nt_cmos2_data[5] + CLMS_198_49/Y6CD td 0.103 3.401 f CLKROUTE_0/Z + net (fanout=1) 5.822 9.223 ntR3940 + CLMA_138_8/M0 f u_ov5640/cmos2_d_d0[5]/opit_0/D - Data arrival time 8.761 Logic Levels: 2 - Logic: 1.146ns(14.766%), Route: 6.615ns(85.234%) + Data arrival time 9.223 Logic Levels: 3 + Logic: 1.249ns(15.189%), Route: 6.974ns(84.811%) ---------------------------------------------------------------------------------------------------- Clock cmos2_pclk (rising edge) 11.900 11.900 r @@ -8239,32 +9073,32 @@ Clock Skew : 3.512 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOBD_37_0/DIN td 0.735 12.706 r cmos2_pclk_ibuf/opit_0/O net (fanout=1) 0.000 12.706 cmos2_pclk_ibuf/ntD IOL_39_6/RX_DATA_DD td 0.066 12.772 r cmos2_pclk_ibuf/opit_1/OUT - net (fanout=1) 1.745 14.517 nt_cmos2_pclk - USCM_84_118/CLK_USCM td 0.000 14.517 r clkbufg_6/gopclkbufg/CLKOUT - net (fanout=118) 0.895 15.412 ntclkbufg_6 - CLMA_134_40/CLK r u_ov5640/cmos2_d_d0[5]/opit_0/CLK - clock pessimism 0.000 15.412 - clock uncertainty -0.250 15.162 + net (fanout=1) 1.744 14.516 nt_cmos2_pclk + USCM_84_119/CLK_USCM td 0.000 14.516 r clkbufg_7/gopclkbufg/CLKOUT + net (fanout=118) 0.895 15.411 ntclkbufg_7 + CLMA_138_8/CLK r u_ov5640/cmos2_d_d0[5]/opit_0/CLK + clock pessimism 0.000 15.411 + clock uncertainty -0.250 15.161 - Setup time -0.068 15.094 + Setup time -0.068 15.093 - Data required time 15.094 + Data required time 15.093 ---------------------------------------------------------------------------------------------------- - Data required time 15.094 - Data arrival time 8.761 + Data required time 15.093 + Data arrival time 9.223 ---------------------------------------------------------------------------------------------------- - Slack (MET) 6.333 + Slack (MET) 5.870 ==================================================================================================== ==================================================================================================== -Startpoint : cmos2_data[6] (port) -Endpoint : u_ov5640/cmos2_d_d0[6]/opit_0/D +Startpoint : cmos2_href (port) +Endpoint : u_ov5640/cmos2_href_d0/opit_0/D Path Group : cmos2_pclk Path Type : max (fast corner) Path Class : sequential timing path -Clock Skew : 3.512 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 3.512 +Clock Skew : 3.550 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 3.550 Launch Clock Delay : 0.000 Clock Pessimism Removal : 0.000 @@ -8274,18 +9108,20 @@ Clock Skew : 3.512 (Capture Clock Delay - Launch Clock Delay + Clock Pessim Clock cmos2_pclk (rising edge) 0.000 0.000 r Input external delay 1.000 1.000 f - Y9 0.000 1.000 f cmos2_data[6] (port) - net (fanout=1) 0.078 1.078 cmos2_data[6] - IOBD_129_0/DIN td 1.049 2.127 f cmos2_data_ibuf[6]/opit_0/O - net (fanout=1) 0.000 2.127 cmos2_data_ibuf[6]/ntD - IOL_131_6/RX_DATA_DD td 0.097 2.224 f cmos2_data_ibuf[6]/opit_1/OUT - net (fanout=1) 0.831 3.055 nt_cmos2_data[6] - CLMA_94_8/Y6AB td 0.101 3.156 f CLKROUTE_2/Z - net (fanout=1) 5.292 8.448 ntR3903 - CLMA_134_40/M1 f u_ov5640/cmos2_d_d0[6]/opit_0/D + AB5 0.000 1.000 f cmos2_href (port) + net (fanout=1) 0.093 1.093 cmos2_href + IOBS_TB_32_0/DIN td 0.918 2.011 f cmos2_href_ibuf/opit_0/O + net (fanout=1) 0.000 2.011 cmos2_href_ibuf/ntD + IOL_35_5/RX_DATA_DD td 0.097 2.108 f cmos2_href_ibuf/opit_1/OUT + net (fanout=1) 0.521 2.629 nt_cmos2_href + CLMA_18_12/Y6AB td 0.101 2.730 f CLKROUTE_2/Z + net (fanout=1) 3.087 5.817 ntR3942 + CLMA_18_80/Y6CD td 0.103 5.920 f CLKROUTE_1/Z + net (fanout=1) 3.317 9.237 ntR3941 + CLMS_78_21/CD f u_ov5640/cmos2_href_d0/opit_0/D - Data arrival time 8.448 Logic Levels: 3 - Logic: 1.247ns(16.743%), Route: 6.201ns(83.257%) + Data arrival time 9.237 Logic Levels: 4 + Logic: 1.219ns(14.799%), Route: 7.018ns(85.201%) ---------------------------------------------------------------------------------------------------- Clock cmos2_pclk (rising edge) 11.900 11.900 r @@ -8294,33 +9130,33 @@ Clock Skew : 3.512 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOBD_37_0/DIN td 0.735 12.706 r cmos2_pclk_ibuf/opit_0/O net (fanout=1) 0.000 12.706 cmos2_pclk_ibuf/ntD IOL_39_6/RX_DATA_DD td 0.066 12.772 r cmos2_pclk_ibuf/opit_1/OUT - net (fanout=1) 1.745 14.517 nt_cmos2_pclk - USCM_84_118/CLK_USCM td 0.000 14.517 r clkbufg_6/gopclkbufg/CLKOUT - net (fanout=118) 0.895 15.412 ntclkbufg_6 - CLMA_134_40/CLK r u_ov5640/cmos2_d_d0[6]/opit_0/CLK - clock pessimism 0.000 15.412 - clock uncertainty -0.250 15.162 + net (fanout=1) 1.744 14.516 nt_cmos2_pclk + USCM_84_119/CLK_USCM td 0.000 14.516 r clkbufg_7/gopclkbufg/CLKOUT + net (fanout=118) 0.934 15.450 ntclkbufg_7 + CLMS_78_21/CLK r u_ov5640/cmos2_href_d0/opit_0/CLK + clock pessimism 0.000 15.450 + clock uncertainty -0.250 15.200 - Setup time -0.068 15.094 + Setup time 0.024 15.224 - Data required time 15.094 + Data required time 15.224 ---------------------------------------------------------------------------------------------------- - Data required time 15.094 - Data arrival time 8.448 + Data required time 15.224 + Data arrival time 9.237 ---------------------------------------------------------------------------------------------------- - Slack (MET) 6.646 + Slack (MET) 5.987 ==================================================================================================== ==================================================================================================== -Startpoint : u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK -Endpoint : u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/D +Startpoint : u_ov5640/cmos2_href_d0/opit_0/CLK +Endpoint : u_ov5640/cmos2_href_d1/opit_0/D Path Group : cmos2_pclk Path Type : min (fast corner) Path Class : sequential timing path -Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 3.861 - Launch Clock Delay : 3.512 +Clock Skew : 0.007 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 3.887 + Launch Clock Delay : 3.550 Clock Pessimism Removal : -0.330 Location Delay Type Incr Path Logical Resource @@ -8332,17 +9168,17 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOBD_37_0/DIN td 0.735 0.806 r cmos2_pclk_ibuf/opit_0/O net (fanout=1) 0.000 0.806 cmos2_pclk_ibuf/ntD IOL_39_6/RX_DATA_DD td 0.066 0.872 r cmos2_pclk_ibuf/opit_1/OUT - net (fanout=1) 1.745 2.617 nt_cmos2_pclk - USCM_84_118/CLK_USCM td 0.000 2.617 r clkbufg_6/gopclkbufg/CLKOUT - net (fanout=118) 0.895 3.512 ntclkbufg_6 - CLMS_150_53/CLK r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK + net (fanout=1) 1.744 2.616 nt_cmos2_pclk + USCM_84_119/CLK_USCM td 0.000 2.616 r clkbufg_7/gopclkbufg/CLKOUT + net (fanout=118) 0.934 3.550 ntclkbufg_7 + CLMS_78_21/CLK r u_ov5640/cmos2_href_d0/opit_0/CLK - CLMS_150_53/Q3 tco 0.182 3.694 r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/Q - net (fanout=1) 0.280 3.974 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr1 [4] - CLMA_154_53/M1 r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/D + CLMS_78_21/Y2 tco 0.236 3.786 r u_ov5640/cmos2_href_d0/opit_0/Q + net (fanout=1) 0.210 3.996 u_ov5640/cmos2_href_d0 + CLMS_74_17/M2 r u_ov5640/cmos2_href_d1/opit_0/D - Data arrival time 3.974 Logic Levels: 0 - Logic: 0.182ns(39.394%), Route: 0.280ns(60.606%) + Data arrival time 3.996 Logic Levels: 0 + Logic: 0.236ns(52.915%), Route: 0.210ns(47.085%) ---------------------------------------------------------------------------------------------------- Clock cmos2_pclk (rising edge) 0.000 0.000 r @@ -8351,34 +9187,34 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOBD_37_0/DIN td 0.861 0.932 r cmos2_pclk_ibuf/opit_0/O net (fanout=1) 0.000 0.932 cmos2_pclk_ibuf/ntD IOL_39_6/RX_DATA_DD td 0.096 1.028 r cmos2_pclk_ibuf/opit_1/OUT - net (fanout=1) 1.908 2.936 nt_cmos2_pclk - USCM_84_118/CLK_USCM td 0.000 2.936 r clkbufg_6/gopclkbufg/CLKOUT - net (fanout=118) 0.925 3.861 ntclkbufg_6 - CLMA_154_53/CLK r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/CLK - clock pessimism -0.330 3.531 - clock uncertainty 0.200 3.731 + net (fanout=1) 1.907 2.935 nt_cmos2_pclk + USCM_84_119/CLK_USCM td 0.000 2.935 r clkbufg_7/gopclkbufg/CLKOUT + net (fanout=118) 0.952 3.887 ntclkbufg_7 + CLMS_74_17/CLK r u_ov5640/cmos2_href_d1/opit_0/CLK + clock pessimism -0.330 3.557 + clock uncertainty 0.200 3.757 - Hold time -0.011 3.720 + Hold time -0.011 3.746 - Data required time 3.720 + Data required time 3.746 ---------------------------------------------------------------------------------------------------- - Data required time 3.720 - Data arrival time 3.974 + Data required time 3.746 + Data arrival time 3.996 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.254 + Slack (MET) 0.250 ==================================================================================================== ==================================================================================================== -Startpoint : u_ov5640/cmos2_8_16bit/pdata_i0[1]/opit_0/CLK -Endpoint : u_ov5640/cmos2_8_16bit/pdata_i1[1]/opit_0/D +Startpoint : u_ov5640/cmos2_d_d0[4]/opit_0/CLK +Endpoint : u_ov5640/cmos2_d_d1[4]/opit_0/D Path Group : cmos2_pclk Path Type : min (fast corner) Path Class : sequential timing path -Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 3.861 - Launch Clock Delay : 3.512 - Clock Pessimism Removal : -0.330 +Clock Skew : 0.001 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 3.860 + Launch Clock Delay : 3.511 + Clock Pessimism Removal : -0.348 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -8389,17 +9225,17 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOBD_37_0/DIN td 0.735 0.806 r cmos2_pclk_ibuf/opit_0/O net (fanout=1) 0.000 0.806 cmos2_pclk_ibuf/ntD IOL_39_6/RX_DATA_DD td 0.066 0.872 r cmos2_pclk_ibuf/opit_1/OUT - net (fanout=1) 1.745 2.617 nt_cmos2_pclk - USCM_84_118/CLK_USCM td 0.000 2.617 r clkbufg_6/gopclkbufg/CLKOUT - net (fanout=118) 0.895 3.512 ntclkbufg_6 - CLMS_130_45/CLK r u_ov5640/cmos2_8_16bit/pdata_i0[1]/opit_0/CLK + net (fanout=1) 1.744 2.616 nt_cmos2_pclk + USCM_84_119/CLK_USCM td 0.000 2.616 r clkbufg_7/gopclkbufg/CLKOUT + net (fanout=118) 0.895 3.511 ntclkbufg_7 + CLMA_138_20/CLK r u_ov5640/cmos2_d_d0[4]/opit_0/CLK - CLMS_130_45/Y2 tco 0.236 3.748 r u_ov5640/cmos2_8_16bit/pdata_i0[1]/opit_0/Q - net (fanout=1) 0.234 3.982 u_ov5640/cmos2_8_16bit/pdata_i0 [1] - CLMA_134_52/M3 r u_ov5640/cmos2_8_16bit/pdata_i1[1]/opit_0/D + CLMA_138_20/Y0 tco 0.236 3.747 r u_ov5640/cmos2_d_d0[4]/opit_0/Q + net (fanout=1) 0.211 3.958 u_ov5640/cmos2_d_d0 [4] + CLMA_138_20/M2 r u_ov5640/cmos2_d_d1[4]/opit_0/D - Data arrival time 3.982 Logic Levels: 0 - Logic: 0.236ns(50.213%), Route: 0.234ns(49.787%) + Data arrival time 3.958 Logic Levels: 0 + Logic: 0.236ns(52.796%), Route: 0.211ns(47.204%) ---------------------------------------------------------------------------------------------------- Clock cmos2_pclk (rising edge) 0.000 0.000 r @@ -8408,33 +9244,33 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOBD_37_0/DIN td 0.861 0.932 r cmos2_pclk_ibuf/opit_0/O net (fanout=1) 0.000 0.932 cmos2_pclk_ibuf/ntD IOL_39_6/RX_DATA_DD td 0.096 1.028 r cmos2_pclk_ibuf/opit_1/OUT - net (fanout=1) 1.908 2.936 nt_cmos2_pclk - USCM_84_118/CLK_USCM td 0.000 2.936 r clkbufg_6/gopclkbufg/CLKOUT - net (fanout=118) 0.925 3.861 ntclkbufg_6 - CLMA_134_52/CLK r u_ov5640/cmos2_8_16bit/pdata_i1[1]/opit_0/CLK - clock pessimism -0.330 3.531 - clock uncertainty 0.200 3.731 + net (fanout=1) 1.907 2.935 nt_cmos2_pclk + USCM_84_119/CLK_USCM td 0.000 2.935 r clkbufg_7/gopclkbufg/CLKOUT + net (fanout=118) 0.925 3.860 ntclkbufg_7 + CLMA_138_20/CLK r u_ov5640/cmos2_d_d1[4]/opit_0/CLK + clock pessimism -0.348 3.512 + clock uncertainty 0.200 3.712 - Hold time -0.011 3.720 + Hold time -0.011 3.701 - Data required time 3.720 + Data required time 3.701 ---------------------------------------------------------------------------------------------------- - Data required time 3.720 - Data arrival time 3.982 + Data required time 3.701 + Data arrival time 3.958 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.262 + Slack (MET) 0.257 ==================================================================================================== ==================================================================================================== -Startpoint : u_ov5640/cmos2_8_16bit/pdata_i2[0]/opit_0/CLK -Endpoint : u_ov5640/cmos2_8_16bit/image_data0[8]/opit_0/D +Startpoint : u_ov5640/cmos2_d_d1[3]/opit_0/CLK +Endpoint : u_ov5640/cmos2_8_16bit/pdata_i0[3]/opit_0/D Path Group : cmos2_pclk Path Type : min (fast corner) Path Class : sequential timing path Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 3.861 - Launch Clock Delay : 3.512 + Capture Clock Delay : 3.860 + Launch Clock Delay : 3.511 Clock Pessimism Removal : -0.330 Location Delay Type Incr Path Logical Resource @@ -8446,17 +9282,17 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOBD_37_0/DIN td 0.735 0.806 r cmos2_pclk_ibuf/opit_0/O net (fanout=1) 0.000 0.806 cmos2_pclk_ibuf/ntD IOL_39_6/RX_DATA_DD td 0.066 0.872 r cmos2_pclk_ibuf/opit_1/OUT - net (fanout=1) 1.745 2.617 nt_cmos2_pclk - USCM_84_118/CLK_USCM td 0.000 2.617 r clkbufg_6/gopclkbufg/CLKOUT - net (fanout=118) 0.895 3.512 ntclkbufg_6 - CLMS_130_53/CLK r u_ov5640/cmos2_8_16bit/pdata_i2[0]/opit_0/CLK + net (fanout=1) 1.744 2.616 nt_cmos2_pclk + USCM_84_119/CLK_USCM td 0.000 2.616 r clkbufg_7/gopclkbufg/CLKOUT + net (fanout=118) 0.895 3.511 ntclkbufg_7 + CLMA_126_25/CLK r u_ov5640/cmos2_d_d1[3]/opit_0/CLK - CLMS_130_53/Q3 tco 0.182 3.694 r u_ov5640/cmos2_8_16bit/pdata_i2[0]/opit_0/Q - net (fanout=1) 0.289 3.983 u_ov5640/cmos2_8_16bit/pdata_i2 [0] - CLMA_138_56/M2 r u_ov5640/cmos2_8_16bit/image_data0[8]/opit_0/D + CLMA_126_25/Q1 tco 0.184 3.695 r u_ov5640/cmos2_d_d1[3]/opit_0/Q + net (fanout=1) 0.285 3.980 u_ov5640/cmos2_d_d1 [3] + CLMA_130_32/M1 r u_ov5640/cmos2_8_16bit/pdata_i0[3]/opit_0/D - Data arrival time 3.983 Logic Levels: 0 - Logic: 0.182ns(38.641%), Route: 0.289ns(61.359%) + Data arrival time 3.980 Logic Levels: 0 + Logic: 0.184ns(39.232%), Route: 0.285ns(60.768%) ---------------------------------------------------------------------------------------------------- Clock cmos2_pclk (rising edge) 0.000 0.000 r @@ -8465,21 +9301,21 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOBD_37_0/DIN td 0.861 0.932 r cmos2_pclk_ibuf/opit_0/O net (fanout=1) 0.000 0.932 cmos2_pclk_ibuf/ntD IOL_39_6/RX_DATA_DD td 0.096 1.028 r cmos2_pclk_ibuf/opit_1/OUT - net (fanout=1) 1.908 2.936 nt_cmos2_pclk - USCM_84_118/CLK_USCM td 0.000 2.936 r clkbufg_6/gopclkbufg/CLKOUT - net (fanout=118) 0.925 3.861 ntclkbufg_6 - CLMA_138_56/CLK r u_ov5640/cmos2_8_16bit/image_data0[8]/opit_0/CLK - clock pessimism -0.330 3.531 - clock uncertainty 0.200 3.731 + net (fanout=1) 1.907 2.935 nt_cmos2_pclk + USCM_84_119/CLK_USCM td 0.000 2.935 r clkbufg_7/gopclkbufg/CLKOUT + net (fanout=118) 0.925 3.860 ntclkbufg_7 + CLMA_130_32/CLK r u_ov5640/cmos2_8_16bit/pdata_i0[3]/opit_0/CLK + clock pessimism -0.330 3.530 + clock uncertainty 0.200 3.730 - Hold time -0.011 3.720 + Hold time -0.011 3.719 - Data required time 3.720 + Data required time 3.719 ---------------------------------------------------------------------------------------------------- - Data required time 3.720 - Data arrival time 3.983 + Data required time 3.719 + Data arrival time 3.980 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.263 + Slack (MET) 0.261 ==================================================================================================== ==================================================================================================== @@ -8504,28 +9340,30 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi net (fanout=1) 0.000 1.582 hdmi_in_clk_ibuf/ntD IOL_163_6/INCK td 0.058 1.640 r hdmi_in_clk_ibuf/opit_1/INCK net (fanout=1) 1.455 3.095 _N37 - USCM_84_111/CLK_USCM td 0.000 3.095 r clkbufg_4/gopclkbufg/CLKOUT - net (fanout=167) 0.925 4.020 ntclkbufg_4 - CLMA_146_68/CLK r u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK - - CLMA_146_68/Q0 tco 0.221 4.241 f u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/Q - net (fanout=4) 1.078 5.319 wr1_data_in_valid - td 0.222 5.541 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Cout - net (fanout=1) 0.000 5.541 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16001 - CLMA_70_96/Y3 td 0.387 5.928 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/Y1 - net (fanout=3) 0.249 6.177 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2 [3] - CLMA_66_88/Y2 td 0.381 6.558 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm/Z - net (fanout=1) 0.283 6.841 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wwptr [3] - td 0.365 7.206 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_0/gateop_A2/Cout - net (fanout=1) 0.000 7.206 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.co [2] - CLMA_66_100/COUT td 0.044 7.250 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_2/gateop_A2/Cout - net (fanout=1) 0.000 7.250 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.co [6] - CLMA_66_104/Y1 td 0.383 7.633 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_4/gateop_A2/Y1 - net (fanout=1) 0.072 7.705 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158 - CLMA_66_104/C4 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L4 - - Data arrival time 7.705 Logic Levels: 4 - Logic: 2.003ns(54.355%), Route: 1.682ns(45.645%) + USCM_84_111/CLK_USCM td 0.000 3.095 r clkbufg_5/gopclkbufg/CLKOUT + net (fanout=167) 0.925 4.020 ntclkbufg_5 + CLMA_110_85/CLK r u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK + + CLMA_110_85/Q0 tco 0.221 4.241 f u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/Q + net (fanout=4) 0.537 4.778 wr1_data_in_valid + td 0.222 5.000 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Cout + net (fanout=1) 0.000 5.000 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15959 + CLMA_90_101/COUT td 0.044 5.044 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/Cout + net (fanout=1) 0.000 5.044 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15961 + td 0.044 5.088 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/Cout + net (fanout=1) 0.000 5.088 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15963 + CLMA_90_105/Y3 td 0.365 5.453 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/Y1 + net (fanout=3) 0.355 5.808 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2 [7] + CLMA_94_112/Y3 td 0.151 5.959 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm/Z + net (fanout=1) 0.366 6.325 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wwptr [7] + CLMA_90_100/COUT td 0.391 6.716 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_2/gateop_A2/Cout + net (fanout=1) 0.000 6.716 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.co [6] + CLMA_90_104/Y1 td 0.383 7.099 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_4/gateop_A2/Y1 + net (fanout=1) 0.074 7.173 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158 + CLMA_90_104/C4 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L4 + + Data arrival time 7.173 Logic Levels: 5 + Logic: 1.821ns(57.755%), Route: 1.332ns(42.245%) ---------------------------------------------------------------------------------------------------- Clock hdmi_in_clk (rising edge) 6.666 6.666 r @@ -8535,9 +9373,9 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi net (fanout=1) 0.000 8.029 hdmi_in_clk_ibuf/ntD IOL_163_6/INCK td 0.038 8.067 r hdmi_in_clk_ibuf/opit_1/INCK net (fanout=1) 1.428 9.495 _N37 - USCM_84_111/CLK_USCM td 0.000 9.495 r clkbufg_4/gopclkbufg/CLKOUT - net (fanout=167) 0.895 10.390 ntclkbufg_4 - CLMA_66_104/CLK r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK + USCM_84_111/CLK_USCM td 0.000 9.495 r clkbufg_5/gopclkbufg/CLKOUT + net (fanout=167) 0.895 10.390 ntclkbufg_5 + CLMA_90_104/CLK r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK clock pessimism 0.277 10.667 clock uncertainty -0.250 10.417 @@ -8546,15 +9384,15 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi Data required time 10.323 ---------------------------------------------------------------------------------------------------- Data required time 10.323 - Data arrival time 7.705 + Data arrival time 7.173 ---------------------------------------------------------------------------------------------------- - Slack (MET) 2.618 + Slack (MET) 3.150 ==================================================================================================== ==================================================================================================== Startpoint : u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK -Endpoint : u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L0 +Endpoint : u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/L2 Path Group : hdmi_in_clk Path Type : max (fast corner) Path Class : sequential timing path @@ -8573,28 +9411,24 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi net (fanout=1) 0.000 1.582 hdmi_in_clk_ibuf/ntD IOL_163_6/INCK td 0.058 1.640 r hdmi_in_clk_ibuf/opit_1/INCK net (fanout=1) 1.455 3.095 _N37 - USCM_84_111/CLK_USCM td 0.000 3.095 r clkbufg_4/gopclkbufg/CLKOUT - net (fanout=167) 0.925 4.020 ntclkbufg_4 - CLMA_146_68/CLK r u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK - - CLMA_146_68/Q0 tco 0.221 4.241 f u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/Q - net (fanout=4) 1.078 5.319 wr1_data_in_valid - td 0.222 5.541 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Cout - net (fanout=1) 0.000 5.541 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16001 - CLMA_70_96/COUT td 0.044 5.585 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/Cout - net (fanout=1) 0.000 5.585 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16003 - td 0.044 5.629 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/Cout - net (fanout=1) 0.000 5.629 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16005 - CLMA_70_100/COUT td 0.044 5.673 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/Cout - net (fanout=1) 0.000 5.673 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16007 - td 0.044 5.717 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/Cout - net (fanout=1) 0.000 5.717 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16009 - CLMA_70_104/Y3 td 0.387 6.104 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_A2Q21/Y1 - net (fanout=3) 0.247 6.351 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2 [11] - CLMA_66_104/C0 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L0 - - Data arrival time 6.351 Logic Levels: 3 - Logic: 1.006ns(43.157%), Route: 1.325ns(56.843%) + USCM_84_111/CLK_USCM td 0.000 3.095 r clkbufg_5/gopclkbufg/CLKOUT + net (fanout=167) 0.925 4.020 ntclkbufg_5 + CLMA_110_85/CLK r u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK + + CLMA_110_85/Q0 tco 0.221 4.241 f u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/Q + net (fanout=4) 0.537 4.778 wr1_data_in_valid + td 0.222 5.000 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Cout + net (fanout=1) 0.000 5.000 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15959 + CLMA_90_101/COUT td 0.044 5.044 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/Cout + net (fanout=1) 0.000 5.044 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15961 + td 0.044 5.088 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/Cout + net (fanout=1) 0.000 5.088 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15963 + CLMA_90_105/Y2 td 0.209 5.297 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/Y0 + net (fanout=3) 0.452 5.749 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2 [6] + CLMA_90_104/D2 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/L2 + + Data arrival time 5.749 Logic Levels: 2 + Logic: 0.740ns(42.799%), Route: 0.989ns(57.201%) ---------------------------------------------------------------------------------------------------- Clock hdmi_in_clk (rising edge) 6.666 6.666 r @@ -8604,26 +9438,26 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi net (fanout=1) 0.000 8.029 hdmi_in_clk_ibuf/ntD IOL_163_6/INCK td 0.038 8.067 r hdmi_in_clk_ibuf/opit_1/INCK net (fanout=1) 1.428 9.495 _N37 - USCM_84_111/CLK_USCM td 0.000 9.495 r clkbufg_4/gopclkbufg/CLKOUT - net (fanout=167) 0.895 10.390 ntclkbufg_4 - CLMA_66_104/CLK r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK + USCM_84_111/CLK_USCM td 0.000 9.495 r clkbufg_5/gopclkbufg/CLKOUT + net (fanout=167) 0.895 10.390 ntclkbufg_5 + CLMA_90_104/CLK r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK clock pessimism 0.277 10.667 clock uncertainty -0.250 10.417 - Setup time -0.150 10.267 + Setup time -0.283 10.134 - Data required time 10.267 + Data required time 10.134 ---------------------------------------------------------------------------------------------------- - Data required time 10.267 - Data arrival time 6.351 + Data required time 10.134 + Data arrival time 5.749 ---------------------------------------------------------------------------------------------------- - Slack (MET) 3.916 + Slack (MET) 4.385 ==================================================================================================== ==================================================================================================== Startpoint : u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK -Endpoint : u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm/L4 +Endpoint : u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L1 Path Group : hdmi_in_clk Path Type : max (fast corner) Path Class : sequential timing path @@ -8642,28 +9476,28 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi net (fanout=1) 0.000 1.582 hdmi_in_clk_ibuf/ntD IOL_163_6/INCK td 0.058 1.640 r hdmi_in_clk_ibuf/opit_1/INCK net (fanout=1) 1.455 3.095 _N37 - USCM_84_111/CLK_USCM td 0.000 3.095 r clkbufg_4/gopclkbufg/CLKOUT - net (fanout=167) 0.925 4.020 ntclkbufg_4 - CLMA_146_68/CLK r u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK - - CLMA_146_68/Q0 tco 0.221 4.241 f u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/Q - net (fanout=4) 1.078 5.319 wr1_data_in_valid - td 0.222 5.541 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Cout - net (fanout=1) 0.000 5.541 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16001 - CLMA_70_96/COUT td 0.044 5.585 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/Cout - net (fanout=1) 0.000 5.585 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16003 - td 0.044 5.629 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/Cout - net (fanout=1) 0.000 5.629 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16005 - CLMA_70_100/COUT td 0.044 5.673 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/Cout - net (fanout=1) 0.000 5.673 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16007 - td 0.044 5.717 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/Cout - net (fanout=1) 0.000 5.717 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16009 - CLMA_70_104/Y3 td 0.387 6.104 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_A2Q21/Y1 - net (fanout=3) 0.247 6.351 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2 [11] - CLMS_66_105/C4 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm/L4 - - Data arrival time 6.351 Logic Levels: 3 - Logic: 1.006ns(43.157%), Route: 1.325ns(56.843%) + USCM_84_111/CLK_USCM td 0.000 3.095 r clkbufg_5/gopclkbufg/CLKOUT + net (fanout=167) 0.925 4.020 ntclkbufg_5 + CLMA_110_85/CLK r u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK + + CLMA_110_85/Q0 tco 0.221 4.241 f u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/Q + net (fanout=4) 0.537 4.778 wr1_data_in_valid + td 0.222 5.000 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Cout + net (fanout=1) 0.000 5.000 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15959 + CLMA_90_101/COUT td 0.044 5.044 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/Cout + net (fanout=1) 0.000 5.044 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15961 + td 0.044 5.088 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/Cout + net (fanout=1) 0.000 5.088 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15963 + CLMA_90_105/COUT td 0.044 5.132 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/Cout + net (fanout=1) 0.000 5.132 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15965 + td 0.044 5.176 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/Cout + net (fanout=1) 0.000 5.176 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15967 + CLMA_90_109/Y3 td 0.365 5.541 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_A2Q21/Y1 + net (fanout=3) 0.259 5.800 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2 [11] + CLMA_90_104/C1 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L1 + + Data arrival time 5.800 Logic Levels: 3 + Logic: 0.984ns(55.281%), Route: 0.796ns(44.719%) ---------------------------------------------------------------------------------------------------- Clock hdmi_in_clk (rising edge) 6.666 6.666 r @@ -8673,26 +9507,26 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi net (fanout=1) 0.000 8.029 hdmi_in_clk_ibuf/ntD IOL_163_6/INCK td 0.038 8.067 r hdmi_in_clk_ibuf/opit_1/INCK net (fanout=1) 1.428 9.495 _N37 - USCM_84_111/CLK_USCM td 0.000 9.495 r clkbufg_4/gopclkbufg/CLKOUT - net (fanout=167) 0.895 10.390 ntclkbufg_4 - CLMS_66_105/CLK r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm/CLK + USCM_84_111/CLK_USCM td 0.000 9.495 r clkbufg_5/gopclkbufg/CLKOUT + net (fanout=167) 0.895 10.390 ntclkbufg_5 + CLMA_90_104/CLK r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK clock pessimism 0.277 10.667 clock uncertainty -0.250 10.417 - Setup time -0.094 10.323 + Setup time -0.190 10.227 - Data required time 10.323 + Data required time 10.227 ---------------------------------------------------------------------------------------------------- - Data required time 10.323 - Data arrival time 6.351 + Data required time 10.227 + Data arrival time 5.800 ---------------------------------------------------------------------------------------------------- - Slack (MET) 3.972 + Slack (MET) 4.427 ==================================================================================================== ==================================================================================================== -Startpoint : u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[2]/opit_0_L5Q_perm/CLK -Endpoint : u_ddr_addr_ctr/u_wr1_addr_ctr/wr_vs_flag/opit_0_L5Q_perm/L0 +Startpoint : u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[2]/opit_0_L5Q_perm/CLK +Endpoint : u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[3]/opit_0_L5Q_perm/L0 Path Group : hdmi_in_clk Path Type : min (fast corner) Path Class : sequential timing path @@ -8711,16 +9545,16 @@ Clock Skew : 0.001 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.000 1.363 hdmi_in_clk_ibuf/ntD IOL_163_6/INCK td 0.038 1.401 r hdmi_in_clk_ibuf/opit_1/INCK net (fanout=1) 1.428 2.829 _N37 - USCM_84_111/CLK_USCM td 0.000 2.829 r clkbufg_4/gopclkbufg/CLKOUT - net (fanout=167) 0.895 3.724 ntclkbufg_4 - CLMA_110_85/CLK r u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[2]/opit_0_L5Q_perm/CLK + USCM_84_111/CLK_USCM td 0.000 2.829 r clkbufg_5/gopclkbufg/CLKOUT + net (fanout=167) 0.895 3.724 ntclkbufg_5 + CLMA_122_92/CLK r u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[2]/opit_0_L5Q_perm/CLK - CLMA_110_85/Q2 tco 0.180 3.904 f u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[2]/opit_0_L5Q_perm/Q - net (fanout=5) 0.062 3.966 u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg [2] - CLMA_110_85/D0 f u_ddr_addr_ctr/u_wr1_addr_ctr/wr_vs_flag/opit_0_L5Q_perm/L0 + CLMA_122_92/Q2 tco 0.180 3.904 f u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[2]/opit_0_L5Q_perm/Q + net (fanout=3) 0.059 3.963 u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt [2] + CLMA_122_92/D0 f u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[3]/opit_0_L5Q_perm/L0 - Data arrival time 3.966 Logic Levels: 0 - Logic: 0.180ns(74.380%), Route: 0.062ns(25.620%) + Data arrival time 3.963 Logic Levels: 0 + Logic: 0.180ns(75.314%), Route: 0.059ns(24.686%) ---------------------------------------------------------------------------------------------------- Clock hdmi_in_clk (rising edge) 0.000 0.000 r @@ -8730,9 +9564,9 @@ Clock Skew : 0.001 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.000 1.582 hdmi_in_clk_ibuf/ntD IOL_163_6/INCK td 0.058 1.640 r hdmi_in_clk_ibuf/opit_1/INCK net (fanout=1) 1.455 3.095 _N37 - USCM_84_111/CLK_USCM td 0.000 3.095 r clkbufg_4/gopclkbufg/CLKOUT - net (fanout=167) 0.925 4.020 ntclkbufg_4 - CLMA_110_85/CLK r u_ddr_addr_ctr/u_wr1_addr_ctr/wr_vs_flag/opit_0_L5Q_perm/CLK + USCM_84_111/CLK_USCM td 0.000 3.095 r clkbufg_5/gopclkbufg/CLKOUT + net (fanout=167) 0.925 4.020 ntclkbufg_5 + CLMA_122_92/CLK r u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[3]/opit_0_L5Q_perm/CLK clock pessimism -0.295 3.725 clock uncertainty 0.200 3.925 @@ -8741,15 +9575,15 @@ Clock Skew : 0.001 (Capture Clock Delay - Launch Clock Delay + Clock Pessim Data required time 3.860 ---------------------------------------------------------------------------------------------------- Data required time 3.860 - Data arrival time 3.966 + Data arrival time 3.963 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.106 + Slack (MET) 0.103 ==================================================================================================== ==================================================================================================== -Startpoint : u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK -Endpoint : u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/D +Startpoint : u_hdmi_in_top/r_in3[3]/opit_0/CLK +Endpoint : u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/DA0[3] Path Group : hdmi_in_clk Path Type : min (fast corner) Path Class : sequential timing path @@ -8768,16 +9602,16 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.000 1.363 hdmi_in_clk_ibuf/ntD IOL_163_6/INCK td 0.038 1.401 r hdmi_in_clk_ibuf/opit_1/INCK net (fanout=1) 1.428 2.829 _N37 - USCM_84_111/CLK_USCM td 0.000 2.829 r clkbufg_4/gopclkbufg/CLKOUT - net (fanout=167) 0.895 3.724 ntclkbufg_4 - CLMA_66_104/CLK r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK + USCM_84_111/CLK_USCM td 0.000 2.829 r clkbufg_5/gopclkbufg/CLKOUT + net (fanout=167) 0.895 3.724 ntclkbufg_5 + CLMS_94_89/CLK r u_hdmi_in_top/r_in3[3]/opit_0/CLK - CLMA_66_104/Q0 tco 0.182 3.906 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/Q - net (fanout=1) 0.137 4.043 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr1 [3] - CLMS_62_101/M2 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/D + CLMS_94_89/Q3 tco 0.178 3.902 f u_hdmi_in_top/r_in3[3]/opit_0/Q + net (fanout=1) 0.265 4.167 wr1_data_in[11] + DRM_82_88/DA0[3] f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/DA0[3] - Data arrival time 4.043 Logic Levels: 0 - Logic: 0.182ns(57.053%), Route: 0.137ns(42.947%) + Data arrival time 4.167 Logic Levels: 0 + Logic: 0.178ns(40.181%), Route: 0.265ns(59.819%) ---------------------------------------------------------------------------------------------------- Clock hdmi_in_clk (rising edge) 0.000 0.000 r @@ -8787,26 +9621,26 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.000 1.582 hdmi_in_clk_ibuf/ntD IOL_163_6/INCK td 0.058 1.640 r hdmi_in_clk_ibuf/opit_1/INCK net (fanout=1) 1.455 3.095 _N37 - USCM_84_111/CLK_USCM td 0.000 3.095 r clkbufg_4/gopclkbufg/CLKOUT - net (fanout=167) 0.925 4.020 ntclkbufg_4 - CLMS_62_101/CLK r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/CLK + USCM_84_111/CLK_USCM td 0.000 3.095 r clkbufg_5/gopclkbufg/CLKOUT + net (fanout=167) 0.925 4.020 ntclkbufg_5 + DRM_82_88/CLKA[0] r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] clock pessimism -0.277 3.743 clock uncertainty 0.200 3.943 - Hold time -0.011 3.932 + Hold time 0.119 4.062 - Data required time 3.932 + Data required time 4.062 ---------------------------------------------------------------------------------------------------- - Data required time 3.932 - Data arrival time 4.043 + Data required time 4.062 + Data arrival time 4.167 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.111 + Slack (MET) 0.105 ==================================================================================================== ==================================================================================================== -Startpoint : u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK -Endpoint : u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/D +Startpoint : u_hdmi_in_top/r_in3[5]/opit_0/CLK +Endpoint : u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/DA0[5] Path Group : hdmi_in_clk Path Type : min (fast corner) Path Class : sequential timing path @@ -8825,16 +9659,16 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.000 1.363 hdmi_in_clk_ibuf/ntD IOL_163_6/INCK td 0.038 1.401 r hdmi_in_clk_ibuf/opit_1/INCK net (fanout=1) 1.428 2.829 _N37 - USCM_84_111/CLK_USCM td 0.000 2.829 r clkbufg_4/gopclkbufg/CLKOUT - net (fanout=167) 0.895 3.724 ntclkbufg_4 - CLMA_62_104/CLK r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK + USCM_84_111/CLK_USCM td 0.000 2.829 r clkbufg_5/gopclkbufg/CLKOUT + net (fanout=167) 0.895 3.724 ntclkbufg_5 + CLMA_90_92/CLK r u_hdmi_in_top/r_in3[5]/opit_0/CLK - CLMA_62_104/Q0 tco 0.182 3.906 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/Q - net (fanout=1) 0.137 4.043 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr1 [7] - CLMA_66_100/M0 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/D + CLMA_90_92/Q3 tco 0.178 3.902 f u_hdmi_in_top/r_in3[5]/opit_0/Q + net (fanout=1) 0.266 4.168 wr1_data_in[13] + DRM_82_88/DA0[5] f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/DA0[5] - Data arrival time 4.043 Logic Levels: 0 - Logic: 0.182ns(57.053%), Route: 0.137ns(42.947%) + Data arrival time 4.168 Logic Levels: 0 + Logic: 0.178ns(40.090%), Route: 0.266ns(59.910%) ---------------------------------------------------------------------------------------------------- Clock hdmi_in_clk (rising edge) 0.000 0.000 r @@ -8844,33 +9678,33 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.000 1.582 hdmi_in_clk_ibuf/ntD IOL_163_6/INCK td 0.058 1.640 r hdmi_in_clk_ibuf/opit_1/INCK net (fanout=1) 1.455 3.095 _N37 - USCM_84_111/CLK_USCM td 0.000 3.095 r clkbufg_4/gopclkbufg/CLKOUT - net (fanout=167) 0.925 4.020 ntclkbufg_4 - CLMA_66_100/CLK r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/CLK + USCM_84_111/CLK_USCM td 0.000 3.095 r clkbufg_5/gopclkbufg/CLKOUT + net (fanout=167) 0.925 4.020 ntclkbufg_5 + DRM_82_88/CLKA[0] r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] clock pessimism -0.277 3.743 clock uncertainty 0.200 3.943 - Hold time -0.011 3.932 + Hold time 0.119 4.062 - Data required time 3.932 + Data required time 4.062 ---------------------------------------------------------------------------------------------------- - Data required time 3.932 - Data arrival time 4.043 + Data required time 4.062 + Data arrival time 4.168 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.111 + Slack (MET) 0.106 ==================================================================================================== ==================================================================================================== -Startpoint : udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/CLK -Endpoint : udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[0]/opit_0_L5Q_perm/CE +Startpoint : udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/CLK +Endpoint : udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[14]/opit_0/CE Path Group : eth_rxc Path Type : max (fast corner) Path Class : sequential timing path Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.650 - Launch Clock Delay : 6.734 - Clock Pessimism Removal : 1.065 + Capture Clock Delay : 5.760 + Launch Clock Delay : 6.846 + Clock Pessimism Removal : 1.067 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -8885,35 +9719,29 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi IOCKDLY_237_367/CLK_OUT td 2.942 4.288 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT net (fanout=1) 1.521 5.809 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf USCM_84_109/CLK_USCM td 0.000 5.809 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - net (fanout=1861) 0.925 6.734 gmii_clk - CLMA_202_140/CLK r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/CLK - - CLMA_202_140/Q2 tco 0.224 6.958 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/Q - net (fanout=2) 0.305 7.263 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num [2] - td 0.365 7.628 f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_1/gateop_A2/Cout - net (fanout=1) 0.000 7.628 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [2] - CLMA_214_140/COUT td 0.044 7.672 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_3/gateop_A2/Cout - net (fanout=1) 0.000 7.672 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [4] - td 0.044 7.716 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_5/gateop_A2/Cout - net (fanout=1) 0.000 7.716 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [6] - CLMA_214_144/COUT td 0.044 7.760 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_7/gateop_A2/Cout - net (fanout=1) 0.000 7.760 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [8] - td 0.044 7.804 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_9/gateop_A2/Cout - net (fanout=1) 0.000 7.804 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [10] - CLMA_214_148/COUT td 0.044 7.848 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_11/gateop_A2/Cout - net (fanout=1) 0.000 7.848 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [12] - CLMA_214_152/Y0 td 0.206 8.054 f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_13/gateop_A2/Y0 - net (fanout=1) 0.468 8.522 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276 [13] - CLMA_210_141/Y3 td 0.431 8.953 f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N277.eq_6/gateop_A2/Y1 - net (fanout=18) 0.529 9.482 _N79 - CLMS_186_153/Y2 td 0.381 9.863 f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_pkt_done/opit_0_L5Q_perm/Z - net (fanout=1) 0.304 10.167 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N323 - CLMA_194_160/Y1 td 0.244 10.411 f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839/gateop_perm/Z - net (fanout=16) 0.553 10.964 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839 - CLMA_214_136/CE f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[0]/opit_0_L5Q_perm/CE - - Data arrival time 10.964 Logic Levels: 7 - Logic: 2.071ns(48.960%), Route: 2.159ns(51.040%) + net (fanout=1862) 1.037 6.846 gmii_clk + CLMA_194_261/CLK r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/CLK + + CLMA_194_261/Q0 tco 0.221 7.067 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/Q + net (fanout=2) 0.560 7.627 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t [0] + CLMA_182_241/Y1 td 0.224 7.851 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_39/gateop_perm/Z + net (fanout=1) 0.458 8.309 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108159 + CLMA_190_252/Y3 td 0.151 8.460 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_59/gateop_perm/Z + net (fanout=1) 0.367 8.827 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108179 + CLMA_190_240/Y2 td 0.150 8.977 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_63/gateop_perm/Z + net (fanout=2) 0.645 9.622 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446 + CLMA_210_265/Y3 td 0.162 9.784 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N289_6/gateop_perm/Z + net (fanout=6) 0.302 10.086 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108187 + CLMA_198_264/Y3 td 0.151 10.237 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/arp_rx_done/opit_0_L5Q_perm/Z + net (fanout=187) 0.449 10.686 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N319 + CLMA_202_272/CECO td 0.132 10.818 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[47]/opit_0/CEOUT + net (fanout=1) 0.000 10.818 ntR2081 + CLMA_202_276/CECO td 0.132 10.950 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[42]/opit_0/CEOUT + net (fanout=6) 0.000 10.950 ntR2080 + CLMA_202_280/CECI f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[14]/opit_0/CE + + Data arrival time 10.950 Logic Levels: 7 + Logic: 1.323ns(32.237%), Route: 2.781ns(67.763%) ---------------------------------------------------------------------------------------------------- Clock eth_rxc (rising edge) 8.000 8.000 r @@ -8926,32 +9754,32 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi IOCKDLY_237_367/CLK_OUT td 2.069 11.262 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT net (fanout=1) 1.493 12.755 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf USCM_84_109/CLK_USCM td 0.000 12.755 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - net (fanout=1861) 0.895 13.650 gmii_clk - CLMA_214_136/CLK r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[0]/opit_0_L5Q_perm/CLK - clock pessimism 1.065 14.715 - clock uncertainty -0.250 14.465 + net (fanout=1862) 1.005 13.760 gmii_clk + CLMA_202_280/CLK r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[14]/opit_0/CLK + clock pessimism 1.067 14.827 + clock uncertainty -0.250 14.577 - Setup time -0.476 13.989 + Setup time -0.576 14.001 - Data required time 13.989 + Data required time 14.001 ---------------------------------------------------------------------------------------------------- - Data required time 13.989 - Data arrival time 10.964 + Data required time 14.001 + Data arrival time 10.950 ---------------------------------------------------------------------------------------------------- - Slack (MET) 3.025 + Slack (MET) 3.051 ==================================================================================================== ==================================================================================================== -Startpoint : udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/CLK -Endpoint : udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[2]/opit_0_L5Q_perm/CE +Startpoint : udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/CLK +Endpoint : udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[22]/opit_0/CE Path Group : eth_rxc Path Type : max (fast corner) Path Class : sequential timing path Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.650 - Launch Clock Delay : 6.734 - Clock Pessimism Removal : 1.065 + Capture Clock Delay : 5.760 + Launch Clock Delay : 6.846 + Clock Pessimism Removal : 1.067 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -8966,35 +9794,29 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi IOCKDLY_237_367/CLK_OUT td 2.942 4.288 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT net (fanout=1) 1.521 5.809 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf USCM_84_109/CLK_USCM td 0.000 5.809 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - net (fanout=1861) 0.925 6.734 gmii_clk - CLMA_202_140/CLK r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/CLK - - CLMA_202_140/Q2 tco 0.224 6.958 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/Q - net (fanout=2) 0.305 7.263 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num [2] - td 0.365 7.628 f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_1/gateop_A2/Cout - net (fanout=1) 0.000 7.628 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [2] - CLMA_214_140/COUT td 0.044 7.672 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_3/gateop_A2/Cout - net (fanout=1) 0.000 7.672 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [4] - td 0.044 7.716 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_5/gateop_A2/Cout - net (fanout=1) 0.000 7.716 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [6] - CLMA_214_144/COUT td 0.044 7.760 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_7/gateop_A2/Cout - net (fanout=1) 0.000 7.760 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [8] - td 0.044 7.804 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_9/gateop_A2/Cout - net (fanout=1) 0.000 7.804 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [10] - CLMA_214_148/COUT td 0.044 7.848 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_11/gateop_A2/Cout - net (fanout=1) 0.000 7.848 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [12] - CLMA_214_152/Y0 td 0.206 8.054 f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_13/gateop_A2/Y0 - net (fanout=1) 0.468 8.522 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276 [13] - CLMA_210_141/Y3 td 0.431 8.953 f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N277.eq_6/gateop_A2/Y1 - net (fanout=18) 0.529 9.482 _N79 - CLMS_186_153/Y2 td 0.381 9.863 f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_pkt_done/opit_0_L5Q_perm/Z - net (fanout=1) 0.304 10.167 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N323 - CLMA_194_160/Y1 td 0.244 10.411 f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839/gateop_perm/Z - net (fanout=16) 0.553 10.964 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839 - CLMA_214_136/CE f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[2]/opit_0_L5Q_perm/CE - - Data arrival time 10.964 Logic Levels: 7 - Logic: 2.071ns(48.960%), Route: 2.159ns(51.040%) + net (fanout=1862) 1.037 6.846 gmii_clk + CLMA_194_261/CLK r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/CLK + + CLMA_194_261/Q0 tco 0.221 7.067 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/Q + net (fanout=2) 0.560 7.627 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t [0] + CLMA_182_241/Y1 td 0.224 7.851 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_39/gateop_perm/Z + net (fanout=1) 0.458 8.309 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108159 + CLMA_190_252/Y3 td 0.151 8.460 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_59/gateop_perm/Z + net (fanout=1) 0.367 8.827 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108179 + CLMA_190_240/Y2 td 0.150 8.977 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_63/gateop_perm/Z + net (fanout=2) 0.645 9.622 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446 + CLMA_210_265/Y3 td 0.162 9.784 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N289_6/gateop_perm/Z + net (fanout=6) 0.302 10.086 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108187 + CLMA_198_264/Y3 td 0.151 10.237 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/arp_rx_done/opit_0_L5Q_perm/Z + net (fanout=187) 0.449 10.686 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N319 + CLMA_202_272/CECO td 0.132 10.818 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[47]/opit_0/CEOUT + net (fanout=1) 0.000 10.818 ntR2081 + CLMA_202_276/CECO td 0.132 10.950 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[42]/opit_0/CEOUT + net (fanout=6) 0.000 10.950 ntR2080 + CLMA_202_280/CECI f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[22]/opit_0/CE + + Data arrival time 10.950 Logic Levels: 7 + Logic: 1.323ns(32.237%), Route: 2.781ns(67.763%) ---------------------------------------------------------------------------------------------------- Clock eth_rxc (rising edge) 8.000 8.000 r @@ -9007,32 +9829,32 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi IOCKDLY_237_367/CLK_OUT td 2.069 11.262 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT net (fanout=1) 1.493 12.755 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf USCM_84_109/CLK_USCM td 0.000 12.755 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - net (fanout=1861) 0.895 13.650 gmii_clk - CLMA_214_136/CLK r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[2]/opit_0_L5Q_perm/CLK - clock pessimism 1.065 14.715 - clock uncertainty -0.250 14.465 + net (fanout=1862) 1.005 13.760 gmii_clk + CLMA_202_280/CLK r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[22]/opit_0/CLK + clock pessimism 1.067 14.827 + clock uncertainty -0.250 14.577 - Setup time -0.476 13.989 + Setup time -0.576 14.001 - Data required time 13.989 + Data required time 14.001 ---------------------------------------------------------------------------------------------------- - Data required time 13.989 - Data arrival time 10.964 + Data required time 14.001 + Data arrival time 10.950 ---------------------------------------------------------------------------------------------------- - Slack (MET) 3.025 + Slack (MET) 3.051 ==================================================================================================== ==================================================================================================== -Startpoint : udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/CLK -Endpoint : udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[5]/opit_0_L5Q_perm/CE +Startpoint : udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/CLK +Endpoint : udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[29]/opit_0/CE Path Group : eth_rxc Path Type : max (fast corner) Path Class : sequential timing path Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.650 - Launch Clock Delay : 6.734 - Clock Pessimism Removal : 1.065 + Capture Clock Delay : 5.760 + Launch Clock Delay : 6.846 + Clock Pessimism Removal : 1.067 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -9047,35 +9869,29 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi IOCKDLY_237_367/CLK_OUT td 2.942 4.288 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT net (fanout=1) 1.521 5.809 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf USCM_84_109/CLK_USCM td 0.000 5.809 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - net (fanout=1861) 0.925 6.734 gmii_clk - CLMA_202_140/CLK r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/CLK - - CLMA_202_140/Q2 tco 0.224 6.958 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/Q - net (fanout=2) 0.305 7.263 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num [2] - td 0.365 7.628 f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_1/gateop_A2/Cout - net (fanout=1) 0.000 7.628 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [2] - CLMA_214_140/COUT td 0.044 7.672 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_3/gateop_A2/Cout - net (fanout=1) 0.000 7.672 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [4] - td 0.044 7.716 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_5/gateop_A2/Cout - net (fanout=1) 0.000 7.716 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [6] - CLMA_214_144/COUT td 0.044 7.760 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_7/gateop_A2/Cout - net (fanout=1) 0.000 7.760 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [8] - td 0.044 7.804 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_9/gateop_A2/Cout - net (fanout=1) 0.000 7.804 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [10] - CLMA_214_148/COUT td 0.044 7.848 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_11/gateop_A2/Cout - net (fanout=1) 0.000 7.848 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [12] - CLMA_214_152/Y0 td 0.206 8.054 f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_13/gateop_A2/Y0 - net (fanout=1) 0.468 8.522 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276 [13] - CLMA_210_141/Y3 td 0.431 8.953 f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N277.eq_6/gateop_A2/Y1 - net (fanout=18) 0.529 9.482 _N79 - CLMS_186_153/Y2 td 0.381 9.863 f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_pkt_done/opit_0_L5Q_perm/Z - net (fanout=1) 0.304 10.167 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N323 - CLMA_194_160/Y1 td 0.244 10.411 f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839/gateop_perm/Z - net (fanout=16) 0.553 10.964 udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839 - CLMA_214_136/CE f udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[5]/opit_0_L5Q_perm/CE - - Data arrival time 10.964 Logic Levels: 7 - Logic: 2.071ns(48.960%), Route: 2.159ns(51.040%) + net (fanout=1862) 1.037 6.846 gmii_clk + CLMA_194_261/CLK r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/CLK + + CLMA_194_261/Q0 tco 0.221 7.067 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/Q + net (fanout=2) 0.560 7.627 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t [0] + CLMA_182_241/Y1 td 0.224 7.851 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_39/gateop_perm/Z + net (fanout=1) 0.458 8.309 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108159 + CLMA_190_252/Y3 td 0.151 8.460 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_59/gateop_perm/Z + net (fanout=1) 0.367 8.827 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108179 + CLMA_190_240/Y2 td 0.150 8.977 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_63/gateop_perm/Z + net (fanout=2) 0.645 9.622 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446 + CLMA_210_265/Y3 td 0.162 9.784 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N289_6/gateop_perm/Z + net (fanout=6) 0.302 10.086 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108187 + CLMA_198_264/Y3 td 0.151 10.237 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/arp_rx_done/opit_0_L5Q_perm/Z + net (fanout=187) 0.449 10.686 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N319 + CLMA_202_272/CECO td 0.132 10.818 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[47]/opit_0/CEOUT + net (fanout=1) 0.000 10.818 ntR2081 + CLMA_202_276/CECO td 0.132 10.950 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[42]/opit_0/CEOUT + net (fanout=6) 0.000 10.950 ntR2080 + CLMA_202_280/CECI f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[29]/opit_0/CE + + Data arrival time 10.950 Logic Levels: 7 + Logic: 1.323ns(32.237%), Route: 2.781ns(67.763%) ---------------------------------------------------------------------------------------------------- Clock eth_rxc (rising edge) 8.000 8.000 r @@ -9088,32 +9904,32 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi IOCKDLY_237_367/CLK_OUT td 2.069 11.262 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT net (fanout=1) 1.493 12.755 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf USCM_84_109/CLK_USCM td 0.000 12.755 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - net (fanout=1861) 0.895 13.650 gmii_clk - CLMA_214_136/CLK r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[5]/opit_0_L5Q_perm/CLK - clock pessimism 1.065 14.715 - clock uncertainty -0.250 14.465 + net (fanout=1862) 1.005 13.760 gmii_clk + CLMA_202_280/CLK r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[29]/opit_0/CLK + clock pessimism 1.067 14.827 + clock uncertainty -0.250 14.577 - Setup time -0.476 13.989 + Setup time -0.576 14.001 - Data required time 13.989 + Data required time 14.001 ---------------------------------------------------------------------------------------------------- - Data required time 13.989 - Data arrival time 10.964 + Data required time 14.001 + Data arrival time 10.950 ---------------------------------------------------------------------------------------------------- - Slack (MET) 3.025 + Slack (MET) 3.051 ==================================================================================================== ==================================================================================================== -Startpoint : udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[4]/opit_0/CLK -Endpoint : udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/DA0[4] +Startpoint : udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[30]/opit_0/CLK +Endpoint : udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][6]/opit_0/D Path Group : eth_rxc Path Type : min (fast corner) Path Class : sequential timing path Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 6.734 - Launch Clock Delay : 5.650 - Clock Pessimism Removal : -1.065 + Capture Clock Delay : 6.846 + Launch Clock Delay : 5.760 + Clock Pessimism Removal : -1.067 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -9128,15 +9944,15 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOCKDLY_237_367/CLK_OUT td 2.069 3.262 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT net (fanout=1) 1.493 4.755 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf USCM_84_109/CLK_USCM td 0.000 4.755 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - net (fanout=1861) 0.895 5.650 gmii_clk - CLMA_210_200/CLK r udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[4]/opit_0/CLK + net (fanout=1862) 1.005 5.760 gmii_clk + CLMA_194_288/CLK r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[30]/opit_0/CLK - CLMA_210_200/Q2 tco 0.183 5.833 r udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[4]/opit_0/Q - net (fanout=1) 0.390 6.223 udp_osd_inst/eth_udp_inst/rec_data [4] - DRM_234_192/DA0[4] r udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/DA0[4] + CLMA_194_288/Q0 tco 0.182 5.942 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[30]/opit_0/Q + net (fanout=3) 0.146 6.088 udp_osd_inst/eth_udp_inst/des_ip [30] + CLMA_198_288/AD r udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][6]/opit_0/D - Data arrival time 6.223 Logic Levels: 0 - Logic: 0.183ns(31.937%), Route: 0.390ns(68.063%) + Data arrival time 6.088 Logic Levels: 0 + Logic: 0.182ns(55.488%), Route: 0.146ns(44.512%) ---------------------------------------------------------------------------------------------------- Clock eth_rxc (rising edge) 0.000 0.000 r @@ -9149,25 +9965,25 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOCKDLY_237_367/CLK_OUT td 2.942 4.288 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT net (fanout=1) 1.521 5.809 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf USCM_84_109/CLK_USCM td 0.000 5.809 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - net (fanout=1861) 0.925 6.734 gmii_clk - DRM_234_192/CLKA[0] r udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] - clock pessimism -1.065 5.669 - clock uncertainty 0.200 5.869 + net (fanout=1862) 1.037 6.846 gmii_clk + CLMA_198_288/CLK r udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][6]/opit_0/CLK + clock pessimism -1.067 5.779 + clock uncertainty 0.200 5.979 - Hold time 0.102 5.971 + Hold time 0.034 6.013 - Data required time 5.971 + Data required time 6.013 ---------------------------------------------------------------------------------------------------- - Data required time 5.971 - Data arrival time 6.223 + Data required time 6.013 + Data arrival time 6.088 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.252 + Slack (MET) 0.075 ==================================================================================================== ==================================================================================================== -Startpoint : udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[3]/opit_0/CLK -Endpoint : udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/DA0[3] +Startpoint : udp_wr_mem_inst/mem[190]/opit_0/CLK +Endpoint : param_manager_inst/param_modify_V/value[6]/opit_0_L5Q_perm/L0 Path Group : eth_rxc Path Type : min (fast corner) Path Class : sequential timing path @@ -9189,15 +10005,15 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOCKDLY_237_367/CLK_OUT td 2.069 3.262 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT net (fanout=1) 1.493 4.755 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf USCM_84_109/CLK_USCM td 0.000 4.755 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - net (fanout=1861) 0.895 5.650 gmii_clk - CLMA_210_201/CLK r udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[3]/opit_0/CLK + net (fanout=1862) 0.895 5.650 gmii_clk + CLMS_222_217/CLK r udp_wr_mem_inst/mem[190]/opit_0/CLK - CLMA_210_201/Q0 tco 0.182 5.832 r udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[3]/opit_0/Q - net (fanout=1) 0.393 6.225 udp_osd_inst/eth_udp_inst/rec_data [3] - DRM_234_192/DA0[3] r udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/DA0[3] + CLMS_222_217/Q1 tco 0.184 5.834 r udp_wr_mem_inst/mem[190]/opit_0/Q + net (fanout=1) 0.212 6.046 mem[190] + CLMA_230_212/C0 r param_manager_inst/param_modify_V/value[6]/opit_0_L5Q_perm/L0 - Data arrival time 6.225 Logic Levels: 0 - Logic: 0.182ns(31.652%), Route: 0.393ns(68.348%) + Data arrival time 6.046 Logic Levels: 0 + Logic: 0.184ns(46.465%), Route: 0.212ns(53.535%) ---------------------------------------------------------------------------------------------------- Clock eth_rxc (rising edge) 0.000 0.000 r @@ -9210,32 +10026,32 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOCKDLY_237_367/CLK_OUT td 2.942 4.288 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT net (fanout=1) 1.521 5.809 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf USCM_84_109/CLK_USCM td 0.000 5.809 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - net (fanout=1861) 0.925 6.734 gmii_clk - DRM_234_192/CLKA[0] r udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] + net (fanout=1862) 0.925 6.734 gmii_clk + CLMA_230_212/CLK r param_manager_inst/param_modify_V/value[6]/opit_0_L5Q_perm/CLK clock pessimism -1.065 5.669 clock uncertainty 0.200 5.869 - Hold time 0.102 5.971 + Hold time -0.078 5.791 - Data required time 5.971 + Data required time 5.791 ---------------------------------------------------------------------------------------------------- - Data required time 5.971 - Data arrival time 6.225 + Data required time 5.791 + Data arrival time 6.046 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.254 + Slack (MET) 0.255 ==================================================================================================== ==================================================================================================== -Startpoint : udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[7]/opit_0/CLK -Endpoint : udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[8]/opit_0_A2Q21/I01 +Startpoint : udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[17]/opit_0_L5Q_perm/CLK +Endpoint : udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[25]/opit_0_L5Q_perm/L1 Path Group : eth_rxc Path Type : min (fast corner) Path Class : sequential timing path -Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 6.734 - Launch Clock Delay : 5.650 - Clock Pessimism Removal : -1.065 +Clock Skew : 0.015 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 6.846 + Launch Clock Delay : 5.760 + Clock Pessimism Removal : -1.071 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -9250,1629 +10066,2069 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOCKDLY_237_367/CLK_OUT td 2.069 3.262 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT net (fanout=1) 1.493 4.755 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf USCM_84_109/CLK_USCM td 0.000 4.755 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - net (fanout=1861) 0.895 5.650 gmii_clk - CLMA_182_209/CLK r udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[7]/opit_0/CLK + net (fanout=1862) 1.005 5.760 gmii_clk + CLMA_186_264/CLK r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[17]/opit_0_L5Q_perm/CLK + + CLMA_186_264/Q2 tco 0.183 5.943 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[17]/opit_0_L5Q_perm/Q + net (fanout=2) 0.194 6.137 udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t [17] + CLMS_186_265/A1 r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[25]/opit_0_L5Q_perm/L1 + + Data arrival time 6.137 Logic Levels: 0 + Logic: 0.183ns(48.541%), Route: 0.194ns(51.459%) +---------------------------------------------------------------------------------------------------- + + Clock eth_rxc (rising edge) 0.000 0.000 r + F14 0.000 0.000 r eth_rxc (port) + net (fanout=1) 0.057 0.057 eth_rxc + IOBD_240_376/DIN td 0.861 0.918 r eth_rxc_ibuf/opit_0/O + net (fanout=1) 0.000 0.918 eth_rxc_ibuf/ntD + IOL_243_374/INCK td 0.058 0.976 r eth_rxc_ibuf/opit_1/INCK + net (fanout=1) 0.370 1.346 _N66 + IOCKDLY_237_367/CLK_OUT td 2.942 4.288 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT + net (fanout=1) 1.521 5.809 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf + USCM_84_109/CLK_USCM td 0.000 5.809 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT + net (fanout=1862) 1.037 6.846 gmii_clk + CLMS_186_265/CLK r udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[25]/opit_0_L5Q_perm/CLK + clock pessimism -1.071 5.775 + clock uncertainty 0.200 5.975 + + Hold time -0.093 5.882 + + Data required time 5.882 +---------------------------------------------------------------------------------------------------- + Data required time 5.882 + Data arrival time 6.137 +---------------------------------------------------------------------------------------------------- + Slack (MET) 0.255 +==================================================================================================== + +==================================================================================================== + +Startpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB +Endpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/L4 +Path Group : clk_50m +Path Type : max (fast corner) +Path Class : sequential timing path +Clock Skew : -0.035 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 3.448 + Launch Clock Delay : 3.764 + Clock Pessimism Removal : 0.281 + + Location Delay Type Incr Path Logical Resource +---------------------------------------------------------------------------------------------------- + + Clock clk_50m (rising edge) 0.000 0.000 r + P20 0.000 0.000 r clk (port) + net (fanout=1) 0.074 0.074 clk + IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 1.578 clk_ibuf/ntD + IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.478 2.114 _N69 + PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.614 2.811 rd3_clk + USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT + net (fanout=2516) 0.953 3.764 ntclkbufg_1 + DRM_54_24/CLKB[0] r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB + + DRM_54_24/QB0[0] tco 1.780 5.544 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/DOB[0] + net (fanout=6) 0.982 6.526 u_rotate_image/dout [0] + CLMS_74_117/Y1 td 0.359 6.885 f u_rotate_image/addr_fifo_valid/opit_0_L5Q_perm/Z + net (fanout=3) 1.071 7.956 u_rotate_image/addr_fifo_rd_en + td 0.222 8.178 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/Cout + net (fanout=1) 0.000 8.178 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16576 + CLMS_50_33/COUT td 0.044 8.222 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/Cout + net (fanout=1) 0.000 8.222 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16578 + CLMS_50_37/Y1 td 0.383 8.605 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/Y1 + net (fanout=1) 0.325 8.930 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11 [5] + CLMA_58_29/Y1 td 0.360 9.290 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[5]/gateop_perm/Z + net (fanout=3) 0.392 9.682 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/rrptr [5] + CLMA_58_36/COUT td 0.394 10.076 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_2/gateop_A2/Cout + net (fanout=1) 0.000 10.076 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.co [6] + CLMA_58_40/Y1 td 0.383 10.459 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_4/gateop_A2/Y1 + net (fanout=1) 0.072 10.531 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21 + CLMA_58_40/C4 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/L4 + + Data arrival time 10.531 Logic Levels: 6 + Logic: 3.925ns(58.002%), Route: 2.842ns(41.998%) +---------------------------------------------------------------------------------------------------- + + Clock clk_50m (rising edge) 20.000 20.000 r + P20 0.000 20.000 r clk (port) + net (fanout=1) 0.074 20.074 clk + IOBS_LR_328_209/DIN td 1.285 21.359 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 21.359 clk_ibuf/ntD + IOL_327_210/INCK td 0.038 21.397 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.463 21.860 _N69 + PLL_158_55/CLK_OUT0 td 0.078 21.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.603 22.541 rd3_clk + USCM_84_108/CLK_USCM td 0.000 22.541 r clkbufg_1/gopclkbufg/CLKOUT + net (fanout=2516) 0.907 23.448 ntclkbufg_1 + CLMA_58_40/CLK r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK + clock pessimism 0.281 23.729 + clock uncertainty -0.150 23.579 + + Setup time -0.094 23.485 + + Data required time 23.485 +---------------------------------------------------------------------------------------------------- + Data required time 23.485 + Data arrival time 10.531 +---------------------------------------------------------------------------------------------------- + Slack (MET) 12.954 +==================================================================================================== + +==================================================================================================== + +Startpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB +Endpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/Cin +Path Group : clk_50m +Path Type : max (fast corner) +Path Class : sequential timing path +Clock Skew : -0.039 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 3.444 + Launch Clock Delay : 3.764 + Clock Pessimism Removal : 0.281 + + Location Delay Type Incr Path Logical Resource +---------------------------------------------------------------------------------------------------- + + Clock clk_50m (rising edge) 0.000 0.000 r + P20 0.000 0.000 r clk (port) + net (fanout=1) 0.074 0.074 clk + IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 1.578 clk_ibuf/ntD + IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.478 2.114 _N69 + PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.614 2.811 rd3_clk + USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT + net (fanout=2516) 0.953 3.764 ntclkbufg_1 + DRM_54_24/CLKB[0] r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB + + DRM_54_24/QB0[0] tco 1.780 5.544 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/DOB[0] + net (fanout=6) 0.982 6.526 u_rotate_image/dout [0] + CLMS_74_117/Y1 td 0.359 6.885 f u_rotate_image/addr_fifo_valid/opit_0_L5Q_perm/Z + net (fanout=3) 1.071 7.956 u_rotate_image/addr_fifo_rd_en + td 0.222 8.178 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/Cout + net (fanout=1) 0.000 8.178 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16576 + CLMS_50_33/COUT td 0.044 8.222 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/Cout + net (fanout=1) 0.000 8.222 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16578 + CLMS_50_37/Y1 td 0.383 8.605 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/Y1 + net (fanout=1) 0.325 8.930 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11 [5] + CLMA_58_29/Y1 td 0.360 9.290 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[5]/gateop_perm/Z + net (fanout=3) 0.257 9.547 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/rrptr [5] + CLMA_62_32/COUT td 0.394 9.941 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N24.eq_2/gateop_A2/Cout + net (fanout=1) 0.000 9.941 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N24.co [6] + CLMA_62_36/CIN r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/Cin + + Data arrival time 9.941 Logic Levels: 5 + Logic: 3.542ns(57.342%), Route: 2.635ns(42.658%) +---------------------------------------------------------------------------------------------------- + + Clock clk_50m (rising edge) 20.000 20.000 r + P20 0.000 20.000 r clk (port) + net (fanout=1) 0.074 20.074 clk + IOBS_LR_328_209/DIN td 1.285 21.359 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 21.359 clk_ibuf/ntD + IOL_327_210/INCK td 0.038 21.397 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.463 21.860 _N69 + PLL_158_55/CLK_OUT0 td 0.078 21.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.603 22.541 rd3_clk + USCM_84_108/CLK_USCM td 0.000 22.541 r clkbufg_1/gopclkbufg/CLKOUT + net (fanout=2516) 0.903 23.444 ntclkbufg_1 + CLMA_62_36/CLK r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/CLK + clock pessimism 0.281 23.725 + clock uncertainty -0.150 23.575 + + Setup time -0.276 23.299 + + Data required time 23.299 +---------------------------------------------------------------------------------------------------- + Data required time 23.299 + Data arrival time 9.941 +---------------------------------------------------------------------------------------------------- + Slack (MET) 13.358 +==================================================================================================== + +==================================================================================================== + +Startpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB +Endpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[11]/opit_0_A2Q21/Cin +Path Group : clk_50m +Path Type : max (fast corner) +Path Class : sequential timing path +Clock Skew : -0.035 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 3.448 + Launch Clock Delay : 3.764 + Clock Pessimism Removal : 0.281 + + Location Delay Type Incr Path Logical Resource +---------------------------------------------------------------------------------------------------- + + Clock clk_50m (rising edge) 0.000 0.000 r + P20 0.000 0.000 r clk (port) + net (fanout=1) 0.074 0.074 clk + IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 1.578 clk_ibuf/ntD + IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.478 2.114 _N69 + PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.614 2.811 rd3_clk + USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT + net (fanout=2516) 0.953 3.764 ntclkbufg_1 + DRM_54_24/CLKB[0] r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB + + DRM_54_24/QB0[0] tco 1.780 5.544 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/DOB[0] + net (fanout=6) 0.982 6.526 u_rotate_image/dout [0] + CLMS_74_117/Y1 td 0.359 6.885 f u_rotate_image/addr_fifo_valid/opit_0_L5Q_perm/Z + net (fanout=3) 1.071 7.956 u_rotate_image/addr_fifo_rd_en + td 0.222 8.178 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/Cout + net (fanout=1) 0.000 8.178 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16576 + CLMS_50_33/COUT td 0.044 8.222 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/Cout + net (fanout=1) 0.000 8.222 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16578 + CLMS_50_37/Y1 td 0.383 8.605 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/Y1 + net (fanout=1) 0.325 8.930 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11 [5] + CLMA_58_29/Y1 td 0.360 9.290 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[5]/gateop_perm/Z + net (fanout=3) 0.364 9.654 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/rrptr [5] + td 0.250 9.904 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[5]/opit_0_A2Q21/Cout + net (fanout=1) 0.000 9.904 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N138_5.co [6] + CLMA_58_37/COUT td 0.044 9.948 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[7]/opit_0_A2Q21/Cout + net (fanout=1) 0.000 9.948 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N138_5.co [8] + td 0.044 9.992 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[9]/opit_0_A2Q21/Cout + net (fanout=1) 0.000 9.992 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N138_5.co [10] + r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[11]/opit_0_A2Q21/Cin + + Data arrival time 9.992 Logic Levels: 5 + Logic: 3.486ns(55.973%), Route: 2.742ns(44.027%) +---------------------------------------------------------------------------------------------------- + + Clock clk_50m (rising edge) 20.000 20.000 r + P20 0.000 20.000 r clk (port) + net (fanout=1) 0.074 20.074 clk + IOBS_LR_328_209/DIN td 1.285 21.359 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 21.359 clk_ibuf/ntD + IOL_327_210/INCK td 0.038 21.397 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.463 21.860 _N69 + PLL_158_55/CLK_OUT0 td 0.078 21.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.603 22.541 rd3_clk + USCM_84_108/CLK_USCM td 0.000 22.541 r clkbufg_1/gopclkbufg/CLKOUT + net (fanout=2516) 0.907 23.448 ntclkbufg_1 + CLMA_58_41/CLK r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[11]/opit_0_A2Q21/CLK + clock pessimism 0.281 23.729 + clock uncertainty -0.150 23.579 + + Setup time -0.128 23.451 + + Data required time 23.451 +---------------------------------------------------------------------------------------------------- + Data required time 23.451 + Data arrival time 9.992 +---------------------------------------------------------------------------------------------------- + Slack (MET) 13.459 +==================================================================================================== + +==================================================================================================== + +Startpoint : u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK +Endpoint : u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[10] +Path Group : clk_50m +Path Type : min (fast corner) +Path Class : sequential timing path +Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 3.736 + Launch Clock Delay : 3.436 + Clock Pessimism Removal : -0.281 + + Location Delay Type Incr Path Logical Resource +---------------------------------------------------------------------------------------------------- + + Clock clk_50m (rising edge) 0.000 0.000 r + P20 0.000 0.000 r clk (port) + net (fanout=1) 0.074 0.074 clk + IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 1.359 clk_ibuf/ntD + IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.463 1.860 _N69 + PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.603 2.541 rd3_clk + USCM_84_108/CLK_USCM td 0.000 2.541 r clkbufg_1/gopclkbufg/CLKOUT + net (fanout=2516) 0.895 3.436 ntclkbufg_1 + CLMS_50_117/CLK r u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK + + CLMS_50_117/Q0 tco 0.182 3.618 r u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/Q0 + net (fanout=5) 0.146 3.764 u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/wr_addr [8] + DRM_54_108/ADA0[10] r u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[10] + + Data arrival time 3.764 Logic Levels: 0 + Logic: 0.182ns(55.488%), Route: 0.146ns(44.512%) +---------------------------------------------------------------------------------------------------- + + Clock clk_50m (rising edge) 0.000 0.000 r + P20 0.000 0.000 r clk (port) + net (fanout=1) 0.074 0.074 clk + IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 1.578 clk_ibuf/ntD + IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.478 2.114 _N69 + PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.614 2.811 rd3_clk + USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT + net (fanout=2516) 0.925 3.736 ntclkbufg_1 + DRM_54_108/CLKA[0] r u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKA + clock pessimism -0.281 3.455 + clock uncertainty 0.000 3.455 + + Hold time 0.166 3.621 + + Data required time 3.621 +---------------------------------------------------------------------------------------------------- + Data required time 3.621 + Data arrival time 3.764 +---------------------------------------------------------------------------------------------------- + Slack (MET) 0.143 +==================================================================================================== + +==================================================================================================== + +Startpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK +Endpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[2] +Path Group : clk_50m +Path Type : min (fast corner) +Path Class : sequential timing path +Clock Skew : 0.008 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 3.760 + Launch Clock Delay : 3.471 + Clock Pessimism Removal : -0.281 + + Location Delay Type Incr Path Logical Resource +---------------------------------------------------------------------------------------------------- + + Clock clk_50m (rising edge) 0.000 0.000 r + P20 0.000 0.000 r clk (port) + net (fanout=1) 0.074 0.074 clk + IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 1.359 clk_ibuf/ntD + IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.463 1.860 _N69 + PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.603 2.541 rd3_clk + USCM_84_108/CLK_USCM td 0.000 2.541 r clkbufg_1/gopclkbufg/CLKOUT + net (fanout=2516) 0.930 3.471 ntclkbufg_1 + CLMA_50_32/CLK r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK + + CLMA_50_32/Q0 tco 0.182 3.653 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Q0 + net (fanout=4) 0.143 3.796 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/wr_addr [0] + DRM_54_24/ADA0[2] r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[2] + + Data arrival time 3.796 Logic Levels: 0 + Logic: 0.182ns(56.000%), Route: 0.143ns(44.000%) +---------------------------------------------------------------------------------------------------- + + Clock clk_50m (rising edge) 0.000 0.000 r + P20 0.000 0.000 r clk (port) + net (fanout=1) 0.074 0.074 clk + IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 1.578 clk_ibuf/ntD + IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.478 2.114 _N69 + PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.614 2.811 rd3_clk + USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT + net (fanout=2516) 0.949 3.760 ntclkbufg_1 + DRM_54_24/CLKA[0] r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKA + clock pessimism -0.281 3.479 + clock uncertainty 0.000 3.479 + + Hold time 0.144 3.623 + + Data required time 3.623 +---------------------------------------------------------------------------------------------------- + Data required time 3.623 + Data arrival time 3.796 +---------------------------------------------------------------------------------------------------- + Slack (MET) 0.173 +==================================================================================================== + +==================================================================================================== + +Startpoint : image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK +Endpoint : image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/ADA0[4] +Path Group : clk_50m +Path Type : min (fast corner) +Path Class : sequential timing path +Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 3.848 + Launch Clock Delay : 3.546 + Clock Pessimism Removal : -0.283 + + Location Delay Type Incr Path Logical Resource +---------------------------------------------------------------------------------------------------- + + Clock clk_50m (rising edge) 0.000 0.000 r + P20 0.000 0.000 r clk (port) + net (fanout=1) 0.074 0.074 clk + IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 1.359 clk_ibuf/ntD + IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.463 1.860 _N69 + PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.603 2.541 rd3_clk + USCM_84_108/CLK_USCM td 0.000 2.541 r clkbufg_1/gopclkbufg/CLKOUT + net (fanout=2516) 1.005 3.546 ntclkbufg_1 + CLMS_78_305/CLK r image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK - CLMA_182_209/Q3 tco 0.182 5.832 r udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[7]/opit_0/Q - net (fanout=2) 0.199 6.031 udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length [7] - CLMA_186_208/A1 r udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[8]/opit_0_A2Q21/I01 + CLMS_78_305/Q1 tco 0.184 3.730 r image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Q1 + net (fanout=4) 0.142 3.872 image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/wr_addr [1] + DRM_82_292/ADA0[4] r image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/ADA0[4] - Data arrival time 6.031 Logic Levels: 0 - Logic: 0.182ns(47.769%), Route: 0.199ns(52.231%) + Data arrival time 3.872 Logic Levels: 0 + Logic: 0.184ns(56.442%), Route: 0.142ns(43.558%) ---------------------------------------------------------------------------------------------------- - Clock eth_rxc (rising edge) 0.000 0.000 r - F14 0.000 0.000 r eth_rxc (port) - net (fanout=1) 0.057 0.057 eth_rxc - IOBD_240_376/DIN td 0.861 0.918 r eth_rxc_ibuf/opit_0/O - net (fanout=1) 0.000 0.918 eth_rxc_ibuf/ntD - IOL_243_374/INCK td 0.058 0.976 r eth_rxc_ibuf/opit_1/INCK - net (fanout=1) 0.370 1.346 _N66 - IOCKDLY_237_367/CLK_OUT td 2.942 4.288 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT - net (fanout=1) 1.521 5.809 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf - USCM_84_109/CLK_USCM td 0.000 5.809 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - net (fanout=1861) 0.925 6.734 gmii_clk - CLMA_186_208/CLK r udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[8]/opit_0_A2Q21/CLK - clock pessimism -1.065 5.669 - clock uncertainty 0.200 5.869 + Clock clk_50m (rising edge) 0.000 0.000 r + P20 0.000 0.000 r clk (port) + net (fanout=1) 0.074 0.074 clk + IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 1.578 clk_ibuf/ntD + IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.478 2.114 _N69 + PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.614 2.811 rd3_clk + USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT + net (fanout=2516) 1.037 3.848 ntclkbufg_1 + DRM_82_292/CLKA[0] r image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] + clock pessimism -0.283 3.565 + clock uncertainty 0.000 3.565 - Hold time -0.093 5.776 + Hold time 0.127 3.692 - Data required time 5.776 + Data required time 3.692 ---------------------------------------------------------------------------------------------------- - Data required time 5.776 - Data arrival time 6.031 + Data required time 3.692 + Data arrival time 3.872 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.255 + Slack (MET) 0.180 ==================================================================================================== ==================================================================================================== -Startpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB -Endpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/L4 -Path Group : clk_50m +Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[16]/opit_0_inv_L5Q_perm/CE +Path Group : clk_200m Path Type : max (fast corner) Path Class : sequential timing path -Clock Skew : -0.066 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 3.436 - Launch Clock Delay : 3.783 - Clock Pessimism Removal : 0.281 +Clock Skew : -0.001 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 3.432 + Launch Clock Delay : 3.732 + Clock Pessimism Removal : 0.299 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_50m (rising edge) 0.000 0.000 r + Clock clk_200m (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.578 clk_ibuf/ntD IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 - PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 - net (fanout=2) 0.614 2.811 rd3_clk - USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 0.972 3.783 ntclkbufg_1 - DRM_82_4/CLKB[0] r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB - - DRM_82_4/QB0[0] tco 1.780 5.563 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/DOB[0] - net (fanout=6) 0.946 6.509 u_rotate_image/dout [0] - CLMS_74_73/Y1 td 0.151 6.660 f u_rotate_image/addr_fifo_valid/opit_0_L5Q_perm/Z - net (fanout=3) 0.793 7.453 u_rotate_image/addr_fifo_rd_en - td 0.222 7.675 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/Cout - net (fanout=1) 0.000 7.675 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16637 - CLMS_78_9/Y3 td 0.387 8.062 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/Y1 - net (fanout=1) 0.236 8.298 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11 [3] - CLMS_74_13/Y3 td 0.151 8.449 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[3]/gateop_perm/Z - net (fanout=3) 0.496 8.945 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/rrptr [3] - td 0.368 9.313 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_0/gateop_A2/Cout - net (fanout=1) 0.000 9.313 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.co [2] - CLMA_90_20/COUT td 0.044 9.357 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_2/gateop_A2/Cout - net (fanout=1) 0.000 9.357 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.co [6] - CLMA_90_24/Y1 td 0.366 9.723 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_4/gateop_A2/Y1 - net (fanout=1) 0.353 10.076 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21 - CLMA_94_16/C4 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/L4 - - Data arrival time 10.076 Logic Levels: 5 - Logic: 3.469ns(55.125%), Route: 2.824ns(44.875%) + PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 + net (fanout=2) 0.614 2.807 ddr_clk + USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + net (fanout=71) 0.925 3.732 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + CLMA_90_197/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK + + CLMA_90_197/Q1 tco 0.223 3.955 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/Q + net (fanout=2) 0.259 4.214 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt [15] + CLMS_94_197/Y0 td 0.376 4.590 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_33/gateop_perm/Z + net (fanout=2) 0.075 4.665 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107154 + CLMA_94_196/Y2 td 0.379 5.044 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_36/gateop_perm/Z + net (fanout=1) 0.067 5.111 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107157 + CLMA_94_196/Y3 td 0.222 5.333 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43_3/gateop_perm/Z + net (fanout=11) 0.279 5.612 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43 + CLMA_90_185/CECO td 0.132 5.744 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[8]/opit_0_inv_L5Q_perm/CEOUT + net (fanout=4) 0.000 5.744 ntR1851 + CLMA_90_193/CECO td 0.132 5.876 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[11]/opit_0_inv_L5Q_perm/CEOUT + net (fanout=4) 0.000 5.876 ntR1850 + CLMA_90_197/CECI f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[16]/opit_0_inv_L5Q_perm/CE + + Data arrival time 5.876 Logic Levels: 5 + Logic: 1.464ns(68.284%), Route: 0.680ns(31.716%) ---------------------------------------------------------------------------------------------------- - Clock clk_50m (rising edge) 20.000 20.000 r - P20 0.000 20.000 r clk (port) - net (fanout=1) 0.074 20.074 clk - IOBS_LR_328_209/DIN td 1.285 21.359 r clk_ibuf/opit_0/O - net (fanout=1) 0.000 21.359 clk_ibuf/ntD - IOL_327_210/INCK td 0.038 21.397 r clk_ibuf/opit_1/INCK - net (fanout=1) 0.463 21.860 _N69 - PLL_158_55/CLK_OUT0 td 0.078 21.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 - net (fanout=2) 0.603 22.541 rd3_clk - USCM_84_108/CLK_USCM td 0.000 22.541 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 0.895 23.436 ntclkbufg_1 - CLMA_94_16/CLK r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK - clock pessimism 0.281 23.717 - clock uncertainty -0.150 23.567 + Clock clk_200m (rising edge) 5.000 5.000 r + P20 0.000 5.000 r clk (port) + net (fanout=1) 0.074 5.074 clk + IOBS_LR_328_209/DIN td 1.285 6.359 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 6.359 clk_ibuf/ntD + IOL_327_210/INCK td 0.038 6.397 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.463 6.860 _N69 + PLL_158_55/CLK_OUT1 td 0.074 6.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 + net (fanout=2) 0.603 7.537 ddr_clk + USCM_84_113/CLK_USCM td 0.000 7.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + net (fanout=71) 0.895 8.432 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + CLMA_90_197/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[16]/opit_0_inv_L5Q_perm/CLK + clock pessimism 0.299 8.731 + clock uncertainty -0.150 8.581 - Setup time -0.078 23.489 + Setup time -0.576 8.005 - Data required time 23.489 + Data required time 8.005 ---------------------------------------------------------------------------------------------------- - Data required time 23.489 - Data arrival time 10.076 + Data required time 8.005 + Data arrival time 5.876 ---------------------------------------------------------------------------------------------------- - Slack (MET) 13.413 + Slack (MET) 2.129 ==================================================================================================== ==================================================================================================== -Startpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB -Endpoint : u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/L4 -Path Group : clk_50m +Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[17]/opit_0_inv_L5Q_perm/CE +Path Group : clk_200m Path Type : max (fast corner) Path Class : sequential timing path -Clock Skew : -0.066 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 3.436 - Launch Clock Delay : 3.783 - Clock Pessimism Removal : 0.281 +Clock Skew : -0.001 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 3.432 + Launch Clock Delay : 3.732 + Clock Pessimism Removal : 0.299 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_50m (rising edge) 0.000 0.000 r + Clock clk_200m (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.578 clk_ibuf/ntD IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 - PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 - net (fanout=2) 0.614 2.811 rd3_clk - USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 0.972 3.783 ntclkbufg_1 - DRM_82_4/CLKB[0] r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB - - DRM_82_4/QB0[0] tco 1.780 5.563 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/DOB[0] - net (fanout=6) 0.772 6.335 u_rotate_image/dout [0] - CLMS_74_73/Y3 td 0.358 6.693 f u_rotate_image/fifo_data_valid/opit_0_L5Q_perm/Z - net (fanout=3) 0.535 7.228 u_rotate_image/N170 - td 0.222 7.450 f u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/Cout - net (fanout=1) 0.000 7.450 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16662 - CLMA_58_92/Y3 td 0.387 7.837 r u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/Y1 - net (fanout=1) 0.162 7.999 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11 [3] - CLMA_58_89/Y3 td 0.358 8.357 f u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[3]/gateop_perm/Z - net (fanout=1) 0.478 8.835 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/rrptr [3] - td 0.368 9.203 f u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N24.eq_0/gateop_A2/Cout - net (fanout=1) 0.000 9.203 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N24.co [2] - CLMS_50_93/COUT td 0.044 9.247 r u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N24.eq_2/gateop_A2/Cout - net (fanout=1) 0.000 9.247 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N24.co [6] - CLMS_50_97/Y0 td 0.123 9.370 r u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/Y0 - net (fanout=1) 0.151 9.521 _N70 - CLMS_50_97/C4 r u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/L4 - - Data arrival time 9.521 Logic Levels: 5 - Logic: 3.640ns(63.437%), Route: 2.098ns(36.563%) + PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 + net (fanout=2) 0.614 2.807 ddr_clk + USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + net (fanout=71) 0.925 3.732 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + CLMA_90_197/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK + + CLMA_90_197/Q1 tco 0.223 3.955 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/Q + net (fanout=2) 0.259 4.214 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt [15] + CLMS_94_197/Y0 td 0.376 4.590 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_33/gateop_perm/Z + net (fanout=2) 0.075 4.665 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107154 + CLMA_94_196/Y2 td 0.379 5.044 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_36/gateop_perm/Z + net (fanout=1) 0.067 5.111 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107157 + CLMA_94_196/Y3 td 0.222 5.333 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43_3/gateop_perm/Z + net (fanout=11) 0.279 5.612 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43 + CLMA_90_185/CECO td 0.132 5.744 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[8]/opit_0_inv_L5Q_perm/CEOUT + net (fanout=4) 0.000 5.744 ntR1851 + CLMA_90_193/CECO td 0.132 5.876 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[11]/opit_0_inv_L5Q_perm/CEOUT + net (fanout=4) 0.000 5.876 ntR1850 + CLMA_90_197/CECI f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[17]/opit_0_inv_L5Q_perm/CE + + Data arrival time 5.876 Logic Levels: 5 + Logic: 1.464ns(68.284%), Route: 0.680ns(31.716%) ---------------------------------------------------------------------------------------------------- - Clock clk_50m (rising edge) 20.000 20.000 r - P20 0.000 20.000 r clk (port) - net (fanout=1) 0.074 20.074 clk - IOBS_LR_328_209/DIN td 1.285 21.359 r clk_ibuf/opit_0/O - net (fanout=1) 0.000 21.359 clk_ibuf/ntD - IOL_327_210/INCK td 0.038 21.397 r clk_ibuf/opit_1/INCK - net (fanout=1) 0.463 21.860 _N69 - PLL_158_55/CLK_OUT0 td 0.078 21.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 - net (fanout=2) 0.603 22.541 rd3_clk - USCM_84_108/CLK_USCM td 0.000 22.541 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 0.895 23.436 ntclkbufg_1 - CLMS_50_97/CLK r u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK - clock pessimism 0.281 23.717 - clock uncertainty -0.150 23.567 + Clock clk_200m (rising edge) 5.000 5.000 r + P20 0.000 5.000 r clk (port) + net (fanout=1) 0.074 5.074 clk + IOBS_LR_328_209/DIN td 1.285 6.359 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 6.359 clk_ibuf/ntD + IOL_327_210/INCK td 0.038 6.397 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.463 6.860 _N69 + PLL_158_55/CLK_OUT1 td 0.074 6.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 + net (fanout=2) 0.603 7.537 ddr_clk + USCM_84_113/CLK_USCM td 0.000 7.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + net (fanout=71) 0.895 8.432 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + CLMA_90_197/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[17]/opit_0_inv_L5Q_perm/CLK + clock pessimism 0.299 8.731 + clock uncertainty -0.150 8.581 - Setup time -0.094 23.473 + Setup time -0.576 8.005 - Data required time 23.473 + Data required time 8.005 ---------------------------------------------------------------------------------------------------- - Data required time 23.473 - Data arrival time 9.521 + Data required time 8.005 + Data arrival time 5.876 ---------------------------------------------------------------------------------------------------- - Slack (MET) 13.952 + Slack (MET) 2.129 ==================================================================================================== ==================================================================================================== -Startpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB -Endpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/Cin -Path Group : clk_50m +Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[18]/opit_0_inv_L5Q_perm/CE +Path Group : clk_200m Path Type : max (fast corner) Path Class : sequential timing path -Clock Skew : -0.066 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 3.436 - Launch Clock Delay : 3.783 - Clock Pessimism Removal : 0.281 +Clock Skew : -0.001 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 3.432 + Launch Clock Delay : 3.732 + Clock Pessimism Removal : 0.299 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_50m (rising edge) 0.000 0.000 r + Clock clk_200m (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.578 clk_ibuf/ntD IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 - PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 - net (fanout=2) 0.614 2.811 rd3_clk - USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 0.972 3.783 ntclkbufg_1 - DRM_82_4/CLKB[0] r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB - - DRM_82_4/QB0[0] tco 1.780 5.563 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/DOB[0] - net (fanout=6) 0.946 6.509 u_rotate_image/dout [0] - CLMS_74_73/Y1 td 0.151 6.660 f u_rotate_image/addr_fifo_valid/opit_0_L5Q_perm/Z - net (fanout=3) 0.793 7.453 u_rotate_image/addr_fifo_rd_en - td 0.222 7.675 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/Cout - net (fanout=1) 0.000 7.675 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16637 - CLMS_78_9/COUT td 0.044 7.719 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/Cout - net (fanout=1) 0.000 7.719 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16639 - td 0.044 7.763 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/Cout - net (fanout=1) 0.000 7.763 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16641 - CLMS_78_13/Y3 td 0.387 8.150 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/Y1 - net (fanout=1) 0.234 8.384 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11 [7] - CLMS_74_13/Y1 td 0.151 8.535 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[7]/gateop_perm/Z - net (fanout=3) 0.323 8.858 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/rrptr [7] - CLMA_94_12/COUT td 0.397 9.255 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N24.eq_2/gateop_A2/Cout - net (fanout=1) 0.000 9.255 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N24.co [6] - CLMA_94_16/CIN r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/Cin - - Data arrival time 9.255 Logic Levels: 5 - Logic: 3.176ns(58.041%), Route: 2.296ns(41.959%) + PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 + net (fanout=2) 0.614 2.807 ddr_clk + USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + net (fanout=71) 0.925 3.732 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + CLMA_90_197/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK + + CLMA_90_197/Q1 tco 0.223 3.955 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/Q + net (fanout=2) 0.259 4.214 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt [15] + CLMS_94_197/Y0 td 0.376 4.590 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_33/gateop_perm/Z + net (fanout=2) 0.075 4.665 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107154 + CLMA_94_196/Y2 td 0.379 5.044 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_36/gateop_perm/Z + net (fanout=1) 0.067 5.111 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107157 + CLMA_94_196/Y3 td 0.222 5.333 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43_3/gateop_perm/Z + net (fanout=11) 0.279 5.612 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43 + CLMA_90_185/CECO td 0.132 5.744 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[8]/opit_0_inv_L5Q_perm/CEOUT + net (fanout=4) 0.000 5.744 ntR1851 + CLMA_90_193/CECO td 0.132 5.876 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[11]/opit_0_inv_L5Q_perm/CEOUT + net (fanout=4) 0.000 5.876 ntR1850 + CLMA_90_197/CECI f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[18]/opit_0_inv_L5Q_perm/CE + + Data arrival time 5.876 Logic Levels: 5 + Logic: 1.464ns(68.284%), Route: 0.680ns(31.716%) ---------------------------------------------------------------------------------------------------- - Clock clk_50m (rising edge) 20.000 20.000 r - P20 0.000 20.000 r clk (port) - net (fanout=1) 0.074 20.074 clk - IOBS_LR_328_209/DIN td 1.285 21.359 r clk_ibuf/opit_0/O - net (fanout=1) 0.000 21.359 clk_ibuf/ntD - IOL_327_210/INCK td 0.038 21.397 r clk_ibuf/opit_1/INCK - net (fanout=1) 0.463 21.860 _N69 - PLL_158_55/CLK_OUT0 td 0.078 21.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 - net (fanout=2) 0.603 22.541 rd3_clk - USCM_84_108/CLK_USCM td 0.000 22.541 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 0.895 23.436 ntclkbufg_1 - CLMA_94_16/CLK r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/CLK - clock pessimism 0.281 23.717 - clock uncertainty -0.150 23.567 + Clock clk_200m (rising edge) 5.000 5.000 r + P20 0.000 5.000 r clk (port) + net (fanout=1) 0.074 5.074 clk + IOBS_LR_328_209/DIN td 1.285 6.359 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 6.359 clk_ibuf/ntD + IOL_327_210/INCK td 0.038 6.397 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.463 6.860 _N69 + PLL_158_55/CLK_OUT1 td 0.074 6.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 + net (fanout=2) 0.603 7.537 ddr_clk + USCM_84_113/CLK_USCM td 0.000 7.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + net (fanout=71) 0.895 8.432 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + CLMA_90_197/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[18]/opit_0_inv_L5Q_perm/CLK + clock pessimism 0.299 8.731 + clock uncertainty -0.150 8.581 - Setup time -0.276 23.291 + Setup time -0.576 8.005 - Data required time 23.291 + Data required time 8.005 ---------------------------------------------------------------------------------------------------- - Data required time 23.291 - Data arrival time 9.255 + Data required time 8.005 + Data arrival time 5.876 ---------------------------------------------------------------------------------------------------- - Slack (MET) 14.036 + Slack (MET) 2.129 ==================================================================================================== ==================================================================================================== -Startpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK -Endpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[8] -Path Group : clk_50m +Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/pll_lock_d[1]/opit_0_inv/CLK +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_b_ff/opit_0_inv/D +Path Group : clk_200m Path Type : min (fast corner) Path Class : sequential timing path -Clock Skew : 0.062 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 3.779 - Launch Clock Delay : 3.436 - Clock Pessimism Removal : -0.281 +Clock Skew : 0.015 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 3.732 + Launch Clock Delay : 3.432 + Clock Pessimism Removal : -0.285 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_50m (rising edge) 0.000 0.000 r + Clock clk_200m (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.359 clk_ibuf/ntD IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK net (fanout=1) 0.463 1.860 _N69 - PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 - net (fanout=2) 0.603 2.541 rd3_clk - USCM_84_108/CLK_USCM td 0.000 2.541 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 0.895 3.436 ntclkbufg_1 - CLMA_90_12/CLK r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK + PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 + net (fanout=2) 0.603 2.537 ddr_clk + USCM_84_113/CLK_USCM td 0.000 2.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + net (fanout=71) 0.895 3.432 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + CLMS_94_193/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/pll_lock_d[1]/opit_0_inv/CLK - CLMA_90_12/Q2 tco 0.180 3.616 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/Q0 - net (fanout=3) 0.183 3.799 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/wr_addr [6] - DRM_82_4/ADA0[8] f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[8] + CLMS_94_193/Q0 tco 0.182 3.614 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/pll_lock_d[1]/opit_0_inv/Q + net (fanout=3) 0.064 3.678 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/pll_lock_d [1] + CLMA_94_192/M0 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_b_ff/opit_0_inv/D - Data arrival time 3.799 Logic Levels: 0 - Logic: 0.180ns(49.587%), Route: 0.183ns(50.413%) + Data arrival time 3.678 Logic Levels: 0 + Logic: 0.182ns(73.984%), Route: 0.064ns(26.016%) ---------------------------------------------------------------------------------------------------- - Clock clk_50m (rising edge) 0.000 0.000 r + Clock clk_200m (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.578 clk_ibuf/ntD IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 - PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 - net (fanout=2) 0.614 2.811 rd3_clk - USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 0.968 3.779 ntclkbufg_1 - DRM_82_4/CLKA[0] r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKA - clock pessimism -0.281 3.498 - clock uncertainty 0.000 3.498 + PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 + net (fanout=2) 0.614 2.807 ddr_clk + USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + net (fanout=71) 0.925 3.732 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + CLMA_94_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_b_ff/opit_0_inv/CLK + clock pessimism -0.285 3.447 + clock uncertainty 0.000 3.447 - Hold time 0.162 3.660 + Hold time -0.011 3.436 - Data required time 3.660 + Data required time 3.436 ---------------------------------------------------------------------------------------------------- - Data required time 3.660 - Data arrival time 3.799 + Data required time 3.436 + Data arrival time 3.678 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.139 + Slack (MET) 0.242 ==================================================================================================== ==================================================================================================== -Startpoint : u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK -Endpoint : u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/D -Path Group : clk_50m +Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]/opit_0_inv_L5Q_perm/CLK +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]/opit_0_inv_L5Q_perm/L4 +Path Group : clk_200m Path Type : min (fast corner) Path Class : sequential timing path -Clock Skew : 0.016 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 3.757 - Launch Clock Delay : 3.456 - Clock Pessimism Removal : -0.285 +Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 3.732 + Launch Clock Delay : 3.432 + Clock Pessimism Removal : -0.300 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_50m (rising edge) 0.000 0.000 r + Clock clk_200m (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.359 clk_ibuf/ntD IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK net (fanout=1) 0.463 1.860 _N69 - PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 - net (fanout=2) 0.603 2.541 rd3_clk - USCM_84_108/CLK_USCM td 0.000 2.541 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 0.915 3.456 ntclkbufg_1 - CLMA_58_88/CLK r u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK + PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 + net (fanout=2) 0.603 2.537 ddr_clk + USCM_84_113/CLK_USCM td 0.000 2.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + net (fanout=71) 0.895 3.432 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + CLMS_38_185/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]/opit_0_inv_L5Q_perm/CLK - CLMA_58_88/Q3 tco 0.178 3.634 f u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/Q - net (fanout=1) 0.058 3.692 u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr1 [8] - CLMA_58_89/AD f u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/D + CLMS_38_185/Q3 tco 0.178 3.610 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]/opit_0_inv_L5Q_perm/Q + net (fanout=3) 0.061 3.671 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg [4] + CLMS_38_185/D4 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]/opit_0_inv_L5Q_perm/L4 - Data arrival time 3.692 Logic Levels: 0 - Logic: 0.178ns(75.424%), Route: 0.058ns(24.576%) + Data arrival time 3.671 Logic Levels: 0 + Logic: 0.178ns(74.477%), Route: 0.061ns(25.523%) ---------------------------------------------------------------------------------------------------- - Clock clk_50m (rising edge) 0.000 0.000 r + Clock clk_200m (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.578 clk_ibuf/ntD IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 - PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 - net (fanout=2) 0.614 2.811 rd3_clk - USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 0.946 3.757 ntclkbufg_1 - CLMA_58_89/CLK r u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/CLK - clock pessimism -0.285 3.472 - clock uncertainty 0.000 3.472 + PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 + net (fanout=2) 0.614 2.807 ddr_clk + USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + net (fanout=71) 0.925 3.732 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + CLMS_38_185/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]/opit_0_inv_L5Q_perm/CLK + clock pessimism -0.300 3.432 + clock uncertainty 0.000 3.432 - Hold time 0.040 3.512 + Hold time -0.028 3.404 - Data required time 3.512 + Data required time 3.404 ---------------------------------------------------------------------------------------------------- - Data required time 3.512 - Data arrival time 3.692 + Data required time 3.404 + Data arrival time 3.671 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.180 + Slack (MET) 0.267 ==================================================================================================== ==================================================================================================== -Startpoint : image_filiter_inst2/hybrid_filter_inst/pixel_ff[27]/opit_0/CLK -Endpoint : image_filiter_inst2/hybrid_filter_inst/pixel_ff[43]/opit_0/D -Path Group : clk_50m +Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[2]/opit_0_inv_L5Q_perm/CLK +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[3]/opit_0_inv_L5Q_perm/L4 +Path Group : clk_200m Path Type : min (fast corner) Path Class : sequential timing path Clock Skew : 0.001 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 3.736 - Launch Clock Delay : 3.436 + Capture Clock Delay : 3.732 + Launch Clock Delay : 3.432 Clock Pessimism Removal : -0.299 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_50m (rising edge) 0.000 0.000 r + Clock clk_200m (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.359 clk_ibuf/ntD IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK net (fanout=1) 0.463 1.860 _N69 - PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 - net (fanout=2) 0.603 2.541 rd3_clk - USCM_84_108/CLK_USCM td 0.000 2.541 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 0.895 3.436 ntclkbufg_1 - CLMA_98_148/CLK r image_filiter_inst2/hybrid_filter_inst/pixel_ff[27]/opit_0/CLK + PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 + net (fanout=2) 0.603 2.537 ddr_clk + USCM_84_113/CLK_USCM td 0.000 2.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + net (fanout=71) 0.895 3.432 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + CLMA_38_184/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[2]/opit_0_inv_L5Q_perm/CLK - CLMA_98_148/Q3 tco 0.178 3.614 f image_filiter_inst2/hybrid_filter_inst/pixel_ff[27]/opit_0/Q - net (fanout=1) 0.058 3.672 image_filiter_inst2/hybrid_filter_inst/pixel_ff [27] - CLMA_98_148/AD f image_filiter_inst2/hybrid_filter_inst/pixel_ff[43]/opit_0/D + CLMA_38_184/Q1 tco 0.180 3.612 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[2]/opit_0_inv_L5Q_perm/Q + net (fanout=4) 0.061 3.673 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg [2] + CLMA_38_184/C4 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[3]/opit_0_inv_L5Q_perm/L4 - Data arrival time 3.672 Logic Levels: 0 - Logic: 0.178ns(75.424%), Route: 0.058ns(24.576%) + Data arrival time 3.673 Logic Levels: 0 + Logic: 0.180ns(74.689%), Route: 0.061ns(25.311%) ---------------------------------------------------------------------------------------------------- - Clock clk_50m (rising edge) 0.000 0.000 r + Clock clk_200m (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.578 clk_ibuf/ntD IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 - PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 - net (fanout=2) 0.614 2.811 rd3_clk - USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 0.925 3.736 ntclkbufg_1 - CLMA_98_148/CLK r image_filiter_inst2/hybrid_filter_inst/pixel_ff[43]/opit_0/CLK - clock pessimism -0.299 3.437 - clock uncertainty 0.000 3.437 + PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 + net (fanout=2) 0.614 2.807 ddr_clk + USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + net (fanout=71) 0.925 3.732 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + CLMA_38_184/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[3]/opit_0_inv_L5Q_perm/CLK + clock pessimism -0.299 3.433 + clock uncertainty 0.000 3.433 - Hold time 0.040 3.477 + Hold time -0.028 3.405 - Data required time 3.477 + Data required time 3.405 ---------------------------------------------------------------------------------------------------- - Data required time 3.477 - Data arrival time 3.672 + Data required time 3.405 + Data arrival time 3.673 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.195 + Slack (MET) 0.268 ==================================================================================================== ==================================================================================================== -Startpoint : u_zoom_image/mult_fra0_0/N2/gopapm/CLK -Endpoint : u_zoom_image/mult_image_r0_0/N2/gopapm/X[0] -Path Group : clk_200m +Startpoint : u_ov5640/coms2_reg_config/clock_20k_cnt[4]/opit_0_inv/CLK +Endpoint : u_ov5640/coms2_reg_config/clock_20k_cnt[10]/opit_0_inv/D +Path Group : clk_25m Path Type : max (fast corner) Path Class : sequential timing path -Clock Skew : 0.080 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 3.542 - Launch Clock Delay : 3.732 - Clock Pessimism Removal : 0.270 +Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 3.441 + Launch Clock Delay : 3.741 + Clock Pessimism Removal : 0.281 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_200m (rising edge) 0.000 0.000 r + Clock clk_25m (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.578 clk_ibuf/ntD IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 - PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.614 2.807 zoom_clk - USCM_84_122/CLK_USCM td 0.000 2.807 r USCMROUTE_2/CLKOUT - net (fanout=759) 0.925 3.732 ntR3909 - APM_206_140/CLK r u_zoom_image/mult_fra0_0/N2/gopapm/CLK - - APM_206_140/P[31] tco 0.822 4.554 f u_zoom_image/mult_fra0_0/N2/gopapm/P[7] - net (fanout=3) 1.670 6.224 u_zoom_image/coe_mult_p0_0 [7] - APM_206_328/X[0] f u_zoom_image/mult_image_r0_0/N2/gopapm/X[0] - - Data arrival time 6.224 Logic Levels: 0 - Logic: 0.822ns(32.986%), Route: 1.670ns(67.014%) + PLL_158_55/CLK_OUT3 td 0.088 2.202 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 + net (fanout=1) 0.614 2.816 clk_25m + USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 0.925 3.741 ntclkbufg_8 + CLMS_118_17/CLK r u_ov5640/coms2_reg_config/clock_20k_cnt[4]/opit_0_inv/CLK + + CLMS_118_17/Q1 tco 0.223 3.964 f u_ov5640/coms2_reg_config/clock_20k_cnt[4]/opit_0_inv/Q + net (fanout=2) 0.262 4.226 u_ov5640/coms2_reg_config/clock_20k_cnt [4] + CLMA_122_16/Y3 td 0.358 4.584 f u_ov5640/coms2_reg_config/N8_mux4_5/gateop_perm/Z + net (fanout=1) 0.365 4.949 u_ov5640/coms2_reg_config/_N9749 + CLMA_122_16/Y2 td 0.150 5.099 f u_ov5640/coms2_reg_config/N8_mux10/gateop_perm/Z + net (fanout=13) 0.372 5.471 u_ov5640/coms2_reg_config/N8 + td 0.368 5.839 f u_ov5640/coms2_reg_config/N11_2_5/gateop_A2/Cout + net (fanout=1) 0.000 5.839 u_ov5640/coms2_reg_config/_N16307 + CLMS_122_17/COUT td 0.044 5.883 r u_ov5640/coms2_reg_config/N11_2_7/gateop_A2/Cout + net (fanout=1) 0.000 5.883 u_ov5640/coms2_reg_config/_N16309 + CLMS_122_21/Y1 td 0.366 6.249 f u_ov5640/coms2_reg_config/N11_2_9/gateop_A2/Y1 + net (fanout=1) 0.471 6.720 u_ov5640/coms2_reg_config/N1114 [10] + CLMS_122_17/M3 f u_ov5640/coms2_reg_config/clock_20k_cnt[10]/opit_0_inv/D + + Data arrival time 6.720 Logic Levels: 4 + Logic: 1.509ns(50.655%), Route: 1.470ns(49.345%) ---------------------------------------------------------------------------------------------------- - Clock clk_200m (rising edge) 5.000 5.000 r - P20 0.000 5.000 r clk (port) - net (fanout=1) 0.074 5.074 clk - IOBS_LR_328_209/DIN td 1.285 6.359 r clk_ibuf/opit_0/O - net (fanout=1) 0.000 6.359 clk_ibuf/ntD - IOL_327_210/INCK td 0.038 6.397 r clk_ibuf/opit_1/INCK - net (fanout=1) 0.463 6.860 _N69 - PLL_158_55/CLK_OUT1 td 0.074 6.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.603 7.537 zoom_clk - USCM_84_122/CLK_USCM td 0.000 7.537 r USCMROUTE_2/CLKOUT - net (fanout=759) 1.005 8.542 ntR3909 - APM_206_328/CLK r u_zoom_image/mult_image_r0_0/N2/gopapm/CLK - clock pessimism 0.270 8.812 - clock uncertainty -0.150 8.662 + Clock clk_25m (rising edge) 40.000 40.000 r + P20 0.000 40.000 r clk (port) + net (fanout=1) 0.074 40.074 clk + IOBS_LR_328_209/DIN td 1.285 41.359 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 41.359 clk_ibuf/ntD + IOL_327_210/INCK td 0.038 41.397 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.463 41.860 _N69 + PLL_158_55/CLK_OUT3 td 0.083 41.943 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 + net (fanout=1) 0.603 42.546 clk_25m + USCM_84_114/CLK_USCM td 0.000 42.546 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 0.895 43.441 ntclkbufg_8 + CLMS_122_17/CLK r u_ov5640/coms2_reg_config/clock_20k_cnt[10]/opit_0_inv/CLK + clock pessimism 0.281 43.722 + clock uncertainty -0.150 43.572 - Setup time -1.731 6.931 + Setup time -0.068 43.504 - Data required time 6.931 + Data required time 43.504 ---------------------------------------------------------------------------------------------------- - Data required time 6.931 - Data arrival time 6.224 + Data required time 43.504 + Data arrival time 6.720 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.707 + Slack (MET) 36.784 ==================================================================================================== ==================================================================================================== -Startpoint : u_zoom_image/mult_fra0_0/N2/gopapm/CLK -Endpoint : u_zoom_image/mult_image_r0_0/N2/gopapm/X[3] -Path Group : clk_200m +Startpoint : u_ov5640/coms2_reg_config/clock_20k_cnt[4]/opit_0_inv/CLK +Endpoint : u_ov5640/coms2_reg_config/clock_20k_cnt[8]/opit_0_inv/D +Path Group : clk_25m Path Type : max (fast corner) Path Class : sequential timing path -Clock Skew : 0.080 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 3.542 - Launch Clock Delay : 3.732 - Clock Pessimism Removal : 0.270 +Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 3.441 + Launch Clock Delay : 3.741 + Clock Pessimism Removal : 0.281 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_200m (rising edge) 0.000 0.000 r + Clock clk_25m (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.578 clk_ibuf/ntD IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 - PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.614 2.807 zoom_clk - USCM_84_122/CLK_USCM td 0.000 2.807 r USCMROUTE_2/CLKOUT - net (fanout=759) 0.925 3.732 ntR3909 - APM_206_140/CLK r u_zoom_image/mult_fra0_0/N2/gopapm/CLK - - APM_206_140/P[34] tco 0.822 4.554 f u_zoom_image/mult_fra0_0/N2/gopapm/P[10] - net (fanout=3) 1.618 6.172 u_zoom_image/coe_mult_p0_0 [10] - APM_206_328/X[3] f u_zoom_image/mult_image_r0_0/N2/gopapm/X[3] - - Data arrival time 6.172 Logic Levels: 0 - Logic: 0.822ns(33.689%), Route: 1.618ns(66.311%) + PLL_158_55/CLK_OUT3 td 0.088 2.202 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 + net (fanout=1) 0.614 2.816 clk_25m + USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 0.925 3.741 ntclkbufg_8 + CLMS_118_17/CLK r u_ov5640/coms2_reg_config/clock_20k_cnt[4]/opit_0_inv/CLK + + CLMS_118_17/Q1 tco 0.223 3.964 f u_ov5640/coms2_reg_config/clock_20k_cnt[4]/opit_0_inv/Q + net (fanout=2) 0.262 4.226 u_ov5640/coms2_reg_config/clock_20k_cnt [4] + CLMA_122_16/Y3 td 0.358 4.584 f u_ov5640/coms2_reg_config/N8_mux4_5/gateop_perm/Z + net (fanout=1) 0.365 4.949 u_ov5640/coms2_reg_config/_N9749 + CLMA_122_16/Y2 td 0.150 5.099 f u_ov5640/coms2_reg_config/N8_mux10/gateop_perm/Z + net (fanout=13) 0.372 5.471 u_ov5640/coms2_reg_config/N8 + td 0.368 5.839 f u_ov5640/coms2_reg_config/N11_2_5/gateop_A2/Cout + net (fanout=1) 0.000 5.839 u_ov5640/coms2_reg_config/_N16307 + CLMS_122_17/Y3 td 0.365 6.204 f u_ov5640/coms2_reg_config/N11_2_7/gateop_A2/Y1 + net (fanout=1) 0.488 6.692 u_ov5640/coms2_reg_config/N1114 [8] + CLMS_122_17/M2 f u_ov5640/coms2_reg_config/clock_20k_cnt[8]/opit_0_inv/D + + Data arrival time 6.692 Logic Levels: 3 + Logic: 1.464ns(49.610%), Route: 1.487ns(50.390%) ---------------------------------------------------------------------------------------------------- - Clock clk_200m (rising edge) 5.000 5.000 r - P20 0.000 5.000 r clk (port) - net (fanout=1) 0.074 5.074 clk - IOBS_LR_328_209/DIN td 1.285 6.359 r clk_ibuf/opit_0/O - net (fanout=1) 0.000 6.359 clk_ibuf/ntD - IOL_327_210/INCK td 0.038 6.397 r clk_ibuf/opit_1/INCK - net (fanout=1) 0.463 6.860 _N69 - PLL_158_55/CLK_OUT1 td 0.074 6.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.603 7.537 zoom_clk - USCM_84_122/CLK_USCM td 0.000 7.537 r USCMROUTE_2/CLKOUT - net (fanout=759) 1.005 8.542 ntR3909 - APM_206_328/CLK r u_zoom_image/mult_image_r0_0/N2/gopapm/CLK - clock pessimism 0.270 8.812 - clock uncertainty -0.150 8.662 + Clock clk_25m (rising edge) 40.000 40.000 r + P20 0.000 40.000 r clk (port) + net (fanout=1) 0.074 40.074 clk + IOBS_LR_328_209/DIN td 1.285 41.359 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 41.359 clk_ibuf/ntD + IOL_327_210/INCK td 0.038 41.397 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.463 41.860 _N69 + PLL_158_55/CLK_OUT3 td 0.083 41.943 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 + net (fanout=1) 0.603 42.546 clk_25m + USCM_84_114/CLK_USCM td 0.000 42.546 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 0.895 43.441 ntclkbufg_8 + CLMS_122_17/CLK r u_ov5640/coms2_reg_config/clock_20k_cnt[8]/opit_0_inv/CLK + clock pessimism 0.281 43.722 + clock uncertainty -0.150 43.572 - Setup time -1.731 6.931 + Setup time -0.068 43.504 - Data required time 6.931 + Data required time 43.504 ---------------------------------------------------------------------------------------------------- - Data required time 6.931 - Data arrival time 6.172 + Data required time 43.504 + Data arrival time 6.692 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.759 + Slack (MET) 36.812 ==================================================================================================== ==================================================================================================== -Startpoint : u_zoom_image/mult_fra0_0/N2/gopapm/CLK -Endpoint : u_zoom_image/mult_image_r0_0/N2/gopapm/X[6] -Path Group : clk_200m +Startpoint : u_ov5640/coms2_reg_config/clock_20k_cnt[4]/opit_0_inv/CLK +Endpoint : u_ov5640/coms2_reg_config/clock_20k_cnt[9]/opit_0_inv/D +Path Group : clk_25m Path Type : max (fast corner) Path Class : sequential timing path -Clock Skew : 0.080 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 3.542 - Launch Clock Delay : 3.732 - Clock Pessimism Removal : 0.270 +Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 3.441 + Launch Clock Delay : 3.741 + Clock Pessimism Removal : 0.281 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_200m (rising edge) 0.000 0.000 r + Clock clk_25m (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.578 clk_ibuf/ntD IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 - PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.614 2.807 zoom_clk - USCM_84_122/CLK_USCM td 0.000 2.807 r USCMROUTE_2/CLKOUT - net (fanout=759) 0.925 3.732 ntR3909 - APM_206_140/CLK r u_zoom_image/mult_fra0_0/N2/gopapm/CLK - - APM_206_140/P[37] tco 0.822 4.554 f u_zoom_image/mult_fra0_0/N2/gopapm/P[13] - net (fanout=3) 1.614 6.168 u_zoom_image/coe_mult_p0_0 [13] - APM_206_328/X[6] f u_zoom_image/mult_image_r0_0/N2/gopapm/X[6] - - Data arrival time 6.168 Logic Levels: 0 - Logic: 0.822ns(33.744%), Route: 1.614ns(66.256%) + PLL_158_55/CLK_OUT3 td 0.088 2.202 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 + net (fanout=1) 0.614 2.816 clk_25m + USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 0.925 3.741 ntclkbufg_8 + CLMS_118_17/CLK r u_ov5640/coms2_reg_config/clock_20k_cnt[4]/opit_0_inv/CLK + + CLMS_118_17/Q1 tco 0.223 3.964 f u_ov5640/coms2_reg_config/clock_20k_cnt[4]/opit_0_inv/Q + net (fanout=2) 0.262 4.226 u_ov5640/coms2_reg_config/clock_20k_cnt [4] + CLMA_122_16/Y3 td 0.358 4.584 f u_ov5640/coms2_reg_config/N8_mux4_5/gateop_perm/Z + net (fanout=1) 0.365 4.949 u_ov5640/coms2_reg_config/_N9749 + CLMA_122_16/Y2 td 0.150 5.099 f u_ov5640/coms2_reg_config/N8_mux10/gateop_perm/Z + net (fanout=13) 0.372 5.471 u_ov5640/coms2_reg_config/N8 + td 0.368 5.839 f u_ov5640/coms2_reg_config/N11_2_5/gateop_A2/Cout + net (fanout=1) 0.000 5.839 u_ov5640/coms2_reg_config/_N16307 + CLMS_122_17/COUT td 0.044 5.883 r u_ov5640/coms2_reg_config/N11_2_7/gateop_A2/Cout + net (fanout=1) 0.000 5.883 u_ov5640/coms2_reg_config/_N16309 + CLMS_122_21/Y0 td 0.206 6.089 f u_ov5640/coms2_reg_config/N11_2_9/gateop_A2/Y0 + net (fanout=1) 0.471 6.560 u_ov5640/coms2_reg_config/N1114 [9] + CLMS_122_17/M1 f u_ov5640/coms2_reg_config/clock_20k_cnt[9]/opit_0_inv/D + + Data arrival time 6.560 Logic Levels: 4 + Logic: 1.349ns(47.854%), Route: 1.470ns(52.146%) ---------------------------------------------------------------------------------------------------- - Clock clk_200m (rising edge) 5.000 5.000 r - P20 0.000 5.000 r clk (port) - net (fanout=1) 0.074 5.074 clk - IOBS_LR_328_209/DIN td 1.285 6.359 r clk_ibuf/opit_0/O - net (fanout=1) 0.000 6.359 clk_ibuf/ntD - IOL_327_210/INCK td 0.038 6.397 r clk_ibuf/opit_1/INCK - net (fanout=1) 0.463 6.860 _N69 - PLL_158_55/CLK_OUT1 td 0.074 6.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.603 7.537 zoom_clk - USCM_84_122/CLK_USCM td 0.000 7.537 r USCMROUTE_2/CLKOUT - net (fanout=759) 1.005 8.542 ntR3909 - APM_206_328/CLK r u_zoom_image/mult_image_r0_0/N2/gopapm/CLK - clock pessimism 0.270 8.812 - clock uncertainty -0.150 8.662 + Clock clk_25m (rising edge) 40.000 40.000 r + P20 0.000 40.000 r clk (port) + net (fanout=1) 0.074 40.074 clk + IOBS_LR_328_209/DIN td 1.285 41.359 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 41.359 clk_ibuf/ntD + IOL_327_210/INCK td 0.038 41.397 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.463 41.860 _N69 + PLL_158_55/CLK_OUT3 td 0.083 41.943 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 + net (fanout=1) 0.603 42.546 clk_25m + USCM_84_114/CLK_USCM td 0.000 42.546 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 0.895 43.441 ntclkbufg_8 + CLMS_122_17/CLK r u_ov5640/coms2_reg_config/clock_20k_cnt[9]/opit_0_inv/CLK + clock pessimism 0.281 43.722 + clock uncertainty -0.150 43.572 - Setup time -1.731 6.931 + Setup time -0.068 43.504 - Data required time 6.931 + Data required time 43.504 ---------------------------------------------------------------------------------------------------- - Data required time 6.931 - Data arrival time 6.168 + Data required time 43.504 + Data arrival time 6.560 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.763 + Slack (MET) 36.944 ==================================================================================================== ==================================================================================================== -Startpoint : u_zoom_image/mult_image_g0/N2/gopapm/CLK -Endpoint : u_zoom_image/mult_image_g1/N2/gopapm/PI[0] -Path Group : clk_200m +Startpoint : u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK +Endpoint : u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/D +Path Group : clk_25m Path Type : min (fast corner) Path Class : sequential timing path -Clock Skew : 0.142 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 3.844 - Launch Clock Delay : 3.432 - Clock Pessimism Removal : -0.270 +Clock Skew : 0.001 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 3.741 + Launch Clock Delay : 3.441 + Clock Pessimism Removal : -0.299 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_200m (rising edge) 0.000 0.000 r + Clock clk_25m (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.359 clk_ibuf/ntD IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK net (fanout=1) 0.463 1.860 _N69 - PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.603 2.537 zoom_clk - USCM_84_122/CLK_USCM td 0.000 2.537 r USCMROUTE_2/CLKOUT - net (fanout=759) 0.895 3.432 ntR3909 - APM_206_240/CLK r u_zoom_image/mult_image_g0/N2/gopapm/CLK + PLL_158_55/CLK_OUT3 td 0.083 1.943 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 + net (fanout=1) 0.603 2.546 clk_25m + USCM_84_114/CLK_USCM td 0.000 2.546 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 0.895 3.441 ntclkbufg_8 + CLMS_122_9/CLK r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK - APM_206_240/PO[0] tco 0.239 3.671 r u_zoom_image/mult_image_g0/N2/gopapm/PO[0] - net (fanout=1) 0.000 3.671 u_zoom_image/mult_image0[2] [0] - APM_206_252/PI[0] r u_zoom_image/mult_image_g1/N2/gopapm/PI[0] + CLMS_122_9/Q1 tco 0.184 3.625 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q + net (fanout=3) 0.194 3.819 u_ov5640/coms1_reg_config/clk_20k_regdiv + CLMS_122_9/M0 r u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/D - Data arrival time 3.671 Logic Levels: 0 - Logic: 0.239ns(100.000%), Route: 0.000ns(0.000%) + Data arrival time 3.819 Logic Levels: 0 + Logic: 0.184ns(48.677%), Route: 0.194ns(51.323%) ---------------------------------------------------------------------------------------------------- - Clock clk_200m (rising edge) 0.000 0.000 r + Clock clk_25m (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.578 clk_ibuf/ntD IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 - PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.614 2.807 zoom_clk - USCM_84_122/CLK_USCM td 0.000 2.807 r USCMROUTE_2/CLKOUT - net (fanout=759) 1.037 3.844 ntR3909 - APM_206_252/CLK r u_zoom_image/mult_image_g1/N2/gopapm/CLK - clock pessimism -0.270 3.574 - clock uncertainty 0.000 3.574 + PLL_158_55/CLK_OUT3 td 0.088 2.202 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 + net (fanout=1) 0.614 2.816 clk_25m + USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 0.925 3.741 ntclkbufg_8 + CLMS_122_9/CLK r u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/CLK + clock pessimism -0.299 3.442 + clock uncertainty 0.000 3.442 - Hold time -0.099 3.475 + Hold time -0.011 3.431 - Data required time 3.475 + Data required time 3.431 ---------------------------------------------------------------------------------------------------- - Data required time 3.475 - Data arrival time 3.671 + Data required time 3.431 + Data arrival time 3.819 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.196 + Slack (MET) 0.388 ==================================================================================================== ==================================================================================================== -Startpoint : u_zoom_image/mult_image_g0/N2/gopapm/CLK -Endpoint : u_zoom_image/mult_image_g1/N2/gopapm/PI[1] -Path Group : clk_200m +Startpoint : u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/CLK +Endpoint : u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite/opit_0_inv/D +Path Group : clk_25m Path Type : min (fast corner) Path Class : sequential timing path -Clock Skew : 0.142 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 3.844 - Launch Clock Delay : 3.432 - Clock Pessimism Removal : -0.270 +Clock Skew : 0.001 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 3.741 + Launch Clock Delay : 3.441 + Clock Pessimism Removal : -0.299 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_200m (rising edge) 0.000 0.000 r + Clock clk_25m (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.359 clk_ibuf/ntD IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK net (fanout=1) 0.463 1.860 _N69 - PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.603 2.537 zoom_clk - USCM_84_122/CLK_USCM td 0.000 2.537 r USCMROUTE_2/CLKOUT - net (fanout=759) 0.895 3.432 ntR3909 - APM_206_240/CLK r u_zoom_image/mult_image_g0/N2/gopapm/CLK + PLL_158_55/CLK_OUT3 td 0.083 1.943 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 + net (fanout=1) 0.603 2.546 clk_25m + USCM_84_114/CLK_USCM td 0.000 2.546 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 0.895 3.441 ntclkbufg_8 + CLMA_122_12/CLK r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/CLK - APM_206_240/PO[1] tco 0.239 3.671 r u_zoom_image/mult_image_g0/N2/gopapm/PO[1] - net (fanout=1) 0.000 3.671 u_zoom_image/mult_image0[2] [1] - APM_206_252/PI[1] r u_zoom_image/mult_image_g1/N2/gopapm/PI[1] + CLMA_122_12/Q1 tco 0.184 3.625 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q + net (fanout=3) 0.217 3.842 u_ov5640/coms2_reg_config/clk_20k_regdiv + CLMA_122_12/M0 r u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite/opit_0_inv/D - Data arrival time 3.671 Logic Levels: 0 - Logic: 0.239ns(100.000%), Route: 0.000ns(0.000%) + Data arrival time 3.842 Logic Levels: 0 + Logic: 0.184ns(45.885%), Route: 0.217ns(54.115%) ---------------------------------------------------------------------------------------------------- - Clock clk_200m (rising edge) 0.000 0.000 r + Clock clk_25m (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.578 clk_ibuf/ntD IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 - PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.614 2.807 zoom_clk - USCM_84_122/CLK_USCM td 0.000 2.807 r USCMROUTE_2/CLKOUT - net (fanout=759) 1.037 3.844 ntR3909 - APM_206_252/CLK r u_zoom_image/mult_image_g1/N2/gopapm/CLK - clock pessimism -0.270 3.574 - clock uncertainty 0.000 3.574 + PLL_158_55/CLK_OUT3 td 0.088 2.202 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 + net (fanout=1) 0.614 2.816 clk_25m + USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 0.925 3.741 ntclkbufg_8 + CLMA_122_12/CLK r u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite/opit_0_inv/CLK + clock pessimism -0.299 3.442 + clock uncertainty 0.000 3.442 - Hold time -0.099 3.475 + Hold time -0.011 3.431 - Data required time 3.475 + Data required time 3.431 ---------------------------------------------------------------------------------------------------- - Data required time 3.475 - Data arrival time 3.671 + Data required time 3.431 + Data arrival time 3.842 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.196 + Slack (MET) 0.411 ==================================================================================================== ==================================================================================================== -Startpoint : u_zoom_image/mult_image_g0/N2/gopapm/CLK -Endpoint : u_zoom_image/mult_image_g1/N2/gopapm/PI[2] -Path Group : clk_200m +Startpoint : u_ov5640/coms1_reg_config/clock_20k_cnt[1]/opit_0_inv/CLK +Endpoint : u_ov5640/coms1_reg_config/clock_20k_cnt[1]/opit_0_inv/D +Path Group : clk_25m Path Type : min (fast corner) Path Class : sequential timing path -Clock Skew : 0.142 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 3.844 - Launch Clock Delay : 3.432 - Clock Pessimism Removal : -0.270 +Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 3.741 + Launch Clock Delay : 3.441 + Clock Pessimism Removal : -0.300 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_200m (rising edge) 0.000 0.000 r + Clock clk_25m (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.359 clk_ibuf/ntD IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK net (fanout=1) 0.463 1.860 _N69 - PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.603 2.537 zoom_clk - USCM_84_122/CLK_USCM td 0.000 2.537 r USCMROUTE_2/CLKOUT - net (fanout=759) 0.895 3.432 ntR3909 - APM_206_240/CLK r u_zoom_image/mult_image_g0/N2/gopapm/CLK + PLL_158_55/CLK_OUT3 td 0.083 1.943 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 + net (fanout=1) 0.603 2.546 clk_25m + USCM_84_114/CLK_USCM td 0.000 2.546 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 0.895 3.441 ntclkbufg_8 + CLMS_118_13/CLK r u_ov5640/coms1_reg_config/clock_20k_cnt[1]/opit_0_inv/CLK - APM_206_240/PO[2] tco 0.239 3.671 r u_zoom_image/mult_image_g0/N2/gopapm/PO[2] - net (fanout=1) 0.000 3.671 u_zoom_image/mult_image0[2] [2] - APM_206_252/PI[2] r u_zoom_image/mult_image_g1/N2/gopapm/PI[2] + CLMS_118_13/Q0 tco 0.179 3.620 f u_ov5640/coms1_reg_config/clock_20k_cnt[1]/opit_0_inv/Q + net (fanout=3) 0.061 3.681 u_ov5640/coms1_reg_config/clock_20k_cnt [1] + CLMS_118_13/Y0 td 0.184 3.865 r u_ov5640/coms1_reg_config/N11_2_1/gateop_A2/Y0 + net (fanout=1) 0.065 3.930 u_ov5640/coms1_reg_config/N1114 [1] + CLMS_118_13/M0 r u_ov5640/coms1_reg_config/clock_20k_cnt[1]/opit_0_inv/D - Data arrival time 3.671 Logic Levels: 0 - Logic: 0.239ns(100.000%), Route: 0.000ns(0.000%) + Data arrival time 3.930 Logic Levels: 1 + Logic: 0.363ns(74.233%), Route: 0.126ns(25.767%) ---------------------------------------------------------------------------------------------------- - Clock clk_200m (rising edge) 0.000 0.000 r + Clock clk_25m (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.578 clk_ibuf/ntD IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 - PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.614 2.807 zoom_clk - USCM_84_122/CLK_USCM td 0.000 2.807 r USCMROUTE_2/CLKOUT - net (fanout=759) 1.037 3.844 ntR3909 - APM_206_252/CLK r u_zoom_image/mult_image_g1/N2/gopapm/CLK - clock pessimism -0.270 3.574 - clock uncertainty 0.000 3.574 + PLL_158_55/CLK_OUT3 td 0.088 2.202 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 + net (fanout=1) 0.614 2.816 clk_25m + USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 0.925 3.741 ntclkbufg_8 + CLMS_118_13/CLK r u_ov5640/coms1_reg_config/clock_20k_cnt[1]/opit_0_inv/CLK + clock pessimism -0.300 3.441 + clock uncertainty 0.000 3.441 - Hold time -0.099 3.475 + Hold time -0.011 3.430 - Data required time 3.475 + Data required time 3.430 ---------------------------------------------------------------------------------------------------- - Data required time 3.475 - Data arrival time 3.671 + Data required time 3.430 + Data arrival time 3.930 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.196 + Slack (MET) 0.500 ==================================================================================================== ==================================================================================================== -Startpoint : u_ov5640/coms1_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK -Endpoint : u_ov5640/coms1_reg_config/clock_20k_cnt[8]/opit_0_inv/D -Path Group : clk_25m +Startpoint : ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK +Endpoint : ms72xx_ctl/ms7200_ctl/addr[0]/opit_0_inv_L5Q_perm/CE +Path Group : clk_10m Path Type : max (fast corner) Path Class : sequential timing path -Clock Skew : -0.001 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 3.441 - Launch Clock Delay : 3.741 - Clock Pessimism Removal : 0.299 +Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 3.547 + Launch Clock Delay : 3.849 + Clock Pessimism Removal : 0.283 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_25m (rising edge) 0.000 0.000 r + Clock clk_10m (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.578 clk_ibuf/ntD IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 - PLL_158_55/CLK_OUT3 td 0.088 2.202 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 - net (fanout=1) 0.614 2.816 clk_25m - USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 0.925 3.741 ntclkbufg_7 - CLMA_182_17/CLK r u_ov5640/coms1_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK - - CLMA_182_17/Q0 tco 0.221 3.962 f u_ov5640/coms1_reg_config/clock_20k_cnt[0]/opit_0_inv/Q - net (fanout=4) 0.365 4.327 u_ov5640/coms1_reg_config/clock_20k_cnt [0] - CLMA_182_13/Y2 td 0.381 4.708 f u_ov5640/coms1_reg_config/N8_mux4_5/gateop_perm/Z - net (fanout=1) 0.256 4.964 u_ov5640/coms1_reg_config/_N9664 - CLMA_186_16/Y0 td 0.150 5.114 f u_ov5640/coms1_reg_config/N8_mux10/gateop_perm/Z - net (fanout=13) 0.508 5.622 u_ov5640/coms1_reg_config/N8 - CLMA_182_12/COUT td 0.391 6.013 r u_ov5640/coms1_reg_config/N11_2_3/gateop_A2/Cout - net (fanout=1) 0.000 6.013 u_ov5640/coms1_reg_config/_N16248 - td 0.044 6.057 r u_ov5640/coms1_reg_config/N11_2_5/gateop_A2/Cout - net (fanout=1) 0.000 6.057 u_ov5640/coms1_reg_config/_N16250 - CLMA_182_16/Y3 td 0.365 6.422 f u_ov5640/coms1_reg_config/N11_2_7/gateop_A2/Y1 - net (fanout=1) 0.375 6.797 u_ov5640/coms1_reg_config/N1114 [8] - CLMA_182_17/M2 f u_ov5640/coms1_reg_config/clock_20k_cnt[8]/opit_0_inv/D - - Data arrival time 6.797 Logic Levels: 4 - Logic: 1.552ns(50.785%), Route: 1.504ns(49.215%) + PLL_158_55/CLK_OUT4 td 0.084 2.198 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 + net (fanout=1) 0.614 2.812 clk_10m + USCM_84_110/CLK_USCM td 0.000 2.812 r clkbufg_4/gopclkbufg/CLKOUT + net (fanout=235) 1.037 3.849 ntclkbufg_4 + CLMS_218_329/CLK r ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK + + CLMS_218_329/Q2 tco 0.223 4.072 f ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/Q + net (fanout=3) 0.174 4.246 ms72xx_ctl/ms7200_ctl/dri_cnt [4] + CLMS_218_333/Y3 td 0.358 4.604 f ms72xx_ctl/ms7200_ctl/N8_3/gateop_perm/Z + net (fanout=1) 0.157 4.761 ms72xx_ctl/ms7200_ctl/_N96627 + CLMS_218_333/Y0 td 0.150 4.911 f ms72xx_ctl/ms7200_ctl/N1872_5/gateop_perm/Z + net (fanout=6) 0.269 5.180 ms72xx_ctl/ms7200_ctl/_N96632 + CLMS_222_329/Y0 td 0.150 5.330 f ms72xx_ctl/ms7200_ctl/N2053_1/gateop_perm/Z + net (fanout=15) 0.363 5.693 ms72xx_ctl/ms7200_ctl/N261 + CLMS_214_321/Y0 td 0.264 5.957 f ms72xx_ctl/ms7200_ctl/N40_9/gateop_perm/Z + net (fanout=4) 0.353 6.310 ms72xx_ctl/ms7200_ctl/N2093 [4] + CLMA_222_324/Y1 td 0.151 6.461 f ms72xx_ctl/ms7200_ctl/N1955/gateop_perm/Z + net (fanout=12) 0.363 6.824 ms72xx_ctl/ms7200_ctl/N1955 + CLMA_230_324/CECO td 0.132 6.956 f ms72xx_ctl/ms7200_ctl/data_in[5]/opit_0_inv_L5Q_perm/CEOUT + net (fanout=4) 0.000 6.956 ntR1800 + CLMA_230_328/CECI f ms72xx_ctl/ms7200_ctl/addr[0]/opit_0_inv_L5Q_perm/CE + + Data arrival time 6.956 Logic Levels: 6 + Logic: 1.428ns(45.961%), Route: 1.679ns(54.039%) ---------------------------------------------------------------------------------------------------- - Clock clk_25m (rising edge) 40.000 40.000 r - P20 0.000 40.000 r clk (port) - net (fanout=1) 0.074 40.074 clk - IOBS_LR_328_209/DIN td 1.285 41.359 r clk_ibuf/opit_0/O - net (fanout=1) 0.000 41.359 clk_ibuf/ntD - IOL_327_210/INCK td 0.038 41.397 r clk_ibuf/opit_1/INCK - net (fanout=1) 0.463 41.860 _N69 - PLL_158_55/CLK_OUT3 td 0.083 41.943 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 - net (fanout=1) 0.603 42.546 clk_25m - USCM_84_114/CLK_USCM td 0.000 42.546 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 0.895 43.441 ntclkbufg_7 - CLMA_182_17/CLK r u_ov5640/coms1_reg_config/clock_20k_cnt[8]/opit_0_inv/CLK - clock pessimism 0.299 43.740 - clock uncertainty -0.150 43.590 + Clock clk_10m (rising edge) 100.000 100.000 r + P20 0.000 100.000 r clk (port) + net (fanout=1) 0.074 100.074 clk + IOBS_LR_328_209/DIN td 1.285 101.359 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 101.359 clk_ibuf/ntD + IOL_327_210/INCK td 0.038 101.397 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.463 101.860 _N69 + PLL_158_55/CLK_OUT4 td 0.079 101.939 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 + net (fanout=1) 0.603 102.542 clk_10m + USCM_84_110/CLK_USCM td 0.000 102.542 r clkbufg_4/gopclkbufg/CLKOUT + net (fanout=235) 1.005 103.547 ntclkbufg_4 + CLMA_230_328/CLK r ms72xx_ctl/ms7200_ctl/addr[0]/opit_0_inv_L5Q_perm/CLK + clock pessimism 0.283 103.830 + clock uncertainty -0.150 103.680 - Setup time -0.068 43.522 + Setup time -0.576 103.104 - Data required time 43.522 + Data required time 103.104 ---------------------------------------------------------------------------------------------------- - Data required time 43.522 - Data arrival time 6.797 + Data required time 103.104 + Data arrival time 6.956 ---------------------------------------------------------------------------------------------------- - Slack (MET) 36.725 + Slack (MET) 96.148 ==================================================================================================== ==================================================================================================== -Startpoint : u_ov5640/coms1_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK -Endpoint : u_ov5640/coms1_reg_config/clock_20k_cnt[10]/opit_0_inv/D -Path Group : clk_25m +Startpoint : ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK +Endpoint : ms72xx_ctl/ms7200_ctl/addr[4]/opit_0_inv_L5Q_perm/CE +Path Group : clk_10m Path Type : max (fast corner) Path Class : sequential timing path -Clock Skew : -0.015 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 3.441 - Launch Clock Delay : 3.741 - Clock Pessimism Removal : 0.285 +Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 3.547 + Launch Clock Delay : 3.849 + Clock Pessimism Removal : 0.283 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_25m (rising edge) 0.000 0.000 r + Clock clk_10m (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.578 clk_ibuf/ntD IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 - PLL_158_55/CLK_OUT3 td 0.088 2.202 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 - net (fanout=1) 0.614 2.816 clk_25m - USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 0.925 3.741 ntclkbufg_7 - CLMA_182_17/CLK r u_ov5640/coms1_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK - - CLMA_182_17/Q0 tco 0.221 3.962 f u_ov5640/coms1_reg_config/clock_20k_cnt[0]/opit_0_inv/Q - net (fanout=4) 0.365 4.327 u_ov5640/coms1_reg_config/clock_20k_cnt [0] - CLMA_182_13/Y2 td 0.381 4.708 f u_ov5640/coms1_reg_config/N8_mux4_5/gateop_perm/Z - net (fanout=1) 0.256 4.964 u_ov5640/coms1_reg_config/_N9664 - CLMA_186_16/Y0 td 0.150 5.114 f u_ov5640/coms1_reg_config/N8_mux10/gateop_perm/Z - net (fanout=13) 0.508 5.622 u_ov5640/coms1_reg_config/N8 - CLMA_182_12/COUT td 0.391 6.013 r u_ov5640/coms1_reg_config/N11_2_3/gateop_A2/Cout - net (fanout=1) 0.000 6.013 u_ov5640/coms1_reg_config/_N16248 - td 0.044 6.057 r u_ov5640/coms1_reg_config/N11_2_5/gateop_A2/Cout - net (fanout=1) 0.000 6.057 u_ov5640/coms1_reg_config/_N16250 - CLMA_182_16/COUT td 0.044 6.101 r u_ov5640/coms1_reg_config/N11_2_7/gateop_A2/Cout - net (fanout=1) 0.000 6.101 u_ov5640/coms1_reg_config/_N16252 - CLMA_182_20/Y1 td 0.366 6.467 f u_ov5640/coms1_reg_config/N11_2_9/gateop_A2/Y1 - net (fanout=1) 0.273 6.740 u_ov5640/coms1_reg_config/N1114 [10] - CLMA_182_20/M0 f u_ov5640/coms1_reg_config/clock_20k_cnt[10]/opit_0_inv/D - - Data arrival time 6.740 Logic Levels: 5 - Logic: 1.597ns(53.251%), Route: 1.402ns(46.749%) + PLL_158_55/CLK_OUT4 td 0.084 2.198 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 + net (fanout=1) 0.614 2.812 clk_10m + USCM_84_110/CLK_USCM td 0.000 2.812 r clkbufg_4/gopclkbufg/CLKOUT + net (fanout=235) 1.037 3.849 ntclkbufg_4 + CLMS_218_329/CLK r ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK + + CLMS_218_329/Q2 tco 0.223 4.072 f ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/Q + net (fanout=3) 0.174 4.246 ms72xx_ctl/ms7200_ctl/dri_cnt [4] + CLMS_218_333/Y3 td 0.358 4.604 f ms72xx_ctl/ms7200_ctl/N8_3/gateop_perm/Z + net (fanout=1) 0.157 4.761 ms72xx_ctl/ms7200_ctl/_N96627 + CLMS_218_333/Y0 td 0.150 4.911 f ms72xx_ctl/ms7200_ctl/N1872_5/gateop_perm/Z + net (fanout=6) 0.269 5.180 ms72xx_ctl/ms7200_ctl/_N96632 + CLMS_222_329/Y0 td 0.150 5.330 f ms72xx_ctl/ms7200_ctl/N2053_1/gateop_perm/Z + net (fanout=15) 0.363 5.693 ms72xx_ctl/ms7200_ctl/N261 + CLMS_214_321/Y0 td 0.264 5.957 f ms72xx_ctl/ms7200_ctl/N40_9/gateop_perm/Z + net (fanout=4) 0.353 6.310 ms72xx_ctl/ms7200_ctl/N2093 [4] + CLMA_222_324/Y1 td 0.151 6.461 f ms72xx_ctl/ms7200_ctl/N1955/gateop_perm/Z + net (fanout=12) 0.363 6.824 ms72xx_ctl/ms7200_ctl/N1955 + CLMA_230_324/CECO td 0.132 6.956 f ms72xx_ctl/ms7200_ctl/data_in[5]/opit_0_inv_L5Q_perm/CEOUT + net (fanout=4) 0.000 6.956 ntR1800 + CLMA_230_328/CECI f ms72xx_ctl/ms7200_ctl/addr[4]/opit_0_inv_L5Q_perm/CE + + Data arrival time 6.956 Logic Levels: 6 + Logic: 1.428ns(45.961%), Route: 1.679ns(54.039%) ---------------------------------------------------------------------------------------------------- - Clock clk_25m (rising edge) 40.000 40.000 r - P20 0.000 40.000 r clk (port) - net (fanout=1) 0.074 40.074 clk - IOBS_LR_328_209/DIN td 1.285 41.359 r clk_ibuf/opit_0/O - net (fanout=1) 0.000 41.359 clk_ibuf/ntD - IOL_327_210/INCK td 0.038 41.397 r clk_ibuf/opit_1/INCK - net (fanout=1) 0.463 41.860 _N69 - PLL_158_55/CLK_OUT3 td 0.083 41.943 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 - net (fanout=1) 0.603 42.546 clk_25m - USCM_84_114/CLK_USCM td 0.000 42.546 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 0.895 43.441 ntclkbufg_7 - CLMA_182_20/CLK r u_ov5640/coms1_reg_config/clock_20k_cnt[10]/opit_0_inv/CLK - clock pessimism 0.285 43.726 - clock uncertainty -0.150 43.576 + Clock clk_10m (rising edge) 100.000 100.000 r + P20 0.000 100.000 r clk (port) + net (fanout=1) 0.074 100.074 clk + IOBS_LR_328_209/DIN td 1.285 101.359 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 101.359 clk_ibuf/ntD + IOL_327_210/INCK td 0.038 101.397 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.463 101.860 _N69 + PLL_158_55/CLK_OUT4 td 0.079 101.939 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 + net (fanout=1) 0.603 102.542 clk_10m + USCM_84_110/CLK_USCM td 0.000 102.542 r clkbufg_4/gopclkbufg/CLKOUT + net (fanout=235) 1.005 103.547 ntclkbufg_4 + CLMA_230_328/CLK r ms72xx_ctl/ms7200_ctl/addr[4]/opit_0_inv_L5Q_perm/CLK + clock pessimism 0.283 103.830 + clock uncertainty -0.150 103.680 - Setup time -0.068 43.508 + Setup time -0.576 103.104 - Data required time 43.508 + Data required time 103.104 ---------------------------------------------------------------------------------------------------- - Data required time 43.508 - Data arrival time 6.740 + Data required time 103.104 + Data arrival time 6.956 ---------------------------------------------------------------------------------------------------- - Slack (MET) 36.768 + Slack (MET) 96.148 ==================================================================================================== ==================================================================================================== -Startpoint : u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK -Endpoint : u_ov5640/coms2_reg_config/clock_20k_cnt[6]/opit_0_inv/D -Path Group : clk_25m +Startpoint : ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK +Endpoint : ms72xx_ctl/ms7200_ctl/addr[5]/opit_0_inv_L5Q_perm/CE +Path Group : clk_10m Path Type : max (fast corner) Path Class : sequential timing path -Clock Skew : -0.015 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 3.441 - Launch Clock Delay : 3.741 - Clock Pessimism Removal : 0.285 +Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 3.547 + Launch Clock Delay : 3.849 + Clock Pessimism Removal : 0.283 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_25m (rising edge) 0.000 0.000 r + Clock clk_10m (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.578 clk_ibuf/ntD IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 - PLL_158_55/CLK_OUT3 td 0.088 2.202 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 - net (fanout=1) 0.614 2.816 clk_25m - USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 0.925 3.741 ntclkbufg_7 - CLMA_182_21/CLK r u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK - - CLMA_182_21/Q2 tco 0.223 3.964 f u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/Q - net (fanout=4) 0.352 4.316 u_ov5640/coms2_reg_config/clock_20k_cnt [0] - CLMA_186_16/Y1 td 0.360 4.676 f u_ov5640/coms2_reg_config/N8_mux4_5/gateop_perm/Z - net (fanout=1) 0.251 4.927 u_ov5640/coms2_reg_config/_N9736 - CLMA_186_20/Y1 td 0.244 5.171 f u_ov5640/coms2_reg_config/N8_mux10/gateop_perm/Z - net (fanout=13) 0.398 5.569 u_ov5640/coms2_reg_config/N8 - td 0.368 5.937 f u_ov5640/coms2_reg_config/N11_2_1/gateop_A2/Cout - net (fanout=1) 0.000 5.937 u_ov5640/coms2_reg_config/_N16399 - CLMA_182_21/COUT td 0.044 5.981 r u_ov5640/coms2_reg_config/N11_2_3/gateop_A2/Cout - net (fanout=1) 0.000 5.981 u_ov5640/coms2_reg_config/_N16401 - CLMA_182_25/Y1 td 0.366 6.347 f u_ov5640/coms2_reg_config/N11_2_5/gateop_A2/Y1 - net (fanout=1) 0.393 6.740 u_ov5640/coms2_reg_config/N1114 [6] - CLMA_182_20/M1 f u_ov5640/coms2_reg_config/clock_20k_cnt[6]/opit_0_inv/D - - Data arrival time 6.740 Logic Levels: 4 - Logic: 1.605ns(53.518%), Route: 1.394ns(46.482%) + PLL_158_55/CLK_OUT4 td 0.084 2.198 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 + net (fanout=1) 0.614 2.812 clk_10m + USCM_84_110/CLK_USCM td 0.000 2.812 r clkbufg_4/gopclkbufg/CLKOUT + net (fanout=235) 1.037 3.849 ntclkbufg_4 + CLMS_218_329/CLK r ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK + + CLMS_218_329/Q2 tco 0.223 4.072 f ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/Q + net (fanout=3) 0.174 4.246 ms72xx_ctl/ms7200_ctl/dri_cnt [4] + CLMS_218_333/Y3 td 0.358 4.604 f ms72xx_ctl/ms7200_ctl/N8_3/gateop_perm/Z + net (fanout=1) 0.157 4.761 ms72xx_ctl/ms7200_ctl/_N96627 + CLMS_218_333/Y0 td 0.150 4.911 f ms72xx_ctl/ms7200_ctl/N1872_5/gateop_perm/Z + net (fanout=6) 0.269 5.180 ms72xx_ctl/ms7200_ctl/_N96632 + CLMS_222_329/Y0 td 0.150 5.330 f ms72xx_ctl/ms7200_ctl/N2053_1/gateop_perm/Z + net (fanout=15) 0.363 5.693 ms72xx_ctl/ms7200_ctl/N261 + CLMS_214_321/Y0 td 0.264 5.957 f ms72xx_ctl/ms7200_ctl/N40_9/gateop_perm/Z + net (fanout=4) 0.353 6.310 ms72xx_ctl/ms7200_ctl/N2093 [4] + CLMA_222_324/Y1 td 0.151 6.461 f ms72xx_ctl/ms7200_ctl/N1955/gateop_perm/Z + net (fanout=12) 0.363 6.824 ms72xx_ctl/ms7200_ctl/N1955 + CLMA_230_324/CECO td 0.132 6.956 f ms72xx_ctl/ms7200_ctl/data_in[5]/opit_0_inv_L5Q_perm/CEOUT + net (fanout=4) 0.000 6.956 ntR1800 + CLMA_230_328/CECI f ms72xx_ctl/ms7200_ctl/addr[5]/opit_0_inv_L5Q_perm/CE + + Data arrival time 6.956 Logic Levels: 6 + Logic: 1.428ns(45.961%), Route: 1.679ns(54.039%) ---------------------------------------------------------------------------------------------------- - Clock clk_25m (rising edge) 40.000 40.000 r - P20 0.000 40.000 r clk (port) - net (fanout=1) 0.074 40.074 clk - IOBS_LR_328_209/DIN td 1.285 41.359 r clk_ibuf/opit_0/O - net (fanout=1) 0.000 41.359 clk_ibuf/ntD - IOL_327_210/INCK td 0.038 41.397 r clk_ibuf/opit_1/INCK - net (fanout=1) 0.463 41.860 _N69 - PLL_158_55/CLK_OUT3 td 0.083 41.943 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 - net (fanout=1) 0.603 42.546 clk_25m - USCM_84_114/CLK_USCM td 0.000 42.546 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 0.895 43.441 ntclkbufg_7 - CLMA_182_20/CLK r u_ov5640/coms2_reg_config/clock_20k_cnt[6]/opit_0_inv/CLK - clock pessimism 0.285 43.726 - clock uncertainty -0.150 43.576 + Clock clk_10m (rising edge) 100.000 100.000 r + P20 0.000 100.000 r clk (port) + net (fanout=1) 0.074 100.074 clk + IOBS_LR_328_209/DIN td 1.285 101.359 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 101.359 clk_ibuf/ntD + IOL_327_210/INCK td 0.038 101.397 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.463 101.860 _N69 + PLL_158_55/CLK_OUT4 td 0.079 101.939 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 + net (fanout=1) 0.603 102.542 clk_10m + USCM_84_110/CLK_USCM td 0.000 102.542 r clkbufg_4/gopclkbufg/CLKOUT + net (fanout=235) 1.005 103.547 ntclkbufg_4 + CLMA_230_328/CLK r ms72xx_ctl/ms7200_ctl/addr[5]/opit_0_inv_L5Q_perm/CLK + clock pessimism 0.283 103.830 + clock uncertainty -0.150 103.680 - Setup time -0.068 43.508 + Setup time -0.576 103.104 - Data required time 43.508 + Data required time 103.104 ---------------------------------------------------------------------------------------------------- - Data required time 43.508 - Data arrival time 6.740 + Data required time 103.104 + Data arrival time 6.956 ---------------------------------------------------------------------------------------------------- - Slack (MET) 36.768 + Slack (MET) 96.148 ==================================================================================================== ==================================================================================================== -Startpoint : u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK -Endpoint : u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/D -Path Group : clk_25m +Startpoint : ms72xx_ctl/iic_dri_tx/receiv_data[5]/opit_0_inv/CLK +Endpoint : ms72xx_ctl/iic_dri_tx/data_out[5]/opit_0/D +Path Group : clk_10m Path Type : min (fast corner) Path Class : sequential timing path -Clock Skew : 0.001 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 3.741 - Launch Clock Delay : 3.441 - Clock Pessimism Removal : -0.299 +Clock Skew : 0.015 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 3.849 + Launch Clock Delay : 3.547 + Clock Pessimism Removal : -0.287 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_25m (rising edge) 0.000 0.000 r + Clock clk_10m (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.359 clk_ibuf/ntD IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK net (fanout=1) 0.463 1.860 _N69 - PLL_158_55/CLK_OUT3 td 0.083 1.943 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 - net (fanout=1) 0.603 2.546 clk_25m - USCM_84_114/CLK_USCM td 0.000 2.546 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 0.895 3.441 ntclkbufg_7 - CLMA_182_12/CLK r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK + PLL_158_55/CLK_OUT4 td 0.079 1.939 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 + net (fanout=1) 0.603 2.542 clk_10m + USCM_84_110/CLK_USCM td 0.000 2.542 r clkbufg_4/gopclkbufg/CLKOUT + net (fanout=235) 1.005 3.547 ntclkbufg_4 + CLMA_194_305/CLK r ms72xx_ctl/iic_dri_tx/receiv_data[5]/opit_0_inv/CLK - CLMA_182_12/Q1 tco 0.184 3.625 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q - net (fanout=3) 0.212 3.837 u_ov5640/coms1_reg_config/clk_20k_regdiv - CLMA_182_12/M0 r u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/D + CLMA_194_305/Y2 tco 0.228 3.775 f ms72xx_ctl/iic_dri_tx/receiv_data[5]/opit_0_inv/Q + net (fanout=2) 0.059 3.834 ms72xx_ctl/iic_dri_tx/receiv_data [5] + CLMA_194_304/CD f ms72xx_ctl/iic_dri_tx/data_out[5]/opit_0/D - Data arrival time 3.837 Logic Levels: 0 - Logic: 0.184ns(46.465%), Route: 0.212ns(53.535%) + Data arrival time 3.834 Logic Levels: 0 + Logic: 0.228ns(79.443%), Route: 0.059ns(20.557%) ---------------------------------------------------------------------------------------------------- - Clock clk_25m (rising edge) 0.000 0.000 r + Clock clk_10m (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.578 clk_ibuf/ntD IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 - PLL_158_55/CLK_OUT3 td 0.088 2.202 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 - net (fanout=1) 0.614 2.816 clk_25m - USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 0.925 3.741 ntclkbufg_7 - CLMA_182_12/CLK r u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/CLK - clock pessimism -0.299 3.442 - clock uncertainty 0.000 3.442 + PLL_158_55/CLK_OUT4 td 0.084 2.198 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 + net (fanout=1) 0.614 2.812 clk_10m + USCM_84_110/CLK_USCM td 0.000 2.812 r clkbufg_4/gopclkbufg/CLKOUT + net (fanout=235) 1.037 3.849 ntclkbufg_4 + CLMA_194_304/CLK r ms72xx_ctl/iic_dri_tx/data_out[5]/opit_0/CLK + clock pessimism -0.287 3.562 + clock uncertainty 0.000 3.562 - Hold time -0.011 3.431 + Hold time 0.040 3.602 - Data required time 3.431 + Data required time 3.602 ---------------------------------------------------------------------------------------------------- - Data required time 3.431 - Data arrival time 3.837 + Data required time 3.602 + Data arrival time 3.834 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.406 + Slack (MET) 0.232 ==================================================================================================== ==================================================================================================== -Startpoint : u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/CLK -Endpoint : u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite/opit_0_inv/D -Path Group : clk_25m +Startpoint : ms72xx_ctl/ms7200_ctl/cmd_index[5]/opit_0_inv_A2Q21/CLK +Endpoint : ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/ADA0[10] +Path Group : clk_10m Path Type : min (fast corner) Path Class : sequential timing path -Clock Skew : 0.001 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 3.741 - Launch Clock Delay : 3.441 - Clock Pessimism Removal : -0.299 +Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 3.849 + Launch Clock Delay : 3.547 + Clock Pessimism Removal : -0.283 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_25m (rising edge) 0.000 0.000 r + Clock clk_10m (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.359 clk_ibuf/ntD IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK net (fanout=1) 0.463 1.860 _N69 - PLL_158_55/CLK_OUT3 td 0.083 1.943 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 - net (fanout=1) 0.603 2.546 clk_25m - USCM_84_114/CLK_USCM td 0.000 2.546 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 0.895 3.441 ntclkbufg_7 - CLMA_182_25/CLK r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/CLK + PLL_158_55/CLK_OUT4 td 0.079 1.939 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 + net (fanout=1) 0.603 2.542 clk_10m + USCM_84_110/CLK_USCM td 0.000 2.542 r clkbufg_4/gopclkbufg/CLKOUT + net (fanout=235) 1.005 3.547 ntclkbufg_4 + CLMA_230_325/CLK r ms72xx_ctl/ms7200_ctl/cmd_index[5]/opit_0_inv_A2Q21/CLK - CLMA_182_25/Q1 tco 0.184 3.625 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q - net (fanout=3) 0.288 3.913 u_ov5640/coms2_reg_config/clk_20k_regdiv - CLMA_182_25/M0 r u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite/opit_0_inv/D + CLMA_230_325/Q1 tco 0.184 3.731 r ms72xx_ctl/ms7200_ctl/cmd_index[5]/opit_0_inv_A2Q21/Q1 + net (fanout=3) 0.197 3.928 ms72xx_ctl/ms7200_ctl/cmd_index [5] + DRM_234_316/ADA0[10] r ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/ADA0[10] - Data arrival time 3.913 Logic Levels: 0 - Logic: 0.184ns(38.983%), Route: 0.288ns(61.017%) + Data arrival time 3.928 Logic Levels: 0 + Logic: 0.184ns(48.294%), Route: 0.197ns(51.706%) ---------------------------------------------------------------------------------------------------- - Clock clk_25m (rising edge) 0.000 0.000 r + Clock clk_10m (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.578 clk_ibuf/ntD IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 - PLL_158_55/CLK_OUT3 td 0.088 2.202 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 - net (fanout=1) 0.614 2.816 clk_25m - USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 0.925 3.741 ntclkbufg_7 - CLMA_182_25/CLK r u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite/opit_0_inv/CLK - clock pessimism -0.299 3.442 - clock uncertainty 0.000 3.442 + PLL_158_55/CLK_OUT4 td 0.084 2.198 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 + net (fanout=1) 0.614 2.812 clk_10m + USCM_84_110/CLK_USCM td 0.000 2.812 r clkbufg_4/gopclkbufg/CLKOUT + net (fanout=235) 1.037 3.849 ntclkbufg_4 + DRM_234_316/CLKA[0] r ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKA[0] + clock pessimism -0.283 3.566 + clock uncertainty 0.000 3.566 - Hold time -0.011 3.431 + Hold time 0.127 3.693 - Data required time 3.431 + Data required time 3.693 ---------------------------------------------------------------------------------------------------- - Data required time 3.431 - Data arrival time 3.913 + Data required time 3.693 + Data arrival time 3.928 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.482 + Slack (MET) 0.235 ==================================================================================================== ==================================================================================================== -Startpoint : u_ov5640/coms1_reg_config/clock_20k_cnt[5]/opit_0_inv/CLK -Endpoint : u_ov5640/coms1_reg_config/clock_20k_cnt[5]/opit_0_inv/D -Path Group : clk_25m +Startpoint : ms72xx_ctl/ms7200_ctl/cmd_index[7]/opit_0_inv_A2Q21/CLK +Endpoint : ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/ADA0[12] +Path Group : clk_10m Path Type : min (fast corner) Path Class : sequential timing path -Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 3.741 - Launch Clock Delay : 3.441 - Clock Pessimism Removal : -0.300 +Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 3.849 + Launch Clock Delay : 3.547 + Clock Pessimism Removal : -0.283 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_25m (rising edge) 0.000 0.000 r + Clock clk_10m (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.359 clk_ibuf/ntD IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK net (fanout=1) 0.463 1.860 _N69 - PLL_158_55/CLK_OUT3 td 0.083 1.943 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 - net (fanout=1) 0.603 2.546 clk_25m - USCM_84_114/CLK_USCM td 0.000 2.546 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 0.895 3.441 ntclkbufg_7 - CLMA_182_17/CLK r u_ov5640/coms1_reg_config/clock_20k_cnt[5]/opit_0_inv/CLK + PLL_158_55/CLK_OUT4 td 0.079 1.939 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 + net (fanout=1) 0.603 2.542 clk_10m + USCM_84_110/CLK_USCM td 0.000 2.542 r clkbufg_4/gopclkbufg/CLKOUT + net (fanout=235) 1.005 3.547 ntclkbufg_4 + CLMA_230_325/CLK r ms72xx_ctl/ms7200_ctl/cmd_index[7]/opit_0_inv_A2Q21/CLK - CLMA_182_17/Y0 tco 0.228 3.669 f u_ov5640/coms1_reg_config/clock_20k_cnt[5]/opit_0_inv/Q - net (fanout=2) 0.060 3.729 u_ov5640/coms1_reg_config/clock_20k_cnt [5] - CLMA_182_16/Y0 td 0.184 3.913 r u_ov5640/coms1_reg_config/N11_2_5/gateop_A2/Y0 - net (fanout=1) 0.131 4.044 u_ov5640/coms1_reg_config/N1114 [5] - CLMA_182_17/AD r u_ov5640/coms1_reg_config/clock_20k_cnt[5]/opit_0_inv/D + CLMA_230_325/Q3 tco 0.182 3.729 r ms72xx_ctl/ms7200_ctl/cmd_index[7]/opit_0_inv_A2Q21/Q1 + net (fanout=3) 0.199 3.928 ms72xx_ctl/ms7200_ctl/cmd_index [7] + DRM_234_316/ADA0[12] r ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/ADA0[12] - Data arrival time 4.044 Logic Levels: 1 - Logic: 0.412ns(68.325%), Route: 0.191ns(31.675%) + Data arrival time 3.928 Logic Levels: 0 + Logic: 0.182ns(47.769%), Route: 0.199ns(52.231%) ---------------------------------------------------------------------------------------------------- - Clock clk_25m (rising edge) 0.000 0.000 r + Clock clk_10m (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.578 clk_ibuf/ntD IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 - PLL_158_55/CLK_OUT3 td 0.088 2.202 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 - net (fanout=1) 0.614 2.816 clk_25m - USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 0.925 3.741 ntclkbufg_7 - CLMA_182_17/CLK r u_ov5640/coms1_reg_config/clock_20k_cnt[5]/opit_0_inv/CLK - clock pessimism -0.300 3.441 - clock uncertainty 0.000 3.441 + PLL_158_55/CLK_OUT4 td 0.084 2.198 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 + net (fanout=1) 0.614 2.812 clk_10m + USCM_84_110/CLK_USCM td 0.000 2.812 r clkbufg_4/gopclkbufg/CLKOUT + net (fanout=235) 1.037 3.849 ntclkbufg_4 + DRM_234_316/CLKA[0] r ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKA[0] + clock pessimism -0.283 3.566 + clock uncertainty 0.000 3.566 - Hold time 0.034 3.475 + Hold time 0.127 3.693 - Data required time 3.475 + Data required time 3.693 ---------------------------------------------------------------------------------------------------- - Data required time 3.475 - Data arrival time 4.044 + Data required time 3.693 + Data arrival time 3.928 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.569 + Slack (MET) 0.235 ==================================================================================================== ==================================================================================================== -Startpoint : ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK -Endpoint : ms72xx_ctl/ms7200_ctl/addr[0]/opit_0_inv_L5Q_perm/CE -Path Group : clk_10m +Startpoint : u_zoom_image/mult_fra1_0/N2/gopapm/CLK +Endpoint : u_zoom_image/mult_image_g1_0/N2/gopapm/X[3] +Path Group : clk_1080p60Hz Path Type : max (fast corner) Path Class : sequential timing path -Clock Skew : -0.015 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 3.437 - Launch Clock Delay : 3.737 - Clock Pessimism Removal : 0.285 +Clock Skew : -0.142 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 5.520 + Launch Clock Delay : 5.994 + Clock Pessimism Removal : 0.332 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_10m (rising edge) 0.000 0.000 r + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.578 clk_ibuf/ntD IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 - PLL_158_55/CLK_OUT4 td 0.084 2.198 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 - net (fanout=1) 0.614 2.812 clk_10m - USCM_84_110/CLK_USCM td 0.000 2.812 r clkbufg_3/gopclkbufg/CLKOUT - net (fanout=235) 0.925 3.737 ntclkbufg_3 - CLMS_242_113/CLK r ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK - - CLMS_242_113/Q3 tco 0.220 3.957 f ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/Q - net (fanout=3) 0.274 4.231 ms72xx_ctl/ms7200_ctl/dri_cnt [4] - CLMS_246_113/Y2 td 0.381 4.612 f ms72xx_ctl/ms7200_ctl/N8_3/gateop_perm/Z - net (fanout=1) 0.069 4.681 ms72xx_ctl/ms7200_ctl/_N95853 - CLMS_246_113/Y0 td 0.150 4.831 f ms72xx_ctl/ms7200_ctl/N1872_5/gateop_perm/Z - net (fanout=6) 0.271 5.102 ms72xx_ctl/ms7200_ctl/_N95857 - CLMS_242_117/Y1 td 0.244 5.346 f ms72xx_ctl/ms7200_ctl/N2053_1/gateop_perm/Z - net (fanout=15) 0.506 5.852 ms72xx_ctl/ms7200_ctl/N261 - CLMA_226_104/Y1 td 0.151 6.003 f ms72xx_ctl/ms7200_ctl/N40_9/gateop_perm/Z - net (fanout=4) 0.309 6.312 ms72xx_ctl/ms7200_ctl/N2093 [4] - CLMA_230_121/Y3 td 0.360 6.672 r ms72xx_ctl/ms7200_ctl/N1955/gateop_perm/Z - net (fanout=12) 0.302 6.974 ms72xx_ctl/ms7200_ctl/N1955 - CLMA_242_116/CECO td 0.141 7.115 r ms72xx_ctl/ms7200_ctl/data_in[6]/opit_0_inv_L5Q_perm/CEOUT - net (fanout=4) 0.000 7.115 ntR1773 - CLMA_242_120/CECI r ms72xx_ctl/ms7200_ctl/addr[0]/opit_0_inv_L5Q_perm/CE - - Data arrival time 7.115 Logic Levels: 6 - Logic: 1.647ns(48.757%), Route: 1.731ns(51.243%) + PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.614 2.811 rd3_clk + USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.131 3.942 ntR3950 + PLL_158_303/CLK_OUT0 td 0.083 4.025 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 0.932 4.957 zoom_clk + USCM_84_118/CLK_USCM td 0.000 4.957 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 1.037 5.994 ntclkbufg_3 + APM_206_264/CLK r u_zoom_image/mult_fra1_0/N2/gopapm/CLK + + APM_206_264/P[34] tco 0.822 6.816 f u_zoom_image/mult_fra1_0/N2/gopapm/P[10] + net (fanout=3) 1.403 8.219 u_zoom_image/coe_mult_p1_0 [10] + APM_206_140/X[3] f u_zoom_image/mult_image_g1_0/N2/gopapm/X[3] + + Data arrival time 8.219 Logic Levels: 0 + Logic: 0.822ns(36.944%), Route: 1.403ns(63.056%) ---------------------------------------------------------------------------------------------------- - Clock clk_10m (rising edge) 100.000 100.000 r - P20 0.000 100.000 r clk (port) - net (fanout=1) 0.074 100.074 clk - IOBS_LR_328_209/DIN td 1.285 101.359 r clk_ibuf/opit_0/O - net (fanout=1) 0.000 101.359 clk_ibuf/ntD - IOL_327_210/INCK td 0.038 101.397 r clk_ibuf/opit_1/INCK - net (fanout=1) 0.463 101.860 _N69 - PLL_158_55/CLK_OUT4 td 0.079 101.939 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 - net (fanout=1) 0.603 102.542 clk_10m - USCM_84_110/CLK_USCM td 0.000 102.542 r clkbufg_3/gopclkbufg/CLKOUT - net (fanout=235) 0.895 103.437 ntclkbufg_3 - CLMA_242_120/CLK r ms72xx_ctl/ms7200_ctl/addr[0]/opit_0_inv_L5Q_perm/CLK - clock pessimism 0.285 103.722 - clock uncertainty -0.150 103.572 + Clock clk_1080p60Hz (rising edge) 6.736 6.736 r + P20 0.000 6.736 r clk (port) + net (fanout=1) 0.074 6.810 clk + IOBS_LR_328_209/DIN td 1.285 8.095 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 8.095 clk_ibuf/ntD + IOL_327_210/INCK td 0.038 8.133 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.463 8.596 _N69 + PLL_158_55/CLK_OUT0 td 0.078 8.674 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.603 9.277 rd3_clk + USCM_84_154/CLK_USCM td 0.000 9.277 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.091 10.368 ntR3950 + PLL_158_303/CLK_OUT0 td 0.078 10.446 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 0.915 11.361 zoom_clk + USCM_84_118/CLK_USCM td 0.000 11.361 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 0.895 12.256 ntclkbufg_3 + APM_206_140/CLK r u_zoom_image/mult_image_g1_0/N2/gopapm/CLK + clock pessimism 0.332 12.588 + clock uncertainty -0.150 12.438 - Setup time -0.563 103.009 + Setup time -1.731 10.707 - Data required time 103.009 + Data required time 10.707 ---------------------------------------------------------------------------------------------------- - Data required time 103.009 - Data arrival time 7.115 + Data required time 10.707 + Data arrival time 8.219 ---------------------------------------------------------------------------------------------------- - Slack (MET) 95.894 + Slack (MET) 2.488 ==================================================================================================== ==================================================================================================== -Startpoint : ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK -Endpoint : ms72xx_ctl/ms7200_ctl/data_in[0]/opit_0_inv_L5Q_perm/CE -Path Group : clk_10m +Startpoint : u_zoom_image/mult_fra1_0/N2/gopapm/CLK +Endpoint : u_zoom_image/mult_image_g1_0/N2/gopapm/X[0] +Path Group : clk_1080p60Hz Path Type : max (fast corner) Path Class : sequential timing path -Clock Skew : -0.015 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 3.437 - Launch Clock Delay : 3.737 - Clock Pessimism Removal : 0.285 +Clock Skew : -0.142 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 5.520 + Launch Clock Delay : 5.994 + Clock Pessimism Removal : 0.332 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_10m (rising edge) 0.000 0.000 r + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.578 clk_ibuf/ntD IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 - PLL_158_55/CLK_OUT4 td 0.084 2.198 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 - net (fanout=1) 0.614 2.812 clk_10m - USCM_84_110/CLK_USCM td 0.000 2.812 r clkbufg_3/gopclkbufg/CLKOUT - net (fanout=235) 0.925 3.737 ntclkbufg_3 - CLMS_242_113/CLK r ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK - - CLMS_242_113/Q3 tco 0.220 3.957 f ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/Q - net (fanout=3) 0.274 4.231 ms72xx_ctl/ms7200_ctl/dri_cnt [4] - CLMS_246_113/Y2 td 0.381 4.612 f ms72xx_ctl/ms7200_ctl/N8_3/gateop_perm/Z - net (fanout=1) 0.069 4.681 ms72xx_ctl/ms7200_ctl/_N95853 - CLMS_246_113/Y0 td 0.150 4.831 f ms72xx_ctl/ms7200_ctl/N1872_5/gateop_perm/Z - net (fanout=6) 0.271 5.102 ms72xx_ctl/ms7200_ctl/_N95857 - CLMS_242_117/Y1 td 0.244 5.346 f ms72xx_ctl/ms7200_ctl/N2053_1/gateop_perm/Z - net (fanout=15) 0.506 5.852 ms72xx_ctl/ms7200_ctl/N261 - CLMA_226_104/Y1 td 0.151 6.003 f ms72xx_ctl/ms7200_ctl/N40_9/gateop_perm/Z - net (fanout=4) 0.309 6.312 ms72xx_ctl/ms7200_ctl/N2093 [4] - CLMA_230_121/Y3 td 0.360 6.672 r ms72xx_ctl/ms7200_ctl/N1955/gateop_perm/Z - net (fanout=12) 0.302 6.974 ms72xx_ctl/ms7200_ctl/N1955 - CLMA_242_116/CECO td 0.141 7.115 r ms72xx_ctl/ms7200_ctl/data_in[6]/opit_0_inv_L5Q_perm/CEOUT - net (fanout=4) 0.000 7.115 ntR1773 - CLMA_242_120/CECI r ms72xx_ctl/ms7200_ctl/data_in[0]/opit_0_inv_L5Q_perm/CE - - Data arrival time 7.115 Logic Levels: 6 - Logic: 1.647ns(48.757%), Route: 1.731ns(51.243%) + PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.614 2.811 rd3_clk + USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.131 3.942 ntR3950 + PLL_158_303/CLK_OUT0 td 0.083 4.025 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 0.932 4.957 zoom_clk + USCM_84_118/CLK_USCM td 0.000 4.957 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 1.037 5.994 ntclkbufg_3 + APM_206_264/CLK r u_zoom_image/mult_fra1_0/N2/gopapm/CLK + + APM_206_264/P[31] tco 0.822 6.816 f u_zoom_image/mult_fra1_0/N2/gopapm/P[7] + net (fanout=3) 1.398 8.214 u_zoom_image/coe_mult_p1_0 [7] + APM_206_140/X[0] f u_zoom_image/mult_image_g1_0/N2/gopapm/X[0] + + Data arrival time 8.214 Logic Levels: 0 + Logic: 0.822ns(37.027%), Route: 1.398ns(62.973%) ---------------------------------------------------------------------------------------------------- - Clock clk_10m (rising edge) 100.000 100.000 r - P20 0.000 100.000 r clk (port) - net (fanout=1) 0.074 100.074 clk - IOBS_LR_328_209/DIN td 1.285 101.359 r clk_ibuf/opit_0/O - net (fanout=1) 0.000 101.359 clk_ibuf/ntD - IOL_327_210/INCK td 0.038 101.397 r clk_ibuf/opit_1/INCK - net (fanout=1) 0.463 101.860 _N69 - PLL_158_55/CLK_OUT4 td 0.079 101.939 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 - net (fanout=1) 0.603 102.542 clk_10m - USCM_84_110/CLK_USCM td 0.000 102.542 r clkbufg_3/gopclkbufg/CLKOUT - net (fanout=235) 0.895 103.437 ntclkbufg_3 - CLMA_242_120/CLK r ms72xx_ctl/ms7200_ctl/data_in[0]/opit_0_inv_L5Q_perm/CLK - clock pessimism 0.285 103.722 - clock uncertainty -0.150 103.572 + Clock clk_1080p60Hz (rising edge) 6.736 6.736 r + P20 0.000 6.736 r clk (port) + net (fanout=1) 0.074 6.810 clk + IOBS_LR_328_209/DIN td 1.285 8.095 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 8.095 clk_ibuf/ntD + IOL_327_210/INCK td 0.038 8.133 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.463 8.596 _N69 + PLL_158_55/CLK_OUT0 td 0.078 8.674 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.603 9.277 rd3_clk + USCM_84_154/CLK_USCM td 0.000 9.277 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.091 10.368 ntR3950 + PLL_158_303/CLK_OUT0 td 0.078 10.446 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 0.915 11.361 zoom_clk + USCM_84_118/CLK_USCM td 0.000 11.361 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 0.895 12.256 ntclkbufg_3 + APM_206_140/CLK r u_zoom_image/mult_image_g1_0/N2/gopapm/CLK + clock pessimism 0.332 12.588 + clock uncertainty -0.150 12.438 - Setup time -0.563 103.009 + Setup time -1.731 10.707 - Data required time 103.009 + Data required time 10.707 ---------------------------------------------------------------------------------------------------- - Data required time 103.009 - Data arrival time 7.115 + Data required time 10.707 + Data arrival time 8.214 ---------------------------------------------------------------------------------------------------- - Slack (MET) 95.894 + Slack (MET) 2.493 ==================================================================================================== ==================================================================================================== -Startpoint : ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK -Endpoint : ms72xx_ctl/ms7200_ctl/data_in[3]/opit_0_inv_L5Q_perm/CE -Path Group : clk_10m +Startpoint : u_zoom_image/mult_fra0_0/N2/gopapm/CLK +Endpoint : u_zoom_image/mult_image_g0_0/N2/gopapm/X[1] +Path Group : clk_1080p60Hz Path Type : max (fast corner) Path Class : sequential timing path -Clock Skew : -0.015 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 3.437 - Launch Clock Delay : 3.737 - Clock Pessimism Removal : 0.285 +Clock Skew : -0.142 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 5.520 + Launch Clock Delay : 5.994 + Clock Pessimism Removal : 0.332 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_10m (rising edge) 0.000 0.000 r + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.578 clk_ibuf/ntD IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 - PLL_158_55/CLK_OUT4 td 0.084 2.198 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 - net (fanout=1) 0.614 2.812 clk_10m - USCM_84_110/CLK_USCM td 0.000 2.812 r clkbufg_3/gopclkbufg/CLKOUT - net (fanout=235) 0.925 3.737 ntclkbufg_3 - CLMS_242_113/CLK r ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK - - CLMS_242_113/Q3 tco 0.220 3.957 f ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/Q - net (fanout=3) 0.274 4.231 ms72xx_ctl/ms7200_ctl/dri_cnt [4] - CLMS_246_113/Y2 td 0.381 4.612 f ms72xx_ctl/ms7200_ctl/N8_3/gateop_perm/Z - net (fanout=1) 0.069 4.681 ms72xx_ctl/ms7200_ctl/_N95853 - CLMS_246_113/Y0 td 0.150 4.831 f ms72xx_ctl/ms7200_ctl/N1872_5/gateop_perm/Z - net (fanout=6) 0.271 5.102 ms72xx_ctl/ms7200_ctl/_N95857 - CLMS_242_117/Y1 td 0.244 5.346 f ms72xx_ctl/ms7200_ctl/N2053_1/gateop_perm/Z - net (fanout=15) 0.506 5.852 ms72xx_ctl/ms7200_ctl/N261 - CLMA_226_104/Y1 td 0.151 6.003 f ms72xx_ctl/ms7200_ctl/N40_9/gateop_perm/Z - net (fanout=4) 0.309 6.312 ms72xx_ctl/ms7200_ctl/N2093 [4] - CLMA_230_121/Y3 td 0.360 6.672 r ms72xx_ctl/ms7200_ctl/N1955/gateop_perm/Z - net (fanout=12) 0.302 6.974 ms72xx_ctl/ms7200_ctl/N1955 - CLMA_242_116/CECO td 0.141 7.115 r ms72xx_ctl/ms7200_ctl/data_in[6]/opit_0_inv_L5Q_perm/CEOUT - net (fanout=4) 0.000 7.115 ntR1773 - CLMA_242_120/CECI r ms72xx_ctl/ms7200_ctl/data_in[3]/opit_0_inv_L5Q_perm/CE - - Data arrival time 7.115 Logic Levels: 6 - Logic: 1.647ns(48.757%), Route: 1.731ns(51.243%) + PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.614 2.811 rd3_clk + USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.131 3.942 ntR3950 + PLL_158_303/CLK_OUT0 td 0.083 4.025 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 0.932 4.957 zoom_clk + USCM_84_118/CLK_USCM td 0.000 4.957 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 1.037 5.994 ntclkbufg_3 + APM_206_264/CLK r u_zoom_image/mult_fra0_0/N2/gopapm/CLK + + APM_206_264/P[8] tco 0.822 6.816 f u_zoom_image/mult_fra0_0/N2/gopapm/P[8] + net (fanout=3) 1.373 8.189 u_zoom_image/coe_mult_p0_0 [8] + APM_206_128/X[1] f u_zoom_image/mult_image_g0_0/N2/gopapm/X[1] + + Data arrival time 8.189 Logic Levels: 0 + Logic: 0.822ns(37.449%), Route: 1.373ns(62.551%) ---------------------------------------------------------------------------------------------------- - Clock clk_10m (rising edge) 100.000 100.000 r - P20 0.000 100.000 r clk (port) - net (fanout=1) 0.074 100.074 clk - IOBS_LR_328_209/DIN td 1.285 101.359 r clk_ibuf/opit_0/O - net (fanout=1) 0.000 101.359 clk_ibuf/ntD - IOL_327_210/INCK td 0.038 101.397 r clk_ibuf/opit_1/INCK - net (fanout=1) 0.463 101.860 _N69 - PLL_158_55/CLK_OUT4 td 0.079 101.939 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 - net (fanout=1) 0.603 102.542 clk_10m - USCM_84_110/CLK_USCM td 0.000 102.542 r clkbufg_3/gopclkbufg/CLKOUT - net (fanout=235) 0.895 103.437 ntclkbufg_3 - CLMA_242_120/CLK r ms72xx_ctl/ms7200_ctl/data_in[3]/opit_0_inv_L5Q_perm/CLK - clock pessimism 0.285 103.722 - clock uncertainty -0.150 103.572 + Clock clk_1080p60Hz (rising edge) 6.736 6.736 r + P20 0.000 6.736 r clk (port) + net (fanout=1) 0.074 6.810 clk + IOBS_LR_328_209/DIN td 1.285 8.095 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 8.095 clk_ibuf/ntD + IOL_327_210/INCK td 0.038 8.133 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.463 8.596 _N69 + PLL_158_55/CLK_OUT0 td 0.078 8.674 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.603 9.277 rd3_clk + USCM_84_154/CLK_USCM td 0.000 9.277 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.091 10.368 ntR3950 + PLL_158_303/CLK_OUT0 td 0.078 10.446 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 0.915 11.361 zoom_clk + USCM_84_118/CLK_USCM td 0.000 11.361 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 0.895 12.256 ntclkbufg_3 + APM_206_128/CLK r u_zoom_image/mult_image_g0_0/N2/gopapm/CLK + clock pessimism 0.332 12.588 + clock uncertainty -0.150 12.438 - Setup time -0.563 103.009 + Setup time -1.731 10.707 - Data required time 103.009 + Data required time 10.707 ---------------------------------------------------------------------------------------------------- - Data required time 103.009 - Data arrival time 7.115 + Data required time 10.707 + Data arrival time 8.189 ---------------------------------------------------------------------------------------------------- - Slack (MET) 95.894 + Slack (MET) 2.518 ==================================================================================================== ==================================================================================================== -Startpoint : ms72xx_ctl/ms7200_ctl/cmd_index[5]/opit_0_inv_A2Q21/CLK -Endpoint : ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/ADA0[9] -Path Group : clk_10m +Startpoint : u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK +Endpoint : u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[7] +Path Group : clk_1080p60Hz Path Type : min (fast corner) Path Class : sequential timing path Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 3.737 - Launch Clock Delay : 3.437 - Clock Pessimism Removal : -0.281 + Capture Clock Delay : 5.882 + Launch Clock Delay : 5.520 + Clock Pessimism Removal : -0.343 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_10m (rising edge) 0.000 0.000 r + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.359 clk_ibuf/ntD IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK net (fanout=1) 0.463 1.860 _N69 - PLL_158_55/CLK_OUT4 td 0.079 1.939 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 - net (fanout=1) 0.603 2.542 clk_10m - USCM_84_110/CLK_USCM td 0.000 2.542 r clkbufg_3/gopclkbufg/CLKOUT - net (fanout=235) 0.895 3.437 ntclkbufg_3 - CLMA_230_117/CLK r ms72xx_ctl/ms7200_ctl/cmd_index[5]/opit_0_inv_A2Q21/CLK + PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.603 2.541 rd3_clk + USCM_84_154/CLK_USCM td 0.000 2.541 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.091 3.632 ntR3950 + PLL_158_303/CLK_OUT0 td 0.078 3.710 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 0.915 4.625 zoom_clk + USCM_84_118/CLK_USCM td 0.000 4.625 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 0.895 5.520 ntclkbufg_3 + CLMA_146_76/CLK r u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK - CLMA_230_117/Q0 tco 0.182 3.619 r ms72xx_ctl/ms7200_ctl/cmd_index[5]/opit_0_inv_A2Q21/Q0 - net (fanout=3) 0.196 3.815 ms72xx_ctl/ms7200_ctl/cmd_index [4] - DRM_234_108/ADA0[9] r ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/ADA0[9] + CLMA_146_76/Q2 tco 0.183 5.703 r u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/Q0 + net (fanout=3) 0.162 5.865 u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/wr_addr [2] + DRM_142_68/ADA0[7] r u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[7] - Data arrival time 3.815 Logic Levels: 0 - Logic: 0.182ns(48.148%), Route: 0.196ns(51.852%) + Data arrival time 5.865 Logic Levels: 0 + Logic: 0.183ns(53.043%), Route: 0.162ns(46.957%) ---------------------------------------------------------------------------------------------------- - Clock clk_10m (rising edge) 0.000 0.000 r + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.578 clk_ibuf/ntD IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 - PLL_158_55/CLK_OUT4 td 0.084 2.198 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 - net (fanout=1) 0.614 2.812 clk_10m - USCM_84_110/CLK_USCM td 0.000 2.812 r clkbufg_3/gopclkbufg/CLKOUT - net (fanout=235) 0.925 3.737 ntclkbufg_3 - DRM_234_108/CLKA[0] r ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKA[0] - clock pessimism -0.281 3.456 - clock uncertainty 0.000 3.456 + PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.614 2.811 rd3_clk + USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.131 3.942 ntR3950 + PLL_158_303/CLK_OUT0 td 0.083 4.025 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 0.932 4.957 zoom_clk + USCM_84_118/CLK_USCM td 0.000 4.957 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 0.925 5.882 ntclkbufg_3 + DRM_142_68/CLKA[0] r u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKA + clock pessimism -0.343 5.539 + clock uncertainty 0.000 5.539 - Hold time 0.127 3.583 + Hold time 0.166 5.705 - Data required time 3.583 + Data required time 5.705 ---------------------------------------------------------------------------------------------------- - Data required time 3.583 - Data arrival time 3.815 + Data required time 5.705 + Data arrival time 5.865 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.232 + Slack (MET) 0.160 ==================================================================================================== ==================================================================================================== -Startpoint : ms72xx_ctl/ms7200_ctl/cmd_index[3]/opit_0_inv_A2Q21/CLK -Endpoint : ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/ADA0[8] -Path Group : clk_10m +Startpoint : u_zoom_image/wr_addr1[2]/opit_0_inv_A2Q21/CLK +Endpoint : u_zoom_image/zoom_ram1_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/ADA0[5] +Path Group : clk_1080p60Hz Path Type : min (fast corner) Path Class : sequential timing path Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 3.737 - Launch Clock Delay : 3.437 - Clock Pessimism Removal : -0.281 + Capture Clock Delay : 5.882 + Launch Clock Delay : 5.520 + Clock Pessimism Removal : -0.343 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_10m (rising edge) 0.000 0.000 r + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.359 clk_ibuf/ntD IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK net (fanout=1) 0.463 1.860 _N69 - PLL_158_55/CLK_OUT4 td 0.079 1.939 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 - net (fanout=1) 0.603 2.542 clk_10m - USCM_84_110/CLK_USCM td 0.000 2.542 r clkbufg_3/gopclkbufg/CLKOUT - net (fanout=235) 0.895 3.437 ntclkbufg_3 - CLMA_230_113/CLK r ms72xx_ctl/ms7200_ctl/cmd_index[3]/opit_0_inv_A2Q21/CLK + PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.603 2.541 rd3_clk + USCM_84_154/CLK_USCM td 0.000 2.541 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.091 3.632 ntR3950 + PLL_158_303/CLK_OUT0 td 0.078 3.710 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 0.915 4.625 zoom_clk + USCM_84_118/CLK_USCM td 0.000 4.625 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 0.895 5.520 ntclkbufg_3 + CLMS_174_177/CLK r u_zoom_image/wr_addr1[2]/opit_0_inv_A2Q21/CLK - CLMA_230_113/Q3 tco 0.182 3.619 r ms72xx_ctl/ms7200_ctl/cmd_index[3]/opit_0_inv_A2Q21/Q1 - net (fanout=3) 0.199 3.818 ms72xx_ctl/ms7200_ctl/cmd_index [3] - DRM_234_108/ADA0[8] r ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/ADA0[8] + CLMS_174_177/Q1 tco 0.184 5.704 r u_zoom_image/wr_addr1[2]/opit_0_inv_A2Q21/Q1 + net (fanout=6) 0.144 5.848 u_zoom_image/wr_addr1 [2] + DRM_178_168/ADA0[5] r u_zoom_image/zoom_ram1_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/ADA0[5] - Data arrival time 3.818 Logic Levels: 0 - Logic: 0.182ns(47.769%), Route: 0.199ns(52.231%) + Data arrival time 5.848 Logic Levels: 0 + Logic: 0.184ns(56.098%), Route: 0.144ns(43.902%) ---------------------------------------------------------------------------------------------------- - Clock clk_10m (rising edge) 0.000 0.000 r + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.578 clk_ibuf/ntD IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 - PLL_158_55/CLK_OUT4 td 0.084 2.198 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 - net (fanout=1) 0.614 2.812 clk_10m - USCM_84_110/CLK_USCM td 0.000 2.812 r clkbufg_3/gopclkbufg/CLKOUT - net (fanout=235) 0.925 3.737 ntclkbufg_3 - DRM_234_108/CLKA[0] r ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKA[0] - clock pessimism -0.281 3.456 - clock uncertainty 0.000 3.456 + PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.614 2.811 rd3_clk + USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.131 3.942 ntR3950 + PLL_158_303/CLK_OUT0 td 0.083 4.025 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 0.932 4.957 zoom_clk + USCM_84_118/CLK_USCM td 0.000 4.957 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 0.925 5.882 ntclkbufg_3 + DRM_178_168/CLKA[0] r u_zoom_image/zoom_ram1_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] + clock pessimism -0.343 5.539 + clock uncertainty 0.000 5.539 - Hold time 0.127 3.583 + Hold time 0.127 5.666 - Data required time 3.583 + Data required time 5.666 ---------------------------------------------------------------------------------------------------- - Data required time 3.583 - Data arrival time 3.818 + Data required time 5.666 + Data arrival time 5.848 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.235 + Slack (MET) 0.182 ==================================================================================================== ==================================================================================================== -Startpoint : ms72xx_ctl/ms7200_ctl/cmd_index[7]/opit_0_inv_A2Q21/CLK -Endpoint : ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/ADA0[12] -Path Group : clk_10m +Startpoint : u_zoom_image/image_valid[2][1]/opit_0/CLK +Endpoint : u_zoom_image/image_valid[3][1]/opit_0/D +Path Group : clk_1080p60Hz Path Type : min (fast corner) Path Class : sequential timing path -Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 3.737 - Launch Clock Delay : 3.437 - Clock Pessimism Removal : -0.281 +Clock Skew : 0.001 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 5.882 + Launch Clock Delay : 5.520 + Clock Pessimism Removal : -0.361 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_10m (rising edge) 0.000 0.000 r + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.359 clk_ibuf/ntD IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK net (fanout=1) 0.463 1.860 _N69 - PLL_158_55/CLK_OUT4 td 0.079 1.939 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 - net (fanout=1) 0.603 2.542 clk_10m - USCM_84_110/CLK_USCM td 0.000 2.542 r clkbufg_3/gopclkbufg/CLKOUT - net (fanout=235) 0.895 3.437 ntclkbufg_3 - CLMA_230_117/CLK r ms72xx_ctl/ms7200_ctl/cmd_index[7]/opit_0_inv_A2Q21/CLK - - CLMA_230_117/Q3 tco 0.182 3.619 r ms72xx_ctl/ms7200_ctl/cmd_index[7]/opit_0_inv_A2Q21/Q1 - net (fanout=3) 0.201 3.820 ms72xx_ctl/ms7200_ctl/cmd_index [7] - DRM_234_108/ADA0[12] r ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/ADA0[12] - - Data arrival time 3.820 Logic Levels: 0 - Logic: 0.182ns(47.520%), Route: 0.201ns(52.480%) + PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.603 2.541 rd3_clk + USCM_84_154/CLK_USCM td 0.000 2.541 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.091 3.632 ntR3950 + PLL_158_303/CLK_OUT0 td 0.078 3.710 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 0.915 4.625 zoom_clk + USCM_84_118/CLK_USCM td 0.000 4.625 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 0.895 5.520 ntclkbufg_3 + CLMA_210_153/CLK r u_zoom_image/image_valid[2][1]/opit_0/CLK + + CLMA_210_153/Q3 tco 0.178 5.698 f u_zoom_image/image_valid[2][1]/opit_0/Q + net (fanout=1) 0.058 5.756 u_zoom_image/image_valid[2] [1] + CLMA_210_153/AD f u_zoom_image/image_valid[3][1]/opit_0/D + + Data arrival time 5.756 Logic Levels: 0 + Logic: 0.178ns(75.424%), Route: 0.058ns(24.576%) ---------------------------------------------------------------------------------------------------- - Clock clk_10m (rising edge) 0.000 0.000 r + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.578 clk_ibuf/ntD IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 - PLL_158_55/CLK_OUT4 td 0.084 2.198 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 - net (fanout=1) 0.614 2.812 clk_10m - USCM_84_110/CLK_USCM td 0.000 2.812 r clkbufg_3/gopclkbufg/CLKOUT - net (fanout=235) 0.925 3.737 ntclkbufg_3 - DRM_234_108/CLKA[0] r ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKA[0] - clock pessimism -0.281 3.456 - clock uncertainty 0.000 3.456 + PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.614 2.811 rd3_clk + USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.131 3.942 ntR3950 + PLL_158_303/CLK_OUT0 td 0.083 4.025 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 0.932 4.957 zoom_clk + USCM_84_118/CLK_USCM td 0.000 4.957 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 0.925 5.882 ntclkbufg_3 + CLMA_210_153/CLK r u_zoom_image/image_valid[3][1]/opit_0/CLK + clock pessimism -0.361 5.521 + clock uncertainty 0.000 5.521 - Hold time 0.127 3.583 + Hold time 0.040 5.561 - Data required time 3.583 + Data required time 5.561 ---------------------------------------------------------------------------------------------------- - Data required time 3.583 - Data arrival time 3.820 + Data required time 5.561 + Data arrival time 5.756 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.237 + Slack (MET) 0.195 ==================================================================================================== ==================================================================================================== -Startpoint : u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK -Endpoint : udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[0]/opit_0_L5Q_perm/CE +Startpoint : udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/rd_cnt[5]/opit_0_A2Q21/CLK +Endpoint : udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0_A2Q1/Cin Path Group : clk_720p60Hz Path Type : max (fast corner) Path Class : sequential timing path Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.516 - Launch Clock Delay : 5.878 - Clock Pessimism Removal : 0.343 + Capture Clock Delay : 5.626 + Launch Clock Delay : 5.990 + Clock Pessimism Removal : 0.345 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -10887,37 +12143,35 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 0.614 2.811 rd3_clk USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.131 3.942 ntR3907 + net (fanout=1) 1.131 3.942 ntR3950 PLL_158_303/CLK_OUT1 td 0.079 4.021 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 net (fanout=2) 0.932 4.953 nt_pix_clk USCM_84_117/CLK_USCM td 0.000 4.953 r clkbufg_2/gopclkbufg/CLKOUT - net (fanout=1635) 0.925 5.878 ntclkbufg_2 - CLMS_186_117/CLK r u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK - - CLMS_186_117/Q2 tco 0.223 6.101 f u_sync_vg/pos_y[8]/opit_0_A2Q21/Q0 - net (fanout=1) 0.530 6.631 pos_y[7] - CLMA_186_116/COUT td 0.397 7.028 r udp_osd_inst/N29.eq_2/gateop_A2/Cout - net (fanout=1) 0.000 7.028 udp_osd_inst/N29.co [6] - CLMA_186_120/Y1 td 0.383 7.411 r udp_osd_inst/N29.eq_4/gateop_A2/Y1 - net (fanout=5) 0.247 7.658 udp_osd_inst/N29 - CLMA_190_120/Y3 td 0.222 7.880 f udp_osd_inst/N69_5/gateop_perm/Z - net (fanout=2) 0.356 8.236 udp_osd_inst/char_osd_inst/pixels_shifter_inst/N64 - CLMA_186_112/Y1 td 0.151 8.387 f udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/gateop_perm/Z - net (fanout=2) 0.255 8.642 udp_osd_inst/char_osd_inst/row_pixels_ready - CLMA_186_108/Y2 td 0.150 8.792 f udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/gateop_perm/Z - net (fanout=6) 0.399 9.191 udp_osd_inst/char_osd_inst/char_next - CLMA_182_88/Y3 td 0.162 9.353 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N79/gateop_perm/Z - net (fanout=1) 0.148 9.501 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N79 - CLMA_182_88/Y2 td 0.150 9.651 f udp_osd_inst/char_osd_inst/char_buf_reader_inst/N358_5/gateop_perm/Z - net (fanout=3) 0.352 10.003 udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N96518 - CLMA_186_80/Y0 td 0.264 10.267 f udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786/gateop_perm/Z - net (fanout=1) 0.359 10.626 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786 - CLMA_182_73/CECO td 0.132 10.758 f udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[4]/opit_0_A2Q21/CEOUT - net (fanout=4) 0.000 10.758 ntR2038 - CLMA_182_77/CECI f udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[0]/opit_0_L5Q_perm/CE - - Data arrival time 10.758 Logic Levels: 9 - Logic: 2.234ns(45.779%), Route: 2.646ns(54.221%) + net (fanout=1635) 1.037 5.990 ntclkbufg_2 + CLMA_214_292/CLK r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/rd_cnt[5]/opit_0_A2Q21/CLK + + CLMA_214_292/Q1 tco 0.223 6.213 f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/rd_cnt[5]/opit_0_A2Q21/Q1 + net (fanout=3) 0.352 6.565 udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/rd_cnt [5] + CLMA_218_284/Y1 td 0.244 6.809 f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N140_20/gateop_perm/Z + net (fanout=1) 0.467 7.276 udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N107752 + CLMA_214_280/Y1 td 0.360 7.636 f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N140_29/gateop_perm/Z + net (fanout=3) 0.169 7.805 udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N98274 + CLMA_214_284/Y1 td 0.151 7.956 f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N135_7/gateop_perm/Z + net (fanout=15) 0.628 8.584 udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/fifo_rd_data_en + td 0.365 8.949 f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/opit_0_inv_A2Q1/Cout + net (fanout=1) 0.000 8.949 udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N13665 + CLMS_186_277/COUT td 0.044 8.993 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/opit_0_inv_A2Q21/Cout + net (fanout=1) 0.000 8.993 udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N13667 + CLMS_186_281/Y1 td 0.383 9.376 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/opit_0_inv_A2Q21/Y1 + net (fanout=3) 0.282 9.658 udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N84 [5] + CLMA_186_292/Y2 td 0.379 10.037 f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[5]/gateop_perm/Z + net (fanout=1) 0.396 10.433 udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rrptr [5] + CLMS_190_285/COUT td 0.394 10.827 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N170.eq_2/gateop_A2/Cout + net (fanout=1) 0.000 10.827 udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N170.co [6] + CLMS_190_289/CIN r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0_A2Q1/Cin + + Data arrival time 10.827 Logic Levels: 7 + Logic: 2.543ns(52.574%), Route: 2.294ns(47.426%) ---------------------------------------------------------------------------------------------------- Clock clk_720p60Hz (rising edge) 13.473 13.473 r @@ -10930,36 +12184,36 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi PLL_158_55/CLK_OUT0 td 0.078 15.411 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 0.603 16.014 rd3_clk USCM_84_154/CLK_USCM td 0.000 16.014 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.091 17.105 ntR3907 + net (fanout=1) 1.091 17.105 ntR3950 PLL_158_303/CLK_OUT1 td 0.074 17.179 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 net (fanout=2) 0.915 18.094 nt_pix_clk USCM_84_117/CLK_USCM td 0.000 18.094 r clkbufg_2/gopclkbufg/CLKOUT - net (fanout=1635) 0.895 18.989 ntclkbufg_2 - CLMA_182_77/CLK r udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[0]/opit_0_L5Q_perm/CLK - clock pessimism 0.343 19.332 - clock uncertainty -0.150 19.182 + net (fanout=1635) 1.005 19.099 ntclkbufg_2 + CLMS_190_289/CLK r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0_A2Q1/CLK + clock pessimism 0.345 19.444 + clock uncertainty -0.150 19.294 - Setup time -0.576 18.606 + Setup time -0.276 19.018 - Data required time 18.606 + Data required time 19.018 ---------------------------------------------------------------------------------------------------- - Data required time 18.606 - Data arrival time 10.758 + Data required time 19.018 + Data arrival time 10.827 ---------------------------------------------------------------------------------------------------- - Slack (MET) 7.848 + Slack (MET) 8.191 ==================================================================================================== ==================================================================================================== Startpoint : u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK -Endpoint : udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[1]/opit_0_L5Q_perm/CE +Endpoint : udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[0]/opit_0_L5Q_perm/CE Path Group : clk_720p60Hz Path Type : max (fast corner) Path Class : sequential timing path Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.516 - Launch Clock Delay : 5.878 - Clock Pessimism Removal : 0.343 + Capture Clock Delay : 5.626 + Launch Clock Delay : 5.990 + Clock Pessimism Removal : 0.345 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -10974,37 +12228,37 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 0.614 2.811 rd3_clk USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.131 3.942 ntR3907 + net (fanout=1) 1.131 3.942 ntR3950 PLL_158_303/CLK_OUT1 td 0.079 4.021 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 net (fanout=2) 0.932 4.953 nt_pix_clk USCM_84_117/CLK_USCM td 0.000 4.953 r clkbufg_2/gopclkbufg/CLKOUT - net (fanout=1635) 0.925 5.878 ntclkbufg_2 - CLMS_186_117/CLK r u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK - - CLMS_186_117/Q2 tco 0.223 6.101 f u_sync_vg/pos_y[8]/opit_0_A2Q21/Q0 - net (fanout=1) 0.530 6.631 pos_y[7] - CLMA_186_116/COUT td 0.397 7.028 r udp_osd_inst/N29.eq_2/gateop_A2/Cout - net (fanout=1) 0.000 7.028 udp_osd_inst/N29.co [6] - CLMA_186_120/Y1 td 0.383 7.411 r udp_osd_inst/N29.eq_4/gateop_A2/Y1 - net (fanout=5) 0.247 7.658 udp_osd_inst/N29 - CLMA_190_120/Y3 td 0.222 7.880 f udp_osd_inst/N69_5/gateop_perm/Z - net (fanout=2) 0.356 8.236 udp_osd_inst/char_osd_inst/pixels_shifter_inst/N64 - CLMA_186_112/Y1 td 0.151 8.387 f udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/gateop_perm/Z - net (fanout=2) 0.255 8.642 udp_osd_inst/char_osd_inst/row_pixels_ready - CLMA_186_108/Y2 td 0.150 8.792 f udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/gateop_perm/Z - net (fanout=6) 0.399 9.191 udp_osd_inst/char_osd_inst/char_next - CLMA_182_88/Y3 td 0.162 9.353 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N79/gateop_perm/Z - net (fanout=1) 0.148 9.501 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N79 - CLMA_182_88/Y2 td 0.150 9.651 f udp_osd_inst/char_osd_inst/char_buf_reader_inst/N358_5/gateop_perm/Z - net (fanout=3) 0.352 10.003 udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N96518 - CLMA_186_80/Y0 td 0.264 10.267 f udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786/gateop_perm/Z - net (fanout=1) 0.359 10.626 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786 - CLMA_182_73/CECO td 0.132 10.758 f udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[4]/opit_0_A2Q21/CEOUT - net (fanout=4) 0.000 10.758 ntR2038 - CLMA_182_77/CECI f udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[1]/opit_0_L5Q_perm/CE - - Data arrival time 10.758 Logic Levels: 9 - Logic: 2.234ns(45.779%), Route: 2.646ns(54.221%) + net (fanout=1635) 1.037 5.990 ntclkbufg_2 + CLMA_246_256/CLK r u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK + + CLMA_246_256/Q2 tco 0.223 6.213 f u_sync_vg/pos_y[8]/opit_0_A2Q21/Q0 + net (fanout=1) 0.460 6.673 pos_y[7] + CLMS_242_257/COUT td 0.397 7.070 r udp_osd_inst/N29.eq_2/gateop_A2/Cout + net (fanout=1) 0.000 7.070 udp_osd_inst/N29.co [6] + CLMS_242_261/Y1 td 0.383 7.453 r udp_osd_inst/N29.eq_4/gateop_A2/Y1 + net (fanout=5) 0.285 7.738 udp_osd_inst/N29 + CLMA_250_257/Y2 td 0.227 7.965 f udp_osd_inst/N69_5/gateop_perm/Z + net (fanout=2) 0.156 8.121 udp_osd_inst/char_osd_inst/pixels_shifter_inst/N64 + CLMA_250_257/Y3 td 0.151 8.272 f udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/gateop_perm/Z + net (fanout=2) 0.253 8.525 udp_osd_inst/char_osd_inst/row_pixels_ready + CLMA_250_261/Y1 td 0.151 8.676 f udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/gateop_perm/Z + net (fanout=12) 0.417 9.093 udp_osd_inst/char_osd_inst/char_next + CLMA_246_284/Y2 td 0.162 9.255 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N74/gateop_perm/Z + net (fanout=1) 0.148 9.403 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N74 + CLMA_246_284/Y1 td 0.151 9.554 f udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_fsm[3:0]_62/gateop_perm/Z + net (fanout=3) 0.255 9.809 udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N97126 + CLMA_250_284/Y0 td 0.150 9.959 f udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786/gateop_perm/Z + net (fanout=1) 0.249 10.208 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786 + CLMA_254_288/CECO td 0.132 10.340 f udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[4]/opit_0_A2Q21/CEOUT + net (fanout=4) 0.000 10.340 ntR2066 + CLMA_254_292/CECI f udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[0]/opit_0_L5Q_perm/CE + + Data arrival time 10.340 Logic Levels: 9 + Logic: 2.127ns(48.897%), Route: 2.223ns(51.103%) ---------------------------------------------------------------------------------------------------- Clock clk_720p60Hz (rising edge) 13.473 13.473 r @@ -11017,36 +12271,36 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi PLL_158_55/CLK_OUT0 td 0.078 15.411 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 0.603 16.014 rd3_clk USCM_84_154/CLK_USCM td 0.000 16.014 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.091 17.105 ntR3907 + net (fanout=1) 1.091 17.105 ntR3950 PLL_158_303/CLK_OUT1 td 0.074 17.179 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 net (fanout=2) 0.915 18.094 nt_pix_clk USCM_84_117/CLK_USCM td 0.000 18.094 r clkbufg_2/gopclkbufg/CLKOUT - net (fanout=1635) 0.895 18.989 ntclkbufg_2 - CLMA_182_77/CLK r udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[1]/opit_0_L5Q_perm/CLK - clock pessimism 0.343 19.332 - clock uncertainty -0.150 19.182 + net (fanout=1635) 1.005 19.099 ntclkbufg_2 + CLMA_254_292/CLK r udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[0]/opit_0_L5Q_perm/CLK + clock pessimism 0.345 19.444 + clock uncertainty -0.150 19.294 - Setup time -0.576 18.606 + Setup time -0.576 18.718 - Data required time 18.606 + Data required time 18.718 ---------------------------------------------------------------------------------------------------- - Data required time 18.606 - Data arrival time 10.758 + Data required time 18.718 + Data arrival time 10.340 ---------------------------------------------------------------------------------------------------- - Slack (MET) 7.848 + Slack (MET) 8.378 ==================================================================================================== ==================================================================================================== Startpoint : u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK -Endpoint : udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[2]/opit_0_L5Q_perm/CE +Endpoint : udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[1]/opit_0_L5Q_perm/CE Path Group : clk_720p60Hz Path Type : max (fast corner) Path Class : sequential timing path Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.516 - Launch Clock Delay : 5.878 - Clock Pessimism Removal : 0.343 + Capture Clock Delay : 5.626 + Launch Clock Delay : 5.990 + Clock Pessimism Removal : 0.345 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -11061,37 +12315,37 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 0.614 2.811 rd3_clk USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.131 3.942 ntR3907 + net (fanout=1) 1.131 3.942 ntR3950 PLL_158_303/CLK_OUT1 td 0.079 4.021 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 net (fanout=2) 0.932 4.953 nt_pix_clk USCM_84_117/CLK_USCM td 0.000 4.953 r clkbufg_2/gopclkbufg/CLKOUT - net (fanout=1635) 0.925 5.878 ntclkbufg_2 - CLMS_186_117/CLK r u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK - - CLMS_186_117/Q2 tco 0.223 6.101 f u_sync_vg/pos_y[8]/opit_0_A2Q21/Q0 - net (fanout=1) 0.530 6.631 pos_y[7] - CLMA_186_116/COUT td 0.397 7.028 r udp_osd_inst/N29.eq_2/gateop_A2/Cout - net (fanout=1) 0.000 7.028 udp_osd_inst/N29.co [6] - CLMA_186_120/Y1 td 0.383 7.411 r udp_osd_inst/N29.eq_4/gateop_A2/Y1 - net (fanout=5) 0.247 7.658 udp_osd_inst/N29 - CLMA_190_120/Y3 td 0.222 7.880 f udp_osd_inst/N69_5/gateop_perm/Z - net (fanout=2) 0.356 8.236 udp_osd_inst/char_osd_inst/pixels_shifter_inst/N64 - CLMA_186_112/Y1 td 0.151 8.387 f udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/gateop_perm/Z - net (fanout=2) 0.255 8.642 udp_osd_inst/char_osd_inst/row_pixels_ready - CLMA_186_108/Y2 td 0.150 8.792 f udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/gateop_perm/Z - net (fanout=6) 0.399 9.191 udp_osd_inst/char_osd_inst/char_next - CLMA_182_88/Y3 td 0.162 9.353 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N79/gateop_perm/Z - net (fanout=1) 0.148 9.501 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N79 - CLMA_182_88/Y2 td 0.150 9.651 f udp_osd_inst/char_osd_inst/char_buf_reader_inst/N358_5/gateop_perm/Z - net (fanout=3) 0.352 10.003 udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N96518 - CLMA_186_80/Y0 td 0.264 10.267 f udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786/gateop_perm/Z - net (fanout=1) 0.359 10.626 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786 - CLMA_182_73/CECO td 0.132 10.758 f udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[4]/opit_0_A2Q21/CEOUT - net (fanout=4) 0.000 10.758 ntR2038 - CLMA_182_77/CECI f udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[2]/opit_0_L5Q_perm/CE - - Data arrival time 10.758 Logic Levels: 9 - Logic: 2.234ns(45.779%), Route: 2.646ns(54.221%) + net (fanout=1635) 1.037 5.990 ntclkbufg_2 + CLMA_246_256/CLK r u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK + + CLMA_246_256/Q2 tco 0.223 6.213 f u_sync_vg/pos_y[8]/opit_0_A2Q21/Q0 + net (fanout=1) 0.460 6.673 pos_y[7] + CLMS_242_257/COUT td 0.397 7.070 r udp_osd_inst/N29.eq_2/gateop_A2/Cout + net (fanout=1) 0.000 7.070 udp_osd_inst/N29.co [6] + CLMS_242_261/Y1 td 0.383 7.453 r udp_osd_inst/N29.eq_4/gateop_A2/Y1 + net (fanout=5) 0.285 7.738 udp_osd_inst/N29 + CLMA_250_257/Y2 td 0.227 7.965 f udp_osd_inst/N69_5/gateop_perm/Z + net (fanout=2) 0.156 8.121 udp_osd_inst/char_osd_inst/pixels_shifter_inst/N64 + CLMA_250_257/Y3 td 0.151 8.272 f udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/gateop_perm/Z + net (fanout=2) 0.253 8.525 udp_osd_inst/char_osd_inst/row_pixels_ready + CLMA_250_261/Y1 td 0.151 8.676 f udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/gateop_perm/Z + net (fanout=12) 0.417 9.093 udp_osd_inst/char_osd_inst/char_next + CLMA_246_284/Y2 td 0.162 9.255 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N74/gateop_perm/Z + net (fanout=1) 0.148 9.403 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N74 + CLMA_246_284/Y1 td 0.151 9.554 f udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_fsm[3:0]_62/gateop_perm/Z + net (fanout=3) 0.255 9.809 udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N97126 + CLMA_250_284/Y0 td 0.150 9.959 f udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786/gateop_perm/Z + net (fanout=1) 0.249 10.208 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786 + CLMA_254_288/CECO td 0.132 10.340 f udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[4]/opit_0_A2Q21/CEOUT + net (fanout=4) 0.000 10.340 ntR2066 + CLMA_254_292/CECI f udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[1]/opit_0_L5Q_perm/CE + + Data arrival time 10.340 Logic Levels: 9 + Logic: 2.127ns(48.897%), Route: 2.223ns(51.103%) ---------------------------------------------------------------------------------------------------- Clock clk_720p60Hz (rising edge) 13.473 13.473 r @@ -11104,29 +12358,29 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi PLL_158_55/CLK_OUT0 td 0.078 15.411 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 0.603 16.014 rd3_clk USCM_84_154/CLK_USCM td 0.000 16.014 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.091 17.105 ntR3907 + net (fanout=1) 1.091 17.105 ntR3950 PLL_158_303/CLK_OUT1 td 0.074 17.179 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 net (fanout=2) 0.915 18.094 nt_pix_clk USCM_84_117/CLK_USCM td 0.000 18.094 r clkbufg_2/gopclkbufg/CLKOUT - net (fanout=1635) 0.895 18.989 ntclkbufg_2 - CLMA_182_77/CLK r udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[2]/opit_0_L5Q_perm/CLK - clock pessimism 0.343 19.332 - clock uncertainty -0.150 19.182 + net (fanout=1635) 1.005 19.099 ntclkbufg_2 + CLMA_254_292/CLK r udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[1]/opit_0_L5Q_perm/CLK + clock pessimism 0.345 19.444 + clock uncertainty -0.150 19.294 - Setup time -0.576 18.606 + Setup time -0.576 18.718 - Data required time 18.606 + Data required time 18.718 ---------------------------------------------------------------------------------------------------- - Data required time 18.606 - Data arrival time 10.758 + Data required time 18.718 + Data arrival time 10.340 ---------------------------------------------------------------------------------------------------- - Slack (MET) 7.848 + Slack (MET) 8.378 ==================================================================================================== ==================================================================================================== -Startpoint : adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/quotient[1]/opit_0_L5Q_perm/CLK -Endpoint : adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/quotient[2]/opit_0_L5Q_perm/L4 +Startpoint : adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm/CLK +Endpoint : adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm/L4 Path Group : clk_720p60Hz Path Type : min (fast corner) Path Class : sequential timing path @@ -11148,16 +12402,16 @@ Clock Skew : 0.015 (Capture Clock Delay - Launch Clock Delay + Clock Pessim PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 0.603 2.541 rd3_clk USCM_84_154/CLK_USCM td 0.000 2.541 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.091 3.632 ntR3907 + net (fanout=1) 1.091 3.632 ntR3950 PLL_158_303/CLK_OUT1 td 0.074 3.706 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 net (fanout=2) 0.915 4.621 nt_pix_clk USCM_84_117/CLK_USCM td 0.000 4.621 r clkbufg_2/gopclkbufg/CLKOUT net (fanout=1635) 0.895 5.516 ntclkbufg_2 - CLMA_266_132/CLK r adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/quotient[1]/opit_0_L5Q_perm/CLK + CLMA_250_177/CLK r adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm/CLK - CLMA_266_132/Q1 tco 0.180 5.696 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/quotient[1]/opit_0_L5Q_perm/Q - net (fanout=1) 0.058 5.754 adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/quotient_t[4] [1] - CLMS_266_133/C4 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/quotient[2]/opit_0_L5Q_perm/L4 + CLMA_250_177/Q2 tco 0.180 5.696 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm/Q + net (fanout=1) 0.058 5.754 adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/dividend_t[13] [9] + CLMA_250_176/A4 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm/L4 Data arrival time 5.754 Logic Levels: 0 Logic: 0.180ns(75.630%), Route: 0.058ns(24.370%) @@ -11173,36 +12427,36 @@ Clock Skew : 0.015 (Capture Clock Delay - Launch Clock Delay + Clock Pessim PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 0.614 2.811 rd3_clk USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.131 3.942 ntR3907 + net (fanout=1) 1.131 3.942 ntR3950 PLL_158_303/CLK_OUT1 td 0.079 4.021 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 net (fanout=2) 0.932 4.953 nt_pix_clk USCM_84_117/CLK_USCM td 0.000 4.953 r clkbufg_2/gopclkbufg/CLKOUT net (fanout=1635) 0.925 5.878 ntclkbufg_2 - CLMS_266_133/CLK r adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/quotient[2]/opit_0_L5Q_perm/CLK + CLMA_250_176/CLK r adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm/CLK clock pessimism -0.347 5.531 clock uncertainty 0.000 5.531 - Hold time -0.028 5.503 + Hold time -0.029 5.502 - Data required time 5.503 + Data required time 5.502 ---------------------------------------------------------------------------------------------------- - Data required time 5.503 + Data required time 5.502 Data arrival time 5.754 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.251 + Slack (MET) 0.252 ==================================================================================================== ==================================================================================================== -Startpoint : adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[3]/opit_0_L5Q_perm/CLK -Endpoint : adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[4]/opit_0_L5Q_perm/L4 +Startpoint : udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[3]/opit_0_A2Q21/CLK +Endpoint : udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr[4]/opit_0_A2Q21/I04 Path Group : clk_720p60Hz Path Type : min (fast corner) Path Class : sequential timing path Clock Skew : 0.015 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.878 - Launch Clock Delay : 5.516 - Clock Pessimism Removal : -0.347 + Capture Clock Delay : 5.990 + Launch Clock Delay : 5.626 + Clock Pessimism Removal : -0.349 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -11217,19 +12471,19 @@ Clock Skew : 0.015 (Capture Clock Delay - Launch Clock Delay + Clock Pessim PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 0.603 2.541 rd3_clk USCM_84_154/CLK_USCM td 0.000 2.541 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.091 3.632 ntR3907 + net (fanout=1) 1.091 3.632 ntR3950 PLL_158_303/CLK_OUT1 td 0.074 3.706 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 net (fanout=2) 0.915 4.621 nt_pix_clk USCM_84_117/CLK_USCM td 0.000 4.621 r clkbufg_2/gopclkbufg/CLKOUT - net (fanout=1635) 0.895 5.516 ntclkbufg_2 - CLMA_262_132/CLK r adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[3]/opit_0_L5Q_perm/CLK + net (fanout=1635) 1.005 5.626 ntclkbufg_2 + CLMA_230_280/CLK r udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[3]/opit_0_A2Q21/CLK - CLMA_262_132/Q2 tco 0.180 5.696 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[3]/opit_0_L5Q_perm/Q - net (fanout=1) 0.058 5.754 adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/quotient_t[1] [3] - CLMS_262_133/A4 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[4]/opit_0_L5Q_perm/L4 + CLMA_230_280/Q1 tco 0.180 5.806 f udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[3]/opit_0_A2Q21/Q1 + net (fanout=2) 0.059 5.865 udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d [3] + CLMA_230_281/C4 f udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr[4]/opit_0_A2Q21/I04 - Data arrival time 5.754 Logic Levels: 0 - Logic: 0.180ns(75.630%), Route: 0.058ns(24.370%) + Data arrival time 5.865 Logic Levels: 0 + Logic: 0.180ns(75.314%), Route: 0.059ns(24.686%) ---------------------------------------------------------------------------------------------------- Clock clk_720p60Hz (rising edge) 0.000 0.000 r @@ -11242,36 +12496,36 @@ Clock Skew : 0.015 (Capture Clock Delay - Launch Clock Delay + Clock Pessim PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 0.614 2.811 rd3_clk USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.131 3.942 ntR3907 + net (fanout=1) 1.131 3.942 ntR3950 PLL_158_303/CLK_OUT1 td 0.079 4.021 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 net (fanout=2) 0.932 4.953 nt_pix_clk USCM_84_117/CLK_USCM td 0.000 4.953 r clkbufg_2/gopclkbufg/CLKOUT - net (fanout=1635) 0.925 5.878 ntclkbufg_2 - CLMS_262_133/CLK r adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[4]/opit_0_L5Q_perm/CLK - clock pessimism -0.347 5.531 - clock uncertainty 0.000 5.531 + net (fanout=1635) 1.037 5.990 ntclkbufg_2 + CLMA_230_281/CLK r udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr[4]/opit_0_A2Q21/CLK + clock pessimism -0.349 5.641 + clock uncertainty 0.000 5.641 - Hold time -0.029 5.502 + Hold time -0.028 5.613 - Data required time 5.502 + Data required time 5.613 ---------------------------------------------------------------------------------------------------- - Data required time 5.502 - Data arrival time 5.754 + Data required time 5.613 + Data arrival time 5.865 ---------------------------------------------------------------------------------------------------- Slack (MET) 0.252 ==================================================================================================== ==================================================================================================== -Startpoint : udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[3]/opit_0_A2Q21/CLK -Endpoint : udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr[4]/opit_0_A2Q21/I04 +Startpoint : u_sync_vg/v_count[3]/opit_0_L5Q_perm/CLK +Endpoint : u_sync_vg/pos_y[4]/opit_0_A2Q21/I04 Path Group : clk_720p60Hz Path Type : min (fast corner) Path Class : sequential timing path Clock Skew : 0.015 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.878 - Launch Clock Delay : 5.516 - Clock Pessimism Removal : -0.347 + Capture Clock Delay : 5.990 + Launch Clock Delay : 5.626 + Clock Pessimism Removal : -0.349 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -11286,19 +12540,19 @@ Clock Skew : 0.015 (Capture Clock Delay - Launch Clock Delay + Clock Pessim PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 0.603 2.541 rd3_clk USCM_84_154/CLK_USCM td 0.000 2.541 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.091 3.632 ntR3907 + net (fanout=1) 1.091 3.632 ntR3950 PLL_158_303/CLK_OUT1 td 0.074 3.706 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 net (fanout=2) 0.915 4.621 nt_pix_clk USCM_84_117/CLK_USCM td 0.000 4.621 r clkbufg_2/gopclkbufg/CLKOUT - net (fanout=1635) 0.895 5.516 ntclkbufg_2 - CLMA_174_52/CLK r udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[3]/opit_0_A2Q21/CLK + net (fanout=1635) 1.005 5.626 ntclkbufg_2 + CLMS_246_253/CLK r u_sync_vg/v_count[3]/opit_0_L5Q_perm/CLK - CLMA_174_52/Q1 tco 0.180 5.696 f udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[3]/opit_0_A2Q21/Q1 - net (fanout=2) 0.059 5.755 udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d [3] - CLMS_174_53/C4 f udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr[4]/opit_0_A2Q21/I04 + CLMS_246_253/Q1 tco 0.180 5.806 f u_sync_vg/v_count[3]/opit_0_L5Q_perm/Q + net (fanout=7) 0.064 5.870 u_sync_vg/v_count [3] + CLMA_246_252/C4 f u_sync_vg/pos_y[4]/opit_0_A2Q21/I04 - Data arrival time 5.755 Logic Levels: 0 - Logic: 0.180ns(75.314%), Route: 0.059ns(24.686%) + Data arrival time 5.870 Logic Levels: 0 + Logic: 0.180ns(73.770%), Route: 0.064ns(26.230%) ---------------------------------------------------------------------------------------------------- Clock clk_720p60Hz (rising edge) 0.000 0.000 r @@ -11311,36 +12565,36 @@ Clock Skew : 0.015 (Capture Clock Delay - Launch Clock Delay + Clock Pessim PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 0.614 2.811 rd3_clk USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.131 3.942 ntR3907 + net (fanout=1) 1.131 3.942 ntR3950 PLL_158_303/CLK_OUT1 td 0.079 4.021 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 net (fanout=2) 0.932 4.953 nt_pix_clk USCM_84_117/CLK_USCM td 0.000 4.953 r clkbufg_2/gopclkbufg/CLKOUT - net (fanout=1635) 0.925 5.878 ntclkbufg_2 - CLMS_174_53/CLK r udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr[4]/opit_0_A2Q21/CLK - clock pessimism -0.347 5.531 - clock uncertainty 0.000 5.531 + net (fanout=1635) 1.037 5.990 ntclkbufg_2 + CLMA_246_252/CLK r u_sync_vg/pos_y[4]/opit_0_A2Q21/CLK + clock pessimism -0.349 5.641 + clock uncertainty 0.000 5.641 - Hold time -0.028 5.503 + Hold time -0.028 5.613 - Data required time 5.503 + Data required time 5.613 ---------------------------------------------------------------------------------------------------- - Data required time 5.503 - Data arrival time 5.755 + Data required time 5.613 + Data arrival time 5.870 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.252 + Slack (MET) 0.257 ==================================================================================================== ==================================================================================================== -Startpoint : u_ov5640/coms2_reg_config/reg_data/iGopDrm/CLKB[0] -Endpoint : u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I0 +Startpoint : u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0] +Endpoint : u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I0 Path Group : clk_20k Path Type : max (fast corner) Path Class : sequential timing path Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.644 - Launch Clock Delay : 6.109 - Clock Pessimism Removal : 0.446 + Capture Clock Delay : 5.862 + Launch Clock Delay : 6.370 + Clock Pessimism Removal : 0.489 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -11354,26 +12608,26 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi net (fanout=1) 0.478 2.114 _N69 PLL_158_55/CLK_OUT3 td 0.088 2.202 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 net (fanout=1) 0.614 2.816 clk_25m - USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 0.925 3.741 ntclkbufg_7 - CLMA_182_25/Q1 tco 0.224 3.965 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q - net (fanout=3) 1.219 5.184 u_ov5640/coms2_reg_config/clk_20k_regdiv - USCM_84_120/CLK_USCM td 0.000 5.184 r u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - net (fanout=19) 0.925 6.109 u_ov5640/coms2_reg_config/clock_20k - DRM_178_24/CLKB[0] r u_ov5640/coms2_reg_config/reg_data/iGopDrm/CLKB[0] - - DRM_178_24/QB0[5] tco 1.780 7.889 f u_ov5640/coms2_reg_config/reg_data/iGopDrm/QB0[5] - net (fanout=1) 0.327 8.216 u_ov5640/coms2_reg_config/i2c_data [21] - CLMA_174_32/Y3 td 0.358 8.574 f u_ov5640/coms2_reg_config/u1/N267_29/gateop/F - net (fanout=1) 0.250 8.824 u_ov5640/coms2_reg_config/u1/_N25904 - CLMS_174_29/Y2 td 0.162 8.986 r u_ov5640/coms2_reg_config/u1/N267_35/gateop_perm/Z - net (fanout=1) 0.152 9.138 u_ov5640/coms2_reg_config/u1/_N25910 - CLMS_174_29/Y1 td 0.212 9.350 f u_ov5640/coms2_reg_config/u1/N267_36/gateop/F - net (fanout=1) 0.167 9.517 u_ov5640/coms2_reg_config/u1/_N25911 - CLMS_174_25/DD f u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I0 - - Data arrival time 9.517 Logic Levels: 3 - Logic: 2.512ns(73.709%), Route: 0.896ns(26.291%) + USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 0.925 3.741 ntclkbufg_8 + CLMS_122_9/Q1 tco 0.224 3.965 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q + net (fanout=3) 1.480 5.445 u_ov5640/coms1_reg_config/clk_20k_regdiv + USCM_84_120/CLK_USCM td 0.000 5.445 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + net (fanout=19) 0.925 6.370 u_ov5640/coms1_reg_config/clock_20k + DRM_142_4/CLKB[0] r u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0] + + DRM_142_4/QB0[6] tco 1.780 8.150 f u_ov5640/coms1_reg_config/reg_data/iGopDrm/QB0[6] + net (fanout=1) 0.343 8.493 u_ov5640/coms1_reg_config/i2c_data [22] + CLMA_146_12/Y1 td 0.359 8.852 f u_ov5640/coms1_reg_config/u1/N267_29/gateop/F + net (fanout=1) 0.369 9.221 u_ov5640/coms1_reg_config/u1/_N25311 + CLMA_138_16/Y0 td 0.162 9.383 r u_ov5640/coms1_reg_config/u1/N267_35/gateop_perm/Z + net (fanout=1) 0.151 9.534 u_ov5640/coms1_reg_config/u1/_N25317 + CLMA_138_16/Y2 td 0.233 9.767 f u_ov5640/coms1_reg_config/u1/N267_36/gateop/F + net (fanout=1) 0.272 10.039 u_ov5640/coms1_reg_config/u1/_N25318 + CLMA_138_9/AD f u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I0 + + Data arrival time 10.039 Logic Levels: 3 + Logic: 2.534ns(69.065%), Route: 1.135ns(30.935%) ---------------------------------------------------------------------------------------------------- Clock clk_20k (rising edge) 50000.000 50000.000 r @@ -11385,37 +12639,37 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi net (fanout=1) 0.463 50001.860 _N69 PLL_158_55/CLK_OUT3 td 0.083 50001.943 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 net (fanout=1) 0.603 50002.546 clk_25m - USCM_84_114/CLK_USCM td 0.000 50002.546 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 0.895 50003.441 ntclkbufg_7 - CLMA_182_25/Q1 tco 0.184 50003.625 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q - net (fanout=3) 1.124 50004.749 u_ov5640/coms2_reg_config/clk_20k_regdiv - USCM_84_120/CLK_USCM td 0.000 50004.749 r u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - net (fanout=19) 0.895 50005.644 u_ov5640/coms2_reg_config/clock_20k - CLMS_174_25/CLK r u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/CLK - clock pessimism 0.446 50006.090 - clock uncertainty -0.050 50006.040 + USCM_84_114/CLK_USCM td 0.000 50002.546 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 0.895 50003.441 ntclkbufg_8 + CLMS_122_9/Q1 tco 0.184 50003.625 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q + net (fanout=3) 1.342 50004.967 u_ov5640/coms1_reg_config/clk_20k_regdiv + USCM_84_120/CLK_USCM td 0.000 50004.967 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + net (fanout=19) 0.895 50005.862 u_ov5640/coms1_reg_config/clock_20k + CLMA_138_9/CLK r u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/CLK + clock pessimism 0.489 50006.351 + clock uncertainty -0.050 50006.301 - Setup time -0.123 50005.917 + Setup time -0.151 50006.150 - Data required time 50005.917 + Data required time 50006.150 ---------------------------------------------------------------------------------------------------- - Data required time 50005.917 - Data arrival time 9.517 + Data required time 50006.150 + Data arrival time 10.039 ---------------------------------------------------------------------------------------------------- - Slack (MET) 49996.400 + Slack (MET) 49996.111 ==================================================================================================== ==================================================================================================== -Startpoint : u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0] -Endpoint : u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I0 +Startpoint : u_ov5640/coms2_reg_config/reg_data/iGopDrm/CLKB[0] +Endpoint : u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_L5Q_perm/L4 Path Group : clk_20k Path Type : max (fast corner) Path Class : sequential timing path -Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.784 - Launch Clock Delay : 6.274 - Clock Pessimism Removal : 0.471 +Clock Skew : -0.066 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 5.796 + Launch Clock Delay : 6.335 + Clock Pessimism Removal : 0.473 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -11429,26 +12683,26 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi net (fanout=1) 0.478 2.114 _N69 PLL_158_55/CLK_OUT3 td 0.088 2.202 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 net (fanout=1) 0.614 2.816 clk_25m - USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 0.925 3.741 ntclkbufg_7 - CLMA_182_12/Q1 tco 0.224 3.965 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q - net (fanout=3) 1.384 5.349 u_ov5640/coms1_reg_config/clk_20k_regdiv - USCM_84_119/CLK_USCM td 0.000 5.349 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - net (fanout=19) 0.925 6.274 u_ov5640/coms1_reg_config/clock_20k - DRM_178_4/CLKB[0] r u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0] - - DRM_178_4/QB0[6] tco 1.780 8.054 f u_ov5640/coms1_reg_config/reg_data/iGopDrm/QB0[6] - net (fanout=1) 0.400 8.454 u_ov5640/coms1_reg_config/i2c_data [22] - CLMS_174_9/Y2 td 0.379 8.833 f u_ov5640/coms1_reg_config/u1/N267_29/gateop/F - net (fanout=1) 0.069 8.902 u_ov5640/coms1_reg_config/u1/_N25461 - CLMA_174_8/Y0 td 0.162 9.064 r u_ov5640/coms1_reg_config/u1/N267_35/gateop_perm/Z - net (fanout=1) 0.072 9.136 u_ov5640/coms1_reg_config/u1/_N25467 - CLMA_174_8/Y1 td 0.211 9.347 r u_ov5640/coms1_reg_config/u1/N267_36/gateop/F - net (fanout=1) 0.268 9.615 u_ov5640/coms1_reg_config/u1/_N25468 - CLMA_174_16/DD r u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I0 - - Data arrival time 9.615 Logic Levels: 3 - Logic: 2.532ns(75.786%), Route: 0.809ns(24.214%) + USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 0.925 3.741 ntclkbufg_8 + CLMA_122_12/Q1 tco 0.224 3.965 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q + net (fanout=3) 1.398 5.363 u_ov5640/coms2_reg_config/clk_20k_regdiv + USCM_84_121/CLK_USCM td 0.000 5.363 r u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + net (fanout=19) 0.972 6.335 u_ov5640/coms2_reg_config/clock_20k + DRM_82_4/CLKB[0] r u_ov5640/coms2_reg_config/reg_data/iGopDrm/CLKB[0] + + DRM_82_4/QB0[5] tco 1.780 8.115 f u_ov5640/coms2_reg_config/reg_data/iGopDrm/QB0[5] + net (fanout=1) 0.306 8.421 u_ov5640/coms2_reg_config/i2c_data [21] + CLMS_78_9/Y1 td 0.359 8.780 f u_ov5640/coms2_reg_config/u1/N267_29/gateop/F + net (fanout=1) 0.391 9.171 u_ov5640/coms2_reg_config/u1/_N25853 + CLMA_90_12/Y2 td 0.162 9.333 r u_ov5640/coms2_reg_config/u1/N267_35/gateop_perm/Z + net (fanout=1) 0.151 9.484 u_ov5640/coms2_reg_config/u1/_N25859 + CLMA_90_12/Y6AB td 0.200 9.684 r u_ov5640/coms2_reg_config/u1/N267_37_muxf6/F + net (fanout=1) 0.151 9.835 u_ov5640/coms2_reg_config/u1/N267 + CLMA_90_13/A4 r u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_L5Q_perm/L4 + + Data arrival time 9.835 Logic Levels: 3 + Logic: 2.501ns(71.457%), Route: 0.999ns(28.543%) ---------------------------------------------------------------------------------------------------- Clock clk_20k (rising edge) 50000.000 50000.000 r @@ -11460,37 +12714,37 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi net (fanout=1) 0.463 50001.860 _N69 PLL_158_55/CLK_OUT3 td 0.083 50001.943 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 net (fanout=1) 0.603 50002.546 clk_25m - USCM_84_114/CLK_USCM td 0.000 50002.546 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 0.895 50003.441 ntclkbufg_7 - CLMA_182_12/Q1 tco 0.184 50003.625 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q - net (fanout=3) 1.264 50004.889 u_ov5640/coms1_reg_config/clk_20k_regdiv - USCM_84_119/CLK_USCM td 0.000 50004.889 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - net (fanout=19) 0.895 50005.784 u_ov5640/coms1_reg_config/clock_20k - CLMA_174_16/CLK r u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/CLK - clock pessimism 0.471 50006.255 - clock uncertainty -0.050 50006.205 + USCM_84_114/CLK_USCM td 0.000 50002.546 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 0.895 50003.441 ntclkbufg_8 + CLMA_122_12/Q1 tco 0.184 50003.625 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q + net (fanout=3) 1.276 50004.901 u_ov5640/coms2_reg_config/clk_20k_regdiv + USCM_84_121/CLK_USCM td 0.000 50004.901 r u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + net (fanout=19) 0.895 50005.796 u_ov5640/coms2_reg_config/clock_20k + CLMA_90_13/CLK r u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_L5Q_perm/CLK + clock pessimism 0.473 50006.269 + clock uncertainty -0.050 50006.219 - Setup time -0.127 50006.078 + Setup time -0.093 50006.126 - Data required time 50006.078 + Data required time 50006.126 ---------------------------------------------------------------------------------------------------- - Data required time 50006.078 - Data arrival time 9.615 + Data required time 50006.126 + Data arrival time 9.835 ---------------------------------------------------------------------------------------------------- - Slack (MET) 49996.463 + Slack (MET) 49996.291 ==================================================================================================== ==================================================================================================== -Startpoint : u_ov5640/coms2_reg_config/reg_data/iGopDrm/CLKB[0] -Endpoint : u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I3 +Startpoint : u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0] +Endpoint : u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I3 Path Group : clk_20k Path Type : max (fast corner) Path Class : sequential timing path Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.644 - Launch Clock Delay : 6.109 - Clock Pessimism Removal : 0.446 + Capture Clock Delay : 5.862 + Launch Clock Delay : 6.370 + Clock Pessimism Removal : 0.489 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -11504,22 +12758,22 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi net (fanout=1) 0.478 2.114 _N69 PLL_158_55/CLK_OUT3 td 0.088 2.202 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 net (fanout=1) 0.614 2.816 clk_25m - USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 0.925 3.741 ntclkbufg_7 - CLMA_182_25/Q1 tco 0.224 3.965 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q - net (fanout=3) 1.219 5.184 u_ov5640/coms2_reg_config/clk_20k_regdiv - USCM_84_120/CLK_USCM td 0.000 5.184 r u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - net (fanout=19) 0.925 6.109 u_ov5640/coms2_reg_config/clock_20k - DRM_178_24/CLKB[0] r u_ov5640/coms2_reg_config/reg_data/iGopDrm/CLKB[0] + USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 0.925 3.741 ntclkbufg_8 + CLMS_122_9/Q1 tco 0.224 3.965 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q + net (fanout=3) 1.480 5.445 u_ov5640/coms1_reg_config/clk_20k_regdiv + USCM_84_120/CLK_USCM td 0.000 5.445 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + net (fanout=19) 0.925 6.370 u_ov5640/coms1_reg_config/clock_20k + DRM_142_4/CLKB[0] r u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0] - DRM_178_24/QB0[1] tco 1.780 7.889 f u_ov5640/coms2_reg_config/reg_data/iGopDrm/QB0[1] - net (fanout=1) 0.514 8.403 u_ov5640/coms2_reg_config/i2c_data [17] - CLMA_182_33/Y1 td 0.469 8.872 f u_ov5640/coms2_reg_config/u1/N267_18_muxf7/F - net (fanout=1) 0.469 9.341 u_ov5640/coms2_reg_config/u1/_N25893 - CLMS_174_25/D0 f u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I3 + DRM_142_4/QA0[9] tco 1.815 8.185 f u_ov5640/coms1_reg_config/reg_data/iGopDrm/QA0[9] + net (fanout=1) 0.410 8.595 u_ov5640/coms1_reg_config/i2c_data [8] + CLMA_146_8/Y1 td 0.469 9.064 f u_ov5640/coms1_reg_config/u1/N267_18_muxf7/F + net (fanout=1) 0.378 9.442 u_ov5640/coms1_reg_config/u1/_N25300 + CLMA_138_9/A0 f u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I3 - Data arrival time 9.341 Logic Levels: 1 - Logic: 2.249ns(69.585%), Route: 0.983ns(30.415%) + Data arrival time 9.442 Logic Levels: 1 + Logic: 2.284ns(74.349%), Route: 0.788ns(25.651%) ---------------------------------------------------------------------------------------------------- Clock clk_20k (rising edge) 50000.000 50000.000 r @@ -11531,37 +12785,37 @@ Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessi net (fanout=1) 0.463 50001.860 _N69 PLL_158_55/CLK_OUT3 td 0.083 50001.943 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 net (fanout=1) 0.603 50002.546 clk_25m - USCM_84_114/CLK_USCM td 0.000 50002.546 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 0.895 50003.441 ntclkbufg_7 - CLMA_182_25/Q1 tco 0.184 50003.625 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q - net (fanout=3) 1.124 50004.749 u_ov5640/coms2_reg_config/clk_20k_regdiv - USCM_84_120/CLK_USCM td 0.000 50004.749 r u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - net (fanout=19) 0.895 50005.644 u_ov5640/coms2_reg_config/clock_20k - CLMS_174_25/CLK r u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/CLK - clock pessimism 0.446 50006.090 - clock uncertainty -0.050 50006.040 + USCM_84_114/CLK_USCM td 0.000 50002.546 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 0.895 50003.441 ntclkbufg_8 + CLMS_122_9/Q1 tco 0.184 50003.625 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q + net (fanout=3) 1.342 50004.967 u_ov5640/coms1_reg_config/clk_20k_regdiv + USCM_84_120/CLK_USCM td 0.000 50004.967 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + net (fanout=19) 0.895 50005.862 u_ov5640/coms1_reg_config/clock_20k + CLMA_138_9/CLK r u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/CLK + clock pessimism 0.489 50006.351 + clock uncertainty -0.050 50006.301 - Setup time -0.148 50005.892 + Setup time -0.154 50006.147 - Data required time 50005.892 + Data required time 50006.147 ---------------------------------------------------------------------------------------------------- - Data required time 50005.892 - Data arrival time 9.341 + Data required time 50006.147 + Data arrival time 9.442 ---------------------------------------------------------------------------------------------------- - Slack (MET) 49996.551 + Slack (MET) 49996.705 ==================================================================================================== ==================================================================================================== -Startpoint : u_ov5640/coms2_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK -Endpoint : u_ov5640/coms2_reg_config/reg_data/iGopDrm/ADA0[5] +Startpoint : u_ov5640/coms1_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK +Endpoint : u_ov5640/coms1_reg_config/reg_data/iGopDrm/ADA0[5] Path Group : clk_20k Path Type : min (fast corner) Path Class : sequential timing path Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 6.109 - Launch Clock Delay : 5.644 - Clock Pessimism Removal : -0.446 + Capture Clock Delay : 6.370 + Launch Clock Delay : 5.862 + Clock Pessimism Removal : -0.489 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -11575,20 +12829,20 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.463 1.860 _N69 PLL_158_55/CLK_OUT3 td 0.083 1.943 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 net (fanout=1) 0.603 2.546 clk_25m - USCM_84_114/CLK_USCM td 0.000 2.546 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 0.895 3.441 ntclkbufg_7 - CLMA_182_25/Q1 tco 0.184 3.625 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q - net (fanout=3) 1.124 4.749 u_ov5640/coms2_reg_config/clk_20k_regdiv - USCM_84_120/CLK_USCM td 0.000 4.749 r u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - net (fanout=19) 0.895 5.644 u_ov5640/coms2_reg_config/clock_20k - CLMA_182_32/CLK r u_ov5640/coms2_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK + USCM_84_114/CLK_USCM td 0.000 2.546 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 0.895 3.441 ntclkbufg_8 + CLMS_122_9/Q1 tco 0.184 3.625 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q + net (fanout=3) 1.342 4.967 u_ov5640/coms1_reg_config/clk_20k_regdiv + USCM_84_120/CLK_USCM td 0.000 4.967 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + net (fanout=19) 0.895 5.862 u_ov5640/coms1_reg_config/clock_20k + CLMA_146_12/CLK r u_ov5640/coms1_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK - CLMA_182_32/Q0 tco 0.182 5.826 r u_ov5640/coms2_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/Q - net (fanout=6) 0.233 6.059 u_ov5640/coms2_reg_config/reg_index [0] - DRM_178_24/ADA0[5] r u_ov5640/coms2_reg_config/reg_data/iGopDrm/ADA0[5] + CLMA_146_12/Q0 tco 0.182 6.044 r u_ov5640/coms1_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/Q + net (fanout=6) 0.237 6.281 u_ov5640/coms1_reg_config/reg_index [0] + DRM_142_4/ADA0[5] r u_ov5640/coms1_reg_config/reg_data/iGopDrm/ADA0[5] - Data arrival time 6.059 Logic Levels: 0 - Logic: 0.182ns(43.855%), Route: 0.233ns(56.145%) + Data arrival time 6.281 Logic Levels: 0 + Logic: 0.182ns(43.437%), Route: 0.237ns(56.563%) ---------------------------------------------------------------------------------------------------- Clock clk_20k (rising edge) 0.000 0.000 r @@ -11600,37 +12854,37 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.478 2.114 _N69 PLL_158_55/CLK_OUT3 td 0.088 2.202 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 net (fanout=1) 0.614 2.816 clk_25m - USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 0.925 3.741 ntclkbufg_7 - CLMA_182_25/Q1 tco 0.224 3.965 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q - net (fanout=3) 1.219 5.184 u_ov5640/coms2_reg_config/clk_20k_regdiv - USCM_84_120/CLK_USCM td 0.000 5.184 r u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - net (fanout=19) 0.925 6.109 u_ov5640/coms2_reg_config/clock_20k - DRM_178_24/CLKA[0] r u_ov5640/coms2_reg_config/reg_data/iGopDrm/CLKA[0] - clock pessimism -0.446 5.663 - clock uncertainty 0.000 5.663 + USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 0.925 3.741 ntclkbufg_8 + CLMS_122_9/Q1 tco 0.224 3.965 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q + net (fanout=3) 1.480 5.445 u_ov5640/coms1_reg_config/clk_20k_regdiv + USCM_84_120/CLK_USCM td 0.000 5.445 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + net (fanout=19) 0.925 6.370 u_ov5640/coms1_reg_config/clock_20k + DRM_142_4/CLKA[0] r u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKA[0] + clock pessimism -0.489 5.881 + clock uncertainty 0.000 5.881 - Hold time 0.127 5.790 + Hold time 0.127 6.008 - Data required time 5.790 + Data required time 6.008 ---------------------------------------------------------------------------------------------------- - Data required time 5.790 - Data arrival time 6.059 + Data required time 6.008 + Data arrival time 6.281 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.269 + Slack (MET) 0.273 ==================================================================================================== ==================================================================================================== -Startpoint : u_ov5640/coms1_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK -Endpoint : u_ov5640/coms1_reg_config/reg_data/iGopDrm/ADA0[5] +Startpoint : u_ov5640/coms2_reg_config/reg_index[4]/opit_0_inv_A2Q21/CLK +Endpoint : u_ov5640/coms2_reg_config/reg_data/iGopDrm/ADB0[8] Path Group : clk_20k Path Type : min (fast corner) Path Class : sequential timing path -Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 6.274 - Launch Clock Delay : 5.784 - Clock Pessimism Removal : -0.471 +Clock Skew : 0.036 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 6.335 + Launch Clock Delay : 5.826 + Clock Pessimism Removal : -0.473 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -11644,20 +12898,20 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.463 1.860 _N69 PLL_158_55/CLK_OUT3 td 0.083 1.943 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 net (fanout=1) 0.603 2.546 clk_25m - USCM_84_114/CLK_USCM td 0.000 2.546 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 0.895 3.441 ntclkbufg_7 - CLMA_182_12/Q1 tco 0.184 3.625 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q - net (fanout=3) 1.264 4.889 u_ov5640/coms1_reg_config/clk_20k_regdiv - USCM_84_119/CLK_USCM td 0.000 4.889 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - net (fanout=19) 0.895 5.784 u_ov5640/coms1_reg_config/clock_20k - CLMA_182_13/CLK r u_ov5640/coms1_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK + USCM_84_114/CLK_USCM td 0.000 2.546 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 0.895 3.441 ntclkbufg_8 + CLMA_122_12/Q1 tco 0.184 3.625 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q + net (fanout=3) 1.276 4.901 u_ov5640/coms2_reg_config/clk_20k_regdiv + USCM_84_121/CLK_USCM td 0.000 4.901 r u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + net (fanout=19) 0.925 5.826 u_ov5640/coms2_reg_config/clock_20k + CLMS_78_13/CLK r u_ov5640/coms2_reg_config/reg_index[4]/opit_0_inv_A2Q21/CLK - CLMA_182_13/Q0 tco 0.182 5.966 r u_ov5640/coms1_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/Q - net (fanout=6) 0.235 6.201 u_ov5640/coms1_reg_config/reg_index [0] - DRM_178_4/ADA0[5] r u_ov5640/coms1_reg_config/reg_data/iGopDrm/ADA0[5] + CLMS_78_13/Q2 tco 0.183 6.009 r u_ov5640/coms2_reg_config/reg_index[4]/opit_0_inv_A2Q21/Q0 + net (fanout=4) 0.199 6.208 u_ov5640/coms2_reg_config/reg_index [3] + DRM_82_4/ADB0[8] r u_ov5640/coms2_reg_config/reg_data/iGopDrm/ADB0[8] - Data arrival time 6.201 Logic Levels: 0 - Logic: 0.182ns(43.645%), Route: 0.235ns(56.355%) + Data arrival time 6.208 Logic Levels: 0 + Logic: 0.183ns(47.906%), Route: 0.199ns(52.094%) ---------------------------------------------------------------------------------------------------- Clock clk_20k (rising edge) 0.000 0.000 r @@ -11669,37 +12923,37 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.478 2.114 _N69 PLL_158_55/CLK_OUT3 td 0.088 2.202 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 net (fanout=1) 0.614 2.816 clk_25m - USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 0.925 3.741 ntclkbufg_7 - CLMA_182_12/Q1 tco 0.224 3.965 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q - net (fanout=3) 1.384 5.349 u_ov5640/coms1_reg_config/clk_20k_regdiv - USCM_84_119/CLK_USCM td 0.000 5.349 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - net (fanout=19) 0.925 6.274 u_ov5640/coms1_reg_config/clock_20k - DRM_178_4/CLKA[0] r u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKA[0] - clock pessimism -0.471 5.803 - clock uncertainty 0.000 5.803 + USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 0.925 3.741 ntclkbufg_8 + CLMA_122_12/Q1 tco 0.224 3.965 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q + net (fanout=3) 1.398 5.363 u_ov5640/coms2_reg_config/clk_20k_regdiv + USCM_84_121/CLK_USCM td 0.000 5.363 r u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + net (fanout=19) 0.972 6.335 u_ov5640/coms2_reg_config/clock_20k + DRM_82_4/CLKB[0] r u_ov5640/coms2_reg_config/reg_data/iGopDrm/CLKB[0] + clock pessimism -0.473 5.862 + clock uncertainty 0.000 5.862 - Hold time 0.127 5.930 + Hold time 0.061 5.923 - Data required time 5.930 + Data required time 5.923 ---------------------------------------------------------------------------------------------------- - Data required time 5.930 - Data arrival time 6.201 + Data required time 5.923 + Data arrival time 6.208 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.271 + Slack (MET) 0.285 ==================================================================================================== ==================================================================================================== -Startpoint : u_ov5640/coms1_reg_config/reg_index[4]/opit_0_inv_A2Q21/CLK -Endpoint : u_ov5640/coms1_reg_config/reg_data/iGopDrm/ADB0[8] +Startpoint : u_ov5640/coms2_reg_config/reg_index[8]/opit_0_inv_A2Q21/CLK +Endpoint : u_ov5640/coms2_reg_config/reg_data/iGopDrm/ADA_CAS Path Group : clk_20k Path Type : min (fast corner) Path Class : sequential timing path -Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 6.274 - Launch Clock Delay : 5.784 - Clock Pessimism Removal : -0.471 +Clock Skew : 0.028 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 6.331 + Launch Clock Delay : 5.830 + Clock Pessimism Removal : -0.473 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -11713,20 +12967,20 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.463 1.860 _N69 PLL_158_55/CLK_OUT3 td 0.083 1.943 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 net (fanout=1) 0.603 2.546 clk_25m - USCM_84_114/CLK_USCM td 0.000 2.546 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 0.895 3.441 ntclkbufg_7 - CLMA_182_12/Q1 tco 0.184 3.625 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q - net (fanout=3) 1.264 4.889 u_ov5640/coms1_reg_config/clk_20k_regdiv - USCM_84_119/CLK_USCM td 0.000 4.889 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - net (fanout=19) 0.895 5.784 u_ov5640/coms1_reg_config/clock_20k - CLMS_174_13/CLK r u_ov5640/coms1_reg_config/reg_index[4]/opit_0_inv_A2Q21/CLK + USCM_84_114/CLK_USCM td 0.000 2.546 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 0.895 3.441 ntclkbufg_8 + CLMA_122_12/Q1 tco 0.184 3.625 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q + net (fanout=3) 1.276 4.901 u_ov5640/coms2_reg_config/clk_20k_regdiv + USCM_84_121/CLK_USCM td 0.000 4.901 r u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + net (fanout=19) 0.929 5.830 u_ov5640/coms2_reg_config/clock_20k + CLMS_78_17/CLK r u_ov5640/coms2_reg_config/reg_index[8]/opit_0_inv_A2Q21/CLK - CLMS_174_13/Q2 tco 0.183 5.967 r u_ov5640/coms1_reg_config/reg_index[4]/opit_0_inv_A2Q21/Q0 - net (fanout=4) 0.197 6.164 u_ov5640/coms1_reg_config/reg_index [3] - DRM_178_4/ADB0[8] r u_ov5640/coms1_reg_config/reg_data/iGopDrm/ADB0[8] + CLMS_78_17/Q3 tco 0.182 6.012 r u_ov5640/coms2_reg_config/reg_index[8]/opit_0_inv_A2Q21/Q1 + net (fanout=5) 0.204 6.216 u_ov5640/coms2_reg_config/reg_index [8] + DRM_82_4/ADA_CAS r u_ov5640/coms2_reg_config/reg_data/iGopDrm/ADA_CAS - Data arrival time 6.164 Logic Levels: 0 - Logic: 0.183ns(48.158%), Route: 0.197ns(51.842%) + Data arrival time 6.216 Logic Levels: 0 + Logic: 0.182ns(47.150%), Route: 0.204ns(52.850%) ---------------------------------------------------------------------------------------------------- Clock clk_20k (rising edge) 0.000 0.000 r @@ -11738,37 +12992,37 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.478 2.114 _N69 PLL_158_55/CLK_OUT3 td 0.088 2.202 r u_sys_pll/u_pll_e3/goppll/CLKOUT3 net (fanout=1) 0.614 2.816 clk_25m - USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_7/gopclkbufg/CLKOUT - net (fanout=26) 0.925 3.741 ntclkbufg_7 - CLMA_182_12/Q1 tco 0.224 3.965 r u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q - net (fanout=3) 1.384 5.349 u_ov5640/coms1_reg_config/clk_20k_regdiv - USCM_84_119/CLK_USCM td 0.000 5.349 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - net (fanout=19) 0.925 6.274 u_ov5640/coms1_reg_config/clock_20k - DRM_178_4/CLKB[0] r u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0] - clock pessimism -0.471 5.803 - clock uncertainty 0.000 5.803 + USCM_84_114/CLK_USCM td 0.000 2.816 r clkbufg_8/gopclkbufg/CLKOUT + net (fanout=26) 0.925 3.741 ntclkbufg_8 + CLMA_122_12/Q1 tco 0.224 3.965 r u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q + net (fanout=3) 1.398 5.363 u_ov5640/coms2_reg_config/clk_20k_regdiv + USCM_84_121/CLK_USCM td 0.000 5.363 r u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + net (fanout=19) 0.968 6.331 u_ov5640/coms2_reg_config/clock_20k + DRM_82_4/CLKA[0] r u_ov5640/coms2_reg_config/reg_data/iGopDrm/CLKA[0] + clock pessimism -0.473 5.858 + clock uncertainty 0.000 5.858 - Hold time 0.061 5.864 + Hold time 0.069 5.927 - Data required time 5.864 + Data required time 5.927 ---------------------------------------------------------------------------------------------------- - Data required time 5.864 - Data arrival time 6.164 + Data required time 5.927 + Data arrival time 6.216 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.300 + Slack (MET) 0.289 ==================================================================================================== ==================================================================================================== Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK -Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/S0 +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/S0 Path Group : ddrphy_clkin Path Type : max (fast corner) Path Class : sequential timing path -Clock Skew : -0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) +Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) Capture Clock Delay : 6.654 Launch Clock Delay : 7.101 - Clock Pessimism Removal : 0.417 + Clock Pessimism Removal : 0.428 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -11781,41 +13035,41 @@ Clock Skew : -0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessi IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.614 2.807 zoom_clk + net (fanout=2) 0.614 2.807 ddr_clk USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.682 4.602 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 4.870 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 1.306 6.176 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 6.176 r clkbufg_0/gopclkbufg/CLKOUT net (fanout=5464) 0.925 7.101 ntclkbufg_0 - CLMA_22_124/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK - - CLMA_22_124/Q3 tco 0.220 7.321 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/Q - net (fanout=5) 0.657 7.978 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mr0_ddr3 [2] - CLMA_30_168/Y3 td 0.358 8.336 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/gateop_perm/Z - net (fanout=2) 0.260 8.596 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_cl [1] - td 0.368 8.964 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_1/gateop_A2/Cout - net (fanout=1) 0.000 8.964 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.co [2] - CLMA_34_168/Y2 td 0.202 9.166 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_3/gateop_A2/Y0 - net (fanout=1) 0.360 9.526 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [2] - CLMA_30_160/Y3 td 0.151 9.677 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[2]/gateop_perm/Z - net (fanout=4) 0.451 10.128 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al [2] - CLMA_30_172/COUT td 0.387 10.515 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_3/gateop_A2/Cout - net (fanout=1) 0.000 10.515 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14576 - CLMA_30_176/Y0 td 0.206 10.721 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_5/gateop/Y - net (fanout=4) 0.996 11.717 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mc_rl [4] - CLMA_30_248/Y0 td 0.380 12.097 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_159_5/gateop_perm/Z - net (fanout=40) 0.617 12.714 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24196 - CLMS_38_245/Y1 td 0.360 13.074 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_170[2]/gateop/F - net (fanout=1) 0.315 13.389 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24359 - CLMS_22_245/D3 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/S0 - - Data arrival time 13.389 Logic Levels: 7 - Logic: 2.632ns(41.858%), Route: 3.656ns(58.142%) + CLMS_10_133/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK + + CLMS_10_133/Q2 tco 0.224 7.325 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/Q + net (fanout=5) 0.420 7.745 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mr0_ddr3 [2] + CLMS_18_149/Y1 td 0.224 7.969 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/gateop_perm/Z + net (fanout=2) 0.257 8.226 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_cl [1] + td 0.368 8.594 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_1/gateop_A2/Cout + net (fanout=1) 0.000 8.594 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.co [2] + CLMS_18_145/Y3 td 0.365 8.959 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_3/gateop_A2/Y1 + net (fanout=1) 0.432 9.391 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [3] + CLMS_46_145/Y1 td 0.244 9.635 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[3]/gateop_perm/Z + net (fanout=4) 0.261 9.896 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al [3] + CLMA_50_144/COUT td 0.391 10.287 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_3/gateop_A2/Cout + net (fanout=1) 0.000 10.287 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14534 + CLMA_50_148/Y0 td 0.206 10.493 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_5/gateop/Y + net (fanout=4) 0.169 10.662 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mc_rl [4] + CLMS_46_149/Y0 td 0.226 10.888 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_159_5/gateop_perm/Z + net (fanout=40) 0.458 11.346 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23975 + CLMA_62_164/Y2 td 0.379 11.725 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_170[12]/gateop/F + net (fanout=1) 0.254 11.979 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24148 + CLMA_58_161/C3 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/S0 + + Data arrival time 11.979 Logic Levels: 7 + Logic: 2.627ns(53.854%), Route: 2.251ns(46.146%) ---------------------------------------------------------------------------------------------------- Clock ddrphy_clkin (rising edge) 10.000 10.000 r @@ -11826,42 +13080,42 @@ Clock Skew : -0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessi IOL_327_210/INCK td 0.038 11.397 r clk_ibuf/opit_1/INCK net (fanout=1) 0.463 11.860 _N69 PLL_158_55/CLK_OUT1 td 0.074 11.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.603 12.537 zoom_clk + net (fanout=2) 0.603 12.537 ddr_clk USCM_84_113/CLK_USCM td 0.000 12.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 0.981 13.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 0.981 13.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.089 13.607 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.669 14.276 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.200 14.476 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.200 14.476 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 14.476 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 14.476 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 1.283 15.759 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 15.759 r clkbufg_0/gopclkbufg/CLKOUT net (fanout=5464) 0.895 16.654 ntclkbufg_0 - CLMS_22_245/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/CLK - clock pessimism 0.417 17.071 - clock uncertainty -0.150 16.921 + CLMA_58_161/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/CLK + clock pessimism 0.428 17.082 + clock uncertainty -0.150 16.932 - Setup time -0.287 16.634 + Setup time -0.308 16.624 - Data required time 16.634 + Data required time 16.624 ---------------------------------------------------------------------------------------------------- - Data required time 16.634 - Data arrival time 13.389 + Data required time 16.624 + Data arrival time 11.979 ---------------------------------------------------------------------------------------------------- - Slack (MET) 3.245 + Slack (MET) 4.645 ==================================================================================================== ==================================================================================================== Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK -Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/S0 +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/S0 Path Group : ddrphy_clkin Path Type : max (fast corner) Path Class : sequential timing path -Clock Skew : -0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) +Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) Capture Clock Delay : 6.654 Launch Clock Delay : 7.101 - Clock Pessimism Removal : 0.417 + Clock Pessimism Removal : 0.428 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -11874,41 +13128,41 @@ Clock Skew : -0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessi IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.614 2.807 zoom_clk + net (fanout=2) 0.614 2.807 ddr_clk USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.682 4.602 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 4.870 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 1.306 6.176 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 6.176 r clkbufg_0/gopclkbufg/CLKOUT net (fanout=5464) 0.925 7.101 ntclkbufg_0 - CLMA_22_124/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK - - CLMA_22_124/Q3 tco 0.220 7.321 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/Q - net (fanout=5) 0.657 7.978 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mr0_ddr3 [2] - CLMA_30_168/Y3 td 0.358 8.336 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/gateop_perm/Z - net (fanout=2) 0.260 8.596 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_cl [1] - td 0.368 8.964 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_1/gateop_A2/Cout - net (fanout=1) 0.000 8.964 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.co [2] - CLMA_34_168/Y2 td 0.202 9.166 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_3/gateop_A2/Y0 - net (fanout=1) 0.360 9.526 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [2] - CLMA_30_160/Y3 td 0.151 9.677 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[2]/gateop_perm/Z - net (fanout=4) 0.451 10.128 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al [2] - CLMA_30_172/COUT td 0.387 10.515 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_3/gateop_A2/Cout - net (fanout=1) 0.000 10.515 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14576 - CLMA_30_176/Y0 td 0.206 10.721 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_5/gateop/Y - net (fanout=4) 0.996 11.717 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mc_rl [4] - CLMA_30_248/Y0 td 0.380 12.097 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_159_5/gateop_perm/Z - net (fanout=40) 0.491 12.588 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24196 - CLMA_30_248/Y1 td 0.360 12.948 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_170[0]/gateop/F - net (fanout=1) 0.398 13.346 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24357 - CLMS_22_245/A3 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/S0 - - Data arrival time 13.346 Logic Levels: 7 - Logic: 2.632ns(42.146%), Route: 3.613ns(57.854%) + CLMS_10_133/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK + + CLMS_10_133/Q2 tco 0.224 7.325 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/Q + net (fanout=5) 0.420 7.745 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mr0_ddr3 [2] + CLMS_18_149/Y1 td 0.224 7.969 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/gateop_perm/Z + net (fanout=2) 0.257 8.226 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_cl [1] + td 0.368 8.594 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_1/gateop_A2/Cout + net (fanout=1) 0.000 8.594 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.co [2] + CLMS_18_145/Y3 td 0.365 8.959 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_3/gateop_A2/Y1 + net (fanout=1) 0.432 9.391 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [3] + CLMS_46_145/Y1 td 0.244 9.635 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[3]/gateop_perm/Z + net (fanout=4) 0.261 9.896 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al [3] + CLMA_50_144/COUT td 0.391 10.287 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_3/gateop_A2/Cout + net (fanout=1) 0.000 10.287 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14534 + CLMA_50_148/Y0 td 0.206 10.493 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_5/gateop/Y + net (fanout=4) 0.169 10.662 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mc_rl [4] + CLMS_46_149/Y0 td 0.226 10.888 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_159_5/gateop_perm/Z + net (fanout=40) 0.519 11.407 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23975 + CLMA_66_156/Y2 td 0.381 11.788 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_170[10]/gateop/F + net (fanout=1) 0.173 11.961 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24146 + CLMA_66_152/B3 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/S0 + + Data arrival time 11.961 Logic Levels: 7 + Logic: 2.629ns(54.095%), Route: 2.231ns(45.905%) ---------------------------------------------------------------------------------------------------- Clock ddrphy_clkin (rising edge) 10.000 10.000 r @@ -11919,42 +13173,42 @@ Clock Skew : -0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessi IOL_327_210/INCK td 0.038 11.397 r clk_ibuf/opit_1/INCK net (fanout=1) 0.463 11.860 _N69 PLL_158_55/CLK_OUT1 td 0.074 11.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.603 12.537 zoom_clk + net (fanout=2) 0.603 12.537 ddr_clk USCM_84_113/CLK_USCM td 0.000 12.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 0.981 13.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 0.981 13.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.089 13.607 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.669 14.276 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.200 14.476 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.200 14.476 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 14.476 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 14.476 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 1.283 15.759 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 15.759 r clkbufg_0/gopclkbufg/CLKOUT net (fanout=5464) 0.895 16.654 ntclkbufg_0 - CLMS_22_245/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/CLK - clock pessimism 0.417 17.071 - clock uncertainty -0.150 16.921 + CLMA_66_152/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/CLK + clock pessimism 0.428 17.082 + clock uncertainty -0.150 16.932 - Setup time -0.308 16.613 + Setup time -0.287 16.645 - Data required time 16.613 + Data required time 16.645 ---------------------------------------------------------------------------------------------------- - Data required time 16.613 - Data arrival time 13.346 + Data required time 16.645 + Data arrival time 11.961 ---------------------------------------------------------------------------------------------------- - Slack (MET) 3.267 + Slack (MET) 4.684 ==================================================================================================== ==================================================================================================== Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK -Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/S0 +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/S0 Path Group : ddrphy_clkin Path Type : max (fast corner) Path Class : sequential timing path -Clock Skew : 0.080 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 6.764 +Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 6.654 Launch Clock Delay : 7.101 - Clock Pessimism Removal : 0.417 + Clock Pessimism Removal : 0.428 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -11967,41 +13221,41 @@ Clock Skew : 0.080 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.614 2.807 zoom_clk + net (fanout=2) 0.614 2.807 ddr_clk USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.682 4.602 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 4.870 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 1.306 6.176 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 6.176 r clkbufg_0/gopclkbufg/CLKOUT net (fanout=5464) 0.925 7.101 ntclkbufg_0 - CLMA_22_124/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK - - CLMA_22_124/Q3 tco 0.220 7.321 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/Q - net (fanout=5) 0.657 7.978 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mr0_ddr3 [2] - CLMA_30_168/Y3 td 0.358 8.336 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/gateop_perm/Z - net (fanout=2) 0.260 8.596 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_cl [1] - td 0.368 8.964 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_1/gateop_A2/Cout - net (fanout=1) 0.000 8.964 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.co [2] - CLMA_34_168/Y2 td 0.202 9.166 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_3/gateop_A2/Y0 - net (fanout=1) 0.360 9.526 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [2] - CLMA_30_160/Y3 td 0.151 9.677 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[2]/gateop_perm/Z - net (fanout=4) 0.451 10.128 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al [2] - CLMA_30_172/COUT td 0.387 10.515 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_3/gateop_A2/Cout - net (fanout=1) 0.000 10.515 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14576 - CLMA_30_176/Y0 td 0.206 10.721 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_5/gateop/Y - net (fanout=4) 0.996 11.717 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mc_rl [4] - CLMA_30_248/Y0 td 0.380 12.097 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_159_5/gateop_perm/Z - net (fanout=40) 0.510 12.607 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24196 - CLMA_34_268/Y3 td 0.360 12.967 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_170[10]/gateop/F - net (fanout=1) 0.484 13.451 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24367 - CLMS_22_265/B3 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/S0 - - Data arrival time 13.451 Logic Levels: 7 - Logic: 2.632ns(41.449%), Route: 3.718ns(58.551%) + CLMS_10_133/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK + + CLMS_10_133/Q2 tco 0.224 7.325 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/Q + net (fanout=5) 0.420 7.745 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mr0_ddr3 [2] + CLMS_18_149/Y1 td 0.224 7.969 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/gateop_perm/Z + net (fanout=2) 0.257 8.226 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_cl [1] + td 0.368 8.594 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_1/gateop_A2/Cout + net (fanout=1) 0.000 8.594 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.co [2] + CLMS_18_145/Y3 td 0.365 8.959 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_3/gateop_A2/Y1 + net (fanout=1) 0.432 9.391 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [3] + CLMS_46_145/Y1 td 0.244 9.635 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[3]/gateop_perm/Z + net (fanout=4) 0.261 9.896 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al [3] + CLMA_50_144/COUT td 0.391 10.287 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_3/gateop_A2/Cout + net (fanout=1) 0.000 10.287 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14534 + CLMA_50_148/Y0 td 0.206 10.493 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_5/gateop/Y + net (fanout=4) 0.169 10.662 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mc_rl [4] + CLMS_46_149/Y0 td 0.226 10.888 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_159_5/gateop_perm/Z + net (fanout=40) 0.539 11.427 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23975 + CLMA_62_160/Y1 td 0.244 11.671 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_170[14]/gateop/F + net (fanout=1) 0.259 11.930 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24150 + CLMA_58_161/A3 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/S0 + + Data arrival time 11.930 Logic Levels: 7 + Logic: 2.492ns(51.605%), Route: 2.337ns(48.395%) ---------------------------------------------------------------------------------------------------- Clock ddrphy_clkin (rising edge) 10.000 10.000 r @@ -12012,42 +13266,42 @@ Clock Skew : 0.080 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.038 11.397 r clk_ibuf/opit_1/INCK net (fanout=1) 0.463 11.860 _N69 PLL_158_55/CLK_OUT1 td 0.074 11.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.603 12.537 zoom_clk + net (fanout=2) 0.603 12.537 ddr_clk USCM_84_113/CLK_USCM td 0.000 12.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 0.981 13.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 0.981 13.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.089 13.607 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.669 14.276 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.200 14.476 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.200 14.476 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 14.476 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 14.476 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 1.283 15.759 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 15.759 r clkbufg_0/gopclkbufg/CLKOUT - net (fanout=5464) 1.005 16.764 ntclkbufg_0 - CLMS_22_265/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/CLK - clock pessimism 0.417 17.181 - clock uncertainty -0.150 17.031 + net (fanout=5464) 0.895 16.654 ntclkbufg_0 + CLMA_58_161/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/CLK + clock pessimism 0.428 17.082 + clock uncertainty -0.150 16.932 - Setup time -0.287 16.744 + Setup time -0.308 16.624 - Data required time 16.744 + Data required time 16.624 ---------------------------------------------------------------------------------------------------- - Data required time 16.744 - Data arrival time 13.451 + Data required time 16.624 + Data arrival time 11.930 ---------------------------------------------------------------------------------------------------- - Slack (MET) 3.293 + Slack (MET) 4.694 ==================================================================================================== ==================================================================================================== -Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[22]/opit_0_inv/CLK -Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_27/ram16x1d/WD +Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_15/ram16x1d/WADM0 Path Group : ddrphy_clkin Path Type : min (fast corner) Path Class : sequential timing path -Clock Skew : 0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 7.101 - Launch Clock Delay : 6.654 - Clock Pessimism Removal : -0.417 +Clock Skew : 0.039 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 7.144 + Launch Clock Delay : 6.677 + Clock Pessimism Removal : -0.428 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -12060,25 +13314,25 @@ Clock Skew : 0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK net (fanout=1) 0.463 1.860 _N69 PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.603 2.537 zoom_clk + net (fanout=2) 0.603 2.537 ddr_clk USCM_84_113/CLK_USCM td 0.000 2.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.089 3.607 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.669 4.276 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.200 4.476 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.200 4.476 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 4.476 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 4.476 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 1.283 5.759 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 5.759 r clkbufg_0/gopclkbufg/CLKOUT - net (fanout=5464) 0.895 6.654 ntclkbufg_0 - CLMA_58_124/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[22]/opit_0_inv/CLK + net (fanout=5464) 0.918 6.677 ntclkbufg_0 + CLMA_34_76/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK - CLMA_58_124/Q0 tco 0.179 6.833 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[22]/opit_0_inv/Q - net (fanout=2) 0.255 7.088 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/dcd_wr_addr [22] - CLMS_50_129/DD f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_27/ram16x1d/WD + CLMA_34_76/Q0 tco 0.179 6.856 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/Q0 + net (fanout=44) 0.268 7.124 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [0] + CLMS_42_81/M0 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_15/ram16x1d/WADM0 - Data arrival time 7.088 Logic Levels: 0 - Logic: 0.179ns(41.244%), Route: 0.255ns(58.756%) + Data arrival time 7.124 Logic Levels: 0 + Logic: 0.179ns(40.045%), Route: 0.268ns(59.955%) ---------------------------------------------------------------------------------------------------- Clock ddrphy_clkin (rising edge) 0.000 0.000 r @@ -12089,41 +13343,41 @@ Clock Skew : 0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.614 2.807 zoom_clk + net (fanout=2) 0.614 2.807 ddr_clk USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.682 4.602 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 4.870 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 1.306 6.176 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 6.176 r clkbufg_0/gopclkbufg/CLKOUT - net (fanout=5464) 0.925 7.101 ntclkbufg_0 - CLMS_50_129/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_27/ram16x1d/WCLK - clock pessimism -0.417 6.684 - clock uncertainty 0.000 6.684 + net (fanout=5464) 0.968 7.144 ntclkbufg_0 + CLMS_42_81/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_15/ram16x1d/WCLK + clock pessimism -0.428 6.716 + clock uncertainty 0.000 6.716 - Hold time 0.293 6.977 + Hold time 0.293 7.009 - Data required time 6.977 + Data required time 7.009 ---------------------------------------------------------------------------------------------------- - Data required time 6.977 - Data arrival time 7.088 + Data required time 7.009 + Data arrival time 7.124 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.111 + Slack (MET) 0.115 ==================================================================================================== ==================================================================================================== -Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK -Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_0/ram32x1dp/WADM0 +Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_16/ram16x1d/WADM0 Path Group : ddrphy_clkin Path Type : min (fast corner) Path Class : sequential timing path -Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 7.101 - Launch Clock Delay : 6.654 +Clock Skew : 0.039 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 7.144 + Launch Clock Delay : 6.677 Clock Pessimism Removal : -0.428 Location Delay Type Incr Path Logical Resource @@ -12137,25 +13391,25 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK net (fanout=1) 0.463 1.860 _N69 PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.603 2.537 zoom_clk + net (fanout=2) 0.603 2.537 ddr_clk USCM_84_113/CLK_USCM td 0.000 2.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.089 3.607 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.669 4.276 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.200 4.476 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.200 4.476 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 4.476 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 4.476 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 1.283 5.759 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 5.759 r clkbufg_0/gopclkbufg/CLKOUT - net (fanout=5464) 0.895 6.654 ntclkbufg_0 - CLMA_58_144/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK + net (fanout=5464) 0.918 6.677 ntclkbufg_0 + CLMA_34_76/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK - CLMA_58_144/Q0 tco 0.179 6.833 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/Q0 - net (fanout=7) 0.251 7.084 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [0] - CLMS_62_145/M0 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_0/ram32x1dp/WADM0 + CLMA_34_76/Q0 tco 0.179 6.856 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/Q0 + net (fanout=44) 0.268 7.124 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [0] + CLMS_42_81/M0 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_16/ram16x1d/WADM0 - Data arrival time 7.084 Logic Levels: 0 - Logic: 0.179ns(41.628%), Route: 0.251ns(58.372%) + Data arrival time 7.124 Logic Levels: 0 + Logic: 0.179ns(40.045%), Route: 0.268ns(59.955%) ---------------------------------------------------------------------------------------------------- Clock ddrphy_clkin (rising edge) 0.000 0.000 r @@ -12166,41 +13420,41 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.614 2.807 zoom_clk + net (fanout=2) 0.614 2.807 ddr_clk USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.682 4.602 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 4.870 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 1.306 6.176 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 6.176 r clkbufg_0/gopclkbufg/CLKOUT - net (fanout=5464) 0.925 7.101 ntclkbufg_0 - CLMS_62_145/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_0/ram32x1dp/WCLK - clock pessimism -0.428 6.673 - clock uncertainty 0.000 6.673 + net (fanout=5464) 0.968 7.144 ntclkbufg_0 + CLMS_42_81/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_16/ram16x1d/WCLK + clock pessimism -0.428 6.716 + clock uncertainty 0.000 6.716 - Hold time 0.293 6.966 + Hold time 0.293 7.009 - Data required time 6.966 + Data required time 7.009 ---------------------------------------------------------------------------------------------------- - Data required time 6.966 - Data arrival time 7.084 + Data required time 7.009 + Data arrival time 7.124 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.118 + Slack (MET) 0.115 ==================================================================================================== ==================================================================================================== -Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK -Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram32x1dp/WADM0 +Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_17/ram16x1d/WADM0 Path Group : ddrphy_clkin Path Type : min (fast corner) Path Class : sequential timing path -Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 7.101 - Launch Clock Delay : 6.654 +Clock Skew : 0.039 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 7.144 + Launch Clock Delay : 6.677 Clock Pessimism Removal : -0.428 Location Delay Type Incr Path Logical Resource @@ -12214,25 +13468,25 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK net (fanout=1) 0.463 1.860 _N69 PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.603 2.537 zoom_clk + net (fanout=2) 0.603 2.537 ddr_clk USCM_84_113/CLK_USCM td 0.000 2.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.089 3.607 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.669 4.276 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.200 4.476 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.200 4.476 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 4.476 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 4.476 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 1.283 5.759 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 5.759 r clkbufg_0/gopclkbufg/CLKOUT - net (fanout=5464) 0.895 6.654 ntclkbufg_0 - CLMA_58_144/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK + net (fanout=5464) 0.918 6.677 ntclkbufg_0 + CLMA_34_76/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK - CLMA_58_144/Q0 tco 0.179 6.833 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/Q0 - net (fanout=7) 0.251 7.084 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [0] - CLMS_62_145/M0 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram32x1dp/WADM0 + CLMA_34_76/Q0 tco 0.179 6.856 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/Q0 + net (fanout=44) 0.268 7.124 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [0] + CLMS_42_81/M0 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_17/ram16x1d/WADM0 - Data arrival time 7.084 Logic Levels: 0 - Logic: 0.179ns(41.628%), Route: 0.251ns(58.372%) + Data arrival time 7.124 Logic Levels: 0 + Logic: 0.179ns(40.045%), Route: 0.268ns(59.955%) ---------------------------------------------------------------------------------------------------- Clock ddrphy_clkin (rising edge) 0.000 0.000 r @@ -12243,29 +13497,29 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.614 2.807 zoom_clk + net (fanout=2) 0.614 2.807 ddr_clk USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.682 4.602 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 4.870 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 1.306 6.176 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 6.176 r clkbufg_0/gopclkbufg/CLKOUT - net (fanout=5464) 0.925 7.101 ntclkbufg_0 - CLMS_62_145/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram32x1dp/WCLK - clock pessimism -0.428 6.673 - clock uncertainty 0.000 6.673 + net (fanout=5464) 0.968 7.144 ntclkbufg_0 + CLMS_42_81/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_17/ram16x1d/WCLK + clock pessimism -0.428 6.716 + clock uncertainty 0.000 6.716 - Hold time 0.293 6.966 + Hold time 0.293 7.009 - Data required time 6.966 + Data required time 7.009 ---------------------------------------------------------------------------------------------------- - Data required time 6.966 - Data arrival time 7.084 + Data required time 7.009 + Data arrival time 7.124 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.118 + Slack (MET) 0.115 ==================================================================================================== ==================================================================================================== @@ -12291,9 +13545,9 @@ Clock Skew : -0.003 (Capture Clock Delay - Launch Clock Delay + Clock Pessi IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.614 2.807 zoom_clk + net (fanout=2) 0.614 2.807 ddr_clk USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.682 4.602 clkout0_wl_0 IOCKGATE_6_312/OUT td 0.268 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT @@ -12316,9 +13570,9 @@ Clock Skew : -0.003 (Capture Clock Delay - Launch Clock Delay + Clock Pessi IOL_327_210/INCK td 0.038 3.897 r clk_ibuf/opit_1/INCK net (fanout=1) 0.463 4.360 _N69 PLL_158_55/CLK_OUT1 td 0.074 4.434 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.603 5.037 zoom_clk + net (fanout=2) 0.603 5.037 ddr_clk USCM_84_113/CLK_USCM td 0.000 5.037 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 0.981 6.018 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 0.981 6.018 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.089 6.107 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.669 6.776 clkout0_wl_0 IOCKGATE_6_312/OUT td 0.200 6.976 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT @@ -12360,9 +13614,9 @@ Clock Skew : -0.003 (Capture Clock Delay - Launch Clock Delay + Clock Pessi IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.614 2.807 zoom_clk + net (fanout=2) 0.614 2.807 ddr_clk USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.682 4.602 clkout0_wl_0 IOCKGATE_6_312/OUT td 0.268 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT @@ -12385,9 +13639,9 @@ Clock Skew : -0.003 (Capture Clock Delay - Launch Clock Delay + Clock Pessi IOL_327_210/INCK td 0.038 3.897 r clk_ibuf/opit_1/INCK net (fanout=1) 0.463 4.360 _N69 PLL_158_55/CLK_OUT1 td 0.074 4.434 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.603 5.037 zoom_clk + net (fanout=2) 0.603 5.037 ddr_clk USCM_84_113/CLK_USCM td 0.000 5.037 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 0.981 6.018 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 0.981 6.018 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.089 6.107 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.669 6.776 clkout0_wl_0 IOCKGATE_6_312/OUT td 0.200 6.976 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT @@ -12429,9 +13683,9 @@ Clock Skew : -0.003 (Capture Clock Delay - Launch Clock Delay + Clock Pessi IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.614 2.807 zoom_clk + net (fanout=2) 0.614 2.807 ddr_clk USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.682 4.602 clkout0_wl_0 IOCKGATE_6_312/OUT td 0.268 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT @@ -12454,9 +13708,9 @@ Clock Skew : -0.003 (Capture Clock Delay - Launch Clock Delay + Clock Pessi IOL_327_210/INCK td 0.038 3.897 r clk_ibuf/opit_1/INCK net (fanout=1) 0.463 4.360 _N69 PLL_158_55/CLK_OUT1 td 0.074 4.434 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.603 5.037 zoom_clk + net (fanout=2) 0.603 5.037 ddr_clk USCM_84_113/CLK_USCM td 0.000 5.037 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 0.981 6.018 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 0.981 6.018 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.089 6.107 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.669 6.776 clkout0_wl_0 IOCKGATE_6_312/OUT td 0.200 6.976 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT @@ -12498,9 +13752,9 @@ Clock Skew : 0.009 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK net (fanout=1) 0.463 1.860 _N69 PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.603 2.537 zoom_clk + net (fanout=2) 0.603 2.537 ddr_clk USCM_84_113/CLK_USCM td 0.000 2.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.089 3.607 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.669 4.276 clkout0_wl_0 IOCKGATE_6_312/OUT td 0.200 4.476 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT @@ -12523,9 +13777,9 @@ Clock Skew : 0.009 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.614 2.807 zoom_clk + net (fanout=2) 0.614 2.807 ddr_clk USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.682 4.602 clkout0_wl_0 IOCKGATE_6_312/OUT td 0.268 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT @@ -12567,9 +13821,9 @@ Clock Skew : 0.009 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK net (fanout=1) 0.463 1.860 _N69 PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.603 2.537 zoom_clk + net (fanout=2) 0.603 2.537 ddr_clk USCM_84_113/CLK_USCM td 0.000 2.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.089 3.607 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.669 4.276 clkout0_wl_0 IOCKGATE_6_312/OUT td 0.200 4.476 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT @@ -12592,9 +13846,9 @@ Clock Skew : 0.009 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.614 2.807 zoom_clk + net (fanout=2) 0.614 2.807 ddr_clk USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.682 4.602 clkout0_wl_0 IOCKGATE_6_312/OUT td 0.268 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT @@ -12636,9 +13890,9 @@ Clock Skew : 0.009 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK net (fanout=1) 0.463 1.860 _N69 PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.603 2.537 zoom_clk + net (fanout=2) 0.603 2.537 ddr_clk USCM_84_113/CLK_USCM td 0.000 2.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.089 3.607 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.669 4.276 clkout0_wl_0 IOCKGATE_6_312/OUT td 0.200 4.476 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT @@ -12661,9 +13915,9 @@ Clock Skew : 0.009 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.614 2.807 zoom_clk + net (fanout=2) 0.614 2.807 ddr_clk USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.682 4.602 clkout0_wl_0 IOCKGATE_6_312/OUT td 0.268 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT @@ -12705,9 +13959,9 @@ Clock Skew : -0.003 (Capture Clock Delay - Launch Clock Delay + Clock Pessi IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.614 2.807 zoom_clk + net (fanout=2) 0.614 2.807 ddr_clk USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.682 4.602 clkout0_wl_0 IOCKGATE_6_188/OUT td 0.268 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT @@ -12730,9 +13984,9 @@ Clock Skew : -0.003 (Capture Clock Delay - Launch Clock Delay + Clock Pessi IOL_327_210/INCK td 0.038 3.897 r clk_ibuf/opit_1/INCK net (fanout=1) 0.463 4.360 _N69 PLL_158_55/CLK_OUT1 td 0.074 4.434 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.603 5.037 zoom_clk + net (fanout=2) 0.603 5.037 ddr_clk USCM_84_113/CLK_USCM td 0.000 5.037 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 0.981 6.018 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 0.981 6.018 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.089 6.107 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.669 6.776 clkout0_wl_0 IOCKGATE_6_188/OUT td 0.200 6.976 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT @@ -12774,9 +14028,9 @@ Clock Skew : -0.003 (Capture Clock Delay - Launch Clock Delay + Clock Pessi IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.614 2.807 zoom_clk + net (fanout=2) 0.614 2.807 ddr_clk USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.682 4.602 clkout0_wl_0 IOCKGATE_6_188/OUT td 0.268 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT @@ -12799,9 +14053,9 @@ Clock Skew : -0.003 (Capture Clock Delay - Launch Clock Delay + Clock Pessi IOL_327_210/INCK td 0.038 3.897 r clk_ibuf/opit_1/INCK net (fanout=1) 0.463 4.360 _N69 PLL_158_55/CLK_OUT1 td 0.074 4.434 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.603 5.037 zoom_clk + net (fanout=2) 0.603 5.037 ddr_clk USCM_84_113/CLK_USCM td 0.000 5.037 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 0.981 6.018 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 0.981 6.018 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.089 6.107 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.669 6.776 clkout0_wl_0 IOCKGATE_6_188/OUT td 0.200 6.976 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT @@ -12843,9 +14097,9 @@ Clock Skew : -0.003 (Capture Clock Delay - Launch Clock Delay + Clock Pessi IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.614 2.807 zoom_clk + net (fanout=2) 0.614 2.807 ddr_clk USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.682 4.602 clkout0_wl_0 IOCKGATE_6_188/OUT td 0.268 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT @@ -12868,9 +14122,9 @@ Clock Skew : -0.003 (Capture Clock Delay - Launch Clock Delay + Clock Pessi IOL_327_210/INCK td 0.038 3.897 r clk_ibuf/opit_1/INCK net (fanout=1) 0.463 4.360 _N69 PLL_158_55/CLK_OUT1 td 0.074 4.434 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.603 5.037 zoom_clk + net (fanout=2) 0.603 5.037 ddr_clk USCM_84_113/CLK_USCM td 0.000 5.037 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 0.981 6.018 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 0.981 6.018 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.089 6.107 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.669 6.776 clkout0_wl_0 IOCKGATE_6_188/OUT td 0.200 6.976 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT @@ -12912,9 +14166,9 @@ Clock Skew : 0.009 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK net (fanout=1) 0.463 1.860 _N69 PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.603 2.537 zoom_clk + net (fanout=2) 0.603 2.537 ddr_clk USCM_84_113/CLK_USCM td 0.000 2.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.089 3.607 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.669 4.276 clkout0_wl_0 IOCKGATE_6_188/OUT td 0.200 4.476 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT @@ -12937,9 +14191,9 @@ Clock Skew : 0.009 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.614 2.807 zoom_clk + net (fanout=2) 0.614 2.807 ddr_clk USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.682 4.602 clkout0_wl_0 IOCKGATE_6_188/OUT td 0.268 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT @@ -12981,9 +14235,9 @@ Clock Skew : 0.009 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK net (fanout=1) 0.463 1.860 _N69 PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.603 2.537 zoom_clk + net (fanout=2) 0.603 2.537 ddr_clk USCM_84_113/CLK_USCM td 0.000 2.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.089 3.607 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.669 4.276 clkout0_wl_0 IOCKGATE_6_188/OUT td 0.200 4.476 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT @@ -13006,9 +14260,9 @@ Clock Skew : 0.009 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.614 2.807 zoom_clk + net (fanout=2) 0.614 2.807 ddr_clk USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.682 4.602 clkout0_wl_0 IOCKGATE_6_188/OUT td 0.268 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT @@ -13050,9 +14304,9 @@ Clock Skew : 0.009 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK net (fanout=1) 0.463 1.860 _N69 PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.603 2.537 zoom_clk + net (fanout=2) 0.603 2.537 ddr_clk USCM_84_113/CLK_USCM td 0.000 2.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.089 3.607 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.669 4.276 clkout0_wl_0 IOCKGATE_6_188/OUT td 0.200 4.476 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT @@ -13075,9 +14329,9 @@ Clock Skew : 0.009 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.614 2.807 zoom_clk + net (fanout=2) 0.614 2.807 ddr_clk USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.682 4.602 clkout0_wl_0 IOCKGATE_6_188/OUT td 0.268 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT @@ -13099,12 +14353,134 @@ Clock Skew : 0.009 (Capture Clock Delay - Launch Clock Delay + Clock Pessim ==================================================================================================== Startpoint : u_clk50m_rst/rst/opit_0_L5Q_perm/CLK -Endpoint : u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/RS +Endpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/RS +Path Group : clk_50m +Path Type : max (fast corner) +Path Class : async timing path +Clock Skew : -0.018 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 3.448 + Launch Clock Delay : 3.736 + Clock Pessimism Removal : 0.270 + + Location Delay Type Incr Path Logical Resource +---------------------------------------------------------------------------------------------------- + + Clock clk_50m (rising edge) 0.000 0.000 r + P20 0.000 0.000 r clk (port) + net (fanout=1) 0.074 0.074 clk + IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 1.578 clk_ibuf/ntD + IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.478 2.114 _N69 + PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.614 2.811 rd3_clk + USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT + net (fanout=2516) 0.925 3.736 ntclkbufg_1 + CLMS_158_237/CLK r u_clk50m_rst/rst/opit_0_L5Q_perm/CLK + + CLMS_158_237/Q0 tco 0.221 3.957 f u_clk50m_rst/rst/opit_0_L5Q_perm/Q + net (fanout=589) 2.173 6.130 rd3_rst + CLMA_58_40/RS f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/RS + + Data arrival time 6.130 Logic Levels: 0 + Logic: 0.221ns(9.231%), Route: 2.173ns(90.769%) +---------------------------------------------------------------------------------------------------- + + Clock clk_50m (rising edge) 20.000 20.000 r + P20 0.000 20.000 r clk (port) + net (fanout=1) 0.074 20.074 clk + IOBS_LR_328_209/DIN td 1.285 21.359 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 21.359 clk_ibuf/ntD + IOL_327_210/INCK td 0.038 21.397 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.463 21.860 _N69 + PLL_158_55/CLK_OUT0 td 0.078 21.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.603 22.541 rd3_clk + USCM_84_108/CLK_USCM td 0.000 22.541 r clkbufg_1/gopclkbufg/CLKOUT + net (fanout=2516) 0.907 23.448 ntclkbufg_1 + CLMA_58_40/CLK r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK + clock pessimism 0.270 23.718 + clock uncertainty -0.150 23.568 + + Recovery time -0.476 23.092 + + Data required time 23.092 +---------------------------------------------------------------------------------------------------- + Data required time 23.092 + Data arrival time 6.130 +---------------------------------------------------------------------------------------------------- + Slack (MET) 16.962 +==================================================================================================== + +==================================================================================================== + +Startpoint : u_clk50m_rst/rst/opit_0_L5Q_perm/CLK +Endpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[1]/opit_0_A2Q21/RS +Path Group : clk_50m +Path Type : max (fast corner) +Path Class : async timing path +Clock Skew : -0.010 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 3.456 + Launch Clock Delay : 3.736 + Clock Pessimism Removal : 0.270 + + Location Delay Type Incr Path Logical Resource +---------------------------------------------------------------------------------------------------- + + Clock clk_50m (rising edge) 0.000 0.000 r + P20 0.000 0.000 r clk (port) + net (fanout=1) 0.074 0.074 clk + IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 1.578 clk_ibuf/ntD + IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.478 2.114 _N69 + PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.614 2.811 rd3_clk + USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT + net (fanout=2516) 0.925 3.736 ntclkbufg_1 + CLMS_158_237/CLK r u_clk50m_rst/rst/opit_0_L5Q_perm/CLK + + CLMS_158_237/Q0 tco 0.221 3.957 f u_clk50m_rst/rst/opit_0_L5Q_perm/Q + net (fanout=589) 2.069 6.026 rd3_rst + CLMA_58_33/RS f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[1]/opit_0_A2Q21/RS + + Data arrival time 6.026 Logic Levels: 0 + Logic: 0.221ns(9.651%), Route: 2.069ns(90.349%) +---------------------------------------------------------------------------------------------------- + + Clock clk_50m (rising edge) 20.000 20.000 r + P20 0.000 20.000 r clk (port) + net (fanout=1) 0.074 20.074 clk + IOBS_LR_328_209/DIN td 1.285 21.359 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 21.359 clk_ibuf/ntD + IOL_327_210/INCK td 0.038 21.397 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.463 21.860 _N69 + PLL_158_55/CLK_OUT0 td 0.078 21.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.603 22.541 rd3_clk + USCM_84_108/CLK_USCM td 0.000 22.541 r clkbufg_1/gopclkbufg/CLKOUT + net (fanout=2516) 0.915 23.456 ntclkbufg_1 + CLMA_58_33/CLK r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[1]/opit_0_A2Q21/CLK + clock pessimism 0.270 23.726 + clock uncertainty -0.150 23.576 + + Recovery time -0.476 23.100 + + Data required time 23.100 +---------------------------------------------------------------------------------------------------- + Data required time 23.100 + Data arrival time 6.026 +---------------------------------------------------------------------------------------------------- + Slack (MET) 17.074 +==================================================================================================== + +==================================================================================================== + +Startpoint : u_clk50m_rst/rst/opit_0_L5Q_perm/CLK +Endpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[3]/opit_0_A2Q21/RS Path Group : clk_50m Path Type : max (fast corner) Path Class : async timing path -Clock Skew : -0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 3.436 +Clock Skew : -0.010 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 3.456 Launch Clock Delay : 3.736 Clock Pessimism Removal : 0.270 @@ -13121,891 +14497,1141 @@ Clock Skew : -0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessi PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 0.614 2.811 rd3_clk USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 0.925 3.736 ntclkbufg_1 - CLMS_94_177/CLK r u_clk50m_rst/rst/opit_0_L5Q_perm/CLK - - CLMS_94_177/Q0 tco 0.221 3.957 f u_clk50m_rst/rst/opit_0_L5Q_perm/Q - net (fanout=573) 1.712 5.669 rd3_rst - CLMS_146_37/RSCO td 0.113 5.782 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/RSOUT - net (fanout=4) 0.000 5.782 ntR414 - CLMS_146_41/RSCO td 0.113 5.895 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/RSOUT - net (fanout=4) 0.000 5.895 ntR413 - CLMS_146_45/RSCO td 0.113 6.008 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/RSOUT - net (fanout=3) 0.000 6.008 ntR412 - CLMS_146_49/RSCO td 0.113 6.121 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/RSOUT - net (fanout=2) 0.000 6.121 ntR411 - CLMS_146_53/RSCO td 0.113 6.234 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/RSOUT - net (fanout=4) 0.000 6.234 ntR410 - CLMS_146_57/RSCO td 0.113 6.347 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/RSOUT - net (fanout=6) 0.000 6.347 ntR409 - CLMS_146_61/RSCO td 0.113 6.460 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/RSOUT - net (fanout=5) 0.000 6.460 ntR408 - CLMS_146_69/RSCI f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/RS - - Data arrival time 6.460 Logic Levels: 7 - Logic: 1.012ns(37.151%), Route: 1.712ns(62.849%) + net (fanout=2516) 0.925 3.736 ntclkbufg_1 + CLMS_158_237/CLK r u_clk50m_rst/rst/opit_0_L5Q_perm/CLK + + CLMS_158_237/Q0 tco 0.221 3.957 f u_clk50m_rst/rst/opit_0_L5Q_perm/Q + net (fanout=589) 2.069 6.026 rd3_rst + CLMA_58_33/RS f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[3]/opit_0_A2Q21/RS + + Data arrival time 6.026 Logic Levels: 0 + Logic: 0.221ns(9.651%), Route: 2.069ns(90.349%) +---------------------------------------------------------------------------------------------------- + + Clock clk_50m (rising edge) 20.000 20.000 r + P20 0.000 20.000 r clk (port) + net (fanout=1) 0.074 20.074 clk + IOBS_LR_328_209/DIN td 1.285 21.359 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 21.359 clk_ibuf/ntD + IOL_327_210/INCK td 0.038 21.397 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.463 21.860 _N69 + PLL_158_55/CLK_OUT0 td 0.078 21.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.603 22.541 rd3_clk + USCM_84_108/CLK_USCM td 0.000 22.541 r clkbufg_1/gopclkbufg/CLKOUT + net (fanout=2516) 0.915 23.456 ntclkbufg_1 + CLMA_58_33/CLK r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[3]/opit_0_A2Q21/CLK + clock pessimism 0.270 23.726 + clock uncertainty -0.150 23.576 + + Recovery time -0.476 23.100 + + Data required time 23.100 +---------------------------------------------------------------------------------------------------- + Data required time 23.100 + Data arrival time 6.026 +---------------------------------------------------------------------------------------------------- + Slack (MET) 17.074 +==================================================================================================== + +==================================================================================================== + +Startpoint : image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK +Endpoint : image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/RS +Path Group : clk_50m +Path Type : min (fast corner) +Path Class : async timing path +Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 3.848 + Launch Clock Delay : 3.546 + Clock Pessimism Removal : -0.283 + + Location Delay Type Incr Path Logical Resource +---------------------------------------------------------------------------------------------------- + + Clock clk_50m (rising edge) 0.000 0.000 r + P20 0.000 0.000 r clk (port) + net (fanout=1) 0.074 0.074 clk + IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 1.359 clk_ibuf/ntD + IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.463 1.860 _N69 + PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.603 2.541 rd3_clk + USCM_84_108/CLK_USCM td 0.000 2.541 r clkbufg_1/gopclkbufg/CLKOUT + net (fanout=2516) 1.005 3.546 ntclkbufg_1 + CLMS_98_321/CLK r image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK + + CLMS_98_321/Q0 tco 0.182 3.728 r image_filiter_inst/multiline_buffer_inst/srst/opit_0/Q + net (fanout=40) 0.206 3.934 image_filiter_inst/multiline_buffer_inst/srst + CLMS_102_325/RSCO td 0.085 4.019 r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/RSOUT + net (fanout=2) 0.000 4.019 ntR19 + CLMS_102_329/RSCI r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/RS + + Data arrival time 4.019 Logic Levels: 1 + Logic: 0.267ns(56.448%), Route: 0.206ns(43.552%) +---------------------------------------------------------------------------------------------------- + + Clock clk_50m (rising edge) 0.000 0.000 r + P20 0.000 0.000 r clk (port) + net (fanout=1) 0.074 0.074 clk + IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 1.578 clk_ibuf/ntD + IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.478 2.114 _N69 + PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.614 2.811 rd3_clk + USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT + net (fanout=2516) 1.037 3.848 ntclkbufg_1 + CLMS_102_329/CLK r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK + clock pessimism -0.283 3.565 + clock uncertainty 0.000 3.565 + + Removal time 0.000 3.565 + + Data required time 3.565 +---------------------------------------------------------------------------------------------------- + Data required time 3.565 + Data arrival time 4.019 +---------------------------------------------------------------------------------------------------- + Slack (MET) 0.454 +==================================================================================================== + +==================================================================================================== + +Startpoint : image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK +Endpoint : image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/RS +Path Group : clk_50m +Path Type : min (fast corner) +Path Class : async timing path +Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 3.848 + Launch Clock Delay : 3.546 + Clock Pessimism Removal : -0.283 + + Location Delay Type Incr Path Logical Resource +---------------------------------------------------------------------------------------------------- + + Clock clk_50m (rising edge) 0.000 0.000 r + P20 0.000 0.000 r clk (port) + net (fanout=1) 0.074 0.074 clk + IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 1.359 clk_ibuf/ntD + IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.463 1.860 _N69 + PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.603 2.541 rd3_clk + USCM_84_108/CLK_USCM td 0.000 2.541 r clkbufg_1/gopclkbufg/CLKOUT + net (fanout=2516) 1.005 3.546 ntclkbufg_1 + CLMS_98_321/CLK r image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK + + CLMS_98_321/Q0 tco 0.182 3.728 r image_filiter_inst/multiline_buffer_inst/srst/opit_0/Q + net (fanout=40) 0.206 3.934 image_filiter_inst/multiline_buffer_inst/srst + CLMS_102_325/RSCO td 0.085 4.019 r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/RSOUT + net (fanout=2) 0.000 4.019 ntR19 + CLMS_102_329/RSCI r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/RS + + Data arrival time 4.019 Logic Levels: 1 + Logic: 0.267ns(56.448%), Route: 0.206ns(43.552%) +---------------------------------------------------------------------------------------------------- + + Clock clk_50m (rising edge) 0.000 0.000 r + P20 0.000 0.000 r clk (port) + net (fanout=1) 0.074 0.074 clk + IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 1.578 clk_ibuf/ntD + IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.478 2.114 _N69 + PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.614 2.811 rd3_clk + USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT + net (fanout=2516) 1.037 3.848 ntclkbufg_1 + CLMS_102_329/CLK r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK + clock pessimism -0.283 3.565 + clock uncertainty 0.000 3.565 + + Removal time 0.000 3.565 + + Data required time 3.565 +---------------------------------------------------------------------------------------------------- + Data required time 3.565 + Data arrival time 4.019 +---------------------------------------------------------------------------------------------------- + Slack (MET) 0.454 +==================================================================================================== + +==================================================================================================== + +Startpoint : image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK +Endpoint : image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0] +Path Group : clk_50m +Path Type : min (fast corner) +Path Class : async timing path +Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 3.848 + Launch Clock Delay : 3.546 + Clock Pessimism Removal : -0.283 + + Location Delay Type Incr Path Logical Resource +---------------------------------------------------------------------------------------------------- + + Clock clk_50m (rising edge) 0.000 0.000 r + P20 0.000 0.000 r clk (port) + net (fanout=1) 0.074 0.074 clk + IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 1.359 clk_ibuf/ntD + IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.463 1.860 _N69 + PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.603 2.541 rd3_clk + USCM_84_108/CLK_USCM td 0.000 2.541 r clkbufg_1/gopclkbufg/CLKOUT + net (fanout=2516) 1.005 3.546 ntclkbufg_1 + CLMS_98_321/CLK r image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK + + CLMS_98_321/Q0 tco 0.179 3.725 f image_filiter_inst/multiline_buffer_inst/srst/opit_0/Q + net (fanout=40) 0.282 4.007 image_filiter_inst/multiline_buffer_inst/srst + DRM_82_316/RSTB[0] f image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0] + + Data arrival time 4.007 Logic Levels: 0 + Logic: 0.179ns(38.829%), Route: 0.282ns(61.171%) +---------------------------------------------------------------------------------------------------- + + Clock clk_50m (rising edge) 0.000 0.000 r + P20 0.000 0.000 r clk (port) + net (fanout=1) 0.074 0.074 clk + IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 1.578 clk_ibuf/ntD + IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.478 2.114 _N69 + PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.614 2.811 rd3_clk + USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT + net (fanout=2516) 1.037 3.848 ntclkbufg_1 + DRM_82_316/CLKB[0] r image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] + clock pessimism -0.283 3.565 + clock uncertainty 0.000 3.565 + + Removal time -0.018 3.547 + + Data required time 3.547 +---------------------------------------------------------------------------------------------------- + Data required time 3.547 + Data arrival time 4.007 +---------------------------------------------------------------------------------------------------- + Slack (MET) 0.460 +==================================================================================================== + +==================================================================================================== + +Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_dqs_rst/opit_0_inv/RS +Path Group : clk_200m +Path Type : max (fast corner) +Path Class : async timing path +Clock Skew : -0.142 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 3.432 + Launch Clock Delay : 3.844 + Clock Pessimism Removal : 0.270 + + Location Delay Type Incr Path Logical Resource +---------------------------------------------------------------------------------------------------- + + Clock clk_200m (rising edge) 0.000 0.000 r + P20 0.000 0.000 r clk (port) + net (fanout=1) 0.074 0.074 clk + IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 1.578 clk_ibuf/ntD + IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.478 2.114 _N69 + PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 + net (fanout=2) 0.614 2.807 ddr_clk + USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + net (fanout=71) 1.037 3.844 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + CLMA_174_252/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK + + CLMA_174_252/Q1 tco 0.223 4.067 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/Q + net (fanout=687) 1.849 5.916 u_axi_ddr_top/I_ipsxb_ddr_top/ddr_rstn + CLMS_10_193/RS f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_dqs_rst/opit_0_inv/RS + + Data arrival time 5.916 Logic Levels: 0 + Logic: 0.223ns(10.763%), Route: 1.849ns(89.237%) ---------------------------------------------------------------------------------------------------- - Clock clk_50m (rising edge) 20.000 20.000 r - P20 0.000 20.000 r clk (port) - net (fanout=1) 0.074 20.074 clk - IOBS_LR_328_209/DIN td 1.285 21.359 r clk_ibuf/opit_0/O - net (fanout=1) 0.000 21.359 clk_ibuf/ntD - IOL_327_210/INCK td 0.038 21.397 r clk_ibuf/opit_1/INCK - net (fanout=1) 0.463 21.860 _N69 - PLL_158_55/CLK_OUT0 td 0.078 21.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 - net (fanout=2) 0.603 22.541 rd3_clk - USCM_84_108/CLK_USCM td 0.000 22.541 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 0.895 23.436 ntclkbufg_1 - CLMS_146_69/CLK r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/CLK - clock pessimism 0.270 23.706 - clock uncertainty -0.150 23.556 + Clock clk_200m (rising edge) 5.000 5.000 r + P20 0.000 5.000 r clk (port) + net (fanout=1) 0.074 5.074 clk + IOBS_LR_328_209/DIN td 1.285 6.359 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 6.359 clk_ibuf/ntD + IOL_327_210/INCK td 0.038 6.397 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.463 6.860 _N69 + PLL_158_55/CLK_OUT1 td 0.074 6.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 + net (fanout=2) 0.603 7.537 ddr_clk + USCM_84_113/CLK_USCM td 0.000 7.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + net (fanout=71) 0.895 8.432 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + CLMS_10_193/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_dqs_rst/opit_0_inv/CLK + clock pessimism 0.270 8.702 + clock uncertainty -0.150 8.552 - Recovery time 0.000 23.556 + Recovery time -0.476 8.076 - Data required time 23.556 + Data required time 8.076 ---------------------------------------------------------------------------------------------------- - Data required time 23.556 - Data arrival time 6.460 + Data required time 8.076 + Data arrival time 5.916 ---------------------------------------------------------------------------------------------------- - Slack (MET) 17.096 + Slack (MET) 2.160 ==================================================================================================== ==================================================================================================== -Startpoint : u_clk50m_rst/rst/opit_0_L5Q_perm/CLK -Endpoint : u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/RS -Path Group : clk_50m +Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d1/opit_0_inv/RS +Path Group : clk_200m Path Type : max (fast corner) Path Class : async timing path -Clock Skew : -0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 3.436 - Launch Clock Delay : 3.736 +Clock Skew : -0.142 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 3.432 + Launch Clock Delay : 3.844 Clock Pessimism Removal : 0.270 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_50m (rising edge) 0.000 0.000 r + Clock clk_200m (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.578 clk_ibuf/ntD IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 - PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 - net (fanout=2) 0.614 2.811 rd3_clk - USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 0.925 3.736 ntclkbufg_1 - CLMS_94_177/CLK r u_clk50m_rst/rst/opit_0_L5Q_perm/CLK - - CLMS_94_177/Q0 tco 0.221 3.957 f u_clk50m_rst/rst/opit_0_L5Q_perm/Q - net (fanout=573) 1.712 5.669 rd3_rst - CLMS_146_37/RSCO td 0.113 5.782 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/RSOUT - net (fanout=4) 0.000 5.782 ntR414 - CLMS_146_41/RSCO td 0.113 5.895 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/RSOUT - net (fanout=4) 0.000 5.895 ntR413 - CLMS_146_45/RSCO td 0.113 6.008 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/RSOUT - net (fanout=3) 0.000 6.008 ntR412 - CLMS_146_49/RSCO td 0.113 6.121 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/RSOUT - net (fanout=2) 0.000 6.121 ntR411 - CLMS_146_53/RSCO td 0.113 6.234 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/RSOUT - net (fanout=4) 0.000 6.234 ntR410 - CLMS_146_57/RSCO td 0.113 6.347 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/RSOUT - net (fanout=6) 0.000 6.347 ntR409 - CLMS_146_61/RSCO td 0.113 6.460 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/RSOUT - net (fanout=5) 0.000 6.460 ntR408 - CLMS_146_69/RSCI f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/RS - - Data arrival time 6.460 Logic Levels: 7 - Logic: 1.012ns(37.151%), Route: 1.712ns(62.849%) + PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 + net (fanout=2) 0.614 2.807 ddr_clk + USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + net (fanout=71) 1.037 3.844 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + CLMA_174_252/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK + + CLMA_174_252/Q1 tco 0.223 4.067 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/Q + net (fanout=687) 1.608 5.675 u_axi_ddr_top/I_ipsxb_ddr_top/ddr_rstn + CLMA_30_184/RS f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d1/opit_0_inv/RS + + Data arrival time 5.675 Logic Levels: 0 + Logic: 0.223ns(12.179%), Route: 1.608ns(87.821%) ---------------------------------------------------------------------------------------------------- - Clock clk_50m (rising edge) 20.000 20.000 r - P20 0.000 20.000 r clk (port) - net (fanout=1) 0.074 20.074 clk - IOBS_LR_328_209/DIN td 1.285 21.359 r clk_ibuf/opit_0/O - net (fanout=1) 0.000 21.359 clk_ibuf/ntD - IOL_327_210/INCK td 0.038 21.397 r clk_ibuf/opit_1/INCK - net (fanout=1) 0.463 21.860 _N69 - PLL_158_55/CLK_OUT0 td 0.078 21.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 - net (fanout=2) 0.603 22.541 rd3_clk - USCM_84_108/CLK_USCM td 0.000 22.541 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 0.895 23.436 ntclkbufg_1 - CLMS_146_69/CLK r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/CLK - clock pessimism 0.270 23.706 - clock uncertainty -0.150 23.556 + Clock clk_200m (rising edge) 5.000 5.000 r + P20 0.000 5.000 r clk (port) + net (fanout=1) 0.074 5.074 clk + IOBS_LR_328_209/DIN td 1.285 6.359 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 6.359 clk_ibuf/ntD + IOL_327_210/INCK td 0.038 6.397 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.463 6.860 _N69 + PLL_158_55/CLK_OUT1 td 0.074 6.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 + net (fanout=2) 0.603 7.537 ddr_clk + USCM_84_113/CLK_USCM td 0.000 7.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + net (fanout=71) 0.895 8.432 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + CLMA_30_184/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d1/opit_0_inv/CLK + clock pessimism 0.270 8.702 + clock uncertainty -0.150 8.552 - Recovery time 0.000 23.556 + Recovery time -0.476 8.076 - Data required time 23.556 + Data required time 8.076 ---------------------------------------------------------------------------------------------------- - Data required time 23.556 - Data arrival time 6.460 + Data required time 8.076 + Data arrival time 5.675 ---------------------------------------------------------------------------------------------------- - Slack (MET) 17.096 + Slack (MET) 2.401 ==================================================================================================== ==================================================================================================== -Startpoint : u_clk50m_rst/rst/opit_0_L5Q_perm/CLK -Endpoint : u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/opit_0/RS -Path Group : clk_50m +Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d2/opit_0_inv/RS +Path Group : clk_200m Path Type : max (fast corner) Path Class : async timing path -Clock Skew : -0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 3.436 - Launch Clock Delay : 3.736 +Clock Skew : -0.142 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 3.432 + Launch Clock Delay : 3.844 Clock Pessimism Removal : 0.270 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_50m (rising edge) 0.000 0.000 r + Clock clk_200m (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.578 clk_ibuf/ntD IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 - PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 - net (fanout=2) 0.614 2.811 rd3_clk - USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 0.925 3.736 ntclkbufg_1 - CLMS_94_177/CLK r u_clk50m_rst/rst/opit_0_L5Q_perm/CLK - - CLMS_94_177/Q0 tco 0.221 3.957 f u_clk50m_rst/rst/opit_0_L5Q_perm/Q - net (fanout=573) 1.712 5.669 rd3_rst - CLMS_146_37/RSCO td 0.113 5.782 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/RSOUT - net (fanout=4) 0.000 5.782 ntR414 - CLMS_146_41/RSCO td 0.113 5.895 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/RSOUT - net (fanout=4) 0.000 5.895 ntR413 - CLMS_146_45/RSCO td 0.113 6.008 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/RSOUT - net (fanout=3) 0.000 6.008 ntR412 - CLMS_146_49/RSCO td 0.113 6.121 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/RSOUT - net (fanout=2) 0.000 6.121 ntR411 - CLMS_146_53/RSCO td 0.113 6.234 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/RSOUT - net (fanout=4) 0.000 6.234 ntR410 - CLMS_146_57/RSCO td 0.113 6.347 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/RSOUT - net (fanout=6) 0.000 6.347 ntR409 - CLMS_146_61/RSCO td 0.113 6.460 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/RSOUT - net (fanout=5) 0.000 6.460 ntR408 - CLMS_146_69/RSCI f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/opit_0/RS - - Data arrival time 6.460 Logic Levels: 7 - Logic: 1.012ns(37.151%), Route: 1.712ns(62.849%) + PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 + net (fanout=2) 0.614 2.807 ddr_clk + USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + net (fanout=71) 1.037 3.844 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + CLMA_174_252/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK + + CLMA_174_252/Q1 tco 0.223 4.067 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/Q + net (fanout=687) 1.608 5.675 u_axi_ddr_top/I_ipsxb_ddr_top/ddr_rstn + CLMA_30_184/RS f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d2/opit_0_inv/RS + + Data arrival time 5.675 Logic Levels: 0 + Logic: 0.223ns(12.179%), Route: 1.608ns(87.821%) ---------------------------------------------------------------------------------------------------- - Clock clk_50m (rising edge) 20.000 20.000 r - P20 0.000 20.000 r clk (port) - net (fanout=1) 0.074 20.074 clk - IOBS_LR_328_209/DIN td 1.285 21.359 r clk_ibuf/opit_0/O - net (fanout=1) 0.000 21.359 clk_ibuf/ntD - IOL_327_210/INCK td 0.038 21.397 r clk_ibuf/opit_1/INCK - net (fanout=1) 0.463 21.860 _N69 - PLL_158_55/CLK_OUT0 td 0.078 21.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 - net (fanout=2) 0.603 22.541 rd3_clk - USCM_84_108/CLK_USCM td 0.000 22.541 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 0.895 23.436 ntclkbufg_1 - CLMS_146_69/CLK r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/opit_0/CLK - clock pessimism 0.270 23.706 - clock uncertainty -0.150 23.556 + Clock clk_200m (rising edge) 5.000 5.000 r + P20 0.000 5.000 r clk (port) + net (fanout=1) 0.074 5.074 clk + IOBS_LR_328_209/DIN td 1.285 6.359 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 6.359 clk_ibuf/ntD + IOL_327_210/INCK td 0.038 6.397 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.463 6.860 _N69 + PLL_158_55/CLK_OUT1 td 0.074 6.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 + net (fanout=2) 0.603 7.537 ddr_clk + USCM_84_113/CLK_USCM td 0.000 7.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + net (fanout=71) 0.895 8.432 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + CLMA_30_184/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d2/opit_0_inv/CLK + clock pessimism 0.270 8.702 + clock uncertainty -0.150 8.552 - Recovery time 0.000 23.556 + Recovery time -0.476 8.076 - Data required time 23.556 + Data required time 8.076 ---------------------------------------------------------------------------------------------------- - Data required time 23.556 - Data arrival time 6.460 + Data required time 8.076 + Data arrival time 5.675 ---------------------------------------------------------------------------------------------------- - Slack (MET) 17.096 + Slack (MET) 2.401 ==================================================================================================== ==================================================================================================== -Startpoint : image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK -Endpoint : image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0] -Path Group : clk_50m +Startpoint : u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/opit_0/RS +Path Group : clk_200m Path Type : min (fast corner) Path Class : async timing path -Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 3.736 - Launch Clock Delay : 3.436 - Clock Pessimism Removal : -0.281 +Clock Skew : 0.039 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 3.844 + Launch Clock Delay : 3.542 + Clock Pessimism Removal : -0.263 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_50m (rising edge) 0.000 0.000 r + Clock clk_200m (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.359 clk_ibuf/ntD IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK net (fanout=1) 0.463 1.860 _N69 - PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 - net (fanout=2) 0.603 2.541 rd3_clk - USCM_84_108/CLK_USCM td 0.000 2.541 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 0.895 3.436 ntclkbufg_1 - CLMS_134_93/CLK r image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK + PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 + net (fanout=2) 0.603 2.537 ddr_clk + USCM_84_153/CLK_USCM td 0.000 2.537 r USCMROUTE_2/CLKOUT + net (fanout=6) 1.005 3.542 ntR3952 + CLMS_174_253/CLK r u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK - CLMS_134_93/Q0 tco 0.179 3.615 f image_filiter_inst/multiline_buffer_inst/srst/opit_0/Q - net (fanout=37) 0.240 3.855 image_filiter_inst/multiline_buffer_inst/srst - DRM_142_88/RSTB[0] f image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0] + CLMS_174_253/Q0 tco 0.179 3.721 f u_ddr_rst/rst/opit_0_inv_L5Q_perm/Q + net (fanout=2) 0.131 3.852 ddr_rst + CLMA_174_252/RS f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/opit_0/RS - Data arrival time 3.855 Logic Levels: 0 - Logic: 0.179ns(42.721%), Route: 0.240ns(57.279%) + Data arrival time 3.852 Logic Levels: 0 + Logic: 0.179ns(57.742%), Route: 0.131ns(42.258%) ---------------------------------------------------------------------------------------------------- - Clock clk_50m (rising edge) 0.000 0.000 r + Clock clk_200m (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.578 clk_ibuf/ntD IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 - PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 - net (fanout=2) 0.614 2.811 rd3_clk - USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 0.925 3.736 ntclkbufg_1 - DRM_142_88/CLKB[0] r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] - clock pessimism -0.281 3.455 - clock uncertainty 0.000 3.455 + PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 + net (fanout=2) 0.614 2.807 ddr_clk + USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + net (fanout=71) 1.037 3.844 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + CLMA_174_252/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/opit_0/CLK + clock pessimism -0.263 3.581 + clock uncertainty 0.000 3.581 - Removal time -0.018 3.437 + Removal time -0.181 3.400 - Data required time 3.437 + Data required time 3.400 ---------------------------------------------------------------------------------------------------- - Data required time 3.437 - Data arrival time 3.855 + Data required time 3.400 + Data arrival time 3.852 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.418 + Slack (MET) 0.452 ==================================================================================================== ==================================================================================================== -Startpoint : image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK -Endpoint : image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTA[0] -Path Group : clk_50m +Startpoint : u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/RS +Path Group : clk_200m Path Type : min (fast corner) Path Class : async timing path -Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 3.736 - Launch Clock Delay : 3.436 - Clock Pessimism Removal : -0.281 +Clock Skew : 0.039 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 3.844 + Launch Clock Delay : 3.542 + Clock Pessimism Removal : -0.263 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_50m (rising edge) 0.000 0.000 r + Clock clk_200m (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.359 clk_ibuf/ntD IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK net (fanout=1) 0.463 1.860 _N69 - PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 - net (fanout=2) 0.603 2.541 rd3_clk - USCM_84_108/CLK_USCM td 0.000 2.541 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 0.895 3.436 ntclkbufg_1 - CLMS_134_93/CLK r image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK + PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 + net (fanout=2) 0.603 2.537 ddr_clk + USCM_84_153/CLK_USCM td 0.000 2.537 r USCMROUTE_2/CLKOUT + net (fanout=6) 1.005 3.542 ntR3952 + CLMS_174_253/CLK r u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK - CLMS_134_93/Q0 tco 0.179 3.615 f image_filiter_inst/multiline_buffer_inst/srst/opit_0/Q - net (fanout=37) 0.240 3.855 image_filiter_inst/multiline_buffer_inst/srst - DRM_142_88/RSTA[0] f image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTA[0] + CLMS_174_253/Q0 tco 0.179 3.721 f u_ddr_rst/rst/opit_0_inv_L5Q_perm/Q + net (fanout=2) 0.131 3.852 ddr_rst + CLMA_174_252/RS f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/RS - Data arrival time 3.855 Logic Levels: 0 - Logic: 0.179ns(42.721%), Route: 0.240ns(57.279%) + Data arrival time 3.852 Logic Levels: 0 + Logic: 0.179ns(57.742%), Route: 0.131ns(42.258%) ---------------------------------------------------------------------------------------------------- - Clock clk_50m (rising edge) 0.000 0.000 r + Clock clk_200m (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.578 clk_ibuf/ntD IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 - PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 - net (fanout=2) 0.614 2.811 rd3_clk - USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 0.925 3.736 ntclkbufg_1 - DRM_142_88/CLKA[0] r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] - clock pessimism -0.281 3.455 - clock uncertainty 0.000 3.455 + PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 + net (fanout=2) 0.614 2.807 ddr_clk + USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + net (fanout=71) 1.037 3.844 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + CLMA_174_252/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK + clock pessimism -0.263 3.581 + clock uncertainty 0.000 3.581 - Removal time -0.038 3.417 + Removal time -0.181 3.400 - Data required time 3.417 + Data required time 3.400 ---------------------------------------------------------------------------------------------------- - Data required time 3.417 - Data arrival time 3.855 + Data required time 3.400 + Data arrival time 3.852 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.438 + Slack (MET) 0.452 ==================================================================================================== ==================================================================================================== -Startpoint : image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK -Endpoint : image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/RS -Path Group : clk_50m +Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q/CLK +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[0]/opit_0_inv_L5Q_perm/RS +Path Group : clk_200m Path Type : min (fast corner) Path Class : async timing path Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 3.736 - Launch Clock Delay : 3.436 + Capture Clock Delay : 3.732 + Launch Clock Delay : 3.432 Clock Pessimism Removal : -0.281 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_50m (rising edge) 0.000 0.000 r + Clock clk_200m (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.359 clk_ibuf/ntD IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK net (fanout=1) 0.463 1.860 _N69 - PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 - net (fanout=2) 0.603 2.541 rd3_clk - USCM_84_108/CLK_USCM td 0.000 2.541 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 0.895 3.436 ntclkbufg_1 - CLMS_134_93/CLK r image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK + PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 + net (fanout=2) 0.603 2.537 ddr_clk + USCM_84_113/CLK_USCM td 0.000 2.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + net (fanout=71) 0.895 3.432 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + CLMA_58_184/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q/CLK - CLMS_134_93/Q0 tco 0.182 3.618 r image_filiter_inst/multiline_buffer_inst/srst/opit_0/Q - net (fanout=37) 0.292 3.910 image_filiter_inst/multiline_buffer_inst/srst - CLMA_138_81/RSCO td 0.085 3.995 r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/RSOUT - net (fanout=2) 0.000 3.995 ntR38 - CLMA_138_85/RSCI r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/RS + CLMA_58_184/Q0 tco 0.182 3.614 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q/Q + net (fanout=22) 0.316 3.930 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/logic_rstn + CLMA_38_184/RS r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[0]/opit_0_inv_L5Q_perm/RS - Data arrival time 3.995 Logic Levels: 1 - Logic: 0.267ns(47.764%), Route: 0.292ns(52.236%) + Data arrival time 3.930 Logic Levels: 0 + Logic: 0.182ns(36.546%), Route: 0.316ns(63.454%) ---------------------------------------------------------------------------------------------------- - Clock clk_50m (rising edge) 0.000 0.000 r + Clock clk_200m (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.578 clk_ibuf/ntD IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 - PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 - net (fanout=2) 0.614 2.811 rd3_clk - USCM_84_108/CLK_USCM td 0.000 2.811 r clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2517) 0.925 3.736 ntclkbufg_1 - CLMA_138_85/CLK r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK - clock pessimism -0.281 3.455 - clock uncertainty 0.000 3.455 + PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 + net (fanout=2) 0.614 2.807 ddr_clk + USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + net (fanout=71) 0.925 3.732 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + CLMA_38_184/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[0]/opit_0_inv_L5Q_perm/CLK + clock pessimism -0.281 3.451 + clock uncertainty 0.000 3.451 - Removal time 0.000 3.455 + Removal time -0.187 3.264 - Data required time 3.455 + Data required time 3.264 ---------------------------------------------------------------------------------------------------- - Data required time 3.455 - Data arrival time 3.995 + Data required time 3.264 + Data arrival time 3.930 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.540 + Slack (MET) 0.666 ==================================================================================================== ==================================================================================================== -Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK -Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d1/opit_0_inv/RS -Path Group : clk_200m +Startpoint : rstn_out1/opit_0_inv/CLK +Endpoint : ms72xx_ctl/rstn_temp1/opit_0_inv/RS +Path Group : clk_10m Path Type : max (fast corner) Path Class : async timing path -Clock Skew : -0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 3.432 - Launch Clock Delay : 3.732 +Clock Skew : 0.080 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 3.547 + Launch Clock Delay : 3.737 Clock Pessimism Removal : 0.270 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_200m (rising edge) 0.000 0.000 r + Clock clk_10m (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.578 clk_ibuf/ntD IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 - PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.614 2.807 zoom_clk - USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 0.925 3.732 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - CLMA_202_148/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK + PLL_158_55/CLK_OUT4 td 0.084 2.198 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 + net (fanout=1) 0.614 2.812 clk_10m + USCM_84_110/CLK_USCM td 0.000 2.812 r clkbufg_4/gopclkbufg/CLKOUT + net (fanout=235) 0.925 3.737 ntclkbufg_4 + CLMS_270_193/CLK r rstn_out1/opit_0_inv/CLK - CLMA_202_148/Q1 tco 0.223 3.955 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/Q - net (fanout=686) 1.964 5.919 u_axi_ddr_top/I_ipsxb_ddr_top/ddr_rstn - CLMS_10_193/RS f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d1/opit_0_inv/RS + CLMS_270_193/Q3 tco 0.220 3.957 f rstn_out1/opit_0_inv/Q + net (fanout=3) 0.853 4.810 nt_eth_rstn + CLMA_262_268/RS f ms72xx_ctl/rstn_temp1/opit_0_inv/RS - Data arrival time 5.919 Logic Levels: 0 - Logic: 0.223ns(10.197%), Route: 1.964ns(89.803%) + Data arrival time 4.810 Logic Levels: 0 + Logic: 0.220ns(20.503%), Route: 0.853ns(79.497%) ---------------------------------------------------------------------------------------------------- - Clock clk_200m (rising edge) 5.000 5.000 r - P20 0.000 5.000 r clk (port) - net (fanout=1) 0.074 5.074 clk - IOBS_LR_328_209/DIN td 1.285 6.359 r clk_ibuf/opit_0/O - net (fanout=1) 0.000 6.359 clk_ibuf/ntD - IOL_327_210/INCK td 0.038 6.397 r clk_ibuf/opit_1/INCK - net (fanout=1) 0.463 6.860 _N69 - PLL_158_55/CLK_OUT1 td 0.074 6.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.603 7.537 zoom_clk - USCM_84_113/CLK_USCM td 0.000 7.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 0.895 8.432 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - CLMS_10_193/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d1/opit_0_inv/CLK - clock pessimism 0.270 8.702 - clock uncertainty -0.150 8.552 + Clock clk_10m (rising edge) 100.000 100.000 r + P20 0.000 100.000 r clk (port) + net (fanout=1) 0.074 100.074 clk + IOBS_LR_328_209/DIN td 1.285 101.359 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 101.359 clk_ibuf/ntD + IOL_327_210/INCK td 0.038 101.397 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.463 101.860 _N69 + PLL_158_55/CLK_OUT4 td 0.079 101.939 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 + net (fanout=1) 0.603 102.542 clk_10m + USCM_84_110/CLK_USCM td 0.000 102.542 r clkbufg_4/gopclkbufg/CLKOUT + net (fanout=235) 1.005 103.547 ntclkbufg_4 + CLMA_262_268/CLK r ms72xx_ctl/rstn_temp1/opit_0_inv/CLK + clock pessimism 0.270 103.817 + clock uncertainty -0.150 103.667 + + Recovery time -0.476 103.191 + + Data required time 103.191 +---------------------------------------------------------------------------------------------------- + Data required time 103.191 + Data arrival time 4.810 +---------------------------------------------------------------------------------------------------- + Slack (MET) 98.381 +==================================================================================================== + +==================================================================================================== + +Startpoint : rstn_out1/opit_0_inv/CLK +Endpoint : ms72xx_ctl/rstn_temp1/opit_0_inv/RS +Path Group : clk_10m +Path Type : min (fast corner) +Path Class : async timing path +Clock Skew : 0.142 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 3.849 + Launch Clock Delay : 3.437 + Clock Pessimism Removal : -0.270 + + Location Delay Type Incr Path Logical Resource +---------------------------------------------------------------------------------------------------- + + Clock clk_10m (rising edge) 0.000 0.000 r + P20 0.000 0.000 r clk (port) + net (fanout=1) 0.074 0.074 clk + IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 1.359 clk_ibuf/ntD + IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.463 1.860 _N69 + PLL_158_55/CLK_OUT4 td 0.079 1.939 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 + net (fanout=1) 0.603 2.542 clk_10m + USCM_84_110/CLK_USCM td 0.000 2.542 r clkbufg_4/gopclkbufg/CLKOUT + net (fanout=235) 0.895 3.437 ntclkbufg_4 + CLMS_270_193/CLK r rstn_out1/opit_0_inv/CLK + + CLMS_270_193/Q3 tco 0.182 3.619 r rstn_out1/opit_0_inv/Q + net (fanout=3) 0.646 4.265 nt_eth_rstn + CLMA_262_268/RS r ms72xx_ctl/rstn_temp1/opit_0_inv/RS + + Data arrival time 4.265 Logic Levels: 0 + Logic: 0.182ns(21.981%), Route: 0.646ns(78.019%) +---------------------------------------------------------------------------------------------------- - Recovery time -0.476 8.076 + Clock clk_10m (rising edge) 0.000 0.000 r + P20 0.000 0.000 r clk (port) + net (fanout=1) 0.074 0.074 clk + IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 1.578 clk_ibuf/ntD + IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.478 2.114 _N69 + PLL_158_55/CLK_OUT4 td 0.084 2.198 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 + net (fanout=1) 0.614 2.812 clk_10m + USCM_84_110/CLK_USCM td 0.000 2.812 r clkbufg_4/gopclkbufg/CLKOUT + net (fanout=235) 1.037 3.849 ntclkbufg_4 + CLMA_262_268/CLK r ms72xx_ctl/rstn_temp1/opit_0_inv/CLK + clock pessimism -0.270 3.579 + clock uncertainty 0.000 3.579 - Data required time 8.076 + Removal time -0.187 3.392 + + Data required time 3.392 ---------------------------------------------------------------------------------------------------- - Data required time 8.076 - Data arrival time 5.919 + Data required time 3.392 + Data arrival time 4.265 ---------------------------------------------------------------------------------------------------- - Slack (MET) 2.157 + Slack (MET) 0.873 ==================================================================================================== ==================================================================================================== -Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK -Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d2/opit_0_inv/RS -Path Group : clk_200m +Startpoint : u_zoom_rst/rst/opit_0_L5Q_perm/CLK +Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/RSTA[0] +Path Group : clk_1080p60Hz Path Type : max (fast corner) Path Class : async timing path -Clock Skew : -0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 3.432 - Launch Clock Delay : 3.732 - Clock Pessimism Removal : 0.270 +Clock Skew : 0.080 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 5.630 + Launch Clock Delay : 5.882 + Clock Pessimism Removal : 0.332 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_200m (rising edge) 0.000 0.000 r + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.578 clk_ibuf/ntD IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 - PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.614 2.807 zoom_clk - USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 0.925 3.732 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - CLMA_202_148/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK + PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.614 2.811 rd3_clk + USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.131 3.942 ntR3950 + PLL_158_303/CLK_OUT0 td 0.083 4.025 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 0.932 4.957 zoom_clk + USCM_84_118/CLK_USCM td 0.000 4.957 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 0.925 5.882 ntclkbufg_3 + CLMA_170_124/CLK r u_zoom_rst/rst/opit_0_L5Q_perm/CLK - CLMA_202_148/Q1 tco 0.223 3.955 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/Q - net (fanout=686) 1.964 5.919 u_axi_ddr_top/I_ipsxb_ddr_top/ddr_rstn - CLMS_10_193/RS f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d2/opit_0_inv/RS + CLMA_170_124/Q0 tco 0.221 6.103 f u_zoom_rst/rst/opit_0_L5Q_perm/Q + net (fanout=114) 2.069 8.172 zoom_rst + DRM_306_252/RSTA[0] f u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/RSTA[0] - Data arrival time 5.919 Logic Levels: 0 - Logic: 0.223ns(10.197%), Route: 1.964ns(89.803%) + Data arrival time 8.172 Logic Levels: 0 + Logic: 0.221ns(9.651%), Route: 2.069ns(90.349%) ---------------------------------------------------------------------------------------------------- - Clock clk_200m (rising edge) 5.000 5.000 r - P20 0.000 5.000 r clk (port) - net (fanout=1) 0.074 5.074 clk - IOBS_LR_328_209/DIN td 1.285 6.359 r clk_ibuf/opit_0/O - net (fanout=1) 0.000 6.359 clk_ibuf/ntD - IOL_327_210/INCK td 0.038 6.397 r clk_ibuf/opit_1/INCK - net (fanout=1) 0.463 6.860 _N69 - PLL_158_55/CLK_OUT1 td 0.074 6.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.603 7.537 zoom_clk - USCM_84_113/CLK_USCM td 0.000 7.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 0.895 8.432 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - CLMS_10_193/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d2/opit_0_inv/CLK - clock pessimism 0.270 8.702 - clock uncertainty -0.150 8.552 + Clock clk_1080p60Hz (rising edge) 6.736 6.736 r + P20 0.000 6.736 r clk (port) + net (fanout=1) 0.074 6.810 clk + IOBS_LR_328_209/DIN td 1.285 8.095 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 8.095 clk_ibuf/ntD + IOL_327_210/INCK td 0.038 8.133 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.463 8.596 _N69 + PLL_158_55/CLK_OUT0 td 0.078 8.674 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.603 9.277 rd3_clk + USCM_84_154/CLK_USCM td 0.000 9.277 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.091 10.368 ntR3950 + PLL_158_303/CLK_OUT0 td 0.078 10.446 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 0.915 11.361 zoom_clk + USCM_84_118/CLK_USCM td 0.000 11.361 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 1.005 12.366 ntclkbufg_3 + DRM_306_252/CLKA[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/CLKA[0] + clock pessimism 0.332 12.698 + clock uncertainty -0.150 12.548 - Recovery time -0.476 8.076 + Recovery time -0.088 12.460 - Data required time 8.076 + Data required time 12.460 ---------------------------------------------------------------------------------------------------- - Data required time 8.076 - Data arrival time 5.919 + Data required time 12.460 + Data arrival time 8.172 ---------------------------------------------------------------------------------------------------- - Slack (MET) 2.157 + Slack (MET) 4.288 ==================================================================================================== ==================================================================================================== Startpoint : u_zoom_rst/rst/opit_0_L5Q_perm/CLK -Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[8].U_GTP_DRM18K/iGopDrm/RSTA[0] -Path Group : clk_200m +Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/RSTA[0] +Path Group : clk_1080p60Hz Path Type : max (fast corner) Path Class : async timing path Clock Skew : 0.080 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 3.542 - Launch Clock Delay : 3.732 - Clock Pessimism Removal : 0.270 + Capture Clock Delay : 5.630 + Launch Clock Delay : 5.882 + Clock Pessimism Removal : 0.332 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_200m (rising edge) 0.000 0.000 r + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.578 clk_ibuf/ntD IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 - PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.614 2.807 zoom_clk - USCM_84_122/CLK_USCM td 0.000 2.807 r USCMROUTE_2/CLKOUT - net (fanout=759) 0.925 3.732 ntR3909 - CLMS_186_125/CLK r u_zoom_rst/rst/opit_0_L5Q_perm/CLK + PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.614 2.811 rd3_clk + USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.131 3.942 ntR3950 + PLL_158_303/CLK_OUT0 td 0.083 4.025 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 0.932 4.957 zoom_clk + USCM_84_118/CLK_USCM td 0.000 4.957 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 0.925 5.882 ntclkbufg_3 + CLMA_170_124/CLK r u_zoom_rst/rst/opit_0_L5Q_perm/CLK - CLMS_186_125/Q0 tco 0.221 3.953 f u_zoom_rst/rst/opit_0_L5Q_perm/Q - net (fanout=131) 2.332 6.285 zoom_rst - DRM_278_356/RSTA[0] f u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[8].U_GTP_DRM18K/iGopDrm/RSTA[0] + CLMA_170_124/Q0 tco 0.221 6.103 f u_zoom_rst/rst/opit_0_L5Q_perm/Q + net (fanout=114) 2.029 8.132 zoom_rst + DRM_306_292/RSTA[0] f u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/RSTA[0] - Data arrival time 6.285 Logic Levels: 0 - Logic: 0.221ns(8.656%), Route: 2.332ns(91.344%) + Data arrival time 8.132 Logic Levels: 0 + Logic: 0.221ns(9.822%), Route: 2.029ns(90.178%) ---------------------------------------------------------------------------------------------------- - Clock clk_200m (rising edge) 5.000 5.000 r - P20 0.000 5.000 r clk (port) - net (fanout=1) 0.074 5.074 clk - IOBS_LR_328_209/DIN td 1.285 6.359 r clk_ibuf/opit_0/O - net (fanout=1) 0.000 6.359 clk_ibuf/ntD - IOL_327_210/INCK td 0.038 6.397 r clk_ibuf/opit_1/INCK - net (fanout=1) 0.463 6.860 _N69 - PLL_158_55/CLK_OUT1 td 0.074 6.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.603 7.537 zoom_clk - USCM_84_122/CLK_USCM td 0.000 7.537 r USCMROUTE_2/CLKOUT - net (fanout=759) 1.005 8.542 ntR3909 - DRM_278_356/CLKA[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[8].U_GTP_DRM18K/iGopDrm/CLKA[0] - clock pessimism 0.270 8.812 - clock uncertainty -0.150 8.662 + Clock clk_1080p60Hz (rising edge) 6.736 6.736 r + P20 0.000 6.736 r clk (port) + net (fanout=1) 0.074 6.810 clk + IOBS_LR_328_209/DIN td 1.285 8.095 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 8.095 clk_ibuf/ntD + IOL_327_210/INCK td 0.038 8.133 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.463 8.596 _N69 + PLL_158_55/CLK_OUT0 td 0.078 8.674 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.603 9.277 rd3_clk + USCM_84_154/CLK_USCM td 0.000 9.277 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.091 10.368 ntR3950 + PLL_158_303/CLK_OUT0 td 0.078 10.446 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 0.915 11.361 zoom_clk + USCM_84_118/CLK_USCM td 0.000 11.361 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 1.005 12.366 ntclkbufg_3 + DRM_306_292/CLKA[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/CLKA[0] + clock pessimism 0.332 12.698 + clock uncertainty -0.150 12.548 - Recovery time -0.088 8.574 + Recovery time -0.088 12.460 - Data required time 8.574 + Data required time 12.460 ---------------------------------------------------------------------------------------------------- - Data required time 8.574 - Data arrival time 6.285 + Data required time 12.460 + Data arrival time 8.132 ---------------------------------------------------------------------------------------------------- - Slack (MET) 2.289 + Slack (MET) 4.328 ==================================================================================================== ==================================================================================================== -Startpoint : u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK -Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/opit_0/RS -Path Group : clk_200m -Path Type : min (fast corner) +Startpoint : u_zoom_rst/rst/opit_0_L5Q_perm/CLK +Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[4].U_GTP_DRM18K/iGopDrm/RSTA[0] +Path Group : clk_1080p60Hz +Path Type : max (fast corner) Path Class : async timing path -Clock Skew : 0.037 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 3.732 - Launch Clock Delay : 3.432 - Clock Pessimism Removal : -0.263 +Clock Skew : 0.080 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 5.630 + Launch Clock Delay : 5.882 + Clock Pessimism Removal : 0.332 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_200m (rising edge) 0.000 0.000 r - P20 0.000 0.000 r clk (port) - net (fanout=1) 0.074 0.074 clk - IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O - net (fanout=1) 0.000 1.359 clk_ibuf/ntD - IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK - net (fanout=1) 0.463 1.860 _N69 - PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.603 2.537 zoom_clk - USCM_84_122/CLK_USCM td 0.000 2.537 r USCMROUTE_2/CLKOUT - net (fanout=759) 0.895 3.432 ntR3909 - CLMS_202_149/CLK r u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK - - CLMS_202_149/Q0 tco 0.179 3.611 f u_ddr_rst/rst/opit_0_inv_L5Q_perm/Q - net (fanout=2) 0.129 3.740 ddr_rst - CLMA_202_148/RS f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/opit_0/RS - - Data arrival time 3.740 Logic Levels: 0 - Logic: 0.179ns(58.117%), Route: 0.129ns(41.883%) ----------------------------------------------------------------------------------------------------- - - Clock clk_200m (rising edge) 0.000 0.000 r + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.578 clk_ibuf/ntD IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 - PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.614 2.807 zoom_clk - USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 0.925 3.732 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - CLMA_202_148/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/opit_0/CLK - clock pessimism -0.263 3.469 - clock uncertainty 0.000 3.469 + PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.614 2.811 rd3_clk + USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.131 3.942 ntR3950 + PLL_158_303/CLK_OUT0 td 0.083 4.025 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 0.932 4.957 zoom_clk + USCM_84_118/CLK_USCM td 0.000 4.957 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 0.925 5.882 ntclkbufg_3 + CLMA_170_124/CLK r u_zoom_rst/rst/opit_0_L5Q_perm/CLK + + CLMA_170_124/Q0 tco 0.221 6.103 f u_zoom_rst/rst/opit_0_L5Q_perm/Q + net (fanout=114) 1.973 8.076 zoom_rst + DRM_306_272/RSTA[0] f u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[4].U_GTP_DRM18K/iGopDrm/RSTA[0] + + Data arrival time 8.076 Logic Levels: 0 + Logic: 0.221ns(10.073%), Route: 1.973ns(89.927%) +---------------------------------------------------------------------------------------------------- - Removal time -0.181 3.288 + Clock clk_1080p60Hz (rising edge) 6.736 6.736 r + P20 0.000 6.736 r clk (port) + net (fanout=1) 0.074 6.810 clk + IOBS_LR_328_209/DIN td 1.285 8.095 r clk_ibuf/opit_0/O + net (fanout=1) 0.000 8.095 clk_ibuf/ntD + IOL_327_210/INCK td 0.038 8.133 r clk_ibuf/opit_1/INCK + net (fanout=1) 0.463 8.596 _N69 + PLL_158_55/CLK_OUT0 td 0.078 8.674 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.603 9.277 rd3_clk + USCM_84_154/CLK_USCM td 0.000 9.277 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.091 10.368 ntR3950 + PLL_158_303/CLK_OUT0 td 0.078 10.446 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 0.915 11.361 zoom_clk + USCM_84_118/CLK_USCM td 0.000 11.361 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 1.005 12.366 ntclkbufg_3 + DRM_306_272/CLKA[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[4].U_GTP_DRM18K/iGopDrm/CLKA[0] + clock pessimism 0.332 12.698 + clock uncertainty -0.150 12.548 - Data required time 3.288 + Recovery time -0.088 12.460 + + Data required time 12.460 ---------------------------------------------------------------------------------------------------- - Data required time 3.288 - Data arrival time 3.740 + Data required time 12.460 + Data arrival time 8.076 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.452 + Slack (MET) 4.384 ==================================================================================================== ==================================================================================================== -Startpoint : u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK -Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/RS -Path Group : clk_200m +Startpoint : u_zoom_rst/rst/opit_0_L5Q_perm/CLK +Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[6].U_GTP_DRM18K/iGopDrm/RSTA[0] +Path Group : clk_1080p60Hz Path Type : min (fast corner) Path Class : async timing path -Clock Skew : 0.037 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 3.732 - Launch Clock Delay : 3.432 - Clock Pessimism Removal : -0.263 +Clock Skew : 0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 5.882 + Launch Clock Delay : 5.520 + Clock Pessimism Removal : -0.332 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_200m (rising edge) 0.000 0.000 r + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.359 clk_ibuf/ntD IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK net (fanout=1) 0.463 1.860 _N69 - PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.603 2.537 zoom_clk - USCM_84_122/CLK_USCM td 0.000 2.537 r USCMROUTE_2/CLKOUT - net (fanout=759) 0.895 3.432 ntR3909 - CLMS_202_149/CLK r u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK + PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.603 2.541 rd3_clk + USCM_84_154/CLK_USCM td 0.000 2.541 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.091 3.632 ntR3950 + PLL_158_303/CLK_OUT0 td 0.078 3.710 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 0.915 4.625 zoom_clk + USCM_84_118/CLK_USCM td 0.000 4.625 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 0.895 5.520 ntclkbufg_3 + CLMA_170_124/CLK r u_zoom_rst/rst/opit_0_L5Q_perm/CLK - CLMS_202_149/Q0 tco 0.179 3.611 f u_ddr_rst/rst/opit_0_inv_L5Q_perm/Q - net (fanout=2) 0.129 3.740 ddr_rst - CLMA_202_148/RS f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/RS + CLMA_170_124/Q0 tco 0.182 5.702 r u_zoom_rst/rst/opit_0_L5Q_perm/Q + net (fanout=114) 0.648 6.350 zoom_rst + DRM_234_128/RSTA[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[6].U_GTP_DRM18K/iGopDrm/RSTA[0] - Data arrival time 3.740 Logic Levels: 0 - Logic: 0.179ns(58.117%), Route: 0.129ns(41.883%) + Data arrival time 6.350 Logic Levels: 0 + Logic: 0.182ns(21.928%), Route: 0.648ns(78.072%) ---------------------------------------------------------------------------------------------------- - Clock clk_200m (rising edge) 0.000 0.000 r + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.578 clk_ibuf/ntD IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 - PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.614 2.807 zoom_clk - USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 0.925 3.732 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - CLMA_202_148/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK - clock pessimism -0.263 3.469 - clock uncertainty 0.000 3.469 + PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.614 2.811 rd3_clk + USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.131 3.942 ntR3950 + PLL_158_303/CLK_OUT0 td 0.083 4.025 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 0.932 4.957 zoom_clk + USCM_84_118/CLK_USCM td 0.000 4.957 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 0.925 5.882 ntclkbufg_3 + DRM_234_128/CLKA[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[6].U_GTP_DRM18K/iGopDrm/CLKA[0] + clock pessimism -0.332 5.550 + clock uncertainty 0.000 5.550 - Removal time -0.181 3.288 + Removal time -0.060 5.490 - Data required time 3.288 + Data required time 5.490 ---------------------------------------------------------------------------------------------------- - Data required time 3.288 - Data arrival time 3.740 + Data required time 5.490 + Data arrival time 6.350 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.452 + Slack (MET) 0.860 ==================================================================================================== ==================================================================================================== -Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q_perm/CLK -Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[0]/opit_0_inv/RS -Path Group : clk_200m +Startpoint : u_zoom_rst/rst/opit_0_L5Q_perm/CLK +Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/RSTA[0] +Path Group : clk_1080p60Hz Path Type : min (fast corner) Path Class : async timing path Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 3.732 - Launch Clock Delay : 3.432 - Clock Pessimism Removal : -0.281 + Capture Clock Delay : 5.882 + Launch Clock Delay : 5.520 + Clock Pessimism Removal : -0.343 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_200m (rising edge) 0.000 0.000 r + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.359 clk_ibuf/ntD IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK net (fanout=1) 0.463 1.860 _N69 - PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.603 2.537 zoom_clk - USCM_84_113/CLK_USCM td 0.000 2.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 0.895 3.432 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - CLMS_78_181/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q_perm/CLK - - CLMS_78_181/Q0 tco 0.182 3.614 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q_perm/Q - net (fanout=14) 0.278 3.892 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/logic_rstn - CLMS_62_181/RSCO td 0.092 3.984 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/pll_lock_d[1]/opit_0_inv/RSOUT - net (fanout=4) 0.000 3.984 ntR1581 - CLMS_62_185/RSCI f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[0]/opit_0_inv/RS - - Data arrival time 3.984 Logic Levels: 1 - Logic: 0.274ns(49.638%), Route: 0.278ns(50.362%) ----------------------------------------------------------------------------------------------------- - - Clock clk_200m (rising edge) 0.000 0.000 r - P20 0.000 0.000 r clk (port) - net (fanout=1) 0.074 0.074 clk - IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O - net (fanout=1) 0.000 1.578 clk_ibuf/ntD - IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK - net (fanout=1) 0.478 2.114 _N69 - PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.614 2.807 zoom_clk - USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 0.925 3.732 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - CLMS_62_185/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[0]/opit_0_inv/CLK - clock pessimism -0.281 3.451 - clock uncertainty 0.000 3.451 - - Removal time 0.000 3.451 - - Data required time 3.451 ----------------------------------------------------------------------------------------------------- - Data required time 3.451 - Data arrival time 3.984 ----------------------------------------------------------------------------------------------------- - Slack (MET) 0.533 -==================================================================================================== - -==================================================================================================== + PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.603 2.541 rd3_clk + USCM_84_154/CLK_USCM td 0.000 2.541 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.091 3.632 ntR3950 + PLL_158_303/CLK_OUT0 td 0.078 3.710 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 0.915 4.625 zoom_clk + USCM_84_118/CLK_USCM td 0.000 4.625 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 0.895 5.520 ntclkbufg_3 + CLMA_170_124/CLK r u_zoom_rst/rst/opit_0_L5Q_perm/CLK -Startpoint : rstn_out1/opit_0_inv/CLK -Endpoint : ms72xx_ctl/rstn_temp1/opit_0_inv/RS -Path Group : clk_10m -Path Type : max (fast corner) -Path Class : async timing path -Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 3.437 - Launch Clock Delay : 3.737 - Clock Pessimism Removal : 0.281 + CLMA_170_124/Q0 tco 0.182 5.702 r u_zoom_rst/rst/opit_0_L5Q_perm/Q + net (fanout=114) 0.689 6.391 zoom_rst + DRM_234_88/RSTA[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/RSTA[0] - Location Delay Type Incr Path Logical Resource + Data arrival time 6.391 Logic Levels: 0 + Logic: 0.182ns(20.896%), Route: 0.689ns(79.104%) ---------------------------------------------------------------------------------------------------- - Clock clk_10m (rising edge) 0.000 0.000 r + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.578 clk_ibuf/ntD IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 - PLL_158_55/CLK_OUT4 td 0.084 2.198 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 - net (fanout=1) 0.614 2.812 clk_10m - USCM_84_110/CLK_USCM td 0.000 2.812 r clkbufg_3/gopclkbufg/CLKOUT - net (fanout=235) 0.925 3.737 ntclkbufg_3 - CLMA_230_69/CLK r rstn_out1/opit_0_inv/CLK - - CLMA_230_69/Q3 tco 0.220 3.957 f rstn_out1/opit_0_inv/Q - net (fanout=3) 0.776 4.733 nt_eth_rstn - CLMA_246_120/RS f ms72xx_ctl/rstn_temp1/opit_0_inv/RS - - Data arrival time 4.733 Logic Levels: 0 - Logic: 0.220ns(22.088%), Route: 0.776ns(77.912%) ----------------------------------------------------------------------------------------------------- - - Clock clk_10m (rising edge) 100.000 100.000 r - P20 0.000 100.000 r clk (port) - net (fanout=1) 0.074 100.074 clk - IOBS_LR_328_209/DIN td 1.285 101.359 r clk_ibuf/opit_0/O - net (fanout=1) 0.000 101.359 clk_ibuf/ntD - IOL_327_210/INCK td 0.038 101.397 r clk_ibuf/opit_1/INCK - net (fanout=1) 0.463 101.860 _N69 - PLL_158_55/CLK_OUT4 td 0.079 101.939 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 - net (fanout=1) 0.603 102.542 clk_10m - USCM_84_110/CLK_USCM td 0.000 102.542 r clkbufg_3/gopclkbufg/CLKOUT - net (fanout=235) 0.895 103.437 ntclkbufg_3 - CLMA_246_120/CLK r ms72xx_ctl/rstn_temp1/opit_0_inv/CLK - clock pessimism 0.281 103.718 - clock uncertainty -0.150 103.568 + PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.614 2.811 rd3_clk + USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.131 3.942 ntR3950 + PLL_158_303/CLK_OUT0 td 0.083 4.025 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 0.932 4.957 zoom_clk + USCM_84_118/CLK_USCM td 0.000 4.957 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 0.925 5.882 ntclkbufg_3 + DRM_234_88/CLKA[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] + clock pessimism -0.343 5.539 + clock uncertainty 0.000 5.539 - Recovery time -0.476 103.092 + Removal time -0.060 5.479 - Data required time 103.092 + Data required time 5.479 ---------------------------------------------------------------------------------------------------- - Data required time 103.092 - Data arrival time 4.733 + Data required time 5.479 + Data arrival time 6.391 ---------------------------------------------------------------------------------------------------- - Slack (MET) 98.359 + Slack (MET) 0.912 ==================================================================================================== ==================================================================================================== -Startpoint : rstn_out1/opit_0_inv/CLK -Endpoint : ms72xx_ctl/rstn_temp1/opit_0_inv/RS -Path Group : clk_10m +Startpoint : u_zoom_rst/rst/opit_0_L5Q_perm/CLK +Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[7].U_GTP_DRM18K/iGopDrm/RSTA[0] +Path Group : clk_1080p60Hz Path Type : min (fast corner) Path Class : async timing path Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 3.737 - Launch Clock Delay : 3.437 - Clock Pessimism Removal : -0.281 + Capture Clock Delay : 5.882 + Launch Clock Delay : 5.520 + Clock Pessimism Removal : -0.343 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_10m (rising edge) 0.000 0.000 r + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.285 1.359 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.359 clk_ibuf/ntD IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK net (fanout=1) 0.463 1.860 _N69 - PLL_158_55/CLK_OUT4 td 0.079 1.939 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 - net (fanout=1) 0.603 2.542 clk_10m - USCM_84_110/CLK_USCM td 0.000 2.542 r clkbufg_3/gopclkbufg/CLKOUT - net (fanout=235) 0.895 3.437 ntclkbufg_3 - CLMA_230_69/CLK r rstn_out1/opit_0_inv/CLK + PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.603 2.541 rd3_clk + USCM_84_154/CLK_USCM td 0.000 2.541 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.091 3.632 ntR3950 + PLL_158_303/CLK_OUT0 td 0.078 3.710 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 0.915 4.625 zoom_clk + USCM_84_118/CLK_USCM td 0.000 4.625 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 0.895 5.520 ntclkbufg_3 + CLMA_170_124/CLK r u_zoom_rst/rst/opit_0_L5Q_perm/CLK - CLMA_230_69/Q3 tco 0.182 3.619 r rstn_out1/opit_0_inv/Q - net (fanout=3) 0.565 4.184 nt_eth_rstn - CLMA_246_120/RS r ms72xx_ctl/rstn_temp1/opit_0_inv/RS + CLMA_170_124/Q0 tco 0.182 5.702 r u_zoom_rst/rst/opit_0_L5Q_perm/Q + net (fanout=114) 0.722 6.424 zoom_rst + DRM_234_108/RSTA[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[7].U_GTP_DRM18K/iGopDrm/RSTA[0] - Data arrival time 4.184 Logic Levels: 0 - Logic: 0.182ns(24.364%), Route: 0.565ns(75.636%) + Data arrival time 6.424 Logic Levels: 0 + Logic: 0.182ns(20.133%), Route: 0.722ns(79.867%) ---------------------------------------------------------------------------------------------------- - Clock clk_10m (rising edge) 0.000 0.000 r + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r P20 0.000 0.000 r clk (port) net (fanout=1) 0.074 0.074 clk IOBS_LR_328_209/DIN td 1.504 1.578 r clk_ibuf/opit_0/O net (fanout=1) 0.000 1.578 clk_ibuf/ntD IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 - PLL_158_55/CLK_OUT4 td 0.084 2.198 r u_sys_pll/u_pll_e3/goppll/CLKOUT4 - net (fanout=1) 0.614 2.812 clk_10m - USCM_84_110/CLK_USCM td 0.000 2.812 r clkbufg_3/gopclkbufg/CLKOUT - net (fanout=235) 0.925 3.737 ntclkbufg_3 - CLMA_246_120/CLK r ms72xx_ctl/rstn_temp1/opit_0_inv/CLK - clock pessimism -0.281 3.456 - clock uncertainty 0.000 3.456 + PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 + net (fanout=2) 0.614 2.811 rd3_clk + USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT + net (fanout=1) 1.131 3.942 ntR3950 + PLL_158_303/CLK_OUT0 td 0.083 4.025 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + net (fanout=1) 0.932 4.957 zoom_clk + USCM_84_118/CLK_USCM td 0.000 4.957 r clkbufg_3/gopclkbufg/CLKOUT + net (fanout=750) 0.925 5.882 ntclkbufg_3 + DRM_234_108/CLKA[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[7].U_GTP_DRM18K/iGopDrm/CLKA[0] + clock pessimism -0.343 5.539 + clock uncertainty 0.000 5.539 - Removal time -0.187 3.269 + Removal time -0.060 5.479 - Data required time 3.269 + Data required time 5.479 ---------------------------------------------------------------------------------------------------- - Data required time 3.269 - Data arrival time 4.184 + Data required time 5.479 + Data arrival time 6.424 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.915 + Slack (MET) 0.945 ==================================================================================================== ==================================================================================================== Startpoint : sync_vg_100m/opit_0_inv_L5Q_perm/CLK -Endpoint : adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[4]/opit_0_L5Q_perm/RS +Endpoint : udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0/RS Path Group : clk_720p60Hz Path Type : max (fast corner) Path Class : async timing path -Clock Skew : -0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.516 - Launch Clock Delay : 5.878 +Clock Skew : -0.032 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 5.626 + Launch Clock Delay : 5.990 Clock Pessimism Removal : 0.332 Location Delay Type Incr Path Logical Resource @@ -14021,39 +15647,47 @@ Clock Skew : -0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessi PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 0.614 2.811 rd3_clk USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.131 3.942 ntR3907 + net (fanout=1) 1.131 3.942 ntR3950 PLL_158_303/CLK_OUT1 td 0.079 4.021 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 net (fanout=2) 0.932 4.953 nt_pix_clk USCM_84_117/CLK_USCM td 0.000 4.953 r clkbufg_2/gopclkbufg/CLKOUT - net (fanout=1635) 0.925 5.878 ntclkbufg_2 - CLMS_150_245/CLK r sync_vg_100m/opit_0_inv_L5Q_perm/CLK - - CLMS_150_245/Q0 tco 0.221 6.099 f sync_vg_100m/opit_0_inv_L5Q_perm/Q - net (fanout=1066) 2.027 8.126 sync_vg_100m - CLMA_294_132/RSCO td 0.113 8.239 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/remainder[3]/opit_0_L5Q_perm/RSOUT - net (fanout=4) 0.000 8.239 ntR491 - CLMA_294_136/RSCO td 0.113 8.352 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm/RSOUT - net (fanout=4) 0.000 8.352 ntR490 - CLMA_294_140/RSCO td 0.113 8.465 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[2]/opit_0_L5Q_perm/RSOUT - net (fanout=1) 0.000 8.465 ntR489 - CLMA_294_144/RSCO td 0.113 8.578 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/remainder[2]/opit_0_A2Q21/RSOUT - net (fanout=2) 0.000 8.578 ntR488 - CLMA_294_148/RSCO td 0.113 8.691 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/remainder[6]/opit_0_A2Q21/RSOUT - net (fanout=4) 0.000 8.691 ntR487 - CLMA_294_152/RSCO td 0.113 8.804 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm/RSOUT - net (fanout=4) 0.000 8.804 ntR486 - CLMA_294_156/RSCO td 0.113 8.917 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/dividend_kp[11]/opit_0_L5Q_perm/RSOUT - net (fanout=4) 0.000 8.917 ntR485 - CLMA_294_160/RSCO td 0.113 9.030 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[2]/opit_0_L5Q_perm/RSOUT - net (fanout=2) 0.000 9.030 ntR484 - CLMA_294_164/RSCO td 0.113 9.143 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[2]/opit_0_A2Q21/RSOUT - net (fanout=2) 0.000 9.143 ntR483 - CLMA_294_168/RSCO td 0.113 9.256 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[6]/opit_0_A2Q21/RSOUT - net (fanout=4) 0.000 9.256 ntR482 - CLMA_294_172/RSCI f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[4]/opit_0_L5Q_perm/RS - - Data arrival time 9.256 Logic Levels: 10 - Logic: 1.351ns(39.994%), Route: 2.027ns(60.006%) + net (fanout=1635) 1.037 5.990 ntclkbufg_2 + CLMA_150_276/CLK r sync_vg_100m/opit_0_inv_L5Q_perm/CLK + + CLMA_150_276/Q0 tco 0.221 6.211 f sync_vg_100m/opit_0_inv_L5Q_perm/Q + net (fanout=911) 1.365 7.576 sync_vg_100m + CLMA_190_240/RSCO td 0.113 7.689 f udp_wr_mem_inst/mem[39]/opit_0/RSOUT + net (fanout=3) 0.000 7.689 ntR687 + CLMA_190_244/RSCO td 0.113 7.802 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[4]/opit_0/RSOUT + net (fanout=4) 0.000 7.802 ntR686 + CLMA_190_248/RSCO td 0.113 7.915 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[40]/opit_0_L5Q_perm/RSOUT + net (fanout=2) 0.000 7.915 ntR685 + CLMA_190_252/RSCO td 0.113 8.028 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[7]/opit_0/RSOUT + net (fanout=6) 0.000 8.028 ntR684 + CLMA_190_256/RSCO td 0.113 8.141 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[7]/opit_0/RSOUT + net (fanout=5) 0.000 8.141 ntR683 + CLMA_190_260/RSCO td 0.113 8.254 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[27]/opit_0_L5Q_perm/RSOUT + net (fanout=6) 0.000 8.254 ntR682 + CLMA_190_264/RSCO td 0.113 8.367 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[22]/opit_0/RSOUT + net (fanout=4) 0.000 8.367 ntR681 + CLMA_190_268/RSCO td 0.113 8.480 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[30]/opit_0_L5Q_perm/RSOUT + net (fanout=4) 0.000 8.480 ntR680 + CLMA_190_272/RSCO td 0.113 8.593 f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[4]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=4) 0.000 8.593 ntR679 + CLMA_190_276/RSCO td 0.113 8.706 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[23]/opit_0/RSOUT + net (fanout=4) 0.000 8.706 ntR678 + CLMA_190_280/RSCO td 0.113 8.819 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][1]/opit_0/RSOUT + net (fanout=4) 0.000 8.819 ntR677 + CLMA_190_284/RSCO td 0.113 8.932 f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/RSOUT + net (fanout=6) 0.000 8.932 ntR676 + CLMA_190_288/RSCO td 0.113 9.045 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[29]/opit_0/RSOUT + net (fanout=1) 0.000 9.045 ntR675 + CLMA_190_292/RSCO td 0.113 9.158 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][1]/opit_0/RSOUT + net (fanout=6) 0.000 9.158 ntR674 + CLMA_190_296/RSCI f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0/RS + + Data arrival time 9.158 Logic Levels: 14 + Logic: 1.803ns(56.913%), Route: 1.365ns(43.087%) ---------------------------------------------------------------------------------------------------- Clock clk_720p60Hz (rising edge) 13.473 13.473 r @@ -14066,35 +15700,35 @@ Clock Skew : -0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessi PLL_158_55/CLK_OUT0 td 0.078 15.411 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 0.603 16.014 rd3_clk USCM_84_154/CLK_USCM td 0.000 16.014 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.091 17.105 ntR3907 + net (fanout=1) 1.091 17.105 ntR3950 PLL_158_303/CLK_OUT1 td 0.074 17.179 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 net (fanout=2) 0.915 18.094 nt_pix_clk USCM_84_117/CLK_USCM td 0.000 18.094 r clkbufg_2/gopclkbufg/CLKOUT - net (fanout=1635) 0.895 18.989 ntclkbufg_2 - CLMA_294_172/CLK r adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[4]/opit_0_L5Q_perm/CLK - clock pessimism 0.332 19.321 - clock uncertainty -0.150 19.171 + net (fanout=1635) 1.005 19.099 ntclkbufg_2 + CLMA_190_296/CLK r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0/CLK + clock pessimism 0.332 19.431 + clock uncertainty -0.150 19.281 - Recovery time 0.000 19.171 + Recovery time 0.000 19.281 - Data required time 19.171 + Data required time 19.281 ---------------------------------------------------------------------------------------------------- - Data required time 19.171 - Data arrival time 9.256 + Data required time 19.281 + Data arrival time 9.158 ---------------------------------------------------------------------------------------------------- - Slack (MET) 9.915 + Slack (MET) 10.123 ==================================================================================================== ==================================================================================================== Startpoint : sync_vg_100m/opit_0_inv_L5Q_perm/CLK -Endpoint : adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[6]/opit_0_L5Q_perm/RS +Endpoint : udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/opit_0/RS Path Group : clk_720p60Hz Path Type : max (fast corner) Path Class : async timing path -Clock Skew : -0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.516 - Launch Clock Delay : 5.878 +Clock Skew : -0.032 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 5.626 + Launch Clock Delay : 5.990 Clock Pessimism Removal : 0.332 Location Delay Type Incr Path Logical Resource @@ -14110,39 +15744,47 @@ Clock Skew : -0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessi PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 0.614 2.811 rd3_clk USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.131 3.942 ntR3907 + net (fanout=1) 1.131 3.942 ntR3950 PLL_158_303/CLK_OUT1 td 0.079 4.021 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 net (fanout=2) 0.932 4.953 nt_pix_clk USCM_84_117/CLK_USCM td 0.000 4.953 r clkbufg_2/gopclkbufg/CLKOUT - net (fanout=1635) 0.925 5.878 ntclkbufg_2 - CLMS_150_245/CLK r sync_vg_100m/opit_0_inv_L5Q_perm/CLK - - CLMS_150_245/Q0 tco 0.221 6.099 f sync_vg_100m/opit_0_inv_L5Q_perm/Q - net (fanout=1066) 2.027 8.126 sync_vg_100m - CLMA_294_132/RSCO td 0.113 8.239 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/remainder[3]/opit_0_L5Q_perm/RSOUT - net (fanout=4) 0.000 8.239 ntR491 - CLMA_294_136/RSCO td 0.113 8.352 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm/RSOUT - net (fanout=4) 0.000 8.352 ntR490 - CLMA_294_140/RSCO td 0.113 8.465 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[2]/opit_0_L5Q_perm/RSOUT - net (fanout=1) 0.000 8.465 ntR489 - CLMA_294_144/RSCO td 0.113 8.578 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/remainder[2]/opit_0_A2Q21/RSOUT - net (fanout=2) 0.000 8.578 ntR488 - CLMA_294_148/RSCO td 0.113 8.691 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/remainder[6]/opit_0_A2Q21/RSOUT - net (fanout=4) 0.000 8.691 ntR487 - CLMA_294_152/RSCO td 0.113 8.804 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm/RSOUT - net (fanout=4) 0.000 8.804 ntR486 - CLMA_294_156/RSCO td 0.113 8.917 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/dividend_kp[11]/opit_0_L5Q_perm/RSOUT - net (fanout=4) 0.000 8.917 ntR485 - CLMA_294_160/RSCO td 0.113 9.030 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[2]/opit_0_L5Q_perm/RSOUT - net (fanout=2) 0.000 9.030 ntR484 - CLMA_294_164/RSCO td 0.113 9.143 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[2]/opit_0_A2Q21/RSOUT - net (fanout=2) 0.000 9.143 ntR483 - CLMA_294_168/RSCO td 0.113 9.256 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[6]/opit_0_A2Q21/RSOUT - net (fanout=4) 0.000 9.256 ntR482 - CLMA_294_172/RSCI f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[6]/opit_0_L5Q_perm/RS - - Data arrival time 9.256 Logic Levels: 10 - Logic: 1.351ns(39.994%), Route: 2.027ns(60.006%) + net (fanout=1635) 1.037 5.990 ntclkbufg_2 + CLMA_150_276/CLK r sync_vg_100m/opit_0_inv_L5Q_perm/CLK + + CLMA_150_276/Q0 tco 0.221 6.211 f sync_vg_100m/opit_0_inv_L5Q_perm/Q + net (fanout=911) 1.365 7.576 sync_vg_100m + CLMA_190_240/RSCO td 0.113 7.689 f udp_wr_mem_inst/mem[39]/opit_0/RSOUT + net (fanout=3) 0.000 7.689 ntR687 + CLMA_190_244/RSCO td 0.113 7.802 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[4]/opit_0/RSOUT + net (fanout=4) 0.000 7.802 ntR686 + CLMA_190_248/RSCO td 0.113 7.915 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[40]/opit_0_L5Q_perm/RSOUT + net (fanout=2) 0.000 7.915 ntR685 + CLMA_190_252/RSCO td 0.113 8.028 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[7]/opit_0/RSOUT + net (fanout=6) 0.000 8.028 ntR684 + CLMA_190_256/RSCO td 0.113 8.141 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[7]/opit_0/RSOUT + net (fanout=5) 0.000 8.141 ntR683 + CLMA_190_260/RSCO td 0.113 8.254 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[27]/opit_0_L5Q_perm/RSOUT + net (fanout=6) 0.000 8.254 ntR682 + CLMA_190_264/RSCO td 0.113 8.367 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[22]/opit_0/RSOUT + net (fanout=4) 0.000 8.367 ntR681 + CLMA_190_268/RSCO td 0.113 8.480 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[30]/opit_0_L5Q_perm/RSOUT + net (fanout=4) 0.000 8.480 ntR680 + CLMA_190_272/RSCO td 0.113 8.593 f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[4]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=4) 0.000 8.593 ntR679 + CLMA_190_276/RSCO td 0.113 8.706 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[23]/opit_0/RSOUT + net (fanout=4) 0.000 8.706 ntR678 + CLMA_190_280/RSCO td 0.113 8.819 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][1]/opit_0/RSOUT + net (fanout=4) 0.000 8.819 ntR677 + CLMA_190_284/RSCO td 0.113 8.932 f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/RSOUT + net (fanout=6) 0.000 8.932 ntR676 + CLMA_190_288/RSCO td 0.113 9.045 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[29]/opit_0/RSOUT + net (fanout=1) 0.000 9.045 ntR675 + CLMA_190_292/RSCO td 0.113 9.158 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][1]/opit_0/RSOUT + net (fanout=6) 0.000 9.158 ntR674 + CLMA_190_296/RSCI f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/opit_0/RS + + Data arrival time 9.158 Logic Levels: 14 + Logic: 1.803ns(56.913%), Route: 1.365ns(43.087%) ---------------------------------------------------------------------------------------------------- Clock clk_720p60Hz (rising edge) 13.473 13.473 r @@ -14155,35 +15797,35 @@ Clock Skew : -0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessi PLL_158_55/CLK_OUT0 td 0.078 15.411 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 0.603 16.014 rd3_clk USCM_84_154/CLK_USCM td 0.000 16.014 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.091 17.105 ntR3907 + net (fanout=1) 1.091 17.105 ntR3950 PLL_158_303/CLK_OUT1 td 0.074 17.179 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 net (fanout=2) 0.915 18.094 nt_pix_clk USCM_84_117/CLK_USCM td 0.000 18.094 r clkbufg_2/gopclkbufg/CLKOUT - net (fanout=1635) 0.895 18.989 ntclkbufg_2 - CLMA_294_172/CLK r adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[6]/opit_0_L5Q_perm/CLK - clock pessimism 0.332 19.321 - clock uncertainty -0.150 19.171 + net (fanout=1635) 1.005 19.099 ntclkbufg_2 + CLMA_190_296/CLK r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/opit_0/CLK + clock pessimism 0.332 19.431 + clock uncertainty -0.150 19.281 - Recovery time 0.000 19.171 + Recovery time 0.000 19.281 - Data required time 19.171 + Data required time 19.281 ---------------------------------------------------------------------------------------------------- - Data required time 19.171 - Data arrival time 9.256 + Data required time 19.281 + Data arrival time 9.158 ---------------------------------------------------------------------------------------------------- - Slack (MET) 9.915 + Slack (MET) 10.123 ==================================================================================================== ==================================================================================================== Startpoint : sync_vg_100m/opit_0_inv_L5Q_perm/CLK -Endpoint : adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[7]/opit_0_L5Q_perm/RS +Endpoint : udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/RS Path Group : clk_720p60Hz Path Type : max (fast corner) Path Class : async timing path -Clock Skew : -0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.516 - Launch Clock Delay : 5.878 +Clock Skew : -0.032 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 5.626 + Launch Clock Delay : 5.990 Clock Pessimism Removal : 0.332 Location Delay Type Incr Path Logical Resource @@ -14199,39 +15841,47 @@ Clock Skew : -0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessi PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 0.614 2.811 rd3_clk USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.131 3.942 ntR3907 + net (fanout=1) 1.131 3.942 ntR3950 PLL_158_303/CLK_OUT1 td 0.079 4.021 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 net (fanout=2) 0.932 4.953 nt_pix_clk USCM_84_117/CLK_USCM td 0.000 4.953 r clkbufg_2/gopclkbufg/CLKOUT - net (fanout=1635) 0.925 5.878 ntclkbufg_2 - CLMS_150_245/CLK r sync_vg_100m/opit_0_inv_L5Q_perm/CLK - - CLMS_150_245/Q0 tco 0.221 6.099 f sync_vg_100m/opit_0_inv_L5Q_perm/Q - net (fanout=1066) 2.027 8.126 sync_vg_100m - CLMA_294_132/RSCO td 0.113 8.239 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/remainder[3]/opit_0_L5Q_perm/RSOUT - net (fanout=4) 0.000 8.239 ntR491 - CLMA_294_136/RSCO td 0.113 8.352 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm/RSOUT - net (fanout=4) 0.000 8.352 ntR490 - CLMA_294_140/RSCO td 0.113 8.465 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[2]/opit_0_L5Q_perm/RSOUT - net (fanout=1) 0.000 8.465 ntR489 - CLMA_294_144/RSCO td 0.113 8.578 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/remainder[2]/opit_0_A2Q21/RSOUT - net (fanout=2) 0.000 8.578 ntR488 - CLMA_294_148/RSCO td 0.113 8.691 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/remainder[6]/opit_0_A2Q21/RSOUT - net (fanout=4) 0.000 8.691 ntR487 - CLMA_294_152/RSCO td 0.113 8.804 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm/RSOUT - net (fanout=4) 0.000 8.804 ntR486 - CLMA_294_156/RSCO td 0.113 8.917 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/dividend_kp[11]/opit_0_L5Q_perm/RSOUT - net (fanout=4) 0.000 8.917 ntR485 - CLMA_294_160/RSCO td 0.113 9.030 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[2]/opit_0_L5Q_perm/RSOUT - net (fanout=2) 0.000 9.030 ntR484 - CLMA_294_164/RSCO td 0.113 9.143 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[2]/opit_0_A2Q21/RSOUT - net (fanout=2) 0.000 9.143 ntR483 - CLMA_294_168/RSCO td 0.113 9.256 f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[6]/opit_0_A2Q21/RSOUT - net (fanout=4) 0.000 9.256 ntR482 - CLMA_294_172/RSCI f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[7]/opit_0_L5Q_perm/RS - - Data arrival time 9.256 Logic Levels: 10 - Logic: 1.351ns(39.994%), Route: 2.027ns(60.006%) + net (fanout=1635) 1.037 5.990 ntclkbufg_2 + CLMA_150_276/CLK r sync_vg_100m/opit_0_inv_L5Q_perm/CLK + + CLMA_150_276/Q0 tco 0.221 6.211 f sync_vg_100m/opit_0_inv_L5Q_perm/Q + net (fanout=911) 1.365 7.576 sync_vg_100m + CLMA_190_240/RSCO td 0.113 7.689 f udp_wr_mem_inst/mem[39]/opit_0/RSOUT + net (fanout=3) 0.000 7.689 ntR687 + CLMA_190_244/RSCO td 0.113 7.802 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[4]/opit_0/RSOUT + net (fanout=4) 0.000 7.802 ntR686 + CLMA_190_248/RSCO td 0.113 7.915 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[40]/opit_0_L5Q_perm/RSOUT + net (fanout=2) 0.000 7.915 ntR685 + CLMA_190_252/RSCO td 0.113 8.028 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[7]/opit_0/RSOUT + net (fanout=6) 0.000 8.028 ntR684 + CLMA_190_256/RSCO td 0.113 8.141 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[7]/opit_0/RSOUT + net (fanout=5) 0.000 8.141 ntR683 + CLMA_190_260/RSCO td 0.113 8.254 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[27]/opit_0_L5Q_perm/RSOUT + net (fanout=6) 0.000 8.254 ntR682 + CLMA_190_264/RSCO td 0.113 8.367 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[22]/opit_0/RSOUT + net (fanout=4) 0.000 8.367 ntR681 + CLMA_190_268/RSCO td 0.113 8.480 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[30]/opit_0_L5Q_perm/RSOUT + net (fanout=4) 0.000 8.480 ntR680 + CLMA_190_272/RSCO td 0.113 8.593 f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[4]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=4) 0.000 8.593 ntR679 + CLMA_190_276/RSCO td 0.113 8.706 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[23]/opit_0/RSOUT + net (fanout=4) 0.000 8.706 ntR678 + CLMA_190_280/RSCO td 0.113 8.819 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][1]/opit_0/RSOUT + net (fanout=4) 0.000 8.819 ntR677 + CLMA_190_284/RSCO td 0.113 8.932 f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/RSOUT + net (fanout=6) 0.000 8.932 ntR676 + CLMA_190_288/RSCO td 0.113 9.045 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[29]/opit_0/RSOUT + net (fanout=1) 0.000 9.045 ntR675 + CLMA_190_292/RSCO td 0.113 9.158 f udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][1]/opit_0/RSOUT + net (fanout=6) 0.000 9.158 ntR674 + CLMA_190_296/RSCI f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/RS + + Data arrival time 9.158 Logic Levels: 14 + Logic: 1.803ns(56.913%), Route: 1.365ns(43.087%) ---------------------------------------------------------------------------------------------------- Clock clk_720p60Hz (rising edge) 13.473 13.473 r @@ -14244,36 +15894,36 @@ Clock Skew : -0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessi PLL_158_55/CLK_OUT0 td 0.078 15.411 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 0.603 16.014 rd3_clk USCM_84_154/CLK_USCM td 0.000 16.014 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.091 17.105 ntR3907 + net (fanout=1) 1.091 17.105 ntR3950 PLL_158_303/CLK_OUT1 td 0.074 17.179 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 net (fanout=2) 0.915 18.094 nt_pix_clk USCM_84_117/CLK_USCM td 0.000 18.094 r clkbufg_2/gopclkbufg/CLKOUT - net (fanout=1635) 0.895 18.989 ntclkbufg_2 - CLMA_294_172/CLK r adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[7]/opit_0_L5Q_perm/CLK - clock pessimism 0.332 19.321 - clock uncertainty -0.150 19.171 + net (fanout=1635) 1.005 19.099 ntclkbufg_2 + CLMA_190_296/CLK r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/CLK + clock pessimism 0.332 19.431 + clock uncertainty -0.150 19.281 - Recovery time 0.000 19.171 + Recovery time 0.000 19.281 - Data required time 19.171 + Data required time 19.281 ---------------------------------------------------------------------------------------------------- - Data required time 19.171 - Data arrival time 9.256 + Data required time 19.281 + Data arrival time 9.158 ---------------------------------------------------------------------------------------------------- - Slack (MET) 9.915 + Slack (MET) 10.123 ==================================================================================================== ==================================================================================================== -Startpoint : u_hdmi_rst/rst/opit_0_L5Q_perm/CLK -Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[12].U_GTP_DRM18K/iGopDrm/RSTB[0] +Startpoint : sync_vg_100m/opit_0_inv_L5Q_perm/CLK +Endpoint : udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0] Path Group : clk_720p60Hz Path Type : min (fast corner) Path Class : async timing path -Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.878 - Launch Clock Delay : 5.516 - Clock Pessimism Removal : -0.343 +Clock Skew : 0.032 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 5.990 + Launch Clock Delay : 5.626 + Clock Pessimism Removal : -0.332 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -14288,19 +15938,19 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 0.603 2.541 rd3_clk USCM_84_154/CLK_USCM td 0.000 2.541 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.091 3.632 ntR3907 + net (fanout=1) 1.091 3.632 ntR3950 PLL_158_303/CLK_OUT1 td 0.074 3.706 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 net (fanout=2) 0.915 4.621 nt_pix_clk USCM_84_117/CLK_USCM td 0.000 4.621 r clkbufg_2/gopclkbufg/CLKOUT - net (fanout=1635) 0.895 5.516 ntclkbufg_2 - CLMA_190_124/CLK r u_hdmi_rst/rst/opit_0_L5Q_perm/CLK + net (fanout=1635) 1.005 5.626 ntclkbufg_2 + CLMA_150_276/CLK r sync_vg_100m/opit_0_inv_L5Q_perm/CLK - CLMA_190_124/Q0 tco 0.182 5.698 r u_hdmi_rst/rst/opit_0_L5Q_perm/Q - net (fanout=163) 0.625 6.323 rd2_rst - DRM_234_88/RSTB[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[12].U_GTP_DRM18K/iGopDrm/RSTB[0] + CLMA_150_276/Q0 tco 0.182 5.808 r sync_vg_100m/opit_0_inv_L5Q_perm/Q + net (fanout=911) 0.509 6.317 sync_vg_100m + DRM_178_272/RSTB[0] r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0] - Data arrival time 6.323 Logic Levels: 0 - Logic: 0.182ns(22.553%), Route: 0.625ns(77.447%) + Data arrival time 6.317 Logic Levels: 0 + Logic: 0.182ns(26.339%), Route: 0.509ns(73.661%) ---------------------------------------------------------------------------------------------------- Clock clk_720p60Hz (rising edge) 0.000 0.000 r @@ -14313,35 +15963,35 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 0.614 2.811 rd3_clk USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.131 3.942 ntR3907 + net (fanout=1) 1.131 3.942 ntR3950 PLL_158_303/CLK_OUT1 td 0.079 4.021 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 net (fanout=2) 0.932 4.953 nt_pix_clk USCM_84_117/CLK_USCM td 0.000 4.953 r clkbufg_2/gopclkbufg/CLKOUT - net (fanout=1635) 0.925 5.878 ntclkbufg_2 - DRM_234_88/CLKB[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[12].U_GTP_DRM18K/iGopDrm/CLKB[0] - clock pessimism -0.343 5.535 - clock uncertainty 0.000 5.535 + net (fanout=1635) 1.037 5.990 ntclkbufg_2 + DRM_178_272/CLKB[0] r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] + clock pessimism -0.332 5.658 + clock uncertainty 0.000 5.658 - Removal time -0.063 5.472 + Removal time -0.063 5.595 - Data required time 5.472 + Data required time 5.595 ---------------------------------------------------------------------------------------------------- - Data required time 5.472 - Data arrival time 6.323 + Data required time 5.595 + Data arrival time 6.317 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.851 + Slack (MET) 0.722 ==================================================================================================== ==================================================================================================== -Startpoint : u_hdmi_rst/rst/opit_0_L5Q_perm/CLK -Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0] +Startpoint : sync_vg_100m/opit_0_inv_L5Q_perm/CLK +Endpoint : udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/RS Path Group : clk_720p60Hz Path Type : min (fast corner) Path Class : async timing path -Clock Skew : 0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.878 - Launch Clock Delay : 5.516 +Clock Skew : 0.032 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 5.990 + Launch Clock Delay : 5.626 Clock Pessimism Removal : -0.332 Location Delay Type Incr Path Logical Resource @@ -14357,19 +16007,25 @@ Clock Skew : 0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessim PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 0.603 2.541 rd3_clk USCM_84_154/CLK_USCM td 0.000 2.541 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.091 3.632 ntR3907 + net (fanout=1) 1.091 3.632 ntR3950 PLL_158_303/CLK_OUT1 td 0.074 3.706 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 net (fanout=2) 0.915 4.621 nt_pix_clk USCM_84_117/CLK_USCM td 0.000 4.621 r clkbufg_2/gopclkbufg/CLKOUT - net (fanout=1635) 0.895 5.516 ntclkbufg_2 - CLMA_190_124/CLK r u_hdmi_rst/rst/opit_0_L5Q_perm/CLK + net (fanout=1635) 1.005 5.626 ntclkbufg_2 + CLMA_150_276/CLK r sync_vg_100m/opit_0_inv_L5Q_perm/CLK - CLMA_190_124/Q0 tco 0.182 5.698 r u_hdmi_rst/rst/opit_0_L5Q_perm/Q - net (fanout=163) 0.711 6.409 rd2_rst - DRM_234_148/RSTB[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0] + CLMA_150_276/Q0 tco 0.182 5.808 r sync_vg_100m/opit_0_inv_L5Q_perm/Q + net (fanout=911) 0.519 6.327 sync_vg_100m + CLMA_182_281/RSCO td 0.085 6.412 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=3) 0.000 6.412 ntR691 + CLMA_182_285/RSCO td 0.085 6.497 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[10]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=4) 0.000 6.497 ntR690 + CLMA_182_289/RSCO td 0.085 6.582 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/RSOUT + net (fanout=5) 0.000 6.582 ntR689 + CLMA_182_293/RSCI r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/RS - Data arrival time 6.409 Logic Levels: 0 - Logic: 0.182ns(20.381%), Route: 0.711ns(79.619%) + Data arrival time 6.582 Logic Levels: 3 + Logic: 0.437ns(45.711%), Route: 0.519ns(54.289%) ---------------------------------------------------------------------------------------------------- Clock clk_720p60Hz (rising edge) 0.000 0.000 r @@ -14382,35 +16038,35 @@ Clock Skew : 0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessim PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 0.614 2.811 rd3_clk USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.131 3.942 ntR3907 + net (fanout=1) 1.131 3.942 ntR3950 PLL_158_303/CLK_OUT1 td 0.079 4.021 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 net (fanout=2) 0.932 4.953 nt_pix_clk USCM_84_117/CLK_USCM td 0.000 4.953 r clkbufg_2/gopclkbufg/CLKOUT - net (fanout=1635) 0.925 5.878 ntclkbufg_2 - DRM_234_148/CLKB[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] - clock pessimism -0.332 5.546 - clock uncertainty 0.000 5.546 + net (fanout=1635) 1.037 5.990 ntclkbufg_2 + CLMA_182_293/CLK r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/CLK + clock pessimism -0.332 5.658 + clock uncertainty 0.000 5.658 - Removal time -0.063 5.483 + Removal time 0.000 5.658 - Data required time 5.483 + Data required time 5.658 ---------------------------------------------------------------------------------------------------- - Data required time 5.483 - Data arrival time 6.409 + Data required time 5.658 + Data arrival time 6.582 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.926 + Slack (MET) 0.924 ==================================================================================================== ==================================================================================================== -Startpoint : u_hdmi_rst/rst/opit_0_L5Q_perm/CLK -Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0] +Startpoint : sync_vg_100m/opit_0_inv_L5Q_perm/CLK +Endpoint : udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm/RS Path Group : clk_720p60Hz Path Type : min (fast corner) Path Class : async timing path -Clock Skew : 0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.878 - Launch Clock Delay : 5.516 +Clock Skew : 0.032 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 5.990 + Launch Clock Delay : 5.626 Clock Pessimism Removal : -0.332 Location Delay Type Incr Path Logical Resource @@ -14426,19 +16082,25 @@ Clock Skew : 0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessim PLL_158_55/CLK_OUT0 td 0.078 1.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 0.603 2.541 rd3_clk USCM_84_154/CLK_USCM td 0.000 2.541 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.091 3.632 ntR3907 + net (fanout=1) 1.091 3.632 ntR3950 PLL_158_303/CLK_OUT1 td 0.074 3.706 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 net (fanout=2) 0.915 4.621 nt_pix_clk USCM_84_117/CLK_USCM td 0.000 4.621 r clkbufg_2/gopclkbufg/CLKOUT - net (fanout=1635) 0.895 5.516 ntclkbufg_2 - CLMA_190_124/CLK r u_hdmi_rst/rst/opit_0_L5Q_perm/CLK + net (fanout=1635) 1.005 5.626 ntclkbufg_2 + CLMA_150_276/CLK r sync_vg_100m/opit_0_inv_L5Q_perm/CLK - CLMA_190_124/Q0 tco 0.182 5.698 r u_hdmi_rst/rst/opit_0_L5Q_perm/Q - net (fanout=163) 0.738 6.436 rd2_rst - DRM_234_168/RSTB[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0] + CLMA_150_276/Q0 tco 0.182 5.808 r sync_vg_100m/opit_0_inv_L5Q_perm/Q + net (fanout=911) 0.519 6.327 sync_vg_100m + CLMA_182_281/RSCO td 0.085 6.412 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=3) 0.000 6.412 ntR691 + CLMA_182_285/RSCO td 0.085 6.497 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[10]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=4) 0.000 6.497 ntR690 + CLMA_182_289/RSCO td 0.085 6.582 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/RSOUT + net (fanout=5) 0.000 6.582 ntR689 + CLMA_182_293/RSCI r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm/RS - Data arrival time 6.436 Logic Levels: 0 - Logic: 0.182ns(19.783%), Route: 0.738ns(80.217%) + Data arrival time 6.582 Logic Levels: 3 + Logic: 0.437ns(45.711%), Route: 0.519ns(54.289%) ---------------------------------------------------------------------------------------------------- Clock clk_720p60Hz (rising edge) 0.000 0.000 r @@ -14451,36 +16113,36 @@ Clock Skew : 0.030 (Capture Clock Delay - Launch Clock Delay + Clock Pessim PLL_158_55/CLK_OUT0 td 0.083 2.197 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 0.614 2.811 rd3_clk USCM_84_154/CLK_USCM td 0.000 2.811 r USCMROUTE_0/CLKOUT - net (fanout=1) 1.131 3.942 ntR3907 + net (fanout=1) 1.131 3.942 ntR3950 PLL_158_303/CLK_OUT1 td 0.079 4.021 r U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 net (fanout=2) 0.932 4.953 nt_pix_clk USCM_84_117/CLK_USCM td 0.000 4.953 r clkbufg_2/gopclkbufg/CLKOUT - net (fanout=1635) 0.925 5.878 ntclkbufg_2 - DRM_234_168/CLKB[0] r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] - clock pessimism -0.332 5.546 - clock uncertainty 0.000 5.546 + net (fanout=1635) 1.037 5.990 ntclkbufg_2 + CLMA_182_293/CLK r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm/CLK + clock pessimism -0.332 5.658 + clock uncertainty 0.000 5.658 - Removal time -0.063 5.483 + Removal time 0.000 5.658 - Data required time 5.483 + Data required time 5.658 ---------------------------------------------------------------------------------------------------- - Data required time 5.483 - Data arrival time 6.436 + Data required time 5.658 + Data arrival time 6.582 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.953 + Slack (MET) 0.924 ==================================================================================================== ==================================================================================================== Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK -Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[24]/opit_0_inv/RS +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/opit_0_inv_L5Q_perm/RS Path Group : ddrphy_clkin Path Type : max (fast corner) Path Class : async timing path -Clock Skew : 0.080 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 6.764 +Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 6.654 Launch Clock Delay : 7.101 - Clock Pessimism Removal : 0.417 + Clock Pessimism Removal : 0.428 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -14493,59 +16155,57 @@ Clock Skew : 0.080 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.614 2.807 zoom_clk + net (fanout=2) 0.614 2.807 ddr_clk USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.682 4.602 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 4.870 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 1.306 6.176 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 6.176 r clkbufg_0/gopclkbufg/CLKOUT net (fanout=5464) 0.925 7.101 ntclkbufg_0 - CLMA_70_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK - - CLMA_70_192/Q0 tco 0.223 7.324 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q - net (fanout=619) 1.016 8.340 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n - CLMA_10_224/RSCO td 0.113 8.453 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=4) 0.000 8.453 ntR1395 - CLMA_10_228/RSCO td 0.113 8.566 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[4]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=4) 0.000 8.566 ntR1394 - CLMA_10_232/RSCO td 0.113 8.679 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=4) 0.000 8.679 ntR1393 - CLMA_10_236/RSCO td 0.113 8.792 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[2]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=6) 0.000 8.792 ntR1392 - CLMA_10_240/RSCO td 0.113 8.905 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[246]/opit_0_inv/RSOUT - net (fanout=4) 0.000 8.905 ntR1391 - CLMA_10_244/RSCO td 0.113 9.018 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q_perm/RSOUT - net (fanout=2) 0.000 9.018 ntR1390 - CLMA_10_248/RSCO td 0.113 9.131 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[4]/opit_0_inv_A2Q21/RSOUT - net (fanout=3) 0.000 9.131 ntR1389 - CLMA_10_252/RSCO td 0.113 9.244 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/opit_0_inv_AQ_perm/RSOUT - net (fanout=4) 0.000 9.244 ntR1388 - CLMA_10_256/RSCO td 0.113 9.357 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=2) 0.000 9.357 ntR1387 - CLMA_10_260/RSCO td 0.113 9.470 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=2) 0.000 9.470 ntR1386 - CLMA_10_264/RSCO td 0.113 9.583 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[4]/opit_0_inv_A2Q21/RSOUT - net (fanout=3) 0.000 9.583 ntR1385 - CLMA_10_268/RSCO td 0.113 9.696 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/opit_0_inv_AQ/RSOUT - net (fanout=3) 0.000 9.696 ntR1384 - CLMA_10_272/RSCO td 0.113 9.809 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs/opit_0_inv/RSOUT - net (fanout=2) 0.000 9.809 ntR1383 - CLMA_10_276/RSCO td 0.113 9.922 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[3]/opit_0_inv_A2Q21/RSOUT - net (fanout=2) 0.000 9.922 ntR1382 - CLMA_10_280/RSCO td 0.113 10.035 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[7]/opit_0_inv_A2Q21/RSOUT - net (fanout=4) 0.000 10.035 ntR1381 - CLMA_10_284/RSCO td 0.113 10.148 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=4) 0.000 10.148 ntR1380 - CLMA_10_288/RSCO td 0.113 10.261 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[223]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=6) 0.000 10.261 ntR1379 - CLMA_10_292/RSCI f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[24]/opit_0_inv/RS - - Data arrival time 10.261 Logic Levels: 17 - Logic: 2.144ns(67.848%), Route: 1.016ns(32.152%) + CLMA_46_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK + + CLMA_46_192/Q0 tco 0.223 7.324 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q + net (fanout=729) 0.921 8.245 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n + CLMA_34_148/RSCO td 0.113 8.358 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[2]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=4) 0.000 8.358 ntR882 + CLMA_34_152/RSCO td 0.113 8.471 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[5]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=4) 0.000 8.471 ntR881 + CLMA_34_156/RSCO td 0.113 8.584 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_we_n_d[0]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=4) 0.000 8.584 ntR880 + CLMA_34_160/RSCO td 0.113 8.697 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cs_n_d[0]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=2) 0.000 8.697 ntR879 + CLMA_34_164/RSCO td 0.113 8.810 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[4]/opit_0_inv_A2Q21/RSOUT + net (fanout=3) 0.000 8.810 ntR878 + CLMA_34_168/RSCO td 0.113 8.923 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[0]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=6) 0.000 8.923 ntR877 + CLMA_34_172/RSCO td 0.113 9.036 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_r[1]/opit_0_inv/RSOUT + net (fanout=5) 0.000 9.036 ntR876 + CLMA_34_176/RSCO td 0.113 9.149 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=2) 0.000 9.149 ntR875 + CLMA_34_180/RSCO td 0.113 9.262 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[4]/opit_0_inv_A2Q21/RSOUT + net (fanout=2) 0.000 9.262 ntR874 + CLMA_34_184/RSCO td 0.113 9.375 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[8]/opit_0_inv_A2Q21/RSOUT + net (fanout=2) 0.000 9.375 ntR873 + CLMA_34_192/RSCO td 0.113 9.488 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[12]/opit_0_inv_A2Q21/RSOUT + net (fanout=2) 0.000 9.488 ntR872 + CLMA_34_196/RSCO td 0.113 9.601 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[16]/opit_0_inv_A2Q21/RSOUT + net (fanout=1) 0.000 9.601 ntR871 + CLMA_34_200/RSCO td 0.113 9.714 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[17]/opit_0_inv_AQ_perm/RSOUT + net (fanout=6) 0.000 9.714 ntR870 + CLMA_34_204/RSCO td 0.113 9.827 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[1]/opit_0_inv/RSOUT + net (fanout=5) 0.000 9.827 ntR869 + CLMA_34_208/RSCO td 0.113 9.940 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[238]/opit_0_inv/RSOUT + net (fanout=5) 0.000 9.940 ntR868 + CLMA_34_212/RSCO td 0.113 10.053 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[86]/opit_0_inv/RSOUT + net (fanout=5) 0.000 10.053 ntR867 + CLMA_34_216/RSCI f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/opit_0_inv_L5Q_perm/RS + + Data arrival time 10.053 Logic Levels: 16 + Logic: 2.031ns(68.801%), Route: 0.921ns(31.199%) ---------------------------------------------------------------------------------------------------- Clock ddrphy_clkin (rising edge) 10.000 10.000 r @@ -14556,42 +16216,42 @@ Clock Skew : 0.080 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.038 11.397 r clk_ibuf/opit_1/INCK net (fanout=1) 0.463 11.860 _N69 PLL_158_55/CLK_OUT1 td 0.074 11.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.603 12.537 zoom_clk + net (fanout=2) 0.603 12.537 ddr_clk USCM_84_113/CLK_USCM td 0.000 12.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 0.981 13.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 0.981 13.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.089 13.607 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.669 14.276 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.200 14.476 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.200 14.476 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 14.476 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 14.476 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 1.283 15.759 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 15.759 r clkbufg_0/gopclkbufg/CLKOUT - net (fanout=5464) 1.005 16.764 ntclkbufg_0 - CLMA_10_292/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[24]/opit_0_inv/CLK - clock pessimism 0.417 17.181 - clock uncertainty -0.150 17.031 + net (fanout=5464) 0.895 16.654 ntclkbufg_0 + CLMA_34_216/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/opit_0_inv_L5Q_perm/CLK + clock pessimism 0.428 17.082 + clock uncertainty -0.150 16.932 - Recovery time 0.000 17.031 + Recovery time 0.000 16.932 - Data required time 17.031 + Data required time 16.932 ---------------------------------------------------------------------------------------------------- - Data required time 17.031 - Data arrival time 10.261 + Data required time 16.932 + Data arrival time 10.053 ---------------------------------------------------------------------------------------------------- - Slack (MET) 6.770 + Slack (MET) 6.879 ==================================================================================================== ==================================================================================================== Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK -Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[58]/opit_0_inv/RS +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[110]/opit_0_inv/RS Path Group : ddrphy_clkin Path Type : max (fast corner) Path Class : async timing path -Clock Skew : 0.080 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 6.764 +Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 6.654 Launch Clock Delay : 7.101 - Clock Pessimism Removal : 0.417 + Clock Pessimism Removal : 0.428 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -14604,59 +16264,57 @@ Clock Skew : 0.080 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.614 2.807 zoom_clk + net (fanout=2) 0.614 2.807 ddr_clk USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.682 4.602 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 4.870 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 1.306 6.176 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 6.176 r clkbufg_0/gopclkbufg/CLKOUT net (fanout=5464) 0.925 7.101 ntclkbufg_0 - CLMA_70_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK - - CLMA_70_192/Q0 tco 0.223 7.324 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q - net (fanout=619) 1.016 8.340 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n - CLMA_10_224/RSCO td 0.113 8.453 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=4) 0.000 8.453 ntR1395 - CLMA_10_228/RSCO td 0.113 8.566 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[4]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=4) 0.000 8.566 ntR1394 - CLMA_10_232/RSCO td 0.113 8.679 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=4) 0.000 8.679 ntR1393 - CLMA_10_236/RSCO td 0.113 8.792 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[2]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=6) 0.000 8.792 ntR1392 - CLMA_10_240/RSCO td 0.113 8.905 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[246]/opit_0_inv/RSOUT - net (fanout=4) 0.000 8.905 ntR1391 - CLMA_10_244/RSCO td 0.113 9.018 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q_perm/RSOUT - net (fanout=2) 0.000 9.018 ntR1390 - CLMA_10_248/RSCO td 0.113 9.131 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[4]/opit_0_inv_A2Q21/RSOUT - net (fanout=3) 0.000 9.131 ntR1389 - CLMA_10_252/RSCO td 0.113 9.244 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/opit_0_inv_AQ_perm/RSOUT - net (fanout=4) 0.000 9.244 ntR1388 - CLMA_10_256/RSCO td 0.113 9.357 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=2) 0.000 9.357 ntR1387 - CLMA_10_260/RSCO td 0.113 9.470 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=2) 0.000 9.470 ntR1386 - CLMA_10_264/RSCO td 0.113 9.583 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[4]/opit_0_inv_A2Q21/RSOUT - net (fanout=3) 0.000 9.583 ntR1385 - CLMA_10_268/RSCO td 0.113 9.696 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/opit_0_inv_AQ/RSOUT - net (fanout=3) 0.000 9.696 ntR1384 - CLMA_10_272/RSCO td 0.113 9.809 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs/opit_0_inv/RSOUT - net (fanout=2) 0.000 9.809 ntR1383 - CLMA_10_276/RSCO td 0.113 9.922 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[3]/opit_0_inv_A2Q21/RSOUT - net (fanout=2) 0.000 9.922 ntR1382 - CLMA_10_280/RSCO td 0.113 10.035 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[7]/opit_0_inv_A2Q21/RSOUT - net (fanout=4) 0.000 10.035 ntR1381 - CLMA_10_284/RSCO td 0.113 10.148 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=4) 0.000 10.148 ntR1380 - CLMA_10_288/RSCO td 0.113 10.261 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[223]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=6) 0.000 10.261 ntR1379 - CLMA_10_292/RSCI f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[58]/opit_0_inv/RS - - Data arrival time 10.261 Logic Levels: 17 - Logic: 2.144ns(67.848%), Route: 1.016ns(32.152%) + CLMA_46_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK + + CLMA_46_192/Q0 tco 0.223 7.324 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q + net (fanout=729) 0.921 8.245 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n + CLMA_34_148/RSCO td 0.113 8.358 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[2]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=4) 0.000 8.358 ntR882 + CLMA_34_152/RSCO td 0.113 8.471 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[5]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=4) 0.000 8.471 ntR881 + CLMA_34_156/RSCO td 0.113 8.584 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_we_n_d[0]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=4) 0.000 8.584 ntR880 + CLMA_34_160/RSCO td 0.113 8.697 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cs_n_d[0]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=2) 0.000 8.697 ntR879 + CLMA_34_164/RSCO td 0.113 8.810 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[4]/opit_0_inv_A2Q21/RSOUT + net (fanout=3) 0.000 8.810 ntR878 + CLMA_34_168/RSCO td 0.113 8.923 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[0]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=6) 0.000 8.923 ntR877 + CLMA_34_172/RSCO td 0.113 9.036 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_r[1]/opit_0_inv/RSOUT + net (fanout=5) 0.000 9.036 ntR876 + CLMA_34_176/RSCO td 0.113 9.149 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=2) 0.000 9.149 ntR875 + CLMA_34_180/RSCO td 0.113 9.262 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[4]/opit_0_inv_A2Q21/RSOUT + net (fanout=2) 0.000 9.262 ntR874 + CLMA_34_184/RSCO td 0.113 9.375 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[8]/opit_0_inv_A2Q21/RSOUT + net (fanout=2) 0.000 9.375 ntR873 + CLMA_34_192/RSCO td 0.113 9.488 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[12]/opit_0_inv_A2Q21/RSOUT + net (fanout=2) 0.000 9.488 ntR872 + CLMA_34_196/RSCO td 0.113 9.601 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[16]/opit_0_inv_A2Q21/RSOUT + net (fanout=1) 0.000 9.601 ntR871 + CLMA_34_200/RSCO td 0.113 9.714 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[17]/opit_0_inv_AQ_perm/RSOUT + net (fanout=6) 0.000 9.714 ntR870 + CLMA_34_204/RSCO td 0.113 9.827 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[1]/opit_0_inv/RSOUT + net (fanout=5) 0.000 9.827 ntR869 + CLMA_34_208/RSCO td 0.113 9.940 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[238]/opit_0_inv/RSOUT + net (fanout=5) 0.000 9.940 ntR868 + CLMA_34_212/RSCO td 0.113 10.053 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[86]/opit_0_inv/RSOUT + net (fanout=5) 0.000 10.053 ntR867 + CLMA_34_216/RSCI f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[110]/opit_0_inv/RS + + Data arrival time 10.053 Logic Levels: 16 + Logic: 2.031ns(68.801%), Route: 0.921ns(31.199%) ---------------------------------------------------------------------------------------------------- Clock ddrphy_clkin (rising edge) 10.000 10.000 r @@ -14667,42 +16325,42 @@ Clock Skew : 0.080 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.038 11.397 r clk_ibuf/opit_1/INCK net (fanout=1) 0.463 11.860 _N69 PLL_158_55/CLK_OUT1 td 0.074 11.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.603 12.537 zoom_clk + net (fanout=2) 0.603 12.537 ddr_clk USCM_84_113/CLK_USCM td 0.000 12.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 0.981 13.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 0.981 13.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.089 13.607 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.669 14.276 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.200 14.476 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.200 14.476 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 14.476 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 14.476 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 1.283 15.759 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 15.759 r clkbufg_0/gopclkbufg/CLKOUT - net (fanout=5464) 1.005 16.764 ntclkbufg_0 - CLMA_10_292/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[58]/opit_0_inv/CLK - clock pessimism 0.417 17.181 - clock uncertainty -0.150 17.031 + net (fanout=5464) 0.895 16.654 ntclkbufg_0 + CLMA_34_216/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[110]/opit_0_inv/CLK + clock pessimism 0.428 17.082 + clock uncertainty -0.150 16.932 - Recovery time 0.000 17.031 + Recovery time 0.000 16.932 - Data required time 17.031 + Data required time 16.932 ---------------------------------------------------------------------------------------------------- - Data required time 17.031 - Data arrival time 10.261 + Data required time 16.932 + Data arrival time 10.053 ---------------------------------------------------------------------------------------------------- - Slack (MET) 6.770 + Slack (MET) 6.879 ==================================================================================================== ==================================================================================================== Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK -Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[60]/opit_0_inv/RS +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[116]/opit_0_inv/RS Path Group : ddrphy_clkin Path Type : max (fast corner) Path Class : async timing path -Clock Skew : 0.080 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 6.764 +Clock Skew : -0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 6.654 Launch Clock Delay : 7.101 - Clock Pessimism Removal : 0.417 + Clock Pessimism Removal : 0.428 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- @@ -14715,59 +16373,57 @@ Clock Skew : 0.080 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.614 2.807 zoom_clk + net (fanout=2) 0.614 2.807 ddr_clk USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.682 4.602 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 4.870 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 1.306 6.176 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 6.176 r clkbufg_0/gopclkbufg/CLKOUT net (fanout=5464) 0.925 7.101 ntclkbufg_0 - CLMA_70_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK - - CLMA_70_192/Q0 tco 0.223 7.324 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q - net (fanout=619) 1.016 8.340 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n - CLMA_10_224/RSCO td 0.113 8.453 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=4) 0.000 8.453 ntR1395 - CLMA_10_228/RSCO td 0.113 8.566 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[4]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=4) 0.000 8.566 ntR1394 - CLMA_10_232/RSCO td 0.113 8.679 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=4) 0.000 8.679 ntR1393 - CLMA_10_236/RSCO td 0.113 8.792 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[2]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=6) 0.000 8.792 ntR1392 - CLMA_10_240/RSCO td 0.113 8.905 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[246]/opit_0_inv/RSOUT - net (fanout=4) 0.000 8.905 ntR1391 - CLMA_10_244/RSCO td 0.113 9.018 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q_perm/RSOUT - net (fanout=2) 0.000 9.018 ntR1390 - CLMA_10_248/RSCO td 0.113 9.131 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[4]/opit_0_inv_A2Q21/RSOUT - net (fanout=3) 0.000 9.131 ntR1389 - CLMA_10_252/RSCO td 0.113 9.244 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/opit_0_inv_AQ_perm/RSOUT - net (fanout=4) 0.000 9.244 ntR1388 - CLMA_10_256/RSCO td 0.113 9.357 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=2) 0.000 9.357 ntR1387 - CLMA_10_260/RSCO td 0.113 9.470 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=2) 0.000 9.470 ntR1386 - CLMA_10_264/RSCO td 0.113 9.583 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[4]/opit_0_inv_A2Q21/RSOUT - net (fanout=3) 0.000 9.583 ntR1385 - CLMA_10_268/RSCO td 0.113 9.696 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/opit_0_inv_AQ/RSOUT - net (fanout=3) 0.000 9.696 ntR1384 - CLMA_10_272/RSCO td 0.113 9.809 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs/opit_0_inv/RSOUT - net (fanout=2) 0.000 9.809 ntR1383 - CLMA_10_276/RSCO td 0.113 9.922 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[3]/opit_0_inv_A2Q21/RSOUT - net (fanout=2) 0.000 9.922 ntR1382 - CLMA_10_280/RSCO td 0.113 10.035 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[7]/opit_0_inv_A2Q21/RSOUT - net (fanout=4) 0.000 10.035 ntR1381 - CLMA_10_284/RSCO td 0.113 10.148 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=4) 0.000 10.148 ntR1380 - CLMA_10_288/RSCO td 0.113 10.261 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[223]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=6) 0.000 10.261 ntR1379 - CLMA_10_292/RSCI f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[60]/opit_0_inv/RS - - Data arrival time 10.261 Logic Levels: 17 - Logic: 2.144ns(67.848%), Route: 1.016ns(32.152%) + CLMA_46_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK + + CLMA_46_192/Q0 tco 0.223 7.324 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q + net (fanout=729) 0.921 8.245 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n + CLMA_34_148/RSCO td 0.113 8.358 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[2]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=4) 0.000 8.358 ntR882 + CLMA_34_152/RSCO td 0.113 8.471 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[5]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=4) 0.000 8.471 ntR881 + CLMA_34_156/RSCO td 0.113 8.584 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_we_n_d[0]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=4) 0.000 8.584 ntR880 + CLMA_34_160/RSCO td 0.113 8.697 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cs_n_d[0]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=2) 0.000 8.697 ntR879 + CLMA_34_164/RSCO td 0.113 8.810 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[4]/opit_0_inv_A2Q21/RSOUT + net (fanout=3) 0.000 8.810 ntR878 + CLMA_34_168/RSCO td 0.113 8.923 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[0]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=6) 0.000 8.923 ntR877 + CLMA_34_172/RSCO td 0.113 9.036 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_r[1]/opit_0_inv/RSOUT + net (fanout=5) 0.000 9.036 ntR876 + CLMA_34_176/RSCO td 0.113 9.149 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/opit_0_inv_L5Q_perm/RSOUT + net (fanout=2) 0.000 9.149 ntR875 + CLMA_34_180/RSCO td 0.113 9.262 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[4]/opit_0_inv_A2Q21/RSOUT + net (fanout=2) 0.000 9.262 ntR874 + CLMA_34_184/RSCO td 0.113 9.375 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[8]/opit_0_inv_A2Q21/RSOUT + net (fanout=2) 0.000 9.375 ntR873 + CLMA_34_192/RSCO td 0.113 9.488 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[12]/opit_0_inv_A2Q21/RSOUT + net (fanout=2) 0.000 9.488 ntR872 + CLMA_34_196/RSCO td 0.113 9.601 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[16]/opit_0_inv_A2Q21/RSOUT + net (fanout=1) 0.000 9.601 ntR871 + CLMA_34_200/RSCO td 0.113 9.714 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[17]/opit_0_inv_AQ_perm/RSOUT + net (fanout=6) 0.000 9.714 ntR870 + CLMA_34_204/RSCO td 0.113 9.827 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[1]/opit_0_inv/RSOUT + net (fanout=5) 0.000 9.827 ntR869 + CLMA_34_208/RSCO td 0.113 9.940 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[238]/opit_0_inv/RSOUT + net (fanout=5) 0.000 9.940 ntR868 + CLMA_34_212/RSCO td 0.113 10.053 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[86]/opit_0_inv/RSOUT + net (fanout=5) 0.000 10.053 ntR867 + CLMA_34_216/RSCI f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[116]/opit_0_inv/RS + + Data arrival time 10.053 Logic Levels: 16 + Logic: 2.031ns(68.801%), Route: 0.921ns(31.199%) ---------------------------------------------------------------------------------------------------- Clock ddrphy_clkin (rising edge) 10.000 10.000 r @@ -14778,35 +16434,35 @@ Clock Skew : 0.080 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.038 11.397 r clk_ibuf/opit_1/INCK net (fanout=1) 0.463 11.860 _N69 PLL_158_55/CLK_OUT1 td 0.074 11.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.603 12.537 zoom_clk + net (fanout=2) 0.603 12.537 ddr_clk USCM_84_113/CLK_USCM td 0.000 12.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 0.981 13.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 0.981 13.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.089 13.607 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.669 14.276 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.200 14.476 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.200 14.476 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 14.476 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 14.476 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 1.283 15.759 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 15.759 r clkbufg_0/gopclkbufg/CLKOUT - net (fanout=5464) 1.005 16.764 ntclkbufg_0 - CLMA_10_292/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[60]/opit_0_inv/CLK - clock pessimism 0.417 17.181 - clock uncertainty -0.150 17.031 + net (fanout=5464) 0.895 16.654 ntclkbufg_0 + CLMA_34_216/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[116]/opit_0_inv/CLK + clock pessimism 0.428 17.082 + clock uncertainty -0.150 16.932 - Recovery time 0.000 17.031 + Recovery time 0.000 16.932 - Data required time 17.031 + Data required time 16.932 ---------------------------------------------------------------------------------------------------- - Data required time 17.031 - Data arrival time 10.261 + Data required time 16.932 + Data arrival time 10.053 ---------------------------------------------------------------------------------------------------- - Slack (MET) 6.770 + Slack (MET) 6.879 ==================================================================================================== ==================================================================================================== Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK -Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[151]/opit_0_inv/RS +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[6]/opit_0_inv_L5Q_perm/RS Path Group : ddrphy_clkin Path Type : min (fast corner) Path Class : async timing path @@ -14826,27 +16482,27 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK net (fanout=1) 0.463 1.860 _N69 PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.603 2.537 zoom_clk + net (fanout=2) 0.603 2.537 ddr_clk USCM_84_113/CLK_USCM td 0.000 2.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.089 3.607 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.669 4.276 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.200 4.476 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.200 4.476 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 4.476 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 4.476 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 1.283 5.759 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 5.759 r clkbufg_0/gopclkbufg/CLKOUT net (fanout=5464) 0.895 6.654 ntclkbufg_0 - CLMA_70_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK + CLMA_46_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK - CLMA_70_192/Q0 tco 0.182 6.836 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q - net (fanout=619) 0.300 7.136 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n - CLMA_66_212/RSCO td 0.092 7.228 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[37]/opit_0_inv/RSOUT - net (fanout=4) 0.000 7.228 ntR1484 - CLMA_66_216/RSCI f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[151]/opit_0_inv/RS + CLMA_46_192/Q0 tco 0.179 6.833 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q + net (fanout=729) 0.237 7.070 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n + CLMA_38_192/RSCO td 0.085 7.155 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[57]/opit_0_inv/RSOUT + net (fanout=4) 0.000 7.155 ntR984 + CLMA_38_196/RSCI r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[6]/opit_0_inv_L5Q_perm/RS - Data arrival time 7.228 Logic Levels: 1 - Logic: 0.274ns(47.735%), Route: 0.300ns(52.265%) + Data arrival time 7.155 Logic Levels: 1 + Logic: 0.264ns(52.695%), Route: 0.237ns(47.305%) ---------------------------------------------------------------------------------------------------- Clock ddrphy_clkin (rising edge) 0.000 0.000 r @@ -14857,18 +16513,18 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.614 2.807 zoom_clk + net (fanout=2) 0.614 2.807 ddr_clk USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.682 4.602 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 4.870 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 1.306 6.176 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 6.176 r clkbufg_0/gopclkbufg/CLKOUT net (fanout=5464) 0.925 7.101 ntclkbufg_0 - CLMA_66_216/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[151]/opit_0_inv/CLK + CLMA_38_196/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[6]/opit_0_inv_L5Q_perm/CLK clock pessimism -0.428 6.673 clock uncertainty 0.000 6.673 @@ -14877,15 +16533,15 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim Data required time 6.673 ---------------------------------------------------------------------------------------------------- Data required time 6.673 - Data arrival time 7.228 + Data arrival time 7.155 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.555 + Slack (MET) 0.482 ==================================================================================================== ==================================================================================================== Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK -Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[2]/opit_0_inv/RS +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[7]/opit_0_inv_L5Q_perm/RS Path Group : ddrphy_clkin Path Type : min (fast corner) Path Class : async timing path @@ -14905,27 +16561,27 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK net (fanout=1) 0.463 1.860 _N69 PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.603 2.537 zoom_clk + net (fanout=2) 0.603 2.537 ddr_clk USCM_84_113/CLK_USCM td 0.000 2.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.089 3.607 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.669 4.276 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.200 4.476 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.200 4.476 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 4.476 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 4.476 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 1.283 5.759 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 5.759 r clkbufg_0/gopclkbufg/CLKOUT net (fanout=5464) 0.895 6.654 ntclkbufg_0 - CLMA_70_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK + CLMA_46_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK - CLMA_70_192/Q0 tco 0.182 6.836 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q - net (fanout=619) 0.300 7.136 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n - CLMA_66_212/RSCO td 0.092 7.228 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[37]/opit_0_inv/RSOUT - net (fanout=4) 0.000 7.228 ntR1484 - CLMA_66_216/RSCI f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[2]/opit_0_inv/RS + CLMA_46_192/Q0 tco 0.179 6.833 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q + net (fanout=729) 0.237 7.070 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n + CLMA_38_192/RSCO td 0.085 7.155 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[57]/opit_0_inv/RSOUT + net (fanout=4) 0.000 7.155 ntR984 + CLMA_38_196/RSCI r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[7]/opit_0_inv_L5Q_perm/RS - Data arrival time 7.228 Logic Levels: 1 - Logic: 0.274ns(47.735%), Route: 0.300ns(52.265%) + Data arrival time 7.155 Logic Levels: 1 + Logic: 0.264ns(52.695%), Route: 0.237ns(47.305%) ---------------------------------------------------------------------------------------------------- Clock ddrphy_clkin (rising edge) 0.000 0.000 r @@ -14936,18 +16592,18 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.614 2.807 zoom_clk + net (fanout=2) 0.614 2.807 ddr_clk USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.682 4.602 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 4.870 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 1.306 6.176 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 6.176 r clkbufg_0/gopclkbufg/CLKOUT net (fanout=5464) 0.925 7.101 ntclkbufg_0 - CLMA_66_216/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[2]/opit_0_inv/CLK + CLMA_38_196/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[7]/opit_0_inv_L5Q_perm/CLK clock pessimism -0.428 6.673 clock uncertainty 0.000 6.673 @@ -14956,15 +16612,15 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim Data required time 6.673 ---------------------------------------------------------------------------------------------------- Data required time 6.673 - Data arrival time 7.228 + Data arrival time 7.155 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.555 + Slack (MET) 0.482 ==================================================================================================== ==================================================================================================== Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK -Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[3]/opit_0_inv/RS +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[8]/opit_0_inv_L5Q_perm/RS Path Group : ddrphy_clkin Path Type : min (fast corner) Path Class : async timing path @@ -14984,27 +16640,27 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.038 1.397 r clk_ibuf/opit_1/INCK net (fanout=1) 0.463 1.860 _N69 PLL_158_55/CLK_OUT1 td 0.074 1.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.603 2.537 zoom_clk + net (fanout=2) 0.603 2.537 ddr_clk USCM_84_113/CLK_USCM td 0.000 2.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 0.981 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.089 3.607 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.669 4.276 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.200 4.476 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.200 4.476 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 4.476 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 4.476 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 1.283 5.759 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 5.759 r clkbufg_0/gopclkbufg/CLKOUT net (fanout=5464) 0.895 6.654 ntclkbufg_0 - CLMA_70_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK + CLMA_46_192/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK - CLMA_70_192/Q0 tco 0.182 6.836 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q - net (fanout=619) 0.300 7.136 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n - CLMA_66_212/RSCO td 0.092 7.228 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[37]/opit_0_inv/RSOUT - net (fanout=4) 0.000 7.228 ntR1484 - CLMA_66_216/RSCI f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[3]/opit_0_inv/RS + CLMA_46_192/Q0 tco 0.179 6.833 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q + net (fanout=729) 0.237 7.070 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n + CLMA_38_192/RSCO td 0.085 7.155 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[57]/opit_0_inv/RSOUT + net (fanout=4) 0.000 7.155 ntR984 + CLMA_38_196/RSCI r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[8]/opit_0_inv_L5Q_perm/RS - Data arrival time 7.228 Logic Levels: 1 - Logic: 0.274ns(47.735%), Route: 0.300ns(52.265%) + Data arrival time 7.155 Logic Levels: 1 + Logic: 0.264ns(52.695%), Route: 0.237ns(47.305%) ---------------------------------------------------------------------------------------------------- Clock ddrphy_clkin (rising edge) 0.000 0.000 r @@ -15015,18 +16671,18 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.614 2.807 zoom_clk + net (fanout=2) 0.614 2.807 ddr_clk USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.682 4.602 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 4.870 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 1.306 6.176 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 6.176 r clkbufg_0/gopclkbufg/CLKOUT net (fanout=5464) 0.925 7.101 ntclkbufg_0 - CLMA_66_216/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[3]/opit_0_inv/CLK + CLMA_38_196/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[8]/opit_0_inv_L5Q_perm/CLK clock pessimism -0.428 6.673 clock uncertainty 0.000 6.673 @@ -15035,14 +16691,14 @@ Clock Skew : 0.019 (Capture Clock Delay - Launch Clock Delay + Clock Pessim Data required time 6.673 ---------------------------------------------------------------------------------------------------- Data required time 6.673 - Data arrival time 7.228 + Data arrival time 7.155 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.555 + Slack (MET) 0.482 ==================================================================================================== ==================================================================================================== -Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/calib_done/opit_0_inv_MUX4TO1Q/CLK +Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_rst/opit_0_inv/CLK Endpoint : mem_rst_n (port) Path Group : **default** Path Type : max (fast corner) @@ -15059,37 +16715,37 @@ Path Class : combinational timing path IOL_327_210/INCK td 0.058 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) 0.478 2.114 _N69 PLL_158_55/CLK_OUT1 td 0.079 2.193 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=2) 0.614 2.807 zoom_clk + net (fanout=2) 0.614 2.807 ddr_clk USCM_84_113/CLK_USCM td 0.000 2.807 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=71) 1.019 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin PLL_158_199/CLK_OUT0_WL td 0.094 3.920 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) 0.682 4.602 clkout0_wl_0 - IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_8/gopclkgate/OUT + IOCKGATE_6_322/OUT td 0.268 4.870 r clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 4.870 ntclkgate_0 IOCKDIV_6_323/CLK_IODIV td 0.000 4.870 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) 1.306 6.176 u_axi_ddr_top/clk USCM_84_116/CLK_USCM td 0.000 6.176 r clkbufg_0/gopclkbufg/CLKOUT net (fanout=5464) 0.925 7.101 ntclkbufg_0 - CLMS_46_173/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/calib_done/opit_0_inv_MUX4TO1Q/CLK - - CLMS_46_173/Q1 tco 0.223 7.324 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/calib_done/opit_0_inv_MUX4TO1Q/Q - net (fanout=575) 1.703 9.027 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/calib_done - CLMS_18_317/Y0 td 0.150 9.177 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/N48/gateop_perm/Z - net (fanout=1) 0.772 9.949 nt_mem_rst_n - IOL_7_369/DO td 0.106 10.055 f mem_rst_n_obuf/opit_1/O - net (fanout=1) 0.000 10.055 mem_rst_n_obuf/ntO - IOBS_LR_0_368/PAD td 3.229 13.284 f mem_rst_n_obuf/opit_0/O - net (fanout=1) 0.096 13.380 mem_rst_n + CLMA_46_156/CLK r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_rst/opit_0_inv/CLK + + CLMA_46_156/Q0 tco 0.221 7.322 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_rst/opit_0_inv/Q + net (fanout=1) 0.497 7.819 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/calib_rst + CLMS_34_173/Y3 td 0.151 7.970 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/N48/gateop_perm/Z + net (fanout=1) 1.679 9.649 nt_mem_rst_n + IOL_7_369/DO td 0.106 9.755 f mem_rst_n_obuf/opit_1/O + net (fanout=1) 0.000 9.755 mem_rst_n_obuf/ntO + IOBS_LR_0_368/PAD td 3.229 12.984 f mem_rst_n_obuf/opit_0/O + net (fanout=1) 0.096 13.080 mem_rst_n C1 f mem_rst_n (port) - Data arrival time 13.380 Logic Levels: 3 - Logic: 3.708ns(59.054%), Route: 2.571ns(40.946%) + Data arrival time 13.080 Logic Levels: 3 + Logic: 3.707ns(62.000%), Route: 2.272ns(38.000%) ==================================================================================================== ==================================================================================================== -Startpoint : param_manager_inst/index[1]/opit_0_L5Q_perm/CLK -Endpoint : led[2] (port) +Startpoint : param_manager_inst/index[0]/opit_0_L5Q_perm/CLK +Endpoint : led[1] (port) Path Group : **default** Path Type : max (fast corner) Path Class : combinational timing path @@ -15107,25 +16763,25 @@ Path Class : combinational timing path IOCKDLY_237_367/CLK_OUT td 2.942 4.288 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT net (fanout=1) 1.521 5.809 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf USCM_84_109/CLK_USCM td 0.000 5.809 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - net (fanout=1861) 0.925 6.734 gmii_clk - CLMA_194_168/CLK r param_manager_inst/index[1]/opit_0_L5Q_perm/CLK - - CLMA_194_168/Q3 tco 0.220 6.954 f param_manager_inst/index[1]/opit_0_L5Q_perm/Q - net (fanout=19) 2.648 9.602 nt_led[2] - IOL_19_373/DO td 0.106 9.708 f led_obuf[2]/opit_1/O - net (fanout=1) 0.000 9.708 led_obuf[2]/ntO - IOBS_TB_17_376/PAD td 3.238 12.946 f led_obuf[2]/opit_0/O - net (fanout=1) 0.107 13.053 led[2] - A2 f led[2] (port) + net (fanout=1862) 0.925 6.734 gmii_clk + CLMA_210_205/CLK r param_manager_inst/index[0]/opit_0_L5Q_perm/CLK - Data arrival time 13.053 Logic Levels: 2 - Logic: 3.564ns(56.401%), Route: 2.755ns(43.599%) + CLMA_210_205/Q0 tco 0.221 6.955 f param_manager_inst/index[0]/opit_0_L5Q_perm/Q + net (fanout=20) 2.671 9.626 nt_led[1] + IOL_19_374/DO td 0.106 9.732 f led_obuf[1]/opit_1/O + net (fanout=1) 0.000 9.732 led_obuf[1]/ntO + IOBD_16_376/PAD td 3.238 12.970 f led_obuf[1]/opit_0/O + net (fanout=1) 0.109 13.079 led[1] + B2 f led[1] (port) + + Data arrival time 13.079 Logic Levels: 2 + Logic: 3.565ns(56.186%), Route: 2.780ns(43.814%) ==================================================================================================== ==================================================================================================== -Startpoint : param_manager_inst/index[3]/opit_0_L5Q_perm/CLK -Endpoint : led[4] (port) +Startpoint : param_manager_inst/index[1]/opit_0_L5Q_perm/CLK +Endpoint : led[2] (port) Path Group : **default** Path Type : max (fast corner) Path Class : combinational timing path @@ -15143,19 +16799,19 @@ Path Class : combinational timing path IOCKDLY_237_367/CLK_OUT td 2.942 4.288 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT net (fanout=1) 1.521 5.809 udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf USCM_84_109/CLK_USCM td 0.000 5.809 r udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - net (fanout=1861) 0.925 6.734 gmii_clk - CLMA_194_168/CLK r param_manager_inst/index[3]/opit_0_L5Q_perm/CLK - - CLMA_194_168/Q1 tco 0.223 6.957 f param_manager_inst/index[3]/opit_0_L5Q_perm/Q - net (fanout=18) 2.603 9.560 nt_led[4] - IOL_35_373/DO td 0.106 9.666 f led_obuf[4]/opit_1/O - net (fanout=1) 0.000 9.666 led_obuf[4]/ntO - IOBS_TB_33_376/PAD td 3.238 12.904 f led_obuf[4]/opit_0/O - net (fanout=1) 0.087 12.991 led[4] - A3 f led[4] (port) + net (fanout=1862) 0.925 6.734 gmii_clk + CLMA_210_205/CLK r param_manager_inst/index[1]/opit_0_L5Q_perm/CLK + + CLMA_210_205/Q3 tco 0.220 6.954 f param_manager_inst/index[1]/opit_0_L5Q_perm/Q + net (fanout=19) 2.580 9.534 nt_led[2] + IOL_19_373/DO td 0.106 9.640 f led_obuf[2]/opit_1/O + net (fanout=1) 0.000 9.640 led_obuf[2]/ntO + IOBS_TB_17_376/PAD td 3.238 12.878 f led_obuf[2]/opit_0/O + net (fanout=1) 0.107 12.985 led[2] + A2 f led[2] (port) - Data arrival time 12.991 Logic Levels: 2 - Logic: 3.567ns(57.008%), Route: 2.690ns(42.992%) + Data arrival time 12.985 Logic Levels: 2 + Logic: 3.564ns(57.015%), Route: 2.687ns(42.985%) ==================================================================================================== ==================================================================================================== @@ -15228,35 +16884,35 @@ Path Class : combinational timing path **************************************************************************************************** Slack Actual Width Require Width Type Location Pin ---------------------------------------------------------------------------------------------------- - 5.232 5.950 0.718 Low Pulse Width DRM_142_24/CLKA[0] u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] - 5.232 5.950 0.718 High Pulse Width DRM_142_24/CLKA[0] u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] - 5.454 5.950 0.496 High Pulse Width CLMS_146_9/CLK u_ov5640/cmos1_8_16bit/de_in0/opit_0/CLK + 5.232 5.950 0.718 Low Pulse Width DRM_142_44/CLKA[0] u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] + 5.232 5.950 0.718 High Pulse Width DRM_142_44/CLKA[0] u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] + 5.454 5.950 0.496 Low Pulse Width CLMS_134_25/CLK u_ov5640/cmos1_8_16bit/de_cnt/opit_0_L5Q_perm/CLK ==================================================================================================== {cmos2_pclk} Minimum Pulse Width : **************************************************************************************************** Slack Actual Width Require Width Type Location Pin ---------------------------------------------------------------------------------------------------- - 5.232 5.950 0.718 Low Pulse Width DRM_142_44/CLKA[0] u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] - 5.232 5.950 0.718 High Pulse Width DRM_142_44/CLKA[0] u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] - 5.454 5.950 0.496 Low Pulse Width CLMS_150_41/CLK u_ov5640/cmos2_8_16bit/de_cnt/opit_0_L5Q/CLK + 5.232 5.950 0.718 Low Pulse Width DRM_142_24/CLKA[0] u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] + 5.232 5.950 0.718 High Pulse Width DRM_142_24/CLKA[0] u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] + 5.454 5.950 0.496 High Pulse Width CLMS_74_17/CLK u_ov5640/cmos2_8_16bit/de_in0/opit_0/CLK ==================================================================================================== {hdmi_in_clk} Minimum Pulse Width : **************************************************************************************************** Slack Actual Width Require Width Type Location Pin ---------------------------------------------------------------------------------------------------- - 2.615 3.333 0.718 Low Pulse Width DRM_82_108/CLKA[0] u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] - 2.615 3.333 0.718 High Pulse Width DRM_82_108/CLKA[0] u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] - 2.615 3.333 0.718 High Pulse Width DRM_54_108/CLKA[0] u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] + 2.615 3.333 0.718 Low Pulse Width DRM_82_128/CLKA[0] u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] + 2.615 3.333 0.718 High Pulse Width DRM_82_128/CLKA[0] u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] + 2.615 3.333 0.718 Low Pulse Width DRM_82_88/CLKA[0] u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] ==================================================================================================== {eth_rxc} Minimum Pulse Width : **************************************************************************************************** Slack Actual Width Require Width Type Location Pin ---------------------------------------------------------------------------------------------------- - 2.787 4.000 1.213 High Pulse Width IOL_71_373/CLK_SYS udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_ctl_in/gateigddr_IOL/SYSCLK 2.787 4.000 1.213 Low Pulse Width IOL_71_373/CLK_SYS udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_ctl_in/gateigddr_IOL/SYSCLK + 2.787 4.000 1.213 High Pulse Width IOL_71_373/CLK_SYS udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_ctl_in/gateigddr_IOL/SYSCLK 2.787 4.000 1.213 Low Pulse Width IOL_311_374/CLK_SYS udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gtp_outbuft1/opit_1_IOL/SYSCLK ==================================================================================================== @@ -15264,63 +16920,72 @@ Path Class : combinational timing path **************************************************************************************************** Slack Actual Width Require Width Type Location Pin ---------------------------------------------------------------------------------------------------- - 9.090 10.000 0.910 High Pulse Width APM_106_116/CLK u_rotate_image/u_rotate_mult0/N2/gopapm/CLK - 9.090 10.000 0.910 Low Pulse Width APM_106_116/CLK u_rotate_image/u_rotate_mult0/N2/gopapm/CLK - 9.090 10.000 0.910 High Pulse Width APM_106_104/CLK u_rotate_image/u_rotate_mult1/N2/gopapm/CLK + 9.090 10.000 0.910 Low Pulse Width APM_206_228/CLK u_rotate_image/u_rotate_mult0/N2/gopapm/CLK + 9.090 10.000 0.910 High Pulse Width APM_206_228/CLK u_rotate_image/u_rotate_mult0/N2/gopapm/CLK + 9.090 10.000 0.910 High Pulse Width APM_206_216/CLK u_rotate_image/u_rotate_mult1/N2/gopapm/CLK ==================================================================================================== {clk_200m} Minimum Pulse Width : **************************************************************************************************** Slack Actual Width Require Width Type Location Pin ---------------------------------------------------------------------------------------------------- - 1.590 2.500 0.910 Low Pulse Width APM_206_228/CLK u_zoom_image/mult_fra0/N2/gopapm/CLK - 1.590 2.500 0.910 High Pulse Width APM_206_228/CLK u_zoom_image/mult_fra0/N2/gopapm/CLK - 1.590 2.500 0.910 Low Pulse Width APM_206_140/CLK u_zoom_image/mult_fra0_0/N2/gopapm/CLK + 2.004 2.500 0.496 Low Pulse Width CLMS_34_181/CLK u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[0]/opit_0_inv_L5Q_perm/CLK + 2.004 2.500 0.496 High Pulse Width CLMS_34_181/CLK u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[0]/opit_0_inv_L5Q_perm/CLK + 2.004 2.500 0.496 High Pulse Width CLMS_34_193/CLK u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[1]/opit_0_inv_L5Q_perm/CLK ==================================================================================================== {clk_25m} Minimum Pulse Width : **************************************************************************************************** Slack Actual Width Require Width Type Location Pin ---------------------------------------------------------------------------------------------------- - 19.664 20.000 0.336 High Pulse Width CLMA_182_12/CLK u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK - 19.664 20.000 0.336 Low Pulse Width CLMA_182_12/CLK u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK - 19.664 20.000 0.336 High Pulse Width CLMA_182_12/CLK u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/CLK + 19.504 20.000 0.496 High Pulse Width CLMS_122_9/CLK u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK + 19.504 20.000 0.496 Low Pulse Width CLMS_122_9/CLK u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK + 19.504 20.000 0.496 High Pulse Width CLMS_122_9/CLK u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/CLK ==================================================================================================== {clk_10m} Minimum Pulse Width : **************************************************************************************************** Slack Actual Width Require Width Type Location Pin ---------------------------------------------------------------------------------------------------- - 49.282 50.000 0.718 Low Pulse Width DRM_234_108/CLKA[0] ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKA[0] - 49.282 50.000 0.718 High Pulse Width DRM_234_108/CLKA[0] ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKA[0] - 49.282 50.000 0.718 Low Pulse Width DRM_234_108/CLKB[0] ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKB[0] + 49.282 50.000 0.718 Low Pulse Width DRM_234_316/CLKA[0] ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKA[0] + 49.282 50.000 0.718 High Pulse Width DRM_234_316/CLKA[0] ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKA[0] + 49.282 50.000 0.718 Low Pulse Width DRM_234_316/CLKB[0] ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKB[0] +==================================================================================================== + +{clk_1080p60Hz} Minimum Pulse Width : +**************************************************************************************************** + Slack Actual Width Require Width Type Location Pin +---------------------------------------------------------------------------------------------------- + 2.458 3.368 0.910 High Pulse Width APM_206_28/CLK u_zoom_image/mult_fra0/N2/gopapm/CLK + 2.458 3.368 0.910 Low Pulse Width APM_206_28/CLK u_zoom_image/mult_fra0/N2/gopapm/CLK + 2.458 3.368 0.910 High Pulse Width APM_206_264/CLK u_zoom_image/mult_fra0_0/N2/gopapm/CLK ==================================================================================================== {clk_720p60Hz} Minimum Pulse Width : **************************************************************************************************** Slack Actual Width Require Width Type Location Pin ---------------------------------------------------------------------------------------------------- - 5.826 6.736 0.910 High Pulse Width APM_258_140/CLK adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N11/gopapm/CLK - 5.826 6.736 0.910 High Pulse Width APM_258_128/CLK adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N135/gopapm/CLK - 5.827 6.737 0.910 Low Pulse Width APM_258_140/CLK adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N11/gopapm/CLK + 5.826 6.736 0.910 High Pulse Width APM_258_216/CLK adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N11/gopapm/CLK + 5.826 6.736 0.910 High Pulse Width APM_258_204/CLK adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N135/gopapm/CLK + 5.827 6.737 0.910 Low Pulse Width APM_258_216/CLK adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N11/gopapm/CLK ==================================================================================================== {clk_20k} Minimum Pulse Width : **************************************************************************************************** Slack Actual Width Require Width Type Location Pin ---------------------------------------------------------------------------------------------------- - 24999.282 25000.000 0.718 Low Pulse Width DRM_178_4/CLKA[0] u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKA[0] - 24999.282 25000.000 0.718 High Pulse Width DRM_178_4/CLKA[0] u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKA[0] - 24999.282 25000.000 0.718 Low Pulse Width DRM_178_4/CLKB[0] u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0] + 24999.282 25000.000 0.718 Low Pulse Width DRM_142_4/CLKA[0] u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKA[0] + 24999.282 25000.000 0.718 High Pulse Width DRM_142_4/CLKA[0] u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKA[0] + 24999.282 25000.000 0.718 Low Pulse Width DRM_142_4/CLKB[0] u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0] ==================================================================================================== {ddrphy_clkin} Minimum Pulse Width : **************************************************************************************************** Slack Actual Width Require Width Type Location Pin ---------------------------------------------------------------------------------------------------- - 3.480 5.000 1.520 High Pulse Width CLMS_38_109/CLK u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram16x1d/WCLK - 3.480 5.000 1.520 Low Pulse Width CLMS_38_109/CLK u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram16x1d/WCLK - 3.480 5.000 1.520 High Pulse Width CLMS_34_113/CLK u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_2/ram16x1d/WCLK + 3.480 5.000 1.520 Low Pulse Width CLMS_38_101/CLK u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram16x1d/WCLK + 3.480 5.000 1.520 High Pulse Width CLMS_38_101/CLK u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram16x1d/WCLK + 3.480 5.000 1.520 Low Pulse Width CLMS_42_101/CLK u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_2/ram16x1d/WCLK ==================================================================================================== {ioclk0} Minimum Pulse Width : @@ -15373,6 +17038,6 @@ Inputs and Outputs : Flow Command: report_timing Peak memory: 1,325 MB -Total CPU time to report_timing completion : 0h:0m:25s -Process Total CPU time to report_timing completion : 0h:0m:32s -Total real time to report_timing completion : 0h:0m:26s +Total CPU time to report_timing completion : 0h:0m:26s +Process Total CPU time to report_timing completion : 0h:0m:35s +Total real time to report_timing completion : 0h:0m:28s diff --git a/project/report_timing/multimedia_video_processor_rtp.adf b/project/report_timing/multimedia_video_processor_rtp.adf index e9f1e03..1104ed2 100644 Binary files a/project/report_timing/multimedia_video_processor_rtp.adf and b/project/report_timing/multimedia_video_processor_rtp.adf differ diff --git a/project/report_timing/rtr.db b/project/report_timing/rtr.db index d0b002a..1ecc4d2 100644 --- a/project/report_timing/rtr.db +++ b/project/report_timing/rtr.db @@ -892,7 +892,7 @@ 50.000MHz 0.000 10.000 - 2517 + 2516 0 clk { u_sys_pll/u_pll_e3/goppll/CLKOUT0 } @@ -904,7 +904,7 @@ 200.000MHz 0.000 2.500 - 825 + 75 5 clk { u_sys_pll/u_pll_e3/goppll/CLKOUT1 } @@ -1024,7 +1024,7 @@ 148.438MHz 0.000 3.368 - 0 + 750 0 clk { U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 } @@ -1085,13 +1085,13 @@ 125.000MHz 0.000 4.000 - 1861 + 1862 1 { eth_rxc } - +
Clock Fmax @@ -1100,69 +1100,75 @@ cmos1_pclk - 161.186MHz + 151.630MHz 84.034MHz - 5.696 + 5.305 cmos2_pclk - 131.423MHz + 132.398MHz 84.034MHz - 4.291 + 4.347 hdmi_in_clk - 180.636MHz + 207.168MHz 150.015MHz - 1.130 + 1.839 eth_rxc - 144.446MHz + 143.390MHz 125.000MHz - 1.077 + 1.026 clk_50m - 109.349MHz + 103.670MHz 50.000MHz - 10.855 + 10.354 - + clk_200m - 172.771MHz + 257.798MHz 200.000MHz - -0.788 + 1.121 clk_25m - 218.293MHz + 222.272MHz 25.000MHz - 35.419 + 35.501 clk_10m - 171.644MHz + 184.775MHz 10.000MHz - 94.174 + 94.588 + + + clk_1080p60Hz + 176.875MHz + 148.438MHz + 1.083 clk_720p60Hz - 124.635MHz + 133.594MHz 74.219MHz - 5.450 + 5.988 clk_20k - 201.939MHz + 185.563MHz 0.020MHz - 49995.048 + 49994.611 ddrphy_clkin - 103.605MHz + 132.837MHz 100.000MHz - 0.348 + 2.472 ioclk0 @@ -1197,11 +1203,11 @@ cmos1_pclk YES Timed - 5.696 + 5.305 0.000 0 251 - 0.199 + 0.175 0.000 0 251 @@ -1239,11 +1245,11 @@ cmos2_pclk YES Timed - 4.291 + 4.347 0.000 0 251 - 0.415 + 0.407 0.000 0 251 @@ -1281,11 +1287,11 @@ hdmi_in_clk YES Timed - 1.130 + 1.839 0.000 0 311 - 0.191 + 0.189 0.000 0 311 @@ -1351,14 +1357,14 @@ eth_rxc YES Timed - 1.077 + 1.026 0.000 0 - 5907 - 0.381 + 5918 + 0.157 0.000 0 - 5907 + 5918 clk_720p60Hz @@ -1368,11 +1374,11 @@ - 1925 + 1926 - 1925 + 1926 cmos1_pclk @@ -1421,14 +1427,14 @@ clk_50m YES Timed - 10.855 + 10.354 0.000 0 - 9690 - 0.182 + 9685 + 0.201 0.000 0 - 9690 + 9685 clk_720p60Hz @@ -1452,137 +1458,179 @@ - 325 + 324 - 325 + 324 - eth_rxc clk_200m - NO + clk_200m + YES + Timed + 1.121 + 0.000 + 0 + 327 + 0.315 + 0.000 + 0 + 327 + + + clk_720p60Hz + clk_200m + YES Asynchronous Groups - 10 + 3 - 10 + 3 - clk_50m + ddrphy_clkin clk_200m YES Asynchronous Groups - 3 + 45 - 3 + 45 - clk_200m - clk_200m - YES - Timed - -0.788 - -18.651 - 44 - 3944 - 0.241 - 0.000 - 0 - 3944 - - - clk_10m - clk_200m + clk_50m + clk_25m YES Asynchronous Groups - 3 + 26 - 3 + 26 - clk_720p60Hz - clk_200m + clk_25m + clk_25m + YES + Timed + 35.501 + 0.000 + 0 + 30 + 0.550 + 0.000 + 0 + 30 + + + clk_10m + clk_10m YES + Timed + 94.588 + 0.000 + 0 + 1093 + 0.287 + 0.000 + 0 + 1093 + + + eth_rxc + clk_1080p60Hz + NO Asynchronous Groups - 20 + 10 - 20 + 10 - ddrphy_clkin - clk_200m + clk_50m + clk_1080p60Hz YES Asynchronous Groups - 98 + 3 - 98 + 3 - clk_50m - clk_25m + clk_10m + clk_1080p60Hz YES Asynchronous Groups - 26 + 3 - 26 + 3 - clk_25m - clk_25m + clk_1080p60Hz + clk_1080p60Hz YES Timed - 35.419 + 1.083 0.000 0 - 30 - 0.575 + 3630 + 0.212 0.000 0 - 30 + 3630 - clk_10m - clk_10m + clk_720p60Hz + clk_1080p60Hz YES - Timed - 94.174 - 0.000 - 0 - 1100 - 0.314 - 0.000 - 0 - 1100 + Asynchronous Groups + + + + 17 + + + + 17 + + + ddrphy_clkin + clk_1080p60Hz + YES + Asynchronous Groups + + + + 53 + + + + 53 eth_rxc @@ -1599,43 +1647,43 @@ 111 - clk_200m + clk_10m clk_720p60Hz YES Asynchronous Groups - 16 + 3 - 16 + 3 - clk_10m + clk_1080p60Hz clk_720p60Hz YES Asynchronous Groups - 3 + 16 - 3 + 16 clk_720p60Hz clk_720p60Hz YES Timed - 5.450 + 5.988 0.000 0 5503 - 0.313 + 0.314 0.000 0 5503 @@ -1673,14 +1721,14 @@ clk_20k YES Timed - 49995.048 + 49994.611 0.000 0 - 181 - 0.376 + 177 + 0.372 0.000 0 - 181 + 177 hdmi_in_clk @@ -1718,25 +1766,39 @@ - 1841 + 1814 - 1841 + 1814 + + + clk_1080p60Hz + ddrphy_clkin + YES + Asynchronous Groups + + + + 27 + + + + 27 ddrphy_clkin ddrphy_clkin YES Timed - 0.348 + 2.472 0.000 0 - 20762 - 0.149 + 20855 + 0.161 0.000 0 - 20762 + 20855 clk_200m @@ -1865,7 +1927,7 @@ 3
- +
Launch Clock Capture Clock @@ -1874,37 +1936,37 @@ Failing Endpoints Total Endpoints - - clk_200m - clk_200m - -0.788 - -18.651 - 44 - 3769 + + eth_rxc + eth_rxc + 1.026 + 0.000 + 0 + 5918 - ddrphy_clkin - ddrphy_clkin - 0.348 + clk_1080p60Hz + clk_1080p60Hz + 1.083 0.000 0 - 18193 + 3524 - eth_rxc - eth_rxc - 1.077 + clk_200m + clk_200m + 1.121 0.000 0 - 5907 + 258 - hdmi_in_clk - hdmi_in_clk - 1.130 + ioclk0 + ioclk0 + 1.692 0.000 0 - 311 + 24 ioclk1 @@ -1915,49 +1977,57 @@ 72 - ioclk0 - ioclk0 - 1.692 + hdmi_in_clk + hdmi_in_clk + 1.839 0.000 0 - 24 + 311 - cmos2_pclk - cmos2_pclk - 4.291 + ddrphy_clkin + ddrphy_clkin + 2.472 0.000 0 - 251 + 18286 - clk_720p60Hz - clk_720p60Hz - 5.450 + cmos2_pclk + cmos2_pclk + 4.347 0.000 0 - 4786 + 251 cmos1_pclk cmos1_pclk - 5.696 + 5.305 0.000 0 251 + + clk_720p60Hz + clk_720p60Hz + 5.988 + 0.000 + 0 + 4786 + clk_50m clk_50m - 10.855 + 10.354 0.000 0 - 9498 + 9493 clk_25m clk_25m - 35.419 + 35.501 0.000 0 30 @@ -1965,18 +2035,18 @@ clk_10m clk_10m - 94.174 + 94.588 0.000 0 - 1099 + 1092 clk_20k clk_20k - 49995.048 + 49994.611 0.000 0 - 181 + 177
@@ -1988,82 +2058,90 @@ Failing EndpointsTotal Endpoints + + eth_rxc + eth_rxc + 0.157 + 0.000 + 0 + 5918 + ddrphy_clkin ddrphy_clkin - 0.149 + 0.161 0.000 0 - 18193 + 18286 - clk_50m - clk_50m - 0.182 + cmos1_pclk + cmos1_pclk + 0.175 0.000 0 - 9498 + 251 hdmi_in_clk hdmi_in_clk - 0.191 + 0.189 0.000 0 311 - cmos1_pclk - cmos1_pclk - 0.199 + clk_50m + clk_50m + 0.201 0.000 0 - 251 + 9493 - clk_200m - clk_200m - 0.241 + clk_1080p60Hz + clk_1080p60Hz + 0.212 0.000 0 - 3769 + 3524 - clk_720p60Hz - clk_720p60Hz - 0.313 + clk_10m + clk_10m + 0.287 0.000 0 - 4786 + 1092 - clk_10m - clk_10m + clk_720p60Hz + clk_720p60Hz 0.314 0.000 0 - 1099 + 4786 - clk_20k - clk_20k - 0.376 + clk_200m + clk_200m + 0.315 0.000 0 - 181 + 258 - eth_rxc - eth_rxc - 0.381 + clk_20k + clk_20k + 0.372 0.000 0 - 5907 + 177 cmos2_pclk cmos2_pclk - 0.415 + 0.407 0.000 0 251 @@ -2087,7 +2165,7 @@ clk_25m clk_25m - 0.575 + 0.550 0.000 0 30 @@ -2105,15 +2183,23 @@ clk_200m clk_200m - 1.103 + 1.149 + 0.000 + 0 + 69 + + + clk_1080p60Hz + clk_1080p60Hz + 3.268 0.000 0 - 175 + 106 ddrphy_clkin ddrphy_clkin - 5.474 + 5.676 0.000 0 2569 @@ -2121,7 +2207,7 @@ clk_720p60Hz clk_720p60Hz - 8.580 + 8.940 0.000 0 717 @@ -2129,7 +2215,7 @@ clk_50m clk_50m - 16.039 + 15.776 0.000 0 192 @@ -2137,7 +2223,7 @@ clk_10m clk_10m - 97.793 + 97.797 0.000 0 1 @@ -2155,15 +2241,15 @@ clk_200m clk_200m - 0.554 + 0.555 0.000 0 - 175 + 69 clk_50m clk_50m - 0.555 + 0.610 0.000 0 192 @@ -2171,7 +2257,7 @@ ddrphy_clkin ddrphy_clkin - 0.779 + 0.637 0.000 0 2569 @@ -2179,15 +2265,23 @@ clk_720p60Hz clk_720p60Hz - 1.244 + 0.984 0.000 0 717 + + clk_1080p60Hz + clk_1080p60Hz + 1.249 + 0.000 + 0 + 106 + clk_10m clk_10m - 1.312 + 1.263 0.000 0 1 @@ -2209,25 +2303,32 @@ 27 - ioclk0 + ioclk2 0.397 0.000 0 - 11 + 2 - ioclk2 + ioclk0 0.397 0.000 0 - 2 + 11 clk_200m - 1.362 + 1.880 + 0.000 + 0 + 75 + + + clk_1080p60Hz + 2.230 0.000 0 - 825 + 750 hdmi_in_clk @@ -2241,7 +2342,7 @@ 2.483 0.000 0 - 1861 + 1862 ddrphy_clkin @@ -2258,14 +2359,14 @@ 1 - cmos1_pclk + cmos2_pclk 5.052 0.000 0 118 - cmos2_pclk + cmos1_pclk 5.052 0.000 0 @@ -2283,11 +2384,11 @@ 8.862 0.000 0 - 2517 + 2516 clk_25m - 19.580 + 19.380 0.000 0 26 @@ -2328,7 +2429,7 @@ u_sys_pll/u_pll_e3/goppll/CLKIN1 (2.688, 3.103, 2.143, 2.449) - clk_50m (50.00MHZ) (drive 2517 loads) + clk_50m (50.00MHZ) (drive 2516 loads) u_sys_pll/u_pll_e3/goppll/CLKOUT0 (2.788, 3.210, 2.246, 2.553) @@ -2346,244 +2447,244 @@ camera_vs_ff1/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/m_result_data[0]/opit_0_A2Q1/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/m_result_data[0]/opit_0_A2Q1/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/m_result_data[2]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/m_result_data[2]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/m_result_data[4]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/m_result_data[4]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][0][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][0][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][0][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][0][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][0][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][0][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][0][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][0][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][0][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][0][4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][1][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][1][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][1][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][1][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][1][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][1][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][1][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][1][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][1][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][1][4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][2][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][2][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][2][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][2][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][2][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][2][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][2][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][2][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][2][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][2][4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][0][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][0][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][0][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][0][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][0][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][0][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][0][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][0][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][0][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][0][4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][1][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][1][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][1][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][1][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][1][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][1][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][1][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][1][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][1][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][1][4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][2][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][2][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][2][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][2][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][2][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][2][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][2][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][2][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][2][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][2][4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][0][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][0][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][0][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][0][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][0][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][0][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][0][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][0][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][0][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][0][4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][1][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][1][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][1][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][1][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][1][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][1][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][1][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][1][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][1][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][1][4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][2][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][2][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][2][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][2][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][2][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][2][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][2][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][2][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][2][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][2][4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[6]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[7]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum1x4[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum1x4[2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum1x4[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum1x4[3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum1x4[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum1x4[4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum1x4[5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum1x4[5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum1x4[6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum1x4[6]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x1[1]/opit_0_A2Q1/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x1[1]/opit_0_A2Q1/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x1[3]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x1[3]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x1[5]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x1[5]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x1[6]/opit_0_AQ/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x1[6]/opit_0_AQ/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x2[1]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x2[1]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x2[3]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x2[3]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x2[5]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x2[5]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x2[6]/opit_0_AQ/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x2[6]/opit_0_AQ/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum8[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum8[1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum8[3]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum8[3]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum8[5]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum8[5]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum8[7]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum8[7]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum8[8]/opit_0_AQ/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum8[8]/opit_0_AQ/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/m_result_data[0]/opit_0_A2Q1/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/m_result_data[0]/opit_0_A2Q1/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/m_result_data[2]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/m_result_data[2]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/m_result_data[4]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/m_result_data[4]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/m_result_data[5]/opit_0_AQ_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/m_result_data[5]/opit_0_AQ/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][0][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][0][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][0][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][0][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][0][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][0][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][0][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) @@ -2595,31 +2696,31 @@ image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][0][5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][1][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][1][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][1][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][1][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][1][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][1][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][1][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][1][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][1][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][1][4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][1][5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][1][5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][2][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][2][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][2][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][2][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][2][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][2][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][2][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) @@ -2628,70 +2729,70 @@ image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][2][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][2][5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][2][5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][0][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][0][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][0][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][0][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][0][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][0][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][0][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][0][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][0][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][0][5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][0][5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][1][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][1][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][1][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][1][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][1][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][1][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][1][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][1][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][1][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][1][4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][1][5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][1][5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][2][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][2][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][2][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][2][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][2][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][2][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][2][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][2][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][2][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][2][4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][2][5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][2][5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][0][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][0][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][0][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][0][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][0][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][0][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][0][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) @@ -2703,121 +2804,121 @@ image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][0][5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][1][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][1][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][1][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][1][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][1][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][1][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][1][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][1][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][1][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][1][4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][1][5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][1][5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][2][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][2][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][2][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][2][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][2][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][2][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][2][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][2][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][2][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][2][5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][2][5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[6]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[7]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[8]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[8]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum1x4[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum1x4[2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum1x4[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum1x4[3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum1x4[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum1x4[4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum1x4[5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum1x4[5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum1x4[6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum1x4[6]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum1x4[7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum1x4[7]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x1[1]/opit_0_A2Q1/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x1[1]/opit_0_A2Q1/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x1[3]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x1[3]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x1[5]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x1[5]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x1[7]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x1[7]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x2[1]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x2[1]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x2[3]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x2[3]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x2[5]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x2[5]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x2[7]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x2[7]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum8[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum8[1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum8[3]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum8[3]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum8[5]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum8[5]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum8[7]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum8[7]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum8[9]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum8[9]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/m_result_data[0]/opit_0_A2Q1/CLK (5.378, 5.873, 4.857, 5.241) @@ -3039,370 +3140,370 @@ image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum8[8]/opit_0_AQ/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst/hybrid_filter_inst/m_result_valid/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/m_result_valid/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/max[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/max[0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/max[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/max[1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/max[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/max[2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/max[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/max[3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/max[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/max[4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_max[0]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_max[0]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_max[1]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_max[1]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_max[2]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_max[2]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_max[3]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_max[3]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_max[4]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_max[4]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_min[0]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_min[0]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_min[1]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_min[1]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_min[2]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_min[2]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_min[3]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_min[3]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_min[4]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_min[4]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/med[0]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/med[0]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/med[1]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/med[1]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/med[2]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/med[2]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/med[3]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/med[3]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/med[4]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/med[4]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/med_of_vector_med[0]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/med_of_vector_med[0]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/med_of_vector_med[1]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/med_of_vector_med[1]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/med_of_vector_med[2]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/med_of_vector_med[2]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/med_of_vector_med[3]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/med_of_vector_med[3]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/med_of_vector_med[4]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/med_of_vector_med[4]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/min[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/min[0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/min[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/min[1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/min[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/min[2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/min[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/min[3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/min[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/min[4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_max[0]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_max[0]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_max[1]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_max[1]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_max[2]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_max[2]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_max[3]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_max[3]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_max[4]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_max[4]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_min[0]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_min[0]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_min[1]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_min[1]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_min[2]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_min[2]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_min[3]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_min[3]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_min[4]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_min[4]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[5]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[5]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[5]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[5]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[5]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[5]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[5]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[5]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[5]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[5]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[5]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[5]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) @@ -3411,16 +3512,16 @@ image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[5]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[5]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) @@ -3441,88 +3542,88 @@ image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[5]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[5]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[5]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max[0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max[1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max[2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max[3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max[4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max[5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max[5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_max[0]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_max[0]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_max[1]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_max[1]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_max[2]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_max[2]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_max[3]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_max[3]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_max[4]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_max[4]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_max[5]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_max[5]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_min[0]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_min[0]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_min[1]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_min[1]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_min[2]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_min[2]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_min[3]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_min[3]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_min[4]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_min[4]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_min[5]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_min[5]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst/hybrid_filter_inst/median_finder9_g/med[0]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/med[1]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/med[1]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/med[2]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/med[2]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/med[3]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/med[3]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst/hybrid_filter_inst/median_finder9_g/med[4]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) @@ -3549,22 +3650,22 @@ image_filiter_inst/hybrid_filter_inst/median_finder9_g/med_of_vector_med[5]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min[0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min[1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min[2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min[3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min[4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min[5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min[5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_max[0]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) @@ -3573,34 +3674,34 @@ image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_max[1]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_max[2]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_max[2]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_max[3]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_max[3]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_max[4]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_max[4]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_max[5]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_max[5]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_min[0]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_min[0]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_min[1]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_min[1]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_min[2]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_min[2]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_min[3]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_min[3]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_min[4]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_min[4]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_min[5]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_min[5]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) @@ -3717,7 +3818,7 @@ image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/opit_0_L5Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) @@ -3858,37 +3959,37 @@ image_filiter_inst/hybrid_filter_inst/median_finder9_r/min_of_vector_min[4]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst/hybrid_filter_inst/pixel_ff[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/pixel_ff[0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/pixel_ff[1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/pixel_ff[2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/pixel_ff[3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/pixel_ff[4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/pixel_ff[5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/pixel_ff[6]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/pixel_ff[7]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[8]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/pixel_ff[8]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[9]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/pixel_ff[9]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[10]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/pixel_ff[10]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst/hybrid_filter_inst/pixel_ff[11]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) @@ -3906,37 +4007,37 @@ image_filiter_inst/hybrid_filter_inst/pixel_ff[15]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst/hybrid_filter_inst/pixel_ff[16]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/pixel_ff[16]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[17]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/pixel_ff[17]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[18]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/pixel_ff[18]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[19]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/pixel_ff[19]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[20]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/pixel_ff[20]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[21]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/pixel_ff[21]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[22]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/pixel_ff[22]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[23]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/pixel_ff[23]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[24]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/pixel_ff[24]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[25]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/pixel_ff[25]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[26]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/pixel_ff[26]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst/hybrid_filter_inst/pixel_ff[27]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) @@ -3954,37 +4055,37 @@ image_filiter_inst/hybrid_filter_inst/pixel_ff[31]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst/hybrid_filter_inst/pixel_ff[32]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/pixel_ff[32]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[33]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/pixel_ff[33]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[34]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/pixel_ff[34]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[35]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/pixel_ff[35]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[36]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/pixel_ff[36]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[37]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/pixel_ff[37]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[38]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/pixel_ff[38]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[39]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/pixel_ff[39]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[40]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/pixel_ff[40]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[41]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/pixel_ff[41]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[42]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/pixel_ff[42]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst/hybrid_filter_inst/pixel_ff[43]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) @@ -4002,37 +4103,37 @@ image_filiter_inst/hybrid_filter_inst/pixel_ff[47]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst/hybrid_filter_inst/raw_res_b[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/raw_res_b[0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/raw_res_b[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/raw_res_b[1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/raw_res_b[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/raw_res_b[2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/raw_res_b[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/raw_res_b[3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/raw_res_b[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/raw_res_b[4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/raw_res_g[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/raw_res_g[0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/raw_res_g[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/raw_res_g[1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/raw_res_g[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/raw_res_g[2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/raw_res_g[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/raw_res_g[3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/raw_res_g[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/raw_res_g[4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/raw_res_g[5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/raw_res_g[5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst/hybrid_filter_inst/raw_res_r[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) @@ -4050,37 +4151,37 @@ image_filiter_inst/hybrid_filter_inst/raw_res_r[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst/hybrid_filter_inst/res_b[0]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/res_b[0]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/res_b[1]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/res_b[1]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/res_b[2]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/res_b[2]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/res_b[3]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/res_b[3]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/res_b[4]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/res_b[4]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/res_g[0]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/res_g[0]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/res_g[1]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/res_g[1]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/res_g[2]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/res_g[2]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/res_g[3]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/res_g[3]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/res_g[4]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/res_g[4]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/res_g[5]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/res_g[5]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst/hybrid_filter_inst/res_r[0]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) @@ -4098,244 +4199,244 @@ image_filiter_inst/hybrid_filter_inst/res_r[4]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst/hybrid_filter_inst/valid_d[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/valid_d[0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/valid_d[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/valid_d[1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/valid_d[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/valid_d[2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/valid_d[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/hybrid_filter_inst/valid_d[3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[11]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[11]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[11]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[11]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[11]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[11]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[11]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[11]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/hor_cnt[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/hor_cnt[0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/hor_cnt[2]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/hor_cnt[2]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/hor_cnt[4]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/hor_cnt[4]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/hor_cnt[6]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/hor_cnt[6]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/hor_cnt[7]/opit_0_A2Q0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/hor_cnt[7]/opit_0_A2Q0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/hor_cnt[8]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/hor_cnt[8]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/hor_cnt[9]/opit_0_A2Q0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/hor_cnt[9]/opit_0_A2Q0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/hor_cnt[10]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/hor_cnt[10]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/m_pixel_valid/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/m_pixel_valid/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/rst_s1/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/rst_s1/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[2]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[2]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[4]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[4]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[6]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[6]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[8]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[8]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[10]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[10]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/tail_ver_cnt[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/tail_ver_cnt[0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/tail_ver_cnt[2]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/tail_ver_cnt[2]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/tail_ver_cnt[4]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/tail_ver_cnt[4]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/tail_ver_cnt[5]/opit_0_AQ_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/tail_ver_cnt[5]/opit_0_AQ_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/ver_cnt[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/ver_cnt[0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/ver_cnt[2]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/ver_cnt[2]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/ver_cnt[3]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/ver_cnt[3]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/ver_cnt[4]/opit_0_A2Q1/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/ver_cnt[4]/opit_0_A2Q1/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/ver_cnt[5]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/ver_cnt[5]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/ver_cnt[6]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/ver_cnt[6]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/ver_cnt[7]/opit_0_A2Q0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/ver_cnt[7]/opit_0_A2Q0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/ver_cnt[8]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/multiline_buffer_inst/ver_cnt[8]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][0][0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[0][0][0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][0][1]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[0][0][1]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][0][2]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[0][0][2]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][0][3]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[0][0][3]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][0][4]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[0][0][4]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][0][5]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[0][0][5]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][0][6]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[0][0][6]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][0][7]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[0][0][7]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][0][8]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[0][0][8]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst/vector_to_matrix_inst/mat[0][0][9]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst/vector_to_matrix_inst/mat[0][0][10]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[0][0][10]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst/vector_to_matrix_inst/mat[0][0][11]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) @@ -4353,37 +4454,37 @@ image_filiter_inst/vector_to_matrix_inst/mat[0][0][15]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst/vector_to_matrix_inst/mat[0][1][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[0][1][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][1][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[0][1][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][1][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[0][1][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][1][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[0][1][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][1][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[0][1][4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][1][5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[0][1][5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][1][6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[0][1][6]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][1][7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[0][1][7]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][1][8]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[0][1][8]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][1][9]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[0][1][9]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][1][10]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[0][1][10]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst/vector_to_matrix_inst/mat[0][1][11]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) @@ -4401,28 +4502,28 @@ image_filiter_inst/vector_to_matrix_inst/mat[0][1][15]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst/vector_to_matrix_inst/mat[0][2][0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[0][2][0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][2][1]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[0][2][1]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][2][2]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[0][2][2]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][2][3]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[0][2][3]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][2][4]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[0][2][4]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][2][5]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[0][2][5]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][2][6]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[0][2][6]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][2][7]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[0][2][7]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst/vector_to_matrix_inst/mat[0][2][8]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) @@ -4431,7 +4532,7 @@ image_filiter_inst/vector_to_matrix_inst/mat[0][2][9]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst/vector_to_matrix_inst/mat[0][2][10]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[0][2][10]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst/vector_to_matrix_inst/mat[0][2][11]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) @@ -4449,37 +4550,37 @@ image_filiter_inst/vector_to_matrix_inst/mat[0][2][15]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst/vector_to_matrix_inst/mat[1][0][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[1][0][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][0][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[1][0][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][0][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[1][0][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][0][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[1][0][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][0][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[1][0][4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][0][5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[1][0][5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][0][6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[1][0][6]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][0][7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[1][0][7]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][0][8]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[1][0][8]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][0][9]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[1][0][9]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][0][10]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[1][0][10]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst/vector_to_matrix_inst/mat[1][0][11]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) @@ -4497,37 +4598,37 @@ image_filiter_inst/vector_to_matrix_inst/mat[1][0][15]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst/vector_to_matrix_inst/mat[1][1][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[1][1][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][1][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[1][1][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][1][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[1][1][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][1][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[1][1][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][1][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[1][1][4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][1][5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[1][1][5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][1][6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[1][1][6]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][1][7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[1][1][7]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][1][8]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[1][1][8]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][1][9]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[1][1][9]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][1][10]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[1][1][10]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst/vector_to_matrix_inst/mat[1][1][11]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) @@ -4545,37 +4646,37 @@ image_filiter_inst/vector_to_matrix_inst/mat[1][1][15]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst/vector_to_matrix_inst/mat[1][2][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[1][2][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][2][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[1][2][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][2][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[1][2][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][2][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[1][2][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][2][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[1][2][4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][2][5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[1][2][5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][2][6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[1][2][6]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][2][7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[1][2][7]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][2][8]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[1][2][8]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][2][9]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[1][2][9]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][2][10]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[1][2][10]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst/vector_to_matrix_inst/mat[1][2][11]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) @@ -4593,37 +4694,37 @@ image_filiter_inst/vector_to_matrix_inst/mat[1][2][15]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst/vector_to_matrix_inst/mat[2][0][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[2][0][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[2][0][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[2][0][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[2][0][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[2][0][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[2][0][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[2][0][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[2][0][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[2][0][4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[2][0][5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[2][0][5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[2][0][6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[2][0][6]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[2][0][7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[2][0][7]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[2][0][8]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[2][0][8]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst/vector_to_matrix_inst/mat[2][0][9]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst/vector_to_matrix_inst/mat[2][0][10]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[2][0][10]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst/vector_to_matrix_inst/mat[2][0][11]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) @@ -4641,37 +4742,37 @@ image_filiter_inst/vector_to_matrix_inst/mat[2][0][15]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst/vector_to_matrix_inst/mat[2][1][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[2][1][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[2][1][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[2][1][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[2][1][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[2][1][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[2][1][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[2][1][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[2][1][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[2][1][4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[2][1][5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[2][1][5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[2][1][6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[2][1][6]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[2][1][7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[2][1][7]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[2][1][8]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[2][1][8]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[2][1][9]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[2][1][9]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[2][1][10]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[2][1][10]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst/vector_to_matrix_inst/mat[2][1][11]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) @@ -4689,37 +4790,37 @@ image_filiter_inst/vector_to_matrix_inst/mat[2][1][15]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst/vector_to_matrix_inst/mat[2][2][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[2][2][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[2][2][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[2][2][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[2][2][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[2][2][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[2][2][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[2][2][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[2][2][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[2][2][4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[2][2][5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[2][2][5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[2][2][6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[2][2][6]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[2][2][7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[2][2][7]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[2][2][8]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[2][2][8]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst/vector_to_matrix_inst/mat[2][2][9]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst/vector_to_matrix_inst/mat[2][2][10]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/mat[2][2][10]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst/vector_to_matrix_inst/mat[2][2][11]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) @@ -4737,481 +4838,481 @@ image_filiter_inst/vector_to_matrix_inst/mat[2][2][15]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst/vector_to_matrix_inst/valid_d/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst/vector_to_matrix_inst/valid_d/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/m_result_data[0]/opit_0_A2Q1/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/m_result_data[0]/opit_0_A2Q1/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/m_result_data[2]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/m_result_data[2]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/m_result_data[4]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/m_result_data[4]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][0][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][0][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][0][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][0][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][0][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][0][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][0][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][0][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][0][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][0][4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][1][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][1][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][1][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][1][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][1][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][1][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][1][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][1][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][1][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][1][4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][2][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][2][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][2][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][2][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][2][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][2][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][2][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][2][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][2][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][2][4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][0][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][0][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][0][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][0][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][0][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][0][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][0][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][0][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][0][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][0][4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][1][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][1][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][1][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][1][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][1][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][1][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][1][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][1][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][1][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][1][4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][2][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][2][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][2][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][2][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][2][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][2][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][2][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][2][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][2][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][2][4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][0][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][0][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][0][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][0][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][0][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][0][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][0][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][0][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][0][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][0][4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][1][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][1][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][1][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][1][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][1][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][1][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][1][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][1][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][1][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][1][4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][2][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][2][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][2][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][2][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][2][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][2][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][2][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][2][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][2][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][2][4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[6]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[7]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum1x4[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum1x4[2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum1x4[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum1x4[3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum1x4[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum1x4[4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum1x4[5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum1x4[5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum1x4[6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum1x4[6]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x1[1]/opit_0_A2Q1/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x1[1]/opit_0_A2Q1/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x1[3]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x1[3]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x1[5]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x1[5]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x1[6]/opit_0_AQ/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x1[6]/opit_0_AQ/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x2[1]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x2[1]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x2[3]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x2[3]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x2[5]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x2[5]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x2[6]/opit_0_AQ/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x2[6]/opit_0_AQ/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum8[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum8[1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum8[3]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum8[3]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum8[5]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum8[5]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum8[7]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum8[7]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum8[8]/opit_0_AQ/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum8[8]/opit_0_AQ/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/m_result_data[0]/opit_0_A2Q1/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/m_result_data[0]/opit_0_A2Q1/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/m_result_data[2]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/m_result_data[2]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/m_result_data[4]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/m_result_data[4]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/m_result_data[5]/opit_0_AQ/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/m_result_data[5]/opit_0_AQ/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][0][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][0][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][0][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][0][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][0][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][0][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][0][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][0][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][0][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][0][4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][0][5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][0][5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][1][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][1][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][1][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][1][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][1][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][1][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][1][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][1][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][1][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][1][4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][1][5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][1][5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][2][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][2][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][2][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][2][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][2][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][2][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][2][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][2][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][2][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][2][4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][2][5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][2][5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][0][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][0][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][0][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][0][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][0][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][0][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][0][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][0][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][0][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][0][4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][0][5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][0][5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][1][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][1][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][1][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][1][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][1][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][1][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][1][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][1][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][1][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][1][4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][1][5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][1][5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][2][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][2][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][2][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][2][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][2][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][2][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][2][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][2][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][2][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][2][4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][2][5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][2][5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][0][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][0][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][0][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][0][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][0][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][0][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][0][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][0][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][0][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][0][4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][0][5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][0][5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][1][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][1][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][1][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][1][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][1][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][1][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][1][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][1][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][1][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][1][4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][1][5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][1][5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][2][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][2][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][2][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][2][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][2][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][2][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][2][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][2][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][2][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][2][4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][2][5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][2][5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[6]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[7]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[8]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[8]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum1x4[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum1x4[2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum1x4[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum1x4[3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum1x4[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum1x4[4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum1x4[5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum1x4[5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum1x4[6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum1x4[6]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum1x4[7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum1x4[7]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x1[1]/opit_0_A2Q1/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x1[1]/opit_0_A2Q1/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x1[3]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x1[3]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x1[5]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x1[5]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x1[7]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x1[7]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x2[1]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x2[1]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x2[3]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x2[3]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x2[5]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x2[5]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x2[7]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x2[7]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum8[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum8[1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum8[3]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum8[3]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum8[5]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum8[5]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum8[7]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum8[7]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum8[9]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum8[9]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/m_result_data[0]/opit_0_A2Q1/CLK (5.378, 5.873, 4.857, 5.241) @@ -5436,421 +5537,421 @@ image_filiter_inst2/hybrid_filter_inst/m_result_valid/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max[0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max[1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max[2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max[3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max[4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_max[0]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_max[0]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_max[1]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_max[1]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_max[2]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_max[2]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_max[3]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_max[3]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_max[4]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_max[4]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_min[0]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_min[0]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_min[1]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_min[1]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_min[2]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_min[2]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_min[3]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_min[3]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_min[4]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_min[4]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med[0]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med[0]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med[1]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med[1]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med[2]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med[2]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med[3]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med[3]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med[4]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med[4]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med_of_vector_med[0]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med_of_vector_med[0]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med_of_vector_med[1]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med_of_vector_med[1]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med_of_vector_med[2]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med_of_vector_med[2]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med_of_vector_med[3]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med_of_vector_med[3]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med_of_vector_med[4]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med_of_vector_med[4]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min[0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min[1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min[2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min[3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min[4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_max[0]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_max[0]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_max[1]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_max[1]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_max[2]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_max[2]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_max[3]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_max[3]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_max[4]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_max[4]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_min[0]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_min[0]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_min[1]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_min[1]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_min[2]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_min[2]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_min[3]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_min[3]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_min[4]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_min[4]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[5]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[5]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[5]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[5]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[5]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[5]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[5]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[5]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[5]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[5]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[5]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[5]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[5]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[5]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[5]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[5]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[5]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[5]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) @@ -5865,10 +5966,10 @@ image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max[4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max[5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max[5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_max[0]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) @@ -5883,28 +5984,28 @@ image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_max[3]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_max[4]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_max[4]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_max[5]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_max[5]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_min[0]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_min[0]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_min[1]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_min[1]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_min[2]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_min[2]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_min[3]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_min[3]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_min[4]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_min[4]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_min[5]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_min[5]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med[0]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) @@ -5925,40 +6026,40 @@ image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med[5]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med_of_vector_med[0]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med_of_vector_med[0]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med_of_vector_med[1]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med_of_vector_med[1]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med_of_vector_med[2]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med_of_vector_med[2]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med_of_vector_med[3]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med_of_vector_med[3]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med_of_vector_med[4]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med_of_vector_med[4]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med_of_vector_med[5]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med_of_vector_med[5]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min[0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min[2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min[3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min[4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min[5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min[5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_max[0]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) @@ -5973,28 +6074,28 @@ image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_max[3]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_max[4]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_max[4]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_max[5]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_max[5]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_min[0]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_min[0]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_min[1]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_min[1]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_min[2]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_min[2]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_min[3]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_min[3]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_min[4]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_min[4]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_min[5]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_min[5]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) @@ -6252,37 +6353,37 @@ image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min_of_vector_min[4]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst2/hybrid_filter_inst/pixel_ff[6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[7]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[8]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[8]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[9]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[9]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[10]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[10]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst2/hybrid_filter_inst/pixel_ff[11]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) @@ -6300,37 +6401,37 @@ image_filiter_inst2/hybrid_filter_inst/pixel_ff[15]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[16]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[16]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[17]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[17]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[18]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[18]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[19]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[19]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[20]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[20]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[21]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[21]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst2/hybrid_filter_inst/pixel_ff[22]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[23]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[23]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[24]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[24]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[25]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[25]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[26]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[26]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst2/hybrid_filter_inst/pixel_ff[27]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) @@ -6348,37 +6449,37 @@ image_filiter_inst2/hybrid_filter_inst/pixel_ff[31]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[32]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[32]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[33]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[33]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[34]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[34]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[35]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[35]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[36]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[36]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[37]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[37]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst2/hybrid_filter_inst/pixel_ff[38]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[39]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[39]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[40]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[40]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst2/hybrid_filter_inst/pixel_ff[41]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[42]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[42]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst2/hybrid_filter_inst/pixel_ff[43]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) @@ -6396,22 +6497,22 @@ image_filiter_inst2/hybrid_filter_inst/pixel_ff[47]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst2/hybrid_filter_inst/raw_res_b[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/raw_res_b[0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/raw_res_b[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/raw_res_b[1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/raw_res_b[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/raw_res_b[2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/raw_res_b[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/raw_res_b[3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/raw_res_b[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/raw_res_b[4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/raw_res_g[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/raw_res_g[0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst2/hybrid_filter_inst/raw_res_g[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) @@ -6444,19 +6545,19 @@ image_filiter_inst2/hybrid_filter_inst/raw_res_r[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst2/hybrid_filter_inst/res_b[0]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/res_b[0]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/res_b[1]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/res_b[1]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/res_b[2]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/res_b[2]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/res_b[3]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/res_b[3]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/hybrid_filter_inst/res_b[4]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/hybrid_filter_inst/res_b[4]/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst2/hybrid_filter_inst/res_g[0]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) @@ -6504,226 +6605,226 @@ image_filiter_inst2/hybrid_filter_inst/valid_d[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[11]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[11]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[11]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[11]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[11]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[11]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[11]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[11]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/hor_cnt[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/hor_cnt[0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/hor_cnt[2]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/hor_cnt[2]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/hor_cnt[4]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/hor_cnt[4]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/hor_cnt[6]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/hor_cnt[6]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/hor_cnt[7]/opit_0_A2Q0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/hor_cnt[7]/opit_0_A2Q0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/hor_cnt[8]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/hor_cnt[8]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/hor_cnt[9]/opit_0_A2Q0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/hor_cnt[9]/opit_0_A2Q0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/hor_cnt[10]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/hor_cnt[10]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/m_pixel_valid/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/m_pixel_valid/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[2]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[2]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[4]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[4]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[6]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[6]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[8]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[8]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[10]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[10]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[2]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[2]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[4]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[4]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[5]/opit_0_AQ_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[5]/opit_0_AQ/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/ver_cnt[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/ver_cnt[0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/ver_cnt[2]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/ver_cnt[2]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/ver_cnt[3]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/ver_cnt[3]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/ver_cnt[4]/opit_0_A2Q1/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/ver_cnt[4]/opit_0_A2Q1/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/ver_cnt[5]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/ver_cnt[5]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/ver_cnt[6]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/ver_cnt[6]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/ver_cnt[7]/opit_0_A2Q0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/ver_cnt[7]/opit_0_A2Q0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/multiline_buffer_inst/ver_cnt[8]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/multiline_buffer_inst/ver_cnt[8]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[0][0][0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[0][0][0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[0][0][1]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[0][0][1]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[0][0][2]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[0][0][2]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[0][0][3]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[0][0][3]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[0][0][4]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[0][0][4]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[0][0][5]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[0][0][5]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[0][0][6]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[0][0][6]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[0][0][7]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[0][0][7]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[0][0][8]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[0][0][8]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[0][0][9]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[0][0][9]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[0][0][10]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[0][0][10]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst2/vector_to_matrix_inst/mat[0][0][11]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) @@ -6741,37 +6842,37 @@ image_filiter_inst2/vector_to_matrix_inst/mat[0][0][15]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst2/vector_to_matrix_inst/mat[0][1][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[0][1][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[0][1][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[0][1][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[0][1][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[0][1][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[0][1][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[0][1][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[0][1][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[0][1][4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[0][1][5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[0][1][5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[0][1][6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[0][1][6]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[0][1][7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[0][1][7]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[0][1][8]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[0][1][8]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[0][1][9]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[0][1][9]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[0][1][10]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[0][1][10]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst2/vector_to_matrix_inst/mat[0][1][11]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) @@ -6789,37 +6890,37 @@ image_filiter_inst2/vector_to_matrix_inst/mat[0][1][15]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst2/vector_to_matrix_inst/mat[0][2][0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[0][2][0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[0][2][1]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[0][2][1]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[0][2][2]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[0][2][2]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[0][2][3]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[0][2][3]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[0][2][4]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[0][2][4]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[0][2][5]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[0][2][5]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[0][2][6]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[0][2][6]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[0][2][7]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[0][2][7]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[0][2][8]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[0][2][8]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[0][2][9]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[0][2][9]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[0][2][10]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[0][2][10]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst2/vector_to_matrix_inst/mat[0][2][11]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) @@ -6837,37 +6938,37 @@ image_filiter_inst2/vector_to_matrix_inst/mat[0][2][15]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst2/vector_to_matrix_inst/mat[1][0][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[1][0][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[1][0][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[1][0][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[1][0][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[1][0][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[1][0][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[1][0][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[1][0][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[1][0][4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[1][0][5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[1][0][5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[1][0][6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[1][0][6]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[1][0][7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[1][0][7]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[1][0][8]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[1][0][8]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[1][0][9]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[1][0][9]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[1][0][10]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[1][0][10]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst2/vector_to_matrix_inst/mat[1][0][11]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) @@ -6885,37 +6986,37 @@ image_filiter_inst2/vector_to_matrix_inst/mat[1][0][15]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst2/vector_to_matrix_inst/mat[1][1][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[1][1][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[1][1][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[1][1][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[1][1][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[1][1][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[1][1][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[1][1][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[1][1][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[1][1][4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[1][1][5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[1][1][5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[1][1][6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[1][1][6]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[1][1][7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[1][1][7]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[1][1][8]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[1][1][8]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[1][1][9]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[1][1][9]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[1][1][10]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[1][1][10]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst2/vector_to_matrix_inst/mat[1][1][11]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) @@ -6933,37 +7034,37 @@ image_filiter_inst2/vector_to_matrix_inst/mat[1][1][15]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst2/vector_to_matrix_inst/mat[1][2][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[1][2][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[1][2][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[1][2][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[1][2][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[1][2][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[1][2][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[1][2][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[1][2][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[1][2][4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[1][2][5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[1][2][5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[1][2][6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[1][2][6]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[1][2][7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[1][2][7]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[1][2][8]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[1][2][8]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[1][2][9]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[1][2][9]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[1][2][10]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[1][2][10]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst2/vector_to_matrix_inst/mat[1][2][11]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) @@ -6981,37 +7082,37 @@ image_filiter_inst2/vector_to_matrix_inst/mat[1][2][15]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst2/vector_to_matrix_inst/mat[2][0][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[2][0][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[2][0][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[2][0][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[2][0][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[2][0][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[2][0][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[2][0][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[2][0][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[2][0][4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[2][0][5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[2][0][5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[2][0][6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[2][0][6]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[2][0][7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[2][0][7]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[2][0][8]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[2][0][8]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[2][0][9]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[2][0][9]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[2][0][10]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[2][0][10]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst2/vector_to_matrix_inst/mat[2][0][11]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) @@ -7029,37 +7130,37 @@ image_filiter_inst2/vector_to_matrix_inst/mat[2][0][15]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst2/vector_to_matrix_inst/mat[2][1][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[2][1][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[2][1][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[2][1][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[2][1][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[2][1][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[2][1][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[2][1][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[2][1][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[2][1][4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[2][1][5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[2][1][5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[2][1][6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[2][1][6]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[2][1][7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[2][1][7]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[2][1][8]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[2][1][8]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[2][1][9]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[2][1][9]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[2][1][10]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[2][1][10]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst2/vector_to_matrix_inst/mat[2][1][11]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) @@ -7077,37 +7178,37 @@ image_filiter_inst2/vector_to_matrix_inst/mat[2][1][15]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst2/vector_to_matrix_inst/mat[2][2][0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[2][2][0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[2][2][1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[2][2][1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[2][2][2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[2][2][2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[2][2][3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[2][2][3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[2][2][4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[2][2][4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[2][2][5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[2][2][5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[2][2][6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[2][2][6]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[2][2][7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[2][2][7]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[2][2][8]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[2][2][8]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[2][2][9]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[2][2][9]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst2/vector_to_matrix_inst/mat[2][2][10]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + image_filiter_inst2/vector_to_matrix_inst/mat[2][2][10]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) image_filiter_inst2/vector_to_matrix_inst/mat[2][2][11]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) @@ -7128,148 +7229,148 @@ image_filiter_inst2/vector_to_matrix_inst/valid_d/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/rd3_data_valid0/opit_0_L5Q_perm/CLK (5.421, 5.918, 4.901, 5.286) + u_axi_ddr_top/rd3_data_valid0/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK (5.392, 5.888, 4.871, 5.256) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK (5.403, 5.899, 4.883, 5.268) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (5.400, 5.896, 4.879, 5.264) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (5.387, 5.882, 4.866, 5.250) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (5.400, 5.896, 4.879, 5.264) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (5.387, 5.882, 4.866, 5.250) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (5.394, 5.890, 4.874, 5.258) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (5.392, 5.888, 4.871, 5.256) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (5.394, 5.890, 4.874, 5.258) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (5.392, 5.888, 4.871, 5.256) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (5.389, 5.885, 4.868, 5.253) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (5.398, 5.894, 4.877, 5.262) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_A2Q21/CLK (5.389, 5.885, 4.868, 5.253) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_A2Q21/CLK (5.398, 5.894, 4.877, 5.262) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm/CLK (5.400, 5.896, 4.879, 5.264) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm/CLK (5.394, 5.890, 4.874, 5.258) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm/CLK (5.394, 5.890, 4.874, 5.258) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm/CLK (5.400, 5.896, 4.879, 5.264) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/CLK (5.394, 5.890, 4.874, 5.258) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/CLK (5.389, 5.885, 4.868, 5.253) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK (5.400, 5.896, 4.879, 5.264) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK (5.403, 5.899, 4.883, 5.268) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/CLK (5.400, 5.896, 4.879, 5.264) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/CLK (5.403, 5.899, 4.883, 5.268) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/CLK (5.394, 5.890, 4.874, 5.258) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/CLK (5.403, 5.899, 4.883, 5.268) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm/CLK (5.392, 5.888, 4.871, 5.256) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm/CLK (5.403, 5.899, 4.883, 5.268) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm/CLK (5.392, 5.888, 4.871, 5.256) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm/CLK (5.403, 5.899, 4.883, 5.268) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm/CLK (5.383, 5.879, 4.862, 5.247) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm/CLK (5.403, 5.899, 4.883, 5.268) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm/CLK (5.392, 5.888, 4.871, 5.256) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm/CLK (5.403, 5.899, 4.883, 5.268) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0/CLK (5.412, 5.909, 4.892, 5.277) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0/CLK (5.387, 5.882, 4.866, 5.250) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/opit_0/CLK (5.421, 5.918, 4.901, 5.286) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/opit_0/CLK (5.395, 5.891, 4.875, 5.260) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK (5.403, 5.899, 4.883, 5.268) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK (5.387, 5.882, 4.866, 5.250) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK (5.403, 5.899, 4.883, 5.268) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK (5.395, 5.891, 4.875, 5.260) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK (5.403, 5.899, 4.883, 5.268) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK (5.395, 5.891, 4.875, 5.260) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/CLK (5.421, 5.918, 4.901, 5.286) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/CLK (5.401, 5.897, 4.880, 5.265) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/opit_0/CLK (5.410, 5.906, 4.889, 5.274) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/opit_0/CLK (5.401, 5.897, 4.880, 5.265) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK (5.410, 5.906, 4.889, 5.274) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK (5.421, 5.918, 4.901, 5.286) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/opit_0/CLK (5.410, 5.906, 4.889, 5.274) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/opit_0/CLK (5.421, 5.918, 4.901, 5.286) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/opit_0/CLK (5.410, 5.906, 4.889, 5.274) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/opit_0/CLK (5.398, 5.894, 4.877, 5.262) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[10]/opit_0/CLK (5.392, 5.888, 4.871, 5.256) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[10]/opit_0/CLK (5.398, 5.894, 4.877, 5.262) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[11]/opit_0/CLK (5.392, 5.888, 4.871, 5.256) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[11]/opit_0/CLK (5.398, 5.894, 4.877, 5.262) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[0]/opit_0/CLK (5.412, 5.909, 4.892, 5.277) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[0]/opit_0/CLK (5.387, 5.882, 4.866, 5.250) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/CLK (5.421, 5.918, 4.901, 5.286) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/CLK (5.387, 5.882, 4.866, 5.250) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK (5.412, 5.909, 4.892, 5.277) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK (5.395, 5.891, 4.875, 5.260) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/CLK (5.412, 5.909, 4.892, 5.277) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/CLK (5.395, 5.891, 4.875, 5.260) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/CLK (5.403, 5.899, 4.883, 5.268) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/CLK (5.395, 5.891, 4.875, 5.260) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[5]/opit_0/CLK (5.421, 5.918, 4.901, 5.286) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[5]/opit_0/CLK (5.401, 5.897, 4.880, 5.265) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[6]/opit_0/CLK (5.403, 5.899, 4.883, 5.268) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[6]/opit_0/CLK (5.401, 5.897, 4.880, 5.265) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/CLK (5.392, 5.888, 4.871, 5.256) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/CLK (5.421, 5.918, 4.901, 5.286) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[8]/opit_0/CLK (5.392, 5.888, 4.871, 5.256) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[8]/opit_0/CLK (5.421, 5.918, 4.901, 5.286) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/CLK (5.392, 5.888, 4.871, 5.256) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/CLK (5.398, 5.894, 4.877, 5.262) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/CLK (5.392, 5.888, 4.871, 5.256) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/CLK (5.398, 5.894, 4.877, 5.262) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[11]/opit_0/CLK (5.383, 5.879, 4.862, 5.247) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[11]/opit_0/CLK (5.398, 5.894, 4.877, 5.262) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.434, 5.930, 4.913, 5.298) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.401, 5.897, 4.880, 5.265) u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.439, 5.936, 4.918, 5.304) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.401, 5.897, 4.880, 5.265) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.428, 5.925, 4.907, 5.293) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[3].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.407, 5.903, 4.886, 5.271) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[3].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.412, 5.909, 4.892, 5.277) u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0_A2Q1/CLK (5.378, 5.873, 4.857, 5.241) @@ -7500,364 +7601,364 @@ u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK (5.392, 5.888, 4.871, 5.256) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (5.400, 5.896, 4.879, 5.264) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (5.400, 5.896, 4.879, 5.264) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (5.389, 5.885, 4.868, 5.253) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (5.389, 5.885, 4.868, 5.253) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (5.383, 5.879, 4.862, 5.247) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_A2Q21/CLK (5.383, 5.879, 4.862, 5.247) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm/CLK (5.400, 5.896, 4.879, 5.264) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm/CLK (5.403, 5.899, 4.883, 5.268) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/CLK (5.400, 5.896, 4.879, 5.264) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK (5.400, 5.896, 4.879, 5.264) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/CLK (5.383, 5.879, 4.862, 5.247) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q/CLK (5.383, 5.879, 4.862, 5.247) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm/CLK (5.392, 5.888, 4.871, 5.256) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm/CLK (5.392, 5.888, 4.871, 5.256) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm/CLK (5.392, 5.888, 4.871, 5.256) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm/CLK (5.392, 5.888, 4.871, 5.256) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0/CLK (5.409, 5.905, 4.888, 5.273) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/opit_0/CLK (5.418, 5.914, 4.897, 5.282) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK (5.409, 5.905, 4.888, 5.273) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK (5.409, 5.905, 4.888, 5.273) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK (5.409, 5.905, 4.888, 5.273) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/CLK (5.398, 5.894, 4.877, 5.262) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/opit_0/CLK (5.409, 5.905, 4.888, 5.273) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK (5.392, 5.888, 4.871, 5.256) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/opit_0/CLK (5.392, 5.888, 4.871, 5.256) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/opit_0/CLK (5.392, 5.888, 4.871, 5.256) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[0]/opit_0/CLK (5.409, 5.905, 4.888, 5.273) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/CLK (5.409, 5.905, 4.888, 5.273) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK (5.403, 5.899, 4.883, 5.268) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/CLK (5.409, 5.905, 4.888, 5.273) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/CLK (5.409, 5.905, 4.888, 5.273) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[5]/opit_0/CLK (5.398, 5.894, 4.877, 5.262) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[6]/opit_0/CLK (5.409, 5.905, 4.888, 5.273) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/CLK (5.398, 5.894, 4.877, 5.262) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[8]/opit_0/CLK (5.392, 5.888, 4.871, 5.256) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[8]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/CLK (5.398, 5.894, 4.877, 5.262) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.428, 5.925, 4.907, 5.293) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.412, 5.909, 4.892, 5.277) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK (5.419, 5.915, 4.898, 5.284) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (5.409, 5.905, 4.888, 5.273) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (5.409, 5.905, 4.888, 5.273) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (5.398, 5.894, 4.877, 5.262) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (5.398, 5.894, 4.877, 5.262) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (5.392, 5.888, 4.871, 5.256) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_A2Q21/CLK (5.392, 5.888, 4.871, 5.256) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm/CLK (5.403, 5.899, 4.883, 5.268) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm/CLK (5.403, 5.899, 4.883, 5.268) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm/CLK (5.403, 5.899, 4.883, 5.268) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm/CLK (5.403, 5.899, 4.883, 5.268) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/CLK (5.416, 5.912, 4.895, 5.280) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK (5.416, 5.912, 4.895, 5.280) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/CLK (5.416, 5.912, 4.895, 5.280) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/CLK (5.387, 5.882, 4.866, 5.250) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm/CLK (5.387, 5.882, 4.866, 5.250) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm/CLK (5.387, 5.882, 4.866, 5.250) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm/CLK (5.387, 5.882, 4.866, 5.250) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm/CLK (5.383, 5.879, 4.862, 5.247) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0/CLK (5.421, 5.918, 4.901, 5.286) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/opit_0/CLK (5.400, 5.896, 4.879, 5.264) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK (5.421, 5.918, 4.901, 5.286) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK (5.436, 5.933, 4.915, 5.301) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK (5.421, 5.918, 4.901, 5.286) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/CLK (5.436, 5.933, 4.915, 5.301) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/opit_0/CLK (5.416, 5.912, 4.895, 5.280) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK (5.428, 5.925, 4.907, 5.293) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/opit_0/CLK (5.425, 5.921, 4.904, 5.289) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/opit_0/CLK (5.425, 5.921, 4.904, 5.289) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[10]/opit_0/CLK (5.419, 5.915, 4.898, 5.284) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[10]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[11]/opit_0/CLK (5.419, 5.915, 4.898, 5.284) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[11]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[0]/opit_0/CLK (5.436, 5.933, 4.915, 5.301) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/CLK (5.421, 5.918, 4.901, 5.286) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK (5.436, 5.933, 4.915, 5.301) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/CLK (5.421, 5.918, 4.901, 5.286) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/CLK (5.436, 5.933, 4.915, 5.301) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[5]/opit_0/CLK (5.428, 5.925, 4.907, 5.293) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[6]/opit_0/CLK (5.436, 5.933, 4.915, 5.301) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/CLK (5.428, 5.925, 4.907, 5.293) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[8]/opit_0/CLK (5.425, 5.921, 4.904, 5.289) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[8]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/CLK (5.428, 5.925, 4.907, 5.293) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/CLK (5.425, 5.921, 4.904, 5.289) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[11]/opit_0/CLK (5.419, 5.915, 4.898, 5.284) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[11]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKA (5.401, 5.897, 4.880, 5.265) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKA (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0/CLK (5.403, 5.899, 4.883, 5.268) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (5.387, 5.882, 4.866, 5.250) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (5.387, 5.882, 4.866, 5.250) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (5.392, 5.888, 4.871, 5.256) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (5.392, 5.888, 4.871, 5.256) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (5.398, 5.894, 4.877, 5.262) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm/CLK (5.392, 5.888, 4.871, 5.256) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm/CLK (5.383, 5.879, 4.862, 5.247) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm/CLK (5.410, 5.906, 4.889, 5.274) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm/CLK (5.389, 5.885, 4.868, 5.253) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm/CLK (5.389, 5.885, 4.868, 5.253) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm/CLK (5.389, 5.885, 4.868, 5.253) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm/CLK (5.389, 5.885, 4.868, 5.253) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/CLK (5.403, 5.899, 4.883, 5.268) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/CLK (5.403, 5.899, 4.883, 5.268) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0/CLK (5.398, 5.894, 4.877, 5.262) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/opit_0/CLK (5.392, 5.888, 4.871, 5.256) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/opit_0/CLK (5.392, 5.888, 4.871, 5.256) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/opit_0/CLK (5.410, 5.906, 4.889, 5.274) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/opit_0/CLK (5.398, 5.894, 4.877, 5.262) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/opit_0/CLK (5.410, 5.906, 4.889, 5.274) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/opit_0/CLK (5.398, 5.894, 4.877, 5.262) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/opit_0/CLK (5.403, 5.899, 4.883, 5.268) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK (5.403, 5.899, 4.883, 5.268) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/CLK (5.403, 5.899, 4.883, 5.268) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/CLK (5.410, 5.906, 4.889, 5.274) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[1]/opit_0/CLK (5.392, 5.888, 4.871, 5.256) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[2]/opit_0/CLK (5.410, 5.906, 4.889, 5.274) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[3]/opit_0/CLK (5.392, 5.888, 4.871, 5.256) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/CLK (5.403, 5.899, 4.883, 5.268) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[5]/opit_0/CLK (5.425, 5.921, 4.904, 5.289) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[6]/opit_0/CLK (5.398, 5.894, 4.877, 5.262) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[7]/opit_0/CLK (5.403, 5.899, 4.883, 5.268) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/CLK (5.403, 5.899, 4.883, 5.268) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[9]/opit_0/CLK (5.403, 5.899, 4.883, 5.268) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[9]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm_inv/CLKB (5.407, 5.903, 4.886, 5.271) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm_inv/CLKB (5.378, 5.873, 4.857, 5.241) u_clk50m_rst/rst/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) @@ -7869,40 +7970,37 @@ u_clk50m_rst/rst1/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_ddr_addr_ctr/clk_cnt[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + u_ddr_addr_ctr/clk_cnt[0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - u_ddr_addr_ctr/clk_cnt[2]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_ddr_addr_ctr/clk_cnt[2]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - u_ddr_addr_ctr/clk_cnt[4]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_ddr_addr_ctr/clk_cnt[4]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - u_ddr_addr_ctr/clk_cnt[6]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_ddr_addr_ctr/clk_cnt[6]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - u_ddr_addr_ctr/clk_cnt[8]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_ddr_addr_ctr/clk_cnt[8]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - u_ddr_addr_ctr/clk_cnt[10]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_ddr_addr_ctr/clk_cnt[10]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - u_ddr_addr_ctr/clk_cnt[12]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_ddr_addr_ctr/clk_cnt[12]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - u_ddr_addr_ctr/clk_cnt[14]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_ddr_addr_ctr/clk_cnt[14]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - u_ddr_addr_ctr/clk_cnt[16]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_ddr_addr_ctr/clk_cnt[16]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - u_ddr_addr_ctr/clk_cnt[18]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_ddr_addr_ctr/clk_cnt[18]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - u_ddr_addr_ctr/clk_cnt[20]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - - - u_ddr_addr_ctr/clk_cnt[21]/opit_0_AQ/CLK (5.378, 5.873, 4.857, 5.241) + u_ddr_addr_ctr/clk_cnt[19]/opit_0_AQ/CLK (5.499, 5.996, 4.972, 5.359) u_ddr_addr_ctr/u_rd0_addr_ctr/image_perimt/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) @@ -7980,7 +8078,7 @@ u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[6]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[7]/opit_0_AQ_perm/CLK (5.378, 5.873, 4.857, 5.241) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[7]/opit_0_AQ/CLK (5.378, 5.873, 4.857, 5.241) u_ddr_addr_ctr/u_rd0_addr_ctr/wr_image_cnt0[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) @@ -8028,7 +8126,7 @@ u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[3]/opit_0/CLK (5.421, 5.918, 4.901, 5.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) @@ -8061,7 +8159,7 @@ u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[3]/opit_0/CLK (5.421, 5.918, 4.901, 5.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) @@ -8232,10 +8330,10 @@ u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[3]/opit_0/CLK (5.421, 5.918, 4.901, 5.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[4]/opit_0/CLK (5.421, 5.918, 4.901, 5.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) @@ -8250,7 +8348,7 @@ u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[8]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[9]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[9]/opit_0/CLK (5.430, 5.927, 4.909, 5.295) u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[10]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) @@ -8334,7 +8432,7 @@ u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[3]/opit_0/CLK (5.407, 5.903, 4.886, 5.271) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) @@ -8373,22 +8471,22 @@ u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[23]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_ddr_addr_ctr/u_rd3_addr_ctr/rd_ddr_valid0/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_ddr_addr_ctr/u_rd3_addr_ctr/rd_ddr_valid0/opit_0/CLK (5.427, 5.923, 4.906, 5.291) - u_ddr_addr_ctr/u_rd3_addr_ctr/rd_ddr_valid1/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_ddr_addr_ctr/u_rd3_addr_ctr/rd_ddr_valid1/opit_0/CLK (5.416, 5.912, 4.895, 5.280) - u_ddr_addr_ctr/u_rd3_addr_ctr/rd_ddr_valid2/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_ddr_addr_ctr/u_rd3_addr_ctr/rd_ddr_valid2/opit_0/CLK (5.416, 5.912, 4.895, 5.280) - u_ddr_addr_ctr/u_rd3_addr_ctr/rd_ddr_valid3/opit_0/CLK (5.419, 5.915, 4.898, 5.284) + u_ddr_addr_ctr/u_rd3_addr_ctr/rd_ddr_valid3/opit_0/CLK (5.416, 5.912, 4.895, 5.280) - u_ddr_addr_ctr/u_rd3_addr_ctr/rd_ddr_valid4/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_ddr_addr_ctr/u_rd3_addr_ctr/rd_ddr_valid4/opit_0/CLK (5.427, 5.923, 4.906, 5.291) - u_ddr_addr_ctr/u_rd3_addr_ctr/rd_ddr_valid5/opit_0/CLK (5.419, 5.915, 4.898, 5.284) + u_ddr_addr_ctr/u_rd3_addr_ctr/rd_ddr_valid5/opit_0/CLK (5.416, 5.912, 4.895, 5.280) u_ddr_addr_ctr/u_rd3_addr_ctr/rd_image_cnt[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) @@ -8619,7 +8717,7 @@ u_ddr_addr_ctr/vs_15hz/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_ddr_addr_ctr/vs_30hz/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + u_ddr_addr_ctr/vs_30hz/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) u_ov5640/power_on_delay_inst/camera_pwnd_reg/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) @@ -8976,7 +9074,7 @@ u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[10]/opit_0_inv_AQ_perm/CLK (5.378, 5.873, 4.857, 5.241) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[10]/opit_0_inv_AQ/CLK (5.378, 5.873, 4.857, 5.241) u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) @@ -9081,601 +9179,601 @@ u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (5.378, 5.873, 4.857, 5.241) - u_rotate_image/addr_fifo_valid/opit_0_L5Q_perm/CLK (5.410, 5.906, 4.889, 5.274) + u_rotate_image/addr_fifo_valid/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/centerX[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/centerX[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/centerX[2]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/centerX[2]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/centerX[4]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/centerX[4]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/centerX[6]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/centerX[6]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/centerX[8]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/centerX[8]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/centerX[10]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/centerX[10]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/centerX[11]/opit_0_AQ/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/centerX[11]/opit_0_AQ/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/centerY[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/centerY[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/centerY[2]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/centerY[2]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/centerY[4]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/centerY[4]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/centerY[6]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/centerY[6]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/centerY[8]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/centerY[8]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/centerY[10]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/centerY[10]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/centerY[11]/opit_0_AQ/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/centerY[11]/opit_0_AQ/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/cnt_h[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/cnt_h[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/cnt_h[2]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/cnt_h[2]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/cnt_h[4]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/cnt_h[4]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/cnt_h[6]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/cnt_h[6]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/cnt_h[8]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/cnt_h[8]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/cnt_h[10]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/cnt_h[10]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/cnt_w[0]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/cnt_w[0]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/cnt_w[2]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/cnt_w[2]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/cnt_w[4]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/cnt_w[4]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/cnt_w[6]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/cnt_w[6]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/cnt_w[8]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/cnt_w[8]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/cnt_w[10]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/cnt_w[10]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/data_out2[0]/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/data_out2[0]/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/data_out2[1]/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/data_out2[1]/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/data_out2[2]/opit_0_inv/CLK (5.387, 5.882, 4.866, 5.250) + u_rotate_image/data_out2[2]/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/data_out2[3]/opit_0_inv/CLK (5.387, 5.882, 4.866, 5.250) + u_rotate_image/data_out2[3]/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/data_out2[4]/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/data_out2[4]/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/data_out2[5]/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/data_out2[5]/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/data_out2[6]/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/data_out2[6]/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/data_out2[7]/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/data_out2[7]/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/data_out2[8]/opit_0_inv/CLK (5.404, 5.901, 4.884, 5.269) + u_rotate_image/data_out2[8]/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/data_out2[9]/opit_0_inv/CLK (5.404, 5.901, 4.884, 5.269) + u_rotate_image/data_out2[9]/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/data_out2[10]/opit_0_inv/CLK (5.404, 5.901, 4.884, 5.269) + u_rotate_image/data_out2[10]/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/data_out2[11]/opit_0_inv/CLK (5.404, 5.901, 4.884, 5.269) + u_rotate_image/data_out2[11]/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/data_out2[12]/opit_0_inv/CLK (5.410, 5.906, 4.889, 5.274) + u_rotate_image/data_out2[12]/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/data_out2[13]/opit_0_inv/CLK (5.410, 5.906, 4.889, 5.274) + u_rotate_image/data_out2[13]/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/data_out2[14]/opit_0_inv/CLK (5.404, 5.901, 4.884, 5.269) + u_rotate_image/data_out2[14]/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/data_out2[15]/opit_0_inv/CLK (5.404, 5.901, 4.884, 5.269) + u_rotate_image/data_out2[15]/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/data_out_valid1/opit_0_L5Q_perm/CLK (5.410, 5.906, 4.889, 5.274) + u_rotate_image/data_out_valid1/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/data_out_valid2/opit_0_L5Q_perm/CLK (5.410, 5.906, 4.889, 5.274) + u_rotate_image/data_out_valid2/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/ddr_data_in0[0]/opit_0/CLK (5.427, 5.923, 4.906, 5.291) + u_rotate_image/ddr_data_in0[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/ddr_data_in0[1]/opit_0/CLK (5.427, 5.923, 4.906, 5.291) + u_rotate_image/ddr_data_in0[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/ddr_data_in0[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/ddr_data_in0[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/ddr_data_in0[3]/opit_0/CLK (5.421, 5.918, 4.901, 5.286) + u_rotate_image/ddr_data_in0[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/ddr_data_in0[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/ddr_data_in0[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/ddr_data_in0[5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/ddr_data_in0[5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/ddr_data_in0[6]/opit_0/CLK (5.436, 5.933, 4.915, 5.301) + u_rotate_image/ddr_data_in0[6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/ddr_data_in0[7]/opit_0/CLK (5.436, 5.933, 4.915, 5.301) + u_rotate_image/ddr_data_in0[7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/ddr_data_in0[8]/opit_0/CLK (5.436, 5.933, 4.915, 5.301) + u_rotate_image/ddr_data_in0[8]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/ddr_data_in0[9]/opit_0/CLK (5.421, 5.918, 4.901, 5.286) + u_rotate_image/ddr_data_in0[9]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/ddr_data_in0[10]/opit_0/CLK (5.421, 5.918, 4.901, 5.286) + u_rotate_image/ddr_data_in0[10]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/ddr_data_in0[11]/opit_0/CLK (5.427, 5.923, 4.906, 5.291) + u_rotate_image/ddr_data_in0[11]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/ddr_data_in0[12]/opit_0/CLK (5.427, 5.923, 4.906, 5.291) + u_rotate_image/ddr_data_in0[12]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/ddr_data_in0[13]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/ddr_data_in0[13]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/ddr_data_in0[14]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/ddr_data_in0[14]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/ddr_data_in0[15]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/ddr_data_in0[15]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/ddr_data_in_valid0/opit_0/CLK (5.421, 5.918, 4.901, 5.286) + u_rotate_image/ddr_data_in_valid0/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/fifo_data_valid/opit_0_L5Q_perm/CLK (5.410, 5.906, 4.889, 5.274) + u_rotate_image/fifo_data_valid/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_blank_valid/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_blank_valid/opit_0_L5Q_perm/CLK (5.403, 5.899, 4.883, 5.268) - u_rotate_image/image_h_add0[7]/opit_0_A2Q1/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_h_add0[7]/opit_0_A2Q1/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_h_add0[9]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_h_add0[9]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_h_add0[11]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_h_add0[11]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_h_add0[13]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_h_add0[13]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_h_add0[15]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_h_add0[15]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_h_add0[17]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_h_add0[17]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_h_add0[19]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_h_add0[19]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_h_add0[21]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_h_add0[21]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_h_add0[23]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_h_add0[23]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_h_add0[25]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_h_add0[25]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_h_add1[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_h_add1[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_h_add1[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_h_add1[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_h_add1[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_h_add1[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_h_add1[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_h_add1[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_h_add1[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_h_add1[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_h_add1[5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_h_add1[5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_h_add1[6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_h_add1[6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_h_add1[7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_h_add1[7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_h_add1[8]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_h_add1[8]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_h_add1[9]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_h_add1[9]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_h_add1[10]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_h_add1[10]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_h_add2[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_h_add2[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_h_add2[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_h_add2[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_h_add2[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_h_add2[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_h_add2[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_h_add2[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_h_add2[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_h_add2[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_h_add2[5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_h_add2[5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_h_add2[6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_h_add2[6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_h_add2[7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_h_add2[7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_h_add2[8]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_h_add2[8]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_h_add2[9]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_h_add2[9]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_h_add2[10]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_h_add2[10]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_h_add_addr[7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_h_add_addr[7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_h_add_addr[8]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_h_add_addr[8]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_h_add_addr[9]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_h_add_addr[9]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_h_add_addr[10]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_h_add_addr[10]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_h_add_addr[11]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_h_add_addr[11]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_h_add_addr[12]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_h_add_addr[12]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_h_add_addr[13]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_h_add_addr[13]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_h_add_addr[14]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_h_add_addr[14]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_h_add_addr[15]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_h_add_addr[15]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_h_add_addr[16]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_h_add_addr[16]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_h_add_addr[17]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_h_add_addr[17]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_h_add_addr[18]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_h_add_addr[18]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_h_blank_valid/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_h_blank_valid/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_add0[7]/opit_0_A2Q1/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_add0[7]/opit_0_A2Q1/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_add0[9]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_add0[9]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_add0[11]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_add0[11]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_add0[13]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_add0[13]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_add0[15]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_add0[15]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_add0[17]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_add0[17]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_add0[19]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_add0[19]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_add0[21]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_add0[21]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_add0[23]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_add0[23]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_add0[25]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_add0[25]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_add1[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_add1[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_add1[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_add1[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_add1[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_add1[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_add1[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_add1[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_add1[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_add1[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_add1[5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_add1[5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_add1[6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_add1[6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_add1[7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_add1[7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_add1[8]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_add1[8]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_add1[9]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_add1[9]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_add1[10]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_add1[10]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_add2[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_add2[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_add2[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_add2[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_add2[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_add2[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_add2[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_add2[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_add2[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_add2[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_add2[5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_add2[5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_add2[6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_add2[6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_add2[7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_add2[7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_add2[8]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_add2[8]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_add2[9]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_add2[9]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_add2[10]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_add2[10]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_add_addr[7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_add_addr[7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_add_addr[8]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_add_addr[8]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_add_addr[9]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_add_addr[9]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_add_addr[10]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_add_addr[10]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_add_addr[11]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_add_addr[11]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_add_addr[12]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_add_addr[12]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_add_addr[13]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_add_addr[13]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_add_addr[14]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_add_addr[14]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_add_addr[15]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_add_addr[15]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_add_addr[16]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_add_addr[16]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_add_addr[17]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_add_addr[17]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_add_addr[18]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_add_addr[18]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_blank_valid/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_blank_valid/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_valid0[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_valid0[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/image_w_valid0[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_valid0[1]/opit_0/CLK (5.416, 5.912, 4.895, 5.280) - u_rotate_image/image_w_valid0[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_valid0[2]/opit_0/CLK (5.416, 5.912, 4.895, 5.280) - u_rotate_image/image_w_valid0[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_valid0[3]/opit_0/CLK (5.416, 5.912, 4.895, 5.280) - u_rotate_image/image_w_valid0[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/image_w_valid0[4]/opit_0/CLK (5.403, 5.899, 4.883, 5.268) - u_rotate_image/offsetX_ff[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/offsetX_ff[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/offsetX_ff[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/offsetX_ff[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/offsetX_ff[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/offsetX_ff[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/offsetX_ff[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/offsetX_ff[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/offsetX_ff[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/offsetX_ff[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/offsetX_ff[5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/offsetX_ff[5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/offsetX_ff[6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/offsetX_ff[6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/offsetX_ff[7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/offsetX_ff[7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/offsetX_ff[8]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/offsetX_ff[8]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/offsetX_ff[9]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/offsetX_ff[9]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/offsetX_ff[10]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/offsetX_ff[10]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/offsetX_ff[11]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/offsetX_ff[11]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/offsetY_ff[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/offsetY_ff[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/offsetY_ff[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/offsetY_ff[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/offsetY_ff[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/offsetY_ff[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/offsetY_ff[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/offsetY_ff[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/offsetY_ff[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/offsetY_ff[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/offsetY_ff[5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/offsetY_ff[5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/offsetY_ff[6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/offsetY_ff[6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/offsetY_ff[7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/offsetY_ff[7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/offsetY_ff[8]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/offsetY_ff[8]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/offsetY_ff[9]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/offsetY_ff[9]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/offsetY_ff[10]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/offsetY_ff[10]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/offsetY_ff[11]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/offsetY_ff[11]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/rd_addr[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/rd_addr[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/rd_addr[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/rd_addr[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/rd_addr[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/rd_addr[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/rd_addr[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/rd_addr[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/rd_addr[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/rd_addr[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/rd_addr[5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/rd_addr[5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/rd_addr[6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/rd_addr[6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/rd_addr[7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/rd_addr[7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/rd_ddr_addr_valid1/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/rd_ddr_addr_valid1/opit_0_L5Q_perm/CLK (5.416, 5.912, 4.895, 5.280) - u_rotate_image/rd_sta_reg[0]/opit_0_MUX4TO1Q/CLK (5.419, 5.915, 4.898, 5.284) + u_rotate_image/rd_sta_reg[0]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/rd_sta_reg[1]/opit_0_MUX4TO1Q/CLK (5.419, 5.915, 4.898, 5.284) + u_rotate_image/rd_sta_reg[1]/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/rd_sta_reg[2]/opit_0_L5Q_perm/CLK (5.419, 5.915, 4.898, 5.284) + u_rotate_image/rd_sta_reg[2]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/rd_sta_s2/opit_0_L5Q_perm/CLK (5.404, 5.901, 4.884, 5.269) + u_rotate_image/rd_sta_s2/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/rotate_sta_reg[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/rotate_sta_reg[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/rotate_sta_reg[1]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/rotate_sta_reg[1]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/rotate_sta_reg[2]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/rotate_sta_reg[2]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) u_rotate_image/u_rotate_mult0/N2/gopapm/CLK (5.378, 5.873, 4.857, 5.241) @@ -9690,88 +9788,88 @@ u_rotate_image/u_rotate_mult3/N2/gopapm/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/u_rotate_mult_zoom0/N2/gopapm/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/u_rotate_mult_zoom0/N2/gopapm/CLK (5.499, 5.996, 4.972, 5.359) u_rotate_image/u_rotate_mult_zoom1/N2/gopapm/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/u_rotate_rom/U_ipml_rom_rotate_rom/U_ipml_spram_rotate_rom/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKA (5.378, 5.873, 4.857, 5.241) + u_rotate_image/u_rotate_rom/U_ipml_rom_rotate_rom/U_ipml_spram_rotate_rom/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKA (5.499, 5.996, 4.972, 5.359) - u_rotate_image/u_rotate_rom/U_ipml_rom_rotate_rom/U_ipml_spram_rotate_rom/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB (5.378, 5.873, 4.857, 5.241) + u_rotate_image/u_rotate_rom/U_ipml_rom_rotate_rom/U_ipml_spram_rotate_rom/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB (5.499, 5.996, 4.972, 5.359) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (5.419, 5.915, 4.898, 5.284) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (5.421, 5.918, 4.901, 5.286) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (5.419, 5.915, 4.898, 5.284) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (5.421, 5.918, 4.901, 5.286) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (5.413, 5.910, 4.893, 5.278) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (5.416, 5.912, 4.895, 5.280) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (5.413, 5.910, 4.893, 5.278) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (5.416, 5.912, 4.895, 5.280) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (5.419, 5.915, 4.898, 5.284) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (5.410, 5.906, 4.889, 5.274) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[11]/opit_0_inv_A2Q21/CLK (5.419, 5.915, 4.898, 5.284) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[11]/opit_0_inv_A2Q21/CLK (5.410, 5.906, 4.889, 5.274) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/CLK (5.389, 5.885, 4.868, 5.253) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK (5.392, 5.888, 4.871, 5.256) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (5.421, 5.918, 4.901, 5.286) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (5.421, 5.918, 4.901, 5.286) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (5.416, 5.912, 4.895, 5.280) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (5.416, 5.912, 4.895, 5.280) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (5.410, 5.906, 4.889, 5.274) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[11]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[11]/opit_0_inv_A2Q21/CLK (5.410, 5.906, 4.889, 5.274) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[1]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[1]/opit_0_A2Q21/CLK (5.403, 5.899, 4.883, 5.268) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[3]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[3]/opit_0_A2Q21/CLK (5.403, 5.899, 4.883, 5.268) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[5]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[5]/opit_0_A2Q21/CLK (5.398, 5.894, 4.877, 5.262) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[7]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[7]/opit_0_A2Q21/CLK (5.398, 5.894, 4.877, 5.262) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[9]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[9]/opit_0_A2Q21/CLK (5.392, 5.888, 4.871, 5.256) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[11]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[11]/opit_0_A2Q21/CLK (5.392, 5.888, 4.871, 5.256) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKA (5.428, 5.925, 4.907, 5.293) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKA (5.407, 5.903, 4.886, 5.271) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB (5.434, 5.930, 4.913, 5.298) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB (5.412, 5.909, 4.892, 5.277) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (5.409, 5.905, 4.888, 5.273) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (5.409, 5.905, 4.888, 5.273) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) @@ -9792,10 +9890,10 @@ u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (5.427, 5.923, 4.906, 5.291) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (5.427, 5.923, 4.906, 5.291) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) @@ -9813,7 +9911,7 @@ u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.378, 5.873, 4.857, 5.241) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (5.412, 5.909, 4.892, 5.277) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (5.378, 5.873, 4.857, 5.241) vs_down_delay_cnt[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) @@ -9897,137 +9995,17 @@ - clk_200m (200.00MHZ) (drive 825 loads) + clk_200m (200.00MHZ) (drive 75 loads) u_sys_pll/u_pll_e3/goppll/CLKOUT1 (2.784, 3.204, 2.241, 2.549) - zoom_clk (net) + ddr_clk (net) USCMROUTE_2/CLK (3.843, 4.282, 3.300, 3.627) USCMROUTE_2/CLKOUT (3.843, 4.282, 3.300, 3.627) - ntR3909 (net) - - u_axi_ddr_top/u_axi_rd_connect/rd1_data_valid0/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0_A2Q1/CLK (5.495, 5.990, 4.967, 5.355) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (5.495, 5.990, 4.967, 5.355) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (5.495, 5.990, 4.967, 5.355) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (5.495, 5.990, 4.967, 5.355) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[11]/opit_0_inv_A2Q21/CLK (5.495, 5.990, 4.967, 5.355) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm/CLK (5.495, 5.990, 4.967, 5.355) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/CLK (5.495, 5.990, 4.967, 5.355) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/CLK (5.495, 5.990, 4.967, 5.355) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm/CLK (5.495, 5.990, 4.967, 5.355) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[11]/opit_0_L5Q_perm/CLK (5.495, 5.990, 4.967, 5.355) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/opit_0/CLK (5.495, 5.990, 4.967, 5.355) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/opit_0/CLK (5.495, 5.990, 4.967, 5.355) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/opit_0/CLK (5.495, 5.990, 4.967, 5.355) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/opit_0/CLK (5.495, 5.990, 4.967, 5.355) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/opit_0/CLK (5.495, 5.990, 4.967, 5.355) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK (5.495, 5.990, 4.967, 5.355) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/CLK (5.495, 5.990, 4.967, 5.355) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[1]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[2]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[3]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/CLK (5.495, 5.990, 4.967, 5.355) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[5]/opit_0/CLK (5.495, 5.990, 4.967, 5.355) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[6]/opit_0/CLK (5.495, 5.990, 4.967, 5.355) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[7]/opit_0/CLK (5.495, 5.990, 4.967, 5.355) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/CLK (5.495, 5.990, 4.967, 5.355) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[9]/opit_0/CLK (5.495, 5.990, 4.967, 5.355) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm_inv/CLKB[0] (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm_inv/CLKB[0] (5.495, 5.990, 4.967, 5.355) - + ntR3952 (net) u_axi_rst/rst/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) @@ -10038,74479 +10016,74244 @@ u_axi_rst/rst1/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - u_ddr_addr_ctr/rd1_vs0/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/delay_cnt[0]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/delay_cnt[1]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/delay_cnt[2]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/gen_start_addr3[19]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/gen_start_addr3[20]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/gen_start_addr3[21]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_addr[7]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_addr[8]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_addr[10]/opit_0_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_addr[12]/opit_0_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_addr[14]/opit_0_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_addr[16]/opit_0_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_addr[18]/opit_0_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_addr[19]/opit_0_AQ/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_h[1]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_h[2]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_h[3]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_h[4]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_h[5]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_h[6]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_h[7]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_h[8]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_h[9]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_h[10]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/rd1_sta_reg[0]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/rd1_sta_reg[1]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/rd1_sta_reg[2]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/rd3_image_cnt[0]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/rd3_image_cnt[1]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/rd3_image_cnt[2]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[7]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[8]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[9]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[10]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[11]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[12]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[13]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[14]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[15]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[16]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[17]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[18]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[19]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[20]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[21]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[22]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_done0/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_done1/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_done2/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_valid0/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_valid1/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_vs0/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_vs1/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_vs_rise0/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.rbin[8]/opit_0_inv_AQ/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_AQ_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.wbin[8]/opit_0_inv_AQ/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKA (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/data_in0[0]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/data_in0[1]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/data_in0[2]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/data_in1[0]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/data_in1[1]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/data_in1[2]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/data_in2[0]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/data_in2[1]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/data_in2[2]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/data_in3[0]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/data_in3[1]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/data_in3[2]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/data_vary0/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_image_fram_cnt1[0]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_image_fram_cnt1[1]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_image_fram_cnt1[2]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) + u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK (5.495, 5.990, 4.967, 5.355) - u_ddr_rst/rst0/opit_0_inv/CLK (5.374, 5.867, 4.852, 5.237) + u_ddr_rst/rst0/opit_0_inv/CLK (5.495, 5.990, 4.967, 5.355) - u_ddr_rst/rst1/opit_0_inv/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[13]/opit_0_inv_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[15]/opit_0_inv_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[12]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[13]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[14]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[15]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[10]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[11]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[12]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[13]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[14]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[15]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[5]/opit_0_L6Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[6]/opit_0_L6Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[7]/opit_0_L6Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[8]/opit_0_L6Q/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[9]/opit_0_L6Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[10]/opit_0_L6Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[11]/opit_0_L6Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[12]/opit_0_L6Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[0]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[5]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[6]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[8]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[11]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[12]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[13]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[14]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[15]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.495, 5.990, 4.967, 5.355) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[3].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[4].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.495, 5.990, 4.967, 5.355) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[6].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.495, 5.990, 4.967, 5.355) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[7].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[8].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.495, 5.990, 4.967, 5.355) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[9].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[10].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.495, 5.990, 4.967, 5.355) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[11].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[12].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[13].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[14].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.495, 5.990, 4.967, 5.355) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[15].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[2].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.495, 5.990, 4.967, 5.355) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[3].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[4].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[6].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.495, 5.990, 4.967, 5.355) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[7].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[8].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.495, 5.990, 4.967, 5.355) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[9].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.495, 5.990, 4.967, 5.355) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[10].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.495, 5.990, 4.967, 5.355) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[11].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[12].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.374, 5.867, 4.852, 5.237) - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[13].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.495, 5.990, 4.967, 5.355) + u_ddr_rst/rst1/opit_0_inv/CLK (5.495, 5.990, 4.967, 5.355) + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLK (3.843, 4.282, 3.300, 3.627) + + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT (3.843, 4.282, 3.300, 3.627) + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin (net) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[14].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.495, 5.990, 4.967, 5.355) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/opit_0/CLK (5.495, 5.990, 4.967, 5.355) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[15].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK (5.495, 5.990, 4.967, 5.355) - u_zoom_image/addr_sta_reg[0]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[0]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/addr_sta_reg[1]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[1]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/addr_sta_reg[2]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[2]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/addr_sta_reg[3]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[3]/opit_0_inv_MUX4TO1Q/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/addr_sta_reg[4]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_ack_rst_ctrl/opit_0_inv/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/cnt_h[0]/opit_0_L5Q/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_n/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/cnt_h[1]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[0]/opit_0_inv/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/cnt_h[2]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[1]/opit_0_inv/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/cnt_h[3]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[0]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/cnt_h[4]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[1]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/cnt_h[5]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[2]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/cnt_h[6]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[3]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/cnt_h[7]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[0]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/cnt_h[8]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[1]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/cnt_h[9]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[2]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/cnt_h[10]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[3]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/cnt_record_ram[0]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[4]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/cnt_record_ram[1]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[5]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/cnt_record_ram[2]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[6]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/cnt_w[0]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[7]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/cnt_w[1]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_dll_rst_rg/opit_0_inv_L5Q/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/cnt_w[2]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_dqs_rst/opit_0_inv/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/cnt_w[4]/opit_0_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[0]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/cnt_w[6]/opit_0_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[1]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/cnt_w[8]/opit_0_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[2]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/cnt_w[10]/opit_0_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[3]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/coe_valid[0]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[4]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/coe_valid[1]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[5]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/coe_valid[2]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[6]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/coe_valid[3]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[7]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/data_in0[0]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[8]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/data_in0[1]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[9]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/data_in0[2]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[10]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/data_in0[3]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[11]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/data_in0[4]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[12]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/data_in0[5]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[13]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/data_in0[6]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[14]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/data_in0[7]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/data_in0[8]/opit_0/CLK (5.495, 5.990, 4.967, 5.355) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[16]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/data_in0[9]/opit_0/CLK (5.495, 5.990, 4.967, 5.355) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[17]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/data_in0[10]/opit_0/CLK (5.495, 5.990, 4.967, 5.355) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[18]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/data_in0[11]/opit_0/CLK (5.495, 5.990, 4.967, 5.355) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_b_ff/opit_0_inv/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/data_in0[12]/opit_0/CLK (5.495, 5.990, 4.967, 5.355) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_b_neg/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/data_in0[13]/opit_0/CLK (5.495, 5.990, 4.967, 5.355) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_deb_pre/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/data_in0[14]/opit_0/CLK (5.495, 5.990, 4.967, 5.355) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_rst/opit_0_inv/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/data_in0[15]/opit_0/CLK (5.495, 5.990, 4.967, 5.355) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_rst_n_rg/opit_0_inv/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/data_in_valid0/opit_0/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/dll_lock_d[0]/opit_0_inv/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/data_out1[0]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/dll_lock_d[1]/opit_0_inv/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/data_out1[1]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/dll_update_ack_rst_ctrl_d[0]/opit_0_inv/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/data_out1[2]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/dll_update_ack_rst_ctrl_d[1]/opit_0_inv/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/data_out1[3]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/dll_update_req_rst_ctrl/opit_0_inv/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/data_out1[4]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/data_out1[5]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/pll_lock_d[0]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/data_out1[6]/opit_0/CLK (5.495, 5.990, 4.967, 5.355) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/pll_lock_d[1]/opit_0_inv/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/data_out1[7]/opit_0/CLK (5.495, 5.990, 4.967, 5.355) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[0]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/data_out1[8]/opit_0/CLK (5.495, 5.990, 4.967, 5.355) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[1]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/data_out1[9]/opit_0/CLK (5.495, 5.990, 4.967, 5.355) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[2]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/data_out1[10]/opit_0/CLK (5.495, 5.990, 4.967, 5.355) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[3]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/data_out1[11]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/data_out1[12]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[5]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/data_out1[13]/opit_0/CLK (5.495, 5.990, 4.967, 5.355) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[6]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/data_out1[14]/opit_0/CLK (5.495, 5.990, 4.967, 5.355) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[7]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/data_out1[15]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[8]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/data_out2[0]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/training_error_d[0]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/data_out2[1]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/training_error_d[1]/opit_0_inv/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/data_out2[2]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d1/opit_0_inv/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/data_out2[3]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d2/opit_0_inv/CLK (5.374, 5.867, 4.852, 5.237) - u_zoom_image/data_out2[4]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/data_out2[5]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/data_out2[6]/opit_0/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/data_out2[7]/opit_0/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/data_out2[8]/opit_0/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/data_out2[9]/opit_0/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/data_out2[10]/opit_0/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/data_out2[11]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/data_out2[12]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/data_out2[13]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/data_out2[14]/opit_0/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/data_out2[15]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/data_out_valid1/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/data_out_valid2/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/delay_cnt[0]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/delay_cnt[1]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/delay_cnt[2]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/fifo_full0/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/imag_addr0[0]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/imag_addr0[1]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/imag_addr0[2]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/imag_addr0[3]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/imag_addr0[4]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/imag_addr0[5]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/imag_addr0[6]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/imag_addr0[7]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/imag_addr0[8]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/imag_addr0[9]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/imag_addr1[0]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/imag_addr1[1]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/imag_addr1[2]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/imag_addr1[3]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/imag_addr1[5]/opit_0_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/imag_addr1[7]/opit_0_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/imag_addr1[9]/opit_0_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/imag_addr_valid0/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/imag_addr_valid1/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h0[0]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h0[1]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h0[2]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h0[3]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h0[4]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h0[5]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h0[6]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h0[8]/opit_0_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h0[10]/opit_0_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h0[12]/opit_0_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h0[14]/opit_0_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h0[16]/opit_0_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h0[18]/opit_0_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h0[20]/opit_0_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h1[1]/opit_0_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h1[3]/opit_0_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h1[5]/opit_0_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h1[7]/opit_0_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h1[9]/opit_0_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h1[11]/opit_0_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h1[13]/opit_0_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h1[15]/opit_0_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h1[17]/opit_0_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h1[19]/opit_0_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h1[20]/opit_0_AQ/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h2[0]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h2[1]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h2[2]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h2[3]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h2[4]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h2[5]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h2[6]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h2[7]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h2[8]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h2[9]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h2[10]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h2[11]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h2[12]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h2[13]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h2[14]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h2[15]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h2[16]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h2[17]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h2[18]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h2[19]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h2[20]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h2_coe0[0]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h2_coe0[1]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h2_coe0[2]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h2_coe0[3]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h2_coe0[4]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h2_coe0[5]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h2_coe0[6]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h2_coe1[0]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h2_coe1[1]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h2_coe1[2]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h2_coe1[3]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h2_coe1[4]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h2_coe1[5]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h2_coe1[6]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h2_coe[0]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h2_coe[1]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h2_coe[2]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h2_coe[3]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h2_coe[4]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h2_coe[5]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h2_coe[6]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h_valid[0]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_h_valid[1]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_valid[0][0]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_valid[0][1]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_valid[1][0]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_valid[1][1]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_valid[2][0]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_valid[2][1]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_valid[3][0]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_valid[3][1]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_valid[4][0]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_valid[4][1]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_valid[5][0]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_valid[5][1]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_valid[6][0]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_valid[6][1]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w1[1]/opit_0_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w1[3]/opit_0_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w1[5]/opit_0_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w1[7]/opit_0_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w1[9]/opit_0_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w1[11]/opit_0_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w1[13]/opit_0_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w1[15]/opit_0_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w1[17]/opit_0_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w1[19]/opit_0_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w1[20]/opit_0_AQ/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w2[0]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w2[1]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w2[2]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w2[3]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w2[4]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w2[5]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w2[6]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w2[15]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w2[16]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w2[17]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w2[18]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w2[19]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w2[20]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w2_coe0[0]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w2_coe0[1]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w2_coe0[2]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w2_coe0[3]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w2_coe0[4]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w2_coe0[5]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w2_coe0[6]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w2_coe1[0]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w2_coe1[1]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w2_coe1[2]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w2_coe1[3]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w2_coe1[4]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w2_coe1[5]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w2_coe1[6]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w2_coe[0]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w2_coe[1]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w2_coe[2]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w2_coe[3]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w2_coe[4]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w2_coe[5]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w2_coe[6]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w_valid[0]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/image_w_valid[1]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/judge_cnt_h[0]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/judge_cnt_h[1]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/judge_cnt_h[2]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/judge_cnt_h[3]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/judge_cnt_h[4]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/judge_cnt_h[5]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/judge_cnt_h[6]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/judge_cnt_h[7]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/judge_cnt_h[8]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/judge_cnt_h[9]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/judge_cnt_h[10]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/judge_cnt_h[11]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/judge_cnt_h[12]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/judge_cnt_h[13]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/judge_cnt_h_valid/opit_0_MUX4TO1Q/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/mult_fra0/N2/gopapm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/mult_fra0_0/N2/gopapm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/mult_fra1/N2/gopapm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/mult_fra1_0/N2/gopapm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/mult_h0[0]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/mult_h0[1]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/mult_h0[2]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/mult_h0[3]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/mult_h0[4]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/mult_h0[5]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/mult_h0[6]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/mult_h0[7]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/mult_h0[8]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/mult_h0[9]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/mult_h0[10]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/mult_h0[11]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/mult_h0[12]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/mult_h0[13]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/mult_image2[0][7]/opit_0_A2Q1/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/mult_image2[0][9]/opit_0_A2Q21/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/mult_image2[0][11]/opit_0_A2Q21/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/mult_image2[1][7]/opit_0_A2Q1/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/mult_image2[1][9]/opit_0_A2Q21/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/mult_image2[1][11]/opit_0_A2Q21/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/mult_image2[1][12]/opit_0_AQ_perm/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/mult_image2[2][7]/opit_0_A2Q1/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/mult_image2[2][9]/opit_0_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/mult_image2[2][11]/opit_0_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/mult_image_b0/N2/gopapm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/mult_image_b0_0/N2/gopapm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/mult_image_b1/N2/gopapm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/mult_image_b1_0/N2/gopapm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/mult_image_g0/N2/gopapm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/mult_image_g0_0/N2/gopapm/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/mult_image_g1/N2/gopapm/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/mult_image_g1_0/N2/gopapm/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/mult_image_r0/N2/gopapm/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/mult_image_r0_0/N2/gopapm/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/mult_image_r1/N2/gopapm/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/mult_image_r1_0/N2/gopapm/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/no_need_rd_ddr/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/no_one_need_rd_ddr/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/ram_ch0[0]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/ram_ch0[1]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/ram_ch1[0]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/ram_ch1[1]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/ram_ch2[0]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/ram_ch2[1]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/ram_ch[0]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/ram_ch[1]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/ram_idle/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/ram_idle0/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/ram_idle1/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/ram_sta_reg[0]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/ram_sta_reg[1]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/ram_sta_reg[2]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/ram_sta_reg[3]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/rd_addr0[0]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/rd_addr0[1]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/rd_addr0[2]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/rd_addr0[3]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/rd_addr0[4]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/rd_addr0[5]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/rd_addr0[6]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/rd_addr0[7]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/rd_addr0[8]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/rd_addr0[9]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/rd_addr0[10]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/rd_addr[0]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/rd_addr[1]/opit_0_A2Q1/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/rd_addr[3]/opit_0_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/rd_addr[5]/opit_0_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/rd_addr[7]/opit_0_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/rd_addr[9]/opit_0_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/rd_addr[10]/opit_0_AQ_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/rd_data_0[0]/opit_0_MUX4TO1Q/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/rd_data_0[1]/opit_0_MUX4TO1Q/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/rd_data_0[2]/opit_0_MUX4TO1Q/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/rd_data_0[3]/opit_0_MUX4TO1Q/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/rd_data_0[4]/opit_0_MUX4TO1Q/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/rd_data_0[5]/opit_0_MUX4TO1Q/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/rd_data_0[6]/opit_0_MUX4TO1Q/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/rd_data_0[7]/opit_0_MUX4TO1Q/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/rd_data_0[8]/opit_0_MUX4TO1Q/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/rd_data_0[9]/opit_0_MUX4TO1Q/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/rd_data_0[10]/opit_0_MUX4TO1Q/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/rd_data_0[11]/opit_0_MUX4TO1Q/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/rd_data_0[12]/opit_0_MUX4TO1Q/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/rd_data_0[13]/opit_0_MUX4TO1Q/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/rd_data_0[14]/opit_0_MUX4TO1Q/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/rd_data_0[15]/opit_0_MUX4TO1Q/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/rd_data_0[16]/opit_0_MUX4TO1Q/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/rd_data_0[17]/opit_0_MUX4TO1Q/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/rd_data_0[18]/opit_0_MUX4TO1Q/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/rd_data_0[19]/opit_0_MUX4TO1Q/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/rd_data_0[20]/opit_0_MUX4TO1Q/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/rd_data_0[21]/opit_0_MUX4TO1Q/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/rd_data_0[22]/opit_0_MUX4TO1Q/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/rd_data_0[23]/opit_0_MUX4TO1Q/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/rd_data_0[24]/opit_0_MUX4TO1Q/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/rd_data_0[25]/opit_0_MUX4TO1Q/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/rd_data_0[26]/opit_0_MUX4TO1Q/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/rd_data_0[27]/opit_0_MUX4TO1Q/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/rd_data_0[28]/opit_0_MUX4TO1Q/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/rd_data_0[29]/opit_0_MUX4TO1Q/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/rd_data_0[30]/opit_0_MUX4TO1Q/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/rd_data_0[31]/opit_0_MUX4TO1Q/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/rd_data[0]/opit_0_MUX4TO1Q/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/rd_data[1]/opit_0_MUX4TO1Q/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/rd_data[2]/opit_0_MUX4TO1Q/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/rd_data[3]/opit_0_MUX4TO1Q/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/rd_data[4]/opit_0_MUX4TO1Q/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/rd_data[5]/opit_0_MUX4TO1Q/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/rd_data[6]/opit_0_MUX4TO1Q/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/rd_data[7]/opit_0_MUX4TO1Q/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/rd_data[8]/opit_0_MUX4TO1Q/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/rd_data[9]/opit_0_MUX4TO1Q/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/rd_data[10]/opit_0_MUX4TO1Q/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/rd_data[11]/opit_0_MUX4TO1Q/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/rd_data[12]/opit_0_MUX4TO1Q/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/rd_data[13]/opit_0_MUX4TO1Q/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/rd_data[14]/opit_0_MUX4TO1Q/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/rd_data[15]/opit_0_MUX4TO1Q/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/rd_data[16]/opit_0_MUX4TO1Q/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/rd_data[17]/opit_0_MUX4TO1Q/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/rd_data[18]/opit_0_MUX4TO1Q/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/rd_data[19]/opit_0_MUX4TO1Q/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/rd_data[20]/opit_0_MUX4TO1Q/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/rd_data[21]/opit_0_MUX4TO1Q/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/rd_data[22]/opit_0_MUX4TO1Q/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/rd_data[23]/opit_0_MUX4TO1Q/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/rd_data[24]/opit_0_MUX4TO1Q/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/rd_data[25]/opit_0_MUX4TO1Q/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/rd_data[26]/opit_0_MUX4TO1Q/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/rd_data[27]/opit_0_MUX4TO1Q/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/rd_data[28]/opit_0_MUX4TO1Q/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/rd_data[29]/opit_0_MUX4TO1Q/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/rd_data[30]/opit_0_MUX4TO1Q/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/rd_data[31]/opit_0_MUX4TO1Q/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/rd_one_ram/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/record_ram_valid/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/store_addr[0]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/store_addr[1]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/store_addr[2]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/store_addr[3]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/store_addr[4]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/store_addr[5]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/store_addr[6]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/store_addr[7]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/store_addr[8]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/store_addr[9]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/store_addr[10]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/store_addr[11]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/store_addr[12]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/store_addr[13]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/store_mult_h0[0]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/store_mult_h0[1]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/store_mult_h[0]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/store_mult_h[1]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/u_image_h_mult/N3/gopapm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/u_image_w_mult/N3/gopapm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/wr_addr0[0]/opit_0_L5Q_perm/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/wr_addr0[2]/opit_0_A2Q21/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/wr_addr0[4]/opit_0_A2Q21/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/wr_addr0[6]/opit_0_A2Q21/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/wr_addr0[8]/opit_0_A2Q21/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/wr_addr0[10]/opit_0_A2Q21/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/wr_addr1[0]/opit_0_inv_L5Q_perm/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/wr_addr1[2]/opit_0_inv_A2Q21/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/wr_addr1[4]/opit_0_inv_A2Q21/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/wr_addr1[6]/opit_0_inv_A2Q21/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/wr_addr1[8]/opit_0_inv_A2Q21/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/wr_addr1[10]/opit_0_inv_A2Q21/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/wr_addr2[0]/opit_0_inv_L5Q_perm/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/wr_addr2[2]/opit_0_inv_A2Q21/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/wr_addr2[4]/opit_0_inv_A2Q21/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/wr_addr2[6]/opit_0_inv_A2Q21/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/wr_addr2[8]/opit_0_inv_A2Q21/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/wr_addr2[10]/opit_0_inv_A2Q21/CLK (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/wr_addr3[0]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/wr_addr3[2]/opit_0_inv_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/wr_addr3[4]/opit_0_inv_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/wr_addr3[6]/opit_0_inv_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/wr_addr3[8]/opit_0_inv_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/wr_addr3[10]/opit_0_inv_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/wr_ram_done/opit_0_L6Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/zoom_num0[1]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/zoom_num0[2]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/zoom_num0[3]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/zoom_num0[4]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/zoom_num0[5]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/zoom_num0[6]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/zoom_num0[7]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/zoom_num0[8]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/zoom_num0[9]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/zoom_num1[0]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/zoom_num1[1]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/zoom_num1[2]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/zoom_num1[3]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/zoom_num1[4]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/zoom_num1[5]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/zoom_num1[6]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/zoom_num1[7]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/zoom_num1[8]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/zoom_ram0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/zoom_ram0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/zoom_ram0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/zoom_ram0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/zoom_ram0_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/zoom_ram0_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/zoom_ram0_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/zoom_ram0_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/zoom_ram1/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/zoom_ram1/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/zoom_ram1/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/zoom_ram1/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/zoom_ram1_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/zoom_ram1_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/zoom_ram1_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/zoom_ram1_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/zoom_ram2/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/zoom_ram2/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/zoom_ram2/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/zoom_ram2/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/zoom_ram2_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/zoom_ram2_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/zoom_ram2_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/zoom_ram2_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/zoom_ram3/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/zoom_ram3/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/zoom_ram3/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/zoom_ram3/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/zoom_ram3_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/zoom_ram3_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/zoom_ram3_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/zoom_ram3_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (5.495, 5.990, 4.967, 5.355) - - - u_zoom_image/zoom_sta_param/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/zoom_sta_param0/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/zoom_sta_param1/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/zoom_sta_reg[0]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/zoom_sta_reg[1]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/zoom_sta_reg[2]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/zoom_sta_reg[3]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/zoom_sta_reg[4]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/zoom_sta_reg[5]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_image/zoom_sta_reg[6]/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_rst/rst/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_rst/rst0/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_zoom_rst/rst1/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - zoom_ff0[0]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - zoom_ff0[1]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - zoom_ff0[2]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - zoom_ff0[3]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - zoom_ff0[4]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - zoom_ff0[5]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - zoom_ff0[6]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - zoom_ff0[7]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - zoom_ff0[8]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - zoom_ff0[9]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - zoom_ff1[0]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - zoom_ff1[1]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - zoom_ff1[2]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - zoom_ff1[3]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - zoom_ff1[4]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - zoom_ff1[5]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - zoom_ff1[6]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - zoom_ff1[7]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - zoom_ff1[8]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - zoom_ff1[9]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - zoom_ff2[0]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - zoom_ff2[1]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - zoom_ff2[2]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - zoom_ff2[3]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - zoom_ff2[4]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - zoom_ff2[5]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - zoom_ff2[6]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - zoom_ff2[7]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - zoom_ff2[8]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - zoom_ff2[9]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - zoom_fifo_full/opit_0_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - zoom_vs_out0/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - zoom_vs_out1/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLK (3.843, 4.282, 3.300, 3.627) - - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT (3.843, 4.282, 3.300, 3.627) - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin (net) - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[0]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[1]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[2]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[3]/opit_0_inv_MUX4TO1Q/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_ack_rst_ctrl/opit_0_inv/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_n/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[0]/opit_0_inv/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[1]/opit_0_inv/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[0]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[1]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[2]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[3]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[0]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[2]/opit_0_inv_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[4]/opit_0_inv_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[6]/opit_0_inv_A2Q21/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[7]/opit_0_inv_AQ_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_dll_rst_rg/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_dqs_rst/opit_0_inv/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[0]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[1]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[2]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[3]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[4]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[5]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[6]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[7]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[8]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[9]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[10]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[11]/opit_0_inv_L5Q/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[12]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[13]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[14]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[16]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[17]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[18]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_b_ff/opit_0_inv/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_b_neg/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_deb_pre/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_rst/opit_0_inv/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_rst_n_rg/opit_0_inv/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/dll_lock_d[0]/opit_0_inv/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/dll_lock_d[1]/opit_0_inv/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/dll_update_ack_rst_ctrl_d[0]/opit_0_inv/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/dll_update_ack_rst_ctrl_d[1]/opit_0_inv/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/dll_update_req_rst_ctrl/opit_0_inv/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/pll_lock_d[0]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/pll_lock_d[1]/opit_0_inv/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[0]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[1]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[2]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[3]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[5]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[6]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[7]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[8]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/training_error_d[0]/opit_0_inv_L5Q_perm/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/training_error_d[1]/opit_0_inv/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d1/opit_0_inv/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d2/opit_0_inv/CLK (5.374, 5.867, 4.852, 5.237) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKIN1 (5.508, 6.020, 4.986, 5.391) - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL (5.631, 6.149, 5.111, 5.518) - - clkout0_wl_0 (net) - - clkgate_8/gopclkgate/CLK (6.733, 7.270, 6.213, 6.639) - - clkgate_8/gopclkgate/OUT (6.982, 7.618, 6.462, 6.987) - - ntclkgate_0 (net) - - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLK (6.982, 7.618, 6.462, 6.987) - - ddrphy_clkin (100.00MHZ) (drive 5464 loads) - - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV (6.982, 7.618, 6.462, 6.987) - - u_axi_ddr_top/clk (net) - - clkbufg_0/gopclkbufg/CLK (9.134, 9.809, 8.612, 9.175) - - clkbufg_0/gopclkbufg/CLKOUT (9.134, 9.809, 8.612, 9.175) - - ntclkbufg_0 (net) - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[2]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[3]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[9]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[10]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[11]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[12]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[13]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[14]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_ba[0]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_ba[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_cas_n/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_cke/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_cs_n/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_odt/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_ras_n/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_we_n/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cke_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[2]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[4]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[6]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[7]/opit_0_inv_AQ_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_pwron_pass/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[2]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[4]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[6]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[8]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[10]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[12]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[14]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[15]/opit_0_inv_AQ_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[0]/opit_0_inv_L5Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[2]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[4]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[6]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[8]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[10]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[12]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[14]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[15]/opit_0_inv_AQ_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tmod_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tmrd_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_txpr_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit[2]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit[4]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit[6]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit[8]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit[9]/opit_0_inv_AQ_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[9]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[10]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[11]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[12]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[13]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[14]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_ba[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_ba[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_cas_n/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_cke/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_cs_n/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_done/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_rst/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[9]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_we_n/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/mr_load_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/mr_load_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/mr_load_done/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/calib_done/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/init_start/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/rdcal_start/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/wrlvl_start/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[2]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[4]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[6]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[7]/opit_0_inv_AQ_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cnt_tmod_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cnt_twldqsen_pass/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[5]/opit_0_inv_L5Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[7]/opit_0_inv_L5Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[8]/opit_0_inv_L5Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[9]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[10]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[11]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[12]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_ba[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_cas_n/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_cke/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_done/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_dqs_req/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_dqs_resp_r/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_odt/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[2]/opit_0_inv_A2Q1/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[4]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[6]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[8]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[10]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[12]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[14]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[16]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[17]/opit_0_inv_AQ_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt_trfc_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/ddrphy_rst_ack_r[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/ddrphy_rst_ack_r[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/ddrphy_rst_req/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/gate_move_en/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/gatecal_start/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/init_adj_rdel/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_address[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_address[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_address[10]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_ba[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_cas_n/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_cs_n/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_done/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_odt/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_ras_n/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[9]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[10]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[11]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[12]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[13]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[14]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[15]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[16]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[17]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_success/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_we_n/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[32]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[64]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[96]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[128]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[160]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[192]/opit_0_inv_A2Q0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[224]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata_en[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata_en[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata_en[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata_en[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rddata_cal/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdel_calibration/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdel_move_en/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/ref_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/ref_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/ref_cnt_done/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/reinit_adj_rdel/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/wr_enable/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/calib_done_r/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/dfi_init_complete/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[6]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[8]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[9]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[10]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[11]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[12]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[13]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[14]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[15]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[30]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[31]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[32]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[33]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[34]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[35]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[36]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[37]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[38]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[39]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[40]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[41]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[9]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[10]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[11]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[12]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[13]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[14]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[30]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[31]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[32]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[33]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[34]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[35]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[36]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[37]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[38]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[39]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[40]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[41]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba[6]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba[7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba[8]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cas_n[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cas_n[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cas_n_d[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cas_n_d[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cke[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cke_d[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cs_n[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cs_n[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cs_n_d[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cs_n_d[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_odt[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_odt[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_odt_d[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_odt_d[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ras_n[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ras_n[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ras_n_d[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ras_n_d[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_we_n[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_we_n[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_we_n_d[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_we_n_d[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[6]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[8]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[9]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[10]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[11]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[12]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[13]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[14]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[15]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[16]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[17]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[18]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[19]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[20]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[21]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[22]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[23]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[24]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[25]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[26]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[27]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[28]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[29]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[30]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[31]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[32]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[33]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[34]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[35]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[36]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[37]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[38]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[39]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[40]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[41]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[42]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[43]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[44]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[45]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[46]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[47]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[48]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[49]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[50]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[51]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[52]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[53]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[54]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[55]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[56]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[57]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[58]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[59]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[60]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[61]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[62]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[63]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[64]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[65]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[66]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[67]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[68]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[69]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[70]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[71]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[72]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[73]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[74]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[75]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[76]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[77]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[78]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[79]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[80]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[81]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[82]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[83]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[84]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[85]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[86]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[87]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[88]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[89]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[90]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[91]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[92]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[93]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[94]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[95]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[96]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[97]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[98]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[99]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[100]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[101]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[102]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[103]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[104]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[105]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[106]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[107]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[108]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[109]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[110]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[111]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[112]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[113]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[114]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[115]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[116]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[117]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[118]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[119]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[120]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[121]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[122]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[123]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[124]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[125]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[126]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[127]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[128]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[129]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[130]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[131]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[132]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[133]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[134]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[135]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[136]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[137]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[138]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[139]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[140]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[141]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[142]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[143]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[144]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[145]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[146]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[147]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[148]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[149]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[150]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[151]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[152]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[153]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[154]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[155]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[156]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[157]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[158]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[159]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[160]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[161]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[162]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[163]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[164]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[165]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[166]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[167]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[168]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[169]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[170]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[171]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[172]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[173]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[174]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[175]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[176]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[177]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[178]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[179]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[180]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[181]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[182]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[183]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[184]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[185]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[186]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[187]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[188]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[189]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[190]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[191]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[192]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[193]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[194]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[195]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[196]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[197]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[198]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[199]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[200]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[201]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[202]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[203]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[204]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[205]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[206]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[207]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[208]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[209]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[210]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[211]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[212]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[213]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[214]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[215]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[216]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[217]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[218]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[219]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[220]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[221]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[222]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[223]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[224]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[225]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[226]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[227]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[228]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[229]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[230]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[231]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[232]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[233]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[234]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[235]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[236]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[237]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[238]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[239]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[240]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[241]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[242]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[243]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[244]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[245]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[246]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[247]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[248]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[249]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[250]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[251]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[252]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[253]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[254]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[255]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[9]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[10]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[11]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[12]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[13]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[14]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[15]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[16]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[17]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[18]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[19]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[20]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[21]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[22]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[23]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[24]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[25]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[26]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[27]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[28]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[29]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[30]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[31]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[32]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[33]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[34]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[35]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[36]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[37]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[38]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[39]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[40]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[41]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[42]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[43]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[44]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[45]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[46]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[47]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[48]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[49]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[50]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[51]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[52]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[53]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[54]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[55]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[56]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[57]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[58]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[59]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[60]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[61]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[62]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[63]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[64]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[65]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[66]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[67]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[68]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[69]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[70]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[71]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[72]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[73]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[74]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[75]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[76]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[77]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[78]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[79]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[80]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[81]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[82]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[83]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[84]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[85]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[86]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[87]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[88]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[89]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[90]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[91]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[92]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[93]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[94]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[95]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[96]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[97]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[98]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[99]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[100]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[101]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[102]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[103]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[104]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[105]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[106]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[107]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[108]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[109]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[110]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[111]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[112]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[113]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[114]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[115]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[116]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[117]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[118]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[119]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[120]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[121]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[122]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[123]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[124]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[125]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[126]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[127]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[128]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[129]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[130]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[131]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[132]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[133]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[134]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[135]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[136]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[137]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[138]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[139]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[140]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[141]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[142]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[143]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[144]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[145]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[146]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[147]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[148]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[149]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[150]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[151]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[152]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[153]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[154]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[155]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[156]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[157]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[158]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[159]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[160]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[161]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[162]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[163]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[164]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[165]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[166]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[167]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[168]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[169]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[170]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[171]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[172]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[173]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[174]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[175]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[176]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[177]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[178]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[179]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[180]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[181]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[182]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[183]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[184]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[185]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[186]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[187]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[188]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[189]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[190]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[191]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[192]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[193]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[194]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[195]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[196]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[197]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[198]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[199]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[200]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[201]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[202]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[203]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[204]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[205]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[206]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[207]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[208]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[209]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[210]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[211]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[212]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[213]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[214]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[215]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[216]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[217]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[218]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[219]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[220]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[221]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[222]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[223]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[224]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[225]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[226]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[227]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[228]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[229]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[230]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[231]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[232]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[233]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[234]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[235]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[236]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[237]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[238]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[239]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[240]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[241]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[242]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[243]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[244]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[245]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[246]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[247]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[248]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[249]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[250]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[251]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[252]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[253]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[254]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[255]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_en[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_en[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_en[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_en[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask[8]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask[24]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[24]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[9]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[10]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[11]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[12]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[13]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[14]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[9]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[10]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[11]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[12]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[13]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[14]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[9]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[10]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[11]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[12]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[13]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[14]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[3]/opit_0_inv_L5Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[9]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[10]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[11]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[12]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[13]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[14]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r1[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_dll_rst_sync/sig_async_r1[0]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_dll_rst_sync/sig_async_r2[0]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_ddc_ca/opit_0/CLK_REGIONAL (10.723, 11.454, 10.222, 10.845) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[1].u_ddc_ca/opit_0/CLK_REGIONAL (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[2].u_ddc_ca/opit_0/CLK_REGIONAL (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[3].u_ddc_ca/opit_0/CLK_REGIONAL (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[1]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[3]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_vld/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_comb_r[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_comb_r[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r1[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r1[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r2[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r2[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r3[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r3[2]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_adj_done/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_cal_error/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_error/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass_d/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[2]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[4]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[5]/opit_0_inv_AQ/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_check_done/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_set_bin_tra[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_set_bin_tra[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_set_bin_tra[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_set_bin_tra[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_set_bin_tra[4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_set_bin_tra[5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_set_bin_tra[6]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_set_bin_tra[7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[2]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[4]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[6]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/opit_0_inv_AQ_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt[0]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ddrphy_gatei/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/dq_rising/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[1]/opit_0_inv_A2Q1/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[7]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[2]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[4]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[6]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/opit_0_inv_AQ_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_done_flag/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_flag/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_resp/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_error/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[1].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[2].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[3].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[4].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[5].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[6].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[7].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/dqs_gate_check_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gate_check/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_check_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[6]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[8]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[9]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[10]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[11]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[12]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[13]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[14]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[15]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[16]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[17]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[18]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[19]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[20]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[21]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[22]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[23]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[24]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[25]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[26]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[27]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[28]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[29]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[30]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[31]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[32]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[33]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[34]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[35]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[36]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[37]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[38]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[39]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[40]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[41]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[42]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[43]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[44]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[45]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[46]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[47]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[48]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[49]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[50]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[51]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[52]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[53]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[54]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[55]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[56]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[57]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[58]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[59]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[60]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[61]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[62]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[63]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rdvalid_r1/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_inc_dec_n/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_rdel_done/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[2]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[4]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[6]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[8]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[9]/opit_0_inv_AQ_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[1]/opit_0_inv_A2Q1/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[7]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[7]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_cal_vld/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_done/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_error/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calibration_d/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_move_done/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_sync/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/reinit_adj_rdel_d/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[1]/opit_0_inv_A2Q1/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[7]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[9]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[10]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[11]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[1]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[7]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[8]/opit_0_inv_AQ/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/CLK_REGIONAL (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_iobufco_dqs/opit_2_O/SYSCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_outbuft_dm/opit_1_IOL/SYSCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_r2[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_r[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_r[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_r[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_r[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[1]/opit_0_inv_MUX4TO1Q/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[3]/opit_0_inv_MUX4TO1Q/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[1]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[2]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[3]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[0]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[1]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[2]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[3]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[0]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[1]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[2]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[3]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4[3]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[1]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[2]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_vld/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_adj_done/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_cal_error/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_error/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass_d/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[1]/opit_0_inv_L5Q/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[3]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[4]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[1]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[3]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[5]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[0]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[1]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[2]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[3]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[4]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[5]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[1]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[2]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[2]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[4]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[5]/opit_0_inv_AQ/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ck_check_done/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[2]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[4]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[6]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/opit_0_inv_AQ_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ddrphy_gatei/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/dq_rising/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[1]/opit_0_inv_A2Q1/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[7]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[2]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[4]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[6]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/opit_0_inv_AQ_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_done_flag/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_flag/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_resp/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_error/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[1].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[2].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[3].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[4].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[5].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[6].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[7].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/dqs_gate_check_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gate_check/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_check_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[6]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[8]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[9]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[10]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[11]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[12]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[13]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[14]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[15]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[16]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[17]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[18]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[19]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[20]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[21]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[22]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[23]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[24]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[25]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[26]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[27]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[28]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[29]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[30]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[31]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[32]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[33]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[34]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[35]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[36]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[37]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[38]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[39]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[40]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[41]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[42]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[43]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[44]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[45]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[46]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[47]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[48]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[49]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[50]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[51]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[52]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[53]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[54]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[55]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[56]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[57]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[58]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[59]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[60]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[61]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[62]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[63]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rdvalid_r1/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/adj_rdel_done/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[2]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[4]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[6]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[8]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[9]/opit_0_inv_AQ/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[1]/opit_0_inv_A2Q1/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[7]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_done/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_error/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_move_done/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_sync/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[1]/opit_0_inv_A2Q1/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[7]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[9]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[10]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[11]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[1]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[7]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[8]/opit_0_inv_AQ/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/u_ddc_dqs/opit_0/CLK_REGIONAL (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/u_iobufco_dqs/opit_2_O/SYSCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/u_outbuft_dm/opit_1_IOL/SYSCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[1]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[2]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[4]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[1]/opit_0_inv_MUX4TO1Q/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[3]/opit_0_inv_MUX4TO1Q/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[1]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[2]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[3]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[0]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[1]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[2]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[3]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[0]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[1]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[2]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[3]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4[3]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[1]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[2]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_vld/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_adj_done/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_cal_error/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_error/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass_d/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[1]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[2]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[3]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[4]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[0]/opit_0_inv_MUX4TO1Q/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[1]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[2]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[3]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[4]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[5]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[0]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[1]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[2]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[3]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[4]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[5]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[1]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[2]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[2]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[4]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[5]/opit_0_inv_AQ_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_check_done/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[2]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[4]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[6]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/opit_0_inv_AQ_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt[0]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ddrphy_gatei/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/dq_rising/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[1]/opit_0_inv_A2Q1/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[7]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[2]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[4]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[6]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/opit_0_inv_AQ_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_done_flag/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_flag/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_resp/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_error/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[1]/opit_0_inv_L5Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[1].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[2].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[3].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[4].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[5].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[6].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[7].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/dqs_gate_check_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gate_check/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_check_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[6]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[8]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[9]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[10]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[11]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[12]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[13]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[14]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[15]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[16]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[17]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[18]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[19]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[20]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[21]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[22]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[23]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[24]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[25]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[26]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[27]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[28]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[29]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[30]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[31]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[32]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[33]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[34]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[35]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[36]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[37]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[38]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[39]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[40]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[41]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[42]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[43]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[44]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[45]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[46]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[47]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[48]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[49]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[50]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[51]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[52]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[53]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[54]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[55]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[56]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[57]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[58]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[59]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[60]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[61]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[62]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[63]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rdvalid_r1/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/adj_rdel_done/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[2]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[4]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[5]/opit_0_inv_A2Q20/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[8]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[9]/opit_0_inv_AQ_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[1]/opit_0_inv_A2Q1/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[7]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_done/opit_0_inv_L5Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_error/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_move_done/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_sync/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[1]/opit_0_inv_A2Q1/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[7]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[9]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[10]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[11]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[1]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[7]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[8]/opit_0_inv_AQ/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/u_ddc_dqs/opit_0/CLK_REGIONAL (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/u_iobufco_dqs/opit_2_O/SYSCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/u_outbuft_dm/opit_1_IOL/SYSCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[1]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[2]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[4]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[1]/opit_0_inv_MUX4TO1Q/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[3]/opit_0_inv_MUX4TO1Q/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[1]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[2]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[3]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[0]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[1]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[2]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[3]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[0]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[1]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[2]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[3]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4[3]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[1]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[2]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_vld/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_adj_done/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_cal_error/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_error/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass_d/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[1]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[2]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[3]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[4]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[1]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[2]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[3]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[4]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[5]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[0]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[1]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[2]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[3]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[4]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[5]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[1]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[2]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[2]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[4]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[5]/opit_0_inv_AQ/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_check_done/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[2]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[4]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[6]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/opit_0_inv_AQ_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt[1]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt[2]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt[3]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt[4]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ddrphy_gatei/opit_0_inv_MUX4TO1Q/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/dq_rising/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[1]/opit_0_inv_A2Q1/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[3]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[5]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[7]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[2]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[4]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[6]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/opit_0_inv_AQ/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_done_flag/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[1]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[2]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[3]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[4]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[5]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[6]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[1]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[2]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[3]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_flag/opit_0_inv_MUX4TO1Q/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_pass/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[1]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[2]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[1]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[2]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_resp/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_error/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[1]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[2]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[3]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[4]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[5]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[6]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[1].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[2].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[3].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[4].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[5].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[6].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[7].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/dqs_gate_check_pass/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gate_check/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[1]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[2]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[3]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[4]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_check_pass/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[0]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[1]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[2]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[3]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[4]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[5]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[6]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[7]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[8]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[9]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[10]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[11]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[12]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[13]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[14]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[15]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[16]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[17]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[18]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[19]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[20]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[21]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[22]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[23]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[24]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[25]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[26]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[27]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[28]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[29]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[30]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[31]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[32]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[33]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[34]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[35]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[36]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[37]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[38]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[39]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[40]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[41]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[42]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[43]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[44]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[45]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[46]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[47]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[48]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[49]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[50]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[51]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[52]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[53]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[54]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[55]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[56]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[57]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[58]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[59]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[60]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[61]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[62]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[63]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rdvalid_r1/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/adj_rdel_done/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[2]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[4]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[6]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[8]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[9]/opit_0_inv_AQ_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[1]/opit_0_inv_A2Q1/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[7]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_done/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_error/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_move_done/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[0]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[1]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_sync/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[1]/opit_0_inv_A2Q1/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[7]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[9]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[10]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[11]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[1]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[7]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[8]/opit_0_inv_AQ/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/CLK_REGIONAL (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_iobufco_dqs/opit_2_O/SYSCLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_outbuft_dm/opit_1_IOL/SYSCLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_control_path_adj/phy_addr_r[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_control_path_adj/phy_cke_r[3]/opit_0_inv/CLK (10.703, 11.433, 10.202, 10.824) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_control_path_adj/phy_odt_r[3]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_logic_rstn_sync/sig_async_r1[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_logic_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_addr_0/opit_1_IOL/SYSCLK (10.723, 11.454, 10.222, 10.845) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_addr_1/opit_1_IOL/SYSCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_addr_2/opit_1_IOL/SYSCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_addr_3/opit_1_IOL/SYSCLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_addr_4/opit_1_IOL/SYSCLK (10.712, 11.442, 10.211, 10.833) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_addr_5/opit_1_IOL/SYSCLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_addr_6/opit_1_IOL/SYSCLK (10.712, 11.442, 10.211, 10.833) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_addr_7/opit_1_IOL/SYSCLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_addr_8/opit_1_IOL/SYSCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_addr_9/opit_1_IOL/SYSCLK (10.706, 11.436, 10.205, 10.828) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_addr_10/opit_1_IOL/SYSCLK (10.706, 11.436, 10.205, 10.828) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_addr_11/opit_1_IOL/SYSCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_addr_12/opit_1_IOL/SYSCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_addr_13/opit_1_IOL/SYSCLK (10.706, 11.436, 10.205, 10.828) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_addr_14/opit_1_IOL/SYSCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_ba0/opit_1_IOL/SYSCLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_ba1/opit_1_IOL/SYSCLK (10.712, 11.442, 10.211, 10.833) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_ba2/opit_1_IOL/SYSCLK (10.723, 11.454, 10.222, 10.845) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_casn/opit_1_IOL/SYSCLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_cke/opit_1_IOL/SYSCLK (10.712, 11.442, 10.211, 10.833) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_csn/opit_1_IOL/SYSCLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_odt/opit_1_IOL/SYSCLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_rasn/opit_1_IOL/SYSCLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_wen/opit_1_IOL/SYSCLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuftco_ck/opit_3_IOL/SYSCLK (10.717, 11.448, 10.216, 10.839) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[6]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[8]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[9]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[10]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[11]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[12]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[13]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[14]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[15]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[16]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[17]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[18]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[19]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[20]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[21]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[22]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[23]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[24]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[25]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[26]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[27]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[28]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[29]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[30]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[31]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[32]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[33]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[34]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[35]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[36]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[37]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[38]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[39]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[40]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[41]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[42]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[43]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[44]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[45]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[46]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[47]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[48]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[49]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[50]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[51]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[52]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[53]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[54]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[55]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[56]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[57]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[58]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[59]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[60]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[61]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[62]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[63]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[64]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[65]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[66]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[67]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[68]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[69]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[70]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[71]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[72]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[73]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[74]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[75]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[76]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[77]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[78]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[79]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[80]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[81]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[82]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[83]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[84]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[85]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[86]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[87]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[88]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[89]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[90]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[91]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[92]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[93]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[94]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[95]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[96]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[97]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[98]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[99]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[100]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[101]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[102]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[103]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[104]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[105]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[106]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[107]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[108]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[109]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[110]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[111]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[112]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[113]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[114]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[115]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[116]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[117]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[118]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[119]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[120]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[121]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[122]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[123]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[124]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[125]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[126]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[127]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[128]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[129]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[130]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[131]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[132]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[133]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[134]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[135]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[136]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[137]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[138]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[139]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[140]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[141]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[142]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[143]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[144]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[145]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[146]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[147]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[148]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[149]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[150]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[151]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[152]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[153]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[154]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[155]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[156]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[157]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[158]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[159]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[160]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[161]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[162]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[163]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[164]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[165]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[166]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[167]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[168]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[169]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[170]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[171]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[172]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[173]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[174]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[175]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[176]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[177]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[178]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[179]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[180]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[181]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[182]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[183]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[184]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[185]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[186]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[187]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[188]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[189]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[190]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[191]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[192]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[193]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[194]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[195]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[196]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[197]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[198]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[199]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[200]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[201]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[202]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[203]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[204]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[205]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[206]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[207]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[208]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[209]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[210]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[211]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[212]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[213]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[214]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[215]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[216]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[217]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[218]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[219]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[220]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[221]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[222]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[223]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[224]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[225]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[226]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[227]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[228]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[229]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[230]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[231]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[232]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[233]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[234]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[235]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[236]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[237]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[238]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[239]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[240]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[241]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[242]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[243]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[244]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[245]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[246]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[247]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[248]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[249]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[250]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[251]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[252]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[253]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[254]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[255]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_start_rst/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_dqs_training_rstn/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_dqs_training_rstn_d/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_rst_req_d1/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_rst_req_d2/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_rst_req_d3/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/dqs_rst_training_high_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/dqs_rst_training_high_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/dqs_rst_training_high_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[6]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[8]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[9]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[10]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[11]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[12]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[13]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[14]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[6]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[8]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[9]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_baddr_l[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_baddr_l[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_baddr_l[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_baddr_m[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_baddr_m[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_baddr_m[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_l[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_l[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_l[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_l[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_l[4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_l[5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_l[6]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_l[7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_m[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_m[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_m[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_m[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_m[4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_m[6]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_m[7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_cfg_apb/ddr_init_done/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[9]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[10]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[11]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[12]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[13]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[14]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[15]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[16]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[17]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[18]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[19]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[20]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[21]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[22]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[23]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[24]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[25]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[26]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[27]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_id[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_id[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_id[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_id[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_len[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_len[1]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_len[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_len[3]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_new_row/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_new_valid/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_pre_row/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_refresh/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_write/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/r_init/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[9]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[10]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[11]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[12]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_req/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[13]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[14]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[15]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[16]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[17]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[18]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[19]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[20]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[21]/opit_0_inv_L5Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[22]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[23]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[24]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[25]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[26]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[27]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_cmd_ready/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/cnt[2]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/cnt[3]/opit_0_inv_L6Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[9]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[10]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[11]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[12]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[13]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[14]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[15]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[16]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[17]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[18]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[19]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[20]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[21]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[22]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[23]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[24]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[25]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[26]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[27]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_cmd[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_cmd[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_cmd[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_cmd[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_en/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_id[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_id[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_id[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_id[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_tworw/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[6]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[8]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[9]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[10]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[11]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[12]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[13]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[14]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[15]/opit_0_inv/CLK (10.690, 11.420, 10.190, 10.812) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[16]/opit_0_inv/CLK (10.690, 11.420, 10.190, 10.812) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[17]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[18]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[19]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[20]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[21]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[22]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[23]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[24]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[25]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[26]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[27]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_done/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/rw_diff/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm/CLK (10.681, 11.411, 10.181, 10.802) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.681, 11.411, 10.181, 10.802) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm/CLK (10.676, 11.406, 10.175, 10.797) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm/CLK (10.676, 11.406, 10.175, 10.797) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm/CLK (10.676, 11.406, 10.175, 10.797) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm/CLK (10.670, 11.400, 10.169, 10.791) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm/CLK (10.676, 11.406, 10.175, 10.797) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm/CLK (10.670, 11.400, 10.169, 10.791) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm/CLK (10.670, 11.400, 10.169, 10.791) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm/CLK (10.670, 11.400, 10.169, 10.791) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm/CLK (10.670, 11.400, 10.169, 10.791) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm/CLK (10.670, 11.400, 10.169, 10.791) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm/CLK (10.670, 11.400, 10.169, 10.791) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.670, 11.400, 10.169, 10.791) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm/CLK (10.694, 11.424, 10.193, 10.815) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm/CLK (10.694, 11.424, 10.193, 10.815) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm/CLK (10.676, 11.406, 10.175, 10.797) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm/CLK (10.676, 11.406, 10.175, 10.797) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm/CLK (10.676, 11.406, 10.175, 10.797) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm/CLK (10.676, 11.406, 10.175, 10.797) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm/CLK (10.676, 11.406, 10.175, 10.797) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm/CLK (10.694, 11.424, 10.193, 10.815) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm/CLK (10.694, 11.424, 10.193, 10.815) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm/CLK (10.676, 11.406, 10.175, 10.797) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm/CLK (10.676, 11.406, 10.175, 10.797) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm/CLK (10.705, 11.435, 10.204, 10.826) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.705, 11.435, 10.204, 10.826) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm/CLK (10.705, 11.435, 10.204, 10.826) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm/CLK (10.705, 11.435, 10.204, 10.826) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm/CLK (10.697, 11.427, 10.196, 10.818) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm/CLK (10.697, 11.427, 10.196, 10.818) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm/CLK (10.723, 11.454, 10.222, 10.845) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm/CLK (10.723, 11.454, 10.222, 10.845) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm/CLK (10.723, 11.454, 10.222, 10.845) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm/CLK (10.705, 11.435, 10.204, 10.826) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm/CLK (10.714, 11.444, 10.213, 10.835) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm/CLK (10.714, 11.444, 10.213, 10.835) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm/CLK (10.705, 11.435, 10.204, 10.826) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm/CLK (10.685, 11.415, 10.184, 10.806) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.690, 11.420, 10.190, 10.812) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm/CLK (10.685, 11.415, 10.184, 10.806) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm/CLK (10.685, 11.415, 10.184, 10.806) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm/CLK (10.694, 11.424, 10.193, 10.815) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm/CLK (10.690, 11.420, 10.190, 10.812) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm/CLK (10.705, 11.435, 10.204, 10.826) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm/CLK (10.690, 11.420, 10.190, 10.812) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm/CLK (10.699, 11.430, 10.199, 10.821) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm/CLK (10.694, 11.424, 10.193, 10.815) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm/CLK (10.694, 11.424, 10.193, 10.815) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm/CLK (10.685, 11.415, 10.184, 10.806) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm/CLK (10.694, 11.424, 10.193, 10.815) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm/CLK (10.676, 11.406, 10.175, 10.797) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.696, 11.426, 10.195, 10.817) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm/CLK (10.696, 11.426, 10.195, 10.817) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm/CLK (10.696, 11.426, 10.195, 10.817) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm/CLK (10.679, 11.409, 10.178, 10.800) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm/CLK (10.694, 11.424, 10.193, 10.815) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm/CLK (10.705, 11.435, 10.204, 10.826) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm/CLK (10.696, 11.426, 10.195, 10.817) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm/CLK (10.705, 11.435, 10.204, 10.826) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm/CLK (10.696, 11.426, 10.195, 10.817) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm/CLK (10.681, 11.411, 10.181, 10.802) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.681, 11.411, 10.181, 10.802) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm/CLK (10.685, 11.415, 10.184, 10.806) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm/CLK (10.685, 11.415, 10.184, 10.806) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm/CLK (10.705, 11.435, 10.204, 10.826) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm/CLK (10.694, 11.424, 10.193, 10.815) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm/CLK (10.685, 11.415, 10.184, 10.806) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm/CLK (10.705, 11.435, 10.204, 10.826) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm/CLK (10.685, 11.415, 10.184, 10.806) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm/CLK (10.685, 11.415, 10.184, 10.806) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm/CLK (10.685, 11.415, 10.184, 10.806) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm/CLK (10.685, 11.415, 10.184, 10.806) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm/CLK (10.685, 11.415, 10.184, 10.806) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm/CLK (10.699, 11.430, 10.199, 10.821) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.699, 11.430, 10.199, 10.821) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm/CLK (10.723, 11.454, 10.222, 10.845) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm/CLK (10.714, 11.444, 10.213, 10.835) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm/CLK (10.712, 11.442, 10.211, 10.833) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm/CLK (10.703, 11.433, 10.202, 10.824) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm/CLK (10.712, 11.442, 10.211, 10.833) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm/CLK (10.712, 11.442, 10.211, 10.833) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm/CLK (10.703, 11.433, 10.202, 10.824) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm/CLK (10.717, 11.448, 10.216, 10.839) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm/CLK (10.717, 11.448, 10.216, 10.839) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm/CLK (10.717, 11.448, 10.216, 10.839) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm/CLK (10.717, 11.448, 10.216, 10.839) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm/CLK (10.699, 11.430, 10.199, 10.821) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.714, 11.444, 10.213, 10.835) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm/CLK (10.703, 11.433, 10.202, 10.824) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm/CLK (10.703, 11.433, 10.202, 10.824) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm/CLK (10.712, 11.442, 10.211, 10.833) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[0].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.676, 11.406, 10.175, 10.797) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[0].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.676, 11.406, 10.175, 10.797) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[0].trc_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.676, 11.406, 10.175, 10.797) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[0].trc_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.676, 11.406, 10.175, 10.797) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[1].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[1].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[1].trc_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[1].trc_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[2].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.676, 11.406, 10.175, 10.797) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[2].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.670, 11.400, 10.169, 10.791) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[2].trc_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.676, 11.406, 10.175, 10.797) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[2].trc_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.670, 11.400, 10.169, 10.791) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[3].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.685, 11.415, 10.184, 10.806) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[3].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.685, 11.415, 10.184, 10.806) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[3].trc_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.681, 11.411, 10.181, 10.802) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[3].trc_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.685, 11.415, 10.184, 10.806) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[4].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.697, 11.427, 10.196, 10.818) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[4].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.697, 11.427, 10.196, 10.818) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[4].trc_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.697, 11.427, 10.196, 10.818) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[4].trc_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.697, 11.427, 10.196, 10.818) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[5].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.691, 11.422, 10.191, 10.813) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[5].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.691, 11.422, 10.191, 10.813) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[5].trc_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.691, 11.422, 10.191, 10.813) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[5].trc_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.691, 11.422, 10.191, 10.813) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[6].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.670, 11.400, 10.169, 10.791) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[6].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.670, 11.400, 10.169, 10.791) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[6].trc_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.670, 11.400, 10.169, 10.791) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[6].trc_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.670, 11.400, 10.169, 10.791) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[7].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.682, 11.412, 10.182, 10.804) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[7].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.682, 11.412, 10.182, 10.804) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[7].trc_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.682, 11.412, 10.182, 10.804) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[7].trc_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.682, 11.412, 10.182, 10.804) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.676, 11.406, 10.175, 10.797) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.699, 11.430, 10.199, 10.821) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.699, 11.430, 10.199, 10.821) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.699, 11.430, 10.199, 10.821) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.699, 11.430, 10.199, 10.821) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.674, 11.403, 10.173, 10.794) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.674, 11.403, 10.173, 10.794) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.674, 11.403, 10.173, 10.794) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.679, 11.409, 10.178, 10.800) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.679, 11.409, 10.178, 10.800) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.670, 11.400, 10.169, 10.791) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.676, 11.406, 10.175, 10.797) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.670, 11.400, 10.169, 10.791) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.670, 11.400, 10.169, 10.791) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.670, 11.400, 10.169, 10.791) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.685, 11.415, 10.184, 10.806) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.681, 11.411, 10.181, 10.802) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.681, 11.411, 10.181, 10.802) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.690, 11.420, 10.190, 10.812) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.681, 11.411, 10.181, 10.802) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.670, 11.400, 10.169, 10.791) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.682, 11.412, 10.182, 10.804) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.682, 11.412, 10.182, 10.804) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.682, 11.412, 10.182, 10.804) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.682, 11.412, 10.182, 10.804) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.674, 11.403, 10.173, 10.794) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.694, 11.424, 10.193, 10.815) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.694, 11.424, 10.193, 10.815) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.694, 11.424, 10.193, 10.815) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.697, 11.427, 10.196, 10.818) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.712, 11.442, 10.211, 10.833) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.715, 11.446, 10.214, 10.837) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.712, 11.442, 10.211, 10.833) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.712, 11.442, 10.211, 10.833) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.712, 11.442, 10.211, 10.833) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.721, 11.451, 10.220, 10.842) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.715, 11.446, 10.214, 10.837) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.715, 11.446, 10.214, 10.837) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.700, 11.431, 10.200, 10.822) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.712, 11.442, 10.211, 10.833) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.712, 11.442, 10.211, 10.833) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.715, 11.446, 10.214, 10.837) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.703, 11.433, 10.202, 10.824) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.694, 11.424, 10.193, 10.815) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.694, 11.424, 10.193, 10.815) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.694, 11.424, 10.193, 10.815) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.712, 11.442, 10.211, 10.833) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.694, 11.424, 10.193, 10.815) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.682, 11.412, 10.182, 10.804) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.700, 11.431, 10.200, 10.822) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.682, 11.412, 10.182, 10.804) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.700, 11.431, 10.200, 10.822) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.682, 11.412, 10.182, 10.804) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.700, 11.431, 10.200, 10.822) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.706, 11.436, 10.205, 10.828) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.706, 11.436, 10.205, 10.828) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.715, 11.446, 10.214, 10.837) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.706, 11.436, 10.205, 10.828) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.706, 11.436, 10.205, 10.828) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.697, 11.427, 10.196, 10.818) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.700, 11.431, 10.200, 10.822) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.715, 11.446, 10.214, 10.837) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.715, 11.446, 10.214, 10.837) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.700, 11.431, 10.200, 10.822) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.700, 11.431, 10.200, 10.822) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.700, 11.431, 10.200, 10.822) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.712, 11.442, 10.211, 10.833) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.721, 11.451, 10.220, 10.842) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.715, 11.446, 10.214, 10.837) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.721, 11.451, 10.220, 10.842) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.721, 11.451, 10.220, 10.842) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.721, 11.451, 10.220, 10.842) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[6]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[8]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[9]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[10]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[11]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[12]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[13]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[14]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[15]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[16]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[17]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[18]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[19]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[20]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[21]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[22]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[23]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[24]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[25]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[26]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[27]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[28]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[29]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[30]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[31]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[32]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[33]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[34]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[35]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[36]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[38]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[39]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[40]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[41]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[42]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_valid_d1/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/cmd_act_pass/opit_0_inv_L5Q_perm/CLK (10.717, 11.448, 10.216, 10.839) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/ctrl_back_rdy/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/cmd_rd_pass/opit_0_inv_MUX4TO1Q/CLK (10.705, 11.435, 10.204, 10.826) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm/CLK (10.717, 11.448, 10.216, 10.839) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/r_cnt_pass/opit_0_inv_MUX4TO1Q/CLK (10.723, 11.454, 10.222, 10.845) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm/CLK (10.717, 11.448, 10.216, 10.839) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm/CLK (10.723, 11.454, 10.222, 10.845) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm/CLK (10.732, 11.463, 10.231, 10.854) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm/CLK (10.732, 11.463, 10.231, 10.854) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_cmd_accepted_l/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_cmd_accepted_m/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_cmd_act/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[6]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[8]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[9]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[10]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[11]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[12]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[13]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[14]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[15]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[16]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[17]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[18]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[19]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[20]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[21]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[22]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[23]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[24]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[25]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[26]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[27]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_cmd[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_cmd[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_cmd[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_cmd[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_id[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_id[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_id[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_id[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[9]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[10]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[11]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[12]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[13]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[14]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[15]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[16]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[17]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[18]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[19]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[20]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[21]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[22]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[23]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[24]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[25]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[26]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[27]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[28]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[29]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[30]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[31]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[32]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[33]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[34]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[35]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[36]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[38]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[39]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[40]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[41]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[42]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_valid/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.699, 11.430, 10.199, 10.821) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[1].mcdq_tfaw/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.705, 11.435, 10.204, 10.826) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[1].mcdq_tfaw/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[1].mcdq_tfaw/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[1].mcdq_tfaw/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[1].mcdq_tfaw/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.705, 11.435, 10.204, 10.826) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/cnt_pass/opit_0_inv_L5Q_perm/CLK (10.705, 11.435, 10.204, 10.826) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.681, 11.411, 10.181, 10.802) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.681, 11.411, 10.181, 10.802) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.681, 11.411, 10.181, 10.802) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.681, 11.411, 10.181, 10.802) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[3]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.705, 11.435, 10.204, 10.826) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[5]/opit_0_inv_L5Q_perm/CLK (10.705, 11.435, 10.204, 10.826) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[6]/opit_0_inv_L5Q_perm/CLK (10.705, 11.435, 10.204, 10.826) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.723, 11.454, 10.222, 10.845) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt0[1]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt0[2]/opit_0_inv_L5Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm/CLK (10.732, 11.463, 10.231, 10.854) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm/CLK (10.732, 11.463, 10.231, 10.854) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm/CLK (10.723, 11.454, 10.222, 10.845) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/cmd_wr_pass/opit_0_inv_MUX4TO1Q/CLK (10.717, 11.448, 10.216, 10.839) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm/CLK (10.717, 11.448, 10.216, 10.839) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.717, 11.448, 10.216, 10.839) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm/CLK (10.717, 11.448, 10.216, 10.839) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm/CLK (10.717, 11.448, 10.216, 10.839) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_2/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_3/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_4/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_5/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_6/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_7/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_8/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_9/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_10/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_11/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_12/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_13/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_14/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_15/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_16/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_17/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_18/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_19/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_20/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_21/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_22/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_23/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_24/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_25/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_26/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_27/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_28/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_29/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_30/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_31/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_32/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_33/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_34/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_35/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_36/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_38/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_39/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_40/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_41/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_42/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.raddr_msb/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[1]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[4]/opit_0_inv_AQ/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_almost_full/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_rempty/opit_0_inv_AQ_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_wfull/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.waddr_msb/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[4]/opit_0_inv_AQ/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_2/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_3/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_4/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_5/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_6/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_7/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_8/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_9/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_10/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_11/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_12/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_13/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_14/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_15/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_16/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_17/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_18/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_19/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_20/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_21/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_22/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_23/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_24/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_25/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_26/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_27/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_28/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_29/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_30/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_31/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_32/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_33/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_34/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_35/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_36/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_38/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_39/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_40/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_41/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_42/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.raddr_msb/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[1]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[4]/opit_0_inv_AQ/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_almost_full/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_rempty/opit_0_inv_AQ_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_wfull/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.waddr_msb/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[4]/opit_0_inv_AQ/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_a_valid/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_b_valid/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[6]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[8]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[9]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[10]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[11]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[12]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[13]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[14]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[15]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[16]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[17]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[18]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[19]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[20]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[21]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[22]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[23]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[24]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[25]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[26]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[27]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[28]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[29]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[30]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[31]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[32]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[33]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[34]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[35]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[36]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[38]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[39]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[40]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[41]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[42]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[6]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[8]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[9]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[10]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[11]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[12]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[13]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[14]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[15]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[16]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[17]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[18]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[19]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[20]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[21]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[22]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[23]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[24]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[25]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[26]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[27]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[28]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[29]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[30]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[31]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[32]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[33]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[34]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[35]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[36]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[38]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[39]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[40]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[41]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[42]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/poll/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/rd_poll/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/rd_poll_d/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[9]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[10]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[11]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[12]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[13]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[14]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[15]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[16]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[17]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[18]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[19]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[20]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[21]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[22]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[23]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[24]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[25]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[26]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[27]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[28]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[29]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[30]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[31]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[32]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[33]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[34]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[35]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[36]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[38]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[39]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[40]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[41]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[42]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_valid/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[9]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[10]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[11]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[12]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[13]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[14]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[9]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_l[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_l[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_l[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_m[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_m[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_m[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_l[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_l[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_l[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_l[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_m[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_m[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_m[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_m[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rvld/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_wvld_l/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_wvld_m/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[9]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[10]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[11]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[12]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[13]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[14]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[15]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[16]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[17]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[18]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[19]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[20]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[21]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[22]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[23]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[24]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[25]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[26]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_bank[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_bank[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_bank[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_bank[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_bank[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_bank[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_cas_n[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_cas_n[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_cs_n[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_cs_n[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_odt_reg[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_odt_reg_1[0]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_ras_n[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_ras_n[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_we_n[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_we_n[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[6]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[8]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[9]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[10]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[11]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[12]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[13]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[14]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[15]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[16]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[17]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[18]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[19]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[20]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[21]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[22]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[23]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[24]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[25]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[26]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_bank[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_bank[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_bank[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_bank[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_bank[4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_bank[5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_cas_n[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_cas_n[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_cke[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_cs_n[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_cs_n[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_odt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_odt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_ras_n[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_ras_n[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_we_n[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_we_n[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/r_brd_m/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/r_bwr_m/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/fifo_vld/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_0/ram32x1dp/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram32x1dp/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_2/ram32x1dp/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_3/ram32x1dp/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.raddr_msb/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[1]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_rempty/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_wfull/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.waddr_msb/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/rd_data_ff1[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/rd_data_ff1[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/rd_data_ff1[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/rd_data_ff1[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/double_wr/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[5]/opit_0_inv_L5Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[9]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[10]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[11]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[12]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[13]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[14]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[15]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[16]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[17]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[18]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[19]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[20]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[21]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[22]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[23]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[24]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[25]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[26]/opit_0_inv_L5Q_perm/CLK (10.712, 11.442, 10.211, 10.833) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[27]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[28]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[29]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[30]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[31]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[32]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[33]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[34]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[35]/opit_0_inv_L5Q_perm/CLK (10.712, 11.442, 10.211, 10.833) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[37]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[9]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[10]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[11]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[12]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[13]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[14]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[15]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[16]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[17]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[18]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[19]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[20]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[21]/opit_0_inv_L5Q_perm/CLK (10.723, 11.454, 10.222, 10.845) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[22]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[23]/opit_0_inv_L5Q_perm/CLK (10.723, 11.454, 10.222, 10.845) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[24]/opit_0_inv_L5Q_perm/CLK (10.708, 11.439, 10.208, 10.830) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[25]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[26]/opit_0_inv_L5Q_perm/CLK (10.723, 11.454, 10.222, 10.845) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[27]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[28]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[29]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[30]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[31]/opit_0_inv_L5Q_perm/CLK (10.708, 11.439, 10.208, 10.830) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[32]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[33]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[34]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[35]/opit_0_inv_L5Q_perm/CLK (10.708, 11.439, 10.208, 10.830) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[37]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_valid_0/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_valid_1/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/rptr/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/next_len[0]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/next_len[1]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/next_len[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/next_len[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][6]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][8]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][9]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][10]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][11]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][12]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][13]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][14]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][6]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][8]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][9]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][10]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][11]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][12]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][13]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][14]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][6]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][8]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][9]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][10]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][11]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][12]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][13]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][14]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][6]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][8]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][9]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][10]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][11]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][12]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][13]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][14]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][6]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][8]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][9]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][10]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][11]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][12]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][13]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][14]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][6]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][8]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][9]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][10]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][11]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][12]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][13]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][14]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][6]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][8]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][9]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][10]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][11]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][12]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][13]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][14]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][6]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][8]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][9]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][10]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][11]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][12]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][13]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][14]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[8]/opit_0_inv_A2Q1/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[10]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[12]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[14]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[16]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[18]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[20]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[22]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[24]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[26]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[27]/opit_0_inv_AQ_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_data_in_valid/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_id[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_id[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_id[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_id[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_len[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_len[1]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_len[2]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_len[3]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_write/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/ptr/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[6]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[8]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[9]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[10]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[11]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[12]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[13]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[14]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[15]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[16]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[17]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[18]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[19]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[20]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[21]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[22]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[23]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[24]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[25]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[26]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[27]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[28]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[29]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[30]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[31]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[32]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[33]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[34]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[35]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[37]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[39]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[40]/opit_0_inv_MUX8TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[41]/opit_0_inv_MUX8TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[42]/opit_0_inv_MUX8TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[43]/opit_0_inv_MUX8TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[44]/opit_0_inv_MUX8TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[45]/opit_0_inv_MUX8TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[46]/opit_0_inv_MUX8TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[47]/opit_0_inv_MUX8TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[48]/opit_0_inv_MUX8TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[49]/opit_0_inv_MUX8TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[50]/opit_0_inv_MUX8TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[51]/opit_0_inv_MUX8TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[52]/opit_0_inv_MUX8TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[53]/opit_0_inv_MUX8TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[54]/opit_0_inv_MUX8TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[6]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[8]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[9]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[10]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[11]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[12]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[13]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[14]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[15]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[16]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[17]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[18]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[19]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[20]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[21]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[22]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[23]/opit_0_inv/CLK (10.714, 11.444, 10.213, 10.835) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[24]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[25]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[26]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[27]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[28]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[29]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[30]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[31]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[32]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[33]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[34]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[35]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[37]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[39]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[40]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[41]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[42]/opit_0_inv/CLK (10.714, 11.444, 10.213, 10.835) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[43]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[44]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[45]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[46]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[47]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[48]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[49]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[50]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[51]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[52]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[53]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[54]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_valid_0/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_valid_1/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/wptr/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/data_out[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/data_out[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_0/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.raddr_msb/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[1]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[4]/opit_0_inv_AQ/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_rempty/opit_0_inv_AQ_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_wfull/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.waddr_msb/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[4]/opit_0_inv_AQ/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mc3q_wdp_dcp/o_rdy/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mc3q_wdp_dcp/r_wvld[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[192]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[193]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[194]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[195]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[196]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[197]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[198]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[199]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[200]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[201]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[202]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[203]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[204]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[205]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[206]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[207]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[208]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[209]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[210]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[211]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[212]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[213]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[214]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[215]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[216]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[217]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[218]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[219]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[220]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[221]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[222]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[223]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[224]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[225]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[226]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[227]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[228]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[229]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[230]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[231]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[232]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[233]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[234]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[235]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[236]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[237]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[238]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[239]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[240]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[241]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[242]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[243]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[244]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[245]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[246]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[247]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[248]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[249]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[250]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[251]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[252]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[253]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[254]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[255]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[128]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[129]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[130]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[131]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[132]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[133]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[134]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[135]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[136]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[137]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[138]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[139]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[140]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[141]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[142]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[143]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[144]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[145]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[146]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[147]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[148]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[149]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[150]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[151]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[152]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[153]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[154]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[155]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[156]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[157]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[158]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[159]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[160]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[161]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[162]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[163]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[164]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[165]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[166]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[167]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[168]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[169]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[170]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[171]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[172]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[173]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[174]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[175]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[176]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[177]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[178]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[179]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[180]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[181]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[182]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[183]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[184]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[185]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[186]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[187]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[188]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[189]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[190]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[191]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[192]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[193]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[194]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[195]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[196]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[197]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[198]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[199]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[200]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[201]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[202]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[203]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[204]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[205]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[206]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[207]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[208]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[209]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[210]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[211]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[212]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[213]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[214]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[215]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[216]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[217]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[218]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[219]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[220]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[221]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[222]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[223]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[224]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[225]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[226]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[227]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[228]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[229]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[230]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[231]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[232]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[233]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[234]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[235]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[236]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[237]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[238]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[239]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[240]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[241]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[242]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[243]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[244]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[245]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[246]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[247]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[248]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[249]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[250]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[251]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[252]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[253]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[254]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[255]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_wdin_en[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_wvld_m/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wdin_en_dly[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[24]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[6]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[8]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[9]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[10]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[11]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[12]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[13]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[14]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[15]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[16]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[17]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[18]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[19]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[20]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[21]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[22]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[23]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[24]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[25]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[26]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[27]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[28]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[29]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[30]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[31]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[32]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[33]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[34]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[35]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[36]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[37]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[38]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[39]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[40]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[41]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[42]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[43]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[44]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[45]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[46]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[47]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[48]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[49]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[50]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[51]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[52]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[53]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[54]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[55]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[56]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[57]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[58]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[59]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[60]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[61]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[62]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[63]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[64]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[65]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[66]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[67]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[68]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[69]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[70]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[71]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[72]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[73]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[74]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[75]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[76]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[77]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[78]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[79]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[80]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[81]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[82]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[83]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[84]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[85]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[86]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[87]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[88]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[89]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[90]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[91]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[92]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[93]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[94]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[95]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[96]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[97]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[98]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[99]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[100]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[101]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[102]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[103]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[104]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[105]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[106]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[107]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[108]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[109]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[110]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[111]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[112]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[113]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[114]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[115]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[116]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[117]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[118]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[119]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[120]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[121]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[122]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[123]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[124]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[125]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[126]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[127]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[128]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[129]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[130]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[131]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[132]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[133]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[134]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[135]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[136]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[137]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[138]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[139]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[140]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[141]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[142]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[143]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[144]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[145]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[146]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[147]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[148]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[149]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[150]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[151]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[152]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[153]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[154]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[155]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[156]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[157]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[158]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[159]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[160]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[161]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[162]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[163]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[164]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[165]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[166]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[167]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[168]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[169]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[170]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[171]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[172]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[173]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[174]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[175]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[176]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[177]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[178]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[179]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[180]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[181]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[182]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[183]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[184]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[185]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[186]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[187]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[188]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[189]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[190]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[191]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[192]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[193]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[194]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[195]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[196]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[197]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[198]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[199]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[200]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[201]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[202]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[203]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[204]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[205]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[206]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[207]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[208]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[209]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[210]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[211]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[212]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[213]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[214]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[215]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[216]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[217]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[218]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[219]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[220]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[221]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[222]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[223]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[224]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[225]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[226]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[227]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[228]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[229]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[230]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[231]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[232]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[233]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[234]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[235]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[236]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[237]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[238]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[239]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[240]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[241]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[242]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[243]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[244]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[245]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[246]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[247]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[248]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[249]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[250]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[251]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[252]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[253]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[254]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[255]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata_en[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata_en[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/usr_wdp_rdy_dly/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/axi_fifo_full0/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/cnt0_times[0]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/cnt0_times[1]/opit_0_A2Q1/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/cnt0_times[3]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/cnt0_times[5]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/cnt0_times[7]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/cnt0_times[8]/opit_0_AQ_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/cnt1_times[0]/opit_0_L5Q_perm/CLK (10.706, 11.436, 10.205, 10.828) - - - u_axi_ddr_top/cnt1_times[1]/opit_0_A2Q1/CLK (10.706, 11.436, 10.205, 10.828) - - - u_axi_ddr_top/cnt1_times[3]/opit_0_A2Q21/CLK (10.706, 11.436, 10.205, 10.828) - - - u_axi_ddr_top/cnt1_times[5]/opit_0_A2Q21/CLK (10.700, 11.431, 10.200, 10.822) - - - u_axi_ddr_top/cnt1_times[7]/opit_0_A2Q21/CLK (10.700, 11.431, 10.200, 10.822) - - - u_axi_ddr_top/cnt1_times[8]/opit_0_AQ_perm/CLK (10.706, 11.436, 10.205, 10.828) - - - u_axi_ddr_top/cnt_wr_num[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/cnt_wr_num[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/cnt_wr_num[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/delay_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/delay_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/delay_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/delay_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/delay_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_addr_start_fall/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_addr_start_valid0/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_addr_start_valid1/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_cnt_num[0]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_cnt_num[2]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_cnt_num[4]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_cnt_num[6]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_cnt_num[8]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_cnt_num[10]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_cnt_num[12]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_cnt_num[14]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_cnt_num[15]/opit_0_AQ/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_done0/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_done1/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr0[10]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr0[11]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr0[12]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr0[13]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr0[14]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr0[15]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr0[16]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr0[17]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr0[18]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr0[19]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr0[20]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr0[21]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr0[22]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr0[23]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr0[24]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr0[25]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr0[26]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr0[27]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr0[28]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr0[29]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr1[10]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr1[11]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr1[12]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr1[13]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr1[14]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr1[15]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr1[16]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr1[17]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr1[18]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr1[19]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr1[20]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr1[21]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr1[22]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr1[23]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr1[24]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr1[25]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr1[26]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr1[27]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr1[28]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr1[29]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr2[10]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr2[11]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr2[12]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr2[13]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr2[14]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr2[15]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr2[16]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr2[17]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr2[18]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr2[19]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr2[20]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr2[21]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr2[22]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr2[23]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr2[24]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr2[25]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr2[26]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr2[27]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr2[28]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_ddr_sart_addr2[29]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_done_cnt[0]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_done_cnt[1]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_done_cnt[2]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd0_time_permit/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_addr_start_fall/opit_0_L5Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_addr_start_valid0/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_addr_start_valid1/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_cnt_num[0]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_cnt_num[2]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_cnt_num[4]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_cnt_num[6]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_cnt_num[8]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_cnt_num[10]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_cnt_num[12]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_cnt_num[14]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_cnt_num[15]/opit_0_AQ/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_done0/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_done1/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr0[9]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr0[10]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr0[11]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr0[12]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr0[13]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr0[14]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr0[15]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr0[16]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr0[17]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr0[18]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr0[19]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr0[20]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr0[21]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr0[22]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr0[23]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr0[24]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr1[9]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr1[10]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr1[11]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr1[12]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr1[13]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr1[14]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr1[15]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr1[16]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr1[17]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr1[18]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr1[19]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr1[20]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr1[21]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr1[22]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr1[23]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr1[24]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr2[9]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr2[10]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr2[11]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr2[12]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr2[13]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr2[14]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr2[15]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr2[16]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr2[17]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr2[18]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr2[19]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr2[20]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr2[21]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr2[22]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr2[23]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_ddr_sart_addr2[24]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_done_cnt[0]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_done_cnt[1]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_done_cnt[2]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd1_time_permit/opit_0_L5Q_perm/CLK (10.700, 11.431, 10.200, 10.822) - - - u_axi_ddr_top/rd3_data_en0/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd3_data_en1/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd3_data_en2/opit_0/CLK (10.721, 11.451, 10.220, 10.842) - - - u_axi_ddr_top/rd3_ddr_data[0]/opit_0_MUX16TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd3_ddr_data[1]/opit_0_MUX16TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd3_ddr_data[2]/opit_0_MUX16TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd3_ddr_data[3]/opit_0_MUX16TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd3_ddr_data[4]/opit_0_MUX16TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd3_ddr_data[5]/opit_0_MUX16TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd3_ddr_data[6]/opit_0_MUX16TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd3_ddr_data[7]/opit_0_MUX16TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd3_ddr_data[8]/opit_0_MUX16TO1Q/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/rd3_ddr_data[9]/opit_0_MUX16TO1Q/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/rd3_ddr_data[10]/opit_0_MUX16TO1Q/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/rd3_ddr_data[11]/opit_0_MUX16TO1Q/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/rd3_ddr_data[12]/opit_0_MUX16TO1Q/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/rd3_ddr_data[13]/opit_0_MUX16TO1Q/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/rd3_ddr_data[14]/opit_0_MUX16TO1Q/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/rd3_ddr_data[15]/opit_0_MUX16TO1Q/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/rd_all_full/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd_ddr_idle/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd_importance/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd_sta0_reg0/opit_0/CLK (10.717, 11.448, 10.216, 10.839) - - - u_axi_ddr_top/rd_sta0_reg1/opit_0/CLK (10.706, 11.436, 10.205, 10.828) - - - u_axi_ddr_top/rd_sta2_reg0/opit_0/CLK (10.717, 11.448, 10.216, 10.839) - - - u_axi_ddr_top/rd_sta2_reg1/opit_0/CLK (10.706, 11.436, 10.205, 10.828) - - - u_axi_ddr_top/rd_sta_reg[0]/opit_0_L5Q_perm/CLK (10.712, 11.442, 10.211, 10.833) - - - u_axi_ddr_top/rd_sta_reg[1]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd_sta_reg[2]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd_sta_reg[3]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd_sta_reg[4]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd_sta_reg[6]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd_sta_reg[7]/opit_0_L5Q_perm/CLK (10.699, 11.430, 10.199, 10.821) - - - u_axi_ddr_top/rd_wr_fast_empty/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rd_wr_fifo_empty/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/record_addr_valid/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/record_araddr_valid/opit_0_L5Q_perm/CLK (10.703, 11.433, 10.202, 10.824) - - - u_axi_ddr_top/record_data_valid/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rst0/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rx_rd0_addr_valid/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/rx_rd1_addr_valid/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_araddr[5]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_araddr[6]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_araddr[7]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_araddr[8]/opit_0_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_araddr[9]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_araddr[10]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_araddr[11]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_araddr[12]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_araddr[13]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_araddr[14]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_araddr[15]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_araddr[16]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_araddr[17]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_araddr[18]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_araddr[19]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_araddr[20]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_araddr[21]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_araddr[22]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_araddr[23]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_araddr[24]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_araddr[25]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_araddr[26]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_araddr[27]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_araddr[28]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_araddr[29]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_arid[0]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_arid[1]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_arid[2]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_arid[3]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_arlen[0]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[0]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[1]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[2]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[3]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[4]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[5]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[6]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[7]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[8]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[9]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[10]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[11]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[12]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[13]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[14]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[15]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[16]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[17]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[18]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[19]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[20]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[21]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[22]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[23]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[24]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[25]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[26]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[27]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[28]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[29]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[30]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[31]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[32]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[33]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[34]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[35]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[36]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[37]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[38]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[39]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[40]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[41]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[42]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[43]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[44]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[45]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[46]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[47]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[48]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[49]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[50]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[51]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[52]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[53]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[54]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[55]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[56]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[57]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[58]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[59]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[60]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[61]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[62]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[63]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[64]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[65]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[66]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[67]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[68]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[69]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[70]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[71]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[72]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[73]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[74]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[75]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[76]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[77]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[78]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[79]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[80]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[81]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[82]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[83]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[84]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[85]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[86]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[87]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[88]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[89]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[90]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[91]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[92]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[93]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[94]/opit_0_L5Q/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[95]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[96]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[97]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[98]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[99]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[100]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[101]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[102]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[103]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[104]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[105]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[106]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[107]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[108]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[109]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[110]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[111]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[112]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[113]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[114]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[115]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[116]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[117]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[118]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[119]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[120]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[121]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[122]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[123]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[124]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[125]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[126]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[127]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[128]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[129]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[130]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[131]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[132]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[133]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[134]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[135]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[136]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[137]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[138]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[139]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[140]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[141]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[142]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[143]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[144]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[145]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[146]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[147]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[148]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[149]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[150]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[151]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[152]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[153]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[154]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[155]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[156]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[157]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[158]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[159]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[160]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[161]/opit_0_L5Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[162]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[163]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[164]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[165]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[166]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[167]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[168]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[169]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[170]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[171]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[172]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[173]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[174]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[175]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[176]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[177]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[178]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[179]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[180]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[181]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[182]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[183]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[184]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[185]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[186]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[187]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[188]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[189]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[190]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[191]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[192]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[193]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[194]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[195]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[196]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[197]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[198]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[199]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[200]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[201]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[202]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[203]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[204]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[205]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[206]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[207]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[208]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[209]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[210]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[211]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[212]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[213]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[214]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[215]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[216]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[217]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[218]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[219]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[220]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[221]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[222]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[223]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[224]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[225]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[226]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[227]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[228]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[229]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[230]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[231]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[232]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[233]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[234]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[235]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[236]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[237]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[238]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[239]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[240]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[241]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[242]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[243]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[244]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[245]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[246]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[247]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata0[248]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[249]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[250]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[251]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[252]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[253]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[254]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata0[255]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[0]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[1]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[2]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[3]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[4]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[5]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[6]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[7]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[8]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[9]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[10]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[11]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[12]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[13]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[14]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[15]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[16]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[17]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[18]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[19]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[20]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[21]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[22]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[23]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[24]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[25]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[26]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[27]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[28]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[29]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[30]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[31]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[32]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[33]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[34]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[35]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[36]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[37]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[38]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[39]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[40]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[41]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[42]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[43]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[44]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[45]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[46]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[47]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[48]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[49]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[50]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[51]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[52]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[53]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[54]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[55]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[56]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[57]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[58]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[59]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[60]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[61]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[62]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[63]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[64]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[65]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[66]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[67]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[68]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[69]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[70]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[71]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[72]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[73]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[74]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[75]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[76]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[77]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[78]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[79]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[80]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[81]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[82]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[83]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[84]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[85]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[86]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[87]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[88]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[89]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[90]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[91]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[92]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[93]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[94]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[95]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[96]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[97]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[98]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[99]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[100]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[101]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[102]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[103]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[104]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[105]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[106]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[107]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[108]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[109]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[110]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[111]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[112]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[113]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[114]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[115]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[116]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[117]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[118]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[119]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[120]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[121]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[122]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[123]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[124]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[125]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[126]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[127]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[128]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[129]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[130]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[131]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[132]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[133]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[134]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[135]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[136]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[137]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[138]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[139]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[140]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[141]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[142]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[143]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[144]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[145]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[146]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[147]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[148]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[149]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[150]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[151]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[152]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[153]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[154]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[155]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[156]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[157]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[158]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[159]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[160]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[161]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[162]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[163]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[164]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[165]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[166]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[167]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[168]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[169]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[170]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[171]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[172]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[173]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[174]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[175]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[176]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[177]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[178]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[179]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[180]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[181]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[182]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[183]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[184]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[185]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[186]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[187]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[188]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[189]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[190]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[191]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[192]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[193]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[194]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[195]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[196]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[197]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[198]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[199]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[200]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[201]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[202]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[203]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[204]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[205]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[206]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[207]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[208]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[209]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[210]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[211]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[212]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[213]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[214]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[215]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[216]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[217]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[218]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[219]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[220]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[221]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[222]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[223]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[224]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[225]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[226]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[227]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[228]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[229]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[230]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[231]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[232]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[233]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[234]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[235]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[236]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[237]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[238]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[239]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[240]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[241]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[242]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[243]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[244]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[245]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[246]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[247]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/s_axi_rdata1[248]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[249]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[250]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[251]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[252]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[253]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[254]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/s_axi_rdata1[255]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/switch_data0[0]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/switch_data0[1]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/switch_data0[2]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/switch_data0[3]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0_A2Q1/CLK (10.694, 11.424, 10.193, 10.815) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (10.699, 11.430, 10.199, 10.821) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (10.699, 11.430, 10.199, 10.821) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (10.694, 11.424, 10.193, 10.815) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (10.694, 11.424, 10.193, 10.815) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (10.688, 11.418, 10.187, 10.809) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[11]/opit_0_inv_A2Q21/CLK (10.688, 11.418, 10.187, 10.809) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm/CLK (10.705, 11.435, 10.204, 10.826) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm/CLK (10.705, 11.435, 10.204, 10.826) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/CLK (10.705, 11.435, 10.204, 10.826) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm/CLK (10.705, 11.435, 10.204, 10.826) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm/CLK (10.708, 11.439, 10.208, 10.830) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm/CLK (10.708, 11.439, 10.208, 10.830) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm/CLK (10.708, 11.439, 10.208, 10.830) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm/CLK (10.694, 11.424, 10.193, 10.815) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[11]/opit_0_L5Q_perm/CLK (10.694, 11.424, 10.193, 10.815) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0/CLK (10.705, 11.435, 10.204, 10.826) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/opit_0/CLK (10.696, 11.426, 10.195, 10.817) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/opit_0/CLK (10.696, 11.426, 10.195, 10.817) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/opit_0/CLK (10.705, 11.435, 10.204, 10.826) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/opit_0/CLK (10.690, 11.420, 10.190, 10.812) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/opit_0/CLK (10.690, 11.420, 10.190, 10.812) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/opit_0/CLK (10.690, 11.420, 10.190, 10.812) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/opit_0/CLK (10.685, 11.415, 10.184, 10.806) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK (10.685, 11.415, 10.184, 10.806) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/CLK (10.685, 11.415, 10.184, 10.806) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/opit_0/CLK (10.685, 11.415, 10.184, 10.806) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[11]/opit_0/CLK (10.685, 11.415, 10.184, 10.806) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/CLK (10.696, 11.426, 10.195, 10.817) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[1]/opit_0/CLK (10.696, 11.426, 10.195, 10.817) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[2]/opit_0/CLK (10.696, 11.426, 10.195, 10.817) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[3]/opit_0/CLK (10.696, 11.426, 10.195, 10.817) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/CLK (10.690, 11.420, 10.190, 10.812) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[5]/opit_0/CLK (10.690, 11.420, 10.190, 10.812) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[6]/opit_0/CLK (10.685, 11.415, 10.184, 10.806) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[7]/opit_0/CLK (10.685, 11.415, 10.184, 10.806) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/CLK (10.685, 11.415, 10.184, 10.806) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[9]/opit_0/CLK (10.685, 11.415, 10.184, 10.806) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[10]/opit_0/CLK (10.685, 11.415, 10.184, 10.806) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[11]/opit_0/CLK (10.685, 11.415, 10.184, 10.806) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.726, 11.457, 10.225, 10.848) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.709, 11.440, 10.209, 10.831) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.694, 11.424, 10.193, 10.815) - - - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[3].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.699, 11.430, 10.199, 10.821) - - - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0/CLK (10.714, 11.444, 10.213, 10.835) - - - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK (10.714, 11.444, 10.213, 10.835) - - - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (10.717, 11.448, 10.216, 10.839) - - - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (10.717, 11.448, 10.216, 10.839) - - - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (10.723, 11.454, 10.222, 10.845) - - - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (10.723, 11.454, 10.222, 10.845) - - - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.726, 11.457, 10.225, 10.848) - - - u_axi_ddr_top/u_axi_rd_connect/cnt_times[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/cnt_times[2]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/cnt_times[4]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/cnt_times[6]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/cnt_times[7]/opit_0_inv_AQ/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/ddr_fifo_full0/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/rd0_fifo_empty0/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/rd0_fifo_full0/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/rd1_fifo_full0/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/rd_ddr_valid/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/rd_sta_reg[0]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/rd_sta_reg[1]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/rd_sta_reg[2]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/rd_sta_reg[3]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/rid_dout0[0]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/rid_dout0[1]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/rid_valid_cnt[0]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/rid_valid_cnt[1]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/rid_valid_cnt[2]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[10]/opit_0_inv_AQ/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[10]/opit_0_inv_AQ/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKA (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[10]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[11]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wr_water_level[1]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wr_water_level[3]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wr_water_level[5]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wr_water_level[7]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wr_water_level[9]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[5]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[6]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[8]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[11]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[10]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[11]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wr_water_level[9]/opit_0_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[5]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[6]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[8]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[11]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm_inv/CLKA[0] (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm_inv/CLKA[0] (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[11]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[1]/opit_0_A2Q1/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[3]/opit_0_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[5]/opit_0_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[7]/opit_0_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[9]/opit_0_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM18K/iGopDrm/CLKA[0] (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[3].U_GTP_DRM18K/iGopDrm/CLKA[0] (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[3].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[4].U_GTP_DRM18K/iGopDrm/CLKA[0] (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[4].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/CLKA[0] (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[6].U_GTP_DRM18K/iGopDrm/CLKA[0] (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[6].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[7].U_GTP_DRM18K/iGopDrm/CLKA[0] (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[7].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_axi_wr_connect/axi_addr0[0]/opit_0_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_addr0[1]/opit_0_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_addr0[2]/opit_0_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_addr0[3]/opit_0_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_addr0[4]/opit_0_A2Q1/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_addr0[6]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_addr0[8]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_addr0[10]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_addr0[12]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_addr0[14]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_addr0[16]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_addr0[18]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_addr0[19]/opit_0_AQ/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_addr_valid0/opit_0_L5Q_perm/CLK (10.705, 11.435, 10.204, 10.826) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[0]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[1]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[2]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[3]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[4]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[5]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[6]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[7]/opit_0_L5Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[8]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[9]/opit_0_L5Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[10]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[11]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[12]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[13]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[14]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[15]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[16]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[17]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[18]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[19]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[20]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[21]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[22]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[23]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[24]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[25]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[26]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[27]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[28]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[29]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[30]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[31]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[32]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[33]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[34]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[35]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[36]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[37]/opit_0_L5Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[38]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[39]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[40]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[41]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[42]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[43]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[44]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[45]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[46]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[47]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[48]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[49]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[50]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[51]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[52]/opit_0_L5Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[53]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[54]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[55]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[56]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[57]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[58]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[59]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[60]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[61]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[62]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[63]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/axi_data_valid0/opit_0_L5Q_perm/CLK (10.705, 11.435, 10.204, 10.826) - - - u_axi_ddr_top/u_axi_wr_connect/cnt_times[0]/opit_0_L5Q_perm/CLK (10.703, 11.433, 10.202, 10.824) - - - u_axi_ddr_top/u_axi_wr_connect/cnt_times[2]/opit_0_A2Q21/CLK (10.697, 11.427, 10.196, 10.818) - - - u_axi_ddr_top/u_axi_wr_connect/cnt_times[4]/opit_0_A2Q21/CLK (10.697, 11.427, 10.196, 10.818) - - - u_axi_ddr_top/u_axi_wr_connect/cnt_times[6]/opit_0_A2Q21/CLK (10.703, 11.433, 10.202, 10.824) - - - u_axi_ddr_top/u_axi_wr_connect/ddr0_valid_fall0/opit_0_L5Q/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/ddr0_valid_fall2/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/ddr1_valid_fall0/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/ddr1_valid_fall2/opit_0/CLK (10.717, 11.448, 10.216, 10.839) - - - u_axi_ddr_top/u_axi_wr_connect/ddr3_valid_fall0/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/ddr3_valid_fall2/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/delay_cnt0[0]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/delay_cnt0[1]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/delay_cnt0[2]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/delay_cnt1[0]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/delay_cnt1[1]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/delay_cnt1[2]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/delay_cnt3[0]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/delay_cnt3[1]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/delay_cnt3[2]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/fifo0_data_full/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/fifo1_data_full/opit_0_L5Q_perm/CLK (10.696, 11.426, 10.195, 10.817) - - - u_axi_ddr_top/u_axi_wr_connect/fifo3_data_full/opit_0_L5Q_perm/CLK (10.691, 11.422, 10.191, 10.813) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[11]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[5]/opit_0_A2Q1/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[7]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[9]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[2]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[3]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[5]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[6]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[7]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[9]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[10]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[11]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0/CLK (10.681, 11.411, 10.181, 10.802) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm/CLK (10.696, 11.426, 10.195, 10.817) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm/CLK (10.696, 11.426, 10.195, 10.817) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/CLK (10.696, 11.426, 10.195, 10.817) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm/CLK (10.696, 11.426, 10.195, 10.817) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/opit_0/CLK (10.681, 11.411, 10.181, 10.802) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/opit_0/CLK (10.705, 11.435, 10.204, 10.826) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/opit_0/CLK (10.687, 11.417, 10.186, 10.808) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/opit_0/CLK (10.714, 11.444, 10.213, 10.835) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/opit_0/CLK (10.681, 11.411, 10.181, 10.802) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/opit_0/CLK (10.705, 11.435, 10.204, 10.826) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK (10.681, 11.411, 10.181, 10.802) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/CLK (10.705, 11.435, 10.204, 10.826) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/opit_0/CLK (10.681, 11.411, 10.181, 10.802) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[11]/opit_0/CLK (10.705, 11.435, 10.204, 10.826) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[5]/opit_0_A2Q1/CLK (10.687, 11.417, 10.186, 10.808) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[7]/opit_0_A2Q21/CLK (10.687, 11.417, 10.186, 10.808) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[9]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[2]/opit_0/CLK (10.681, 11.411, 10.181, 10.802) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[3]/opit_0/CLK (10.705, 11.435, 10.204, 10.826) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/CLK (10.681, 11.411, 10.181, 10.802) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[5]/opit_0/CLK (10.687, 11.417, 10.186, 10.808) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[6]/opit_0/CLK (10.687, 11.417, 10.186, 10.808) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[7]/opit_0/CLK (10.705, 11.435, 10.204, 10.826) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/CLK (10.681, 11.411, 10.181, 10.802) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[9]/opit_0/CLK (10.687, 11.417, 10.186, 10.808) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[10]/opit_0/CLK (10.681, 11.411, 10.181, 10.802) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[11]/opit_0/CLK (10.681, 11.411, 10.181, 10.802) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0/CLK (10.688, 11.418, 10.187, 10.809) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (10.705, 11.435, 10.204, 10.826) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (10.705, 11.435, 10.204, 10.826) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (10.694, 11.424, 10.193, 10.815) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (10.694, 11.424, 10.193, 10.815) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (10.688, 11.418, 10.187, 10.809) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm/CLK (10.699, 11.430, 10.199, 10.821) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm/CLK (10.699, 11.430, 10.199, 10.821) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/CLK (10.699, 11.430, 10.199, 10.821) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm/CLK (10.690, 11.420, 10.190, 10.812) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm/CLK (10.699, 11.430, 10.199, 10.821) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm/CLK (10.685, 11.415, 10.184, 10.806) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm/CLK (10.685, 11.415, 10.184, 10.806) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/opit_0/CLK (10.690, 11.420, 10.190, 10.812) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/opit_0/CLK (10.694, 11.424, 10.193, 10.815) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/opit_0/CLK (10.690, 11.420, 10.190, 10.812) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/opit_0/CLK (10.714, 11.444, 10.213, 10.835) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/opit_0/CLK (10.685, 11.415, 10.184, 10.806) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/opit_0/CLK (10.685, 11.415, 10.184, 10.806) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK (10.674, 11.403, 10.173, 10.794) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/CLK (10.697, 11.427, 10.196, 10.818) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/opit_0/CLK (10.674, 11.403, 10.173, 10.794) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[11]/opit_0/CLK (10.674, 11.403, 10.173, 10.794) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[5]/opit_0_A2Q1/CLK (10.703, 11.433, 10.202, 10.824) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[7]/opit_0_A2Q21/CLK (10.703, 11.433, 10.202, 10.824) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[9]/opit_0_A2Q21/CLK (10.697, 11.427, 10.196, 10.818) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[2]/opit_0/CLK (10.694, 11.424, 10.193, 10.815) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[3]/opit_0/CLK (10.714, 11.444, 10.213, 10.835) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/CLK (10.714, 11.444, 10.213, 10.835) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[5]/opit_0/CLK (10.714, 11.444, 10.213, 10.835) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[6]/opit_0/CLK (10.703, 11.433, 10.202, 10.824) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[7]/opit_0/CLK (10.714, 11.444, 10.213, 10.835) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/CLK (10.697, 11.427, 10.196, 10.818) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[9]/opit_0/CLK (10.714, 11.444, 10.213, 10.835) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[10]/opit_0/CLK (10.694, 11.424, 10.193, 10.815) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[11]/opit_0/CLK (10.697, 11.427, 10.196, 10.818) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.721, 11.451, 10.220, 10.842) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.682, 11.412, 10.182, 10.804) - - - u_axi_ddr_top/u_axi_wr_connect/rd_sta0[0]/opit_0/CLK (10.705, 11.435, 10.204, 10.826) - - - u_axi_ddr_top/u_axi_wr_connect/rd_sta0[1]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/rd_sta0[2]/opit_0/CLK (10.699, 11.430, 10.199, 10.821) - - - u_axi_ddr_top/u_axi_wr_connect/rd_sta0[3]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/rd_sta0[4]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/rd_sta0[6]/opit_0/CLK (10.699, 11.430, 10.199, 10.821) - - - u_axi_ddr_top/u_axi_wr_connect/rd_sta0[7]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[0]/opit_0_MUX4TO1Q/CLK (10.712, 11.442, 10.211, 10.833) - - - u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[1]/opit_0_L5Q_perm/CLK (10.699, 11.430, 10.199, 10.821) - - - u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[2]/opit_0_MUX4TO1Q/CLK (10.699, 11.430, 10.199, 10.821) - - - u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[3]/opit_0_L5Q_perm/CLK (10.694, 11.424, 10.193, 10.815) - - - u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[4]/opit_0_L5Q_perm/CLK (10.699, 11.430, 10.199, 10.821) - - - u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[6]/opit_0_L5Q_perm/CLK (10.696, 11.426, 10.195, 10.817) - - - u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[7]/opit_0_L5Q_perm/CLK (10.712, 11.442, 10.211, 10.833) - - - u_axi_ddr_top/u_axi_wr_connect/rx0_addr_valid/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/rx1_addr_valid/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/rx3_addr_valid/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[0]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[2]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[4]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[6]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[8]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[10]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[12]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[14]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[15]/opit_0_AQ/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_done0/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_done1/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr0[13]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr0[14]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr0[15]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr0[16]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr0[17]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr1[13]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr1[14]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr1[15]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr1[16]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr1[17]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr2[13]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr2[14]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr2[15]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr2[16]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr2[17]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr_valid0/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr_valid1/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr_valid2/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[0]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[2]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[4]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[6]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[8]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[10]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[12]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[14]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[15]/opit_0_AQ/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_done0/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_done1/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr0[13]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr0[14]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr0[15]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr0[16]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr0[17]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr1[13]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr1[14]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr1[15]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr1[16]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr1[17]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr2[13]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr2[14]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr2[15]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr2[16]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr2[17]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr_valid0/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr_valid1/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr_valid2/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[0]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[2]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[4]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[6]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[8]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[10]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[12]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[14]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[15]/opit_0_AQ/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_done0/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_done1/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr0[13]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr0[14]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr0[15]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr1[13]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr1[14]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr1[15]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr2[13]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr2[14]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr2[15]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr_valid0/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr_valid1/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr_valid2/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0_A2Q1/CLK (10.679, 11.409, 10.178, 10.800) - - - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (10.703, 11.433, 10.202, 10.824) - - - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (10.703, 11.433, 10.202, 10.824) - - - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (10.697, 11.427, 10.196, 10.818) - - - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (10.697, 11.427, 10.196, 10.818) - - - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (10.691, 11.422, 10.191, 10.813) - - - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[11]/opit_0_inv_A2Q21/CLK (10.691, 11.422, 10.191, 10.813) - - - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm/CLK (10.714, 11.444, 10.213, 10.835) - - - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm/CLK (10.696, 11.426, 10.195, 10.817) - - - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/CLK (10.714, 11.444, 10.213, 10.835) - - - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm/CLK (10.714, 11.444, 10.213, 10.835) - - - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm/CLK (10.714, 11.444, 10.213, 10.835) - - - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm/CLK (10.714, 11.444, 10.213, 10.835) - - - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm/CLK (10.676, 11.406, 10.175, 10.797) - - - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm/CLK (10.706, 11.436, 10.205, 10.828) - - - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/CLK (10.700, 11.431, 10.200, 10.822) - - - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/CLK (10.706, 11.436, 10.205, 10.828) - - - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm/CLK (10.706, 11.436, 10.205, 10.828) - - - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[11]/opit_0_L5Q_perm/CLK (10.706, 11.436, 10.205, 10.828) - - - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0/CLK (10.696, 11.426, 10.195, 10.817) - - - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/opit_0/CLK (10.696, 11.426, 10.195, 10.817) - - - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/opit_0/CLK (10.714, 11.444, 10.213, 10.835) - - - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/opit_0/CLK (10.714, 11.444, 10.213, 10.835) - - - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/opit_0/CLK (10.685, 11.415, 10.184, 10.806) - - - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/opit_0/CLK (10.685, 11.415, 10.184, 10.806) - - - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/opit_0/CLK (10.714, 11.444, 10.213, 10.835) - - - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/opit_0/CLK (10.679, 11.409, 10.178, 10.800) - - - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK (10.679, 11.409, 10.178, 10.800) - - - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/CLK (10.670, 11.400, 10.169, 10.791) - - - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/opit_0/CLK (10.679, 11.409, 10.178, 10.800) - - - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[11]/opit_0/CLK (10.679, 11.409, 10.178, 10.800) - - - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/CLK (10.696, 11.426, 10.195, 10.817) - - - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[1]/opit_0/CLK (10.714, 11.444, 10.213, 10.835) - - - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[2]/opit_0/CLK (10.676, 11.406, 10.175, 10.797) - - - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[3]/opit_0/CLK (10.696, 11.426, 10.195, 10.817) - - - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/CLK (10.685, 11.415, 10.184, 10.806) - - - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[5]/opit_0/CLK (10.676, 11.406, 10.175, 10.797) - - - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[6]/opit_0/CLK (10.685, 11.415, 10.184, 10.806) - - - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[7]/opit_0/CLK (10.676, 11.406, 10.175, 10.797) - - - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/CLK (10.670, 11.400, 10.169, 10.791) - - - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[9]/opit_0/CLK (10.676, 11.406, 10.175, 10.797) - - - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[10]/opit_0/CLK (10.670, 11.400, 10.169, 10.791) - - - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[11]/opit_0/CLK (10.670, 11.400, 10.169, 10.791) - - - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB (10.694, 11.424, 10.193, 10.815) - - - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK (10.717, 11.448, 10.216, 10.839) - - - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (10.697, 11.427, 10.196, 10.818) - - - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (10.697, 11.427, 10.196, 10.818) - - - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (10.703, 11.433, 10.202, 10.824) - - - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (10.703, 11.433, 10.202, 10.824) - - - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (10.708, 11.439, 10.208, 10.830) - - - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm/CLK (10.706, 11.436, 10.205, 10.828) - - - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm/CLK (10.706, 11.436, 10.205, 10.828) - - - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm/CLK (10.706, 11.436, 10.205, 10.828) - - - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm/CLK (10.706, 11.436, 10.205, 10.828) - - - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/CLK (10.703, 11.433, 10.202, 10.824) - - - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK (10.703, 11.433, 10.202, 10.824) - - - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/CLK (10.703, 11.433, 10.202, 10.824) - - - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/CLK (10.703, 11.433, 10.202, 10.824) - - - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm/CLK (10.717, 11.448, 10.216, 10.839) - - - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm/CLK (10.717, 11.448, 10.216, 10.839) - - - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0/CLK (10.700, 11.431, 10.200, 10.822) - - - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/opit_0/CLK (10.670, 11.400, 10.169, 10.791) - - - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK (10.700, 11.431, 10.200, 10.822) - - - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK (10.706, 11.436, 10.205, 10.828) - - - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK (10.700, 11.431, 10.200, 10.822) - - - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/CLK (10.706, 11.436, 10.205, 10.828) - - - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/opit_0/CLK (10.700, 11.431, 10.200, 10.822) - - - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK (10.726, 11.457, 10.225, 10.848) - - - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/opit_0/CLK (10.717, 11.448, 10.216, 10.839) - - - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/opit_0/CLK (10.687, 11.417, 10.186, 10.808) - - - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wr_water_level[3]/opit_0_A2Q21/CLK (10.706, 11.436, 10.205, 10.828) - - - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wr_water_level[5]/opit_0_A2Q21/CLK (10.712, 11.442, 10.211, 10.833) - - - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wr_water_level[7]/opit_0_A2Q21/CLK (10.712, 11.442, 10.211, 10.833) - - - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wr_water_level[9]/opit_0_A2Q21/CLK (10.717, 11.448, 10.216, 10.839) - - - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[0]/opit_0/CLK (10.700, 11.431, 10.200, 10.822) - - - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/CLK (10.670, 11.400, 10.169, 10.791) - - - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK (10.715, 11.446, 10.214, 10.837) - - - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/CLK (10.715, 11.446, 10.214, 10.837) - - - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/CLK (10.715, 11.446, 10.214, 10.837) - - - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[5]/opit_0/CLK (10.717, 11.448, 10.216, 10.839) - - - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[6]/opit_0/CLK (10.715, 11.446, 10.214, 10.837) - - - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/CLK (10.700, 11.431, 10.200, 10.822) - - - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[8]/opit_0/CLK (10.717, 11.448, 10.216, 10.839) - - - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/CLK (10.717, 11.448, 10.216, 10.839) - - - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm_inv/CLKA (10.688, 11.418, 10.187, 10.809) - - - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[11]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[3]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[5]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[7]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[9]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[11]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM18K/iGopDrm/CLKA[0] (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[3].U_GTP_DRM18K/iGopDrm/CLKA[0] (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[3].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[4].U_GTP_DRM18K/iGopDrm/CLKA[0] (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[4].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/CLKA[0] (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[6].U_GTP_DRM18K/iGopDrm/CLKA[0] (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[6].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[7].U_GTP_DRM18K/iGopDrm/CLKA[0] (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[7].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.786, 11.517, 10.279, 10.903) - - - u_axi_ddr_top/wr_sta_idle/opit_0/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/wr_sta_reg[0]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/wr_sta_reg[1]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/wr_sta_reg[2]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - u_axi_ddr_top/wr_sta_reg[3]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) - - - - - - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/CLK (6.733, 7.270, 6.213, 6.639) - - ioclk0 (400.00MHZ) (drive 11 loads) - - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT (6.982, 7.618, 6.462, 6.987) - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] (net) - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[1].u_ddc_ca/opit_0/IOCLK (7.041, 7.692, 6.520, 7.059) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[3].u_ddc_ca/opit_0/IOCLK (7.041, 7.692, 6.520, 7.059) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[1].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[2].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[3].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[4].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[5].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[6].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[7].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK (7.041, 7.692, 6.520, 7.059) - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/CLK (6.733, 7.270, 6.213, 6.639) - - ioclk1 (400.00MHZ) (drive 27 loads) - - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT (6.982, 7.618, 6.462, 6.987) - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] (net) - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[1].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[2].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[3].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[4].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[5].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[6].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[7].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK (7.041, 7.692, 6.520, 7.059) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[1].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[2].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[3].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[4].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[5].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[6].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[7].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK (7.041, 7.692, 6.520, 7.059) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[1].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[2].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[3].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[4].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[5].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[6].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[7].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK (7.041, 7.692, 6.520, 7.059) - - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT1 (5.604, 6.121, 5.084, 5.491) - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk_gate_clk_pll (net) - - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg_gate/gopclkbufg/CLK (6.663, 7.199, 6.143, 6.569) - - ioclk_gate_clk (100.00MHZ) (drive 1 loads) - - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg_gate/gopclkbufg/CLKOUT (6.663, 7.199, 6.143, 6.569) - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk_gate_clk (net) - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_ioclk_gate/opit_0_inv_L5Q_perm/CLK (8.194, 8.784, 7.695, 8.179) - - - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_1/u_pll_e3/goppll/CLKIN1 (5.508, 6.020, 4.986, 5.391) - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_1/u_pll_e3/goppll/CLKOUT0_WL (5.631, 6.149, 5.111, 5.518) - - clkout0_wl_1 (net) - - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_2/gopclkgate/CLK (6.733, 7.270, 6.213, 6.639) - - ioclk2 (400.00MHZ) (drive 2 loads) - - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_2/gopclkgate/OUT (6.982, 7.618, 6.462, 6.987) - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [2] (net) - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_ddc_ca/opit_0/IOCLK (7.041, 7.692, 6.520, 7.059) - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[2].u_ddc_ca/opit_0/IOCLK (7.041, 7.692, 6.520, 7.059) - - - - - - - - - - - - - - - - clk_25m (25.00MHZ) (drive 26 loads) - - u_sys_pll/u_pll_e3/goppll/CLKOUT3 (2.793, 3.214, 2.250, 2.558) - - clk_25m (net) - - clkbufg_7/gopclkbufg/CLK (3.852, 4.292, 3.309, 3.636) - - clkbufg_7/gopclkbufg/CLKOUT (3.852, 4.292, 3.309, 3.636) - - ntclkbufg_7 (net) - - u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - - - u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - - - u_ov5640/coms1_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - - - u_ov5640/coms1_reg_config/clock_20k_cnt[1]/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - - - u_ov5640/coms1_reg_config/clock_20k_cnt[2]/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - - - u_ov5640/coms1_reg_config/clock_20k_cnt[3]/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - - - u_ov5640/coms1_reg_config/clock_20k_cnt[4]/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - - - u_ov5640/coms1_reg_config/clock_20k_cnt[5]/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - - - u_ov5640/coms1_reg_config/clock_20k_cnt[6]/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - - - u_ov5640/coms1_reg_config/clock_20k_cnt[7]/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - - - u_ov5640/coms1_reg_config/clock_20k_cnt[8]/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - - - u_ov5640/coms1_reg_config/clock_20k_cnt[9]/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - - - u_ov5640/coms1_reg_config/clock_20k_cnt[10]/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - - - u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - - - u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - - - u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - - - u_ov5640/coms2_reg_config/clock_20k_cnt[1]/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - - - u_ov5640/coms2_reg_config/clock_20k_cnt[2]/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - - - u_ov5640/coms2_reg_config/clock_20k_cnt[3]/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - - - u_ov5640/coms2_reg_config/clock_20k_cnt[4]/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - - - u_ov5640/coms2_reg_config/clock_20k_cnt[5]/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - - - u_ov5640/coms2_reg_config/clock_20k_cnt[6]/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - - - u_ov5640/coms2_reg_config/clock_20k_cnt[7]/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - - - u_ov5640/coms2_reg_config/clock_20k_cnt[8]/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - - - u_ov5640/coms2_reg_config/clock_20k_cnt[9]/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - - - u_ov5640/coms2_reg_config/clock_20k_cnt[10]/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - - - - - - - - - clk_10m (10.00MHZ) (drive 235 loads) - - u_sys_pll/u_pll_e3/goppll/CLKOUT4 (2.788, 3.210, 2.246, 2.553) - - clk_10m (net) - - clkbufg_3/gopclkbufg/CLK (3.847, 4.288, 3.305, 3.631) - - clkbufg_3/gopclkbufg/CLKOUT (3.847, 4.288, 3.305, 3.631) - - ntclkbufg_3 (net) - - ms72xx_ctl/iic_dri_rx/busy/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/byte_over/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/data_out[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/data_out[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/data_out[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/data_out[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/data_out[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/data_out[5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/data_out[6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/data_out[7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/fre_cnt[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/fre_cnt[1]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/fre_cnt[2]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/fre_cnt[3]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/fre_cnt[4]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/pluse_1d/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/pluse_2d/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/pluse_3d/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/receiv_data[0]/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/receiv_data[1]/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/receiv_data[2]/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/receiv_data[3]/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/receiv_data[4]/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/receiv_data[5]/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/receiv_data[6]/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/receiv_data[7]/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/scl_out/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/sda_out/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/send_data[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/send_data[1]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/send_data[2]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/send_data[3]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/send_data[4]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/send_data[5]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/send_data[6]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/send_data[7]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/start_en/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/state_reg[0]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/state_reg[1]/opit_0_inv_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/state_reg[2]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/state_reg[3]/opit_0_inv_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/state_reg[4]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/state_reg[5]/opit_0_inv_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/state_reg[6]/opit_0_inv_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/trans_bit[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/trans_bit[1]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/trans_bit[2]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/trans_byte[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/trans_byte[1]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/trans_byte[2]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/trans_byte[3]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/trans_byte_max[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/trans_byte_max[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/trans_en/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/twr_cnt[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/twr_cnt[1]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/twr_cnt[2]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/twr_cnt[3]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/twr_en/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/w_r_1d/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_rx/w_r_2d/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/busy/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/byte_over/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/data_out[0]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/data_out[1]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/data_out[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/data_out[3]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/data_out[4]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/data_out[5]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/data_out[6]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/data_out[7]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/pluse_1d/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/pluse_2d/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/pluse_3d/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/receiv_data[0]/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/receiv_data[1]/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/receiv_data[2]/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/receiv_data[3]/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/receiv_data[4]/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/receiv_data[5]/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/receiv_data[6]/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/receiv_data[7]/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/scl_out/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/sda_out/opit_0_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/send_data[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/send_data[1]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/send_data[2]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/send_data[3]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/send_data[4]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/send_data[5]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/send_data[6]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/send_data[7]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/start_en/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/state_reg[0]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/state_reg[1]/opit_0_inv_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/state_reg[2]/opit_0_inv_L5Q/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/state_reg[3]/opit_0_inv_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/state_reg[4]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/state_reg[5]/opit_0_inv_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/state_reg[6]/opit_0_inv_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/trans_bit[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/trans_bit[1]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/trans_bit[2]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/trans_byte[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/trans_byte[1]/opit_0_L5Q/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/trans_byte[2]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/trans_byte[3]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/trans_byte_max[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/trans_byte_max[2]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/trans_en/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/twr_cnt[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/twr_cnt[1]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/twr_cnt[2]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/twr_cnt[3]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/twr_en/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/w_r_1d/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/iic_dri_tx/w_r_2d/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKA[0] (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKB[0] (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/addr[0]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/addr[1]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/addr[2]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/addr[3]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/addr[4]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/addr[5]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/addr[6]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/addr[7]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/addr[8]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/addr[9]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/addr[12]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/addr[13]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/busy_1d/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/cmd_index[0]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/cmd_index[1]/opit_0_inv_A2Q1/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/cmd_index[3]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/cmd_index[5]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/cmd_index[7]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/cmd_index[8]/opit_0_inv_AQ/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/data_in[0]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/data_in[1]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/data_in[2]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/data_in[3]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/data_in[4]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/data_in[5]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/data_in[6]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/data_in[7]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/dri_cnt[0]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/dri_cnt[1]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/dri_cnt[2]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/dri_cnt[3]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/dri_cnt[5]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/dri_cnt[6]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/dri_cnt[7]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/dri_cnt[8]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/freq_ensure/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/freq_rec_1d[16]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/freq_rec_1d[17]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/freq_rec_2d[16]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/freq_rec_2d[17]/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/freq_rec[16]/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/freq_rec[17]/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/iic_trig/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/init_over/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/state_reg[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/state_reg[1]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/state_reg[2]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/state_reg[3]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/state_reg[4]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7200_ctl/w_r/opit_0_inv_MUX4TO1Q/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/N325_1_concat_2/iGopDrm/CLKA (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/N325_1_concat_2/iGopDrm/CLKB (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/addr[0]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/addr[1]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/addr[2]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/addr[3]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/addr[4]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/addr[5]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/addr[6]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/addr[7]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/addr[8]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/addr[9]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/addr[10]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/addr[11]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/busy_1d/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/cmd_index[0]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/cmd_index[1]/opit_0_inv_A2Q1/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/cmd_index[3]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/cmd_index[5]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/data_in[0]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/data_in[1]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/data_in[2]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/data_in[3]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/data_in[4]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/data_in[5]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/data_in[6]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/data_in[7]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/delay_cnt[0]/opit_0_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/delay_cnt[2]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/delay_cnt[4]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/delay_cnt[6]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/delay_cnt[8]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/delay_cnt[10]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/delay_cnt[12]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/delay_cnt[14]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/delay_cnt[16]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/delay_cnt[18]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/delay_cnt[20]/opit_0_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/delay_cnt[21]/opit_0_AQ/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/dri_cnt[0]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/dri_cnt[1]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/dri_cnt[2]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/dri_cnt[3]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/iic_trig/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/init_over/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/state_reg[1]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/state_reg[2]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/state_reg[3]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/state_reg[4]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/state_reg[5]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/ms7210_ctl/w_r/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/rstn/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/rstn_temp1/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - - - ms72xx_ctl/rstn_temp2/opit_0/CLK (5.378, 5.873, 4.857, 5.241) - - - rstn_1ms[0]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - rstn_1ms[2]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - - - rstn_1ms[4]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - - - rstn_1ms[6]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - - - rstn_1ms[8]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - - - rstn_1ms[10]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - - - rstn_1ms[12]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - - - rstn_1ms[13]/opit_0_inv_AQ/CLK (5.378, 5.873, 4.857, 5.241) - - - rstn_out0/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - - - rstn_out1/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) - - - - - - - - - - - - - - - - - - cmos1_pclk (84.03MHZ) (drive 118 loads) (min_rise, max_rise, min_fall, max_fall) - - cmos1_pclk (0.000, 0.000, 0.000, 0.000) - - cmos1_pclk_ibuf/opit_0/I (0.076, 0.076, 0.076, 0.076) - - cmos1_pclk_ibuf/opit_0/O (1.123, 1.330, 1.218, 1.443) - - cmos1_pclk_ibuf/ntD (net) - - cmos1_pclk_ibuf/opit_1/IN (1.123, 1.330, 1.218, 1.443) - - cmos1_pclk_ibuf/opit_1/INCK (1.171, 1.406, 1.266, 1.518) - - _N64 (net) - - clkbufg_5/gopclkbufg/CLK (3.657, 3.936, 3.758, 4.054) - - clkbufg_5/gopclkbufg/CLKOUT (3.657, 3.936, 3.758, 4.054) - - ntclkbufg_5 (net) - - u_ov5640/cmos1_8_16bit/de_cnt/opit_0_L5Q_perm/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/de_in0/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/de_in1/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/image_data0[0]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/image_data0[1]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/image_data0[2]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/image_data0[3]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/image_data0[4]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/image_data0[5]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/image_data0[6]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/image_data0[7]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/image_data0[8]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/image_data0[9]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/image_data0[10]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/image_data0[11]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/image_data0[12]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/image_data0[13]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/image_data0[14]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/image_data0[15]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/image_data_valid0/opit_0_L5Q_perm/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/image_in_en/opit_0_L5Q_perm/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/pdata_i0[0]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/pdata_i0[1]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/pdata_i0[2]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/pdata_i0[3]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/pdata_i0[4]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/pdata_i0[5]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/pdata_i0[6]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/pdata_i0[7]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/pdata_i1[0]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/pdata_i1[1]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/pdata_i1[2]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/pdata_i1[3]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/pdata_i1[4]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/pdata_i1[5]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/pdata_i1[6]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/pdata_i1[7]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/pdata_i2[0]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/pdata_i2[1]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/pdata_i2[2]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/pdata_i2[3]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/pdata_i2[4]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/pdata_i2[5]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/pdata_i2[6]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/pdata_i2[7]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/vs_in0/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_8_16bit/vs_in1/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_d_d0[0]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_d_d0[1]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_d_d0[2]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_d_d0[3]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_d_d0[4]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_d_d0[5]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_d_d0[6]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_d_d0[7]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_d_d1[0]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_d_d1[1]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_d_d1[2]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_d_d1[3]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_d_d1[4]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_d_d1[5]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_d_d1[6]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_d_d1[7]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_href_d0/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_href_d1/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_vsync_d0/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/cmos1_vsync_d1/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/cnt0_h[0]/opit_0_L5Q_perm/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/cnt0_w[0]/opit_0_L5Q_perm/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/cnt0_w[2]/opit_0_A2Q21/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/cnt0_w[4]/opit_0_A2Q21/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/cnt0_w[6]/opit_0_A2Q21/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/cnt0_w[7]/opit_0_A2Q0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/cnt0_w[8]/opit_0_L5Q_perm/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/cnt0_w[9]/opit_0_A2Q0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/cnt0_w[10]/opit_0_L5Q_perm/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/image1_en/opit_0_L5Q_perm/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[10]/opit_0_inv_AQ/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[10]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[0]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[5]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[6]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[8]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) - - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.188, 5.521, 5.310, 5.664) - - - - - - - - - - - - - - cmos2_pclk (84.03MHZ) (drive 118 loads) (min_rise, max_rise, min_fall, max_fall) - - cmos2_pclk (0.000, 0.000, 0.000, 0.000) - - cmos2_pclk_ibuf/opit_0/I (0.071, 0.071, 0.071, 0.071) - - cmos2_pclk_ibuf/opit_0/O (1.118, 1.325, 1.213, 1.438) - - cmos2_pclk_ibuf/ntD (net) - - cmos2_pclk_ibuf/opit_1/IN (1.118, 1.325, 1.213, 1.438) - - cmos2_pclk_ibuf/opit_1/OUT (1.200, 1.451, 1.295, 1.565) - - nt_cmos2_pclk (net) - - clkbufg_6/gopclkbufg/CLK (4.020, 4.617, 4.213, 4.777) - - clkbufg_6/gopclkbufg/CLKOUT (4.020, 4.617, 4.213, 4.777) - - ntclkbufg_6 (net) - - u_ov5640/cmos2_8_16bit/de_cnt/opit_0_L5Q/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/de_in0/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/de_in1/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/image_data0[0]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/image_data0[1]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/image_data0[2]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/image_data0[3]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/image_data0[4]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/image_data0[5]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/image_data0[6]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/image_data0[7]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/image_data0[8]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/image_data0[9]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/image_data0[10]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/image_data0[11]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/image_data0[12]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/image_data0[13]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/image_data0[14]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/image_data0[15]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/image_data_valid0/opit_0_L5Q_perm/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/image_in_en/opit_0_L5Q_perm/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/pdata_i0[0]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/pdata_i0[1]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/pdata_i0[2]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/pdata_i0[3]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/pdata_i0[4]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/pdata_i0[5]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/pdata_i0[6]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/pdata_i0[7]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/pdata_i1[0]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/pdata_i1[1]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/pdata_i1[2]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/pdata_i1[3]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/pdata_i1[4]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/pdata_i1[5]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/pdata_i1[6]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/pdata_i1[7]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/pdata_i2[0]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/pdata_i2[1]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/pdata_i2[2]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/pdata_i2[3]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/pdata_i2[4]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/pdata_i2[5]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/pdata_i2[6]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/pdata_i2[7]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/vs_in0/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_8_16bit/vs_in1/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_d_d0[0]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_d_d0[1]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_d_d0[2]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_d_d0[3]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_d_d0[4]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_d_d0[5]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_d_d0[6]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_d_d0[7]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_d_d1[0]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_d_d1[1]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_d_d1[2]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_d_d1[3]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_d_d1[4]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_d_d1[5]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_d_d1[6]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_d_d1[7]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_href_d0/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_href_d1/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_vsync_d0/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/cmos2_vsync_d1/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/cnt1_h[0]/opit_0_L5Q_perm/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/cnt1_w[0]/opit_0_L5Q/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/cnt1_w[2]/opit_0_A2Q21/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/cnt1_w[4]/opit_0_A2Q21/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/cnt1_w[6]/opit_0_A2Q21/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/cnt1_w[7]/opit_0_A2Q0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/cnt1_w[8]/opit_0_L5Q_perm/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/cnt1_w[9]/opit_0_A2Q0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/cnt1_w[10]/opit_0_L5Q_perm/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/image2_en/opit_0_L5Q_perm/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[10]/opit_0_inv_AQ_perm/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[10]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[0]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[5]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[6]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[8]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/CLK (5.551, 6.202, 5.765, 6.387) - - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.551, 6.202, 5.765, 6.387) - - - - - - - - - - - - - - hdmi_in_clk (150.02MHZ) (drive 167 loads) (min_rise, max_rise, min_fall, max_fall) - - hdmi_in_clk (0.000, 0.000, 0.000, 0.000) - - hdmi_in_clk_ibuf/opit_0/I (0.078, 0.078, 0.078, 0.078) - - hdmi_in_clk_ibuf/opit_0/O (1.886, 2.244, 1.342, 1.591) - - hdmi_in_clk_ibuf/ntD (net) - - hdmi_in_clk_ibuf/opit_1/IN (1.886, 2.244, 1.342, 1.591) - - hdmi_in_clk_ibuf/opit_1/INCK (1.934, 2.320, 1.390, 1.666) - - _N37 (net) - - clkbufg_4/gopclkbufg/CLK (4.420, 4.850, 3.882, 4.202) - - clkbufg_4/gopclkbufg/CLKOUT (4.420, 4.850, 3.882, 4.202) - - ntclkbufg_4 (net) - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (5.951, 6.435, 5.434, 5.812) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (5.951, 6.435, 5.434, 5.812) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (5.951, 6.435, 5.434, 5.812) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (5.951, 6.435, 5.434, 5.812) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (5.951, 6.435, 5.434, 5.812) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_A2Q21/CLK (5.951, 6.435, 5.434, 5.812) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm/CLK (5.982, 6.467, 5.465, 5.844) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/CLK (5.982, 6.467, 5.465, 5.844) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[0]/opit_0/CLK (5.982, 6.467, 5.465, 5.844) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/CLK (5.982, 6.467, 5.465, 5.844) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK (5.982, 6.467, 5.465, 5.844) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[5]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[6]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[8]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.951, 6.435, 5.434, 5.812) - - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[0]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[1]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[2]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[3]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/image_fram_cnt1[0]/opit_0_L5Q/CLK (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/image_fram_cnt1[1]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/image_fram_cnt1[2]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/image_fram_cnt1[3]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/image_fram_cnt1[4]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_in0[0]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_in0[1]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_in0[2]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_in0[3]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_in0[4]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_in1[0]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_in1[1]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_in1[2]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_in1[3]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_in1[4]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_in2[0]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_in2[1]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_in2[2]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_in2[3]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_in2[4]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_in3[0]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_in3[1]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_in3[2]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_in3[3]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_in3[4]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_vary0/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/wr_addr_valid0/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/wr_ddr_addr0[19]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/wr_ddr_addr0[20]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/wr_ddr_addr0[21]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/wr_ddr_addr0[22]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/wr_ddr_addr0[23]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/wr_ddr_done0/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/wr_ddr_done1/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/wr_ddr_done2/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[0]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[1]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[2]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/wr_vs0/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/wr_vs1/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/wr_vs2/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_ddr_addr_ctr/u_wr1_addr_ctr/wr_vs_flag/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdm_in_rst/rst/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdm_in_rst/rst0/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdm_in_rst/rst1/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/b_in0[3]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/b_in0[4]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/b_in0[5]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/b_in0[6]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/b_in0[7]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/b_in1[3]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/b_in1[4]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/b_in1[5]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/b_in1[6]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/b_in1[7]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/b_in2[3]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/b_in2[4]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/b_in2[5]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/b_in2[6]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/b_in2[7]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/b_in3[3]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/b_in3[4]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/b_in3[5]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/b_in3[6]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/b_in3[7]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/de_cnt[0]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/de_cnt[1]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/de_in0/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/de_in1/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/de_in2/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/g_in0[2]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/g_in0[3]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/g_in0[4]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/g_in0[5]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/g_in0[6]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/g_in0[7]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/g_in1[2]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/g_in1[3]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/g_in1[4]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/g_in1[5]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/g_in1[6]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/g_in1[7]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/g_in2[2]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/g_in2[3]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/g_in2[4]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/g_in2[5]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/g_in2[6]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/g_in2[7]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/g_in3[2]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/g_in3[3]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/g_in3[4]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/g_in3[5]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/g_in3[6]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/g_in3[7]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/hdmi_in_en/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/hs_cnt[0]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/hs_cnt[1]/opit_0_L5Q/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/hs_in0/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/hs_in1/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/hs_in2/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/r_in0[3]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/r_in0[4]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/r_in0[5]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/r_in0[6]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/r_in0[7]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/r_in1[3]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/r_in1[4]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/r_in1[5]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/r_in1[6]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/r_in1[7]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/r_in2[3]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/r_in2[4]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/r_in2[5]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/r_in2[6]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/r_in2[7]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/r_in3[3]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/r_in3[4]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/r_in3[5]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/r_in3[6]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/r_in3[7]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/vs_in0/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/vs_in1/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - u_hdmi_in_top/vs_in2/opit_0/CLK (5.951, 6.435, 5.434, 5.812) - - - - - - - - - - - - - - eth_rxc (125.00MHZ) (drive 1861 loads) (min_rise, max_rise, min_fall, max_fall) - - eth_rxc (0.000, 0.000, 0.000, 0.000) - - eth_rxc_ibuf/opit_0/I (0.057, 0.057, 0.057, 0.057) - - eth_rxc_ibuf/opit_0/O (1.104, 1.311, 1.199, 1.424) - - eth_rxc_ibuf/ntD (net) - - eth_rxc_ibuf/opit_1/IN (1.104, 1.311, 1.199, 1.424) - - eth_rxc_ibuf/opit_1/INCK (1.152, 1.387, 1.247, 1.499) - - _N66 (net) - - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKIN (1.788, 2.034, 1.880, 2.144) - - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT (4.362, 5.846, 4.454, 5.973) - - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf (net) - - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLK (6.915, 8.445, 7.006, 8.571) - - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT (6.915, 8.445, 7.006, 8.571) - - gmii_clk (net) - - param_manager_inst/clk_ms/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/filiter1_mode_flags_ff0/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/filiter1_mode_flags_ff1/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/filiter1_mode_load/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/filiter2_mode_flags_ff0/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/filiter2_mode_flags_ff1/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/filiter2_mode_load/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/index[0]/opit_0_L5Q/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/index[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/index[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/index[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/key_debounce_key_left/change/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/key_debounce_key_left/clk_ms_ff0/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/key_debounce_key_left/clk_ms_ff1/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/key_debounce_key_left/cnt[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/key_debounce_key_left/cnt[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/key_debounce_key_left/cnt[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/key_debounce_key_left/cnt[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/key_debounce_key_left/cnt[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/key_debounce_key_left/key_ff0/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/key_debounce_key_left/key_ff1/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/key_debounce_key_left/pluse_ms/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/key_debounce_key_left/pressed/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/key_debounce_key_restore/cnt[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/key_debounce_key_restore/cnt[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/key_debounce_key_restore/cnt[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/key_debounce_key_restore/cnt[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/key_debounce_key_restore/cnt[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/key_debounce_key_restore/key_ff0/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/key_debounce_key_restore/key_ff1/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/key_debounce_key_restore/pressed/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/key_debounce_key_right/change/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/key_debounce_key_right/cnt[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/key_debounce_key_right/cnt[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/key_debounce_key_right/cnt[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/key_debounce_key_right/cnt[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/key_debounce_key_right/cnt[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/key_debounce_key_right/key_ff0/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/key_debounce_key_right/key_ff1/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/key_debounce_key_right/pressed/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/modify_H_flags_ff0/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/modify_H_flags_ff1/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/modify_H_flags_ff2/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/modify_H_flags_ff3/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/modify_H_load/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/modify_S_flags_ff0/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/modify_S_flags_ff1/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/modify_S_flags_ff2/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/modify_S_flags_ff3/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/modify_S_load/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/modify_V_flags_ff0/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/modify_V_flags_ff1/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/modify_V_flags_ff2/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/modify_V_flags_ff3/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/modify_V_load/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/ms_cnt[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/ms_cnt[2]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/ms_cnt[4]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/ms_cnt[6]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/ms_cnt[8]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/ms_cnt[10]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/ms_cnt[12]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/ms_cnt[14]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/ms_cnt[16]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/offsetX_flags_ff0/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/offsetX_flags_ff1/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/offsetX_flags_ff2/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/offsetX_flags_ff3/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/offsetX_load/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/offsetY_flags_ff0/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/offsetY_flags_ff1/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/offsetY_flags_ff2/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/offsetY_flags_ff3/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/offsetY_load/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/osd_char_height_flags_ff0/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/osd_char_height_flags_ff1/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/osd_char_height_flags_ff2/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/osd_char_height_flags_ff3/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/osd_char_height_load/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/osd_char_width_flags_ff0/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/osd_char_width_flags_ff1/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/osd_char_width_flags_ff2/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/osd_char_width_flags_ff3/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/osd_char_width_load/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/osd_startX_flags_ff0/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/osd_startX_flags_ff1/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/osd_startX_flags_ff2/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/osd_startX_flags_ff3/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/osd_startX_load/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/osd_startY_flags_ff0/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/osd_startY_flags_ff1/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/osd_startY_flags_ff2/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/osd_startY_flags_ff3/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/osd_startY_load/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_filiter1_mode/cnt[0]/opit_0_L5Q/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_filiter1_mode/cnt[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_filiter1_mode/cnt[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_filiter1_mode/cnt[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_filiter1_mode/cnt[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_filiter1_mode/cnt[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_filiter1_mode/cnt[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_filiter1_mode/cnt[7]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_filiter1_mode/cnt[8]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_filiter1_mode/cnt[9]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_filiter1_mode/cnt[10]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_filiter1_mode/cnt[11]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_filiter1_mode/key_debounce_inst1/change/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_filiter1_mode/key_debounce_inst1/cnt[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_filiter1_mode/key_debounce_inst1/cnt[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_filiter1_mode/key_debounce_inst1/cnt[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_filiter1_mode/key_debounce_inst1/cnt[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_filiter1_mode/key_debounce_inst1/cnt[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_filiter1_mode/key_debounce_inst1/key_ff0/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_filiter1_mode/key_debounce_inst1/key_ff1/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_filiter1_mode/key_debounce_inst1/pressed/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_filiter1_mode/key_debounce_inst2/change/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_filiter1_mode/key_debounce_inst2/cnt[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_filiter1_mode/key_debounce_inst2/cnt[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_filiter1_mode/key_debounce_inst2/cnt[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_filiter1_mode/key_debounce_inst2/cnt[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_filiter1_mode/key_debounce_inst2/cnt[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_filiter1_mode/key_debounce_inst2/key_ff0/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_filiter1_mode/key_debounce_inst2/key_ff1/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_filiter1_mode/key_debounce_inst2/pressed/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_filiter1_mode/pluse/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_filiter1_mode/value[0]/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_filiter1_mode/value[1]/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_filiter1_mode/value[2]/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_filiter2_mode/value[0]/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_filiter2_mode/value[1]/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_filiter2_mode/value[2]/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_modify_H/cnt[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_modify_H/cnt[1]/opit_0_A2Q0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_modify_H/cnt[2]/opit_0_L5Q/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_modify_H/cnt[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_modify_H/cnt[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_modify_H/cnt[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_modify_H/cnt[6]/opit_0_A2Q1/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_modify_H/cnt[8]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_modify_H/cnt[10]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_modify_H/cnt[11]/opit_0_AQ_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_modify_H/pluse/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_modify_H/value[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_modify_H/value[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_modify_H/value[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_modify_H/value[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_modify_H/value[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_modify_H/value[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_modify_H/value[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_modify_H/value[7]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_modify_H/value[8]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_modify_S/value[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_modify_S/value[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_modify_S/value[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_modify_S/value[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_modify_S/value[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_modify_S/value[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_modify_S/value[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_modify_S/value[7]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_modify_S/value[8]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_modify_V/value[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_modify_V/value[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_modify_V/value[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_modify_V/value[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_modify_V/value[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_modify_V/value[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_modify_V/value[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_modify_V/value[7]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_modify_V/value[8]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_offsetX/cnt[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_offsetX/cnt[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_offsetX/cnt[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_offsetX/cnt[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_offsetX/cnt[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_offsetX/cnt[6]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_offsetX/cnt[8]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_offsetX/cnt[10]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_offsetX/cnt[11]/opit_0_AQ_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_offsetX/pluse/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_offsetX/value[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_offsetX/value[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_offsetX/value[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_offsetX/value[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_offsetX/value[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_offsetX/value[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_offsetX/value[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_offsetX/value[7]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_offsetX/value[8]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_offsetX/value[9]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_offsetX/value[10]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_offsetX/value[11]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_offsetY/value[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_offsetY/value[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_offsetY/value[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_offsetY/value[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_offsetY/value[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_offsetY/value[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_offsetY/value[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_offsetY/value[7]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_offsetY/value[8]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_offsetY/value[9]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_offsetY/value[10]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_offsetY/value[11]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_char_height/cnt[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_char_height/cnt[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_char_height/cnt[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_char_height/cnt[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_char_height/cnt[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_char_height/cnt[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_char_height/cnt[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_char_height/cnt[8]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_char_height/cnt[10]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_char_height/cnt[11]/opit_0_AQ_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_char_height/pluse/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_char_height/value[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_char_height/value[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_char_height/value[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_char_height/value[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_char_height/value[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_char_height/value[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_char_height/value[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_char_height/value[7]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_char_height/value[8]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_char_height/value[9]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_char_height/value[10]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_char_width/value[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_char_width/value[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_char_width/value[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_char_width/value[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_char_width/value[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_char_width/value[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_char_width/value[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_char_width/value[7]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_char_width/value[8]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_char_width/value[9]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_char_width/value[10]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_startX/cnt[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_startX/cnt[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_startX/cnt[2]/opit_0_L5Q/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_startX/cnt[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_startX/cnt[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_startX/cnt[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_startX/cnt[6]/opit_0_A2Q1/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_startX/cnt[8]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_startX/cnt[10]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_startX/cnt[11]/opit_0_AQ_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_startX/pluse/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_startX/value[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_startX/value[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_startX/value[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_startX/value[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_startX/value[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_startX/value[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_startX/value[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_startX/value[7]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_startX/value[8]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_startX/value[9]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_startX/value[10]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_startY/value[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_startY/value[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_startY/value[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_startY/value[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_startY/value[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_startY/value[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_startY/value[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_startY/value[7]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_startY/value[8]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_startY/value[9]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_osd_startY/value[10]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_rotate/cnt[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_rotate/cnt[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_rotate/cnt[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_rotate/cnt[3]/opit_0_A2Q0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_rotate/cnt[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_rotate/cnt[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_rotate/cnt[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_rotate/cnt[8]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_rotate/cnt[10]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_rotate/cnt[11]/opit_0_AQ_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_rotate/pluse/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_rotate/value[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_rotate/value[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_rotate/value[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_rotate/value[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_rotate/value[4]/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_rotate/value[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_rotate/value[6]/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_rotate/value[7]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_rotate_A/value[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_rotate_A/value[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_rotate_A/value[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_rotate_A/value[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_rotate_A/value[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_rotate_A/value[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_rotate_A/value[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_rotate_A/value[7]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_rotate_A/value[8]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_rotate_A/value[9]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_zoom/value[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_zoom/value[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_zoom/value[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_zoom/value[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_zoom/value[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_zoom/value[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_zoom/value[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_zoom/value[7]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_zoom/value[8]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/param_zoom/value[9]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/rotate_A_flags_ff0/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/rotate_A_flags_ff1/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/rotate_A_flags_ff2/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/rotate_A_flags_ff3/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/rotate_A_load/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/rotate_flags_ff0/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/rotate_flags_ff1/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/rotate_load/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/selected[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/selected[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/selected[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/selected[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/selected[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/selected[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/selected[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/selected[7]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/selected[8]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/selected[9]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/selected[10]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/selected[11]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/selected[12]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/selected[13]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/zoom_flags_ff0/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/zoom_flags_ff1/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/zoom_flags_ff2/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/zoom_flags_ff3/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - param_manager_inst/zoom_load/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0_A2Q1/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[11]/opit_0_inv_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[11]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[11]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[10]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[11]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[9]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[10]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[11]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[8]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[11]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/arp_rx_done/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/arp_rx_type/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[2]/opit_0_L5Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[4]/opit_0_L6Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[7]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[8]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[9]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[10]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[11]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[12]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[13]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[14]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[15]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[16]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[17]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[18]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[19]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[20]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[21]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[22]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[23]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[24]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[25]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[26]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[27]/opit_0_L5Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[28]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[29]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[30]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[31]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[8]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[9]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[10]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[11]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[12]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[13]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[14]/opit_0_L5Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[15]/opit_0_L5Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[16]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[17]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[18]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[19]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[20]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[21]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[22]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[23]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[24]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[25]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[26]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[27]/opit_0_L5Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[28]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[29]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[30]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[31]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[32]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[33]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[34]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[35]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[36]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[37]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[38]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[39]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[40]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[41]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[42]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[43]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[44]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[45]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[46]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[47]/opit_0_L5Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/error_en/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/eth_type[8]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/eth_type[9]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/eth_type[10]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/eth_type[11]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/eth_type[12]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/eth_type[13]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/eth_type[14]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/eth_type[15]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[8]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[9]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[10]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[11]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[12]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[13]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[14]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[15]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/skip_en/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[8]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[9]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[10]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[11]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[12]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[13]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[14]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[15]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[16]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[17]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[18]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[19]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[20]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[21]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[22]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[23]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[24]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[25]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[26]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[27]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[28]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[29]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[30]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[31]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[8]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[9]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[10]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[11]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[12]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[13]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[14]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[15]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[16]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[17]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[18]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[19]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[20]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[21]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[22]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[23]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[24]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[25]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[26]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[27]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[28]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[29]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[30]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[31]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[8]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[9]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[10]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[11]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[12]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[13]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[14]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[15]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[16]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[17]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[18]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[19]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[20]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[21]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[22]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[23]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[24]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[25]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[26]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[27]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[28]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[29]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[30]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[31]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[32]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[33]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[34]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[35]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[36]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[37]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[38]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[39]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[40]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[41]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[42]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[43]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[44]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[45]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[46]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[47]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[8]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[9]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[10]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[11]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[12]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[13]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[14]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[15]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[16]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[17]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[18]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[19]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[20]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[21]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[22]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[23]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[24]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[25]/opit_0_L5Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[26]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[27]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[28]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[29]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[30]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[31]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[32]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[33]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[34]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[35]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[36]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[37]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[38]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[39]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[40]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[41]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[42]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[43]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[44]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[45]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[46]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[47]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[7][0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[7][1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[18][0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[18][1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[18][2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[18][3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[18][4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[18][5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[18][6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[18][7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[19][0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[19][1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[19][2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[19][3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[19][4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[19][5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[19][6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[19][7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[20][0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[20][1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[20][2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[20][3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[20][4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[20][5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[20][6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[20][7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[21][0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[21][1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[21][2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[21][3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[21][4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[21][5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[21][6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[21][7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[22][0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[22][1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[22][2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[22][3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[22][4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[22][5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[22][6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[22][7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[23][0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[23][1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[23][2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[23][3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[23][4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[23][5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[23][6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[23][7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[26][0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[26][1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[26][2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[26][3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[26][4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[26][5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[26][6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[26][7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[4]/opit_0_A2Q1/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/crc_clr/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/crc_en/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cur_state_reg[0]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cur_state_reg[1]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cur_state_reg[2]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cur_state_reg[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cur_state_reg[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/data_cnt[0]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/data_cnt[1]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/data_cnt[2]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/data_cnt[3]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/data_cnt[4]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/gmii_txd_data[0]/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/gmii_txd_data[1]/opit_0_MUX4TO1Q/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/gmii_txd_data[2]/opit_0_MUX4TO1Q/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/gmii_txd_data[3]/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/gmii_txd_data[4]/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/gmii_txd_data[5]/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/gmii_txd_data[6]/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/gmii_txd_data[7]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/gmii_txd_valid/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/skip_en/opit_0_MUX4TO1Q/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/tx_done_t/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/tx_en_d0/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/tx_en_d1/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/tx_en_d2/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[0]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[4]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[5]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[7]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[8]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[9]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[10]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[11]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[12]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[13]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[14]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[15]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[16]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[17]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[18]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[19]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[20]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[21]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[22]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[23]/opit_0_L5Q/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[24]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[25]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[26]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[27]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[28]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[29]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[30]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[31]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_eth_ctrl/arp_rx_flag/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_eth_ctrl/arp_tx_en/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[7]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_valid/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_eth_ctrl/icmp_tx_req_d0/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_eth_ctrl/protocol_sw_reg[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_en/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_ctl_in/gateigddr_IOL/SYSCLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_rxd_data[0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_rxd_data[1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_rxd_data[2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_rxd_data[3]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_rxd_data[4]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_rxd_data[5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_rxd_data[6]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_rxd_data[7]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_rxd_valid/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gtp_outbuft1/opit_1_IOL/SYSCLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gtp_outbuft6/opit_1_IOL/SYSCLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rx_data[0].gmii_rxd_in/gateigddr_IOL/SYSCLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rx_data[1].gmii_rxd_in/gateigddr_IOL/SYSCLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rx_data[2].gmii_rxd_in/gateigddr_IOL/SYSCLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rx_data[3].gmii_rxd_in/gateigddr_IOL/SYSCLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_tx_data[0].gtp_outbuft1/opit_1_IOL/SYSCLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_tx_data[1].gtp_outbuft1/opit_1_IOL/SYSCLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_tx_data[2].gtp_outbuft1/opit_1_IOL/SYSCLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_tx_data[3].gtp_outbuft1/opit_1_IOL/SYSCLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[7]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[8]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[9]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[10]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[11]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[12]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[13]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[14]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[15]/opit_0_L5Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[16]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[17]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[18]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[19]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[20]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[21]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[22]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[23]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[24]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[25]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[26]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[27]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[28]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[29]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[30]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[31]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[8]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[9]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[10]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[11]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[12]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[13]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[14]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[15]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[16]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[17]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[18]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[19]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[20]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[21]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[22]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[23]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[8]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[9]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[10]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[11]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[12]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[13]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[14]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[15]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[16]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[17]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[18]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[19]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[20]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[21]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[22]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[23]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[24]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[25]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[26]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[27]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[28]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[29]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[30]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[31]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[32]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[33]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[34]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[35]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[36]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[37]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[38]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[39]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[40]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[41]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[42]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[43]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[44]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[45]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[46]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[47]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/error_en/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/eth_type[8]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/eth_type[9]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/eth_type[10]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/eth_type[11]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/eth_type[12]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/eth_type[13]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/eth_type[14]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/eth_type[15]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[4]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[6]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[8]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[10]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[12]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[14]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[15]/opit_0_AQ/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[8]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[9]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[10]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[11]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[12]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[13]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[14]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[15]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[2]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[4]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[6]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[8]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[10]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[12]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[14]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[15]/opit_0_AQ_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_data_d0[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_data_d0[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_data_d0[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_data_d0[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_data_d0[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_data_d0[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_data_d0[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_data_d0[7]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[8]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[9]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[10]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[11]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[12]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[13]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[14]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[15]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_type[0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_type[1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_type[2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_type[3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_type[4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_type[5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_type[6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_type[7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/ip_head_byte_num[2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/ip_head_byte_num[3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/ip_head_byte_num[4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/ip_head_byte_num[5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[8]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[9]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[10]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[11]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[12]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[13]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[14]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[15]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_data[0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_data[1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_data[2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_data[3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_data[4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_data[5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_data[6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_data[7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_en/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_pkt_done/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[8]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[9]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[10]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[11]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[12]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[13]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[14]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[15]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[16]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[17]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[18]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[19]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[20]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[21]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[22]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[23]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[24]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[25]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[26]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[27]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[28]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[29]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[30]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[31]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[7]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[8]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[9]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[10]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[11]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[12]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[13]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[14]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[15]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[16]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[17]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[18]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[19]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[20]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[21]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[22]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[23]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[24]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[25]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[26]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[27]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[28]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[29]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[30]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[31]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/skip_en/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[8]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[9]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[10]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[11]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[12]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[13]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[14]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[15]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer[1]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer[3]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer[5]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer[7]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer[9]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer[11]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer[13]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer[15]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer[17]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer[19]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[1]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[3]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[5]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[7]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[9]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[11]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[13]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[15]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[17]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[19]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[21]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[23]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[25]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[27]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[29]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[31]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cnt[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cnt[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cnt[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cnt[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cnt[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/crc_clr/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/crc_en/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[7]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[2]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[4]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[6]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[8]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[10]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[12]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[14]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[15]/opit_0_AQ_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[0][0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[0][1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[0][2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[0][3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[0][4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[0][5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[0][6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[0][7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[1][0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[1][1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[1][2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[1][3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[1][4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[1][5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[1][6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[1][7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[2][0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[2][1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[2][2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[2][3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[2][4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[2][5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[2][6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[2][7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[3][0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[3][1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[3][2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[3][3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[3][4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[3][5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[3][6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[3][7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[4][0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[4][1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[4][2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[4][3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[4][4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[4][5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[4][6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[4][7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[5][0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[5][1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[5][2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[5][3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[5][4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[5][5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[5][6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[5][7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/gmii_txd_data[0]/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/gmii_txd_data[1]/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/gmii_txd_data[2]/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/gmii_txd_data[3]/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/gmii_txd_data[4]/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/gmii_txd_data[5]/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/gmii_txd_data[6]/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/gmii_txd_data[7]/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/gmii_txd_valid/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][8]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][9]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][10]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][11]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][12]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][13]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][14]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][15]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][16]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][18]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][20]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][22]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][24]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][26]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][28]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][30]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][31]/opit_0_AQ_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][7]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][8]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][9]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][10]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][11]/opit_0_L5Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][12]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][13]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][14]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][15]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][8]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][9]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][10]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][11]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][12]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][13]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][14]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][15]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][16]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][17]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][18]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][19]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][20]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][21]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][22]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][23]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][24]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][25]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][26]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][27]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][28]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][29]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][30]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][31]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][0]/opit_0_L5Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][1]/opit_0_L5Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][3]/opit_0_L5Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][5]/opit_0_L5Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][6]/opit_0_L5Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][7]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][8]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][9]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][10]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][11]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][12]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][13]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][14]/opit_0_L5Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][15]/opit_0_L5Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][8]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][9]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][10]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][11]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][12]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][13]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][14]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][15]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][16]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][17]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][18]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][19]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][20]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][21]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][22]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][23]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][24]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][25]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][26]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][27]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][28]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][29]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][30]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][31]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/real_add_cnt[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/real_add_cnt[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/real_add_cnt[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/real_add_cnt[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/real_add_cnt[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/skip_en/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/start_en_d0/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/start_en_d1/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/start_en_d2/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[4]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[6]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[8]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[10]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[12]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[14]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[15]/opit_0_AQ/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/trig_tx_en/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_bit_sel[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_bit_sel[1]/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[8]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[9]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[10]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[11]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[12]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[13]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[14]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[15]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_done_t/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_req/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[5]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[7]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[9]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[11]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[13]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[15]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_cnt[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_cnt[2]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_cnt[4]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_cnt[6]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_cnt[8]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_cnt[10]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_cnt[12]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_cnt[14]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_cnt[15]/opit_0_AQ_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[8]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[9]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[10]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[11]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[12]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[13]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[14]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[15]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[16]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[17]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[18]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[19]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[20]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[21]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[22]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[23]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[8]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[9]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[10]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[11]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[12]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[13]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[14]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[15]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[16]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[17]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[18]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[19]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[20]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[21]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[22]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[23]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[24]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[25]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[26]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[27]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[28]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[29]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[30]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[31]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[32]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[33]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[34]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[35]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[36]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[37]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[38]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[39]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[40]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[41]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[42]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[43]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[44]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[45]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[46]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[47]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/error_en/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/eth_type[8]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/eth_type[9]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/eth_type[10]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/eth_type[11]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/eth_type[12]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/eth_type[13]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/eth_type[14]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/eth_type[15]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[7]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[8]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[9]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[10]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[11]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[12]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[13]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[14]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[15]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_data[0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_data[1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_data[2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_data[3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_data[4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_data[5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_data[6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_data[7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_en/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_pkt_done/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_pkt_start/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/skip_en/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[8]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[9]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[10]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[11]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[12]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[13]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[14]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[15]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[8]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[9]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[10]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[11]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[12]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[13]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[14]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[15]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_done_cdc/in_req/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_done_cdc/out_ack_sync0/opit_0_inv/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_done_cdc/out_ack_sync1/opit_0_inv/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/opit_0_inv_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[2]/opit_0_inv_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[4]/opit_0_inv_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[6]/opit_0_inv_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[8]/opit_0_inv_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[10]/opit_0_inv_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[10]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[11]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[8]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[11]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (8.446, 10.030, 8.558, 10.181) - - - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_start_i_ff/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/data_count[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/data_count[1]/opit_0_A2Q1/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/data_count[3]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/data_count[5]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/data_count[7]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/flags[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/flags[1]/opit_0_L5Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/flags[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/flags[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/flags[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/flags[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/flags[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/flags[7]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/flags[8]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/flags[9]/opit_0_L5Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/flags[10]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/flags[11]/opit_0_L5Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/flags[12]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/flags[13]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/flags[14]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/flags[15]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/flags[16]/opit_0_L5Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/flags[17]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/flags[18]/opit_0_L5Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/flags[19]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/flags[20]/opit_0_L5Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/flags[21]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/flags[22]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/flags[23]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/flags[24]/opit_0_L5Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/index[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/index[1]/opit_0_A2Q1/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/index[3]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/index[5]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/index[7]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[8]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[9]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[10]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[16]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[17]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[18]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[19]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[20]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[21]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[22]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[23]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[24]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[25]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[32]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[33]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[34]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[35]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[36]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[37]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[38]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[39]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[40]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[41]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[42]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[43]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[44]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[45]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[46]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[47]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[48]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[49]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[50]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[56]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[57]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[58]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[59]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[60]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[61]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[62]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[63]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[64]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[65]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[66]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[72]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[73]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[74]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[75]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[76]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[77]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[78]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[79]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[80]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[81]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[82]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[88]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[89]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[90]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[91]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[92]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[93]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[94]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[95]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[96]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[97]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[98]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[104]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[105]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[106]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[107]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[108]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[109]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[110]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[111]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[112]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[113]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[120]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[121]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[122]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[123]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[124]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[125]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[126]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[127]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[128]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[129]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[130]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[131]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[136]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[137]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[138]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[139]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[140]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[141]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[142]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[143]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[144]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[145]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[146]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[147]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[152]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[153]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[154]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[155]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[156]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[157]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[158]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[159]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[160]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[168]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[169]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[170]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[171]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[172]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[173]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[174]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[175]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[176]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[184]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[185]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[186]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[187]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[188]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[189]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[190]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[191]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/mem[192]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/pkt_data_cnt[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/pkt_data_cnt[1]/opit_0_A2Q1/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/pkt_data_cnt[3]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/pkt_data_cnt[5]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/pkt_data_cnt[7]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/pkt_data_cnt[9]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/pkt_data_cnt[11]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/pkt_data_cnt[13]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/pkt_data_cnt[15]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/state_reg[0]/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/state_reg[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/state_reg[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) - - - udp_wr_mem_inst/state_reg[3]/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) - - - - - - - - - - - - - - - - - clk_100m (100.00MHZ) (drive 0 loads) (min_rise, max_rise, min_fall, max_fall) - - - clk_1080p60Hz (148.44MHZ) (drive 0 loads) (min_rise, max_rise, min_fall, max_fall) - - - clk_720p60Hz (74.22MHZ) (drive 1635 loads) (min_rise, max_rise, min_fall, max_fall) - - - clk_20k (0.02MHZ) (drive 38 loads) (min_rise, max_rise, min_fall, max_fall) - -
- - - Slack - Logic Levels - High Fanout - Start Point - End Point - Exception - Launch Clock - Capture Clock - Clock Edges - Clock Skew - Launch Clock Delay - Capture Clock Delay - Clock Pessimism Removal - Requirement - Data delay - Logic delay - Route delay - - - -0.788 - 5 - 34 - u_zoom_image/data_out_valid2/opit_0/CLK - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[9]/opit_0_L6Q_perm/B3 - - clk_200m - clk_200m - rise-rise - -0.054 - 5.867 - 5.374 - 0.439 - 5.000 - 5.158 - 2.350 (45.6%) - 2.808 (54.4%) - - Path #1: setup slack is -0.788(VIOLATED) - -
- - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_200m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.101 - 3.204 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.078 - 4.282 - - zoom_clk - - - USCM_84_122/CLK_USCM - td - 0.000 - 4.282 - r - USCMROUTE_2/CLKOUT - - - - net (fanout=759) - 1.585 - 5.867 - - ntR3909 - - - CLMA_242_124/CLK - - - - r - u_zoom_image/data_out_valid2/opit_0/CLK - - - CLMA_242_124/Q0 - tco - 0.289 - 6.156 - r - u_zoom_image/data_out_valid2/opit_0/Q - - - - net (fanout=34) - 0.630 - 6.786 - - zoom_data_out_valid - - - - td - 0.288 - 7.074 - f - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Cout - - - - net (fanout=1) - 0.000 - 7.074 - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16324 - - - CLMA_242_96/COUT - td - 0.058 - 7.132 - r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/Cout - - - - net (fanout=1) - 0.000 - 7.132 - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16326 - - - CLMA_242_100/Y1 - td - 0.475 - 7.607 - f - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/Y1 - - - - net (fanout=3) - 1.345 - 8.952 - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N2 [5] - - - CLMA_246_176/Y2 - td - 0.210 - 9.162 - r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[5]/gateop_perm/Z - - - - net (fanout=3) - 0.417 - 9.579 - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wwptr [5] - - - - td - 0.474 - 10.053 - f - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_5/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 10.053 - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [6] - - - CLMS_242_169/COUT - td - 0.058 - 10.111 - r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_7/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 10.111 - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [8] - - - CLMS_242_173/Y1 - td - 0.498 - 10.609 - r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_9/gateop_A2/Y1 - - - - net (fanout=2) - 0.416 - 11.025 - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/nb6 [9] - - - CLMA_246_180/D3 - - - - r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[9]/opit_0_L6Q_perm/B3 - -
- - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_200m (rising edge) - - 5.000 - 5.000 - r - - - - P20 - - 0.000 - 5.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 5.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 6.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 6.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 6.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 7.688 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.096 - 7.784 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.059 - 8.843 - - zoom_clk - - - USCM_84_122/CLK_USCM - td - 0.000 - 8.843 - r - USCMROUTE_2/CLKOUT - - - - net (fanout=759) - 1.531 - 10.374 - - ntR3909 - - - CLMA_246_180/CLK - - - - r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[9]/opit_0_L6Q_perm/CLK - - - clock pessimism - - 0.439 - 10.813 - - - - - clock uncertainty - - -0.150 - 10.663 - - - - - Setup time - - -0.426 - 10.237 - - - -
-
- -
- - -0.788 - 0 - 3 - u_zoom_image/mult_fra0_0/N2/gopapm/CLK - u_zoom_image/mult_image_r0_0/N2/gopapm/X[0] - - clk_200m - clk_200m - rise-rise - 0.067 - 5.867 - 5.495 - 0.439 - 5.000 - 3.462 - 1.067 (30.8%) - 2.395 (69.2%) - - Path #2: setup slack is -0.788(VIOLATED) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_200m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.101 - 3.204 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.078 - 4.282 - - zoom_clk - - - USCM_84_122/CLK_USCM - td - 0.000 - 4.282 - r - USCMROUTE_2/CLKOUT - - - - net (fanout=759) - 1.585 - 5.867 - - ntR3909 - - - APM_206_140/CLK - - - - r - u_zoom_image/mult_fra0_0/N2/gopapm/CLK - - - APM_206_140/P[31] - tco - 1.067 - 6.934 - f - u_zoom_image/mult_fra0_0/N2/gopapm/P[7] - - - - net (fanout=3) - 2.395 - 9.329 - - u_zoom_image/coe_mult_p0_0 [7] - - - APM_206_328/X[0] - - - - f - u_zoom_image/mult_image_r0_0/N2/gopapm/X[0] - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_200m (rising edge) - - 5.000 - 5.000 - r - - - - P20 - - 0.000 - 5.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 5.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 6.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 6.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 6.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 7.688 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.096 - 7.784 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.059 - 8.843 - - zoom_clk - - - USCM_84_122/CLK_USCM - td - 0.000 - 8.843 - r - USCMROUTE_2/CLKOUT - - - - net (fanout=759) - 1.652 - 10.495 - - ntR3909 - - - APM_206_328/CLK - - - - r - u_zoom_image/mult_image_r0_0/N2/gopapm/CLK - - - clock pessimism - - 0.439 - 10.934 - - - - - clock uncertainty - - -0.150 - 10.784 - - - - - Setup time - - -2.243 - 8.541 - - - -
-
-
-
- - -0.740 - 0 - 3 - u_zoom_image/mult_fra0_0/N2/gopapm/CLK - u_zoom_image/mult_image_r0_0/N2/gopapm/X[3] - - clk_200m - clk_200m - rise-rise - 0.067 - 5.867 - 5.495 - 0.439 - 5.000 - 3.414 - 1.067 (31.3%) - 2.347 (68.7%) - - Path #3: setup slack is -0.740(VIOLATED) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_200m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.101 - 3.204 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.078 - 4.282 - - zoom_clk - - - USCM_84_122/CLK_USCM - td - 0.000 - 4.282 - r - USCMROUTE_2/CLKOUT - - - - net (fanout=759) - 1.585 - 5.867 - - ntR3909 - - - APM_206_140/CLK - - - - r - u_zoom_image/mult_fra0_0/N2/gopapm/CLK - - - APM_206_140/P[34] - tco - 1.067 - 6.934 - f - u_zoom_image/mult_fra0_0/N2/gopapm/P[10] - - - - net (fanout=3) - 2.347 - 9.281 - - u_zoom_image/coe_mult_p0_0 [10] - - - APM_206_328/X[3] - - - - f - u_zoom_image/mult_image_r0_0/N2/gopapm/X[3] - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_200m (rising edge) - - 5.000 - 5.000 - r - - - - P20 - - 0.000 - 5.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 5.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 6.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 6.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 6.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 7.688 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.096 - 7.784 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.059 - 8.843 - - zoom_clk - - - USCM_84_122/CLK_USCM - td - 0.000 - 8.843 - r - USCMROUTE_2/CLKOUT - - - - net (fanout=759) - 1.652 - 10.495 - - ntR3909 - - - APM_206_328/CLK - - - - r - u_zoom_image/mult_image_r0_0/N2/gopapm/CLK - - - clock pessimism - - 0.439 - 10.934 - - - - - clock uncertainty - - -0.150 - 10.784 - - - - - Setup time - - -2.243 - 8.541 - - - -
-
-
-
- - 0.348 - 7 - 40 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[6]/opit_0_inv_L5Q_perm/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/S0 - - ddrphy_clkin - ddrphy_clkin - rise-rise - -0.054 - 11.394 - 10.665 - 0.675 - 10.000 - 9.071 - 3.183 (35.1%) - 5.888 (64.9%) - - Path #4: setup slack is 0.348(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ddrphy_clkin (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.101 - 3.204 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.078 - 4.282 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 4.282 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.738 - 6.020 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.129 - 6.149 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.121 - 7.270 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.348 - 7.618 - r - clkgate_8/gopclkgate/OUT - - - - net (fanout=1) - 0.000 - 7.618 - - ntclkgate_0 - - - IOCKDIV_6_323/CLK_IODIV - td - 0.000 - 7.618 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV - - - - net (fanout=1) - 2.191 - 9.809 - - u_axi_ddr_top/clk - - - USCM_84_116/CLK_USCM - td - 0.000 - 9.809 - r - clkbufg_0/gopclkbufg/CLKOUT - - - - net (fanout=5464) - 1.585 - 11.394 - - ntclkbufg_0 - - - CLMA_22_124/CLK - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[6]/opit_0_inv_L5Q_perm/CLK - - - CLMA_22_124/Q2 - tco - 0.289 - 11.683 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[6]/opit_0_inv_L5Q_perm/Q - - - - net (fanout=5) - 1.236 - 12.919 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mr0_ddr3 [6] - - - CLMA_30_168/Y3 - td - 0.210 - 13.129 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/gateop_perm/Z - - - - net (fanout=2) - 0.407 - 13.536 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_cl [1] - - - - td - 0.477 - 14.013 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_1/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 14.013 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.co [2] - - - CLMA_34_168/Y2 - td - 0.271 - 14.284 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_3/gateop_A2/Y0 - - - - net (fanout=1) - 0.554 - 14.838 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [2] - - - CLMA_30_160/Y3 - td - 0.210 - 15.048 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[2]/gateop_perm/Z - - - - net (fanout=4) - 0.690 - 15.738 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al [2] - - - CLMA_30_172/COUT - td - 0.502 - 16.240 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_3/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 16.240 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14576 - - - CLMA_30_176/Y0 - td - 0.269 - 16.509 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_5/gateop/Y - - - - net (fanout=4) - 1.536 - 18.045 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mc_rl [4] - - - CLMA_30_248/Y0 - td - 0.487 - 18.532 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_159_5/gateop_perm/Z - - - - net (fanout=40) - 0.995 - 19.527 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24196 - - - CLMS_38_245/Y1 - td - 0.468 - 19.995 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_170[2]/gateop/F - - - - net (fanout=1) - 0.470 - 20.465 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24359 - - - CLMS_22_245/D3 - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/S0 - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ddrphy_clkin (rising edge) - - 10.000 - 10.000 - r - - - - P20 - - 0.000 - 10.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 10.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 11.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 11.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 11.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 12.688 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.096 - 12.784 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.059 - 13.843 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 13.843 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.665 - 15.508 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.123 - 15.631 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.102 - 16.733 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.249 - 16.982 - r - clkgate_8/gopclkgate/OUT - - - - net (fanout=1) - 0.000 - 16.982 - - ntclkgate_0 - - - IOCKDIV_6_323/CLK_IODIV - td - 0.000 - 16.982 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV - - - - net (fanout=1) - 2.152 - 19.134 - - u_axi_ddr_top/clk - - - USCM_84_116/CLK_USCM - td - 0.000 - 19.134 - r - clkbufg_0/gopclkbufg/CLKOUT - - - - net (fanout=5464) - 1.531 - 20.665 - - ntclkbufg_0 - - - CLMS_22_245/CLK - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/CLK - - - clock pessimism - - 0.675 - 21.340 - - - - - clock uncertainty - - -0.150 - 21.190 - - - - - Setup time - - -0.377 - 20.813 - - - -
-
-
-
- - 0.411 - 7 - 40 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[6]/opit_0_inv_L5Q_perm/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/S0 - - ddrphy_clkin - ddrphy_clkin - rise-rise - 0.067 - 11.394 - 10.786 - 0.675 - 10.000 - 9.129 - 3.189 (34.9%) - 5.940 (65.1%) - - Path #5: setup slack is 0.411(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ddrphy_clkin (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.101 - 3.204 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.078 - 4.282 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 4.282 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.738 - 6.020 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.129 - 6.149 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.121 - 7.270 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.348 - 7.618 - r - clkgate_8/gopclkgate/OUT - - - - net (fanout=1) - 0.000 - 7.618 - - ntclkgate_0 - - - IOCKDIV_6_323/CLK_IODIV - td - 0.000 - 7.618 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV - - - - net (fanout=1) - 2.191 - 9.809 - - u_axi_ddr_top/clk - - - USCM_84_116/CLK_USCM - td - 0.000 - 9.809 - r - clkbufg_0/gopclkbufg/CLKOUT - - - - net (fanout=5464) - 1.585 - 11.394 - - ntclkbufg_0 - - - CLMA_22_124/CLK - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[6]/opit_0_inv_L5Q_perm/CLK - - - CLMA_22_124/Q2 - tco - 0.289 - 11.683 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[6]/opit_0_inv_L5Q_perm/Q - - - - net (fanout=5) - 1.236 - 12.919 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mr0_ddr3 [6] - - - CLMA_30_168/Y3 - td - 0.210 - 13.129 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/gateop_perm/Z - - - - net (fanout=2) - 0.407 - 13.536 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_cl [1] - - - - td - 0.477 - 14.013 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_1/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 14.013 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.co [2] - - - CLMA_34_168/Y2 - td - 0.271 - 14.284 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_3/gateop_A2/Y0 - - - - net (fanout=1) - 0.554 - 14.838 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [2] - - - CLMA_30_160/Y3 - td - 0.210 - 15.048 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[2]/gateop_perm/Z - - - - net (fanout=4) - 0.690 - 15.738 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al [2] - - - CLMA_30_172/COUT - td - 0.502 - 16.240 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_3/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 16.240 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14576 - - - CLMA_30_176/Y0 - td - 0.269 - 16.509 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_5/gateop/Y - - - - net (fanout=4) - 1.536 - 18.045 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mc_rl [4] - - - CLMA_30_248/Y0 - td - 0.493 - 18.538 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_159_5/gateop_perm/Z - - - - net (fanout=40) - 0.749 - 19.287 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24196 - - - CLMA_34_268/Y3 - td - 0.468 - 19.755 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_170[10]/gateop/F - - - - net (fanout=1) - 0.768 - 20.523 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24367 - - - CLMS_22_265/B3 - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/S0 - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ddrphy_clkin (rising edge) - - 10.000 - 10.000 - r - - - - P20 - - 0.000 - 10.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 10.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 11.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 11.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 11.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 12.688 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.096 - 12.784 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.059 - 13.843 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 13.843 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.665 - 15.508 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.123 - 15.631 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.102 - 16.733 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.249 - 16.982 - r - clkgate_8/gopclkgate/OUT - - - - net (fanout=1) - 0.000 - 16.982 - - ntclkgate_0 - - - IOCKDIV_6_323/CLK_IODIV - td - 0.000 - 16.982 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV - - - - net (fanout=1) - 2.152 - 19.134 - - u_axi_ddr_top/clk - - - USCM_84_116/CLK_USCM - td - 0.000 - 19.134 - r - clkbufg_0/gopclkbufg/CLKOUT - - - - net (fanout=5464) - 1.652 - 20.786 - - ntclkbufg_0 - - - CLMS_22_265/CLK - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/CLK - - - clock pessimism - - 0.675 - 21.461 - - - - - clock uncertainty - - -0.150 - 21.311 - - - - - Setup time - - -0.377 - 20.934 - - - -
-
-
-
- - 0.418 - 7 - 40 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[6]/opit_0_inv_L5Q_perm/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/S0 - - ddrphy_clkin - ddrphy_clkin - rise-rise - -0.054 - 11.394 - 10.665 - 0.675 - 10.000 - 8.981 - 3.189 (35.5%) - 5.792 (64.5%) - - Path #6: setup slack is 0.418(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ddrphy_clkin (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.101 - 3.204 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.078 - 4.282 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 4.282 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.738 - 6.020 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.129 - 6.149 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.121 - 7.270 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.348 - 7.618 - r - clkgate_8/gopclkgate/OUT - - - - net (fanout=1) - 0.000 - 7.618 - - ntclkgate_0 - - - IOCKDIV_6_323/CLK_IODIV - td - 0.000 - 7.618 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV - - - - net (fanout=1) - 2.191 - 9.809 - - u_axi_ddr_top/clk - - - USCM_84_116/CLK_USCM - td - 0.000 - 9.809 - r - clkbufg_0/gopclkbufg/CLKOUT - - - - net (fanout=5464) - 1.585 - 11.394 - - ntclkbufg_0 - - - CLMA_22_124/CLK - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[6]/opit_0_inv_L5Q_perm/CLK - - - CLMA_22_124/Q2 - tco - 0.289 - 11.683 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[6]/opit_0_inv_L5Q_perm/Q - - - - net (fanout=5) - 1.236 - 12.919 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mr0_ddr3 [6] - - - CLMA_30_168/Y3 - td - 0.210 - 13.129 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/gateop_perm/Z - - - - net (fanout=2) - 0.407 - 13.536 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_cl [1] - - - - td - 0.477 - 14.013 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_1/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 14.013 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.co [2] - - - CLMA_34_168/Y2 - td - 0.271 - 14.284 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_3/gateop_A2/Y0 - - - - net (fanout=1) - 0.554 - 14.838 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [2] - - - CLMA_30_160/Y3 - td - 0.210 - 15.048 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[2]/gateop_perm/Z - - - - net (fanout=4) - 0.690 - 15.738 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al [2] - - - CLMA_30_172/COUT - td - 0.502 - 16.240 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_3/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 16.240 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14576 - - - CLMA_30_176/Y0 - td - 0.269 - 16.509 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_5/gateop/Y - - - - net (fanout=4) - 1.536 - 18.045 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mc_rl [4] - - - CLMA_30_248/Y0 - td - 0.493 - 18.538 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_159_5/gateop_perm/Z - - - - net (fanout=40) - 0.731 - 19.269 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24196 - - - CLMA_30_248/Y1 - td - 0.468 - 19.737 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_170[0]/gateop/F - - - - net (fanout=1) - 0.638 - 20.375 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24357 - - - CLMS_22_245/A3 - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/S0 - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ddrphy_clkin (rising edge) - - 10.000 - 10.000 - r - - - - P20 - - 0.000 - 10.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 10.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 11.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 11.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 11.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 12.688 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.096 - 12.784 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.059 - 13.843 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 13.843 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.665 - 15.508 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.123 - 15.631 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.102 - 16.733 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.249 - 16.982 - r - clkgate_8/gopclkgate/OUT - - - - net (fanout=1) - 0.000 - 16.982 - - ntclkgate_0 - - - IOCKDIV_6_323/CLK_IODIV - td - 0.000 - 16.982 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV - - - - net (fanout=1) - 2.152 - 19.134 - - u_axi_ddr_top/clk - - - USCM_84_116/CLK_USCM - td - 0.000 - 19.134 - r - clkbufg_0/gopclkbufg/CLKOUT - - - - net (fanout=5464) - 1.531 - 20.665 - - ntclkbufg_0 - - - CLMS_22_245/CLK - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/CLK - - - clock pessimism - - 0.675 - 21.340 - - - - - clock uncertainty - - -0.150 - 21.190 - - - - - Setup time - - -0.397 - 20.793 - - - -
-
-
-
- - 1.077 - 7 - 18 - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/CLK - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[0]/opit_0_L5Q_perm/CE - - eth_rxc - eth_rxc - rise-rise - -0.036 - 10.030 - 8.446 - 1.548 - 8.000 - 6.020 - 2.738 (45.5%) - 3.282 (54.5%) - - Path #7: setup slack is 1.077(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock eth_rxc (rising edge) - - 0.000 - 0.000 - r - - - - F14 - - 0.000 - 0.000 - r - eth_rxc (port) - - - - net (fanout=1) - 0.057 - 0.057 - - eth_rxc - - - IOBD_240_376/DIN - td - 1.254 - 1.311 - r - eth_rxc_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.311 - - eth_rxc_ibuf/ntD - - - IOL_243_374/INCK - td - 0.076 - 1.387 - r - eth_rxc_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.647 - 2.034 - - _N66 - - - IOCKDLY_237_367/CLK_OUT - td - 3.812 - 5.846 - r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT - - - - net (fanout=1) - 2.599 - 8.445 - - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf - - - USCM_84_109/CLK_USCM - td - 0.000 - 8.445 - r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - - - - net (fanout=1861) - 1.585 - 10.030 - - gmii_clk - - - CLMA_202_140/CLK - - - - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/CLK - - - CLMA_202_140/Q2 - tco - 0.290 - 10.320 - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/Q - - - - net (fanout=2) - 0.494 - 10.814 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num [2] - - - - td - 0.474 - 11.288 - f - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_1/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 11.288 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [2] - - - CLMA_214_140/COUT - td - 0.058 - 11.346 - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_3/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 11.346 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [4] - - - - td - 0.058 - 11.404 - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_5/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 11.404 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [6] - - - CLMA_214_144/COUT - td - 0.058 - 11.462 - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_7/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 11.462 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [8] - - - - td - 0.058 - 11.520 - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_9/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 11.520 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [10] - - - CLMA_214_148/COUT - td - 0.058 - 11.578 - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_11/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 11.578 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [12] - - - CLMA_214_152/Y0 - td - 0.269 - 11.847 - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_13/gateop_A2/Y0 - - - - net (fanout=1) - 0.713 - 12.560 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276 [13] - - - CLMA_210_141/Y3 - td - 0.612 - 13.172 - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N277.eq_6/gateop_A2/Y1 - - - - net (fanout=18) - 0.777 - 13.949 - - _N79 - - - CLMS_186_153/Y2 - td - 0.487 - 14.436 - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_pkt_done/opit_0_L5Q_perm/Z - - - - net (fanout=1) - 0.502 - 14.938 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N323 - - - CLMA_194_160/Y1 - td - 0.316 - 15.254 - f - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839/gateop_perm/Z - - - - net (fanout=16) - 0.796 - 16.050 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839 - - - CLMA_214_136/CE - - - - f - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[0]/opit_0_L5Q_perm/CE - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock eth_rxc (rising edge) - - 8.000 - 8.000 - r - - - - F14 - - 0.000 - 8.000 - r - eth_rxc (port) - - - - net (fanout=1) - 0.057 - 8.057 - - eth_rxc - - - IOBD_240_376/DIN - td - 1.047 - 9.104 - r - eth_rxc_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 9.104 - - eth_rxc_ibuf/ntD - - - IOL_243_374/INCK - td - 0.048 - 9.152 - r - eth_rxc_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.636 - 9.788 - - _N66 - - - IOCKDLY_237_367/CLK_OUT - td - 2.574 - 12.362 - r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT - - - - net (fanout=1) - 2.553 - 14.915 - - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf - - - USCM_84_109/CLK_USCM - td - 0.000 - 14.915 - r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - - - - net (fanout=1861) - 1.531 - 16.446 - - gmii_clk - - - CLMA_214_136/CLK - - - - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[0]/opit_0_L5Q_perm/CLK - - - clock pessimism - - 1.548 - 17.994 - - - - - clock uncertainty - - -0.250 - 17.744 - - - - - Setup time - - -0.617 - 17.127 - - - -
-
-
-
- - 1.077 - 7 - 18 - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/CLK - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[2]/opit_0_L5Q_perm/CE - - eth_rxc - eth_rxc - rise-rise - -0.036 - 10.030 - 8.446 - 1.548 - 8.000 - 6.020 - 2.738 (45.5%) - 3.282 (54.5%) - - Path #8: setup slack is 1.077(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock eth_rxc (rising edge) - - 0.000 - 0.000 - r - - - - F14 - - 0.000 - 0.000 - r - eth_rxc (port) - - - - net (fanout=1) - 0.057 - 0.057 - - eth_rxc - - - IOBD_240_376/DIN - td - 1.254 - 1.311 - r - eth_rxc_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.311 - - eth_rxc_ibuf/ntD - - - IOL_243_374/INCK - td - 0.076 - 1.387 - r - eth_rxc_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.647 - 2.034 - - _N66 - - - IOCKDLY_237_367/CLK_OUT - td - 3.812 - 5.846 - r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT - - - - net (fanout=1) - 2.599 - 8.445 - - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf - - - USCM_84_109/CLK_USCM - td - 0.000 - 8.445 - r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - - - - net (fanout=1861) - 1.585 - 10.030 - - gmii_clk - - - CLMA_202_140/CLK - - - - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/CLK - - - CLMA_202_140/Q2 - tco - 0.290 - 10.320 - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/Q - - - - net (fanout=2) - 0.494 - 10.814 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num [2] - - - - td - 0.474 - 11.288 - f - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_1/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 11.288 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [2] - - - CLMA_214_140/COUT - td - 0.058 - 11.346 - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_3/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 11.346 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [4] - - - - td - 0.058 - 11.404 - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_5/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 11.404 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [6] - - - CLMA_214_144/COUT - td - 0.058 - 11.462 - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_7/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 11.462 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [8] - - - - td - 0.058 - 11.520 - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_9/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 11.520 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [10] - - - CLMA_214_148/COUT - td - 0.058 - 11.578 - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_11/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 11.578 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [12] - - - CLMA_214_152/Y0 - td - 0.269 - 11.847 - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_13/gateop_A2/Y0 - - - - net (fanout=1) - 0.713 - 12.560 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276 [13] - - - CLMA_210_141/Y3 - td - 0.612 - 13.172 - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N277.eq_6/gateop_A2/Y1 - - - - net (fanout=18) - 0.777 - 13.949 - - _N79 - - - CLMS_186_153/Y2 - td - 0.487 - 14.436 - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_pkt_done/opit_0_L5Q_perm/Z - - - - net (fanout=1) - 0.502 - 14.938 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N323 - - - CLMA_194_160/Y1 - td - 0.316 - 15.254 - f - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839/gateop_perm/Z - - - - net (fanout=16) - 0.796 - 16.050 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839 - - - CLMA_214_136/CE - - - - f - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[2]/opit_0_L5Q_perm/CE - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock eth_rxc (rising edge) - - 8.000 - 8.000 - r - - - - F14 - - 0.000 - 8.000 - r - eth_rxc (port) - - - - net (fanout=1) - 0.057 - 8.057 - - eth_rxc - - - IOBD_240_376/DIN - td - 1.047 - 9.104 - r - eth_rxc_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 9.104 - - eth_rxc_ibuf/ntD - - - IOL_243_374/INCK - td - 0.048 - 9.152 - r - eth_rxc_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.636 - 9.788 - - _N66 - - - IOCKDLY_237_367/CLK_OUT - td - 2.574 - 12.362 - r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT - - - - net (fanout=1) - 2.553 - 14.915 - - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf - - - USCM_84_109/CLK_USCM - td - 0.000 - 14.915 - r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - - - - net (fanout=1861) - 1.531 - 16.446 - - gmii_clk - - - CLMA_214_136/CLK - - - - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[2]/opit_0_L5Q_perm/CLK - - - clock pessimism - - 1.548 - 17.994 - - - - - clock uncertainty - - -0.250 - 17.744 - - - - - Setup time - - -0.617 - 17.127 - - - -
-
-
-
- - 1.077 - 7 - 18 - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/CLK - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[5]/opit_0_L5Q_perm/CE - - eth_rxc - eth_rxc - rise-rise - -0.036 - 10.030 - 8.446 - 1.548 - 8.000 - 6.020 - 2.738 (45.5%) - 3.282 (54.5%) - - Path #9: setup slack is 1.077(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock eth_rxc (rising edge) - - 0.000 - 0.000 - r - - - - F14 - - 0.000 - 0.000 - r - eth_rxc (port) - - - - net (fanout=1) - 0.057 - 0.057 - - eth_rxc - - - IOBD_240_376/DIN - td - 1.254 - 1.311 - r - eth_rxc_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.311 - - eth_rxc_ibuf/ntD - - - IOL_243_374/INCK - td - 0.076 - 1.387 - r - eth_rxc_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.647 - 2.034 - - _N66 - - - IOCKDLY_237_367/CLK_OUT - td - 3.812 - 5.846 - r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT - - - - net (fanout=1) - 2.599 - 8.445 - - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf - - - USCM_84_109/CLK_USCM - td - 0.000 - 8.445 - r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - - - - net (fanout=1861) - 1.585 - 10.030 - - gmii_clk - - - CLMA_202_140/CLK - - - - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/CLK - - - CLMA_202_140/Q2 - tco - 0.290 - 10.320 - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/Q - - - - net (fanout=2) - 0.494 - 10.814 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num [2] - - - - td - 0.474 - 11.288 - f - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_1/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 11.288 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [2] - - - CLMA_214_140/COUT - td - 0.058 - 11.346 - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_3/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 11.346 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [4] - - - - td - 0.058 - 11.404 - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_5/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 11.404 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [6] - - - CLMA_214_144/COUT - td - 0.058 - 11.462 - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_7/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 11.462 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [8] - - - - td - 0.058 - 11.520 - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_9/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 11.520 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [10] - - - CLMA_214_148/COUT - td - 0.058 - 11.578 - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_11/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 11.578 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [12] - - - CLMA_214_152/Y0 - td - 0.269 - 11.847 - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_13/gateop_A2/Y0 - - - - net (fanout=1) - 0.713 - 12.560 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276 [13] - - - CLMA_210_141/Y3 - td - 0.612 - 13.172 - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N277.eq_6/gateop_A2/Y1 - - - - net (fanout=18) - 0.777 - 13.949 - - _N79 - - - CLMS_186_153/Y2 - td - 0.487 - 14.436 - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_pkt_done/opit_0_L5Q_perm/Z - - - - net (fanout=1) - 0.502 - 14.938 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N323 - - - CLMA_194_160/Y1 - td - 0.316 - 15.254 - f - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839/gateop_perm/Z - - - - net (fanout=16) - 0.796 - 16.050 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839 - - - CLMA_214_136/CE - - - - f - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[5]/opit_0_L5Q_perm/CE - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock eth_rxc (rising edge) - - 8.000 - 8.000 - r - - - - F14 - - 0.000 - 8.000 - r - eth_rxc (port) - - - - net (fanout=1) - 0.057 - 8.057 - - eth_rxc - - - IOBD_240_376/DIN - td - 1.047 - 9.104 - r - eth_rxc_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 9.104 - - eth_rxc_ibuf/ntD - - - IOL_243_374/INCK - td - 0.048 - 9.152 - r - eth_rxc_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.636 - 9.788 - - _N66 - - - IOCKDLY_237_367/CLK_OUT - td - 2.574 - 12.362 - r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT - - - - net (fanout=1) - 2.553 - 14.915 - - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf - - - USCM_84_109/CLK_USCM - td - 0.000 - 14.915 - r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - - - - net (fanout=1861) - 1.531 - 16.446 - - gmii_clk - - - CLMA_214_136/CLK - - - - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[5]/opit_0_L5Q_perm/CLK - - - clock pessimism - - 1.548 - 17.994 - - - - - clock uncertainty - - -0.250 - 17.744 - - - - - Setup time - - -0.617 - 17.127 - - - -
-
-
-
- - 1.130 - 4 - 4 - u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L4 - - hdmi_in_clk - hdmi_in_clk - rise-rise - -0.036 - 6.435 - 5.951 - 0.448 - 6.666 - 5.127 - 2.593 (50.6%) - 2.534 (49.4%) - - Path #10: setup slack is 1.130(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock hdmi_in_clk (rising edge) - - 0.000 - 0.000 - r - - - - AA12 - - 0.000 - 0.000 - r - hdmi_in_clk (port) - - - - net (fanout=1) - 0.078 - 0.078 - - hdmi_in_clk - - - IOBD_161_0/DIN - td - 2.166 - 2.244 - r - hdmi_in_clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.244 - - hdmi_in_clk_ibuf/ntD - - - IOL_163_6/INCK - td - 0.076 - 2.320 - r - hdmi_in_clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 2.530 - 4.850 - - _N37 - - - USCM_84_111/CLK_USCM - td - 0.000 - 4.850 - r - clkbufg_4/gopclkbufg/CLKOUT - - - - net (fanout=167) - 1.585 - 6.435 - - ntclkbufg_4 - - - CLMA_146_68/CLK - - - - r - u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK - - - CLMA_146_68/Q0 - tco - 0.287 - 6.722 - f - u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/Q - - - - net (fanout=4) - 1.542 - 8.264 - - wr1_data_in_valid - - - - td - 0.288 - 8.552 - f - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Cout - - - - net (fanout=1) - 0.000 - 8.552 - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16001 - - - CLMA_70_96/Y3 - td - 0.501 - 9.053 - r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/Y1 - - - - net (fanout=3) - 0.417 - 9.470 - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2 [3] - - - CLMA_66_88/Y2 - td - 0.487 - 9.957 - r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm/Z - - - - net (fanout=1) - 0.455 - 10.412 - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wwptr [3] - - - - td - 0.474 - 10.886 - f - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_0/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 10.886 - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.co [2] - - - CLMA_66_100/COUT - td - 0.058 - 10.944 - r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_2/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 10.944 - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.co [6] - - - CLMA_66_104/Y1 - td - 0.498 - 11.442 - r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_4/gateop_A2/Y1 - - - - net (fanout=1) - 0.120 - 11.562 - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158 - - - CLMA_66_104/C4 - - - - r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L4 - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock hdmi_in_clk (rising edge) - - 6.666 - 6.666 - r - - - - AA12 - - 0.000 - 6.666 - r - hdmi_in_clk (port) - - - - net (fanout=1) - 0.078 - 6.744 - - hdmi_in_clk - - - IOBD_161_0/DIN - td - 1.808 - 8.552 - r - hdmi_in_clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 8.552 - - hdmi_in_clk_ibuf/ntD - - - IOL_163_6/INCK - td - 0.048 - 8.600 - r - hdmi_in_clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 2.486 - 11.086 - - _N37 - - - USCM_84_111/CLK_USCM - td - 0.000 - 11.086 - r - clkbufg_4/gopclkbufg/CLKOUT - - - - net (fanout=167) - 1.531 - 12.617 - - ntclkbufg_4 - - - CLMA_66_104/CLK - - - - r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK - - - clock pessimism - - 0.448 - 13.065 - - - - - clock uncertainty - - -0.250 - 12.815 - - - - - Setup time - - -0.123 - 12.692 - - - -
-
-
-
- - 1.692 - 0 - 8 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[0] - - ioclk1 - ioclk1 - rise-rise - 0.006 - 7.692 - 7.062 - 0.636 - 2.500 - 0.528 - 0.528 (100.0%) - 0.000 (0.0%) - - Path #11: setup slack is 1.692(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ioclk1 (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.101 - 3.204 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.078 - 4.282 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 4.282 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.738 - 6.020 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.129 - 6.149 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.121 - 7.270 - - clkout0_wl_0 - - - IOCKGATE_6_188/OUT - td - 0.348 - 7.618 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT - - - - net (fanout=28) - 0.074 - 7.692 - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] - - - DQSL_6_152/CLK_IO - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - - - DQSL_6_152/IFIFO_RADDR[0] - tco - 0.528 - 8.220 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[0] - - - - net (fanout=8) - 0.000 - 8.220 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [0] - - - IOL_7_162/IFIFO_RADDR[0] - - - - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[0] - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ioclk1 (rising edge) - - 2.500 - 2.500 - r - - - - P20 - - 0.000 - 2.500 - r - clk (port) - - - - net (fanout=1) - 0.074 - 2.574 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 4.382 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 4.382 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 4.430 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 5.188 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.096 - 5.284 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.059 - 6.343 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 6.343 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.665 - 8.008 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.123 - 8.131 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.102 - 9.233 - - clkout0_wl_0 - - - IOCKGATE_6_188/OUT - td - 0.249 - 9.482 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT - - - - net (fanout=28) - 0.080 - 9.562 - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] - - - IOL_7_162/CLK_IO - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK - - - clock pessimism - - 0.636 - 10.198 - - - - - clock uncertainty - - -0.150 - 10.048 - - - - - Setup time - - -0.136 - 9.912 - - - -
-
-
-
- - 1.692 - 0 - 8 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[1] - - ioclk1 - ioclk1 - rise-rise - 0.006 - 7.692 - 7.062 - 0.636 - 2.500 - 0.528 - 0.528 (100.0%) - 0.000 (0.0%) - - Path #12: setup slack is 1.692(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ioclk1 (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.101 - 3.204 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.078 - 4.282 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 4.282 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.738 - 6.020 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.129 - 6.149 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.121 - 7.270 - - clkout0_wl_0 - - - IOCKGATE_6_188/OUT - td - 0.348 - 7.618 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT - - - - net (fanout=28) - 0.074 - 7.692 - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] - - - DQSL_6_152/CLK_IO - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - - - DQSL_6_152/IFIFO_RADDR[1] - tco - 0.528 - 8.220 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[1] - - - - net (fanout=8) - 0.000 - 8.220 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [1] - - - IOL_7_162/IFIFO_RADDR[1] - - - - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[1] - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ioclk1 (rising edge) - - 2.500 - 2.500 - r - - - - P20 - - 0.000 - 2.500 - r - clk (port) - - - - net (fanout=1) - 0.074 - 2.574 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 4.382 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 4.382 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 4.430 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 5.188 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.096 - 5.284 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.059 - 6.343 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 6.343 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.665 - 8.008 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.123 - 8.131 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.102 - 9.233 - - clkout0_wl_0 - - - IOCKGATE_6_188/OUT - td - 0.249 - 9.482 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT - - - - net (fanout=28) - 0.080 - 9.562 - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] - - - IOL_7_162/CLK_IO - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK - - - clock pessimism - - 0.636 - 10.198 - - - - - clock uncertainty - - -0.150 - 10.048 - - - - - Setup time - - -0.136 - 9.912 - - - -
-
-
-
- - 1.692 - 0 - 8 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[2] - - ioclk1 - ioclk1 - rise-rise - 0.006 - 7.692 - 7.062 - 0.636 - 2.500 - 0.528 - 0.528 (100.0%) - 0.000 (0.0%) - - Path #13: setup slack is 1.692(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ioclk1 (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.101 - 3.204 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.078 - 4.282 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 4.282 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.738 - 6.020 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.129 - 6.149 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.121 - 7.270 - - clkout0_wl_0 - - - IOCKGATE_6_188/OUT - td - 0.348 - 7.618 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT - - - - net (fanout=28) - 0.074 - 7.692 - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] - - - DQSL_6_152/CLK_IO - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - - - DQSL_6_152/IFIFO_RADDR[2] - tco - 0.528 - 8.220 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[2] - - - - net (fanout=8) - 0.000 - 8.220 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [2] - - - IOL_7_162/IFIFO_RADDR[2] - - - - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[2] - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ioclk1 (rising edge) - - 2.500 - 2.500 - r - - - - P20 - - 0.000 - 2.500 - r - clk (port) - - - - net (fanout=1) - 0.074 - 2.574 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 4.382 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 4.382 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 4.430 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 5.188 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.096 - 5.284 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.059 - 6.343 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 6.343 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.665 - 8.008 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.123 - 8.131 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.102 - 9.233 - - clkout0_wl_0 - - - IOCKGATE_6_188/OUT - td - 0.249 - 9.482 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT - - - - net (fanout=28) - 0.080 - 9.562 - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] - - - IOL_7_162/CLK_IO - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK - - - clock pessimism - - 0.636 - 10.198 - - - - - clock uncertainty - - -0.150 - 10.048 - - - - - Setup time - - -0.136 - 9.912 - - - -
-
-
-
- - 1.692 - 0 - 8 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[0] - - ioclk0 - ioclk0 - rise-rise - 0.006 - 7.692 - 7.062 - 0.636 - 2.500 - 0.528 - 0.528 (100.0%) - 0.000 (0.0%) - - Path #14: setup slack is 1.692(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ioclk0 (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.101 - 3.204 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.078 - 4.282 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 4.282 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.738 - 6.020 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.129 - 6.149 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.121 - 7.270 - - clkout0_wl_0 - - - IOCKGATE_6_312/OUT - td - 0.348 - 7.618 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT - - - - net (fanout=11) - 0.074 - 7.692 - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] - - - DQSL_6_276/CLK_IO - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - - - DQSL_6_276/IFIFO_RADDR[0] - tco - 0.528 - 8.220 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[0] - - - - net (fanout=8) - 0.000 - 8.220 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [0] - - - IOL_7_285/IFIFO_RADDR[0] - - - - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[0] - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ioclk0 (rising edge) - - 2.500 - 2.500 - r - - - - P20 - - 0.000 - 2.500 - r - clk (port) - - - - net (fanout=1) - 0.074 - 2.574 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 4.382 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 4.382 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 4.430 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 5.188 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.096 - 5.284 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.059 - 6.343 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 6.343 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.665 - 8.008 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.123 - 8.131 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.102 - 9.233 - - clkout0_wl_0 - - - IOCKGATE_6_312/OUT - td - 0.249 - 9.482 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT - - - - net (fanout=11) - 0.080 - 9.562 - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] - - - IOL_7_285/CLK_IO - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK - - - clock pessimism - - 0.636 - 10.198 - - - - - clock uncertainty - - -0.150 - 10.048 - - - - - Setup time - - -0.136 - 9.912 - - - -
-
-
-
- - 1.692 - 0 - 8 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[1] - - ioclk0 - ioclk0 - rise-rise - 0.006 - 7.692 - 7.062 - 0.636 - 2.500 - 0.528 - 0.528 (100.0%) - 0.000 (0.0%) - - Path #15: setup slack is 1.692(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ioclk0 (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.101 - 3.204 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.078 - 4.282 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 4.282 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.738 - 6.020 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.129 - 6.149 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.121 - 7.270 - - clkout0_wl_0 - - - IOCKGATE_6_312/OUT - td - 0.348 - 7.618 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT - - - - net (fanout=11) - 0.074 - 7.692 - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] - - - DQSL_6_276/CLK_IO - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - - - DQSL_6_276/IFIFO_RADDR[1] - tco - 0.528 - 8.220 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[1] - - - - net (fanout=8) - 0.000 - 8.220 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [1] - - - IOL_7_285/IFIFO_RADDR[1] - - - - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[1] - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ioclk0 (rising edge) - - 2.500 - 2.500 - r - - - - P20 - - 0.000 - 2.500 - r - clk (port) - - - - net (fanout=1) - 0.074 - 2.574 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 4.382 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 4.382 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 4.430 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 5.188 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.096 - 5.284 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.059 - 6.343 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 6.343 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.665 - 8.008 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.123 - 8.131 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.102 - 9.233 - - clkout0_wl_0 - - - IOCKGATE_6_312/OUT - td - 0.249 - 9.482 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT - - - - net (fanout=11) - 0.080 - 9.562 - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] - - - IOL_7_285/CLK_IO - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK - - - clock pessimism - - 0.636 - 10.198 - - - - - clock uncertainty - - -0.150 - 10.048 - - - - - Setup time - - -0.136 - 9.912 - - - -
-
-
-
- - 1.692 - 0 - 8 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[2] - - ioclk0 - ioclk0 - rise-rise - 0.006 - 7.692 - 7.062 - 0.636 - 2.500 - 0.528 - 0.528 (100.0%) - 0.000 (0.0%) - - Path #16: setup slack is 1.692(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ioclk0 (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.101 - 3.204 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.078 - 4.282 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 4.282 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.738 - 6.020 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.129 - 6.149 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.121 - 7.270 - - clkout0_wl_0 - - - IOCKGATE_6_312/OUT - td - 0.348 - 7.618 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT - - - - net (fanout=11) - 0.074 - 7.692 - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] - - - DQSL_6_276/CLK_IO - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - - - DQSL_6_276/IFIFO_RADDR[2] - tco - 0.528 - 8.220 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[2] - - - - net (fanout=8) - 0.000 - 8.220 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [2] - - - IOL_7_285/IFIFO_RADDR[2] - - - - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[2] - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ioclk0 (rising edge) - - 2.500 - 2.500 - r - - - - P20 - - 0.000 - 2.500 - r - clk (port) - - - - net (fanout=1) - 0.074 - 2.574 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 4.382 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 4.382 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 4.430 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 5.188 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.096 - 5.284 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.059 - 6.343 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 6.343 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.665 - 8.008 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.123 - 8.131 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.102 - 9.233 - - clkout0_wl_0 - - - IOCKGATE_6_312/OUT - td - 0.249 - 9.482 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT - - - - net (fanout=11) - 0.080 - 9.562 - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] - - - IOL_7_285/CLK_IO - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK - - - clock pessimism - - 0.636 - 10.198 - - - - - clock uncertainty - - -0.150 - 10.048 - - - - - Setup time - - -0.136 - 9.912 - - - -
-
-
-
- - 2.921 - 3 - 4 - u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L0 - - hdmi_in_clk - hdmi_in_clk - rise-rise - -0.036 - 6.435 - 5.951 - 0.448 - 6.666 - 3.263 - 1.308 (40.1%) - 1.955 (59.9%) - - Path #17: setup slack is 2.921(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock hdmi_in_clk (rising edge) - - 0.000 - 0.000 - r - - - - AA12 - - 0.000 - 0.000 - r - hdmi_in_clk (port) - - - - net (fanout=1) - 0.078 - 0.078 - - hdmi_in_clk - - - IOBD_161_0/DIN - td - 2.166 - 2.244 - r - hdmi_in_clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.244 - - hdmi_in_clk_ibuf/ntD - - - IOL_163_6/INCK - td - 0.076 - 2.320 - r - hdmi_in_clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 2.530 - 4.850 - - _N37 - - - USCM_84_111/CLK_USCM - td - 0.000 - 4.850 - r - clkbufg_4/gopclkbufg/CLKOUT - - - - net (fanout=167) - 1.585 - 6.435 - - ntclkbufg_4 - - - CLMA_146_68/CLK - - - - r - u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK - - - CLMA_146_68/Q0 - tco - 0.287 - 6.722 - f - u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/Q - - - - net (fanout=4) - 1.542 - 8.264 - - wr1_data_in_valid - - - - td - 0.288 - 8.552 - f - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Cout - - - - net (fanout=1) - 0.000 - 8.552 - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16001 - - - CLMA_70_96/COUT - td - 0.058 - 8.610 - r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/Cout - - - - net (fanout=1) - 0.000 - 8.610 - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16003 - - - - td - 0.058 - 8.668 - r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/Cout - - - - net (fanout=1) - 0.000 - 8.668 - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16005 - - - CLMA_70_100/COUT - td - 0.058 - 8.726 - r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/Cout - - - - net (fanout=1) - 0.000 - 8.726 - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16007 - - - - td - 0.058 - 8.784 - r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/Cout - - - - net (fanout=1) - 0.000 - 8.784 - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16009 - - - CLMA_70_104/Y3 - td - 0.501 - 9.285 - r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_A2Q21/Y1 - - - - net (fanout=3) - 0.413 - 9.698 - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2 [11] - - - CLMA_66_104/C0 - - - - r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L0 - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock hdmi_in_clk (rising edge) - - 6.666 - 6.666 - r - - - - AA12 - - 0.000 - 6.666 - r - hdmi_in_clk (port) - - - - net (fanout=1) - 0.078 - 6.744 - - hdmi_in_clk - - - IOBD_161_0/DIN - td - 1.808 - 8.552 - r - hdmi_in_clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 8.552 - - hdmi_in_clk_ibuf/ntD - - - IOL_163_6/INCK - td - 0.048 - 8.600 - r - hdmi_in_clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 2.486 - 11.086 - - _N37 - - - USCM_84_111/CLK_USCM - td - 0.000 - 11.086 - r - clkbufg_4/gopclkbufg/CLKOUT - - - - net (fanout=167) - 1.531 - 12.617 - - ntclkbufg_4 - - - CLMA_66_104/CLK - - - - r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK - - - clock pessimism - - 0.448 - 13.065 - - - - - clock uncertainty - - -0.250 - 12.815 - - - - - Setup time - - -0.196 - 12.619 - - - -
-
-
-
- - 2.994 - 3 - 4 - u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm/L4 - - hdmi_in_clk - hdmi_in_clk - rise-rise - -0.036 - 6.435 - 5.951 - 0.448 - 6.666 - 3.263 - 1.308 (40.1%) - 1.955 (59.9%) - - Path #18: setup slack is 2.994(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock hdmi_in_clk (rising edge) - - 0.000 - 0.000 - r - - - - AA12 - - 0.000 - 0.000 - r - hdmi_in_clk (port) - - - - net (fanout=1) - 0.078 - 0.078 - - hdmi_in_clk - - - IOBD_161_0/DIN - td - 2.166 - 2.244 - r - hdmi_in_clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.244 - - hdmi_in_clk_ibuf/ntD - - - IOL_163_6/INCK - td - 0.076 - 2.320 - r - hdmi_in_clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 2.530 - 4.850 - - _N37 - - - USCM_84_111/CLK_USCM - td - 0.000 - 4.850 - r - clkbufg_4/gopclkbufg/CLKOUT - - - - net (fanout=167) - 1.585 - 6.435 - - ntclkbufg_4 - - - CLMA_146_68/CLK - - - - r - u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK - - - CLMA_146_68/Q0 - tco - 0.287 - 6.722 - f - u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/Q - - - - net (fanout=4) - 1.542 - 8.264 - - wr1_data_in_valid - - - - td - 0.288 - 8.552 - f - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Cout - - - - net (fanout=1) - 0.000 - 8.552 - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16001 - - - CLMA_70_96/COUT - td - 0.058 - 8.610 - r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/Cout - - - - net (fanout=1) - 0.000 - 8.610 - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16003 - - - - td - 0.058 - 8.668 - r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/Cout - - - - net (fanout=1) - 0.000 - 8.668 - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16005 - - - CLMA_70_100/COUT - td - 0.058 - 8.726 - r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/Cout - - - - net (fanout=1) - 0.000 - 8.726 - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16007 - - - - td - 0.058 - 8.784 - r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/Cout - - - - net (fanout=1) - 0.000 - 8.784 - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16009 - - - CLMA_70_104/Y3 - td - 0.501 - 9.285 - r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_A2Q21/Y1 - - - - net (fanout=3) - 0.413 - 9.698 - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2 [11] - - - CLMS_66_105/C4 - - - - r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm/L4 - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock hdmi_in_clk (rising edge) - - 6.666 - 6.666 - r - - - - AA12 - - 0.000 - 6.666 - r - hdmi_in_clk (port) - - - - net (fanout=1) - 0.078 - 6.744 - - hdmi_in_clk - - - IOBD_161_0/DIN - td - 1.808 - 8.552 - r - hdmi_in_clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 8.552 - - hdmi_in_clk_ibuf/ntD - - - IOL_163_6/INCK - td - 0.048 - 8.600 - r - hdmi_in_clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 2.486 - 11.086 - - _N37 - - - USCM_84_111/CLK_USCM - td - 0.000 - 11.086 - r - clkbufg_4/gopclkbufg/CLKOUT - - - - net (fanout=167) - 1.531 - 12.617 - - ntclkbufg_4 - - - CLMS_66_105/CLK - - - - r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm/CLK - - - clock pessimism - - 0.448 - 13.065 - - - - - clock uncertainty - - -0.250 - 12.815 - - - - - Setup time - - -0.123 - 12.692 - - - -
-
-
-
- - 4.291 - 2 - 1 - cmos2_data[7] - u_ov5640/cmos2_d_d0[7]/opit_0/D - - cmos2_pclk - cmos2_pclk - rise-rise - 5.551 - 0.000 - 5.551 - 0.000 - 11.900 - 11.831 - 2.292 (19.4%) - 9.539 (80.6%) - - Path #19: setup slack is 4.291(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock cmos2_pclk (rising edge) - - 0.000 - 0.000 - r - - - - Input external delay - - 1.000 - 1.000 - r - - - - AB9 - - 0.000 - 1.000 - r - cmos2_data[7] (port) - - - - net (fanout=1) - 0.080 - 1.080 - - cmos2_data[7] - - - IOBS_TB_128_0/DIN - td - 2.166 - 3.246 - r - cmos2_data_ibuf[7]/opit_0/O - - - - net (fanout=1) - 0.000 - 3.246 - - cmos2_data_ibuf[7]/ntD - - - IOL_131_5/RX_DATA_DD - td - 0.126 - 3.372 - r - cmos2_data_ibuf[7]/opit_1/OUT - - - - net (fanout=1) - 9.459 - 12.831 - - nt_cmos2_data[7] - - - CLMS_130_37/M2 - - - - r - u_ov5640/cmos2_d_d0[7]/opit_0/D - -
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- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock cmos2_pclk (rising edge) - - 11.900 - 11.900 - r - - - - W6 - - 0.000 - 11.900 - r - cmos2_pclk (port) - - - - net (fanout=1) - 0.071 - 11.971 - - cmos2_pclk - - - IOBD_37_0/DIN - td - 1.047 - 13.018 - r - cmos2_pclk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 13.018 - - cmos2_pclk_ibuf/ntD - - - IOL_39_6/RX_DATA_DD - td - 0.082 - 13.100 - r - cmos2_pclk_ibuf/opit_1/OUT - - - - net (fanout=1) - 2.820 - 15.920 - - nt_cmos2_pclk - - - USCM_84_118/CLK_USCM - td - 0.000 - 15.920 - r - clkbufg_6/gopclkbufg/CLKOUT - - - - net (fanout=118) - 1.531 - 17.451 - - ntclkbufg_6 - - - CLMS_130_37/CLK - - - - r - u_ov5640/cmos2_d_d0[7]/opit_0/CLK - - - clock pessimism - - 0.000 - 17.451 - - - - - clock uncertainty - - -0.250 - 17.201 - - - - - Setup time - - -0.079 - 17.122 - - - -
-
-
-
- - 4.870 - 2 - 1 - cmos2_data[2] - u_ov5640/cmos2_d_d0[2]/opit_0/D - - cmos2_pclk - cmos2_pclk - rise-rise - 5.551 - 0.000 - 5.551 - 0.000 - 11.900 - 11.252 - 2.292 (20.4%) - 8.960 (79.6%) - - Path #20: setup slack is 4.870(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock cmos2_pclk (rising edge) - - 0.000 - 0.000 - r - - - - Input external delay - - 1.000 - 1.000 - r - - - - T8 - - 0.000 - 1.000 - r - cmos2_data[2] (port) - - - - net (fanout=1) - 0.057 - 1.057 - - cmos2_data[2] - - - IOBD_61_0/DIN - td - 2.166 - 3.223 - r - cmos2_data_ibuf[2]/opit_0/O - - - - net (fanout=1) - 0.000 - 3.223 - - cmos2_data_ibuf[2]/ntD - - - IOL_63_6/RX_DATA_DD - td - 0.126 - 3.349 - r - cmos2_data_ibuf[2]/opit_1/OUT - - - - net (fanout=1) - 8.903 - 12.252 - - nt_cmos2_data[2] - - - CLMA_134_40/M3 - - - - r - u_ov5640/cmos2_d_d0[2]/opit_0/D - -
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- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock cmos2_pclk (rising edge) - - 11.900 - 11.900 - r - - - - W6 - - 0.000 - 11.900 - r - cmos2_pclk (port) - - - - net (fanout=1) - 0.071 - 11.971 - - cmos2_pclk - - - IOBD_37_0/DIN - td - 1.047 - 13.018 - r - cmos2_pclk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 13.018 - - cmos2_pclk_ibuf/ntD - - - IOL_39_6/RX_DATA_DD - td - 0.082 - 13.100 - r - cmos2_pclk_ibuf/opit_1/OUT - - - - net (fanout=1) - 2.820 - 15.920 - - nt_cmos2_pclk - - - USCM_84_118/CLK_USCM - td - 0.000 - 15.920 - r - clkbufg_6/gopclkbufg/CLKOUT - - - - net (fanout=118) - 1.531 - 17.451 - - ntclkbufg_6 - - - CLMA_134_40/CLK - - - - r - u_ov5640/cmos2_d_d0[2]/opit_0/CLK - - - clock pessimism - - 0.000 - 17.451 - - - - - clock uncertainty - - -0.250 - 17.201 - - - - - Setup time - - -0.079 - 17.122 - - - -
-
-
-
- - 4.900 - 2 - 1 - cmos2_data[5] - u_ov5640/cmos2_d_d0[5]/opit_0/D - - cmos2_pclk - cmos2_pclk - rise-rise - 5.551 - 0.000 - 5.551 - 0.000 - 11.900 - 11.213 - 1.640 (14.6%) - 9.573 (85.4%) - - Path #21: setup slack is 4.900(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock cmos2_pclk (rising edge) - - 0.000 - 0.000 - r - - - - Input external delay - - 1.000 - 1.000 - f - - - - AB8 - - 0.000 - 1.000 - f - cmos2_data[5] (port) - - - - net (fanout=1) - 0.084 - 1.084 - - cmos2_data[5] - - - IOBS_TB_116_0/DIN - td - 1.513 - 2.597 - f - cmos2_data_ibuf[5]/opit_0/O - - - - net (fanout=1) - 0.000 - 2.597 - - cmos2_data_ibuf[5]/ntD - - - IOL_119_5/RX_DATA_DD - td - 0.127 - 2.724 - f - cmos2_data_ibuf[5]/opit_1/OUT - - - - net (fanout=1) - 9.489 - 12.213 - - nt_cmos2_data[5] - - - CLMA_134_40/M0 - - - - f - u_ov5640/cmos2_d_d0[5]/opit_0/D - -
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- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock cmos2_pclk (rising edge) - - 11.900 - 11.900 - r - - - - W6 - - 0.000 - 11.900 - r - cmos2_pclk (port) - - - - net (fanout=1) - 0.071 - 11.971 - - cmos2_pclk - - - IOBD_37_0/DIN - td - 1.047 - 13.018 - r - cmos2_pclk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 13.018 - - cmos2_pclk_ibuf/ntD - - - IOL_39_6/RX_DATA_DD - td - 0.082 - 13.100 - r - cmos2_pclk_ibuf/opit_1/OUT - - - - net (fanout=1) - 2.820 - 15.920 - - nt_cmos2_pclk - - - USCM_84_118/CLK_USCM - td - 0.000 - 15.920 - r - clkbufg_6/gopclkbufg/CLKOUT - - - - net (fanout=118) - 1.531 - 17.451 - - ntclkbufg_6 - - - CLMA_134_40/CLK - - - - r - u_ov5640/cmos2_d_d0[5]/opit_0/CLK - - - clock pessimism - - 0.000 - 17.451 - - - - - clock uncertainty - - -0.250 - 17.201 - - - - - Setup time - - -0.088 - 17.113 - - - -
-
-
-
- - 5.450 - 9 - 6 - u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK - udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[0]/opit_0_L5Q_perm/CE - - clk_720p60Hz - clk_720p60Hz - rise-rise - -0.036 - 9.434 - 8.831 - 0.567 - 13.473 - 7.090 - 2.943 (41.5%) - 4.147 (58.5%) - - Path #22: setup slack is 5.450(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_720p60Hz (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.107 - 3.210 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.078 - 4.288 - - rd3_clk - - - USCM_84_154/CLK_USCM - td - 0.000 - 4.288 - r - USCMROUTE_0/CLKOUT - - - - net (fanout=1) - 1.861 - 6.149 - - ntR3907 - - - PLL_158_303/CLK_OUT1 - td - 0.101 - 6.250 - r - U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.599 - 7.849 - - nt_pix_clk - - - USCM_84_117/CLK_USCM - td - 0.000 - 7.849 - r - clkbufg_2/gopclkbufg/CLKOUT - - - - net (fanout=1635) - 1.585 - 9.434 - - ntclkbufg_2 - - - CLMS_186_117/CLK - - - - r - u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK - - - CLMS_186_117/Q2 - tco - 0.290 - 9.724 - r - u_sync_vg/pos_y[8]/opit_0_A2Q21/Q0 - - - - net (fanout=1) - 0.857 - 10.581 - - pos_y[7] - - - CLMA_186_116/COUT - td - 0.515 - 11.096 - r - udp_osd_inst/N29.eq_2/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 11.096 - - udp_osd_inst/N29.co [6] - - - CLMA_186_120/Y1 - td - 0.498 - 11.594 - r - udp_osd_inst/N29.eq_4/gateop_A2/Y1 - - - - net (fanout=5) - 0.410 - 12.004 - - udp_osd_inst/N29 - - - CLMA_190_120/Y3 - td - 0.287 - 12.291 - r - udp_osd_inst/N69_5/gateop_perm/Z - - - - net (fanout=2) - 0.551 - 12.842 - - udp_osd_inst/char_osd_inst/pixels_shifter_inst/N64 - - - CLMA_186_112/Y1 - td - 0.212 - 13.054 - r - udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/gateop_perm/Z - - - - net (fanout=2) - 0.401 - 13.455 - - udp_osd_inst/char_osd_inst/row_pixels_ready - - - CLMA_186_108/Y2 - td - 0.210 - 13.665 - r - udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/gateop_perm/Z - - - - net (fanout=6) - 0.587 - 14.252 - - udp_osd_inst/char_osd_inst/char_next - - - CLMA_182_88/Y3 - td - 0.210 - 14.462 - r - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N79/gateop_perm/Z - - - - net (fanout=1) - 0.253 - 14.715 - - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N79 - - - CLMA_182_88/Y2 - td - 0.210 - 14.925 - r - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N358_5/gateop_perm/Z - - - - net (fanout=3) - 0.548 - 15.473 - - udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N96518 - - - CLMA_186_80/Y0 - td - 0.341 - 15.814 - f - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786/gateop_perm/Z - - - - net (fanout=1) - 0.540 - 16.354 - - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786 - - - CLMA_182_73/CECO - td - 0.170 - 16.524 - f - udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[4]/opit_0_A2Q21/CEOUT - - - - net (fanout=4) - 0.000 - 16.524 - - ntR2038 - - - CLMA_182_77/CECI - - - - f - udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[0]/opit_0_L5Q_perm/CE - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_720p60Hz (rising edge) - - 13.473 - 13.473 - r - - - - P20 - - 0.000 - 13.473 - r - clk (port) - - - - net (fanout=1) - 0.074 - 13.547 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 15.355 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 15.355 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 15.403 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 16.161 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.100 - 16.261 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.059 - 17.320 - - rd3_clk - - - USCM_84_154/CLK_USCM - td - 0.000 - 17.320 - r - USCMROUTE_0/CLKOUT - - - - net (fanout=1) - 1.786 - 19.106 - - ntR3907 - - - PLL_158_303/CLK_OUT1 - td - 0.096 - 19.202 - r - U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.571 - 20.773 - - nt_pix_clk - - - USCM_84_117/CLK_USCM - td - 0.000 - 20.773 - r - clkbufg_2/gopclkbufg/CLKOUT - - - - net (fanout=1635) - 1.531 - 22.304 - - ntclkbufg_2 - - - CLMA_182_77/CLK - - - - r - udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[0]/opit_0_L5Q_perm/CLK - - - clock pessimism - - 0.567 - 22.871 - - - - - clock uncertainty - - -0.150 - 22.721 - - - - - Setup time - - -0.747 - 21.974 - - - -
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-
-
- - 5.450 - 9 - 6 - u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK - udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[1]/opit_0_L5Q_perm/CE - - clk_720p60Hz - clk_720p60Hz - rise-rise - -0.036 - 9.434 - 8.831 - 0.567 - 13.473 - 7.090 - 2.943 (41.5%) - 4.147 (58.5%) - - Path #23: setup slack is 5.450(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_720p60Hz (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.107 - 3.210 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.078 - 4.288 - - rd3_clk - - - USCM_84_154/CLK_USCM - td - 0.000 - 4.288 - r - USCMROUTE_0/CLKOUT - - - - net (fanout=1) - 1.861 - 6.149 - - ntR3907 - - - PLL_158_303/CLK_OUT1 - td - 0.101 - 6.250 - r - U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.599 - 7.849 - - nt_pix_clk - - - USCM_84_117/CLK_USCM - td - 0.000 - 7.849 - r - clkbufg_2/gopclkbufg/CLKOUT - - - - net (fanout=1635) - 1.585 - 9.434 - - ntclkbufg_2 - - - CLMS_186_117/CLK - - - - r - u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK - - - CLMS_186_117/Q2 - tco - 0.290 - 9.724 - r - u_sync_vg/pos_y[8]/opit_0_A2Q21/Q0 - - - - net (fanout=1) - 0.857 - 10.581 - - pos_y[7] - - - CLMA_186_116/COUT - td - 0.515 - 11.096 - r - udp_osd_inst/N29.eq_2/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 11.096 - - udp_osd_inst/N29.co [6] - - - CLMA_186_120/Y1 - td - 0.498 - 11.594 - r - udp_osd_inst/N29.eq_4/gateop_A2/Y1 - - - - net (fanout=5) - 0.410 - 12.004 - - udp_osd_inst/N29 - - - CLMA_190_120/Y3 - td - 0.287 - 12.291 - r - udp_osd_inst/N69_5/gateop_perm/Z - - - - net (fanout=2) - 0.551 - 12.842 - - udp_osd_inst/char_osd_inst/pixels_shifter_inst/N64 - - - CLMA_186_112/Y1 - td - 0.212 - 13.054 - r - udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/gateop_perm/Z - - - - net (fanout=2) - 0.401 - 13.455 - - udp_osd_inst/char_osd_inst/row_pixels_ready - - - CLMA_186_108/Y2 - td - 0.210 - 13.665 - r - udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/gateop_perm/Z - - - - net (fanout=6) - 0.587 - 14.252 - - udp_osd_inst/char_osd_inst/char_next - - - CLMA_182_88/Y3 - td - 0.210 - 14.462 - r - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N79/gateop_perm/Z - - - - net (fanout=1) - 0.253 - 14.715 - - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N79 - - - CLMA_182_88/Y2 - td - 0.210 - 14.925 - r - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N358_5/gateop_perm/Z - - - - net (fanout=3) - 0.548 - 15.473 - - udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N96518 - - - CLMA_186_80/Y0 - td - 0.341 - 15.814 - f - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786/gateop_perm/Z - - - - net (fanout=1) - 0.540 - 16.354 - - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786 - - - CLMA_182_73/CECO - td - 0.170 - 16.524 - f - udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[4]/opit_0_A2Q21/CEOUT - - - - net (fanout=4) - 0.000 - 16.524 - - ntR2038 - - - CLMA_182_77/CECI - - - - f - udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[1]/opit_0_L5Q_perm/CE - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_720p60Hz (rising edge) - - 13.473 - 13.473 - r - - - - P20 - - 0.000 - 13.473 - r - clk (port) - - - - net (fanout=1) - 0.074 - 13.547 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 15.355 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 15.355 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 15.403 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 16.161 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.100 - 16.261 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.059 - 17.320 - - rd3_clk - - - USCM_84_154/CLK_USCM - td - 0.000 - 17.320 - r - USCMROUTE_0/CLKOUT - - - - net (fanout=1) - 1.786 - 19.106 - - ntR3907 - - - PLL_158_303/CLK_OUT1 - td - 0.096 - 19.202 - r - U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.571 - 20.773 - - nt_pix_clk - - - USCM_84_117/CLK_USCM - td - 0.000 - 20.773 - r - clkbufg_2/gopclkbufg/CLKOUT - - - - net (fanout=1635) - 1.531 - 22.304 - - ntclkbufg_2 - - - CLMA_182_77/CLK - - - - r - udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[1]/opit_0_L5Q_perm/CLK - - - clock pessimism - - 0.567 - 22.871 - - - - - clock uncertainty - - -0.150 - 22.721 - - - - - Setup time - - -0.747 - 21.974 - - - -
-
-
-
- - 5.450 - 9 - 6 - u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK - udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[2]/opit_0_L5Q_perm/CE - - clk_720p60Hz - clk_720p60Hz - rise-rise - -0.036 - 9.434 - 8.831 - 0.567 - 13.473 - 7.090 - 2.943 (41.5%) - 4.147 (58.5%) - - Path #24: setup slack is 5.450(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_720p60Hz (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.107 - 3.210 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.078 - 4.288 - - rd3_clk - - - USCM_84_154/CLK_USCM - td - 0.000 - 4.288 - r - USCMROUTE_0/CLKOUT - - - - net (fanout=1) - 1.861 - 6.149 - - ntR3907 - - - PLL_158_303/CLK_OUT1 - td - 0.101 - 6.250 - r - U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.599 - 7.849 - - nt_pix_clk - - - USCM_84_117/CLK_USCM - td - 0.000 - 7.849 - r - clkbufg_2/gopclkbufg/CLKOUT - - - - net (fanout=1635) - 1.585 - 9.434 - - ntclkbufg_2 - - - CLMS_186_117/CLK - - - - r - u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK - - - CLMS_186_117/Q2 - tco - 0.290 - 9.724 - r - u_sync_vg/pos_y[8]/opit_0_A2Q21/Q0 - - - - net (fanout=1) - 0.857 - 10.581 - - pos_y[7] - - - CLMA_186_116/COUT - td - 0.515 - 11.096 - r - udp_osd_inst/N29.eq_2/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 11.096 - - udp_osd_inst/N29.co [6] - - - CLMA_186_120/Y1 - td - 0.498 - 11.594 - r - udp_osd_inst/N29.eq_4/gateop_A2/Y1 - - - - net (fanout=5) - 0.410 - 12.004 - - udp_osd_inst/N29 - - - CLMA_190_120/Y3 - td - 0.287 - 12.291 - r - udp_osd_inst/N69_5/gateop_perm/Z - - - - net (fanout=2) - 0.551 - 12.842 - - udp_osd_inst/char_osd_inst/pixels_shifter_inst/N64 - - - CLMA_186_112/Y1 - td - 0.212 - 13.054 - r - udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/gateop_perm/Z - - - - net (fanout=2) - 0.401 - 13.455 - - udp_osd_inst/char_osd_inst/row_pixels_ready - - - CLMA_186_108/Y2 - td - 0.210 - 13.665 - r - udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/gateop_perm/Z - - - - net (fanout=6) - 0.587 - 14.252 - - udp_osd_inst/char_osd_inst/char_next - - - CLMA_182_88/Y3 - td - 0.210 - 14.462 - r - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N79/gateop_perm/Z - - - - net (fanout=1) - 0.253 - 14.715 - - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N79 - - - CLMA_182_88/Y2 - td - 0.210 - 14.925 - r - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N358_5/gateop_perm/Z - - - - net (fanout=3) - 0.548 - 15.473 - - udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N96518 - - - CLMA_186_80/Y0 - td - 0.341 - 15.814 - f - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786/gateop_perm/Z - - - - net (fanout=1) - 0.540 - 16.354 - - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786 - - - CLMA_182_73/CECO - td - 0.170 - 16.524 - f - udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[4]/opit_0_A2Q21/CEOUT - - - - net (fanout=4) - 0.000 - 16.524 - - ntR2038 - - - CLMA_182_77/CECI - - - - f - udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[2]/opit_0_L5Q_perm/CE - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_720p60Hz (rising edge) - - 13.473 - 13.473 - r - - - - P20 - - 0.000 - 13.473 - r - clk (port) - - - - net (fanout=1) - 0.074 - 13.547 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 15.355 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 15.355 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 15.403 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 16.161 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.100 - 16.261 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.059 - 17.320 - - rd3_clk - - - USCM_84_154/CLK_USCM - td - 0.000 - 17.320 - r - USCMROUTE_0/CLKOUT - - - - net (fanout=1) - 1.786 - 19.106 - - ntR3907 - - - PLL_158_303/CLK_OUT1 - td - 0.096 - 19.202 - r - U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.571 - 20.773 - - nt_pix_clk - - - USCM_84_117/CLK_USCM - td - 0.000 - 20.773 - r - clkbufg_2/gopclkbufg/CLKOUT - - - - net (fanout=1635) - 1.531 - 22.304 - - ntclkbufg_2 - - - CLMA_182_77/CLK - - - - r - udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[2]/opit_0_L5Q_perm/CLK - - - clock pessimism - - 0.567 - 22.871 - - - - - clock uncertainty - - -0.150 - 22.721 - - - - - Setup time - - -0.747 - 21.974 - - - -
-
-
-
- - 5.696 - 3 - 1 - cmos1_data[5] - u_ov5640/cmos1_d_d0[5]/opit_0/D - - cmos1_pclk - cmos1_pclk - rise-rise - 5.188 - 0.000 - 5.188 - 0.000 - 11.900 - 10.063 - 2.441 (24.3%) - 7.622 (75.7%) - - Path #25: setup slack is 5.696(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock cmos1_pclk (rising edge) - - 0.000 - 0.000 - r - - - - Input external delay - - 1.000 - 1.000 - r - - - - AB11 - - 0.000 - 1.000 - r - cmos1_data[5] (port) - - - - net (fanout=1) - 0.077 - 1.077 - - cmos1_data[5] - - - IOBS_TB_156_0/DIN - td - 2.166 - 3.243 - r - cmos1_data_ibuf[5]/opit_0/O - - - - net (fanout=1) - 0.000 - 3.243 - - cmos1_data_ibuf[5]/ntD - - - IOL_159_5/RX_DATA_DD - td - 0.126 - 3.369 - r - cmos1_data_ibuf[5]/opit_1/OUT - - - - net (fanout=1) - 2.329 - 5.698 - - nt_cmos1_data[5] - - - CLMS_322_9/Y6CD - td - 0.149 - 5.847 - r - CLKROUTE_0/Z - - - - net (fanout=1) - 5.216 - 11.063 - - ntR3901 - - - CLMS_146_9/M0 - - - - r - u_ov5640/cmos1_d_d0[5]/opit_0/D - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock cmos1_pclk (rising edge) - - 11.900 - 11.900 - r - - - - T12 - - 0.000 - 11.900 - r - cmos1_pclk (port) - - - - net (fanout=1) - 0.076 - 11.976 - - cmos1_pclk - - - IOBD_169_0/DIN - td - 1.047 - 13.023 - r - cmos1_pclk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 13.023 - - cmos1_pclk_ibuf/ntD - - - IOL_171_6/INCK - td - 0.048 - 13.071 - r - cmos1_pclk_ibuf/opit_1/INCK - - - - net (fanout=1) - 2.486 - 15.557 - - _N64 - - - USCM_84_112/CLK_USCM - td - 0.000 - 15.557 - r - clkbufg_5/gopclkbufg/CLKOUT - - - - net (fanout=118) - 1.531 - 17.088 - - ntclkbufg_5 - - - CLMS_146_9/CLK - - - - r - u_ov5640/cmos1_d_d0[5]/opit_0/CLK - - - clock pessimism - - 0.000 - 17.088 - - - - - clock uncertainty - - -0.250 - 16.838 - - - - - Setup time - - -0.079 - 16.759 - - - -
-
-
-
- - 5.704 - 2 - 1 - cmos1_data[4] - u_ov5640/cmos1_d_d0[4]/opit_0/D - - cmos1_pclk - cmos1_pclk - rise-rise - 5.188 - 0.000 - 5.188 - 0.000 - 11.900 - 10.163 - 2.292 (22.6%) - 7.871 (77.4%) - - Path #26: setup slack is 5.704(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock cmos1_pclk (rising edge) - - 0.000 - 0.000 - r - - - - Input external delay - - 1.000 - 1.000 - r - - - - W11 - - 0.000 - 1.000 - r - cmos1_data[4] (port) - - - - net (fanout=1) - 0.041 - 1.041 - - cmos1_data[4] - - - IOBS_TB_132_0/DIN - td - 2.166 - 3.207 - r - cmos1_data_ibuf[4]/opit_0/O - - - - net (fanout=1) - 0.000 - 3.207 - - cmos1_data_ibuf[4]/ntD - - - IOL_135_5/RX_DATA_DD - td - 0.126 - 3.333 - r - cmos1_data_ibuf[4]/opit_1/OUT - - - - net (fanout=1) - 7.830 - 11.163 - - nt_cmos1_data[4] - - - CLMS_134_13/AD - - - - r - u_ov5640/cmos1_d_d0[4]/opit_0/D - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock cmos1_pclk (rising edge) - - 11.900 - 11.900 - r - - - - T12 - - 0.000 - 11.900 - r - cmos1_pclk (port) - - - - net (fanout=1) - 0.076 - 11.976 - - cmos1_pclk - - - IOBD_169_0/DIN - td - 1.047 - 13.023 - r - cmos1_pclk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 13.023 - - cmos1_pclk_ibuf/ntD - - - IOL_171_6/INCK - td - 0.048 - 13.071 - r - cmos1_pclk_ibuf/opit_1/INCK - - - - net (fanout=1) - 2.486 - 15.557 - - _N64 - - - USCM_84_112/CLK_USCM - td - 0.000 - 15.557 - r - clkbufg_5/gopclkbufg/CLKOUT - - - - net (fanout=118) - 1.531 - 17.088 - - ntclkbufg_5 - - - CLMS_134_13/CLK - - - - r - u_ov5640/cmos1_d_d0[4]/opit_0/CLK - - - clock pessimism - - 0.000 - 17.088 - - - - - clock uncertainty - - -0.250 - 16.838 - - - - - Setup time - - 0.029 - 16.867 - - - -
-
-
-
- - 5.727 - 2 - 1 - cmos1_href - u_ov5640/cmos1_href_d0/opit_0/D - - cmos1_pclk - cmos1_pclk - rise-rise - 5.188 - 0.000 - 5.188 - 0.000 - 11.900 - 10.140 - 1.494 (14.7%) - 8.646 (85.3%) - - Path #27: setup slack is 5.727(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock cmos1_pclk (rising edge) - - 0.000 - 0.000 - r - - - - Input external delay - - 1.000 - 1.000 - f - - - - AB10 - - 0.000 - 1.000 - f - cmos1_href (port) - - - - net (fanout=1) - 0.063 - 1.063 - - cmos1_href - - - IOBR_TB_148_0/DIN - td - 1.367 - 2.430 - f - cmos1_href_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.430 - - cmos1_href_ibuf/ntD - - - IOL_151_5/RX_DATA_DD - td - 0.127 - 2.557 - f - cmos1_href_ibuf/opit_1/OUT - - - - net (fanout=1) - 8.583 - 11.140 - - nt_cmos1_href - - - CLMS_146_9/AD - - - - f - u_ov5640/cmos1_href_d0/opit_0/D - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock cmos1_pclk (rising edge) - - 11.900 - 11.900 - r - - - - T12 - - 0.000 - 11.900 - r - cmos1_pclk (port) - - - - net (fanout=1) - 0.076 - 11.976 - - cmos1_pclk - - - IOBD_169_0/DIN - td - 1.047 - 13.023 - r - cmos1_pclk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 13.023 - - cmos1_pclk_ibuf/ntD - - - IOL_171_6/INCK - td - 0.048 - 13.071 - r - cmos1_pclk_ibuf/opit_1/INCK - - - - net (fanout=1) - 2.486 - 15.557 - - _N64 - - - USCM_84_112/CLK_USCM - td - 0.000 - 15.557 - r - clkbufg_5/gopclkbufg/CLKOUT - - - - net (fanout=118) - 1.531 - 17.088 - - ntclkbufg_5 - - - CLMS_146_9/CLK - - - - r - u_ov5640/cmos1_href_d0/opit_0/CLK - - - clock pessimism - - 0.000 - 17.088 - - - - - clock uncertainty - - -0.250 - 16.838 - - - - - Setup time - - 0.029 - 16.867 - - - -
-
-
-
- - 10.855 - 5 - 6 - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/L4 - - clk_50m - clk_50m - rise-rise - -0.093 - 5.930 - 5.378 - 0.459 - 20.000 - 8.779 - 4.536 (51.7%) - 4.243 (48.3%) - - Path #28: setup slack is 10.855(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_50m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.107 - 3.210 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.078 - 4.288 - - rd3_clk - - - USCM_84_108/CLK_USCM - td - 0.000 - 4.288 - r - clkbufg_1/gopclkbufg/CLKOUT - - - - net (fanout=2517) - 1.642 - 5.930 - - ntclkbufg_1 - - - DRM_82_4/CLKB[0] - - - - r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB - - - DRM_82_4/QB0[0] - tco - 2.307 - 8.237 - f - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/DOB[0] - - - - net (fanout=6) - 1.382 - 9.619 - - u_rotate_image/dout [0] - - - CLMS_74_73/Y1 - td - 0.197 - 9.816 - f - u_rotate_image/addr_fifo_valid/opit_0_L5Q_perm/Z - - - - net (fanout=3) - 1.147 - 10.963 - - u_rotate_image/addr_fifo_rd_en - - - - td - 0.288 - 11.251 - f - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/Cout - - - - net (fanout=1) - 0.000 - 11.251 - - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16637 - - - CLMS_78_9/Y3 - td - 0.501 - 11.752 - r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/Y1 - - - - net (fanout=1) - 0.401 - 12.153 - - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11 [3] - - - CLMS_74_13/Y3 - td - 0.210 - 12.363 - r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[3]/gateop_perm/Z - - - - net (fanout=3) - 0.766 - 13.129 - - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/rrptr [3] - - - - td - 0.477 - 13.606 - f - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_0/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 13.606 - - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.co [2] - - - CLMA_90_20/COUT - td - 0.058 - 13.664 - r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_2/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 13.664 - - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.co [6] - - - CLMA_90_24/Y1 - td - 0.498 - 14.162 - r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_4/gateop_A2/Y1 - - - - net (fanout=1) - 0.547 - 14.709 - - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21 - - - CLMA_94_16/C4 - - - - r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/L4 - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_50m (rising edge) - - 20.000 - 20.000 - r - - - - P20 - - 0.000 - 20.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 20.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 21.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 21.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 21.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 22.688 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.100 - 22.788 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.059 - 23.847 - - rd3_clk - - - USCM_84_108/CLK_USCM - td - 0.000 - 23.847 - r - clkbufg_1/gopclkbufg/CLKOUT - - - - net (fanout=2517) - 1.531 - 25.378 - - ntclkbufg_1 - - - CLMA_94_16/CLK - - - - r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK - - - clock pessimism - - 0.459 - 25.837 - - - - - clock uncertainty - - -0.150 - 25.687 - - - - - Setup time - - -0.123 - 25.564 - - - -
-
-
-
- - 11.756 - 5 - 6 - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/L4 - - clk_50m - clk_50m - rise-rise - -0.093 - 5.930 - 5.378 - 0.459 - 20.000 - 7.878 - 4.714 (59.8%) - 3.164 (40.2%) - - Path #29: setup slack is 11.756(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_50m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.107 - 3.210 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.078 - 4.288 - - rd3_clk - - - USCM_84_108/CLK_USCM - td - 0.000 - 4.288 - r - clkbufg_1/gopclkbufg/CLKOUT - - - - net (fanout=2517) - 1.642 - 5.930 - - ntclkbufg_1 - - - DRM_82_4/CLKB[0] - - - - r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB - - - DRM_82_4/QB0[0] - tco - 2.307 - 8.237 - f - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/DOB[0] - - - - net (fanout=6) - 1.130 - 9.367 - - u_rotate_image/dout [0] - - - CLMS_74_73/Y3 - td - 0.465 - 9.832 - f - u_rotate_image/fifo_data_valid/opit_0_L5Q_perm/Z - - - - net (fanout=3) - 0.774 - 10.606 - - u_rotate_image/N170 - - - - td - 0.288 - 10.894 - f - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/Cout - - - - net (fanout=1) - 0.000 - 10.894 - - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16662 - - - CLMA_58_92/Y3 - td - 0.501 - 11.395 - r - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/Y1 - - - - net (fanout=1) - 0.268 - 11.663 - - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11 [3] - - - CLMA_58_89/Y3 - td - 0.459 - 12.122 - r - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[3]/gateop_perm/Z - - - - net (fanout=1) - 0.735 - 12.857 - - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/rrptr [3] - - - - td - 0.477 - 13.334 - f - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N24.eq_0/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 13.334 - - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N24.co [2] - - - CLMS_50_93/COUT - td - 0.058 - 13.392 - r - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N24.eq_2/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 13.392 - - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N24.co [6] - - - CLMS_50_97/Y0 - td - 0.159 - 13.551 - r - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/Y0 - - - - net (fanout=1) - 0.257 - 13.808 - - _N70 - - - CLMS_50_97/C4 - - - - r - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/L4 - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_50m (rising edge) - - 20.000 - 20.000 - r - - - - P20 - - 0.000 - 20.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 20.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 21.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 21.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 21.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 22.688 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.100 - 22.788 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.059 - 23.847 - - rd3_clk - - - USCM_84_108/CLK_USCM - td - 0.000 - 23.847 - r - clkbufg_1/gopclkbufg/CLKOUT - - - - net (fanout=2517) - 1.531 - 25.378 - - ntclkbufg_1 - - - CLMS_50_97/CLK - - - - r - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK - - - clock pessimism - - 0.459 - 25.837 - - - - - clock uncertainty - - -0.150 - 25.687 - - - - - Setup time - - -0.123 - 25.564 - - - -
-
-
-
- - 11.848 - 5 - 6 - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/Cin - - clk_50m - clk_50m - rise-rise - -0.093 - 5.930 - 5.378 - 0.459 - 20.000 - 7.552 - 4.136 (54.8%) - 3.416 (45.2%) - - Path #30: setup slack is 11.848(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_50m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.107 - 3.210 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.078 - 4.288 - - rd3_clk - - - USCM_84_108/CLK_USCM - td - 0.000 - 4.288 - r - clkbufg_1/gopclkbufg/CLKOUT - - - - net (fanout=2517) - 1.642 - 5.930 - - ntclkbufg_1 - - - DRM_82_4/CLKB[0] - - - - r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB - - - DRM_82_4/QB0[0] - tco - 2.307 - 8.237 - f - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/DOB[0] - - - - net (fanout=6) - 1.382 - 9.619 - - u_rotate_image/dout [0] - - - CLMS_74_73/Y1 - td - 0.197 - 9.816 - f - u_rotate_image/addr_fifo_valid/opit_0_L5Q_perm/Z - - - - net (fanout=3) - 1.147 - 10.963 - - u_rotate_image/addr_fifo_rd_en - - - - td - 0.288 - 11.251 - f - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/Cout - - - - net (fanout=1) - 0.000 - 11.251 - - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16637 - - - CLMS_78_9/COUT - td - 0.058 - 11.309 - r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/Cout - - - - net (fanout=1) - 0.000 - 11.309 - - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16639 - - - - td - 0.058 - 11.367 - r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/Cout - - - - net (fanout=1) - 0.000 - 11.367 - - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16641 - - - CLMS_78_13/Y3 - td - 0.501 - 11.868 - r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/Y1 - - - - net (fanout=1) - 0.395 - 12.263 - - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11 [7] - - - CLMS_74_13/Y1 - td - 0.212 - 12.475 - r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[7]/gateop_perm/Z - - - - net (fanout=3) - 0.492 - 12.967 - - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/rrptr [7] - - - CLMA_94_12/COUT - td - 0.515 - 13.482 - r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N24.eq_2/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 13.482 - - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N24.co [6] - - - CLMA_94_16/CIN - - - - r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/Cin - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_50m (rising edge) - - 20.000 - 20.000 - r - - - - P20 - - 0.000 - 20.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 20.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 21.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 21.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 21.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 22.688 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.100 - 22.788 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.059 - 23.847 - - rd3_clk - - - USCM_84_108/CLK_USCM - td - 0.000 - 23.847 - r - clkbufg_1/gopclkbufg/CLKOUT - - - - net (fanout=2517) - 1.531 - 25.378 - - ntclkbufg_1 - - - CLMA_94_16/CLK - - - - r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/CLK - - - clock pessimism - - 0.459 - 25.837 - - - - - clock uncertainty - - -0.150 - 25.687 - - - - - Setup time - - -0.357 - 25.330 - - - -
-
-
-
- - 35.419 - 4 - 13 - u_ov5640/coms1_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK - u_ov5640/coms1_reg_config/clock_20k_cnt[8]/opit_0_inv/D - - clk_25m - clk_25m - rise-rise - 0.000 - 5.877 - 5.383 - 0.494 - 40.000 - 4.352 - 2.052 (47.2%) - 2.300 (52.8%) - - Path #31: setup slack is 35.419(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_25m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT3 - td - 0.111 - 3.214 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT3 - - - - net (fanout=1) - 1.078 - 4.292 - - clk_25m - - - USCM_84_114/CLK_USCM - td - 0.000 - 4.292 - r - clkbufg_7/gopclkbufg/CLKOUT - - - - net (fanout=26) - 1.585 - 5.877 - - ntclkbufg_7 - - - CLMA_182_17/CLK - - - - r - u_ov5640/coms1_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK - - - CLMA_182_17/Q0 - tco - 0.289 - 6.166 - r - u_ov5640/coms1_reg_config/clock_20k_cnt[0]/opit_0_inv/Q - - - - net (fanout=4) - 0.557 - 6.723 - - u_ov5640/coms1_reg_config/clock_20k_cnt [0] - - - CLMA_182_13/Y2 - td - 0.487 - 7.210 - r - u_ov5640/coms1_reg_config/N8_mux4_5/gateop_perm/Z - - - - net (fanout=1) - 0.403 - 7.613 - - u_ov5640/coms1_reg_config/_N9664 - - - CLMA_186_16/Y0 - td - 0.210 - 7.823 - r - u_ov5640/coms1_reg_config/N8_mux10/gateop_perm/Z - - - - net (fanout=13) - 0.777 - 8.600 - - u_ov5640/coms1_reg_config/N8 - - - CLMA_182_12/COUT - td - 0.507 - 9.107 - r - u_ov5640/coms1_reg_config/N11_2_3/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 9.107 - - u_ov5640/coms1_reg_config/_N16248 - - - - td - 0.058 - 9.165 - r - u_ov5640/coms1_reg_config/N11_2_5/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 9.165 - - u_ov5640/coms1_reg_config/_N16250 - - - CLMA_182_16/Y3 - td - 0.501 - 9.666 - r - u_ov5640/coms1_reg_config/N11_2_7/gateop_A2/Y1 - - - - net (fanout=1) - 0.563 - 10.229 - - u_ov5640/coms1_reg_config/N1114 [8] - - - CLMA_182_17/M2 - - - - r - u_ov5640/coms1_reg_config/clock_20k_cnt[8]/opit_0_inv/D - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_25m (rising edge) - - 40.000 - 40.000 - r - - - - P20 - - 0.000 - 40.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 40.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 41.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 41.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 41.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 42.688 - - _N69 - - - PLL_158_55/CLK_OUT3 - td - 0.105 - 42.793 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT3 - - - - net (fanout=1) - 1.059 - 43.852 - - clk_25m - - - USCM_84_114/CLK_USCM - td - 0.000 - 43.852 - r - clkbufg_7/gopclkbufg/CLKOUT - - - - net (fanout=26) - 1.531 - 45.383 - - ntclkbufg_7 - - - CLMA_182_17/CLK - - - - r - u_ov5640/coms1_reg_config/clock_20k_cnt[8]/opit_0_inv/CLK - - - clock pessimism - - 0.494 - 45.877 - - - - - clock uncertainty - - -0.150 - 45.727 - - - - - Setup time - - -0.079 - 45.648 - - - -
-
-
-
- - 35.435 - 4 - 13 - u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK - u_ov5640/coms2_reg_config/clock_20k_cnt[6]/opit_0_inv/D - - clk_25m - clk_25m - rise-rise - -0.029 - 5.877 - 5.383 - 0.465 - 40.000 - 4.307 - 2.095 (48.6%) - 2.212 (51.4%) - - Path #32: setup slack is 35.435(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_25m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT3 - td - 0.111 - 3.214 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT3 - - - - net (fanout=1) - 1.078 - 4.292 - - clk_25m - - - USCM_84_114/CLK_USCM - td - 0.000 - 4.292 - r - clkbufg_7/gopclkbufg/CLKOUT - - - - net (fanout=26) - 1.585 - 5.877 - - ntclkbufg_7 - - - CLMA_182_21/CLK - - - - r - u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK - - - CLMA_182_21/Q2 - tco - 0.290 - 6.167 - r - u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/Q - - - - net (fanout=4) - 0.548 - 6.715 - - u_ov5640/coms2_reg_config/clock_20k_cnt [0] - - - CLMA_186_16/Y1 - td - 0.468 - 7.183 - r - u_ov5640/coms2_reg_config/N8_mux4_5/gateop_perm/Z - - - - net (fanout=1) - 0.398 - 7.581 - - u_ov5640/coms2_reg_config/_N9736 - - - CLMA_186_20/Y1 - td - 0.304 - 7.885 - r - u_ov5640/coms2_reg_config/N8_mux10/gateop_perm/Z - - - - net (fanout=13) - 0.644 - 8.529 - - u_ov5640/coms2_reg_config/N8 - - - - td - 0.477 - 9.006 - f - u_ov5640/coms2_reg_config/N11_2_1/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 9.006 - - u_ov5640/coms2_reg_config/_N16399 - - - CLMA_182_21/COUT - td - 0.058 - 9.064 - r - u_ov5640/coms2_reg_config/N11_2_3/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 9.064 - - u_ov5640/coms2_reg_config/_N16401 - - - CLMA_182_25/Y1 - td - 0.498 - 9.562 - r - u_ov5640/coms2_reg_config/N11_2_5/gateop_A2/Y1 - - - - net (fanout=1) - 0.622 - 10.184 - - u_ov5640/coms2_reg_config/N1114 [6] - - - CLMA_182_20/M1 - - - - r - u_ov5640/coms2_reg_config/clock_20k_cnt[6]/opit_0_inv/D - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_25m (rising edge) - - 40.000 - 40.000 - r - - - - P20 - - 0.000 - 40.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 40.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 41.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 41.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 41.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 42.688 - - _N69 - - - PLL_158_55/CLK_OUT3 - td - 0.105 - 42.793 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT3 - - - - net (fanout=1) - 1.059 - 43.852 - - clk_25m - - - USCM_84_114/CLK_USCM - td - 0.000 - 43.852 - r - clkbufg_7/gopclkbufg/CLKOUT - - - - net (fanout=26) - 1.531 - 45.383 - - ntclkbufg_7 - - - CLMA_182_20/CLK - - - - r - u_ov5640/coms2_reg_config/clock_20k_cnt[6]/opit_0_inv/CLK - - - clock pessimism - - 0.465 - 45.848 - - - - - clock uncertainty - - -0.150 - 45.698 - - - - - Setup time - - -0.079 - 45.619 - - - -
-
-
-
- - 35.450 - 3 - 13 - u_ov5640/coms1_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK - u_ov5640/coms1_reg_config/clock_20k_cnt[4]/opit_0_inv/D - - clk_25m - clk_25m - rise-rise - -0.029 - 5.877 - 5.383 - 0.465 - 40.000 - 4.292 - 1.964 (45.8%) - 2.328 (54.2%) - - Path #33: setup slack is 35.450(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_25m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT3 - td - 0.111 - 3.214 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT3 - - - - net (fanout=1) - 1.078 - 4.292 - - clk_25m - - - USCM_84_114/CLK_USCM - td - 0.000 - 4.292 - r - clkbufg_7/gopclkbufg/CLKOUT - - - - net (fanout=26) - 1.585 - 5.877 - - ntclkbufg_7 - - - CLMA_182_17/CLK - - - - r - u_ov5640/coms1_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK - - - CLMA_182_17/Q0 - tco - 0.289 - 6.166 - r - u_ov5640/coms1_reg_config/clock_20k_cnt[0]/opit_0_inv/Q - - - - net (fanout=4) - 0.557 - 6.723 - - u_ov5640/coms1_reg_config/clock_20k_cnt [0] - - - CLMA_182_13/Y2 - td - 0.487 - 7.210 - r - u_ov5640/coms1_reg_config/N8_mux4_5/gateop_perm/Z - - - - net (fanout=1) - 0.403 - 7.613 - - u_ov5640/coms1_reg_config/_N9664 - - - CLMA_186_16/Y0 - td - 0.210 - 7.823 - r - u_ov5640/coms1_reg_config/N8_mux10/gateop_perm/Z - - - - net (fanout=13) - 0.598 - 8.421 - - u_ov5640/coms1_reg_config/N8 - - - - td - 0.477 - 8.898 - f - u_ov5640/coms1_reg_config/N11_2_1/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 8.898 - - u_ov5640/coms1_reg_config/_N16246 - - - CLMA_182_12/Y3 - td - 0.501 - 9.399 - r - u_ov5640/coms1_reg_config/N11_2_3/gateop_A2/Y1 - - - - net (fanout=1) - 0.770 - 10.169 - - u_ov5640/coms1_reg_config/N1114 [4] - - - CLMA_182_16/M0 - - - - r - u_ov5640/coms1_reg_config/clock_20k_cnt[4]/opit_0_inv/D - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_25m (rising edge) - - 40.000 - 40.000 - r - - - - P20 - - 0.000 - 40.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 40.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 41.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 41.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 41.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 42.688 - - _N69 - - - PLL_158_55/CLK_OUT3 - td - 0.105 - 42.793 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT3 - - - - net (fanout=1) - 1.059 - 43.852 - - clk_25m - - - USCM_84_114/CLK_USCM - td - 0.000 - 43.852 - r - clkbufg_7/gopclkbufg/CLKOUT - - - - net (fanout=26) - 1.531 - 45.383 - - ntclkbufg_7 - - - CLMA_182_16/CLK - - - - r - u_ov5640/coms1_reg_config/clock_20k_cnt[4]/opit_0_inv/CLK - - - clock pessimism - - 0.465 - 45.848 - - - - - clock uncertainty - - -0.150 - 45.698 - - - - - Setup time - - -0.079 - 45.619 - - - -
-
-
-
- - 94.174 - 6 - 15 - ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK - ms72xx_ctl/ms7200_ctl/freq_ensure/opit_0_L5Q_perm/L4 - - clk_10m - clk_10m - rise-rise - -0.036 - 5.873 - 5.378 - 0.459 - 100.000 - 5.519 - 2.198 (39.8%) - 3.321 (60.2%) - - Path #34: setup slack is 94.174(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_10m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT4 - td - 0.107 - 3.210 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT4 - - - - net (fanout=1) - 1.078 - 4.288 - - clk_10m - - - USCM_84_110/CLK_USCM - td - 0.000 - 4.288 - r - clkbufg_3/gopclkbufg/CLKOUT - - - - net (fanout=235) - 1.585 - 5.873 - - ntclkbufg_3 - - - CLMS_242_113/CLK - - - - r - ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK - - - CLMS_242_113/Q3 - tco - 0.288 - 6.161 - r - ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/Q - - - - net (fanout=3) - 0.420 - 6.581 - - ms72xx_ctl/ms7200_ctl/dri_cnt [4] - - - CLMS_246_113/Y2 - td - 0.487 - 7.068 - r - ms72xx_ctl/ms7200_ctl/N8_3/gateop_perm/Z - - - - net (fanout=1) - 0.120 - 7.188 - - ms72xx_ctl/ms7200_ctl/_N95853 - - - CLMS_246_113/Y0 - td - 0.210 - 7.398 - r - ms72xx_ctl/ms7200_ctl/N1872_5/gateop_perm/Z - - - - net (fanout=6) - 0.421 - 7.819 - - ms72xx_ctl/ms7200_ctl/_N95857 - - - CLMS_242_117/Y1 - td - 0.304 - 8.123 - r - ms72xx_ctl/ms7200_ctl/N2053_1/gateop_perm/Z - - - - net (fanout=15) - 0.790 - 8.913 - - ms72xx_ctl/ms7200_ctl/N261 - - - CLMA_226_104/Y1 - td - 0.212 - 9.125 - r - ms72xx_ctl/ms7200_ctl/N40_9/gateop_perm/Z - - - - net (fanout=4) - 0.550 - 9.675 - - ms72xx_ctl/ms7200_ctl/N2093 [4] - - - CLMA_230_108/Y0 - td - 0.210 - 9.885 - r - ms72xx_ctl/ms7200_ctl/state_reg[1]/opit_0_inv_L5Q_perm/Z - - - - net (fanout=2) - 0.608 - 10.493 - - ms72xx_ctl/ms7200_ctl/state_n [1] - - - CLMS_226_105/Y0 - td - 0.487 - 10.980 - r - ms72xx_ctl/ms7200_ctl/N1797/gateop_perm/Z - - - - net (fanout=1) - 0.412 - 11.392 - - ms72xx_ctl/ms7200_ctl/N1797 - - - CLMA_230_105/A4 - - - - r - ms72xx_ctl/ms7200_ctl/freq_ensure/opit_0_L5Q_perm/L4 - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_10m (rising edge) - - 100.000 - 100.000 - r - - - - P20 - - 0.000 - 100.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 100.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 101.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 101.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 101.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 102.688 - - _N69 - - - PLL_158_55/CLK_OUT4 - td - 0.100 - 102.788 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT4 - - - - net (fanout=1) - 1.059 - 103.847 - - clk_10m - - - USCM_84_110/CLK_USCM - td - 0.000 - 103.847 - r - clkbufg_3/gopclkbufg/CLKOUT - - - - net (fanout=235) - 1.531 - 105.378 - - ntclkbufg_3 - - - CLMA_230_105/CLK - - - - r - ms72xx_ctl/ms7200_ctl/freq_ensure/opit_0_L5Q_perm/CLK - - - clock pessimism - - 0.459 - 105.837 - - - - - clock uncertainty - - -0.150 - 105.687 - - - - - Setup time - - -0.121 - 105.566 - - - -
-
-
-
- - 94.230 - 6 - 15 - ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK - ms72xx_ctl/ms7200_ctl/freq_rec_2d[16]/opit_0/CE - - clk_10m - clk_10m - rise-rise - -0.036 - 5.873 - 5.378 - 0.459 - 100.000 - 4.967 - 1.908 (38.4%) - 3.059 (61.6%) - - Path #35: setup slack is 94.230(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_10m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT4 - td - 0.107 - 3.210 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT4 - - - - net (fanout=1) - 1.078 - 4.288 - - clk_10m - - - USCM_84_110/CLK_USCM - td - 0.000 - 4.288 - r - clkbufg_3/gopclkbufg/CLKOUT - - - - net (fanout=235) - 1.585 - 5.873 - - ntclkbufg_3 - - - CLMS_242_113/CLK - - - - r - ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK - - - CLMS_242_113/Q3 - tco - 0.288 - 6.161 - r - ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/Q - - - - net (fanout=3) - 0.420 - 6.581 - - ms72xx_ctl/ms7200_ctl/dri_cnt [4] - - - CLMS_246_113/Y2 - td - 0.487 - 7.068 - r - ms72xx_ctl/ms7200_ctl/N8_3/gateop_perm/Z - - - - net (fanout=1) - 0.120 - 7.188 - - ms72xx_ctl/ms7200_ctl/_N95853 - - - CLMS_246_113/Y0 - td - 0.210 - 7.398 - r - ms72xx_ctl/ms7200_ctl/N1872_5/gateop_perm/Z - - - - net (fanout=6) - 0.421 - 7.819 - - ms72xx_ctl/ms7200_ctl/_N95857 - - - CLMS_242_117/Y1 - td - 0.304 - 8.123 - r - ms72xx_ctl/ms7200_ctl/N2053_1/gateop_perm/Z - - - - net (fanout=15) - 0.790 - 8.913 - - ms72xx_ctl/ms7200_ctl/N261 - - - CLMA_226_104/Y1 - td - 0.212 - 9.125 - r - ms72xx_ctl/ms7200_ctl/N40_9/gateop_perm/Z - - - - net (fanout=4) - 0.550 - 9.675 - - ms72xx_ctl/ms7200_ctl/N2093 [4] - - - CLMA_230_108/Y0 - td - 0.210 - 9.885 - r - ms72xx_ctl/ms7200_ctl/state_reg[1]/opit_0_inv_L5Q_perm/Z - - - - net (fanout=2) - 0.656 - 10.541 - - ms72xx_ctl/ms7200_ctl/state_n [1] - - - CLMS_226_105/Y1 - td - 0.197 - 10.738 - f - ms72xx_ctl/ms7200_ctl/N8_7/gateop_perm/Z - - - - net (fanout=3) - 0.102 - 10.840 - - ms72xx_ctl/ms7200_ctl/N8 - - - CLMS_226_105/CE - - - - f - ms72xx_ctl/ms7200_ctl/freq_rec_2d[16]/opit_0/CE - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_10m (rising edge) - - 100.000 - 100.000 - r - - - - P20 - - 0.000 - 100.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 100.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 101.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 101.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 101.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 102.688 - - _N69 - - - PLL_158_55/CLK_OUT4 - td - 0.100 - 102.788 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT4 - - - - net (fanout=1) - 1.059 - 103.847 - - clk_10m - - - USCM_84_110/CLK_USCM - td - 0.000 - 103.847 - r - clkbufg_3/gopclkbufg/CLKOUT - - - - net (fanout=235) - 1.531 - 105.378 - - ntclkbufg_3 - - - CLMS_226_105/CLK - - - - r - ms72xx_ctl/ms7200_ctl/freq_rec_2d[16]/opit_0/CLK - - - clock pessimism - - 0.459 - 105.837 - - - - - clock uncertainty - - -0.150 - 105.687 - - - - - Setup time - - -0.617 - 105.070 - - - -
-
-
-
- - 94.230 - 6 - 15 - ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK - ms72xx_ctl/ms7200_ctl/freq_rec_2d[17]/opit_0/CE - - clk_10m - clk_10m - rise-rise - -0.036 - 5.873 - 5.378 - 0.459 - 100.000 - 4.967 - 1.908 (38.4%) - 3.059 (61.6%) - - Path #36: setup slack is 94.230(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_10m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT4 - td - 0.107 - 3.210 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT4 - - - - net (fanout=1) - 1.078 - 4.288 - - clk_10m - - - USCM_84_110/CLK_USCM - td - 0.000 - 4.288 - r - clkbufg_3/gopclkbufg/CLKOUT - - - - net (fanout=235) - 1.585 - 5.873 - - ntclkbufg_3 - - - CLMS_242_113/CLK - - - - r - ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK - - - CLMS_242_113/Q3 - tco - 0.288 - 6.161 - r - ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/Q - - - - net (fanout=3) - 0.420 - 6.581 - - ms72xx_ctl/ms7200_ctl/dri_cnt [4] - - - CLMS_246_113/Y2 - td - 0.487 - 7.068 - r - ms72xx_ctl/ms7200_ctl/N8_3/gateop_perm/Z - - - - net (fanout=1) - 0.120 - 7.188 - - ms72xx_ctl/ms7200_ctl/_N95853 - - - CLMS_246_113/Y0 - td - 0.210 - 7.398 - r - ms72xx_ctl/ms7200_ctl/N1872_5/gateop_perm/Z - - - - net (fanout=6) - 0.421 - 7.819 - - ms72xx_ctl/ms7200_ctl/_N95857 - - - CLMS_242_117/Y1 - td - 0.304 - 8.123 - r - ms72xx_ctl/ms7200_ctl/N2053_1/gateop_perm/Z - - - - net (fanout=15) - 0.790 - 8.913 - - ms72xx_ctl/ms7200_ctl/N261 - - - CLMA_226_104/Y1 - td - 0.212 - 9.125 - r - ms72xx_ctl/ms7200_ctl/N40_9/gateop_perm/Z - - - - net (fanout=4) - 0.550 - 9.675 - - ms72xx_ctl/ms7200_ctl/N2093 [4] - - - CLMA_230_108/Y0 - td - 0.210 - 9.885 - r - ms72xx_ctl/ms7200_ctl/state_reg[1]/opit_0_inv_L5Q_perm/Z - - - - net (fanout=2) - 0.656 - 10.541 - - ms72xx_ctl/ms7200_ctl/state_n [1] - - - CLMS_226_105/Y1 - td - 0.197 - 10.738 - f - ms72xx_ctl/ms7200_ctl/N8_7/gateop_perm/Z - - - - net (fanout=3) - 0.102 - 10.840 - - ms72xx_ctl/ms7200_ctl/N8 - - - CLMS_226_105/CE - - - - f - ms72xx_ctl/ms7200_ctl/freq_rec_2d[17]/opit_0/CE - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_10m (rising edge) - - 100.000 - 100.000 - r - - - - P20 - - 0.000 - 100.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 100.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 101.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 101.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 101.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 102.688 - - _N69 - - - PLL_158_55/CLK_OUT4 - td - 0.100 - 102.788 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT4 - - - - net (fanout=1) - 1.059 - 103.847 - - clk_10m - - - USCM_84_110/CLK_USCM - td - 0.000 - 103.847 - r - clkbufg_3/gopclkbufg/CLKOUT - - - - net (fanout=235) - 1.531 - 105.378 - - ntclkbufg_3 - - - CLMS_226_105/CLK - - - - r - ms72xx_ctl/ms7200_ctl/freq_rec_2d[17]/opit_0/CLK - - - clock pessimism - - 0.459 - 105.837 - - - - - clock uncertainty - - -0.150 - 105.687 - - - - - Setup time - - -0.617 - 105.070 - - - -
-
-
-
- - 49995.048 - 3 - 1 - u_ov5640/coms2_reg_config/reg_data/iGopDrm/CLKB[0] - u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I0 - - clk_20k - clk_20k - rise-rise - -0.036 - 9.812 - 9.014 - 0.762 - 50000.000 - 4.701 - 3.229 (68.7%) - 1.472 (31.3%) - - Path #37: setup slack is 49995.048(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_20k (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT3 - td - 0.111 - 3.214 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT3 - - - - net (fanout=1) - 1.078 - 4.292 - - clk_25m - - - USCM_84_114/CLK_USCM - td - 0.000 - 4.292 - r - clkbufg_7/gopclkbufg/CLKOUT - - - - net (fanout=26) - 1.585 - 5.877 - - ntclkbufg_7 - - - CLMA_182_25/Q1 - tco - 0.291 - 6.168 - r - u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q - - - - net (fanout=3) - 2.059 - 8.227 - - u_ov5640/coms2_reg_config/clk_20k_regdiv - - - USCM_84_120/CLK_USCM - td - 0.000 - 8.227 - r - u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - - - - net (fanout=19) - 1.585 - 9.812 - - u_ov5640/coms2_reg_config/clock_20k - - - DRM_178_24/CLKB[0] - - - - r - u_ov5640/coms2_reg_config/reg_data/iGopDrm/CLKB[0] - - - DRM_178_24/QB0[5] - tco - 2.286 - 12.098 - r - u_ov5640/coms2_reg_config/reg_data/iGopDrm/QB0[5] - - - - net (fanout=1) - 0.543 - 12.641 - - u_ov5640/coms2_reg_config/i2c_data [21] - - - CLMA_174_32/Y3 - td - 0.459 - 13.100 - r - u_ov5640/coms2_reg_config/u1/N267_29/gateop/F - - - - net (fanout=1) - 0.407 - 13.507 - - u_ov5640/coms2_reg_config/u1/_N25904 - - - CLMS_174_29/Y2 - td - 0.210 - 13.717 - r - u_ov5640/coms2_reg_config/u1/N267_35/gateop_perm/Z - - - - net (fanout=1) - 0.259 - 13.976 - - u_ov5640/coms2_reg_config/u1/_N25910 - - - CLMS_174_29/Y1 - td - 0.274 - 14.250 - r - u_ov5640/coms2_reg_config/u1/N267_36/gateop/F - - - - net (fanout=1) - 0.263 - 14.513 - - u_ov5640/coms2_reg_config/u1/_N25911 - - - CLMS_174_25/DD - - - - r - u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I0 - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_20k (rising edge) - - 50000.000 - 50000.000 - r - - - - P20 - - 0.000 - 50000.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 50000.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 50001.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 50001.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 50001.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 50002.688 - - _N69 - - - PLL_158_55/CLK_OUT3 - td - 0.105 - 50002.793 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT3 - - - - net (fanout=1) - 1.059 - 50003.852 - - clk_25m - - - USCM_84_114/CLK_USCM - td - 0.000 - 50003.852 - r - clkbufg_7/gopclkbufg/CLKOUT - - - - net (fanout=26) - 1.531 - 50005.383 - - ntclkbufg_7 - - - CLMA_182_25/Q1 - tco - 0.229 - 50005.612 - r - u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q - - - - net (fanout=3) - 1.871 - 50007.483 - - u_ov5640/coms2_reg_config/clk_20k_regdiv - - - USCM_84_120/CLK_USCM - td - 0.000 - 50007.483 - r - u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - - - - net (fanout=19) - 1.531 - 50009.014 - - u_ov5640/coms2_reg_config/clock_20k - - - CLMS_174_25/CLK - - - - r - u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/CLK - - - clock pessimism - - 0.762 - 50009.776 - - - - - clock uncertainty - - -0.050 - 50009.726 - - - - - Setup time - - -0.165 - 50009.561 - - - -
-
-
-
- - 49995.178 - 3 - 1 - u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0] - u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I0 - - clk_20k - clk_20k - rise-rise - -0.036 - 10.099 - 9.247 - 0.816 - 50000.000 - 4.571 - 3.269 (71.5%) - 1.302 (28.5%) - - Path #38: setup slack is 49995.178(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_20k (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT3 - td - 0.111 - 3.214 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT3 - - - - net (fanout=1) - 1.078 - 4.292 - - clk_25m - - - USCM_84_114/CLK_USCM - td - 0.000 - 4.292 - r - clkbufg_7/gopclkbufg/CLKOUT - - - - net (fanout=26) - 1.585 - 5.877 - - ntclkbufg_7 - - - CLMA_182_12/Q1 - tco - 0.291 - 6.168 - r - u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q - - - - net (fanout=3) - 2.346 - 8.514 - - u_ov5640/coms1_reg_config/clk_20k_regdiv - - - USCM_84_119/CLK_USCM - td - 0.000 - 8.514 - r - u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - - - - net (fanout=19) - 1.585 - 10.099 - - u_ov5640/coms1_reg_config/clock_20k - - - DRM_178_4/CLKB[0] - - - - r - u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0] - - - DRM_178_4/QB0[6] - tco - 2.307 - 12.406 - f - u_ov5640/coms1_reg_config/reg_data/iGopDrm/QB0[6] - - - - net (fanout=1) - 0.619 - 13.025 - - u_ov5640/coms1_reg_config/i2c_data [22] - - - CLMS_174_9/Y2 - td - 0.478 - 13.503 - r - u_ov5640/coms1_reg_config/u1/N267_29/gateop/F - - - - net (fanout=1) - 0.119 - 13.622 - - u_ov5640/coms1_reg_config/u1/_N25461 - - - CLMA_174_8/Y0 - td - 0.210 - 13.832 - r - u_ov5640/coms1_reg_config/u1/N267_35/gateop_perm/Z - - - - net (fanout=1) - 0.120 - 13.952 - - u_ov5640/coms1_reg_config/u1/_N25467 - - - CLMA_174_8/Y1 - td - 0.274 - 14.226 - r - u_ov5640/coms1_reg_config/u1/N267_36/gateop/F - - - - net (fanout=1) - 0.444 - 14.670 - - u_ov5640/coms1_reg_config/u1/_N25468 - - - CLMA_174_16/DD - - - - r - u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I0 - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_20k (rising edge) - - 50000.000 - 50000.000 - r - - - - P20 - - 0.000 - 50000.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 50000.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 50001.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 50001.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 50001.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 50002.688 - - _N69 - - - PLL_158_55/CLK_OUT3 - td - 0.105 - 50002.793 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT3 - - - - net (fanout=1) - 1.059 - 50003.852 - - clk_25m - - - USCM_84_114/CLK_USCM - td - 0.000 - 50003.852 - r - clkbufg_7/gopclkbufg/CLKOUT - - - - net (fanout=26) - 1.531 - 50005.383 - - ntclkbufg_7 - - - CLMA_182_12/Q1 - tco - 0.229 - 50005.612 - r - u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q - - - - net (fanout=3) - 2.104 - 50007.716 - - u_ov5640/coms1_reg_config/clk_20k_regdiv - - - USCM_84_119/CLK_USCM - td - 0.000 - 50007.716 - r - u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - - - - net (fanout=19) - 1.531 - 50009.247 - - u_ov5640/coms1_reg_config/clock_20k - - - CLMA_174_16/CLK - - - - r - u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/CLK - - - clock pessimism - - 0.816 - 50010.063 - - - - - clock uncertainty - - -0.050 - 50010.013 - - - - - Setup time - - -0.165 - 50009.848 - - - -
-
-
-
- - 49995.210 - 5 - 5 - u_ov5640/coms1_reg_config/reg_index[2]/opit_0_inv_A2Q21/CLK - u_ov5640/coms1_reg_config/reg_index[6]/opit_0_inv_A2Q21/CE - - clk_20k - clk_20k - rise-rise - -0.029 - 10.099 - 9.247 - 0.823 - 50000.000 - 3.982 - 1.684 (42.3%) - 2.298 (57.7%) - - Path #39: setup slack is 49995.210(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_20k (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT3 - td - 0.111 - 3.214 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT3 - - - - net (fanout=1) - 1.078 - 4.292 - - clk_25m - - - USCM_84_114/CLK_USCM - td - 0.000 - 4.292 - r - clkbufg_7/gopclkbufg/CLKOUT - - - - net (fanout=26) - 1.585 - 5.877 - - ntclkbufg_7 - - - CLMA_182_12/Q1 - tco - 0.291 - 6.168 - r - u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q - - - - net (fanout=3) - 2.346 - 8.514 - - u_ov5640/coms1_reg_config/clk_20k_regdiv - - - USCM_84_119/CLK_USCM - td - 0.000 - 8.514 - r - u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - - - - net (fanout=19) - 1.585 - 10.099 - - u_ov5640/coms1_reg_config/clock_20k - - - CLMS_174_13/CLK - - - - r - u_ov5640/coms1_reg_config/reg_index[2]/opit_0_inv_A2Q21/CLK - - - CLMS_174_13/Q0 - tco - 0.289 - 10.388 - r - u_ov5640/coms1_reg_config/reg_index[2]/opit_0_inv_A2Q21/Q0 - - - - net (fanout=5) - 0.475 - 10.863 - - u_ov5640/coms1_reg_config/reg_index [1] - - - CLMA_182_13/Y1 - td - 0.304 - 11.167 - r - u_ov5640/coms1_reg_config/N26_mux2/gateop_perm/Z - - - - net (fanout=1) - 0.730 - 11.897 - - u_ov5640/coms1_reg_config/_N9682 - - - CLMS_174_9/Y3 - td - 0.210 - 12.107 - r - u_ov5640/coms1_reg_config/N26_mux6_3/gateop_perm/Z - - - - net (fanout=2) - 0.557 - 12.664 - - u_ov5640/coms1_reg_config/_N9690 - - - CLMS_174_21/Y2 - td - 0.210 - 12.874 - r - u_ov5640/coms1_reg_config/N1134_1/gateop_perm/Z - - - - net (fanout=4) - 0.123 - 12.997 - - u_ov5640/coms1_reg_config/_N96528 - - - CLMS_174_21/Y0 - td - 0.487 - 13.484 - r - u_ov5640/coms1_reg_config/N1169/gateop_perm/Z - - - - net (fanout=3) - 0.413 - 13.897 - - u_ov5640/coms1_reg_config/N1169 - - - CLMS_174_13/CECO - td - 0.184 - 14.081 - r - u_ov5640/coms1_reg_config/reg_index[4]/opit_0_inv_A2Q21/CEOUT - - - - net (fanout=2) - 0.000 - 14.081 - - ntR1983 - - - CLMS_174_17/CECI - - - - r - u_ov5640/coms1_reg_config/reg_index[6]/opit_0_inv_A2Q21/CE - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_20k (rising edge) - - 50000.000 - 50000.000 - r - - - - P20 - - 0.000 - 50000.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 50000.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 50001.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 50001.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 50001.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 50002.688 - - _N69 - - - PLL_158_55/CLK_OUT3 - td - 0.105 - 50002.793 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT3 - - - - net (fanout=1) - 1.059 - 50003.852 - - clk_25m - - - USCM_84_114/CLK_USCM - td - 0.000 - 50003.852 - r - clkbufg_7/gopclkbufg/CLKOUT - - - - net (fanout=26) - 1.531 - 50005.383 - - ntclkbufg_7 - - - CLMA_182_12/Q1 - tco - 0.229 - 50005.612 - r - u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q - - - - net (fanout=3) - 2.104 - 50007.716 - - u_ov5640/coms1_reg_config/clk_20k_regdiv - - - USCM_84_119/CLK_USCM - td - 0.000 - 50007.716 - r - u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - - - - net (fanout=19) - 1.531 - 50009.247 - - u_ov5640/coms1_reg_config/clock_20k - - - CLMS_174_17/CLK - - - - r - u_ov5640/coms1_reg_config/reg_index[6]/opit_0_inv_A2Q21/CLK - - - clock pessimism - - 0.823 - 50010.070 - - - - - clock uncertainty - - -0.050 - 50010.020 - - - - - Setup time - - -0.729 - 50009.291 - - - -
-
-
-
- - - - Slack - Logic Levels - High Fanout - Start Point - End Point - Exception - Launch Clock - Capture Clock - Clock Edges - Clock Skew - Launch Clock Delay - Capture Clock Delay - Clock Pessimism Removal - Requirement - Data delay - Logic delay - Route delay - - - 0.149 - 0 - 2 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[22]/opit_0_inv/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_27/ram16x1d/WD - - ddrphy_clkin - ddrphy_clkin - rise-rise - 0.054 - 10.665 - 11.394 - -0.675 - 0.000 - 0.583 - 0.222 (38.1%) - 0.361 (61.9%) - - Path #1: hold slack is 0.149(MET) - -
- - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ddrphy_clkin (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 1.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 1.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 2.688 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.096 - 2.784 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.059 - 3.843 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 3.843 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.665 - 5.508 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.123 - 5.631 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.102 - 6.733 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.249 - 6.982 - r - clkgate_8/gopclkgate/OUT - - - - net (fanout=1) - 0.000 - 6.982 - - ntclkgate_0 - - - IOCKDIV_6_323/CLK_IODIV - td - 0.000 - 6.982 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV - - - - net (fanout=1) - 2.152 - 9.134 - - u_axi_ddr_top/clk - - - USCM_84_116/CLK_USCM - td - 0.000 - 9.134 - r - clkbufg_0/gopclkbufg/CLKOUT - - - - net (fanout=5464) - 1.531 - 10.665 - - ntclkbufg_0 - - - CLMA_58_124/CLK - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[22]/opit_0_inv/CLK - - - CLMA_58_124/Q0 - tco - 0.222 - 10.887 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[22]/opit_0_inv/Q - - - - net (fanout=2) - 0.361 - 11.248 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/dcd_wr_addr [22] - - - CLMS_50_129/DD - - - - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_27/ram16x1d/WD - -
- - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ddrphy_clkin (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.101 - 3.204 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.078 - 4.282 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 4.282 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.738 - 6.020 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.129 - 6.149 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.121 - 7.270 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.348 - 7.618 - r - clkgate_8/gopclkgate/OUT - - - - net (fanout=1) - 0.000 - 7.618 - - ntclkgate_0 - - - IOCKDIV_6_323/CLK_IODIV - td - 0.000 - 7.618 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV - - - - net (fanout=1) - 2.191 - 9.809 - - u_axi_ddr_top/clk - - - USCM_84_116/CLK_USCM - td - 0.000 - 9.809 - r - clkbufg_0/gopclkbufg/CLKOUT - - - - net (fanout=5464) - 1.585 - 11.394 - - ntclkbufg_0 - - - CLMS_50_129/CLK - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_27/ram16x1d/WCLK - - - clock pessimism - - -0.675 - 10.719 - - - - - clock uncertainty - - 0.000 - 10.719 - - - - - Hold time - - 0.380 - 11.099 - - - -
-
- -
- - 0.162 - 0 - 7 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_0/ram32x1dp/WADM0 - - ddrphy_clkin - ddrphy_clkin - rise-rise - 0.036 - 10.665 - 11.394 - -0.693 - 0.000 - 0.578 - 0.222 (38.4%) - 0.356 (61.6%) - - Path #2: hold slack is 0.162(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ddrphy_clkin (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 1.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 1.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 2.688 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.096 - 2.784 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.059 - 3.843 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 3.843 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.665 - 5.508 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.123 - 5.631 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.102 - 6.733 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.249 - 6.982 - r - clkgate_8/gopclkgate/OUT - - - - net (fanout=1) - 0.000 - 6.982 - - ntclkgate_0 - - - IOCKDIV_6_323/CLK_IODIV - td - 0.000 - 6.982 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV - - - - net (fanout=1) - 2.152 - 9.134 - - u_axi_ddr_top/clk - - - USCM_84_116/CLK_USCM - td - 0.000 - 9.134 - r - clkbufg_0/gopclkbufg/CLKOUT - - - - net (fanout=5464) - 1.531 - 10.665 - - ntclkbufg_0 - - - CLMA_58_144/CLK - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK - - - CLMA_58_144/Q0 - tco - 0.222 - 10.887 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/Q0 - - - - net (fanout=7) - 0.356 - 11.243 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [0] - - - CLMS_62_145/M0 - - - - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_0/ram32x1dp/WADM0 - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ddrphy_clkin (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.101 - 3.204 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.078 - 4.282 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 4.282 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.738 - 6.020 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.129 - 6.149 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.121 - 7.270 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.348 - 7.618 - r - clkgate_8/gopclkgate/OUT - - - - net (fanout=1) - 0.000 - 7.618 - - ntclkgate_0 - - - IOCKDIV_6_323/CLK_IODIV - td - 0.000 - 7.618 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV - - - - net (fanout=1) - 2.191 - 9.809 - - u_axi_ddr_top/clk - - - USCM_84_116/CLK_USCM - td - 0.000 - 9.809 - r - clkbufg_0/gopclkbufg/CLKOUT - - - - net (fanout=5464) - 1.585 - 11.394 - - ntclkbufg_0 - - - CLMS_62_145/CLK - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_0/ram32x1dp/WCLK - - - clock pessimism - - -0.693 - 10.701 - - - - - clock uncertainty - - 0.000 - 10.701 - - - - - Hold time - - 0.380 - 11.081 - - - -
-
-
-
- - 0.162 - 0 - 7 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram32x1dp/WADM0 - - ddrphy_clkin - ddrphy_clkin - rise-rise - 0.036 - 10.665 - 11.394 - -0.693 - 0.000 - 0.578 - 0.222 (38.4%) - 0.356 (61.6%) - - Path #3: hold slack is 0.162(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ddrphy_clkin (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 1.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 1.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 2.688 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.096 - 2.784 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.059 - 3.843 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 3.843 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.665 - 5.508 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.123 - 5.631 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.102 - 6.733 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.249 - 6.982 - r - clkgate_8/gopclkgate/OUT - - - - net (fanout=1) - 0.000 - 6.982 - - ntclkgate_0 - - - IOCKDIV_6_323/CLK_IODIV - td - 0.000 - 6.982 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV - - - - net (fanout=1) - 2.152 - 9.134 - - u_axi_ddr_top/clk - - - USCM_84_116/CLK_USCM - td - 0.000 - 9.134 - r - clkbufg_0/gopclkbufg/CLKOUT - - - - net (fanout=5464) - 1.531 - 10.665 - - ntclkbufg_0 - - - CLMA_58_144/CLK - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK - - - CLMA_58_144/Q0 - tco - 0.222 - 10.887 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/Q0 - - - - net (fanout=7) - 0.356 - 11.243 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [0] - - - CLMS_62_145/M0 - - - - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram32x1dp/WADM0 - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ddrphy_clkin (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.101 - 3.204 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.078 - 4.282 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 4.282 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.738 - 6.020 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.129 - 6.149 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.121 - 7.270 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.348 - 7.618 - r - clkgate_8/gopclkgate/OUT - - - - net (fanout=1) - 0.000 - 7.618 - - ntclkgate_0 - - - IOCKDIV_6_323/CLK_IODIV - td - 0.000 - 7.618 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV - - - - net (fanout=1) - 2.191 - 9.809 - - u_axi_ddr_top/clk - - - USCM_84_116/CLK_USCM - td - 0.000 - 9.809 - r - clkbufg_0/gopclkbufg/CLKOUT - - - - net (fanout=5464) - 1.585 - 11.394 - - ntclkbufg_0 - - - CLMS_62_145/CLK - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram32x1dp/WCLK - - - clock pessimism - - -0.693 - 10.701 - - - - - clock uncertainty - - 0.000 - 10.701 - - - - - Hold time - - 0.380 - 11.081 - - - -
-
-
-
- - 0.182 - 0 - 3 - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[8] - - clk_50m - clk_50m - rise-rise - 0.088 - 5.378 - 5.925 - -0.459 - 0.000 - 0.480 - 0.224 (46.7%) - 0.256 (53.3%) - - Path #4: hold slack is 0.182(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_50m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 1.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 1.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 2.688 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.100 - 2.788 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.059 - 3.847 - - rd3_clk - - - USCM_84_108/CLK_USCM - td - 0.000 - 3.847 - r - clkbufg_1/gopclkbufg/CLKOUT - - - - net (fanout=2517) - 1.531 - 5.378 - - ntclkbufg_1 - - - CLMA_90_12/CLK - - - - r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK - - - CLMA_90_12/Q2 - tco - 0.224 - 5.602 - f - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/Q0 - - - - net (fanout=3) - 0.256 - 5.858 - - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/wr_addr [6] - - - DRM_82_4/ADA0[8] - - - - f - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[8] - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_50m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.107 - 3.210 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.078 - 4.288 - - rd3_clk - - - USCM_84_108/CLK_USCM - td - 0.000 - 4.288 - r - clkbufg_1/gopclkbufg/CLKOUT - - - - net (fanout=2517) - 1.637 - 5.925 - - ntclkbufg_1 - - - DRM_82_4/CLKA[0] - - - - r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKA - - - clock pessimism - - -0.459 - 5.466 - - - - - clock uncertainty - - 0.000 - 5.466 - - - - - Hold time - - 0.210 - 5.676 - - - -
-
-
-
- - 0.191 - 0 - 5 - u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[2]/opit_0_L5Q_perm/CLK - u_ddr_addr_ctr/u_wr1_addr_ctr/wr_vs_flag/opit_0_L5Q_perm/L0 - - hdmi_in_clk - hdmi_in_clk - rise-rise - 0.000 - 5.951 - 6.435 - -0.484 - 0.000 - 0.312 - 0.224 (71.8%) - 0.088 (28.2%) - - Path #5: hold slack is 0.191(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock hdmi_in_clk (rising edge) - - 0.000 - 0.000 - r - - - - AA12 - - 0.000 - 0.000 - r - hdmi_in_clk (port) - - - - net (fanout=1) - 0.078 - 0.078 - - hdmi_in_clk - - - IOBD_161_0/DIN - td - 1.808 - 1.886 - r - hdmi_in_clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.886 - - hdmi_in_clk_ibuf/ntD - - - IOL_163_6/INCK - td - 0.048 - 1.934 - r - hdmi_in_clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 2.486 - 4.420 - - _N37 - - - USCM_84_111/CLK_USCM - td - 0.000 - 4.420 - r - clkbufg_4/gopclkbufg/CLKOUT - - - - net (fanout=167) - 1.531 - 5.951 - - ntclkbufg_4 - - - CLMA_110_85/CLK - - - - r - u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[2]/opit_0_L5Q_perm/CLK - - - CLMA_110_85/Q2 - tco - 0.224 - 6.175 - f - u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[2]/opit_0_L5Q_perm/Q - - - - net (fanout=5) - 0.088 - 6.263 - - u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg [2] - - - CLMA_110_85/D0 - - - - f - u_ddr_addr_ctr/u_wr1_addr_ctr/wr_vs_flag/opit_0_L5Q_perm/L0 - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock hdmi_in_clk (rising edge) - - 0.000 - 0.000 - r - - - - AA12 - - 0.000 - 0.000 - r - hdmi_in_clk (port) - - - - net (fanout=1) - 0.078 - 0.078 - - hdmi_in_clk - - - IOBD_161_0/DIN - td - 2.166 - 2.244 - r - hdmi_in_clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.244 - - hdmi_in_clk_ibuf/ntD - - - IOL_163_6/INCK - td - 0.076 - 2.320 - r - hdmi_in_clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 2.530 - 4.850 - - _N37 - - - USCM_84_111/CLK_USCM - td - 0.000 - 4.850 - r - clkbufg_4/gopclkbufg/CLKOUT - - - - net (fanout=167) - 1.585 - 6.435 - - ntclkbufg_4 - - - CLMA_110_85/CLK - - - - r - u_ddr_addr_ctr/u_wr1_addr_ctr/wr_vs_flag/opit_0_L5Q_perm/CLK - - - clock pessimism - - -0.484 - 5.951 - - - - - clock uncertainty - - 0.200 - 6.151 - - - - - Hold time - - -0.079 - 6.072 - - - -
-
-
-
- - 0.199 - 0 - 24 - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/L0 - - cmos1_pclk - cmos1_pclk - rise-rise - 0.000 - 5.188 - 5.521 - -0.333 - 0.000 - 0.319 - 0.221 (69.3%) - 0.098 (30.7%) - - Path #6: hold slack is 0.199(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock cmos1_pclk (rising edge) - - 0.000 - 0.000 - r - - - - T12 - - 0.000 - 0.000 - r - cmos1_pclk (port) - - - - net (fanout=1) - 0.076 - 0.076 - - cmos1_pclk - - - IOBD_169_0/DIN - td - 1.047 - 1.123 - r - cmos1_pclk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.123 - - cmos1_pclk_ibuf/ntD - - - IOL_171_6/INCK - td - 0.048 - 1.171 - r - cmos1_pclk_ibuf/opit_1/INCK - - - - net (fanout=1) - 2.486 - 3.657 - - _N64 - - - USCM_84_112/CLK_USCM - td - 0.000 - 3.657 - r - clkbufg_5/gopclkbufg/CLKOUT - - - - net (fanout=118) - 1.531 - 5.188 - - ntclkbufg_5 - - - CLMA_138_36/CLK - - - - r - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK - - - CLMA_138_36/Q3 - tco - 0.221 - 5.409 - f - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/Q - - - - net (fanout=24) - 0.098 - 5.507 - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wfull - - - CLMA_138_36/B0 - - - - f - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/L0 - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock cmos1_pclk (rising edge) - - 0.000 - 0.000 - r - - - - T12 - - 0.000 - 0.000 - r - cmos1_pclk (port) - - - - net (fanout=1) - 0.076 - 0.076 - - cmos1_pclk - - - IOBD_169_0/DIN - td - 1.254 - 1.330 - r - cmos1_pclk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.330 - - cmos1_pclk_ibuf/ntD - - - IOL_171_6/INCK - td - 0.076 - 1.406 - r - cmos1_pclk_ibuf/opit_1/INCK - - - - net (fanout=1) - 2.530 - 3.936 - - _N64 - - - USCM_84_112/CLK_USCM - td - 0.000 - 3.936 - r - clkbufg_5/gopclkbufg/CLKOUT - - - - net (fanout=118) - 1.585 - 5.521 - - ntclkbufg_5 - - - CLMA_138_36/CLK - - - - r - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/CLK - - - clock pessimism - - -0.333 - 5.188 - - - - - clock uncertainty - - 0.200 - 5.388 - - - - - Hold time - - -0.080 - 5.308 - - - -
-
-
-
- - 0.201 - 0 - 2 - u_ov5640/u_mix_image/cnt0_h[0]/opit_0_L5Q_perm/CLK - u_ov5640/u_mix_image/cnt0_h[0]/opit_0_L5Q_perm/L0 - - cmos1_pclk - cmos1_pclk - rise-rise - 0.000 - 5.188 - 5.521 - -0.333 - 0.000 - 0.307 - 0.222 (72.3%) - 0.085 (27.7%) - - Path #7: hold slack is 0.201(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock cmos1_pclk (rising edge) - - 0.000 - 0.000 - r - - - - T12 - - 0.000 - 0.000 - r - cmos1_pclk (port) - - - - net (fanout=1) - 0.076 - 0.076 - - cmos1_pclk - - - IOBD_169_0/DIN - td - 1.047 - 1.123 - r - cmos1_pclk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.123 - - cmos1_pclk_ibuf/ntD - - - IOL_171_6/INCK - td - 0.048 - 1.171 - r - cmos1_pclk_ibuf/opit_1/INCK - - - - net (fanout=1) - 2.486 - 3.657 - - _N64 - - - USCM_84_112/CLK_USCM - td - 0.000 - 3.657 - r - clkbufg_5/gopclkbufg/CLKOUT - - - - net (fanout=118) - 1.531 - 5.188 - - ntclkbufg_5 - - - CLMA_154_28/CLK - - - - r - u_ov5640/u_mix_image/cnt0_h[0]/opit_0_L5Q_perm/CLK - - - CLMA_154_28/Q0 - tco - 0.222 - 5.410 - f - u_ov5640/u_mix_image/cnt0_h[0]/opit_0_L5Q_perm/Q - - - - net (fanout=2) - 0.085 - 5.495 - - u_ov5640/u_mix_image/cnt0_h [0] - - - CLMA_154_28/A0 - - - - f - u_ov5640/u_mix_image/cnt0_h[0]/opit_0_L5Q_perm/L0 - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock cmos1_pclk (rising edge) - - 0.000 - 0.000 - r - - - - T12 - - 0.000 - 0.000 - r - cmos1_pclk (port) - - - - net (fanout=1) - 0.076 - 0.076 - - cmos1_pclk - - - IOBD_169_0/DIN - td - 1.254 - 1.330 - r - cmos1_pclk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.330 - - cmos1_pclk_ibuf/ntD - - - IOL_171_6/INCK - td - 0.076 - 1.406 - r - cmos1_pclk_ibuf/opit_1/INCK - - - - net (fanout=1) - 2.530 - 3.936 - - _N64 - - - USCM_84_112/CLK_USCM - td - 0.000 - 3.936 - r - clkbufg_5/gopclkbufg/CLKOUT - - - - net (fanout=118) - 1.585 - 5.521 - - ntclkbufg_5 - - - CLMA_154_28/CLK - - - - r - u_ov5640/u_mix_image/cnt0_h[0]/opit_0_L5Q_perm/CLK - - - clock pessimism - - -0.333 - 5.188 - - - - - clock uncertainty - - 0.200 - 5.388 - - - - - Hold time - - -0.094 - 5.294 - - - -
-
-
-
- - 0.201 - 0 - 2 - u_ov5640/u_mix_image/image1_en/opit_0_L5Q_perm/CLK - u_ov5640/u_mix_image/image1_en/opit_0_L5Q_perm/L0 - - cmos1_pclk - cmos1_pclk - rise-rise - 0.000 - 5.188 - 5.521 - -0.333 - 0.000 - 0.307 - 0.222 (72.3%) - 0.085 (27.7%) - - Path #8: hold slack is 0.201(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock cmos1_pclk (rising edge) - - 0.000 - 0.000 - r - - - - T12 - - 0.000 - 0.000 - r - cmos1_pclk (port) - - - - net (fanout=1) - 0.076 - 0.076 - - cmos1_pclk - - - IOBD_169_0/DIN - td - 1.047 - 1.123 - r - cmos1_pclk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.123 - - cmos1_pclk_ibuf/ntD - - - IOL_171_6/INCK - td - 0.048 - 1.171 - r - cmos1_pclk_ibuf/opit_1/INCK - - - - net (fanout=1) - 2.486 - 3.657 - - _N64 - - - USCM_84_112/CLK_USCM - td - 0.000 - 3.657 - r - clkbufg_5/gopclkbufg/CLKOUT - - - - net (fanout=118) - 1.531 - 5.188 - - ntclkbufg_5 - - - CLMA_150_28/CLK - - - - r - u_ov5640/u_mix_image/image1_en/opit_0_L5Q_perm/CLK - - - CLMA_150_28/Q0 - tco - 0.222 - 5.410 - f - u_ov5640/u_mix_image/image1_en/opit_0_L5Q_perm/Q - - - - net (fanout=2) - 0.085 - 5.495 - - u_ov5640/u_mix_image/image1_en - - - CLMA_150_28/A0 - - - - f - u_ov5640/u_mix_image/image1_en/opit_0_L5Q_perm/L0 - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock cmos1_pclk (rising edge) - - 0.000 - 0.000 - r - - - - T12 - - 0.000 - 0.000 - r - cmos1_pclk (port) - - - - net (fanout=1) - 0.076 - 0.076 - - cmos1_pclk - - - IOBD_169_0/DIN - td - 1.254 - 1.330 - r - cmos1_pclk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.330 - - cmos1_pclk_ibuf/ntD - - - IOL_171_6/INCK - td - 0.076 - 1.406 - r - cmos1_pclk_ibuf/opit_1/INCK - - - - net (fanout=1) - 2.530 - 3.936 - - _N64 - - - USCM_84_112/CLK_USCM - td - 0.000 - 3.936 - r - clkbufg_5/gopclkbufg/CLKOUT - - - - net (fanout=118) - 1.585 - 5.521 - - ntclkbufg_5 - - - CLMA_150_28/CLK - - - - r - u_ov5640/u_mix_image/image1_en/opit_0_L5Q_perm/CLK - - - clock pessimism - - -0.333 - 5.188 - - - - - clock uncertainty - - 0.200 - 5.388 - - - - - Hold time - - -0.094 - 5.294 - - - -
-
-
-
- - 0.203 - 0 - 24 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm/L0 - - hdmi_in_clk - hdmi_in_clk - rise-rise - 0.000 - 5.951 - 6.435 - -0.484 - 0.000 - 0.324 - 0.224 (69.1%) - 0.100 (30.9%) - - Path #9: hold slack is 0.203(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock hdmi_in_clk (rising edge) - - 0.000 - 0.000 - r - - - - AA12 - - 0.000 - 0.000 - r - hdmi_in_clk (port) - - - - net (fanout=1) - 0.078 - 0.078 - - hdmi_in_clk - - - IOBD_161_0/DIN - td - 1.808 - 1.886 - r - hdmi_in_clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.886 - - hdmi_in_clk_ibuf/ntD - - - IOL_163_6/INCK - td - 0.048 - 1.934 - r - hdmi_in_clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 2.486 - 4.420 - - _N37 - - - USCM_84_111/CLK_USCM - td - 0.000 - 4.420 - r - clkbufg_4/gopclkbufg/CLKOUT - - - - net (fanout=167) - 1.531 - 5.951 - - ntclkbufg_4 - - - CLMA_66_104/CLK - - - - r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK - - - CLMA_66_104/Q2 - tco - 0.224 - 6.175 - f - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/Q - - - - net (fanout=24) - 0.100 - 6.275 - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wfull - - - CLMA_66_104/D0 - - - - f - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm/L0 - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock hdmi_in_clk (rising edge) - - 0.000 - 0.000 - r - - - - AA12 - - 0.000 - 0.000 - r - hdmi_in_clk (port) - - - - net (fanout=1) - 0.078 - 0.078 - - hdmi_in_clk - - - IOBD_161_0/DIN - td - 2.166 - 2.244 - r - hdmi_in_clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.244 - - hdmi_in_clk_ibuf/ntD - - - IOL_163_6/INCK - td - 0.076 - 2.320 - r - hdmi_in_clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 2.530 - 4.850 - - _N37 - - - USCM_84_111/CLK_USCM - td - 0.000 - 4.850 - r - clkbufg_4/gopclkbufg/CLKOUT - - - - net (fanout=167) - 1.585 - 6.435 - - ntclkbufg_4 - - - CLMA_66_104/CLK - - - - r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm/CLK - - - clock pessimism - - -0.484 - 5.951 - - - - - clock uncertainty - - 0.200 - 6.151 - - - - - Hold time - - -0.079 - 6.072 - - - -
-
-
-
- - 0.206 - 0 - 13 - u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[0]/opit_0_L5Q_perm/CLK - u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[0]/opit_0_L5Q_perm/L0 - - hdmi_in_clk - hdmi_in_clk - rise-rise - 0.000 - 5.951 - 6.435 - -0.484 - 0.000 - 0.312 - 0.222 (71.2%) - 0.090 (28.8%) - - Path #10: hold slack is 0.206(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock hdmi_in_clk (rising edge) - - 0.000 - 0.000 - r - - - - AA12 - - 0.000 - 0.000 - r - hdmi_in_clk (port) - - - - net (fanout=1) - 0.078 - 0.078 - - hdmi_in_clk - - - IOBD_161_0/DIN - td - 1.808 - 1.886 - r - hdmi_in_clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.886 - - hdmi_in_clk_ibuf/ntD - - - IOL_163_6/INCK - td - 0.048 - 1.934 - r - hdmi_in_clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 2.486 - 4.420 - - _N37 - - - USCM_84_111/CLK_USCM - td - 0.000 - 4.420 - r - clkbufg_4/gopclkbufg/CLKOUT - - - - net (fanout=167) - 1.531 - 5.951 - - ntclkbufg_4 - - - CLMA_110_85/CLK - - - - r - u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[0]/opit_0_L5Q_perm/CLK - - - CLMA_110_85/Q0 - tco - 0.222 - 6.173 - f - u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[0]/opit_0_L5Q_perm/Q - - - - net (fanout=13) - 0.090 - 6.263 - - u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg [0] - - - CLMA_110_85/A0 - - - - f - u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[0]/opit_0_L5Q_perm/L0 - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock hdmi_in_clk (rising edge) - - 0.000 - 0.000 - r - - - - AA12 - - 0.000 - 0.000 - r - hdmi_in_clk (port) - - - - net (fanout=1) - 0.078 - 0.078 - - hdmi_in_clk - - - IOBD_161_0/DIN - td - 2.166 - 2.244 - r - hdmi_in_clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.244 - - hdmi_in_clk_ibuf/ntD - - - IOL_163_6/INCK - td - 0.076 - 2.320 - r - hdmi_in_clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 2.530 - 4.850 - - _N37 - - - USCM_84_111/CLK_USCM - td - 0.000 - 4.850 - r - clkbufg_4/gopclkbufg/CLKOUT - - - - net (fanout=167) - 1.585 - 6.435 - - ntclkbufg_4 - - - CLMA_110_85/CLK - - - - r - u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[0]/opit_0_L5Q_perm/CLK - - - clock pessimism - - -0.484 - 5.951 - - - - - clock uncertainty - - 0.200 - 6.151 - - - - - Hold time - - -0.094 - 6.057 - - - -
-
-
-
- - 0.222 - 0 - 1 - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/D - - clk_50m - clk_50m - rise-rise - 0.030 - 5.403 - 5.899 - -0.466 - 0.000 - 0.305 - 0.221 (72.5%) - 0.084 (27.5%) - - Path #11: hold slack is 0.222(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_50m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 1.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 1.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 2.688 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.100 - 2.788 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.059 - 3.847 - - rd3_clk - - - USCM_84_108/CLK_USCM - td - 0.000 - 3.847 - r - clkbufg_1/gopclkbufg/CLKOUT - - - - net (fanout=2517) - 1.556 - 5.403 - - ntclkbufg_1 - - - CLMA_58_88/CLK - - - - r - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK - - - CLMA_58_88/Q3 - tco - 0.221 - 5.624 - f - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/Q - - - - net (fanout=1) - 0.084 - 5.708 - - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr1 [8] - - - CLMA_58_89/AD - - - - f - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/D - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_50m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.107 - 3.210 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.078 - 4.288 - - rd3_clk - - - USCM_84_108/CLK_USCM - td - 0.000 - 4.288 - r - clkbufg_1/gopclkbufg/CLKOUT - - - - net (fanout=2517) - 1.611 - 5.899 - - ntclkbufg_1 - - - CLMA_58_89/CLK - - - - r - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/CLK - - - clock pessimism - - -0.466 - 5.433 - - - - - clock uncertainty - - 0.000 - 5.433 - - - - - Hold time - - 0.053 - 5.486 - - - -
-
-
-
- - 0.241 - 0 - 1 - u_zoom_image/mult_image_g0/N2/gopapm/CLK - u_zoom_image/mult_image_g1/N2/gopapm/PI[0] - - clk_200m - clk_200m - rise-rise - 0.177 - 5.374 - 5.990 - -0.439 - 0.000 - 0.297 - 0.297 (100.0%) - 0.000 (0.0%) - - Path #12: hold slack is 0.241(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_200m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 1.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 1.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 2.688 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.096 - 2.784 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.059 - 3.843 - - zoom_clk - - - USCM_84_122/CLK_USCM - td - 0.000 - 3.843 - r - USCMROUTE_2/CLKOUT - - - - net (fanout=759) - 1.531 - 5.374 - - ntR3909 - - - APM_206_240/CLK - - - - r - u_zoom_image/mult_image_g0/N2/gopapm/CLK - - - APM_206_240/PO[0] - tco - 0.297 - 5.671 - r - u_zoom_image/mult_image_g0/N2/gopapm/PO[0] - - - - net (fanout=1) - 0.000 - 5.671 - - u_zoom_image/mult_image0[2] [0] - - - APM_206_252/PI[0] - - - - r - u_zoom_image/mult_image_g1/N2/gopapm/PI[0] - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_200m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.101 - 3.204 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.078 - 4.282 - - zoom_clk - - - USCM_84_122/CLK_USCM - td - 0.000 - 4.282 - r - USCMROUTE_2/CLKOUT - - - - net (fanout=759) - 1.708 - 5.990 - - ntR3909 - - - APM_206_252/CLK - - - - r - u_zoom_image/mult_image_g1/N2/gopapm/CLK - - - clock pessimism - - -0.439 - 5.551 - - - - - clock uncertainty - - 0.000 - 5.551 - - - - - Hold time - - -0.121 - 5.430 - - - -
-
-
-
- - 0.241 - 0 - 1 - u_zoom_image/mult_image_g0/N2/gopapm/CLK - u_zoom_image/mult_image_g1/N2/gopapm/PI[1] - - clk_200m - clk_200m - rise-rise - 0.177 - 5.374 - 5.990 - -0.439 - 0.000 - 0.297 - 0.297 (100.0%) - 0.000 (0.0%) - - Path #13: hold slack is 0.241(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_200m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 1.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 1.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 2.688 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.096 - 2.784 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.059 - 3.843 - - zoom_clk - - - USCM_84_122/CLK_USCM - td - 0.000 - 3.843 - r - USCMROUTE_2/CLKOUT - - - - net (fanout=759) - 1.531 - 5.374 - - ntR3909 - - - APM_206_240/CLK - - - - r - u_zoom_image/mult_image_g0/N2/gopapm/CLK - - - APM_206_240/PO[1] - tco - 0.297 - 5.671 - r - u_zoom_image/mult_image_g0/N2/gopapm/PO[1] - - - - net (fanout=1) - 0.000 - 5.671 - - u_zoom_image/mult_image0[2] [1] - - - APM_206_252/PI[1] - - - - r - u_zoom_image/mult_image_g1/N2/gopapm/PI[1] - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_200m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.101 - 3.204 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.078 - 4.282 - - zoom_clk - - - USCM_84_122/CLK_USCM - td - 0.000 - 4.282 - r - USCMROUTE_2/CLKOUT - - - - net (fanout=759) - 1.708 - 5.990 - - ntR3909 - - - APM_206_252/CLK - - - - r - u_zoom_image/mult_image_g1/N2/gopapm/CLK - - - clock pessimism - - -0.439 - 5.551 - - - - - clock uncertainty - - 0.000 - 5.551 - - - - - Hold time - - -0.121 - 5.430 - - - -
-
-
-
- - 0.241 - 0 - 1 - u_zoom_image/mult_image_g0/N2/gopapm/CLK - u_zoom_image/mult_image_g1/N2/gopapm/PI[2] - - clk_200m - clk_200m - rise-rise - 0.177 - 5.374 - 5.990 - -0.439 - 0.000 - 0.297 - 0.297 (100.0%) - 0.000 (0.0%) - - Path #14: hold slack is 0.241(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_200m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 1.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 1.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 2.688 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.096 - 2.784 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.059 - 3.843 - - zoom_clk - - - USCM_84_122/CLK_USCM - td - 0.000 - 3.843 - r - USCMROUTE_2/CLKOUT - - - - net (fanout=759) - 1.531 - 5.374 - - ntR3909 - - - APM_206_240/CLK - - - - r - u_zoom_image/mult_image_g0/N2/gopapm/CLK - - - APM_206_240/PO[2] - tco - 0.297 - 5.671 - r - u_zoom_image/mult_image_g0/N2/gopapm/PO[2] - - - - net (fanout=1) - 0.000 - 5.671 - - u_zoom_image/mult_image0[2] [2] - - - APM_206_252/PI[2] - - - - r - u_zoom_image/mult_image_g1/N2/gopapm/PI[2] - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_200m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.101 - 3.204 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.078 - 4.282 - - zoom_clk - - - USCM_84_122/CLK_USCM - td - 0.000 - 4.282 - r - USCMROUTE_2/CLKOUT - - - - net (fanout=759) - 1.708 - 5.990 - - ntR3909 - - - APM_206_252/CLK - - - - r - u_zoom_image/mult_image_g1/N2/gopapm/CLK - - - clock pessimism - - -0.439 - 5.551 - - - - - clock uncertainty - - 0.000 - 5.551 - - - - - Hold time - - -0.121 - 5.430 - - - -
-
-
-
- - 0.252 - 0 - 1 - image_filiter_inst2/hybrid_filter_inst/pixel_ff[27]/opit_0/CLK - image_filiter_inst2/hybrid_filter_inst/pixel_ff[43]/opit_0/D - - clk_50m - clk_50m - rise-rise - 0.000 - 5.378 - 5.873 - -0.495 - 0.000 - 0.305 - 0.221 (72.5%) - 0.084 (27.5%) - - Path #15: hold slack is 0.252(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_50m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 1.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 1.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 2.688 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.100 - 2.788 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.059 - 3.847 - - rd3_clk - - - USCM_84_108/CLK_USCM - td - 0.000 - 3.847 - r - clkbufg_1/gopclkbufg/CLKOUT - - - - net (fanout=2517) - 1.531 - 5.378 - - ntclkbufg_1 - - - CLMA_98_148/CLK - - - - r - image_filiter_inst2/hybrid_filter_inst/pixel_ff[27]/opit_0/CLK - - - CLMA_98_148/Q3 - tco - 0.221 - 5.599 - f - image_filiter_inst2/hybrid_filter_inst/pixel_ff[27]/opit_0/Q - - - - net (fanout=1) - 0.084 - 5.683 - - image_filiter_inst2/hybrid_filter_inst/pixel_ff [27] - - - CLMA_98_148/AD - - - - f - image_filiter_inst2/hybrid_filter_inst/pixel_ff[43]/opit_0/D - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_50m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.107 - 3.210 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.078 - 4.288 - - rd3_clk - - - USCM_84_108/CLK_USCM - td - 0.000 - 4.288 - r - clkbufg_1/gopclkbufg/CLKOUT - - - - net (fanout=2517) - 1.585 - 5.873 - - ntclkbufg_1 - - - CLMA_98_148/CLK - - - - r - image_filiter_inst2/hybrid_filter_inst/pixel_ff[43]/opit_0/CLK - - - clock pessimism - - -0.495 - 5.378 - - - - - clock uncertainty - - 0.000 - 5.378 - - - - - Hold time - - 0.053 - 5.431 - - - -
-
-
-
- - 0.313 - 0 - 1 - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/quotient[1]/opit_0_L5Q_perm/CLK - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/quotient[2]/opit_0_L5Q_perm/L4 - - clk_720p60Hz - clk_720p60Hz - rise-rise - 0.029 - 8.831 - 9.434 - -0.574 - 0.000 - 0.308 - 0.224 (72.7%) - 0.084 (27.3%) - - Path #16: hold slack is 0.313(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_720p60Hz (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 1.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 1.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 2.688 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.100 - 2.788 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.059 - 3.847 - - rd3_clk - - - USCM_84_154/CLK_USCM - td - 0.000 - 3.847 - r - USCMROUTE_0/CLKOUT - - - - net (fanout=1) - 1.786 - 5.633 - - ntR3907 - - - PLL_158_303/CLK_OUT1 - td - 0.096 - 5.729 - r - U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.571 - 7.300 - - nt_pix_clk - - - USCM_84_117/CLK_USCM - td - 0.000 - 7.300 - r - clkbufg_2/gopclkbufg/CLKOUT - - - - net (fanout=1635) - 1.531 - 8.831 - - ntclkbufg_2 - - - CLMA_266_132/CLK - - - - r - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/quotient[1]/opit_0_L5Q_perm/CLK - - - CLMA_266_132/Q1 - tco - 0.224 - 9.055 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/quotient[1]/opit_0_L5Q_perm/Q - - - - net (fanout=1) - 0.084 - 9.139 - - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/quotient_t[4] [1] - - - CLMS_266_133/C4 - - - - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/quotient[2]/opit_0_L5Q_perm/L4 - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_720p60Hz (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.107 - 3.210 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.078 - 4.288 - - rd3_clk - - - USCM_84_154/CLK_USCM - td - 0.000 - 4.288 - r - USCMROUTE_0/CLKOUT - - - - net (fanout=1) - 1.861 - 6.149 - - ntR3907 - - - PLL_158_303/CLK_OUT1 - td - 0.101 - 6.250 - r - U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.599 - 7.849 - - nt_pix_clk - - - USCM_84_117/CLK_USCM - td - 0.000 - 7.849 - r - clkbufg_2/gopclkbufg/CLKOUT - - - - net (fanout=1635) - 1.585 - 9.434 - - ntclkbufg_2 - - - CLMS_266_133/CLK - - - - r - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/quotient[2]/opit_0_L5Q_perm/CLK - - - clock pessimism - - -0.574 - 8.860 - - - - - clock uncertainty - - 0.000 - 8.860 - - - - - Hold time - - -0.034 - 8.826 - - - -
-
-
-
- - 0.314 - 0 - 1 - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[3]/opit_0_L5Q_perm/CLK - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[4]/opit_0_L5Q_perm/L4 - - clk_720p60Hz - clk_720p60Hz - rise-rise - 0.029 - 8.831 - 9.434 - -0.574 - 0.000 - 0.308 - 0.224 (72.7%) - 0.084 (27.3%) - - Path #17: hold slack is 0.314(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_720p60Hz (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 1.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 1.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 2.688 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.100 - 2.788 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.059 - 3.847 - - rd3_clk - - - USCM_84_154/CLK_USCM - td - 0.000 - 3.847 - r - USCMROUTE_0/CLKOUT - - - - net (fanout=1) - 1.786 - 5.633 - - ntR3907 - - - PLL_158_303/CLK_OUT1 - td - 0.096 - 5.729 - r - U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.571 - 7.300 - - nt_pix_clk - - - USCM_84_117/CLK_USCM - td - 0.000 - 7.300 - r - clkbufg_2/gopclkbufg/CLKOUT - - - - net (fanout=1635) - 1.531 - 8.831 - - ntclkbufg_2 - - - CLMA_262_132/CLK - - - - r - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[3]/opit_0_L5Q_perm/CLK - - - CLMA_262_132/Q2 - tco - 0.224 - 9.055 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[3]/opit_0_L5Q_perm/Q - - - - net (fanout=1) - 0.084 - 9.139 - - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/quotient_t[1] [3] - - - CLMS_262_133/A4 - - - - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[4]/opit_0_L5Q_perm/L4 - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_720p60Hz (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.107 - 3.210 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.078 - 4.288 - - rd3_clk - - - USCM_84_154/CLK_USCM - td - 0.000 - 4.288 - r - USCMROUTE_0/CLKOUT - - - - net (fanout=1) - 1.861 - 6.149 - - ntR3907 - - - PLL_158_303/CLK_OUT1 - td - 0.101 - 6.250 - r - U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.599 - 7.849 - - nt_pix_clk - - - USCM_84_117/CLK_USCM - td - 0.000 - 7.849 - r - clkbufg_2/gopclkbufg/CLKOUT - - - - net (fanout=1635) - 1.585 - 9.434 - - ntclkbufg_2 - - - CLMS_262_133/CLK - - - - r - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[4]/opit_0_L5Q_perm/CLK - - - clock pessimism - - -0.574 - 8.860 - - - - - clock uncertainty - - 0.000 - 8.860 - - - - - Hold time - - -0.035 - 8.825 - - - -
-
-
-
- - 0.314 - 0 - 2 - ms72xx_ctl/iic_dri_tx/receiv_data[1]/opit_0_inv/CLK - ms72xx_ctl/iic_dri_tx/data_out[1]/opit_0/D - - clk_10m - clk_10m - rise-rise - 0.029 - 5.378 - 5.873 - -0.466 - 0.000 - 0.329 - 0.226 (68.7%) - 0.103 (31.3%) - - Path #18: hold slack is 0.314(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_10m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 1.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 1.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 2.688 - - _N69 - - - PLL_158_55/CLK_OUT4 - td - 0.100 - 2.788 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT4 - - - - net (fanout=1) - 1.059 - 3.847 - - clk_10m - - - USCM_84_110/CLK_USCM - td - 0.000 - 3.847 - r - clkbufg_3/gopclkbufg/CLKOUT - - - - net (fanout=235) - 1.531 - 5.378 - - ntclkbufg_3 - - - CLMS_202_113/CLK - - - - r - ms72xx_ctl/iic_dri_tx/receiv_data[1]/opit_0_inv/CLK - - - CLMS_202_113/Q0 - tco - 0.226 - 5.604 - r - ms72xx_ctl/iic_dri_tx/receiv_data[1]/opit_0_inv/Q - - - - net (fanout=2) - 0.103 - 5.707 - - ms72xx_ctl/iic_dri_tx/receiv_data [1] - - - CLMA_202_112/M0 - - - - r - ms72xx_ctl/iic_dri_tx/data_out[1]/opit_0/D - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_10m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT4 - td - 0.107 - 3.210 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT4 - - - - net (fanout=1) - 1.078 - 4.288 - - clk_10m - - - USCM_84_110/CLK_USCM - td - 0.000 - 4.288 - r - clkbufg_3/gopclkbufg/CLKOUT - - - - net (fanout=235) - 1.585 - 5.873 - - ntclkbufg_3 - - - CLMA_202_112/CLK - - - - r - ms72xx_ctl/iic_dri_tx/data_out[1]/opit_0/CLK - - - clock pessimism - - -0.466 - 5.407 - - - - - clock uncertainty - - 0.000 - 5.407 - - - - - Hold time - - -0.014 - 5.393 - - - -
-
-
-
- - 0.314 - 0 - 2 - udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[3]/opit_0_A2Q21/CLK - udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr[4]/opit_0_A2Q21/I04 - - clk_720p60Hz - clk_720p60Hz - rise-rise - 0.029 - 8.831 - 9.434 - -0.574 - 0.000 - 0.309 - 0.224 (72.5%) - 0.085 (27.5%) - - Path #19: hold slack is 0.314(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_720p60Hz (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 1.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 1.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 2.688 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.100 - 2.788 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.059 - 3.847 - - rd3_clk - - - USCM_84_154/CLK_USCM - td - 0.000 - 3.847 - r - USCMROUTE_0/CLKOUT - - - - net (fanout=1) - 1.786 - 5.633 - - ntR3907 - - - PLL_158_303/CLK_OUT1 - td - 0.096 - 5.729 - r - U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.571 - 7.300 - - nt_pix_clk - - - USCM_84_117/CLK_USCM - td - 0.000 - 7.300 - r - clkbufg_2/gopclkbufg/CLKOUT - - - - net (fanout=1635) - 1.531 - 8.831 - - ntclkbufg_2 - - - CLMA_174_52/CLK - - - - r - udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[3]/opit_0_A2Q21/CLK - - - CLMA_174_52/Q1 - tco - 0.224 - 9.055 - f - udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[3]/opit_0_A2Q21/Q1 - - - - net (fanout=2) - 0.085 - 9.140 - - udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d [3] - - - CLMS_174_53/C4 - - - - f - udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr[4]/opit_0_A2Q21/I04 - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_720p60Hz (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.107 - 3.210 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.078 - 4.288 - - rd3_clk - - - USCM_84_154/CLK_USCM - td - 0.000 - 4.288 - r - USCMROUTE_0/CLKOUT - - - - net (fanout=1) - 1.861 - 6.149 - - ntR3907 - - - PLL_158_303/CLK_OUT1 - td - 0.101 - 6.250 - r - U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.599 - 7.849 - - nt_pix_clk - - - USCM_84_117/CLK_USCM - td - 0.000 - 7.849 - r - clkbufg_2/gopclkbufg/CLKOUT - - - - net (fanout=1635) - 1.585 - 9.434 - - ntclkbufg_2 - - - CLMS_174_53/CLK - - - - r - udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr[4]/opit_0_A2Q21/CLK - - - clock pessimism - - -0.574 - 8.860 - - - - - clock uncertainty - - 0.000 - 8.860 - - - - - Hold time - - -0.034 - 8.826 - - - -
-
-
-
- - 0.331 - 0 - 3 - ms72xx_ctl/ms7200_ctl/cmd_index[5]/opit_0_inv_A2Q21/CLK - ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/ADB0[9] - - clk_10m - clk_10m - rise-rise - 0.036 - 5.378 - 5.873 - -0.459 - 0.000 - 0.446 - 0.226 (50.7%) - 0.220 (49.3%) - - Path #20: hold slack is 0.331(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_10m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 1.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 1.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 2.688 - - _N69 - - - PLL_158_55/CLK_OUT4 - td - 0.100 - 2.788 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT4 - - - - net (fanout=1) - 1.059 - 3.847 - - clk_10m - - - USCM_84_110/CLK_USCM - td - 0.000 - 3.847 - r - clkbufg_3/gopclkbufg/CLKOUT - - - - net (fanout=235) - 1.531 - 5.378 - - ntclkbufg_3 - - - CLMA_230_117/CLK - - - - r - ms72xx_ctl/ms7200_ctl/cmd_index[5]/opit_0_inv_A2Q21/CLK - - - CLMA_230_117/Q0 - tco - 0.226 - 5.604 - r - ms72xx_ctl/ms7200_ctl/cmd_index[5]/opit_0_inv_A2Q21/Q0 - - - - net (fanout=3) - 0.220 - 5.824 - - ms72xx_ctl/ms7200_ctl/cmd_index [4] - - - DRM_234_108/ADB0[9] - - - - r - ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/ADB0[9] - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_10m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT4 - td - 0.107 - 3.210 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT4 - - - - net (fanout=1) - 1.078 - 4.288 - - clk_10m - - - USCM_84_110/CLK_USCM - td - 0.000 - 4.288 - r - clkbufg_3/gopclkbufg/CLKOUT - - - - net (fanout=235) - 1.585 - 5.873 - - ntclkbufg_3 - - - DRM_234_108/CLKB[0] - - - - r - ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKB[0] - - - clock pessimism - - -0.459 - 5.414 - - - - - clock uncertainty - - 0.000 - 5.414 - - - - - Hold time - - 0.079 - 5.493 - - - -
-
-
-
- - 0.340 - 0 - 3 - ms72xx_ctl/ms7200_ctl/cmd_index[5]/opit_0_inv_A2Q21/CLK - ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/ADA0[9] - - clk_10m - clk_10m - rise-rise - 0.036 - 5.378 - 5.873 - -0.459 - 0.000 - 0.537 - 0.222 (41.3%) - 0.315 (58.7%) - - Path #21: hold slack is 0.340(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_10m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 1.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 1.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 2.688 - - _N69 - - - PLL_158_55/CLK_OUT4 - td - 0.100 - 2.788 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT4 - - - - net (fanout=1) - 1.059 - 3.847 - - clk_10m - - - USCM_84_110/CLK_USCM - td - 0.000 - 3.847 - r - clkbufg_3/gopclkbufg/CLKOUT - - - - net (fanout=235) - 1.531 - 5.378 - - ntclkbufg_3 - - - CLMA_230_117/CLK - - - - r - ms72xx_ctl/ms7200_ctl/cmd_index[5]/opit_0_inv_A2Q21/CLK - - - CLMA_230_117/Q0 - tco - 0.222 - 5.600 - f - ms72xx_ctl/ms7200_ctl/cmd_index[5]/opit_0_inv_A2Q21/Q0 - - - - net (fanout=3) - 0.315 - 5.915 - - ms72xx_ctl/ms7200_ctl/cmd_index [4] - - - DRM_234_108/ADA0[9] - - - - f - ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/ADA0[9] - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_10m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT4 - td - 0.107 - 3.210 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT4 - - - - net (fanout=1) - 1.078 - 4.288 - - clk_10m - - - USCM_84_110/CLK_USCM - td - 0.000 - 4.288 - r - clkbufg_3/gopclkbufg/CLKOUT - - - - net (fanout=235) - 1.585 - 5.873 - - ntclkbufg_3 - - - DRM_234_108/CLKA[0] - - - - r - ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKA[0] - - - clock pessimism - - -0.459 - 5.414 - - - - - clock uncertainty - - 0.000 - 5.414 - - - - - Hold time - - 0.161 - 5.575 - - - -
-
-
-
- - 0.376 - 0 - 6 - u_ov5640/coms1_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK - u_ov5640/coms1_reg_config/reg_data/iGopDrm/ADA0[5] - - clk_20k - clk_20k - rise-rise - 0.036 - 9.247 - 10.099 - -0.816 - 0.000 - 0.573 - 0.222 (38.7%) - 0.351 (61.3%) - - Path #22: hold slack is 0.376(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_20k (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 1.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 1.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 2.688 - - _N69 - - - PLL_158_55/CLK_OUT3 - td - 0.105 - 2.793 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT3 - - - - net (fanout=1) - 1.059 - 3.852 - - clk_25m - - - USCM_84_114/CLK_USCM - td - 0.000 - 3.852 - r - clkbufg_7/gopclkbufg/CLKOUT - - - - net (fanout=26) - 1.531 - 5.383 - - ntclkbufg_7 - - - CLMA_182_12/Q1 - tco - 0.229 - 5.612 - r - u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q - - - - net (fanout=3) - 2.104 - 7.716 - - u_ov5640/coms1_reg_config/clk_20k_regdiv - - - USCM_84_119/CLK_USCM - td - 0.000 - 7.716 - r - u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - - - - net (fanout=19) - 1.531 - 9.247 - - u_ov5640/coms1_reg_config/clock_20k - - - CLMA_182_13/CLK - - - - r - u_ov5640/coms1_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK - - - CLMA_182_13/Q0 - tco - 0.222 - 9.469 - f - u_ov5640/coms1_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/Q - - - - net (fanout=6) - 0.351 - 9.820 - - u_ov5640/coms1_reg_config/reg_index [0] - - - DRM_178_4/ADA0[5] - - - - f - u_ov5640/coms1_reg_config/reg_data/iGopDrm/ADA0[5] - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_20k (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT3 - td - 0.111 - 3.214 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT3 - - - - net (fanout=1) - 1.078 - 4.292 - - clk_25m - - - USCM_84_114/CLK_USCM - td - 0.000 - 4.292 - r - clkbufg_7/gopclkbufg/CLKOUT - - - - net (fanout=26) - 1.585 - 5.877 - - ntclkbufg_7 - - - CLMA_182_12/Q1 - tco - 0.291 - 6.168 - r - u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q - - - - net (fanout=3) - 2.346 - 8.514 - - u_ov5640/coms1_reg_config/clk_20k_regdiv - - - USCM_84_119/CLK_USCM - td - 0.000 - 8.514 - r - u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - - - - net (fanout=19) - 1.585 - 10.099 - - u_ov5640/coms1_reg_config/clock_20k - - - DRM_178_4/CLKA[0] - - - - r - u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKA[0] - - - clock pessimism - - -0.816 - 9.283 - - - - - clock uncertainty - - 0.000 - 9.283 - - - - - Hold time - - 0.161 - 9.444 - - - -
-
-
-
- - 0.378 - 0 - 6 - u_ov5640/coms2_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK - u_ov5640/coms2_reg_config/reg_data/iGopDrm/ADA0[5] - - clk_20k - clk_20k - rise-rise - 0.036 - 9.014 - 9.812 - -0.762 - 0.000 - 0.575 - 0.222 (38.6%) - 0.353 (61.4%) - - Path #23: hold slack is 0.378(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_20k (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 1.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 1.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 2.688 - - _N69 - - - PLL_158_55/CLK_OUT3 - td - 0.105 - 2.793 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT3 - - - - net (fanout=1) - 1.059 - 3.852 - - clk_25m - - - USCM_84_114/CLK_USCM - td - 0.000 - 3.852 - r - clkbufg_7/gopclkbufg/CLKOUT - - - - net (fanout=26) - 1.531 - 5.383 - - ntclkbufg_7 - - - CLMA_182_25/Q1 - tco - 0.229 - 5.612 - r - u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q - - - - net (fanout=3) - 1.871 - 7.483 - - u_ov5640/coms2_reg_config/clk_20k_regdiv - - - USCM_84_120/CLK_USCM - td - 0.000 - 7.483 - r - u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - - - - net (fanout=19) - 1.531 - 9.014 - - u_ov5640/coms2_reg_config/clock_20k - - - CLMA_182_32/CLK - - - - r - u_ov5640/coms2_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK - - - CLMA_182_32/Q0 - tco - 0.222 - 9.236 - f - u_ov5640/coms2_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/Q - - - - net (fanout=6) - 0.353 - 9.589 - - u_ov5640/coms2_reg_config/reg_index [0] - - - DRM_178_24/ADA0[5] - - - - f - u_ov5640/coms2_reg_config/reg_data/iGopDrm/ADA0[5] - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_20k (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT3 - td - 0.111 - 3.214 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT3 - - - - net (fanout=1) - 1.078 - 4.292 - - clk_25m - - - USCM_84_114/CLK_USCM - td - 0.000 - 4.292 - r - clkbufg_7/gopclkbufg/CLKOUT - - - - net (fanout=26) - 1.585 - 5.877 - - ntclkbufg_7 - - - CLMA_182_25/Q1 - tco - 0.291 - 6.168 - r - u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q - - - - net (fanout=3) - 2.059 - 8.227 - - u_ov5640/coms2_reg_config/clk_20k_regdiv - - - USCM_84_120/CLK_USCM - td - 0.000 - 8.227 - r - u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - - - - net (fanout=19) - 1.585 - 9.812 - - u_ov5640/coms2_reg_config/clock_20k - - - DRM_178_24/CLKA[0] - - - - r - u_ov5640/coms2_reg_config/reg_data/iGopDrm/CLKA[0] - - - clock pessimism - - -0.762 - 9.050 - - - - - clock uncertainty - - 0.000 - 9.050 - - - - - Hold time - - 0.161 - 9.211 - - - -
-
-
-
- - 0.381 - 0 - 5 - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[3]/opit_0_L5Q_perm/CLK - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[4]/opit_0_L6Q_perm/A3 - - eth_rxc - eth_rxc - rise-rise - 0.000 - 8.446 - 10.030 - -1.584 - 0.000 - 0.312 - 0.224 (71.8%) - 0.088 (28.2%) - - Path #24: hold slack is 0.381(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock eth_rxc (rising edge) - - 0.000 - 0.000 - r - - - - F14 - - 0.000 - 0.000 - r - eth_rxc (port) - - - - net (fanout=1) - 0.057 - 0.057 - - eth_rxc - - - IOBD_240_376/DIN - td - 1.047 - 1.104 - r - eth_rxc_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.104 - - eth_rxc_ibuf/ntD - - - IOL_243_374/INCK - td - 0.048 - 1.152 - r - eth_rxc_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.636 - 1.788 - - _N66 - - - IOCKDLY_237_367/CLK_OUT - td - 2.574 - 4.362 - r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT - - - - net (fanout=1) - 2.553 - 6.915 - - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf - - - USCM_84_109/CLK_USCM - td - 0.000 - 6.915 - r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - - - - net (fanout=1861) - 1.531 - 8.446 - - gmii_clk - - - CLMS_162_225/CLK - - - - r - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[3]/opit_0_L5Q_perm/CLK - - - CLMS_162_225/Q2 - tco - 0.224 - 8.670 - f - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[3]/opit_0_L5Q_perm/Q - - - - net (fanout=5) - 0.088 - 8.758 - - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg [3] - - - CLMS_162_225/A3 - - - - f - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[4]/opit_0_L6Q_perm/A3 - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock eth_rxc (rising edge) - - 0.000 - 0.000 - r - - - - F14 - - 0.000 - 0.000 - r - eth_rxc (port) - - - - net (fanout=1) - 0.057 - 0.057 - - eth_rxc - - - IOBD_240_376/DIN - td - 1.254 - 1.311 - r - eth_rxc_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.311 - - eth_rxc_ibuf/ntD - - - IOL_243_374/INCK - td - 0.076 - 1.387 - r - eth_rxc_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.647 - 2.034 - - _N66 - - - IOCKDLY_237_367/CLK_OUT - td - 3.812 - 5.846 - r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT - - - - net (fanout=1) - 2.599 - 8.445 - - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf - - - USCM_84_109/CLK_USCM - td - 0.000 - 8.445 - r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - - - - net (fanout=1861) - 1.585 - 10.030 - - gmii_clk - - - CLMS_162_225/CLK - - - - r - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[4]/opit_0_L6Q_perm/CLK - - - clock pessimism - - -1.584 - 8.446 - - - - - clock uncertainty - - 0.200 - 8.646 - - - - - Hold time - - -0.269 - 8.377 - - - -
-
-
-
- - 0.386 - 0 - 2 - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[12]/opit_0/CLK - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[14]/opit_0_A2Q21/Cin - - eth_rxc - eth_rxc - rise-rise - 0.029 - 8.446 - 10.030 - -1.555 - 0.000 - 0.544 - 0.357 (65.6%) - 0.187 (34.4%) - - Path #25: hold slack is 0.386(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock eth_rxc (rising edge) - - 0.000 - 0.000 - r - - - - F14 - - 0.000 - 0.000 - r - eth_rxc (port) - - - - net (fanout=1) - 0.057 - 0.057 - - eth_rxc - - - IOBD_240_376/DIN - td - 1.047 - 1.104 - r - eth_rxc_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.104 - - eth_rxc_ibuf/ntD - - - IOL_243_374/INCK - td - 0.048 - 1.152 - r - eth_rxc_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.636 - 1.788 - - _N66 - - - IOCKDLY_237_367/CLK_OUT - td - 2.574 - 4.362 - r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT - - - - net (fanout=1) - 2.553 - 6.915 - - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf - - - USCM_84_109/CLK_USCM - td - 0.000 - 6.915 - r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - - - - net (fanout=1861) - 1.531 - 8.446 - - gmii_clk - - - CLMS_186_213/CLK - - - - r - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[12]/opit_0/CLK - - - CLMS_186_213/Q3 - tco - 0.221 - 8.667 - f - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[12]/opit_0/Q - - - - net (fanout=2) - 0.187 - 8.854 - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length [12] - - - - td - 0.136 - 8.990 - f - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[12]/opit_0_A2Q21/Cout - - - - net (fanout=1) - 0.000 - 8.990 - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N168_1.co [10] - - - - - - - f - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[14]/opit_0_A2Q21/Cin - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock eth_rxc (rising edge) - - 0.000 - 0.000 - r - - - - F14 - - 0.000 - 0.000 - r - eth_rxc (port) - - - - net (fanout=1) - 0.057 - 0.057 - - eth_rxc - - - IOBD_240_376/DIN - td - 1.254 - 1.311 - r - eth_rxc_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.311 - - eth_rxc_ibuf/ntD - - - IOL_243_374/INCK - td - 0.076 - 1.387 - r - eth_rxc_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.647 - 2.034 - - _N66 - - - IOCKDLY_237_367/CLK_OUT - td - 3.812 - 5.846 - r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT - - - - net (fanout=1) - 2.599 - 8.445 - - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf - - - USCM_84_109/CLK_USCM - td - 0.000 - 8.445 - r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - - - - net (fanout=1861) - 1.585 - 10.030 - - gmii_clk - - - CLMA_186_212/CLK - - - - r - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[14]/opit_0_A2Q21/CLK - - - clock pessimism - - -1.555 - 8.475 - - - - - clock uncertainty - - 0.200 - 8.675 - - - - - Hold time - - -0.071 - 8.604 - - - -
-
-
-
- - 0.391 - 0 - 1 - param_manager_inst/modify_H_flags_ff1/opit_0/CLK - param_manager_inst/modify_H_load/opit_0_L5Q_perm/L2 - - eth_rxc - eth_rxc - rise-rise - 0.000 - 8.446 - 10.030 - -1.584 - 0.000 - 0.370 - 0.284 (76.8%) - 0.086 (23.2%) - - Path #26: hold slack is 0.391(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock eth_rxc (rising edge) - - 0.000 - 0.000 - r - - - - F14 - - 0.000 - 0.000 - r - eth_rxc (port) - - - - net (fanout=1) - 0.057 - 0.057 - - eth_rxc - - - IOBD_240_376/DIN - td - 1.047 - 1.104 - r - eth_rxc_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.104 - - eth_rxc_ibuf/ntD - - - IOL_243_374/INCK - td - 0.048 - 1.152 - r - eth_rxc_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.636 - 1.788 - - _N66 - - - IOCKDLY_237_367/CLK_OUT - td - 2.574 - 4.362 - r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT - - - - net (fanout=1) - 2.553 - 6.915 - - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf - - - USCM_84_109/CLK_USCM - td - 0.000 - 6.915 - r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - - - - net (fanout=1861) - 1.531 - 8.446 - - gmii_clk - - - CLMS_214_137/CLK - - - - r - param_manager_inst/modify_H_flags_ff1/opit_0/CLK - - - CLMS_214_137/Y2 - tco - 0.284 - 8.730 - f - param_manager_inst/modify_H_flags_ff1/opit_0/Q - - - - net (fanout=1) - 0.086 - 8.816 - - param_manager_inst/modify_H_flags_ff1 - - - CLMS_214_137/B2 - - - - f - param_manager_inst/modify_H_load/opit_0_L5Q_perm/L2 - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock eth_rxc (rising edge) - - 0.000 - 0.000 - r - - - - F14 - - 0.000 - 0.000 - r - eth_rxc (port) - - - - net (fanout=1) - 0.057 - 0.057 - - eth_rxc - - - IOBD_240_376/DIN - td - 1.254 - 1.311 - r - eth_rxc_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.311 - - eth_rxc_ibuf/ntD - - - IOL_243_374/INCK - td - 0.076 - 1.387 - r - eth_rxc_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.647 - 2.034 - - _N66 - - - IOCKDLY_237_367/CLK_OUT - td - 3.812 - 5.846 - r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT - - - - net (fanout=1) - 2.599 - 8.445 - - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf - - - USCM_84_109/CLK_USCM - td - 0.000 - 8.445 - r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - - - - net (fanout=1861) - 1.585 - 10.030 - - gmii_clk - - - CLMS_214_137/CLK - - - - r - param_manager_inst/modify_H_load/opit_0_L5Q_perm/CLK - - - clock pessimism - - -1.584 - 8.446 - - - - - clock uncertainty - - 0.200 - 8.646 - - - - - Hold time - - -0.221 - 8.425 - - - -
-
-
-
- - 0.401 - 0 - 2 - u_ov5640/coms2_reg_config/u1/sclk/opit_0_inv_L5Q_perm/CLK - u_ov5640/coms2_reg_config/u1/sclk/opit_0_inv_L5Q_perm/L0 - - clk_20k - clk_20k - rise-rise - 0.000 - 9.014 - 9.812 - -0.798 - 0.000 - 0.307 - 0.222 (72.3%) - 0.085 (27.7%) - - Path #27: hold slack is 0.401(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_20k (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 1.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 1.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 2.688 - - _N69 - - - PLL_158_55/CLK_OUT3 - td - 0.105 - 2.793 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT3 - - - - net (fanout=1) - 1.059 - 3.852 - - clk_25m - - - USCM_84_114/CLK_USCM - td - 0.000 - 3.852 - r - clkbufg_7/gopclkbufg/CLKOUT - - - - net (fanout=26) - 1.531 - 5.383 - - ntclkbufg_7 - - - CLMA_182_25/Q1 - tco - 0.229 - 5.612 - r - u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q - - - - net (fanout=3) - 1.871 - 7.483 - - u_ov5640/coms2_reg_config/clk_20k_regdiv - - - USCM_84_120/CLK_USCM - td - 0.000 - 7.483 - r - u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - - - - net (fanout=19) - 1.531 - 9.014 - - u_ov5640/coms2_reg_config/clock_20k - - - CLMS_174_25/CLK - - - - r - u_ov5640/coms2_reg_config/u1/sclk/opit_0_inv_L5Q_perm/CLK - - - CLMS_174_25/Q0 - tco - 0.222 - 9.236 - f - u_ov5640/coms2_reg_config/u1/sclk/opit_0_inv_L5Q_perm/Q - - - - net (fanout=2) - 0.085 - 9.321 - - u_ov5640/coms2_reg_config/u1/sclk - - - CLMS_174_25/A0 - - - - f - u_ov5640/coms2_reg_config/u1/sclk/opit_0_inv_L5Q_perm/L0 - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_20k (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT3 - td - 0.111 - 3.214 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT3 - - - - net (fanout=1) - 1.078 - 4.292 - - clk_25m - - - USCM_84_114/CLK_USCM - td - 0.000 - 4.292 - r - clkbufg_7/gopclkbufg/CLKOUT - - - - net (fanout=26) - 1.585 - 5.877 - - ntclkbufg_7 - - - CLMA_182_25/Q1 - tco - 0.291 - 6.168 - r - u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q - - - - net (fanout=3) - 2.059 - 8.227 - - u_ov5640/coms2_reg_config/clk_20k_regdiv - - - USCM_84_120/CLK_USCM - td - 0.000 - 8.227 - r - u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - - - - net (fanout=19) - 1.585 - 9.812 - - u_ov5640/coms2_reg_config/clock_20k - - - CLMS_174_25/CLK - - - - r - u_ov5640/coms2_reg_config/u1/sclk/opit_0_inv_L5Q_perm/CLK - - - clock pessimism - - -0.798 - 9.014 - - - - - clock uncertainty - - 0.000 - 9.014 - - - - - Hold time - - -0.094 - 8.920 - - - -
-
-
-
- - 0.415 - 0 - 5 - u_ov5640/cmos2_8_16bit/image_data_valid0/opit_0_L5Q_perm/CLK - u_ov5640/u_mix_image/cnt1_w[0]/opit_0_L5Q/CE - - cmos2_pclk - cmos2_pclk - rise-rise - 0.036 - 5.551 - 6.202 - -0.615 - 0.000 - 0.431 - 0.222 (51.5%) - 0.209 (48.5%) - - Path #28: hold slack is 0.415(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock cmos2_pclk (rising edge) - - 0.000 - 0.000 - r - - - - W6 - - 0.000 - 0.000 - r - cmos2_pclk (port) - - - - net (fanout=1) - 0.071 - 0.071 - - cmos2_pclk - - - IOBD_37_0/DIN - td - 1.047 - 1.118 - r - cmos2_pclk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.118 - - cmos2_pclk_ibuf/ntD - - - IOL_39_6/RX_DATA_DD - td - 0.082 - 1.200 - r - cmos2_pclk_ibuf/opit_1/OUT - - - - net (fanout=1) - 2.820 - 4.020 - - nt_cmos2_pclk - - - USCM_84_118/CLK_USCM - td - 0.000 - 4.020 - r - clkbufg_6/gopclkbufg/CLKOUT - - - - net (fanout=118) - 1.531 - 5.551 - - ntclkbufg_6 - - - CLMS_150_41/CLK - - - - r - u_ov5640/cmos2_8_16bit/image_data_valid0/opit_0_L5Q_perm/CLK - - - CLMS_150_41/Q0 - tco - 0.222 - 5.773 - f - u_ov5640/cmos2_8_16bit/image_data_valid0/opit_0_L5Q_perm/Q - - - - net (fanout=5) - 0.209 - 5.982 - - u_ov5640/cmos2_href_16bit - - - CLMA_154_37/CE - - - - f - u_ov5640/u_mix_image/cnt1_w[0]/opit_0_L5Q/CE - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock cmos2_pclk (rising edge) - - 0.000 - 0.000 - r - - - - W6 - - 0.000 - 0.000 - r - cmos2_pclk (port) - - - - net (fanout=1) - 0.071 - 0.071 - - cmos2_pclk - - - IOBD_37_0/DIN - td - 1.254 - 1.325 - r - cmos2_pclk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.325 - - cmos2_pclk_ibuf/ntD - - - IOL_39_6/RX_DATA_DD - td - 0.126 - 1.451 - r - cmos2_pclk_ibuf/opit_1/OUT - - - - net (fanout=1) - 3.166 - 4.617 - - nt_cmos2_pclk - - - USCM_84_118/CLK_USCM - td - 0.000 - 4.617 - r - clkbufg_6/gopclkbufg/CLKOUT - - - - net (fanout=118) - 1.585 - 6.202 - - ntclkbufg_6 - - - CLMA_154_37/CLK - - - - r - u_ov5640/u_mix_image/cnt1_w[0]/opit_0_L5Q/CLK - - - clock pessimism - - -0.615 - 5.587 - - - - - clock uncertainty - - 0.200 - 5.787 - - - - - Hold time - - -0.220 - 5.567 - - - -
-
-
-
- - 0.419 - 0 - 5 - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/L2 - - cmos2_pclk - cmos2_pclk - rise-rise - 0.029 - 5.551 - 6.202 - -0.622 - 0.000 - 0.413 - 0.221 (53.5%) - 0.192 (46.5%) - - Path #29: hold slack is 0.419(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock cmos2_pclk (rising edge) - - 0.000 - 0.000 - r - - - - W6 - - 0.000 - 0.000 - r - cmos2_pclk (port) - - - - net (fanout=1) - 0.071 - 0.071 - - cmos2_pclk - - - IOBD_37_0/DIN - td - 1.047 - 1.118 - r - cmos2_pclk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.118 - - cmos2_pclk_ibuf/ntD - - - IOL_39_6/RX_DATA_DD - td - 0.082 - 1.200 - r - cmos2_pclk_ibuf/opit_1/OUT - - - - net (fanout=1) - 2.820 - 4.020 - - nt_cmos2_pclk - - - USCM_84_118/CLK_USCM - td - 0.000 - 4.020 - r - clkbufg_6/gopclkbufg/CLKOUT - - - - net (fanout=118) - 1.531 - 5.551 - - ntclkbufg_6 - - - CLMA_150_52/CLK - - - - r - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK - - - CLMA_150_52/Q3 - tco - 0.221 - 5.772 - f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/Q1 - - - - net (fanout=5) - 0.192 - 5.964 - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/wr_addr [7] - - - CLMS_150_53/C2 - - - - f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/L2 - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock cmos2_pclk (rising edge) - - 0.000 - 0.000 - r - - - - W6 - - 0.000 - 0.000 - r - cmos2_pclk (port) - - - - net (fanout=1) - 0.071 - 0.071 - - cmos2_pclk - - - IOBD_37_0/DIN - td - 1.254 - 1.325 - r - cmos2_pclk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.325 - - cmos2_pclk_ibuf/ntD - - - IOL_39_6/RX_DATA_DD - td - 0.126 - 1.451 - r - cmos2_pclk_ibuf/opit_1/OUT - - - - net (fanout=1) - 3.166 - 4.617 - - nt_cmos2_pclk - - - USCM_84_118/CLK_USCM - td - 0.000 - 4.617 - r - clkbufg_6/gopclkbufg/CLKOUT - - - - net (fanout=118) - 1.585 - 6.202 - - ntclkbufg_6 - - - CLMS_150_53/CLK - - - - r - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/CLK - - - clock pessimism - - -0.622 - 5.580 - - - - - clock uncertainty - - 0.200 - 5.780 - - - - - Hold time - - -0.235 - 5.545 - - - -
-
-
-
- - 0.424 - 0 - 5 - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm/L2 - - cmos2_pclk - cmos2_pclk - rise-rise - 0.029 - 5.551 - 6.202 - -0.622 - 0.000 - 0.418 - 0.224 (53.6%) - 0.194 (46.4%) - - Path #30: hold slack is 0.424(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock cmos2_pclk (rising edge) - - 0.000 - 0.000 - r - - - - W6 - - 0.000 - 0.000 - r - cmos2_pclk (port) - - - - net (fanout=1) - 0.071 - 0.071 - - cmos2_pclk - - - IOBD_37_0/DIN - td - 1.047 - 1.118 - r - cmos2_pclk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.118 - - cmos2_pclk_ibuf/ntD - - - IOL_39_6/RX_DATA_DD - td - 0.082 - 1.200 - r - cmos2_pclk_ibuf/opit_1/OUT - - - - net (fanout=1) - 2.820 - 4.020 - - nt_cmos2_pclk - - - USCM_84_118/CLK_USCM - td - 0.000 - 4.020 - r - clkbufg_6/gopclkbufg/CLKOUT - - - - net (fanout=118) - 1.531 - 5.551 - - ntclkbufg_6 - - - CLMA_150_48/CLK - - - - r - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK - - - CLMA_150_48/Q1 - tco - 0.224 - 5.775 - f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Q1 - - - - net (fanout=5) - 0.194 - 5.969 - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/wr_addr [1] - - - CLMS_150_49/A2 - - - - f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm/L2 - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock cmos2_pclk (rising edge) - - 0.000 - 0.000 - r - - - - W6 - - 0.000 - 0.000 - r - cmos2_pclk (port) - - - - net (fanout=1) - 0.071 - 0.071 - - cmos2_pclk - - - IOBD_37_0/DIN - td - 1.254 - 1.325 - r - cmos2_pclk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.325 - - cmos2_pclk_ibuf/ntD - - - IOL_39_6/RX_DATA_DD - td - 0.126 - 1.451 - r - cmos2_pclk_ibuf/opit_1/OUT - - - - net (fanout=1) - 3.166 - 4.617 - - nt_cmos2_pclk - - - USCM_84_118/CLK_USCM - td - 0.000 - 4.617 - r - clkbufg_6/gopclkbufg/CLKOUT - - - - net (fanout=118) - 1.585 - 6.202 - - ntclkbufg_6 - - - CLMS_150_49/CLK - - - - r - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm/CLK - - - clock pessimism - - -0.622 - 5.580 - - - - - clock uncertainty - - 0.200 - 5.780 - - - - - Hold time - - -0.235 - 5.545 - - - -
-
-
-
- - 0.450 - 0 - 8 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[0] - - ioclk1 - ioclk1 - rise-rise - 0.035 - 7.041 - 7.712 - -0.636 - 0.000 - 0.421 - 0.421 (100.0%) - 0.000 (0.0%) - - Path #31: hold slack is 0.450(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ioclk1 (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 1.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 1.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 2.688 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.096 - 2.784 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.059 - 3.843 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 3.843 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.665 - 5.508 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.123 - 5.631 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.102 - 6.733 - - clkout0_wl_0 - - - IOCKGATE_6_188/OUT - td - 0.249 - 6.982 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT - - - - net (fanout=28) - 0.059 - 7.041 - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] - - - DQSL_6_152/CLK_IO - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - - - DQSL_6_152/IFIFO_RADDR[0] - tco - 0.421 - 7.462 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[0] - - - - net (fanout=8) - 0.000 - 7.462 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [0] - - - IOL_7_162/IFIFO_RADDR[0] - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[0] - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ioclk1 (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.101 - 3.204 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.078 - 4.282 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 4.282 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.738 - 6.020 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.129 - 6.149 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.121 - 7.270 - - clkout0_wl_0 - - - IOCKGATE_6_188/OUT - td - 0.348 - 7.618 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT - - - - net (fanout=28) - 0.094 - 7.712 - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] - - - IOL_7_162/CLK_IO - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK - - - clock pessimism - - -0.636 - 7.076 - - - - - clock uncertainty - - 0.000 - 7.076 - - - - - Hold time - - -0.064 - 7.012 - - - -
-
-
-
- - 0.450 - 0 - 8 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[1] - - ioclk1 - ioclk1 - rise-rise - 0.035 - 7.041 - 7.712 - -0.636 - 0.000 - 0.421 - 0.421 (100.0%) - 0.000 (0.0%) - - Path #32: hold slack is 0.450(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ioclk1 (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 1.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 1.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 2.688 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.096 - 2.784 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.059 - 3.843 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 3.843 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.665 - 5.508 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.123 - 5.631 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.102 - 6.733 - - clkout0_wl_0 - - - IOCKGATE_6_188/OUT - td - 0.249 - 6.982 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT - - - - net (fanout=28) - 0.059 - 7.041 - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] - - - DQSL_6_152/CLK_IO - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - - - DQSL_6_152/IFIFO_RADDR[1] - tco - 0.421 - 7.462 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[1] - - - - net (fanout=8) - 0.000 - 7.462 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [1] - - - IOL_7_162/IFIFO_RADDR[1] - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[1] - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ioclk1 (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.101 - 3.204 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.078 - 4.282 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 4.282 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.738 - 6.020 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.129 - 6.149 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.121 - 7.270 - - clkout0_wl_0 - - - IOCKGATE_6_188/OUT - td - 0.348 - 7.618 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT - - - - net (fanout=28) - 0.094 - 7.712 - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] - - - IOL_7_162/CLK_IO - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK - - - clock pessimism - - -0.636 - 7.076 - - - - - clock uncertainty - - 0.000 - 7.076 - - - - - Hold time - - -0.064 - 7.012 - - - -
-
-
-
- - 0.450 - 0 - 8 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[2] - - ioclk1 - ioclk1 - rise-rise - 0.035 - 7.041 - 7.712 - -0.636 - 0.000 - 0.421 - 0.421 (100.0%) - 0.000 (0.0%) - - Path #33: hold slack is 0.450(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ioclk1 (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 1.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 1.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 2.688 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.096 - 2.784 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.059 - 3.843 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 3.843 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.665 - 5.508 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.123 - 5.631 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.102 - 6.733 - - clkout0_wl_0 - - - IOCKGATE_6_188/OUT - td - 0.249 - 6.982 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT - - - - net (fanout=28) - 0.059 - 7.041 - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] - - - DQSL_6_152/CLK_IO - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - - - DQSL_6_152/IFIFO_RADDR[2] - tco - 0.421 - 7.462 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[2] - - - - net (fanout=8) - 0.000 - 7.462 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [2] - - - IOL_7_162/IFIFO_RADDR[2] - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[2] - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ioclk1 (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.101 - 3.204 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.078 - 4.282 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 4.282 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.738 - 6.020 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.129 - 6.149 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.121 - 7.270 - - clkout0_wl_0 - - - IOCKGATE_6_188/OUT - td - 0.348 - 7.618 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT - - - - net (fanout=28) - 0.094 - 7.712 - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] - - - IOL_7_162/CLK_IO - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK - - - clock pessimism - - -0.636 - 7.076 - - - - - clock uncertainty - - 0.000 - 7.076 - - - - - Hold time - - -0.064 - 7.012 - - - -
-
-
-
- - 0.450 - 0 - 8 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[0] - - ioclk0 - ioclk0 - rise-rise - 0.035 - 7.041 - 7.712 - -0.636 - 0.000 - 0.421 - 0.421 (100.0%) - 0.000 (0.0%) - - Path #34: hold slack is 0.450(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ioclk0 (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 1.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 1.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 2.688 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.096 - 2.784 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.059 - 3.843 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 3.843 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.665 - 5.508 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.123 - 5.631 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.102 - 6.733 - - clkout0_wl_0 - - - IOCKGATE_6_312/OUT - td - 0.249 - 6.982 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT - - - - net (fanout=11) - 0.059 - 7.041 - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] - - - DQSL_6_276/CLK_IO - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - - - DQSL_6_276/IFIFO_RADDR[0] - tco - 0.421 - 7.462 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[0] - - - - net (fanout=8) - 0.000 - 7.462 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [0] - - - IOL_7_285/IFIFO_RADDR[0] - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[0] - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ioclk0 (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.101 - 3.204 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.078 - 4.282 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 4.282 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.738 - 6.020 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.129 - 6.149 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.121 - 7.270 - - clkout0_wl_0 - - - IOCKGATE_6_312/OUT - td - 0.348 - 7.618 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT - - - - net (fanout=11) - 0.094 - 7.712 - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] - - - IOL_7_285/CLK_IO - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK - - - clock pessimism - - -0.636 - 7.076 - - - - - clock uncertainty - - 0.000 - 7.076 - - - - - Hold time - - -0.064 - 7.012 - - - -
-
-
-
- - 0.450 - 0 - 8 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[1] - - ioclk0 - ioclk0 - rise-rise - 0.035 - 7.041 - 7.712 - -0.636 - 0.000 - 0.421 - 0.421 (100.0%) - 0.000 (0.0%) - - Path #35: hold slack is 0.450(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ioclk0 (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 1.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 1.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 2.688 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.096 - 2.784 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.059 - 3.843 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 3.843 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.665 - 5.508 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.123 - 5.631 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.102 - 6.733 - - clkout0_wl_0 - - - IOCKGATE_6_312/OUT - td - 0.249 - 6.982 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT - - - - net (fanout=11) - 0.059 - 7.041 - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] - - - DQSL_6_276/CLK_IO - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - - - DQSL_6_276/IFIFO_RADDR[1] - tco - 0.421 - 7.462 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[1] - - - - net (fanout=8) - 0.000 - 7.462 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [1] - - - IOL_7_285/IFIFO_RADDR[1] - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[1] - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ioclk0 (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.101 - 3.204 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.078 - 4.282 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 4.282 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.738 - 6.020 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.129 - 6.149 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.121 - 7.270 - - clkout0_wl_0 - - - IOCKGATE_6_312/OUT - td - 0.348 - 7.618 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT - - - - net (fanout=11) - 0.094 - 7.712 - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] - - - IOL_7_285/CLK_IO - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK - - - clock pessimism - - -0.636 - 7.076 - - - - - clock uncertainty - - 0.000 - 7.076 - - - - - Hold time - - -0.064 - 7.012 - - - -
-
-
-
- - 0.450 - 0 - 8 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[2] - - ioclk0 - ioclk0 - rise-rise - 0.035 - 7.041 - 7.712 - -0.636 - 0.000 - 0.421 - 0.421 (100.0%) - 0.000 (0.0%) - - Path #36: hold slack is 0.450(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ioclk0 (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 1.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 1.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 2.688 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.096 - 2.784 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.059 - 3.843 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 3.843 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.665 - 5.508 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.123 - 5.631 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.102 - 6.733 - - clkout0_wl_0 - - - IOCKGATE_6_312/OUT - td - 0.249 - 6.982 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT - - - - net (fanout=11) - 0.059 - 7.041 - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] - - - DQSL_6_276/CLK_IO - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - - - DQSL_6_276/IFIFO_RADDR[2] - tco - 0.421 - 7.462 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[2] - - - - net (fanout=8) - 0.000 - 7.462 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [2] - - - IOL_7_285/IFIFO_RADDR[2] - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[2] - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ioclk0 (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.101 - 3.204 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.078 - 4.282 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 4.282 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.738 - 6.020 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.129 - 6.149 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.121 - 7.270 - - clkout0_wl_0 - - - IOCKGATE_6_312/OUT - td - 0.348 - 7.618 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT - - - - net (fanout=11) - 0.094 - 7.712 - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] - - - IOL_7_285/CLK_IO - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK - - - clock pessimism - - -0.636 - 7.076 - - - - - clock uncertainty - - 0.000 - 7.076 - - - - - Hold time - - -0.064 - 7.012 - - - -
-
-
-
- - 0.575 - 0 - 3 - u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK - u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/D - - clk_25m - clk_25m - rise-rise - 0.000 - 5.383 - 5.877 - -0.494 - 0.000 - 0.561 - 0.229 (40.8%) - 0.332 (59.2%) - - Path #37: hold slack is 0.575(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_25m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 1.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 1.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 2.688 - - _N69 - - - PLL_158_55/CLK_OUT3 - td - 0.105 - 2.793 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT3 - - - - net (fanout=1) - 1.059 - 3.852 - - clk_25m - - - USCM_84_114/CLK_USCM - td - 0.000 - 3.852 - r - clkbufg_7/gopclkbufg/CLKOUT - - - - net (fanout=26) - 1.531 - 5.383 - - ntclkbufg_7 - - - CLMA_182_12/CLK - - - - r - u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK - - - CLMA_182_12/Q1 - tco - 0.229 - 5.612 - r - u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q - - - - net (fanout=3) - 0.332 - 5.944 - - u_ov5640/coms1_reg_config/clk_20k_regdiv - - - CLMA_182_12/M0 - - - - r - u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/D - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_25m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT3 - td - 0.111 - 3.214 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT3 - - - - net (fanout=1) - 1.078 - 4.292 - - clk_25m - - - USCM_84_114/CLK_USCM - td - 0.000 - 4.292 - r - clkbufg_7/gopclkbufg/CLKOUT - - - - net (fanout=26) - 1.585 - 5.877 - - ntclkbufg_7 - - - CLMA_182_12/CLK - - - - r - u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/CLK - - - clock pessimism - - -0.494 - 5.383 - - - - - clock uncertainty - - 0.000 - 5.383 - - - - - Hold time - - -0.014 - 5.369 - - - -
-
-
-
- - 0.711 - 0 - 3 - u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/CLK - u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite/opit_0_inv/D - - clk_25m - clk_25m - rise-rise - 0.000 - 5.383 - 5.877 - -0.494 - 0.000 - 0.697 - 0.229 (32.9%) - 0.468 (67.1%) - - Path #38: hold slack is 0.711(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_25m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 1.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 1.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 2.688 - - _N69 - - - PLL_158_55/CLK_OUT3 - td - 0.105 - 2.793 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT3 - - - - net (fanout=1) - 1.059 - 3.852 - - clk_25m - - - USCM_84_114/CLK_USCM - td - 0.000 - 3.852 - r - clkbufg_7/gopclkbufg/CLKOUT - - - - net (fanout=26) - 1.531 - 5.383 - - ntclkbufg_7 - - - CLMA_182_25/CLK - - - - r - u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/CLK - - - CLMA_182_25/Q1 - tco - 0.229 - 5.612 - r - u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q - - - - net (fanout=3) - 0.468 - 6.080 - - u_ov5640/coms2_reg_config/clk_20k_regdiv - - - CLMA_182_25/M0 - - - - r - u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite/opit_0_inv/D - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_25m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT3 - td - 0.111 - 3.214 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT3 - - - - net (fanout=1) - 1.078 - 4.292 - - clk_25m - - - USCM_84_114/CLK_USCM - td - 0.000 - 4.292 - r - clkbufg_7/gopclkbufg/CLKOUT - - - - net (fanout=26) - 1.585 - 5.877 - - ntclkbufg_7 - - - CLMA_182_25/CLK - - - - r - u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite/opit_0_inv/CLK - - - clock pessimism - - -0.494 - 5.383 - - - - - clock uncertainty - - 0.000 - 5.383 - - - - - Hold time - - -0.014 - 5.369 - - - -
-
-
-
- - 0.742 - 1 - 2 - u_ov5640/coms1_reg_config/clock_20k_cnt[5]/opit_0_inv/CLK - u_ov5640/coms1_reg_config/clock_20k_cnt[5]/opit_0_inv/D - - clk_25m - clk_25m - rise-rise - 0.000 - 5.383 - 5.877 - -0.494 - 0.000 - 0.795 - 0.516 (64.9%) - 0.279 (35.1%) - - Path #39: hold slack is 0.742(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_25m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 1.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 1.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 2.688 - - _N69 - - - PLL_158_55/CLK_OUT3 - td - 0.105 - 2.793 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT3 - - - - net (fanout=1) - 1.059 - 3.852 - - clk_25m - - - USCM_84_114/CLK_USCM - td - 0.000 - 3.852 - r - clkbufg_7/gopclkbufg/CLKOUT - - - - net (fanout=26) - 1.531 - 5.383 - - ntclkbufg_7 - - - CLMA_182_17/CLK - - - - r - u_ov5640/coms1_reg_config/clock_20k_cnt[5]/opit_0_inv/CLK - - - CLMA_182_17/Y0 - tco - 0.284 - 5.667 - f - u_ov5640/coms1_reg_config/clock_20k_cnt[5]/opit_0_inv/Q - - - - net (fanout=2) - 0.086 - 5.753 - - u_ov5640/coms1_reg_config/clock_20k_cnt [5] - - - CLMA_182_16/Y0 - td - 0.232 - 5.985 - f - u_ov5640/coms1_reg_config/N11_2_5/gateop_A2/Y0 - - - - net (fanout=1) - 0.193 - 6.178 - - u_ov5640/coms1_reg_config/N1114 [5] - - - CLMA_182_17/AD - - - - f - u_ov5640/coms1_reg_config/clock_20k_cnt[5]/opit_0_inv/D - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_25m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT3 - td - 0.111 - 3.214 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT3 - - - - net (fanout=1) - 1.078 - 4.292 - - clk_25m - - - USCM_84_114/CLK_USCM - td - 0.000 - 4.292 - r - clkbufg_7/gopclkbufg/CLKOUT - - - - net (fanout=26) - 1.585 - 5.877 - - ntclkbufg_7 - - - CLMA_182_17/CLK - - - - r - u_ov5640/coms1_reg_config/clock_20k_cnt[5]/opit_0_inv/CLK - - - clock pessimism - - -0.494 - 5.383 - - - - - clock uncertainty - - 0.000 - 5.383 - - - - - Hold time - - 0.053 - 5.436 - - - -
-
-
-
- - - - Slack - Logic Levels - High Fanout - Start Point - End Point - Exception - Launch Clock - Capture Clock - Clock Edges - Clock Skew - Launch Clock Delay - Capture Clock Delay - Clock Pessimism Removal - Requirement - Data delay - Logic delay - Route delay - - - 1.103 - 0 - 686 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d1/opit_0_inv/RS - - clk_200m - clk_200m - rise-rise - -0.054 - 5.867 - 5.374 - 0.439 - 5.000 - 3.076 - 0.289 (9.4%) - 2.787 (90.6%) - - Path #1: recovery slack is 1.103(MET) - -
- - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_200m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.101 - 3.204 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.078 - 4.282 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 4.282 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.585 - 5.867 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - CLMA_202_148/CLK - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK - - - CLMA_202_148/Q1 - tco - 0.289 - 6.156 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/Q - - - - net (fanout=686) - 2.787 - 8.943 - - u_axi_ddr_top/I_ipsxb_ddr_top/ddr_rstn - - - CLMS_10_193/RS - - - - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d1/opit_0_inv/RS - -
- - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_200m (rising edge) - - 5.000 - 5.000 - r - - - - P20 - - 0.000 - 5.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 5.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 6.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 6.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 6.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 7.688 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.096 - 7.784 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.059 - 8.843 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 8.843 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.531 - 10.374 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - CLMS_10_193/CLK - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d1/opit_0_inv/CLK - - - clock pessimism - - 0.439 - 10.813 - - - - - clock uncertainty - - -0.150 - 10.663 - - - - - Recovery time - - -0.617 - 10.046 - - - -
-
- -
- - 1.103 - 0 - 686 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d2/opit_0_inv/RS - - clk_200m - clk_200m - rise-rise - -0.054 - 5.867 - 5.374 - 0.439 - 5.000 - 3.076 - 0.289 (9.4%) - 2.787 (90.6%) - - Path #2: recovery slack is 1.103(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_200m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.101 - 3.204 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.078 - 4.282 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 4.282 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.585 - 5.867 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - CLMA_202_148/CLK - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK - - - CLMA_202_148/Q1 - tco - 0.289 - 6.156 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/Q - - - - net (fanout=686) - 2.787 - 8.943 - - u_axi_ddr_top/I_ipsxb_ddr_top/ddr_rstn - - - CLMS_10_193/RS - - - - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d2/opit_0_inv/RS - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_200m (rising edge) - - 5.000 - 5.000 - r - - - - P20 - - 0.000 - 5.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 5.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 6.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 6.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 6.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 7.688 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.096 - 7.784 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.059 - 8.843 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 8.843 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.531 - 10.374 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - CLMS_10_193/CLK - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d2/opit_0_inv/CLK - - - clock pessimism - - 0.439 - 10.813 - - - - - clock uncertainty - - -0.150 - 10.663 - - - - - Recovery time - - -0.617 - 10.046 - - - -
-
-
-
- - 1.191 - 0 - 131 - u_zoom_rst/rst/opit_0_L5Q_perm/CLK - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[8].U_GTP_DRM18K/iGopDrm/RSTA[0] - - clk_200m - clk_200m - rise-rise - 0.067 - 5.867 - 5.495 - 0.439 - 5.000 - 3.611 - 0.287 (7.9%) - 3.324 (92.1%) - - Path #3: recovery slack is 1.191(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_200m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.101 - 3.204 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.078 - 4.282 - - zoom_clk - - - USCM_84_122/CLK_USCM - td - 0.000 - 4.282 - r - USCMROUTE_2/CLKOUT - - - - net (fanout=759) - 1.585 - 5.867 - - ntR3909 - - - CLMS_186_125/CLK - - - - r - u_zoom_rst/rst/opit_0_L5Q_perm/CLK - - - CLMS_186_125/Q0 - tco - 0.287 - 6.154 - f - u_zoom_rst/rst/opit_0_L5Q_perm/Q - - - - net (fanout=131) - 3.324 - 9.478 - - zoom_rst - - - DRM_278_356/RSTA[0] - - - - f - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[8].U_GTP_DRM18K/iGopDrm/RSTA[0] - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_200m (rising edge) - - 5.000 - 5.000 - r - - - - P20 - - 0.000 - 5.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 5.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 6.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 6.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 6.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 7.688 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.096 - 7.784 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.059 - 8.843 - - zoom_clk - - - USCM_84_122/CLK_USCM - td - 0.000 - 8.843 - r - USCMROUTE_2/CLKOUT - - - - net (fanout=759) - 1.652 - 10.495 - - ntR3909 - - - DRM_278_356/CLKA[0] - - - - r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[8].U_GTP_DRM18K/iGopDrm/CLKA[0] - - - clock pessimism - - 0.439 - 10.934 - - - - - clock uncertainty - - -0.150 - 10.784 - - - - - Recovery time - - -0.115 - 10.669 - - - -
-
-
-
- - 5.474 - 17 - 619 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[24]/opit_0_inv/RS - - ddrphy_clkin - ddrphy_clkin - rise-rise - 0.067 - 11.394 - 10.786 - 0.675 - 10.000 - 4.443 - 2.788 (62.8%) - 1.655 (37.2%) - - Path #4: recovery slack is 5.474(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ddrphy_clkin (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.101 - 3.204 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.078 - 4.282 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 4.282 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.738 - 6.020 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.129 - 6.149 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.121 - 7.270 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.348 - 7.618 - r - clkgate_8/gopclkgate/OUT - - - - net (fanout=1) - 0.000 - 7.618 - - ntclkgate_0 - - - IOCKDIV_6_323/CLK_IODIV - td - 0.000 - 7.618 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV - - - - net (fanout=1) - 2.191 - 9.809 - - u_axi_ddr_top/clk - - - USCM_84_116/CLK_USCM - td - 0.000 - 9.809 - r - clkbufg_0/gopclkbufg/CLKOUT - - - - net (fanout=5464) - 1.585 - 11.394 - - ntclkbufg_0 - - - CLMA_70_192/CLK - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK - - - CLMA_70_192/Q0 - tco - 0.289 - 11.683 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q - - - - net (fanout=619) - 1.655 - 13.338 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n - - - CLMA_10_224/RSCO - td - 0.147 - 13.485 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm/RSOUT - - - - net (fanout=4) - 0.000 - 13.485 - - ntR1395 - - - CLMA_10_228/RSCO - td - 0.147 - 13.632 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[4]/opit_0_inv_L5Q_perm/RSOUT - - - - net (fanout=4) - 0.000 - 13.632 - - ntR1394 - - - CLMA_10_232/RSCO - td - 0.147 - 13.779 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/RSOUT - - - - net (fanout=4) - 0.000 - 13.779 - - ntR1393 - - - CLMA_10_236/RSCO - td - 0.147 - 13.926 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[2]/opit_0_inv_L5Q_perm/RSOUT - - - - net (fanout=6) - 0.000 - 13.926 - - ntR1392 - - - CLMA_10_240/RSCO - td - 0.147 - 14.073 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[246]/opit_0_inv/RSOUT - - - - net (fanout=4) - 0.000 - 14.073 - - ntR1391 - - - CLMA_10_244/RSCO - td - 0.147 - 14.220 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q_perm/RSOUT - - - - net (fanout=2) - 0.000 - 14.220 - - ntR1390 - - - CLMA_10_248/RSCO - td - 0.147 - 14.367 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[4]/opit_0_inv_A2Q21/RSOUT - - - - net (fanout=3) - 0.000 - 14.367 - - ntR1389 - - - CLMA_10_252/RSCO - td - 0.147 - 14.514 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/opit_0_inv_AQ_perm/RSOUT - - - - net (fanout=4) - 0.000 - 14.514 - - ntR1388 - - - CLMA_10_256/RSCO - td - 0.147 - 14.661 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/opit_0_inv_L5Q_perm/RSOUT - - - - net (fanout=2) - 0.000 - 14.661 - - ntR1387 - - - CLMA_10_260/RSCO - td - 0.147 - 14.808 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/RSOUT - - - - net (fanout=2) - 0.000 - 14.808 - - ntR1386 - - - CLMA_10_264/RSCO - td - 0.147 - 14.955 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[4]/opit_0_inv_A2Q21/RSOUT - - - - net (fanout=3) - 0.000 - 14.955 - - ntR1385 - - - CLMA_10_268/RSCO - td - 0.147 - 15.102 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/opit_0_inv_AQ/RSOUT - - - - net (fanout=3) - 0.000 - 15.102 - - ntR1384 - - - CLMA_10_272/RSCO - td - 0.147 - 15.249 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs/opit_0_inv/RSOUT - - - - net (fanout=2) - 0.000 - 15.249 - - ntR1383 - - - CLMA_10_276/RSCO - td - 0.147 - 15.396 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[3]/opit_0_inv_A2Q21/RSOUT - - - - net (fanout=2) - 0.000 - 15.396 - - ntR1382 - - - CLMA_10_280/RSCO - td - 0.147 - 15.543 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[7]/opit_0_inv_A2Q21/RSOUT - - - - net (fanout=4) - 0.000 - 15.543 - - ntR1381 - - - CLMA_10_284/RSCO - td - 0.147 - 15.690 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm/RSOUT - - - - net (fanout=4) - 0.000 - 15.690 - - ntR1380 - - - CLMA_10_288/RSCO - td - 0.147 - 15.837 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[223]/opit_0_inv_L5Q_perm/RSOUT - - - - net (fanout=6) - 0.000 - 15.837 - - ntR1379 - - - CLMA_10_292/RSCI - - - - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[24]/opit_0_inv/RS - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ddrphy_clkin (rising edge) - - 10.000 - 10.000 - r - - - - P20 - - 0.000 - 10.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 10.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 11.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 11.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 11.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 12.688 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.096 - 12.784 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.059 - 13.843 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 13.843 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.665 - 15.508 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.123 - 15.631 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.102 - 16.733 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.249 - 16.982 - r - clkgate_8/gopclkgate/OUT - - - - net (fanout=1) - 0.000 - 16.982 - - ntclkgate_0 - - - IOCKDIV_6_323/CLK_IODIV - td - 0.000 - 16.982 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV - - - - net (fanout=1) - 2.152 - 19.134 - - u_axi_ddr_top/clk - - - USCM_84_116/CLK_USCM - td - 0.000 - 19.134 - r - clkbufg_0/gopclkbufg/CLKOUT - - - - net (fanout=5464) - 1.652 - 20.786 - - ntclkbufg_0 - - - CLMA_10_292/CLK - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[24]/opit_0_inv/CLK - - - clock pessimism - - 0.675 - 21.461 - - - - - clock uncertainty - - -0.150 - 21.311 - - - - - Recovery time - - 0.000 - 21.311 - - - -
-
-
-
- - 5.474 - 17 - 619 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[58]/opit_0_inv/RS - - ddrphy_clkin - ddrphy_clkin - rise-rise - 0.067 - 11.394 - 10.786 - 0.675 - 10.000 - 4.443 - 2.788 (62.8%) - 1.655 (37.2%) - - Path #5: recovery slack is 5.474(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ddrphy_clkin (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.101 - 3.204 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.078 - 4.282 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 4.282 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.738 - 6.020 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.129 - 6.149 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.121 - 7.270 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.348 - 7.618 - r - clkgate_8/gopclkgate/OUT - - - - net (fanout=1) - 0.000 - 7.618 - - ntclkgate_0 - - - IOCKDIV_6_323/CLK_IODIV - td - 0.000 - 7.618 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV - - - - net (fanout=1) - 2.191 - 9.809 - - u_axi_ddr_top/clk - - - USCM_84_116/CLK_USCM - td - 0.000 - 9.809 - r - clkbufg_0/gopclkbufg/CLKOUT - - - - net (fanout=5464) - 1.585 - 11.394 - - ntclkbufg_0 - - - CLMA_70_192/CLK - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK - - - CLMA_70_192/Q0 - tco - 0.289 - 11.683 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q - - - - net (fanout=619) - 1.655 - 13.338 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n - - - CLMA_10_224/RSCO - td - 0.147 - 13.485 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm/RSOUT - - - - net (fanout=4) - 0.000 - 13.485 - - ntR1395 - - - CLMA_10_228/RSCO - td - 0.147 - 13.632 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[4]/opit_0_inv_L5Q_perm/RSOUT - - - - net (fanout=4) - 0.000 - 13.632 - - ntR1394 - - - CLMA_10_232/RSCO - td - 0.147 - 13.779 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/RSOUT - - - - net (fanout=4) - 0.000 - 13.779 - - ntR1393 - - - CLMA_10_236/RSCO - td - 0.147 - 13.926 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[2]/opit_0_inv_L5Q_perm/RSOUT - - - - net (fanout=6) - 0.000 - 13.926 - - ntR1392 - - - CLMA_10_240/RSCO - td - 0.147 - 14.073 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[246]/opit_0_inv/RSOUT - - - - net (fanout=4) - 0.000 - 14.073 - - ntR1391 - - - CLMA_10_244/RSCO - td - 0.147 - 14.220 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q_perm/RSOUT - - - - net (fanout=2) - 0.000 - 14.220 - - ntR1390 - - - CLMA_10_248/RSCO - td - 0.147 - 14.367 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[4]/opit_0_inv_A2Q21/RSOUT - - - - net (fanout=3) - 0.000 - 14.367 - - ntR1389 - - - CLMA_10_252/RSCO - td - 0.147 - 14.514 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/opit_0_inv_AQ_perm/RSOUT - - - - net (fanout=4) - 0.000 - 14.514 - - ntR1388 - - - CLMA_10_256/RSCO - td - 0.147 - 14.661 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/opit_0_inv_L5Q_perm/RSOUT - - - - net (fanout=2) - 0.000 - 14.661 - - ntR1387 - - - CLMA_10_260/RSCO - td - 0.147 - 14.808 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/RSOUT - - - - net (fanout=2) - 0.000 - 14.808 - - ntR1386 - - - CLMA_10_264/RSCO - td - 0.147 - 14.955 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[4]/opit_0_inv_A2Q21/RSOUT - - - - net (fanout=3) - 0.000 - 14.955 - - ntR1385 - - - CLMA_10_268/RSCO - td - 0.147 - 15.102 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/opit_0_inv_AQ/RSOUT - - - - net (fanout=3) - 0.000 - 15.102 - - ntR1384 - - - CLMA_10_272/RSCO - td - 0.147 - 15.249 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs/opit_0_inv/RSOUT - - - - net (fanout=2) - 0.000 - 15.249 - - ntR1383 - - - CLMA_10_276/RSCO - td - 0.147 - 15.396 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[3]/opit_0_inv_A2Q21/RSOUT - - - - net (fanout=2) - 0.000 - 15.396 - - ntR1382 - - - CLMA_10_280/RSCO - td - 0.147 - 15.543 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[7]/opit_0_inv_A2Q21/RSOUT - - - - net (fanout=4) - 0.000 - 15.543 - - ntR1381 - - - CLMA_10_284/RSCO - td - 0.147 - 15.690 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm/RSOUT - - - - net (fanout=4) - 0.000 - 15.690 - - ntR1380 - - - CLMA_10_288/RSCO - td - 0.147 - 15.837 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[223]/opit_0_inv_L5Q_perm/RSOUT - - - - net (fanout=6) - 0.000 - 15.837 - - ntR1379 - - - CLMA_10_292/RSCI - - - - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[58]/opit_0_inv/RS - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ddrphy_clkin (rising edge) - - 10.000 - 10.000 - r - - - - P20 - - 0.000 - 10.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 10.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 11.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 11.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 11.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 12.688 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.096 - 12.784 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.059 - 13.843 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 13.843 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.665 - 15.508 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.123 - 15.631 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.102 - 16.733 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.249 - 16.982 - r - clkgate_8/gopclkgate/OUT - - - - net (fanout=1) - 0.000 - 16.982 - - ntclkgate_0 - - - IOCKDIV_6_323/CLK_IODIV - td - 0.000 - 16.982 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV - - - - net (fanout=1) - 2.152 - 19.134 - - u_axi_ddr_top/clk - - - USCM_84_116/CLK_USCM - td - 0.000 - 19.134 - r - clkbufg_0/gopclkbufg/CLKOUT - - - - net (fanout=5464) - 1.652 - 20.786 - - ntclkbufg_0 - - - CLMA_10_292/CLK - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[58]/opit_0_inv/CLK - - - clock pessimism - - 0.675 - 21.461 - - - - - clock uncertainty - - -0.150 - 21.311 - - - - - Recovery time - - 0.000 - 21.311 - - - -
-
-
-
- - 5.474 - 17 - 619 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[60]/opit_0_inv/RS - - ddrphy_clkin - ddrphy_clkin - rise-rise - 0.067 - 11.394 - 10.786 - 0.675 - 10.000 - 4.443 - 2.788 (62.8%) - 1.655 (37.2%) - - Path #6: recovery slack is 5.474(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ddrphy_clkin (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.101 - 3.204 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.078 - 4.282 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 4.282 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.738 - 6.020 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.129 - 6.149 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.121 - 7.270 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.348 - 7.618 - r - clkgate_8/gopclkgate/OUT - - - - net (fanout=1) - 0.000 - 7.618 - - ntclkgate_0 - - - IOCKDIV_6_323/CLK_IODIV - td - 0.000 - 7.618 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV - - - - net (fanout=1) - 2.191 - 9.809 - - u_axi_ddr_top/clk - - - USCM_84_116/CLK_USCM - td - 0.000 - 9.809 - r - clkbufg_0/gopclkbufg/CLKOUT - - - - net (fanout=5464) - 1.585 - 11.394 - - ntclkbufg_0 - - - CLMA_70_192/CLK - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK - - - CLMA_70_192/Q0 - tco - 0.289 - 11.683 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q - - - - net (fanout=619) - 1.655 - 13.338 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n - - - CLMA_10_224/RSCO - td - 0.147 - 13.485 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm/RSOUT - - - - net (fanout=4) - 0.000 - 13.485 - - ntR1395 - - - CLMA_10_228/RSCO - td - 0.147 - 13.632 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[4]/opit_0_inv_L5Q_perm/RSOUT - - - - net (fanout=4) - 0.000 - 13.632 - - ntR1394 - - - CLMA_10_232/RSCO - td - 0.147 - 13.779 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/RSOUT - - - - net (fanout=4) - 0.000 - 13.779 - - ntR1393 - - - CLMA_10_236/RSCO - td - 0.147 - 13.926 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[2]/opit_0_inv_L5Q_perm/RSOUT - - - - net (fanout=6) - 0.000 - 13.926 - - ntR1392 - - - CLMA_10_240/RSCO - td - 0.147 - 14.073 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[246]/opit_0_inv/RSOUT - - - - net (fanout=4) - 0.000 - 14.073 - - ntR1391 - - - CLMA_10_244/RSCO - td - 0.147 - 14.220 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q_perm/RSOUT - - - - net (fanout=2) - 0.000 - 14.220 - - ntR1390 - - - CLMA_10_248/RSCO - td - 0.147 - 14.367 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[4]/opit_0_inv_A2Q21/RSOUT - - - - net (fanout=3) - 0.000 - 14.367 - - ntR1389 - - - CLMA_10_252/RSCO - td - 0.147 - 14.514 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/opit_0_inv_AQ_perm/RSOUT - - - - net (fanout=4) - 0.000 - 14.514 - - ntR1388 - - - CLMA_10_256/RSCO - td - 0.147 - 14.661 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/opit_0_inv_L5Q_perm/RSOUT - - - - net (fanout=2) - 0.000 - 14.661 - - ntR1387 - - - CLMA_10_260/RSCO - td - 0.147 - 14.808 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/RSOUT - - - - net (fanout=2) - 0.000 - 14.808 - - ntR1386 - - - CLMA_10_264/RSCO - td - 0.147 - 14.955 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[4]/opit_0_inv_A2Q21/RSOUT - - - - net (fanout=3) - 0.000 - 14.955 - - ntR1385 - - - CLMA_10_268/RSCO - td - 0.147 - 15.102 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/opit_0_inv_AQ/RSOUT - - - - net (fanout=3) - 0.000 - 15.102 - - ntR1384 - - - CLMA_10_272/RSCO - td - 0.147 - 15.249 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs/opit_0_inv/RSOUT - - - - net (fanout=2) - 0.000 - 15.249 - - ntR1383 - - - CLMA_10_276/RSCO - td - 0.147 - 15.396 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[3]/opit_0_inv_A2Q21/RSOUT - - - - net (fanout=2) - 0.000 - 15.396 - - ntR1382 - - - CLMA_10_280/RSCO - td - 0.147 - 15.543 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[7]/opit_0_inv_A2Q21/RSOUT - - - - net (fanout=4) - 0.000 - 15.543 - - ntR1381 - - - CLMA_10_284/RSCO - td - 0.147 - 15.690 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm/RSOUT - - - - net (fanout=4) - 0.000 - 15.690 - - ntR1380 - - - CLMA_10_288/RSCO - td - 0.147 - 15.837 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[223]/opit_0_inv_L5Q_perm/RSOUT - - - - net (fanout=6) - 0.000 - 15.837 - - ntR1379 - - - CLMA_10_292/RSCI - - - - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[60]/opit_0_inv/RS - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ddrphy_clkin (rising edge) - - 10.000 - 10.000 - r - - - - P20 - - 0.000 - 10.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 10.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 11.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 11.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 11.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 12.688 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.096 - 12.784 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.059 - 13.843 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 13.843 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.665 - 15.508 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.123 - 15.631 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.102 - 16.733 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.249 - 16.982 - r - clkgate_8/gopclkgate/OUT - - - - net (fanout=1) - 0.000 - 16.982 - - ntclkgate_0 - - - IOCKDIV_6_323/CLK_IODIV - td - 0.000 - 16.982 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV - - - - net (fanout=1) - 2.152 - 19.134 - - u_axi_ddr_top/clk - - - USCM_84_116/CLK_USCM - td - 0.000 - 19.134 - r - clkbufg_0/gopclkbufg/CLKOUT - - - - net (fanout=5464) - 1.652 - 20.786 - - ntclkbufg_0 - - - CLMA_10_292/CLK - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[60]/opit_0_inv/CLK - - - clock pessimism - - 0.675 - 21.461 - - - - - clock uncertainty - - -0.150 - 21.311 - - - - - Recovery time - - 0.000 - 21.311 - - - -
-
-
-
- - 8.580 - 10 - 1066 - sync_vg_100m/opit_0_inv_L5Q_perm/CLK - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[4]/opit_0_L5Q_perm/RS - - clk_720p60Hz - clk_720p60Hz - rise-rise - -0.054 - 9.434 - 8.831 - 0.549 - 13.473 - 4.689 - 1.757 (37.5%) - 2.932 (62.5%) - - Path #7: recovery slack is 8.580(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_720p60Hz (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.107 - 3.210 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.078 - 4.288 - - rd3_clk - - - USCM_84_154/CLK_USCM - td - 0.000 - 4.288 - r - USCMROUTE_0/CLKOUT - - - - net (fanout=1) - 1.861 - 6.149 - - ntR3907 - - - PLL_158_303/CLK_OUT1 - td - 0.101 - 6.250 - r - U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.599 - 7.849 - - nt_pix_clk - - - USCM_84_117/CLK_USCM - td - 0.000 - 7.849 - r - clkbufg_2/gopclkbufg/CLKOUT - - - - net (fanout=1635) - 1.585 - 9.434 - - ntclkbufg_2 - - - CLMS_150_245/CLK - - - - r - sync_vg_100m/opit_0_inv_L5Q_perm/CLK - - - CLMS_150_245/Q0 - tco - 0.287 - 9.721 - f - sync_vg_100m/opit_0_inv_L5Q_perm/Q - - - - net (fanout=1066) - 2.932 - 12.653 - - sync_vg_100m - - - CLMA_294_132/RSCO - td - 0.147 - 12.800 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/remainder[3]/opit_0_L5Q_perm/RSOUT - - - - net (fanout=4) - 0.000 - 12.800 - - ntR491 - - - CLMA_294_136/RSCO - td - 0.147 - 12.947 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm/RSOUT - - - - net (fanout=4) - 0.000 - 12.947 - - ntR490 - - - CLMA_294_140/RSCO - td - 0.147 - 13.094 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[2]/opit_0_L5Q_perm/RSOUT - - - - net (fanout=1) - 0.000 - 13.094 - - ntR489 - - - CLMA_294_144/RSCO - td - 0.147 - 13.241 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/remainder[2]/opit_0_A2Q21/RSOUT - - - - net (fanout=2) - 0.000 - 13.241 - - ntR488 - - - CLMA_294_148/RSCO - td - 0.147 - 13.388 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/remainder[6]/opit_0_A2Q21/RSOUT - - - - net (fanout=4) - 0.000 - 13.388 - - ntR487 - - - CLMA_294_152/RSCO - td - 0.147 - 13.535 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm/RSOUT - - - - net (fanout=4) - 0.000 - 13.535 - - ntR486 - - - CLMA_294_156/RSCO - td - 0.147 - 13.682 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/dividend_kp[11]/opit_0_L5Q_perm/RSOUT - - - - net (fanout=4) - 0.000 - 13.682 - - ntR485 - - - CLMA_294_160/RSCO - td - 0.147 - 13.829 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[2]/opit_0_L5Q_perm/RSOUT - - - - net (fanout=2) - 0.000 - 13.829 - - ntR484 - - - CLMA_294_164/RSCO - td - 0.147 - 13.976 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[2]/opit_0_A2Q21/RSOUT - - - - net (fanout=2) - 0.000 - 13.976 - - ntR483 - - - CLMA_294_168/RSCO - td - 0.147 - 14.123 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[6]/opit_0_A2Q21/RSOUT - - - - net (fanout=4) - 0.000 - 14.123 - - ntR482 - - - CLMA_294_172/RSCI - - - - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[4]/opit_0_L5Q_perm/RS - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_720p60Hz (rising edge) - - 13.473 - 13.473 - r - - - - P20 - - 0.000 - 13.473 - r - clk (port) - - - - net (fanout=1) - 0.074 - 13.547 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 15.355 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 15.355 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 15.403 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 16.161 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.100 - 16.261 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.059 - 17.320 - - rd3_clk - - - USCM_84_154/CLK_USCM - td - 0.000 - 17.320 - r - USCMROUTE_0/CLKOUT - - - - net (fanout=1) - 1.786 - 19.106 - - ntR3907 - - - PLL_158_303/CLK_OUT1 - td - 0.096 - 19.202 - r - U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.571 - 20.773 - - nt_pix_clk - - - USCM_84_117/CLK_USCM - td - 0.000 - 20.773 - r - clkbufg_2/gopclkbufg/CLKOUT - - - - net (fanout=1635) - 1.531 - 22.304 - - ntclkbufg_2 - - - CLMA_294_172/CLK - - - - r - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[4]/opit_0_L5Q_perm/CLK - - - clock pessimism - - 0.549 - 22.853 - - - - - clock uncertainty - - -0.150 - 22.703 - - - - - Recovery time - - 0.000 - 22.703 - - - -
-
-
-
- - 8.580 - 10 - 1066 - sync_vg_100m/opit_0_inv_L5Q_perm/CLK - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[6]/opit_0_L5Q_perm/RS - - clk_720p60Hz - clk_720p60Hz - rise-rise - -0.054 - 9.434 - 8.831 - 0.549 - 13.473 - 4.689 - 1.757 (37.5%) - 2.932 (62.5%) - - Path #8: recovery slack is 8.580(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_720p60Hz (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.107 - 3.210 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.078 - 4.288 - - rd3_clk - - - USCM_84_154/CLK_USCM - td - 0.000 - 4.288 - r - USCMROUTE_0/CLKOUT - - - - net (fanout=1) - 1.861 - 6.149 - - ntR3907 - - - PLL_158_303/CLK_OUT1 - td - 0.101 - 6.250 - r - U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.599 - 7.849 - - nt_pix_clk - - - USCM_84_117/CLK_USCM - td - 0.000 - 7.849 - r - clkbufg_2/gopclkbufg/CLKOUT - - - - net (fanout=1635) - 1.585 - 9.434 - - ntclkbufg_2 - - - CLMS_150_245/CLK - - - - r - sync_vg_100m/opit_0_inv_L5Q_perm/CLK - - - CLMS_150_245/Q0 - tco - 0.287 - 9.721 - f - sync_vg_100m/opit_0_inv_L5Q_perm/Q - - - - net (fanout=1066) - 2.932 - 12.653 - - sync_vg_100m - - - CLMA_294_132/RSCO - td - 0.147 - 12.800 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/remainder[3]/opit_0_L5Q_perm/RSOUT - - - - net (fanout=4) - 0.000 - 12.800 - - ntR491 - - - CLMA_294_136/RSCO - td - 0.147 - 12.947 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm/RSOUT - - - - net (fanout=4) - 0.000 - 12.947 - - ntR490 - - - CLMA_294_140/RSCO - td - 0.147 - 13.094 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[2]/opit_0_L5Q_perm/RSOUT - - - - net (fanout=1) - 0.000 - 13.094 - - ntR489 - - - CLMA_294_144/RSCO - td - 0.147 - 13.241 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/remainder[2]/opit_0_A2Q21/RSOUT - - - - net (fanout=2) - 0.000 - 13.241 - - ntR488 - - - CLMA_294_148/RSCO - td - 0.147 - 13.388 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/remainder[6]/opit_0_A2Q21/RSOUT - - - - net (fanout=4) - 0.000 - 13.388 - - ntR487 - - - CLMA_294_152/RSCO - td - 0.147 - 13.535 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm/RSOUT - - - - net (fanout=4) - 0.000 - 13.535 - - ntR486 - - - CLMA_294_156/RSCO - td - 0.147 - 13.682 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/dividend_kp[11]/opit_0_L5Q_perm/RSOUT - - - - net (fanout=4) - 0.000 - 13.682 - - ntR485 - - - CLMA_294_160/RSCO - td - 0.147 - 13.829 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[2]/opit_0_L5Q_perm/RSOUT - - - - net (fanout=2) - 0.000 - 13.829 - - ntR484 - - - CLMA_294_164/RSCO - td - 0.147 - 13.976 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[2]/opit_0_A2Q21/RSOUT - - - - net (fanout=2) - 0.000 - 13.976 - - ntR483 - - - CLMA_294_168/RSCO - td - 0.147 - 14.123 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[6]/opit_0_A2Q21/RSOUT - - - - net (fanout=4) - 0.000 - 14.123 - - ntR482 - - - CLMA_294_172/RSCI - - - - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[6]/opit_0_L5Q_perm/RS - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_720p60Hz (rising edge) - - 13.473 - 13.473 - r - - - - P20 - - 0.000 - 13.473 - r - clk (port) - - - - net (fanout=1) - 0.074 - 13.547 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 15.355 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 15.355 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 15.403 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 16.161 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.100 - 16.261 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.059 - 17.320 - - rd3_clk - - - USCM_84_154/CLK_USCM - td - 0.000 - 17.320 - r - USCMROUTE_0/CLKOUT - - - - net (fanout=1) - 1.786 - 19.106 - - ntR3907 - - - PLL_158_303/CLK_OUT1 - td - 0.096 - 19.202 - r - U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.571 - 20.773 - - nt_pix_clk - - - USCM_84_117/CLK_USCM - td - 0.000 - 20.773 - r - clkbufg_2/gopclkbufg/CLKOUT - - - - net (fanout=1635) - 1.531 - 22.304 - - ntclkbufg_2 - - - CLMA_294_172/CLK - - - - r - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[6]/opit_0_L5Q_perm/CLK - - - clock pessimism - - 0.549 - 22.853 - - - - - clock uncertainty - - -0.150 - 22.703 - - - - - Recovery time - - 0.000 - 22.703 - - - -
-
-
-
- - 8.580 - 10 - 1066 - sync_vg_100m/opit_0_inv_L5Q_perm/CLK - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[7]/opit_0_L5Q_perm/RS - - clk_720p60Hz - clk_720p60Hz - rise-rise - -0.054 - 9.434 - 8.831 - 0.549 - 13.473 - 4.689 - 1.757 (37.5%) - 2.932 (62.5%) - - Path #9: recovery slack is 8.580(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_720p60Hz (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.107 - 3.210 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.078 - 4.288 - - rd3_clk - - - USCM_84_154/CLK_USCM - td - 0.000 - 4.288 - r - USCMROUTE_0/CLKOUT - - - - net (fanout=1) - 1.861 - 6.149 - - ntR3907 - - - PLL_158_303/CLK_OUT1 - td - 0.101 - 6.250 - r - U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.599 - 7.849 - - nt_pix_clk - - - USCM_84_117/CLK_USCM - td - 0.000 - 7.849 - r - clkbufg_2/gopclkbufg/CLKOUT - - - - net (fanout=1635) - 1.585 - 9.434 - - ntclkbufg_2 - - - CLMS_150_245/CLK - - - - r - sync_vg_100m/opit_0_inv_L5Q_perm/CLK - - - CLMS_150_245/Q0 - tco - 0.287 - 9.721 - f - sync_vg_100m/opit_0_inv_L5Q_perm/Q - - - - net (fanout=1066) - 2.932 - 12.653 - - sync_vg_100m - - - CLMA_294_132/RSCO - td - 0.147 - 12.800 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/remainder[3]/opit_0_L5Q_perm/RSOUT - - - - net (fanout=4) - 0.000 - 12.800 - - ntR491 - - - CLMA_294_136/RSCO - td - 0.147 - 12.947 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm/RSOUT - - - - net (fanout=4) - 0.000 - 12.947 - - ntR490 - - - CLMA_294_140/RSCO - td - 0.147 - 13.094 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[2]/opit_0_L5Q_perm/RSOUT - - - - net (fanout=1) - 0.000 - 13.094 - - ntR489 - - - CLMA_294_144/RSCO - td - 0.147 - 13.241 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/remainder[2]/opit_0_A2Q21/RSOUT - - - - net (fanout=2) - 0.000 - 13.241 - - ntR488 - - - CLMA_294_148/RSCO - td - 0.147 - 13.388 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/remainder[6]/opit_0_A2Q21/RSOUT - - - - net (fanout=4) - 0.000 - 13.388 - - ntR487 - - - CLMA_294_152/RSCO - td - 0.147 - 13.535 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm/RSOUT - - - - net (fanout=4) - 0.000 - 13.535 - - ntR486 - - - CLMA_294_156/RSCO - td - 0.147 - 13.682 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/dividend_kp[11]/opit_0_L5Q_perm/RSOUT - - - - net (fanout=4) - 0.000 - 13.682 - - ntR485 - - - CLMA_294_160/RSCO - td - 0.147 - 13.829 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[2]/opit_0_L5Q_perm/RSOUT - - - - net (fanout=2) - 0.000 - 13.829 - - ntR484 - - - CLMA_294_164/RSCO - td - 0.147 - 13.976 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[2]/opit_0_A2Q21/RSOUT - - - - net (fanout=2) - 0.000 - 13.976 - - ntR483 - - - CLMA_294_168/RSCO - td - 0.147 - 14.123 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[6]/opit_0_A2Q21/RSOUT - - - - net (fanout=4) - 0.000 - 14.123 - - ntR482 - - - CLMA_294_172/RSCI - - - - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[7]/opit_0_L5Q_perm/RS - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_720p60Hz (rising edge) - - 13.473 - 13.473 - r - - - - P20 - - 0.000 - 13.473 - r - clk (port) - - - - net (fanout=1) - 0.074 - 13.547 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 15.355 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 15.355 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 15.403 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 16.161 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.100 - 16.261 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.059 - 17.320 - - rd3_clk - - - USCM_84_154/CLK_USCM - td - 0.000 - 17.320 - r - USCMROUTE_0/CLKOUT - - - - net (fanout=1) - 1.786 - 19.106 - - ntR3907 - - - PLL_158_303/CLK_OUT1 - td - 0.096 - 19.202 - r - U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.571 - 20.773 - - nt_pix_clk - - - USCM_84_117/CLK_USCM - td - 0.000 - 20.773 - r - clkbufg_2/gopclkbufg/CLKOUT - - - - net (fanout=1635) - 1.531 - 22.304 - - ntclkbufg_2 - - - CLMA_294_172/CLK - - - - r - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[7]/opit_0_L5Q_perm/CLK - - - clock pessimism - - 0.549 - 22.853 - - - - - clock uncertainty - - -0.150 - 22.703 - - - - - Recovery time - - 0.000 - 22.703 - - - -
-
-
-
- - 16.039 - 7 - 573 - u_clk50m_rst/rst/opit_0_L5Q_perm/CLK - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/RS - - clk_50m - clk_50m - rise-rise - -0.054 - 5.873 - 5.378 - 0.441 - 20.000 - 3.757 - 1.316 (35.0%) - 2.441 (65.0%) - - Path #10: recovery slack is 16.039(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_50m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.107 - 3.210 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.078 - 4.288 - - rd3_clk - - - USCM_84_108/CLK_USCM - td - 0.000 - 4.288 - r - clkbufg_1/gopclkbufg/CLKOUT - - - - net (fanout=2517) - 1.585 - 5.873 - - ntclkbufg_1 - - - CLMS_94_177/CLK - - - - r - u_clk50m_rst/rst/opit_0_L5Q_perm/CLK - - - CLMS_94_177/Q0 - tco - 0.287 - 6.160 - f - u_clk50m_rst/rst/opit_0_L5Q_perm/Q - - - - net (fanout=573) - 2.441 - 8.601 - - rd3_rst - - - CLMS_146_37/RSCO - td - 0.147 - 8.748 - f - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/RSOUT - - - - net (fanout=4) - 0.000 - 8.748 - - ntR414 - - - CLMS_146_41/RSCO - td - 0.147 - 8.895 - f - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/RSOUT - - - - net (fanout=4) - 0.000 - 8.895 - - ntR413 - - - CLMS_146_45/RSCO - td - 0.147 - 9.042 - f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/RSOUT - - - - net (fanout=3) - 0.000 - 9.042 - - ntR412 - - - CLMS_146_49/RSCO - td - 0.147 - 9.189 - f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/RSOUT - - - - net (fanout=2) - 0.000 - 9.189 - - ntR411 - - - CLMS_146_53/RSCO - td - 0.147 - 9.336 - f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/RSOUT - - - - net (fanout=4) - 0.000 - 9.336 - - ntR410 - - - CLMS_146_57/RSCO - td - 0.147 - 9.483 - f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/RSOUT - - - - net (fanout=6) - 0.000 - 9.483 - - ntR409 - - - CLMS_146_61/RSCO - td - 0.147 - 9.630 - f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/RSOUT - - - - net (fanout=5) - 0.000 - 9.630 - - ntR408 - - - CLMS_146_69/RSCI - - - - f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/RS - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_50m (rising edge) - - 20.000 - 20.000 - r - - - - P20 - - 0.000 - 20.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 20.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 21.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 21.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 21.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 22.688 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.100 - 22.788 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.059 - 23.847 - - rd3_clk - - - USCM_84_108/CLK_USCM - td - 0.000 - 23.847 - r - clkbufg_1/gopclkbufg/CLKOUT - - - - net (fanout=2517) - 1.531 - 25.378 - - ntclkbufg_1 - - - CLMS_146_69/CLK - - - - r - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/CLK - - - clock pessimism - - 0.441 - 25.819 - - - - - clock uncertainty - - -0.150 - 25.669 - - - - - Recovery time - - 0.000 - 25.669 - - - -
-
-
-
- - 16.039 - 7 - 573 - u_clk50m_rst/rst/opit_0_L5Q_perm/CLK - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/RS - - clk_50m - clk_50m - rise-rise - -0.054 - 5.873 - 5.378 - 0.441 - 20.000 - 3.757 - 1.316 (35.0%) - 2.441 (65.0%) - - Path #11: recovery slack is 16.039(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_50m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.107 - 3.210 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.078 - 4.288 - - rd3_clk - - - USCM_84_108/CLK_USCM - td - 0.000 - 4.288 - r - clkbufg_1/gopclkbufg/CLKOUT - - - - net (fanout=2517) - 1.585 - 5.873 - - ntclkbufg_1 - - - CLMS_94_177/CLK - - - - r - u_clk50m_rst/rst/opit_0_L5Q_perm/CLK - - - CLMS_94_177/Q0 - tco - 0.287 - 6.160 - f - u_clk50m_rst/rst/opit_0_L5Q_perm/Q - - - - net (fanout=573) - 2.441 - 8.601 - - rd3_rst - - - CLMS_146_37/RSCO - td - 0.147 - 8.748 - f - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/RSOUT - - - - net (fanout=4) - 0.000 - 8.748 - - ntR414 - - - CLMS_146_41/RSCO - td - 0.147 - 8.895 - f - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/RSOUT - - - - net (fanout=4) - 0.000 - 8.895 - - ntR413 - - - CLMS_146_45/RSCO - td - 0.147 - 9.042 - f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/RSOUT - - - - net (fanout=3) - 0.000 - 9.042 - - ntR412 - - - CLMS_146_49/RSCO - td - 0.147 - 9.189 - f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/RSOUT - - - - net (fanout=2) - 0.000 - 9.189 - - ntR411 - - - CLMS_146_53/RSCO - td - 0.147 - 9.336 - f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/RSOUT - - - - net (fanout=4) - 0.000 - 9.336 - - ntR410 - - - CLMS_146_57/RSCO - td - 0.147 - 9.483 - f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/RSOUT - - - - net (fanout=6) - 0.000 - 9.483 - - ntR409 - - - CLMS_146_61/RSCO - td - 0.147 - 9.630 - f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/RSOUT - - - - net (fanout=5) - 0.000 - 9.630 - - ntR408 - - - CLMS_146_69/RSCI - - - - f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/RS - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_50m (rising edge) - - 20.000 - 20.000 - r - - - - P20 - - 0.000 - 20.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 20.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 21.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 21.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 21.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 22.688 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.100 - 22.788 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.059 - 23.847 - - rd3_clk - - - USCM_84_108/CLK_USCM - td - 0.000 - 23.847 - r - clkbufg_1/gopclkbufg/CLKOUT - - - - net (fanout=2517) - 1.531 - 25.378 - - ntclkbufg_1 - - - CLMS_146_69/CLK - - - - r - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/CLK - - - clock pessimism - - 0.441 - 25.819 - - - - - clock uncertainty - - -0.150 - 25.669 - - - - - Recovery time - - 0.000 - 25.669 - - - -
-
-
-
- - 16.039 - 7 - 573 - u_clk50m_rst/rst/opit_0_L5Q_perm/CLK - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/opit_0/RS - - clk_50m - clk_50m - rise-rise - -0.054 - 5.873 - 5.378 - 0.441 - 20.000 - 3.757 - 1.316 (35.0%) - 2.441 (65.0%) - - Path #12: recovery slack is 16.039(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_50m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.107 - 3.210 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.078 - 4.288 - - rd3_clk - - - USCM_84_108/CLK_USCM - td - 0.000 - 4.288 - r - clkbufg_1/gopclkbufg/CLKOUT - - - - net (fanout=2517) - 1.585 - 5.873 - - ntclkbufg_1 - - - CLMS_94_177/CLK - - - - r - u_clk50m_rst/rst/opit_0_L5Q_perm/CLK - - - CLMS_94_177/Q0 - tco - 0.287 - 6.160 - f - u_clk50m_rst/rst/opit_0_L5Q_perm/Q - - - - net (fanout=573) - 2.441 - 8.601 - - rd3_rst - - - CLMS_146_37/RSCO - td - 0.147 - 8.748 - f - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/RSOUT - - - - net (fanout=4) - 0.000 - 8.748 - - ntR414 - - - CLMS_146_41/RSCO - td - 0.147 - 8.895 - f - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/RSOUT - - - - net (fanout=4) - 0.000 - 8.895 - - ntR413 - - - CLMS_146_45/RSCO - td - 0.147 - 9.042 - f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/RSOUT - - - - net (fanout=3) - 0.000 - 9.042 - - ntR412 - - - CLMS_146_49/RSCO - td - 0.147 - 9.189 - f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/RSOUT - - - - net (fanout=2) - 0.000 - 9.189 - - ntR411 - - - CLMS_146_53/RSCO - td - 0.147 - 9.336 - f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/RSOUT - - - - net (fanout=4) - 0.000 - 9.336 - - ntR410 - - - CLMS_146_57/RSCO - td - 0.147 - 9.483 - f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/RSOUT - - - - net (fanout=6) - 0.000 - 9.483 - - ntR409 - - - CLMS_146_61/RSCO - td - 0.147 - 9.630 - f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/RSOUT - - - - net (fanout=5) - 0.000 - 9.630 - - ntR408 - - - CLMS_146_69/RSCI - - - - f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/opit_0/RS - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_50m (rising edge) - - 20.000 - 20.000 - r - - - - P20 - - 0.000 - 20.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 20.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 21.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 21.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 21.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 22.688 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.100 - 22.788 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.059 - 23.847 - - rd3_clk - - - USCM_84_108/CLK_USCM - td - 0.000 - 23.847 - r - clkbufg_1/gopclkbufg/CLKOUT - - - - net (fanout=2517) - 1.531 - 25.378 - - ntclkbufg_1 - - - CLMS_146_69/CLK - - - - r - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/opit_0/CLK - - - clock pessimism - - 0.441 - 25.819 - - - - - clock uncertainty - - -0.150 - 25.669 - - - - - Recovery time - - 0.000 - 25.669 - - - -
-
-
-
- - 97.793 - 0 - 3 - rstn_out1/opit_0_inv/CLK - ms72xx_ctl/rstn_temp1/opit_0_inv/RS - - clk_10m - clk_10m - rise-rise - -0.036 - 5.873 - 5.378 - 0.459 - 100.000 - 1.404 - 0.286 (20.4%) - 1.118 (79.6%) - - Path #13: recovery slack is 97.793(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_10m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT4 - td - 0.107 - 3.210 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT4 - - - - net (fanout=1) - 1.078 - 4.288 - - clk_10m - - - USCM_84_110/CLK_USCM - td - 0.000 - 4.288 - r - clkbufg_3/gopclkbufg/CLKOUT - - - - net (fanout=235) - 1.585 - 5.873 - - ntclkbufg_3 - - - CLMA_230_69/CLK - - - - r - rstn_out1/opit_0_inv/CLK - - - CLMA_230_69/Q3 - tco - 0.286 - 6.159 - f - rstn_out1/opit_0_inv/Q - - - - net (fanout=3) - 1.118 - 7.277 - - nt_eth_rstn - - - CLMA_246_120/RS - - - - f - ms72xx_ctl/rstn_temp1/opit_0_inv/RS - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_10m (rising edge) - - 100.000 - 100.000 - r - - - - P20 - - 0.000 - 100.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 100.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 101.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 101.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 101.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 102.688 - - _N69 - - - PLL_158_55/CLK_OUT4 - td - 0.100 - 102.788 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT4 - - - - net (fanout=1) - 1.059 - 103.847 - - clk_10m - - - USCM_84_110/CLK_USCM - td - 0.000 - 103.847 - r - clkbufg_3/gopclkbufg/CLKOUT - - - - net (fanout=235) - 1.531 - 105.378 - - ntclkbufg_3 - - - CLMA_246_120/CLK - - - - r - ms72xx_ctl/rstn_temp1/opit_0_inv/CLK - - - clock pessimism - - 0.459 - 105.837 - - - - - clock uncertainty - - -0.150 - 105.687 - - - - - Recovery time - - -0.617 - 105.070 - - - -
-
-
-
- - - - Slack - Logic Levels - High Fanout - Start Point - End Point - Exception - Launch Clock - Capture Clock - Clock Edges - Clock Skew - Launch Clock Delay - Capture Clock Delay - Clock Pessimism Removal - Requirement - Data delay - Logic delay - Route delay - - - 0.554 - 0 - 2 - u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/opit_0/RS - - clk_200m - clk_200m - rise-rise - 0.067 - 5.374 - 5.867 - -0.426 - 0.000 - 0.401 - 0.222 (55.4%) - 0.179 (44.6%) - - Path #1: removal slack is 0.554(MET) - -
- - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_200m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 1.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 1.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 2.688 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.096 - 2.784 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.059 - 3.843 - - zoom_clk - - - USCM_84_122/CLK_USCM - td - 0.000 - 3.843 - r - USCMROUTE_2/CLKOUT - - - - net (fanout=759) - 1.531 - 5.374 - - ntR3909 - - - CLMS_202_149/CLK - - - - r - u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK - - - CLMS_202_149/Q0 - tco - 0.222 - 5.596 - f - u_ddr_rst/rst/opit_0_inv_L5Q_perm/Q - - - - net (fanout=2) - 0.179 - 5.775 - - ddr_rst - - - CLMA_202_148/RS - - - - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/opit_0/RS - -
- - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_200m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.101 - 3.204 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.078 - 4.282 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 4.282 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.585 - 5.867 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - CLMA_202_148/CLK - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/opit_0/CLK - - - clock pessimism - - -0.426 - 5.441 - - - - - clock uncertainty - - 0.000 - 5.441 - - - - - Removal time - - -0.220 - 5.221 - - - -
-
- -
- - 0.554 - 0 - 2 - u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/RS - - clk_200m - clk_200m - rise-rise - 0.067 - 5.374 - 5.867 - -0.426 - 0.000 - 0.401 - 0.222 (55.4%) - 0.179 (44.6%) - - Path #2: removal slack is 0.554(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_200m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 1.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 1.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 2.688 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.096 - 2.784 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.059 - 3.843 - - zoom_clk - - - USCM_84_122/CLK_USCM - td - 0.000 - 3.843 - r - USCMROUTE_2/CLKOUT - - - - net (fanout=759) - 1.531 - 5.374 - - ntR3909 - - - CLMS_202_149/CLK - - - - r - u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK - - - CLMS_202_149/Q0 - tco - 0.222 - 5.596 - f - u_ddr_rst/rst/opit_0_inv_L5Q_perm/Q - - - - net (fanout=2) - 0.179 - 5.775 - - ddr_rst - - - CLMA_202_148/RS - - - - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/RS - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_200m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.101 - 3.204 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.078 - 4.282 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 4.282 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.585 - 5.867 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - CLMA_202_148/CLK - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK - - - clock pessimism - - -0.426 - 5.441 - - - - - clock uncertainty - - 0.000 - 5.441 - - - - - Removal time - - -0.220 - 5.221 - - - -
-
-
-
- - 0.555 - 0 - 37 - image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0] - - clk_50m - clk_50m - rise-rise - 0.036 - 5.378 - 5.873 - -0.459 - 0.000 - 0.569 - 0.222 (39.0%) - 0.347 (61.0%) - - Path #3: removal slack is 0.555(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_50m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 1.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 1.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 2.688 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.100 - 2.788 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.059 - 3.847 - - rd3_clk - - - USCM_84_108/CLK_USCM - td - 0.000 - 3.847 - r - clkbufg_1/gopclkbufg/CLKOUT - - - - net (fanout=2517) - 1.531 - 5.378 - - ntclkbufg_1 - - - CLMS_134_93/CLK - - - - r - image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK - - - CLMS_134_93/Q0 - tco - 0.222 - 5.600 - f - image_filiter_inst/multiline_buffer_inst/srst/opit_0/Q - - - - net (fanout=37) - 0.347 - 5.947 - - image_filiter_inst/multiline_buffer_inst/srst - - - DRM_142_88/RSTB[0] - - - - f - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0] - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_50m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.107 - 3.210 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.078 - 4.288 - - rd3_clk - - - USCM_84_108/CLK_USCM - td - 0.000 - 4.288 - r - clkbufg_1/gopclkbufg/CLKOUT - - - - net (fanout=2517) - 1.585 - 5.873 - - ntclkbufg_1 - - - DRM_142_88/CLKB[0] - - - - r - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] - - - clock pessimism - - -0.459 - 5.414 - - - - - clock uncertainty - - 0.000 - 5.414 - - - - - Removal time - - -0.022 - 5.392 - - - -
-
-
-
- - 0.579 - 0 - 37 - image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTA[0] - - clk_50m - clk_50m - rise-rise - 0.036 - 5.378 - 5.873 - -0.459 - 0.000 - 0.569 - 0.222 (39.0%) - 0.347 (61.0%) - - Path #4: removal slack is 0.579(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_50m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 1.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 1.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 2.688 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.100 - 2.788 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.059 - 3.847 - - rd3_clk - - - USCM_84_108/CLK_USCM - td - 0.000 - 3.847 - r - clkbufg_1/gopclkbufg/CLKOUT - - - - net (fanout=2517) - 1.531 - 5.378 - - ntclkbufg_1 - - - CLMS_134_93/CLK - - - - r - image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK - - - CLMS_134_93/Q0 - tco - 0.222 - 5.600 - f - image_filiter_inst/multiline_buffer_inst/srst/opit_0/Q - - - - net (fanout=37) - 0.347 - 5.947 - - image_filiter_inst/multiline_buffer_inst/srst - - - DRM_142_88/RSTA[0] - - - - f - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTA[0] - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_50m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.107 - 3.210 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.078 - 4.288 - - rd3_clk - - - USCM_84_108/CLK_USCM - td - 0.000 - 4.288 - r - clkbufg_1/gopclkbufg/CLKOUT - - - - net (fanout=2517) - 1.585 - 5.873 - - ntclkbufg_1 - - - DRM_142_88/CLKA[0] - - - - r - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] - - - clock pessimism - - -0.459 - 5.414 - - - - - clock uncertainty - - 0.000 - 5.414 - - - - - Removal time - - -0.046 - 5.368 - - - -
-
-
-
- - 0.734 - 1 - 14 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q_perm/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[0]/opit_0_inv/RS - - clk_200m - clk_200m - rise-rise - 0.036 - 5.374 - 5.867 - -0.457 - 0.000 - 0.770 - 0.327 (42.5%) - 0.443 (57.5%) - - Path #5: removal slack is 0.734(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_200m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 1.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 1.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 2.688 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.096 - 2.784 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.059 - 3.843 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 3.843 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.531 - 5.374 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - CLMS_78_181/CLK - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q_perm/CLK - - - CLMS_78_181/Q0 - tco - 0.222 - 5.596 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q_perm/Q - - - - net (fanout=14) - 0.443 - 6.039 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/logic_rstn - - - CLMS_62_181/RSCO - td - 0.105 - 6.144 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/pll_lock_d[1]/opit_0_inv/RSOUT - - - - net (fanout=4) - 0.000 - 6.144 - - ntR1581 - - - CLMS_62_185/RSCI - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[0]/opit_0_inv/RS - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_200m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.101 - 3.204 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.078 - 4.282 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 4.282 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.585 - 5.867 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - CLMS_62_185/CLK - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[0]/opit_0_inv/CLK - - - clock pessimism - - -0.457 - 5.410 - - - - - clock uncertainty - - 0.000 - 5.410 - - - - - Removal time - - 0.000 - 5.410 - - - -
-
-
-
- - 0.760 - 1 - 37 - image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/RS - - clk_50m - clk_50m - rise-rise - 0.036 - 5.378 - 5.873 - -0.459 - 0.000 - 0.796 - 0.331 (41.6%) - 0.465 (58.4%) - - Path #6: removal slack is 0.760(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_50m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 1.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 1.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 2.688 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.100 - 2.788 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.059 - 3.847 - - rd3_clk - - - USCM_84_108/CLK_USCM - td - 0.000 - 3.847 - r - clkbufg_1/gopclkbufg/CLKOUT - - - - net (fanout=2517) - 1.531 - 5.378 - - ntclkbufg_1 - - - CLMS_134_93/CLK - - - - r - image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK - - - CLMS_134_93/Q0 - tco - 0.226 - 5.604 - r - image_filiter_inst/multiline_buffer_inst/srst/opit_0/Q - - - - net (fanout=37) - 0.465 - 6.069 - - image_filiter_inst/multiline_buffer_inst/srst - - - CLMA_138_81/RSCO - td - 0.105 - 6.174 - r - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/RSOUT - - - - net (fanout=2) - 0.000 - 6.174 - - ntR38 - - - CLMA_138_85/RSCI - - - - r - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/RS - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_50m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.107 - 3.210 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.078 - 4.288 - - rd3_clk - - - USCM_84_108/CLK_USCM - td - 0.000 - 4.288 - r - clkbufg_1/gopclkbufg/CLKOUT - - - - net (fanout=2517) - 1.585 - 5.873 - - ntclkbufg_1 - - - CLMA_138_85/CLK - - - - r - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK - - - clock pessimism - - -0.459 - 5.414 - - - - - clock uncertainty - - 0.000 - 5.414 - - - - - Removal time - - 0.000 - 5.414 - - - -
-
-
-
- - 0.779 - 1 - 619 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[151]/opit_0_inv/RS - - ddrphy_clkin - ddrphy_clkin - rise-rise - 0.036 - 10.665 - 11.394 - -0.693 - 0.000 - 0.815 - 0.327 (40.1%) - 0.488 (59.9%) - - Path #7: removal slack is 0.779(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ddrphy_clkin (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 1.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 1.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 2.688 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.096 - 2.784 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.059 - 3.843 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 3.843 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.665 - 5.508 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.123 - 5.631 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.102 - 6.733 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.249 - 6.982 - r - clkgate_8/gopclkgate/OUT - - - - net (fanout=1) - 0.000 - 6.982 - - ntclkgate_0 - - - IOCKDIV_6_323/CLK_IODIV - td - 0.000 - 6.982 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV - - - - net (fanout=1) - 2.152 - 9.134 - - u_axi_ddr_top/clk - - - USCM_84_116/CLK_USCM - td - 0.000 - 9.134 - r - clkbufg_0/gopclkbufg/CLKOUT - - - - net (fanout=5464) - 1.531 - 10.665 - - ntclkbufg_0 - - - CLMA_70_192/CLK - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK - - - CLMA_70_192/Q0 - tco - 0.222 - 10.887 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q - - - - net (fanout=619) - 0.488 - 11.375 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n - - - CLMA_66_212/RSCO - td - 0.105 - 11.480 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[37]/opit_0_inv/RSOUT - - - - net (fanout=4) - 0.000 - 11.480 - - ntR1484 - - - CLMA_66_216/RSCI - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[151]/opit_0_inv/RS - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ddrphy_clkin (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.101 - 3.204 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.078 - 4.282 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 4.282 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.738 - 6.020 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.129 - 6.149 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.121 - 7.270 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.348 - 7.618 - r - clkgate_8/gopclkgate/OUT - - - - net (fanout=1) - 0.000 - 7.618 - - ntclkgate_0 - - - IOCKDIV_6_323/CLK_IODIV - td - 0.000 - 7.618 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV - - - - net (fanout=1) - 2.191 - 9.809 - - u_axi_ddr_top/clk - - - USCM_84_116/CLK_USCM - td - 0.000 - 9.809 - r - clkbufg_0/gopclkbufg/CLKOUT - - - - net (fanout=5464) - 1.585 - 11.394 - - ntclkbufg_0 - - - CLMA_66_216/CLK - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[151]/opit_0_inv/CLK - - - clock pessimism - - -0.693 - 10.701 - - - - - clock uncertainty - - 0.000 - 10.701 - - - - - Removal time - - 0.000 - 10.701 - - - -
-
-
-
- - 0.779 - 1 - 619 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[2]/opit_0_inv/RS - - ddrphy_clkin - ddrphy_clkin - rise-rise - 0.036 - 10.665 - 11.394 - -0.693 - 0.000 - 0.815 - 0.327 (40.1%) - 0.488 (59.9%) - - Path #8: removal slack is 0.779(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ddrphy_clkin (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 1.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 1.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 2.688 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.096 - 2.784 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.059 - 3.843 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 3.843 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.665 - 5.508 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.123 - 5.631 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.102 - 6.733 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.249 - 6.982 - r - clkgate_8/gopclkgate/OUT - - - - net (fanout=1) - 0.000 - 6.982 - - ntclkgate_0 - - - IOCKDIV_6_323/CLK_IODIV - td - 0.000 - 6.982 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV - - - - net (fanout=1) - 2.152 - 9.134 - - u_axi_ddr_top/clk - - - USCM_84_116/CLK_USCM - td - 0.000 - 9.134 - r - clkbufg_0/gopclkbufg/CLKOUT - - - - net (fanout=5464) - 1.531 - 10.665 - - ntclkbufg_0 - - - CLMA_70_192/CLK - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK - - - CLMA_70_192/Q0 - tco - 0.222 - 10.887 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q - - - - net (fanout=619) - 0.488 - 11.375 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n - - - CLMA_66_212/RSCO - td - 0.105 - 11.480 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[37]/opit_0_inv/RSOUT - - - - net (fanout=4) - 0.000 - 11.480 - - ntR1484 - - - CLMA_66_216/RSCI - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[2]/opit_0_inv/RS - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ddrphy_clkin (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.101 - 3.204 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.078 - 4.282 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 4.282 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.738 - 6.020 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.129 - 6.149 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.121 - 7.270 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.348 - 7.618 - r - clkgate_8/gopclkgate/OUT - - - - net (fanout=1) - 0.000 - 7.618 - - ntclkgate_0 - - - IOCKDIV_6_323/CLK_IODIV - td - 0.000 - 7.618 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV - - - - net (fanout=1) - 2.191 - 9.809 - - u_axi_ddr_top/clk - - - USCM_84_116/CLK_USCM - td - 0.000 - 9.809 - r - clkbufg_0/gopclkbufg/CLKOUT - - - - net (fanout=5464) - 1.585 - 11.394 - - ntclkbufg_0 - - - CLMA_66_216/CLK - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[2]/opit_0_inv/CLK - - - clock pessimism - - -0.693 - 10.701 - - - - - clock uncertainty - - 0.000 - 10.701 - - - - - Removal time - - 0.000 - 10.701 - - - -
-
-
-
- - 0.779 - 1 - 619 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[3]/opit_0_inv/RS - - ddrphy_clkin - ddrphy_clkin - rise-rise - 0.036 - 10.665 - 11.394 - -0.693 - 0.000 - 0.815 - 0.327 (40.1%) - 0.488 (59.9%) - - Path #9: removal slack is 0.779(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ddrphy_clkin (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 1.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 1.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 2.688 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.096 - 2.784 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.059 - 3.843 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 3.843 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.665 - 5.508 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.123 - 5.631 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.102 - 6.733 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.249 - 6.982 - r - clkgate_8/gopclkgate/OUT - - - - net (fanout=1) - 0.000 - 6.982 - - ntclkgate_0 - - - IOCKDIV_6_323/CLK_IODIV - td - 0.000 - 6.982 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV - - - - net (fanout=1) - 2.152 - 9.134 - - u_axi_ddr_top/clk - - - USCM_84_116/CLK_USCM - td - 0.000 - 9.134 - r - clkbufg_0/gopclkbufg/CLKOUT - - - - net (fanout=5464) - 1.531 - 10.665 - - ntclkbufg_0 - - - CLMA_70_192/CLK - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK - - - CLMA_70_192/Q0 - tco - 0.222 - 10.887 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q - - - - net (fanout=619) - 0.488 - 11.375 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n - - - CLMA_66_212/RSCO - td - 0.105 - 11.480 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[37]/opit_0_inv/RSOUT - - - - net (fanout=4) - 0.000 - 11.480 - - ntR1484 - - - CLMA_66_216/RSCI - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[3]/opit_0_inv/RS - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ddrphy_clkin (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.101 - 3.204 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.078 - 4.282 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 4.282 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.738 - 6.020 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.129 - 6.149 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 1.121 - 7.270 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.348 - 7.618 - r - clkgate_8/gopclkgate/OUT - - - - net (fanout=1) - 0.000 - 7.618 - - ntclkgate_0 - - - IOCKDIV_6_323/CLK_IODIV - td - 0.000 - 7.618 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV - - - - net (fanout=1) - 2.191 - 9.809 - - u_axi_ddr_top/clk - - - USCM_84_116/CLK_USCM - td - 0.000 - 9.809 - r - clkbufg_0/gopclkbufg/CLKOUT - - - - net (fanout=5464) - 1.585 - 11.394 - - ntclkbufg_0 - - - CLMA_66_216/CLK - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[3]/opit_0_inv/CLK - - - clock pessimism - - -0.693 - 10.701 - - - - - clock uncertainty - - 0.000 - 10.701 - - - - - Removal time - - 0.000 - 10.701 - - - -
-
-
-
- - 1.244 - 0 - 163 - u_hdmi_rst/rst/opit_0_L5Q_perm/CLK - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[12].U_GTP_DRM18K/iGopDrm/RSTB[0] - - clk_720p60Hz - clk_720p60Hz - rise-rise - 0.036 - 8.831 - 9.434 - -0.567 - 0.000 - 1.203 - 0.226 (18.8%) - 0.977 (81.2%) - - Path #10: removal slack is 1.244(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_720p60Hz (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 1.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 1.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 2.688 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.100 - 2.788 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.059 - 3.847 - - rd3_clk - - - USCM_84_154/CLK_USCM - td - 0.000 - 3.847 - r - USCMROUTE_0/CLKOUT - - - - net (fanout=1) - 1.786 - 5.633 - - ntR3907 - - - PLL_158_303/CLK_OUT1 - td - 0.096 - 5.729 - r - U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.571 - 7.300 - - nt_pix_clk - - - USCM_84_117/CLK_USCM - td - 0.000 - 7.300 - r - clkbufg_2/gopclkbufg/CLKOUT - - - - net (fanout=1635) - 1.531 - 8.831 - - ntclkbufg_2 - - - CLMA_190_124/CLK - - - - r - u_hdmi_rst/rst/opit_0_L5Q_perm/CLK - - - CLMA_190_124/Q0 - tco - 0.226 - 9.057 - r - u_hdmi_rst/rst/opit_0_L5Q_perm/Q - - - - net (fanout=163) - 0.977 - 10.034 - - rd2_rst - - - DRM_234_88/RSTB[0] - - - - r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[12].U_GTP_DRM18K/iGopDrm/RSTB[0] - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_720p60Hz (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.107 - 3.210 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.078 - 4.288 - - rd3_clk - - - USCM_84_154/CLK_USCM - td - 0.000 - 4.288 - r - USCMROUTE_0/CLKOUT - - - - net (fanout=1) - 1.861 - 6.149 - - ntR3907 - - - PLL_158_303/CLK_OUT1 - td - 0.101 - 6.250 - r - U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.599 - 7.849 - - nt_pix_clk - - - USCM_84_117/CLK_USCM - td - 0.000 - 7.849 - r - clkbufg_2/gopclkbufg/CLKOUT - - - - net (fanout=1635) - 1.585 - 9.434 - - ntclkbufg_2 - - - DRM_234_88/CLKB[0] - - - - r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[12].U_GTP_DRM18K/iGopDrm/CLKB[0] - - - clock pessimism - - -0.567 - 8.867 - - - - - clock uncertainty - - 0.000 - 8.867 - - - - - Removal time - - -0.077 - 8.790 - - - -
-
-
-
- - 1.312 - 0 - 3 - rstn_out1/opit_0_inv/CLK - ms72xx_ctl/rstn_temp1/opit_0_inv/RS - - clk_10m - clk_10m - rise-rise - 0.036 - 5.378 - 5.873 - -0.459 - 0.000 - 1.122 - 0.226 (20.1%) - 0.896 (79.9%) - - Path #11: removal slack is 1.312(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_10m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 1.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 1.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 2.688 - - _N69 - - - PLL_158_55/CLK_OUT4 - td - 0.100 - 2.788 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT4 - - - - net (fanout=1) - 1.059 - 3.847 - - clk_10m - - - USCM_84_110/CLK_USCM - td - 0.000 - 3.847 - r - clkbufg_3/gopclkbufg/CLKOUT - - - - net (fanout=235) - 1.531 - 5.378 - - ntclkbufg_3 - - - CLMA_230_69/CLK - - - - r - rstn_out1/opit_0_inv/CLK - - - CLMA_230_69/Q3 - tco - 0.226 - 5.604 - r - rstn_out1/opit_0_inv/Q - - - - net (fanout=3) - 0.896 - 6.500 - - nt_eth_rstn - - - CLMA_246_120/RS - - - - r - ms72xx_ctl/rstn_temp1/opit_0_inv/RS - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_10m (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT4 - td - 0.107 - 3.210 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT4 - - - - net (fanout=1) - 1.078 - 4.288 - - clk_10m - - - USCM_84_110/CLK_USCM - td - 0.000 - 4.288 - r - clkbufg_3/gopclkbufg/CLKOUT - - - - net (fanout=235) - 1.585 - 5.873 - - ntclkbufg_3 - - - CLMA_246_120/CLK - - - - r - ms72xx_ctl/rstn_temp1/opit_0_inv/CLK - - - clock pessimism - - -0.459 - 5.414 - - - - - clock uncertainty - - 0.000 - 5.414 - - - - - Removal time - - -0.226 - 5.188 - - - -
-
-
-
- - 1.355 - 0 - 163 - u_hdmi_rst/rst/opit_0_L5Q_perm/CLK - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0] - - clk_720p60Hz - clk_720p60Hz - rise-rise - 0.054 - 8.831 - 9.434 - -0.549 - 0.000 - 1.332 - 0.226 (17.0%) - 1.106 (83.0%) - - Path #12: removal slack is 1.355(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_720p60Hz (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 1.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 1.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 2.688 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.100 - 2.788 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.059 - 3.847 - - rd3_clk - - - USCM_84_154/CLK_USCM - td - 0.000 - 3.847 - r - USCMROUTE_0/CLKOUT - - - - net (fanout=1) - 1.786 - 5.633 - - ntR3907 - - - PLL_158_303/CLK_OUT1 - td - 0.096 - 5.729 - r - U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.571 - 7.300 - - nt_pix_clk - - - USCM_84_117/CLK_USCM - td - 0.000 - 7.300 - r - clkbufg_2/gopclkbufg/CLKOUT - - - - net (fanout=1635) - 1.531 - 8.831 - - ntclkbufg_2 - - - CLMA_190_124/CLK - - - - r - u_hdmi_rst/rst/opit_0_L5Q_perm/CLK - - - CLMA_190_124/Q0 - tco - 0.226 - 9.057 - r - u_hdmi_rst/rst/opit_0_L5Q_perm/Q - - - - net (fanout=163) - 1.106 - 10.163 - - rd2_rst - - - DRM_234_148/RSTB[0] - - - - r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0] - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_720p60Hz (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.107 - 3.210 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.078 - 4.288 - - rd3_clk - - - USCM_84_154/CLK_USCM - td - 0.000 - 4.288 - r - USCMROUTE_0/CLKOUT - - - - net (fanout=1) - 1.861 - 6.149 - - ntR3907 - - - PLL_158_303/CLK_OUT1 - td - 0.101 - 6.250 - r - U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.599 - 7.849 - - nt_pix_clk - - - USCM_84_117/CLK_USCM - td - 0.000 - 7.849 - r - clkbufg_2/gopclkbufg/CLKOUT - - - - net (fanout=1635) - 1.585 - 9.434 - - ntclkbufg_2 - - - DRM_234_148/CLKB[0] - - - - r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] - - - clock pessimism - - -0.549 - 8.885 - - - - - clock uncertainty - - 0.000 - 8.885 - - - - - Removal time - - -0.077 - 8.808 - - - -
-
-
-
- - 1.377 - 0 - 163 - u_hdmi_rst/rst/opit_0_L5Q_perm/CLK - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[15]/opit_0/RS - - clk_720p60Hz - clk_720p60Hz - rise-rise - 0.054 - 8.831 - 9.434 - -0.549 - 0.000 - 1.205 - 0.226 (18.8%) - 0.979 (81.2%) - - Path #13: removal slack is 1.377(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_720p60Hz (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.808 - 1.882 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.882 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.048 - 1.930 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.758 - 2.688 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.100 - 2.788 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.059 - 3.847 - - rd3_clk - - - USCM_84_154/CLK_USCM - td - 0.000 - 3.847 - r - USCMROUTE_0/CLKOUT - - - - net (fanout=1) - 1.786 - 5.633 - - ntR3907 - - - PLL_158_303/CLK_OUT1 - td - 0.096 - 5.729 - r - U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.571 - 7.300 - - nt_pix_clk - - - USCM_84_117/CLK_USCM - td - 0.000 - 7.300 - r - clkbufg_2/gopclkbufg/CLKOUT - - - - net (fanout=1635) - 1.531 - 8.831 - - ntclkbufg_2 - - - CLMA_190_124/CLK - - - - r - u_hdmi_rst/rst/opit_0_L5Q_perm/CLK - - - CLMA_190_124/Q0 - tco - 0.226 - 9.057 - r - u_hdmi_rst/rst/opit_0_L5Q_perm/Q - - - - net (fanout=163) - 0.979 - 10.036 - - rd2_rst - - - CLMS_226_173/RS - - - - r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[15]/opit_0/RS - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_720p60Hz (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 2.166 - 2.240 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 2.240 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.076 - 2.316 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.787 - 3.103 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.107 - 3.210 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 1.078 - 4.288 - - rd3_clk - - - USCM_84_154/CLK_USCM - td - 0.000 - 4.288 - r - USCMROUTE_0/CLKOUT - - - - net (fanout=1) - 1.861 - 6.149 - - ntR3907 - - - PLL_158_303/CLK_OUT1 - td - 0.101 - 6.250 - r - U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 1.599 - 7.849 - - nt_pix_clk - - - USCM_84_117/CLK_USCM - td - 0.000 - 7.849 - r - clkbufg_2/gopclkbufg/CLKOUT - - - - net (fanout=1635) - 1.585 - 9.434 - - ntclkbufg_2 - - - CLMS_226_173/CLK - - - - r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[15]/opit_0/CLK - - - clock pessimism - - -0.549 - 8.885 - - - - - clock uncertainty - - 0.000 - 8.885 - - - - - Removal time - - -0.226 - 8.659 - - - -
-
-
-
- - - - Slack - Actual Width - Require Width - Clock - Type - Location - Pin - - - 0.397 - 1.250 - 0.853 - ioclk2 - Low Pulse Width - DQSL_6_28/CLK_IO - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_ddc_ca/opit_0/IOCLK - - - 0.397 - 1.250 - 0.853 - ioclk2 - High Pulse Width - DQSL_6_28/CLK_IO - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_ddc_ca/opit_0/IOCLK - - - 0.397 - 1.250 - 0.853 - ioclk0 - Low Pulse Width - DQSL_6_348/CLK_IO - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[1].u_ddc_ca/opit_0/IOCLK - - - 0.397 - 1.250 - 0.853 - ioclk0 - High Pulse Width - DQSL_6_348/CLK_IO - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[1].u_ddc_ca/opit_0/IOCLK - - - 0.397 - 1.250 - 0.853 - ioclk2 - High Pulse Width - DQSL_6_100/CLK_IO - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[2].u_ddc_ca/opit_0/IOCLK - - - 0.397 - 1.250 - 0.853 - ioclk0 - High Pulse Width - DQSL_6_304/CLK_IO - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[3].u_ddc_ca/opit_0/IOCLK - - - 0.397 - 1.250 - 0.853 - ioclk1 - High Pulse Width - DQSL_6_152/CLK_IO - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - - - 0.397 - 1.250 - 0.853 - ioclk1 - Low Pulse Width - DQSL_6_152/CLK_IO - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - - - 0.397 - 1.250 - 0.853 - ioclk1 - High Pulse Width - DQSL_6_180/CLK_IO - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - - - 1.362 - 2.500 - 1.138 - clk_200m - High Pulse Width - APM_206_228/CLK - u_zoom_image/mult_fra0/N2/gopapm/CLK - - - 1.362 - 2.500 - 1.138 - clk_200m - Low Pulse Width - APM_206_228/CLK - u_zoom_image/mult_fra0/N2/gopapm/CLK - - - 1.362 - 2.500 - 1.138 - clk_200m - Low Pulse Width - APM_206_140/CLK - u_zoom_image/mult_fra0_0/N2/gopapm/CLK - - - 2.435 - 3.333 - 0.898 - hdmi_in_clk - Low Pulse Width - DRM_82_108/CLKA[0] - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] - - - 2.435 - 3.333 - 0.898 - hdmi_in_clk - High Pulse Width - DRM_82_108/CLKA[0] - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] - - - 2.435 - 3.333 - 0.898 - hdmi_in_clk - High Pulse Width - DRM_54_108/CLKA[0] - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] - - - 2.483 - 4.000 - 1.517 - eth_rxc - High Pulse Width - IOL_71_373/CLK_SYS - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_ctl_in/gateigddr_IOL/SYSCLK - - - 2.483 - 4.000 - 1.517 - eth_rxc - Low Pulse Width - IOL_71_373/CLK_SYS - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_ctl_in/gateigddr_IOL/SYSCLK - - - 2.483 - 4.000 - 1.517 - eth_rxc - Low Pulse Width - IOL_311_374/CLK_SYS - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gtp_outbuft1/opit_1_IOL/SYSCLK - - - 3.100 - 5.000 - 1.900 - ddrphy_clkin - High Pulse Width - CLMS_38_109/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram16x1d/WCLK - - - 3.100 - 5.000 - 1.900 - ddrphy_clkin - Low Pulse Width - CLMS_38_109/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram16x1d/WCLK - - - 3.100 - 5.000 - 1.900 - ddrphy_clkin - High Pulse Width - CLMS_34_113/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_2/ram16x1d/WCLK - - - 4.580 - 5.000 - 0.420 - ioclk_gate_clk - High Pulse Width - CLMA_150_192/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_ioclk_gate/opit_0_inv_L5Q_perm/CLK - - - 4.580 - 5.000 - 0.420 - ioclk_gate_clk - Low Pulse Width - CLMA_150_192/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_ioclk_gate/opit_0_inv_L5Q_perm/CLK - - - 5.052 - 5.950 - 0.898 - cmos1_pclk - Low Pulse Width - DRM_142_24/CLKA[0] - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] - - - 5.052 - 5.950 - 0.898 - cmos1_pclk - High Pulse Width - DRM_142_24/CLKA[0] - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] - - - 5.052 - 5.950 - 0.898 - cmos2_pclk - Low Pulse Width - DRM_142_44/CLKA[0] - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] - - - 5.052 - 5.950 - 0.898 - cmos2_pclk - High Pulse Width - DRM_142_44/CLKA[0] - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] - - - 5.330 - 5.950 - 0.620 - cmos1_pclk - High Pulse Width - CLMS_146_9/CLK - u_ov5640/cmos1_8_16bit/de_in0/opit_0/CLK - - - 5.330 - 5.950 - 0.620 - cmos2_pclk - Low Pulse Width - CLMS_150_41/CLK - u_ov5640/cmos2_8_16bit/de_cnt/opit_0_L5Q/CLK - - - 5.598 - 6.736 - 1.138 - clk_720p60Hz - High Pulse Width - APM_258_140/CLK - adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N11/gopapm/CLK - - - 5.598 - 6.736 - 1.138 - clk_720p60Hz - High Pulse Width - APM_258_128/CLK - adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N135/gopapm/CLK - - - 5.599 - 6.737 - 1.138 - clk_720p60Hz - Low Pulse Width - APM_258_140/CLK - adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N11/gopapm/CLK - - - 8.862 - 10.000 - 1.138 - clk_50m - High Pulse Width - APM_106_116/CLK - u_rotate_image/u_rotate_mult0/N2/gopapm/CLK - - - 8.862 - 10.000 - 1.138 - clk_50m - Low Pulse Width - APM_106_116/CLK - u_rotate_image/u_rotate_mult0/N2/gopapm/CLK - - - 8.862 - 10.000 - 1.138 - clk_50m - High Pulse Width - APM_106_104/CLK - u_rotate_image/u_rotate_mult1/N2/gopapm/CLK - - - 19.580 - 20.000 - 0.420 - clk_25m - Low Pulse Width - CLMA_182_12/CLK - u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK - - - 19.580 - 20.000 - 0.420 - clk_25m - High Pulse Width - CLMA_182_12/CLK - u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK - - - 19.580 - 20.000 - 0.420 - clk_25m - High Pulse Width - CLMA_182_12/CLK - u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/CLK - - - 49.102 - 50.000 - 0.898 - clk_10m - Low Pulse Width - DRM_234_108/CLKA[0] - ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKA[0] - - - 49.102 - 50.000 - 0.898 - clk_10m - High Pulse Width - DRM_234_108/CLKA[0] - ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKA[0] - - - 49.102 - 50.000 - 0.898 - clk_10m - Low Pulse Width - DRM_234_108/CLKB[0] - ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKB[0] - - - 24999.102 - 25000.000 - 0.898 - clk_20k - High Pulse Width - DRM_178_4/CLKA[0] - u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKA[0] - - - 24999.102 - 25000.000 - 0.898 - clk_20k - Low Pulse Width - DRM_178_4/CLKA[0] - u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKA[0] - - - 24999.102 - 25000.000 - 0.898 - clk_20k - Low Pulse Width - DRM_178_4/CLKB[0] - u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0] - -
- - - Launch Clock - Capture Clock - WNS(ns) - TNS(ns) - Failing Endpoints - Total Endpoints - - - clk_200m - clk_200m - 0.707 - 0.000 - 0 - 3769 - - - ioclk1 - ioclk1 - 1.834 - 0.000 - 0 - 72 - - - ioclk0 - ioclk0 - 1.834 - 0.000 - 0 - 24 - - - hdmi_in_clk - hdmi_in_clk - 2.618 - 0.000 - 0 - 311 - - - eth_rxc - eth_rxc - 3.025 - 0.000 - 0 - 5907 - - - ddrphy_clkin - ddrphy_clkin - 3.245 - 0.000 - 0 - 18193 - - - cmos2_pclk - cmos2_pclk - 6.092 - 0.000 - 0 - 251 - - - cmos1_pclk - cmos1_pclk - 6.761 - 0.000 - 0 - 251 - - - clk_720p60Hz - clk_720p60Hz - 7.848 - 0.000 - 0 - 4786 - - - clk_50m - clk_50m - 13.413 - 0.000 - 0 - 9498 - - - clk_25m - clk_25m - 36.725 - 0.000 - 0 - 30 - - - clk_10m - clk_10m - 95.894 - 0.000 - 0 - 1099 - - - clk_20k - clk_20k - 49996.400 - 0.000 - 0 - 181 - -
- - - Launch Clock - Capture Clock - WHS(ns) - THS(ns) - Failing Endpoints - Total Endpoints - - - hdmi_in_clk - hdmi_in_clk - 0.106 - 0.000 - 0 - 311 - - - cmos1_pclk - cmos1_pclk - 0.108 - 0.000 - 0 - 251 - - - ddrphy_clkin - ddrphy_clkin - 0.111 - 0.000 - 0 - 18193 - - - clk_50m - clk_50m - 0.139 - 0.000 - 0 - 9498 - - - clk_200m - clk_200m - 0.196 - 0.000 - 0 - 3769 - - - clk_10m - clk_10m - 0.232 - 0.000 - 0 - 1099 - - - clk_720p60Hz - clk_720p60Hz - 0.251 - 0.000 - 0 - 4786 - - - eth_rxc - eth_rxc - 0.252 - 0.000 - 0 - 5907 - - - cmos2_pclk - cmos2_pclk - 0.254 - 0.000 - 0 - 251 - - - clk_20k - clk_20k - 0.269 - 0.000 - 0 - 181 - - - ioclk1 - ioclk1 - 0.383 - 0.000 - 0 - 72 - - - ioclk0 - ioclk0 - 0.383 - 0.000 - 0 - 24 - - - clk_25m - clk_25m - 0.406 - 0.000 - 0 - 30 - -
- - - Launch Clock - Capture Clock - WNS(ns) - TNS(ns) - Failing Endpoints - Total Endpoints - - - clk_200m - clk_200m - 2.157 - 0.000 - 0 - 175 - - - ddrphy_clkin - ddrphy_clkin - 6.770 - 0.000 - 0 - 2569 - - - clk_720p60Hz - clk_720p60Hz - 9.915 - 0.000 - 0 - 717 - - - clk_50m - clk_50m - 17.096 - 0.000 - 0 - 192 - - - clk_10m - clk_10m - 98.359 - 0.000 - 0 - 1 - -
- - - Launch Clock - Capture Clock - WHS(ns) - THS(ns) - Failing Endpoints - Total Endpoints - - - clk_50m - clk_50m - 0.418 - 0.000 - 0 - 192 - - - clk_200m - clk_200m - 0.452 - 0.000 - 0 - 175 - - - ddrphy_clkin - ddrphy_clkin - 0.555 - 0.000 - 0 - 2569 - - - clk_720p60Hz - clk_720p60Hz - 0.851 - 0.000 - 0 - 717 - - - clk_10m - clk_10m - 0.915 - 0.000 - 0 - 1 - -
- - - Clock - WPWS - TPWS - Failing End Point - Total End Point - - - ioclk1 - 0.568 - 0.000 - 0 - 27 - - - ioclk0 - 0.568 - 0.000 - 0 - 11 - - - ioclk2 - 0.568 - 0.000 - 0 - 2 - - - clk_200m - 1.590 - 0.000 - 0 - 825 - - - hdmi_in_clk - 2.615 - 0.000 - 0 - 167 - - - eth_rxc - 2.787 - 0.000 - 0 - 1861 - - - ddrphy_clkin - 3.480 - 0.000 - 0 - 5464 - - - ioclk_gate_clk - 4.664 - 0.000 - 0 - 1 - - - cmos1_pclk - 5.232 - 0.000 - 0 - 118 - - - cmos2_pclk - 5.232 - 0.000 - 0 - 118 - - - clk_720p60Hz - 5.826 - 0.000 - 0 - 1635 - - - clk_50m - 9.090 - 0.000 - 0 - 2517 - - - clk_25m - 19.664 - 0.000 - 0 - 26 - - - clk_10m - 49.282 - 0.000 - 0 - 235 - - - clk_20k - 24999.282 - 0.000 - 0 - 38 - -
- - - - clk (50.00MHZ) (drive 0 loads) (min_rise, max_rise, min_fall, max_fall) - - clk (0.000, 0.000, 0.000, 0.000) - - clk_ibuf/opit_0/I (0.074, 0.074, 0.074, 0.074) - - clk_ibuf/opit_0/O (1.359, 1.578, 0.970, 1.123) - - clk_ibuf/ntD (net) - - clk_ibuf/opit_1/IN (1.359, 1.578, 0.970, 1.123) - - clk_ibuf/opit_1/INCK (1.397, 1.636, 1.008, 1.180) - - _N69 (net) - - u_sys_pll/u_pll_e3/goppll/CLKIN1 (1.860, 2.114, 1.464, 1.651) - - clk_50m (50.00MHZ) (drive 2517 loads) - - u_sys_pll/u_pll_e3/goppll/CLKOUT0 (1.938, 2.197, 1.540, 1.732) - - rd3_clk (net) - - clkbufg_1/gopclkbufg/CLK (2.541, 2.811, 2.137, 2.340) - - clkbufg_1/gopclkbufg/CLKOUT (2.541, 2.811, 2.137, 2.340) - - ntclkbufg_1 (net) - - camera_vs_ff0/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - camera_vs_ff1/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/m_result_data[0]/opit_0_A2Q1/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/m_result_data[2]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/m_result_data[4]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][0][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][0][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][0][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][0][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][0][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][1][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][1][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][1][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][1][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][1][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][2][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][2][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][2][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][2][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][2][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][0][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][0][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][0][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][0][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][0][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][1][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][1][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][1][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][1][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][1][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][2][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][2][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][2][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][2][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][2][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][0][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][0][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][0][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][0][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][0][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][1][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][1][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][1][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][1][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][1][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][2][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][2][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][2][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][2][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][2][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum1x4[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum1x4[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum1x4[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum1x4[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum1x4[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x1[1]/opit_0_A2Q1/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x1[3]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x1[5]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x1[6]/opit_0_AQ/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x2[1]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x2[3]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x2[5]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x2[6]/opit_0_AQ/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum8[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum8[3]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum8[5]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum8[7]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum8[8]/opit_0_AQ/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/m_result_data[0]/opit_0_A2Q1/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/m_result_data[2]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/m_result_data[4]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/m_result_data[5]/opit_0_AQ_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][0][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][0][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][0][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][0][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][0][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][0][5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][1][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][1][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][1][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][1][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][1][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][1][5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][2][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][2][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][2][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][2][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][2][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][2][5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][0][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][0][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][0][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][0][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][0][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][0][5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][1][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][1][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][1][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][1][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][1][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][1][5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][2][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][2][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][2][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][2][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][2][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][2][5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][0][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][0][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][0][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][0][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][0][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][0][5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][1][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][1][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][1][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][1][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][1][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][1][5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][2][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][2][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][2][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][2][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][2][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][2][5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum1x4[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum1x4[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum1x4[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum1x4[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum1x4[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum1x4[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x1[1]/opit_0_A2Q1/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x1[3]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x1[5]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x1[7]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x2[1]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x2[3]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x2[5]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x2[7]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum8[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum8[3]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum8[5]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum8[7]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum8[9]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/m_result_data[0]/opit_0_A2Q1/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/m_result_data[2]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/m_result_data[4]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][0][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][0][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][0][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][0][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][0][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][1][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][1][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][1][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][1][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][1][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][2][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][2][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][2][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][2][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][2][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][0][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][0][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][0][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][0][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][0][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][1][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][1][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][1][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][1][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][1][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][2][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][2][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][2][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][2][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][2][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][0][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][0][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][0][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][0][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][0][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][1][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][1][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][1][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][1][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][1][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][2][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][2][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][2][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][2][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][2][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/product4x2[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/product4x2[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/product4x2[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/product4x2[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/product4x2[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/product4x2[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/product4x2[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum1x4[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum1x4[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum1x4[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum1x4[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum1x4[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x1[1]/opit_0_A2Q1/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x1[3]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x1[5]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x1[6]/opit_0_AQ/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x2[1]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x2[3]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x2[5]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x2[6]/opit_0_AQ/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum8[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum8[3]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum8[5]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum8[7]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum8[8]/opit_0_AQ/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/m_result_valid/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/max[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/max[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/max[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/max[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/max[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_max[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_max[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_max[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_max[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_max[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_min[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_min[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_min[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_min[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_min[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/med[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/med[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/med[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/med[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/med[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/med_of_vector_med[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/med_of_vector_med[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/med_of_vector_med[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/med_of_vector_med[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/med_of_vector_med[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/min[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/min[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/min[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/min[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/min[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_max[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_max[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_max[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_max[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_max[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_min[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_min[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_min[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_min[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_min[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[5]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[5]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[5]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[5]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[5]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[5]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[5]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[5]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[5]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_max[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_max[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_max[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_max[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_max[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_max[5]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_min[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_min[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_min[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_min[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_min[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_min[5]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/med[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/med[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/med[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/med[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/med[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/med[5]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/med_of_vector_med[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/med_of_vector_med[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/med_of_vector_med[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/med_of_vector_med[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/med_of_vector_med[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/med_of_vector_med[5]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_max[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_max[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_max[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_max[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_max[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_max[5]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_min[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_min[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_min[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_min[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_min[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_min[5]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/opit_0_L5Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/max[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/max[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/max[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/max[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/max[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/max_of_vector_max[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/max_of_vector_max[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/max_of_vector_max[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/max_of_vector_max[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/max_of_vector_max[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/max_of_vector_min[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/max_of_vector_min[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/max_of_vector_min[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/max_of_vector_min[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/max_of_vector_min[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/med[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/med[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/med[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/med[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/med[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/med_of_vector_med[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/med_of_vector_med[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/med_of_vector_med[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/med_of_vector_med[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/med_of_vector_med[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - - - image_filiter_inst/hybrid_filter_inst/median_finder9_r/min[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKIN1 (5.508, 6.020, 4.986, 5.391) + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL (5.631, 6.149, 5.111, 5.518) + + clkout0_wl_0 (net) + + clkgate_9/gopclkgate/CLK (6.733, 7.270, 6.213, 6.639) + + clkgate_9/gopclkgate/OUT (6.982, 7.618, 6.462, 6.987) + + ntclkgate_0 (net) + + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLK (6.982, 7.618, 6.462, 6.987) + + ddrphy_clkin (100.00MHZ) (drive 5464 loads) + + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV (6.982, 7.618, 6.462, 6.987) + + u_axi_ddr_top/clk (net) + + clkbufg_0/gopclkbufg/CLK (9.134, 9.809, 8.612, 9.175) + + clkbufg_0/gopclkbufg/CLKOUT (9.134, 9.809, 8.612, 9.175) + + ntclkbufg_0 (net) + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[2]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[3]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[9]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[10]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[11]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[12]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[13]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[14]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_ba[0]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_ba[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_cas_n/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_cke/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_cs_n/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_odt/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_ras_n/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_we_n/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cke_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[2]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[4]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[6]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[7]/opit_0_inv_AQ_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_pwron_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[2]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[4]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[6]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[8]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[10]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[12]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[14]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[15]/opit_0_inv_AQ_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[2]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[4]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[6]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[8]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[10]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[12]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[14]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[15]/opit_0_inv_AQ_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tmod_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tmrd_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_txpr_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit[2]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit[4]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit[6]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit[8]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit[9]/opit_0_inv_AQ_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[9]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[10]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[11]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[12]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[13]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[14]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_ba[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_ba[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_cas_n/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_cke/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_cs_n/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_done/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_rst/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[9]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_we_n/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/mr_load_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/mr_load_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/mr_load_done/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/calib_done/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/init_start/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/rdcal_start/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/wrlvl_start/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[2]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[4]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[6]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[7]/opit_0_inv_AQ_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cnt_tmod_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cnt_twldqsen_pass/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[9]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[10]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[11]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[12]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_ba[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_cas_n/opit_0_inv_L5Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_cke/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_done/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_dqs_req/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_dqs_resp_r/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_odt/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[2]/opit_0_inv_A2Q1/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[4]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[6]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[8]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[10]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[12]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[14]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[16]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[17]/opit_0_inv_AQ_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt_trfc_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/ddrphy_rst_ack_r[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/ddrphy_rst_ack_r[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/ddrphy_rst_req/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/gate_move_en/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/gatecal_start/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/init_adj_rdel/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_address[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_address[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_address[10]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_ba[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_cas_n/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_cs_n/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_done/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_odt/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_ras_n/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[9]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[10]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[11]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[12]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[13]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[14]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[15]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[16]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[17]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_success/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_we_n/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[32]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[64]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[96]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[128]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[160]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[192]/opit_0_inv_A2Q0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[224]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata_en[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata_en[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata_en[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata_en[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rddata_cal/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdel_calibration/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdel_move_en/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/ref_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/ref_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/ref_cnt_done/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/reinit_adj_rdel/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/wr_enable/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/calib_done_r/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/dfi_init_complete/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[6]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[8]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[9]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[10]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[11]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[12]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[13]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[14]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[15]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[30]/opit_0_inv/CLK (10.696, 11.426, 10.195, 10.817) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[31]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[32]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[33]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[34]/opit_0_inv/CLK (10.679, 11.409, 10.178, 10.800) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[35]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[36]/opit_0_inv/CLK (10.699, 11.430, 10.199, 10.821) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[37]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[38]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[39]/opit_0_inv/CLK (10.699, 11.430, 10.199, 10.821) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[40]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[41]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[9]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[10]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[11]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[12]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[13]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[14]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[30]/opit_0_inv_L5Q_perm/CLK (10.696, 11.426, 10.195, 10.817) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[31]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[32]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[33]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[34]/opit_0_inv_L5Q_perm/CLK (10.679, 11.409, 10.178, 10.800) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[35]/opit_0_inv_L5Q_perm/CLK (10.696, 11.426, 10.195, 10.817) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[36]/opit_0_inv_L5Q_perm/CLK (10.699, 11.430, 10.199, 10.821) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[37]/opit_0_inv_L5Q_perm/CLK (10.696, 11.426, 10.195, 10.817) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[38]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[39]/opit_0_inv_L5Q_perm/CLK (10.699, 11.430, 10.199, 10.821) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[40]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[41]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba[6]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba[7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba[8]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cas_n[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cas_n[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cas_n_d[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cas_n_d[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cke[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cke_d[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cs_n[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cs_n[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cs_n_d[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cs_n_d[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_odt[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_odt[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_odt_d[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_odt_d[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ras_n[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ras_n[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ras_n_d[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ras_n_d[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_we_n[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_we_n[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_we_n_d[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_we_n_d[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[6]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[8]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[9]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[10]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[11]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[12]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[13]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[14]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[15]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[16]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[17]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[18]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[19]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[20]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[21]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[22]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[23]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[24]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[25]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[26]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[27]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[28]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[29]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[30]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[31]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[32]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[33]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[34]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[35]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[36]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[37]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[38]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[39]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[40]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[41]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[42]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[43]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[44]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[45]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[46]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[47]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[48]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[49]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[50]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[51]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[52]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[53]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[54]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[55]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[56]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[57]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[58]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[59]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[60]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[61]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[62]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[63]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[64]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[65]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[66]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[67]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[68]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[69]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[70]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[71]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[72]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[73]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[74]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[75]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[76]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[77]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[78]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[79]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[80]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[81]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[82]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[83]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[84]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[85]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[86]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[87]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[88]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[89]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[90]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[91]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[92]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[93]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[94]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[95]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[96]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[97]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[98]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[99]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[100]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[101]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[102]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[103]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[104]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[105]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[106]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[107]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[108]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[109]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[110]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[111]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[112]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[113]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[114]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[115]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[116]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[117]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[118]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[119]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[120]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[121]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[122]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[123]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[124]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[125]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[126]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[127]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[128]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[129]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[130]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[131]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[132]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[133]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[134]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[135]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[136]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[137]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[138]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[139]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[140]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[141]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[142]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[143]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[144]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[145]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[146]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[147]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[148]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[149]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[150]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[151]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[152]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[153]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[154]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[155]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[156]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[157]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[158]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[159]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[160]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[161]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[162]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[163]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[164]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[165]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[166]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[167]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[168]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[169]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[170]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[171]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[172]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[173]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[174]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[175]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[176]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[177]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[178]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[179]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[180]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[181]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[182]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[183]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[184]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[185]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[186]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[187]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[188]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[189]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[190]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[191]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[192]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[193]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[194]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[195]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[196]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[197]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[198]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[199]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[200]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[201]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[202]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[203]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[204]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[205]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[206]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[207]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[208]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[209]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[210]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[211]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[212]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[213]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[214]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[215]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[216]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[217]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[218]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[219]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[220]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[221]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[222]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[223]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[224]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[225]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[226]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[227]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[228]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[229]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[230]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[231]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[232]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[233]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[234]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[235]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[236]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[237]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[238]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[239]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[240]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[241]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[242]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[243]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[244]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[245]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[246]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[247]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[248]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[249]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[250]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[251]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[252]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[253]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[254]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[255]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[9]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[10]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[11]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[12]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[13]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[14]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[15]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[16]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[17]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[18]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[19]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[20]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[21]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[22]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[23]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[24]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[25]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[26]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[27]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[28]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[29]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[30]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[31]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[32]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[33]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[34]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[35]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[36]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[37]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[38]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[39]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[40]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[41]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[42]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[43]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[44]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[45]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[46]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[47]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[48]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[49]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[50]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[51]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[52]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[53]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[54]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[55]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[56]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[57]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[58]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[59]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[60]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[61]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[62]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[63]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[64]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[65]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[66]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[67]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[68]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[69]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[70]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[71]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[72]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[73]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[74]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[75]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[76]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[77]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[78]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[79]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[80]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[81]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[82]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[83]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[84]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[85]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[86]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[87]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[88]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[89]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[90]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[91]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[92]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[93]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[94]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[95]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[96]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[97]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[98]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[99]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[100]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[101]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[102]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[103]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[104]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[105]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[106]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[107]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[108]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[109]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[110]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[111]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[112]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[113]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[114]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[115]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[116]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[117]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[118]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[119]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[120]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[121]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[122]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[123]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[124]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[125]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[126]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[127]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[128]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[129]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[130]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[131]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[132]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[133]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[134]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[135]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[136]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[137]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[138]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[139]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[140]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[141]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[142]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[143]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[144]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[145]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[146]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[147]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[148]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[149]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[150]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[151]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[152]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[153]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[154]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[155]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[156]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[157]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[158]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[159]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[160]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[161]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[162]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[163]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[164]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[165]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[166]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[167]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[168]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[169]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[170]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[171]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[172]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[173]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[174]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[175]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[176]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[177]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[178]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[179]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[180]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[181]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[182]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[183]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[184]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[185]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[186]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[187]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[188]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[189]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[190]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[191]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[192]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[193]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[194]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[195]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[196]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[197]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[198]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[199]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[200]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[201]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[202]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[203]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[204]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[205]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[206]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[207]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[208]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[209]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[210]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[211]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[212]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[213]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[214]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[215]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[216]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[217]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[218]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[219]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[220]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[221]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[222]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[223]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[224]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[225]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[226]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[227]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[228]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[229]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[230]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[231]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[232]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[233]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[234]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[235]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[236]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[237]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[238]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[239]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[240]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[241]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[242]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[243]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[244]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[245]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[246]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[247]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[248]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[249]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[250]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[251]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[252]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[253]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[254]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[255]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_en[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_en[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_en[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_en[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask[8]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask[24]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[24]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[9]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[10]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[11]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[12]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[13]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[14]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[9]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[10]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[11]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[12]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[13]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[14]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[9]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[10]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[11]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[12]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[13]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[14]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[9]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[10]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[11]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[12]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[13]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[14]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r1[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_dll_rst_sync/sig_async_r1[0]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_dll_rst_sync/sig_async_r2[0]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_ddc_ca/opit_0/CLK_REGIONAL (10.723, 11.454, 10.222, 10.845) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[1].u_ddc_ca/opit_0/CLK_REGIONAL (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[2].u_ddc_ca/opit_0/CLK_REGIONAL (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[3].u_ddc_ca/opit_0/CLK_REGIONAL (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[1]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[3]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_vld/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_comb_r[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_comb_r[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r1[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r1[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r2[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r2[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r3[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r3[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_adj_done/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_cal_error/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_error/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass_d/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[1]/opit_0_inv_A2Q1/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_check_done/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_set_bin_tra[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_set_bin_tra[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_set_bin_tra[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_set_bin_tra[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_set_bin_tra[4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_set_bin_tra[5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_set_bin_tra[6]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_set_bin_tra[7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[2]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[4]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[6]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/opit_0_inv_AQ_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt[3]/opit_0_inv_L5Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ddrphy_gatei/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/dq_rising/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[1]/opit_0_inv_A2Q1/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[7]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[2]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[4]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[6]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/opit_0_inv_AQ_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_done_flag/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_flag/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_resp/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_error/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[1].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[2].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[3].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[4].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[5].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[6].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[7].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/dqs_gate_check_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gate_check/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_check_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[6]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[8]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[9]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[10]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[11]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[12]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[13]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[14]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[15]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[16]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[17]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[18]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[19]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[20]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[21]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[22]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[23]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[24]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[25]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[26]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[27]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[28]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[29]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[30]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[31]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[32]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[33]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[34]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[35]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[36]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[37]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[38]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[39]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[40]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[41]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[42]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[43]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[44]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[45]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[46]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[47]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[48]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[49]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[50]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[51]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[52]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[53]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[54]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[55]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[56]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[57]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[58]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[59]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[60]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[61]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[62]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[63]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rdvalid_r1/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_inc_dec_n/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_rdel_done/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[2]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[4]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[6]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[8]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[9]/opit_0_inv_AQ_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[1]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[2]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[3]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[4]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[5]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[6]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[7]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[1]/opit_0_inv_A2Q1/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[7]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[1]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[2]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[3]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[4]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[5]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[6]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[7]/opit_0_inv_MUX4TO1Q/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_cal_vld/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_done/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_error/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calibration_d/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_move_done/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_sync/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/reinit_adj_rdel_d/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[1]/opit_0_inv_A2Q1/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[7]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[9]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[10]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[11]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[1]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[5]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[7]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[8]/opit_0_inv_AQ/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/CLK_REGIONAL (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_iobufco_dqs/opit_2_O/SYSCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_outbuft_dm/opit_1_IOL/SYSCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_r2[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_r[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_r[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_r[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_r[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[1]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[3]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_vld/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_adj_done/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_cal_error/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_error/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass_d/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[2]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[4]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[5]/opit_0_inv_AQ/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ck_check_done/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[2]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[4]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[6]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/opit_0_inv_AQ_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt[0]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ddrphy_gatei/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/dq_rising/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[1]/opit_0_inv_A2Q1/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[7]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[2]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[4]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[6]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/opit_0_inv_AQ_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_done_flag/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_flag/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_resp/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_error/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[1].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[2].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[3].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[4].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[5].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[6].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[7].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/dqs_gate_check_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gate_check/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_check_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[6]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[8]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[9]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[10]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[11]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[12]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[13]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[14]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[15]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[16]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[17]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[18]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[19]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[20]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[21]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[22]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[23]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[24]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[25]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[26]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[27]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[28]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[29]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[30]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[31]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[32]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[33]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[34]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[35]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[36]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[37]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[38]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[39]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[40]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[41]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[42]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[43]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[44]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[45]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[46]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[47]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[48]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[49]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[50]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[51]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[52]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[53]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[54]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[55]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[56]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[57]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[58]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[59]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[60]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[61]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[62]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[63]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rdvalid_r1/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/adj_rdel_done/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[2]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[4]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[6]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[8]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[9]/opit_0_inv_AQ/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[1]/opit_0_inv_A2Q1/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[7]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_done/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_error/opit_0_inv_MUX4TO1Q/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_move_done/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_sync/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[1]/opit_0_inv_A2Q1/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[7]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[9]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[10]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[11]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[1]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[7]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[8]/opit_0_inv_AQ/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/u_ddc_dqs/opit_0/CLK_REGIONAL (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/u_iobufco_dqs/opit_2_O/SYSCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/u_outbuft_dm/opit_1_IOL/SYSCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[1]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[3]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_vld/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_adj_done/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_cal_error/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_error/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass_d/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[2]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[4]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[5]/opit_0_inv_AQ/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_check_done/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[2]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[4]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[6]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/opit_0_inv_AQ_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt[0]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ddrphy_gatei/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/dq_rising/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[1]/opit_0_inv_A2Q1/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[7]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[2]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[4]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[6]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/opit_0_inv_AQ/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_done_flag/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_flag/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_resp/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_error/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[2]/opit_0_inv_L5Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[1].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[2].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[3].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[4].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[5].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[6].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[7].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/dqs_gate_check_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gate_check/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_check_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[6]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[8]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[9]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[10]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[11]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[12]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[13]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[14]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[15]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[16]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[17]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[18]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[19]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[20]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[21]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[22]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[23]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[24]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[25]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[26]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[27]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[28]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[29]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[30]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[31]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[32]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[33]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[34]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[35]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[36]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[37]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[38]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[39]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[40]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[41]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[42]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[43]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[44]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[45]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[46]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[47]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[48]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[49]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[50]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[51]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[52]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[53]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[54]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[55]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[56]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[57]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[58]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[59]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[60]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[61]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[62]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[63]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rdvalid_r1/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/adj_rdel_done/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[2]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[4]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[6]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[8]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[9]/opit_0_inv_AQ_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[1]/opit_0_inv_A2Q1/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[3]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[4]/opit_0_inv_A2Q20/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[7]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_done/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_error/opit_0_inv_MUX4TO1Q/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[1]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[2]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_move_done/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[2]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[3]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_sync/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[1]/opit_0_inv_A2Q1/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[3]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[5]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[7]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[1]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[2]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[3]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[4]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[5]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[6]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[7]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[8]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[9]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[10]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[11]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[1]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[3]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[5]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[7]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[8]/opit_0_inv_AQ/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/u_ddc_dqs/opit_0/CLK_REGIONAL (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/u_iobufco_dqs/opit_2_O/SYSCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/u_outbuft_dm/opit_1_IOL/SYSCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[1]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[3]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_vld/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_adj_done/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_cal_error/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_error/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass_d/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[2]/opit_0_inv_L5Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[2]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[4]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[5]/opit_0_inv_AQ/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_check_done/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[2]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[4]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[6]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/opit_0_inv_AQ_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt[0]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ddrphy_gatei/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/dq_rising/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[1]/opit_0_inv_A2Q1/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[3]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[5]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[7]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[2]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[4]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[6]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/opit_0_inv_AQ_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_done_flag/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_flag/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_resp/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_error/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[1]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[2]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[3]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[4]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[5]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[6]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[1].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[2].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[3].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[4].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[5].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[6].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[7].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/dqs_gate_check_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gate_check/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_check_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[0]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[1]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[2]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[3]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[4]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[5]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[6]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[7]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[8]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[9]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[10]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[11]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[12]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[13]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[14]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[15]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[16]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[17]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[18]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[19]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[20]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[21]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[22]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[23]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[24]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[25]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[26]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[27]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[28]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[29]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[30]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[31]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[32]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[33]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[34]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[35]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[36]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[37]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[38]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[39]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[40]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[41]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[42]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[43]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[44]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[45]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[46]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[47]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[48]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[49]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[50]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[51]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[52]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[53]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[54]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[55]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[56]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[57]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[58]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[59]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[60]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[61]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[62]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[63]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rdvalid_r1/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/adj_rdel_done/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[2]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[4]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[6]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[8]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[9]/opit_0_inv_AQ_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[1]/opit_0_inv_A2Q1/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[3]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[5]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[7]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_done/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_error/opit_0_inv_MUX4TO1Q/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[1]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[2]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_move_done/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[0]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[1]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[2]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[3]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_sync/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[1]/opit_0_inv_A2Q1/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[3]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[5]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[7]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[0]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[1]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[2]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[3]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[4]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[5]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[6]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[7]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[8]/opit_0_inv_L5Q/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[9]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[10]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[11]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[1]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[3]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[5]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[7]/opit_0_inv_A2Q21/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[8]/opit_0_inv_AQ/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/CLK_REGIONAL (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_iobufco_dqs/opit_2_O/SYSCLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_outbuft_dm/opit_1_IOL/SYSCLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_control_path_adj/phy_addr_r[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_control_path_adj/phy_cke_r[3]/opit_0_inv/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_control_path_adj/phy_odt_r[3]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_logic_rstn_sync/sig_async_r1[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_logic_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_addr_0/opit_1_IOL/SYSCLK (10.723, 11.454, 10.222, 10.845) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_addr_1/opit_1_IOL/SYSCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_addr_2/opit_1_IOL/SYSCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_addr_3/opit_1_IOL/SYSCLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_addr_4/opit_1_IOL/SYSCLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_addr_5/opit_1_IOL/SYSCLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_addr_6/opit_1_IOL/SYSCLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_addr_7/opit_1_IOL/SYSCLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_addr_8/opit_1_IOL/SYSCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_addr_9/opit_1_IOL/SYSCLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_addr_10/opit_1_IOL/SYSCLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_addr_11/opit_1_IOL/SYSCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_addr_12/opit_1_IOL/SYSCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_addr_13/opit_1_IOL/SYSCLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_addr_14/opit_1_IOL/SYSCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_ba0/opit_1_IOL/SYSCLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_ba1/opit_1_IOL/SYSCLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_ba2/opit_1_IOL/SYSCLK (10.723, 11.454, 10.222, 10.845) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_casn/opit_1_IOL/SYSCLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_cke/opit_1_IOL/SYSCLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_csn/opit_1_IOL/SYSCLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_odt/opit_1_IOL/SYSCLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_rasn/opit_1_IOL/SYSCLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuft_wen/opit_1_IOL/SYSCLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_outbuftco_ck/opit_3_IOL/SYSCLK (10.717, 11.448, 10.216, 10.839) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[6]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[8]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[9]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[10]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[11]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[12]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[13]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[14]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[15]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[16]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[17]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[18]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[19]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[20]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[21]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[22]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[23]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[24]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[25]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[26]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[27]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[28]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[29]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[30]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[31]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[32]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[33]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[34]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[35]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[36]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[37]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[38]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[39]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[40]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[41]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[42]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[43]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[44]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[45]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[46]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[47]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[48]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[49]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[50]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[51]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[52]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[53]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[54]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[55]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[56]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[57]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[58]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[59]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[60]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[61]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[62]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[63]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[64]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[65]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[66]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[67]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[68]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[69]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[70]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[71]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[72]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[73]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[74]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[75]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[76]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[77]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[78]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[79]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[80]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[81]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[82]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[83]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[84]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[85]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[86]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[87]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[88]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[89]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[90]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[91]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[92]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[93]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[94]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[95]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[96]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[97]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[98]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[99]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[100]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[101]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[102]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[103]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[104]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[105]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[106]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[107]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[108]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[109]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[110]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[111]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[112]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[113]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[114]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[115]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[116]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[117]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[118]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[119]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[120]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[121]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[122]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[123]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[124]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[125]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[126]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[127]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[128]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[129]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[130]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[131]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[132]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[133]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[134]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[135]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[136]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[137]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[138]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[139]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[140]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[141]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[142]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[143]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[144]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[145]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[146]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[147]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[148]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[149]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[150]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[151]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[152]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[153]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[154]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[155]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[156]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[157]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[158]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[159]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[160]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[161]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[162]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[163]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[164]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[165]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[166]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[167]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[168]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[169]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[170]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[171]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[172]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[173]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[174]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[175]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[176]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[177]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[178]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[179]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[180]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[181]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[182]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[183]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[184]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[185]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[186]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[187]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[188]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[189]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[190]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[191]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[192]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[193]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[194]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[195]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[196]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[197]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[198]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[199]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[200]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[201]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[202]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[203]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[204]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[205]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[206]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[207]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[208]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[209]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[210]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[211]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[212]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[213]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[214]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[215]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[216]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[217]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[218]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[219]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[220]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[221]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[222]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[223]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[224]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[225]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[226]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[227]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[228]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[229]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[230]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[231]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[232]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[233]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[234]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[235]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[236]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[237]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[238]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[239]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[240]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[241]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[242]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[243]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[244]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[245]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[246]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[247]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[248]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[249]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[250]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[251]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[252]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[253]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[254]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[255]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_start_rst/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_dqs_training_rstn/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_dqs_training_rstn_d/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_rst_req_d1/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_rst_req_d2/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_rst_req_d3/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/dqs_rst_training_high_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/dqs_rst_training_high_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/dqs_rst_training_high_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[6]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[8]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[9]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[10]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[11]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[12]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[13]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[14]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[4]/opit_0_inv/CLK (10.694, 11.424, 10.193, 10.815) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[6]/opit_0_inv/CLK (10.694, 11.424, 10.193, 10.815) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[8]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[9]/opit_0_inv/CLK (10.723, 11.454, 10.222, 10.845) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_baddr_l[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_baddr_l[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_baddr_l[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_baddr_m[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_baddr_m[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_baddr_m[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_l[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_l[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_l[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_l[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_l[4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_l[5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_l[6]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_l[7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_m[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_m[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_m[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_m[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_m[4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_m[6]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_m[7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_cfg_apb/ddr_init_done/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[0]/opit_0_inv_L5Q_perm/CLK (10.679, 11.409, 10.178, 10.800) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[1]/opit_0_inv_L5Q_perm/CLK (10.679, 11.409, 10.178, 10.800) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[2]/opit_0_inv_L5Q_perm/CLK (10.679, 11.409, 10.178, 10.800) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[3]/opit_0_inv_L5Q_perm/CLK (10.709, 11.440, 10.209, 10.831) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[4]/opit_0_inv_L5Q_perm/CLK (10.717, 11.448, 10.216, 10.839) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[5]/opit_0_inv_L5Q_perm/CLK (10.676, 11.406, 10.175, 10.797) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[6]/opit_0_inv_L5Q_perm/CLK (10.690, 11.420, 10.190, 10.812) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[7]/opit_0_inv_L5Q_perm/CLK (10.676, 11.406, 10.175, 10.797) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[8]/opit_0_inv_L5Q_perm/CLK (10.732, 11.463, 10.231, 10.854) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[9]/opit_0_inv_L5Q_perm/CLK (10.709, 11.440, 10.209, 10.831) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[10]/opit_0_inv_L5Q_perm/CLK (10.732, 11.463, 10.231, 10.854) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[11]/opit_0_inv_L5Q_perm/CLK (10.732, 11.463, 10.231, 10.854) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[12]/opit_0_inv_L5Q_perm/CLK (10.732, 11.463, 10.231, 10.854) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[13]/opit_0_inv_MUX4TO1Q/CLK (10.700, 11.431, 10.200, 10.822) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[14]/opit_0_inv_MUX4TO1Q/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[15]/opit_0_inv_MUX4TO1Q/CLK (10.685, 11.415, 10.184, 10.806) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[16]/opit_0_inv_MUX4TO1Q/CLK (10.691, 11.422, 10.191, 10.813) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[17]/opit_0_inv_MUX4TO1Q/CLK (10.703, 11.433, 10.202, 10.824) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[18]/opit_0_inv_MUX4TO1Q/CLK (10.685, 11.415, 10.184, 10.806) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[19]/opit_0_inv_MUX4TO1Q/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[20]/opit_0_inv_MUX4TO1Q/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[21]/opit_0_inv_MUX4TO1Q/CLK (10.703, 11.433, 10.202, 10.824) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[22]/opit_0_inv_MUX4TO1Q/CLK (10.691, 11.422, 10.191, 10.813) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[23]/opit_0_inv_MUX4TO1Q/CLK (10.691, 11.422, 10.191, 10.813) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[24]/opit_0_inv_MUX4TO1Q/CLK (10.703, 11.433, 10.202, 10.824) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[25]/opit_0_inv_MUX4TO1Q/CLK (10.685, 11.415, 10.184, 10.806) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[26]/opit_0_inv_MUX4TO1Q/CLK (10.691, 11.422, 10.191, 10.813) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[27]/opit_0_inv_MUX4TO1Q/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_id[0]/opit_0_inv_L5Q_perm/CLK (10.679, 11.409, 10.178, 10.800) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_id[1]/opit_0_inv_L5Q_perm/CLK (10.679, 11.409, 10.178, 10.800) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_id[2]/opit_0_inv_L5Q_perm/CLK (10.679, 11.409, 10.178, 10.800) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_id[3]/opit_0_inv_L5Q_perm/CLK (10.679, 11.409, 10.178, 10.800) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_len[0]/opit_0_inv_L5Q_perm/CLK (10.709, 11.440, 10.209, 10.831) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_len[1]/opit_0_inv_MUX4TO1Q/CLK (10.709, 11.440, 10.209, 10.831) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_len[2]/opit_0_inv_L5Q_perm/CLK (10.690, 11.420, 10.190, 10.812) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_len[3]/opit_0_inv_MUX4TO1Q/CLK (10.690, 11.420, 10.190, 10.812) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_new_row/opit_0_inv_MUX4TO1Q/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_new_valid/opit_0_inv_L5Q_perm/CLK (10.721, 11.451, 10.220, 10.842) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_pre_row/opit_0_inv_MUX4TO1Q/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_refresh/opit_0_inv_L5Q_perm/CLK (10.721, 11.451, 10.220, 10.842) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_write/opit_0_inv_L5Q_perm/CLK (10.676, 11.406, 10.175, 10.797) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[0]/opit_0_inv_L5Q_perm/CLK (10.708, 11.439, 10.208, 10.830) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[1]/opit_0_inv_L5Q_perm/CLK (10.717, 11.448, 10.216, 10.839) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[2]/opit_0_inv_L5Q_perm/CLK (10.708, 11.439, 10.208, 10.830) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[3]/opit_0_inv_L5Q_perm/CLK (10.717, 11.448, 10.216, 10.839) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[4]/opit_0_inv_L5Q_perm/CLK (10.708, 11.439, 10.208, 10.830) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[5]/opit_0_inv_L5Q_perm/CLK (10.717, 11.448, 10.216, 10.839) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[6]/opit_0_inv_L5Q_perm/CLK (10.708, 11.439, 10.208, 10.830) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[7]/opit_0_inv_L5Q_perm/CLK (10.717, 11.448, 10.216, 10.839) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/r_init/opit_0_inv_L5Q_perm/CLK (10.723, 11.454, 10.222, 10.845) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.715, 11.446, 10.214, 10.837) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[5]/opit_0_inv_L5Q_perm/CLK (10.700, 11.431, 10.200, 10.822) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[6]/opit_0_inv_L5Q_perm/CLK (10.700, 11.431, 10.200, 10.822) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[7]/opit_0_inv_L5Q_perm/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[8]/opit_0_inv_L5Q_perm/CLK (10.700, 11.431, 10.200, 10.822) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[9]/opit_0_inv_L5Q_perm/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[10]/opit_0_inv_L5Q_perm/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[11]/opit_0_inv_L5Q_perm/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[12]/opit_0_inv_L5Q_perm/CLK (10.700, 11.431, 10.200, 10.822) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_req/opit_0_inv_L5Q_perm/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[13]/opit_0_inv_L5Q_perm/CLK (10.715, 11.446, 10.214, 10.837) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[14]/opit_0_inv_L5Q_perm/CLK (10.715, 11.446, 10.214, 10.837) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[15]/opit_0_inv_L5Q_perm/CLK (10.685, 11.415, 10.184, 10.806) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[16]/opit_0_inv_L5Q_perm/CLK (10.691, 11.422, 10.191, 10.813) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[17]/opit_0_inv_L5Q_perm/CLK (10.685, 11.415, 10.184, 10.806) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[18]/opit_0_inv_L5Q_perm/CLK (10.685, 11.415, 10.184, 10.806) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[19]/opit_0_inv_L5Q_perm/CLK (10.715, 11.446, 10.214, 10.837) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[20]/opit_0_inv_L5Q_perm/CLK (10.715, 11.446, 10.214, 10.837) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[21]/opit_0_inv_L5Q_perm/CLK (10.685, 11.415, 10.184, 10.806) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[22]/opit_0_inv_L5Q_perm/CLK (10.691, 11.422, 10.191, 10.813) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[23]/opit_0_inv_L5Q_perm/CLK (10.685, 11.415, 10.184, 10.806) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[24]/opit_0_inv_L5Q_perm/CLK (10.691, 11.422, 10.191, 10.813) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[25]/opit_0_inv_L5Q_perm/CLK (10.685, 11.415, 10.184, 10.806) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[26]/opit_0_inv_L5Q_perm/CLK (10.691, 11.422, 10.191, 10.813) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[27]/opit_0_inv_L5Q_perm/CLK (10.715, 11.446, 10.214, 10.837) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_cmd_ready/opit_0_inv_L5Q_perm/CLK (10.723, 11.454, 10.222, 10.845) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/cnt[0]/opit_0_inv_L5Q_perm/CLK (10.714, 11.444, 10.213, 10.835) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/cnt[1]/opit_0_inv_L5Q_perm/CLK (10.723, 11.454, 10.222, 10.845) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/cnt[2]/opit_0_inv_MUX4TO1Q/CLK (10.723, 11.454, 10.222, 10.845) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/cnt[3]/opit_0_inv_L6Q_perm/CLK (10.723, 11.454, 10.222, 10.845) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[0]/opit_0_inv_L5Q_perm/CLK (10.690, 11.420, 10.190, 10.812) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[1]/opit_0_inv_L5Q_perm/CLK (10.690, 11.420, 10.190, 10.812) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[2]/opit_0_inv_L5Q_perm/CLK (10.690, 11.420, 10.190, 10.812) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[3]/opit_0_inv_L5Q_perm/CLK (10.700, 11.431, 10.200, 10.822) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[4]/opit_0_inv_L5Q_perm/CLK (10.694, 11.424, 10.193, 10.815) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[5]/opit_0_inv_L5Q_perm/CLK (10.694, 11.424, 10.193, 10.815) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[6]/opit_0_inv_L5Q_perm/CLK (10.700, 11.431, 10.200, 10.822) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[7]/opit_0_inv_L5Q_perm/CLK (10.694, 11.424, 10.193, 10.815) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[8]/opit_0_inv_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[9]/opit_0_inv_L5Q_perm/CLK (10.694, 11.424, 10.193, 10.815) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[10]/opit_0_inv/CLK (10.721, 11.451, 10.220, 10.842) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[11]/opit_0_inv/CLK (10.721, 11.451, 10.220, 10.842) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[12]/opit_0_inv/CLK (10.721, 11.451, 10.220, 10.842) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[13]/opit_0_inv/CLK (10.705, 11.435, 10.204, 10.826) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[14]/opit_0_inv/CLK (10.705, 11.435, 10.204, 10.826) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[15]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[16]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[17]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[18]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[19]/opit_0_inv/CLK (10.705, 11.435, 10.204, 10.826) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[20]/opit_0_inv/CLK (10.705, 11.435, 10.204, 10.826) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[21]/opit_0_inv/CLK (10.705, 11.435, 10.204, 10.826) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[22]/opit_0_inv/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[23]/opit_0_inv/CLK (10.721, 11.451, 10.220, 10.842) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[24]/opit_0_inv/CLK (10.721, 11.451, 10.220, 10.842) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[25]/opit_0_inv/CLK (10.721, 11.451, 10.220, 10.842) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[26]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[27]/opit_0_inv/CLK (10.705, 11.435, 10.204, 10.826) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_cmd[0]/opit_0_inv_L5Q_perm/CLK (10.726, 11.457, 10.225, 10.848) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_cmd[1]/opit_0_inv_L5Q_perm/CLK (10.726, 11.457, 10.225, 10.848) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_cmd[2]/opit_0_inv/CLK (10.726, 11.457, 10.225, 10.848) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_cmd[3]/opit_0_inv_L5Q_perm/CLK (10.726, 11.457, 10.225, 10.848) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_en/opit_0_inv_L5Q_perm/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_id[0]/opit_0_inv/CLK (10.708, 11.439, 10.208, 10.830) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_id[1]/opit_0_inv/CLK (10.708, 11.439, 10.208, 10.830) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_id[2]/opit_0_inv/CLK (10.708, 11.439, 10.208, 10.830) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_id[3]/opit_0_inv/CLK (10.708, 11.439, 10.208, 10.830) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_tworw/opit_0_inv_L5Q_perm/CLK (10.723, 11.454, 10.222, 10.845) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[0]/opit_0_inv/CLK (10.687, 11.417, 10.186, 10.808) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[1]/opit_0_inv/CLK (10.687, 11.417, 10.186, 10.808) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[2]/opit_0_inv/CLK (10.687, 11.417, 10.186, 10.808) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[3]/opit_0_inv/CLK (10.703, 11.433, 10.202, 10.824) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[4]/opit_0_inv/CLK (10.703, 11.433, 10.202, 10.824) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[5]/opit_0_inv/CLK (10.699, 11.430, 10.199, 10.821) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[6]/opit_0_inv/CLK (10.679, 11.409, 10.178, 10.800) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[7]/opit_0_inv/CLK (10.687, 11.417, 10.186, 10.808) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[8]/opit_0_inv/CLK (10.688, 11.418, 10.187, 10.809) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[9]/opit_0_inv/CLK (10.703, 11.433, 10.202, 10.824) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[10]/opit_0_inv/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[11]/opit_0_inv/CLK (10.703, 11.433, 10.202, 10.824) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[12]/opit_0_inv/CLK (10.703, 11.433, 10.202, 10.824) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[13]/opit_0_inv/CLK (10.688, 11.418, 10.187, 10.809) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[14]/opit_0_inv/CLK (10.688, 11.418, 10.187, 10.809) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[15]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[16]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[17]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[18]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[19]/opit_0_inv/CLK (10.703, 11.433, 10.202, 10.824) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[20]/opit_0_inv/CLK (10.688, 11.418, 10.187, 10.809) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[21]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[22]/opit_0_inv/CLK (10.703, 11.433, 10.202, 10.824) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[23]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[24]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[25]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[26]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[27]/opit_0_inv/CLK (10.688, 11.418, 10.187, 10.809) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_done/opit_0_inv_L5Q/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/rw_diff/opit_0_inv_L5Q_perm/CLK (10.708, 11.439, 10.208, 10.830) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[0]/opit_0_inv_L5Q_perm/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[1]/opit_0_inv_L5Q_perm/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[2]/opit_0_inv_L5Q_perm/CLK (10.721, 11.451, 10.220, 10.842) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[3]/opit_0_inv_L5Q_perm/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[4]/opit_0_inv_L5Q_perm/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[5]/opit_0_inv/CLK (10.721, 11.451, 10.220, 10.842) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[0].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[0].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[0].trc_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[0].trc_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[1].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[1].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[1].trc_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[1].trc_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[2].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[2].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[2].trc_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[2].trc_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[3].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[3].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[3].trc_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[3].trc_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[4].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[4].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[4].trc_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[4].trc_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[5].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[5].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[5].trc_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[5].trc_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[6].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[6].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[6].trc_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[6].trc_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[7].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[7].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[7].trc_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[7].trc_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[6]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[8]/opit_0_inv/CLK (10.694, 11.424, 10.193, 10.815) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[9]/opit_0_inv/CLK (10.694, 11.424, 10.193, 10.815) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[10]/opit_0_inv/CLK (10.679, 11.409, 10.178, 10.800) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[11]/opit_0_inv/CLK (10.679, 11.409, 10.178, 10.800) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[12]/opit_0_inv/CLK (10.696, 11.426, 10.195, 10.817) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[13]/opit_0_inv/CLK (10.679, 11.409, 10.178, 10.800) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[14]/opit_0_inv/CLK (10.694, 11.424, 10.193, 10.815) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[15]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[16]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[17]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[18]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[19]/opit_0_inv/CLK (10.696, 11.426, 10.195, 10.817) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[20]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[21]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[22]/opit_0_inv/CLK (10.696, 11.426, 10.195, 10.817) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[23]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[24]/opit_0_inv/CLK (10.696, 11.426, 10.195, 10.817) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[25]/opit_0_inv/CLK (10.679, 11.409, 10.178, 10.800) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[26]/opit_0_inv/CLK (10.696, 11.426, 10.195, 10.817) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[27]/opit_0_inv/CLK (10.694, 11.424, 10.193, 10.815) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[28]/opit_0_inv/CLK (10.694, 11.424, 10.193, 10.815) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[29]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[30]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[31]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[32]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[33]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[34]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[35]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[36]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[38]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[39]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[40]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[41]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[42]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_valid_d1/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/cmd_act_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/ctrl_back_rdy/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/cmd_rd_pass/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/r_cnt_pass/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_cmd_accepted_l/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_cmd_accepted_m/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_cmd_act/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[4]/opit_0_inv/CLK (10.694, 11.424, 10.193, 10.815) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[5]/opit_0_inv/CLK (10.694, 11.424, 10.193, 10.815) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[6]/opit_0_inv/CLK (10.694, 11.424, 10.193, 10.815) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[7]/opit_0_inv/CLK (10.714, 11.444, 10.213, 10.835) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[8]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[9]/opit_0_inv/CLK (10.699, 11.430, 10.199, 10.821) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[10]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[11]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[12]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[13]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[14]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[15]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[16]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[17]/opit_0_inv/CLK (10.714, 11.444, 10.213, 10.835) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[18]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[19]/opit_0_inv/CLK (10.699, 11.430, 10.199, 10.821) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[20]/opit_0_inv/CLK (10.694, 11.424, 10.193, 10.815) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[21]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[22]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[23]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[24]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[25]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[26]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[27]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_cmd[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_cmd[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_cmd[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_cmd[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_id[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_id[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_id[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_id[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[5]/opit_0_inv_L5Q_perm/CLK (10.699, 11.430, 10.199, 10.821) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[8]/opit_0_inv_L5Q_perm/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[9]/opit_0_inv_L5Q_perm/CLK (10.676, 11.406, 10.175, 10.797) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[10]/opit_0_inv_L5Q_perm/CLK (10.676, 11.406, 10.175, 10.797) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[11]/opit_0_inv_L5Q_perm/CLK (10.685, 11.415, 10.184, 10.806) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[12]/opit_0_inv_L5Q_perm/CLK (10.687, 11.417, 10.186, 10.808) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[13]/opit_0_inv_L5Q_perm/CLK (10.685, 11.415, 10.184, 10.806) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[14]/opit_0_inv_L5Q_perm/CLK (10.699, 11.430, 10.199, 10.821) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[15]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[16]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[17]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[18]/opit_0_inv_L5Q_perm/CLK (10.699, 11.430, 10.199, 10.821) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[19]/opit_0_inv_L5Q_perm/CLK (10.687, 11.417, 10.186, 10.808) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[20]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[21]/opit_0_inv_L5Q_perm/CLK (10.714, 11.444, 10.213, 10.835) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[22]/opit_0_inv_L5Q_perm/CLK (10.687, 11.417, 10.186, 10.808) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[23]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[24]/opit_0_inv_L5Q_perm/CLK (10.676, 11.406, 10.175, 10.797) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[25]/opit_0_inv_L5Q_perm/CLK (10.676, 11.406, 10.175, 10.797) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[26]/opit_0_inv_L5Q_perm/CLK (10.687, 11.417, 10.186, 10.808) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[27]/opit_0_inv_L5Q_perm/CLK (10.699, 11.430, 10.199, 10.821) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[28]/opit_0_inv_L5Q_perm/CLK (10.714, 11.444, 10.213, 10.835) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[29]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[30]/opit_0_inv_L5Q_perm/CLK (10.714, 11.444, 10.213, 10.835) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[31]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[32]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[33]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[34]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[35]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[36]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[38]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[39]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[40]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[41]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[42]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_valid/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[1].mcdq_tfaw/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[1].mcdq_tfaw/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[1].mcdq_tfaw/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[1].mcdq_tfaw/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[1].mcdq_tfaw/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/cnt_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[3]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt0[1]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/cmd_wr_pass/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_2/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_3/ram16x1d/WCLK (10.732, 11.463, 10.231, 10.854) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_4/ram16x1d/WCLK (10.732, 11.463, 10.231, 10.854) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_5/ram16x1d/WCLK (10.714, 11.444, 10.213, 10.835) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_6/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_7/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_8/ram16x1d/WCLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_9/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_10/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_11/ram16x1d/WCLK (10.674, 11.403, 10.173, 10.794) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_12/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_13/ram16x1d/WCLK (10.674, 11.403, 10.173, 10.794) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_14/ram16x1d/WCLK (10.676, 11.406, 10.175, 10.797) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_15/ram16x1d/WCLK (10.715, 11.446, 10.214, 10.837) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_16/ram16x1d/WCLK (10.715, 11.446, 10.214, 10.837) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_17/ram16x1d/WCLK (10.715, 11.446, 10.214, 10.837) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_18/ram16x1d/WCLK (10.714, 11.444, 10.213, 10.835) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_19/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_20/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_21/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_22/ram16x1d/WCLK (10.676, 11.406, 10.175, 10.797) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_23/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_24/ram16x1d/WCLK (10.676, 11.406, 10.175, 10.797) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_25/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_26/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_27/ram16x1d/WCLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_28/ram16x1d/WCLK (10.714, 11.444, 10.213, 10.835) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_29/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_30/ram16x1d/WCLK (10.714, 11.444, 10.213, 10.835) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_31/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_32/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_33/ram16x1d/WCLK (10.732, 11.463, 10.231, 10.854) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_34/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_35/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_36/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_38/ram16x1d/WCLK (10.732, 11.463, 10.231, 10.854) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_39/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_40/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_41/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_42/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.raddr_msb/opit_0_inv_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[1]/opit_0_inv_A2Q21/CLK (10.682, 11.412, 10.182, 10.804) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[3]/opit_0_inv_A2Q21/CLK (10.682, 11.412, 10.182, 10.804) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[4]/opit_0_inv_AQ/CLK (10.688, 11.418, 10.187, 10.809) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_almost_full/opit_0_inv_MUX4TO1Q/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_rempty/opit_0_inv_AQ_perm/CLK (10.688, 11.418, 10.187, 10.809) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_wfull/opit_0_inv_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.waddr_msb/opit_0_inv_L5Q_perm/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK (10.691, 11.422, 10.191, 10.813) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[3]/opit_0_inv_A2Q21/CLK (10.691, 11.422, 10.191, 10.813) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[4]/opit_0_inv_AQ/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_2/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_3/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_4/ram16x1d/WCLK (10.717, 11.448, 10.216, 10.839) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_5/ram16x1d/WCLK (10.717, 11.448, 10.216, 10.839) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_6/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_7/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_8/ram16x1d/WCLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_9/ram16x1d/WCLK (10.670, 11.400, 10.169, 10.791) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_10/ram16x1d/WCLK (10.670, 11.400, 10.169, 10.791) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_11/ram16x1d/WCLK (10.681, 11.411, 10.181, 10.802) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_12/ram16x1d/WCLK (10.681, 11.411, 10.181, 10.802) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_13/ram16x1d/WCLK (10.670, 11.400, 10.169, 10.791) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_14/ram16x1d/WCLK (10.681, 11.411, 10.181, 10.802) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_15/ram16x1d/WCLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_16/ram16x1d/WCLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_17/ram16x1d/WCLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_18/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_19/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_20/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_21/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_22/ram16x1d/WCLK (10.681, 11.411, 10.181, 10.802) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_23/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_24/ram16x1d/WCLK (10.687, 11.417, 10.186, 10.808) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_25/ram16x1d/WCLK (10.670, 11.400, 10.169, 10.791) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_26/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_27/ram16x1d/WCLK (10.703, 11.433, 10.202, 10.824) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_28/ram16x1d/WCLK (10.717, 11.448, 10.216, 10.839) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_29/ram16x1d/WCLK (10.687, 11.417, 10.186, 10.808) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_30/ram16x1d/WCLK (10.717, 11.448, 10.216, 10.839) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_31/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_32/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_33/ram16x1d/WCLK (10.723, 11.454, 10.222, 10.845) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_34/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_35/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_36/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_38/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_39/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_40/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_41/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_42/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.raddr_msb/opit_0_inv_L5Q_perm/CLK (10.708, 11.439, 10.208, 10.830) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[1]/opit_0_inv_A2Q21/CLK (10.717, 11.448, 10.216, 10.839) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[3]/opit_0_inv_A2Q21/CLK (10.717, 11.448, 10.216, 10.839) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[4]/opit_0_inv_AQ/CLK (10.723, 11.454, 10.222, 10.845) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_almost_full/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_rempty/opit_0_inv_AQ_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_wfull/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.waddr_msb/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK (10.717, 11.448, 10.216, 10.839) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[3]/opit_0_inv_A2Q21/CLK (10.717, 11.448, 10.216, 10.839) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[4]/opit_0_inv_AQ/CLK (10.723, 11.454, 10.222, 10.845) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_a_valid/opit_0_inv_MUX4TO1Q/CLK (10.708, 11.439, 10.208, 10.830) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_b_valid/opit_0_inv_L5Q_perm/CLK (10.723, 11.454, 10.222, 10.845) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[4]/opit_0_inv/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[5]/opit_0_inv/CLK (10.717, 11.448, 10.216, 10.839) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[6]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[8]/opit_0_inv/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[9]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[10]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[11]/opit_0_inv/CLK (10.674, 11.403, 10.173, 10.794) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[12]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[13]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[14]/opit_0_inv/CLK (10.682, 11.412, 10.182, 10.804) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[15]/opit_0_inv/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[16]/opit_0_inv/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[17]/opit_0_inv/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[18]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[19]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[20]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[21]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[22]/opit_0_inv/CLK (10.690, 11.420, 10.190, 10.812) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[23]/opit_0_inv/CLK (10.690, 11.420, 10.190, 10.812) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[24]/opit_0_inv/CLK (10.690, 11.420, 10.190, 10.812) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[25]/opit_0_inv/CLK (10.690, 11.420, 10.190, 10.812) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[26]/opit_0_inv/CLK (10.690, 11.420, 10.190, 10.812) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[27]/opit_0_inv/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[28]/opit_0_inv/CLK (10.717, 11.448, 10.216, 10.839) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[29]/opit_0_inv/CLK (10.690, 11.420, 10.190, 10.812) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[30]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[31]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[32]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[33]/opit_0_inv/CLK (10.717, 11.448, 10.216, 10.839) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[34]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[35]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[36]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[38]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[39]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[40]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[41]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[42]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[4]/opit_0_inv/CLK (10.726, 11.457, 10.225, 10.848) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[5]/opit_0_inv/CLK (10.726, 11.457, 10.225, 10.848) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[6]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[8]/opit_0_inv/CLK (10.703, 11.433, 10.202, 10.824) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[9]/opit_0_inv/CLK (10.670, 11.400, 10.169, 10.791) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[10]/opit_0_inv/CLK (10.670, 11.400, 10.169, 10.791) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[11]/opit_0_inv/CLK (10.670, 11.400, 10.169, 10.791) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[12]/opit_0_inv/CLK (10.690, 11.420, 10.190, 10.812) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[13]/opit_0_inv/CLK (10.670, 11.400, 10.169, 10.791) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[14]/opit_0_inv/CLK (10.703, 11.433, 10.202, 10.824) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[15]/opit_0_inv/CLK (10.726, 11.457, 10.225, 10.848) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[16]/opit_0_inv/CLK (10.726, 11.457, 10.225, 10.848) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[17]/opit_0_inv/CLK (10.726, 11.457, 10.225, 10.848) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[18]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[19]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[20]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[21]/opit_0_inv/CLK (10.705, 11.435, 10.204, 10.826) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[22]/opit_0_inv/CLK (10.690, 11.420, 10.190, 10.812) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[23]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[24]/opit_0_inv/CLK (10.690, 11.420, 10.190, 10.812) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[25]/opit_0_inv/CLK (10.670, 11.400, 10.169, 10.791) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[26]/opit_0_inv/CLK (10.690, 11.420, 10.190, 10.812) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[27]/opit_0_inv/CLK (10.703, 11.433, 10.202, 10.824) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[28]/opit_0_inv/CLK (10.726, 11.457, 10.225, 10.848) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[29]/opit_0_inv/CLK (10.705, 11.435, 10.204, 10.826) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[30]/opit_0_inv/CLK (10.705, 11.435, 10.204, 10.826) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[31]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[32]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[33]/opit_0_inv/CLK (10.705, 11.435, 10.204, 10.826) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[34]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[35]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[36]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[38]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[39]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[40]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[41]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[42]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/poll/opit_0_inv_L5Q_perm/CLK (10.723, 11.454, 10.222, 10.845) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/rd_poll/opit_0_inv_L5Q_perm/CLK (10.723, 11.454, 10.222, 10.845) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/rd_poll_d/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[4]/opit_0_inv_L5Q_perm/CLK (10.732, 11.463, 10.231, 10.854) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[5]/opit_0_inv_L5Q_perm/CLK (10.708, 11.439, 10.208, 10.830) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[8]/opit_0_inv_L5Q_perm/CLK (10.721, 11.451, 10.220, 10.842) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[9]/opit_0_inv_L5Q_perm/CLK (10.685, 11.415, 10.184, 10.806) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[10]/opit_0_inv_L5Q_perm/CLK (10.685, 11.415, 10.184, 10.806) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[11]/opit_0_inv_L5Q_perm/CLK (10.685, 11.415, 10.184, 10.806) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[12]/opit_0_inv_L5Q_perm/CLK (10.681, 11.411, 10.181, 10.802) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[13]/opit_0_inv_L5Q_perm/CLK (10.685, 11.415, 10.184, 10.806) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[14]/opit_0_inv_L5Q_perm/CLK (10.699, 11.430, 10.199, 10.821) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[15]/opit_0_inv_L5Q_perm/CLK (10.721, 11.451, 10.220, 10.842) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[16]/opit_0_inv_L5Q_perm/CLK (10.721, 11.451, 10.220, 10.842) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[17]/opit_0_inv_L5Q_perm/CLK (10.721, 11.451, 10.220, 10.842) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[18]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[19]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[20]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[21]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[22]/opit_0_inv_L5Q_perm/CLK (10.681, 11.411, 10.181, 10.802) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[23]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[24]/opit_0_inv_L5Q_perm/CLK (10.681, 11.411, 10.181, 10.802) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[25]/opit_0_inv_L5Q_perm/CLK (10.681, 11.411, 10.181, 10.802) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[26]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[27]/opit_0_inv_L5Q_perm/CLK (10.699, 11.430, 10.199, 10.821) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[28]/opit_0_inv_L5Q_perm/CLK (10.699, 11.430, 10.199, 10.821) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[29]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[30]/opit_0_inv_L5Q_perm/CLK (10.699, 11.430, 10.199, 10.821) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[31]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[32]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[33]/opit_0_inv_L5Q_perm/CLK (10.732, 11.463, 10.231, 10.854) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[34]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[35]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[36]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[38]/opit_0_inv_L5Q_perm/CLK (10.732, 11.463, 10.231, 10.854) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[39]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[40]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[41]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[42]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_valid/opit_0_inv_L5Q_perm/CLK (10.732, 11.463, 10.231, 10.854) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[4]/opit_0_inv_L5Q_perm/CLK (10.705, 11.435, 10.204, 10.826) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[6]/opit_0_inv_L5Q_perm/CLK (10.705, 11.435, 10.204, 10.826) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[7]/opit_0_inv_L5Q_perm/CLK (10.705, 11.435, 10.204, 10.826) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[9]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[10]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[11]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[12]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[13]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[14]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[4]/opit_0_inv_L5Q_perm/CLK (10.699, 11.430, 10.199, 10.821) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[5]/opit_0_inv_L5Q_perm/CLK (10.705, 11.435, 10.204, 10.826) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[6]/opit_0_inv_L5Q_perm/CLK (10.699, 11.430, 10.199, 10.821) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[7]/opit_0_inv_L5Q_perm/CLK (10.714, 11.444, 10.213, 10.835) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[9]/opit_0_inv_L5Q_perm/CLK (10.708, 11.439, 10.208, 10.830) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_l[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_l[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_l[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_m[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_m[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_m[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_l[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_l[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_l[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_l[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_m[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_m[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_m[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_m[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rvld/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_wvld_l/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_wvld_m/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[6]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[7]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[9]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[10]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[11]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[12]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[13]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[14]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[15]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[16]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[17]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[18]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[19]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[20]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[21]/opit_0_inv_L5Q_perm/CLK (10.705, 11.435, 10.204, 10.826) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[22]/opit_0_inv_L5Q_perm/CLK (10.705, 11.435, 10.204, 10.826) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[23]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[24]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[25]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[26]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_bank[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_bank[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_bank[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_bank[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_bank[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_bank[5]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_cas_n[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_cas_n[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_cs_n[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_cs_n[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_odt_reg[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_odt_reg_1[0]/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_ras_n[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_ras_n[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_we_n[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_we_n[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[6]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[8]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[9]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[10]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[11]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[12]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[13]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[14]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[15]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[16]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[17]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[18]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[19]/opit_0_inv/CLK (10.682, 11.412, 10.182, 10.804) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[20]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[21]/opit_0_inv/CLK (10.714, 11.444, 10.213, 10.835) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[22]/opit_0_inv/CLK (10.714, 11.444, 10.213, 10.835) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[23]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[24]/opit_0_inv/CLK (10.699, 11.430, 10.199, 10.821) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[25]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[26]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_bank[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_bank[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_bank[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_bank[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_bank[4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_bank[5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_cas_n[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_cas_n[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_cke[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_cs_n[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_cs_n[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_odt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_odt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_ras_n[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_ras_n[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_we_n[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_we_n[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/r_brd_m/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/r_bwr_m/opit_0_inv_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/fifo_vld/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_0/ram32x1dp/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram32x1dp/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_2/ram32x1dp/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_3/ram32x1dp/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.raddr_msb/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[1]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_rempty/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_wfull/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.waddr_msb/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/rd_data_ff1[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/rd_data_ff1[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/rd_data_ff1[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/rd_data_ff1[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/double_wr/opit_0_inv_L5Q_perm/CLK (10.685, 11.415, 10.184, 10.806) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[0]/opit_0_inv_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[4]/opit_0_inv_L5Q_perm/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[5]/opit_0_inv_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[6]/opit_0_inv_L5Q_perm/CLK (10.694, 11.424, 10.193, 10.815) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[7]/opit_0_inv_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[8]/opit_0_inv_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[9]/opit_0_inv_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[10]/opit_0_inv_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[11]/opit_0_inv_L5Q_perm/CLK (10.714, 11.444, 10.213, 10.835) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[12]/opit_0_inv_L5Q_perm/CLK (10.714, 11.444, 10.213, 10.835) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[13]/opit_0_inv_L5Q_perm/CLK (10.714, 11.444, 10.213, 10.835) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[14]/opit_0_inv_L5Q_perm/CLK (10.714, 11.444, 10.213, 10.835) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[15]/opit_0_inv_L5Q_perm/CLK (10.703, 11.433, 10.202, 10.824) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[16]/opit_0_inv_L5Q_perm/CLK (10.703, 11.433, 10.202, 10.824) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[17]/opit_0_inv_L5Q_perm/CLK (10.703, 11.433, 10.202, 10.824) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[18]/opit_0_inv_L5Q_perm/CLK (10.717, 11.448, 10.216, 10.839) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[19]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[20]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[21]/opit_0_inv_L5Q_perm/CLK (10.717, 11.448, 10.216, 10.839) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[22]/opit_0_inv_L5Q_perm/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[23]/opit_0_inv_L5Q_perm/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[24]/opit_0_inv_L5Q_perm/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[25]/opit_0_inv_L5Q_perm/CLK (10.703, 11.433, 10.202, 10.824) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[26]/opit_0_inv_L5Q_perm/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[27]/opit_0_inv_L5Q_perm/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[28]/opit_0_inv_L5Q_perm/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[29]/opit_0_inv_L5Q_perm/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[30]/opit_0_inv_L5Q_perm/CLK (10.703, 11.433, 10.202, 10.824) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[31]/opit_0_inv_L5Q_perm/CLK (10.703, 11.433, 10.202, 10.824) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[32]/opit_0_inv_L5Q_perm/CLK (10.717, 11.448, 10.216, 10.839) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[33]/opit_0_inv_L5Q_perm/CLK (10.717, 11.448, 10.216, 10.839) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[34]/opit_0_inv_L5Q_perm/CLK (10.703, 11.433, 10.202, 10.824) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[35]/opit_0_inv_L5Q_perm/CLK (10.703, 11.433, 10.202, 10.824) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[37]/opit_0_inv/CLK (10.688, 11.418, 10.187, 10.809) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[0]/opit_0_inv_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[4]/opit_0_inv_L5Q_perm/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[5]/opit_0_inv_L5Q_perm/CLK (10.694, 11.424, 10.193, 10.815) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[6]/opit_0_inv_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[7]/opit_0_inv_L5Q_perm/CLK (10.694, 11.424, 10.193, 10.815) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[8]/opit_0_inv_L5Q_perm/CLK (10.694, 11.424, 10.193, 10.815) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[9]/opit_0_inv_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[10]/opit_0_inv_L5Q_perm/CLK (10.694, 11.424, 10.193, 10.815) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[11]/opit_0_inv_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[12]/opit_0_inv_L5Q_perm/CLK (10.708, 11.439, 10.208, 10.830) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[13]/opit_0_inv_L5Q_perm/CLK (10.705, 11.435, 10.204, 10.826) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[14]/opit_0_inv_L5Q_perm/CLK (10.705, 11.435, 10.204, 10.826) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[15]/opit_0_inv_L5Q_perm/CLK (10.708, 11.439, 10.208, 10.830) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[16]/opit_0_inv_L5Q_perm/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[17]/opit_0_inv_L5Q_perm/CLK (10.708, 11.439, 10.208, 10.830) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[18]/opit_0_inv_L5Q_perm/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[19]/opit_0_inv_L5Q_perm/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[20]/opit_0_inv_L5Q_perm/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[21]/opit_0_inv_L5Q_perm/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[22]/opit_0_inv_L5Q_perm/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[23]/opit_0_inv_L5Q_perm/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[24]/opit_0_inv_L5Q_perm/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[25]/opit_0_inv_L5Q_perm/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[26]/opit_0_inv_L5Q_perm/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[27]/opit_0_inv_L5Q_perm/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[28]/opit_0_inv_L5Q_perm/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[29]/opit_0_inv_L5Q_perm/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[30]/opit_0_inv_L5Q_perm/CLK (10.708, 11.439, 10.208, 10.830) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[31]/opit_0_inv_L5Q_perm/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[32]/opit_0_inv_L5Q_perm/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[33]/opit_0_inv_L5Q_perm/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[34]/opit_0_inv_L5Q_perm/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[35]/opit_0_inv_L5Q_perm/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[37]/opit_0_inv_L5Q_perm/CLK (10.691, 11.422, 10.191, 10.813) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_valid_0/opit_0_inv_L5Q_perm/CLK (10.699, 11.430, 10.199, 10.821) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_valid_1/opit_0_inv_L5Q_perm/CLK (10.699, 11.430, 10.199, 10.821) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/rptr/opit_0_inv_L5Q_perm/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/next_len[0]/opit_0_inv_MUX4TO1Q/CLK (10.696, 11.426, 10.195, 10.817) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/next_len[1]/opit_0_inv_MUX4TO1Q/CLK (10.696, 11.426, 10.195, 10.817) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/next_len[2]/opit_0_inv_L5Q_perm/CLK (10.696, 11.426, 10.195, 10.817) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/next_len[3]/opit_0_inv_L5Q_perm/CLK (10.696, 11.426, 10.195, 10.817) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][0]/opit_0_inv/CLK (10.714, 11.444, 10.213, 10.835) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][1]/opit_0_inv/CLK (10.714, 11.444, 10.213, 10.835) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][2]/opit_0_inv/CLK (10.690, 11.420, 10.190, 10.812) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][3]/opit_0_inv/CLK (10.714, 11.444, 10.213, 10.835) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][6]/opit_0_inv/CLK (10.714, 11.444, 10.213, 10.835) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][7]/opit_0_inv/CLK (10.714, 11.444, 10.213, 10.835) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][8]/opit_0_inv/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][9]/opit_0_inv/CLK (10.674, 11.403, 10.173, 10.794) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][10]/opit_0_inv/CLK (10.674, 11.403, 10.173, 10.794) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][11]/opit_0_inv/CLK (10.674, 11.403, 10.173, 10.794) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][12]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][13]/opit_0_inv/CLK (10.674, 11.403, 10.173, 10.794) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][14]/opit_0_inv/CLK (10.714, 11.444, 10.213, 10.835) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][0]/opit_0_inv/CLK (10.723, 11.454, 10.222, 10.845) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][1]/opit_0_inv/CLK (10.723, 11.454, 10.222, 10.845) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][2]/opit_0_inv/CLK (10.685, 11.415, 10.184, 10.806) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][3]/opit_0_inv/CLK (10.685, 11.415, 10.184, 10.806) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][4]/opit_0_inv/CLK (10.676, 11.406, 10.175, 10.797) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][5]/opit_0_inv/CLK (10.685, 11.415, 10.184, 10.806) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][6]/opit_0_inv/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][7]/opit_0_inv/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][8]/opit_0_inv/CLK (10.676, 11.406, 10.175, 10.797) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][9]/opit_0_inv/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][10]/opit_0_inv/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][11]/opit_0_inv/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][12]/opit_0_inv/CLK (10.676, 11.406, 10.175, 10.797) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][13]/opit_0_inv/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][14]/opit_0_inv/CLK (10.723, 11.454, 10.222, 10.845) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][0]/opit_0_inv/CLK (10.696, 11.426, 10.195, 10.817) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][1]/opit_0_inv/CLK (10.700, 11.431, 10.200, 10.822) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][2]/opit_0_inv/CLK (10.696, 11.426, 10.195, 10.817) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][3]/opit_0_inv/CLK (10.696, 11.426, 10.195, 10.817) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][4]/opit_0_inv/CLK (10.703, 11.433, 10.202, 10.824) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][5]/opit_0_inv/CLK (10.696, 11.426, 10.195, 10.817) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][6]/opit_0_inv/CLK (10.700, 11.431, 10.200, 10.822) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][7]/opit_0_inv/CLK (10.700, 11.431, 10.200, 10.822) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][8]/opit_0_inv/CLK (10.703, 11.433, 10.202, 10.824) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][9]/opit_0_inv/CLK (10.700, 11.431, 10.200, 10.822) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][10]/opit_0_inv/CLK (10.703, 11.433, 10.202, 10.824) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][11]/opit_0_inv/CLK (10.703, 11.433, 10.202, 10.824) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][12]/opit_0_inv/CLK (10.674, 11.403, 10.173, 10.794) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][13]/opit_0_inv/CLK (10.700, 11.431, 10.200, 10.822) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][14]/opit_0_inv/CLK (10.696, 11.426, 10.195, 10.817) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][0]/opit_0_inv/CLK (10.703, 11.433, 10.202, 10.824) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][1]/opit_0_inv/CLK (10.703, 11.433, 10.202, 10.824) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][2]/opit_0_inv/CLK (10.681, 11.411, 10.181, 10.802) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][3]/opit_0_inv/CLK (10.703, 11.433, 10.202, 10.824) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][4]/opit_0_inv/CLK (10.685, 11.415, 10.184, 10.806) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][5]/opit_0_inv/CLK (10.679, 11.409, 10.178, 10.800) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][6]/opit_0_inv/CLK (10.703, 11.433, 10.202, 10.824) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][7]/opit_0_inv/CLK (10.700, 11.431, 10.200, 10.822) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][8]/opit_0_inv/CLK (10.685, 11.415, 10.184, 10.806) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][9]/opit_0_inv/CLK (10.700, 11.431, 10.200, 10.822) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][10]/opit_0_inv/CLK (10.685, 11.415, 10.184, 10.806) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][11]/opit_0_inv/CLK (10.685, 11.415, 10.184, 10.806) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][12]/opit_0_inv/CLK (10.679, 11.409, 10.178, 10.800) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][13]/opit_0_inv/CLK (10.685, 11.415, 10.184, 10.806) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][14]/opit_0_inv/CLK (10.703, 11.433, 10.202, 10.824) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][0]/opit_0_inv/CLK (10.717, 11.448, 10.216, 10.839) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][1]/opit_0_inv/CLK (10.717, 11.448, 10.216, 10.839) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][2]/opit_0_inv/CLK (10.696, 11.426, 10.195, 10.817) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][3]/opit_0_inv/CLK (10.696, 11.426, 10.195, 10.817) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][4]/opit_0_inv/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][5]/opit_0_inv/CLK (10.679, 11.409, 10.178, 10.800) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][6]/opit_0_inv/CLK (10.679, 11.409, 10.178, 10.800) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][7]/opit_0_inv/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][8]/opit_0_inv/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][9]/opit_0_inv/CLK (10.679, 11.409, 10.178, 10.800) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][10]/opit_0_inv/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][11]/opit_0_inv/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][12]/opit_0_inv/CLK (10.676, 11.406, 10.175, 10.797) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][13]/opit_0_inv/CLK (10.679, 11.409, 10.178, 10.800) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][14]/opit_0_inv/CLK (10.696, 11.426, 10.195, 10.817) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][0]/opit_0_inv/CLK (10.723, 11.454, 10.222, 10.845) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][1]/opit_0_inv/CLK (10.723, 11.454, 10.222, 10.845) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][2]/opit_0_inv/CLK (10.670, 11.400, 10.169, 10.791) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][3]/opit_0_inv/CLK (10.723, 11.454, 10.222, 10.845) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][4]/opit_0_inv/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][5]/opit_0_inv/CLK (10.670, 11.400, 10.169, 10.791) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][6]/opit_0_inv/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][7]/opit_0_inv/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][8]/opit_0_inv/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][9]/opit_0_inv/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][10]/opit_0_inv/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][11]/opit_0_inv/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][12]/opit_0_inv/CLK (10.670, 11.400, 10.169, 10.791) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][13]/opit_0_inv/CLK (10.670, 11.400, 10.169, 10.791) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][14]/opit_0_inv/CLK (10.723, 11.454, 10.222, 10.845) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][0]/opit_0_inv/CLK (10.703, 11.433, 10.202, 10.824) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][1]/opit_0_inv/CLK (10.703, 11.433, 10.202, 10.824) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][2]/opit_0_inv/CLK (10.703, 11.433, 10.202, 10.824) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][3]/opit_0_inv/CLK (10.703, 11.433, 10.202, 10.824) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][4]/opit_0_inv/CLK (10.679, 11.409, 10.178, 10.800) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][5]/opit_0_inv/CLK (10.703, 11.433, 10.202, 10.824) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][6]/opit_0_inv/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][7]/opit_0_inv/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][8]/opit_0_inv/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][9]/opit_0_inv/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][10]/opit_0_inv/CLK (10.679, 11.409, 10.178, 10.800) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][11]/opit_0_inv/CLK (10.679, 11.409, 10.178, 10.800) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][12]/opit_0_inv/CLK (10.679, 11.409, 10.178, 10.800) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][13]/opit_0_inv/CLK (10.679, 11.409, 10.178, 10.800) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][14]/opit_0_inv/CLK (10.703, 11.433, 10.202, 10.824) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][0]/opit_0_inv/CLK (10.708, 11.439, 10.208, 10.830) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][1]/opit_0_inv/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][2]/opit_0_inv/CLK (10.708, 11.439, 10.208, 10.830) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][3]/opit_0_inv/CLK (10.708, 11.439, 10.208, 10.830) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][4]/opit_0_inv/CLK (10.690, 11.420, 10.190, 10.812) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][5]/opit_0_inv/CLK (10.674, 11.403, 10.173, 10.794) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][6]/opit_0_inv/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][7]/opit_0_inv/CLK (10.674, 11.403, 10.173, 10.794) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][8]/opit_0_inv/CLK (10.708, 11.439, 10.208, 10.830) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][9]/opit_0_inv/CLK (10.674, 11.403, 10.173, 10.794) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][10]/opit_0_inv/CLK (10.674, 11.403, 10.173, 10.794) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][11]/opit_0_inv/CLK (10.674, 11.403, 10.173, 10.794) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][12]/opit_0_inv/CLK (10.674, 11.403, 10.173, 10.794) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][13]/opit_0_inv/CLK (10.674, 11.403, 10.173, 10.794) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][14]/opit_0_inv/CLK (10.708, 11.439, 10.208, 10.830) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[0]/opit_0_inv_L5Q_perm/CLK (10.670, 11.400, 10.169, 10.791) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[1]/opit_0_inv_L5Q_perm/CLK (10.696, 11.426, 10.195, 10.817) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[2]/opit_0_inv_L5Q_perm/CLK (10.670, 11.400, 10.169, 10.791) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[3]/opit_0_inv_L5Q_perm/CLK (10.696, 11.426, 10.195, 10.817) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[4]/opit_0_inv_L5Q_perm/CLK (10.687, 11.417, 10.186, 10.808) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[5]/opit_0_inv_L5Q_perm/CLK (10.687, 11.417, 10.186, 10.808) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[6]/opit_0_inv_L5Q_perm/CLK (10.687, 11.417, 10.186, 10.808) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[7]/opit_0_inv_L5Q_perm/CLK (10.687, 11.417, 10.186, 10.808) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[8]/opit_0_inv_A2Q1/CLK (10.681, 11.411, 10.181, 10.802) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[10]/opit_0_inv_A2Q21/CLK (10.681, 11.411, 10.181, 10.802) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[12]/opit_0_inv_A2Q21/CLK (10.687, 11.417, 10.186, 10.808) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[14]/opit_0_inv_A2Q21/CLK (10.687, 11.417, 10.186, 10.808) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[16]/opit_0_inv_A2Q21/CLK (10.676, 11.406, 10.175, 10.797) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[18]/opit_0_inv_A2Q21/CLK (10.676, 11.406, 10.175, 10.797) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[20]/opit_0_inv_A2Q21/CLK (10.670, 11.400, 10.169, 10.791) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[22]/opit_0_inv_A2Q21/CLK (10.670, 11.400, 10.169, 10.791) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[24]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[26]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[27]/opit_0_inv_AQ/CLK (10.670, 11.400, 10.169, 10.791) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_data_in_valid/opit_0_inv_L5Q_perm/CLK (10.699, 11.430, 10.199, 10.821) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_id[0]/opit_0_inv_L5Q_perm/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_id[1]/opit_0_inv_L5Q_perm/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_id[2]/opit_0_inv_L5Q_perm/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_id[3]/opit_0_inv_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_len[0]/opit_0_inv_MUX4TO1Q/CLK (10.685, 11.415, 10.184, 10.806) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_len[1]/opit_0_inv_MUX4TO1Q/CLK (10.685, 11.415, 10.184, 10.806) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_len[2]/opit_0_inv_L5Q_perm/CLK (10.696, 11.426, 10.195, 10.817) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_len[3]/opit_0_inv_MUX4TO1Q/CLK (10.696, 11.426, 10.195, 10.817) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_write/opit_0_inv_L5Q_perm/CLK (10.688, 11.418, 10.187, 10.809) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/ptr/opit_0_inv_L5Q_perm/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[0]/opit_0_inv/CLK (10.726, 11.457, 10.225, 10.848) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[1]/opit_0_inv/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[2]/opit_0_inv/CLK (10.714, 11.444, 10.213, 10.835) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[3]/opit_0_inv/CLK (10.685, 11.415, 10.184, 10.806) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[4]/opit_0_inv/CLK (10.685, 11.415, 10.184, 10.806) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[5]/opit_0_inv/CLK (10.685, 11.415, 10.184, 10.806) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[6]/opit_0_inv/CLK (10.670, 11.400, 10.169, 10.791) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[7]/opit_0_inv/CLK (10.670, 11.400, 10.169, 10.791) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[8]/opit_0_inv/CLK (10.685, 11.415, 10.184, 10.806) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[9]/opit_0_inv/CLK (10.685, 11.415, 10.184, 10.806) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[10]/opit_0_inv/CLK (10.685, 11.415, 10.184, 10.806) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[11]/opit_0_inv/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[12]/opit_0_inv/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[13]/opit_0_inv/CLK (10.694, 11.424, 10.193, 10.815) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[14]/opit_0_inv/CLK (10.705, 11.435, 10.204, 10.826) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[15]/opit_0_inv/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[16]/opit_0_inv/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[17]/opit_0_inv/CLK (10.709, 11.440, 10.209, 10.831) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[18]/opit_0_inv/CLK (10.714, 11.444, 10.213, 10.835) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[19]/opit_0_inv/CLK (10.714, 11.444, 10.213, 10.835) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[20]/opit_0_inv/CLK (10.726, 11.457, 10.225, 10.848) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[21]/opit_0_inv/CLK (10.709, 11.440, 10.209, 10.831) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[22]/opit_0_inv/CLK (10.709, 11.440, 10.209, 10.831) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[23]/opit_0_inv/CLK (10.679, 11.409, 10.178, 10.800) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[24]/opit_0_inv/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[25]/opit_0_inv/CLK (10.679, 11.409, 10.178, 10.800) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[26]/opit_0_inv/CLK (10.679, 11.409, 10.178, 10.800) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[27]/opit_0_inv/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[28]/opit_0_inv/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[29]/opit_0_inv/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[30]/opit_0_inv/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[31]/opit_0_inv/CLK (10.679, 11.409, 10.178, 10.800) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[32]/opit_0_inv/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[33]/opit_0_inv/CLK (10.685, 11.415, 10.184, 10.806) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[34]/opit_0_inv/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[35]/opit_0_inv/CLK (10.709, 11.440, 10.209, 10.831) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[37]/opit_0_inv/CLK (10.685, 11.415, 10.184, 10.806) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[39]/opit_0_inv_L5Q_perm/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[40]/opit_0_inv_MUX8TO1Q/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[41]/opit_0_inv_MUX8TO1Q/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[42]/opit_0_inv_MUX8TO1Q/CLK (10.679, 11.409, 10.178, 10.800) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[43]/opit_0_inv_MUX8TO1Q/CLK (10.714, 11.444, 10.213, 10.835) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[44]/opit_0_inv_MUX8TO1Q/CLK (10.670, 11.400, 10.169, 10.791) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[45]/opit_0_inv_MUX8TO1Q/CLK (10.679, 11.409, 10.178, 10.800) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[46]/opit_0_inv_MUX8TO1Q/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[47]/opit_0_inv_MUX8TO1Q/CLK (10.709, 11.440, 10.209, 10.831) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[48]/opit_0_inv_MUX8TO1Q/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[49]/opit_0_inv_MUX8TO1Q/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[50]/opit_0_inv_MUX8TO1Q/CLK (10.679, 11.409, 10.178, 10.800) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[51]/opit_0_inv_MUX8TO1Q/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[52]/opit_0_inv_MUX8TO1Q/CLK (10.670, 11.400, 10.169, 10.791) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[53]/opit_0_inv_MUX8TO1Q/CLK (10.679, 11.409, 10.178, 10.800) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[54]/opit_0_inv_MUX8TO1Q/CLK (10.714, 11.444, 10.213, 10.835) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[0]/opit_0_inv/CLK (10.732, 11.463, 10.231, 10.854) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[1]/opit_0_inv/CLK (10.732, 11.463, 10.231, 10.854) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[2]/opit_0_inv/CLK (10.685, 11.415, 10.184, 10.806) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[3]/opit_0_inv/CLK (10.685, 11.415, 10.184, 10.806) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[4]/opit_0_inv/CLK (10.679, 11.409, 10.178, 10.800) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[5]/opit_0_inv/CLK (10.681, 11.411, 10.181, 10.802) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[6]/opit_0_inv/CLK (10.681, 11.411, 10.181, 10.802) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[7]/opit_0_inv/CLK (10.681, 11.411, 10.181, 10.802) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[8]/opit_0_inv/CLK (10.690, 11.420, 10.190, 10.812) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[9]/opit_0_inv/CLK (10.690, 11.420, 10.190, 10.812) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[10]/opit_0_inv/CLK (10.690, 11.420, 10.190, 10.812) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[11]/opit_0_inv/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[12]/opit_0_inv/CLK (10.732, 11.463, 10.231, 10.854) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[13]/opit_0_inv/CLK (10.694, 11.424, 10.193, 10.815) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[14]/opit_0_inv/CLK (10.676, 11.406, 10.175, 10.797) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[15]/opit_0_inv/CLK (10.694, 11.424, 10.193, 10.815) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[16]/opit_0_inv/CLK (10.732, 11.463, 10.231, 10.854) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[17]/opit_0_inv/CLK (10.691, 11.422, 10.191, 10.813) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[18]/opit_0_inv/CLK (10.703, 11.433, 10.202, 10.824) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[19]/opit_0_inv/CLK (10.703, 11.433, 10.202, 10.824) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[20]/opit_0_inv/CLK (10.732, 11.463, 10.231, 10.854) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[21]/opit_0_inv/CLK (10.715, 11.446, 10.214, 10.837) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[22]/opit_0_inv/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[23]/opit_0_inv/CLK (10.685, 11.415, 10.184, 10.806) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[24]/opit_0_inv/CLK (10.715, 11.446, 10.214, 10.837) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[25]/opit_0_inv/CLK (10.681, 11.411, 10.181, 10.802) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[26]/opit_0_inv/CLK (10.679, 11.409, 10.178, 10.800) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[27]/opit_0_inv/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[28]/opit_0_inv/CLK (10.691, 11.422, 10.191, 10.813) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[29]/opit_0_inv/CLK (10.714, 11.444, 10.213, 10.835) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[30]/opit_0_inv/CLK (10.715, 11.446, 10.214, 10.837) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[31]/opit_0_inv/CLK (10.696, 11.426, 10.195, 10.817) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[32]/opit_0_inv/CLK (10.714, 11.444, 10.213, 10.835) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[33]/opit_0_inv/CLK (10.681, 11.411, 10.181, 10.802) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[34]/opit_0_inv/CLK (10.715, 11.446, 10.214, 10.837) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[35]/opit_0_inv/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[37]/opit_0_inv/CLK (10.679, 11.409, 10.178, 10.800) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[39]/opit_0_inv/CLK (10.732, 11.463, 10.231, 10.854) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[40]/opit_0_inv/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[41]/opit_0_inv/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[42]/opit_0_inv/CLK (10.685, 11.415, 10.184, 10.806) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[43]/opit_0_inv/CLK (10.715, 11.446, 10.214, 10.837) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[44]/opit_0_inv/CLK (10.681, 11.411, 10.181, 10.802) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[45]/opit_0_inv/CLK (10.679, 11.409, 10.178, 10.800) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[46]/opit_0_inv/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[47]/opit_0_inv/CLK (10.691, 11.422, 10.191, 10.813) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[48]/opit_0_inv/CLK (10.714, 11.444, 10.213, 10.835) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[49]/opit_0_inv/CLK (10.715, 11.446, 10.214, 10.837) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[50]/opit_0_inv/CLK (10.696, 11.426, 10.195, 10.817) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[51]/opit_0_inv/CLK (10.714, 11.444, 10.213, 10.835) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[52]/opit_0_inv/CLK (10.679, 11.409, 10.178, 10.800) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[53]/opit_0_inv/CLK (10.679, 11.409, 10.178, 10.800) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[54]/opit_0_inv/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_valid_0/opit_0_inv_L5Q_perm/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_valid_1/opit_0_inv_L5Q_perm/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr/opit_0_inv_L5Q_perm/CLK (10.723, 11.454, 10.222, 10.845) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/wptr/opit_0_inv_L5Q_perm/CLK (10.679, 11.409, 10.178, 10.800) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/data_out[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/data_out[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_0/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram16x1d/WCLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.raddr_msb/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[1]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[4]/opit_0_inv_AQ/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_rempty/opit_0_inv_AQ_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_wfull/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.waddr_msb/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[4]/opit_0_inv_AQ/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mc3q_wdp_dcp/o_rdy/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mc3q_wdp_dcp/r_wvld[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[192]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[193]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[194]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[195]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[196]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[197]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[198]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[199]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[200]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[201]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[202]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[203]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[204]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[205]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[206]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[207]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[208]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[209]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[210]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[211]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[212]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[213]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[214]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[215]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[216]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[217]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[218]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[219]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[220]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[221]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[222]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[223]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[224]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[225]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[226]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[227]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[228]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[229]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[230]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[231]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[232]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[233]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[234]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[235]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[236]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[237]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[238]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[239]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[240]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[241]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[242]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[243]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[244]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[245]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[246]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[247]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[248]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[249]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[250]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[251]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[252]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[253]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[254]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[255]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[128]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[129]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[130]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[131]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[132]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[133]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[134]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[135]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[136]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[137]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[138]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[139]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[140]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[141]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[142]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[143]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[144]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[145]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[146]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[147]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[148]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[149]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[150]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[151]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[152]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[153]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[154]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[155]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[156]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[157]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[158]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[159]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[160]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[161]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[162]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[163]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[164]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[165]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[166]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[167]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[168]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[169]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[170]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[171]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[172]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[173]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[174]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[175]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[176]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[177]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[178]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[179]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[180]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[181]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[182]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[183]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[184]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[185]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[186]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[187]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[188]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[189]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[190]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[191]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[192]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[193]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[194]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[195]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[196]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[197]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[198]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[199]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[200]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[201]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[202]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[203]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[204]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[205]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[206]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[207]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[208]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[209]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[210]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[211]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[212]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[213]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[214]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[215]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[216]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[217]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[218]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[219]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[220]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[221]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[222]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[223]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[224]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[225]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[226]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[227]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[228]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[229]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[230]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[231]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[232]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[233]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[234]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[235]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[236]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[237]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[238]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[239]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[240]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[241]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[242]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[243]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[244]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[245]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[246]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[247]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[248]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[249]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[250]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[251]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[252]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[253]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[254]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[255]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_wdin_en[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_wvld_m/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wdin_en_dly[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[8]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[24]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[1]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[2]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[3]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[4]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[5]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[6]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[7]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[8]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[9]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[10]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[11]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[12]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[13]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[14]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[15]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[16]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[17]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[18]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[19]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[20]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[21]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[22]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[23]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[24]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[25]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[26]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[27]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[28]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[29]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[30]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[31]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[32]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[33]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[34]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[35]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[36]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[37]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[38]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[39]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[40]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[41]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[42]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[43]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[44]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[45]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[46]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[47]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[48]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[49]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[50]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[51]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[52]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[53]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[54]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[55]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[56]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[57]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[58]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[59]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[60]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[61]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[62]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[63]/opit_0_inv/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[64]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[65]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[66]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[67]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[68]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[69]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[70]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[71]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[72]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[73]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[74]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[75]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[76]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[77]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[78]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[79]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[80]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[81]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[82]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[83]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[84]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[85]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[86]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[87]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[88]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[89]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[90]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[91]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[92]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[93]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[94]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[95]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[96]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[97]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[98]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[99]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[100]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[101]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[102]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[103]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[104]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[105]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[106]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[107]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[108]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[109]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[110]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[111]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[112]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[113]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[114]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[115]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[116]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[117]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[118]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[119]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[120]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[121]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[122]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[123]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[124]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[125]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[126]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[127]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[128]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[129]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[130]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[131]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[132]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[133]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[134]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[135]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[136]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[137]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[138]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[139]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[140]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[141]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[142]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[143]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[144]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[145]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[146]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[147]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[148]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[149]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[150]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[151]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[152]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[153]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[154]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[155]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[156]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[157]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[158]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[159]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[160]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[161]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[162]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[163]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[164]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[165]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[166]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[167]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[168]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[169]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[170]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[171]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[172]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[173]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[174]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[175]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[176]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[177]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[178]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[179]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[180]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[181]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[182]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[183]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[184]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[185]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[186]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[187]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[188]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[189]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[190]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[191]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[192]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[193]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[194]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[195]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[196]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[197]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[198]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[199]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[200]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[201]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[202]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[203]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[204]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[205]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[206]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[207]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[208]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[209]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[210]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[211]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[212]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[213]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[214]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[215]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[216]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[217]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[218]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[219]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[220]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[221]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[222]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[223]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[224]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[225]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[226]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[227]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[228]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[229]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[230]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[231]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[232]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[233]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[234]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[235]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[236]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[237]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[238]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[239]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[240]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[241]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[242]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[243]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[244]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[245]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[246]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[247]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[248]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[249]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[250]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[251]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[252]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[253]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[254]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[255]/opit_0_inv_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata_en[0]/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata_en[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/usr_wdp_rdy_dly/opit_0_inv/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/axi_fifo_full0/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/cnt0_times[0]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/cnt0_times[1]/opit_0_A2Q1/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/cnt0_times[3]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/cnt0_times[5]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/cnt0_times[7]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/cnt0_times[8]/opit_0_AQ_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/cnt1_times[0]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/cnt1_times[1]/opit_0_A2Q1/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/cnt1_times[3]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/cnt1_times[5]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/cnt1_times[7]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/cnt1_times[8]/opit_0_AQ_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/cnt_wr_num[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/cnt_wr_num[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/cnt_wr_num[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/delay_cnt[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/delay_cnt[1]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/delay_cnt[2]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/delay_cnt[3]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/delay_cnt[4]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_addr_start_fall/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_addr_start_valid0/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_addr_start_valid1/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_cnt_num[0]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_cnt_num[2]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_cnt_num[4]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_cnt_num[6]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_cnt_num[8]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_cnt_num[10]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_cnt_num[12]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_cnt_num[14]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_cnt_num[15]/opit_0_AQ/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_done0/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_done1/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr0[10]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr0[11]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr0[12]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr0[13]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr0[14]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr0[15]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr0[16]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr0[17]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr0[18]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr0[19]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr0[20]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr0[21]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr0[22]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr0[23]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr0[24]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr0[25]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr0[26]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr0[27]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr0[28]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr0[29]/opit_0/CLK (10.700, 11.431, 10.200, 10.822) + + + u_axi_ddr_top/rd0_ddr_sart_addr1[10]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr1[11]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr1[12]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr1[13]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr1[14]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr1[15]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr1[16]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr1[17]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr1[18]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr1[19]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr1[20]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr1[21]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr1[22]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr1[23]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr1[24]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr1[25]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr1[26]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr1[27]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr1[28]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr1[29]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr2[10]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr2[11]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr2[12]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr2[13]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr2[14]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr2[15]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr2[16]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr2[17]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr2[18]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr2[19]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr2[20]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr2[21]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr2[22]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr2[23]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr2[24]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr2[25]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr2[26]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr2[27]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr2[28]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_ddr_sart_addr2[29]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_done_cnt[0]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_done_cnt[1]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_done_cnt[2]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd0_time_permit/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_addr_start_fall/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_addr_start_valid0/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_addr_start_valid1/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_cnt_num[0]/opit_0_L5Q_perm/CLK (10.723, 11.454, 10.222, 10.845) + + + u_axi_ddr_top/rd1_cnt_num[2]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_cnt_num[4]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_cnt_num[6]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_cnt_num[8]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_cnt_num[10]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_cnt_num[12]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_cnt_num[14]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_cnt_num[15]/opit_0_AQ/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_done0/opit_0_L5Q_perm/CLK (10.700, 11.431, 10.200, 10.822) + + + u_axi_ddr_top/rd1_ddr_done1/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr0[9]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr0[10]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr0[11]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr0[12]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr0[13]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr0[14]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr0[15]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr0[16]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr0[17]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr0[18]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr0[19]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr0[20]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr0[21]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr0[22]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr0[23]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr0[24]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr1[9]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr1[10]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr1[11]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr1[12]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr1[13]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr1[14]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr1[15]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr1[16]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr1[17]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr1[18]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr1[19]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr1[20]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr1[21]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr1[22]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr1[23]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr1[24]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr2[9]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr2[10]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr2[11]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr2[12]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr2[13]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr2[14]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr2[15]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr2[16]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr2[17]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr2[18]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr2[19]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr2[20]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr2[21]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr2[22]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr2[23]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_ddr_sart_addr2[24]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_done_cnt[0]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_done_cnt[1]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_done_cnt[2]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd1_time_permit/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd3_data_en0/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd3_data_en1/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd3_data_en2/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd3_ddr_data[0]/opit_0_MUX16TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd3_ddr_data[1]/opit_0_MUX16TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd3_ddr_data[2]/opit_0_MUX16TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd3_ddr_data[3]/opit_0_MUX16TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd3_ddr_data[4]/opit_0_MUX16TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd3_ddr_data[5]/opit_0_MUX16TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd3_ddr_data[6]/opit_0_MUX16TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd3_ddr_data[7]/opit_0_MUX16TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd3_ddr_data[8]/opit_0_MUX16TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd3_ddr_data[9]/opit_0_MUX16TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd3_ddr_data[10]/opit_0_MUX16TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd3_ddr_data[11]/opit_0_MUX16TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd3_ddr_data[12]/opit_0_MUX16TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd3_ddr_data[13]/opit_0_MUX16TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd3_ddr_data[14]/opit_0_MUX16TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd3_ddr_data[15]/opit_0_MUX16TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd_all_full/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd_ddr_idle/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd_importance/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd_sta0_reg0/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd_sta0_reg1/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd_sta2_reg0/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd_sta2_reg1/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd_sta_reg[0]/opit_0_L5Q_perm/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/rd_sta_reg[1]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd_sta_reg[2]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd_sta_reg[3]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd_sta_reg[4]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd_sta_reg[6]/opit_0_L5Q_perm/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/rd_sta_reg[7]/opit_0_L5Q_perm/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/rd_wr_fast_empty/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rd_wr_fifo_empty/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/record_addr_valid/opit_0_L5Q_perm/CLK (10.691, 11.422, 10.191, 10.813) + + + u_axi_ddr_top/record_araddr_valid/opit_0_L5Q_perm/CLK (10.700, 11.431, 10.200, 10.822) + + + u_axi_ddr_top/record_data_valid/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rst0/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rx_rd0_addr_valid/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/rx_rd1_addr_valid/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_araddr[5]/opit_0_L5Q_perm/CLK (10.682, 11.412, 10.182, 10.804) + + + u_axi_ddr_top/s_axi_araddr[6]/opit_0_L5Q_perm/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/s_axi_araddr[7]/opit_0_L5Q_perm/CLK (10.682, 11.412, 10.182, 10.804) + + + u_axi_ddr_top/s_axi_araddr[8]/opit_0_MUX4TO1Q/CLK (10.717, 11.448, 10.216, 10.839) + + + u_axi_ddr_top/s_axi_araddr[9]/opit_0_L5Q_perm/CLK (10.717, 11.448, 10.216, 10.839) + + + u_axi_ddr_top/s_axi_araddr[10]/opit_0_L5Q_perm/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/s_axi_araddr[11]/opit_0_L5Q_perm/CLK (10.717, 11.448, 10.216, 10.839) + + + u_axi_ddr_top/s_axi_araddr[12]/opit_0_L5Q_perm/CLK (10.717, 11.448, 10.216, 10.839) + + + u_axi_ddr_top/s_axi_araddr[13]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_araddr[14]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_araddr[15]/opit_0_L5Q_perm/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/s_axi_araddr[16]/opit_0_L5Q_perm/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/s_axi_araddr[17]/opit_0_L5Q_perm/CLK (10.700, 11.431, 10.200, 10.822) + + + u_axi_ddr_top/s_axi_araddr[18]/opit_0_L5Q_perm/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/s_axi_araddr[19]/opit_0_L5Q_perm/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/s_axi_araddr[20]/opit_0_L5Q_perm/CLK (10.700, 11.431, 10.200, 10.822) + + + u_axi_ddr_top/s_axi_araddr[21]/opit_0_L5Q_perm/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/s_axi_araddr[22]/opit_0_L5Q/CLK (10.700, 11.431, 10.200, 10.822) + + + u_axi_ddr_top/s_axi_araddr[23]/opit_0_L5Q_perm/CLK (10.700, 11.431, 10.200, 10.822) + + + u_axi_ddr_top/s_axi_araddr[24]/opit_0_L5Q_perm/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/s_axi_araddr[25]/opit_0_L5Q_perm/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/s_axi_araddr[26]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_araddr[27]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_araddr[28]/opit_0_L5Q_perm/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/s_axi_araddr[29]/opit_0_L5Q_perm/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/s_axi_arid[0]/opit_0/CLK (10.682, 11.412, 10.182, 10.804) + + + u_axi_ddr_top/s_axi_arid[1]/opit_0/CLK (10.682, 11.412, 10.182, 10.804) + + + u_axi_ddr_top/s_axi_arid[2]/opit_0/CLK (10.682, 11.412, 10.182, 10.804) + + + u_axi_ddr_top/s_axi_arid[3]/opit_0_L5Q_perm/CLK (10.682, 11.412, 10.182, 10.804) + + + u_axi_ddr_top/s_axi_arlen[0]/opit_0_L5Q_perm/CLK (10.682, 11.412, 10.182, 10.804) + + + u_axi_ddr_top/s_axi_rdata0[0]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[1]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[2]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[3]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[4]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[5]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[6]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[7]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[8]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[9]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[10]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[11]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[12]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[13]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[14]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[15]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[16]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[17]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[18]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[19]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[20]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[21]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[22]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[23]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[24]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[25]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[26]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[27]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[28]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[29]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[30]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[31]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[32]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[33]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[34]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[35]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[36]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[37]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[38]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[39]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[40]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[41]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[42]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[43]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[44]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[45]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[46]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[47]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[48]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[49]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[50]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[51]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[52]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[53]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[54]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[55]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[56]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/s_axi_rdata0[57]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/s_axi_rdata0[58]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/s_axi_rdata0[59]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/s_axi_rdata0[60]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/s_axi_rdata0[61]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/s_axi_rdata0[62]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/s_axi_rdata0[63]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/s_axi_rdata0[64]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[65]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[66]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[67]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[68]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[69]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[70]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[71]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[72]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[73]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[74]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[75]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[76]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[77]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[78]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[79]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[80]/opit_0_L5Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[81]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[82]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[83]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[84]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[85]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[86]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[87]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[88]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[89]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[90]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[91]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[92]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[93]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[94]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[95]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[96]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[97]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[98]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[99]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[100]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[101]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[102]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[103]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[104]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[105]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[106]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[107]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[108]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[109]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[110]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[111]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[112]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[113]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[114]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[115]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[116]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[117]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[118]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[119]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[120]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/s_axi_rdata0[121]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/s_axi_rdata0[122]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/s_axi_rdata0[123]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/s_axi_rdata0[124]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/s_axi_rdata0[125]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/s_axi_rdata0[126]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/s_axi_rdata0[127]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/s_axi_rdata0[128]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[129]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[130]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[131]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[132]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[133]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[134]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[135]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[136]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[137]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[138]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[139]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[140]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[141]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[142]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[143]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[144]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[145]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[146]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[147]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[148]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[149]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[150]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[151]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[152]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[153]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[154]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[155]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[156]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[157]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[158]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[159]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[160]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[161]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[162]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[163]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[164]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[165]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[166]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[167]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[168]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[169]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[170]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[171]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[172]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[173]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[174]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[175]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[176]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[177]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[178]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[179]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[180]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[181]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[182]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[183]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[184]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/s_axi_rdata0[185]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/s_axi_rdata0[186]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/s_axi_rdata0[187]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/s_axi_rdata0[188]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/s_axi_rdata0[189]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/s_axi_rdata0[190]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/s_axi_rdata0[191]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/s_axi_rdata0[192]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[193]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[194]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[195]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[196]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[197]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[198]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[199]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[200]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[201]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[202]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[203]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[204]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[205]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[206]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[207]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[208]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[209]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[210]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[211]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[212]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[213]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[214]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[215]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[216]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[217]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[218]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[219]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[220]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[221]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[222]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[223]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[224]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[225]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[226]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[227]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[228]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[229]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[230]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[231]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[232]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[233]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[234]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[235]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[236]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[237]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[238]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[239]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[240]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[241]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[242]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[243]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[244]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[245]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[246]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[247]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata0[248]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/s_axi_rdata0[249]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/s_axi_rdata0[250]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/s_axi_rdata0[251]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/s_axi_rdata0[252]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/s_axi_rdata0[253]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/s_axi_rdata0[254]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/s_axi_rdata0[255]/opit_0_L5Q_perm/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/s_axi_rdata1[0]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[1]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[2]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[3]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[4]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[5]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[6]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[7]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[8]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[9]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[10]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[11]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[12]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[13]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[14]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[15]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[16]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[17]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[18]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[19]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[20]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[21]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[22]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[23]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[24]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[25]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[26]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[27]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[28]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[29]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[30]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[31]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[32]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[33]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[34]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[35]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[36]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[37]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[38]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[39]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[40]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[41]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[42]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[43]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[44]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[45]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[46]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[47]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[48]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[49]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[50]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + 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u_axi_ddr_top/s_axi_rdata1[195]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[196]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[197]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[198]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[199]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[200]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[201]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[202]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[203]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[204]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[205]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[206]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[207]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[208]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[209]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[210]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[211]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[212]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[213]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[214]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[215]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[216]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[217]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[218]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[219]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[220]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[221]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[222]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[223]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[224]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[225]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[226]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[227]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[228]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[229]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[230]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[231]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[232]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[233]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[234]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[235]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[236]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[237]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[238]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[239]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[240]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[241]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[242]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[243]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[244]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[245]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[246]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[247]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[248]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/s_axi_rdata1[249]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/s_axi_rdata1[250]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/s_axi_rdata1[251]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[252]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[253]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[254]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/s_axi_rdata1[255]/opit_0/CLK (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/switch_data0[0]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/switch_data0[1]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/switch_data0[2]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/switch_data0[3]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0_A2Q1/CLK (10.694, 11.424, 10.193, 10.815) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (10.691, 11.422, 10.191, 10.813) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (10.691, 11.422, 10.191, 10.813) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (10.703, 11.433, 10.202, 10.824) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[11]/opit_0_inv_A2Q21/CLK (10.703, 11.433, 10.202, 10.824) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm/CLK (10.682, 11.412, 10.182, 10.804) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm/CLK (10.682, 11.412, 10.182, 10.804) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/CLK (10.682, 11.412, 10.182, 10.804) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm/CLK (10.682, 11.412, 10.182, 10.804) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm/CLK (10.694, 11.424, 10.193, 10.815) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm/CLK (10.694, 11.424, 10.193, 10.815) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/CLK (10.694, 11.424, 10.193, 10.815) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/CLK (10.694, 11.424, 10.193, 10.815) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm/CLK (10.694, 11.424, 10.193, 10.815) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[11]/opit_0_L5Q_perm/CLK (10.694, 11.424, 10.193, 10.815) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0/CLK (10.670, 11.400, 10.169, 10.791) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/opit_0/CLK (10.670, 11.400, 10.169, 10.791) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/opit_0/CLK (10.670, 11.400, 10.169, 10.791) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/opit_0/CLK (10.670, 11.400, 10.169, 10.791) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/opit_0/CLK (10.670, 11.400, 10.169, 10.791) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/opit_0/CLK (10.670, 11.400, 10.169, 10.791) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/opit_0/CLK (10.670, 11.400, 10.169, 10.791) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/opit_0/CLK (10.694, 11.424, 10.193, 10.815) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK (10.670, 11.400, 10.169, 10.791) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/CLK (10.699, 11.430, 10.199, 10.821) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/opit_0/CLK (10.699, 11.430, 10.199, 10.821) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[11]/opit_0/CLK (10.679, 11.409, 10.178, 10.800) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/CLK (10.679, 11.409, 10.178, 10.800) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[1]/opit_0/CLK (10.679, 11.409, 10.178, 10.800) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[2]/opit_0/CLK (10.679, 11.409, 10.178, 10.800) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[3]/opit_0/CLK (10.670, 11.400, 10.169, 10.791) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/CLK (10.670, 11.400, 10.169, 10.791) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[5]/opit_0/CLK (10.670, 11.400, 10.169, 10.791) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[6]/opit_0/CLK (10.679, 11.409, 10.178, 10.800) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[7]/opit_0/CLK (10.699, 11.430, 10.199, 10.821) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/CLK (10.670, 11.400, 10.169, 10.791) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[9]/opit_0/CLK (10.699, 11.430, 10.199, 10.821) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[10]/opit_0/CLK (10.699, 11.430, 10.199, 10.821) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[11]/opit_0/CLK (10.699, 11.430, 10.199, 10.821) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.694, 11.424, 10.193, 10.815) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.709, 11.440, 10.209, 10.831) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.721, 11.451, 10.220, 10.842) + + + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[3].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.682, 11.412, 10.182, 10.804) + + + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (10.723, 11.454, 10.222, 10.845) + + + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (10.723, 11.454, 10.222, 10.845) + + + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (10.717, 11.448, 10.216, 10.839) + + + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (10.717, 11.448, 10.216, 10.839) + + + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK (10.697, 11.427, 10.196, 10.818) + + + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (10.717, 11.448, 10.216, 10.839) + + + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (10.717, 11.448, 10.216, 10.839) + + + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (10.712, 11.442, 10.211, 10.833) + + + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (10.706, 11.436, 10.205, 10.828) + + + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (10.721, 11.451, 10.220, 10.842) + + + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.726, 11.457, 10.225, 10.848) + + + u_axi_ddr_top/u_axi_rd_connect/cnt_times[0]/opit_0_inv_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/cnt_times[2]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/cnt_times[4]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/cnt_times[6]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/cnt_times[7]/opit_0_inv_AQ/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/ddr_fifo_full0/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/rd0_fifo_empty0/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/rd0_fifo_full0/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/rd1_fifo_full0/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/rd_ddr_valid/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/rd_sta_reg[0]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/rd_sta_reg[1]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/rd_sta_reg[2]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/rd_sta_reg[3]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/rid_dout0[0]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/rid_dout0[1]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/rid_valid_cnt[0]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/rid_valid_cnt[1]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/rid_valid_cnt[2]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[10]/opit_0_inv_AQ/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[10]/opit_0_inv_AQ/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKA (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[10]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[11]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wr_water_level[1]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wr_water_level[3]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wr_water_level[5]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wr_water_level[7]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wr_water_level[9]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[5]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[6]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[8]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[11]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[10]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[11]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wr_water_level[9]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[5]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[6]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[8]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[11]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm_inv/CLKA[0] (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm_inv/CLKA[0] (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[11]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[1]/opit_0_A2Q1/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[3]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[5]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[7]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[9]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM18K/iGopDrm/CLKA[0] (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[3].U_GTP_DRM18K/iGopDrm/CLKA[0] (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[3].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[4].U_GTP_DRM18K/iGopDrm/CLKA[0] (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[4].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/CLKA[0] (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[6].U_GTP_DRM18K/iGopDrm/CLKA[0] (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[6].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[7].U_GTP_DRM18K/iGopDrm/CLKA[0] (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[7].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/u_axi_wr_connect/axi_addr0[0]/opit_0_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_addr0[1]/opit_0_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_addr0[2]/opit_0_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_addr0[3]/opit_0_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_addr0[4]/opit_0_A2Q1/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_addr0[6]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_addr0[8]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_addr0[10]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_addr0[12]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_addr0[14]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_addr0[16]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_addr0[18]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_addr0[19]/opit_0_AQ/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_addr_valid0/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[0]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[1]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[2]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[3]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[4]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[5]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[6]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[7]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[8]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[9]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[10]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[11]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[12]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[13]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[14]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[15]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[16]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[17]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[18]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[19]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[20]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[21]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[22]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[23]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[24]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[25]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[26]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[27]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[28]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[29]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[30]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[31]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[32]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[33]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[34]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[35]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[36]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[37]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[38]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[39]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[40]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[41]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[42]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[43]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[44]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[45]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[46]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[47]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[48]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[49]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[50]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[51]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[52]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[53]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[54]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[55]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[56]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[57]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[58]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[59]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[60]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[61]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[62]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[63]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/axi_data_valid0/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/cnt_times[0]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/cnt_times[2]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/cnt_times[4]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/cnt_times[6]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/ddr0_valid_fall0/opit_0_L5Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/ddr0_valid_fall2/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/ddr1_valid_fall0/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/ddr1_valid_fall2/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/ddr3_valid_fall0/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/ddr3_valid_fall2/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/delay_cnt0[0]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/delay_cnt0[1]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/delay_cnt0[2]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/delay_cnt1[0]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/delay_cnt1[1]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/delay_cnt1[2]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/delay_cnt3[0]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/delay_cnt3[1]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/delay_cnt3[2]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/fifo0_data_full/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/fifo1_data_full/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/fifo3_data_full/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[11]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[5]/opit_0_A2Q1/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[7]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[9]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[2]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[3]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[5]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[6]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[7]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[9]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[10]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[11]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[11]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[5]/opit_0_A2Q1/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[7]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[9]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[2]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[3]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[5]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[6]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[7]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[9]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[10]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[11]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.726, 11.457, 10.225, 10.848) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[11]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[5]/opit_0_A2Q1/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[7]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[9]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[2]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[3]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[5]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[6]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[7]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[9]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[10]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[11]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/rd_sta0[0]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/rd_sta0[1]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/rd_sta0[2]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/rd_sta0[3]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/rd_sta0[4]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/rd_sta0[6]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/rd_sta0[7]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[0]/opit_0_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[1]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[2]/opit_0_MUX4TO1Q/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[3]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[4]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[6]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[7]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/rx0_addr_valid/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/rx1_addr_valid/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/rx3_addr_valid/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[0]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[2]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[4]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[6]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[8]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[10]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[12]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[14]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[15]/opit_0_AQ/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_done0/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_done1/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr0[13]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr0[14]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr0[15]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr0[16]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr0[17]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr1[13]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr1[14]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr1[15]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr1[16]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr1[17]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr2[13]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr2[14]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr2[15]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr2[16]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr2[17]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr_valid0/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr_valid1/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr_valid2/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[0]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[2]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[4]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[6]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[8]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[10]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[12]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[14]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[15]/opit_0_AQ/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_done0/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_done1/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr0[13]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr0[14]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr0[15]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr0[16]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr0[17]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr1[13]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr1[14]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr1[15]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr1[16]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr1[17]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr2[13]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr2[14]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr2[15]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr2[16]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr2[17]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr_valid0/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr_valid1/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr_valid2/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[0]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[2]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[4]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[6]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[8]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[10]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[12]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[14]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[15]/opit_0_AQ/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_done0/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_done1/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr0[13]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr0[14]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr0[15]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr1[13]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr1[14]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr1[15]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr2[13]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr2[14]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr2[15]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr_valid0/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr_valid1/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr_valid2/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0_A2Q1/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[11]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[11]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[11]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[1]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[2]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[3]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[5]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[6]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[7]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[9]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[10]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[11]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wr_water_level[3]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wr_water_level[5]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wr_water_level[7]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wr_water_level[9]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[0]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[5]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[6]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[8]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm_inv/CLKA (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[11]/opit_0_inv_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[3]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[5]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[7]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[9]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[11]/opit_0_A2Q21/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM18K/iGopDrm/CLKA[0] (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[3].U_GTP_DRM18K/iGopDrm/CLKA[0] (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[3].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[4].U_GTP_DRM18K/iGopDrm/CLKA[0] (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[4].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/CLKA[0] (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[6].U_GTP_DRM18K/iGopDrm/CLKA[0] (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[6].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[7].U_GTP_DRM18K/iGopDrm/CLKA[0] (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[7].U_GTP_DRM18K/iGopDrm/CLKB[0] (10.786, 11.517, 10.279, 10.903) + + + u_axi_ddr_top/wr_sta_idle/opit_0/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/wr_sta_reg[0]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/wr_sta_reg[1]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/wr_sta_reg[2]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + u_axi_ddr_top/wr_sta_reg[3]/opit_0_L5Q_perm/CLK (10.665, 11.394, 10.164, 10.785) + + + + + + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/CLK (6.733, 7.270, 6.213, 6.639) + + ioclk0 (400.00MHZ) (drive 11 loads) + + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT (6.982, 7.618, 6.462, 6.987) + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] (net) + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[1].u_ddc_ca/opit_0/IOCLK (7.041, 7.692, 6.520, 7.059) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[3].u_ddc_ca/opit_0/IOCLK (7.041, 7.692, 6.520, 7.059) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[1].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[2].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[3].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[4].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[5].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[6].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[7].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK (7.041, 7.692, 6.520, 7.059) + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/CLK (6.733, 7.270, 6.213, 6.639) + + ioclk1 (400.00MHZ) (drive 27 loads) + + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT (6.982, 7.618, 6.462, 6.987) + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] (net) + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[1].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[2].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[3].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[4].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[5].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[6].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[7].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK (7.041, 7.692, 6.520, 7.059) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[1].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[2].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[3].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[4].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[5].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[6].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[7].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK (7.041, 7.692, 6.520, 7.059) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[1].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[2].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[3].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[4].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[5].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[6].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[7].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK (7.062, 7.712, 6.537, 7.085) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK (7.041, 7.692, 6.520, 7.059) + + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT1 (5.604, 6.121, 5.084, 5.491) + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk_gate_clk_pll (net) + + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg_gate/gopclkbufg/CLK (6.663, 7.199, 6.143, 6.569) + + ioclk_gate_clk (100.00MHZ) (drive 1 loads) + + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg_gate/gopclkbufg/CLKOUT (6.663, 7.199, 6.143, 6.569) + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk_gate_clk (net) + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_ioclk_gate/opit_0_inv_L5Q_perm/CLK (8.194, 8.784, 7.695, 8.179) + + + + + + + - image_filiter_inst/hybrid_filter_inst/median_finder9_r/min[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_1/u_pll_e3/goppll/CLKIN1 (5.508, 6.020, 4.986, 5.391) + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_1/u_pll_e3/goppll/CLKOUT0_WL (5.631, 6.149, 5.111, 5.518) + + clkout0_wl_1 (net) + + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_2/gopclkgate/CLK (6.733, 7.270, 6.213, 6.639) + + ioclk2 (400.00MHZ) (drive 2 loads) + + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_2/gopclkgate/OUT (6.982, 7.618, 6.462, 6.987) + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [2] (net) + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_ddc_ca/opit_0/IOCLK (7.041, 7.692, 6.520, 7.059) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[2].u_ddc_ca/opit_0/IOCLK (7.041, 7.692, 6.520, 7.059) + + + + + + + + + + + + + + + clk_25m (25.00MHZ) (drive 26 loads) + + u_sys_pll/u_pll_e3/goppll/CLKOUT3 (2.793, 3.214, 2.250, 2.558) + + clk_25m (net) + + clkbufg_8/gopclkbufg/CLK (3.852, 4.292, 3.309, 3.636) + + clkbufg_8/gopclkbufg/CLKOUT (3.852, 4.292, 3.309, 3.636) + + ntclkbufg_8 (net) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/min[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/min[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/min[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_ov5640/coms1_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/min_of_vector_max[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + u_ov5640/coms1_reg_config/clock_20k_cnt[1]/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/min_of_vector_max[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + u_ov5640/coms1_reg_config/clock_20k_cnt[2]/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/min_of_vector_max[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + u_ov5640/coms1_reg_config/clock_20k_cnt[3]/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/min_of_vector_max[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + u_ov5640/coms1_reg_config/clock_20k_cnt[4]/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/min_of_vector_max[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + u_ov5640/coms1_reg_config/clock_20k_cnt[5]/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/min_of_vector_min[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + u_ov5640/coms1_reg_config/clock_20k_cnt[6]/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/min_of_vector_min[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + u_ov5640/coms1_reg_config/clock_20k_cnt[7]/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/min_of_vector_min[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + u_ov5640/coms1_reg_config/clock_20k_cnt[8]/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/min_of_vector_min[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + u_ov5640/coms1_reg_config/clock_20k_cnt[9]/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/min_of_vector_min[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + u_ov5640/coms1_reg_config/clock_20k_cnt[10]/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - image_filiter_inst/hybrid_filter_inst/pixel_ff[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - image_filiter_inst/hybrid_filter_inst/pixel_ff[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - image_filiter_inst/hybrid_filter_inst/pixel_ff[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - image_filiter_inst/hybrid_filter_inst/pixel_ff[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_ov5640/coms2_reg_config/clock_20k_cnt[1]/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - image_filiter_inst/hybrid_filter_inst/pixel_ff[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_ov5640/coms2_reg_config/clock_20k_cnt[2]/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - image_filiter_inst/hybrid_filter_inst/pixel_ff[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_ov5640/coms2_reg_config/clock_20k_cnt[3]/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - image_filiter_inst/hybrid_filter_inst/pixel_ff[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_ov5640/coms2_reg_config/clock_20k_cnt[4]/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - image_filiter_inst/hybrid_filter_inst/pixel_ff[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_ov5640/coms2_reg_config/clock_20k_cnt[5]/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - image_filiter_inst/hybrid_filter_inst/pixel_ff[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_ov5640/coms2_reg_config/clock_20k_cnt[6]/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - image_filiter_inst/hybrid_filter_inst/pixel_ff[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_ov5640/coms2_reg_config/clock_20k_cnt[7]/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - image_filiter_inst/hybrid_filter_inst/pixel_ff[10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_ov5640/coms2_reg_config/clock_20k_cnt[8]/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - image_filiter_inst/hybrid_filter_inst/pixel_ff[11]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_ov5640/coms2_reg_config/clock_20k_cnt[9]/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) - image_filiter_inst/hybrid_filter_inst/pixel_ff[12]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_ov5640/coms2_reg_config/clock_20k_cnt[10]/opit_0_inv/CLK (5.383, 5.877, 4.861, 5.246) + + + + + + + + clk_10m (10.00MHZ) (drive 235 loads) + + u_sys_pll/u_pll_e3/goppll/CLKOUT4 (2.788, 3.210, 2.246, 2.553) + + clk_10m (net) + + clkbufg_4/gopclkbufg/CLK (3.847, 4.288, 3.305, 3.631) + + clkbufg_4/gopclkbufg/CLKOUT (3.847, 4.288, 3.305, 3.631) + + ntclkbufg_4 (net) - image_filiter_inst/hybrid_filter_inst/pixel_ff[13]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/busy/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[14]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/byte_over/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[15]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/data_out[0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[16]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/data_out[1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[17]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/data_out[2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[18]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/data_out[3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[19]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/data_out[4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[20]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/data_out[5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[21]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/data_out[6]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[22]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/data_out[7]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[23]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/fre_cnt[0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[24]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/fre_cnt[1]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[25]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/fre_cnt[2]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[26]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/fre_cnt[3]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[27]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/fre_cnt[4]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[28]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/pluse_1d/opit_0_inv/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[29]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/pluse_2d/opit_0_inv/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[30]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/pluse_3d/opit_0_inv/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[31]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/receiv_data[0]/opit_0_inv/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[32]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/receiv_data[1]/opit_0_inv/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[33]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/receiv_data[2]/opit_0_inv/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[34]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/receiv_data[3]/opit_0_inv/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[35]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/receiv_data[4]/opit_0_inv/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[36]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/receiv_data[5]/opit_0_inv/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[37]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/receiv_data[6]/opit_0_inv/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[38]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/receiv_data[7]/opit_0_inv/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[39]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/scl_out/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[40]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/sda_out/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[41]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/send_data[0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[42]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/send_data[1]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[43]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/send_data[2]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[44]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/send_data[3]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[45]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/send_data[4]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[46]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/send_data[5]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/pixel_ff[47]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/send_data[6]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/raw_res_b[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/send_data[7]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/raw_res_b[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/start_en/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/raw_res_b[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/state_reg[0]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/raw_res_b[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/state_reg[1]/opit_0_inv_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/raw_res_b[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/state_reg[2]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/raw_res_g[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/state_reg[3]/opit_0_inv_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/raw_res_g[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/state_reg[4]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/raw_res_g[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/state_reg[5]/opit_0_inv_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/raw_res_g[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/state_reg[6]/opit_0_inv_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/raw_res_g[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/trans_bit[0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/raw_res_g[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/trans_bit[1]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/raw_res_r[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/trans_bit[2]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/raw_res_r[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/trans_byte[0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/raw_res_r[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/trans_byte[1]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/raw_res_r[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/trans_byte[2]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/raw_res_r[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/trans_byte[3]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/res_b[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/trans_byte_max[0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/res_b[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/trans_byte_max[2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/res_b[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/trans_en/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/res_b[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/twr_cnt[0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/res_b[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/twr_cnt[1]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/res_g[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/twr_cnt[2]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/res_g[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/twr_cnt[3]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/res_g[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/twr_en/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/res_g[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/w_r_1d/opit_0_inv/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/res_g[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_rx/w_r_2d/opit_0_inv/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/res_g[5]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/busy/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/res_r[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/byte_over/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/res_r[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/data_out[0]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/res_r[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/data_out[1]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/res_r[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/data_out[2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/res_r[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/data_out[3]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/valid_d[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/data_out[4]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/valid_d[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/data_out[5]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/valid_d[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/data_out[6]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/hybrid_filter_inst/valid_d[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/data_out[7]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/pluse_1d/opit_0_inv/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/pluse_2d/opit_0_inv/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/pluse_3d/opit_0_inv/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/receiv_data[0]/opit_0_inv/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/receiv_data[1]/opit_0_inv/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[11]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/receiv_data[2]/opit_0_inv/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/receiv_data[3]/opit_0_inv/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/receiv_data[4]/opit_0_inv/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/receiv_data[5]/opit_0_inv/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/receiv_data[6]/opit_0_inv/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/receiv_data[7]/opit_0_inv/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/scl_out/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/sda_out/opit_0_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[11]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/send_data[0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/send_data[1]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/send_data[2]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/send_data[3]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/send_data[4]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/send_data[5]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/send_data[6]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/send_data[7]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/start_en/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/state_reg[0]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[11]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/state_reg[1]/opit_0_inv_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/state_reg[2]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/state_reg[3]/opit_0_inv_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/state_reg[4]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/state_reg[5]/opit_0_inv_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/state_reg[6]/opit_0_inv_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/trans_bit[0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/trans_bit[1]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[11]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/trans_bit[2]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/trans_byte[0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/trans_byte[1]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/trans_byte[2]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/trans_byte[3]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/hor_cnt[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/trans_byte_max[0]/opit_0_L5Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/hor_cnt[2]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/trans_byte_max[2]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/hor_cnt[4]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/trans_en/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/hor_cnt[6]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/twr_cnt[0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/hor_cnt[7]/opit_0_A2Q0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/twr_cnt[1]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/hor_cnt[8]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/twr_cnt[2]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/hor_cnt[9]/opit_0_A2Q0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/twr_cnt[3]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/hor_cnt[10]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/twr_en/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/m_pixel_valid/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/w_r_1d/opit_0_inv/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/rst_s1/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/iic_dri_tx/w_r_2d/opit_0_inv/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKA[0] (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKB[0] (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[2]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/addr[0]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[4]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/addr[1]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[6]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/addr[2]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[8]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/addr[3]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[10]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/addr[4]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/tail_ver_cnt[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/addr[5]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/tail_ver_cnt[2]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/addr[6]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/tail_ver_cnt[4]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/addr[7]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/tail_ver_cnt[5]/opit_0_AQ_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/addr[8]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/ver_cnt[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/addr[9]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/ver_cnt[2]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/addr[12]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/ver_cnt[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/addr[13]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/ver_cnt[4]/opit_0_A2Q1/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/busy_1d/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/ver_cnt[5]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/cmd_index[0]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/ver_cnt[6]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/cmd_index[1]/opit_0_inv_A2Q1/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/ver_cnt[7]/opit_0_A2Q0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/cmd_index[3]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/multiline_buffer_inst/ver_cnt[8]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/cmd_index[5]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][0][0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/cmd_index[7]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][0][1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/cmd_index[8]/opit_0_inv_AQ/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][0][2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/data_in[0]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][0][3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/data_in[1]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][0][4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/data_in[2]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][0][5]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/data_in[3]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][0][6]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/data_in[4]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][0][7]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/data_in[5]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][0][8]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/data_in[6]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][0][9]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/data_in[7]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][0][10]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/dri_cnt[0]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][0][11]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/dri_cnt[1]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][0][12]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/dri_cnt[2]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][0][13]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/dri_cnt[3]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][0][14]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][0][15]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/dri_cnt[5]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][1][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/dri_cnt[6]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][1][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/dri_cnt[7]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][1][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/dri_cnt[8]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][1][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/freq_ensure/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][1][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/freq_rec_1d[16]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][1][5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/freq_rec_1d[17]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][1][6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/freq_rec_2d[16]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][1][7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/freq_rec_2d[17]/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][1][8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/freq_rec[16]/opit_0_inv/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][1][9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/freq_rec[17]/opit_0_inv/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][1][10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/iic_trig/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][1][11]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/init_over/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][1][12]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/state_reg[0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][1][13]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/state_reg[1]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][1][14]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/state_reg[2]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][1][15]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/state_reg[3]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][2][0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/state_reg[4]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][2][1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7200_ctl/w_r/opit_0_inv_MUX4TO1Q/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][2][2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/N325_1_concat_2/iGopDrm/CLKA (5.378, 5.873, 4.857, 5.241) - image_filiter_inst/vector_to_matrix_inst/mat[0][2][3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/N325_1_concat_2/iGopDrm/CLKB (5.378, 5.873, 4.857, 5.241) - image_filiter_inst/vector_to_matrix_inst/mat[0][2][4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/addr[0]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][2][5]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/addr[1]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][2][6]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/addr[2]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][2][7]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/addr[3]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][2][8]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/addr[4]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][2][9]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/addr[5]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][2][10]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/addr[6]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][2][11]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/addr[7]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][2][12]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/addr[8]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][2][13]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/addr[9]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][2][14]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/addr[10]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[0][2][15]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/addr[11]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][0][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/busy_1d/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][0][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/cmd_index[0]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][0][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/cmd_index[1]/opit_0_inv_A2Q1/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][0][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/cmd_index[3]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][0][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/cmd_index[5]/opit_0_inv_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][0][5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/data_in[0]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][0][6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/data_in[1]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][0][7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/data_in[2]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][0][8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/data_in[3]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][0][9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/data_in[4]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][0][10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/data_in[5]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][0][11]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/data_in[6]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][0][12]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/data_in[7]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][0][13]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/delay_cnt[0]/opit_0_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][0][14]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/delay_cnt[2]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][0][15]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/delay_cnt[4]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][1][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/delay_cnt[6]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][1][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/delay_cnt[8]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][1][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/delay_cnt[10]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][1][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/delay_cnt[12]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][1][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/delay_cnt[14]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][1][5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/delay_cnt[16]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][1][6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/delay_cnt[18]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][1][7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/delay_cnt[20]/opit_0_A2Q21/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][1][8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/delay_cnt[21]/opit_0_AQ/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][1][9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/dri_cnt[0]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][1][10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/dri_cnt[1]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][1][11]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/dri_cnt[2]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][1][12]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/dri_cnt[3]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][1][13]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][1][14]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/iic_trig/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][1][15]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/init_over/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][2][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/state_reg[1]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][2][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/state_reg[2]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][2][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/state_reg[3]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][2][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/state_reg[4]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][2][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/state_reg[5]/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][2][5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/ms7210_ctl/w_r/opit_0_inv_L5Q_perm/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][2][6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/rstn/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][2][7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/rstn_temp1/opit_0_inv/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][2][8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + ms72xx_ctl/rstn_temp2/opit_0/CLK (5.499, 5.996, 4.972, 5.359) - image_filiter_inst/vector_to_matrix_inst/mat[1][2][9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + rstn_1ms[0]/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst/vector_to_matrix_inst/mat[1][2][10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + rstn_1ms[2]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst/vector_to_matrix_inst/mat[1][2][11]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + rstn_1ms[4]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst/vector_to_matrix_inst/mat[1][2][12]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + rstn_1ms[6]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst/vector_to_matrix_inst/mat[1][2][13]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + rstn_1ms[8]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst/vector_to_matrix_inst/mat[1][2][14]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + rstn_1ms[10]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst/vector_to_matrix_inst/mat[1][2][15]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + rstn_1ms[12]/opit_0_inv_A2Q21/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst/vector_to_matrix_inst/mat[2][0][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + rstn_1ms[13]/opit_0_inv_AQ/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst/vector_to_matrix_inst/mat[2][0][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + rstn_out0/opit_0_inv_L5Q_perm/CLK (5.378, 5.873, 4.857, 5.241) - image_filiter_inst/vector_to_matrix_inst/mat[2][0][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + rstn_out1/opit_0_inv/CLK (5.378, 5.873, 4.857, 5.241) + + + + + + + + + + + + + + + + + cmos1_pclk (84.03MHZ) (drive 118 loads) (min_rise, max_rise, min_fall, max_fall) + + cmos1_pclk (0.000, 0.000, 0.000, 0.000) + + cmos1_pclk_ibuf/opit_0/I (0.076, 0.076, 0.076, 0.076) + + cmos1_pclk_ibuf/opit_0/O (1.123, 1.330, 1.218, 1.443) + + cmos1_pclk_ibuf/ntD (net) + + cmos1_pclk_ibuf/opit_1/IN (1.123, 1.330, 1.218, 1.443) + + cmos1_pclk_ibuf/opit_1/INCK (1.171, 1.406, 1.266, 1.518) + + _N64 (net) + + clkbufg_6/gopclkbufg/CLK (3.657, 3.936, 3.758, 4.054) + + clkbufg_6/gopclkbufg/CLKOUT (3.657, 3.936, 3.758, 4.054) + + ntclkbufg_6 (net) + + u_ov5640/cmos1_8_16bit/de_cnt/opit_0_L5Q_perm/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/de_in0/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/de_in1/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/image_data0[0]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/image_data0[1]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/image_data0[2]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/image_data0[3]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/image_data0[4]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/image_data0[5]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/image_data0[6]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/image_data0[7]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/image_data0[8]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/image_data0[9]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/image_data0[10]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/image_data0[11]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/image_data0[12]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/image_data0[13]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/image_data0[14]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/image_data0[15]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/image_data_valid0/opit_0_L5Q_perm/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/image_in_en/opit_0_L5Q_perm/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/pdata_i0[0]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/pdata_i0[1]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/pdata_i0[2]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/pdata_i0[3]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/pdata_i0[4]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/pdata_i0[5]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/pdata_i0[6]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/pdata_i0[7]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/pdata_i1[0]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/pdata_i1[1]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/pdata_i1[2]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/pdata_i1[3]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/pdata_i1[4]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/pdata_i1[5]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/pdata_i1[6]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/pdata_i1[7]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/pdata_i2[0]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/pdata_i2[1]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/pdata_i2[2]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/pdata_i2[3]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/pdata_i2[4]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/pdata_i2[5]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/pdata_i2[6]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/pdata_i2[7]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/vs_in0/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_8_16bit/vs_in1/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_d_d0[0]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_d_d0[1]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_d_d0[2]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_d_d0[3]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_d_d0[4]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_d_d0[5]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_d_d0[6]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_d_d0[7]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_d_d1[0]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_d_d1[1]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_d_d1[2]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_d_d1[3]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_d_d1[4]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_d_d1[5]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_d_d1[6]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_d_d1[7]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_href_d0/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_href_d1/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_vsync_d0/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/cmos1_vsync_d1/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/cnt0_h[0]/opit_0_L5Q_perm/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/cnt0_w[0]/opit_0_L5Q_perm/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/cnt0_w[2]/opit_0_A2Q21/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/cnt0_w[4]/opit_0_A2Q21/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/cnt0_w[6]/opit_0_A2Q21/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/cnt0_w[7]/opit_0_A2Q0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/cnt0_w[8]/opit_0_L5Q_perm/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/cnt0_w[9]/opit_0_A2Q0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/cnt0_w[10]/opit_0_L5Q_perm/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/image1_en/opit_0_L5Q_perm/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[10]/opit_0_inv_AQ/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[10]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[0]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[5]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[6]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[8]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/CLK (5.188, 5.521, 5.310, 5.664) + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.188, 5.521, 5.310, 5.664) + + + + + + + + + + + + + + cmos2_pclk (84.03MHZ) (drive 118 loads) (min_rise, max_rise, min_fall, max_fall) + + cmos2_pclk (0.000, 0.000, 0.000, 0.000) + + cmos2_pclk_ibuf/opit_0/I (0.071, 0.071, 0.071, 0.071) + + cmos2_pclk_ibuf/opit_0/O (1.118, 1.325, 1.213, 1.438) + + cmos2_pclk_ibuf/ntD (net) + + cmos2_pclk_ibuf/opit_1/IN (1.118, 1.325, 1.213, 1.438) + + cmos2_pclk_ibuf/opit_1/OUT (1.200, 1.451, 1.295, 1.565) + + nt_cmos2_pclk (net) + + clkbufg_7/gopclkbufg/CLK (4.017, 4.615, 4.211, 4.775) + + clkbufg_7/gopclkbufg/CLKOUT (4.017, 4.615, 4.211, 4.775) + + ntclkbufg_7 (net) + + u_ov5640/cmos2_8_16bit/de_cnt/opit_0_L5Q_perm/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_8_16bit/de_in0/opit_0/CLK (5.580, 6.233, 5.795, 6.418) + + + u_ov5640/cmos2_8_16bit/de_in1/opit_0/CLK (5.595, 6.248, 5.810, 6.433) + + + u_ov5640/cmos2_8_16bit/image_data0[0]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_8_16bit/image_data0[1]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_8_16bit/image_data0[2]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_8_16bit/image_data0[3]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_8_16bit/image_data0[4]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_8_16bit/image_data0[5]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_8_16bit/image_data0[6]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_8_16bit/image_data0[7]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_8_16bit/image_data0[8]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_8_16bit/image_data0[9]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_8_16bit/image_data0[10]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_8_16bit/image_data0[11]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_8_16bit/image_data0[12]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_8_16bit/image_data0[13]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_8_16bit/image_data0[14]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_8_16bit/image_data0[15]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_8_16bit/image_data_valid0/opit_0_L5Q_perm/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_8_16bit/image_in_en/opit_0_L5Q_perm/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_8_16bit/pdata_i0[0]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_8_16bit/pdata_i0[1]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_8_16bit/pdata_i0[2]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_8_16bit/pdata_i0[3]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_8_16bit/pdata_i0[4]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_8_16bit/pdata_i0[5]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_8_16bit/pdata_i0[6]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_8_16bit/pdata_i0[7]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_8_16bit/pdata_i1[0]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_8_16bit/pdata_i1[1]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_8_16bit/pdata_i1[2]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_8_16bit/pdata_i1[3]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_8_16bit/pdata_i1[4]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_8_16bit/pdata_i1[5]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_8_16bit/pdata_i1[6]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_8_16bit/pdata_i1[7]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_8_16bit/pdata_i2[0]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_8_16bit/pdata_i2[1]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_8_16bit/pdata_i2[2]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_8_16bit/pdata_i2[3]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_8_16bit/pdata_i2[4]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_8_16bit/pdata_i2[5]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_8_16bit/pdata_i2[6]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_8_16bit/pdata_i2[7]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_8_16bit/vs_in0/opit_0/CLK (5.595, 6.248, 5.810, 6.433) + + + u_ov5640/cmos2_8_16bit/vs_in1/opit_0/CLK (5.595, 6.248, 5.810, 6.433) + + + u_ov5640/cmos2_d_d0[0]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_d_d0[1]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_d_d0[2]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_d_d0[3]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_d_d0[4]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_d_d0[5]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_d_d0[6]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_d_d0[7]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_d_d1[0]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_d_d1[1]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_d_d1[2]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_d_d1[3]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_d_d1[4]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_d_d1[5]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_d_d1[6]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_d_d1[7]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/cmos2_href_d0/opit_0/CLK (5.595, 6.248, 5.810, 6.433) + + + u_ov5640/cmos2_href_d1/opit_0/CLK (5.580, 6.233, 5.795, 6.418) + + + u_ov5640/cmos2_vsync_d0/opit_0/CLK (5.595, 6.248, 5.810, 6.433) + + + u_ov5640/cmos2_vsync_d1/opit_0/CLK (5.595, 6.248, 5.810, 6.433) + + + u_ov5640/u_mix_image/cnt1_h[0]/opit_0_L5Q_perm/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/cnt1_w[0]/opit_0_L5Q/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/cnt1_w[2]/opit_0_A2Q21/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/cnt1_w[4]/opit_0_A2Q21/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/cnt1_w[6]/opit_0_A2Q21/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/cnt1_w[7]/opit_0_A2Q0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/cnt1_w[8]/opit_0_L5Q_perm/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/cnt1_w[9]/opit_0_A2Q0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/cnt1_w[10]/opit_0_L5Q_perm/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/image2_en/opit_0_L5Q_perm/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[10]/opit_0_inv_AQ_perm/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[10]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[0]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[5]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[6]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[8]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/CLK (5.548, 6.200, 5.763, 6.385) + + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.548, 6.200, 5.763, 6.385) + + + + + + + + + + + + + + hdmi_in_clk (150.02MHZ) (drive 167 loads) (min_rise, max_rise, min_fall, max_fall) + + hdmi_in_clk (0.000, 0.000, 0.000, 0.000) + + hdmi_in_clk_ibuf/opit_0/I (0.078, 0.078, 0.078, 0.078) + + hdmi_in_clk_ibuf/opit_0/O (1.886, 2.244, 1.342, 1.591) + + hdmi_in_clk_ibuf/ntD (net) + + hdmi_in_clk_ibuf/opit_1/IN (1.886, 2.244, 1.342, 1.591) + + hdmi_in_clk_ibuf/opit_1/INCK (1.934, 2.320, 1.390, 1.666) + + _N37 (net) + + clkbufg_5/gopclkbufg/CLK (4.420, 4.850, 3.882, 4.202) + + clkbufg_5/gopclkbufg/CLKOUT (4.420, 4.850, 3.882, 4.202) + + ntclkbufg_5 (net) + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (5.951, 6.435, 5.434, 5.812) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (5.951, 6.435, 5.434, 5.812) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (5.951, 6.435, 5.434, 5.812) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (5.951, 6.435, 5.434, 5.812) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (5.951, 6.435, 5.434, 5.812) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_A2Q21/CLK (5.951, 6.435, 5.434, 5.812) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[0]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[5]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[6]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[8]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.951, 6.435, 5.434, 5.812) + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[0]/opit_0_L5Q/CLK (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[1]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[2]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[3]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/image_fram_cnt1[0]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/image_fram_cnt1[1]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/image_fram_cnt1[2]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/image_fram_cnt1[3]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/image_fram_cnt1[4]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_in0[0]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_in0[1]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_in0[2]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_in0[3]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_in0[4]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_in1[0]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_in1[1]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_in1[2]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_in1[3]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_in1[4]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_in2[0]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_in2[1]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_in2[2]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_in2[3]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_in2[4]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_in3[0]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_in3[1]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_in3[2]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_in3[3]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_in3[4]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/wr0_async_to_wr1_sync/data_vary0/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/wr_addr_valid0/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/wr_ddr_addr0[19]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/wr_ddr_addr0[20]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/wr_ddr_addr0[21]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/wr_ddr_addr0[22]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/wr_ddr_addr0[23]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/wr_ddr_done0/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/wr_ddr_done1/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/wr_ddr_done2/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[0]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[1]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[2]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/wr_vs0/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/wr_vs1/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/wr_vs2/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_ddr_addr_ctr/u_wr1_addr_ctr/wr_vs_flag/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdm_in_rst/rst/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdm_in_rst/rst0/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdm_in_rst/rst1/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/b_in0[3]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/b_in0[4]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/b_in0[5]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/b_in0[6]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/b_in0[7]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/b_in1[3]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/b_in1[4]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/b_in1[5]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/b_in1[6]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/b_in1[7]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/b_in2[3]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/b_in2[4]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/b_in2[5]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/b_in2[6]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/b_in2[7]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/b_in3[3]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/b_in3[4]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/b_in3[5]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/b_in3[6]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/b_in3[7]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/de_cnt[0]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/de_cnt[1]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/de_in0/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/de_in1/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/de_in2/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/g_in0[2]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/g_in0[3]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/g_in0[4]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/g_in0[5]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/g_in0[6]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/g_in0[7]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/g_in1[2]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/g_in1[3]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/g_in1[4]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/g_in1[5]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/g_in1[6]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/g_in1[7]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/g_in2[2]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/g_in2[3]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/g_in2[4]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/g_in2[5]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/g_in2[6]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/g_in2[7]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/g_in3[2]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/g_in3[3]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/g_in3[4]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/g_in3[5]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/g_in3[6]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/g_in3[7]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/hdmi_in_en/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/hs_cnt[0]/opit_0_L5Q_perm/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/hs_cnt[1]/opit_0_L5Q/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/hs_in0/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/hs_in1/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/hs_in2/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/r_in0[3]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/r_in0[4]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/r_in0[5]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/r_in0[6]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/r_in0[7]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/r_in1[3]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/r_in1[4]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/r_in1[5]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/r_in1[6]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/r_in1[7]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/r_in2[3]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/r_in2[4]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/r_in2[5]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/r_in2[6]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/r_in2[7]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/r_in3[3]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/r_in3[4]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/r_in3[5]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/r_in3[6]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/r_in3[7]/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/vs_in0/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/vs_in1/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + u_hdmi_in_top/vs_in2/opit_0/CLK (5.951, 6.435, 5.434, 5.812) + + + + + + + + + + + + + + eth_rxc (125.00MHZ) (drive 1862 loads) (min_rise, max_rise, min_fall, max_fall) + + eth_rxc (0.000, 0.000, 0.000, 0.000) + + eth_rxc_ibuf/opit_0/I (0.057, 0.057, 0.057, 0.057) + + eth_rxc_ibuf/opit_0/O (1.104, 1.311, 1.199, 1.424) + + eth_rxc_ibuf/ntD (net) + + eth_rxc_ibuf/opit_1/IN (1.104, 1.311, 1.199, 1.424) + + eth_rxc_ibuf/opit_1/INCK (1.152, 1.387, 1.247, 1.499) + + _N66 (net) + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKIN (1.788, 2.034, 1.880, 2.144) + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT (4.362, 5.846, 4.454, 5.973) + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf (net) + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLK (6.915, 8.445, 7.006, 8.571) + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT (6.915, 8.445, 7.006, 8.571) + + gmii_clk (net) + + param_manager_inst/clk_ms/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/filiter1_mode_flags_ff0/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/filiter1_mode_flags_ff1/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/filiter1_mode_load/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/filiter2_mode_flags_ff0/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/filiter2_mode_flags_ff1/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/filiter2_mode_load/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/index[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/index[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/index[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/index[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/key_debounce_key_left/change/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/key_debounce_key_left/clk_ms_ff0/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/key_debounce_key_left/clk_ms_ff1/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/key_debounce_key_left/cnt[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/key_debounce_key_left/cnt[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/key_debounce_key_left/cnt[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/key_debounce_key_left/cnt[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/key_debounce_key_left/cnt[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/key_debounce_key_left/key_ff0/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/key_debounce_key_left/key_ff1/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/key_debounce_key_left/pluse_ms/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/key_debounce_key_left/pressed/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/key_debounce_key_restore/cnt[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/key_debounce_key_restore/cnt[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/key_debounce_key_restore/cnt[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/key_debounce_key_restore/cnt[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/key_debounce_key_restore/cnt[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/key_debounce_key_restore/key_ff0/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/key_debounce_key_restore/key_ff1/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/key_debounce_key_restore/pressed/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/key_debounce_key_right/change/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/key_debounce_key_right/cnt[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/key_debounce_key_right/cnt[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/key_debounce_key_right/cnt[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/key_debounce_key_right/cnt[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/key_debounce_key_right/cnt[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/key_debounce_key_right/key_ff0/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/key_debounce_key_right/key_ff1/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/key_debounce_key_right/pressed/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/modify_H_flags_ff0/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/modify_H_flags_ff1/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/modify_H_flags_ff2/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/modify_H_flags_ff3/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/modify_H_load/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/modify_S_flags_ff0/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/modify_S_flags_ff1/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/modify_S_flags_ff2/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/modify_S_flags_ff3/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/modify_S_load/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/modify_V_flags_ff0/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/modify_V_flags_ff1/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/modify_V_flags_ff2/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/modify_V_flags_ff3/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/modify_V_load/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/ms_cnt[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/ms_cnt[2]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/ms_cnt[4]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/ms_cnt[6]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/ms_cnt[8]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/ms_cnt[10]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/ms_cnt[12]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/ms_cnt[14]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/ms_cnt[16]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/offsetX_flags_ff0/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/offsetX_flags_ff1/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/offsetX_flags_ff2/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/offsetX_flags_ff3/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/offsetX_load/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/offsetY_flags_ff0/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/offsetY_flags_ff1/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/offsetY_flags_ff2/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/offsetY_flags_ff3/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/offsetY_load/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/osd_char_height_flags_ff0/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/osd_char_height_flags_ff1/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/osd_char_height_flags_ff2/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/osd_char_height_flags_ff3/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/osd_char_height_load/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/osd_char_width_flags_ff0/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/osd_char_width_flags_ff1/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/osd_char_width_flags_ff2/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/osd_char_width_flags_ff3/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/osd_char_width_load/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/osd_startX_flags_ff0/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/osd_startX_flags_ff1/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/osd_startX_flags_ff2/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/osd_startX_flags_ff3/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/osd_startX_load/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/osd_startY_flags_ff0/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/osd_startY_flags_ff1/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/osd_startY_flags_ff2/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/osd_startY_flags_ff3/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/osd_startY_load/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_filiter1_mode/cnt[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_filiter1_mode/cnt[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_filiter1_mode/cnt[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_filiter1_mode/cnt[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_filiter1_mode/cnt[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_filiter1_mode/cnt[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_filiter1_mode/cnt[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_filiter1_mode/cnt[7]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_filiter1_mode/cnt[8]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_filiter1_mode/cnt[9]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_filiter1_mode/cnt[10]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_filiter1_mode/cnt[11]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_filiter1_mode/key_debounce_inst1/change/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_filiter1_mode/key_debounce_inst1/cnt[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_filiter1_mode/key_debounce_inst1/cnt[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_filiter1_mode/key_debounce_inst1/cnt[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_filiter1_mode/key_debounce_inst1/cnt[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_filiter1_mode/key_debounce_inst1/cnt[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_filiter1_mode/key_debounce_inst1/key_ff0/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_filiter1_mode/key_debounce_inst1/key_ff1/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_filiter1_mode/key_debounce_inst1/pressed/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_filiter1_mode/key_debounce_inst2/change/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_filiter1_mode/key_debounce_inst2/cnt[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_filiter1_mode/key_debounce_inst2/cnt[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_filiter1_mode/key_debounce_inst2/cnt[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_filiter1_mode/key_debounce_inst2/cnt[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_filiter1_mode/key_debounce_inst2/cnt[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_filiter1_mode/key_debounce_inst2/key_ff0/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_filiter1_mode/key_debounce_inst2/key_ff1/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_filiter1_mode/key_debounce_inst2/pressed/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_filiter1_mode/pluse/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_filiter1_mode/value[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_filiter1_mode/value[1]/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_filiter1_mode/value[2]/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_filiter2_mode/value[0]/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_filiter2_mode/value[1]/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_filiter2_mode/value[2]/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_modify_H/cnt[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_modify_H/cnt[1]/opit_0_A2Q0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_modify_H/cnt[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_modify_H/cnt[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_modify_H/cnt[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_modify_H/cnt[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_modify_H/cnt[6]/opit_0_A2Q1/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_modify_H/cnt[8]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_modify_H/cnt[10]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_modify_H/cnt[11]/opit_0_AQ_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_modify_H/pluse/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_modify_H/value[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_modify_H/value[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_modify_H/value[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_modify_H/value[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_modify_H/value[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_modify_H/value[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_modify_H/value[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_modify_H/value[7]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_modify_H/value[8]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_modify_S/value[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_modify_S/value[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_modify_S/value[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_modify_S/value[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_modify_S/value[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_modify_S/value[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_modify_S/value[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_modify_S/value[7]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_modify_S/value[8]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_modify_V/value[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_modify_V/value[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_modify_V/value[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_modify_V/value[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_modify_V/value[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_modify_V/value[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_modify_V/value[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_modify_V/value[7]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_modify_V/value[8]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_offsetX/cnt[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_offsetX/cnt[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_offsetX/cnt[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_offsetX/cnt[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_offsetX/cnt[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_offsetX/cnt[6]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_offsetX/cnt[8]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_offsetX/cnt[10]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_offsetX/cnt[11]/opit_0_AQ_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_offsetX/pluse/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_offsetX/value[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_offsetX/value[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_offsetX/value[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_offsetX/value[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_offsetX/value[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_offsetX/value[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_offsetX/value[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_offsetX/value[7]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_offsetX/value[8]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_offsetX/value[9]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_offsetX/value[10]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_offsetX/value[11]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_offsetY/value[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_offsetY/value[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_offsetY/value[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_offsetY/value[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_offsetY/value[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_offsetY/value[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_offsetY/value[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_offsetY/value[7]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_offsetY/value[8]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_offsetY/value[9]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_offsetY/value[10]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_offsetY/value[11]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_char_height/cnt[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_char_height/cnt[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_char_height/cnt[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_char_height/cnt[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_char_height/cnt[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_char_height/cnt[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_char_height/cnt[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_char_height/cnt[8]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_char_height/cnt[10]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_char_height/cnt[11]/opit_0_AQ_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_char_height/pluse/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_char_height/value[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_char_height/value[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_char_height/value[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_char_height/value[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_char_height/value[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_char_height/value[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_char_height/value[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_char_height/value[7]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_char_height/value[8]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_char_height/value[9]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_char_height/value[10]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_char_width/value[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_char_width/value[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_char_width/value[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_char_width/value[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_char_width/value[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_char_width/value[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_char_width/value[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_char_width/value[7]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_char_width/value[8]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_char_width/value[9]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_char_width/value[10]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_startX/cnt[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_startX/cnt[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_startX/cnt[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_startX/cnt[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_startX/cnt[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_startX/cnt[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_startX/cnt[6]/opit_0_A2Q1/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_startX/cnt[8]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_startX/cnt[10]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_startX/cnt[11]/opit_0_AQ_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_startX/pluse/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_startX/value[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_startX/value[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_startX/value[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_startX/value[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_startX/value[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_startX/value[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_startX/value[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_startX/value[7]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_startX/value[8]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_startX/value[9]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_startX/value[10]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_startY/value[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_startY/value[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_startY/value[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_startY/value[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_startY/value[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_startY/value[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_startY/value[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_startY/value[7]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_startY/value[8]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_startY/value[9]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_osd_startY/value[10]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_rotate/cnt[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_rotate/cnt[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_rotate/cnt[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_rotate/cnt[3]/opit_0_A2Q0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_rotate/cnt[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_rotate/cnt[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_rotate/cnt[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_rotate/cnt[8]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_rotate/cnt[10]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_rotate/cnt[11]/opit_0_AQ_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_rotate/pluse/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_rotate/value[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_rotate/value[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_rotate/value[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_rotate/value[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_rotate/value[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_rotate/value[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_rotate/value[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_rotate/value[7]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_rotate_A/value[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_rotate_A/value[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_rotate_A/value[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_rotate_A/value[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_rotate_A/value[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_rotate_A/value[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_rotate_A/value[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_rotate_A/value[7]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_rotate_A/value[8]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_rotate_A/value[9]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_zoom/value[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_zoom/value[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_zoom/value[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_zoom/value[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_zoom/value[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_zoom/value[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_zoom/value[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_zoom/value[7]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_zoom/value[8]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/param_zoom/value[9]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/rotate_A_flags_ff0/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/rotate_A_flags_ff1/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/rotate_A_flags_ff2/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/rotate_A_flags_ff3/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/rotate_A_load/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/rotate_flags_ff0/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/rotate_flags_ff1/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/rotate_load/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/selected[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/selected[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/selected[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/selected[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/selected[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/selected[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/selected[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/selected[7]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/selected[8]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/selected[9]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/selected[10]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/selected[11]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/selected[12]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/selected[13]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/zoom_flags_ff0/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/zoom_flags_ff1/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/zoom_flags_ff2/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/zoom_flags_ff3/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + param_manager_inst/zoom_load/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0_A2Q1/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[11]/opit_0_inv_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[11]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[11]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[10]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[11]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[3]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[6]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[7]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[9]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[10]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[11]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[6]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[8]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[11]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/arp_rx_done/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/arp_rx_type/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt[0]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt[1]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt[2]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt[3]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt[4]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[4]/opit_0_L6Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[1]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[2]/opit_0_L5Q/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[3]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[4]/opit_0_L5Q/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[5]/opit_0_L5Q/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[6]/opit_0_L5Q/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[7]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[8]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[9]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[10]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[11]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[12]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[13]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[14]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[15]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[16]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[17]/opit_0_L5Q/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[18]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[19]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[20]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[21]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[22]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[23]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[24]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[25]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[26]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[27]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[28]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[29]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[30]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[31]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[3]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[4]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[8]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[9]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[10]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[11]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[12]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[13]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[14]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[15]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[16]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[17]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[18]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[19]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[20]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[21]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[22]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[23]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[24]/opit_0_L5Q/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[25]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[26]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[27]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[28]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[29]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[30]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[31]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[32]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[33]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[34]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[35]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[36]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[37]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[38]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[39]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[40]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[41]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[42]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[43]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[44]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[45]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[46]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[47]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/error_en/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/eth_type[8]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/eth_type[9]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/eth_type[10]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/eth_type[11]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/eth_type[12]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/eth_type[13]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/eth_type[14]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/eth_type[15]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[3]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[4]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[6]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[7]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[8]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[9]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[10]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[11]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[12]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[13]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[14]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[15]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/skip_en/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[3]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[6]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[7]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[8]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[9]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[10]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[11]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[12]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[13]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[14]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[15]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[16]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[17]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[18]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[19]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[20]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[21]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[22]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[23]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[24]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[25]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[26]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[27]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[28]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[29]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[30]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[31]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[3]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[4]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[6]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[7]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[8]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[9]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[10]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[11]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[12]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[13]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[14]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[15]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[16]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[17]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[18]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[19]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[20]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[21]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[22]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[23]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[24]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[25]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[26]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[27]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[28]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[29]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[30]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[31]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[3]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[4]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[6]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[7]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[8]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[9]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[10]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[11]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[12]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[13]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[14]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[15]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[16]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[17]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[18]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[19]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[20]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[21]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[22]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[23]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[24]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[25]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[26]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[27]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[28]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[29]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[30]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[31]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[32]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[33]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[34]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[35]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[36]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[37]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[38]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[39]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[40]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[41]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[42]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[43]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[44]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[45]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[46]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[47]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[3]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[4]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[6]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[7]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[8]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[9]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[10]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[11]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[12]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[13]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[14]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[15]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[16]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[17]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[18]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[19]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[20]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[21]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[22]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[23]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[24]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[25]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[26]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[27]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[28]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[29]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[30]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[31]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[32]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[33]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[34]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[35]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[36]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[37]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[38]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[39]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[40]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[41]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[42]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[43]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[44]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[45]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[46]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[47]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[7][0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[7][1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[18][0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[18][1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[18][2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[18][3]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[18][4]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[18][5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[18][6]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[18][7]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[19][0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[19][1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[19][2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[19][3]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[19][4]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[19][5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[19][6]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[19][7]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[20][0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[20][1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[20][2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[20][3]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[20][4]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[20][5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[20][6]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[20][7]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[21][0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[21][1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[21][2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[21][3]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[21][4]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[21][5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[21][6]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[21][7]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[22][0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[22][1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[22][2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[22][3]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[22][4]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[22][5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[22][6]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[22][7]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[23][0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[23][1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[23][2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[23][3]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[23][4]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[23][5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[23][6]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[23][7]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][3]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][4]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][6]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][7]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][3]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][4]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][6]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][7]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[26][0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[26][1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[26][2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[26][3]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[26][4]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[26][5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[26][6]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[26][7]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][3]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][4]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][6]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][7]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[0]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[1]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[2]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[3]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[4]/opit_0_A2Q1/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[5]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/crc_clr/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/crc_en/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cur_state_reg[0]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cur_state_reg[1]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cur_state_reg[2]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cur_state_reg[3]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cur_state_reg[4]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/data_cnt[0]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/data_cnt[1]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/data_cnt[2]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/data_cnt[3]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/data_cnt[4]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/gmii_txd_data[0]/opit_0_MUX4TO1Q/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/gmii_txd_data[1]/opit_0_MUX4TO1Q/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/gmii_txd_data[2]/opit_0_MUX4TO1Q/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/gmii_txd_data[3]/opit_0_MUX4TO1Q/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/gmii_txd_data[4]/opit_0_MUX4TO1Q/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/gmii_txd_data[5]/opit_0_MUX4TO1Q/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/gmii_txd_data[6]/opit_0_MUX4TO1Q/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/gmii_txd_data[7]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/gmii_txd_valid/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/skip_en/opit_0_MUX4TO1Q/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/tx_done_t/opit_0_MUX4TO1Q/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/tx_en_d0/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/tx_en_d1/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/tx_en_d2/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[0]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[1]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[2]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[3]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[4]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[5]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[6]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[7]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[8]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[9]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[10]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[11]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[12]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[13]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[14]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[15]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[16]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[17]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[18]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[19]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[20]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[21]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[22]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[23]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[24]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[25]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[26]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[27]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[28]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[29]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[30]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[31]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_eth_ctrl/arp_rx_flag/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_eth_ctrl/arp_tx_en/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[0]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[1]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[2]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[3]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[4]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[5]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[6]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[7]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_valid/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_eth_ctrl/icmp_tx_req_d0/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_eth_ctrl/protocol_sw_reg[0]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[3]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[4]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[6]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[7]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_en/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_ctl_in/gateigddr_IOL/SYSCLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_rxd_data[0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_rxd_data[1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_rxd_data[2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_rxd_data[3]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_rxd_data[4]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_rxd_data[5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_rxd_data[6]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_rxd_data[7]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_rxd_valid/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gtp_outbuft1/opit_1_IOL/SYSCLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gtp_outbuft6/opit_1_IOL/SYSCLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rx_data[0].gmii_rxd_in/gateigddr_IOL/SYSCLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rx_data[1].gmii_rxd_in/gateigddr_IOL/SYSCLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rx_data[2].gmii_rxd_in/gateigddr_IOL/SYSCLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rx_data[3].gmii_rxd_in/gateigddr_IOL/SYSCLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_tx_data[0].gtp_outbuft1/opit_1_IOL/SYSCLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_tx_data[1].gtp_outbuft1/opit_1_IOL/SYSCLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_tx_data[2].gtp_outbuft1/opit_1_IOL/SYSCLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_tx_data[3].gtp_outbuft1/opit_1_IOL/SYSCLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[0]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[1]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[2]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[3]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[4]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[5]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[6]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[7]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[8]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[9]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[10]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[11]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[12]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[13]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[14]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[15]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[16]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[17]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[18]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[19]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[20]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[21]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[22]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[23]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[24]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[25]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[26]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[27]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[28]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[29]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[30]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[31]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[0]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[1]/opit_0_L5Q/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[2]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[3]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[4]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[5]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[6]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[8]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[9]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[10]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[11]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[12]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[13]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[14]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[15]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[16]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[17]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[18]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[19]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[20]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[21]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[22]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[23]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[6]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[8]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[9]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[10]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[11]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[12]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[13]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[14]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[15]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[16]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[17]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[18]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[19]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[20]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[21]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[22]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[23]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[24]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[25]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[26]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[27]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[28]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[29]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[30]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[31]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[32]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[33]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[34]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[35]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[36]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[37]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[38]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[39]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[40]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[41]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[42]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[43]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[44]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[45]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[46]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[47]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/error_en/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/eth_type[8]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/eth_type[9]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/eth_type[10]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/eth_type[11]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/eth_type[12]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/eth_type[13]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/eth_type[14]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/eth_type[15]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[2]/opit_0_L5Q/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[4]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[6]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[8]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[10]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[12]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[14]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[15]/opit_0_AQ/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[3]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[4]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[6]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[7]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[8]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[9]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[10]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[11]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[12]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[13]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[14]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[15]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[0]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[2]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[4]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[6]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[8]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[10]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[12]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[14]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[15]/opit_0_AQ_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_data_d0[0]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_data_d0[1]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_data_d0[2]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_data_d0[3]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_data_d0[4]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_data_d0[5]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_data_d0[6]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_data_d0[7]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[3]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[4]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[6]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[7]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[8]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[9]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[10]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[11]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[12]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[13]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[14]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[15]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_type[0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_type[1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_type[2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_type[3]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_type[4]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_type[5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_type[6]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_type[7]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/ip_head_byte_num[2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/ip_head_byte_num[3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/ip_head_byte_num[4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/ip_head_byte_num[5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[3]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[4]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[6]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[7]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[8]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[9]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[10]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[11]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[12]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[13]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[14]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[15]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_data[0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_data[1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_data[2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_data[3]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_data[4]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_data[5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_data[6]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_data[7]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_en/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_pkt_done/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[3]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[4]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[6]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[7]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[8]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[9]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[10]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[11]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[12]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[13]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[14]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[15]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[16]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[17]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[18]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[19]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[20]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[21]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[22]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[23]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[24]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[25]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[26]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[27]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[28]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[29]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[30]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[31]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[0]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[1]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[2]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[3]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[4]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[5]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[6]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[7]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[8]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[9]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[10]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[11]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[12]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[13]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[14]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[15]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[16]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[17]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[18]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[19]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[20]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[21]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[22]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[23]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[24]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[25]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[26]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[27]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[28]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[29]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[30]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[31]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/skip_en/opit_0_MUX4TO1Q/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[3]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[4]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[6]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[7]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[8]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[9]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[10]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[11]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[12]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[13]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[14]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[15]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer[1]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer[3]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer[5]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer[7]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer[9]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer[11]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer[13]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer[15]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer[17]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer[19]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[1]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[3]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[5]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[7]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[9]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[11]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[13]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[15]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[17]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[19]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[21]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[23]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[25]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[27]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[29]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[31]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cnt[0]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cnt[1]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cnt[2]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cnt[3]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cnt[4]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/crc_clr/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/crc_en/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[0]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[1]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[2]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[3]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[4]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[5]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[6]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[7]/opit_0_L5Q/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[0]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[2]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[4]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[6]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[8]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[10]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[12]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[14]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[15]/opit_0_AQ_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[0][0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[0][1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[0][2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[0][3]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[0][4]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[0][5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[0][6]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[0][7]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[1][0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[1][1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[1][2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[1][3]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[1][4]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[1][5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[1][6]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[1][7]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[2][0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[2][1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[2][2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[2][3]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[2][4]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[2][5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[2][6]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[2][7]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[3][0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[3][1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[3][2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[3][3]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[3][4]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[3][5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[3][6]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[3][7]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[4][0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[4][1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[4][2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[4][3]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[4][4]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[4][5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[4][6]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[4][7]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[5][0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[5][1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[5][2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[5][3]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[5][4]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[5][5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[5][6]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[5][7]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/gmii_txd_data[0]/opit_0_MUX4TO1Q/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/gmii_txd_data[1]/opit_0_MUX4TO1Q/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/gmii_txd_data[2]/opit_0_MUX4TO1Q/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/gmii_txd_data[3]/opit_0_MUX4TO1Q/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/gmii_txd_data[4]/opit_0_MUX4TO1Q/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/gmii_txd_data[5]/opit_0_MUX4TO1Q/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/gmii_txd_data[6]/opit_0_MUX4TO1Q/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/gmii_txd_data[7]/opit_0_MUX4TO1Q/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/gmii_txd_valid/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][3]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][4]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][6]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][7]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][8]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][9]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][10]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][11]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][12]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][13]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][14]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][15]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][16]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][18]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][20]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][22]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][24]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][26]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][28]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][30]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][31]/opit_0_AQ/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][0]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][1]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][2]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][3]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][4]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][5]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][6]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][7]/opit_0_L5Q/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][8]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][9]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][10]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][11]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][12]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][13]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][14]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][15]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][3]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][4]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][6]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][7]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][8]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][9]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][10]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][11]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][12]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][13]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][14]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][15]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][16]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][17]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][18]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][19]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][20]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][21]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][22]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][23]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][24]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][25]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][26]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][27]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][28]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][29]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][30]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][31]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][0]/opit_0_L5Q/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][1]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][2]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][3]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][4]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][5]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][6]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][7]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][8]/opit_0_L5Q/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][9]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][10]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][11]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][12]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][13]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][14]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][15]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][3]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][4]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][6]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][7]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][8]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][9]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][10]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][11]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][12]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][13]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][14]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][15]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][16]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][17]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][18]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][19]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][20]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][21]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][22]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][23]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][24]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][25]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][26]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][27]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][28]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][29]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][30]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][31]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/real_add_cnt[0]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/real_add_cnt[1]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/real_add_cnt[2]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/real_add_cnt[3]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/real_add_cnt[4]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/skip_en/opit_0_MUX4TO1Q/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/start_en_d0/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/start_en_d1/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/start_en_d2/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[2]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[4]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[6]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[8]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[10]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[12]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[14]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[15]/opit_0_AQ/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/trig_tx_en/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_bit_sel[0]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_bit_sel[1]/opit_0_MUX4TO1Q/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[3]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[4]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[6]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[7]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[8]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[9]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[10]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[11]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[12]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[13]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[14]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[15]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_done_t/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_req/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt[0]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt[2]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt[3]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt[4]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[1]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[5]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[6]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[5]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[7]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[9]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[11]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[13]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[15]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_cnt[0]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_cnt[2]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_cnt[4]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_cnt[6]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_cnt[8]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_cnt[10]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_cnt[12]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_cnt[14]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_cnt[15]/opit_0_AQ_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[3]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[4]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[6]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[7]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[8]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[9]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[10]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[11]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[12]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[13]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[14]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[15]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[16]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[17]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[18]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[19]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[20]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[21]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[22]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[23]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[8]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[9]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[10]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[11]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[12]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[13]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[14]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[15]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[16]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[17]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[18]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[19]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[20]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[21]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[22]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[23]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[24]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[25]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[26]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[27]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[28]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[29]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[30]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[31]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[32]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[33]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[34]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[35]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[36]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[37]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[38]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[39]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[40]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[41]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[42]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[43]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[44]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[45]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[46]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[47]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/error_en/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/eth_type[8]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/eth_type[9]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/eth_type[10]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/eth_type[11]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/eth_type[12]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/eth_type[13]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/eth_type[14]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/eth_type[15]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[0]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[7]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[8]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[9]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[10]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[11]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[12]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[13]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[14]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[15]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_data[0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_data[1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_data[2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_data[3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_data[4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_data[5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_data[6]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_data[7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_en/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_pkt_done/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_pkt_start/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/skip_en/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[3]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[4]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[5]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[6]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[7]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[8]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[9]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[10]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[11]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[12]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[13]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[14]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[15]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[3]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[4]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[6]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[7]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[8]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[9]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[10]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[11]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[12]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[13]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[14]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[15]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_done_cdc/in_req/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_done_cdc/out_ack_sync0/opit_0_inv/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_done_cdc/out_ack_sync1/opit_0_inv/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/opit_0_inv_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[2]/opit_0_inv_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[4]/opit_0_inv_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[6]/opit_0_inv_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[8]/opit_0_inv_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[10]/opit_0_inv_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_MUX4TO1Q/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_MUX4TO1Q/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_MUX4TO1Q/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_MUX4TO1Q/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_MUX4TO1Q/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_MUX4TO1Q/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_MUX4TO1Q/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_MUX4TO1Q/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_MUX4TO1Q/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[10]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[11]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[0]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[5]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[6]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[8]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[11]/opit_0/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (8.567, 10.153, 8.673, 10.299) + + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_start_i_ff/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/data_count[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/data_count[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/data_count[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/data_count[4]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/data_count[6]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/data_count[7]/opit_0_AQ_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/flags[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/flags[1]/opit_0_L5Q/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/flags[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/flags[3]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/flags[4]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/flags[5]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/flags[6]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/flags[7]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/flags[8]/opit_0_L5Q/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/flags[9]/opit_0_L5Q/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/flags[10]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/flags[11]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/flags[12]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/flags[13]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/flags[14]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/flags[15]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/flags[16]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/flags[17]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/flags[18]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/flags[19]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/flags[20]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/flags[21]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/flags[22]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/flags[23]/opit_0_L5Q/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/flags[24]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/index[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/index[1]/opit_0_A2Q1/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/index[3]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/index[5]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/index[7]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[0]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[1]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[2]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[8]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[9]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[10]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[16]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[17]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[18]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[19]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[20]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[21]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[22]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[23]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[24]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[25]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[32]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[33]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[34]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[35]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[36]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[37]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[38]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[39]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[40]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[41]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[42]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[43]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[44]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[45]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[46]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[47]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[48]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[49]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[50]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[56]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[57]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[58]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[59]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[60]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[61]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[62]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[63]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[64]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[65]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[66]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[72]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[73]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[74]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[75]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[76]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[77]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[78]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[79]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[80]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[81]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[82]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[88]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[89]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[90]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[91]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[92]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[93]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[94]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[95]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[96]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[97]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[98]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[104]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[105]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[106]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[107]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[108]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[109]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[110]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[111]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[112]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[113]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[120]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[121]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[122]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[123]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[124]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[125]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[126]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[127]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[128]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[129]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[130]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[131]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[136]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[137]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[138]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[139]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[140]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[141]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[142]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[143]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[144]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[145]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[146]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[147]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[152]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[153]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[154]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[155]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[156]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[157]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[158]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[159]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[160]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[168]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[169]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[170]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[171]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[172]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[173]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[174]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[175]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[176]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[184]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[185]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[186]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[187]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[188]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[189]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[190]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[191]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/mem[192]/opit_0/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/pkt_data_cnt[0]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/pkt_data_cnt[1]/opit_0_A2Q1/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/pkt_data_cnt[3]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/pkt_data_cnt[5]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/pkt_data_cnt[7]/opit_0_A2Q21/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/pkt_data_cnt[9]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_wr_mem_inst/pkt_data_cnt[11]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_wr_mem_inst/pkt_data_cnt[13]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_wr_mem_inst/pkt_data_cnt[15]/opit_0_A2Q21/CLK (8.567, 10.153, 8.673, 10.299) + + + udp_wr_mem_inst/state_reg[0]/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/state_reg[1]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/state_reg[2]/opit_0_L5Q_perm/CLK (8.446, 10.030, 8.558, 10.181) + + + udp_wr_mem_inst/state_reg[3]/opit_0_MUX4TO1Q/CLK (8.446, 10.030, 8.558, 10.181) + + + + + + + + + + + + + + + + + clk_100m (100.00MHZ) (drive 0 loads) (min_rise, max_rise, min_fall, max_fall) + + + clk_1080p60Hz (148.44MHZ) (drive 750 loads) (min_rise, max_rise, min_fall, max_fall) + + + clk_720p60Hz (74.22MHZ) (drive 1635 loads) (min_rise, max_rise, min_fall, max_fall) + + + clk_20k (0.02MHZ) (drive 38 loads) (min_rise, max_rise, min_fall, max_fall) + +
+ + + Slack + Logic Levels + High Fanout + Start Point + End Point + Exception + Launch Clock + Capture Clock + Clock Edges + Clock Skew + Launch Clock Delay + Capture Clock Delay + Clock Pessimism Removal + Requirement + Data delay + Logic delay + Route delay + + + 1.026 + 6 + 187 + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/CLK + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[4]/opit_0/D + + eth_rxc + eth_rxc + rise-rise + -0.029 + 10.153 + 8.567 + 1.557 + 8.000 + 6.607 + 1.613 (24.4%) + 4.994 (75.6%) + + Path #1: setup slack is 1.026(MET) + +
+ + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock eth_rxc (rising edge) + + 0.000 + 0.000 + r + + + + F14 + + 0.000 + 0.000 + r + eth_rxc (port) + + + + net (fanout=1) + 0.057 + 0.057 + + eth_rxc + + + IOBD_240_376/DIN + td + 1.254 + 1.311 + r + eth_rxc_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.311 + + eth_rxc_ibuf/ntD + + + IOL_243_374/INCK + td + 0.076 + 1.387 + r + eth_rxc_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.647 + 2.034 + + _N66 + + + IOCKDLY_237_367/CLK_OUT + td + 3.812 + 5.846 + r + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT + + + + net (fanout=1) + 2.599 + 8.445 + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf + + + USCM_84_109/CLK_USCM + td + 0.000 + 8.445 + r + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT + + + + net (fanout=1862) + 1.708 + 10.153 + + gmii_clk + + + CLMA_194_261/CLK + + + + r + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/CLK + + + CLMA_194_261/Q0 + tco + 0.289 + 10.442 + r + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/Q + + + + net (fanout=2) + 0.817 + 11.259 + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t [0] + + + CLMA_182_241/Y1 + td + 0.288 + 11.547 + r + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_39/gateop_perm/Z + + + + net (fanout=1) + 0.698 + 12.245 + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108159 + + + CLMA_190_252/Y3 + td + 0.210 + 12.455 + r + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_59/gateop_perm/Z + + + + net (fanout=1) + 0.559 + 13.014 + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108179 + + + CLMA_190_240/Y2 + td + 0.210 + 13.224 + r + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_63/gateop_perm/Z + + + + net (fanout=2) + 0.934 + 14.158 + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446 + + + CLMA_210_265/Y3 + td + 0.210 + 14.368 + r + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N289_6/gateop_perm/Z + + + + net (fanout=6) + 0.490 + 14.858 + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108187 + + + CLMA_198_264/Y3 + td + 0.210 + 15.068 + r + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/arp_rx_done/opit_0_L5Q_perm/Z + + + + net (fanout=187) + 0.763 + 15.831 + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N319 + + + CLMA_194_264/Y0 + td + 0.196 + 16.027 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[4]/opit_0_L5Q/Z + + + + net (fanout=3) + 0.733 + 16.760 + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N642 [4] + + + CLMA_194_257/M1 + + + + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[4]/opit_0/D + +
+ + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock eth_rxc (rising edge) + + 8.000 + 8.000 + r + + + + F14 + + 0.000 + 8.000 + r + eth_rxc (port) + + + + net (fanout=1) + 0.057 + 8.057 + + eth_rxc + + + IOBD_240_376/DIN + td + 1.047 + 9.104 + r + eth_rxc_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 9.104 + + eth_rxc_ibuf/ntD + + + IOL_243_374/INCK + td + 0.048 + 9.152 + r + eth_rxc_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.636 + 9.788 + + _N66 + + + IOCKDLY_237_367/CLK_OUT + td + 2.574 + 12.362 + r + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT + + + + net (fanout=1) + 2.553 + 14.915 + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf + + + USCM_84_109/CLK_USCM + td + 0.000 + 14.915 + r + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT + + + + net (fanout=1862) + 1.652 + 16.567 + + gmii_clk + + + CLMA_194_257/CLK + + + + r + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[4]/opit_0/CLK + + + clock pessimism + + 1.557 + 18.124 + + + + + clock uncertainty + + -0.250 + 17.874 + + + + + Setup time + + -0.088 + 17.786 + + + +
+
+ +
+ + 1.030 + 7 + 187 + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/CLK + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[14]/opit_0/CE + + eth_rxc + eth_rxc + rise-rise + -0.036 + 10.153 + 8.567 + 1.550 + 8.000 + 5.955 + 1.785 (30.0%) + 4.170 (70.0%) + + Path #2: setup slack is 1.030(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock eth_rxc (rising edge) + + 0.000 + 0.000 + r + + + + F14 + + 0.000 + 0.000 + r + eth_rxc (port) + + + + net (fanout=1) + 0.057 + 0.057 + + eth_rxc + + + IOBD_240_376/DIN + td + 1.254 + 1.311 + r + eth_rxc_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.311 + + eth_rxc_ibuf/ntD + + + IOL_243_374/INCK + td + 0.076 + 1.387 + r + eth_rxc_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.647 + 2.034 + + _N66 + + + IOCKDLY_237_367/CLK_OUT + td + 3.812 + 5.846 + r + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT + + + + net (fanout=1) + 2.599 + 8.445 + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf + + + USCM_84_109/CLK_USCM + td + 0.000 + 8.445 + r + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT + + + + net (fanout=1862) + 1.708 + 10.153 + + gmii_clk + + + CLMA_194_261/CLK + + + + r + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/CLK + + + CLMA_194_261/Q0 + tco + 0.289 + 10.442 + r + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/Q + + + + net (fanout=2) + 0.817 + 11.259 + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t [0] + + + CLMA_182_241/Y1 + td + 0.288 + 11.547 + r + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_39/gateop_perm/Z + + + + net (fanout=1) + 0.698 + 12.245 + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108159 + + + CLMA_190_252/Y3 + td + 0.210 + 12.455 + r + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_59/gateop_perm/Z + + + + net (fanout=1) + 0.559 + 13.014 + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108179 + + + CLMA_190_240/Y2 + td + 0.210 + 13.224 + r + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_63/gateop_perm/Z + + + + net (fanout=2) + 0.934 + 14.158 + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446 + + + CLMA_210_265/Y3 + td + 0.210 + 14.368 + r + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N289_6/gateop_perm/Z + + + + net (fanout=6) + 0.490 + 14.858 + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108187 + + + CLMA_198_264/Y3 + td + 0.210 + 15.068 + r + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/arp_rx_done/opit_0_L5Q_perm/Z + + + + net (fanout=187) + 0.672 + 15.740 + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N319 + + + CLMA_202_272/CECO + td + 0.184 + 15.924 + r + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[47]/opit_0/CEOUT + + + + net (fanout=1) + 0.000 + 15.924 + + ntR2081 + + + CLMA_202_276/CECO + td + 0.184 + 16.108 + r + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[42]/opit_0/CEOUT + + + + net (fanout=6) + 0.000 + 16.108 + + ntR2080 + + + CLMA_202_280/CECI + + + + r + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[14]/opit_0/CE + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock eth_rxc (rising edge) + + 8.000 + 8.000 + r + + + + F14 + + 0.000 + 8.000 + r + eth_rxc (port) + + + + net (fanout=1) + 0.057 + 8.057 + + eth_rxc + + + IOBD_240_376/DIN + td + 1.047 + 9.104 + r + eth_rxc_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 9.104 + + eth_rxc_ibuf/ntD + + + IOL_243_374/INCK + td + 0.048 + 9.152 + r + eth_rxc_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.636 + 9.788 + + _N66 + + + IOCKDLY_237_367/CLK_OUT + td + 2.574 + 12.362 + r + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT + + + + net (fanout=1) + 2.553 + 14.915 + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf + + + USCM_84_109/CLK_USCM + td + 0.000 + 14.915 + r + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT + + + + net (fanout=1862) + 1.652 + 16.567 + + gmii_clk + + + CLMA_202_280/CLK + + + + r + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[14]/opit_0/CLK + + + clock pessimism + + 1.550 + 18.117 + + + + + clock uncertainty + + -0.250 + 17.867 + + + + + Setup time + + -0.729 + 17.138 + + + +
+
+
+
+ + 1.030 + 7 + 187 + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/CLK + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[22]/opit_0/CE + + eth_rxc + eth_rxc + rise-rise + -0.036 + 10.153 + 8.567 + 1.550 + 8.000 + 5.955 + 1.785 (30.0%) + 4.170 (70.0%) + + Path #3: setup slack is 1.030(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock eth_rxc (rising edge) + + 0.000 + 0.000 + r + + + + F14 + + 0.000 + 0.000 + r + eth_rxc (port) + + + + net (fanout=1) + 0.057 + 0.057 + + eth_rxc + + + IOBD_240_376/DIN + td + 1.254 + 1.311 + r + eth_rxc_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.311 + + eth_rxc_ibuf/ntD + + + IOL_243_374/INCK + td + 0.076 + 1.387 + r + eth_rxc_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.647 + 2.034 + + _N66 + + + IOCKDLY_237_367/CLK_OUT + td + 3.812 + 5.846 + r + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT + + + + net (fanout=1) + 2.599 + 8.445 + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf + + + USCM_84_109/CLK_USCM + td + 0.000 + 8.445 + r + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT + + + + net (fanout=1862) + 1.708 + 10.153 + + gmii_clk + + + CLMA_194_261/CLK + + + + r + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/CLK + + + CLMA_194_261/Q0 + tco + 0.289 + 10.442 + r + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/Q + + + + net (fanout=2) + 0.817 + 11.259 + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t [0] + + + CLMA_182_241/Y1 + td + 0.288 + 11.547 + r + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_39/gateop_perm/Z + + + + net (fanout=1) + 0.698 + 12.245 + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108159 + + + CLMA_190_252/Y3 + td + 0.210 + 12.455 + r + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_59/gateop_perm/Z + + + + net (fanout=1) + 0.559 + 13.014 + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108179 + + + CLMA_190_240/Y2 + td + 0.210 + 13.224 + r + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_63/gateop_perm/Z + + + + net (fanout=2) + 0.934 + 14.158 + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446 + + + CLMA_210_265/Y3 + td + 0.210 + 14.368 + r + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N289_6/gateop_perm/Z + + + + net (fanout=6) + 0.490 + 14.858 + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108187 + + + CLMA_198_264/Y3 + td + 0.210 + 15.068 + r + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/arp_rx_done/opit_0_L5Q_perm/Z + + + + net (fanout=187) + 0.672 + 15.740 + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N319 + + + CLMA_202_272/CECO + td + 0.184 + 15.924 + r + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[47]/opit_0/CEOUT + + + + net (fanout=1) + 0.000 + 15.924 + + ntR2081 + + + CLMA_202_276/CECO + td + 0.184 + 16.108 + r + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[42]/opit_0/CEOUT + + + + net (fanout=6) + 0.000 + 16.108 + + ntR2080 + + + CLMA_202_280/CECI + + + + r + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[22]/opit_0/CE + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock eth_rxc (rising edge) + + 8.000 + 8.000 + r + + + + F14 + + 0.000 + 8.000 + r + eth_rxc (port) + + + + net (fanout=1) + 0.057 + 8.057 + + eth_rxc + + + IOBD_240_376/DIN + td + 1.047 + 9.104 + r + eth_rxc_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 9.104 + + eth_rxc_ibuf/ntD + + + IOL_243_374/INCK + td + 0.048 + 9.152 + r + eth_rxc_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.636 + 9.788 + + _N66 + + + IOCKDLY_237_367/CLK_OUT + td + 2.574 + 12.362 + r + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT + + + + net (fanout=1) + 2.553 + 14.915 + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf + + + USCM_84_109/CLK_USCM + td + 0.000 + 14.915 + r + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT + + + + net (fanout=1862) + 1.652 + 16.567 + + gmii_clk + + + CLMA_202_280/CLK + + + + r + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[22]/opit_0/CLK + + + clock pessimism + + 1.550 + 18.117 + + + + + clock uncertainty + + -0.250 + 17.867 + + + + + Setup time + + -0.729 + 17.138 + + + +
+
+
+
+ + 1.083 + 0 + 3 + u_zoom_image/mult_fra1_0/N2/gopapm/CLK + u_zoom_image/mult_image_g1_0/N2/gopapm/X[3] + + clk_1080p60Hz + clk_1080p60Hz + rise-rise + -0.177 + 9.563 + 8.835 + 0.551 + 6.736 + 3.083 + 1.067 (34.6%) + 2.016 (65.4%) + + Path #4: setup slack is 1.083(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_1080p60Hz (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.107 + 3.210 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.078 + 4.288 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 4.288 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.861 + 6.149 + + ntR3950 + + + PLL_158_303/CLK_OUT0 + td + 0.107 + 6.256 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=1) + 1.599 + 7.855 + + zoom_clk + + + USCM_84_118/CLK_USCM + td + 0.000 + 7.855 + r + clkbufg_3/gopclkbufg/CLKOUT + + + + net (fanout=750) + 1.708 + 9.563 + + ntclkbufg_3 + + + APM_206_264/CLK + + + + r + u_zoom_image/mult_fra1_0/N2/gopapm/CLK + + + APM_206_264/P[34] + tco + 1.067 + 10.630 + f + u_zoom_image/mult_fra1_0/N2/gopapm/P[10] + + + + net (fanout=3) + 2.016 + 12.646 + + u_zoom_image/coe_mult_p1_0 [10] + + + APM_206_140/X[3] + + + + f + u_zoom_image/mult_image_g1_0/N2/gopapm/X[3] + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_1080p60Hz (rising edge) + + 6.736 + 6.736 + r + + + + P20 + + 0.000 + 6.736 + r + clk (port) + + + + net (fanout=1) + 0.074 + 6.810 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 8.618 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 8.618 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 8.666 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 9.424 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.100 + 9.524 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.059 + 10.583 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 10.583 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.786 + 12.369 + + ntR3950 + + + PLL_158_303/CLK_OUT0 + td + 0.100 + 12.469 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=1) + 1.571 + 14.040 + + zoom_clk + + + USCM_84_118/CLK_USCM + td + 0.000 + 14.040 + r + clkbufg_3/gopclkbufg/CLKOUT + + + + net (fanout=750) + 1.531 + 15.571 + + ntclkbufg_3 + + + APM_206_140/CLK + + + + r + u_zoom_image/mult_image_g1_0/N2/gopapm/CLK + + + clock pessimism + + 0.551 + 16.122 + + + + + clock uncertainty + + -0.150 + 15.972 + + + + + Setup time + + -2.243 + 13.729 + + + +
+
+
+
+ + 1.099 + 0 + 3 + u_zoom_image/mult_fra1_0/N2/gopapm/CLK + u_zoom_image/mult_image_g1_0/N2/gopapm/X[0] + + clk_1080p60Hz + clk_1080p60Hz + rise-rise + -0.177 + 9.563 + 8.835 + 0.551 + 6.736 + 3.067 + 1.067 (34.8%) + 2.000 (65.2%) + + Path #5: setup slack is 1.099(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_1080p60Hz (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.107 + 3.210 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.078 + 4.288 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 4.288 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.861 + 6.149 + + ntR3950 + + + PLL_158_303/CLK_OUT0 + td + 0.107 + 6.256 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=1) + 1.599 + 7.855 + + zoom_clk + + + USCM_84_118/CLK_USCM + td + 0.000 + 7.855 + r + clkbufg_3/gopclkbufg/CLKOUT + + + + net (fanout=750) + 1.708 + 9.563 + + ntclkbufg_3 + + + APM_206_264/CLK + + + + r + u_zoom_image/mult_fra1_0/N2/gopapm/CLK + + + APM_206_264/P[31] + tco + 1.067 + 10.630 + f + u_zoom_image/mult_fra1_0/N2/gopapm/P[7] + + + + net (fanout=3) + 2.000 + 12.630 + + u_zoom_image/coe_mult_p1_0 [7] + + + APM_206_140/X[0] + + + + f + u_zoom_image/mult_image_g1_0/N2/gopapm/X[0] + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_1080p60Hz (rising edge) + + 6.736 + 6.736 + r + + + + P20 + + 0.000 + 6.736 + r + clk (port) + + + + net (fanout=1) + 0.074 + 6.810 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 8.618 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 8.618 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 8.666 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 9.424 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.100 + 9.524 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.059 + 10.583 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 10.583 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.786 + 12.369 + + ntR3950 + + + PLL_158_303/CLK_OUT0 + td + 0.100 + 12.469 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=1) + 1.571 + 14.040 + + zoom_clk + + + USCM_84_118/CLK_USCM + td + 0.000 + 14.040 + r + clkbufg_3/gopclkbufg/CLKOUT + + + + net (fanout=750) + 1.531 + 15.571 + + ntclkbufg_3 + + + APM_206_140/CLK + + + + r + u_zoom_image/mult_image_g1_0/N2/gopapm/CLK + + + clock pessimism + + 0.551 + 16.122 + + + + + clock uncertainty + + -0.150 + 15.972 + + + + + Setup time + + -2.243 + 13.729 + + + +
+
+
+
+ + 1.121 + 5 + 11 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CE + + clk_200m + clk_200m + rise-rise + 0.000 + 5.867 + 5.374 + 0.493 + 5.000 + 3.000 + 1.911 (63.7%) + 1.089 (36.3%) + + Path #6: setup slack is 1.121(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_200m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.101 + 3.204 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.078 + 4.282 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 4.282 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.585 + 5.867 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + CLMA_90_197/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK + + + CLMA_90_197/Q1 + tco + 0.291 + 6.158 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/Q + + + + net (fanout=2) + 0.408 + 6.566 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt [15] + + + CLMS_94_197/Y0 + td + 0.487 + 7.053 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_33/gateop_perm/Z + + + + net (fanout=2) + 0.123 + 7.176 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107154 + + + CLMA_94_196/Y2 + td + 0.478 + 7.654 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_36/gateop_perm/Z + + + + net (fanout=1) + 0.120 + 7.774 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107157 + + + CLMA_94_196/Y3 + td + 0.287 + 8.061 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43_3/gateop_perm/Z + + + + net (fanout=11) + 0.438 + 8.499 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43 + + + CLMA_90_185/CECO + td + 0.184 + 8.683 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[8]/opit_0_inv_L5Q_perm/CEOUT + + + + net (fanout=4) + 0.000 + 8.683 + + ntR1851 + + + CLMA_90_193/CECO + td + 0.184 + 8.867 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[11]/opit_0_inv_L5Q_perm/CEOUT + + + + net (fanout=4) + 0.000 + 8.867 + + ntR1850 + + + CLMA_90_197/CECI + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CE + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_200m (rising edge) + + 5.000 + 5.000 + r + + + + P20 + + 0.000 + 5.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 5.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 6.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 6.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 6.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 7.688 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.096 + 7.784 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.059 + 8.843 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 8.843 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.531 + 10.374 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + CLMA_90_197/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK + + + clock pessimism + + 0.493 + 10.867 + + + + + clock uncertainty + + -0.150 + 10.717 + + + + + Setup time + + -0.729 + 9.988 + + + +
+
+
+
+ + 1.121 + 5 + 11 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[16]/opit_0_inv_L5Q_perm/CE + + clk_200m + clk_200m + rise-rise + 0.000 + 5.867 + 5.374 + 0.493 + 5.000 + 3.000 + 1.911 (63.7%) + 1.089 (36.3%) + + Path #7: setup slack is 1.121(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_200m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.101 + 3.204 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.078 + 4.282 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 4.282 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.585 + 5.867 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + CLMA_90_197/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK + + + CLMA_90_197/Q1 + tco + 0.291 + 6.158 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/Q + + + + net (fanout=2) + 0.408 + 6.566 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt [15] + + + CLMS_94_197/Y0 + td + 0.487 + 7.053 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_33/gateop_perm/Z + + + + net (fanout=2) + 0.123 + 7.176 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107154 + + + CLMA_94_196/Y2 + td + 0.478 + 7.654 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_36/gateop_perm/Z + + + + net (fanout=1) + 0.120 + 7.774 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107157 + + + CLMA_94_196/Y3 + td + 0.287 + 8.061 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43_3/gateop_perm/Z + + + + net (fanout=11) + 0.438 + 8.499 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43 + + + CLMA_90_185/CECO + td + 0.184 + 8.683 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[8]/opit_0_inv_L5Q_perm/CEOUT + + + + net (fanout=4) + 0.000 + 8.683 + + ntR1851 + + + CLMA_90_193/CECO + td + 0.184 + 8.867 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[11]/opit_0_inv_L5Q_perm/CEOUT + + + + net (fanout=4) + 0.000 + 8.867 + + ntR1850 + + + CLMA_90_197/CECI + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[16]/opit_0_inv_L5Q_perm/CE + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_200m (rising edge) + + 5.000 + 5.000 + r + + + + P20 + + 0.000 + 5.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 5.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 6.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 6.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 6.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 7.688 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.096 + 7.784 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.059 + 8.843 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 8.843 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.531 + 10.374 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + CLMA_90_197/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[16]/opit_0_inv_L5Q_perm/CLK + + + clock pessimism + + 0.493 + 10.867 + + + + + clock uncertainty + + -0.150 + 10.717 + + + + + Setup time + + -0.729 + 9.988 + + + +
+
+
+
+ + 1.121 + 5 + 11 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[17]/opit_0_inv_L5Q_perm/CE + + clk_200m + clk_200m + rise-rise + 0.000 + 5.867 + 5.374 + 0.493 + 5.000 + 3.000 + 1.911 (63.7%) + 1.089 (36.3%) + + Path #8: setup slack is 1.121(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_200m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.101 + 3.204 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.078 + 4.282 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 4.282 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.585 + 5.867 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + CLMA_90_197/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK + + + CLMA_90_197/Q1 + tco + 0.291 + 6.158 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/Q + + + + net (fanout=2) + 0.408 + 6.566 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt [15] + + + CLMS_94_197/Y0 + td + 0.487 + 7.053 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_33/gateop_perm/Z + + + + net (fanout=2) + 0.123 + 7.176 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107154 + + + CLMA_94_196/Y2 + td + 0.478 + 7.654 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_36/gateop_perm/Z + + + + net (fanout=1) + 0.120 + 7.774 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107157 + + + CLMA_94_196/Y3 + td + 0.287 + 8.061 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43_3/gateop_perm/Z + + + + net (fanout=11) + 0.438 + 8.499 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43 + + + CLMA_90_185/CECO + td + 0.184 + 8.683 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[8]/opit_0_inv_L5Q_perm/CEOUT + + + + net (fanout=4) + 0.000 + 8.683 + + ntR1851 + + + CLMA_90_193/CECO + td + 0.184 + 8.867 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[11]/opit_0_inv_L5Q_perm/CEOUT + + + + net (fanout=4) + 0.000 + 8.867 + + ntR1850 + + + CLMA_90_197/CECI + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[17]/opit_0_inv_L5Q_perm/CE + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_200m (rising edge) + + 5.000 + 5.000 + r + + + + P20 + + 0.000 + 5.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 5.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 6.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 6.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 6.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 7.688 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.096 + 7.784 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.059 + 8.843 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 8.843 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.531 + 10.374 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + CLMA_90_197/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[17]/opit_0_inv_L5Q_perm/CLK + + + clock pessimism + + 0.493 + 10.867 + + + + + clock uncertainty + + -0.150 + 10.717 + + + + + Setup time + + -0.729 + 9.988 + + + +
+
+
+
+ + 1.131 + 0 + 3 + u_zoom_image/mult_fra0_0/N2/gopapm/CLK + u_zoom_image/mult_image_g0_0/N2/gopapm/X[1] + + clk_1080p60Hz + clk_1080p60Hz + rise-rise + -0.177 + 9.563 + 8.835 + 0.551 + 6.736 + 3.035 + 1.067 (35.2%) + 1.968 (64.8%) + + Path #9: setup slack is 1.131(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_1080p60Hz (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.107 + 3.210 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.078 + 4.288 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 4.288 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.861 + 6.149 + + ntR3950 + + + PLL_158_303/CLK_OUT0 + td + 0.107 + 6.256 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=1) + 1.599 + 7.855 + + zoom_clk + + + USCM_84_118/CLK_USCM + td + 0.000 + 7.855 + r + clkbufg_3/gopclkbufg/CLKOUT + + + + net (fanout=750) + 1.708 + 9.563 + + ntclkbufg_3 + + + APM_206_264/CLK + + + + r + u_zoom_image/mult_fra0_0/N2/gopapm/CLK + + + APM_206_264/P[8] + tco + 1.067 + 10.630 + f + u_zoom_image/mult_fra0_0/N2/gopapm/P[8] + + + + net (fanout=3) + 1.968 + 12.598 + + u_zoom_image/coe_mult_p0_0 [8] + + + APM_206_128/X[1] + + + + f + u_zoom_image/mult_image_g0_0/N2/gopapm/X[1] + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_1080p60Hz (rising edge) + + 6.736 + 6.736 + r + + + + P20 + + 0.000 + 6.736 + r + clk (port) + + + + net (fanout=1) + 0.074 + 6.810 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 8.618 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 8.618 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 8.666 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 9.424 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.100 + 9.524 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.059 + 10.583 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 10.583 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.786 + 12.369 + + ntR3950 + + + PLL_158_303/CLK_OUT0 + td + 0.100 + 12.469 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=1) + 1.571 + 14.040 + + zoom_clk + + + USCM_84_118/CLK_USCM + td + 0.000 + 14.040 + r + clkbufg_3/gopclkbufg/CLKOUT + + + + net (fanout=750) + 1.531 + 15.571 + + ntclkbufg_3 + + + APM_206_128/CLK + + + + r + u_zoom_image/mult_image_g0_0/N2/gopapm/CLK + + + clock pessimism + + 0.551 + 16.122 + + + + + clock uncertainty + + -0.150 + 15.972 + + + + + Setup time + + -2.243 + 13.729 + + + +
+
+
+
+ + 1.692 + 0 + 8 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[0] + + ioclk1 + ioclk1 + rise-rise + 0.006 + 7.692 + 7.062 + 0.636 + 2.500 + 0.528 + 0.528 (100.0%) + 0.000 (0.0%) + + Path #10: setup slack is 1.692(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk1 (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.101 + 3.204 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.078 + 4.282 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 4.282 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.738 + 6.020 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.129 + 6.149 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.121 + 7.270 + + clkout0_wl_0 + + + IOCKGATE_6_188/OUT + td + 0.348 + 7.618 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT + + + + net (fanout=28) + 0.074 + 7.692 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + + + DQSL_6_152/CLK_IO + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + + + DQSL_6_152/IFIFO_RADDR[0] + tco + 0.528 + 8.220 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[0] + + + + net (fanout=8) + 0.000 + 8.220 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [0] + + + IOL_7_162/IFIFO_RADDR[0] + + + + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[0] + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk1 (rising edge) + + 2.500 + 2.500 + r + + + + P20 + + 0.000 + 2.500 + r + clk (port) + + + + net (fanout=1) + 0.074 + 2.574 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 4.382 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 4.382 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 4.430 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 5.188 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.096 + 5.284 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.059 + 6.343 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 6.343 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.665 + 8.008 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.123 + 8.131 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.102 + 9.233 + + clkout0_wl_0 + + + IOCKGATE_6_188/OUT + td + 0.249 + 9.482 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT + + + + net (fanout=28) + 0.080 + 9.562 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + + + IOL_7_162/CLK_IO + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK + + + clock pessimism + + 0.636 + 10.198 + + + + + clock uncertainty + + -0.150 + 10.048 + + + + + Setup time + + -0.136 + 9.912 + + + +
+
+
+
+ + 1.692 + 0 + 8 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[1] + + ioclk1 + ioclk1 + rise-rise + 0.006 + 7.692 + 7.062 + 0.636 + 2.500 + 0.528 + 0.528 (100.0%) + 0.000 (0.0%) + + Path #11: setup slack is 1.692(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk1 (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.101 + 3.204 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.078 + 4.282 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 4.282 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.738 + 6.020 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.129 + 6.149 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.121 + 7.270 + + clkout0_wl_0 + + + IOCKGATE_6_188/OUT + td + 0.348 + 7.618 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT + + + + net (fanout=28) + 0.074 + 7.692 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + + + DQSL_6_152/CLK_IO + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + + + DQSL_6_152/IFIFO_RADDR[1] + tco + 0.528 + 8.220 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[1] + + + + net (fanout=8) + 0.000 + 8.220 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [1] + + + IOL_7_162/IFIFO_RADDR[1] + + + + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[1] + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk1 (rising edge) + + 2.500 + 2.500 + r + + + + P20 + + 0.000 + 2.500 + r + clk (port) + + + + net (fanout=1) + 0.074 + 2.574 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 4.382 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 4.382 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 4.430 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 5.188 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.096 + 5.284 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.059 + 6.343 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 6.343 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.665 + 8.008 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.123 + 8.131 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.102 + 9.233 + + clkout0_wl_0 + + + IOCKGATE_6_188/OUT + td + 0.249 + 9.482 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT + + + + net (fanout=28) + 0.080 + 9.562 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + + + IOL_7_162/CLK_IO + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK + + + clock pessimism + + 0.636 + 10.198 + + + + + clock uncertainty + + -0.150 + 10.048 + + + + + Setup time + + -0.136 + 9.912 + + + +
+
+
+
+ + 1.692 + 0 + 8 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[2] + + ioclk1 + ioclk1 + rise-rise + 0.006 + 7.692 + 7.062 + 0.636 + 2.500 + 0.528 + 0.528 (100.0%) + 0.000 (0.0%) + + Path #12: setup slack is 1.692(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk1 (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.101 + 3.204 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.078 + 4.282 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 4.282 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.738 + 6.020 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.129 + 6.149 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.121 + 7.270 + + clkout0_wl_0 + + + IOCKGATE_6_188/OUT + td + 0.348 + 7.618 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT + + + + net (fanout=28) + 0.074 + 7.692 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + + + DQSL_6_152/CLK_IO + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + + + DQSL_6_152/IFIFO_RADDR[2] + tco + 0.528 + 8.220 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[2] + + + + net (fanout=8) + 0.000 + 8.220 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [2] + + + IOL_7_162/IFIFO_RADDR[2] + + + + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[2] + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk1 (rising edge) + + 2.500 + 2.500 + r + + + + P20 + + 0.000 + 2.500 + r + clk (port) + + + + net (fanout=1) + 0.074 + 2.574 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 4.382 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 4.382 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 4.430 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 5.188 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.096 + 5.284 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.059 + 6.343 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 6.343 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.665 + 8.008 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.123 + 8.131 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.102 + 9.233 + + clkout0_wl_0 + + + IOCKGATE_6_188/OUT + td + 0.249 + 9.482 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT + + + + net (fanout=28) + 0.080 + 9.562 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + + + IOL_7_162/CLK_IO + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK + + + clock pessimism + + 0.636 + 10.198 + + + + + clock uncertainty + + -0.150 + 10.048 + + + + + Setup time + + -0.136 + 9.912 + + + +
+
+
+
+ + 1.692 + 0 + 8 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[0] + + ioclk0 + ioclk0 + rise-rise + 0.006 + 7.692 + 7.062 + 0.636 + 2.500 + 0.528 + 0.528 (100.0%) + 0.000 (0.0%) + + Path #13: setup slack is 1.692(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk0 (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.101 + 3.204 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.078 + 4.282 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 4.282 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.738 + 6.020 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.129 + 6.149 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.121 + 7.270 + + clkout0_wl_0 + + + IOCKGATE_6_312/OUT + td + 0.348 + 7.618 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT + + + + net (fanout=11) + 0.074 + 7.692 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + + + DQSL_6_276/CLK_IO + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + + + DQSL_6_276/IFIFO_RADDR[0] + tco + 0.528 + 8.220 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[0] + + + + net (fanout=8) + 0.000 + 8.220 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [0] + + + IOL_7_285/IFIFO_RADDR[0] + + + + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[0] + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk0 (rising edge) + + 2.500 + 2.500 + r + + + + P20 + + 0.000 + 2.500 + r + clk (port) + + + + net (fanout=1) + 0.074 + 2.574 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 4.382 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 4.382 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 4.430 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 5.188 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.096 + 5.284 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.059 + 6.343 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 6.343 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.665 + 8.008 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.123 + 8.131 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.102 + 9.233 + + clkout0_wl_0 + + + IOCKGATE_6_312/OUT + td + 0.249 + 9.482 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT + + + + net (fanout=11) + 0.080 + 9.562 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + + + IOL_7_285/CLK_IO + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK + + + clock pessimism + + 0.636 + 10.198 + + + + + clock uncertainty + + -0.150 + 10.048 + + + + + Setup time + + -0.136 + 9.912 + + + +
+
+
+
+ + 1.692 + 0 + 8 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[1] + + ioclk0 + ioclk0 + rise-rise + 0.006 + 7.692 + 7.062 + 0.636 + 2.500 + 0.528 + 0.528 (100.0%) + 0.000 (0.0%) + + Path #14: setup slack is 1.692(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk0 (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.101 + 3.204 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.078 + 4.282 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 4.282 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.738 + 6.020 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.129 + 6.149 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.121 + 7.270 + + clkout0_wl_0 + + + IOCKGATE_6_312/OUT + td + 0.348 + 7.618 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT + + + + net (fanout=11) + 0.074 + 7.692 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + + + DQSL_6_276/CLK_IO + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + + + DQSL_6_276/IFIFO_RADDR[1] + tco + 0.528 + 8.220 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[1] + + + + net (fanout=8) + 0.000 + 8.220 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [1] + + + IOL_7_285/IFIFO_RADDR[1] + + + + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[1] + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk0 (rising edge) + + 2.500 + 2.500 + r + + + + P20 + + 0.000 + 2.500 + r + clk (port) + + + + net (fanout=1) + 0.074 + 2.574 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 4.382 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 4.382 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 4.430 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 5.188 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.096 + 5.284 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.059 + 6.343 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 6.343 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.665 + 8.008 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.123 + 8.131 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.102 + 9.233 + + clkout0_wl_0 + + + IOCKGATE_6_312/OUT + td + 0.249 + 9.482 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT + + + + net (fanout=11) + 0.080 + 9.562 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + + + IOL_7_285/CLK_IO + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK + + + clock pessimism + + 0.636 + 10.198 + + + + + clock uncertainty + + -0.150 + 10.048 + + + + + Setup time + + -0.136 + 9.912 + + + +
+
+
+
+ + 1.692 + 0 + 8 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[2] + + ioclk0 + ioclk0 + rise-rise + 0.006 + 7.692 + 7.062 + 0.636 + 2.500 + 0.528 + 0.528 (100.0%) + 0.000 (0.0%) + + Path #15: setup slack is 1.692(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk0 (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.101 + 3.204 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.078 + 4.282 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 4.282 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.738 + 6.020 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.129 + 6.149 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.121 + 7.270 + + clkout0_wl_0 + + + IOCKGATE_6_312/OUT + td + 0.348 + 7.618 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT + + + + net (fanout=11) + 0.074 + 7.692 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + + + DQSL_6_276/CLK_IO + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + + + DQSL_6_276/IFIFO_RADDR[2] + tco + 0.528 + 8.220 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[2] + + + + net (fanout=8) + 0.000 + 8.220 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [2] + + + IOL_7_285/IFIFO_RADDR[2] + + + + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[2] + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk0 (rising edge) + + 2.500 + 2.500 + r + + + + P20 + + 0.000 + 2.500 + r + clk (port) + + + + net (fanout=1) + 0.074 + 2.574 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 4.382 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 4.382 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 4.430 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 5.188 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.096 + 5.284 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.059 + 6.343 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 6.343 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.665 + 8.008 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.123 + 8.131 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.102 + 9.233 + + clkout0_wl_0 + + + IOCKGATE_6_312/OUT + td + 0.249 + 9.482 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT + + + + net (fanout=11) + 0.080 + 9.562 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + + + IOL_7_285/CLK_IO + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK + + + clock pessimism + + 0.636 + 10.198 + + + + + clock uncertainty + + -0.150 + 10.048 + + + + + Setup time + + -0.136 + 9.912 + + + +
+
+
+
+ + 1.839 + 5 + 4 + u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L4 + + hdmi_in_clk + hdmi_in_clk + rise-rise + -0.036 + 6.435 + 5.951 + 0.448 + 6.666 + 4.418 + 2.352 (53.2%) + 2.066 (46.8%) + + Path #16: setup slack is 1.839(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock hdmi_in_clk (rising edge) + + 0.000 + 0.000 + r + + + + AA12 + + 0.000 + 0.000 + r + hdmi_in_clk (port) + + + + net (fanout=1) + 0.078 + 0.078 + + hdmi_in_clk + + + IOBD_161_0/DIN + td + 2.166 + 2.244 + r + hdmi_in_clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.244 + + hdmi_in_clk_ibuf/ntD + + + IOL_163_6/INCK + td + 0.076 + 2.320 + r + hdmi_in_clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 2.530 + 4.850 + + _N37 + + + USCM_84_111/CLK_USCM + td + 0.000 + 4.850 + r + clkbufg_5/gopclkbufg/CLKOUT + + + + net (fanout=167) + 1.585 + 6.435 + + ntclkbufg_5 + + + CLMA_110_85/CLK + + + + r + u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK + + + CLMA_110_85/Q0 + tco + 0.289 + 6.724 + r + u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/Q + + + + net (fanout=4) + 0.769 + 7.493 + + wr1_data_in_valid + + + + td + 0.288 + 7.781 + f + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Cout + + + + net (fanout=1) + 0.000 + 7.781 + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15959 + + + CLMA_90_101/COUT + td + 0.058 + 7.839 + r + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/Cout + + + + net (fanout=1) + 0.000 + 7.839 + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15961 + + + CLMA_90_105/Y1 + td + 0.498 + 8.337 + r + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/Y1 + + + + net (fanout=3) + 0.658 + 8.995 + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2 [5] + + + CLMS_74_105/Y3 + td + 0.210 + 9.205 + r + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[5]_1/gateop_perm/Z + + + + net (fanout=1) + 0.517 + 9.722 + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N109251 + + + CLMA_90_100/COUT + td + 0.511 + 10.233 + r + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_2/gateop_A2/Cout + + + + net (fanout=1) + 0.000 + 10.233 + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.co [6] + + + CLMA_90_104/Y1 + td + 0.498 + 10.731 + r + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_4/gateop_A2/Y1 + + + + net (fanout=1) + 0.122 + 10.853 + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158 + + + CLMA_90_104/C4 + + + + r + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L4 + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock hdmi_in_clk (rising edge) + + 6.666 + 6.666 + r + + + + AA12 + + 0.000 + 6.666 + r + hdmi_in_clk (port) + + + + net (fanout=1) + 0.078 + 6.744 + + hdmi_in_clk + + + IOBD_161_0/DIN + td + 1.808 + 8.552 + r + hdmi_in_clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 8.552 + + hdmi_in_clk_ibuf/ntD + + + IOL_163_6/INCK + td + 0.048 + 8.600 + r + hdmi_in_clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 2.486 + 11.086 + + _N37 + + + USCM_84_111/CLK_USCM + td + 0.000 + 11.086 + r + clkbufg_5/gopclkbufg/CLKOUT + + + + net (fanout=167) + 1.531 + 12.617 + + ntclkbufg_5 + + + CLMA_90_104/CLK + + + + r + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK + + + clock pessimism + + 0.448 + 13.065 + + + + + clock uncertainty + + -0.250 + 12.815 + + + + + Setup time + + -0.123 + 12.692 + + + +
+
+
+
+ + 2.472 + 7 + 40 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/S0 + + ddrphy_clkin + ddrphy_clkin + rise-rise + -0.036 + 11.394 + 10.665 + 0.693 + 10.000 + 6.944 + 3.399 (48.9%) + 3.545 (51.1%) + + Path #17: setup slack is 2.472(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ddrphy_clkin (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.101 + 3.204 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.078 + 4.282 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 4.282 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.738 + 6.020 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.129 + 6.149 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.121 + 7.270 + + clkout0_wl_0 + + + IOCKGATE_6_322/OUT + td + 0.348 + 7.618 + r + clkgate_9/gopclkgate/OUT + + + + net (fanout=1) + 0.000 + 7.618 + + ntclkgate_0 + + + IOCKDIV_6_323/CLK_IODIV + td + 0.000 + 7.618 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + + + + net (fanout=1) + 2.191 + 9.809 + + u_axi_ddr_top/clk + + + USCM_84_116/CLK_USCM + td + 0.000 + 9.809 + r + clkbufg_0/gopclkbufg/CLKOUT + + + + net (fanout=5464) + 1.585 + 11.394 + + ntclkbufg_0 + + + CLMS_10_133/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK + + + CLMS_10_133/Q2 + tco + 0.290 + 11.684 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/Q + + + + net (fanout=5) + 0.687 + 12.371 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mr0_ddr3 [2] + + + CLMS_18_149/Y1 + td + 0.288 + 12.659 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/gateop_perm/Z + + + + net (fanout=2) + 0.402 + 13.061 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_cl [1] + + + + td + 0.477 + 13.538 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_1/gateop_A2/Cout + + + + net (fanout=1) + 0.000 + 13.538 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.co [2] + + + CLMS_18_145/Y3 + td + 0.501 + 14.039 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_3/gateop_A2/Y1 + + + + net (fanout=1) + 0.661 + 14.700 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [3] + + + CLMS_46_145/Y1 + td + 0.304 + 15.004 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[3]/gateop_perm/Z + + + + net (fanout=4) + 0.406 + 15.410 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al [3] + + + CLMA_50_144/COUT + td + 0.507 + 15.917 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_3/gateop_A2/Cout + + + + net (fanout=1) + 0.000 + 15.917 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14534 + + + CLMA_50_148/Y0 + td + 0.269 + 16.186 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_5/gateop/Y + + + + net (fanout=4) + 0.267 + 16.453 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mc_rl [4] + + + CLMS_46_149/Y0 + td + 0.285 + 16.738 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_159_5/gateop_perm/Z + + + + net (fanout=40) + 0.720 + 17.458 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23975 + + + CLMA_62_164/Y2 + td + 0.478 + 17.936 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_170[12]/gateop/F + + + + net (fanout=1) + 0.402 + 18.338 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24148 + + + CLMA_58_161/C3 + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/S0 + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ddrphy_clkin (rising edge) + + 10.000 + 10.000 + r + + + + P20 + + 0.000 + 10.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 10.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 11.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 11.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 11.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 12.688 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.096 + 12.784 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.059 + 13.843 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 13.843 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.665 + 15.508 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.123 + 15.631 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.102 + 16.733 + + clkout0_wl_0 + + + IOCKGATE_6_322/OUT + td + 0.249 + 16.982 + r + clkgate_9/gopclkgate/OUT + + + + net (fanout=1) + 0.000 + 16.982 + + ntclkgate_0 + + + IOCKDIV_6_323/CLK_IODIV + td + 0.000 + 16.982 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + + + + net (fanout=1) + 2.152 + 19.134 + + u_axi_ddr_top/clk + + + USCM_84_116/CLK_USCM + td + 0.000 + 19.134 + r + clkbufg_0/gopclkbufg/CLKOUT + + + + net (fanout=5464) + 1.531 + 20.665 + + ntclkbufg_0 + + + CLMA_58_161/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/CLK + + + clock pessimism + + 0.693 + 21.358 + + + + + clock uncertainty + + -0.150 + 21.208 + + + + + Setup time + + -0.398 + 20.810 + + + +
+
+
+
+ + 2.514 + 7 + 56 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[3]/opit_0_inv_MUX4TO1Q/I2 + + ddrphy_clkin + ddrphy_clkin + rise-rise + -0.036 + 11.394 + 10.665 + 0.693 + 10.000 + 6.909 + 3.131 (45.3%) + 3.778 (54.7%) + + Path #18: setup slack is 2.514(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ddrphy_clkin (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.101 + 3.204 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.078 + 4.282 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 4.282 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.738 + 6.020 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.129 + 6.149 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.121 + 7.270 + + clkout0_wl_0 + + + IOCKGATE_6_322/OUT + td + 0.348 + 7.618 + r + clkgate_9/gopclkgate/OUT + + + + net (fanout=1) + 0.000 + 7.618 + + ntclkgate_0 + + + IOCKDIV_6_323/CLK_IODIV + td + 0.000 + 7.618 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + + + + net (fanout=1) + 2.191 + 9.809 + + u_axi_ddr_top/clk + + + USCM_84_116/CLK_USCM + td + 0.000 + 9.809 + r + clkbufg_0/gopclkbufg/CLKOUT + + + + net (fanout=5464) + 1.585 + 11.394 + + ntclkbufg_0 + + + CLMS_10_133/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK + + + CLMS_10_133/Q2 + tco + 0.290 + 11.684 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/Q + + + + net (fanout=5) + 0.687 + 12.371 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mr0_ddr3 [2] + + + CLMS_18_149/Y1 + td + 0.288 + 12.659 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/gateop_perm/Z + + + + net (fanout=2) + 0.402 + 13.061 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_cl [1] + + + + td + 0.477 + 13.538 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_1/gateop_A2/Cout + + + + net (fanout=1) + 0.000 + 13.538 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.co [2] + + + CLMS_18_145/Y3 + td + 0.501 + 14.039 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_3/gateop_A2/Y1 + + + + net (fanout=1) + 0.661 + 14.700 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [3] + + + CLMS_46_145/Y1 + td + 0.304 + 15.004 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[3]/gateop_perm/Z + + + + net (fanout=4) + 0.406 + 15.410 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al [3] + + + CLMA_50_144/COUT + td + 0.507 + 15.917 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_3/gateop_A2/Cout + + + + net (fanout=1) + 0.000 + 15.917 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14534 + + + CLMA_50_148/Y0 + td + 0.269 + 16.186 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_5/gateop/Y + + + + net (fanout=4) + 0.406 + 16.592 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mc_rl [4] + + + CLMS_46_145/Y0 + td + 0.285 + 16.877 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_198_5/gateop_perm/Z + + + + net (fanout=56) + 0.635 + 17.512 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23906 + + + CLMS_50_157/Y2 + td + 0.210 + 17.722 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[15]/gateop_perm/Z + + + + net (fanout=1) + 0.581 + 18.303 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23991 + + + CLMA_58_156/C2 + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[3]/opit_0_inv_MUX4TO1Q/I2 + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ddrphy_clkin (rising edge) + + 10.000 + 10.000 + r + + + + P20 + + 0.000 + 10.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 10.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 11.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 11.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 11.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 12.688 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.096 + 12.784 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.059 + 13.843 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 13.843 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.665 + 15.508 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.123 + 15.631 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.102 + 16.733 + + clkout0_wl_0 + + + IOCKGATE_6_322/OUT + td + 0.249 + 16.982 + r + clkgate_9/gopclkgate/OUT + + + + net (fanout=1) + 0.000 + 16.982 + + ntclkgate_0 + + + IOCKDIV_6_323/CLK_IODIV + td + 0.000 + 16.982 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + + + + net (fanout=1) + 2.152 + 19.134 + + u_axi_ddr_top/clk + + + USCM_84_116/CLK_USCM + td + 0.000 + 19.134 + r + clkbufg_0/gopclkbufg/CLKOUT + + + + net (fanout=5464) + 1.531 + 20.665 + + ntclkbufg_0 + + + CLMA_58_156/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[3]/opit_0_inv_MUX4TO1Q/CLK + + + clock pessimism + + 0.693 + 21.358 + + + + + clock uncertainty + + -0.150 + 21.208 + + + + + Setup time + + -0.391 + 20.817 + + + +
+
+
+
+ + 2.527 + 7 + 56 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/I2 + + ddrphy_clkin + ddrphy_clkin + rise-rise + -0.036 + 11.394 + 10.665 + 0.693 + 10.000 + 6.899 + 3.140 (45.5%) + 3.759 (54.5%) + + Path #19: setup slack is 2.527(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ddrphy_clkin (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.101 + 3.204 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.078 + 4.282 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 4.282 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.738 + 6.020 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.129 + 6.149 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.121 + 7.270 + + clkout0_wl_0 + + + IOCKGATE_6_322/OUT + td + 0.348 + 7.618 + r + clkgate_9/gopclkgate/OUT + + + + net (fanout=1) + 0.000 + 7.618 + + ntclkgate_0 + + + IOCKDIV_6_323/CLK_IODIV + td + 0.000 + 7.618 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + + + + net (fanout=1) + 2.191 + 9.809 + + u_axi_ddr_top/clk + + + USCM_84_116/CLK_USCM + td + 0.000 + 9.809 + r + clkbufg_0/gopclkbufg/CLKOUT + + + + net (fanout=5464) + 1.585 + 11.394 + + ntclkbufg_0 + + + CLMS_10_133/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK + + + CLMS_10_133/Q2 + tco + 0.290 + 11.684 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/Q + + + + net (fanout=5) + 0.687 + 12.371 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mr0_ddr3 [2] + + + CLMS_18_149/Y1 + td + 0.288 + 12.659 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/gateop_perm/Z + + + + net (fanout=2) + 0.402 + 13.061 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_cl [1] + + + + td + 0.477 + 13.538 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_1/gateop_A2/Cout + + + + net (fanout=1) + 0.000 + 13.538 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.co [2] + + + CLMS_18_145/Y3 + td + 0.501 + 14.039 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_3/gateop_A2/Y1 + + + + net (fanout=1) + 0.661 + 14.700 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [3] + + + CLMS_46_145/Y1 + td + 0.304 + 15.004 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[3]/gateop_perm/Z + + + + net (fanout=4) + 0.406 + 15.410 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al [3] + + + CLMA_50_144/COUT + td + 0.507 + 15.917 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_3/gateop_A2/Cout + + + + net (fanout=1) + 0.000 + 15.917 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14534 + + + CLMA_50_148/Y0 + td + 0.269 + 16.186 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_5/gateop/Y + + + + net (fanout=4) + 0.406 + 16.592 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mc_rl [4] + + + CLMS_46_145/Y0 + td + 0.294 + 16.886 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_198_5/gateop_perm/Z + + + + net (fanout=56) + 0.643 + 17.529 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23906 + + + CLMA_62_160/Y3 + td + 0.210 + 17.739 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[14]/gateop_perm/Z + + + + net (fanout=1) + 0.554 + 18.293 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23990 + + + CLMA_58_161/A2 + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/I2 + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ddrphy_clkin (rising edge) + + 10.000 + 10.000 + r + + + + P20 + + 0.000 + 10.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 10.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 11.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 11.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 11.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 12.688 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.096 + 12.784 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.059 + 13.843 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 13.843 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.665 + 15.508 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.123 + 15.631 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.102 + 16.733 + + clkout0_wl_0 + + + IOCKGATE_6_322/OUT + td + 0.249 + 16.982 + r + clkgate_9/gopclkgate/OUT + + + + net (fanout=1) + 0.000 + 16.982 + + ntclkgate_0 + + + IOCKDIV_6_323/CLK_IODIV + td + 0.000 + 16.982 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + + + + net (fanout=1) + 2.152 + 19.134 + + u_axi_ddr_top/clk + + + USCM_84_116/CLK_USCM + td + 0.000 + 19.134 + r + clkbufg_0/gopclkbufg/CLKOUT + + + + net (fanout=5464) + 1.531 + 20.665 + + ntclkbufg_0 + + + CLMA_58_161/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/CLK + + + clock pessimism + + 0.693 + 21.358 + + + + + clock uncertainty + + -0.150 + 21.208 + + + + + Setup time + + -0.388 + 20.820 + + + +
+
+
+
+ + 3.545 + 2 + 4 + u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/L2 + + hdmi_in_clk + hdmi_in_clk + rise-rise + -0.036 + 6.435 + 5.951 + 0.448 + 6.666 + 2.467 + 0.964 (39.1%) + 1.503 (60.9%) + + Path #20: setup slack is 3.545(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock hdmi_in_clk (rising edge) + + 0.000 + 0.000 + r + + + + AA12 + + 0.000 + 0.000 + r + hdmi_in_clk (port) + + + + net (fanout=1) + 0.078 + 0.078 + + hdmi_in_clk + + + IOBD_161_0/DIN + td + 2.166 + 2.244 + r + hdmi_in_clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.244 + + hdmi_in_clk_ibuf/ntD + + + IOL_163_6/INCK + td + 0.076 + 2.320 + r + hdmi_in_clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 2.530 + 4.850 + + _N37 + + + USCM_84_111/CLK_USCM + td + 0.000 + 4.850 + r + clkbufg_5/gopclkbufg/CLKOUT + + + + net (fanout=167) + 1.585 + 6.435 + + ntclkbufg_5 + + + CLMA_110_85/CLK + + + + r + u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK + + + CLMA_110_85/Q0 + tco + 0.289 + 6.724 + r + u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/Q + + + + net (fanout=4) + 0.769 + 7.493 + + wr1_data_in_valid + + + + td + 0.288 + 7.781 + f + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Cout + + + + net (fanout=1) + 0.000 + 7.781 + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15959 + + + CLMA_90_101/COUT + td + 0.058 + 7.839 + r + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/Cout + + + + net (fanout=1) + 0.000 + 7.839 + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15961 + + + + td + 0.058 + 7.897 + r + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/Cout + + + + net (fanout=1) + 0.000 + 7.897 + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15963 + + + CLMA_90_105/Y2 + td + 0.271 + 8.168 + r + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/Y0 + + + + net (fanout=3) + 0.734 + 8.902 + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2 [6] + + + CLMA_90_104/D2 + + + + r + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/L2 + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock hdmi_in_clk (rising edge) + + 6.666 + 6.666 + r + + + + AA12 + + 0.000 + 6.666 + r + hdmi_in_clk (port) + + + + net (fanout=1) + 0.078 + 6.744 + + hdmi_in_clk + + + IOBD_161_0/DIN + td + 1.808 + 8.552 + r + hdmi_in_clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 8.552 + + hdmi_in_clk_ibuf/ntD + + + IOL_163_6/INCK + td + 0.048 + 8.600 + r + hdmi_in_clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 2.486 + 11.086 + + _N37 + + + USCM_84_111/CLK_USCM + td + 0.000 + 11.086 + r + clkbufg_5/gopclkbufg/CLKOUT + + + + net (fanout=167) + 1.531 + 12.617 + + ntclkbufg_5 + + + CLMA_90_104/CLK + + + + r + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK + + + clock pessimism + + 0.448 + 13.065 + + + + + clock uncertainty + + -0.250 + 12.815 + + + + + Setup time + + -0.368 + 12.447 + + + +
+
+
+
+ + 3.657 + 3 + 4 + u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L1 + + hdmi_in_clk + hdmi_in_clk + rise-rise + -0.036 + 6.435 + 5.951 + 0.448 + 6.666 + 2.489 + 1.310 (52.6%) + 1.179 (47.4%) + + Path #21: setup slack is 3.657(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock hdmi_in_clk (rising edge) + + 0.000 + 0.000 + r + + + + AA12 + + 0.000 + 0.000 + r + hdmi_in_clk (port) + + + + net (fanout=1) + 0.078 + 0.078 + + hdmi_in_clk + + + IOBD_161_0/DIN + td + 2.166 + 2.244 + r + hdmi_in_clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.244 + + hdmi_in_clk_ibuf/ntD + + + IOL_163_6/INCK + td + 0.076 + 2.320 + r + hdmi_in_clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 2.530 + 4.850 + + _N37 + + + USCM_84_111/CLK_USCM + td + 0.000 + 4.850 + r + clkbufg_5/gopclkbufg/CLKOUT + + + + net (fanout=167) + 1.585 + 6.435 + + ntclkbufg_5 + + + CLMA_110_85/CLK + + + + r + u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK + + + CLMA_110_85/Q0 + tco + 0.289 + 6.724 + r + u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/Q + + + + net (fanout=4) + 0.769 + 7.493 + + wr1_data_in_valid + + + + td + 0.288 + 7.781 + f + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Cout + + + + net (fanout=1) + 0.000 + 7.781 + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15959 + + + CLMA_90_101/COUT + td + 0.058 + 7.839 + r + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/Cout + + + + net (fanout=1) + 0.000 + 7.839 + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15961 + + + + td + 0.058 + 7.897 + r + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/Cout + + + + net (fanout=1) + 0.000 + 7.897 + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15963 + + + CLMA_90_105/COUT + td + 0.058 + 7.955 + r + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/Cout + + + + net (fanout=1) + 0.000 + 7.955 + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15965 + + + + td + 0.058 + 8.013 + r + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/Cout + + + + net (fanout=1) + 0.000 + 8.013 + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15967 + + + CLMA_90_109/Y3 + td + 0.501 + 8.514 + r + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_A2Q21/Y1 + + + + net (fanout=3) + 0.410 + 8.924 + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2 [11] + + + CLMA_90_104/C1 + + + + r + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L1 + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock hdmi_in_clk (rising edge) + + 6.666 + 6.666 + r + + + + AA12 + + 0.000 + 6.666 + r + hdmi_in_clk (port) + + + + net (fanout=1) + 0.078 + 6.744 + + hdmi_in_clk + + + IOBD_161_0/DIN + td + 1.808 + 8.552 + r + hdmi_in_clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 8.552 + + hdmi_in_clk_ibuf/ntD + + + IOL_163_6/INCK + td + 0.048 + 8.600 + r + hdmi_in_clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 2.486 + 11.086 + + _N37 + + + USCM_84_111/CLK_USCM + td + 0.000 + 11.086 + r + clkbufg_5/gopclkbufg/CLKOUT + + + + net (fanout=167) + 1.531 + 12.617 + + ntclkbufg_5 + + + CLMA_90_104/CLK + + + + r + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK + + + clock pessimism + + 0.448 + 13.065 + + + + + clock uncertainty + + -0.250 + 12.815 + + + + + Setup time + + -0.234 + 12.581 + + + +
+
+
+
+ + 4.347 + 2 + 1 + cmos2_data[6] + u_ov5640/cmos2_d_d0[6]/opit_0/D + + cmos2_pclk + cmos2_pclk + rise-rise + 5.548 + 0.000 + 5.548 + 0.000 + 11.900 + 11.763 + 1.640 (13.9%) + 10.123 (86.1%) + + Path #22: setup slack is 4.347(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock cmos2_pclk (rising edge) + + 0.000 + 0.000 + r + + + + Input external delay + + 1.000 + 1.000 + f + + + + Y9 + + 0.000 + 1.000 + f + cmos2_data[6] (port) + + + + net (fanout=1) + 0.078 + 1.078 + + cmos2_data[6] + + + IOBD_129_0/DIN + td + 1.513 + 2.591 + f + cmos2_data_ibuf[6]/opit_0/O + + + + net (fanout=1) + 0.000 + 2.591 + + cmos2_data_ibuf[6]/ntD + + + IOL_131_6/RX_DATA_DD + td + 0.127 + 2.718 + f + cmos2_data_ibuf[6]/opit_1/OUT + + + + net (fanout=1) + 10.045 + 12.763 + + nt_cmos2_data[6] + + + CLMA_138_8/M1 + + + + f + u_ov5640/cmos2_d_d0[6]/opit_0/D + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock cmos2_pclk (rising edge) + + 11.900 + 11.900 + r + + + + W6 + + 0.000 + 11.900 + r + cmos2_pclk (port) + + + + net (fanout=1) + 0.071 + 11.971 + + cmos2_pclk + + + IOBD_37_0/DIN + td + 1.047 + 13.018 + r + cmos2_pclk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 13.018 + + cmos2_pclk_ibuf/ntD + + + IOL_39_6/RX_DATA_DD + td + 0.082 + 13.100 + r + cmos2_pclk_ibuf/opit_1/OUT + + + + net (fanout=1) + 2.817 + 15.917 + + nt_cmos2_pclk + + + USCM_84_119/CLK_USCM + td + 0.000 + 15.917 + r + clkbufg_7/gopclkbufg/CLKOUT + + + + net (fanout=118) + 1.531 + 17.448 + + ntclkbufg_7 + + + CLMA_138_8/CLK + + + + r + u_ov5640/cmos2_d_d0[6]/opit_0/CLK + + + clock pessimism + + 0.000 + 17.448 + + + + + clock uncertainty + + -0.250 + 17.198 + + + + + Setup time + + -0.088 + 17.110 + + + +
+
+
+
+ + 4.366 + 3 + 1 + cmos2_data[5] + u_ov5640/cmos2_d_d0[5]/opit_0/D + + cmos2_pclk + cmos2_pclk + rise-rise + 5.548 + 0.000 + 5.548 + 0.000 + 11.900 + 11.744 + 1.774 (15.1%) + 9.970 (84.9%) + + Path #23: setup slack is 4.366(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock cmos2_pclk (rising edge) + + 0.000 + 0.000 + r + + + + Input external delay + + 1.000 + 1.000 + f + + + + AB8 + + 0.000 + 1.000 + f + cmos2_data[5] (port) + + + + net (fanout=1) + 0.084 + 1.084 + + cmos2_data[5] + + + IOBS_TB_116_0/DIN + td + 1.513 + 2.597 + f + cmos2_data_ibuf[5]/opit_0/O + + + + net (fanout=1) + 0.000 + 2.597 + + cmos2_data_ibuf[5]/ntD + + + IOL_119_5/RX_DATA_DD + td + 0.127 + 2.724 + f + cmos2_data_ibuf[5]/opit_1/OUT + + + + net (fanout=1) + 1.531 + 4.255 + + nt_cmos2_data[5] + + + CLMS_198_49/Y6CD + td + 0.134 + 4.389 + f + CLKROUTE_0/Z + + + + net (fanout=1) + 8.355 + 12.744 + + ntR3940 + + + CLMA_138_8/M0 + + + + f + u_ov5640/cmos2_d_d0[5]/opit_0/D + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock cmos2_pclk (rising edge) + + 11.900 + 11.900 + r + + + + W6 + + 0.000 + 11.900 + r + cmos2_pclk (port) + + + + net (fanout=1) + 0.071 + 11.971 + + cmos2_pclk + + + IOBD_37_0/DIN + td + 1.047 + 13.018 + r + cmos2_pclk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 13.018 + + cmos2_pclk_ibuf/ntD + + + IOL_39_6/RX_DATA_DD + td + 0.082 + 13.100 + r + cmos2_pclk_ibuf/opit_1/OUT + + + + net (fanout=1) + 2.817 + 15.917 + + nt_cmos2_pclk + + + USCM_84_119/CLK_USCM + td + 0.000 + 15.917 + r + clkbufg_7/gopclkbufg/CLKOUT + + + + net (fanout=118) + 1.531 + 17.448 + + ntclkbufg_7 + + + CLMA_138_8/CLK + + + + r + u_ov5640/cmos2_d_d0[5]/opit_0/CLK + + + clock pessimism + + 0.000 + 17.448 + + + + + clock uncertainty + + -0.250 + 17.198 + + + + + Setup time + + -0.088 + 17.110 + + + +
+
+
+
+ + 4.403 + 4 + 1 + cmos2_href + u_ov5640/cmos2_href_d0/opit_0/D + + cmos2_pclk + cmos2_pclk + rise-rise + 5.595 + 0.000 + 5.595 + 0.000 + 11.900 + 11.871 + 1.760 (14.8%) + 10.111 (85.2%) + + Path #24: setup slack is 4.403(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock cmos2_pclk (rising edge) + + 0.000 + 0.000 + r + + + + Input external delay + + 1.000 + 1.000 + f + + + + AB5 + + 0.000 + 1.000 + f + cmos2_href (port) + + + + net (fanout=1) + 0.093 + 1.093 + + cmos2_href + + + IOBS_TB_32_0/DIN + td + 1.367 + 2.460 + f + cmos2_href_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.460 + + cmos2_href_ibuf/ntD + + + IOL_35_5/RX_DATA_DD + td + 0.127 + 2.587 + f + cmos2_href_ibuf/opit_1/OUT + + + + net (fanout=1) + 0.780 + 3.367 + + nt_cmos2_href + + + CLMA_18_12/Y6AB + td + 0.132 + 3.499 + f + CLKROUTE_2/Z + + + + net (fanout=1) + 4.461 + 7.960 + + ntR3942 + + + CLMA_18_80/Y6CD + td + 0.134 + 8.094 + f + CLKROUTE_1/Z + + + + net (fanout=1) + 4.777 + 12.871 + + ntR3941 + + + CLMS_78_21/CD + + + + f + u_ov5640/cmos2_href_d0/opit_0/D + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock cmos2_pclk (rising edge) + + 11.900 + 11.900 + r + + + + W6 + + 0.000 + 11.900 + r + cmos2_pclk (port) + + + + net (fanout=1) + 0.071 + 11.971 + + cmos2_pclk + + + IOBD_37_0/DIN + td + 1.047 + 13.018 + r + cmos2_pclk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 13.018 + + cmos2_pclk_ibuf/ntD + + + IOL_39_6/RX_DATA_DD + td + 0.082 + 13.100 + r + cmos2_pclk_ibuf/opit_1/OUT + + + + net (fanout=1) + 2.817 + 15.917 + + nt_cmos2_pclk + + + USCM_84_119/CLK_USCM + td + 0.000 + 15.917 + r + clkbufg_7/gopclkbufg/CLKOUT + + + + net (fanout=118) + 1.578 + 17.495 + + ntclkbufg_7 + + + CLMS_78_21/CLK + + + + r + u_ov5640/cmos2_href_d0/opit_0/CLK + + + clock pessimism + + 0.000 + 17.495 + + + + + clock uncertainty + + -0.250 + 17.245 + + + + + Setup time + + 0.029 + 17.274 + + + +
+
+
+
+ + 5.305 + 2 + 1 + cmos1_href + u_ov5640/cmos1_href_d0/opit_0/D + + cmos1_pclk + cmos1_pclk + rise-rise + 5.188 + 0.000 + 5.188 + 0.000 + 11.900 + 10.445 + 1.494 (14.3%) + 8.951 (85.7%) + + Path #25: setup slack is 5.305(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock cmos1_pclk (rising edge) + + 0.000 + 0.000 + r + + + + Input external delay + + 1.000 + 1.000 + f + + + + AB10 + + 0.000 + 1.000 + f + cmos1_href (port) + + + + net (fanout=1) + 0.063 + 1.063 + + cmos1_href + + + IOBR_TB_148_0/DIN + td + 1.367 + 2.430 + f + cmos1_href_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.430 + + cmos1_href_ibuf/ntD + + + IOL_151_5/RX_DATA_DD + td + 0.127 + 2.557 + f + cmos1_href_ibuf/opit_1/OUT + + + + net (fanout=1) + 8.888 + 11.445 + + nt_cmos1_href + + + CLMA_150_12/M1 + + + + f + u_ov5640/cmos1_href_d0/opit_0/D + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock cmos1_pclk (rising edge) + + 11.900 + 11.900 + r + + + + T12 + + 0.000 + 11.900 + r + cmos1_pclk (port) + + + + net (fanout=1) + 0.076 + 11.976 + + cmos1_pclk + + + IOBD_169_0/DIN + td + 1.047 + 13.023 + r + cmos1_pclk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 13.023 + + cmos1_pclk_ibuf/ntD + + + IOL_171_6/INCK + td + 0.048 + 13.071 + r + cmos1_pclk_ibuf/opit_1/INCK + + + + net (fanout=1) + 2.486 + 15.557 + + _N64 + + + USCM_84_112/CLK_USCM + td + 0.000 + 15.557 + r + clkbufg_6/gopclkbufg/CLKOUT + + + + net (fanout=118) + 1.531 + 17.088 + + ntclkbufg_6 + + + CLMA_150_12/CLK + + + + r + u_ov5640/cmos1_href_d0/opit_0/CLK + + + clock pessimism + + 0.000 + 17.088 + + + + + clock uncertainty + + -0.250 + 16.838 + + + + + Setup time + + -0.088 + 16.750 + + + +
+
+
+
+ + 5.924 + 2 + 1 + cmos1_data[6] + u_ov5640/cmos1_d_d0[6]/opit_0/D + + cmos1_pclk + cmos1_pclk + rise-rise + 5.188 + 0.000 + 5.188 + 0.000 + 11.900 + 9.835 + 2.292 (23.3%) + 7.543 (76.7%) + + Path #26: setup slack is 5.924(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock cmos1_pclk (rising edge) + + 0.000 + 0.000 + r + + + + Input external delay + + 1.000 + 1.000 + r + + + + AA10 + + 0.000 + 1.000 + r + cmos1_data[6] (port) + + + + net (fanout=1) + 0.080 + 1.080 + + cmos1_data[6] + + + IOBD_149_0/DIN + td + 2.166 + 3.246 + r + cmos1_data_ibuf[6]/opit_0/O + + + + net (fanout=1) + 0.000 + 3.246 + + cmos1_data_ibuf[6]/ntD + + + IOL_151_6/RX_DATA_DD + td + 0.126 + 3.372 + r + cmos1_data_ibuf[6]/opit_1/OUT + + + + net (fanout=1) + 7.463 + 10.835 + + nt_cmos1_data[6] + + + CLMS_150_41/M1 + + + + r + u_ov5640/cmos1_d_d0[6]/opit_0/D + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock cmos1_pclk (rising edge) + + 11.900 + 11.900 + r + + + + T12 + + 0.000 + 11.900 + r + cmos1_pclk (port) + + + + net (fanout=1) + 0.076 + 11.976 + + cmos1_pclk + + + IOBD_169_0/DIN + td + 1.047 + 13.023 + r + cmos1_pclk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 13.023 + + cmos1_pclk_ibuf/ntD + + + IOL_171_6/INCK + td + 0.048 + 13.071 + r + cmos1_pclk_ibuf/opit_1/INCK + + + + net (fanout=1) + 2.486 + 15.557 + + _N64 + + + USCM_84_112/CLK_USCM + td + 0.000 + 15.557 + r + clkbufg_6/gopclkbufg/CLKOUT + + + + net (fanout=118) + 1.531 + 17.088 + + ntclkbufg_6 + + + CLMS_150_41/CLK + + + + r + u_ov5640/cmos1_d_d0[6]/opit_0/CLK + + + clock pessimism + + 0.000 + 17.088 + + + + + clock uncertainty + + -0.250 + 16.838 + + + + + Setup time + + -0.079 + 16.759 + + + +
+
+
+
+ + 5.988 + 7 + 15 + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/rd_cnt[5]/opit_0_A2Q21/CLK + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0_A2Q1/Cin + + clk_720p60Hz + clk_720p60Hz + rise-rise + -0.036 + 9.557 + 8.952 + 0.569 + 13.473 + 6.942 + 3.294 (47.5%) + 3.648 (52.5%) + + Path #27: setup slack is 5.988(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_720p60Hz (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.107 + 3.210 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.078 + 4.288 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 4.288 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.861 + 6.149 + + ntR3950 + + + PLL_158_303/CLK_OUT1 + td + 0.101 + 6.250 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.599 + 7.849 + + nt_pix_clk + + + USCM_84_117/CLK_USCM + td + 0.000 + 7.849 + r + clkbufg_2/gopclkbufg/CLKOUT + + + + net (fanout=1635) + 1.708 + 9.557 + + ntclkbufg_2 + + + CLMA_214_292/CLK + + + + r + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/rd_cnt[5]/opit_0_A2Q21/CLK + + + CLMA_214_292/Q1 + tco + 0.291 + 9.848 + r + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/rd_cnt[5]/opit_0_A2Q21/Q1 + + + + net (fanout=3) + 0.549 + 10.397 + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/rd_cnt [5] + + + CLMA_218_284/Y1 + td + 0.304 + 10.701 + r + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N140_20/gateop_perm/Z + + + + net (fanout=1) + 0.736 + 11.437 + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N107752 + + + CLMA_214_280/Y1 + td + 0.468 + 11.905 + r + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N140_29/gateop_perm/Z + + + + net (fanout=3) + 0.268 + 12.173 + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N98274 + + + CLMA_214_284/Y1 + td + 0.212 + 12.385 + r + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N135_7/gateop_perm/Z + + + + net (fanout=15) + 0.990 + 13.375 + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/fifo_rd_data_en + + + + td + 0.474 + 13.849 + f + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/opit_0_inv_A2Q1/Cout + + + + net (fanout=1) + 0.000 + 13.849 + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N13665 + + + CLMS_186_277/COUT + td + 0.058 + 13.907 + r + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/opit_0_inv_A2Q21/Cout + + + + net (fanout=1) + 0.000 + 13.907 + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N13667 + + + CLMS_186_281/Y1 + td + 0.498 + 14.405 + r + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/opit_0_inv_A2Q21/Y1 + + + + net (fanout=3) + 0.461 + 14.866 + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N84 [5] + + + CLMA_186_292/Y2 + td + 0.478 + 15.344 + r + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[5]/gateop_perm/Z + + + + net (fanout=1) + 0.644 + 15.988 + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rrptr [5] + + + CLMS_190_285/COUT + td + 0.511 + 16.499 + r + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N170.eq_2/gateop_A2/Cout + + + + net (fanout=1) + 0.000 + 16.499 + + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N170.co [6] + + + CLMS_190_289/CIN + + + + r + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0_A2Q1/Cin + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_720p60Hz (rising edge) + + 13.473 + 13.473 + r + + + + P20 + + 0.000 + 13.473 + r + clk (port) + + + + net (fanout=1) + 0.074 + 13.547 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 15.355 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 15.355 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 15.403 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 16.161 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.100 + 16.261 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.059 + 17.320 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 17.320 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.786 + 19.106 + + ntR3950 + + + PLL_158_303/CLK_OUT1 + td + 0.096 + 19.202 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.571 + 20.773 + + nt_pix_clk + + + USCM_84_117/CLK_USCM + td + 0.000 + 20.773 + r + clkbufg_2/gopclkbufg/CLKOUT + + + + net (fanout=1635) + 1.652 + 22.425 + + ntclkbufg_2 + + + CLMS_190_289/CLK + + + + r + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0_A2Q1/CLK + + + clock pessimism + + 0.569 + 22.994 + + + + + clock uncertainty + + -0.150 + 22.844 + + + + + Setup time + + -0.357 + 22.487 + + + +
+
+
+
+ + 6.037 + 2 + 1 + cmos1_data[0] + u_ov5640/cmos1_d_d0[0]/opit_0/D + + cmos1_pclk + cmos1_pclk + rise-rise + 5.188 + 0.000 + 5.188 + 0.000 + 11.900 + 9.830 + 2.292 (23.3%) + 7.538 (76.7%) + + Path #28: setup slack is 6.037(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock cmos1_pclk (rising edge) + + 0.000 + 0.000 + r + + + + Input external delay + + 1.000 + 1.000 + r + + + + V11 + + 0.000 + 1.000 + r + cmos1_data[0] (port) + + + + net (fanout=1) + 0.053 + 1.053 + + cmos1_data[0] + + + IOBD_133_0/DIN + td + 2.166 + 3.219 + r + cmos1_data_ibuf[0]/opit_0/O + + + + net (fanout=1) + 0.000 + 3.219 + + cmos1_data_ibuf[0]/ntD + + + IOL_135_6/RX_DATA_DD + td + 0.126 + 3.345 + r + cmos1_data_ibuf[0]/opit_1/OUT + + + + net (fanout=1) + 7.485 + 10.830 + + nt_cmos1_data[0] + + + CLMS_134_45/CD + + + + r + u_ov5640/cmos1_d_d0[0]/opit_0/D + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock cmos1_pclk (rising edge) + + 11.900 + 11.900 + r + + + + T12 + + 0.000 + 11.900 + r + cmos1_pclk (port) + + + + net (fanout=1) + 0.076 + 11.976 + + cmos1_pclk + + + IOBD_169_0/DIN + td + 1.047 + 13.023 + r + cmos1_pclk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 13.023 + + cmos1_pclk_ibuf/ntD + + + IOL_171_6/INCK + td + 0.048 + 13.071 + r + cmos1_pclk_ibuf/opit_1/INCK + + + + net (fanout=1) + 2.486 + 15.557 + + _N64 + + + USCM_84_112/CLK_USCM + td + 0.000 + 15.557 + r + clkbufg_6/gopclkbufg/CLKOUT + + + + net (fanout=118) + 1.531 + 17.088 + + ntclkbufg_6 + + + CLMS_134_45/CLK + + + + r + u_ov5640/cmos1_d_d0[0]/opit_0/CLK + + + clock pessimism + + 0.000 + 17.088 + + + + + clock uncertainty + + -0.250 + 16.838 + + + + + Setup time + + 0.029 + 16.867 + + + +
+
+
+
+ + 6.184 + 9 + 12 + u_sync_vg/pos_x[2]/opit_0/CLK + udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[0]/opit_0_L5Q_perm/CE + + clk_720p60Hz + clk_720p60Hz + rise-rise + -0.036 + 9.557 + 8.952 + 0.569 + 13.473 + 6.374 + 2.619 (41.1%) + 3.755 (58.9%) + + Path #29: setup slack is 6.184(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_720p60Hz (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.107 + 3.210 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.078 + 4.288 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 4.288 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.861 + 6.149 + + ntR3950 + + + PLL_158_303/CLK_OUT1 + td + 0.101 + 6.250 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.599 + 7.849 + + nt_pix_clk + + + USCM_84_117/CLK_USCM + td + 0.000 + 7.849 + r + clkbufg_2/gopclkbufg/CLKOUT + + + + net (fanout=1635) + 1.708 + 9.557 + + ntclkbufg_2 + + + CLMA_242_252/CLK + + + + r + u_sync_vg/pos_x[2]/opit_0/CLK + + + CLMA_242_252/Q0 + tco + 0.289 + 9.846 + r + u_sync_vg/pos_x[2]/opit_0/Q + + + + net (fanout=2) + 0.770 + 10.616 + + pos_x[2] + + + + td + 0.326 + 10.942 + f + udp_osd_inst/N26.lt_0/gateop_A2/Cout + + + + net (fanout=1) + 0.000 + 10.942 + + udp_osd_inst/N26.co [2] + + + CLMA_230_244/COUT + td + 0.058 + 11.000 + r + udp_osd_inst/N26.lt_2/gateop_A2/Cout + + + + net (fanout=1) + 0.000 + 11.000 + + udp_osd_inst/N26.co [6] + + + CLMA_230_248/Y1 + td + 0.498 + 11.498 + r + udp_osd_inst/N26.lt_4/gateop_A2/Y1 + + + + net (fanout=4) + 0.645 + 12.143 + + udp_osd_inst/N26 + + + CLMA_250_257/Y2 + td + 0.210 + 12.353 + r + udp_osd_inst/N69_5/gateop_perm/Z + + + + net (fanout=2) + 0.257 + 12.610 + + udp_osd_inst/char_osd_inst/pixels_shifter_inst/N64 + + + CLMA_250_257/Y3 + td + 0.210 + 12.820 + r + udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/gateop_perm/Z + + + + net (fanout=2) + 0.401 + 13.221 + + udp_osd_inst/char_osd_inst/row_pixels_ready + + + CLMA_250_261/Y1 + td + 0.212 + 13.433 + r + udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/gateop_perm/Z + + + + net (fanout=12) + 0.631 + 14.064 + + udp_osd_inst/char_osd_inst/char_next + + + CLMA_246_284/Y2 + td + 0.210 + 14.274 + r + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N74/gateop_perm/Z + + + + net (fanout=1) + 0.253 + 14.527 + + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N74 + + + CLMA_246_284/Y1 + td + 0.212 + 14.739 + r + udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_fsm[3:0]_62/gateop_perm/Z + + + + net (fanout=3) + 0.403 + 15.142 + + udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N97126 + + + CLMA_250_284/Y0 + td + 0.210 + 15.352 + r + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786/gateop_perm/Z + + + + net (fanout=1) + 0.395 + 15.747 + + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786 + + + CLMA_254_288/CECO + td + 0.184 + 15.931 + r + udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[4]/opit_0_A2Q21/CEOUT + + + + net (fanout=4) + 0.000 + 15.931 + + ntR2066 + + + CLMA_254_292/CECI + + + + r + udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[0]/opit_0_L5Q_perm/CE + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_720p60Hz (rising edge) + + 13.473 + 13.473 + r + + + + P20 + + 0.000 + 13.473 + r + clk (port) + + + + net (fanout=1) + 0.074 + 13.547 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 15.355 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 15.355 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 15.403 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 16.161 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.100 + 16.261 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.059 + 17.320 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 17.320 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.786 + 19.106 + + ntR3950 + + + PLL_158_303/CLK_OUT1 + td + 0.096 + 19.202 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.571 + 20.773 + + nt_pix_clk + + + USCM_84_117/CLK_USCM + td + 0.000 + 20.773 + r + clkbufg_2/gopclkbufg/CLKOUT + + + + net (fanout=1635) + 1.652 + 22.425 + + ntclkbufg_2 + + + CLMA_254_292/CLK + + + + r + udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[0]/opit_0_L5Q_perm/CLK + + + clock pessimism + + 0.569 + 22.994 + + + + + clock uncertainty + + -0.150 + 22.844 + + + + + Setup time + + -0.729 + 22.115 + + + +
+
+
+
+ + 6.184 + 9 + 12 + u_sync_vg/pos_x[2]/opit_0/CLK + udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[1]/opit_0_L5Q_perm/CE + + clk_720p60Hz + clk_720p60Hz + rise-rise + -0.036 + 9.557 + 8.952 + 0.569 + 13.473 + 6.374 + 2.619 (41.1%) + 3.755 (58.9%) + + Path #30: setup slack is 6.184(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_720p60Hz (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.107 + 3.210 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.078 + 4.288 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 4.288 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.861 + 6.149 + + ntR3950 + + + PLL_158_303/CLK_OUT1 + td + 0.101 + 6.250 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.599 + 7.849 + + nt_pix_clk + + + USCM_84_117/CLK_USCM + td + 0.000 + 7.849 + r + clkbufg_2/gopclkbufg/CLKOUT + + + + net (fanout=1635) + 1.708 + 9.557 + + ntclkbufg_2 + + + CLMA_242_252/CLK + + + + r + u_sync_vg/pos_x[2]/opit_0/CLK + + + CLMA_242_252/Q0 + tco + 0.289 + 9.846 + r + u_sync_vg/pos_x[2]/opit_0/Q + + + + net (fanout=2) + 0.770 + 10.616 + + pos_x[2] + + + + td + 0.326 + 10.942 + f + udp_osd_inst/N26.lt_0/gateop_A2/Cout + + + + net (fanout=1) + 0.000 + 10.942 + + udp_osd_inst/N26.co [2] + + + CLMA_230_244/COUT + td + 0.058 + 11.000 + r + udp_osd_inst/N26.lt_2/gateop_A2/Cout + + + + net (fanout=1) + 0.000 + 11.000 + + udp_osd_inst/N26.co [6] + + + CLMA_230_248/Y1 + td + 0.498 + 11.498 + r + udp_osd_inst/N26.lt_4/gateop_A2/Y1 + + + + net (fanout=4) + 0.645 + 12.143 + + udp_osd_inst/N26 + + + CLMA_250_257/Y2 + td + 0.210 + 12.353 + r + udp_osd_inst/N69_5/gateop_perm/Z + + + + net (fanout=2) + 0.257 + 12.610 + + udp_osd_inst/char_osd_inst/pixels_shifter_inst/N64 + + + CLMA_250_257/Y3 + td + 0.210 + 12.820 + r + udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/gateop_perm/Z + + + + net (fanout=2) + 0.401 + 13.221 + + udp_osd_inst/char_osd_inst/row_pixels_ready + + + CLMA_250_261/Y1 + td + 0.212 + 13.433 + r + udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/gateop_perm/Z + + + + net (fanout=12) + 0.631 + 14.064 + + udp_osd_inst/char_osd_inst/char_next + + + CLMA_246_284/Y2 + td + 0.210 + 14.274 + r + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N74/gateop_perm/Z + + + + net (fanout=1) + 0.253 + 14.527 + + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N74 + + + CLMA_246_284/Y1 + td + 0.212 + 14.739 + r + udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_fsm[3:0]_62/gateop_perm/Z + + + + net (fanout=3) + 0.403 + 15.142 + + udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N97126 + + + CLMA_250_284/Y0 + td + 0.210 + 15.352 + r + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786/gateop_perm/Z + + + + net (fanout=1) + 0.395 + 15.747 + + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786 + + + CLMA_254_288/CECO + td + 0.184 + 15.931 + r + udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[4]/opit_0_A2Q21/CEOUT + + + + net (fanout=4) + 0.000 + 15.931 + + ntR2066 + + + CLMA_254_292/CECI + + + + r + udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[1]/opit_0_L5Q_perm/CE + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_720p60Hz (rising edge) + + 13.473 + 13.473 + r + + + + P20 + + 0.000 + 13.473 + r + clk (port) + + + + net (fanout=1) + 0.074 + 13.547 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 15.355 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 15.355 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 15.403 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 16.161 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.100 + 16.261 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.059 + 17.320 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 17.320 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.786 + 19.106 + + ntR3950 + + + PLL_158_303/CLK_OUT1 + td + 0.096 + 19.202 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.571 + 20.773 + + nt_pix_clk + + + USCM_84_117/CLK_USCM + td + 0.000 + 20.773 + r + clkbufg_2/gopclkbufg/CLKOUT + + + + net (fanout=1635) + 1.652 + 22.425 + + ntclkbufg_2 + + + CLMA_254_292/CLK + + + + r + udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[1]/opit_0_L5Q_perm/CLK + + + clock pessimism + + 0.569 + 22.994 + + + + + clock uncertainty + + -0.150 + 22.844 + + + + + Setup time + + -0.729 + 22.115 + + + +
+
+
+
+ + 10.354 + 6 + 6 + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/L4 + + clk_50m + clk_50m + rise-rise + -0.058 + 5.909 + 5.392 + 0.459 + 20.000 + 9.315 + 5.094 (54.7%) + 4.221 (45.3%) + + Path #31: setup slack is 10.354(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_50m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.107 + 3.210 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.078 + 4.288 + + rd3_clk + + + USCM_84_108/CLK_USCM + td + 0.000 + 4.288 + r + clkbufg_1/gopclkbufg/CLKOUT + + + + net (fanout=2516) + 1.621 + 5.909 + + ntclkbufg_1 + + + DRM_54_24/CLKB[0] + + + + r + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB + + + DRM_54_24/QB0[0] + tco + 2.307 + 8.216 + f + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/DOB[0] + + + + net (fanout=6) + 1.422 + 9.638 + + u_rotate_image/dout [0] + + + CLMS_74_117/Y1 + td + 0.466 + 10.104 + f + u_rotate_image/addr_fifo_valid/opit_0_L5Q_perm/Z + + + + net (fanout=3) + 1.540 + 11.644 + + u_rotate_image/addr_fifo_rd_en + + + + td + 0.288 + 11.932 + f + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/Cout + + + + net (fanout=1) + 0.000 + 11.932 + + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16576 + + + CLMS_50_33/COUT + td + 0.058 + 11.990 + r + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/Cout + + + + net (fanout=1) + 0.000 + 11.990 + + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16578 + + + CLMS_50_37/Y1 + td + 0.498 + 12.488 + r + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/Y1 + + + + net (fanout=1) + 0.527 + 13.015 + + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11 [5] + + + CLMA_58_29/Y1 + td + 0.468 + 13.483 + r + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[5]/gateop_perm/Z + + + + net (fanout=3) + 0.612 + 14.095 + + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/rrptr [5] + + + CLMA_58_36/COUT + td + 0.511 + 14.606 + r + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_2/gateop_A2/Cout + + + + net (fanout=1) + 0.000 + 14.606 + + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.co [6] + + + CLMA_58_40/Y1 + td + 0.498 + 15.104 + r + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_4/gateop_A2/Y1 + + + + net (fanout=1) + 0.120 + 15.224 + + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21 + + + CLMA_58_40/C4 + + + + r + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/L4 + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_50m (rising edge) + + 20.000 + 20.000 + r + + + + P20 + + 0.000 + 20.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 20.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 21.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 21.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 21.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 22.688 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.100 + 22.788 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.059 + 23.847 + + rd3_clk + + + USCM_84_108/CLK_USCM + td + 0.000 + 23.847 + r + clkbufg_1/gopclkbufg/CLKOUT + + + + net (fanout=2516) + 1.545 + 25.392 + + ntclkbufg_1 + + + CLMA_58_40/CLK + + + + r + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK + + + clock pessimism + + 0.459 + 25.851 + + + + + clock uncertainty + + -0.150 + 25.701 + + + + + Setup time + + -0.123 + 25.578 + + + +
+
+
+
+ + 10.942 + 5 + 6 + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/Cin + + clk_50m + clk_50m + rise-rise + -0.061 + 5.909 + 5.389 + 0.459 + 20.000 + 8.490 + 4.596 (54.1%) + 3.894 (45.9%) + + Path #32: setup slack is 10.942(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_50m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.107 + 3.210 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.078 + 4.288 + + rd3_clk + + + USCM_84_108/CLK_USCM + td + 0.000 + 4.288 + r + clkbufg_1/gopclkbufg/CLKOUT + + + + net (fanout=2516) + 1.621 + 5.909 + + ntclkbufg_1 + + + DRM_54_24/CLKB[0] + + + + r + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB + + + DRM_54_24/QB0[0] + tco + 2.307 + 8.216 + f + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/DOB[0] + + + + net (fanout=6) + 1.422 + 9.638 + + u_rotate_image/dout [0] + + + CLMS_74_117/Y1 + td + 0.466 + 10.104 + f + u_rotate_image/addr_fifo_valid/opit_0_L5Q_perm/Z + + + + net (fanout=3) + 1.540 + 11.644 + + u_rotate_image/addr_fifo_rd_en + + + + td + 0.288 + 11.932 + f + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/Cout + + + + net (fanout=1) + 0.000 + 11.932 + + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16576 + + + CLMS_50_33/COUT + td + 0.058 + 11.990 + r + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/Cout + + + + net (fanout=1) + 0.000 + 11.990 + + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16578 + + + CLMS_50_37/Y1 + td + 0.498 + 12.488 + r + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/Y1 + + + + net (fanout=1) + 0.527 + 13.015 + + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11 [5] + + + CLMA_58_29/Y1 + td + 0.468 + 13.483 + r + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[5]/gateop_perm/Z + + + + net (fanout=3) + 0.405 + 13.888 + + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/rrptr [5] + + + CLMA_62_32/COUT + td + 0.511 + 14.399 + r + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N24.eq_2/gateop_A2/Cout + + + + net (fanout=1) + 0.000 + 14.399 + + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N24.co [6] + + + CLMA_62_36/CIN + + + + r + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/Cin + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_50m (rising edge) + + 20.000 + 20.000 + r + + + + P20 + + 0.000 + 20.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 20.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 21.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 21.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 21.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 22.688 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.100 + 22.788 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.059 + 23.847 + + rd3_clk + + + USCM_84_108/CLK_USCM + td + 0.000 + 23.847 + r + clkbufg_1/gopclkbufg/CLKOUT + + + + net (fanout=2516) + 1.542 + 25.389 + + ntclkbufg_1 + + + CLMA_62_36/CLK + + + + r + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/CLK + + + clock pessimism + + 0.459 + 25.848 + + + + + clock uncertainty + + -0.150 + 25.698 + + + + + Setup time + + -0.357 + 25.341 + + + +
+
+
+
+ + 10.957 + 9 + 5 + image_filiter_inst/multiline_buffer_inst/hor_cnt[4]/opit_0_A2Q21/CLK + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/L4 + + clk_50m + clk_50m + rise-rise + -0.036 + 5.996 + 5.499 + 0.461 + 20.000 + 8.734 + 4.330 (49.6%) + 4.404 (50.4%) + + Path #33: setup slack is 10.957(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_50m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.107 + 3.210 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.078 + 4.288 + + rd3_clk + + + USCM_84_108/CLK_USCM + td + 0.000 + 4.288 + r + clkbufg_1/gopclkbufg/CLKOUT + + + + net (fanout=2516) + 1.708 + 5.996 + + ntclkbufg_1 + + + CLMA_78_280/CLK + + + + r + image_filiter_inst/multiline_buffer_inst/hor_cnt[4]/opit_0_A2Q21/CLK + + + CLMA_78_280/Q2 + tco + 0.290 + 6.286 + r + image_filiter_inst/multiline_buffer_inst/hor_cnt[4]/opit_0_A2Q21/Q0 + + + + net (fanout=2) + 0.417 + 6.703 + + image_filiter_inst/multiline_buffer_inst/hor_cnt [3] + + + CLMA_74_280/Y1 + td + 0.460 + 7.163 + r + image_filiter_inst/multiline_buffer_inst/N229_8/gateop_perm/Z + + + + net (fanout=1) + 0.407 + 7.570 + + image_filiter_inst/multiline_buffer_inst/_N104607 + + + CLMS_78_285/Y2 + td + 0.286 + 7.856 + r + image_filiter_inst/multiline_buffer_inst/N229_11/gateop_perm/Z + + + + net (fanout=5) + 0.525 + 8.381 + + image_filiter_inst/multiline_buffer_inst/N229 + + + CLMS_94_289/Y2 + td + 0.487 + 8.868 + r + image_filiter_inst/multiline_buffer_inst/N176_7/gateop_perm/Z + + + + net (fanout=1) + 0.403 + 9.271 + + image_filiter_inst/multiline_buffer_inst/N176 + + + CLMA_90_284/Y2 + td + 0.478 + 9.749 + r + image_filiter_inst/multiline_buffer_inst/N189[1]_4/gateop_perm/Z + + + + net (fanout=4) + 0.839 + 10.588 + + image_filiter_inst/multiline_buffer_inst/rd_en [1] + + + + td + 0.234 + 10.822 + f + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/Cout + + + + net (fanout=1) + 0.000 + 10.822 + + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N14178 + + + CLMS_78_269/COUT + td + 0.058 + 10.880 + r + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/Cout + + + + net (fanout=1) + 0.000 + 10.880 + + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N14180 + + + + td + 0.058 + 10.938 + r + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/Cout + + + + net (fanout=1) + 0.000 + 10.938 + + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N14182 + + + CLMS_78_273/Y3 + td + 0.501 + 11.439 + r + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/Y1 + + + + net (fanout=1) + 0.519 + 11.958 + + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11 [7] + + + CLMS_94_273/Y3 + td + 0.465 + 12.423 + f + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[7]/gateop_perm/Z + + + + net (fanout=2) + 0.847 + 13.270 + + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/rrptr [7] + + + CLMA_90_276/COUT + td + 0.515 + 13.785 + r + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N21.eq_2/gateop_A2/Cout + + + + net (fanout=1) + 0.000 + 13.785 + + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N21.co [6] + + + CLMA_90_280/Y1 + td + 0.498 + 14.283 + r + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N21.eq_4/gateop_A2/Y1 + + + + net (fanout=1) + 0.447 + 14.730 + + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N21 + + + CLMA_90_272/C4 + + + + r + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/L4 + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_50m (rising edge) + + 20.000 + 20.000 + r + + + + P20 + + 0.000 + 20.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 20.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 21.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 21.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 21.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 22.688 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.100 + 22.788 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.059 + 23.847 + + rd3_clk + + + USCM_84_108/CLK_USCM + td + 0.000 + 23.847 + r + clkbufg_1/gopclkbufg/CLKOUT + + + + net (fanout=2516) + 1.652 + 25.499 + + ntclkbufg_1 + + + CLMA_90_272/CLK + + + + r + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK + + + clock pessimism + + 0.461 + 25.960 + + + + + clock uncertainty + + -0.150 + 25.810 + + + + + Setup time + + -0.123 + 25.687 + + + +
+
+
+
+ + 35.501 + 4 + 13 + u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK + u_ov5640/coms2_reg_config/clock_20k_cnt[10]/opit_0_inv/D + + clk_25m + clk_25m + rise-rise + -0.029 + 5.877 + 5.383 + 0.465 + 40.000 + 4.241 + 2.002 (47.2%) + 2.239 (52.8%) + + Path #34: setup slack is 35.501(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_25m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT3 + td + 0.111 + 3.214 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT3 + + + + net (fanout=1) + 1.078 + 4.292 + + clk_25m + + + USCM_84_114/CLK_USCM + td + 0.000 + 4.292 + r + clkbufg_8/gopclkbufg/CLKOUT + + + + net (fanout=26) + 1.585 + 5.877 + + ntclkbufg_8 + + + CLMS_122_13/CLK + + + + r + u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK + + + CLMS_122_13/Q1 + tco + 0.291 + 6.168 + r + u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/Q + + + + net (fanout=4) + 0.406 + 6.574 + + u_ov5640/coms2_reg_config/clock_20k_cnt [0] + + + CLMA_122_16/Y3 + td + 0.468 + 7.042 + r + u_ov5640/coms2_reg_config/N8_mux4_5/gateop_perm/Z + + + + net (fanout=1) + 0.560 + 7.602 + + u_ov5640/coms2_reg_config/_N9749 + + + CLMA_122_16/Y2 + td + 0.210 + 7.812 + r + u_ov5640/coms2_reg_config/N8_mux10/gateop_perm/Z + + + + net (fanout=13) + 0.569 + 8.381 + + u_ov5640/coms2_reg_config/N8 + + + + td + 0.477 + 8.858 + f + u_ov5640/coms2_reg_config/N11_2_5/gateop_A2/Cout + + + + net (fanout=1) + 0.000 + 8.858 + + u_ov5640/coms2_reg_config/_N16307 + + + CLMS_122_17/COUT + td + 0.058 + 8.916 + r + u_ov5640/coms2_reg_config/N11_2_7/gateop_A2/Cout + + + + net (fanout=1) + 0.000 + 8.916 + + u_ov5640/coms2_reg_config/_N16309 + + + CLMS_122_21/Y1 + td + 0.498 + 9.414 + r + u_ov5640/coms2_reg_config/N11_2_9/gateop_A2/Y1 + + + + net (fanout=1) + 0.704 + 10.118 + + u_ov5640/coms2_reg_config/N1114 [10] + + + CLMS_122_17/M3 + + + + r + u_ov5640/coms2_reg_config/clock_20k_cnt[10]/opit_0_inv/D + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_25m (rising edge) + + 40.000 + 40.000 + r + + + + P20 + + 0.000 + 40.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 40.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 41.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 41.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 41.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 42.688 + + _N69 + + + PLL_158_55/CLK_OUT3 + td + 0.105 + 42.793 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT3 + + + + net (fanout=1) + 1.059 + 43.852 + + clk_25m + + + USCM_84_114/CLK_USCM + td + 0.000 + 43.852 + r + clkbufg_8/gopclkbufg/CLKOUT + + + + net (fanout=26) + 1.531 + 45.383 + + ntclkbufg_8 + + + CLMS_122_17/CLK + + + + r + u_ov5640/coms2_reg_config/clock_20k_cnt[10]/opit_0_inv/CLK + + + clock pessimism + + 0.465 + 45.848 + + + + + clock uncertainty + + -0.150 + 45.698 + + + + + Setup time + + -0.079 + 45.619 + + + +
+
+
+
+ + 35.513 + 3 + 13 + u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK + u_ov5640/coms2_reg_config/clock_20k_cnt[8]/opit_0_inv/D + + clk_25m + clk_25m + rise-rise + -0.029 + 5.877 + 5.383 + 0.465 + 40.000 + 4.229 + 1.947 (46.0%) + 2.282 (54.0%) + + Path #35: setup slack is 35.513(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_25m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT3 + td + 0.111 + 3.214 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT3 + + + + net (fanout=1) + 1.078 + 4.292 + + clk_25m + + + USCM_84_114/CLK_USCM + td + 0.000 + 4.292 + r + clkbufg_8/gopclkbufg/CLKOUT + + + + net (fanout=26) + 1.585 + 5.877 + + ntclkbufg_8 + + + CLMS_122_13/CLK + + + + r + u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK + + + CLMS_122_13/Q1 + tco + 0.291 + 6.168 + r + u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/Q + + + + net (fanout=4) + 0.406 + 6.574 + + u_ov5640/coms2_reg_config/clock_20k_cnt [0] + + + CLMA_122_16/Y3 + td + 0.468 + 7.042 + r + u_ov5640/coms2_reg_config/N8_mux4_5/gateop_perm/Z + + + + net (fanout=1) + 0.560 + 7.602 + + u_ov5640/coms2_reg_config/_N9749 + + + CLMA_122_16/Y2 + td + 0.210 + 7.812 + r + u_ov5640/coms2_reg_config/N8_mux10/gateop_perm/Z + + + + net (fanout=13) + 0.569 + 8.381 + + u_ov5640/coms2_reg_config/N8 + + + + td + 0.477 + 8.858 + f + u_ov5640/coms2_reg_config/N11_2_5/gateop_A2/Cout + + + + net (fanout=1) + 0.000 + 8.858 + + u_ov5640/coms2_reg_config/_N16307 + + + CLMS_122_17/Y3 + td + 0.501 + 9.359 + r + u_ov5640/coms2_reg_config/N11_2_7/gateop_A2/Y1 + + + + net (fanout=1) + 0.747 + 10.106 + + u_ov5640/coms2_reg_config/N1114 [8] + + + CLMS_122_17/M2 + + + + r + u_ov5640/coms2_reg_config/clock_20k_cnt[8]/opit_0_inv/D + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_25m (rising edge) + + 40.000 + 40.000 + r + + + + P20 + + 0.000 + 40.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 40.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 41.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 41.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 41.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 42.688 + + _N69 + + + PLL_158_55/CLK_OUT3 + td + 0.105 + 42.793 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT3 + + + + net (fanout=1) + 1.059 + 43.852 + + clk_25m + + + USCM_84_114/CLK_USCM + td + 0.000 + 43.852 + r + clkbufg_8/gopclkbufg/CLKOUT + + + + net (fanout=26) + 1.531 + 45.383 + + ntclkbufg_8 + + + CLMS_122_17/CLK + + + + r + u_ov5640/coms2_reg_config/clock_20k_cnt[8]/opit_0_inv/CLK + + + clock pessimism + + 0.465 + 45.848 + + + + + clock uncertainty + + -0.150 + 45.698 + + + + + Setup time + + -0.079 + 45.619 + + + +
+
+
+
+ + 35.717 + 4 + 13 + u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK + u_ov5640/coms2_reg_config/clock_20k_cnt[9]/opit_0_inv/D + + clk_25m + clk_25m + rise-rise + -0.029 + 5.877 + 5.383 + 0.465 + 40.000 + 4.016 + 1.771 (44.1%) + 2.245 (55.9%) + + Path #36: setup slack is 35.717(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_25m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT3 + td + 0.111 + 3.214 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT3 + + + + net (fanout=1) + 1.078 + 4.292 + + clk_25m + + + USCM_84_114/CLK_USCM + td + 0.000 + 4.292 + r + clkbufg_8/gopclkbufg/CLKOUT + + + + net (fanout=26) + 1.585 + 5.877 + + ntclkbufg_8 + + + CLMS_122_13/CLK + + + + r + u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK + + + CLMS_122_13/Q1 + tco + 0.291 + 6.168 + r + u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/Q + + + + net (fanout=4) + 0.406 + 6.574 + + u_ov5640/coms2_reg_config/clock_20k_cnt [0] + + + CLMA_122_16/Y3 + td + 0.468 + 7.042 + r + u_ov5640/coms2_reg_config/N8_mux4_5/gateop_perm/Z + + + + net (fanout=1) + 0.560 + 7.602 + + u_ov5640/coms2_reg_config/_N9749 + + + CLMA_122_16/Y2 + td + 0.210 + 7.812 + r + u_ov5640/coms2_reg_config/N8_mux10/gateop_perm/Z + + + + net (fanout=13) + 0.569 + 8.381 + + u_ov5640/coms2_reg_config/N8 + + + + td + 0.477 + 8.858 + f + u_ov5640/coms2_reg_config/N11_2_5/gateop_A2/Cout + + + + net (fanout=1) + 0.000 + 8.858 + + u_ov5640/coms2_reg_config/_N16307 + + + CLMS_122_17/COUT + td + 0.058 + 8.916 + r + u_ov5640/coms2_reg_config/N11_2_7/gateop_A2/Cout + + + + net (fanout=1) + 0.000 + 8.916 + + u_ov5640/coms2_reg_config/_N16309 + + + CLMS_122_21/Y0 + td + 0.267 + 9.183 + f + u_ov5640/coms2_reg_config/N11_2_9/gateop_A2/Y0 + + + + net (fanout=1) + 0.710 + 9.893 + + u_ov5640/coms2_reg_config/N1114 [9] + + + CLMS_122_17/M1 + + + + f + u_ov5640/coms2_reg_config/clock_20k_cnt[9]/opit_0_inv/D + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_25m (rising edge) + + 40.000 + 40.000 + r + + + + P20 + + 0.000 + 40.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 40.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 41.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 41.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 41.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 42.688 + + _N69 + + + PLL_158_55/CLK_OUT3 + td + 0.105 + 42.793 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT3 + + + + net (fanout=1) + 1.059 + 43.852 + + clk_25m + + + USCM_84_114/CLK_USCM + td + 0.000 + 43.852 + r + clkbufg_8/gopclkbufg/CLKOUT + + + + net (fanout=26) + 1.531 + 45.383 + + ntclkbufg_8 + + + CLMS_122_17/CLK + + + + r + u_ov5640/coms2_reg_config/clock_20k_cnt[9]/opit_0_inv/CLK + + + clock pessimism + + 0.465 + 45.848 + + + + + clock uncertainty + + -0.150 + 45.698 + + + + + Setup time + + -0.088 + 45.610 + + + +
+
+
+
+ + 94.588 + 6 + 15 + ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK + ms72xx_ctl/ms7200_ctl/addr[0]/opit_0_inv_L5Q_perm/CE + + clk_10m + clk_10m + rise-rise + -0.036 + 5.996 + 5.499 + 0.461 + 100.000 + 4.497 + 1.885 (41.9%) + 2.612 (58.1%) + + Path #37: setup slack is 94.588(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_10m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT4 + td + 0.107 + 3.210 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT4 + + + + net (fanout=1) + 1.078 + 4.288 + + clk_10m + + + USCM_84_110/CLK_USCM + td + 0.000 + 4.288 + r + clkbufg_4/gopclkbufg/CLKOUT + + + + net (fanout=235) + 1.708 + 5.996 + + ntclkbufg_4 + + + CLMS_218_329/CLK + + + + r + ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK + + + CLMS_218_329/Q2 + tco + 0.290 + 6.286 + r + ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/Q + + + + net (fanout=3) + 0.271 + 6.557 + + ms72xx_ctl/ms7200_ctl/dri_cnt [4] + + + CLMS_218_333/Y3 + td + 0.459 + 7.016 + r + ms72xx_ctl/ms7200_ctl/N8_3/gateop_perm/Z + + + + net (fanout=1) + 0.257 + 7.273 + + ms72xx_ctl/ms7200_ctl/_N96627 + + + CLMS_218_333/Y0 + td + 0.210 + 7.483 + r + ms72xx_ctl/ms7200_ctl/N1872_5/gateop_perm/Z + + + + net (fanout=6) + 0.412 + 7.895 + + ms72xx_ctl/ms7200_ctl/_N96632 + + + CLMS_222_329/Y0 + td + 0.210 + 8.105 + r + ms72xx_ctl/ms7200_ctl/N2053_1/gateop_perm/Z + + + + net (fanout=15) + 0.564 + 8.669 + + ms72xx_ctl/ms7200_ctl/N261 + + + CLMS_214_321/Y0 + td + 0.320 + 8.989 + r + ms72xx_ctl/ms7200_ctl/N40_9/gateop_perm/Z + + + + net (fanout=4) + 0.548 + 9.537 + + ms72xx_ctl/ms7200_ctl/N2093 [4] + + + CLMA_222_324/Y1 + td + 0.212 + 9.749 + r + ms72xx_ctl/ms7200_ctl/N1955/gateop_perm/Z + + + + net (fanout=12) + 0.560 + 10.309 + + ms72xx_ctl/ms7200_ctl/N1955 + + + CLMA_230_324/CECO + td + 0.184 + 10.493 + r + ms72xx_ctl/ms7200_ctl/data_in[5]/opit_0_inv_L5Q_perm/CEOUT + + + + net (fanout=4) + 0.000 + 10.493 + + ntR1800 + + + CLMA_230_328/CECI + + + + r + ms72xx_ctl/ms7200_ctl/addr[0]/opit_0_inv_L5Q_perm/CE + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_10m (rising edge) + + 100.000 + 100.000 + r + + + + P20 + + 0.000 + 100.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 100.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 101.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 101.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 101.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 102.688 + + _N69 + + + PLL_158_55/CLK_OUT4 + td + 0.100 + 102.788 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT4 + + + + net (fanout=1) + 1.059 + 103.847 + + clk_10m + + + USCM_84_110/CLK_USCM + td + 0.000 + 103.847 + r + clkbufg_4/gopclkbufg/CLKOUT + + + + net (fanout=235) + 1.652 + 105.499 + + ntclkbufg_4 + + + CLMA_230_328/CLK + + + + r + ms72xx_ctl/ms7200_ctl/addr[0]/opit_0_inv_L5Q_perm/CLK + + + clock pessimism + + 0.461 + 105.960 + + + + + clock uncertainty + + -0.150 + 105.810 + + + + + Setup time + + -0.729 + 105.081 + + + +
+
+
+
+ + 94.588 + 6 + 15 + ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK + ms72xx_ctl/ms7200_ctl/addr[4]/opit_0_inv_L5Q_perm/CE + + clk_10m + clk_10m + rise-rise + -0.036 + 5.996 + 5.499 + 0.461 + 100.000 + 4.497 + 1.885 (41.9%) + 2.612 (58.1%) + + Path #38: setup slack is 94.588(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_10m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT4 + td + 0.107 + 3.210 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT4 + + + + net (fanout=1) + 1.078 + 4.288 + + clk_10m + + + USCM_84_110/CLK_USCM + td + 0.000 + 4.288 + r + clkbufg_4/gopclkbufg/CLKOUT + + + + net (fanout=235) + 1.708 + 5.996 + + ntclkbufg_4 + + + CLMS_218_329/CLK + + + + r + ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK + + + CLMS_218_329/Q2 + tco + 0.290 + 6.286 + r + ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/Q + + + + net (fanout=3) + 0.271 + 6.557 + + ms72xx_ctl/ms7200_ctl/dri_cnt [4] + + + CLMS_218_333/Y3 + td + 0.459 + 7.016 + r + ms72xx_ctl/ms7200_ctl/N8_3/gateop_perm/Z + + + + net (fanout=1) + 0.257 + 7.273 + + ms72xx_ctl/ms7200_ctl/_N96627 + + + CLMS_218_333/Y0 + td + 0.210 + 7.483 + r + ms72xx_ctl/ms7200_ctl/N1872_5/gateop_perm/Z + + + + net (fanout=6) + 0.412 + 7.895 + + ms72xx_ctl/ms7200_ctl/_N96632 + + + CLMS_222_329/Y0 + td + 0.210 + 8.105 + r + ms72xx_ctl/ms7200_ctl/N2053_1/gateop_perm/Z + + + + net (fanout=15) + 0.564 + 8.669 + + ms72xx_ctl/ms7200_ctl/N261 + + + CLMS_214_321/Y0 + td + 0.320 + 8.989 + r + ms72xx_ctl/ms7200_ctl/N40_9/gateop_perm/Z + + + + net (fanout=4) + 0.548 + 9.537 + + ms72xx_ctl/ms7200_ctl/N2093 [4] + + + CLMA_222_324/Y1 + td + 0.212 + 9.749 + r + ms72xx_ctl/ms7200_ctl/N1955/gateop_perm/Z + + + + net (fanout=12) + 0.560 + 10.309 + + ms72xx_ctl/ms7200_ctl/N1955 + + + CLMA_230_324/CECO + td + 0.184 + 10.493 + r + ms72xx_ctl/ms7200_ctl/data_in[5]/opit_0_inv_L5Q_perm/CEOUT + + + + net (fanout=4) + 0.000 + 10.493 + + ntR1800 + + + CLMA_230_328/CECI + + + + r + ms72xx_ctl/ms7200_ctl/addr[4]/opit_0_inv_L5Q_perm/CE + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_10m (rising edge) + + 100.000 + 100.000 + r + + + + P20 + + 0.000 + 100.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 100.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 101.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 101.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 101.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 102.688 + + _N69 + + + PLL_158_55/CLK_OUT4 + td + 0.100 + 102.788 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT4 + + + + net (fanout=1) + 1.059 + 103.847 + + clk_10m + + + USCM_84_110/CLK_USCM + td + 0.000 + 103.847 + r + clkbufg_4/gopclkbufg/CLKOUT + + + + net (fanout=235) + 1.652 + 105.499 + + ntclkbufg_4 + + + CLMA_230_328/CLK + + + + r + ms72xx_ctl/ms7200_ctl/addr[4]/opit_0_inv_L5Q_perm/CLK + + + clock pessimism + + 0.461 + 105.960 + + + + + clock uncertainty + + -0.150 + 105.810 + + + + + Setup time + + -0.729 + 105.081 + + + +
+
+
+
+ + 94.588 + 6 + 15 + ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK + ms72xx_ctl/ms7200_ctl/addr[5]/opit_0_inv_L5Q_perm/CE + + clk_10m + clk_10m + rise-rise + -0.036 + 5.996 + 5.499 + 0.461 + 100.000 + 4.497 + 1.885 (41.9%) + 2.612 (58.1%) + + Path #39: setup slack is 94.588(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_10m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT4 + td + 0.107 + 3.210 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT4 + + + + net (fanout=1) + 1.078 + 4.288 + + clk_10m + + + USCM_84_110/CLK_USCM + td + 0.000 + 4.288 + r + clkbufg_4/gopclkbufg/CLKOUT + + + + net (fanout=235) + 1.708 + 5.996 + + ntclkbufg_4 + + + CLMS_218_329/CLK + + + + r + ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK + + + CLMS_218_329/Q2 + tco + 0.290 + 6.286 + r + ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/Q + + + + net (fanout=3) + 0.271 + 6.557 + + ms72xx_ctl/ms7200_ctl/dri_cnt [4] + + + CLMS_218_333/Y3 + td + 0.459 + 7.016 + r + ms72xx_ctl/ms7200_ctl/N8_3/gateop_perm/Z + + + + net (fanout=1) + 0.257 + 7.273 + + ms72xx_ctl/ms7200_ctl/_N96627 + + + CLMS_218_333/Y0 + td + 0.210 + 7.483 + r + ms72xx_ctl/ms7200_ctl/N1872_5/gateop_perm/Z + + + + net (fanout=6) + 0.412 + 7.895 + + ms72xx_ctl/ms7200_ctl/_N96632 + + + CLMS_222_329/Y0 + td + 0.210 + 8.105 + r + ms72xx_ctl/ms7200_ctl/N2053_1/gateop_perm/Z + + + + net (fanout=15) + 0.564 + 8.669 + + ms72xx_ctl/ms7200_ctl/N261 + + + CLMS_214_321/Y0 + td + 0.320 + 8.989 + r + ms72xx_ctl/ms7200_ctl/N40_9/gateop_perm/Z + + + + net (fanout=4) + 0.548 + 9.537 + + ms72xx_ctl/ms7200_ctl/N2093 [4] + + + CLMA_222_324/Y1 + td + 0.212 + 9.749 + r + ms72xx_ctl/ms7200_ctl/N1955/gateop_perm/Z + + + + net (fanout=12) + 0.560 + 10.309 + + ms72xx_ctl/ms7200_ctl/N1955 + + + CLMA_230_324/CECO + td + 0.184 + 10.493 + r + ms72xx_ctl/ms7200_ctl/data_in[5]/opit_0_inv_L5Q_perm/CEOUT + + + + net (fanout=4) + 0.000 + 10.493 + + ntR1800 + + + CLMA_230_328/CECI + + + + r + ms72xx_ctl/ms7200_ctl/addr[5]/opit_0_inv_L5Q_perm/CE + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_10m (rising edge) + + 100.000 + 100.000 + r + + + + P20 + + 0.000 + 100.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 100.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 101.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 101.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 101.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 102.688 + + _N69 + + + PLL_158_55/CLK_OUT4 + td + 0.100 + 102.788 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT4 + + + + net (fanout=1) + 1.059 + 103.847 + + clk_10m + + + USCM_84_110/CLK_USCM + td + 0.000 + 103.847 + r + clkbufg_4/gopclkbufg/CLKOUT + + + + net (fanout=235) + 1.652 + 105.499 + + ntclkbufg_4 + + + CLMA_230_328/CLK + + + + r + ms72xx_ctl/ms7200_ctl/addr[5]/opit_0_inv_L5Q_perm/CLK + + + clock pessimism + + 0.461 + 105.960 + + + + + clock uncertainty + + -0.150 + 105.810 + + + + + Setup time + + -0.729 + 105.081 + + + +
+
+
+
+ + 49994.611 + 3 + 1 + u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0] + u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I0 + + clk_20k + clk_20k + rise-rise + -0.036 + 10.251 + 9.367 + 0.848 + 50000.000 + 5.107 + 3.251 (63.7%) + 1.856 (36.3%) + + Path #40: setup slack is 49994.611(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_20k (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT3 + td + 0.111 + 3.214 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT3 + + + + net (fanout=1) + 1.078 + 4.292 + + clk_25m + + + USCM_84_114/CLK_USCM + td + 0.000 + 4.292 + r + clkbufg_8/gopclkbufg/CLKOUT + + + + net (fanout=26) + 1.585 + 5.877 + + ntclkbufg_8 + + + CLMS_122_9/Q1 + tco + 0.291 + 6.168 + r + u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q + + + + net (fanout=3) + 2.498 + 8.666 + + u_ov5640/coms1_reg_config/clk_20k_regdiv + + + USCM_84_120/CLK_USCM + td + 0.000 + 8.666 + r + u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + + + + net (fanout=19) + 1.585 + 10.251 + + u_ov5640/coms1_reg_config/clock_20k + + + DRM_142_4/CLKB[0] + + + + r + u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0] + + + DRM_142_4/QB0[6] + tco + 2.286 + 12.537 + r + u_ov5640/coms1_reg_config/reg_data/iGopDrm/QB0[6] + + + + net (fanout=1) + 0.573 + 13.110 + + u_ov5640/coms1_reg_config/i2c_data [22] + + + CLMA_146_12/Y1 + td + 0.460 + 13.570 + r + u_ov5640/coms1_reg_config/u1/N267_29/gateop/F + + + + net (fanout=1) + 0.580 + 14.150 + + u_ov5640/coms1_reg_config/u1/_N25311 + + + CLMA_138_16/Y0 + td + 0.210 + 14.360 + r + u_ov5640/coms1_reg_config/u1/N267_35/gateop_perm/Z + + + + net (fanout=1) + 0.256 + 14.616 + + u_ov5640/coms1_reg_config/u1/_N25317 + + + CLMA_138_16/Y2 + td + 0.295 + 14.911 + r + u_ov5640/coms1_reg_config/u1/N267_36/gateop/F + + + + net (fanout=1) + 0.447 + 15.358 + + u_ov5640/coms1_reg_config/u1/_N25318 + + + CLMA_138_9/AD + + + + r + u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I0 + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_20k (rising edge) + + 50000.000 + 50000.000 + r + + + + P20 + + 0.000 + 50000.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 50000.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 50001.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 50001.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 50001.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 50002.688 + + _N69 + + + PLL_158_55/CLK_OUT3 + td + 0.105 + 50002.793 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT3 + + + + net (fanout=1) + 1.059 + 50003.852 + + clk_25m + + + USCM_84_114/CLK_USCM + td + 0.000 + 50003.852 + r + clkbufg_8/gopclkbufg/CLKOUT + + + + net (fanout=26) + 1.531 + 50005.383 + + ntclkbufg_8 + + + CLMS_122_9/Q1 + tco + 0.229 + 50005.612 + r + u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q + + + + net (fanout=3) + 2.224 + 50007.836 + + u_ov5640/coms1_reg_config/clk_20k_regdiv + + + USCM_84_120/CLK_USCM + td + 0.000 + 50007.836 + r + u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + + + + net (fanout=19) + 1.531 + 50009.367 + + u_ov5640/coms1_reg_config/clock_20k + + + CLMA_138_9/CLK + + + + r + u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/CLK + + + clock pessimism + + 0.848 + 50010.215 + + + + + clock uncertainty + + -0.050 + 50010.165 + + + + + Setup time + + -0.196 + 50009.969 + + + +
+
+
+
+ + 49994.893 + 3 + 1 + u_ov5640/coms2_reg_config/reg_data/iGopDrm/CLKB[0] + u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_L5Q_perm/L4 + + clk_20k + clk_20k + rise-rise + -0.093 + 10.167 + 9.258 + 0.816 + 50000.000 + 4.843 + 3.215 (66.4%) + 1.628 (33.6%) + + Path #41: setup slack is 49994.893(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_20k (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT3 + td + 0.111 + 3.214 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT3 + + + + net (fanout=1) + 1.078 + 4.292 + + clk_25m + + + USCM_84_114/CLK_USCM + td + 0.000 + 4.292 + r + clkbufg_8/gopclkbufg/CLKOUT + + + + net (fanout=26) + 1.585 + 5.877 + + ntclkbufg_8 + + + CLMA_122_12/Q1 + tco + 0.291 + 6.168 + r + u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q + + + + net (fanout=3) + 2.357 + 8.525 + + u_ov5640/coms2_reg_config/clk_20k_regdiv + + + USCM_84_121/CLK_USCM + td + 0.000 + 8.525 + r + u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + + + + net (fanout=19) + 1.642 + 10.167 + + u_ov5640/coms2_reg_config/clock_20k + + + DRM_82_4/CLKB[0] + + + + r + u_ov5640/coms2_reg_config/reg_data/iGopDrm/CLKB[0] + + + DRM_82_4/QB0[5] + tco + 2.286 + 12.453 + r + u_ov5640/coms2_reg_config/reg_data/iGopDrm/QB0[5] + + + + net (fanout=1) + 0.501 + 12.954 + + u_ov5640/coms2_reg_config/i2c_data [21] + + + CLMS_78_9/Y1 + td + 0.460 + 13.414 + r + u_ov5640/coms2_reg_config/u1/N267_29/gateop/F + + + + net (fanout=1) + 0.612 + 14.026 + + u_ov5640/coms2_reg_config/u1/_N25853 + + + CLMA_90_12/Y2 + td + 0.210 + 14.236 + r + u_ov5640/coms2_reg_config/u1/N267_35/gateop_perm/Z + + + + net (fanout=1) + 0.257 + 14.493 + + u_ov5640/coms2_reg_config/u1/_N25859 + + + CLMA_90_12/Y6AB + td + 0.259 + 14.752 + r + u_ov5640/coms2_reg_config/u1/N267_37_muxf6/F + + + + net (fanout=1) + 0.258 + 15.010 + + u_ov5640/coms2_reg_config/u1/N267 + + + CLMA_90_13/A4 + + + + r + u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_L5Q_perm/L4 + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_20k (rising edge) + + 50000.000 + 50000.000 + r + + + + P20 + + 0.000 + 50000.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 50000.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 50001.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 50001.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 50001.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 50002.688 + + _N69 + + + PLL_158_55/CLK_OUT3 + td + 0.105 + 50002.793 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT3 + + + + net (fanout=1) + 1.059 + 50003.852 + + clk_25m + + + USCM_84_114/CLK_USCM + td + 0.000 + 50003.852 + r + clkbufg_8/gopclkbufg/CLKOUT + + + + net (fanout=26) + 1.531 + 50005.383 + + ntclkbufg_8 + + + CLMA_122_12/Q1 + tco + 0.229 + 50005.612 + r + u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q + + + + net (fanout=3) + 2.115 + 50007.727 + + u_ov5640/coms2_reg_config/clk_20k_regdiv + + + USCM_84_121/CLK_USCM + td + 0.000 + 50007.727 + r + u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + + + + net (fanout=19) + 1.531 + 50009.258 + + u_ov5640/coms2_reg_config/clock_20k + + + CLMA_90_13/CLK + + + + r + u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_L5Q_perm/CLK + + + clock pessimism + + 0.816 + 50010.074 + + + + + clock uncertainty + + -0.050 + 50010.024 + + + + + Setup time + + -0.121 + 50009.903 + + + +
+
+
+
+ + 49995.537 + 1 + 1 + u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0] + u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I3 + + clk_20k + clk_20k + rise-rise + -0.036 + 10.251 + 9.367 + 0.848 + 50000.000 + 4.183 + 2.934 (70.1%) + 1.249 (29.9%) + + Path #42: setup slack is 49995.537(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_20k (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT3 + td + 0.111 + 3.214 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT3 + + + + net (fanout=1) + 1.078 + 4.292 + + clk_25m + + + USCM_84_114/CLK_USCM + td + 0.000 + 4.292 + r + clkbufg_8/gopclkbufg/CLKOUT + + + + net (fanout=26) + 1.585 + 5.877 + + ntclkbufg_8 + + + CLMS_122_9/Q1 + tco + 0.291 + 6.168 + r + u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q + + + + net (fanout=3) + 2.498 + 8.666 + + u_ov5640/coms1_reg_config/clk_20k_regdiv + + + USCM_84_120/CLK_USCM + td + 0.000 + 8.666 + r + u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + + + + net (fanout=19) + 1.585 + 10.251 + + u_ov5640/coms1_reg_config/clock_20k + + + DRM_142_4/CLKB[0] + + + + r + u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0] + + + DRM_142_4/QA0[9] + tco + 2.331 + 12.582 + r + u_ov5640/coms1_reg_config/reg_data/iGopDrm/QA0[9] + + + + net (fanout=1) + 0.664 + 13.246 + + u_ov5640/coms1_reg_config/i2c_data [8] + + + CLMA_146_8/Y1 + td + 0.603 + 13.849 + r + u_ov5640/coms1_reg_config/u1/N267_18_muxf7/F + + + + net (fanout=1) + 0.585 + 14.434 + + u_ov5640/coms1_reg_config/u1/_N25300 + + + CLMA_138_9/A0 + + + + r + u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I3 + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_20k (rising edge) + + 50000.000 + 50000.000 + r + + + + P20 + + 0.000 + 50000.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 50000.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 50001.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 50001.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 50001.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 50002.688 + + _N69 + + + PLL_158_55/CLK_OUT3 + td + 0.105 + 50002.793 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT3 + + + + net (fanout=1) + 1.059 + 50003.852 + + clk_25m + + + USCM_84_114/CLK_USCM + td + 0.000 + 50003.852 + r + clkbufg_8/gopclkbufg/CLKOUT + + + + net (fanout=26) + 1.531 + 50005.383 + + ntclkbufg_8 + + + CLMS_122_9/Q1 + tco + 0.229 + 50005.612 + r + u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q + + + + net (fanout=3) + 2.224 + 50007.836 + + u_ov5640/coms1_reg_config/clk_20k_regdiv + + + USCM_84_120/CLK_USCM + td + 0.000 + 50007.836 + r + u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + + + + net (fanout=19) + 1.531 + 50009.367 + + u_ov5640/coms1_reg_config/clock_20k + + + CLMA_138_9/CLK + + + + r + u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/CLK + + + clock pessimism + + 0.848 + 50010.215 + + + + + clock uncertainty + + -0.050 + 50010.165 + + + + + Setup time + + -0.194 + 50009.971 + + + +
+
+
+
+ + + + Slack + Logic Levels + High Fanout + Start Point + End Point + Exception + Launch Clock + Capture Clock + Clock Edges + Clock Skew + Launch Clock Delay + Capture Clock Delay + Clock Pessimism Removal + Requirement + Data delay + Logic delay + Route delay + + + 0.157 + 0 + 3 + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[30]/opit_0/CLK + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][6]/opit_0/D + + eth_rxc + eth_rxc + rise-rise + 0.036 + 8.567 + 10.153 + -1.550 + 0.000 + 0.446 + 0.222 (49.8%) + 0.224 (50.2%) + + Path #1: hold slack is 0.157(MET) + +
+ + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock eth_rxc (rising edge) + + 0.000 + 0.000 + r + + + + F14 + + 0.000 + 0.000 + r + eth_rxc (port) + + + + net (fanout=1) + 0.057 + 0.057 + + eth_rxc + + + IOBD_240_376/DIN + td + 1.047 + 1.104 + r + eth_rxc_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.104 + + eth_rxc_ibuf/ntD + + + IOL_243_374/INCK + td + 0.048 + 1.152 + r + eth_rxc_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.636 + 1.788 + + _N66 + + + IOCKDLY_237_367/CLK_OUT + td + 2.574 + 4.362 + r + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT + + + + net (fanout=1) + 2.553 + 6.915 + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf + + + USCM_84_109/CLK_USCM + td + 0.000 + 6.915 + r + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT + + + + net (fanout=1862) + 1.652 + 8.567 + + gmii_clk + + + CLMA_194_288/CLK + + + + r + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[30]/opit_0/CLK + + + CLMA_194_288/Q0 + tco + 0.222 + 8.789 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[30]/opit_0/Q + + + + net (fanout=3) + 0.224 + 9.013 + + udp_osd_inst/eth_udp_inst/des_ip [30] + + + CLMA_198_288/AD + + + + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][6]/opit_0/D + +
+ + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock eth_rxc (rising edge) + + 0.000 + 0.000 + r + + + + F14 + + 0.000 + 0.000 + r + eth_rxc (port) + + + + net (fanout=1) + 0.057 + 0.057 + + eth_rxc + + + IOBD_240_376/DIN + td + 1.254 + 1.311 + r + eth_rxc_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.311 + + eth_rxc_ibuf/ntD + + + IOL_243_374/INCK + td + 0.076 + 1.387 + r + eth_rxc_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.647 + 2.034 + + _N66 + + + IOCKDLY_237_367/CLK_OUT + td + 3.812 + 5.846 + r + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT + + + + net (fanout=1) + 2.599 + 8.445 + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf + + + USCM_84_109/CLK_USCM + td + 0.000 + 8.445 + r + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT + + + + net (fanout=1862) + 1.708 + 10.153 + + gmii_clk + + + CLMA_198_288/CLK + + + + r + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][6]/opit_0/CLK + + + clock pessimism + + -1.550 + 8.603 + + + + + clock uncertainty + + 0.200 + 8.803 + + + + + Hold time + + 0.053 + 8.856 + + + +
+
+ +
+ + 0.161 + 0 + 2 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[16]/opit_0_inv/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_21/ram16x1d/WD + + ddrphy_clkin + ddrphy_clkin + rise-rise + 0.036 + 10.665 + 11.394 + -0.693 + 0.000 + 0.577 + 0.222 (38.5%) + 0.355 (61.5%) + + Path #2: hold slack is 0.161(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ddrphy_clkin (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.096 + 2.784 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.059 + 3.843 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 3.843 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.665 + 5.508 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.123 + 5.631 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.102 + 6.733 + + clkout0_wl_0 + + + IOCKGATE_6_322/OUT + td + 0.249 + 6.982 + r + clkgate_9/gopclkgate/OUT + + + + net (fanout=1) + 0.000 + 6.982 + + ntclkgate_0 + + + IOCKDIV_6_323/CLK_IODIV + td + 0.000 + 6.982 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + + + + net (fanout=1) + 2.152 + 9.134 + + u_axi_ddr_top/clk + + + USCM_84_116/CLK_USCM + td + 0.000 + 9.134 + r + clkbufg_0/gopclkbufg/CLKOUT + + + + net (fanout=5464) + 1.531 + 10.665 + + ntclkbufg_0 + + + CLMA_50_96/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[16]/opit_0_inv/CLK + + + CLMA_50_96/Q0 + tco + 0.222 + 10.887 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[16]/opit_0_inv/Q + + + + net (fanout=2) + 0.355 + 11.242 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/dcd_wr_addr [16] + + + CLMS_34_97/AD + + + + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_21/ram16x1d/WD + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ddrphy_clkin (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.101 + 3.204 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.078 + 4.282 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 4.282 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.738 + 6.020 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.129 + 6.149 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.121 + 7.270 + + clkout0_wl_0 + + + IOCKGATE_6_322/OUT + td + 0.348 + 7.618 + r + clkgate_9/gopclkgate/OUT + + + + net (fanout=1) + 0.000 + 7.618 + + ntclkgate_0 + + + IOCKDIV_6_323/CLK_IODIV + td + 0.000 + 7.618 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + + + + net (fanout=1) + 2.191 + 9.809 + + u_axi_ddr_top/clk + + + USCM_84_116/CLK_USCM + td + 0.000 + 9.809 + r + clkbufg_0/gopclkbufg/CLKOUT + + + + net (fanout=5464) + 1.585 + 11.394 + + ntclkbufg_0 + + + CLMS_34_97/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_21/ram16x1d/WCLK + + + clock pessimism + + -0.693 + 10.701 + + + + + clock uncertainty + + 0.000 + 10.701 + + + + + Hold time + + 0.380 + 11.081 + + + +
+
+
+
+ + 0.164 + 0 + 2 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[12]/opit_0_inv/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_17/ram16x1d/WD + + ddrphy_clkin + ddrphy_clkin + rise-rise + 0.022 + 10.721 + 11.436 + -0.693 + 0.000 + 0.566 + 0.224 (39.6%) + 0.342 (60.4%) + + Path #3: hold slack is 0.164(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ddrphy_clkin (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.096 + 2.784 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.059 + 3.843 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 3.843 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.665 + 5.508 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.123 + 5.631 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.102 + 6.733 + + clkout0_wl_0 + + + IOCKGATE_6_322/OUT + td + 0.249 + 6.982 + r + clkgate_9/gopclkgate/OUT + + + + net (fanout=1) + 0.000 + 6.982 + + ntclkgate_0 + + + IOCKDIV_6_323/CLK_IODIV + td + 0.000 + 6.982 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + + + + net (fanout=1) + 2.152 + 9.134 + + u_axi_ddr_top/clk + + + USCM_84_116/CLK_USCM + td + 0.000 + 9.134 + r + clkbufg_0/gopclkbufg/CLKOUT + + + + net (fanout=5464) + 1.587 + 10.721 + + ntclkbufg_0 + + + CLMS_42_85/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[12]/opit_0_inv/CLK + + + CLMS_42_85/Q1 + tco + 0.224 + 10.945 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[12]/opit_0_inv/Q + + + + net (fanout=2) + 0.342 + 11.287 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/dcd_wr_addr [12] + + + CLMS_38_81/DD + + + + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_17/ram16x1d/WD + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ddrphy_clkin (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.101 + 3.204 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.078 + 4.282 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 4.282 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.738 + 6.020 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.129 + 6.149 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.121 + 7.270 + + clkout0_wl_0 + + + IOCKGATE_6_322/OUT + td + 0.348 + 7.618 + r + clkgate_9/gopclkgate/OUT + + + + net (fanout=1) + 0.000 + 7.618 + + ntclkgate_0 + + + IOCKDIV_6_323/CLK_IODIV + td + 0.000 + 7.618 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + + + + net (fanout=1) + 2.191 + 9.809 + + u_axi_ddr_top/clk + + + USCM_84_116/CLK_USCM + td + 0.000 + 9.809 + r + clkbufg_0/gopclkbufg/CLKOUT + + + + net (fanout=5464) + 1.627 + 11.436 + + ntclkbufg_0 + + + CLMS_38_81/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_17/ram16x1d/WCLK + + + clock pessimism + + -0.693 + 10.743 + + + + + clock uncertainty + + 0.000 + 10.743 + + + + + Hold time + + 0.380 + 11.123 + + + +
+
+
+
+ + 0.172 + 0 + 44 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_15/ram16x1d/WADM0 + + ddrphy_clkin + ddrphy_clkin + rise-rise + 0.062 + 10.691 + 11.446 + -0.693 + 0.000 + 0.614 + 0.222 (36.2%) + 0.392 (63.8%) + + Path #4: hold slack is 0.172(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ddrphy_clkin (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.096 + 2.784 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.059 + 3.843 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 3.843 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.665 + 5.508 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.123 + 5.631 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.102 + 6.733 + + clkout0_wl_0 + + + IOCKGATE_6_322/OUT + td + 0.249 + 6.982 + r + clkgate_9/gopclkgate/OUT + + + + net (fanout=1) + 0.000 + 6.982 + + ntclkgate_0 + + + IOCKDIV_6_323/CLK_IODIV + td + 0.000 + 6.982 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + + + + net (fanout=1) + 2.152 + 9.134 + + u_axi_ddr_top/clk + + + USCM_84_116/CLK_USCM + td + 0.000 + 9.134 + r + clkbufg_0/gopclkbufg/CLKOUT + + + + net (fanout=5464) + 1.557 + 10.691 + + ntclkbufg_0 + + + CLMA_34_76/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK + + + CLMA_34_76/Q0 + tco + 0.222 + 10.913 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/Q0 + + + + net (fanout=44) + 0.392 + 11.305 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [0] + + + CLMS_42_81/M0 + + + + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_15/ram16x1d/WADM0 + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ddrphy_clkin (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.101 + 3.204 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.078 + 4.282 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 4.282 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.738 + 6.020 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.129 + 6.149 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.121 + 7.270 + + clkout0_wl_0 + + + IOCKGATE_6_322/OUT + td + 0.348 + 7.618 + r + clkgate_9/gopclkgate/OUT + + + + net (fanout=1) + 0.000 + 7.618 + + ntclkgate_0 + + + IOCKDIV_6_323/CLK_IODIV + td + 0.000 + 7.618 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + + + + net (fanout=1) + 2.191 + 9.809 + + u_axi_ddr_top/clk + + + USCM_84_116/CLK_USCM + td + 0.000 + 9.809 + r + clkbufg_0/gopclkbufg/CLKOUT + + + + net (fanout=5464) + 1.637 + 11.446 + + ntclkbufg_0 + + + CLMS_42_81/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_15/ram16x1d/WCLK + + + clock pessimism + + -0.693 + 10.753 + + + + + clock uncertainty + + 0.000 + 10.753 + + + + + Hold time + + 0.380 + 11.133 + + + +
+
+
+
+ + 0.175 + 0 + 5 + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/L0 + + cmos1_pclk + cmos1_pclk + rise-rise + 0.029 + 5.188 + 5.521 + -0.304 + 0.000 + 0.310 + 0.222 (71.6%) + 0.088 (28.4%) + + Path #5: hold slack is 0.175(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock cmos1_pclk (rising edge) + + 0.000 + 0.000 + r + + + + T12 + + 0.000 + 0.000 + r + cmos1_pclk (port) + + + + net (fanout=1) + 0.076 + 0.076 + + cmos1_pclk + + + IOBD_169_0/DIN + td + 1.047 + 1.123 + r + cmos1_pclk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.123 + + cmos1_pclk_ibuf/ntD + + + IOL_171_6/INCK + td + 0.048 + 1.171 + r + cmos1_pclk_ibuf/opit_1/INCK + + + + net (fanout=1) + 2.486 + 3.657 + + _N64 + + + USCM_84_112/CLK_USCM + td + 0.000 + 3.657 + r + clkbufg_6/gopclkbufg/CLKOUT + + + + net (fanout=118) + 1.531 + 5.188 + + ntclkbufg_6 + + + CLMA_138_60/CLK + + + + r + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK + + + CLMA_138_60/Q0 + tco + 0.222 + 5.410 + f + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/Q0 + + + + net (fanout=5) + 0.088 + 5.498 + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/wr_addr [8] + + + CLMA_138_61/A0 + + + + f + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/L0 + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock cmos1_pclk (rising edge) + + 0.000 + 0.000 + r + + + + T12 + + 0.000 + 0.000 + r + cmos1_pclk (port) + + + + net (fanout=1) + 0.076 + 0.076 + + cmos1_pclk + + + IOBD_169_0/DIN + td + 1.254 + 1.330 + r + cmos1_pclk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.330 + + cmos1_pclk_ibuf/ntD + + + IOL_171_6/INCK + td + 0.076 + 1.406 + r + cmos1_pclk_ibuf/opit_1/INCK + + + + net (fanout=1) + 2.530 + 3.936 + + _N64 + + + USCM_84_112/CLK_USCM + td + 0.000 + 3.936 + r + clkbufg_6/gopclkbufg/CLKOUT + + + + net (fanout=118) + 1.585 + 5.521 + + ntclkbufg_6 + + + CLMA_138_61/CLK + + + + r + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/CLK + + + clock pessimism + + -0.304 + 5.217 + + + + + clock uncertainty + + 0.200 + 5.417 + + + + + Hold time + + -0.094 + 5.323 + + + +
+
+
+
+ + 0.177 + 0 + 5 + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/L0 + + cmos1_pclk + cmos1_pclk + rise-rise + 0.029 + 5.188 + 5.521 + -0.304 + 0.000 + 0.313 + 0.224 (71.6%) + 0.089 (28.4%) + + Path #6: hold slack is 0.177(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock cmos1_pclk (rising edge) + + 0.000 + 0.000 + r + + + + T12 + + 0.000 + 0.000 + r + cmos1_pclk (port) + + + + net (fanout=1) + 0.076 + 0.076 + + cmos1_pclk + + + IOBD_169_0/DIN + td + 1.047 + 1.123 + r + cmos1_pclk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.123 + + cmos1_pclk_ibuf/ntD + + + IOL_171_6/INCK + td + 0.048 + 1.171 + r + cmos1_pclk_ibuf/opit_1/INCK + + + + net (fanout=1) + 2.486 + 3.657 + + _N64 + + + USCM_84_112/CLK_USCM + td + 0.000 + 3.657 + r + clkbufg_6/gopclkbufg/CLKOUT + + + + net (fanout=118) + 1.531 + 5.188 + + ntclkbufg_6 + + + CLMA_138_56/CLK + + + + r + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK + + + CLMA_138_56/Q1 + tco + 0.224 + 5.412 + f + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/Q1 + + + + net (fanout=5) + 0.089 + 5.501 + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/wr_addr [5] + + + CLMA_138_57/C0 + + + + f + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/L0 + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock cmos1_pclk (rising edge) + + 0.000 + 0.000 + r + + + + T12 + + 0.000 + 0.000 + r + cmos1_pclk (port) + + + + net (fanout=1) + 0.076 + 0.076 + + cmos1_pclk + + + IOBD_169_0/DIN + td + 1.254 + 1.330 + r + cmos1_pclk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.330 + + cmos1_pclk_ibuf/ntD + + + IOL_171_6/INCK + td + 0.076 + 1.406 + r + cmos1_pclk_ibuf/opit_1/INCK + + + + net (fanout=1) + 2.530 + 3.936 + + _N64 + + + USCM_84_112/CLK_USCM + td + 0.000 + 3.936 + r + clkbufg_6/gopclkbufg/CLKOUT + + + + net (fanout=118) + 1.585 + 5.521 + + ntclkbufg_6 + + + CLMA_138_57/CLK + + + + r + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/CLK + + + clock pessimism + + -0.304 + 5.217 + + + + + clock uncertainty + + 0.200 + 5.417 + + + + + Hold time + + -0.093 + 5.324 + + + +
+
+
+
+ + 0.189 + 0 + 3 + u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[2]/opit_0_L5Q_perm/CLK + u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[3]/opit_0_L5Q_perm/L0 + + hdmi_in_clk + hdmi_in_clk + rise-rise + 0.000 + 5.951 + 6.435 + -0.484 + 0.000 + 0.310 + 0.224 (72.3%) + 0.086 (27.7%) + + Path #7: hold slack is 0.189(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock hdmi_in_clk (rising edge) + + 0.000 + 0.000 + r + + + + AA12 + + 0.000 + 0.000 + r + hdmi_in_clk (port) + + + + net (fanout=1) + 0.078 + 0.078 + + hdmi_in_clk + + + IOBD_161_0/DIN + td + 1.808 + 1.886 + r + hdmi_in_clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.886 + + hdmi_in_clk_ibuf/ntD + + + IOL_163_6/INCK + td + 0.048 + 1.934 + r + hdmi_in_clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 2.486 + 4.420 + + _N37 + + + USCM_84_111/CLK_USCM + td + 0.000 + 4.420 + r + clkbufg_5/gopclkbufg/CLKOUT + + + + net (fanout=167) + 1.531 + 5.951 + + ntclkbufg_5 + + + CLMA_122_92/CLK + + + + r + u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[2]/opit_0_L5Q_perm/CLK + + + CLMA_122_92/Q2 + tco + 0.224 + 6.175 + f + u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[2]/opit_0_L5Q_perm/Q + + + + net (fanout=3) + 0.086 + 6.261 + + u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt [2] + + + CLMA_122_92/D0 + + + + f + u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[3]/opit_0_L5Q_perm/L0 + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock hdmi_in_clk (rising edge) + + 0.000 + 0.000 + r + + + + AA12 + + 0.000 + 0.000 + r + hdmi_in_clk (port) + + + + net (fanout=1) + 0.078 + 0.078 + + hdmi_in_clk + + + IOBD_161_0/DIN + td + 2.166 + 2.244 + r + hdmi_in_clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.244 + + hdmi_in_clk_ibuf/ntD + + + IOL_163_6/INCK + td + 0.076 + 2.320 + r + hdmi_in_clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 2.530 + 4.850 + + _N37 + + + USCM_84_111/CLK_USCM + td + 0.000 + 4.850 + r + clkbufg_5/gopclkbufg/CLKOUT + + + + net (fanout=167) + 1.585 + 6.435 + + ntclkbufg_5 + + + CLMA_122_92/CLK + + + + r + u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[3]/opit_0_L5Q_perm/CLK + + + clock pessimism + + -0.484 + 5.951 + + + + + clock uncertainty + + 0.200 + 6.151 + + + + + Hold time + + -0.079 + 6.072 + + + +
+
+
+
+ + 0.190 + 0 + 6 + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/L1 + + hdmi_in_clk + hdmi_in_clk + rise-rise + 0.029 + 5.951 + 6.435 + -0.455 + 0.000 + 0.313 + 0.224 (71.6%) + 0.089 (28.4%) + + Path #8: hold slack is 0.190(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock hdmi_in_clk (rising edge) + + 0.000 + 0.000 + r + + + + AA12 + + 0.000 + 0.000 + r + hdmi_in_clk (port) + + + + net (fanout=1) + 0.078 + 0.078 + + hdmi_in_clk + + + IOBD_161_0/DIN + td + 1.808 + 1.886 + r + hdmi_in_clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.886 + + hdmi_in_clk_ibuf/ntD + + + IOL_163_6/INCK + td + 0.048 + 1.934 + r + hdmi_in_clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 2.486 + 4.420 + + _N37 + + + USCM_84_111/CLK_USCM + td + 0.000 + 4.420 + r + clkbufg_5/gopclkbufg/CLKOUT + + + + net (fanout=167) + 1.531 + 5.951 + + ntclkbufg_5 + + + CLMA_90_105/CLK + + + + r + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK + + + CLMA_90_105/Q1 + tco + 0.224 + 6.175 + f + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/Q1 + + + + net (fanout=6) + 0.089 + 6.264 + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/wr_addr [5] + + + CLMA_90_104/D1 + + + + f + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/L1 + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock hdmi_in_clk (rising edge) + + 0.000 + 0.000 + r + + + + AA12 + + 0.000 + 0.000 + r + hdmi_in_clk (port) + + + + net (fanout=1) + 0.078 + 0.078 + + hdmi_in_clk + + + IOBD_161_0/DIN + td + 2.166 + 2.244 + r + hdmi_in_clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.244 + + hdmi_in_clk_ibuf/ntD + + + IOL_163_6/INCK + td + 0.076 + 2.320 + r + hdmi_in_clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 2.530 + 4.850 + + _N37 + + + USCM_84_111/CLK_USCM + td + 0.000 + 4.850 + r + clkbufg_5/gopclkbufg/CLKOUT + + + + net (fanout=167) + 1.585 + 6.435 + + ntclkbufg_5 + + + CLMA_90_104/CLK + + + + r + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK + + + clock pessimism + + -0.455 + 5.980 + + + + + clock uncertainty + + 0.200 + 6.180 + + + + + Hold time + + -0.106 + 6.074 + + + +
+
+
+
+ + 0.192 + 0 + 5 + u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[2]/opit_0_L5Q_perm/CLK + u_ddr_addr_ctr/u_wr1_addr_ctr/wr_vs_flag/opit_0_L5Q_perm/L0 + + hdmi_in_clk + hdmi_in_clk + rise-rise + 0.000 + 5.951 + 6.435 + -0.484 + 0.000 + 0.313 + 0.224 (71.6%) + 0.089 (28.4%) + + Path #9: hold slack is 0.192(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock hdmi_in_clk (rising edge) + + 0.000 + 0.000 + r + + + + AA12 + + 0.000 + 0.000 + r + hdmi_in_clk (port) + + + + net (fanout=1) + 0.078 + 0.078 + + hdmi_in_clk + + + IOBD_161_0/DIN + td + 1.808 + 1.886 + r + hdmi_in_clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.886 + + hdmi_in_clk_ibuf/ntD + + + IOL_163_6/INCK + td + 0.048 + 1.934 + r + hdmi_in_clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 2.486 + 4.420 + + _N37 + + + USCM_84_111/CLK_USCM + td + 0.000 + 4.420 + r + clkbufg_5/gopclkbufg/CLKOUT + + + + net (fanout=167) + 1.531 + 5.951 + + ntclkbufg_5 + + + CLMS_118_93/CLK + + + + r + u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[2]/opit_0_L5Q_perm/CLK + + + CLMS_118_93/Q2 + tco + 0.224 + 6.175 + f + u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[2]/opit_0_L5Q_perm/Q + + + + net (fanout=5) + 0.089 + 6.264 + + u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg [2] + + + CLMS_118_93/D0 + + + + f + u_ddr_addr_ctr/u_wr1_addr_ctr/wr_vs_flag/opit_0_L5Q_perm/L0 + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock hdmi_in_clk (rising edge) + + 0.000 + 0.000 + r + + + + AA12 + + 0.000 + 0.000 + r + hdmi_in_clk (port) + + + + net (fanout=1) + 0.078 + 0.078 + + hdmi_in_clk + + + IOBD_161_0/DIN + td + 2.166 + 2.244 + r + hdmi_in_clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.244 + + hdmi_in_clk_ibuf/ntD + + + IOL_163_6/INCK + td + 0.076 + 2.320 + r + hdmi_in_clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 2.530 + 4.850 + + _N37 + + + USCM_84_111/CLK_USCM + td + 0.000 + 4.850 + r + clkbufg_5/gopclkbufg/CLKOUT + + + + net (fanout=167) + 1.585 + 6.435 + + ntclkbufg_5 + + + CLMS_118_93/CLK + + + + r + u_ddr_addr_ctr/u_wr1_addr_ctr/wr_vs_flag/opit_0_L5Q_perm/CLK + + + clock pessimism + + -0.484 + 5.951 + + + + + clock uncertainty + + 0.200 + 6.151 + + + + + Hold time + + -0.079 + 6.072 + + + +
+
+
+
+ + 0.193 + 0 + 1 + u_ov5640/cmos1_8_16bit/pdata_i2[4]/opit_0/CLK + u_ov5640/cmos1_8_16bit/image_data0[12]/opit_0/D + + cmos1_pclk + cmos1_pclk + rise-rise + 0.029 + 5.188 + 5.521 + -0.304 + 0.000 + 0.475 + 0.284 (59.8%) + 0.191 (40.2%) + + Path #10: hold slack is 0.193(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock cmos1_pclk (rising edge) + + 0.000 + 0.000 + r + + + + T12 + + 0.000 + 0.000 + r + cmos1_pclk (port) + + + + net (fanout=1) + 0.076 + 0.076 + + cmos1_pclk + + + IOBD_169_0/DIN + td + 1.047 + 1.123 + r + cmos1_pclk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.123 + + cmos1_pclk_ibuf/ntD + + + IOL_171_6/INCK + td + 0.048 + 1.171 + r + cmos1_pclk_ibuf/opit_1/INCK + + + + net (fanout=1) + 2.486 + 3.657 + + _N64 + + + USCM_84_112/CLK_USCM + td + 0.000 + 3.657 + r + clkbufg_6/gopclkbufg/CLKOUT + + + + net (fanout=118) + 1.531 + 5.188 + + ntclkbufg_6 + + + CLMA_138_44/CLK + + + + r + u_ov5640/cmos1_8_16bit/pdata_i2[4]/opit_0/CLK + + + CLMA_138_44/Y0 + tco + 0.284 + 5.472 + f + u_ov5640/cmos1_8_16bit/pdata_i2[4]/opit_0/Q + + + + net (fanout=1) + 0.191 + 5.663 + + u_ov5640/cmos1_8_16bit/pdata_i2 [4] + + + CLMA_138_45/AD + + + + f + u_ov5640/cmos1_8_16bit/image_data0[12]/opit_0/D + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock cmos1_pclk (rising edge) + + 0.000 + 0.000 + r + + + + T12 + + 0.000 + 0.000 + r + cmos1_pclk (port) + + + + net (fanout=1) + 0.076 + 0.076 + + cmos1_pclk + + + IOBD_169_0/DIN + td + 1.254 + 1.330 + r + cmos1_pclk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.330 + + cmos1_pclk_ibuf/ntD + + + IOL_171_6/INCK + td + 0.076 + 1.406 + r + cmos1_pclk_ibuf/opit_1/INCK + + + + net (fanout=1) + 2.530 + 3.936 + + _N64 + + + USCM_84_112/CLK_USCM + td + 0.000 + 3.936 + r + clkbufg_6/gopclkbufg/CLKOUT + + + + net (fanout=118) + 1.585 + 5.521 + + ntclkbufg_6 + + + CLMA_138_45/CLK + + + + r + u_ov5640/cmos1_8_16bit/image_data0[12]/opit_0/CLK + + + clock pessimism + + -0.304 + 5.217 + + + + + clock uncertainty + + 0.200 + 5.417 + + + + + Hold time + + 0.053 + 5.470 + + + +
+
+
+
+ + 0.201 + 0 + 5 + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[10] + + clk_50m + clk_50m + rise-rise + 0.036 + 5.378 + 5.873 + -0.459 + 0.000 + 0.447 + 0.222 (49.7%) + 0.225 (50.3%) + + Path #11: hold slack is 0.201(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_50m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.100 + 2.788 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.059 + 3.847 + + rd3_clk + + + USCM_84_108/CLK_USCM + td + 0.000 + 3.847 + r + clkbufg_1/gopclkbufg/CLKOUT + + + + net (fanout=2516) + 1.531 + 5.378 + + ntclkbufg_1 + + + CLMS_50_117/CLK + + + + r + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK + + + CLMS_50_117/Q0 + tco + 0.222 + 5.600 + f + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/Q0 + + + + net (fanout=5) + 0.225 + 5.825 + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/wr_addr [8] + + + DRM_54_108/ADA0[10] + + + + f + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[10] + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_50m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.107 + 3.210 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.078 + 4.288 + + rd3_clk + + + USCM_84_108/CLK_USCM + td + 0.000 + 4.288 + r + clkbufg_1/gopclkbufg/CLKOUT + + + + net (fanout=2516) + 1.585 + 5.873 + + ntclkbufg_1 + + + DRM_54_108/CLKA[0] + + + + r + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKA + + + clock pessimism + + -0.459 + 5.414 + + + + + clock uncertainty + + 0.000 + 5.414 + + + + + Hold time + + 0.210 + 5.624 + + + +
+
+
+
+ + 0.212 + 0 + 3 + u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK + u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[7] + + clk_1080p60Hz + clk_1080p60Hz + rise-rise + 0.036 + 8.835 + 9.440 + -0.569 + 0.000 + 0.458 + 0.224 (48.9%) + 0.234 (51.1%) + + Path #12: hold slack is 0.212(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_1080p60Hz (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.100 + 2.788 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.059 + 3.847 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 3.847 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.786 + 5.633 + + ntR3950 + + + PLL_158_303/CLK_OUT0 + td + 0.100 + 5.733 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=1) + 1.571 + 7.304 + + zoom_clk + + + USCM_84_118/CLK_USCM + td + 0.000 + 7.304 + r + clkbufg_3/gopclkbufg/CLKOUT + + + + net (fanout=750) + 1.531 + 8.835 + + ntclkbufg_3 + + + CLMA_146_76/CLK + + + + r + u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK + + + CLMA_146_76/Q2 + tco + 0.224 + 9.059 + f + u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/Q0 + + + + net (fanout=3) + 0.234 + 9.293 + + u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/wr_addr [2] + + + DRM_142_68/ADA0[7] + + + + f + u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[7] + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_1080p60Hz (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.107 + 3.210 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.078 + 4.288 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 4.288 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.861 + 6.149 + + ntR3950 + + + PLL_158_303/CLK_OUT0 + td + 0.107 + 6.256 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=1) + 1.599 + 7.855 + + zoom_clk + + + USCM_84_118/CLK_USCM + td + 0.000 + 7.855 + r + clkbufg_3/gopclkbufg/CLKOUT + + + + net (fanout=750) + 1.585 + 9.440 + + ntclkbufg_3 + + + DRM_142_68/CLKA[0] + + + + r + u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKA + + + clock pessimism + + -0.569 + 8.871 + + + + + clock uncertainty + + 0.000 + 8.871 + + + + + Hold time + + 0.210 + 9.081 + + + +
+
+
+
+ + 0.226 + 0 + 1 + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/D + + clk_50m + clk_50m + rise-rise + 0.029 + 5.378 + 5.873 + -0.466 + 0.000 + 0.308 + 0.224 (72.7%) + 0.084 (27.3%) + + Path #13: hold slack is 0.226(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_50m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.100 + 2.788 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.059 + 3.847 + + rd3_clk + + + USCM_84_108/CLK_USCM + td + 0.000 + 3.847 + r + clkbufg_1/gopclkbufg/CLKOUT + + + + net (fanout=2516) + 1.531 + 5.378 + + ntclkbufg_1 + + + CLMA_58_108/CLK + + + + r + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK + + + CLMA_58_108/Q2 + tco + 0.224 + 5.602 + f + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/Q + + + + net (fanout=1) + 0.084 + 5.686 + + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr1 [2] + + + CLMA_58_109/CD + + + + f + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/D + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_50m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.107 + 3.210 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.078 + 4.288 + + rd3_clk + + + USCM_84_108/CLK_USCM + td + 0.000 + 4.288 + r + clkbufg_1/gopclkbufg/CLKOUT + + + + net (fanout=2516) + 1.585 + 5.873 + + ntclkbufg_1 + + + CLMA_58_109/CLK + + + + r + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK + + + clock pessimism + + -0.466 + 5.407 + + + + + clock uncertainty + + 0.000 + 5.407 + + + + + Hold time + + 0.053 + 5.460 + + + +
+
+
+
+ + 0.231 + 0 + 4 + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[2] + + clk_50m + clk_50m + rise-rise + 0.023 + 5.421 + 5.903 + -0.459 + 0.000 + 0.440 + 0.222 (50.5%) + 0.218 (49.5%) + + Path #14: hold slack is 0.231(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_50m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.100 + 2.788 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.059 + 3.847 + + rd3_clk + + + USCM_84_108/CLK_USCM + td + 0.000 + 3.847 + r + clkbufg_1/gopclkbufg/CLKOUT + + + + net (fanout=2516) + 1.574 + 5.421 + + ntclkbufg_1 + + + CLMA_50_32/CLK + + + + r + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK + + + CLMA_50_32/Q0 + tco + 0.222 + 5.643 + f + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Q0 + + + + net (fanout=4) + 0.218 + 5.861 + + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/wr_addr [0] + + + DRM_54_24/ADA0[2] + + + + f + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[2] + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_50m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.107 + 3.210 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.078 + 4.288 + + rd3_clk + + + USCM_84_108/CLK_USCM + td + 0.000 + 4.288 + r + clkbufg_1/gopclkbufg/CLKOUT + + + + net (fanout=2516) + 1.615 + 5.903 + + ntclkbufg_1 + + + DRM_54_24/CLKA[0] + + + + r + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKA + + + clock pessimism + + -0.459 + 5.444 + + + + + clock uncertainty + + 0.000 + 5.444 + + + + + Hold time + + 0.186 + 5.630 + + + +
+
+
+
+ + 0.248 + 0 + 6 + u_zoom_image/wr_addr1[2]/opit_0_inv_A2Q21/CLK + u_zoom_image/zoom_ram1_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/ADA0[5] + + clk_1080p60Hz + clk_1080p60Hz + rise-rise + 0.036 + 8.835 + 9.440 + -0.569 + 0.000 + 0.445 + 0.224 (50.3%) + 0.221 (49.7%) + + Path #15: hold slack is 0.248(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_1080p60Hz (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.100 + 2.788 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.059 + 3.847 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 3.847 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.786 + 5.633 + + ntR3950 + + + PLL_158_303/CLK_OUT0 + td + 0.100 + 5.733 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=1) + 1.571 + 7.304 + + zoom_clk + + + USCM_84_118/CLK_USCM + td + 0.000 + 7.304 + r + clkbufg_3/gopclkbufg/CLKOUT + + + + net (fanout=750) + 1.531 + 8.835 + + ntclkbufg_3 + + + CLMS_174_177/CLK + + + + r + u_zoom_image/wr_addr1[2]/opit_0_inv_A2Q21/CLK + + + CLMS_174_177/Q1 + tco + 0.224 + 9.059 + f + u_zoom_image/wr_addr1[2]/opit_0_inv_A2Q21/Q1 + + + + net (fanout=6) + 0.221 + 9.280 + + u_zoom_image/wr_addr1 [2] + + + DRM_178_168/ADA0[5] + + + + f + u_zoom_image/zoom_ram1_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/ADA0[5] + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_1080p60Hz (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.107 + 3.210 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.078 + 4.288 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 4.288 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.861 + 6.149 + + ntR3950 + + + PLL_158_303/CLK_OUT0 + td + 0.107 + 6.256 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=1) + 1.599 + 7.855 + + zoom_clk + + + USCM_84_118/CLK_USCM + td + 0.000 + 7.855 + r + clkbufg_3/gopclkbufg/CLKOUT + + + + net (fanout=750) + 1.585 + 9.440 + + ntclkbufg_3 + + + DRM_178_168/CLKA[0] + + + + r + u_zoom_image/zoom_ram1_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] + + + clock pessimism + + -0.569 + 8.871 + + + + + clock uncertainty + + 0.000 + 8.871 + + + + + Hold time + + 0.161 + 9.032 + + + +
+
+
+
+ + 0.252 + 0 + 1 + u_zoom_image/image_valid[2][1]/opit_0/CLK + u_zoom_image/image_valid[3][1]/opit_0/D + + clk_1080p60Hz + clk_1080p60Hz + rise-rise + 0.000 + 8.835 + 9.440 + -0.605 + 0.000 + 0.305 + 0.221 (72.5%) + 0.084 (27.5%) + + Path #16: hold slack is 0.252(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_1080p60Hz (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.100 + 2.788 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.059 + 3.847 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 3.847 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.786 + 5.633 + + ntR3950 + + + PLL_158_303/CLK_OUT0 + td + 0.100 + 5.733 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=1) + 1.571 + 7.304 + + zoom_clk + + + USCM_84_118/CLK_USCM + td + 0.000 + 7.304 + r + clkbufg_3/gopclkbufg/CLKOUT + + + + net (fanout=750) + 1.531 + 8.835 + + ntclkbufg_3 + + + CLMA_210_153/CLK + + + + r + u_zoom_image/image_valid[2][1]/opit_0/CLK + + + CLMA_210_153/Q3 + tco + 0.221 + 9.056 + f + u_zoom_image/image_valid[2][1]/opit_0/Q + + + + net (fanout=1) + 0.084 + 9.140 + + u_zoom_image/image_valid[2] [1] + + + CLMA_210_153/AD + + + + f + u_zoom_image/image_valid[3][1]/opit_0/D + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_1080p60Hz (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.107 + 3.210 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.078 + 4.288 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 4.288 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.861 + 6.149 + + ntR3950 + + + PLL_158_303/CLK_OUT0 + td + 0.107 + 6.256 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=1) + 1.599 + 7.855 + + zoom_clk + + + USCM_84_118/CLK_USCM + td + 0.000 + 7.855 + r + clkbufg_3/gopclkbufg/CLKOUT + + + + net (fanout=750) + 1.585 + 9.440 + + ntclkbufg_3 + + + CLMA_210_153/CLK + + + + r + u_zoom_image/image_valid[3][1]/opit_0/CLK + + + clock pessimism + + -0.605 + 8.835 + + + + + clock uncertainty + + 0.000 + 8.835 + + + + + Hold time + + 0.053 + 8.888 + + + +
+
+
+
+ + 0.287 + 0 + 2 + ms72xx_ctl/iic_dri_tx/receiv_data[5]/opit_0_inv/CLK + ms72xx_ctl/iic_dri_tx/data_out[5]/opit_0/D + + clk_10m + clk_10m + rise-rise + 0.029 + 5.499 + 5.996 + -0.468 + 0.000 + 0.369 + 0.284 (77.0%) + 0.085 (23.0%) + + Path #17: hold slack is 0.287(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_10m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT4 + td + 0.100 + 2.788 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT4 + + + + net (fanout=1) + 1.059 + 3.847 + + clk_10m + + + USCM_84_110/CLK_USCM + td + 0.000 + 3.847 + r + clkbufg_4/gopclkbufg/CLKOUT + + + + net (fanout=235) + 1.652 + 5.499 + + ntclkbufg_4 + + + CLMA_194_305/CLK + + + + r + ms72xx_ctl/iic_dri_tx/receiv_data[5]/opit_0_inv/CLK + + + CLMA_194_305/Y2 + tco + 0.284 + 5.783 + f + ms72xx_ctl/iic_dri_tx/receiv_data[5]/opit_0_inv/Q + + + + net (fanout=2) + 0.085 + 5.868 + + ms72xx_ctl/iic_dri_tx/receiv_data [5] + + + CLMA_194_304/CD + + + + f + ms72xx_ctl/iic_dri_tx/data_out[5]/opit_0/D + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_10m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT4 + td + 0.107 + 3.210 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT4 + + + + net (fanout=1) + 1.078 + 4.288 + + clk_10m + + + USCM_84_110/CLK_USCM + td + 0.000 + 4.288 + r + clkbufg_4/gopclkbufg/CLKOUT + + + + net (fanout=235) + 1.708 + 5.996 + + ntclkbufg_4 + + + CLMA_194_304/CLK + + + + r + ms72xx_ctl/iic_dri_tx/data_out[5]/opit_0/CLK + + + clock pessimism + + -0.468 + 5.528 + + + + + clock uncertainty + + 0.000 + 5.528 + + + + + Hold time + + 0.053 + 5.581 + + + +
+
+
+
+ + 0.314 + 0 + 1 + adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm/CLK + adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm/L4 + + clk_720p60Hz + clk_720p60Hz + rise-rise + 0.029 + 8.831 + 9.434 + -0.574 + 0.000 + 0.308 + 0.224 (72.7%) + 0.084 (27.3%) + + Path #18: hold slack is 0.314(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_720p60Hz (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.100 + 2.788 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.059 + 3.847 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 3.847 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.786 + 5.633 + + ntR3950 + + + PLL_158_303/CLK_OUT1 + td + 0.096 + 5.729 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.571 + 7.300 + + nt_pix_clk + + + USCM_84_117/CLK_USCM + td + 0.000 + 7.300 + r + clkbufg_2/gopclkbufg/CLKOUT + + + + net (fanout=1635) + 1.531 + 8.831 + + ntclkbufg_2 + + + CLMA_250_177/CLK + + + + r + adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm/CLK + + + CLMA_250_177/Q2 + tco + 0.224 + 9.055 + f + adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm/Q + + + + net (fanout=1) + 0.084 + 9.139 + + adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/dividend_t[13] [9] + + + CLMA_250_176/A4 + + + + f + adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm/L4 + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_720p60Hz (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.107 + 3.210 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.078 + 4.288 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 4.288 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.861 + 6.149 + + ntR3950 + + + PLL_158_303/CLK_OUT1 + td + 0.101 + 6.250 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.599 + 7.849 + + nt_pix_clk + + + USCM_84_117/CLK_USCM + td + 0.000 + 7.849 + r + clkbufg_2/gopclkbufg/CLKOUT + + + + net (fanout=1635) + 1.585 + 9.434 + + ntclkbufg_2 + + + CLMA_250_176/CLK + + + + r + adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm/CLK + + + clock pessimism + + -0.574 + 8.860 + + + + + clock uncertainty + + 0.000 + 8.860 + + + + + Hold time + + -0.035 + 8.825 + + + +
+
+
+
+ + 0.314 + 0 + 2 + ms72xx_ctl/iic_dri_tx/receiv_data[1]/opit_0_inv/CLK + ms72xx_ctl/iic_dri_tx/data_out[1]/opit_0/D + + clk_10m + clk_10m + rise-rise + 0.029 + 5.499 + 5.996 + -0.468 + 0.000 + 0.329 + 0.226 (68.7%) + 0.103 (31.3%) + + Path #19: hold slack is 0.314(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_10m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT4 + td + 0.100 + 2.788 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT4 + + + + net (fanout=1) + 1.059 + 3.847 + + clk_10m + + + USCM_84_110/CLK_USCM + td + 0.000 + 3.847 + r + clkbufg_4/gopclkbufg/CLKOUT + + + + net (fanout=235) + 1.652 + 5.499 + + ntclkbufg_4 + + + CLMA_194_305/CLK + + + + r + ms72xx_ctl/iic_dri_tx/receiv_data[1]/opit_0_inv/CLK + + + CLMA_194_305/Q0 + tco + 0.226 + 5.725 + r + ms72xx_ctl/iic_dri_tx/receiv_data[1]/opit_0_inv/Q + + + + net (fanout=2) + 0.103 + 5.828 + + ms72xx_ctl/iic_dri_tx/receiv_data [1] + + + CLMA_194_304/M0 + + + + r + ms72xx_ctl/iic_dri_tx/data_out[1]/opit_0/D + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_10m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT4 + td + 0.107 + 3.210 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT4 + + + + net (fanout=1) + 1.078 + 4.288 + + clk_10m + + + USCM_84_110/CLK_USCM + td + 0.000 + 4.288 + r + clkbufg_4/gopclkbufg/CLKOUT + + + + net (fanout=235) + 1.708 + 5.996 + + ntclkbufg_4 + + + CLMA_194_304/CLK + + + + r + ms72xx_ctl/iic_dri_tx/data_out[1]/opit_0/CLK + + + clock pessimism + + -0.468 + 5.528 + + + + + clock uncertainty + + 0.000 + 5.528 + + + + + Hold time + + -0.014 + 5.514 + + + +
+
+
+
+ + 0.314 + 0 + 2 + udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[3]/opit_0_A2Q21/CLK + udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr[4]/opit_0_A2Q21/I04 + + clk_720p60Hz + clk_720p60Hz + rise-rise + 0.029 + 8.952 + 9.557 + -0.576 + 0.000 + 0.309 + 0.224 (72.5%) + 0.085 (27.5%) + + Path #20: hold slack is 0.314(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_720p60Hz (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.100 + 2.788 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.059 + 3.847 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 3.847 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.786 + 5.633 + + ntR3950 + + + PLL_158_303/CLK_OUT1 + td + 0.096 + 5.729 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.571 + 7.300 + + nt_pix_clk + + + USCM_84_117/CLK_USCM + td + 0.000 + 7.300 + r + clkbufg_2/gopclkbufg/CLKOUT + + + + net (fanout=1635) + 1.652 + 8.952 + + ntclkbufg_2 + + + CLMA_230_280/CLK + + + + r + udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[3]/opit_0_A2Q21/CLK + + + CLMA_230_280/Q1 + tco + 0.224 + 9.176 + f + udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[3]/opit_0_A2Q21/Q1 + + + + net (fanout=2) + 0.085 + 9.261 + + udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d [3] + + + CLMA_230_281/C4 + + + + f + udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr[4]/opit_0_A2Q21/I04 + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_720p60Hz (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.107 + 3.210 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.078 + 4.288 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 4.288 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.861 + 6.149 + + ntR3950 + + + PLL_158_303/CLK_OUT1 + td + 0.101 + 6.250 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.599 + 7.849 + + nt_pix_clk + + + USCM_84_117/CLK_USCM + td + 0.000 + 7.849 + r + clkbufg_2/gopclkbufg/CLKOUT + + + + net (fanout=1635) + 1.708 + 9.557 + + ntclkbufg_2 + + + CLMA_230_281/CLK + + + + r + udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr[4]/opit_0_A2Q21/CLK + + + clock pessimism + + -0.576 + 8.981 + + + + + clock uncertainty + + 0.000 + 8.981 + + + + + Hold time + + -0.034 + 8.947 + + + +
+
+
+
+ + 0.315 + 0 + 3 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/pll_lock_d[1]/opit_0_inv/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_b_ff/opit_0_inv/D + + clk_200m + clk_200m + rise-rise + 0.029 + 5.374 + 5.867 + -0.464 + 0.000 + 0.330 + 0.226 (68.5%) + 0.104 (31.5%) + + Path #21: hold slack is 0.315(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_200m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.096 + 2.784 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.059 + 3.843 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 3.843 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.531 + 5.374 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + CLMS_94_193/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/pll_lock_d[1]/opit_0_inv/CLK + + + CLMS_94_193/Q0 + tco + 0.226 + 5.600 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/pll_lock_d[1]/opit_0_inv/Q + + + + net (fanout=3) + 0.104 + 5.704 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/pll_lock_d [1] + + + CLMA_94_192/M0 + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_b_ff/opit_0_inv/D + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_200m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.101 + 3.204 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.078 + 4.282 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 4.282 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.585 + 5.867 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + CLMA_94_192/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_b_ff/opit_0_inv/CLK + + + clock pessimism + + -0.464 + 5.403 + + + + + clock uncertainty + + 0.000 + 5.403 + + + + + Hold time + + -0.014 + 5.389 + + + +
+
+
+
+ + 0.318 + 0 + 7 + u_sync_vg/v_count[3]/opit_0_L5Q_perm/CLK + u_sync_vg/pos_y[4]/opit_0_A2Q21/I04 + + clk_720p60Hz + clk_720p60Hz + rise-rise + 0.029 + 8.952 + 9.557 + -0.576 + 0.000 + 0.313 + 0.224 (71.6%) + 0.089 (28.4%) + + Path #22: hold slack is 0.318(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_720p60Hz (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.100 + 2.788 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.059 + 3.847 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 3.847 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.786 + 5.633 + + ntR3950 + + + PLL_158_303/CLK_OUT1 + td + 0.096 + 5.729 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.571 + 7.300 + + nt_pix_clk + + + USCM_84_117/CLK_USCM + td + 0.000 + 7.300 + r + clkbufg_2/gopclkbufg/CLKOUT + + + + net (fanout=1635) + 1.652 + 8.952 + + ntclkbufg_2 + + + CLMS_246_253/CLK + + + + r + u_sync_vg/v_count[3]/opit_0_L5Q_perm/CLK + + + CLMS_246_253/Q1 + tco + 0.224 + 9.176 + f + u_sync_vg/v_count[3]/opit_0_L5Q_perm/Q + + + + net (fanout=7) + 0.089 + 9.265 + + u_sync_vg/v_count [3] + + + CLMA_246_252/C4 + + + + f + u_sync_vg/pos_y[4]/opit_0_A2Q21/I04 + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_720p60Hz (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.107 + 3.210 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.078 + 4.288 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 4.288 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.861 + 6.149 + + ntR3950 + + + PLL_158_303/CLK_OUT1 + td + 0.101 + 6.250 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.599 + 7.849 + + nt_pix_clk + + + USCM_84_117/CLK_USCM + td + 0.000 + 7.849 + r + clkbufg_2/gopclkbufg/CLKOUT + + + + net (fanout=1635) + 1.708 + 9.557 + + ntclkbufg_2 + + + CLMA_246_252/CLK + + + + r + u_sync_vg/pos_y[4]/opit_0_A2Q21/CLK + + + clock pessimism + + -0.576 + 8.981 + + + + + clock uncertainty + + 0.000 + 8.981 + + + + + Hold time + + -0.034 + 8.947 + + + +
+
+
+
+ + 0.334 + 0 + 1 + ms72xx_ctl/iic_dri_tx/receiv_data[7]/opit_0_inv/CLK + ms72xx_ctl/iic_dri_tx/data_out[7]/opit_0/D + + clk_10m + clk_10m + rise-rise + 0.029 + 5.499 + 5.996 + -0.468 + 0.000 + 0.416 + 0.224 (53.8%) + 0.192 (46.2%) + + Path #23: hold slack is 0.334(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_10m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT4 + td + 0.100 + 2.788 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT4 + + + + net (fanout=1) + 1.059 + 3.847 + + clk_10m + + + USCM_84_110/CLK_USCM + td + 0.000 + 3.847 + r + clkbufg_4/gopclkbufg/CLKOUT + + + + net (fanout=235) + 1.652 + 5.499 + + ntclkbufg_4 + + + CLMA_194_305/CLK + + + + r + ms72xx_ctl/iic_dri_tx/receiv_data[7]/opit_0_inv/CLK + + + CLMA_194_305/Q2 + tco + 0.224 + 5.723 + f + ms72xx_ctl/iic_dri_tx/receiv_data[7]/opit_0_inv/Q + + + + net (fanout=1) + 0.192 + 5.915 + + ms72xx_ctl/iic_dri_tx/receiv_data [7] + + + CLMA_194_304/AD + + + + f + ms72xx_ctl/iic_dri_tx/data_out[7]/opit_0/D + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_10m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT4 + td + 0.107 + 3.210 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT4 + + + + net (fanout=1) + 1.078 + 4.288 + + clk_10m + + + USCM_84_110/CLK_USCM + td + 0.000 + 4.288 + r + clkbufg_4/gopclkbufg/CLKOUT + + + + net (fanout=235) + 1.708 + 5.996 + + ntclkbufg_4 + + + CLMA_194_304/CLK + + + + r + ms72xx_ctl/iic_dri_tx/data_out[7]/opit_0/CLK + + + clock pessimism + + -0.468 + 5.528 + + + + + clock uncertainty + + 0.000 + 5.528 + + + + + Hold time + + 0.053 + 5.581 + + + +
+
+
+
+ + 0.342 + 0 + 3 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]/opit_0_inv_L5Q_perm/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]/opit_0_inv_L5Q_perm/L4 + + clk_200m + clk_200m + rise-rise + 0.000 + 5.374 + 5.867 + -0.493 + 0.000 + 0.308 + 0.221 (71.8%) + 0.087 (28.2%) + + Path #24: hold slack is 0.342(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_200m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.096 + 2.784 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.059 + 3.843 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 3.843 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.531 + 5.374 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + CLMS_38_185/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]/opit_0_inv_L5Q_perm/CLK + + + CLMS_38_185/Q3 + tco + 0.221 + 5.595 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]/opit_0_inv_L5Q_perm/Q + + + + net (fanout=3) + 0.087 + 5.682 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg [4] + + + CLMS_38_185/D4 + + + + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]/opit_0_inv_L5Q_perm/L4 + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_200m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.101 + 3.204 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.078 + 4.282 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 4.282 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.585 + 5.867 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + CLMS_38_185/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]/opit_0_inv_L5Q_perm/CLK + + + clock pessimism + + -0.493 + 5.374 + + + + + clock uncertainty + + 0.000 + 5.374 + + + + + Hold time + + -0.034 + 5.340 + + + +
+
+
+
+ + 0.344 + 0 + 4 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[2]/opit_0_inv_L5Q_perm/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[3]/opit_0_inv_L5Q_perm/L4 + + clk_200m + clk_200m + rise-rise + 0.000 + 5.374 + 5.867 + -0.493 + 0.000 + 0.309 + 0.222 (71.8%) + 0.087 (28.2%) + + Path #25: hold slack is 0.344(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_200m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.096 + 2.784 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.059 + 3.843 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 3.843 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.531 + 5.374 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + CLMS_38_185/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[2]/opit_0_inv_L5Q_perm/CLK + + + CLMS_38_185/Q0 + tco + 0.222 + 5.596 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[2]/opit_0_inv_L5Q_perm/Q + + + + net (fanout=4) + 0.087 + 5.683 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg [2] + + + CLMS_38_185/B4 + + + + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[3]/opit_0_inv_L5Q_perm/L4 + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_200m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.101 + 3.204 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.078 + 4.282 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 4.282 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.585 + 5.867 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + CLMS_38_185/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[3]/opit_0_inv_L5Q_perm/CLK + + + clock pessimism + + -0.493 + 5.374 + + + + + clock uncertainty + + 0.000 + 5.374 + + + + + Hold time + + -0.035 + 5.339 + + + +
+
+
+
+ + 0.372 + 0 + 6 + u_ov5640/coms2_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK + u_ov5640/coms2_reg_config/reg_index[2]/opit_0_inv_A2Q21/I00 + + clk_20k + clk_20k + rise-rise + 0.031 + 9.293 + 10.147 + -0.823 + 0.000 + 0.309 + 0.222 (71.8%) + 0.087 (28.2%) + + Path #26: hold slack is 0.372(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_20k (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT3 + td + 0.105 + 2.793 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT3 + + + + net (fanout=1) + 1.059 + 3.852 + + clk_25m + + + USCM_84_114/CLK_USCM + td + 0.000 + 3.852 + r + clkbufg_8/gopclkbufg/CLKOUT + + + + net (fanout=26) + 1.531 + 5.383 + + ntclkbufg_8 + + + CLMA_122_12/Q1 + tco + 0.229 + 5.612 + r + u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q + + + + net (fanout=3) + 2.115 + 7.727 + + u_ov5640/coms2_reg_config/clk_20k_regdiv + + + USCM_84_121/CLK_USCM + td + 0.000 + 7.727 + r + u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + + + + net (fanout=19) + 1.566 + 9.293 + + u_ov5640/coms2_reg_config/clock_20k + + + CLMA_78_12/CLK + + + + r + u_ov5640/coms2_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK + + + CLMA_78_12/Q0 + tco + 0.222 + 9.515 + f + u_ov5640/coms2_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/Q + + + + net (fanout=6) + 0.087 + 9.602 + + u_ov5640/coms2_reg_config/reg_index [0] + + + CLMS_78_13/A0 + + + + f + u_ov5640/coms2_reg_config/reg_index[2]/opit_0_inv_A2Q21/I00 + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_20k (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT3 + td + 0.111 + 3.214 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT3 + + + + net (fanout=1) + 1.078 + 4.292 + + clk_25m + + + USCM_84_114/CLK_USCM + td + 0.000 + 4.292 + r + clkbufg_8/gopclkbufg/CLKOUT + + + + net (fanout=26) + 1.585 + 5.877 + + ntclkbufg_8 + + + CLMA_122_12/Q1 + tco + 0.291 + 6.168 + r + u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q + + + + net (fanout=3) + 2.357 + 8.525 + + u_ov5640/coms2_reg_config/clk_20k_regdiv + + + USCM_84_121/CLK_USCM + td + 0.000 + 8.525 + r + u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + + + + net (fanout=19) + 1.622 + 10.147 + + u_ov5640/coms2_reg_config/clock_20k + + + CLMS_78_13/CLK + + + + r + u_ov5640/coms2_reg_config/reg_index[2]/opit_0_inv_A2Q21/CLK + + + clock pessimism + + -0.823 + 9.324 + + + + + clock uncertainty + + 0.000 + 9.324 + + + + + Hold time + + -0.094 + 9.230 + + + +
+
+
+
+ + 0.383 + 1 + 3 + param_manager_inst/param_offsetX/cnt[3]/opit_0_L5Q_perm/CLK + param_manager_inst/param_offsetX/cnt[6]/opit_0_A2Q21/Cin + + eth_rxc + eth_rxc + rise-rise + 0.029 + 8.446 + 10.030 + -1.555 + 0.000 + 0.527 + 0.339 (64.3%) + 0.188 (35.7%) + + Path #27: hold slack is 0.383(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock eth_rxc (rising edge) + + 0.000 + 0.000 + r + + + + F14 + + 0.000 + 0.000 + r + eth_rxc (port) + + + + net (fanout=1) + 0.057 + 0.057 + + eth_rxc + + + IOBD_240_376/DIN + td + 1.047 + 1.104 + r + eth_rxc_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.104 + + eth_rxc_ibuf/ntD + + + IOL_243_374/INCK + td + 0.048 + 1.152 + r + eth_rxc_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.636 + 1.788 + + _N66 + + + IOCKDLY_237_367/CLK_OUT + td + 2.574 + 4.362 + r + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT + + + + net (fanout=1) + 2.553 + 6.915 + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf + + + USCM_84_109/CLK_USCM + td + 0.000 + 6.915 + r + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT + + + + net (fanout=1862) + 1.531 + 8.446 + + gmii_clk + + + CLMA_250_212/CLK + + + + r + param_manager_inst/param_offsetX/cnt[3]/opit_0_L5Q_perm/CLK + + + CLMA_250_212/Q3 + tco + 0.221 + 8.667 + f + param_manager_inst/param_offsetX/cnt[3]/opit_0_L5Q_perm/Q + + + + net (fanout=3) + 0.188 + 8.855 + + param_manager_inst/param_offsetX/cnt [3] + + + CLMA_250_213/COUT + td + 0.118 + 8.973 + r + param_manager_inst/param_offsetX/N26_1.fsub_3/gateop_A2/Cout + + + + net (fanout=1) + 0.000 + 8.973 + + param_manager_inst/param_offsetX/N26_1.co [4] + + + CLMA_250_217/CIN + + + + r + param_manager_inst/param_offsetX/cnt[6]/opit_0_A2Q21/Cin + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock eth_rxc (rising edge) + + 0.000 + 0.000 + r + + + + F14 + + 0.000 + 0.000 + r + eth_rxc (port) + + + + net (fanout=1) + 0.057 + 0.057 + + eth_rxc + + + IOBD_240_376/DIN + td + 1.254 + 1.311 + r + eth_rxc_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.311 + + eth_rxc_ibuf/ntD + + + IOL_243_374/INCK + td + 0.076 + 1.387 + r + eth_rxc_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.647 + 2.034 + + _N66 + + + IOCKDLY_237_367/CLK_OUT + td + 3.812 + 5.846 + r + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT + + + + net (fanout=1) + 2.599 + 8.445 + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf + + + USCM_84_109/CLK_USCM + td + 0.000 + 8.445 + r + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT + + + + net (fanout=1862) + 1.585 + 10.030 + + gmii_clk + + + CLMA_250_217/CLK + + + + r + param_manager_inst/param_offsetX/cnt[6]/opit_0_A2Q21/CLK + + + clock pessimism + + -1.555 + 8.475 + + + + + clock uncertainty + + 0.200 + 8.675 + + + + + Hold time + + -0.085 + 8.590 + + + +
+
+
+
+ + 0.384 + 0 + 6 + u_ov5640/coms1_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK + u_ov5640/coms1_reg_config/reg_data/iGopDrm/ADA0[5] + + clk_20k + clk_20k + rise-rise + 0.036 + 9.367 + 10.251 + -0.848 + 0.000 + 0.581 + 0.222 (38.2%) + 0.359 (61.8%) + + Path #28: hold slack is 0.384(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_20k (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT3 + td + 0.105 + 2.793 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT3 + + + + net (fanout=1) + 1.059 + 3.852 + + clk_25m + + + USCM_84_114/CLK_USCM + td + 0.000 + 3.852 + r + clkbufg_8/gopclkbufg/CLKOUT + + + + net (fanout=26) + 1.531 + 5.383 + + ntclkbufg_8 + + + CLMS_122_9/Q1 + tco + 0.229 + 5.612 + r + u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q + + + + net (fanout=3) + 2.224 + 7.836 + + u_ov5640/coms1_reg_config/clk_20k_regdiv + + + USCM_84_120/CLK_USCM + td + 0.000 + 7.836 + r + u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + + + + net (fanout=19) + 1.531 + 9.367 + + u_ov5640/coms1_reg_config/clock_20k + + + CLMA_146_12/CLK + + + + r + u_ov5640/coms1_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK + + + CLMA_146_12/Q0 + tco + 0.222 + 9.589 + f + u_ov5640/coms1_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/Q + + + + net (fanout=6) + 0.359 + 9.948 + + u_ov5640/coms1_reg_config/reg_index [0] + + + DRM_142_4/ADA0[5] + + + + f + u_ov5640/coms1_reg_config/reg_data/iGopDrm/ADA0[5] + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_20k (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT3 + td + 0.111 + 3.214 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT3 + + + + net (fanout=1) + 1.078 + 4.292 + + clk_25m + + + USCM_84_114/CLK_USCM + td + 0.000 + 4.292 + r + clkbufg_8/gopclkbufg/CLKOUT + + + + net (fanout=26) + 1.585 + 5.877 + + ntclkbufg_8 + + + CLMS_122_9/Q1 + tco + 0.291 + 6.168 + r + u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q + + + + net (fanout=3) + 2.498 + 8.666 + + u_ov5640/coms1_reg_config/clk_20k_regdiv + + + USCM_84_120/CLK_USCM + td + 0.000 + 8.666 + r + u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + + + + net (fanout=19) + 1.585 + 10.251 + + u_ov5640/coms1_reg_config/clock_20k + + + DRM_142_4/CLKA[0] + + + + r + u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKA[0] + + + clock pessimism + + -0.848 + 9.403 + + + + + clock uncertainty + + 0.000 + 9.403 + + + + + Hold time + + 0.161 + 9.564 + + + +
+
+
+
+ + 0.397 + 0 + 3 + udp_wr_mem_inst/data_count[1]/opit_0_L5Q_perm/CLK + udp_wr_mem_inst/data_count[4]/opit_0_A2Q21/Cin + + eth_rxc + eth_rxc + rise-rise + 0.029 + 8.446 + 10.030 + -1.555 + 0.000 + 0.544 + 0.458 (84.2%) + 0.086 (15.8%) + + Path #29: hold slack is 0.397(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock eth_rxc (rising edge) + + 0.000 + 0.000 + r + + + + F14 + + 0.000 + 0.000 + r + eth_rxc (port) + + + + net (fanout=1) + 0.057 + 0.057 + + eth_rxc + + + IOBD_240_376/DIN + td + 1.047 + 1.104 + r + eth_rxc_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.104 + + eth_rxc_ibuf/ntD + + + IOL_243_374/INCK + td + 0.048 + 1.152 + r + eth_rxc_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.636 + 1.788 + + _N66 + + + IOCKDLY_237_367/CLK_OUT + td + 2.574 + 4.362 + r + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT + + + + net (fanout=1) + 2.553 + 6.915 + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf + + + USCM_84_109/CLK_USCM + td + 0.000 + 6.915 + r + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT + + + + net (fanout=1862) + 1.531 + 8.446 + + gmii_clk + + + CLMA_198_224/CLK + + + + r + udp_wr_mem_inst/data_count[1]/opit_0_L5Q_perm/CLK + + + CLMA_198_224/Q0 + tco + 0.222 + 8.668 + f + udp_wr_mem_inst/data_count[1]/opit_0_L5Q_perm/Q + + + + net (fanout=3) + 0.086 + 8.754 + + udp_wr_mem_inst/data_count [1] + + + + td + 0.236 + 8.990 + r + udp_wr_mem_inst/N30_1.fsub_1/gateop_A2/Cout + + + + net (fanout=1) + 0.000 + 8.990 + + udp_wr_mem_inst/N30_1.co [2] + + + + + + + r + udp_wr_mem_inst/data_count[4]/opit_0_A2Q21/Cin + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock eth_rxc (rising edge) + + 0.000 + 0.000 + r + + + + F14 + + 0.000 + 0.000 + r + eth_rxc (port) + + + + net (fanout=1) + 0.057 + 0.057 + + eth_rxc + + + IOBD_240_376/DIN + td + 1.254 + 1.311 + r + eth_rxc_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.311 + + eth_rxc_ibuf/ntD + + + IOL_243_374/INCK + td + 0.076 + 1.387 + r + eth_rxc_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.647 + 2.034 + + _N66 + + + IOCKDLY_237_367/CLK_OUT + td + 3.812 + 5.846 + r + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT + + + + net (fanout=1) + 2.599 + 8.445 + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf + + + USCM_84_109/CLK_USCM + td + 0.000 + 8.445 + r + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT + + + + net (fanout=1862) + 1.585 + 10.030 + + gmii_clk + + + CLMS_198_225/CLK + + + + r + udp_wr_mem_inst/data_count[4]/opit_0_A2Q21/CLK + + + clock pessimism + + -1.555 + 8.475 + + + + + clock uncertainty + + 0.200 + 8.675 + + + + + Hold time + + -0.082 + 8.593 + + + +
+
+
+
+ + 0.402 + 0 + 3 + u_ov5640/coms1_reg_config/u1/tr_end/opit_0_inv_L5Q_perm/CLK + u_ov5640/coms1_reg_config/u1/tr_end/opit_0_inv_L5Q_perm/L0 + + clk_20k + clk_20k + rise-rise + 0.000 + 9.367 + 10.251 + -0.884 + 0.000 + 0.308 + 0.222 (72.1%) + 0.086 (27.9%) + + Path #30: hold slack is 0.402(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_20k (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT3 + td + 0.105 + 2.793 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT3 + + + + net (fanout=1) + 1.059 + 3.852 + + clk_25m + + + USCM_84_114/CLK_USCM + td + 0.000 + 3.852 + r + clkbufg_8/gopclkbufg/CLKOUT + + + + net (fanout=26) + 1.531 + 5.383 + + ntclkbufg_8 + + + CLMS_122_9/Q1 + tco + 0.229 + 5.612 + r + u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q + + + + net (fanout=3) + 2.224 + 7.836 + + u_ov5640/coms1_reg_config/clk_20k_regdiv + + + USCM_84_120/CLK_USCM + td + 0.000 + 7.836 + r + u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + + + + net (fanout=19) + 1.531 + 9.367 + + u_ov5640/coms1_reg_config/clock_20k + + + CLMA_134_12/CLK + + + + r + u_ov5640/coms1_reg_config/u1/tr_end/opit_0_inv_L5Q_perm/CLK + + + CLMA_134_12/Q0 + tco + 0.222 + 9.589 + f + u_ov5640/coms1_reg_config/u1/tr_end/opit_0_inv_L5Q_perm/Q + + + + net (fanout=3) + 0.086 + 9.675 + + u_ov5640/coms1_reg_config/tr_end + + + CLMA_134_12/A0 + + + + f + u_ov5640/coms1_reg_config/u1/tr_end/opit_0_inv_L5Q_perm/L0 + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_20k (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT3 + td + 0.111 + 3.214 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT3 + + + + net (fanout=1) + 1.078 + 4.292 + + clk_25m + + + USCM_84_114/CLK_USCM + td + 0.000 + 4.292 + r + clkbufg_8/gopclkbufg/CLKOUT + + + + net (fanout=26) + 1.585 + 5.877 + + ntclkbufg_8 + + + CLMS_122_9/Q1 + tco + 0.291 + 6.168 + r + u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q + + + + net (fanout=3) + 2.498 + 8.666 + + u_ov5640/coms1_reg_config/clk_20k_regdiv + + + USCM_84_120/CLK_USCM + td + 0.000 + 8.666 + r + u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + + + + net (fanout=19) + 1.585 + 10.251 + + u_ov5640/coms1_reg_config/clock_20k + + + CLMA_134_12/CLK + + + + r + u_ov5640/coms1_reg_config/u1/tr_end/opit_0_inv_L5Q_perm/CLK + + + clock pessimism + + -0.884 + 9.367 + + + + + clock uncertainty + + 0.000 + 9.367 + + + + + Hold time + + -0.094 + 9.273 + + + +
+
+
+
+ + 0.407 + 0 + 3 + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/CLK + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L3 + + cmos2_pclk + cmos2_pclk + rise-rise + 0.000 + 5.548 + 6.200 + -0.652 + 0.000 + 0.369 + 0.284 (77.0%) + 0.085 (23.0%) + + Path #31: hold slack is 0.407(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock cmos2_pclk (rising edge) + + 0.000 + 0.000 + r + + + + W6 + + 0.000 + 0.000 + r + cmos2_pclk (port) + + + + net (fanout=1) + 0.071 + 0.071 + + cmos2_pclk + + + IOBD_37_0/DIN + td + 1.047 + 1.118 + r + cmos2_pclk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.118 + + cmos2_pclk_ibuf/ntD + + + IOL_39_6/RX_DATA_DD + td + 0.082 + 1.200 + r + cmos2_pclk_ibuf/opit_1/OUT + + + + net (fanout=1) + 2.817 + 4.017 + + nt_cmos2_pclk + + + USCM_84_119/CLK_USCM + td + 0.000 + 4.017 + r + clkbufg_7/gopclkbufg/CLKOUT + + + + net (fanout=118) + 1.531 + 5.548 + + ntclkbufg_7 + + + CLMA_138_41/CLK + + + + r + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/CLK + + + CLMA_138_41/Y2 + tco + 0.284 + 5.832 + f + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/Q + + + + net (fanout=3) + 0.085 + 5.917 + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2 [10] + + + CLMA_138_41/A3 + + + + f + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L3 + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock cmos2_pclk (rising edge) + + 0.000 + 0.000 + r + + + + W6 + + 0.000 + 0.000 + r + cmos2_pclk (port) + + + + net (fanout=1) + 0.071 + 0.071 + + cmos2_pclk + + + IOBD_37_0/DIN + td + 1.254 + 1.325 + r + cmos2_pclk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.325 + + cmos2_pclk_ibuf/ntD + + + IOL_39_6/RX_DATA_DD + td + 0.126 + 1.451 + r + cmos2_pclk_ibuf/opit_1/OUT + + + + net (fanout=1) + 3.164 + 4.615 + + nt_cmos2_pclk + + + USCM_84_119/CLK_USCM + td + 0.000 + 4.615 + r + clkbufg_7/gopclkbufg/CLKOUT + + + + net (fanout=118) + 1.585 + 6.200 + + ntclkbufg_7 + + + CLMA_138_41/CLK + + + + r + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK + + + clock pessimism + + -0.652 + 5.548 + + + + + clock uncertainty + + 0.200 + 5.748 + + + + + Hold time + + -0.238 + 5.510 + + + +
+
+
+
+ + 0.425 + 0 + 5 + u_ov5640/cmos2_8_16bit/image_data_valid0/opit_0_L5Q_perm/CLK + u_ov5640/u_mix_image/cnt1_w[2]/opit_0_A2Q21/CE + + cmos2_pclk + cmos2_pclk + rise-rise + 0.029 + 5.548 + 6.200 + -0.623 + 0.000 + 0.434 + 0.224 (51.6%) + 0.210 (48.4%) + + Path #32: hold slack is 0.425(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock cmos2_pclk (rising edge) + + 0.000 + 0.000 + r + + + + W6 + + 0.000 + 0.000 + r + cmos2_pclk (port) + + + + net (fanout=1) + 0.071 + 0.071 + + cmos2_pclk + + + IOBD_37_0/DIN + td + 1.047 + 1.118 + r + cmos2_pclk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.118 + + cmos2_pclk_ibuf/ntD + + + IOL_39_6/RX_DATA_DD + td + 0.082 + 1.200 + r + cmos2_pclk_ibuf/opit_1/OUT + + + + net (fanout=1) + 2.817 + 4.017 + + nt_cmos2_pclk + + + USCM_84_119/CLK_USCM + td + 0.000 + 4.017 + r + clkbufg_7/gopclkbufg/CLKOUT + + + + net (fanout=118) + 1.531 + 5.548 + + ntclkbufg_7 + + + CLMA_90_20/CLK + + + + r + u_ov5640/cmos2_8_16bit/image_data_valid0/opit_0_L5Q_perm/CLK + + + CLMA_90_20/Q2 + tco + 0.224 + 5.772 + f + u_ov5640/cmos2_8_16bit/image_data_valid0/opit_0_L5Q_perm/Q + + + + net (fanout=5) + 0.210 + 5.982 + + u_ov5640/cmos2_href_16bit + + + CLMA_90_24/CE + + + + f + u_ov5640/u_mix_image/cnt1_w[2]/opit_0_A2Q21/CE + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock cmos2_pclk (rising edge) + + 0.000 + 0.000 + r + + + + W6 + + 0.000 + 0.000 + r + cmos2_pclk (port) + + + + net (fanout=1) + 0.071 + 0.071 + + cmos2_pclk + + + IOBD_37_0/DIN + td + 1.254 + 1.325 + r + cmos2_pclk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.325 + + cmos2_pclk_ibuf/ntD + + + IOL_39_6/RX_DATA_DD + td + 0.126 + 1.451 + r + cmos2_pclk_ibuf/opit_1/OUT + + + + net (fanout=1) + 3.164 + 4.615 + + nt_cmos2_pclk + + + USCM_84_119/CLK_USCM + td + 0.000 + 4.615 + r + clkbufg_7/gopclkbufg/CLKOUT + + + + net (fanout=118) + 1.585 + 6.200 + + ntclkbufg_7 + + + CLMA_90_24/CLK + + + + r + u_ov5640/u_mix_image/cnt1_w[2]/opit_0_A2Q21/CLK + + + clock pessimism + + -0.623 + 5.577 + + + + + clock uncertainty + + 0.200 + 5.777 + + + + + Hold time + + -0.220 + 5.557 + + + +
+
+
+
+ + 0.425 + 0 + 5 + u_ov5640/cmos2_8_16bit/image_data_valid0/opit_0_L5Q_perm/CLK + u_ov5640/u_mix_image/cnt1_w[4]/opit_0_A2Q21/CE + + cmos2_pclk + cmos2_pclk + rise-rise + 0.029 + 5.548 + 6.200 + -0.623 + 0.000 + 0.434 + 0.224 (51.6%) + 0.210 (48.4%) + + Path #33: hold slack is 0.425(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock cmos2_pclk (rising edge) + + 0.000 + 0.000 + r + + + + W6 + + 0.000 + 0.000 + r + cmos2_pclk (port) + + + + net (fanout=1) + 0.071 + 0.071 + + cmos2_pclk + + + IOBD_37_0/DIN + td + 1.047 + 1.118 + r + cmos2_pclk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.118 + + cmos2_pclk_ibuf/ntD + + + IOL_39_6/RX_DATA_DD + td + 0.082 + 1.200 + r + cmos2_pclk_ibuf/opit_1/OUT + + + + net (fanout=1) + 2.817 + 4.017 + + nt_cmos2_pclk + + + USCM_84_119/CLK_USCM + td + 0.000 + 4.017 + r + clkbufg_7/gopclkbufg/CLKOUT + + + + net (fanout=118) + 1.531 + 5.548 + + ntclkbufg_7 + + + CLMA_90_20/CLK + + + + r + u_ov5640/cmos2_8_16bit/image_data_valid0/opit_0_L5Q_perm/CLK + + + CLMA_90_20/Q2 + tco + 0.224 + 5.772 + f + u_ov5640/cmos2_8_16bit/image_data_valid0/opit_0_L5Q_perm/Q + + + + net (fanout=5) + 0.210 + 5.982 + + u_ov5640/cmos2_href_16bit + + + CLMA_90_24/CE + + + + f + u_ov5640/u_mix_image/cnt1_w[4]/opit_0_A2Q21/CE + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock cmos2_pclk (rising edge) + + 0.000 + 0.000 + r + + + + W6 + + 0.000 + 0.000 + r + cmos2_pclk (port) + + + + net (fanout=1) + 0.071 + 0.071 + + cmos2_pclk + + + IOBD_37_0/DIN + td + 1.254 + 1.325 + r + cmos2_pclk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.325 + + cmos2_pclk_ibuf/ntD + + + IOL_39_6/RX_DATA_DD + td + 0.126 + 1.451 + r + cmos2_pclk_ibuf/opit_1/OUT + + + + net (fanout=1) + 3.164 + 4.615 + + nt_cmos2_pclk + + + USCM_84_119/CLK_USCM + td + 0.000 + 4.615 + r + clkbufg_7/gopclkbufg/CLKOUT + + + + net (fanout=118) + 1.585 + 6.200 + + ntclkbufg_7 + + + CLMA_90_24/CLK + + + + r + u_ov5640/u_mix_image/cnt1_w[4]/opit_0_A2Q21/CLK + + + clock pessimism + + -0.623 + 5.577 + + + + + clock uncertainty + + 0.200 + 5.777 + + + + + Hold time + + -0.220 + 5.557 + + + +
+
+
+
+ + 0.450 + 0 + 8 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[0] + + ioclk1 + ioclk1 + rise-rise + 0.035 + 7.041 + 7.712 + -0.636 + 0.000 + 0.421 + 0.421 (100.0%) + 0.000 (0.0%) + + Path #34: hold slack is 0.450(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk1 (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.096 + 2.784 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.059 + 3.843 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 3.843 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.665 + 5.508 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.123 + 5.631 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.102 + 6.733 + + clkout0_wl_0 + + + IOCKGATE_6_188/OUT + td + 0.249 + 6.982 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT + + + + net (fanout=28) + 0.059 + 7.041 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + + + DQSL_6_152/CLK_IO + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + + + DQSL_6_152/IFIFO_RADDR[0] + tco + 0.421 + 7.462 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[0] + + + + net (fanout=8) + 0.000 + 7.462 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [0] + + + IOL_7_162/IFIFO_RADDR[0] + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[0] + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk1 (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.101 + 3.204 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.078 + 4.282 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 4.282 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.738 + 6.020 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.129 + 6.149 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.121 + 7.270 + + clkout0_wl_0 + + + IOCKGATE_6_188/OUT + td + 0.348 + 7.618 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT + + + + net (fanout=28) + 0.094 + 7.712 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + + + IOL_7_162/CLK_IO + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK + + + clock pessimism + + -0.636 + 7.076 + + + + + clock uncertainty + + 0.000 + 7.076 + + + + + Hold time + + -0.064 + 7.012 + + + +
+
+
+
+ + 0.450 + 0 + 8 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[1] + + ioclk1 + ioclk1 + rise-rise + 0.035 + 7.041 + 7.712 + -0.636 + 0.000 + 0.421 + 0.421 (100.0%) + 0.000 (0.0%) + + Path #35: hold slack is 0.450(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk1 (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.096 + 2.784 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.059 + 3.843 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 3.843 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.665 + 5.508 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.123 + 5.631 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.102 + 6.733 + + clkout0_wl_0 + + + IOCKGATE_6_188/OUT + td + 0.249 + 6.982 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT + + + + net (fanout=28) + 0.059 + 7.041 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + + + DQSL_6_152/CLK_IO + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + + + DQSL_6_152/IFIFO_RADDR[1] + tco + 0.421 + 7.462 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[1] + + + + net (fanout=8) + 0.000 + 7.462 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [1] + + + IOL_7_162/IFIFO_RADDR[1] + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[1] + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk1 (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.101 + 3.204 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.078 + 4.282 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 4.282 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.738 + 6.020 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.129 + 6.149 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.121 + 7.270 + + clkout0_wl_0 + + + IOCKGATE_6_188/OUT + td + 0.348 + 7.618 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT + + + + net (fanout=28) + 0.094 + 7.712 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + + + IOL_7_162/CLK_IO + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK + + + clock pessimism + + -0.636 + 7.076 + + + + + clock uncertainty + + 0.000 + 7.076 + + + + + Hold time + + -0.064 + 7.012 + + + +
+
+
+
+ + 0.450 + 0 + 8 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[2] + + ioclk1 + ioclk1 + rise-rise + 0.035 + 7.041 + 7.712 + -0.636 + 0.000 + 0.421 + 0.421 (100.0%) + 0.000 (0.0%) + + Path #36: hold slack is 0.450(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk1 (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.096 + 2.784 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.059 + 3.843 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 3.843 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.665 + 5.508 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.123 + 5.631 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.102 + 6.733 + + clkout0_wl_0 + + + IOCKGATE_6_188/OUT + td + 0.249 + 6.982 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT + + + + net (fanout=28) + 0.059 + 7.041 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + + + DQSL_6_152/CLK_IO + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + + + DQSL_6_152/IFIFO_RADDR[2] + tco + 0.421 + 7.462 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[2] + + + + net (fanout=8) + 0.000 + 7.462 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [2] + + + IOL_7_162/IFIFO_RADDR[2] + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[2] + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk1 (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.101 + 3.204 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.078 + 4.282 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 4.282 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.738 + 6.020 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.129 + 6.149 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.121 + 7.270 + + clkout0_wl_0 + + + IOCKGATE_6_188/OUT + td + 0.348 + 7.618 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT + + + + net (fanout=28) + 0.094 + 7.712 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + + + IOL_7_162/CLK_IO + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK + + + clock pessimism + + -0.636 + 7.076 + + + + + clock uncertainty + + 0.000 + 7.076 + + + + + Hold time + + -0.064 + 7.012 + + + +
+
+
+
+ + 0.450 + 0 + 8 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[0] + + ioclk0 + ioclk0 + rise-rise + 0.035 + 7.041 + 7.712 + -0.636 + 0.000 + 0.421 + 0.421 (100.0%) + 0.000 (0.0%) + + Path #37: hold slack is 0.450(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk0 (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.096 + 2.784 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.059 + 3.843 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 3.843 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.665 + 5.508 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.123 + 5.631 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.102 + 6.733 + + clkout0_wl_0 + + + IOCKGATE_6_312/OUT + td + 0.249 + 6.982 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT + + + + net (fanout=11) + 0.059 + 7.041 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + + + DQSL_6_276/CLK_IO + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + + + DQSL_6_276/IFIFO_RADDR[0] + tco + 0.421 + 7.462 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[0] + + + + net (fanout=8) + 0.000 + 7.462 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [0] + + + IOL_7_285/IFIFO_RADDR[0] + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[0] + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk0 (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.101 + 3.204 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.078 + 4.282 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 4.282 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.738 + 6.020 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.129 + 6.149 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.121 + 7.270 + + clkout0_wl_0 + + + IOCKGATE_6_312/OUT + td + 0.348 + 7.618 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT + + + + net (fanout=11) + 0.094 + 7.712 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + + + IOL_7_285/CLK_IO + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK + + + clock pessimism + + -0.636 + 7.076 + + + + + clock uncertainty + + 0.000 + 7.076 + + + + + Hold time + + -0.064 + 7.012 + + + +
+
+
+
+ + 0.450 + 0 + 8 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[1] + + ioclk0 + ioclk0 + rise-rise + 0.035 + 7.041 + 7.712 + -0.636 + 0.000 + 0.421 + 0.421 (100.0%) + 0.000 (0.0%) + + Path #38: hold slack is 0.450(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk0 (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.096 + 2.784 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.059 + 3.843 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 3.843 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.665 + 5.508 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.123 + 5.631 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.102 + 6.733 + + clkout0_wl_0 + + + IOCKGATE_6_312/OUT + td + 0.249 + 6.982 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT + + + + net (fanout=11) + 0.059 + 7.041 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + + + DQSL_6_276/CLK_IO + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + + + DQSL_6_276/IFIFO_RADDR[1] + tco + 0.421 + 7.462 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[1] + + + + net (fanout=8) + 0.000 + 7.462 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [1] + + + IOL_7_285/IFIFO_RADDR[1] + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[1] + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk0 (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.101 + 3.204 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.078 + 4.282 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 4.282 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.738 + 6.020 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.129 + 6.149 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.121 + 7.270 + + clkout0_wl_0 + + + IOCKGATE_6_312/OUT + td + 0.348 + 7.618 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT + + + + net (fanout=11) + 0.094 + 7.712 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + + + IOL_7_285/CLK_IO + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK + + + clock pessimism + + -0.636 + 7.076 + + + + + clock uncertainty + + 0.000 + 7.076 + + + + + Hold time + + -0.064 + 7.012 + + + +
+
+
+
+ + 0.450 + 0 + 8 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[2] + + ioclk0 + ioclk0 + rise-rise + 0.035 + 7.041 + 7.712 + -0.636 + 0.000 + 0.421 + 0.421 (100.0%) + 0.000 (0.0%) + + Path #39: hold slack is 0.450(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk0 (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.096 + 2.784 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.059 + 3.843 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 3.843 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.665 + 5.508 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.123 + 5.631 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.102 + 6.733 + + clkout0_wl_0 + + + IOCKGATE_6_312/OUT + td + 0.249 + 6.982 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT + + + + net (fanout=11) + 0.059 + 7.041 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + + + DQSL_6_276/CLK_IO + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + + + DQSL_6_276/IFIFO_RADDR[2] + tco + 0.421 + 7.462 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[2] + + + + net (fanout=8) + 0.000 + 7.462 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [2] + + + IOL_7_285/IFIFO_RADDR[2] + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[2] + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk0 (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.101 + 3.204 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.078 + 4.282 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 4.282 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.738 + 6.020 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.129 + 6.149 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.121 + 7.270 + + clkout0_wl_0 + + + IOCKGATE_6_312/OUT + td + 0.348 + 7.618 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT + + + + net (fanout=11) + 0.094 + 7.712 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + + + IOL_7_285/CLK_IO + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK + + + clock pessimism + + -0.636 + 7.076 + + + + + clock uncertainty + + 0.000 + 7.076 + + + + + Hold time + + -0.064 + 7.012 + + + +
+
+
+
+ + 0.550 + 0 + 3 + u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK + u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/D + + clk_25m + clk_25m + rise-rise + 0.000 + 5.383 + 5.877 + -0.494 + 0.000 + 0.526 + 0.224 (42.6%) + 0.302 (57.4%) + + Path #40: hold slack is 0.550(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_25m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT3 + td + 0.105 + 2.793 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT3 + + + + net (fanout=1) + 1.059 + 3.852 + + clk_25m + + + USCM_84_114/CLK_USCM + td + 0.000 + 3.852 + r + clkbufg_8/gopclkbufg/CLKOUT + + + + net (fanout=26) + 1.531 + 5.383 + + ntclkbufg_8 + + + CLMS_122_9/CLK + + + + r + u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK + + + CLMS_122_9/Q1 + tco + 0.224 + 5.607 + f + u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q + + + + net (fanout=3) + 0.302 + 5.909 + + u_ov5640/coms1_reg_config/clk_20k_regdiv + + + CLMS_122_9/M0 + + + + f + u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/D + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_25m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT3 + td + 0.111 + 3.214 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT3 + + + + net (fanout=1) + 1.078 + 4.292 + + clk_25m + + + USCM_84_114/CLK_USCM + td + 0.000 + 4.292 + r + clkbufg_8/gopclkbufg/CLKOUT + + + + net (fanout=26) + 1.585 + 5.877 + + ntclkbufg_8 + + + CLMS_122_9/CLK + + + + r + u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/CLK + + + clock pessimism + + -0.494 + 5.383 + + + + + clock uncertainty + + 0.000 + 5.383 + + + + + Hold time + + -0.024 + 5.359 + + + +
+
+
+
+ + 0.581 + 0 + 3 + u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/CLK + u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite/opit_0_inv/D + + clk_25m + clk_25m + rise-rise + 0.000 + 5.383 + 5.877 + -0.494 + 0.000 + 0.567 + 0.229 (40.4%) + 0.338 (59.6%) + + Path #41: hold slack is 0.581(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_25m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT3 + td + 0.105 + 2.793 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT3 + + + + net (fanout=1) + 1.059 + 3.852 + + clk_25m + + + USCM_84_114/CLK_USCM + td + 0.000 + 3.852 + r + clkbufg_8/gopclkbufg/CLKOUT + + + + net (fanout=26) + 1.531 + 5.383 + + ntclkbufg_8 + + + CLMA_122_12/CLK + + + + r + u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/CLK + + + CLMA_122_12/Q1 + tco + 0.229 + 5.612 + r + u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q + + + + net (fanout=3) + 0.338 + 5.950 + + u_ov5640/coms2_reg_config/clk_20k_regdiv + + + CLMA_122_12/M0 + + + + r + u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite/opit_0_inv/D + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_25m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT3 + td + 0.111 + 3.214 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT3 + + + + net (fanout=1) + 1.078 + 4.292 + + clk_25m + + + USCM_84_114/CLK_USCM + td + 0.000 + 4.292 + r + clkbufg_8/gopclkbufg/CLKOUT + + + + net (fanout=26) + 1.585 + 5.877 + + ntclkbufg_8 + + + CLMA_122_12/CLK + + + + r + u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite/opit_0_inv/CLK + + + clock pessimism + + -0.494 + 5.383 + + + + + clock uncertainty + + 0.000 + 5.383 + + + + + Hold time + + -0.014 + 5.369 + + + +
+
+
+
+ + 0.655 + 1 + 3 + u_ov5640/coms1_reg_config/clock_20k_cnt[1]/opit_0_inv/CLK + u_ov5640/coms1_reg_config/clock_20k_cnt[1]/opit_0_inv/D + + clk_25m + clk_25m + rise-rise + 0.000 + 5.383 + 5.877 + -0.494 + 0.000 + 0.641 + 0.451 (70.4%) + 0.190 (29.6%) + + Path #42: hold slack is 0.655(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_25m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT3 + td + 0.105 + 2.793 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT3 + + + + net (fanout=1) + 1.059 + 3.852 + + clk_25m + + + USCM_84_114/CLK_USCM + td + 0.000 + 3.852 + r + clkbufg_8/gopclkbufg/CLKOUT + + + + net (fanout=26) + 1.531 + 5.383 + + ntclkbufg_8 + + + CLMS_118_13/CLK + + + + r + u_ov5640/coms1_reg_config/clock_20k_cnt[1]/opit_0_inv/CLK + + + CLMS_118_13/Q0 + tco + 0.222 + 5.605 + f + u_ov5640/coms1_reg_config/clock_20k_cnt[1]/opit_0_inv/Q + + + + net (fanout=3) + 0.086 + 5.691 + + u_ov5640/coms1_reg_config/clock_20k_cnt [1] + + + CLMS_118_13/Y0 + td + 0.229 + 5.920 + r + u_ov5640/coms1_reg_config/N11_2_1/gateop_A2/Y0 + + + + net (fanout=1) + 0.104 + 6.024 + + u_ov5640/coms1_reg_config/N1114 [1] + + + CLMS_118_13/M0 + + + + r + u_ov5640/coms1_reg_config/clock_20k_cnt[1]/opit_0_inv/D + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_25m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT3 + td + 0.111 + 3.214 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT3 + + + + net (fanout=1) + 1.078 + 4.292 + + clk_25m + + + USCM_84_114/CLK_USCM + td + 0.000 + 4.292 + r + clkbufg_8/gopclkbufg/CLKOUT + + + + net (fanout=26) + 1.585 + 5.877 + + ntclkbufg_8 + + + CLMS_118_13/CLK + + + + r + u_ov5640/coms1_reg_config/clock_20k_cnt[1]/opit_0_inv/CLK + + + clock pessimism + + -0.494 + 5.383 + + + + + clock uncertainty + + 0.000 + 5.383 + + + + + Hold time + + -0.014 + 5.369 + + + +
+
+
+
+ + + + Slack + Logic Levels + High Fanout + Start Point + End Point + Exception + Launch Clock + Capture Clock + Clock Edges + Clock Skew + Launch Clock Delay + Capture Clock Delay + Clock Pessimism Removal + Requirement + Data delay + Logic delay + Route delay + + + 1.149 + 0 + 687 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_dqs_rst/opit_0_inv/RS + + clk_200m + clk_200m + rise-rise + -0.177 + 5.990 + 5.374 + 0.439 + 5.000 + 2.907 + 0.289 (9.9%) + 2.618 (90.1%) + + Path #1: recovery slack is 1.149(MET) + +
+ + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_200m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.101 + 3.204 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.078 + 4.282 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 4.282 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.708 + 5.990 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + CLMA_174_252/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK + + + CLMA_174_252/Q1 + tco + 0.289 + 6.279 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/Q + + + + net (fanout=687) + 2.618 + 8.897 + + u_axi_ddr_top/I_ipsxb_ddr_top/ddr_rstn + + + CLMS_10_193/RS + + + + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_dqs_rst/opit_0_inv/RS + +
+ + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_200m (rising edge) + + 5.000 + 5.000 + r + + + + P20 + + 0.000 + 5.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 5.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 6.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 6.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 6.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 7.688 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.096 + 7.784 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.059 + 8.843 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 8.843 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.531 + 10.374 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + CLMS_10_193/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_dqs_rst/opit_0_inv/CLK + + + clock pessimism + + 0.439 + 10.813 + + + + + clock uncertainty + + -0.150 + 10.663 + + + + + Recovery time + + -0.617 + 10.046 + + + +
+
+ +
+ + 1.493 + 0 + 687 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d1/opit_0_inv/RS + + clk_200m + clk_200m + rise-rise + -0.177 + 5.990 + 5.374 + 0.439 + 5.000 + 2.563 + 0.289 (11.3%) + 2.274 (88.7%) + + Path #2: recovery slack is 1.493(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_200m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.101 + 3.204 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.078 + 4.282 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 4.282 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.708 + 5.990 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + CLMA_174_252/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK + + + CLMA_174_252/Q1 + tco + 0.289 + 6.279 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/Q + + + + net (fanout=687) + 2.274 + 8.553 + + u_axi_ddr_top/I_ipsxb_ddr_top/ddr_rstn + + + CLMA_30_184/RS + + + + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d1/opit_0_inv/RS + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_200m (rising edge) + + 5.000 + 5.000 + r + + + + P20 + + 0.000 + 5.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 5.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 6.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 6.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 6.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 7.688 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.096 + 7.784 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.059 + 8.843 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 8.843 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.531 + 10.374 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + CLMA_30_184/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d1/opit_0_inv/CLK + + + clock pessimism + + 0.439 + 10.813 + + + + + clock uncertainty + + -0.150 + 10.663 + + + + + Recovery time + + -0.617 + 10.046 + + + +
+
+
+
+ + 1.493 + 0 + 687 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d2/opit_0_inv/RS + + clk_200m + clk_200m + rise-rise + -0.177 + 5.990 + 5.374 + 0.439 + 5.000 + 2.563 + 0.289 (11.3%) + 2.274 (88.7%) + + Path #3: recovery slack is 1.493(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_200m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.101 + 3.204 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.078 + 4.282 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 4.282 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.708 + 5.990 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + CLMA_174_252/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK + + + CLMA_174_252/Q1 + tco + 0.289 + 6.279 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/Q + + + + net (fanout=687) + 2.274 + 8.553 + + u_axi_ddr_top/I_ipsxb_ddr_top/ddr_rstn + + + CLMA_30_184/RS + + + + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d2/opit_0_inv/RS + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_200m (rising edge) + + 5.000 + 5.000 + r + + + + P20 + + 0.000 + 5.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 5.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 6.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 6.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 6.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 7.688 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.096 + 7.784 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.059 + 8.843 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 8.843 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.531 + 10.374 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + CLMA_30_184/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d2/opit_0_inv/CLK + + + clock pessimism + + 0.439 + 10.813 + + + + + clock uncertainty + + -0.150 + 10.663 + + + + + Recovery time + + -0.617 + 10.046 + + + +
+
+
+
+ + 3.268 + 0 + 114 + u_zoom_rst/rst/opit_0_L5Q_perm/CLK + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/RSTA[0] + + clk_1080p60Hz + clk_1080p60Hz + rise-rise + 0.067 + 9.440 + 8.956 + 0.551 + 6.736 + 3.270 + 0.287 (8.8%) + 2.983 (91.2%) + + Path #4: recovery slack is 3.268(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_1080p60Hz (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.107 + 3.210 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.078 + 4.288 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 4.288 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.861 + 6.149 + + ntR3950 + + + PLL_158_303/CLK_OUT0 + td + 0.107 + 6.256 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=1) + 1.599 + 7.855 + + zoom_clk + + + USCM_84_118/CLK_USCM + td + 0.000 + 7.855 + r + clkbufg_3/gopclkbufg/CLKOUT + + + + net (fanout=750) + 1.585 + 9.440 + + ntclkbufg_3 + + + CLMA_170_124/CLK + + + + r + u_zoom_rst/rst/opit_0_L5Q_perm/CLK + + + CLMA_170_124/Q0 + tco + 0.287 + 9.727 + f + u_zoom_rst/rst/opit_0_L5Q_perm/Q + + + + net (fanout=114) + 2.983 + 12.710 + + zoom_rst + + + DRM_306_252/RSTA[0] + + + + f + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/RSTA[0] + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_1080p60Hz (rising edge) + + 6.736 + 6.736 + r + + + + P20 + + 0.000 + 6.736 + r + clk (port) + + + + net (fanout=1) + 0.074 + 6.810 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 8.618 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 8.618 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 8.666 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 9.424 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.100 + 9.524 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.059 + 10.583 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 10.583 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.786 + 12.369 + + ntR3950 + + + PLL_158_303/CLK_OUT0 + td + 0.100 + 12.469 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=1) + 1.571 + 14.040 + + zoom_clk + + + USCM_84_118/CLK_USCM + td + 0.000 + 14.040 + r + clkbufg_3/gopclkbufg/CLKOUT + + + + net (fanout=750) + 1.652 + 15.692 + + ntclkbufg_3 + + + DRM_306_252/CLKA[0] + + + + r + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/CLKA[0] + + + clock pessimism + + 0.551 + 16.243 + + + + + clock uncertainty + + -0.150 + 16.093 + + + + + Recovery time + + -0.115 + 15.978 + + + +
+
+
+
+ + 3.320 + 0 + 114 + u_zoom_rst/rst/opit_0_L5Q_perm/CLK + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/RSTA[0] + + clk_1080p60Hz + clk_1080p60Hz + rise-rise + 0.067 + 9.440 + 8.956 + 0.551 + 6.736 + 3.218 + 0.287 (8.9%) + 2.931 (91.1%) + + Path #5: recovery slack is 3.320(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_1080p60Hz (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.107 + 3.210 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.078 + 4.288 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 4.288 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.861 + 6.149 + + ntR3950 + + + PLL_158_303/CLK_OUT0 + td + 0.107 + 6.256 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=1) + 1.599 + 7.855 + + zoom_clk + + + USCM_84_118/CLK_USCM + td + 0.000 + 7.855 + r + clkbufg_3/gopclkbufg/CLKOUT + + + + net (fanout=750) + 1.585 + 9.440 + + ntclkbufg_3 + + + CLMA_170_124/CLK + + + + r + u_zoom_rst/rst/opit_0_L5Q_perm/CLK + + + CLMA_170_124/Q0 + tco + 0.287 + 9.727 + f + u_zoom_rst/rst/opit_0_L5Q_perm/Q + + + + net (fanout=114) + 2.931 + 12.658 + + zoom_rst + + + DRM_306_292/RSTA[0] + + + + f + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/RSTA[0] + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_1080p60Hz (rising edge) + + 6.736 + 6.736 + r + + + + P20 + + 0.000 + 6.736 + r + clk (port) + + + + net (fanout=1) + 0.074 + 6.810 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 8.618 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 8.618 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 8.666 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 9.424 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.100 + 9.524 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.059 + 10.583 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 10.583 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.786 + 12.369 + + ntR3950 + + + PLL_158_303/CLK_OUT0 + td + 0.100 + 12.469 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=1) + 1.571 + 14.040 + + zoom_clk + + + USCM_84_118/CLK_USCM + td + 0.000 + 14.040 + r + clkbufg_3/gopclkbufg/CLKOUT + + + + net (fanout=750) + 1.652 + 15.692 + + ntclkbufg_3 + + + DRM_306_292/CLKA[0] + + + + r + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/CLKA[0] + + + clock pessimism + + 0.551 + 16.243 + + + + + clock uncertainty + + -0.150 + 16.093 + + + + + Recovery time + + -0.115 + 15.978 + + + +
+
+
+
+ + 3.423 + 0 + 114 + u_zoom_rst/rst/opit_0_L5Q_perm/CLK + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[4].U_GTP_DRM18K/iGopDrm/RSTA[0] + + clk_1080p60Hz + clk_1080p60Hz + rise-rise + 0.067 + 9.440 + 8.956 + 0.551 + 6.736 + 3.115 + 0.287 (9.2%) + 2.828 (90.8%) + + Path #6: recovery slack is 3.423(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_1080p60Hz (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.107 + 3.210 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.078 + 4.288 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 4.288 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.861 + 6.149 + + ntR3950 + + + PLL_158_303/CLK_OUT0 + td + 0.107 + 6.256 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=1) + 1.599 + 7.855 + + zoom_clk + + + USCM_84_118/CLK_USCM + td + 0.000 + 7.855 + r + clkbufg_3/gopclkbufg/CLKOUT + + + + net (fanout=750) + 1.585 + 9.440 + + ntclkbufg_3 + + + CLMA_170_124/CLK + + + + r + u_zoom_rst/rst/opit_0_L5Q_perm/CLK + + + CLMA_170_124/Q0 + tco + 0.287 + 9.727 + f + u_zoom_rst/rst/opit_0_L5Q_perm/Q + + + + net (fanout=114) + 2.828 + 12.555 + + zoom_rst + + + DRM_306_272/RSTA[0] + + + + f + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[4].U_GTP_DRM18K/iGopDrm/RSTA[0] + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_1080p60Hz (rising edge) + + 6.736 + 6.736 + r + + + + P20 + + 0.000 + 6.736 + r + clk (port) + + + + net (fanout=1) + 0.074 + 6.810 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 8.618 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 8.618 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 8.666 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 9.424 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.100 + 9.524 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.059 + 10.583 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 10.583 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.786 + 12.369 + + ntR3950 + + + PLL_158_303/CLK_OUT0 + td + 0.100 + 12.469 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=1) + 1.571 + 14.040 + + zoom_clk + + + USCM_84_118/CLK_USCM + td + 0.000 + 14.040 + r + clkbufg_3/gopclkbufg/CLKOUT + + + + net (fanout=750) + 1.652 + 15.692 + + ntclkbufg_3 + + + DRM_306_272/CLKA[0] + + + + r + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[4].U_GTP_DRM18K/iGopDrm/CLKA[0] + + + clock pessimism + + 0.551 + 16.243 + + + + + clock uncertainty + + -0.150 + 16.093 + + + + + Recovery time + + -0.115 + 15.978 + + + +
+
+
+
+ + 5.676 + 16 + 729 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/opit_0_inv_L5Q_perm/RS + + ddrphy_clkin + ddrphy_clkin + rise-rise + -0.036 + 11.394 + 10.665 + 0.693 + 10.000 + 4.138 + 2.641 (63.8%) + 1.497 (36.2%) + + Path #7: recovery slack is 5.676(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ddrphy_clkin (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.101 + 3.204 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.078 + 4.282 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 4.282 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.738 + 6.020 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.129 + 6.149 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.121 + 7.270 + + clkout0_wl_0 + + + IOCKGATE_6_322/OUT + td + 0.348 + 7.618 + r + clkgate_9/gopclkgate/OUT + + + + net (fanout=1) + 0.000 + 7.618 + + ntclkgate_0 + + + IOCKDIV_6_323/CLK_IODIV + td + 0.000 + 7.618 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + + + + net (fanout=1) + 2.191 + 9.809 + + u_axi_ddr_top/clk + + + USCM_84_116/CLK_USCM + td + 0.000 + 9.809 + r + clkbufg_0/gopclkbufg/CLKOUT + + + + net (fanout=5464) + 1.585 + 11.394 + + ntclkbufg_0 + + + CLMA_46_192/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK + + + CLMA_46_192/Q0 + tco + 0.289 + 11.683 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q + + + + net (fanout=729) + 1.497 + 13.180 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n + + + CLMA_34_148/RSCO + td + 0.147 + 13.327 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[2]/opit_0_inv_L5Q_perm/RSOUT + + + + net (fanout=4) + 0.000 + 13.327 + + ntR882 + + + CLMA_34_152/RSCO + td + 0.147 + 13.474 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[5]/opit_0_inv_L5Q_perm/RSOUT + + + + net (fanout=4) + 0.000 + 13.474 + + ntR881 + + + CLMA_34_156/RSCO + td + 0.147 + 13.621 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_we_n_d[0]/opit_0_inv_L5Q_perm/RSOUT + + + + net (fanout=4) + 0.000 + 13.621 + + ntR880 + + + CLMA_34_160/RSCO + td + 0.147 + 13.768 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cs_n_d[0]/opit_0_inv_L5Q_perm/RSOUT + + + + net (fanout=2) + 0.000 + 13.768 + + ntR879 + + + CLMA_34_164/RSCO + td + 0.147 + 13.915 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[4]/opit_0_inv_A2Q21/RSOUT + + + + net (fanout=3) + 0.000 + 13.915 + + ntR878 + + + CLMA_34_168/RSCO + td + 0.147 + 14.062 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[0]/opit_0_inv_L5Q_perm/RSOUT + + + + net (fanout=6) + 0.000 + 14.062 + + ntR877 + + + CLMA_34_172/RSCO + td + 0.147 + 14.209 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_r[1]/opit_0_inv/RSOUT + + + + net (fanout=5) + 0.000 + 14.209 + + ntR876 + + + CLMA_34_176/RSCO + td + 0.147 + 14.356 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/opit_0_inv_L5Q_perm/RSOUT + + + + net (fanout=2) + 0.000 + 14.356 + + ntR875 + + + CLMA_34_180/RSCO + td + 0.147 + 14.503 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[4]/opit_0_inv_A2Q21/RSOUT + + + + net (fanout=2) + 0.000 + 14.503 + + ntR874 + + + CLMA_34_184/RSCO + td + 0.147 + 14.650 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[8]/opit_0_inv_A2Q21/RSOUT + + + + net (fanout=2) + 0.000 + 14.650 + + ntR873 + + + CLMA_34_192/RSCO + td + 0.147 + 14.797 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[12]/opit_0_inv_A2Q21/RSOUT + + + + net (fanout=2) + 0.000 + 14.797 + + ntR872 + + + CLMA_34_196/RSCO + td + 0.147 + 14.944 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[16]/opit_0_inv_A2Q21/RSOUT + + + + net (fanout=1) + 0.000 + 14.944 + + ntR871 + + + CLMA_34_200/RSCO + td + 0.147 + 15.091 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[17]/opit_0_inv_AQ_perm/RSOUT + + + + net (fanout=6) + 0.000 + 15.091 + + ntR870 + + + CLMA_34_204/RSCO + td + 0.147 + 15.238 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[1]/opit_0_inv/RSOUT + + + + net (fanout=5) + 0.000 + 15.238 + + ntR869 + + + CLMA_34_208/RSCO + td + 0.147 + 15.385 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[238]/opit_0_inv/RSOUT + + + + net (fanout=5) + 0.000 + 15.385 + + ntR868 + + + CLMA_34_212/RSCO + td + 0.147 + 15.532 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[86]/opit_0_inv/RSOUT + + + + net (fanout=5) + 0.000 + 15.532 + + ntR867 + + + CLMA_34_216/RSCI + + + + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/opit_0_inv_L5Q_perm/RS + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ddrphy_clkin (rising edge) + + 10.000 + 10.000 + r + + + + P20 + + 0.000 + 10.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 10.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 11.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 11.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 11.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 12.688 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.096 + 12.784 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.059 + 13.843 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 13.843 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.665 + 15.508 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.123 + 15.631 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.102 + 16.733 + + clkout0_wl_0 + + + IOCKGATE_6_322/OUT + td + 0.249 + 16.982 + r + clkgate_9/gopclkgate/OUT + + + + net (fanout=1) + 0.000 + 16.982 + + ntclkgate_0 + + + IOCKDIV_6_323/CLK_IODIV + td + 0.000 + 16.982 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + + + + net (fanout=1) + 2.152 + 19.134 + + u_axi_ddr_top/clk + + + USCM_84_116/CLK_USCM + td + 0.000 + 19.134 + r + clkbufg_0/gopclkbufg/CLKOUT + + + + net (fanout=5464) + 1.531 + 20.665 + + ntclkbufg_0 + + + CLMA_34_216/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/opit_0_inv_L5Q_perm/CLK + + + clock pessimism + + 0.693 + 21.358 + + + + + clock uncertainty + + -0.150 + 21.208 + + + + + Recovery time + + 0.000 + 21.208 + + + +
+
+
+
+ + 5.676 + 16 + 729 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[110]/opit_0_inv/RS + + ddrphy_clkin + ddrphy_clkin + rise-rise + -0.036 + 11.394 + 10.665 + 0.693 + 10.000 + 4.138 + 2.641 (63.8%) + 1.497 (36.2%) + + Path #8: recovery slack is 5.676(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ddrphy_clkin (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.101 + 3.204 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.078 + 4.282 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 4.282 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.738 + 6.020 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.129 + 6.149 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.121 + 7.270 + + clkout0_wl_0 + + + IOCKGATE_6_322/OUT + td + 0.348 + 7.618 + r + clkgate_9/gopclkgate/OUT + + + + net (fanout=1) + 0.000 + 7.618 + + ntclkgate_0 + + + IOCKDIV_6_323/CLK_IODIV + td + 0.000 + 7.618 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + + + + net (fanout=1) + 2.191 + 9.809 + + u_axi_ddr_top/clk + + + USCM_84_116/CLK_USCM + td + 0.000 + 9.809 + r + clkbufg_0/gopclkbufg/CLKOUT + + + + net (fanout=5464) + 1.585 + 11.394 + + ntclkbufg_0 + + + CLMA_46_192/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK + + + CLMA_46_192/Q0 + tco + 0.289 + 11.683 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q + + + + net (fanout=729) + 1.497 + 13.180 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n + + + CLMA_34_148/RSCO + td + 0.147 + 13.327 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[2]/opit_0_inv_L5Q_perm/RSOUT + + + + net (fanout=4) + 0.000 + 13.327 + + ntR882 + + + CLMA_34_152/RSCO + td + 0.147 + 13.474 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[5]/opit_0_inv_L5Q_perm/RSOUT + + + + net (fanout=4) + 0.000 + 13.474 + + ntR881 + + + CLMA_34_156/RSCO + td + 0.147 + 13.621 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_we_n_d[0]/opit_0_inv_L5Q_perm/RSOUT + + + + net (fanout=4) + 0.000 + 13.621 + + ntR880 + + + CLMA_34_160/RSCO + td + 0.147 + 13.768 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cs_n_d[0]/opit_0_inv_L5Q_perm/RSOUT + + + + net (fanout=2) + 0.000 + 13.768 + + ntR879 + + + CLMA_34_164/RSCO + td + 0.147 + 13.915 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[4]/opit_0_inv_A2Q21/RSOUT + + + + net (fanout=3) + 0.000 + 13.915 + + ntR878 + + + CLMA_34_168/RSCO + td + 0.147 + 14.062 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[0]/opit_0_inv_L5Q_perm/RSOUT + + + + net (fanout=6) + 0.000 + 14.062 + + ntR877 + + + CLMA_34_172/RSCO + td + 0.147 + 14.209 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_r[1]/opit_0_inv/RSOUT + + + + net (fanout=5) + 0.000 + 14.209 + + ntR876 + + + CLMA_34_176/RSCO + td + 0.147 + 14.356 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/opit_0_inv_L5Q_perm/RSOUT + + + + net (fanout=2) + 0.000 + 14.356 + + ntR875 + + + CLMA_34_180/RSCO + td + 0.147 + 14.503 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[4]/opit_0_inv_A2Q21/RSOUT + + + + net (fanout=2) + 0.000 + 14.503 + + ntR874 + + + CLMA_34_184/RSCO + td + 0.147 + 14.650 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[8]/opit_0_inv_A2Q21/RSOUT + + + + net (fanout=2) + 0.000 + 14.650 + + ntR873 + + + CLMA_34_192/RSCO + td + 0.147 + 14.797 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[12]/opit_0_inv_A2Q21/RSOUT + + + + net (fanout=2) + 0.000 + 14.797 + + ntR872 + + + CLMA_34_196/RSCO + td + 0.147 + 14.944 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[16]/opit_0_inv_A2Q21/RSOUT + + + + net (fanout=1) + 0.000 + 14.944 + + ntR871 + + + CLMA_34_200/RSCO + td + 0.147 + 15.091 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[17]/opit_0_inv_AQ_perm/RSOUT + + + + net (fanout=6) + 0.000 + 15.091 + + ntR870 + + + CLMA_34_204/RSCO + td + 0.147 + 15.238 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[1]/opit_0_inv/RSOUT + + + + net (fanout=5) + 0.000 + 15.238 + + ntR869 + + + CLMA_34_208/RSCO + td + 0.147 + 15.385 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[238]/opit_0_inv/RSOUT + + + + net (fanout=5) + 0.000 + 15.385 + + ntR868 + + + CLMA_34_212/RSCO + td + 0.147 + 15.532 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[86]/opit_0_inv/RSOUT + + + + net (fanout=5) + 0.000 + 15.532 + + ntR867 + + + CLMA_34_216/RSCI + + + + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[110]/opit_0_inv/RS + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ddrphy_clkin (rising edge) + + 10.000 + 10.000 + r + + + + P20 + + 0.000 + 10.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 10.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 11.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 11.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 11.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 12.688 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.096 + 12.784 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.059 + 13.843 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 13.843 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.665 + 15.508 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.123 + 15.631 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.102 + 16.733 + + clkout0_wl_0 + + + IOCKGATE_6_322/OUT + td + 0.249 + 16.982 + r + clkgate_9/gopclkgate/OUT + + + + net (fanout=1) + 0.000 + 16.982 + + ntclkgate_0 + + + IOCKDIV_6_323/CLK_IODIV + td + 0.000 + 16.982 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + + + + net (fanout=1) + 2.152 + 19.134 + + u_axi_ddr_top/clk + + + USCM_84_116/CLK_USCM + td + 0.000 + 19.134 + r + clkbufg_0/gopclkbufg/CLKOUT + + + + net (fanout=5464) + 1.531 + 20.665 + + ntclkbufg_0 + + + CLMA_34_216/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[110]/opit_0_inv/CLK + + + clock pessimism + + 0.693 + 21.358 + + + + + clock uncertainty + + -0.150 + 21.208 + + + + + Recovery time + + 0.000 + 21.208 + + + +
+
+
+
+ + 5.676 + 16 + 729 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[116]/opit_0_inv/RS + + ddrphy_clkin + ddrphy_clkin + rise-rise + -0.036 + 11.394 + 10.665 + 0.693 + 10.000 + 4.138 + 2.641 (63.8%) + 1.497 (36.2%) + + Path #9: recovery slack is 5.676(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ddrphy_clkin (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.101 + 3.204 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.078 + 4.282 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 4.282 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.738 + 6.020 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.129 + 6.149 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.121 + 7.270 + + clkout0_wl_0 + + + IOCKGATE_6_322/OUT + td + 0.348 + 7.618 + r + clkgate_9/gopclkgate/OUT + + + + net (fanout=1) + 0.000 + 7.618 + + ntclkgate_0 + + + IOCKDIV_6_323/CLK_IODIV + td + 0.000 + 7.618 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + + + + net (fanout=1) + 2.191 + 9.809 + + u_axi_ddr_top/clk + + + USCM_84_116/CLK_USCM + td + 0.000 + 9.809 + r + clkbufg_0/gopclkbufg/CLKOUT + + + + net (fanout=5464) + 1.585 + 11.394 + + ntclkbufg_0 + + + CLMA_46_192/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK + + + CLMA_46_192/Q0 + tco + 0.289 + 11.683 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q + + + + net (fanout=729) + 1.497 + 13.180 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n + + + CLMA_34_148/RSCO + td + 0.147 + 13.327 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[2]/opit_0_inv_L5Q_perm/RSOUT + + + + net (fanout=4) + 0.000 + 13.327 + + ntR882 + + + CLMA_34_152/RSCO + td + 0.147 + 13.474 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[5]/opit_0_inv_L5Q_perm/RSOUT + + + + net (fanout=4) + 0.000 + 13.474 + + ntR881 + + + CLMA_34_156/RSCO + td + 0.147 + 13.621 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_we_n_d[0]/opit_0_inv_L5Q_perm/RSOUT + + + + net (fanout=4) + 0.000 + 13.621 + + ntR880 + + + CLMA_34_160/RSCO + td + 0.147 + 13.768 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cs_n_d[0]/opit_0_inv_L5Q_perm/RSOUT + + + + net (fanout=2) + 0.000 + 13.768 + + ntR879 + + + CLMA_34_164/RSCO + td + 0.147 + 13.915 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[4]/opit_0_inv_A2Q21/RSOUT + + + + net (fanout=3) + 0.000 + 13.915 + + ntR878 + + + CLMA_34_168/RSCO + td + 0.147 + 14.062 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[0]/opit_0_inv_L5Q_perm/RSOUT + + + + net (fanout=6) + 0.000 + 14.062 + + ntR877 + + + CLMA_34_172/RSCO + td + 0.147 + 14.209 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_r[1]/opit_0_inv/RSOUT + + + + net (fanout=5) + 0.000 + 14.209 + + ntR876 + + + CLMA_34_176/RSCO + td + 0.147 + 14.356 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/opit_0_inv_L5Q_perm/RSOUT + + + + net (fanout=2) + 0.000 + 14.356 + + ntR875 + + + CLMA_34_180/RSCO + td + 0.147 + 14.503 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[4]/opit_0_inv_A2Q21/RSOUT + + + + net (fanout=2) + 0.000 + 14.503 + + ntR874 + + + CLMA_34_184/RSCO + td + 0.147 + 14.650 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[8]/opit_0_inv_A2Q21/RSOUT + + + + net (fanout=2) + 0.000 + 14.650 + + ntR873 + + + CLMA_34_192/RSCO + td + 0.147 + 14.797 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[12]/opit_0_inv_A2Q21/RSOUT + + + + net (fanout=2) + 0.000 + 14.797 + + ntR872 + + + CLMA_34_196/RSCO + td + 0.147 + 14.944 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[16]/opit_0_inv_A2Q21/RSOUT + + + + net (fanout=1) + 0.000 + 14.944 + + ntR871 + + + CLMA_34_200/RSCO + td + 0.147 + 15.091 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[17]/opit_0_inv_AQ_perm/RSOUT + + + + net (fanout=6) + 0.000 + 15.091 + + ntR870 + + + CLMA_34_204/RSCO + td + 0.147 + 15.238 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[1]/opit_0_inv/RSOUT + + + + net (fanout=5) + 0.000 + 15.238 + + ntR869 + + + CLMA_34_208/RSCO + td + 0.147 + 15.385 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[238]/opit_0_inv/RSOUT + + + + net (fanout=5) + 0.000 + 15.385 + + ntR868 + + + CLMA_34_212/RSCO + td + 0.147 + 15.532 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[86]/opit_0_inv/RSOUT + + + + net (fanout=5) + 0.000 + 15.532 + + ntR867 + + + CLMA_34_216/RSCI + + + + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[116]/opit_0_inv/RS + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ddrphy_clkin (rising edge) + + 10.000 + 10.000 + r + + + + P20 + + 0.000 + 10.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 10.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 11.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 11.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 11.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 12.688 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.096 + 12.784 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.059 + 13.843 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 13.843 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.665 + 15.508 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.123 + 15.631 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.102 + 16.733 + + clkout0_wl_0 + + + IOCKGATE_6_322/OUT + td + 0.249 + 16.982 + r + clkgate_9/gopclkgate/OUT + + + + net (fanout=1) + 0.000 + 16.982 + + ntclkgate_0 + + + IOCKDIV_6_323/CLK_IODIV + td + 0.000 + 16.982 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + + + + net (fanout=1) + 2.152 + 19.134 + + u_axi_ddr_top/clk + + + USCM_84_116/CLK_USCM + td + 0.000 + 19.134 + r + clkbufg_0/gopclkbufg/CLKOUT + + + + net (fanout=5464) + 1.531 + 20.665 + + ntclkbufg_0 + + + CLMA_34_216/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[116]/opit_0_inv/CLK + + + clock pessimism + + 0.693 + 21.358 + + + + + clock uncertainty + + -0.150 + 21.208 + + + + + Recovery time + + 0.000 + 21.208 + + + +
+
+
+
+ + 8.940 + 14 + 911 + sync_vg_100m/opit_0_inv_L5Q_perm/CLK + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0/RS + + clk_720p60Hz + clk_720p60Hz + rise-rise + -0.056 + 9.557 + 8.952 + 0.549 + 13.473 + 4.327 + 2.345 (54.2%) + 1.982 (45.8%) + + Path #10: recovery slack is 8.940(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_720p60Hz (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.107 + 3.210 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.078 + 4.288 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 4.288 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.861 + 6.149 + + ntR3950 + + + PLL_158_303/CLK_OUT1 + td + 0.101 + 6.250 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.599 + 7.849 + + nt_pix_clk + + + USCM_84_117/CLK_USCM + td + 0.000 + 7.849 + r + clkbufg_2/gopclkbufg/CLKOUT + + + + net (fanout=1635) + 1.708 + 9.557 + + ntclkbufg_2 + + + CLMA_150_276/CLK + + + + r + sync_vg_100m/opit_0_inv_L5Q_perm/CLK + + + CLMA_150_276/Q0 + tco + 0.287 + 9.844 + f + sync_vg_100m/opit_0_inv_L5Q_perm/Q + + + + net (fanout=911) + 1.982 + 11.826 + + sync_vg_100m + + + CLMA_190_240/RSCO + td + 0.147 + 11.973 + f + udp_wr_mem_inst/mem[39]/opit_0/RSOUT + + + + net (fanout=3) + 0.000 + 11.973 + + ntR687 + + + CLMA_190_244/RSCO + td + 0.147 + 12.120 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[4]/opit_0/RSOUT + + + + net (fanout=4) + 0.000 + 12.120 + + ntR686 + + + CLMA_190_248/RSCO + td + 0.147 + 12.267 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[40]/opit_0_L5Q_perm/RSOUT + + + + net (fanout=2) + 0.000 + 12.267 + + ntR685 + + + CLMA_190_252/RSCO + td + 0.147 + 12.414 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[7]/opit_0/RSOUT + + + + net (fanout=6) + 0.000 + 12.414 + + ntR684 + + + CLMA_190_256/RSCO + td + 0.147 + 12.561 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[7]/opit_0/RSOUT + + + + net (fanout=5) + 0.000 + 12.561 + + ntR683 + + + CLMA_190_260/RSCO + td + 0.147 + 12.708 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[27]/opit_0_L5Q_perm/RSOUT + + + + net (fanout=6) + 0.000 + 12.708 + + ntR682 + + + CLMA_190_264/RSCO + td + 0.147 + 12.855 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[22]/opit_0/RSOUT + + + + net (fanout=4) + 0.000 + 12.855 + + ntR681 + + + CLMA_190_268/RSCO + td + 0.147 + 13.002 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[30]/opit_0_L5Q_perm/RSOUT + + + + net (fanout=4) + 0.000 + 13.002 + + ntR680 + + + CLMA_190_272/RSCO + td + 0.147 + 13.149 + f + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[4]/opit_0_inv_L5Q_perm/RSOUT + + + + net (fanout=4) + 0.000 + 13.149 + + ntR679 + + + CLMA_190_276/RSCO + td + 0.147 + 13.296 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[23]/opit_0/RSOUT + + + + net (fanout=4) + 0.000 + 13.296 + + ntR678 + + + CLMA_190_280/RSCO + td + 0.147 + 13.443 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][1]/opit_0/RSOUT + + + + net (fanout=4) + 0.000 + 13.443 + + ntR677 + + + CLMA_190_284/RSCO + td + 0.147 + 13.590 + f + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/RSOUT + + + + net (fanout=6) + 0.000 + 13.590 + + ntR676 + + + CLMA_190_288/RSCO + td + 0.147 + 13.737 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[29]/opit_0/RSOUT + + + + net (fanout=1) + 0.000 + 13.737 + + ntR675 + + + CLMA_190_292/RSCO + td + 0.147 + 13.884 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][1]/opit_0/RSOUT + + + + net (fanout=6) + 0.000 + 13.884 + + ntR674 + + + CLMA_190_296/RSCI + + + + f + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0/RS + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_720p60Hz (rising edge) + + 13.473 + 13.473 + r + + + + P20 + + 0.000 + 13.473 + r + clk (port) + + + + net (fanout=1) + 0.074 + 13.547 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 15.355 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 15.355 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 15.403 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 16.161 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.100 + 16.261 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.059 + 17.320 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 17.320 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.786 + 19.106 + + ntR3950 + + + PLL_158_303/CLK_OUT1 + td + 0.096 + 19.202 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.571 + 20.773 + + nt_pix_clk + + + USCM_84_117/CLK_USCM + td + 0.000 + 20.773 + r + clkbufg_2/gopclkbufg/CLKOUT + + + + net (fanout=1635) + 1.652 + 22.425 + + ntclkbufg_2 + + + CLMA_190_296/CLK + + + + r + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0/CLK + + + clock pessimism + + 0.549 + 22.974 + + + + + clock uncertainty + + -0.150 + 22.824 + + + + + Recovery time + + 0.000 + 22.824 + + + +
+
+
+
+ + 8.940 + 14 + 911 + sync_vg_100m/opit_0_inv_L5Q_perm/CLK + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/opit_0/RS + + clk_720p60Hz + clk_720p60Hz + rise-rise + -0.056 + 9.557 + 8.952 + 0.549 + 13.473 + 4.327 + 2.345 (54.2%) + 1.982 (45.8%) + + Path #11: recovery slack is 8.940(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_720p60Hz (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.107 + 3.210 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.078 + 4.288 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 4.288 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.861 + 6.149 + + ntR3950 + + + PLL_158_303/CLK_OUT1 + td + 0.101 + 6.250 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.599 + 7.849 + + nt_pix_clk + + + USCM_84_117/CLK_USCM + td + 0.000 + 7.849 + r + clkbufg_2/gopclkbufg/CLKOUT + + + + net (fanout=1635) + 1.708 + 9.557 + + ntclkbufg_2 + + + CLMA_150_276/CLK + + + + r + sync_vg_100m/opit_0_inv_L5Q_perm/CLK + + + CLMA_150_276/Q0 + tco + 0.287 + 9.844 + f + sync_vg_100m/opit_0_inv_L5Q_perm/Q + + + + net (fanout=911) + 1.982 + 11.826 + + sync_vg_100m + + + CLMA_190_240/RSCO + td + 0.147 + 11.973 + f + udp_wr_mem_inst/mem[39]/opit_0/RSOUT + + + + net (fanout=3) + 0.000 + 11.973 + + ntR687 + + + CLMA_190_244/RSCO + td + 0.147 + 12.120 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[4]/opit_0/RSOUT + + + + net (fanout=4) + 0.000 + 12.120 + + ntR686 + + + CLMA_190_248/RSCO + td + 0.147 + 12.267 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[40]/opit_0_L5Q_perm/RSOUT + + + + net (fanout=2) + 0.000 + 12.267 + + ntR685 + + + CLMA_190_252/RSCO + td + 0.147 + 12.414 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[7]/opit_0/RSOUT + + + + net (fanout=6) + 0.000 + 12.414 + + ntR684 + + + CLMA_190_256/RSCO + td + 0.147 + 12.561 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[7]/opit_0/RSOUT + + + + net (fanout=5) + 0.000 + 12.561 + + ntR683 + + + CLMA_190_260/RSCO + td + 0.147 + 12.708 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[27]/opit_0_L5Q_perm/RSOUT + + + + net (fanout=6) + 0.000 + 12.708 + + ntR682 + + + CLMA_190_264/RSCO + td + 0.147 + 12.855 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[22]/opit_0/RSOUT + + + + net (fanout=4) + 0.000 + 12.855 + + ntR681 + + + CLMA_190_268/RSCO + td + 0.147 + 13.002 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[30]/opit_0_L5Q_perm/RSOUT + + + + net (fanout=4) + 0.000 + 13.002 + + ntR680 + + + CLMA_190_272/RSCO + td + 0.147 + 13.149 + f + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[4]/opit_0_inv_L5Q_perm/RSOUT + + + + net (fanout=4) + 0.000 + 13.149 + + ntR679 + + + CLMA_190_276/RSCO + td + 0.147 + 13.296 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[23]/opit_0/RSOUT + + + + net (fanout=4) + 0.000 + 13.296 + + ntR678 + + + CLMA_190_280/RSCO + td + 0.147 + 13.443 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][1]/opit_0/RSOUT + + + + net (fanout=4) + 0.000 + 13.443 + + ntR677 + + + CLMA_190_284/RSCO + td + 0.147 + 13.590 + f + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/RSOUT + + + + net (fanout=6) + 0.000 + 13.590 + + ntR676 + + + CLMA_190_288/RSCO + td + 0.147 + 13.737 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[29]/opit_0/RSOUT + + + + net (fanout=1) + 0.000 + 13.737 + + ntR675 + + + CLMA_190_292/RSCO + td + 0.147 + 13.884 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][1]/opit_0/RSOUT + + + + net (fanout=6) + 0.000 + 13.884 + + ntR674 + + + CLMA_190_296/RSCI + + + + f + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/opit_0/RS + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_720p60Hz (rising edge) + + 13.473 + 13.473 + r + + + + P20 + + 0.000 + 13.473 + r + clk (port) + + + + net (fanout=1) + 0.074 + 13.547 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 15.355 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 15.355 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 15.403 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 16.161 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.100 + 16.261 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.059 + 17.320 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 17.320 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.786 + 19.106 + + ntR3950 + + + PLL_158_303/CLK_OUT1 + td + 0.096 + 19.202 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.571 + 20.773 + + nt_pix_clk + + + USCM_84_117/CLK_USCM + td + 0.000 + 20.773 + r + clkbufg_2/gopclkbufg/CLKOUT + + + + net (fanout=1635) + 1.652 + 22.425 + + ntclkbufg_2 + + + CLMA_190_296/CLK + + + + r + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/opit_0/CLK + + + clock pessimism + + 0.549 + 22.974 + + + + + clock uncertainty + + -0.150 + 22.824 + + + + + Recovery time + + 0.000 + 22.824 + + + +
+
+
+
+ + 8.940 + 14 + 911 + sync_vg_100m/opit_0_inv_L5Q_perm/CLK + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/RS + + clk_720p60Hz + clk_720p60Hz + rise-rise + -0.056 + 9.557 + 8.952 + 0.549 + 13.473 + 4.327 + 2.345 (54.2%) + 1.982 (45.8%) + + Path #12: recovery slack is 8.940(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_720p60Hz (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.107 + 3.210 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.078 + 4.288 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 4.288 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.861 + 6.149 + + ntR3950 + + + PLL_158_303/CLK_OUT1 + td + 0.101 + 6.250 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.599 + 7.849 + + nt_pix_clk + + + USCM_84_117/CLK_USCM + td + 0.000 + 7.849 + r + clkbufg_2/gopclkbufg/CLKOUT + + + + net (fanout=1635) + 1.708 + 9.557 + + ntclkbufg_2 + + + CLMA_150_276/CLK + + + + r + sync_vg_100m/opit_0_inv_L5Q_perm/CLK + + + CLMA_150_276/Q0 + tco + 0.287 + 9.844 + f + sync_vg_100m/opit_0_inv_L5Q_perm/Q + + + + net (fanout=911) + 1.982 + 11.826 + + sync_vg_100m + + + CLMA_190_240/RSCO + td + 0.147 + 11.973 + f + udp_wr_mem_inst/mem[39]/opit_0/RSOUT + + + + net (fanout=3) + 0.000 + 11.973 + + ntR687 + + + CLMA_190_244/RSCO + td + 0.147 + 12.120 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[4]/opit_0/RSOUT + + + + net (fanout=4) + 0.000 + 12.120 + + ntR686 + + + CLMA_190_248/RSCO + td + 0.147 + 12.267 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[40]/opit_0_L5Q_perm/RSOUT + + + + net (fanout=2) + 0.000 + 12.267 + + ntR685 + + + CLMA_190_252/RSCO + td + 0.147 + 12.414 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[7]/opit_0/RSOUT + + + + net (fanout=6) + 0.000 + 12.414 + + ntR684 + + + CLMA_190_256/RSCO + td + 0.147 + 12.561 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[7]/opit_0/RSOUT + + + + net (fanout=5) + 0.000 + 12.561 + + ntR683 + + + CLMA_190_260/RSCO + td + 0.147 + 12.708 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[27]/opit_0_L5Q_perm/RSOUT + + + + net (fanout=6) + 0.000 + 12.708 + + ntR682 + + + CLMA_190_264/RSCO + td + 0.147 + 12.855 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[22]/opit_0/RSOUT + + + + net (fanout=4) + 0.000 + 12.855 + + ntR681 + + + CLMA_190_268/RSCO + td + 0.147 + 13.002 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[30]/opit_0_L5Q_perm/RSOUT + + + + net (fanout=4) + 0.000 + 13.002 + + ntR680 + + + CLMA_190_272/RSCO + td + 0.147 + 13.149 + f + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[4]/opit_0_inv_L5Q_perm/RSOUT + + + + net (fanout=4) + 0.000 + 13.149 + + ntR679 + + + CLMA_190_276/RSCO + td + 0.147 + 13.296 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[23]/opit_0/RSOUT + + + + net (fanout=4) + 0.000 + 13.296 + + ntR678 + + + CLMA_190_280/RSCO + td + 0.147 + 13.443 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][1]/opit_0/RSOUT + + + + net (fanout=4) + 0.000 + 13.443 + + ntR677 + + + CLMA_190_284/RSCO + td + 0.147 + 13.590 + f + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/RSOUT + + + + net (fanout=6) + 0.000 + 13.590 + + ntR676 + + + CLMA_190_288/RSCO + td + 0.147 + 13.737 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[29]/opit_0/RSOUT + + + + net (fanout=1) + 0.000 + 13.737 + + ntR675 + + + CLMA_190_292/RSCO + td + 0.147 + 13.884 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][1]/opit_0/RSOUT + + + + net (fanout=6) + 0.000 + 13.884 + + ntR674 + + + CLMA_190_296/RSCI + + + + f + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/RS + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_720p60Hz (rising edge) + + 13.473 + 13.473 + r + + + + P20 + + 0.000 + 13.473 + r + clk (port) + + + + net (fanout=1) + 0.074 + 13.547 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 15.355 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 15.355 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 15.403 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 16.161 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.100 + 16.261 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.059 + 17.320 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 17.320 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.786 + 19.106 + + ntR3950 + + + PLL_158_303/CLK_OUT1 + td + 0.096 + 19.202 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.571 + 20.773 + + nt_pix_clk + + + USCM_84_117/CLK_USCM + td + 0.000 + 20.773 + r + clkbufg_2/gopclkbufg/CLKOUT + + + + net (fanout=1635) + 1.652 + 22.425 + + ntclkbufg_2 + + + CLMA_190_296/CLK + + + + r + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/CLK + + + clock pessimism + + 0.549 + 22.974 + + + + + clock uncertainty + + -0.150 + 22.824 + + + + + Recovery time + + 0.000 + 22.824 + + + +
+
+
+
+ + 15.776 + 0 + 589 + u_clk50m_rst/rst/opit_0_L5Q_perm/CLK + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/RS + + clk_50m + clk_50m + rise-rise + -0.040 + 5.873 + 5.392 + 0.441 + 20.000 + 3.417 + 0.287 (8.4%) + 3.130 (91.6%) + + Path #13: recovery slack is 15.776(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_50m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.107 + 3.210 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.078 + 4.288 + + rd3_clk + + + USCM_84_108/CLK_USCM + td + 0.000 + 4.288 + r + clkbufg_1/gopclkbufg/CLKOUT + + + + net (fanout=2516) + 1.585 + 5.873 + + ntclkbufg_1 + + + CLMS_158_237/CLK + + + + r + u_clk50m_rst/rst/opit_0_L5Q_perm/CLK + + + CLMS_158_237/Q0 + tco + 0.287 + 6.160 + f + u_clk50m_rst/rst/opit_0_L5Q_perm/Q + + + + net (fanout=589) + 3.130 + 9.290 + + rd3_rst + + + CLMA_58_40/RS + + + + f + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/RS + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_50m (rising edge) + + 20.000 + 20.000 + r + + + + P20 + + 0.000 + 20.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 20.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 21.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 21.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 21.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 22.688 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.100 + 22.788 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.059 + 23.847 + + rd3_clk + + + USCM_84_108/CLK_USCM + td + 0.000 + 23.847 + r + clkbufg_1/gopclkbufg/CLKOUT + + + + net (fanout=2516) + 1.545 + 25.392 + + ntclkbufg_1 + + + CLMA_58_40/CLK + + + + r + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK + + + clock pessimism + + 0.441 + 25.833 + + + + + clock uncertainty + + -0.150 + 25.683 + + + + + Recovery time + + -0.617 + 25.066 + + + +
+
+
+
+ + 15.952 + 0 + 589 + u_clk50m_rst/rst/opit_0_L5Q_perm/CLK + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[1]/opit_0_A2Q21/RS + + clk_50m + clk_50m + rise-rise + -0.029 + 5.873 + 5.403 + 0.441 + 20.000 + 3.252 + 0.287 (8.8%) + 2.965 (91.2%) + + Path #14: recovery slack is 15.952(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_50m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.107 + 3.210 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.078 + 4.288 + + rd3_clk + + + USCM_84_108/CLK_USCM + td + 0.000 + 4.288 + r + clkbufg_1/gopclkbufg/CLKOUT + + + + net (fanout=2516) + 1.585 + 5.873 + + ntclkbufg_1 + + + CLMS_158_237/CLK + + + + r + u_clk50m_rst/rst/opit_0_L5Q_perm/CLK + + + CLMS_158_237/Q0 + tco + 0.287 + 6.160 + f + u_clk50m_rst/rst/opit_0_L5Q_perm/Q + + + + net (fanout=589) + 2.965 + 9.125 + + rd3_rst + + + CLMA_58_33/RS + + + + f + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[1]/opit_0_A2Q21/RS + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_50m (rising edge) + + 20.000 + 20.000 + r + + + + P20 + + 0.000 + 20.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 20.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 21.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 21.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 21.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 22.688 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.100 + 22.788 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.059 + 23.847 + + rd3_clk + + + USCM_84_108/CLK_USCM + td + 0.000 + 23.847 + r + clkbufg_1/gopclkbufg/CLKOUT + + + + net (fanout=2516) + 1.556 + 25.403 + + ntclkbufg_1 + + + CLMA_58_33/CLK + + + + r + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[1]/opit_0_A2Q21/CLK + + + clock pessimism + + 0.441 + 25.844 + + + + + clock uncertainty + + -0.150 + 25.694 + + + + + Recovery time + + -0.617 + 25.077 + + + +
+
+
+
+ + 15.952 + 0 + 589 + u_clk50m_rst/rst/opit_0_L5Q_perm/CLK + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[3]/opit_0_A2Q21/RS + + clk_50m + clk_50m + rise-rise + -0.029 + 5.873 + 5.403 + 0.441 + 20.000 + 3.252 + 0.287 (8.8%) + 2.965 (91.2%) + + Path #15: recovery slack is 15.952(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_50m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.107 + 3.210 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.078 + 4.288 + + rd3_clk + + + USCM_84_108/CLK_USCM + td + 0.000 + 4.288 + r + clkbufg_1/gopclkbufg/CLKOUT + + + + net (fanout=2516) + 1.585 + 5.873 + + ntclkbufg_1 + + + CLMS_158_237/CLK + + + + r + u_clk50m_rst/rst/opit_0_L5Q_perm/CLK + + + CLMS_158_237/Q0 + tco + 0.287 + 6.160 + f + u_clk50m_rst/rst/opit_0_L5Q_perm/Q + + + + net (fanout=589) + 2.965 + 9.125 + + rd3_rst + + + CLMA_58_33/RS + + + + f + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[3]/opit_0_A2Q21/RS + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_50m (rising edge) + + 20.000 + 20.000 + r + + + + P20 + + 0.000 + 20.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 20.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 21.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 21.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 21.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 22.688 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.100 + 22.788 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.059 + 23.847 + + rd3_clk + + + USCM_84_108/CLK_USCM + td + 0.000 + 23.847 + r + clkbufg_1/gopclkbufg/CLKOUT + + + + net (fanout=2516) + 1.556 + 25.403 + + ntclkbufg_1 + + + CLMA_58_33/CLK + + + + r + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[3]/opit_0_A2Q21/CLK + + + clock pessimism + + 0.441 + 25.844 + + + + + clock uncertainty + + -0.150 + 25.694 + + + + + Recovery time + + -0.617 + 25.077 + + + +
+
+
+
+ + 97.797 + 0 + 3 + rstn_out1/opit_0_inv/CLK + ms72xx_ctl/rstn_temp1/opit_0_inv/RS + + clk_10m + clk_10m + rise-rise + 0.067 + 5.873 + 5.499 + 0.441 + 100.000 + 1.503 + 0.286 (19.0%) + 1.217 (81.0%) + + Path #16: recovery slack is 97.797(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_10m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT4 + td + 0.107 + 3.210 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT4 + + + + net (fanout=1) + 1.078 + 4.288 + + clk_10m + + + USCM_84_110/CLK_USCM + td + 0.000 + 4.288 + r + clkbufg_4/gopclkbufg/CLKOUT + + + + net (fanout=235) + 1.585 + 5.873 + + ntclkbufg_4 + + + CLMS_270_193/CLK + + + + r + rstn_out1/opit_0_inv/CLK + + + CLMS_270_193/Q3 + tco + 0.286 + 6.159 + f + rstn_out1/opit_0_inv/Q + + + + net (fanout=3) + 1.217 + 7.376 + + nt_eth_rstn + + + CLMA_262_268/RS + + + + f + ms72xx_ctl/rstn_temp1/opit_0_inv/RS + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_10m (rising edge) + + 100.000 + 100.000 + r + + + + P20 + + 0.000 + 100.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 100.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 101.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 101.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 101.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 102.688 + + _N69 + + + PLL_158_55/CLK_OUT4 + td + 0.100 + 102.788 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT4 + + + + net (fanout=1) + 1.059 + 103.847 + + clk_10m + + + USCM_84_110/CLK_USCM + td + 0.000 + 103.847 + r + clkbufg_4/gopclkbufg/CLKOUT + + + + net (fanout=235) + 1.652 + 105.499 + + ntclkbufg_4 + + + CLMA_262_268/CLK + + + + r + ms72xx_ctl/rstn_temp1/opit_0_inv/CLK + + + clock pessimism + + 0.441 + 105.940 + + + + + clock uncertainty + + -0.150 + 105.790 + + + + + Recovery time + + -0.617 + 105.173 + + + +
+
+
+
+ + + + Slack + Logic Levels + High Fanout + Start Point + End Point + Exception + Launch Clock + Capture Clock + Clock Edges + Clock Skew + Launch Clock Delay + Capture Clock Delay + Clock Pessimism Removal + Requirement + Data delay + Logic delay + Route delay + + + 0.555 + 0 + 2 + u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/opit_0/RS + + clk_200m + clk_200m + rise-rise + 0.069 + 5.495 + 5.990 + -0.426 + 0.000 + 0.404 + 0.222 (55.0%) + 0.182 (45.0%) + + Path #1: removal slack is 0.555(MET) + +
+ + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_200m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.096 + 2.784 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.059 + 3.843 + + ddr_clk + + + USCM_84_153/CLK_USCM + td + 0.000 + 3.843 + r + USCMROUTE_2/CLKOUT + + + + net (fanout=6) + 1.652 + 5.495 + + ntR3952 + + + CLMS_174_253/CLK + + + + r + u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK + + + CLMS_174_253/Q0 + tco + 0.222 + 5.717 + f + u_ddr_rst/rst/opit_0_inv_L5Q_perm/Q + + + + net (fanout=2) + 0.182 + 5.899 + + ddr_rst + + + CLMA_174_252/RS + + + + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/opit_0/RS + +
+ + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_200m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.101 + 3.204 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.078 + 4.282 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 4.282 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.708 + 5.990 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + CLMA_174_252/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/opit_0/CLK + + + clock pessimism + + -0.426 + 5.564 + + + + + clock uncertainty + + 0.000 + 5.564 + + + + + Removal time + + -0.220 + 5.344 + + + +
+
+ +
+ + 0.555 + 0 + 2 + u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/RS + + clk_200m + clk_200m + rise-rise + 0.069 + 5.495 + 5.990 + -0.426 + 0.000 + 0.404 + 0.222 (55.0%) + 0.182 (45.0%) + + Path #2: removal slack is 0.555(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_200m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.096 + 2.784 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.059 + 3.843 + + ddr_clk + + + USCM_84_153/CLK_USCM + td + 0.000 + 3.843 + r + USCMROUTE_2/CLKOUT + + + + net (fanout=6) + 1.652 + 5.495 + + ntR3952 + + + CLMS_174_253/CLK + + + + r + u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK + + + CLMS_174_253/Q0 + tco + 0.222 + 5.717 + f + u_ddr_rst/rst/opit_0_inv_L5Q_perm/Q + + + + net (fanout=2) + 0.182 + 5.899 + + ddr_rst + + + CLMA_174_252/RS + + + + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/RS + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_200m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.101 + 3.204 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.078 + 4.282 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 4.282 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.708 + 5.990 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + CLMA_174_252/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK + + + clock pessimism + + -0.426 + 5.564 + + + + + clock uncertainty + + 0.000 + 5.564 + + + + + Removal time + + -0.220 + 5.344 + + + +
+
+
+
+ + 0.610 + 0 + 40 + image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0] + + clk_50m + clk_50m + rise-rise + 0.036 + 5.499 + 5.996 + -0.461 + 0.000 + 0.624 + 0.222 (35.6%) + 0.402 (64.4%) + + Path #3: removal slack is 0.610(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_50m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.100 + 2.788 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.059 + 3.847 + + rd3_clk + + + USCM_84_108/CLK_USCM + td + 0.000 + 3.847 + r + clkbufg_1/gopclkbufg/CLKOUT + + + + net (fanout=2516) + 1.652 + 5.499 + + ntclkbufg_1 + + + CLMS_98_321/CLK + + + + r + image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK + + + CLMS_98_321/Q0 + tco + 0.222 + 5.721 + f + image_filiter_inst/multiline_buffer_inst/srst/opit_0/Q + + + + net (fanout=40) + 0.402 + 6.123 + + image_filiter_inst/multiline_buffer_inst/srst + + + DRM_82_316/RSTB[0] + + + + f + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0] + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_50m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.107 + 3.210 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.078 + 4.288 + + rd3_clk + + + USCM_84_108/CLK_USCM + td + 0.000 + 4.288 + r + clkbufg_1/gopclkbufg/CLKOUT + + + + net (fanout=2516) + 1.708 + 5.996 + + ntclkbufg_1 + + + DRM_82_316/CLKB[0] + + + + r + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] + + + clock pessimism + + -0.461 + 5.535 + + + + + clock uncertainty + + 0.000 + 5.535 + + + + + Removal time + + -0.022 + 5.513 + + + +
+
+
+
+ + 0.619 + 1 + 40 + image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/RS + + clk_50m + clk_50m + rise-rise + 0.036 + 5.499 + 5.996 + -0.461 + 0.000 + 0.655 + 0.337 (51.5%) + 0.318 (48.5%) + + Path #4: removal slack is 0.619(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_50m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.100 + 2.788 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.059 + 3.847 + + rd3_clk + + + USCM_84_108/CLK_USCM + td + 0.000 + 3.847 + r + clkbufg_1/gopclkbufg/CLKOUT + + + + net (fanout=2516) + 1.652 + 5.499 + + ntclkbufg_1 + + + CLMS_98_321/CLK + + + + r + image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK + + + CLMS_98_321/Q0 + tco + 0.222 + 5.721 + f + image_filiter_inst/multiline_buffer_inst/srst/opit_0/Q + + + + net (fanout=40) + 0.318 + 6.039 + + image_filiter_inst/multiline_buffer_inst/srst + + + CLMS_102_325/RSCO + td + 0.115 + 6.154 + f + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/RSOUT + + + + net (fanout=2) + 0.000 + 6.154 + + ntR19 + + + CLMS_102_329/RSCI + + + + f + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/RS + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_50m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.107 + 3.210 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.078 + 4.288 + + rd3_clk + + + USCM_84_108/CLK_USCM + td + 0.000 + 4.288 + r + clkbufg_1/gopclkbufg/CLKOUT + + + + net (fanout=2516) + 1.708 + 5.996 + + ntclkbufg_1 + + + CLMS_102_329/CLK + + + + r + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK + + + clock pessimism + + -0.461 + 5.535 + + + + + clock uncertainty + + 0.000 + 5.535 + + + + + Removal time + + 0.000 + 5.535 + + + +
+
+
+
+ + 0.619 + 1 + 40 + image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/RS + + clk_50m + clk_50m + rise-rise + 0.036 + 5.499 + 5.996 + -0.461 + 0.000 + 0.655 + 0.337 (51.5%) + 0.318 (48.5%) + + Path #5: removal slack is 0.619(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_50m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.100 + 2.788 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.059 + 3.847 + + rd3_clk + + + USCM_84_108/CLK_USCM + td + 0.000 + 3.847 + r + clkbufg_1/gopclkbufg/CLKOUT + + + + net (fanout=2516) + 1.652 + 5.499 + + ntclkbufg_1 + + + CLMS_98_321/CLK + + + + r + image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK + + + CLMS_98_321/Q0 + tco + 0.222 + 5.721 + f + image_filiter_inst/multiline_buffer_inst/srst/opit_0/Q + + + + net (fanout=40) + 0.318 + 6.039 + + image_filiter_inst/multiline_buffer_inst/srst + + + CLMS_102_325/RSCO + td + 0.115 + 6.154 + f + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/RSOUT + + + + net (fanout=2) + 0.000 + 6.154 + + ntR19 + + + CLMS_102_329/RSCI + + + + f + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/RS + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_50m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.107 + 3.210 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.078 + 4.288 + + rd3_clk + + + USCM_84_108/CLK_USCM + td + 0.000 + 4.288 + r + clkbufg_1/gopclkbufg/CLKOUT + + + + net (fanout=2516) + 1.708 + 5.996 + + ntclkbufg_1 + + + CLMS_102_329/CLK + + + + r + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK + + + clock pessimism + + -0.461 + 5.535 + + + + + clock uncertainty + + 0.000 + 5.535 + + + + + Removal time + + 0.000 + 5.535 + + + +
+
+
+
+ + 0.637 + 1 + 729 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[6]/opit_0_inv_L5Q_perm/RS + + ddrphy_clkin + ddrphy_clkin + rise-rise + 0.036 + 10.665 + 11.394 + -0.693 + 0.000 + 0.673 + 0.327 (48.6%) + 0.346 (51.4%) + + Path #6: removal slack is 0.637(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ddrphy_clkin (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.096 + 2.784 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.059 + 3.843 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 3.843 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.665 + 5.508 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.123 + 5.631 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.102 + 6.733 + + clkout0_wl_0 + + + IOCKGATE_6_322/OUT + td + 0.249 + 6.982 + r + clkgate_9/gopclkgate/OUT + + + + net (fanout=1) + 0.000 + 6.982 + + ntclkgate_0 + + + IOCKDIV_6_323/CLK_IODIV + td + 0.000 + 6.982 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + + + + net (fanout=1) + 2.152 + 9.134 + + u_axi_ddr_top/clk + + + USCM_84_116/CLK_USCM + td + 0.000 + 9.134 + r + clkbufg_0/gopclkbufg/CLKOUT + + + + net (fanout=5464) + 1.531 + 10.665 + + ntclkbufg_0 + + + CLMA_46_192/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK + + + CLMA_46_192/Q0 + tco + 0.222 + 10.887 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q + + + + net (fanout=729) + 0.346 + 11.233 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n + + + CLMA_38_192/RSCO + td + 0.105 + 11.338 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[57]/opit_0_inv/RSOUT + + + + net (fanout=4) + 0.000 + 11.338 + + ntR984 + + + CLMA_38_196/RSCI + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[6]/opit_0_inv_L5Q_perm/RS + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ddrphy_clkin (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.101 + 3.204 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.078 + 4.282 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 4.282 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.738 + 6.020 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.129 + 6.149 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.121 + 7.270 + + clkout0_wl_0 + + + IOCKGATE_6_322/OUT + td + 0.348 + 7.618 + r + clkgate_9/gopclkgate/OUT + + + + net (fanout=1) + 0.000 + 7.618 + + ntclkgate_0 + + + IOCKDIV_6_323/CLK_IODIV + td + 0.000 + 7.618 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + + + + net (fanout=1) + 2.191 + 9.809 + + u_axi_ddr_top/clk + + + USCM_84_116/CLK_USCM + td + 0.000 + 9.809 + r + clkbufg_0/gopclkbufg/CLKOUT + + + + net (fanout=5464) + 1.585 + 11.394 + + ntclkbufg_0 + + + CLMA_38_196/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[6]/opit_0_inv_L5Q_perm/CLK + + + clock pessimism + + -0.693 + 10.701 + + + + + clock uncertainty + + 0.000 + 10.701 + + + + + Removal time + + 0.000 + 10.701 + + + +
+
+
+
+ + 0.637 + 1 + 729 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[7]/opit_0_inv_L5Q_perm/RS + + ddrphy_clkin + ddrphy_clkin + rise-rise + 0.036 + 10.665 + 11.394 + -0.693 + 0.000 + 0.673 + 0.327 (48.6%) + 0.346 (51.4%) + + Path #7: removal slack is 0.637(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ddrphy_clkin (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.096 + 2.784 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.059 + 3.843 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 3.843 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.665 + 5.508 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.123 + 5.631 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.102 + 6.733 + + clkout0_wl_0 + + + IOCKGATE_6_322/OUT + td + 0.249 + 6.982 + r + clkgate_9/gopclkgate/OUT + + + + net (fanout=1) + 0.000 + 6.982 + + ntclkgate_0 + + + IOCKDIV_6_323/CLK_IODIV + td + 0.000 + 6.982 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + + + + net (fanout=1) + 2.152 + 9.134 + + u_axi_ddr_top/clk + + + USCM_84_116/CLK_USCM + td + 0.000 + 9.134 + r + clkbufg_0/gopclkbufg/CLKOUT + + + + net (fanout=5464) + 1.531 + 10.665 + + ntclkbufg_0 + + + CLMA_46_192/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK + + + CLMA_46_192/Q0 + tco + 0.222 + 10.887 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q + + + + net (fanout=729) + 0.346 + 11.233 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n + + + CLMA_38_192/RSCO + td + 0.105 + 11.338 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[57]/opit_0_inv/RSOUT + + + + net (fanout=4) + 0.000 + 11.338 + + ntR984 + + + CLMA_38_196/RSCI + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[7]/opit_0_inv_L5Q_perm/RS + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ddrphy_clkin (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.101 + 3.204 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.078 + 4.282 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 4.282 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.738 + 6.020 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.129 + 6.149 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.121 + 7.270 + + clkout0_wl_0 + + + IOCKGATE_6_322/OUT + td + 0.348 + 7.618 + r + clkgate_9/gopclkgate/OUT + + + + net (fanout=1) + 0.000 + 7.618 + + ntclkgate_0 + + + IOCKDIV_6_323/CLK_IODIV + td + 0.000 + 7.618 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + + + + net (fanout=1) + 2.191 + 9.809 + + u_axi_ddr_top/clk + + + USCM_84_116/CLK_USCM + td + 0.000 + 9.809 + r + clkbufg_0/gopclkbufg/CLKOUT + + + + net (fanout=5464) + 1.585 + 11.394 + + ntclkbufg_0 + + + CLMA_38_196/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[7]/opit_0_inv_L5Q_perm/CLK + + + clock pessimism + + -0.693 + 10.701 + + + + + clock uncertainty + + 0.000 + 10.701 + + + + + Removal time + + 0.000 + 10.701 + + + +
+
+
+
+ + 0.637 + 1 + 729 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[8]/opit_0_inv_L5Q_perm/RS + + ddrphy_clkin + ddrphy_clkin + rise-rise + 0.036 + 10.665 + 11.394 + -0.693 + 0.000 + 0.673 + 0.327 (48.6%) + 0.346 (51.4%) + + Path #8: removal slack is 0.637(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ddrphy_clkin (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.096 + 2.784 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.059 + 3.843 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 3.843 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.665 + 5.508 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.123 + 5.631 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.102 + 6.733 + + clkout0_wl_0 + + + IOCKGATE_6_322/OUT + td + 0.249 + 6.982 + r + clkgate_9/gopclkgate/OUT + + + + net (fanout=1) + 0.000 + 6.982 + + ntclkgate_0 + + + IOCKDIV_6_323/CLK_IODIV + td + 0.000 + 6.982 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + + + + net (fanout=1) + 2.152 + 9.134 + + u_axi_ddr_top/clk + + + USCM_84_116/CLK_USCM + td + 0.000 + 9.134 + r + clkbufg_0/gopclkbufg/CLKOUT + + + + net (fanout=5464) + 1.531 + 10.665 + + ntclkbufg_0 + + + CLMA_46_192/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK + + + CLMA_46_192/Q0 + tco + 0.222 + 10.887 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q + + + + net (fanout=729) + 0.346 + 11.233 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n + + + CLMA_38_192/RSCO + td + 0.105 + 11.338 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[57]/opit_0_inv/RSOUT + + + + net (fanout=4) + 0.000 + 11.338 + + ntR984 + + + CLMA_38_196/RSCI + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[8]/opit_0_inv_L5Q_perm/RS + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ddrphy_clkin (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.101 + 3.204 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.078 + 4.282 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 4.282 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.738 + 6.020 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.129 + 6.149 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 1.121 + 7.270 + + clkout0_wl_0 + + + IOCKGATE_6_322/OUT + td + 0.348 + 7.618 + r + clkgate_9/gopclkgate/OUT + + + + net (fanout=1) + 0.000 + 7.618 + + ntclkgate_0 + + + IOCKDIV_6_323/CLK_IODIV + td + 0.000 + 7.618 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + + + + net (fanout=1) + 2.191 + 9.809 + + u_axi_ddr_top/clk + + + USCM_84_116/CLK_USCM + td + 0.000 + 9.809 + r + clkbufg_0/gopclkbufg/CLKOUT + + + + net (fanout=5464) + 1.585 + 11.394 + + ntclkbufg_0 + + + CLMA_38_196/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[8]/opit_0_inv_L5Q_perm/CLK + + + clock pessimism + + -0.693 + 10.701 + + + + + clock uncertainty + + 0.000 + 10.701 + + + + + Removal time + + 0.000 + 10.701 + + + +
+
+
+
+ + 0.891 + 0 + 22 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/training_error_d[1]/opit_0_inv/RS + + clk_200m + clk_200m + rise-rise + 0.036 + 5.374 + 5.867 + -0.457 + 0.000 + 0.707 + 0.222 (31.4%) + 0.485 (68.6%) + + Path #9: removal slack is 0.891(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_200m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.096 + 2.784 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.059 + 3.843 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 3.843 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.531 + 5.374 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + CLMA_58_184/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q/CLK + + + CLMA_58_184/Q0 + tco + 0.222 + 5.596 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q/Q + + + + net (fanout=22) + 0.485 + 6.081 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/logic_rstn + + + CLMA_50_196/RS + + + + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/training_error_d[1]/opit_0_inv/RS + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_200m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.101 + 3.204 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.078 + 4.282 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 4.282 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.585 + 5.867 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + CLMA_50_196/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/training_error_d[1]/opit_0_inv/CLK + + + clock pessimism + + -0.457 + 5.410 + + + + + clock uncertainty + + 0.000 + 5.410 + + + + + Removal time + + -0.220 + 5.190 + + + +
+
+
+
+ + 0.984 + 0 + 911 + sync_vg_100m/opit_0_inv_L5Q_perm/CLK + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0] + + clk_720p60Hz + clk_720p60Hz + rise-rise + 0.056 + 8.952 + 9.557 + -0.549 + 0.000 + 1.018 + 0.222 (21.8%) + 0.796 (78.2%) + + Path #10: removal slack is 0.984(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_720p60Hz (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.100 + 2.788 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.059 + 3.847 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 3.847 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.786 + 5.633 + + ntR3950 + + + PLL_158_303/CLK_OUT1 + td + 0.096 + 5.729 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.571 + 7.300 + + nt_pix_clk + + + USCM_84_117/CLK_USCM + td + 0.000 + 7.300 + r + clkbufg_2/gopclkbufg/CLKOUT + + + + net (fanout=1635) + 1.652 + 8.952 + + ntclkbufg_2 + + + CLMA_150_276/CLK + + + + r + sync_vg_100m/opit_0_inv_L5Q_perm/CLK + + + CLMA_150_276/Q0 + tco + 0.222 + 9.174 + f + sync_vg_100m/opit_0_inv_L5Q_perm/Q + + + + net (fanout=911) + 0.796 + 9.970 + + sync_vg_100m + + + DRM_178_272/RSTB[0] + + + + f + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0] + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_720p60Hz (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.107 + 3.210 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.078 + 4.288 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 4.288 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.861 + 6.149 + + ntR3950 + + + PLL_158_303/CLK_OUT1 + td + 0.101 + 6.250 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.599 + 7.849 + + nt_pix_clk + + + USCM_84_117/CLK_USCM + td + 0.000 + 7.849 + r + clkbufg_2/gopclkbufg/CLKOUT + + + + net (fanout=1635) + 1.708 + 9.557 + + ntclkbufg_2 + + + DRM_178_272/CLKB[0] + + + + r + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] + + + clock pessimism + + -0.549 + 9.008 + + + + + clock uncertainty + + 0.000 + 9.008 + + + + + Removal time + + -0.022 + 8.986 + + + +
+
+
+
+ + 1.249 + 0 + 114 + u_zoom_rst/rst/opit_0_L5Q_perm/CLK + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[6].U_GTP_DRM18K/iGopDrm/RSTA[0] + + clk_1080p60Hz + clk_1080p60Hz + rise-rise + 0.054 + 8.835 + 9.440 + -0.551 + 0.000 + 1.230 + 0.226 (18.4%) + 1.004 (81.6%) + + Path #11: removal slack is 1.249(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_1080p60Hz (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.100 + 2.788 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.059 + 3.847 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 3.847 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.786 + 5.633 + + ntR3950 + + + PLL_158_303/CLK_OUT0 + td + 0.100 + 5.733 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=1) + 1.571 + 7.304 + + zoom_clk + + + USCM_84_118/CLK_USCM + td + 0.000 + 7.304 + r + clkbufg_3/gopclkbufg/CLKOUT + + + + net (fanout=750) + 1.531 + 8.835 + + ntclkbufg_3 + + + CLMA_170_124/CLK + + + + r + u_zoom_rst/rst/opit_0_L5Q_perm/CLK + + + CLMA_170_124/Q0 + tco + 0.226 + 9.061 + r + u_zoom_rst/rst/opit_0_L5Q_perm/Q + + + + net (fanout=114) + 1.004 + 10.065 + + zoom_rst + + + DRM_234_128/RSTA[0] + + + + r + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[6].U_GTP_DRM18K/iGopDrm/RSTA[0] + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_1080p60Hz (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.107 + 3.210 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.078 + 4.288 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 4.288 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.861 + 6.149 + + ntR3950 + + + PLL_158_303/CLK_OUT0 + td + 0.107 + 6.256 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=1) + 1.599 + 7.855 + + zoom_clk + + + USCM_84_118/CLK_USCM + td + 0.000 + 7.855 + r + clkbufg_3/gopclkbufg/CLKOUT + + + + net (fanout=750) + 1.585 + 9.440 + + ntclkbufg_3 + + + DRM_234_128/CLKA[0] + + + + r + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[6].U_GTP_DRM18K/iGopDrm/CLKA[0] + + + clock pessimism + + -0.551 + 8.889 + + + + + clock uncertainty + + 0.000 + 8.889 + + + + + Removal time + + -0.073 + 8.816 + + + +
+
+
+
+ + 1.263 + 0 + 3 + rstn_out1/opit_0_inv/CLK + ms72xx_ctl/rstn_temp1/opit_0_inv/RS + + clk_10m + clk_10m + rise-rise + 0.177 + 5.378 + 5.996 + -0.441 + 0.000 + 1.214 + 0.226 (18.6%) + 0.988 (81.4%) + + Path #12: removal slack is 1.263(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_10m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT4 + td + 0.100 + 2.788 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT4 + + + + net (fanout=1) + 1.059 + 3.847 + + clk_10m + + + USCM_84_110/CLK_USCM + td + 0.000 + 3.847 + r + clkbufg_4/gopclkbufg/CLKOUT + + + + net (fanout=235) + 1.531 + 5.378 + + ntclkbufg_4 + + + CLMS_270_193/CLK + + + + r + rstn_out1/opit_0_inv/CLK + + + CLMS_270_193/Q3 + tco + 0.226 + 5.604 + r + rstn_out1/opit_0_inv/Q + + + + net (fanout=3) + 0.988 + 6.592 + + nt_eth_rstn + + + CLMA_262_268/RS + + + + r + ms72xx_ctl/rstn_temp1/opit_0_inv/RS + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_10m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT4 + td + 0.107 + 3.210 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT4 + + + + net (fanout=1) + 1.078 + 4.288 + + clk_10m + + + USCM_84_110/CLK_USCM + td + 0.000 + 4.288 + r + clkbufg_4/gopclkbufg/CLKOUT + + + + net (fanout=235) + 1.708 + 5.996 + + ntclkbufg_4 + + + CLMA_262_268/CLK + + + + r + ms72xx_ctl/rstn_temp1/opit_0_inv/CLK + + + clock pessimism + + -0.441 + 5.555 + + + + + clock uncertainty + + 0.000 + 5.555 + + + + + Removal time + + -0.226 + 5.329 + + + +
+
+
+
+ + 1.286 + 3 + 911 + sync_vg_100m/opit_0_inv_L5Q_perm/CLK + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/RS + + clk_720p60Hz + clk_720p60Hz + rise-rise + 0.056 + 8.952 + 9.557 + -0.549 + 0.000 + 1.342 + 0.541 (40.3%) + 0.801 (59.7%) + + Path #13: removal slack is 1.286(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_720p60Hz (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.100 + 2.788 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.059 + 3.847 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 3.847 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.786 + 5.633 + + ntR3950 + + + PLL_158_303/CLK_OUT1 + td + 0.096 + 5.729 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.571 + 7.300 + + nt_pix_clk + + + USCM_84_117/CLK_USCM + td + 0.000 + 7.300 + r + clkbufg_2/gopclkbufg/CLKOUT + + + + net (fanout=1635) + 1.652 + 8.952 + + ntclkbufg_2 + + + CLMA_150_276/CLK + + + + r + sync_vg_100m/opit_0_inv_L5Q_perm/CLK + + + CLMA_150_276/Q0 + tco + 0.226 + 9.178 + r + sync_vg_100m/opit_0_inv_L5Q_perm/Q + + + + net (fanout=911) + 0.801 + 9.979 + + sync_vg_100m + + + CLMA_182_281/RSCO + td + 0.105 + 10.084 + r + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_L5Q_perm/RSOUT + + + + net (fanout=3) + 0.000 + 10.084 + + ntR691 + + + CLMA_182_285/RSCO + td + 0.105 + 10.189 + r + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[10]/opit_0_inv_L5Q_perm/RSOUT + + + + net (fanout=4) + 0.000 + 10.189 + + ntR690 + + + CLMA_182_289/RSCO + td + 0.105 + 10.294 + r + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/RSOUT + + + + net (fanout=5) + 0.000 + 10.294 + + ntR689 + + + CLMA_182_293/RSCI + + + + r + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/RS + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_720p60Hz (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.107 + 3.210 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.078 + 4.288 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 4.288 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.861 + 6.149 + + ntR3950 + + + PLL_158_303/CLK_OUT1 + td + 0.101 + 6.250 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.599 + 7.849 + + nt_pix_clk + + + USCM_84_117/CLK_USCM + td + 0.000 + 7.849 + r + clkbufg_2/gopclkbufg/CLKOUT + + + + net (fanout=1635) + 1.708 + 9.557 + + ntclkbufg_2 + + + CLMA_182_293/CLK + + + + r + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/CLK + + + clock pessimism + + -0.549 + 9.008 + + + + + clock uncertainty + + 0.000 + 9.008 + + + + + Removal time + + 0.000 + 9.008 + + + +
+
+
+
+ + 1.286 + 3 + 911 + sync_vg_100m/opit_0_inv_L5Q_perm/CLK + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm/RS + + clk_720p60Hz + clk_720p60Hz + rise-rise + 0.056 + 8.952 + 9.557 + -0.549 + 0.000 + 1.342 + 0.541 (40.3%) + 0.801 (59.7%) + + Path #14: removal slack is 1.286(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_720p60Hz (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.100 + 2.788 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.059 + 3.847 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 3.847 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.786 + 5.633 + + ntR3950 + + + PLL_158_303/CLK_OUT1 + td + 0.096 + 5.729 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.571 + 7.300 + + nt_pix_clk + + + USCM_84_117/CLK_USCM + td + 0.000 + 7.300 + r + clkbufg_2/gopclkbufg/CLKOUT + + + + net (fanout=1635) + 1.652 + 8.952 + + ntclkbufg_2 + + + CLMA_150_276/CLK + + + + r + sync_vg_100m/opit_0_inv_L5Q_perm/CLK + + + CLMA_150_276/Q0 + tco + 0.226 + 9.178 + r + sync_vg_100m/opit_0_inv_L5Q_perm/Q + + + + net (fanout=911) + 0.801 + 9.979 + + sync_vg_100m + + + CLMA_182_281/RSCO + td + 0.105 + 10.084 + r + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_L5Q_perm/RSOUT + + + + net (fanout=3) + 0.000 + 10.084 + + ntR691 + + + CLMA_182_285/RSCO + td + 0.105 + 10.189 + r + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[10]/opit_0_inv_L5Q_perm/RSOUT + + + + net (fanout=4) + 0.000 + 10.189 + + ntR690 + + + CLMA_182_289/RSCO + td + 0.105 + 10.294 + r + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/RSOUT + + + + net (fanout=5) + 0.000 + 10.294 + + ntR689 + + + CLMA_182_293/RSCI + + + + r + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm/RS + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_720p60Hz (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.107 + 3.210 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.078 + 4.288 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 4.288 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.861 + 6.149 + + ntR3950 + + + PLL_158_303/CLK_OUT1 + td + 0.101 + 6.250 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 1.599 + 7.849 + + nt_pix_clk + + + USCM_84_117/CLK_USCM + td + 0.000 + 7.849 + r + clkbufg_2/gopclkbufg/CLKOUT + + + + net (fanout=1635) + 1.708 + 9.557 + + ntclkbufg_2 + + + CLMA_182_293/CLK + + + + r + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm/CLK + + + clock pessimism + + -0.549 + 9.008 + + + + + clock uncertainty + + 0.000 + 9.008 + + + + + Removal time + + 0.000 + 9.008 + + + +
+
+
+
+ + 1.303 + 0 + 114 + u_zoom_rst/rst/opit_0_L5Q_perm/CLK + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/RSTA[0] + + clk_1080p60Hz + clk_1080p60Hz + rise-rise + 0.036 + 8.835 + 9.440 + -0.569 + 0.000 + 1.266 + 0.226 (17.9%) + 1.040 (82.1%) + + Path #15: removal slack is 1.303(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_1080p60Hz (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.100 + 2.788 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.059 + 3.847 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 3.847 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.786 + 5.633 + + ntR3950 + + + PLL_158_303/CLK_OUT0 + td + 0.100 + 5.733 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=1) + 1.571 + 7.304 + + zoom_clk + + + USCM_84_118/CLK_USCM + td + 0.000 + 7.304 + r + clkbufg_3/gopclkbufg/CLKOUT + + + + net (fanout=750) + 1.531 + 8.835 + + ntclkbufg_3 + + + CLMA_170_124/CLK + + + + r + u_zoom_rst/rst/opit_0_L5Q_perm/CLK + + + CLMA_170_124/Q0 + tco + 0.226 + 9.061 + r + u_zoom_rst/rst/opit_0_L5Q_perm/Q + + + + net (fanout=114) + 1.040 + 10.101 + + zoom_rst + + + DRM_234_88/RSTA[0] + + + + r + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/RSTA[0] + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_1080p60Hz (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.107 + 3.210 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.078 + 4.288 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 4.288 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.861 + 6.149 + + ntR3950 + + + PLL_158_303/CLK_OUT0 + td + 0.107 + 6.256 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=1) + 1.599 + 7.855 + + zoom_clk + + + USCM_84_118/CLK_USCM + td + 0.000 + 7.855 + r + clkbufg_3/gopclkbufg/CLKOUT + + + + net (fanout=750) + 1.585 + 9.440 + + ntclkbufg_3 + + + DRM_234_88/CLKA[0] + + + + r + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] + + + clock pessimism + + -0.569 + 8.871 + + + + + clock uncertainty + + 0.000 + 8.871 + + + + + Removal time + + -0.073 + 8.798 + + + +
+
+
+
+ + 1.383 + 0 + 114 + u_zoom_rst/rst/opit_0_L5Q_perm/CLK + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[7].U_GTP_DRM18K/iGopDrm/RSTA[0] + + clk_1080p60Hz + clk_1080p60Hz + rise-rise + 0.036 + 8.835 + 9.440 + -0.569 + 0.000 + 1.346 + 0.226 (16.8%) + 1.120 (83.2%) + + Path #16: removal slack is 1.383(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_1080p60Hz (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.808 + 1.882 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.882 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.048 + 1.930 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.758 + 2.688 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.100 + 2.788 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.059 + 3.847 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 3.847 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.786 + 5.633 + + ntR3950 + + + PLL_158_303/CLK_OUT0 + td + 0.100 + 5.733 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=1) + 1.571 + 7.304 + + zoom_clk + + + USCM_84_118/CLK_USCM + td + 0.000 + 7.304 + r + clkbufg_3/gopclkbufg/CLKOUT + + + + net (fanout=750) + 1.531 + 8.835 + + ntclkbufg_3 + + + CLMA_170_124/CLK + + + + r + u_zoom_rst/rst/opit_0_L5Q_perm/CLK + + + CLMA_170_124/Q0 + tco + 0.226 + 9.061 + r + u_zoom_rst/rst/opit_0_L5Q_perm/Q + + + + net (fanout=114) + 1.120 + 10.181 + + zoom_rst + + + DRM_234_108/RSTA[0] + + + + r + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[7].U_GTP_DRM18K/iGopDrm/RSTA[0] + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_1080p60Hz (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 2.166 + 2.240 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 2.240 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.076 + 2.316 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.787 + 3.103 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.107 + 3.210 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 1.078 + 4.288 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 4.288 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.861 + 6.149 + + ntR3950 + + + PLL_158_303/CLK_OUT0 + td + 0.107 + 6.256 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=1) + 1.599 + 7.855 + + zoom_clk + + + USCM_84_118/CLK_USCM + td + 0.000 + 7.855 + r + clkbufg_3/gopclkbufg/CLKOUT + + + + net (fanout=750) + 1.585 + 9.440 + + ntclkbufg_3 + + + DRM_234_108/CLKA[0] + + + + r + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[7].U_GTP_DRM18K/iGopDrm/CLKA[0] + + + clock pessimism + + -0.569 + 8.871 + + + + + clock uncertainty + + 0.000 + 8.871 + + + + + Removal time + + -0.073 + 8.798 + + + +
+
+
+
+ + + + Slack + Actual Width + Require Width + Clock + Type + Location + Pin + + + 0.397 + 1.250 + 0.853 + ioclk2 + High Pulse Width + DQSL_6_28/CLK_IO + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_ddc_ca/opit_0/IOCLK + + + 0.397 + 1.250 + 0.853 + ioclk2 + Low Pulse Width + DQSL_6_28/CLK_IO + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_ddc_ca/opit_0/IOCLK + + + 0.397 + 1.250 + 0.853 + ioclk0 + High Pulse Width + DQSL_6_348/CLK_IO + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[1].u_ddc_ca/opit_0/IOCLK + + + 0.397 + 1.250 + 0.853 + ioclk0 + Low Pulse Width + DQSL_6_348/CLK_IO + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[1].u_ddc_ca/opit_0/IOCLK + + + 0.397 + 1.250 + 0.853 + ioclk2 + High Pulse Width + DQSL_6_100/CLK_IO + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[2].u_ddc_ca/opit_0/IOCLK + + + 0.397 + 1.250 + 0.853 + ioclk0 + High Pulse Width + DQSL_6_304/CLK_IO + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[3].u_ddc_ca/opit_0/IOCLK + + + 0.397 + 1.250 + 0.853 + ioclk1 + High Pulse Width + DQSL_6_152/CLK_IO + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + + + 0.397 + 1.250 + 0.853 + ioclk1 + Low Pulse Width + DQSL_6_152/CLK_IO + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + + + 0.397 + 1.250 + 0.853 + ioclk1 + High Pulse Width + DQSL_6_180/CLK_IO + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + + + 1.880 + 2.500 + 0.620 + clk_200m + High Pulse Width + CLMS_34_181/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[0]/opit_0_inv_L5Q_perm/CLK + + + 1.880 + 2.500 + 0.620 + clk_200m + Low Pulse Width + CLMS_34_181/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[0]/opit_0_inv_L5Q_perm/CLK + + + 1.880 + 2.500 + 0.620 + clk_200m + High Pulse Width + CLMS_34_193/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[1]/opit_0_inv_L5Q_perm/CLK + + + 2.230 + 3.368 + 1.138 + clk_1080p60Hz + Low Pulse Width + APM_206_28/CLK + u_zoom_image/mult_fra0/N2/gopapm/CLK + + + 2.230 + 3.368 + 1.138 + clk_1080p60Hz + High Pulse Width + APM_206_28/CLK + u_zoom_image/mult_fra0/N2/gopapm/CLK + + + 2.230 + 3.368 + 1.138 + clk_1080p60Hz + High Pulse Width + APM_206_264/CLK + u_zoom_image/mult_fra0_0/N2/gopapm/CLK + + + 2.435 + 3.333 + 0.898 + hdmi_in_clk + High Pulse Width + DRM_82_128/CLKA[0] + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] + + + 2.435 + 3.333 + 0.898 + hdmi_in_clk + Low Pulse Width + DRM_82_128/CLKA[0] + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] + + + 2.435 + 3.333 + 0.898 + hdmi_in_clk + Low Pulse Width + DRM_82_88/CLKA[0] + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] + + + 2.483 + 4.000 + 1.517 + eth_rxc + High Pulse Width + IOL_71_373/CLK_SYS + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_ctl_in/gateigddr_IOL/SYSCLK + + + 2.483 + 4.000 + 1.517 + eth_rxc + Low Pulse Width + IOL_71_373/CLK_SYS + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_ctl_in/gateigddr_IOL/SYSCLK + + + 2.483 + 4.000 + 1.517 + eth_rxc + Low Pulse Width + IOL_311_374/CLK_SYS + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gtp_outbuft1/opit_1_IOL/SYSCLK + + + 3.100 + 5.000 + 1.900 + ddrphy_clkin + Low Pulse Width + CLMS_38_101/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram16x1d/WCLK + + + 3.100 + 5.000 + 1.900 + ddrphy_clkin + High Pulse Width + CLMS_38_101/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram16x1d/WCLK + + + 3.100 + 5.000 + 1.900 + ddrphy_clkin + Low Pulse Width + CLMS_42_101/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_2/ram16x1d/WCLK + + + 4.580 + 5.000 + 0.420 + ioclk_gate_clk + Low Pulse Width + CLMA_150_192/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_ioclk_gate/opit_0_inv_L5Q_perm/CLK + + + 4.580 + 5.000 + 0.420 + ioclk_gate_clk + High Pulse Width + CLMA_150_192/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_ioclk_gate/opit_0_inv_L5Q_perm/CLK + + + 5.052 + 5.950 + 0.898 + cmos1_pclk + Low Pulse Width + DRM_142_44/CLKA[0] + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] + + + 5.052 + 5.950 + 0.898 + cmos1_pclk + High Pulse Width + DRM_142_44/CLKA[0] + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] + + + 5.052 + 5.950 + 0.898 + cmos2_pclk + Low Pulse Width + DRM_142_24/CLKA[0] + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] + + + 5.052 + 5.950 + 0.898 + cmos2_pclk + High Pulse Width + DRM_142_24/CLKA[0] + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] + + + 5.330 + 5.950 + 0.620 + cmos1_pclk + Low Pulse Width + CLMS_134_25/CLK + u_ov5640/cmos1_8_16bit/de_cnt/opit_0_L5Q_perm/CLK + + + 5.330 + 5.950 + 0.620 + cmos2_pclk + High Pulse Width + CLMS_74_17/CLK + u_ov5640/cmos2_8_16bit/de_in0/opit_0/CLK + + + 5.598 + 6.736 + 1.138 + clk_720p60Hz + High Pulse Width + APM_258_216/CLK + adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N11/gopapm/CLK + + + 5.598 + 6.736 + 1.138 + clk_720p60Hz + High Pulse Width + APM_258_204/CLK + adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N135/gopapm/CLK + + + 5.599 + 6.737 + 1.138 + clk_720p60Hz + Low Pulse Width + APM_258_216/CLK + adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N11/gopapm/CLK + + + 8.862 + 10.000 + 1.138 + clk_50m + Low Pulse Width + APM_206_228/CLK + u_rotate_image/u_rotate_mult0/N2/gopapm/CLK + + + 8.862 + 10.000 + 1.138 + clk_50m + High Pulse Width + APM_206_228/CLK + u_rotate_image/u_rotate_mult0/N2/gopapm/CLK + + + 8.862 + 10.000 + 1.138 + clk_50m + High Pulse Width + APM_206_216/CLK + u_rotate_image/u_rotate_mult1/N2/gopapm/CLK + + + 19.380 + 20.000 + 0.620 + clk_25m + Low Pulse Width + CLMS_122_9/CLK + u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK + + + 19.380 + 20.000 + 0.620 + clk_25m + High Pulse Width + CLMS_122_9/CLK + u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK + + + 19.380 + 20.000 + 0.620 + clk_25m + High Pulse Width + CLMS_122_9/CLK + u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/CLK + + + 49.102 + 50.000 + 0.898 + clk_10m + Low Pulse Width + DRM_234_316/CLKA[0] + ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKA[0] + + + 49.102 + 50.000 + 0.898 + clk_10m + High Pulse Width + DRM_234_316/CLKA[0] + ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKA[0] + + + 49.102 + 50.000 + 0.898 + clk_10m + Low Pulse Width + DRM_234_316/CLKB[0] + ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKB[0] + + + 24999.102 + 25000.000 + 0.898 + clk_20k + High Pulse Width + DRM_142_4/CLKA[0] + u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKA[0] + + + 24999.102 + 25000.000 + 0.898 + clk_20k + Low Pulse Width + DRM_142_4/CLKA[0] + u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKA[0] + + + 24999.102 + 25000.000 + 0.898 + clk_20k + Low Pulse Width + DRM_142_4/CLKB[0] + u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0] + +
+ + + Launch Clock + Capture Clock + WNS(ns) + TNS(ns) + Failing Endpoints + Total Endpoints + + + ioclk1 + ioclk1 + 1.834 + 0.000 + 0 + 72 + + + ioclk0 + ioclk0 + 1.834 + 0.000 + 0 + 24 + + + clk_200m + clk_200m + 2.129 + 0.000 + 0 + 258 + + + clk_1080p60Hz + clk_1080p60Hz + 2.488 + 0.000 + 0 + 3524 + + + eth_rxc + eth_rxc + 3.051 + 0.000 + 0 + 5918 + + + hdmi_in_clk + hdmi_in_clk + 3.150 + 0.000 + 0 + 311 + + + ddrphy_clkin + ddrphy_clkin + 4.645 + 0.000 + 0 + 18286 + + + cmos2_pclk + cmos2_pclk + 5.869 + 0.000 + 0 + 251 + + + cmos1_pclk + cmos1_pclk + 6.435 + 0.000 + 0 + 251 + + + clk_720p60Hz + clk_720p60Hz + 8.191 + 0.000 + 0 + 4786 + + + clk_50m + clk_50m + 12.954 + 0.000 + 0 + 9493 + + + clk_25m + clk_25m + 36.784 + 0.000 + 0 + 30 + + + clk_10m + clk_10m + 96.148 + 0.000 + 0 + 1092 + + + clk_20k + clk_20k + 49996.111 + 0.000 + 0 + 177 + +
+ + + Launch Clock + Capture Clock + WHS(ns) + THS(ns) + Failing Endpoints + Total Endpoints + + + eth_rxc + eth_rxc + 0.075 + 0.000 + 0 + 5918 + + + hdmi_in_clk + hdmi_in_clk + 0.103 + 0.000 + 0 + 311 + + + cmos1_pclk + cmos1_pclk + 0.104 + 0.000 + 0 + 251 + + + ddrphy_clkin + ddrphy_clkin + 0.115 + 0.000 + 0 + 18286 + + + clk_50m + clk_50m + 0.143 + 0.000 + 0 + 9493 + + + clk_1080p60Hz + clk_1080p60Hz + 0.160 + 0.000 + 0 + 3524 + + + clk_10m + clk_10m + 0.232 + 0.000 + 0 + 1092 + + + clk_200m + clk_200m + 0.242 + 0.000 + 0 + 258 + + + cmos2_pclk + cmos2_pclk + 0.250 + 0.000 + 0 + 251 + + + clk_720p60Hz + clk_720p60Hz + 0.252 + 0.000 + 0 + 4786 + + + clk_20k + clk_20k + 0.273 + 0.000 + 0 + 177 + + + ioclk1 + ioclk1 + 0.383 + 0.000 + 0 + 72 + + + ioclk0 + ioclk0 + 0.383 + 0.000 + 0 + 24 + + + clk_25m + clk_25m + 0.388 + 0.000 + 0 + 30 + +
+ + + Launch Clock + Capture Clock + WNS(ns) + TNS(ns) + Failing Endpoints + Total Endpoints + + + clk_200m + clk_200m + 2.160 + 0.000 + 0 + 69 + + + clk_1080p60Hz + clk_1080p60Hz + 4.288 + 0.000 + 0 + 106 + + + ddrphy_clkin + ddrphy_clkin + 6.879 + 0.000 + 0 + 2569 + + + clk_720p60Hz + clk_720p60Hz + 10.123 + 0.000 + 0 + 717 + + + clk_50m + clk_50m + 16.962 + 0.000 + 0 + 192 + + + clk_10m + clk_10m + 98.381 + 0.000 + 0 + 1 + +
+ + + Launch Clock + Capture Clock + WHS(ns) + THS(ns) + Failing Endpoints + Total Endpoints + + + clk_200m + clk_200m + 0.452 + 0.000 + 0 + 69 + + + clk_50m + clk_50m + 0.454 + 0.000 + 0 + 192 + + + ddrphy_clkin + ddrphy_clkin + 0.482 + 0.000 + 0 + 2569 + + + clk_720p60Hz + clk_720p60Hz + 0.722 + 0.000 + 0 + 717 + + + clk_1080p60Hz + clk_1080p60Hz + 0.860 + 0.000 + 0 + 106 + + + clk_10m + clk_10m + 0.873 + 0.000 + 0 + 1 + +
+ + + Clock + WPWS + TPWS + Failing End Point + Total End Point + + + ioclk1 + 0.568 + 0.000 + 0 + 27 + + + ioclk2 + 0.568 + 0.000 + 0 + 2 + + + ioclk0 + 0.568 + 0.000 + 0 + 11 + + + clk_200m + 2.004 + 0.000 + 0 + 75 + + + clk_1080p60Hz + 2.458 + 0.000 + 0 + 750 + + + hdmi_in_clk + 2.615 + 0.000 + 0 + 167 + + + eth_rxc + 2.787 + 0.000 + 0 + 1862 + + + ddrphy_clkin + 3.480 + 0.000 + 0 + 5464 + + + ioclk_gate_clk + 4.664 + 0.000 + 0 + 1 + + + cmos2_pclk + 5.232 + 0.000 + 0 + 118 + + + cmos1_pclk + 5.232 + 0.000 + 0 + 118 + + + clk_720p60Hz + 5.826 + 0.000 + 0 + 1635 + + + clk_50m + 9.090 + 0.000 + 0 + 2516 + + + clk_25m + 19.504 + 0.000 + 0 + 26 + + + clk_10m + 49.282 + 0.000 + 0 + 235 + + + clk_20k + 24999.282 + 0.000 + 0 + 38 + +
+ + + + clk (50.00MHZ) (drive 0 loads) (min_rise, max_rise, min_fall, max_fall) + + clk (0.000, 0.000, 0.000, 0.000) + + clk_ibuf/opit_0/I (0.074, 0.074, 0.074, 0.074) + + clk_ibuf/opit_0/O (1.359, 1.578, 0.970, 1.123) + + clk_ibuf/ntD (net) + + clk_ibuf/opit_1/IN (1.359, 1.578, 0.970, 1.123) + + clk_ibuf/opit_1/INCK (1.397, 1.636, 1.008, 1.180) + + _N69 (net) + + u_sys_pll/u_pll_e3/goppll/CLKIN1 (1.860, 2.114, 1.464, 1.651) + + clk_50m (50.00MHZ) (drive 2516 loads) + + u_sys_pll/u_pll_e3/goppll/CLKOUT0 (1.938, 2.197, 1.540, 1.732) + + rd3_clk (net) + + clkbufg_1/gopclkbufg/CLK (2.541, 2.811, 2.137, 2.340) + + clkbufg_1/gopclkbufg/CLKOUT (2.541, 2.811, 2.137, 2.340) + + ntclkbufg_1 (net) - image_filiter_inst/vector_to_matrix_inst/mat[2][0][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + camera_vs_ff0/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst/vector_to_matrix_inst/mat[2][0][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + camera_vs_ff1/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst/vector_to_matrix_inst/mat[2][0][5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/m_result_data[0]/opit_0_A2Q1/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst/vector_to_matrix_inst/mat[2][0][6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/m_result_data[2]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst/vector_to_matrix_inst/mat[2][0][7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/m_result_data[4]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst/vector_to_matrix_inst/mat[2][0][8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][0][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst/vector_to_matrix_inst/mat[2][0][9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][0][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst/vector_to_matrix_inst/mat[2][0][10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][0][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst/vector_to_matrix_inst/mat[2][0][11]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][0][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst/vector_to_matrix_inst/mat[2][0][12]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][0][4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst/vector_to_matrix_inst/mat[2][0][13]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][1][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst/vector_to_matrix_inst/mat[2][0][14]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][1][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst/vector_to_matrix_inst/mat[2][0][15]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][1][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst/vector_to_matrix_inst/mat[2][1][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][1][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst/vector_to_matrix_inst/mat[2][1][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][1][4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst/vector_to_matrix_inst/mat[2][1][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][2][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst/vector_to_matrix_inst/mat[2][1][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][2][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst/vector_to_matrix_inst/mat[2][1][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][2][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst/vector_to_matrix_inst/mat[2][1][5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][2][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst/vector_to_matrix_inst/mat[2][1][6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][2][4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst/vector_to_matrix_inst/mat[2][1][7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][0][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst/vector_to_matrix_inst/mat[2][1][8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][0][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst/vector_to_matrix_inst/mat[2][1][9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][0][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst/vector_to_matrix_inst/mat[2][1][10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][0][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst/vector_to_matrix_inst/mat[2][1][11]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][0][4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst/vector_to_matrix_inst/mat[2][1][12]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][1][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst/vector_to_matrix_inst/mat[2][1][13]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][1][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst/vector_to_matrix_inst/mat[2][1][14]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][1][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst/vector_to_matrix_inst/mat[2][1][15]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][1][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst/vector_to_matrix_inst/mat[2][2][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][1][4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst/vector_to_matrix_inst/mat[2][2][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][2][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst/vector_to_matrix_inst/mat[2][2][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][2][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst/vector_to_matrix_inst/mat[2][2][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][2][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst/vector_to_matrix_inst/mat[2][2][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][2][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst/vector_to_matrix_inst/mat[2][2][5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][2][4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst/vector_to_matrix_inst/mat[2][2][6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][0][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst/vector_to_matrix_inst/mat[2][2][7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][0][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst/vector_to_matrix_inst/mat[2][2][8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][0][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst/vector_to_matrix_inst/mat[2][2][9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][0][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst/vector_to_matrix_inst/mat[2][2][10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][0][4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst/vector_to_matrix_inst/mat[2][2][11]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][1][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst/vector_to_matrix_inst/mat[2][2][12]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][1][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst/vector_to_matrix_inst/mat[2][2][13]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][1][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst/vector_to_matrix_inst/mat[2][2][14]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][1][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst/vector_to_matrix_inst/mat[2][2][15]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][1][4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst/vector_to_matrix_inst/valid_d/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][2][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/m_result_data[0]/opit_0_A2Q1/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][2][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/m_result_data[2]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][2][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/m_result_data[4]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][2][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][0][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][2][4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][0][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][0][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][0][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][0][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][1][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[5]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][1][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[6]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][1][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[7]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][1][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum1x4[2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][1][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum1x4[3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][2][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum1x4[4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][2][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum1x4[5]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][2][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum1x4[6]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][2][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x1[1]/opit_0_A2Q1/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][2][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x1[3]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][0][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x1[5]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][0][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x1[6]/opit_0_AQ/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][0][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x2[1]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][0][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x2[3]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][0][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x2[5]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][1][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x2[6]/opit_0_AQ/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][1][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum8[1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][1][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum8[3]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][1][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum8[5]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][1][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum8[7]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][2][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum8[8]/opit_0_AQ/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][2][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/m_result_data[0]/opit_0_A2Q1/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][2][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/m_result_data[2]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][2][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/m_result_data[4]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][2][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/m_result_data[5]/opit_0_AQ/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][0][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][0][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][0][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][0][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][0][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][0][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][0][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][0][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][0][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][0][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][1][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][0][5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][1][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][1][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][1][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][1][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][1][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][1][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][1][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][1][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][2][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][1][4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][2][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][1][5]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][2][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][2][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][2][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][2][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][2][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][2][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][2][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][2][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][2][5]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][0][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][0][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][0][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][0][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum1x4[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][0][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum1x4[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][0][5]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum1x4[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][1][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum1x4[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][1][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum1x4[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][1][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x1[1]/opit_0_A2Q1/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][1][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x1[3]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][1][4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x1[5]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][1][5]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x1[6]/opit_0_AQ/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][2][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x2[1]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][2][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x2[3]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][2][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x2[5]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][2][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x2[6]/opit_0_AQ/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][2][4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum8[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][2][5]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum8[3]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][0][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum8[5]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][0][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum8[7]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][0][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum8[8]/opit_0_AQ/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][0][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/m_result_data[0]/opit_0_A2Q1/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][0][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/m_result_data[2]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][0][5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/m_result_data[4]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][1][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/m_result_data[5]/opit_0_AQ/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][1][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][0][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][1][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][0][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][1][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][0][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][1][4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][0][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][1][5]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][0][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][2][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][0][5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][2][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][1][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][2][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][1][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][2][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][1][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][2][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][1][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][2][5]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][1][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][1][5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][2][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][2][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][2][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[5]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][2][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[6]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][2][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[7]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][2][5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[8]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][0][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum1x4[2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][0][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum1x4[3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][0][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum1x4[4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][0][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum1x4[5]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][0][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum1x4[6]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][0][5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum1x4[7]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][1][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x1[1]/opit_0_A2Q1/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][1][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x1[3]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][1][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x1[5]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][1][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x1[7]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][1][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x2[1]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][1][5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x2[3]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][2][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x2[5]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][2][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x2[7]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][2][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum8[1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][2][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum8[3]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][2][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum8[5]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][2][5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum8[7]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][0][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum8[9]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][0][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/m_result_data[0]/opit_0_A2Q1/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][0][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/m_result_data[2]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][0][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/m_result_data[4]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][0][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][0][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][0][5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][0][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][1][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][0][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][1][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][0][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][1][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][0][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][1][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][1][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][1][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][1][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][1][5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][1][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][2][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][1][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][2][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][1][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][2][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][2][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][2][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][2][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][2][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][2][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][2][5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][2][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][2][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][0][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][0][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][0][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][0][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][0][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][1][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][1][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum1x4[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][1][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum1x4[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][1][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum1x4[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][1][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum1x4[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][2][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum1x4[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][2][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum1x4[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][2][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x1[1]/opit_0_A2Q1/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][2][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x1[3]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][2][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x1[5]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][0][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x1[7]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][0][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x2[1]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][0][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x2[3]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][0][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x2[5]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][0][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x2[7]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][1][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum8[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][1][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum8[3]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][1][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum8[5]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][1][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum8[7]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][1][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum8[9]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][2][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/m_result_data[0]/opit_0_A2Q1/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][2][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/m_result_data[2]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][2][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/m_result_data[4]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][2][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][0][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][2][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][0][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/product4x2[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][0][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/product4x2[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][0][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/product4x2[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][0][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/product4x2[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][1][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/product4x2[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][1][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/product4x2[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][1][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/product4x2[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][1][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum1x4[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][1][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum1x4[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][2][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum1x4[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][2][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum1x4[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][2][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum1x4[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][2][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x1[1]/opit_0_A2Q1/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][2][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x1[3]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][0][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x1[5]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][0][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x1[6]/opit_0_AQ/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][0][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x2[1]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][0][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x2[3]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][0][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x2[5]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][1][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x2[6]/opit_0_AQ/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][1][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum8[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][1][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum8[3]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][1][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum8[5]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][1][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum8[7]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][2][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum8[8]/opit_0_AQ/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][2][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/m_result_valid/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][2][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][2][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][2][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][0][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][0][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][0][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][0][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][0][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][1][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][1][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][1][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][1][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][1][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][2][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][2][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][2][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][2][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][2][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/product4x2[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/product4x2[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/product4x2[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/product4x2[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/product4x2[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/product4x2[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/product4x2[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum1x4[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum1x4[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum1x4[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum1x4[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum1x4[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum4x1[1]/opit_0_A2Q1/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum4x1[3]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum4x1[5]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum4x1[6]/opit_0_AQ/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum4x2[1]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum4x2[3]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum4x2[5]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum4x2[6]/opit_0_AQ/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum8[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum8[3]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum8[5]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum8[7]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum8[8]/opit_0_AQ/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/m_result_valid/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/max[0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/max[1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/max[2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/max[3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/max[4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_max[0]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_max[1]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_max[2]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_max[3]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_max[4]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_min[0]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_min[1]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_min[2]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_min[3]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_min[4]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/med[0]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/med[1]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/med[2]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/med[3]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/med[4]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/med_of_vector_med[0]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/med_of_vector_med[1]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/med_of_vector_med[2]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/med_of_vector_med[3]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/med_of_vector_med[4]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/min[0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/min[1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/min[2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/min[3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/min[4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_max[0]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_max[1]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_max[2]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_max[3]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_max[4]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_min[0]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_min[1]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_min[2]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_min[3]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_min[4]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[5]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_max[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_max[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_max[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[5]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_max[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_max[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_min[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_min[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_min[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_min[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[5]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_min[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[5]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med_of_vector_med[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med_of_vector_med[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med_of_vector_med[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med_of_vector_med[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med_of_vector_med[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[5]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_max[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_max[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[5]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_max[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_max[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_max[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_min[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_min[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_min[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[5]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_min[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_min[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[5]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[5]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[5]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max[0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[5]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max[1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max[2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max[3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max[4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max[5]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_max[0]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[5]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_max[1]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_max[2]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_max[3]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_max[4]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_max[5]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_min[0]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[5]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_min[1]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_min[2]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_min[3]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_min[4]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_min[5]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/med[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[5]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/med[1]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/med[2]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/med[3]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/med[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/med[5]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/med_of_vector_med[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[5]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/med_of_vector_med[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/med_of_vector_med[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/med_of_vector_med[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/med_of_vector_med[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/med_of_vector_med[5]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min[0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[5]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min[1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min[2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min[3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min[4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min[5]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_max[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[5]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_max[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_max[2]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_max[3]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_max[4]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_max[5]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_min[0]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[5]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_min[1]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_min[2]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_min[3]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_min[4]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_min[5]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_max[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_max[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_max[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_max[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_max[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_max[5]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_min[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_min[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_min[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_min[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_min[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_min[5]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med[5]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med_of_vector_med[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med_of_vector_med[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med_of_vector_med[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med_of_vector_med[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med_of_vector_med[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med_of_vector_med[5]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_max[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_max[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_max[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_max[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_max[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_max[5]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_min[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_min[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_min[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_min[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_min[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_min[5]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/max[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/max[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/max[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/max[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/max[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/max_of_vector_max[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/max_of_vector_max[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/max_of_vector_max[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/max_of_vector_max[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/max_of_vector_max[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/max_of_vector_min[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/max_of_vector_min[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/max_of_vector_min[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/max_of_vector_min[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/max_of_vector_min[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/med[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/med[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/med[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/med[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/med[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/med_of_vector_med[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/med_of_vector_med[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/med_of_vector_med[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/med_of_vector_med[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/med_of_vector_med[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/min[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/min[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/min[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/min[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/min[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/min_of_vector_max[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/min_of_vector_max[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/min_of_vector_max[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/min_of_vector_max[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/min_of_vector_max[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/min_of_vector_min[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/min_of_vector_min[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/min_of_vector_min[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/min_of_vector_min[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/min_of_vector_min[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[5]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[6]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[7]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[8]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max_of_vector_max[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[9]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max_of_vector_max[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[10]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max_of_vector_max[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[11]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max_of_vector_max[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[12]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max_of_vector_max[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[13]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max_of_vector_min[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[14]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max_of_vector_min[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[15]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max_of_vector_min[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[16]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max_of_vector_min[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[17]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max_of_vector_min[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[18]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/med[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[19]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/med[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[20]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/med[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[21]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/med[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[22]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/med[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[23]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/med_of_vector_med[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[24]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/med_of_vector_med[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[25]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/med_of_vector_med[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[26]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/med_of_vector_med[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[27]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/med_of_vector_med[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[28]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[29]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[30]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[31]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[32]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[33]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min_of_vector_max[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[34]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min_of_vector_max[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[35]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min_of_vector_max[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[36]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min_of_vector_max[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[37]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min_of_vector_max[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[38]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min_of_vector_min[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[39]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min_of_vector_min[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[40]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min_of_vector_min[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[41]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min_of_vector_min[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[42]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min_of_vector_min[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[43]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[44]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[45]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[46]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/pixel_ff[47]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/raw_res_b[0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/raw_res_b[1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/raw_res_b[2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/raw_res_b[3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/raw_res_b[4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/raw_res_g[0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/raw_res_g[1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[11]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/raw_res_g[2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[12]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/raw_res_g[3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[13]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/raw_res_g[4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[14]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/raw_res_g[5]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[15]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/raw_res_r[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[16]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/raw_res_r[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[17]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/raw_res_r[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[18]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/raw_res_r[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[19]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/raw_res_r[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[20]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/res_b[0]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[21]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/res_b[1]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[22]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/res_b[2]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[23]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/res_b[3]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[24]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/res_b[4]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[25]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/res_g[0]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[26]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/res_g[1]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[27]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/res_g[2]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[28]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/res_g[3]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[29]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/res_g[4]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[30]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/res_g[5]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[31]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/res_r[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[32]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/res_r[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[33]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/res_r[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[34]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/res_r[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[35]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/res_r[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[36]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/valid_d[0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[37]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/valid_d[1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[38]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/valid_d[2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[39]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/hybrid_filter_inst/valid_d[3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[40]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[41]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[42]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[43]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[44]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[45]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[11]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[46]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[47]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/raw_res_b[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/raw_res_b[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/raw_res_b[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/raw_res_b[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/raw_res_b[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/raw_res_g[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[11]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/raw_res_g[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/raw_res_g[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/raw_res_g[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/raw_res_g[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/raw_res_g[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/raw_res_r[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/raw_res_r[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/raw_res_r[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/raw_res_r[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/raw_res_r[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[11]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/res_b[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/res_b[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/res_b[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/res_b[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/res_b[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/res_g[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/res_g[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/res_g[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[11]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/res_g[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/res_g[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/res_g[5]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/res_r[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/res_r[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/hor_cnt[0]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/res_r[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/hor_cnt[2]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/res_r[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/hor_cnt[4]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/res_r[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/hor_cnt[6]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/valid_d[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/hor_cnt[7]/opit_0_A2Q0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/valid_d[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/hor_cnt[8]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/valid_d[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/hor_cnt[9]/opit_0_A2Q0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/hybrid_filter_inst/valid_d[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/hor_cnt[10]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/m_pixel_valid/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/rst_s1/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[0]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[2]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[11]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[4]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[6]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[8]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[10]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/tail_ver_cnt[0]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/tail_ver_cnt[2]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/tail_ver_cnt[4]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/tail_ver_cnt[5]/opit_0_AQ_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[11]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/ver_cnt[0]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/ver_cnt[2]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/ver_cnt[3]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/ver_cnt[4]/opit_0_A2Q1/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/ver_cnt[5]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/ver_cnt[6]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/ver_cnt[7]/opit_0_A2Q0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/multiline_buffer_inst/ver_cnt[8]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][0][0]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][0][1]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[11]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][0][2]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][0][3]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][0][4]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][0][5]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][0][6]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][0][7]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][0][8]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][0][9]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[11]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][0][10]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][0][11]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][0][12]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][0][13]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][0][14]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/multiline_buffer_inst/hor_cnt[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][0][15]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/multiline_buffer_inst/hor_cnt[2]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][1][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/hor_cnt[4]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][1][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/hor_cnt[6]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][1][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/hor_cnt[7]/opit_0_A2Q0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][1][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/hor_cnt[8]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][1][4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/hor_cnt[9]/opit_0_A2Q0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][1][5]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/hor_cnt[10]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][1][6]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/m_pixel_valid/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][1][7]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][1][8]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[2]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][1][9]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[4]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][1][10]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[6]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][1][11]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[8]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][1][12]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[10]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][1][13]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][1][14]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[2]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][1][15]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[4]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][2][0]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[5]/opit_0_AQ_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][2][1]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/ver_cnt[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][2][2]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/ver_cnt[2]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][2][3]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/ver_cnt[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][2][4]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/ver_cnt[4]/opit_0_A2Q1/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][2][5]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/ver_cnt[5]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][2][6]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/ver_cnt[6]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][2][7]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/multiline_buffer_inst/ver_cnt[7]/opit_0_A2Q0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][2][8]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/multiline_buffer_inst/ver_cnt[8]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][2][9]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/vector_to_matrix_inst/mat[0][0][0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][2][10]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[0][0][1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][2][11]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/vector_to_matrix_inst/mat[0][0][2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][2][12]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/vector_to_matrix_inst/mat[0][0][3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][2][13]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/vector_to_matrix_inst/mat[0][0][4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][2][14]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/vector_to_matrix_inst/mat[0][0][5]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[0][2][15]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/vector_to_matrix_inst/mat[0][0][6]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][0][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[0][0][7]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][0][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[0][0][8]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][0][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[0][0][9]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][0][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[0][0][10]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][0][4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[0][0][11]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][0][5]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[0][0][12]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][0][6]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[0][0][13]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][0][7]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[0][0][14]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][0][8]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[0][0][15]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][0][9]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[0][1][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][0][10]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[0][1][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][0][11]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/vector_to_matrix_inst/mat[0][1][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][0][12]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/vector_to_matrix_inst/mat[0][1][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][0][13]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/vector_to_matrix_inst/mat[0][1][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][0][14]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/vector_to_matrix_inst/mat[0][1][5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][0][15]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/vector_to_matrix_inst/mat[0][1][6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][1][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[0][1][7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][1][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[0][1][8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][1][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[0][1][9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][1][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[0][1][10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][1][4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[0][1][11]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][1][5]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[0][1][12]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][1][6]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[0][1][13]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][1][7]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[0][1][14]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][1][8]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[0][1][15]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][1][9]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[0][2][0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][1][10]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[0][2][1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][1][11]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/vector_to_matrix_inst/mat[0][2][2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][1][12]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/vector_to_matrix_inst/mat[0][2][3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][1][13]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/vector_to_matrix_inst/mat[0][2][4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][1][14]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/vector_to_matrix_inst/mat[0][2][5]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][1][15]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/vector_to_matrix_inst/mat[0][2][6]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][2][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[0][2][7]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][2][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[0][2][8]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][2][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[0][2][9]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][2][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[0][2][10]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][2][4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[0][2][11]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][2][5]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[0][2][12]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][2][6]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[0][2][13]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][2][7]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[0][2][14]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][2][8]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[0][2][15]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][2][9]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[1][0][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][2][10]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[1][0][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][2][11]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/vector_to_matrix_inst/mat[1][0][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][2][12]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/vector_to_matrix_inst/mat[1][0][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][2][13]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/vector_to_matrix_inst/mat[1][0][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][2][14]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/vector_to_matrix_inst/mat[1][0][5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[1][2][15]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/vector_to_matrix_inst/mat[1][0][6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][0][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[1][0][7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][0][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[1][0][8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][0][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[1][0][9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][0][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[1][0][10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][0][4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[1][0][11]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][0][5]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[1][0][12]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][0][6]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[1][0][13]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][0][7]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[1][0][14]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][0][8]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[1][0][15]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][0][9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/vector_to_matrix_inst/mat[1][1][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][0][10]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[1][1][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][0][11]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/vector_to_matrix_inst/mat[1][1][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][0][12]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/vector_to_matrix_inst/mat[1][1][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][0][13]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/vector_to_matrix_inst/mat[1][1][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][0][14]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/vector_to_matrix_inst/mat[1][1][5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][0][15]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/vector_to_matrix_inst/mat[1][1][6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][1][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[1][1][7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][1][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[1][1][8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][1][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[1][1][9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][1][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[1][1][10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][1][4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[1][1][11]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][1][5]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[1][1][12]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][1][6]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[1][1][13]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][1][7]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[1][1][14]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][1][8]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[1][1][15]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][1][9]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[1][2][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][1][10]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[1][2][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][1][11]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/vector_to_matrix_inst/mat[1][2][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][1][12]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/vector_to_matrix_inst/mat[1][2][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][1][13]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/vector_to_matrix_inst/mat[1][2][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][1][14]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/vector_to_matrix_inst/mat[1][2][5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][1][15]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/vector_to_matrix_inst/mat[1][2][6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][2][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[1][2][7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][2][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[1][2][8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][2][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[1][2][9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][2][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[1][2][10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][2][4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[1][2][11]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][2][5]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[1][2][12]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][2][6]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[1][2][13]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][2][7]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[1][2][14]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][2][8]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[1][2][15]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][2][9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/vector_to_matrix_inst/mat[2][0][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][2][10]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[2][0][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][2][11]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/vector_to_matrix_inst/mat[2][0][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][2][12]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/vector_to_matrix_inst/mat[2][0][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][2][13]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/vector_to_matrix_inst/mat[2][0][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][2][14]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/vector_to_matrix_inst/mat[2][0][5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/mat[2][2][15]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - image_filiter_inst2/vector_to_matrix_inst/mat[2][0][6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst/vector_to_matrix_inst/valid_d/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[2][0][7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/m_result_data[0]/opit_0_A2Q1/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[2][0][8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/m_result_data[2]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[2][0][9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/m_result_data[4]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[2][0][10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][0][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[2][0][11]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][0][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[2][0][12]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][0][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[2][0][13]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][0][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[2][0][14]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][0][4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[2][0][15]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][1][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[2][1][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][1][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[2][1][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][1][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[2][1][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][1][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[2][1][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][1][4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[2][1][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][2][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[2][1][5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][2][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[2][1][6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][2][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[2][1][7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][2][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[2][1][8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][2][4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[2][1][9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][0][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[2][1][10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][0][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[2][1][11]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][0][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[2][1][12]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][0][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[2][1][13]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][0][4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[2][1][14]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][1][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[2][1][15]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][1][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[2][2][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][1][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[2][2][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][1][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[2][2][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][1][4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[2][2][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][2][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[2][2][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][2][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[2][2][5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][2][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[2][2][6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][2][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[2][2][7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][2][4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[2][2][8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][0][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[2][2][9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][0][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[2][2][10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][0][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[2][2][11]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][0][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[2][2][12]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][0][4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[2][2][13]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][1][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[2][2][14]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][1][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/mat[2][2][15]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][1][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - image_filiter_inst2/vector_to_matrix_inst/valid_d/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][1][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/rd3_data_valid0/opit_0_L5Q_perm/CLK (3.471, 3.772, 3.090, 3.326) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][1][4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK (3.448, 3.748, 3.066, 3.302) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][2][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (3.453, 3.753, 3.072, 3.308) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][2][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (3.453, 3.753, 3.072, 3.308) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][2][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (3.449, 3.749, 3.067, 3.303) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][2][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (3.449, 3.749, 3.067, 3.303) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][2][4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (3.444, 3.744, 3.063, 3.299) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_A2Q21/CLK (3.444, 3.744, 3.063, 3.299) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm/CLK (3.453, 3.753, 3.072, 3.308) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm/CLK (3.449, 3.749, 3.067, 3.303) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm/CLK (3.449, 3.749, 3.067, 3.303) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[5]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm/CLK (3.453, 3.753, 3.072, 3.308) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[6]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/CLK (3.449, 3.749, 3.067, 3.303) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[7]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK (3.453, 3.753, 3.072, 3.308) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum1x4[2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/CLK (3.453, 3.753, 3.072, 3.308) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum1x4[3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/CLK (3.449, 3.749, 3.067, 3.303) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum1x4[4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm/CLK (3.448, 3.748, 3.066, 3.302) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum1x4[5]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm/CLK (3.448, 3.748, 3.066, 3.302) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum1x4[6]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm/CLK (3.440, 3.740, 3.059, 3.294) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x1[1]/opit_0_A2Q1/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm/CLK (3.448, 3.748, 3.066, 3.302) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x1[3]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0/CLK (3.464, 3.764, 3.083, 3.319) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x1[5]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/opit_0/CLK (3.471, 3.772, 3.090, 3.326) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x1[6]/opit_0_AQ/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK (3.456, 3.757, 3.075, 3.311) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x2[1]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK (3.456, 3.757, 3.075, 3.311) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x2[3]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK (3.456, 3.757, 3.075, 3.311) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x2[5]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/CLK (3.471, 3.772, 3.090, 3.326) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x2[6]/opit_0_AQ/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/opit_0/CLK (3.463, 3.763, 3.082, 3.317) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum8[1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK (3.463, 3.763, 3.082, 3.317) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum8[3]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/opit_0/CLK (3.463, 3.763, 3.082, 3.317) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum8[5]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/opit_0/CLK (3.463, 3.763, 3.082, 3.317) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum8[7]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[10]/opit_0/CLK (3.448, 3.748, 3.066, 3.302) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum8[8]/opit_0_AQ/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[11]/opit_0/CLK (3.448, 3.748, 3.066, 3.302) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/m_result_data[0]/opit_0_A2Q1/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[0]/opit_0/CLK (3.464, 3.764, 3.083, 3.319) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/m_result_data[2]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/CLK (3.471, 3.772, 3.090, 3.326) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/m_result_data[4]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK (3.464, 3.764, 3.083, 3.319) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/m_result_data[5]/opit_0_AQ/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/CLK (3.464, 3.764, 3.083, 3.319) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][0][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/CLK (3.456, 3.757, 3.075, 3.311) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][0][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[5]/opit_0/CLK (3.471, 3.772, 3.090, 3.326) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][0][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[6]/opit_0/CLK (3.456, 3.757, 3.075, 3.311) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][0][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/CLK (3.448, 3.748, 3.066, 3.302) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][0][4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[8]/opit_0/CLK (3.448, 3.748, 3.066, 3.302) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][0][5]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/CLK (3.448, 3.748, 3.066, 3.302) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][1][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/CLK (3.448, 3.748, 3.066, 3.302) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][1][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[11]/opit_0/CLK (3.440, 3.740, 3.059, 3.294) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][1][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.482, 3.783, 3.101, 3.337) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][1][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.487, 3.787, 3.105, 3.342) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][1][4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.455, 3.755, 3.074, 3.310) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][1][5]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[3].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.460, 3.760, 3.078, 3.314) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][2][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0_A2Q1/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][2][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][2][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][2][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][2][4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][2][5]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][0][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[11]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][0][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][0][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][0][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][0][4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][0][5]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][1][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][1][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][1][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][1][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][1][4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[11]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][1][5]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][2][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][2][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][2][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][2][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][2][4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][2][5]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][0][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][0][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][0][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][0][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][0][4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][0][5]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][1][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][1][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][1][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][1][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][1][4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][1][5]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][2][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][2][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][2][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][2][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][2][4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][2][5]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[5]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[6]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[7]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[8]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum1x4[2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum1x4[3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum1x4[4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum1x4[5]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum1x4[6]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum1x4[7]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x1[1]/opit_0_A2Q1/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x1[3]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x1[5]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x1[7]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x2[1]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x2[3]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x2[5]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x2[7]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum8[1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum8[3]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum8[5]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum8[7]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum8[9]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/m_result_data[0]/opit_0_A2Q1/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/m_result_data[2]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/m_result_data[4]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][0][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][0][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][0][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][0][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][0][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK (3.448, 3.748, 3.066, 3.302) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][1][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (3.453, 3.753, 3.072, 3.308) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][1][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (3.453, 3.753, 3.072, 3.308) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][1][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (3.444, 3.744, 3.063, 3.299) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][1][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (3.444, 3.744, 3.063, 3.299) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][1][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (3.440, 3.740, 3.059, 3.294) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][2][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_A2Q21/CLK (3.440, 3.740, 3.059, 3.294) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][2][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm/CLK (3.453, 3.753, 3.072, 3.308) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][2][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm/CLK (3.456, 3.757, 3.075, 3.311) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][2][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/CLK (3.453, 3.753, 3.072, 3.308) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][2][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK (3.453, 3.753, 3.072, 3.308) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][0][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/CLK (3.440, 3.740, 3.059, 3.294) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][0][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q/CLK (3.440, 3.740, 3.059, 3.294) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][0][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm/CLK (3.448, 3.748, 3.066, 3.302) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][0][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm/CLK (3.448, 3.748, 3.066, 3.302) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][0][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm/CLK (3.448, 3.748, 3.066, 3.302) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][1][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm/CLK (3.448, 3.748, 3.066, 3.302) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][1][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0/CLK (3.461, 3.761, 3.079, 3.315) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][1][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/opit_0/CLK (3.468, 3.769, 3.087, 3.323) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][1][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK (3.461, 3.761, 3.079, 3.315) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][1][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK (3.461, 3.761, 3.079, 3.315) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][2][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK (3.461, 3.761, 3.079, 3.315) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][2][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/CLK (3.452, 3.752, 3.071, 3.306) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][2][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/opit_0/CLK (3.461, 3.761, 3.079, 3.315) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][2][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK (3.448, 3.748, 3.066, 3.302) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][2][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/opit_0/CLK (3.448, 3.748, 3.066, 3.302) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][0][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/opit_0/CLK (3.448, 3.748, 3.066, 3.302) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][0][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[0]/opit_0/CLK (3.461, 3.761, 3.079, 3.315) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][0][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/CLK (3.461, 3.761, 3.079, 3.315) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][0][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK (3.456, 3.757, 3.075, 3.311) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][0][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/CLK (3.461, 3.761, 3.079, 3.315) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][1][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/CLK (3.461, 3.761, 3.079, 3.315) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][1][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[5]/opit_0/CLK (3.452, 3.752, 3.071, 3.306) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][1][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[6]/opit_0/CLK (3.461, 3.761, 3.079, 3.315) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][1][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/CLK (3.452, 3.752, 3.071, 3.306) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][1][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[8]/opit_0/CLK (3.448, 3.748, 3.066, 3.302) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][2][0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/CLK (3.452, 3.752, 3.071, 3.306) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][2][1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.478, 3.779, 3.097, 3.333) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][2][2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.464, 3.764, 3.083, 3.319) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][2][3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK (3.470, 3.771, 3.089, 3.325) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][2][4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (3.461, 3.761, 3.079, 3.315) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/product4x2[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (3.461, 3.761, 3.079, 3.315) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/product4x2[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (3.452, 3.752, 3.071, 3.306) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/product4x2[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (3.452, 3.752, 3.071, 3.306) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/product4x2[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (3.448, 3.748, 3.066, 3.302) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/product4x2[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_A2Q21/CLK (3.448, 3.748, 3.066, 3.302) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/product4x2[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm/CLK (3.456, 3.757, 3.075, 3.311) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/product4x2[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm/CLK (3.456, 3.757, 3.075, 3.311) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum1x4[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm/CLK (3.456, 3.757, 3.075, 3.311) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum1x4[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm/CLK (3.456, 3.757, 3.075, 3.311) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum1x4[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/CLK (3.467, 3.768, 3.086, 3.322) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum1x4[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK (3.467, 3.768, 3.086, 3.322) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum1x4[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/CLK (3.467, 3.768, 3.086, 3.322) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum4x1[1]/opit_0_A2Q1/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/CLK (3.443, 3.743, 3.062, 3.298) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum4x1[3]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm/CLK (3.443, 3.743, 3.062, 3.298) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum4x1[5]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm/CLK (3.443, 3.743, 3.062, 3.298) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum4x1[6]/opit_0_AQ/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm/CLK (3.443, 3.743, 3.062, 3.298) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum4x2[1]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm/CLK (3.440, 3.740, 3.059, 3.294) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum4x2[3]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0/CLK (3.471, 3.772, 3.090, 3.326) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum4x2[5]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/opit_0/CLK (3.453, 3.753, 3.072, 3.308) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum4x2[6]/opit_0_AQ/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK (3.471, 3.772, 3.090, 3.326) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum8[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK (3.483, 3.784, 3.102, 3.338) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum8[3]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK (3.471, 3.772, 3.090, 3.326) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum8[5]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/CLK (3.483, 3.784, 3.102, 3.338) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum8[7]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/opit_0/CLK (3.467, 3.768, 3.086, 3.322) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum8[8]/opit_0_AQ/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK (3.478, 3.779, 3.097, 3.333) + image_filiter_inst2/hybrid_filter_inst/m_result_valid/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/opit_0/CLK (3.475, 3.775, 3.093, 3.330) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/opit_0/CLK (3.475, 3.775, 3.093, 3.330) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[10]/opit_0/CLK (3.470, 3.771, 3.089, 3.325) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[11]/opit_0/CLK (3.470, 3.771, 3.089, 3.325) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[0]/opit_0/CLK (3.483, 3.784, 3.102, 3.338) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/CLK (3.471, 3.772, 3.090, 3.326) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK (3.483, 3.784, 3.102, 3.338) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/CLK (3.471, 3.772, 3.090, 3.326) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/CLK (3.483, 3.784, 3.102, 3.338) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[5]/opit_0/CLK (3.478, 3.779, 3.097, 3.333) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[6]/opit_0/CLK (3.483, 3.784, 3.102, 3.338) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/CLK (3.478, 3.779, 3.097, 3.333) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[8]/opit_0/CLK (3.475, 3.775, 3.093, 3.330) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/CLK (3.478, 3.779, 3.097, 3.333) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/CLK (3.475, 3.775, 3.093, 3.330) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[11]/opit_0/CLK (3.470, 3.771, 3.089, 3.325) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKA (3.455, 3.755, 3.074, 3.310) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0/CLK (3.456, 3.757, 3.075, 3.311) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (3.443, 3.743, 3.062, 3.298) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (3.443, 3.743, 3.062, 3.298) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (3.448, 3.748, 3.066, 3.302) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (3.448, 3.748, 3.066, 3.302) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (3.452, 3.752, 3.071, 3.306) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm/CLK (3.448, 3.748, 3.066, 3.302) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm/CLK (3.440, 3.740, 3.059, 3.294) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm/CLK (3.463, 3.763, 3.082, 3.317) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm/CLK (3.444, 3.744, 3.063, 3.299) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm/CLK (3.444, 3.744, 3.063, 3.299) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm/CLK (3.444, 3.744, 3.063, 3.299) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm/CLK (3.444, 3.744, 3.063, 3.299) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/CLK (3.456, 3.757, 3.075, 3.311) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/CLK (3.456, 3.757, 3.075, 3.311) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0/CLK (3.452, 3.752, 3.071, 3.306) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/opit_0/CLK (3.448, 3.748, 3.066, 3.302) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/opit_0/CLK (3.448, 3.748, 3.066, 3.302) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/opit_0/CLK (3.463, 3.763, 3.082, 3.317) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/opit_0/CLK (3.452, 3.752, 3.071, 3.306) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/opit_0/CLK (3.463, 3.763, 3.082, 3.317) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/opit_0/CLK (3.452, 3.752, 3.071, 3.306) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/opit_0/CLK (3.456, 3.757, 3.075, 3.311) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK (3.456, 3.757, 3.075, 3.311) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/CLK (3.456, 3.757, 3.075, 3.311) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/CLK (3.463, 3.763, 3.082, 3.317) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[1]/opit_0/CLK (3.448, 3.748, 3.066, 3.302) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[2]/opit_0/CLK (3.463, 3.763, 3.082, 3.317) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max[0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[3]/opit_0/CLK (3.448, 3.748, 3.066, 3.302) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max[1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/CLK (3.456, 3.757, 3.075, 3.311) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max[2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[5]/opit_0/CLK (3.475, 3.775, 3.093, 3.330) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max[3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[6]/opit_0/CLK (3.452, 3.752, 3.071, 3.306) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max[4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[7]/opit_0/CLK (3.456, 3.757, 3.075, 3.311) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_max[0]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/CLK (3.456, 3.757, 3.075, 3.311) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_max[1]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[9]/opit_0/CLK (3.456, 3.757, 3.075, 3.311) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_max[2]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm_inv/CLKB (3.460, 3.760, 3.078, 3.314) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_max[3]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_clk50m_rst/rst/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_max[4]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_clk50m_rst/rst0/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_min[0]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_clk50m_rst/rst1/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_min[1]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/clk_cnt[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_min[2]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/clk_cnt[2]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_min[3]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/clk_cnt[4]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_min[4]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/clk_cnt[6]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med[0]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/clk_cnt[8]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med[1]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/clk_cnt[10]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med[2]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/clk_cnt[12]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med[3]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/clk_cnt[14]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med[4]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/clk_cnt[16]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med_of_vector_med[0]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/clk_cnt[18]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med_of_vector_med[1]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/clk_cnt[20]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med_of_vector_med[2]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/clk_cnt[21]/opit_0_AQ/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med_of_vector_med[3]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd0_addr_ctr/image_perimt/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med_of_vector_med[4]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd0_addr_ctr/image_perimt0/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min[0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd0_addr_ctr/image_perimt1/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min[1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd0_sta_reg[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min[2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd0_sta_reg[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min[3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd0_sta_reg[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min[4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[8]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_max[0]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[10]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_max[1]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[12]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_max[2]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[14]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_max[3]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[16]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_max[4]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[18]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_min[0]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[20]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_min[1]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[22]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_min[2]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[24]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_min[3]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[26]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_min[4]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[27]/opit_0_AQ_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_done0/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_done1/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_done_rise/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_valid0/opit_0_inv_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[5]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[2]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[4]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[6]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[7]/opit_0_AQ_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd0_addr_ctr/wr_image_cnt0[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd0_addr_ctr/wr_image_cnt0[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[5]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd0_addr_ctr/wr_image_cnt0[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd0_addr_ctr/wr_image_cnt0[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd0_addr_ctr/wr_image_cnt0[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_h[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_h[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_h[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[5]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_h[4]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_h[6]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_h[8]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_h[10]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[5]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[3]/opit_0/CLK (3.471, 3.772, 3.090, 3.326) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[5]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[5]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[3]/opit_0/CLK (3.471, 3.772, 3.090, 3.326) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[5]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr0[21]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr0[22]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr0[23]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr0[24]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[5]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr0[25]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr2[12]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr2[21]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr2[22]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr2[23]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr2[24]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[5]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr2[25]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr3[12]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr3[21]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr3[22]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr3[23]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max[4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr3[24]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max[5]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr3[25]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_max[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_h0[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_max[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_h0[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_max[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_h0[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_max[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_h0[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_max[4]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_h0[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_max[5]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_h0[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_min[0]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_h0[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_min[1]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_h0[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_min[2]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_h0[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_min[3]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_h0[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_min[4]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_h0[10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_min[5]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_h1[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_h1[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_h1[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_h1[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_h1[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_h1[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med[5]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_h1[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med_of_vector_med[0]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_h1[10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med_of_vector_med[1]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_w0[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med_of_vector_med[2]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_w0[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med_of_vector_med[3]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_w0[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med_of_vector_med[4]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_w0[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med_of_vector_med[5]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_w0[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min[0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_w0[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_w0[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min[2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_w0[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min[3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_w0[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min[4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_w0[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min[5]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_w0[10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_max[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_max[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_max[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[3]/opit_0/CLK (3.471, 3.772, 3.090, 3.326) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_max[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[4]/opit_0/CLK (3.471, 3.772, 3.090, 3.326) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_max[4]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_max[5]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_min[0]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_min[1]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_min[2]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_min[3]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_min[4]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[11]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_min[5]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[13]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[15]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[17]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[19]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[21]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[23]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[25]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[26]/opit_0_AQ/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[8]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[9]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[10]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[11]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[12]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[13]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[14]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[15]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[16]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[17]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[18]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[19]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[20]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[21]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[22]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[3]/opit_0/CLK (3.460, 3.760, 3.078, 3.314) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[9]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/max[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[11]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/max[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[13]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/max[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[15]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/max[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[17]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/max[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[19]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[21]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[23]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/rd_ddr_valid0/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/rd_ddr_valid1/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/rd_ddr_valid2/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/rd_ddr_valid3/opit_0/CLK (3.470, 3.771, 3.089, 3.325) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/rd_ddr_valid4/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/rd_ddr_valid5/opit_0/CLK (3.470, 3.771, 3.089, 3.325) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/rd_image_cnt[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/rd_image_cnt[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/rd_image_cnt[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/rd_image_cnt[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/rd_image_cnt[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/rd_vs0/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/rd_vs1/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max_of_vector_max[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/rd_vs_rise0/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max_of_vector_max[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in1[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max_of_vector_max[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in1[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max_of_vector_max[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in1[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max_of_vector_max[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in1[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max_of_vector_min[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in1[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max_of_vector_min[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in2[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max_of_vector_min[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in2[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max_of_vector_min[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in2[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max_of_vector_min[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in2[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/med[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in2[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/med[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in3[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/med[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in3[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/med[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in3[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/med[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in3[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/med_of_vector_med[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in3[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/med_of_vector_med[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_vary0/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/med_of_vector_med[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/wr_image_cnt1[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/med_of_vector_med[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/wr_image_cnt1[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/med_of_vector_med[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/wr_image_cnt1[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/wr_image_cnt1[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd3_addr_ctr/wr_image_cnt1[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_wr0_addr_ctr/delay_cnt[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_wr0_addr_ctr/delay_cnt[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_wr0_addr_ctr/delay_cnt[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min_of_vector_max[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_wr0_addr_ctr/delay_cnt[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min_of_vector_max[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_wr0_addr_ctr/image_fram_cnt0[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min_of_vector_max[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_wr0_addr_ctr/image_fram_cnt0[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min_of_vector_max[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_wr0_addr_ctr/image_fram_cnt0[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min_of_vector_max[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_wr0_addr_ctr/image_fram_cnt0[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min_of_vector_min[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_wr0_addr_ctr/image_fram_cnt0[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min_of_vector_min[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_wr0_addr_ctr/wr_addr_valid0/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min_of_vector_min[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_wr0_addr_ctr/wr_ddr_addr0[19]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min_of_vector_min[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_wr0_addr_ctr/wr_ddr_addr0[20]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min_of_vector_min[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_wr0_addr_ctr/wr_ddr_addr0[21]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_wr0_addr_ctr/wr_ddr_addr0[22]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_wr0_addr_ctr/wr_ddr_addr0[23]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_wr0_addr_ctr/wr_ddr_done0/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_wr0_addr_ctr/wr_ddr_done1/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_wr0_addr_ctr/wr_ddr_done2/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[5]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_wr0_addr_ctr/wr_sta_reg[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_wr0_addr_ctr/wr_sta_reg[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[7]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_wr0_addr_ctr/wr_sta_reg[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[8]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_wr0_addr_ctr/wr_vs0/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[9]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_wr0_addr_ctr/wr_vs1/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[10]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_wr0_addr_ctr/wr_vs2/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[11]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_wr0_addr_ctr/wr_vs_flag/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[12]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_wr3_addr_ctr/delay_cnt[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[13]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_wr3_addr_ctr/delay_cnt[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[14]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_wr3_addr_ctr/delay_cnt[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[15]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_wr3_addr_ctr/delay_cnt[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[16]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_wr3_addr_ctr/image_fram_cnt0[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[17]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_wr3_addr_ctr/image_fram_cnt0[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[18]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_wr3_addr_ctr/image_fram_cnt0[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[19]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_wr3_addr_ctr/wr_addr_valid0/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[20]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_wr3_addr_ctr/wr_ddr_addr0[19]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[21]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_wr3_addr_ctr/wr_ddr_addr0[20]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[22]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_wr3_addr_ctr/wr_ddr_addr0[21]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[23]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_wr3_addr_ctr/wr_ddr_done0/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[24]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_wr3_addr_ctr/wr_ddr_done1/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[25]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_wr3_addr_ctr/wr_ddr_done2/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[26]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_wr3_addr_ctr/wr_sta_reg[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[27]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_wr3_addr_ctr/wr_sta_reg[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[28]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_wr3_addr_ctr/wr_sta_reg[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[29]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_wr3_addr_ctr/wr_vs0/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[30]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_wr3_addr_ctr/wr_vs1/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[31]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_wr3_addr_ctr/wr_vs2/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[32]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_wr3_addr_ctr/wr_vs_out/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[33]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/vs_15hz/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[34]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/vs_30hz/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[35]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/power_on_delay_inst/camera_pwnd_reg/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[36]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/power_on_delay_inst/camera_rstn_reg/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[37]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/power_on_delay_inst/cnt1[0]/opit_0_inv_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[38]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ov5640/power_on_delay_inst/cnt1[2]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[39]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/power_on_delay_inst/cnt1[4]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[40]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/power_on_delay_inst/cnt1[6]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[41]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ov5640/power_on_delay_inst/cnt1[8]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[42]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/power_on_delay_inst/cnt1[10]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[43]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ov5640/power_on_delay_inst/cnt1[12]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[44]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ov5640/power_on_delay_inst/cnt1[14]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[45]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ov5640/power_on_delay_inst/cnt1[16]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[46]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ov5640/power_on_delay_inst/cnt1[18]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[47]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ov5640/power_on_delay_inst/cnt2[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/raw_res_b[0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/power_on_delay_inst/cnt2[2]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/raw_res_b[1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/power_on_delay_inst/cnt2[4]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/raw_res_b[2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/power_on_delay_inst/cnt2[6]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/raw_res_b[3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/power_on_delay_inst/cnt2[8]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/raw_res_b[4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/power_on_delay_inst/cnt2[10]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/raw_res_g[0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/power_on_delay_inst/cnt2[12]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/raw_res_g[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ov5640/power_on_delay_inst/cnt2[14]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/raw_res_g[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ov5640/power_on_delay_inst/cnt2[15]/opit_0_AQ/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/raw_res_g[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ov5640/u_mix_image/data_out1[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/raw_res_g[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ov5640/u_mix_image/data_out1[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/raw_res_g[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ov5640/u_mix_image/data_out1[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/raw_res_r[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ov5640/u_mix_image/data_out1[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/raw_res_r[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ov5640/u_mix_image/data_out1[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/raw_res_r[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ov5640/u_mix_image/data_out1[5]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/raw_res_r[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ov5640/u_mix_image/data_out1[6]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/raw_res_r[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ov5640/u_mix_image/data_out1[7]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/res_b[0]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/data_out1[8]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/res_b[1]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/data_out1[9]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/res_b[2]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/data_out1[10]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/res_b[3]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/data_out1[11]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/res_b[4]/opit_0_MUX4TO1Q/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/data_out1[12]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/res_g[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ov5640/u_mix_image/data_out1[13]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/res_g[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ov5640/u_mix_image/data_out1[14]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/res_g[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ov5640/u_mix_image/data_out1[15]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/res_g[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ov5640/u_mix_image/data_out_valid0/opit_0_inv_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/res_g[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ov5640/u_mix_image/data_out_valid1/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/res_g[5]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ov5640/u_mix_image/data_vs/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/res_r[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ov5640/u_mix_image/rd_h[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/res_r[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ov5640/u_mix_image/rd_h[2]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/res_r[2]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ov5640/u_mix_image/rd_h[4]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/res_r[3]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ov5640/u_mix_image/rd_h[6]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/res_r[4]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_ov5640/u_mix_image/rd_h[8]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/valid_d[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ov5640/u_mix_image/rd_h[10]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/valid_d[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ov5640/u_mix_image/rd_sta0[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/valid_d[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ov5640/u_mix_image/rd_sta0[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/hybrid_filter_inst/valid_d[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ov5640/u_mix_image/rd_sta0[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/rd_sta0[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/rd_sta0[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/rd_sta_reg[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/rd_sta_reg[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/rd_sta_reg[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[11]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/rd_sta_reg[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/rd_sta_reg[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/rd_vs0/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/rd_vs1/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/rd_vs2/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/rd_vs_rise/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/rd_w[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/rd_w[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[11]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/rd_w[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/rd_w[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/rd_w[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/rd_w[5]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/rd_w[6]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/rd_w[7]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/rd_w[8]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/rd_w[9]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/rd_w[10]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0_A2Q1/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[11]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[10]/opit_0_inv_AQ/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[11]/opit_0_inv_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/hor_cnt[0]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/hor_cnt[2]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/hor_cnt[4]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/hor_cnt[6]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/hor_cnt[7]/opit_0_A2Q0/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/hor_cnt[8]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/hor_cnt[9]/opit_0_A2Q0/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/hor_cnt[10]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/m_pixel_valid/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[0]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[2]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[4]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[6]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[8]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[10]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[0]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[2]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[4]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[5]/opit_0_AQ/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/ver_cnt[0]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/ver_cnt[2]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/ver_cnt[3]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/ver_cnt[4]/opit_0_A2Q1/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/ver_cnt[5]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/ver_cnt[6]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/ver_cnt[7]/opit_0_A2Q0/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/multiline_buffer_inst/ver_cnt[8]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][0][0]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0_A2Q1/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][0][1]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][0][2]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][0][3]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][0][4]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][0][5]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][0][6]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[10]/opit_0_inv_AQ_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][0][7]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][0][8]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][0][9]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][0][10]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][0][11]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][0][12]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][0][13]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][0][14]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][0][15]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][1][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][1][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][1][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][1][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][1][4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][1][5]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][1][6]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][1][7]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][1][8]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][1][9]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][1][10]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][1][11]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][1][12]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][1][13]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][1][14]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][1][15]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][2][0]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][2][1]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][2][2]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][2][3]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][2][4]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][2][5]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][2][6]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][2][7]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][2][8]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][2][9]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/addr_fifo_valid/opit_0_L5Q_perm/CLK (3.463, 3.763, 3.082, 3.317) + image_filiter_inst2/vector_to_matrix_inst/mat[0][2][10]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/centerX[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][2][11]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/centerX[2]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][2][12]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/centerX[4]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][2][13]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/centerX[6]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][2][14]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/centerX[8]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[0][2][15]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/centerX[10]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[1][0][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/centerX[11]/opit_0_AQ/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[1][0][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/centerY[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[1][0][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/centerY[2]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[1][0][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/centerY[4]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[1][0][4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/centerY[6]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[1][0][5]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/centerY[8]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[1][0][6]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/centerY[10]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[1][0][7]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/centerY[11]/opit_0_AQ/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[1][0][8]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/cnt_h[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[1][0][9]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/cnt_h[2]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[1][0][10]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/cnt_h[4]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[1][0][11]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/cnt_h[6]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[1][0][12]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/cnt_h[8]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[1][0][13]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/cnt_h[10]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[1][0][14]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/cnt_w[0]/opit_0_inv_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[1][0][15]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/cnt_w[2]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[1][1][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/cnt_w[4]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[1][1][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/cnt_w[6]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[1][1][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/cnt_w[8]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[1][1][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/cnt_w[10]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[1][1][4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/data_out2[0]/opit_0_inv/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[1][1][5]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/data_out2[1]/opit_0_inv/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[1][1][6]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/data_out2[2]/opit_0_inv/CLK (3.443, 3.743, 3.062, 3.298) + image_filiter_inst2/vector_to_matrix_inst/mat[1][1][7]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/data_out2[3]/opit_0_inv/CLK (3.443, 3.743, 3.062, 3.298) + image_filiter_inst2/vector_to_matrix_inst/mat[1][1][8]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/data_out2[4]/opit_0_inv/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[1][1][9]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/data_out2[5]/opit_0_inv/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[1][1][10]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/data_out2[6]/opit_0_inv/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[1][1][11]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/data_out2[7]/opit_0_inv/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[1][1][12]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/data_out2[8]/opit_0_inv/CLK (3.459, 3.759, 3.077, 3.313) + image_filiter_inst2/vector_to_matrix_inst/mat[1][1][13]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/data_out2[9]/opit_0_inv/CLK (3.459, 3.759, 3.077, 3.313) + image_filiter_inst2/vector_to_matrix_inst/mat[1][1][14]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/data_out2[10]/opit_0_inv/CLK (3.459, 3.759, 3.077, 3.313) + image_filiter_inst2/vector_to_matrix_inst/mat[1][1][15]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/data_out2[11]/opit_0_inv/CLK (3.459, 3.759, 3.077, 3.313) + image_filiter_inst2/vector_to_matrix_inst/mat[1][2][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/data_out2[12]/opit_0_inv/CLK (3.463, 3.763, 3.082, 3.317) + image_filiter_inst2/vector_to_matrix_inst/mat[1][2][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/data_out2[13]/opit_0_inv/CLK (3.463, 3.763, 3.082, 3.317) + image_filiter_inst2/vector_to_matrix_inst/mat[1][2][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/data_out2[14]/opit_0_inv/CLK (3.459, 3.759, 3.077, 3.313) + image_filiter_inst2/vector_to_matrix_inst/mat[1][2][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/data_out2[15]/opit_0_inv/CLK (3.459, 3.759, 3.077, 3.313) + image_filiter_inst2/vector_to_matrix_inst/mat[1][2][4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/data_out_valid1/opit_0_L5Q_perm/CLK (3.463, 3.763, 3.082, 3.317) + image_filiter_inst2/vector_to_matrix_inst/mat[1][2][5]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/data_out_valid2/opit_0_L5Q_perm/CLK (3.463, 3.763, 3.082, 3.317) + image_filiter_inst2/vector_to_matrix_inst/mat[1][2][6]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/ddr_data_in0[0]/opit_0/CLK (3.476, 3.776, 3.094, 3.331) + image_filiter_inst2/vector_to_matrix_inst/mat[1][2][7]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/ddr_data_in0[1]/opit_0/CLK (3.476, 3.776, 3.094, 3.331) + image_filiter_inst2/vector_to_matrix_inst/mat[1][2][8]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/ddr_data_in0[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[1][2][9]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/ddr_data_in0[3]/opit_0/CLK (3.471, 3.772, 3.090, 3.326) + image_filiter_inst2/vector_to_matrix_inst/mat[1][2][10]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/ddr_data_in0[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[1][2][11]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/ddr_data_in0[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[1][2][12]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/ddr_data_in0[6]/opit_0/CLK (3.483, 3.784, 3.102, 3.338) + image_filiter_inst2/vector_to_matrix_inst/mat[1][2][13]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/ddr_data_in0[7]/opit_0/CLK (3.483, 3.784, 3.102, 3.338) + image_filiter_inst2/vector_to_matrix_inst/mat[1][2][14]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/ddr_data_in0[8]/opit_0/CLK (3.483, 3.784, 3.102, 3.338) + image_filiter_inst2/vector_to_matrix_inst/mat[1][2][15]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/ddr_data_in0[9]/opit_0/CLK (3.471, 3.772, 3.090, 3.326) + image_filiter_inst2/vector_to_matrix_inst/mat[2][0][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/ddr_data_in0[10]/opit_0/CLK (3.471, 3.772, 3.090, 3.326) + image_filiter_inst2/vector_to_matrix_inst/mat[2][0][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/ddr_data_in0[11]/opit_0/CLK (3.476, 3.776, 3.094, 3.331) + image_filiter_inst2/vector_to_matrix_inst/mat[2][0][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/ddr_data_in0[12]/opit_0/CLK (3.476, 3.776, 3.094, 3.331) + image_filiter_inst2/vector_to_matrix_inst/mat[2][0][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/ddr_data_in0[13]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[2][0][4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/ddr_data_in0[14]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[2][0][5]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/ddr_data_in0[15]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[2][0][6]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/ddr_data_in_valid0/opit_0/CLK (3.471, 3.772, 3.090, 3.326) + image_filiter_inst2/vector_to_matrix_inst/mat[2][0][7]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/fifo_data_valid/opit_0_L5Q_perm/CLK (3.463, 3.763, 3.082, 3.317) + image_filiter_inst2/vector_to_matrix_inst/mat[2][0][8]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/image_blank_valid/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[2][0][9]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/image_h_add0[7]/opit_0_A2Q1/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[2][0][10]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/image_h_add0[9]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[2][0][11]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/image_h_add0[11]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[2][0][12]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/image_h_add0[13]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[2][0][13]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/image_h_add0[15]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[2][0][14]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/image_h_add0[17]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[2][0][15]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/image_h_add0[19]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[2][1][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/image_h_add0[21]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[2][1][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/image_h_add0[23]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[2][1][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/image_h_add0[25]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[2][1][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/image_h_add1[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[2][1][4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/image_h_add1[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[2][1][5]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/image_h_add1[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[2][1][6]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/image_h_add1[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[2][1][7]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/image_h_add1[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[2][1][8]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/image_h_add1[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[2][1][9]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/image_h_add1[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[2][1][10]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/image_h_add1[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[2][1][11]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/image_h_add1[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[2][1][12]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/image_h_add1[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[2][1][13]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/image_h_add1[10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[2][1][14]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/image_h_add2[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[2][1][15]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/image_h_add2[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[2][2][0]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/image_h_add2[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[2][2][1]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/image_h_add2[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[2][2][2]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/image_h_add2[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[2][2][3]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/image_h_add2[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[2][2][4]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/image_h_add2[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[2][2][5]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/image_h_add2[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[2][2][6]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/image_h_add2[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[2][2][7]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/image_h_add2[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[2][2][8]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/image_h_add2[10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[2][2][9]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/image_h_add_addr[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[2][2][10]/opit_0/CLK (3.546, 3.848, 3.156, 3.393) - u_rotate_image/image_h_add_addr[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[2][2][11]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/image_h_add_addr[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[2][2][12]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/image_h_add_addr[10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[2][2][13]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/image_h_add_addr[11]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[2][2][14]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/image_h_add_addr[12]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/mat[2][2][15]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/image_h_add_addr[13]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + image_filiter_inst2/vector_to_matrix_inst/valid_d/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/image_h_add_addr[14]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/rd3_data_valid0/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/image_h_add_addr[15]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK (3.456, 3.757, 3.075, 3.311) - u_rotate_image/image_h_add_addr[16]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (3.443, 3.743, 3.062, 3.298) - u_rotate_image/image_h_add_addr[17]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (3.443, 3.743, 3.062, 3.298) - u_rotate_image/image_h_add_addr[18]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (3.448, 3.748, 3.066, 3.302) - u_rotate_image/image_h_blank_valid/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (3.448, 3.748, 3.066, 3.302) - u_rotate_image/image_w_add0[7]/opit_0_A2Q1/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (3.452, 3.752, 3.071, 3.306) - u_rotate_image/image_w_add0[9]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_A2Q21/CLK (3.452, 3.752, 3.071, 3.306) - u_rotate_image/image_w_add0[11]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/image_w_add0[13]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/image_w_add0[15]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/image_w_add0[17]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/image_w_add0[19]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/CLK (3.444, 3.744, 3.063, 3.299) - u_rotate_image/image_w_add0[21]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK (3.456, 3.757, 3.075, 3.311) - u_rotate_image/image_w_add0[23]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/CLK (3.456, 3.757, 3.075, 3.311) - u_rotate_image/image_w_add0[25]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/CLK (3.456, 3.757, 3.075, 3.311) - u_rotate_image/image_w_add1[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm/CLK (3.456, 3.757, 3.075, 3.311) - u_rotate_image/image_w_add1[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm/CLK (3.456, 3.757, 3.075, 3.311) - u_rotate_image/image_w_add1[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm/CLK (3.456, 3.757, 3.075, 3.311) - u_rotate_image/image_w_add1[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm/CLK (3.456, 3.757, 3.075, 3.311) - u_rotate_image/image_w_add1[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0/CLK (3.443, 3.743, 3.062, 3.298) - u_rotate_image/image_w_add1[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/opit_0/CLK (3.451, 3.751, 3.070, 3.305) - u_rotate_image/image_w_add1[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK (3.443, 3.743, 3.062, 3.298) - u_rotate_image/image_w_add1[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK (3.451, 3.751, 3.070, 3.305) - u_rotate_image/image_w_add1[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK (3.451, 3.751, 3.070, 3.305) - u_rotate_image/image_w_add1[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/CLK (3.455, 3.755, 3.074, 3.310) - u_rotate_image/image_w_add1[10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/opit_0/CLK (3.455, 3.755, 3.074, 3.310) - u_rotate_image/image_w_add2[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK (3.471, 3.772, 3.090, 3.326) - u_rotate_image/image_w_add2[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/opit_0/CLK (3.471, 3.772, 3.090, 3.326) - u_rotate_image/image_w_add2[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/opit_0/CLK (3.452, 3.752, 3.071, 3.306) - u_rotate_image/image_w_add2[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[10]/opit_0/CLK (3.452, 3.752, 3.071, 3.306) - u_rotate_image/image_w_add2[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[11]/opit_0/CLK (3.452, 3.752, 3.071, 3.306) - u_rotate_image/image_w_add2[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[0]/opit_0/CLK (3.443, 3.743, 3.062, 3.298) - u_rotate_image/image_w_add2[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/CLK (3.443, 3.743, 3.062, 3.298) - u_rotate_image/image_w_add2[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK (3.451, 3.751, 3.070, 3.305) - u_rotate_image/image_w_add2[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/CLK (3.451, 3.751, 3.070, 3.305) - u_rotate_image/image_w_add2[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/CLK (3.451, 3.751, 3.070, 3.305) - u_rotate_image/image_w_add2[10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[5]/opit_0/CLK (3.455, 3.755, 3.074, 3.310) - u_rotate_image/image_w_add_addr[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[6]/opit_0/CLK (3.455, 3.755, 3.074, 3.310) - u_rotate_image/image_w_add_addr[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/CLK (3.471, 3.772, 3.090, 3.326) - u_rotate_image/image_w_add_addr[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[8]/opit_0/CLK (3.471, 3.772, 3.090, 3.326) - u_rotate_image/image_w_add_addr[10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/CLK (3.452, 3.752, 3.071, 3.306) - u_rotate_image/image_w_add_addr[11]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/CLK (3.452, 3.752, 3.071, 3.306) - u_rotate_image/image_w_add_addr[12]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[11]/opit_0/CLK (3.452, 3.752, 3.071, 3.306) - u_rotate_image/image_w_add_addr[13]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.455, 3.755, 3.074, 3.310) - u_rotate_image/image_w_add_addr[14]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.487, 3.787, 3.105, 3.342) - u_rotate_image/image_w_add_addr[15]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.478, 3.779, 3.097, 3.333) - u_rotate_image/image_w_add_addr[16]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[3].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.464, 3.764, 3.083, 3.319) - u_rotate_image/image_w_add_addr[17]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0_A2Q1/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/image_w_add_addr[18]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/image_w_blank_valid/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/image_w_valid0[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/image_w_valid0[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/image_w_valid0[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/image_w_valid0[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[11]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/image_w_valid0[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/offsetX_ff[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/offsetX_ff[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/offsetX_ff[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/offsetX_ff[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/offsetX_ff[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/offsetX_ff[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/offsetX_ff[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/offsetX_ff[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/offsetX_ff[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[11]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/offsetX_ff[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/offsetX_ff[10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/offsetX_ff[11]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/offsetY_ff[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/offsetY_ff[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/offsetY_ff[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/offsetY_ff[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/offsetY_ff[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/offsetY_ff[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/offsetY_ff[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/offsetY_ff[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/offsetY_ff[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/offsetY_ff[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/offsetY_ff[10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/offsetY_ff[11]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/rd_addr[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/rd_addr[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/rd_addr[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/rd_addr[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/rd_addr[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/rd_addr[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/rd_addr[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/rd_addr[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/rd_ddr_addr_valid1/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/rd_sta_reg[0]/opit_0_MUX4TO1Q/CLK (3.470, 3.771, 3.089, 3.325) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/rd_sta_reg[1]/opit_0_MUX4TO1Q/CLK (3.470, 3.771, 3.089, 3.325) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/rd_sta_reg[2]/opit_0_L5Q_perm/CLK (3.470, 3.771, 3.089, 3.325) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/rd_sta_s2/opit_0_L5Q_perm/CLK (3.459, 3.759, 3.077, 3.313) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/rotate_sta_reg[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/rotate_sta_reg[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/rotate_sta_reg[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_rotate_mult0/N2/gopapm/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_rotate_mult1/N2/gopapm/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_rotate_mult2/N2/gopapm/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_rotate_mult3/N2/gopapm/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_rotate_mult_zoom0/N2/gopapm/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_rotate_mult_zoom1/N2/gopapm/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_rotate_rom/U_ipml_rom_rotate_rom/U_ipml_spram_rotate_rom/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKA (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_rotate_rom/U_ipml_rom_rotate_rom/U_ipml_spram_rotate_rom/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (3.470, 3.771, 3.089, 3.325) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (3.470, 3.771, 3.089, 3.325) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (3.466, 3.766, 3.085, 3.321) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (3.466, 3.766, 3.085, 3.321) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (3.470, 3.771, 3.089, 3.325) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[11]/opit_0_inv_A2Q21/CLK (3.470, 3.771, 3.089, 3.325) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[11]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[1]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[3]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[5]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[7]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[9]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[11]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKA (3.478, 3.779, 3.097, 3.333) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB (3.482, 3.783, 3.101, 3.337) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (3.461, 3.761, 3.079, 3.315) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (3.461, 3.761, 3.079, 3.315) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[10]/opit_0_inv_AQ/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (3.476, 3.776, 3.094, 3.331) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (3.476, 3.776, 3.094, 3.331) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.wbin[10]/opit_0_inv_AQ/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (3.464, 3.764, 3.083, 3.319) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - vs_down_delay_cnt[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - vs_down_delay_cnt[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - vs_down_delay_cnt[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - vs_down_delay_cnt[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - vs_down_delay_cnt[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - vs_down_delay_cnt[5]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - vs_down_delay_cnt[6]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - vs_down_delay_cnt[7]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - vs_down_delay_cnt[8]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - vs_down_delay_cnt[9]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - vs_down_delay_cnt[10]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - vs_down_delay_cnt[11]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - vs_pos_delay_cnt[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - vs_pos_delay_cnt[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - vs_pos_delay_cnt[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - vs_pos_delay_cnt[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - vs_pos_delay_cnt[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - vs_pos_delay_cnt[5]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - vs_pos_delay_cnt[6]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - vs_pos_delay_cnt[7]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.436, 3.736, 3.055, 3.290) - vs_pos_delay_cnt[8]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.436, 3.736, 3.055, 3.290) - vs_pos_delay_cnt[9]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - vs_pos_delay_cnt[10]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - vs_pos_delay_cnt[11]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - wr0_vs/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - - - - - - - - clk_200m (200.00MHZ) (drive 825 loads) - - u_sys_pll/u_pll_e3/goppll/CLKOUT1 (1.934, 2.193, 1.536, 1.728) - - zoom_clk (net) - - USCMROUTE_2/CLK (2.537, 2.807, 2.133, 2.336) - - USCMROUTE_2/CLKOUT (2.537, 2.807, 2.133, 2.336) - - ntR3909 (net) - u_axi_ddr_top/u_axi_rd_connect/rd1_data_valid0/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0_A2Q1/CLK (3.542, 3.844, 3.152, 3.389) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (3.542, 3.844, 3.152, 3.389) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (3.542, 3.844, 3.152, 3.389) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (3.542, 3.844, 3.152, 3.389) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[11]/opit_0_inv_A2Q21/CLK (3.542, 3.844, 3.152, 3.389) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm/CLK (3.542, 3.844, 3.152, 3.389) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/CLK (3.542, 3.844, 3.152, 3.389) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/CLK (3.542, 3.844, 3.152, 3.389) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm/CLK (3.542, 3.844, 3.152, 3.389) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[11]/opit_0_L5Q_perm/CLK (3.542, 3.844, 3.152, 3.389) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/opit_0/CLK (3.542, 3.844, 3.152, 3.389) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/opit_0/CLK (3.542, 3.844, 3.152, 3.389) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/opit_0/CLK (3.542, 3.844, 3.152, 3.389) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/opit_0/CLK (3.542, 3.844, 3.152, 3.389) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/opit_0/CLK (3.542, 3.844, 3.152, 3.389) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK (3.542, 3.844, 3.152, 3.389) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[11]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/CLK (3.542, 3.844, 3.152, 3.389) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[1]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[2]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[3]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/CLK (3.542, 3.844, 3.152, 3.389) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[5]/opit_0/CLK (3.542, 3.844, 3.152, 3.389) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[6]/opit_0/CLK (3.542, 3.844, 3.152, 3.389) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[7]/opit_0/CLK (3.542, 3.844, 3.152, 3.389) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/CLK (3.542, 3.844, 3.152, 3.389) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[9]/opit_0/CLK (3.542, 3.844, 3.152, 3.389) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm_inv/CLKB[0] (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[11]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm_inv/CLKB[0] (3.542, 3.844, 3.152, 3.389) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKA (3.436, 3.736, 3.055, 3.290) - u_axi_rst/rst/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_rst/rst0/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_axi_rst/rst1/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/rd1_vs0/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/delay_cnt[0]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/delay_cnt[1]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/delay_cnt[2]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/gen_start_addr3[19]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/gen_start_addr3[20]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/gen_start_addr3[21]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_addr[7]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_addr[8]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_addr[10]/opit_0_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_addr[12]/opit_0_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_addr[14]/opit_0_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_addr[16]/opit_0_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_addr[18]/opit_0_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_addr[19]/opit_0_AQ/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_h[1]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_h[2]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_h[3]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_h[4]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_h[5]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_h[6]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_h[7]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_h[8]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_h[9]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_h[10]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd1_sta_reg[0]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd1_sta_reg[1]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd1_sta_reg[2]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd3_image_cnt[0]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd3_image_cnt[1]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd3_image_cnt[2]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[7]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[8]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[9]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm_inv/CLKB (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[10]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_clk50m_rst/rst/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[11]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_clk50m_rst/rst0/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[12]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_clk50m_rst/rst1/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[13]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/clk_cnt[0]/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[14]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/clk_cnt[2]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[15]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/clk_cnt[4]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[16]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/clk_cnt[6]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[17]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/clk_cnt[8]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[18]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/clk_cnt[10]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[19]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/clk_cnt[12]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[20]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/clk_cnt[14]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[21]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/clk_cnt[16]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[22]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/clk_cnt[18]/opit_0_A2Q21/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_done0/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/clk_cnt[19]/opit_0_AQ/CLK (3.546, 3.848, 3.156, 3.393) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_done1/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd0_addr_ctr/image_perimt/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_done2/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd0_addr_ctr/image_perimt0/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_valid0/opit_0_inv_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd0_addr_ctr/image_perimt1/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_valid1/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd0_sta_reg[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_vs0/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd0_sta_reg[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_vs1/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd0_sta_reg[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_vs_rise0/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[8]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[10]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[12]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[14]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[16]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.rbin[8]/opit_0_inv_AQ/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[18]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_AQ_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[20]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[22]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[24]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[26]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[27]/opit_0_AQ_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_done0/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.wbin[8]/opit_0_inv_AQ/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_done1/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKA (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_done_rise/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_valid0/opit_0_inv_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/data_in0[0]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/data_in0[1]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[2]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/data_in0[2]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[4]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/data_in1[0]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[6]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/data_in1[1]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[7]/opit_0_AQ/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/data_in1[2]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd0_addr_ctr/wr_image_cnt0[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/data_in2[0]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd0_addr_ctr/wr_image_cnt0[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/data_in2[1]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd0_addr_ctr/wr_image_cnt0[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/data_in2[2]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd0_addr_ctr/wr_image_cnt0[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/data_in3[0]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd0_addr_ctr/wr_image_cnt0[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/data_in3[1]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_h[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/data_in3[2]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_h[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/data_vary0/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_h[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_image_fram_cnt1[0]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_h[4]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_image_fram_cnt1[1]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_h[6]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_image_fram_cnt1[2]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_h[8]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_h[10]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_rst/rst0/opit_0_inv/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_ddr_rst/rst1/opit_0_inv/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[13]/opit_0_inv_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[15]/opit_0_inv_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr0[21]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[12]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr0[22]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[13]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr0[23]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[14]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr0[24]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[15]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr0[25]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr2[12]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr2[21]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr2[22]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr2[23]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr2[24]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr2[25]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr3[12]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr3[21]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr3[22]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr3[23]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[10]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr3[24]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[11]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr3[25]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[12]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_h0[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[13]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_h0[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[14]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_h0[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[15]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_h0[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[5]/opit_0_L6Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_h0[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[6]/opit_0_L6Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_h0[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[7]/opit_0_L6Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_h0[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[8]/opit_0_L6Q/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_h0[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[9]/opit_0_L6Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_h0[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[10]/opit_0_L6Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_h0[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[11]/opit_0_L6Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_h0[10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[12]/opit_0_L6Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_h1[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[0]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_h1[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_h1[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_h1[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_h1[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_h1[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[5]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_h1[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[6]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_h1[10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_w0[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[8]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_w0[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_w0[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_w0[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[11]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_w0[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[12]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_w0[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[13]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_w0[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[14]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_w0[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[15]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_w0[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_w0[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_w0[10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.542, 3.844, 3.152, 3.389) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[3].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[4].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.542, 3.844, 3.152, 3.389) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[6].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.542, 3.844, 3.152, 3.389) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[7].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[8].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.542, 3.844, 3.152, 3.389) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[9].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[10].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.542, 3.844, 3.152, 3.389) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[9]/opit_0/CLK (3.479, 3.780, 3.098, 3.334) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[11].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[12].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[11]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[13].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[13]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[14].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.542, 3.844, 3.152, 3.389) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[15]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[15].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[17]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[19]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[21]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[2].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.542, 3.844, 3.152, 3.389) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[23]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[3].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[25]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[4].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[26]/opit_0_AQ/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[8]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[6].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.542, 3.844, 3.152, 3.389) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[9]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[7].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[10]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[8].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.542, 3.844, 3.152, 3.389) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[11]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[9].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.542, 3.844, 3.152, 3.389) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[12]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[10].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.542, 3.844, 3.152, 3.389) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[13]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[11].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[14]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[12].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[15]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[13].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.542, 3.844, 3.152, 3.389) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[16]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[14].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.542, 3.844, 3.152, 3.389) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[17]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[15].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[18]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/addr_sta_reg[0]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[19]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/addr_sta_reg[1]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[20]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/addr_sta_reg[2]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[21]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/addr_sta_reg[3]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[22]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/addr_sta_reg[4]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/cnt_h[0]/opit_0_L5Q/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/cnt_h[1]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/cnt_h[2]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/cnt_h[3]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/cnt_h[4]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/cnt_h[5]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/cnt_h[6]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[9]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/cnt_h[7]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[11]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/cnt_h[8]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[13]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/cnt_h[9]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[15]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/cnt_h[10]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[17]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/cnt_record_ram[0]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[19]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/cnt_record_ram[1]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[21]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/cnt_record_ram[2]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[23]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/cnt_w[0]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/rd_ddr_valid0/opit_0/CLK (3.476, 3.776, 3.094, 3.331) - u_zoom_image/cnt_w[1]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/rd_ddr_valid1/opit_0/CLK (3.467, 3.768, 3.086, 3.322) - u_zoom_image/cnt_w[2]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/rd_ddr_valid2/opit_0/CLK (3.467, 3.768, 3.086, 3.322) - u_zoom_image/cnt_w[4]/opit_0_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/rd_ddr_valid3/opit_0/CLK (3.467, 3.768, 3.086, 3.322) - u_zoom_image/cnt_w[6]/opit_0_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/rd_ddr_valid4/opit_0/CLK (3.476, 3.776, 3.094, 3.331) - u_zoom_image/cnt_w[8]/opit_0_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/rd_ddr_valid5/opit_0/CLK (3.467, 3.768, 3.086, 3.322) - u_zoom_image/cnt_w[10]/opit_0_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/rd_image_cnt[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/coe_valid[0]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/rd_image_cnt[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/coe_valid[1]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/rd_image_cnt[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/coe_valid[2]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/rd_image_cnt[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/coe_valid[3]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/rd_image_cnt[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_in0[0]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/rd_vs0/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_in0[1]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/rd_vs1/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_in0[2]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/rd_vs_rise0/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_in0[3]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in1[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_in0[4]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in1[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_in0[5]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in1[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_in0[6]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in1[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_in0[7]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in1[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_in0[8]/opit_0/CLK (3.542, 3.844, 3.152, 3.389) + u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in2[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_in0[9]/opit_0/CLK (3.542, 3.844, 3.152, 3.389) + u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in2[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_in0[10]/opit_0/CLK (3.542, 3.844, 3.152, 3.389) + u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in2[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_in0[11]/opit_0/CLK (3.542, 3.844, 3.152, 3.389) + u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in2[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_in0[12]/opit_0/CLK (3.542, 3.844, 3.152, 3.389) + u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in2[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_in0[13]/opit_0/CLK (3.542, 3.844, 3.152, 3.389) + u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in3[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_in0[14]/opit_0/CLK (3.542, 3.844, 3.152, 3.389) + u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in3[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_in0[15]/opit_0/CLK (3.542, 3.844, 3.152, 3.389) + u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in3[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_in_valid0/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in3[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_out1[0]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in3[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_out1[1]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_vary0/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_out1[2]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/wr_image_cnt1[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_out1[3]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/wr_image_cnt1[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_out1[4]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/wr_image_cnt1[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_out1[5]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_rd3_addr_ctr/wr_image_cnt1[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_out1[6]/opit_0/CLK (3.542, 3.844, 3.152, 3.389) + u_ddr_addr_ctr/u_rd3_addr_ctr/wr_image_cnt1[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_out1[7]/opit_0/CLK (3.542, 3.844, 3.152, 3.389) + u_ddr_addr_ctr/u_wr0_addr_ctr/delay_cnt[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_out1[8]/opit_0/CLK (3.542, 3.844, 3.152, 3.389) + u_ddr_addr_ctr/u_wr0_addr_ctr/delay_cnt[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_out1[9]/opit_0/CLK (3.542, 3.844, 3.152, 3.389) + u_ddr_addr_ctr/u_wr0_addr_ctr/delay_cnt[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_out1[10]/opit_0/CLK (3.542, 3.844, 3.152, 3.389) + u_ddr_addr_ctr/u_wr0_addr_ctr/delay_cnt[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_out1[11]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_wr0_addr_ctr/image_fram_cnt0[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_out1[12]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_wr0_addr_ctr/image_fram_cnt0[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_out1[13]/opit_0/CLK (3.542, 3.844, 3.152, 3.389) + u_ddr_addr_ctr/u_wr0_addr_ctr/image_fram_cnt0[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_out1[14]/opit_0/CLK (3.542, 3.844, 3.152, 3.389) + u_ddr_addr_ctr/u_wr0_addr_ctr/image_fram_cnt0[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_out1[15]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_wr0_addr_ctr/image_fram_cnt0[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_out2[0]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_wr0_addr_ctr/wr_addr_valid0/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_out2[1]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_wr0_addr_ctr/wr_ddr_addr0[19]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_out2[2]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_wr0_addr_ctr/wr_ddr_addr0[20]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_out2[3]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_wr0_addr_ctr/wr_ddr_addr0[21]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_out2[4]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_wr0_addr_ctr/wr_ddr_addr0[22]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_out2[5]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_wr0_addr_ctr/wr_ddr_addr0[23]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_out2[6]/opit_0/CLK (3.542, 3.844, 3.152, 3.389) + u_ddr_addr_ctr/u_wr0_addr_ctr/wr_ddr_done0/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_out2[7]/opit_0/CLK (3.542, 3.844, 3.152, 3.389) + u_ddr_addr_ctr/u_wr0_addr_ctr/wr_ddr_done1/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_out2[8]/opit_0/CLK (3.542, 3.844, 3.152, 3.389) + u_ddr_addr_ctr/u_wr0_addr_ctr/wr_ddr_done2/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_out2[9]/opit_0/CLK (3.542, 3.844, 3.152, 3.389) + u_ddr_addr_ctr/u_wr0_addr_ctr/wr_sta_reg[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_out2[10]/opit_0/CLK (3.542, 3.844, 3.152, 3.389) + u_ddr_addr_ctr/u_wr0_addr_ctr/wr_sta_reg[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_out2[11]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_wr0_addr_ctr/wr_sta_reg[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_out2[12]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_wr0_addr_ctr/wr_vs0/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_out2[13]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_wr0_addr_ctr/wr_vs1/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_out2[14]/opit_0/CLK (3.542, 3.844, 3.152, 3.389) + u_ddr_addr_ctr/u_wr0_addr_ctr/wr_vs2/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_out2[15]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_wr0_addr_ctr/wr_vs_flag/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_out_valid1/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_wr3_addr_ctr/delay_cnt[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/data_out_valid2/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_wr3_addr_ctr/delay_cnt[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/delay_cnt[0]/opit_0_inv_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_wr3_addr_ctr/delay_cnt[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/delay_cnt[1]/opit_0_inv_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_wr3_addr_ctr/delay_cnt[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/delay_cnt[2]/opit_0_inv_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_wr3_addr_ctr/image_fram_cnt0[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/fifo_full0/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_wr3_addr_ctr/image_fram_cnt0[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/imag_addr0[0]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_wr3_addr_ctr/image_fram_cnt0[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/imag_addr0[1]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_wr3_addr_ctr/wr_addr_valid0/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/imag_addr0[2]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_wr3_addr_ctr/wr_ddr_addr0[19]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/imag_addr0[3]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_wr3_addr_ctr/wr_ddr_addr0[20]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/imag_addr0[4]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_wr3_addr_ctr/wr_ddr_addr0[21]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/imag_addr0[5]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_wr3_addr_ctr/wr_ddr_done0/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/imag_addr0[6]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_wr3_addr_ctr/wr_ddr_done1/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/imag_addr0[7]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_wr3_addr_ctr/wr_ddr_done2/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/imag_addr0[8]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_wr3_addr_ctr/wr_sta_reg[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/imag_addr0[9]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_wr3_addr_ctr/wr_sta_reg[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/imag_addr1[0]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_wr3_addr_ctr/wr_sta_reg[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/imag_addr1[1]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_wr3_addr_ctr/wr_vs0/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/imag_addr1[2]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_wr3_addr_ctr/wr_vs1/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/imag_addr1[3]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_wr3_addr_ctr/wr_vs2/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/imag_addr1[5]/opit_0_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/u_wr3_addr_ctr/wr_vs_out/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/imag_addr1[7]/opit_0_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/vs_15hz/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/imag_addr1[9]/opit_0_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_addr_ctr/vs_30hz/opit_0_L5Q_perm/CLK (3.546, 3.848, 3.156, 3.393) - u_zoom_image/imag_addr_valid0/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/power_on_delay_inst/camera_pwnd_reg/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/imag_addr_valid1/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/power_on_delay_inst/camera_rstn_reg/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h0[0]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/power_on_delay_inst/cnt1[0]/opit_0_inv_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h0[1]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/power_on_delay_inst/cnt1[2]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h0[2]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/power_on_delay_inst/cnt1[4]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h0[3]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/power_on_delay_inst/cnt1[6]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h0[4]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/power_on_delay_inst/cnt1[8]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h0[5]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/power_on_delay_inst/cnt1[10]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h0[6]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/power_on_delay_inst/cnt1[12]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h0[8]/opit_0_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/power_on_delay_inst/cnt1[14]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h0[10]/opit_0_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/power_on_delay_inst/cnt1[16]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h0[12]/opit_0_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/power_on_delay_inst/cnt1[18]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h0[14]/opit_0_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/power_on_delay_inst/cnt2[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h0[16]/opit_0_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/power_on_delay_inst/cnt2[2]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h0[18]/opit_0_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/power_on_delay_inst/cnt2[4]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h0[20]/opit_0_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/power_on_delay_inst/cnt2[6]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h1[1]/opit_0_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/power_on_delay_inst/cnt2[8]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h1[3]/opit_0_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/power_on_delay_inst/cnt2[10]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h1[5]/opit_0_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/power_on_delay_inst/cnt2[12]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h1[7]/opit_0_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/power_on_delay_inst/cnt2[14]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h1[9]/opit_0_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/power_on_delay_inst/cnt2[15]/opit_0_AQ/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h1[11]/opit_0_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/data_out1[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h1[13]/opit_0_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/data_out1[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h1[15]/opit_0_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/data_out1[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h1[17]/opit_0_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/data_out1[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h1[19]/opit_0_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/data_out1[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h1[20]/opit_0_AQ/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/data_out1[5]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h2[0]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/data_out1[6]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h2[1]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/data_out1[7]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h2[2]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/data_out1[8]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h2[3]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/data_out1[9]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h2[4]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/data_out1[10]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h2[5]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/data_out1[11]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h2[6]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/data_out1[12]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h2[7]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/data_out1[13]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h2[8]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/data_out1[14]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h2[9]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/data_out1[15]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h2[10]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/data_out_valid0/opit_0_inv_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h2[11]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/data_out_valid1/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h2[12]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/data_vs/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h2[13]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/rd_h[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h2[14]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/rd_h[2]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h2[15]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/rd_h[4]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h2[16]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/rd_h[6]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h2[17]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/rd_h[8]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h2[18]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/rd_h[10]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h2[19]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/rd_sta0[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h2[20]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/rd_sta0[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h2_coe0[0]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/rd_sta0[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h2_coe0[1]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/rd_sta0[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h2_coe0[2]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/rd_sta0[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h2_coe0[3]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/rd_sta_reg[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h2_coe0[4]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/rd_sta_reg[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h2_coe0[5]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/rd_sta_reg[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h2_coe0[6]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/rd_sta_reg[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h2_coe1[0]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/rd_sta_reg[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h2_coe1[1]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/rd_vs0/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h2_coe1[2]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/rd_vs1/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h2_coe1[3]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/rd_vs2/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h2_coe1[4]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/rd_vs_rise/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h2_coe1[5]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/rd_w[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h2_coe1[6]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/rd_w[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h2_coe[0]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/rd_w[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h2_coe[1]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/rd_w[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h2_coe[2]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/rd_w[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h2_coe[3]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/rd_w[5]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h2_coe[4]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/rd_w[6]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h2_coe[5]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/rd_w[7]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h2_coe[6]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/rd_w[8]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h_valid[0]/opit_0_inv_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/rd_w[9]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_h_valid[1]/opit_0_inv_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/rd_w[10]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_valid[0][0]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0_A2Q1/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_valid[0][1]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_valid[1][0]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_valid[1][1]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_valid[2][0]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_valid[2][1]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_valid[3][0]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[10]/opit_0_inv_AQ/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_valid[3][1]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_valid[4][0]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_valid[4][1]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_valid[5][0]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_valid[5][1]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_valid[6][0]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_valid[6][1]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w1[1]/opit_0_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w1[3]/opit_0_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w1[5]/opit_0_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w1[7]/opit_0_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w1[9]/opit_0_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w1[11]/opit_0_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w1[13]/opit_0_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w1[15]/opit_0_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w1[17]/opit_0_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w1[19]/opit_0_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w1[20]/opit_0_AQ/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w2[0]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w2[1]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w2[2]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w2[3]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w2[4]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w2[5]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w2[6]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w2[15]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w2[16]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w2[17]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w2[18]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w2[19]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w2[20]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w2_coe0[0]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w2_coe0[1]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w2_coe0[2]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w2_coe0[3]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0_A2Q1/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w2_coe0[4]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w2_coe0[5]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w2_coe0[6]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w2_coe1[0]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w2_coe1[1]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w2_coe1[2]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[10]/opit_0_inv_AQ/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w2_coe1[3]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w2_coe1[4]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w2_coe1[5]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w2_coe1[6]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w2_coe[0]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w2_coe[1]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w2_coe[2]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w2_coe[3]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w2_coe[4]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w2_coe[5]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w2_coe[6]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w_valid[0]/opit_0_inv_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/image_w_valid[1]/opit_0_inv_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/judge_cnt_h[0]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/judge_cnt_h[1]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/judge_cnt_h[2]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/judge_cnt_h[3]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/judge_cnt_h[4]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/judge_cnt_h[5]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/judge_cnt_h[6]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/judge_cnt_h[7]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/judge_cnt_h[8]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/judge_cnt_h[9]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/judge_cnt_h[10]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/judge_cnt_h[11]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/judge_cnt_h[12]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/judge_cnt_h[13]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/judge_cnt_h_valid/opit_0_MUX4TO1Q/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/mult_fra0/N2/gopapm/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/mult_fra0_0/N2/gopapm/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/mult_fra1/N2/gopapm/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/mult_fra1_0/N2/gopapm/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/mult_h0[0]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/mult_h0[1]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (3.436, 3.736, 3.055, 3.290) - u_zoom_image/mult_h0[2]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/addr_fifo_valid/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/mult_h0[3]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/centerX[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/mult_h0[4]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/centerX[2]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/mult_h0[5]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/centerX[4]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/mult_h0[6]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/centerX[6]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/mult_h0[7]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/centerX[8]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/mult_h0[8]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/centerX[10]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/mult_h0[9]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/centerX[11]/opit_0_AQ/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/mult_h0[10]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/centerY[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/mult_h0[11]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/centerY[2]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/mult_h0[12]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/centerY[4]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/mult_h0[13]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/centerY[6]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/mult_image2[0][7]/opit_0_A2Q1/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/centerY[8]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/mult_image2[0][9]/opit_0_A2Q21/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/centerY[10]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/mult_image2[0][11]/opit_0_A2Q21/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/centerY[11]/opit_0_AQ/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/mult_image2[1][7]/opit_0_A2Q1/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/cnt_h[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/mult_image2[1][9]/opit_0_A2Q21/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/cnt_h[2]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/mult_image2[1][11]/opit_0_A2Q21/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/cnt_h[4]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/mult_image2[1][12]/opit_0_AQ_perm/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/cnt_h[6]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/mult_image2[2][7]/opit_0_A2Q1/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/cnt_h[8]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/mult_image2[2][9]/opit_0_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/cnt_h[10]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/mult_image2[2][11]/opit_0_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/cnt_w[0]/opit_0_inv_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/mult_image_b0/N2/gopapm/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/cnt_w[2]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/mult_image_b0_0/N2/gopapm/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/cnt_w[4]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/mult_image_b1/N2/gopapm/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/cnt_w[6]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/mult_image_b1_0/N2/gopapm/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/cnt_w[8]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/mult_image_g0/N2/gopapm/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/cnt_w[10]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/mult_image_g0_0/N2/gopapm/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/data_out2[0]/opit_0_inv/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/mult_image_g1/N2/gopapm/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/data_out2[1]/opit_0_inv/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/mult_image_g1_0/N2/gopapm/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/data_out2[2]/opit_0_inv/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/mult_image_r0/N2/gopapm/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/data_out2[3]/opit_0_inv/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/mult_image_r0_0/N2/gopapm/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/data_out2[4]/opit_0_inv/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/mult_image_r1/N2/gopapm/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/data_out2[5]/opit_0_inv/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/mult_image_r1_0/N2/gopapm/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/data_out2[6]/opit_0_inv/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/no_need_rd_ddr/opit_0_inv_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/data_out2[7]/opit_0_inv/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/no_one_need_rd_ddr/opit_0_inv_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/data_out2[8]/opit_0_inv/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/ram_ch0[0]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/data_out2[9]/opit_0_inv/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/ram_ch0[1]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/data_out2[10]/opit_0_inv/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/ram_ch1[0]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/data_out2[11]/opit_0_inv/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/ram_ch1[1]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/data_out2[12]/opit_0_inv/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/ram_ch2[0]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/data_out2[13]/opit_0_inv/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/ram_ch2[1]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/data_out2[14]/opit_0_inv/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/ram_ch[0]/opit_0_inv_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/data_out2[15]/opit_0_inv/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/ram_ch[1]/opit_0_inv_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/data_out_valid1/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/ram_idle/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/data_out_valid2/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/ram_idle0/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/ddr_data_in0[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/ram_idle1/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/ddr_data_in0[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/ram_sta_reg[0]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/ddr_data_in0[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/ram_sta_reg[1]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/ddr_data_in0[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/ram_sta_reg[2]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/ddr_data_in0[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/ram_sta_reg[3]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/ddr_data_in0[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_addr0[0]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/ddr_data_in0[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_addr0[1]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/ddr_data_in0[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_addr0[2]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/ddr_data_in0[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_addr0[3]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/ddr_data_in0[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_addr0[4]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/ddr_data_in0[10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_addr0[5]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/ddr_data_in0[11]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_addr0[6]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/ddr_data_in0[12]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_addr0[7]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/ddr_data_in0[13]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_addr0[8]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/ddr_data_in0[14]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_addr0[9]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/ddr_data_in0[15]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_addr0[10]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/ddr_data_in_valid0/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_addr[0]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/fifo_data_valid/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_addr[1]/opit_0_A2Q1/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_blank_valid/opit_0_L5Q_perm/CLK (3.456, 3.757, 3.075, 3.311) - u_zoom_image/rd_addr[3]/opit_0_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_h_add0[7]/opit_0_A2Q1/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_addr[5]/opit_0_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_h_add0[9]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_addr[7]/opit_0_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_h_add0[11]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_addr[9]/opit_0_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_h_add0[13]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_addr[10]/opit_0_AQ_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_h_add0[15]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data_0[0]/opit_0_MUX4TO1Q/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_h_add0[17]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data_0[1]/opit_0_MUX4TO1Q/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_h_add0[19]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data_0[2]/opit_0_MUX4TO1Q/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_h_add0[21]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data_0[3]/opit_0_MUX4TO1Q/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_h_add0[23]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data_0[4]/opit_0_MUX4TO1Q/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_h_add0[25]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data_0[5]/opit_0_MUX4TO1Q/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_h_add1[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data_0[6]/opit_0_MUX4TO1Q/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_h_add1[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data_0[7]/opit_0_MUX4TO1Q/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_h_add1[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data_0[8]/opit_0_MUX4TO1Q/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/image_h_add1[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data_0[9]/opit_0_MUX4TO1Q/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/image_h_add1[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data_0[10]/opit_0_MUX4TO1Q/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/image_h_add1[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data_0[11]/opit_0_MUX4TO1Q/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/image_h_add1[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data_0[12]/opit_0_MUX4TO1Q/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/image_h_add1[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data_0[13]/opit_0_MUX4TO1Q/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/image_h_add1[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data_0[14]/opit_0_MUX4TO1Q/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/image_h_add1[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data_0[15]/opit_0_MUX4TO1Q/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/image_h_add1[10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data_0[16]/opit_0_MUX4TO1Q/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_h_add2[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data_0[17]/opit_0_MUX4TO1Q/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_h_add2[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data_0[18]/opit_0_MUX4TO1Q/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_h_add2[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data_0[19]/opit_0_MUX4TO1Q/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_h_add2[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data_0[20]/opit_0_MUX4TO1Q/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_h_add2[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data_0[21]/opit_0_MUX4TO1Q/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_h_add2[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data_0[22]/opit_0_MUX4TO1Q/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_h_add2[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data_0[23]/opit_0_MUX4TO1Q/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_h_add2[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data_0[24]/opit_0_MUX4TO1Q/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/image_h_add2[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data_0[25]/opit_0_MUX4TO1Q/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/image_h_add2[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data_0[26]/opit_0_MUX4TO1Q/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/image_h_add2[10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data_0[27]/opit_0_MUX4TO1Q/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/image_h_add_addr[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data_0[28]/opit_0_MUX4TO1Q/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/image_h_add_addr[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data_0[29]/opit_0_MUX4TO1Q/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/image_h_add_addr[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data_0[30]/opit_0_MUX4TO1Q/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/image_h_add_addr[10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data_0[31]/opit_0_MUX4TO1Q/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/image_h_add_addr[11]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data[0]/opit_0_MUX4TO1Q/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_h_add_addr[12]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data[1]/opit_0_MUX4TO1Q/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_h_add_addr[13]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data[2]/opit_0_MUX4TO1Q/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_h_add_addr[14]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data[3]/opit_0_MUX4TO1Q/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_h_add_addr[15]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data[4]/opit_0_MUX4TO1Q/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_h_add_addr[16]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data[5]/opit_0_MUX4TO1Q/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/image_h_add_addr[17]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data[6]/opit_0_MUX4TO1Q/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/image_h_add_addr[18]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data[7]/opit_0_MUX4TO1Q/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/image_h_blank_valid/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data[8]/opit_0_MUX4TO1Q/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/image_w_add0[7]/opit_0_A2Q1/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data[9]/opit_0_MUX4TO1Q/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/image_w_add0[9]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data[10]/opit_0_MUX4TO1Q/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/image_w_add0[11]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data[11]/opit_0_MUX4TO1Q/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/image_w_add0[13]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data[12]/opit_0_MUX4TO1Q/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/image_w_add0[15]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data[13]/opit_0_MUX4TO1Q/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/image_w_add0[17]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data[14]/opit_0_MUX4TO1Q/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/image_w_add0[19]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data[15]/opit_0_MUX4TO1Q/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/image_w_add0[21]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data[16]/opit_0_MUX4TO1Q/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_w_add0[23]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data[17]/opit_0_MUX4TO1Q/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_w_add0[25]/opit_0_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data[18]/opit_0_MUX4TO1Q/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_w_add1[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data[19]/opit_0_MUX4TO1Q/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_w_add1[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data[20]/opit_0_MUX4TO1Q/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_w_add1[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data[21]/opit_0_MUX4TO1Q/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/image_w_add1[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data[22]/opit_0_MUX4TO1Q/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/image_w_add1[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data[23]/opit_0_MUX4TO1Q/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/image_w_add1[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data[24]/opit_0_MUX4TO1Q/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/image_w_add1[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data[25]/opit_0_MUX4TO1Q/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/image_w_add1[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data[26]/opit_0_MUX4TO1Q/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/image_w_add1[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data[27]/opit_0_MUX4TO1Q/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/image_w_add1[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data[28]/opit_0_MUX4TO1Q/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/image_w_add1[10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data[29]/opit_0_MUX4TO1Q/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/image_w_add2[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data[30]/opit_0_MUX4TO1Q/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/image_w_add2[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_data[31]/opit_0_MUX4TO1Q/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/image_w_add2[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/rd_one_ram/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_w_add2[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/record_ram_valid/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_w_add2[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/store_addr[0]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_w_add2[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/store_addr[1]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_w_add2[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/store_addr[2]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_w_add2[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/store_addr[3]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_w_add2[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/store_addr[4]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_w_add2[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/store_addr[5]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_w_add2[10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/store_addr[6]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_w_add_addr[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/store_addr[7]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_w_add_addr[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/store_addr[8]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_w_add_addr[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/store_addr[9]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_w_add_addr[10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/store_addr[10]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_w_add_addr[11]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/store_addr[11]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_w_add_addr[12]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/store_addr[12]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_w_add_addr[13]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/store_addr[13]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_w_add_addr[14]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/store_mult_h0[0]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_w_add_addr[15]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/store_mult_h0[1]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_w_add_addr[16]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/store_mult_h[0]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_w_add_addr[17]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/store_mult_h[1]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_w_add_addr[18]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/u_image_h_mult/N3/gopapm/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_w_blank_valid/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/u_image_w_mult/N3/gopapm/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/image_w_valid0[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/wr_addr0[0]/opit_0_L5Q_perm/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/image_w_valid0[1]/opit_0/CLK (3.467, 3.768, 3.086, 3.322) - u_zoom_image/wr_addr0[2]/opit_0_A2Q21/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/image_w_valid0[2]/opit_0/CLK (3.467, 3.768, 3.086, 3.322) - u_zoom_image/wr_addr0[4]/opit_0_A2Q21/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/image_w_valid0[3]/opit_0/CLK (3.467, 3.768, 3.086, 3.322) - u_zoom_image/wr_addr0[6]/opit_0_A2Q21/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/image_w_valid0[4]/opit_0/CLK (3.456, 3.757, 3.075, 3.311) - u_zoom_image/wr_addr0[8]/opit_0_A2Q21/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/offsetX_ff[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/wr_addr0[10]/opit_0_A2Q21/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/offsetX_ff[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/wr_addr1[0]/opit_0_inv_L5Q_perm/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/offsetX_ff[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/wr_addr1[2]/opit_0_inv_A2Q21/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/offsetX_ff[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/wr_addr1[4]/opit_0_inv_A2Q21/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/offsetX_ff[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/wr_addr1[6]/opit_0_inv_A2Q21/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/offsetX_ff[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/wr_addr1[8]/opit_0_inv_A2Q21/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/offsetX_ff[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/wr_addr1[10]/opit_0_inv_A2Q21/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/offsetX_ff[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/wr_addr2[0]/opit_0_inv_L5Q_perm/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/offsetX_ff[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/wr_addr2[2]/opit_0_inv_A2Q21/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/offsetX_ff[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/wr_addr2[4]/opit_0_inv_A2Q21/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/offsetX_ff[10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/wr_addr2[6]/opit_0_inv_A2Q21/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/offsetX_ff[11]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/wr_addr2[8]/opit_0_inv_A2Q21/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/offsetY_ff[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/wr_addr2[10]/opit_0_inv_A2Q21/CLK (3.542, 3.844, 3.152, 3.389) + u_rotate_image/offsetY_ff[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/wr_addr3[0]/opit_0_inv_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/offsetY_ff[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/wr_addr3[2]/opit_0_inv_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/offsetY_ff[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/wr_addr3[4]/opit_0_inv_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/offsetY_ff[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/wr_addr3[6]/opit_0_inv_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/offsetY_ff[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/wr_addr3[8]/opit_0_inv_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/offsetY_ff[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/wr_addr3[10]/opit_0_inv_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/offsetY_ff[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/wr_ram_done/opit_0_L6Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/offsetY_ff[8]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/zoom_num0[1]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/offsetY_ff[9]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/zoom_num0[2]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/offsetY_ff[10]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/zoom_num0[3]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/offsetY_ff[11]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/zoom_num0[4]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/rd_addr[0]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/zoom_num0[5]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/rd_addr[1]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/zoom_num0[6]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/rd_addr[2]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/zoom_num0[7]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/rd_addr[3]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/zoom_num0[8]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/rd_addr[4]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/zoom_num0[9]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/rd_addr[5]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/zoom_num1[0]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/rd_addr[6]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/zoom_num1[1]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/rd_addr[7]/opit_0/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/zoom_num1[2]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/rd_ddr_addr_valid1/opit_0_L5Q_perm/CLK (3.467, 3.768, 3.086, 3.322) - u_zoom_image/zoom_num1[3]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/rd_sta_reg[0]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/zoom_num1[4]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/rd_sta_reg[1]/opit_0_MUX4TO1Q/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/zoom_num1[5]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/rd_sta_reg[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/zoom_num1[6]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/rd_sta_s2/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/zoom_num1[7]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/rotate_sta_reg[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/zoom_num1[8]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/rotate_sta_reg[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/zoom_ram0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.432, 3.732, 3.051, 3.286) + u_rotate_image/rotate_sta_reg[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/zoom_ram0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (3.432, 3.732, 3.051, 3.286) + u_rotate_image/u_rotate_mult0/N2/gopapm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/zoom_ram0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.542, 3.844, 3.152, 3.389) + u_rotate_image/u_rotate_mult1/N2/gopapm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/zoom_ram0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (3.542, 3.844, 3.152, 3.389) + u_rotate_image/u_rotate_mult2/N2/gopapm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/zoom_ram0_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.432, 3.732, 3.051, 3.286) + u_rotate_image/u_rotate_mult3/N2/gopapm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/zoom_ram0_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (3.432, 3.732, 3.051, 3.286) + u_rotate_image/u_rotate_mult_zoom0/N2/gopapm/CLK (3.546, 3.848, 3.156, 3.393) - u_zoom_image/zoom_ram0_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.542, 3.844, 3.152, 3.389) + u_rotate_image/u_rotate_mult_zoom1/N2/gopapm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/zoom_ram0_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (3.542, 3.844, 3.152, 3.389) + u_rotate_image/u_rotate_rom/U_ipml_rom_rotate_rom/U_ipml_spram_rotate_rom/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKA (3.546, 3.848, 3.156, 3.393) - u_zoom_image/zoom_ram1/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.542, 3.844, 3.152, 3.389) + u_rotate_image/u_rotate_rom/U_ipml_rom_rotate_rom/U_ipml_spram_rotate_rom/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB (3.546, 3.848, 3.156, 3.393) - u_zoom_image/zoom_ram1/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (3.542, 3.844, 3.152, 3.389) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (3.471, 3.772, 3.090, 3.326) - u_zoom_image/zoom_ram1/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.542, 3.844, 3.152, 3.389) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (3.471, 3.772, 3.090, 3.326) - u_zoom_image/zoom_ram1/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (3.542, 3.844, 3.152, 3.389) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (3.467, 3.768, 3.086, 3.322) - u_zoom_image/zoom_ram1_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.432, 3.732, 3.051, 3.286) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (3.467, 3.768, 3.086, 3.322) - u_zoom_image/zoom_ram1_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (3.432, 3.732, 3.051, 3.286) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (3.463, 3.763, 3.082, 3.317) - u_zoom_image/zoom_ram1_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.542, 3.844, 3.152, 3.389) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[11]/opit_0_inv_A2Q21/CLK (3.463, 3.763, 3.082, 3.317) - u_zoom_image/zoom_ram1_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (3.542, 3.844, 3.152, 3.389) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/CLK (3.444, 3.744, 3.063, 3.299) - u_zoom_image/zoom_ram2/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.432, 3.732, 3.051, 3.286) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK (3.448, 3.748, 3.066, 3.302) - u_zoom_image/zoom_ram2/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (3.432, 3.732, 3.051, 3.286) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (3.471, 3.772, 3.090, 3.326) - u_zoom_image/zoom_ram2/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.542, 3.844, 3.152, 3.389) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (3.471, 3.772, 3.090, 3.326) - u_zoom_image/zoom_ram2/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (3.542, 3.844, 3.152, 3.389) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (3.467, 3.768, 3.086, 3.322) - u_zoom_image/zoom_ram2_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.432, 3.732, 3.051, 3.286) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (3.467, 3.768, 3.086, 3.322) - u_zoom_image/zoom_ram2_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (3.432, 3.732, 3.051, 3.286) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (3.463, 3.763, 3.082, 3.317) - u_zoom_image/zoom_ram2_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.542, 3.844, 3.152, 3.389) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[11]/opit_0_inv_A2Q21/CLK (3.463, 3.763, 3.082, 3.317) - u_zoom_image/zoom_ram2_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (3.542, 3.844, 3.152, 3.389) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[1]/opit_0_A2Q21/CLK (3.456, 3.757, 3.075, 3.311) - u_zoom_image/zoom_ram3/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.432, 3.732, 3.051, 3.286) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[3]/opit_0_A2Q21/CLK (3.456, 3.757, 3.075, 3.311) - u_zoom_image/zoom_ram3/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (3.432, 3.732, 3.051, 3.286) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[5]/opit_0_A2Q21/CLK (3.452, 3.752, 3.071, 3.306) - u_zoom_image/zoom_ram3/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.542, 3.844, 3.152, 3.389) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[7]/opit_0_A2Q21/CLK (3.452, 3.752, 3.071, 3.306) - u_zoom_image/zoom_ram3/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (3.542, 3.844, 3.152, 3.389) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[9]/opit_0_A2Q21/CLK (3.448, 3.748, 3.066, 3.302) - u_zoom_image/zoom_ram3_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.432, 3.732, 3.051, 3.286) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[11]/opit_0_A2Q21/CLK (3.448, 3.748, 3.066, 3.302) - u_zoom_image/zoom_ram3_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (3.432, 3.732, 3.051, 3.286) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKA (3.460, 3.760, 3.078, 3.314) - u_zoom_image/zoom_ram3_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.542, 3.844, 3.152, 3.389) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB (3.464, 3.764, 3.083, 3.319) - u_zoom_image/zoom_ram3_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (3.542, 3.844, 3.152, 3.389) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/zoom_sta_param/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/zoom_sta_param0/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/zoom_sta_param1/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/zoom_sta_reg[0]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/zoom_sta_reg[1]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[10]/opit_0_inv_AQ/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/zoom_sta_reg[2]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/zoom_sta_reg[3]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/zoom_sta_reg[4]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/zoom_sta_reg[5]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_image/zoom_sta_reg[6]/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_rst/rst/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_rst/rst0/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (3.436, 3.736, 3.055, 3.290) - u_zoom_rst/rst1/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.wbin[10]/opit_0_inv_AQ/CLK (3.436, 3.736, 3.055, 3.290) - zoom_ff0[0]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.436, 3.736, 3.055, 3.290) - zoom_ff0[1]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (3.436, 3.736, 3.055, 3.290) - zoom_ff0[2]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + vs_down_delay_cnt[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - zoom_ff0[3]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + vs_down_delay_cnt[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - zoom_ff0[4]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + vs_down_delay_cnt[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - zoom_ff0[5]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + vs_down_delay_cnt[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - zoom_ff0[6]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + vs_down_delay_cnt[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - zoom_ff0[7]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + vs_down_delay_cnt[5]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - zoom_ff0[8]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + vs_down_delay_cnt[6]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - zoom_ff0[9]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + vs_down_delay_cnt[7]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - zoom_ff1[0]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + vs_down_delay_cnt[8]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - zoom_ff1[1]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + vs_down_delay_cnt[9]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - zoom_ff1[2]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + vs_down_delay_cnt[10]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - zoom_ff1[3]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + vs_down_delay_cnt[11]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - zoom_ff1[4]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + vs_pos_delay_cnt[0]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - zoom_ff1[5]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + vs_pos_delay_cnt[1]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - zoom_ff1[6]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + vs_pos_delay_cnt[2]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - zoom_ff1[7]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + vs_pos_delay_cnt[3]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - zoom_ff1[8]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + vs_pos_delay_cnt[4]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - zoom_ff1[9]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + vs_pos_delay_cnt[5]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - zoom_ff2[0]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + vs_pos_delay_cnt[6]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - zoom_ff2[1]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + vs_pos_delay_cnt[7]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - zoom_ff2[2]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + vs_pos_delay_cnt[8]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - zoom_ff2[3]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + vs_pos_delay_cnt[9]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - zoom_ff2[4]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + vs_pos_delay_cnt[10]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - zoom_ff2[5]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + vs_pos_delay_cnt[11]/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) - zoom_ff2[6]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + wr0_vs/opit_0_L5Q_perm/CLK (3.436, 3.736, 3.055, 3.290) + + + + + + + + clk_200m (200.00MHZ) (drive 75 loads) + + u_sys_pll/u_pll_e3/goppll/CLKOUT1 (1.934, 2.193, 1.536, 1.728) + + ddr_clk (net) + + USCMROUTE_2/CLK (2.537, 2.807, 2.133, 2.336) + + USCMROUTE_2/CLKOUT (2.537, 2.807, 2.133, 2.336) + + ntR3952 (net) - zoom_ff2[7]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_rst/rst/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) - zoom_ff2[8]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_rst/rst0/opit_0/CLK (3.432, 3.732, 3.051, 3.286) - zoom_ff2[9]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_rst/rst1/opit_0/CLK (3.432, 3.732, 3.051, 3.286) - zoom_fifo_full/opit_0_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK (3.542, 3.844, 3.152, 3.389) - zoom_vs_out0/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_rst/rst0/opit_0_inv/CLK (3.542, 3.844, 3.152, 3.389) - zoom_vs_out1/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_ddr_rst/rst1/opit_0_inv/CLK (3.542, 3.844, 3.152, 3.389) @@ -84522,10 +84265,10 @@ u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin (net) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/opit_0/CLK (3.542, 3.844, 3.152, 3.389) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK (3.542, 3.844, 3.152, 3.389) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[0]/opit_0_inv_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) @@ -84567,19 +84310,28 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[0]/opit_0_inv_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[2]/opit_0_inv_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[1]/opit_0_inv_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[2]/opit_0_inv_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[3]/opit_0_inv_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[4]/opit_0_inv_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[4]/opit_0_inv_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[6]/opit_0_inv_A2Q21/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[5]/opit_0_inv_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[7]/opit_0_inv_AQ_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[6]/opit_0_inv_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_dll_rst_rg/opit_0_inv_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[7]/opit_0_inv_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_dll_rst_rg/opit_0_inv_L5Q/CLK (3.432, 3.732, 3.051, 3.286) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_dqs_rst/opit_0_inv/CLK (3.432, 3.732, 3.051, 3.286) @@ -84618,7 +84370,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[10]/opit_0_inv_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[11]/opit_0_inv_L5Q/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[11]/opit_0_inv_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[12]/opit_0_inv_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) @@ -84672,7 +84424,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/dll_update_req_rst_ctrl/opit_0_inv/CLK (3.432, 3.732, 3.051, 3.286) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q/CLK (3.432, 3.732, 3.051, 3.286) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/pll_lock_d[0]/opit_0_inv_L5Q_perm/CLK (3.432, 3.732, 3.051, 3.286) @@ -84726,9 +84478,9 @@ clkout0_wl_0 (net) - clkgate_8/gopclkgate/CLK (4.276, 4.602, 3.895, 4.157) + clkgate_9/gopclkgate/CLK (4.276, 4.602, 3.895, 4.157) - clkgate_8/gopclkgate/OUT (4.476, 4.870, 4.095, 4.425) + clkgate_9/gopclkgate/OUT (4.476, 4.870, 4.095, 4.425) ntclkgate_0 (net) @@ -84833,37 +84585,37 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[7]/opit_0_inv_AQ_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_pwron_pass/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_pwron_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[2]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[2]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[4]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[4]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[6]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[6]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[8]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[8]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[10]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[10]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[12]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[12]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[14]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[14]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[15]/opit_0_inv_AQ_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[15]/opit_0_inv_AQ_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[0]/opit_0_inv_L5Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[2]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) @@ -84983,7 +84735,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_done/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_rst/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_rst/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -85091,16 +84843,16 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[5]/opit_0_inv_L5Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[5]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[6]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[7]/opit_0_inv_L5Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[7]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[8]/opit_0_inv_L5Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[8]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[9]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -85118,7 +84870,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_ba[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_cas_n/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_cas_n/opit_0_inv_L5Q/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_cke/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) @@ -85415,7 +85167,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[15]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[30]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[30]/opit_0_inv/CLK (6.679, 7.126, 6.306, 6.692) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[31]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) @@ -85427,13 +85179,13 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[33]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[34]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[34]/opit_0_inv/CLK (6.666, 7.113, 6.293, 6.679) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[35]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[36]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[36]/opit_0_inv/CLK (6.682, 7.129, 6.310, 6.696) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[37]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) @@ -85442,7 +85194,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[38]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[39]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[39]/opit_0_inv/CLK (6.682, 7.129, 6.310, 6.696) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[40]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) @@ -85496,7 +85248,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[14]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[30]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[30]/opit_0_inv_L5Q_perm/CLK (6.679, 7.126, 6.306, 6.692) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[31]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -85508,22 +85260,22 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[33]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[34]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[34]/opit_0_inv_L5Q_perm/CLK (6.666, 7.113, 6.293, 6.679) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[35]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[35]/opit_0_inv_L5Q_perm/CLK (6.679, 7.126, 6.306, 6.692) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[36]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[36]/opit_0_inv_L5Q_perm/CLK (6.682, 7.129, 6.310, 6.696) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[37]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[37]/opit_0_inv_L5Q_perm/CLK (6.679, 7.126, 6.306, 6.692) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[38]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[39]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[39]/opit_0_inv_L5Q_perm/CLK (6.682, 7.129, 6.310, 6.696) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[40]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -85778,28 +85530,28 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[47]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[48]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[48]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[49]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[50]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[50]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[51]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[51]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[52]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[52]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[53]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[53]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[54]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[54]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[55]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[55]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[56]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) @@ -85889,7 +85641,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[84]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[85]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[85]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[86]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) @@ -85970,25 +85722,25 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[111]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[112]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[112]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[113]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[114]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[114]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[115]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[115]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[116]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[117]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[117]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[118]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[118]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[119]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) @@ -86174,13 +85926,13 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[179]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[180]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[180]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[181]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[182]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[182]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[183]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) @@ -86261,7 +86013,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[208]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[209]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[209]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[210]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) @@ -86270,7 +86022,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[211]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[212]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[212]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[213]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) @@ -86354,25 +86106,25 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[239]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[240]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[240]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[241]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[241]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[242]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[243]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[243]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[244]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[245]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[245]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[246]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[246]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[247]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) @@ -86552,19 +86304,19 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[49]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[50]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[50]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[51]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[52]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[52]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[53]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[53]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[54]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[54]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[55]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) @@ -86936,19 +86688,19 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[177]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[178]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[178]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[179]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[180]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[180]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[181]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[182]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[182]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[183]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) @@ -87344,7 +87096,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[3]/opit_0_inv_L5Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -87536,7 +87288,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r3[0]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r3[2]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r3[2]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -87629,13 +87381,13 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[2]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[1]/opit_0_inv_A2Q1/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[4]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[3]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[5]/opit_0_inv_AQ/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[5]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_check_done/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -87680,7 +87432,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/opit_0_inv_AQ_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt[0]/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -87689,7 +87441,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt[3]/opit_0_inv_L5Q/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -88085,28 +87837,28 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rdvalid_r1/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_cnt[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_cnt[1]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_cnt[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_cnt[4]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_inc_dec_n/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_inc_dec_n/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_rdel_done/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[2]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) @@ -88121,31 +87873,31 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[8]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[9]/opit_0_inv_AQ_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[9]/opit_0_inv_AQ_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[1]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[2]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[3]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[4]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[5]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[5]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[6]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[6]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[7]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[7]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -88163,28 +87915,28 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[7]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[1]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[2]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[3]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[4]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[5]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[5]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[6]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[6]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[7]/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[7]/opit_0_inv_MUX4TO1Q/CLK (6.764, 7.213, 6.383, 6.770) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_cal_vld/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -88196,7 +87948,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_error/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calibration_d/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calibration_d/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -88226,7 +87978,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_sync/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/reinit_adj_rdel_d/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/reinit_adj_rdel_d/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -88286,13 +88038,13 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[3]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[5]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[5]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[7]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[7]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[8]/opit_0_inv_AQ/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[8]/opit_0_inv_AQ/CLK (6.764, 7.213, 6.383, 6.770) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/CLK_REGIONAL (6.654, 7.101, 6.282, 6.667) @@ -88334,64 +88086,64 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[1]/opit_0_inv_MUX4TO1Q/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[1]/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[3]/opit_0_inv_MUX4TO1Q/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[3]/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[1]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[2]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[3]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[0]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[0]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[1]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[1]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[2]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[2]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[3]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[3]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[0]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[0]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[1]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[1]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[2]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[2]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[3]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[3]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4[3]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4[3]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[1]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[2]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_vld/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -88418,73 +88170,73 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_error/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass_d/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass_d/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[1]/opit_0_inv_L5Q/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[3]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[4]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[1]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[3]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[5]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[5]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[0]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[0]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[1]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[1]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[2]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[2]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[3]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[3]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[4]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[4]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[5]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[5]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[1]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[2]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[2]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) @@ -88493,7 +88245,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[4]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[5]/opit_0_inv_AQ/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[5]/opit_0_inv_AQ/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ck_check_done/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -88514,7 +88266,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/opit_0_inv_AQ_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt[0]/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -88640,7 +88392,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_resp/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -88739,7 +88491,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[5]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[6]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[6]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[7]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) @@ -88763,7 +88515,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[13]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[14]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[14]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[15]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) @@ -88781,19 +88533,19 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[19]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[20]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[20]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[21]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[22]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[22]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[23]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[24]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[24]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[25]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) @@ -88805,7 +88557,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[27]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[28]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[28]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[29]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) @@ -88823,7 +88575,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[33]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[34]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[34]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[35]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) @@ -88841,7 +88593,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[39]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[40]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[40]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[41]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) @@ -88922,7 +88674,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/adj_rdel_done/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[2]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) @@ -88937,7 +88689,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[8]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[9]/opit_0_inv_AQ/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[9]/opit_0_inv_AQ/CLK (6.764, 7.213, 6.383, 6.770) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -88958,7 +88710,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_done/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_error/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_error/opit_0_inv_MUX4TO1Q/CLK (6.764, 7.213, 6.383, 6.770) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -89051,7 +88803,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[7]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[8]/opit_0_inv_AQ/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[8]/opit_0_inv_AQ/CLK (6.764, 7.213, 6.383, 6.770) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/u_ddc_dqs/opit_0/CLK_REGIONAL (6.654, 7.101, 6.282, 6.667) @@ -89063,91 +88815,91 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/u_outbuft_dm/opit_1_IOL/SYSCLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[1]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[2]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[4]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[1]/opit_0_inv_MUX4TO1Q/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[1]/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[3]/opit_0_inv_MUX4TO1Q/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[3]/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[1]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[2]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[3]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[0]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[0]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[1]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[1]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[2]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[2]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[3]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[3]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[0]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[0]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[1]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[1]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[2]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[2]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[3]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[3]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4[3]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4[3]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[1]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[2]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_vld/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_vld/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[1]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) @@ -89156,94 +88908,94 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_adj_done/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_cal_error/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_cal_error/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_error/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_error/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass_d/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass_d/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[1]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[2]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[3]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[4]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[0]/opit_0_inv_MUX4TO1Q/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[1]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[2]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[3]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[4]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[5]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[5]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[0]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[0]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[1]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[1]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[2]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[2]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[3]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[3]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[4]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[4]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[5]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[5]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[1]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[2]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[2]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[2]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[4]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[4]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[5]/opit_0_inv_AQ_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[5]/opit_0_inv_AQ/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_check_done/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[2]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) @@ -89252,10 +89004,10 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[4]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[6]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[6]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/opit_0_inv_AQ_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/opit_0_inv_AQ_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt[0]/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) @@ -89309,7 +89061,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[6]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/opit_0_inv_AQ_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/opit_0_inv_AQ/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_done_flag/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -89396,10 +89148,10 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[1]/opit_0_inv_L5Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[2]/opit_0_inv_L5Q/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -89663,58 +89415,58 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rdvalid_r1/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/adj_rdel_done/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/adj_rdel_done/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[2]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[2]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[4]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[4]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[5]/opit_0_inv_A2Q20/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[6]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[8]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[8]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[9]/opit_0_inv_AQ_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[9]/opit_0_inv_AQ_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[1]/opit_0_inv_A2Q1/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[1]/opit_0_inv_A2Q1/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[3]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[3]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[5]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[4]/opit_0_inv_A2Q20/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[7]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[7]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_done/opit_0_inv_L5Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_done/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_error/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_error/opit_0_inv_MUX4TO1Q/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[1]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[2]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_move_done/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_move_done/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[0]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) @@ -89723,79 +89475,79 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[1]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[2]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[2]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[3]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[3]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_sync/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_sync/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[1]/opit_0_inv_A2Q1/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[1]/opit_0_inv_A2Q1/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[3]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[3]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[5]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[5]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[7]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[7]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[1]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[2]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[2]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[3]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[4]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[5]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[5]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[6]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[6]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[7]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[7]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[8]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[8]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[9]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[9]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[10]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[10]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[11]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[11]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[1]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[1]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[3]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[3]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[5]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[5]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[7]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[7]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[8]/opit_0_inv_AQ/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[8]/opit_0_inv_AQ/CLK (6.764, 7.213, 6.383, 6.770) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/u_ddc_dqs/opit_0/CLK_REGIONAL (6.654, 7.101, 6.282, 6.667) @@ -89807,223 +89559,223 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/u_outbuft_dm/opit_1_IOL/SYSCLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[1]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[2]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[4]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[1]/opit_0_inv_MUX4TO1Q/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[1]/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[3]/opit_0_inv_MUX4TO1Q/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[3]/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[1]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[2]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[3]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[0]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[0]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[1]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[1]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[2]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[2]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[3]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[3]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[0]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[0]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[1]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[1]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[2]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[2]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[3]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[3]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4[3]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4[3]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[1]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[2]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_vld/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_vld/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[1]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_adj_done/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_adj_done/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_cal_error/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_cal_error/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_error/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_error/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass_d/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass_d/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[1]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[2]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[3]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[4]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[1]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[2]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[3]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[4]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[5]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[5]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[0]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[0]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[1]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[1]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[2]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[2]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[3]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[3]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[4]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[4]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[5]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[5]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[1]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[2]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[2]/opit_0_inv_L5Q/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[2]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[2]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[4]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[4]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[5]/opit_0_inv_AQ/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[5]/opit_0_inv_AQ/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_check_done/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_check_done/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[2]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[2]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[4]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[4]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[6]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[6]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/opit_0_inv_AQ_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/opit_0_inv_AQ_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt[0]/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt[1]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt[2]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt[3]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt[4]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ddrphy_gatei/opit_0_inv_MUX4TO1Q/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ddrphy_gatei/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/dq_rising/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/dq_rising/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) @@ -90041,100 +89793,100 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[7]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[2]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[2]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[4]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[4]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[6]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[6]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/opit_0_inv_AQ/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/opit_0_inv_AQ_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_done_flag/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_done_flag/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[1]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[2]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[3]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[4]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[5]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[5]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[6]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[6]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[1]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[2]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[3]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_flag/opit_0_inv_MUX4TO1Q/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_flag/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_pass/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[1]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[2]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[1]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[2]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_resp/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_resp/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_error/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_error/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) @@ -90185,28 +89937,28 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[7].DQ0_GTP_ISERDES/gateop_a_IO/SYSCLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/dqs_gate_check_pass/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/dqs_gate_check_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gate_check/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gate_check/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[1]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[2]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[3]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[4]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_check_pass/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_check_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[0]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) @@ -90401,64 +90153,64 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[63]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rdvalid_r1/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/adj_rdel_done/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/adj_rdel_done/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[2]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[2]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[4]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[4]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[6]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[6]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[8]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[8]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[9]/opit_0_inv_AQ_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[9]/opit_0_inv_AQ_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[1]/opit_0_inv_A2Q1/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[1]/opit_0_inv_A2Q1/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[3]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[3]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[5]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[5]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[7]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[7]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_done/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_done/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_error/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_error/opit_0_inv_MUX4TO1Q/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[1]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[2]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_move_done/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_move_done/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[0]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) @@ -90467,79 +90219,79 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[1]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[2]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[2]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[3]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[3]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_sync/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_sync/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[1]/opit_0_inv_A2Q1/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[1]/opit_0_inv_A2Q1/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[3]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[3]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[5]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[5]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[7]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[7]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[1]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[2]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[2]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[3]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[4]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[5]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[5]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[6]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[6]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[7]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[7]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[8]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[8]/opit_0_inv_L5Q/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[9]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[9]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[10]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[10]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[11]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[11]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[1]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[1]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[3]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[3]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[5]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[5]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[7]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[7]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[8]/opit_0_inv_AQ/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[8]/opit_0_inv_AQ/CLK (6.764, 7.213, 6.383, 6.770) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/CLK_REGIONAL (6.764, 7.213, 6.383, 6.770) @@ -90554,7 +90306,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_control_path_adj/phy_addr_r[3]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_control_path_adj/phy_cke_r[3]/opit_0_inv/CLK (6.685, 7.133, 6.313, 6.699) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_control_path_adj/phy_cke_r[3]/opit_0_inv/CLK (6.681, 7.128, 6.309, 6.694) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_control_path_adj/phy_odt_r[3]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) @@ -90833,193 +90585,193 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[63]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[64]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[64]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[65]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[66]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[66]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[67]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[68]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[68]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[69]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[70]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[70]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[71]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[72]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[72]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[73]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[74]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[74]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[75]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[76]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[76]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[77]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[78]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[78]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[79]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[80]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[80]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[81]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[82]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[82]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[83]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[84]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[84]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[85]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[86]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[86]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[87]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[88]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[88]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[89]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[90]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[90]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[91]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[92]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[92]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[93]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[94]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[94]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[95]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[96]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[96]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[97]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[98]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[98]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[99]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[100]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[100]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[101]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[102]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[102]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[103]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[104]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[104]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[105]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[106]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[106]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[107]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[108]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[108]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[109]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[110]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[110]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[111]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[112]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[112]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[113]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[114]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[114]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[115]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[116]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[116]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[117]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[118]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[118]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[119]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[120]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[120]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[121]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[122]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[122]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[123]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[124]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[124]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[125]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[126]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[126]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[127]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) @@ -91217,31 +90969,31 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[191]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[192]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[192]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[193]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[194]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[194]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[195]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[196]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[196]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[197]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[198]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[198]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[199]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[200]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[200]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[201]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) @@ -91253,13 +91005,13 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[203]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[204]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[204]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[205]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[206]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[206]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[207]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) @@ -91277,19 +91029,19 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[211]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[212]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[212]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[213]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[214]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[214]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[215]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[216]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[216]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[217]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) @@ -91301,67 +91053,67 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[219]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[220]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[220]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[221]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[222]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[222]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[223]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[224]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[224]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[225]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[226]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[226]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[227]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[228]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[228]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[229]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[230]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[230]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[231]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[232]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[232]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[233]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[234]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[234]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[235]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[236]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[236]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[237]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[238]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[238]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[239]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[240]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[240]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[241]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) @@ -91373,13 +91125,13 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[243]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[244]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[244]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[245]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[246]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[246]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[247]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) @@ -91391,19 +91143,19 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[249]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[250]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[250]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[251]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[252]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[252]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[253]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[254]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[254]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[255]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) @@ -91505,13 +91257,13 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[3]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[4]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[4]/opit_0_inv/CLK (6.678, 7.125, 6.305, 6.691) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[5]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[6]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[6]/opit_0_inv/CLK (6.678, 7.125, 6.305, 6.691) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[7]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) @@ -91520,7 +91272,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[8]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[9]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[9]/opit_0_inv/CLK (6.701, 7.149, 6.329, 6.715) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_baddr_l[0]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) @@ -91589,301 +91341,301 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_cfg_apb/ddr_init_done/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[0]/opit_0_inv_L5Q_perm/CLK (6.666, 7.113, 6.293, 6.679) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[1]/opit_0_inv_L5Q_perm/CLK (6.666, 7.113, 6.293, 6.679) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[2]/opit_0_inv_L5Q_perm/CLK (6.666, 7.113, 6.293, 6.679) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[3]/opit_0_inv_L5Q_perm/CLK (6.692, 7.139, 6.319, 6.705) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[4]/opit_0_inv_L5Q_perm/CLK (6.697, 7.145, 6.325, 6.711) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[5]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[5]/opit_0_inv_L5Q_perm/CLK (6.662, 7.109, 6.290, 6.676) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[6]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[6]/opit_0_inv_L5Q_perm/CLK (6.674, 7.122, 6.302, 6.688) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[7]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[7]/opit_0_inv_L5Q_perm/CLK (6.662, 7.109, 6.290, 6.676) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[8]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[8]/opit_0_inv_L5Q_perm/CLK (6.709, 7.157, 6.337, 6.723) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[9]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[9]/opit_0_inv_L5Q_perm/CLK (6.692, 7.139, 6.319, 6.705) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[10]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[10]/opit_0_inv_L5Q_perm/CLK (6.709, 7.157, 6.337, 6.723) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[11]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[11]/opit_0_inv_L5Q_perm/CLK (6.709, 7.157, 6.337, 6.723) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[12]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[12]/opit_0_inv_L5Q_perm/CLK (6.709, 7.157, 6.337, 6.723) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[13]/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[13]/opit_0_inv_MUX4TO1Q/CLK (6.684, 7.131, 6.312, 6.698) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[14]/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[14]/opit_0_inv_MUX4TO1Q/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[15]/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[15]/opit_0_inv_MUX4TO1Q/CLK (6.670, 7.117, 6.298, 6.683) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[16]/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[16]/opit_0_inv_MUX4TO1Q/CLK (6.677, 7.124, 6.304, 6.690) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[17]/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[17]/opit_0_inv_MUX4TO1Q/CLK (6.685, 7.133, 6.313, 6.699) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[18]/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[18]/opit_0_inv_MUX4TO1Q/CLK (6.670, 7.117, 6.298, 6.683) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[19]/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[19]/opit_0_inv_MUX4TO1Q/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[20]/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[20]/opit_0_inv_MUX4TO1Q/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[21]/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[21]/opit_0_inv_MUX4TO1Q/CLK (6.685, 7.133, 6.313, 6.699) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[22]/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[22]/opit_0_inv_MUX4TO1Q/CLK (6.677, 7.124, 6.304, 6.690) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[23]/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[23]/opit_0_inv_MUX4TO1Q/CLK (6.677, 7.124, 6.304, 6.690) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[24]/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[24]/opit_0_inv_MUX4TO1Q/CLK (6.685, 7.133, 6.313, 6.699) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[25]/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[25]/opit_0_inv_MUX4TO1Q/CLK (6.670, 7.117, 6.298, 6.683) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[26]/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[26]/opit_0_inv_MUX4TO1Q/CLK (6.677, 7.124, 6.304, 6.690) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[27]/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[27]/opit_0_inv_MUX4TO1Q/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_id[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_id[0]/opit_0_inv_L5Q_perm/CLK (6.666, 7.113, 6.293, 6.679) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_id[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_id[1]/opit_0_inv_L5Q_perm/CLK (6.666, 7.113, 6.293, 6.679) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_id[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_id[2]/opit_0_inv_L5Q_perm/CLK (6.666, 7.113, 6.293, 6.679) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_id[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_id[3]/opit_0_inv_L5Q_perm/CLK (6.666, 7.113, 6.293, 6.679) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_len[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_len[0]/opit_0_inv_L5Q_perm/CLK (6.692, 7.139, 6.319, 6.705) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_len[1]/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_len[1]/opit_0_inv_MUX4TO1Q/CLK (6.692, 7.139, 6.319, 6.705) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_len[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_len[2]/opit_0_inv_L5Q_perm/CLK (6.674, 7.122, 6.302, 6.688) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_len[3]/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_len[3]/opit_0_inv_MUX4TO1Q/CLK (6.674, 7.122, 6.302, 6.688) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_new_row/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_new_row/opit_0_inv_MUX4TO1Q/CLK (6.693, 7.140, 6.320, 6.707) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_new_valid/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_new_valid/opit_0_inv_L5Q_perm/CLK (6.700, 7.148, 6.328, 6.714) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_pre_row/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_pre_row/opit_0_inv_MUX4TO1Q/CLK (6.693, 7.140, 6.320, 6.707) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_refresh/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_refresh/opit_0_inv_L5Q_perm/CLK (6.700, 7.148, 6.328, 6.714) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_write/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_write/opit_0_inv_L5Q_perm/CLK (6.662, 7.109, 6.290, 6.676) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[0]/opit_0_inv_L5Q_perm/CLK (6.689, 7.137, 6.317, 6.703) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[1]/opit_0_inv_L5Q_perm/CLK (6.697, 7.145, 6.325, 6.711) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[2]/opit_0_inv_L5Q_perm/CLK (6.689, 7.137, 6.317, 6.703) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[3]/opit_0_inv_L5Q_perm/CLK (6.697, 7.145, 6.325, 6.711) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[4]/opit_0_inv_L5Q_perm/CLK (6.689, 7.137, 6.317, 6.703) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[5]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[5]/opit_0_inv_L5Q_perm/CLK (6.697, 7.145, 6.325, 6.711) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[6]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[6]/opit_0_inv_L5Q_perm/CLK (6.689, 7.137, 6.317, 6.703) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[7]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[7]/opit_0_inv_L5Q_perm/CLK (6.697, 7.145, 6.325, 6.711) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/r_init/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/r_init/opit_0_inv_L5Q_perm/CLK (6.701, 7.149, 6.329, 6.715) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[1]/opit_0_inv_L5Q_perm/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[4]/opit_0_inv_L5Q_perm/CLK (6.696, 7.144, 6.324, 6.710) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[5]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[5]/opit_0_inv_L5Q_perm/CLK (6.684, 7.131, 6.312, 6.698) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[6]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[6]/opit_0_inv_L5Q_perm/CLK (6.684, 7.131, 6.312, 6.698) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[7]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[7]/opit_0_inv_L5Q_perm/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[8]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[8]/opit_0_inv_L5Q_perm/CLK (6.684, 7.131, 6.312, 6.698) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[9]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[9]/opit_0_inv_L5Q_perm/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[10]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[10]/opit_0_inv_L5Q_perm/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[11]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[11]/opit_0_inv_L5Q_perm/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[12]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[12]/opit_0_inv_L5Q_perm/CLK (6.684, 7.131, 6.312, 6.698) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_req/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_req/opit_0_inv_L5Q_perm/CLK (6.693, 7.140, 6.320, 6.707) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[13]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[13]/opit_0_inv_L5Q_perm/CLK (6.696, 7.144, 6.324, 6.710) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[14]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[14]/opit_0_inv_L5Q_perm/CLK (6.696, 7.144, 6.324, 6.710) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[15]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[15]/opit_0_inv_L5Q_perm/CLK (6.670, 7.117, 6.298, 6.683) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[16]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[16]/opit_0_inv_L5Q_perm/CLK (6.677, 7.124, 6.304, 6.690) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[17]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[17]/opit_0_inv_L5Q_perm/CLK (6.670, 7.117, 6.298, 6.683) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[18]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[18]/opit_0_inv_L5Q_perm/CLK (6.670, 7.117, 6.298, 6.683) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[19]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[19]/opit_0_inv_L5Q_perm/CLK (6.696, 7.144, 6.324, 6.710) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[20]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[20]/opit_0_inv_L5Q_perm/CLK (6.696, 7.144, 6.324, 6.710) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[21]/opit_0_inv_L5Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[21]/opit_0_inv_L5Q_perm/CLK (6.670, 7.117, 6.298, 6.683) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[22]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[22]/opit_0_inv_L5Q_perm/CLK (6.677, 7.124, 6.304, 6.690) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[23]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[23]/opit_0_inv_L5Q_perm/CLK (6.670, 7.117, 6.298, 6.683) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[24]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[24]/opit_0_inv_L5Q_perm/CLK (6.677, 7.124, 6.304, 6.690) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[25]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[25]/opit_0_inv_L5Q_perm/CLK (6.670, 7.117, 6.298, 6.683) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[26]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[26]/opit_0_inv_L5Q_perm/CLK (6.677, 7.124, 6.304, 6.690) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[27]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[27]/opit_0_inv_L5Q_perm/CLK (6.696, 7.144, 6.324, 6.710) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_cmd_ready/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_cmd_ready/opit_0_inv_L5Q_perm/CLK (6.701, 7.149, 6.329, 6.715) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/cnt[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/cnt[0]/opit_0_inv_L5Q_perm/CLK (6.694, 7.141, 6.321, 6.708) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/cnt[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/cnt[1]/opit_0_inv_L5Q_perm/CLK (6.701, 7.149, 6.329, 6.715) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/cnt[2]/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/cnt[2]/opit_0_inv_MUX4TO1Q/CLK (6.701, 7.149, 6.329, 6.715) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/cnt[3]/opit_0_inv_L6Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/cnt[3]/opit_0_inv_L6Q_perm/CLK (6.701, 7.149, 6.329, 6.715) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[0]/opit_0_inv_L5Q_perm/CLK (6.674, 7.122, 6.302, 6.688) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[1]/opit_0_inv_L5Q_perm/CLK (6.674, 7.122, 6.302, 6.688) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[2]/opit_0_inv_L5Q_perm/CLK (6.674, 7.122, 6.302, 6.688) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[3]/opit_0_inv_L5Q_perm/CLK (6.684, 7.131, 6.312, 6.698) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[4]/opit_0_inv_L5Q_perm/CLK (6.678, 7.125, 6.305, 6.691) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[5]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[5]/opit_0_inv_L5Q_perm/CLK (6.678, 7.125, 6.305, 6.691) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[6]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[6]/opit_0_inv_L5Q_perm/CLK (6.684, 7.131, 6.312, 6.698) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[7]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[7]/opit_0_inv_L5Q_perm/CLK (6.678, 7.125, 6.305, 6.691) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[8]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[8]/opit_0_inv_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[9]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[9]/opit_0_inv_L5Q_perm/CLK (6.678, 7.125, 6.305, 6.691) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[10]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[10]/opit_0_inv/CLK (6.700, 7.148, 6.328, 6.714) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[11]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[11]/opit_0_inv/CLK (6.700, 7.148, 6.328, 6.714) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[12]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[12]/opit_0_inv/CLK (6.700, 7.148, 6.328, 6.714) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[13]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[13]/opit_0_inv/CLK (6.686, 7.134, 6.314, 6.700) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[14]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[14]/opit_0_inv/CLK (6.686, 7.134, 6.314, 6.700) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[15]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) @@ -91898,112 +91650,112 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[18]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[19]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[19]/opit_0_inv/CLK (6.686, 7.134, 6.314, 6.700) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[20]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[20]/opit_0_inv/CLK (6.686, 7.134, 6.314, 6.700) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[21]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[21]/opit_0_inv/CLK (6.686, 7.134, 6.314, 6.700) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[22]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[22]/opit_0_inv/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[23]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[23]/opit_0_inv/CLK (6.700, 7.148, 6.328, 6.714) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[24]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[24]/opit_0_inv/CLK (6.700, 7.148, 6.328, 6.714) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[25]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[25]/opit_0_inv/CLK (6.700, 7.148, 6.328, 6.714) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[26]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[27]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[27]/opit_0_inv/CLK (6.686, 7.134, 6.314, 6.700) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_cmd[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_cmd[0]/opit_0_inv_L5Q_perm/CLK (6.705, 7.152, 6.332, 6.719) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_cmd[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_cmd[1]/opit_0_inv_L5Q_perm/CLK (6.705, 7.152, 6.332, 6.719) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_cmd[2]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_cmd[2]/opit_0_inv/CLK (6.705, 7.152, 6.332, 6.719) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_cmd[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_cmd[3]/opit_0_inv_L5Q_perm/CLK (6.705, 7.152, 6.332, 6.719) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_en/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_en/opit_0_inv_L5Q_perm/CLK (6.681, 7.128, 6.309, 6.694) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_id[0]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_id[0]/opit_0_inv/CLK (6.689, 7.137, 6.317, 6.703) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_id[1]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_id[1]/opit_0_inv/CLK (6.689, 7.137, 6.317, 6.703) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_id[2]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_id[2]/opit_0_inv/CLK (6.689, 7.137, 6.317, 6.703) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_id[3]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_id[3]/opit_0_inv/CLK (6.689, 7.137, 6.317, 6.703) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_tworw/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_tworw/opit_0_inv_L5Q_perm/CLK (6.701, 7.149, 6.329, 6.715) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[0]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[0]/opit_0_inv/CLK (6.671, 7.118, 6.299, 6.685) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[1]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[1]/opit_0_inv/CLK (6.671, 7.118, 6.299, 6.685) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[2]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[2]/opit_0_inv/CLK (6.671, 7.118, 6.299, 6.685) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[3]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[3]/opit_0_inv/CLK (6.685, 7.133, 6.313, 6.699) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[4]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[4]/opit_0_inv/CLK (6.685, 7.133, 6.313, 6.699) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[5]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[5]/opit_0_inv/CLK (6.682, 7.129, 6.310, 6.696) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[6]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[6]/opit_0_inv/CLK (6.666, 7.113, 6.293, 6.679) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[7]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[7]/opit_0_inv/CLK (6.671, 7.118, 6.299, 6.685) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[8]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[8]/opit_0_inv/CLK (6.673, 7.120, 6.301, 6.687) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[9]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[9]/opit_0_inv/CLK (6.685, 7.133, 6.313, 6.699) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[10]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[10]/opit_0_inv/CLK (6.693, 7.140, 6.320, 6.707) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[11]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[11]/opit_0_inv/CLK (6.685, 7.133, 6.313, 6.699) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[12]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[12]/opit_0_inv/CLK (6.685, 7.133, 6.313, 6.699) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[13]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[13]/opit_0_inv/CLK (6.673, 7.120, 6.301, 6.687) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[14]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[14]/opit_0_inv/CLK (6.673, 7.120, 6.301, 6.687) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[15]/opit_0_inv/CLK (6.674, 7.122, 6.302, 6.688) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[15]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[16]/opit_0_inv/CLK (6.674, 7.122, 6.302, 6.688) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[16]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[17]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) @@ -92012,16 +91764,16 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[18]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[19]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[19]/opit_0_inv/CLK (6.685, 7.133, 6.313, 6.699) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[20]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[20]/opit_0_inv/CLK (6.673, 7.120, 6.301, 6.687) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[21]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[22]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[22]/opit_0_inv/CLK (6.685, 7.133, 6.313, 6.699) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[23]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) @@ -92036,355 +91788,355 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[26]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[27]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[27]/opit_0_inv/CLK (6.673, 7.120, 6.301, 6.687) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_done/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_done/opit_0_inv_L5Q/CLK (6.681, 7.128, 6.309, 6.694) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/rw_diff/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/rw_diff/opit_0_inv_L5Q_perm/CLK (6.689, 7.137, 6.317, 6.703) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[0]/opit_0_inv_L5Q_perm/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[1]/opit_0_inv_L5Q_perm/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[2]/opit_0_inv_L5Q_perm/CLK (6.700, 7.148, 6.328, 6.714) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[3]/opit_0_inv_L5Q_perm/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[4]/opit_0_inv_L5Q_perm/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[5]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[5]/opit_0_inv/CLK (6.700, 7.148, 6.328, 6.714) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm/CLK (6.667, 7.114, 6.294, 6.680) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.667, 7.114, 6.294, 6.680) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm/CLK (6.662, 7.109, 6.290, 6.676) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm/CLK (6.662, 7.109, 6.290, 6.676) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm/CLK (6.662, 7.109, 6.290, 6.676) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm/CLK (6.658, 7.105, 6.286, 6.671) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm/CLK (6.662, 7.109, 6.290, 6.676) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm/CLK (6.658, 7.105, 6.286, 6.671) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm/CLK (6.658, 7.105, 6.286, 6.671) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm/CLK (6.658, 7.105, 6.286, 6.671) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm/CLK (6.658, 7.105, 6.286, 6.671) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm/CLK (6.658, 7.105, 6.286, 6.671) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm/CLK (6.658, 7.105, 6.286, 6.671) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.658, 7.105, 6.286, 6.671) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm/CLK (6.678, 7.125, 6.305, 6.691) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm/CLK (6.678, 7.125, 6.305, 6.691) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm/CLK (6.662, 7.109, 6.290, 6.676) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm/CLK (6.662, 7.109, 6.290, 6.676) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm/CLK (6.662, 7.109, 6.290, 6.676) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm/CLK (6.662, 7.109, 6.290, 6.676) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm/CLK (6.662, 7.109, 6.290, 6.676) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm/CLK (6.678, 7.125, 6.305, 6.691) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm/CLK (6.678, 7.125, 6.305, 6.691) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm/CLK (6.662, 7.109, 6.290, 6.676) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm/CLK (6.662, 7.109, 6.290, 6.676) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm/CLK (6.686, 7.134, 6.314, 6.700) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.686, 7.134, 6.314, 6.700) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm/CLK (6.686, 7.134, 6.314, 6.700) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm/CLK (6.686, 7.134, 6.314, 6.700) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm/CLK (6.681, 7.128, 6.309, 6.694) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm/CLK (6.681, 7.128, 6.309, 6.694) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm/CLK (6.701, 7.149, 6.329, 6.715) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm/CLK (6.701, 7.149, 6.329, 6.715) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm/CLK (6.701, 7.149, 6.329, 6.715) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm/CLK (6.686, 7.134, 6.314, 6.700) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm/CLK (6.694, 7.141, 6.321, 6.708) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm/CLK (6.694, 7.141, 6.321, 6.708) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm/CLK (6.686, 7.134, 6.314, 6.700) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm/CLK (6.670, 7.117, 6.298, 6.683) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.674, 7.122, 6.302, 6.688) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm/CLK (6.670, 7.117, 6.298, 6.683) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm/CLK (6.670, 7.117, 6.298, 6.683) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm/CLK (6.678, 7.125, 6.305, 6.691) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm/CLK (6.674, 7.122, 6.302, 6.688) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm/CLK (6.686, 7.134, 6.314, 6.700) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm/CLK (6.674, 7.122, 6.302, 6.688) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm/CLK (6.682, 7.129, 6.310, 6.696) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm/CLK (6.678, 7.125, 6.305, 6.691) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm/CLK (6.678, 7.125, 6.305, 6.691) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm/CLK (6.670, 7.117, 6.298, 6.683) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm/CLK (6.678, 7.125, 6.305, 6.691) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm/CLK (6.662, 7.109, 6.290, 6.676) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.679, 7.126, 6.306, 6.692) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm/CLK (6.679, 7.126, 6.306, 6.692) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm/CLK (6.679, 7.126, 6.306, 6.692) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm/CLK (6.666, 7.113, 6.293, 6.679) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm/CLK (6.678, 7.125, 6.305, 6.691) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm/CLK (6.686, 7.134, 6.314, 6.700) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm/CLK (6.679, 7.126, 6.306, 6.692) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm/CLK (6.686, 7.134, 6.314, 6.700) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm/CLK (6.679, 7.126, 6.306, 6.692) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm/CLK (6.667, 7.114, 6.294, 6.680) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.667, 7.114, 6.294, 6.680) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm/CLK (6.670, 7.117, 6.298, 6.683) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm/CLK (6.670, 7.117, 6.298, 6.683) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm/CLK (6.686, 7.134, 6.314, 6.700) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm/CLK (6.678, 7.125, 6.305, 6.691) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm/CLK (6.670, 7.117, 6.298, 6.683) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm/CLK (6.686, 7.134, 6.314, 6.700) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm/CLK (6.670, 7.117, 6.298, 6.683) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm/CLK (6.670, 7.117, 6.298, 6.683) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm/CLK (6.670, 7.117, 6.298, 6.683) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm/CLK (6.670, 7.117, 6.298, 6.683) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm/CLK (6.670, 7.117, 6.298, 6.683) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm/CLK (6.682, 7.129, 6.310, 6.696) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.682, 7.129, 6.310, 6.696) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm/CLK (6.701, 7.149, 6.329, 6.715) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm/CLK (6.694, 7.141, 6.321, 6.708) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm/CLK (6.693, 7.140, 6.320, 6.707) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm/CLK (6.685, 7.133, 6.313, 6.699) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm/CLK (6.693, 7.140, 6.320, 6.707) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm/CLK (6.693, 7.140, 6.320, 6.707) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm/CLK (6.685, 7.133, 6.313, 6.699) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm/CLK (6.697, 7.145, 6.325, 6.711) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm/CLK (6.697, 7.145, 6.325, 6.711) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm/CLK (6.697, 7.145, 6.325, 6.711) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm/CLK (6.697, 7.145, 6.325, 6.711) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm/CLK (6.682, 7.129, 6.310, 6.696) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.694, 7.141, 6.321, 6.708) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm/CLK (6.685, 7.133, 6.313, 6.699) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt0[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm/CLK (6.685, 7.133, 6.313, 6.699) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm/CLK (6.693, 7.140, 6.320, 6.707) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[0].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.662, 7.109, 6.290, 6.676) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[0].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[0].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.662, 7.109, 6.290, 6.676) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[0].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[0].trc_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.662, 7.109, 6.290, 6.676) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[0].trc_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[0].trc_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (6.662, 7.109, 6.290, 6.676) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[0].trc_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[1].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -92399,340 +92151,340 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[1].trc_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[2].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.662, 7.109, 6.290, 6.676) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[2].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[2].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.658, 7.105, 6.286, 6.671) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[2].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[2].trc_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.662, 7.109, 6.290, 6.676) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[2].trc_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[2].trc_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (6.658, 7.105, 6.286, 6.671) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[2].trc_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[3].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.670, 7.117, 6.298, 6.683) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[3].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[3].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.670, 7.117, 6.298, 6.683) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[3].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[3].trc_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.667, 7.114, 6.294, 6.680) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[3].trc_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[3].trc_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (6.670, 7.117, 6.298, 6.683) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[3].trc_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[4].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.681, 7.128, 6.309, 6.694) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[4].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[4].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.681, 7.128, 6.309, 6.694) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[4].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[4].trc_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.681, 7.128, 6.309, 6.694) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[4].trc_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[4].trc_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (6.681, 7.128, 6.309, 6.694) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[4].trc_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[5].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.677, 7.124, 6.304, 6.690) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[5].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[5].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.677, 7.124, 6.304, 6.690) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[5].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[5].trc_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.677, 7.124, 6.304, 6.690) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[5].trc_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[5].trc_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (6.677, 7.124, 6.304, 6.690) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[5].trc_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[6].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.658, 7.105, 6.286, 6.671) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[6].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[6].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.658, 7.105, 6.286, 6.671) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[6].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[6].trc_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.658, 7.105, 6.286, 6.671) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[6].trc_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[6].trc_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (6.658, 7.105, 6.286, 6.671) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[6].trc_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[7].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.669, 7.116, 6.297, 6.682) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[7].trc_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[7].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.669, 7.116, 6.297, 6.682) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[7].trc_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[7].trc_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.669, 7.116, 6.297, 6.682) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[7].trc_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[7].trc_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (6.669, 7.116, 6.297, 6.682) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[7].trc_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.662, 7.109, 6.290, 6.676) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.682, 7.129, 6.310, 6.696) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (6.682, 7.129, 6.310, 6.696) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.682, 7.129, 6.310, 6.696) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.682, 7.129, 6.310, 6.696) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.661, 7.108, 6.289, 6.675) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.661, 7.108, 6.289, 6.675) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (6.661, 7.108, 6.289, 6.675) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.666, 7.113, 6.293, 6.679) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.666, 7.113, 6.293, 6.679) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.658, 7.105, 6.286, 6.671) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.662, 7.109, 6.290, 6.676) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (6.658, 7.105, 6.286, 6.671) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.658, 7.105, 6.286, 6.671) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.658, 7.105, 6.286, 6.671) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.670, 7.117, 6.298, 6.683) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.667, 7.114, 6.294, 6.680) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (6.667, 7.114, 6.294, 6.680) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.674, 7.122, 6.302, 6.688) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.667, 7.114, 6.294, 6.680) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.658, 7.105, 6.286, 6.671) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.669, 7.116, 6.297, 6.682) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (6.669, 7.116, 6.297, 6.682) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.669, 7.116, 6.297, 6.682) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.669, 7.116, 6.297, 6.682) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.661, 7.108, 6.289, 6.675) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (6.678, 7.125, 6.305, 6.691) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.678, 7.125, 6.305, 6.691) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.678, 7.125, 6.305, 6.691) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (6.681, 7.128, 6.309, 6.694) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.693, 7.140, 6.320, 6.707) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.696, 7.144, 6.324, 6.710) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (6.693, 7.140, 6.320, 6.707) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.693, 7.140, 6.320, 6.707) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.693, 7.140, 6.320, 6.707) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (6.700, 7.148, 6.328, 6.714) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.696, 7.144, 6.324, 6.710) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.696, 7.144, 6.324, 6.710) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (6.684, 7.131, 6.312, 6.698) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.693, 7.140, 6.320, 6.707) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.693, 7.140, 6.320, 6.707) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (6.696, 7.144, 6.324, 6.710) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.685, 7.133, 6.313, 6.699) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.678, 7.125, 6.305, 6.691) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (6.678, 7.125, 6.305, 6.691) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.678, 7.125, 6.305, 6.691) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.693, 7.140, 6.320, 6.707) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (6.678, 7.125, 6.305, 6.691) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.669, 7.116, 6.297, 6.682) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.684, 7.131, 6.312, 6.698) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (6.669, 7.116, 6.297, 6.682) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.684, 7.131, 6.312, 6.698) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.669, 7.116, 6.297, 6.682) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (6.684, 7.131, 6.312, 6.698) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.688, 7.136, 6.316, 6.702) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.688, 7.136, 6.316, 6.702) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (6.696, 7.144, 6.324, 6.710) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.688, 7.136, 6.316, 6.702) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.688, 7.136, 6.316, 6.702) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (6.681, 7.128, 6.309, 6.694) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.684, 7.131, 6.312, 6.698) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.696, 7.144, 6.324, 6.710) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (6.696, 7.144, 6.324, 6.710) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.684, 7.131, 6.312, 6.698) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.684, 7.131, 6.312, 6.698) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (6.684, 7.131, 6.312, 6.698) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.693, 7.140, 6.320, 6.707) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.700, 7.148, 6.328, 6.714) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (6.696, 7.144, 6.324, 6.710) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.700, 7.148, 6.328, 6.714) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.700, 7.148, 6.328, 6.714) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (6.700, 7.148, 6.328, 6.714) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[1]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) @@ -92756,25 +92508,25 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[7]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[8]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[8]/opit_0_inv/CLK (6.678, 7.125, 6.305, 6.691) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[9]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[9]/opit_0_inv/CLK (6.678, 7.125, 6.305, 6.691) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[10]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[10]/opit_0_inv/CLK (6.666, 7.113, 6.293, 6.679) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[11]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[11]/opit_0_inv/CLK (6.666, 7.113, 6.293, 6.679) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[12]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[12]/opit_0_inv/CLK (6.679, 7.126, 6.306, 6.692) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[13]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[13]/opit_0_inv/CLK (6.666, 7.113, 6.293, 6.679) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[14]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[14]/opit_0_inv/CLK (6.678, 7.125, 6.305, 6.691) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[15]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) @@ -92789,7 +92541,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[18]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[19]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[19]/opit_0_inv/CLK (6.679, 7.126, 6.306, 6.692) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[20]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) @@ -92798,25 +92550,25 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[21]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[22]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[22]/opit_0_inv/CLK (6.679, 7.126, 6.306, 6.692) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[23]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[24]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[24]/opit_0_inv/CLK (6.679, 7.126, 6.306, 6.692) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[25]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[25]/opit_0_inv/CLK (6.666, 7.113, 6.293, 6.679) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[26]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[26]/opit_0_inv/CLK (6.679, 7.126, 6.306, 6.692) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[27]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[27]/opit_0_inv/CLK (6.678, 7.125, 6.305, 6.691) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[28]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[28]/opit_0_inv/CLK (6.678, 7.125, 6.305, 6.691) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[29]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) @@ -92861,31 +92613,31 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_valid_d1/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/cmd_act_pass/opit_0_inv_L5Q_perm/CLK (6.697, 7.145, 6.325, 6.711) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/cmd_act_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/ctrl_back_rdy/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/cmd_rd_pass/opit_0_inv_MUX4TO1Q/CLK (6.686, 7.134, 6.314, 6.700) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/cmd_rd_pass/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm/CLK (6.697, 7.145, 6.325, 6.711) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/r_cnt_pass/opit_0_inv_MUX4TO1Q/CLK (6.701, 7.149, 6.329, 6.715) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/r_cnt_pass/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm/CLK (6.697, 7.145, 6.325, 6.711) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm/CLK (6.701, 7.149, 6.329, 6.715) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm/CLK (6.709, 7.157, 6.337, 6.723) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm/CLK (6.709, 7.157, 6.337, 6.723) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_cmd_accepted_l/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -92909,22 +92661,22 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[3]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[4]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[4]/opit_0_inv/CLK (6.678, 7.125, 6.305, 6.691) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[5]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[5]/opit_0_inv/CLK (6.678, 7.125, 6.305, 6.691) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[6]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[6]/opit_0_inv/CLK (6.678, 7.125, 6.305, 6.691) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[7]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[7]/opit_0_inv/CLK (6.694, 7.141, 6.321, 6.708) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[8]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[9]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[9]/opit_0_inv/CLK (6.682, 7.129, 6.310, 6.696) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[10]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) @@ -92948,16 +92700,16 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[16]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[17]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[17]/opit_0_inv/CLK (6.694, 7.141, 6.321, 6.708) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[18]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[19]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[19]/opit_0_inv/CLK (6.682, 7.129, 6.310, 6.696) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[20]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[20]/opit_0_inv/CLK (6.678, 7.125, 6.305, 6.691) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[21]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) @@ -93017,7 +92769,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[5]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[5]/opit_0_inv_L5Q_perm/CLK (6.682, 7.129, 6.310, 6.696) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[6]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -93026,25 +92778,25 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[7]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[8]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[8]/opit_0_inv_L5Q_perm/CLK (6.693, 7.140, 6.320, 6.707) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[9]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[9]/opit_0_inv_L5Q_perm/CLK (6.662, 7.109, 6.290, 6.676) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[10]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[10]/opit_0_inv_L5Q_perm/CLK (6.662, 7.109, 6.290, 6.676) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[11]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[11]/opit_0_inv_L5Q_perm/CLK (6.670, 7.117, 6.298, 6.683) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[12]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[12]/opit_0_inv_L5Q_perm/CLK (6.671, 7.118, 6.299, 6.685) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[13]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[13]/opit_0_inv_L5Q_perm/CLK (6.670, 7.117, 6.298, 6.683) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[14]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[14]/opit_0_inv_L5Q_perm/CLK (6.682, 7.129, 6.310, 6.696) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[15]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -93056,43 +92808,43 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[17]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[18]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[18]/opit_0_inv_L5Q_perm/CLK (6.682, 7.129, 6.310, 6.696) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[19]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[19]/opit_0_inv_L5Q_perm/CLK (6.671, 7.118, 6.299, 6.685) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[20]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[21]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[21]/opit_0_inv_L5Q_perm/CLK (6.694, 7.141, 6.321, 6.708) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[22]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[22]/opit_0_inv_L5Q_perm/CLK (6.671, 7.118, 6.299, 6.685) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[23]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[24]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[24]/opit_0_inv_L5Q_perm/CLK (6.662, 7.109, 6.290, 6.676) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[25]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[25]/opit_0_inv_L5Q_perm/CLK (6.662, 7.109, 6.290, 6.676) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[26]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[26]/opit_0_inv_L5Q_perm/CLK (6.671, 7.118, 6.299, 6.685) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[27]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[27]/opit_0_inv_L5Q_perm/CLK (6.682, 7.129, 6.310, 6.696) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[28]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[28]/opit_0_inv_L5Q_perm/CLK (6.694, 7.141, 6.321, 6.708) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[29]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[30]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[30]/opit_0_inv_L5Q_perm/CLK (6.694, 7.141, 6.321, 6.708) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[31]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -93131,7 +92883,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_valid/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.682, 7.129, 6.310, 6.696) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -93146,7 +92898,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[1].mcdq_tfaw/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.686, 7.134, 6.314, 6.700) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[1].mcdq_tfaw/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[1].mcdq_tfaw/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -93161,7 +92913,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[1].mcdq_tfaw/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.686, 7.134, 6.314, 6.700) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -93182,40 +92934,40 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/cnt[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/cnt_pass/opit_0_inv_L5Q_perm/CLK (6.686, 7.134, 6.314, 6.700) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/cnt_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.667, 7.114, 6.294, 6.680) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.667, 7.114, 6.294, 6.680) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (6.667, 7.114, 6.294, 6.680) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.667, 7.114, 6.294, 6.680) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[3]/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (6.686, 7.134, 6.314, 6.700) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[5]/opit_0_inv_L5Q_perm/CLK (6.686, 7.134, 6.314, 6.700) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[5]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[6]/opit_0_inv_L5Q_perm/CLK (6.686, 7.134, 6.314, 6.700) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[6]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.701, 7.149, 6.329, 6.715) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt0[1]/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt0[2]/opit_0_inv_L5Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt0[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -93227,16 +92979,16 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm/CLK (6.709, 7.157, 6.337, 6.723) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm/CLK (6.709, 7.157, 6.337, 6.723) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt2[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm/CLK (6.701, 7.149, 6.329, 6.715) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt2[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt2[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -93266,19 +93018,19 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[6]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/cmd_wr_pass/opit_0_inv_MUX4TO1Q/CLK (6.697, 7.145, 6.325, 6.711) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/cmd_wr_pass/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm/CLK (6.697, 7.145, 6.325, 6.711) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/r_cnt_almost_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.697, 7.145, 6.325, 6.711) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/r_cnt_pass/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm/CLK (6.697, 7.145, 6.325, 6.711) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/timing_cnt1[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm/CLK (6.697, 7.145, 6.325, 6.711) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/timing_cnt1[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) @@ -93287,13 +93039,13 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_2/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_3/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_3/ram16x1d/WCLK (6.709, 7.157, 6.337, 6.723) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_4/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_4/ram16x1d/WCLK (6.709, 7.157, 6.337, 6.723) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_5/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_5/ram16x1d/WCLK (6.694, 7.141, 6.321, 6.708) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_6/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) @@ -93302,7 +93054,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_7/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_8/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_8/ram16x1d/WCLK (6.681, 7.128, 6.309, 6.694) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_9/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) @@ -93311,28 +93063,28 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_10/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_11/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_11/ram16x1d/WCLK (6.661, 7.108, 6.289, 6.675) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_12/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_13/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_13/ram16x1d/WCLK (6.661, 7.108, 6.289, 6.675) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_14/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_14/ram16x1d/WCLK (6.662, 7.109, 6.290, 6.676) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_15/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_15/ram16x1d/WCLK (6.696, 7.144, 6.324, 6.710) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_16/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_16/ram16x1d/WCLK (6.696, 7.144, 6.324, 6.710) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_17/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_17/ram16x1d/WCLK (6.696, 7.144, 6.324, 6.710) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_18/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_18/ram16x1d/WCLK (6.694, 7.141, 6.321, 6.708) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_19/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) @@ -93344,13 +93096,13 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_21/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_22/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_22/ram16x1d/WCLK (6.662, 7.109, 6.290, 6.676) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_23/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_24/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_24/ram16x1d/WCLK (6.662, 7.109, 6.290, 6.676) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_25/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) @@ -93359,16 +93111,16 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_26/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_27/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_27/ram16x1d/WCLK (6.681, 7.128, 6.309, 6.694) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_28/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_28/ram16x1d/WCLK (6.694, 7.141, 6.321, 6.708) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_29/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_30/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_30/ram16x1d/WCLK (6.694, 7.141, 6.321, 6.708) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_31/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) @@ -93377,7 +93129,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_32/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_33/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_33/ram16x1d/WCLK (6.709, 7.157, 6.337, 6.723) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_34/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) @@ -93389,7 +93141,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_36/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_38/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_38/ram16x1d/WCLK (6.709, 7.157, 6.337, 6.723) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_39/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) @@ -93404,37 +93156,37 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_42/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.raddr_msb/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.raddr_msb/opit_0_inv_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[1]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[1]/opit_0_inv_A2Q21/CLK (6.669, 7.116, 6.297, 6.682) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[3]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[3]/opit_0_inv_A2Q21/CLK (6.669, 7.116, 6.297, 6.682) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[4]/opit_0_inv_AQ/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[4]/opit_0_inv_AQ/CLK (6.673, 7.120, 6.301, 6.687) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_almost_full/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_almost_full/opit_0_inv_MUX4TO1Q/CLK (6.681, 7.128, 6.309, 6.694) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_rempty/opit_0_inv_AQ_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_rempty/opit_0_inv_AQ_perm/CLK (6.673, 7.120, 6.301, 6.687) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_wfull/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_wfull/opit_0_inv_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.waddr_msb/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.waddr_msb/opit_0_inv_L5Q_perm/CLK (6.681, 7.128, 6.309, 6.694) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK (6.677, 7.124, 6.304, 6.690) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[3]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[3]/opit_0_inv_A2Q21/CLK (6.677, 7.124, 6.304, 6.690) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[4]/opit_0_inv_AQ/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[4]/opit_0_inv_AQ/CLK (6.681, 7.128, 6.309, 6.694) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) @@ -93446,10 +93198,10 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_3/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_4/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_4/ram16x1d/WCLK (6.697, 7.145, 6.325, 6.711) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_5/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_5/ram16x1d/WCLK (6.697, 7.145, 6.325, 6.711) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_6/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) @@ -93458,34 +93210,34 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_7/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_8/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_8/ram16x1d/WCLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_9/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_9/ram16x1d/WCLK (6.658, 7.105, 6.286, 6.671) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_10/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_10/ram16x1d/WCLK (6.658, 7.105, 6.286, 6.671) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_11/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_11/ram16x1d/WCLK (6.667, 7.114, 6.294, 6.680) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_12/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_12/ram16x1d/WCLK (6.667, 7.114, 6.294, 6.680) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_13/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_13/ram16x1d/WCLK (6.658, 7.105, 6.286, 6.671) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_14/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_14/ram16x1d/WCLK (6.667, 7.114, 6.294, 6.680) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_15/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_15/ram16x1d/WCLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_16/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_16/ram16x1d/WCLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_17/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_17/ram16x1d/WCLK (6.688, 7.136, 6.316, 6.702) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_18/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) @@ -93500,31 +93252,31 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_21/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_22/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_22/ram16x1d/WCLK (6.667, 7.114, 6.294, 6.680) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_23/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_24/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_24/ram16x1d/WCLK (6.671, 7.118, 6.299, 6.685) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_25/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_25/ram16x1d/WCLK (6.658, 7.105, 6.286, 6.671) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_26/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_27/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_27/ram16x1d/WCLK (6.685, 7.133, 6.313, 6.699) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_28/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_28/ram16x1d/WCLK (6.697, 7.145, 6.325, 6.711) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_29/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_29/ram16x1d/WCLK (6.671, 7.118, 6.299, 6.685) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_30/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_30/ram16x1d/WCLK (6.697, 7.145, 6.325, 6.711) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_31/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) @@ -93533,7 +93285,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_32/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_33/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_33/ram16x1d/WCLK (6.701, 7.149, 6.329, 6.715) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_34/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) @@ -93560,16 +93312,16 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_42/ram16x1d/WCLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.raddr_msb/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.raddr_msb/opit_0_inv_L5Q_perm/CLK (6.689, 7.137, 6.317, 6.703) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[1]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[1]/opit_0_inv_A2Q21/CLK (6.697, 7.145, 6.325, 6.711) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[3]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[3]/opit_0_inv_A2Q21/CLK (6.697, 7.145, 6.325, 6.711) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[4]/opit_0_inv_AQ/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[4]/opit_0_inv_AQ/CLK (6.701, 7.149, 6.329, 6.715) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_almost_full/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) @@ -93584,19 +93336,19 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.waddr_msb/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK (6.697, 7.145, 6.325, 6.711) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[3]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[3]/opit_0_inv_A2Q21/CLK (6.697, 7.145, 6.325, 6.711) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[4]/opit_0_inv_AQ/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[4]/opit_0_inv_AQ/CLK (6.701, 7.149, 6.329, 6.715) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_a_valid/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_a_valid/opit_0_inv_MUX4TO1Q/CLK (6.689, 7.137, 6.317, 6.703) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_b_valid/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_b_valid/opit_0_inv_L5Q_perm/CLK (6.701, 7.149, 6.329, 6.715) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[1]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) @@ -93608,10 +93360,10 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[3]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[4]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[4]/opit_0_inv/CLK (6.693, 7.140, 6.320, 6.707) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[5]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[5]/opit_0_inv/CLK (6.697, 7.145, 6.325, 6.711) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[6]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) @@ -93620,7 +93372,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[7]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[8]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[8]/opit_0_inv/CLK (6.693, 7.140, 6.320, 6.707) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[9]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) @@ -93629,7 +93381,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[10]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[11]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[11]/opit_0_inv/CLK (6.661, 7.108, 6.289, 6.675) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[12]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) @@ -93638,16 +93390,16 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[13]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[14]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[14]/opit_0_inv/CLK (6.669, 7.116, 6.297, 6.682) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[15]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[15]/opit_0_inv/CLK (6.693, 7.140, 6.320, 6.707) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[16]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[16]/opit_0_inv/CLK (6.693, 7.140, 6.320, 6.707) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[17]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[17]/opit_0_inv/CLK (6.693, 7.140, 6.320, 6.707) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[18]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) @@ -93662,28 +93414,28 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[21]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[22]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[22]/opit_0_inv/CLK (6.674, 7.122, 6.302, 6.688) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[23]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[23]/opit_0_inv/CLK (6.674, 7.122, 6.302, 6.688) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[24]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[24]/opit_0_inv/CLK (6.674, 7.122, 6.302, 6.688) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[25]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[25]/opit_0_inv/CLK (6.674, 7.122, 6.302, 6.688) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[26]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[26]/opit_0_inv/CLK (6.674, 7.122, 6.302, 6.688) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[27]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[27]/opit_0_inv/CLK (6.693, 7.140, 6.320, 6.707) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[28]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[28]/opit_0_inv/CLK (6.697, 7.145, 6.325, 6.711) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[29]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[29]/opit_0_inv/CLK (6.674, 7.122, 6.302, 6.688) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[30]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) @@ -93695,7 +93447,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[32]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[33]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[33]/opit_0_inv/CLK (6.697, 7.145, 6.325, 6.711) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[34]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) @@ -93731,10 +93483,10 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[3]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[4]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[4]/opit_0_inv/CLK (6.705, 7.152, 6.332, 6.719) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[5]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[5]/opit_0_inv/CLK (6.705, 7.152, 6.332, 6.719) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[6]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) @@ -93743,34 +93495,34 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[7]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[8]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[8]/opit_0_inv/CLK (6.685, 7.133, 6.313, 6.699) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[9]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[9]/opit_0_inv/CLK (6.658, 7.105, 6.286, 6.671) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[10]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[10]/opit_0_inv/CLK (6.658, 7.105, 6.286, 6.671) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[11]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[11]/opit_0_inv/CLK (6.658, 7.105, 6.286, 6.671) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[12]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[12]/opit_0_inv/CLK (6.674, 7.122, 6.302, 6.688) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[13]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[13]/opit_0_inv/CLK (6.658, 7.105, 6.286, 6.671) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[14]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[14]/opit_0_inv/CLK (6.685, 7.133, 6.313, 6.699) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[15]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[15]/opit_0_inv/CLK (6.705, 7.152, 6.332, 6.719) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[16]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[16]/opit_0_inv/CLK (6.705, 7.152, 6.332, 6.719) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[17]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[17]/opit_0_inv/CLK (6.705, 7.152, 6.332, 6.719) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[18]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) @@ -93782,34 +93534,34 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[20]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[21]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[21]/opit_0_inv/CLK (6.686, 7.134, 6.314, 6.700) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[22]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[22]/opit_0_inv/CLK (6.674, 7.122, 6.302, 6.688) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[23]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[24]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[24]/opit_0_inv/CLK (6.674, 7.122, 6.302, 6.688) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[25]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[25]/opit_0_inv/CLK (6.658, 7.105, 6.286, 6.671) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[26]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[26]/opit_0_inv/CLK (6.674, 7.122, 6.302, 6.688) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[27]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[27]/opit_0_inv/CLK (6.685, 7.133, 6.313, 6.699) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[28]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[28]/opit_0_inv/CLK (6.705, 7.152, 6.332, 6.719) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[29]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[29]/opit_0_inv/CLK (6.686, 7.134, 6.314, 6.700) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[30]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[30]/opit_0_inv/CLK (6.686, 7.134, 6.314, 6.700) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[31]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) @@ -93818,7 +93570,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[32]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[33]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[33]/opit_0_inv/CLK (6.686, 7.134, 6.314, 6.700) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[34]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) @@ -93845,10 +93597,10 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[42]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/poll/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/poll/opit_0_inv_L5Q_perm/CLK (6.701, 7.149, 6.329, 6.715) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/rd_poll/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/rd_poll/opit_0_inv_L5Q_perm/CLK (6.701, 7.149, 6.329, 6.715) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/rd_poll_d/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) @@ -93863,10 +93615,10 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[4]/opit_0_inv_L5Q_perm/CLK (6.709, 7.157, 6.337, 6.723) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[5]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[5]/opit_0_inv_L5Q_perm/CLK (6.689, 7.137, 6.317, 6.703) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[6]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -93875,34 +93627,34 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[7]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[8]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[8]/opit_0_inv_L5Q_perm/CLK (6.700, 7.148, 6.328, 6.714) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[9]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[9]/opit_0_inv_L5Q_perm/CLK (6.670, 7.117, 6.298, 6.683) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[10]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[10]/opit_0_inv_L5Q_perm/CLK (6.670, 7.117, 6.298, 6.683) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[11]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[11]/opit_0_inv_L5Q_perm/CLK (6.670, 7.117, 6.298, 6.683) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[12]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[12]/opit_0_inv_L5Q_perm/CLK (6.667, 7.114, 6.294, 6.680) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[13]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[13]/opit_0_inv_L5Q_perm/CLK (6.670, 7.117, 6.298, 6.683) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[14]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[14]/opit_0_inv_L5Q_perm/CLK (6.682, 7.129, 6.310, 6.696) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[15]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[15]/opit_0_inv_L5Q_perm/CLK (6.700, 7.148, 6.328, 6.714) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[16]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[16]/opit_0_inv_L5Q_perm/CLK (6.700, 7.148, 6.328, 6.714) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[17]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[17]/opit_0_inv_L5Q_perm/CLK (6.700, 7.148, 6.328, 6.714) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[18]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -93917,31 +93669,31 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[21]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[22]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[22]/opit_0_inv_L5Q_perm/CLK (6.667, 7.114, 6.294, 6.680) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[23]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[24]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[24]/opit_0_inv_L5Q_perm/CLK (6.667, 7.114, 6.294, 6.680) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[25]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[25]/opit_0_inv_L5Q_perm/CLK (6.667, 7.114, 6.294, 6.680) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[26]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[27]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[27]/opit_0_inv_L5Q_perm/CLK (6.682, 7.129, 6.310, 6.696) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[28]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[28]/opit_0_inv_L5Q_perm/CLK (6.682, 7.129, 6.310, 6.696) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[29]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[30]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[30]/opit_0_inv_L5Q_perm/CLK (6.682, 7.129, 6.310, 6.696) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[31]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -93950,7 +93702,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[32]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[33]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[33]/opit_0_inv_L5Q_perm/CLK (6.709, 7.157, 6.337, 6.723) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[34]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -93962,7 +93714,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[36]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[38]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[38]/opit_0_inv_L5Q_perm/CLK (6.709, 7.157, 6.337, 6.723) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[39]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -93977,7 +93729,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[42]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_valid/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_valid/opit_0_inv_L5Q_perm/CLK (6.709, 7.157, 6.337, 6.723) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -93992,16 +93744,16 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[4]/opit_0_inv_L5Q_perm/CLK (6.686, 7.134, 6.314, 6.700) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[5]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[6]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[6]/opit_0_inv_L5Q_perm/CLK (6.686, 7.134, 6.314, 6.700) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[7]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[7]/opit_0_inv_L5Q_perm/CLK (6.686, 7.134, 6.314, 6.700) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[8]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -94037,22 +93789,22 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[4]/opit_0_inv_L5Q_perm/CLK (6.682, 7.129, 6.310, 6.696) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[5]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[5]/opit_0_inv_L5Q_perm/CLK (6.686, 7.134, 6.314, 6.700) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[6]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[6]/opit_0_inv_L5Q_perm/CLK (6.682, 7.129, 6.310, 6.696) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[7]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[7]/opit_0_inv_L5Q_perm/CLK (6.694, 7.141, 6.321, 6.708) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[8]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[9]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[9]/opit_0_inv_L5Q_perm/CLK (6.689, 7.137, 6.317, 6.703) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_l[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -94226,10 +93978,10 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[20]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[21]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[21]/opit_0_inv_L5Q_perm/CLK (6.686, 7.134, 6.314, 6.700) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[22]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[22]/opit_0_inv_L5Q_perm/CLK (6.686, 7.134, 6.314, 6.700) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[23]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -94349,22 +94101,22 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[18]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[19]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[19]/opit_0_inv/CLK (6.669, 7.116, 6.297, 6.682) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[20]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[21]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[21]/opit_0_inv/CLK (6.694, 7.141, 6.321, 6.708) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[22]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[22]/opit_0_inv/CLK (6.694, 7.141, 6.321, 6.708) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[23]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[24]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[24]/opit_0_inv/CLK (6.682, 7.129, 6.310, 6.696) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[25]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) @@ -94487,55 +94239,55 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/rd_data_ff1[3]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/double_wr/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/double_wr/opit_0_inv_L5Q_perm/CLK (6.670, 7.117, 6.298, 6.683) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[0]/opit_0_inv_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[4]/opit_0_inv_L5Q_perm/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[5]/opit_0_inv_L5Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[5]/opit_0_inv_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[6]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[6]/opit_0_inv_L5Q_perm/CLK (6.678, 7.125, 6.305, 6.691) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[7]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[7]/opit_0_inv_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[8]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[8]/opit_0_inv_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[9]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[9]/opit_0_inv_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[10]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[10]/opit_0_inv_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[11]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[11]/opit_0_inv_L5Q_perm/CLK (6.694, 7.141, 6.321, 6.708) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[12]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[12]/opit_0_inv_L5Q_perm/CLK (6.694, 7.141, 6.321, 6.708) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[13]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[13]/opit_0_inv_L5Q_perm/CLK (6.694, 7.141, 6.321, 6.708) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[14]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[14]/opit_0_inv_L5Q_perm/CLK (6.694, 7.141, 6.321, 6.708) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[15]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[15]/opit_0_inv_L5Q_perm/CLK (6.685, 7.133, 6.313, 6.699) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[16]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[16]/opit_0_inv_L5Q_perm/CLK (6.685, 7.133, 6.313, 6.699) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[17]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[17]/opit_0_inv_L5Q_perm/CLK (6.685, 7.133, 6.313, 6.699) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[18]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[18]/opit_0_inv_L5Q_perm/CLK (6.697, 7.145, 6.325, 6.711) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[19]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -94544,187 +94296,187 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[20]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[21]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[21]/opit_0_inv_L5Q_perm/CLK (6.697, 7.145, 6.325, 6.711) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[22]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[22]/opit_0_inv_L5Q_perm/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[23]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[23]/opit_0_inv_L5Q_perm/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[24]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[24]/opit_0_inv_L5Q_perm/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[25]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[25]/opit_0_inv_L5Q_perm/CLK (6.685, 7.133, 6.313, 6.699) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[26]/opit_0_inv_L5Q_perm/CLK (6.693, 7.140, 6.320, 6.707) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[26]/opit_0_inv_L5Q_perm/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[27]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[27]/opit_0_inv_L5Q_perm/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[28]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[28]/opit_0_inv_L5Q_perm/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[29]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[29]/opit_0_inv_L5Q_perm/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[30]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[30]/opit_0_inv_L5Q_perm/CLK (6.685, 7.133, 6.313, 6.699) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[31]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[31]/opit_0_inv_L5Q_perm/CLK (6.685, 7.133, 6.313, 6.699) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[32]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[32]/opit_0_inv_L5Q_perm/CLK (6.697, 7.145, 6.325, 6.711) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[33]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[33]/opit_0_inv_L5Q_perm/CLK (6.697, 7.145, 6.325, 6.711) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[34]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[34]/opit_0_inv_L5Q_perm/CLK (6.685, 7.133, 6.313, 6.699) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[35]/opit_0_inv_L5Q_perm/CLK (6.693, 7.140, 6.320, 6.707) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[35]/opit_0_inv_L5Q_perm/CLK (6.685, 7.133, 6.313, 6.699) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[37]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[37]/opit_0_inv/CLK (6.673, 7.120, 6.301, 6.687) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[0]/opit_0_inv_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[4]/opit_0_inv_L5Q_perm/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[5]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[5]/opit_0_inv_L5Q_perm/CLK (6.678, 7.125, 6.305, 6.691) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[6]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[6]/opit_0_inv_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[7]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[7]/opit_0_inv_L5Q_perm/CLK (6.678, 7.125, 6.305, 6.691) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[8]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[8]/opit_0_inv_L5Q_perm/CLK (6.678, 7.125, 6.305, 6.691) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[9]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[9]/opit_0_inv_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[10]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[10]/opit_0_inv_L5Q_perm/CLK (6.678, 7.125, 6.305, 6.691) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[11]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[11]/opit_0_inv_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[12]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[12]/opit_0_inv_L5Q_perm/CLK (6.689, 7.137, 6.317, 6.703) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[13]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[13]/opit_0_inv_L5Q_perm/CLK (6.686, 7.134, 6.314, 6.700) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[14]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[14]/opit_0_inv_L5Q_perm/CLK (6.686, 7.134, 6.314, 6.700) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[15]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[15]/opit_0_inv_L5Q_perm/CLK (6.689, 7.137, 6.317, 6.703) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[16]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[16]/opit_0_inv_L5Q_perm/CLK (6.693, 7.140, 6.320, 6.707) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[17]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[17]/opit_0_inv_L5Q_perm/CLK (6.689, 7.137, 6.317, 6.703) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[18]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[18]/opit_0_inv_L5Q_perm/CLK (6.693, 7.140, 6.320, 6.707) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[19]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[19]/opit_0_inv_L5Q_perm/CLK (6.693, 7.140, 6.320, 6.707) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[20]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[20]/opit_0_inv_L5Q_perm/CLK (6.693, 7.140, 6.320, 6.707) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[21]/opit_0_inv_L5Q_perm/CLK (6.701, 7.149, 6.329, 6.715) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[21]/opit_0_inv_L5Q_perm/CLK (6.693, 7.140, 6.320, 6.707) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[22]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[22]/opit_0_inv_L5Q_perm/CLK (6.693, 7.140, 6.320, 6.707) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[23]/opit_0_inv_L5Q_perm/CLK (6.701, 7.149, 6.329, 6.715) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[23]/opit_0_inv_L5Q_perm/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[24]/opit_0_inv_L5Q_perm/CLK (6.689, 7.137, 6.317, 6.703) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[24]/opit_0_inv_L5Q_perm/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[25]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[25]/opit_0_inv_L5Q_perm/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[26]/opit_0_inv_L5Q_perm/CLK (6.701, 7.149, 6.329, 6.715) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[26]/opit_0_inv_L5Q_perm/CLK (6.693, 7.140, 6.320, 6.707) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[27]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[27]/opit_0_inv_L5Q_perm/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[28]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[28]/opit_0_inv_L5Q_perm/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[29]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[29]/opit_0_inv_L5Q_perm/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[30]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[30]/opit_0_inv_L5Q_perm/CLK (6.689, 7.137, 6.317, 6.703) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[31]/opit_0_inv_L5Q_perm/CLK (6.689, 7.137, 6.317, 6.703) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[31]/opit_0_inv_L5Q_perm/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[32]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[32]/opit_0_inv_L5Q_perm/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[33]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[33]/opit_0_inv_L5Q_perm/CLK (6.693, 7.140, 6.320, 6.707) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[34]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[34]/opit_0_inv_L5Q_perm/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[35]/opit_0_inv_L5Q_perm/CLK (6.689, 7.137, 6.317, 6.703) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[35]/opit_0_inv_L5Q_perm/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[37]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[37]/opit_0_inv_L5Q_perm/CLK (6.677, 7.124, 6.304, 6.690) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_valid_0/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_valid_0/opit_0_inv_L5Q_perm/CLK (6.682, 7.129, 6.310, 6.696) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_valid_1/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_valid_1/opit_0_inv_L5Q_perm/CLK (6.682, 7.129, 6.310, 6.696) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/rptr/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/rptr/opit_0_inv_L5Q_perm/CLK (6.681, 7.128, 6.309, 6.694) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/next_len[0]/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/next_len[0]/opit_0_inv_MUX4TO1Q/CLK (6.679, 7.126, 6.306, 6.692) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/next_len[1]/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/next_len[1]/opit_0_inv_MUX4TO1Q/CLK (6.679, 7.126, 6.306, 6.692) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/next_len[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/next_len[2]/opit_0_inv_L5Q_perm/CLK (6.679, 7.126, 6.306, 6.692) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/next_len[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/next_len[3]/opit_0_inv_L5Q_perm/CLK (6.679, 7.126, 6.306, 6.692) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][0]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][0]/opit_0_inv/CLK (6.694, 7.141, 6.321, 6.708) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][1]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][1]/opit_0_inv/CLK (6.694, 7.141, 6.321, 6.708) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][2]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][2]/opit_0_inv/CLK (6.674, 7.122, 6.302, 6.688) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][3]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][3]/opit_0_inv/CLK (6.694, 7.141, 6.321, 6.708) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][4]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) @@ -94733,394 +94485,394 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][5]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][6]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][6]/opit_0_inv/CLK (6.694, 7.141, 6.321, 6.708) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][7]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][7]/opit_0_inv/CLK (6.694, 7.141, 6.321, 6.708) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][8]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][8]/opit_0_inv/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][9]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][9]/opit_0_inv/CLK (6.661, 7.108, 6.289, 6.675) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][10]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][10]/opit_0_inv/CLK (6.661, 7.108, 6.289, 6.675) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][11]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][11]/opit_0_inv/CLK (6.661, 7.108, 6.289, 6.675) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][12]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][13]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][13]/opit_0_inv/CLK (6.661, 7.108, 6.289, 6.675) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][14]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][14]/opit_0_inv/CLK (6.694, 7.141, 6.321, 6.708) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][0]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][0]/opit_0_inv/CLK (6.701, 7.149, 6.329, 6.715) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][1]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][1]/opit_0_inv/CLK (6.701, 7.149, 6.329, 6.715) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][2]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][2]/opit_0_inv/CLK (6.670, 7.117, 6.298, 6.683) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][3]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][3]/opit_0_inv/CLK (6.670, 7.117, 6.298, 6.683) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][4]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][4]/opit_0_inv/CLK (6.662, 7.109, 6.290, 6.676) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][5]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][5]/opit_0_inv/CLK (6.670, 7.117, 6.298, 6.683) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][6]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][6]/opit_0_inv/CLK (6.681, 7.128, 6.309, 6.694) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][7]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][7]/opit_0_inv/CLK (6.681, 7.128, 6.309, 6.694) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][8]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][8]/opit_0_inv/CLK (6.662, 7.109, 6.290, 6.676) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][9]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][9]/opit_0_inv/CLK (6.681, 7.128, 6.309, 6.694) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][10]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][10]/opit_0_inv/CLK (6.681, 7.128, 6.309, 6.694) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][11]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][11]/opit_0_inv/CLK (6.681, 7.128, 6.309, 6.694) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][12]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][12]/opit_0_inv/CLK (6.662, 7.109, 6.290, 6.676) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][13]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][13]/opit_0_inv/CLK (6.681, 7.128, 6.309, 6.694) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][14]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][14]/opit_0_inv/CLK (6.701, 7.149, 6.329, 6.715) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][0]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][0]/opit_0_inv/CLK (6.679, 7.126, 6.306, 6.692) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][1]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][1]/opit_0_inv/CLK (6.684, 7.131, 6.312, 6.698) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][2]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][2]/opit_0_inv/CLK (6.679, 7.126, 6.306, 6.692) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][3]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][3]/opit_0_inv/CLK (6.679, 7.126, 6.306, 6.692) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][4]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][4]/opit_0_inv/CLK (6.685, 7.133, 6.313, 6.699) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][5]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][5]/opit_0_inv/CLK (6.679, 7.126, 6.306, 6.692) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][6]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][6]/opit_0_inv/CLK (6.684, 7.131, 6.312, 6.698) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][7]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][7]/opit_0_inv/CLK (6.684, 7.131, 6.312, 6.698) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][8]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][8]/opit_0_inv/CLK (6.685, 7.133, 6.313, 6.699) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][9]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][9]/opit_0_inv/CLK (6.684, 7.131, 6.312, 6.698) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][10]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][10]/opit_0_inv/CLK (6.685, 7.133, 6.313, 6.699) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][11]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][11]/opit_0_inv/CLK (6.685, 7.133, 6.313, 6.699) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][12]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][12]/opit_0_inv/CLK (6.661, 7.108, 6.289, 6.675) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][13]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][13]/opit_0_inv/CLK (6.684, 7.131, 6.312, 6.698) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][14]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][14]/opit_0_inv/CLK (6.679, 7.126, 6.306, 6.692) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][0]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][0]/opit_0_inv/CLK (6.685, 7.133, 6.313, 6.699) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][1]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][1]/opit_0_inv/CLK (6.685, 7.133, 6.313, 6.699) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][2]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][2]/opit_0_inv/CLK (6.667, 7.114, 6.294, 6.680) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][3]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][3]/opit_0_inv/CLK (6.685, 7.133, 6.313, 6.699) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][4]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][4]/opit_0_inv/CLK (6.670, 7.117, 6.298, 6.683) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][5]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][5]/opit_0_inv/CLK (6.666, 7.113, 6.293, 6.679) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][6]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][6]/opit_0_inv/CLK (6.685, 7.133, 6.313, 6.699) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][7]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][7]/opit_0_inv/CLK (6.684, 7.131, 6.312, 6.698) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][8]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][8]/opit_0_inv/CLK (6.670, 7.117, 6.298, 6.683) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][9]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][9]/opit_0_inv/CLK (6.684, 7.131, 6.312, 6.698) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][10]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][10]/opit_0_inv/CLK (6.670, 7.117, 6.298, 6.683) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][11]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][11]/opit_0_inv/CLK (6.670, 7.117, 6.298, 6.683) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][12]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][12]/opit_0_inv/CLK (6.666, 7.113, 6.293, 6.679) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][13]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][13]/opit_0_inv/CLK (6.670, 7.117, 6.298, 6.683) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][14]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][14]/opit_0_inv/CLK (6.685, 7.133, 6.313, 6.699) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][0]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][0]/opit_0_inv/CLK (6.697, 7.145, 6.325, 6.711) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][1]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][1]/opit_0_inv/CLK (6.697, 7.145, 6.325, 6.711) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][2]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][2]/opit_0_inv/CLK (6.679, 7.126, 6.306, 6.692) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][3]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][3]/opit_0_inv/CLK (6.679, 7.126, 6.306, 6.692) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][4]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][4]/opit_0_inv/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][5]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][5]/opit_0_inv/CLK (6.666, 7.113, 6.293, 6.679) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][6]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][6]/opit_0_inv/CLK (6.666, 7.113, 6.293, 6.679) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][7]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][7]/opit_0_inv/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][8]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][8]/opit_0_inv/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][9]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][9]/opit_0_inv/CLK (6.666, 7.113, 6.293, 6.679) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][10]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][10]/opit_0_inv/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][11]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][11]/opit_0_inv/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][12]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][12]/opit_0_inv/CLK (6.662, 7.109, 6.290, 6.676) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][13]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][13]/opit_0_inv/CLK (6.666, 7.113, 6.293, 6.679) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][14]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][14]/opit_0_inv/CLK (6.679, 7.126, 6.306, 6.692) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][0]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][0]/opit_0_inv/CLK (6.701, 7.149, 6.329, 6.715) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][1]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][1]/opit_0_inv/CLK (6.701, 7.149, 6.329, 6.715) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][2]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][2]/opit_0_inv/CLK (6.658, 7.105, 6.286, 6.671) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][3]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][3]/opit_0_inv/CLK (6.701, 7.149, 6.329, 6.715) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][4]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][4]/opit_0_inv/CLK (6.681, 7.128, 6.309, 6.694) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][5]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][5]/opit_0_inv/CLK (6.658, 7.105, 6.286, 6.671) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][6]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][6]/opit_0_inv/CLK (6.681, 7.128, 6.309, 6.694) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][7]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][7]/opit_0_inv/CLK (6.681, 7.128, 6.309, 6.694) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][8]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][8]/opit_0_inv/CLK (6.693, 7.140, 6.320, 6.707) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][9]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][9]/opit_0_inv/CLK (6.681, 7.128, 6.309, 6.694) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][10]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][10]/opit_0_inv/CLK (6.681, 7.128, 6.309, 6.694) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][11]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][11]/opit_0_inv/CLK (6.681, 7.128, 6.309, 6.694) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][12]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][12]/opit_0_inv/CLK (6.658, 7.105, 6.286, 6.671) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][13]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][13]/opit_0_inv/CLK (6.658, 7.105, 6.286, 6.671) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][14]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][14]/opit_0_inv/CLK (6.701, 7.149, 6.329, 6.715) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][0]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][0]/opit_0_inv/CLK (6.685, 7.133, 6.313, 6.699) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][1]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][1]/opit_0_inv/CLK (6.685, 7.133, 6.313, 6.699) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][2]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][2]/opit_0_inv/CLK (6.685, 7.133, 6.313, 6.699) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][3]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][3]/opit_0_inv/CLK (6.685, 7.133, 6.313, 6.699) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][4]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][4]/opit_0_inv/CLK (6.666, 7.113, 6.293, 6.679) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][5]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][5]/opit_0_inv/CLK (6.685, 7.133, 6.313, 6.699) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][6]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][6]/opit_0_inv/CLK (6.681, 7.128, 6.309, 6.694) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][7]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][7]/opit_0_inv/CLK (6.681, 7.128, 6.309, 6.694) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][8]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][8]/opit_0_inv/CLK (6.681, 7.128, 6.309, 6.694) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][9]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][9]/opit_0_inv/CLK (6.681, 7.128, 6.309, 6.694) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][10]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][10]/opit_0_inv/CLK (6.666, 7.113, 6.293, 6.679) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][11]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][11]/opit_0_inv/CLK (6.666, 7.113, 6.293, 6.679) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][12]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][12]/opit_0_inv/CLK (6.666, 7.113, 6.293, 6.679) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][13]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][13]/opit_0_inv/CLK (6.666, 7.113, 6.293, 6.679) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][14]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][14]/opit_0_inv/CLK (6.685, 7.133, 6.313, 6.699) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][0]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][0]/opit_0_inv/CLK (6.689, 7.137, 6.317, 6.703) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][1]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][1]/opit_0_inv/CLK (6.693, 7.140, 6.320, 6.707) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][2]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][2]/opit_0_inv/CLK (6.689, 7.137, 6.317, 6.703) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][3]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][3]/opit_0_inv/CLK (6.689, 7.137, 6.317, 6.703) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][4]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][4]/opit_0_inv/CLK (6.674, 7.122, 6.302, 6.688) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][5]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][5]/opit_0_inv/CLK (6.661, 7.108, 6.289, 6.675) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][6]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][6]/opit_0_inv/CLK (6.693, 7.140, 6.320, 6.707) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][7]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][7]/opit_0_inv/CLK (6.661, 7.108, 6.289, 6.675) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][8]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][8]/opit_0_inv/CLK (6.689, 7.137, 6.317, 6.703) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][9]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][9]/opit_0_inv/CLK (6.661, 7.108, 6.289, 6.675) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][10]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][10]/opit_0_inv/CLK (6.661, 7.108, 6.289, 6.675) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][11]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][11]/opit_0_inv/CLK (6.661, 7.108, 6.289, 6.675) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][12]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][12]/opit_0_inv/CLK (6.661, 7.108, 6.289, 6.675) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][13]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][13]/opit_0_inv/CLK (6.661, 7.108, 6.289, 6.675) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][14]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][14]/opit_0_inv/CLK (6.689, 7.137, 6.317, 6.703) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[0]/opit_0_inv_L5Q_perm/CLK (6.658, 7.105, 6.286, 6.671) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[1]/opit_0_inv_L5Q_perm/CLK (6.679, 7.126, 6.306, 6.692) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[2]/opit_0_inv_L5Q_perm/CLK (6.658, 7.105, 6.286, 6.671) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[3]/opit_0_inv_L5Q_perm/CLK (6.679, 7.126, 6.306, 6.692) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[4]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[4]/opit_0_inv_L5Q_perm/CLK (6.671, 7.118, 6.299, 6.685) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[5]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[5]/opit_0_inv_L5Q_perm/CLK (6.671, 7.118, 6.299, 6.685) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[6]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[6]/opit_0_inv_L5Q_perm/CLK (6.671, 7.118, 6.299, 6.685) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[7]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[7]/opit_0_inv_L5Q_perm/CLK (6.671, 7.118, 6.299, 6.685) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[8]/opit_0_inv_A2Q1/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[8]/opit_0_inv_A2Q1/CLK (6.667, 7.114, 6.294, 6.680) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[10]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[10]/opit_0_inv_A2Q21/CLK (6.667, 7.114, 6.294, 6.680) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[12]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[12]/opit_0_inv_A2Q21/CLK (6.671, 7.118, 6.299, 6.685) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[14]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[14]/opit_0_inv_A2Q21/CLK (6.671, 7.118, 6.299, 6.685) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[16]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[16]/opit_0_inv_A2Q21/CLK (6.662, 7.109, 6.290, 6.676) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[18]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[18]/opit_0_inv_A2Q21/CLK (6.662, 7.109, 6.290, 6.676) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[20]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[20]/opit_0_inv_A2Q21/CLK (6.658, 7.105, 6.286, 6.671) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[22]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[22]/opit_0_inv_A2Q21/CLK (6.658, 7.105, 6.286, 6.671) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[24]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) @@ -95129,370 +94881,370 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[26]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[27]/opit_0_inv_AQ_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[27]/opit_0_inv_AQ/CLK (6.658, 7.105, 6.286, 6.671) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_data_in_valid/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_data_in_valid/opit_0_inv_L5Q_perm/CLK (6.682, 7.129, 6.310, 6.696) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_id[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_id[0]/opit_0_inv_L5Q_perm/CLK (6.681, 7.128, 6.309, 6.694) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_id[1]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_id[1]/opit_0_inv_L5Q_perm/CLK (6.681, 7.128, 6.309, 6.694) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_id[2]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_id[2]/opit_0_inv_L5Q_perm/CLK (6.681, 7.128, 6.309, 6.694) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_id[3]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_id[3]/opit_0_inv_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_len[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_len[0]/opit_0_inv_MUX4TO1Q/CLK (6.670, 7.117, 6.298, 6.683) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_len[1]/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_len[1]/opit_0_inv_MUX4TO1Q/CLK (6.670, 7.117, 6.298, 6.683) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_len[2]/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_len[2]/opit_0_inv_L5Q_perm/CLK (6.679, 7.126, 6.306, 6.692) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_len[3]/opit_0_inv_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_len[3]/opit_0_inv_MUX4TO1Q/CLK (6.679, 7.126, 6.306, 6.692) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_write/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_write/opit_0_inv_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/ptr/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/ptr/opit_0_inv_L5Q_perm/CLK (6.681, 7.128, 6.309, 6.694) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[0]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[0]/opit_0_inv/CLK (6.705, 7.152, 6.332, 6.719) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[1]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[1]/opit_0_inv/CLK (6.693, 7.140, 6.320, 6.707) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[2]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[2]/opit_0_inv/CLK (6.694, 7.141, 6.321, 6.708) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[3]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[3]/opit_0_inv/CLK (6.670, 7.117, 6.298, 6.683) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[4]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[4]/opit_0_inv/CLK (6.670, 7.117, 6.298, 6.683) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[5]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[5]/opit_0_inv/CLK (6.670, 7.117, 6.298, 6.683) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[6]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[6]/opit_0_inv/CLK (6.658, 7.105, 6.286, 6.671) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[7]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[7]/opit_0_inv/CLK (6.658, 7.105, 6.286, 6.671) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[8]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[8]/opit_0_inv/CLK (6.670, 7.117, 6.298, 6.683) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[9]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[9]/opit_0_inv/CLK (6.670, 7.117, 6.298, 6.683) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[10]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[10]/opit_0_inv/CLK (6.670, 7.117, 6.298, 6.683) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[11]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[11]/opit_0_inv/CLK (6.693, 7.140, 6.320, 6.707) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[12]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[12]/opit_0_inv/CLK (6.693, 7.140, 6.320, 6.707) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[13]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[13]/opit_0_inv/CLK (6.678, 7.125, 6.305, 6.691) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[14]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[14]/opit_0_inv/CLK (6.686, 7.134, 6.314, 6.700) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[15]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[15]/opit_0_inv/CLK (6.681, 7.128, 6.309, 6.694) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[16]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[16]/opit_0_inv/CLK (6.693, 7.140, 6.320, 6.707) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[17]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[17]/opit_0_inv/CLK (6.692, 7.139, 6.319, 6.705) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[18]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[18]/opit_0_inv/CLK (6.694, 7.141, 6.321, 6.708) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[19]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[19]/opit_0_inv/CLK (6.694, 7.141, 6.321, 6.708) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[20]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[20]/opit_0_inv/CLK (6.705, 7.152, 6.332, 6.719) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[21]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[21]/opit_0_inv/CLK (6.692, 7.139, 6.319, 6.705) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[22]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[22]/opit_0_inv/CLK (6.692, 7.139, 6.319, 6.705) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[23]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[23]/opit_0_inv/CLK (6.666, 7.113, 6.293, 6.679) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[24]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[24]/opit_0_inv/CLK (6.681, 7.128, 6.309, 6.694) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[25]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[25]/opit_0_inv/CLK (6.666, 7.113, 6.293, 6.679) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[26]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[26]/opit_0_inv/CLK (6.666, 7.113, 6.293, 6.679) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[27]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[27]/opit_0_inv/CLK (6.693, 7.140, 6.320, 6.707) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[28]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[28]/opit_0_inv/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[29]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[29]/opit_0_inv/CLK (6.693, 7.140, 6.320, 6.707) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[30]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[30]/opit_0_inv/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[31]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[31]/opit_0_inv/CLK (6.666, 7.113, 6.293, 6.679) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[32]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[32]/opit_0_inv/CLK (6.693, 7.140, 6.320, 6.707) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[33]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[33]/opit_0_inv/CLK (6.670, 7.117, 6.298, 6.683) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[34]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[34]/opit_0_inv/CLK (6.681, 7.128, 6.309, 6.694) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[35]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[35]/opit_0_inv/CLK (6.692, 7.139, 6.319, 6.705) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[37]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[37]/opit_0_inv/CLK (6.670, 7.117, 6.298, 6.683) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[39]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[39]/opit_0_inv_L5Q_perm/CLK (6.693, 7.140, 6.320, 6.707) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[40]/opit_0_inv_MUX8TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[40]/opit_0_inv_MUX8TO1Q/CLK (6.681, 7.128, 6.309, 6.694) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[41]/opit_0_inv_MUX8TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[41]/opit_0_inv_MUX8TO1Q/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[42]/opit_0_inv_MUX8TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[42]/opit_0_inv_MUX8TO1Q/CLK (6.666, 7.113, 6.293, 6.679) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[43]/opit_0_inv_MUX8TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[43]/opit_0_inv_MUX8TO1Q/CLK (6.694, 7.141, 6.321, 6.708) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[44]/opit_0_inv_MUX8TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[44]/opit_0_inv_MUX8TO1Q/CLK (6.658, 7.105, 6.286, 6.671) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[45]/opit_0_inv_MUX8TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[45]/opit_0_inv_MUX8TO1Q/CLK (6.666, 7.113, 6.293, 6.679) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[46]/opit_0_inv_MUX8TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[46]/opit_0_inv_MUX8TO1Q/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[47]/opit_0_inv_MUX8TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[47]/opit_0_inv_MUX8TO1Q/CLK (6.692, 7.139, 6.319, 6.705) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[48]/opit_0_inv_MUX8TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[48]/opit_0_inv_MUX8TO1Q/CLK (6.693, 7.140, 6.320, 6.707) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[49]/opit_0_inv_MUX8TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[49]/opit_0_inv_MUX8TO1Q/CLK (6.681, 7.128, 6.309, 6.694) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[50]/opit_0_inv_MUX8TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[50]/opit_0_inv_MUX8TO1Q/CLK (6.666, 7.113, 6.293, 6.679) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[51]/opit_0_inv_MUX8TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[51]/opit_0_inv_MUX8TO1Q/CLK (6.693, 7.140, 6.320, 6.707) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[52]/opit_0_inv_MUX8TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[52]/opit_0_inv_MUX8TO1Q/CLK (6.658, 7.105, 6.286, 6.671) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[53]/opit_0_inv_MUX8TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[53]/opit_0_inv_MUX8TO1Q/CLK (6.666, 7.113, 6.293, 6.679) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[54]/opit_0_inv_MUX8TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[54]/opit_0_inv_MUX8TO1Q/CLK (6.694, 7.141, 6.321, 6.708) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[0]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[0]/opit_0_inv/CLK (6.709, 7.157, 6.337, 6.723) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[1]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[1]/opit_0_inv/CLK (6.709, 7.157, 6.337, 6.723) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[2]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[2]/opit_0_inv/CLK (6.670, 7.117, 6.298, 6.683) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[3]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[3]/opit_0_inv/CLK (6.670, 7.117, 6.298, 6.683) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[4]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[4]/opit_0_inv/CLK (6.666, 7.113, 6.293, 6.679) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[5]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[5]/opit_0_inv/CLK (6.667, 7.114, 6.294, 6.680) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[6]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[6]/opit_0_inv/CLK (6.667, 7.114, 6.294, 6.680) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[7]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[7]/opit_0_inv/CLK (6.667, 7.114, 6.294, 6.680) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[8]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[8]/opit_0_inv/CLK (6.674, 7.122, 6.302, 6.688) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[9]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[9]/opit_0_inv/CLK (6.674, 7.122, 6.302, 6.688) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[10]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[10]/opit_0_inv/CLK (6.674, 7.122, 6.302, 6.688) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[11]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[11]/opit_0_inv/CLK (6.681, 7.128, 6.309, 6.694) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[12]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[12]/opit_0_inv/CLK (6.709, 7.157, 6.337, 6.723) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[13]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[13]/opit_0_inv/CLK (6.678, 7.125, 6.305, 6.691) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[14]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[14]/opit_0_inv/CLK (6.662, 7.109, 6.290, 6.676) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[15]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[15]/opit_0_inv/CLK (6.678, 7.125, 6.305, 6.691) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[16]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[16]/opit_0_inv/CLK (6.709, 7.157, 6.337, 6.723) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[17]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[17]/opit_0_inv/CLK (6.677, 7.124, 6.304, 6.690) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[18]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[18]/opit_0_inv/CLK (6.685, 7.133, 6.313, 6.699) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[19]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[19]/opit_0_inv/CLK (6.685, 7.133, 6.313, 6.699) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[20]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[20]/opit_0_inv/CLK (6.709, 7.157, 6.337, 6.723) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[21]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[21]/opit_0_inv/CLK (6.696, 7.144, 6.324, 6.710) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[22]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[22]/opit_0_inv/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[23]/opit_0_inv/CLK (6.694, 7.141, 6.321, 6.708) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[23]/opit_0_inv/CLK (6.670, 7.117, 6.298, 6.683) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[24]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[24]/opit_0_inv/CLK (6.696, 7.144, 6.324, 6.710) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[25]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[25]/opit_0_inv/CLK (6.667, 7.114, 6.294, 6.680) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[26]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[26]/opit_0_inv/CLK (6.666, 7.113, 6.293, 6.679) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[27]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[27]/opit_0_inv/CLK (6.681, 7.128, 6.309, 6.694) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[28]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[28]/opit_0_inv/CLK (6.677, 7.124, 6.304, 6.690) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[29]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[29]/opit_0_inv/CLK (6.694, 7.141, 6.321, 6.708) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[30]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[30]/opit_0_inv/CLK (6.696, 7.144, 6.324, 6.710) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[31]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[31]/opit_0_inv/CLK (6.679, 7.126, 6.306, 6.692) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[32]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[32]/opit_0_inv/CLK (6.694, 7.141, 6.321, 6.708) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[33]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[33]/opit_0_inv/CLK (6.667, 7.114, 6.294, 6.680) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[34]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[34]/opit_0_inv/CLK (6.696, 7.144, 6.324, 6.710) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[35]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[35]/opit_0_inv/CLK (6.681, 7.128, 6.309, 6.694) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[37]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[37]/opit_0_inv/CLK (6.666, 7.113, 6.293, 6.679) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[39]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[39]/opit_0_inv/CLK (6.709, 7.157, 6.337, 6.723) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[40]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[40]/opit_0_inv/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[41]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[41]/opit_0_inv/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[42]/opit_0_inv/CLK (6.694, 7.141, 6.321, 6.708) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[42]/opit_0_inv/CLK (6.670, 7.117, 6.298, 6.683) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[43]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[43]/opit_0_inv/CLK (6.696, 7.144, 6.324, 6.710) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[44]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[44]/opit_0_inv/CLK (6.667, 7.114, 6.294, 6.680) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[45]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[45]/opit_0_inv/CLK (6.666, 7.113, 6.293, 6.679) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[46]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[46]/opit_0_inv/CLK (6.681, 7.128, 6.309, 6.694) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[47]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[47]/opit_0_inv/CLK (6.677, 7.124, 6.304, 6.690) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[48]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[48]/opit_0_inv/CLK (6.694, 7.141, 6.321, 6.708) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[49]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[49]/opit_0_inv/CLK (6.696, 7.144, 6.324, 6.710) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[50]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[50]/opit_0_inv/CLK (6.679, 7.126, 6.306, 6.692) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[51]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[51]/opit_0_inv/CLK (6.694, 7.141, 6.321, 6.708) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[52]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[52]/opit_0_inv/CLK (6.666, 7.113, 6.293, 6.679) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[53]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[53]/opit_0_inv/CLK (6.666, 7.113, 6.293, 6.679) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[54]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[54]/opit_0_inv/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_valid_0/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_valid_0/opit_0_inv_L5Q_perm/CLK (6.693, 7.140, 6.320, 6.707) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_valid_1/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_valid_1/opit_0_inv_L5Q_perm/CLK (6.693, 7.140, 6.320, 6.707) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr/opit_0_inv_L5Q_perm/CLK (6.701, 7.149, 6.329, 6.715) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/wptr/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/wptr/opit_0_inv_L5Q_perm/CLK (6.666, 7.113, 6.293, 6.679) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/data_out[0]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) @@ -95879,7 +95631,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[175]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[176]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[176]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[177]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) @@ -96281,22 +96033,22 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[47]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[48]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[48]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[49]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[50]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[50]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[51]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[52]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[52]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[53]/opit_0_inv/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[53]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[54]/opit_0_inv/CLK (6.764, 7.213, 6.383, 6.770) @@ -96935,22 +96687,22 @@ u_axi_ddr_top/cnt0_times[8]/opit_0_AQ_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/cnt1_times[0]/opit_0_L5Q_perm/CLK (6.688, 7.136, 6.316, 6.702) + u_axi_ddr_top/cnt1_times[0]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/cnt1_times[1]/opit_0_A2Q1/CLK (6.688, 7.136, 6.316, 6.702) + u_axi_ddr_top/cnt1_times[1]/opit_0_A2Q1/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/cnt1_times[3]/opit_0_A2Q21/CLK (6.688, 7.136, 6.316, 6.702) + u_axi_ddr_top/cnt1_times[3]/opit_0_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/cnt1_times[5]/opit_0_A2Q21/CLK (6.684, 7.131, 6.312, 6.698) + u_axi_ddr_top/cnt1_times[5]/opit_0_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/cnt1_times[7]/opit_0_A2Q21/CLK (6.684, 7.131, 6.312, 6.698) + u_axi_ddr_top/cnt1_times[7]/opit_0_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/cnt1_times[8]/opit_0_AQ_perm/CLK (6.688, 7.136, 6.316, 6.702) + u_axi_ddr_top/cnt1_times[8]/opit_0_AQ_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/cnt_wr_num[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -97076,7 +96828,7 @@ u_axi_ddr_top/rd0_ddr_sart_addr0[28]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/rd0_ddr_sart_addr0[29]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/rd0_ddr_sart_addr0[29]/opit_0/CLK (6.684, 7.131, 6.312, 6.698) u_axi_ddr_top/rd0_ddr_sart_addr1[10]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) @@ -97211,7 +96963,7 @@ u_axi_ddr_top/rd0_time_permit/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/rd1_addr_start_fall/opit_0_L5Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/rd1_addr_start_fall/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/rd1_addr_start_valid0/opit_0/CLK (6.654, 7.101, 6.282, 6.667) @@ -97220,7 +96972,7 @@ u_axi_ddr_top/rd1_addr_start_valid1/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/rd1_cnt_num[0]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/rd1_cnt_num[0]/opit_0_L5Q_perm/CLK (6.701, 7.149, 6.329, 6.715) u_axi_ddr_top/rd1_cnt_num[2]/opit_0_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) @@ -97247,7 +96999,7 @@ u_axi_ddr_top/rd1_cnt_num[15]/opit_0_AQ/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/rd1_ddr_done0/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/rd1_ddr_done0/opit_0_L5Q_perm/CLK (6.684, 7.131, 6.312, 6.698) u_axi_ddr_top/rd1_ddr_done1/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -97406,7 +97158,7 @@ u_axi_ddr_top/rd1_done_cnt[2]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/rd1_time_permit/opit_0_L5Q_perm/CLK (6.684, 7.131, 6.312, 6.698) + u_axi_ddr_top/rd1_time_permit/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/rd3_data_en0/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -97415,7 +97167,7 @@ u_axi_ddr_top/rd3_data_en1/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/rd3_data_en2/opit_0/CLK (6.700, 7.148, 6.328, 6.714) + u_axi_ddr_top/rd3_data_en2/opit_0/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/rd3_ddr_data[0]/opit_0_MUX16TO1Q/CLK (6.654, 7.101, 6.282, 6.667) @@ -97442,28 +97194,28 @@ u_axi_ddr_top/rd3_ddr_data[7]/opit_0_MUX16TO1Q/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/rd3_ddr_data[8]/opit_0_MUX16TO1Q/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/rd3_ddr_data[8]/opit_0_MUX16TO1Q/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/rd3_ddr_data[9]/opit_0_MUX16TO1Q/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/rd3_ddr_data[9]/opit_0_MUX16TO1Q/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/rd3_ddr_data[10]/opit_0_MUX16TO1Q/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/rd3_ddr_data[10]/opit_0_MUX16TO1Q/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/rd3_ddr_data[11]/opit_0_MUX16TO1Q/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/rd3_ddr_data[11]/opit_0_MUX16TO1Q/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/rd3_ddr_data[12]/opit_0_MUX16TO1Q/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/rd3_ddr_data[12]/opit_0_MUX16TO1Q/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/rd3_ddr_data[13]/opit_0_MUX16TO1Q/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/rd3_ddr_data[13]/opit_0_MUX16TO1Q/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/rd3_ddr_data[14]/opit_0_MUX16TO1Q/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/rd3_ddr_data[14]/opit_0_MUX16TO1Q/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/rd3_ddr_data[15]/opit_0_MUX16TO1Q/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/rd3_ddr_data[15]/opit_0_MUX16TO1Q/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/rd_all_full/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -97475,16 +97227,16 @@ u_axi_ddr_top/rd_importance/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/rd_sta0_reg0/opit_0/CLK (6.697, 7.145, 6.325, 6.711) + u_axi_ddr_top/rd_sta0_reg0/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/rd_sta0_reg1/opit_0/CLK (6.688, 7.136, 6.316, 6.702) + u_axi_ddr_top/rd_sta0_reg1/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/rd_sta2_reg0/opit_0/CLK (6.697, 7.145, 6.325, 6.711) + u_axi_ddr_top/rd_sta2_reg0/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/rd_sta2_reg1/opit_0/CLK (6.688, 7.136, 6.316, 6.702) + u_axi_ddr_top/rd_sta2_reg1/opit_0/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/rd_sta_reg[0]/opit_0_L5Q_perm/CLK (6.693, 7.140, 6.320, 6.707) @@ -97502,10 +97254,10 @@ u_axi_ddr_top/rd_sta_reg[4]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/rd_sta_reg[6]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/rd_sta_reg[6]/opit_0_L5Q_perm/CLK (6.693, 7.140, 6.320, 6.707) - u_axi_ddr_top/rd_sta_reg[7]/opit_0_L5Q_perm/CLK (6.682, 7.129, 6.310, 6.696) + u_axi_ddr_top/rd_sta_reg[7]/opit_0_L5Q_perm/CLK (6.693, 7.140, 6.320, 6.707) u_axi_ddr_top/rd_wr_fast_empty/opit_0/CLK (6.654, 7.101, 6.282, 6.667) @@ -97514,10 +97266,10 @@ u_axi_ddr_top/rd_wr_fifo_empty/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/record_addr_valid/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/record_addr_valid/opit_0_L5Q_perm/CLK (6.677, 7.124, 6.304, 6.690) - u_axi_ddr_top/record_araddr_valid/opit_0_L5Q_perm/CLK (6.685, 7.133, 6.313, 6.699) + u_axi_ddr_top/record_araddr_valid/opit_0_L5Q_perm/CLK (6.684, 7.131, 6.312, 6.698) u_axi_ddr_top/record_data_valid/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -97532,28 +97284,28 @@ u_axi_ddr_top/rx_rd1_addr_valid/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_araddr[5]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/s_axi_araddr[5]/opit_0_L5Q_perm/CLK (6.669, 7.116, 6.297, 6.682) - u_axi_ddr_top/s_axi_araddr[6]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/s_axi_araddr[6]/opit_0_L5Q_perm/CLK (6.681, 7.128, 6.309, 6.694) - u_axi_ddr_top/s_axi_araddr[7]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/s_axi_araddr[7]/opit_0_L5Q_perm/CLK (6.669, 7.116, 6.297, 6.682) - u_axi_ddr_top/s_axi_araddr[8]/opit_0_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/s_axi_araddr[8]/opit_0_MUX4TO1Q/CLK (6.697, 7.145, 6.325, 6.711) - u_axi_ddr_top/s_axi_araddr[9]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/s_axi_araddr[9]/opit_0_L5Q_perm/CLK (6.697, 7.145, 6.325, 6.711) - u_axi_ddr_top/s_axi_araddr[10]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/s_axi_araddr[10]/opit_0_L5Q_perm/CLK (6.693, 7.140, 6.320, 6.707) - u_axi_ddr_top/s_axi_araddr[11]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/s_axi_araddr[11]/opit_0_L5Q_perm/CLK (6.697, 7.145, 6.325, 6.711) - u_axi_ddr_top/s_axi_araddr[12]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/s_axi_araddr[12]/opit_0_L5Q_perm/CLK (6.697, 7.145, 6.325, 6.711) u_axi_ddr_top/s_axi_araddr[13]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -97562,37 +97314,37 @@ u_axi_ddr_top/s_axi_araddr[14]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_araddr[15]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/s_axi_araddr[15]/opit_0_L5Q_perm/CLK (6.693, 7.140, 6.320, 6.707) - u_axi_ddr_top/s_axi_araddr[16]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/s_axi_araddr[16]/opit_0_L5Q_perm/CLK (6.693, 7.140, 6.320, 6.707) - u_axi_ddr_top/s_axi_araddr[17]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/s_axi_araddr[17]/opit_0_L5Q_perm/CLK (6.684, 7.131, 6.312, 6.698) - u_axi_ddr_top/s_axi_araddr[18]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/s_axi_araddr[18]/opit_0_L5Q_perm/CLK (6.681, 7.128, 6.309, 6.694) - u_axi_ddr_top/s_axi_araddr[19]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/s_axi_araddr[19]/opit_0_L5Q_perm/CLK (6.693, 7.140, 6.320, 6.707) - u_axi_ddr_top/s_axi_araddr[20]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/s_axi_araddr[20]/opit_0_L5Q_perm/CLK (6.684, 7.131, 6.312, 6.698) - u_axi_ddr_top/s_axi_araddr[21]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/s_axi_araddr[21]/opit_0_L5Q_perm/CLK (6.681, 7.128, 6.309, 6.694) - u_axi_ddr_top/s_axi_araddr[22]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/s_axi_araddr[22]/opit_0_L5Q/CLK (6.684, 7.131, 6.312, 6.698) - u_axi_ddr_top/s_axi_araddr[23]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/s_axi_araddr[23]/opit_0_L5Q_perm/CLK (6.684, 7.131, 6.312, 6.698) - u_axi_ddr_top/s_axi_araddr[24]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/s_axi_araddr[24]/opit_0_L5Q_perm/CLK (6.693, 7.140, 6.320, 6.707) - u_axi_ddr_top/s_axi_araddr[25]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/s_axi_araddr[25]/opit_0_L5Q_perm/CLK (6.693, 7.140, 6.320, 6.707) u_axi_ddr_top/s_axi_araddr[26]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -97601,25 +97353,25 @@ u_axi_ddr_top/s_axi_araddr[27]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_araddr[28]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/s_axi_araddr[28]/opit_0_L5Q_perm/CLK (6.681, 7.128, 6.309, 6.694) - u_axi_ddr_top/s_axi_araddr[29]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/s_axi_araddr[29]/opit_0_L5Q_perm/CLK (6.693, 7.140, 6.320, 6.707) - u_axi_ddr_top/s_axi_arid[0]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/s_axi_arid[0]/opit_0/CLK (6.669, 7.116, 6.297, 6.682) - u_axi_ddr_top/s_axi_arid[1]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/s_axi_arid[1]/opit_0/CLK (6.669, 7.116, 6.297, 6.682) - u_axi_ddr_top/s_axi_arid[2]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/s_axi_arid[2]/opit_0/CLK (6.669, 7.116, 6.297, 6.682) - u_axi_ddr_top/s_axi_arid[3]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/s_axi_arid[3]/opit_0_L5Q_perm/CLK (6.669, 7.116, 6.297, 6.682) - u_axi_ddr_top/s_axi_arlen[0]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/s_axi_arlen[0]/opit_0_L5Q_perm/CLK (6.669, 7.116, 6.297, 6.682) u_axi_ddr_top/s_axi_rdata0[0]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -97646,28 +97398,28 @@ u_axi_ddr_top/s_axi_rdata0[7]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[8]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[8]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[9]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[9]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[10]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[10]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[11]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[11]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[12]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[12]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[13]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[13]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[14]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[14]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[15]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[15]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/s_axi_rdata0[16]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -97694,28 +97446,28 @@ u_axi_ddr_top/s_axi_rdata0[23]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[24]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[24]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[25]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[25]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[26]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[26]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[27]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[27]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[28]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[28]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[29]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[29]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[30]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[30]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[31]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[31]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/s_axi_rdata0[32]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -97838,31 +97590,31 @@ u_axi_ddr_top/s_axi_rdata0[71]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[72]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[72]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[73]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[73]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[74]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[74]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[75]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[75]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[76]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[76]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[77]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[77]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[78]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[78]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[79]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[79]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[80]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/s_axi_rdata0[80]/opit_0_L5Q/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/s_axi_rdata0[81]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -97886,28 +97638,28 @@ u_axi_ddr_top/s_axi_rdata0[87]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[88]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[88]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[89]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[89]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[90]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[90]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[91]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[91]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[92]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[92]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[93]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[93]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[94]/opit_0_L5Q/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[94]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[95]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[95]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/s_axi_rdata0[96]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -97934,7 +97686,7 @@ u_axi_ddr_top/s_axi_rdata0[103]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[104]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[104]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/s_axi_rdata0[105]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -98030,28 +97782,28 @@ u_axi_ddr_top/s_axi_rdata0[135]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[136]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[136]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[137]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[137]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[138]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[138]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[139]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[139]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[140]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[140]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[141]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[141]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[142]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[142]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[143]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[143]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/s_axi_rdata0[144]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -98078,34 +97830,34 @@ u_axi_ddr_top/s_axi_rdata0[151]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[152]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[152]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[153]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[153]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[154]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[154]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[155]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[155]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[156]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[156]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[157]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[157]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[158]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[158]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[159]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[159]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/s_axi_rdata0[160]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[161]/opit_0_L5Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/s_axi_rdata0[161]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/s_axi_rdata0[162]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -98222,28 +97974,28 @@ u_axi_ddr_top/s_axi_rdata0[199]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[200]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[200]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[201]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[201]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[202]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[202]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[203]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[203]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[204]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[204]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[205]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[205]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[206]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[206]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[207]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[207]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/s_axi_rdata0[208]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -98270,28 +98022,28 @@ u_axi_ddr_top/s_axi_rdata0[215]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[216]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[216]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[217]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[217]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[218]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[218]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[219]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[219]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[220]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[220]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[221]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[221]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[222]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[222]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata0[223]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata0[223]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/s_axi_rdata0[224]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -98414,28 +98166,28 @@ u_axi_ddr_top/s_axi_rdata1[7]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[8]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[8]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[9]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[9]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[10]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[10]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[11]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[11]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[12]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[12]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[13]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[13]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[14]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[14]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[15]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[15]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/s_axi_rdata1[16]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) @@ -98462,28 +98214,28 @@ u_axi_ddr_top/s_axi_rdata1[23]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[24]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[24]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[25]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[25]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[26]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[26]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[27]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[27]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[28]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[28]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[29]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[29]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[30]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[30]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[31]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[31]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/s_axi_rdata1[32]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) @@ -98510,28 +98262,28 @@ u_axi_ddr_top/s_axi_rdata1[39]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[40]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[40]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[41]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[41]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[42]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[42]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/s_axi_rdata1[43]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[44]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[44]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[45]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[45]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[46]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[46]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[47]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[47]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/s_axi_rdata1[48]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) @@ -98558,7 +98310,7 @@ u_axi_ddr_top/s_axi_rdata1[55]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[56]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[56]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/s_axi_rdata1[57]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) @@ -98573,10 +98325,10 @@ u_axi_ddr_top/s_axi_rdata1[60]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/s_axi_rdata1[61]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[61]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[62]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[62]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/s_axi_rdata1[63]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) @@ -98606,28 +98358,28 @@ u_axi_ddr_top/s_axi_rdata1[71]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[72]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[72]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[73]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[73]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[74]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[74]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[75]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[75]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[76]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[76]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[77]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[77]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[78]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[78]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[79]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[79]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/s_axi_rdata1[80]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) @@ -98654,28 +98406,28 @@ u_axi_ddr_top/s_axi_rdata1[87]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[88]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[88]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[89]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[89]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[90]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[90]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[91]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[91]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[92]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[92]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[93]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[93]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[94]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[94]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[95]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[95]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/s_axi_rdata1[96]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) @@ -98702,16 +98454,16 @@ u_axi_ddr_top/s_axi_rdata1[103]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[104]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[104]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[105]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[105]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[106]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[106]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[107]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[107]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/s_axi_rdata1[108]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) @@ -98720,10 +98472,10 @@ u_axi_ddr_top/s_axi_rdata1[109]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[110]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[110]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[111]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[111]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/s_axi_rdata1[112]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) @@ -98750,13 +98502,13 @@ u_axi_ddr_top/s_axi_rdata1[119]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[120]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[120]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[121]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[121]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[122]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[122]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/s_axi_rdata1[123]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) @@ -98765,13 +98517,13 @@ u_axi_ddr_top/s_axi_rdata1[124]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/s_axi_rdata1[125]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[125]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[126]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[126]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[127]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[127]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/s_axi_rdata1[128]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) @@ -98798,28 +98550,28 @@ u_axi_ddr_top/s_axi_rdata1[135]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[136]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[136]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[137]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[137]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[138]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[138]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[139]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[139]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[140]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[140]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[141]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[141]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[142]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[142]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[143]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[143]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/s_axi_rdata1[144]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) @@ -98846,28 +98598,28 @@ u_axi_ddr_top/s_axi_rdata1[151]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[152]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[152]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[153]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[153]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[154]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[154]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[155]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[155]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[156]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[156]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[157]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[157]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[158]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[158]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[159]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[159]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/s_axi_rdata1[160]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) @@ -98894,25 +98646,25 @@ u_axi_ddr_top/s_axi_rdata1[167]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[168]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[168]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[169]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[169]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[170]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[170]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[171]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[171]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/s_axi_rdata1[172]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[173]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[173]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[174]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[174]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/s_axi_rdata1[175]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) @@ -98945,25 +98697,25 @@ u_axi_ddr_top/s_axi_rdata1[184]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/s_axi_rdata1[185]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[185]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/s_axi_rdata1[186]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/s_axi_rdata1[187]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[187]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[188]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[188]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[189]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[189]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[190]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[190]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[191]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[191]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/s_axi_rdata1[192]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) @@ -98990,28 +98742,28 @@ u_axi_ddr_top/s_axi_rdata1[199]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[200]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[200]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[201]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[201]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[202]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[202]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[203]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[203]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[204]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[204]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[205]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[205]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[206]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[206]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[207]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[207]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/s_axi_rdata1[208]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) @@ -99038,28 +98790,28 @@ u_axi_ddr_top/s_axi_rdata1[215]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[216]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[216]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[217]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[217]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[218]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[218]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[219]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[219]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[220]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[220]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[221]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[221]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[222]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[222]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[223]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[223]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/s_axi_rdata1[224]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) @@ -99086,13 +98838,13 @@ u_axi_ddr_top/s_axi_rdata1[231]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[232]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[232]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[233]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[233]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[234]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[234]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/s_axi_rdata1[235]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) @@ -99104,7 +98856,7 @@ u_axi_ddr_top/s_axi_rdata1[237]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[238]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[238]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/s_axi_rdata1[239]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) @@ -99143,16 +98895,16 @@ u_axi_ddr_top/s_axi_rdata1[250]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/s_axi_rdata1[251]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[251]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[252]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[252]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[253]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[253]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/s_axi_rdata1[254]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/s_axi_rdata1[254]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/s_axi_rdata1[255]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) @@ -99173,52 +98925,52 @@ u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0_A2Q1/CLK (6.678, 7.125, 6.305, 6.691) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (6.682, 7.129, 6.310, 6.696) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (6.677, 7.124, 6.304, 6.690) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (6.682, 7.129, 6.310, 6.696) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (6.677, 7.124, 6.304, 6.690) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (6.678, 7.125, 6.305, 6.691) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (6.681, 7.128, 6.309, 6.694) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (6.678, 7.125, 6.305, 6.691) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (6.681, 7.128, 6.309, 6.694) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (6.673, 7.120, 6.301, 6.687) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (6.685, 7.133, 6.313, 6.699) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[11]/opit_0_inv_A2Q21/CLK (6.673, 7.120, 6.301, 6.687) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[11]/opit_0_inv_A2Q21/CLK (6.685, 7.133, 6.313, 6.699) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm/CLK (6.686, 7.134, 6.314, 6.700) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm/CLK (6.669, 7.116, 6.297, 6.682) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm/CLK (6.686, 7.134, 6.314, 6.700) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm/CLK (6.669, 7.116, 6.297, 6.682) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/CLK (6.686, 7.134, 6.314, 6.700) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/CLK (6.669, 7.116, 6.297, 6.682) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm/CLK (6.686, 7.134, 6.314, 6.700) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm/CLK (6.669, 7.116, 6.297, 6.682) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm/CLK (6.689, 7.137, 6.317, 6.703) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm/CLK (6.681, 7.128, 6.309, 6.694) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm/CLK (6.689, 7.137, 6.317, 6.703) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm/CLK (6.678, 7.125, 6.305, 6.691) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm/CLK (6.689, 7.137, 6.317, 6.703) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm/CLK (6.681, 7.128, 6.309, 6.694) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm/CLK (6.678, 7.125, 6.305, 6.691) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/CLK (6.678, 7.125, 6.305, 6.691) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/CLK (6.678, 7.125, 6.305, 6.691) u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm/CLK (6.678, 7.125, 6.305, 6.691) @@ -99227,109 +98979,109 @@ u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[11]/opit_0_L5Q_perm/CLK (6.678, 7.125, 6.305, 6.691) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0/CLK (6.686, 7.134, 6.314, 6.700) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0/CLK (6.658, 7.105, 6.286, 6.671) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/opit_0/CLK (6.679, 7.126, 6.306, 6.692) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/opit_0/CLK (6.658, 7.105, 6.286, 6.671) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/opit_0/CLK (6.679, 7.126, 6.306, 6.692) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/opit_0/CLK (6.658, 7.105, 6.286, 6.671) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/opit_0/CLK (6.686, 7.134, 6.314, 6.700) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/opit_0/CLK (6.658, 7.105, 6.286, 6.671) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/opit_0/CLK (6.674, 7.122, 6.302, 6.688) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/opit_0/CLK (6.658, 7.105, 6.286, 6.671) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/opit_0/CLK (6.674, 7.122, 6.302, 6.688) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/opit_0/CLK (6.658, 7.105, 6.286, 6.671) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/opit_0/CLK (6.674, 7.122, 6.302, 6.688) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/opit_0/CLK (6.658, 7.105, 6.286, 6.671) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/opit_0/CLK (6.670, 7.117, 6.298, 6.683) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/opit_0/CLK (6.678, 7.125, 6.305, 6.691) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK (6.670, 7.117, 6.298, 6.683) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK (6.658, 7.105, 6.286, 6.671) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/CLK (6.670, 7.117, 6.298, 6.683) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/CLK (6.682, 7.129, 6.310, 6.696) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/opit_0/CLK (6.670, 7.117, 6.298, 6.683) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/opit_0/CLK (6.682, 7.129, 6.310, 6.696) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[11]/opit_0/CLK (6.670, 7.117, 6.298, 6.683) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[11]/opit_0/CLK (6.666, 7.113, 6.293, 6.679) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/CLK (6.679, 7.126, 6.306, 6.692) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/CLK (6.666, 7.113, 6.293, 6.679) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[1]/opit_0/CLK (6.679, 7.126, 6.306, 6.692) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[1]/opit_0/CLK (6.666, 7.113, 6.293, 6.679) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[2]/opit_0/CLK (6.679, 7.126, 6.306, 6.692) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[2]/opit_0/CLK (6.666, 7.113, 6.293, 6.679) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[3]/opit_0/CLK (6.679, 7.126, 6.306, 6.692) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[3]/opit_0/CLK (6.658, 7.105, 6.286, 6.671) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/CLK (6.674, 7.122, 6.302, 6.688) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/CLK (6.658, 7.105, 6.286, 6.671) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[5]/opit_0/CLK (6.674, 7.122, 6.302, 6.688) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[5]/opit_0/CLK (6.658, 7.105, 6.286, 6.671) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[6]/opit_0/CLK (6.670, 7.117, 6.298, 6.683) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[6]/opit_0/CLK (6.666, 7.113, 6.293, 6.679) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[7]/opit_0/CLK (6.670, 7.117, 6.298, 6.683) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[7]/opit_0/CLK (6.682, 7.129, 6.310, 6.696) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/CLK (6.670, 7.117, 6.298, 6.683) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/CLK (6.658, 7.105, 6.286, 6.671) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[9]/opit_0/CLK (6.670, 7.117, 6.298, 6.683) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[9]/opit_0/CLK (6.682, 7.129, 6.310, 6.696) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[10]/opit_0/CLK (6.670, 7.117, 6.298, 6.683) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[10]/opit_0/CLK (6.682, 7.129, 6.310, 6.696) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[11]/opit_0/CLK (6.670, 7.117, 6.298, 6.683) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[11]/opit_0/CLK (6.682, 7.129, 6.310, 6.696) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (6.705, 7.152, 6.332, 6.719) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (6.678, 7.125, 6.305, 6.691) u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (6.692, 7.139, 6.319, 6.705) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM18K/iGopDrm/CLKB[0] (6.678, 7.125, 6.305, 6.691) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM18K/iGopDrm/CLKB[0] (6.700, 7.148, 6.328, 6.714) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[3].U_GTP_DRM18K/iGopDrm/CLKB[0] (6.682, 7.129, 6.310, 6.696) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[3].U_GTP_DRM18K/iGopDrm/CLKB[0] (6.669, 7.116, 6.297, 6.682) - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (6.701, 7.149, 6.329, 6.715) - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (6.701, 7.149, 6.329, 6.715) - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (6.697, 7.145, 6.325, 6.711) - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (6.697, 7.145, 6.325, 6.711) - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (6.693, 7.140, 6.320, 6.707) - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0/CLK (6.694, 7.141, 6.321, 6.708) + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0/CLK (6.681, 7.128, 6.309, 6.694) - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK (6.694, 7.141, 6.321, 6.708) + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK (6.681, 7.128, 6.309, 6.694) u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (6.697, 7.145, 6.325, 6.711) @@ -99338,37 +99090,37 @@ u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (6.697, 7.145, 6.325, 6.711) - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (6.701, 7.149, 6.329, 6.715) + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (6.693, 7.140, 6.320, 6.707) - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (6.701, 7.149, 6.329, 6.715) + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (6.693, 7.140, 6.320, 6.707) - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (6.688, 7.136, 6.316, 6.702) - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (6.700, 7.148, 6.328, 6.714) u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (6.705, 7.152, 6.332, 6.719) - u_axi_ddr_top/u_axi_rd_connect/cnt_times[0]/opit_0_inv_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/cnt_times[0]/opit_0_inv_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/cnt_times[2]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/cnt_times[2]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/cnt_times[4]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/cnt_times[4]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/cnt_times[6]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/cnt_times[6]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/cnt_times[7]/opit_0_inv_AQ/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/cnt_times[7]/opit_0_inv_AQ/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/ddr_fifo_full0/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/ddr_fifo_full0/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/u_axi_rd_connect/rd0_fifo_empty0/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -99380,19 +99132,19 @@ u_axi_ddr_top/u_axi_rd_connect/rd1_fifo_full0/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/rd_ddr_valid/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/rd_ddr_valid/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/rd_sta_reg[0]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/rd_sta_reg[0]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/rd_sta_reg[1]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/rd_sta_reg[1]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/rd_sta_reg[2]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/rd_sta_reg[2]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/rd_sta_reg[3]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/rd_sta_reg[3]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/u_axi_rd_connect/rid_dout0[0]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) @@ -99581,7 +99333,7 @@ u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[11]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) @@ -99590,13 +99342,13 @@ u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -99614,19 +99366,19 @@ u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) @@ -99644,22 +99396,22 @@ u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[10]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[10]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[11]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[11]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wr_water_level[9]/opit_0_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wr_water_level[9]/opit_0_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) @@ -99677,79 +99429,79 @@ u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[6]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[8]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[8]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[11]/opit_0/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[11]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm_inv/CLKA[0] (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm_inv/CLKA[0] (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm_inv/CLKA[0] (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[11]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[11]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[1]/opit_0_A2Q1/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[1]/opit_0_A2Q1/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[3]/opit_0_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[3]/opit_0_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[5]/opit_0_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[5]/opit_0_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[7]/opit_0_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[7]/opit_0_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[9]/opit_0_A2Q21/CLK (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[9]/opit_0_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (6.654, 7.101, 6.282, 6.667) @@ -99758,22 +99510,22 @@ u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM18K/iGopDrm/CLKA[0] (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM18K/iGopDrm/CLKA[0] (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM18K/iGopDrm/CLKB[0] (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM18K/iGopDrm/CLKB[0] (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[3].U_GTP_DRM18K/iGopDrm/CLKA[0] (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[3].U_GTP_DRM18K/iGopDrm/CLKA[0] (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[3].U_GTP_DRM18K/iGopDrm/CLKB[0] (6.764, 7.213, 6.383, 6.770) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[3].U_GTP_DRM18K/iGopDrm/CLKB[0] (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[4].U_GTP_DRM18K/iGopDrm/CLKA[0] (6.654, 7.101, 6.282, 6.667) @@ -99788,10 +99540,10 @@ u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/CLKB[0] (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[6].U_GTP_DRM18K/iGopDrm/CLKA[0] (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[6].U_GTP_DRM18K/iGopDrm/CLKA[0] (6.764, 7.213, 6.383, 6.770) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[6].U_GTP_DRM18K/iGopDrm/CLKB[0] (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[6].U_GTP_DRM18K/iGopDrm/CLKB[0] (6.764, 7.213, 6.383, 6.770) u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[7].U_GTP_DRM18K/iGopDrm/CLKA[0] (6.764, 7.213, 6.383, 6.770) @@ -99839,7 +99591,7 @@ u_axi_ddr_top/u_axi_wr_connect/axi_addr0[19]/opit_0_AQ/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/axi_addr_valid0/opit_0_L5Q_perm/CLK (6.686, 7.134, 6.314, 6.700) + u_axi_ddr_top/u_axi_wr_connect/axi_addr_valid0/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[0]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -99863,13 +99615,13 @@ u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[6]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[7]/opit_0_L5Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[7]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[8]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[9]/opit_0_L5Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[9]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[10]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -99953,7 +99705,7 @@ u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[36]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[37]/opit_0_L5Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[37]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[38]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -99998,7 +99750,7 @@ u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[51]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[52]/opit_0_L5Q/CLK (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[52]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[53]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -100034,19 +99786,19 @@ u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[63]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/axi_data_valid0/opit_0_L5Q_perm/CLK (6.686, 7.134, 6.314, 6.700) + u_axi_ddr_top/u_axi_wr_connect/axi_data_valid0/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/cnt_times[0]/opit_0_L5Q_perm/CLK (6.685, 7.133, 6.313, 6.699) + u_axi_ddr_top/u_axi_wr_connect/cnt_times[0]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/cnt_times[2]/opit_0_A2Q21/CLK (6.681, 7.128, 6.309, 6.694) + u_axi_ddr_top/u_axi_wr_connect/cnt_times[2]/opit_0_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/cnt_times[4]/opit_0_A2Q21/CLK (6.681, 7.128, 6.309, 6.694) + u_axi_ddr_top/u_axi_wr_connect/cnt_times[4]/opit_0_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/cnt_times[6]/opit_0_A2Q21/CLK (6.685, 7.133, 6.313, 6.699) + u_axi_ddr_top/u_axi_wr_connect/cnt_times[6]/opit_0_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/u_axi_wr_connect/ddr0_valid_fall0/opit_0_L5Q/CLK (6.654, 7.101, 6.282, 6.667) @@ -100058,7 +99810,7 @@ u_axi_ddr_top/u_axi_wr_connect/ddr1_valid_fall0/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/ddr1_valid_fall2/opit_0/CLK (6.697, 7.145, 6.325, 6.711) + u_axi_ddr_top/u_axi_wr_connect/ddr1_valid_fall2/opit_0/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/u_axi_wr_connect/ddr3_valid_fall0/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -100097,10 +99849,10 @@ u_axi_ddr_top/u_axi_wr_connect/fifo0_data_full/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/fifo1_data_full/opit_0_L5Q_perm/CLK (6.679, 7.126, 6.306, 6.692) + u_axi_ddr_top/u_axi_wr_connect/fifo1_data_full/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/fifo3_data_full/opit_0_L5Q_perm/CLK (6.677, 7.124, 6.304, 6.690) + u_axi_ddr_top/u_axi_wr_connect/fifo3_data_full/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0/CLK (6.654, 7.101, 6.282, 6.667) @@ -100226,7 +99978,7 @@ u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0/CLK (6.667, 7.114, 6.294, 6.680) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) @@ -100244,13 +99996,13 @@ u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm/CLK (6.679, 7.126, 6.306, 6.692) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm/CLK (6.679, 7.126, 6.306, 6.692) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/CLK (6.679, 7.126, 6.306, 6.692) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -100265,7 +100017,7 @@ u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm/CLK (6.679, 7.126, 6.306, 6.692) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -100274,211 +100026,211 @@ u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/opit_0/CLK (6.667, 7.114, 6.294, 6.680) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/opit_0/CLK (6.686, 7.134, 6.314, 6.700) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/opit_0/CLK (6.671, 7.118, 6.299, 6.685) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/opit_0/CLK (6.694, 7.141, 6.321, 6.708) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/opit_0/CLK (6.667, 7.114, 6.294, 6.680) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/opit_0/CLK (6.686, 7.134, 6.314, 6.700) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK (6.667, 7.114, 6.294, 6.680) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/CLK (6.686, 7.134, 6.314, 6.700) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/opit_0/CLK (6.667, 7.114, 6.294, 6.680) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[11]/opit_0/CLK (6.686, 7.134, 6.314, 6.700) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[11]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[5]/opit_0_A2Q1/CLK (6.671, 7.118, 6.299, 6.685) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[5]/opit_0_A2Q1/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[7]/opit_0_A2Q21/CLK (6.671, 7.118, 6.299, 6.685) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[7]/opit_0_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[9]/opit_0_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[2]/opit_0/CLK (6.667, 7.114, 6.294, 6.680) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[2]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[3]/opit_0/CLK (6.686, 7.134, 6.314, 6.700) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[3]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/CLK (6.667, 7.114, 6.294, 6.680) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[5]/opit_0/CLK (6.671, 7.118, 6.299, 6.685) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[5]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[6]/opit_0/CLK (6.671, 7.118, 6.299, 6.685) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[6]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[7]/opit_0/CLK (6.686, 7.134, 6.314, 6.700) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[7]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/CLK (6.667, 7.114, 6.294, 6.680) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[9]/opit_0/CLK (6.671, 7.118, 6.299, 6.685) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[9]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[10]/opit_0/CLK (6.667, 7.114, 6.294, 6.680) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[10]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[11]/opit_0/CLK (6.667, 7.114, 6.294, 6.680) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[11]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (6.654, 7.101, 6.282, 6.667) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (6.705, 7.152, 6.332, 6.719) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0/CLK (6.673, 7.120, 6.301, 6.687) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (6.686, 7.134, 6.314, 6.700) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (6.686, 7.134, 6.314, 6.700) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (6.678, 7.125, 6.305, 6.691) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (6.678, 7.125, 6.305, 6.691) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (6.673, 7.120, 6.301, 6.687) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm/CLK (6.682, 7.129, 6.310, 6.696) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm/CLK (6.682, 7.129, 6.310, 6.696) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/CLK (6.682, 7.129, 6.310, 6.696) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm/CLK (6.674, 7.122, 6.302, 6.688) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm/CLK (6.682, 7.129, 6.310, 6.696) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm/CLK (6.670, 7.117, 6.298, 6.683) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm/CLK (6.670, 7.117, 6.298, 6.683) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/CLK (6.673, 7.120, 6.301, 6.687) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/opit_0/CLK (6.674, 7.122, 6.302, 6.688) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/opit_0/CLK (6.678, 7.125, 6.305, 6.691) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/opit_0/CLK (6.674, 7.122, 6.302, 6.688) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/opit_0/CLK (6.694, 7.141, 6.321, 6.708) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/opit_0/CLK (6.670, 7.117, 6.298, 6.683) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/opit_0/CLK (6.670, 7.117, 6.298, 6.683) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK (6.661, 7.108, 6.289, 6.675) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/CLK (6.681, 7.128, 6.309, 6.694) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/opit_0/CLK (6.661, 7.108, 6.289, 6.675) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[11]/opit_0/CLK (6.661, 7.108, 6.289, 6.675) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[11]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[5]/opit_0_A2Q1/CLK (6.685, 7.133, 6.313, 6.699) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[5]/opit_0_A2Q1/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[7]/opit_0_A2Q21/CLK (6.685, 7.133, 6.313, 6.699) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[7]/opit_0_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[9]/opit_0_A2Q21/CLK (6.681, 7.128, 6.309, 6.694) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[9]/opit_0_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[2]/opit_0/CLK (6.678, 7.125, 6.305, 6.691) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[2]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[3]/opit_0/CLK (6.694, 7.141, 6.321, 6.708) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[3]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/CLK (6.694, 7.141, 6.321, 6.708) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[5]/opit_0/CLK (6.694, 7.141, 6.321, 6.708) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[5]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[6]/opit_0/CLK (6.685, 7.133, 6.313, 6.699) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[6]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[7]/opit_0/CLK (6.694, 7.141, 6.321, 6.708) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[7]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/CLK (6.681, 7.128, 6.309, 6.694) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[9]/opit_0/CLK (6.694, 7.141, 6.321, 6.708) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[9]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[10]/opit_0/CLK (6.678, 7.125, 6.305, 6.691) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[10]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[11]/opit_0/CLK (6.681, 7.128, 6.309, 6.694) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[11]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (6.700, 7.148, 6.328, 6.714) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (6.669, 7.116, 6.297, 6.682) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKB[0] (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/rd_sta0[0]/opit_0/CLK (6.686, 7.134, 6.314, 6.700) + u_axi_ddr_top/u_axi_wr_connect/rd_sta0[0]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/u_axi_wr_connect/rd_sta0[1]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/rd_sta0[2]/opit_0/CLK (6.682, 7.129, 6.310, 6.696) + u_axi_ddr_top/u_axi_wr_connect/rd_sta0[2]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/u_axi_wr_connect/rd_sta0[3]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) @@ -100487,31 +100239,31 @@ u_axi_ddr_top/u_axi_wr_connect/rd_sta0[4]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/rd_sta0[6]/opit_0/CLK (6.682, 7.129, 6.310, 6.696) + u_axi_ddr_top/u_axi_wr_connect/rd_sta0[6]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/u_axi_wr_connect/rd_sta0[7]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[0]/opit_0_MUX4TO1Q/CLK (6.693, 7.140, 6.320, 6.707) + u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[0]/opit_0_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[1]/opit_0_L5Q_perm/CLK (6.682, 7.129, 6.310, 6.696) + u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[1]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[2]/opit_0_MUX4TO1Q/CLK (6.682, 7.129, 6.310, 6.696) + u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[2]/opit_0_MUX4TO1Q/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[3]/opit_0_L5Q_perm/CLK (6.678, 7.125, 6.305, 6.691) + u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[3]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[4]/opit_0_L5Q_perm/CLK (6.682, 7.129, 6.310, 6.696) + u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[4]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[6]/opit_0_L5Q_perm/CLK (6.679, 7.126, 6.306, 6.692) + u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[6]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[7]/opit_0_L5Q_perm/CLK (6.693, 7.140, 6.320, 6.707) + u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[7]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/u_axi_wr_connect/rx0_addr_valid/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) @@ -100766,259 +100518,259 @@ u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr_valid2/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0_A2Q1/CLK (6.666, 7.113, 6.293, 6.679) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0_A2Q1/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (6.685, 7.133, 6.313, 6.699) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (6.685, 7.133, 6.313, 6.699) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (6.681, 7.128, 6.309, 6.694) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (6.681, 7.128, 6.309, 6.694) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (6.677, 7.124, 6.304, 6.690) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[11]/opit_0_inv_A2Q21/CLK (6.677, 7.124, 6.304, 6.690) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[11]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm/CLK (6.694, 7.141, 6.321, 6.708) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm/CLK (6.679, 7.126, 6.306, 6.692) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/CLK (6.694, 7.141, 6.321, 6.708) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm/CLK (6.694, 7.141, 6.321, 6.708) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm/CLK (6.694, 7.141, 6.321, 6.708) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm/CLK (6.694, 7.141, 6.321, 6.708) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm/CLK (6.662, 7.109, 6.290, 6.676) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm/CLK (6.688, 7.136, 6.316, 6.702) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/CLK (6.684, 7.131, 6.312, 6.698) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/CLK (6.688, 7.136, 6.316, 6.702) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm/CLK (6.688, 7.136, 6.316, 6.702) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[11]/opit_0_L5Q_perm/CLK (6.688, 7.136, 6.316, 6.702) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[11]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0/CLK (6.679, 7.126, 6.306, 6.692) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/opit_0/CLK (6.679, 7.126, 6.306, 6.692) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/opit_0/CLK (6.694, 7.141, 6.321, 6.708) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/opit_0/CLK (6.694, 7.141, 6.321, 6.708) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/opit_0/CLK (6.670, 7.117, 6.298, 6.683) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/opit_0/CLK (6.670, 7.117, 6.298, 6.683) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/opit_0/CLK (6.694, 7.141, 6.321, 6.708) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/opit_0/CLK (6.666, 7.113, 6.293, 6.679) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK (6.666, 7.113, 6.293, 6.679) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/CLK (6.658, 7.105, 6.286, 6.671) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/opit_0/CLK (6.666, 7.113, 6.293, 6.679) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[11]/opit_0/CLK (6.666, 7.113, 6.293, 6.679) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[11]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/CLK (6.679, 7.126, 6.306, 6.692) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[1]/opit_0/CLK (6.694, 7.141, 6.321, 6.708) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[1]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[2]/opit_0/CLK (6.662, 7.109, 6.290, 6.676) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[2]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[3]/opit_0/CLK (6.679, 7.126, 6.306, 6.692) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[3]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/CLK (6.670, 7.117, 6.298, 6.683) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[5]/opit_0/CLK (6.662, 7.109, 6.290, 6.676) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[5]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[6]/opit_0/CLK (6.670, 7.117, 6.298, 6.683) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[6]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[7]/opit_0/CLK (6.662, 7.109, 6.290, 6.676) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[7]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/CLK (6.658, 7.105, 6.286, 6.671) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[9]/opit_0/CLK (6.662, 7.109, 6.290, 6.676) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[9]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[10]/opit_0/CLK (6.658, 7.105, 6.286, 6.671) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[10]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[11]/opit_0/CLK (6.658, 7.105, 6.286, 6.671) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[11]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB (6.678, 7.125, 6.305, 6.691) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK (6.697, 7.145, 6.325, 6.711) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (6.681, 7.128, 6.309, 6.694) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (6.681, 7.128, 6.309, 6.694) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (6.685, 7.133, 6.313, 6.699) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (6.685, 7.133, 6.313, 6.699) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (6.689, 7.137, 6.317, 6.703) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm/CLK (6.688, 7.136, 6.316, 6.702) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm/CLK (6.688, 7.136, 6.316, 6.702) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm/CLK (6.688, 7.136, 6.316, 6.702) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm/CLK (6.688, 7.136, 6.316, 6.702) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/CLK (6.685, 7.133, 6.313, 6.699) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK (6.685, 7.133, 6.313, 6.699) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/CLK (6.685, 7.133, 6.313, 6.699) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/CLK (6.685, 7.133, 6.313, 6.699) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm/CLK (6.697, 7.145, 6.325, 6.711) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm/CLK (6.697, 7.145, 6.325, 6.711) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0/CLK (6.684, 7.131, 6.312, 6.698) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/opit_0/CLK (6.658, 7.105, 6.286, 6.671) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK (6.684, 7.131, 6.312, 6.698) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK (6.688, 7.136, 6.316, 6.702) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK (6.684, 7.131, 6.312, 6.698) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/CLK (6.688, 7.136, 6.316, 6.702) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/opit_0/CLK (6.684, 7.131, 6.312, 6.698) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK (6.705, 7.152, 6.332, 6.719) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/opit_0/CLK (6.697, 7.145, 6.325, 6.711) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/opit_0/CLK (6.671, 7.118, 6.299, 6.685) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wr_water_level[3]/opit_0_A2Q21/CLK (6.688, 7.136, 6.316, 6.702) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wr_water_level[3]/opit_0_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wr_water_level[5]/opit_0_A2Q21/CLK (6.693, 7.140, 6.320, 6.707) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wr_water_level[5]/opit_0_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wr_water_level[7]/opit_0_A2Q21/CLK (6.693, 7.140, 6.320, 6.707) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wr_water_level[7]/opit_0_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wr_water_level[9]/opit_0_A2Q21/CLK (6.697, 7.145, 6.325, 6.711) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wr_water_level[9]/opit_0_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[0]/opit_0/CLK (6.684, 7.131, 6.312, 6.698) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[0]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/CLK (6.658, 7.105, 6.286, 6.671) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK (6.696, 7.144, 6.324, 6.710) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/CLK (6.696, 7.144, 6.324, 6.710) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/CLK (6.696, 7.144, 6.324, 6.710) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[5]/opit_0/CLK (6.697, 7.145, 6.325, 6.711) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[5]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[6]/opit_0/CLK (6.696, 7.144, 6.324, 6.710) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[6]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/CLK (6.684, 7.131, 6.312, 6.698) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[8]/opit_0/CLK (6.697, 7.145, 6.325, 6.711) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[8]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/CLK (6.697, 7.145, 6.325, 6.711) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/CLK (6.654, 7.101, 6.282, 6.667) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm_inv/CLKA (6.673, 7.120, 6.301, 6.687) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm_inv/CLKA (6.654, 7.101, 6.282, 6.667) u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (6.654, 7.101, 6.282, 6.667) @@ -101349,11 +101101,11 @@ clk_25m (net) - clkbufg_7/gopclkbufg/CLK (2.546, 2.816, 2.139, 2.342) + clkbufg_8/gopclkbufg/CLK (2.546, 2.816, 2.139, 2.342) - clkbufg_7/gopclkbufg/CLKOUT (2.546, 2.816, 2.139, 2.342) + clkbufg_8/gopclkbufg/CLKOUT (2.546, 2.816, 2.139, 2.342) - ntclkbufg_7 (net) + ntclkbufg_8 (net) u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK (3.441, 3.741, 3.057, 3.292) @@ -101445,520 +101197,520 @@ clk_10m (net) - clkbufg_3/gopclkbufg/CLK (2.542, 2.812, 2.136, 2.339) + clkbufg_4/gopclkbufg/CLK (2.542, 2.812, 2.136, 2.339) - clkbufg_3/gopclkbufg/CLKOUT (2.542, 2.812, 2.136, 2.339) + clkbufg_4/gopclkbufg/CLKOUT (2.542, 2.812, 2.136, 2.339) - ntclkbufg_3 (net) + ntclkbufg_4 (net) - ms72xx_ctl/iic_dri_rx/busy/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/busy/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/byte_over/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/byte_over/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/data_out[0]/opit_0/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/data_out[0]/opit_0/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/data_out[1]/opit_0/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/data_out[1]/opit_0/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/data_out[2]/opit_0/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/data_out[2]/opit_0/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/data_out[3]/opit_0/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/data_out[3]/opit_0/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/data_out[4]/opit_0/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/data_out[4]/opit_0/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/data_out[5]/opit_0/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/data_out[5]/opit_0/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/data_out[6]/opit_0/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/data_out[6]/opit_0/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/data_out[7]/opit_0/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/data_out[7]/opit_0/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/fre_cnt[0]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/fre_cnt[0]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/fre_cnt[1]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/fre_cnt[1]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/fre_cnt[2]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/fre_cnt[2]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/fre_cnt[3]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/fre_cnt[3]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/fre_cnt[4]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/fre_cnt[4]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/pluse_1d/opit_0_inv/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/pluse_1d/opit_0_inv/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/pluse_2d/opit_0_inv/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/pluse_2d/opit_0_inv/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/pluse_3d/opit_0_inv/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/pluse_3d/opit_0_inv/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/receiv_data[0]/opit_0_inv/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/receiv_data[0]/opit_0_inv/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/receiv_data[1]/opit_0_inv/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/receiv_data[1]/opit_0_inv/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/receiv_data[2]/opit_0_inv/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/receiv_data[2]/opit_0_inv/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/receiv_data[3]/opit_0_inv/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/receiv_data[3]/opit_0_inv/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/receiv_data[4]/opit_0_inv/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/receiv_data[4]/opit_0_inv/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/receiv_data[5]/opit_0_inv/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/receiv_data[5]/opit_0_inv/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/receiv_data[6]/opit_0_inv/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/receiv_data[6]/opit_0_inv/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/receiv_data[7]/opit_0_inv/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/receiv_data[7]/opit_0_inv/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/scl_out/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/scl_out/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/sda_out/opit_0_MUX4TO1Q/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/sda_out/opit_0_MUX4TO1Q/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/send_data[0]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/send_data[0]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/send_data[1]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/send_data[1]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/send_data[2]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/send_data[2]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/send_data[3]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/send_data[3]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/send_data[4]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/send_data[4]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/send_data[5]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/send_data[5]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/send_data[6]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/send_data[6]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/send_data[7]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/send_data[7]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/start_en/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/start_en/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/state_reg[0]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/state_reg[0]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/state_reg[1]/opit_0_inv_MUX4TO1Q/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/state_reg[1]/opit_0_inv_MUX4TO1Q/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/state_reg[2]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/state_reg[2]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/state_reg[3]/opit_0_inv_MUX4TO1Q/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/state_reg[3]/opit_0_inv_MUX4TO1Q/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/state_reg[4]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/state_reg[4]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/state_reg[5]/opit_0_inv_MUX4TO1Q/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/state_reg[5]/opit_0_inv_MUX4TO1Q/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/state_reg[6]/opit_0_inv_MUX4TO1Q/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/state_reg[6]/opit_0_inv_MUX4TO1Q/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/trans_bit[0]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/trans_bit[0]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/trans_bit[1]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/trans_bit[1]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/trans_bit[2]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/trans_bit[2]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/trans_byte[0]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/trans_byte[0]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/trans_byte[1]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/trans_byte[1]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/trans_byte[2]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/trans_byte[2]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/trans_byte[3]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/trans_byte[3]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/trans_byte_max[0]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/trans_byte_max[0]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/trans_byte_max[2]/opit_0/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/trans_byte_max[2]/opit_0/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/trans_en/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/trans_en/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/twr_cnt[0]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/twr_cnt[0]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/twr_cnt[1]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/twr_cnt[1]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/twr_cnt[2]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/twr_cnt[2]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/twr_cnt[3]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/twr_cnt[3]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/twr_en/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/twr_en/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/w_r_1d/opit_0_inv/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/w_r_1d/opit_0_inv/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_rx/w_r_2d/opit_0_inv/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_rx/w_r_2d/opit_0_inv/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/busy/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/busy/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/byte_over/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/byte_over/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/data_out[0]/opit_0/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/data_out[0]/opit_0/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/data_out[1]/opit_0/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/data_out[1]/opit_0/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/data_out[2]/opit_0/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/data_out[2]/opit_0/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/data_out[3]/opit_0/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/data_out[3]/opit_0/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/data_out[4]/opit_0/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/data_out[4]/opit_0/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/data_out[5]/opit_0/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/data_out[5]/opit_0/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/data_out[6]/opit_0/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/data_out[6]/opit_0/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/data_out[7]/opit_0/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/data_out[7]/opit_0/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/pluse_1d/opit_0_inv/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/pluse_1d/opit_0_inv/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/pluse_2d/opit_0_inv/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/pluse_2d/opit_0_inv/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/pluse_3d/opit_0_inv/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/pluse_3d/opit_0_inv/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/receiv_data[0]/opit_0_inv/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/receiv_data[0]/opit_0_inv/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/receiv_data[1]/opit_0_inv/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/receiv_data[1]/opit_0_inv/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/receiv_data[2]/opit_0_inv/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/receiv_data[2]/opit_0_inv/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/receiv_data[3]/opit_0_inv/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/receiv_data[3]/opit_0_inv/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/receiv_data[4]/opit_0_inv/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/receiv_data[4]/opit_0_inv/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/receiv_data[5]/opit_0_inv/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/receiv_data[5]/opit_0_inv/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/receiv_data[6]/opit_0_inv/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/receiv_data[6]/opit_0_inv/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/receiv_data[7]/opit_0_inv/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/receiv_data[7]/opit_0_inv/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/scl_out/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/scl_out/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/sda_out/opit_0_MUX4TO1Q/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/sda_out/opit_0_MUX4TO1Q/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/send_data[0]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/send_data[0]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/send_data[1]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/send_data[1]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/send_data[2]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/send_data[2]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/send_data[3]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/send_data[3]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/send_data[4]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/send_data[4]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/send_data[5]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/send_data[5]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/send_data[6]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/send_data[6]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/send_data[7]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/send_data[7]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/start_en/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/start_en/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/state_reg[0]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/state_reg[0]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/state_reg[1]/opit_0_inv_MUX4TO1Q/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/state_reg[1]/opit_0_inv_MUX4TO1Q/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/state_reg[2]/opit_0_inv_L5Q/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/state_reg[2]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/state_reg[3]/opit_0_inv_MUX4TO1Q/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/state_reg[3]/opit_0_inv_MUX4TO1Q/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/state_reg[4]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/state_reg[4]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/state_reg[5]/opit_0_inv_MUX4TO1Q/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/state_reg[5]/opit_0_inv_MUX4TO1Q/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/state_reg[6]/opit_0_inv_MUX4TO1Q/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/state_reg[6]/opit_0_inv_MUX4TO1Q/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/trans_bit[0]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/trans_bit[0]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/trans_bit[1]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/trans_bit[1]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/trans_bit[2]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/trans_bit[2]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/trans_byte[0]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/trans_byte[0]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/trans_byte[1]/opit_0_L5Q/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/trans_byte[1]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/trans_byte[2]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/trans_byte[2]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/trans_byte[3]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/trans_byte[3]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/trans_byte_max[0]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/trans_byte_max[0]/opit_0_L5Q/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/trans_byte_max[2]/opit_0/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/trans_byte_max[2]/opit_0/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/trans_en/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/trans_en/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/twr_cnt[0]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/twr_cnt[0]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/twr_cnt[1]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/twr_cnt[1]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/twr_cnt[2]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/twr_cnt[2]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/twr_cnt[3]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/twr_cnt[3]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/twr_en/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/twr_en/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/w_r_1d/opit_0_inv/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/w_r_1d/opit_0_inv/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/iic_dri_tx/w_r_2d/opit_0_inv/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/iic_dri_tx/w_r_2d/opit_0_inv/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKA[0] (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKA[0] (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKB[0] (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKB[0] (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/addr[0]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/addr[0]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/addr[1]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/addr[1]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/addr[2]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/addr[2]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/addr[3]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/addr[3]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/addr[4]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/addr[4]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/addr[5]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/addr[5]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/addr[6]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/addr[6]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/addr[7]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/addr[7]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/addr[8]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/addr[8]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/addr[9]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/addr[9]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/addr[12]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/addr[12]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/addr[13]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/addr[13]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/busy_1d/opit_0/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/busy_1d/opit_0/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/cmd_index[0]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/cmd_index[0]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/cmd_index[1]/opit_0_inv_A2Q1/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/cmd_index[1]/opit_0_inv_A2Q1/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/cmd_index[3]/opit_0_inv_A2Q21/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/cmd_index[3]/opit_0_inv_A2Q21/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/cmd_index[5]/opit_0_inv_A2Q21/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/cmd_index[5]/opit_0_inv_A2Q21/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/cmd_index[7]/opit_0_inv_A2Q21/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/cmd_index[7]/opit_0_inv_A2Q21/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/cmd_index[8]/opit_0_inv_AQ/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/cmd_index[8]/opit_0_inv_AQ/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/data_in[0]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/data_in[0]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/data_in[1]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/data_in[1]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/data_in[2]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/data_in[2]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/data_in[3]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/data_in[3]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/data_in[4]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/data_in[4]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/data_in[5]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/data_in[5]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/data_in[6]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/data_in[6]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/data_in[7]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/data_in[7]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/dri_cnt[0]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/dri_cnt[0]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/dri_cnt[1]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/dri_cnt[1]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/dri_cnt[2]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/dri_cnt[2]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/dri_cnt[3]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/dri_cnt[3]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/dri_cnt[5]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/dri_cnt[5]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/dri_cnt[6]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/dri_cnt[6]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/dri_cnt[7]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/dri_cnt[7]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/dri_cnt[8]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/dri_cnt[8]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/freq_ensure/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/freq_ensure/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/freq_rec_1d[16]/opit_0/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/freq_rec_1d[16]/opit_0/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/freq_rec_1d[17]/opit_0/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/freq_rec_1d[17]/opit_0/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/freq_rec_2d[16]/opit_0/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/freq_rec_2d[16]/opit_0/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/freq_rec_2d[17]/opit_0/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/freq_rec_2d[17]/opit_0/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/freq_rec[16]/opit_0_inv/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/freq_rec[16]/opit_0_inv/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/freq_rec[17]/opit_0_inv/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/freq_rec[17]/opit_0_inv/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/iic_trig/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/iic_trig/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/init_over/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/init_over/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/state_reg[0]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/state_reg[0]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/state_reg[1]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/state_reg[1]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/state_reg[2]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/state_reg[2]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/state_reg[3]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/state_reg[3]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/state_reg[4]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/state_reg[4]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7200_ctl/w_r/opit_0_inv_MUX4TO1Q/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7200_ctl/w_r/opit_0_inv_MUX4TO1Q/CLK (3.547, 3.849, 3.155, 3.392) ms72xx_ctl/ms7210_ctl/N325_1_concat_2/iGopDrm/CLKA (3.437, 3.737, 3.054, 3.289) @@ -101967,163 +101719,163 @@ ms72xx_ctl/ms7210_ctl/N325_1_concat_2/iGopDrm/CLKB (3.437, 3.737, 3.054, 3.289) - ms72xx_ctl/ms7210_ctl/addr[0]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/addr[0]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/addr[1]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/addr[1]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/addr[2]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/addr[2]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/addr[3]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/addr[3]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/addr[4]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/addr[4]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/addr[5]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/addr[5]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/addr[6]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/addr[6]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/addr[7]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/addr[7]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/addr[8]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/addr[8]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/addr[9]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/addr[9]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/addr[10]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/addr[10]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/addr[11]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/addr[11]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/busy_1d/opit_0/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/busy_1d/opit_0/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/cmd_index[0]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/cmd_index[0]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/cmd_index[1]/opit_0_inv_A2Q1/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/cmd_index[1]/opit_0_inv_A2Q1/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/cmd_index[3]/opit_0_inv_A2Q21/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/cmd_index[3]/opit_0_inv_A2Q21/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/cmd_index[5]/opit_0_inv_A2Q21/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/cmd_index[5]/opit_0_inv_A2Q21/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/data_in[0]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/data_in[0]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/data_in[1]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/data_in[1]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/data_in[2]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/data_in[2]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/data_in[3]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/data_in[3]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/data_in[4]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/data_in[4]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/data_in[5]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/data_in[5]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/data_in[6]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/data_in[6]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/data_in[7]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/data_in[7]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/delay_cnt[0]/opit_0_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/delay_cnt[0]/opit_0_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/delay_cnt[2]/opit_0_A2Q21/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/delay_cnt[2]/opit_0_A2Q21/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/delay_cnt[4]/opit_0_A2Q21/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/delay_cnt[4]/opit_0_A2Q21/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/delay_cnt[6]/opit_0_A2Q21/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/delay_cnt[6]/opit_0_A2Q21/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/delay_cnt[8]/opit_0_A2Q21/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/delay_cnt[8]/opit_0_A2Q21/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/delay_cnt[10]/opit_0_A2Q21/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/delay_cnt[10]/opit_0_A2Q21/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/delay_cnt[12]/opit_0_A2Q21/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/delay_cnt[12]/opit_0_A2Q21/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/delay_cnt[14]/opit_0_A2Q21/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/delay_cnt[14]/opit_0_A2Q21/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/delay_cnt[16]/opit_0_A2Q21/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/delay_cnt[16]/opit_0_A2Q21/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/delay_cnt[18]/opit_0_A2Q21/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/delay_cnt[18]/opit_0_A2Q21/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/delay_cnt[20]/opit_0_A2Q21/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/delay_cnt[20]/opit_0_A2Q21/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/delay_cnt[21]/opit_0_AQ/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/delay_cnt[21]/opit_0_AQ/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/dri_cnt[0]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/dri_cnt[0]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/dri_cnt[1]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/dri_cnt[1]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/dri_cnt[2]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/dri_cnt[2]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/dri_cnt[3]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/dri_cnt[3]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/iic_trig/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/iic_trig/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/init_over/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/init_over/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/state_reg[1]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/state_reg[1]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/state_reg[2]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/state_reg[2]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/state_reg[3]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/state_reg[3]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/state_reg[4]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/state_reg[4]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/state_reg[5]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/state_reg[5]/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/ms7210_ctl/w_r/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/ms7210_ctl/w_r/opit_0_inv_L5Q_perm/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/rstn/opit_0/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/rstn/opit_0/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/rstn_temp1/opit_0_inv/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/rstn_temp1/opit_0_inv/CLK (3.547, 3.849, 3.155, 3.392) - ms72xx_ctl/rstn_temp2/opit_0/CLK (3.437, 3.737, 3.054, 3.289) + ms72xx_ctl/rstn_temp2/opit_0/CLK (3.547, 3.849, 3.155, 3.392) rstn_1ms[0]/opit_0_inv_L5Q_perm/CLK (3.437, 3.737, 3.054, 3.289) @@ -102187,11 +101939,11 @@ _N64 (net) - clkbufg_5/gopclkbufg/CLK (2.277, 2.450, 2.320, 2.499) + clkbufg_6/gopclkbufg/CLK (2.277, 2.450, 2.320, 2.499) - clkbufg_5/gopclkbufg/CLKOUT (2.277, 2.450, 2.320, 2.499) + clkbufg_6/gopclkbufg/CLKOUT (2.277, 2.450, 2.320, 2.499) - ntclkbufg_5 (net) + ntclkbufg_6 (net) u_ov5640/cmos1_8_16bit/de_cnt/opit_0_L5Q_perm/CLK (3.172, 3.375, 3.238, 3.449) @@ -102334,64 +102086,64 @@ u_ov5640/cmos1_8_16bit/vs_in1/opit_0/CLK (3.172, 3.375, 3.238, 3.449) - u_ov5640/cmos1_d_d0[0]/opit_0/CLK (3.172, 3.375, 3.238, 3.449) + u_ov5640/cmos1_d_d0[0]/opit_0/CLK (3.172, 3.375, 3.238, 3.449) - u_ov5640/cmos1_d_d0[1]/opit_0/CLK (3.172, 3.375, 3.238, 3.449) + u_ov5640/cmos1_d_d0[1]/opit_0/CLK (3.172, 3.375, 3.238, 3.449) - u_ov5640/cmos1_d_d0[2]/opit_0/CLK (3.172, 3.375, 3.238, 3.449) + u_ov5640/cmos1_d_d0[2]/opit_0/CLK (3.172, 3.375, 3.238, 3.449) - u_ov5640/cmos1_d_d0[3]/opit_0/CLK (3.172, 3.375, 3.238, 3.449) + u_ov5640/cmos1_d_d0[3]/opit_0/CLK (3.172, 3.375, 3.238, 3.449) - u_ov5640/cmos1_d_d0[4]/opit_0/CLK (3.172, 3.375, 3.238, 3.449) + u_ov5640/cmos1_d_d0[4]/opit_0/CLK (3.172, 3.375, 3.238, 3.449) - u_ov5640/cmos1_d_d0[5]/opit_0/CLK (3.172, 3.375, 3.238, 3.449) + u_ov5640/cmos1_d_d0[5]/opit_0/CLK (3.172, 3.375, 3.238, 3.449) - u_ov5640/cmos1_d_d0[6]/opit_0/CLK (3.172, 3.375, 3.238, 3.449) + u_ov5640/cmos1_d_d0[6]/opit_0/CLK (3.172, 3.375, 3.238, 3.449) - u_ov5640/cmos1_d_d0[7]/opit_0/CLK (3.172, 3.375, 3.238, 3.449) + u_ov5640/cmos1_d_d0[7]/opit_0/CLK (3.172, 3.375, 3.238, 3.449) - u_ov5640/cmos1_d_d1[0]/opit_0/CLK (3.172, 3.375, 3.238, 3.449) + u_ov5640/cmos1_d_d1[0]/opit_0/CLK (3.172, 3.375, 3.238, 3.449) - u_ov5640/cmos1_d_d1[1]/opit_0/CLK (3.172, 3.375, 3.238, 3.449) + u_ov5640/cmos1_d_d1[1]/opit_0/CLK (3.172, 3.375, 3.238, 3.449) - u_ov5640/cmos1_d_d1[2]/opit_0/CLK (3.172, 3.375, 3.238, 3.449) + u_ov5640/cmos1_d_d1[2]/opit_0/CLK (3.172, 3.375, 3.238, 3.449) - u_ov5640/cmos1_d_d1[3]/opit_0/CLK (3.172, 3.375, 3.238, 3.449) + u_ov5640/cmos1_d_d1[3]/opit_0/CLK (3.172, 3.375, 3.238, 3.449) - u_ov5640/cmos1_d_d1[4]/opit_0/CLK (3.172, 3.375, 3.238, 3.449) + u_ov5640/cmos1_d_d1[4]/opit_0/CLK (3.172, 3.375, 3.238, 3.449) - u_ov5640/cmos1_d_d1[5]/opit_0/CLK (3.172, 3.375, 3.238, 3.449) + u_ov5640/cmos1_d_d1[5]/opit_0/CLK (3.172, 3.375, 3.238, 3.449) - u_ov5640/cmos1_d_d1[6]/opit_0/CLK (3.172, 3.375, 3.238, 3.449) + u_ov5640/cmos1_d_d1[6]/opit_0/CLK (3.172, 3.375, 3.238, 3.449) - u_ov5640/cmos1_d_d1[7]/opit_0/CLK (3.172, 3.375, 3.238, 3.449) + u_ov5640/cmos1_d_d1[7]/opit_0/CLK (3.172, 3.375, 3.238, 3.449) - u_ov5640/cmos1_href_d0/opit_0/CLK (3.172, 3.375, 3.238, 3.449) + u_ov5640/cmos1_href_d0/opit_0/CLK (3.172, 3.375, 3.238, 3.449) - u_ov5640/cmos1_href_d1/opit_0/CLK (3.172, 3.375, 3.238, 3.449) + u_ov5640/cmos1_href_d1/opit_0/CLK (3.172, 3.375, 3.238, 3.449) - u_ov5640/cmos1_vsync_d0/opit_0/CLK (3.172, 3.375, 3.238, 3.449) + u_ov5640/cmos1_vsync_d0/opit_0/CLK (3.172, 3.375, 3.238, 3.449) - u_ov5640/cmos1_vsync_d1/opit_0/CLK (3.172, 3.375, 3.238, 3.449) + u_ov5640/cmos1_vsync_d1/opit_0/CLK (3.172, 3.375, 3.238, 3.449) u_ov5640/u_mix_image/cnt0_h[0]/opit_0_L5Q_perm/CLK (3.172, 3.375, 3.238, 3.449) @@ -102574,364 +102326,364 @@ nt_cmos2_pclk (net) - clkbufg_6/gopclkbufg/CLK (2.617, 2.936, 2.870, 3.180) + clkbufg_7/gopclkbufg/CLK (2.616, 2.935, 2.869, 3.179) - clkbufg_6/gopclkbufg/CLKOUT (2.617, 2.936, 2.870, 3.180) + clkbufg_7/gopclkbufg/CLKOUT (2.616, 2.935, 2.869, 3.179) - ntclkbufg_6 (net) + ntclkbufg_7 (net) - u_ov5640/cmos2_8_16bit/de_cnt/opit_0_L5Q/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/de_cnt/opit_0_L5Q_perm/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_8_16bit/de_in0/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/de_in0/opit_0/CLK (3.538, 3.887, 3.814, 4.156) - u_ov5640/cmos2_8_16bit/de_in1/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/de_in1/opit_0/CLK (3.550, 3.899, 3.825, 4.169) - u_ov5640/cmos2_8_16bit/image_data0[0]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/image_data0[0]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_8_16bit/image_data0[1]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/image_data0[1]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_8_16bit/image_data0[2]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/image_data0[2]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_8_16bit/image_data0[3]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/image_data0[3]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_8_16bit/image_data0[4]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/image_data0[4]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_8_16bit/image_data0[5]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/image_data0[5]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_8_16bit/image_data0[6]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/image_data0[6]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_8_16bit/image_data0[7]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/image_data0[7]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_8_16bit/image_data0[8]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/image_data0[8]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_8_16bit/image_data0[9]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/image_data0[9]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_8_16bit/image_data0[10]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/image_data0[10]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_8_16bit/image_data0[11]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/image_data0[11]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_8_16bit/image_data0[12]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/image_data0[12]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_8_16bit/image_data0[13]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/image_data0[13]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_8_16bit/image_data0[14]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/image_data0[14]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_8_16bit/image_data0[15]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/image_data0[15]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_8_16bit/image_data_valid0/opit_0_L5Q_perm/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/image_data_valid0/opit_0_L5Q_perm/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_8_16bit/image_in_en/opit_0_L5Q_perm/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/image_in_en/opit_0_L5Q_perm/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_8_16bit/pdata_i0[0]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/pdata_i0[0]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_8_16bit/pdata_i0[1]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/pdata_i0[1]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_8_16bit/pdata_i0[2]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/pdata_i0[2]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_8_16bit/pdata_i0[3]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/pdata_i0[3]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_8_16bit/pdata_i0[4]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/pdata_i0[4]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_8_16bit/pdata_i0[5]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/pdata_i0[5]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_8_16bit/pdata_i0[6]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/pdata_i0[6]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_8_16bit/pdata_i0[7]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/pdata_i0[7]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_8_16bit/pdata_i1[0]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/pdata_i1[0]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_8_16bit/pdata_i1[1]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/pdata_i1[1]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_8_16bit/pdata_i1[2]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/pdata_i1[2]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_8_16bit/pdata_i1[3]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/pdata_i1[3]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_8_16bit/pdata_i1[4]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/pdata_i1[4]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_8_16bit/pdata_i1[5]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/pdata_i1[5]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_8_16bit/pdata_i1[6]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/pdata_i1[6]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_8_16bit/pdata_i1[7]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/pdata_i1[7]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_8_16bit/pdata_i2[0]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/pdata_i2[0]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_8_16bit/pdata_i2[1]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/pdata_i2[1]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_8_16bit/pdata_i2[2]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/pdata_i2[2]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_8_16bit/pdata_i2[3]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/pdata_i2[3]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_8_16bit/pdata_i2[4]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/pdata_i2[4]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_8_16bit/pdata_i2[5]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/pdata_i2[5]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_8_16bit/pdata_i2[6]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/pdata_i2[6]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_8_16bit/pdata_i2[7]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/pdata_i2[7]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_8_16bit/vs_in0/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/vs_in0/opit_0/CLK (3.550, 3.899, 3.825, 4.169) - u_ov5640/cmos2_8_16bit/vs_in1/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_8_16bit/vs_in1/opit_0/CLK (3.550, 3.899, 3.825, 4.169) - u_ov5640/cmos2_d_d0[0]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_d_d0[0]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_d_d0[1]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_d_d0[1]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_d_d0[2]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_d_d0[2]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_d_d0[3]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_d_d0[3]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_d_d0[4]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_d_d0[4]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_d_d0[5]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_d_d0[5]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_d_d0[6]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_d_d0[6]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_d_d0[7]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_d_d0[7]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_d_d1[0]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_d_d1[0]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_d_d1[1]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_d_d1[1]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_d_d1[2]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_d_d1[2]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_d_d1[3]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_d_d1[3]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_d_d1[4]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_d_d1[4]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_d_d1[5]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_d_d1[5]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_d_d1[6]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_d_d1[6]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_d_d1[7]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_d_d1[7]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/cmos2_href_d0/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_href_d0/opit_0/CLK (3.550, 3.899, 3.825, 4.169) - u_ov5640/cmos2_href_d1/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_href_d1/opit_0/CLK (3.538, 3.887, 3.814, 4.156) - u_ov5640/cmos2_vsync_d0/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_vsync_d0/opit_0/CLK (3.550, 3.899, 3.825, 4.169) - u_ov5640/cmos2_vsync_d1/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/cmos2_vsync_d1/opit_0/CLK (3.550, 3.899, 3.825, 4.169) - u_ov5640/u_mix_image/cnt1_h[0]/opit_0_L5Q_perm/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/cnt1_h[0]/opit_0_L5Q_perm/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/cnt1_w[0]/opit_0_L5Q/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/cnt1_w[0]/opit_0_L5Q/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/cnt1_w[2]/opit_0_A2Q21/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/cnt1_w[2]/opit_0_A2Q21/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/cnt1_w[4]/opit_0_A2Q21/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/cnt1_w[4]/opit_0_A2Q21/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/cnt1_w[6]/opit_0_A2Q21/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/cnt1_w[6]/opit_0_A2Q21/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/cnt1_w[7]/opit_0_A2Q0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/cnt1_w[7]/opit_0_A2Q0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/cnt1_w[8]/opit_0_L5Q_perm/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/cnt1_w[8]/opit_0_L5Q_perm/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/cnt1_w[9]/opit_0_A2Q0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/cnt1_w[9]/opit_0_A2Q0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/cnt1_w[10]/opit_0_L5Q_perm/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/cnt1_w[10]/opit_0_L5Q_perm/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/image2_en/opit_0_L5Q_perm/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/image2_en/opit_0_L5Q_perm/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[10]/opit_0_inv_AQ_perm/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[10]/opit_0_inv_AQ_perm/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[10]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[10]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[0]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[0]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[5]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[5]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[6]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[6]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[8]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[8]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/CLK (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/CLK (3.511, 3.860, 3.787, 4.129) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.512, 3.861, 3.788, 4.130) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.511, 3.860, 3.787, 4.129) @@ -102961,11 +102713,11 @@ _N37 (net) - clkbufg_4/gopclkbufg/CLK (2.829, 3.095, 2.434, 2.632) + clkbufg_5/gopclkbufg/CLK (2.829, 3.095, 2.434, 2.632) - clkbufg_4/gopclkbufg/CLKOUT (2.829, 3.095, 2.434, 2.632) + clkbufg_5/gopclkbufg/CLKOUT (2.829, 3.095, 2.434, 2.632) - ntclkbufg_4 (net) + ntclkbufg_5 (net) u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK (3.724, 4.020, 3.352, 3.582) @@ -102991,10 +102743,10 @@ u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm/CLK (3.724, 4.020, 3.352, 3.582) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm/CLK (3.749, 4.045, 3.376, 3.607) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm/CLK (3.724, 4.020, 3.352, 3.582) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/CLK (3.749, 4.045, 3.376, 3.607) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/CLK (3.724, 4.020, 3.352, 3.582) u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK (3.724, 4.020, 3.352, 3.582) @@ -103048,13 +102800,13 @@ u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/opit_0/CLK (3.724, 4.020, 3.352, 3.582) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[0]/opit_0/CLK (3.749, 4.045, 3.376, 3.607) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[0]/opit_0/CLK (3.724, 4.020, 3.352, 3.582) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/CLK (3.749, 4.045, 3.376, 3.607) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/CLK (3.724, 4.020, 3.352, 3.582) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK (3.749, 4.045, 3.376, 3.607) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK (3.724, 4.020, 3.352, 3.582) u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/CLK (3.724, 4.020, 3.352, 3.582) @@ -103084,7 +102836,7 @@ u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] (3.724, 4.020, 3.352, 3.582) - u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[0]/opit_0_L5Q_perm/CLK (3.724, 4.020, 3.352, 3.582) + u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[0]/opit_0_L5Q/CLK (3.724, 4.020, 3.352, 3.582) u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[1]/opit_0_L5Q_perm/CLK (3.724, 4.020, 3.352, 3.582) @@ -103096,7 +102848,7 @@ u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[3]/opit_0_L5Q_perm/CLK (3.724, 4.020, 3.352, 3.582) - u_ddr_addr_ctr/u_wr1_addr_ctr/image_fram_cnt1[0]/opit_0_L5Q/CLK (3.724, 4.020, 3.352, 3.582) + u_ddr_addr_ctr/u_wr1_addr_ctr/image_fram_cnt1[0]/opit_0_L5Q_perm/CLK (3.724, 4.020, 3.352, 3.582) u_ddr_addr_ctr/u_wr1_addr_ctr/image_fram_cnt1[1]/opit_0_L5Q_perm/CLK (3.724, 4.020, 3.352, 3.582) @@ -103479,7 +103231,7 @@ - eth_rxc (125.00MHZ) (drive 1861 loads) (min_rise, max_rise, min_fall, max_fall) + eth_rxc (125.00MHZ) (drive 1862 loads) (min_rise, max_rise, min_fall, max_fall) eth_rxc (0.000, 0.000, 0.000, 0.000) @@ -103507,37 +103259,37 @@ gmii_clk (net) - param_manager_inst/clk_ms/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/clk_ms/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/filiter1_mode_flags_ff0/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/filiter1_mode_flags_ff0/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/filiter1_mode_flags_ff1/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/filiter1_mode_flags_ff1/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/filiter1_mode_load/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/filiter1_mode_load/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/filiter2_mode_flags_ff0/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/filiter2_mode_flags_ff0/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/filiter2_mode_flags_ff1/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/filiter2_mode_flags_ff1/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/filiter2_mode_load/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/filiter2_mode_load/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/index[0]/opit_0_L5Q/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/index[0]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/index[1]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/index[1]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/index[2]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/index[2]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/index[3]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/index[3]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) param_manager_inst/key_debounce_key_left/change/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) @@ -103627,169 +103379,169 @@ param_manager_inst/key_debounce_key_right/pressed/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/modify_H_flags_ff0/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/modify_H_flags_ff0/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/modify_H_flags_ff1/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/modify_H_flags_ff1/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/modify_H_flags_ff2/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/modify_H_flags_ff2/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/modify_H_flags_ff3/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/modify_H_flags_ff3/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/modify_H_load/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/modify_H_load/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/modify_S_flags_ff0/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/modify_S_flags_ff0/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/modify_S_flags_ff1/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/modify_S_flags_ff1/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/modify_S_flags_ff2/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/modify_S_flags_ff2/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/modify_S_flags_ff3/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/modify_S_flags_ff3/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/modify_S_load/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/modify_S_load/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/modify_V_flags_ff0/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/modify_V_flags_ff0/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/modify_V_flags_ff1/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/modify_V_flags_ff1/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/modify_V_flags_ff2/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/modify_V_flags_ff2/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/modify_V_flags_ff3/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/modify_V_flags_ff3/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/modify_V_load/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/modify_V_load/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/ms_cnt[0]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/ms_cnt[0]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/ms_cnt[2]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/ms_cnt[2]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/ms_cnt[4]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/ms_cnt[4]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/ms_cnt[6]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/ms_cnt[6]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/ms_cnt[8]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/ms_cnt[8]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/ms_cnt[10]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/ms_cnt[10]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/ms_cnt[12]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/ms_cnt[12]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/ms_cnt[14]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/ms_cnt[14]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/ms_cnt[16]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/ms_cnt[16]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/offsetX_flags_ff0/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/offsetX_flags_ff0/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/offsetX_flags_ff1/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/offsetX_flags_ff1/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/offsetX_flags_ff2/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/offsetX_flags_ff2/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/offsetX_flags_ff3/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/offsetX_flags_ff3/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/offsetX_load/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/offsetX_load/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/offsetY_flags_ff0/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/offsetY_flags_ff0/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/offsetY_flags_ff1/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/offsetY_flags_ff1/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/offsetY_flags_ff2/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/offsetY_flags_ff2/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/offsetY_flags_ff3/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/offsetY_flags_ff3/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/offsetY_load/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/offsetY_load/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/osd_char_height_flags_ff0/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/osd_char_height_flags_ff0/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/osd_char_height_flags_ff1/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/osd_char_height_flags_ff1/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/osd_char_height_flags_ff2/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/osd_char_height_flags_ff2/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/osd_char_height_flags_ff3/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/osd_char_height_flags_ff3/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/osd_char_height_load/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/osd_char_height_load/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/osd_char_width_flags_ff0/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/osd_char_width_flags_ff0/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/osd_char_width_flags_ff1/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/osd_char_width_flags_ff1/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/osd_char_width_flags_ff2/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/osd_char_width_flags_ff2/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/osd_char_width_flags_ff3/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/osd_char_width_flags_ff3/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/osd_char_width_load/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/osd_char_width_load/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/osd_startX_flags_ff0/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/osd_startX_flags_ff0/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/osd_startX_flags_ff1/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/osd_startX_flags_ff1/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/osd_startX_flags_ff2/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/osd_startX_flags_ff2/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/osd_startX_flags_ff3/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/osd_startX_flags_ff3/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/osd_startX_load/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/osd_startX_load/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/osd_startY_flags_ff0/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/osd_startY_flags_ff0/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/osd_startY_flags_ff1/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/osd_startY_flags_ff1/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/osd_startY_flags_ff2/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/osd_startY_flags_ff2/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/osd_startY_flags_ff3/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/osd_startY_flags_ff3/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/osd_startY_load/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/osd_startY_load/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/param_filiter1_mode/cnt[0]/opit_0_L5Q/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/param_filiter1_mode/cnt[0]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) param_manager_inst/param_filiter1_mode/cnt[1]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) @@ -103882,7 +103634,7 @@ param_manager_inst/param_filiter1_mode/pluse/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/param_filiter1_mode/value[0]/opit_0_MUX4TO1Q/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/param_filiter1_mode/value[0]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) param_manager_inst/param_filiter1_mode/value[1]/opit_0_MUX4TO1Q/CLK (5.650, 6.734, 5.707, 6.813) @@ -103906,7 +103658,7 @@ param_manager_inst/param_modify_H/cnt[1]/opit_0_A2Q0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/param_modify_H/cnt[2]/opit_0_L5Q/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/param_modify_H/cnt[2]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) param_manager_inst/param_modify_H/cnt[3]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) @@ -104221,7 +103973,7 @@ param_manager_inst/param_osd_startX/cnt[1]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/param_osd_startX/cnt[2]/opit_0_L5Q/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/param_osd_startX/cnt[2]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) param_manager_inst/param_osd_startX/cnt[3]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) @@ -104359,13 +104111,13 @@ param_manager_inst/param_rotate/value[3]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/param_rotate/value[4]/opit_0_MUX4TO1Q/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/param_rotate/value[4]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) param_manager_inst/param_rotate/value[5]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/param_rotate/value[6]/opit_0_MUX4TO1Q/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/param_rotate/value[6]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) param_manager_inst/param_rotate/value[7]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) @@ -104431,370 +104183,370 @@ param_manager_inst/param_zoom/value[9]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/rotate_A_flags_ff0/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/rotate_A_flags_ff0/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/rotate_A_flags_ff1/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/rotate_A_flags_ff1/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/rotate_A_flags_ff2/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/rotate_A_flags_ff2/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/rotate_A_flags_ff3/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/rotate_A_flags_ff3/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/rotate_A_load/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/rotate_A_load/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/rotate_flags_ff0/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/rotate_flags_ff0/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/rotate_flags_ff1/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/rotate_flags_ff1/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/rotate_load/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/rotate_load/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/selected[0]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/selected[0]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/selected[1]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/selected[1]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/selected[2]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/selected[2]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/selected[3]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/selected[3]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/selected[4]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/selected[4]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/selected[5]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/selected[5]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/selected[6]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/selected[6]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/selected[7]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/selected[7]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/selected[8]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/selected[8]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/selected[9]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/selected[9]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/selected[10]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/selected[10]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/selected[11]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/selected[11]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/selected[12]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/selected[12]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/selected[13]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/selected[13]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/zoom_flags_ff0/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/zoom_flags_ff0/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/zoom_flags_ff1/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/zoom_flags_ff1/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/zoom_flags_ff2/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/zoom_flags_ff2/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/zoom_flags_ff3/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/zoom_flags_ff3/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - param_manager_inst/zoom_load/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + param_manager_inst/zoom_load/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0_A2Q1/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0_A2Q1/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/opit_0_inv_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/opit_0_inv_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/opit_0_inv_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[11]/opit_0_inv_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[11]/opit_0_inv_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[11]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[11]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[11]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[11]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[10]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[10]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[11]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[11]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[1]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[1]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[2]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[2]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[3]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[3]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[5]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[5]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[6]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[6]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[7]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[7]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[9]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[9]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[10]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[10]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[11]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[11]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[0]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[5]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[5]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[6]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[6]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[8]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[8]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[11]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[11]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/arp_rx_done/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/arp_rx_done/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/arp_rx_type/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/arp_rx_type/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt[0]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt[0]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt[1]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt[1]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt[2]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt[2]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt[3]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt[3]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt[4]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt[4]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[0]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) @@ -104803,7 +104555,7 @@ udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[1]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[2]/opit_0_L5Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[2]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[3]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) @@ -104812,100 +104564,100 @@ udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cur_state_reg[4]/opit_0_L6Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[1]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[1]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[2]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[2]/opit_0_L5Q/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[3]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[3]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[4]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[4]/opit_0_L5Q/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[5]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[5]/opit_0_L5Q/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[6]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[6]/opit_0_L5Q/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[7]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[7]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[8]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[8]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[9]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[9]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[10]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[10]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[11]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[11]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[12]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[12]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[13]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[13]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[14]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[14]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[15]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[15]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[16]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[16]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[17]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[17]/opit_0_L5Q/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[18]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[18]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[19]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[19]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[20]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[20]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[21]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[21]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[22]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[22]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[23]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[23]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[24]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[24]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[25]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[25]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[26]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[26]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[27]/opit_0_L5Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[27]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[28]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[28]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[29]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[29]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[30]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[30]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[31]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[31]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) @@ -104914,16 +104666,16 @@ udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[1]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[2]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[2]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[3]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[3]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[4]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[4]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[5]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[5]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[6]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) @@ -104932,31 +104684,31 @@ udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[7]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[8]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[8]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[9]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[9]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[10]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[10]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[11]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[11]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[12]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[12]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[13]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[13]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[14]/opit_0_L5Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[14]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[15]/opit_0_L5Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[15]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[16]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[16]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[17]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) @@ -104965,7 +104717,7 @@ udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[18]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[19]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[19]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[20]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) @@ -104974,13 +104726,13 @@ udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[21]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[22]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[22]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[23]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[24]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[24]/opit_0_L5Q/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[25]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) @@ -104989,7 +104741,7 @@ udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[26]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[27]/opit_0_L5Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[27]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[28]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) @@ -105004,7 +104756,7 @@ udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[31]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[32]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[32]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[33]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) @@ -105049,82 +104801,82 @@ udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[46]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[47]/opit_0_L5Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[47]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/error_en/opit_0_MUX4TO1Q/CLK (5.650, 6.734, 5.707, 6.813) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/eth_type[8]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/eth_type[8]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/eth_type[9]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/eth_type[9]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/eth_type[10]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/eth_type[10]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/eth_type[11]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/eth_type[11]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/eth_type[12]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/eth_type[12]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/eth_type[13]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/eth_type[13]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/eth_type[14]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/eth_type[14]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/eth_type[15]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/eth_type[15]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[0]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[1]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[1]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[2]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[2]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[3]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[3]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[4]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[4]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[5]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[5]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[6]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[6]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[7]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[7]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[8]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[8]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[9]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[9]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[10]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[10]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[11]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[11]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[12]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[12]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[13]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[13]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[14]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[14]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[15]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/op_data[15]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/skip_en/opit_0_MUX4TO1Q/CLK (5.650, 6.734, 5.707, 6.813) @@ -105139,7 +104891,7 @@ udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[2]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[3]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[3]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[4]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) @@ -105148,10 +104900,10 @@ udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[5]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[6]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[6]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[7]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[7]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[8]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) @@ -105160,49 +104912,49 @@ udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[9]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[10]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[10]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[11]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[11]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[12]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[12]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[13]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[14]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[14]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[15]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[15]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[16]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[16]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[17]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[18]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[18]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[19]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[19]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[20]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[20]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[21]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[21]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[22]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[22]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[23]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[23]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[24]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[24]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[25]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) @@ -105211,46 +104963,46 @@ udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[26]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[27]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[27]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[28]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[28]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[29]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[29]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[30]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[30]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[31]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[31]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[0]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[1]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[1]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[2]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[3]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[3]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[4]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[4]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[5]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[5]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[6]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[6]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[7]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[7]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[8]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[8]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[9]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) @@ -105259,22 +105011,22 @@ udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[10]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[11]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[11]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[12]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[12]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[13]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[13]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[14]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[14]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[15]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[16]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[16]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[17]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) @@ -105283,340 +105035,340 @@ udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[18]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[19]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[19]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[20]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[20]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[21]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[21]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[22]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[22]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[23]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[23]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[24]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[24]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[25]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[25]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[26]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[27]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[27]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[28]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[28]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[29]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[29]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[30]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[30]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[31]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[0]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[1]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[1]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[2]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[3]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[3]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[4]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[4]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[5]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[5]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[6]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[6]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[7]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[7]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[8]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[8]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[9]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[9]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[10]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[10]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[11]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[11]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[12]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[12]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[13]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[13]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[14]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[14]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[15]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[15]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[16]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[16]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[17]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[17]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[18]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[18]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[19]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[19]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[20]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[20]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[21]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[21]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[22]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[22]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[23]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[23]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[24]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[24]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[25]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[25]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[26]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[26]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[27]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[27]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[28]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[28]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[29]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[29]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[30]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[30]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[31]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[31]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[32]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[32]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[33]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[33]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[34]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[34]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[35]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[35]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[36]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[36]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[37]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[37]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[38]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[38]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[39]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[39]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[40]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[40]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[41]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[41]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[42]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[42]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[43]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[43]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[44]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[44]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[45]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[45]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[46]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[46]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[47]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[47]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[0]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[1]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[1]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[2]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[2]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[3]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[3]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[4]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[4]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[5]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[5]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[6]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[6]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[7]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[7]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[8]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[8]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[9]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[9]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[10]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[10]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[11]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[11]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[12]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[12]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[13]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[13]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[14]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[14]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[15]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[15]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[16]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[16]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[17]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[17]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[18]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[18]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[19]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[19]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[20]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[20]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[21]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[21]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[22]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[22]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[23]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[23]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[24]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[24]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[25]/opit_0_L5Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[25]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[26]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[26]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[27]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[27]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[28]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[28]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[29]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[29]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[30]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[30]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[31]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[31]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[32]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[32]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[33]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[33]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[34]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[34]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[35]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[35]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[36]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[36]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[37]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[37]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[38]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[38]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[39]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[39]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[40]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[40]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[41]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[41]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[42]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[42]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[43]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[43]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[44]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[44]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[45]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[45]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[46]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[46]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[47]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[47]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[7][0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[7][0]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[7][1]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[7][1]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[18][0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[18][0]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[18][1]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) @@ -105625,22 +105377,22 @@ udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[18][2]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[18][3]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[18][3]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[18][4]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[18][4]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[18][5]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[18][5]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[18][6]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[18][6]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[18][7]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[18][7]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[19][0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[19][0]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[19][1]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) @@ -105649,46 +105401,46 @@ udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[19][2]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[19][3]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[19][3]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[19][4]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[19][4]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[19][5]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[19][5]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[19][6]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[19][6]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[19][7]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[19][7]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[20][0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[20][0]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[20][1]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[20][2]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[20][2]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[20][3]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[20][3]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[20][4]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[20][4]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[20][5]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[20][5]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[20][6]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[20][6]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[20][7]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[20][7]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[21][0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[21][0]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[21][1]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) @@ -105697,46 +105449,46 @@ udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[21][2]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[21][3]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[21][3]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[21][4]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[21][4]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[21][5]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[21][5]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[21][6]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[21][6]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[21][7]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[21][7]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[22][0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[22][0]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[22][1]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[22][2]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[22][2]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[22][3]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[22][3]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[22][4]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[22][4]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[22][5]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[22][5]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[22][6]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[22][6]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[22][7]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[22][7]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[23][0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[23][0]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[23][1]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) @@ -105745,22 +105497,22 @@ udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[23][2]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[23][3]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[23][3]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[23][4]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[23][4]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[23][5]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[23][5]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[23][6]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[23][6]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[23][7]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[23][7]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][0]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][1]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) @@ -105769,22 +105521,22 @@ udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][2]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][3]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][3]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][4]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][4]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][5]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][5]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][6]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][6]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][7]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][7]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][0]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][1]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) @@ -105793,22 +105545,22 @@ udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][2]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][3]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][3]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][4]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][4]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][5]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][5]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][6]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][6]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][7]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][7]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[26][0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[26][0]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[26][1]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) @@ -105817,22 +105569,22 @@ udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[26][2]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[26][3]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[26][3]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[26][4]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[26][4]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[26][5]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[26][6]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[26][6]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[26][7]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[26][7]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][0]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][1]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) @@ -105841,40 +105593,40 @@ udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][2]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][3]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][3]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][4]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][4]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][5]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][6]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][6]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][7]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][7]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[0]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[0]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[1]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[1]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[2]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[2]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[3]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[3]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[4]/opit_0_A2Q1/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[4]/opit_0_A2Q1/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[5]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cnt[5]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/crc_clr/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/crc_clr/opit_0/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/crc_en/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) @@ -105889,10 +105641,10 @@ udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cur_state_reg[2]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cur_state_reg[3]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cur_state_reg[3]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cur_state_reg[4]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/cur_state_reg[4]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/data_cnt[0]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) @@ -105910,7 +105662,7 @@ udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/data_cnt[4]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/gmii_txd_data[0]/opit_0_MUX4TO1Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/gmii_txd_data[0]/opit_0_MUX4TO1Q/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/gmii_txd_data[1]/opit_0_MUX4TO1Q/CLK (5.760, 6.846, 5.808, 6.916) @@ -105919,49 +105671,49 @@ udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/gmii_txd_data[2]/opit_0_MUX4TO1Q/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/gmii_txd_data[3]/opit_0_MUX4TO1Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/gmii_txd_data[3]/opit_0_MUX4TO1Q/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/gmii_txd_data[4]/opit_0_MUX4TO1Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/gmii_txd_data[4]/opit_0_MUX4TO1Q/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/gmii_txd_data[5]/opit_0_MUX4TO1Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/gmii_txd_data[5]/opit_0_MUX4TO1Q/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/gmii_txd_data[6]/opit_0_MUX4TO1Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/gmii_txd_data[6]/opit_0_MUX4TO1Q/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/gmii_txd_data[7]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/gmii_txd_data[7]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/gmii_txd_valid/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/gmii_txd_valid/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/skip_en/opit_0_MUX4TO1Q/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/tx_done_t/opit_0_MUX4TO1Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/tx_done_t/opit_0_MUX4TO1Q/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/tx_en_d0/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/tx_en_d0/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/tx_en_d1/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/tx_en_d1/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/tx_en_d2/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/tx_en_d2/opit_0/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[0]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[1]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[1]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[2]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[2]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[3]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[3]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[4]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) @@ -105970,7 +105722,7 @@ udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[5]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[6]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[6]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[7]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) @@ -105979,13 +105731,13 @@ udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[8]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[9]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[9]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[10]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[10]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[11]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[11]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[12]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) @@ -106003,43 +105755,43 @@ udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[16]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[17]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[17]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[18]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[18]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[19]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[19]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[20]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[21]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[21]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[22]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[23]/opit_0_L5Q/CLK (5.760, 6.846, 5.808, 6.916) + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[23]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[24]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[25]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[25]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[26]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[27]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[27]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[28]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[29]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[29]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[30]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) @@ -106048,70 +105800,70 @@ udp_osd_inst/eth_udp_inst/u_arp/u_crc32_d8/crc_data[31]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_eth_ctrl/arp_rx_flag/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_eth_ctrl/arp_rx_flag/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_eth_ctrl/arp_tx_en/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_eth_ctrl/arp_tx_en/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[0]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[0]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[1]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[1]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[2]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[2]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[3]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[3]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[4]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[4]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[5]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[5]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[6]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[6]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[7]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_data[7]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_valid/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_eth_ctrl/gmii_txd_valid/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_eth_ctrl/icmp_tx_req_d0/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_eth_ctrl/icmp_tx_req_d0/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_eth_ctrl/protocol_sw_reg[0]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_eth_ctrl/protocol_sw_reg[0]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[0]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[1]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[1]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[2]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[2]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[3]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[3]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[4]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[4]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[5]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[5]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[6]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[6]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[7]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[7]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_en/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_en/opit_0/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_ctl_in/gateigddr_IOL/SYSCLK (5.760, 6.846, 5.808, 6.916) @@ -106141,7 +105893,7 @@ udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_rxd_data[7]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_rxd_valid/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_rxd_valid/opit_0/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gtp_outbuft1/opit_1_IOL/SYSCLK (5.760, 6.846, 5.808, 6.916) @@ -106174,100 +105926,100 @@ udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_tx_data[3].gtp_outbuft1/opit_1_IOL/SYSCLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[0]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[0]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[1]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[1]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[2]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[2]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[3]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[3]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[4]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[4]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[5]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[5]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[6]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[6]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[7]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[7]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[8]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[8]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[9]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[9]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[10]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[10]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[11]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[11]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[12]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[12]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[13]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[13]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[14]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[14]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[15]/opit_0_L5Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[15]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[16]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[16]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[17]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[17]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[18]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[18]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[19]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[19]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[20]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[20]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[21]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[21]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[22]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[22]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[23]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[23]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[24]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[24]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[25]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[25]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[26]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[26]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[27]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[27]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[28]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[28]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[29]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[29]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[30]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[30]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[31]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_crc32_d8/crc_data[31]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt[0]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) @@ -106285,25 +106037,25 @@ udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt[4]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[0]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[0]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[1]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[1]/opit_0_L5Q/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[2]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[2]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[3]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[3]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[4]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[4]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[5]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[5]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[6]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg[6]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) @@ -106378,13 +106130,13 @@ udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[23]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[0]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[1]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[2]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[2]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[3]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) @@ -106396,19 +106148,19 @@ udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[5]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[6]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[6]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[7]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[8]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[8]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[9]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[10]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[10]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[11]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) @@ -106420,19 +106172,19 @@ udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[13]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[14]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[14]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[15]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[16]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[16]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[17]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[18]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[18]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[19]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) @@ -106450,13 +106202,13 @@ udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[23]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[24]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[24]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[25]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[26]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[26]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[27]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) @@ -106498,13 +106250,13 @@ udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[39]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[40]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[40]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[41]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[42]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[42]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_mac[43]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) @@ -106525,229 +106277,229 @@ udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/error_en/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/eth_type[8]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/eth_type[8]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/eth_type[9]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/eth_type[9]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/eth_type[10]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/eth_type[10]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/eth_type[11]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/eth_type[11]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/eth_type[12]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/eth_type[12]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/eth_type[13]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/eth_type[13]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/eth_type[14]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/eth_type[14]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/eth_type[15]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/eth_type[15]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[0]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[1]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[1]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[2]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[2]/opit_0_L5Q/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[4]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[4]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[6]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[6]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[8]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[8]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[10]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[10]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[12]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[12]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[14]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[14]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[15]/opit_0_AQ/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[15]/opit_0_AQ/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[0]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[1]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[1]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[2]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[2]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[3]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[3]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[4]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[4]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[5]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[5]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[6]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[6]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[7]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[7]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[8]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[8]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[9]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[9]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[10]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[10]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[11]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[11]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[12]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[12]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[13]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[13]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[14]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[14]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[15]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_id[15]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[0]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[0]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[2]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[2]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[4]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[4]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[6]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[6]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[8]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[8]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[10]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[10]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[12]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[12]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[14]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[14]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[15]/opit_0_AQ_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_cnt[15]/opit_0_AQ_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_data_d0[0]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_data_d0[0]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_data_d0[1]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_data_d0[1]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_data_d0[2]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_data_d0[2]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_data_d0[3]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_data_d0[3]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_data_d0[4]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_data_d0[4]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_data_d0[5]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_data_d0[5]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_data_d0[6]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_data_d0[6]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_data_d0[7]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_rx_data_d0[7]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[0]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[1]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[1]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[2]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[2]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[3]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[3]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[4]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[4]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[5]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[5]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[6]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[6]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[7]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[7]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[8]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[8]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[9]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[9]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[10]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[10]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[11]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[11]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[12]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[12]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[13]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[13]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[14]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[14]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[15]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_seq[15]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_type[0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_type[0]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_type[1]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_type[1]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_type[2]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_type[2]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_type[3]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_type[3]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_type[4]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_type[4]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_type[5]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_type[5]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_type[6]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_type[6]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_type[7]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_type[7]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/ip_head_byte_num[2]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) @@ -106762,148 +106514,148 @@ udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/ip_head_byte_num[5]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[0]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[1]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[1]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[2]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[2]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[3]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[3]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[4]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[4]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[5]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[5]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[6]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[6]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[7]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[7]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[8]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[8]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[9]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[9]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[10]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[10]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[11]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[11]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[12]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[12]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[13]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[13]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[14]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[14]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[15]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_byte_num[15]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_data[0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_data[0]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_data[1]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_data[1]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_data[2]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_data[2]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_data[3]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_data[3]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_data[4]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_data[4]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_data[5]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_data[5]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_data[6]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_data[6]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_data[7]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_data[7]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_en/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_en/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_pkt_done/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/rec_pkt_done/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[0]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[1]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[1]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[2]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[2]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[3]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[3]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[4]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[4]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[5]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[5]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[6]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[6]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[7]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[7]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[8]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[8]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[9]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[9]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[10]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[10]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[11]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[11]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[12]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[12]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[13]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[13]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[14]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[14]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[15]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[15]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[16]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[16]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[17]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[17]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[18]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[18]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[19]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[19]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[20]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[20]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[21]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[21]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[22]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) @@ -106936,76 +106688,76 @@ udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum[31]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[0]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[0]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[1]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[1]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[2]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[2]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[3]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[3]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[4]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[4]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[5]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[5]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[6]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[6]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[7]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[7]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[8]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[8]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[9]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[9]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[10]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[10]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[11]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[11]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[12]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[12]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[13]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[13]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[14]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[14]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[15]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[15]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[16]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[16]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[17]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[17]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[18]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[18]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[19]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[19]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[20]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[20]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[21]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[21]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[22]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[22]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[23]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[23]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[24]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) @@ -107032,115 +106784,115 @@ udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/reply_checksum_add[31]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/skip_en/opit_0_MUX4TO1Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/skip_en/opit_0_MUX4TO1Q/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[0]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[1]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[1]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[2]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[2]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[3]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[3]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[4]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[4]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[5]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[5]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[6]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[6]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[7]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[7]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[8]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[8]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[9]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[9]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[10]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[10]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[11]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[11]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[12]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[12]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[13]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[13]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[14]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[14]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[15]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[15]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer[1]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer[1]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer[3]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer[3]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer[5]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer[5]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer[7]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer[7]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer[9]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer[9]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer[11]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer[11]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer[13]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer[13]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer[15]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer[15]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer[17]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer[17]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer[19]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer[19]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[1]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[1]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[3]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[3]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[5]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[5]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[7]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[7]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[9]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[9]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[11]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[11]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[13]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[13]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[15]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[15]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[17]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[17]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[19]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[19]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[21]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) @@ -107161,745 +106913,745 @@ udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer_icmp[31]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cnt[0]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cnt[0]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cnt[1]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cnt[1]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cnt[2]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cnt[2]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cnt[3]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cnt[3]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cnt[4]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cnt[4]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/crc_clr/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/crc_clr/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/crc_en/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/crc_en/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[0]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[0]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[1]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[1]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[2]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[2]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[3]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[3]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[4]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[4]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[5]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[5]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[6]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[6]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[7]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg[7]/opit_0_L5Q/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[0]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[0]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[2]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[2]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[4]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[4]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[6]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[6]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[8]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[8]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[10]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[10]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[12]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[12]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[14]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[14]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[15]/opit_0_AQ_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[15]/opit_0_AQ_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[0][0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[0][0]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[0][1]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[0][1]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[0][2]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[0][2]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[0][3]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[0][3]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[0][4]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[0][4]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[0][5]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[0][5]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[0][6]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[0][6]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[0][7]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[0][7]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[1][0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[1][0]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[1][1]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[1][1]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[1][2]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[1][2]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[1][3]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[1][3]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[1][4]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[1][4]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[1][5]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[1][5]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[1][6]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[1][6]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[1][7]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[1][7]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[2][0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[2][0]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[2][1]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[2][1]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[2][2]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[2][2]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[2][3]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[2][3]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[2][4]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[2][4]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[2][5]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[2][5]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[2][6]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[2][6]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[2][7]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[2][7]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[3][0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[3][0]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[3][1]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[3][1]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[3][2]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[3][2]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[3][3]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[3][3]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[3][4]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[3][4]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[3][5]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[3][5]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[3][6]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[3][6]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[3][7]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[3][7]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[4][0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[4][0]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[4][1]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[4][1]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[4][2]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[4][2]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[4][3]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[4][3]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[4][4]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[4][4]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[4][5]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[4][5]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[4][6]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[4][6]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[4][7]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[4][7]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[5][0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[5][0]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[5][1]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[5][1]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[5][2]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[5][2]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[5][3]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[5][3]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[5][4]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[5][4]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[5][5]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[5][5]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[5][6]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[5][6]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[5][7]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[5][7]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/gmii_txd_data[0]/opit_0_MUX4TO1Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/gmii_txd_data[0]/opit_0_MUX4TO1Q/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/gmii_txd_data[1]/opit_0_MUX4TO1Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/gmii_txd_data[1]/opit_0_MUX4TO1Q/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/gmii_txd_data[2]/opit_0_MUX4TO1Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/gmii_txd_data[2]/opit_0_MUX4TO1Q/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/gmii_txd_data[3]/opit_0_MUX4TO1Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/gmii_txd_data[3]/opit_0_MUX4TO1Q/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/gmii_txd_data[4]/opit_0_MUX4TO1Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/gmii_txd_data[4]/opit_0_MUX4TO1Q/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/gmii_txd_data[5]/opit_0_MUX4TO1Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/gmii_txd_data[5]/opit_0_MUX4TO1Q/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/gmii_txd_data[6]/opit_0_MUX4TO1Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/gmii_txd_data[6]/opit_0_MUX4TO1Q/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/gmii_txd_data[7]/opit_0_MUX4TO1Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/gmii_txd_data[7]/opit_0_MUX4TO1Q/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/gmii_txd_valid/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/gmii_txd_valid/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][0]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][1]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][1]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][2]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][2]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][3]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][3]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][4]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][4]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][5]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][5]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][6]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][6]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][7]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][7]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][8]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][8]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][9]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][9]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][10]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][10]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][11]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][11]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][12]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][12]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][13]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][13]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][14]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][14]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][15]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[0][15]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][16]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][16]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][18]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][18]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][20]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][20]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][22]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][22]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][24]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][24]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][26]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][26]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][28]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][28]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][30]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][30]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][31]/opit_0_AQ_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[1][31]/opit_0_AQ/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][0]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][0]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][1]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][1]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][2]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][2]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][3]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][3]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][4]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][4]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][5]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][5]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][6]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][6]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][7]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][7]/opit_0_L5Q/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][8]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][8]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][9]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][9]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][10]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][10]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][11]/opit_0_L5Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][11]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][12]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][12]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][13]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][13]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][14]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][14]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][15]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[2][15]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][0]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][1]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][1]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][2]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][2]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][3]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][3]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][4]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][4]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][5]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][5]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][6]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][6]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][7]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][7]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][8]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][8]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][9]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][9]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][10]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][10]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][11]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][11]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][12]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][12]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][13]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][13]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][14]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][14]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][15]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][15]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][16]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][16]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][17]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][17]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][18]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][18]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][19]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][19]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][20]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][20]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][21]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][21]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][22]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][22]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][23]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][23]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][24]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][24]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][25]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][25]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][26]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][26]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][27]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][27]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][28]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][28]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][29]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][29]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][30]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][30]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][31]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[4][31]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][0]/opit_0_L5Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][0]/opit_0_L5Q/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][1]/opit_0_L5Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][1]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][2]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][2]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][3]/opit_0_L5Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][3]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][4]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][4]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][5]/opit_0_L5Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][5]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][6]/opit_0_L5Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][6]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][7]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][7]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][8]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][8]/opit_0_L5Q/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][9]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][9]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][10]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][10]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][11]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][11]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][12]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][12]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][13]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][13]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][14]/opit_0_L5Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][14]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][15]/opit_0_L5Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[5][15]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][0]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][1]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][1]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][2]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][2]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][3]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][3]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][4]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][4]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][5]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][5]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][6]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][6]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][7]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][7]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][8]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][8]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][9]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][9]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][10]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][10]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][11]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][11]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][12]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][12]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][13]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][13]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][14]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][14]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][15]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][15]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][16]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][16]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][17]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][17]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][18]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][18]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][19]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][19]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][20]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][20]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][21]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][21]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][22]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][22]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][23]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][23]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][24]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][24]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][25]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][25]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][26]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][26]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][27]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][27]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][28]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][28]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][29]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][29]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][30]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][30]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][31]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/ip_head[6][31]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/real_add_cnt[0]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/real_add_cnt[0]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/real_add_cnt[1]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/real_add_cnt[1]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/real_add_cnt[2]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/real_add_cnt[2]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/real_add_cnt[3]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/real_add_cnt[3]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/real_add_cnt[4]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/real_add_cnt[4]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/skip_en/opit_0_MUX4TO1Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/skip_en/opit_0_MUX4TO1Q/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/start_en_d0/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/start_en_d0/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/start_en_d1/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/start_en_d1/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/start_en_d2/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/start_en_d2/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[0]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[1]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[1]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[2]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[2]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[4]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[4]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[6]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[6]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[8]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[8]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[10]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[10]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[12]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[12]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[14]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[14]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[15]/opit_0_AQ/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/total_num[15]/opit_0_AQ/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/trig_tx_en/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/trig_tx_en/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_bit_sel[0]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_bit_sel[0]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_bit_sel[1]/opit_0_MUX4TO1Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_bit_sel[1]/opit_0_MUX4TO1Q/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[2]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[2]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[3]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[3]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[4]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[4]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[5]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[5]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[6]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[6]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[7]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[7]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[8]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[8]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[9]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[9]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[10]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[10]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[11]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[11]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[12]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[12]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[13]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[13]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[14]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[14]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[15]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[15]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_done_t/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_done_t/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_req/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_req/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt[0]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt[0]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt[1]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt[2]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt[2]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt[3]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt[3]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt[4]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt[4]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[0]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[1]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[1]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[2]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) @@ -107911,13 +107663,13 @@ udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[4]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[5]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[5]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[6]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg[6]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[0]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[1]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) @@ -107929,121 +107681,121 @@ udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[3]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[5]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[5]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[7]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[7]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[9]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[9]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[11]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[11]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[13]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[13]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[15]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[15]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_cnt[0]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_cnt[0]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_cnt[2]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_cnt[2]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_cnt[4]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_cnt[4]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_cnt[6]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_cnt[6]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_cnt[8]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_cnt[8]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_cnt[10]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_cnt[10]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_cnt[12]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_cnt[12]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_cnt[14]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_cnt[14]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_cnt[15]/opit_0_AQ_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_cnt[15]/opit_0_AQ_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[0]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[1]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[1]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[2]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[2]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[3]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[3]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[4]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[4]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[5]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[5]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[6]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[6]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[7]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[7]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[8]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[8]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[9]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[9]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[10]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[10]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[11]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[11]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[12]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[12]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[13]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[13]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[14]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[14]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[15]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[15]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[16]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[16]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[17]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[17]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[18]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[18]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[19]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[19]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[20]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[20]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[21]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[21]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[22]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[22]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[23]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[23]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_mac[0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) @@ -108217,7 +107969,7 @@ udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/eth_type[15]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[0]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[0]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[1]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) @@ -108253,16 +108005,16 @@ udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[11]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[12]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[12]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[13]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[13]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[14]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[14]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[15]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[15]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_data[0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) @@ -108283,16 +108035,16 @@ udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_data[5]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_data[6]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_data[6]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_data[7]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_en/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_en/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_pkt_done/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_pkt_done/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_pkt_start/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) @@ -108325,235 +108077,235 @@ udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[7]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[8]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[8]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[9]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[9]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[10]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[10]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[11]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[11]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[12]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[12]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[13]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[13]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[14]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[14]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[15]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_byte_num[15]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[0]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[1]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[1]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[2]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[2]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[3]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[3]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[4]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[4]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[5]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[5]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[6]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[6]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[7]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[7]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[8]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[8]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[9]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[9]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[10]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[10]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[11]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[11]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[12]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[12]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[13]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[13]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[14]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[14]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[15]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[15]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_done_cdc/in_req/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_done_cdc/in_req/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_done_cdc/out_ack_sync0/opit_0_inv/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_done_cdc/out_ack_sync0/opit_0_inv/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_done_cdc/out_ack_sync1/opit_0_inv/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_done_cdc/out_ack_sync1/opit_0_inv/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/opit_0_inv_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/opit_0_inv_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[2]/opit_0_inv_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[2]/opit_0_inv_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[4]/opit_0_inv_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[4]/opit_0_inv_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[6]/opit_0_inv_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[6]/opit_0_inv_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[8]/opit_0_inv_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[8]/opit_0_inv_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[10]/opit_0_inv_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[10]/opit_0_inv_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_MUX4TO1Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/opit_0_MUX4TO1Q/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_MUX4TO1Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/opit_0_MUX4TO1Q/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_MUX4TO1Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/opit_0_MUX4TO1Q/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_MUX4TO1Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_MUX4TO1Q/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_MUX4TO1Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_MUX4TO1Q/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_MUX4TO1Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/opit_0_MUX4TO1Q/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_MUX4TO1Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_MUX4TO1Q/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_MUX4TO1Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/opit_0_MUX4TO1Q/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_MUX4TO1Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/opit_0_MUX4TO1Q/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[10]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[10]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[11]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[11]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[0]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[0]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[2]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[5]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[5]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[6]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[6]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[8]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[8]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[11]/opit_0/CLK (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[11]/opit_0/CLK (5.760, 6.846, 5.808, 6.916) - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.650, 6.734, 5.707, 6.813) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] (5.760, 6.846, 5.808, 6.916) udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_start_i_ff/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) @@ -108562,16 +108314,19 @@ udp_wr_mem_inst/data_count[0]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - udp_wr_mem_inst/data_count[1]/opit_0_A2Q1/CLK (5.650, 6.734, 5.707, 6.813) + udp_wr_mem_inst/data_count[1]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - udp_wr_mem_inst/data_count[3]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_wr_mem_inst/data_count[2]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - udp_wr_mem_inst/data_count[5]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_wr_mem_inst/data_count[4]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) - udp_wr_mem_inst/data_count[7]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_wr_mem_inst/data_count[6]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + + + udp_wr_mem_inst/data_count[7]/opit_0_AQ_perm/CLK (5.650, 6.734, 5.707, 6.813) udp_wr_mem_inst/flags[0]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) @@ -108598,7 +108353,7 @@ udp_wr_mem_inst/flags[7]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - udp_wr_mem_inst/flags[8]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_wr_mem_inst/flags[8]/opit_0_L5Q/CLK (5.650, 6.734, 5.707, 6.813) udp_wr_mem_inst/flags[9]/opit_0_L5Q/CLK (5.650, 6.734, 5.707, 6.813) @@ -108607,7 +108362,7 @@ udp_wr_mem_inst/flags[10]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - udp_wr_mem_inst/flags[11]/opit_0_L5Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_wr_mem_inst/flags[11]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) udp_wr_mem_inst/flags[12]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) @@ -108622,19 +108377,19 @@ udp_wr_mem_inst/flags[15]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - udp_wr_mem_inst/flags[16]/opit_0_L5Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_wr_mem_inst/flags[16]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) udp_wr_mem_inst/flags[17]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - udp_wr_mem_inst/flags[18]/opit_0_L5Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_wr_mem_inst/flags[18]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) udp_wr_mem_inst/flags[19]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - udp_wr_mem_inst/flags[20]/opit_0_L5Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_wr_mem_inst/flags[20]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) udp_wr_mem_inst/flags[21]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) @@ -108643,10 +108398,10 @@ udp_wr_mem_inst/flags[22]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) - udp_wr_mem_inst/flags[23]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) + udp_wr_mem_inst/flags[23]/opit_0_L5Q/CLK (5.650, 6.734, 5.707, 6.813) - udp_wr_mem_inst/flags[24]/opit_0_L5Q/CLK (5.650, 6.734, 5.707, 6.813) + udp_wr_mem_inst/flags[24]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) udp_wr_mem_inst/index[0]/opit_0_L5Q_perm/CLK (5.650, 6.734, 5.707, 6.813) @@ -109066,16 +108821,16 @@ udp_wr_mem_inst/pkt_data_cnt[7]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) - udp_wr_mem_inst/pkt_data_cnt[9]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_wr_mem_inst/pkt_data_cnt[9]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_wr_mem_inst/pkt_data_cnt[11]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_wr_mem_inst/pkt_data_cnt[11]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_wr_mem_inst/pkt_data_cnt[13]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_wr_mem_inst/pkt_data_cnt[13]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) - udp_wr_mem_inst/pkt_data_cnt[15]/opit_0_A2Q21/CLK (5.650, 6.734, 5.707, 6.813) + udp_wr_mem_inst/pkt_data_cnt[15]/opit_0_A2Q21/CLK (5.760, 6.846, 5.808, 6.916) udp_wr_mem_inst/state_reg[0]/opit_0_MUX4TO1Q/CLK (5.650, 6.734, 5.707, 6.813) @@ -109099,65 +108854,3963 @@ - - - - - - clk_100m (100.00MHZ) (drive 0 loads) (min_rise, max_rise, min_fall, max_fall) - - - clk_1080p60Hz (148.44MHZ) (drive 0 loads) (min_rise, max_rise, min_fall, max_fall) - - - clk_720p60Hz (74.22MHZ) (drive 1635 loads) (min_rise, max_rise, min_fall, max_fall) - - - clk_20k (0.02MHZ) (drive 38 loads) (min_rise, max_rise, min_fall, max_fall) + + + + + + clk_100m (100.00MHZ) (drive 0 loads) (min_rise, max_rise, min_fall, max_fall) + + + clk_1080p60Hz (148.44MHZ) (drive 750 loads) (min_rise, max_rise, min_fall, max_fall) + + + clk_720p60Hz (74.22MHZ) (drive 1635 loads) (min_rise, max_rise, min_fall, max_fall) + + + clk_20k (0.02MHZ) (drive 38 loads) (min_rise, max_rise, min_fall, max_fall) + +
+ + + Slack + Logic Levels + High Fanout + Start Point + End Point + Exception + Launch Clock + Capture Clock + Clock Edges + Clock Skew + Launch Clock Delay + Capture Clock Delay + Clock Pessimism Removal + Requirement + Data delay + Logic delay + Route delay + + + 1.834 + 0 + 8 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[0] + + ioclk1 + ioclk1 + rise-rise + -0.003 + 4.916 + 4.519 + 0.394 + 2.500 + 0.408 + 0.408 (100.0%) + 0.000 (0.0%) + + Path #1: setup slack is 1.834(MET) + +
+ + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk1 (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.504 + 1.578 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.578 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.058 + 1.636 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.478 + 2.114 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.079 + 2.193 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 0.614 + 2.807 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 2.807 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.019 + 3.826 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.094 + 3.920 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 0.682 + 4.602 + + clkout0_wl_0 + + + IOCKGATE_6_188/OUT + td + 0.268 + 4.870 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT + + + + net (fanout=28) + 0.046 + 4.916 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + + + DQSL_6_152/CLK_IO + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + + + DQSL_6_152/IFIFO_RADDR[0] + tco + 0.408 + 5.324 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[0] + + + + net (fanout=8) + 0.000 + 5.324 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [0] + + + IOL_7_162/IFIFO_RADDR[0] + + + + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[0] + +
+ + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk1 (rising edge) + + 2.500 + 2.500 + r + + + + P20 + + 0.000 + 2.500 + r + clk (port) + + + + net (fanout=1) + 0.074 + 2.574 + + clk + + + IOBS_LR_328_209/DIN + td + 1.285 + 3.859 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 3.859 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.038 + 3.897 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.463 + 4.360 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.074 + 4.434 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 0.603 + 5.037 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 5.037 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 0.981 + 6.018 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.089 + 6.107 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 0.669 + 6.776 + + clkout0_wl_0 + + + IOCKGATE_6_188/OUT + td + 0.200 + 6.976 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT + + + + net (fanout=28) + 0.043 + 7.019 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + + + IOL_7_162/CLK_IO + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK + + + clock pessimism + + 0.394 + 7.413 + + + + + clock uncertainty + + -0.150 + 7.263 + + + + + Setup time + + -0.105 + 7.158 + + + +
+
+ +
+ + 1.834 + 0 + 8 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[1] + + ioclk1 + ioclk1 + rise-rise + -0.003 + 4.916 + 4.519 + 0.394 + 2.500 + 0.408 + 0.408 (100.0%) + 0.000 (0.0%) + + Path #2: setup slack is 1.834(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk1 (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.504 + 1.578 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.578 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.058 + 1.636 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.478 + 2.114 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.079 + 2.193 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 0.614 + 2.807 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 2.807 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.019 + 3.826 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.094 + 3.920 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 0.682 + 4.602 + + clkout0_wl_0 + + + IOCKGATE_6_188/OUT + td + 0.268 + 4.870 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT + + + + net (fanout=28) + 0.046 + 4.916 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + + + DQSL_6_152/CLK_IO + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + + + DQSL_6_152/IFIFO_RADDR[1] + tco + 0.408 + 5.324 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[1] + + + + net (fanout=8) + 0.000 + 5.324 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [1] + + + IOL_7_162/IFIFO_RADDR[1] + + + + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[1] + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk1 (rising edge) + + 2.500 + 2.500 + r + + + + P20 + + 0.000 + 2.500 + r + clk (port) + + + + net (fanout=1) + 0.074 + 2.574 + + clk + + + IOBS_LR_328_209/DIN + td + 1.285 + 3.859 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 3.859 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.038 + 3.897 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.463 + 4.360 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.074 + 4.434 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 0.603 + 5.037 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 5.037 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 0.981 + 6.018 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.089 + 6.107 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 0.669 + 6.776 + + clkout0_wl_0 + + + IOCKGATE_6_188/OUT + td + 0.200 + 6.976 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT + + + + net (fanout=28) + 0.043 + 7.019 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + + + IOL_7_162/CLK_IO + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK + + + clock pessimism + + 0.394 + 7.413 + + + + + clock uncertainty + + -0.150 + 7.263 + + + + + Setup time + + -0.105 + 7.158 + + + +
+
+
+
+ + 1.834 + 0 + 8 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[2] + + ioclk1 + ioclk1 + rise-rise + -0.003 + 4.916 + 4.519 + 0.394 + 2.500 + 0.408 + 0.408 (100.0%) + 0.000 (0.0%) + + Path #3: setup slack is 1.834(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk1 (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.504 + 1.578 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.578 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.058 + 1.636 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.478 + 2.114 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.079 + 2.193 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 0.614 + 2.807 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 2.807 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.019 + 3.826 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.094 + 3.920 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 0.682 + 4.602 + + clkout0_wl_0 + + + IOCKGATE_6_188/OUT + td + 0.268 + 4.870 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT + + + + net (fanout=28) + 0.046 + 4.916 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + + + DQSL_6_152/CLK_IO + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + + + DQSL_6_152/IFIFO_RADDR[2] + tco + 0.408 + 5.324 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[2] + + + + net (fanout=8) + 0.000 + 5.324 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [2] + + + IOL_7_162/IFIFO_RADDR[2] + + + + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[2] + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk1 (rising edge) + + 2.500 + 2.500 + r + + + + P20 + + 0.000 + 2.500 + r + clk (port) + + + + net (fanout=1) + 0.074 + 2.574 + + clk + + + IOBS_LR_328_209/DIN + td + 1.285 + 3.859 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 3.859 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.038 + 3.897 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.463 + 4.360 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.074 + 4.434 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 0.603 + 5.037 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 5.037 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 0.981 + 6.018 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.089 + 6.107 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 0.669 + 6.776 + + clkout0_wl_0 + + + IOCKGATE_6_188/OUT + td + 0.200 + 6.976 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT + + + + net (fanout=28) + 0.043 + 7.019 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + + + IOL_7_162/CLK_IO + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK + + + clock pessimism + + 0.394 + 7.413 + + + + + clock uncertainty + + -0.150 + 7.263 + + + + + Setup time + + -0.105 + 7.158 + + + +
+
+
+
+ + 1.834 + 0 + 8 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[0] + + ioclk0 + ioclk0 + rise-rise + -0.003 + 4.916 + 4.519 + 0.394 + 2.500 + 0.408 + 0.408 (100.0%) + 0.000 (0.0%) + + Path #4: setup slack is 1.834(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk0 (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.504 + 1.578 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.578 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.058 + 1.636 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.478 + 2.114 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.079 + 2.193 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 0.614 + 2.807 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 2.807 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.019 + 3.826 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.094 + 3.920 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 0.682 + 4.602 + + clkout0_wl_0 + + + IOCKGATE_6_312/OUT + td + 0.268 + 4.870 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT + + + + net (fanout=11) + 0.046 + 4.916 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + + + DQSL_6_276/CLK_IO + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + + + DQSL_6_276/IFIFO_RADDR[0] + tco + 0.408 + 5.324 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[0] + + + + net (fanout=8) + 0.000 + 5.324 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [0] + + + IOL_7_285/IFIFO_RADDR[0] + + + + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[0] + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk0 (rising edge) + + 2.500 + 2.500 + r + + + + P20 + + 0.000 + 2.500 + r + clk (port) + + + + net (fanout=1) + 0.074 + 2.574 + + clk + + + IOBS_LR_328_209/DIN + td + 1.285 + 3.859 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 3.859 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.038 + 3.897 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.463 + 4.360 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.074 + 4.434 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 0.603 + 5.037 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 5.037 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 0.981 + 6.018 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.089 + 6.107 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 0.669 + 6.776 + + clkout0_wl_0 + + + IOCKGATE_6_312/OUT + td + 0.200 + 6.976 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT + + + + net (fanout=11) + 0.043 + 7.019 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + + + IOL_7_285/CLK_IO + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK + + + clock pessimism + + 0.394 + 7.413 + + + + + clock uncertainty + + -0.150 + 7.263 + + + + + Setup time + + -0.105 + 7.158 + + + +
+
+
+
+ + 1.834 + 0 + 8 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[1] + + ioclk0 + ioclk0 + rise-rise + -0.003 + 4.916 + 4.519 + 0.394 + 2.500 + 0.408 + 0.408 (100.0%) + 0.000 (0.0%) + + Path #5: setup slack is 1.834(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk0 (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.504 + 1.578 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.578 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.058 + 1.636 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.478 + 2.114 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.079 + 2.193 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 0.614 + 2.807 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 2.807 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.019 + 3.826 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.094 + 3.920 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 0.682 + 4.602 + + clkout0_wl_0 + + + IOCKGATE_6_312/OUT + td + 0.268 + 4.870 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT + + + + net (fanout=11) + 0.046 + 4.916 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + + + DQSL_6_276/CLK_IO + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + + + DQSL_6_276/IFIFO_RADDR[1] + tco + 0.408 + 5.324 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[1] + + + + net (fanout=8) + 0.000 + 5.324 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [1] + + + IOL_7_285/IFIFO_RADDR[1] + + + + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[1] + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk0 (rising edge) + + 2.500 + 2.500 + r + + + + P20 + + 0.000 + 2.500 + r + clk (port) + + + + net (fanout=1) + 0.074 + 2.574 + + clk + + + IOBS_LR_328_209/DIN + td + 1.285 + 3.859 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 3.859 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.038 + 3.897 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.463 + 4.360 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.074 + 4.434 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 0.603 + 5.037 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 5.037 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 0.981 + 6.018 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.089 + 6.107 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 0.669 + 6.776 + + clkout0_wl_0 + + + IOCKGATE_6_312/OUT + td + 0.200 + 6.976 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT + + + + net (fanout=11) + 0.043 + 7.019 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + + + IOL_7_285/CLK_IO + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK + + + clock pessimism + + 0.394 + 7.413 + + + + + clock uncertainty + + -0.150 + 7.263 + + + + + Setup time + + -0.105 + 7.158 + + + +
+
+
+
+ + 1.834 + 0 + 8 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[2] + + ioclk0 + ioclk0 + rise-rise + -0.003 + 4.916 + 4.519 + 0.394 + 2.500 + 0.408 + 0.408 (100.0%) + 0.000 (0.0%) + + Path #6: setup slack is 1.834(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk0 (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.504 + 1.578 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.578 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.058 + 1.636 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.478 + 2.114 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.079 + 2.193 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 0.614 + 2.807 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 2.807 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.019 + 3.826 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.094 + 3.920 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 0.682 + 4.602 + + clkout0_wl_0 + + + IOCKGATE_6_312/OUT + td + 0.268 + 4.870 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT + + + + net (fanout=11) + 0.046 + 4.916 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + + + DQSL_6_276/CLK_IO + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + + + DQSL_6_276/IFIFO_RADDR[2] + tco + 0.408 + 5.324 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[2] + + + + net (fanout=8) + 0.000 + 5.324 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [2] + + + IOL_7_285/IFIFO_RADDR[2] + + + + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[2] + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk0 (rising edge) + + 2.500 + 2.500 + r + + + + P20 + + 0.000 + 2.500 + r + clk (port) + + + + net (fanout=1) + 0.074 + 2.574 + + clk + + + IOBS_LR_328_209/DIN + td + 1.285 + 3.859 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 3.859 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.038 + 3.897 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.463 + 4.360 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.074 + 4.434 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 0.603 + 5.037 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 5.037 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 0.981 + 6.018 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.089 + 6.107 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 0.669 + 6.776 + + clkout0_wl_0 + + + IOCKGATE_6_312/OUT + td + 0.200 + 6.976 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT + + + + net (fanout=11) + 0.043 + 7.019 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + + + IOL_7_285/CLK_IO + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK + + + clock pessimism + + 0.394 + 7.413 + + + + + clock uncertainty + + -0.150 + 7.263 + + + + + Setup time + + -0.105 + 7.158 + + + +
+
+
+
+ + 2.129 + 5 + 11 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[16]/opit_0_inv_L5Q_perm/CE + + clk_200m + clk_200m + rise-rise + -0.001 + 3.732 + 3.432 + 0.299 + 5.000 + 2.144 + 1.464 (68.3%) + 0.680 (31.7%) + + Path #7: setup slack is 2.129(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_200m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.504 + 1.578 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.578 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.058 + 1.636 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.478 + 2.114 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.079 + 2.193 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 0.614 + 2.807 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 2.807 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 0.925 + 3.732 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + CLMA_90_197/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK + + + CLMA_90_197/Q1 + tco + 0.223 + 3.955 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/Q + + + + net (fanout=2) + 0.259 + 4.214 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt [15] + + + CLMS_94_197/Y0 + td + 0.376 + 4.590 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_33/gateop_perm/Z + + + + net (fanout=2) + 0.075 + 4.665 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107154 + + + CLMA_94_196/Y2 + td + 0.379 + 5.044 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_36/gateop_perm/Z + + + + net (fanout=1) + 0.067 + 5.111 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107157 + + + CLMA_94_196/Y3 + td + 0.222 + 5.333 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43_3/gateop_perm/Z + + + + net (fanout=11) + 0.279 + 5.612 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43 + + + CLMA_90_185/CECO + td + 0.132 + 5.744 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[8]/opit_0_inv_L5Q_perm/CEOUT + + + + net (fanout=4) + 0.000 + 5.744 + + ntR1851 + + + CLMA_90_193/CECO + td + 0.132 + 5.876 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[11]/opit_0_inv_L5Q_perm/CEOUT + + + + net (fanout=4) + 0.000 + 5.876 + + ntR1850 + + + CLMA_90_197/CECI + + + + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[16]/opit_0_inv_L5Q_perm/CE + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_200m (rising edge) + + 5.000 + 5.000 + r + + + + P20 + + 0.000 + 5.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 5.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.285 + 6.359 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 6.359 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.038 + 6.397 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.463 + 6.860 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.074 + 6.934 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 0.603 + 7.537 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 7.537 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 0.895 + 8.432 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + CLMA_90_197/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[16]/opit_0_inv_L5Q_perm/CLK + + + clock pessimism + + 0.299 + 8.731 + + + + + clock uncertainty + + -0.150 + 8.581 + + + + + Setup time + + -0.576 + 8.005 + + + +
+
+
+
+ + 2.129 + 5 + 11 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[17]/opit_0_inv_L5Q_perm/CE + + clk_200m + clk_200m + rise-rise + -0.001 + 3.732 + 3.432 + 0.299 + 5.000 + 2.144 + 1.464 (68.3%) + 0.680 (31.7%) + + Path #8: setup slack is 2.129(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_200m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.504 + 1.578 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.578 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.058 + 1.636 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.478 + 2.114 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.079 + 2.193 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 0.614 + 2.807 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 2.807 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 0.925 + 3.732 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + CLMA_90_197/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK + + + CLMA_90_197/Q1 + tco + 0.223 + 3.955 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/Q + + + + net (fanout=2) + 0.259 + 4.214 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt [15] + + + CLMS_94_197/Y0 + td + 0.376 + 4.590 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_33/gateop_perm/Z + + + + net (fanout=2) + 0.075 + 4.665 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107154 + + + CLMA_94_196/Y2 + td + 0.379 + 5.044 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_36/gateop_perm/Z + + + + net (fanout=1) + 0.067 + 5.111 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107157 + + + CLMA_94_196/Y3 + td + 0.222 + 5.333 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43_3/gateop_perm/Z + + + + net (fanout=11) + 0.279 + 5.612 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43 + + + CLMA_90_185/CECO + td + 0.132 + 5.744 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[8]/opit_0_inv_L5Q_perm/CEOUT + + + + net (fanout=4) + 0.000 + 5.744 + + ntR1851 + + + CLMA_90_193/CECO + td + 0.132 + 5.876 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[11]/opit_0_inv_L5Q_perm/CEOUT + + + + net (fanout=4) + 0.000 + 5.876 + + ntR1850 + + + CLMA_90_197/CECI + + + + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[17]/opit_0_inv_L5Q_perm/CE + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_200m (rising edge) + + 5.000 + 5.000 + r + + + + P20 + + 0.000 + 5.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 5.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.285 + 6.359 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 6.359 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.038 + 6.397 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.463 + 6.860 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.074 + 6.934 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 0.603 + 7.537 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 7.537 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 0.895 + 8.432 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + CLMA_90_197/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[17]/opit_0_inv_L5Q_perm/CLK + + + clock pessimism + + 0.299 + 8.731 + + + + + clock uncertainty + + -0.150 + 8.581 + + + + + Setup time + + -0.576 + 8.005 + + + +
+
+
+
+ + 2.129 + 5 + 11 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[18]/opit_0_inv_L5Q_perm/CE + + clk_200m + clk_200m + rise-rise + -0.001 + 3.732 + 3.432 + 0.299 + 5.000 + 2.144 + 1.464 (68.3%) + 0.680 (31.7%) + + Path #9: setup slack is 2.129(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_200m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.504 + 1.578 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.578 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.058 + 1.636 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.478 + 2.114 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.079 + 2.193 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 0.614 + 2.807 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 2.807 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 0.925 + 3.732 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + CLMA_90_197/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/CLK + + + CLMA_90_197/Q1 + tco + 0.223 + 3.955 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/opit_0_inv_L5Q_perm/Q + + + + net (fanout=2) + 0.259 + 4.214 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt [15] + + + CLMS_94_197/Y0 + td + 0.376 + 4.590 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_33/gateop_perm/Z + + + + net (fanout=2) + 0.075 + 4.665 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107154 + + + CLMA_94_196/Y2 + td + 0.379 + 5.044 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_36/gateop_perm/Z + + + + net (fanout=1) + 0.067 + 5.111 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107157 + + + CLMA_94_196/Y3 + td + 0.222 + 5.333 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43_3/gateop_perm/Z + + + + net (fanout=11) + 0.279 + 5.612 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43 + + + CLMA_90_185/CECO + td + 0.132 + 5.744 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[8]/opit_0_inv_L5Q_perm/CEOUT + + + + net (fanout=4) + 0.000 + 5.744 + + ntR1851 + + + CLMA_90_193/CECO + td + 0.132 + 5.876 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[11]/opit_0_inv_L5Q_perm/CEOUT + + + + net (fanout=4) + 0.000 + 5.876 + + ntR1850 + + + CLMA_90_197/CECI + + + + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[18]/opit_0_inv_L5Q_perm/CE + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_200m (rising edge) + + 5.000 + 5.000 + r + + + + P20 + + 0.000 + 5.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 5.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.285 + 6.359 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 6.359 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.038 + 6.397 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.463 + 6.860 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.074 + 6.934 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 0.603 + 7.537 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 7.537 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 0.895 + 8.432 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + CLMA_90_197/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[18]/opit_0_inv_L5Q_perm/CLK + + + clock pessimism + + 0.299 + 8.731 + + + + + clock uncertainty + + -0.150 + 8.581 + + + + + Setup time + + -0.576 + 8.005 + + + +
+
+
+
+ + 2.488 + 0 + 3 + u_zoom_image/mult_fra1_0/N2/gopapm/CLK + u_zoom_image/mult_image_g1_0/N2/gopapm/X[3] + + clk_1080p60Hz + clk_1080p60Hz + rise-rise + -0.142 + 5.994 + 5.520 + 0.332 + 6.736 + 2.225 + 0.822 (36.9%) + 1.403 (63.1%) + + Path #10: setup slack is 2.488(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_1080p60Hz (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.504 + 1.578 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.578 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.058 + 1.636 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.478 + 2.114 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.083 + 2.197 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 0.614 + 2.811 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 2.811 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.131 + 3.942 + + ntR3950 + + + PLL_158_303/CLK_OUT0 + td + 0.083 + 4.025 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=1) + 0.932 + 4.957 + + zoom_clk + + + USCM_84_118/CLK_USCM + td + 0.000 + 4.957 + r + clkbufg_3/gopclkbufg/CLKOUT + + + + net (fanout=750) + 1.037 + 5.994 + + ntclkbufg_3 + + + APM_206_264/CLK + + + + r + u_zoom_image/mult_fra1_0/N2/gopapm/CLK + + + APM_206_264/P[34] + tco + 0.822 + 6.816 + f + u_zoom_image/mult_fra1_0/N2/gopapm/P[10] + + + + net (fanout=3) + 1.403 + 8.219 + + u_zoom_image/coe_mult_p1_0 [10] + + + APM_206_140/X[3] + + + + f + u_zoom_image/mult_image_g1_0/N2/gopapm/X[3] + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_1080p60Hz (rising edge) + + 6.736 + 6.736 + r + + + + P20 + + 0.000 + 6.736 + r + clk (port) + + + + net (fanout=1) + 0.074 + 6.810 + + clk + + + IOBS_LR_328_209/DIN + td + 1.285 + 8.095 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 8.095 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.038 + 8.133 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.463 + 8.596 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.078 + 8.674 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 0.603 + 9.277 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 9.277 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.091 + 10.368 + + ntR3950 + + + PLL_158_303/CLK_OUT0 + td + 0.078 + 10.446 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=1) + 0.915 + 11.361 + + zoom_clk + + + USCM_84_118/CLK_USCM + td + 0.000 + 11.361 + r + clkbufg_3/gopclkbufg/CLKOUT + + + + net (fanout=750) + 0.895 + 12.256 + + ntclkbufg_3 + + + APM_206_140/CLK + + + + r + u_zoom_image/mult_image_g1_0/N2/gopapm/CLK + + + clock pessimism + + 0.332 + 12.588 + + + + + clock uncertainty + + -0.150 + 12.438 + + + + + Setup time + + -1.731 + 10.707 + + + +
+
+
+
+ + 2.493 + 0 + 3 + u_zoom_image/mult_fra1_0/N2/gopapm/CLK + u_zoom_image/mult_image_g1_0/N2/gopapm/X[0] + + clk_1080p60Hz + clk_1080p60Hz + rise-rise + -0.142 + 5.994 + 5.520 + 0.332 + 6.736 + 2.220 + 0.822 (37.0%) + 1.398 (63.0%) + + Path #11: setup slack is 2.493(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_1080p60Hz (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.504 + 1.578 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.578 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.058 + 1.636 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.478 + 2.114 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.083 + 2.197 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 0.614 + 2.811 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 2.811 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.131 + 3.942 + + ntR3950 + + + PLL_158_303/CLK_OUT0 + td + 0.083 + 4.025 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=1) + 0.932 + 4.957 + + zoom_clk + + + USCM_84_118/CLK_USCM + td + 0.000 + 4.957 + r + clkbufg_3/gopclkbufg/CLKOUT + + + + net (fanout=750) + 1.037 + 5.994 + + ntclkbufg_3 + + + APM_206_264/CLK + + + + r + u_zoom_image/mult_fra1_0/N2/gopapm/CLK + + + APM_206_264/P[31] + tco + 0.822 + 6.816 + f + u_zoom_image/mult_fra1_0/N2/gopapm/P[7] + + + + net (fanout=3) + 1.398 + 8.214 + + u_zoom_image/coe_mult_p1_0 [7] + + + APM_206_140/X[0] + + + + f + u_zoom_image/mult_image_g1_0/N2/gopapm/X[0] + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_1080p60Hz (rising edge) + + 6.736 + 6.736 + r + + + + P20 + + 0.000 + 6.736 + r + clk (port) + + + + net (fanout=1) + 0.074 + 6.810 + + clk + + + IOBS_LR_328_209/DIN + td + 1.285 + 8.095 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 8.095 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.038 + 8.133 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.463 + 8.596 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.078 + 8.674 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 0.603 + 9.277 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 9.277 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.091 + 10.368 + + ntR3950 + + + PLL_158_303/CLK_OUT0 + td + 0.078 + 10.446 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=1) + 0.915 + 11.361 + + zoom_clk + + + USCM_84_118/CLK_USCM + td + 0.000 + 11.361 + r + clkbufg_3/gopclkbufg/CLKOUT + + + + net (fanout=750) + 0.895 + 12.256 + + ntclkbufg_3 + + + APM_206_140/CLK + + + + r + u_zoom_image/mult_image_g1_0/N2/gopapm/CLK + + + clock pessimism + + 0.332 + 12.588 + + + + + clock uncertainty + + -0.150 + 12.438 + + + + + Setup time + + -1.731 + 10.707 + + + +
+
+
- - - - Slack - Logic Levels - High Fanout - Start Point - End Point - Exception - Launch Clock - Capture Clock - Clock Edges - Clock Skew - Launch Clock Delay - Capture Clock Delay - Clock Pessimism Removal - Requirement - Data delay - Logic delay - Route delay - - 0.707 + 2.518 0 3 u_zoom_image/mult_fra0_0/N2/gopapm/CLK - u_zoom_image/mult_image_r0_0/N2/gopapm/X[0] + u_zoom_image/mult_image_g0_0/N2/gopapm/X[1] - clk_200m - clk_200m + clk_1080p60Hz + clk_1080p60Hz rise-rise - 0.080 - 3.732 - 3.542 - 0.270 - 5.000 - 2.492 - 0.822 (33.0%) - 1.670 (67.0%) + -0.142 + 5.994 + 5.520 + 0.332 + 6.736 + 2.195 + 0.822 (37.4%) + 1.373 (62.6%) - Path #1: setup slack is 0.707(MET) + Path #12: setup slack is 2.518(MET) -
+
Location Delay Type @@ -109167,129 +112820,591 @@ Logical Resource - Clock clk_200m (rising edge) + Clock clk_1080p60Hz (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.504 + 1.578 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.578 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.058 + 1.636 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.478 + 2.114 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.083 + 2.197 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 0.614 + 2.811 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 2.811 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.131 + 3.942 + + ntR3950 + + + PLL_158_303/CLK_OUT0 + td + 0.083 + 4.025 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=1) + 0.932 + 4.957 + + zoom_clk + + + USCM_84_118/CLK_USCM + td + 0.000 + 4.957 + r + clkbufg_3/gopclkbufg/CLKOUT + + + + net (fanout=750) + 1.037 + 5.994 + + ntclkbufg_3 + + + APM_206_264/CLK + + + + r + u_zoom_image/mult_fra0_0/N2/gopapm/CLK + + + APM_206_264/P[8] + tco + 0.822 + 6.816 + f + u_zoom_image/mult_fra0_0/N2/gopapm/P[8] + + + + net (fanout=3) + 1.373 + 8.189 + + u_zoom_image/coe_mult_p0_0 [8] + + + APM_206_128/X[1] + + + + f + u_zoom_image/mult_image_g0_0/N2/gopapm/X[1] + +
+ + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_1080p60Hz (rising edge) + + 6.736 + 6.736 + r + + + + P20 + + 0.000 + 6.736 + r + clk (port) + + + + net (fanout=1) + 0.074 + 6.810 + + clk + + + IOBS_LR_328_209/DIN + td + 1.285 + 8.095 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 8.095 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.038 + 8.133 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.463 + 8.596 + + _N69 + + + PLL_158_55/CLK_OUT0 + td + 0.078 + 8.674 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 0.603 + 9.277 + + rd3_clk + + + USCM_84_154/CLK_USCM + td + 0.000 + 9.277 + r + USCMROUTE_0/CLKOUT + + + + net (fanout=1) + 1.091 + 10.368 + + ntR3950 + + + PLL_158_303/CLK_OUT0 + td + 0.078 + 10.446 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=1) + 0.915 + 11.361 + + zoom_clk + + + USCM_84_118/CLK_USCM + td + 0.000 + 11.361 + r + clkbufg_3/gopclkbufg/CLKOUT + + + + net (fanout=750) + 0.895 + 12.256 + + ntclkbufg_3 + + + APM_206_128/CLK + + + + r + u_zoom_image/mult_image_g0_0/N2/gopapm/CLK + + + clock pessimism + + 0.332 + 12.588 + + + + + clock uncertainty + + -0.150 + 12.438 + + + + + Setup time + + -1.731 + 10.707 + + + +
+
+ +
+ + 3.051 + 7 + 187 + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/CLK + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[14]/opit_0/CE + + eth_rxc + eth_rxc + rise-rise + -0.019 + 6.846 + 5.760 + 1.067 + 8.000 + 4.104 + 1.323 (32.2%) + 2.781 (67.8%) + + Path #13: setup slack is 3.051(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock eth_rxc (rising edge) + + 0.000 + 0.000 + r + + + + F14 + + 0.000 + 0.000 + r + eth_rxc (port) + + + + net (fanout=1) + 0.057 + 0.057 + + eth_rxc + + + IOBD_240_376/DIN + td + 0.861 + 0.918 + r + eth_rxc_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 0.918 + + eth_rxc_ibuf/ntD + + + IOL_243_374/INCK + td + 0.058 + 0.976 + r + eth_rxc_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.370 + 1.346 + + _N66 + + + IOCKDLY_237_367/CLK_OUT + td + 2.942 + 4.288 + r + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT + + + + net (fanout=1) + 1.521 + 5.809 + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf + + + USCM_84_109/CLK_USCM + td + 0.000 + 5.809 + r + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT + + + + net (fanout=1862) + 1.037 + 6.846 + + gmii_clk + + + CLMA_194_261/CLK + + - 0.000 - 0.000 r - + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/CLK - P20 - - 0.000 - 0.000 - r - clk (port) + CLMA_194_261/Q0 + tco + 0.221 + 7.067 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/Q - net (fanout=1) - 0.074 - 0.074 - - clk + net (fanout=2) + 0.560 + 7.627 + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t [0] - IOBS_LR_328_209/DIN + CLMA_182_241/Y1 td - 1.504 - 1.578 - r - clk_ibuf/opit_0/O + 0.224 + 7.851 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_39/gateop_perm/Z net (fanout=1) - 0.000 - 1.578 - - clk_ibuf/ntD + 0.458 + 8.309 + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108159 - IOL_327_210/INCK + CLMA_190_252/Y3 td - 0.058 - 1.636 - r - clk_ibuf/opit_1/INCK + 0.151 + 8.460 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_59/gateop_perm/Z net (fanout=1) - 0.478 - 2.114 - - _N69 + 0.367 + 8.827 + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108179 - PLL_158_55/CLK_OUT1 + CLMA_190_240/Y2 td - 0.079 - 2.193 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 + 0.150 + 8.977 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_63/gateop_perm/Z net (fanout=2) - 0.614 - 2.807 - - zoom_clk + 0.645 + 9.622 + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446 - USCM_84_122/CLK_USCM + CLMA_210_265/Y3 td - 0.000 - 2.807 + 0.162 + 9.784 r - USCMROUTE_2/CLKOUT + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N289_6/gateop_perm/Z - net (fanout=759) - 0.925 - 3.732 - - ntR3909 + net (fanout=6) + 0.302 + 10.086 + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108187 + + + CLMA_198_264/Y3 + td + 0.151 + 10.237 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/arp_rx_done/opit_0_L5Q_perm/Z - APM_206_140/CLK - + net (fanout=187) + 0.449 + 10.686 + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N319 + + + CLMA_202_272/CECO + td + 0.132 + 10.818 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[47]/opit_0/CEOUT + + - r - u_zoom_image/mult_fra0_0/N2/gopapm/CLK + net (fanout=1) + 0.000 + 10.818 + + ntR2081 - APM_206_140/P[31] - tco - 0.822 - 4.554 + CLMA_202_276/CECO + td + 0.132 + 10.950 f - u_zoom_image/mult_fra0_0/N2/gopapm/P[7] + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[42]/opit_0/CEOUT - net (fanout=3) - 1.670 - 6.224 + net (fanout=6) + 0.000 + 10.950 - u_zoom_image/coe_mult_p0_0 [7] + ntR2080 - APM_206_328/X[0] + CLMA_202_280/CECI f - u_zoom_image/mult_image_r0_0/N2/gopapm/X[0] + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[14]/opit_0/CE
- +
Location Delay Type @@ -109299,122 +113414,122 @@ Logical Resource - Clock clk_200m (rising edge) + Clock eth_rxc (rising edge) - 5.000 - 5.000 + 8.000 + 8.000 r - P20 + F14 0.000 - 5.000 + 8.000 r - clk (port) + eth_rxc (port) net (fanout=1) - 0.074 - 5.074 + 0.057 + 8.057 - clk + eth_rxc - IOBS_LR_328_209/DIN + IOBD_240_376/DIN td - 1.285 - 6.359 + 0.735 + 8.792 r - clk_ibuf/opit_0/O + eth_rxc_ibuf/opit_0/O net (fanout=1) 0.000 - 6.359 + 8.792 - clk_ibuf/ntD + eth_rxc_ibuf/ntD - IOL_327_210/INCK + IOL_243_374/INCK td 0.038 - 6.397 + 8.830 r - clk_ibuf/opit_1/INCK + eth_rxc_ibuf/opit_1/INCK net (fanout=1) - 0.463 - 6.860 + 0.363 + 9.193 - _N69 + _N66 - PLL_158_55/CLK_OUT1 + IOCKDLY_237_367/CLK_OUT td - 0.074 - 6.934 + 2.069 + 11.262 r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT - net (fanout=2) - 0.603 - 7.537 + net (fanout=1) + 1.493 + 12.755 - zoom_clk + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf - USCM_84_122/CLK_USCM + USCM_84_109/CLK_USCM td 0.000 - 7.537 + 12.755 r - USCMROUTE_2/CLKOUT + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - net (fanout=759) + net (fanout=1862) 1.005 - 8.542 + 13.760 - ntR3909 + gmii_clk - APM_206_328/CLK + CLMA_202_280/CLK r - u_zoom_image/mult_image_r0_0/N2/gopapm/CLK + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[14]/opit_0/CLK clock pessimism - 0.270 - 8.812 + 1.067 + 14.827 clock uncertainty - -0.150 - 8.662 + -0.250 + 14.577 Setup time - -1.731 - 6.931 + -0.576 + 14.001 @@ -109423,27 +113538,27 @@ - 0.759 - 0 - 3 - u_zoom_image/mult_fra0_0/N2/gopapm/CLK - u_zoom_image/mult_image_r0_0/N2/gopapm/X[3] + 3.051 + 7 + 187 + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/CLK + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[22]/opit_0/CE - clk_200m - clk_200m + eth_rxc + eth_rxc rise-rise - 0.080 - 3.732 - 3.542 - 0.270 - 5.000 - 2.440 - 0.822 (33.7%) - 1.618 (66.3%) + -0.019 + 6.846 + 5.760 + 1.067 + 8.000 + 4.104 + 1.323 (32.2%) + 2.781 (67.8%) - Path #2: setup slack is 0.759(MET) + Path #14: setup slack is 3.051(MET) -
+
Location Delay Type @@ -109453,7 +113568,7 @@ Logical Resource - Clock clk_200m (rising edge) + Clock eth_rxc (rising edge) 0.000 0.000 @@ -109461,121 +113576,233 @@ - P20 + F14 0.000 0.000 r - clk (port) + eth_rxc (port) net (fanout=1) - 0.074 - 0.074 + 0.057 + 0.057 - clk + eth_rxc - IOBS_LR_328_209/DIN + IOBD_240_376/DIN td - 1.504 - 1.578 + 0.861 + 0.918 r - clk_ibuf/opit_0/O + eth_rxc_ibuf/opit_0/O net (fanout=1) 0.000 - 1.578 + 0.918 - clk_ibuf/ntD + eth_rxc_ibuf/ntD - IOL_327_210/INCK + IOL_243_374/INCK td 0.058 - 1.636 + 0.976 r - clk_ibuf/opit_1/INCK + eth_rxc_ibuf/opit_1/INCK net (fanout=1) - 0.478 - 2.114 + 0.370 + 1.346 - _N69 + _N66 - PLL_158_55/CLK_OUT1 + IOCKDLY_237_367/CLK_OUT td - 0.079 - 2.193 + 2.942 + 4.288 r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT - net (fanout=2) - 0.614 - 2.807 + net (fanout=1) + 1.521 + 5.809 - zoom_clk + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf - USCM_84_122/CLK_USCM + USCM_84_109/CLK_USCM td 0.000 - 2.807 + 5.809 r - USCMROUTE_2/CLKOUT + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - net (fanout=759) - 0.925 - 3.732 + net (fanout=1862) + 1.037 + 6.846 - ntR3909 + gmii_clk - APM_206_140/CLK + CLMA_194_261/CLK r - u_zoom_image/mult_fra0_0/N2/gopapm/CLK + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/CLK - APM_206_140/P[34] + CLMA_194_261/Q0 tco - 0.822 - 4.554 + 0.221 + 7.067 f - u_zoom_image/mult_fra0_0/N2/gopapm/P[10] + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/Q - net (fanout=3) - 1.618 - 6.172 + net (fanout=2) + 0.560 + 7.627 + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t [0] + + + CLMA_182_241/Y1 + td + 0.224 + 7.851 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_39/gateop_perm/Z + + + + net (fanout=1) + 0.458 + 8.309 + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108159 + + + CLMA_190_252/Y3 + td + 0.151 + 8.460 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_59/gateop_perm/Z + + + + net (fanout=1) + 0.367 + 8.827 + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108179 + + + CLMA_190_240/Y2 + td + 0.150 + 8.977 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_63/gateop_perm/Z + + + + net (fanout=2) + 0.645 + 9.622 + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446 + + + CLMA_210_265/Y3 + td + 0.162 + 9.784 + r + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N289_6/gateop_perm/Z + + + + net (fanout=6) + 0.302 + 10.086 + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108187 + + + CLMA_198_264/Y3 + td + 0.151 + 10.237 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/arp_rx_done/opit_0_L5Q_perm/Z + + + + net (fanout=187) + 0.449 + 10.686 + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N319 + + + CLMA_202_272/CECO + td + 0.132 + 10.818 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[47]/opit_0/CEOUT + + + + net (fanout=1) + 0.000 + 10.818 + + ntR2081 + + + CLMA_202_276/CECO + td + 0.132 + 10.950 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[42]/opit_0/CEOUT + + + + net (fanout=6) + 0.000 + 10.950 - u_zoom_image/coe_mult_p0_0 [10] + ntR2080 - APM_206_328/X[3] + CLMA_202_280/CECI f - u_zoom_image/mult_image_r0_0/N2/gopapm/X[3] + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[22]/opit_0/CE
- +
Location Delay Type @@ -109585,122 +113812,122 @@ Logical Resource - Clock clk_200m (rising edge) + Clock eth_rxc (rising edge) - 5.000 - 5.000 + 8.000 + 8.000 r - P20 + F14 0.000 - 5.000 + 8.000 r - clk (port) + eth_rxc (port) net (fanout=1) - 0.074 - 5.074 + 0.057 + 8.057 - clk + eth_rxc - IOBS_LR_328_209/DIN + IOBD_240_376/DIN td - 1.285 - 6.359 + 0.735 + 8.792 r - clk_ibuf/opit_0/O + eth_rxc_ibuf/opit_0/O net (fanout=1) 0.000 - 6.359 + 8.792 - clk_ibuf/ntD + eth_rxc_ibuf/ntD - IOL_327_210/INCK + IOL_243_374/INCK td 0.038 - 6.397 + 8.830 r - clk_ibuf/opit_1/INCK + eth_rxc_ibuf/opit_1/INCK net (fanout=1) - 0.463 - 6.860 + 0.363 + 9.193 - _N69 + _N66 - PLL_158_55/CLK_OUT1 + IOCKDLY_237_367/CLK_OUT td - 0.074 - 6.934 + 2.069 + 11.262 r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT - net (fanout=2) - 0.603 - 7.537 + net (fanout=1) + 1.493 + 12.755 - zoom_clk + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf - USCM_84_122/CLK_USCM + USCM_84_109/CLK_USCM td 0.000 - 7.537 + 12.755 r - USCMROUTE_2/CLKOUT + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - net (fanout=759) + net (fanout=1862) 1.005 - 8.542 + 13.760 - ntR3909 + gmii_clk - APM_206_328/CLK + CLMA_202_280/CLK r - u_zoom_image/mult_image_r0_0/N2/gopapm/CLK + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[22]/opit_0/CLK clock pessimism - 0.270 - 8.812 + 1.067 + 14.827 clock uncertainty - -0.150 - 8.662 + -0.250 + 14.577 Setup time - -1.731 - 6.931 + -0.576 + 14.001 @@ -109709,27 +113936,27 @@ - 0.763 - 0 - 3 - u_zoom_image/mult_fra0_0/N2/gopapm/CLK - u_zoom_image/mult_image_r0_0/N2/gopapm/X[6] + 3.051 + 7 + 187 + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/CLK + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[29]/opit_0/CE - clk_200m - clk_200m + eth_rxc + eth_rxc rise-rise - 0.080 - 3.732 - 3.542 - 0.270 - 5.000 - 2.436 - 0.822 (33.7%) - 1.614 (66.3%) + -0.019 + 6.846 + 5.760 + 1.067 + 8.000 + 4.104 + 1.323 (32.2%) + 2.781 (67.8%) - Path #3: setup slack is 0.763(MET) + Path #15: setup slack is 3.051(MET) -
+
Location Delay Type @@ -109739,7 +113966,7 @@ Logical Resource - Clock clk_200m (rising edge) + Clock eth_rxc (rising edge) 0.000 0.000 @@ -109747,121 +113974,233 @@ - P20 + F14 0.000 0.000 r - clk (port) + eth_rxc (port) net (fanout=1) - 0.074 - 0.074 + 0.057 + 0.057 - clk + eth_rxc - IOBS_LR_328_209/DIN + IOBD_240_376/DIN td - 1.504 - 1.578 + 0.861 + 0.918 r - clk_ibuf/opit_0/O + eth_rxc_ibuf/opit_0/O net (fanout=1) 0.000 - 1.578 + 0.918 - clk_ibuf/ntD + eth_rxc_ibuf/ntD - IOL_327_210/INCK + IOL_243_374/INCK td 0.058 - 1.636 + 0.976 r - clk_ibuf/opit_1/INCK + eth_rxc_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.370 + 1.346 + + _N66 + + + IOCKDLY_237_367/CLK_OUT + td + 2.942 + 4.288 + r + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT + + + + net (fanout=1) + 1.521 + 5.809 + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf + + + USCM_84_109/CLK_USCM + td + 0.000 + 5.809 + r + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT + + + + net (fanout=1862) + 1.037 + 6.846 + + gmii_clk + + + CLMA_194_261/CLK + + + + r + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/CLK + + + CLMA_194_261/Q0 + tco + 0.221 + 7.067 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[0]/opit_0_L5Q_perm/Q + + + + net (fanout=2) + 0.560 + 7.627 + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t [0] + + + CLMA_182_241/Y1 + td + 0.224 + 7.851 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_39/gateop_perm/Z + + + + net (fanout=1) + 0.458 + 8.309 + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108159 + + + CLMA_190_252/Y3 + td + 0.151 + 8.460 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_59/gateop_perm/Z + + + + net (fanout=1) + 0.367 + 8.827 + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108179 + + + CLMA_190_240/Y2 + td + 0.150 + 8.977 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446_63/gateop_perm/Z - net (fanout=1) - 0.478 - 2.114 - - _N69 + net (fanout=2) + 0.645 + 9.622 + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N446 - PLL_158_55/CLK_OUT1 + CLMA_210_265/Y3 td - 0.079 - 2.193 + 0.162 + 9.784 r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N289_6/gateop_perm/Z - net (fanout=2) - 0.614 - 2.807 - - zoom_clk + net (fanout=6) + 0.302 + 10.086 + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/_N108187 - USCM_84_122/CLK_USCM + CLMA_198_264/Y3 td - 0.000 - 2.807 - r - USCMROUTE_2/CLKOUT + 0.151 + 10.237 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/arp_rx_done/opit_0_L5Q_perm/Z - net (fanout=759) - 0.925 - 3.732 - - ntR3909 + net (fanout=187) + 0.449 + 10.686 + + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N319 + + + CLMA_202_272/CECO + td + 0.132 + 10.818 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[47]/opit_0/CEOUT - APM_206_140/CLK - - - r - u_zoom_image/mult_fra0_0/N2/gopapm/CLK + net (fanout=1) + 0.000 + 10.818 + + ntR2081 - APM_206_140/P[37] - tco - 0.822 - 4.554 + CLMA_202_276/CECO + td + 0.132 + 10.950 f - u_zoom_image/mult_fra0_0/N2/gopapm/P[13] + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[42]/opit_0/CEOUT - net (fanout=3) - 1.614 - 6.168 + net (fanout=6) + 0.000 + 10.950 - u_zoom_image/coe_mult_p0_0 [13] + ntR2080 - APM_206_328/X[6] + CLMA_202_280/CECI f - u_zoom_image/mult_image_r0_0/N2/gopapm/X[6] + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[29]/opit_0/CE
- +
Location Delay Type @@ -109871,122 +114210,122 @@ Logical Resource - Clock clk_200m (rising edge) + Clock eth_rxc (rising edge) - 5.000 - 5.000 + 8.000 + 8.000 r - P20 + F14 0.000 - 5.000 + 8.000 r - clk (port) + eth_rxc (port) net (fanout=1) - 0.074 - 5.074 + 0.057 + 8.057 - clk + eth_rxc - IOBS_LR_328_209/DIN + IOBD_240_376/DIN td - 1.285 - 6.359 + 0.735 + 8.792 r - clk_ibuf/opit_0/O + eth_rxc_ibuf/opit_0/O net (fanout=1) 0.000 - 6.359 + 8.792 - clk_ibuf/ntD + eth_rxc_ibuf/ntD - IOL_327_210/INCK + IOL_243_374/INCK td 0.038 - 6.397 + 8.830 r - clk_ibuf/opit_1/INCK + eth_rxc_ibuf/opit_1/INCK net (fanout=1) - 0.463 - 6.860 + 0.363 + 9.193 - _N69 + _N66 - PLL_158_55/CLK_OUT1 + IOCKDLY_237_367/CLK_OUT td - 0.074 - 6.934 + 2.069 + 11.262 r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT - net (fanout=2) - 0.603 - 7.537 + net (fanout=1) + 1.493 + 12.755 - zoom_clk + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf - USCM_84_122/CLK_USCM + USCM_84_109/CLK_USCM td 0.000 - 7.537 + 12.755 r - USCMROUTE_2/CLKOUT + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - net (fanout=759) + net (fanout=1862) 1.005 - 8.542 + 13.760 - ntR3909 + gmii_clk - APM_206_328/CLK + CLMA_202_280/CLK r - u_zoom_image/mult_image_r0_0/N2/gopapm/CLK + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac[29]/opit_0/CLK clock pessimism - 0.270 - 8.812 + 1.067 + 14.827 clock uncertainty - -0.150 - 8.662 + -0.250 + 14.577 Setup time - -1.731 - 6.931 + -0.576 + 14.001 @@ -109995,27 +114334,27 @@ - 1.834 - 0 - 8 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[0] + 3.150 + 5 + 4 + u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L4 - ioclk1 - ioclk1 + hdmi_in_clk + hdmi_in_clk rise-rise - -0.003 - 4.916 - 4.519 - 0.394 - 2.500 - 0.408 - 0.408 (100.0%) - 0.000 (0.0%) + -0.019 + 4.020 + 3.724 + 0.277 + 6.666 + 3.153 + 1.821 (57.8%) + 1.332 (42.2%) - Path #4: setup slack is 1.834(MET) + Path #16: setup slack is 3.150(MET) -
+
Location Delay Type @@ -110025,7 +114364,7 @@ Logical Resource - Clock ioclk1 (rising edge) + Clock hdmi_in_clk (rising edge) 0.000 0.000 @@ -110033,153 +114372,217 @@ - P20 + AA12 0.000 0.000 r - clk (port) + hdmi_in_clk (port) net (fanout=1) - 0.074 - 0.074 + 0.078 + 0.078 - clk + hdmi_in_clk - IOBS_LR_328_209/DIN + IOBD_161_0/DIN td 1.504 - 1.578 + 1.582 r - clk_ibuf/opit_0/O + hdmi_in_clk_ibuf/opit_0/O net (fanout=1) 0.000 - 1.578 + 1.582 - clk_ibuf/ntD + hdmi_in_clk_ibuf/ntD - IOL_327_210/INCK + IOL_163_6/INCK td 0.058 - 1.636 + 1.640 r - clk_ibuf/opit_1/INCK + hdmi_in_clk_ibuf/opit_1/INCK net (fanout=1) - 0.478 - 2.114 + 1.455 + 3.095 - _N69 + _N37 - PLL_158_55/CLK_OUT1 + USCM_84_111/CLK_USCM td - 0.079 - 2.193 + 0.000 + 3.095 r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 + clkbufg_5/gopclkbufg/CLKOUT - net (fanout=2) - 0.614 - 2.807 + net (fanout=167) + 0.925 + 4.020 - zoom_clk + ntclkbufg_5 - USCM_84_113/CLK_USCM - td - 0.000 - 2.807 + CLMA_110_85/CLK + + + r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK + + + CLMA_110_85/Q0 + tco + 0.221 + 4.241 + f + u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/Q - net (fanout=68) - 1.019 - 3.826 + net (fanout=4) + 0.537 + 4.778 + + wr1_data_in_valid + + + + td + 0.222 + 5.000 + f + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Cout + + - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=1) + 0.000 + 5.000 + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15959 - PLL_158_199/CLK_OUT0_WL + CLMA_90_101/COUT td - 0.094 - 3.920 + 0.044 + 5.044 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/Cout - net (fanout=3) - 0.682 - 4.602 - - clkout0_wl_0 + net (fanout=1) + 0.000 + 5.044 + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15961 - IOCKGATE_6_188/OUT + td - 0.268 - 4.870 + 0.044 + 5.088 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/Cout - net (fanout=28) - 0.046 - 4.916 - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + net (fanout=1) + 0.000 + 5.088 + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15963 + + + CLMA_90_105/Y3 + td + 0.365 + 5.453 + f + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/Y1 - DQSL_6_152/CLK_IO - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + net (fanout=3) + 0.355 + 5.808 + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2 [7] - DQSL_6_152/IFIFO_RADDR[0] - tco - 0.408 - 5.324 + CLMA_94_112/Y3 + td + 0.151 + 5.959 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[0] + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[7]/gateop_perm/Z - net (fanout=8) + net (fanout=1) + 0.366 + 6.325 + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wwptr [7] + + + CLMA_90_100/COUT + td + 0.391 + 6.716 + r + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_2/gateop_A2/Cout + + + + net (fanout=1) 0.000 - 5.324 + 6.716 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [0] + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.co [6] - IOL_7_162/IFIFO_RADDR[0] + CLMA_90_104/Y1 + td + 0.383 + 7.099 + r + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_4/gateop_A2/Y1 + + + + net (fanout=1) + 0.074 + 7.173 + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158 + + + CLMA_90_104/C4 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[0] + r + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L4
- +
Location Delay Type @@ -110189,154 +114592,106 @@ Logical Resource - Clock ioclk1 (rising edge) + Clock hdmi_in_clk (rising edge) - 2.500 - 2.500 + 6.666 + 6.666 r - P20 + AA12 0.000 - 2.500 + 6.666 r - clk (port) + hdmi_in_clk (port) net (fanout=1) - 0.074 - 2.574 + 0.078 + 6.744 - clk + hdmi_in_clk - IOBS_LR_328_209/DIN + IOBD_161_0/DIN td 1.285 - 3.859 + 8.029 r - clk_ibuf/opit_0/O + hdmi_in_clk_ibuf/opit_0/O net (fanout=1) 0.000 - 3.859 + 8.029 - clk_ibuf/ntD + hdmi_in_clk_ibuf/ntD - IOL_327_210/INCK + IOL_163_6/INCK td 0.038 - 3.897 + 8.067 r - clk_ibuf/opit_1/INCK + hdmi_in_clk_ibuf/opit_1/INCK net (fanout=1) - 0.463 - 4.360 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.074 - 4.434 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 0.603 - 5.037 + 1.428 + 9.495 - zoom_clk + _N37 - USCM_84_113/CLK_USCM + USCM_84_111/CLK_USCM td 0.000 - 5.037 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 0.981 - 6.018 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.089 - 6.107 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 0.669 - 6.776 - - clkout0_wl_0 - - - IOCKGATE_6_188/OUT - td - 0.200 - 6.976 + 9.495 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT + clkbufg_5/gopclkbufg/CLKOUT - net (fanout=28) - 0.043 - 7.019 + net (fanout=167) + 0.895 + 10.390 - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + ntclkbufg_5 - IOL_7_162/CLK_IO + CLMA_90_104/CLK r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK clock pessimism - 0.394 - 7.413 + 0.277 + 10.667 clock uncertainty - -0.150 - 7.263 + -0.250 + 10.417 Setup time - -0.105 - 7.158 + -0.094 + 10.323 @@ -110345,27 +114700,27 @@ - 1.834 - 0 - 8 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[1] + 4.385 + 2 + 4 + u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/L2 - ioclk1 - ioclk1 + hdmi_in_clk + hdmi_in_clk rise-rise - -0.003 - 4.916 - 4.519 - 0.394 - 2.500 - 0.408 - 0.408 (100.0%) - 0.000 (0.0%) + -0.019 + 4.020 + 3.724 + 0.277 + 6.666 + 1.729 + 0.740 (42.8%) + 0.989 (57.2%) - Path #5: setup slack is 1.834(MET) + Path #17: setup slack is 4.385(MET) -
+
Location Delay Type @@ -110375,7 +114730,7 @@ Logical Resource - Clock ioclk1 (rising edge) + Clock hdmi_in_clk (rising edge) 0.000 0.000 @@ -110383,153 +114738,169 @@ - P20 + AA12 0.000 0.000 r - clk (port) + hdmi_in_clk (port) net (fanout=1) - 0.074 - 0.074 + 0.078 + 0.078 - clk + hdmi_in_clk - IOBS_LR_328_209/DIN + IOBD_161_0/DIN td 1.504 - 1.578 + 1.582 r - clk_ibuf/opit_0/O + hdmi_in_clk_ibuf/opit_0/O net (fanout=1) 0.000 - 1.578 + 1.582 - clk_ibuf/ntD + hdmi_in_clk_ibuf/ntD - IOL_327_210/INCK + IOL_163_6/INCK td 0.058 - 1.636 + 1.640 r - clk_ibuf/opit_1/INCK + hdmi_in_clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 1.455 + 3.095 + + _N37 + + + USCM_84_111/CLK_USCM + td + 0.000 + 3.095 + r + clkbufg_5/gopclkbufg/CLKOUT + + + + net (fanout=167) + 0.925 + 4.020 + + ntclkbufg_5 + CLMA_110_85/CLK - net (fanout=1) - 0.478 - 2.114 - _N69 + + r + u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK - PLL_158_55/CLK_OUT1 - td - 0.079 - 2.193 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 + CLMA_110_85/Q0 + tco + 0.221 + 4.241 + f + u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/Q - net (fanout=2) - 0.614 - 2.807 - - zoom_clk + net (fanout=4) + 0.537 + 4.778 + + wr1_data_in_valid - USCM_84_113/CLK_USCM + td - 0.000 - 2.807 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + 0.222 + 5.000 + f + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Cout - net (fanout=68) - 1.019 - 3.826 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=1) + 0.000 + 5.000 + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15959 - PLL_158_199/CLK_OUT0_WL + CLMA_90_101/COUT td - 0.094 - 3.920 + 0.044 + 5.044 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/Cout - net (fanout=3) - 0.682 - 4.602 - - clkout0_wl_0 + net (fanout=1) + 0.000 + 5.044 + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15961 - IOCKGATE_6_188/OUT + td - 0.268 - 4.870 + 0.044 + 5.088 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/Cout - net (fanout=28) - 0.046 - 4.916 - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + net (fanout=1) + 0.000 + 5.088 + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15963 - DQSL_6_152/CLK_IO - - - + CLMA_90_105/Y2 + td + 0.209 + 5.297 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - - - DQSL_6_152/IFIFO_RADDR[1] - tco - 0.408 - 5.324 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[1] + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/Y0 - net (fanout=8) - 0.000 - 5.324 + net (fanout=3) + 0.452 + 5.749 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [1] + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2 [6] - IOL_7_162/IFIFO_RADDR[1] + CLMA_90_104/D2 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[1] + r + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/L2
- +
Location Delay Type @@ -110539,154 +114910,106 @@ Logical Resource - Clock ioclk1 (rising edge) + Clock hdmi_in_clk (rising edge) - 2.500 - 2.500 + 6.666 + 6.666 r - P20 + AA12 0.000 - 2.500 + 6.666 r - clk (port) + hdmi_in_clk (port) net (fanout=1) - 0.074 - 2.574 + 0.078 + 6.744 - clk + hdmi_in_clk - IOBS_LR_328_209/DIN + IOBD_161_0/DIN td 1.285 - 3.859 + 8.029 r - clk_ibuf/opit_0/O + hdmi_in_clk_ibuf/opit_0/O net (fanout=1) 0.000 - 3.859 + 8.029 - clk_ibuf/ntD + hdmi_in_clk_ibuf/ntD - IOL_327_210/INCK + IOL_163_6/INCK td 0.038 - 3.897 + 8.067 r - clk_ibuf/opit_1/INCK + hdmi_in_clk_ibuf/opit_1/INCK net (fanout=1) - 0.463 - 4.360 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.074 - 4.434 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 0.603 - 5.037 + 1.428 + 9.495 - zoom_clk + _N37 - USCM_84_113/CLK_USCM + USCM_84_111/CLK_USCM td 0.000 - 5.037 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 0.981 - 6.018 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.089 - 6.107 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 0.669 - 6.776 - - clkout0_wl_0 - - - IOCKGATE_6_188/OUT - td - 0.200 - 6.976 + 9.495 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT + clkbufg_5/gopclkbufg/CLKOUT - net (fanout=28) - 0.043 - 7.019 + net (fanout=167) + 0.895 + 10.390 - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + ntclkbufg_5 - IOL_7_162/CLK_IO + CLMA_90_104/CLK r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/opit_0_L5Q_perm/CLK clock pessimism - 0.394 - 7.413 + 0.277 + 10.667 clock uncertainty - -0.150 - 7.263 + -0.250 + 10.417 Setup time - -0.105 - 7.158 + -0.283 + 10.134 @@ -110695,27 +115018,27 @@ - 1.834 - 0 - 8 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[2] + 4.427 + 3 + 4 + u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L1 - ioclk1 - ioclk1 + hdmi_in_clk + hdmi_in_clk rise-rise - -0.003 - 4.916 - 4.519 - 0.394 - 2.500 - 0.408 - 0.408 (100.0%) - 0.000 (0.0%) + -0.019 + 4.020 + 3.724 + 0.277 + 6.666 + 1.780 + 0.984 (55.3%) + 0.796 (44.7%) - Path #6: setup slack is 1.834(MET) + Path #18: setup slack is 4.427(MET) -
+
Location Delay Type @@ -110725,7 +115048,7 @@ Logical Resource - Clock ioclk1 (rising edge) + Clock hdmi_in_clk (rising edge) 0.000 0.000 @@ -110733,153 +115056,201 @@ - P20 + AA12 0.000 0.000 r - clk (port) + hdmi_in_clk (port) net (fanout=1) - 0.074 - 0.074 + 0.078 + 0.078 - clk + hdmi_in_clk - IOBS_LR_328_209/DIN + IOBD_161_0/DIN td 1.504 - 1.578 + 1.582 r - clk_ibuf/opit_0/O + hdmi_in_clk_ibuf/opit_0/O net (fanout=1) 0.000 - 1.578 + 1.582 - clk_ibuf/ntD + hdmi_in_clk_ibuf/ntD - IOL_327_210/INCK + IOL_163_6/INCK td 0.058 - 1.636 + 1.640 r - clk_ibuf/opit_1/INCK + hdmi_in_clk_ibuf/opit_1/INCK net (fanout=1) - 0.478 - 2.114 + 1.455 + 3.095 - _N69 + _N37 - PLL_158_55/CLK_OUT1 + USCM_84_111/CLK_USCM td - 0.079 - 2.193 + 0.000 + 3.095 r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 + clkbufg_5/gopclkbufg/CLKOUT - net (fanout=2) - 0.614 - 2.807 + net (fanout=167) + 0.925 + 4.020 - zoom_clk + ntclkbufg_5 - USCM_84_113/CLK_USCM - td - 0.000 - 2.807 + CLMA_110_85/CLK + + + r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK + + + CLMA_110_85/Q0 + tco + 0.221 + 4.241 + f + u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/Q - net (fanout=68) - 1.019 - 3.826 + net (fanout=4) + 0.537 + 4.778 + + wr1_data_in_valid + + + + td + 0.222 + 5.000 + f + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Cout + + - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=1) + 0.000 + 5.000 + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15959 - PLL_158_199/CLK_OUT0_WL + CLMA_90_101/COUT td - 0.094 - 3.920 + 0.044 + 5.044 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/Cout - net (fanout=3) - 0.682 - 4.602 - - clkout0_wl_0 + net (fanout=1) + 0.000 + 5.044 + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15961 - IOCKGATE_6_188/OUT + td - 0.268 - 4.870 + 0.044 + 5.088 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/Cout - net (fanout=28) - 0.046 - 4.916 - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + net (fanout=1) + 0.000 + 5.088 + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15963 + + + CLMA_90_105/COUT + td + 0.044 + 5.132 + r + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/Cout - DQSL_6_152/CLK_IO - - + net (fanout=1) + 0.000 + 5.132 + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15965 + + + + td + 0.044 + 5.176 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/Cout - DQSL_6_152/IFIFO_RADDR[2] - tco - 0.408 - 5.324 + + net (fanout=1) + 0.000 + 5.176 + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15967 + + + CLMA_90_109/Y3 + td + 0.365 + 5.541 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[2] + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_A2Q21/Y1 - net (fanout=8) - 0.000 - 5.324 + net (fanout=3) + 0.259 + 5.800 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [2] + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2 [11] - IOL_7_162/IFIFO_RADDR[2] + CLMA_90_104/C1 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[2] + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L1
- +
Location Delay Type @@ -110889,154 +115260,106 @@ Logical Resource - Clock ioclk1 (rising edge) + Clock hdmi_in_clk (rising edge) - 2.500 - 2.500 + 6.666 + 6.666 r - P20 + AA12 0.000 - 2.500 + 6.666 r - clk (port) + hdmi_in_clk (port) net (fanout=1) - 0.074 - 2.574 + 0.078 + 6.744 - clk + hdmi_in_clk - IOBS_LR_328_209/DIN + IOBD_161_0/DIN td 1.285 - 3.859 + 8.029 r - clk_ibuf/opit_0/O + hdmi_in_clk_ibuf/opit_0/O net (fanout=1) 0.000 - 3.859 + 8.029 - clk_ibuf/ntD + hdmi_in_clk_ibuf/ntD - IOL_327_210/INCK + IOL_163_6/INCK td 0.038 - 3.897 + 8.067 r - clk_ibuf/opit_1/INCK + hdmi_in_clk_ibuf/opit_1/INCK net (fanout=1) - 0.463 - 4.360 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.074 - 4.434 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 0.603 - 5.037 + 1.428 + 9.495 - zoom_clk + _N37 - USCM_84_113/CLK_USCM + USCM_84_111/CLK_USCM td 0.000 - 5.037 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 0.981 - 6.018 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.089 - 6.107 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 0.669 - 6.776 - - clkout0_wl_0 - - - IOCKGATE_6_188/OUT - td - 0.200 - 6.976 + 9.495 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT + clkbufg_5/gopclkbufg/CLKOUT - net (fanout=28) - 0.043 - 7.019 + net (fanout=167) + 0.895 + 10.390 - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + ntclkbufg_5 - IOL_7_162/CLK_IO + CLMA_90_104/CLK r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK clock pessimism - 0.394 - 7.413 + 0.277 + 10.667 clock uncertainty - -0.150 - 7.263 + -0.250 + 10.417 Setup time - -0.105 - 7.158 + -0.190 + 10.227 @@ -111045,27 +115368,27 @@ - 1.834 - 0 - 8 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[0] + 4.645 + 7 + 40 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/S0 - ioclk0 - ioclk0 + ddrphy_clkin + ddrphy_clkin rise-rise - -0.003 - 4.916 - 4.519 - 0.394 - 2.500 - 0.408 - 0.408 (100.0%) - 0.000 (0.0%) + -0.019 + 7.101 + 6.654 + 0.428 + 10.000 + 4.878 + 2.627 (53.9%) + 2.251 (46.1%) - Path #7: setup slack is 1.834(MET) + Path #19: setup slack is 4.645(MET) -
+
Location Delay Type @@ -111075,7 +115398,7 @@ Logical Resource - Clock ioclk0 (rising edge) + Clock ddrphy_clkin (rising edge) 0.000 0.000 @@ -111144,7 +115467,7 @@ 0.614 2.807 - zoom_clk + ddr_clk USCM_84_113/CLK_USCM @@ -111156,7 +115479,7 @@ - net (fanout=68) + net (fanout=71) 1.019 3.826 @@ -111179,57 +115502,217 @@ clkout0_wl_0 - IOCKGATE_6_312/OUT + IOCKGATE_6_322/OUT td 0.268 4.870 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT + clkgate_9/gopclkgate/OUT - net (fanout=11) - 0.046 - 4.916 + net (fanout=1) + 0.000 + 4.870 - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + ntclkgate_0 - DQSL_6_276/CLK_IO + IOCKDIV_6_323/CLK_IODIV + td + 0.000 + 4.870 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + + + + net (fanout=1) + 1.306 + 6.176 + + u_axi_ddr_top/clk + + + USCM_84_116/CLK_USCM + td + 0.000 + 6.176 + r + clkbufg_0/gopclkbufg/CLKOUT + + + + net (fanout=5464) + 0.925 + 7.101 + + ntclkbufg_0 + + + CLMS_10_133/CLK r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK - DQSL_6_276/IFIFO_RADDR[0] + CLMS_10_133/Q2 tco - 0.408 - 5.324 + 0.224 + 7.325 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/Q + + + + net (fanout=5) + 0.420 + 7.745 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mr0_ddr3 [2] + + + CLMS_18_149/Y1 + td + 0.224 + 7.969 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[0] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/gateop_perm/Z - net (fanout=8) + net (fanout=2) + 0.257 + 8.226 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_cl [1] + + + + td + 0.368 + 8.594 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_1/gateop_A2/Cout + + + + net (fanout=1) 0.000 - 5.324 + 8.594 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [0] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.co [2] - IOL_7_285/IFIFO_RADDR[0] + CLMS_18_145/Y3 + td + 0.365 + 8.959 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_3/gateop_A2/Y1 + + + + net (fanout=1) + 0.432 + 9.391 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [3] + + + CLMS_46_145/Y1 + td + 0.244 + 9.635 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[3]/gateop_perm/Z + + + + net (fanout=4) + 0.261 + 9.896 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al [3] + + + CLMA_50_144/COUT + td + 0.391 + 10.287 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_3/gateop_A2/Cout + + + + net (fanout=1) + 0.000 + 10.287 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14534 + + + CLMA_50_148/Y0 + td + 0.206 + 10.493 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_5/gateop/Y + + + + net (fanout=4) + 0.169 + 10.662 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mc_rl [4] + + + CLMS_46_149/Y0 + td + 0.226 + 10.888 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_159_5/gateop_perm/Z + + + + net (fanout=40) + 0.458 + 11.346 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23975 + + + CLMA_62_164/Y2 + td + 0.379 + 11.725 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_170[12]/gateop/F + + + + net (fanout=1) + 0.254 + 11.979 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24148 + + + CLMA_58_161/C3 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[0] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/S0
- +
Location Delay Type @@ -111239,10 +115722,10 @@ Logical Resource - Clock ioclk0 (rising edge) + Clock ddrphy_clkin (rising edge) - 2.500 - 2.500 + 10.000 + 10.000 r @@ -111250,7 +115733,7 @@ P200.000 - 2.500 + 10.000rclk (port) @@ -111258,7 +115741,7 @@ net (fanout=1) 0.074 - 2.574 + 10.074 clk @@ -111266,7 +115749,7 @@ IOBS_LR_328_209/DIN td 1.285 - 3.859 + 11.359 r clk_ibuf/opit_0/O @@ -111274,7 +115757,7 @@ net (fanout=1) 0.000 - 3.859 + 11.359 clk_ibuf/ntD @@ -111282,7 +115765,7 @@ IOL_327_210/INCK td 0.038 - 3.897 + 11.397 r clk_ibuf/opit_1/INCK @@ -111290,7 +115773,7 @@ net (fanout=1) 0.463 - 4.360 + 11.860 _N69 @@ -111298,7 +115781,7 @@ PLL_158_55/CLK_OUT1 td 0.074 - 4.434 + 11.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 @@ -111306,23 +115789,23 @@ net (fanout=2) 0.603 - 5.037 + 12.537 - zoom_clk + ddr_clk USCM_84_113/CLK_USCM td 0.000 - 5.037 + 12.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) + net (fanout=71) 0.981 - 6.018 + 13.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin @@ -111330,7 +115813,7 @@ PLL_158_199/CLK_OUT0_WL td 0.089 - 6.107 + 13.607 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL @@ -111338,39 +115821,71 @@ net (fanout=3) 0.669 - 6.776 + 14.276 clkout0_wl_0 - IOCKGATE_6_312/OUT + IOCKGATE_6_322/OUT td 0.200 - 6.976 + 14.476 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT + clkgate_9/gopclkgate/OUT - net (fanout=11) - 0.043 - 7.019 + net (fanout=1) + 0.000 + 14.476 - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + ntclkgate_0 - IOL_7_285/CLK_IO + IOCKDIV_6_323/CLK_IODIV + td + 0.000 + 14.476 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + + + + net (fanout=1) + 1.283 + 15.759 + + u_axi_ddr_top/clk + + + USCM_84_116/CLK_USCM + td + 0.000 + 15.759 + r + clkbufg_0/gopclkbufg/CLKOUT + + + + net (fanout=5464) + 0.895 + 16.654 + + ntclkbufg_0 + + + CLMA_58_161/CLK r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/CLK clock pessimism - 0.394 - 7.413 + 0.428 + 17.082 @@ -111378,15 +115893,15 @@ clock uncertainty -0.150 - 7.263 + 16.932 Setup time - -0.105 - 7.158 + -0.308 + 16.624 @@ -111395,27 +115910,27 @@ - 1.834 - 0 - 8 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[1] + 4.684 + 7 + 40 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/S0 - ioclk0 - ioclk0 + ddrphy_clkin + ddrphy_clkin rise-rise - -0.003 - 4.916 - 4.519 - 0.394 - 2.500 - 0.408 - 0.408 (100.0%) - 0.000 (0.0%) + -0.019 + 7.101 + 6.654 + 0.428 + 10.000 + 4.860 + 2.629 (54.1%) + 2.231 (45.9%) - Path #8: setup slack is 1.834(MET) + Path #20: setup slack is 4.684(MET) -
+
Location Delay Type @@ -111425,7 +115940,7 @@ Logical Resource - Clock ioclk0 (rising edge) + Clock ddrphy_clkin (rising edge) 0.000 0.000 @@ -111494,7 +116009,7 @@ 0.614 2.807 - zoom_clk + ddr_clk USCM_84_113/CLK_USCM @@ -111506,7 +116021,7 @@ - net (fanout=68) + net (fanout=71) 1.019 3.826 @@ -111529,57 +116044,217 @@ clkout0_wl_0 - IOCKGATE_6_312/OUT + IOCKGATE_6_322/OUT td 0.268 4.870 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT + clkgate_9/gopclkgate/OUT - net (fanout=11) - 0.046 - 4.916 + net (fanout=1) + 0.000 + 4.870 - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + ntclkgate_0 - DQSL_6_276/CLK_IO + IOCKDIV_6_323/CLK_IODIV + td + 0.000 + 4.870 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + + + + net (fanout=1) + 1.306 + 6.176 + + u_axi_ddr_top/clk + + + USCM_84_116/CLK_USCM + td + 0.000 + 6.176 + r + clkbufg_0/gopclkbufg/CLKOUT + + + + net (fanout=5464) + 0.925 + 7.101 + + ntclkbufg_0 + + + CLMS_10_133/CLK r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK - DQSL_6_276/IFIFO_RADDR[1] + CLMS_10_133/Q2 tco - 0.408 - 5.324 + 0.224 + 7.325 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/Q + + + + net (fanout=5) + 0.420 + 7.745 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mr0_ddr3 [2] + + + CLMS_18_149/Y1 + td + 0.224 + 7.969 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[1] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/gateop_perm/Z - net (fanout=8) + net (fanout=2) + 0.257 + 8.226 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_cl [1] + + + + td + 0.368 + 8.594 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_1/gateop_A2/Cout + + + + net (fanout=1) 0.000 - 5.324 + 8.594 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [1] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.co [2] + + + CLMS_18_145/Y3 + td + 0.365 + 8.959 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_3/gateop_A2/Y1 - IOL_7_285/IFIFO_RADDR[1] + net (fanout=1) + 0.432 + 9.391 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [3] + + + CLMS_46_145/Y1 + td + 0.244 + 9.635 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[3]/gateop_perm/Z + + + net (fanout=4) + 0.261 + 9.896 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al [3] + + + CLMA_50_144/COUT + td + 0.391 + 10.287 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_3/gateop_A2/Cout + + + net (fanout=1) + 0.000 + 10.287 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14534 + + + CLMA_50_148/Y0 + td + 0.206 + 10.493 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[1] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_5/gateop/Y + + + + net (fanout=4) + 0.169 + 10.662 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mc_rl [4] + + + CLMS_46_149/Y0 + td + 0.226 + 10.888 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_159_5/gateop_perm/Z + + + + net (fanout=40) + 0.519 + 11.407 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23975 + + + CLMA_66_156/Y2 + td + 0.381 + 11.788 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_170[10]/gateop/F + + + + net (fanout=1) + 0.173 + 11.961 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24146 + + + CLMA_66_152/B3 + + + + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/S0
- +
Location Delay Type @@ -111589,10 +116264,10 @@ Logical Resource - Clock ioclk0 (rising edge) + Clock ddrphy_clkin (rising edge) - 2.500 - 2.500 + 10.000 + 10.000 r @@ -111600,7 +116275,7 @@ P200.000 - 2.500 + 10.000rclk (port) @@ -111608,7 +116283,7 @@ net (fanout=1) 0.074 - 2.574 + 10.074 clk @@ -111616,7 +116291,7 @@ IOBS_LR_328_209/DIN td 1.285 - 3.859 + 11.359 r clk_ibuf/opit_0/O @@ -111624,7 +116299,7 @@ net (fanout=1) 0.000 - 3.859 + 11.359 clk_ibuf/ntD @@ -111632,7 +116307,7 @@ IOL_327_210/INCK td 0.038 - 3.897 + 11.397 r clk_ibuf/opit_1/INCK @@ -111640,7 +116315,7 @@ net (fanout=1) 0.463 - 4.360 + 11.860 _N69 @@ -111648,7 +116323,7 @@ PLL_158_55/CLK_OUT1 td 0.074 - 4.434 + 11.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 @@ -111656,23 +116331,23 @@ net (fanout=2) 0.603 - 5.037 + 12.537 - zoom_clk + ddr_clk USCM_84_113/CLK_USCM td 0.000 - 5.037 + 12.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) + net (fanout=71) 0.981 - 6.018 + 13.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin @@ -111680,47 +116355,79 @@ PLL_158_199/CLK_OUT0_WL td 0.089 - 6.107 + 13.607 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 0.669 + 14.276 + + clkout0_wl_0 + + + IOCKGATE_6_322/OUT + td + 0.200 + 14.476 + r + clkgate_9/gopclkgate/OUT + + + + net (fanout=1) + 0.000 + 14.476 + + ntclkgate_0 + + + IOCKDIV_6_323/CLK_IODIV + td + 0.000 + 14.476 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV - net (fanout=3) - 0.669 - 6.776 + net (fanout=1) + 1.283 + 15.759 - clkout0_wl_0 + u_axi_ddr_top/clk - IOCKGATE_6_312/OUT + USCM_84_116/CLK_USCM td - 0.200 - 6.976 + 0.000 + 15.759 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT + clkbufg_0/gopclkbufg/CLKOUT - net (fanout=11) - 0.043 - 7.019 + net (fanout=5464) + 0.895 + 16.654 - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + ntclkbufg_0 - IOL_7_285/CLK_IO + CLMA_66_152/CLK r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/CLK clock pessimism - 0.394 - 7.413 + 0.428 + 17.082 @@ -111728,15 +116435,15 @@ clock uncertainty -0.150 - 7.263 + 16.932 Setup time - -0.105 - 7.158 + -0.287 + 16.645 @@ -111745,27 +116452,27 @@ - 1.834 - 0 - 8 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[2] + 4.694 + 7 + 40 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/S0 - ioclk0 - ioclk0 + ddrphy_clkin + ddrphy_clkin rise-rise - -0.003 - 4.916 - 4.519 - 0.394 - 2.500 - 0.408 - 0.408 (100.0%) - 0.000 (0.0%) + -0.019 + 7.101 + 6.654 + 0.428 + 10.000 + 4.829 + 2.492 (51.6%) + 2.337 (48.4%) - Path #9: setup slack is 1.834(MET) + Path #21: setup slack is 4.694(MET) -
+
Location Delay Type @@ -111775,7 +116482,7 @@ Logical Resource - Clock ioclk0 (rising edge) + Clock ddrphy_clkin (rising edge) 0.000 0.000 @@ -111844,7 +116551,7 @@ 0.614 2.807 - zoom_clk + ddr_clk USCM_84_113/CLK_USCM @@ -111856,7 +116563,7 @@ - net (fanout=68) + net (fanout=71) 1.019 3.826 @@ -111879,57 +116586,217 @@ clkout0_wl_0 - IOCKGATE_6_312/OUT + IOCKGATE_6_322/OUT td 0.268 4.870 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT + clkgate_9/gopclkgate/OUT - net (fanout=11) - 0.046 - 4.916 + net (fanout=1) + 0.000 + 4.870 - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + ntclkgate_0 - DQSL_6_276/CLK_IO + IOCKDIV_6_323/CLK_IODIV + td + 0.000 + 4.870 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + + + + net (fanout=1) + 1.306 + 6.176 + + u_axi_ddr_top/clk + + + USCM_84_116/CLK_USCM + td + 0.000 + 6.176 + r + clkbufg_0/gopclkbufg/CLKOUT + + + + net (fanout=5464) + 0.925 + 7.101 + + ntclkbufg_0 + + + CLMS_10_133/CLK r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK - DQSL_6_276/IFIFO_RADDR[2] + CLMS_10_133/Q2 tco - 0.408 - 5.324 + 0.224 + 7.325 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/Q + + + + net (fanout=5) + 0.420 + 7.745 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mr0_ddr3 [2] + + + CLMS_18_149/Y1 + td + 0.224 + 7.969 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[2] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/gateop_perm/Z - net (fanout=8) + net (fanout=2) + 0.257 + 8.226 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_cl [1] + + + + td + 0.368 + 8.594 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_1/gateop_A2/Cout + + + + net (fanout=1) 0.000 - 5.324 + 8.594 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [2] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.co [2] + + + CLMS_18_145/Y3 + td + 0.365 + 8.959 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_3/gateop_A2/Y1 - IOL_7_285/IFIFO_RADDR[2] + net (fanout=1) + 0.432 + 9.391 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [3] + + + CLMS_46_145/Y1 + td + 0.244 + 9.635 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[3]/gateop_perm/Z + + + net (fanout=4) + 0.261 + 9.896 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al [3] + + + CLMA_50_144/COUT + td + 0.391 + 10.287 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_3/gateop_A2/Cout + + + net (fanout=1) + 0.000 + 10.287 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14534 + + + CLMA_50_148/Y0 + td + 0.206 + 10.493 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[2] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_5/gateop/Y + + + + net (fanout=4) + 0.169 + 10.662 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mc_rl [4] + + + CLMS_46_149/Y0 + td + 0.226 + 10.888 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_159_5/gateop_perm/Z + + + + net (fanout=40) + 0.539 + 11.427 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23975 + + + CLMA_62_160/Y1 + td + 0.244 + 11.671 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_170[14]/gateop/F + + + + net (fanout=1) + 0.259 + 11.930 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24150 + + + CLMA_58_161/A3 + + + + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/S0
- +
Location Delay Type @@ -111939,10 +116806,10 @@ Logical Resource - Clock ioclk0 (rising edge) + Clock ddrphy_clkin (rising edge) - 2.500 - 2.500 + 10.000 + 10.000 r @@ -111950,7 +116817,7 @@ P200.000 - 2.500 + 10.000rclk (port) @@ -111958,7 +116825,7 @@ net (fanout=1) 0.074 - 2.574 + 10.074 clk @@ -111966,7 +116833,7 @@ IOBS_LR_328_209/DIN td 1.285 - 3.859 + 11.359 r clk_ibuf/opit_0/O @@ -111974,7 +116841,7 @@ net (fanout=1) 0.000 - 3.859 + 11.359 clk_ibuf/ntD @@ -111982,7 +116849,7 @@ IOL_327_210/INCK td 0.038 - 3.897 + 11.397 r clk_ibuf/opit_1/INCK @@ -111990,7 +116857,7 @@ net (fanout=1) 0.463 - 4.360 + 11.860 _N69 @@ -111998,7 +116865,7 @@ PLL_158_55/CLK_OUT1 td 0.074 - 4.434 + 11.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 @@ -112006,23 +116873,23 @@ net (fanout=2) 0.603 - 5.037 + 12.537 - zoom_clk + ddr_clk USCM_84_113/CLK_USCM td 0.000 - 5.037 + 12.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) + net (fanout=71) 0.981 - 6.018 + 13.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin @@ -112030,7 +116897,7 @@ PLL_158_199/CLK_OUT0_WL td 0.089 - 6.107 + 13.607 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL @@ -112038,39 +116905,71 @@ net (fanout=3) 0.669 - 6.776 + 14.276 clkout0_wl_0 - IOCKGATE_6_312/OUT + IOCKGATE_6_322/OUT td 0.200 - 6.976 + 14.476 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT + clkgate_9/gopclkgate/OUT - net (fanout=11) - 0.043 - 7.019 + net (fanout=1) + 0.000 + 14.476 - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + ntclkgate_0 + + + IOCKDIV_6_323/CLK_IODIV + td + 0.000 + 14.476 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + + + + net (fanout=1) + 1.283 + 15.759 + + u_axi_ddr_top/clk + + + USCM_84_116/CLK_USCM + td + 0.000 + 15.759 + r + clkbufg_0/gopclkbufg/CLKOUT - IOL_7_285/CLK_IO + + net (fanout=5464) + 0.895 + 16.654 + + ntclkbufg_0 + + + CLMA_58_161/CLK r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/CLK clock pessimism - 0.394 - 7.413 + 0.428 + 17.082 @@ -112078,15 +116977,15 @@ clock uncertainty -0.150 - 7.263 + 16.932 Setup time - -0.105 - 7.158 + -0.308 + 16.624 @@ -112095,27 +116994,27 @@ - 2.618 - 4 - 4 - u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L4 + 5.869 + 2 + 1 + cmos2_data[6] + u_ov5640/cmos2_d_d0[6]/opit_0/D - hdmi_in_clk - hdmi_in_clk + cmos2_pclk + cmos2_pclk rise-rise - -0.019 - 4.020 - 3.724 - 0.277 - 6.666 - 3.685 - 2.003 (54.4%) - 1.682 (45.6%) + 3.511 + 0.000 + 3.511 + 0.000 + 11.900 + 8.224 + 1.146 (13.9%) + 7.078 (86.1%) - Path #10: setup slack is 2.618(MET) + Path #22: setup slack is 5.869(MET) -
+
Location Delay Type @@ -112125,7 +117024,7 @@ Logical Resource - Clock hdmi_in_clk (rising edge) + Clock cmos2_pclk (rising edge) 0.000 0.000 @@ -112133,201 +117032,311 @@ - AA12 - + Input external delay + + 1.000 + 1.000 + f + + + + Y9 + + 0.000 + 1.000 + f + cmos2_data[6] (port) + + + + net (fanout=1) + 0.078 + 1.078 + + cmos2_data[6] + + + IOBD_129_0/DIN + td + 1.049 + 2.127 + f + cmos2_data_ibuf[6]/opit_0/O + + + + net (fanout=1) 0.000 + 2.127 + + cmos2_data_ibuf[6]/ntD + + + IOL_131_6/RX_DATA_DD + td + 0.097 + 2.224 + f + cmos2_data_ibuf[6]/opit_1/OUT + + + + net (fanout=1) + 7.000 + 9.224 + + nt_cmos2_data[6] + + + CLMA_138_8/M1 + + + + f + u_ov5640/cmos2_d_d0[6]/opit_0/D + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock cmos2_pclk (rising edge) + + 11.900 + 11.900 + r + + + + W6 + 0.000 + 11.900 r - hdmi_in_clk (port) + cmos2_pclk (port) net (fanout=1) - 0.078 - 0.078 + 0.071 + 11.971 - hdmi_in_clk + cmos2_pclk - IOBD_161_0/DIN + IOBD_37_0/DIN td - 1.504 - 1.582 + 0.735 + 12.706 r - hdmi_in_clk_ibuf/opit_0/O + cmos2_pclk_ibuf/opit_0/O net (fanout=1) 0.000 - 1.582 + 12.706 - hdmi_in_clk_ibuf/ntD + cmos2_pclk_ibuf/ntD - IOL_163_6/INCK + IOL_39_6/RX_DATA_DD td - 0.058 - 1.640 + 0.066 + 12.772 r - hdmi_in_clk_ibuf/opit_1/INCK + cmos2_pclk_ibuf/opit_1/OUT net (fanout=1) - 1.455 - 3.095 + 1.744 + 14.516 - _N37 + nt_cmos2_pclk - USCM_84_111/CLK_USCM + USCM_84_119/CLK_USCM td 0.000 - 3.095 + 14.516 r - clkbufg_4/gopclkbufg/CLKOUT + clkbufg_7/gopclkbufg/CLKOUT - net (fanout=167) - 0.925 - 4.020 + net (fanout=118) + 0.895 + 15.411 - ntclkbufg_4 + ntclkbufg_7 - CLMA_146_68/CLK + CLMA_138_8/CLK r - u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK - - - CLMA_146_68/Q0 - tco - 0.221 - 4.241 - f - u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/Q + u_ov5640/cmos2_d_d0[6]/opit_0/CLK + clock pessimism + + 0.000 + 15.411 + - net (fanout=4) - 1.078 - 5.319 - - wr1_data_in_valid - - td - 0.222 - 5.541 - f - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Cout + clock uncertainty + + -0.250 + 15.161 + + + Setup time + + -0.068 + 15.093 + - net (fanout=1) - 0.000 - 5.541 - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16001 +
+
+
+
+ + 5.870 + 3 + 1 + cmos2_data[5] + u_ov5640/cmos2_d_d0[5]/opit_0/D + + cmos2_pclk + cmos2_pclk + rise-rise + 3.511 + 0.000 + 3.511 + 0.000 + 11.900 + 8.223 + 1.249 (15.2%) + 6.974 (84.8%) + + Path #23: setup slack is 5.870(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + - CLMA_70_96/Y3 - td - 0.387 - 5.928 + Clock cmos2_pclk (rising edge) + + 0.000 + 0.000 r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/Y1 + + Input external delay + + 1.000 + 1.000 + f - net (fanout=3) - 0.249 - 6.177 - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2 [3] - CLMA_66_88/Y2 - td - 0.381 - 6.558 + AB8 + + 0.000 + 1.000 f - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N3[3]/gateop_perm/Z + cmos2_data[5] (port) net (fanout=1) - 0.283 - 6.841 + 0.084 + 1.084 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wwptr [3] + cmos2_data[5] - + IOBS_TB_116_0/DIN td - 0.365 - 7.206 + 1.049 + 2.133 f - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_0/gateop_A2/Cout + cmos2_data_ibuf[5]/opit_0/O net (fanout=1) 0.000 - 7.206 + 2.133 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.co [2] + cmos2_data_ibuf[5]/ntD - CLMA_66_100/COUT + IOL_119_5/RX_DATA_DD td - 0.044 - 7.250 - r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_2/gateop_A2/Cout + 0.097 + 2.230 + f + cmos2_data_ibuf[5]/opit_1/OUT net (fanout=1) - 0.000 - 7.250 + 1.068 + 3.298 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.co [6] + nt_cmos2_data[5] - CLMA_66_104/Y1 + CLMS_198_49/Y6CD td - 0.383 - 7.633 - r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_4/gateop_A2/Y1 + 0.103 + 3.401 + f + CLKROUTE_0/Z net (fanout=1) - 0.072 - 7.705 + 5.822 + 9.223 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158 + ntR3940 - CLMA_66_104/C4 + CLMA_138_8/M0 - r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L4 + f + u_ov5640/cmos2_d_d0[5]/opit_0/D
- +
Location Delay Type @@ -112337,90 +117346,90 @@ Logical Resource - Clock hdmi_in_clk (rising edge) + Clock cmos2_pclk (rising edge) - 6.666 - 6.666 + 11.900 + 11.900 r - AA12 + W6 0.000 - 6.666 + 11.900 r - hdmi_in_clk (port) + cmos2_pclk (port) net (fanout=1) - 0.078 - 6.744 + 0.071 + 11.971 - hdmi_in_clk + cmos2_pclk - IOBD_161_0/DIN + IOBD_37_0/DIN td - 1.285 - 8.029 + 0.735 + 12.706 r - hdmi_in_clk_ibuf/opit_0/O + cmos2_pclk_ibuf/opit_0/O net (fanout=1) 0.000 - 8.029 + 12.706 - hdmi_in_clk_ibuf/ntD + cmos2_pclk_ibuf/ntD - IOL_163_6/INCK + IOL_39_6/RX_DATA_DD td - 0.038 - 8.067 + 0.066 + 12.772 r - hdmi_in_clk_ibuf/opit_1/INCK + cmos2_pclk_ibuf/opit_1/OUT net (fanout=1) - 1.428 - 9.495 + 1.744 + 14.516 - _N37 + nt_cmos2_pclk - USCM_84_111/CLK_USCM + USCM_84_119/CLK_USCM td 0.000 - 9.495 + 14.516 r - clkbufg_4/gopclkbufg/CLKOUT + clkbufg_7/gopclkbufg/CLKOUT - net (fanout=167) + net (fanout=118) 0.895 - 10.390 + 15.411 - ntclkbufg_4 + ntclkbufg_7 - CLMA_66_104/CLK + CLMA_138_8/CLK r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK + u_ov5640/cmos2_d_d0[5]/opit_0/CLK clock pessimism - 0.277 - 10.667 + 0.000 + 15.411 @@ -112428,15 +117437,15 @@ clock uncertainty -0.250 - 10.417 + 15.161 Setup time - -0.094 - 10.323 + -0.068 + 15.093 @@ -112445,27 +117454,27 @@ - 3.025 - 7 - 18 - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/CLK - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[0]/opit_0_L5Q_perm/CE + 5.987 + 4 + 1 + cmos2_href + u_ov5640/cmos2_href_d0/opit_0/D - eth_rxc - eth_rxc + cmos2_pclk + cmos2_pclk rise-rise - -0.019 - 6.734 - 5.650 - 1.065 - 8.000 - 4.230 - 2.071 (49.0%) - 2.159 (51.0%) + 3.550 + 0.000 + 3.550 + 0.000 + 11.900 + 8.237 + 1.219 (14.8%) + 7.018 (85.2%) - Path #11: setup slack is 3.025(MET) + Path #24: setup slack is 5.987(MET) -
+
Location Delay Type @@ -112475,7 +117484,7 @@ Logical Resource - Clock eth_rxc (rising edge) + Clock cmos2_pclk (rising edge) 0.000 0.000 @@ -112483,281 +117492,327 @@ - F14 - - 0.000 + Input external delay + + 1.000 + 1.000 + f + + + + AB5 + 0.000 - r - eth_rxc (port) + 1.000 + f + cmos2_href (port) net (fanout=1) - 0.057 - 0.057 - - eth_rxc + 0.093 + 1.093 + + cmos2_href - IOBD_240_376/DIN + IOBS_TB_32_0/DIN td - 0.861 0.918 - r - eth_rxc_ibuf/opit_0/O + 2.011 + f + cmos2_href_ibuf/opit_0/O net (fanout=1) 0.000 - 0.918 - - eth_rxc_ibuf/ntD + 2.011 + + cmos2_href_ibuf/ntD - IOL_243_374/INCK + IOL_35_5/RX_DATA_DD td - 0.058 - 0.976 - r - eth_rxc_ibuf/opit_1/INCK + 0.097 + 2.108 + f + cmos2_href_ibuf/opit_1/OUT net (fanout=1) - 0.370 - 1.346 - - _N66 + 0.521 + 2.629 + + nt_cmos2_href - IOCKDLY_237_367/CLK_OUT + CLMA_18_12/Y6AB td - 2.942 - 4.288 - r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT + 0.101 + 2.730 + f + CLKROUTE_2/Z net (fanout=1) - 1.521 - 5.809 - - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf + 3.087 + 5.817 + + ntR3942 - USCM_84_109/CLK_USCM + CLMA_18_80/Y6CD td - 0.000 - 5.809 - r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT + 0.103 + 5.920 + f + CLKROUTE_1/Z - net (fanout=1861) - 0.925 - 6.734 - - gmii_clk + net (fanout=1) + 3.317 + 9.237 + + ntR3941 - CLMA_202_140/CLK + CLMS_78_21/CD - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/CLK + f + u_ov5640/cmos2_href_d0/opit_0/D +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + - CLMA_202_140/Q2 - tco - 0.224 - 6.958 + Clock cmos2_pclk (rising edge) + + 11.900 + 11.900 r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/Q - - - net (fanout=2) - 0.305 - 7.263 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num [2] - - td - 0.365 - 7.628 - f - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_1/gateop_A2/Cout + W6 + + 0.000 + 11.900 + r + cmos2_pclk (port) net (fanout=1) - 0.000 - 7.628 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [2] + 0.071 + 11.971 + + cmos2_pclk - CLMA_214_140/COUT + IOBD_37_0/DIN td - 0.044 - 7.672 + 0.735 + 12.706 r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_3/gateop_A2/Cout + cmos2_pclk_ibuf/opit_0/O net (fanout=1) 0.000 - 7.672 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [4] + 12.706 + + cmos2_pclk_ibuf/ntD - + IOL_39_6/RX_DATA_DD td - 0.044 - 7.716 + 0.066 + 12.772 r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_5/gateop_A2/Cout + cmos2_pclk_ibuf/opit_1/OUT net (fanout=1) - 0.000 - 7.716 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [6] + 1.744 + 14.516 + + nt_cmos2_pclk - CLMA_214_144/COUT + USCM_84_119/CLK_USCM td - 0.044 - 7.760 + 0.000 + 14.516 r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_7/gateop_A2/Cout + clkbufg_7/gopclkbufg/CLKOUT - net (fanout=1) - 0.000 - 7.760 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [8] + net (fanout=118) + 0.934 + 15.450 + + ntclkbufg_7 - - td - 0.044 - 7.804 + CLMS_78_21/CLK + + + r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_9/gateop_A2/Cout + u_ov5640/cmos2_href_d0/opit_0/CLK + clock pessimism - net (fanout=1) 0.000 - 7.804 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [10] + 15.450 + + - CLMA_214_148/COUT - td - 0.044 - 7.848 - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_11/gateop_A2/Cout + clock uncertainty + + -0.250 + 15.200 + + + Setup time + + 0.024 + 15.224 + - net (fanout=1) - 0.000 - 7.848 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [12] +
+
+
+
+ + 6.435 + 2 + 1 + cmos1_href + u_ov5640/cmos1_href_d0/opit_0/D + + cmos1_pclk + cmos1_pclk + rise-rise + 3.172 + 0.000 + 3.172 + 0.000 + 11.900 + 7.319 + 1.015 (13.9%) + 6.304 (86.1%) + + Path #25: setup slack is 6.435(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + - CLMA_214_152/Y0 - td - 0.206 - 8.054 - f - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_13/gateop_A2/Y0 + Clock cmos1_pclk (rising edge) + + 0.000 + 0.000 + r + + Input external delay + + 1.000 + 1.000 + f - net (fanout=1) - 0.468 - 8.522 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276 [13] - CLMA_210_141/Y3 - td - 0.431 - 8.953 + AB10 + + 0.000 + 1.000 f - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N277.eq_6/gateop_A2/Y1 + cmos1_href (port) - net (fanout=18) - 0.529 - 9.482 + net (fanout=1) + 0.063 + 1.063 - _N79 + cmos1_href - CLMS_186_153/Y2 + IOBR_TB_148_0/DIN td - 0.381 - 9.863 + 0.918 + 1.981 f - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_pkt_done/opit_0_L5Q_perm/Z + cmos1_href_ibuf/opit_0/O net (fanout=1) - 0.304 - 10.167 + 0.000 + 1.981 - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N323 + cmos1_href_ibuf/ntD - CLMA_194_160/Y1 + IOL_151_5/RX_DATA_DD td - 0.244 - 10.411 + 0.097 + 2.078 f - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839/gateop_perm/Z + cmos1_href_ibuf/opit_1/OUT - net (fanout=16) - 0.553 - 10.964 + net (fanout=1) + 6.241 + 8.319 - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839 + nt_cmos1_href - CLMA_214_136/CE + CLMA_150_12/M1 f - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[0]/opit_0_L5Q_perm/CE + u_ov5640/cmos1_href_d0/opit_0/D
- +
Location Delay Type @@ -112767,151 +117822,219 @@ Logical Resource - Clock eth_rxc (rising edge) + Clock cmos1_pclk (rising edge) - 8.000 - 8.000 + 11.900 + 11.900 r - F14 + T12 0.000 - 8.000 + 11.900 r - eth_rxc (port) + cmos1_pclk (port) net (fanout=1) - 0.057 - 8.057 + 0.076 + 11.976 - eth_rxc + cmos1_pclk - IOBD_240_376/DIN + IOBD_169_0/DIN td 0.735 - 8.792 + 12.711 r - eth_rxc_ibuf/opit_0/O + cmos1_pclk_ibuf/opit_0/O net (fanout=1) 0.000 - 8.792 + 12.711 - eth_rxc_ibuf/ntD + cmos1_pclk_ibuf/ntD - IOL_243_374/INCK + IOL_171_6/INCK td 0.038 - 8.830 + 12.749 r - eth_rxc_ibuf/opit_1/INCK + cmos1_pclk_ibuf/opit_1/INCK net (fanout=1) - 0.363 - 9.193 + 1.428 + 14.177 - _N66 + _N64 - IOCKDLY_237_367/CLK_OUT + USCM_84_112/CLK_USCM td - 2.069 - 11.262 + 0.000 + 14.177 r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT + clkbufg_6/gopclkbufg/CLKOUT - net (fanout=1) - 1.493 - 12.755 + net (fanout=118) + 0.895 + 15.072 - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf + ntclkbufg_6 - USCM_84_109/CLK_USCM - td - 0.000 - 12.755 + CLMA_150_12/CLK + + + r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT + u_ov5640/cmos1_href_d0/opit_0/CLK + clock pessimism + + 0.000 + 15.072 + + + + + clock uncertainty + + -0.250 + 14.822 - net (fanout=1861) - 0.895 - 13.650 - gmii_clk - CLMA_214_136/CLK + Setup time + + -0.068 + 14.754 + +
+
+
+
+ + 7.113 + 2 + 1 + cmos1_data[0] + u_ov5640/cmos1_d_d0[0]/opit_0/D + + cmos1_pclk + cmos1_pclk + rise-rise + 3.172 + 0.000 + 3.172 + 0.000 + 11.900 + 6.733 + 1.146 (17.0%) + 5.587 (83.0%) + + Path #26: setup slack is 7.113(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock cmos1_pclk (rising edge) + 0.000 + 0.000 r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[0]/opit_0_L5Q_perm/CLK + - clock pessimism + Input external delay + + 1.000 + 1.000 + f - 1.065 - 14.715 + + + V11 + + 0.000 + 1.000 + f + cmos1_data[0] (port) + + + net (fanout=1) + 0.053 + 1.053 + + cmos1_data[0] + + + IOBD_133_0/DIN + td + 1.049 + 2.102 + f + cmos1_data_ibuf[0]/opit_0/O + + + net (fanout=1) + 0.000 + 2.102 + + cmos1_data_ibuf[0]/ntD + + + IOL_135_6/RX_DATA_DD + td + 0.097 + 2.199 + f + cmos1_data_ibuf[0]/opit_1/OUT - clock uncertainty - - -0.250 - 14.465 - + net (fanout=1) + 5.534 + 7.733 + + nt_cmos1_data[0] - Setup time + CLMS_134_45/CD - -0.476 - 13.989 + f + u_ov5640/cmos1_d_d0[0]/opit_0/D
-
-
- - 3.025 - 7 - 18 - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/CLK - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[2]/opit_0_L5Q_perm/CE - - eth_rxc - eth_rxc - rise-rise - -0.019 - 6.734 - 5.650 - 1.065 - 8.000 - 4.230 - 2.071 (49.0%) - 2.159 (51.0%) - - Path #12: setup slack is 3.025(MET) - +
Location Delay Type @@ -112921,289 +118044,219 @@ Logical Resource - Clock eth_rxc (rising edge) + Clock cmos1_pclk (rising edge) - 0.000 - 0.000 + 11.900 + 11.900 r - F14 + T12 0.000 - 0.000 + 11.900 r - eth_rxc (port) + cmos1_pclk (port) net (fanout=1) - 0.057 - 0.057 + 0.076 + 11.976 - eth_rxc + cmos1_pclk - IOBD_240_376/DIN + IOBD_169_0/DIN td - 0.861 - 0.918 + 0.735 + 12.711 r - eth_rxc_ibuf/opit_0/O + cmos1_pclk_ibuf/opit_0/O net (fanout=1) 0.000 - 0.918 + 12.711 - eth_rxc_ibuf/ntD + cmos1_pclk_ibuf/ntD - IOL_243_374/INCK + IOL_171_6/INCK td - 0.058 - 0.976 + 0.038 + 12.749 r - eth_rxc_ibuf/opit_1/INCK + cmos1_pclk_ibuf/opit_1/INCK net (fanout=1) - 0.370 - 1.346 + 1.428 + 14.177 - _N66 + _N64 - IOCKDLY_237_367/CLK_OUT + USCM_84_112/CLK_USCM td - 2.942 - 4.288 + 0.000 + 14.177 r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT + clkbufg_6/gopclkbufg/CLKOUT - net (fanout=1) - 1.521 - 5.809 + net (fanout=118) + 0.895 + 15.072 - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf + ntclkbufg_6 - USCM_84_109/CLK_USCM - td - 0.000 - 5.809 + CLMS_134_45/CLK + + + r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT + u_ov5640/cmos1_d_d0[0]/opit_0/CLK + clock pessimism + + 0.000 + 15.072 - net (fanout=1861) - 0.925 - 6.734 - gmii_clk - CLMA_202_140/CLK + clock uncertainty + -0.250 + 14.822 - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/CLK - - - CLMA_202_140/Q2 - tco - 0.224 - 6.958 - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/Q + Setup time - net (fanout=2) - 0.305 - 7.263 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num [2] - - - - td - 0.365 - 7.628 - f - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_1/gateop_A2/Cout - - + 0.024 + 14.846 - net (fanout=1) - 0.000 - 7.628 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [2] - - - CLMA_214_140/COUT - td - 0.044 - 7.672 - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_3/gateop_A2/Cout - - - net (fanout=1) - 0.000 - 7.672 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [4] - - - - td - 0.044 - 7.716 - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_5/gateop_A2/Cout +
+
+
+
+ + 7.237 + 2 + 1 + cmos1_data[6] + u_ov5640/cmos1_d_d0[6]/opit_0/D + + cmos1_pclk + cmos1_pclk + rise-rise + 3.172 + 0.000 + 3.172 + 0.000 + 11.900 + 6.517 + 1.146 (17.6%) + 5.371 (82.4%) + + Path #27: setup slack is 7.237(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + Clock cmos1_pclk (rising edge) - net (fanout=1) 0.000 - 7.716 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [6] - - - CLMA_214_144/COUT - td - 0.044 - 7.760 - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_7/gateop_A2/Cout - - - - net (fanout=1) 0.000 - 7.760 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [8] - - - - td - 0.044 - 7.804 r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_9/gateop_A2/Cout - - - net (fanout=1) - 0.000 - 7.804 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [10] - - - CLMA_214_148/COUT - td - 0.044 - 7.848 - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_11/gateop_A2/Cout + Input external delay - net (fanout=1) - 0.000 - 7.848 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [12] - - - CLMA_214_152/Y0 - td - 0.206 - 8.054 + 1.000 + 1.000 f - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_13/gateop_A2/Y0 - - - net (fanout=1) - 0.468 - 8.522 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276 [13] - CLMA_210_141/Y3 - td - 0.431 - 8.953 + AA10 + + 0.000 + 1.000 f - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N277.eq_6/gateop_A2/Y1 + cmos1_data[6] (port) - net (fanout=18) - 0.529 - 9.482 + net (fanout=1) + 0.080 + 1.080 - _N79 + cmos1_data[6] - CLMS_186_153/Y2 + IOBD_149_0/DIN td - 0.381 - 9.863 + 1.049 + 2.129 f - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_pkt_done/opit_0_L5Q_perm/Z + cmos1_data_ibuf[6]/opit_0/O net (fanout=1) - 0.304 - 10.167 + 0.000 + 2.129 - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N323 + cmos1_data_ibuf[6]/ntD - CLMA_194_160/Y1 + IOL_151_6/RX_DATA_DD td - 0.244 - 10.411 + 0.097 + 2.226 f - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839/gateop_perm/Z + cmos1_data_ibuf[6]/opit_1/OUT - net (fanout=16) - 0.553 - 10.964 + net (fanout=1) + 5.291 + 7.517 - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839 + nt_cmos1_data[6] - CLMA_214_136/CE + CLMS_150_41/M1 f - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[2]/opit_0_L5Q_perm/CE + u_ov5640/cmos1_d_d0[6]/opit_0/D
- +
Location Delay Type @@ -113213,106 +118266,90 @@ Logical Resource - Clock eth_rxc (rising edge) + Clock cmos1_pclk (rising edge) - 8.000 - 8.000 + 11.900 + 11.900 r - F14 + T12 0.000 - 8.000 + 11.900 r - eth_rxc (port) + cmos1_pclk (port) net (fanout=1) - 0.057 - 8.057 + 0.076 + 11.976 - eth_rxc + cmos1_pclk - IOBD_240_376/DIN + IOBD_169_0/DIN td 0.735 - 8.792 + 12.711 r - eth_rxc_ibuf/opit_0/O + cmos1_pclk_ibuf/opit_0/O net (fanout=1) 0.000 - 8.792 + 12.711 - eth_rxc_ibuf/ntD + cmos1_pclk_ibuf/ntD - IOL_243_374/INCK + IOL_171_6/INCK td 0.038 - 8.830 - r - eth_rxc_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.363 - 9.193 - - _N66 - - - IOCKDLY_237_367/CLK_OUT - td - 2.069 - 11.262 + 12.749 r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT + cmos1_pclk_ibuf/opit_1/INCK net (fanout=1) - 1.493 - 12.755 + 1.428 + 14.177 - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf + _N64 - USCM_84_109/CLK_USCM + USCM_84_112/CLK_USCM td 0.000 - 12.755 + 14.177 r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT + clkbufg_6/gopclkbufg/CLKOUT - net (fanout=1861) + net (fanout=118) 0.895 - 13.650 + 15.072 - gmii_clk + ntclkbufg_6 - CLMA_214_136/CLK + CLMS_150_41/CLK r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[2]/opit_0_L5Q_perm/CLK + u_ov5640/cmos1_d_d0[6]/opit_0/CLK clock pessimism - 1.065 - 14.715 + 0.000 + 15.072 @@ -113320,15 +118357,15 @@ clock uncertainty -0.250 - 14.465 + 14.822 Setup time - -0.476 - 13.989 + -0.068 + 14.754 @@ -113337,27 +118374,27 @@ - 3.025 + 8.191 7 - 18 - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/CLK - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[5]/opit_0_L5Q_perm/CE + 15 + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/rd_cnt[5]/opit_0_A2Q21/CLK + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0_A2Q1/Cin - eth_rxc - eth_rxc + clk_720p60Hz + clk_720p60Hz rise-rise -0.019 - 6.734 - 5.650 - 1.065 - 8.000 - 4.230 - 2.071 (49.0%) - 2.159 (51.0%) + 5.990 + 5.626 + 0.345 + 13.473 + 4.837 + 2.543 (52.6%) + 2.294 (47.4%) - Path #13: setup slack is 3.025(MET) + Path #28: setup slack is 8.191(MET) -
+
Location Delay Type @@ -113367,7 +118404,7 @@ Logical Resource - Clock eth_rxc (rising edge) + Clock clk_720p60Hz (rising edge) 0.000 0.000 @@ -113375,281 +118412,281 @@ - F14 + P20 0.000 0.000 r - eth_rxc (port) + clk (port) net (fanout=1) - 0.057 - 0.057 + 0.074 + 0.074 - eth_rxc + clk - IOBD_240_376/DIN + IOBS_LR_328_209/DIN td - 0.861 - 0.918 + 1.504 + 1.578 r - eth_rxc_ibuf/opit_0/O + clk_ibuf/opit_0/O net (fanout=1) 0.000 - 0.918 + 1.578 - eth_rxc_ibuf/ntD + clk_ibuf/ntD - IOL_243_374/INCK + IOL_327_210/INCK td 0.058 - 0.976 + 1.636 r - eth_rxc_ibuf/opit_1/INCK + clk_ibuf/opit_1/INCK net (fanout=1) - 0.370 - 1.346 + 0.478 + 2.114 - _N66 + _N69 - IOCKDLY_237_367/CLK_OUT + PLL_158_55/CLK_OUT0 td - 2.942 - 4.288 + 0.083 + 2.197 r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT + u_sys_pll/u_pll_e3/goppll/CLKOUT0 - net (fanout=1) - 1.521 - 5.809 + net (fanout=2) + 0.614 + 2.811 - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf + rd3_clk - USCM_84_109/CLK_USCM + USCM_84_154/CLK_USCM td 0.000 - 5.809 + 2.811 r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT + USCMROUTE_0/CLKOUT - net (fanout=1861) - 0.925 - 6.734 + net (fanout=1) + 1.131 + 3.942 - gmii_clk + ntR3950 + + + PLL_158_303/CLK_OUT1 + td + 0.079 + 4.021 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - CLMA_202_140/CLK - + net (fanout=2) + 0.932 + 4.953 - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/CLK + nt_pix_clk - CLMA_202_140/Q2 - tco - 0.224 - 6.958 + USCM_84_117/CLK_USCM + td + 0.000 + 4.953 r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num[2]/opit_0/Q + clkbufg_2/gopclkbufg/CLKOUT - net (fanout=2) - 0.305 - 7.263 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/data_byte_num [2] + net (fanout=1635) + 1.037 + 5.990 + + ntclkbufg_2 - - td - 0.365 - 7.628 + CLMA_214_292/CLK + + + + r + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/rd_cnt[5]/opit_0_A2Q21/CLK + + + CLMA_214_292/Q1 + tco + 0.223 + 6.213 f - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_1/gateop_A2/Cout + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/rd_cnt[5]/opit_0_A2Q21/Q1 - net (fanout=1) - 0.000 - 7.628 + net (fanout=3) + 0.352 + 6.565 - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [2] + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/rd_cnt [5] - CLMA_214_140/COUT + CLMA_218_284/Y1 td - 0.044 - 7.672 - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_3/gateop_A2/Cout + 0.244 + 6.809 + f + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N140_20/gateop_perm/Z net (fanout=1) - 0.000 - 7.672 + 0.467 + 7.276 - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [4] + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N107752 - + CLMA_214_280/Y1 td - 0.044 - 7.716 - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_5/gateop_A2/Cout + 0.360 + 7.636 + f + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N140_29/gateop_perm/Z - net (fanout=1) - 0.000 - 7.716 + net (fanout=3) + 0.169 + 7.805 - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [6] + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/_N98274 - CLMA_214_144/COUT + CLMA_214_284/Y1 td - 0.044 - 7.760 - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_7/gateop_A2/Cout + 0.151 + 7.956 + f + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N135_7/gateop_perm/Z - net (fanout=1) - 0.000 - 7.760 + net (fanout=15) + 0.628 + 8.584 - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [8] + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/fifo_rd_data_en td - 0.044 - 7.804 - r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_9/gateop_A2/Cout + 0.365 + 8.949 + f + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/opit_0_inv_A2Q1/Cout net (fanout=1) 0.000 - 7.804 + 8.949 - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [10] + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N13665 - CLMA_214_148/COUT + CLMS_186_277/COUT td 0.044 - 7.848 + 8.993 r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_11/gateop_A2/Cout + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/opit_0_inv_A2Q21/Cout net (fanout=1) 0.000 - 7.848 - - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.co [12] - - - CLMA_214_152/Y0 - td - 0.206 - 8.054 - f - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276_1.fsub_13/gateop_A2/Y0 - - - - net (fanout=1) - 0.468 - 8.522 + 8.993 - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N276 [13] + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N13667 - CLMA_210_141/Y3 + CLMS_186_281/Y1 td - 0.431 - 8.953 - f - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N277.eq_6/gateop_A2/Y1 + 0.383 + 9.376 + r + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/opit_0_inv_A2Q21/Y1 - net (fanout=18) - 0.529 - 9.482 + net (fanout=3) + 0.282 + 9.658 - _N79 + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N84 [5] - CLMS_186_153/Y2 + CLMA_186_292/Y2 td - 0.381 - 9.863 + 0.379 + 10.037 f - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_pkt_done/opit_0_L5Q_perm/Z + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N85[5]/gateop_perm/Z net (fanout=1) - 0.304 - 10.167 + 0.396 + 10.433 - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N323 + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rrptr [5] - CLMA_194_160/Y1 + CLMS_190_285/COUT td - 0.244 - 10.411 - f - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839/gateop_perm/Z + 0.394 + 10.827 + r + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N170.eq_2/gateop_A2/Cout - net (fanout=16) - 0.553 - 10.964 + net (fanout=1) + 0.000 + 10.827 - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N839 + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N170.co [6] - CLMA_214_136/CE + CLMS_190_289/CIN - f - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[5]/opit_0_L5Q_perm/CE + r + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0_A2Q1/Cin
- +
Location Delay Type @@ -113659,122 +118696,154 @@ Logical Resource - Clock eth_rxc (rising edge) + Clock clk_720p60Hz (rising edge) - 8.000 - 8.000 + 13.473 + 13.473 r - F14 + P20 0.000 - 8.000 + 13.473 + r + clk (port) + + + + net (fanout=1) + 0.074 + 13.547 + + clk + + + IOBS_LR_328_209/DIN + td + 1.285 + 14.832 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 14.832 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.038 + 14.870 r - eth_rxc (port) + clk_ibuf/opit_1/INCK net (fanout=1) - 0.057 - 8.057 + 0.463 + 15.333 - eth_rxc + _N69 - IOBD_240_376/DIN + PLL_158_55/CLK_OUT0 td - 0.735 - 8.792 + 0.078 + 15.411 r - eth_rxc_ibuf/opit_0/O + u_sys_pll/u_pll_e3/goppll/CLKOUT0 - net (fanout=1) - 0.000 - 8.792 + net (fanout=2) + 0.603 + 16.014 - eth_rxc_ibuf/ntD + rd3_clk - IOL_243_374/INCK + USCM_84_154/CLK_USCM td - 0.038 - 8.830 + 0.000 + 16.014 r - eth_rxc_ibuf/opit_1/INCK + USCMROUTE_0/CLKOUT net (fanout=1) - 0.363 - 9.193 + 1.091 + 17.105 - _N66 + ntR3950 - IOCKDLY_237_367/CLK_OUT + PLL_158_303/CLK_OUT1 td - 2.069 - 11.262 + 0.074 + 17.179 r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - net (fanout=1) - 1.493 - 12.755 + net (fanout=2) + 0.915 + 18.094 - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf + nt_pix_clk - USCM_84_109/CLK_USCM + USCM_84_117/CLK_USCM td 0.000 - 12.755 + 18.094 r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT + clkbufg_2/gopclkbufg/CLKOUT - net (fanout=1861) - 0.895 - 13.650 + net (fanout=1635) + 1.005 + 19.099 - gmii_clk + ntclkbufg_2 - CLMA_214_136/CLK + CLMS_190_289/CLK r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/rec_byte_num[5]/opit_0_L5Q_perm/CLK + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/opit_0_A2Q1/CLK clock pessimism - 1.065 - 14.715 + 0.345 + 19.444 clock uncertainty - -0.250 - 14.465 + -0.150 + 19.294 Setup time - -0.476 - 13.989 + -0.276 + 19.018 @@ -113783,27 +118852,27 @@ - 3.245 - 7 - 40 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/S0 + 8.378 + 9 + 12 + u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK + udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[0]/opit_0_L5Q_perm/CE - ddrphy_clkin - ddrphy_clkin + clk_720p60Hz + clk_720p60Hz rise-rise - -0.030 - 7.101 - 6.654 - 0.417 - 10.000 - 6.288 - 2.632 (41.9%) - 3.656 (58.1%) + -0.019 + 5.990 + 5.626 + 0.345 + 13.473 + 4.350 + 2.127 (48.9%) + 2.223 (51.1%) - Path #14: setup slack is 3.245(MET) + Path #29: setup slack is 8.378(MET) -
+
Location Delay Type @@ -113813,7 +118882,7 @@ Logical Resource - Clock ddrphy_clkin (rising edge) + Clock clk_720p60Hz (rising edge) 0.000 0.000 @@ -113869,265 +118938,249 @@ _N69 - PLL_158_55/CLK_OUT1 + PLL_158_55/CLK_OUT0 td - 0.079 - 2.193 + 0.083 + 2.197 r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 + u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 0.614 - 2.807 + 2.811 - zoom_clk + rd3_clk - USCM_84_113/CLK_USCM + USCM_84_154/CLK_USCM td 0.000 - 2.807 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.019 - 3.826 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.094 - 3.920 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 0.682 - 4.602 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.268 - 4.870 + 2.811 r - clkgate_8/gopclkgate/OUT + USCMROUTE_0/CLKOUT net (fanout=1) - 0.000 - 4.870 + 1.131 + 3.942 - ntclkgate_0 + ntR3950 - IOCKDIV_6_323/CLK_IODIV + PLL_158_303/CLK_OUT1 td - 0.000 - 4.870 + 0.079 + 4.021 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - net (fanout=1) - 1.306 - 6.176 + net (fanout=2) + 0.932 + 4.953 - u_axi_ddr_top/clk + nt_pix_clk - USCM_84_116/CLK_USCM + USCM_84_117/CLK_USCM td 0.000 - 6.176 + 4.953 r - clkbufg_0/gopclkbufg/CLKOUT + clkbufg_2/gopclkbufg/CLKOUT - net (fanout=5464) - 0.925 - 7.101 + net (fanout=1635) + 1.037 + 5.990 - ntclkbufg_0 + ntclkbufg_2 - CLMA_22_124/CLK + CLMA_246_256/CLK r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK + u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK - CLMA_22_124/Q3 + CLMA_246_256/Q2 tco - 0.220 - 7.321 + 0.223 + 6.213 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/Q + u_sync_vg/pos_y[8]/opit_0_A2Q21/Q0 - net (fanout=5) - 0.657 - 7.978 + net (fanout=1) + 0.460 + 6.673 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mr0_ddr3 [2] + pos_y[7] - CLMA_30_168/Y3 + CLMS_242_257/COUT td - 0.358 - 8.336 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/gateop_perm/Z + 0.397 + 7.070 + r + udp_osd_inst/N29.eq_2/gateop_A2/Cout - net (fanout=2) - 0.260 - 8.596 + net (fanout=1) + 0.000 + 7.070 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_cl [1] + udp_osd_inst/N29.co [6] + + + CLMS_242_261/Y1 + td + 0.383 + 7.453 + r + udp_osd_inst/N29.eq_4/gateop_A2/Y1 + + net (fanout=5) + 0.285 + 7.738 + udp_osd_inst/N29 + + + CLMA_250_257/Y2 td - 0.368 - 8.964 + 0.227 + 7.965 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_1/gateop_A2/Cout + udp_osd_inst/N69_5/gateop_perm/Z - net (fanout=1) - 0.000 - 8.964 + net (fanout=2) + 0.156 + 8.121 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.co [2] + udp_osd_inst/char_osd_inst/pixels_shifter_inst/N64 - CLMA_34_168/Y2 + CLMA_250_257/Y3 td - 0.202 - 9.166 + 0.151 + 8.272 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_3/gateop_A2/Y0 + udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/gateop_perm/Z - net (fanout=1) - 0.360 - 9.526 + net (fanout=2) + 0.253 + 8.525 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [2] + udp_osd_inst/char_osd_inst/row_pixels_ready - CLMA_30_160/Y3 + CLMA_250_261/Y1 td 0.151 - 9.677 + 8.676 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[2]/gateop_perm/Z + udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/gateop_perm/Z - net (fanout=4) - 0.451 - 10.128 + net (fanout=12) + 0.417 + 9.093 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al [2] + udp_osd_inst/char_osd_inst/char_next - CLMA_30_172/COUT + CLMA_246_284/Y2 td - 0.387 - 10.515 + 0.162 + 9.255 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_3/gateop_A2/Cout + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N74/gateop_perm/Z net (fanout=1) - 0.000 - 10.515 + 0.148 + 9.403 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14576 + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N74 - CLMA_30_176/Y0 + CLMA_246_284/Y1 td - 0.206 - 10.721 + 0.151 + 9.554 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_5/gateop/Y + udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_fsm[3:0]_62/gateop_perm/Z - net (fanout=4) - 0.996 - 11.717 + net (fanout=3) + 0.255 + 9.809 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mc_rl [4] + udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N97126 - CLMA_30_248/Y0 + CLMA_250_284/Y0 td - 0.380 - 12.097 + 0.150 + 9.959 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_159_5/gateop_perm/Z + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786/gateop_perm/Z - net (fanout=40) - 0.617 - 12.714 + net (fanout=1) + 0.249 + 10.208 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24196 + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786 - CLMS_38_245/Y1 + CLMA_254_288/CECO td - 0.360 - 13.074 + 0.132 + 10.340 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_170[2]/gateop/F + udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[4]/opit_0_A2Q21/CEOUT - net (fanout=1) - 0.315 - 13.389 + net (fanout=4) + 0.000 + 10.340 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24359 + ntR2066 - CLMS_22_245/D3 + CLMA_254_292/CECI f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/S0 + udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[0]/opit_0_L5Q_perm/CE
- +
Location Delay Type @@ -114137,10 +119190,10 @@ Logical Resource - Clock ddrphy_clkin (rising edge) + Clock clk_720p60Hz (rising edge) - 10.000 - 10.000 + 13.473 + 13.473 r @@ -114148,7 +119201,7 @@ P200.000 - 10.000 + 13.473rclk (port) @@ -114156,7 +119209,7 @@ net (fanout=1) 0.074 - 10.074 + 13.547 clk @@ -114164,7 +119217,7 @@ IOBS_LR_328_209/DIN td 1.285 - 11.359 + 14.832 r clk_ibuf/opit_0/O @@ -114172,7 +119225,7 @@ net (fanout=1) 0.000 - 11.359 + 14.832 clk_ibuf/ntD @@ -114180,7 +119233,7 @@ IOL_327_210/INCK td 0.038 - 11.397 + 14.870 r clk_ibuf/opit_1/INCK @@ -114188,119 +119241,87 @@ net (fanout=1) 0.463 - 11.860 + 15.333 _N69 - PLL_158_55/CLK_OUT1 + PLL_158_55/CLK_OUT0 td - 0.074 - 11.934 + 0.078 + 15.411 r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 + u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 0.603 - 12.537 + 16.014 - zoom_clk + rd3_clk - USCM_84_113/CLK_USCM + USCM_84_154/CLK_USCM td 0.000 - 12.537 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 0.981 - 13.518 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.089 - 13.607 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 0.669 - 14.276 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.200 - 14.476 + 16.014 r - clkgate_8/gopclkgate/OUT + USCMROUTE_0/CLKOUT net (fanout=1) - 0.000 - 14.476 + 1.091 + 17.105 - ntclkgate_0 + ntR3950 - IOCKDIV_6_323/CLK_IODIV + PLL_158_303/CLK_OUT1 td - 0.000 - 14.476 + 0.074 + 17.179 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - net (fanout=1) - 1.283 - 15.759 + net (fanout=2) + 0.915 + 18.094 - u_axi_ddr_top/clk + nt_pix_clk - USCM_84_116/CLK_USCM + USCM_84_117/CLK_USCM td 0.000 - 15.759 + 18.094 r - clkbufg_0/gopclkbufg/CLKOUT + clkbufg_2/gopclkbufg/CLKOUT - net (fanout=5464) - 0.895 - 16.654 + net (fanout=1635) + 1.005 + 19.099 - ntclkbufg_0 + ntclkbufg_2 - CLMS_22_245/CLK + CLMA_254_292/CLK r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/CLK + udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[0]/opit_0_L5Q_perm/CLK clock pessimism - 0.417 - 17.071 + 0.345 + 19.444 @@ -114308,15 +119329,15 @@ clock uncertainty -0.150 - 16.921 + 19.294 Setup time - -0.287 - 16.634 + -0.576 + 18.718 @@ -114325,27 +119346,27 @@ - 3.267 - 7 - 40 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/S0 + 8.378 + 9 + 12 + u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK + udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[1]/opit_0_L5Q_perm/CE - ddrphy_clkin - ddrphy_clkin + clk_720p60Hz + clk_720p60Hz rise-rise - -0.030 - 7.101 - 6.654 - 0.417 - 10.000 - 6.245 - 2.632 (42.1%) - 3.613 (57.9%) + -0.019 + 5.990 + 5.626 + 0.345 + 13.473 + 4.350 + 2.127 (48.9%) + 2.223 (51.1%) - Path #15: setup slack is 3.267(MET) + Path #30: setup slack is 8.378(MET) -
+
Location Delay Type @@ -114355,7 +119376,7 @@ Logical Resource - Clock ddrphy_clkin (rising edge) + Clock clk_720p60Hz (rising edge) 0.000 0.000 @@ -114411,265 +119432,249 @@ _N69 - PLL_158_55/CLK_OUT1 + PLL_158_55/CLK_OUT0 td - 0.079 - 2.193 + 0.083 + 2.197 r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 + u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 0.614 - 2.807 + 2.811 - zoom_clk + rd3_clk - USCM_84_113/CLK_USCM + USCM_84_154/CLK_USCM td 0.000 - 2.807 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.019 - 3.826 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.094 - 3.920 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 0.682 - 4.602 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.268 - 4.870 + 2.811 r - clkgate_8/gopclkgate/OUT + USCMROUTE_0/CLKOUT net (fanout=1) - 0.000 - 4.870 + 1.131 + 3.942 - ntclkgate_0 + ntR3950 - IOCKDIV_6_323/CLK_IODIV + PLL_158_303/CLK_OUT1 td - 0.000 - 4.870 + 0.079 + 4.021 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - net (fanout=1) - 1.306 - 6.176 + net (fanout=2) + 0.932 + 4.953 - u_axi_ddr_top/clk + nt_pix_clk - USCM_84_116/CLK_USCM + USCM_84_117/CLK_USCM td 0.000 - 6.176 + 4.953 r - clkbufg_0/gopclkbufg/CLKOUT + clkbufg_2/gopclkbufg/CLKOUT - net (fanout=5464) - 0.925 - 7.101 + net (fanout=1635) + 1.037 + 5.990 - ntclkbufg_0 + ntclkbufg_2 - CLMA_22_124/CLK + CLMA_246_256/CLK r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK + u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK - CLMA_22_124/Q3 + CLMA_246_256/Q2 tco - 0.220 - 7.321 + 0.223 + 6.213 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/Q + u_sync_vg/pos_y[8]/opit_0_A2Q21/Q0 - net (fanout=5) - 0.657 - 7.978 + net (fanout=1) + 0.460 + 6.673 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mr0_ddr3 [2] + pos_y[7] - CLMA_30_168/Y3 + CLMS_242_257/COUT td - 0.358 - 8.336 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/gateop_perm/Z + 0.397 + 7.070 + r + udp_osd_inst/N29.eq_2/gateop_A2/Cout - net (fanout=2) - 0.260 - 8.596 + net (fanout=1) + 0.000 + 7.070 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_cl [1] + udp_osd_inst/N29.co [6] + + + CLMS_242_261/Y1 + td + 0.383 + 7.453 + r + udp_osd_inst/N29.eq_4/gateop_A2/Y1 + + net (fanout=5) + 0.285 + 7.738 + udp_osd_inst/N29 + + + CLMA_250_257/Y2 td - 0.368 - 8.964 + 0.227 + 7.965 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_1/gateop_A2/Cout + udp_osd_inst/N69_5/gateop_perm/Z - net (fanout=1) - 0.000 - 8.964 + net (fanout=2) + 0.156 + 8.121 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.co [2] + udp_osd_inst/char_osd_inst/pixels_shifter_inst/N64 - CLMA_34_168/Y2 + CLMA_250_257/Y3 td - 0.202 - 9.166 + 0.151 + 8.272 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_3/gateop_A2/Y0 + udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/gateop_perm/Z - net (fanout=1) - 0.360 - 9.526 + net (fanout=2) + 0.253 + 8.525 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [2] + udp_osd_inst/char_osd_inst/row_pixels_ready - CLMA_30_160/Y3 + CLMA_250_261/Y1 td 0.151 - 9.677 + 8.676 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[2]/gateop_perm/Z + udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/gateop_perm/Z - net (fanout=4) - 0.451 - 10.128 + net (fanout=12) + 0.417 + 9.093 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al [2] + udp_osd_inst/char_osd_inst/char_next - CLMA_30_172/COUT + CLMA_246_284/Y2 td - 0.387 - 10.515 + 0.162 + 9.255 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_3/gateop_A2/Cout + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N74/gateop_perm/Z net (fanout=1) - 0.000 - 10.515 + 0.148 + 9.403 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14576 + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N74 - CLMA_30_176/Y0 + CLMA_246_284/Y1 td - 0.206 - 10.721 + 0.151 + 9.554 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_5/gateop/Y + udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_fsm[3:0]_62/gateop_perm/Z - net (fanout=4) - 0.996 - 11.717 + net (fanout=3) + 0.255 + 9.809 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mc_rl [4] + udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N97126 - CLMA_30_248/Y0 + CLMA_250_284/Y0 td - 0.380 - 12.097 + 0.150 + 9.959 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_159_5/gateop_perm/Z + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786/gateop_perm/Z - net (fanout=40) - 0.491 - 12.588 + net (fanout=1) + 0.249 + 10.208 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24196 + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786 - CLMA_30_248/Y1 + CLMA_254_288/CECO td - 0.360 - 12.948 + 0.132 + 10.340 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_170[0]/gateop/F + udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[4]/opit_0_A2Q21/CEOUT - net (fanout=1) - 0.398 - 13.346 + net (fanout=4) + 0.000 + 10.340 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24357 + ntR2066 - CLMS_22_245/A3 + CLMA_254_292/CECI f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/S0 + udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[1]/opit_0_L5Q_perm/CE
- +
Location Delay Type @@ -114679,10 +119684,10 @@ Logical Resource - Clock ddrphy_clkin (rising edge) + Clock clk_720p60Hz (rising edge) - 10.000 - 10.000 + 13.473 + 13.473 r @@ -114690,7 +119695,7 @@ P200.000 - 10.000 + 13.473rclk (port) @@ -114698,7 +119703,7 @@ net (fanout=1) 0.074 - 10.074 + 13.547 clk @@ -114706,7 +119711,7 @@ IOBS_LR_328_209/DIN td 1.285 - 11.359 + 14.832 r clk_ibuf/opit_0/O @@ -114714,7 +119719,7 @@ net (fanout=1) 0.000 - 11.359 + 14.832 clk_ibuf/ntD @@ -114722,7 +119727,7 @@ IOL_327_210/INCK td 0.038 - 11.397 + 14.870 r clk_ibuf/opit_1/INCK @@ -114730,119 +119735,87 @@ net (fanout=1) 0.463 - 11.860 + 15.333 _N69 - PLL_158_55/CLK_OUT1 + PLL_158_55/CLK_OUT0 td - 0.074 - 11.934 + 0.078 + 15.411 r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 + u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 0.603 - 12.537 + 16.014 - zoom_clk + rd3_clk - USCM_84_113/CLK_USCM + USCM_84_154/CLK_USCM td 0.000 - 12.537 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 0.981 - 13.518 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.089 - 13.607 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 0.669 - 14.276 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.200 - 14.476 + 16.014 r - clkgate_8/gopclkgate/OUT + USCMROUTE_0/CLKOUT net (fanout=1) - 0.000 - 14.476 + 1.091 + 17.105 - ntclkgate_0 + ntR3950 - IOCKDIV_6_323/CLK_IODIV + PLL_158_303/CLK_OUT1 td - 0.000 - 14.476 + 0.074 + 17.179 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - net (fanout=1) - 1.283 - 15.759 + net (fanout=2) + 0.915 + 18.094 - u_axi_ddr_top/clk + nt_pix_clk - USCM_84_116/CLK_USCM + USCM_84_117/CLK_USCM td 0.000 - 15.759 + 18.094 r - clkbufg_0/gopclkbufg/CLKOUT + clkbufg_2/gopclkbufg/CLKOUT - net (fanout=5464) - 0.895 - 16.654 + net (fanout=1635) + 1.005 + 19.099 - ntclkbufg_0 + ntclkbufg_2 - CLMS_22_245/CLK + CLMA_254_292/CLK r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/opit_0_inv_MUX4TO1Q/CLK + udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[1]/opit_0_L5Q_perm/CLK clock pessimism - 0.417 - 17.071 + 0.345 + 19.444 @@ -114850,15 +119823,15 @@ clock uncertainty -0.150 - 16.921 + 19.294 Setup time - -0.308 - 16.613 + -0.576 + 18.718 @@ -114867,27 +119840,27 @@ - 3.293 - 7 - 40 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/S0 + 12.954 + 6 + 6 + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/L4 - ddrphy_clkin - ddrphy_clkin + clk_50m + clk_50m rise-rise - 0.080 - 7.101 - 6.764 - 0.417 - 10.000 - 6.350 - 2.632 (41.4%) - 3.718 (58.6%) + -0.035 + 3.764 + 3.448 + 0.281 + 20.000 + 6.767 + 3.925 (58.0%) + 2.842 (42.0%) - Path #16: setup slack is 3.293(MET) + Path #31: setup slack is 12.954(MET) -
+
Location Delay Type @@ -114897,7 +119870,7 @@ Logical Resource - Clock ddrphy_clkin (rising edge) + Clock clk_50m (rising edge) 0.000 0.000 @@ -114953,265 +119926,185 @@ _N69 - PLL_158_55/CLK_OUT1 + PLL_158_55/CLK_OUT0 td - 0.079 - 2.193 + 0.083 + 2.197 r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 + u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 0.614 - 2.807 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 2.807 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.019 - 3.826 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.094 - 3.920 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 0.682 - 4.602 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.268 - 4.870 - r - clkgate_8/gopclkgate/OUT - - - - net (fanout=1) - 0.000 - 4.870 - - ntclkgate_0 - - - IOCKDIV_6_323/CLK_IODIV - td - 0.000 - 4.870 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV - - - - net (fanout=1) - 1.306 - 6.176 + 2.811 - u_axi_ddr_top/clk + rd3_clk - USCM_84_116/CLK_USCM + USCM_84_108/CLK_USCM td 0.000 - 6.176 + 2.811 r - clkbufg_0/gopclkbufg/CLKOUT + clkbufg_1/gopclkbufg/CLKOUT - net (fanout=5464) - 0.925 - 7.101 + net (fanout=2516) + 0.953 + 3.764 - ntclkbufg_0 + ntclkbufg_1 - CLMA_22_124/CLK + DRM_54_24/CLKB[0] r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/CLK + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB - CLMA_22_124/Q3 + DRM_54_24/QB0[0] tco - 0.220 - 7.321 + 1.780 + 5.544 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/opit_0_inv_L5Q_perm/Q + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/DOB[0] - net (fanout=5) - 0.657 - 7.978 + net (fanout=6) + 0.982 + 6.526 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mr0_ddr3 [2] + u_rotate_image/dout [0] - CLMA_30_168/Y3 + CLMS_74_117/Y1 td - 0.358 - 8.336 + 0.359 + 6.885 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/gateop_perm/Z + u_rotate_image/addr_fifo_valid/opit_0_L5Q_perm/Z - net (fanout=2) - 0.260 - 8.596 + net (fanout=3) + 1.071 + 7.956 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_cl [1] + u_rotate_image/addr_fifo_rd_en td - 0.368 - 8.964 + 0.222 + 8.178 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_1/gateop_A2/Cout + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/Cout net (fanout=1) 0.000 - 8.964 + 8.178 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.co [2] + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16576 - CLMA_34_168/Y2 + CLMS_50_33/COUT td - 0.202 - 9.166 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_3/gateop_A2/Y0 + 0.044 + 8.222 + r + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/Cout net (fanout=1) - 0.360 - 9.526 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [2] - - - CLMA_30_160/Y3 - td - 0.151 - 9.677 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[2]/gateop_perm/Z - - - - net (fanout=4) - 0.451 - 10.128 + 0.000 + 8.222 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al [2] + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16578 - CLMA_30_172/COUT + CLMS_50_37/Y1 td - 0.387 - 10.515 + 0.383 + 8.605 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_3/gateop_A2/Cout + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/Y1 net (fanout=1) - 0.000 - 10.515 + 0.325 + 8.930 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14576 + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11 [5] - CLMA_30_176/Y0 + CLMA_58_29/Y1 td - 0.206 - 10.721 + 0.360 + 9.290 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_5/gateop/Y + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[5]/gateop_perm/Z - net (fanout=4) - 0.996 - 11.717 + net (fanout=3) + 0.392 + 9.682 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mc_rl [4] + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/rrptr [5] - CLMA_30_248/Y0 + CLMA_58_36/COUT td - 0.380 - 12.097 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_159_5/gateop_perm/Z + 0.394 + 10.076 + r + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_2/gateop_A2/Cout - net (fanout=40) - 0.510 - 12.607 + net (fanout=1) + 0.000 + 10.076 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24196 + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.co [6] - CLMA_34_268/Y3 + CLMA_58_40/Y1 td - 0.360 - 12.967 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_170[10]/gateop/F + 0.383 + 10.459 + r + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_4/gateop_A2/Y1 net (fanout=1) - 0.484 - 13.451 + 0.072 + 10.531 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24367 + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21 - CLMS_22_265/B3 + CLMA_58_40/C4 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/S0 + r + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/L4
- +
Location Delay Type @@ -115221,10 +120114,10 @@ Logical Resource - Clock ddrphy_clkin (rising edge) + Clock clk_50m (rising edge) - 10.000 - 10.000 + 20.000 + 20.000 r @@ -115232,7 +120125,7 @@ P200.000 - 10.000 + 20.000rclk (port) @@ -115240,7 +120133,7 @@ net (fanout=1) 0.074 - 10.074 + 20.074 clk @@ -115248,7 +120141,7 @@ IOBS_LR_328_209/DIN td 1.285 - 11.359 + 21.359 r clk_ibuf/opit_0/O @@ -115256,7 +120149,7 @@ net (fanout=1) 0.000 - 11.359 + 21.359 clk_ibuf/ntD @@ -115264,7 +120157,7 @@ IOL_327_210/INCK td 0.038 - 11.397 + 21.397 r clk_ibuf/opit_1/INCK @@ -115272,119 +120165,55 @@ net (fanout=1) 0.463 - 11.860 + 21.860 _N69 - PLL_158_55/CLK_OUT1 + PLL_158_55/CLK_OUT0 td - 0.074 - 11.934 + 0.078 + 21.938 r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 + u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 0.603 - 12.537 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 12.537 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 0.981 - 13.518 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.089 - 13.607 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 0.669 - 14.276 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.200 - 14.476 - r - clkgate_8/gopclkgate/OUT - - - - net (fanout=1) - 0.000 - 14.476 - - ntclkgate_0 - - - IOCKDIV_6_323/CLK_IODIV - td - 0.000 - 14.476 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV - - - - net (fanout=1) - 1.283 - 15.759 + 22.541 - u_axi_ddr_top/clk + rd3_clk - USCM_84_116/CLK_USCM + USCM_84_108/CLK_USCM td 0.000 - 15.759 + 22.541 r - clkbufg_0/gopclkbufg/CLKOUT + clkbufg_1/gopclkbufg/CLKOUT - net (fanout=5464) - 1.005 - 16.764 + net (fanout=2516) + 0.907 + 23.448 - ntclkbufg_0 + ntclkbufg_1 - CLMS_22_265/CLK + CLMA_58_40/CLK r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/opit_0_inv_MUX4TO1Q/CLK + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK clock pessimism - 0.417 - 17.181 + 0.281 + 23.729 @@ -115392,15 +120221,15 @@ clock uncertainty -0.150 - 17.031 + 23.579 Setup time - -0.287 - 16.744 + -0.094 + 23.485 @@ -115409,27 +120238,27 @@ - 3.916 - 3 - 4 - u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L0 + 13.358 + 5 + 6 + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/Cin - hdmi_in_clk - hdmi_in_clk + clk_50m + clk_50m rise-rise - -0.019 - 4.020 - 3.724 - 0.277 - 6.666 - 2.331 - 1.006 (43.2%) - 1.325 (56.8%) + -0.039 + 3.764 + 3.444 + 0.281 + 20.000 + 6.177 + 3.542 (57.3%) + 2.635 (42.7%) - Path #17: setup slack is 3.916(MET) + Path #32: setup slack is 13.358(MET) -
+
Location Delay Type @@ -115439,7 +120268,7 @@ Logical Resource - Clock hdmi_in_clk (rising edge) + Clock clk_50m (rising edge) 0.000 0.000 @@ -115447,201 +120276,217 @@ - AA12 + P20 0.000 0.000 r - hdmi_in_clk (port) + clk (port) net (fanout=1) - 0.078 - 0.078 + 0.074 + 0.074 - hdmi_in_clk + clk - IOBD_161_0/DIN + IOBS_LR_328_209/DIN td 1.504 - 1.582 + 1.578 r - hdmi_in_clk_ibuf/opit_0/O + clk_ibuf/opit_0/O net (fanout=1) 0.000 - 1.582 + 1.578 - hdmi_in_clk_ibuf/ntD + clk_ibuf/ntD - IOL_163_6/INCK + IOL_327_210/INCK td 0.058 - 1.640 + 1.636 r - hdmi_in_clk_ibuf/opit_1/INCK + clk_ibuf/opit_1/INCK net (fanout=1) - 1.455 - 3.095 + 0.478 + 2.114 - _N37 + _N69 - USCM_84_111/CLK_USCM + PLL_158_55/CLK_OUT0 + td + 0.083 + 2.197 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 0.614 + 2.811 + + rd3_clk + + + USCM_84_108/CLK_USCM td 0.000 - 3.095 + 2.811 r - clkbufg_4/gopclkbufg/CLKOUT + clkbufg_1/gopclkbufg/CLKOUT - net (fanout=167) - 0.925 - 4.020 + net (fanout=2516) + 0.953 + 3.764 - ntclkbufg_4 + ntclkbufg_1 - CLMA_146_68/CLK + DRM_54_24/CLKB[0] r - u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB - CLMA_146_68/Q0 + DRM_54_24/QB0[0] tco - 0.221 - 4.241 + 1.780 + 5.544 f - u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/Q + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/DOB[0] - net (fanout=4) - 1.078 - 5.319 + net (fanout=6) + 0.982 + 6.526 - wr1_data_in_valid + u_rotate_image/dout [0] - + CLMS_74_117/Y1 td - 0.222 - 5.541 + 0.359 + 6.885 f - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Cout + u_rotate_image/addr_fifo_valid/opit_0_L5Q_perm/Z - - net (fanout=1) - 0.000 - 5.541 + + net (fanout=3) + 1.071 + 7.956 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16001 + u_rotate_image/addr_fifo_rd_en - CLMA_70_96/COUT + td - 0.044 - 5.585 - r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/Cout + 0.222 + 8.178 + f + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/Cout net (fanout=1) 0.000 - 5.585 + 8.178 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16003 + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16576 - + CLMS_50_33/COUT td 0.044 - 5.629 + 8.222 r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/Cout + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/Cout net (fanout=1) 0.000 - 5.629 + 8.222 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16005 + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16578 - CLMA_70_100/COUT + CLMS_50_37/Y1 td - 0.044 - 5.673 + 0.383 + 8.605 r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/Cout + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/Y1 net (fanout=1) - 0.000 - 5.673 + 0.325 + 8.930 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16007 + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11 [5] - + CLMA_58_29/Y1 td - 0.044 - 5.717 - r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/Cout + 0.360 + 9.290 + f + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[5]/gateop_perm/Z - net (fanout=1) - 0.000 - 5.717 + net (fanout=3) + 0.257 + 9.547 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16009 + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/rrptr [5] - CLMA_70_104/Y3 + CLMA_62_32/COUT td - 0.387 - 6.104 + 0.394 + 9.941 r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_A2Q21/Y1 + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N24.eq_2/gateop_A2/Cout - net (fanout=3) - 0.247 - 6.351 + net (fanout=1) + 0.000 + 9.941 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2 [11] + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N24.co [6] - CLMA_66_104/C0 + CLMA_62_36/CIN r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/L0 + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/Cin
- +
Location Delay Type @@ -115651,106 +120496,122 @@ Logical Resource - Clock hdmi_in_clk (rising edge) + Clock clk_50m (rising edge) - 6.666 - 6.666 + 20.000 + 20.000 r - AA12 + P20 0.000 - 6.666 + 20.000 r - hdmi_in_clk (port) + clk (port) net (fanout=1) - 0.078 - 6.744 + 0.074 + 20.074 - hdmi_in_clk + clk - IOBD_161_0/DIN + IOBS_LR_328_209/DIN td 1.285 - 8.029 + 21.359 r - hdmi_in_clk_ibuf/opit_0/O + clk_ibuf/opit_0/O net (fanout=1) 0.000 - 8.029 + 21.359 - hdmi_in_clk_ibuf/ntD + clk_ibuf/ntD - IOL_163_6/INCK + IOL_327_210/INCK td 0.038 - 8.067 + 21.397 r - hdmi_in_clk_ibuf/opit_1/INCK + clk_ibuf/opit_1/INCK net (fanout=1) - 1.428 - 9.495 + 0.463 + 21.860 - _N37 + _N69 - USCM_84_111/CLK_USCM + PLL_158_55/CLK_OUT0 + td + 0.078 + 21.938 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 0.603 + 22.541 + + rd3_clk + + + USCM_84_108/CLK_USCM td 0.000 - 9.495 + 22.541 r - clkbufg_4/gopclkbufg/CLKOUT + clkbufg_1/gopclkbufg/CLKOUT - net (fanout=167) - 0.895 - 10.390 + net (fanout=2516) + 0.903 + 23.444 - ntclkbufg_4 + ntclkbufg_1 - CLMA_66_104/CLK + CLMA_62_36/CLK r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/opit_0_L5Q_perm/CLK + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/CLK clock pessimism - 0.277 - 10.667 + 0.281 + 23.725 clock uncertainty - -0.250 - 10.417 + -0.150 + 23.575 Setup time - -0.150 - 10.267 + -0.276 + 23.299 @@ -115759,27 +120620,27 @@ - 3.972 - 3 - 4 - u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm/L4 + 13.459 + 5 + 6 + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[11]/opit_0_A2Q21/Cin - hdmi_in_clk - hdmi_in_clk + clk_50m + clk_50m rise-rise - -0.019 - 4.020 - 3.724 - 0.277 - 6.666 - 2.331 - 1.006 (43.2%) - 1.325 (56.8%) + -0.035 + 3.764 + 3.448 + 0.281 + 20.000 + 6.228 + 3.486 (56.0%) + 2.742 (44.0%) - Path #18: setup slack is 3.972(MET) + Path #33: setup slack is 13.459(MET) -
+
Location Delay Type @@ -115789,7 +120650,7 @@ Logical Resource - Clock hdmi_in_clk (rising edge) + Clock clk_50m (rising edge) 0.000 0.000 @@ -115797,201 +120658,249 @@ - AA12 + P20 0.000 0.000 r - hdmi_in_clk (port) + clk (port) net (fanout=1) - 0.078 - 0.078 + 0.074 + 0.074 - hdmi_in_clk + clk - IOBD_161_0/DIN + IOBS_LR_328_209/DIN td 1.504 - 1.582 + 1.578 r - hdmi_in_clk_ibuf/opit_0/O + clk_ibuf/opit_0/O net (fanout=1) 0.000 - 1.582 + 1.578 - hdmi_in_clk_ibuf/ntD + clk_ibuf/ntD - IOL_163_6/INCK + IOL_327_210/INCK td 0.058 - 1.640 + 1.636 r - hdmi_in_clk_ibuf/opit_1/INCK + clk_ibuf/opit_1/INCK net (fanout=1) - 1.455 - 3.095 + 0.478 + 2.114 - _N37 + _N69 - USCM_84_111/CLK_USCM + PLL_158_55/CLK_OUT0 + td + 0.083 + 2.197 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 0.614 + 2.811 + + rd3_clk + + + USCM_84_108/CLK_USCM td 0.000 - 3.095 + 2.811 r - clkbufg_4/gopclkbufg/CLKOUT + clkbufg_1/gopclkbufg/CLKOUT - net (fanout=167) - 0.925 - 4.020 + net (fanout=2516) + 0.953 + 3.764 - ntclkbufg_4 + ntclkbufg_1 - CLMA_146_68/CLK + DRM_54_24/CLKB[0] r - u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/CLK + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB - CLMA_146_68/Q0 + DRM_54_24/QB0[0] tco - 0.221 - 4.241 + 1.780 + 5.544 f - u_hdmi_in_top/hdmi_data_valid0/opit_0_L5Q_perm/Q + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/DOB[0] - net (fanout=4) - 1.078 - 5.319 + net (fanout=6) + 0.982 + 6.526 - wr1_data_in_valid + u_rotate_image/dout [0] + + + CLMS_74_117/Y1 + td + 0.359 + 6.885 + f + u_rotate_image/addr_fifo_valid/opit_0_L5Q_perm/Z + + + + net (fanout=3) + 1.071 + 7.956 + + u_rotate_image/addr_fifo_rd_en td 0.222 - 5.541 + 8.178 f - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Cout + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/Cout net (fanout=1) 0.000 - 5.541 + 8.178 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16001 + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16576 - CLMA_70_96/COUT + CLMS_50_33/COUT td 0.044 - 5.585 + 8.222 r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/opit_0_inv_A2Q21/Cout + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/Cout net (fanout=1) 0.000 - 5.585 + 8.222 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16003 + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16578 - + CLMS_50_37/Y1 td - 0.044 - 5.629 + 0.383 + 8.605 r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/Cout + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/Y1 net (fanout=1) - 0.000 - 5.629 + 0.325 + 8.930 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16005 + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11 [5] - CLMA_70_100/COUT + CLMA_58_29/Y1 td - 0.044 - 5.673 - r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_A2Q21/Cout + 0.360 + 9.290 + f + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[5]/gateop_perm/Z + + + + net (fanout=3) + 0.364 + 9.654 + + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/rrptr [5] + + + + td + 0.250 + 9.904 + f + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[5]/opit_0_A2Q21/Cout net (fanout=1) 0.000 - 5.673 + 9.904 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16007 + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N138_5.co [6] - + CLMA_58_37/COUT td 0.044 - 5.717 + 9.948 r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/Cout + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[7]/opit_0_A2Q21/Cout net (fanout=1) 0.000 - 5.717 + 9.948 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16009 + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N138_5.co [8] - CLMA_70_104/Y3 + td - 0.387 - 6.104 + 0.044 + 9.992 r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/opit_0_inv_A2Q21/Y1 + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[9]/opit_0_A2Q21/Cout - net (fanout=3) - 0.247 - 6.351 + net (fanout=1) + 0.000 + 9.992 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2 [11] + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N138_5.co [10] - CLMS_66_105/C4 + r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm/L4 + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[11]/opit_0_A2Q21/Cin
- +
Location Delay Type @@ -116001,106 +120910,122 @@ Logical Resource - Clock hdmi_in_clk (rising edge) + Clock clk_50m (rising edge) - 6.666 - 6.666 + 20.000 + 20.000 r - AA12 + P20 0.000 - 6.666 + 20.000 r - hdmi_in_clk (port) + clk (port) net (fanout=1) - 0.078 - 6.744 + 0.074 + 20.074 - hdmi_in_clk + clk - IOBD_161_0/DIN + IOBS_LR_328_209/DIN td 1.285 - 8.029 + 21.359 r - hdmi_in_clk_ibuf/opit_0/O + clk_ibuf/opit_0/O net (fanout=1) 0.000 - 8.029 + 21.359 - hdmi_in_clk_ibuf/ntD + clk_ibuf/ntD - IOL_163_6/INCK + IOL_327_210/INCK td 0.038 - 8.067 + 21.397 r - hdmi_in_clk_ibuf/opit_1/INCK + clk_ibuf/opit_1/INCK net (fanout=1) - 1.428 - 9.495 + 0.463 + 21.860 - _N37 + _N69 - USCM_84_111/CLK_USCM + PLL_158_55/CLK_OUT0 + td + 0.078 + 21.938 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 0.603 + 22.541 + + rd3_clk + + + USCM_84_108/CLK_USCM td 0.000 - 9.495 + 22.541 r - clkbufg_4/gopclkbufg/CLKOUT + clkbufg_1/gopclkbufg/CLKOUT - net (fanout=167) - 0.895 - 10.390 + net (fanout=2516) + 0.907 + 23.448 - ntclkbufg_4 + ntclkbufg_1 - CLMS_66_105/CLK + CLMA_58_41/CLK r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/opit_0_L5Q_perm/CLK + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[11]/opit_0_A2Q21/CLK clock pessimism - 0.277 - 10.667 + 0.281 + 23.729 clock uncertainty - -0.250 - 10.417 + -0.150 + 23.579 Setup time - -0.094 - 10.323 + -0.128 + 23.451 @@ -116109,27 +121034,27 @@ - 6.092 - 2 - 1 - cmos2_data[7] - u_ov5640/cmos2_d_d0[7]/opit_0/D + 36.784 + 4 + 13 + u_ov5640/coms2_reg_config/clock_20k_cnt[4]/opit_0_inv/CLK + u_ov5640/coms2_reg_config/clock_20k_cnt[10]/opit_0_inv/D - cmos2_pclk - cmos2_pclk + clk_25m + clk_25m rise-rise - 3.512 - 0.000 - 3.512 - 0.000 - 11.900 - 8.002 - 1.146 (14.3%) - 6.856 (85.7%) + -0.019 + 3.741 + 3.441 + 0.281 + 40.000 + 2.979 + 1.509 (50.7%) + 1.470 (49.3%) - Path #19: setup slack is 6.092(MET) + Path #34: setup slack is 36.784(MET) -
+
Location Delay Type @@ -116139,7 +121064,7 @@ Logical Resource - Clock cmos2_pclk (rising edge) + Clock clk_25m (rising edge) 0.000 0.000 @@ -116147,295 +121072,201 @@ - Input external delay - - 1.000 - 1.000 - f - - - - AB9 - + P20 + 0.000 - 1.000 - f - cmos2_data[7] (port) - - - - net (fanout=1) - 0.080 - 1.080 - - cmos2_data[7] - - - IOBS_TB_128_0/DIN - td - 1.049 - 2.129 - f - cmos2_data_ibuf[7]/opit_0/O - - - - net (fanout=1) 0.000 - 2.129 - - cmos2_data_ibuf[7]/ntD - - - IOL_131_5/RX_DATA_DD - td - 0.097 - 2.226 - f - cmos2_data_ibuf[7]/opit_1/OUT + r + clk (port) net (fanout=1) - 6.776 - 9.002 - - nt_cmos2_data[7] - - - CLMS_130_37/M2 - - - - f - u_ov5640/cmos2_d_d0[7]/opit_0/D - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock cmos2_pclk (rising edge) - - 11.900 - 11.900 - r + 0.074 + 0.074 + clk - W6 - - 0.000 - 11.900 + IOBS_LR_328_209/DIN + td + 1.504 + 1.578 r - cmos2_pclk (port) + clk_ibuf/opit_0/O net (fanout=1) - 0.071 - 11.971 + 0.000 + 1.578 - cmos2_pclk + clk_ibuf/ntD - IOBD_37_0/DIN + IOL_327_210/INCK td - 0.735 - 12.706 + 0.058 + 1.636 r - cmos2_pclk_ibuf/opit_0/O + clk_ibuf/opit_1/INCK net (fanout=1) - 0.000 - 12.706 + 0.478 + 2.114 - cmos2_pclk_ibuf/ntD + _N69 - IOL_39_6/RX_DATA_DD + PLL_158_55/CLK_OUT3 td - 0.066 - 12.772 + 0.088 + 2.202 r - cmos2_pclk_ibuf/opit_1/OUT + u_sys_pll/u_pll_e3/goppll/CLKOUT3 net (fanout=1) - 1.745 - 14.517 + 0.614 + 2.816 - nt_cmos2_pclk + clk_25m - USCM_84_118/CLK_USCM + USCM_84_114/CLK_USCM td 0.000 - 14.517 + 2.816 r - clkbufg_6/gopclkbufg/CLKOUT + clkbufg_8/gopclkbufg/CLKOUT - net (fanout=118) - 0.895 - 15.412 + net (fanout=26) + 0.925 + 3.741 - ntclkbufg_6 + ntclkbufg_8 - CLMS_130_37/CLK + CLMS_118_17/CLK r - u_ov5640/cmos2_d_d0[7]/opit_0/CLK + u_ov5640/coms2_reg_config/clock_20k_cnt[4]/opit_0_inv/CLK - clock pessimism - - 0.000 - 15.412 - - + CLMS_118_17/Q1 + tco + 0.223 + 3.964 + f + u_ov5640/coms2_reg_config/clock_20k_cnt[4]/opit_0_inv/Q - clock uncertainty - - -0.250 - 15.162 - + net (fanout=2) + 0.262 + 4.226 + + u_ov5640/coms2_reg_config/clock_20k_cnt [4] - Setup time - - -0.068 - 15.094 - - + CLMA_122_16/Y3 + td + 0.358 + 4.584 + f + u_ov5640/coms2_reg_config/N8_mux4_5/gateop_perm/Z -
-
-
-
- - 6.333 - 2 - 1 - cmos2_data[5] - u_ov5640/cmos2_d_d0[5]/opit_0/D - - cmos2_pclk - cmos2_pclk - rise-rise - 3.512 - 0.000 - 3.512 - 0.000 - 11.900 - 7.761 - 1.146 (14.8%) - 6.615 (85.2%) - - Path #20: setup slack is 6.333(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - Clock cmos2_pclk (rising edge) - - 0.000 - 0.000 - r + net (fanout=1) + 0.365 + 4.949 + + u_ov5640/coms2_reg_config/_N9749 - Input external delay - - 1.000 - 1.000 + CLMA_122_16/Y2 + td + 0.150 + 5.099 f + u_ov5640/coms2_reg_config/N8_mux10/gateop_perm/Z + + + net (fanout=13) + 0.372 + 5.471 + + u_ov5640/coms2_reg_config/N8 - AB8 - 0.000 - 1.000 + td + 0.368 + 5.839 f - cmos2_data[5] (port) + u_ov5640/coms2_reg_config/N11_2_5/gateop_A2/Cout net (fanout=1) - 0.084 - 1.084 + 0.000 + 5.839 - cmos2_data[5] + u_ov5640/coms2_reg_config/_N16307 - IOBS_TB_116_0/DIN + CLMS_122_17/COUT td - 1.049 - 2.133 - f - cmos2_data_ibuf[5]/opit_0/O + 0.044 + 5.883 + r + u_ov5640/coms2_reg_config/N11_2_7/gateop_A2/Cout net (fanout=1) 0.000 - 2.133 + 5.883 - cmos2_data_ibuf[5]/ntD + u_ov5640/coms2_reg_config/_N16309 - IOL_119_5/RX_DATA_DD + CLMS_122_21/Y1 td - 0.097 - 2.230 + 0.366 + 6.249 f - cmos2_data_ibuf[5]/opit_1/OUT + u_ov5640/coms2_reg_config/N11_2_9/gateop_A2/Y1 net (fanout=1) - 6.531 - 8.761 + 0.471 + 6.720 - nt_cmos2_data[5] + u_ov5640/coms2_reg_config/N1114 [10] - CLMA_134_40/M0 + CLMS_122_17/M3 f - u_ov5640/cmos2_d_d0[5]/opit_0/D + u_ov5640/coms2_reg_config/clock_20k_cnt[10]/opit_0_inv/D
- +
Location Delay Type @@ -116445,98 +121276,114 @@ Logical Resource - Clock cmos2_pclk (rising edge) + Clock clk_25m (rising edge) - 11.900 - 11.900 + 40.000 + 40.000 r - W6 + P20 0.000 - 11.900 + 40.000 r - cmos2_pclk (port) + clk (port) net (fanout=1) - 0.071 - 11.971 + 0.074 + 40.074 - cmos2_pclk + clk - IOBD_37_0/DIN + IOBS_LR_328_209/DIN td - 0.735 - 12.706 + 1.285 + 41.359 r - cmos2_pclk_ibuf/opit_0/O + clk_ibuf/opit_0/O net (fanout=1) 0.000 - 12.706 + 41.359 - cmos2_pclk_ibuf/ntD + clk_ibuf/ntD - IOL_39_6/RX_DATA_DD + IOL_327_210/INCK td - 0.066 - 12.772 + 0.038 + 41.397 r - cmos2_pclk_ibuf/opit_1/OUT + clk_ibuf/opit_1/INCK net (fanout=1) - 1.745 - 14.517 + 0.463 + 41.860 - nt_cmos2_pclk + _N69 - USCM_84_118/CLK_USCM + PLL_158_55/CLK_OUT3 + td + 0.083 + 41.943 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT3 + + + + net (fanout=1) + 0.603 + 42.546 + + clk_25m + + + USCM_84_114/CLK_USCM td 0.000 - 14.517 + 42.546 r - clkbufg_6/gopclkbufg/CLKOUT + clkbufg_8/gopclkbufg/CLKOUT - net (fanout=118) + net (fanout=26) 0.895 - 15.412 + 43.441 - ntclkbufg_6 + ntclkbufg_8 - CLMA_134_40/CLK + CLMS_122_17/CLK r - u_ov5640/cmos2_d_d0[5]/opit_0/CLK + u_ov5640/coms2_reg_config/clock_20k_cnt[10]/opit_0_inv/CLK clock pessimism - 0.000 - 15.412 + 0.281 + 43.722 clock uncertainty - -0.250 - 15.162 + -0.150 + 43.572 @@ -116544,7 +121391,7 @@ Setup time -0.068 - 15.094 + 43.504 @@ -116553,27 +121400,27 @@ - 6.646 + 36.812 3 - 1 - cmos2_data[6] - u_ov5640/cmos2_d_d0[6]/opit_0/D + 13 + u_ov5640/coms2_reg_config/clock_20k_cnt[4]/opit_0_inv/CLK + u_ov5640/coms2_reg_config/clock_20k_cnt[8]/opit_0_inv/D - cmos2_pclk - cmos2_pclk + clk_25m + clk_25m rise-rise - 3.512 - 0.000 - 3.512 - 0.000 - 11.900 - 7.448 - 1.247 (16.7%) - 6.201 (83.3%) + -0.019 + 3.741 + 3.441 + 0.281 + 40.000 + 2.951 + 1.464 (49.6%) + 1.487 (50.4%) - Path #21: setup slack is 6.646(MET) + Path #35: setup slack is 36.812(MET) -
+
Location Delay Type @@ -116583,7 +121430,7 @@ Logical Resource - Clock cmos2_pclk (rising edge) + Clock clk_25m (rising edge) 0.000 0.000 @@ -116591,311 +121438,185 @@ - Input external delay - - 1.000 - 1.000 - f - - - - Y9 - + P20 + 0.000 - 1.000 - f - cmos2_data[6] (port) - - - - net (fanout=1) - 0.078 - 1.078 - - cmos2_data[6] - - - IOBD_129_0/DIN - td - 1.049 - 2.127 - f - cmos2_data_ibuf[6]/opit_0/O - - - - net (fanout=1) 0.000 - 2.127 - - cmos2_data_ibuf[6]/ntD - - - IOL_131_6/RX_DATA_DD - td - 0.097 - 2.224 - f - cmos2_data_ibuf[6]/opit_1/OUT - - - - net (fanout=1) - 0.831 - 3.055 - - nt_cmos2_data[6] - - - CLMA_94_8/Y6AB - td - 0.101 - 3.156 - f - CLKROUTE_2/Z + r + clk (port) net (fanout=1) - 5.292 - 8.448 - - ntR3903 - - - CLMA_134_40/M1 - - - - f - u_ov5640/cmos2_d_d0[6]/opit_0/D - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock cmos2_pclk (rising edge) - - 11.900 - 11.900 - r + 0.074 + 0.074 + clk - W6 - - 0.000 - 11.900 + IOBS_LR_328_209/DIN + td + 1.504 + 1.578 r - cmos2_pclk (port) + clk_ibuf/opit_0/O net (fanout=1) - 0.071 - 11.971 + 0.000 + 1.578 - cmos2_pclk + clk_ibuf/ntD - IOBD_37_0/DIN + IOL_327_210/INCK td - 0.735 - 12.706 + 0.058 + 1.636 r - cmos2_pclk_ibuf/opit_0/O + clk_ibuf/opit_1/INCK net (fanout=1) - 0.000 - 12.706 + 0.478 + 2.114 - cmos2_pclk_ibuf/ntD + _N69 - IOL_39_6/RX_DATA_DD + PLL_158_55/CLK_OUT3 td - 0.066 - 12.772 + 0.088 + 2.202 r - cmos2_pclk_ibuf/opit_1/OUT + u_sys_pll/u_pll_e3/goppll/CLKOUT3 net (fanout=1) - 1.745 - 14.517 + 0.614 + 2.816 - nt_cmos2_pclk + clk_25m - USCM_84_118/CLK_USCM + USCM_84_114/CLK_USCM td 0.000 - 14.517 + 2.816 r - clkbufg_6/gopclkbufg/CLKOUT + clkbufg_8/gopclkbufg/CLKOUT - net (fanout=118) - 0.895 - 15.412 + net (fanout=26) + 0.925 + 3.741 - ntclkbufg_6 + ntclkbufg_8 - CLMA_134_40/CLK + CLMS_118_17/CLK r - u_ov5640/cmos2_d_d0[6]/opit_0/CLK - - - clock pessimism - - 0.000 - 15.412 - - + u_ov5640/coms2_reg_config/clock_20k_cnt[4]/opit_0_inv/CLK - clock uncertainty - - -0.250 - 15.162 - - + CLMS_118_17/Q1 + tco + 0.223 + 3.964 + f + u_ov5640/coms2_reg_config/clock_20k_cnt[4]/opit_0_inv/Q - Setup time - - -0.068 - 15.094 - + net (fanout=2) + 0.262 + 4.226 + + u_ov5640/coms2_reg_config/clock_20k_cnt [4] -
-
-
-
- - 6.761 - 2 - 1 - cmos1_data[4] - u_ov5640/cmos1_d_d0[4]/opit_0/D - - cmos1_pclk - cmos1_pclk - rise-rise - 3.172 - 0.000 - 3.172 - 0.000 - 11.900 - 7.085 - 1.146 (16.2%) - 5.939 (83.8%) - - Path #22: setup slack is 6.761(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - Clock cmos1_pclk (rising edge) - - 0.000 - 0.000 - r - + CLMA_122_16/Y3 + td + 0.358 + 4.584 + f + u_ov5640/coms2_reg_config/N8_mux4_5/gateop_perm/Z - Input external delay - - 1.000 - 1.000 - f + net (fanout=1) + 0.365 + 4.949 + + u_ov5640/coms2_reg_config/_N9749 - W11 - - 0.000 - 1.000 + CLMA_122_16/Y2 + td + 0.150 + 5.099 f - cmos1_data[4] (port) + u_ov5640/coms2_reg_config/N8_mux10/gateop_perm/Z - net (fanout=1) - 0.041 - 1.041 + net (fanout=13) + 0.372 + 5.471 - cmos1_data[4] + u_ov5640/coms2_reg_config/N8 - IOBS_TB_132_0/DIN + td - 1.049 - 2.090 + 0.368 + 5.839 f - cmos1_data_ibuf[4]/opit_0/O + u_ov5640/coms2_reg_config/N11_2_5/gateop_A2/Cout net (fanout=1) 0.000 - 2.090 + 5.839 - cmos1_data_ibuf[4]/ntD + u_ov5640/coms2_reg_config/_N16307 - IOL_135_5/RX_DATA_DD + CLMS_122_17/Y3 td - 0.097 - 2.187 + 0.365 + 6.204 f - cmos1_data_ibuf[4]/opit_1/OUT + u_ov5640/coms2_reg_config/N11_2_7/gateop_A2/Y1 net (fanout=1) - 5.898 - 8.085 + 0.488 + 6.692 - nt_cmos1_data[4] + u_ov5640/coms2_reg_config/N1114 [8] - CLMS_134_13/AD + CLMS_122_17/M2 f - u_ov5640/cmos1_d_d0[4]/opit_0/D + u_ov5640/coms2_reg_config/clock_20k_cnt[8]/opit_0_inv/D
- +
Location Delay Type @@ -116905,106 +121626,122 @@ Logical Resource - Clock cmos1_pclk (rising edge) + Clock clk_25m (rising edge) - 11.900 - 11.900 + 40.000 + 40.000 r - T12 + P20 0.000 - 11.900 + 40.000 r - cmos1_pclk (port) + clk (port) net (fanout=1) - 0.076 - 11.976 + 0.074 + 40.074 - cmos1_pclk + clk - IOBD_169_0/DIN + IOBS_LR_328_209/DIN td - 0.735 - 12.711 + 1.285 + 41.359 r - cmos1_pclk_ibuf/opit_0/O + clk_ibuf/opit_0/O net (fanout=1) 0.000 - 12.711 + 41.359 - cmos1_pclk_ibuf/ntD + clk_ibuf/ntD - IOL_171_6/INCK + IOL_327_210/INCK td 0.038 - 12.749 + 41.397 r - cmos1_pclk_ibuf/opit_1/INCK + clk_ibuf/opit_1/INCK net (fanout=1) - 1.428 - 14.177 + 0.463 + 41.860 - _N64 + _N69 - USCM_84_112/CLK_USCM + PLL_158_55/CLK_OUT3 + td + 0.083 + 41.943 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT3 + + + + net (fanout=1) + 0.603 + 42.546 + + clk_25m + + + USCM_84_114/CLK_USCM td 0.000 - 14.177 + 42.546 r - clkbufg_5/gopclkbufg/CLKOUT + clkbufg_8/gopclkbufg/CLKOUT - net (fanout=118) + net (fanout=26) 0.895 - 15.072 + 43.441 - ntclkbufg_5 + ntclkbufg_8 - CLMS_134_13/CLK + CLMS_122_17/CLK r - u_ov5640/cmos1_d_d0[4]/opit_0/CLK + u_ov5640/coms2_reg_config/clock_20k_cnt[8]/opit_0_inv/CLK clock pessimism - 0.000 - 15.072 + 0.281 + 43.722 clock uncertainty - -0.250 - 14.822 + -0.150 + 43.572 Setup time - 0.024 - 14.846 + -0.068 + 43.504 @@ -117013,27 +121750,27 @@ - 6.838 - 2 - 1 - cmos1_href - u_ov5640/cmos1_href_d0/opit_0/D + 36.944 + 4 + 13 + u_ov5640/coms2_reg_config/clock_20k_cnt[4]/opit_0_inv/CLK + u_ov5640/coms2_reg_config/clock_20k_cnt[9]/opit_0_inv/D - cmos1_pclk - cmos1_pclk + clk_25m + clk_25m rise-rise - 3.172 - 0.000 - 3.172 - 0.000 - 11.900 - 7.008 - 1.015 (14.5%) - 5.993 (85.5%) + -0.019 + 3.741 + 3.441 + 0.281 + 40.000 + 2.819 + 1.349 (47.9%) + 1.470 (52.1%) - Path #23: setup slack is 6.838(MET) + Path #36: setup slack is 36.944(MET) -
+
Location Delay Type @@ -117043,81 +121780,209 @@ Logical Resource - Clock cmos1_pclk (rising edge) + Clock clk_25m (rising edge) + + 0.000 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.504 + 1.578 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.578 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.058 + 1.636 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.478 + 2.114 + + _N69 + + + PLL_158_55/CLK_OUT3 + td + 0.088 + 2.202 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT3 + + + net (fanout=1) + 0.614 + 2.816 + + clk_25m + + + USCM_84_114/CLK_USCM + td 0.000 - 0.000 + 2.816 r + clkbufg_8/gopclkbufg/CLKOUT + + + + net (fanout=26) + 0.925 + 3.741 + ntclkbufg_8 - Input external delay + CLMS_118_17/CLK - 1.000 - 1.000 - f + + r + u_ov5640/coms2_reg_config/clock_20k_cnt[4]/opit_0_inv/CLK - AB10 + CLMS_118_17/Q1 + tco + 0.223 + 3.964 + f + u_ov5640/coms2_reg_config/clock_20k_cnt[4]/opit_0_inv/Q + + + + net (fanout=2) + 0.262 + 4.226 - 0.000 - 1.000 + u_ov5640/coms2_reg_config/clock_20k_cnt [4] + + + CLMA_122_16/Y3 + td + 0.358 + 4.584 f - cmos1_href (port) + u_ov5640/coms2_reg_config/N8_mux4_5/gateop_perm/Z net (fanout=1) - 0.063 - 1.063 + 0.365 + 4.949 - cmos1_href + u_ov5640/coms2_reg_config/_N9749 - IOBR_TB_148_0/DIN + CLMA_122_16/Y2 td - 0.918 - 1.981 + 0.150 + 5.099 f - cmos1_href_ibuf/opit_0/O + u_ov5640/coms2_reg_config/N8_mux10/gateop_perm/Z + + + + net (fanout=13) + 0.372 + 5.471 + + u_ov5640/coms2_reg_config/N8 + + + + td + 0.368 + 5.839 + f + u_ov5640/coms2_reg_config/N11_2_5/gateop_A2/Cout net (fanout=1) 0.000 - 1.981 + 5.839 - cmos1_href_ibuf/ntD + u_ov5640/coms2_reg_config/_N16307 - IOL_151_5/RX_DATA_DD + CLMS_122_17/COUT td - 0.097 - 2.078 + 0.044 + 5.883 + r + u_ov5640/coms2_reg_config/N11_2_7/gateop_A2/Cout + + + + net (fanout=1) + 0.000 + 5.883 + + u_ov5640/coms2_reg_config/_N16309 + + + CLMS_122_21/Y0 + td + 0.206 + 6.089 f - cmos1_href_ibuf/opit_1/OUT + u_ov5640/coms2_reg_config/N11_2_9/gateop_A2/Y0 net (fanout=1) - 5.930 - 8.008 + 0.471 + 6.560 - nt_cmos1_href + u_ov5640/coms2_reg_config/N1114 [9] - CLMS_146_9/AD + CLMS_122_17/M1 f - u_ov5640/cmos1_href_d0/opit_0/D + u_ov5640/coms2_reg_config/clock_20k_cnt[9]/opit_0_inv/D
- +
Location Delay Type @@ -117127,106 +121992,122 @@ Logical Resource - Clock cmos1_pclk (rising edge) + Clock clk_25m (rising edge) - 11.900 - 11.900 + 40.000 + 40.000 r - T12 + P20 0.000 - 11.900 + 40.000 r - cmos1_pclk (port) + clk (port) net (fanout=1) - 0.076 - 11.976 + 0.074 + 40.074 - cmos1_pclk + clk - IOBD_169_0/DIN + IOBS_LR_328_209/DIN td - 0.735 - 12.711 + 1.285 + 41.359 r - cmos1_pclk_ibuf/opit_0/O + clk_ibuf/opit_0/O net (fanout=1) 0.000 - 12.711 + 41.359 - cmos1_pclk_ibuf/ntD + clk_ibuf/ntD - IOL_171_6/INCK + IOL_327_210/INCK td 0.038 - 12.749 + 41.397 r - cmos1_pclk_ibuf/opit_1/INCK + clk_ibuf/opit_1/INCK net (fanout=1) - 1.428 - 14.177 + 0.463 + 41.860 - _N64 + _N69 - USCM_84_112/CLK_USCM + PLL_158_55/CLK_OUT3 + td + 0.083 + 41.943 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT3 + + + + net (fanout=1) + 0.603 + 42.546 + + clk_25m + + + USCM_84_114/CLK_USCM td 0.000 - 14.177 + 42.546 r - clkbufg_5/gopclkbufg/CLKOUT + clkbufg_8/gopclkbufg/CLKOUT - net (fanout=118) + net (fanout=26) 0.895 - 15.072 + 43.441 - ntclkbufg_5 + ntclkbufg_8 - CLMS_146_9/CLK + CLMS_122_17/CLK r - u_ov5640/cmos1_href_d0/opit_0/CLK + u_ov5640/coms2_reg_config/clock_20k_cnt[9]/opit_0_inv/CLK clock pessimism - 0.000 - 15.072 + 0.281 + 43.722 clock uncertainty - -0.250 - 14.822 + -0.150 + 43.572 Setup time - 0.024 - 14.846 + -0.068 + 43.504 @@ -117235,27 +122116,27 @@ - 6.914 - 3 - 1 - cmos1_data[5] - u_ov5640/cmos1_d_d0[5]/opit_0/D + 96.148 + 6 + 15 + ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK + ms72xx_ctl/ms7200_ctl/addr[0]/opit_0_inv_L5Q_perm/CE - cmos1_pclk - cmos1_pclk + clk_10m + clk_10m rise-rise - 3.172 - 0.000 - 3.172 - 0.000 - 11.900 - 6.840 - 1.249 (18.3%) - 5.591 (81.7%) + -0.019 + 3.849 + 3.547 + 0.283 + 100.000 + 3.107 + 1.428 (46.0%) + 1.679 (54.0%) - Path #24: setup slack is 6.914(MET) + Path #37: setup slack is 96.148(MET) -
+
Location Delay Type @@ -117265,7 +122146,7 @@ Logical Resource - Clock cmos1_pclk (rising edge) + Clock clk_10m (rising edge) 0.000 0.000 @@ -117273,89 +122154,217 @@ - Input external delay + P20 + + 0.000 + 0.000 + r + clk (port) + + - 1.000 - 1.000 - f + net (fanout=1) + 0.074 + 0.074 + clk - AB11 - + IOBS_LR_328_209/DIN + td + 1.504 + 1.578 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) 0.000 - 1.000 - f - cmos1_data[5] (port) + 1.578 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.058 + 1.636 + r + clk_ibuf/opit_1/INCK net (fanout=1) - 0.077 - 1.077 - - cmos1_data[5] + 0.478 + 2.114 + + _N69 - IOBS_TB_156_0/DIN + PLL_158_55/CLK_OUT4 td - 1.049 - 2.126 - f - cmos1_data_ibuf[5]/opit_0/O + 0.084 + 2.198 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT4 net (fanout=1) + 0.614 + 2.812 + + clk_10m + + + USCM_84_110/CLK_USCM + td 0.000 - 2.126 + 2.812 + r + clkbufg_4/gopclkbufg/CLKOUT + + + + net (fanout=235) + 1.037 + 3.849 + + ntclkbufg_4 + + + CLMS_218_329/CLK + + + + r + ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK + + + CLMS_218_329/Q2 + tco + 0.223 + 4.072 + f + ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/Q + + + + net (fanout=3) + 0.174 + 4.246 - cmos1_data_ibuf[5]/ntD + ms72xx_ctl/ms7200_ctl/dri_cnt [4] - IOL_159_5/RX_DATA_DD + CLMS_218_333/Y3 td - 0.097 - 2.223 + 0.358 + 4.604 f - cmos1_data_ibuf[5]/opit_1/OUT + ms72xx_ctl/ms7200_ctl/N8_3/gateop_perm/Z net (fanout=1) - 1.648 - 3.871 + 0.157 + 4.761 - nt_cmos1_data[5] + ms72xx_ctl/ms7200_ctl/_N96627 - CLMS_322_9/Y6CD + CLMS_218_333/Y0 td - 0.103 - 3.974 + 0.150 + 4.911 f - CLKROUTE_0/Z + ms72xx_ctl/ms7200_ctl/N1872_5/gateop_perm/Z - net (fanout=1) - 3.866 - 7.840 + net (fanout=6) + 0.269 + 5.180 + + ms72xx_ctl/ms7200_ctl/_N96632 + + + CLMS_222_329/Y0 + td + 0.150 + 5.330 + f + ms72xx_ctl/ms7200_ctl/N2053_1/gateop_perm/Z + + + + net (fanout=15) + 0.363 + 5.693 + + ms72xx_ctl/ms7200_ctl/N261 + + + CLMS_214_321/Y0 + td + 0.264 + 5.957 + f + ms72xx_ctl/ms7200_ctl/N40_9/gateop_perm/Z + + + + net (fanout=4) + 0.353 + 6.310 + + ms72xx_ctl/ms7200_ctl/N2093 [4] + + + CLMA_222_324/Y1 + td + 0.151 + 6.461 + f + ms72xx_ctl/ms7200_ctl/N1955/gateop_perm/Z + + + + net (fanout=12) + 0.363 + 6.824 + + ms72xx_ctl/ms7200_ctl/N1955 + + + CLMA_230_324/CECO + td + 0.132 + 6.956 + f + ms72xx_ctl/ms7200_ctl/data_in[5]/opit_0_inv_L5Q_perm/CEOUT + + + + net (fanout=4) + 0.000 + 6.956 - ntR3901 + ntR1800 - CLMS_146_9/M0 + CLMA_230_328/CECI f - u_ov5640/cmos1_d_d0[5]/opit_0/D + ms72xx_ctl/ms7200_ctl/addr[0]/opit_0_inv_L5Q_perm/CE
- +
Location Delay Type @@ -117365,106 +122374,122 @@ Logical Resource - Clock cmos1_pclk (rising edge) + Clock clk_10m (rising edge) - 11.900 - 11.900 + 100.000 + 100.000 r - T12 + P20 0.000 - 11.900 + 100.000 r - cmos1_pclk (port) + clk (port) net (fanout=1) - 0.076 - 11.976 + 0.074 + 100.074 - cmos1_pclk + clk - IOBD_169_0/DIN + IOBS_LR_328_209/DIN td - 0.735 - 12.711 + 1.285 + 101.359 r - cmos1_pclk_ibuf/opit_0/O + clk_ibuf/opit_0/O net (fanout=1) 0.000 - 12.711 + 101.359 - cmos1_pclk_ibuf/ntD + clk_ibuf/ntD - IOL_171_6/INCK + IOL_327_210/INCK td 0.038 - 12.749 + 101.397 r - cmos1_pclk_ibuf/opit_1/INCK + clk_ibuf/opit_1/INCK net (fanout=1) - 1.428 - 14.177 + 0.463 + 101.860 - _N64 + _N69 - USCM_84_112/CLK_USCM + PLL_158_55/CLK_OUT4 + td + 0.079 + 101.939 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT4 + + + + net (fanout=1) + 0.603 + 102.542 + + clk_10m + + + USCM_84_110/CLK_USCM td 0.000 - 14.177 + 102.542 r - clkbufg_5/gopclkbufg/CLKOUT + clkbufg_4/gopclkbufg/CLKOUT - net (fanout=118) - 0.895 - 15.072 + net (fanout=235) + 1.005 + 103.547 - ntclkbufg_5 + ntclkbufg_4 - CLMS_146_9/CLK + CLMA_230_328/CLK r - u_ov5640/cmos1_d_d0[5]/opit_0/CLK + ms72xx_ctl/ms7200_ctl/addr[0]/opit_0_inv_L5Q_perm/CLK clock pessimism - 0.000 - 15.072 + 0.283 + 103.830 clock uncertainty - -0.250 - 14.822 + -0.150 + 103.680 Setup time - -0.068 - 14.754 + -0.576 + 103.104 @@ -117473,27 +122498,27 @@ - 7.848 - 9 + 96.148 6 - u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK - udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[0]/opit_0_L5Q_perm/CE + 15 + ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK + ms72xx_ctl/ms7200_ctl/addr[4]/opit_0_inv_L5Q_perm/CE - clk_720p60Hz - clk_720p60Hz + clk_10m + clk_10m rise-rise -0.019 - 5.878 - 5.516 - 0.343 - 13.473 - 4.880 - 2.234 (45.8%) - 2.646 (54.2%) + 3.849 + 3.547 + 0.283 + 100.000 + 3.107 + 1.428 (46.0%) + 1.679 (54.0%) - Path #25: setup slack is 7.848(MET) + Path #38: setup slack is 96.148(MET) -
+
Location Delay Type @@ -117503,7 +122528,7 @@ Logical Resource - Clock clk_720p60Hz (rising edge) + Clock clk_10m (rising edge) 0.000 0.000 @@ -117559,249 +122584,169 @@ _N69 - PLL_158_55/CLK_OUT0 - td - 0.083 - 2.197 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 0.614 - 2.811 - - rd3_clk - - - USCM_84_154/CLK_USCM + PLL_158_55/CLK_OUT4 td - 0.000 - 2.811 + 0.084 + 2.198 r - USCMROUTE_0/CLKOUT + u_sys_pll/u_pll_e3/goppll/CLKOUT4 net (fanout=1) - 1.131 - 3.942 - - ntR3907 - - - PLL_158_303/CLK_OUT1 - td - 0.079 - 4.021 - r - U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 0.932 - 4.953 + 0.614 + 2.812 - nt_pix_clk + clk_10m - USCM_84_117/CLK_USCM + USCM_84_110/CLK_USCM td 0.000 - 4.953 - r - clkbufg_2/gopclkbufg/CLKOUT - - - - net (fanout=1635) - 0.925 - 5.878 - - ntclkbufg_2 - - - CLMS_186_117/CLK - - - - r - u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK - - - CLMS_186_117/Q2 - tco - 0.223 - 6.101 - f - u_sync_vg/pos_y[8]/opit_0_A2Q21/Q0 - - - - net (fanout=1) - 0.530 - 6.631 - - pos_y[7] - - - CLMA_186_116/COUT - td - 0.397 - 7.028 + 2.812 r - udp_osd_inst/N29.eq_2/gateop_A2/Cout + clkbufg_4/gopclkbufg/CLKOUT - net (fanout=1) - 0.000 - 7.028 - - udp_osd_inst/N29.co [6] - - - CLMA_186_120/Y1 - td - 0.383 - 7.411 - r - udp_osd_inst/N29.eq_4/gateop_A2/Y1 + net (fanout=235) + 1.037 + 3.849 + + ntclkbufg_4 + CLMS_218_329/CLK - net (fanout=5) - 0.247 - 7.658 - - udp_osd_inst/N29 + + + r + ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK - CLMA_190_120/Y3 - td - 0.222 - 7.880 + CLMS_218_329/Q2 + tco + 0.223 + 4.072 f - udp_osd_inst/N69_5/gateop_perm/Z + ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/Q - net (fanout=2) - 0.356 - 8.236 + net (fanout=3) + 0.174 + 4.246 - udp_osd_inst/char_osd_inst/pixels_shifter_inst/N64 + ms72xx_ctl/ms7200_ctl/dri_cnt [4] - CLMA_186_112/Y1 + CLMS_218_333/Y3 td - 0.151 - 8.387 + 0.358 + 4.604 f - udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/gateop_perm/Z + ms72xx_ctl/ms7200_ctl/N8_3/gateop_perm/Z - net (fanout=2) - 0.255 - 8.642 + net (fanout=1) + 0.157 + 4.761 - udp_osd_inst/char_osd_inst/row_pixels_ready + ms72xx_ctl/ms7200_ctl/_N96627 - CLMA_186_108/Y2 + CLMS_218_333/Y0 td 0.150 - 8.792 + 4.911 f - udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/gateop_perm/Z + ms72xx_ctl/ms7200_ctl/N1872_5/gateop_perm/Z net (fanout=6) - 0.399 - 9.191 + 0.269 + 5.180 - udp_osd_inst/char_osd_inst/char_next + ms72xx_ctl/ms7200_ctl/_N96632 - CLMA_182_88/Y3 + CLMS_222_329/Y0 td - 0.162 - 9.353 - r - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N79/gateop_perm/Z + 0.150 + 5.330 + f + ms72xx_ctl/ms7200_ctl/N2053_1/gateop_perm/Z - net (fanout=1) - 0.148 - 9.501 + net (fanout=15) + 0.363 + 5.693 - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N79 + ms72xx_ctl/ms7200_ctl/N261 - CLMA_182_88/Y2 + CLMS_214_321/Y0 td - 0.150 - 9.651 + 0.264 + 5.957 f - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N358_5/gateop_perm/Z + ms72xx_ctl/ms7200_ctl/N40_9/gateop_perm/Z - net (fanout=3) - 0.352 - 10.003 + net (fanout=4) + 0.353 + 6.310 - udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N96518 + ms72xx_ctl/ms7200_ctl/N2093 [4] - CLMA_186_80/Y0 + CLMA_222_324/Y1 td - 0.264 - 10.267 + 0.151 + 6.461 f - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786/gateop_perm/Z + ms72xx_ctl/ms7200_ctl/N1955/gateop_perm/Z - net (fanout=1) - 0.359 - 10.626 + net (fanout=12) + 0.363 + 6.824 - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786 + ms72xx_ctl/ms7200_ctl/N1955 - CLMA_182_73/CECO + CLMA_230_324/CECO td 0.132 - 10.758 + 6.956 f - udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[4]/opit_0_A2Q21/CEOUT + ms72xx_ctl/ms7200_ctl/data_in[5]/opit_0_inv_L5Q_perm/CEOUT net (fanout=4) 0.000 - 10.758 + 6.956 - ntR2038 + ntR1800 - CLMA_182_77/CECI + CLMA_230_328/CECI f - udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[0]/opit_0_L5Q_perm/CE + ms72xx_ctl/ms7200_ctl/addr[4]/opit_0_inv_L5Q_perm/CE
- +
Location Delay Type @@ -117811,10 +122756,10 @@ Logical Resource - Clock clk_720p60Hz (rising edge) + Clock clk_10m (rising edge) - 13.473 - 13.473 + 100.000 + 100.000 r @@ -117822,7 +122767,7 @@ P200.000 - 13.473 + 100.000rclk (port) @@ -117830,7 +122775,7 @@ net (fanout=1) 0.074 - 13.547 + 100.074 clk @@ -117838,7 +122783,7 @@ IOBS_LR_328_209/DIN td 1.285 - 14.832 + 101.359 r clk_ibuf/opit_0/O @@ -117846,7 +122791,7 @@ net (fanout=1) 0.000 - 14.832 + 101.359 clk_ibuf/ntD @@ -117854,7 +122799,7 @@ IOL_327_210/INCK td 0.038 - 14.870 + 101.397 r clk_ibuf/opit_1/INCK @@ -117862,87 +122807,55 @@ net (fanout=1) 0.463 - 15.333 + 101.860 _N69 - PLL_158_55/CLK_OUT0 - td - 0.078 - 15.411 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 0.603 - 16.014 - - rd3_clk - - - USCM_84_154/CLK_USCM + PLL_158_55/CLK_OUT4 td - 0.000 - 16.014 + 0.079 + 101.939 r - USCMROUTE_0/CLKOUT + u_sys_pll/u_pll_e3/goppll/CLKOUT4 net (fanout=1) - 1.091 - 17.105 - - ntR3907 - - - PLL_158_303/CLK_OUT1 - td - 0.074 - 17.179 - r - U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 0.915 - 18.094 + 0.603 + 102.542 - nt_pix_clk + clk_10m - USCM_84_117/CLK_USCM + USCM_84_110/CLK_USCM td 0.000 - 18.094 + 102.542 r - clkbufg_2/gopclkbufg/CLKOUT + clkbufg_4/gopclkbufg/CLKOUT - net (fanout=1635) - 0.895 - 18.989 + net (fanout=235) + 1.005 + 103.547 - ntclkbufg_2 + ntclkbufg_4 - CLMA_182_77/CLK + CLMA_230_328/CLK r - udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[0]/opit_0_L5Q_perm/CLK + ms72xx_ctl/ms7200_ctl/addr[4]/opit_0_inv_L5Q_perm/CLK clock pessimism - 0.343 - 19.332 + 0.283 + 103.830 @@ -117950,7 +122863,7 @@ clock uncertainty -0.150 - 19.182 + 103.680 @@ -117958,7 +122871,7 @@ Setup time -0.576 - 18.606 + 103.104 @@ -117967,27 +122880,27 @@ - 7.848 - 9 + 96.148 6 - u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK - udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[1]/opit_0_L5Q_perm/CE + 15 + ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK + ms72xx_ctl/ms7200_ctl/addr[5]/opit_0_inv_L5Q_perm/CE - clk_720p60Hz - clk_720p60Hz + clk_10m + clk_10m rise-rise -0.019 - 5.878 - 5.516 - 0.343 - 13.473 - 4.880 - 2.234 (45.8%) - 2.646 (54.2%) + 3.849 + 3.547 + 0.283 + 100.000 + 3.107 + 1.428 (46.0%) + 1.679 (54.0%) - Path #26: setup slack is 7.848(MET) + Path #39: setup slack is 96.148(MET) -
+
Location Delay Type @@ -117997,7 +122910,7 @@ Logical Resource - Clock clk_720p60Hz (rising edge) + Clock clk_10m (rising edge) 0.000 0.000 @@ -118053,249 +122966,169 @@ _N69 - PLL_158_55/CLK_OUT0 - td - 0.083 - 2.197 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 0.614 - 2.811 - - rd3_clk - - - USCM_84_154/CLK_USCM + PLL_158_55/CLK_OUT4 td - 0.000 - 2.811 + 0.084 + 2.198 r - USCMROUTE_0/CLKOUT + u_sys_pll/u_pll_e3/goppll/CLKOUT4 net (fanout=1) - 1.131 - 3.942 - - ntR3907 - - - PLL_158_303/CLK_OUT1 - td - 0.079 - 4.021 - r - U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 0.932 - 4.953 + 0.614 + 2.812 - nt_pix_clk + clk_10m - USCM_84_117/CLK_USCM + USCM_84_110/CLK_USCM td 0.000 - 4.953 + 2.812 r - clkbufg_2/gopclkbufg/CLKOUT + clkbufg_4/gopclkbufg/CLKOUT - net (fanout=1635) - 0.925 - 5.878 + net (fanout=235) + 1.037 + 3.849 - ntclkbufg_2 + ntclkbufg_4 - CLMS_186_117/CLK + CLMS_218_329/CLK r - u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK + ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK - CLMS_186_117/Q2 + CLMS_218_329/Q2 tco 0.223 - 6.101 - f - u_sync_vg/pos_y[8]/opit_0_A2Q21/Q0 - - - - net (fanout=1) - 0.530 - 6.631 - - pos_y[7] - - - CLMA_186_116/COUT - td - 0.397 - 7.028 - r - udp_osd_inst/N29.eq_2/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 7.028 - - udp_osd_inst/N29.co [6] - - - CLMA_186_120/Y1 - td - 0.383 - 7.411 - r - udp_osd_inst/N29.eq_4/gateop_A2/Y1 - - - - net (fanout=5) - 0.247 - 7.658 - - udp_osd_inst/N29 - - - CLMA_190_120/Y3 - td - 0.222 - 7.880 + 4.072 f - udp_osd_inst/N69_5/gateop_perm/Z + ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/Q - net (fanout=2) - 0.356 - 8.236 + net (fanout=3) + 0.174 + 4.246 - udp_osd_inst/char_osd_inst/pixels_shifter_inst/N64 + ms72xx_ctl/ms7200_ctl/dri_cnt [4] - CLMA_186_112/Y1 + CLMS_218_333/Y3 td - 0.151 - 8.387 + 0.358 + 4.604 f - udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/gateop_perm/Z + ms72xx_ctl/ms7200_ctl/N8_3/gateop_perm/Z - net (fanout=2) - 0.255 - 8.642 + net (fanout=1) + 0.157 + 4.761 - udp_osd_inst/char_osd_inst/row_pixels_ready + ms72xx_ctl/ms7200_ctl/_N96627 - CLMA_186_108/Y2 + CLMS_218_333/Y0 td 0.150 - 8.792 + 4.911 f - udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/gateop_perm/Z + ms72xx_ctl/ms7200_ctl/N1872_5/gateop_perm/Z net (fanout=6) - 0.399 - 9.191 + 0.269 + 5.180 - udp_osd_inst/char_osd_inst/char_next + ms72xx_ctl/ms7200_ctl/_N96632 - CLMA_182_88/Y3 + CLMS_222_329/Y0 td - 0.162 - 9.353 - r - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N79/gateop_perm/Z + 0.150 + 5.330 + f + ms72xx_ctl/ms7200_ctl/N2053_1/gateop_perm/Z - net (fanout=1) - 0.148 - 9.501 + net (fanout=15) + 0.363 + 5.693 - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N79 + ms72xx_ctl/ms7200_ctl/N261 - CLMA_182_88/Y2 + CLMS_214_321/Y0 td - 0.150 - 9.651 + 0.264 + 5.957 f - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N358_5/gateop_perm/Z + ms72xx_ctl/ms7200_ctl/N40_9/gateop_perm/Z - net (fanout=3) - 0.352 - 10.003 + net (fanout=4) + 0.353 + 6.310 - udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N96518 + ms72xx_ctl/ms7200_ctl/N2093 [4] - CLMA_186_80/Y0 + CLMA_222_324/Y1 td - 0.264 - 10.267 + 0.151 + 6.461 f - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786/gateop_perm/Z + ms72xx_ctl/ms7200_ctl/N1955/gateop_perm/Z - net (fanout=1) - 0.359 - 10.626 + net (fanout=12) + 0.363 + 6.824 - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786 + ms72xx_ctl/ms7200_ctl/N1955 - CLMA_182_73/CECO + CLMA_230_324/CECO td 0.132 - 10.758 + 6.956 f - udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[4]/opit_0_A2Q21/CEOUT + ms72xx_ctl/ms7200_ctl/data_in[5]/opit_0_inv_L5Q_perm/CEOUT net (fanout=4) 0.000 - 10.758 + 6.956 - ntR2038 + ntR1800 - CLMA_182_77/CECI + CLMA_230_328/CECI f - udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[1]/opit_0_L5Q_perm/CE + ms72xx_ctl/ms7200_ctl/addr[5]/opit_0_inv_L5Q_perm/CE
- +
Location Delay Type @@ -118305,10 +123138,10 @@ Logical Resource - Clock clk_720p60Hz (rising edge) + Clock clk_10m (rising edge) - 13.473 - 13.473 + 100.000 + 100.000 r @@ -118316,7 +123149,7 @@ P200.000 - 13.473 + 100.000rclk (port) @@ -118324,7 +123157,7 @@ net (fanout=1) 0.074 - 13.547 + 100.074 clk @@ -118332,7 +123165,7 @@ IOBS_LR_328_209/DIN td 1.285 - 14.832 + 101.359 r clk_ibuf/opit_0/O @@ -118340,7 +123173,7 @@ net (fanout=1) 0.000 - 14.832 + 101.359 clk_ibuf/ntD @@ -118348,7 +123181,7 @@ IOL_327_210/INCK td 0.038 - 14.870 + 101.397 r clk_ibuf/opit_1/INCK @@ -118356,87 +123189,55 @@ net (fanout=1) 0.463 - 15.333 + 101.860 _N69 - PLL_158_55/CLK_OUT0 - td - 0.078 - 15.411 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 0.603 - 16.014 - - rd3_clk - - - USCM_84_154/CLK_USCM + PLL_158_55/CLK_OUT4 td - 0.000 - 16.014 + 0.079 + 101.939 r - USCMROUTE_0/CLKOUT + u_sys_pll/u_pll_e3/goppll/CLKOUT4 net (fanout=1) - 1.091 - 17.105 - - ntR3907 - - - PLL_158_303/CLK_OUT1 - td - 0.074 - 17.179 - r - U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 0.915 - 18.094 + 0.603 + 102.542 - nt_pix_clk + clk_10m - USCM_84_117/CLK_USCM + USCM_84_110/CLK_USCM td 0.000 - 18.094 + 102.542 r - clkbufg_2/gopclkbufg/CLKOUT + clkbufg_4/gopclkbufg/CLKOUT - net (fanout=1635) - 0.895 - 18.989 + net (fanout=235) + 1.005 + 103.547 - ntclkbufg_2 + ntclkbufg_4 - CLMA_182_77/CLK + CLMA_230_328/CLK r - udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[1]/opit_0_L5Q_perm/CLK + ms72xx_ctl/ms7200_ctl/addr[5]/opit_0_inv_L5Q_perm/CLK clock pessimism - 0.343 - 19.332 + 0.283 + 103.830 @@ -118444,7 +123245,7 @@ clock uncertainty -0.150 - 19.182 + 103.680 @@ -118452,7 +123253,7 @@ Setup time -0.576 - 18.606 + 103.104 @@ -118461,27 +123262,27 @@ - 7.848 - 9 - 6 - u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK - udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[2]/opit_0_L5Q_perm/CE + 49996.111 + 3 + 1 + u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0] + u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I0 - clk_720p60Hz - clk_720p60Hz + clk_20k + clk_20k rise-rise -0.019 - 5.878 - 5.516 - 0.343 - 13.473 - 4.880 - 2.234 (45.8%) - 2.646 (54.2%) + 6.370 + 5.862 + 0.489 + 50000.000 + 3.669 + 2.534 (69.1%) + 1.135 (30.9%) - Path #27: setup slack is 7.848(MET) + Path #40: setup slack is 49996.111(MET) -
+
Location Delay Type @@ -118491,7 +123292,7 @@ Logical Resource - Clock clk_720p60Hz (rising edge) + Clock clk_20k (rising edge) 0.000 0.000 @@ -118547,249 +123348,153 @@ _N69 - PLL_158_55/CLK_OUT0 + PLL_158_55/CLK_OUT3 td - 0.083 - 2.197 + 0.088 + 2.202 r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 + u_sys_pll/u_pll_e3/goppll/CLKOUT3 - net (fanout=2) + net (fanout=1) 0.614 - 2.811 + 2.816 - rd3_clk + clk_25m - USCM_84_154/CLK_USCM + USCM_84_114/CLK_USCM td 0.000 - 2.811 + 2.816 r - USCMROUTE_0/CLKOUT + clkbufg_8/gopclkbufg/CLKOUT - net (fanout=1) - 1.131 - 3.942 + net (fanout=26) + 0.925 + 3.741 - ntR3907 + ntclkbufg_8 - PLL_158_303/CLK_OUT1 - td - 0.079 - 4.021 + CLMS_122_9/Q1 + tco + 0.224 + 3.965 r - U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q - net (fanout=2) - 0.932 - 4.953 + net (fanout=3) + 1.480 + 5.445 - nt_pix_clk + u_ov5640/coms1_reg_config/clk_20k_regdiv - USCM_84_117/CLK_USCM + USCM_84_120/CLK_USCM td 0.000 - 4.953 + 5.445 r - clkbufg_2/gopclkbufg/CLKOUT + u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - net (fanout=1635) + net (fanout=19) 0.925 - 5.878 - - ntclkbufg_2 - - - CLMS_186_117/CLK - - - - r - u_sync_vg/pos_y[8]/opit_0_A2Q21/CLK - - - CLMS_186_117/Q2 - tco - 0.223 - 6.101 - f - u_sync_vg/pos_y[8]/opit_0_A2Q21/Q0 - - - - net (fanout=1) - 0.530 - 6.631 - - pos_y[7] - - - CLMA_186_116/COUT - td - 0.397 - 7.028 - r - udp_osd_inst/N29.eq_2/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 7.028 - - udp_osd_inst/N29.co [6] - - - CLMA_186_120/Y1 - td - 0.383 - 7.411 - r - udp_osd_inst/N29.eq_4/gateop_A2/Y1 - - - - net (fanout=5) - 0.247 - 7.658 - - udp_osd_inst/N29 - - - CLMA_190_120/Y3 - td - 0.222 - 7.880 - f - udp_osd_inst/N69_5/gateop_perm/Z - - - - net (fanout=2) - 0.356 - 8.236 - - udp_osd_inst/char_osd_inst/pixels_shifter_inst/N64 - - - CLMA_186_112/Y1 - td - 0.151 - 8.387 - f - udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/gateop_perm/Z - - + 6.370 - net (fanout=2) - 0.255 - 8.642 - - udp_osd_inst/char_osd_inst/row_pixels_ready - - - CLMA_186_108/Y2 - td - 0.150 - 8.792 - f - udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/gateop_perm/Z + u_ov5640/coms1_reg_config/clock_20k + DRM_142_4/CLKB[0] - net (fanout=6) - 0.399 - 9.191 - - udp_osd_inst/char_osd_inst/char_next + + + r + u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0] - CLMA_182_88/Y3 - td - 0.162 - 9.353 - r - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N79/gateop_perm/Z + DRM_142_4/QB0[6] + tco + 1.780 + 8.150 + f + u_ov5640/coms1_reg_config/reg_data/iGopDrm/QB0[6] net (fanout=1) - 0.148 - 9.501 + 0.343 + 8.493 - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N79 + u_ov5640/coms1_reg_config/i2c_data [22] - CLMA_182_88/Y2 + CLMA_146_12/Y1 td - 0.150 - 9.651 + 0.359 + 8.852 f - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N358_5/gateop_perm/Z + u_ov5640/coms1_reg_config/u1/N267_29/gateop/F - net (fanout=3) - 0.352 - 10.003 + net (fanout=1) + 0.369 + 9.221 - udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N96518 + u_ov5640/coms1_reg_config/u1/_N25311 - CLMA_186_80/Y0 + CLMA_138_16/Y0 td - 0.264 - 10.267 - f - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786/gateop_perm/Z + 0.162 + 9.383 + r + u_ov5640/coms1_reg_config/u1/N267_35/gateop_perm/Z net (fanout=1) - 0.359 - 10.626 + 0.151 + 9.534 - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N786 + u_ov5640/coms1_reg_config/u1/_N25317 - CLMA_182_73/CECO + CLMA_138_16/Y2 td - 0.132 - 10.758 + 0.233 + 9.767 f - udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[4]/opit_0_A2Q21/CEOUT + u_ov5640/coms1_reg_config/u1/N267_36/gateop/F - net (fanout=4) - 0.000 - 10.758 + net (fanout=1) + 0.272 + 10.039 - ntR2038 + u_ov5640/coms1_reg_config/u1/_N25318 - CLMA_182_77/CECI + CLMA_138_9/AD f - udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[2]/opit_0_L5Q_perm/CE + u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I0
- +
Location Delay Type @@ -118799,10 +123504,10 @@ Logical Resource - Clock clk_720p60Hz (rising edge) + Clock clk_20k (rising edge) - 13.473 - 13.473 + 50000.000 + 50000.000 r @@ -118810,7 +123515,7 @@ P200.000 - 13.473 + 50000.000rclk (port) @@ -118818,7 +123523,7 @@ net (fanout=1) 0.074 - 13.547 + 50000.074 clk @@ -118826,7 +123531,7 @@ IOBS_LR_328_209/DIN td 1.285 - 14.832 + 50001.359 r clk_ibuf/opit_0/O @@ -118834,7 +123539,7 @@ net (fanout=1) 0.000 - 14.832 + 50001.359 clk_ibuf/ntD @@ -118842,7 +123547,7 @@ IOL_327_210/INCK td 0.038 - 14.870 + 50001.397 r clk_ibuf/opit_1/INCK @@ -118850,103 +123555,103 @@ net (fanout=1) 0.463 - 15.333 + 50001.860 _N69 - PLL_158_55/CLK_OUT0 + PLL_158_55/CLK_OUT3 td - 0.078 - 15.411 + 0.083 + 50001.943 r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 + u_sys_pll/u_pll_e3/goppll/CLKOUT3 - net (fanout=2) + net (fanout=1) 0.603 - 16.014 + 50002.546 - rd3_clk + clk_25m - USCM_84_154/CLK_USCM + USCM_84_114/CLK_USCM td 0.000 - 16.014 + 50002.546 r - USCMROUTE_0/CLKOUT + clkbufg_8/gopclkbufg/CLKOUT - net (fanout=1) - 1.091 - 17.105 + net (fanout=26) + 0.895 + 50003.441 - ntR3907 + ntclkbufg_8 - PLL_158_303/CLK_OUT1 - td - 0.074 - 17.179 + CLMS_122_9/Q1 + tco + 0.184 + 50003.625 r - U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q - net (fanout=2) - 0.915 - 18.094 + net (fanout=3) + 1.342 + 50004.967 - nt_pix_clk + u_ov5640/coms1_reg_config/clk_20k_regdiv - USCM_84_117/CLK_USCM + USCM_84_120/CLK_USCM td 0.000 - 18.094 + 50004.967 r - clkbufg_2/gopclkbufg/CLKOUT + u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - net (fanout=1635) + net (fanout=19) 0.895 - 18.989 + 50005.862 - ntclkbufg_2 + u_ov5640/coms1_reg_config/clock_20k - CLMA_182_77/CLK + CLMA_138_9/CLK r - udp_osd_inst/char_osd_inst/char_buf_reader_inst/cnt[2]/opit_0_L5Q_perm/CLK + u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/CLK clock pessimism - 0.343 - 19.332 + 0.489 + 50006.351 clock uncertainty - -0.150 - 19.182 + -0.050 + 50006.301 Setup time - -0.576 - 18.606 + -0.151 + 50006.150 @@ -118955,27 +123660,27 @@ - 13.413 - 5 - 6 - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/L4 + 49996.291 + 3 + 1 + u_ov5640/coms2_reg_config/reg_data/iGopDrm/CLKB[0] + u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_L5Q_perm/L4 - clk_50m - clk_50m + clk_20k + clk_20k rise-rise -0.066 - 3.783 - 3.436 - 0.281 - 20.000 - 6.293 - 3.469 (55.1%) - 2.824 (44.9%) + 6.335 + 5.796 + 0.473 + 50000.000 + 3.500 + 2.501 (71.5%) + 0.999 (28.5%) - Path #28: setup slack is 13.413(MET) + Path #41: setup slack is 49996.291(MET) -
+
Location Delay Type @@ -118985,7 +123690,7 @@ Logical Resource - Clock clk_50m (rising edge) + Clock clk_20k (rising edge) 0.000 0.000 @@ -119041,185 +123746,153 @@ _N69 - PLL_158_55/CLK_OUT0 + PLL_158_55/CLK_OUT3 td - 0.083 - 2.197 + 0.088 + 2.202 r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 + u_sys_pll/u_pll_e3/goppll/CLKOUT3 - net (fanout=2) + net (fanout=1) 0.614 - 2.811 + 2.816 - rd3_clk + clk_25m - USCM_84_108/CLK_USCM + USCM_84_114/CLK_USCM td 0.000 - 2.811 + 2.816 r - clkbufg_1/gopclkbufg/CLKOUT - - - - net (fanout=2517) - 0.972 - 3.783 - - ntclkbufg_1 + clkbufg_8/gopclkbufg/CLKOUT - DRM_82_4/CLKB[0] - + net (fanout=26) + 0.925 + 3.741 - r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB + ntclkbufg_8 - DRM_82_4/QB0[0] + CLMA_122_12/Q1 tco - 1.780 - 5.563 - f - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/DOB[0] - - - - net (fanout=6) - 0.946 - 6.509 - - u_rotate_image/dout [0] - - - CLMS_74_73/Y1 - td - 0.151 - 6.660 - f - u_rotate_image/addr_fifo_valid/opit_0_L5Q_perm/Z + 0.224 + 3.965 + r + u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q net (fanout=3) - 0.793 - 7.453 - - u_rotate_image/addr_fifo_rd_en + 1.398 + 5.363 + + u_ov5640/coms2_reg_config/clk_20k_regdiv - + USCM_84_121/CLK_USCM td - 0.222 - 7.675 - f - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/Cout - - - - net (fanout=1) 0.000 - 7.675 - - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16637 + 5.363 + r + u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - CLMS_78_9/Y3 - td - 0.387 - 8.062 - r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/Y1 + + net (fanout=19) + 0.972 + 6.335 + + u_ov5640/coms2_reg_config/clock_20k + DRM_82_4/CLKB[0] - net (fanout=1) - 0.236 - 8.298 - - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11 [3] + + + r + u_ov5640/coms2_reg_config/reg_data/iGopDrm/CLKB[0] - CLMS_74_13/Y3 - td - 0.151 - 8.449 + DRM_82_4/QB0[5] + tco + 1.780 + 8.115 f - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[3]/gateop_perm/Z + u_ov5640/coms2_reg_config/reg_data/iGopDrm/QB0[5] - net (fanout=3) - 0.496 - 8.945 + net (fanout=1) + 0.306 + 8.421 - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/rrptr [3] + u_ov5640/coms2_reg_config/i2c_data [21] - + CLMS_78_9/Y1 td - 0.368 - 9.313 + 0.359 + 8.780 f - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_0/gateop_A2/Cout + u_ov5640/coms2_reg_config/u1/N267_29/gateop/F net (fanout=1) - 0.000 - 9.313 + 0.391 + 9.171 - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.co [2] + u_ov5640/coms2_reg_config/u1/_N25853 - CLMA_90_20/COUT + CLMA_90_12/Y2 td - 0.044 - 9.357 + 0.162 + 9.333 r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_2/gateop_A2/Cout + u_ov5640/coms2_reg_config/u1/N267_35/gateop_perm/Z net (fanout=1) - 0.000 - 9.357 + 0.151 + 9.484 - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.co [6] + u_ov5640/coms2_reg_config/u1/_N25859 - CLMA_90_24/Y1 + CLMA_90_12/Y6AB td - 0.366 - 9.723 - f - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_4/gateop_A2/Y1 + 0.200 + 9.684 + r + u_ov5640/coms2_reg_config/u1/N267_37_muxf6/F net (fanout=1) - 0.353 - 10.076 + 0.151 + 9.835 - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21 + u_ov5640/coms2_reg_config/u1/N267 - CLMA_94_16/C4 + CLMA_90_13/A4 - f - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/L4 + r + u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_L5Q_perm/L4
- +
Location Delay Type @@ -119229,10 +123902,10 @@ Logical Resource - Clock clk_50m (rising edge) + Clock clk_20k (rising edge) - 20.000 - 20.000 + 50000.000 + 50000.000 r @@ -119240,7 +123913,7 @@ P200.000 - 20.000 + 50000.000rclk (port) @@ -119248,7 +123921,7 @@ net (fanout=1) 0.074 - 20.074 + 50000.074 clk @@ -119256,7 +123929,7 @@ IOBS_LR_328_209/DIN td 1.285 - 21.359 + 50001.359 r clk_ibuf/opit_0/O @@ -119264,7 +123937,7 @@ net (fanout=1) 0.000 - 21.359 + 50001.359 clk_ibuf/ntD @@ -119272,7 +123945,7 @@ IOL_327_210/INCK td 0.038 - 21.397 + 50001.397 r clk_ibuf/opit_1/INCK @@ -119280,71 +123953,103 @@ net (fanout=1) 0.463 - 21.860 + 50001.860 _N69 - PLL_158_55/CLK_OUT0 + PLL_158_55/CLK_OUT3 td - 0.078 - 21.938 + 0.083 + 50001.943 r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 + u_sys_pll/u_pll_e3/goppll/CLKOUT3 - net (fanout=2) + net (fanout=1) 0.603 - 22.541 + 50002.546 - rd3_clk + clk_25m - USCM_84_108/CLK_USCM + USCM_84_114/CLK_USCM td 0.000 - 22.541 + 50002.546 r - clkbufg_1/gopclkbufg/CLKOUT + clkbufg_8/gopclkbufg/CLKOUT - net (fanout=2517) + net (fanout=26) 0.895 - 23.436 + 50003.441 - ntclkbufg_1 + ntclkbufg_8 + + + CLMA_122_12/Q1 + tco + 0.184 + 50003.625 + r + u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q + + + + net (fanout=3) + 1.276 + 50004.901 + + u_ov5640/coms2_reg_config/clk_20k_regdiv + + + USCM_84_121/CLK_USCM + td + 0.000 + 50004.901 + r + u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - CLMA_94_16/CLK + + net (fanout=19) + 0.895 + 50005.796 + + u_ov5640/coms2_reg_config/clock_20k + + + CLMA_90_13/CLK r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK + u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_L5Q_perm/CLK clock pessimism - 0.281 - 23.717 + 0.473 + 50006.269 clock uncertainty - -0.150 - 23.567 + -0.050 + 50006.219 Setup time - -0.078 - 23.489 + -0.093 + 50006.126 @@ -119353,27 +124058,27 @@ - 13.952 - 5 - 6 - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/L4 + 49996.705 + 1 + 1 + u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0] + u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I3 - clk_50m - clk_50m + clk_20k + clk_20k rise-rise - -0.066 - 3.783 - 3.436 - 0.281 - 20.000 - 5.738 - 3.640 (63.4%) - 2.098 (36.6%) + -0.019 + 6.370 + 5.862 + 0.489 + 50000.000 + 3.072 + 2.284 (74.3%) + 0.788 (25.7%) - Path #29: setup slack is 13.952(MET) + Path #42: setup slack is 49996.705(MET) -
+
Location Delay Type @@ -119383,7 +124088,7 @@ Logical Resource - Clock clk_50m (rising edge) + Clock clk_20k (rising edge) 0.000 0.000 @@ -119439,185 +124144,121 @@ _N69 - PLL_158_55/CLK_OUT0 + PLL_158_55/CLK_OUT3 td - 0.083 - 2.197 + 0.088 + 2.202 r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 + u_sys_pll/u_pll_e3/goppll/CLKOUT3 - net (fanout=2) + net (fanout=1) 0.614 - 2.811 + 2.816 - rd3_clk + clk_25m - USCM_84_108/CLK_USCM + USCM_84_114/CLK_USCM td 0.000 - 2.811 + 2.816 r - clkbufg_1/gopclkbufg/CLKOUT - - - - net (fanout=2517) - 0.972 - 3.783 - - ntclkbufg_1 + clkbufg_8/gopclkbufg/CLKOUT - DRM_82_4/CLKB[0] - + net (fanout=26) + 0.925 + 3.741 - r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB + ntclkbufg_8 - DRM_82_4/QB0[0] + CLMS_122_9/Q1 tco - 1.780 - 5.563 - f - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/DOB[0] - - - - net (fanout=6) - 0.772 - 6.335 - - u_rotate_image/dout [0] - - - CLMS_74_73/Y3 - td - 0.358 - 6.693 - f - u_rotate_image/fifo_data_valid/opit_0_L5Q_perm/Z + 0.224 + 3.965 + r + u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q net (fanout=3) - 0.535 - 7.228 - - u_rotate_image/N170 - - - - td - 0.222 - 7.450 - f - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/Cout - - + 1.480 + 5.445 - net (fanout=1) - 0.000 - 7.450 - - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16662 + u_ov5640/coms1_reg_config/clk_20k_regdiv - CLMA_58_92/Y3 + USCM_84_120/CLK_USCM td - 0.387 - 7.837 + 0.000 + 5.445 r - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/Y1 + u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - net (fanout=1) - 0.162 - 7.999 - - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11 [3] - - - CLMA_58_89/Y3 - td - 0.358 - 8.357 - f - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[3]/gateop_perm/Z - - + net (fanout=19) + 0.925 + 6.370 - net (fanout=1) - 0.478 - 8.835 - - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/rrptr [3] - - - - td - 0.368 - 9.203 - f - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N24.eq_0/gateop_A2/Cout + u_ov5640/coms1_reg_config/clock_20k + DRM_142_4/CLKB[0] - net (fanout=1) - 0.000 - 9.203 - - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N24.co [2] + + + r + u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0] - CLMS_50_93/COUT - td - 0.044 - 9.247 - r - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N24.eq_2/gateop_A2/Cout + DRM_142_4/QA0[9] + tco + 1.815 + 8.185 + f + u_ov5640/coms1_reg_config/reg_data/iGopDrm/QA0[9] net (fanout=1) - 0.000 - 9.247 + 0.410 + 8.595 - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N24.co [6] + u_ov5640/coms1_reg_config/i2c_data [8] - CLMS_50_97/Y0 + CLMA_146_8/Y1 td - 0.123 - 9.370 - r - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/Y0 + 0.469 + 9.064 + f + u_ov5640/coms1_reg_config/u1/N267_18_muxf7/F net (fanout=1) - 0.151 - 9.521 + 0.378 + 9.442 - _N70 + u_ov5640/coms1_reg_config/u1/_N25300 - CLMS_50_97/C4 + CLMA_138_9/A0 - r - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/L4 + f + u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I3
- +
Location Delay Type @@ -119627,10 +124268,10 @@ Logical Resource - Clock clk_50m (rising edge) + Clock clk_20k (rising edge) - 20.000 - 20.000 + 50000.000 + 50000.000 r @@ -119638,7 +124279,7 @@ P200.000 - 20.000 + 50000.000rclk (port) @@ -119646,7 +124287,7 @@ net (fanout=1) 0.074 - 20.074 + 50000.074 clk @@ -119654,7 +124295,7 @@ IOBS_LR_328_209/DIN td 1.285 - 21.359 + 50001.359 r clk_ibuf/opit_0/O @@ -119662,7 +124303,7 @@ net (fanout=1) 0.000 - 21.359 + 50001.359 clk_ibuf/ntD @@ -119670,7 +124311,7 @@ IOL_327_210/INCK td 0.038 - 21.397 + 50001.397 r clk_ibuf/opit_1/INCK @@ -119678,71 +124319,103 @@ net (fanout=1) 0.463 - 21.860 + 50001.860 _N69 - PLL_158_55/CLK_OUT0 + PLL_158_55/CLK_OUT3 td - 0.078 - 21.938 + 0.083 + 50001.943 r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 + u_sys_pll/u_pll_e3/goppll/CLKOUT3 - net (fanout=2) + net (fanout=1) 0.603 - 22.541 + 50002.546 - rd3_clk + clk_25m - USCM_84_108/CLK_USCM + USCM_84_114/CLK_USCM td 0.000 - 22.541 + 50002.546 r - clkbufg_1/gopclkbufg/CLKOUT + clkbufg_8/gopclkbufg/CLKOUT - net (fanout=2517) + net (fanout=26) 0.895 - 23.436 + 50003.441 - ntclkbufg_1 + ntclkbufg_8 + + + CLMS_122_9/Q1 + tco + 0.184 + 50003.625 + r + u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q + + + + net (fanout=3) + 1.342 + 50004.967 + + u_ov5640/coms1_reg_config/clk_20k_regdiv + + + USCM_84_120/CLK_USCM + td + 0.000 + 50004.967 + r + u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + + + + net (fanout=19) + 0.895 + 50005.862 + + u_ov5640/coms1_reg_config/clock_20k - CLMS_50_97/CLK + CLMA_138_9/CLK r - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK + u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/CLK clock pessimism - 0.281 - 23.717 + 0.489 + 50006.351 clock uncertainty - -0.150 - 23.567 + -0.050 + 50006.301 Setup time - -0.094 - 23.473 + -0.154 + 50006.147 @@ -119750,28 +124423,49 @@ +
+ + + Slack + Logic Levels + High Fanout + Start Point + End Point + Exception + Launch Clock + Capture Clock + Clock Edges + Clock Skew + Launch Clock Delay + Capture Clock Delay + Clock Pessimism Removal + Requirement + Data delay + Logic delay + Route delay + - 14.036 - 5 - 6 - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/Cin + 0.075 + 0 + 3 + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[30]/opit_0/CLK + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][6]/opit_0/D - clk_50m - clk_50m + eth_rxc + eth_rxc rise-rise - -0.066 - 3.783 - 3.436 - 0.281 - 20.000 - 5.472 - 3.176 (58.0%) - 2.296 (42.0%) + 0.019 + 5.760 + 6.846 + -1.067 + 0.000 + 0.328 + 0.182 (55.5%) + 0.146 (44.5%) - Path #30: setup slack is 14.036(MET) + Path #1: hold slack is 0.075(MET) -
+
Location Delay Type @@ -119781,7 +124475,7 @@ Logical Resource - Clock clk_50m (rising edge) + Clock eth_rxc (rising edge) 0.000 0.000 @@ -119789,233 +124483,275 @@ - P20 + F14 0.000 0.000 r - clk (port) + eth_rxc (port) net (fanout=1) - 0.074 - 0.074 + 0.057 + 0.057 - clk + eth_rxc - IOBS_LR_328_209/DIN + IOBD_240_376/DIN td - 1.504 - 1.578 + 0.735 + 0.792 r - clk_ibuf/opit_0/O + eth_rxc_ibuf/opit_0/O net (fanout=1) 0.000 - 1.578 + 0.792 - clk_ibuf/ntD + eth_rxc_ibuf/ntD - IOL_327_210/INCK + IOL_243_374/INCK td - 0.058 - 1.636 + 0.038 + 0.830 r - clk_ibuf/opit_1/INCK + eth_rxc_ibuf/opit_1/INCK net (fanout=1) - 0.478 - 2.114 + 0.363 + 1.193 - _N69 + _N66 - PLL_158_55/CLK_OUT0 + IOCKDLY_237_367/CLK_OUT td - 0.083 - 2.197 + 2.069 + 3.262 r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT - net (fanout=2) - 0.614 - 2.811 + net (fanout=1) + 1.493 + 4.755 - rd3_clk + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf - USCM_84_108/CLK_USCM + USCM_84_109/CLK_USCM td 0.000 - 2.811 + 4.755 r - clkbufg_1/gopclkbufg/CLKOUT + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - net (fanout=2517) - 0.972 - 3.783 + net (fanout=1862) + 1.005 + 5.760 - ntclkbufg_1 + gmii_clk - DRM_82_4/CLKB[0] + CLMA_194_288/CLK r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKB + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[30]/opit_0/CLK - DRM_82_4/QB0[0] + CLMA_194_288/Q0 tco - 1.780 - 5.563 - f - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/DOB[0] + 0.182 + 5.942 + r + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[30]/opit_0/Q - net (fanout=6) - 0.946 - 6.509 + net (fanout=3) + 0.146 + 6.088 - u_rotate_image/dout [0] + udp_osd_inst/eth_udp_inst/des_ip [30] - CLMS_74_73/Y1 - td - 0.151 - 6.660 - f - u_rotate_image/addr_fifo_valid/opit_0_L5Q_perm/Z + CLMA_198_288/AD + + + + r + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][6]/opit_0/D +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + Clock eth_rxc (rising edge) + + 0.000 + 0.000 + r - net (fanout=3) - 0.793 - 7.453 - - u_rotate_image/addr_fifo_rd_en - - td - 0.222 - 7.675 - f - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/opit_0_inv_A2Q21/Cout + F14 + + 0.000 + 0.000 + r + eth_rxc (port) net (fanout=1) - 0.000 - 7.675 - - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16637 + 0.057 + 0.057 + + eth_rxc - CLMS_78_9/COUT + IOBD_240_376/DIN td - 0.044 - 7.719 + 0.861 + 0.918 r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/Cout + eth_rxc_ibuf/opit_0/O net (fanout=1) 0.000 - 7.719 - - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16639 + 0.918 + + eth_rxc_ibuf/ntD - + IOL_243_374/INCK td - 0.044 - 7.763 + 0.058 + 0.976 r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/Cout + eth_rxc_ibuf/opit_1/INCK net (fanout=1) - 0.000 - 7.763 - - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16641 + 0.370 + 1.346 + + _N66 - CLMS_78_13/Y3 + IOCKDLY_237_367/CLK_OUT td - 0.387 - 8.150 + 2.942 + 4.288 r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/Y1 + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT net (fanout=1) - 0.234 - 8.384 - - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11 [7] + 1.521 + 5.809 + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf - CLMS_74_13/Y1 + USCM_84_109/CLK_USCM td - 0.151 - 8.535 - f - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[7]/gateop_perm/Z + 0.000 + 5.809 + r + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - net (fanout=3) - 0.323 - 8.858 - - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/rrptr [7] + net (fanout=1862) + 1.037 + 6.846 + + gmii_clk - CLMA_94_12/COUT - td - 0.397 - 9.255 + CLMA_198_288/CLK + + + r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N24.eq_2/gateop_A2/Cout + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[24][6]/opit_0/CLK + clock pessimism + + -1.067 + 5.779 + - net (fanout=1) - 0.000 - 9.255 - - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N24.co [6] - CLMA_94_16/CIN + clock uncertainty + 0.200 + 5.979 + + + + + Hold time + + 0.034 + 6.013 - r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/Cin
+
+
+ + 0.103 + 0 + 3 + u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[2]/opit_0_L5Q_perm/CLK + u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[3]/opit_0_L5Q_perm/L0 + + hdmi_in_clk + hdmi_in_clk + rise-rise + 0.001 + 3.724 + 4.020 + -0.295 + 0.000 + 0.239 + 0.180 (75.3%) + 0.059 (24.7%) + + Path #2: hold slack is 0.103(MET) - +
Location Delay Type @@ -120025,151 +124761,113 @@ Logical Resource - Clock clk_50m (rising edge) + Clock hdmi_in_clk (rising edge) - 20.000 - 20.000 + 0.000 + 0.000 r - P20 + AA12 0.000 - 20.000 + 0.000 r - clk (port) + hdmi_in_clk (port) net (fanout=1) - 0.074 - 20.074 + 0.078 + 0.078 - clk + hdmi_in_clk - IOBS_LR_328_209/DIN + IOBD_161_0/DIN td 1.285 - 21.359 + 1.363 r - clk_ibuf/opit_0/O + hdmi_in_clk_ibuf/opit_0/O net (fanout=1) 0.000 - 21.359 + 1.363 - clk_ibuf/ntD + hdmi_in_clk_ibuf/ntD - IOL_327_210/INCK + IOL_163_6/INCK td 0.038 - 21.397 + 1.401 r - clk_ibuf/opit_1/INCK + hdmi_in_clk_ibuf/opit_1/INCK net (fanout=1) - 0.463 - 21.860 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.078 - 21.938 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 0.603 - 22.541 + 1.428 + 2.829 - rd3_clk + _N37 - USCM_84_108/CLK_USCM + USCM_84_111/CLK_USCM td 0.000 - 22.541 + 2.829 r - clkbufg_1/gopclkbufg/CLKOUT + clkbufg_5/gopclkbufg/CLKOUT - net (fanout=2517) + net (fanout=167) 0.895 - 23.436 + 3.724 - ntclkbufg_1 + ntclkbufg_5 - CLMA_94_16/CLK + CLMA_122_92/CLK r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/opit_0_A2Q1/CLK + u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[2]/opit_0_L5Q_perm/CLK - clock pessimism - - 0.281 - 23.717 - - + CLMA_122_92/Q2 + tco + 0.180 + 3.904 + f + u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[2]/opit_0_L5Q_perm/Q - clock uncertainty - - -0.150 - 23.567 - + net (fanout=3) + 0.059 + 3.963 + + u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt [2] - Setup time + CLMA_122_92/D0 - -0.276 - 23.291 + f + u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[3]/opit_0_L5Q_perm/L0
-
-
- - 36.725 - 4 - 13 - u_ov5640/coms1_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK - u_ov5640/coms1_reg_config/clock_20k_cnt[8]/opit_0_inv/D - - clk_25m - clk_25m - rise-rise - -0.001 - 3.741 - 3.441 - 0.299 - 40.000 - 3.056 - 1.552 (50.8%) - 1.504 (49.2%) - - Path #31: setup slack is 36.725(MET) - +
Location Delay Type @@ -120179,7 +124877,7 @@ Logical Resource - Clock clk_25m (rising edge) + Clock hdmi_in_clk (rising edge) 0.000 0.000 @@ -120187,201 +124885,243 @@ - P20 + AA12 0.000 0.000 r - clk (port) + hdmi_in_clk (port) net (fanout=1) - 0.074 - 0.074 + 0.078 + 0.078 - clk + hdmi_in_clk - IOBS_LR_328_209/DIN + IOBD_161_0/DIN td 1.504 - 1.578 + 1.582 r - clk_ibuf/opit_0/O + hdmi_in_clk_ibuf/opit_0/O net (fanout=1) 0.000 - 1.578 + 1.582 - clk_ibuf/ntD + hdmi_in_clk_ibuf/ntD - IOL_327_210/INCK + IOL_163_6/INCK td 0.058 - 1.636 + 1.640 r - clk_ibuf/opit_1/INCK + hdmi_in_clk_ibuf/opit_1/INCK net (fanout=1) - 0.478 - 2.114 + 1.455 + 3.095 - _N69 + _N37 - PLL_158_55/CLK_OUT3 + USCM_84_111/CLK_USCM td - 0.088 - 2.202 + 0.000 + 3.095 r - u_sys_pll/u_pll_e3/goppll/CLKOUT3 + clkbufg_5/gopclkbufg/CLKOUT - net (fanout=1) - 0.614 - 2.816 + net (fanout=167) + 0.925 + 4.020 - clk_25m + ntclkbufg_5 - USCM_84_114/CLK_USCM - td - 0.000 - 2.816 + CLMA_122_92/CLK + + + r - clkbufg_7/gopclkbufg/CLKOUT + u_ddr_addr_ctr/u_wr1_addr_ctr/delay_cnt[3]/opit_0_L5Q_perm/CLK + clock pessimism + + -0.295 + 3.725 - net (fanout=26) - 0.925 - 3.741 - ntclkbufg_7 - CLMA_182_17/CLK + clock uncertainty + 0.200 + 3.925 - r - u_ov5640/coms1_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK - CLMA_182_17/Q0 - tco - 0.221 - 3.962 - f - u_ov5640/coms1_reg_config/clock_20k_cnt[0]/opit_0_inv/Q + Hold time + + -0.065 + 3.860 + + +
+
+
+
+ + 0.104 + 0 + 5 + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/L0 + + cmos1_pclk + cmos1_pclk + rise-rise + 0.015 + 3.172 + 3.375 + -0.188 + 0.000 + 0.242 + 0.180 (74.4%) + 0.062 (25.6%) + + Path #3: hold slack is 0.104(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + Clock cmos1_pclk (rising edge) + + 0.000 + 0.000 + r - net (fanout=4) - 0.365 - 4.327 - - u_ov5640/coms1_reg_config/clock_20k_cnt [0] - CLMA_182_13/Y2 - td - 0.381 - 4.708 - f - u_ov5640/coms1_reg_config/N8_mux4_5/gateop_perm/Z + T12 + + 0.000 + 0.000 + r + cmos1_pclk (port) net (fanout=1) - 0.256 - 4.964 - - u_ov5640/coms1_reg_config/_N9664 + 0.076 + 0.076 + + cmos1_pclk - CLMA_186_16/Y0 + IOBD_169_0/DIN td - 0.150 - 5.114 - f - u_ov5640/coms1_reg_config/N8_mux10/gateop_perm/Z + 0.735 + 0.811 + r + cmos1_pclk_ibuf/opit_0/O - net (fanout=13) - 0.508 - 5.622 - - u_ov5640/coms1_reg_config/N8 + net (fanout=1) + 0.000 + 0.811 + + cmos1_pclk_ibuf/ntD - CLMA_182_12/COUT + IOL_171_6/INCK td - 0.391 - 6.013 + 0.038 + 0.849 r - u_ov5640/coms1_reg_config/N11_2_3/gateop_A2/Cout + cmos1_pclk_ibuf/opit_1/INCK net (fanout=1) - 0.000 - 6.013 - - u_ov5640/coms1_reg_config/_N16248 + 1.428 + 2.277 + + _N64 - + USCM_84_112/CLK_USCM td - 0.044 - 6.057 + 0.000 + 2.277 r - u_ov5640/coms1_reg_config/N11_2_5/gateop_A2/Cout + clkbufg_6/gopclkbufg/CLKOUT - net (fanout=1) - 0.000 - 6.057 - - u_ov5640/coms1_reg_config/_N16250 + net (fanout=118) + 0.895 + 3.172 + + ntclkbufg_6 - CLMA_182_16/Y3 - td - 0.365 - 6.422 + CLMA_138_56/CLK + + + + r + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/CLK + + + CLMA_138_56/Q1 + tco + 0.180 + 3.352 f - u_ov5640/coms1_reg_config/N11_2_7/gateop_A2/Y1 + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/opit_0_inv_A2Q21/Q1 - net (fanout=1) - 0.375 - 6.797 + net (fanout=5) + 0.062 + 3.414 - u_ov5640/coms1_reg_config/N1114 [8] + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/wr_addr [5] - CLMA_182_17/M2 + CLMA_138_57/C0 f - u_ov5640/coms1_reg_config/clock_20k_cnt[8]/opit_0_inv/D + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/L0
- +
Location Delay Type @@ -120391,122 +125131,106 @@ Logical Resource - Clock clk_25m (rising edge) + Clock cmos1_pclk (rising edge) - 40.000 - 40.000 + 0.000 + 0.000 r - P20 + T12 0.000 - 40.000 + 0.000 r - clk (port) + cmos1_pclk (port) net (fanout=1) - 0.074 - 40.074 + 0.076 + 0.076 - clk + cmos1_pclk - IOBS_LR_328_209/DIN + IOBD_169_0/DIN td - 1.285 - 41.359 + 0.861 + 0.937 r - clk_ibuf/opit_0/O + cmos1_pclk_ibuf/opit_0/O net (fanout=1) 0.000 - 41.359 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.038 - 41.397 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.463 - 41.860 + 0.937 - _N69 + cmos1_pclk_ibuf/ntD - PLL_158_55/CLK_OUT3 + IOL_171_6/INCK td - 0.083 - 41.943 + 0.058 + 0.995 r - u_sys_pll/u_pll_e3/goppll/CLKOUT3 + cmos1_pclk_ibuf/opit_1/INCK net (fanout=1) - 0.603 - 42.546 + 1.455 + 2.450 - clk_25m + _N64 - USCM_84_114/CLK_USCM + USCM_84_112/CLK_USCM td 0.000 - 42.546 + 2.450 r - clkbufg_7/gopclkbufg/CLKOUT + clkbufg_6/gopclkbufg/CLKOUT - net (fanout=26) - 0.895 - 43.441 + net (fanout=118) + 0.925 + 3.375 - ntclkbufg_7 + ntclkbufg_6 - CLMA_182_17/CLK + CLMA_138_57/CLK r - u_ov5640/coms1_reg_config/clock_20k_cnt[8]/opit_0_inv/CLK + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/opit_0_L5Q_perm/CLK clock pessimism - 0.299 - 43.740 + -0.188 + 3.187 clock uncertainty - -0.150 - 43.590 + 0.200 + 3.387 - Setup time + Hold time - -0.068 - 43.522 + -0.077 + 3.310 @@ -120515,27 +125239,27 @@ - 36.768 + 0.104 + 0 5 - 13 - u_ov5640/coms1_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK - u_ov5640/coms1_reg_config/clock_20k_cnt[10]/opit_0_inv/D + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/L0 - clk_25m - clk_25m + cmos1_pclk + cmos1_pclk rise-rise - -0.015 - 3.741 - 3.441 - 0.285 - 40.000 - 2.999 - 1.597 (53.3%) - 1.402 (46.7%) + 0.015 + 3.172 + 3.375 + -0.188 + 0.000 + 0.241 + 0.179 (74.3%) + 0.062 (25.7%) - Path #32: setup slack is 36.768(MET) + Path #4: hold slack is 0.104(MET) -
+
Location Delay Type @@ -120545,7 +125269,7 @@ Logical Resource - Clock clk_25m (rising edge) + Clock cmos1_pclk (rising edge) 0.000 0.000 @@ -120553,217 +125277,105 @@ - P20 + T12 0.000 0.000 r - clk (port) + cmos1_pclk (port) net (fanout=1) - 0.074 - 0.074 + 0.076 + 0.076 - clk + cmos1_pclk - IOBS_LR_328_209/DIN + IOBD_169_0/DIN td - 1.504 - 1.578 + 0.735 + 0.811 r - clk_ibuf/opit_0/O + cmos1_pclk_ibuf/opit_0/O net (fanout=1) 0.000 - 1.578 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.058 - 1.636 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.478 - 2.114 + 0.811 - _N69 + cmos1_pclk_ibuf/ntD - PLL_158_55/CLK_OUT3 + IOL_171_6/INCK td - 0.088 - 2.202 + 0.038 + 0.849 r - u_sys_pll/u_pll_e3/goppll/CLKOUT3 + cmos1_pclk_ibuf/opit_1/INCK net (fanout=1) - 0.614 - 2.816 + 1.428 + 2.277 - clk_25m + _N64 - USCM_84_114/CLK_USCM + USCM_84_112/CLK_USCM td 0.000 - 2.816 + 2.277 r - clkbufg_7/gopclkbufg/CLKOUT + clkbufg_6/gopclkbufg/CLKOUT - net (fanout=26) - 0.925 - 3.741 + net (fanout=118) + 0.895 + 3.172 - ntclkbufg_7 + ntclkbufg_6 - CLMA_182_17/CLK + CLMA_138_60/CLK r - u_ov5640/coms1_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK - CLMA_182_17/Q0 + CLMA_138_60/Q0 tco - 0.221 - 3.962 - f - u_ov5640/coms1_reg_config/clock_20k_cnt[0]/opit_0_inv/Q - - - - net (fanout=4) - 0.365 - 4.327 - - u_ov5640/coms1_reg_config/clock_20k_cnt [0] - - - CLMA_182_13/Y2 - td - 0.381 - 4.708 - f - u_ov5640/coms1_reg_config/N8_mux4_5/gateop_perm/Z - - - - net (fanout=1) - 0.256 - 4.964 - - u_ov5640/coms1_reg_config/_N9664 - - - CLMA_186_16/Y0 - td - 0.150 - 5.114 - f - u_ov5640/coms1_reg_config/N8_mux10/gateop_perm/Z - - - - net (fanout=13) - 0.508 - 5.622 - - u_ov5640/coms1_reg_config/N8 - - - CLMA_182_12/COUT - td - 0.391 - 6.013 - r - u_ov5640/coms1_reg_config/N11_2_3/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 6.013 - - u_ov5640/coms1_reg_config/_N16248 - - - - td - 0.044 - 6.057 - r - u_ov5640/coms1_reg_config/N11_2_5/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 6.057 - - u_ov5640/coms1_reg_config/_N16250 - - - CLMA_182_16/COUT - td - 0.044 - 6.101 - r - u_ov5640/coms1_reg_config/N11_2_7/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 6.101 - - u_ov5640/coms1_reg_config/_N16252 - - - CLMA_182_20/Y1 - td - 0.366 - 6.467 + 0.179 + 3.351 f - u_ov5640/coms1_reg_config/N11_2_9/gateop_A2/Y1 + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/Q0 - net (fanout=1) - 0.273 - 6.740 + net (fanout=5) + 0.062 + 3.413 - u_ov5640/coms1_reg_config/N1114 [10] + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/wr_addr [8] - CLMA_182_20/M0 + CLMA_138_61/A0 f - u_ov5640/coms1_reg_config/clock_20k_cnt[10]/opit_0_inv/D + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/L0
- +
Location Delay Type @@ -120773,122 +125385,106 @@ Logical Resource - Clock clk_25m (rising edge) + Clock cmos1_pclk (rising edge) - 40.000 - 40.000 + 0.000 + 0.000 r - P20 + T12 0.000 - 40.000 + 0.000 r - clk (port) + cmos1_pclk (port) net (fanout=1) - 0.074 - 40.074 + 0.076 + 0.076 - clk + cmos1_pclk - IOBS_LR_328_209/DIN + IOBD_169_0/DIN td - 1.285 - 41.359 + 0.861 + 0.937 r - clk_ibuf/opit_0/O + cmos1_pclk_ibuf/opit_0/O net (fanout=1) 0.000 - 41.359 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.038 - 41.397 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.463 - 41.860 + 0.937 - _N69 + cmos1_pclk_ibuf/ntD - PLL_158_55/CLK_OUT3 + IOL_171_6/INCK td - 0.083 - 41.943 + 0.058 + 0.995 r - u_sys_pll/u_pll_e3/goppll/CLKOUT3 + cmos1_pclk_ibuf/opit_1/INCK net (fanout=1) - 0.603 - 42.546 + 1.455 + 2.450 - clk_25m + _N64 - USCM_84_114/CLK_USCM + USCM_84_112/CLK_USCM td 0.000 - 42.546 + 2.450 r - clkbufg_7/gopclkbufg/CLKOUT + clkbufg_6/gopclkbufg/CLKOUT - net (fanout=26) - 0.895 - 43.441 + net (fanout=118) + 0.925 + 3.375 - ntclkbufg_7 + ntclkbufg_6 - CLMA_182_20/CLK + CLMA_138_61/CLK r - u_ov5640/coms1_reg_config/clock_20k_cnt[10]/opit_0_inv/CLK + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/opit_0_L5Q_perm/CLK clock pessimism - 0.285 - 43.726 + -0.188 + 3.187 clock uncertainty - -0.150 - 43.576 + 0.200 + 3.387 - Setup time + Hold time - -0.068 - 43.508 + -0.078 + 3.309 @@ -120897,27 +125493,27 @@ - 36.768 - 4 - 13 - u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK - u_ov5640/coms2_reg_config/clock_20k_cnt[6]/opit_0_inv/D + 0.105 + 0 + 1 + u_hdmi_in_top/r_in3[3]/opit_0/CLK + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/DA0[3] - clk_25m - clk_25m + hdmi_in_clk + hdmi_in_clk rise-rise - -0.015 - 3.741 - 3.441 - 0.285 - 40.000 - 2.999 - 1.605 (53.5%) - 1.394 (46.5%) + 0.019 + 3.724 + 4.020 + -0.277 + 0.000 + 0.443 + 0.178 (40.2%) + 0.265 (59.8%) - Path #33: setup slack is 36.768(MET) + Path #5: hold slack is 0.105(MET) -
+
Location Delay Type @@ -120927,7 +125523,7 @@ Logical Resource - Clock clk_25m (rising edge) + Clock hdmi_in_clk (rising edge) 0.000 0.000 @@ -120935,201 +125531,105 @@ - P20 + AA12 0.000 0.000 r - clk (port) + hdmi_in_clk (port) net (fanout=1) - 0.074 - 0.074 + 0.078 + 0.078 - clk + hdmi_in_clk - IOBS_LR_328_209/DIN + IOBD_161_0/DIN td - 1.504 - 1.578 + 1.285 + 1.363 r - clk_ibuf/opit_0/O + hdmi_in_clk_ibuf/opit_0/O net (fanout=1) 0.000 - 1.578 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.058 - 1.636 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.478 - 2.114 + 1.363 - _N69 + hdmi_in_clk_ibuf/ntD - PLL_158_55/CLK_OUT3 + IOL_163_6/INCK td - 0.088 - 2.202 + 0.038 + 1.401 r - u_sys_pll/u_pll_e3/goppll/CLKOUT3 + hdmi_in_clk_ibuf/opit_1/INCK net (fanout=1) - 0.614 - 2.816 + 1.428 + 2.829 - clk_25m + _N37 - USCM_84_114/CLK_USCM + USCM_84_111/CLK_USCM td 0.000 - 2.816 + 2.829 r - clkbufg_7/gopclkbufg/CLKOUT + clkbufg_5/gopclkbufg/CLKOUT - net (fanout=26) - 0.925 - 3.741 + net (fanout=167) + 0.895 + 3.724 - ntclkbufg_7 + ntclkbufg_5 - CLMA_182_21/CLK + CLMS_94_89/CLK r - u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/CLK + u_hdmi_in_top/r_in3[3]/opit_0/CLK - CLMA_182_21/Q2 + CLMS_94_89/Q3 tco - 0.223 - 3.964 - f - u_ov5640/coms2_reg_config/clock_20k_cnt[0]/opit_0_inv/Q - - - - net (fanout=4) - 0.352 - 4.316 - - u_ov5640/coms2_reg_config/clock_20k_cnt [0] - - - CLMA_186_16/Y1 - td - 0.360 - 4.676 - f - u_ov5640/coms2_reg_config/N8_mux4_5/gateop_perm/Z - - - - net (fanout=1) - 0.251 - 4.927 - - u_ov5640/coms2_reg_config/_N9736 - - - CLMA_186_20/Y1 - td - 0.244 - 5.171 - f - u_ov5640/coms2_reg_config/N8_mux10/gateop_perm/Z - - - - net (fanout=13) - 0.398 - 5.569 - - u_ov5640/coms2_reg_config/N8 - - - - td - 0.368 - 5.937 - f - u_ov5640/coms2_reg_config/N11_2_1/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 5.937 - - u_ov5640/coms2_reg_config/_N16399 - - - CLMA_182_21/COUT - td - 0.044 - 5.981 - r - u_ov5640/coms2_reg_config/N11_2_3/gateop_A2/Cout - - - - net (fanout=1) - 0.000 - 5.981 - - u_ov5640/coms2_reg_config/_N16401 - - - CLMA_182_25/Y1 - td - 0.366 - 6.347 + 0.178 + 3.902 f - u_ov5640/coms2_reg_config/N11_2_5/gateop_A2/Y1 + u_hdmi_in_top/r_in3[3]/opit_0/Q net (fanout=1) - 0.393 - 6.740 + 0.265 + 4.167 - u_ov5640/coms2_reg_config/N1114 [6] + wr1_data_in[11] - CLMA_182_20/M1 + DRM_82_88/DA0[3] f - u_ov5640/coms2_reg_config/clock_20k_cnt[6]/opit_0_inv/D + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/DA0[3]
- +
Location Delay Type @@ -121139,122 +125639,106 @@ Logical Resource - Clock clk_25m (rising edge) - - 40.000 - 40.000 - r - - - - P20 - - 0.000 - 40.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 40.074 + Clock hdmi_in_clk (rising edge) + + 0.000 + 0.000 + r - clk - IOBS_LR_328_209/DIN - td - 1.285 - 41.359 + AA12 + + 0.000 + 0.000 r - clk_ibuf/opit_0/O + hdmi_in_clk (port) net (fanout=1) - 0.000 - 41.359 + 0.078 + 0.078 - clk_ibuf/ntD + hdmi_in_clk - IOL_327_210/INCK + IOBD_161_0/DIN td - 0.038 - 41.397 + 1.504 + 1.582 r - clk_ibuf/opit_1/INCK + hdmi_in_clk_ibuf/opit_0/O net (fanout=1) - 0.463 - 41.860 + 0.000 + 1.582 - _N69 + hdmi_in_clk_ibuf/ntD - PLL_158_55/CLK_OUT3 + IOL_163_6/INCK td - 0.083 - 41.943 + 0.058 + 1.640 r - u_sys_pll/u_pll_e3/goppll/CLKOUT3 + hdmi_in_clk_ibuf/opit_1/INCK net (fanout=1) - 0.603 - 42.546 + 1.455 + 3.095 - clk_25m + _N37 - USCM_84_114/CLK_USCM + USCM_84_111/CLK_USCM td 0.000 - 42.546 + 3.095 r - clkbufg_7/gopclkbufg/CLKOUT + clkbufg_5/gopclkbufg/CLKOUT - net (fanout=26) - 0.895 - 43.441 + net (fanout=167) + 0.925 + 4.020 - ntclkbufg_7 + ntclkbufg_5 - CLMA_182_20/CLK + DRM_82_88/CLKA[0] r - u_ov5640/coms2_reg_config/clock_20k_cnt[6]/opit_0_inv/CLK + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] clock pessimism - 0.285 - 43.726 + -0.277 + 3.743 clock uncertainty - -0.150 - 43.576 + 0.200 + 3.943 - Setup time + Hold time - -0.068 - 43.508 + 0.119 + 4.062 @@ -121263,27 +125747,27 @@ - 95.894 - 6 - 15 - ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK - ms72xx_ctl/ms7200_ctl/addr[0]/opit_0_inv_L5Q_perm/CE + 0.106 + 0 + 1 + u_hdmi_in_top/r_in3[5]/opit_0/CLK + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/DA0[5] - clk_10m - clk_10m + hdmi_in_clk + hdmi_in_clk rise-rise - -0.015 - 3.737 - 3.437 - 0.285 - 100.000 - 3.378 - 1.647 (48.8%) - 1.731 (51.2%) + 0.019 + 3.724 + 4.020 + -0.277 + 0.000 + 0.444 + 0.178 (40.1%) + 0.266 (59.9%) - Path #34: setup slack is 95.894(MET) + Path #6: hold slack is 0.106(MET) -
+
Location Delay Type @@ -121293,7 +125777,7 @@ Logical Resource - Clock clk_10m (rising edge) + Clock hdmi_in_clk (rising edge) 0.000 0.000 @@ -121301,217 +125785,105 @@ - P20 + AA12 0.000 0.000 r - clk (port) + hdmi_in_clk (port) net (fanout=1) - 0.074 - 0.074 + 0.078 + 0.078 - clk + hdmi_in_clk - IOBS_LR_328_209/DIN + IOBD_161_0/DIN td - 1.504 - 1.578 + 1.285 + 1.363 r - clk_ibuf/opit_0/O + hdmi_in_clk_ibuf/opit_0/O net (fanout=1) 0.000 - 1.578 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.058 - 1.636 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.478 - 2.114 + 1.363 - _N69 + hdmi_in_clk_ibuf/ntD - PLL_158_55/CLK_OUT4 + IOL_163_6/INCK td - 0.084 - 2.198 + 0.038 + 1.401 r - u_sys_pll/u_pll_e3/goppll/CLKOUT4 + hdmi_in_clk_ibuf/opit_1/INCK net (fanout=1) - 0.614 - 2.812 + 1.428 + 2.829 - clk_10m + _N37 - USCM_84_110/CLK_USCM + USCM_84_111/CLK_USCM td 0.000 - 2.812 + 2.829 r - clkbufg_3/gopclkbufg/CLKOUT + clkbufg_5/gopclkbufg/CLKOUT - net (fanout=235) - 0.925 - 3.737 + net (fanout=167) + 0.895 + 3.724 - ntclkbufg_3 + ntclkbufg_5 - CLMS_242_113/CLK + CLMA_90_92/CLK r - ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK + u_hdmi_in_top/r_in3[5]/opit_0/CLK - CLMS_242_113/Q3 + CLMA_90_92/Q3 tco - 0.220 - 3.957 - f - ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/Q - - - - net (fanout=3) - 0.274 - 4.231 - - ms72xx_ctl/ms7200_ctl/dri_cnt [4] - - - CLMS_246_113/Y2 - td - 0.381 - 4.612 + 0.178 + 3.902 f - ms72xx_ctl/ms7200_ctl/N8_3/gateop_perm/Z + u_hdmi_in_top/r_in3[5]/opit_0/Q net (fanout=1) - 0.069 - 4.681 - - ms72xx_ctl/ms7200_ctl/_N95853 - - - CLMS_246_113/Y0 - td - 0.150 - 4.831 - f - ms72xx_ctl/ms7200_ctl/N1872_5/gateop_perm/Z - - - - net (fanout=6) - 0.271 - 5.102 - - ms72xx_ctl/ms7200_ctl/_N95857 - - - CLMS_242_117/Y1 - td - 0.244 - 5.346 - f - ms72xx_ctl/ms7200_ctl/N2053_1/gateop_perm/Z - - - - net (fanout=15) - 0.506 - 5.852 - - ms72xx_ctl/ms7200_ctl/N261 - - - CLMA_226_104/Y1 - td - 0.151 - 6.003 - f - ms72xx_ctl/ms7200_ctl/N40_9/gateop_perm/Z - - - - net (fanout=4) - 0.309 - 6.312 - - ms72xx_ctl/ms7200_ctl/N2093 [4] - - - CLMA_230_121/Y3 - td - 0.360 - 6.672 - r - ms72xx_ctl/ms7200_ctl/N1955/gateop_perm/Z - - - - net (fanout=12) - 0.302 - 6.974 - - ms72xx_ctl/ms7200_ctl/N1955 - - - CLMA_242_116/CECO - td - 0.141 - 7.115 - r - ms72xx_ctl/ms7200_ctl/data_in[6]/opit_0_inv_L5Q_perm/CEOUT - - - - net (fanout=4) - 0.000 - 7.115 + 0.266 + 4.168 - ntR1773 + wr1_data_in[13] - CLMA_242_120/CECI + DRM_82_88/DA0[5] - r - ms72xx_ctl/ms7200_ctl/addr[0]/opit_0_inv_L5Q_perm/CE + f + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/DA0[5]
- +
Location Delay Type @@ -121521,122 +125893,106 @@ Logical Resource - Clock clk_10m (rising edge) + Clock hdmi_in_clk (rising edge) - 100.000 - 100.000 + 0.000 + 0.000 r - P20 + AA12 0.000 - 100.000 + 0.000 r - clk (port) + hdmi_in_clk (port) net (fanout=1) - 0.074 - 100.074 + 0.078 + 0.078 - clk + hdmi_in_clk - IOBS_LR_328_209/DIN + IOBD_161_0/DIN td - 1.285 - 101.359 + 1.504 + 1.582 r - clk_ibuf/opit_0/O + hdmi_in_clk_ibuf/opit_0/O net (fanout=1) 0.000 - 101.359 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.038 - 101.397 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.463 - 101.860 + 1.582 - _N69 + hdmi_in_clk_ibuf/ntD - PLL_158_55/CLK_OUT4 + IOL_163_6/INCK td - 0.079 - 101.939 + 0.058 + 1.640 r - u_sys_pll/u_pll_e3/goppll/CLKOUT4 + hdmi_in_clk_ibuf/opit_1/INCK net (fanout=1) - 0.603 - 102.542 + 1.455 + 3.095 - clk_10m + _N37 - USCM_84_110/CLK_USCM + USCM_84_111/CLK_USCM td 0.000 - 102.542 + 3.095 r - clkbufg_3/gopclkbufg/CLKOUT + clkbufg_5/gopclkbufg/CLKOUT - net (fanout=235) - 0.895 - 103.437 + net (fanout=167) + 0.925 + 4.020 - ntclkbufg_3 + ntclkbufg_5 - CLMA_242_120/CLK + DRM_82_88/CLKA[0] r - ms72xx_ctl/ms7200_ctl/addr[0]/opit_0_inv_L5Q_perm/CLK + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] clock pessimism - 0.285 - 103.722 + -0.277 + 3.743 clock uncertainty - -0.150 - 103.572 + 0.200 + 3.943 - Setup time + Hold time - -0.563 - 103.009 + 0.119 + 4.062 @@ -121645,27 +126001,27 @@ - 95.894 - 6 - 15 - ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK - ms72xx_ctl/ms7200_ctl/data_in[0]/opit_0_inv_L5Q_perm/CE + 0.108 + 0 + 1 + u_ov5640/cmos1_8_16bit/pdata_i2[4]/opit_0/CLK + u_ov5640/cmos1_8_16bit/image_data0[12]/opit_0/D - clk_10m - clk_10m + cmos1_pclk + cmos1_pclk rise-rise - -0.015 - 3.737 - 3.437 - 0.285 - 100.000 - 3.378 - 1.647 (48.8%) - 1.731 (51.2%) + 0.015 + 3.172 + 3.375 + -0.188 + 0.000 + 0.363 + 0.228 (62.8%) + 0.135 (37.2%) - Path #35: setup slack is 95.894(MET) + Path #7: hold slack is 0.108(MET) -
+
Location Delay Type @@ -121675,7 +126031,7 @@ Logical Resource - Clock clk_10m (rising edge) + Clock cmos1_pclk (rising edge) 0.000 0.000 @@ -121683,217 +126039,105 @@ - P20 + T12 0.000 0.000 r - clk (port) + cmos1_pclk (port) net (fanout=1) - 0.074 - 0.074 + 0.076 + 0.076 - clk + cmos1_pclk - IOBS_LR_328_209/DIN + IOBD_169_0/DIN td - 1.504 - 1.578 + 0.735 + 0.811 r - clk_ibuf/opit_0/O + cmos1_pclk_ibuf/opit_0/O net (fanout=1) 0.000 - 1.578 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.058 - 1.636 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.478 - 2.114 + 0.811 - _N69 + cmos1_pclk_ibuf/ntD - PLL_158_55/CLK_OUT4 + IOL_171_6/INCK td - 0.084 - 2.198 + 0.038 + 0.849 r - u_sys_pll/u_pll_e3/goppll/CLKOUT4 + cmos1_pclk_ibuf/opit_1/INCK net (fanout=1) - 0.614 - 2.812 + 1.428 + 2.277 - clk_10m + _N64 - USCM_84_110/CLK_USCM + USCM_84_112/CLK_USCM td 0.000 - 2.812 + 2.277 r - clkbufg_3/gopclkbufg/CLKOUT + clkbufg_6/gopclkbufg/CLKOUT - net (fanout=235) - 0.925 - 3.737 + net (fanout=118) + 0.895 + 3.172 - ntclkbufg_3 + ntclkbufg_6 - CLMS_242_113/CLK + CLMA_138_44/CLK r - ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK + u_ov5640/cmos1_8_16bit/pdata_i2[4]/opit_0/CLK - CLMS_242_113/Q3 + CLMA_138_44/Y0 tco - 0.220 - 3.957 - f - ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/Q - - - - net (fanout=3) - 0.274 - 4.231 - - ms72xx_ctl/ms7200_ctl/dri_cnt [4] - - - CLMS_246_113/Y2 - td - 0.381 - 4.612 + 0.228 + 3.400 f - ms72xx_ctl/ms7200_ctl/N8_3/gateop_perm/Z + u_ov5640/cmos1_8_16bit/pdata_i2[4]/opit_0/Q net (fanout=1) - 0.069 - 4.681 - - ms72xx_ctl/ms7200_ctl/_N95853 - - - CLMS_246_113/Y0 - td - 0.150 - 4.831 - f - ms72xx_ctl/ms7200_ctl/N1872_5/gateop_perm/Z - - - - net (fanout=6) - 0.271 - 5.102 - - ms72xx_ctl/ms7200_ctl/_N95857 - - - CLMS_242_117/Y1 - td - 0.244 - 5.346 - f - ms72xx_ctl/ms7200_ctl/N2053_1/gateop_perm/Z - - - - net (fanout=15) - 0.506 - 5.852 - - ms72xx_ctl/ms7200_ctl/N261 - - - CLMA_226_104/Y1 - td - 0.151 - 6.003 - f - ms72xx_ctl/ms7200_ctl/N40_9/gateop_perm/Z - - - - net (fanout=4) - 0.309 - 6.312 - - ms72xx_ctl/ms7200_ctl/N2093 [4] - - - CLMA_230_121/Y3 - td - 0.360 - 6.672 - r - ms72xx_ctl/ms7200_ctl/N1955/gateop_perm/Z - - - - net (fanout=12) - 0.302 - 6.974 - - ms72xx_ctl/ms7200_ctl/N1955 - - - CLMA_242_116/CECO - td - 0.141 - 7.115 - r - ms72xx_ctl/ms7200_ctl/data_in[6]/opit_0_inv_L5Q_perm/CEOUT - - - - net (fanout=4) - 0.000 - 7.115 + 0.135 + 3.535 - ntR1773 + u_ov5640/cmos1_8_16bit/pdata_i2 [4] - CLMA_242_120/CECI + CLMA_138_45/AD - r - ms72xx_ctl/ms7200_ctl/data_in[0]/opit_0_inv_L5Q_perm/CE + f + u_ov5640/cmos1_8_16bit/image_data0[12]/opit_0/D
- +
Location Delay Type @@ -121903,122 +126147,106 @@ Logical Resource - Clock clk_10m (rising edge) + Clock cmos1_pclk (rising edge) - 100.000 - 100.000 + 0.000 + 0.000 r - P20 + T12 0.000 - 100.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 100.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.285 - 101.359 + 0.000 r - clk_ibuf/opit_0/O + cmos1_pclk (port) net (fanout=1) - 0.000 - 101.359 + 0.076 + 0.076 - clk_ibuf/ntD + cmos1_pclk - IOL_327_210/INCK + IOBD_169_0/DIN td - 0.038 - 101.397 + 0.861 + 0.937 r - clk_ibuf/opit_1/INCK + cmos1_pclk_ibuf/opit_0/O net (fanout=1) - 0.463 - 101.860 + 0.000 + 0.937 - _N69 + cmos1_pclk_ibuf/ntD - PLL_158_55/CLK_OUT4 + IOL_171_6/INCK td - 0.079 - 101.939 + 0.058 + 0.995 r - u_sys_pll/u_pll_e3/goppll/CLKOUT4 + cmos1_pclk_ibuf/opit_1/INCK net (fanout=1) - 0.603 - 102.542 + 1.455 + 2.450 - clk_10m + _N64 - USCM_84_110/CLK_USCM + USCM_84_112/CLK_USCM td 0.000 - 102.542 + 2.450 r - clkbufg_3/gopclkbufg/CLKOUT + clkbufg_6/gopclkbufg/CLKOUT - net (fanout=235) - 0.895 - 103.437 + net (fanout=118) + 0.925 + 3.375 - ntclkbufg_3 + ntclkbufg_6 - CLMA_242_120/CLK + CLMA_138_45/CLK r - ms72xx_ctl/ms7200_ctl/data_in[0]/opit_0_inv_L5Q_perm/CLK + u_ov5640/cmos1_8_16bit/image_data0[12]/opit_0/CLK clock pessimism - 0.285 - 103.722 + -0.188 + 3.187 clock uncertainty - -0.150 - 103.572 + 0.200 + 3.387 - Setup time + Hold time - -0.563 - 103.009 + 0.040 + 3.427 @@ -122027,27 +126255,27 @@ - 95.894 - 6 - 15 - ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK - ms72xx_ctl/ms7200_ctl/data_in[3]/opit_0_inv_L5Q_perm/CE + 0.115 + 0 + 44 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_15/ram16x1d/WADM0 - clk_10m - clk_10m + ddrphy_clkin + ddrphy_clkin rise-rise - -0.015 - 3.737 - 3.437 - 0.285 - 100.000 - 3.378 - 1.647 (48.8%) - 1.731 (51.2%) + 0.039 + 6.677 + 7.144 + -0.428 + 0.000 + 0.447 + 0.179 (40.0%) + 0.268 (60.0%) - Path #36: setup slack is 95.894(MET) + Path #8: hold slack is 0.115(MET) -
+
Location Delay Type @@ -122057,7 +126285,7 @@ Logical Resource - Clock clk_10m (rising edge) + Clock ddrphy_clkin (rising edge) 0.000 0.000 @@ -122083,8 +126311,8 @@ IOBS_LR_328_209/DIN td - 1.504 - 1.578 + 1.285 + 1.359 r clk_ibuf/opit_0/O @@ -122092,190 +126320,158 @@ net (fanout=1) 0.000 - 1.578 + 1.359 clk_ibuf/ntD IOL_327_210/INCK td - 0.058 - 1.636 + 0.038 + 1.397 r clk_ibuf/opit_1/INCK net (fanout=1) - 0.478 - 2.114 + 0.463 + 1.860 _N69 - PLL_158_55/CLK_OUT4 + PLL_158_55/CLK_OUT1 td - 0.084 - 2.198 + 0.074 + 1.934 r - u_sys_pll/u_pll_e3/goppll/CLKOUT4 + u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=1) - 0.614 - 2.812 + net (fanout=2) + 0.603 + 2.537 - clk_10m + ddr_clk - USCM_84_110/CLK_USCM + USCM_84_113/CLK_USCM td 0.000 - 2.812 + 2.537 r - clkbufg_3/gopclkbufg/CLKOUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=235) - 0.925 - 3.737 + net (fanout=71) + 0.981 + 3.518 - ntclkbufg_3 + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - CLMS_242_113/CLK - - - + PLL_158_199/CLK_OUT0_WL + td + 0.089 + 3.607 r - ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/CLK - - - CLMS_242_113/Q3 - tco - 0.220 - 3.957 - f - ms72xx_ctl/ms7200_ctl/dri_cnt[4]/opit_0_inv_L5Q_perm/Q + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) - 0.274 - 4.231 - - ms72xx_ctl/ms7200_ctl/dri_cnt [4] + 0.669 + 4.276 + + clkout0_wl_0 - CLMS_246_113/Y2 + IOCKGATE_6_322/OUT td - 0.381 - 4.612 - f - ms72xx_ctl/ms7200_ctl/N8_3/gateop_perm/Z + 0.200 + 4.476 + r + clkgate_9/gopclkgate/OUT net (fanout=1) - 0.069 - 4.681 - - ms72xx_ctl/ms7200_ctl/_N95853 - - - CLMS_246_113/Y0 - td - 0.150 - 4.831 - f - ms72xx_ctl/ms7200_ctl/N1872_5/gateop_perm/Z - - + 0.000 + 4.476 - net (fanout=6) - 0.271 - 5.102 - - ms72xx_ctl/ms7200_ctl/_N95857 + ntclkgate_0 - CLMS_242_117/Y1 + IOCKDIV_6_323/CLK_IODIV td - 0.244 - 5.346 - f - ms72xx_ctl/ms7200_ctl/N2053_1/gateop_perm/Z + 0.000 + 4.476 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV - net (fanout=15) - 0.506 - 5.852 - - ms72xx_ctl/ms7200_ctl/N261 - - - CLMA_226_104/Y1 - td - 0.151 - 6.003 - f - ms72xx_ctl/ms7200_ctl/N40_9/gateop_perm/Z - - + net (fanout=1) + 1.283 + 5.759 - net (fanout=4) - 0.309 - 6.312 - - ms72xx_ctl/ms7200_ctl/N2093 [4] + u_axi_ddr_top/clk - CLMA_230_121/Y3 + USCM_84_116/CLK_USCM td - 0.360 - 6.672 + 0.000 + 5.759 r - ms72xx_ctl/ms7200_ctl/N1955/gateop_perm/Z + clkbufg_0/gopclkbufg/CLKOUT - net (fanout=12) - 0.302 - 6.974 - - ms72xx_ctl/ms7200_ctl/N1955 + net (fanout=5464) + 0.918 + 6.677 + + ntclkbufg_0 - CLMA_242_116/CECO - td - 0.141 - 7.115 + CLMA_34_76/CLK + + + r - ms72xx_ctl/ms7200_ctl/data_in[6]/opit_0_inv_L5Q_perm/CEOUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK + + + CLMA_34_76/Q0 + tco + 0.179 + 6.856 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/Q0 - net (fanout=4) - 0.000 - 7.115 + net (fanout=44) + 0.268 + 7.124 - ntR1773 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [0] - CLMA_242_120/CECI + CLMS_42_81/M0 - r - ms72xx_ctl/ms7200_ctl/data_in[3]/opit_0_inv_L5Q_perm/CE + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_15/ram16x1d/WADM0
- +
Location Delay Type @@ -122285,10 +126481,10 @@ Logical Resource - Clock clk_10m (rising edge) + Clock ddrphy_clkin (rising edge) - 100.000 - 100.000 + 0.000 + 0.000 r @@ -122296,7 +126492,7 @@ P200.000 - 100.000 + 0.000rclk (port) @@ -122304,15 +126500,15 @@ net (fanout=1) 0.074 - 100.074 + 0.074 clk IOBS_LR_328_209/DIN td - 1.285 - 101.359 + 1.504 + 1.578 r clk_ibuf/opit_0/O @@ -122320,87 +126516,151 @@ net (fanout=1) 0.000 - 101.359 + 1.578 clk_ibuf/ntD IOL_327_210/INCK td - 0.038 - 101.397 + 0.058 + 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) - 0.463 - 101.860 + 0.478 + 2.114 _N69 - PLL_158_55/CLK_OUT4 + PLL_158_55/CLK_OUT1 td 0.079 - 101.939 + 2.193 r - u_sys_pll/u_pll_e3/goppll/CLKOUT4 + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 0.614 + 2.807 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 2.807 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 1.019 + 3.826 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.094 + 3.920 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 0.682 + 4.602 + + clkout0_wl_0 + + + IOCKGATE_6_322/OUT + td + 0.268 + 4.870 + r + clkgate_9/gopclkgate/OUT net (fanout=1) - 0.603 - 102.542 + 0.000 + 4.870 - clk_10m + ntclkgate_0 - USCM_84_110/CLK_USCM + IOCKDIV_6_323/CLK_IODIV td 0.000 - 102.542 + 4.870 r - clkbufg_3/gopclkbufg/CLKOUT + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV - net (fanout=235) - 0.895 - 103.437 + net (fanout=1) + 1.306 + 6.176 - ntclkbufg_3 + u_axi_ddr_top/clk + + + USCM_84_116/CLK_USCM + td + 0.000 + 6.176 + r + clkbufg_0/gopclkbufg/CLKOUT + + + + net (fanout=5464) + 0.968 + 7.144 + + ntclkbufg_0 - CLMA_242_120/CLK + CLMS_42_81/CLK r - ms72xx_ctl/ms7200_ctl/data_in[3]/opit_0_inv_L5Q_perm/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_15/ram16x1d/WCLK clock pessimism - 0.285 - 103.722 + -0.428 + 6.716 clock uncertainty - -0.150 - 103.572 + 0.000 + 6.716 - Setup time + Hold time - -0.563 - 103.009 + 0.293 + 7.009 @@ -122409,27 +126669,27 @@ - 49996.400 - 3 - 1 - u_ov5640/coms2_reg_config/reg_data/iGopDrm/CLKB[0] - u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I0 + 0.115 + 0 + 44 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_16/ram16x1d/WADM0 - clk_20k - clk_20k + ddrphy_clkin + ddrphy_clkin rise-rise - -0.019 - 6.109 - 5.644 - 0.446 - 50000.000 - 3.408 - 2.512 (73.7%) - 0.896 (26.3%) + 0.039 + 6.677 + 7.144 + -0.428 + 0.000 + 0.447 + 0.179 (40.0%) + 0.268 (60.0%) - Path #37: setup slack is 49996.400(MET) + Path #9: hold slack is 0.115(MET) -
+
Location Delay Type @@ -122439,7 +126699,7 @@ Logical Resource - Clock clk_20k (rising edge) + Clock ddrphy_clkin (rising edge) 0.000 0.000 @@ -122465,8 +126725,8 @@ IOBS_LR_328_209/DIN td - 1.504 - 1.578 + 1.285 + 1.359 r clk_ibuf/opit_0/O @@ -122474,174 +126734,158 @@ net (fanout=1) 0.000 - 1.578 + 1.359 clk_ibuf/ntD IOL_327_210/INCK td - 0.058 - 1.636 + 0.038 + 1.397 r clk_ibuf/opit_1/INCK net (fanout=1) - 0.478 - 2.114 + 0.463 + 1.860 _N69 - PLL_158_55/CLK_OUT3 + PLL_158_55/CLK_OUT1 td - 0.088 - 2.202 + 0.074 + 1.934 r - u_sys_pll/u_pll_e3/goppll/CLKOUT3 + u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=1) - 0.614 - 2.816 + net (fanout=2) + 0.603 + 2.537 - clk_25m + ddr_clk - USCM_84_114/CLK_USCM + USCM_84_113/CLK_USCM td 0.000 - 2.816 + 2.537 r - clkbufg_7/gopclkbufg/CLKOUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=26) - 0.925 - 3.741 + net (fanout=71) + 0.981 + 3.518 - ntclkbufg_7 + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - CLMA_182_25/Q1 - tco - 0.224 - 3.965 + PLL_158_199/CLK_OUT0_WL + td + 0.089 + 3.607 r - u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) - 1.219 - 5.184 + 0.669 + 4.276 - u_ov5640/coms2_reg_config/clk_20k_regdiv + clkout0_wl_0 - USCM_84_120/CLK_USCM + IOCKGATE_6_322/OUT td - 0.000 - 5.184 + 0.200 + 4.476 r - u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + clkgate_9/gopclkgate/OUT - net (fanout=19) - 0.925 - 6.109 + net (fanout=1) + 0.000 + 4.476 - u_ov5640/coms2_reg_config/clock_20k + ntclkgate_0 - DRM_178_24/CLKB[0] - - - + IOCKDIV_6_323/CLK_IODIV + td + 0.000 + 4.476 r - u_ov5640/coms2_reg_config/reg_data/iGopDrm/CLKB[0] - - - DRM_178_24/QB0[5] - tco - 1.780 - 7.889 - f - u_ov5640/coms2_reg_config/reg_data/iGopDrm/QB0[5] + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) - 0.327 - 8.216 - - u_ov5640/coms2_reg_config/i2c_data [21] + 1.283 + 5.759 + + u_axi_ddr_top/clk - CLMA_174_32/Y3 + USCM_84_116/CLK_USCM td - 0.358 - 8.574 - f - u_ov5640/coms2_reg_config/u1/N267_29/gateop/F + 0.000 + 5.759 + r + clkbufg_0/gopclkbufg/CLKOUT - net (fanout=1) - 0.250 - 8.824 - - u_ov5640/coms2_reg_config/u1/_N25904 - - - CLMS_174_29/Y2 - td - 0.162 - 8.986 - r - u_ov5640/coms2_reg_config/u1/N267_35/gateop_perm/Z + net (fanout=5464) + 0.918 + 6.677 + + ntclkbufg_0 + CLMA_34_76/CLK - net (fanout=1) - 0.152 - 9.138 - - u_ov5640/coms2_reg_config/u1/_N25910 + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK - CLMS_174_29/Y1 - td - 0.212 - 9.350 + CLMA_34_76/Q0 + tco + 0.179 + 6.856 f - u_ov5640/coms2_reg_config/u1/N267_36/gateop/F + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/Q0 - net (fanout=1) - 0.167 - 9.517 + net (fanout=44) + 0.268 + 7.124 - u_ov5640/coms2_reg_config/u1/_N25911 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [0] - CLMS_174_25/DD + CLMS_42_81/M0 f - u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I0 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_16/ram16x1d/WADM0
- +
Location Delay Type @@ -122651,10 +126895,10 @@ Logical Resource - Clock clk_20k (rising edge) + Clock ddrphy_clkin (rising edge) - 50000.000 - 50000.000 + 0.000 + 0.000 r @@ -122662,7 +126906,7 @@ P200.000 - 50000.000 + 0.000rclk (port) @@ -122670,15 +126914,15 @@ net (fanout=1) 0.074 - 50000.074 + 0.074 clk IOBS_LR_328_209/DIN td - 1.285 - 50001.359 + 1.504 + 1.578 r clk_ibuf/opit_0/O @@ -122686,119 +126930,151 @@ net (fanout=1) 0.000 - 50001.359 + 1.578 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.058 + 1.636 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.478 + 2.114 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.079 + 2.193 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 0.614 + 2.807 - clk_ibuf/ntD + ddr_clk - IOL_327_210/INCK + USCM_84_113/CLK_USCM td - 0.038 - 50001.397 + 0.000 + 2.807 r - clk_ibuf/opit_1/INCK + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=1) - 0.463 - 50001.860 + net (fanout=71) + 1.019 + 3.826 - _N69 + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - PLL_158_55/CLK_OUT3 + PLL_158_199/CLK_OUT0_WL td - 0.083 - 50001.943 + 0.094 + 3.920 r - u_sys_pll/u_pll_e3/goppll/CLKOUT3 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - net (fanout=1) - 0.603 - 50002.546 + net (fanout=3) + 0.682 + 4.602 - clk_25m + clkout0_wl_0 - USCM_84_114/CLK_USCM + IOCKGATE_6_322/OUT td - 0.000 - 50002.546 + 0.268 + 4.870 r - clkbufg_7/gopclkbufg/CLKOUT + clkgate_9/gopclkgate/OUT - net (fanout=26) - 0.895 - 50003.441 + net (fanout=1) + 0.000 + 4.870 - ntclkbufg_7 + ntclkgate_0 - CLMA_182_25/Q1 - tco - 0.184 - 50003.625 + IOCKDIV_6_323/CLK_IODIV + td + 0.000 + 4.870 r - u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV - net (fanout=3) - 1.124 - 50004.749 + net (fanout=1) + 1.306 + 6.176 - u_ov5640/coms2_reg_config/clk_20k_regdiv + u_axi_ddr_top/clk - USCM_84_120/CLK_USCM + USCM_84_116/CLK_USCM td 0.000 - 50004.749 + 6.176 r - u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + clkbufg_0/gopclkbufg/CLKOUT - net (fanout=19) - 0.895 - 50005.644 + net (fanout=5464) + 0.968 + 7.144 - u_ov5640/coms2_reg_config/clock_20k + ntclkbufg_0 - CLMS_174_25/CLK + CLMS_42_81/CLK r - u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_16/ram16x1d/WCLK clock pessimism - 0.446 - 50006.090 + -0.428 + 6.716 clock uncertainty - -0.050 - 50006.040 + 0.000 + 6.716 - Setup time + Hold time - -0.123 - 50005.917 + 0.293 + 7.009 @@ -122807,27 +127083,27 @@ - 49996.463 - 3 - 1 - u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0] - u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I0 + 0.115 + 0 + 44 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_17/ram16x1d/WADM0 - clk_20k - clk_20k + ddrphy_clkin + ddrphy_clkin rise-rise - -0.019 - 6.274 - 5.784 - 0.471 - 50000.000 - 3.341 - 2.532 (75.8%) - 0.809 (24.2%) + 0.039 + 6.677 + 7.144 + -0.428 + 0.000 + 0.447 + 0.179 (40.0%) + 0.268 (60.0%) - Path #38: setup slack is 49996.463(MET) + Path #10: hold slack is 0.115(MET) -
+
Location Delay Type @@ -122837,7 +127113,7 @@ Logical Resource - Clock clk_20k (rising edge) + Clock ddrphy_clkin (rising edge) 0.000 0.000 @@ -122863,8 +127139,8 @@ IOBS_LR_328_209/DIN td - 1.504 - 1.578 + 1.285 + 1.359 r clk_ibuf/opit_0/O @@ -122872,174 +127148,158 @@ net (fanout=1) 0.000 - 1.578 + 1.359 clk_ibuf/ntD IOL_327_210/INCK td - 0.058 - 1.636 + 0.038 + 1.397 r clk_ibuf/opit_1/INCK net (fanout=1) - 0.478 - 2.114 + 0.463 + 1.860 _N69 - PLL_158_55/CLK_OUT3 + PLL_158_55/CLK_OUT1 td - 0.088 - 2.202 + 0.074 + 1.934 r - u_sys_pll/u_pll_e3/goppll/CLKOUT3 + u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=1) - 0.614 - 2.816 + net (fanout=2) + 0.603 + 2.537 - clk_25m + ddr_clk - USCM_84_114/CLK_USCM + USCM_84_113/CLK_USCM td 0.000 - 2.816 + 2.537 r - clkbufg_7/gopclkbufg/CLKOUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=26) - 0.925 - 3.741 + net (fanout=71) + 0.981 + 3.518 - ntclkbufg_7 + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - CLMA_182_12/Q1 - tco - 0.224 - 3.965 + PLL_158_199/CLK_OUT0_WL + td + 0.089 + 3.607 r - u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) - 1.384 - 5.349 + 0.669 + 4.276 - u_ov5640/coms1_reg_config/clk_20k_regdiv + clkout0_wl_0 - USCM_84_119/CLK_USCM + IOCKGATE_6_322/OUT td - 0.000 - 5.349 + 0.200 + 4.476 r - u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + clkgate_9/gopclkgate/OUT - net (fanout=19) - 0.925 - 6.274 + net (fanout=1) + 0.000 + 4.476 - u_ov5640/coms1_reg_config/clock_20k + ntclkgate_0 - DRM_178_4/CLKB[0] - - - + IOCKDIV_6_323/CLK_IODIV + td + 0.000 + 4.476 r - u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0] - - - DRM_178_4/QB0[6] - tco - 1.780 - 8.054 - f - u_ov5640/coms1_reg_config/reg_data/iGopDrm/QB0[6] + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) - 0.400 - 8.454 - - u_ov5640/coms1_reg_config/i2c_data [22] - - - CLMS_174_9/Y2 - td - 0.379 - 8.833 - f - u_ov5640/coms1_reg_config/u1/N267_29/gateop/F - - + 1.283 + 5.759 - net (fanout=1) - 0.069 - 8.902 - - u_ov5640/coms1_reg_config/u1/_N25461 + u_axi_ddr_top/clk - CLMA_174_8/Y0 + USCM_84_116/CLK_USCM td - 0.162 - 9.064 + 0.000 + 5.759 r - u_ov5640/coms1_reg_config/u1/N267_35/gateop_perm/Z + clkbufg_0/gopclkbufg/CLKOUT - net (fanout=1) - 0.072 - 9.136 - - u_ov5640/coms1_reg_config/u1/_N25467 + net (fanout=5464) + 0.918 + 6.677 + + ntclkbufg_0 - CLMA_174_8/Y1 - td - 0.211 - 9.347 + CLMA_34_76/CLK + + + r - u_ov5640/coms1_reg_config/u1/N267_36/gateop/F + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK + + + CLMA_34_76/Q0 + tco + 0.179 + 6.856 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/Q0 - net (fanout=1) + net (fanout=44) 0.268 - 9.615 + 7.124 - u_ov5640/coms1_reg_config/u1/_N25468 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [0] - CLMA_174_16/DD + CLMS_42_81/M0 - r - u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I0 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_17/ram16x1d/WADM0
- +
Location Delay Type @@ -123049,10 +127309,10 @@ Logical Resource - Clock clk_20k (rising edge) + Clock ddrphy_clkin (rising edge) - 50000.000 - 50000.000 + 0.000 + 0.000 r @@ -123060,7 +127320,7 @@ P200.000 - 50000.000 + 0.000rclk (port) @@ -123068,15 +127328,15 @@ net (fanout=1) 0.074 - 50000.074 + 0.074 clk IOBS_LR_328_209/DIN td - 1.285 - 50001.359 + 1.504 + 1.578 r clk_ibuf/opit_0/O @@ -123084,119 +127344,151 @@ net (fanout=1) 0.000 - 50001.359 + 1.578 clk_ibuf/ntD IOL_327_210/INCK td - 0.038 - 50001.397 + 0.058 + 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) - 0.463 - 50001.860 + 0.478 + 2.114 _N69 - PLL_158_55/CLK_OUT3 + PLL_158_55/CLK_OUT1 td - 0.083 - 50001.943 + 0.079 + 2.193 r - u_sys_pll/u_pll_e3/goppll/CLKOUT3 + u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=1) - 0.603 - 50002.546 + net (fanout=2) + 0.614 + 2.807 - clk_25m + ddr_clk - USCM_84_114/CLK_USCM + USCM_84_113/CLK_USCM td 0.000 - 50002.546 + 2.807 r - clkbufg_7/gopclkbufg/CLKOUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=26) - 0.895 - 50003.441 + net (fanout=71) + 1.019 + 3.826 - ntclkbufg_7 + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - CLMA_182_12/Q1 - tco - 0.184 - 50003.625 + PLL_158_199/CLK_OUT0_WL + td + 0.094 + 3.920 r - u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) - 1.264 - 50004.889 + 0.682 + 4.602 - u_ov5640/coms1_reg_config/clk_20k_regdiv + clkout0_wl_0 - USCM_84_119/CLK_USCM + IOCKGATE_6_322/OUT + td + 0.268 + 4.870 + r + clkgate_9/gopclkgate/OUT + + + + net (fanout=1) + 0.000 + 4.870 + + ntclkgate_0 + + + IOCKDIV_6_323/CLK_IODIV td 0.000 - 50004.889 + 4.870 r - u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV - net (fanout=19) - 0.895 - 50005.784 + net (fanout=1) + 1.306 + 6.176 - u_ov5640/coms1_reg_config/clock_20k + u_axi_ddr_top/clk + + + USCM_84_116/CLK_USCM + td + 0.000 + 6.176 + r + clkbufg_0/gopclkbufg/CLKOUT + + + + net (fanout=5464) + 0.968 + 7.144 + + ntclkbufg_0 - CLMA_174_16/CLK + CLMS_42_81/CLK r - u_ov5640/coms1_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_17/ram16x1d/WCLK clock pessimism - 0.471 - 50006.255 + -0.428 + 6.716 clock uncertainty - -0.050 - 50006.205 + 0.000 + 6.716 - Setup time + Hold time - -0.127 - 50006.078 + 0.293 + 7.009 @@ -123205,27 +127497,27 @@ - 49996.551 - 1 - 1 - u_ov5640/coms2_reg_config/reg_data/iGopDrm/CLKB[0] - u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I3 + 0.143 + 0 + 5 + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[10] - clk_20k - clk_20k + clk_50m + clk_50m rise-rise - -0.019 - 6.109 - 5.644 - 0.446 - 50000.000 - 3.232 - 2.249 (69.6%) - 0.983 (30.4%) + 0.019 + 3.436 + 3.736 + -0.281 + 0.000 + 0.328 + 0.182 (55.5%) + 0.146 (44.5%) - Path #39: setup slack is 49996.551(MET) + Path #11: hold slack is 0.143(MET) -
+
Location Delay Type @@ -123235,7 +127527,7 @@ Logical Resource - Clock clk_20k (rising edge) + Clock clk_50m (rising edge) 0.000 0.000 @@ -123261,8 +127553,8 @@ IOBS_LR_328_209/DIN td - 1.504 - 1.578 + 1.285 + 1.359 r clk_ibuf/opit_0/O @@ -123270,142 +127562,94 @@ net (fanout=1) 0.000 - 1.578 + 1.359 clk_ibuf/ntD IOL_327_210/INCK td - 0.058 - 1.636 + 0.038 + 1.397 r clk_ibuf/opit_1/INCK net (fanout=1) - 0.478 - 2.114 + 0.463 + 1.860 _N69 - PLL_158_55/CLK_OUT3 - td - 0.088 - 2.202 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT3 - - - - net (fanout=1) - 0.614 - 2.816 - - clk_25m - - - USCM_84_114/CLK_USCM + PLL_158_55/CLK_OUT0 td - 0.000 - 2.816 - r - clkbufg_7/gopclkbufg/CLKOUT - - - - net (fanout=26) - 0.925 - 3.741 - - ntclkbufg_7 - - - CLMA_182_25/Q1 - tco - 0.224 - 3.965 + 0.078 + 1.938 r - u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q + u_sys_pll/u_pll_e3/goppll/CLKOUT0 - net (fanout=3) - 1.219 - 5.184 + net (fanout=2) + 0.603 + 2.541 - u_ov5640/coms2_reg_config/clk_20k_regdiv + rd3_clk - USCM_84_120/CLK_USCM + USCM_84_108/CLK_USCM td 0.000 - 5.184 + 2.541 r - u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + clkbufg_1/gopclkbufg/CLKOUT - net (fanout=19) - 0.925 - 6.109 + net (fanout=2516) + 0.895 + 3.436 - u_ov5640/coms2_reg_config/clock_20k + ntclkbufg_1 - DRM_178_24/CLKB[0] + CLMS_50_117/CLK r - u_ov5640/coms2_reg_config/reg_data/iGopDrm/CLKB[0] + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/CLK - DRM_178_24/QB0[1] + CLMS_50_117/Q0 tco - 1.780 - 7.889 - f - u_ov5640/coms2_reg_config/reg_data/iGopDrm/QB0[1] - - - - net (fanout=1) - 0.514 - 8.403 - - u_ov5640/coms2_reg_config/i2c_data [17] - - - CLMA_182_33/Y1 - td - 0.469 - 8.872 - f - u_ov5640/coms2_reg_config/u1/N267_18_muxf7/F + 0.182 + 3.618 + r + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/opit_0_inv_A2Q21/Q0 - net (fanout=1) - 0.469 - 9.341 + net (fanout=5) + 0.146 + 3.764 - u_ov5640/coms2_reg_config/u1/_N25893 + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/wr_addr [8] - CLMS_174_25/D0 + DRM_54_108/ADA0[10] - f - u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/I3 + r + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[10]
- +
Location Delay Type @@ -123415,10 +127659,10 @@ Logical Resource - Clock clk_20k (rising edge) + Clock clk_50m (rising edge) - 50000.000 - 50000.000 + 0.000 + 0.000 r @@ -123426,7 +127670,7 @@ P200.000 - 50000.000 + 0.000rclk (port) @@ -123434,15 +127678,15 @@ net (fanout=1) 0.074 - 50000.074 + 0.074 clk IOBS_LR_328_209/DIN td - 1.285 - 50001.359 + 1.504 + 1.578 r clk_ibuf/opit_0/O @@ -123450,119 +127694,87 @@ net (fanout=1) 0.000 - 50001.359 + 1.578 clk_ibuf/ntD IOL_327_210/INCK td - 0.038 - 50001.397 + 0.058 + 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) - 0.463 - 50001.860 + 0.478 + 2.114 _N69 - PLL_158_55/CLK_OUT3 + PLL_158_55/CLK_OUT0 td 0.083 - 50001.943 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT3 - - - - net (fanout=1) - 0.603 - 50002.546 - - clk_25m - - - USCM_84_114/CLK_USCM - td - 0.000 - 50002.546 - r - clkbufg_7/gopclkbufg/CLKOUT - - - - net (fanout=26) - 0.895 - 50003.441 - - ntclkbufg_7 - - - CLMA_182_25/Q1 - tco - 0.184 - 50003.625 + 2.197 r - u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q + u_sys_pll/u_pll_e3/goppll/CLKOUT0 - net (fanout=3) - 1.124 - 50004.749 + net (fanout=2) + 0.614 + 2.811 - u_ov5640/coms2_reg_config/clk_20k_regdiv + rd3_clk - USCM_84_120/CLK_USCM + USCM_84_108/CLK_USCM td 0.000 - 50004.749 + 2.811 r - u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + clkbufg_1/gopclkbufg/CLKOUT - net (fanout=19) - 0.895 - 50005.644 + net (fanout=2516) + 0.925 + 3.736 - u_ov5640/coms2_reg_config/clock_20k + ntclkbufg_1 - CLMS_174_25/CLK + DRM_54_108/CLKA[0] r - u_ov5640/coms2_reg_config/u1/reg_sdat/opit_0_inv_MUX4TO1Q/CLK + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKA clock pessimism - 0.446 - 50006.090 + -0.281 + 3.455 clock uncertainty - -0.050 - 50006.040 + 0.000 + 3.455 - Setup time + Hold time - -0.148 - 50005.892 + 0.166 + 3.621 @@ -123570,49 +127782,28 @@ -
- - - Slack - Logic Levels - High Fanout - Start Point - End Point - Exception - Launch Clock - Capture Clock - Clock Edges - Clock Skew - Launch Clock Delay - Capture Clock Delay - Clock Pessimism Removal - Requirement - Data delay - Logic delay - Route delay - - 0.106 + 0.160 0 - 5 - u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[2]/opit_0_L5Q_perm/CLK - u_ddr_addr_ctr/u_wr1_addr_ctr/wr_vs_flag/opit_0_L5Q_perm/L0 + 3 + u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK + u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[7] - hdmi_in_clk - hdmi_in_clk + clk_1080p60Hz + clk_1080p60Hz rise-rise - 0.001 - 3.724 - 4.020 - -0.295 + 0.019 + 5.520 + 5.882 + -0.343 0.000 - 0.242 - 0.180 (74.4%) - 0.062 (25.6%) + 0.345 + 0.183 (53.0%) + 0.162 (47.0%) - Path #1: hold slack is 0.106(MET) + Path #12: hold slack is 0.160(MET) -
+
Location Delay Type @@ -123622,7 +127813,7 @@ Logical Resource - Clock hdmi_in_clk (rising edge) + Clock clk_1080p60Hz (rising edge) 0.000 0.000 @@ -123630,105 +127821,153 @@ - AA12 + P20 0.000 0.000 r - hdmi_in_clk (port) + clk (port) net (fanout=1) - 0.078 - 0.078 + 0.074 + 0.074 - hdmi_in_clk + clk - IOBD_161_0/DIN + IOBS_LR_328_209/DIN td 1.285 - 1.363 + 1.359 r - hdmi_in_clk_ibuf/opit_0/O + clk_ibuf/opit_0/O net (fanout=1) 0.000 - 1.363 + 1.359 - hdmi_in_clk_ibuf/ntD + clk_ibuf/ntD - IOL_163_6/INCK + IOL_327_210/INCK td 0.038 - 1.401 + 1.397 r - hdmi_in_clk_ibuf/opit_1/INCK + clk_ibuf/opit_1/INCK net (fanout=1) - 1.428 - 2.829 + 0.463 + 1.860 - _N37 + _N69 - USCM_84_111/CLK_USCM + PLL_158_55/CLK_OUT0 + td + 0.078 + 1.938 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 0.603 + 2.541 + + rd3_clk + + + USCM_84_154/CLK_USCM td 0.000 - 2.829 + 2.541 r - clkbufg_4/gopclkbufg/CLKOUT + USCMROUTE_0/CLKOUT - net (fanout=167) + net (fanout=1) + 1.091 + 3.632 + + ntR3950 + + + PLL_158_303/CLK_OUT0 + td + 0.078 + 3.710 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=1) + 0.915 + 4.625 + + zoom_clk + + + USCM_84_118/CLK_USCM + td + 0.000 + 4.625 + r + clkbufg_3/gopclkbufg/CLKOUT + + + + net (fanout=750) 0.895 - 3.724 + 5.520 - ntclkbufg_4 + ntclkbufg_3 - CLMA_110_85/CLK + CLMA_146_76/CLK r - u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[2]/opit_0_L5Q_perm/CLK + u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/CLK - CLMA_110_85/Q2 + CLMA_146_76/Q2 tco - 0.180 - 3.904 - f - u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg[2]/opit_0_L5Q_perm/Q + 0.183 + 5.703 + r + u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/opit_0_inv_A2Q21/Q0 - net (fanout=5) - 0.062 - 3.966 + net (fanout=3) + 0.162 + 5.865 - u_ddr_addr_ctr/u_wr1_addr_ctr/wr_sta_reg [2] + u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/wr_addr [2] - CLMA_110_85/D0 + DRM_142_68/ADA0[7] - f - u_ddr_addr_ctr/u_wr1_addr_ctr/wr_vs_flag/opit_0_L5Q_perm/L0 + r + u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[7]
- +
Location Delay Type @@ -123738,7 +127977,7 @@ Logical Resource - Clock hdmi_in_clk (rising edge) + Clock clk_1080p60Hz (rising edge) 0.000 0.000 @@ -123746,98 +127985,146 @@ - AA12 + P20 0.000 0.000 r - hdmi_in_clk (port) + clk (port) net (fanout=1) - 0.078 - 0.078 + 0.074 + 0.074 - hdmi_in_clk + clk - IOBD_161_0/DIN + IOBS_LR_328_209/DIN td 1.504 - 1.582 + 1.578 r - hdmi_in_clk_ibuf/opit_0/O + clk_ibuf/opit_0/O net (fanout=1) 0.000 - 1.582 + 1.578 - hdmi_in_clk_ibuf/ntD + clk_ibuf/ntD - IOL_163_6/INCK + IOL_327_210/INCK td 0.058 - 1.640 + 1.636 r - hdmi_in_clk_ibuf/opit_1/INCK + clk_ibuf/opit_1/INCK net (fanout=1) - 1.455 - 3.095 + 0.478 + 2.114 - _N37 + _N69 - USCM_84_111/CLK_USCM + PLL_158_55/CLK_OUT0 + td + 0.083 + 2.197 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 0.614 + 2.811 + + rd3_clk + + + USCM_84_154/CLK_USCM td 0.000 - 3.095 + 2.811 r - clkbufg_4/gopclkbufg/CLKOUT + USCMROUTE_0/CLKOUT - net (fanout=167) + net (fanout=1) + 1.131 + 3.942 + + ntR3950 + + + PLL_158_303/CLK_OUT0 + td + 0.083 + 4.025 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=1) + 0.932 + 4.957 + + zoom_clk + + + USCM_84_118/CLK_USCM + td + 0.000 + 4.957 + r + clkbufg_3/gopclkbufg/CLKOUT + + + + net (fanout=750) 0.925 - 4.020 + 5.882 - ntclkbufg_4 + ntclkbufg_3 - CLMA_110_85/CLK + DRM_142_68/CLKA[0] r - u_ddr_addr_ctr/u_wr1_addr_ctr/wr_vs_flag/opit_0_L5Q_perm/CLK + u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKA clock pessimism - -0.295 - 3.725 + -0.343 + 5.539 clock uncertainty - 0.200 - 3.925 + 0.000 + 5.539 Hold time - -0.065 - 3.860 + 0.166 + 5.705 @@ -123846,27 +128133,27 @@ - 0.108 + 0.173 0 - 1 - u_ov5640/cmos1_8_16bit/image_data0[5]/opit_0/CLK - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/DA0[5] + 4 + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[2] - cmos1_pclk - cmos1_pclk + clk_50m + clk_50m rise-rise - 0.019 - 3.172 - 3.375 - -0.184 + 0.008 + 3.471 + 3.760 + -0.281 0.000 - 0.446 - 0.180 (40.4%) - 0.266 (59.6%) + 0.325 + 0.182 (56.0%) + 0.143 (44.0%) - Path #2: hold slack is 0.108(MET) + Path #13: hold slack is 0.173(MET) -
+
Location Delay Type @@ -123876,7 +128163,7 @@ Logical Resource - Clock cmos1_pclk (rising edge) + Clock clk_50m (rising edge) 0.000 0.000 @@ -123884,105 +128171,121 @@ - T12 + P20 0.000 0.000 r - cmos1_pclk (port) + clk (port) net (fanout=1) - 0.076 - 0.076 + 0.074 + 0.074 - cmos1_pclk + clk - IOBD_169_0/DIN + IOBS_LR_328_209/DIN td - 0.735 - 0.811 + 1.285 + 1.359 r - cmos1_pclk_ibuf/opit_0/O + clk_ibuf/opit_0/O net (fanout=1) 0.000 - 0.811 + 1.359 - cmos1_pclk_ibuf/ntD + clk_ibuf/ntD - IOL_171_6/INCK + IOL_327_210/INCK td 0.038 - 0.849 + 1.397 r - cmos1_pclk_ibuf/opit_1/INCK + clk_ibuf/opit_1/INCK net (fanout=1) - 1.428 - 2.277 + 0.463 + 1.860 - _N64 + _N69 - USCM_84_112/CLK_USCM + PLL_158_55/CLK_OUT0 + td + 0.078 + 1.938 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 0.603 + 2.541 + + rd3_clk + + + USCM_84_108/CLK_USCM td 0.000 - 2.277 + 2.541 r - clkbufg_5/gopclkbufg/CLKOUT + clkbufg_1/gopclkbufg/CLKOUT - net (fanout=118) - 0.895 - 3.172 + net (fanout=2516) + 0.930 + 3.471 - ntclkbufg_5 + ntclkbufg_1 - CLMS_146_33/CLK + CLMA_50_32/CLK r - u_ov5640/cmos1_8_16bit/image_data0[5]/opit_0/CLK + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK - CLMS_146_33/Q2 + CLMA_50_32/Q0 tco - 0.180 - 3.352 - f - u_ov5640/cmos1_8_16bit/image_data0[5]/opit_0/Q + 0.182 + 3.653 + r + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Q0 - net (fanout=1) - 0.266 - 3.618 + net (fanout=4) + 0.143 + 3.796 - u_ov5640/cmos1_d_16bit [5] + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/wr_addr [0] - DRM_142_24/DA0[5] + DRM_54_24/ADA0[2] - f - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/DA0[5] + r + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[2]
- +
Location Delay Type @@ -123992,7 +128295,7 @@ Logical Resource - Clock cmos1_pclk (rising edge) + Clock clk_50m (rising edge) 0.000 0.000 @@ -124000,98 +128303,114 @@ - T12 + P20 0.000 0.000 r - cmos1_pclk (port) + clk (port) net (fanout=1) - 0.076 - 0.076 + 0.074 + 0.074 - cmos1_pclk + clk - IOBD_169_0/DIN + IOBS_LR_328_209/DIN td - 0.861 - 0.937 + 1.504 + 1.578 r - cmos1_pclk_ibuf/opit_0/O + clk_ibuf/opit_0/O net (fanout=1) 0.000 - 0.937 + 1.578 - cmos1_pclk_ibuf/ntD + clk_ibuf/ntD - IOL_171_6/INCK + IOL_327_210/INCK td 0.058 - 0.995 + 1.636 r - cmos1_pclk_ibuf/opit_1/INCK + clk_ibuf/opit_1/INCK net (fanout=1) - 1.455 - 2.450 + 0.478 + 2.114 - _N64 + _N69 - USCM_84_112/CLK_USCM + PLL_158_55/CLK_OUT0 + td + 0.083 + 2.197 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 0.614 + 2.811 + + rd3_clk + + + USCM_84_108/CLK_USCM td 0.000 - 2.450 + 2.811 r - clkbufg_5/gopclkbufg/CLKOUT + clkbufg_1/gopclkbufg/CLKOUT - net (fanout=118) - 0.925 - 3.375 + net (fanout=2516) + 0.949 + 3.760 - ntclkbufg_5 + ntclkbufg_1 - DRM_142_24/CLKA[0] + DRM_54_24/CLKA[0] r - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKA clock pessimism - -0.184 - 3.191 + -0.281 + 3.479 clock uncertainty - 0.200 - 3.391 + 0.000 + 3.479 Hold time - 0.119 - 3.510 + 0.144 + 3.623 @@ -124100,27 +128419,27 @@ - 0.110 + 0.180 0 - 1 - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/opit_0/CLK - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/D + 4 + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/ADA0[4] - cmos1_pclk - cmos1_pclk + clk_50m + clk_50m rise-rise 0.019 - 3.172 - 3.375 - -0.184 + 3.546 + 3.848 + -0.283 0.000 - 0.318 - 0.182 (57.2%) - 0.136 (42.8%) + 0.326 + 0.184 (56.4%) + 0.142 (43.6%) - Path #3: hold slack is 0.110(MET) + Path #14: hold slack is 0.180(MET) -
+
Location Delay Type @@ -124130,7 +128449,7 @@ Logical Resource - Clock cmos1_pclk (rising edge) + Clock clk_50m (rising edge) 0.000 0.000 @@ -124138,105 +128457,121 @@ - T12 + P20 0.000 0.000 r - cmos1_pclk (port) + clk (port) net (fanout=1) - 0.076 - 0.076 + 0.074 + 0.074 - cmos1_pclk + clk - IOBD_169_0/DIN + IOBS_LR_328_209/DIN td - 0.735 - 0.811 + 1.285 + 1.359 r - cmos1_pclk_ibuf/opit_0/O + clk_ibuf/opit_0/O net (fanout=1) 0.000 - 0.811 + 1.359 - cmos1_pclk_ibuf/ntD + clk_ibuf/ntD - IOL_171_6/INCK + IOL_327_210/INCK td 0.038 - 0.849 + 1.397 r - cmos1_pclk_ibuf/opit_1/INCK + clk_ibuf/opit_1/INCK net (fanout=1) - 1.428 - 2.277 + 0.463 + 1.860 - _N64 + _N69 - USCM_84_112/CLK_USCM + PLL_158_55/CLK_OUT0 + td + 0.078 + 1.938 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 0.603 + 2.541 + + rd3_clk + + + USCM_84_108/CLK_USCM td 0.000 - 2.277 + 2.541 r - clkbufg_5/gopclkbufg/CLKOUT + clkbufg_1/gopclkbufg/CLKOUT - net (fanout=118) - 0.895 - 3.172 + net (fanout=2516) + 1.005 + 3.546 - ntclkbufg_5 + ntclkbufg_1 - CLMA_138_24/CLK + CLMS_78_305/CLK r - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/opit_0/CLK + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/CLK - CLMA_138_24/Q0 + CLMS_78_305/Q1 tco - 0.182 - 3.354 + 0.184 + 3.730 r - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/opit_0/Q + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/opit_0_inv_A2Q21/Q1 - net (fanout=1) - 0.136 - 3.490 + net (fanout=4) + 0.142 + 3.872 - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr1 [1] + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/wr_addr [1] - CLMA_134_28/M2 + DRM_82_292/ADA0[4] r - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/D + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/ADA0[4]
- +
Location Delay Type @@ -124246,7 +128581,7 @@ Logical Resource - Clock cmos1_pclk (rising edge) + Clock clk_50m (rising edge) 0.000 0.000 @@ -124254,98 +128589,114 @@ - T12 + P20 0.000 0.000 r - cmos1_pclk (port) + clk (port) net (fanout=1) - 0.076 - 0.076 + 0.074 + 0.074 - cmos1_pclk + clk - IOBD_169_0/DIN + IOBS_LR_328_209/DIN td - 0.861 - 0.937 + 1.504 + 1.578 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.578 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.058 + 1.636 r - cmos1_pclk_ibuf/opit_0/O + clk_ibuf/opit_1/INCK net (fanout=1) - 0.000 - 0.937 + 0.478 + 2.114 - cmos1_pclk_ibuf/ntD + _N69 - IOL_171_6/INCK + PLL_158_55/CLK_OUT0 td - 0.058 - 0.995 + 0.083 + 2.197 r - cmos1_pclk_ibuf/opit_1/INCK + u_sys_pll/u_pll_e3/goppll/CLKOUT0 - net (fanout=1) - 1.455 - 2.450 + net (fanout=2) + 0.614 + 2.811 - _N64 + rd3_clk - USCM_84_112/CLK_USCM + USCM_84_108/CLK_USCM td 0.000 - 2.450 + 2.811 r - clkbufg_5/gopclkbufg/CLKOUT + clkbufg_1/gopclkbufg/CLKOUT - net (fanout=118) - 0.925 - 3.375 + net (fanout=2516) + 1.037 + 3.848 - ntclkbufg_5 + ntclkbufg_1 - CLMA_134_28/CLK + DRM_82_292/CLKA[0] r - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[1]/opit_0/CLK + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] clock pessimism - -0.184 - 3.191 + -0.283 + 3.565 clock uncertainty - 0.200 - 3.391 + 0.000 + 3.565 Hold time - -0.011 - 3.380 + 0.127 + 3.692 @@ -124354,27 +128705,27 @@ - 0.111 + 0.182 0 - 2 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[22]/opit_0_inv/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_27/ram16x1d/WD + 6 + u_zoom_image/wr_addr1[2]/opit_0_inv_A2Q21/CLK + u_zoom_image/zoom_ram1_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/ADA0[5] - ddrphy_clkin - ddrphy_clkin + clk_1080p60Hz + clk_1080p60Hz rise-rise - 0.030 - 6.654 - 7.101 - -0.417 + 0.019 + 5.520 + 5.882 + -0.343 0.000 - 0.434 - 0.179 (41.2%) - 0.255 (58.8%) + 0.328 + 0.184 (56.1%) + 0.144 (43.9%) - Path #4: hold slack is 0.111(MET) + Path #15: hold slack is 0.182(MET) -
+
Location Delay Type @@ -124384,7 +128735,7 @@ Logical Resource - Clock ddrphy_clkin (rising edge) + Clock clk_1080p60Hz (rising edge) 0.000 0.000 @@ -124440,137 +128791,105 @@ _N69 - PLL_158_55/CLK_OUT1 + PLL_158_55/CLK_OUT0 td - 0.074 - 1.934 + 0.078 + 1.938 r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 + u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 0.603 - 2.537 + 2.541 - zoom_clk + rd3_clk - USCM_84_113/CLK_USCM + USCM_84_154/CLK_USCM td 0.000 - 2.537 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 0.981 - 3.518 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.089 - 3.607 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 0.669 - 4.276 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.200 - 4.476 + 2.541 r - clkgate_8/gopclkgate/OUT + USCMROUTE_0/CLKOUT net (fanout=1) - 0.000 - 4.476 + 1.091 + 3.632 - ntclkgate_0 + ntR3950 - IOCKDIV_6_323/CLK_IODIV + PLL_158_303/CLK_OUT0 td - 0.000 - 4.476 + 0.078 + 3.710 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 net (fanout=1) - 1.283 - 5.759 + 0.915 + 4.625 - u_axi_ddr_top/clk + zoom_clk - USCM_84_116/CLK_USCM + USCM_84_118/CLK_USCM td 0.000 - 5.759 + 4.625 r - clkbufg_0/gopclkbufg/CLKOUT + clkbufg_3/gopclkbufg/CLKOUT - net (fanout=5464) + net (fanout=750) 0.895 - 6.654 + 5.520 - ntclkbufg_0 + ntclkbufg_3 - CLMA_58_124/CLK + CLMS_174_177/CLK r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[22]/opit_0_inv/CLK + u_zoom_image/wr_addr1[2]/opit_0_inv_A2Q21/CLK - CLMA_58_124/Q0 + CLMS_174_177/Q1 tco - 0.179 - 6.833 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[22]/opit_0_inv/Q + 0.184 + 5.704 + r + u_zoom_image/wr_addr1[2]/opit_0_inv_A2Q21/Q1 - net (fanout=2) - 0.255 - 7.088 + net (fanout=6) + 0.144 + 5.848 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/dcd_wr_addr [22] + u_zoom_image/wr_addr1 [2] - CLMS_50_129/DD + DRM_178_168/ADA0[5] - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_27/ram16x1d/WD + r + u_zoom_image/zoom_ram1_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/ADA0[5]
- +
Location Delay Type @@ -124580,7 +128899,7 @@ Logical Resource - Clock ddrphy_clkin (rising edge) + Clock clk_1080p60Hz (rising edge) 0.000 0.000 @@ -124636,114 +128955,82 @@ _N69 - PLL_158_55/CLK_OUT1 + PLL_158_55/CLK_OUT0 td - 0.079 - 2.193 + 0.083 + 2.197 r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 + u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 0.614 - 2.807 + 2.811 - zoom_clk + rd3_clk - USCM_84_113/CLK_USCM + USCM_84_154/CLK_USCM td 0.000 - 2.807 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.019 - 3.826 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.094 - 3.920 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 0.682 - 4.602 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.268 - 4.870 + 2.811 r - clkgate_8/gopclkgate/OUT + USCMROUTE_0/CLKOUT net (fanout=1) - 0.000 - 4.870 + 1.131 + 3.942 - ntclkgate_0 + ntR3950 - IOCKDIV_6_323/CLK_IODIV + PLL_158_303/CLK_OUT0 td - 0.000 - 4.870 + 0.083 + 4.025 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 net (fanout=1) - 1.306 - 6.176 + 0.932 + 4.957 - u_axi_ddr_top/clk + zoom_clk - USCM_84_116/CLK_USCM + USCM_84_118/CLK_USCM td 0.000 - 6.176 + 4.957 r - clkbufg_0/gopclkbufg/CLKOUT + clkbufg_3/gopclkbufg/CLKOUT - net (fanout=5464) + net (fanout=750) 0.925 - 7.101 + 5.882 - ntclkbufg_0 + ntclkbufg_3 - CLMS_50_129/CLK + DRM_178_168/CLKA[0] r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_27/ram16x1d/WCLK + u_zoom_image/zoom_ram1_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] clock pessimism - -0.417 - 6.684 + -0.343 + 5.539 @@ -124751,15 +129038,15 @@ clock uncertainty 0.000 - 6.684 + 5.539 Hold time - 0.293 - 6.977 + 0.127 + 5.666 @@ -124768,27 +129055,27 @@ - 0.111 + 0.195 0 1 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/D + u_zoom_image/image_valid[2][1]/opit_0/CLK + u_zoom_image/image_valid[3][1]/opit_0/D - hdmi_in_clk - hdmi_in_clk + clk_1080p60Hz + clk_1080p60Hz rise-rise - 0.019 - 3.724 - 4.020 - -0.277 + 0.001 + 5.520 + 5.882 + -0.361 0.000 - 0.319 - 0.182 (57.1%) - 0.137 (42.9%) + 0.236 + 0.178 (75.4%) + 0.058 (24.6%) - Path #5: hold slack is 0.111(MET) + Path #16: hold slack is 0.195(MET) -
+
Location Delay Type @@ -124798,7 +129085,7 @@ Logical Resource - Clock hdmi_in_clk (rising edge) + Clock clk_1080p60Hz (rising edge) 0.000 0.000 @@ -124806,105 +129093,153 @@ - AA12 + P20 0.000 0.000 r - hdmi_in_clk (port) + clk (port) net (fanout=1) - 0.078 - 0.078 + 0.074 + 0.074 - hdmi_in_clk + clk - IOBD_161_0/DIN + IOBS_LR_328_209/DIN td 1.285 - 1.363 + 1.359 r - hdmi_in_clk_ibuf/opit_0/O + clk_ibuf/opit_0/O net (fanout=1) 0.000 - 1.363 + 1.359 - hdmi_in_clk_ibuf/ntD + clk_ibuf/ntD - IOL_163_6/INCK + IOL_327_210/INCK td 0.038 - 1.401 + 1.397 r - hdmi_in_clk_ibuf/opit_1/INCK + clk_ibuf/opit_1/INCK net (fanout=1) - 1.428 - 2.829 + 0.463 + 1.860 - _N37 + _N69 - USCM_84_111/CLK_USCM + PLL_158_55/CLK_OUT0 + td + 0.078 + 1.938 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 0.603 + 2.541 + + rd3_clk + + + USCM_84_154/CLK_USCM td 0.000 - 2.829 + 2.541 r - clkbufg_4/gopclkbufg/CLKOUT + USCMROUTE_0/CLKOUT - net (fanout=167) + net (fanout=1) + 1.091 + 3.632 + + ntR3950 + + + PLL_158_303/CLK_OUT0 + td + 0.078 + 3.710 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=1) + 0.915 + 4.625 + + zoom_clk + + + USCM_84_118/CLK_USCM + td + 0.000 + 4.625 + r + clkbufg_3/gopclkbufg/CLKOUT + + + + net (fanout=750) 0.895 - 3.724 + 5.520 - ntclkbufg_4 + ntclkbufg_3 - CLMA_66_104/CLK + CLMA_210_153/CLK r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/CLK + u_zoom_image/image_valid[2][1]/opit_0/CLK - CLMA_66_104/Q0 + CLMA_210_153/Q3 tco - 0.182 - 3.906 - r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/opit_0/Q + 0.178 + 5.698 + f + u_zoom_image/image_valid[2][1]/opit_0/Q net (fanout=1) - 0.137 - 4.043 + 0.058 + 5.756 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr1 [3] + u_zoom_image/image_valid[2] [1] - CLMS_62_101/M2 + CLMA_210_153/AD - r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/D + f + u_zoom_image/image_valid[3][1]/opit_0/D
- +
Location Delay Type @@ -124914,7 +129249,7 @@ Logical Resource - Clock hdmi_in_clk (rising edge) + Clock clk_1080p60Hz (rising edge) 0.000 0.000 @@ -124922,98 +129257,146 @@ - AA12 + P20 0.000 0.000 r - hdmi_in_clk (port) + clk (port) net (fanout=1) - 0.078 - 0.078 + 0.074 + 0.074 - hdmi_in_clk + clk - IOBD_161_0/DIN + IOBS_LR_328_209/DIN td 1.504 - 1.582 + 1.578 r - hdmi_in_clk_ibuf/opit_0/O + clk_ibuf/opit_0/O net (fanout=1) 0.000 - 1.582 + 1.578 - hdmi_in_clk_ibuf/ntD + clk_ibuf/ntD - IOL_163_6/INCK + IOL_327_210/INCK td 0.058 - 1.640 + 1.636 r - hdmi_in_clk_ibuf/opit_1/INCK + clk_ibuf/opit_1/INCK net (fanout=1) - 1.455 - 3.095 + 0.478 + 2.114 - _N37 + _N69 - USCM_84_111/CLK_USCM + PLL_158_55/CLK_OUT0 + td + 0.083 + 2.197 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=2) + 0.614 + 2.811 + + rd3_clk + + + USCM_84_154/CLK_USCM td 0.000 - 3.095 + 2.811 r - clkbufg_4/gopclkbufg/CLKOUT + USCMROUTE_0/CLKOUT - net (fanout=167) + net (fanout=1) + 1.131 + 3.942 + + ntR3950 + + + PLL_158_303/CLK_OUT0 + td + 0.083 + 4.025 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 + + + + net (fanout=1) + 0.932 + 4.957 + + zoom_clk + + + USCM_84_118/CLK_USCM + td + 0.000 + 4.957 + r + clkbufg_3/gopclkbufg/CLKOUT + + + + net (fanout=750) 0.925 - 4.020 + 5.882 - ntclkbufg_4 + ntclkbufg_3 - CLMS_62_101/CLK + CLMA_210_153/CLK r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[3]/opit_0/CLK + u_zoom_image/image_valid[3][1]/opit_0/CLK clock pessimism - -0.277 - 3.743 + -0.361 + 5.521 clock uncertainty - 0.200 - 3.943 + 0.000 + 5.521 Hold time - -0.011 - 3.932 + 0.040 + 5.561 @@ -125022,27 +129405,27 @@ - 0.111 + 0.232 0 - 1 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/D + 2 + ms72xx_ctl/iic_dri_tx/receiv_data[5]/opit_0_inv/CLK + ms72xx_ctl/iic_dri_tx/data_out[5]/opit_0/D - hdmi_in_clk - hdmi_in_clk + clk_10m + clk_10m rise-rise - 0.019 - 3.724 - 4.020 - -0.277 + 0.015 + 3.547 + 3.849 + -0.287 0.000 - 0.319 - 0.182 (57.1%) - 0.137 (42.9%) + 0.287 + 0.228 (79.4%) + 0.059 (20.6%) - Path #6: hold slack is 0.111(MET) + Path #17: hold slack is 0.232(MET) -
+
Location Delay Type @@ -125052,7 +129435,7 @@ Logical Resource - Clock hdmi_in_clk (rising edge) + Clock clk_10m (rising edge) 0.000 0.000 @@ -125060,105 +129443,121 @@ - AA12 + P20 0.000 0.000 r - hdmi_in_clk (port) + clk (port) net (fanout=1) - 0.078 - 0.078 + 0.074 + 0.074 - hdmi_in_clk + clk - IOBD_161_0/DIN + IOBS_LR_328_209/DIN td 1.285 - 1.363 + 1.359 r - hdmi_in_clk_ibuf/opit_0/O + clk_ibuf/opit_0/O net (fanout=1) 0.000 - 1.363 + 1.359 - hdmi_in_clk_ibuf/ntD + clk_ibuf/ntD - IOL_163_6/INCK + IOL_327_210/INCK td 0.038 - 1.401 + 1.397 r - hdmi_in_clk_ibuf/opit_1/INCK + clk_ibuf/opit_1/INCK net (fanout=1) - 1.428 - 2.829 + 0.463 + 1.860 - _N37 + _N69 - USCM_84_111/CLK_USCM + PLL_158_55/CLK_OUT4 + td + 0.079 + 1.939 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT4 + + + + net (fanout=1) + 0.603 + 2.542 + + clk_10m + + + USCM_84_110/CLK_USCM td 0.000 - 2.829 + 2.542 r - clkbufg_4/gopclkbufg/CLKOUT + clkbufg_4/gopclkbufg/CLKOUT - net (fanout=167) - 0.895 - 3.724 + net (fanout=235) + 1.005 + 3.547 ntclkbufg_4 - CLMA_62_104/CLK + CLMA_194_305/CLK r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/CLK + ms72xx_ctl/iic_dri_tx/receiv_data[5]/opit_0_inv/CLK - CLMA_62_104/Q0 + CLMA_194_305/Y2 tco - 0.182 - 3.906 - r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/opit_0/Q + 0.228 + 3.775 + f + ms72xx_ctl/iic_dri_tx/receiv_data[5]/opit_0_inv/Q - net (fanout=1) - 0.137 - 4.043 + net (fanout=2) + 0.059 + 3.834 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr1 [7] + ms72xx_ctl/iic_dri_tx/receiv_data [5] - CLMA_66_100/M0 + CLMA_194_304/CD - r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/D + f + ms72xx_ctl/iic_dri_tx/data_out[5]/opit_0/D
- +
Location Delay Type @@ -125168,7 +129567,7 @@ Logical Resource - Clock hdmi_in_clk (rising edge) + Clock clk_10m (rising edge) 0.000 0.000 @@ -125176,98 +129575,114 @@ - AA12 + P20 0.000 0.000 r - hdmi_in_clk (port) + clk (port) net (fanout=1) - 0.078 - 0.078 + 0.074 + 0.074 - hdmi_in_clk + clk - IOBD_161_0/DIN + IOBS_LR_328_209/DIN + td + 1.504 + 1.578 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.578 + + clk_ibuf/ntD + + + IOL_327_210/INCK td - 1.504 - 1.582 + 0.058 + 1.636 r - hdmi_in_clk_ibuf/opit_0/O + clk_ibuf/opit_1/INCK net (fanout=1) - 0.000 - 1.582 + 0.478 + 2.114 - hdmi_in_clk_ibuf/ntD + _N69 - IOL_163_6/INCK + PLL_158_55/CLK_OUT4 td - 0.058 - 1.640 + 0.084 + 2.198 r - hdmi_in_clk_ibuf/opit_1/INCK + u_sys_pll/u_pll_e3/goppll/CLKOUT4 net (fanout=1) - 1.455 - 3.095 + 0.614 + 2.812 - _N37 + clk_10m - USCM_84_111/CLK_USCM + USCM_84_110/CLK_USCM td 0.000 - 3.095 + 2.812 r - clkbufg_4/gopclkbufg/CLKOUT + clkbufg_4/gopclkbufg/CLKOUT - net (fanout=167) - 0.925 - 4.020 + net (fanout=235) + 1.037 + 3.849 ntclkbufg_4 - CLMA_66_100/CLK + CLMA_194_304/CLK r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[7]/opit_0/CLK + ms72xx_ctl/iic_dri_tx/data_out[5]/opit_0/CLK clock pessimism - -0.277 - 3.743 + -0.287 + 3.562 clock uncertainty - 0.200 - 3.943 + 0.000 + 3.562 Hold time - -0.011 - 3.932 + 0.040 + 3.602 @@ -125276,27 +129691,27 @@ - 0.111 + 0.235 0 - 1 - u_ov5640/cmos1_8_16bit/pdata_i2[0]/opit_0/CLK - u_ov5640/cmos1_8_16bit/image_data0[8]/opit_0/D + 3 + ms72xx_ctl/ms7200_ctl/cmd_index[5]/opit_0_inv_A2Q21/CLK + ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/ADA0[10] - cmos1_pclk - cmos1_pclk + clk_10m + clk_10m rise-rise - 0.015 - 3.172 - 3.375 - -0.188 + 0.019 + 3.547 + 3.849 + -0.283 0.000 - 0.315 - 0.182 (57.8%) - 0.133 (42.2%) + 0.381 + 0.184 (48.3%) + 0.197 (51.7%) - Path #7: hold slack is 0.111(MET) + Path #18: hold slack is 0.235(MET) -
+
Location Delay Type @@ -125306,7 +129721,7 @@ Logical Resource - Clock cmos1_pclk (rising edge) + Clock clk_10m (rising edge) 0.000 0.000 @@ -125314,105 +129729,121 @@ - T12 + P20 0.000 0.000 r - cmos1_pclk (port) + clk (port) net (fanout=1) - 0.076 - 0.076 + 0.074 + 0.074 - cmos1_pclk + clk - IOBD_169_0/DIN + IOBS_LR_328_209/DIN td - 0.735 - 0.811 + 1.285 + 1.359 r - cmos1_pclk_ibuf/opit_0/O + clk_ibuf/opit_0/O net (fanout=1) 0.000 - 0.811 + 1.359 - cmos1_pclk_ibuf/ntD + clk_ibuf/ntD - IOL_171_6/INCK + IOL_327_210/INCK td 0.038 - 0.849 + 1.397 r - cmos1_pclk_ibuf/opit_1/INCK + clk_ibuf/opit_1/INCK net (fanout=1) - 1.428 - 2.277 + 0.463 + 1.860 - _N64 + _N69 - USCM_84_112/CLK_USCM + PLL_158_55/CLK_OUT4 + td + 0.079 + 1.939 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT4 + + + + net (fanout=1) + 0.603 + 2.542 + + clk_10m + + + USCM_84_110/CLK_USCM td 0.000 - 2.277 + 2.542 r - clkbufg_5/gopclkbufg/CLKOUT + clkbufg_4/gopclkbufg/CLKOUT - net (fanout=118) - 0.895 - 3.172 + net (fanout=235) + 1.005 + 3.547 - ntclkbufg_5 + ntclkbufg_4 - CLMA_138_25/CLK + CLMA_230_325/CLK r - u_ov5640/cmos1_8_16bit/pdata_i2[0]/opit_0/CLK + ms72xx_ctl/ms7200_ctl/cmd_index[5]/opit_0_inv_A2Q21/CLK - CLMA_138_25/Q3 + CLMA_230_325/Q1 tco - 0.182 - 3.354 + 0.184 + 3.731 r - u_ov5640/cmos1_8_16bit/pdata_i2[0]/opit_0/Q + ms72xx_ctl/ms7200_ctl/cmd_index[5]/opit_0_inv_A2Q21/Q1 - net (fanout=1) - 0.133 - 3.487 + net (fanout=3) + 0.197 + 3.928 - u_ov5640/cmos1_8_16bit/pdata_i2 [0] + ms72xx_ctl/ms7200_ctl/cmd_index [5] - CLMA_138_29/M1 + DRM_234_316/ADA0[10] r - u_ov5640/cmos1_8_16bit/image_data0[8]/opit_0/D + ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/ADA0[10]
- +
Location Delay Type @@ -125422,7 +129853,7 @@ Logical Resource - Clock cmos1_pclk (rising edge) + Clock clk_10m (rising edge) 0.000 0.000 @@ -125430,98 +129861,114 @@ - T12 + P20 0.000 0.000 r - cmos1_pclk (port) + clk (port) net (fanout=1) - 0.076 - 0.076 + 0.074 + 0.074 - cmos1_pclk + clk - IOBD_169_0/DIN + IOBS_LR_328_209/DIN td - 0.861 - 0.937 + 1.504 + 1.578 r - cmos1_pclk_ibuf/opit_0/O + clk_ibuf/opit_0/O net (fanout=1) 0.000 - 0.937 + 1.578 - cmos1_pclk_ibuf/ntD + clk_ibuf/ntD - IOL_171_6/INCK + IOL_327_210/INCK td 0.058 - 0.995 + 1.636 r - cmos1_pclk_ibuf/opit_1/INCK + clk_ibuf/opit_1/INCK net (fanout=1) - 1.455 - 2.450 + 0.478 + 2.114 - _N64 + _N69 - USCM_84_112/CLK_USCM + PLL_158_55/CLK_OUT4 + td + 0.084 + 2.198 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT4 + + + + net (fanout=1) + 0.614 + 2.812 + + clk_10m + + + USCM_84_110/CLK_USCM td 0.000 - 2.450 + 2.812 r - clkbufg_5/gopclkbufg/CLKOUT + clkbufg_4/gopclkbufg/CLKOUT - net (fanout=118) - 0.925 - 3.375 + net (fanout=235) + 1.037 + 3.849 - ntclkbufg_5 + ntclkbufg_4 - CLMA_138_29/CLK + DRM_234_316/CLKA[0] r - u_ov5640/cmos1_8_16bit/image_data0[8]/opit_0/CLK + ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKA[0] clock pessimism - -0.188 - 3.187 + -0.283 + 3.566 clock uncertainty - 0.200 - 3.387 + 0.000 + 3.566 Hold time - -0.011 - 3.376 + 0.127 + 3.693 @@ -125530,27 +129977,27 @@ - 0.118 + 0.235 0 - 7 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_0/ram32x1dp/WADM0 + 3 + ms72xx_ctl/ms7200_ctl/cmd_index[7]/opit_0_inv_A2Q21/CLK + ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/ADA0[12] - ddrphy_clkin - ddrphy_clkin + clk_10m + clk_10m rise-rise 0.019 - 6.654 - 7.101 - -0.428 + 3.547 + 3.849 + -0.283 0.000 - 0.430 - 0.179 (41.6%) - 0.251 (58.4%) + 0.381 + 0.182 (47.8%) + 0.199 (52.2%) - Path #8: hold slack is 0.118(MET) + Path #19: hold slack is 0.235(MET) -
+
Location Delay Type @@ -125560,7 +130007,7 @@ Logical Resource - Clock ddrphy_clkin (rising edge) + Clock clk_10m (rising edge) 0.000 0.000 @@ -125616,137 +130063,73 @@ _N69 - PLL_158_55/CLK_OUT1 - td - 0.074 - 1.934 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 0.603 - 2.537 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 2.537 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 0.981 - 3.518 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.089 - 3.607 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 0.669 - 4.276 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.200 - 4.476 - r - clkgate_8/gopclkgate/OUT - - - - net (fanout=1) - 0.000 - 4.476 - - ntclkgate_0 - - - IOCKDIV_6_323/CLK_IODIV + PLL_158_55/CLK_OUT4 td - 0.000 - 4.476 + 0.079 + 1.939 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + u_sys_pll/u_pll_e3/goppll/CLKOUT4 net (fanout=1) - 1.283 - 5.759 + 0.603 + 2.542 - u_axi_ddr_top/clk + clk_10m - USCM_84_116/CLK_USCM + USCM_84_110/CLK_USCM td 0.000 - 5.759 + 2.542 r - clkbufg_0/gopclkbufg/CLKOUT + clkbufg_4/gopclkbufg/CLKOUT - net (fanout=5464) - 0.895 - 6.654 + net (fanout=235) + 1.005 + 3.547 - ntclkbufg_0 + ntclkbufg_4 - CLMA_58_144/CLK + CLMA_230_325/CLK r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK + ms72xx_ctl/ms7200_ctl/cmd_index[7]/opit_0_inv_A2Q21/CLK - CLMA_58_144/Q0 + CLMA_230_325/Q3 tco - 0.179 - 6.833 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/Q0 + 0.182 + 3.729 + r + ms72xx_ctl/ms7200_ctl/cmd_index[7]/opit_0_inv_A2Q21/Q1 - net (fanout=7) - 0.251 - 7.084 + net (fanout=3) + 0.199 + 3.928 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [0] + ms72xx_ctl/ms7200_ctl/cmd_index [7] - CLMS_62_145/M0 + DRM_234_316/ADA0[12] - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_0/ram32x1dp/WADM0 + r + ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/ADA0[12]
- +
Location Delay Type @@ -125756,7 +130139,7 @@ Logical Resource - Clock ddrphy_clkin (rising edge) + Clock clk_10m (rising edge) 0.000 0.000 @@ -125812,114 +130195,50 @@ _N69 - PLL_158_55/CLK_OUT1 - td - 0.079 - 2.193 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 0.614 - 2.807 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 2.807 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.019 - 3.826 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.094 - 3.920 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 0.682 - 4.602 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.268 - 4.870 - r - clkgate_8/gopclkgate/OUT - - - - net (fanout=1) - 0.000 - 4.870 - - ntclkgate_0 - - - IOCKDIV_6_323/CLK_IODIV + PLL_158_55/CLK_OUT4 td - 0.000 - 4.870 + 0.084 + 2.198 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + u_sys_pll/u_pll_e3/goppll/CLKOUT4 net (fanout=1) - 1.306 - 6.176 + 0.614 + 2.812 - u_axi_ddr_top/clk + clk_10m - USCM_84_116/CLK_USCM + USCM_84_110/CLK_USCM td 0.000 - 6.176 + 2.812 r - clkbufg_0/gopclkbufg/CLKOUT + clkbufg_4/gopclkbufg/CLKOUT - net (fanout=5464) - 0.925 - 7.101 + net (fanout=235) + 1.037 + 3.849 - ntclkbufg_0 + ntclkbufg_4 - CLMS_62_145/CLK + DRM_234_316/CLKA[0] r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_0/ram32x1dp/WCLK + ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKA[0] clock pessimism - -0.428 - 6.673 + -0.283 + 3.566 @@ -125927,15 +130246,15 @@ clock uncertainty 0.000 - 6.673 + 3.566 Hold time - 0.293 - 6.966 + 0.127 + 3.693 @@ -125944,27 +130263,27 @@ - 0.118 + 0.242 0 - 7 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram32x1dp/WADM0 + 3 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/pll_lock_d[1]/opit_0_inv/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_b_ff/opit_0_inv/D - ddrphy_clkin - ddrphy_clkin + clk_200m + clk_200m rise-rise - 0.019 - 6.654 - 7.101 - -0.428 + 0.015 + 3.432 + 3.732 + -0.285 0.000 - 0.430 - 0.179 (41.6%) - 0.251 (58.4%) + 0.246 + 0.182 (74.0%) + 0.064 (26.0%) - Path #9: hold slack is 0.118(MET) + Path #20: hold slack is 0.242(MET) -
+
Location Delay Type @@ -125974,7 +130293,7 @@ Logical Resource - Clock ddrphy_clkin (rising edge) + Clock clk_200m (rising edge) 0.000 0.000 @@ -126043,7 +130362,7 @@ 0.603 2.537 - zoom_clk + ddr_clk USCM_84_113/CLK_USCM @@ -126055,112 +130374,48 @@ - net (fanout=68) - 0.981 - 3.518 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.089 - 3.607 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 0.669 - 4.276 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.200 - 4.476 - r - clkgate_8/gopclkgate/OUT - - - - net (fanout=1) - 0.000 - 4.476 - - ntclkgate_0 - - - IOCKDIV_6_323/CLK_IODIV - td - 0.000 - 4.476 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV - - - - net (fanout=1) - 1.283 - 5.759 - - u_axi_ddr_top/clk - - - USCM_84_116/CLK_USCM - td - 0.000 - 5.759 - r - clkbufg_0/gopclkbufg/CLKOUT - - - - net (fanout=5464) + net (fanout=71) 0.895 - 6.654 + 3.432 - ntclkbufg_0 + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - CLMA_58_144/CLK + CLMS_94_193/CLK r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/pll_lock_d[1]/opit_0_inv/CLK - CLMA_58_144/Q0 + CLMS_94_193/Q0 tco - 0.179 - 6.833 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/opit_0_inv_A2Q21/Q0 + 0.182 + 3.614 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/pll_lock_d[1]/opit_0_inv/Q - net (fanout=7) - 0.251 - 7.084 + net (fanout=3) + 0.064 + 3.678 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/wr_addr [0] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/pll_lock_d [1] - CLMS_62_145/M0 + CLMA_94_192/M0 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram32x1dp/WADM0 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_b_ff/opit_0_inv/D
- +
Location Delay Type @@ -126170,7 +130425,7 @@ Logical Resource - Clock ddrphy_clkin (rising edge) + Clock clk_200m (rising edge) 0.000 0.000 @@ -126239,7 +130494,7 @@ 0.614 2.807 - zoom_clk + ddr_clk USCM_84_113/CLK_USCM @@ -126251,89 +130506,25 @@ - net (fanout=68) - 1.019 - 3.826 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.094 - 3.920 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 0.682 - 4.602 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.268 - 4.870 - r - clkgate_8/gopclkgate/OUT - - - - net (fanout=1) - 0.000 - 4.870 - - ntclkgate_0 - - - IOCKDIV_6_323/CLK_IODIV - td - 0.000 - 4.870 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV - - - - net (fanout=1) - 1.306 - 6.176 - - u_axi_ddr_top/clk - - - USCM_84_116/CLK_USCM - td - 0.000 - 6.176 - r - clkbufg_0/gopclkbufg/CLKOUT - - - - net (fanout=5464) + net (fanout=71) 0.925 - 7.101 + 3.732 - ntclkbufg_0 + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - CLMS_62_145/CLK + CLMA_94_192/CLK r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram32x1dp/WCLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_b_ff/opit_0_inv/CLK clock pessimism - -0.428 - 6.673 + -0.285 + 3.447 @@ -126341,15 +130532,15 @@ clock uncertainty 0.000 - 6.673 + 3.447 Hold time - 0.293 - 6.966 + -0.011 + 3.436 @@ -126358,27 +130549,27 @@ - 0.139 + 0.250 0 - 3 - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[8] + 1 + u_ov5640/cmos2_href_d0/opit_0/CLK + u_ov5640/cmos2_href_d1/opit_0/D - clk_50m - clk_50m + cmos2_pclk + cmos2_pclk rise-rise - 0.062 - 3.436 - 3.779 - -0.281 + 0.007 + 3.550 + 3.887 + -0.330 0.000 - 0.363 - 0.180 (49.6%) - 0.183 (50.4%) + 0.446 + 0.236 (52.9%) + 0.210 (47.1%) - Path #10: hold slack is 0.139(MET) + Path #21: hold slack is 0.250(MET) -
+
Location Delay Type @@ -126388,7 +130579,7 @@ Logical Resource - Clock clk_50m (rising edge) + Clock cmos2_pclk (rising edge) 0.000 0.000 @@ -126396,121 +130587,105 @@ - P20 + W6 0.000 0.000 r - clk (port) + cmos2_pclk (port) net (fanout=1) - 0.074 - 0.074 + 0.071 + 0.071 - clk + cmos2_pclk - IOBS_LR_328_209/DIN + IOBD_37_0/DIN td - 1.285 - 1.359 + 0.735 + 0.806 r - clk_ibuf/opit_0/O + cmos2_pclk_ibuf/opit_0/O net (fanout=1) 0.000 - 1.359 + 0.806 - clk_ibuf/ntD + cmos2_pclk_ibuf/ntD - IOL_327_210/INCK + IOL_39_6/RX_DATA_DD td - 0.038 - 1.397 + 0.066 + 0.872 r - clk_ibuf/opit_1/INCK + cmos2_pclk_ibuf/opit_1/OUT net (fanout=1) - 0.463 - 1.860 - - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.078 - 1.938 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 0.603 - 2.541 + 1.744 + 2.616 - rd3_clk + nt_cmos2_pclk - USCM_84_108/CLK_USCM + USCM_84_119/CLK_USCM td 0.000 - 2.541 + 2.616 r - clkbufg_1/gopclkbufg/CLKOUT + clkbufg_7/gopclkbufg/CLKOUT - net (fanout=2517) - 0.895 - 3.436 + net (fanout=118) + 0.934 + 3.550 - ntclkbufg_1 + ntclkbufg_7 - CLMA_90_12/CLK + CLMS_78_21/CLK r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/CLK + u_ov5640/cmos2_href_d0/opit_0/CLK - CLMA_90_12/Q2 + CLMS_78_21/Y2 tco - 0.180 - 3.616 - f - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/opit_0_inv_A2Q21/Q0 + 0.236 + 3.786 + r + u_ov5640/cmos2_href_d0/opit_0/Q - net (fanout=3) - 0.183 - 3.799 + net (fanout=1) + 0.210 + 3.996 - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/wr_addr [6] + u_ov5640/cmos2_href_d0 - DRM_82_4/ADA0[8] + CLMS_74_17/M2 - f - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/ADDRA[8] + r + u_ov5640/cmos2_href_d1/opit_0/D
- +
Location Delay Type @@ -126520,7 +130695,7 @@ Logical Resource - Clock clk_50m (rising edge) + Clock cmos2_pclk (rising edge) 0.000 0.000 @@ -126528,114 +130703,98 @@ - P20 + W6 0.000 0.000 r - clk (port) + cmos2_pclk (port) net (fanout=1) - 0.074 - 0.074 + 0.071 + 0.071 - clk + cmos2_pclk - IOBS_LR_328_209/DIN + IOBD_37_0/DIN td - 1.504 - 1.578 + 0.861 + 0.932 r - clk_ibuf/opit_0/O + cmos2_pclk_ibuf/opit_0/O net (fanout=1) 0.000 - 1.578 + 0.932 - clk_ibuf/ntD + cmos2_pclk_ibuf/ntD - IOL_327_210/INCK + IOL_39_6/RX_DATA_DD td - 0.058 - 1.636 + 0.096 + 1.028 r - clk_ibuf/opit_1/INCK + cmos2_pclk_ibuf/opit_1/OUT net (fanout=1) - 0.478 - 2.114 + 1.907 + 2.935 - _N69 - - - PLL_158_55/CLK_OUT0 - td - 0.083 - 2.197 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 0.614 - 2.811 - - rd3_clk + nt_cmos2_pclk - USCM_84_108/CLK_USCM + USCM_84_119/CLK_USCM td 0.000 - 2.811 + 2.935 r - clkbufg_1/gopclkbufg/CLKOUT + clkbufg_7/gopclkbufg/CLKOUT - net (fanout=2517) - 0.968 - 3.779 + net (fanout=118) + 0.952 + 3.887 - ntclkbufg_1 + ntclkbufg_7 - DRM_82_4/CLKA[0] + CLMS_74_17/CLK r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/iGopDrm/CLKA + u_ov5640/cmos2_href_d1/opit_0/CLK clock pessimism - -0.281 - 3.498 + -0.330 + 3.557 clock uncertainty - 0.000 - 3.498 + 0.200 + 3.757 Hold time - 0.162 - 3.660 + -0.011 + 3.746 @@ -126644,27 +130803,27 @@ - 0.180 + 0.252 0 1 - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/D + adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm/CLK + adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm/L4 - clk_50m - clk_50m + clk_720p60Hz + clk_720p60Hz rise-rise - 0.016 - 3.456 - 3.757 - -0.285 + 0.015 + 5.516 + 5.878 + -0.347 0.000 - 0.236 - 0.178 (75.4%) - 0.058 (24.6%) + 0.238 + 0.180 (75.6%) + 0.058 (24.4%) - Path #11: hold slack is 0.180(MET) + Path #22: hold slack is 0.252(MET) -
+
Location Delay Type @@ -126674,7 +130833,7 @@ Logical Resource - Clock clk_50m (rising edge) + Clock clk_720p60Hz (rising edge) 0.000 0.000 @@ -126746,57 +130905,89 @@ rd3_clk - USCM_84_108/CLK_USCM + USCM_84_154/CLK_USCM td 0.000 2.541 r - clkbufg_1/gopclkbufg/CLKOUT + USCMROUTE_0/CLKOUT - net (fanout=2517) + net (fanout=1) + 1.091 + 3.632 + + ntR3950 + + + PLL_158_303/CLK_OUT1 + td + 0.074 + 3.706 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) 0.915 - 3.456 + 4.621 - ntclkbufg_1 + nt_pix_clk + + + USCM_84_117/CLK_USCM + td + 0.000 + 4.621 + r + clkbufg_2/gopclkbufg/CLKOUT - CLMA_58_88/CLK + + net (fanout=1635) + 0.895 + 5.516 + + ntclkbufg_2 + + + CLMA_250_177/CLK r - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/CLK + adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm/CLK - CLMA_58_88/Q3 + CLMA_250_177/Q2 tco - 0.178 - 3.634 + 0.180 + 5.696 f - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/opit_0/Q + adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm/Q net (fanout=1) 0.058 - 3.692 + 5.754 - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr1 [8] + adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/dividend_t[13] [9] - CLMA_58_89/AD + CLMA_250_176/A4 f - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/D + adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm/L4
- +
Location Delay Type @@ -126806,7 +130997,7 @@ Logical Resource - Clock clk_50m (rising edge) + Clock clk_720p60Hz (rising edge) 0.000 0.000 @@ -126878,34 +131069,66 @@ rd3_clk - USCM_84_108/CLK_USCM + USCM_84_154/CLK_USCM td 0.000 2.811 r - clkbufg_1/gopclkbufg/CLKOUT + USCMROUTE_0/CLKOUT - net (fanout=2517) - 0.946 - 3.757 + net (fanout=1) + 1.131 + 3.942 - ntclkbufg_1 + ntR3950 + + + PLL_158_303/CLK_OUT1 + td + 0.079 + 4.021 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - CLMA_58_89/CLK + + net (fanout=2) + 0.932 + 4.953 + + nt_pix_clk + + + USCM_84_117/CLK_USCM + td + 0.000 + 4.953 + r + clkbufg_2/gopclkbufg/CLKOUT + + + + net (fanout=1635) + 0.925 + 5.878 + + ntclkbufg_2 + + + CLMA_250_176/CLK r - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[8]/opit_0/CLK + adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/dividend_kp[9]/opit_0_L5Q_perm/CLK clock pessimism - -0.285 - 3.472 + -0.347 + 5.531 @@ -126913,15 +131136,15 @@ clock uncertainty 0.000 - 3.472 + 5.531 Hold time - 0.040 - 3.512 + -0.029 + 5.502 @@ -126930,27 +131153,27 @@ - 0.195 + 0.252 0 - 1 - image_filiter_inst2/hybrid_filter_inst/pixel_ff[27]/opit_0/CLK - image_filiter_inst2/hybrid_filter_inst/pixel_ff[43]/opit_0/D + 2 + udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[3]/opit_0_A2Q21/CLK + udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr[4]/opit_0_A2Q21/I04 - clk_50m - clk_50m + clk_720p60Hz + clk_720p60Hz rise-rise - 0.001 - 3.436 - 3.736 - -0.299 + 0.015 + 5.626 + 5.990 + -0.349 0.000 - 0.236 - 0.178 (75.4%) - 0.058 (24.6%) + 0.239 + 0.180 (75.3%) + 0.059 (24.7%) - Path #12: hold slack is 0.195(MET) + Path #23: hold slack is 0.252(MET) -
+
Location Delay Type @@ -126960,7 +131183,7 @@ Logical Resource - Clock clk_50m (rising edge) + Clock clk_720p60Hz (rising edge) 0.000 0.000 @@ -127032,57 +131255,89 @@ rd3_clk - USCM_84_108/CLK_USCM + USCM_84_154/CLK_USCM td 0.000 2.541 r - clkbufg_1/gopclkbufg/CLKOUT + USCMROUTE_0/CLKOUT - net (fanout=2517) - 0.895 - 3.436 + net (fanout=1) + 1.091 + 3.632 - ntclkbufg_1 + ntR3950 + + + PLL_158_303/CLK_OUT1 + td + 0.074 + 3.706 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - CLMA_98_148/CLK + + net (fanout=2) + 0.915 + 4.621 + + nt_pix_clk + + + USCM_84_117/CLK_USCM + td + 0.000 + 4.621 + r + clkbufg_2/gopclkbufg/CLKOUT + + + + net (fanout=1635) + 1.005 + 5.626 + + ntclkbufg_2 + + + CLMA_230_280/CLK r - image_filiter_inst2/hybrid_filter_inst/pixel_ff[27]/opit_0/CLK + udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[3]/opit_0_A2Q21/CLK - CLMA_98_148/Q3 + CLMA_230_280/Q1 tco - 0.178 - 3.614 + 0.180 + 5.806 f - image_filiter_inst2/hybrid_filter_inst/pixel_ff[27]/opit_0/Q + udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[3]/opit_0_A2Q21/Q1 - net (fanout=1) - 0.058 - 3.672 + net (fanout=2) + 0.059 + 5.865 - image_filiter_inst2/hybrid_filter_inst/pixel_ff [27] + udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d [3] - CLMA_98_148/AD + CLMA_230_281/C4 f - image_filiter_inst2/hybrid_filter_inst/pixel_ff[43]/opit_0/D + udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr[4]/opit_0_A2Q21/I04
- +
Location Delay Type @@ -127092,7 +131347,7 @@ Logical Resource - Clock clk_50m (rising edge) + Clock clk_720p60Hz (rising edge) 0.000 0.000 @@ -127164,34 +131419,66 @@ rd3_clk - USCM_84_108/CLK_USCM + USCM_84_154/CLK_USCM td 0.000 2.811 r - clkbufg_1/gopclkbufg/CLKOUT + USCMROUTE_0/CLKOUT - net (fanout=2517) - 0.925 - 3.736 + net (fanout=1) + 1.131 + 3.942 - ntclkbufg_1 + ntR3950 + + + PLL_158_303/CLK_OUT1 + td + 0.079 + 4.021 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - CLMA_98_148/CLK + + net (fanout=2) + 0.932 + 4.953 + + nt_pix_clk + + + USCM_84_117/CLK_USCM + td + 0.000 + 4.953 + r + clkbufg_2/gopclkbufg/CLKOUT + + + + net (fanout=1635) + 1.037 + 5.990 + + ntclkbufg_2 + + + CLMA_230_281/CLK r - image_filiter_inst2/hybrid_filter_inst/pixel_ff[43]/opit_0/CLK + udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr[4]/opit_0_A2Q21/CLK clock pessimism - -0.299 - 3.437 + -0.349 + 5.641 @@ -127199,15 +131486,15 @@ clock uncertainty 0.000 - 3.437 + 5.641 Hold time - 0.040 - 3.477 + -0.028 + 5.613 @@ -127216,27 +131503,27 @@ - 0.196 + 0.255 0 1 - u_zoom_image/mult_image_g0/N2/gopapm/CLK - u_zoom_image/mult_image_g1/N2/gopapm/PI[0] + udp_wr_mem_inst/mem[190]/opit_0/CLK + param_manager_inst/param_modify_V/value[6]/opit_0_L5Q_perm/L0 - clk_200m - clk_200m + eth_rxc + eth_rxc rise-rise - 0.142 - 3.432 - 3.844 - -0.270 + 0.019 + 5.650 + 6.734 + -1.065 0.000 - 0.239 - 0.239 (100.0%) - 0.000 (0.0%) + 0.396 + 0.184 (46.5%) + 0.212 (53.5%) - Path #13: hold slack is 0.196(MET) + Path #24: hold slack is 0.255(MET) -
+
Location Delay Type @@ -127246,7 +131533,7 @@ Logical Resource - Clock clk_200m (rising edge) + Clock eth_rxc (rising edge) 0.000 0.000 @@ -127254,121 +131541,121 @@ - P20 + F14 0.000 0.000 r - clk (port) + eth_rxc (port) net (fanout=1) - 0.074 - 0.074 + 0.057 + 0.057 - clk + eth_rxc - IOBS_LR_328_209/DIN + IOBD_240_376/DIN td - 1.285 - 1.359 + 0.735 + 0.792 r - clk_ibuf/opit_0/O + eth_rxc_ibuf/opit_0/O net (fanout=1) 0.000 - 1.359 + 0.792 - clk_ibuf/ntD + eth_rxc_ibuf/ntD - IOL_327_210/INCK + IOL_243_374/INCK td 0.038 - 1.397 + 0.830 r - clk_ibuf/opit_1/INCK + eth_rxc_ibuf/opit_1/INCK net (fanout=1) - 0.463 - 1.860 + 0.363 + 1.193 - _N69 + _N66 - PLL_158_55/CLK_OUT1 + IOCKDLY_237_367/CLK_OUT td - 0.074 - 1.934 + 2.069 + 3.262 r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT - net (fanout=2) - 0.603 - 2.537 + net (fanout=1) + 1.493 + 4.755 - zoom_clk + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf - USCM_84_122/CLK_USCM + USCM_84_109/CLK_USCM td 0.000 - 2.537 + 4.755 r - USCMROUTE_2/CLKOUT + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - net (fanout=759) + net (fanout=1862) 0.895 - 3.432 + 5.650 - ntR3909 + gmii_clk - APM_206_240/CLK + CLMS_222_217/CLK r - u_zoom_image/mult_image_g0/N2/gopapm/CLK + udp_wr_mem_inst/mem[190]/opit_0/CLK - APM_206_240/PO[0] + CLMS_222_217/Q1 tco - 0.239 - 3.671 + 0.184 + 5.834 r - u_zoom_image/mult_image_g0/N2/gopapm/PO[0] + udp_wr_mem_inst/mem[190]/opit_0/Q net (fanout=1) - 0.000 - 3.671 + 0.212 + 6.046 - u_zoom_image/mult_image0[2] [0] + mem[190] - APM_206_252/PI[0] + CLMA_230_212/C0 r - u_zoom_image/mult_image_g1/N2/gopapm/PI[0] + param_manager_inst/param_modify_V/value[6]/opit_0_L5Q_perm/L0
- +
Location Delay Type @@ -127378,7 +131665,7 @@ Logical Resource - Clock clk_200m (rising edge) + Clock eth_rxc (rising edge) 0.000 0.000 @@ -127386,114 +131673,114 @@ - P20 + F14 0.000 0.000 r - clk (port) + eth_rxc (port) net (fanout=1) - 0.074 - 0.074 + 0.057 + 0.057 - clk + eth_rxc - IOBS_LR_328_209/DIN + IOBD_240_376/DIN td - 1.504 - 1.578 + 0.861 + 0.918 r - clk_ibuf/opit_0/O + eth_rxc_ibuf/opit_0/O net (fanout=1) 0.000 - 1.578 + 0.918 - clk_ibuf/ntD + eth_rxc_ibuf/ntD - IOL_327_210/INCK + IOL_243_374/INCK td 0.058 - 1.636 + 0.976 r - clk_ibuf/opit_1/INCK + eth_rxc_ibuf/opit_1/INCK net (fanout=1) - 0.478 - 2.114 + 0.370 + 1.346 - _N69 + _N66 - PLL_158_55/CLK_OUT1 + IOCKDLY_237_367/CLK_OUT td - 0.079 - 2.193 + 2.942 + 4.288 r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT - net (fanout=2) - 0.614 - 2.807 + net (fanout=1) + 1.521 + 5.809 - zoom_clk + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf - USCM_84_122/CLK_USCM + USCM_84_109/CLK_USCM td 0.000 - 2.807 + 5.809 r - USCMROUTE_2/CLKOUT + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - net (fanout=759) - 1.037 - 3.844 + net (fanout=1862) + 0.925 + 6.734 - ntR3909 + gmii_clk - APM_206_252/CLK + CLMA_230_212/CLK r - u_zoom_image/mult_image_g1/N2/gopapm/CLK + param_manager_inst/param_modify_V/value[6]/opit_0_L5Q_perm/CLK clock pessimism - -0.270 - 3.574 + -1.065 + 5.669 clock uncertainty - 0.000 - 3.574 + 0.200 + 5.869 Hold time - -0.099 - 3.475 + -0.078 + 5.791 @@ -127502,27 +131789,27 @@ - 0.196 + 0.255 0 - 1 - u_zoom_image/mult_image_g0/N2/gopapm/CLK - u_zoom_image/mult_image_g1/N2/gopapm/PI[1] + 2 + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[17]/opit_0_L5Q_perm/CLK + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[25]/opit_0_L5Q_perm/L1 - clk_200m - clk_200m + eth_rxc + eth_rxc rise-rise - 0.142 - 3.432 - 3.844 - -0.270 + 0.015 + 5.760 + 6.846 + -1.071 0.000 - 0.239 - 0.239 (100.0%) - 0.000 (0.0%) + 0.377 + 0.183 (48.5%) + 0.194 (51.5%) - Path #14: hold slack is 0.196(MET) + Path #25: hold slack is 0.255(MET) -
+
Location Delay Type @@ -127532,7 +131819,7 @@ Logical Resource - Clock clk_200m (rising edge) + Clock eth_rxc (rising edge) 0.000 0.000 @@ -127540,121 +131827,121 @@ - P20 + F14 0.000 0.000 r - clk (port) + eth_rxc (port) net (fanout=1) - 0.074 - 0.074 + 0.057 + 0.057 - clk + eth_rxc - IOBS_LR_328_209/DIN + IOBD_240_376/DIN td - 1.285 - 1.359 + 0.735 + 0.792 r - clk_ibuf/opit_0/O + eth_rxc_ibuf/opit_0/O net (fanout=1) 0.000 - 1.359 + 0.792 - clk_ibuf/ntD + eth_rxc_ibuf/ntD - IOL_327_210/INCK + IOL_243_374/INCK td 0.038 - 1.397 + 0.830 r - clk_ibuf/opit_1/INCK + eth_rxc_ibuf/opit_1/INCK net (fanout=1) - 0.463 - 1.860 + 0.363 + 1.193 - _N69 + _N66 - PLL_158_55/CLK_OUT1 + IOCKDLY_237_367/CLK_OUT td - 0.074 - 1.934 + 2.069 + 3.262 r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT - net (fanout=2) - 0.603 - 2.537 + net (fanout=1) + 1.493 + 4.755 - zoom_clk + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf - USCM_84_122/CLK_USCM + USCM_84_109/CLK_USCM td 0.000 - 2.537 + 4.755 r - USCMROUTE_2/CLKOUT + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - net (fanout=759) - 0.895 - 3.432 + net (fanout=1862) + 1.005 + 5.760 - ntR3909 + gmii_clk - APM_206_240/CLK + CLMA_186_264/CLK r - u_zoom_image/mult_image_g0/N2/gopapm/CLK + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[17]/opit_0_L5Q_perm/CLK - APM_206_240/PO[1] + CLMA_186_264/Q2 tco - 0.239 - 3.671 + 0.183 + 5.943 r - u_zoom_image/mult_image_g0/N2/gopapm/PO[1] + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[17]/opit_0_L5Q_perm/Q - net (fanout=1) - 0.000 - 3.671 + net (fanout=2) + 0.194 + 6.137 - u_zoom_image/mult_image0[2] [1] + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t [17] - APM_206_252/PI[1] + CLMS_186_265/A1 r - u_zoom_image/mult_image_g1/N2/gopapm/PI[1] + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[25]/opit_0_L5Q_perm/L1
- +
Location Delay Type @@ -127664,7 +131951,7 @@ Logical Resource - Clock clk_200m (rising edge) + Clock eth_rxc (rising edge) 0.000 0.000 @@ -127672,114 +131959,114 @@ - P20 + F14 0.000 0.000 r - clk (port) + eth_rxc (port) net (fanout=1) - 0.074 - 0.074 + 0.057 + 0.057 - clk + eth_rxc - IOBS_LR_328_209/DIN + IOBD_240_376/DIN td - 1.504 - 1.578 + 0.861 + 0.918 r - clk_ibuf/opit_0/O + eth_rxc_ibuf/opit_0/O net (fanout=1) 0.000 - 1.578 + 0.918 - clk_ibuf/ntD + eth_rxc_ibuf/ntD - IOL_327_210/INCK + IOL_243_374/INCK td 0.058 - 1.636 + 0.976 r - clk_ibuf/opit_1/INCK + eth_rxc_ibuf/opit_1/INCK net (fanout=1) - 0.478 - 2.114 + 0.370 + 1.346 - _N69 + _N66 - PLL_158_55/CLK_OUT1 + IOCKDLY_237_367/CLK_OUT td - 0.079 - 2.193 + 2.942 + 4.288 r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT - net (fanout=2) - 0.614 - 2.807 + net (fanout=1) + 1.521 + 5.809 - zoom_clk + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf - USCM_84_122/CLK_USCM + USCM_84_109/CLK_USCM td 0.000 - 2.807 + 5.809 r - USCMROUTE_2/CLKOUT + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT - net (fanout=759) + net (fanout=1862) 1.037 - 3.844 + 6.846 - ntR3909 + gmii_clk - APM_206_252/CLK + CLMS_186_265/CLK r - u_zoom_image/mult_image_g1/N2/gopapm/CLK + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[25]/opit_0_L5Q_perm/CLK clock pessimism - -0.270 - 3.574 + -1.071 + 5.775 clock uncertainty - 0.000 - 3.574 + 0.200 + 5.975 Hold time - -0.099 - 3.475 + -0.093 + 5.882 @@ -127788,27 +132075,27 @@ - 0.196 + 0.257 0 1 - u_zoom_image/mult_image_g0/N2/gopapm/CLK - u_zoom_image/mult_image_g1/N2/gopapm/PI[2] + u_ov5640/cmos2_d_d0[4]/opit_0/CLK + u_ov5640/cmos2_d_d1[4]/opit_0/D - clk_200m - clk_200m + cmos2_pclk + cmos2_pclk rise-rise - 0.142 - 3.432 - 3.844 - -0.270 + 0.001 + 3.511 + 3.860 + -0.348 0.000 - 0.239 - 0.239 (100.0%) - 0.000 (0.0%) + 0.447 + 0.236 (52.8%) + 0.211 (47.2%) - Path #15: hold slack is 0.196(MET) + Path #26: hold slack is 0.257(MET) -
+
Location Delay Type @@ -127818,7 +132105,7 @@ Logical Resource - Clock clk_200m (rising edge) + Clock cmos2_pclk (rising edge) 0.000 0.000 @@ -127826,121 +132113,105 @@ - P20 + W6 0.000 0.000 r - clk (port) + cmos2_pclk (port) net (fanout=1) - 0.074 - 0.074 + 0.071 + 0.071 - clk + cmos2_pclk - IOBS_LR_328_209/DIN + IOBD_37_0/DIN td - 1.285 - 1.359 + 0.735 + 0.806 r - clk_ibuf/opit_0/O + cmos2_pclk_ibuf/opit_0/O net (fanout=1) 0.000 - 1.359 + 0.806 - clk_ibuf/ntD + cmos2_pclk_ibuf/ntD - IOL_327_210/INCK + IOL_39_6/RX_DATA_DD td - 0.038 - 1.397 + 0.066 + 0.872 r - clk_ibuf/opit_1/INCK + cmos2_pclk_ibuf/opit_1/OUT net (fanout=1) - 0.463 - 1.860 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.074 - 1.934 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 0.603 - 2.537 + 1.744 + 2.616 - zoom_clk + nt_cmos2_pclk - USCM_84_122/CLK_USCM + USCM_84_119/CLK_USCM td 0.000 - 2.537 + 2.616 r - USCMROUTE_2/CLKOUT + clkbufg_7/gopclkbufg/CLKOUT - net (fanout=759) + net (fanout=118) 0.895 - 3.432 + 3.511 - ntR3909 + ntclkbufg_7 - APM_206_240/CLK + CLMA_138_20/CLK r - u_zoom_image/mult_image_g0/N2/gopapm/CLK + u_ov5640/cmos2_d_d0[4]/opit_0/CLK - APM_206_240/PO[2] + CLMA_138_20/Y0 tco - 0.239 - 3.671 + 0.236 + 3.747 r - u_zoom_image/mult_image_g0/N2/gopapm/PO[2] + u_ov5640/cmos2_d_d0[4]/opit_0/Q net (fanout=1) - 0.000 - 3.671 + 0.211 + 3.958 - u_zoom_image/mult_image0[2] [2] + u_ov5640/cmos2_d_d0 [4] - APM_206_252/PI[2] + CLMA_138_20/M2 r - u_zoom_image/mult_image_g1/N2/gopapm/PI[2] + u_ov5640/cmos2_d_d1[4]/opit_0/D
- +
Location Delay Type @@ -127950,7 +132221,7 @@ Logical Resource - Clock clk_200m (rising edge) + Clock cmos2_pclk (rising edge) 0.000 0.000 @@ -127958,114 +132229,98 @@ - P20 + W6 0.000 0.000 r - clk (port) + cmos2_pclk (port) net (fanout=1) - 0.074 - 0.074 + 0.071 + 0.071 - clk + cmos2_pclk - IOBS_LR_328_209/DIN + IOBD_37_0/DIN td - 1.504 - 1.578 + 0.861 + 0.932 r - clk_ibuf/opit_0/O + cmos2_pclk_ibuf/opit_0/O net (fanout=1) 0.000 - 1.578 + 0.932 - clk_ibuf/ntD + cmos2_pclk_ibuf/ntD - IOL_327_210/INCK + IOL_39_6/RX_DATA_DD td - 0.058 - 1.636 + 0.096 + 1.028 r - clk_ibuf/opit_1/INCK + cmos2_pclk_ibuf/opit_1/OUT net (fanout=1) - 0.478 - 2.114 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.079 - 2.193 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 0.614 - 2.807 + 1.907 + 2.935 - zoom_clk + nt_cmos2_pclk - USCM_84_122/CLK_USCM + USCM_84_119/CLK_USCM td 0.000 - 2.807 + 2.935 r - USCMROUTE_2/CLKOUT + clkbufg_7/gopclkbufg/CLKOUT - net (fanout=759) - 1.037 - 3.844 + net (fanout=118) + 0.925 + 3.860 - ntR3909 + ntclkbufg_7 - APM_206_252/CLK + CLMA_138_20/CLK r - u_zoom_image/mult_image_g1/N2/gopapm/CLK + u_ov5640/cmos2_d_d1[4]/opit_0/CLK clock pessimism - -0.270 - 3.574 + -0.348 + 3.512 clock uncertainty - 0.000 - 3.574 + 0.200 + 3.712 Hold time - -0.099 - 3.475 + -0.011 + 3.701 @@ -128074,27 +132329,27 @@ - 0.232 + 0.257 0 - 3 - ms72xx_ctl/ms7200_ctl/cmd_index[5]/opit_0_inv_A2Q21/CLK - ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/ADA0[9] + 7 + u_sync_vg/v_count[3]/opit_0_L5Q_perm/CLK + u_sync_vg/pos_y[4]/opit_0_A2Q21/I04 - clk_10m - clk_10m + clk_720p60Hz + clk_720p60Hz rise-rise - 0.019 - 3.437 - 3.737 - -0.281 + 0.015 + 5.626 + 5.990 + -0.349 0.000 - 0.378 - 0.182 (48.1%) - 0.196 (51.9%) + 0.244 + 0.180 (73.8%) + 0.064 (26.2%) - Path #16: hold slack is 0.232(MET) + Path #27: hold slack is 0.257(MET) -
+
Location Delay Type @@ -128104,7 +132359,7 @@ Logical Resource - Clock clk_10m (rising edge) + Clock clk_720p60Hz (rising edge) 0.000 0.000 @@ -128160,73 +132415,105 @@ _N69 - PLL_158_55/CLK_OUT4 + PLL_158_55/CLK_OUT0 td - 0.079 - 1.939 + 0.078 + 1.938 r - u_sys_pll/u_pll_e3/goppll/CLKOUT4 + u_sys_pll/u_pll_e3/goppll/CLKOUT0 - net (fanout=1) + net (fanout=2) 0.603 - 2.542 + 2.541 - clk_10m + rd3_clk - USCM_84_110/CLK_USCM + USCM_84_154/CLK_USCM td 0.000 - 2.542 + 2.541 r - clkbufg_3/gopclkbufg/CLKOUT + USCMROUTE_0/CLKOUT - net (fanout=235) - 0.895 - 3.437 + net (fanout=1) + 1.091 + 3.632 - ntclkbufg_3 + ntR3950 + + + PLL_158_303/CLK_OUT1 + td + 0.074 + 3.706 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 0.915 + 4.621 + + nt_pix_clk + + + USCM_84_117/CLK_USCM + td + 0.000 + 4.621 + r + clkbufg_2/gopclkbufg/CLKOUT + + + + net (fanout=1635) + 1.005 + 5.626 + + ntclkbufg_2 - CLMA_230_117/CLK + CLMS_246_253/CLK r - ms72xx_ctl/ms7200_ctl/cmd_index[5]/opit_0_inv_A2Q21/CLK + u_sync_vg/v_count[3]/opit_0_L5Q_perm/CLK - CLMA_230_117/Q0 + CLMS_246_253/Q1 tco - 0.182 - 3.619 - r - ms72xx_ctl/ms7200_ctl/cmd_index[5]/opit_0_inv_A2Q21/Q0 + 0.180 + 5.806 + f + u_sync_vg/v_count[3]/opit_0_L5Q_perm/Q - net (fanout=3) - 0.196 - 3.815 + net (fanout=7) + 0.064 + 5.870 - ms72xx_ctl/ms7200_ctl/cmd_index [4] + u_sync_vg/v_count [3] - DRM_234_108/ADA0[9] + CLMA_246_252/C4 - r - ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/ADA0[9] + f + u_sync_vg/pos_y[4]/opit_0_A2Q21/I04
- +
Location Delay Type @@ -128236,7 +132523,7 @@ Logical Resource - Clock clk_10m (rising edge) + Clock clk_720p60Hz (rising edge) 0.000 0.000 @@ -128292,50 +132579,82 @@ _N69 - PLL_158_55/CLK_OUT4 + PLL_158_55/CLK_OUT0 td - 0.084 - 2.198 + 0.083 + 2.197 r - u_sys_pll/u_pll_e3/goppll/CLKOUT4 + u_sys_pll/u_pll_e3/goppll/CLKOUT0 - net (fanout=1) + net (fanout=2) 0.614 - 2.812 + 2.811 - clk_10m + rd3_clk - USCM_84_110/CLK_USCM + USCM_84_154/CLK_USCM td 0.000 - 2.812 + 2.811 r - clkbufg_3/gopclkbufg/CLKOUT + USCMROUTE_0/CLKOUT - net (fanout=235) - 0.925 - 3.737 + net (fanout=1) + 1.131 + 3.942 - ntclkbufg_3 + ntR3950 - DRM_234_108/CLKA[0] + PLL_158_303/CLK_OUT1 + td + 0.079 + 4.021 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 0.932 + 4.953 + + nt_pix_clk + + + USCM_84_117/CLK_USCM + td + 0.000 + 4.953 + r + clkbufg_2/gopclkbufg/CLKOUT + + + + net (fanout=1635) + 1.037 + 5.990 + + ntclkbufg_2 + + + CLMA_246_252/CLK r - ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKA[0] + u_sync_vg/pos_y[4]/opit_0_A2Q21/CLK clock pessimism - -0.281 - 3.456 + -0.349 + 5.641 @@ -128343,15 +132662,15 @@ clock uncertainty 0.000 - 3.456 + 5.641 Hold time - 0.127 - 3.583 + -0.028 + 5.613 @@ -128360,27 +132679,27 @@ - 0.235 + 0.261 0 - 3 - ms72xx_ctl/ms7200_ctl/cmd_index[3]/opit_0_inv_A2Q21/CLK - ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/ADA0[8] + 1 + u_ov5640/cmos2_d_d1[3]/opit_0/CLK + u_ov5640/cmos2_8_16bit/pdata_i0[3]/opit_0/D - clk_10m - clk_10m + cmos2_pclk + cmos2_pclk rise-rise 0.019 - 3.437 - 3.737 - -0.281 + 3.511 + 3.860 + -0.330 0.000 - 0.381 - 0.182 (47.8%) - 0.199 (52.2%) + 0.469 + 0.184 (39.2%) + 0.285 (60.8%) - Path #17: hold slack is 0.235(MET) + Path #28: hold slack is 0.261(MET) -
+
Location Delay Type @@ -128390,7 +132709,7 @@ Logical Resource - Clock clk_10m (rising edge) + Clock cmos2_pclk (rising edge) 0.000 0.000 @@ -128398,121 +132717,105 @@ - P20 + W6 0.000 0.000 r - clk (port) + cmos2_pclk (port) net (fanout=1) - 0.074 - 0.074 + 0.071 + 0.071 - clk + cmos2_pclk - IOBS_LR_328_209/DIN + IOBD_37_0/DIN td - 1.285 - 1.359 + 0.735 + 0.806 r - clk_ibuf/opit_0/O + cmos2_pclk_ibuf/opit_0/O net (fanout=1) 0.000 - 1.359 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.038 - 1.397 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.463 - 1.860 + 0.806 - _N69 + cmos2_pclk_ibuf/ntD - PLL_158_55/CLK_OUT4 + IOL_39_6/RX_DATA_DD td - 0.079 - 1.939 + 0.066 + 0.872 r - u_sys_pll/u_pll_e3/goppll/CLKOUT4 + cmos2_pclk_ibuf/opit_1/OUT net (fanout=1) - 0.603 - 2.542 + 1.744 + 2.616 - clk_10m + nt_cmos2_pclk - USCM_84_110/CLK_USCM + USCM_84_119/CLK_USCM td 0.000 - 2.542 + 2.616 r - clkbufg_3/gopclkbufg/CLKOUT + clkbufg_7/gopclkbufg/CLKOUT - net (fanout=235) + net (fanout=118) 0.895 - 3.437 + 3.511 - ntclkbufg_3 + ntclkbufg_7 - CLMA_230_113/CLK + CLMA_126_25/CLK r - ms72xx_ctl/ms7200_ctl/cmd_index[3]/opit_0_inv_A2Q21/CLK + u_ov5640/cmos2_d_d1[3]/opit_0/CLK - CLMA_230_113/Q3 + CLMA_126_25/Q1 tco - 0.182 - 3.619 + 0.184 + 3.695 r - ms72xx_ctl/ms7200_ctl/cmd_index[3]/opit_0_inv_A2Q21/Q1 + u_ov5640/cmos2_d_d1[3]/opit_0/Q - net (fanout=3) - 0.199 - 3.818 + net (fanout=1) + 0.285 + 3.980 - ms72xx_ctl/ms7200_ctl/cmd_index [3] + u_ov5640/cmos2_d_d1 [3] - DRM_234_108/ADA0[8] + CLMA_130_32/M1 r - ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/ADA0[8] + u_ov5640/cmos2_8_16bit/pdata_i0[3]/opit_0/D
- +
Location Delay Type @@ -128522,7 +132825,7 @@ Logical Resource - Clock clk_10m (rising edge) + Clock cmos2_pclk (rising edge) 0.000 0.000 @@ -128530,114 +132833,98 @@ - P20 + W6 0.000 0.000 r - clk (port) + cmos2_pclk (port) net (fanout=1) - 0.074 - 0.074 + 0.071 + 0.071 - clk + cmos2_pclk - IOBS_LR_328_209/DIN + IOBD_37_0/DIN td - 1.504 - 1.578 + 0.861 + 0.932 r - clk_ibuf/opit_0/O + cmos2_pclk_ibuf/opit_0/O net (fanout=1) 0.000 - 1.578 + 0.932 - clk_ibuf/ntD + cmos2_pclk_ibuf/ntD - IOL_327_210/INCK + IOL_39_6/RX_DATA_DD td - 0.058 - 1.636 + 0.096 + 1.028 r - clk_ibuf/opit_1/INCK + cmos2_pclk_ibuf/opit_1/OUT net (fanout=1) - 0.478 - 2.114 - - _N69 - - - PLL_158_55/CLK_OUT4 - td - 0.084 - 2.198 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT4 - - + 1.907 + 2.935 - net (fanout=1) - 0.614 - 2.812 - - clk_10m + nt_cmos2_pclk - USCM_84_110/CLK_USCM + USCM_84_119/CLK_USCM td 0.000 - 2.812 + 2.935 r - clkbufg_3/gopclkbufg/CLKOUT + clkbufg_7/gopclkbufg/CLKOUT - net (fanout=235) + net (fanout=118) 0.925 - 3.737 + 3.860 - ntclkbufg_3 + ntclkbufg_7 - DRM_234_108/CLKA[0] + CLMA_130_32/CLK r - ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKA[0] + u_ov5640/cmos2_8_16bit/pdata_i0[3]/opit_0/CLK clock pessimism - -0.281 - 3.456 + -0.330 + 3.530 clock uncertainty - 0.000 - 3.456 + 0.200 + 3.730 Hold time - 0.127 - 3.583 + -0.011 + 3.719 @@ -128646,27 +132933,27 @@ - 0.237 + 0.267 0 3 - ms72xx_ctl/ms7200_ctl/cmd_index[7]/opit_0_inv_A2Q21/CLK - ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/ADA0[12] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]/opit_0_inv_L5Q_perm/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]/opit_0_inv_L5Q_perm/L4 - clk_10m - clk_10m + clk_200m + clk_200m rise-rise - 0.019 - 3.437 - 3.737 - -0.281 0.000 - 0.383 - 0.182 (47.5%) - 0.201 (52.5%) + 3.432 + 3.732 + -0.300 + 0.000 + 0.239 + 0.178 (74.5%) + 0.061 (25.5%) - Path #18: hold slack is 0.237(MET) + Path #29: hold slack is 0.267(MET) -
+
Location Delay Type @@ -128676,7 +132963,7 @@ Logical Resource - Clock clk_10m (rising edge) + Clock clk_200m (rising edge) 0.000 0.000 @@ -128732,73 +133019,73 @@ _N69 - PLL_158_55/CLK_OUT4 + PLL_158_55/CLK_OUT1 td - 0.079 - 1.939 + 0.074 + 1.934 r - u_sys_pll/u_pll_e3/goppll/CLKOUT4 + u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=1) + net (fanout=2) 0.603 - 2.542 + 2.537 - clk_10m + ddr_clk - USCM_84_110/CLK_USCM + USCM_84_113/CLK_USCM td 0.000 - 2.542 + 2.537 r - clkbufg_3/gopclkbufg/CLKOUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=235) + net (fanout=71) 0.895 - 3.437 + 3.432 - ntclkbufg_3 + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - CLMA_230_117/CLK + CLMS_38_185/CLK r - ms72xx_ctl/ms7200_ctl/cmd_index[7]/opit_0_inv_A2Q21/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]/opit_0_inv_L5Q_perm/CLK - CLMA_230_117/Q3 + CLMS_38_185/Q3 tco - 0.182 - 3.619 - r - ms72xx_ctl/ms7200_ctl/cmd_index[7]/opit_0_inv_A2Q21/Q1 + 0.178 + 3.610 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]/opit_0_inv_L5Q_perm/Q net (fanout=3) - 0.201 - 3.820 + 0.061 + 3.671 - ms72xx_ctl/ms7200_ctl/cmd_index [7] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg [4] - DRM_234_108/ADA0[12] + CLMS_38_185/D4 - r - ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/ADA0[12] + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]/opit_0_inv_L5Q_perm/L4
- +
Location Delay Type @@ -128808,7 +133095,7 @@ Logical Resource - Clock clk_10m (rising edge) + Clock clk_200m (rising edge) 0.000 0.000 @@ -128864,50 +133151,50 @@ _N69 - PLL_158_55/CLK_OUT4 + PLL_158_55/CLK_OUT1 td - 0.084 - 2.198 + 0.079 + 2.193 r - u_sys_pll/u_pll_e3/goppll/CLKOUT4 + u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=1) + net (fanout=2) 0.614 - 2.812 + 2.807 - clk_10m + ddr_clk - USCM_84_110/CLK_USCM + USCM_84_113/CLK_USCM td 0.000 - 2.812 + 2.807 r - clkbufg_3/gopclkbufg/CLKOUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=235) + net (fanout=71) 0.925 - 3.737 + 3.732 - ntclkbufg_3 + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - DRM_234_108/CLKA[0] + CLMS_38_185/CLK r - ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKA[0] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]/opit_0_inv_L5Q_perm/CLK clock pessimism - -0.281 - 3.456 + -0.300 + 3.432 @@ -128915,15 +133202,15 @@ clock uncertainty 0.000 - 3.456 + 3.432 Hold time - 0.127 - 3.583 + -0.028 + 3.404 @@ -128932,27 +133219,27 @@ - 0.251 + 0.268 0 - 1 - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/quotient[1]/opit_0_L5Q_perm/CLK - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/quotient[2]/opit_0_L5Q_perm/L4 + 4 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[2]/opit_0_inv_L5Q_perm/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[3]/opit_0_inv_L5Q_perm/L4 - clk_720p60Hz - clk_720p60Hz + clk_200m + clk_200m rise-rise - 0.015 - 5.516 - 5.878 - -0.347 + 0.001 + 3.432 + 3.732 + -0.299 0.000 - 0.238 - 0.180 (75.6%) - 0.058 (24.4%) + 0.241 + 0.180 (74.7%) + 0.061 (25.3%) - Path #19: hold slack is 0.251(MET) + Path #30: hold slack is 0.268(MET) -
+
Location Delay Type @@ -128962,7 +133249,7 @@ Logical Resource - Clock clk_720p60Hz (rising edge) + Clock clk_200m (rising edge) 0.000 0.000 @@ -129018,105 +133305,73 @@ _N69 - PLL_158_55/CLK_OUT0 - td - 0.078 - 1.938 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 - - - - net (fanout=2) - 0.603 - 2.541 - - rd3_clk - - - USCM_84_154/CLK_USCM - td - 0.000 - 2.541 - r - USCMROUTE_0/CLKOUT - - - - net (fanout=1) - 1.091 - 3.632 - - ntR3907 - - - PLL_158_303/CLK_OUT1 + PLL_158_55/CLK_OUT1 td 0.074 - 3.706 + 1.934 r - U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + u_sys_pll/u_pll_e3/goppll/CLKOUT1 net (fanout=2) - 0.915 - 4.621 + 0.603 + 2.537 - nt_pix_clk + ddr_clk - USCM_84_117/CLK_USCM + USCM_84_113/CLK_USCM td 0.000 - 4.621 + 2.537 r - clkbufg_2/gopclkbufg/CLKOUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=1635) + net (fanout=71) 0.895 - 5.516 + 3.432 - ntclkbufg_2 + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - CLMA_266_132/CLK + CLMA_38_184/CLK r - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/quotient[1]/opit_0_L5Q_perm/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[2]/opit_0_inv_L5Q_perm/CLK - CLMA_266_132/Q1 + CLMA_38_184/Q1 tco 0.180 - 5.696 + 3.612 f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/quotient[1]/opit_0_L5Q_perm/Q + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[2]/opit_0_inv_L5Q_perm/Q - net (fanout=1) - 0.058 - 5.754 + net (fanout=4) + 0.061 + 3.673 - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/quotient_t[4] [1] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg [2] - CLMS_266_133/C4 + CLMA_38_184/C4 f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/quotient[2]/opit_0_L5Q_perm/L4 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[3]/opit_0_inv_L5Q_perm/L4
- +
Location Delay Type @@ -129126,7 +133381,7 @@ Logical Resource - Clock clk_720p60Hz (rising edge) + Clock clk_200m (rising edge) 0.000 0.000 @@ -129182,82 +133437,50 @@ _N69 - PLL_158_55/CLK_OUT0 + PLL_158_55/CLK_OUT1 td - 0.083 - 2.197 + 0.079 + 2.193 r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 + u_sys_pll/u_pll_e3/goppll/CLKOUT1 net (fanout=2) 0.614 - 2.811 - - rd3_clk - - - USCM_84_154/CLK_USCM - td - 0.000 - 2.811 - r - USCMROUTE_0/CLKOUT - - - - net (fanout=1) - 1.131 - 3.942 + 2.807 - ntR3907 - - - PLL_158_303/CLK_OUT1 - td - 0.079 - 4.021 - r - U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + ddr_clk - - net (fanout=2) - 0.932 - 4.953 - - nt_pix_clk - - - USCM_84_117/CLK_USCM + USCM_84_113/CLK_USCM td 0.000 - 4.953 + 2.807 r - clkbufg_2/gopclkbufg/CLKOUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=1635) + net (fanout=71) 0.925 - 5.878 + 3.732 - ntclkbufg_2 + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - CLMS_266_133/CLK + CLMA_38_184/CLK r - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/quotient[2]/opit_0_L5Q_perm/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[3]/opit_0_inv_L5Q_perm/CLK clock pessimism - -0.347 - 5.531 + -0.299 + 3.433 @@ -129265,7 +133488,7 @@ clock uncertainty 0.000 - 5.531 + 3.433 @@ -129273,7 +133496,7 @@ Hold time -0.028 - 5.503 + 3.405 @@ -129282,27 +133505,27 @@ - 0.252 + 0.273 0 - 1 - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[3]/opit_0_L5Q_perm/CLK - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[4]/opit_0_L5Q_perm/L4 + 6 + u_ov5640/coms1_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK + u_ov5640/coms1_reg_config/reg_data/iGopDrm/ADA0[5] - clk_720p60Hz - clk_720p60Hz + clk_20k + clk_20k rise-rise - 0.015 - 5.516 - 5.878 - -0.347 + 0.019 + 5.862 + 6.370 + -0.489 0.000 - 0.238 - 0.180 (75.6%) - 0.058 (24.4%) + 0.419 + 0.182 (43.4%) + 0.237 (56.6%) - Path #20: hold slack is 0.252(MET) + Path #31: hold slack is 0.273(MET) -
+
Location Delay Type @@ -129312,7 +133535,7 @@ Logical Resource - Clock clk_720p60Hz (rising edge) + Clock clk_20k (rising edge) 0.000 0.000 @@ -129368,105 +133591,105 @@ _N69 - PLL_158_55/CLK_OUT0 + PLL_158_55/CLK_OUT3 td - 0.078 - 1.938 + 0.083 + 1.943 r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 + u_sys_pll/u_pll_e3/goppll/CLKOUT3 - net (fanout=2) + net (fanout=1) 0.603 - 2.541 + 2.546 - rd3_clk + clk_25m - USCM_84_154/CLK_USCM + USCM_84_114/CLK_USCM td 0.000 - 2.541 + 2.546 r - USCMROUTE_0/CLKOUT + clkbufg_8/gopclkbufg/CLKOUT - net (fanout=1) - 1.091 - 3.632 + net (fanout=26) + 0.895 + 3.441 - ntR3907 + ntclkbufg_8 - PLL_158_303/CLK_OUT1 - td - 0.074 - 3.706 + CLMS_122_9/Q1 + tco + 0.184 + 3.625 r - U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q - net (fanout=2) - 0.915 - 4.621 + net (fanout=3) + 1.342 + 4.967 - nt_pix_clk + u_ov5640/coms1_reg_config/clk_20k_regdiv - USCM_84_117/CLK_USCM + USCM_84_120/CLK_USCM td 0.000 - 4.621 + 4.967 r - clkbufg_2/gopclkbufg/CLKOUT + u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - net (fanout=1635) + net (fanout=19) 0.895 - 5.516 + 5.862 - ntclkbufg_2 + u_ov5640/coms1_reg_config/clock_20k - CLMA_262_132/CLK + CLMA_146_12/CLK r - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[3]/opit_0_L5Q_perm/CLK + u_ov5640/coms1_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK - CLMA_262_132/Q2 + CLMA_146_12/Q0 tco - 0.180 - 5.696 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[3]/opit_0_L5Q_perm/Q + 0.182 + 6.044 + r + u_ov5640/coms1_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/Q - net (fanout=1) - 0.058 - 5.754 + net (fanout=6) + 0.237 + 6.281 - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/quotient_t[1] [3] + u_ov5640/coms1_reg_config/reg_index [0] - CLMS_262_133/A4 + DRM_142_4/ADA0[5] - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[4]/opit_0_L5Q_perm/L4 + r + u_ov5640/coms1_reg_config/reg_data/iGopDrm/ADA0[5]
- +
Location Delay Type @@ -129476,7 +133699,7 @@ Logical Resource - Clock clk_720p60Hz (rising edge) + Clock clk_20k (rising edge) 0.000 0.000 @@ -129532,82 +133755,82 @@ _N69 - PLL_158_55/CLK_OUT0 + PLL_158_55/CLK_OUT3 td - 0.083 - 2.197 + 0.088 + 2.202 r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 + u_sys_pll/u_pll_e3/goppll/CLKOUT3 - net (fanout=2) + net (fanout=1) 0.614 - 2.811 + 2.816 - rd3_clk + clk_25m - USCM_84_154/CLK_USCM + USCM_84_114/CLK_USCM td 0.000 - 2.811 + 2.816 r - USCMROUTE_0/CLKOUT + clkbufg_8/gopclkbufg/CLKOUT - net (fanout=1) - 1.131 - 3.942 + net (fanout=26) + 0.925 + 3.741 - ntR3907 + ntclkbufg_8 - PLL_158_303/CLK_OUT1 - td - 0.079 - 4.021 + CLMS_122_9/Q1 + tco + 0.224 + 3.965 r - U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q - net (fanout=2) - 0.932 - 4.953 + net (fanout=3) + 1.480 + 5.445 - nt_pix_clk + u_ov5640/coms1_reg_config/clk_20k_regdiv - USCM_84_117/CLK_USCM + USCM_84_120/CLK_USCM td 0.000 - 4.953 + 5.445 r - clkbufg_2/gopclkbufg/CLKOUT + u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - net (fanout=1635) + net (fanout=19) 0.925 - 5.878 + 6.370 - ntclkbufg_2 + u_ov5640/coms1_reg_config/clock_20k - CLMS_262_133/CLK + DRM_142_4/CLKA[0] r - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[12].u_divider_step/quotient[4]/opit_0_L5Q_perm/CLK + u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKA[0] clock pessimism - -0.347 - 5.531 + -0.489 + 5.881 @@ -129615,15 +133838,15 @@ clock uncertainty 0.000 - 5.531 + 5.881 Hold time - -0.029 - 5.502 + 0.127 + 6.008 @@ -129632,27 +133855,27 @@ - 0.252 + 0.285 0 - 2 - udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[3]/opit_0_A2Q21/CLK - udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr[4]/opit_0_A2Q21/I04 + 4 + u_ov5640/coms2_reg_config/reg_index[4]/opit_0_inv_A2Q21/CLK + u_ov5640/coms2_reg_config/reg_data/iGopDrm/ADB0[8] - clk_720p60Hz - clk_720p60Hz + clk_20k + clk_20k rise-rise - 0.015 - 5.516 - 5.878 - -0.347 + 0.036 + 5.826 + 6.335 + -0.473 0.000 - 0.239 - 0.180 (75.3%) - 0.059 (24.7%) + 0.382 + 0.183 (47.9%) + 0.199 (52.1%) - Path #21: hold slack is 0.252(MET) + Path #32: hold slack is 0.285(MET) -
+
Location Delay Type @@ -129662,7 +133885,7 @@ Logical Resource - Clock clk_720p60Hz (rising edge) + Clock clk_20k (rising edge) 0.000 0.000 @@ -129718,105 +133941,105 @@ _N69 - PLL_158_55/CLK_OUT0 + PLL_158_55/CLK_OUT3 td - 0.078 - 1.938 + 0.083 + 1.943 r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 + u_sys_pll/u_pll_e3/goppll/CLKOUT3 - net (fanout=2) + net (fanout=1) 0.603 - 2.541 + 2.546 - rd3_clk + clk_25m - USCM_84_154/CLK_USCM + USCM_84_114/CLK_USCM td 0.000 - 2.541 + 2.546 r - USCMROUTE_0/CLKOUT + clkbufg_8/gopclkbufg/CLKOUT - net (fanout=1) - 1.091 - 3.632 + net (fanout=26) + 0.895 + 3.441 - ntR3907 + ntclkbufg_8 - PLL_158_303/CLK_OUT1 - td - 0.074 - 3.706 + CLMA_122_12/Q1 + tco + 0.184 + 3.625 r - U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q - net (fanout=2) - 0.915 - 4.621 + net (fanout=3) + 1.276 + 4.901 - nt_pix_clk + u_ov5640/coms2_reg_config/clk_20k_regdiv - USCM_84_117/CLK_USCM + USCM_84_121/CLK_USCM td 0.000 - 4.621 + 4.901 r - clkbufg_2/gopclkbufg/CLKOUT + u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - net (fanout=1635) - 0.895 - 5.516 + net (fanout=19) + 0.925 + 5.826 - ntclkbufg_2 + u_ov5640/coms2_reg_config/clock_20k - CLMA_174_52/CLK + CLMS_78_13/CLK r - udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[3]/opit_0_A2Q21/CLK + u_ov5640/coms2_reg_config/reg_index[4]/opit_0_inv_A2Q21/CLK - CLMA_174_52/Q1 + CLMS_78_13/Q2 tco - 0.180 - 5.696 - f - udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[3]/opit_0_A2Q21/Q1 + 0.183 + 6.009 + r + u_ov5640/coms2_reg_config/reg_index[4]/opit_0_inv_A2Q21/Q0 - net (fanout=2) - 0.059 - 5.755 + net (fanout=4) + 0.199 + 6.208 - udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d [3] + u_ov5640/coms2_reg_config/reg_index [3] - CLMS_174_53/C4 + DRM_82_4/ADB0[8] - f - udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr[4]/opit_0_A2Q21/I04 + r + u_ov5640/coms2_reg_config/reg_data/iGopDrm/ADB0[8]
- +
Location Delay Type @@ -129826,7 +134049,7 @@ Logical Resource - Clock clk_720p60Hz (rising edge) + Clock clk_20k (rising edge) 0.000 0.000 @@ -129882,82 +134105,82 @@ _N69 - PLL_158_55/CLK_OUT0 + PLL_158_55/CLK_OUT3 td - 0.083 - 2.197 + 0.088 + 2.202 r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 + u_sys_pll/u_pll_e3/goppll/CLKOUT3 - net (fanout=2) + net (fanout=1) 0.614 - 2.811 + 2.816 - rd3_clk + clk_25m - USCM_84_154/CLK_USCM + USCM_84_114/CLK_USCM td 0.000 - 2.811 + 2.816 r - USCMROUTE_0/CLKOUT + clkbufg_8/gopclkbufg/CLKOUT - net (fanout=1) - 1.131 - 3.942 + net (fanout=26) + 0.925 + 3.741 - ntR3907 + ntclkbufg_8 - PLL_158_303/CLK_OUT1 - td - 0.079 - 4.021 + CLMA_122_12/Q1 + tco + 0.224 + 3.965 r - U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q - net (fanout=2) - 0.932 - 4.953 + net (fanout=3) + 1.398 + 5.363 - nt_pix_clk + u_ov5640/coms2_reg_config/clk_20k_regdiv - USCM_84_117/CLK_USCM + USCM_84_121/CLK_USCM td 0.000 - 4.953 + 5.363 r - clkbufg_2/gopclkbufg/CLKOUT + u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - net (fanout=1635) - 0.925 - 5.878 + net (fanout=19) + 0.972 + 6.335 - ntclkbufg_2 + u_ov5640/coms2_reg_config/clock_20k - CLMS_174_53/CLK + DRM_82_4/CLKB[0] r - udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr[4]/opit_0_A2Q21/CLK + u_ov5640/coms2_reg_config/reg_data/iGopDrm/CLKB[0] clock pessimism - -0.347 - 5.531 + -0.473 + 5.862 @@ -129965,15 +134188,15 @@ clock uncertainty 0.000 - 5.531 + 5.862 Hold time - -0.028 - 5.503 + 0.061 + 5.923 @@ -129982,27 +134205,27 @@ - 0.252 + 0.289 0 - 1 - udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[4]/opit_0/CLK - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/DA0[4] + 5 + u_ov5640/coms2_reg_config/reg_index[8]/opit_0_inv_A2Q21/CLK + u_ov5640/coms2_reg_config/reg_data/iGopDrm/ADA_CAS - eth_rxc - eth_rxc + clk_20k + clk_20k rise-rise - 0.019 - 5.650 - 6.734 - -1.065 + 0.028 + 5.830 + 6.331 + -0.473 0.000 - 0.573 - 0.183 (31.9%) - 0.390 (68.1%) + 0.386 + 0.182 (47.2%) + 0.204 (52.8%) - Path #22: hold slack is 0.252(MET) + Path #33: hold slack is 0.289(MET) -
+
Location Delay Type @@ -130012,7 +134235,7 @@ Logical Resource - Clock eth_rxc (rising edge) + Clock clk_20k (rising edge) 0.000 0.000 @@ -130020,121 +134243,153 @@ - F14 + P20 0.000 0.000 r - eth_rxc (port) + clk (port) net (fanout=1) - 0.057 - 0.057 + 0.074 + 0.074 - eth_rxc + clk - IOBD_240_376/DIN + IOBS_LR_328_209/DIN td - 0.735 - 0.792 + 1.285 + 1.359 r - eth_rxc_ibuf/opit_0/O + clk_ibuf/opit_0/O net (fanout=1) 0.000 - 0.792 + 1.359 - eth_rxc_ibuf/ntD + clk_ibuf/ntD - IOL_243_374/INCK + IOL_327_210/INCK td 0.038 - 0.830 + 1.397 r - eth_rxc_ibuf/opit_1/INCK + clk_ibuf/opit_1/INCK net (fanout=1) - 0.363 - 1.193 + 0.463 + 1.860 - _N66 + _N69 - IOCKDLY_237_367/CLK_OUT + PLL_158_55/CLK_OUT3 td - 2.069 - 3.262 + 0.083 + 1.943 r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT + u_sys_pll/u_pll_e3/goppll/CLKOUT3 net (fanout=1) - 1.493 - 4.755 + 0.603 + 2.546 - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf + clk_25m - USCM_84_109/CLK_USCM + USCM_84_114/CLK_USCM td 0.000 - 4.755 + 2.546 r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT + clkbufg_8/gopclkbufg/CLKOUT - net (fanout=1861) + net (fanout=26) 0.895 - 5.650 + 3.441 - gmii_clk + ntclkbufg_8 + + + CLMA_122_12/Q1 + tco + 0.184 + 3.625 + r + u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q + + + + net (fanout=3) + 1.276 + 4.901 + + u_ov5640/coms2_reg_config/clk_20k_regdiv + + + USCM_84_121/CLK_USCM + td + 0.000 + 4.901 + r + u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + + + + net (fanout=19) + 0.929 + 5.830 + + u_ov5640/coms2_reg_config/clock_20k - CLMA_210_200/CLK + CLMS_78_17/CLK r - udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[4]/opit_0/CLK + u_ov5640/coms2_reg_config/reg_index[8]/opit_0_inv_A2Q21/CLK - CLMA_210_200/Q2 + CLMS_78_17/Q3 tco - 0.183 - 5.833 + 0.182 + 6.012 r - udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[4]/opit_0/Q + u_ov5640/coms2_reg_config/reg_index[8]/opit_0_inv_A2Q21/Q1 - net (fanout=1) - 0.390 - 6.223 + net (fanout=5) + 0.204 + 6.216 - udp_osd_inst/eth_udp_inst/rec_data [4] + u_ov5640/coms2_reg_config/reg_index [8] - DRM_234_192/DA0[4] + DRM_82_4/ADA_CAS r - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/DA0[4] + u_ov5640/coms2_reg_config/reg_data/iGopDrm/ADA_CAS
- +
Location Delay Type @@ -130144,7 +134399,7 @@ Logical Resource - Clock eth_rxc (rising edge) + Clock clk_20k (rising edge) 0.000 0.000 @@ -130152,114 +134407,146 @@ - F14 + P20 0.000 0.000 r - eth_rxc (port) + clk (port) net (fanout=1) - 0.057 - 0.057 + 0.074 + 0.074 - eth_rxc + clk - IOBD_240_376/DIN + IOBS_LR_328_209/DIN td - 0.861 - 0.918 + 1.504 + 1.578 r - eth_rxc_ibuf/opit_0/O + clk_ibuf/opit_0/O net (fanout=1) 0.000 - 0.918 + 1.578 - eth_rxc_ibuf/ntD + clk_ibuf/ntD - IOL_243_374/INCK + IOL_327_210/INCK td 0.058 - 0.976 + 1.636 r - eth_rxc_ibuf/opit_1/INCK + clk_ibuf/opit_1/INCK net (fanout=1) - 0.370 - 1.346 + 0.478 + 2.114 - _N66 + _N69 - IOCKDLY_237_367/CLK_OUT + PLL_158_55/CLK_OUT3 td - 2.942 - 4.288 + 0.088 + 2.202 r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT + u_sys_pll/u_pll_e3/goppll/CLKOUT3 net (fanout=1) - 1.521 - 5.809 + 0.614 + 2.816 - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf + clk_25m - USCM_84_109/CLK_USCM + USCM_84_114/CLK_USCM td 0.000 - 5.809 + 2.816 r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT + clkbufg_8/gopclkbufg/CLKOUT - net (fanout=1861) + net (fanout=26) 0.925 - 6.734 + 3.741 - gmii_clk + ntclkbufg_8 + + + CLMA_122_12/Q1 + tco + 0.224 + 3.965 + r + u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q + + + + net (fanout=3) + 1.398 + 5.363 + + u_ov5640/coms2_reg_config/clk_20k_regdiv + + + USCM_84_121/CLK_USCM + td + 0.000 + 5.363 + r + u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + + + + net (fanout=19) + 0.968 + 6.331 + + u_ov5640/coms2_reg_config/clock_20k - DRM_234_192/CLKA[0] + DRM_82_4/CLKA[0] r - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] + u_ov5640/coms2_reg_config/reg_data/iGopDrm/CLKA[0] clock pessimism - -1.065 - 5.669 + -0.473 + 5.858 clock uncertainty - 0.200 - 5.869 + 0.000 + 5.858 Hold time - 0.102 - 5.971 + 0.069 + 5.927 @@ -130268,27 +134555,27 @@ - 0.254 + 0.383 0 - 1 - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/D + 8 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[0] - cmos2_pclk - cmos2_pclk + ioclk1 + ioclk1 rise-rise - 0.019 - 3.512 - 3.861 - -0.330 + 0.009 + 4.513 + 4.916 + -0.394 0.000 - 0.462 - 0.182 (39.4%) - 0.280 (60.6%) + 0.339 + 0.339 (100.0%) + 0.000 (0.0%) - Path #23: hold slack is 0.254(MET) + Path #34: hold slack is 0.383(MET) -
+
Location Delay Type @@ -130298,7 +134585,7 @@ Logical Resource - Clock cmos2_pclk (rising edge) + Clock ioclk1 (rising edge) 0.000 0.000 @@ -130306,105 +134593,153 @@ - W6 + P20 0.000 0.000 r - cmos2_pclk (port) + clk (port) net (fanout=1) - 0.071 - 0.071 + 0.074 + 0.074 - cmos2_pclk + clk - IOBD_37_0/DIN + IOBS_LR_328_209/DIN td - 0.735 - 0.806 + 1.285 + 1.359 r - cmos2_pclk_ibuf/opit_0/O + clk_ibuf/opit_0/O net (fanout=1) 0.000 - 0.806 + 1.359 - cmos2_pclk_ibuf/ntD + clk_ibuf/ntD - IOL_39_6/RX_DATA_DD + IOL_327_210/INCK td - 0.066 - 0.872 + 0.038 + 1.397 r - cmos2_pclk_ibuf/opit_1/OUT + clk_ibuf/opit_1/INCK net (fanout=1) - 1.745 - 2.617 + 0.463 + 1.860 - nt_cmos2_pclk + _N69 - USCM_84_118/CLK_USCM + PLL_158_55/CLK_OUT1 + td + 0.074 + 1.934 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 0.603 + 2.537 + + ddr_clk + + + USCM_84_113/CLK_USCM td 0.000 - 2.617 + 2.537 r - clkbufg_6/gopclkbufg/CLKOUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=118) - 0.895 - 3.512 + net (fanout=71) + 0.981 + 3.518 - ntclkbufg_6 + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.089 + 3.607 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 0.669 + 4.276 + + clkout0_wl_0 + + + IOCKGATE_6_188/OUT + td + 0.200 + 4.476 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT + + + + net (fanout=28) + 0.037 + 4.513 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] - CLMS_150_53/CLK + DQSL_6_152/CLK_IO r - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - CLMS_150_53/Q3 + DQSL_6_152/IFIFO_RADDR[0] tco - 0.182 - 3.694 + 0.339 + 4.852 r - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/opit_0/Q + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[0] - net (fanout=1) - 0.280 - 3.974 + net (fanout=8) + 0.000 + 4.852 - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr1 [4] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [0] - CLMA_154_53/M1 + IOL_7_162/IFIFO_RADDR[0] r - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/D + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[0]
- +
Location Delay Type @@ -130414,7 +134749,7 @@ Logical Resource - Clock cmos2_pclk (rising edge) + Clock ioclk1 (rising edge) 0.000 0.000 @@ -130422,98 +134757,146 @@ - W6 + P20 0.000 0.000 r - cmos2_pclk (port) + clk (port) net (fanout=1) - 0.071 - 0.071 + 0.074 + 0.074 - cmos2_pclk + clk - IOBD_37_0/DIN + IOBS_LR_328_209/DIN td - 0.861 - 0.932 + 1.504 + 1.578 r - cmos2_pclk_ibuf/opit_0/O + clk_ibuf/opit_0/O net (fanout=1) 0.000 - 0.932 + 1.578 - cmos2_pclk_ibuf/ntD + clk_ibuf/ntD - IOL_39_6/RX_DATA_DD + IOL_327_210/INCK td - 0.096 - 1.028 + 0.058 + 1.636 r - cmos2_pclk_ibuf/opit_1/OUT + clk_ibuf/opit_1/INCK net (fanout=1) - 1.908 - 2.936 + 0.478 + 2.114 - nt_cmos2_pclk + _N69 - USCM_84_118/CLK_USCM + PLL_158_55/CLK_OUT1 + td + 0.079 + 2.193 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 0.614 + 2.807 + + ddr_clk + + + USCM_84_113/CLK_USCM td 0.000 - 2.936 + 2.807 r - clkbufg_6/gopclkbufg/CLKOUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=118) - 0.925 - 3.861 + net (fanout=71) + 1.019 + 3.826 - ntclkbufg_6 + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.094 + 3.920 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 0.682 + 4.602 + + clkout0_wl_0 + + + IOCKGATE_6_188/OUT + td + 0.268 + 4.870 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT + + + + net (fanout=28) + 0.046 + 4.916 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] - CLMA_154_53/CLK + IOL_7_162/CLK_IO r - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[4]/opit_0/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK clock pessimism - -0.330 - 3.531 + -0.394 + 4.522 clock uncertainty - 0.200 - 3.731 + 0.000 + 4.522 Hold time - -0.011 - 3.720 + -0.053 + 4.469 @@ -130522,27 +134905,27 @@ - 0.254 + 0.383 0 - 1 - udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[3]/opit_0/CLK - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/DA0[3] + 8 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[1] - eth_rxc - eth_rxc + ioclk1 + ioclk1 rise-rise - 0.019 - 5.650 - 6.734 - -1.065 + 0.009 + 4.513 + 4.916 + -0.394 0.000 - 0.575 - 0.182 (31.7%) - 0.393 (68.3%) + 0.339 + 0.339 (100.0%) + 0.000 (0.0%) - Path #24: hold slack is 0.254(MET) + Path #35: hold slack is 0.383(MET) -
+
Location Delay Type @@ -130552,7 +134935,7 @@ Logical Resource - Clock eth_rxc (rising edge) + Clock ioclk1 (rising edge) 0.000 0.000 @@ -130560,121 +134943,153 @@ - F14 + P20 0.000 0.000 r - eth_rxc (port) + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.285 + 1.359 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.359 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.038 + 1.397 + r + clk_ibuf/opit_1/INCK net (fanout=1) - 0.057 - 0.057 + 0.463 + 1.860 - eth_rxc + _N69 - IOBD_240_376/DIN + PLL_158_55/CLK_OUT1 td - 0.735 - 0.792 + 0.074 + 1.934 r - eth_rxc_ibuf/opit_0/O + u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=1) - 0.000 - 0.792 + net (fanout=2) + 0.603 + 2.537 - eth_rxc_ibuf/ntD + ddr_clk - IOL_243_374/INCK + USCM_84_113/CLK_USCM td - 0.038 - 0.830 + 0.000 + 2.537 r - eth_rxc_ibuf/opit_1/INCK + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=1) - 0.363 - 1.193 + net (fanout=71) + 0.981 + 3.518 - _N66 + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - IOCKDLY_237_367/CLK_OUT + PLL_158_199/CLK_OUT0_WL td - 2.069 - 3.262 + 0.089 + 3.607 r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - net (fanout=1) - 1.493 - 4.755 + net (fanout=3) + 0.669 + 4.276 - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf + clkout0_wl_0 - USCM_84_109/CLK_USCM + IOCKGATE_6_188/OUT td - 0.000 - 4.755 + 0.200 + 4.476 r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT - net (fanout=1861) - 0.895 - 5.650 + net (fanout=28) + 0.037 + 4.513 - gmii_clk + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] - CLMA_210_201/CLK + DQSL_6_152/CLK_IO r - udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[3]/opit_0/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - CLMA_210_201/Q0 + DQSL_6_152/IFIFO_RADDR[1] tco - 0.182 - 5.832 + 0.339 + 4.852 r - udp_osd_inst/eth_udp_inst/u_eth_ctrl/rec_data[3]/opit_0/Q + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[1] - net (fanout=1) - 0.393 - 6.225 + net (fanout=8) + 0.000 + 4.852 - udp_osd_inst/eth_udp_inst/rec_data [3] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [1] - DRM_234_192/DA0[3] + IOL_7_162/IFIFO_RADDR[1] r - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/DA0[3] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[1]
- +
Location Delay Type @@ -130684,7 +135099,7 @@ Logical Resource - Clock eth_rxc (rising edge) + Clock ioclk1 (rising edge) 0.000 0.000 @@ -130692,114 +135107,146 @@ - F14 + P20 0.000 0.000 r - eth_rxc (port) + clk (port) net (fanout=1) - 0.057 - 0.057 + 0.074 + 0.074 - eth_rxc + clk - IOBD_240_376/DIN + IOBS_LR_328_209/DIN td - 0.861 - 0.918 + 1.504 + 1.578 r - eth_rxc_ibuf/opit_0/O + clk_ibuf/opit_0/O net (fanout=1) 0.000 - 0.918 + 1.578 - eth_rxc_ibuf/ntD + clk_ibuf/ntD - IOL_243_374/INCK + IOL_327_210/INCK td 0.058 - 0.976 + 1.636 r - eth_rxc_ibuf/opit_1/INCK + clk_ibuf/opit_1/INCK net (fanout=1) - 0.370 - 1.346 + 0.478 + 2.114 - _N66 + _N69 - IOCKDLY_237_367/CLK_OUT + PLL_158_55/CLK_OUT1 td - 2.942 - 4.288 + 0.079 + 2.193 r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT + u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=1) - 1.521 - 5.809 + net (fanout=2) + 0.614 + 2.807 - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf + ddr_clk - USCM_84_109/CLK_USCM + USCM_84_113/CLK_USCM td 0.000 - 5.809 + 2.807 r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=1861) - 0.925 - 6.734 + net (fanout=71) + 1.019 + 3.826 - gmii_clk + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.094 + 3.920 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 0.682 + 4.602 + + clkout0_wl_0 + + + IOCKGATE_6_188/OUT + td + 0.268 + 4.870 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT + + + + net (fanout=28) + 0.046 + 4.916 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] - DRM_234_192/CLKA[0] + IOL_7_162/CLK_IO r - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK clock pessimism - -1.065 - 5.669 + -0.394 + 4.522 clock uncertainty - 0.200 - 5.869 + 0.000 + 4.522 Hold time - 0.102 - 5.971 + -0.053 + 4.469 @@ -130808,27 +135255,27 @@ - 0.255 + 0.383 0 - 2 - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[7]/opit_0/CLK - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[8]/opit_0_A2Q21/I01 + 8 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[2] - eth_rxc - eth_rxc + ioclk1 + ioclk1 rise-rise - 0.019 - 5.650 - 6.734 - -1.065 + 0.009 + 4.513 + 4.916 + -0.394 0.000 - 0.381 - 0.182 (47.8%) - 0.199 (52.2%) + 0.339 + 0.339 (100.0%) + 0.000 (0.0%) - Path #25: hold slack is 0.255(MET) + Path #36: hold slack is 0.383(MET) -
+
Location Delay Type @@ -130838,7 +135285,7 @@ Logical Resource - Clock eth_rxc (rising edge) + Clock ioclk1 (rising edge) 0.000 0.000 @@ -130846,121 +135293,153 @@ - F14 + P20 0.000 0.000 r - eth_rxc (port) + clk (port) net (fanout=1) - 0.057 - 0.057 + 0.074 + 0.074 - eth_rxc + clk - IOBD_240_376/DIN + IOBS_LR_328_209/DIN td - 0.735 - 0.792 + 1.285 + 1.359 r - eth_rxc_ibuf/opit_0/O + clk_ibuf/opit_0/O net (fanout=1) 0.000 - 0.792 + 1.359 - eth_rxc_ibuf/ntD + clk_ibuf/ntD - IOL_243_374/INCK + IOL_327_210/INCK td 0.038 - 0.830 + 1.397 r - eth_rxc_ibuf/opit_1/INCK + clk_ibuf/opit_1/INCK net (fanout=1) - 0.363 - 1.193 + 0.463 + 1.860 - _N66 + _N69 - IOCKDLY_237_367/CLK_OUT + PLL_158_55/CLK_OUT1 td - 2.069 - 3.262 + 0.074 + 1.934 r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT + u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=1) - 1.493 - 4.755 + net (fanout=2) + 0.603 + 2.537 - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf + ddr_clk - USCM_84_109/CLK_USCM + USCM_84_113/CLK_USCM td 0.000 - 4.755 + 2.537 r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=1861) - 0.895 - 5.650 + net (fanout=71) + 0.981 + 3.518 - gmii_clk + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.089 + 3.607 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 0.669 + 4.276 + + clkout0_wl_0 + + + IOCKGATE_6_188/OUT + td + 0.200 + 4.476 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT + + + + net (fanout=28) + 0.037 + 4.513 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] - CLMA_182_209/CLK + DQSL_6_152/CLK_IO r - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[7]/opit_0/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - CLMA_182_209/Q3 + DQSL_6_152/IFIFO_RADDR[2] tco - 0.182 - 5.832 + 0.339 + 4.852 r - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length[7]/opit_0/Q + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[2] - net (fanout=2) - 0.199 - 6.031 + net (fanout=8) + 0.000 + 4.852 - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/total_length [7] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [2] - CLMA_186_208/A1 + IOL_7_162/IFIFO_RADDR[2] r - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[8]/opit_0_A2Q21/I01 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[2]
- +
Location Delay Type @@ -130970,7 +135449,7 @@ Logical Resource - Clock eth_rxc (rising edge) + Clock ioclk1 (rising edge) 0.000 0.000 @@ -130978,114 +135457,146 @@ - F14 + P20 0.000 0.000 r - eth_rxc (port) + clk (port) net (fanout=1) - 0.057 - 0.057 + 0.074 + 0.074 - eth_rxc + clk - IOBD_240_376/DIN + IOBS_LR_328_209/DIN td - 0.861 - 0.918 + 1.504 + 1.578 r - eth_rxc_ibuf/opit_0/O + clk_ibuf/opit_0/O net (fanout=1) 0.000 - 0.918 + 1.578 - eth_rxc_ibuf/ntD + clk_ibuf/ntD - IOL_243_374/INCK + IOL_327_210/INCK td 0.058 - 0.976 + 1.636 r - eth_rxc_ibuf/opit_1/INCK + clk_ibuf/opit_1/INCK net (fanout=1) - 0.370 - 1.346 + 0.478 + 2.114 - _N66 + _N69 - IOCKDLY_237_367/CLK_OUT + PLL_158_55/CLK_OUT1 td - 2.942 - 4.288 + 0.079 + 2.193 r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/opit_0/CLKOUT + u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=1) - 1.521 - 5.809 + net (fanout=2) + 0.614 + 2.807 - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf + ddr_clk - USCM_84_109/CLK_USCM + USCM_84_113/CLK_USCM td 0.000 - 5.809 + 2.807 r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/gopclkbufg/CLKOUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=1861) - 0.925 - 6.734 + net (fanout=71) + 1.019 + 3.826 - gmii_clk + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.094 + 3.920 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 0.682 + 4.602 + + clkout0_wl_0 - CLMA_186_208/CLK + IOCKGATE_6_188/OUT + td + 0.268 + 4.870 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT + + + + net (fanout=28) + 0.046 + 4.916 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + + + IOL_7_162/CLK_IO r - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/icmp_data_length[8]/opit_0_A2Q21/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK clock pessimism - -1.065 - 5.669 + -0.394 + 4.522 clock uncertainty - 0.200 - 5.869 + 0.000 + 4.522 Hold time - -0.093 - 5.776 + -0.053 + 4.469 @@ -131094,27 +135605,27 @@ - 0.262 + 0.383 0 - 1 - u_ov5640/cmos2_8_16bit/pdata_i0[1]/opit_0/CLK - u_ov5640/cmos2_8_16bit/pdata_i1[1]/opit_0/D + 8 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[0] - cmos2_pclk - cmos2_pclk + ioclk0 + ioclk0 rise-rise - 0.019 - 3.512 - 3.861 - -0.330 + 0.009 + 4.513 + 4.916 + -0.394 0.000 - 0.470 - 0.236 (50.2%) - 0.234 (49.8%) + 0.339 + 0.339 (100.0%) + 0.000 (0.0%) - Path #26: hold slack is 0.262(MET) + Path #37: hold slack is 0.383(MET) -
+
Location Delay Type @@ -131124,113 +135635,161 @@ Logical Resource - Clock cmos2_pclk (rising edge) + Clock ioclk0 (rising edge) + + 0.000 + 0.000 + r + + + P20 + 0.000 0.000 r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk + + + IOBS_LR_328_209/DIN + td + 1.285 + 1.359 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.359 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.038 + 1.397 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.463 + 1.860 + _N69 - W6 - - 0.000 - 0.000 + PLL_158_55/CLK_OUT1 + td + 0.074 + 1.934 r - cmos2_pclk (port) + u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=1) - 0.071 - 0.071 + net (fanout=2) + 0.603 + 2.537 - cmos2_pclk + ddr_clk - IOBD_37_0/DIN + USCM_84_113/CLK_USCM td - 0.735 - 0.806 + 0.000 + 2.537 r - cmos2_pclk_ibuf/opit_0/O + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=1) - 0.000 - 0.806 + net (fanout=71) + 0.981 + 3.518 - cmos2_pclk_ibuf/ntD + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - IOL_39_6/RX_DATA_DD + PLL_158_199/CLK_OUT0_WL td - 0.066 - 0.872 + 0.089 + 3.607 r - cmos2_pclk_ibuf/opit_1/OUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - net (fanout=1) - 1.745 - 2.617 + net (fanout=3) + 0.669 + 4.276 - nt_cmos2_pclk + clkout0_wl_0 - USCM_84_118/CLK_USCM + IOCKGATE_6_312/OUT td - 0.000 - 2.617 + 0.200 + 4.476 r - clkbufg_6/gopclkbufg/CLKOUT + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT - net (fanout=118) - 0.895 - 3.512 + net (fanout=11) + 0.037 + 4.513 - ntclkbufg_6 + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] - CLMS_130_45/CLK + DQSL_6_276/CLK_IO r - u_ov5640/cmos2_8_16bit/pdata_i0[1]/opit_0/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - CLMS_130_45/Y2 + DQSL_6_276/IFIFO_RADDR[0] tco - 0.236 - 3.748 + 0.339 + 4.852 r - u_ov5640/cmos2_8_16bit/pdata_i0[1]/opit_0/Q + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[0] - net (fanout=1) - 0.234 - 3.982 + net (fanout=8) + 0.000 + 4.852 - u_ov5640/cmos2_8_16bit/pdata_i0 [1] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [0] - CLMA_134_52/M3 + IOL_7_285/IFIFO_RADDR[0] r - u_ov5640/cmos2_8_16bit/pdata_i1[1]/opit_0/D + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[0]
- +
Location Delay Type @@ -131240,7 +135799,7 @@ Logical Resource - Clock cmos2_pclk (rising edge) + Clock ioclk0 (rising edge) 0.000 0.000 @@ -131248,98 +135807,146 @@ - W6 + P20 0.000 0.000 r - cmos2_pclk (port) + clk (port) net (fanout=1) - 0.071 - 0.071 + 0.074 + 0.074 - cmos2_pclk + clk - IOBD_37_0/DIN + IOBS_LR_328_209/DIN td - 0.861 - 0.932 + 1.504 + 1.578 r - cmos2_pclk_ibuf/opit_0/O + clk_ibuf/opit_0/O net (fanout=1) 0.000 - 0.932 + 1.578 - cmos2_pclk_ibuf/ntD + clk_ibuf/ntD - IOL_39_6/RX_DATA_DD + IOL_327_210/INCK td - 0.096 - 1.028 + 0.058 + 1.636 r - cmos2_pclk_ibuf/opit_1/OUT + clk_ibuf/opit_1/INCK net (fanout=1) - 1.908 - 2.936 + 0.478 + 2.114 - nt_cmos2_pclk + _N69 - USCM_84_118/CLK_USCM + PLL_158_55/CLK_OUT1 + td + 0.079 + 2.193 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 0.614 + 2.807 + + ddr_clk + + + USCM_84_113/CLK_USCM td 0.000 - 2.936 + 2.807 r - clkbufg_6/gopclkbufg/CLKOUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=118) - 0.925 - 3.861 + net (fanout=71) + 1.019 + 3.826 - ntclkbufg_6 + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.094 + 3.920 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 0.682 + 4.602 + + clkout0_wl_0 + + + IOCKGATE_6_312/OUT + td + 0.268 + 4.870 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT + + + + net (fanout=11) + 0.046 + 4.916 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] - CLMA_134_52/CLK + IOL_7_285/CLK_IO r - u_ov5640/cmos2_8_16bit/pdata_i1[1]/opit_0/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK clock pessimism - -0.330 - 3.531 + -0.394 + 4.522 clock uncertainty - 0.200 - 3.731 + 0.000 + 4.522 Hold time - -0.011 - 3.720 + -0.053 + 4.469 @@ -131348,27 +135955,27 @@ - 0.263 + 0.383 0 - 1 - u_ov5640/cmos2_8_16bit/pdata_i2[0]/opit_0/CLK - u_ov5640/cmos2_8_16bit/image_data0[8]/opit_0/D + 8 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[1] - cmos2_pclk - cmos2_pclk + ioclk0 + ioclk0 rise-rise - 0.019 - 3.512 - 3.861 - -0.330 + 0.009 + 4.513 + 4.916 + -0.394 0.000 - 0.471 - 0.182 (38.6%) - 0.289 (61.4%) + 0.339 + 0.339 (100.0%) + 0.000 (0.0%) - Path #27: hold slack is 0.263(MET) + Path #38: hold slack is 0.383(MET) -
+
Location Delay Type @@ -131378,7 +135985,7 @@ Logical Resource - Clock cmos2_pclk (rising edge) + Clock ioclk0 (rising edge) 0.000 0.000 @@ -131386,105 +135993,153 @@ - W6 + P20 0.000 0.000 r - cmos2_pclk (port) + clk (port) net (fanout=1) - 0.071 - 0.071 + 0.074 + 0.074 - cmos2_pclk + clk - IOBD_37_0/DIN + IOBS_LR_328_209/DIN td - 0.735 - 0.806 + 1.285 + 1.359 r - cmos2_pclk_ibuf/opit_0/O + clk_ibuf/opit_0/O net (fanout=1) 0.000 - 0.806 + 1.359 - cmos2_pclk_ibuf/ntD + clk_ibuf/ntD - IOL_39_6/RX_DATA_DD + IOL_327_210/INCK td - 0.066 - 0.872 + 0.038 + 1.397 r - cmos2_pclk_ibuf/opit_1/OUT + clk_ibuf/opit_1/INCK net (fanout=1) - 1.745 - 2.617 + 0.463 + 1.860 - nt_cmos2_pclk + _N69 - USCM_84_118/CLK_USCM + PLL_158_55/CLK_OUT1 + td + 0.074 + 1.934 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 0.603 + 2.537 + + ddr_clk + + + USCM_84_113/CLK_USCM td 0.000 - 2.617 + 2.537 r - clkbufg_6/gopclkbufg/CLKOUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=118) - 0.895 - 3.512 + net (fanout=71) + 0.981 + 3.518 - ntclkbufg_6 + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.089 + 3.607 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 0.669 + 4.276 + + clkout0_wl_0 + + + IOCKGATE_6_312/OUT + td + 0.200 + 4.476 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT - CLMS_130_53/CLK + + net (fanout=11) + 0.037 + 4.513 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + + + DQSL_6_276/CLK_IO r - u_ov5640/cmos2_8_16bit/pdata_i2[0]/opit_0/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - CLMS_130_53/Q3 + DQSL_6_276/IFIFO_RADDR[1] tco - 0.182 - 3.694 + 0.339 + 4.852 r - u_ov5640/cmos2_8_16bit/pdata_i2[0]/opit_0/Q + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[1] - net (fanout=1) - 0.289 - 3.983 + net (fanout=8) + 0.000 + 4.852 - u_ov5640/cmos2_8_16bit/pdata_i2 [0] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [1] - CLMA_138_56/M2 + IOL_7_285/IFIFO_RADDR[1] r - u_ov5640/cmos2_8_16bit/image_data0[8]/opit_0/D + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[1]
- +
Location Delay Type @@ -131494,7 +136149,7 @@ Logical Resource - Clock cmos2_pclk (rising edge) + Clock ioclk0 (rising edge) 0.000 0.000 @@ -131502,98 +136157,146 @@ - W6 + P20 0.000 0.000 r - cmos2_pclk (port) + clk (port) net (fanout=1) - 0.071 - 0.071 + 0.074 + 0.074 - cmos2_pclk + clk - IOBD_37_0/DIN + IOBS_LR_328_209/DIN td - 0.861 - 0.932 + 1.504 + 1.578 r - cmos2_pclk_ibuf/opit_0/O + clk_ibuf/opit_0/O net (fanout=1) 0.000 - 0.932 + 1.578 - cmos2_pclk_ibuf/ntD + clk_ibuf/ntD - IOL_39_6/RX_DATA_DD + IOL_327_210/INCK td - 0.096 - 1.028 + 0.058 + 1.636 r - cmos2_pclk_ibuf/opit_1/OUT + clk_ibuf/opit_1/INCK net (fanout=1) - 1.908 - 2.936 + 0.478 + 2.114 - nt_cmos2_pclk + _N69 - USCM_84_118/CLK_USCM + PLL_158_55/CLK_OUT1 + td + 0.079 + 2.193 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 0.614 + 2.807 + + ddr_clk + + + USCM_84_113/CLK_USCM td 0.000 - 2.936 + 2.807 r - clkbufg_6/gopclkbufg/CLKOUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=118) - 0.925 - 3.861 + net (fanout=71) + 1.019 + 3.826 - ntclkbufg_6 + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - CLMA_138_56/CLK + PLL_158_199/CLK_OUT0_WL + td + 0.094 + 3.920 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 0.682 + 4.602 + + clkout0_wl_0 + + + IOCKGATE_6_312/OUT + td + 0.268 + 4.870 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT + + + + net (fanout=11) + 0.046 + 4.916 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + + + IOL_7_285/CLK_IO r - u_ov5640/cmos2_8_16bit/image_data0[8]/opit_0/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK clock pessimism - -0.330 - 3.531 + -0.394 + 4.522 clock uncertainty - 0.200 - 3.731 + 0.000 + 4.522 Hold time - -0.011 - 3.720 + -0.053 + 4.469 @@ -131602,27 +136305,27 @@ - 0.269 + 0.383 0 - 6 - u_ov5640/coms2_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK - u_ov5640/coms2_reg_config/reg_data/iGopDrm/ADA0[5] + 8 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[2] - clk_20k - clk_20k + ioclk0 + ioclk0 rise-rise - 0.019 - 5.644 - 6.109 - -0.446 + 0.009 + 4.513 + 4.916 + -0.394 0.000 - 0.415 - 0.182 (43.9%) - 0.233 (56.1%) + 0.339 + 0.339 (100.0%) + 0.000 (0.0%) - Path #28: hold slack is 0.269(MET) + Path #39: hold slack is 0.383(MET) -
+
Location Delay Type @@ -131632,7 +136335,7 @@ Logical Resource - Clock clk_20k (rising edge) + Clock ioclk0 (rising edge) 0.000 0.000 @@ -131688,105 +136391,105 @@ _N69 - PLL_158_55/CLK_OUT3 + PLL_158_55/CLK_OUT1 td - 0.083 - 1.943 + 0.074 + 1.934 r - u_sys_pll/u_pll_e3/goppll/CLKOUT3 + u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=1) + net (fanout=2) 0.603 - 2.546 + 2.537 - clk_25m + ddr_clk - USCM_84_114/CLK_USCM + USCM_84_113/CLK_USCM td 0.000 - 2.546 + 2.537 r - clkbufg_7/gopclkbufg/CLKOUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=26) - 0.895 - 3.441 + net (fanout=71) + 0.981 + 3.518 - ntclkbufg_7 + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - CLMA_182_25/Q1 - tco - 0.184 - 3.625 + PLL_158_199/CLK_OUT0_WL + td + 0.089 + 3.607 r - u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) - 1.124 - 4.749 + 0.669 + 4.276 - u_ov5640/coms2_reg_config/clk_20k_regdiv + clkout0_wl_0 - USCM_84_120/CLK_USCM + IOCKGATE_6_312/OUT td - 0.000 - 4.749 + 0.200 + 4.476 r - u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT - net (fanout=19) - 0.895 - 5.644 + net (fanout=11) + 0.037 + 4.513 - u_ov5640/coms2_reg_config/clock_20k + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] - CLMA_182_32/CLK + DQSL_6_276/CLK_IO r - u_ov5640/coms2_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - CLMA_182_32/Q0 + DQSL_6_276/IFIFO_RADDR[2] tco - 0.182 - 5.826 + 0.339 + 4.852 r - u_ov5640/coms2_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/Q + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[2] - net (fanout=6) - 0.233 - 6.059 + net (fanout=8) + 0.000 + 4.852 - u_ov5640/coms2_reg_config/reg_index [0] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [2] - DRM_178_24/ADA0[5] + IOL_7_285/IFIFO_RADDR[2] r - u_ov5640/coms2_reg_config/reg_data/iGopDrm/ADA0[5] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[2]
- +
Location Delay Type @@ -131796,7 +136499,7 @@ Logical Resource - Clock clk_20k (rising edge) + Clock ioclk0 (rising edge) 0.000 0.000 @@ -131852,82 +136555,82 @@ _N69 - PLL_158_55/CLK_OUT3 + PLL_158_55/CLK_OUT1 td - 0.088 - 2.202 + 0.079 + 2.193 r - u_sys_pll/u_pll_e3/goppll/CLKOUT3 + u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=1) + net (fanout=2) 0.614 - 2.816 + 2.807 - clk_25m + ddr_clk - USCM_84_114/CLK_USCM + USCM_84_113/CLK_USCM td 0.000 - 2.816 + 2.807 r - clkbufg_7/gopclkbufg/CLKOUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=26) - 0.925 - 3.741 + net (fanout=71) + 1.019 + 3.826 - ntclkbufg_7 + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - CLMA_182_25/Q1 - tco - 0.224 - 3.965 + PLL_158_199/CLK_OUT0_WL + td + 0.094 + 3.920 r - u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL net (fanout=3) - 1.219 - 5.184 + 0.682 + 4.602 - u_ov5640/coms2_reg_config/clk_20k_regdiv + clkout0_wl_0 - USCM_84_120/CLK_USCM + IOCKGATE_6_312/OUT td - 0.000 - 5.184 + 0.268 + 4.870 r - u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT - net (fanout=19) - 0.925 - 6.109 + net (fanout=11) + 0.046 + 4.916 - u_ov5640/coms2_reg_config/clock_20k + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] - DRM_178_24/CLKA[0] + IOL_7_285/CLK_IO r - u_ov5640/coms2_reg_config/reg_data/iGopDrm/CLKA[0] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK clock pessimism - -0.446 - 5.663 + -0.394 + 4.522 @@ -131935,15 +136638,15 @@ clock uncertainty 0.000 - 5.663 + 4.522 Hold time - 0.127 - 5.790 + -0.053 + 4.469 @@ -131952,27 +136655,27 @@ - 0.271 + 0.388 0 - 6 - u_ov5640/coms1_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK - u_ov5640/coms1_reg_config/reg_data/iGopDrm/ADA0[5] + 3 + u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK + u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/D - clk_20k - clk_20k + clk_25m + clk_25m rise-rise - 0.019 - 5.784 - 6.274 - -0.471 + 0.001 + 3.441 + 3.741 + -0.299 0.000 - 0.417 - 0.182 (43.6%) - 0.235 (56.4%) + 0.378 + 0.184 (48.7%) + 0.194 (51.3%) - Path #29: hold slack is 0.271(MET) + Path #40: hold slack is 0.388(MET) -
+
Location Delay Type @@ -131982,7 +136685,7 @@ Logical Resource - Clock clk_20k (rising edge) + Clock clk_25m (rising edge) 0.000 0.000 @@ -132059,7 +136762,7 @@ 0.000 2.546 r - clkbufg_7/gopclkbufg/CLKOUT + clkbufg_8/gopclkbufg/CLKOUT @@ -132067,76 +136770,44 @@ 0.895 3.441 - ntclkbufg_7 - - - CLMA_182_12/Q1 - tco - 0.184 - 3.625 - r - u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q - - - - net (fanout=3) - 1.264 - 4.889 - - u_ov5640/coms1_reg_config/clk_20k_regdiv - - - USCM_84_119/CLK_USCM - td - 0.000 - 4.889 - r - u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - - - - net (fanout=19) - 0.895 - 5.784 - - u_ov5640/coms1_reg_config/clock_20k + ntclkbufg_8 - CLMA_182_13/CLK + CLMS_122_9/CLK r - u_ov5640/coms1_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/CLK + u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK - CLMA_182_13/Q0 + CLMS_122_9/Q1 tco - 0.182 - 5.966 + 0.184 + 3.625 r - u_ov5640/coms1_reg_config/reg_index[0]/opit_0_inv_L5Q_perm/Q + u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q - net (fanout=6) - 0.235 - 6.201 + net (fanout=3) + 0.194 + 3.819 - u_ov5640/coms1_reg_config/reg_index [0] + u_ov5640/coms1_reg_config/clk_20k_regdiv - DRM_178_4/ADA0[5] + CLMS_122_9/M0 r - u_ov5640/coms1_reg_config/reg_data/iGopDrm/ADA0[5] + u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/D
- +
Location Delay Type @@ -132146,7 +136817,7 @@ Logical Resource - Clock clk_20k (rising edge) + Clock clk_25m (rising edge) 0.000 0.000 @@ -132223,7 +136894,7 @@ 0.000 2.816 r - clkbufg_7/gopclkbufg/CLKOUT + clkbufg_8/gopclkbufg/CLKOUT @@ -132231,53 +136902,21 @@ 0.925 3.741 - ntclkbufg_7 - - - CLMA_182_12/Q1 - tco - 0.224 - 3.965 - r - u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q - - - - net (fanout=3) - 1.384 - 5.349 - - u_ov5640/coms1_reg_config/clk_20k_regdiv - - - USCM_84_119/CLK_USCM - td - 0.000 - 5.349 - r - u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - - - - net (fanout=19) - 0.925 - 6.274 - - u_ov5640/coms1_reg_config/clock_20k + ntclkbufg_8 - DRM_178_4/CLKA[0] + CLMS_122_9/CLK r - u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKA[0] + u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/CLK clock pessimism - -0.471 - 5.803 + -0.299 + 3.442 @@ -132285,15 +136924,15 @@ clock uncertainty 0.000 - 5.803 + 3.442 Hold time - 0.127 - 5.930 + -0.011 + 3.431 @@ -132302,27 +136941,27 @@ - 0.300 + 0.411 0 - 4 - u_ov5640/coms1_reg_config/reg_index[4]/opit_0_inv_A2Q21/CLK - u_ov5640/coms1_reg_config/reg_data/iGopDrm/ADB0[8] + 3 + u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/CLK + u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite/opit_0_inv/D - clk_20k - clk_20k + clk_25m + clk_25m rise-rise - 0.019 - 5.784 - 6.274 - -0.471 + 0.001 + 3.441 + 3.741 + -0.299 0.000 - 0.380 - 0.183 (48.2%) - 0.197 (51.8%) + 0.401 + 0.184 (45.9%) + 0.217 (54.1%) - Path #30: hold slack is 0.300(MET) + Path #41: hold slack is 0.411(MET) -
+
Location Delay Type @@ -132332,7 +136971,7 @@ Logical Resource - Clock clk_20k (rising edge) + Clock clk_25m (rising edge) 0.000 0.000 @@ -132409,7 +137048,7 @@ 0.000 2.546 r - clkbufg_7/gopclkbufg/CLKOUT + clkbufg_8/gopclkbufg/CLKOUT @@ -132417,76 +137056,44 @@ 0.895 3.441 - ntclkbufg_7 - - - CLMA_182_12/Q1 - tco - 0.184 - 3.625 - r - u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q - - - - net (fanout=3) - 1.264 - 4.889 - - u_ov5640/coms1_reg_config/clk_20k_regdiv - - - USCM_84_119/CLK_USCM - td - 0.000 - 4.889 - r - u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - - - - net (fanout=19) - 0.895 - 5.784 - - u_ov5640/coms1_reg_config/clock_20k + ntclkbufg_8 - CLMS_174_13/CLK + CLMA_122_12/CLK r - u_ov5640/coms1_reg_config/reg_index[4]/opit_0_inv_A2Q21/CLK + u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/CLK - CLMS_174_13/Q2 + CLMA_122_12/Q1 tco - 0.183 - 5.967 + 0.184 + 3.625 r - u_ov5640/coms1_reg_config/reg_index[4]/opit_0_inv_A2Q21/Q0 + u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q - net (fanout=4) - 0.197 - 6.164 + net (fanout=3) + 0.217 + 3.842 - u_ov5640/coms1_reg_config/reg_index [3] + u_ov5640/coms2_reg_config/clk_20k_regdiv - DRM_178_4/ADB0[8] + CLMA_122_12/M0 r - u_ov5640/coms1_reg_config/reg_data/iGopDrm/ADB0[8] + u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite/opit_0_inv/D
- +
Location Delay Type @@ -132496,7 +137103,7 @@ Logical Resource - Clock clk_20k (rising edge) + Clock clk_25m (rising edge) 0.000 0.000 @@ -132573,7 +137180,7 @@ 0.000 2.816 r - clkbufg_7/gopclkbufg/CLKOUT + clkbufg_8/gopclkbufg/CLKOUT @@ -132581,53 +137188,21 @@ 0.925 3.741 - ntclkbufg_7 - - - CLMA_182_12/Q1 - tco - 0.224 - 3.965 - r - u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q - - - - net (fanout=3) - 1.384 - 5.349 - - u_ov5640/coms1_reg_config/clk_20k_regdiv - - - USCM_84_119/CLK_USCM - td - 0.000 - 5.349 - r - u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/gopclkbufg/CLKOUT - - - - net (fanout=19) - 0.925 - 6.274 - - u_ov5640/coms1_reg_config/clock_20k + ntclkbufg_8 - DRM_178_4/CLKB[0] + CLMA_122_12/CLK r - u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0] + u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite/opit_0_inv/CLK clock pessimism - -0.471 - 5.803 + -0.299 + 3.442 @@ -132635,15 +137210,15 @@ clock uncertainty 0.000 - 5.803 + 3.442 Hold time - 0.061 - 5.864 + -0.011 + 3.431 @@ -132652,27 +137227,27 @@ - 0.383 - 0 - 8 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[0] + 0.500 + 1 + 3 + u_ov5640/coms1_reg_config/clock_20k_cnt[1]/opit_0_inv/CLK + u_ov5640/coms1_reg_config/clock_20k_cnt[1]/opit_0_inv/D - ioclk1 - ioclk1 + clk_25m + clk_25m rise-rise - 0.009 - 4.513 - 4.916 - -0.394 0.000 - 0.339 - 0.339 (100.0%) - 0.000 (0.0%) + 3.441 + 3.741 + -0.300 + 0.000 + 0.489 + 0.363 (74.2%) + 0.126 (25.8%) - Path #31: hold slack is 0.383(MET) + Path #42: hold slack is 0.500(MET) -
+
Location Delay Type @@ -132682,7 +137257,7 @@ Logical Resource - Clock ioclk1 (rising edge) + Clock clk_25m (rising edge) 0.000 0.000 @@ -132738,291 +137313,89 @@ _N69 - PLL_158_55/CLK_OUT1 + PLL_158_55/CLK_OUT3 td - 0.074 - 1.934 + 0.083 + 1.943 r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 + u_sys_pll/u_pll_e3/goppll/CLKOUT3 - net (fanout=2) + net (fanout=1) 0.603 - 2.537 + 2.546 - zoom_clk + clk_25m - USCM_84_113/CLK_USCM + USCM_84_114/CLK_USCM td 0.000 - 2.537 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 0.981 - 3.518 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.089 - 3.607 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 0.669 - 4.276 - - clkout0_wl_0 - - - IOCKGATE_6_188/OUT - td - 0.200 - 4.476 + 2.546 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT + clkbufg_8/gopclkbufg/CLKOUT - net (fanout=28) - 0.037 - 4.513 + net (fanout=26) + 0.895 + 3.441 - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + ntclkbufg_8 - DQSL_6_152/CLK_IO + CLMS_118_13/CLK r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + u_ov5640/coms1_reg_config/clock_20k_cnt[1]/opit_0_inv/CLK - DQSL_6_152/IFIFO_RADDR[0] + CLMS_118_13/Q0 tco - 0.339 - 4.852 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[0] - - - - net (fanout=8) - 0.000 - 4.852 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [0] - - - IOL_7_162/IFIFO_RADDR[0] - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[0] - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ioclk1 (rising edge) - - 0.000 - 0.000 - r - - - - P20 - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.074 - 0.074 - - clk - - - IOBS_LR_328_209/DIN - td - 1.504 - 1.578 - r - clk_ibuf/opit_0/O - - - - net (fanout=1) - 0.000 - 1.578 - - clk_ibuf/ntD - - - IOL_327_210/INCK - td - 0.058 - 1.636 - r - clk_ibuf/opit_1/INCK - - - - net (fanout=1) - 0.478 - 2.114 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.079 - 2.193 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 0.614 - 2.807 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 2.807 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.019 - 3.826 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.094 - 3.920 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + 0.179 + 3.620 + f + u_ov5640/coms1_reg_config/clock_20k_cnt[1]/opit_0_inv/Q net (fanout=3) - 0.682 - 4.602 - - clkout0_wl_0 + 0.061 + 3.681 + + u_ov5640/coms1_reg_config/clock_20k_cnt [1] - IOCKGATE_6_188/OUT + CLMS_118_13/Y0 td - 0.268 - 4.870 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT - - - - net (fanout=28) - 0.046 - 4.916 - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] - - - IOL_7_162/CLK_IO - - - + 0.184 + 3.865 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK - - - clock pessimism - - -0.394 - 4.522 - - + u_ov5640/coms1_reg_config/N11_2_1/gateop_A2/Y0 - - clock uncertainty - - 0.000 - 4.522 - + + net (fanout=1) + 0.065 + 3.930 + + u_ov5640/coms1_reg_config/N1114 [1] - Hold time + CLMS_118_13/M0 - -0.053 - 4.469 + r + u_ov5640/coms1_reg_config/clock_20k_cnt[1]/opit_0_inv/D
-
-
- - 0.383 - 0 - 8 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[1] - - ioclk1 - ioclk1 - rise-rise - 0.009 - 4.513 - 4.916 - -0.394 - 0.000 - 0.339 - 0.339 (100.0%) - 0.000 (0.0%) - - Path #32: hold slack is 0.383(MET) - +
Location Delay Type @@ -133032,7 +137405,7 @@ Logical Resource - Clock ioclk1 (rising edge) + Clock clk_25m (rising edge) 0.000 0.000 @@ -133058,8 +137431,8 @@ IOBS_LR_328_209/DIN td - 1.285 - 1.359 + 1.504 + 1.578 r clk_ibuf/opit_0/O @@ -133067,126 +137440,137 @@ net (fanout=1) 0.000 - 1.359 + 1.578 clk_ibuf/ntD IOL_327_210/INCK td - 0.038 - 1.397 + 0.058 + 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) - 0.463 - 1.860 + 0.478 + 2.114 _N69 - PLL_158_55/CLK_OUT1 + PLL_158_55/CLK_OUT3 td - 0.074 - 1.934 + 0.088 + 2.202 r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 + u_sys_pll/u_pll_e3/goppll/CLKOUT3 - net (fanout=2) - 0.603 - 2.537 + net (fanout=1) + 0.614 + 2.816 - zoom_clk + clk_25m - USCM_84_113/CLK_USCM + USCM_84_114/CLK_USCM td 0.000 - 2.537 + 2.816 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + clkbufg_8/gopclkbufg/CLKOUT - net (fanout=68) - 0.981 - 3.518 + net (fanout=26) + 0.925 + 3.741 - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.089 - 3.607 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + ntclkbufg_8 + CLMS_118_13/CLK - net (fanout=3) - 0.669 - 4.276 - - clkout0_wl_0 - - - IOCKGATE_6_188/OUT - td - 0.200 - 4.476 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT - - - net (fanout=28) - 0.037 - 4.513 - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + r + u_ov5640/coms1_reg_config/clock_20k_cnt[1]/opit_0_inv/CLK - DQSL_6_152/CLK_IO + clock pessimism + -0.300 + 3.441 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - - - DQSL_6_152/IFIFO_RADDR[1] - tco - 0.339 - 4.852 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[1] + clock uncertainty - net (fanout=8) 0.000 - 4.852 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [1] + 3.441 + + - IOL_7_162/IFIFO_RADDR[1] + Hold time + -0.011 + 3.430 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[1]
+
+
+ + + + Slack + Logic Levels + High Fanout + Start Point + End Point + Exception + Launch Clock + Capture Clock + Clock Edges + Clock Skew + Launch Clock Delay + Capture Clock Delay + Clock Pessimism Removal + Requirement + Data delay + Logic delay + Route delay + + + 2.160 + 0 + 687 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_dqs_rst/opit_0_inv/RS + + clk_200m + clk_200m + rise-rise + -0.142 + 3.844 + 3.432 + 0.270 + 5.000 + 2.072 + 0.223 (10.8%) + 1.849 (89.2%) + + Path #1: recovery slack is 2.160(MET) -
+
Location Delay Type @@ -133196,7 +137580,7 @@ Logical Resource - Clock ioclk1 (rising edge) + Clock clk_200m (rising edge) 0.000 0.000 @@ -133265,7 +137649,7 @@ 0.614 2.807 - zoom_clk + ddr_clk USCM_84_113/CLK_USCM @@ -133277,102 +137661,48 @@ - net (fanout=68) - 1.019 - 3.826 + net (fanout=71) + 1.037 + 3.844 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - PLL_158_199/CLK_OUT0_WL - td - 0.094 - 3.920 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 0.682 - 4.602 - - clkout0_wl_0 - - - IOCKGATE_6_188/OUT - td - 0.268 - 4.870 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT - - - - net (fanout=28) - 0.046 - 4.916 - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] - - - IOL_7_162/CLK_IO + CLMA_174_252/CLK r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK - clock pessimism - - -0.394 - 4.522 - - + CLMA_174_252/Q1 + tco + 0.223 + 4.067 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/Q - clock uncertainty - - 0.000 - 4.522 - + net (fanout=687) + 1.849 + 5.916 + + u_axi_ddr_top/I_ipsxb_ddr_top/ddr_rstn - Hold time + CLMS_10_193/RS - -0.053 - 4.469 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_dqs_rst/opit_0_inv/RS
- -
- - 0.383 - 0 - 8 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[2] - - ioclk1 - ioclk1 - rise-rise - 0.009 - 4.513 - 4.916 - -0.394 - 0.000 - 0.339 - 0.339 (100.0%) - 0.000 (0.0%) - - Path #33: hold slack is 0.383(MET) - +
Location Delay Type @@ -133382,10 +137712,10 @@ Logical Resource - Clock ioclk1 (rising edge) + Clock clk_200m (rising edge) - 0.000 - 0.000 + 5.000 + 5.000 r @@ -133393,7 +137723,7 @@ P200.000 - 0.000 + 5.000rclk (port) @@ -133401,7 +137731,7 @@ net (fanout=1) 0.074 - 0.074 + 5.074 clk @@ -133409,7 +137739,7 @@ IOBS_LR_328_209/DIN td 1.285 - 1.359 + 6.359 r clk_ibuf/opit_0/O @@ -133417,7 +137747,7 @@ net (fanout=1) 0.000 - 1.359 + 6.359 clk_ibuf/ntD @@ -133425,7 +137755,7 @@ IOL_327_210/INCK td 0.038 - 1.397 + 6.397 r clk_ibuf/opit_1/INCK @@ -133433,7 +137763,7 @@ net (fanout=1) 0.463 - 1.860 + 6.860 _N69 @@ -133441,7 +137771,7 @@ PLL_158_55/CLK_OUT1 td 0.074 - 1.934 + 6.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 @@ -133449,94 +137779,84 @@ net (fanout=2) 0.603 - 2.537 + 7.537 - zoom_clk + ddr_clk USCM_84_113/CLK_USCM td 0.000 - 2.537 + 7.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) - 0.981 - 3.518 + net (fanout=71) + 0.895 + 8.432 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - PLL_158_199/CLK_OUT0_WL - td - 0.089 - 3.607 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - + CLMS_10_193/CLK + - net (fanout=3) - 0.669 - 4.276 - clkout0_wl_0 - - - IOCKGATE_6_188/OUT - td - 0.200 - 4.476 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_dqs_rst/opit_0_inv/CLK + clock pessimism + + 0.270 + 8.702 - net (fanout=28) - 0.037 - 4.513 - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] - DQSL_6_152/CLK_IO - + clock uncertainty + -0.150 + 8.552 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - - - DQSL_6_152/IFIFO_RADDR[2] - tco - 0.339 - 4.852 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[2] - - - net (fanout=8) - 0.000 - 4.852 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [2] - IOL_7_162/IFIFO_RADDR[2] + Recovery time + -0.476 + 8.076 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[2]
+
+
+ + 2.401 + 0 + 687 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d1/opit_0_inv/RS + + clk_200m + clk_200m + rise-rise + -0.142 + 3.844 + 3.432 + 0.270 + 5.000 + 1.831 + 0.223 (12.2%) + 1.608 (87.8%) + + Path #2: recovery slack is 2.401(MET) - +
Location Delay Type @@ -133546,7 +137866,7 @@ Logical Resource - Clock ioclk1 (rising edge) + Clock clk_200m (rising edge) 0.000 0.000 @@ -133615,7 +137935,7 @@ 0.614 2.807 - zoom_clk + ddr_clk USCM_84_113/CLK_USCM @@ -133627,102 +137947,48 @@ - net (fanout=68) - 1.019 - 3.826 + net (fanout=71) + 1.037 + 3.844 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - PLL_158_199/CLK_OUT0_WL - td - 0.094 - 3.920 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 0.682 - 4.602 - - clkout0_wl_0 - - - IOCKGATE_6_188/OUT - td - 0.268 - 4.870 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/gopclkgate/OUT - - - - net (fanout=28) - 0.046 - 4.916 - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] - - - IOL_7_162/CLK_IO + CLMA_174_252/CLK r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK - clock pessimism - - -0.394 - 4.522 - - + CLMA_174_252/Q1 + tco + 0.223 + 4.067 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/Q - clock uncertainty - - 0.000 - 4.522 - + net (fanout=687) + 1.608 + 5.675 + + u_axi_ddr_top/I_ipsxb_ddr_top/ddr_rstn - Hold time + CLMA_30_184/RS - -0.053 - 4.469 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d1/opit_0_inv/RS
-
-
- - 0.383 - 0 - 8 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[0] - - ioclk0 - ioclk0 - rise-rise - 0.009 - 4.513 - 4.916 - -0.394 - 0.000 - 0.339 - 0.339 (100.0%) - 0.000 (0.0%) - - Path #34: hold slack is 0.383(MET) - +
Location Delay Type @@ -133732,10 +137998,10 @@ Logical Resource - Clock ioclk0 (rising edge) + Clock clk_200m (rising edge) - 0.000 - 0.000 + 5.000 + 5.000 r @@ -133743,7 +138009,7 @@ P200.000 - 0.000 + 5.000rclk (port) @@ -133751,7 +138017,7 @@ net (fanout=1) 0.074 - 0.074 + 5.074 clk @@ -133759,7 +138025,7 @@ IOBS_LR_328_209/DIN td 1.285 - 1.359 + 6.359 r clk_ibuf/opit_0/O @@ -133767,7 +138033,7 @@ net (fanout=1) 0.000 - 1.359 + 6.359 clk_ibuf/ntD @@ -133775,7 +138041,7 @@ IOL_327_210/INCK td 0.038 - 1.397 + 6.397 r clk_ibuf/opit_1/INCK @@ -133783,7 +138049,7 @@ net (fanout=1) 0.463 - 1.860 + 6.860 _N69 @@ -133791,7 +138057,7 @@ PLL_158_55/CLK_OUT1 td 0.074 - 1.934 + 6.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 @@ -133799,94 +138065,84 @@ net (fanout=2) 0.603 - 2.537 + 7.537 - zoom_clk + ddr_clk USCM_84_113/CLK_USCM td 0.000 - 2.537 + 7.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) - 0.981 - 3.518 + net (fanout=71) + 0.895 + 8.432 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - PLL_158_199/CLK_OUT0_WL - td - 0.089 - 3.607 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 0.669 - 4.276 - - clkout0_wl_0 - - - IOCKGATE_6_312/OUT - td - 0.200 - 4.476 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT - - - - net (fanout=11) - 0.037 - 4.513 - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] - - - DQSL_6_276/CLK_IO + CLMA_30_184/CLK r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d1/opit_0_inv/CLK - DQSL_6_276/IFIFO_RADDR[0] - tco - 0.339 - 4.852 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[0] + clock pessimism + + 0.270 + 8.702 + + + clock uncertainty + + -0.150 + 8.552 + - net (fanout=8) - 0.000 - 4.852 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [0] - IOL_7_285/IFIFO_RADDR[0] + Recovery time + -0.476 + 8.076 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[0]
+
+
+ + 2.401 + 0 + 687 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d2/opit_0_inv/RS + + clk_200m + clk_200m + rise-rise + -0.142 + 3.844 + 3.432 + 0.270 + 5.000 + 1.831 + 0.223 (12.2%) + 1.608 (87.8%) + + Path #3: recovery slack is 2.401(MET) - +
Location Delay Type @@ -133896,7 +138152,7 @@ Logical Resource - Clock ioclk0 (rising edge) + Clock clk_200m (rising edge) 0.000 0.000 @@ -133965,7 +138221,7 @@ 0.614 2.807 - zoom_clk + ddr_clk USCM_84_113/CLK_USCM @@ -133977,102 +138233,48 @@ - net (fanout=68) - 1.019 - 3.826 + net (fanout=71) + 1.037 + 3.844 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - PLL_158_199/CLK_OUT0_WL - td - 0.094 - 3.920 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 0.682 - 4.602 - - clkout0_wl_0 - - - IOCKGATE_6_312/OUT - td - 0.268 - 4.870 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT - - - - net (fanout=11) - 0.046 - 4.916 - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] - - - IOL_7_285/CLK_IO + CLMA_174_252/CLK r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK - clock pessimism - - -0.394 - 4.522 - - + CLMA_174_252/Q1 + tco + 0.223 + 4.067 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/Q - clock uncertainty - - 0.000 - 4.522 - + net (fanout=687) + 1.608 + 5.675 + + u_axi_ddr_top/I_ipsxb_ddr_top/ddr_rstn - Hold time + CLMA_30_184/RS - -0.053 - 4.469 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d2/opit_0_inv/RS
-
-
- - 0.383 - 0 - 8 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[1] - - ioclk0 - ioclk0 - rise-rise - 0.009 - 4.513 - 4.916 - -0.394 - 0.000 - 0.339 - 0.339 (100.0%) - 0.000 (0.0%) - - Path #35: hold slack is 0.383(MET) - +
Location Delay Type @@ -134082,10 +138284,10 @@ Logical Resource - Clock ioclk0 (rising edge) + Clock clk_200m (rising edge) - 0.000 - 0.000 + 5.000 + 5.000 r @@ -134093,7 +138295,7 @@ P200.000 - 0.000 + 5.000rclk (port) @@ -134101,7 +138303,7 @@ net (fanout=1) 0.074 - 0.074 + 5.074 clk @@ -134109,7 +138311,7 @@ IOBS_LR_328_209/DIN td 1.285 - 1.359 + 6.359 r clk_ibuf/opit_0/O @@ -134117,7 +138319,7 @@ net (fanout=1) 0.000 - 1.359 + 6.359 clk_ibuf/ntD @@ -134125,7 +138327,7 @@ IOL_327_210/INCK td 0.038 - 1.397 + 6.397 r clk_ibuf/opit_1/INCK @@ -134133,7 +138335,7 @@ net (fanout=1) 0.463 - 1.860 + 6.860 _N69 @@ -134141,7 +138343,7 @@ PLL_158_55/CLK_OUT1 td 0.074 - 1.934 + 6.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 @@ -134149,94 +138351,84 @@ net (fanout=2) 0.603 - 2.537 + 7.537 - zoom_clk + ddr_clk USCM_84_113/CLK_USCM td 0.000 - 2.537 + 7.537 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=68) - 0.981 - 3.518 + net (fanout=71) + 0.895 + 8.432 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - PLL_158_199/CLK_OUT0_WL - td - 0.089 - 3.607 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - + CLMA_30_184/CLK + - net (fanout=3) - 0.669 - 4.276 - clkout0_wl_0 - - - IOCKGATE_6_312/OUT - td - 0.200 - 4.476 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d2/opit_0_inv/CLK + clock pessimism + + 0.270 + 8.702 - net (fanout=11) - 0.037 - 4.513 - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] - DQSL_6_276/CLK_IO - + clock uncertainty + -0.150 + 8.552 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - - - DQSL_6_276/IFIFO_RADDR[1] - tco - 0.339 - 4.852 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[1] - - - net (fanout=8) - 0.000 - 4.852 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [1] - IOL_7_285/IFIFO_RADDR[1] + Recovery time + -0.476 + 8.076 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[1]
+
+
+ + 4.288 + 0 + 114 + u_zoom_rst/rst/opit_0_L5Q_perm/CLK + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/RSTA[0] + + clk_1080p60Hz + clk_1080p60Hz + rise-rise + 0.080 + 5.882 + 5.630 + 0.332 + 6.736 + 2.290 + 0.221 (9.7%) + 2.069 (90.3%) + + Path #4: recovery slack is 4.288(MET) - +
Location Delay Type @@ -134246,7 +138438,7 @@ Logical Resource - Clock ioclk0 (rising edge) + Clock clk_1080p60Hz (rising edge) 0.000 0.000 @@ -134302,127 +138494,105 @@ _N69 - PLL_158_55/CLK_OUT1 + PLL_158_55/CLK_OUT0 td - 0.079 - 2.193 + 0.083 + 2.197 r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 + u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 0.614 - 2.807 + 2.811 - zoom_clk + rd3_clk - USCM_84_113/CLK_USCM + USCM_84_154/CLK_USCM td 0.000 - 2.807 + 2.811 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + USCMROUTE_0/CLKOUT - net (fanout=68) - 1.019 - 3.826 + net (fanout=1) + 1.131 + 3.942 - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + ntR3950 - PLL_158_199/CLK_OUT0_WL + PLL_158_303/CLK_OUT0 td - 0.094 - 3.920 + 0.083 + 4.025 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 - net (fanout=3) - 0.682 - 4.602 + net (fanout=1) + 0.932 + 4.957 - clkout0_wl_0 + zoom_clk - IOCKGATE_6_312/OUT + USCM_84_118/CLK_USCM td - 0.268 - 4.870 + 0.000 + 4.957 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT + clkbufg_3/gopclkbufg/CLKOUT - net (fanout=11) - 0.046 - 4.916 + net (fanout=750) + 0.925 + 5.882 - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + ntclkbufg_3 - IOL_7_285/CLK_IO + CLMA_170_124/CLK r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK + u_zoom_rst/rst/opit_0_L5Q_perm/CLK - clock pessimism - - -0.394 - 4.522 - - + CLMA_170_124/Q0 + tco + 0.221 + 6.103 + f + u_zoom_rst/rst/opit_0_L5Q_perm/Q - clock uncertainty - - 0.000 - 4.522 - + net (fanout=114) + 2.069 + 8.172 + + zoom_rst - Hold time + DRM_306_252/RSTA[0] - -0.053 - 4.469 + f + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/RSTA[0]
-
-
- - 0.383 - 0 - 8 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[2] - - ioclk0 - ioclk0 - rise-rise - 0.009 - 4.513 - 4.916 - -0.394 - 0.000 - 0.339 - 0.339 (100.0%) - 0.000 (0.0%) - - Path #36: hold slack is 0.383(MET) - +
Location Delay Type @@ -134432,10 +138602,10 @@ Logical Resource - Clock ioclk0 (rising edge) + Clock clk_1080p60Hz (rising edge) - 0.000 - 0.000 + 6.736 + 6.736 r @@ -134443,7 +138613,7 @@ P200.000 - 0.000 + 6.736rclk (port) @@ -134451,7 +138621,7 @@ net (fanout=1) 0.074 - 0.074 + 6.810 clk @@ -134459,7 +138629,7 @@ IOBS_LR_328_209/DIN td 1.285 - 1.359 + 8.095 r clk_ibuf/opit_0/O @@ -134467,7 +138637,7 @@ net (fanout=1) 0.000 - 1.359 + 8.095 clk_ibuf/ntD @@ -134475,7 +138645,7 @@ IOL_327_210/INCK td 0.038 - 1.397 + 8.133 r clk_ibuf/opit_1/INCK @@ -134483,110 +138653,132 @@ net (fanout=1) 0.463 - 1.860 + 8.596 _N69 - PLL_158_55/CLK_OUT1 + PLL_158_55/CLK_OUT0 td - 0.074 - 1.934 + 0.078 + 8.674 r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 + u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 0.603 - 2.537 + 9.277 - zoom_clk + rd3_clk - USCM_84_113/CLK_USCM + USCM_84_154/CLK_USCM td 0.000 - 2.537 + 9.277 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + USCMROUTE_0/CLKOUT - net (fanout=68) - 0.981 - 3.518 + net (fanout=1) + 1.091 + 10.368 - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + ntR3950 - PLL_158_199/CLK_OUT0_WL + PLL_158_303/CLK_OUT0 td - 0.089 - 3.607 + 0.078 + 10.446 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 - net (fanout=3) - 0.669 - 4.276 + net (fanout=1) + 0.915 + 11.361 - clkout0_wl_0 + zoom_clk - IOCKGATE_6_312/OUT + USCM_84_118/CLK_USCM td - 0.200 - 4.476 + 0.000 + 11.361 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT + clkbufg_3/gopclkbufg/CLKOUT - net (fanout=11) - 0.037 - 4.513 + net (fanout=750) + 1.005 + 12.366 - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + ntclkbufg_3 - DQSL_6_276/CLK_IO + DRM_306_252/CLKA[0] r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/CLKA[0] - DQSL_6_276/IFIFO_RADDR[2] - tco - 0.339 - 4.852 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IFIFO_RADDR[2] + clock pessimism + + 0.332 + 12.698 + + + clock uncertainty + + -0.150 + 12.548 + - net (fanout=8) - 0.000 - 4.852 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [2] - IOL_7_285/IFIFO_RADDR[2] + Recovery time + -0.088 + 12.460 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/IFIFO_RADDR[2]
+
+
+ + 4.328 + 0 + 114 + u_zoom_rst/rst/opit_0_L5Q_perm/CLK + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/RSTA[0] + + clk_1080p60Hz + clk_1080p60Hz + rise-rise + 0.080 + 5.882 + 5.630 + 0.332 + 6.736 + 2.250 + 0.221 (9.8%) + 2.029 (90.2%) + + Path #5: recovery slack is 4.328(MET) - +
Location Delay Type @@ -134596,7 +138788,7 @@ Logical Resource - Clock ioclk0 (rising edge) + Clock clk_1080p60Hz (rising edge) 0.000 0.000 @@ -134652,127 +138844,105 @@ _N69 - PLL_158_55/CLK_OUT1 + PLL_158_55/CLK_OUT0 td - 0.079 - 2.193 + 0.083 + 2.197 r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 + u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 0.614 - 2.807 + 2.811 - zoom_clk + rd3_clk - USCM_84_113/CLK_USCM + USCM_84_154/CLK_USCM td 0.000 - 2.807 + 2.811 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + USCMROUTE_0/CLKOUT - net (fanout=68) - 1.019 - 3.826 + net (fanout=1) + 1.131 + 3.942 - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + ntR3950 - PLL_158_199/CLK_OUT0_WL + PLL_158_303/CLK_OUT0 td - 0.094 - 3.920 + 0.083 + 4.025 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 - net (fanout=3) - 0.682 - 4.602 + net (fanout=1) + 0.932 + 4.957 - clkout0_wl_0 + zoom_clk - IOCKGATE_6_312/OUT + USCM_84_118/CLK_USCM td - 0.268 - 4.870 + 0.000 + 4.957 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/gopclkgate/OUT + clkbufg_3/gopclkbufg/CLKOUT - net (fanout=11) - 0.046 - 4.916 + net (fanout=750) + 0.925 + 5.882 - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + ntclkbufg_3 - IOL_7_285/CLK_IO + CLMA_170_124/CLK r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/gateop_a_IO/DESCLK - - - clock pessimism - - -0.394 - 4.522 - - - - - clock uncertainty - - 0.000 - 4.522 - - + u_zoom_rst/rst/opit_0_L5Q_perm/CLK - Hold time - - -0.053 - 4.469 - - + CLMA_170_124/Q0 + tco + 0.221 + 6.103 + f + u_zoom_rst/rst/opit_0_L5Q_perm/Q -
-
-
-
- - 0.406 - 0 - 3 - u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK - u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/D - - clk_25m - clk_25m - rise-rise - 0.001 - 3.441 - 3.741 - -0.299 - 0.000 - 0.396 - 0.184 (46.5%) - 0.212 (53.5%) - - Path #37: hold slack is 0.406(MET) + + + net (fanout=114) + 2.029 + 8.132 + + zoom_rst + + + DRM_306_292/RSTA[0] + + + + f + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/RSTA[0] + + + - +
Location Delay Type @@ -134782,10 +138952,10 @@ Logical Resource - Clock clk_25m (rising edge) + Clock clk_1080p60Hz (rising edge) - 0.000 - 0.000 + 6.736 + 6.736 r @@ -134793,7 +138963,7 @@ P200.000 - 0.000 + 6.736rclk (port) @@ -134801,7 +138971,7 @@ net (fanout=1) 0.074 - 0.074 + 6.810 clk @@ -134809,7 +138979,7 @@ IOBS_LR_328_209/DIN td 1.285 - 1.359 + 8.095 r clk_ibuf/opit_0/O @@ -134817,7 +138987,7 @@ net (fanout=1) 0.000 - 1.359 + 8.095 clk_ibuf/ntD @@ -134825,7 +138995,7 @@ IOL_327_210/INCK td 0.038 - 1.397 + 8.133 r clk_ibuf/opit_1/INCK @@ -134833,78 +139003,132 @@ net (fanout=1) 0.463 - 1.860 + 8.596 _N69 - PLL_158_55/CLK_OUT3 + PLL_158_55/CLK_OUT0 td - 0.083 - 1.943 + 0.078 + 8.674 r - u_sys_pll/u_pll_e3/goppll/CLKOUT3 + u_sys_pll/u_pll_e3/goppll/CLKOUT0 - net (fanout=1) + net (fanout=2) 0.603 - 2.546 + 9.277 - clk_25m + rd3_clk - USCM_84_114/CLK_USCM + USCM_84_154/CLK_USCM td 0.000 - 2.546 + 9.277 r - clkbufg_7/gopclkbufg/CLKOUT + USCMROUTE_0/CLKOUT - net (fanout=26) - 0.895 - 3.441 + net (fanout=1) + 1.091 + 10.368 - ntclkbufg_7 + ntR3950 + + + PLL_158_303/CLK_OUT0 + td + 0.078 + 10.446 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 - CLMA_182_12/CLK - + net (fanout=1) + 0.915 + 11.361 - r - u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK + zoom_clk - CLMA_182_12/Q1 - tco - 0.184 - 3.625 + USCM_84_118/CLK_USCM + td + 0.000 + 11.361 r - u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/Q + clkbufg_3/gopclkbufg/CLKOUT - net (fanout=3) - 0.212 - 3.837 - - u_ov5640/coms1_reg_config/clk_20k_regdiv + net (fanout=750) + 1.005 + 12.366 + + ntclkbufg_3 - CLMA_182_12/M0 + DRM_306_292/CLKA[0] r - u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/D + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[5].U_GTP_DRM18K/iGopDrm/CLKA[0] + + + clock pessimism + + 0.332 + 12.698 + + + + + clock uncertainty + + -0.150 + 12.548 + + + + + Recovery time + + -0.088 + 12.460 + +
+
+
+ + 4.384 + 0 + 114 + u_zoom_rst/rst/opit_0_L5Q_perm/CLK + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[4].U_GTP_DRM18K/iGopDrm/RSTA[0] + + clk_1080p60Hz + clk_1080p60Hz + rise-rise + 0.080 + 5.882 + 5.630 + 0.332 + 6.736 + 2.194 + 0.221 (10.1%) + 1.973 (89.9%) + + Path #6: recovery slack is 4.384(MET) - +
Location Delay Type @@ -134914,7 +139138,7 @@ Logical Resource - Clock clk_25m (rising edge) + Clock clk_1080p60Hz (rising edge) 0.000 0.000 @@ -134970,95 +139194,105 @@ _N69 - PLL_158_55/CLK_OUT3 + PLL_158_55/CLK_OUT0 td - 0.088 - 2.202 + 0.083 + 2.197 r - u_sys_pll/u_pll_e3/goppll/CLKOUT3 + u_sys_pll/u_pll_e3/goppll/CLKOUT0 - net (fanout=1) + net (fanout=2) 0.614 - 2.816 + 2.811 - clk_25m + rd3_clk - USCM_84_114/CLK_USCM + USCM_84_154/CLK_USCM td 0.000 - 2.816 + 2.811 r - clkbufg_7/gopclkbufg/CLKOUT + USCMROUTE_0/CLKOUT - net (fanout=26) - 0.925 - 3.741 + net (fanout=1) + 1.131 + 3.942 - ntclkbufg_7 + ntR3950 + + + PLL_158_303/CLK_OUT0 + td + 0.083 + 4.025 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 - CLMA_182_12/CLK - + net (fanout=1) + 0.932 + 4.957 + zoom_clk + + + USCM_84_118/CLK_USCM + td + 0.000 + 4.957 r - u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/CLK + clkbufg_3/gopclkbufg/CLKOUT - clock pessimism - - -0.299 - 3.442 + net (fanout=750) + 0.925 + 5.882 + ntclkbufg_3 - clock uncertainty + CLMA_170_124/CLK - 0.000 - 3.442 + r + u_zoom_rst/rst/opit_0_L5Q_perm/CLK + + + CLMA_170_124/Q0 + tco + 0.221 + 6.103 + f + u_zoom_rst/rst/opit_0_L5Q_perm/Q - Hold time - -0.011 - 3.431 + net (fanout=114) + 1.973 + 8.076 + + zoom_rst + + + DRM_306_272/RSTA[0] + + f + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[4].U_GTP_DRM18K/iGopDrm/RSTA[0]
-
-
- - 0.482 - 0 - 3 - u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/CLK - u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite/opit_0_inv/D - - clk_25m - clk_25m - rise-rise - 0.001 - 3.441 - 3.741 - -0.299 - 0.000 - 0.472 - 0.184 (39.0%) - 0.288 (61.0%) - - Path #38: hold slack is 0.482(MET) - +
Location Delay Type @@ -135068,10 +139302,10 @@ Logical Resource - Clock clk_25m (rising edge) + Clock clk_1080p60Hz (rising edge) - 0.000 - 0.000 + 6.736 + 6.736 r @@ -135079,7 +139313,7 @@ P200.000 - 0.000 + 6.736rclk (port) @@ -135087,7 +139321,7 @@ net (fanout=1) 0.074 - 0.074 + 6.810 clk @@ -135095,7 +139329,7 @@ IOBS_LR_328_209/DIN td 1.285 - 1.359 + 8.095 r clk_ibuf/opit_0/O @@ -135103,7 +139337,7 @@ net (fanout=1) 0.000 - 1.359 + 8.095 clk_ibuf/ntD @@ -135111,7 +139345,7 @@ IOL_327_210/INCK td 0.038 - 1.397 + 8.133 r clk_ibuf/opit_1/INCK @@ -135119,78 +139353,132 @@ net (fanout=1) 0.463 - 1.860 + 8.596 _N69 - PLL_158_55/CLK_OUT3 + PLL_158_55/CLK_OUT0 td - 0.083 - 1.943 + 0.078 + 8.674 r - u_sys_pll/u_pll_e3/goppll/CLKOUT3 + u_sys_pll/u_pll_e3/goppll/CLKOUT0 - net (fanout=1) + net (fanout=2) 0.603 - 2.546 + 9.277 - clk_25m + rd3_clk - USCM_84_114/CLK_USCM + USCM_84_154/CLK_USCM td 0.000 - 2.546 + 9.277 r - clkbufg_7/gopclkbufg/CLKOUT + USCMROUTE_0/CLKOUT - net (fanout=26) - 0.895 - 3.441 + net (fanout=1) + 1.091 + 10.368 - ntclkbufg_7 + ntR3950 + + + PLL_158_303/CLK_OUT0 + td + 0.078 + 10.446 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 - CLMA_182_25/CLK - + net (fanout=1) + 0.915 + 11.361 - r - u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/CLK + zoom_clk - CLMA_182_25/Q1 - tco - 0.184 - 3.625 + USCM_84_118/CLK_USCM + td + 0.000 + 11.361 r - u_ov5640/coms2_reg_config/clk_20k_regdiv/opit_0_inv/Q + clkbufg_3/gopclkbufg/CLKOUT - net (fanout=3) - 0.288 - 3.913 - - u_ov5640/coms2_reg_config/clk_20k_regdiv + net (fanout=750) + 1.005 + 12.366 + + ntclkbufg_3 - CLMA_182_25/M0 + DRM_306_272/CLKA[0] r - u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite/opit_0_inv/D + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[4].U_GTP_DRM18K/iGopDrm/CLKA[0] + + + clock pessimism + + 0.332 + 12.698 + + + + + clock uncertainty + + -0.150 + 12.548 + + + + + Recovery time + + -0.088 + 12.460 + +
+
+
+ + 6.879 + 16 + 729 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/opit_0_inv_L5Q_perm/RS + + ddrphy_clkin + ddrphy_clkin + rise-rise + -0.019 + 7.101 + 6.654 + 0.428 + 10.000 + 2.952 + 2.031 (68.8%) + 0.921 (31.2%) + + Path #7: recovery slack is 6.879(MET) - +
Location Delay Type @@ -135200,7 +139488,7 @@ Logical Resource - Clock clk_25m (rising edge) + Clock ddrphy_clkin (rising edge) 0.000 0.000 @@ -135256,243 +139544,393 @@ _N69 - PLL_158_55/CLK_OUT3 + PLL_158_55/CLK_OUT1 td - 0.088 - 2.202 + 0.079 + 2.193 r - u_sys_pll/u_pll_e3/goppll/CLKOUT3 + u_sys_pll/u_pll_e3/goppll/CLKOUT1 - net (fanout=1) + net (fanout=2) 0.614 - 2.816 + 2.807 - clk_25m + ddr_clk - USCM_84_114/CLK_USCM + USCM_84_113/CLK_USCM td 0.000 - 2.816 + 2.807 r - clkbufg_7/gopclkbufg/CLKOUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=26) - 0.925 - 3.741 + net (fanout=71) + 1.019 + 3.826 - ntclkbufg_7 + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.094 + 3.920 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - CLMA_182_25/CLK + net (fanout=3) + 0.682 + 4.602 + + clkout0_wl_0 + + + IOCKGATE_6_322/OUT + td + 0.268 + 4.870 + r + clkgate_9/gopclkgate/OUT + + + net (fanout=1) + 0.000 + 4.870 + ntclkgate_0 + + + IOCKDIV_6_323/CLK_IODIV + td + 0.000 + 4.870 r - u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite/opit_0_inv/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV - clock pessimism - -0.299 - 3.442 + net (fanout=1) + 1.306 + 6.176 + u_axi_ddr_top/clk + + + USCM_84_116/CLK_USCM + td + 0.000 + 6.176 + r + clkbufg_0/gopclkbufg/CLKOUT + + + + net (fanout=5464) + 0.925 + 7.101 + ntclkbufg_0 - clock uncertainty + CLMA_46_192/CLK - 0.000 - 3.442 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK + + + CLMA_46_192/Q0 + tco + 0.223 + 7.324 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q - Hold time - -0.011 - 3.431 + net (fanout=729) + 0.921 + 8.245 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n + + + CLMA_34_148/RSCO + td + 0.113 + 8.358 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[2]/opit_0_inv_L5Q_perm/RSOUT + + + net (fanout=4) + 0.000 + 8.358 + + ntR882 + + + CLMA_34_152/RSCO + td + 0.113 + 8.471 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[5]/opit_0_inv_L5Q_perm/RSOUT + + + net (fanout=4) + 0.000 + 8.471 + + ntR881 + + + CLMA_34_156/RSCO + td + 0.113 + 8.584 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_we_n_d[0]/opit_0_inv_L5Q_perm/RSOUT -
-
-
-
- - 0.569 - 1 - 2 - u_ov5640/coms1_reg_config/clock_20k_cnt[5]/opit_0_inv/CLK - u_ov5640/coms1_reg_config/clock_20k_cnt[5]/opit_0_inv/D - - clk_25m - clk_25m - rise-rise - 0.000 - 3.441 - 3.741 - -0.300 - 0.000 - 0.603 - 0.412 (68.3%) - 0.191 (31.7%) - - Path #39: hold slack is 0.569(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - Clock clk_25m (rising edge) + net (fanout=4) 0.000 + 8.584 + + ntR880 + + + CLMA_34_160/RSCO + td + 0.113 + 8.697 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cs_n_d[0]/opit_0_inv_L5Q_perm/RSOUT + + + + net (fanout=2) 0.000 - r + 8.697 + + ntR879 + + + CLMA_34_164/RSCO + td + 0.113 + 8.810 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[4]/opit_0_inv_A2Q21/RSOUT + + + net (fanout=3) + 0.000 + 8.810 + + ntR878 - P20 - + CLMA_34_168/RSCO + td + 0.113 + 8.923 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[0]/opit_0_inv_L5Q_perm/RSOUT + + + + net (fanout=6) 0.000 + 8.923 + + ntR877 + + + CLMA_34_172/RSCO + td + 0.113 + 9.036 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_r[1]/opit_0_inv/RSOUT + + + + net (fanout=5) 0.000 - r - clk (port) + 9.036 + + ntR876 + + + CLMA_34_176/RSCO + td + 0.113 + 9.149 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=1) - 0.074 - 0.074 + net (fanout=2) + 0.000 + 9.149 + + ntR875 + + + CLMA_34_180/RSCO + td + 0.113 + 9.262 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[4]/opit_0_inv_A2Q21/RSOUT + + - clk + net (fanout=2) + 0.000 + 9.262 + + ntR874 - IOBS_LR_328_209/DIN + CLMA_34_184/RSCO td - 1.285 - 1.359 - r - clk_ibuf/opit_0/O + 0.113 + 9.375 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[8]/opit_0_inv_A2Q21/RSOUT - net (fanout=1) + net (fanout=2) 0.000 - 1.359 - - clk_ibuf/ntD + 9.375 + + ntR873 - IOL_327_210/INCK + CLMA_34_192/RSCO td - 0.038 - 1.397 - r - clk_ibuf/opit_1/INCK + 0.113 + 9.488 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[12]/opit_0_inv_A2Q21/RSOUT - net (fanout=1) - 0.463 - 1.860 - - _N69 + net (fanout=2) + 0.000 + 9.488 + + ntR872 - PLL_158_55/CLK_OUT3 + CLMA_34_196/RSCO td - 0.083 - 1.943 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT3 + 0.113 + 9.601 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[16]/opit_0_inv_A2Q21/RSOUT net (fanout=1) - 0.603 - 2.546 - - clk_25m + 0.000 + 9.601 + + ntR871 - USCM_84_114/CLK_USCM + CLMA_34_200/RSCO td - 0.000 - 2.546 - r - clkbufg_7/gopclkbufg/CLKOUT + 0.113 + 9.714 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[17]/opit_0_inv_AQ_perm/RSOUT - net (fanout=26) - 0.895 - 3.441 - - ntclkbufg_7 + net (fanout=6) + 0.000 + 9.714 + + ntR870 + + + CLMA_34_204/RSCO + td + 0.113 + 9.827 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[1]/opit_0_inv/RSOUT - CLMA_182_17/CLK - - - r - u_ov5640/coms1_reg_config/clock_20k_cnt[5]/opit_0_inv/CLK + net (fanout=5) + 0.000 + 9.827 + + ntR869 - CLMA_182_17/Y0 - tco - 0.228 - 3.669 + CLMA_34_208/RSCO + td + 0.113 + 9.940 f - u_ov5640/coms1_reg_config/clock_20k_cnt[5]/opit_0_inv/Q + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[238]/opit_0_inv/RSOUT - net (fanout=2) - 0.060 - 3.729 + net (fanout=5) + 0.000 + 9.940 - u_ov5640/coms1_reg_config/clock_20k_cnt [5] + ntR868 - CLMA_182_16/Y0 + CLMA_34_212/RSCO td - 0.184 - 3.913 - r - u_ov5640/coms1_reg_config/N11_2_5/gateop_A2/Y0 + 0.113 + 10.053 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[86]/opit_0_inv/RSOUT - net (fanout=1) - 0.131 - 4.044 + net (fanout=5) + 0.000 + 10.053 - u_ov5640/coms1_reg_config/N1114 [5] + ntR867 - CLMA_182_17/AD + CLMA_34_216/RSCI - r - u_ov5640/coms1_reg_config/clock_20k_cnt[5]/opit_0_inv/D + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/opit_0_inv_L5Q_perm/RS
- +
Location Delay Type @@ -135502,10 +139940,10 @@ Logical Resource - Clock clk_25m (rising edge) + Clock ddrphy_clkin (rising edge) - 0.000 - 0.000 + 10.000 + 10.000 r @@ -135513,7 +139951,7 @@ P200.000 - 0.000 + 10.000rclk (port) @@ -135521,15 +139959,15 @@ net (fanout=1) 0.074 - 0.074 + 10.074 clk IOBS_LR_328_209/DIN td - 1.504 - 1.578 + 1.285 + 11.359 r clk_ibuf/opit_0/O @@ -135537,87 +139975,151 @@ net (fanout=1) 0.000 - 1.578 + 11.359 clk_ibuf/ntD IOL_327_210/INCK td - 0.058 - 1.636 + 0.038 + 11.397 r clk_ibuf/opit_1/INCK net (fanout=1) - 0.478 - 2.114 + 0.463 + 11.860 _N69 - PLL_158_55/CLK_OUT3 + PLL_158_55/CLK_OUT1 td - 0.088 - 2.202 + 0.074 + 11.934 r - u_sys_pll/u_pll_e3/goppll/CLKOUT3 + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 0.603 + 12.537 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 12.537 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 0.981 + 13.518 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.089 + 13.607 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 0.669 + 14.276 + + clkout0_wl_0 + + + IOCKGATE_6_322/OUT + td + 0.200 + 14.476 + r + clkgate_9/gopclkgate/OUT net (fanout=1) - 0.614 - 2.816 + 0.000 + 14.476 - clk_25m + ntclkgate_0 - USCM_84_114/CLK_USCM + IOCKDIV_6_323/CLK_IODIV td 0.000 - 2.816 + 14.476 r - clkbufg_7/gopclkbufg/CLKOUT + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV - net (fanout=26) - 0.925 - 3.741 + net (fanout=1) + 1.283 + 15.759 - ntclkbufg_7 + u_axi_ddr_top/clk + + + USCM_84_116/CLK_USCM + td + 0.000 + 15.759 + r + clkbufg_0/gopclkbufg/CLKOUT + + + + net (fanout=5464) + 0.895 + 16.654 + + ntclkbufg_0 - CLMA_182_17/CLK + CLMA_34_216/CLK r - u_ov5640/coms1_reg_config/clock_20k_cnt[5]/opit_0_inv/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/opit_0_inv_L5Q_perm/CLK clock pessimism - -0.300 - 3.441 + 0.428 + 17.082 clock uncertainty - 0.000 - 3.441 + -0.150 + 16.932 - Hold time + Recovery time - 0.034 - 3.475 + 0.000 + 16.932 @@ -135625,49 +140127,28 @@ -
- - - Slack - Logic Levels - High Fanout - Start Point - End Point - Exception - Launch Clock - Capture Clock - Clock Edges - Clock Skew - Launch Clock Delay - Capture Clock Delay - Clock Pessimism Removal - Requirement - Data delay - Logic delay - Route delay - - 2.157 - 0 - 686 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d1/opit_0_inv/RS + 6.879 + 16 + 729 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[110]/opit_0_inv/RS - clk_200m - clk_200m + ddrphy_clkin + ddrphy_clkin rise-rise - -0.030 - 3.732 - 3.432 - 0.270 - 5.000 - 2.187 - 0.223 (10.2%) - 1.964 (89.8%) + -0.019 + 7.101 + 6.654 + 0.428 + 10.000 + 2.952 + 2.031 (68.8%) + 0.921 (31.2%) - Path #1: recovery slack is 2.157(MET) + Path #8: recovery slack is 6.879(MET) -
+
Location Delay Type @@ -135677,7 +140158,7 @@ Logical Resource - Clock clk_200m (rising edge) + Clock ddrphy_clkin (rising edge) 0.000 0.000 @@ -135746,7 +140227,7 @@ 0.614 2.807 - zoom_clk + ddr_clk USCM_84_113/CLK_USCM @@ -135758,488 +140239,368 @@ - net (fanout=68) - 0.925 - 3.732 + net (fanout=71) + 1.019 + 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - CLMA_202_148/CLK - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK - - - CLMA_202_148/Q1 - tco - 0.223 - 3.955 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/Q - - - - net (fanout=686) - 1.964 - 5.919 - - u_axi_ddr_top/I_ipsxb_ddr_top/ddr_rstn - - - CLMS_10_193/RS - - - - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d1/opit_0_inv/RS - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_200m (rising edge) - - 5.000 - 5.000 - r - - - - P20 - - 0.000 - 5.000 + PLL_158_199/CLK_OUT0_WL + td + 0.094 + 3.920 r - clk (port) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - net (fanout=1) - 0.074 - 5.074 + net (fanout=3) + 0.682 + 4.602 - clk + clkout0_wl_0 - IOBS_LR_328_209/DIN + IOCKGATE_6_322/OUT td - 1.285 - 6.359 + 0.268 + 4.870 r - clk_ibuf/opit_0/O + clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 - 6.359 + 4.870 - clk_ibuf/ntD + ntclkgate_0 - IOL_327_210/INCK + IOCKDIV_6_323/CLK_IODIV td - 0.038 - 6.397 + 0.000 + 4.870 r - clk_ibuf/opit_1/INCK + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) - 0.463 - 6.860 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.074 - 6.934 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 0.603 - 7.537 + 1.306 + 6.176 - zoom_clk + u_axi_ddr_top/clk - USCM_84_113/CLK_USCM + USCM_84_116/CLK_USCM td 0.000 - 7.537 + 6.176 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + clkbufg_0/gopclkbufg/CLKOUT - net (fanout=68) - 0.895 - 8.432 + net (fanout=5464) + 0.925 + 7.101 - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + ntclkbufg_0 - CLMS_10_193/CLK + CLMA_46_192/CLK r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d1/opit_0_inv/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK - clock pessimism - - 0.270 - 8.702 - - + CLMA_46_192/Q0 + tco + 0.223 + 7.324 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q - clock uncertainty - - -0.150 - 8.552 - + net (fanout=729) + 0.921 + 8.245 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n - Recovery time - - -0.476 - 8.076 - - + CLMA_34_148/RSCO + td + 0.113 + 8.358 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[2]/opit_0_inv_L5Q_perm/RSOUT -
-
-
-
- - 2.157 - 0 - 686 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d2/opit_0_inv/RS - - clk_200m - clk_200m - rise-rise - -0.030 - 3.732 - 3.432 - 0.270 - 5.000 - 2.187 - 0.223 (10.2%) - 1.964 (89.8%) - - Path #2: recovery slack is 2.157(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - Clock clk_200m (rising edge) + net (fanout=4) 0.000 - 0.000 - r - + 8.358 + + ntR882 - P20 - - 0.000 - 0.000 - r - clk (port) + CLMA_34_152/RSCO + td + 0.113 + 8.471 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[5]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=1) - 0.074 - 0.074 - - clk + net (fanout=4) + 0.000 + 8.471 + + ntR881 - IOBS_LR_328_209/DIN + CLMA_34_156/RSCO td - 1.504 - 1.578 - r - clk_ibuf/opit_0/O + 0.113 + 8.584 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_we_n_d[0]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=1) + net (fanout=4) 0.000 - 1.578 - - clk_ibuf/ntD + 8.584 + + ntR880 - IOL_327_210/INCK + CLMA_34_160/RSCO td - 0.058 - 1.636 - r - clk_ibuf/opit_1/INCK + 0.113 + 8.697 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cs_n_d[0]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=1) - 0.478 - 2.114 - - _N69 + net (fanout=2) + 0.000 + 8.697 + + ntR879 - PLL_158_55/CLK_OUT1 + CLMA_34_164/RSCO td - 0.079 - 2.193 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 + 0.113 + 8.810 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[4]/opit_0_inv_A2Q21/RSOUT - net (fanout=2) - 0.614 - 2.807 - - zoom_clk + net (fanout=3) + 0.000 + 8.810 + + ntR878 - USCM_84_113/CLK_USCM + CLMA_34_168/RSCO td - 0.000 - 2.807 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + 0.113 + 8.923 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[0]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=68) - 0.925 - 3.732 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=6) + 0.000 + 8.923 + + ntR877 + + + CLMA_34_172/RSCO + td + 0.113 + 9.036 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_r[1]/opit_0_inv/RSOUT - CLMA_202_148/CLK - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK + net (fanout=5) + 0.000 + 9.036 + + ntR876 - CLMA_202_148/Q1 - tco - 0.223 - 3.955 + CLMA_34_176/RSCO + td + 0.113 + 9.149 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/Q + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=686) - 1.964 - 5.919 + net (fanout=2) + 0.000 + 9.149 - u_axi_ddr_top/I_ipsxb_ddr_top/ddr_rstn + ntR875 - CLMS_10_193/RS - - - + CLMA_34_180/RSCO + td + 0.113 + 9.262 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d2/opit_0_inv/RS + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[4]/opit_0_inv_A2Q21/RSOUT -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - Clock clk_200m (rising edge) - - 5.000 - 5.000 - r + net (fanout=2) + 0.000 + 9.262 + + ntR874 - P20 - - 0.000 - 5.000 - r - clk (port) + CLMA_34_184/RSCO + td + 0.113 + 9.375 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[8]/opit_0_inv_A2Q21/RSOUT - net (fanout=1) - 0.074 - 5.074 - - clk + net (fanout=2) + 0.000 + 9.375 + + ntR873 - IOBS_LR_328_209/DIN + CLMA_34_192/RSCO td - 1.285 - 6.359 - r - clk_ibuf/opit_0/O + 0.113 + 9.488 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[12]/opit_0_inv_A2Q21/RSOUT - net (fanout=1) + net (fanout=2) 0.000 - 6.359 - - clk_ibuf/ntD + 9.488 + + ntR872 - IOL_327_210/INCK + CLMA_34_196/RSCO td - 0.038 - 6.397 - r - clk_ibuf/opit_1/INCK + 0.113 + 9.601 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[16]/opit_0_inv_A2Q21/RSOUT net (fanout=1) - 0.463 - 6.860 - - _N69 + 0.000 + 9.601 + + ntR871 - PLL_158_55/CLK_OUT1 + CLMA_34_200/RSCO td - 0.074 - 6.934 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 + 0.113 + 9.714 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[17]/opit_0_inv_AQ_perm/RSOUT - net (fanout=2) - 0.603 - 7.537 - - zoom_clk + net (fanout=6) + 0.000 + 9.714 + + ntR870 - USCM_84_113/CLK_USCM + CLMA_34_204/RSCO td - 0.000 - 7.537 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + 0.113 + 9.827 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[1]/opit_0_inv/RSOUT - net (fanout=68) - 0.895 - 8.432 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=5) + 0.000 + 9.827 + + ntR869 - CLMS_10_193/CLK - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d2/opit_0_inv/CLK + CLMA_34_208/RSCO + td + 0.113 + 9.940 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[238]/opit_0_inv/RSOUT - clock pessimism - - 0.270 - 8.702 - + net (fanout=5) + 0.000 + 9.940 + + ntR868 + + + CLMA_34_212/RSCO + td + 0.113 + 10.053 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[86]/opit_0_inv/RSOUT - clock uncertainty - - -0.150 - 8.552 - + net (fanout=5) + 0.000 + 10.053 + + ntR867 - Recovery time + CLMA_34_216/RSCI - -0.476 - 8.076 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[110]/opit_0_inv/RS
-
-
- - 2.289 - 0 - 131 - u_zoom_rst/rst/opit_0_L5Q_perm/CLK - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[8].U_GTP_DRM18K/iGopDrm/RSTA[0] - - clk_200m - clk_200m - rise-rise - 0.080 - 3.732 - 3.542 - 0.270 - 5.000 - 2.553 - 0.221 (8.7%) - 2.332 (91.3%) - - Path #3: recovery slack is 2.289(MET) - +
Location Delay Type @@ -136249,10 +140610,10 @@ Logical Resource - Clock clk_200m (rising edge) + Clock ddrphy_clkin (rising edge) - 0.000 - 0.000 + 10.000 + 10.000 r @@ -136260,7 +140621,7 @@ P200.000 - 0.000 + 10.000rclk (port) @@ -136268,15 +140629,15 @@ net (fanout=1) 0.074 - 0.074 + 10.074 clk IOBS_LR_328_209/DIN td - 1.504 - 1.578 + 1.285 + 11.359 r clk_ibuf/opit_0/O @@ -136284,203 +140645,135 @@ net (fanout=1) 0.000 - 1.578 + 11.359 clk_ibuf/ntD IOL_327_210/INCK td - 0.058 - 1.636 + 0.038 + 11.397 r clk_ibuf/opit_1/INCK net (fanout=1) - 0.478 - 2.114 + 0.463 + 11.860 _N69 PLL_158_55/CLK_OUT1 td - 0.079 - 2.193 + 0.074 + 11.934 r u_sys_pll/u_pll_e3/goppll/CLKOUT1 net (fanout=2) - 0.614 - 2.807 + 0.603 + 12.537 - zoom_clk + ddr_clk - USCM_84_122/CLK_USCM + USCM_84_113/CLK_USCM td 0.000 - 2.807 - r - USCMROUTE_2/CLKOUT - - - - net (fanout=759) - 0.925 - 3.732 - - ntR3909 - - - CLMS_186_125/CLK - - - + 12.537 r - u_zoom_rst/rst/opit_0_L5Q_perm/CLK - - - CLMS_186_125/Q0 - tco - 0.221 - 3.953 - f - u_zoom_rst/rst/opit_0_L5Q_perm/Q - - - - net (fanout=131) - 2.332 - 6.285 - - zoom_rst - - - DRM_278_356/RSTA[0] - - - - f - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[8].U_GTP_DRM18K/iGopDrm/RSTA[0] + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - Clock clk_200m (rising edge) - 5.000 - 5.000 - r + net (fanout=71) + 0.981 + 13.518 + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - P20 - - 0.000 - 5.000 + PLL_158_199/CLK_OUT0_WL + td + 0.089 + 13.607 r - clk (port) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - net (fanout=1) - 0.074 - 5.074 + net (fanout=3) + 0.669 + 14.276 - clk + clkout0_wl_0 - IOBS_LR_328_209/DIN + IOCKGATE_6_322/OUT td - 1.285 - 6.359 + 0.200 + 14.476 r - clk_ibuf/opit_0/O + clkgate_9/gopclkgate/OUT net (fanout=1) 0.000 - 6.359 + 14.476 - clk_ibuf/ntD + ntclkgate_0 - IOL_327_210/INCK + IOCKDIV_6_323/CLK_IODIV td - 0.038 - 6.397 + 0.000 + 14.476 r - clk_ibuf/opit_1/INCK + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV net (fanout=1) - 0.463 - 6.860 - - _N69 - - - PLL_158_55/CLK_OUT1 - td - 0.074 - 6.934 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 0.603 - 7.537 + 1.283 + 15.759 - zoom_clk + u_axi_ddr_top/clk - USCM_84_122/CLK_USCM + USCM_84_116/CLK_USCM td 0.000 - 7.537 + 15.759 r - USCMROUTE_2/CLKOUT + clkbufg_0/gopclkbufg/CLKOUT - net (fanout=759) - 1.005 - 8.542 + net (fanout=5464) + 0.895 + 16.654 - ntR3909 + ntclkbufg_0 - DRM_278_356/CLKA[0] + CLMA_34_216/CLK r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[8].U_GTP_DRM18K/iGopDrm/CLKA[0] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[110]/opit_0_inv/CLK clock pessimism - 0.270 - 8.812 + 0.428 + 17.082 @@ -136488,15 +140781,15 @@ clock uncertainty -0.150 - 8.662 + 16.932 Recovery time - -0.088 - 8.574 + 0.000 + 16.932 @@ -136505,27 +140798,27 @@ - 6.770 - 17 - 619 + 6.879 + 16 + 729 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[24]/opit_0_inv/RS + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[116]/opit_0_inv/RS ddrphy_clkin ddrphy_clkin rise-rise - 0.080 + -0.019 7.101 - 6.764 - 0.417 + 6.654 + 0.428 10.000 - 3.160 - 2.144 (67.8%) - 1.016 (32.2%) + 2.952 + 2.031 (68.8%) + 0.921 (31.2%) - Path #4: recovery slack is 6.770(MET) + Path #9: recovery slack is 6.879(MET) -
+
Location Delay Type @@ -136604,7 +140897,7 @@ 0.614 2.807 - zoom_clk + ddr_clk USCM_84_113/CLK_USCM @@ -136616,7 +140909,7 @@ - net (fanout=68) + net (fanout=71) 1.019 3.826 @@ -136644,7 +140937,7 @@ 0.268 4.870 r - clkgate_8/gopclkgate/OUT + clkgate_9/gopclkgate/OUT @@ -136687,7 +140980,7 @@ ntclkbufg_0 - CLMA_70_192/CLK + CLMA_46_192/CLK @@ -136695,7 +140988,7 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK - CLMA_70_192/Q0 + CLMA_46_192/Q0 tco 0.223 7.324 @@ -136704,296 +140997,280 @@ - net (fanout=619) - 1.016 - 8.340 + net (fanout=729) + 0.921 + 8.245 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n - CLMA_10_224/RSCO + CLMA_34_148/RSCO td 0.113 - 8.453 + 8.358 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm/RSOUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[2]/opit_0_inv_L5Q_perm/RSOUT net (fanout=4) 0.000 - 8.453 + 8.358 - ntR1395 + ntR882 - CLMA_10_228/RSCO + CLMA_34_152/RSCO td 0.113 - 8.566 + 8.471 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[4]/opit_0_inv_L5Q_perm/RSOUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[5]/opit_0_inv_L5Q_perm/RSOUT net (fanout=4) 0.000 - 8.566 + 8.471 - ntR1394 + ntR881 - CLMA_10_232/RSCO + CLMA_34_156/RSCO td 0.113 - 8.679 + 8.584 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/RSOUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_we_n_d[0]/opit_0_inv_L5Q_perm/RSOUT net (fanout=4) 0.000 - 8.679 - - ntR1393 - - - CLMA_10_236/RSCO - td - 0.113 - 8.792 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[2]/opit_0_inv_L5Q_perm/RSOUT - - - - net (fanout=6) - 0.000 - 8.792 + 8.584 - ntR1392 + ntR880 - CLMA_10_240/RSCO + CLMA_34_160/RSCO td 0.113 - 8.905 + 8.697 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[246]/opit_0_inv/RSOUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cs_n_d[0]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=4) + net (fanout=2) 0.000 - 8.905 + 8.697 - ntR1391 + ntR879 - CLMA_10_244/RSCO + CLMA_34_164/RSCO td 0.113 - 9.018 + 8.810 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q_perm/RSOUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[4]/opit_0_inv_A2Q21/RSOUT - net (fanout=2) + net (fanout=3) 0.000 - 9.018 + 8.810 - ntR1390 + ntR878 - CLMA_10_248/RSCO + CLMA_34_168/RSCO td 0.113 - 9.131 + 8.923 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[4]/opit_0_inv_A2Q21/RSOUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[0]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=3) + net (fanout=6) 0.000 - 9.131 + 8.923 - ntR1389 + ntR877 - CLMA_10_252/RSCO + CLMA_34_172/RSCO td 0.113 - 9.244 + 9.036 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/opit_0_inv_AQ_perm/RSOUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_r[1]/opit_0_inv/RSOUT - net (fanout=4) + net (fanout=5) 0.000 - 9.244 + 9.036 - ntR1388 + ntR876 - CLMA_10_256/RSCO + CLMA_34_176/RSCO td 0.113 - 9.357 + 9.149 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/opit_0_inv_L5Q_perm/RSOUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/opit_0_inv_L5Q_perm/RSOUT net (fanout=2) 0.000 - 9.357 + 9.149 - ntR1387 + ntR875 - CLMA_10_260/RSCO + CLMA_34_180/RSCO td 0.113 - 9.470 + 9.262 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/RSOUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[4]/opit_0_inv_A2Q21/RSOUT net (fanout=2) 0.000 - 9.470 + 9.262 - ntR1386 + ntR874 - CLMA_10_264/RSCO + CLMA_34_184/RSCO td 0.113 - 9.583 + 9.375 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[4]/opit_0_inv_A2Q21/RSOUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[8]/opit_0_inv_A2Q21/RSOUT - net (fanout=3) + net (fanout=2) 0.000 - 9.583 + 9.375 - ntR1385 + ntR873 - CLMA_10_268/RSCO + CLMA_34_192/RSCO td 0.113 - 9.696 + 9.488 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/opit_0_inv_AQ/RSOUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[12]/opit_0_inv_A2Q21/RSOUT - net (fanout=3) + net (fanout=2) 0.000 - 9.696 + 9.488 - ntR1384 + ntR872 - CLMA_10_272/RSCO + CLMA_34_196/RSCO td 0.113 - 9.809 + 9.601 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs/opit_0_inv/RSOUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[16]/opit_0_inv_A2Q21/RSOUT - net (fanout=2) + net (fanout=1) 0.000 - 9.809 + 9.601 - ntR1383 + ntR871 - CLMA_10_276/RSCO + CLMA_34_200/RSCO td 0.113 - 9.922 + 9.714 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[3]/opit_0_inv_A2Q21/RSOUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[17]/opit_0_inv_AQ_perm/RSOUT - net (fanout=2) + net (fanout=6) 0.000 - 9.922 + 9.714 - ntR1382 + ntR870 - CLMA_10_280/RSCO + CLMA_34_204/RSCO td 0.113 - 10.035 + 9.827 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[7]/opit_0_inv_A2Q21/RSOUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[1]/opit_0_inv/RSOUT - net (fanout=4) + net (fanout=5) 0.000 - 10.035 + 9.827 - ntR1381 + ntR869 - CLMA_10_284/RSCO + CLMA_34_208/RSCO td 0.113 - 10.148 + 9.940 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm/RSOUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[238]/opit_0_inv/RSOUT - net (fanout=4) + net (fanout=5) 0.000 - 10.148 + 9.940 - ntR1380 + ntR868 - CLMA_10_288/RSCO + CLMA_34_212/RSCO td 0.113 - 10.261 + 10.053 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[223]/opit_0_inv_L5Q_perm/RSOUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[86]/opit_0_inv/RSOUT - net (fanout=6) + net (fanout=5) 0.000 - 10.261 + 10.053 - ntR1379 + ntR867 - CLMA_10_292/RSCI + CLMA_34_216/RSCI f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[24]/opit_0_inv/RS + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[116]/opit_0_inv/RS
- +
Location Delay Type @@ -137072,7 +141349,7 @@ 0.603 12.537 - zoom_clk + ddr_clk USCM_84_113/CLK_USCM @@ -137084,7 +141361,7 @@ - net (fanout=68) + net (fanout=71) 0.981 13.518 @@ -137112,7 +141389,7 @@ 0.200 14.476 r - clkgate_8/gopclkgate/OUT + clkgate_9/gopclkgate/OUT @@ -137149,24 +141426,24 @@ net (fanout=5464) - 1.005 - 16.764 + 0.895 + 16.654 ntclkbufg_0 - CLMA_10_292/CLK + CLMA_34_216/CLK r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[24]/opit_0_inv/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[116]/opit_0_inv/CLK clock pessimism - 0.417 - 17.181 + 0.428 + 17.082 @@ -137174,7 +141451,7 @@ clock uncertainty -0.150 - 17.031 + 16.932 @@ -137182,7 +141459,7 @@ Recovery time 0.000 - 17.031 + 16.932 @@ -137191,27 +141468,27 @@ - 6.770 - 17 - 619 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[58]/opit_0_inv/RS + 10.123 + 14 + 911 + sync_vg_100m/opit_0_inv_L5Q_perm/CLK + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0/RS - ddrphy_clkin - ddrphy_clkin + clk_720p60Hz + clk_720p60Hz rise-rise - 0.080 - 7.101 - 6.764 - 0.417 - 10.000 - 3.160 - 2.144 (67.8%) - 1.016 (32.2%) + -0.032 + 5.990 + 5.626 + 0.332 + 13.473 + 3.168 + 1.803 (56.9%) + 1.365 (43.1%) - Path #5: recovery slack is 6.770(MET) + Path #10: recovery slack is 10.123(MET) -
+
Location Delay Type @@ -137221,7 +141498,7 @@ Logical Resource - Clock ddrphy_clkin (rising edge) + Clock clk_720p60Hz (rising edge) 0.000 0.000 @@ -137277,409 +141554,329 @@ _N69 - PLL_158_55/CLK_OUT1 + PLL_158_55/CLK_OUT0 td - 0.079 - 2.193 + 0.083 + 2.197 r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 + u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 0.614 - 2.807 + 2.811 - zoom_clk + rd3_clk - USCM_84_113/CLK_USCM + USCM_84_154/CLK_USCM td 0.000 - 2.807 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.019 - 3.826 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.094 - 3.920 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 0.682 - 4.602 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.268 - 4.870 + 2.811 r - clkgate_8/gopclkgate/OUT + USCMROUTE_0/CLKOUT net (fanout=1) - 0.000 - 4.870 + 1.131 + 3.942 - ntclkgate_0 + ntR3950 - IOCKDIV_6_323/CLK_IODIV + PLL_158_303/CLK_OUT1 td - 0.000 - 4.870 + 0.079 + 4.021 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - net (fanout=1) - 1.306 - 6.176 + net (fanout=2) + 0.932 + 4.953 - u_axi_ddr_top/clk + nt_pix_clk - USCM_84_116/CLK_USCM + USCM_84_117/CLK_USCM td 0.000 - 6.176 + 4.953 r - clkbufg_0/gopclkbufg/CLKOUT + clkbufg_2/gopclkbufg/CLKOUT - net (fanout=5464) - 0.925 - 7.101 + net (fanout=1635) + 1.037 + 5.990 - ntclkbufg_0 + ntclkbufg_2 - CLMA_70_192/CLK + CLMA_150_276/CLK r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK + sync_vg_100m/opit_0_inv_L5Q_perm/CLK - CLMA_70_192/Q0 + CLMA_150_276/Q0 tco - 0.223 - 7.324 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q - - - - net (fanout=619) - 1.016 - 8.340 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n - - - CLMA_10_224/RSCO - td - 0.113 - 8.453 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm/RSOUT - - - - net (fanout=4) - 0.000 - 8.453 - - ntR1395 - - - CLMA_10_228/RSCO - td - 0.113 - 8.566 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[4]/opit_0_inv_L5Q_perm/RSOUT - - - - net (fanout=4) - 0.000 - 8.566 - - ntR1394 - - - CLMA_10_232/RSCO - td - 0.113 - 8.679 + 0.221 + 6.211 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/RSOUT + sync_vg_100m/opit_0_inv_L5Q_perm/Q - net (fanout=4) - 0.000 - 8.679 + net (fanout=911) + 1.365 + 7.576 - ntR1393 + sync_vg_100m - CLMA_10_236/RSCO + CLMA_190_240/RSCO td 0.113 - 8.792 + 7.689 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[2]/opit_0_inv_L5Q_perm/RSOUT + udp_wr_mem_inst/mem[39]/opit_0/RSOUT - net (fanout=6) + net (fanout=3) 0.000 - 8.792 + 7.689 - ntR1392 + ntR687 - CLMA_10_240/RSCO + CLMA_190_244/RSCO td 0.113 - 8.905 + 7.802 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[246]/opit_0_inv/RSOUT + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[4]/opit_0/RSOUT net (fanout=4) 0.000 - 8.905 + 7.802 - ntR1391 + ntR686 - CLMA_10_244/RSCO + CLMA_190_248/RSCO td 0.113 - 9.018 + 7.915 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q_perm/RSOUT + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[40]/opit_0_L5Q_perm/RSOUT net (fanout=2) 0.000 - 9.018 + 7.915 - ntR1390 + ntR685 - CLMA_10_248/RSCO + CLMA_190_252/RSCO td 0.113 - 9.131 + 8.028 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[4]/opit_0_inv_A2Q21/RSOUT + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[7]/opit_0/RSOUT - net (fanout=3) + net (fanout=6) 0.000 - 9.131 + 8.028 - ntR1389 + ntR684 - CLMA_10_252/RSCO + CLMA_190_256/RSCO td 0.113 - 9.244 + 8.141 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/opit_0_inv_AQ_perm/RSOUT + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[7]/opit_0/RSOUT - net (fanout=4) + net (fanout=5) 0.000 - 9.244 + 8.141 - ntR1388 + ntR683 - CLMA_10_256/RSCO + CLMA_190_260/RSCO td 0.113 - 9.357 + 8.254 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/opit_0_inv_L5Q_perm/RSOUT + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[27]/opit_0_L5Q_perm/RSOUT - net (fanout=2) + net (fanout=6) 0.000 - 9.357 + 8.254 - ntR1387 + ntR682 - CLMA_10_260/RSCO + CLMA_190_264/RSCO td 0.113 - 9.470 + 8.367 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/RSOUT + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[22]/opit_0/RSOUT - net (fanout=2) + net (fanout=4) 0.000 - 9.470 + 8.367 - ntR1386 + ntR681 - CLMA_10_264/RSCO + CLMA_190_268/RSCO td 0.113 - 9.583 + 8.480 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[4]/opit_0_inv_A2Q21/RSOUT + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[30]/opit_0_L5Q_perm/RSOUT - net (fanout=3) + net (fanout=4) 0.000 - 9.583 + 8.480 - ntR1385 + ntR680 - CLMA_10_268/RSCO + CLMA_190_272/RSCO td 0.113 - 9.696 + 8.593 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/opit_0_inv_AQ/RSOUT + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[4]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=3) + net (fanout=4) 0.000 - 9.696 + 8.593 - ntR1384 + ntR679 - CLMA_10_272/RSCO + CLMA_190_276/RSCO td 0.113 - 9.809 + 8.706 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs/opit_0_inv/RSOUT + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[23]/opit_0/RSOUT - net (fanout=2) + net (fanout=4) 0.000 - 9.809 + 8.706 - ntR1383 + ntR678 - CLMA_10_276/RSCO + CLMA_190_280/RSCO td 0.113 - 9.922 + 8.819 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[3]/opit_0_inv_A2Q21/RSOUT + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][1]/opit_0/RSOUT - net (fanout=2) + net (fanout=4) 0.000 - 9.922 + 8.819 - ntR1382 + ntR677 - CLMA_10_280/RSCO + CLMA_190_284/RSCO td 0.113 - 10.035 + 8.932 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[7]/opit_0_inv_A2Q21/RSOUT + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/RSOUT - net (fanout=4) + net (fanout=6) 0.000 - 10.035 + 8.932 - ntR1381 + ntR676 - CLMA_10_284/RSCO + CLMA_190_288/RSCO td 0.113 - 10.148 + 9.045 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm/RSOUT + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[29]/opit_0/RSOUT - net (fanout=4) + net (fanout=1) 0.000 - 10.148 + 9.045 - ntR1380 + ntR675 - CLMA_10_288/RSCO + CLMA_190_292/RSCO td 0.113 - 10.261 + 9.158 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[223]/opit_0_inv_L5Q_perm/RSOUT + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][1]/opit_0/RSOUT net (fanout=6) 0.000 - 10.261 + 9.158 - ntR1379 + ntR674 - CLMA_10_292/RSCI + CLMA_190_296/RSCI f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[58]/opit_0_inv/RS + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0/RS
- +
Location Delay Type @@ -137689,10 +141886,10 @@ Logical Resource - Clock ddrphy_clkin (rising edge) + Clock clk_720p60Hz (rising edge) - 10.000 - 10.000 + 13.473 + 13.473 r @@ -137700,7 +141897,7 @@ P200.000 - 10.000 + 13.473rclk (port) @@ -137708,7 +141905,7 @@ net (fanout=1) 0.074 - 10.074 + 13.547 clk @@ -137716,7 +141913,7 @@ IOBS_LR_328_209/DIN td 1.285 - 11.359 + 14.832 r clk_ibuf/opit_0/O @@ -137724,7 +141921,7 @@ net (fanout=1) 0.000 - 11.359 + 14.832 clk_ibuf/ntD @@ -137732,7 +141929,7 @@ IOL_327_210/INCK td 0.038 - 11.397 + 14.870 r clk_ibuf/opit_1/INCK @@ -137740,119 +141937,87 @@ net (fanout=1) 0.463 - 11.860 + 15.333 _N69 - PLL_158_55/CLK_OUT1 + PLL_158_55/CLK_OUT0 td - 0.074 - 11.934 + 0.078 + 15.411 r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 + u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 0.603 - 12.537 + 16.014 - zoom_clk + rd3_clk - USCM_84_113/CLK_USCM + USCM_84_154/CLK_USCM td 0.000 - 12.537 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 0.981 - 13.518 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.089 - 13.607 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 0.669 - 14.276 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.200 - 14.476 + 16.014 r - clkgate_8/gopclkgate/OUT + USCMROUTE_0/CLKOUT net (fanout=1) - 0.000 - 14.476 + 1.091 + 17.105 - ntclkgate_0 + ntR3950 - IOCKDIV_6_323/CLK_IODIV + PLL_158_303/CLK_OUT1 td - 0.000 - 14.476 + 0.074 + 17.179 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - net (fanout=1) - 1.283 - 15.759 + net (fanout=2) + 0.915 + 18.094 - u_axi_ddr_top/clk + nt_pix_clk - USCM_84_116/CLK_USCM + USCM_84_117/CLK_USCM td 0.000 - 15.759 + 18.094 r - clkbufg_0/gopclkbufg/CLKOUT + clkbufg_2/gopclkbufg/CLKOUT - net (fanout=5464) + net (fanout=1635) 1.005 - 16.764 + 19.099 - ntclkbufg_0 + ntclkbufg_2 - CLMA_10_292/CLK + CLMA_190_296/CLK r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[58]/opit_0_inv/CLK + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/opit_0/CLK clock pessimism - 0.417 - 17.181 + 0.332 + 19.431 @@ -137860,7 +142025,7 @@ clock uncertainty -0.150 - 17.031 + 19.281 @@ -137868,7 +142033,7 @@ Recovery time 0.000 - 17.031 + 19.281 @@ -137877,27 +142042,27 @@ - 6.770 - 17 - 619 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[60]/opit_0_inv/RS + 10.123 + 14 + 911 + sync_vg_100m/opit_0_inv_L5Q_perm/CLK + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/opit_0/RS - ddrphy_clkin - ddrphy_clkin + clk_720p60Hz + clk_720p60Hz rise-rise - 0.080 - 7.101 - 6.764 - 0.417 - 10.000 - 3.160 - 2.144 (67.8%) - 1.016 (32.2%) + -0.032 + 5.990 + 5.626 + 0.332 + 13.473 + 3.168 + 1.803 (56.9%) + 1.365 (43.1%) - Path #6: recovery slack is 6.770(MET) + Path #11: recovery slack is 10.123(MET) -
+
Location Delay Type @@ -137907,7 +142072,7 @@ Logical Resource - Clock ddrphy_clkin (rising edge) + Clock clk_720p60Hz (rising edge) 0.000 0.000 @@ -137963,409 +142128,329 @@ _N69 - PLL_158_55/CLK_OUT1 + PLL_158_55/CLK_OUT0 td - 0.079 - 2.193 + 0.083 + 2.197 r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 + u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 0.614 - 2.807 + 2.811 - zoom_clk + rd3_clk - USCM_84_113/CLK_USCM + USCM_84_154/CLK_USCM td 0.000 - 2.807 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.019 - 3.826 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.094 - 3.920 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 0.682 - 4.602 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.268 - 4.870 + 2.811 r - clkgate_8/gopclkgate/OUT + USCMROUTE_0/CLKOUT net (fanout=1) - 0.000 - 4.870 + 1.131 + 3.942 - ntclkgate_0 + ntR3950 - IOCKDIV_6_323/CLK_IODIV + PLL_158_303/CLK_OUT1 td - 0.000 - 4.870 + 0.079 + 4.021 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - net (fanout=1) - 1.306 - 6.176 + net (fanout=2) + 0.932 + 4.953 - u_axi_ddr_top/clk + nt_pix_clk - USCM_84_116/CLK_USCM + USCM_84_117/CLK_USCM td 0.000 - 6.176 + 4.953 r - clkbufg_0/gopclkbufg/CLKOUT + clkbufg_2/gopclkbufg/CLKOUT - net (fanout=5464) - 0.925 - 7.101 + net (fanout=1635) + 1.037 + 5.990 - ntclkbufg_0 + ntclkbufg_2 - CLMA_70_192/CLK + CLMA_150_276/CLK r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK + sync_vg_100m/opit_0_inv_L5Q_perm/CLK - CLMA_70_192/Q0 + CLMA_150_276/Q0 tco - 0.223 - 7.324 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q - - - - net (fanout=619) - 1.016 - 8.340 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n - - - CLMA_10_224/RSCO - td - 0.113 - 8.453 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm/RSOUT - - - - net (fanout=4) - 0.000 - 8.453 - - ntR1395 - - - CLMA_10_228/RSCO - td - 0.113 - 8.566 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[4]/opit_0_inv_L5Q_perm/RSOUT - - - - net (fanout=4) - 0.000 - 8.566 - - ntR1394 - - - CLMA_10_232/RSCO - td - 0.113 - 8.679 + 0.221 + 6.211 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/RSOUT + sync_vg_100m/opit_0_inv_L5Q_perm/Q - net (fanout=4) - 0.000 - 8.679 + net (fanout=911) + 1.365 + 7.576 - ntR1393 + sync_vg_100m - CLMA_10_236/RSCO + CLMA_190_240/RSCO td 0.113 - 8.792 + 7.689 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[2]/opit_0_inv_L5Q_perm/RSOUT + udp_wr_mem_inst/mem[39]/opit_0/RSOUT - net (fanout=6) + net (fanout=3) 0.000 - 8.792 + 7.689 - ntR1392 + ntR687 - CLMA_10_240/RSCO + CLMA_190_244/RSCO td 0.113 - 8.905 + 7.802 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[246]/opit_0_inv/RSOUT + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[4]/opit_0/RSOUT net (fanout=4) 0.000 - 8.905 + 7.802 - ntR1391 + ntR686 - CLMA_10_244/RSCO + CLMA_190_248/RSCO td 0.113 - 9.018 + 7.915 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/opit_0_inv_L5Q_perm/RSOUT + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[40]/opit_0_L5Q_perm/RSOUT net (fanout=2) 0.000 - 9.018 + 7.915 - ntR1390 + ntR685 - CLMA_10_248/RSCO + CLMA_190_252/RSCO td 0.113 - 9.131 + 8.028 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[4]/opit_0_inv_A2Q21/RSOUT + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[7]/opit_0/RSOUT - net (fanout=3) + net (fanout=6) 0.000 - 9.131 + 8.028 - ntR1389 + ntR684 - CLMA_10_252/RSCO + CLMA_190_256/RSCO td 0.113 - 9.244 + 8.141 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/opit_0_inv_AQ_perm/RSOUT + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[7]/opit_0/RSOUT - net (fanout=4) + net (fanout=5) 0.000 - 9.244 + 8.141 - ntR1388 + ntR683 - CLMA_10_256/RSCO + CLMA_190_260/RSCO td 0.113 - 9.357 + 8.254 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/opit_0_inv_L5Q_perm/RSOUT + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[27]/opit_0_L5Q_perm/RSOUT - net (fanout=2) + net (fanout=6) 0.000 - 9.357 + 8.254 - ntR1387 + ntR682 - CLMA_10_260/RSCO + CLMA_190_264/RSCO td 0.113 - 9.470 + 8.367 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/opit_0_inv_L5Q_perm/RSOUT + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[22]/opit_0/RSOUT - net (fanout=2) + net (fanout=4) 0.000 - 9.470 + 8.367 - ntR1386 + ntR681 - CLMA_10_264/RSCO + CLMA_190_268/RSCO td 0.113 - 9.583 + 8.480 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[4]/opit_0_inv_A2Q21/RSOUT + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[30]/opit_0_L5Q_perm/RSOUT - net (fanout=3) + net (fanout=4) 0.000 - 9.583 + 8.480 - ntR1385 + ntR680 - CLMA_10_268/RSCO + CLMA_190_272/RSCO td 0.113 - 9.696 + 8.593 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/opit_0_inv_AQ/RSOUT + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[4]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=3) + net (fanout=4) 0.000 - 9.696 + 8.593 - ntR1384 + ntR679 - CLMA_10_272/RSCO + CLMA_190_276/RSCO td 0.113 - 9.809 + 8.706 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs/opit_0_inv/RSOUT + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[23]/opit_0/RSOUT - net (fanout=2) + net (fanout=4) 0.000 - 9.809 + 8.706 - ntR1383 + ntR678 - CLMA_10_276/RSCO + CLMA_190_280/RSCO td 0.113 - 9.922 + 8.819 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[3]/opit_0_inv_A2Q21/RSOUT + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][1]/opit_0/RSOUT - net (fanout=2) + net (fanout=4) 0.000 - 9.922 + 8.819 - ntR1382 + ntR677 - CLMA_10_280/RSCO + CLMA_190_284/RSCO td 0.113 - 10.035 + 8.932 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[7]/opit_0_inv_A2Q21/RSOUT + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/RSOUT - net (fanout=4) + net (fanout=6) 0.000 - 10.035 + 8.932 - ntR1381 + ntR676 - CLMA_10_284/RSCO + CLMA_190_288/RSCO td 0.113 - 10.148 + 9.045 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/opit_0_inv_L5Q_perm/RSOUT + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[29]/opit_0/RSOUT - net (fanout=4) + net (fanout=1) 0.000 - 10.148 + 9.045 - ntR1380 + ntR675 - CLMA_10_288/RSCO + CLMA_190_292/RSCO td 0.113 - 10.261 + 9.158 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[223]/opit_0_inv_L5Q_perm/RSOUT + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][1]/opit_0/RSOUT net (fanout=6) 0.000 - 10.261 + 9.158 - ntR1379 + ntR674 - CLMA_10_292/RSCI + CLMA_190_296/RSCI f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[60]/opit_0_inv/RS + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/opit_0/RS
- +
Location Delay Type @@ -138375,10 +142460,10 @@ Logical Resource - Clock ddrphy_clkin (rising edge) + Clock clk_720p60Hz (rising edge) - 10.000 - 10.000 + 13.473 + 13.473 r @@ -138386,7 +142471,7 @@ P200.000 - 10.000 + 13.473rclk (port) @@ -138394,7 +142479,7 @@ net (fanout=1) 0.074 - 10.074 + 13.547 clk @@ -138402,7 +142487,7 @@ IOBS_LR_328_209/DIN td 1.285 - 11.359 + 14.832 r clk_ibuf/opit_0/O @@ -138410,7 +142495,7 @@ net (fanout=1) 0.000 - 11.359 + 14.832 clk_ibuf/ntD @@ -138418,7 +142503,7 @@ IOL_327_210/INCK td 0.038 - 11.397 + 14.870 r clk_ibuf/opit_1/INCK @@ -138426,119 +142511,87 @@ net (fanout=1) 0.463 - 11.860 + 15.333 _N69 - PLL_158_55/CLK_OUT1 + PLL_158_55/CLK_OUT0 td - 0.074 - 11.934 + 0.078 + 15.411 r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 + u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 0.603 - 12.537 + 16.014 - zoom_clk + rd3_clk - USCM_84_113/CLK_USCM + USCM_84_154/CLK_USCM td 0.000 - 12.537 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 0.981 - 13.518 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.089 - 13.607 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 0.669 - 14.276 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.200 - 14.476 + 16.014 r - clkgate_8/gopclkgate/OUT + USCMROUTE_0/CLKOUT net (fanout=1) - 0.000 - 14.476 + 1.091 + 17.105 - ntclkgate_0 + ntR3950 - IOCKDIV_6_323/CLK_IODIV + PLL_158_303/CLK_OUT1 td - 0.000 - 14.476 + 0.074 + 17.179 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - net (fanout=1) - 1.283 - 15.759 + net (fanout=2) + 0.915 + 18.094 - u_axi_ddr_top/clk + nt_pix_clk - USCM_84_116/CLK_USCM + USCM_84_117/CLK_USCM td 0.000 - 15.759 + 18.094 r - clkbufg_0/gopclkbufg/CLKOUT + clkbufg_2/gopclkbufg/CLKOUT - net (fanout=5464) + net (fanout=1635) 1.005 - 16.764 + 19.099 - ntclkbufg_0 + ntclkbufg_2 - CLMA_10_292/CLK + CLMA_190_296/CLK r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[60]/opit_0_inv/CLK + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/opit_0/CLK clock pessimism - 0.417 - 17.181 + 0.332 + 19.431 @@ -138546,7 +142599,7 @@ clock uncertainty -0.150 - 17.031 + 19.281 @@ -138554,7 +142607,7 @@ Recovery time 0.000 - 17.031 + 19.281 @@ -138563,27 +142616,27 @@ - 9.915 - 10 - 1066 + 10.123 + 14 + 911 sync_vg_100m/opit_0_inv_L5Q_perm/CLK - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[4]/opit_0_L5Q_perm/RS + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/RS clk_720p60Hz clk_720p60Hz rise-rise - -0.030 - 5.878 - 5.516 + -0.032 + 5.990 + 5.626 0.332 13.473 - 3.378 - 1.351 (40.0%) - 2.027 (60.0%) + 3.168 + 1.803 (56.9%) + 1.365 (43.1%) - Path #7: recovery slack is 9.915(MET) + Path #12: recovery slack is 10.123(MET) -
+
Location Delay Type @@ -138678,7 +142731,7 @@ 1.131 3.942 - ntR3907 + ntR3950 PLL_158_303/CLK_OUT1 @@ -138707,13 +142760,13 @@ net (fanout=1635) - 0.925 - 5.878 + 1.037 + 5.990 ntclkbufg_2 - CLMS_150_245/CLK + CLMA_150_276/CLK @@ -138721,193 +142774,257 @@ sync_vg_100m/opit_0_inv_L5Q_perm/CLK - CLMS_150_245/Q0 + CLMA_150_276/Q0 tco 0.221 - 6.099 + 6.211 f sync_vg_100m/opit_0_inv_L5Q_perm/Q - net (fanout=1066) - 2.027 - 8.126 + net (fanout=911) + 1.365 + 7.576 sync_vg_100m - CLMA_294_132/RSCO + CLMA_190_240/RSCO td 0.113 - 8.239 + 7.689 f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/remainder[3]/opit_0_L5Q_perm/RSOUT + udp_wr_mem_inst/mem[39]/opit_0/RSOUT - net (fanout=4) + net (fanout=3) 0.000 - 8.239 + 7.689 - ntR491 + ntR687 - CLMA_294_136/RSCO + CLMA_190_244/RSCO td 0.113 - 8.352 + 7.802 f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm/RSOUT + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[4]/opit_0/RSOUT net (fanout=4) 0.000 - 8.352 + 7.802 - ntR490 + ntR686 - CLMA_294_140/RSCO + CLMA_190_248/RSCO td 0.113 - 8.465 + 7.915 f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[2]/opit_0_L5Q_perm/RSOUT + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_mac_t[40]/opit_0_L5Q_perm/RSOUT - net (fanout=1) + net (fanout=2) 0.000 - 8.465 + 7.915 - ntR489 + ntR685 - CLMA_294_144/RSCO + CLMA_190_252/RSCO td 0.113 - 8.578 + 8.028 f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/remainder[2]/opit_0_A2Q21/RSOUT + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[7]/opit_0/RSOUT - net (fanout=2) + net (fanout=6) 0.000 - 8.578 + 8.028 - ntR488 + ntR684 - CLMA_294_148/RSCO + CLMA_190_256/RSCO td 0.113 - 8.691 + 8.141 f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/remainder[6]/opit_0_A2Q21/RSOUT + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_mac_t[7]/opit_0/RSOUT - net (fanout=4) + net (fanout=5) + 0.000 + 8.141 + + ntR683 + + + CLMA_190_260/RSCO + td + 0.113 + 8.254 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[27]/opit_0_L5Q_perm/RSOUT + + + + net (fanout=6) 0.000 - 8.691 + 8.254 - ntR487 + ntR682 - CLMA_294_152/RSCO + CLMA_190_264/RSCO td 0.113 - 8.804 + 8.367 f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm/RSOUT + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/des_ip_t[22]/opit_0/RSOUT net (fanout=4) 0.000 - 8.804 + 8.367 - ntR486 + ntR681 - CLMA_294_156/RSCO + CLMA_190_268/RSCO td 0.113 - 8.917 + 8.480 f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/dividend_kp[11]/opit_0_L5Q_perm/RSOUT + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip_t[30]/opit_0_L5Q_perm/RSOUT net (fanout=4) 0.000 - 8.917 + 8.480 - ntR485 + ntR680 - CLMA_294_160/RSCO + CLMA_190_272/RSCO td 0.113 - 9.030 + 8.593 f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[2]/opit_0_L5Q_perm/RSOUT + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[4]/opit_0_inv_L5Q_perm/RSOUT - net (fanout=2) + net (fanout=4) 0.000 - 9.030 + 8.593 - ntR484 + ntR679 - CLMA_294_164/RSCO + CLMA_190_276/RSCO td 0.113 - 9.143 + 8.706 f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[2]/opit_0_A2Q21/RSOUT + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[23]/opit_0/RSOUT - net (fanout=2) + net (fanout=4) 0.000 - 9.143 + 8.706 - ntR483 + ntR678 - CLMA_294_168/RSCO + CLMA_190_280/RSCO td 0.113 - 9.256 + 8.819 f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[6]/opit_0_A2Q21/RSOUT + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[27][1]/opit_0/RSOUT net (fanout=4) 0.000 - 9.256 + 8.819 + + ntR677 + + + CLMA_190_284/RSCO + td + 0.113 + 8.932 + f + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/RSOUT + + + + net (fanout=6) + 0.000 + 8.932 + + ntR676 + + + CLMA_190_288/RSCO + td + 0.113 + 9.045 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/src_ip[29]/opit_0/RSOUT + + + + net (fanout=1) + 0.000 + 9.045 + + ntR675 + + + CLMA_190_292/RSCO + td + 0.113 + 9.158 + f + udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/arp_data[25][1]/opit_0/RSOUT + + + + net (fanout=6) + 0.000 + 9.158 - ntR482 + ntR674 - CLMA_294_172/RSCI + CLMA_190_296/RSCI f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[4]/opit_0_L5Q_perm/RS + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/RS
- +
Location Delay Type @@ -139002,7 +143119,7 @@ 1.091 17.105 - ntR3907 + ntR3950 PLL_158_303/CLK_OUT1 @@ -139031,24 +143148,24 @@ net (fanout=1635) - 0.895 - 18.989 + 1.005 + 19.099 ntclkbufg_2 - CLMA_294_172/CLK + CLMA_190_296/CLK r - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[4]/opit_0_L5Q_perm/CLK + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/CLK clock pessimism 0.332 - 19.321 + 19.431 @@ -139056,7 +143173,7 @@ clock uncertainty -0.150 - 19.171 + 19.281 @@ -139064,7 +143181,7 @@ Recovery time 0.000 - 19.171 + 19.281 @@ -139073,27 +143190,27 @@ - 9.915 - 10 - 1066 - sync_vg_100m/opit_0_inv_L5Q_perm/CLK - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[6]/opit_0_L5Q_perm/RS + 16.962 + 0 + 589 + u_clk50m_rst/rst/opit_0_L5Q_perm/CLK + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/RS - clk_720p60Hz - clk_720p60Hz + clk_50m + clk_50m rise-rise - -0.030 - 5.878 - 5.516 - 0.332 - 13.473 - 3.378 - 1.351 (40.0%) - 2.027 (60.0%) + -0.018 + 3.736 + 3.448 + 0.270 + 20.000 + 2.394 + 0.221 (9.2%) + 2.173 (90.8%) - Path #8: recovery slack is 9.915(MET) + Path #13: recovery slack is 16.962(MET) -
+
Location Delay Type @@ -139103,7 +143220,7 @@ Logical Resource - Clock clk_720p60Hz (rising edge) + Clock clk_50m (rising edge) 0.000 0.000 @@ -139175,249 +143292,343 @@ rd3_clk - USCM_84_154/CLK_USCM + USCM_84_108/CLK_USCM td 0.000 2.811 r - USCMROUTE_0/CLKOUT + clkbufg_1/gopclkbufg/CLKOUT - net (fanout=1) - 1.131 - 3.942 + net (fanout=2516) + 0.925 + 3.736 - ntR3907 + ntclkbufg_1 - PLL_158_303/CLK_OUT1 - td - 0.079 - 4.021 + CLMS_158_237/CLK + + + r - U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + u_clk50m_rst/rst/opit_0_L5Q_perm/CLK + + + CLMS_158_237/Q0 + tco + 0.221 + 3.957 + f + u_clk50m_rst/rst/opit_0_L5Q_perm/Q - net (fanout=2) - 0.932 - 4.953 + net (fanout=589) + 2.173 + 6.130 + + rd3_rst + + + CLMA_58_40/RS + + + + f + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/RS + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_50m (rising edge) + + 20.000 + 20.000 + r - nt_pix_clk - USCM_84_117/CLK_USCM - td + P20 + 0.000 - 4.953 + 20.000 r - clkbufg_2/gopclkbufg/CLKOUT + clk (port) - net (fanout=1635) - 0.925 - 5.878 + net (fanout=1) + 0.074 + 20.074 - ntclkbufg_2 + clk + + + IOBS_LR_328_209/DIN + td + 1.285 + 21.359 + r + clk_ibuf/opit_0/O - CLMS_150_245/CLK - + net (fanout=1) + 0.000 + 21.359 - r - sync_vg_100m/opit_0_inv_L5Q_perm/CLK + clk_ibuf/ntD - CLMS_150_245/Q0 - tco - 0.221 - 6.099 - f - sync_vg_100m/opit_0_inv_L5Q_perm/Q + IOL_327_210/INCK + td + 0.038 + 21.397 + r + clk_ibuf/opit_1/INCK - net (fanout=1066) - 2.027 - 8.126 - - sync_vg_100m + net (fanout=1) + 0.463 + 21.860 + + _N69 - CLMA_294_132/RSCO + PLL_158_55/CLK_OUT0 td - 0.113 - 8.239 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/remainder[3]/opit_0_L5Q_perm/RSOUT + 0.078 + 21.938 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 - net (fanout=4) - 0.000 - 8.239 - - ntR491 + net (fanout=2) + 0.603 + 22.541 + + rd3_clk - CLMA_294_136/RSCO + USCM_84_108/CLK_USCM td - 0.113 - 8.352 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm/RSOUT + 0.000 + 22.541 + r + clkbufg_1/gopclkbufg/CLKOUT - net (fanout=4) - 0.000 - 8.352 - - ntR490 + net (fanout=2516) + 0.907 + 23.448 + + ntclkbufg_1 - CLMA_294_140/RSCO - td - 0.113 - 8.465 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[2]/opit_0_L5Q_perm/RSOUT + CLMA_58_40/CLK + + + + r + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/opit_0_L5Q_perm/CLK + clock pessimism + + 0.270 + 23.718 + - net (fanout=1) - 0.000 - 8.465 - - ntR489 - CLMA_294_144/RSCO - td - 0.113 - 8.578 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/remainder[2]/opit_0_A2Q21/RSOUT + clock uncertainty + + -0.150 + 23.568 + + + Recovery time + + -0.476 + 23.092 + + + +
+
+
+
+ + 17.074 + 0 + 589 + u_clk50m_rst/rst/opit_0_L5Q_perm/CLK + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[1]/opit_0_A2Q21/RS + + clk_50m + clk_50m + rise-rise + -0.010 + 3.736 + 3.456 + 0.270 + 20.000 + 2.290 + 0.221 (9.7%) + 2.069 (90.3%) + + Path #14: recovery slack is 17.074(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_50m (rising edge) - net (fanout=2) 0.000 - 8.578 - - ntR488 + 0.000 + r + + + + P20 + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.074 + 0.074 + + clk - CLMA_294_148/RSCO + IOBS_LR_328_209/DIN td - 0.113 - 8.691 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/remainder[6]/opit_0_A2Q21/RSOUT + 1.504 + 1.578 + r + clk_ibuf/opit_0/O - net (fanout=4) + net (fanout=1) 0.000 - 8.691 - - ntR487 + 1.578 + + clk_ibuf/ntD - CLMA_294_152/RSCO + IOL_327_210/INCK td - 0.113 - 8.804 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm/RSOUT + 0.058 + 1.636 + r + clk_ibuf/opit_1/INCK - net (fanout=4) - 0.000 - 8.804 - - ntR486 + net (fanout=1) + 0.478 + 2.114 + + _N69 - CLMA_294_156/RSCO + PLL_158_55/CLK_OUT0 td - 0.113 - 8.917 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/dividend_kp[11]/opit_0_L5Q_perm/RSOUT + 0.083 + 2.197 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT0 - net (fanout=4) - 0.000 - 8.917 - - ntR485 + net (fanout=2) + 0.614 + 2.811 + + rd3_clk - CLMA_294_160/RSCO + USCM_84_108/CLK_USCM td - 0.113 - 9.030 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[2]/opit_0_L5Q_perm/RSOUT - - - - net (fanout=2) 0.000 - 9.030 - - ntR484 + 2.811 + r + clkbufg_1/gopclkbufg/CLKOUT - CLMA_294_164/RSCO - td - 0.113 - 9.143 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[2]/opit_0_A2Q21/RSOUT + + net (fanout=2516) + 0.925 + 3.736 + + ntclkbufg_1 + CLMS_158_237/CLK - net (fanout=2) - 0.000 - 9.143 - - ntR483 + + + r + u_clk50m_rst/rst/opit_0_L5Q_perm/CLK - CLMA_294_168/RSCO - td - 0.113 - 9.256 + CLMS_158_237/Q0 + tco + 0.221 + 3.957 f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[6]/opit_0_A2Q21/RSOUT + u_clk50m_rst/rst/opit_0_L5Q_perm/Q - net (fanout=4) - 0.000 - 9.256 + net (fanout=589) + 2.069 + 6.026 - ntR482 + rd3_rst - CLMA_294_172/RSCI + CLMA_58_33/RS f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[6]/opit_0_L5Q_perm/RS + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[1]/opit_0_A2Q21/RS
- +
Location Delay Type @@ -139427,10 +143638,10 @@ Logical Resource - Clock clk_720p60Hz (rising edge) + Clock clk_50m (rising edge) - 13.473 - 13.473 + 20.000 + 20.000 r @@ -139438,7 +143649,7 @@ P200.000 - 13.473 + 20.000rclk (port) @@ -139446,7 +143657,7 @@ net (fanout=1) 0.074 - 13.547 + 20.074 clk @@ -139454,7 +143665,7 @@ IOBS_LR_328_209/DIN td 1.285 - 14.832 + 21.359 r clk_ibuf/opit_0/O @@ -139462,7 +143673,7 @@ net (fanout=1) 0.000 - 14.832 + 21.359 clk_ibuf/ntD @@ -139470,7 +143681,7 @@ IOL_327_210/INCK td 0.038 - 14.870 + 21.397 r clk_ibuf/opit_1/INCK @@ -139478,7 +143689,7 @@ net (fanout=1) 0.463 - 15.333 + 21.860 _N69 @@ -139486,7 +143697,7 @@ PLL_158_55/CLK_OUT0 td 0.078 - 15.411 + 21.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 @@ -139494,71 +143705,39 @@ net (fanout=2) 0.603 - 16.014 + 22.541 rd3_clk - USCM_84_154/CLK_USCM + USCM_84_108/CLK_USCM td 0.000 - 16.014 - r - USCMROUTE_0/CLKOUT - - - - net (fanout=1) - 1.091 - 17.105 - - ntR3907 - - - PLL_158_303/CLK_OUT1 - td - 0.074 - 17.179 + 22.541 r - U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2) + net (fanout=2516) 0.915 - 18.094 - - nt_pix_clk - - - USCM_84_117/CLK_USCM - td - 0.000 - 18.094 - r - clkbufg_2/gopclkbufg/CLKOUT - - + 23.456 - net (fanout=1635) - 0.895 - 18.989 - - ntclkbufg_2 + ntclkbufg_1 - CLMA_294_172/CLK + CLMA_58_33/CLK r - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[6]/opit_0_L5Q_perm/CLK + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[1]/opit_0_A2Q21/CLK clock pessimism - 0.332 - 19.321 + 0.270 + 23.726 @@ -139566,15 +143745,15 @@ clock uncertainty -0.150 - 19.171 + 23.576 Recovery time - 0.000 - 19.171 + -0.476 + 23.100 @@ -139583,27 +143762,27 @@ - 9.915 - 10 - 1066 - sync_vg_100m/opit_0_inv_L5Q_perm/CLK - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[7]/opit_0_L5Q_perm/RS + 17.074 + 0 + 589 + u_clk50m_rst/rst/opit_0_L5Q_perm/CLK + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[3]/opit_0_A2Q21/RS - clk_720p60Hz - clk_720p60Hz + clk_50m + clk_50m rise-rise - -0.030 - 5.878 - 5.516 - 0.332 - 13.473 - 3.378 - 1.351 (40.0%) - 2.027 (60.0%) + -0.010 + 3.736 + 3.456 + 0.270 + 20.000 + 2.290 + 0.221 (9.7%) + 2.069 (90.3%) - Path #9: recovery slack is 9.915(MET) + Path #15: recovery slack is 17.074(MET) -
+
Location Delay Type @@ -139613,7 +143792,7 @@ Logical Resource - Clock clk_720p60Hz (rising edge) + Clock clk_50m (rising edge) 0.000 0.000 @@ -139685,249 +143864,57 @@ rd3_clk - USCM_84_154/CLK_USCM + USCM_84_108/CLK_USCM td 0.000 2.811 r - USCMROUTE_0/CLKOUT - - - - net (fanout=1) - 1.131 - 3.942 - - ntR3907 - - - PLL_158_303/CLK_OUT1 - td - 0.079 - 4.021 - r - U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 0.932 - 4.953 - - nt_pix_clk - - - USCM_84_117/CLK_USCM - td - 0.000 - 4.953 - r - clkbufg_2/gopclkbufg/CLKOUT + clkbufg_1/gopclkbufg/CLKOUT - net (fanout=1635) + net (fanout=2516) 0.925 - 5.878 + 3.736 - ntclkbufg_2 + ntclkbufg_1 - CLMS_150_245/CLK + CLMS_158_237/CLK r - sync_vg_100m/opit_0_inv_L5Q_perm/CLK + u_clk50m_rst/rst/opit_0_L5Q_perm/CLK - CLMS_150_245/Q0 + CLMS_158_237/Q0 tco 0.221 - 6.099 - f - sync_vg_100m/opit_0_inv_L5Q_perm/Q - - - - net (fanout=1066) - 2.027 - 8.126 - - sync_vg_100m - - - CLMA_294_132/RSCO - td - 0.113 - 8.239 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/remainder[3]/opit_0_L5Q_perm/RSOUT - - - - net (fanout=4) - 0.000 - 8.239 - - ntR491 - - - CLMA_294_136/RSCO - td - 0.113 - 8.352 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/divisor_kp[3]/opit_0_L5Q_perm/RSOUT - - - - net (fanout=4) - 0.000 - 8.352 - - ntR490 - - - CLMA_294_140/RSCO - td - 0.113 - 8.465 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/divisor_kp[2]/opit_0_L5Q_perm/RSOUT - - - - net (fanout=1) - 0.000 - 8.465 - - ntR489 - - - CLMA_294_144/RSCO - td - 0.113 - 8.578 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/remainder[2]/opit_0_A2Q21/RSOUT - - - - net (fanout=2) - 0.000 - 8.578 - - ntR488 - - - CLMA_294_148/RSCO - td - 0.113 - 8.691 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/u_divider_step0/remainder[6]/opit_0_A2Q21/RSOUT - - - - net (fanout=4) - 0.000 - 8.691 - - ntR487 - - - CLMA_294_152/RSCO - td - 0.113 - 8.804 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[4].u_divider_step/divisor_kp[6]/opit_0_L5Q_perm/RSOUT - - - - net (fanout=4) - 0.000 - 8.804 - - ntR486 - - - CLMA_294_156/RSCO - td - 0.113 - 8.917 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/dividend_kp[11]/opit_0_L5Q_perm/RSOUT - - - - net (fanout=4) - 0.000 - 8.917 - - ntR485 - - - CLMA_294_160/RSCO - td - 0.113 - 9.030 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[2]/opit_0_L5Q_perm/RSOUT - - - - net (fanout=2) - 0.000 - 9.030 - - ntR484 - - - CLMA_294_164/RSCO - td - 0.113 - 9.143 - f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[2]/opit_0_A2Q21/RSOUT - - - - net (fanout=2) - 0.000 - 9.143 - - ntR483 - - - CLMA_294_168/RSCO - td - 0.113 - 9.256 + 3.957 f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/remainder[6]/opit_0_A2Q21/RSOUT + u_clk50m_rst/rst/opit_0_L5Q_perm/Q - net (fanout=4) - 0.000 - 9.256 + net (fanout=589) + 2.069 + 6.026 - ntR482 + rd3_rst - CLMA_294_172/RSCI + CLMA_58_33/RS f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[7]/opit_0_L5Q_perm/RS + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[3]/opit_0_A2Q21/RS
- +
Location Delay Type @@ -139937,10 +143924,10 @@ Logical Resource - Clock clk_720p60Hz (rising edge) + Clock clk_50m (rising edge) - 13.473 - 13.473 + 20.000 + 20.000 r @@ -139948,7 +143935,7 @@ P200.000 - 13.473 + 20.000rclk (port) @@ -139956,7 +143943,7 @@ net (fanout=1) 0.074 - 13.547 + 20.074 clk @@ -139964,7 +143951,7 @@ IOBS_LR_328_209/DIN td 1.285 - 14.832 + 21.359 r clk_ibuf/opit_0/O @@ -139972,7 +143959,7 @@ net (fanout=1) 0.000 - 14.832 + 21.359 clk_ibuf/ntD @@ -139980,7 +143967,7 @@ IOL_327_210/INCK td 0.038 - 14.870 + 21.397 r clk_ibuf/opit_1/INCK @@ -139988,7 +143975,7 @@ net (fanout=1) 0.463 - 15.333 + 21.860 _N69 @@ -139996,7 +143983,7 @@ PLL_158_55/CLK_OUT0 td 0.078 - 15.411 + 21.938 r u_sys_pll/u_pll_e3/goppll/CLKOUT0 @@ -140004,71 +143991,39 @@ net (fanout=2) 0.603 - 16.014 + 22.541 rd3_clk - USCM_84_154/CLK_USCM + USCM_84_108/CLK_USCM td 0.000 - 16.014 - r - USCMROUTE_0/CLKOUT - - - - net (fanout=1) - 1.091 - 17.105 - - ntR3907 - - - PLL_158_303/CLK_OUT1 - td - 0.074 - 17.179 + 22.541 r - U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + clkbufg_1/gopclkbufg/CLKOUT - net (fanout=2) + net (fanout=2516) 0.915 - 18.094 - - nt_pix_clk - - - USCM_84_117/CLK_USCM - td - 0.000 - 18.094 - r - clkbufg_2/gopclkbufg/CLKOUT - - - - net (fanout=1635) - 0.895 - 18.989 + 23.456 - ntclkbufg_2 + ntclkbufg_1 - CLMA_294_172/CLK + CLMA_58_33/CLK r - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/u_divider_step0/divisor_kp[7]/opit_0_L5Q_perm/CLK + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[3]/opit_0_A2Q21/CLK clock pessimism - 0.332 - 19.321 + 0.270 + 23.726 @@ -140076,15 +144031,15 @@ clock uncertainty -0.150 - 19.171 + 23.576 Recovery time - 0.000 - 19.171 + -0.476 + 23.100 @@ -140093,27 +144048,27 @@ - 17.096 - 7 - 573 - u_clk50m_rst/rst/opit_0_L5Q_perm/CLK - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/RS + 98.381 + 0 + 3 + rstn_out1/opit_0_inv/CLK + ms72xx_ctl/rstn_temp1/opit_0_inv/RS - clk_50m - clk_50m + clk_10m + clk_10m rise-rise - -0.030 - 3.736 - 3.436 + 0.080 + 3.737 + 3.547 0.270 - 20.000 - 2.724 - 1.012 (37.2%) - 1.712 (62.8%) + 100.000 + 1.073 + 0.220 (20.5%) + 0.853 (79.5%) - Path #10: recovery slack is 17.096(MET) + Path #16: recovery slack is 98.381(MET) -
+
Location Delay Type @@ -140123,7 +144078,7 @@ Logical Resource - Clock clk_50m (rising edge) + Clock clk_10m (rising edge) 0.000 0.000 @@ -140179,185 +144134,73 @@ _N69 - PLL_158_55/CLK_OUT0 + PLL_158_55/CLK_OUT4 td - 0.083 - 2.197 + 0.084 + 2.198 r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 + u_sys_pll/u_pll_e3/goppll/CLKOUT4 - net (fanout=2) + net (fanout=1) 0.614 - 2.811 + 2.812 - rd3_clk + clk_10m - USCM_84_108/CLK_USCM + USCM_84_110/CLK_USCM td 0.000 - 2.811 + 2.812 r - clkbufg_1/gopclkbufg/CLKOUT + clkbufg_4/gopclkbufg/CLKOUT - net (fanout=2517) + net (fanout=235) 0.925 - 3.736 - - ntclkbufg_1 - - - CLMS_94_177/CLK - - - - r - u_clk50m_rst/rst/opit_0_L5Q_perm/CLK - - - CLMS_94_177/Q0 - tco - 0.221 - 3.957 - f - u_clk50m_rst/rst/opit_0_L5Q_perm/Q - - - - net (fanout=573) - 1.712 - 5.669 - - rd3_rst - - - CLMS_146_37/RSCO - td - 0.113 - 5.782 - f - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/RSOUT - - - - net (fanout=4) - 0.000 - 5.782 - - ntR414 - - - CLMS_146_41/RSCO - td - 0.113 - 5.895 - f - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/RSOUT - - - - net (fanout=4) - 0.000 - 5.895 - - ntR413 - - - CLMS_146_45/RSCO - td - 0.113 - 6.008 - f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/RSOUT - - + 3.737 - net (fanout=3) - 0.000 - 6.008 - - ntR412 - - - CLMS_146_49/RSCO - td - 0.113 - 6.121 - f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/RSOUT + ntclkbufg_4 + CLMS_270_193/CLK - net (fanout=2) - 0.000 - 6.121 - - ntR411 - - - CLMS_146_53/RSCO - td - 0.113 - 6.234 - f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/RSOUT - - - net (fanout=4) - 0.000 - 6.234 - - ntR410 - - - CLMS_146_57/RSCO - td - 0.113 - 6.347 - f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/RSOUT - - - net (fanout=6) - 0.000 - 6.347 - - ntR409 + r + rstn_out1/opit_0_inv/CLK - CLMS_146_61/RSCO - td - 0.113 - 6.460 + CLMS_270_193/Q3 + tco + 0.220 + 3.957 f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/RSOUT + rstn_out1/opit_0_inv/Q - net (fanout=5) - 0.000 - 6.460 + net (fanout=3) + 0.853 + 4.810 - ntR408 + nt_eth_rstn - CLMS_146_69/RSCI + CLMA_262_268/RS f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/RS + ms72xx_ctl/rstn_temp1/opit_0_inv/RS
- +
Location Delay Type @@ -140367,10 +144210,10 @@ Logical Resource - Clock clk_50m (rising edge) + Clock clk_10m (rising edge) - 20.000 - 20.000 + 100.000 + 100.000 r @@ -140378,7 +144221,7 @@ P200.000 - 20.000 + 100.000rclk (port) @@ -140386,7 +144229,7 @@ net (fanout=1) 0.074 - 20.074 + 100.074 clk @@ -140394,7 +144237,7 @@ IOBS_LR_328_209/DIN td 1.285 - 21.359 + 101.359 r clk_ibuf/opit_0/O @@ -140402,7 +144245,7 @@ net (fanout=1) 0.000 - 21.359 + 101.359 clk_ibuf/ntD @@ -140410,7 +144253,7 @@ IOL_327_210/INCK td 0.038 - 21.397 + 101.397 r clk_ibuf/opit_1/INCK @@ -140418,55 +144261,55 @@ net (fanout=1) 0.463 - 21.860 + 101.860 _N69 - PLL_158_55/CLK_OUT0 + PLL_158_55/CLK_OUT4 td - 0.078 - 21.938 + 0.079 + 101.939 r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 + u_sys_pll/u_pll_e3/goppll/CLKOUT4 - net (fanout=2) + net (fanout=1) 0.603 - 22.541 + 102.542 - rd3_clk + clk_10m - USCM_84_108/CLK_USCM + USCM_84_110/CLK_USCM td 0.000 - 22.541 + 102.542 r - clkbufg_1/gopclkbufg/CLKOUT + clkbufg_4/gopclkbufg/CLKOUT - net (fanout=2517) - 0.895 - 23.436 + net (fanout=235) + 1.005 + 103.547 - ntclkbufg_1 + ntclkbufg_4 - CLMS_146_69/CLK + CLMA_262_268/CLK r - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/CLK + ms72xx_ctl/rstn_temp1/opit_0_inv/CLK clock pessimism 0.270 - 23.706 + 103.817 @@ -140474,15 +144317,15 @@ clock uncertainty -0.150 - 23.556 + 103.667 Recovery time - 0.000 - 23.556 + -0.476 + 103.191 @@ -140490,28 +144333,49 @@ +
+ + + Slack + Logic Levels + High Fanout + Start Point + End Point + Exception + Launch Clock + Capture Clock + Clock Edges + Clock Skew + Launch Clock Delay + Capture Clock Delay + Clock Pessimism Removal + Requirement + Data delay + Logic delay + Route delay + - 17.096 - 7 - 573 - u_clk50m_rst/rst/opit_0_L5Q_perm/CLK - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/RS + 0.452 + 0 + 2 + u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/opit_0/RS - clk_50m - clk_50m + clk_200m + clk_200m rise-rise - -0.030 - 3.736 - 3.436 - 0.270 - 20.000 - 2.724 - 1.012 (37.2%) - 1.712 (62.8%) + 0.039 + 3.542 + 3.844 + -0.263 + 0.000 + 0.310 + 0.179 (57.7%) + 0.131 (42.3%) - Path #11: recovery slack is 17.096(MET) + Path #1: removal slack is 0.452(MET) -
+
Location Delay Type @@ -140521,7 +144385,7 @@ Logical Resource - Clock clk_50m (rising edge) + Clock clk_200m (rising edge) 0.000 0.000 @@ -140547,8 +144411,8 @@ IOBS_LR_328_209/DIN td - 1.504 - 1.578 + 1.285 + 1.359 r clk_ibuf/opit_0/O @@ -140556,206 +144420,94 @@ net (fanout=1) 0.000 - 1.578 + 1.359 clk_ibuf/ntD IOL_327_210/INCK td - 0.058 - 1.636 + 0.038 + 1.397 r clk_ibuf/opit_1/INCK net (fanout=1) - 0.478 - 2.114 + 0.463 + 1.860 _N69 - PLL_158_55/CLK_OUT0 + PLL_158_55/CLK_OUT1 td - 0.083 - 2.197 + 0.074 + 1.934 r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 + u_sys_pll/u_pll_e3/goppll/CLKOUT1 net (fanout=2) - 0.614 - 2.811 + 0.603 + 2.537 - rd3_clk + ddr_clk - USCM_84_108/CLK_USCM + USCM_84_153/CLK_USCM td 0.000 - 2.811 + 2.537 r - clkbufg_1/gopclkbufg/CLKOUT + USCMROUTE_2/CLKOUT - net (fanout=2517) - 0.925 - 3.736 + net (fanout=6) + 1.005 + 3.542 - ntclkbufg_1 + ntR3952 - CLMS_94_177/CLK + CLMS_174_253/CLK r - u_clk50m_rst/rst/opit_0_L5Q_perm/CLK + u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK - CLMS_94_177/Q0 + CLMS_174_253/Q0 tco - 0.221 - 3.957 - f - u_clk50m_rst/rst/opit_0_L5Q_perm/Q - - - - net (fanout=573) - 1.712 - 5.669 - - rd3_rst - - - CLMS_146_37/RSCO - td - 0.113 - 5.782 - f - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/RSOUT - - - - net (fanout=4) - 0.000 - 5.782 - - ntR414 - - - CLMS_146_41/RSCO - td - 0.113 - 5.895 - f - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/RSOUT - - - - net (fanout=4) - 0.000 - 5.895 - - ntR413 - - - CLMS_146_45/RSCO - td - 0.113 - 6.008 - f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/RSOUT - - - - net (fanout=3) - 0.000 - 6.008 - - ntR412 - - - CLMS_146_49/RSCO - td - 0.113 - 6.121 + 0.179 + 3.721 f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/RSOUT + u_ddr_rst/rst/opit_0_inv_L5Q_perm/Q net (fanout=2) - 0.000 - 6.121 - - ntR411 - - - CLMS_146_53/RSCO - td - 0.113 - 6.234 - f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/RSOUT - - - - net (fanout=4) - 0.000 - 6.234 - - ntR410 - - - CLMS_146_57/RSCO - td - 0.113 - 6.347 - f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/RSOUT - - - - net (fanout=6) - 0.000 - 6.347 - - ntR409 - - - CLMS_146_61/RSCO - td - 0.113 - 6.460 - f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/RSOUT - - - - net (fanout=5) - 0.000 - 6.460 + 0.131 + 3.852 - ntR408 + ddr_rst - CLMS_146_69/RSCI + CLMA_174_252/RS f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/RS + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/opit_0/RS
- +
Location Delay Type @@ -140765,10 +144517,10 @@ Logical Resource - Clock clk_50m (rising edge) + Clock clk_200m (rising edge) - 20.000 - 20.000 + 0.000 + 0.000 r @@ -140776,7 +144528,7 @@ P200.000 - 20.000 + 0.000rclk (port) @@ -140784,15 +144536,15 @@ net (fanout=1) 0.074 - 20.074 + 0.074 clk IOBS_LR_328_209/DIN td - 1.285 - 21.359 + 1.504 + 1.578 r clk_ibuf/opit_0/O @@ -140800,87 +144552,87 @@ net (fanout=1) 0.000 - 21.359 + 1.578 clk_ibuf/ntD IOL_327_210/INCK td - 0.038 - 21.397 + 0.058 + 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) - 0.463 - 21.860 + 0.478 + 2.114 _N69 - PLL_158_55/CLK_OUT0 + PLL_158_55/CLK_OUT1 td - 0.078 - 21.938 + 0.079 + 2.193 r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 + u_sys_pll/u_pll_e3/goppll/CLKOUT1 net (fanout=2) - 0.603 - 22.541 + 0.614 + 2.807 - rd3_clk + ddr_clk - USCM_84_108/CLK_USCM + USCM_84_113/CLK_USCM td 0.000 - 22.541 + 2.807 r - clkbufg_1/gopclkbufg/CLKOUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=2517) - 0.895 - 23.436 + net (fanout=71) + 1.037 + 3.844 - ntclkbufg_1 + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - CLMS_146_69/CLK + CLMA_174_252/CLK r - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/opit_0/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/opit_0/CLK clock pessimism - 0.270 - 23.706 + -0.263 + 3.581 clock uncertainty - -0.150 - 23.556 + 0.000 + 3.581 - Recovery time + Removal time - 0.000 - 23.556 + -0.181 + 3.400 @@ -140889,27 +144641,27 @@ - 17.096 - 7 - 573 - u_clk50m_rst/rst/opit_0_L5Q_perm/CLK - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/opit_0/RS + 0.452 + 0 + 2 + u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/RS - clk_50m - clk_50m + clk_200m + clk_200m rise-rise - -0.030 - 3.736 - 3.436 - 0.270 - 20.000 - 2.724 - 1.012 (37.2%) - 1.712 (62.8%) + 0.039 + 3.542 + 3.844 + -0.263 + 0.000 + 0.310 + 0.179 (57.7%) + 0.131 (42.3%) - Path #12: recovery slack is 17.096(MET) + Path #2: removal slack is 0.452(MET) -
+
Location Delay Type @@ -140919,7 +144671,7 @@ Logical Resource - Clock clk_50m (rising edge) + Clock clk_200m (rising edge) 0.000 0.000 @@ -140945,8 +144697,8 @@ IOBS_LR_328_209/DIN td - 1.504 - 1.578 + 1.285 + 1.359 r clk_ibuf/opit_0/O @@ -140954,206 +144706,94 @@ net (fanout=1) 0.000 - 1.578 + 1.359 clk_ibuf/ntD IOL_327_210/INCK td - 0.058 - 1.636 + 0.038 + 1.397 r clk_ibuf/opit_1/INCK net (fanout=1) - 0.478 - 2.114 + 0.463 + 1.860 _N69 - PLL_158_55/CLK_OUT0 + PLL_158_55/CLK_OUT1 td - 0.083 - 2.197 + 0.074 + 1.934 r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 + u_sys_pll/u_pll_e3/goppll/CLKOUT1 net (fanout=2) - 0.614 - 2.811 + 0.603 + 2.537 - rd3_clk + ddr_clk - USCM_84_108/CLK_USCM + USCM_84_153/CLK_USCM td 0.000 - 2.811 + 2.537 r - clkbufg_1/gopclkbufg/CLKOUT + USCMROUTE_2/CLKOUT - net (fanout=2517) - 0.925 - 3.736 + net (fanout=6) + 1.005 + 3.542 - ntclkbufg_1 + ntR3952 - CLMS_94_177/CLK + CLMS_174_253/CLK r - u_clk50m_rst/rst/opit_0_L5Q_perm/CLK + u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK - CLMS_94_177/Q0 + CLMS_174_253/Q0 tco - 0.221 - 3.957 - f - u_clk50m_rst/rst/opit_0_L5Q_perm/Q - - - - net (fanout=573) - 1.712 - 5.669 - - rd3_rst - - - CLMS_146_37/RSCO - td - 0.113 - 5.782 - f - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[0]/opit_0/RSOUT - - - - net (fanout=4) - 0.000 - 5.782 - - ntR414 - - - CLMS_146_41/RSCO - td - 0.113 - 5.895 - f - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/opit_0_L5Q_perm/RSOUT - - - - net (fanout=4) - 0.000 - 5.895 - - ntR413 - - - CLMS_146_45/RSCO - td - 0.113 - 6.008 - f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/opit_0_L5Q_perm/RSOUT - - - - net (fanout=3) - 0.000 - 6.008 - - ntR412 - - - CLMS_146_49/RSCO - td - 0.113 - 6.121 + 0.179 + 3.721 f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/opit_0/RSOUT + u_ddr_rst/rst/opit_0_inv_L5Q_perm/Q net (fanout=2) - 0.000 - 6.121 - - ntR411 - - - CLMS_146_53/RSCO - td - 0.113 - 6.234 - f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[10]/opit_0/RSOUT - - - - net (fanout=4) - 0.000 - 6.234 - - ntR410 - - - CLMS_146_57/RSCO - td - 0.113 - 6.347 - f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[4]/opit_0/RSOUT - - - - net (fanout=6) - 0.000 - 6.347 - - ntR409 - - - CLMS_146_61/RSCO - td - 0.113 - 6.460 - f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wrptr2[9]/opit_0/RSOUT - - - - net (fanout=5) - 0.000 - 6.460 + 0.131 + 3.852 - ntR408 + ddr_rst - CLMS_146_69/RSCI + CLMA_174_252/RS f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/opit_0/RS + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/RS
- +
Location Delay Type @@ -141163,10 +144803,10 @@ Logical Resource - Clock clk_50m (rising edge) + Clock clk_200m (rising edge) - 20.000 - 20.000 + 0.000 + 0.000 r @@ -141174,7 +144814,7 @@ P200.000 - 20.000 + 0.000rclk (port) @@ -141182,15 +144822,15 @@ net (fanout=1) 0.074 - 20.074 + 0.074 clk IOBS_LR_328_209/DIN td - 1.285 - 21.359 + 1.504 + 1.578 r clk_ibuf/opit_0/O @@ -141198,87 +144838,87 @@ net (fanout=1) 0.000 - 21.359 + 1.578 clk_ibuf/ntD IOL_327_210/INCK td - 0.038 - 21.397 + 0.058 + 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) - 0.463 - 21.860 + 0.478 + 2.114 _N69 - PLL_158_55/CLK_OUT0 + PLL_158_55/CLK_OUT1 td - 0.078 - 21.938 + 0.079 + 2.193 r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 + u_sys_pll/u_pll_e3/goppll/CLKOUT1 net (fanout=2) - 0.603 - 22.541 + 0.614 + 2.807 - rd3_clk + ddr_clk - USCM_84_108/CLK_USCM + USCM_84_113/CLK_USCM td 0.000 - 22.541 + 2.807 r - clkbufg_1/gopclkbufg/CLKOUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=2517) - 0.895 - 23.436 + net (fanout=71) + 1.037 + 3.844 - ntclkbufg_1 + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - CLMS_146_69/CLK + CLMA_174_252/CLK r - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/opit_0/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK clock pessimism - 0.270 - 23.706 + -0.263 + 3.581 clock uncertainty - -0.150 - 23.556 + 0.000 + 3.581 - Recovery time + Removal time - 0.000 - 23.556 + -0.181 + 3.400 @@ -141287,27 +144927,27 @@ - 98.359 - 0 - 3 - rstn_out1/opit_0_inv/CLK - ms72xx_ctl/rstn_temp1/opit_0_inv/RS + 0.454 + 1 + 40 + image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/RS - clk_10m - clk_10m + clk_50m + clk_50m rise-rise - -0.019 - 3.737 - 3.437 - 0.281 - 100.000 - 0.996 - 0.220 (22.1%) - 0.776 (77.9%) + 0.019 + 3.546 + 3.848 + -0.283 + 0.000 + 0.473 + 0.267 (56.4%) + 0.206 (43.6%) - Path #13: recovery slack is 98.359(MET) + Path #3: removal slack is 0.454(MET) -
+
Location Delay Type @@ -141317,7 +144957,7 @@ Logical Resource - Clock clk_10m (rising edge) + Clock clk_50m (rising edge) 0.000 0.000 @@ -141343,8 +144983,8 @@ IOBS_LR_328_209/DIN td - 1.504 - 1.578 + 1.285 + 1.359 r clk_ibuf/opit_0/O @@ -141352,94 +144992,110 @@ net (fanout=1) 0.000 - 1.578 + 1.359 clk_ibuf/ntD IOL_327_210/INCK td - 0.058 - 1.636 + 0.038 + 1.397 r clk_ibuf/opit_1/INCK net (fanout=1) - 0.478 - 2.114 + 0.463 + 1.860 _N69 - PLL_158_55/CLK_OUT4 + PLL_158_55/CLK_OUT0 td - 0.084 - 2.198 + 0.078 + 1.938 r - u_sys_pll/u_pll_e3/goppll/CLKOUT4 + u_sys_pll/u_pll_e3/goppll/CLKOUT0 - net (fanout=1) - 0.614 - 2.812 + net (fanout=2) + 0.603 + 2.541 - clk_10m + rd3_clk - USCM_84_110/CLK_USCM + USCM_84_108/CLK_USCM td 0.000 - 2.812 + 2.541 r - clkbufg_3/gopclkbufg/CLKOUT + clkbufg_1/gopclkbufg/CLKOUT - net (fanout=235) - 0.925 - 3.737 + net (fanout=2516) + 1.005 + 3.546 - ntclkbufg_3 + ntclkbufg_1 - CLMA_230_69/CLK + CLMS_98_321/CLK r - rstn_out1/opit_0_inv/CLK + image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK - CLMA_230_69/Q3 + CLMS_98_321/Q0 tco - 0.220 - 3.957 - f - rstn_out1/opit_0_inv/Q + 0.182 + 3.728 + r + image_filiter_inst/multiline_buffer_inst/srst/opit_0/Q - net (fanout=3) - 0.776 - 4.733 + net (fanout=40) + 0.206 + 3.934 - nt_eth_rstn + image_filiter_inst/multiline_buffer_inst/srst - CLMA_246_120/RS + CLMS_102_325/RSCO + td + 0.085 + 4.019 + r + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/RSOUT + + + + net (fanout=2) + 0.000 + 4.019 + + ntR19 + + + CLMS_102_329/RSCI - f - ms72xx_ctl/rstn_temp1/opit_0_inv/RS + r + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/RS
- +
Location Delay Type @@ -141449,10 +145105,10 @@ Logical Resource - Clock clk_10m (rising edge) + Clock clk_50m (rising edge) - 100.000 - 100.000 + 0.000 + 0.000 r @@ -141460,7 +145116,7 @@ P200.000 - 100.000 + 0.000rclk (port) @@ -141468,15 +145124,15 @@ net (fanout=1) 0.074 - 100.074 + 0.074 clk IOBS_LR_328_209/DIN td - 1.285 - 101.359 + 1.504 + 1.578 r clk_ibuf/opit_0/O @@ -141484,87 +145140,87 @@ net (fanout=1) 0.000 - 101.359 + 1.578 clk_ibuf/ntD IOL_327_210/INCK td - 0.038 - 101.397 + 0.058 + 1.636 r clk_ibuf/opit_1/INCK net (fanout=1) - 0.463 - 101.860 + 0.478 + 2.114 _N69 - PLL_158_55/CLK_OUT4 + PLL_158_55/CLK_OUT0 td - 0.079 - 101.939 + 0.083 + 2.197 r - u_sys_pll/u_pll_e3/goppll/CLKOUT4 + u_sys_pll/u_pll_e3/goppll/CLKOUT0 - net (fanout=1) - 0.603 - 102.542 + net (fanout=2) + 0.614 + 2.811 - clk_10m + rd3_clk - USCM_84_110/CLK_USCM + USCM_84_108/CLK_USCM td 0.000 - 102.542 + 2.811 r - clkbufg_3/gopclkbufg/CLKOUT + clkbufg_1/gopclkbufg/CLKOUT - net (fanout=235) - 0.895 - 103.437 + net (fanout=2516) + 1.037 + 3.848 - ntclkbufg_3 + ntclkbufg_1 - CLMA_246_120/CLK + CLMS_102_329/CLK r - ms72xx_ctl/rstn_temp1/opit_0_inv/CLK + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK clock pessimism - 0.281 - 103.718 + -0.283 + 3.565 clock uncertainty - -0.150 - 103.568 + 0.000 + 3.565 - Recovery time + Removal time - -0.476 - 103.092 + 0.000 + 3.565 @@ -141572,49 +145228,28 @@ -
- - - Slack - Logic Levels - High Fanout - Start Point - End Point - Exception - Launch Clock - Capture Clock - Clock Edges - Clock Skew - Launch Clock Delay - Capture Clock Delay - Clock Pessimism Removal - Requirement - Data delay - Logic delay - Route delay - - 0.418 - 0 - 37 + 0.454 + 1 + 40 image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0] + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/RS clk_50m clk_50m rise-rise 0.019 - 3.436 - 3.736 - -0.281 + 3.546 + 3.848 + -0.283 0.000 - 0.419 - 0.179 (42.7%) - 0.240 (57.3%) + 0.473 + 0.267 (56.4%) + 0.206 (43.6%) - Path #1: removal slack is 0.418(MET) + Path #4: removal slack is 0.454(MET) -
+
Location Delay Type @@ -141705,14 +145340,14 @@ - net (fanout=2517) - 0.895 - 3.436 + net (fanout=2516) + 1.005 + 3.546 ntclkbufg_1 - CLMS_134_93/CLK + CLMS_98_321/CLK @@ -141720,33 +145355,49 @@ image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK - CLMS_134_93/Q0 + CLMS_98_321/Q0 tco - 0.179 - 3.615 - f + 0.182 + 3.728 + r image_filiter_inst/multiline_buffer_inst/srst/opit_0/Q - net (fanout=37) - 0.240 - 3.855 + net (fanout=40) + 0.206 + 3.934 image_filiter_inst/multiline_buffer_inst/srst - DRM_142_88/RSTB[0] + CLMS_102_325/RSCO + td + 0.085 + 4.019 + r + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/RSOUT + + + net (fanout=2) + 0.000 + 4.019 + + ntR19 + + + CLMS_102_329/RSCI - f - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0] + + r + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/RS
- +
Location Delay Type @@ -141837,25 +145488,25 @@ - net (fanout=2517) - 0.925 - 3.736 + net (fanout=2516) + 1.037 + 3.848 ntclkbufg_1 - DRM_142_88/CLKB[0] + CLMS_102_329/CLK r - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/opit_0_inv_A2Q21/CLK clock pessimism - -0.281 - 3.455 + -0.283 + 3.565 @@ -141863,15 +145514,15 @@ clock uncertainty 0.000 - 3.455 + 3.565 Removal time - -0.018 - 3.437 + 0.000 + 3.565 @@ -141880,27 +145531,27 @@ - 0.438 + 0.460 0 - 37 + 40 image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTA[0] + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0] clk_50m clk_50m rise-rise 0.019 - 3.436 - 3.736 - -0.281 + 3.546 + 3.848 + -0.283 0.000 - 0.419 - 0.179 (42.7%) - 0.240 (57.3%) + 0.461 + 0.179 (38.8%) + 0.282 (61.2%) - Path #2: removal slack is 0.438(MET) + Path #5: removal slack is 0.460(MET) -
+
Location Delay Type @@ -141991,14 +145642,14 @@ - net (fanout=2517) - 0.895 - 3.436 + net (fanout=2516) + 1.005 + 3.546 ntclkbufg_1 - CLMS_134_93/CLK + CLMS_98_321/CLK @@ -142006,33 +145657,33 @@ image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK - CLMS_134_93/Q0 + CLMS_98_321/Q0 tco 0.179 - 3.615 + 3.725 f image_filiter_inst/multiline_buffer_inst/srst/opit_0/Q - net (fanout=37) - 0.240 - 3.855 + net (fanout=40) + 0.282 + 4.007 image_filiter_inst/multiline_buffer_inst/srst - DRM_142_88/RSTA[0] + DRM_82_316/RSTB[0] f - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTA[0] + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0]
- +
Location Delay Type @@ -142123,25 +145774,25 @@ - net (fanout=2517) - 0.925 - 3.736 + net (fanout=2516) + 1.037 + 3.848 ntclkbufg_1 - DRM_142_88/CLKA[0] + DRM_82_316/CLKB[0] r - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] clock pessimism - -0.281 - 3.455 + -0.283 + 3.565 @@ -142149,15 +145800,15 @@ clock uncertainty 0.000 - 3.455 + 3.565 Removal time - -0.038 - 3.417 + -0.018 + 3.547 @@ -142166,27 +145817,27 @@ - 0.452 - 0 - 2 - u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/opit_0/RS + 0.482 + 1 + 729 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[6]/opit_0_inv_L5Q_perm/RS - clk_200m - clk_200m + ddrphy_clkin + ddrphy_clkin rise-rise - 0.037 - 3.432 - 3.732 - -0.263 + 0.019 + 6.654 + 7.101 + -0.428 0.000 - 0.308 - 0.179 (58.1%) - 0.129 (41.9%) + 0.501 + 0.264 (52.7%) + 0.237 (47.3%) - Path #3: removal slack is 0.452(MET) + Path #6: removal slack is 0.482(MET) -
+
Location Delay Type @@ -142196,7 +145847,7 @@ Logical Resource - Clock clk_200m (rising edge) + Clock ddrphy_clkin (rising edge) 0.000 0.000 @@ -142222,103 +145873,183 @@ IOBS_LR_328_209/DIN td - 1.285 - 1.359 + 1.285 + 1.359 + r + clk_ibuf/opit_0/O + + + + net (fanout=1) + 0.000 + 1.359 + + clk_ibuf/ntD + + + IOL_327_210/INCK + td + 0.038 + 1.397 + r + clk_ibuf/opit_1/INCK + + + + net (fanout=1) + 0.463 + 1.860 + + _N69 + + + PLL_158_55/CLK_OUT1 + td + 0.074 + 1.934 + r + u_sys_pll/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 0.603 + 2.537 + + ddr_clk + + + USCM_84_113/CLK_USCM + td + 0.000 + 2.537 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 0.981 + 3.518 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.089 + 3.607 r - clk_ibuf/opit_0/O + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - net (fanout=1) - 0.000 - 1.359 + net (fanout=3) + 0.669 + 4.276 - clk_ibuf/ntD + clkout0_wl_0 - IOL_327_210/INCK + IOCKGATE_6_322/OUT td - 0.038 - 1.397 + 0.200 + 4.476 r - clk_ibuf/opit_1/INCK + clkgate_9/gopclkgate/OUT net (fanout=1) - 0.463 - 1.860 + 0.000 + 4.476 - _N69 + ntclkgate_0 - PLL_158_55/CLK_OUT1 + IOCKDIV_6_323/CLK_IODIV td - 0.074 - 1.934 + 0.000 + 4.476 r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV - net (fanout=2) - 0.603 - 2.537 + net (fanout=1) + 1.283 + 5.759 - zoom_clk + u_axi_ddr_top/clk - USCM_84_122/CLK_USCM + USCM_84_116/CLK_USCM td 0.000 - 2.537 + 5.759 r - USCMROUTE_2/CLKOUT + clkbufg_0/gopclkbufg/CLKOUT - net (fanout=759) + net (fanout=5464) 0.895 - 3.432 + 6.654 - ntR3909 + ntclkbufg_0 - CLMS_202_149/CLK + CLMA_46_192/CLK r - u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK - CLMS_202_149/Q0 + CLMA_46_192/Q0 tco 0.179 - 3.611 + 6.833 f - u_ddr_rst/rst/opit_0_inv_L5Q_perm/Q + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q - net (fanout=2) - 0.129 - 3.740 + net (fanout=729) + 0.237 + 7.070 - ddr_rst + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n + + + CLMA_38_192/RSCO + td + 0.085 + 7.155 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[57]/opit_0_inv/RSOUT + + + + net (fanout=4) + 0.000 + 7.155 + + ntR984 - CLMA_202_148/RS + CLMA_38_196/RSCI - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/opit_0/RS + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[6]/opit_0_inv_L5Q_perm/RS
- +
Location Delay Type @@ -142328,7 +146059,7 @@ Logical Resource - Clock clk_200m (rising edge) + Clock ddrphy_clkin (rising edge) 0.000 0.000 @@ -142397,7 +146128,7 @@ 0.614 2.807 - zoom_clk + ddr_clk USCM_84_113/CLK_USCM @@ -142409,25 +146140,89 @@ - net (fanout=68) - 0.925 - 3.732 + net (fanout=71) + 1.019 + 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - CLMA_202_148/CLK + PLL_158_199/CLK_OUT0_WL + td + 0.094 + 3.920 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 0.682 + 4.602 + clkout0_wl_0 + + + IOCKGATE_6_322/OUT + td + 0.268 + 4.870 + r + clkgate_9/gopclkgate/OUT + + + net (fanout=1) + 0.000 + 4.870 + ntclkgate_0 + + + IOCKDIV_6_323/CLK_IODIV + td + 0.000 + 4.870 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/opit_0/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + + + + net (fanout=1) + 1.306 + 6.176 + + u_axi_ddr_top/clk + + + USCM_84_116/CLK_USCM + td + 0.000 + 6.176 + r + clkbufg_0/gopclkbufg/CLKOUT + + + + net (fanout=5464) + 0.925 + 7.101 + + ntclkbufg_0 + + + CLMA_38_196/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[6]/opit_0_inv_L5Q_perm/CLK clock pessimism - -0.263 - 3.469 + -0.428 + 6.673 @@ -142435,15 +146230,15 @@ clock uncertainty 0.000 - 3.469 + 6.673 Removal time - -0.181 - 3.288 + 0.000 + 6.673 @@ -142452,27 +146247,27 @@ - 0.452 - 0 - 2 - u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/RS + 0.482 + 1 + 729 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[7]/opit_0_inv_L5Q_perm/RS - clk_200m - clk_200m + ddrphy_clkin + ddrphy_clkin rise-rise - 0.037 - 3.432 - 3.732 - -0.263 + 0.019 + 6.654 + 7.101 + -0.428 0.000 - 0.308 - 0.179 (58.1%) - 0.129 (41.9%) + 0.501 + 0.264 (52.7%) + 0.237 (47.3%) - Path #4: removal slack is 0.452(MET) + Path #7: removal slack is 0.482(MET) -
+
Location Delay Type @@ -142482,7 +146277,7 @@ Logical Resource - Clock clk_200m (rising edge) + Clock ddrphy_clkin (rising edge) 0.000 0.000 @@ -142551,60 +146346,140 @@ 0.603 2.537 - zoom_clk + ddr_clk - USCM_84_122/CLK_USCM + USCM_84_113/CLK_USCM td 0.000 2.537 r - USCMROUTE_2/CLKOUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT + + + + net (fanout=71) + 0.981 + 3.518 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.089 + 3.607 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 0.669 + 4.276 + + clkout0_wl_0 + + + IOCKGATE_6_322/OUT + td + 0.200 + 4.476 + r + clkgate_9/gopclkgate/OUT + + + + net (fanout=1) + 0.000 + 4.476 + + ntclkgate_0 + + + IOCKDIV_6_323/CLK_IODIV + td + 0.000 + 4.476 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + + + + net (fanout=1) + 1.283 + 5.759 + + u_axi_ddr_top/clk + + + USCM_84_116/CLK_USCM + td + 0.000 + 5.759 + r + clkbufg_0/gopclkbufg/CLKOUT - net (fanout=759) + net (fanout=5464) 0.895 - 3.432 + 6.654 - ntR3909 + ntclkbufg_0 - CLMS_202_149/CLK + CLMA_46_192/CLK r - u_ddr_rst/rst/opit_0_inv_L5Q_perm/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK - CLMS_202_149/Q0 + CLMA_46_192/Q0 tco 0.179 - 3.611 + 6.833 f - u_ddr_rst/rst/opit_0_inv_L5Q_perm/Q + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q - net (fanout=2) - 0.129 - 3.740 + net (fanout=729) + 0.237 + 7.070 - ddr_rst + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n - CLMA_202_148/RS + CLMA_38_192/RSCO + td + 0.085 + 7.155 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[57]/opit_0_inv/RSOUT + + + + net (fanout=4) + 0.000 + 7.155 + + ntR984 + + + CLMA_38_196/RSCI - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/RS + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[7]/opit_0_inv_L5Q_perm/RS
- +
Location Delay Type @@ -142614,7 +146489,7 @@ Logical Resource - Clock clk_200m (rising edge) + Clock ddrphy_clkin (rising edge) 0.000 0.000 @@ -142683,7 +146558,7 @@ 0.614 2.807 - zoom_clk + ddr_clk USCM_84_113/CLK_USCM @@ -142695,25 +146570,89 @@ - net (fanout=68) - 0.925 - 3.732 + net (fanout=71) + 1.019 + 3.826 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - CLMA_202_148/CLK + PLL_158_199/CLK_OUT0_WL + td + 0.094 + 3.920 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 0.682 + 4.602 + clkout0_wl_0 + + + IOCKGATE_6_322/OUT + td + 0.268 + 4.870 + r + clkgate_9/gopclkgate/OUT + + + net (fanout=1) + 0.000 + 4.870 + ntclkgate_0 + + + IOCKDIV_6_323/CLK_IODIV + td + 0.000 + 4.870 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/opit_0/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + + + + net (fanout=1) + 1.306 + 6.176 + + u_axi_ddr_top/clk + + + USCM_84_116/CLK_USCM + td + 0.000 + 6.176 + r + clkbufg_0/gopclkbufg/CLKOUT + + + + net (fanout=5464) + 0.925 + 7.101 + + ntclkbufg_0 + + + CLMA_38_196/CLK + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[7]/opit_0_inv_L5Q_perm/CLK clock pessimism - -0.263 - 3.469 + -0.428 + 6.673 @@ -142721,15 +146660,15 @@ clock uncertainty 0.000 - 3.469 + 6.673 Removal time - -0.181 - 3.288 + 0.000 + 6.673 @@ -142738,27 +146677,27 @@ - 0.533 + 0.482 1 - 14 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q_perm/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[0]/opit_0_inv/RS + 729 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[8]/opit_0_inv_L5Q_perm/RS - clk_200m - clk_200m + ddrphy_clkin + ddrphy_clkin rise-rise 0.019 - 3.432 - 3.732 - -0.281 + 6.654 + 7.101 + -0.428 0.000 - 0.552 - 0.274 (49.6%) - 0.278 (50.4%) + 0.501 + 0.264 (52.7%) + 0.237 (47.3%) - Path #5: removal slack is 0.533(MET) + Path #8: removal slack is 0.482(MET) -
+
Location Delay Type @@ -142768,7 +146707,7 @@ Logical Resource - Clock clk_200m (rising edge) + Clock ddrphy_clkin (rising edge) 0.000 0.000 @@ -142837,7 +146776,7 @@ 0.603 2.537 - zoom_clk + ddr_clk USCM_84_113/CLK_USCM @@ -142849,64 +146788,128 @@ - net (fanout=68) - 0.895 - 3.432 + net (fanout=71) + 0.981 + 3.518 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - CLMS_78_181/CLK + PLL_158_199/CLK_OUT0_WL + td + 0.089 + 3.607 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 0.669 + 4.276 + + clkout0_wl_0 + + + IOCKGATE_6_322/OUT + td + 0.200 + 4.476 + r + clkgate_9/gopclkgate/OUT + + + + net (fanout=1) + 0.000 + 4.476 + + ntclkgate_0 + + + IOCKDIV_6_323/CLK_IODIV + td + 0.000 + 4.476 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + + + + net (fanout=1) + 1.283 + 5.759 + + u_axi_ddr_top/clk + + + USCM_84_116/CLK_USCM + td + 0.000 + 5.759 + r + clkbufg_0/gopclkbufg/CLKOUT + + + + net (fanout=5464) + 0.895 + 6.654 + + ntclkbufg_0 + + + CLMA_46_192/CLK r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q_perm/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK - CLMS_78_181/Q0 + CLMA_46_192/Q0 tco - 0.182 - 3.614 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q_perm/Q + 0.179 + 6.833 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q - net (fanout=14) - 0.278 - 3.892 + net (fanout=729) + 0.237 + 7.070 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/logic_rstn + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n - CLMS_62_181/RSCO + CLMA_38_192/RSCO td - 0.092 - 3.984 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/pll_lock_d[1]/opit_0_inv/RSOUT + 0.085 + 7.155 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[57]/opit_0_inv/RSOUT net (fanout=4) 0.000 - 3.984 + 7.155 - ntR1581 + ntR984 - CLMS_62_185/RSCI + CLMA_38_196/RSCI - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[0]/opit_0_inv/RS + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[8]/opit_0_inv_L5Q_perm/RS
- +
Location Delay Type @@ -142916,7 +146919,7 @@ Logical Resource - Clock clk_200m (rising edge) + Clock ddrphy_clkin (rising edge) 0.000 0.000 @@ -142985,7 +146988,7 @@ 0.614 2.807 - zoom_clk + ddr_clk USCM_84_113/CLK_USCM @@ -142997,25 +147000,89 @@ - net (fanout=68) + net (fanout=71) + 1.019 + 3.826 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + PLL_158_199/CLK_OUT0_WL + td + 0.094 + 3.920 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL + + + + net (fanout=3) + 0.682 + 4.602 + + clkout0_wl_0 + + + IOCKGATE_6_322/OUT + td + 0.268 + 4.870 + r + clkgate_9/gopclkgate/OUT + + + + net (fanout=1) + 0.000 + 4.870 + + ntclkgate_0 + + + IOCKDIV_6_323/CLK_IODIV + td + 0.000 + 4.870 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + + + + net (fanout=1) + 1.306 + 6.176 + + u_axi_ddr_top/clk + + + USCM_84_116/CLK_USCM + td + 0.000 + 6.176 + r + clkbufg_0/gopclkbufg/CLKOUT + + + + net (fanout=5464) 0.925 - 3.732 + 7.101 - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + ntclkbufg_0 - CLMS_62_185/CLK + CLMA_38_196/CLK r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[0]/opit_0_inv/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[8]/opit_0_inv_L5Q_perm/CLK clock pessimism - -0.281 - 3.451 + -0.428 + 6.673 @@ -143023,7 +147090,7 @@ clock uncertainty 0.000 - 3.451 + 6.673 @@ -143031,7 +147098,7 @@ Removal time 0.000 - 3.451 + 6.673 @@ -143040,27 +147107,27 @@ - 0.540 - 1 - 37 - image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/RS + 0.666 + 0 + 22 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[0]/opit_0_inv_L5Q_perm/RS - clk_50m - clk_50m + clk_200m + clk_200m rise-rise 0.019 - 3.436 - 3.736 + 3.432 + 3.732 -0.281 0.000 - 0.559 - 0.267 (47.8%) - 0.292 (52.2%) + 0.498 + 0.182 (36.5%) + 0.316 (63.5%) - Path #6: removal slack is 0.540(MET) + Path #9: removal slack is 0.666(MET) -
+
Location Delay Type @@ -143070,7 +147137,7 @@ Logical Resource - Clock clk_50m (rising edge) + Clock clk_200m (rising edge) 0.000 0.000 @@ -143126,89 +147193,73 @@ _N69 - PLL_158_55/CLK_OUT0 + PLL_158_55/CLK_OUT1 td - 0.078 - 1.938 + 0.074 + 1.934 r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 + u_sys_pll/u_pll_e3/goppll/CLKOUT1 net (fanout=2) 0.603 - 2.541 + 2.537 - rd3_clk + ddr_clk - USCM_84_108/CLK_USCM + USCM_84_113/CLK_USCM td 0.000 - 2.541 + 2.537 r - clkbufg_1/gopclkbufg/CLKOUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=2517) + net (fanout=71) 0.895 - 3.436 + 3.432 - ntclkbufg_1 + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - CLMS_134_93/CLK + CLMA_58_184/CLK r - image_filiter_inst/multiline_buffer_inst/srst/opit_0/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q/CLK - CLMS_134_93/Q0 + CLMA_58_184/Q0 tco 0.182 - 3.618 - r - image_filiter_inst/multiline_buffer_inst/srst/opit_0/Q - - - - net (fanout=37) - 0.292 - 3.910 - - image_filiter_inst/multiline_buffer_inst/srst - - - CLMA_138_81/RSCO - td - 0.085 - 3.995 + 3.614 r - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/opit_0_inv_A2Q21/RSOUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/opit_0_inv_L5Q/Q - net (fanout=2) - 0.000 - 3.995 + net (fanout=22) + 0.316 + 3.930 - ntR38 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/logic_rstn - CLMA_138_85/RSCI + CLMA_38_184/RS r - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/RS + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[0]/opit_0_inv_L5Q_perm/RS
- +
Location Delay Type @@ -143218,7 +147269,7 @@ Logical Resource - Clock clk_50m (rising edge) + Clock clk_200m (rising edge) 0.000 0.000 @@ -143274,50 +147325,50 @@ _N69 - PLL_158_55/CLK_OUT0 + PLL_158_55/CLK_OUT1 td - 0.083 - 2.197 + 0.079 + 2.193 r - u_sys_pll/u_pll_e3/goppll/CLKOUT0 + u_sys_pll/u_pll_e3/goppll/CLKOUT1 net (fanout=2) 0.614 - 2.811 + 2.807 - rd3_clk + ddr_clk - USCM_84_108/CLK_USCM + USCM_84_113/CLK_USCM td 0.000 - 2.811 + 2.807 r - clkbufg_1/gopclkbufg/CLKOUT + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - net (fanout=2517) + net (fanout=71) 0.925 - 3.736 + 3.732 - ntclkbufg_1 + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - CLMA_138_85/CLK + CLMA_38_184/CLK r - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/opit_0_inv_A2Q21/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[0]/opit_0_inv_L5Q_perm/CLK clock pessimism -0.281 - 3.455 + 3.451 @@ -143325,15 +147376,15 @@ clock uncertainty 0.000 - 3.455 + 3.451 Removal time - 0.000 - 3.455 + -0.187 + 3.264 @@ -143342,27 +147393,27 @@ - 0.555 - 1 - 619 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[151]/opit_0_inv/RS + 0.722 + 0 + 911 + sync_vg_100m/opit_0_inv_L5Q_perm/CLK + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0] - ddrphy_clkin - ddrphy_clkin + clk_720p60Hz + clk_720p60Hz rise-rise - 0.019 - 6.654 - 7.101 - -0.428 + 0.032 + 5.626 + 5.990 + -0.332 0.000 - 0.574 - 0.274 (47.7%) - 0.300 (52.3%) + 0.691 + 0.182 (26.3%) + 0.509 (73.7%) - Path #7: removal slack is 0.555(MET) + Path #10: removal slack is 0.722(MET) -
+
Location Delay Type @@ -143372,7 +147423,7 @@ Logical Resource - Clock ddrphy_clkin (rising edge) + Clock clk_720p60Hz (rising edge) 0.000 0.000 @@ -143428,153 +147479,105 @@ _N69 - PLL_158_55/CLK_OUT1 + PLL_158_55/CLK_OUT0 td - 0.074 - 1.934 + 0.078 + 1.938 r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 + u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 0.603 - 2.537 + 2.541 - zoom_clk + rd3_clk - USCM_84_113/CLK_USCM + USCM_84_154/CLK_USCM td 0.000 - 2.537 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 0.981 - 3.518 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.089 - 3.607 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 0.669 - 4.276 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.200 - 4.476 + 2.541 r - clkgate_8/gopclkgate/OUT + USCMROUTE_0/CLKOUT net (fanout=1) - 0.000 - 4.476 + 1.091 + 3.632 - ntclkgate_0 + ntR3950 - IOCKDIV_6_323/CLK_IODIV + PLL_158_303/CLK_OUT1 td - 0.000 - 4.476 + 0.074 + 3.706 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - net (fanout=1) - 1.283 - 5.759 + net (fanout=2) + 0.915 + 4.621 - u_axi_ddr_top/clk + nt_pix_clk - USCM_84_116/CLK_USCM + USCM_84_117/CLK_USCM td 0.000 - 5.759 + 4.621 r - clkbufg_0/gopclkbufg/CLKOUT + clkbufg_2/gopclkbufg/CLKOUT - net (fanout=5464) - 0.895 - 6.654 + net (fanout=1635) + 1.005 + 5.626 - ntclkbufg_0 + ntclkbufg_2 - CLMA_70_192/CLK + CLMA_150_276/CLK r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK + sync_vg_100m/opit_0_inv_L5Q_perm/CLK - CLMA_70_192/Q0 + CLMA_150_276/Q0 tco 0.182 - 6.836 + 5.808 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q - - - - net (fanout=619) - 0.300 - 7.136 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n - - - CLMA_66_212/RSCO - td - 0.092 - 7.228 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[37]/opit_0_inv/RSOUT + sync_vg_100m/opit_0_inv_L5Q_perm/Q - net (fanout=4) - 0.000 - 7.228 + net (fanout=911) + 0.509 + 6.317 - ntR1484 + sync_vg_100m - CLMA_66_216/RSCI + DRM_178_272/RSTB[0] - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[151]/opit_0_inv/RS + r + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0]
- +
Location Delay Type @@ -143584,7 +147587,7 @@ Logical Resource - Clock ddrphy_clkin (rising edge) + Clock clk_720p60Hz (rising edge) 0.000 0.000 @@ -143640,114 +147643,82 @@ _N69 - PLL_158_55/CLK_OUT1 + PLL_158_55/CLK_OUT0 td - 0.079 - 2.193 + 0.083 + 2.197 r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 + u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 0.614 - 2.807 + 2.811 - zoom_clk + rd3_clk - USCM_84_113/CLK_USCM + USCM_84_154/CLK_USCM td 0.000 - 2.807 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.019 - 3.826 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.094 - 3.920 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 0.682 - 4.602 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.268 - 4.870 + 2.811 r - clkgate_8/gopclkgate/OUT + USCMROUTE_0/CLKOUT net (fanout=1) - 0.000 - 4.870 + 1.131 + 3.942 - ntclkgate_0 + ntR3950 - IOCKDIV_6_323/CLK_IODIV + PLL_158_303/CLK_OUT1 td - 0.000 - 4.870 + 0.079 + 4.021 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - net (fanout=1) - 1.306 - 6.176 + net (fanout=2) + 0.932 + 4.953 - u_axi_ddr_top/clk + nt_pix_clk - USCM_84_116/CLK_USCM + USCM_84_117/CLK_USCM td 0.000 - 6.176 + 4.953 r - clkbufg_0/gopclkbufg/CLKOUT + clkbufg_2/gopclkbufg/CLKOUT - net (fanout=5464) - 0.925 - 7.101 + net (fanout=1635) + 1.037 + 5.990 - ntclkbufg_0 + ntclkbufg_2 - CLMA_66_216/CLK + DRM_178_272/CLKB[0] r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[151]/opit_0_inv/CLK + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] clock pessimism - -0.428 - 6.673 + -0.332 + 5.658 @@ -143755,15 +147726,15 @@ clock uncertainty 0.000 - 6.673 + 5.658 Removal time - 0.000 - 6.673 + -0.063 + 5.595 @@ -143772,27 +147743,27 @@ - 0.555 - 1 - 619 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[2]/opit_0_inv/RS + 0.860 + 0 + 114 + u_zoom_rst/rst/opit_0_L5Q_perm/CLK + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[6].U_GTP_DRM18K/iGopDrm/RSTA[0] - ddrphy_clkin - ddrphy_clkin + clk_1080p60Hz + clk_1080p60Hz rise-rise - 0.019 - 6.654 - 7.101 - -0.428 + 0.030 + 5.520 + 5.882 + -0.332 0.000 - 0.574 - 0.274 (47.7%) - 0.300 (52.3%) + 0.830 + 0.182 (21.9%) + 0.648 (78.1%) - Path #8: removal slack is 0.555(MET) + Path #11: removal slack is 0.860(MET) -
+
Location Delay Type @@ -143802,7 +147773,7 @@ Logical Resource - Clock ddrphy_clkin (rising edge) + Clock clk_1080p60Hz (rising edge) 0.000 0.000 @@ -143858,153 +147829,105 @@ _N69 - PLL_158_55/CLK_OUT1 + PLL_158_55/CLK_OUT0 td - 0.074 - 1.934 + 0.078 + 1.938 r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 + u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 0.603 - 2.537 + 2.541 - zoom_clk + rd3_clk - USCM_84_113/CLK_USCM + USCM_84_154/CLK_USCM td 0.000 - 2.537 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 0.981 - 3.518 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.089 - 3.607 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 0.669 - 4.276 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.200 - 4.476 + 2.541 r - clkgate_8/gopclkgate/OUT + USCMROUTE_0/CLKOUT net (fanout=1) - 0.000 - 4.476 + 1.091 + 3.632 - ntclkgate_0 + ntR3950 - IOCKDIV_6_323/CLK_IODIV + PLL_158_303/CLK_OUT0 td - 0.000 - 4.476 + 0.078 + 3.710 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 net (fanout=1) - 1.283 - 5.759 + 0.915 + 4.625 - u_axi_ddr_top/clk + zoom_clk - USCM_84_116/CLK_USCM + USCM_84_118/CLK_USCM td 0.000 - 5.759 + 4.625 r - clkbufg_0/gopclkbufg/CLKOUT + clkbufg_3/gopclkbufg/CLKOUT - net (fanout=5464) + net (fanout=750) 0.895 - 6.654 + 5.520 - ntclkbufg_0 + ntclkbufg_3 - CLMA_70_192/CLK + CLMA_170_124/CLK r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK + u_zoom_rst/rst/opit_0_L5Q_perm/CLK - CLMA_70_192/Q0 + CLMA_170_124/Q0 tco 0.182 - 6.836 + 5.702 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q - - - - net (fanout=619) - 0.300 - 7.136 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n - - - CLMA_66_212/RSCO - td - 0.092 - 7.228 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[37]/opit_0_inv/RSOUT + u_zoom_rst/rst/opit_0_L5Q_perm/Q - net (fanout=4) - 0.000 - 7.228 + net (fanout=114) + 0.648 + 6.350 - ntR1484 + zoom_rst - CLMA_66_216/RSCI + DRM_234_128/RSTA[0] - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[2]/opit_0_inv/RS + r + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[6].U_GTP_DRM18K/iGopDrm/RSTA[0]
- +
Location Delay Type @@ -144014,7 +147937,7 @@ Logical Resource - Clock ddrphy_clkin (rising edge) + Clock clk_1080p60Hz (rising edge) 0.000 0.000 @@ -144070,114 +147993,82 @@ _N69 - PLL_158_55/CLK_OUT1 + PLL_158_55/CLK_OUT0 td - 0.079 - 2.193 + 0.083 + 2.197 r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 + u_sys_pll/u_pll_e3/goppll/CLKOUT0 net (fanout=2) 0.614 - 2.807 + 2.811 - zoom_clk + rd3_clk - USCM_84_113/CLK_USCM + USCM_84_154/CLK_USCM td 0.000 - 2.807 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.019 - 3.826 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.094 - 3.920 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 0.682 - 4.602 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.268 - 4.870 + 2.811 r - clkgate_8/gopclkgate/OUT + USCMROUTE_0/CLKOUT net (fanout=1) - 0.000 - 4.870 + 1.131 + 3.942 - ntclkgate_0 + ntR3950 - IOCKDIV_6_323/CLK_IODIV + PLL_158_303/CLK_OUT0 td - 0.000 - 4.870 + 0.083 + 4.025 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 net (fanout=1) - 1.306 - 6.176 + 0.932 + 4.957 - u_axi_ddr_top/clk + zoom_clk - USCM_84_116/CLK_USCM + USCM_84_118/CLK_USCM td 0.000 - 6.176 + 4.957 r - clkbufg_0/gopclkbufg/CLKOUT + clkbufg_3/gopclkbufg/CLKOUT - net (fanout=5464) + net (fanout=750) 0.925 - 7.101 + 5.882 - ntclkbufg_0 + ntclkbufg_3 - CLMA_66_216/CLK + DRM_234_128/CLKA[0] r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[2]/opit_0_inv/CLK + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[6].U_GTP_DRM18K/iGopDrm/CLKA[0] clock pessimism - -0.428 - 6.673 + -0.332 + 5.550 @@ -144185,15 +148076,15 @@ clock uncertainty 0.000 - 6.673 + 5.550 Removal time - 0.000 - 6.673 + -0.060 + 5.490 @@ -144202,27 +148093,27 @@ - 0.555 - 1 - 619 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[3]/opit_0_inv/RS + 0.873 + 0 + 3 + rstn_out1/opit_0_inv/CLK + ms72xx_ctl/rstn_temp1/opit_0_inv/RS - ddrphy_clkin - ddrphy_clkin + clk_10m + clk_10m rise-rise - 0.019 - 6.654 - 7.101 - -0.428 + 0.142 + 3.437 + 3.849 + -0.270 0.000 - 0.574 - 0.274 (47.7%) - 0.300 (52.3%) + 0.828 + 0.182 (22.0%) + 0.646 (78.0%) - Path #9: removal slack is 0.555(MET) + Path #12: removal slack is 0.873(MET) -
+
Location Delay Type @@ -144232,7 +148123,7 @@ Logical Resource - Clock ddrphy_clkin (rising edge) + Clock clk_10m (rising edge) 0.000 0.000 @@ -144288,153 +148179,73 @@ _N69 - PLL_158_55/CLK_OUT1 - td - 0.074 - 1.934 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 0.603 - 2.537 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 2.537 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 0.981 - 3.518 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.089 - 3.607 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 0.669 - 4.276 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.200 - 4.476 - r - clkgate_8/gopclkgate/OUT - - - - net (fanout=1) - 0.000 - 4.476 - - ntclkgate_0 - - - IOCKDIV_6_323/CLK_IODIV + PLL_158_55/CLK_OUT4 td - 0.000 - 4.476 + 0.079 + 1.939 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + u_sys_pll/u_pll_e3/goppll/CLKOUT4 net (fanout=1) - 1.283 - 5.759 + 0.603 + 2.542 - u_axi_ddr_top/clk + clk_10m - USCM_84_116/CLK_USCM + USCM_84_110/CLK_USCM td 0.000 - 5.759 + 2.542 r - clkbufg_0/gopclkbufg/CLKOUT + clkbufg_4/gopclkbufg/CLKOUT - net (fanout=5464) + net (fanout=235) 0.895 - 6.654 + 3.437 - ntclkbufg_0 + ntclkbufg_4 - CLMA_70_192/CLK + CLMS_270_193/CLK r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/CLK + rstn_out1/opit_0_inv/CLK - CLMA_70_192/Q0 + CLMS_270_193/Q3 tco 0.182 - 6.836 + 3.619 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/opit_0_inv/Q - - - - net (fanout=619) - 0.300 - 7.136 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n - - - CLMA_66_212/RSCO - td - 0.092 - 7.228 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[37]/opit_0_inv/RSOUT + rstn_out1/opit_0_inv/Q - net (fanout=4) - 0.000 - 7.228 + net (fanout=3) + 0.646 + 4.265 - ntR1484 + nt_eth_rstn - CLMA_66_216/RSCI + CLMA_262_268/RS - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[3]/opit_0_inv/RS + r + ms72xx_ctl/rstn_temp1/opit_0_inv/RS
- +
Location Delay Type @@ -144444,7 +148255,7 @@ Logical Resource - Clock ddrphy_clkin (rising edge) + Clock clk_10m (rising edge) 0.000 0.000 @@ -144500,114 +148311,50 @@ _N69 - PLL_158_55/CLK_OUT1 - td - 0.079 - 2.193 - r - u_sys_pll/u_pll_e3/goppll/CLKOUT1 - - - - net (fanout=2) - 0.614 - 2.807 - - zoom_clk - - - USCM_84_113/CLK_USCM - td - 0.000 - 2.807 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/gopclkbufg/CLKOUT - - - - net (fanout=68) - 1.019 - 3.826 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - PLL_158_199/CLK_OUT0_WL - td - 0.094 - 3.920 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/goppll/CLKOUT0_WL - - - - net (fanout=3) - 0.682 - 4.602 - - clkout0_wl_0 - - - IOCKGATE_6_322/OUT - td - 0.268 - 4.870 - r - clkgate_8/gopclkgate/OUT - - - - net (fanout=1) - 0.000 - 4.870 - - ntclkgate_0 - - - IOCKDIV_6_323/CLK_IODIV + PLL_158_55/CLK_OUT4 td - 0.000 - 4.870 + 0.084 + 2.198 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/gopclkdiv/CLKDIV + u_sys_pll/u_pll_e3/goppll/CLKOUT4 net (fanout=1) - 1.306 - 6.176 + 0.614 + 2.812 - u_axi_ddr_top/clk + clk_10m - USCM_84_116/CLK_USCM + USCM_84_110/CLK_USCM td 0.000 - 6.176 + 2.812 r - clkbufg_0/gopclkbufg/CLKOUT + clkbufg_4/gopclkbufg/CLKOUT - net (fanout=5464) - 0.925 - 7.101 + net (fanout=235) + 1.037 + 3.849 - ntclkbufg_0 + ntclkbufg_4 - CLMA_66_216/CLK + CLMA_262_268/CLK r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[3]/opit_0_inv/CLK + ms72xx_ctl/rstn_temp1/opit_0_inv/CLK clock pessimism - -0.428 - 6.673 + -0.270 + 3.579 @@ -144615,15 +148362,15 @@ clock uncertainty 0.000 - 6.673 + 3.579 Removal time - 0.000 - 6.673 + -0.187 + 3.392 @@ -144632,27 +148379,27 @@ - 0.851 + 0.912 0 - 163 - u_hdmi_rst/rst/opit_0_L5Q_perm/CLK - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[12].U_GTP_DRM18K/iGopDrm/RSTB[0] + 114 + u_zoom_rst/rst/opit_0_L5Q_perm/CLK + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/RSTA[0] - clk_720p60Hz - clk_720p60Hz + clk_1080p60Hz + clk_1080p60Hz rise-rise 0.019 - 5.516 - 5.878 + 5.520 + 5.882 -0.343 0.000 - 0.807 - 0.182 (22.6%) - 0.625 (77.4%) + 0.871 + 0.182 (20.9%) + 0.689 (79.1%) - Path #10: removal slack is 0.851(MET) + Path #13: removal slack is 0.912(MET) -
+
Location Delay Type @@ -144662,7 +148409,7 @@ Logical Resource - Clock clk_720p60Hz (rising edge) + Clock clk_1080p60Hz (rising edge) 0.000 0.000 @@ -144747,76 +148494,76 @@ 1.091 3.632 - ntR3907 + ntR3950 - PLL_158_303/CLK_OUT1 + PLL_158_303/CLK_OUT0 td - 0.074 - 3.706 + 0.078 + 3.710 r - U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 - net (fanout=2) + net (fanout=1) 0.915 - 4.621 + 4.625 - nt_pix_clk + zoom_clk - USCM_84_117/CLK_USCM + USCM_84_118/CLK_USCM td 0.000 - 4.621 + 4.625 r - clkbufg_2/gopclkbufg/CLKOUT + clkbufg_3/gopclkbufg/CLKOUT - net (fanout=1635) + net (fanout=750) 0.895 - 5.516 + 5.520 - ntclkbufg_2 + ntclkbufg_3 - CLMA_190_124/CLK + CLMA_170_124/CLK r - u_hdmi_rst/rst/opit_0_L5Q_perm/CLK + u_zoom_rst/rst/opit_0_L5Q_perm/CLK - CLMA_190_124/Q0 + CLMA_170_124/Q0 tco 0.182 - 5.698 + 5.702 r - u_hdmi_rst/rst/opit_0_L5Q_perm/Q + u_zoom_rst/rst/opit_0_L5Q_perm/Q - net (fanout=163) - 0.625 - 6.323 + net (fanout=114) + 0.689 + 6.391 - rd2_rst + zoom_rst - DRM_234_88/RSTB[0] + DRM_234_88/RSTA[0] r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[12].U_GTP_DRM18K/iGopDrm/RSTB[0] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/RSTA[0]
- +
Location Delay Type @@ -144826,7 +148573,7 @@ Logical Resource - Clock clk_720p60Hz (rising edge) + Clock clk_1080p60Hz (rising edge) 0.000 0.000 @@ -144911,53 +148658,53 @@ 1.131 3.942 - ntR3907 + ntR3950 - PLL_158_303/CLK_OUT1 + PLL_158_303/CLK_OUT0 td - 0.079 - 4.021 + 0.083 + 4.025 r - U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 - net (fanout=2) + net (fanout=1) 0.932 - 4.953 + 4.957 - nt_pix_clk + zoom_clk - USCM_84_117/CLK_USCM + USCM_84_118/CLK_USCM td 0.000 - 4.953 + 4.957 r - clkbufg_2/gopclkbufg/CLKOUT + clkbufg_3/gopclkbufg/CLKOUT - net (fanout=1635) + net (fanout=750) 0.925 - 5.878 + 5.882 - ntclkbufg_2 + ntclkbufg_3 - DRM_234_88/CLKB[0] + DRM_234_88/CLKA[0] r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[12].U_GTP_DRM18K/iGopDrm/CLKB[0] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] clock pessimism -0.343 - 5.535 + 5.539 @@ -144965,15 +148712,15 @@ clock uncertainty 0.000 - 5.535 + 5.539 Removal time - -0.063 - 5.472 + -0.060 + 5.479 @@ -144982,27 +148729,27 @@ - 0.915 - 0 + 0.924 3 - rstn_out1/opit_0_inv/CLK - ms72xx_ctl/rstn_temp1/opit_0_inv/RS + 911 + sync_vg_100m/opit_0_inv_L5Q_perm/CLK + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/RS - clk_10m - clk_10m + clk_720p60Hz + clk_720p60Hz rise-rise - 0.019 - 3.437 - 3.737 - -0.281 + 0.032 + 5.626 + 5.990 + -0.332 0.000 - 0.747 - 0.182 (24.4%) - 0.565 (75.6%) + 0.956 + 0.437 (45.7%) + 0.519 (54.3%) - Path #11: removal slack is 0.915(MET) + Path #14: removal slack is 0.924(MET) -
+
Location Delay Type @@ -145012,7 +148759,7 @@ Logical Resource - Clock clk_10m (rising edge) + Clock clk_720p60Hz (rising edge) 0.000 0.000 @@ -145068,73 +148815,153 @@ _N69 - PLL_158_55/CLK_OUT4 + PLL_158_55/CLK_OUT0 td - 0.079 - 1.939 + 0.078 + 1.938 r - u_sys_pll/u_pll_e3/goppll/CLKOUT4 + u_sys_pll/u_pll_e3/goppll/CLKOUT0 - net (fanout=1) + net (fanout=2) 0.603 - 2.542 + 2.541 - clk_10m + rd3_clk - USCM_84_110/CLK_USCM + USCM_84_154/CLK_USCM td 0.000 - 2.542 + 2.541 r - clkbufg_3/gopclkbufg/CLKOUT + USCMROUTE_0/CLKOUT - net (fanout=235) - 0.895 - 3.437 + net (fanout=1) + 1.091 + 3.632 - ntclkbufg_3 + ntR3950 + + + PLL_158_303/CLK_OUT1 + td + 0.074 + 3.706 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + + + + net (fanout=2) + 0.915 + 4.621 + + nt_pix_clk + + + USCM_84_117/CLK_USCM + td + 0.000 + 4.621 + r + clkbufg_2/gopclkbufg/CLKOUT + + + + net (fanout=1635) + 1.005 + 5.626 + + ntclkbufg_2 - CLMA_230_69/CLK + CLMA_150_276/CLK r - rstn_out1/opit_0_inv/CLK + sync_vg_100m/opit_0_inv_L5Q_perm/CLK - CLMA_230_69/Q3 + CLMA_150_276/Q0 tco 0.182 - 3.619 + 5.808 r - rstn_out1/opit_0_inv/Q + sync_vg_100m/opit_0_inv_L5Q_perm/Q + + + + net (fanout=911) + 0.519 + 6.327 + + sync_vg_100m + + + CLMA_182_281/RSCO + td + 0.085 + 6.412 + r + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_L5Q_perm/RSOUT net (fanout=3) - 0.565 - 4.184 + 0.000 + 6.412 - nt_eth_rstn + ntR691 + + + CLMA_182_285/RSCO + td + 0.085 + 6.497 + r + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[10]/opit_0_inv_L5Q_perm/RSOUT + + + + net (fanout=4) + 0.000 + 6.497 + + ntR690 + + + CLMA_182_289/RSCO + td + 0.085 + 6.582 + r + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/RSOUT - CLMA_246_120/RS + + net (fanout=5) + 0.000 + 6.582 + + ntR689 + + + CLMA_182_293/RSCI r - ms72xx_ctl/rstn_temp1/opit_0_inv/RS + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/RS
- +
Location Delay Type @@ -145144,7 +148971,7 @@ Logical Resource - Clock clk_10m (rising edge) + Clock clk_720p60Hz (rising edge) 0.000 0.000 @@ -145200,50 +149027,82 @@ _N69 - PLL_158_55/CLK_OUT4 + PLL_158_55/CLK_OUT0 td - 0.084 - 2.198 + 0.083 + 2.197 r - u_sys_pll/u_pll_e3/goppll/CLKOUT4 + u_sys_pll/u_pll_e3/goppll/CLKOUT0 - net (fanout=1) + net (fanout=2) 0.614 - 2.812 + 2.811 - clk_10m + rd3_clk - USCM_84_110/CLK_USCM + USCM_84_154/CLK_USCM td 0.000 - 2.812 + 2.811 r - clkbufg_3/gopclkbufg/CLKOUT + USCMROUTE_0/CLKOUT - net (fanout=235) - 0.925 - 3.737 + net (fanout=1) + 1.131 + 3.942 - ntclkbufg_3 + ntR3950 + + + PLL_158_303/CLK_OUT1 + td + 0.079 + 4.021 + r + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 - CLMA_246_120/CLK + + net (fanout=2) + 0.932 + 4.953 + + nt_pix_clk + + + USCM_84_117/CLK_USCM + td + 0.000 + 4.953 + r + clkbufg_2/gopclkbufg/CLKOUT + + + + net (fanout=1635) + 1.037 + 5.990 + + ntclkbufg_2 + + + CLMA_182_293/CLK r - ms72xx_ctl/rstn_temp1/opit_0_inv/CLK + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/opit_0_L5Q_perm/CLK clock pessimism - -0.281 - 3.456 + -0.332 + 5.658 @@ -145251,15 +149110,15 @@ clock uncertainty 0.000 - 3.456 + 5.658 Removal time - -0.187 - 3.269 + 0.000 + 5.658 @@ -145268,27 +149127,27 @@ - 0.926 - 0 - 163 - u_hdmi_rst/rst/opit_0_L5Q_perm/CLK - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0] + 0.924 + 3 + 911 + sync_vg_100m/opit_0_inv_L5Q_perm/CLK + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm/RS clk_720p60Hz clk_720p60Hz rise-rise - 0.030 - 5.516 - 5.878 + 0.032 + 5.626 + 5.990 -0.332 0.000 - 0.893 - 0.182 (20.4%) - 0.711 (79.6%) + 0.956 + 0.437 (45.7%) + 0.519 (54.3%) - Path #12: removal slack is 0.926(MET) + Path #15: removal slack is 0.924(MET) -
+
Location Delay Type @@ -145383,7 +149242,7 @@ 1.091 3.632 - ntR3907 + ntR3950 PLL_158_303/CLK_OUT1 @@ -145412,47 +149271,95 @@ net (fanout=1635) - 0.895 - 5.516 + 1.005 + 5.626 ntclkbufg_2 - CLMA_190_124/CLK + CLMA_150_276/CLK r - u_hdmi_rst/rst/opit_0_L5Q_perm/CLK + sync_vg_100m/opit_0_inv_L5Q_perm/CLK - CLMA_190_124/Q0 + CLMA_150_276/Q0 tco 0.182 - 5.698 + 5.808 r - u_hdmi_rst/rst/opit_0_L5Q_perm/Q + sync_vg_100m/opit_0_inv_L5Q_perm/Q - net (fanout=163) - 0.711 - 6.409 + net (fanout=911) + 0.519 + 6.327 - rd2_rst + sync_vg_100m + + + CLMA_182_281/RSCO + td + 0.085 + 6.412 + r + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/opit_0_inv_L5Q_perm/RSOUT - DRM_234_148/RSTB[0] + + net (fanout=3) + 0.000 + 6.412 + + ntR691 + + + CLMA_182_285/RSCO + td + 0.085 + 6.497 + r + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[10]/opit_0_inv_L5Q_perm/RSOUT + + + + net (fanout=4) + 0.000 + 6.497 + + ntR690 + + + CLMA_182_289/RSCO + td + 0.085 + 6.582 + r + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/opit_0/RSOUT + + + + net (fanout=5) + 0.000 + 6.582 + + ntR689 + + + CLMA_182_293/RSCI r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0] + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm/RS
- +
Location Delay Type @@ -145547,7 +149454,7 @@ 1.131 3.942 - ntR3907 + ntR3950 PLL_158_303/CLK_OUT1 @@ -145576,24 +149483,24 @@ net (fanout=1635) - 0.925 - 5.878 + 1.037 + 5.990 ntclkbufg_2 - DRM_234_148/CLKB[0] + CLMA_182_293/CLK r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/opit_0_L5Q_perm/CLK clock pessimism -0.332 - 5.546 + 5.658 @@ -145601,15 +149508,15 @@ clock uncertainty 0.000 - 5.546 + 5.658 Removal time - -0.063 - 5.483 + 0.000 + 5.658 @@ -145618,27 +149525,27 @@ - 0.953 + 0.945 0 - 163 - u_hdmi_rst/rst/opit_0_L5Q_perm/CLK - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0] + 114 + u_zoom_rst/rst/opit_0_L5Q_perm/CLK + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[7].U_GTP_DRM18K/iGopDrm/RSTA[0] - clk_720p60Hz - clk_720p60Hz + clk_1080p60Hz + clk_1080p60Hz rise-rise - 0.030 - 5.516 - 5.878 - -0.332 + 0.019 + 5.520 + 5.882 + -0.343 0.000 - 0.920 - 0.182 (19.8%) - 0.738 (80.2%) + 0.904 + 0.182 (20.1%) + 0.722 (79.9%) - Path #13: removal slack is 0.953(MET) + Path #16: removal slack is 0.945(MET) -
+
Location Delay Type @@ -145648,7 +149555,7 @@ Logical Resource - Clock clk_720p60Hz (rising edge) + Clock clk_1080p60Hz (rising edge) 0.000 0.000 @@ -145733,76 +149640,76 @@ 1.091 3.632 - ntR3907 + ntR3950 - PLL_158_303/CLK_OUT1 + PLL_158_303/CLK_OUT0 td - 0.074 - 3.706 + 0.078 + 3.710 r - U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 - net (fanout=2) + net (fanout=1) 0.915 - 4.621 + 4.625 - nt_pix_clk + zoom_clk - USCM_84_117/CLK_USCM + USCM_84_118/CLK_USCM td 0.000 - 4.621 + 4.625 r - clkbufg_2/gopclkbufg/CLKOUT + clkbufg_3/gopclkbufg/CLKOUT - net (fanout=1635) + net (fanout=750) 0.895 - 5.516 + 5.520 - ntclkbufg_2 + ntclkbufg_3 - CLMA_190_124/CLK + CLMA_170_124/CLK r - u_hdmi_rst/rst/opit_0_L5Q_perm/CLK + u_zoom_rst/rst/opit_0_L5Q_perm/CLK - CLMA_190_124/Q0 + CLMA_170_124/Q0 tco 0.182 - 5.698 + 5.702 r - u_hdmi_rst/rst/opit_0_L5Q_perm/Q + u_zoom_rst/rst/opit_0_L5Q_perm/Q - net (fanout=163) - 0.738 - 6.436 + net (fanout=114) + 0.722 + 6.424 - rd2_rst + zoom_rst - DRM_234_168/RSTB[0] + DRM_234_108/RSTA[0] r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/RSTB[0] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[7].U_GTP_DRM18K/iGopDrm/RSTA[0]
- +
Location Delay Type @@ -145812,7 +149719,7 @@ Logical Resource - Clock clk_720p60Hz (rising edge) + Clock clk_1080p60Hz (rising edge) 0.000 0.000 @@ -145897,53 +149804,53 @@ 1.131 3.942 - ntR3907 + ntR3950 - PLL_158_303/CLK_OUT1 + PLL_158_303/CLK_OUT0 td - 0.079 - 4.021 + 0.083 + 4.025 r - U_HDMI_PLL/u_pll_e3/goppll/CLKOUT1 + U_HDMI_PLL/u_pll_e3/goppll/CLKOUT0 - net (fanout=2) + net (fanout=1) 0.932 - 4.953 + 4.957 - nt_pix_clk + zoom_clk - USCM_84_117/CLK_USCM + USCM_84_118/CLK_USCM td 0.000 - 4.953 + 4.957 r - clkbufg_2/gopclkbufg/CLKOUT + clkbufg_3/gopclkbufg/CLKOUT - net (fanout=1635) + net (fanout=750) 0.925 - 5.878 + 5.882 - ntclkbufg_2 + ntclkbufg_3 - DRM_234_168/CLKB[0] + DRM_234_108/CLKA[0] r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKB[0] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[7].U_GTP_DRM18K/iGopDrm/CLKA[0] clock pessimism - -0.332 - 5.546 + -0.343 + 5.539 @@ -145951,15 +149858,15 @@ clock uncertainty 0.000 - 5.546 + 5.539 Removal time - -0.063 - 5.483 + -0.060 + 5.479 @@ -145983,7 +149890,7 @@ 1.250 0.682 ioclk2 - Low Pulse Width + High Pulse Width DQSL_6_28/CLK_IO u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_ddc_ca/opit_0/IOCLK @@ -145992,7 +149899,7 @@ 1.250 0.682 ioclk2 - High Pulse Width + Low Pulse Width DQSL_6_28/CLK_IO u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_ddc_ca/opit_0/IOCLK @@ -146001,7 +149908,7 @@ 1.250 0.682 ioclk0 - Low Pulse Width + High Pulse Width DQSL_6_348/CLK_IO u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[1].u_ddc_ca/opit_0/IOCLK @@ -146010,7 +149917,7 @@ 1.250 0.682 ioclk0 - High Pulse Width + Low Pulse Width DQSL_6_348/CLK_IO u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[1].u_ddc_ca/opit_0/IOCLK @@ -146060,30 +149967,57 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/u_ddc_dqs/opit_0/IOCLK - 1.590 + 2.004 2.500 - 0.910 + 0.496 clk_200m High Pulse Width - APM_206_228/CLK - u_zoom_image/mult_fra0/N2/gopapm/CLK + CLMS_34_181/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[0]/opit_0_inv_L5Q_perm/CLK - 1.590 + 2.004 2.500 - 0.910 + 0.496 clk_200m Low Pulse Width - APM_206_228/CLK - u_zoom_image/mult_fra0/N2/gopapm/CLK + CLMS_34_181/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[0]/opit_0_inv_L5Q_perm/CLK - 1.590 + 2.004 2.500 - 0.910 + 0.496 clk_200m + High Pulse Width + CLMS_34_193/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[1]/opit_0_inv_L5Q_perm/CLK + + + 2.458 + 3.368 + 0.910 + clk_1080p60Hz Low Pulse Width - APM_206_140/CLK + APM_206_28/CLK + u_zoom_image/mult_fra0/N2/gopapm/CLK + + + 2.458 + 3.368 + 0.910 + clk_1080p60Hz + High Pulse Width + APM_206_28/CLK + u_zoom_image/mult_fra0/N2/gopapm/CLK + + + 2.458 + 3.368 + 0.910 + clk_1080p60Hz + High Pulse Width + APM_206_264/CLK u_zoom_image/mult_fra0_0/N2/gopapm/CLK @@ -146091,8 +150025,8 @@ 3.333 0.718 hdmi_in_clk - Low Pulse Width - DRM_82_108/CLKA[0] + High Pulse Width + DRM_82_128/CLKA[0] u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] @@ -146100,8 +150034,8 @@ 3.333 0.718 hdmi_in_clk - High Pulse Width - DRM_82_108/CLKA[0] + Low Pulse Width + DRM_82_128/CLKA[0] u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] @@ -146109,8 +150043,8 @@ 3.333 0.718 hdmi_in_clk - High Pulse Width - DRM_54_108/CLKA[0] + Low Pulse Width + DRM_82_88/CLKA[0] u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/iGopDrm/CLKA[0] @@ -146145,8 +150079,8 @@ 5.000 1.520 ddrphy_clkin - High Pulse Width - CLMS_38_109/CLK + Low Pulse Width + CLMS_38_101/CLK u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram16x1d/WCLK @@ -146154,8 +150088,8 @@ 5.000 1.520 ddrphy_clkin - Low Pulse Width - CLMS_38_109/CLK + High Pulse Width + CLMS_38_101/CLK u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/ram16x1d/WCLK @@ -146163,8 +150097,8 @@ 5.000 1.520 ddrphy_clkin - High Pulse Width - CLMS_34_113/CLK + Low Pulse Width + CLMS_42_101/CLK u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_2/ram16x1d/WCLK @@ -146172,7 +150106,7 @@ 5.000 0.336 ioclk_gate_clk - High Pulse Width + Low Pulse Width CLMA_150_192/CLK u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_ioclk_gate/opit_0_inv_L5Q_perm/CLK @@ -146181,7 +150115,7 @@ 5.000 0.336 ioclk_gate_clk - Low Pulse Width + High Pulse Width CLMA_150_192/CLK u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_ioclk_gate/opit_0_inv_L5Q_perm/CLK @@ -146191,7 +150125,7 @@ 0.718 cmos1_pclk Low Pulse Width - DRM_142_24/CLKA[0] + DRM_142_44/CLKA[0] u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] @@ -146200,7 +150134,7 @@ 0.718 cmos1_pclk High Pulse Width - DRM_142_24/CLKA[0] + DRM_142_44/CLKA[0] u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] @@ -146209,7 +150143,7 @@ 0.718 cmos2_pclk Low Pulse Width - DRM_142_44/CLKA[0] + DRM_142_24/CLKA[0] u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] @@ -146218,7 +150152,7 @@ 0.718 cmos2_pclk High Pulse Width - DRM_142_44/CLKA[0] + DRM_142_24/CLKA[0] u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/iGopDrm/CLKA[0] @@ -146226,18 +150160,18 @@ 5.950 0.496 cmos1_pclk - High Pulse Width - CLMS_146_9/CLK - u_ov5640/cmos1_8_16bit/de_in0/opit_0/CLK + Low Pulse Width + CLMS_134_25/CLK + u_ov5640/cmos1_8_16bit/de_cnt/opit_0_L5Q_perm/CLK 5.454 5.950 0.496 cmos2_pclk - Low Pulse Width - CLMS_150_41/CLK - u_ov5640/cmos2_8_16bit/de_cnt/opit_0_L5Q/CLK + High Pulse Width + CLMS_74_17/CLK + u_ov5640/cmos2_8_16bit/de_in0/opit_0/CLK 5.826 @@ -146245,7 +150179,7 @@ 0.910 clk_720p60Hz High Pulse Width - APM_258_140/CLK + APM_258_216/CLK adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N11/gopapm/CLK @@ -146254,7 +150188,7 @@ 0.910 clk_720p60Hz High Pulse Width - APM_258_128/CLK + APM_258_204/CLK adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N135/gopapm/CLK @@ -146263,7 +150197,7 @@ 0.910 clk_720p60Hz Low Pulse Width - APM_258_140/CLK + APM_258_216/CLK adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/N11/gopapm/CLK @@ -146271,8 +150205,8 @@ 10.000 0.910 clk_50m - High Pulse Width - APM_106_116/CLK + Low Pulse Width + APM_206_228/CLK u_rotate_image/u_rotate_mult0/N2/gopapm/CLK @@ -146280,8 +150214,8 @@ 10.000 0.910 clk_50m - Low Pulse Width - APM_106_116/CLK + High Pulse Width + APM_206_228/CLK u_rotate_image/u_rotate_mult0/N2/gopapm/CLK @@ -146290,34 +150224,34 @@ 0.910 clk_50m High Pulse Width - APM_106_104/CLK + APM_206_216/CLK u_rotate_image/u_rotate_mult1/N2/gopapm/CLK - 19.664 + 19.504 20.000 - 0.336 + 0.496 clk_25m Low Pulse Width - CLMA_182_12/CLK + CLMS_122_9/CLK u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK - 19.664 + 19.504 20.000 - 0.336 + 0.496 clk_25m High Pulse Width - CLMA_182_12/CLK + CLMS_122_9/CLK u_ov5640/coms1_reg_config/clk_20k_regdiv/opit_0_inv/CLK - 19.664 + 19.504 20.000 - 0.336 + 0.496 clk_25m High Pulse Width - CLMA_182_12/CLK + CLMS_122_9/CLK u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/opit_0_inv/CLK @@ -146326,7 +150260,7 @@ 0.718 clk_10m Low Pulse Width - DRM_234_108/CLKA[0] + DRM_234_316/CLKA[0] ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKA[0] @@ -146335,7 +150269,7 @@ 0.718 clk_10m High Pulse Width - DRM_234_108/CLKA[0] + DRM_234_316/CLKA[0] ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKA[0] @@ -146344,7 +150278,7 @@ 0.718 clk_10m Low Pulse Width - DRM_234_108/CLKB[0] + DRM_234_316/CLKB[0] ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/iGopDrm/CLKB[0] @@ -146353,7 +150287,7 @@ 0.718 clk_20k High Pulse Width - DRM_178_4/CLKA[0] + DRM_142_4/CLKA[0] u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKA[0] @@ -146362,7 +150296,7 @@ 0.718 clk_20k Low Pulse Width - DRM_178_4/CLKA[0] + DRM_142_4/CLKA[0] u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKA[0] @@ -146371,7 +150305,7 @@ 0.718 clk_20k Low Pulse Width - DRM_178_4/CLKB[0] + DRM_142_4/CLKB[0] u_ov5640/coms1_reg_config/reg_data/iGopDrm/CLKB[0]
@@ -146386,9 +150320,9 @@ RAM(GB) - 0h:0m:25s - 0h:0m:32s 0h:0m:26s + 0h:0m:35s + 0h:0m:28s 1,325 WINDOWS 10 x86_64 Intel(R) Core(TM) i7-9750H CPU @ 2.60GHz @@ -146400,9 +150334,6 @@ STA-3009: The clock clk_100m is not connected to any clock endpoints,it will be treated as a normal port or pin. - - STA-3009: The clock clk_1080p60Hz is not connected to any clock endpoints,it will be treated as a normal port or pin. - Timing-4086: Port 'cmos1_scl' is not constrained, it is treated as combinational input. diff --git a/project/synthesize/formal.pvf b/project/synthesize/formal.pvf index 89dbe61..6d9fb7b 100644 --- a/project/synthesize/formal.pvf +++ b/project/synthesize/formal.pvf @@ -3,13 +3,13 @@ #Application name: pds_shell.exe #OS: Windows 10 10.0.19045 #Hostname: OMEN-WSH -Generated by Fabric Compiler (version 2022.2-SP1-Lite build 132640) at Sat Nov 11 17:52:59 2023 +Generated by Fabric Compiler (version 2022.2-SP1-Lite build 132640) at Wed Nov 15 19:34:13 2023 #Build: Fabric Compiler 2022.2-SP1-Lite, Build 132640, Aug 18 15:12 2023 #Install: D:\Program_Files\PDS_2022.2-SP1-Lite\bin #Application name: pds_shell.exe #OS: Windows 10 10.0.19045 #Hostname: OMEN-WSH -Generated by Fabric Compiler (version 2022.2-SP1-Lite build 132640) at Sat Nov 11 17:52:08 2023 +Generated by Fabric Compiler (version 2022.2-SP1-Lite build 132640) at Wed Nov 15 19:33:20 2023 # pvf -action compile pvf_reg_constant clk_cnt[31] 0 @@ -7740,8 +7740,6 @@ pvf_reg_merging -survived param_manager_inst/param_filiter1_mode/key_debounce_i pvf_reg_merging -survived param_manager_inst/param_filiter1_mode/key_debounce_inst1/cnt[5] -deleted param_manager_inst/param_filiter1_mode/key_debounce_inst1/cnt[23] -pvf_reg_merging -survived image_filiter_inst/multiline_buffer_inst/ver_cnt[9] -deleted image_filiter_inst/multiline_buffer_inst/ver_cnt[10] - pvf_reg_merging -survived param_manager_inst/param_filiter1_mode/key_debounce_inst2/cnt[5] -deleted param_manager_inst/param_filiter1_mode/key_debounce_inst2/cnt[6] pvf_reg_merging -survived param_manager_inst/param_filiter1_mode/key_debounce_inst2/cnt[5] -deleted param_manager_inst/param_filiter1_mode/key_debounce_inst2/cnt[7] @@ -8390,6 +8388,8 @@ pvf_reg_merging -survived param_manager_inst/param_osd_startX/key_debounce_inst pvf_reg_merging -survived param_manager_inst/param_osd_startX/key_debounce_inst1/cnt[5] -deleted param_manager_inst/param_osd_startX/key_debounce_inst1/cnt[23] +pvf_reg_merging -survived image_filiter_inst/multiline_buffer_inst/ver_cnt[9] -deleted image_filiter_inst/multiline_buffer_inst/ver_cnt[10] + pvf_reg_merging -survived param_manager_inst/param_osd_startX/key_debounce_inst2/cnt[5] -deleted param_manager_inst/param_osd_startX/key_debounce_inst2/cnt[6] pvf_reg_merging -survived param_manager_inst/param_osd_startX/key_debounce_inst2/cnt[5] -deleted param_manager_inst/param_osd_startX/key_debounce_inst2/cnt[7] @@ -8694,23 +8694,27 @@ pvf_reg_merging -survived u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_sli pvf_reg_merging -survived u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/adj_cnt[5] -deleted u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/adj_cnt[7] -pvf_reg_merging -survived u_ddr_addr_ctr/clk_cnt[22] -deleted u_ddr_addr_ctr/clk_cnt[23] +pvf_reg_merging -survived u_ddr_addr_ctr/clk_cnt[20] -deleted u_ddr_addr_ctr/clk_cnt[21] -pvf_reg_merging -survived u_ddr_addr_ctr/clk_cnt[22] -deleted u_ddr_addr_ctr/clk_cnt[24] +pvf_reg_merging -survived u_ddr_addr_ctr/clk_cnt[20] -deleted u_ddr_addr_ctr/clk_cnt[22] -pvf_reg_merging -survived u_ddr_addr_ctr/clk_cnt[22] -deleted u_ddr_addr_ctr/clk_cnt[25] +pvf_reg_merging -survived u_ddr_addr_ctr/clk_cnt[20] -deleted u_ddr_addr_ctr/clk_cnt[23] -pvf_reg_merging -survived u_ddr_addr_ctr/clk_cnt[22] -deleted u_ddr_addr_ctr/clk_cnt[26] +pvf_reg_merging -survived u_ddr_addr_ctr/clk_cnt[20] -deleted u_ddr_addr_ctr/clk_cnt[24] -pvf_reg_merging -survived u_ddr_addr_ctr/clk_cnt[22] -deleted u_ddr_addr_ctr/clk_cnt[27] +pvf_reg_merging -survived u_ddr_addr_ctr/clk_cnt[20] -deleted u_ddr_addr_ctr/clk_cnt[25] -pvf_reg_merging -survived u_ddr_addr_ctr/clk_cnt[22] -deleted u_ddr_addr_ctr/clk_cnt[28] +pvf_reg_merging -survived u_ddr_addr_ctr/clk_cnt[20] -deleted u_ddr_addr_ctr/clk_cnt[26] -pvf_reg_merging -survived u_ddr_addr_ctr/clk_cnt[22] -deleted u_ddr_addr_ctr/clk_cnt[29] +pvf_reg_merging -survived u_ddr_addr_ctr/clk_cnt[20] -deleted u_ddr_addr_ctr/clk_cnt[27] -pvf_reg_merging -survived u_ddr_addr_ctr/clk_cnt[22] -deleted u_ddr_addr_ctr/clk_cnt[30] +pvf_reg_merging -survived u_ddr_addr_ctr/clk_cnt[20] -deleted u_ddr_addr_ctr/clk_cnt[28] -pvf_reg_merging -survived u_ddr_addr_ctr/clk_cnt[22] -deleted u_ddr_addr_ctr/clk_cnt[31] +pvf_reg_merging -survived u_ddr_addr_ctr/clk_cnt[20] -deleted u_ddr_addr_ctr/clk_cnt[29] + +pvf_reg_merging -survived u_ddr_addr_ctr/clk_cnt[20] -deleted u_ddr_addr_ctr/clk_cnt[30] + +pvf_reg_merging -survived u_ddr_addr_ctr/clk_cnt[20] -deleted u_ddr_addr_ctr/clk_cnt[31] pvf_reg_merging -survived image_filiter_inst2/multiline_buffer_inst/ver_cnt[9] -deleted image_filiter_inst2/multiline_buffer_inst/ver_cnt[10] @@ -8828,7 +8832,7 @@ pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_lp/state_re pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/zqcs_req 0 -pvf_reg_constant u_ddr_addr_ctr/clk_cnt[22] 0 +pvf_reg_constant u_ddr_addr_ctr/clk_cnt[20] 0 pvf_reg_constant u_ddr_addr_ctr/u_rd0_addr_ctr/rd0_sta_reg[3] 0 @@ -9820,35 +9824,35 @@ pvf_reg_merging -survived param_manager_inst/param_filiter1_mode/key_debounce_i pvf_reg_merging -survived param_manager_inst/param_filiter1_mode/key_debounce_inst2/cnt[23:0] -deleted param_manager_inst/param_rotate/key_debounce_inst2/cnt[23:0] -pvf_reg_merging -survived udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][7:0] -deleted udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[4][7:0] +pvf_reg_merging -survived udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][7:0] -deleted udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[2][7:0] -pvf_reg_merging -survived udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][7:0] -deleted udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[5][7:0] +pvf_reg_merging -survived udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][7:0] -deleted udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][7:0] -pvf_reg_merging -survived udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][7:0] -deleted udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[6][7:0] +pvf_reg_merging -survived udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][7:0] -deleted udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[4][7:0] -pvf_reg_merging -survived udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][7:0] -deleted udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/eth_head[11][7:0] +pvf_reg_merging -survived udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][7:0] -deleted udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[5][7:0] -pvf_reg_merging -survived udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][7:0] -deleted udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[0][7:0] +pvf_reg_merging -survived udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][7:0] -deleted udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[6][7:0] -pvf_reg_merging -survived udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][7:0] -deleted udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][7:0] +pvf_reg_merging -survived udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][7:0] -deleted udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/eth_head[11][7:0] -pvf_reg_merging -survived udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][7:0] -deleted udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[2][7:0] +pvf_reg_merging -survived udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][7:0] -deleted udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[0][7:0] -pvf_reg_merging -survived udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][7:0] -deleted udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/preamble[0][7:0] +pvf_reg_merging -survived udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][7:0] -deleted udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/preamble[0][7:0] -pvf_reg_merging -survived udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][7:0] -deleted udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/preamble[1][7:0] +pvf_reg_merging -survived udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][7:0] -deleted udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/preamble[1][7:0] -pvf_reg_merging -survived udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][7:0] -deleted udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/preamble[2][7:0] +pvf_reg_merging -survived udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][7:0] -deleted udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/preamble[2][7:0] -pvf_reg_merging -survived udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][7:0] -deleted udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/preamble[3][7:0] +pvf_reg_merging -survived udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][7:0] -deleted udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/preamble[3][7:0] -pvf_reg_merging -survived udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][7:0] -deleted udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/preamble[4][7:0] +pvf_reg_merging -survived udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][7:0] -deleted udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/preamble[4][7:0] -pvf_reg_merging -survived udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][7:0] -deleted udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/preamble[5][7:0] +pvf_reg_merging -survived udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][7:0] -deleted udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/preamble[5][7:0] -pvf_reg_merging -survived udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][7:0] -deleted udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/preamble[6][7:0] +pvf_reg_merging -survived udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][7:0] -deleted udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/preamble[6][7:0] -pvf_reg_merging -survived udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][7:0] -deleted udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[11][7:0] +pvf_reg_merging -survived udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][7:0] -deleted udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[11][7:0] pvf_reg_merging -survived udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[7][7:0] -deleted udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/preamble[7][7:0] @@ -10632,21 +10636,21 @@ pvf_reg_constant udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/eth_head[13][6] 0 pvf_reg_constant udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/eth_head[13][7] 0 -pvf_reg_constant udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][0] 1 +pvf_reg_constant udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][0] 1 -pvf_reg_constant udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][1] 0 +pvf_reg_constant udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][1] 0 -pvf_reg_constant udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][2] 1 +pvf_reg_constant udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][2] 1 -pvf_reg_constant udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][3] 0 +pvf_reg_constant udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][3] 0 -pvf_reg_constant udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][4] 1 +pvf_reg_constant udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][4] 1 -pvf_reg_constant udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][5] 0 +pvf_reg_constant udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][5] 0 -pvf_reg_constant udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][6] 1 +pvf_reg_constant udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][6] 1 -pvf_reg_constant udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][7] 0 +pvf_reg_constant udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][7] 0 pvf_reg_constant udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[7][0] 1 @@ -10824,32 +10828,32 @@ pvf_reg_constant u_ddr_addr_ctr/u_rd1_addr_ctr/dec_sift[9] 0 pvf_reg_constant u_ddr_addr_ctr/u_rd1_addr_ctr/mult_h[0] 0 -pvf_reg_constant u_ddr_addr_ctr/u_rd1_addr_ctr/mult_addr[6] 0 - -pvf_reg_constant u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[6] 0 - pvf_reg_constant u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[23] 1 pvf_reg_constant u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[24] 1 -pvf_reg_constant u_axi_ddr_top/rd1_ddr_sart_addr0[8] 0 +pvf_reg_constant u_ddr_addr_ctr/u_rd1_addr_ctr/mult_addr[6] 0 pvf_reg_constant u_axi_ddr_top/rd1_ddr_sart_addr0[25] 1 pvf_reg_constant u_axi_ddr_top/rd1_ddr_sart_addr0[26] 1 -pvf_reg_constant u_axi_ddr_top/rd1_ddr_sart_addr1[8] 0 +pvf_reg_constant u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[6] 0 pvf_reg_constant u_axi_ddr_top/rd1_ddr_sart_addr1[25] 1 pvf_reg_constant u_axi_ddr_top/rd1_ddr_sart_addr1[26] 1 -pvf_reg_constant u_axi_ddr_top/rd1_ddr_sart_addr2[8] 0 +pvf_reg_constant u_axi_ddr_top/rd1_ddr_sart_addr0[8] 0 pvf_reg_constant u_axi_ddr_top/rd1_ddr_sart_addr2[25] 1 pvf_reg_constant u_axi_ddr_top/rd1_ddr_sart_addr2[26] 1 +pvf_reg_constant u_axi_ddr_top/rd1_ddr_sart_addr1[8] 0 + +pvf_reg_constant u_axi_ddr_top/rd1_ddr_sart_addr2[8] 0 + pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt0[2] 0 pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt0[0] 0 @@ -10984,6 +10988,58 @@ pvf_reg_merging -survived u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi pvf_reg_merging -survived u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[41] -deleted u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[42] +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[4] 0 + +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt0[0] 0 + +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt0[5] 0 + +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[6] 0 + +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt2[4] 0 + +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt0[0] 0 + +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt0[5] 0 + +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[6] 0 + +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[4] 0 + +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/timing_cnt[5] 0 + +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/timing_cnt[5] 0 + +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/timing_cnt[5] 0 + +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/timing_cnt[5] 0 + +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[5] 0 + +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/timing_cnt[5] 0 + +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/timing_cnt[5] 0 + +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/timing_cnt[5] 0 + +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[6] 0 + +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[6] 0 + +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[6] 0 + +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[6] 0 + +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[6] 0 + +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[6] 0 + +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[6] 0 + +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[6] 0 + +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[4] 0 + pvf_reg_constant u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[0] 0 pvf_reg_constant u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[1] 0 @@ -11000,8 +11056,6 @@ pvf_reg_constant u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[6] 0 pvf_reg_constant u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[7] 0 -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[4] 0 - pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[6] 0 pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt0[0] 0 @@ -11062,56 +11116,6 @@ pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcd pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[6] 0 -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[4] 0 - -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt0[0] 0 - -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt0[5] 0 - -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[6] 0 - -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt2[4] 0 - -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt0[0] 0 - -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt0[5] 0 - -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[6] 0 - -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[4] 0 - -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/timing_cnt[5] 0 - -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/timing_cnt[5] 0 - -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/timing_cnt[5] 0 - -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/timing_cnt[5] 0 - -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[5] 0 - -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/timing_cnt[5] 0 - -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/timing_cnt[5] 0 - -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/timing_cnt[5] 0 - -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[6] 0 - -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[6] 0 - -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[6] 0 - -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[6] 0 - -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[6] 0 - -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[6] 0 - -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[6] 0 - -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[6] 0 - pvf_reg_constant u_axi_ddr_top/rd0_ddr_sart_addr0[2] 0 pvf_reg_constant u_axi_ddr_top/rd0_ddr_sart_addr0[3] 0 @@ -11144,6 +11148,8 @@ pvf_reg_constant u_axi_ddr_top/rd0_ddr_sart_addr1[8] 0 pvf_reg_constant u_axi_ddr_top/rd0_ddr_sart_addr1[9] 0 +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/update_start 0 + pvf_reg_constant u_axi_ddr_top/rd0_ddr_sart_addr2[2] 0 pvf_reg_constant u_axi_ddr_top/rd0_ddr_sart_addr2[3] 0 @@ -11160,48 +11166,12 @@ pvf_reg_constant u_axi_ddr_top/rd0_ddr_sart_addr2[8] 0 pvf_reg_constant u_axi_ddr_top/rd0_ddr_sart_addr2[9] 0 -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/update_start 0 - pvf_reg_constant u_axi_ddr_top/s_axi_araddr[2] 0 pvf_reg_constant u_axi_ddr_top/s_axi_araddr[3] 0 pvf_reg_constant u_axi_ddr_top/s_axi_araddr[4] 0 -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/upcal/upcal_state_reg[0] 1 - -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[5] 0 - -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt0[4] 0 - -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[5] 0 - -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/timing_cnt1[4] 0 - -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt0[4] 0 - -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[5] 0 - -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt0[4] 0 - -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[5] 0 - -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt0[4] 0 - -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[5] 0 - -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt0[4] 0 - -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[5] 0 - -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt0[4] 0 - -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[5] 0 - -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt0[4] 0 - -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[5] 0 - pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt0[4] 0 pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[5] 0 @@ -11242,6 +11212,40 @@ pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcd pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[5] 0 +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/upcal/upcal_state_reg[0] 1 + +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[5] 0 + +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt0[4] 0 + +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[5] 0 + +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/timing_cnt1[4] 0 + +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt0[4] 0 + +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[5] 0 + +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt0[4] 0 + +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[5] 0 + +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt0[4] 0 + +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[5] 0 + +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt0[4] 0 + +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[5] 0 + +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt0[4] 0 + +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[5] 0 + +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt0[4] 0 + +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[5] 0 + pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/upcal/rdata_rem_vld 0 pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/upcal/pre_cnt[0] 0 @@ -11330,10 +11334,6 @@ pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_gate_update_c pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_gate_update_ctrl/drift_dqs_group[3].ddrphy_drift_ctrl/dqs_drift_last_samp[1] 0 -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_gate_update_ctrl/drift_dqs_group[0].ddrphy_drift_ctrl/dqs_drift_last[0] 0 - -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_gate_update_ctrl/drift_dqs_group[0].ddrphy_drift_ctrl/dqs_drift_last[1] 0 - pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_gate_update_ctrl/drift_dqs_group[0].ddrphy_drift_ctrl/dqs_drift_last_cnt[1] 0 pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_gate_update_ctrl/drift_dqs_group[0].ddrphy_drift_ctrl/dqs_drift_last_cnt[2] 0 @@ -11352,6 +11352,10 @@ pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_gate_update_c pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_gate_update_ctrl/drift_dqs_group[0].ddrphy_drift_ctrl/dqs_drift_last_cnt[9] 0 +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_gate_update_ctrl/drift_dqs_group[0].ddrphy_drift_ctrl/dqs_drift_last[0] 0 + +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_gate_update_ctrl/drift_dqs_group[0].ddrphy_drift_ctrl/dqs_drift_last[1] 0 + pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_gate_update_ctrl/drift_dqs_group[1].ddrphy_drift_ctrl/dqs_drift_last[0] 0 pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_gate_update_ctrl/drift_dqs_group[1].ddrphy_drift_ctrl/dqs_drift_last[1] 0 @@ -11418,12 +11422,12 @@ pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_gate_update_c pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_gate_update_ctrl/drift_dqs_group[3].ddrphy_drift_ctrl/dqs_drift_last[1] 0 -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_gate_update_ctrl/drift_dqs_group[0].ddrphy_drift_ctrl/ddrphy_update_comp_val[0] 0 - pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_gate_update_ctrl/drift_dqs_group[0].ddrphy_drift_ctrl/dqs_drift_last_cnt[0] 0 pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_gate_update_ctrl/drift_dqs_group[0].ddrphy_drift_ctrl/dqs_drift_last_done 0 +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_gate_update_ctrl/drift_dqs_group[0].ddrphy_drift_ctrl/ddrphy_update_comp_val[0] 0 + pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_gate_update_ctrl/drift_dqs_group[1].ddrphy_drift_ctrl/ddrphy_update_comp_val[0] 0 pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_gate_update_ctrl/drift_dqs_group[1].ddrphy_drift_ctrl/dqs_drift_last_cnt[0] 0 @@ -11494,6 +11498,10 @@ pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_d pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/upcal/upcal_state_reg[4] 0 +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt0[3] 0 + +pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt0[3] 0 + pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[5] 0 pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[5] 0 @@ -11520,8 +11528,4 @@ pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcd pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt0[3] 0 -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt0[3] 0 - -pvf_reg_constant u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt0[3] 0 - pvf_reg_merging -survived u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt0[2] -deleted u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/timing_cnt1[2] diff --git a/project/synthesize/multimedia_video_processor.snr b/project/synthesize/multimedia_video_processor.snr index 5bbb8f4..8b6dce7 100644 --- a/project/synthesize/multimedia_video_processor.snr +++ b/project/synthesize/multimedia_video_processor.snr @@ -1,4 +1,4 @@ -Generated by Fabric Compiler ( version 2022.2-SP1-Lite ) at Sat Nov 11 17:52:55 2023 +Generated by Fabric Compiler ( version 2022.2-SP1-Lite ) at Wed Nov 15 19:34:09 2023 Cell Usage: @@ -12,7 +12,7 @@ GTP_DFF_CE 2812 uses GTP_DFF_E 779 uses GTP_DFF_P 150 uses GTP_DFF_PE 227 uses -GTP_DFF_R 1515 uses +GTP_DFF_R 1513 uses GTP_DFF_RE 1347 uses GTP_DFF_S 109 uses GTP_DFF_SE 57 uses @@ -26,15 +26,15 @@ GTP_IOCLKDELAY 1 use GTP_IOCLKDIV 1 use GTP_IODELAY 32 uses GTP_ISERDES 37 uses -GTP_LUT1 146 uses -GTP_LUT2 1431 uses -GTP_LUT3 2070 uses -GTP_LUT4 1796 uses -GTP_LUT5 2751 uses -GTP_LUT5CARRY 4656 uses -GTP_LUT5M 995 uses -GTP_MUX2LUT6 114 uses -GTP_MUX2LUT7 32 uses +GTP_LUT1 145 uses +GTP_LUT2 1448 uses +GTP_LUT3 2040 uses +GTP_LUT4 1794 uses +GTP_LUT5 2782 uses +GTP_LUT5CARRY 4653 uses +GTP_LUT5M 989 uses +GTP_MUX2LUT6 104 uses +GTP_MUX2LUT7 31 uses GTP_OSERDES 71 uses GTP_PLL_E3 4 uses GTP_RAM16X1DP 84 uses @@ -49,10 +49,10 @@ GTP_OUTBUFT 42 uses GTP_OUTBUFTCO 1 use Mapping Summary: -Total LUTs: 13933 of 42800 (32.55%) +Total LUTs: 13939 of 42800 (32.57%) LUTs as dram: 88 of 17000 (0.52%) - LUTs as logic: 13845 -Total Registers: 13710 of 64200 (21.36%) + LUTs as logic: 13851 +Total Registers: 13708 of 64200 (21.35%) Total Latches: 0 DRM18K: @@ -91,7 +91,7 @@ Flip-Flop Distribution: ------------------------------------------------------------------------ NO NO NO 2434 NO NO YES 4430 - NO YES NO 1624 + NO YES NO 1622 YES NO NO 779 YES NO YES 3039 YES YES NO 1404 @@ -114,11 +114,11 @@ Device Utilization Summary Of Each Module: +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Module Inst Name | LUT | FF | Distributed RAM | APM | DRM | ADC | CGRA | CRYSTAL | DLL | DQSL | EFUSECODE | FLSIF | HMEMC | HSST | IO | IOCKDIV | IOCKDLY | IOCKGATE | IPAL | LUT CARRY | LUT6 MUX | LUT7 MUX | LUT8 MUX | OSC | PCIE | PLL | RCKB | RESCAL | SCANCHAIN | START | UDID | USCM +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -| multimedia_video_processor | 13933 | 13710 | 88 | 20.5 | 98.5 | 0 | 0 | 0 | 2 | 8 | 0 | 0 | 0 | 0 | 180 | 1 | 1 | 3 | 0 | 4656 | 114 | 32 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 1 | 0 | 5 +| multimedia_video_processor | 13939 | 13708 | 88 | 20.5 | 98.5 | 0 | 0 | 0 | 2 | 8 | 0 | 0 | 0 | 0 | 180 | 1 | 1 | 3 | 0 | 4653 | 104 | 31 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 1 | 0 | 5 | + U_HDMI_PLL | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 -| + adjust_color_wrapper_inst | 1127 | 1096 | 0 | 1.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 463 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + adjust_color_inst | 1127 | 1018 | 0 | 1.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 463 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + convert_hsv2rgb_inst | 69 | 81 | 0 | 1.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 26 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + adjust_color_wrapper_inst | 1128 | 1096 | 0 | 1.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 463 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + adjust_color_inst | 1128 | 1018 | 0 | 1.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 463 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + convert_hsv2rgb_inst | 70 | 81 | 0 | 1.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 26 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + convert_rgb2hsv_inst | 1006 | 883 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 407 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + divider_inst_h | 415 | 268 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 164 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + g_sqrt_stepx[1].u_divider_step | 36 | 23 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 14 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 @@ -179,8 +179,8 @@ Device Utilization Summary Of Each Module: | + U_ipml_fifo_ctrl | 61 | 26 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 36 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + U_ipml_sdpram | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + vector_to_matrix_inst | 0 | 145 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + image_filiter_inst2 | 946 | 856 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 504 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + hybrid_filter_inst | 727 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 399 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + image_filiter_inst2 | 945 | 856 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 504 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + hybrid_filter_inst | 726 | 621 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 399 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + gaussian_conv_b | 56 | 83 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 53 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + gaussian_conv_g | 65 | 98 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + gaussian_conv_r | 56 | 83 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 53 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 @@ -206,35 +206,35 @@ Device Utilization Summary Of Each Module: | + U_ipml_fifo_ctrl | 61 | 26 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 36 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + U_ipml_sdpram | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + vector_to_matrix_inst | 0 | 145 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + ms72xx_ctl | 338 | 326 | 0 | 0 | 1.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 48 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + iic_dri_rx | 82 | 61 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + iic_dri_tx | 66 | 56 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + ms72xx_ctl | 337 | 326 | 0 | 0 | 1.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 48 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + iic_dri_rx | 83 | 61 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + iic_dri_tx | 65 | 56 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + ms7200_ctl | 102 | 144 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + ms7210_ctl | 88 | 62 | 0 | 0 | 0.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 27 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + param_manager_inst | 666 | 354 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 193 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + ms7210_ctl | 87 | 62 | 0 | 0 | 0.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 27 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + param_manager_inst | 672 | 354 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 193 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + key_debounce_key_left | 16 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + key_debounce_key_restore | 13 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + key_debounce_key_right | 14 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + param_filiter1_mode | 67 | 34 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + param_filiter1_mode | 69 | 34 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + key_debounce_inst1 | 14 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + key_debounce_inst2 | 14 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + param_filiter2_mode | 8 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + param_modify_H | 51 | 22 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 19 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + param_modify_S | 28 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + param_modify_V | 28 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + param_offsetX | 56 | 25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 22 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + param_modify_H | 52 | 22 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 19 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + param_modify_S | 30 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + param_modify_V | 29 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + param_offsetX | 54 | 25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 22 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + param_offsetY | 33 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + param_osd_char_height | 57 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + param_osd_char_width | 32 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + param_osd_char_height | 55 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + param_osd_char_width | 33 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + param_osd_startX | 55 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + param_osd_startY | 32 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + param_rotate | 47 | 21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + param_rotate_A | 33 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + param_rotate | 49 | 21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + param_rotate_A | 34 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + param_zoom | 33 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + u_axi_ddr_top | 5787 | 6000 | 88 | 0 | 30.5 | 0 | 0 | 0 | 1 | 8 | 0 | 0 | 0 | 0 | 70 | 1 | 0 | 3 | 0 | 1258 | 61 | 16 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2 -| + I_ipsxb_ddr_top | 4258 | 4123 | 88 | 0 | 0 | 0 | 0 | 0 | 1 | 8 | 0 | 0 | 0 | 0 | 70 | 1 | 0 | 3 | 0 | 637 | 29 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2 +| + u_axi_ddr_top | 5796 | 6000 | 88 | 0 | 30.5 | 0 | 0 | 0 | 1 | 8 | 0 | 0 | 0 | 0 | 70 | 1 | 0 | 3 | 0 | 1258 | 61 | 16 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2 +| + I_ipsxb_ddr_top | 4267 | 4123 | 88 | 0 | 0 | 0 | 0 | 0 | 1 | 8 | 0 | 0 | 0 | 0 | 70 | 1 | 0 | 3 | 0 | 637 | 29 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2 | + u_ddrp_rstn_sync | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + u_ddrphy_top | 2602 | 2360 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 8 | 0 | 0 | 0 | 0 | 70 | 0 | 0 | 0 | 0 | 482 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + u_ddrphy_top | 2614 | 2360 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 8 | 0 | 0 | 0 | 0 | 70 | 0 | 0 | 0 | 0 | 482 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + ddrphy_calib_top | 320 | 236 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 70 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + calib_mux | 23 | 23 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + ddrphy_init | 136 | 92 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 46 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 @@ -244,41 +244,41 @@ Device Utilization Summary Of Each Module: | + upcal | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + ddrphy_dfi | 567 | 613 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + ddrphy_dll_update_ctrl | 11 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + ddrphy_info | 100 | 60 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + ddrphy_reset_ctrl | 75 | 60 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + ddrphy_pll_lock_debounce | 44 | 22 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + ddrphy_info | 103 | 60 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + ddrphy_reset_ctrl | 84 | 60 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + ddrphy_pll_lock_debounce | 45 | 22 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_ddrphy_rstn_sync | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_dll_rst_sync | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + ddrphy_slice_top | 1523 | 1371 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 70 | 0 | 0 | 0 | 0 | 372 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + i_dqs_group[0].u_ddrphy_data_slice | 489 | 308 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 11 | 0 | 0 | 0 | 0 | 110 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + i_dqs_group[0].u_ddrphy_data_slice | 490 | 308 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 11 | 0 | 0 | 0 | 0 | 110 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + data_slice_dqs_gate_cal | 159 | 69 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + dqs_gate_coarse_cal | 109 | 34 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + gatecal | 50 | 35 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + data_slice_wrlvl | 108 | 76 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 22 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + data_slice_wrlvl | 106 | 76 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 22 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + dqs_rddata_align | 45 | 74 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + dqsi_rdel_cal | 168 | 84 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 77 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + dqsi_rdel_cal | 171 | 84 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 77 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + wdata_path_adj | 9 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + i_dqs_group[1].u_ddrphy_data_slice | 327 | 262 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 11 | 0 | 0 | 0 | 0 | 85 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + i_dqs_group[1].u_ddrphy_data_slice | 331 | 262 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 11 | 0 | 0 | 0 | 0 | 85 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + data_slice_dqs_gate_cal | 79 | 61 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + dqs_gate_coarse_cal | 30 | 26 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + gatecal | 49 | 35 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + data_slice_wrlvl | 102 | 68 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 22 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + dqs_rddata_align | 44 | 74 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + data_slice_wrlvl | 105 | 68 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 22 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + dqs_rddata_align | 45 | 74 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + dqsi_rdel_cal | 97 | 59 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 52 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + wdata_path_adj | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + i_dqs_group[2].u_ddrphy_data_slice | 333 | 262 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 11 | 0 | 0 | 0 | 0 | 85 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + data_slice_dqs_gate_cal | 77 | 61 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + i_dqs_group[2].u_ddrphy_data_slice | 329 | 262 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 11 | 0 | 0 | 0 | 0 | 85 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + data_slice_dqs_gate_cal | 78 | 61 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + dqs_gate_coarse_cal | 30 | 26 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + gatecal | 47 | 35 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + data_slice_wrlvl | 107 | 68 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 22 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + gatecal | 48 | 35 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + data_slice_wrlvl | 106 | 68 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 22 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + dqs_rddata_align | 44 | 74 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + dqsi_rdel_cal | 100 | 59 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 52 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + dqsi_rdel_cal | 96 | 59 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 52 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + wdata_path_adj | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + i_dqs_group[3].u_ddrphy_data_slice | 336 | 262 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 11 | 0 | 0 | 0 | 0 | 85 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + i_dqs_group[3].u_ddrphy_data_slice | 335 | 262 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 11 | 0 | 0 | 0 | 0 | 85 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + data_slice_dqs_gate_cal | 78 | 61 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + dqs_gate_coarse_cal | 30 | 26 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + gatecal | 48 | 35 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + data_slice_wrlvl | 103 | 68 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 22 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + data_slice_wrlvl | 102 | 68 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 22 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + dqs_rddata_align | 44 | 74 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + dqsi_rdel_cal | 106 | 59 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 52 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + wdata_path_adj | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 @@ -286,15 +286,15 @@ Device Utilization Summary Of Each Module: | + u_logic_rstn_sync | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_slice_rddata_align | 5 | 260 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + ddrphy_training_ctrl | 6 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + u_ipsxb_ddrc_top | 1654 | 1761 | 88 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 155 | 21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + u_ipsxb_ddrc_top | 1651 | 1761 | 88 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 155 | 21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + mcdq_calib_delay | 0 | 46 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + mcdq_cfg_apb | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + mcdq_dcd_top | 164 | 158 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 19 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + mcdq_dcd_top | 163 | 158 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 19 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + mcdq_dcd_bm | 113 | 80 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + mcdq_dcd_rowaddr | 17 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + mcdq_dcd_sm | 51 | 78 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + mcdq_dcp_top | 854 | 626 | 82 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 66 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + mcdq_dcp_back_ctrl | 545 | 406 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + mcdq_dcd_rowaddr | 12 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + mcdq_dcd_sm | 50 | 78 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + mcdq_dcp_top | 852 | 626 | 82 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 66 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + mcdq_dcp_back_ctrl | 543 | 406 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + PRE_PASS_LOOP[0].timing_pre_pass | 21 | 13 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + PRE_PASS_LOOP[1].timing_pre_pass | 21 | 13 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + PRE_PASS_LOOP[2].timing_pre_pass | 21 | 13 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 @@ -311,7 +311,7 @@ Device Utilization Summary Of Each Module: | + TRC_LOOP[5].trc_timing | 4 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + TRC_LOOP[6].trc_timing | 4 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + TRC_LOOP[7].trc_timing | 4 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + TRDA2ACT_LOOP[0].trda2act_timing | 8 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + TRDA2ACT_LOOP[0].trda2act_timing | 7 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + TRDA2ACT_LOOP[1].trda2act_timing | 7 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + TRDA2ACT_LOOP[2].trda2act_timing | 7 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + TRDA2ACT_LOOP[3].trda2act_timing | 7 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 @@ -327,15 +327,15 @@ Device Utilization Summary Of Each Module: | + TWRA2ACT_LOOP[5].twra2act_timing | 9 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + TWRA2ACT_LOOP[6].twra2act_timing | 9 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + TWRA2ACT_LOOP[7].twra2act_timing | 9 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + mcdq_timing_rd_pass | 11 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + mcdq_timing_rd_pass | 10 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + tfaw_timing | 24 | 18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + TFAW_LOOP[0].mcdq_tfaw | 7 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + TFAW_LOOP[1].mcdq_tfaw | 7 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + TFAW_LOOP[2].mcdq_tfaw | 7 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + timing_act_pass | 27 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + timing_prea_pass | 15 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + timing_prea_pass | 16 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + timing_ref_pass | 19 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + timing_wr_pass | 9 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + timing_wr_pass | 8 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + mcdq_dcp_buf | 244 | 159 | 82 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 62 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + A_ipsxb_distributed_fifo | 83 | 15 | 41 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 28 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_ipsxb_distributed_fifo_distributed_fifo_v1_0 | 83 | 15 | 41 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 28 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 @@ -354,8 +354,8 @@ Device Utilization Summary Of Each Module: | + ipsxb_distributed_sdpram_distributed_fifo_v1_0 | 4 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_ipsxb_distributed_fifo_ctr | 31 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + mcdq_ui_axi | 233 | 345 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 39 | 15 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + mcdq_reg_fifo2 | 95 | 71 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + u_user_cmd_fifo | 25 | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + mcdq_reg_fifo2 | 94 | 71 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + u_user_cmd_fifo | 26 | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + mcdq_wdatapath | 288 | 475 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + ipsxb_distributed_fifo | 27 | 14 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_ipsxb_distributed_fifo_distributed_fifo_v1_0 | 27 | 14 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 @@ -416,7 +416,7 @@ Device Utilization Summary Of Each Module: | + U_ipml_sdpram | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_axi_rst | 2 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_clk50m_rst | 1 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + u_ddr_addr_ctr | 280 | 434 | 0 | 0 | 0.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 140 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + u_ddr_addr_ctr | 277 | 432 | 0 | 0 | 0.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 138 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_rd0_addr_ctr | 38 | 43 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 26 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_rd1_addr_ctr | 77 | 95 | 0 | 0 | 0.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 36 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_rd1_ddr_addr_fifo1 | 42 | 20 | 0 | 0 | 0.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 23 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 @@ -434,13 +434,13 @@ Device Utilization Summary Of Each Module: | + u_hdm_in_rst | 2 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_hdmi_in_top | 9 | 79 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_hdmi_rst | 2 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + u_ov5640 | 453 | 504 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 185 | 4 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 +| + u_ov5640 | 455 | 504 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 185 | 3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | + cmos1_8_16bit | 3 | 47 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + cmos2_8_16bit | 3 | 47 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + coms1_reg_config | 61 | 36 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 23 | 2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | + u1 | 29 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + coms2_reg_config | 61 | 36 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 23 | 2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 -| + u1 | 29 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + coms2_reg_config | 63 | 36 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 23 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 +| + u1 | 31 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + power_on_delay_inst | 41 | 37 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_mix_image | 284 | 261 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 106 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_mix_fifo1 | 86 | 90 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 @@ -471,11 +471,11 @@ Device Utilization Summary Of Each Module: | + U_ipml_sdpram | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_sync_vg | 75 | 90 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 37 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_sys_pll | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 -| + u_zoom_hdmi_fifo | 182 | 139 | 0 | 0 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + U_ipml_fifo_zoom_hdmi_fifo | 182 | 139 | 0 | 0 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + U_ipml_fifo_ctrl | 165 | 138 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + u_zoom_hdmi_fifo | 172 | 139 | 0 | 0 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + U_ipml_fifo_zoom_hdmi_fifo | 172 | 139 | 0 | 0 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + U_ipml_fifo_ctrl | 155 | 138 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + U_ipml_sdpram | 17 | 1 | 0 | 0 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + u_zoom_image | 430 | 509 | 0 | 13 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 230 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + u_zoom_image | 430 | 509 | 0 | 13 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 230 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + mult_fra0 | 0 | 0 | 0 | 0.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + mult_fra0_0 | 0 | 0 | 0 | 0.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + mult_fra1 | 0 | 0 | 0 | 0.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 @@ -511,41 +511,41 @@ Device Utilization Summary Of Each Module: | + zoom_ram3_0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + U_ipml_sdpram_zoom_ram | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_zoom_rst | 1 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + udp_osd_inst | 2209 | 1831 | 0 | 0 | 4 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 11 | 0 | 1 | 0 | 0 | 779 | 39 | 14 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 +| + udp_osd_inst | 2212 | 1831 | 0 | 0 | 4 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 11 | 0 | 1 | 0 | 0 | 779 | 39 | 14 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | + char_buf_writer_inst | 93 | 56 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 51 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + char_osd_inst | 262 | 215 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 122 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + char_buf_reader_inst | 176 | 129 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 76 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + char_pic_rom_inst | 41 | 47 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 30 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + char_buf_reader_inst | 177 | 129 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 76 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + char_pic_rom_inst | 40 | 47 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 30 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + ascii_char_rom_inst | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + U_ipml_rom_ascii_char_rom | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + U_ipml_spram_ascii_char_rom | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + pixels_shifter_inst | 45 | 39 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + char_ram | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + U_ipml_sdpram_async_ram2048x8_2clk | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + eth_udp_inst | 1818 | 1541 | 0 | 0 | 2 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 11 | 0 | 1 | 0 | 0 | 588 | 39 | 14 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 +| + eth_udp_inst | 1821 | 1541 | 0 | 0 | 2 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 11 | 0 | 1 | 0 | 0 | 588 | 39 | 14 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | + icmp_async_fifo_2048x8b | 97 | 98 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 36 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + U_ipml_fifo_async_fifo_2048x8 | 97 | 98 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 36 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + U_ipml_fifo_ctrl | 97 | 98 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 36 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + U_ipml_sdpram | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + u_arp | 423 | 424 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 16 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + u_arp_rx | 215 | 278 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + u_arp | 422 | 424 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 16 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + u_arp_rx | 214 | 278 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_arp_tx | 154 | 114 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 14 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_crc32_d8 | 54 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_eth_ctrl | 12 | 22 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_gmii_to_rgmii | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 11 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 -| + u_icmp | 927 | 628 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 426 | 23 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + u_icmp | 929 | 628 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 426 | 23 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_crc32_d8 | 55 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + u_icmp_rx | 289 | 284 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 128 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + u_icmp_tx | 583 | 312 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 298 | 22 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + u_udp | 161 | 185 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + u_udp_rx | 161 | 185 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + u_icmp_tx | 585 | 312 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 298 | 22 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + u_udp | 163 | 185 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + u_udp_rx | 163 | 185 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + udp_receive_buffer_inst | 192 | 175 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 71 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + udp_rx_done_cdc | 3 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + udp_rx_fifo | 107 | 98 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 35 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + U_ipml_fifo_async_fifo_2048x8 | 107 | 98 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 35 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + U_ipml_fifo_ctrl | 107 | 98 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 35 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | + U_ipml_sdpram | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 -| + udp_wr_mem_inst | 105 | 190 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +| + udp_wr_mem_inst | 106 | 190 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 31 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -557,8 +557,8 @@ Timing analysis mode : single corner Clock Period Waveform Type Loads Loads Sources -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- clk 20.000 {0 10} Declared 0 7 {clk} - clk_50m 20.000 {0 10} Generated (clk) 2826 0 {u_sys_pll/u_pll_e3/CLKOUT0} - clk_200m 5.000 {0 2.5} Generated (clk) 919 5 {u_sys_pll/u_pll_e3/CLKOUT1} + clk_50m 20.000 {0 10} Generated (clk) 2824 0 {u_sys_pll/u_pll_e3/CLKOUT0} + clk_200m 5.000 {0 2.5} Generated (clk) 75 5 {u_sys_pll/u_pll_e3/CLKOUT1} ddrphy_clkin 10.000 {0 5} Generated (clk_200m) 5817 0 {u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT} ioclk0 2.500 {0 1.25} Generated (clk_200m) 11 0 {u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT} ioclk1 2.500 {0 1.25} Generated (clk_200m) 27 1 {u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT} @@ -568,7 +568,7 @@ Timing analysis mode : single corner clk_25m 40.000 {0 20} Generated (clk) 26 2 {u_sys_pll/u_pll_e3/CLKOUT3} clk_20k 50000.000 {0 25000} Generated (clk_25m) 50 0 {u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/CLKOUT u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/CLKOUT} clk_10m 100.000 {0 50} Generated (clk) 256 0 {u_sys_pll/u_pll_e3/CLKOUT4} - clk_1080p60Hz 6.737 {0 3.368} Generated (clk) 0 0 {U_HDMI_PLL/u_pll_e3/CLKOUT0} + clk_1080p60Hz 6.737 {0 3.368} Generated (clk) 844 0 {U_HDMI_PLL/u_pll_e3/CLKOUT0} clk_720p60Hz 13.474 {0 6.736} Generated (clk) 1757 1 {U_HDMI_PLL/u_pll_e3/CLKOUT1} cmos1_pclk 11.900 {0 5.95} Declared 126 0 {cmos1_pclk} cmos2_pclk 11.900 {0 5.95} Declared 126 0 {cmos2_pclk} @@ -607,13 +607,14 @@ Timing analysis mode : single corner cmos2_pclk 84.034 MHz 202.224 MHz 11.900 4.945 6.955 hdmi_in_clk 150.015 MHz 210.571 MHz 6.666 4.749 1.917 eth_rxc 125.000 MHz 146.306 MHz 8.000 6.835 1.165 - clk_50m 50.000 MHz 127.389 MHz 20.000 7.850 12.150 - clk_200m 200.000 MHz 205.339 MHz 5.000 4.870 0.130 + clk_50m 50.000 MHz 127.372 MHz 20.000 7.851 12.149 + clk_200m 200.000 MHz 254.065 MHz 5.000 3.936 1.064 clk_25m 25.000 MHz 283.366 MHz 40.000 3.529 36.471 clk_10m 10.000 MHz 152.742 MHz 100.000 6.547 93.453 - clk_720p60Hz 74.219 MHz 126.448 MHz 13.474 7.908 5.565 + clk_1080p60Hz 148.438 MHz 196.323 MHz 6.737 5.094 1.643 + clk_720p60Hz 74.219 MHz 127.155 MHz 13.474 7.864 5.609 clk_20k 0.020 MHz 184.672 MHz 50000.000 5.415 49994.585 - ddrphy_clkin 100.000 MHz 128.403 MHz 10.000 7.788 2.212 + ddrphy_clkin 100.000 MHz 130.993 MHz 10.000 7.634 2.366 ioclk0 400.000 MHz 708.215 MHz 2.500 1.412 1.088 ioclk1 400.000 MHz 708.215 MHz 2.500 1.412 1.088 ==================================================================================================== @@ -629,13 +630,14 @@ Setup Summary(Slow Corner): cmos2_pclk cmos2_pclk 6.955 0.000 0 189 hdmi_in_clk hdmi_in_clk 1.917 0.000 0 217 eth_rxc eth_rxc 1.165 0.000 0 3783 - clk_50m clk_50m 12.150 0.000 0 5747 - clk_200m clk_200m 0.130 0.000 0 2828 + clk_50m clk_50m 12.149 0.000 0 5743 + clk_200m clk_200m 1.064 0.000 0 108 clk_25m clk_25m 36.471 0.000 0 30 clk_10m clk_10m 93.453 0.000 0 599 - clk_720p60Hz clk_720p60Hz 5.565 0.000 0 3149 + clk_1080p60Hz clk_1080p60Hz 1.643 0.000 0 2720 + clk_720p60Hz clk_720p60Hz 5.609 0.000 0 3149 clk_20k clk_20k 49994.585 0.000 0 122 - ddrphy_clkin ddrphy_clkin 2.212 0.000 0 9577 + ddrphy_clkin ddrphy_clkin 2.366 0.000 0 9577 ioclk0 ioclk0 1.088 0.000 0 24 ioclk1 ioclk1 1.088 0.000 0 72 ==================================================================================================== @@ -649,10 +651,11 @@ Hold Summary(Slow Corner): cmos2_pclk cmos2_pclk -1.352 -12.168 9 189 hdmi_in_clk hdmi_in_clk 0.540 0.000 0 217 eth_rxc eth_rxc 0.540 0.000 0 3783 - clk_50m clk_50m 0.650 0.000 0 5747 - clk_200m clk_200m 0.656 0.000 0 2828 + clk_50m clk_50m 0.649 0.000 0 5743 + clk_200m clk_200m 0.740 0.000 0 108 clk_25m clk_25m 0.881 0.000 0 30 clk_10m clk_10m 0.740 0.000 0 599 + clk_1080p60Hz clk_1080p60Hz 0.656 0.000 0 2720 clk_720p60Hz clk_720p60Hz 0.650 0.000 0 3149 clk_20k clk_20k 0.829 0.000 0 122 ddrphy_clkin ddrphy_clkin 0.453 0.000 0 9577 @@ -666,8 +669,9 @@ Recovery Summary(Slow Corner): Launch Clock Capture Clock WNS(ns) TNS(ns) Endpoints Endpoints ---------------------------------------------------------------------------------------------------- clk_50m clk_50m 16.577 0.000 0 278 - clk_200m clk_200m 1.564 0.000 0 194 + clk_200m clk_200m 1.564 0.000 0 69 clk_10m clk_10m 98.374 0.000 0 1 + clk_1080p60Hz clk_1080p60Hz 4.552 0.000 0 125 clk_720p60Hz clk_720p60Hz 9.504 0.000 0 736 ddrphy_clkin ddrphy_clkin 6.273 0.000 0 2809 ==================================================================================================== @@ -677,9 +681,10 @@ Removal Summary(Slow Corner): THS Failing THS Total Launch Clock Capture Clock WHS(ns) THS(ns) Endpoints Endpoints ---------------------------------------------------------------------------------------------------- - clk_50m clk_50m 1.337 0.000 0 278 - clk_200m clk_200m -1.158 -2.316 2 194 + clk_50m clk_50m 1.336 0.000 0 278 + clk_200m clk_200m -1.158 -2.316 2 69 clk_10m clk_10m 1.185 0.000 0 1 + clk_1080p60Hz clk_1080p60Hz 1.545 0.000 0 125 clk_720p60Hz clk_720p60Hz 1.608 0.000 0 736 ddrphy_clkin ddrphy_clkin 1.092 0.000 0 2809 ==================================================================================================== @@ -693,10 +698,11 @@ Minimum Pulse Width Summary(Slow Corner): cmos2_pclk 5.052 0.000 0 126 hdmi_in_clk 2.435 0.000 0 173 eth_rxc 2.483 0.000 0 1988 - clk_50m 8.862 0.000 0 2826 - clk_200m 1.362 0.000 0 919 + clk_50m 8.862 0.000 0 2824 + clk_200m 1.880 0.000 0 75 clk_25m 19.380 0.000 0 26 clk_10m 49.102 0.000 0 256 + clk_1080p60Hz 2.230 0.000 0 844 clk_720p60Hz 5.598 0.000 0 1757 clk_20k 24999.102 0.000 0 50 ddrphy_clkin 3.100 0.000 0 5817 @@ -773,31 +779,31 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=3) 0.605 6.295 u_ov5640/u_mix_image/wr1_en u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_1/I0 (GTP_LUT5CARRY) td 0.201 6.496 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_1/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.496 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16508 + net (fanout=1) 0.000 6.496 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16412 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_2/CIN (GTP_LUT5CARRY) td 0.030 6.526 r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_2/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.526 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16509 + net (fanout=1) 0.000 6.526 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16413 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_3/CIN (GTP_LUT5CARRY) td 0.030 6.556 r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_3/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.556 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16510 + net (fanout=1) 0.000 6.556 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16414 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_4/CIN (GTP_LUT5CARRY) td 0.030 6.586 r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_4/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.586 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16511 + net (fanout=1) 0.000 6.586 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16415 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_5/CIN (GTP_LUT5CARRY) td 0.030 6.616 r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_5/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.616 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16512 + net (fanout=1) 0.000 6.616 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16416 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_6/CIN (GTP_LUT5CARRY) td 0.030 6.646 r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_6/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.646 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16513 + net (fanout=1) 0.000 6.646 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16417 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_7/CIN (GTP_LUT5CARRY) td 0.030 6.676 r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_7/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.676 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16514 + net (fanout=1) 0.000 6.676 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16418 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_8/CIN (GTP_LUT5CARRY) td 0.030 6.706 r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_8/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.706 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16515 + net (fanout=1) 0.000 6.706 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16419 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_9/CIN (GTP_LUT5CARRY) td 0.030 6.736 r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_9/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.736 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16516 + net (fanout=1) 0.000 6.736 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16420 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_10/CIN (GTP_LUT5CARRY) td 0.236 6.972 r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_10/Z (GTP_LUT5CARRY) net (fanout=4) 0.641 7.613 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2 [9] @@ -866,31 +872,31 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=3) 0.605 6.295 u_ov5640/u_mix_image/wr1_en u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_1/I0 (GTP_LUT5CARRY) td 0.201 6.496 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_1/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.496 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16508 + net (fanout=1) 0.000 6.496 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16412 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_2/CIN (GTP_LUT5CARRY) td 0.030 6.526 r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_2/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.526 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16509 + net (fanout=1) 0.000 6.526 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16413 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_3/CIN (GTP_LUT5CARRY) td 0.030 6.556 r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_3/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.556 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16510 + net (fanout=1) 0.000 6.556 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16414 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_4/CIN (GTP_LUT5CARRY) td 0.030 6.586 r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_4/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.586 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16511 + net (fanout=1) 0.000 6.586 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16415 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_5/CIN (GTP_LUT5CARRY) td 0.030 6.616 r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_5/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.616 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16512 + net (fanout=1) 0.000 6.616 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16416 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_6/CIN (GTP_LUT5CARRY) td 0.030 6.646 r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_6/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.646 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16513 + net (fanout=1) 0.000 6.646 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16417 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_7/CIN (GTP_LUT5CARRY) td 0.030 6.676 r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_7/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.676 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16514 + net (fanout=1) 0.000 6.676 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16418 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_8/CIN (GTP_LUT5CARRY) td 0.030 6.706 r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_8/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.706 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16515 + net (fanout=1) 0.000 6.706 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16419 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_9/CIN (GTP_LUT5CARRY) td 0.030 6.736 r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_9/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.736 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16516 + net (fanout=1) 0.000 6.736 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16420 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_10/CIN (GTP_LUT5CARRY) td 0.236 6.972 r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_10/Z (GTP_LUT5CARRY) net (fanout=4) 0.641 7.613 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2 [9] @@ -953,28 +959,28 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=3) 0.605 6.295 u_ov5640/u_mix_image/wr1_en u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_1/I0 (GTP_LUT5CARRY) td 0.201 6.496 f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_1/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.496 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16508 + net (fanout=1) 0.000 6.496 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16412 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_2/CIN (GTP_LUT5CARRY) td 0.030 6.526 r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_2/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.526 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16509 + net (fanout=1) 0.000 6.526 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16413 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_3/CIN (GTP_LUT5CARRY) td 0.030 6.556 r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_3/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.556 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16510 + net (fanout=1) 0.000 6.556 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16414 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_4/CIN (GTP_LUT5CARRY) td 0.030 6.586 r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_4/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.586 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16511 + net (fanout=1) 0.000 6.586 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16415 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_5/CIN (GTP_LUT5CARRY) td 0.030 6.616 r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_5/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.616 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16512 + net (fanout=1) 0.000 6.616 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16416 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_6/CIN (GTP_LUT5CARRY) td 0.030 6.646 r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_6/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.646 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16513 + net (fanout=1) 0.000 6.646 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16417 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_7/CIN (GTP_LUT5CARRY) td 0.030 6.676 r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_7/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.676 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16514 + net (fanout=1) 0.000 6.676 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16418 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_8/CIN (GTP_LUT5CARRY) td 0.030 6.706 r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_8/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.706 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16515 + net (fanout=1) 0.000 6.706 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16419 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_9/CIN (GTP_LUT5CARRY) td 0.236 6.942 r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_9/Z (GTP_LUT5CARRY) net (fanout=4) 0.641 7.583 u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2 [8] @@ -1184,31 +1190,31 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=3) 0.605 6.295 u_ov5640/u_mix_image/wr2_en u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_1/I0 (GTP_LUT5CARRY) td 0.201 6.496 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_1/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.496 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16532 + net (fanout=1) 0.000 6.496 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16442 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_2/CIN (GTP_LUT5CARRY) td 0.030 6.526 r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_2/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.526 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16533 + net (fanout=1) 0.000 6.526 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16443 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_3/CIN (GTP_LUT5CARRY) td 0.030 6.556 r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_3/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.556 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16534 + net (fanout=1) 0.000 6.556 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16444 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_4/CIN (GTP_LUT5CARRY) td 0.030 6.586 r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_4/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.586 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16535 + net (fanout=1) 0.000 6.586 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16445 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_5/CIN (GTP_LUT5CARRY) td 0.030 6.616 r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_5/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.616 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16536 + net (fanout=1) 0.000 6.616 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16446 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_6/CIN (GTP_LUT5CARRY) td 0.030 6.646 r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_6/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.646 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16537 + net (fanout=1) 0.000 6.646 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16447 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_7/CIN (GTP_LUT5CARRY) td 0.030 6.676 r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_7/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.676 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16538 + net (fanout=1) 0.000 6.676 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16448 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_8/CIN (GTP_LUT5CARRY) td 0.030 6.706 r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_8/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.706 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16539 + net (fanout=1) 0.000 6.706 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16449 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_9/CIN (GTP_LUT5CARRY) td 0.030 6.736 r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_9/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.736 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16540 + net (fanout=1) 0.000 6.736 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16450 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_10/CIN (GTP_LUT5CARRY) td 0.236 6.972 r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_10/Z (GTP_LUT5CARRY) net (fanout=4) 0.641 7.613 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2 [9] @@ -1277,31 +1283,31 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=3) 0.605 6.295 u_ov5640/u_mix_image/wr2_en u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_1/I0 (GTP_LUT5CARRY) td 0.201 6.496 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_1/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.496 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16532 + net (fanout=1) 0.000 6.496 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16442 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_2/CIN (GTP_LUT5CARRY) td 0.030 6.526 r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_2/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.526 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16533 + net (fanout=1) 0.000 6.526 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16443 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_3/CIN (GTP_LUT5CARRY) td 0.030 6.556 r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_3/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.556 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16534 + net (fanout=1) 0.000 6.556 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16444 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_4/CIN (GTP_LUT5CARRY) td 0.030 6.586 r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_4/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.586 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16535 + net (fanout=1) 0.000 6.586 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16445 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_5/CIN (GTP_LUT5CARRY) td 0.030 6.616 r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_5/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.616 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16536 + net (fanout=1) 0.000 6.616 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16446 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_6/CIN (GTP_LUT5CARRY) td 0.030 6.646 r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_6/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.646 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16537 + net (fanout=1) 0.000 6.646 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16447 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_7/CIN (GTP_LUT5CARRY) td 0.030 6.676 r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_7/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.676 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16538 + net (fanout=1) 0.000 6.676 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16448 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_8/CIN (GTP_LUT5CARRY) td 0.030 6.706 r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_8/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.706 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16539 + net (fanout=1) 0.000 6.706 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16449 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_9/CIN (GTP_LUT5CARRY) td 0.030 6.736 r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_9/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.736 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16540 + net (fanout=1) 0.000 6.736 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16450 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_10/CIN (GTP_LUT5CARRY) td 0.236 6.972 r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_10/Z (GTP_LUT5CARRY) net (fanout=4) 0.641 7.613 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2 [9] @@ -1364,28 +1370,28 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=3) 0.605 6.295 u_ov5640/u_mix_image/wr2_en u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_1/I0 (GTP_LUT5CARRY) td 0.201 6.496 f u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_1/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.496 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16532 + net (fanout=1) 0.000 6.496 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16442 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_2/CIN (GTP_LUT5CARRY) td 0.030 6.526 r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_2/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.526 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16533 + net (fanout=1) 0.000 6.526 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16443 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_3/CIN (GTP_LUT5CARRY) td 0.030 6.556 r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_3/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.556 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16534 + net (fanout=1) 0.000 6.556 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16444 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_4/CIN (GTP_LUT5CARRY) td 0.030 6.586 r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_4/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.586 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16535 + net (fanout=1) 0.000 6.586 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16445 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_5/CIN (GTP_LUT5CARRY) td 0.030 6.616 r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_5/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.616 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16536 + net (fanout=1) 0.000 6.616 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16446 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_6/CIN (GTP_LUT5CARRY) td 0.030 6.646 r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_6/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.646 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16537 + net (fanout=1) 0.000 6.646 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16447 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_7/CIN (GTP_LUT5CARRY) td 0.030 6.676 r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_7/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.676 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16538 + net (fanout=1) 0.000 6.676 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16448 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_8/CIN (GTP_LUT5CARRY) td 0.030 6.706 r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_8/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.706 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16539 + net (fanout=1) 0.000 6.706 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16449 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_9/CIN (GTP_LUT5CARRY) td 0.236 6.942 r u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_9/Z (GTP_LUT5CARRY) net (fanout=4) 0.641 7.583 u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2 [8] @@ -1670,31 +1676,31 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=5) 0.670 5.414 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/wr_addr [0] u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_2/I1 (GTP_LUT5CARRY) td 0.295 5.709 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_2/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 5.709 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16001 + net (fanout=1) 0.000 5.709 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15959 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_3/CIN (GTP_LUT5CARRY) td 0.030 5.739 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_3/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 5.739 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16002 + net (fanout=1) 0.000 5.739 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15960 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_4/CIN (GTP_LUT5CARRY) td 0.030 5.769 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_4/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 5.769 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16003 + net (fanout=1) 0.000 5.769 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15961 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_5/CIN (GTP_LUT5CARRY) td 0.030 5.799 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_5/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 5.799 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16004 + net (fanout=1) 0.000 5.799 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15962 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_6/CIN (GTP_LUT5CARRY) td 0.030 5.829 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_6/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 5.829 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16005 + net (fanout=1) 0.000 5.829 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15963 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_7/CIN (GTP_LUT5CARRY) td 0.030 5.859 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_7/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 5.859 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16006 + net (fanout=1) 0.000 5.859 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15964 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_8/CIN (GTP_LUT5CARRY) td 0.030 5.889 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_8/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 5.889 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16007 + net (fanout=1) 0.000 5.889 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15965 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_9/CIN (GTP_LUT5CARRY) td 0.030 5.919 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_9/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 5.919 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16008 + net (fanout=1) 0.000 5.919 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15966 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_10/CIN (GTP_LUT5CARRY) td 0.030 5.949 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_10/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 5.949 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16009 + net (fanout=1) 0.000 5.949 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15967 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_11/CIN (GTP_LUT5CARRY) td 0.236 6.185 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_11/Z (GTP_LUT5CARRY) net (fanout=4) 0.641 6.826 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2 [10] @@ -1754,28 +1760,28 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=5) 0.670 5.414 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/wr_addr [0] u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_2/I1 (GTP_LUT5CARRY) td 0.295 5.709 f u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_2/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 5.709 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16001 + net (fanout=1) 0.000 5.709 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15959 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_3/CIN (GTP_LUT5CARRY) td 0.030 5.739 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_3/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 5.739 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16002 + net (fanout=1) 0.000 5.739 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15960 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_4/CIN (GTP_LUT5CARRY) td 0.030 5.769 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_4/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 5.769 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16003 + net (fanout=1) 0.000 5.769 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15961 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_5/CIN (GTP_LUT5CARRY) td 0.030 5.799 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_5/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 5.799 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16004 + net (fanout=1) 0.000 5.799 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15962 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_6/CIN (GTP_LUT5CARRY) td 0.030 5.829 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_6/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 5.829 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16005 + net (fanout=1) 0.000 5.829 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15963 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_7/CIN (GTP_LUT5CARRY) td 0.030 5.859 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_7/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 5.859 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16006 + net (fanout=1) 0.000 5.859 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15964 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_8/CIN (GTP_LUT5CARRY) td 0.030 5.889 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_8/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 5.889 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16007 + net (fanout=1) 0.000 5.889 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15965 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_9/CIN (GTP_LUT5CARRY) td 0.030 5.919 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_9/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 5.919 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16008 + net (fanout=1) 0.000 5.919 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15966 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_10/CIN (GTP_LUT5CARRY) td 0.236 6.155 r u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_10/Z (GTP_LUT5CARRY) net (fanout=4) 0.641 6.796 u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2 [9] @@ -1992,24 +1998,24 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim tco 0.329 5.929 r udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[0]/Q (GTP_DFF_CE) net (fanout=1) 0.464 6.393 udp_osd_inst/eth_udp_inst/udp_rx_pkt_dest_port [0] - udp_osd_inst/eth_udp_inst/N72_16/I0 (GTP_LUT5) - td 0.318 6.711 f udp_osd_inst/eth_udp_inst/N72_16/Z (GTP_LUT5) - net (fanout=1) 0.464 7.175 udp_osd_inst/eth_udp_inst/_N104315 - udp_osd_inst/eth_udp_inst/N72_17/I4 (GTP_LUT5) - td 0.185 7.360 r udp_osd_inst/eth_udp_inst/N72_17/Z (GTP_LUT5) - net (fanout=2) 0.553 7.913 _N97297 - udp_osd_inst/eth_udp_inst/N72_23/I3 (GTP_LUT4) - td 0.185 8.098 r udp_osd_inst/eth_udp_inst/N72_23/Z (GTP_LUT4) - net (fanout=2) 0.553 8.651 udp_osd_inst/eth_udp_inst/_N106920 - udp_osd_inst/eth_udp_inst/N72_24/I4 (GTP_LUT5) - td 0.185 8.836 r udp_osd_inst/eth_udp_inst/N72_24/Z (GTP_LUT5) + udp_osd_inst/eth_udp_inst/N72_18/I0 (GTP_LUT5) + td 0.318 6.711 f udp_osd_inst/eth_udp_inst/N72_18/Z (GTP_LUT5) + net (fanout=1) 0.464 7.175 udp_osd_inst/eth_udp_inst/_N105154 + udp_osd_inst/eth_udp_inst/N72_19/I4 (GTP_LUT5) + td 0.185 7.360 r udp_osd_inst/eth_udp_inst/N72_19/Z (GTP_LUT5) + net (fanout=2) 0.553 7.913 _N98118 + udp_osd_inst/eth_udp_inst/N72_25/I3 (GTP_LUT4) + td 0.185 8.098 r udp_osd_inst/eth_udp_inst/N72_25/Z (GTP_LUT4) + net (fanout=2) 0.553 8.651 udp_osd_inst/eth_udp_inst/_N107744 + udp_osd_inst/eth_udp_inst/N72_26/I4 (GTP_LUT5) + td 0.185 8.836 r udp_osd_inst/eth_udp_inst/N72_26/Z (GTP_LUT5) net (fanout=2) 0.553 9.389 udp_osd_inst/eth_udp_inst/N72 udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N10/I2 (GTP_LUT3) td 0.185 9.574 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N10/Z (GTP_LUT3) net (fanout=10) 0.758 10.332 udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/fifo_wr_en udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[1]_1/I0 (GTP_LUT5) td 0.185 10.517 r udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[1]_1/Z (GTP_LUT5) - net (fanout=1) 0.464 10.981 udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N108382 + net (fanout=1) 0.464 10.981 udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N109270 udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167.eq_0/I3 (GTP_LUT5CARRY) td 0.233 11.214 f udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167.eq_0/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 11.214 udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167.co [0] @@ -2096,10 +2102,10 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=5) 0.670 6.599 udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num [11] udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_9/I0 (GTP_LUT4) td 0.290 6.889 f udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_9/Z (GTP_LUT4) - net (fanout=1) 0.464 7.353 udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N107696 + net (fanout=1) 0.464 7.353 udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N108528 udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_11/I4 (GTP_LUT5) td 0.185 7.538 r udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_11/Z (GTP_LUT5) - net (fanout=1) 0.464 8.002 udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N107698 + net (fanout=1) 0.464 8.002 udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N108530 udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_12/I4 (GTP_LUT5) td 0.185 8.187 r udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_12/Z (GTP_LUT5) net (fanout=16) 0.819 9.006 udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3 @@ -2198,10 +2204,10 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=5) 0.670 6.599 udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num [11] udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_9/I0 (GTP_LUT4) td 0.290 6.889 f udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_9/Z (GTP_LUT4) - net (fanout=1) 0.464 7.353 udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N107696 + net (fanout=1) 0.464 7.353 udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N108528 udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_11/I4 (GTP_LUT5) td 0.185 7.538 r udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_11/Z (GTP_LUT5) - net (fanout=1) 0.464 8.002 udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N107698 + net (fanout=1) 0.464 8.002 udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N108530 udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_12/I4 (GTP_LUT5) td 0.185 8.187 r udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_12/Z (GTP_LUT5) net (fanout=16) 0.819 9.006 udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3 @@ -2463,9 +2469,9 @@ Endpoint : u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctr Path Group : clk_50m Path Type : max (slow corner) Path Class : sequential timing path -Clock Skew : -0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.526 - Launch Clock Delay : 6.040 +Clock Skew : -0.515 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 5.523 + Launch Clock Delay : 6.038 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -2479,56 +2485,56 @@ Clock Skew : -0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessi net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.644 6.040 rd3_clk + net (fanout=2825) 3.642 6.038 rd3_clk r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/CLKB (GTP_DRM9K) - tco 2.024 8.064 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/DOB[0] (GTP_DRM9K) - net (fanout=6) 1.132 9.196 u_rotate_image/dout [0] + tco 2.024 8.062 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/DOB[0] (GTP_DRM9K) + net (fanout=6) 1.132 9.194 u_rotate_image/dout [0] u_rotate_image/N181_1/I2 (GTP_LUT5) - td 0.185 9.381 r u_rotate_image/N181_1/Z (GTP_LUT5) - net (fanout=4) 0.641 10.022 u_rotate_image/addr_fifo_rd_en + td 0.185 9.379 r u_rotate_image/N181_1/Z (GTP_LUT5) + net (fanout=4) 0.641 10.020 u_rotate_image/addr_fifo_rd_en u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_1/I0 (GTP_LUT5CARRY) - td 0.201 10.223 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_1/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 10.223 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16636 + td 0.201 10.221 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_1/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 10.221 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16575 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_2/CIN (GTP_LUT5CARRY) - td 0.030 10.253 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_2/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 10.253 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16637 + td 0.030 10.251 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_2/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 10.251 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16576 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_3/CIN (GTP_LUT5CARRY) - td 0.030 10.283 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_3/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 10.283 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16638 + td 0.030 10.281 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_3/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 10.281 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16577 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_4/CIN (GTP_LUT5CARRY) - td 0.030 10.313 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_4/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 10.313 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16639 + td 0.030 10.311 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_4/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 10.311 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16578 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_5/CIN (GTP_LUT5CARRY) - td 0.030 10.343 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_5/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 10.343 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16640 + td 0.030 10.341 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_5/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 10.341 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16579 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_6/CIN (GTP_LUT5CARRY) - td 0.030 10.373 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_6/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 10.373 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16641 + td 0.030 10.371 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_6/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 10.371 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16580 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_7/CIN (GTP_LUT5CARRY) - td 0.030 10.403 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_7/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 10.403 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16642 + td 0.030 10.401 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_7/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 10.401 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16581 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_8/CIN (GTP_LUT5CARRY) - td 0.030 10.433 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_8/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 10.433 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16643 + td 0.030 10.431 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_8/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 10.431 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16582 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_9/CIN (GTP_LUT5CARRY) - td 0.236 10.669 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_9/Z (GTP_LUT5CARRY) - net (fanout=2) 0.553 11.222 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11 [8] + td 0.236 10.667 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_9/Z (GTP_LUT5CARRY) + net (fanout=2) 0.553 11.220 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11 [8] u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[8]/I2 (GTP_LUT3) - td 0.185 11.407 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[8]/Z (GTP_LUT3) - net (fanout=3) 0.605 12.012 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/rrptr [8] + td 0.185 11.405 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[8]/Z (GTP_LUT3) + net (fanout=3) 0.605 12.010 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/rrptr [8] u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_4/I1 (GTP_LUT5CARRY) - td 0.363 12.375 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_4/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 12.375 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.co [8] + td 0.363 12.373 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_4/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 12.373 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.co [8] u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_5/CIN (GTP_LUT5CARRY) - td 0.236 12.611 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_5/Z (GTP_LUT5CARRY) - net (fanout=1) 0.464 13.075 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21 + td 0.236 12.609 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_5/Z (GTP_LUT5CARRY) + net (fanout=1) 0.464 13.073 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N22/I0 (GTP_LUT2) - td 0.185 13.260 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N22/Z (GTP_LUT2) - net (fanout=1) 0.000 13.260 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N22 + td 0.185 13.258 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N22/Z (GTP_LUT2) + net (fanout=1) 0.000 13.258 u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N22 r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/D (GTP_DFF_C) - Data arrival time 13.260 Logic Levels: 7 + Data arrival time 13.258 Logic Levels: 7 Logic: 3.825ns(52.978%), Route: 3.395ns(47.022%) ---------------------------------------------------------------------------------------------------- @@ -2540,19 +2546,19 @@ Clock Skew : -0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessi net (fanout=1) 1.091 22.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 22.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.130 25.526 rd3_clk + net (fanout=2825) 3.127 25.523 rd3_clk r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/CLK (GTP_DFF_C) - clock pessimism 0.000 25.526 - clock uncertainty -0.150 25.376 + clock pessimism 0.000 25.523 + clock uncertainty -0.150 25.373 - Setup time 0.034 25.410 + Setup time 0.034 25.407 - Data required time 25.410 + Data required time 25.407 ---------------------------------------------------------------------------------------------------- - Data required time 25.410 - Data arrival time 13.260 + Data required time 25.407 + Data arrival time 13.258 ---------------------------------------------------------------------------------------------------- - Slack (MET) 12.150 + Slack (MET) 12.149 ==================================================================================================== ==================================================================================================== @@ -2563,8 +2569,8 @@ Path Group : clk_50m Path Type : max (slow corner) Path Class : sequential timing path Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.526 - Launch Clock Delay : 5.526 + Capture Clock Delay : 5.523 + Launch Clock Delay : 5.523 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -2578,65 +2584,65 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.130 5.526 rd3_clk + net (fanout=2825) 3.127 5.523 rd3_clk r image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[1]/CLK (GTP_DFF_RE) - tco 0.329 5.855 r image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[1]/Q (GTP_DFF_RE) - net (fanout=3) 0.605 6.460 image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt [1] - image_filiter_inst2/multiline_buffer_inst/N199_mux5_8/I0 (GTP_LUT5) - td 0.308 6.768 f image_filiter_inst2/multiline_buffer_inst/N199_mux5_8/Z (GTP_LUT5) - net (fanout=4) 0.641 7.409 image_filiter_inst2/multiline_buffer_inst/N53 + tco 0.329 5.852 r image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[1]/Q (GTP_DFF_RE) + net (fanout=3) 0.605 6.457 image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt [1] + image_filiter_inst2/multiline_buffer_inst/N53_mux5_8/I0 (GTP_LUT5) + td 0.308 6.765 f image_filiter_inst2/multiline_buffer_inst/N53_mux5_8/Z (GTP_LUT5) + net (fanout=4) 0.641 7.406 image_filiter_inst2/multiline_buffer_inst/N53 image_filiter_inst2/multiline_buffer_inst/N199_mux5/I0 (GTP_LUT2) - td 0.185 7.594 r image_filiter_inst2/multiline_buffer_inst/N199_mux5/Z (GTP_LUT2) - net (fanout=17) 0.826 8.420 image_filiter_inst2/multiline_buffer_inst/N199 - image_filiter_inst2/multiline_buffer_inst/N96_3/I0 (GTP_LUT5) - td 0.185 8.605 r image_filiter_inst2/multiline_buffer_inst/N96_3/Z (GTP_LUT5) - net (fanout=1) 0.464 9.069 image_filiter_inst2/multiline_buffer_inst/N96 + td 0.185 7.591 r image_filiter_inst2/multiline_buffer_inst/N199_mux5/Z (GTP_LUT2) + net (fanout=17) 0.826 8.417 image_filiter_inst2/multiline_buffer_inst/N199 + image_filiter_inst2/multiline_buffer_inst/N96_1/I0 (GTP_LUT5) + td 0.185 8.602 r image_filiter_inst2/multiline_buffer_inst/N96_1/Z (GTP_LUT5) + net (fanout=1) 0.464 9.066 image_filiter_inst2/multiline_buffer_inst/N96 image_filiter_inst2/multiline_buffer_inst/N130[0]/I1 (GTP_LUT5) - td 0.185 9.254 r image_filiter_inst2/multiline_buffer_inst/N130[0]/Z (GTP_LUT5) - net (fanout=5) 0.670 9.924 image_filiter_inst2/multiline_buffer_inst/rd_en [0] + td 0.185 9.251 r image_filiter_inst2/multiline_buffer_inst/N130[0]/Z (GTP_LUT5) + net (fanout=5) 0.670 9.921 image_filiter_inst2/multiline_buffer_inst/rd_en [0] image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_1/I0 (GTP_LUT5CARRY) - td 0.201 10.125 f image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_1/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 10.125 image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13408 + td 0.201 10.122 f image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_1/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 10.122 image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13410 image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_2/CIN (GTP_LUT5CARRY) - td 0.030 10.155 r image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_2/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 10.155 image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13409 + td 0.030 10.152 r image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_2/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 10.152 image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13411 image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_3/CIN (GTP_LUT5CARRY) - td 0.030 10.185 r image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_3/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 10.185 image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13410 + td 0.030 10.182 r image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_3/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 10.182 image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13412 image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_4/CIN (GTP_LUT5CARRY) - td 0.030 10.215 r image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_4/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 10.215 image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13411 + td 0.030 10.212 r image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_4/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 10.212 image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13413 image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_5/CIN (GTP_LUT5CARRY) - td 0.030 10.245 r image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_5/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 10.245 image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13412 + td 0.030 10.242 r image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_5/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 10.242 image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13414 image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_6/CIN (GTP_LUT5CARRY) - td 0.030 10.275 r image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_6/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 10.275 image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13413 + td 0.030 10.272 r image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_6/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 10.272 image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13415 image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_7/CIN (GTP_LUT5CARRY) - td 0.030 10.305 r image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_7/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 10.305 image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13414 + td 0.030 10.302 r image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_7/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 10.302 image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13416 image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_8/CIN (GTP_LUT5CARRY) - td 0.030 10.335 r image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_8/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 10.335 image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13415 + td 0.030 10.332 r image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_8/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 10.332 image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13417 image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_9/CIN (GTP_LUT5CARRY) - td 0.236 10.571 r image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_9/Z (GTP_LUT5CARRY) - net (fanout=2) 0.553 11.124 image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11 [8] + td 0.236 10.568 r image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_9/Z (GTP_LUT5CARRY) + net (fanout=2) 0.553 11.121 image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11 [8] image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[8]/I2 (GTP_LUT3) - td 0.185 11.309 r image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[8]/Z (GTP_LUT3) - net (fanout=2) 0.553 11.862 image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/rrptr [8] + td 0.185 11.306 r image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[8]/Z (GTP_LUT3) + net (fanout=2) 0.553 11.859 image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/rrptr [8] image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N21.eq_4/I1 (GTP_LUT5CARRY) - td 0.363 12.225 f image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N21.eq_4/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 12.225 image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N21.co [8] + td 0.363 12.222 f image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N21.eq_4/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 12.222 image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N21.co [8] image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N21.eq_5/CIN (GTP_LUT5CARRY) - td 0.236 12.461 r image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N21.eq_5/Z (GTP_LUT5CARRY) - net (fanout=1) 0.464 12.925 image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N21 + td 0.236 12.458 r image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N21.eq_5/Z (GTP_LUT5CARRY) + net (fanout=1) 0.464 12.922 image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N21 image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N22/I4 (GTP_LUT5) - td 0.185 13.110 r image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N22/Z (GTP_LUT5) - net (fanout=1) 0.000 13.110 image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N22 + td 0.185 13.107 r image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N22/Z (GTP_LUT5) + net (fanout=1) 0.000 13.107 image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N22 r image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/D (GTP_DFF_C) - Data arrival time 13.110 Logic Levels: 10 + Data arrival time 13.107 Logic Levels: 10 Logic: 2.808ns(37.025%), Route: 4.776ns(62.975%) ---------------------------------------------------------------------------------------------------- @@ -2648,17 +2654,17 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 22.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 22.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.130 25.526 rd3_clk + net (fanout=2825) 3.127 25.523 rd3_clk r image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/CLK (GTP_DFF_C) - clock pessimism 0.000 25.526 - clock uncertainty -0.150 25.376 + clock pessimism 0.000 25.523 + clock uncertainty -0.150 25.373 - Setup time 0.034 25.410 + Setup time 0.034 25.407 - Data required time 25.410 + Data required time 25.407 ---------------------------------------------------------------------------------------------------- - Data required time 25.410 - Data arrival time 13.110 + Data required time 25.407 + Data arrival time 13.107 ---------------------------------------------------------------------------------------------------- Slack (MET) 12.300 ==================================================================================================== @@ -2670,9 +2676,9 @@ Endpoint : u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_i Path Group : clk_50m Path Type : max (slow corner) Path Class : sequential timing path -Clock Skew : -0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.526 - Launch Clock Delay : 6.040 +Clock Skew : -0.515 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 5.523 + Launch Clock Delay : 6.038 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -2686,53 +2692,53 @@ Clock Skew : -0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessi net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.644 6.040 rd3_clk + net (fanout=2825) 3.642 6.038 rd3_clk r u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/CLKB (GTP_DRM9K) - tco 2.024 8.064 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/DOB[0] (GTP_DRM9K) - net (fanout=6) 1.132 9.196 u_rotate_image/dout [0] + tco 2.024 8.062 f u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/DOB[0] (GTP_DRM9K) + net (fanout=6) 1.132 9.194 u_rotate_image/dout [0] u_rotate_image/N170_5/I2 (GTP_LUT4) - td 0.185 9.381 r u_rotate_image/N170_5/Z (GTP_LUT4) - net (fanout=4) 0.641 10.022 u_rotate_image/N170 + td 0.185 9.379 r u_rotate_image/N170_5/Z (GTP_LUT4) + net (fanout=4) 0.641 10.020 u_rotate_image/N170 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_1/I0 (GTP_LUT5CARRY) - td 0.201 10.223 f u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_1/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 10.223 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16661 + td 0.201 10.221 f u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_1/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 10.221 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16600 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_2/CIN (GTP_LUT5CARRY) - td 0.030 10.253 r u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_2/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 10.253 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16662 + td 0.030 10.251 r u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_2/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 10.251 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16601 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_3/CIN (GTP_LUT5CARRY) - td 0.030 10.283 r u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_3/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 10.283 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16663 + td 0.030 10.281 r u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_3/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 10.281 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16602 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_4/CIN (GTP_LUT5CARRY) - td 0.030 10.313 r u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_4/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 10.313 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16664 + td 0.030 10.311 r u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_4/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 10.311 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16603 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_5/CIN (GTP_LUT5CARRY) - td 0.030 10.343 r u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_5/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 10.343 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16665 + td 0.030 10.341 r u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_5/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 10.341 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16604 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_6/CIN (GTP_LUT5CARRY) - td 0.030 10.373 r u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_6/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 10.373 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16666 + td 0.030 10.371 r u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_6/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 10.371 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16605 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_7/CIN (GTP_LUT5CARRY) - td 0.030 10.403 r u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_7/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 10.403 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16667 + td 0.030 10.401 r u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_7/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 10.401 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16606 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_8/CIN (GTP_LUT5CARRY) - td 0.030 10.433 r u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_8/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 10.433 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16668 + td 0.030 10.431 r u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_8/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 10.431 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16607 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_9/CIN (GTP_LUT5CARRY) - td 0.236 10.669 r u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_9/Z (GTP_LUT5CARRY) - net (fanout=2) 0.553 11.222 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11 [8] + td 0.236 10.667 r u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_9/Z (GTP_LUT5CARRY) + net (fanout=2) 0.553 11.220 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11 [8] u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[8]/I2 (GTP_LUT3) - td 0.185 11.407 r u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[8]/Z (GTP_LUT3) - net (fanout=1) 0.464 11.871 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/rrptr [8] + td 0.185 11.405 r u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[8]/Z (GTP_LUT3) + net (fanout=1) 0.464 11.869 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/rrptr [8] u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N24.eq_4/I1 (GTP_LUT5CARRY) - td 0.363 12.234 f u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N24.eq_4/COUT (GTP_LUT5CARRY) - net (fanout=2) 0.553 12.787 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N21 + td 0.363 12.232 f u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N24.eq_4/COUT (GTP_LUT5CARRY) + net (fanout=2) 0.553 12.785 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N21 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N22/I1 (GTP_LUT5) - td 0.185 12.972 r u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N22/Z (GTP_LUT5) - net (fanout=1) 0.000 12.972 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N22 + td 0.185 12.970 r u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N22/Z (GTP_LUT5) + net (fanout=1) 0.000 12.970 u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N22 r u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/D (GTP_DFF_C) - Data arrival time 12.972 Logic Levels: 7 + Data arrival time 12.970 Logic Levels: 7 Logic: 3.589ns(51.774%), Route: 3.343ns(48.226%) ---------------------------------------------------------------------------------------------------- @@ -2744,19 +2750,19 @@ Clock Skew : -0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessi net (fanout=1) 1.091 22.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 22.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.130 25.526 rd3_clk + net (fanout=2825) 3.127 25.523 rd3_clk r u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/CLK (GTP_DFF_C) - clock pessimism 0.000 25.526 - clock uncertainty -0.150 25.376 + clock pessimism 0.000 25.523 + clock uncertainty -0.150 25.373 - Setup time 0.034 25.410 + Setup time 0.034 25.407 - Data required time 25.410 + Data required time 25.407 ---------------------------------------------------------------------------------------------------- - Data required time 25.410 - Data arrival time 12.972 + Data required time 25.407 + Data arrival time 12.970 ---------------------------------------------------------------------------------------------------- - Slack (MET) 12.438 + Slack (MET) 12.437 ==================================================================================================== ==================================================================================================== @@ -2766,9 +2772,9 @@ Endpoint : u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ Path Group : clk_50m Path Type : min (slow corner) Path Class : sequential timing path -Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 6.040 - Launch Clock Delay : 5.526 +Clock Skew : 0.515 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 6.038 + Launch Clock Delay : 5.523 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -2782,14 +2788,14 @@ Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.130 5.526 rd3_clk + net (fanout=2825) 3.127 5.523 rd3_clk r u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[5]/CLK (GTP_DFF) - tco 0.323 5.849 f u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[5]/Q (GTP_DFF) - net (fanout=1) 0.978 6.827 rd3_ddr_addr[5] + tco 0.323 5.846 f u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[5]/Q (GTP_DFF) + net (fanout=1) 0.978 6.824 rd3_ddr_addr[5] f u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/DIA[5] (GTP_DRM18K) - Data arrival time 6.827 Logic Levels: 0 + Data arrival time 6.824 Logic Levels: 0 Logic: 0.323ns(24.827%), Route: 0.978ns(75.173%) ---------------------------------------------------------------------------------------------------- @@ -2801,19 +2807,19 @@ Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.644 6.040 rd3_clk + net (fanout=2825) 3.642 6.038 rd3_clk r u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (GTP_DRM18K) - clock pessimism 0.000 6.040 - clock uncertainty 0.000 6.040 + clock pessimism 0.000 6.038 + clock uncertainty 0.000 6.038 - Hold time 0.137 6.177 + Hold time 0.137 6.175 - Data required time 6.177 + Data required time 6.175 ---------------------------------------------------------------------------------------------------- - Data required time 6.177 - Data arrival time 6.827 + Data required time 6.175 + Data arrival time 6.824 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.650 + Slack (MET) 0.649 ==================================================================================================== ==================================================================================================== @@ -2823,9 +2829,9 @@ Endpoint : u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ Path Group : clk_50m Path Type : min (slow corner) Path Class : sequential timing path -Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 6.040 - Launch Clock Delay : 5.526 +Clock Skew : 0.515 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 6.038 + Launch Clock Delay : 5.523 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -2839,14 +2845,14 @@ Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.130 5.526 rd3_clk + net (fanout=2825) 3.127 5.523 rd3_clk r u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[6]/CLK (GTP_DFF) - tco 0.323 5.849 f u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[6]/Q (GTP_DFF) - net (fanout=1) 0.978 6.827 rd3_ddr_addr[6] + tco 0.323 5.846 f u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[6]/Q (GTP_DFF) + net (fanout=1) 0.978 6.824 rd3_ddr_addr[6] f u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/DIA[6] (GTP_DRM18K) - Data arrival time 6.827 Logic Levels: 0 + Data arrival time 6.824 Logic Levels: 0 Logic: 0.323ns(24.827%), Route: 0.978ns(75.173%) ---------------------------------------------------------------------------------------------------- @@ -2858,19 +2864,19 @@ Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.644 6.040 rd3_clk + net (fanout=2825) 3.642 6.038 rd3_clk r u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (GTP_DRM18K) - clock pessimism 0.000 6.040 - clock uncertainty 0.000 6.040 + clock pessimism 0.000 6.038 + clock uncertainty 0.000 6.038 - Hold time 0.137 6.177 + Hold time 0.137 6.175 - Data required time 6.177 + Data required time 6.175 ---------------------------------------------------------------------------------------------------- - Data required time 6.177 - Data arrival time 6.827 + Data required time 6.175 + Data arrival time 6.824 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.650 + Slack (MET) 0.649 ==================================================================================================== ==================================================================================================== @@ -2880,9 +2886,9 @@ Endpoint : u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ Path Group : clk_50m Path Type : min (slow corner) Path Class : sequential timing path -Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 6.040 - Launch Clock Delay : 5.526 +Clock Skew : 0.515 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 6.038 + Launch Clock Delay : 5.523 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -2896,14 +2902,14 @@ Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.130 5.526 rd3_clk + net (fanout=2825) 3.127 5.523 rd3_clk r u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[7]/CLK (GTP_DFF) - tco 0.323 5.849 f u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[7]/Q (GTP_DFF) - net (fanout=1) 0.978 6.827 rd3_ddr_addr[7] + tco 0.323 5.846 f u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[7]/Q (GTP_DFF) + net (fanout=1) 0.978 6.824 rd3_ddr_addr[7] f u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/DIA[7] (GTP_DRM18K) - Data arrival time 6.827 Logic Levels: 0 + Data arrival time 6.824 Logic Levels: 0 Logic: 0.323ns(24.827%), Route: 0.978ns(75.173%) ---------------------------------------------------------------------------------------------------- @@ -2915,31 +2921,31 @@ Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.644 6.040 rd3_clk + net (fanout=2825) 3.642 6.038 rd3_clk r u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (GTP_DRM18K) - clock pessimism 0.000 6.040 - clock uncertainty 0.000 6.040 + clock pessimism 0.000 6.038 + clock uncertainty 0.000 6.038 - Hold time 0.137 6.177 + Hold time 0.137 6.175 - Data required time 6.177 + Data required time 6.175 ---------------------------------------------------------------------------------------------------- - Data required time 6.177 - Data arrival time 6.827 + Data required time 6.175 + Data arrival time 6.824 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.650 + Slack (MET) 0.649 ==================================================================================================== ==================================================================================================== -Startpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/CLK (GTP_DFF_CE) -Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[12]/D (GTP_DFF_C) +Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[14]/CLK (GTP_DFF_CE) +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[0]/CE (GTP_DFF_CE) Path Group : clk_200m Path Type : max (slow corner) Path Class : sequential timing path Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 4.367 - Launch Clock Delay : 4.367 + Capture Clock Delay : 5.192 + Launch Clock Delay : 5.192 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -2953,63 +2959,27 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk - r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/CLK (GTP_DFF_CE) - - tco 0.329 4.696 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/Q (GTP_DFF_CE) - net (fanout=36) 0.958 5.654 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/wr_addr [0] - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N2_2/I1 (GTP_LUT5CARRY) - td 0.298 5.952 f u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N2_2/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 5.952 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16324 - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N2_3/CIN (GTP_LUT5CARRY) - td 0.236 6.188 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N2_3/Z (GTP_LUT5CARRY) - net (fanout=4) 0.641 6.829 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N2 [2] - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[2]/I2 (GTP_LUT3) - td 0.185 7.014 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[2]/Z (GTP_LUT3) - net (fanout=3) 0.605 7.619 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wwptr [2] - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_3/I2 (GTP_LUT5CARRY) - td 0.258 7.877 f u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_3/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 7.877 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [3] - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_4/CIN (GTP_LUT5CARRY) - td 0.030 7.907 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_4/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 7.907 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [4] - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_5/CIN (GTP_LUT5CARRY) - td 0.030 7.937 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_5/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 7.937 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [5] - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_6/CIN (GTP_LUT5CARRY) - td 0.030 7.967 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_6/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 7.967 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [6] - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_7/CIN (GTP_LUT5CARRY) - td 0.030 7.997 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_7/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 7.997 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [7] - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_8/CIN (GTP_LUT5CARRY) - td 0.030 8.027 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_8/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 8.027 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [8] - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_9/CIN (GTP_LUT5CARRY) - td 0.030 8.057 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_9/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 8.057 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [9] - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_10/CIN (GTP_LUT5CARRY) - td 0.030 8.087 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_10/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 8.087 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [10] - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_11/CIN (GTP_LUT5CARRY) - td 0.030 8.117 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_11/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 8.117 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [11] - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_12/CIN (GTP_LUT5CARRY) - td 0.030 8.147 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_12/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 8.147 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [12] - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_13/CIN (GTP_LUT5CARRY) - td 0.236 8.383 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_13/Z (GTP_LUT5CARRY) - net (fanout=2) 0.553 8.936 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/nb6 [12] - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_5[12]/I2 (GTP_LUT4) - td 0.185 9.121 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_5[12]/Z (GTP_LUT4) - net (fanout=1) 0.000 9.121 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N25859 - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_6[12]/I0 (GTP_MUX2LUT6) - td 0.000 9.121 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_6[12]/Z (GTP_MUX2LUT6) - net (fanout=1) 0.000 9.121 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336 [12] - r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[12]/D (GTP_DFF_C) - - Data arrival time 9.121 Logic Levels: 7 - Logic: 1.997ns(42.007%), Route: 2.757ns(57.993%) + net (fanout=7) 0.605 2.996 ddr_clk + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 2.196 5.192 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[14]/CLK (GTP_DFF_CE) + + tco 0.329 5.521 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[14]/Q (GTP_DFF_CE) + net (fanout=2) 0.553 6.074 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt [14] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_33/I0 (GTP_LUT5) + td 0.318 6.392 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_33/Z (GTP_LUT5) + net (fanout=2) 0.553 6.945 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107154 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_36/I4 (GTP_LUT5) + td 0.185 7.130 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_36/Z (GTP_LUT5) + net (fanout=1) 0.464 7.594 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107157 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43_3/I4 (GTP_LUT5) + td 0.172 7.766 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43_3/Z (GTP_LUT5) + net (fanout=19) 0.670 8.436 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43 + f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[0]/CE (GTP_DFF_CE) + + Data arrival time 8.436 Logic Levels: 3 + Logic: 1.004ns(30.949%), Route: 2.240ns(69.051%) ---------------------------------------------------------------------------------------------------- Clock clk_200m (rising edge) 5.000 5.000 r @@ -3020,31 +2990,34 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 7.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 7.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 9.367 zoom_clk - r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[12]/CLK (GTP_DFF_C) - clock pessimism 0.000 9.367 - clock uncertainty -0.150 9.217 + net (fanout=7) 0.605 7.996 ddr_clk + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + td 0.000 7.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 2.196 10.192 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[0]/CLK (GTP_DFF_CE) + clock pessimism 0.000 10.192 + clock uncertainty -0.150 10.042 - Setup time 0.034 9.251 + Setup time -0.542 9.500 - Data required time 9.251 + Data required time 9.500 ---------------------------------------------------------------------------------------------------- - Data required time 9.251 - Data arrival time 9.121 + Data required time 9.500 + Data arrival time 8.436 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.130 + Slack (MET) 1.064 ==================================================================================================== ==================================================================================================== -Startpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/CLK (GTP_DFF_CE) -Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[11]/D (GTP_DFF_C) +Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[14]/CLK (GTP_DFF_CE) +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[1]/CE (GTP_DFF_CE) Path Group : clk_200m Path Type : max (slow corner) Path Class : sequential timing path Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 4.367 - Launch Clock Delay : 4.367 + Capture Clock Delay : 5.192 + Launch Clock Delay : 5.192 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -3058,60 +3031,27 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk - r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/CLK (GTP_DFF_CE) - - tco 0.329 4.696 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/Q (GTP_DFF_CE) - net (fanout=36) 0.958 5.654 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/wr_addr [0] - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N2_2/I1 (GTP_LUT5CARRY) - td 0.298 5.952 f u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N2_2/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 5.952 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16324 - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N2_3/CIN (GTP_LUT5CARRY) - td 0.236 6.188 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N2_3/Z (GTP_LUT5CARRY) - net (fanout=4) 0.641 6.829 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N2 [2] - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[2]/I2 (GTP_LUT3) - td 0.185 7.014 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[2]/Z (GTP_LUT3) - net (fanout=3) 0.605 7.619 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wwptr [2] - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_3/I2 (GTP_LUT5CARRY) - td 0.258 7.877 f u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_3/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 7.877 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [3] - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_4/CIN (GTP_LUT5CARRY) - td 0.030 7.907 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_4/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 7.907 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [4] - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_5/CIN (GTP_LUT5CARRY) - td 0.030 7.937 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_5/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 7.937 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [5] - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_6/CIN (GTP_LUT5CARRY) - td 0.030 7.967 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_6/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 7.967 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [6] - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_7/CIN (GTP_LUT5CARRY) - td 0.030 7.997 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_7/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 7.997 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [7] - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_8/CIN (GTP_LUT5CARRY) - td 0.030 8.027 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_8/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 8.027 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [8] - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_9/CIN (GTP_LUT5CARRY) - td 0.030 8.057 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_9/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 8.057 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [9] - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_10/CIN (GTP_LUT5CARRY) - td 0.030 8.087 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_10/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 8.087 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [10] - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_11/CIN (GTP_LUT5CARRY) - td 0.030 8.117 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_11/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 8.117 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [11] - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_12/CIN (GTP_LUT5CARRY) - td 0.236 8.353 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_12/Z (GTP_LUT5CARRY) - net (fanout=2) 0.553 8.906 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/nb6 [11] - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_5[11]/I2 (GTP_LUT4) - td 0.185 9.091 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_5[11]/Z (GTP_LUT4) - net (fanout=1) 0.000 9.091 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N25858 - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_6[11]/I0 (GTP_MUX2LUT6) - td 0.000 9.091 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_6[11]/Z (GTP_MUX2LUT6) - net (fanout=1) 0.000 9.091 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336 [11] - r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[11]/D (GTP_DFF_C) - - Data arrival time 9.091 Logic Levels: 7 - Logic: 1.967ns(41.638%), Route: 2.757ns(58.362%) + net (fanout=7) 0.605 2.996 ddr_clk + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 2.196 5.192 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[14]/CLK (GTP_DFF_CE) + + tco 0.329 5.521 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[14]/Q (GTP_DFF_CE) + net (fanout=2) 0.553 6.074 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt [14] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_33/I0 (GTP_LUT5) + td 0.318 6.392 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_33/Z (GTP_LUT5) + net (fanout=2) 0.553 6.945 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107154 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_36/I4 (GTP_LUT5) + td 0.185 7.130 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_36/Z (GTP_LUT5) + net (fanout=1) 0.464 7.594 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107157 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43_3/I4 (GTP_LUT5) + td 0.172 7.766 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43_3/Z (GTP_LUT5) + net (fanout=19) 0.670 8.436 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43 + f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[1]/CE (GTP_DFF_CE) + + Data arrival time 8.436 Logic Levels: 3 + Logic: 1.004ns(30.949%), Route: 2.240ns(69.051%) ---------------------------------------------------------------------------------------------------- Clock clk_200m (rising edge) 5.000 5.000 r @@ -3122,31 +3062,34 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 7.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 7.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 9.367 zoom_clk - r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[11]/CLK (GTP_DFF_C) - clock pessimism 0.000 9.367 - clock uncertainty -0.150 9.217 + net (fanout=7) 0.605 7.996 ddr_clk + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + td 0.000 7.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 2.196 10.192 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[1]/CLK (GTP_DFF_CE) + clock pessimism 0.000 10.192 + clock uncertainty -0.150 10.042 - Setup time 0.034 9.251 + Setup time -0.542 9.500 - Data required time 9.251 + Data required time 9.500 ---------------------------------------------------------------------------------------------------- - Data required time 9.251 - Data arrival time 9.091 + Data required time 9.500 + Data arrival time 8.436 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.160 + Slack (MET) 1.064 ==================================================================================================== ==================================================================================================== -Startpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/CLK (GTP_DFF_CE) -Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[10]/D (GTP_DFF_C) +Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[14]/CLK (GTP_DFF_CE) +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[2]/CE (GTP_DFF_CE) Path Group : clk_200m Path Type : max (slow corner) Path Class : sequential timing path Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 4.367 - Launch Clock Delay : 4.367 + Capture Clock Delay : 5.192 + Launch Clock Delay : 5.192 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -3160,57 +3103,27 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk - r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/CLK (GTP_DFF_CE) - - tco 0.329 4.696 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/Q (GTP_DFF_CE) - net (fanout=36) 0.958 5.654 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/wr_addr [0] - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N2_2/I1 (GTP_LUT5CARRY) - td 0.298 5.952 f u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N2_2/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 5.952 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16324 - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N2_3/CIN (GTP_LUT5CARRY) - td 0.236 6.188 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N2_3/Z (GTP_LUT5CARRY) - net (fanout=4) 0.641 6.829 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N2 [2] - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[2]/I2 (GTP_LUT3) - td 0.185 7.014 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[2]/Z (GTP_LUT3) - net (fanout=3) 0.605 7.619 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wwptr [2] - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_3/I2 (GTP_LUT5CARRY) - td 0.258 7.877 f u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_3/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 7.877 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [3] - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_4/CIN (GTP_LUT5CARRY) - td 0.030 7.907 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_4/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 7.907 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [4] - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_5/CIN (GTP_LUT5CARRY) - td 0.030 7.937 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_5/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 7.937 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [5] - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_6/CIN (GTP_LUT5CARRY) - td 0.030 7.967 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_6/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 7.967 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [6] - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_7/CIN (GTP_LUT5CARRY) - td 0.030 7.997 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_7/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 7.997 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [7] - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_8/CIN (GTP_LUT5CARRY) - td 0.030 8.027 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_8/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 8.027 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [8] - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_9/CIN (GTP_LUT5CARRY) - td 0.030 8.057 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_9/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 8.057 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [9] - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_10/CIN (GTP_LUT5CARRY) - td 0.030 8.087 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_10/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 8.087 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [10] - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_11/CIN (GTP_LUT5CARRY) - td 0.236 8.323 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_11/Z (GTP_LUT5CARRY) - net (fanout=2) 0.553 8.876 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/nb6 [10] - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_5[10]/I2 (GTP_LUT4) - td 0.185 9.061 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_5[10]/Z (GTP_LUT4) - net (fanout=1) 0.000 9.061 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N25857 - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_6[10]/I0 (GTP_MUX2LUT6) - td 0.000 9.061 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_6[10]/Z (GTP_MUX2LUT6) - net (fanout=1) 0.000 9.061 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336 [10] - r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[10]/D (GTP_DFF_C) - - Data arrival time 9.061 Logic Levels: 7 - Logic: 1.937ns(41.265%), Route: 2.757ns(58.735%) + net (fanout=7) 0.605 2.996 ddr_clk + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 2.196 5.192 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[14]/CLK (GTP_DFF_CE) + + tco 0.329 5.521 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[14]/Q (GTP_DFF_CE) + net (fanout=2) 0.553 6.074 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt [14] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_33/I0 (GTP_LUT5) + td 0.318 6.392 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_33/Z (GTP_LUT5) + net (fanout=2) 0.553 6.945 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107154 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_36/I4 (GTP_LUT5) + td 0.185 7.130 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_36/Z (GTP_LUT5) + net (fanout=1) 0.464 7.594 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107157 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43_3/I4 (GTP_LUT5) + td 0.172 7.766 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43_3/Z (GTP_LUT5) + net (fanout=19) 0.670 8.436 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43 + f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[2]/CE (GTP_DFF_CE) + + Data arrival time 8.436 Logic Levels: 3 + Logic: 1.004ns(30.949%), Route: 2.240ns(69.051%) ---------------------------------------------------------------------------------------------------- Clock clk_200m (rising edge) 5.000 5.000 r @@ -3221,31 +3134,34 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 7.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 7.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 9.367 zoom_clk - r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[10]/CLK (GTP_DFF_C) - clock pessimism 0.000 9.367 - clock uncertainty -0.150 9.217 + net (fanout=7) 0.605 7.996 ddr_clk + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + td 0.000 7.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 2.196 10.192 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[2]/CLK (GTP_DFF_CE) + clock pessimism 0.000 10.192 + clock uncertainty -0.150 10.042 - Setup time 0.034 9.251 + Setup time -0.542 9.500 - Data required time 9.251 + Data required time 9.500 ---------------------------------------------------------------------------------------------------- - Data required time 9.251 - Data arrival time 9.061 + Data required time 9.500 + Data arrival time 8.436 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.190 + Slack (MET) 1.064 ==================================================================================================== ==================================================================================================== -Startpoint : u_zoom_image/imag_addr1[0]/CLK (GTP_DFF) -Endpoint : u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/DIA[0] (GTP_DRM9K) +Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/CLK (GTP_DFF_C) +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/D (GTP_DFF_C) Path Group : clk_200m Path Type : min (slow corner) Path Class : sequential timing path -Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 4.881 - Launch Clock Delay : 4.367 +Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 5.192 + Launch Clock Delay : 5.192 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -3259,15 +3175,18 @@ Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk - r u_zoom_image/imag_addr1[0]/CLK (GTP_DFF) + net (fanout=7) 0.605 2.996 ddr_clk + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 2.196 5.192 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/CLK (GTP_DFF_C) - tco 0.323 4.690 f u_zoom_image/imag_addr1[0]/Q (GTP_DFF) - net (fanout=1) 0.978 5.668 zoom_image_addr[0] - f u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/DIA[0] (GTP_DRM9K) + tco 0.323 5.515 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/Q (GTP_DFF_C) + net (fanout=1) 0.464 5.979 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1 [0] + f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/D (GTP_DFF_C) - Data arrival time 5.668 Logic Levels: 0 - Logic: 0.323ns(24.827%), Route: 0.978ns(75.173%) + Data arrival time 5.979 Logic Levels: 0 + Logic: 0.323ns(41.042%), Route: 0.464ns(58.958%) ---------------------------------------------------------------------------------------------------- Clock clk_200m (rising edge) 0.000 0.000 r @@ -3278,31 +3197,34 @@ Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 2.490 4.881 zoom_clk - r u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/CLKA (GTP_DRM9K) - clock pessimism 0.000 4.881 - clock uncertainty 0.000 4.881 + net (fanout=7) 0.605 2.996 ddr_clk + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 2.196 5.192 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/CLK (GTP_DFF_C) + clock pessimism 0.000 5.192 + clock uncertainty 0.000 5.192 - Hold time 0.131 5.012 + Hold time 0.047 5.239 - Data required time 5.012 + Data required time 5.239 ---------------------------------------------------------------------------------------------------- - Data required time 5.012 - Data arrival time 5.668 + Data required time 5.239 + Data arrival time 5.979 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.656 + Slack (MET) 0.740 ==================================================================================================== ==================================================================================================== -Startpoint : u_zoom_image/imag_addr1[1]/CLK (GTP_DFF) -Endpoint : u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/DIA[1] (GTP_DRM9K) +Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/dll_update_req_rst_ctrl/CLK (GTP_DFF_C) +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[0]/D (GTP_DFF_C) Path Group : clk_200m Path Type : min (slow corner) Path Class : sequential timing path -Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 4.881 - Launch Clock Delay : 4.367 +Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 5.192 + Launch Clock Delay : 5.192 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -3316,15 +3238,18 @@ Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk - r u_zoom_image/imag_addr1[1]/CLK (GTP_DFF) + net (fanout=7) 0.605 2.996 ddr_clk + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 2.196 5.192 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/dll_update_req_rst_ctrl/CLK (GTP_DFF_C) - tco 0.323 4.690 f u_zoom_image/imag_addr1[1]/Q (GTP_DFF) - net (fanout=1) 0.978 5.668 zoom_image_addr[1] - f u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/DIA[1] (GTP_DRM9K) + tco 0.323 5.515 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/dll_update_req_rst_ctrl/Q (GTP_DFF_C) + net (fanout=1) 0.464 5.979 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/dll_update_req_rst_ctrl + f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[0]/D (GTP_DFF_C) - Data arrival time 5.668 Logic Levels: 0 - Logic: 0.323ns(24.827%), Route: 0.978ns(75.173%) + Data arrival time 5.979 Logic Levels: 0 + Logic: 0.323ns(41.042%), Route: 0.464ns(58.958%) ---------------------------------------------------------------------------------------------------- Clock clk_200m (rising edge) 0.000 0.000 r @@ -3335,31 +3260,34 @@ Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 2.490 4.881 zoom_clk - r u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/CLKA (GTP_DRM9K) - clock pessimism 0.000 4.881 - clock uncertainty 0.000 4.881 + net (fanout=7) 0.605 2.996 ddr_clk + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 2.196 5.192 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[0]/CLK (GTP_DFF_C) + clock pessimism 0.000 5.192 + clock uncertainty 0.000 5.192 - Hold time 0.131 5.012 + Hold time 0.047 5.239 - Data required time 5.012 + Data required time 5.239 ---------------------------------------------------------------------------------------------------- - Data required time 5.012 - Data arrival time 5.668 + Data required time 5.239 + Data arrival time 5.979 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.656 + Slack (MET) 0.740 ==================================================================================================== ==================================================================================================== -Startpoint : u_zoom_image/imag_addr1[2]/CLK (GTP_DFF) -Endpoint : u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/DIA[2] (GTP_DRM9K) +Startpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[0]/CLK (GTP_DFF_C) +Endpoint : u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[1]/D (GTP_DFF_C) Path Group : clk_200m Path Type : min (slow corner) Path Class : sequential timing path -Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 4.881 - Launch Clock Delay : 4.367 +Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 5.192 + Launch Clock Delay : 5.192 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -3373,15 +3301,18 @@ Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk - r u_zoom_image/imag_addr1[2]/CLK (GTP_DFF) + net (fanout=7) 0.605 2.996 ddr_clk + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 2.196 5.192 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[0]/CLK (GTP_DFF_C) - tco 0.323 4.690 f u_zoom_image/imag_addr1[2]/Q (GTP_DFF) - net (fanout=1) 0.978 5.668 zoom_image_addr[2] - f u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/DIA[2] (GTP_DRM9K) + tco 0.323 5.515 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[0]/Q (GTP_DFF_C) + net (fanout=1) 0.464 5.979 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d [0] + f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[1]/D (GTP_DFF_C) - Data arrival time 5.668 Logic Levels: 0 - Logic: 0.323ns(24.827%), Route: 0.978ns(75.173%) + Data arrival time 5.979 Logic Levels: 0 + Logic: 0.323ns(41.042%), Route: 0.464ns(58.958%) ---------------------------------------------------------------------------------------------------- Clock clk_200m (rising edge) 0.000 0.000 r @@ -3392,19 +3323,22 @@ Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 2.490 4.881 zoom_clk - r u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/CLKA (GTP_DRM9K) - clock pessimism 0.000 4.881 - clock uncertainty 0.000 4.881 + net (fanout=7) 0.605 2.996 ddr_clk + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 2.196 5.192 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[1]/CLK (GTP_DFF_C) + clock pessimism 0.000 5.192 + clock uncertainty 0.000 5.192 - Hold time 0.131 5.012 + Hold time 0.047 5.239 - Data required time 5.012 + Data required time 5.239 ---------------------------------------------------------------------------------------------------- - Data required time 5.012 - Data arrival time 5.668 + Data required time 5.239 + Data arrival time 5.979 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.656 + Slack (MET) 0.740 ==================================================================================================== ==================================================================================================== @@ -3437,37 +3371,37 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=4) 0.641 4.083 u_ov5640/coms1_reg_config/clock_20k_cnt [0] u_ov5640/coms1_reg_config/N8_mux4_5/I0 (GTP_LUT5) td 0.303 4.386 f u_ov5640/coms1_reg_config/N8_mux4_5/Z (GTP_LUT5) - net (fanout=1) 0.464 4.850 u_ov5640/coms1_reg_config/_N9664 + net (fanout=1) 0.464 4.850 u_ov5640/coms1_reg_config/_N9677 u_ov5640/coms1_reg_config/N8_mux10/I0 (GTP_LUT5) td 0.185 5.035 r u_ov5640/coms1_reg_config/N8_mux10/Z (GTP_LUT5) net (fanout=12) 0.782 5.817 u_ov5640/coms1_reg_config/N8 u_ov5640/coms1_reg_config/N11_2_1/I2 (GTP_LUT5CARRY) td 0.233 6.050 f u_ov5640/coms1_reg_config/N11_2_1/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.050 u_ov5640/coms1_reg_config/_N16245 + net (fanout=1) 0.000 6.050 u_ov5640/coms1_reg_config/_N16267 u_ov5640/coms1_reg_config/N11_2_2/CIN (GTP_LUT5CARRY) td 0.030 6.080 r u_ov5640/coms1_reg_config/N11_2_2/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.080 u_ov5640/coms1_reg_config/_N16246 + net (fanout=1) 0.000 6.080 u_ov5640/coms1_reg_config/_N16268 u_ov5640/coms1_reg_config/N11_2_3/CIN (GTP_LUT5CARRY) td 0.030 6.110 r u_ov5640/coms1_reg_config/N11_2_3/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.110 u_ov5640/coms1_reg_config/_N16247 + net (fanout=1) 0.000 6.110 u_ov5640/coms1_reg_config/_N16269 u_ov5640/coms1_reg_config/N11_2_4/CIN (GTP_LUT5CARRY) td 0.030 6.140 r u_ov5640/coms1_reg_config/N11_2_4/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.140 u_ov5640/coms1_reg_config/_N16248 + net (fanout=1) 0.000 6.140 u_ov5640/coms1_reg_config/_N16270 u_ov5640/coms1_reg_config/N11_2_5/CIN (GTP_LUT5CARRY) td 0.030 6.170 r u_ov5640/coms1_reg_config/N11_2_5/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.170 u_ov5640/coms1_reg_config/_N16249 + net (fanout=1) 0.000 6.170 u_ov5640/coms1_reg_config/_N16271 u_ov5640/coms1_reg_config/N11_2_6/CIN (GTP_LUT5CARRY) td 0.030 6.200 r u_ov5640/coms1_reg_config/N11_2_6/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.200 u_ov5640/coms1_reg_config/_N16250 + net (fanout=1) 0.000 6.200 u_ov5640/coms1_reg_config/_N16272 u_ov5640/coms1_reg_config/N11_2_7/CIN (GTP_LUT5CARRY) td 0.030 6.230 r u_ov5640/coms1_reg_config/N11_2_7/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.230 u_ov5640/coms1_reg_config/_N16251 + net (fanout=1) 0.000 6.230 u_ov5640/coms1_reg_config/_N16273 u_ov5640/coms1_reg_config/N11_2_8/CIN (GTP_LUT5CARRY) td 0.030 6.260 r u_ov5640/coms1_reg_config/N11_2_8/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.260 u_ov5640/coms1_reg_config/_N16252 + net (fanout=1) 0.000 6.260 u_ov5640/coms1_reg_config/_N16274 u_ov5640/coms1_reg_config/N11_2_9/CIN (GTP_LUT5CARRY) td 0.030 6.290 r u_ov5640/coms1_reg_config/N11_2_9/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.290 u_ov5640/coms1_reg_config/_N16253 + net (fanout=1) 0.000 6.290 u_ov5640/coms1_reg_config/_N16275 u_ov5640/coms1_reg_config/N11_2_10/CIN (GTP_LUT5CARRY) td 0.236 6.526 r u_ov5640/coms1_reg_config/N11_2_10/Z (GTP_LUT5CARRY) net (fanout=1) 0.000 6.526 u_ov5640/coms1_reg_config/N1114 [10] @@ -3530,37 +3464,37 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=4) 0.641 4.083 u_ov5640/coms2_reg_config/clock_20k_cnt [0] u_ov5640/coms2_reg_config/N8_mux4_5/I4 (GTP_LUT5) td 0.303 4.386 f u_ov5640/coms2_reg_config/N8_mux4_5/Z (GTP_LUT5) - net (fanout=1) 0.464 4.850 u_ov5640/coms2_reg_config/_N9736 + net (fanout=1) 0.464 4.850 u_ov5640/coms2_reg_config/_N9749 u_ov5640/coms2_reg_config/N8_mux10/I0 (GTP_LUT5) td 0.185 5.035 r u_ov5640/coms2_reg_config/N8_mux10/Z (GTP_LUT5) net (fanout=12) 0.782 5.817 u_ov5640/coms2_reg_config/N8 u_ov5640/coms2_reg_config/N11_2_1/I2 (GTP_LUT5CARRY) td 0.233 6.050 f u_ov5640/coms2_reg_config/N11_2_1/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.050 u_ov5640/coms2_reg_config/_N16398 + net (fanout=1) 0.000 6.050 u_ov5640/coms2_reg_config/_N16302 u_ov5640/coms2_reg_config/N11_2_2/CIN (GTP_LUT5CARRY) td 0.030 6.080 r u_ov5640/coms2_reg_config/N11_2_2/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.080 u_ov5640/coms2_reg_config/_N16399 + net (fanout=1) 0.000 6.080 u_ov5640/coms2_reg_config/_N16303 u_ov5640/coms2_reg_config/N11_2_3/CIN (GTP_LUT5CARRY) td 0.030 6.110 r u_ov5640/coms2_reg_config/N11_2_3/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.110 u_ov5640/coms2_reg_config/_N16400 + net (fanout=1) 0.000 6.110 u_ov5640/coms2_reg_config/_N16304 u_ov5640/coms2_reg_config/N11_2_4/CIN (GTP_LUT5CARRY) td 0.030 6.140 r u_ov5640/coms2_reg_config/N11_2_4/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.140 u_ov5640/coms2_reg_config/_N16401 + net (fanout=1) 0.000 6.140 u_ov5640/coms2_reg_config/_N16305 u_ov5640/coms2_reg_config/N11_2_5/CIN (GTP_LUT5CARRY) td 0.030 6.170 r u_ov5640/coms2_reg_config/N11_2_5/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.170 u_ov5640/coms2_reg_config/_N16402 + net (fanout=1) 0.000 6.170 u_ov5640/coms2_reg_config/_N16306 u_ov5640/coms2_reg_config/N11_2_6/CIN (GTP_LUT5CARRY) td 0.030 6.200 r u_ov5640/coms2_reg_config/N11_2_6/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.200 u_ov5640/coms2_reg_config/_N16403 + net (fanout=1) 0.000 6.200 u_ov5640/coms2_reg_config/_N16307 u_ov5640/coms2_reg_config/N11_2_7/CIN (GTP_LUT5CARRY) td 0.030 6.230 r u_ov5640/coms2_reg_config/N11_2_7/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.230 u_ov5640/coms2_reg_config/_N16404 + net (fanout=1) 0.000 6.230 u_ov5640/coms2_reg_config/_N16308 u_ov5640/coms2_reg_config/N11_2_8/CIN (GTP_LUT5CARRY) td 0.030 6.260 r u_ov5640/coms2_reg_config/N11_2_8/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.260 u_ov5640/coms2_reg_config/_N16405 + net (fanout=1) 0.000 6.260 u_ov5640/coms2_reg_config/_N16309 u_ov5640/coms2_reg_config/N11_2_9/CIN (GTP_LUT5CARRY) td 0.030 6.290 r u_ov5640/coms2_reg_config/N11_2_9/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.290 u_ov5640/coms2_reg_config/_N16406 + net (fanout=1) 0.000 6.290 u_ov5640/coms2_reg_config/_N16310 u_ov5640/coms2_reg_config/N11_2_10/CIN (GTP_LUT5CARRY) td 0.236 6.526 r u_ov5640/coms2_reg_config/N11_2_10/Z (GTP_LUT5CARRY) net (fanout=1) 0.000 6.526 u_ov5640/coms2_reg_config/N1114 [10] @@ -3623,34 +3557,34 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=4) 0.641 4.083 u_ov5640/coms1_reg_config/clock_20k_cnt [0] u_ov5640/coms1_reg_config/N8_mux4_5/I0 (GTP_LUT5) td 0.303 4.386 f u_ov5640/coms1_reg_config/N8_mux4_5/Z (GTP_LUT5) - net (fanout=1) 0.464 4.850 u_ov5640/coms1_reg_config/_N9664 + net (fanout=1) 0.464 4.850 u_ov5640/coms1_reg_config/_N9677 u_ov5640/coms1_reg_config/N8_mux10/I0 (GTP_LUT5) td 0.185 5.035 r u_ov5640/coms1_reg_config/N8_mux10/Z (GTP_LUT5) net (fanout=12) 0.782 5.817 u_ov5640/coms1_reg_config/N8 u_ov5640/coms1_reg_config/N11_2_1/I2 (GTP_LUT5CARRY) td 0.233 6.050 f u_ov5640/coms1_reg_config/N11_2_1/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.050 u_ov5640/coms1_reg_config/_N16245 + net (fanout=1) 0.000 6.050 u_ov5640/coms1_reg_config/_N16267 u_ov5640/coms1_reg_config/N11_2_2/CIN (GTP_LUT5CARRY) td 0.030 6.080 r u_ov5640/coms1_reg_config/N11_2_2/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.080 u_ov5640/coms1_reg_config/_N16246 + net (fanout=1) 0.000 6.080 u_ov5640/coms1_reg_config/_N16268 u_ov5640/coms1_reg_config/N11_2_3/CIN (GTP_LUT5CARRY) td 0.030 6.110 r u_ov5640/coms1_reg_config/N11_2_3/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.110 u_ov5640/coms1_reg_config/_N16247 + net (fanout=1) 0.000 6.110 u_ov5640/coms1_reg_config/_N16269 u_ov5640/coms1_reg_config/N11_2_4/CIN (GTP_LUT5CARRY) td 0.030 6.140 r u_ov5640/coms1_reg_config/N11_2_4/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.140 u_ov5640/coms1_reg_config/_N16248 + net (fanout=1) 0.000 6.140 u_ov5640/coms1_reg_config/_N16270 u_ov5640/coms1_reg_config/N11_2_5/CIN (GTP_LUT5CARRY) td 0.030 6.170 r u_ov5640/coms1_reg_config/N11_2_5/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.170 u_ov5640/coms1_reg_config/_N16249 + net (fanout=1) 0.000 6.170 u_ov5640/coms1_reg_config/_N16271 u_ov5640/coms1_reg_config/N11_2_6/CIN (GTP_LUT5CARRY) td 0.030 6.200 r u_ov5640/coms1_reg_config/N11_2_6/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.200 u_ov5640/coms1_reg_config/_N16250 + net (fanout=1) 0.000 6.200 u_ov5640/coms1_reg_config/_N16272 u_ov5640/coms1_reg_config/N11_2_7/CIN (GTP_LUT5CARRY) td 0.030 6.230 r u_ov5640/coms1_reg_config/N11_2_7/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.230 u_ov5640/coms1_reg_config/_N16251 + net (fanout=1) 0.000 6.230 u_ov5640/coms1_reg_config/_N16273 u_ov5640/coms1_reg_config/N11_2_8/CIN (GTP_LUT5CARRY) td 0.030 6.260 r u_ov5640/coms1_reg_config/N11_2_8/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 6.260 u_ov5640/coms1_reg_config/_N16252 + net (fanout=1) 0.000 6.260 u_ov5640/coms1_reg_config/_N16274 u_ov5640/coms1_reg_config/N11_2_9/CIN (GTP_LUT5CARRY) td 0.236 6.496 r u_ov5640/coms1_reg_config/N11_2_9/Z (GTP_LUT5CARRY) net (fanout=1) 0.000 6.496 u_ov5640/coms1_reg_config/N1114 [9] @@ -3887,10 +3821,10 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=3) 0.605 4.444 ms72xx_ctl/ms7200_ctl/dri_cnt [4] ms72xx_ctl/ms7200_ctl/N8_3/I0 (GTP_LUT3) td 0.243 4.687 f ms72xx_ctl/ms7200_ctl/N8_3/Z (GTP_LUT3) - net (fanout=1) 0.464 5.151 ms72xx_ctl/ms7200_ctl/_N95853 + net (fanout=1) 0.464 5.151 ms72xx_ctl/ms7200_ctl/_N96627 ms72xx_ctl/ms7200_ctl/N1872_5/I3 (GTP_LUT4) td 0.185 5.336 r ms72xx_ctl/ms7200_ctl/N1872_5/Z (GTP_LUT4) - net (fanout=6) 0.693 6.029 ms72xx_ctl/ms7200_ctl/_N95857 + net (fanout=6) 0.693 6.029 ms72xx_ctl/ms7200_ctl/_N96632 ms72xx_ctl/ms7200_ctl/N2053_1/I1 (GTP_LUT2) td 0.185 6.214 r ms72xx_ctl/ms7200_ctl/N2053_1/Z (GTP_LUT2) net (fanout=15) 0.810 7.024 ms72xx_ctl/ms7200_ctl/N261 @@ -3962,10 +3896,10 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=3) 0.605 4.444 ms72xx_ctl/ms7200_ctl/dri_cnt [4] ms72xx_ctl/ms7200_ctl/N8_3/I0 (GTP_LUT3) td 0.243 4.687 f ms72xx_ctl/ms7200_ctl/N8_3/Z (GTP_LUT3) - net (fanout=1) 0.464 5.151 ms72xx_ctl/ms7200_ctl/_N95853 + net (fanout=1) 0.464 5.151 ms72xx_ctl/ms7200_ctl/_N96627 ms72xx_ctl/ms7200_ctl/N1872_5/I3 (GTP_LUT4) td 0.185 5.336 r ms72xx_ctl/ms7200_ctl/N1872_5/Z (GTP_LUT4) - net (fanout=6) 0.693 6.029 ms72xx_ctl/ms7200_ctl/_N95857 + net (fanout=6) 0.693 6.029 ms72xx_ctl/ms7200_ctl/_N96632 ms72xx_ctl/ms7200_ctl/N2053_1/I1 (GTP_LUT2) td 0.185 6.214 r ms72xx_ctl/ms7200_ctl/N2053_1/Z (GTP_LUT2) net (fanout=15) 0.810 7.024 ms72xx_ctl/ms7200_ctl/N261 @@ -4037,10 +3971,10 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=3) 0.605 4.444 ms72xx_ctl/ms7200_ctl/dri_cnt [4] ms72xx_ctl/ms7200_ctl/N8_3/I0 (GTP_LUT3) td 0.243 4.687 f ms72xx_ctl/ms7200_ctl/N8_3/Z (GTP_LUT3) - net (fanout=1) 0.464 5.151 ms72xx_ctl/ms7200_ctl/_N95853 + net (fanout=1) 0.464 5.151 ms72xx_ctl/ms7200_ctl/_N96627 ms72xx_ctl/ms7200_ctl/N1872_5/I3 (GTP_LUT4) td 0.185 5.336 r ms72xx_ctl/ms7200_ctl/N1872_5/Z (GTP_LUT4) - net (fanout=6) 0.693 6.029 ms72xx_ctl/ms7200_ctl/_N95857 + net (fanout=6) 0.693 6.029 ms72xx_ctl/ms7200_ctl/_N96632 ms72xx_ctl/ms7200_ctl/N2053_1/I1 (GTP_LUT2) td 0.185 6.214 r ms72xx_ctl/ms7200_ctl/N2053_1/Z (GTP_LUT2) net (fanout=15) 0.810 7.024 ms72xx_ctl/ms7200_ctl/N261 @@ -4055,7 +3989,7 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=3) 0.553 9.378 ms72xx_ctl/ms7200_ctl/N8 ms72xx_ctl/ms7200_ctl/freq_ensure_rs_mux/I0 (GTP_LUT4) td 0.258 9.636 f ms72xx_ctl/ms7200_ctl/freq_ensure_rs_mux/Z (GTP_LUT4) - net (fanout=1) 0.000 9.636 ms72xx_ctl/ms7200_ctl/_N103492 + net (fanout=1) 0.000 9.636 ms72xx_ctl/ms7200_ctl/_N104304 f ms72xx_ctl/ms7200_ctl/freq_ensure/D (GTP_DFF) Data arrival time 9.636 Logic Levels: 7 @@ -4258,20 +4192,20 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim ==================================================================================================== -Startpoint : sync_vg_100m/CLK (GTP_DFF_P) -Endpoint : udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[0]/D (GTP_DFF_SE) -Path Group : clk_720p60Hz +Startpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[15]/CLK (GTP_DFF_C) +Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[12]/D (GTP_DFF_C) +Path Group : clk_1080p60Hz Path Type : max (slow corner) Path Class : sequential timing path Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 8.073 - Launch Clock Delay : 8.073 + Capture Clock Delay : 7.588 + Launch Clock Delay : 7.588 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_720p60Hz (rising edge) 0.000 0.000 r + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r clk 0.000 0.000 r clk (port) net (fanout=1) 0.000 0.000 clk clk_ibuf/I (GTP_INBUF) @@ -4279,80 +4213,110 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.130 5.526 rd3_clk + net (fanout=2825) 3.127 5.523 rd3_clk U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.089 5.615 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=1758) 2.458 8.073 nt_pix_clk - r sync_vg_100m/CLK (GTP_DFF_P) - - tco 0.329 8.402 r sync_vg_100m/Q (GTP_DFF_P) - net (fanout=2548) 2.954 11.356 sync_vg_100m - udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/I0 (GTP_LUT5) - td 0.185 11.541 r udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/Z (GTP_LUT5) - net (fanout=2) 0.553 12.094 udp_osd_inst/char_osd_inst/row_pixels_ready - udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/I1 (GTP_LUT3) - td 0.185 12.279 r udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/Z (GTP_LUT3) - net (fanout=10) 0.693 12.972 udp_osd_inst/char_osd_inst/char_next - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N97/I0 (GTP_LUT2) - td 0.185 13.157 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N97/Z (GTP_LUT2) - net (fanout=9) 0.745 13.902 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N97 - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N839/I1 (GTP_LUT2) - td 0.185 14.087 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N839/Z (GTP_LUT2) - net (fanout=3) 0.605 14.692 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N839 - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_15_3/I2 (GTP_LUT3) - td 0.185 14.877 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_15_3/Z (GTP_LUT3) - net (fanout=11) 0.771 15.648 udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N18404 - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_11_inv[0]/I0 (GTP_LUT5) - td 0.217 15.865 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_11_inv[0]/Z (GTP_LUT5) - net (fanout=1) 0.000 15.865 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847 [0] - r udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[0]/D (GTP_DFF_SE) + td 0.094 5.617 r U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=844) 1.971 7.588 zoom_clk + r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[15]/CLK (GTP_DFF_C) + + tco 0.329 7.917 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[15]/Q (GTP_DFF_C) + net (fanout=14) 0.802 8.719 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2 [15] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_16/I4 (GTP_LUT5) + td 0.283 9.002 f u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_16/Z (GTP_LUT5) + net (fanout=1) 0.464 9.466 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr [11] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_22/I0 (GTP_LUT5) + td 0.185 9.651 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_22/Z (GTP_LUT5) + net (fanout=10) 0.758 10.409 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr [7] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_14/I0 (GTP_LUT3) + td 0.185 10.594 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_14/Z (GTP_LUT3) + net (fanout=2) 0.553 11.147 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr [1] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_2/I2 (GTP_LUT5CARRY) + td 0.233 11.380 f u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_2/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 11.380 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [2] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_3/CIN (GTP_LUT5CARRY) + td 0.030 11.410 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_3/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 11.410 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [3] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_4/CIN (GTP_LUT5CARRY) + td 0.030 11.440 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_4/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 11.440 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [4] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_5/CIN (GTP_LUT5CARRY) + td 0.030 11.470 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_5/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 11.470 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [5] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_6/CIN (GTP_LUT5CARRY) + td 0.030 11.500 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_6/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 11.500 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [6] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_7/CIN (GTP_LUT5CARRY) + td 0.030 11.530 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_7/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 11.530 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [7] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_8/CIN (GTP_LUT5CARRY) + td 0.030 11.560 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_8/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 11.560 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [8] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_9/CIN (GTP_LUT5CARRY) + td 0.030 11.590 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_9/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 11.590 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [9] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_10/CIN (GTP_LUT5CARRY) + td 0.030 11.620 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_10/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 11.620 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [10] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_11/CIN (GTP_LUT5CARRY) + td 0.030 11.650 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_11/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 11.650 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [11] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_12/CIN (GTP_LUT5CARRY) + td 0.030 11.680 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_12/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 11.680 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [12] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_13/CIN (GTP_LUT5CARRY) + td 0.236 11.916 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_13/Z (GTP_LUT5CARRY) + net (fanout=1) 0.464 12.380 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/nb6 [12] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_6[12]/I0 (GTP_LUT3) + td 0.185 12.565 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_6[12]/Z (GTP_LUT3) + net (fanout=1) 0.000 12.565 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336 [12] + r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[12]/D (GTP_DFF_C) - Data arrival time 15.865 Logic Levels: 6 - Logic: 1.471ns(18.878%), Route: 6.321ns(81.122%) + Data arrival time 12.565 Logic Levels: 7 + Logic: 1.936ns(38.899%), Route: 3.041ns(61.101%) ---------------------------------------------------------------------------------------------------- - Clock clk_720p60Hz (rising edge) 13.473 13.473 r - clk 0.000 13.473 r clk (port) - net (fanout=1) 0.000 13.473 clk + Clock clk_1080p60Hz (rising edge) 6.736 6.736 r + clk 0.000 6.736 r clk (port) + net (fanout=1) 0.000 6.736 clk clk_ibuf/I (GTP_INBUF) - td 1.211 14.684 r clk_ibuf/O (GTP_INBUF) - net (fanout=1) 1.091 15.775 nt_clk + td 1.211 7.947 r clk_ibuf/O (GTP_INBUF) + net (fanout=1) 1.091 9.038 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 15.869 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.130 18.999 rd3_clk + td 0.094 9.132 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=2825) 3.127 12.259 rd3_clk U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.089 19.088 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=1758) 2.458 21.546 nt_pix_clk - r udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[0]/CLK (GTP_DFF_SE) - clock pessimism 0.000 21.546 - clock uncertainty -0.150 21.396 + td 0.094 12.353 r U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=844) 1.971 14.324 zoom_clk + r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[12]/CLK (GTP_DFF_C) + clock pessimism 0.000 14.324 + clock uncertainty -0.150 14.174 - Setup time 0.034 21.430 + Setup time 0.034 14.208 - Data required time 21.430 + Data required time 14.208 ---------------------------------------------------------------------------------------------------- - Data required time 21.430 - Data arrival time 15.865 + Data required time 14.208 + Data arrival time 12.565 ---------------------------------------------------------------------------------------------------- - Slack (MET) 5.565 + Slack (MET) 1.643 ==================================================================================================== ==================================================================================================== -Startpoint : sync_vg_100m/CLK (GTP_DFF_P) -Endpoint : udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[1]/D (GTP_DFF_SE) -Path Group : clk_720p60Hz +Startpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[15]/CLK (GTP_DFF_C) +Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[11]/D (GTP_DFF_C) +Path Group : clk_1080p60Hz Path Type : max (slow corner) Path Class : sequential timing path Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 8.073 - Launch Clock Delay : 8.073 + Capture Clock Delay : 7.588 + Launch Clock Delay : 7.588 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_720p60Hz (rising edge) 0.000 0.000 r + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r clk 0.000 0.000 r clk (port) net (fanout=1) 0.000 0.000 clk clk_ibuf/I (GTP_INBUF) @@ -4360,80 +4324,107 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.130 5.526 rd3_clk + net (fanout=2825) 3.127 5.523 rd3_clk U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.089 5.615 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=1758) 2.458 8.073 nt_pix_clk - r sync_vg_100m/CLK (GTP_DFF_P) - - tco 0.329 8.402 r sync_vg_100m/Q (GTP_DFF_P) - net (fanout=2548) 2.954 11.356 sync_vg_100m - udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/I0 (GTP_LUT5) - td 0.185 11.541 r udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/Z (GTP_LUT5) - net (fanout=2) 0.553 12.094 udp_osd_inst/char_osd_inst/row_pixels_ready - udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/I1 (GTP_LUT3) - td 0.185 12.279 r udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/Z (GTP_LUT3) - net (fanout=10) 0.693 12.972 udp_osd_inst/char_osd_inst/char_next - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N97/I0 (GTP_LUT2) - td 0.185 13.157 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N97/Z (GTP_LUT2) - net (fanout=9) 0.745 13.902 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N97 - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N839/I1 (GTP_LUT2) - td 0.185 14.087 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N839/Z (GTP_LUT2) - net (fanout=3) 0.605 14.692 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N839 - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_15_3/I2 (GTP_LUT3) - td 0.185 14.877 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_15_3/Z (GTP_LUT3) - net (fanout=11) 0.771 15.648 udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N18404 - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_11_inv[1]/I0 (GTP_LUT5) - td 0.217 15.865 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_11_inv[1]/Z (GTP_LUT5) - net (fanout=1) 0.000 15.865 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847 [1] - r udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[1]/D (GTP_DFF_SE) + td 0.094 5.617 r U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=844) 1.971 7.588 zoom_clk + r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[15]/CLK (GTP_DFF_C) + + tco 0.329 7.917 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[15]/Q (GTP_DFF_C) + net (fanout=14) 0.802 8.719 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2 [15] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_16/I4 (GTP_LUT5) + td 0.283 9.002 f u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_16/Z (GTP_LUT5) + net (fanout=1) 0.464 9.466 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr [11] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_22/I0 (GTP_LUT5) + td 0.185 9.651 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_22/Z (GTP_LUT5) + net (fanout=10) 0.758 10.409 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr [7] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_14/I0 (GTP_LUT3) + td 0.185 10.594 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_14/Z (GTP_LUT3) + net (fanout=2) 0.553 11.147 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr [1] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_2/I2 (GTP_LUT5CARRY) + td 0.233 11.380 f u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_2/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 11.380 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [2] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_3/CIN (GTP_LUT5CARRY) + td 0.030 11.410 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_3/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 11.410 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [3] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_4/CIN (GTP_LUT5CARRY) + td 0.030 11.440 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_4/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 11.440 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [4] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_5/CIN (GTP_LUT5CARRY) + td 0.030 11.470 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_5/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 11.470 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [5] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_6/CIN (GTP_LUT5CARRY) + td 0.030 11.500 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_6/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 11.500 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [6] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_7/CIN (GTP_LUT5CARRY) + td 0.030 11.530 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_7/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 11.530 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [7] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_8/CIN (GTP_LUT5CARRY) + td 0.030 11.560 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_8/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 11.560 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [8] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_9/CIN (GTP_LUT5CARRY) + td 0.030 11.590 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_9/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 11.590 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [9] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_10/CIN (GTP_LUT5CARRY) + td 0.030 11.620 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_10/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 11.620 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [10] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_11/CIN (GTP_LUT5CARRY) + td 0.030 11.650 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_11/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 11.650 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [11] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_12/CIN (GTP_LUT5CARRY) + td 0.236 11.886 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_12/Z (GTP_LUT5CARRY) + net (fanout=1) 0.464 12.350 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/nb6 [11] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_6[11]/I0 (GTP_LUT3) + td 0.185 12.535 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_6[11]/Z (GTP_LUT3) + net (fanout=1) 0.000 12.535 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336 [11] + r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[11]/D (GTP_DFF_C) - Data arrival time 15.865 Logic Levels: 6 - Logic: 1.471ns(18.878%), Route: 6.321ns(81.122%) + Data arrival time 12.535 Logic Levels: 7 + Logic: 1.906ns(38.528%), Route: 3.041ns(61.472%) ---------------------------------------------------------------------------------------------------- - Clock clk_720p60Hz (rising edge) 13.473 13.473 r - clk 0.000 13.473 r clk (port) - net (fanout=1) 0.000 13.473 clk + Clock clk_1080p60Hz (rising edge) 6.736 6.736 r + clk 0.000 6.736 r clk (port) + net (fanout=1) 0.000 6.736 clk clk_ibuf/I (GTP_INBUF) - td 1.211 14.684 r clk_ibuf/O (GTP_INBUF) - net (fanout=1) 1.091 15.775 nt_clk + td 1.211 7.947 r clk_ibuf/O (GTP_INBUF) + net (fanout=1) 1.091 9.038 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 15.869 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.130 18.999 rd3_clk + td 0.094 9.132 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=2825) 3.127 12.259 rd3_clk U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.089 19.088 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=1758) 2.458 21.546 nt_pix_clk - r udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[1]/CLK (GTP_DFF_SE) - clock pessimism 0.000 21.546 - clock uncertainty -0.150 21.396 + td 0.094 12.353 r U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=844) 1.971 14.324 zoom_clk + r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[11]/CLK (GTP_DFF_C) + clock pessimism 0.000 14.324 + clock uncertainty -0.150 14.174 - Setup time 0.034 21.430 + Setup time 0.034 14.208 - Data required time 21.430 + Data required time 14.208 ---------------------------------------------------------------------------------------------------- - Data required time 21.430 - Data arrival time 15.865 + Data required time 14.208 + Data arrival time 12.535 ---------------------------------------------------------------------------------------------------- - Slack (MET) 5.565 + Slack (MET) 1.673 ==================================================================================================== ==================================================================================================== -Startpoint : sync_vg_100m/CLK (GTP_DFF_P) -Endpoint : udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[2]/D (GTP_DFF_SE) -Path Group : clk_720p60Hz +Startpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[15]/CLK (GTP_DFF_C) +Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/D (GTP_DFF_C) +Path Group : clk_1080p60Hz Path Type : max (slow corner) Path Class : sequential timing path Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 8.073 - Launch Clock Delay : 8.073 + Capture Clock Delay : 7.588 + Launch Clock Delay : 7.588 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_720p60Hz (rising edge) 0.000 0.000 r + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r clk 0.000 0.000 r clk (port) net (fanout=1) 0.000 0.000 clk clk_ibuf/I (GTP_INBUF) @@ -4441,80 +4432,98 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.130 5.526 rd3_clk + net (fanout=2825) 3.127 5.523 rd3_clk U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.089 5.615 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=1758) 2.458 8.073 nt_pix_clk - r sync_vg_100m/CLK (GTP_DFF_P) - - tco 0.329 8.402 r sync_vg_100m/Q (GTP_DFF_P) - net (fanout=2548) 2.954 11.356 sync_vg_100m - udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/I0 (GTP_LUT5) - td 0.185 11.541 r udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/Z (GTP_LUT5) - net (fanout=2) 0.553 12.094 udp_osd_inst/char_osd_inst/row_pixels_ready - udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/I1 (GTP_LUT3) - td 0.185 12.279 r udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/Z (GTP_LUT3) - net (fanout=10) 0.693 12.972 udp_osd_inst/char_osd_inst/char_next - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N97/I0 (GTP_LUT2) - td 0.185 13.157 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N97/Z (GTP_LUT2) - net (fanout=9) 0.745 13.902 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N97 - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N839/I1 (GTP_LUT2) - td 0.185 14.087 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N839/Z (GTP_LUT2) - net (fanout=3) 0.605 14.692 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N839 - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_15_3/I2 (GTP_LUT3) - td 0.185 14.877 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_15_3/Z (GTP_LUT3) - net (fanout=11) 0.771 15.648 udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N18404 - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_11_inv[2]/I0 (GTP_LUT5) - td 0.217 15.865 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_11_inv[2]/Z (GTP_LUT5) - net (fanout=1) 0.000 15.865 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847 [2] - r udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[2]/D (GTP_DFF_SE) - - Data arrival time 15.865 Logic Levels: 6 - Logic: 1.471ns(18.878%), Route: 6.321ns(81.122%) ----------------------------------------------------------------------------------------------------- - - Clock clk_720p60Hz (rising edge) 13.473 13.473 r - clk 0.000 13.473 r clk (port) - net (fanout=1) 0.000 13.473 clk - clk_ibuf/I (GTP_INBUF) - td 1.211 14.684 r clk_ibuf/O (GTP_INBUF) - net (fanout=1) 1.091 15.775 nt_clk - u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 15.869 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.130 18.999 rd3_clk + td 0.094 5.617 r U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=844) 1.971 7.588 zoom_clk + r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[15]/CLK (GTP_DFF_C) + + tco 0.329 7.917 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[15]/Q (GTP_DFF_C) + net (fanout=14) 0.802 8.719 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2 [15] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_16/I4 (GTP_LUT5) + td 0.283 9.002 f u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_16/Z (GTP_LUT5) + net (fanout=1) 0.464 9.466 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr [11] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_22/I0 (GTP_LUT5) + td 0.185 9.651 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_22/Z (GTP_LUT5) + net (fanout=10) 0.758 10.409 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr [7] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_32/I0 (GTP_LUT4) + td 0.185 10.594 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_32/Z (GTP_LUT4) + net (fanout=2) 0.553 11.147 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr [0] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.eq_0/I1 (GTP_LUT5CARRY) + td 0.298 11.445 f u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.eq_0/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 11.445 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.co [0] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.eq_1/CIN (GTP_LUT5CARRY) + td 0.030 11.475 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.eq_1/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 11.475 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.co [2] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.eq_2/CIN (GTP_LUT5CARRY) + td 0.030 11.505 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.eq_2/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 11.505 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.co [4] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.eq_3/CIN (GTP_LUT5CARRY) + td 0.030 11.535 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.eq_3/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 11.535 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.co [6] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.eq_4/CIN (GTP_LUT5CARRY) + td 0.030 11.565 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.eq_4/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 11.565 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.co [8] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.eq_5/CIN (GTP_LUT5CARRY) + td 0.030 11.595 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.eq_5/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 11.595 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.co [10] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.eq_6/CIN (GTP_LUT5CARRY) + td 0.030 11.625 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.eq_6/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 11.625 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.co [12] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.eq_7/CIN (GTP_LUT5CARRY) + td 0.236 11.861 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.eq_7/Z (GTP_LUT5CARRY) + net (fanout=1) 0.464 12.325 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207 + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N208/I1 (GTP_LUT5) + td 0.185 12.510 r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N208/Z (GTP_LUT5) + net (fanout=1) 0.000 12.510 u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N208 + r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/D (GTP_DFF_C) + + Data arrival time 12.510 Logic Levels: 6 + Logic: 1.881ns(38.216%), Route: 3.041ns(61.784%) +---------------------------------------------------------------------------------------------------- + + Clock clk_1080p60Hz (rising edge) 6.736 6.736 r + clk 0.000 6.736 r clk (port) + net (fanout=1) 0.000 6.736 clk + clk_ibuf/I (GTP_INBUF) + td 1.211 7.947 r clk_ibuf/O (GTP_INBUF) + net (fanout=1) 1.091 9.038 nt_clk + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.094 9.132 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=2825) 3.127 12.259 rd3_clk U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.089 19.088 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=1758) 2.458 21.546 nt_pix_clk - r udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[2]/CLK (GTP_DFF_SE) - clock pessimism 0.000 21.546 - clock uncertainty -0.150 21.396 + td 0.094 12.353 r U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=844) 1.971 14.324 zoom_clk + r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/CLK (GTP_DFF_C) + clock pessimism 0.000 14.324 + clock uncertainty -0.150 14.174 - Setup time 0.034 21.430 + Setup time 0.034 14.208 - Data required time 21.430 + Data required time 14.208 ---------------------------------------------------------------------------------------------------- - Data required time 21.430 - Data arrival time 15.865 + Data required time 14.208 + Data arrival time 12.510 ---------------------------------------------------------------------------------------------------- - Slack (MET) 5.565 + Slack (MET) 1.698 ==================================================================================================== ==================================================================================================== -Startpoint : udp_osd_inst/char_buf_writer_inst/ram_din[0]/CLK (GTP_DFF_RE) -Endpoint : udp_osd_inst/char_ram/U_ipml_sdpram_async_ram2048x8_2clk/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/DIA[0] (GTP_DRM18K) -Path Group : clk_720p60Hz +Startpoint : u_zoom_image/imag_addr1[0]/CLK (GTP_DFF) +Endpoint : u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/DIA[0] (GTP_DRM9K) +Path Group : clk_1080p60Hz Path Type : min (slow corner) Path Class : sequential timing path Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 8.587 - Launch Clock Delay : 8.073 + Capture Clock Delay : 8.102 + Launch Clock Delay : 7.588 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_720p60Hz (rising edge) 0.000 0.000 r + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r clk 0.000 0.000 r clk (port) net (fanout=1) 0.000 0.000 clk clk_ibuf/I (GTP_INBUF) @@ -4522,21 +4531,21 @@ Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.130 5.526 rd3_clk + net (fanout=2825) 3.127 5.523 rd3_clk U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.089 5.615 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=1758) 2.458 8.073 nt_pix_clk - r udp_osd_inst/char_buf_writer_inst/ram_din[0]/CLK (GTP_DFF_RE) + td 0.094 5.617 r U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=844) 1.971 7.588 zoom_clk + r u_zoom_image/imag_addr1[0]/CLK (GTP_DFF) - tco 0.323 8.396 f udp_osd_inst/char_buf_writer_inst/ram_din[0]/Q (GTP_DFF_RE) - net (fanout=1) 0.978 9.374 udp_osd_inst/ram_din [0] - f udp_osd_inst/char_ram/U_ipml_sdpram_async_ram2048x8_2clk/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/DIA[0] (GTP_DRM18K) + tco 0.323 7.911 f u_zoom_image/imag_addr1[0]/Q (GTP_DFF) + net (fanout=1) 0.978 8.889 zoom_image_addr[0] + f u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/DIA[0] (GTP_DRM9K) - Data arrival time 9.374 Logic Levels: 0 + Data arrival time 8.889 Logic Levels: 0 Logic: 0.323ns(24.827%), Route: 0.978ns(75.173%) ---------------------------------------------------------------------------------------------------- - Clock clk_720p60Hz (rising edge) 0.000 0.000 r + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r clk 0.000 0.000 r clk (port) net (fanout=1) 0.000 0.000 clk clk_ibuf/I (GTP_INBUF) @@ -4544,40 +4553,40 @@ Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.130 5.526 rd3_clk + net (fanout=2825) 3.127 5.523 rd3_clk U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.089 5.615 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=1758) 2.972 8.587 nt_pix_clk - r udp_osd_inst/char_ram/U_ipml_sdpram_async_ram2048x8_2clk/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (GTP_DRM18K) - clock pessimism 0.000 8.587 - clock uncertainty 0.000 8.587 + td 0.094 5.617 r U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=844) 2.485 8.102 zoom_clk + r u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/CLKA (GTP_DRM9K) + clock pessimism 0.000 8.102 + clock uncertainty 0.000 8.102 - Hold time 0.137 8.724 + Hold time 0.131 8.233 - Data required time 8.724 + Data required time 8.233 ---------------------------------------------------------------------------------------------------- - Data required time 8.724 - Data arrival time 9.374 + Data required time 8.233 + Data arrival time 8.889 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.650 + Slack (MET) 0.656 ==================================================================================================== ==================================================================================================== -Startpoint : udp_osd_inst/char_buf_writer_inst/ram_din[1]/CLK (GTP_DFF_RE) -Endpoint : udp_osd_inst/char_ram/U_ipml_sdpram_async_ram2048x8_2clk/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/DIA[1] (GTP_DRM18K) -Path Group : clk_720p60Hz +Startpoint : u_zoom_image/imag_addr1[1]/CLK (GTP_DFF) +Endpoint : u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/DIA[1] (GTP_DRM9K) +Path Group : clk_1080p60Hz Path Type : min (slow corner) Path Class : sequential timing path Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 8.587 - Launch Clock Delay : 8.073 + Capture Clock Delay : 8.102 + Launch Clock Delay : 7.588 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_720p60Hz (rising edge) 0.000 0.000 r + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r clk 0.000 0.000 r clk (port) net (fanout=1) 0.000 0.000 clk clk_ibuf/I (GTP_INBUF) @@ -4585,21 +4594,21 @@ Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.130 5.526 rd3_clk + net (fanout=2825) 3.127 5.523 rd3_clk U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.089 5.615 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=1758) 2.458 8.073 nt_pix_clk - r udp_osd_inst/char_buf_writer_inst/ram_din[1]/CLK (GTP_DFF_RE) + td 0.094 5.617 r U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=844) 1.971 7.588 zoom_clk + r u_zoom_image/imag_addr1[1]/CLK (GTP_DFF) - tco 0.323 8.396 f udp_osd_inst/char_buf_writer_inst/ram_din[1]/Q (GTP_DFF_RE) - net (fanout=1) 0.978 9.374 udp_osd_inst/ram_din [1] - f udp_osd_inst/char_ram/U_ipml_sdpram_async_ram2048x8_2clk/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/DIA[1] (GTP_DRM18K) + tco 0.323 7.911 f u_zoom_image/imag_addr1[1]/Q (GTP_DFF) + net (fanout=1) 0.978 8.889 zoom_image_addr[1] + f u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/DIA[1] (GTP_DRM9K) - Data arrival time 9.374 Logic Levels: 0 + Data arrival time 8.889 Logic Levels: 0 Logic: 0.323ns(24.827%), Route: 0.978ns(75.173%) ---------------------------------------------------------------------------------------------------- - Clock clk_720p60Hz (rising edge) 0.000 0.000 r + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r clk 0.000 0.000 r clk (port) net (fanout=1) 0.000 0.000 clk clk_ibuf/I (GTP_INBUF) @@ -4607,40 +4616,40 @@ Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.130 5.526 rd3_clk + net (fanout=2825) 3.127 5.523 rd3_clk U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.089 5.615 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=1758) 2.972 8.587 nt_pix_clk - r udp_osd_inst/char_ram/U_ipml_sdpram_async_ram2048x8_2clk/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (GTP_DRM18K) - clock pessimism 0.000 8.587 - clock uncertainty 0.000 8.587 + td 0.094 5.617 r U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=844) 2.485 8.102 zoom_clk + r u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/CLKA (GTP_DRM9K) + clock pessimism 0.000 8.102 + clock uncertainty 0.000 8.102 - Hold time 0.137 8.724 + Hold time 0.131 8.233 - Data required time 8.724 + Data required time 8.233 ---------------------------------------------------------------------------------------------------- - Data required time 8.724 - Data arrival time 9.374 + Data required time 8.233 + Data arrival time 8.889 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.650 + Slack (MET) 0.656 ==================================================================================================== ==================================================================================================== -Startpoint : udp_osd_inst/char_buf_writer_inst/ram_din[2]/CLK (GTP_DFF_RE) -Endpoint : udp_osd_inst/char_ram/U_ipml_sdpram_async_ram2048x8_2clk/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/DIA[2] (GTP_DRM18K) -Path Group : clk_720p60Hz +Startpoint : u_zoom_image/imag_addr1[2]/CLK (GTP_DFF) +Endpoint : u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/DIA[2] (GTP_DRM9K) +Path Group : clk_1080p60Hz Path Type : min (slow corner) Path Class : sequential timing path Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 8.587 - Launch Clock Delay : 8.073 + Capture Clock Delay : 8.102 + Launch Clock Delay : 7.588 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_720p60Hz (rising edge) 0.000 0.000 r + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r clk 0.000 0.000 r clk (port) net (fanout=1) 0.000 0.000 clk clk_ibuf/I (GTP_INBUF) @@ -4648,21 +4657,21 @@ Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.130 5.526 rd3_clk + net (fanout=2825) 3.127 5.523 rd3_clk U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.089 5.615 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=1758) 2.458 8.073 nt_pix_clk - r udp_osd_inst/char_buf_writer_inst/ram_din[2]/CLK (GTP_DFF_RE) + td 0.094 5.617 r U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=844) 1.971 7.588 zoom_clk + r u_zoom_image/imag_addr1[2]/CLK (GTP_DFF) - tco 0.323 8.396 f udp_osd_inst/char_buf_writer_inst/ram_din[2]/Q (GTP_DFF_RE) - net (fanout=1) 0.978 9.374 udp_osd_inst/ram_din [2] - f udp_osd_inst/char_ram/U_ipml_sdpram_async_ram2048x8_2clk/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/DIA[2] (GTP_DRM18K) + tco 0.323 7.911 f u_zoom_image/imag_addr1[2]/Q (GTP_DFF) + net (fanout=1) 0.978 8.889 zoom_image_addr[2] + f u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/DIA[2] (GTP_DRM9K) - Data arrival time 9.374 Logic Levels: 0 + Data arrival time 8.889 Logic Levels: 0 Logic: 0.323ns(24.827%), Route: 0.978ns(75.173%) ---------------------------------------------------------------------------------------------------- - Clock clk_720p60Hz (rising edge) 0.000 0.000 r + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r clk 0.000 0.000 r clk (port) net (fanout=1) 0.000 0.000 clk clk_ibuf/I (GTP_INBUF) @@ -4670,71 +4679,503 @@ Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.130 5.526 rd3_clk + net (fanout=2825) 3.127 5.523 rd3_clk U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.089 5.615 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=1758) 2.972 8.587 nt_pix_clk - r udp_osd_inst/char_ram/U_ipml_sdpram_async_ram2048x8_2clk/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (GTP_DRM18K) - clock pessimism 0.000 8.587 - clock uncertainty 0.000 8.587 + td 0.094 5.617 r U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=844) 2.485 8.102 zoom_clk + r u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/CLKA (GTP_DRM9K) + clock pessimism 0.000 8.102 + clock uncertainty 0.000 8.102 - Hold time 0.137 8.724 + Hold time 0.131 8.233 - Data required time 8.724 + Data required time 8.233 ---------------------------------------------------------------------------------------------------- - Data required time 8.724 - Data arrival time 9.374 + Data required time 8.233 + Data arrival time 8.889 ---------------------------------------------------------------------------------------------------- - Slack (MET) 0.650 + Slack (MET) 0.656 ==================================================================================================== ==================================================================================================== -Startpoint : u_ov5640/coms1_reg_config/reg_data/CLKB (GTP_DRM18K) -Endpoint : u_ov5640/coms1_reg_config/u1/reg_sdat/D (GTP_DFF_S) -Path Group : clk_20k +Startpoint : sync_vg_100m/CLK (GTP_DFF_P) +Endpoint : udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[0]/D (GTP_DFF_SE) +Path Group : clk_720p60Hz Path Type : max (slow corner) Path Class : sequential timing path Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 6.243 - Launch Clock Delay : 6.243 + Capture Clock Delay : 8.070 + Launch Clock Delay : 8.070 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource ---------------------------------------------------------------------------------------------------- - Clock clk_20k (rising edge) 0.000 0.000 r + Clock clk_720p60Hz (rising edge) 0.000 0.000 r clk 0.000 0.000 r clk (port) net (fanout=1) 0.000 0.000 clk clk_ibuf/I (GTP_INBUF) td 1.211 1.211 r clk_ibuf/O (GTP_INBUF) net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.098 2.400 r u_sys_pll/u_pll_e3/CLKOUT3 (GTP_PLL_E3) - net (fanout=26) 0.713 3.113 clk_25m - r u_ov5640/coms1_reg_config/clk_20k_regdiv/CLK (GTP_DFF_RE) - tco 0.329 3.442 r u_ov5640/coms1_reg_config/clk_20k_regdiv/Q (GTP_DFF_RE) - net (fanout=3) 0.605 4.047 u_ov5640/coms1_reg_config/clk_20k_regdiv - u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/CLKIN (GTP_CLKBUFG) - td 0.000 4.047 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/CLKOUT (GTP_CLKBUFG) - net (fanout=25) 2.196 6.243 u_ov5640/coms1_reg_config/clock_20k - r u_ov5640/coms1_reg_config/reg_data/CLKB (GTP_DRM18K) - - tco 2.024 8.267 f u_ov5640/coms1_reg_config/reg_data/DOB[7] (GTP_DRM18K) - net (fanout=1) 0.903 9.170 u_ov5640/coms1_reg_config/i2c_data [23] - u_ov5640/coms1_reg_config/u1/N267_29/I1 (GTP_LUT5M) - td 0.365 9.535 f u_ov5640/coms1_reg_config/u1/N267_29/Z (GTP_LUT5M) - net (fanout=1) 0.464 9.999 u_ov5640/coms1_reg_config/u1/_N25461 - u_ov5640/coms1_reg_config/u1/N267_35/I0 (GTP_LUT5) - td 0.185 10.184 r u_ov5640/coms1_reg_config/u1/N267_35/Z (GTP_LUT5) - net (fanout=1) 0.464 10.648 u_ov5640/coms1_reg_config/u1/_N25467 - u_ov5640/coms1_reg_config/u1/N267_36/ID (GTP_LUT5M) - td 0.265 10.913 f u_ov5640/coms1_reg_config/u1/N267_36/Z (GTP_LUT5M) - net (fanout=1) 0.464 11.377 u_ov5640/coms1_reg_config/u1/_N25468 - u_ov5640/coms1_reg_config/u1/reg_sdat_ce_mux/ID (GTP_LUT5M) - td 0.265 11.642 f u_ov5640/coms1_reg_config/u1/reg_sdat_ce_mux/Z (GTP_LUT5M) - net (fanout=1) 0.000 11.642 u_ov5640/coms1_reg_config/u1/_N103476 - f u_ov5640/coms1_reg_config/u1/reg_sdat/D (GTP_DFF_S) + td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=2825) 3.127 5.523 rd3_clk + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.089 5.612 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + net (fanout=1758) 2.458 8.070 nt_pix_clk + r sync_vg_100m/CLK (GTP_DFF_P) + + tco 0.329 8.399 r sync_vg_100m/Q (GTP_DFF_P) + net (fanout=2548) 2.954 11.353 sync_vg_100m + udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/I0 (GTP_LUT5) + td 0.185 11.538 r udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/Z (GTP_LUT5) + net (fanout=2) 0.553 12.091 udp_osd_inst/char_osd_inst/row_pixels_ready + udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/I1 (GTP_LUT3) + td 0.185 12.276 r udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/Z (GTP_LUT3) + net (fanout=16) 0.782 13.058 udp_osd_inst/char_osd_inst/char_next + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N358_5/I0 (GTP_LUT3) + td 0.185 13.243 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N358_5/Z (GTP_LUT3) + net (fanout=5) 0.670 13.913 udp_osd_inst/_N97124 + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_9/I0 (GTP_LUT5) + td 0.185 14.098 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_9/Z (GTP_LUT5) + net (fanout=1) 0.464 14.562 udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N18403 + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_15_3/I1 (GTP_LUT5M) + td 0.300 14.862 f udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_15_3/Z (GTP_LUT5M) + net (fanout=11) 0.771 15.633 udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N18404 + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_11_inv[0]/I0 (GTP_LUT5) + td 0.185 15.818 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_11_inv[0]/Z (GTP_LUT5) + net (fanout=1) 0.000 15.818 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847 [0] + r udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[0]/D (GTP_DFF_SE) + + Data arrival time 15.818 Logic Levels: 6 + Logic: 1.554ns(20.057%), Route: 6.194ns(79.943%) +---------------------------------------------------------------------------------------------------- + + Clock clk_720p60Hz (rising edge) 13.473 13.473 r + clk 0.000 13.473 r clk (port) + net (fanout=1) 0.000 13.473 clk + clk_ibuf/I (GTP_INBUF) + td 1.211 14.684 r clk_ibuf/O (GTP_INBUF) + net (fanout=1) 1.091 15.775 nt_clk + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.094 15.869 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=2825) 3.127 18.996 rd3_clk + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.089 19.085 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + net (fanout=1758) 2.458 21.543 nt_pix_clk + r udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[0]/CLK (GTP_DFF_SE) + clock pessimism 0.000 21.543 + clock uncertainty -0.150 21.393 + + Setup time 0.034 21.427 + + Data required time 21.427 +---------------------------------------------------------------------------------------------------- + Data required time 21.427 + Data arrival time 15.818 +---------------------------------------------------------------------------------------------------- + Slack (MET) 5.609 +==================================================================================================== + +==================================================================================================== + +Startpoint : sync_vg_100m/CLK (GTP_DFF_P) +Endpoint : udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[1]/D (GTP_DFF_SE) +Path Group : clk_720p60Hz +Path Type : max (slow corner) +Path Class : sequential timing path +Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 8.070 + Launch Clock Delay : 8.070 + Clock Pessimism Removal : 0.000 + + Location Delay Type Incr Path Logical Resource +---------------------------------------------------------------------------------------------------- + + Clock clk_720p60Hz (rising edge) 0.000 0.000 r + clk 0.000 0.000 r clk (port) + net (fanout=1) 0.000 0.000 clk + clk_ibuf/I (GTP_INBUF) + td 1.211 1.211 r clk_ibuf/O (GTP_INBUF) + net (fanout=1) 1.091 2.302 nt_clk + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=2825) 3.127 5.523 rd3_clk + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.089 5.612 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + net (fanout=1758) 2.458 8.070 nt_pix_clk + r sync_vg_100m/CLK (GTP_DFF_P) + + tco 0.329 8.399 r sync_vg_100m/Q (GTP_DFF_P) + net (fanout=2548) 2.954 11.353 sync_vg_100m + udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/I0 (GTP_LUT5) + td 0.185 11.538 r udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/Z (GTP_LUT5) + net (fanout=2) 0.553 12.091 udp_osd_inst/char_osd_inst/row_pixels_ready + udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/I1 (GTP_LUT3) + td 0.185 12.276 r udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/Z (GTP_LUT3) + net (fanout=16) 0.782 13.058 udp_osd_inst/char_osd_inst/char_next + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N358_5/I0 (GTP_LUT3) + td 0.185 13.243 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N358_5/Z (GTP_LUT3) + net (fanout=5) 0.670 13.913 udp_osd_inst/_N97124 + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_9/I0 (GTP_LUT5) + td 0.185 14.098 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_9/Z (GTP_LUT5) + net (fanout=1) 0.464 14.562 udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N18403 + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_15_3/I1 (GTP_LUT5M) + td 0.300 14.862 f udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_15_3/Z (GTP_LUT5M) + net (fanout=11) 0.771 15.633 udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N18404 + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_11_inv[1]/I0 (GTP_LUT5) + td 0.185 15.818 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_11_inv[1]/Z (GTP_LUT5) + net (fanout=1) 0.000 15.818 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847 [1] + r udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[1]/D (GTP_DFF_SE) + + Data arrival time 15.818 Logic Levels: 6 + Logic: 1.554ns(20.057%), Route: 6.194ns(79.943%) +---------------------------------------------------------------------------------------------------- + + Clock clk_720p60Hz (rising edge) 13.473 13.473 r + clk 0.000 13.473 r clk (port) + net (fanout=1) 0.000 13.473 clk + clk_ibuf/I (GTP_INBUF) + td 1.211 14.684 r clk_ibuf/O (GTP_INBUF) + net (fanout=1) 1.091 15.775 nt_clk + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.094 15.869 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=2825) 3.127 18.996 rd3_clk + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.089 19.085 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + net (fanout=1758) 2.458 21.543 nt_pix_clk + r udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[1]/CLK (GTP_DFF_SE) + clock pessimism 0.000 21.543 + clock uncertainty -0.150 21.393 + + Setup time 0.034 21.427 + + Data required time 21.427 +---------------------------------------------------------------------------------------------------- + Data required time 21.427 + Data arrival time 15.818 +---------------------------------------------------------------------------------------------------- + Slack (MET) 5.609 +==================================================================================================== + +==================================================================================================== + +Startpoint : sync_vg_100m/CLK (GTP_DFF_P) +Endpoint : udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[2]/D (GTP_DFF_SE) +Path Group : clk_720p60Hz +Path Type : max (slow corner) +Path Class : sequential timing path +Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 8.070 + Launch Clock Delay : 8.070 + Clock Pessimism Removal : 0.000 + + Location Delay Type Incr Path Logical Resource +---------------------------------------------------------------------------------------------------- + + Clock clk_720p60Hz (rising edge) 0.000 0.000 r + clk 0.000 0.000 r clk (port) + net (fanout=1) 0.000 0.000 clk + clk_ibuf/I (GTP_INBUF) + td 1.211 1.211 r clk_ibuf/O (GTP_INBUF) + net (fanout=1) 1.091 2.302 nt_clk + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=2825) 3.127 5.523 rd3_clk + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.089 5.612 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + net (fanout=1758) 2.458 8.070 nt_pix_clk + r sync_vg_100m/CLK (GTP_DFF_P) + + tco 0.329 8.399 r sync_vg_100m/Q (GTP_DFF_P) + net (fanout=2548) 2.954 11.353 sync_vg_100m + udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/I0 (GTP_LUT5) + td 0.185 11.538 r udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/Z (GTP_LUT5) + net (fanout=2) 0.553 12.091 udp_osd_inst/char_osd_inst/row_pixels_ready + udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/I1 (GTP_LUT3) + td 0.185 12.276 r udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/Z (GTP_LUT3) + net (fanout=16) 0.782 13.058 udp_osd_inst/char_osd_inst/char_next + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N358_5/I0 (GTP_LUT3) + td 0.185 13.243 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N358_5/Z (GTP_LUT3) + net (fanout=5) 0.670 13.913 udp_osd_inst/_N97124 + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_9/I0 (GTP_LUT5) + td 0.185 14.098 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_9/Z (GTP_LUT5) + net (fanout=1) 0.464 14.562 udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N18403 + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_15_3/I1 (GTP_LUT5M) + td 0.300 14.862 f udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_15_3/Z (GTP_LUT5M) + net (fanout=11) 0.771 15.633 udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N18404 + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_11_inv[2]/I0 (GTP_LUT5) + td 0.185 15.818 r udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_11_inv[2]/Z (GTP_LUT5) + net (fanout=1) 0.000 15.818 udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847 [2] + r udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[2]/D (GTP_DFF_SE) + + Data arrival time 15.818 Logic Levels: 6 + Logic: 1.554ns(20.057%), Route: 6.194ns(79.943%) +---------------------------------------------------------------------------------------------------- + + Clock clk_720p60Hz (rising edge) 13.473 13.473 r + clk 0.000 13.473 r clk (port) + net (fanout=1) 0.000 13.473 clk + clk_ibuf/I (GTP_INBUF) + td 1.211 14.684 r clk_ibuf/O (GTP_INBUF) + net (fanout=1) 1.091 15.775 nt_clk + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.094 15.869 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=2825) 3.127 18.996 rd3_clk + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.089 19.085 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + net (fanout=1758) 2.458 21.543 nt_pix_clk + r udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[2]/CLK (GTP_DFF_SE) + clock pessimism 0.000 21.543 + clock uncertainty -0.150 21.393 + + Setup time 0.034 21.427 + + Data required time 21.427 +---------------------------------------------------------------------------------------------------- + Data required time 21.427 + Data arrival time 15.818 +---------------------------------------------------------------------------------------------------- + Slack (MET) 5.609 +==================================================================================================== + +==================================================================================================== + +Startpoint : udp_osd_inst/char_buf_writer_inst/ram_din[0]/CLK (GTP_DFF_RE) +Endpoint : udp_osd_inst/char_ram/U_ipml_sdpram_async_ram2048x8_2clk/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/DIA[0] (GTP_DRM18K) +Path Group : clk_720p60Hz +Path Type : min (slow corner) +Path Class : sequential timing path +Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 8.584 + Launch Clock Delay : 8.070 + Clock Pessimism Removal : 0.000 + + Location Delay Type Incr Path Logical Resource +---------------------------------------------------------------------------------------------------- + + Clock clk_720p60Hz (rising edge) 0.000 0.000 r + clk 0.000 0.000 r clk (port) + net (fanout=1) 0.000 0.000 clk + clk_ibuf/I (GTP_INBUF) + td 1.211 1.211 r clk_ibuf/O (GTP_INBUF) + net (fanout=1) 1.091 2.302 nt_clk + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=2825) 3.127 5.523 rd3_clk + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.089 5.612 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + net (fanout=1758) 2.458 8.070 nt_pix_clk + r udp_osd_inst/char_buf_writer_inst/ram_din[0]/CLK (GTP_DFF_RE) + + tco 0.323 8.393 f udp_osd_inst/char_buf_writer_inst/ram_din[0]/Q (GTP_DFF_RE) + net (fanout=1) 0.978 9.371 udp_osd_inst/ram_din [0] + f udp_osd_inst/char_ram/U_ipml_sdpram_async_ram2048x8_2clk/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/DIA[0] (GTP_DRM18K) + + Data arrival time 9.371 Logic Levels: 0 + Logic: 0.323ns(24.827%), Route: 0.978ns(75.173%) +---------------------------------------------------------------------------------------------------- + + Clock clk_720p60Hz (rising edge) 0.000 0.000 r + clk 0.000 0.000 r clk (port) + net (fanout=1) 0.000 0.000 clk + clk_ibuf/I (GTP_INBUF) + td 1.211 1.211 r clk_ibuf/O (GTP_INBUF) + net (fanout=1) 1.091 2.302 nt_clk + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=2825) 3.127 5.523 rd3_clk + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.089 5.612 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + net (fanout=1758) 2.972 8.584 nt_pix_clk + r udp_osd_inst/char_ram/U_ipml_sdpram_async_ram2048x8_2clk/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (GTP_DRM18K) + clock pessimism 0.000 8.584 + clock uncertainty 0.000 8.584 + + Hold time 0.137 8.721 + + Data required time 8.721 +---------------------------------------------------------------------------------------------------- + Data required time 8.721 + Data arrival time 9.371 +---------------------------------------------------------------------------------------------------- + Slack (MET) 0.650 +==================================================================================================== + +==================================================================================================== + +Startpoint : udp_osd_inst/char_buf_writer_inst/ram_din[1]/CLK (GTP_DFF_RE) +Endpoint : udp_osd_inst/char_ram/U_ipml_sdpram_async_ram2048x8_2clk/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/DIA[1] (GTP_DRM18K) +Path Group : clk_720p60Hz +Path Type : min (slow corner) +Path Class : sequential timing path +Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 8.584 + Launch Clock Delay : 8.070 + Clock Pessimism Removal : 0.000 + + Location Delay Type Incr Path Logical Resource +---------------------------------------------------------------------------------------------------- + + Clock clk_720p60Hz (rising edge) 0.000 0.000 r + clk 0.000 0.000 r clk (port) + net (fanout=1) 0.000 0.000 clk + clk_ibuf/I (GTP_INBUF) + td 1.211 1.211 r clk_ibuf/O (GTP_INBUF) + net (fanout=1) 1.091 2.302 nt_clk + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=2825) 3.127 5.523 rd3_clk + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.089 5.612 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + net (fanout=1758) 2.458 8.070 nt_pix_clk + r udp_osd_inst/char_buf_writer_inst/ram_din[1]/CLK (GTP_DFF_RE) + + tco 0.323 8.393 f udp_osd_inst/char_buf_writer_inst/ram_din[1]/Q (GTP_DFF_RE) + net (fanout=1) 0.978 9.371 udp_osd_inst/ram_din [1] + f udp_osd_inst/char_ram/U_ipml_sdpram_async_ram2048x8_2clk/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/DIA[1] (GTP_DRM18K) + + Data arrival time 9.371 Logic Levels: 0 + Logic: 0.323ns(24.827%), Route: 0.978ns(75.173%) +---------------------------------------------------------------------------------------------------- + + Clock clk_720p60Hz (rising edge) 0.000 0.000 r + clk 0.000 0.000 r clk (port) + net (fanout=1) 0.000 0.000 clk + clk_ibuf/I (GTP_INBUF) + td 1.211 1.211 r clk_ibuf/O (GTP_INBUF) + net (fanout=1) 1.091 2.302 nt_clk + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=2825) 3.127 5.523 rd3_clk + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.089 5.612 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + net (fanout=1758) 2.972 8.584 nt_pix_clk + r udp_osd_inst/char_ram/U_ipml_sdpram_async_ram2048x8_2clk/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (GTP_DRM18K) + clock pessimism 0.000 8.584 + clock uncertainty 0.000 8.584 + + Hold time 0.137 8.721 + + Data required time 8.721 +---------------------------------------------------------------------------------------------------- + Data required time 8.721 + Data arrival time 9.371 +---------------------------------------------------------------------------------------------------- + Slack (MET) 0.650 +==================================================================================================== + +==================================================================================================== + +Startpoint : udp_osd_inst/char_buf_writer_inst/ram_din[2]/CLK (GTP_DFF_RE) +Endpoint : udp_osd_inst/char_ram/U_ipml_sdpram_async_ram2048x8_2clk/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/DIA[2] (GTP_DRM18K) +Path Group : clk_720p60Hz +Path Type : min (slow corner) +Path Class : sequential timing path +Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 8.584 + Launch Clock Delay : 8.070 + Clock Pessimism Removal : 0.000 + + Location Delay Type Incr Path Logical Resource +---------------------------------------------------------------------------------------------------- + + Clock clk_720p60Hz (rising edge) 0.000 0.000 r + clk 0.000 0.000 r clk (port) + net (fanout=1) 0.000 0.000 clk + clk_ibuf/I (GTP_INBUF) + td 1.211 1.211 r clk_ibuf/O (GTP_INBUF) + net (fanout=1) 1.091 2.302 nt_clk + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=2825) 3.127 5.523 rd3_clk + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.089 5.612 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + net (fanout=1758) 2.458 8.070 nt_pix_clk + r udp_osd_inst/char_buf_writer_inst/ram_din[2]/CLK (GTP_DFF_RE) + + tco 0.323 8.393 f udp_osd_inst/char_buf_writer_inst/ram_din[2]/Q (GTP_DFF_RE) + net (fanout=1) 0.978 9.371 udp_osd_inst/ram_din [2] + f udp_osd_inst/char_ram/U_ipml_sdpram_async_ram2048x8_2clk/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/DIA[2] (GTP_DRM18K) + + Data arrival time 9.371 Logic Levels: 0 + Logic: 0.323ns(24.827%), Route: 0.978ns(75.173%) +---------------------------------------------------------------------------------------------------- + + Clock clk_720p60Hz (rising edge) 0.000 0.000 r + clk 0.000 0.000 r clk (port) + net (fanout=1) 0.000 0.000 clk + clk_ibuf/I (GTP_INBUF) + td 1.211 1.211 r clk_ibuf/O (GTP_INBUF) + net (fanout=1) 1.091 2.302 nt_clk + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=2825) 3.127 5.523 rd3_clk + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.089 5.612 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + net (fanout=1758) 2.972 8.584 nt_pix_clk + r udp_osd_inst/char_ram/U_ipml_sdpram_async_ram2048x8_2clk/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (GTP_DRM18K) + clock pessimism 0.000 8.584 + clock uncertainty 0.000 8.584 + + Hold time 0.137 8.721 + + Data required time 8.721 +---------------------------------------------------------------------------------------------------- + Data required time 8.721 + Data arrival time 9.371 +---------------------------------------------------------------------------------------------------- + Slack (MET) 0.650 +==================================================================================================== + +==================================================================================================== + +Startpoint : u_ov5640/coms1_reg_config/reg_data/CLKB (GTP_DRM18K) +Endpoint : u_ov5640/coms1_reg_config/u1/reg_sdat/D (GTP_DFF_S) +Path Group : clk_20k +Path Type : max (slow corner) +Path Class : sequential timing path +Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 6.243 + Launch Clock Delay : 6.243 + Clock Pessimism Removal : 0.000 + + Location Delay Type Incr Path Logical Resource +---------------------------------------------------------------------------------------------------- + + Clock clk_20k (rising edge) 0.000 0.000 r + clk 0.000 0.000 r clk (port) + net (fanout=1) 0.000 0.000 clk + clk_ibuf/I (GTP_INBUF) + td 1.211 1.211 r clk_ibuf/O (GTP_INBUF) + net (fanout=1) 1.091 2.302 nt_clk + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.098 2.400 r u_sys_pll/u_pll_e3/CLKOUT3 (GTP_PLL_E3) + net (fanout=26) 0.713 3.113 clk_25m + r u_ov5640/coms1_reg_config/clk_20k_regdiv/CLK (GTP_DFF_RE) + tco 0.329 3.442 r u_ov5640/coms1_reg_config/clk_20k_regdiv/Q (GTP_DFF_RE) + net (fanout=3) 0.605 4.047 u_ov5640/coms1_reg_config/clk_20k_regdiv + u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/CLKIN (GTP_CLKBUFG) + td 0.000 4.047 r u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/CLKOUT (GTP_CLKBUFG) + net (fanout=25) 2.196 6.243 u_ov5640/coms1_reg_config/clock_20k + r u_ov5640/coms1_reg_config/reg_data/CLKB (GTP_DRM18K) + + tco 2.024 8.267 f u_ov5640/coms1_reg_config/reg_data/DOB[7] (GTP_DRM18K) + net (fanout=1) 0.903 9.170 u_ov5640/coms1_reg_config/i2c_data [23] + u_ov5640/coms1_reg_config/u1/N267_29/I1 (GTP_LUT5M) + td 0.365 9.535 f u_ov5640/coms1_reg_config/u1/N267_29/Z (GTP_LUT5M) + net (fanout=1) 0.464 9.999 u_ov5640/coms1_reg_config/u1/_N25311 + u_ov5640/coms1_reg_config/u1/N267_35/I0 (GTP_LUT5) + td 0.185 10.184 r u_ov5640/coms1_reg_config/u1/N267_35/Z (GTP_LUT5) + net (fanout=1) 0.464 10.648 u_ov5640/coms1_reg_config/u1/_N25317 + u_ov5640/coms1_reg_config/u1/N267_36/ID (GTP_LUT5M) + td 0.265 10.913 f u_ov5640/coms1_reg_config/u1/N267_36/Z (GTP_LUT5M) + net (fanout=1) 0.464 11.377 u_ov5640/coms1_reg_config/u1/_N25318 + u_ov5640/coms1_reg_config/u1/reg_sdat_ce_mux/ID (GTP_LUT5M) + td 0.265 11.642 f u_ov5640/coms1_reg_config/u1/reg_sdat_ce_mux/Z (GTP_LUT5M) + net (fanout=1) 0.000 11.642 u_ov5640/coms1_reg_config/u1/_N104288 + f u_ov5640/coms1_reg_config/u1/reg_sdat/D (GTP_DFF_S) Data arrival time 11.642 Logic Levels: 4 Logic: 3.104ns(57.492%), Route: 2.295ns(42.508%) @@ -4805,20 +5246,23 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 0.903 9.170 u_ov5640/coms2_reg_config/i2c_data [20] u_ov5640/coms2_reg_config/u1/N267_29/I1 (GTP_LUT5M) td 0.365 9.535 f u_ov5640/coms2_reg_config/u1/N267_29/Z (GTP_LUT5M) - net (fanout=1) 0.464 9.999 u_ov5640/coms2_reg_config/u1/_N25904 + net (fanout=1) 0.464 9.999 u_ov5640/coms2_reg_config/u1/_N25853 u_ov5640/coms2_reg_config/u1/N267_35/I0 (GTP_LUT5) td 0.185 10.184 r u_ov5640/coms2_reg_config/u1/N267_35/Z (GTP_LUT5) - net (fanout=1) 0.464 10.648 u_ov5640/coms2_reg_config/u1/_N25910 + net (fanout=1) 0.464 10.648 u_ov5640/coms2_reg_config/u1/_N25859 u_ov5640/coms2_reg_config/u1/N267_36/ID (GTP_LUT5M) td 0.265 10.913 f u_ov5640/coms2_reg_config/u1/N267_36/Z (GTP_LUT5M) - net (fanout=1) 0.464 11.377 u_ov5640/coms2_reg_config/u1/_N25911 - u_ov5640/coms2_reg_config/u1/reg_sdat_ce_mux/ID (GTP_LUT5M) - td 0.265 11.642 f u_ov5640/coms2_reg_config/u1/reg_sdat_ce_mux/Z (GTP_LUT5M) - net (fanout=1) 0.000 11.642 u_ov5640/coms2_reg_config/u1/_N103481 - f u_ov5640/coms2_reg_config/u1/reg_sdat/D (GTP_DFF_S) + net (fanout=1) 0.000 10.913 u_ov5640/coms2_reg_config/u1/_N25860 + u_ov5640/coms2_reg_config/u1/N267_37/I0 (GTP_MUX2LUT6) + td 0.000 10.913 f u_ov5640/coms2_reg_config/u1/N267_37/Z (GTP_MUX2LUT6) + net (fanout=1) 0.464 11.377 u_ov5640/coms2_reg_config/u1/N267 + u_ov5640/coms2_reg_config/u1/reg_sdat_ce_mux/I2 (GTP_LUT5) + td 0.185 11.562 r u_ov5640/coms2_reg_config/u1/reg_sdat_ce_mux/Z (GTP_LUT5) + net (fanout=1) 0.000 11.562 u_ov5640/coms2_reg_config/u1/_N104293 + r u_ov5640/coms2_reg_config/u1/reg_sdat/D (GTP_DFF_S) - Data arrival time 11.642 Logic Levels: 4 - Logic: 3.104ns(57.492%), Route: 2.295ns(42.508%) + Data arrival time 11.562 Logic Levels: 5 + Logic: 3.024ns(56.853%), Route: 2.295ns(43.147%) ---------------------------------------------------------------------------------------------------- Clock clk_20k (rising edge) 50000.000 50000.000 r @@ -4845,9 +5289,9 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim Data required time 50006.227 ---------------------------------------------------------------------------------------------------- Data required time 50006.227 - Data arrival time 11.642 + Data arrival time 11.562 ---------------------------------------------------------------------------------------------------- - Slack (MET) 49994.585 + Slack (MET) 49994.665 ==================================================================================================== ==================================================================================================== @@ -4886,13 +5330,13 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=6) 0.693 7.265 u_ov5640/coms1_reg_config/reg_index [0] u_ov5640/coms1_reg_config/N26_mux2/I0 (GTP_LUT3) td 0.237 7.502 f u_ov5640/coms1_reg_config/N26_mux2/Z (GTP_LUT3) - net (fanout=1) 0.464 7.966 u_ov5640/coms1_reg_config/_N9682 + net (fanout=1) 0.464 7.966 u_ov5640/coms1_reg_config/_N9695 u_ov5640/coms1_reg_config/N26_mux6_3/I0 (GTP_LUT5) td 0.185 8.151 r u_ov5640/coms1_reg_config/N26_mux6_3/Z (GTP_LUT5) - net (fanout=2) 0.553 8.704 u_ov5640/coms1_reg_config/_N9690 + net (fanout=2) 0.553 8.704 u_ov5640/coms1_reg_config/_N9703 u_ov5640/coms1_reg_config/N1134_1/I0 (GTP_LUT4) td 0.185 8.889 r u_ov5640/coms1_reg_config/N1134_1/Z (GTP_LUT4) - net (fanout=4) 0.641 9.530 u_ov5640/coms1_reg_config/_N96528 + net (fanout=4) 0.641 9.530 u_ov5640/coms1_reg_config/_N97285 u_ov5640/coms1_reg_config/N1193_3/I1 (GTP_LUT3) td 0.185 9.715 r u_ov5640/coms1_reg_config/N1193_3/Z (GTP_LUT3) net (fanout=2) 1.067 10.782 u_ov5640/coms1_reg_config/N1193 @@ -5146,8 +5590,8 @@ Path Group : ddrphy_clkin Path Type : max (slow corner) Path Class : sequential timing path Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 9.059 - Launch Clock Delay : 9.059 + Capture Clock Delay : 7.688 + Launch Clock Delay : 7.688 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -5161,57 +5605,57 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 4.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 5.214 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 5.308 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 5.913 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) - td 0.000 5.913 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) - net (fanout=5817) 3.146 9.059 u_axi_ddr_top/clk + td 0.000 4.542 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + net (fanout=5817) 3.146 7.688 u_axi_ddr_top/clk r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[16]/CLK (GTP_DFF_CE) - tco 0.329 9.388 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[16]/Q (GTP_DFF_CE) - net (fanout=50) 1.028 10.416 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [16] + tco 0.329 8.017 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[16]/Q (GTP_DFF_CE) + net (fanout=17) 0.826 8.843 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [16] u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N702_7[0]/I2 (GTP_LUT5M) - td 0.300 10.716 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N702_7[0]/Z (GTP_LUT5M) - net (fanout=1) 0.000 10.716 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N25007 + td 0.327 9.170 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N702_7[0]/Z (GTP_LUT5M) + net (fanout=1) 0.000 9.170 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N24733 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N702_8[0]/I0 (GTP_MUX2LUT6) - td 0.000 10.716 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N702_8[0]/Z (GTP_MUX2LUT6) - net (fanout=4) 0.641 11.357 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/cmd_pre_pass_l + td 0.000 9.170 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N702_8[0]/Z (GTP_MUX2LUT6) + net (fanout=4) 0.641 9.811 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/cmd_pre_pass_l u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N244/I0 (GTP_LUT2) - td 0.185 11.542 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N244/Z (GTP_LUT2) - net (fanout=8) 0.730 12.272 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_pre + td 0.206 10.017 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N244/Z (GTP_LUT2) + net (fanout=8) 0.730 10.747 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_pre u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N31.lt_1/I1 (GTP_LUT5CARRY) - td 0.233 12.505 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N31.lt_1/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 12.505 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N31.co [2] + td 0.233 10.980 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N31.lt_1/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 10.980 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N31.co [2] u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N31.lt_2/CIN (GTP_LUT5CARRY) - td 0.030 12.535 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N31.lt_2/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 12.535 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N31.co [4] + td 0.030 11.010 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N31.lt_2/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 11.010 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N31.co [4] u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N31.lt_3/CIN (GTP_LUT5CARRY) - td 0.236 12.771 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N31.lt_3/Z (GTP_LUT5CARRY) - net (fanout=2) 0.553 13.324 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N31 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_54/I2 (GTP_LUT5) - td 0.185 13.509 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_54/Z (GTP_LUT5) - net (fanout=9) 0.745 14.254 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N25124 + td 0.236 11.246 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N31.lt_3/Z (GTP_LUT5CARRY) + net (fanout=2) 0.553 11.799 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N31 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_51/I2 (GTP_LUT5) + td 0.185 11.984 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_51/Z (GTP_LUT5) + net (fanout=9) 0.745 12.729 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N24930 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_50[3]_2/I0 (GTP_LUT3) - td 0.185 14.439 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_50[3]_2/Z (GTP_LUT3) - net (fanout=3) 0.605 15.044 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N103199_2 + td 0.185 12.914 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_50[3]_2/Z (GTP_LUT3) + net (fanout=3) 0.605 13.519 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N103967_2 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_8_maj1_1/I3 (GTP_LUT5M) - td 0.300 15.344 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_8_maj1_1/Z (GTP_LUT5M) - net (fanout=2) 0.553 15.897 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N15659 + td 0.300 13.819 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_8_maj1_1/Z (GTP_LUT5M) + net (fanout=2) 0.553 14.372 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N15350 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_8_sum3_6/I0 (GTP_LUT5) - td 0.185 16.082 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_8_sum3_6/Z (GTP_LUT5) - net (fanout=1) 0.464 16.546 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N17326 + td 0.185 14.557 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_8_sum3_6/Z (GTP_LUT5) + net (fanout=1) 0.464 15.021 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N17304 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_2[6]_1/I0 (GTP_LUT2) - td 0.185 16.731 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_2[6]_1/Z (GTP_LUT2) - net (fanout=1) 0.000 16.731 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77 [6] + td 0.185 15.206 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_2[6]_1/Z (GTP_LUT2) + net (fanout=1) 0.000 15.206 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77 [6] r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[6]/D (GTP_DFF_C) - Data arrival time 16.731 Logic Levels: 9 - Logic: 2.353ns(30.670%), Route: 5.319ns(69.330%) + Data arrival time 15.206 Logic Levels: 9 + Logic: 2.401ns(31.937%), Route: 5.117ns(68.063%) ---------------------------------------------------------------------------------------------------- Clock ddrphy_clkin (rising edge) 10.000 10.000 r @@ -5222,28 +5666,28 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 12.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 12.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 14.367 zoom_clk + net (fanout=7) 0.605 12.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 14.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 15.214 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 12.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 13.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 15.308 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 15.913 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 13.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 14.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) - td 0.000 15.913 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) - net (fanout=5817) 3.146 19.059 u_axi_ddr_top/clk + td 0.000 14.542 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + net (fanout=5817) 3.146 17.688 u_axi_ddr_top/clk r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[6]/CLK (GTP_DFF_C) - clock pessimism 0.000 19.059 - clock uncertainty -0.150 18.909 + clock pessimism 0.000 17.688 + clock uncertainty -0.150 17.538 - Setup time 0.034 18.943 + Setup time 0.034 17.572 - Data required time 18.943 + Data required time 17.572 ---------------------------------------------------------------------------------------------------- - Data required time 18.943 - Data arrival time 16.731 + Data required time 17.572 + Data arrival time 15.206 ---------------------------------------------------------------------------------------------------- - Slack (MET) 2.212 + Slack (MET) 2.366 ==================================================================================================== ==================================================================================================== @@ -5254,8 +5698,8 @@ Path Group : ddrphy_clkin Path Type : max (slow corner) Path Class : sequential timing path Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 9.059 - Launch Clock Delay : 9.059 + Capture Clock Delay : 7.688 + Launch Clock Delay : 7.688 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -5269,68 +5713,68 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 4.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 5.214 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 5.308 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 5.913 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) - td 0.000 5.913 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) - net (fanout=5817) 3.146 9.059 u_axi_ddr_top/clk + td 0.000 4.542 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + net (fanout=5817) 3.146 7.688 u_axi_ddr_top/clk r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/calib_done/CLK (GTP_DFF_C) - tco 0.329 9.388 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/calib_done/Q (GTP_DFF_C) - net (fanout=575) 2.721 12.109 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/calib_done + tco 0.329 8.017 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/calib_done/Q (GTP_DFF_C) + net (fanout=575) 2.721 10.738 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/calib_done u_axi_ddr_top/u_axi_rd_connect/N1_2/I1 (GTP_LUT3) - td 0.185 12.294 r u_axi_ddr_top/u_axi_rd_connect/N1_2/Z (GTP_LUT3) - net (fanout=3) 0.605 12.899 u_axi_ddr_top/u_axi_rd_connect/wr_en + td 0.185 10.923 r u_axi_ddr_top/u_axi_rd_connect/N1_2/Z (GTP_LUT3) + net (fanout=3) 0.605 11.528 u_axi_ddr_top/u_axi_rd_connect/wr_en u_axi_ddr_top/u_axi_rd_connect/N7_4/I0 (GTP_LUT4) - td 0.185 13.084 r u_axi_ddr_top/u_axi_rd_connect/N7_4/Z (GTP_LUT4) - net (fanout=3) 0.605 13.689 u_axi_ddr_top/u_axi_rd_connect/wr_rid_en + td 0.185 11.713 r u_axi_ddr_top/u_axi_rd_connect/N7_4/Z (GTP_LUT4) + net (fanout=3) 0.605 12.318 u_axi_ddr_top/u_axi_rd_connect/wr_rid_en u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_1/I0 (GTP_LUT5CARRY) - td 0.201 13.890 f u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_1/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 13.890 u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/_N15823 + td 0.201 12.519 f u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_1/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 12.519 u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/_N15759 u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_2/CIN (GTP_LUT5CARRY) - td 0.030 13.920 r u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_2/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 13.920 u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/_N15824 + td 0.030 12.549 r u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_2/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 12.549 u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/_N15760 u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_3/CIN (GTP_LUT5CARRY) - td 0.030 13.950 r u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_3/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 13.950 u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/_N15825 + td 0.030 12.579 r u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_3/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 12.579 u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/_N15761 u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_4/CIN (GTP_LUT5CARRY) - td 0.030 13.980 r u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_4/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 13.980 u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/_N15826 + td 0.030 12.609 r u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_4/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 12.609 u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/_N15762 u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_5/CIN (GTP_LUT5CARRY) - td 0.030 14.010 r u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_5/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 14.010 u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/_N15827 + td 0.030 12.639 r u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_5/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 12.639 u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/_N15763 u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_6/CIN (GTP_LUT5CARRY) - td 0.030 14.040 r u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_6/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 14.040 u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/_N15828 + td 0.030 12.669 r u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_6/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 12.669 u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/_N15764 u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_7/CIN (GTP_LUT5CARRY) - td 0.030 14.070 r u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_7/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 14.070 u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/_N15829 + td 0.030 12.699 r u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_7/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 12.699 u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/_N15765 u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_8/CIN (GTP_LUT5CARRY) - td 0.030 14.100 r u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_8/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 14.100 u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/_N15830 + td 0.030 12.729 r u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_8/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 12.729 u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/_N15766 u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_9/CIN (GTP_LUT5CARRY) - td 0.030 14.130 r u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_9/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 14.130 u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/_N15831 + td 0.030 12.759 r u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_9/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 12.759 u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/_N15767 u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_10/CIN (GTP_LUT5CARRY) - td 0.236 14.366 r u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_10/Z (GTP_LUT5CARRY) - net (fanout=2) 0.553 14.919 u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2 [9] + td 0.236 12.995 r u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_10/Z (GTP_LUT5CARRY) + net (fanout=2) 0.553 13.548 u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2 [9] u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N3[9]/I2 (GTP_LUT3) - td 0.185 15.104 r u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N3[9]/Z (GTP_LUT3) - net (fanout=1) 0.464 15.568 u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/rwptr [9] + td 0.185 13.733 r u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N3[9]/Z (GTP_LUT3) + net (fanout=1) 0.464 14.197 u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/rwptr [9] u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N24.eq_4/I2 (GTP_LUT5CARRY) - td 0.233 15.801 f u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N24.eq_4/COUT (GTP_LUT5CARRY) - net (fanout=2) 0.553 16.354 u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N21 + td 0.233 14.430 f u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N24.eq_4/COUT (GTP_LUT5CARRY) + net (fanout=2) 0.553 14.983 u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N21 u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N22/I4 (GTP_LUT5) - td 0.185 16.539 r u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N22/Z (GTP_LUT5) - net (fanout=1) 0.000 16.539 u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N22 + td 0.185 15.168 r u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N22/Z (GTP_LUT5) + net (fanout=1) 0.000 15.168 u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N22 r u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/D (GTP_DFF_C) - Data arrival time 16.539 Logic Levels: 8 + Data arrival time 15.168 Logic Levels: 8 Logic: 1.979ns(26.457%), Route: 5.501ns(73.543%) ---------------------------------------------------------------------------------------------------- @@ -5342,26 +5786,26 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 12.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 12.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 14.367 zoom_clk + net (fanout=7) 0.605 12.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 14.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 15.214 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 12.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 13.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 15.308 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 15.913 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 13.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 14.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) - td 0.000 15.913 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) - net (fanout=5817) 3.146 19.059 u_axi_ddr_top/clk + td 0.000 14.542 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + net (fanout=5817) 3.146 17.688 u_axi_ddr_top/clk r u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/CLK (GTP_DFF_C) - clock pessimism 0.000 19.059 - clock uncertainty -0.150 18.909 + clock pessimism 0.000 17.688 + clock uncertainty -0.150 17.538 - Setup time 0.034 18.943 + Setup time 0.034 17.572 - Data required time 18.943 + Data required time 17.572 ---------------------------------------------------------------------------------------------------- - Data required time 18.943 - Data arrival time 16.539 + Data required time 17.572 + Data arrival time 15.168 ---------------------------------------------------------------------------------------------------- Slack (MET) 2.404 ==================================================================================================== @@ -5374,8 +5818,8 @@ Path Group : ddrphy_clkin Path Type : max (slow corner) Path Class : sequential timing path Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 9.059 - Launch Clock Delay : 9.059 + Capture Clock Delay : 7.688 + Launch Clock Delay : 7.688 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -5389,53 +5833,53 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 4.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 5.214 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 5.308 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 5.913 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) - td 0.000 5.913 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) - net (fanout=5817) 3.146 9.059 u_axi_ddr_top/clk + td 0.000 4.542 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + net (fanout=5817) 3.146 7.688 u_axi_ddr_top/clk r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/CLK (GTP_DFF_CE) - tco 0.329 9.388 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/Q (GTP_DFF_CE) - net (fanout=5) 0.670 10.058 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mr0_ddr3 [2] + tco 0.329 8.017 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/Q (GTP_DFF_CE) + net (fanout=5) 0.670 8.687 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mr0_ddr3 [2] u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/I0 (GTP_LUT4) - td 0.290 10.348 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/Z (GTP_LUT4) - net (fanout=2) 0.553 10.901 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_cl [1] + td 0.290 8.977 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/Z (GTP_LUT4) + net (fanout=2) 0.553 9.530 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_cl [1] u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_2/I3 (GTP_LUT5CARRY) - td 0.363 11.264 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_2/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 11.264 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.co [2] + td 0.363 9.893 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_2/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 9.893 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.co [2] u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_3/CIN (GTP_LUT5CARRY) - td 0.236 11.500 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_3/Z (GTP_LUT5CARRY) - net (fanout=1) 0.464 11.964 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [2] + td 0.236 10.129 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_3/Z (GTP_LUT5CARRY) + net (fanout=1) 0.464 10.593 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [2] u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[2]/I2 (GTP_LUT3) - td 0.185 12.149 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[2]/Z (GTP_LUT3) - net (fanout=4) 0.641 12.790 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al [2] + td 0.185 10.778 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[2]/Z (GTP_LUT3) + net (fanout=4) 0.641 11.419 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al [2] u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_3/I2 (GTP_LUT5CARRY) - td 0.233 13.023 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_3/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 13.023 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14575 + td 0.233 11.652 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_3/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 11.652 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14533 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_4/CIN (GTP_LUT5CARRY) - td 0.030 13.053 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_4/COUT (GTP_LUT5CARRY) - net (fanout=1) 0.000 13.053 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14576 + td 0.030 11.682 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_4/COUT (GTP_LUT5CARRY) + net (fanout=1) 0.000 11.682 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14534 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_5/CIN (GTP_LUT5CARRY) - td 0.236 13.289 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_5/Z (GTP_LUT5CARRY) - net (fanout=4) 0.641 13.930 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mc_rl [4] + td 0.236 11.918 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_5/Z (GTP_LUT5CARRY) + net (fanout=4) 0.641 12.559 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mc_rl [4] u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_198_5/I4 (GTP_LUT5) - td 0.277 14.207 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_198_5/Z (GTP_LUT5) - net (fanout=56) 1.058 15.265 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24127 + td 0.277 12.836 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_198_5/Z (GTP_LUT5) + net (fanout=56) 1.058 13.894 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23906 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[0]/I2 (GTP_LUT3) - td 0.185 15.450 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[0]/Z (GTP_LUT3) - net (fanout=1) 0.464 15.914 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24197 + td 0.185 14.079 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[0]/Z (GTP_LUT3) + net (fanout=1) 0.464 14.543 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23976 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_172[0]/I1 (GTP_LUT5M) - td 0.430 16.344 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_172[0]/Z (GTP_LUT5M) - net (fanout=1) 0.000 16.344 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj [0] + td 0.430 14.973 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_172[0]/Z (GTP_LUT5M) + net (fanout=1) 0.000 14.973 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj [0] f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/D (GTP_DFF_C) - Data arrival time 16.344 Logic Levels: 7 + Data arrival time 14.973 Logic Levels: 7 Logic: 2.794ns(38.353%), Route: 4.491ns(61.647%) ---------------------------------------------------------------------------------------------------- @@ -5447,26 +5891,26 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 12.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 12.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 14.367 zoom_clk + net (fanout=7) 0.605 12.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 14.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 15.214 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 12.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 13.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 15.308 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 15.913 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 13.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 14.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) - td 0.000 15.913 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) - net (fanout=5817) 3.146 19.059 u_axi_ddr_top/clk + td 0.000 14.542 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + net (fanout=5817) 3.146 17.688 u_axi_ddr_top/clk r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/CLK (GTP_DFF_C) - clock pessimism 0.000 19.059 - clock uncertainty -0.150 18.909 + clock pessimism 0.000 17.688 + clock uncertainty -0.150 17.538 - Setup time 0.034 18.943 + Setup time 0.034 17.572 - Data required time 18.943 + Data required time 17.572 ---------------------------------------------------------------------------------------------------- - Data required time 18.943 - Data arrival time 16.344 + Data required time 17.572 + Data arrival time 14.973 ---------------------------------------------------------------------------------------------------- Slack (MET) 2.599 ==================================================================================================== @@ -5479,8 +5923,8 @@ Path Group : ddrphy_clkin Path Type : min (slow corner) Path Class : sequential timing path Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 9.059 - Launch Clock Delay : 9.059 + Capture Clock Delay : 7.688 + Launch Clock Delay : 7.688 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -5494,23 +5938,23 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 4.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 5.214 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 5.308 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 5.913 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) - td 0.000 5.913 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) - net (fanout=5817) 3.146 9.059 u_axi_ddr_top/clk + td 0.000 4.542 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + net (fanout=5817) 3.146 7.688 u_axi_ddr_top/clk r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[0]/CLK (GTP_DFF_C) - tco 0.323 9.382 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[0]/Q (GTP_DFF_C) - net (fanout=1) 0.464 9.846 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/rid [0] + tco 0.323 8.011 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[0]/Q (GTP_DFF_C) + net (fanout=1) 0.464 8.475 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/rid [0] f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_0/DI (GTP_RAM32X1DP) - Data arrival time 9.846 Logic Levels: 0 + Data arrival time 8.475 Logic Levels: 0 Logic: 0.323ns(41.042%), Route: 0.464ns(58.958%) ---------------------------------------------------------------------------------------------------- @@ -5522,26 +5966,26 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 4.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 5.214 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 5.308 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 5.913 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) - td 0.000 5.913 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) - net (fanout=5817) 3.146 9.059 u_axi_ddr_top/clk + td 0.000 4.542 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + net (fanout=5817) 3.146 7.688 u_axi_ddr_top/clk r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_0/WCLK (GTP_RAM32X1DP) - clock pessimism 0.000 9.059 - clock uncertainty 0.000 9.059 + clock pessimism 0.000 7.688 + clock uncertainty 0.000 7.688 - Hold time 0.334 9.393 + Hold time 0.334 8.022 - Data required time 9.393 + Data required time 8.022 ---------------------------------------------------------------------------------------------------- - Data required time 9.393 - Data arrival time 9.846 + Data required time 8.022 + Data arrival time 8.475 ---------------------------------------------------------------------------------------------------- Slack (MET) 0.453 ==================================================================================================== @@ -5554,8 +5998,8 @@ Path Group : ddrphy_clkin Path Type : min (slow corner) Path Class : sequential timing path Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 9.059 - Launch Clock Delay : 9.059 + Capture Clock Delay : 7.688 + Launch Clock Delay : 7.688 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -5569,23 +6013,23 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 4.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 5.214 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 5.308 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 5.913 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) - td 0.000 5.913 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) - net (fanout=5817) 3.146 9.059 u_axi_ddr_top/clk + td 0.000 4.542 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + net (fanout=5817) 3.146 7.688 u_axi_ddr_top/clk r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[1]/CLK (GTP_DFF_C) - tco 0.323 9.382 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[1]/Q (GTP_DFF_C) - net (fanout=1) 0.464 9.846 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/rid [1] + tco 0.323 8.011 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[1]/Q (GTP_DFF_C) + net (fanout=1) 0.464 8.475 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/rid [1] f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/DI (GTP_RAM32X1DP) - Data arrival time 9.846 Logic Levels: 0 + Data arrival time 8.475 Logic Levels: 0 Logic: 0.323ns(41.042%), Route: 0.464ns(58.958%) ---------------------------------------------------------------------------------------------------- @@ -5597,26 +6041,26 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 4.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 5.214 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 5.308 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 5.913 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) - td 0.000 5.913 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) - net (fanout=5817) 3.146 9.059 u_axi_ddr_top/clk + td 0.000 4.542 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + net (fanout=5817) 3.146 7.688 u_axi_ddr_top/clk r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/WCLK (GTP_RAM32X1DP) - clock pessimism 0.000 9.059 - clock uncertainty 0.000 9.059 + clock pessimism 0.000 7.688 + clock uncertainty 0.000 7.688 - Hold time 0.334 9.393 + Hold time 0.334 8.022 - Data required time 9.393 + Data required time 8.022 ---------------------------------------------------------------------------------------------------- - Data required time 9.393 - Data arrival time 9.846 + Data required time 8.022 + Data arrival time 8.475 ---------------------------------------------------------------------------------------------------- Slack (MET) 0.453 ==================================================================================================== @@ -5629,8 +6073,8 @@ Path Group : ddrphy_clkin Path Type : min (slow corner) Path Class : sequential timing path Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 9.059 - Launch Clock Delay : 9.059 + Capture Clock Delay : 7.688 + Launch Clock Delay : 7.688 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -5644,23 +6088,23 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 4.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 5.214 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 5.308 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 5.913 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) - td 0.000 5.913 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) - net (fanout=5817) 3.146 9.059 u_axi_ddr_top/clk + td 0.000 4.542 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + net (fanout=5817) 3.146 7.688 u_axi_ddr_top/clk r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[2]/CLK (GTP_DFF_C) - tco 0.323 9.382 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[2]/Q (GTP_DFF_C) - net (fanout=1) 0.464 9.846 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/rid [2] + tco 0.323 8.011 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[2]/Q (GTP_DFF_C) + net (fanout=1) 0.464 8.475 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/rid [2] f u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_2/DI (GTP_RAM32X1DP) - Data arrival time 9.846 Logic Levels: 0 + Data arrival time 8.475 Logic Levels: 0 Logic: 0.323ns(41.042%), Route: 0.464ns(58.958%) ---------------------------------------------------------------------------------------------------- @@ -5672,26 +6116,26 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 4.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 5.214 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 5.308 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 5.913 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) - td 0.000 5.913 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) - net (fanout=5817) 3.146 9.059 u_axi_ddr_top/clk + td 0.000 4.542 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + net (fanout=5817) 3.146 7.688 u_axi_ddr_top/clk r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_2/WCLK (GTP_RAM32X1DP) - clock pessimism 0.000 9.059 - clock uncertainty 0.000 9.059 + clock pessimism 0.000 7.688 + clock uncertainty 0.000 7.688 - Hold time 0.334 9.393 + Hold time 0.334 8.022 - Data required time 9.393 + Data required time 8.022 ---------------------------------------------------------------------------------------------------- - Data required time 9.393 - Data arrival time 9.846 + Data required time 8.022 + Data arrival time 8.475 ---------------------------------------------------------------------------------------------------- Slack (MET) 0.453 ==================================================================================================== @@ -5704,8 +6148,8 @@ Path Group : ioclk0 Path Type : max (slow corner) Path Class : sequential timing path Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 6.990 - Launch Clock Delay : 6.990 + Capture Clock Delay : 5.619 + Launch Clock Delay : 5.619 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -5719,23 +6163,23 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 4.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 5.214 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 5.308 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 5.913 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKIN (GTP_IOCLKBUF) - td 0.306 6.219 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) - net (fanout=11) 0.771 6.990 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + td 0.306 4.848 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) + net (fanout=11) 0.771 5.619 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/CLKA (GTP_DDC_E1) - tco 0.464 7.454 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[0] (GTP_DDC_E1) - net (fanout=8) 0.730 8.184 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [0] + tco 0.464 6.083 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[0] (GTP_DDC_E1) + net (fanout=8) 0.730 6.813 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [0] f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[0] (GTP_ISERDES) - Data arrival time 8.184 Logic Levels: 0 + Data arrival time 6.813 Logic Levels: 0 Logic: 0.464ns(38.861%), Route: 0.730ns(61.139%) ---------------------------------------------------------------------------------------------------- @@ -5747,26 +6191,26 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 4.802 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 4.891 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 6.867 zoom_clk + net (fanout=7) 0.605 5.496 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 6.867 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 7.714 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 5.496 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 6.343 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 7.808 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 8.413 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 6.437 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 7.042 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKIN (GTP_IOCLKBUF) - td 0.306 8.719 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) - net (fanout=11) 0.771 9.490 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + td 0.306 7.348 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) + net (fanout=11) 0.771 8.119 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/DESCLK (GTP_ISERDES) - clock pessimism 0.000 9.490 - clock uncertainty -0.150 9.340 + clock pessimism 0.000 8.119 + clock uncertainty -0.150 7.969 - Setup time -0.068 9.272 + Setup time -0.068 7.901 - Data required time 9.272 + Data required time 7.901 ---------------------------------------------------------------------------------------------------- - Data required time 9.272 - Data arrival time 8.184 + Data required time 7.901 + Data arrival time 6.813 ---------------------------------------------------------------------------------------------------- Slack (MET) 1.088 ==================================================================================================== @@ -5779,8 +6223,8 @@ Path Group : ioclk0 Path Type : max (slow corner) Path Class : sequential timing path Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 6.990 - Launch Clock Delay : 6.990 + Capture Clock Delay : 5.619 + Launch Clock Delay : 5.619 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -5794,23 +6238,23 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 4.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 5.214 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 5.308 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 5.913 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKIN (GTP_IOCLKBUF) - td 0.306 6.219 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) - net (fanout=11) 0.771 6.990 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + td 0.306 4.848 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) + net (fanout=11) 0.771 5.619 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/CLKA (GTP_DDC_E1) - tco 0.464 7.454 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[1] (GTP_DDC_E1) - net (fanout=8) 0.730 8.184 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [1] + tco 0.464 6.083 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[1] (GTP_DDC_E1) + net (fanout=8) 0.730 6.813 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [1] f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[1] (GTP_ISERDES) - Data arrival time 8.184 Logic Levels: 0 + Data arrival time 6.813 Logic Levels: 0 Logic: 0.464ns(38.861%), Route: 0.730ns(61.139%) ---------------------------------------------------------------------------------------------------- @@ -5822,26 +6266,26 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 4.802 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 4.891 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 6.867 zoom_clk + net (fanout=7) 0.605 5.496 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 6.867 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 7.714 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 5.496 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 6.343 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 7.808 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 8.413 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 6.437 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 7.042 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKIN (GTP_IOCLKBUF) - td 0.306 8.719 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) - net (fanout=11) 0.771 9.490 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + td 0.306 7.348 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) + net (fanout=11) 0.771 8.119 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/DESCLK (GTP_ISERDES) - clock pessimism 0.000 9.490 - clock uncertainty -0.150 9.340 + clock pessimism 0.000 8.119 + clock uncertainty -0.150 7.969 - Setup time -0.068 9.272 + Setup time -0.068 7.901 - Data required time 9.272 + Data required time 7.901 ---------------------------------------------------------------------------------------------------- - Data required time 9.272 - Data arrival time 8.184 + Data required time 7.901 + Data arrival time 6.813 ---------------------------------------------------------------------------------------------------- Slack (MET) 1.088 ==================================================================================================== @@ -5854,8 +6298,8 @@ Path Group : ioclk0 Path Type : max (slow corner) Path Class : sequential timing path Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 6.990 - Launch Clock Delay : 6.990 + Capture Clock Delay : 5.619 + Launch Clock Delay : 5.619 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -5869,23 +6313,23 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 4.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 5.214 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 5.308 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 5.913 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKIN (GTP_IOCLKBUF) - td 0.306 6.219 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) - net (fanout=11) 0.771 6.990 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + td 0.306 4.848 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) + net (fanout=11) 0.771 5.619 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/CLKA (GTP_DDC_E1) - tco 0.464 7.454 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[2] (GTP_DDC_E1) - net (fanout=8) 0.730 8.184 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [2] + tco 0.464 6.083 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[2] (GTP_DDC_E1) + net (fanout=8) 0.730 6.813 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [2] f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[2] (GTP_ISERDES) - Data arrival time 8.184 Logic Levels: 0 + Data arrival time 6.813 Logic Levels: 0 Logic: 0.464ns(38.861%), Route: 0.730ns(61.139%) ---------------------------------------------------------------------------------------------------- @@ -5897,26 +6341,26 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 4.802 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 4.891 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 6.867 zoom_clk + net (fanout=7) 0.605 5.496 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 6.867 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 7.714 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 5.496 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 6.343 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 7.808 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 8.413 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 6.437 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 7.042 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKIN (GTP_IOCLKBUF) - td 0.306 8.719 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) - net (fanout=11) 0.771 9.490 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + td 0.306 7.348 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) + net (fanout=11) 0.771 8.119 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/DESCLK (GTP_ISERDES) - clock pessimism 0.000 9.490 - clock uncertainty -0.150 9.340 + clock pessimism 0.000 8.119 + clock uncertainty -0.150 7.969 - Setup time -0.068 9.272 + Setup time -0.068 7.901 - Data required time 9.272 + Data required time 7.901 ---------------------------------------------------------------------------------------------------- - Data required time 9.272 - Data arrival time 8.184 + Data required time 7.901 + Data arrival time 6.813 ---------------------------------------------------------------------------------------------------- Slack (MET) 1.088 ==================================================================================================== @@ -5929,8 +6373,8 @@ Path Group : ioclk0 Path Type : min (slow corner) Path Class : sequential timing path Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 6.990 - Launch Clock Delay : 6.990 + Capture Clock Delay : 5.619 + Launch Clock Delay : 5.619 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -5944,23 +6388,23 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 4.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 5.214 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 5.308 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 5.913 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKIN (GTP_IOCLKBUF) - td 0.306 6.219 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) - net (fanout=11) 0.771 6.990 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + td 0.306 4.848 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) + net (fanout=11) 0.771 5.619 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/CLKA (GTP_DDC_E1) - tco 0.464 7.454 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[0] (GTP_DDC_E1) - net (fanout=8) 0.730 8.184 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [0] + tco 0.464 6.083 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[0] (GTP_DDC_E1) + net (fanout=8) 0.730 6.813 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [0] f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[0] (GTP_ISERDES) - Data arrival time 8.184 Logic Levels: 0 + Data arrival time 6.813 Logic Levels: 0 Logic: 0.464ns(38.861%), Route: 0.730ns(61.139%) ---------------------------------------------------------------------------------------------------- @@ -5972,26 +6416,26 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 4.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 5.214 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 5.308 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 5.913 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKIN (GTP_IOCLKBUF) - td 0.306 6.219 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) - net (fanout=11) 0.771 6.990 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + td 0.306 4.848 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) + net (fanout=11) 0.771 5.619 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/DESCLK (GTP_ISERDES) - clock pessimism 0.000 6.990 - clock uncertainty 0.000 6.990 + clock pessimism 0.000 5.619 + clock uncertainty 0.000 5.619 - Hold time 0.001 6.991 + Hold time 0.001 5.620 - Data required time 6.991 + Data required time 5.620 ---------------------------------------------------------------------------------------------------- - Data required time 6.991 - Data arrival time 8.184 + Data required time 5.620 + Data arrival time 6.813 ---------------------------------------------------------------------------------------------------- Slack (MET) 1.193 ==================================================================================================== @@ -6004,8 +6448,8 @@ Path Group : ioclk0 Path Type : min (slow corner) Path Class : sequential timing path Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 6.990 - Launch Clock Delay : 6.990 + Capture Clock Delay : 5.619 + Launch Clock Delay : 5.619 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -6019,23 +6463,23 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 4.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 5.214 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 5.308 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 5.913 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKIN (GTP_IOCLKBUF) - td 0.306 6.219 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) - net (fanout=11) 0.771 6.990 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + td 0.306 4.848 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) + net (fanout=11) 0.771 5.619 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/CLKA (GTP_DDC_E1) - tco 0.464 7.454 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[1] (GTP_DDC_E1) - net (fanout=8) 0.730 8.184 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [1] + tco 0.464 6.083 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[1] (GTP_DDC_E1) + net (fanout=8) 0.730 6.813 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [1] f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[1] (GTP_ISERDES) - Data arrival time 8.184 Logic Levels: 0 + Data arrival time 6.813 Logic Levels: 0 Logic: 0.464ns(38.861%), Route: 0.730ns(61.139%) ---------------------------------------------------------------------------------------------------- @@ -6047,26 +6491,26 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 4.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 5.214 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 5.308 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 5.913 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKIN (GTP_IOCLKBUF) - td 0.306 6.219 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) - net (fanout=11) 0.771 6.990 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + td 0.306 4.848 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) + net (fanout=11) 0.771 5.619 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/DESCLK (GTP_ISERDES) - clock pessimism 0.000 6.990 - clock uncertainty 0.000 6.990 + clock pessimism 0.000 5.619 + clock uncertainty 0.000 5.619 - Hold time 0.001 6.991 + Hold time 0.001 5.620 - Data required time 6.991 + Data required time 5.620 ---------------------------------------------------------------------------------------------------- - Data required time 6.991 - Data arrival time 8.184 + Data required time 5.620 + Data arrival time 6.813 ---------------------------------------------------------------------------------------------------- Slack (MET) 1.193 ==================================================================================================== @@ -6079,8 +6523,8 @@ Path Group : ioclk0 Path Type : min (slow corner) Path Class : sequential timing path Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 6.990 - Launch Clock Delay : 6.990 + Capture Clock Delay : 5.619 + Launch Clock Delay : 5.619 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -6094,23 +6538,23 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 4.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 5.214 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 5.308 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 5.913 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKIN (GTP_IOCLKBUF) - td 0.306 6.219 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) - net (fanout=11) 0.771 6.990 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + td 0.306 4.848 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) + net (fanout=11) 0.771 5.619 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/CLKA (GTP_DDC_E1) - tco 0.464 7.454 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[2] (GTP_DDC_E1) - net (fanout=8) 0.730 8.184 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [2] + tco 0.464 6.083 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[2] (GTP_DDC_E1) + net (fanout=8) 0.730 6.813 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [2] f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[2] (GTP_ISERDES) - Data arrival time 8.184 Logic Levels: 0 + Data arrival time 6.813 Logic Levels: 0 Logic: 0.464ns(38.861%), Route: 0.730ns(61.139%) ---------------------------------------------------------------------------------------------------- @@ -6122,26 +6566,26 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 4.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 5.214 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 5.308 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 5.913 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKIN (GTP_IOCLKBUF) - td 0.306 6.219 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) - net (fanout=11) 0.771 6.990 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + td 0.306 4.848 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) + net (fanout=11) 0.771 5.619 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/DESCLK (GTP_ISERDES) - clock pessimism 0.000 6.990 - clock uncertainty 0.000 6.990 + clock pessimism 0.000 5.619 + clock uncertainty 0.000 5.619 - Hold time 0.001 6.991 + Hold time 0.001 5.620 - Data required time 6.991 + Data required time 5.620 ---------------------------------------------------------------------------------------------------- - Data required time 6.991 - Data arrival time 8.184 + Data required time 5.620 + Data arrival time 6.813 ---------------------------------------------------------------------------------------------------- Slack (MET) 1.193 ==================================================================================================== @@ -6154,8 +6598,8 @@ Path Group : ioclk1 Path Type : max (slow corner) Path Class : sequential timing path Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 7.137 - Launch Clock Delay : 7.137 + Capture Clock Delay : 5.766 + Launch Clock Delay : 5.766 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -6169,23 +6613,23 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 4.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 5.214 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 5.308 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 5.913 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKIN (GTP_IOCLKBUF) - td 0.306 6.219 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) - net (fanout=28) 0.918 7.137 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + td 0.306 4.848 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) + net (fanout=28) 0.918 5.766 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/CLKA (GTP_DDC_E1) - tco 0.464 7.601 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[0] (GTP_DDC_E1) - net (fanout=8) 0.730 8.331 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [0] + tco 0.464 6.230 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[0] (GTP_DDC_E1) + net (fanout=8) 0.730 6.960 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [0] f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[0] (GTP_ISERDES) - Data arrival time 8.331 Logic Levels: 0 + Data arrival time 6.960 Logic Levels: 0 Logic: 0.464ns(38.861%), Route: 0.730ns(61.139%) ---------------------------------------------------------------------------------------------------- @@ -6197,26 +6641,26 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 4.802 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 4.891 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 6.867 zoom_clk + net (fanout=7) 0.605 5.496 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 6.867 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 7.714 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 5.496 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 6.343 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 7.808 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 8.413 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 6.437 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 7.042 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKIN (GTP_IOCLKBUF) - td 0.306 8.719 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) - net (fanout=28) 0.918 9.637 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + td 0.306 7.348 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) + net (fanout=28) 0.918 8.266 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/DESCLK (GTP_ISERDES) - clock pessimism 0.000 9.637 - clock uncertainty -0.150 9.487 + clock pessimism 0.000 8.266 + clock uncertainty -0.150 8.116 - Setup time -0.068 9.419 + Setup time -0.068 8.048 - Data required time 9.419 + Data required time 8.048 ---------------------------------------------------------------------------------------------------- - Data required time 9.419 - Data arrival time 8.331 + Data required time 8.048 + Data arrival time 6.960 ---------------------------------------------------------------------------------------------------- Slack (MET) 1.088 ==================================================================================================== @@ -6229,8 +6673,8 @@ Path Group : ioclk1 Path Type : max (slow corner) Path Class : sequential timing path Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 7.137 - Launch Clock Delay : 7.137 + Capture Clock Delay : 5.766 + Launch Clock Delay : 5.766 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -6244,23 +6688,23 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 4.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 5.214 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 5.308 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 5.913 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKIN (GTP_IOCLKBUF) - td 0.306 6.219 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) - net (fanout=28) 0.918 7.137 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + td 0.306 4.848 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) + net (fanout=28) 0.918 5.766 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/CLKA (GTP_DDC_E1) - tco 0.464 7.601 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[1] (GTP_DDC_E1) - net (fanout=8) 0.730 8.331 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [1] + tco 0.464 6.230 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[1] (GTP_DDC_E1) + net (fanout=8) 0.730 6.960 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [1] f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[1] (GTP_ISERDES) - Data arrival time 8.331 Logic Levels: 0 + Data arrival time 6.960 Logic Levels: 0 Logic: 0.464ns(38.861%), Route: 0.730ns(61.139%) ---------------------------------------------------------------------------------------------------- @@ -6272,26 +6716,26 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 4.802 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 4.891 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 6.867 zoom_clk + net (fanout=7) 0.605 5.496 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 6.867 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 7.714 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 5.496 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 6.343 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 7.808 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 8.413 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 6.437 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 7.042 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKIN (GTP_IOCLKBUF) - td 0.306 8.719 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) - net (fanout=28) 0.918 9.637 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + td 0.306 7.348 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) + net (fanout=28) 0.918 8.266 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/DESCLK (GTP_ISERDES) - clock pessimism 0.000 9.637 - clock uncertainty -0.150 9.487 + clock pessimism 0.000 8.266 + clock uncertainty -0.150 8.116 - Setup time -0.068 9.419 + Setup time -0.068 8.048 - Data required time 9.419 + Data required time 8.048 ---------------------------------------------------------------------------------------------------- - Data required time 9.419 - Data arrival time 8.331 + Data required time 8.048 + Data arrival time 6.960 ---------------------------------------------------------------------------------------------------- Slack (MET) 1.088 ==================================================================================================== @@ -6304,8 +6748,8 @@ Path Group : ioclk1 Path Type : max (slow corner) Path Class : sequential timing path Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 7.137 - Launch Clock Delay : 7.137 + Capture Clock Delay : 5.766 + Launch Clock Delay : 5.766 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -6319,23 +6763,23 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 4.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 5.214 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 5.308 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 5.913 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKIN (GTP_IOCLKBUF) - td 0.306 6.219 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) - net (fanout=28) 0.918 7.137 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + td 0.306 4.848 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) + net (fanout=28) 0.918 5.766 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/CLKA (GTP_DDC_E1) - tco 0.464 7.601 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[2] (GTP_DDC_E1) - net (fanout=8) 0.730 8.331 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [2] + tco 0.464 6.230 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[2] (GTP_DDC_E1) + net (fanout=8) 0.730 6.960 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [2] f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[2] (GTP_ISERDES) - Data arrival time 8.331 Logic Levels: 0 + Data arrival time 6.960 Logic Levels: 0 Logic: 0.464ns(38.861%), Route: 0.730ns(61.139%) ---------------------------------------------------------------------------------------------------- @@ -6347,26 +6791,26 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 4.802 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 4.891 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 6.867 zoom_clk + net (fanout=7) 0.605 5.496 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 6.867 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 7.714 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 5.496 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 6.343 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 7.808 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 8.413 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 6.437 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 7.042 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKIN (GTP_IOCLKBUF) - td 0.306 8.719 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) - net (fanout=28) 0.918 9.637 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + td 0.306 7.348 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) + net (fanout=28) 0.918 8.266 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/DESCLK (GTP_ISERDES) - clock pessimism 0.000 9.637 - clock uncertainty -0.150 9.487 + clock pessimism 0.000 8.266 + clock uncertainty -0.150 8.116 - Setup time -0.068 9.419 + Setup time -0.068 8.048 - Data required time 9.419 + Data required time 8.048 ---------------------------------------------------------------------------------------------------- - Data required time 9.419 - Data arrival time 8.331 + Data required time 8.048 + Data arrival time 6.960 ---------------------------------------------------------------------------------------------------- Slack (MET) 1.088 ==================================================================================================== @@ -6379,8 +6823,8 @@ Path Group : ioclk1 Path Type : min (slow corner) Path Class : sequential timing path Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 7.137 - Launch Clock Delay : 7.137 + Capture Clock Delay : 5.766 + Launch Clock Delay : 5.766 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -6394,23 +6838,23 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 4.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 5.214 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 5.308 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 5.913 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKIN (GTP_IOCLKBUF) - td 0.306 6.219 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) - net (fanout=28) 0.918 7.137 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + td 0.306 4.848 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) + net (fanout=28) 0.918 5.766 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/CLKA (GTP_DDC_E1) - tco 0.464 7.601 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[0] (GTP_DDC_E1) - net (fanout=8) 0.730 8.331 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [0] + tco 0.464 6.230 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[0] (GTP_DDC_E1) + net (fanout=8) 0.730 6.960 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [0] f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[0] (GTP_ISERDES) - Data arrival time 8.331 Logic Levels: 0 + Data arrival time 6.960 Logic Levels: 0 Logic: 0.464ns(38.861%), Route: 0.730ns(61.139%) ---------------------------------------------------------------------------------------------------- @@ -6422,26 +6866,26 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 4.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 5.214 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 5.308 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 5.913 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKIN (GTP_IOCLKBUF) - td 0.306 6.219 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) - net (fanout=28) 0.918 7.137 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + td 0.306 4.848 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) + net (fanout=28) 0.918 5.766 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/DESCLK (GTP_ISERDES) - clock pessimism 0.000 7.137 - clock uncertainty 0.000 7.137 + clock pessimism 0.000 5.766 + clock uncertainty 0.000 5.766 - Hold time 0.001 7.138 + Hold time 0.001 5.767 - Data required time 7.138 + Data required time 5.767 ---------------------------------------------------------------------------------------------------- - Data required time 7.138 - Data arrival time 8.331 + Data required time 5.767 + Data arrival time 6.960 ---------------------------------------------------------------------------------------------------- Slack (MET) 1.193 ==================================================================================================== @@ -6454,8 +6898,8 @@ Path Group : ioclk1 Path Type : min (slow corner) Path Class : sequential timing path Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 7.137 - Launch Clock Delay : 7.137 + Capture Clock Delay : 5.766 + Launch Clock Delay : 5.766 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -6469,23 +6913,23 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 4.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 5.214 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 5.308 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 5.913 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKIN (GTP_IOCLKBUF) - td 0.306 6.219 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) - net (fanout=28) 0.918 7.137 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + td 0.306 4.848 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) + net (fanout=28) 0.918 5.766 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/CLKA (GTP_DDC_E1) - tco 0.464 7.601 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[1] (GTP_DDC_E1) - net (fanout=8) 0.730 8.331 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [1] + tco 0.464 6.230 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[1] (GTP_DDC_E1) + net (fanout=8) 0.730 6.960 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [1] f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[1] (GTP_ISERDES) - Data arrival time 8.331 Logic Levels: 0 + Data arrival time 6.960 Logic Levels: 0 Logic: 0.464ns(38.861%), Route: 0.730ns(61.139%) ---------------------------------------------------------------------------------------------------- @@ -6497,26 +6941,26 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 4.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 5.214 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 5.308 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 5.913 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKIN (GTP_IOCLKBUF) - td 0.306 6.219 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) - net (fanout=28) 0.918 7.137 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + td 0.306 4.848 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) + net (fanout=28) 0.918 5.766 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/DESCLK (GTP_ISERDES) - clock pessimism 0.000 7.137 - clock uncertainty 0.000 7.137 + clock pessimism 0.000 5.766 + clock uncertainty 0.000 5.766 - Hold time 0.001 7.138 + Hold time 0.001 5.767 - Data required time 7.138 + Data required time 5.767 ---------------------------------------------------------------------------------------------------- - Data required time 7.138 - Data arrival time 8.331 + Data required time 5.767 + Data arrival time 6.960 ---------------------------------------------------------------------------------------------------- Slack (MET) 1.193 ==================================================================================================== @@ -6529,8 +6973,8 @@ Path Group : ioclk1 Path Type : min (slow corner) Path Class : sequential timing path Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 7.137 - Launch Clock Delay : 7.137 + Capture Clock Delay : 5.766 + Launch Clock Delay : 5.766 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -6544,23 +6988,23 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 4.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 5.214 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 5.308 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 5.913 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKIN (GTP_IOCLKBUF) - td 0.306 6.219 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) - net (fanout=28) 0.918 7.137 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + td 0.306 4.848 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) + net (fanout=28) 0.918 5.766 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/CLKA (GTP_DDC_E1) - tco 0.464 7.601 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[2] (GTP_DDC_E1) - net (fanout=8) 0.730 8.331 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [2] + tco 0.464 6.230 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[2] (GTP_DDC_E1) + net (fanout=8) 0.730 6.960 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [2] f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[2] (GTP_ISERDES) - Data arrival time 8.331 Logic Levels: 0 + Data arrival time 6.960 Logic Levels: 0 Logic: 0.464ns(38.861%), Route: 0.730ns(61.139%) ---------------------------------------------------------------------------------------------------- @@ -6572,26 +7016,26 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 4.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 5.214 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 5.308 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 5.913 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKIN (GTP_IOCLKBUF) - td 0.306 6.219 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) - net (fanout=28) 0.918 7.137 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + td 0.306 4.848 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) + net (fanout=28) 0.918 5.766 u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/DESCLK (GTP_ISERDES) - clock pessimism 0.000 7.137 - clock uncertainty 0.000 7.137 + clock pessimism 0.000 5.766 + clock uncertainty 0.000 5.766 - Hold time 0.001 7.138 + Hold time 0.001 5.767 - Data required time 7.138 + Data required time 5.767 ---------------------------------------------------------------------------------------------------- - Data required time 7.138 - Data arrival time 8.331 + Data required time 5.767 + Data arrival time 6.960 ---------------------------------------------------------------------------------------------------- Slack (MET) 1.193 ==================================================================================================== @@ -6604,8 +7048,8 @@ Path Group : clk_50m Path Type : max (slow corner) Path Class : async timing path Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.526 - Launch Clock Delay : 5.526 + Capture Clock Delay : 5.523 + Launch Clock Delay : 5.523 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -6619,14 +7063,14 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.130 5.526 rd3_clk + net (fanout=2825) 3.127 5.523 rd3_clk r u_clk50m_rst/rst/CLK (GTP_DFF_P) - tco 0.323 5.849 f u_clk50m_rst/rst/Q (GTP_DFF_P) - net (fanout=1674) 2.408 8.257 rd3_rst + tco 0.323 5.846 f u_clk50m_rst/rst/Q (GTP_DFF_P) + net (fanout=1674) 2.408 8.254 rd3_rst f image_filiter_inst/multiline_buffer_inst/rst_s1/P (GTP_DFF_P) - Data arrival time 8.257 Logic Levels: 0 + Data arrival time 8.254 Logic Levels: 0 Logic: 0.323ns(11.827%), Route: 2.408ns(88.173%) ---------------------------------------------------------------------------------------------------- @@ -6638,17 +7082,17 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 22.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 22.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.130 25.526 rd3_clk + net (fanout=2825) 3.127 25.523 rd3_clk r image_filiter_inst/multiline_buffer_inst/rst_s1/CLK (GTP_DFF_P) - clock pessimism 0.000 25.526 - clock uncertainty -0.150 25.376 + clock pessimism 0.000 25.523 + clock uncertainty -0.150 25.373 - Recovery time -0.542 24.834 + Recovery time -0.542 24.831 - Data required time 24.834 + Data required time 24.831 ---------------------------------------------------------------------------------------------------- - Data required time 24.834 - Data arrival time 8.257 + Data required time 24.831 + Data arrival time 8.254 ---------------------------------------------------------------------------------------------------- Slack (MET) 16.577 ==================================================================================================== @@ -6661,8 +7105,8 @@ Path Group : clk_50m Path Type : max (slow corner) Path Class : async timing path Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.526 - Launch Clock Delay : 5.526 + Capture Clock Delay : 5.523 + Launch Clock Delay : 5.523 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -6676,14 +7120,14 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.130 5.526 rd3_clk + net (fanout=2825) 3.127 5.523 rd3_clk r u_clk50m_rst/rst/CLK (GTP_DFF_P) - tco 0.323 5.849 f u_clk50m_rst/rst/Q (GTP_DFF_P) - net (fanout=1674) 2.408 8.257 rd3_rst + tco 0.323 5.846 f u_clk50m_rst/rst/Q (GTP_DFF_P) + net (fanout=1674) 2.408 8.254 rd3_rst f image_filiter_inst/multiline_buffer_inst/srst/P (GTP_DFF_P) - Data arrival time 8.257 Logic Levels: 0 + Data arrival time 8.254 Logic Levels: 0 Logic: 0.323ns(11.827%), Route: 2.408ns(88.173%) ---------------------------------------------------------------------------------------------------- @@ -6695,17 +7139,17 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 22.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 22.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.130 25.526 rd3_clk + net (fanout=2825) 3.127 25.523 rd3_clk r image_filiter_inst/multiline_buffer_inst/srst/CLK (GTP_DFF_P) - clock pessimism 0.000 25.526 - clock uncertainty -0.150 25.376 + clock pessimism 0.000 25.523 + clock uncertainty -0.150 25.373 - Recovery time -0.542 24.834 + Recovery time -0.542 24.831 - Data required time 24.834 + Data required time 24.831 ---------------------------------------------------------------------------------------------------- - Data required time 24.834 - Data arrival time 8.257 + Data required time 24.831 + Data arrival time 8.254 ---------------------------------------------------------------------------------------------------- Slack (MET) 16.577 ==================================================================================================== @@ -6718,8 +7162,8 @@ Path Group : clk_50m Path Type : max (slow corner) Path Class : async timing path Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 5.526 - Launch Clock Delay : 5.526 + Capture Clock Delay : 5.523 + Launch Clock Delay : 5.523 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -6733,14 +7177,14 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.130 5.526 rd3_clk + net (fanout=2825) 3.127 5.523 rd3_clk r u_clk50m_rst/rst/CLK (GTP_DFF_P) - tco 0.323 5.849 f u_clk50m_rst/rst/Q (GTP_DFF_P) - net (fanout=1674) 2.408 8.257 rd3_rst + tco 0.323 5.846 f u_clk50m_rst/rst/Q (GTP_DFF_P) + net (fanout=1674) 2.408 8.254 rd3_rst f u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/P (GTP_DFF_P) - Data arrival time 8.257 Logic Levels: 0 + Data arrival time 8.254 Logic Levels: 0 Logic: 0.323ns(11.827%), Route: 2.408ns(88.173%) ---------------------------------------------------------------------------------------------------- @@ -6752,17 +7196,17 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 22.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 22.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.130 25.526 rd3_clk + net (fanout=2825) 3.127 25.523 rd3_clk r u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/CLK (GTP_DFF_P) - clock pessimism 0.000 25.526 - clock uncertainty -0.150 25.376 + clock pessimism 0.000 25.523 + clock uncertainty -0.150 25.373 - Recovery time -0.542 24.834 + Recovery time -0.542 24.831 - Data required time 24.834 + Data required time 24.831 ---------------------------------------------------------------------------------------------------- - Data required time 24.834 - Data arrival time 8.257 + Data required time 24.831 + Data arrival time 8.254 ---------------------------------------------------------------------------------------------------- Slack (MET) 16.577 ==================================================================================================== @@ -6774,9 +7218,9 @@ Endpoint : image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fi Path Group : clk_50m Path Type : min (slow corner) Path Class : async timing path -Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 6.040 - Launch Clock Delay : 5.526 +Clock Skew : 0.515 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 6.038 + Launch Clock Delay : 5.523 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -6790,14 +7234,14 @@ Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.130 5.526 rd3_clk + net (fanout=2825) 3.127 5.523 rd3_clk r image_filiter_inst/multiline_buffer_inst/srst/CLK (GTP_DFF_P) - tco 0.323 5.849 f image_filiter_inst/multiline_buffer_inst/srst/Q (GTP_DFF_P) - net (fanout=120) 1.502 7.351 image_filiter_inst/multiline_buffer_inst/srst + tco 0.323 5.846 f image_filiter_inst/multiline_buffer_inst/srst/Q (GTP_DFF_P) + net (fanout=120) 1.502 7.348 image_filiter_inst/multiline_buffer_inst/srst f image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/RSTB (GTP_DRM18K) - Data arrival time 7.351 Logic Levels: 0 + Data arrival time 7.348 Logic Levels: 0 Logic: 0.323ns(17.699%), Route: 1.502ns(82.301%) ---------------------------------------------------------------------------------------------------- @@ -6809,19 +7253,19 @@ Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.644 6.040 rd3_clk + net (fanout=2825) 3.642 6.038 rd3_clk r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKB (GTP_DRM18K) - clock pessimism 0.000 6.040 - clock uncertainty 0.000 6.040 + clock pessimism 0.000 6.038 + clock uncertainty 0.000 6.038 - Removal time -0.026 6.014 + Removal time -0.026 6.012 - Data required time 6.014 + Data required time 6.012 ---------------------------------------------------------------------------------------------------- - Data required time 6.014 - Data arrival time 7.351 + Data required time 6.012 + Data arrival time 7.348 ---------------------------------------------------------------------------------------------------- - Slack (MET) 1.337 + Slack (MET) 1.336 ==================================================================================================== ==================================================================================================== @@ -6831,9 +7275,9 @@ Endpoint : image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fi Path Group : clk_50m Path Type : min (slow corner) Path Class : async timing path -Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 6.040 - Launch Clock Delay : 5.526 +Clock Skew : 0.515 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 6.038 + Launch Clock Delay : 5.523 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -6847,14 +7291,14 @@ Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.130 5.526 rd3_clk + net (fanout=2825) 3.127 5.523 rd3_clk r image_filiter_inst/multiline_buffer_inst/srst/CLK (GTP_DFF_P) - tco 0.323 5.849 f image_filiter_inst/multiline_buffer_inst/srst/Q (GTP_DFF_P) - net (fanout=120) 1.502 7.351 image_filiter_inst/multiline_buffer_inst/srst + tco 0.323 5.846 f image_filiter_inst/multiline_buffer_inst/srst/Q (GTP_DFF_P) + net (fanout=120) 1.502 7.348 image_filiter_inst/multiline_buffer_inst/srst f image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/RSTB (GTP_DRM18K) - Data arrival time 7.351 Logic Levels: 0 + Data arrival time 7.348 Logic Levels: 0 Logic: 0.323ns(17.699%), Route: 1.502ns(82.301%) ---------------------------------------------------------------------------------------------------- @@ -6866,19 +7310,19 @@ Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.644 6.040 rd3_clk + net (fanout=2825) 3.642 6.038 rd3_clk r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKB (GTP_DRM18K) - clock pessimism 0.000 6.040 - clock uncertainty 0.000 6.040 + clock pessimism 0.000 6.038 + clock uncertainty 0.000 6.038 - Removal time -0.026 6.014 + Removal time -0.026 6.012 - Data required time 6.014 + Data required time 6.012 ---------------------------------------------------------------------------------------------------- - Data required time 6.014 - Data arrival time 7.351 + Data required time 6.012 + Data arrival time 7.348 ---------------------------------------------------------------------------------------------------- - Slack (MET) 1.337 + Slack (MET) 1.336 ==================================================================================================== ==================================================================================================== @@ -6888,9 +7332,9 @@ Endpoint : image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fi Path Group : clk_50m Path Type : min (slow corner) Path Class : async timing path -Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 6.040 - Launch Clock Delay : 5.526 +Clock Skew : 0.515 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 6.038 + Launch Clock Delay : 5.523 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -6904,14 +7348,14 @@ Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.130 5.526 rd3_clk + net (fanout=2825) 3.127 5.523 rd3_clk r image_filiter_inst/multiline_buffer_inst/srst/CLK (GTP_DFF_P) - tco 0.323 5.849 f image_filiter_inst/multiline_buffer_inst/srst/Q (GTP_DFF_P) - net (fanout=120) 1.502 7.351 image_filiter_inst/multiline_buffer_inst/srst + tco 0.323 5.846 f image_filiter_inst/multiline_buffer_inst/srst/Q (GTP_DFF_P) + net (fanout=120) 1.502 7.348 image_filiter_inst/multiline_buffer_inst/srst f image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/RSTB (GTP_DRM18K) - Data arrival time 7.351 Logic Levels: 0 + Data arrival time 7.348 Logic Levels: 0 Logic: 0.323ns(17.699%), Route: 1.502ns(82.301%) ---------------------------------------------------------------------------------------------------- @@ -6923,19 +7367,19 @@ Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.644 6.040 rd3_clk + net (fanout=2825) 3.642 6.038 rd3_clk r image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKB (GTP_DRM18K) - clock pessimism 0.000 6.040 - clock uncertainty 0.000 6.040 + clock pessimism 0.000 6.038 + clock uncertainty 0.000 6.038 - Removal time -0.026 6.014 + Removal time -0.026 6.012 - Data required time 6.014 + Data required time 6.012 ---------------------------------------------------------------------------------------------------- - Data required time 6.014 - Data arrival time 7.351 + Data required time 6.012 + Data arrival time 7.348 ---------------------------------------------------------------------------------------------------- - Slack (MET) 1.337 + Slack (MET) 1.336 ==================================================================================================== ==================================================================================================== @@ -6946,8 +7390,8 @@ Path Group : clk_200m Path Type : max (slow corner) Path Class : async timing path Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 6.563 - Launch Clock Delay : 6.563 + Capture Clock Delay : 5.192 + Launch Clock Delay : 5.192 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -6961,20 +7405,20 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 4.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 2.196 6.563 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 2.196 5.192 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/CLK (GTP_DFF_C) - tco 0.329 6.892 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/Q (GTP_DFF_C) - net (fanout=1) 0.000 6.892 u_axi_ddr_top/I_ipsxb_ddr_top/ddr_rstn + tco 0.329 5.521 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/Q (GTP_DFF_C) + net (fanout=1) 0.000 5.521 u_axi_ddr_top/I_ipsxb_ddr_top/ddr_rstn u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N17/I (GTP_INV) - td 0.000 6.892 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N17/Z (GTP_INV) - net (fanout=1809) 2.415 9.307 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/rst + td 0.000 5.521 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N17/Z (GTP_INV) + net (fanout=1809) 2.415 7.936 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/rst f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[0]/C (GTP_DFF_CE) - Data arrival time 9.307 Logic Levels: 1 + Data arrival time 7.936 Logic Levels: 1 Logic: 0.329ns(11.990%), Route: 2.415ns(88.010%) ---------------------------------------------------------------------------------------------------- @@ -6986,20 +7430,20 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 7.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 7.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 9.367 zoom_clk + net (fanout=7) 0.605 7.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 9.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 2.196 11.563 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 7.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 2.196 10.192 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[0]/CLK (GTP_DFF_CE) - clock pessimism 0.000 11.563 - clock uncertainty -0.150 11.413 + clock pessimism 0.000 10.192 + clock uncertainty -0.150 10.042 - Recovery time -0.542 10.871 + Recovery time -0.542 9.500 - Data required time 10.871 + Data required time 9.500 ---------------------------------------------------------------------------------------------------- - Data required time 10.871 - Data arrival time 9.307 + Data required time 9.500 + Data arrival time 7.936 ---------------------------------------------------------------------------------------------------- Slack (MET) 1.564 ==================================================================================================== @@ -7012,8 +7456,8 @@ Path Group : clk_200m Path Type : max (slow corner) Path Class : async timing path Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 6.563 - Launch Clock Delay : 6.563 + Capture Clock Delay : 5.192 + Launch Clock Delay : 5.192 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -7027,20 +7471,20 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 4.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 2.196 6.563 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 2.196 5.192 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/CLK (GTP_DFF_C) - tco 0.329 6.892 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/Q (GTP_DFF_C) - net (fanout=1) 0.000 6.892 u_axi_ddr_top/I_ipsxb_ddr_top/ddr_rstn + tco 0.329 5.521 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/Q (GTP_DFF_C) + net (fanout=1) 0.000 5.521 u_axi_ddr_top/I_ipsxb_ddr_top/ddr_rstn u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N17/I (GTP_INV) - td 0.000 6.892 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N17/Z (GTP_INV) - net (fanout=1809) 2.415 9.307 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/rst + td 0.000 5.521 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N17/Z (GTP_INV) + net (fanout=1809) 2.415 7.936 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/rst f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[1]/C (GTP_DFF_CE) - Data arrival time 9.307 Logic Levels: 1 + Data arrival time 7.936 Logic Levels: 1 Logic: 0.329ns(11.990%), Route: 2.415ns(88.010%) ---------------------------------------------------------------------------------------------------- @@ -7052,20 +7496,20 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 7.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 7.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 9.367 zoom_clk + net (fanout=7) 0.605 7.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 9.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 2.196 11.563 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 7.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 2.196 10.192 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[1]/CLK (GTP_DFF_CE) - clock pessimism 0.000 11.563 - clock uncertainty -0.150 11.413 + clock pessimism 0.000 10.192 + clock uncertainty -0.150 10.042 - Recovery time -0.542 10.871 + Recovery time -0.542 9.500 - Data required time 10.871 + Data required time 9.500 ---------------------------------------------------------------------------------------------------- - Data required time 10.871 - Data arrival time 9.307 + Data required time 9.500 + Data arrival time 7.936 ---------------------------------------------------------------------------------------------------- Slack (MET) 1.564 ==================================================================================================== @@ -7078,8 +7522,8 @@ Path Group : clk_200m Path Type : max (slow corner) Path Class : async timing path Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 6.563 - Launch Clock Delay : 6.563 + Capture Clock Delay : 5.192 + Launch Clock Delay : 5.192 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -7093,20 +7537,20 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 4.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 2.196 6.563 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 2.196 5.192 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/CLK (GTP_DFF_C) - tco 0.329 6.892 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/Q (GTP_DFF_C) - net (fanout=1) 0.000 6.892 u_axi_ddr_top/I_ipsxb_ddr_top/ddr_rstn + tco 0.329 5.521 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/Q (GTP_DFF_C) + net (fanout=1) 0.000 5.521 u_axi_ddr_top/I_ipsxb_ddr_top/ddr_rstn u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N17/I (GTP_INV) - td 0.000 6.892 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N17/Z (GTP_INV) - net (fanout=1809) 2.415 9.307 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/rst + td 0.000 5.521 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N17/Z (GTP_INV) + net (fanout=1809) 2.415 7.936 u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/rst f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[2]/C (GTP_DFF_CE) - Data arrival time 9.307 Logic Levels: 1 + Data arrival time 7.936 Logic Levels: 1 Logic: 0.329ns(11.990%), Route: 2.415ns(88.010%) ---------------------------------------------------------------------------------------------------- @@ -7118,20 +7562,20 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 7.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 7.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 9.367 zoom_clk + net (fanout=7) 0.605 7.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 9.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 2.196 11.563 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 7.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 2.196 10.192 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[2]/CLK (GTP_DFF_CE) - clock pessimism 0.000 11.563 - clock uncertainty -0.150 11.413 + clock pessimism 0.000 10.192 + clock uncertainty -0.150 10.042 - Recovery time -0.542 10.871 + Recovery time -0.542 9.500 - Data required time 10.871 + Data required time 9.500 ---------------------------------------------------------------------------------------------------- - Data required time 10.871 - Data arrival time 9.307 + Data required time 9.500 + Data arrival time 7.936 ---------------------------------------------------------------------------------------------------- Slack (MET) 1.564 ==================================================================================================== @@ -7144,8 +7588,8 @@ Path Group : clk_200m Path Type : min (slow corner) Path Class : async timing path Clock Skew : 2.196 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 6.563 - Launch Clock Delay : 4.367 + Capture Clock Delay : 5.192 + Launch Clock Delay : 2.996 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -7159,14 +7603,14 @@ Clock Skew : 2.196 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk r u_ddr_rst/rst/CLK (GTP_DFF_P) - tco 0.323 4.690 f u_ddr_rst/rst/Q (GTP_DFF_P) - net (fanout=2) 0.464 5.154 ddr_rst + tco 0.323 3.319 f u_ddr_rst/rst/Q (GTP_DFF_P) + net (fanout=2) 0.464 3.783 ddr_rst f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/C (GTP_DFF_C) - Data arrival time 5.154 Logic Levels: 0 + Data arrival time 3.783 Logic Levels: 0 Logic: 0.323ns(41.042%), Route: 0.464ns(58.958%) ---------------------------------------------------------------------------------------------------- @@ -7178,20 +7622,20 @@ Clock Skew : 2.196 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 4.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 2.196 6.563 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 2.196 5.192 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/CLK (GTP_DFF_C) - clock pessimism 0.000 6.563 - clock uncertainty 0.000 6.563 + clock pessimism 0.000 5.192 + clock uncertainty 0.000 5.192 - Removal time -0.251 6.312 + Removal time -0.251 4.941 - Data required time 6.312 + Data required time 4.941 ---------------------------------------------------------------------------------------------------- - Data required time 6.312 - Data arrival time 5.154 + Data required time 4.941 + Data arrival time 3.783 ---------------------------------------------------------------------------------------------------- Slack (VIOLATED) -1.158 ==================================================================================================== @@ -7204,8 +7648,8 @@ Path Group : clk_200m Path Type : min (slow corner) Path Class : async timing path Clock Skew : 2.196 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 6.563 - Launch Clock Delay : 4.367 + Capture Clock Delay : 5.192 + Launch Clock Delay : 2.996 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -7219,14 +7663,14 @@ Clock Skew : 2.196 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk r u_ddr_rst/rst/CLK (GTP_DFF_P) - tco 0.323 4.690 f u_ddr_rst/rst/Q (GTP_DFF_P) - net (fanout=2) 0.464 5.154 ddr_rst + tco 0.323 3.319 f u_ddr_rst/rst/Q (GTP_DFF_P) + net (fanout=2) 0.464 3.783 ddr_rst f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/C (GTP_DFF_C) - Data arrival time 5.154 Logic Levels: 0 + Data arrival time 3.783 Logic Levels: 0 Logic: 0.323ns(41.042%), Route: 0.464ns(58.958%) ---------------------------------------------------------------------------------------------------- @@ -7238,20 +7682,20 @@ Clock Skew : 2.196 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 4.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 2.196 6.563 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 2.196 5.192 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/CLK (GTP_DFF_C) - clock pessimism 0.000 6.563 - clock uncertainty 0.000 6.563 + clock pessimism 0.000 5.192 + clock uncertainty 0.000 5.192 - Removal time -0.251 6.312 + Removal time -0.251 4.941 - Data required time 6.312 + Data required time 4.941 ---------------------------------------------------------------------------------------------------- - Data required time 6.312 - Data arrival time 5.154 + Data required time 4.941 + Data arrival time 3.783 ---------------------------------------------------------------------------------------------------- Slack (VIOLATED) -1.158 ==================================================================================================== @@ -7264,8 +7708,8 @@ Path Group : clk_200m Path Type : min (slow corner) Path Class : async timing path Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 6.563 - Launch Clock Delay : 6.563 + Capture Clock Delay : 5.192 + Launch Clock Delay : 5.192 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -7279,20 +7723,20 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 4.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 2.196 6.563 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 2.196 5.192 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/CLK (GTP_DFF_C) - tco 0.329 6.892 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/Q (GTP_DFF_C) - net (fanout=1) 0.000 6.892 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/logic_rstn + tco 0.329 5.521 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/Q (GTP_DFF_C) + net (fanout=1) 0.000 5.521 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/logic_rstn u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/N0/I (GTP_INV) - td 0.000 6.892 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/N0/Z (GTP_INV) - net (fanout=22) 0.693 7.585 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/N0 + td 0.000 5.521 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/N0/Z (GTP_INV) + net (fanout=22) 0.693 6.214 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/N0 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[0]/C (GTP_DFF_C) - Data arrival time 7.585 Logic Levels: 1 + Data arrival time 6.214 Logic Levels: 1 Logic: 0.329ns(32.192%), Route: 0.693ns(67.808%) ---------------------------------------------------------------------------------------------------- @@ -7304,20 +7748,20 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 4.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 2.196 6.563 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 2.196 5.192 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[0]/CLK (GTP_DFF_C) - clock pessimism 0.000 6.563 - clock uncertainty 0.000 6.563 + clock pessimism 0.000 5.192 + clock uncertainty 0.000 5.192 - Removal time -0.251 6.312 + Removal time -0.251 4.941 - Data required time 6.312 + Data required time 4.941 ---------------------------------------------------------------------------------------------------- - Data required time 6.312 - Data arrival time 7.585 + Data required time 4.941 + Data arrival time 6.214 ---------------------------------------------------------------------------------------------------- Slack (MET) 1.273 ==================================================================================================== @@ -7444,14 +7888,392 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim ==================================================================================================== +Startpoint : u_zoom_rst/rst/CLK (GTP_DFF_P) +Endpoint : u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.rbin[0]/C (GTP_DFF_CE) +Path Group : clk_1080p60Hz +Path Type : max (slow corner) +Path Class : async timing path +Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 7.588 + Launch Clock Delay : 7.588 + Clock Pessimism Removal : 0.000 + + Location Delay Type Incr Path Logical Resource +---------------------------------------------------------------------------------------------------- + + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r + clk 0.000 0.000 r clk (port) + net (fanout=1) 0.000 0.000 clk + clk_ibuf/I (GTP_INBUF) + td 1.211 1.211 r clk_ibuf/O (GTP_INBUF) + net (fanout=1) 1.091 2.302 nt_clk + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=2825) 3.127 5.523 rd3_clk + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.094 5.617 r U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=844) 1.971 7.588 zoom_clk + r u_zoom_rst/rst/CLK (GTP_DFF_P) + + tco 0.323 7.911 f u_zoom_rst/rst/Q (GTP_DFF_P) + net (fanout=181) 1.169 9.080 zoom_rst + f u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.rbin[0]/C (GTP_DFF_CE) + + Data arrival time 9.080 Logic Levels: 0 + Logic: 0.323ns(21.649%), Route: 1.169ns(78.351%) +---------------------------------------------------------------------------------------------------- + + Clock clk_1080p60Hz (rising edge) 6.736 6.736 r + clk 0.000 6.736 r clk (port) + net (fanout=1) 0.000 6.736 clk + clk_ibuf/I (GTP_INBUF) + td 1.211 7.947 r clk_ibuf/O (GTP_INBUF) + net (fanout=1) 1.091 9.038 nt_clk + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.094 9.132 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=2825) 3.127 12.259 rd3_clk + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.094 12.353 r U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=844) 1.971 14.324 zoom_clk + r u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.rbin[0]/CLK (GTP_DFF_CE) + clock pessimism 0.000 14.324 + clock uncertainty -0.150 14.174 + + Recovery time -0.542 13.632 + + Data required time 13.632 +---------------------------------------------------------------------------------------------------- + Data required time 13.632 + Data arrival time 9.080 +---------------------------------------------------------------------------------------------------- + Slack (MET) 4.552 +==================================================================================================== + +==================================================================================================== + +Startpoint : u_zoom_rst/rst/CLK (GTP_DFF_P) +Endpoint : u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/C (GTP_DFF_CE) +Path Group : clk_1080p60Hz +Path Type : max (slow corner) +Path Class : async timing path +Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 7.588 + Launch Clock Delay : 7.588 + Clock Pessimism Removal : 0.000 + + Location Delay Type Incr Path Logical Resource +---------------------------------------------------------------------------------------------------- + + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r + clk 0.000 0.000 r clk (port) + net (fanout=1) 0.000 0.000 clk + clk_ibuf/I (GTP_INBUF) + td 1.211 1.211 r clk_ibuf/O (GTP_INBUF) + net (fanout=1) 1.091 2.302 nt_clk + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=2825) 3.127 5.523 rd3_clk + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.094 5.617 r U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=844) 1.971 7.588 zoom_clk + r u_zoom_rst/rst/CLK (GTP_DFF_P) + + tco 0.323 7.911 f u_zoom_rst/rst/Q (GTP_DFF_P) + net (fanout=181) 1.169 9.080 zoom_rst + f u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/C (GTP_DFF_CE) + + Data arrival time 9.080 Logic Levels: 0 + Logic: 0.323ns(21.649%), Route: 1.169ns(78.351%) +---------------------------------------------------------------------------------------------------- + + Clock clk_1080p60Hz (rising edge) 6.736 6.736 r + clk 0.000 6.736 r clk (port) + net (fanout=1) 0.000 6.736 clk + clk_ibuf/I (GTP_INBUF) + td 1.211 7.947 r clk_ibuf/O (GTP_INBUF) + net (fanout=1) 1.091 9.038 nt_clk + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.094 9.132 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=2825) 3.127 12.259 rd3_clk + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.094 12.353 r U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=844) 1.971 14.324 zoom_clk + r u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/CLK (GTP_DFF_CE) + clock pessimism 0.000 14.324 + clock uncertainty -0.150 14.174 + + Recovery time -0.542 13.632 + + Data required time 13.632 +---------------------------------------------------------------------------------------------------- + Data required time 13.632 + Data arrival time 9.080 +---------------------------------------------------------------------------------------------------- + Slack (MET) 4.552 +==================================================================================================== + +==================================================================================================== + +Startpoint : u_zoom_rst/rst/CLK (GTP_DFF_P) +Endpoint : u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.rbin[2]/C (GTP_DFF_CE) +Path Group : clk_1080p60Hz +Path Type : max (slow corner) +Path Class : async timing path +Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 7.588 + Launch Clock Delay : 7.588 + Clock Pessimism Removal : 0.000 + + Location Delay Type Incr Path Logical Resource +---------------------------------------------------------------------------------------------------- + + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r + clk 0.000 0.000 r clk (port) + net (fanout=1) 0.000 0.000 clk + clk_ibuf/I (GTP_INBUF) + td 1.211 1.211 r clk_ibuf/O (GTP_INBUF) + net (fanout=1) 1.091 2.302 nt_clk + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=2825) 3.127 5.523 rd3_clk + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.094 5.617 r U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=844) 1.971 7.588 zoom_clk + r u_zoom_rst/rst/CLK (GTP_DFF_P) + + tco 0.323 7.911 f u_zoom_rst/rst/Q (GTP_DFF_P) + net (fanout=181) 1.169 9.080 zoom_rst + f u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.rbin[2]/C (GTP_DFF_CE) + + Data arrival time 9.080 Logic Levels: 0 + Logic: 0.323ns(21.649%), Route: 1.169ns(78.351%) +---------------------------------------------------------------------------------------------------- + + Clock clk_1080p60Hz (rising edge) 6.736 6.736 r + clk 0.000 6.736 r clk (port) + net (fanout=1) 0.000 6.736 clk + clk_ibuf/I (GTP_INBUF) + td 1.211 7.947 r clk_ibuf/O (GTP_INBUF) + net (fanout=1) 1.091 9.038 nt_clk + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.094 9.132 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=2825) 3.127 12.259 rd3_clk + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.094 12.353 r U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=844) 1.971 14.324 zoom_clk + r u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.rbin[2]/CLK (GTP_DFF_CE) + clock pessimism 0.000 14.324 + clock uncertainty -0.150 14.174 + + Recovery time -0.542 13.632 + + Data required time 13.632 +---------------------------------------------------------------------------------------------------- + Data required time 13.632 + Data arrival time 9.080 +---------------------------------------------------------------------------------------------------- + Slack (MET) 4.552 +==================================================================================================== + +==================================================================================================== + +Startpoint : u_zoom_rst/rst/CLK (GTP_DFF_P) +Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/RSTA (GTP_DRM18K) +Path Group : clk_1080p60Hz +Path Type : min (slow corner) +Path Class : async timing path +Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 8.102 + Launch Clock Delay : 7.588 + Clock Pessimism Removal : 0.000 + + Location Delay Type Incr Path Logical Resource +---------------------------------------------------------------------------------------------------- + + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r + clk 0.000 0.000 r clk (port) + net (fanout=1) 0.000 0.000 clk + clk_ibuf/I (GTP_INBUF) + td 1.211 1.211 r clk_ibuf/O (GTP_INBUF) + net (fanout=1) 1.091 2.302 nt_clk + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=2825) 3.127 5.523 rd3_clk + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.094 5.617 r U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=844) 1.971 7.588 zoom_clk + r u_zoom_rst/rst/CLK (GTP_DFF_P) + + tco 0.323 7.911 f u_zoom_rst/rst/Q (GTP_DFF_P) + net (fanout=181) 1.683 9.594 zoom_rst + f u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/RSTA (GTP_DRM18K) + + Data arrival time 9.594 Logic Levels: 0 + Logic: 0.323ns(16.102%), Route: 1.683ns(83.898%) +---------------------------------------------------------------------------------------------------- + + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r + clk 0.000 0.000 r clk (port) + net (fanout=1) 0.000 0.000 clk + clk_ibuf/I (GTP_INBUF) + td 1.211 1.211 r clk_ibuf/O (GTP_INBUF) + net (fanout=1) 1.091 2.302 nt_clk + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=2825) 3.127 5.523 rd3_clk + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.094 5.617 r U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=844) 2.485 8.102 zoom_clk + r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (GTP_DRM18K) + clock pessimism 0.000 8.102 + clock uncertainty 0.000 8.102 + + Removal time -0.053 8.049 + + Data required time 8.049 +---------------------------------------------------------------------------------------------------- + Data required time 8.049 + Data arrival time 9.594 +---------------------------------------------------------------------------------------------------- + Slack (MET) 1.545 +==================================================================================================== + +==================================================================================================== + +Startpoint : u_zoom_rst/rst/CLK (GTP_DFF_P) +Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/RSTA (GTP_DRM18K) +Path Group : clk_1080p60Hz +Path Type : min (slow corner) +Path Class : async timing path +Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 8.102 + Launch Clock Delay : 7.588 + Clock Pessimism Removal : 0.000 + + Location Delay Type Incr Path Logical Resource +---------------------------------------------------------------------------------------------------- + + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r + clk 0.000 0.000 r clk (port) + net (fanout=1) 0.000 0.000 clk + clk_ibuf/I (GTP_INBUF) + td 1.211 1.211 r clk_ibuf/O (GTP_INBUF) + net (fanout=1) 1.091 2.302 nt_clk + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=2825) 3.127 5.523 rd3_clk + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.094 5.617 r U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=844) 1.971 7.588 zoom_clk + r u_zoom_rst/rst/CLK (GTP_DFF_P) + + tco 0.323 7.911 f u_zoom_rst/rst/Q (GTP_DFF_P) + net (fanout=181) 1.683 9.594 zoom_rst + f u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/RSTA (GTP_DRM18K) + + Data arrival time 9.594 Logic Levels: 0 + Logic: 0.323ns(16.102%), Route: 1.683ns(83.898%) +---------------------------------------------------------------------------------------------------- + + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r + clk 0.000 0.000 r clk (port) + net (fanout=1) 0.000 0.000 clk + clk_ibuf/I (GTP_INBUF) + td 1.211 1.211 r clk_ibuf/O (GTP_INBUF) + net (fanout=1) 1.091 2.302 nt_clk + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=2825) 3.127 5.523 rd3_clk + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.094 5.617 r U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=844) 2.485 8.102 zoom_clk + r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKA (GTP_DRM18K) + clock pessimism 0.000 8.102 + clock uncertainty 0.000 8.102 + + Removal time -0.053 8.049 + + Data required time 8.049 +---------------------------------------------------------------------------------------------------- + Data required time 8.049 + Data arrival time 9.594 +---------------------------------------------------------------------------------------------------- + Slack (MET) 1.545 +==================================================================================================== + +==================================================================================================== + +Startpoint : u_zoom_rst/rst/CLK (GTP_DFF_P) +Endpoint : u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM18K/RSTA (GTP_DRM18K) +Path Group : clk_1080p60Hz +Path Type : min (slow corner) +Path Class : async timing path +Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) + Capture Clock Delay : 8.102 + Launch Clock Delay : 7.588 + Clock Pessimism Removal : 0.000 + + Location Delay Type Incr Path Logical Resource +---------------------------------------------------------------------------------------------------- + + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r + clk 0.000 0.000 r clk (port) + net (fanout=1) 0.000 0.000 clk + clk_ibuf/I (GTP_INBUF) + td 1.211 1.211 r clk_ibuf/O (GTP_INBUF) + net (fanout=1) 1.091 2.302 nt_clk + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=2825) 3.127 5.523 rd3_clk + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.094 5.617 r U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=844) 1.971 7.588 zoom_clk + r u_zoom_rst/rst/CLK (GTP_DFF_P) + + tco 0.323 7.911 f u_zoom_rst/rst/Q (GTP_DFF_P) + net (fanout=181) 1.683 9.594 zoom_rst + f u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM18K/RSTA (GTP_DRM18K) + + Data arrival time 9.594 Logic Levels: 0 + Logic: 0.323ns(16.102%), Route: 1.683ns(83.898%) +---------------------------------------------------------------------------------------------------- + + Clock clk_1080p60Hz (rising edge) 0.000 0.000 r + clk 0.000 0.000 r clk (port) + net (fanout=1) 0.000 0.000 clk + clk_ibuf/I (GTP_INBUF) + td 1.211 1.211 r clk_ibuf/O (GTP_INBUF) + net (fanout=1) 1.091 2.302 nt_clk + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=2825) 3.127 5.523 rd3_clk + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) + td 0.094 5.617 r U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=844) 2.485 8.102 zoom_clk + r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM18K/CLKA (GTP_DRM18K) + clock pessimism 0.000 8.102 + clock uncertainty 0.000 8.102 + + Removal time -0.053 8.049 + + Data required time 8.049 +---------------------------------------------------------------------------------------------------- + Data required time 8.049 + Data arrival time 9.594 +---------------------------------------------------------------------------------------------------- + Slack (MET) 1.545 +==================================================================================================== + +==================================================================================================== + Startpoint : sync_vg_100m/CLK (GTP_DFF_P) Endpoint : adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[5]/C (GTP_DFF_C) Path Group : clk_720p60Hz Path Type : max (slow corner) Path Class : async timing path Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 8.073 - Launch Clock Delay : 8.073 + Capture Clock Delay : 8.070 + Launch Clock Delay : 8.070 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -7465,17 +8287,17 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.130 5.526 rd3_clk + net (fanout=2825) 3.127 5.523 rd3_clk U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.089 5.615 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=1758) 2.458 8.073 nt_pix_clk + td 0.089 5.612 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + net (fanout=1758) 2.458 8.070 nt_pix_clk r sync_vg_100m/CLK (GTP_DFF_P) - tco 0.323 8.396 f sync_vg_100m/Q (GTP_DFF_P) - net (fanout=2548) 2.954 11.350 sync_vg_100m + tco 0.323 8.393 f sync_vg_100m/Q (GTP_DFF_P) + net (fanout=2548) 2.954 11.347 sync_vg_100m f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[5]/C (GTP_DFF_C) - Data arrival time 11.350 Logic Levels: 0 + Data arrival time 11.347 Logic Levels: 0 Logic: 0.323ns(9.857%), Route: 2.954ns(90.143%) ---------------------------------------------------------------------------------------------------- @@ -7487,20 +8309,20 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 15.775 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 15.869 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.130 18.999 rd3_clk + net (fanout=2825) 3.127 18.996 rd3_clk U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.089 19.088 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=1758) 2.458 21.546 nt_pix_clk + td 0.089 19.085 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + net (fanout=1758) 2.458 21.543 nt_pix_clk r adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[5]/CLK (GTP_DFF_C) - clock pessimism 0.000 21.546 - clock uncertainty -0.150 21.396 + clock pessimism 0.000 21.543 + clock uncertainty -0.150 21.393 - Recovery time -0.542 20.854 + Recovery time -0.542 20.851 - Data required time 20.854 + Data required time 20.851 ---------------------------------------------------------------------------------------------------- - Data required time 20.854 - Data arrival time 11.350 + Data required time 20.851 + Data arrival time 11.347 ---------------------------------------------------------------------------------------------------- Slack (MET) 9.504 ==================================================================================================== @@ -7513,8 +8335,8 @@ Path Group : clk_720p60Hz Path Type : max (slow corner) Path Class : async timing path Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 8.073 - Launch Clock Delay : 8.073 + Capture Clock Delay : 8.070 + Launch Clock Delay : 8.070 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -7528,17 +8350,17 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.130 5.526 rd3_clk + net (fanout=2825) 3.127 5.523 rd3_clk U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.089 5.615 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=1758) 2.458 8.073 nt_pix_clk + td 0.089 5.612 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + net (fanout=1758) 2.458 8.070 nt_pix_clk r sync_vg_100m/CLK (GTP_DFF_P) - tco 0.323 8.396 f sync_vg_100m/Q (GTP_DFF_P) - net (fanout=2548) 2.954 11.350 sync_vg_100m + tco 0.323 8.393 f sync_vg_100m/Q (GTP_DFF_P) + net (fanout=2548) 2.954 11.347 sync_vg_100m f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[6]/C (GTP_DFF_C) - Data arrival time 11.350 Logic Levels: 0 + Data arrival time 11.347 Logic Levels: 0 Logic: 0.323ns(9.857%), Route: 2.954ns(90.143%) ---------------------------------------------------------------------------------------------------- @@ -7550,20 +8372,20 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 15.775 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 15.869 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.130 18.999 rd3_clk + net (fanout=2825) 3.127 18.996 rd3_clk U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.089 19.088 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=1758) 2.458 21.546 nt_pix_clk + td 0.089 19.085 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + net (fanout=1758) 2.458 21.543 nt_pix_clk r adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[6]/CLK (GTP_DFF_C) - clock pessimism 0.000 21.546 - clock uncertainty -0.150 21.396 + clock pessimism 0.000 21.543 + clock uncertainty -0.150 21.393 - Recovery time -0.542 20.854 + Recovery time -0.542 20.851 - Data required time 20.854 + Data required time 20.851 ---------------------------------------------------------------------------------------------------- - Data required time 20.854 - Data arrival time 11.350 + Data required time 20.851 + Data arrival time 11.347 ---------------------------------------------------------------------------------------------------- Slack (MET) 9.504 ==================================================================================================== @@ -7576,8 +8398,8 @@ Path Group : clk_720p60Hz Path Type : max (slow corner) Path Class : async timing path Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 8.073 - Launch Clock Delay : 8.073 + Capture Clock Delay : 8.070 + Launch Clock Delay : 8.070 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -7591,17 +8413,17 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.130 5.526 rd3_clk + net (fanout=2825) 3.127 5.523 rd3_clk U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.089 5.615 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=1758) 2.458 8.073 nt_pix_clk + td 0.089 5.612 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + net (fanout=1758) 2.458 8.070 nt_pix_clk r sync_vg_100m/CLK (GTP_DFF_P) - tco 0.323 8.396 f sync_vg_100m/Q (GTP_DFF_P) - net (fanout=2548) 2.954 11.350 sync_vg_100m + tco 0.323 8.393 f sync_vg_100m/Q (GTP_DFF_P) + net (fanout=2548) 2.954 11.347 sync_vg_100m f adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[7]/C (GTP_DFF_C) - Data arrival time 11.350 Logic Levels: 0 + Data arrival time 11.347 Logic Levels: 0 Logic: 0.323ns(9.857%), Route: 2.954ns(90.143%) ---------------------------------------------------------------------------------------------------- @@ -7613,20 +8435,20 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 15.775 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 15.869 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.130 18.999 rd3_clk + net (fanout=2825) 3.127 18.996 rd3_clk U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.089 19.088 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=1758) 2.458 21.546 nt_pix_clk + td 0.089 19.085 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + net (fanout=1758) 2.458 21.543 nt_pix_clk r adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[7]/CLK (GTP_DFF_C) - clock pessimism 0.000 21.546 - clock uncertainty -0.150 21.396 + clock pessimism 0.000 21.543 + clock uncertainty -0.150 21.393 - Recovery time -0.542 20.854 + Recovery time -0.542 20.851 - Data required time 20.854 + Data required time 20.851 ---------------------------------------------------------------------------------------------------- - Data required time 20.854 - Data arrival time 11.350 + Data required time 20.851 + Data arrival time 11.347 ---------------------------------------------------------------------------------------------------- Slack (MET) 9.504 ==================================================================================================== @@ -7639,8 +8461,8 @@ Path Group : clk_720p60Hz Path Type : min (slow corner) Path Class : async timing path Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 8.587 - Launch Clock Delay : 8.073 + Capture Clock Delay : 8.584 + Launch Clock Delay : 8.070 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -7654,17 +8476,17 @@ Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.130 5.526 rd3_clk + net (fanout=2825) 3.127 5.523 rd3_clk U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.089 5.615 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=1758) 2.458 8.073 nt_pix_clk + td 0.089 5.612 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + net (fanout=1758) 2.458 8.070 nt_pix_clk r u_hdmi_rst/rst/CLK (GTP_DFF_P) - tco 0.323 8.396 f u_hdmi_rst/rst/Q (GTP_DFF_P) - net (fanout=219) 1.773 10.169 rd2_rst + tco 0.323 8.393 f u_hdmi_rst/rst/Q (GTP_DFF_P) + net (fanout=219) 1.773 10.166 rd2_rst f u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/RSTB (GTP_DRM18K) - Data arrival time 10.169 Logic Levels: 0 + Data arrival time 10.166 Logic Levels: 0 Logic: 0.323ns(15.410%), Route: 1.773ns(84.590%) ---------------------------------------------------------------------------------------------------- @@ -7676,20 +8498,20 @@ Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.130 5.526 rd3_clk + net (fanout=2825) 3.127 5.523 rd3_clk U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.089 5.615 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=1758) 2.972 8.587 nt_pix_clk + td 0.089 5.612 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + net (fanout=1758) 2.972 8.584 nt_pix_clk r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKB (GTP_DRM18K) - clock pessimism 0.000 8.587 - clock uncertainty 0.000 8.587 + clock pessimism 0.000 8.584 + clock uncertainty 0.000 8.584 - Removal time -0.026 8.561 + Removal time -0.026 8.558 - Data required time 8.561 + Data required time 8.558 ---------------------------------------------------------------------------------------------------- - Data required time 8.561 - Data arrival time 10.169 + Data required time 8.558 + Data arrival time 10.166 ---------------------------------------------------------------------------------------------------- Slack (MET) 1.608 ==================================================================================================== @@ -7702,8 +8524,8 @@ Path Group : clk_720p60Hz Path Type : min (slow corner) Path Class : async timing path Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 8.587 - Launch Clock Delay : 8.073 + Capture Clock Delay : 8.584 + Launch Clock Delay : 8.070 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -7717,17 +8539,17 @@ Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.130 5.526 rd3_clk + net (fanout=2825) 3.127 5.523 rd3_clk U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.089 5.615 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=1758) 2.458 8.073 nt_pix_clk + td 0.089 5.612 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + net (fanout=1758) 2.458 8.070 nt_pix_clk r u_hdmi_rst/rst/CLK (GTP_DFF_P) - tco 0.323 8.396 f u_hdmi_rst/rst/Q (GTP_DFF_P) - net (fanout=219) 1.773 10.169 rd2_rst + tco 0.323 8.393 f u_hdmi_rst/rst/Q (GTP_DFF_P) + net (fanout=219) 1.773 10.166 rd2_rst f u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/RSTB (GTP_DRM18K) - Data arrival time 10.169 Logic Levels: 0 + Data arrival time 10.166 Logic Levels: 0 Logic: 0.323ns(15.410%), Route: 1.773ns(84.590%) ---------------------------------------------------------------------------------------------------- @@ -7739,20 +8561,20 @@ Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.130 5.526 rd3_clk + net (fanout=2825) 3.127 5.523 rd3_clk U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.089 5.615 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=1758) 2.972 8.587 nt_pix_clk + td 0.089 5.612 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + net (fanout=1758) 2.972 8.584 nt_pix_clk r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKB (GTP_DRM18K) - clock pessimism 0.000 8.587 - clock uncertainty 0.000 8.587 + clock pessimism 0.000 8.584 + clock uncertainty 0.000 8.584 - Removal time -0.026 8.561 + Removal time -0.026 8.558 - Data required time 8.561 + Data required time 8.558 ---------------------------------------------------------------------------------------------------- - Data required time 8.561 - Data arrival time 10.169 + Data required time 8.558 + Data arrival time 10.166 ---------------------------------------------------------------------------------------------------- Slack (MET) 1.608 ==================================================================================================== @@ -7765,8 +8587,8 @@ Path Group : clk_720p60Hz Path Type : min (slow corner) Path Class : async timing path Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 8.587 - Launch Clock Delay : 8.073 + Capture Clock Delay : 8.584 + Launch Clock Delay : 8.070 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -7780,17 +8602,17 @@ Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.130 5.526 rd3_clk + net (fanout=2825) 3.127 5.523 rd3_clk U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.089 5.615 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=1758) 2.458 8.073 nt_pix_clk + td 0.089 5.612 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + net (fanout=1758) 2.458 8.070 nt_pix_clk r u_hdmi_rst/rst/CLK (GTP_DFF_P) - tco 0.323 8.396 f u_hdmi_rst/rst/Q (GTP_DFF_P) - net (fanout=219) 1.773 10.169 rd2_rst + tco 0.323 8.393 f u_hdmi_rst/rst/Q (GTP_DFF_P) + net (fanout=219) 1.773 10.166 rd2_rst f u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM18K/RSTB (GTP_DRM18K) - Data arrival time 10.169 Logic Levels: 0 + Data arrival time 10.166 Logic Levels: 0 Logic: 0.323ns(15.410%), Route: 1.773ns(84.590%) ---------------------------------------------------------------------------------------------------- @@ -7802,20 +8624,20 @@ Clock Skew : 0.514 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.130 5.526 rd3_clk + net (fanout=2825) 3.127 5.523 rd3_clk U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.089 5.615 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=1758) 2.972 8.587 nt_pix_clk + td 0.089 5.612 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + net (fanout=1758) 2.972 8.584 nt_pix_clk r u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM18K/CLKB (GTP_DRM18K) - clock pessimism 0.000 8.587 - clock uncertainty 0.000 8.587 + clock pessimism 0.000 8.584 + clock uncertainty 0.000 8.584 - Removal time -0.026 8.561 + Removal time -0.026 8.558 - Data required time 8.561 + Data required time 8.558 ---------------------------------------------------------------------------------------------------- - Data required time 8.561 - Data arrival time 10.169 + Data required time 8.558 + Data arrival time 10.166 ---------------------------------------------------------------------------------------------------- Slack (MET) 1.608 ==================================================================================================== @@ -7828,8 +8650,8 @@ Path Group : ddrphy_clkin Path Type : max (slow corner) Path Class : async timing path Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 9.059 - Launch Clock Delay : 9.059 + Capture Clock Delay : 7.688 + Launch Clock Delay : 7.688 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -7843,26 +8665,26 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 4.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 5.214 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 5.308 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 5.913 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) - td 0.000 5.913 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) - net (fanout=5817) 3.146 9.059 u_axi_ddr_top/clk + td 0.000 4.542 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + net (fanout=5817) 3.146 7.688 u_axi_ddr_top/clk r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/CLK (GTP_DFF_C) - tco 0.329 9.388 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/Q (GTP_DFF_C) - net (fanout=1) 0.000 9.388 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n + tco 0.329 8.017 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/Q (GTP_DFF_C) + net (fanout=1) 0.000 8.017 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/N0/I (GTP_INV) - td 0.000 9.388 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/N0/Z (GTP_INV) - net (fanout=2275) 2.706 12.094 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/N0 + td 0.000 8.017 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/N0/Z (GTP_INV) + net (fanout=2275) 2.706 10.723 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/N0 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[0]/C (GTP_DFF_C) - Data arrival time 12.094 Logic Levels: 1 + Data arrival time 10.723 Logic Levels: 1 Logic: 0.329ns(10.840%), Route: 2.706ns(89.160%) ---------------------------------------------------------------------------------------------------- @@ -7874,26 +8696,26 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 12.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 12.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 14.367 zoom_clk + net (fanout=7) 0.605 12.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 14.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 15.214 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 12.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 13.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 15.308 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 15.913 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 13.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 14.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) - td 0.000 15.913 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) - net (fanout=5817) 3.146 19.059 u_axi_ddr_top/clk + td 0.000 14.542 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + net (fanout=5817) 3.146 17.688 u_axi_ddr_top/clk r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[0]/CLK (GTP_DFF_C) - clock pessimism 0.000 19.059 - clock uncertainty -0.150 18.909 + clock pessimism 0.000 17.688 + clock uncertainty -0.150 17.538 - Recovery time -0.542 18.367 + Recovery time -0.542 16.996 - Data required time 18.367 + Data required time 16.996 ---------------------------------------------------------------------------------------------------- - Data required time 18.367 - Data arrival time 12.094 + Data required time 16.996 + Data arrival time 10.723 ---------------------------------------------------------------------------------------------------- Slack (MET) 6.273 ==================================================================================================== @@ -7906,8 +8728,8 @@ Path Group : ddrphy_clkin Path Type : max (slow corner) Path Class : async timing path Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 9.059 - Launch Clock Delay : 9.059 + Capture Clock Delay : 7.688 + Launch Clock Delay : 7.688 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -7921,26 +8743,26 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 4.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 5.214 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 5.308 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 5.913 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) - td 0.000 5.913 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) - net (fanout=5817) 3.146 9.059 u_axi_ddr_top/clk + td 0.000 4.542 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + net (fanout=5817) 3.146 7.688 u_axi_ddr_top/clk r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/CLK (GTP_DFF_C) - tco 0.329 9.388 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/Q (GTP_DFF_C) - net (fanout=1) 0.000 9.388 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n + tco 0.329 8.017 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/Q (GTP_DFF_C) + net (fanout=1) 0.000 8.017 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/N0/I (GTP_INV) - td 0.000 9.388 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/N0/Z (GTP_INV) - net (fanout=2275) 2.706 12.094 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/N0 + td 0.000 8.017 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/N0/Z (GTP_INV) + net (fanout=2275) 2.706 10.723 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/N0 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[1]/C (GTP_DFF_C) - Data arrival time 12.094 Logic Levels: 1 + Data arrival time 10.723 Logic Levels: 1 Logic: 0.329ns(10.840%), Route: 2.706ns(89.160%) ---------------------------------------------------------------------------------------------------- @@ -7952,26 +8774,26 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 12.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 12.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 14.367 zoom_clk + net (fanout=7) 0.605 12.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 14.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 15.214 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 12.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 13.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 15.308 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 15.913 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 13.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 14.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) - td 0.000 15.913 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) - net (fanout=5817) 3.146 19.059 u_axi_ddr_top/clk + td 0.000 14.542 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + net (fanout=5817) 3.146 17.688 u_axi_ddr_top/clk r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[1]/CLK (GTP_DFF_C) - clock pessimism 0.000 19.059 - clock uncertainty -0.150 18.909 + clock pessimism 0.000 17.688 + clock uncertainty -0.150 17.538 - Recovery time -0.542 18.367 + Recovery time -0.542 16.996 - Data required time 18.367 + Data required time 16.996 ---------------------------------------------------------------------------------------------------- - Data required time 18.367 - Data arrival time 12.094 + Data required time 16.996 + Data arrival time 10.723 ---------------------------------------------------------------------------------------------------- Slack (MET) 6.273 ==================================================================================================== @@ -7984,8 +8806,8 @@ Path Group : ddrphy_clkin Path Type : max (slow corner) Path Class : async timing path Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 9.059 - Launch Clock Delay : 9.059 + Capture Clock Delay : 7.688 + Launch Clock Delay : 7.688 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -7999,26 +8821,26 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 4.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 5.214 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 5.308 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 5.913 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) - td 0.000 5.913 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) - net (fanout=5817) 3.146 9.059 u_axi_ddr_top/clk + td 0.000 4.542 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + net (fanout=5817) 3.146 7.688 u_axi_ddr_top/clk r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/CLK (GTP_DFF_C) - tco 0.329 9.388 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/Q (GTP_DFF_C) - net (fanout=1) 0.000 9.388 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n + tco 0.329 8.017 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/Q (GTP_DFF_C) + net (fanout=1) 0.000 8.017 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/N0/I (GTP_INV) - td 0.000 9.388 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/N0/Z (GTP_INV) - net (fanout=2275) 2.706 12.094 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/N0 + td 0.000 8.017 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/N0/Z (GTP_INV) + net (fanout=2275) 2.706 10.723 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/N0 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[2]/C (GTP_DFF_C) - Data arrival time 12.094 Logic Levels: 1 + Data arrival time 10.723 Logic Levels: 1 Logic: 0.329ns(10.840%), Route: 2.706ns(89.160%) ---------------------------------------------------------------------------------------------------- @@ -8030,26 +8852,26 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 12.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 12.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 14.367 zoom_clk + net (fanout=7) 0.605 12.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 14.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 15.214 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 12.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 13.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 15.308 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 15.913 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 13.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 14.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) - td 0.000 15.913 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) - net (fanout=5817) 3.146 19.059 u_axi_ddr_top/clk + td 0.000 14.542 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + net (fanout=5817) 3.146 17.688 u_axi_ddr_top/clk r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[2]/CLK (GTP_DFF_C) - clock pessimism 0.000 19.059 - clock uncertainty -0.150 18.909 + clock pessimism 0.000 17.688 + clock uncertainty -0.150 17.538 - Recovery time -0.542 18.367 + Recovery time -0.542 16.996 - Data required time 18.367 + Data required time 16.996 ---------------------------------------------------------------------------------------------------- - Data required time 18.367 - Data arrival time 12.094 + Data required time 16.996 + Data arrival time 10.723 ---------------------------------------------------------------------------------------------------- Slack (MET) 6.273 ==================================================================================================== @@ -8062,8 +8884,8 @@ Path Group : ddrphy_clkin Path Type : min (slow corner) Path Class : async timing path Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 9.059 - Launch Clock Delay : 9.059 + Capture Clock Delay : 7.688 + Launch Clock Delay : 7.688 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -8077,23 +8899,23 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 4.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 5.214 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 5.308 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 5.913 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) - td 0.000 5.913 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) - net (fanout=5817) 3.146 9.059 u_axi_ddr_top/clk + td 0.000 4.542 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + net (fanout=5817) 3.146 7.688 u_axi_ddr_top/clk r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_dqs_training_rstn/CLK (GTP_DFF_C) - tco 0.323 9.382 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_dqs_training_rstn/Q (GTP_DFF_C) - net (fanout=10) 0.758 10.140 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dqs_training_rstn + tco 0.323 8.011 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_dqs_training_rstn/Q (GTP_DFF_C) + net (fanout=10) 0.758 8.769 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dqs_training_rstn f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_ddc_ca/RST_TRAINING_N (GTP_DDC_E1) - Data arrival time 10.140 Logic Levels: 0 + Data arrival time 8.769 Logic Levels: 0 Logic: 0.323ns(29.880%), Route: 0.758ns(70.120%) ---------------------------------------------------------------------------------------------------- @@ -8105,26 +8927,26 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 4.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 5.214 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 5.308 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 5.913 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) - td 0.000 5.913 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) - net (fanout=5817) 3.146 9.059 u_axi_ddr_top/clk + td 0.000 4.542 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + net (fanout=5817) 3.146 7.688 u_axi_ddr_top/clk r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_ddc_ca/CLKB (GTP_DDC_E1) - clock pessimism 0.000 9.059 - clock uncertainty 0.000 9.059 + clock pessimism 0.000 7.688 + clock uncertainty 0.000 7.688 - Removal time -0.011 9.048 + Removal time -0.011 7.677 - Data required time 9.048 + Data required time 7.677 ---------------------------------------------------------------------------------------------------- - Data required time 9.048 - Data arrival time 10.140 + Data required time 7.677 + Data arrival time 8.769 ---------------------------------------------------------------------------------------------------- Slack (MET) 1.092 ==================================================================================================== @@ -8137,8 +8959,8 @@ Path Group : ddrphy_clkin Path Type : min (slow corner) Path Class : async timing path Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 9.059 - Launch Clock Delay : 9.059 + Capture Clock Delay : 7.688 + Launch Clock Delay : 7.688 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -8152,23 +8974,23 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 4.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 5.214 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 5.308 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 5.913 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) - td 0.000 5.913 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) - net (fanout=5817) 3.146 9.059 u_axi_ddr_top/clk + td 0.000 4.542 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + net (fanout=5817) 3.146 7.688 u_axi_ddr_top/clk r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_dqs_training_rstn/CLK (GTP_DFF_C) - tco 0.323 9.382 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_dqs_training_rstn/Q (GTP_DFF_C) - net (fanout=10) 0.758 10.140 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dqs_training_rstn + tco 0.323 8.011 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_dqs_training_rstn/Q (GTP_DFF_C) + net (fanout=10) 0.758 8.769 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dqs_training_rstn f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[1].u_ddc_ca/RST_TRAINING_N (GTP_DDC_E1) - Data arrival time 10.140 Logic Levels: 0 + Data arrival time 8.769 Logic Levels: 0 Logic: 0.323ns(29.880%), Route: 0.758ns(70.120%) ---------------------------------------------------------------------------------------------------- @@ -8180,26 +9002,26 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 4.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 5.214 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 5.308 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 5.913 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) - td 0.000 5.913 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) - net (fanout=5817) 3.146 9.059 u_axi_ddr_top/clk + td 0.000 4.542 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + net (fanout=5817) 3.146 7.688 u_axi_ddr_top/clk r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[1].u_ddc_ca/CLKB (GTP_DDC_E1) - clock pessimism 0.000 9.059 - clock uncertainty 0.000 9.059 + clock pessimism 0.000 7.688 + clock uncertainty 0.000 7.688 - Removal time -0.011 9.048 + Removal time -0.011 7.677 - Data required time 9.048 + Data required time 7.677 ---------------------------------------------------------------------------------------------------- - Data required time 9.048 - Data arrival time 10.140 + Data required time 7.677 + Data arrival time 8.769 ---------------------------------------------------------------------------------------------------- Slack (MET) 1.092 ==================================================================================================== @@ -8212,8 +9034,8 @@ Path Group : ddrphy_clkin Path Type : min (slow corner) Path Class : async timing path Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessimism Removal) - Capture Clock Delay : 9.059 - Launch Clock Delay : 9.059 + Capture Clock Delay : 7.688 + Launch Clock Delay : 7.688 Clock Pessimism Removal : 0.000 Location Delay Type Incr Path Logical Resource @@ -8227,23 +9049,23 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 4.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 5.214 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 5.308 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 5.913 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) - td 0.000 5.913 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) - net (fanout=5817) 3.146 9.059 u_axi_ddr_top/clk + td 0.000 4.542 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + net (fanout=5817) 3.146 7.688 u_axi_ddr_top/clk r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_dqs_training_rstn/CLK (GTP_DFF_C) - tco 0.323 9.382 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_dqs_training_rstn/Q (GTP_DFF_C) - net (fanout=10) 0.758 10.140 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dqs_training_rstn + tco 0.323 8.011 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_dqs_training_rstn/Q (GTP_DFF_C) + net (fanout=10) 0.758 8.769 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dqs_training_rstn f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[2].u_ddc_ca/RST_TRAINING_N (GTP_DDC_E1) - Data arrival time 10.140 Logic Levels: 0 + Data arrival time 8.769 Logic Levels: 0 Logic: 0.323ns(29.880%), Route: 0.758ns(70.120%) ---------------------------------------------------------------------------------------------------- @@ -8255,26 +9077,26 @@ Clock Skew : 0.000 (Capture Clock Delay - Launch Clock Delay + Clock Pessim net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 4.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 5.214 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 5.308 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 5.913 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) - td 0.000 5.913 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) - net (fanout=5817) 3.146 9.059 u_axi_ddr_top/clk + td 0.000 4.542 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + net (fanout=5817) 3.146 7.688 u_axi_ddr_top/clk r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[2].u_ddc_ca/CLKB (GTP_DDC_E1) - clock pessimism 0.000 9.059 - clock uncertainty 0.000 9.059 + clock pessimism 0.000 7.688 + clock uncertainty 0.000 7.688 - Removal time -0.011 9.048 + Removal time -0.011 7.677 - Data required time 9.048 + Data required time 7.677 ---------------------------------------------------------------------------------------------------- - Data required time 9.048 - Data arrival time 10.140 + Data required time 7.677 + Data arrival time 8.769 ---------------------------------------------------------------------------------------------------- Slack (MET) 1.092 ==================================================================================================== @@ -8298,29 +9120,29 @@ Path Class : combinational timing path net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.089 2.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) 1.976 4.367 zoom_clk + net (fanout=7) 0.605 2.996 ddr_clk u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - td 0.000 4.367 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=71) 0.847 5.214 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + td 0.000 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + net (fanout=71) 0.847 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 5.308 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) 0.605 5.913 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + td 0.094 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + net (fanout=3) 0.605 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) - td 0.000 5.913 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) - net (fanout=5817) 3.146 9.059 u_axi_ddr_top/clk + td 0.000 4.542 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + net (fanout=5817) 3.146 7.688 u_axi_ddr_top/clk r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/calib_done/CLK (GTP_DFF_C) - tco 0.329 9.388 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/calib_done/Q (GTP_DFF_C) - net (fanout=575) 2.721 12.109 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/calib_done + tco 0.329 8.017 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/calib_done/Q (GTP_DFF_C) + net (fanout=575) 2.721 10.738 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/calib_done u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/N48/I0 (GTP_LUT2) - td 0.172 12.281 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/N48/Z (GTP_LUT2) - net (fanout=1) 1.091 13.372 nt_mem_rst_n + td 0.172 10.910 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/N48/Z (GTP_LUT2) + net (fanout=1) 1.091 12.001 nt_mem_rst_n mem_rst_n_obuf/I (GTP_OUTBUF) - td 2.803 16.175 f mem_rst_n_obuf/O (GTP_OUTBUF) - net (fanout=1) 0.000 16.175 mem_rst_n + td 2.803 14.804 f mem_rst_n_obuf/O (GTP_OUTBUF) + net (fanout=1) 0.000 14.804 mem_rst_n mem_rst_n f mem_rst_n (port) - Data arrival time 16.175 Logic Levels: 2 + Data arrival time 14.804 Logic Levels: 2 Logic: 3.304ns(46.431%), Route: 3.812ns(53.569%) ==================================================================================================== @@ -8343,20 +9165,20 @@ Path Class : combinational timing path net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.130 5.526 rd3_clk + net (fanout=2825) 3.127 5.523 rd3_clk U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.089 5.615 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=1758) 2.458 8.073 nt_pix_clk + td 0.089 5.612 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + net (fanout=1758) 2.458 8.070 nt_pix_clk r adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/b[0]/CLK (GTP_DFF) - tco 0.323 8.396 f adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/b[0]/Q (GTP_DFF) - net (fanout=1) 1.091 9.487 nt_b_out[0] + tco 0.323 8.393 f adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/b[0]/Q (GTP_DFF) + net (fanout=1) 1.091 9.484 nt_b_out[0] b_out_obuf[0]/I (GTP_OUTBUF) - td 2.803 12.290 f b_out_obuf[0]/O (GTP_OUTBUF) - net (fanout=1) 0.000 12.290 b_out[0] + td 2.803 12.287 f b_out_obuf[0]/O (GTP_OUTBUF) + net (fanout=1) 0.000 12.287 b_out[0] b_out[0] f b_out[0] (port) - Data arrival time 12.290 Logic Levels: 1 + Data arrival time 12.287 Logic Levels: 1 Logic: 3.126ns(74.129%), Route: 1.091ns(25.871%) ==================================================================================================== @@ -8379,20 +9201,20 @@ Path Class : combinational timing path net (fanout=1) 1.091 2.302 nt_clk u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 2.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) 3.130 5.526 rd3_clk + net (fanout=2825) 3.127 5.523 rd3_clk U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.089 5.615 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=1758) 2.458 8.073 nt_pix_clk + td 0.089 5.612 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + net (fanout=1758) 2.458 8.070 nt_pix_clk r adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/b[1]/CLK (GTP_DFF) - tco 0.323 8.396 f adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/b[1]/Q (GTP_DFF) - net (fanout=1) 1.091 9.487 nt_b_out[1] + tco 0.323 8.393 f adjust_color_wrapper_inst/adjust_color_inst/convert_hsv2rgb_inst/b[1]/Q (GTP_DFF) + net (fanout=1) 1.091 9.484 nt_b_out[1] b_out_obuf[1]/I (GTP_OUTBUF) - td 2.803 12.290 f b_out_obuf[1]/O (GTP_OUTBUF) - net (fanout=1) 0.000 12.290 b_out[1] + td 2.803 12.287 f b_out_obuf[1]/O (GTP_OUTBUF) + net (fanout=1) 0.000 12.287 b_out[1] b_out[1] f b_out[1] (port) - Data arrival time 12.290 Logic Levels: 1 + Data arrival time 12.287 Logic Levels: 1 Logic: 3.126ns(74.129%), Route: 1.091ns(25.871%) ==================================================================================================== @@ -8514,9 +9336,9 @@ Path Class : combinational timing path **************************************************************************************************** Slack Actual Width Require Width Type Location Pin ---------------------------------------------------------------------------------------------------- - 1.362 2.500 1.138 Low Pulse Width u_zoom_image/mult_fra0/N2/CLK - 1.362 2.500 1.138 High Pulse Width u_zoom_image/mult_fra0/N2/CLK - 1.362 2.500 1.138 Low Pulse Width u_zoom_image/mult_fra0_0/N2/CLK + 1.880 2.500 0.620 High Pulse Width u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/CLK + 1.880 2.500 0.620 Low Pulse Width u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/CLK + 1.880 2.500 0.620 High Pulse Width u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/CLK ==================================================================================================== {clk_25m} Minimum Pulse Width : @@ -8537,6 +9359,15 @@ Path Class : combinational timing path 49.102 50.000 0.898 Low Pulse Width ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/CLKB ==================================================================================================== +{clk_1080p60Hz} Minimum Pulse Width : +**************************************************************************************************** + Slack Actual Width Require Width Type Location Pin +---------------------------------------------------------------------------------------------------- + 2.230 3.368 1.138 High Pulse Width u_zoom_image/mult_fra0/N2/CLK + 2.230 3.368 1.138 Low Pulse Width u_zoom_image/mult_fra0/N2/CLK + 2.230 3.368 1.138 High Pulse Width u_zoom_image/mult_fra0_0/N2/CLK +==================================================================================================== + {clk_720p60Hz} Minimum Pulse Width : **************************************************************************************************** Slack Actual Width Require Width Type Location Pin @@ -8616,7 +9447,7 @@ Inputs and Outputs : Flow Command: synthesize -frequency {100} -selected_syn_tool_opt 2 -Peak memory: 764 MB -Total CPU time to synthesize completion : 0h:1m:28s -Process Total CPU time to synthesize completion : 0h:1m:39s -Total real time to synthesize completion : 0h:1m:58s +Peak memory: 759 MB +Total CPU time to synthesize completion : 0h:1m:32s +Process Total CPU time to synthesize completion : 0h:1m:43s +Total real time to synthesize completion : 0h:1m:59s diff --git a/project/synthesize/multimedia_video_processor_controlsets.txt b/project/synthesize/multimedia_video_processor_controlsets.txt index fa7fd98..8d247d0 100644 --- a/project/synthesize/multimedia_video_processor_controlsets.txt +++ b/project/synthesize/multimedia_video_processor_controlsets.txt @@ -1,4 +1,4 @@ -Generated by Fabric Compiler ( version 2022.2-SP1-Lite ) at Sat Nov 11 17:54:12 2023 +Generated by Fabric Compiler ( version 2022.2-SP1-Lite ) at Wed Nov 15 19:35:28 2023 Number of unique control sets : 504 CLK(clk_10m) : 47 @@ -48,7 +48,7 @@ Number of unique control sets : 504 CLK(nt_pix_clk), CE(u_sync_vg.N145) : 11 CLK(nt_pix_clk), CE(u_sync_vg.N54) : 11 CLK(rd3_clk), CE(u_ov5640.u_mix_image.N417) : 11 - CLK(rd3_clk), CE(u_rotate_image.N302) : 11 + CLK(rd3_clk), CE(u_rotate_image.N350) : 11 CLK(zoom_clk), CE(u_zoom_image.N843) : 11 CLK(zoom_clk), CE(u_zoom_image.N850) : 11 CLK(rd3_clk), CE(~rd3_rst) : 13 @@ -82,12 +82,12 @@ Number of unique control sets : 504 CLK(u_axi_ddr_top.clk), P(u_axi_ddr_top.I_ipsxb_ddr_top.u_ddrphy_top.ddrphy_reset_ctrl.ddrphy_dll_rst_rg) : 2 CLK(u_axi_ddr_top.clk), C(~u_axi_ddr_top.I_ipsxb_ddr_top.u_ddrphy_top.ddrphy_reset_ctrl.ddrphy_rst_n_rg) : 2 CLK(u_axi_ddr_top.clk), C(~u_axi_ddr_top.I_ipsxb_ddr_top.u_ddrphy_top.logic_rstn) : 2 + CLK(ddr_clk), P(u_axi_rst.N0) : 3 + CLK(ddr_clk), P(~nt_rstn) : 3 CLK(nt_hdmi_in_clk), P(u_hdm_in_rst.N0) : 3 CLK(nt_pix_clk), P(u_hdmi_rst.N0) : 3 CLK(rd3_clk), P(u_axi_rst.N0) : 3 - CLK(zoom_clk), P(u_axi_rst.N0) : 3 CLK(zoom_clk), P(u_hdmi_rst.N0) : 3 - CLK(zoom_clk), P(~nt_rstn) : 3 CLK(rd3_clk), CP(image_filiter_inst.multiline_buffer_inst.srst) : 8 CLK(rd3_clk), C(image_filiter_inst.multiline_buffer_inst.srst) : 4 CLK(rd3_clk), P(image_filiter_inst.multiline_buffer_inst.srst) : 4 @@ -184,8 +184,8 @@ Number of unique control sets : 504 CLK(u_axi_ddr_top.clk), P(~u_axi_ddr_top.I_ipsxb_ddr_top.ddr_rstn), CE(u_axi_ddr_top.I_ipsxb_ddr_top.u_ipsxb_ddrc_top.mcdq_dcd_top.mcdq_dcd_sm.N371) : 1 CLK(u_axi_ddr_top.clk), C(~u_axi_ddr_top.I_ipsxb_ddr_top.ddr_rstn), CE(~u_axi_ddr_top.I_ipsxb_ddr_top.u_ipsxb_ddrc_top.mcdq_rdatapath.mcdq_prefetch_fifo.empty) : 6 CLK(u_axi_ddr_top.clk), C(~u_axi_ddr_top.I_ipsxb_ddr_top.ddr_rstn), CE(~u_axi_ddr_top.I_ipsxb_ddr_top.u_ipsxb_ddrc_top.mcdq_rdatapath.mcdq_prefetch_fifo.full) : 6 - CLK(u_axi_ddr_top.clk), C(~u_axi_ddr_top.I_ipsxb_ddr_top.u_ddrphy_top.ddrphy_rst_n), CE(u_axi_ddr_top.I_ipsxb_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_group[0].u_ddrphy_data_slice.data_slice_dqs_gate_cal.gatecal.N139) : 6 CLK(u_axi_ddr_top.clk), C(~u_axi_ddr_top.I_ipsxb_ddr_top.u_ddrphy_top.ddrphy_rst_n), CE(u_axi_ddr_top.I_ipsxb_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_group[0].u_ddrphy_data_slice.data_slice_dqs_gate_cal.gatecal.N327) : 6 + CLK(u_axi_ddr_top.clk), C(~u_axi_ddr_top.I_ipsxb_ddr_top.u_ddrphy_top.ddrphy_rst_n), CE(u_axi_ddr_top.I_ipsxb_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_group[0].u_ddrphy_data_slice.data_slice_dqs_gate_cal.gatecal.N431) : 6 CLK(u_axi_ddr_top.clk), C(~u_axi_ddr_top.I_ipsxb_ddr_top.u_ddrphy_top.ddrphy_rst_n), CE(u_axi_ddr_top.I_ipsxb_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_group[0].u_ddrphy_data_slice.data_slice_wrlvl.N449) : 6 CLK(u_axi_ddr_top.clk), C(~u_axi_ddr_top.I_ipsxb_ddr_top.u_ddrphy_top.ddrphy_rst_n), CE(u_axi_ddr_top.I_ipsxb_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_group[0].u_ddrphy_data_slice.gate_check) : 6 CLK(u_axi_ddr_top.clk), C(~u_axi_ddr_top.I_ipsxb_ddr_top.u_ddrphy_top.ddrphy_rst_n), CE(u_axi_ddr_top.I_ipsxb_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_group[1].u_ddrphy_data_slice.data_slice_dqs_gate_cal.gatecal.N139) : 6 @@ -427,9 +427,9 @@ Number of unique control sets : 504 CLK(zoom_clk), R(u_zoom_image.image_valid[6] [0]) : 16 CLK(gmii_clk), R(param_manager_inst.N335) : 17 CLK(nt_pix_clk), R(adjust_color_wrapper_inst.adjust_color_inst.hsv_modify_inst.N76) : 20 + CLK(rd3_clk), R(u_ddr_addr_ctr.N76) : 20 CLK(clk_10m), R(ms72xx_ctl.ms7210_ctl.N539) : 22 CLK(clk_25m), R(~nt_cmos1_reset) : 22 - CLK(rd3_clk), R(u_ddr_addr_ctr.N73) : 22 CLK(u_axi_ddr_top.clk), RS(u_axi_ddr_top.rst) : 28 CLK(u_axi_ddr_top.clk), R(u_axi_ddr_top.rst) : 24 CLK(u_axi_ddr_top.clk), S(u_axi_ddr_top.rst) : 4 @@ -666,7 +666,7 @@ Number of DFF:CE Signals : 421 u_axi_ddr_top.I_ipsxb_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_group[1].u_ddrphy_data_slice.data_slice_wrlvl.N466(from GTP_LUT2:Z) : 4 u_axi_ddr_top.I_ipsxb_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_group[2].u_ddrphy_data_slice.data_slice_wrlvl.N466(from GTP_LUT2:Z) : 4 u_axi_ddr_top.I_ipsxb_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_group[3].u_ddrphy_data_slice.data_slice_wrlvl.N466(from GTP_LUT2:Z) : 4 - u_axi_ddr_top.I_ipsxb_ddr_top.u_ipsxb_ddrc_top.mcdq_dcd_top.mcdq_dcd_sm.N418(from GTP_LUT4:Z) : 4 + u_axi_ddr_top.I_ipsxb_ddr_top.u_ipsxb_ddrc_top.mcdq_dcd_top.mcdq_dcd_sm.N418(from GTP_LUT5:Z) : 4 u_axi_ddr_top.I_ipsxb_ddr_top.u_ipsxb_ddrc_top.mcdq_dcd_top.mcdq_dcd_sm.state_reg[0](from GTP_DFF_PE:Q) : 4 u_axi_ddr_top.I_ipsxb_ddr_top.u_ipsxb_ddrc_top.mcdq_dcp_top.mcdq_dcp_back_ctrl.tfaw_timing.TFAW_LOOP[0].mcdq_tfaw.N19(from GTP_LUT5:Z) : 4 u_axi_ddr_top.I_ipsxb_ddr_top.u_ipsxb_ddrc_top.mcdq_dcp_top.mcdq_dcp_back_ctrl.tfaw_timing.TFAW_LOOP[1].mcdq_tfaw.N19(from GTP_LUT5:Z) : 4 @@ -705,7 +705,7 @@ Number of DFF:CE Signals : 421 u_ddr_addr_ctr.u_wr1_addr_ctr.N132(from GTP_LUT2:Z) : 5 u_ddr_addr_ctr.u_wr1_addr_ctr.wr0_async_to_wr1_sync.data_vary0(from GTP_DFF:Q) : 5 u_ddr_addr_ctr.u_wr1_addr_ctr.wr_sta_reg[0](from GTP_DFF_S:Q) : 5 - udp_osd_inst.char_osd_inst.char_buf_reader_inst.N873(from GTP_LUT5M:Z) : 5 + udp_osd_inst.char_osd_inst.char_buf_reader_inst.N873(from GTP_LUT4:Z) : 5 udp_osd_inst.eth_udp_inst.u_arp.u_arp_rx.N563(from GTP_LUT5:Z) : 5 udp_osd_inst.eth_udp_inst.u_arp.u_arp_tx.N781(from GTP_LUT5:Z) : 5 udp_osd_inst.eth_udp_inst.u_icmp.u_icmp_rx.N803(from GTP_LUT5:Z) : 5 @@ -725,8 +725,8 @@ Number of DFF:CE Signals : 421 image_filiter_inst2.multiline_buffer_inst.N272(from GTP_LUT4:Z) : 6 ms72xx_ctl.iic_dri_rx.dsu(from GTP_LUT5:Z) : 6 ms72xx_ctl.ms7210_ctl.N580(from GTP_LUT5:Z) : 6 - u_axi_ddr_top.I_ipsxb_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_group[0].u_ddrphy_data_slice.data_slice_dqs_gate_cal.gatecal.N139(from GTP_LUT5:Z) : 6 u_axi_ddr_top.I_ipsxb_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_group[0].u_ddrphy_data_slice.data_slice_dqs_gate_cal.gatecal.N327(from GTP_LUT2:Z) : 6 + u_axi_ddr_top.I_ipsxb_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_group[0].u_ddrphy_data_slice.data_slice_dqs_gate_cal.gatecal.N431(from GTP_LUT5:Z) : 6 u_axi_ddr_top.I_ipsxb_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_group[0].u_ddrphy_data_slice.data_slice_wrlvl.N449(from GTP_LUT5:Z) : 6 u_axi_ddr_top.I_ipsxb_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_group[0].u_ddrphy_data_slice.gate_check(from GTP_DFF_C:Q) : 6 u_axi_ddr_top.I_ipsxb_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_group[1].u_ddrphy_data_slice.data_slice_dqs_gate_cal.gatecal.N139(from GTP_LUT5:Z) : 6 @@ -734,7 +734,7 @@ Number of DFF:CE Signals : 421 u_axi_ddr_top.I_ipsxb_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_group[1].u_ddrphy_data_slice.data_slice_wrlvl.N449(from GTP_LUT5:Z) : 6 u_axi_ddr_top.I_ipsxb_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_group[1].u_ddrphy_data_slice.gate_check(from GTP_DFF_C:Q) : 6 u_axi_ddr_top.I_ipsxb_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_group[2].u_ddrphy_data_slice.data_slice_dqs_gate_cal.gatecal.N139(from GTP_LUT5:Z) : 6 - u_axi_ddr_top.I_ipsxb_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_group[2].u_ddrphy_data_slice.data_slice_dqs_gate_cal.gatecal.N327(from GTP_LUT4:Z) : 6 + u_axi_ddr_top.I_ipsxb_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_group[2].u_ddrphy_data_slice.data_slice_dqs_gate_cal.gatecal.N327(from GTP_LUT2:Z) : 6 u_axi_ddr_top.I_ipsxb_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_group[2].u_ddrphy_data_slice.data_slice_wrlvl.N449(from GTP_LUT5:Z) : 6 u_axi_ddr_top.I_ipsxb_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_group[2].u_ddrphy_data_slice.gate_check(from GTP_DFF_C:Q) : 6 u_axi_ddr_top.I_ipsxb_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_group[3].u_ddrphy_data_slice.data_slice_dqs_gate_cal.gatecal.N139(from GTP_LUT5:Z) : 6 @@ -744,7 +744,7 @@ Number of DFF:CE Signals : 421 u_axi_ddr_top.I_ipsxb_ddr_top.u_ipsxb_ddrc_top.mcdq_dcd_top.mcdq_dcd_sm.N371(from GTP_LUT5M:Z) : 6 u_ov5640.coms1_reg_config.u1.N195(from GTP_LUT5:Z) : 6 u_ov5640.coms2_reg_config.u1.N195(from GTP_LUT5:Z) : 6 - udp_osd_inst.char_osd_inst.char_buf_reader_inst.N786(from GTP_LUT4:Z) : 6 + udp_osd_inst.char_osd_inst.char_buf_reader_inst.N786(from GTP_LUT5:Z) : 6 udp_osd_inst.char_osd_inst.pixels_shifter_inst.N135(from GTP_LUT5:Z) : 6 udp_osd_inst.eth_udp_inst.u_arp.u_arp_tx.N765(from GTP_LUT5:Z) : 6 udp_osd_inst.eth_udp_inst.udp_receive_buffer_inst.N321(from GTP_LUT4:Z) : 6 @@ -768,7 +768,7 @@ Number of DFF:CE Signals : 421 u_axi_ddr_top.I_ipsxb_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_group[0].u_ddrphy_data_slice.data_slice_wrlvl.N439(from GTP_LUT5:Z) : 8 u_axi_ddr_top.I_ipsxb_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_group[0].u_ddrphy_data_slice.dqsi_rdel_cal.N607(from GTP_LUT5:Z) : 8 u_axi_ddr_top.I_ipsxb_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_group[0].u_ddrphy_data_slice.dqsi_rdel_cal.N610(from GTP_LUT5:Z) : 8 - u_axi_ddr_top.I_ipsxb_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_group[1].u_ddrphy_data_slice.data_slice_wrlvl.N136(from GTP_LUT4:Z) : 8 + u_axi_ddr_top.I_ipsxb_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_group[1].u_ddrphy_data_slice.data_slice_wrlvl.N136(from GTP_LUT5:Z) : 8 u_axi_ddr_top.I_ipsxb_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_group[1].u_ddrphy_data_slice.data_slice_wrlvl.N377(from GTP_LUT5M:Z) : 8 u_axi_ddr_top.I_ipsxb_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_group[1].u_ddrphy_data_slice.data_slice_wrlvl.N386(from GTP_LUT4:Z) : 8 u_axi_ddr_top.I_ipsxb_ddr_top.u_ddrphy_top.ddrphy_slice_top.i_dqs_group[1].u_ddrphy_data_slice.data_slice_wrlvl.N439(from GTP_LUT5:Z) : 8 @@ -795,21 +795,21 @@ Number of DFF:CE Signals : 421 udp_osd_inst.eth_udp_inst.u_arp.u_arp_rx.N847(from GTP_LUT3:Z) : 8 udp_osd_inst.eth_udp_inst.u_arp.u_arp_rx.N866(from GTP_LUT4:Z) : 8 udp_osd_inst.eth_udp_inst.u_arp.u_arp_tx.N817(from GTP_LUT5:Z) : 8 - udp_osd_inst.eth_udp_inst.u_icmp.u_icmp_rx.N1014(from GTP_LUT4:Z) : 8 + udp_osd_inst.eth_udp_inst.u_icmp.u_icmp_rx.N1014(from GTP_LUT5:Z) : 8 udp_osd_inst.eth_udp_inst.u_icmp.u_icmp_rx.N1057(from GTP_LUT5:Z) : 8 udp_osd_inst.eth_udp_inst.u_icmp.u_icmp_rx.N1082(from GTP_LUT3:Z) : 8 udp_osd_inst.eth_udp_inst.u_icmp.u_icmp_rx.N1213(from GTP_LUT4:Z) : 8 - udp_osd_inst.eth_udp_inst.u_icmp.u_icmp_rx.N1269(from GTP_LUT5:Z) : 8 + udp_osd_inst.eth_udp_inst.u_icmp.u_icmp_rx.N1269(from GTP_LUT4:Z) : 8 udp_osd_inst.eth_udp_inst.u_icmp.u_icmp_rx.N1294(from GTP_LUT5:Z) : 8 - udp_osd_inst.eth_udp_inst.u_icmp.u_icmp_rx.N838(from GTP_LUT4:Z) : 8 - udp_osd_inst.eth_udp_inst.u_icmp.u_icmp_rx.N943(from GTP_LUT4:Z) : 8 + udp_osd_inst.eth_udp_inst.u_icmp.u_icmp_rx.N838(from GTP_LUT5:Z) : 8 + udp_osd_inst.eth_udp_inst.u_icmp.u_icmp_rx.N943(from GTP_LUT5:Z) : 8 udp_osd_inst.eth_udp_inst.u_icmp.u_icmp_rx.N956(from GTP_LUT5:Z) : 8 udp_osd_inst.eth_udp_inst.u_icmp.u_icmp_tx.N1036(from GTP_LUT5:Z) : 8 udp_osd_inst.eth_udp_inst.u_udp.u_udp_rx.N630(from GTP_LUT4:Z) : 8 - udp_osd_inst.eth_udp_inst.u_udp.u_udp_rx.N697(from GTP_LUT5:Z) : 8 + udp_osd_inst.eth_udp_inst.u_udp.u_udp_rx.N697(from GTP_LUT4:Z) : 8 udp_osd_inst.eth_udp_inst.u_udp.u_udp_rx.N710(from GTP_LUT4:Z) : 8 udp_osd_inst.eth_udp_inst.u_udp.u_udp_rx.N859(from GTP_LUT4:Z) : 8 - udp_osd_inst.eth_udp_inst.u_udp.u_udp_rx.N878(from GTP_LUT5:Z) : 8 + udp_osd_inst.eth_udp_inst.u_udp.u_udp_rx.N878(from GTP_LUT4:Z) : 8 udp_osd_inst.eth_udp_inst.udp_receive_buffer_inst.N296(from GTP_LUT3:Z) : 8 udp_wr_mem_inst.N727(from GTP_LUT3:Z) : 8 udp_wr_mem_inst.N730(from GTP_LUT3:Z) : 8 @@ -872,14 +872,14 @@ Number of DFF:CE Signals : 421 u_ov5640.cmos2_href_16bit(from GTP_DFF:Q) : 11 u_ov5640.u_mix_image.N417(from GTP_LUT5:Z) : 11 u_ov5640.u_mix_image.rd_sta[4](from GTP_DFF_R:Q) : 11 - u_rotate_image.N302(from GTP_LUT5:Z) : 11 + u_rotate_image.N350(from GTP_LUT5:Z) : 11 u_sync_vg.N145(from GTP_LUT5:Z) : 11 u_sync_vg.N54(from GTP_LUT5:Z) : 11 u_zoom_image.N843(from GTP_LUT5:Z) : 11 u_zoom_image.N850(from GTP_LUT4:Z) : 11 u_zoom_image.zoom_ram0.wr_en(from GTP_LUT2:Z) : 11 udp_osd_inst.char_buf_writer_inst.N222(from GTP_LUT2:Z) : 11 - udp_osd_inst.char_osd_inst.char_buf_reader_inst.N684(from GTP_LUT4:Z) : 11 + udp_osd_inst.char_osd_inst.char_buf_reader_inst.N684(from GTP_LUT5:Z) : 11 udp_osd_inst.char_osd_inst.char_buf_reader_inst.N711(from GTP_LUT5:Z) : 11 udp_osd_inst.char_osd_inst.char_buf_reader_inst.N848(from GTP_LUT5:Z) : 11 udp_osd_inst.char_osd_inst.char_buf_reader_inst.N862(from GTP_LUT5M:Z) : 11 @@ -936,14 +936,14 @@ Number of DFF:CE Signals : 421 u_axi_ddr_top.I_ipsxb_ddr_top.u_ddrphy_top.ddrphy_info.N532(from GTP_LUT5:Z) : 15 u_axi_ddr_top.I_ipsxb_ddr_top.u_ipsxb_ddrc_top.mcdq_dcd_top.mcdq_dcd_bm.N304(from GTP_LUT2:Z) : 15 u_axi_ddr_top.I_ipsxb_ddr_top.u_ipsxb_ddrc_top.mcdq_dcd_top.mcdq_dcd_bm.N317(from GTP_LUT4:Z) : 15 - u_axi_ddr_top.I_ipsxb_ddr_top.u_ipsxb_ddrc_top.mcdq_ui_axi.N254(from GTP_LUT4:Z) : 15 - u_axi_ddr_top.I_ipsxb_ddr_top.u_ipsxb_ddrc_top.mcdq_ui_axi.N258(from GTP_LUT4:Z) : 15 - u_axi_ddr_top.I_ipsxb_ddr_top.u_ipsxb_ddrc_top.mcdq_ui_axi.N262(from GTP_LUT4:Z) : 15 - u_axi_ddr_top.I_ipsxb_ddr_top.u_ipsxb_ddrc_top.mcdq_ui_axi.N266(from GTP_LUT4:Z) : 15 - u_axi_ddr_top.I_ipsxb_ddr_top.u_ipsxb_ddrc_top.mcdq_ui_axi.N270(from GTP_LUT4:Z) : 15 - u_axi_ddr_top.I_ipsxb_ddr_top.u_ipsxb_ddrc_top.mcdq_ui_axi.N274(from GTP_LUT4:Z) : 15 - u_axi_ddr_top.I_ipsxb_ddr_top.u_ipsxb_ddrc_top.mcdq_ui_axi.N278(from GTP_LUT4:Z) : 15 - u_axi_ddr_top.I_ipsxb_ddr_top.u_ipsxb_ddrc_top.mcdq_ui_axi.N282(from GTP_LUT4:Z) : 15 + u_axi_ddr_top.I_ipsxb_ddr_top.u_ipsxb_ddrc_top.mcdq_ui_axi.N254(from GTP_LUT5:Z) : 15 + u_axi_ddr_top.I_ipsxb_ddr_top.u_ipsxb_ddrc_top.mcdq_ui_axi.N258(from GTP_LUT5:Z) : 15 + u_axi_ddr_top.I_ipsxb_ddr_top.u_ipsxb_ddrc_top.mcdq_ui_axi.N262(from GTP_LUT5:Z) : 15 + u_axi_ddr_top.I_ipsxb_ddr_top.u_ipsxb_ddrc_top.mcdq_ui_axi.N266(from GTP_LUT5:Z) : 15 + u_axi_ddr_top.I_ipsxb_ddr_top.u_ipsxb_ddrc_top.mcdq_ui_axi.N270(from GTP_LUT5:Z) : 15 + u_axi_ddr_top.I_ipsxb_ddr_top.u_ipsxb_ddrc_top.mcdq_ui_axi.N274(from GTP_LUT5:Z) : 15 + u_axi_ddr_top.I_ipsxb_ddr_top.u_ipsxb_ddrc_top.mcdq_ui_axi.N278(from GTP_LUT5:Z) : 15 + u_axi_ddr_top.I_ipsxb_ddr_top.u_ipsxb_ddrc_top.mcdq_ui_axi.N282(from GTP_LUT5:Z) : 15 ms72xx_ctl.iic_dri_rx.full_cycle(from GTP_LUT5:Z) : 16 u_axi_ddr_top.I_ipsxb_ddr_top.u_ddrphy_top.ddrphy_calib_top.ddrphy_init.N274(from GTP_LUT5:Z) : 16 u_axi_ddr_top.N871(from GTP_LUT2:Z) : 16 @@ -957,14 +957,14 @@ Number of DFF:CE Signals : 421 u_ov5640.power_on_delay_inst.N15(from GTP_LUT5:Z) : 16 u_ov5640.u_mix_image.N427(from GTP_LUT5:Z) : 16 udp_osd_inst.char_buf_writer_inst.N179(from GTP_LUT3:Z) : 16 - udp_osd_inst.eth_udp_inst.u_icmp.u_icmp_rx.N1170(from GTP_LUT4:Z) : 16 + udp_osd_inst.eth_udp_inst.u_icmp.u_icmp_rx.N1170(from GTP_LUT5:Z) : 16 udp_osd_inst.eth_udp_inst.u_icmp.u_icmp_rx.N456(from GTP_LUT5:Z) : 16 udp_osd_inst.eth_udp_inst.u_icmp.u_icmp_tx.N1094(from GTP_LUT4:Z) : 16 udp_osd_inst.eth_udp_inst.u_icmp.u_icmp_tx.N1731(from GTP_LUT5:Z) : 16 udp_osd_inst.eth_udp_inst.u_icmp.u_icmp_tx.N3084(from GTP_LUT4:Z) : 16 udp_osd_inst.eth_udp_inst.u_icmp.u_icmp_tx.N969(from GTP_LUT5M:Z) : 16 - udp_osd_inst.eth_udp_inst.u_udp.u_udp_rx.N748(from GTP_LUT4:Z) : 16 - udp_osd_inst.eth_udp_inst.u_udp.u_udp_rx.N839(from GTP_LUT5:Z) : 16 + udp_osd_inst.eth_udp_inst.u_udp.u_udp_rx.N748(from GTP_LUT2:Z) : 16 + udp_osd_inst.eth_udp_inst.u_udp.u_udp_rx.N839(from GTP_LUT3:Z) : 16 udp_osd_inst.eth_udp_inst.udp_receive_buffer_inst.N282(from GTP_LUT4:Z) : 16 udp_osd_inst.eth_udp_inst.udp_receive_buffer_inst.N327(from GTP_LUT2:Z) : 16 udp_osd_inst.eth_udp_inst.udp_receive_buffer_inst.change_to_read(from GTP_DFF:Q) : 16 @@ -997,7 +997,7 @@ Number of DFF:CE Signals : 421 udp_osd_inst.eth_udp_inst.u_icmp.u_icmp_tx.N15(from GTP_LUT3:Z) : 30 ms72xx_ctl.ms7200_ctl.N8(from GTP_LUT5:Z) : 32 u_rotate_image.rotate_sta_reg[0](from GTP_DFF_S:Q) : 32 - udp_osd_inst.eth_udp_inst.u_arp.u_arp_rx.N706(from GTP_LUT5:Z) : 32 + udp_osd_inst.eth_udp_inst.u_arp.u_arp_rx.N706(from GTP_LUT4:Z) : 32 udp_osd_inst.eth_udp_inst.u_arp.u_arp_rx.N834(from GTP_LUT4:Z) : 32 udp_osd_inst.eth_udp_inst.u_arp.u_crc32_d8.N263(from GTP_LUT2:Z) : 32 udp_osd_inst.eth_udp_inst.u_icmp.u_crc32_d8.N263(from GTP_LUT2:Z) : 32 @@ -1015,7 +1015,7 @@ Number of DFF:CE Signals : 421 u_axi_ddr_top.I_ipsxb_ddr_top.u_ipsxb_ddrc_top.mcdq_dcp_top.mcdq_dcp_back_ctrl.N104(from GTP_LUT4:Z) : 42 u_axi_ddr_top.I_ipsxb_ddr_top.u_ipsxb_ddrc_top.mcdq_dcp_top.mcdq_dcp_buf.N197(from GTP_LUT5:Z) : 42 udp_osd_inst.char_osd_inst.char_buf_reader_inst.N15(from GTP_LUT5:Z) : 44 - udp_osd_inst.eth_udp_inst.u_arp.u_arp_rx.N639(from GTP_LUT4:Z) : 48 + udp_osd_inst.eth_udp_inst.u_arp.u_arp_rx.N639(from GTP_LUT5:Z) : 48 udp_osd_inst.eth_udp_inst.u_arp.u_arp_rx.N769(from GTP_LUT4:Z) : 48 udp_osd_inst.eth_udp_inst.u_icmp.u_icmp_rx.N817(from GTP_LUT5:Z) : 48 udp_osd_inst.eth_udp_inst.u_icmp.u_icmp_tx.N1125(from GTP_LUT2:Z) : 48 @@ -1026,12 +1026,13 @@ Number of DFF:CE Signals : 421 u_axi_ddr_top.u_axi_wr_connect.N235(from GTP_LUT4:Z) : 64 param_manager_inst.param_rotate.N116(from GTP_LUT2:Z) : 72 udp_osd_inst.eth_udp_inst.u_arp.u_arp_tx.N832(from GTP_LUT3:Z) : 80 - udp_osd_inst.eth_udp_inst.u_arp.u_arp_rx.N319(from GTP_LUT5:Z) : 81 + udp_osd_inst.eth_udp_inst.u_arp.u_arp_rx.N319(from GTP_LUT3:Z) : 81 image_filiter_inst.pixel_valid(from GTP_DFF_R:Q) : 144 image_filiter_inst2.pixel_valid(from GTP_DFF_R:Q) : 144 -Number of DFF:CLK Signals : 14 +Number of DFF:CLK Signals : 15 u_axi_ddr_top.I_ipsxb_ddr_top.ioclk_gate_clk(from GTP_CLKBUFG:CLKOUT) : 1 + ddr_clk(from GTP_PLL_E3:CLKOUT1) : 6 u_ov5640.coms1_reg_config.clock_20k(from GTP_CLKBUFG:CLKOUT) : 23 u_ov5640.coms2_reg_config.clock_20k(from GTP_CLKBUFG:CLKOUT) : 23 clk_25m(from GTP_PLL_E3:CLKOUT3) : 26 @@ -1040,10 +1041,10 @@ Number of DFF:CLK Signals : 14 nt_cmos2_pclk(from GTP_INBUF:O) : 125 nt_hdmi_in_clk(from GTP_INBUF:O) : 171 clk_10m(from GTP_PLL_E3:CLKOUT4) : 342 - zoom_clk(from GTP_PLL_E3:CLKOUT1) : 764 + zoom_clk(from GTP_PLL_E3:CLKOUT0) : 758 nt_pix_clk(from GTP_PLL_E3:CLKOUT1) : 1718 gmii_clk(from GTP_CLKBUFG:CLKOUT) : 1963 - rd3_clk(from GTP_PLL_E3:CLKOUT0) : 2786 + rd3_clk(from GTP_PLL_E3:CLKOUT0) : 2784 u_axi_ddr_top.clk(from GTP_IOCLKDIV:CLKDIVOUT) : 5574 Number of DFF:CP Signals : 20 @@ -1136,8 +1137,8 @@ Number of DFF:RS Signals : 77 param_manager_inst.N335(from GTP_LUT2:Z) : 17 u_ov5640.power_on_delay_inst.camera_pwnd(from GTP_DFF_S:Q) : 17 adjust_color_wrapper_inst.adjust_color_inst.hsv_modify_inst.N76(from GTP_LUT5:Z) : 20 + u_ddr_addr_ctr.N76(from GTP_LUT3:Z) : 20 ms72xx_ctl.ms7210_ctl.N539(from GTP_LUT2:Z) : 22 - u_ddr_addr_ctr.N73(from GTP_LUT3:Z) : 22 udp_osd_inst.eth_udp_inst.u_icmp.u_icmp_tx.N2624(from GTP_LUT3:Z) : 32 zoom_rst(from GTP_DFF_P:Q) : 45 u_axi_ddr_top.rst(from GTP_DFF:Q) : 64 diff --git a/project/synthesize/multimedia_video_processor_syn.adf b/project/synthesize/multimedia_video_processor_syn.adf index ce928f3..fac6222 100644 Binary files a/project/synthesize/multimedia_video_processor_syn.adf and b/project/synthesize/multimedia_video_processor_syn.adf differ diff --git a/project/synthesize/multimedia_video_processor_syn.vm b/project/synthesize/multimedia_video_processor_syn.vm index 8e24278..78c4422 100644 --- a/project/synthesize/multimedia_video_processor_syn.vm +++ b/project/synthesize/multimedia_video_processor_syn.vm @@ -1,14 +1,14 @@ // -// Generated (version 2022.2-SP1-Lite) at Sat Nov 11 17:54:39 2023 +// Generated (version 2022.2-SP1-Lite) at Wed Nov 15 19:35:56 2023 // module HDMI_PLL ( input clkin1, + output clkout0, output clkout1, output pll_lock ); - wire clkout0; wire clkout0_2pad; wire clkout2; wire clkout3; @@ -147,13 +147,10 @@ module convert_hsv2rgb wire [7:0] N154; wire [7:0] N155; wire [2:0] N199; - wire [2:0] N201; wire [15:0] N204; wire [15:0] N205; wire [9:0] \N205_5.co ; wire [8:0] N253; - wire _N11247; - wire _N11248; wire _N11249; wire _N11250; wire _N11251; @@ -197,8 +194,8 @@ module convert_hsv2rgb wire _N11289; wire _N11290; wire _N11291; - wire _N11300; - wire _N11301; + wire _N11292; + wire _N11293; wire _N11302; wire _N11303; wire _N11304; @@ -224,14 +221,17 @@ module convert_hsv2rgb wire _N11324; wire _N11325; wire _N11326; - wire _N13454; - wire _N13455; + wire _N11327; + wire _N11328; wire _N13456; wire _N13457; wire _N13458; wire _N13459; wire _N13460; + wire _N13461; + wire _N13462; wire _N18651; + wire _N96639; wire [15:0] diff; wire [7:0] max_ff1; wire [7:0] max_ff2; @@ -244,6 +244,7 @@ module convert_hsv2rgb wire [2:0] n_ff2; wire [2:0] n_ff3; wire [15:0] nb0; + wire [15:0] nb1; wire \N11_CPO[0]_floating ; wire \N11_CPO[1]_floating ; wire \N11_CPO[2]_floating ; @@ -441,7 +442,7 @@ module convert_hsv2rgb .CPO (), .CXBO (), .CXO (), - .P ({_N11278, _N11277, _N11276, _N11275, _N11274, _N11273, _N11272, _N11271, _N11270, _N11269, _N11268, _N11267, _N11266, _N11265, _N11264, _N11263, _N11262, _N11261, _N11260, _N11259, _N11258, _N11257, _N11256, _N11255, _N11254, _N11253, _N11252, _N11251, _N11250, _N11249, _N11248, _N11247, diff[15], diff[14], diff[13], diff[12], diff[11], diff[10], diff[9], diff[8], diff[7], diff[6], diff[5], diff[4], diff[3], diff[2], diff[1], diff[0]}), + .P ({_N11280, _N11279, _N11278, _N11277, _N11276, _N11275, _N11274, _N11273, _N11272, _N11271, _N11270, _N11269, _N11268, _N11267, _N11266, _N11265, _N11264, _N11263, _N11262, _N11261, _N11260, _N11259, _N11258, _N11257, _N11256, _N11255, _N11254, _N11253, _N11252, _N11251, _N11250, _N11249, diff[15], diff[14], diff[13], diff[12], diff[11], diff[10], diff[9], diff[8], diff[7], diff[6], diff[5], diff[4], diff[3], diff[2], diff[1], diff[0]}), .CPI (), .CXBI (), .CXI (), @@ -690,7 +691,7 @@ module convert_hsv2rgb .CPO (), .CXBO (), .CXO (), - .P ({_N11326, _N11325, _N11324, _N11323, _N11322, _N11321, _N11320, _N11319, _N11318, _N11317, _N11316, _N11315, _N11314, _N11313, _N11312, _N11311, _N11310, _N11309, _N11308, _N11307, _N11306, _N11305, _N11304, _N11303, _N11302, _N11301, _N11300, med2[20], med2[19], med2[18], med2[17], med2[16], med2[15], med2[14], med2[13], _N11291, _N11290, _N11289, _N11288, _N11287, _N11286, _N11285, _N11284, _N11283, _N11282, _N11281, _N11280, _N11279}), + .P ({_N11328, _N11327, _N11326, _N11325, _N11324, _N11323, _N11322, _N11321, _N11320, _N11319, _N11318, _N11317, _N11316, _N11315, _N11314, _N11313, _N11312, _N11311, _N11310, _N11309, _N11308, _N11307, _N11306, _N11305, _N11304, _N11303, _N11302, med2[20], med2[19], med2[18], med2[17], med2[16], med2[15], med2[14], med2[13], _N11293, _N11292, _N11291, _N11290, _N11289, _N11288, _N11287, _N11286, _N11285, _N11284, _N11283, _N11282, _N11281}), .CPI (), .CXBI (), .CXI (), @@ -730,7 +731,7 @@ module convert_hsv2rgb .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N138_1_1 ( - .COUT (_N13454), + .COUT (_N13456), .Z (N253[0]), .CIN (), .I0 (min[0]), @@ -750,9 +751,9 @@ module convert_hsv2rgb .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N138_1_2 ( - .COUT (_N13455), + .COUT (_N13457), .Z (N253[1]), - .CIN (_N13454), + .CIN (_N13456), .I0 (min[0]), .I1 (med2[13]), .I2 (min[1]), @@ -770,9 +771,9 @@ module convert_hsv2rgb .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N138_1_3 ( - .COUT (_N13456), + .COUT (_N13458), .Z (N253[2]), - .CIN (_N13455), + .CIN (_N13457), .I0 (), .I1 (min[2]), .I2 (med2[15]), @@ -790,9 +791,9 @@ module convert_hsv2rgb .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N138_1_4 ( - .COUT (_N13457), + .COUT (_N13459), .Z (N253[3]), - .CIN (_N13456), + .CIN (_N13458), .I0 (), .I1 (min[3]), .I2 (med2[16]), @@ -810,9 +811,9 @@ module convert_hsv2rgb .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N138_1_5 ( - .COUT (_N13458), + .COUT (_N13460), .Z (N253[4]), - .CIN (_N13457), + .CIN (_N13459), .I0 (), .I1 (min[4]), .I2 (med2[17]), @@ -830,9 +831,9 @@ module convert_hsv2rgb .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N138_1_6 ( - .COUT (_N13459), + .COUT (_N13461), .Z (N253[5]), - .CIN (_N13458), + .CIN (_N13460), .I0 (), .I1 (min[5]), .I2 (med2[18]), @@ -850,9 +851,9 @@ module convert_hsv2rgb .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N138_1_7 ( - .COUT (_N13460), + .COUT (_N13462), .Z (N253[6]), - .CIN (_N13459), + .CIN (_N13461), .I0 (), .I1 (min[6]), .I2 (med2[19]), @@ -872,7 +873,7 @@ module convert_hsv2rgb N138_1_8 ( .COUT (), .Z (N253[7]), - .CIN (_N13460), + .CIN (_N13462), .I0 (), .I1 (min[7]), .I2 (med2[20]), @@ -1180,15 +1181,6 @@ module convert_hsv2rgb .ID (max_ff3[7])); // LUT = (ID&I2&~I4)|(ID&I1&~I4)|(I0&I2&I4)|(I0&I1&I4)|(~I1&~I2&I3) ; - GTP_LUT3 /* \N199[0]_2 */ #( - .INIT(8'b00101011)) - \N199[0]_2 ( - .Z (N199[0]), - .I0 (h_s_data[5]), - .I1 (h_s_data[6]), - .I2 (h_s_data[7])); - // LUT = (~I1&~I2)|(I0&~I2)|(I0&~I1) ; - GTP_LUT5 /* \N204[0] */ #( .INIT(32'b11111111111111100000000000000010)) \N204[0] ( @@ -1269,7 +1261,7 @@ module convert_hsv2rgb // CARRY = (1'b0) ? CIN : (1'b1) ; GTP_LUT5CARRY /* \N205_5.fsub_1 */ #( - .INIT(32'b01101001101001011100001100001111), + .INIT(32'b10100101011010010000111111000011), .ID_TO_LUT("FALSE"), .CIN_TO_LUT("TRUE"), .I4_TO_CARRY("TRUE"), @@ -1281,14 +1273,14 @@ module convert_hsv2rgb .I0 (), .I1 (h_s_data[0]), .I2 (nb0[0]), - .I3 (N199[0]), + .I3 (_N96639), .I4 (nb0[0]), .ID ()); - // LUT = (~CIN&~I2&~I3)|(CIN&I2&~I3)|(CIN&I1&~I2&I3)|(~CIN&I1&I2&I3)|(~CIN&~I1&~I2)|(CIN&~I1&I2) ; - // CARRY = ((~I2&~I3)|(I1&I2&I3)|(~I1&~I2)) ? CIN : (I4) ; + // LUT = (CIN&I1&~I2&~I3)|(~CIN&I1&I2&~I3)|(~CIN&~I2&I3)|(CIN&I2&I3)|(~CIN&~I1&~I2)|(CIN&~I1&I2) ; + // CARRY = ((I1&I2&~I3)|(~I2&I3)|(~I1&~I2)) ? CIN : (I4) ; GTP_LUT5CARRY /* \N205_5.fsub_2 */ #( - .INIT(32'b01101001101001011100001100001111), + .INIT(32'b10100101011010010000111111000011), .ID_TO_LUT("FALSE"), .CIN_TO_LUT("TRUE"), .I4_TO_CARRY("TRUE"), @@ -1300,14 +1292,14 @@ module convert_hsv2rgb .I0 (), .I1 (h_s_data[1]), .I2 (nb0[1]), - .I3 (N199[0]), + .I3 (_N96639), .I4 (nb0[1]), .ID ()); - // LUT = (~CIN&~I2&~I3)|(CIN&I2&~I3)|(CIN&I1&~I2&I3)|(~CIN&I1&I2&I3)|(~CIN&~I1&~I2)|(CIN&~I1&I2) ; - // CARRY = ((~I2&~I3)|(I1&I2&I3)|(~I1&~I2)) ? CIN : (I4) ; + // LUT = (CIN&I1&~I2&~I3)|(~CIN&I1&I2&~I3)|(~CIN&~I2&I3)|(CIN&I2&I3)|(~CIN&~I1&~I2)|(CIN&~I1&I2) ; + // CARRY = ((I1&I2&~I3)|(~I2&I3)|(~I1&~I2)) ? CIN : (I4) ; GTP_LUT5CARRY /* \N205_5.fsub_3 */ #( - .INIT(32'b01101001101001011100001100001111), + .INIT(32'b10100101011010010000111111000011), .ID_TO_LUT("FALSE"), .CIN_TO_LUT("TRUE"), .I4_TO_CARRY("TRUE"), @@ -1319,14 +1311,14 @@ module convert_hsv2rgb .I0 (), .I1 (h_s_data[2]), .I2 (nb0[2]), - .I3 (N199[0]), + .I3 (_N96639), .I4 (nb0[2]), .ID ()); - // LUT = (~CIN&~I2&~I3)|(CIN&I2&~I3)|(CIN&I1&~I2&I3)|(~CIN&I1&I2&I3)|(~CIN&~I1&~I2)|(CIN&~I1&I2) ; - // CARRY = ((~I2&~I3)|(I1&I2&I3)|(~I1&~I2)) ? CIN : (I4) ; + // LUT = (CIN&I1&~I2&~I3)|(~CIN&I1&I2&~I3)|(~CIN&~I2&I3)|(CIN&I2&I3)|(~CIN&~I1&~I2)|(CIN&~I1&I2) ; + // CARRY = ((I1&I2&~I3)|(~I2&I3)|(~I1&~I2)) ? CIN : (I4) ; GTP_LUT5CARRY /* \N205_5.fsub_4 */ #( - .INIT(32'b01101001101001011100001100001111), + .INIT(32'b10100101011010010000111111000011), .ID_TO_LUT("FALSE"), .CIN_TO_LUT("TRUE"), .I4_TO_CARRY("TRUE"), @@ -1338,14 +1330,14 @@ module convert_hsv2rgb .I0 (), .I1 (h_s_data[3]), .I2 (nb0[3]), - .I3 (N199[0]), + .I3 (_N96639), .I4 (nb0[3]), .ID ()); - // LUT = (~CIN&~I2&~I3)|(CIN&I2&~I3)|(CIN&I1&~I2&I3)|(~CIN&I1&I2&I3)|(~CIN&~I1&~I2)|(CIN&~I1&I2) ; - // CARRY = ((~I2&~I3)|(I1&I2&I3)|(~I1&~I2)) ? CIN : (I4) ; + // LUT = (CIN&I1&~I2&~I3)|(~CIN&I1&I2&~I3)|(~CIN&~I2&I3)|(CIN&I2&I3)|(~CIN&~I1&~I2)|(CIN&~I1&I2) ; + // CARRY = ((I1&I2&~I3)|(~I2&I3)|(~I1&~I2)) ? CIN : (I4) ; GTP_LUT5CARRY /* \N205_5.fsub_5 */ #( - .INIT(32'b01101001101001011100001100001111), + .INIT(32'b10100101011010010000111111000011), .ID_TO_LUT("FALSE"), .CIN_TO_LUT("TRUE"), .I4_TO_CARRY("TRUE"), @@ -1357,11 +1349,11 @@ module convert_hsv2rgb .I0 (), .I1 (h_s_data[4]), .I2 (nb0[4]), - .I3 (N199[0]), + .I3 (_N96639), .I4 (nb0[4]), .ID ()); - // LUT = (~CIN&~I2&~I3)|(CIN&I2&~I3)|(CIN&I1&~I2&I3)|(~CIN&I1&I2&I3)|(~CIN&~I1&~I2)|(CIN&~I1&I2) ; - // CARRY = ((~I2&~I3)|(I1&I2&I3)|(~I1&~I2)) ? CIN : (I4) ; + // LUT = (CIN&I1&~I2&~I3)|(~CIN&I1&I2&~I3)|(~CIN&~I2&I3)|(CIN&I2&I3)|(~CIN&~I1&~I2)|(CIN&~I1&I2) ; + // CARRY = ((I1&I2&~I3)|(~I2&I3)|(~I1&~I2)) ? CIN : (I4) ; GTP_LUT5CARRY /* \N205_5.fsub_6 */ #( .INIT(32'b10101001000000000000001100000011), @@ -1412,7 +1404,7 @@ module convert_hsv2rgb .Z (N204[7]), .CIN (\N205_5.co [7] ), .I0 (), - .I1 (N201[2]), + .I1 (nb1[7]), .I2 (nb0[7]), .I3 (N19_inv_1), .I4 (nb0[7]), @@ -1439,6 +1431,15 @@ module convert_hsv2rgb // LUT = (~CIN&I3)|(~CIN&I2)|(~CIN&I1) ; // CARRY = (1'b1) ? CIN : (I4) ; + GTP_LUT3 /* N205_13 */ #( + .INIT(8'b10000000)) + N205_13 ( + .Z (nb0[5]), + .I0 (h_s_data[5]), + .I1 (h_s_data[6]), + .I2 (h_s_data[7])); + // LUT = I0&I1&I2 ; + GTP_LUT4 /* \N205_43[0] */ #( .INIT(16'b1010001000100000)) \N205_43[0] ( @@ -1498,31 +1499,40 @@ module convert_hsv2rgb .I2 (h_s_data[7])); // LUT = (~I1&~I2)|(~I0&I1)|(I0&I2) ; - GTP_LUT2 /* N205_46 */ #( + GTP_LUT3 /* N205_45 */ #( + .INIT(8'b11010100)) + N205_45 ( + .Z (_N96639), + .I0 (h_s_data[5]), + .I1 (h_s_data[6]), + .I2 (h_s_data[7])); + // LUT = (~I0&I1)|(~I0&I2)|(I1&I2) ; + + GTP_LUT3 /* N205_45_inv */ #( + .INIT(8'b00101011)) + N205_45_inv ( + .Z (N199[0]), + .I0 (h_s_data[5]), + .I1 (h_s_data[6]), + .I2 (h_s_data[7])); + // LUT = (~I1&~I2)|(I0&~I2)|(I0&~I1) ; + + GTP_LUT2 /* N205_47 */ #( .INIT(4'b0010)) - N205_46 ( + N205_47 ( .Z (N199[1]), .I0 (h_s_data[6]), .I1 (h_s_data[7])); // LUT = I0&~I1 ; - GTP_LUT2 /* N205_48 */ #( + GTP_LUT2 /* N205_49 */ #( .INIT(4'b0100)) - N205_48 ( - .Z (N201[2]), + N205_49 ( + .Z (nb1[7]), .I0 (h_s_data[6]), .I1 (h_s_data[7])); // LUT = ~I0&I1 ; - GTP_LUT3 /* N205_51 */ #( - .INIT(8'b10000000)) - N205_51 ( - .Z (nb0[5]), - .I0 (h_s_data[5]), - .I1 (h_s_data[6]), - .I2 (h_s_data[7])); - // LUT = I0&I1&I2 ; - GTP_DFF /* \b[0] */ #( .GRS_EN("TRUE"), .INIT(1'b0)) @@ -2125,7 +2135,7 @@ module convert_hsv2rgb \n_ff1[2] ( .Q (n_ff1[2]), .CLK (clk), - .D (N201[2]), + .D (nb1[7]), .R (N19)); // ../../sources/designs/adjust_color/convert_hsv2rgb.v:35 @@ -2278,14 +2288,14 @@ module divider_cell wire [7:0] N51; wire [7:0] N53; wire [11:0] N54; - wire _N18853; - wire _N18854; - wire _N18855; - wire _N18856; - wire _N18857; - wire _N18858; - wire _N18859; - wire _N18860; + wire _N18817; + wire _N18818; + wire _N18819; + wire _N18820; + wire _N18821; + wire _N18822; + wire _N18823; + wire _N18824; GTP_LUT5CARRY /* \N6.lt_0 */ #( .INIT(32'b00100000111100100000000000000000), @@ -2415,7 +2425,7 @@ module divider_cell .I4_TO_LUT("FALSE")) \N20.fsub_1 ( .COUT (\N20.co [1] ), - .Z (_N18853), + .Z (_N18817), .CIN (\N20.co [0] ), .I0 (), .I1 (divisor[0]), @@ -2435,7 +2445,7 @@ module divider_cell .I4_TO_LUT("FALSE")) \N20.fsub_2 ( .COUT (\N20.co [2] ), - .Z (_N18854), + .Z (_N18818), .CIN (\N20.co [1] ), .I0 (), .I1 (divisor[1]), @@ -2455,7 +2465,7 @@ module divider_cell .I4_TO_LUT("FALSE")) \N20.fsub_3 ( .COUT (\N20.co [3] ), - .Z (_N18855), + .Z (_N18819), .CIN (\N20.co [2] ), .I0 (), .I1 (divisor[2]), @@ -2475,7 +2485,7 @@ module divider_cell .I4_TO_LUT("FALSE")) \N20.fsub_4 ( .COUT (\N20.co [4] ), - .Z (_N18856), + .Z (_N18820), .CIN (\N20.co [3] ), .I0 (), .I1 (divisor[3]), @@ -2495,7 +2505,7 @@ module divider_cell .I4_TO_LUT("FALSE")) \N20.fsub_5 ( .COUT (\N20.co [5] ), - .Z (_N18857), + .Z (_N18821), .CIN (\N20.co [4] ), .I0 (), .I1 (divisor[4]), @@ -2515,7 +2525,7 @@ module divider_cell .I4_TO_LUT("FALSE")) \N20.fsub_6 ( .COUT (\N20.co [6] ), - .Z (_N18858), + .Z (_N18822), .CIN (\N20.co [5] ), .I0 (), .I1 (divisor[5]), @@ -2535,7 +2545,7 @@ module divider_cell .I4_TO_LUT("FALSE")) \N20.fsub_7 ( .COUT (\N20.co [7] ), - .Z (_N18859), + .Z (_N18823), .CIN (\N20.co [6] ), .I0 (), .I1 (divisor[6]), @@ -2555,7 +2565,7 @@ module divider_cell .I4_TO_LUT("FALSE")) \N20.fsub_8 ( .COUT (), - .Z (_N18860), + .Z (_N18824), .CIN (\N20.co [7] ), .I0 (), .I1 (divisor[7]), @@ -2572,7 +2582,7 @@ module divider_cell \N51_2[0]_1 ( .Z (N51[0]), .I0 (en), - .I1 (_N18853)); + .I1 (_N18817)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[1]_1 */ #( @@ -2580,7 +2590,7 @@ module divider_cell \N51_2[1]_1 ( .Z (N51[1]), .I0 (en), - .I1 (_N18854)); + .I1 (_N18818)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[2]_1 */ #( @@ -2588,7 +2598,7 @@ module divider_cell \N51_2[2]_1 ( .Z (N51[2]), .I0 (en), - .I1 (_N18855)); + .I1 (_N18819)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[3]_1 */ #( @@ -2596,7 +2606,7 @@ module divider_cell \N51_2[3]_1 ( .Z (N51[3]), .I0 (en), - .I1 (_N18856)); + .I1 (_N18820)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[4]_1 */ #( @@ -2604,7 +2614,7 @@ module divider_cell \N51_2[4]_1 ( .Z (N51[4]), .I0 (en), - .I1 (_N18857)); + .I1 (_N18821)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[5]_1 */ #( @@ -2612,7 +2622,7 @@ module divider_cell \N51_2[5]_1 ( .Z (N51[5]), .I0 (en), - .I1 (_N18858)); + .I1 (_N18822)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[6]_1 */ #( @@ -2620,7 +2630,7 @@ module divider_cell \N51_2[6]_1 ( .Z (N51[6]), .I0 (en), - .I1 (_N18859)); + .I1 (_N18823)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[7]_1 */ #( @@ -2628,7 +2638,7 @@ module divider_cell \N51_2[7]_1 ( .Z (N51[7]), .I0 (en), - .I1 (_N18860)); + .I1 (_N18824)); // LUT = I0&I1 ; GTP_LUT2 /* \N53[0]_1 */ #( @@ -3011,14 +3021,14 @@ module divider_cell_unq26 wire [7:0] N51; wire [7:0] N53; wire [11:0] N54; - wire _N18873; - wire _N18874; - wire _N18875; - wire _N18876; - wire _N18877; - wire _N18878; - wire _N18879; - wire _N18880; + wire _N18837; + wire _N18838; + wire _N18839; + wire _N18840; + wire _N18841; + wire _N18842; + wire _N18843; + wire _N18844; GTP_LUT5CARRY /* \N6.lt_0 */ #( .INIT(32'b00100000111100100000000000000000), @@ -3148,7 +3158,7 @@ module divider_cell_unq26 .I4_TO_LUT("FALSE")) \N20.fsub_1 ( .COUT (\N20.co [1] ), - .Z (_N18873), + .Z (_N18837), .CIN (\N20.co [0] ), .I0 (), .I1 (divisor[0]), @@ -3168,7 +3178,7 @@ module divider_cell_unq26 .I4_TO_LUT("FALSE")) \N20.fsub_2 ( .COUT (\N20.co [2] ), - .Z (_N18874), + .Z (_N18838), .CIN (\N20.co [1] ), .I0 (), .I1 (divisor[1]), @@ -3188,7 +3198,7 @@ module divider_cell_unq26 .I4_TO_LUT("FALSE")) \N20.fsub_3 ( .COUT (\N20.co [3] ), - .Z (_N18875), + .Z (_N18839), .CIN (\N20.co [2] ), .I0 (), .I1 (divisor[2]), @@ -3208,7 +3218,7 @@ module divider_cell_unq26 .I4_TO_LUT("FALSE")) \N20.fsub_4 ( .COUT (\N20.co [4] ), - .Z (_N18876), + .Z (_N18840), .CIN (\N20.co [3] ), .I0 (), .I1 (divisor[3]), @@ -3228,7 +3238,7 @@ module divider_cell_unq26 .I4_TO_LUT("FALSE")) \N20.fsub_5 ( .COUT (\N20.co [5] ), - .Z (_N18877), + .Z (_N18841), .CIN (\N20.co [4] ), .I0 (), .I1 (divisor[4]), @@ -3248,7 +3258,7 @@ module divider_cell_unq26 .I4_TO_LUT("FALSE")) \N20.fsub_6 ( .COUT (\N20.co [6] ), - .Z (_N18878), + .Z (_N18842), .CIN (\N20.co [5] ), .I0 (), .I1 (divisor[5]), @@ -3268,7 +3278,7 @@ module divider_cell_unq26 .I4_TO_LUT("FALSE")) \N20.fsub_7 ( .COUT (\N20.co [7] ), - .Z (_N18879), + .Z (_N18843), .CIN (\N20.co [6] ), .I0 (), .I1 (divisor[6]), @@ -3288,7 +3298,7 @@ module divider_cell_unq26 .I4_TO_LUT("FALSE")) \N20.fsub_8 ( .COUT (), - .Z (_N18880), + .Z (_N18844), .CIN (\N20.co [7] ), .I0 (), .I1 (divisor[7]), @@ -3305,7 +3315,7 @@ module divider_cell_unq26 \N51_2[0]_1 ( .Z (N51[0]), .I0 (en), - .I1 (_N18873)); + .I1 (_N18837)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[1]_1 */ #( @@ -3313,7 +3323,7 @@ module divider_cell_unq26 \N51_2[1]_1 ( .Z (N51[1]), .I0 (en), - .I1 (_N18874)); + .I1 (_N18838)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[2]_1 */ #( @@ -3321,7 +3331,7 @@ module divider_cell_unq26 \N51_2[2]_1 ( .Z (N51[2]), .I0 (en), - .I1 (_N18875)); + .I1 (_N18839)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[3]_1 */ #( @@ -3329,7 +3339,7 @@ module divider_cell_unq26 \N51_2[3]_1 ( .Z (N51[3]), .I0 (en), - .I1 (_N18876)); + .I1 (_N18840)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[4]_1 */ #( @@ -3337,7 +3347,7 @@ module divider_cell_unq26 \N51_2[4]_1 ( .Z (N51[4]), .I0 (en), - .I1 (_N18877)); + .I1 (_N18841)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[5]_1 */ #( @@ -3345,7 +3355,7 @@ module divider_cell_unq26 \N51_2[5]_1 ( .Z (N51[5]), .I0 (en), - .I1 (_N18878)); + .I1 (_N18842)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[6]_1 */ #( @@ -3353,7 +3363,7 @@ module divider_cell_unq26 \N51_2[6]_1 ( .Z (N51[6]), .I0 (en), - .I1 (_N18879)); + .I1 (_N18843)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[7]_1 */ #( @@ -3361,7 +3371,7 @@ module divider_cell_unq26 \N51_2[7]_1 ( .Z (N51[7]), .I0 (en), - .I1 (_N18880)); + .I1 (_N18844)); // LUT = I0&I1 ; GTP_LUT2 /* \N53[0]_1 */ #( @@ -3725,14 +3735,14 @@ module divider_cell_unq28 wire [7:0] N51; wire [7:0] N53; wire [11:0] N54; - wire _N18895; - wire _N18896; - wire _N18897; - wire _N18898; - wire _N18899; - wire _N18900; - wire _N18901; - wire _N18902; + wire _N18859; + wire _N18860; + wire _N18861; + wire _N18862; + wire _N18863; + wire _N18864; + wire _N18865; + wire _N18866; GTP_LUT5CARRY /* \N6.lt_0 */ #( .INIT(32'b00100000111100100000000000000000), @@ -3862,7 +3872,7 @@ module divider_cell_unq28 .I4_TO_LUT("FALSE")) \N20.fsub_1 ( .COUT (\N20.co [1] ), - .Z (_N18895), + .Z (_N18859), .CIN (\N20.co [0] ), .I0 (), .I1 (divisor[0]), @@ -3882,7 +3892,7 @@ module divider_cell_unq28 .I4_TO_LUT("FALSE")) \N20.fsub_2 ( .COUT (\N20.co [2] ), - .Z (_N18896), + .Z (_N18860), .CIN (\N20.co [1] ), .I0 (), .I1 (divisor[1]), @@ -3902,7 +3912,7 @@ module divider_cell_unq28 .I4_TO_LUT("FALSE")) \N20.fsub_3 ( .COUT (\N20.co [3] ), - .Z (_N18897), + .Z (_N18861), .CIN (\N20.co [2] ), .I0 (), .I1 (divisor[2]), @@ -3922,7 +3932,7 @@ module divider_cell_unq28 .I4_TO_LUT("FALSE")) \N20.fsub_4 ( .COUT (\N20.co [4] ), - .Z (_N18898), + .Z (_N18862), .CIN (\N20.co [3] ), .I0 (), .I1 (divisor[3]), @@ -3942,7 +3952,7 @@ module divider_cell_unq28 .I4_TO_LUT("FALSE")) \N20.fsub_5 ( .COUT (\N20.co [5] ), - .Z (_N18899), + .Z (_N18863), .CIN (\N20.co [4] ), .I0 (), .I1 (divisor[4]), @@ -3962,7 +3972,7 @@ module divider_cell_unq28 .I4_TO_LUT("FALSE")) \N20.fsub_6 ( .COUT (\N20.co [6] ), - .Z (_N18900), + .Z (_N18864), .CIN (\N20.co [5] ), .I0 (), .I1 (divisor[5]), @@ -3982,7 +3992,7 @@ module divider_cell_unq28 .I4_TO_LUT("FALSE")) \N20.fsub_7 ( .COUT (\N20.co [7] ), - .Z (_N18901), + .Z (_N18865), .CIN (\N20.co [6] ), .I0 (), .I1 (divisor[6]), @@ -4002,7 +4012,7 @@ module divider_cell_unq28 .I4_TO_LUT("FALSE")) \N20.fsub_8 ( .COUT (), - .Z (_N18902), + .Z (_N18866), .CIN (\N20.co [7] ), .I0 (), .I1 (divisor[7]), @@ -4019,7 +4029,7 @@ module divider_cell_unq28 \N51_2[0]_1 ( .Z (N51[0]), .I0 (en), - .I1 (_N18895)); + .I1 (_N18859)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[1]_1 */ #( @@ -4027,7 +4037,7 @@ module divider_cell_unq28 \N51_2[1]_1 ( .Z (N51[1]), .I0 (en), - .I1 (_N18896)); + .I1 (_N18860)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[2]_1 */ #( @@ -4035,7 +4045,7 @@ module divider_cell_unq28 \N51_2[2]_1 ( .Z (N51[2]), .I0 (en), - .I1 (_N18897)); + .I1 (_N18861)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[3]_1 */ #( @@ -4043,7 +4053,7 @@ module divider_cell_unq28 \N51_2[3]_1 ( .Z (N51[3]), .I0 (en), - .I1 (_N18898)); + .I1 (_N18862)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[4]_1 */ #( @@ -4051,7 +4061,7 @@ module divider_cell_unq28 \N51_2[4]_1 ( .Z (N51[4]), .I0 (en), - .I1 (_N18899)); + .I1 (_N18863)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[5]_1 */ #( @@ -4059,7 +4069,7 @@ module divider_cell_unq28 \N51_2[5]_1 ( .Z (N51[5]), .I0 (en), - .I1 (_N18900)); + .I1 (_N18864)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[6]_1 */ #( @@ -4067,7 +4077,7 @@ module divider_cell_unq28 \N51_2[6]_1 ( .Z (N51[6]), .I0 (en), - .I1 (_N18901)); + .I1 (_N18865)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[7]_1 */ #( @@ -4075,7 +4085,7 @@ module divider_cell_unq28 \N51_2[7]_1 ( .Z (N51[7]), .I0 (en), - .I1 (_N18902)); + .I1 (_N18866)); // LUT = I0&I1 ; GTP_LUT2 /* \N53[0]_1 */ #( @@ -4420,14 +4430,14 @@ module divider_cell_unq30 wire [7:0] N51; wire [7:0] N53; wire [11:0] N54; - wire _N18919; - wire _N18920; - wire _N18921; - wire _N18922; - wire _N18923; - wire _N18924; - wire _N18925; - wire _N18926; + wire _N18883; + wire _N18884; + wire _N18885; + wire _N18886; + wire _N18887; + wire _N18888; + wire _N18889; + wire _N18890; GTP_LUT5CARRY /* \N6.lt_0 */ #( .INIT(32'b00100000111100100000000000000000), @@ -4557,7 +4567,7 @@ module divider_cell_unq30 .I4_TO_LUT("FALSE")) \N20.fsub_1 ( .COUT (\N20.co [1] ), - .Z (_N18919), + .Z (_N18883), .CIN (\N20.co [0] ), .I0 (), .I1 (divisor[0]), @@ -4577,7 +4587,7 @@ module divider_cell_unq30 .I4_TO_LUT("FALSE")) \N20.fsub_2 ( .COUT (\N20.co [2] ), - .Z (_N18920), + .Z (_N18884), .CIN (\N20.co [1] ), .I0 (), .I1 (divisor[1]), @@ -4597,7 +4607,7 @@ module divider_cell_unq30 .I4_TO_LUT("FALSE")) \N20.fsub_3 ( .COUT (\N20.co [3] ), - .Z (_N18921), + .Z (_N18885), .CIN (\N20.co [2] ), .I0 (), .I1 (divisor[2]), @@ -4617,7 +4627,7 @@ module divider_cell_unq30 .I4_TO_LUT("FALSE")) \N20.fsub_4 ( .COUT (\N20.co [4] ), - .Z (_N18922), + .Z (_N18886), .CIN (\N20.co [3] ), .I0 (), .I1 (divisor[3]), @@ -4637,7 +4647,7 @@ module divider_cell_unq30 .I4_TO_LUT("FALSE")) \N20.fsub_5 ( .COUT (\N20.co [5] ), - .Z (_N18923), + .Z (_N18887), .CIN (\N20.co [4] ), .I0 (), .I1 (divisor[4]), @@ -4657,7 +4667,7 @@ module divider_cell_unq30 .I4_TO_LUT("FALSE")) \N20.fsub_6 ( .COUT (\N20.co [6] ), - .Z (_N18924), + .Z (_N18888), .CIN (\N20.co [5] ), .I0 (), .I1 (divisor[5]), @@ -4677,7 +4687,7 @@ module divider_cell_unq30 .I4_TO_LUT("FALSE")) \N20.fsub_7 ( .COUT (\N20.co [7] ), - .Z (_N18925), + .Z (_N18889), .CIN (\N20.co [6] ), .I0 (), .I1 (divisor[6]), @@ -4697,7 +4707,7 @@ module divider_cell_unq30 .I4_TO_LUT("FALSE")) \N20.fsub_8 ( .COUT (), - .Z (_N18926), + .Z (_N18890), .CIN (\N20.co [7] ), .I0 (), .I1 (divisor[7]), @@ -4714,7 +4724,7 @@ module divider_cell_unq30 \N51_2[0]_1 ( .Z (N51[0]), .I0 (en), - .I1 (_N18919)); + .I1 (_N18883)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[1]_1 */ #( @@ -4722,7 +4732,7 @@ module divider_cell_unq30 \N51_2[1]_1 ( .Z (N51[1]), .I0 (en), - .I1 (_N18920)); + .I1 (_N18884)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[2]_1 */ #( @@ -4730,7 +4740,7 @@ module divider_cell_unq30 \N51_2[2]_1 ( .Z (N51[2]), .I0 (en), - .I1 (_N18921)); + .I1 (_N18885)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[3]_1 */ #( @@ -4738,7 +4748,7 @@ module divider_cell_unq30 \N51_2[3]_1 ( .Z (N51[3]), .I0 (en), - .I1 (_N18922)); + .I1 (_N18886)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[4]_1 */ #( @@ -4746,7 +4756,7 @@ module divider_cell_unq30 \N51_2[4]_1 ( .Z (N51[4]), .I0 (en), - .I1 (_N18923)); + .I1 (_N18887)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[5]_1 */ #( @@ -4754,7 +4764,7 @@ module divider_cell_unq30 \N51_2[5]_1 ( .Z (N51[5]), .I0 (en), - .I1 (_N18924)); + .I1 (_N18888)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[6]_1 */ #( @@ -4762,7 +4772,7 @@ module divider_cell_unq30 \N51_2[6]_1 ( .Z (N51[6]), .I0 (en), - .I1 (_N18925)); + .I1 (_N18889)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[7]_1 */ #( @@ -4770,7 +4780,7 @@ module divider_cell_unq30 \N51_2[7]_1 ( .Z (N51[7]), .I0 (en), - .I1 (_N18926)); + .I1 (_N18890)); // LUT = I0&I1 ; GTP_LUT2 /* \N53[0]_1 */ #( @@ -5098,14 +5108,14 @@ module divider_cell_unq32 wire [7:0] N51; wire [7:0] N53; wire [11:0] N54; - wire _N18945; - wire _N18946; - wire _N18947; - wire _N18948; - wire _N18949; - wire _N18950; - wire _N18951; - wire _N18952; + wire _N18909; + wire _N18910; + wire _N18911; + wire _N18912; + wire _N18913; + wire _N18914; + wire _N18915; + wire _N18916; GTP_LUT5CARRY /* \N6.lt_0 */ #( .INIT(32'b00100000111100100000000000000000), @@ -5235,7 +5245,7 @@ module divider_cell_unq32 .I4_TO_LUT("FALSE")) \N20.fsub_1 ( .COUT (\N20.co [1] ), - .Z (_N18945), + .Z (_N18909), .CIN (\N20.co [0] ), .I0 (), .I1 (divisor[0]), @@ -5255,7 +5265,7 @@ module divider_cell_unq32 .I4_TO_LUT("FALSE")) \N20.fsub_2 ( .COUT (\N20.co [2] ), - .Z (_N18946), + .Z (_N18910), .CIN (\N20.co [1] ), .I0 (), .I1 (divisor[1]), @@ -5275,7 +5285,7 @@ module divider_cell_unq32 .I4_TO_LUT("FALSE")) \N20.fsub_3 ( .COUT (\N20.co [3] ), - .Z (_N18947), + .Z (_N18911), .CIN (\N20.co [2] ), .I0 (), .I1 (divisor[2]), @@ -5295,7 +5305,7 @@ module divider_cell_unq32 .I4_TO_LUT("FALSE")) \N20.fsub_4 ( .COUT (\N20.co [4] ), - .Z (_N18948), + .Z (_N18912), .CIN (\N20.co [3] ), .I0 (), .I1 (divisor[3]), @@ -5315,7 +5325,7 @@ module divider_cell_unq32 .I4_TO_LUT("FALSE")) \N20.fsub_5 ( .COUT (\N20.co [5] ), - .Z (_N18949), + .Z (_N18913), .CIN (\N20.co [4] ), .I0 (), .I1 (divisor[4]), @@ -5335,7 +5345,7 @@ module divider_cell_unq32 .I4_TO_LUT("FALSE")) \N20.fsub_6 ( .COUT (\N20.co [6] ), - .Z (_N18950), + .Z (_N18914), .CIN (\N20.co [5] ), .I0 (), .I1 (divisor[5]), @@ -5355,7 +5365,7 @@ module divider_cell_unq32 .I4_TO_LUT("FALSE")) \N20.fsub_7 ( .COUT (\N20.co [7] ), - .Z (_N18951), + .Z (_N18915), .CIN (\N20.co [6] ), .I0 (), .I1 (divisor[6]), @@ -5375,7 +5385,7 @@ module divider_cell_unq32 .I4_TO_LUT("FALSE")) \N20.fsub_8 ( .COUT (), - .Z (_N18952), + .Z (_N18916), .CIN (\N20.co [7] ), .I0 (), .I1 (divisor[7]), @@ -5392,7 +5402,7 @@ module divider_cell_unq32 \N51_2[0]_1 ( .Z (N51[0]), .I0 (en), - .I1 (_N18945)); + .I1 (_N18909)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[1]_1 */ #( @@ -5400,7 +5410,7 @@ module divider_cell_unq32 \N51_2[1]_1 ( .Z (N51[1]), .I0 (en), - .I1 (_N18946)); + .I1 (_N18910)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[2]_1 */ #( @@ -5408,7 +5418,7 @@ module divider_cell_unq32 \N51_2[2]_1 ( .Z (N51[2]), .I0 (en), - .I1 (_N18947)); + .I1 (_N18911)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[3]_1 */ #( @@ -5416,7 +5426,7 @@ module divider_cell_unq32 \N51_2[3]_1 ( .Z (N51[3]), .I0 (en), - .I1 (_N18948)); + .I1 (_N18912)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[4]_1 */ #( @@ -5424,7 +5434,7 @@ module divider_cell_unq32 \N51_2[4]_1 ( .Z (N51[4]), .I0 (en), - .I1 (_N18949)); + .I1 (_N18913)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[5]_1 */ #( @@ -5432,7 +5442,7 @@ module divider_cell_unq32 \N51_2[5]_1 ( .Z (N51[5]), .I0 (en), - .I1 (_N18950)); + .I1 (_N18914)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[6]_1 */ #( @@ -5440,7 +5450,7 @@ module divider_cell_unq32 \N51_2[6]_1 ( .Z (N51[6]), .I0 (en), - .I1 (_N18951)); + .I1 (_N18915)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[7]_1 */ #( @@ -5448,7 +5458,7 @@ module divider_cell_unq32 \N51_2[7]_1 ( .Z (N51[7]), .I0 (en), - .I1 (_N18952)); + .I1 (_N18916)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[8] */ #( @@ -5776,14 +5786,14 @@ module divider_cell_unq34 wire [7:0] N51; wire [7:0] N53; wire [11:0] N54; - wire _N18973; - wire _N18974; - wire _N18975; - wire _N18976; - wire _N18977; - wire _N18978; - wire _N18979; - wire _N18980; + wire _N18937; + wire _N18938; + wire _N18939; + wire _N18940; + wire _N18941; + wire _N18942; + wire _N18943; + wire _N18944; GTP_LUT5CARRY /* \N6.lt_0 */ #( .INIT(32'b00100000111100100000000000000000), @@ -5913,7 +5923,7 @@ module divider_cell_unq34 .I4_TO_LUT("FALSE")) \N20.fsub_1 ( .COUT (\N20.co [1] ), - .Z (_N18973), + .Z (_N18937), .CIN (\N20.co [0] ), .I0 (), .I1 (divisor[0]), @@ -5933,7 +5943,7 @@ module divider_cell_unq34 .I4_TO_LUT("FALSE")) \N20.fsub_2 ( .COUT (\N20.co [2] ), - .Z (_N18974), + .Z (_N18938), .CIN (\N20.co [1] ), .I0 (), .I1 (divisor[1]), @@ -5953,7 +5963,7 @@ module divider_cell_unq34 .I4_TO_LUT("FALSE")) \N20.fsub_3 ( .COUT (\N20.co [3] ), - .Z (_N18975), + .Z (_N18939), .CIN (\N20.co [2] ), .I0 (), .I1 (divisor[2]), @@ -5973,7 +5983,7 @@ module divider_cell_unq34 .I4_TO_LUT("FALSE")) \N20.fsub_4 ( .COUT (\N20.co [4] ), - .Z (_N18976), + .Z (_N18940), .CIN (\N20.co [3] ), .I0 (), .I1 (divisor[3]), @@ -5993,7 +6003,7 @@ module divider_cell_unq34 .I4_TO_LUT("FALSE")) \N20.fsub_5 ( .COUT (\N20.co [5] ), - .Z (_N18977), + .Z (_N18941), .CIN (\N20.co [4] ), .I0 (), .I1 (divisor[4]), @@ -6013,7 +6023,7 @@ module divider_cell_unq34 .I4_TO_LUT("FALSE")) \N20.fsub_6 ( .COUT (\N20.co [6] ), - .Z (_N18978), + .Z (_N18942), .CIN (\N20.co [5] ), .I0 (), .I1 (divisor[5]), @@ -6033,7 +6043,7 @@ module divider_cell_unq34 .I4_TO_LUT("FALSE")) \N20.fsub_7 ( .COUT (\N20.co [7] ), - .Z (_N18979), + .Z (_N18943), .CIN (\N20.co [6] ), .I0 (), .I1 (divisor[6]), @@ -6053,7 +6063,7 @@ module divider_cell_unq34 .I4_TO_LUT("FALSE")) \N20.fsub_8 ( .COUT (), - .Z (_N18980), + .Z (_N18944), .CIN (\N20.co [7] ), .I0 (), .I1 (divisor[7]), @@ -6070,7 +6080,7 @@ module divider_cell_unq34 \N51_2[0]_1 ( .Z (N51[0]), .I0 (en), - .I1 (_N18973)); + .I1 (_N18937)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[1]_1 */ #( @@ -6078,7 +6088,7 @@ module divider_cell_unq34 \N51_2[1]_1 ( .Z (N51[1]), .I0 (en), - .I1 (_N18974)); + .I1 (_N18938)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[2]_1 */ #( @@ -6086,7 +6096,7 @@ module divider_cell_unq34 \N51_2[2]_1 ( .Z (N51[2]), .I0 (en), - .I1 (_N18975)); + .I1 (_N18939)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[3]_1 */ #( @@ -6094,7 +6104,7 @@ module divider_cell_unq34 \N51_2[3]_1 ( .Z (N51[3]), .I0 (en), - .I1 (_N18976)); + .I1 (_N18940)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[4]_1 */ #( @@ -6102,7 +6112,7 @@ module divider_cell_unq34 \N51_2[4]_1 ( .Z (N51[4]), .I0 (en), - .I1 (_N18977)); + .I1 (_N18941)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[5]_1 */ #( @@ -6110,7 +6120,7 @@ module divider_cell_unq34 \N51_2[5]_1 ( .Z (N51[5]), .I0 (en), - .I1 (_N18978)); + .I1 (_N18942)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[6]_1 */ #( @@ -6118,7 +6128,7 @@ module divider_cell_unq34 \N51_2[6]_1 ( .Z (N51[6]), .I0 (en), - .I1 (_N18979)); + .I1 (_N18943)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[7]_1 */ #( @@ -6126,7 +6136,7 @@ module divider_cell_unq34 \N51_2[7]_1 ( .Z (N51[7]), .I0 (en), - .I1 (_N18980)); + .I1 (_N18944)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[8]_1 */ #( @@ -6450,14 +6460,14 @@ module divider_cell_unq36 wire [12:0] N45; wire [7:0] N51; wire [7:0] N53; - wire _N19032; - wire _N19033; - wire _N19034; - wire _N19035; - wire _N19036; - wire _N19037; - wire _N19038; - wire _N19039; + wire _N18985; + wire _N18986; + wire _N18987; + wire _N18988; + wire _N18989; + wire _N18990; + wire _N18991; + wire _N18992; GTP_LUT5CARRY /* \N6.lt_0 */ #( .INIT(32'b00100000111100100000000000000000), @@ -6587,7 +6597,7 @@ module divider_cell_unq36 .I4_TO_LUT("FALSE")) \N20.fsub_1 ( .COUT (\N20.co [1] ), - .Z (_N19032), + .Z (_N18985), .CIN (\N20.co [0] ), .I0 (), .I1 (divisor[0]), @@ -6607,7 +6617,7 @@ module divider_cell_unq36 .I4_TO_LUT("FALSE")) \N20.fsub_2 ( .COUT (\N20.co [2] ), - .Z (_N19033), + .Z (_N18986), .CIN (\N20.co [1] ), .I0 (), .I1 (divisor[1]), @@ -6627,7 +6637,7 @@ module divider_cell_unq36 .I4_TO_LUT("FALSE")) \N20.fsub_3 ( .COUT (\N20.co [3] ), - .Z (_N19034), + .Z (_N18987), .CIN (\N20.co [2] ), .I0 (), .I1 (divisor[2]), @@ -6647,7 +6657,7 @@ module divider_cell_unq36 .I4_TO_LUT("FALSE")) \N20.fsub_4 ( .COUT (\N20.co [4] ), - .Z (_N19035), + .Z (_N18988), .CIN (\N20.co [3] ), .I0 (), .I1 (divisor[3]), @@ -6667,7 +6677,7 @@ module divider_cell_unq36 .I4_TO_LUT("FALSE")) \N20.fsub_5 ( .COUT (\N20.co [5] ), - .Z (_N19036), + .Z (_N18989), .CIN (\N20.co [4] ), .I0 (), .I1 (divisor[4]), @@ -6687,7 +6697,7 @@ module divider_cell_unq36 .I4_TO_LUT("FALSE")) \N20.fsub_6 ( .COUT (\N20.co [6] ), - .Z (_N19037), + .Z (_N18990), .CIN (\N20.co [5] ), .I0 (), .I1 (divisor[5]), @@ -6707,7 +6717,7 @@ module divider_cell_unq36 .I4_TO_LUT("FALSE")) \N20.fsub_7 ( .COUT (\N20.co [7] ), - .Z (_N19038), + .Z (_N18991), .CIN (\N20.co [6] ), .I0 (), .I1 (divisor[6]), @@ -6727,7 +6737,7 @@ module divider_cell_unq36 .I4_TO_LUT("FALSE")) \N20.fsub_8 ( .COUT (), - .Z (_N19039), + .Z (_N18992), .CIN (\N20.co [7] ), .I0 (), .I1 (divisor[7]), @@ -6744,7 +6754,7 @@ module divider_cell_unq36 \N51_2[0]_1 ( .Z (N51[0]), .I0 (en), - .I1 (_N19032)); + .I1 (_N18985)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[1]_1 */ #( @@ -6752,7 +6762,7 @@ module divider_cell_unq36 \N51_2[1]_1 ( .Z (N51[1]), .I0 (en), - .I1 (_N19033)); + .I1 (_N18986)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[2]_1 */ #( @@ -6760,7 +6770,7 @@ module divider_cell_unq36 \N51_2[2]_1 ( .Z (N51[2]), .I0 (en), - .I1 (_N19034)); + .I1 (_N18987)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[3]_1 */ #( @@ -6768,7 +6778,7 @@ module divider_cell_unq36 \N51_2[3]_1 ( .Z (N51[3]), .I0 (en), - .I1 (_N19035)); + .I1 (_N18988)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[4]_1 */ #( @@ -6776,7 +6786,7 @@ module divider_cell_unq36 \N51_2[4]_1 ( .Z (N51[4]), .I0 (en), - .I1 (_N19036)); + .I1 (_N18989)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[5]_1 */ #( @@ -6784,7 +6794,7 @@ module divider_cell_unq36 \N51_2[5]_1 ( .Z (N51[5]), .I0 (en), - .I1 (_N19037)); + .I1 (_N18990)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[6]_1 */ #( @@ -6792,7 +6802,7 @@ module divider_cell_unq36 \N51_2[6]_1 ( .Z (N51[6]), .I0 (en), - .I1 (_N19038)); + .I1 (_N18991)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[7]_1 */ #( @@ -6800,7 +6810,7 @@ module divider_cell_unq36 \N51_2[7]_1 ( .Z (N51[7]), .I0 (en), - .I1 (_N19039)); + .I1 (_N18992)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[8]_1 */ #( @@ -7106,34 +7116,30 @@ endmodule module divider_cell_unq38 ( - input [12:0] N45, input [8:0] dividend, input [7:0] divisor, input [12:0] quotient_ci, - input \adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N6 , input clk, input en, input sync_vg_100m, - output [15:0] \adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45 , output [7:0] divisor_kp, output [12:0] quotient, output [7:0] remainder, - output N6, output rdy ); + wire N6; wire [9:0] \N6.co ; wire [7:0] \N20_1.co ; - wire [12:0] N45_alias; + wire [12:0] N45; wire [7:0] N51; wire [7:0] N53; - wire _N19065; - wire _N19066; - wire _N19067; - wire _N19068; - wire _N19069; - wire _N19070; - wire _N19071; - assign N45_alias[0] = N45[0]; + wire _N19032; + wire _N19033; + wire _N19034; + wire _N19035; + wire _N19036; + wire _N19037; + wire _N19038; GTP_LUT5CARRY /* \N6.lt_0 */ #( .INIT(32'b10001110100011100000000000000000), @@ -7263,7 +7269,7 @@ module divider_cell_unq38 .I4_TO_LUT("FALSE")) \N20_1.fsub_1 ( .COUT (\N20_1.co [1] ), - .Z (_N19065), + .Z (_N19032), .CIN (\N20_1.co [0] ), .I0 (), .I1 (divisor[1]), @@ -7283,7 +7289,7 @@ module divider_cell_unq38 .I4_TO_LUT("FALSE")) \N20_1.fsub_2 ( .COUT (\N20_1.co [2] ), - .Z (_N19066), + .Z (_N19033), .CIN (\N20_1.co [1] ), .I0 (), .I1 (divisor[2]), @@ -7303,7 +7309,7 @@ module divider_cell_unq38 .I4_TO_LUT("FALSE")) \N20_1.fsub_3 ( .COUT (\N20_1.co [3] ), - .Z (_N19067), + .Z (_N19034), .CIN (\N20_1.co [2] ), .I0 (), .I1 (divisor[3]), @@ -7323,7 +7329,7 @@ module divider_cell_unq38 .I4_TO_LUT("FALSE")) \N20_1.fsub_4 ( .COUT (\N20_1.co [4] ), - .Z (_N19068), + .Z (_N19035), .CIN (\N20_1.co [3] ), .I0 (), .I1 (divisor[4]), @@ -7343,7 +7349,7 @@ module divider_cell_unq38 .I4_TO_LUT("FALSE")) \N20_1.fsub_5 ( .COUT (\N20_1.co [5] ), - .Z (_N19069), + .Z (_N19036), .CIN (\N20_1.co [4] ), .I0 (), .I1 (divisor[5]), @@ -7363,7 +7369,7 @@ module divider_cell_unq38 .I4_TO_LUT("FALSE")) \N20_1.fsub_6 ( .COUT (\N20_1.co [6] ), - .Z (_N19070), + .Z (_N19037), .CIN (\N20_1.co [5] ), .I0 (), .I1 (divisor[6]), @@ -7383,7 +7389,7 @@ module divider_cell_unq38 .I4_TO_LUT("FALSE")) \N20_1.fsub_7 ( .COUT (), - .Z (_N19071), + .Z (_N19038), .CIN (\N20_1.co [6] ), .I0 (), .I1 (divisor[7]), @@ -7407,9 +7413,9 @@ module divider_cell_unq38 GTP_LUT2 /* \N51_2[0]_1 */ #( .INIT(4'b0010)) \N51_2[0]_1 ( - .Z (\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45 [0] ), + .Z (N45[0]), .I0 (en), - .I1 (\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N6 )); + .I1 (N6)); // LUT = I0&~I1 ; GTP_LUT2 /* \N51_2[1] */ #( @@ -7417,7 +7423,7 @@ module divider_cell_unq38 \N51_2[1] ( .Z (N51[1]), .I0 (en), - .I1 (_N19065)); + .I1 (_N19032)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[2] */ #( @@ -7425,7 +7431,7 @@ module divider_cell_unq38 \N51_2[2] ( .Z (N51[2]), .I0 (en), - .I1 (_N19066)); + .I1 (_N19033)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[3] */ #( @@ -7433,7 +7439,7 @@ module divider_cell_unq38 \N51_2[3] ( .Z (N51[3]), .I0 (en), - .I1 (_N19067)); + .I1 (_N19034)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[4] */ #( @@ -7441,7 +7447,7 @@ module divider_cell_unq38 \N51_2[4] ( .Z (N51[4]), .I0 (en), - .I1 (_N19068)); + .I1 (_N19035)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[5] */ #( @@ -7449,7 +7455,7 @@ module divider_cell_unq38 \N51_2[5] ( .Z (N51[5]), .I0 (en), - .I1 (_N19069)); + .I1 (_N19036)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[6] */ #( @@ -7457,7 +7463,7 @@ module divider_cell_unq38 \N51_2[6] ( .Z (N51[6]), .I0 (en), - .I1 (_N19070)); + .I1 (_N19037)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[7] */ #( @@ -7465,13 +7471,13 @@ module divider_cell_unq38 \N51_2[7] ( .Z (N51[7]), .I0 (en), - .I1 (_N19071)); + .I1 (_N19038)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[9] */ #( .INIT(4'b1000)) \N51_2[9] ( - .Z (N45_alias[1]), + .Z (N45[1]), .I0 (quotient_ci[0]), .I1 (en)); // LUT = I0&I1 ; @@ -7479,7 +7485,7 @@ module divider_cell_unq38 GTP_LUT2 /* \N51_2[10] */ #( .INIT(4'b1000)) \N51_2[10] ( - .Z (N45_alias[2]), + .Z (N45[2]), .I0 (quotient_ci[1]), .I1 (en)); // LUT = I0&I1 ; @@ -7487,7 +7493,7 @@ module divider_cell_unq38 GTP_LUT2 /* \N51_2[11] */ #( .INIT(4'b1000)) \N51_2[11] ( - .Z (N45_alias[3]), + .Z (N45[3]), .I0 (quotient_ci[2]), .I1 (en)); // LUT = I0&I1 ; @@ -7651,7 +7657,7 @@ module divider_cell_unq38 .Q (quotient[0]), .C (sync_vg_100m), .CLK (clk), - .D (N45_alias[0])); + .D (N45[0])); // ../../sources/designs/adjust_color/divider_cell.v:24 GTP_DFF_C /* \quotient[1] */ #( @@ -7661,7 +7667,7 @@ module divider_cell_unq38 .Q (quotient[1]), .C (sync_vg_100m), .CLK (clk), - .D (N45_alias[1])); + .D (N45[1])); // ../../sources/designs/adjust_color/divider_cell.v:24 GTP_DFF_C /* \quotient[2] */ #( @@ -7671,7 +7677,7 @@ module divider_cell_unq38 .Q (quotient[2]), .C (sync_vg_100m), .CLK (clk), - .D (N45_alias[2])); + .D (N45[2])); // ../../sources/designs/adjust_color/divider_cell.v:24 GTP_DFF_C /* \quotient[3] */ #( @@ -7681,7 +7687,7 @@ module divider_cell_unq38 .Q (quotient[3]), .C (sync_vg_100m), .CLK (clk), - .D (N45_alias[3])); + .D (N45[3])); // ../../sources/designs/adjust_color/divider_cell.v:24 GTP_DFF_C /* rdy */ #( @@ -7781,34 +7787,30 @@ endmodule module divider_cell_unq40 ( - input [12:0] N45, input [8:0] dividend, input [7:0] divisor, input [12:0] quotient_ci, - input \adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N6 , input clk, input en, input sync_vg_100m, - output [15:0] \adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45 , output [7:0] divisor_kp, output [12:0] quotient, output [7:0] remainder, - output N6, output rdy ); + wire N6; wire [9:0] \N6.co ; wire [7:0] \N20_1.co ; - wire [12:0] N45_alias; + wire [12:0] N45; wire [7:0] N51; wire [7:0] N53; - wire _N19099; - wire _N19100; - wire _N19101; - wire _N19102; - wire _N19103; - wire _N19104; - wire _N19105; - assign N45_alias[0] = N45[0]; + wire _N19066; + wire _N19067; + wire _N19068; + wire _N19069; + wire _N19070; + wire _N19071; + wire _N19072; GTP_LUT5CARRY /* \N6.lt_0 */ #( .INIT(32'b10001110100011100000000000000000), @@ -7938,7 +7940,7 @@ module divider_cell_unq40 .I4_TO_LUT("FALSE")) \N20_1.fsub_1 ( .COUT (\N20_1.co [1] ), - .Z (_N19099), + .Z (_N19066), .CIN (\N20_1.co [0] ), .I0 (), .I1 (divisor[1]), @@ -7958,7 +7960,7 @@ module divider_cell_unq40 .I4_TO_LUT("FALSE")) \N20_1.fsub_2 ( .COUT (\N20_1.co [2] ), - .Z (_N19100), + .Z (_N19067), .CIN (\N20_1.co [1] ), .I0 (), .I1 (divisor[2]), @@ -7978,7 +7980,7 @@ module divider_cell_unq40 .I4_TO_LUT("FALSE")) \N20_1.fsub_3 ( .COUT (\N20_1.co [3] ), - .Z (_N19101), + .Z (_N19068), .CIN (\N20_1.co [2] ), .I0 (), .I1 (divisor[3]), @@ -7998,7 +8000,7 @@ module divider_cell_unq40 .I4_TO_LUT("FALSE")) \N20_1.fsub_4 ( .COUT (\N20_1.co [4] ), - .Z (_N19102), + .Z (_N19069), .CIN (\N20_1.co [3] ), .I0 (), .I1 (divisor[4]), @@ -8018,7 +8020,7 @@ module divider_cell_unq40 .I4_TO_LUT("FALSE")) \N20_1.fsub_5 ( .COUT (\N20_1.co [5] ), - .Z (_N19103), + .Z (_N19070), .CIN (\N20_1.co [4] ), .I0 (), .I1 (divisor[5]), @@ -8038,7 +8040,7 @@ module divider_cell_unq40 .I4_TO_LUT("FALSE")) \N20_1.fsub_6 ( .COUT (\N20_1.co [6] ), - .Z (_N19104), + .Z (_N19071), .CIN (\N20_1.co [5] ), .I0 (), .I1 (divisor[6]), @@ -8058,7 +8060,7 @@ module divider_cell_unq40 .I4_TO_LUT("FALSE")) \N20_1.fsub_7 ( .COUT (), - .Z (_N19105), + .Z (_N19072), .CIN (\N20_1.co [6] ), .I0 (), .I1 (divisor[7]), @@ -8082,9 +8084,9 @@ module divider_cell_unq40 GTP_LUT2 /* \N51_2[0]_1 */ #( .INIT(4'b0010)) \N51_2[0]_1 ( - .Z (\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45 [0] ), + .Z (N45[0]), .I0 (en), - .I1 (\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N6 )); + .I1 (N6)); // LUT = I0&~I1 ; GTP_LUT2 /* \N51_2[1] */ #( @@ -8092,7 +8094,7 @@ module divider_cell_unq40 \N51_2[1] ( .Z (N51[1]), .I0 (en), - .I1 (_N19099)); + .I1 (_N19066)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[2] */ #( @@ -8100,7 +8102,7 @@ module divider_cell_unq40 \N51_2[2] ( .Z (N51[2]), .I0 (en), - .I1 (_N19100)); + .I1 (_N19067)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[3] */ #( @@ -8108,7 +8110,7 @@ module divider_cell_unq40 \N51_2[3] ( .Z (N51[3]), .I0 (en), - .I1 (_N19101)); + .I1 (_N19068)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[4] */ #( @@ -8116,7 +8118,7 @@ module divider_cell_unq40 \N51_2[4] ( .Z (N51[4]), .I0 (en), - .I1 (_N19102)); + .I1 (_N19069)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[5] */ #( @@ -8124,7 +8126,7 @@ module divider_cell_unq40 \N51_2[5] ( .Z (N51[5]), .I0 (en), - .I1 (_N19103)); + .I1 (_N19070)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[6] */ #( @@ -8132,7 +8134,7 @@ module divider_cell_unq40 \N51_2[6] ( .Z (N51[6]), .I0 (en), - .I1 (_N19104)); + .I1 (_N19071)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[7] */ #( @@ -8140,13 +8142,13 @@ module divider_cell_unq40 \N51_2[7] ( .Z (N51[7]), .I0 (en), - .I1 (_N19105)); + .I1 (_N19072)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[9] */ #( .INIT(4'b1000)) \N51_2[9] ( - .Z (N45_alias[1]), + .Z (N45[1]), .I0 (quotient_ci[0]), .I1 (en)); // LUT = I0&I1 ; @@ -8154,7 +8156,7 @@ module divider_cell_unq40 GTP_LUT2 /* \N51_2[10] */ #( .INIT(4'b1000)) \N51_2[10] ( - .Z (N45_alias[2]), + .Z (N45[2]), .I0 (quotient_ci[1]), .I1 (en)); // LUT = I0&I1 ; @@ -8162,7 +8164,7 @@ module divider_cell_unq40 GTP_LUT2 /* \N51_2[11] */ #( .INIT(4'b1000)) \N51_2[11] ( - .Z (N45_alias[3]), + .Z (N45[3]), .I0 (quotient_ci[2]), .I1 (en)); // LUT = I0&I1 ; @@ -8170,7 +8172,7 @@ module divider_cell_unq40 GTP_LUT2 /* \N51_2[12] */ #( .INIT(4'b1000)) \N51_2[12] ( - .Z (N45_alias[4]), + .Z (N45[4]), .I0 (quotient_ci[3]), .I1 (en)); // LUT = I0&I1 ; @@ -8334,7 +8336,7 @@ module divider_cell_unq40 .Q (quotient[0]), .C (sync_vg_100m), .CLK (clk), - .D (N45_alias[0])); + .D (N45[0])); // ../../sources/designs/adjust_color/divider_cell.v:24 GTP_DFF_C /* \quotient[1] */ #( @@ -8344,7 +8346,7 @@ module divider_cell_unq40 .Q (quotient[1]), .C (sync_vg_100m), .CLK (clk), - .D (N45_alias[1])); + .D (N45[1])); // ../../sources/designs/adjust_color/divider_cell.v:24 GTP_DFF_C /* \quotient[2] */ #( @@ -8354,7 +8356,7 @@ module divider_cell_unq40 .Q (quotient[2]), .C (sync_vg_100m), .CLK (clk), - .D (N45_alias[2])); + .D (N45[2])); // ../../sources/designs/adjust_color/divider_cell.v:24 GTP_DFF_C /* \quotient[3] */ #( @@ -8364,7 +8366,7 @@ module divider_cell_unq40 .Q (quotient[3]), .C (sync_vg_100m), .CLK (clk), - .D (N45_alias[3])); + .D (N45[3])); // ../../sources/designs/adjust_color/divider_cell.v:24 GTP_DFF_C /* \quotient[4] */ #( @@ -8374,7 +8376,7 @@ module divider_cell_unq40 .Q (quotient[4]), .C (sync_vg_100m), .CLK (clk), - .D (N45_alias[4])); + .D (N45[4])); // ../../sources/designs/adjust_color/divider_cell.v:24 GTP_DFF_C /* rdy */ #( @@ -8474,34 +8476,30 @@ endmodule module divider_cell_unq42 ( - input [12:0] N45, input [8:0] dividend, input [7:0] divisor, input [12:0] quotient_ci, - input \adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N6 , input clk, input en, input sync_vg_100m, - output [15:0] \adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45 , output [7:0] divisor_kp, output [12:0] quotient, output [7:0] remainder, - output N6, output rdy ); + wire N6; wire [9:0] \N6.co ; wire [7:0] \N20_1.co ; - wire [12:0] N45_alias; + wire [12:0] N45; wire [7:0] N51; wire [7:0] N53; - wire _N19249; - wire _N19250; - wire _N19251; - wire _N19252; - wire _N19253; - wire _N19254; - wire _N19255; - assign N45_alias[0] = N45[0]; + wire _N19216; + wire _N19217; + wire _N19218; + wire _N19219; + wire _N19220; + wire _N19221; + wire _N19222; GTP_LUT5CARRY /* \N6.lt_0 */ #( .INIT(32'b10001110100011100000000000000000), @@ -8631,7 +8629,7 @@ module divider_cell_unq42 .I4_TO_LUT("FALSE")) \N20_1.fsub_1 ( .COUT (\N20_1.co [1] ), - .Z (_N19249), + .Z (_N19216), .CIN (\N20_1.co [0] ), .I0 (), .I1 (divisor[1]), @@ -8651,7 +8649,7 @@ module divider_cell_unq42 .I4_TO_LUT("FALSE")) \N20_1.fsub_2 ( .COUT (\N20_1.co [2] ), - .Z (_N19250), + .Z (_N19217), .CIN (\N20_1.co [1] ), .I0 (), .I1 (divisor[2]), @@ -8671,7 +8669,7 @@ module divider_cell_unq42 .I4_TO_LUT("FALSE")) \N20_1.fsub_3 ( .COUT (\N20_1.co [3] ), - .Z (_N19251), + .Z (_N19218), .CIN (\N20_1.co [2] ), .I0 (), .I1 (divisor[3]), @@ -8691,7 +8689,7 @@ module divider_cell_unq42 .I4_TO_LUT("FALSE")) \N20_1.fsub_4 ( .COUT (\N20_1.co [4] ), - .Z (_N19252), + .Z (_N19219), .CIN (\N20_1.co [3] ), .I0 (), .I1 (divisor[4]), @@ -8711,7 +8709,7 @@ module divider_cell_unq42 .I4_TO_LUT("FALSE")) \N20_1.fsub_5 ( .COUT (\N20_1.co [5] ), - .Z (_N19253), + .Z (_N19220), .CIN (\N20_1.co [4] ), .I0 (), .I1 (divisor[5]), @@ -8731,7 +8729,7 @@ module divider_cell_unq42 .I4_TO_LUT("FALSE")) \N20_1.fsub_6 ( .COUT (\N20_1.co [6] ), - .Z (_N19254), + .Z (_N19221), .CIN (\N20_1.co [5] ), .I0 (), .I1 (divisor[6]), @@ -8751,7 +8749,7 @@ module divider_cell_unq42 .I4_TO_LUT("FALSE")) \N20_1.fsub_7 ( .COUT (), - .Z (_N19255), + .Z (_N19222), .CIN (\N20_1.co [6] ), .I0 (), .I1 (divisor[7]), @@ -8775,9 +8773,9 @@ module divider_cell_unq42 GTP_LUT2 /* \N51_2[0]_1 */ #( .INIT(4'b0010)) \N51_2[0]_1 ( - .Z (\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45 [0] ), + .Z (N45[0]), .I0 (en), - .I1 (\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N6 )); + .I1 (N6)); // LUT = I0&~I1 ; GTP_LUT2 /* \N51_2[1] */ #( @@ -8785,7 +8783,7 @@ module divider_cell_unq42 \N51_2[1] ( .Z (N51[1]), .I0 (en), - .I1 (_N19249)); + .I1 (_N19216)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[2] */ #( @@ -8793,7 +8791,7 @@ module divider_cell_unq42 \N51_2[2] ( .Z (N51[2]), .I0 (en), - .I1 (_N19250)); + .I1 (_N19217)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[3] */ #( @@ -8801,7 +8799,7 @@ module divider_cell_unq42 \N51_2[3] ( .Z (N51[3]), .I0 (en), - .I1 (_N19251)); + .I1 (_N19218)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[4] */ #( @@ -8809,7 +8807,7 @@ module divider_cell_unq42 \N51_2[4] ( .Z (N51[4]), .I0 (en), - .I1 (_N19252)); + .I1 (_N19219)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[5] */ #( @@ -8817,7 +8815,7 @@ module divider_cell_unq42 \N51_2[5] ( .Z (N51[5]), .I0 (en), - .I1 (_N19253)); + .I1 (_N19220)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[6] */ #( @@ -8825,7 +8823,7 @@ module divider_cell_unq42 \N51_2[6] ( .Z (N51[6]), .I0 (en), - .I1 (_N19254)); + .I1 (_N19221)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[7] */ #( @@ -8833,13 +8831,13 @@ module divider_cell_unq42 \N51_2[7] ( .Z (N51[7]), .I0 (en), - .I1 (_N19255)); + .I1 (_N19222)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[9] */ #( .INIT(4'b1000)) \N51_2[9] ( - .Z (N45_alias[1]), + .Z (N45[1]), .I0 (quotient_ci[0]), .I1 (en)); // LUT = I0&I1 ; @@ -8847,7 +8845,7 @@ module divider_cell_unq42 GTP_LUT2 /* \N51_2[10] */ #( .INIT(4'b1000)) \N51_2[10] ( - .Z (N45_alias[2]), + .Z (N45[2]), .I0 (quotient_ci[1]), .I1 (en)); // LUT = I0&I1 ; @@ -8855,7 +8853,7 @@ module divider_cell_unq42 GTP_LUT2 /* \N51_2[11] */ #( .INIT(4'b1000)) \N51_2[11] ( - .Z (N45_alias[3]), + .Z (N45[3]), .I0 (quotient_ci[2]), .I1 (en)); // LUT = I0&I1 ; @@ -8863,7 +8861,7 @@ module divider_cell_unq42 GTP_LUT2 /* \N51_2[12] */ #( .INIT(4'b1000)) \N51_2[12] ( - .Z (N45_alias[4]), + .Z (N45[4]), .I0 (quotient_ci[3]), .I1 (en)); // LUT = I0&I1 ; @@ -8871,7 +8869,7 @@ module divider_cell_unq42 GTP_LUT2 /* \N51_2[13] */ #( .INIT(4'b1000)) \N51_2[13] ( - .Z (N45_alias[5]), + .Z (N45[5]), .I0 (quotient_ci[4]), .I1 (en)); // LUT = I0&I1 ; @@ -9035,7 +9033,7 @@ module divider_cell_unq42 .Q (quotient[0]), .C (sync_vg_100m), .CLK (clk), - .D (N45_alias[0])); + .D (N45[0])); // ../../sources/designs/adjust_color/divider_cell.v:24 GTP_DFF_C /* \quotient[1] */ #( @@ -9045,7 +9043,7 @@ module divider_cell_unq42 .Q (quotient[1]), .C (sync_vg_100m), .CLK (clk), - .D (N45_alias[1])); + .D (N45[1])); // ../../sources/designs/adjust_color/divider_cell.v:24 GTP_DFF_C /* \quotient[2] */ #( @@ -9055,7 +9053,7 @@ module divider_cell_unq42 .Q (quotient[2]), .C (sync_vg_100m), .CLK (clk), - .D (N45_alias[2])); + .D (N45[2])); // ../../sources/designs/adjust_color/divider_cell.v:24 GTP_DFF_C /* \quotient[3] */ #( @@ -9065,7 +9063,7 @@ module divider_cell_unq42 .Q (quotient[3]), .C (sync_vg_100m), .CLK (clk), - .D (N45_alias[3])); + .D (N45[3])); // ../../sources/designs/adjust_color/divider_cell.v:24 GTP_DFF_C /* \quotient[4] */ #( @@ -9075,7 +9073,7 @@ module divider_cell_unq42 .Q (quotient[4]), .C (sync_vg_100m), .CLK (clk), - .D (N45_alias[4])); + .D (N45[4])); // ../../sources/designs/adjust_color/divider_cell.v:24 GTP_DFF_C /* \quotient[5] */ #( @@ -9085,7 +9083,7 @@ module divider_cell_unq42 .Q (quotient[5]), .C (sync_vg_100m), .CLK (clk), - .D (N45_alias[5])); + .D (N45[5])); // ../../sources/designs/adjust_color/divider_cell.v:24 GTP_DFF_C /* rdy */ #( @@ -9185,34 +9183,30 @@ endmodule module divider_cell_unq44 ( - input [12:0] N45, input [8:0] dividend, input [7:0] divisor, input [12:0] quotient_ci, - input \adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N6 , input clk, input en, input sync_vg_100m, - output [15:0] \adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45 , output [7:0] divisor_kp, output [12:0] quotient, output [7:0] remainder, - output N6, output rdy ); + wire N6; wire [9:0] \N6.co ; wire [7:0] \N20_1.co ; - wire [12:0] N45_alias; + wire [12:0] N45; wire [7:0] N51; wire [7:0] N53; - wire _N19147; - wire _N19148; - wire _N19149; - wire _N19150; - wire _N19151; - wire _N19152; - wire _N19153; - assign N45_alias[0] = N45[0]; + wire _N19132; + wire _N19133; + wire _N19134; + wire _N19135; + wire _N19136; + wire _N19137; + wire _N19138; GTP_LUT5CARRY /* \N6.lt_0 */ #( .INIT(32'b10001110100011100000000000000000), @@ -9342,7 +9336,7 @@ module divider_cell_unq44 .I4_TO_LUT("FALSE")) \N20_1.fsub_1 ( .COUT (\N20_1.co [1] ), - .Z (_N19147), + .Z (_N19132), .CIN (\N20_1.co [0] ), .I0 (), .I1 (divisor[1]), @@ -9362,7 +9356,7 @@ module divider_cell_unq44 .I4_TO_LUT("FALSE")) \N20_1.fsub_2 ( .COUT (\N20_1.co [2] ), - .Z (_N19148), + .Z (_N19133), .CIN (\N20_1.co [1] ), .I0 (), .I1 (divisor[2]), @@ -9382,7 +9376,7 @@ module divider_cell_unq44 .I4_TO_LUT("FALSE")) \N20_1.fsub_3 ( .COUT (\N20_1.co [3] ), - .Z (_N19149), + .Z (_N19134), .CIN (\N20_1.co [2] ), .I0 (), .I1 (divisor[3]), @@ -9402,7 +9396,7 @@ module divider_cell_unq44 .I4_TO_LUT("FALSE")) \N20_1.fsub_4 ( .COUT (\N20_1.co [4] ), - .Z (_N19150), + .Z (_N19135), .CIN (\N20_1.co [3] ), .I0 (), .I1 (divisor[4]), @@ -9422,7 +9416,7 @@ module divider_cell_unq44 .I4_TO_LUT("FALSE")) \N20_1.fsub_5 ( .COUT (\N20_1.co [5] ), - .Z (_N19151), + .Z (_N19136), .CIN (\N20_1.co [4] ), .I0 (), .I1 (divisor[5]), @@ -9442,7 +9436,7 @@ module divider_cell_unq44 .I4_TO_LUT("FALSE")) \N20_1.fsub_6 ( .COUT (\N20_1.co [6] ), - .Z (_N19152), + .Z (_N19137), .CIN (\N20_1.co [5] ), .I0 (), .I1 (divisor[6]), @@ -9462,7 +9456,7 @@ module divider_cell_unq44 .I4_TO_LUT("FALSE")) \N20_1.fsub_7 ( .COUT (), - .Z (_N19153), + .Z (_N19138), .CIN (\N20_1.co [6] ), .I0 (), .I1 (divisor[7]), @@ -9477,7 +9471,7 @@ module divider_cell_unq44 GTP_LUT2 /* \N45_2[1] */ #( .INIT(4'b1000)) \N45_2[1] ( - .Z (N45_alias[1]), + .Z (N45[1]), .I0 (quotient_ci[0]), .I1 (en)); // LUT = I0&I1 ; @@ -9485,7 +9479,7 @@ module divider_cell_unq44 GTP_LUT2 /* \N45_2[2] */ #( .INIT(4'b1000)) \N45_2[2] ( - .Z (N45_alias[2]), + .Z (N45[2]), .I0 (quotient_ci[1]), .I1 (en)); // LUT = I0&I1 ; @@ -9493,7 +9487,7 @@ module divider_cell_unq44 GTP_LUT2 /* \N45_2[3] */ #( .INIT(4'b1000)) \N45_2[3] ( - .Z (N45_alias[3]), + .Z (N45[3]), .I0 (quotient_ci[2]), .I1 (en)); // LUT = I0&I1 ; @@ -9501,7 +9495,7 @@ module divider_cell_unq44 GTP_LUT2 /* \N45_2[4] */ #( .INIT(4'b1000)) \N45_2[4] ( - .Z (N45_alias[4]), + .Z (N45[4]), .I0 (quotient_ci[3]), .I1 (en)); // LUT = I0&I1 ; @@ -9509,7 +9503,7 @@ module divider_cell_unq44 GTP_LUT2 /* \N45_2[5] */ #( .INIT(4'b1000)) \N45_2[5] ( - .Z (N45_alias[5]), + .Z (N45[5]), .I0 (quotient_ci[4]), .I1 (en)); // LUT = I0&I1 ; @@ -9517,7 +9511,7 @@ module divider_cell_unq44 GTP_LUT2 /* \N45_2[6] */ #( .INIT(4'b1000)) \N45_2[6] ( - .Z (N45_alias[6]), + .Z (N45[6]), .I0 (quotient_ci[5]), .I1 (en)); // LUT = I0&I1 ; @@ -9534,9 +9528,9 @@ module divider_cell_unq44 GTP_LUT2 /* \N45_2[12]_1 */ #( .INIT(4'b0010)) \N45_2[12]_1 ( - .Z (\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45 [0] ), + .Z (N45[0]), .I0 (en), - .I1 (\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N6 )); + .I1 (N6)); // LUT = I0&~I1 ; GTP_LUT2 /* \N45_2[13] */ #( @@ -9544,7 +9538,7 @@ module divider_cell_unq44 \N45_2[13] ( .Z (N51[1]), .I0 (en), - .I1 (_N19147)); + .I1 (_N19132)); // LUT = I0&I1 ; GTP_LUT2 /* \N45_2[14] */ #( @@ -9552,7 +9546,7 @@ module divider_cell_unq44 \N45_2[14] ( .Z (N51[2]), .I0 (en), - .I1 (_N19148)); + .I1 (_N19133)); // LUT = I0&I1 ; GTP_LUT2 /* \N45_2[15] */ #( @@ -9560,7 +9554,7 @@ module divider_cell_unq44 \N45_2[15] ( .Z (N51[3]), .I0 (en), - .I1 (_N19149)); + .I1 (_N19134)); // LUT = I0&I1 ; GTP_LUT2 /* \N45_2[16] */ #( @@ -9568,7 +9562,7 @@ module divider_cell_unq44 \N45_2[16] ( .Z (N51[4]), .I0 (en), - .I1 (_N19150)); + .I1 (_N19135)); // LUT = I0&I1 ; GTP_LUT2 /* \N45_2[17] */ #( @@ -9576,7 +9570,7 @@ module divider_cell_unq44 \N45_2[17] ( .Z (N51[5]), .I0 (en), - .I1 (_N19151)); + .I1 (_N19136)); // LUT = I0&I1 ; GTP_LUT2 /* \N45_2[18] */ #( @@ -9584,7 +9578,7 @@ module divider_cell_unq44 \N45_2[18] ( .Z (N51[6]), .I0 (en), - .I1 (_N19152)); + .I1 (_N19137)); // LUT = I0&I1 ; GTP_LUT2 /* \N45_2[19] */ #( @@ -9592,7 +9586,7 @@ module divider_cell_unq44 \N45_2[19] ( .Z (N51[7]), .I0 (en), - .I1 (_N19153)); + .I1 (_N19138)); // LUT = I0&I1 ; GTP_LUT2 /* \N53[0]_1 */ #( @@ -9754,7 +9748,7 @@ module divider_cell_unq44 .Q (quotient[0]), .C (sync_vg_100m), .CLK (clk), - .D (N45_alias[0])); + .D (N45[0])); // ../../sources/designs/adjust_color/divider_cell.v:24 GTP_DFF_C /* \quotient[1] */ #( @@ -9764,7 +9758,7 @@ module divider_cell_unq44 .Q (quotient[1]), .C (sync_vg_100m), .CLK (clk), - .D (N45_alias[1])); + .D (N45[1])); // ../../sources/designs/adjust_color/divider_cell.v:24 GTP_DFF_C /* \quotient[2] */ #( @@ -9774,7 +9768,7 @@ module divider_cell_unq44 .Q (quotient[2]), .C (sync_vg_100m), .CLK (clk), - .D (N45_alias[2])); + .D (N45[2])); // ../../sources/designs/adjust_color/divider_cell.v:24 GTP_DFF_C /* \quotient[3] */ #( @@ -9784,7 +9778,7 @@ module divider_cell_unq44 .Q (quotient[3]), .C (sync_vg_100m), .CLK (clk), - .D (N45_alias[3])); + .D (N45[3])); // ../../sources/designs/adjust_color/divider_cell.v:24 GTP_DFF_C /* \quotient[4] */ #( @@ -9794,7 +9788,7 @@ module divider_cell_unq44 .Q (quotient[4]), .C (sync_vg_100m), .CLK (clk), - .D (N45_alias[4])); + .D (N45[4])); // ../../sources/designs/adjust_color/divider_cell.v:24 GTP_DFF_C /* \quotient[5] */ #( @@ -9804,7 +9798,7 @@ module divider_cell_unq44 .Q (quotient[5]), .C (sync_vg_100m), .CLK (clk), - .D (N45_alias[5])); + .D (N45[5])); // ../../sources/designs/adjust_color/divider_cell.v:24 GTP_DFF_C /* \quotient[6] */ #( @@ -9814,7 +9808,7 @@ module divider_cell_unq44 .Q (quotient[6]), .C (sync_vg_100m), .CLK (clk), - .D (N45_alias[6])); + .D (N45[6])); // ../../sources/designs/adjust_color/divider_cell.v:24 GTP_DFF_C /* rdy */ #( @@ -10193,12 +10187,12 @@ module divider_cell_unq48 wire [7:0] N53; wire [11:0] N54; wire [7:0] N61; - wire _N107245; + wire _N108070; GTP_LUT5 /* N6_mux7_7 */ #( .INIT(32'b11111111111111111111111111110100)) N6_mux7_7 ( - .Z (_N107245), + .Z (_N108070), .I0 (dividend[0]), .I1 (divisor[0]), .I2 (divisor[5]), @@ -10214,7 +10208,7 @@ module divider_cell_unq48 .I1 (divisor[2]), .I2 (divisor[3]), .I3 (divisor[4]), - .I4 (_N107245)); + .I4 (_N108070)); // LUT = (I0)|(I1)|(I2)|(I3)|(I4) ; GTP_LUT5CARRY /* \N20.fsub_0 */ #( @@ -10791,27 +10785,11 @@ module divider ( input [12:0] dividend, input [7:0] divisor, - input [12:0] \g_sqrt_stepx[8].u_divider_step/N45 , - input [12:0] \g_sqrt_stepx[9].u_divider_step/N45 , - input [12:0] \g_sqrt_stepx[10].u_divider_step/N45 , - input [12:0] \g_sqrt_stepx[11].u_divider_step/N45 , - input \adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N6 , - input \adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N6 , - input \adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N6 , - input \adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N6 , input clk, input in_valid, input sync_vg_100m, - output [15:0] \adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45 , - output [15:0] \adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45 , - output [15:0] \adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45 , - output [15:0] \adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45 , output [12:0] quotient, - output [12:0] rdy_t, - output \g_sqrt_stepx[8].u_divider_step/N6 , - output \g_sqrt_stepx[9].u_divider_step/N6 , - output \g_sqrt_stepx[10].u_divider_step/N6 , - output \g_sqrt_stepx[11].u_divider_step/N6 + output [12:0] rdy_t ); wire [11:0] \dividend_t[6] ; wire [11:0] \dividend_t[7] ; @@ -10935,21 +10913,6 @@ module divider wire \g_sqrt_stepx[7].u_divider_step_quotient[10]_floating ; wire \g_sqrt_stepx[7].u_divider_step_quotient[11]_floating ; wire \g_sqrt_stepx[7].u_divider_step_quotient[12]_floating ; - wire \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[1]_floating ; - wire \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[2]_floating ; - wire \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[3]_floating ; - wire \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[4]_floating ; - wire \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[5]_floating ; - wire \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[6]_floating ; - wire \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[7]_floating ; - wire \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[8]_floating ; - wire \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[9]_floating ; - wire \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[10]_floating ; - wire \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[11]_floating ; - wire \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[12]_floating ; - wire \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[13]_floating ; - wire \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[14]_floating ; - wire \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[15]_floating ; wire \g_sqrt_stepx[8].u_divider_step_quotient[4]_floating ; wire \g_sqrt_stepx[8].u_divider_step_quotient[5]_floating ; wire \g_sqrt_stepx[8].u_divider_step_quotient[6]_floating ; @@ -10959,21 +10922,6 @@ module divider wire \g_sqrt_stepx[8].u_divider_step_quotient[10]_floating ; wire \g_sqrt_stepx[8].u_divider_step_quotient[11]_floating ; wire \g_sqrt_stepx[8].u_divider_step_quotient[12]_floating ; - wire \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[1]_floating ; - wire \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[2]_floating ; - wire \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[3]_floating ; - wire \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[4]_floating ; - wire \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[5]_floating ; - wire \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[6]_floating ; - wire \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[7]_floating ; - wire \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[8]_floating ; - wire \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[9]_floating ; - wire \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[10]_floating ; - wire \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[11]_floating ; - wire \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[12]_floating ; - wire \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[13]_floating ; - wire \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[14]_floating ; - wire \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[15]_floating ; wire \g_sqrt_stepx[9].u_divider_step_quotient[5]_floating ; wire \g_sqrt_stepx[9].u_divider_step_quotient[6]_floating ; wire \g_sqrt_stepx[9].u_divider_step_quotient[7]_floating ; @@ -10982,21 +10930,6 @@ module divider wire \g_sqrt_stepx[9].u_divider_step_quotient[10]_floating ; wire \g_sqrt_stepx[9].u_divider_step_quotient[11]_floating ; wire \g_sqrt_stepx[9].u_divider_step_quotient[12]_floating ; - wire \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[1]_floating ; - wire \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[2]_floating ; - wire \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[3]_floating ; - wire \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[4]_floating ; - wire \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[5]_floating ; - wire \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[6]_floating ; - wire \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[7]_floating ; - wire \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[8]_floating ; - wire \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[9]_floating ; - wire \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[10]_floating ; - wire \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[11]_floating ; - wire \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[12]_floating ; - wire \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[13]_floating ; - wire \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[14]_floating ; - wire \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[15]_floating ; wire \g_sqrt_stepx[10].u_divider_step_quotient[6]_floating ; wire \g_sqrt_stepx[10].u_divider_step_quotient[7]_floating ; wire \g_sqrt_stepx[10].u_divider_step_quotient[8]_floating ; @@ -11004,21 +10937,6 @@ module divider wire \g_sqrt_stepx[10].u_divider_step_quotient[10]_floating ; wire \g_sqrt_stepx[10].u_divider_step_quotient[11]_floating ; wire \g_sqrt_stepx[10].u_divider_step_quotient[12]_floating ; - wire \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[1]_floating ; - wire \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[2]_floating ; - wire \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[3]_floating ; - wire \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[4]_floating ; - wire \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[5]_floating ; - wire \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[6]_floating ; - wire \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[7]_floating ; - wire \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[8]_floating ; - wire \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[9]_floating ; - wire \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[10]_floating ; - wire \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[11]_floating ; - wire \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[12]_floating ; - wire \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[13]_floating ; - wire \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[14]_floating ; - wire \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[15]_floating ; wire \g_sqrt_stepx[11].u_divider_step_quotient[7]_floating ; wire \g_sqrt_stepx[11].u_divider_step_quotient[8]_floating ; wire \g_sqrt_stepx[11].u_divider_step_quotient[9]_floating ; @@ -11131,68 +11049,52 @@ module divider // ../../sources/designs/adjust_color/divider.v:54 divider_cell_unq38 \g_sqrt_stepx[8].u_divider_step ( - .\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45 ({\g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[15]_floating , \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[14]_floating , \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[13]_floating , \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[12]_floating , \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[11]_floating , \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[10]_floating , \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[9]_floating , \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[8]_floating , \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[7]_floating , \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[6]_floating , \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[5]_floating , \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[4]_floating , \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[3]_floating , \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[2]_floating , \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[1]_floating , \adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45 [0] }), .divisor_kp ({\divisor_t[4] [7] , \divisor_t[4] [6] , \divisor_t[4] [5] , \divisor_t[4] [4] , \divisor_t[4] [3] , \divisor_t[4] [2] , \divisor_t[4] [1] , \divisor_t[4] [0] }), .quotient ({\g_sqrt_stepx[8].u_divider_step_quotient[12]_floating , \g_sqrt_stepx[8].u_divider_step_quotient[11]_floating , \g_sqrt_stepx[8].u_divider_step_quotient[10]_floating , \g_sqrt_stepx[8].u_divider_step_quotient[9]_floating , \g_sqrt_stepx[8].u_divider_step_quotient[8]_floating , \g_sqrt_stepx[8].u_divider_step_quotient[7]_floating , \g_sqrt_stepx[8].u_divider_step_quotient[6]_floating , \g_sqrt_stepx[8].u_divider_step_quotient[5]_floating , \g_sqrt_stepx[8].u_divider_step_quotient[4]_floating , \quotient_t[4] [3] , \quotient_t[4] [2] , \quotient_t[4] [1] , \quotient_t[4] [0] }), .remainder ({\remainder_t[4] [7] , \remainder_t[4] [6] , \remainder_t[4] [5] , \remainder_t[4] [4] , \remainder_t[4] [3] , \remainder_t[4] [2] , \remainder_t[4] [1] , \remainder_t[4] [0] }), - .N45 ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \g_sqrt_stepx[8].u_divider_step/N45 [0] }), .dividend ({\remainder_t[5] [7] , \remainder_t[5] [6] , \remainder_t[5] [5] , \remainder_t[5] [4] , \remainder_t[5] [3] , \remainder_t[5] [2] , \remainder_t[5] [1] , \remainder_t[5] [0] , 1'bx}), .divisor ({\divisor_t[5] [7] , \divisor_t[5] [6] , \divisor_t[5] [5] , \divisor_t[5] [4] , \divisor_t[5] [3] , \divisor_t[5] [2] , \divisor_t[5] [1] , \divisor_t[5] [0] }), .quotient_ci ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \quotient_t[5] [2] , \quotient_t[5] [1] , \quotient_t[5] [0] }), - .N6 (\g_sqrt_stepx[8].u_divider_step/N6 ), .rdy (rdy_t[4]), - .\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N6 (\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N6 ), .clk (clk), .en (rdy_t[5]), .sync_vg_100m (sync_vg_100m)); // ../../sources/designs/adjust_color/divider.v:54 divider_cell_unq40 \g_sqrt_stepx[9].u_divider_step ( - .\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45 ({\g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[15]_floating , \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[14]_floating , \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[13]_floating , \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[12]_floating , \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[11]_floating , \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[10]_floating , \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[9]_floating , \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[8]_floating , \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[7]_floating , \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[6]_floating , \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[5]_floating , \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[4]_floating , \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[3]_floating , \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[2]_floating , \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[1]_floating , \adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45 [0] }), .divisor_kp ({\divisor_t[3] [7] , \divisor_t[3] [6] , \divisor_t[3] [5] , \divisor_t[3] [4] , \divisor_t[3] [3] , \divisor_t[3] [2] , \divisor_t[3] [1] , \divisor_t[3] [0] }), .quotient ({\g_sqrt_stepx[9].u_divider_step_quotient[12]_floating , \g_sqrt_stepx[9].u_divider_step_quotient[11]_floating , \g_sqrt_stepx[9].u_divider_step_quotient[10]_floating , \g_sqrt_stepx[9].u_divider_step_quotient[9]_floating , \g_sqrt_stepx[9].u_divider_step_quotient[8]_floating , \g_sqrt_stepx[9].u_divider_step_quotient[7]_floating , \g_sqrt_stepx[9].u_divider_step_quotient[6]_floating , \g_sqrt_stepx[9].u_divider_step_quotient[5]_floating , \quotient_t[3] [4] , \quotient_t[3] [3] , \quotient_t[3] [2] , \quotient_t[3] [1] , \quotient_t[3] [0] }), .remainder ({\remainder_t[3] [7] , \remainder_t[3] [6] , \remainder_t[3] [5] , \remainder_t[3] [4] , \remainder_t[3] [3] , \remainder_t[3] [2] , \remainder_t[3] [1] , \remainder_t[3] [0] }), - .N45 ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \g_sqrt_stepx[9].u_divider_step/N45 [0] }), .dividend ({\remainder_t[4] [7] , \remainder_t[4] [6] , \remainder_t[4] [5] , \remainder_t[4] [4] , \remainder_t[4] [3] , \remainder_t[4] [2] , \remainder_t[4] [1] , \remainder_t[4] [0] , 1'bx}), .divisor ({\divisor_t[4] [7] , \divisor_t[4] [6] , \divisor_t[4] [5] , \divisor_t[4] [4] , \divisor_t[4] [3] , \divisor_t[4] [2] , \divisor_t[4] [1] , \divisor_t[4] [0] }), .quotient_ci ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \quotient_t[4] [3] , \quotient_t[4] [2] , \quotient_t[4] [1] , \quotient_t[4] [0] }), - .N6 (\g_sqrt_stepx[9].u_divider_step/N6 ), .rdy (rdy_t[3]), - .\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N6 (\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N6 ), .clk (clk), .en (rdy_t[4]), .sync_vg_100m (sync_vg_100m)); // ../../sources/designs/adjust_color/divider.v:54 divider_cell_unq42 \g_sqrt_stepx[10].u_divider_step ( - .\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45 ({\g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[15]_floating , \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[14]_floating , \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[13]_floating , \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[12]_floating , \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[11]_floating , \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[10]_floating , \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[9]_floating , \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[8]_floating , \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[7]_floating , \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[6]_floating , \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[5]_floating , \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[4]_floating , \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[3]_floating , \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[2]_floating , \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[1]_floating , \adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45 [0] }), .divisor_kp ({\divisor_t[2] [7] , \divisor_t[2] [6] , \divisor_t[2] [5] , \divisor_t[2] [4] , \divisor_t[2] [3] , \divisor_t[2] [2] , \divisor_t[2] [1] , \divisor_t[2] [0] }), .quotient ({\g_sqrt_stepx[10].u_divider_step_quotient[12]_floating , \g_sqrt_stepx[10].u_divider_step_quotient[11]_floating , \g_sqrt_stepx[10].u_divider_step_quotient[10]_floating , \g_sqrt_stepx[10].u_divider_step_quotient[9]_floating , \g_sqrt_stepx[10].u_divider_step_quotient[8]_floating , \g_sqrt_stepx[10].u_divider_step_quotient[7]_floating , \g_sqrt_stepx[10].u_divider_step_quotient[6]_floating , \quotient_t[2] [5] , \quotient_t[2] [4] , \quotient_t[2] [3] , \quotient_t[2] [2] , \quotient_t[2] [1] , \quotient_t[2] [0] }), .remainder ({\remainder_t[2] [7] , \remainder_t[2] [6] , \remainder_t[2] [5] , \remainder_t[2] [4] , \remainder_t[2] [3] , \remainder_t[2] [2] , \remainder_t[2] [1] , \remainder_t[2] [0] }), - .N45 ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \g_sqrt_stepx[10].u_divider_step/N45 [0] }), .dividend ({\remainder_t[3] [7] , \remainder_t[3] [6] , \remainder_t[3] [5] , \remainder_t[3] [4] , \remainder_t[3] [3] , \remainder_t[3] [2] , \remainder_t[3] [1] , \remainder_t[3] [0] , 1'bx}), .divisor ({\divisor_t[3] [7] , \divisor_t[3] [6] , \divisor_t[3] [5] , \divisor_t[3] [4] , \divisor_t[3] [3] , \divisor_t[3] [2] , \divisor_t[3] [1] , \divisor_t[3] [0] }), .quotient_ci ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \quotient_t[3] [4] , \quotient_t[3] [3] , \quotient_t[3] [2] , \quotient_t[3] [1] , \quotient_t[3] [0] }), - .N6 (\g_sqrt_stepx[10].u_divider_step/N6 ), .rdy (rdy_t[2]), - .\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N6 (\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N6 ), .clk (clk), .en (rdy_t[3]), .sync_vg_100m (sync_vg_100m)); // ../../sources/designs/adjust_color/divider.v:54 divider_cell_unq44 \g_sqrt_stepx[11].u_divider_step ( - .\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45 ({\g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[15]_floating , \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[14]_floating , \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[13]_floating , \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[12]_floating , \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[11]_floating , \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[10]_floating , \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[9]_floating , \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[8]_floating , \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[7]_floating , \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[6]_floating , \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[5]_floating , \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[4]_floating , \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[3]_floating , \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[2]_floating , \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[1]_floating , \adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45 [0] }), .divisor_kp ({\divisor_t[1] [7] , \divisor_t[1] [6] , \divisor_t[1] [5] , \divisor_t[1] [4] , \divisor_t[1] [3] , \divisor_t[1] [2] , \divisor_t[1] [1] , \divisor_t[1] [0] }), .quotient ({\g_sqrt_stepx[11].u_divider_step_quotient[12]_floating , \g_sqrt_stepx[11].u_divider_step_quotient[11]_floating , \g_sqrt_stepx[11].u_divider_step_quotient[10]_floating , \g_sqrt_stepx[11].u_divider_step_quotient[9]_floating , \g_sqrt_stepx[11].u_divider_step_quotient[8]_floating , \g_sqrt_stepx[11].u_divider_step_quotient[7]_floating , \quotient_t[1] [6] , \quotient_t[1] [5] , \quotient_t[1] [4] , \quotient_t[1] [3] , \quotient_t[1] [2] , \quotient_t[1] [1] , \quotient_t[1] [0] }), .remainder ({\remainder_t[1] [7] , \remainder_t[1] [6] , \remainder_t[1] [5] , \remainder_t[1] [4] , \remainder_t[1] [3] , \remainder_t[1] [2] , \remainder_t[1] [1] , \remainder_t[1] [0] }), - .N45 ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \g_sqrt_stepx[11].u_divider_step/N45 [0] }), .dividend ({\remainder_t[2] [7] , \remainder_t[2] [6] , \remainder_t[2] [5] , \remainder_t[2] [4] , \remainder_t[2] [3] , \remainder_t[2] [2] , \remainder_t[2] [1] , \remainder_t[2] [0] , 1'bx}), .divisor ({\divisor_t[2] [7] , \divisor_t[2] [6] , \divisor_t[2] [5] , \divisor_t[2] [4] , \divisor_t[2] [3] , \divisor_t[2] [2] , \divisor_t[2] [1] , \divisor_t[2] [0] }), .quotient_ci ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \quotient_t[2] [5] , \quotient_t[2] [4] , \quotient_t[2] [3] , \quotient_t[2] [2] , \quotient_t[2] [1] , \quotient_t[2] [0] }), - .N6 (\g_sqrt_stepx[11].u_divider_step/N6 ), .rdy (rdy_t[1]), - .\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N6 (\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N6 ), .clk (clk), .en (rdy_t[2]), .sync_vg_100m (sync_vg_100m)); @@ -11243,14 +11145,14 @@ module divider_cell_1 wire [7:0] N51; wire [7:0] N53; wire [14:0] N54; - wire _N19304; - wire _N19305; - wire _N19306; - wire _N19307; - wire _N19308; - wire _N19309; - wire _N19310; - wire _N19311; + wire _N19265; + wire _N19266; + wire _N19267; + wire _N19268; + wire _N19269; + wire _N19270; + wire _N19271; + wire _N19272; GTP_LUT5CARRY /* \N6.lt_0 */ #( .INIT(32'b00100000111100100000000000000000), @@ -11380,7 +11282,7 @@ module divider_cell_1 .I4_TO_LUT("FALSE")) \N20.fsub_1 ( .COUT (\N20.co [1] ), - .Z (_N19304), + .Z (_N19265), .CIN (\N20.co [0] ), .I0 (), .I1 (divisor[0]), @@ -11400,7 +11302,7 @@ module divider_cell_1 .I4_TO_LUT("FALSE")) \N20.fsub_2 ( .COUT (\N20.co [2] ), - .Z (_N19305), + .Z (_N19266), .CIN (\N20.co [1] ), .I0 (), .I1 (divisor[1]), @@ -11420,7 +11322,7 @@ module divider_cell_1 .I4_TO_LUT("FALSE")) \N20.fsub_3 ( .COUT (\N20.co [3] ), - .Z (_N19306), + .Z (_N19267), .CIN (\N20.co [2] ), .I0 (), .I1 (divisor[2]), @@ -11440,7 +11342,7 @@ module divider_cell_1 .I4_TO_LUT("FALSE")) \N20.fsub_4 ( .COUT (\N20.co [4] ), - .Z (_N19307), + .Z (_N19268), .CIN (\N20.co [3] ), .I0 (), .I1 (divisor[3]), @@ -11460,7 +11362,7 @@ module divider_cell_1 .I4_TO_LUT("FALSE")) \N20.fsub_5 ( .COUT (\N20.co [5] ), - .Z (_N19308), + .Z (_N19269), .CIN (\N20.co [4] ), .I0 (), .I1 (divisor[4]), @@ -11480,7 +11382,7 @@ module divider_cell_1 .I4_TO_LUT("FALSE")) \N20.fsub_6 ( .COUT (\N20.co [6] ), - .Z (_N19309), + .Z (_N19270), .CIN (\N20.co [5] ), .I0 (), .I1 (divisor[5]), @@ -11500,7 +11402,7 @@ module divider_cell_1 .I4_TO_LUT("FALSE")) \N20.fsub_7 ( .COUT (\N20.co [7] ), - .Z (_N19310), + .Z (_N19271), .CIN (\N20.co [6] ), .I0 (), .I1 (divisor[6]), @@ -11520,7 +11422,7 @@ module divider_cell_1 .I4_TO_LUT("FALSE")) \N20.fsub_8 ( .COUT (), - .Z (_N19311), + .Z (_N19272), .CIN (\N20.co [7] ), .I0 (), .I1 (divisor[7]), @@ -11537,7 +11439,7 @@ module divider_cell_1 \N51_2[0]_1 ( .Z (N51[0]), .I0 (en), - .I1 (_N19304)); + .I1 (_N19265)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[1]_1 */ #( @@ -11545,7 +11447,7 @@ module divider_cell_1 \N51_2[1]_1 ( .Z (N51[1]), .I0 (en), - .I1 (_N19305)); + .I1 (_N19266)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[2]_1 */ #( @@ -11553,7 +11455,7 @@ module divider_cell_1 \N51_2[2]_1 ( .Z (N51[2]), .I0 (en), - .I1 (_N19306)); + .I1 (_N19267)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[3]_1 */ #( @@ -11561,7 +11463,7 @@ module divider_cell_1 \N51_2[3]_1 ( .Z (N51[3]), .I0 (en), - .I1 (_N19307)); + .I1 (_N19268)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[4]_1 */ #( @@ -11569,7 +11471,7 @@ module divider_cell_1 \N51_2[4]_1 ( .Z (N51[4]), .I0 (en), - .I1 (_N19308)); + .I1 (_N19269)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[5]_1 */ #( @@ -11577,7 +11479,7 @@ module divider_cell_1 \N51_2[5]_1 ( .Z (N51[5]), .I0 (en), - .I1 (_N19309)); + .I1 (_N19270)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[6]_1 */ #( @@ -11585,7 +11487,7 @@ module divider_cell_1 \N51_2[6]_1 ( .Z (N51[6]), .I0 (en), - .I1 (_N19310)); + .I1 (_N19271)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[7]_1 */ #( @@ -11593,7 +11495,7 @@ module divider_cell_1 \N51_2[7]_1 ( .Z (N51[7]), .I0 (en), - .I1 (_N19311)); + .I1 (_N19272)); // LUT = I0&I1 ; GTP_LUT2 /* \N53[0]_1 */ #( @@ -11964,14 +11866,14 @@ module divider_cell_1_unq32 wire [7:0] N51; wire [7:0] N53; wire [14:0] N54; - wire _N19324; - wire _N19325; - wire _N19326; - wire _N19327; - wire _N19328; - wire _N19329; - wire _N19330; - wire _N19331; + wire _N19300; + wire _N19301; + wire _N19302; + wire _N19303; + wire _N19304; + wire _N19305; + wire _N19306; + wire _N19307; GTP_LUT5CARRY /* \N6.lt_0 */ #( .INIT(32'b00100000111100100000000000000000), @@ -12101,7 +12003,7 @@ module divider_cell_1_unq32 .I4_TO_LUT("FALSE")) \N20.fsub_1 ( .COUT (\N20.co [1] ), - .Z (_N19324), + .Z (_N19300), .CIN (\N20.co [0] ), .I0 (), .I1 (divisor[0]), @@ -12121,7 +12023,7 @@ module divider_cell_1_unq32 .I4_TO_LUT("FALSE")) \N20.fsub_2 ( .COUT (\N20.co [2] ), - .Z (_N19325), + .Z (_N19301), .CIN (\N20.co [1] ), .I0 (), .I1 (divisor[1]), @@ -12141,7 +12043,7 @@ module divider_cell_1_unq32 .I4_TO_LUT("FALSE")) \N20.fsub_3 ( .COUT (\N20.co [3] ), - .Z (_N19326), + .Z (_N19302), .CIN (\N20.co [2] ), .I0 (), .I1 (divisor[2]), @@ -12161,7 +12063,7 @@ module divider_cell_1_unq32 .I4_TO_LUT("FALSE")) \N20.fsub_4 ( .COUT (\N20.co [4] ), - .Z (_N19327), + .Z (_N19303), .CIN (\N20.co [3] ), .I0 (), .I1 (divisor[3]), @@ -12181,7 +12083,7 @@ module divider_cell_1_unq32 .I4_TO_LUT("FALSE")) \N20.fsub_5 ( .COUT (\N20.co [5] ), - .Z (_N19328), + .Z (_N19304), .CIN (\N20.co [4] ), .I0 (), .I1 (divisor[4]), @@ -12201,7 +12103,7 @@ module divider_cell_1_unq32 .I4_TO_LUT("FALSE")) \N20.fsub_6 ( .COUT (\N20.co [6] ), - .Z (_N19329), + .Z (_N19305), .CIN (\N20.co [5] ), .I0 (), .I1 (divisor[5]), @@ -12221,7 +12123,7 @@ module divider_cell_1_unq32 .I4_TO_LUT("FALSE")) \N20.fsub_7 ( .COUT (\N20.co [7] ), - .Z (_N19330), + .Z (_N19306), .CIN (\N20.co [6] ), .I0 (), .I1 (divisor[6]), @@ -12241,7 +12143,7 @@ module divider_cell_1_unq32 .I4_TO_LUT("FALSE")) \N20.fsub_8 ( .COUT (), - .Z (_N19331), + .Z (_N19307), .CIN (\N20.co [7] ), .I0 (), .I1 (divisor[7]), @@ -12258,7 +12160,7 @@ module divider_cell_1_unq32 \N51_2[0]_1 ( .Z (N51[0]), .I0 (en), - .I1 (_N19324)); + .I1 (_N19300)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[1]_1 */ #( @@ -12266,7 +12168,7 @@ module divider_cell_1_unq32 \N51_2[1]_1 ( .Z (N51[1]), .I0 (en), - .I1 (_N19325)); + .I1 (_N19301)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[2]_1 */ #( @@ -12274,7 +12176,7 @@ module divider_cell_1_unq32 \N51_2[2]_1 ( .Z (N51[2]), .I0 (en), - .I1 (_N19326)); + .I1 (_N19302)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[3]_1 */ #( @@ -12282,7 +12184,7 @@ module divider_cell_1_unq32 \N51_2[3]_1 ( .Z (N51[3]), .I0 (en), - .I1 (_N19327)); + .I1 (_N19303)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[4]_1 */ #( @@ -12290,7 +12192,7 @@ module divider_cell_1_unq32 \N51_2[4]_1 ( .Z (N51[4]), .I0 (en), - .I1 (_N19328)); + .I1 (_N19304)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[5]_1 */ #( @@ -12298,7 +12200,7 @@ module divider_cell_1_unq32 \N51_2[5]_1 ( .Z (N51[5]), .I0 (en), - .I1 (_N19329)); + .I1 (_N19305)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[6]_1 */ #( @@ -12306,7 +12208,7 @@ module divider_cell_1_unq32 \N51_2[6]_1 ( .Z (N51[6]), .I0 (en), - .I1 (_N19330)); + .I1 (_N19306)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[7]_1 */ #( @@ -12314,7 +12216,7 @@ module divider_cell_1_unq32 \N51_2[7]_1 ( .Z (N51[7]), .I0 (en), - .I1 (_N19331)); + .I1 (_N19307)); // LUT = I0&I1 ; GTP_LUT2 /* \N53[0]_1 */ #( @@ -12666,14 +12568,14 @@ module divider_cell_1_unq34 wire [7:0] N51; wire [7:0] N53; wire [14:0] N54; - wire _N19346; - wire _N19347; - wire _N19348; - wire _N19349; - wire _N19350; - wire _N19351; - wire _N19352; - wire _N19353; + wire _N19322; + wire _N19323; + wire _N19324; + wire _N19325; + wire _N19326; + wire _N19327; + wire _N19328; + wire _N19329; GTP_LUT5CARRY /* \N6.lt_0 */ #( .INIT(32'b00100000111100100000000000000000), @@ -12803,7 +12705,7 @@ module divider_cell_1_unq34 .I4_TO_LUT("FALSE")) \N20.fsub_1 ( .COUT (\N20.co [1] ), - .Z (_N19346), + .Z (_N19322), .CIN (\N20.co [0] ), .I0 (), .I1 (divisor[0]), @@ -12823,7 +12725,7 @@ module divider_cell_1_unq34 .I4_TO_LUT("FALSE")) \N20.fsub_2 ( .COUT (\N20.co [2] ), - .Z (_N19347), + .Z (_N19323), .CIN (\N20.co [1] ), .I0 (), .I1 (divisor[1]), @@ -12843,7 +12745,7 @@ module divider_cell_1_unq34 .I4_TO_LUT("FALSE")) \N20.fsub_3 ( .COUT (\N20.co [3] ), - .Z (_N19348), + .Z (_N19324), .CIN (\N20.co [2] ), .I0 (), .I1 (divisor[2]), @@ -12863,7 +12765,7 @@ module divider_cell_1_unq34 .I4_TO_LUT("FALSE")) \N20.fsub_4 ( .COUT (\N20.co [4] ), - .Z (_N19349), + .Z (_N19325), .CIN (\N20.co [3] ), .I0 (), .I1 (divisor[3]), @@ -12883,7 +12785,7 @@ module divider_cell_1_unq34 .I4_TO_LUT("FALSE")) \N20.fsub_5 ( .COUT (\N20.co [5] ), - .Z (_N19350), + .Z (_N19326), .CIN (\N20.co [4] ), .I0 (), .I1 (divisor[4]), @@ -12903,7 +12805,7 @@ module divider_cell_1_unq34 .I4_TO_LUT("FALSE")) \N20.fsub_6 ( .COUT (\N20.co [6] ), - .Z (_N19351), + .Z (_N19327), .CIN (\N20.co [5] ), .I0 (), .I1 (divisor[5]), @@ -12923,7 +12825,7 @@ module divider_cell_1_unq34 .I4_TO_LUT("FALSE")) \N20.fsub_7 ( .COUT (\N20.co [7] ), - .Z (_N19352), + .Z (_N19328), .CIN (\N20.co [6] ), .I0 (), .I1 (divisor[6]), @@ -12943,7 +12845,7 @@ module divider_cell_1_unq34 .I4_TO_LUT("FALSE")) \N20.fsub_8 ( .COUT (), - .Z (_N19353), + .Z (_N19329), .CIN (\N20.co [7] ), .I0 (), .I1 (divisor[7]), @@ -12960,7 +12862,7 @@ module divider_cell_1_unq34 \N51_2[0]_1 ( .Z (N51[0]), .I0 (en), - .I1 (_N19346)); + .I1 (_N19322)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[1]_1 */ #( @@ -12968,7 +12870,7 @@ module divider_cell_1_unq34 \N51_2[1]_1 ( .Z (N51[1]), .I0 (en), - .I1 (_N19347)); + .I1 (_N19323)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[2]_1 */ #( @@ -12976,7 +12878,7 @@ module divider_cell_1_unq34 \N51_2[2]_1 ( .Z (N51[2]), .I0 (en), - .I1 (_N19348)); + .I1 (_N19324)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[3]_1 */ #( @@ -12984,7 +12886,7 @@ module divider_cell_1_unq34 \N51_2[3]_1 ( .Z (N51[3]), .I0 (en), - .I1 (_N19349)); + .I1 (_N19325)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[4]_1 */ #( @@ -12992,7 +12894,7 @@ module divider_cell_1_unq34 \N51_2[4]_1 ( .Z (N51[4]), .I0 (en), - .I1 (_N19350)); + .I1 (_N19326)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[5]_1 */ #( @@ -13000,7 +12902,7 @@ module divider_cell_1_unq34 \N51_2[5]_1 ( .Z (N51[5]), .I0 (en), - .I1 (_N19351)); + .I1 (_N19327)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[6]_1 */ #( @@ -13008,7 +12910,7 @@ module divider_cell_1_unq34 \N51_2[6]_1 ( .Z (N51[6]), .I0 (en), - .I1 (_N19352)); + .I1 (_N19328)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[7]_1 */ #( @@ -13016,7 +12918,7 @@ module divider_cell_1_unq34 \N51_2[7]_1 ( .Z (N51[7]), .I0 (en), - .I1 (_N19353)); + .I1 (_N19329)); // LUT = I0&I1 ; GTP_LUT2 /* \N53[0]_1 */ #( @@ -13349,14 +13251,14 @@ module divider_cell_1_unq36 wire [7:0] N51; wire [7:0] N53; wire [14:0] N54; - wire _N19370; - wire _N19371; - wire _N19372; - wire _N19373; - wire _N19374; - wire _N19375; - wire _N19376; - wire _N19377; + wire _N19346; + wire _N19347; + wire _N19348; + wire _N19349; + wire _N19350; + wire _N19351; + wire _N19352; + wire _N19353; GTP_LUT5CARRY /* \N6.lt_0 */ #( .INIT(32'b00100000111100100000000000000000), @@ -13486,7 +13388,7 @@ module divider_cell_1_unq36 .I4_TO_LUT("FALSE")) \N20.fsub_1 ( .COUT (\N20.co [1] ), - .Z (_N19370), + .Z (_N19346), .CIN (\N20.co [0] ), .I0 (), .I1 (divisor[0]), @@ -13506,7 +13408,7 @@ module divider_cell_1_unq36 .I4_TO_LUT("FALSE")) \N20.fsub_2 ( .COUT (\N20.co [2] ), - .Z (_N19371), + .Z (_N19347), .CIN (\N20.co [1] ), .I0 (), .I1 (divisor[1]), @@ -13526,7 +13428,7 @@ module divider_cell_1_unq36 .I4_TO_LUT("FALSE")) \N20.fsub_3 ( .COUT (\N20.co [3] ), - .Z (_N19372), + .Z (_N19348), .CIN (\N20.co [2] ), .I0 (), .I1 (divisor[2]), @@ -13546,7 +13448,7 @@ module divider_cell_1_unq36 .I4_TO_LUT("FALSE")) \N20.fsub_4 ( .COUT (\N20.co [4] ), - .Z (_N19373), + .Z (_N19349), .CIN (\N20.co [3] ), .I0 (), .I1 (divisor[3]), @@ -13566,7 +13468,7 @@ module divider_cell_1_unq36 .I4_TO_LUT("FALSE")) \N20.fsub_5 ( .COUT (\N20.co [5] ), - .Z (_N19374), + .Z (_N19350), .CIN (\N20.co [4] ), .I0 (), .I1 (divisor[4]), @@ -13586,7 +13488,7 @@ module divider_cell_1_unq36 .I4_TO_LUT("FALSE")) \N20.fsub_6 ( .COUT (\N20.co [6] ), - .Z (_N19375), + .Z (_N19351), .CIN (\N20.co [5] ), .I0 (), .I1 (divisor[5]), @@ -13606,7 +13508,7 @@ module divider_cell_1_unq36 .I4_TO_LUT("FALSE")) \N20.fsub_7 ( .COUT (\N20.co [7] ), - .Z (_N19376), + .Z (_N19352), .CIN (\N20.co [6] ), .I0 (), .I1 (divisor[6]), @@ -13626,7 +13528,7 @@ module divider_cell_1_unq36 .I4_TO_LUT("FALSE")) \N20.fsub_8 ( .COUT (), - .Z (_N19377), + .Z (_N19353), .CIN (\N20.co [7] ), .I0 (), .I1 (divisor[7]), @@ -13643,7 +13545,7 @@ module divider_cell_1_unq36 \N51_2[0]_1 ( .Z (N51[0]), .I0 (en), - .I1 (_N19370)); + .I1 (_N19346)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[1]_1 */ #( @@ -13651,7 +13553,7 @@ module divider_cell_1_unq36 \N51_2[1]_1 ( .Z (N51[1]), .I0 (en), - .I1 (_N19371)); + .I1 (_N19347)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[2]_1 */ #( @@ -13659,7 +13561,7 @@ module divider_cell_1_unq36 \N51_2[2]_1 ( .Z (N51[2]), .I0 (en), - .I1 (_N19372)); + .I1 (_N19348)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[3]_1 */ #( @@ -13667,7 +13569,7 @@ module divider_cell_1_unq36 \N51_2[3]_1 ( .Z (N51[3]), .I0 (en), - .I1 (_N19373)); + .I1 (_N19349)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[4]_1 */ #( @@ -13675,7 +13577,7 @@ module divider_cell_1_unq36 \N51_2[4]_1 ( .Z (N51[4]), .I0 (en), - .I1 (_N19374)); + .I1 (_N19350)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[5]_1 */ #( @@ -13683,7 +13585,7 @@ module divider_cell_1_unq36 \N51_2[5]_1 ( .Z (N51[5]), .I0 (en), - .I1 (_N19375)); + .I1 (_N19351)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[6]_1 */ #( @@ -13691,7 +13593,7 @@ module divider_cell_1_unq36 \N51_2[6]_1 ( .Z (N51[6]), .I0 (en), - .I1 (_N19376)); + .I1 (_N19352)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[7]_1 */ #( @@ -13699,7 +13601,7 @@ module divider_cell_1_unq36 \N51_2[7]_1 ( .Z (N51[7]), .I0 (en), - .I1 (_N19377)); + .I1 (_N19353)); // LUT = I0&I1 ; GTP_LUT2 /* \N53[0]_1 */ #( @@ -14013,14 +13915,14 @@ module divider_cell_1_unq38 wire [7:0] N51; wire [7:0] N53; wire [14:0] N54; - wire _N19396; - wire _N19397; - wire _N19398; - wire _N19399; - wire _N19400; - wire _N19401; - wire _N19402; - wire _N19403; + wire _N19372; + wire _N19373; + wire _N19374; + wire _N19375; + wire _N19376; + wire _N19377; + wire _N19378; + wire _N19379; GTP_LUT5CARRY /* \N6.lt_0 */ #( .INIT(32'b00100000111100100000000000000000), @@ -14150,7 +14052,7 @@ module divider_cell_1_unq38 .I4_TO_LUT("FALSE")) \N20.fsub_1 ( .COUT (\N20.co [1] ), - .Z (_N19396), + .Z (_N19372), .CIN (\N20.co [0] ), .I0 (), .I1 (divisor[0]), @@ -14170,7 +14072,7 @@ module divider_cell_1_unq38 .I4_TO_LUT("FALSE")) \N20.fsub_2 ( .COUT (\N20.co [2] ), - .Z (_N19397), + .Z (_N19373), .CIN (\N20.co [1] ), .I0 (), .I1 (divisor[1]), @@ -14190,7 +14092,7 @@ module divider_cell_1_unq38 .I4_TO_LUT("FALSE")) \N20.fsub_3 ( .COUT (\N20.co [3] ), - .Z (_N19398), + .Z (_N19374), .CIN (\N20.co [2] ), .I0 (), .I1 (divisor[2]), @@ -14210,7 +14112,7 @@ module divider_cell_1_unq38 .I4_TO_LUT("FALSE")) \N20.fsub_4 ( .COUT (\N20.co [4] ), - .Z (_N19399), + .Z (_N19375), .CIN (\N20.co [3] ), .I0 (), .I1 (divisor[3]), @@ -14230,7 +14132,7 @@ module divider_cell_1_unq38 .I4_TO_LUT("FALSE")) \N20.fsub_5 ( .COUT (\N20.co [5] ), - .Z (_N19400), + .Z (_N19376), .CIN (\N20.co [4] ), .I0 (), .I1 (divisor[4]), @@ -14250,7 +14152,7 @@ module divider_cell_1_unq38 .I4_TO_LUT("FALSE")) \N20.fsub_6 ( .COUT (\N20.co [6] ), - .Z (_N19401), + .Z (_N19377), .CIN (\N20.co [5] ), .I0 (), .I1 (divisor[5]), @@ -14270,7 +14172,7 @@ module divider_cell_1_unq38 .I4_TO_LUT("FALSE")) \N20.fsub_7 ( .COUT (\N20.co [7] ), - .Z (_N19402), + .Z (_N19378), .CIN (\N20.co [6] ), .I0 (), .I1 (divisor[6]), @@ -14290,7 +14192,7 @@ module divider_cell_1_unq38 .I4_TO_LUT("FALSE")) \N20.fsub_8 ( .COUT (), - .Z (_N19403), + .Z (_N19379), .CIN (\N20.co [7] ), .I0 (), .I1 (divisor[7]), @@ -14307,7 +14209,7 @@ module divider_cell_1_unq38 \N51_2[0]_1 ( .Z (N51[0]), .I0 (en), - .I1 (_N19396)); + .I1 (_N19372)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[1]_1 */ #( @@ -14315,7 +14217,7 @@ module divider_cell_1_unq38 \N51_2[1]_1 ( .Z (N51[1]), .I0 (en), - .I1 (_N19397)); + .I1 (_N19373)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[2]_1 */ #( @@ -14323,7 +14225,7 @@ module divider_cell_1_unq38 \N51_2[2]_1 ( .Z (N51[2]), .I0 (en), - .I1 (_N19398)); + .I1 (_N19374)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[3]_1 */ #( @@ -14331,7 +14233,7 @@ module divider_cell_1_unq38 \N51_2[3]_1 ( .Z (N51[3]), .I0 (en), - .I1 (_N19399)); + .I1 (_N19375)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[4]_1 */ #( @@ -14339,7 +14241,7 @@ module divider_cell_1_unq38 \N51_2[4]_1 ( .Z (N51[4]), .I0 (en), - .I1 (_N19400)); + .I1 (_N19376)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[5]_1 */ #( @@ -14347,7 +14249,7 @@ module divider_cell_1_unq38 \N51_2[5]_1 ( .Z (N51[5]), .I0 (en), - .I1 (_N19401)); + .I1 (_N19377)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[6]_1 */ #( @@ -14355,7 +14257,7 @@ module divider_cell_1_unq38 \N51_2[6]_1 ( .Z (N51[6]), .I0 (en), - .I1 (_N19402)); + .I1 (_N19378)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[7]_1 */ #( @@ -14363,7 +14265,7 @@ module divider_cell_1_unq38 \N51_2[7]_1 ( .Z (N51[7]), .I0 (en), - .I1 (_N19403)); + .I1 (_N19379)); // LUT = I0&I1 ; GTP_LUT2 /* \N53[0]_1 */ #( @@ -14658,14 +14560,14 @@ module divider_cell_1_unq40 wire [7:0] N51; wire [7:0] N53; wire [14:0] N54; - wire _N19424; - wire _N19425; - wire _N19426; - wire _N19427; - wire _N19428; - wire _N19429; - wire _N19430; - wire _N19431; + wire _N19400; + wire _N19401; + wire _N19402; + wire _N19403; + wire _N19404; + wire _N19405; + wire _N19406; + wire _N19407; GTP_LUT5CARRY /* \N6.lt_0 */ #( .INIT(32'b00100000111100100000000000000000), @@ -14795,7 +14697,7 @@ module divider_cell_1_unq40 .I4_TO_LUT("FALSE")) \N20.fsub_1 ( .COUT (\N20.co [1] ), - .Z (_N19424), + .Z (_N19400), .CIN (\N20.co [0] ), .I0 (), .I1 (divisor[0]), @@ -14815,7 +14717,7 @@ module divider_cell_1_unq40 .I4_TO_LUT("FALSE")) \N20.fsub_2 ( .COUT (\N20.co [2] ), - .Z (_N19425), + .Z (_N19401), .CIN (\N20.co [1] ), .I0 (), .I1 (divisor[1]), @@ -14835,7 +14737,7 @@ module divider_cell_1_unq40 .I4_TO_LUT("FALSE")) \N20.fsub_3 ( .COUT (\N20.co [3] ), - .Z (_N19426), + .Z (_N19402), .CIN (\N20.co [2] ), .I0 (), .I1 (divisor[2]), @@ -14855,7 +14757,7 @@ module divider_cell_1_unq40 .I4_TO_LUT("FALSE")) \N20.fsub_4 ( .COUT (\N20.co [4] ), - .Z (_N19427), + .Z (_N19403), .CIN (\N20.co [3] ), .I0 (), .I1 (divisor[3]), @@ -14875,7 +14777,7 @@ module divider_cell_1_unq40 .I4_TO_LUT("FALSE")) \N20.fsub_5 ( .COUT (\N20.co [5] ), - .Z (_N19428), + .Z (_N19404), .CIN (\N20.co [4] ), .I0 (), .I1 (divisor[4]), @@ -14895,7 +14797,7 @@ module divider_cell_1_unq40 .I4_TO_LUT("FALSE")) \N20.fsub_6 ( .COUT (\N20.co [6] ), - .Z (_N19429), + .Z (_N19405), .CIN (\N20.co [5] ), .I0 (), .I1 (divisor[5]), @@ -14915,7 +14817,7 @@ module divider_cell_1_unq40 .I4_TO_LUT("FALSE")) \N20.fsub_7 ( .COUT (\N20.co [7] ), - .Z (_N19430), + .Z (_N19406), .CIN (\N20.co [6] ), .I0 (), .I1 (divisor[6]), @@ -14935,7 +14837,7 @@ module divider_cell_1_unq40 .I4_TO_LUT("FALSE")) \N20.fsub_8 ( .COUT (), - .Z (_N19431), + .Z (_N19407), .CIN (\N20.co [7] ), .I0 (), .I1 (divisor[7]), @@ -14952,7 +14854,7 @@ module divider_cell_1_unq40 \N51_2[0]_1 ( .Z (N51[0]), .I0 (en), - .I1 (_N19424)); + .I1 (_N19400)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[1]_1 */ #( @@ -14960,7 +14862,7 @@ module divider_cell_1_unq40 \N51_2[1]_1 ( .Z (N51[1]), .I0 (en), - .I1 (_N19425)); + .I1 (_N19401)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[2]_1 */ #( @@ -14968,7 +14870,7 @@ module divider_cell_1_unq40 \N51_2[2]_1 ( .Z (N51[2]), .I0 (en), - .I1 (_N19426)); + .I1 (_N19402)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[3]_1 */ #( @@ -14976,7 +14878,7 @@ module divider_cell_1_unq40 \N51_2[3]_1 ( .Z (N51[3]), .I0 (en), - .I1 (_N19427)); + .I1 (_N19403)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[4]_1 */ #( @@ -14984,7 +14886,7 @@ module divider_cell_1_unq40 \N51_2[4]_1 ( .Z (N51[4]), .I0 (en), - .I1 (_N19428)); + .I1 (_N19404)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[5]_1 */ #( @@ -14992,7 +14894,7 @@ module divider_cell_1_unq40 \N51_2[5]_1 ( .Z (N51[5]), .I0 (en), - .I1 (_N19429)); + .I1 (_N19405)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[6]_1 */ #( @@ -15000,7 +14902,7 @@ module divider_cell_1_unq40 \N51_2[6]_1 ( .Z (N51[6]), .I0 (en), - .I1 (_N19430)); + .I1 (_N19406)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[7]_1 */ #( @@ -15008,7 +14910,7 @@ module divider_cell_1_unq40 \N51_2[7]_1 ( .Z (N51[7]), .I0 (en), - .I1 (_N19431)); + .I1 (_N19407)); // LUT = I0&I1 ; GTP_LUT2 /* \N53[0]_1 */ #( @@ -15283,14 +15185,14 @@ module divider_cell_1_unq42 wire [15:0] N45; wire [7:0] N51; wire [7:0] N53; - wire _N19483; - wire _N19484; - wire _N19485; - wire _N19486; - wire _N19487; - wire _N19488; - wire _N19489; - wire _N19490; + wire _N19430; + wire _N19431; + wire _N19432; + wire _N19433; + wire _N19434; + wire _N19435; + wire _N19436; + wire _N19437; GTP_LUT5CARRY /* \N6.lt_0 */ #( .INIT(32'b00100000111100100000000000000000), @@ -15420,7 +15322,7 @@ module divider_cell_1_unq42 .I4_TO_LUT("FALSE")) \N20.fsub_1 ( .COUT (\N20.co [1] ), - .Z (_N19483), + .Z (_N19430), .CIN (\N20.co [0] ), .I0 (), .I1 (divisor[0]), @@ -15440,7 +15342,7 @@ module divider_cell_1_unq42 .I4_TO_LUT("FALSE")) \N20.fsub_2 ( .COUT (\N20.co [2] ), - .Z (_N19484), + .Z (_N19431), .CIN (\N20.co [1] ), .I0 (), .I1 (divisor[1]), @@ -15460,7 +15362,7 @@ module divider_cell_1_unq42 .I4_TO_LUT("FALSE")) \N20.fsub_3 ( .COUT (\N20.co [3] ), - .Z (_N19485), + .Z (_N19432), .CIN (\N20.co [2] ), .I0 (), .I1 (divisor[2]), @@ -15480,7 +15382,7 @@ module divider_cell_1_unq42 .I4_TO_LUT("FALSE")) \N20.fsub_4 ( .COUT (\N20.co [4] ), - .Z (_N19486), + .Z (_N19433), .CIN (\N20.co [3] ), .I0 (), .I1 (divisor[3]), @@ -15500,7 +15402,7 @@ module divider_cell_1_unq42 .I4_TO_LUT("FALSE")) \N20.fsub_5 ( .COUT (\N20.co [5] ), - .Z (_N19487), + .Z (_N19434), .CIN (\N20.co [4] ), .I0 (), .I1 (divisor[4]), @@ -15520,7 +15422,7 @@ module divider_cell_1_unq42 .I4_TO_LUT("FALSE")) \N20.fsub_6 ( .COUT (\N20.co [6] ), - .Z (_N19488), + .Z (_N19435), .CIN (\N20.co [5] ), .I0 (), .I1 (divisor[5]), @@ -15540,7 +15442,7 @@ module divider_cell_1_unq42 .I4_TO_LUT("FALSE")) \N20.fsub_7 ( .COUT (\N20.co [7] ), - .Z (_N19489), + .Z (_N19436), .CIN (\N20.co [6] ), .I0 (), .I1 (divisor[6]), @@ -15560,7 +15462,7 @@ module divider_cell_1_unq42 .I4_TO_LUT("FALSE")) \N20.fsub_8 ( .COUT (), - .Z (_N19490), + .Z (_N19437), .CIN (\N20.co [7] ), .I0 (), .I1 (divisor[7]), @@ -15577,7 +15479,7 @@ module divider_cell_1_unq42 \N51_2[0]_1 ( .Z (N51[0]), .I0 (en), - .I1 (_N19483)); + .I1 (_N19430)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[1]_1 */ #( @@ -15585,7 +15487,7 @@ module divider_cell_1_unq42 \N51_2[1]_1 ( .Z (N51[1]), .I0 (en), - .I1 (_N19484)); + .I1 (_N19431)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[2]_1 */ #( @@ -15593,7 +15495,7 @@ module divider_cell_1_unq42 \N51_2[2]_1 ( .Z (N51[2]), .I0 (en), - .I1 (_N19485)); + .I1 (_N19432)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[3]_1 */ #( @@ -15601,7 +15503,7 @@ module divider_cell_1_unq42 \N51_2[3]_1 ( .Z (N51[3]), .I0 (en), - .I1 (_N19486)); + .I1 (_N19433)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[4]_1 */ #( @@ -15609,7 +15511,7 @@ module divider_cell_1_unq42 \N51_2[4]_1 ( .Z (N51[4]), .I0 (en), - .I1 (_N19487)); + .I1 (_N19434)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[5]_1 */ #( @@ -15617,7 +15519,7 @@ module divider_cell_1_unq42 \N51_2[5]_1 ( .Z (N51[5]), .I0 (en), - .I1 (_N19488)); + .I1 (_N19435)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[6]_1 */ #( @@ -15625,7 +15527,7 @@ module divider_cell_1_unq42 \N51_2[6]_1 ( .Z (N51[6]), .I0 (en), - .I1 (_N19489)); + .I1 (_N19436)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[7]_1 */ #( @@ -15633,7 +15535,7 @@ module divider_cell_1_unq42 \N51_2[7]_1 ( .Z (N51[7]), .I0 (en), - .I1 (_N19490)); + .I1 (_N19437)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[8] */ #( @@ -15892,33 +15794,29 @@ endmodule module divider_cell_1_unq44 ( - input [15:0] N45, input [8:0] dividend, input [7:0] divisor, input [15:0] quotient_ci, - input \adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N6 , input clk, input en, input sync_vg_100m, - output [12:0] \adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45 , output [7:0] divisor_kp, output [15:0] quotient, - output [7:0] remainder, - output N6 + output [7:0] remainder ); + wire N6; wire [9:0] \N6.co ; wire [7:0] \N20_1.co ; - wire [15:0] N45_alias; + wire [15:0] N45; wire [7:0] N51; wire [7:0] N53; - wire _N19516; - wire _N19517; - wire _N19518; - wire _N19519; - wire _N19520; - wire _N19521; - wire _N19522; - assign N45_alias[0] = N45[0]; + wire _N19463; + wire _N19464; + wire _N19465; + wire _N19466; + wire _N19467; + wire _N19468; + wire _N19469; GTP_LUT5CARRY /* \N6.lt_0 */ #( .INIT(32'b10001110100011100000000000000000), @@ -16048,7 +15946,7 @@ module divider_cell_1_unq44 .I4_TO_LUT("FALSE")) \N20_1.fsub_1 ( .COUT (\N20_1.co [1] ), - .Z (_N19516), + .Z (_N19463), .CIN (\N20_1.co [0] ), .I0 (), .I1 (divisor[1]), @@ -16068,7 +15966,7 @@ module divider_cell_1_unq44 .I4_TO_LUT("FALSE")) \N20_1.fsub_2 ( .COUT (\N20_1.co [2] ), - .Z (_N19517), + .Z (_N19464), .CIN (\N20_1.co [1] ), .I0 (), .I1 (divisor[2]), @@ -16088,7 +15986,7 @@ module divider_cell_1_unq44 .I4_TO_LUT("FALSE")) \N20_1.fsub_3 ( .COUT (\N20_1.co [3] ), - .Z (_N19518), + .Z (_N19465), .CIN (\N20_1.co [2] ), .I0 (), .I1 (divisor[3]), @@ -16108,7 +16006,7 @@ module divider_cell_1_unq44 .I4_TO_LUT("FALSE")) \N20_1.fsub_4 ( .COUT (\N20_1.co [4] ), - .Z (_N19519), + .Z (_N19466), .CIN (\N20_1.co [3] ), .I0 (), .I1 (divisor[4]), @@ -16128,7 +16026,7 @@ module divider_cell_1_unq44 .I4_TO_LUT("FALSE")) \N20_1.fsub_5 ( .COUT (\N20_1.co [5] ), - .Z (_N19520), + .Z (_N19467), .CIN (\N20_1.co [4] ), .I0 (), .I1 (divisor[5]), @@ -16148,7 +16046,7 @@ module divider_cell_1_unq44 .I4_TO_LUT("FALSE")) \N20_1.fsub_6 ( .COUT (\N20_1.co [6] ), - .Z (_N19521), + .Z (_N19468), .CIN (\N20_1.co [5] ), .I0 (), .I1 (divisor[6]), @@ -16168,7 +16066,7 @@ module divider_cell_1_unq44 .I4_TO_LUT("FALSE")) \N20_1.fsub_7 ( .COUT (), - .Z (_N19522), + .Z (_N19469), .CIN (\N20_1.co [6] ), .I0 (), .I1 (divisor[7]), @@ -16192,9 +16090,9 @@ module divider_cell_1_unq44 GTP_LUT2 /* \N51_2[0]_1 */ #( .INIT(4'b0010)) \N51_2[0]_1 ( - .Z (\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45 [0] ), + .Z (N45[0]), .I0 (en), - .I1 (\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N6 )); + .I1 (N6)); // LUT = I0&~I1 ; GTP_LUT2 /* \N51_2[1] */ #( @@ -16202,7 +16100,7 @@ module divider_cell_1_unq44 \N51_2[1] ( .Z (N51[1]), .I0 (en), - .I1 (_N19516)); + .I1 (_N19463)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[2] */ #( @@ -16210,7 +16108,7 @@ module divider_cell_1_unq44 \N51_2[2] ( .Z (N51[2]), .I0 (en), - .I1 (_N19517)); + .I1 (_N19464)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[3] */ #( @@ -16218,7 +16116,7 @@ module divider_cell_1_unq44 \N51_2[3] ( .Z (N51[3]), .I0 (en), - .I1 (_N19518)); + .I1 (_N19465)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[4] */ #( @@ -16226,7 +16124,7 @@ module divider_cell_1_unq44 \N51_2[4] ( .Z (N51[4]), .I0 (en), - .I1 (_N19519)); + .I1 (_N19466)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[5] */ #( @@ -16234,7 +16132,7 @@ module divider_cell_1_unq44 \N51_2[5] ( .Z (N51[5]), .I0 (en), - .I1 (_N19520)); + .I1 (_N19467)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[6] */ #( @@ -16242,7 +16140,7 @@ module divider_cell_1_unq44 \N51_2[6] ( .Z (N51[6]), .I0 (en), - .I1 (_N19521)); + .I1 (_N19468)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[7] */ #( @@ -16250,13 +16148,13 @@ module divider_cell_1_unq44 \N51_2[7] ( .Z (N51[7]), .I0 (en), - .I1 (_N19522)); + .I1 (_N19469)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[9] */ #( .INIT(4'b1000)) \N51_2[9] ( - .Z (N45_alias[1]), + .Z (N45[1]), .I0 (en), .I1 (quotient_ci[0])); // LUT = I0&I1 ; @@ -16420,7 +16318,7 @@ module divider_cell_1_unq44 .Q (quotient[0]), .C (sync_vg_100m), .CLK (clk), - .D (N45_alias[0])); + .D (N45[0])); // ../../sources/designs/adjust_color/divider_cell.v:24 GTP_DFF_C /* \quotient[1] */ #( @@ -16430,7 +16328,7 @@ module divider_cell_1_unq44 .Q (quotient[1]), .C (sync_vg_100m), .CLK (clk), - .D (N45_alias[1])); + .D (N45[1])); // ../../sources/designs/adjust_color/divider_cell.v:24 GTP_DFF_C /* \remainder[0] */ #( @@ -16519,33 +16417,29 @@ endmodule module divider_cell_1_unq46 ( - input [15:0] N45, input [8:0] dividend, input [7:0] divisor, input [15:0] quotient_ci, - input \adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N6 , input clk, input en, input sync_vg_100m, - output [12:0] \adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45 , output [7:0] divisor_kp, output [15:0] quotient, - output [7:0] remainder, - output N6 + output [7:0] remainder ); + wire N6; wire [9:0] \N6.co ; wire [7:0] \N20_1.co ; - wire [15:0] N45_alias; + wire [15:0] N45; wire [7:0] N51; wire [7:0] N53; - wire _N19550; - wire _N19551; - wire _N19552; - wire _N19553; - wire _N19554; - wire _N19555; - wire _N19556; - assign N45_alias[0] = N45[0]; + wire _N19497; + wire _N19498; + wire _N19499; + wire _N19500; + wire _N19501; + wire _N19502; + wire _N19503; GTP_LUT5CARRY /* \N6.lt_0 */ #( .INIT(32'b10001110100011100000000000000000), @@ -16675,7 +16569,7 @@ module divider_cell_1_unq46 .I4_TO_LUT("FALSE")) \N20_1.fsub_1 ( .COUT (\N20_1.co [1] ), - .Z (_N19550), + .Z (_N19497), .CIN (\N20_1.co [0] ), .I0 (), .I1 (divisor[1]), @@ -16695,7 +16589,7 @@ module divider_cell_1_unq46 .I4_TO_LUT("FALSE")) \N20_1.fsub_2 ( .COUT (\N20_1.co [2] ), - .Z (_N19551), + .Z (_N19498), .CIN (\N20_1.co [1] ), .I0 (), .I1 (divisor[2]), @@ -16715,7 +16609,7 @@ module divider_cell_1_unq46 .I4_TO_LUT("FALSE")) \N20_1.fsub_3 ( .COUT (\N20_1.co [3] ), - .Z (_N19552), + .Z (_N19499), .CIN (\N20_1.co [2] ), .I0 (), .I1 (divisor[3]), @@ -16735,7 +16629,7 @@ module divider_cell_1_unq46 .I4_TO_LUT("FALSE")) \N20_1.fsub_4 ( .COUT (\N20_1.co [4] ), - .Z (_N19553), + .Z (_N19500), .CIN (\N20_1.co [3] ), .I0 (), .I1 (divisor[4]), @@ -16755,7 +16649,7 @@ module divider_cell_1_unq46 .I4_TO_LUT("FALSE")) \N20_1.fsub_5 ( .COUT (\N20_1.co [5] ), - .Z (_N19554), + .Z (_N19501), .CIN (\N20_1.co [4] ), .I0 (), .I1 (divisor[5]), @@ -16775,7 +16669,7 @@ module divider_cell_1_unq46 .I4_TO_LUT("FALSE")) \N20_1.fsub_6 ( .COUT (\N20_1.co [6] ), - .Z (_N19555), + .Z (_N19502), .CIN (\N20_1.co [5] ), .I0 (), .I1 (divisor[6]), @@ -16795,7 +16689,7 @@ module divider_cell_1_unq46 .I4_TO_LUT("FALSE")) \N20_1.fsub_7 ( .COUT (), - .Z (_N19556), + .Z (_N19503), .CIN (\N20_1.co [6] ), .I0 (), .I1 (divisor[7]), @@ -16819,9 +16713,9 @@ module divider_cell_1_unq46 GTP_LUT2 /* \N51_2[0]_1 */ #( .INIT(4'b0010)) \N51_2[0]_1 ( - .Z (\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45 [0] ), + .Z (N45[0]), .I0 (en), - .I1 (\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N6 )); + .I1 (N6)); // LUT = I0&~I1 ; GTP_LUT2 /* \N51_2[1] */ #( @@ -16829,7 +16723,7 @@ module divider_cell_1_unq46 \N51_2[1] ( .Z (N51[1]), .I0 (en), - .I1 (_N19550)); + .I1 (_N19497)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[2] */ #( @@ -16837,7 +16731,7 @@ module divider_cell_1_unq46 \N51_2[2] ( .Z (N51[2]), .I0 (en), - .I1 (_N19551)); + .I1 (_N19498)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[3] */ #( @@ -16845,7 +16739,7 @@ module divider_cell_1_unq46 \N51_2[3] ( .Z (N51[3]), .I0 (en), - .I1 (_N19552)); + .I1 (_N19499)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[4] */ #( @@ -16853,7 +16747,7 @@ module divider_cell_1_unq46 \N51_2[4] ( .Z (N51[4]), .I0 (en), - .I1 (_N19553)); + .I1 (_N19500)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[5] */ #( @@ -16861,7 +16755,7 @@ module divider_cell_1_unq46 \N51_2[5] ( .Z (N51[5]), .I0 (en), - .I1 (_N19554)); + .I1 (_N19501)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[6] */ #( @@ -16869,7 +16763,7 @@ module divider_cell_1_unq46 \N51_2[6] ( .Z (N51[6]), .I0 (en), - .I1 (_N19555)); + .I1 (_N19502)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[7] */ #( @@ -16877,13 +16771,13 @@ module divider_cell_1_unq46 \N51_2[7] ( .Z (N51[7]), .I0 (en), - .I1 (_N19556)); + .I1 (_N19503)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[9] */ #( .INIT(4'b1000)) \N51_2[9] ( - .Z (N45_alias[1]), + .Z (N45[1]), .I0 (en), .I1 (quotient_ci[0])); // LUT = I0&I1 ; @@ -16891,7 +16785,7 @@ module divider_cell_1_unq46 GTP_LUT2 /* \N51_2[10] */ #( .INIT(4'b1000)) \N51_2[10] ( - .Z (N45_alias[2]), + .Z (N45[2]), .I0 (en), .I1 (quotient_ci[1])); // LUT = I0&I1 ; @@ -17055,7 +16949,7 @@ module divider_cell_1_unq46 .Q (quotient[0]), .C (sync_vg_100m), .CLK (clk), - .D (N45_alias[0])); + .D (N45[0])); // ../../sources/designs/adjust_color/divider_cell.v:24 GTP_DFF_C /* \quotient[1] */ #( @@ -17065,7 +16959,7 @@ module divider_cell_1_unq46 .Q (quotient[1]), .C (sync_vg_100m), .CLK (clk), - .D (N45_alias[1])); + .D (N45[1])); // ../../sources/designs/adjust_color/divider_cell.v:24 GTP_DFF_C /* \quotient[2] */ #( @@ -17075,7 +16969,7 @@ module divider_cell_1_unq46 .Q (quotient[2]), .C (sync_vg_100m), .CLK (clk), - .D (N45_alias[2])); + .D (N45[2])); // ../../sources/designs/adjust_color/divider_cell.v:24 GTP_DFF_C /* \remainder[0] */ #( @@ -17164,33 +17058,29 @@ endmodule module divider_cell_1_unq48 ( - input [15:0] N45, input [8:0] dividend, input [7:0] divisor, input [15:0] quotient_ci, - input \adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N6 , input clk, input en, input sync_vg_100m, - output [12:0] \adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45 , output [7:0] divisor_kp, output [15:0] quotient, - output [7:0] remainder, - output N6 + output [7:0] remainder ); + wire N6; wire [9:0] \N6.co ; wire [7:0] \N20_1.co ; - wire [15:0] N45_alias; + wire [15:0] N45; wire [7:0] N51; wire [7:0] N53; - wire _N19586; - wire _N19587; - wire _N19588; - wire _N19589; - wire _N19590; - wire _N19591; - wire _N19592; - assign N45_alias[0] = N45[0]; + wire _N19533; + wire _N19534; + wire _N19535; + wire _N19536; + wire _N19537; + wire _N19538; + wire _N19539; GTP_LUT5CARRY /* \N6.lt_0 */ #( .INIT(32'b10001110100011100000000000000000), @@ -17320,7 +17210,7 @@ module divider_cell_1_unq48 .I4_TO_LUT("FALSE")) \N20_1.fsub_1 ( .COUT (\N20_1.co [1] ), - .Z (_N19586), + .Z (_N19533), .CIN (\N20_1.co [0] ), .I0 (), .I1 (divisor[1]), @@ -17340,7 +17230,7 @@ module divider_cell_1_unq48 .I4_TO_LUT("FALSE")) \N20_1.fsub_2 ( .COUT (\N20_1.co [2] ), - .Z (_N19587), + .Z (_N19534), .CIN (\N20_1.co [1] ), .I0 (), .I1 (divisor[2]), @@ -17360,7 +17250,7 @@ module divider_cell_1_unq48 .I4_TO_LUT("FALSE")) \N20_1.fsub_3 ( .COUT (\N20_1.co [3] ), - .Z (_N19588), + .Z (_N19535), .CIN (\N20_1.co [2] ), .I0 (), .I1 (divisor[3]), @@ -17380,7 +17270,7 @@ module divider_cell_1_unq48 .I4_TO_LUT("FALSE")) \N20_1.fsub_4 ( .COUT (\N20_1.co [4] ), - .Z (_N19589), + .Z (_N19536), .CIN (\N20_1.co [3] ), .I0 (), .I1 (divisor[4]), @@ -17400,7 +17290,7 @@ module divider_cell_1_unq48 .I4_TO_LUT("FALSE")) \N20_1.fsub_5 ( .COUT (\N20_1.co [5] ), - .Z (_N19590), + .Z (_N19537), .CIN (\N20_1.co [4] ), .I0 (), .I1 (divisor[5]), @@ -17420,7 +17310,7 @@ module divider_cell_1_unq48 .I4_TO_LUT("FALSE")) \N20_1.fsub_6 ( .COUT (\N20_1.co [6] ), - .Z (_N19591), + .Z (_N19538), .CIN (\N20_1.co [5] ), .I0 (), .I1 (divisor[6]), @@ -17440,7 +17330,7 @@ module divider_cell_1_unq48 .I4_TO_LUT("FALSE")) \N20_1.fsub_7 ( .COUT (), - .Z (_N19592), + .Z (_N19539), .CIN (\N20_1.co [6] ), .I0 (), .I1 (divisor[7]), @@ -17464,9 +17354,9 @@ module divider_cell_1_unq48 GTP_LUT2 /* \N51_2[0]_1 */ #( .INIT(4'b0010)) \N51_2[0]_1 ( - .Z (\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45 [0] ), + .Z (N45[0]), .I0 (en), - .I1 (\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N6 )); + .I1 (N6)); // LUT = I0&~I1 ; GTP_LUT2 /* \N51_2[1] */ #( @@ -17474,7 +17364,7 @@ module divider_cell_1_unq48 \N51_2[1] ( .Z (N51[1]), .I0 (en), - .I1 (_N19586)); + .I1 (_N19533)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[2] */ #( @@ -17482,7 +17372,7 @@ module divider_cell_1_unq48 \N51_2[2] ( .Z (N51[2]), .I0 (en), - .I1 (_N19587)); + .I1 (_N19534)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[3] */ #( @@ -17490,7 +17380,7 @@ module divider_cell_1_unq48 \N51_2[3] ( .Z (N51[3]), .I0 (en), - .I1 (_N19588)); + .I1 (_N19535)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[4] */ #( @@ -17498,7 +17388,7 @@ module divider_cell_1_unq48 \N51_2[4] ( .Z (N51[4]), .I0 (en), - .I1 (_N19589)); + .I1 (_N19536)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[5] */ #( @@ -17506,7 +17396,7 @@ module divider_cell_1_unq48 \N51_2[5] ( .Z (N51[5]), .I0 (en), - .I1 (_N19590)); + .I1 (_N19537)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[6] */ #( @@ -17514,7 +17404,7 @@ module divider_cell_1_unq48 \N51_2[6] ( .Z (N51[6]), .I0 (en), - .I1 (_N19591)); + .I1 (_N19538)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[7] */ #( @@ -17522,13 +17412,13 @@ module divider_cell_1_unq48 \N51_2[7] ( .Z (N51[7]), .I0 (en), - .I1 (_N19592)); + .I1 (_N19539)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[9] */ #( .INIT(4'b1000)) \N51_2[9] ( - .Z (N45_alias[1]), + .Z (N45[1]), .I0 (en), .I1 (quotient_ci[0])); // LUT = I0&I1 ; @@ -17536,7 +17426,7 @@ module divider_cell_1_unq48 GTP_LUT2 /* \N51_2[10] */ #( .INIT(4'b1000)) \N51_2[10] ( - .Z (N45_alias[2]), + .Z (N45[2]), .I0 (en), .I1 (quotient_ci[1])); // LUT = I0&I1 ; @@ -17544,7 +17434,7 @@ module divider_cell_1_unq48 GTP_LUT2 /* \N51_2[11] */ #( .INIT(4'b1000)) \N51_2[11] ( - .Z (N45_alias[3]), + .Z (N45[3]), .I0 (en), .I1 (quotient_ci[2])); // LUT = I0&I1 ; @@ -17708,7 +17598,7 @@ module divider_cell_1_unq48 .Q (quotient[0]), .C (sync_vg_100m), .CLK (clk), - .D (N45_alias[0])); + .D (N45[0])); // ../../sources/designs/adjust_color/divider_cell.v:24 GTP_DFF_C /* \quotient[1] */ #( @@ -17718,7 +17608,7 @@ module divider_cell_1_unq48 .Q (quotient[1]), .C (sync_vg_100m), .CLK (clk), - .D (N45_alias[1])); + .D (N45[1])); // ../../sources/designs/adjust_color/divider_cell.v:24 GTP_DFF_C /* \quotient[2] */ #( @@ -17728,7 +17618,7 @@ module divider_cell_1_unq48 .Q (quotient[2]), .C (sync_vg_100m), .CLK (clk), - .D (N45_alias[2])); + .D (N45[2])); // ../../sources/designs/adjust_color/divider_cell.v:24 GTP_DFF_C /* \quotient[3] */ #( @@ -17738,7 +17628,7 @@ module divider_cell_1_unq48 .Q (quotient[3]), .C (sync_vg_100m), .CLK (clk), - .D (N45_alias[3])); + .D (N45[3])); // ../../sources/designs/adjust_color/divider_cell.v:24 GTP_DFF_C /* \remainder[0] */ #( @@ -17827,33 +17717,29 @@ endmodule module divider_cell_1_unq50 ( - input [15:0] N45, input [8:0] dividend, input [7:0] divisor, input [15:0] quotient_ci, - input \adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N6 , input clk, input en, input sync_vg_100m, - output [12:0] \adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45 , output [7:0] divisor_kp, output [15:0] quotient, - output [7:0] remainder, - output N6 + output [7:0] remainder ); + wire N6; wire [9:0] \N6.co ; wire [7:0] \N20_1.co ; - wire [15:0] N45_alias; + wire [15:0] N45; wire [7:0] N51; wire [7:0] N53; - wire _N19699; - wire _N19700; - wire _N19701; - wire _N19702; - wire _N19703; - wire _N19704; - wire _N19705; - assign N45_alias[0] = N45[0]; + wire _N19646; + wire _N19647; + wire _N19648; + wire _N19649; + wire _N19650; + wire _N19651; + wire _N19652; GTP_LUT5CARRY /* \N6.lt_0 */ #( .INIT(32'b10001110100011100000000000000000), @@ -17983,7 +17869,7 @@ module divider_cell_1_unq50 .I4_TO_LUT("FALSE")) \N20_1.fsub_1 ( .COUT (\N20_1.co [1] ), - .Z (_N19699), + .Z (_N19646), .CIN (\N20_1.co [0] ), .I0 (), .I1 (divisor[1]), @@ -18003,7 +17889,7 @@ module divider_cell_1_unq50 .I4_TO_LUT("FALSE")) \N20_1.fsub_2 ( .COUT (\N20_1.co [2] ), - .Z (_N19700), + .Z (_N19647), .CIN (\N20_1.co [1] ), .I0 (), .I1 (divisor[2]), @@ -18023,7 +17909,7 @@ module divider_cell_1_unq50 .I4_TO_LUT("FALSE")) \N20_1.fsub_3 ( .COUT (\N20_1.co [3] ), - .Z (_N19701), + .Z (_N19648), .CIN (\N20_1.co [2] ), .I0 (), .I1 (divisor[3]), @@ -18043,7 +17929,7 @@ module divider_cell_1_unq50 .I4_TO_LUT("FALSE")) \N20_1.fsub_4 ( .COUT (\N20_1.co [4] ), - .Z (_N19702), + .Z (_N19649), .CIN (\N20_1.co [3] ), .I0 (), .I1 (divisor[4]), @@ -18063,7 +17949,7 @@ module divider_cell_1_unq50 .I4_TO_LUT("FALSE")) \N20_1.fsub_5 ( .COUT (\N20_1.co [5] ), - .Z (_N19703), + .Z (_N19650), .CIN (\N20_1.co [4] ), .I0 (), .I1 (divisor[5]), @@ -18083,7 +17969,7 @@ module divider_cell_1_unq50 .I4_TO_LUT("FALSE")) \N20_1.fsub_6 ( .COUT (\N20_1.co [6] ), - .Z (_N19704), + .Z (_N19651), .CIN (\N20_1.co [5] ), .I0 (), .I1 (divisor[6]), @@ -18103,7 +17989,7 @@ module divider_cell_1_unq50 .I4_TO_LUT("FALSE")) \N20_1.fsub_7 ( .COUT (), - .Z (_N19705), + .Z (_N19652), .CIN (\N20_1.co [6] ), .I0 (), .I1 (divisor[7]), @@ -18127,9 +18013,9 @@ module divider_cell_1_unq50 GTP_LUT2 /* \N51_2[0]_1 */ #( .INIT(4'b0010)) \N51_2[0]_1 ( - .Z (\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45 [0] ), + .Z (N45[0]), .I0 (en), - .I1 (\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N6 )); + .I1 (N6)); // LUT = I0&~I1 ; GTP_LUT2 /* \N51_2[1] */ #( @@ -18137,7 +18023,7 @@ module divider_cell_1_unq50 \N51_2[1] ( .Z (N51[1]), .I0 (en), - .I1 (_N19699)); + .I1 (_N19646)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[2] */ #( @@ -18145,7 +18031,7 @@ module divider_cell_1_unq50 \N51_2[2] ( .Z (N51[2]), .I0 (en), - .I1 (_N19700)); + .I1 (_N19647)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[3] */ #( @@ -18153,7 +18039,7 @@ module divider_cell_1_unq50 \N51_2[3] ( .Z (N51[3]), .I0 (en), - .I1 (_N19701)); + .I1 (_N19648)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[4] */ #( @@ -18161,7 +18047,7 @@ module divider_cell_1_unq50 \N51_2[4] ( .Z (N51[4]), .I0 (en), - .I1 (_N19702)); + .I1 (_N19649)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[5] */ #( @@ -18169,7 +18055,7 @@ module divider_cell_1_unq50 \N51_2[5] ( .Z (N51[5]), .I0 (en), - .I1 (_N19703)); + .I1 (_N19650)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[6] */ #( @@ -18177,7 +18063,7 @@ module divider_cell_1_unq50 \N51_2[6] ( .Z (N51[6]), .I0 (en), - .I1 (_N19704)); + .I1 (_N19651)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[7] */ #( @@ -18185,13 +18071,13 @@ module divider_cell_1_unq50 \N51_2[7] ( .Z (N51[7]), .I0 (en), - .I1 (_N19705)); + .I1 (_N19652)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[9] */ #( .INIT(4'b1000)) \N51_2[9] ( - .Z (N45_alias[1]), + .Z (N45[1]), .I0 (en), .I1 (quotient_ci[0])); // LUT = I0&I1 ; @@ -18199,7 +18085,7 @@ module divider_cell_1_unq50 GTP_LUT2 /* \N51_2[10] */ #( .INIT(4'b1000)) \N51_2[10] ( - .Z (N45_alias[2]), + .Z (N45[2]), .I0 (en), .I1 (quotient_ci[1])); // LUT = I0&I1 ; @@ -18207,7 +18093,7 @@ module divider_cell_1_unq50 GTP_LUT2 /* \N51_2[11] */ #( .INIT(4'b1000)) \N51_2[11] ( - .Z (N45_alias[3]), + .Z (N45[3]), .I0 (en), .I1 (quotient_ci[2])); // LUT = I0&I1 ; @@ -18215,7 +18101,7 @@ module divider_cell_1_unq50 GTP_LUT2 /* \N51_2[12] */ #( .INIT(4'b1000)) \N51_2[12] ( - .Z (N45_alias[4]), + .Z (N45[4]), .I0 (en), .I1 (quotient_ci[3])); // LUT = I0&I1 ; @@ -18379,7 +18265,7 @@ module divider_cell_1_unq50 .Q (quotient[0]), .C (sync_vg_100m), .CLK (clk), - .D (N45_alias[0])); + .D (N45[0])); // ../../sources/designs/adjust_color/divider_cell.v:24 GTP_DFF_C /* \quotient[1] */ #( @@ -18389,7 +18275,7 @@ module divider_cell_1_unq50 .Q (quotient[1]), .C (sync_vg_100m), .CLK (clk), - .D (N45_alias[1])); + .D (N45[1])); // ../../sources/designs/adjust_color/divider_cell.v:24 GTP_DFF_C /* \quotient[2] */ #( @@ -18399,7 +18285,7 @@ module divider_cell_1_unq50 .Q (quotient[2]), .C (sync_vg_100m), .CLK (clk), - .D (N45_alias[2])); + .D (N45[2])); // ../../sources/designs/adjust_color/divider_cell.v:24 GTP_DFF_C /* \quotient[3] */ #( @@ -18409,7 +18295,7 @@ module divider_cell_1_unq50 .Q (quotient[3]), .C (sync_vg_100m), .CLK (clk), - .D (N45_alias[3])); + .D (N45[3])); // ../../sources/designs/adjust_color/divider_cell.v:24 GTP_DFF_C /* \quotient[4] */ #( @@ -18419,7 +18305,7 @@ module divider_cell_1_unq50 .Q (quotient[4]), .C (sync_vg_100m), .CLK (clk), - .D (N45_alias[4])); + .D (N45[4])); // ../../sources/designs/adjust_color/divider_cell.v:24 GTP_DFF_C /* \remainder[0] */ #( @@ -18525,13 +18411,13 @@ module divider_cell_1_unq52 wire [15:0] N45; wire [7:0] N51; wire [7:0] N53; - wire _N19739; - wire _N19740; - wire _N19741; - wire _N19742; - wire _N19743; - wire _N19744; - wire _N19745; + wire _N19686; + wire _N19687; + wire _N19688; + wire _N19689; + wire _N19690; + wire _N19691; + wire _N19692; GTP_LUT5CARRY /* \N6.lt_0 */ #( .INIT(32'b10001110100011100000000000000000), @@ -18661,7 +18547,7 @@ module divider_cell_1_unq52 .I4_TO_LUT("FALSE")) \N20_1.fsub_1 ( .COUT (\N20_1.co [1] ), - .Z (_N19739), + .Z (_N19686), .CIN (\N20_1.co [0] ), .I0 (), .I1 (divisor[1]), @@ -18681,7 +18567,7 @@ module divider_cell_1_unq52 .I4_TO_LUT("FALSE")) \N20_1.fsub_2 ( .COUT (\N20_1.co [2] ), - .Z (_N19740), + .Z (_N19687), .CIN (\N20_1.co [1] ), .I0 (), .I1 (divisor[2]), @@ -18701,7 +18587,7 @@ module divider_cell_1_unq52 .I4_TO_LUT("FALSE")) \N20_1.fsub_3 ( .COUT (\N20_1.co [3] ), - .Z (_N19741), + .Z (_N19688), .CIN (\N20_1.co [2] ), .I0 (), .I1 (divisor[3]), @@ -18721,7 +18607,7 @@ module divider_cell_1_unq52 .I4_TO_LUT("FALSE")) \N20_1.fsub_4 ( .COUT (\N20_1.co [4] ), - .Z (_N19742), + .Z (_N19689), .CIN (\N20_1.co [3] ), .I0 (), .I1 (divisor[4]), @@ -18741,7 +18627,7 @@ module divider_cell_1_unq52 .I4_TO_LUT("FALSE")) \N20_1.fsub_5 ( .COUT (\N20_1.co [5] ), - .Z (_N19743), + .Z (_N19690), .CIN (\N20_1.co [4] ), .I0 (), .I1 (divisor[5]), @@ -18761,7 +18647,7 @@ module divider_cell_1_unq52 .I4_TO_LUT("FALSE")) \N20_1.fsub_6 ( .COUT (\N20_1.co [6] ), - .Z (_N19744), + .Z (_N19691), .CIN (\N20_1.co [5] ), .I0 (), .I1 (divisor[6]), @@ -18781,7 +18667,7 @@ module divider_cell_1_unq52 .I4_TO_LUT("FALSE")) \N20_1.fsub_7 ( .COUT (), - .Z (_N19745), + .Z (_N19692), .CIN (\N20_1.co [6] ), .I0 (), .I1 (divisor[7]), @@ -18815,7 +18701,7 @@ module divider_cell_1_unq52 \N51_2[1] ( .Z (N51[1]), .I0 (en), - .I1 (_N19739)); + .I1 (_N19686)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[2] */ #( @@ -18823,7 +18709,7 @@ module divider_cell_1_unq52 \N51_2[2] ( .Z (N51[2]), .I0 (en), - .I1 (_N19740)); + .I1 (_N19687)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[3] */ #( @@ -18831,7 +18717,7 @@ module divider_cell_1_unq52 \N51_2[3] ( .Z (N51[3]), .I0 (en), - .I1 (_N19741)); + .I1 (_N19688)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[4] */ #( @@ -18839,7 +18725,7 @@ module divider_cell_1_unq52 \N51_2[4] ( .Z (N51[4]), .I0 (en), - .I1 (_N19742)); + .I1 (_N19689)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[5] */ #( @@ -18847,7 +18733,7 @@ module divider_cell_1_unq52 \N51_2[5] ( .Z (N51[5]), .I0 (en), - .I1 (_N19743)); + .I1 (_N19690)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[6] */ #( @@ -18855,7 +18741,7 @@ module divider_cell_1_unq52 \N51_2[6] ( .Z (N51[6]), .I0 (en), - .I1 (_N19744)); + .I1 (_N19691)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[7] */ #( @@ -18863,7 +18749,7 @@ module divider_cell_1_unq52 \N51_2[7] ( .Z (N51[7]), .I0 (en), - .I1 (_N19745)); + .I1 (_N19692)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[9] */ #( @@ -19232,13 +19118,13 @@ module divider_cell_1_unq54 wire [15:0] N45; wire [7:0] N51; wire [7:0] N53; - wire _N19893; - wire _N19894; - wire _N19895; - wire _N19896; - wire _N19897; - wire _N19898; - wire _N19899; + wire _N19832; + wire _N19833; + wire _N19834; + wire _N19835; + wire _N19836; + wire _N19837; + wire _N19838; GTP_LUT5CARRY /* \N6.lt_0 */ #( .INIT(32'b10001110100011100000000000000000), @@ -19368,7 +19254,7 @@ module divider_cell_1_unq54 .I4_TO_LUT("FALSE")) \N20_1.fsub_1 ( .COUT (\N20_1.co [1] ), - .Z (_N19893), + .Z (_N19832), .CIN (\N20_1.co [0] ), .I0 (), .I1 (divisor[1]), @@ -19388,7 +19274,7 @@ module divider_cell_1_unq54 .I4_TO_LUT("FALSE")) \N20_1.fsub_2 ( .COUT (\N20_1.co [2] ), - .Z (_N19894), + .Z (_N19833), .CIN (\N20_1.co [1] ), .I0 (), .I1 (divisor[2]), @@ -19408,7 +19294,7 @@ module divider_cell_1_unq54 .I4_TO_LUT("FALSE")) \N20_1.fsub_3 ( .COUT (\N20_1.co [3] ), - .Z (_N19895), + .Z (_N19834), .CIN (\N20_1.co [2] ), .I0 (), .I1 (divisor[3]), @@ -19428,7 +19314,7 @@ module divider_cell_1_unq54 .I4_TO_LUT("FALSE")) \N20_1.fsub_4 ( .COUT (\N20_1.co [4] ), - .Z (_N19896), + .Z (_N19835), .CIN (\N20_1.co [3] ), .I0 (), .I1 (divisor[4]), @@ -19448,7 +19334,7 @@ module divider_cell_1_unq54 .I4_TO_LUT("FALSE")) \N20_1.fsub_5 ( .COUT (\N20_1.co [5] ), - .Z (_N19897), + .Z (_N19836), .CIN (\N20_1.co [4] ), .I0 (), .I1 (divisor[5]), @@ -19468,7 +19354,7 @@ module divider_cell_1_unq54 .I4_TO_LUT("FALSE")) \N20_1.fsub_6 ( .COUT (\N20_1.co [6] ), - .Z (_N19898), + .Z (_N19837), .CIN (\N20_1.co [5] ), .I0 (), .I1 (divisor[6]), @@ -19488,7 +19374,7 @@ module divider_cell_1_unq54 .I4_TO_LUT("FALSE")) \N20_1.fsub_7 ( .COUT (), - .Z (_N19899), + .Z (_N19838), .CIN (\N20_1.co [6] ), .I0 (), .I1 (divisor[7]), @@ -19522,7 +19408,7 @@ module divider_cell_1_unq54 \N51_2[1] ( .Z (N51[1]), .I0 (en), - .I1 (_N19893)); + .I1 (_N19832)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[2] */ #( @@ -19530,7 +19416,7 @@ module divider_cell_1_unq54 \N51_2[2] ( .Z (N51[2]), .I0 (en), - .I1 (_N19894)); + .I1 (_N19833)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[3] */ #( @@ -19538,7 +19424,7 @@ module divider_cell_1_unq54 \N51_2[3] ( .Z (N51[3]), .I0 (en), - .I1 (_N19895)); + .I1 (_N19834)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[4] */ #( @@ -19546,7 +19432,7 @@ module divider_cell_1_unq54 \N51_2[4] ( .Z (N51[4]), .I0 (en), - .I1 (_N19896)); + .I1 (_N19835)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[5] */ #( @@ -19554,7 +19440,7 @@ module divider_cell_1_unq54 \N51_2[5] ( .Z (N51[5]), .I0 (en), - .I1 (_N19897)); + .I1 (_N19836)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[6] */ #( @@ -19562,7 +19448,7 @@ module divider_cell_1_unq54 \N51_2[6] ( .Z (N51[6]), .I0 (en), - .I1 (_N19898)); + .I1 (_N19837)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[7] */ #( @@ -19570,7 +19456,7 @@ module divider_cell_1_unq54 \N51_2[7] ( .Z (N51[7]), .I0 (en), - .I1 (_N19899)); + .I1 (_N19838)); // LUT = I0&I1 ; GTP_LUT2 /* \N51_2[9] */ #( @@ -19957,13 +19843,13 @@ module divider_cell_1_unq56 wire [15:0] N45; wire [7:0] N51; wire [7:0] N53; - wire _N19796; - wire _N19797; - wire _N19798; - wire _N19799; - wire _N19800; - wire _N19801; - wire _N19802; + wire _N19743; + wire _N19744; + wire _N19745; + wire _N19746; + wire _N19747; + wire _N19748; + wire _N19749; GTP_LUT5CARRY /* \N6.lt_0 */ #( .INIT(32'b10001110100011100000000000000000), @@ -20093,7 +19979,7 @@ module divider_cell_1_unq56 .I4_TO_LUT("FALSE")) \N20_1.fsub_1 ( .COUT (\N20_1.co [1] ), - .Z (_N19796), + .Z (_N19743), .CIN (\N20_1.co [0] ), .I0 (), .I1 (divisor[1]), @@ -20113,7 +19999,7 @@ module divider_cell_1_unq56 .I4_TO_LUT("FALSE")) \N20_1.fsub_2 ( .COUT (\N20_1.co [2] ), - .Z (_N19797), + .Z (_N19744), .CIN (\N20_1.co [1] ), .I0 (), .I1 (divisor[2]), @@ -20133,7 +20019,7 @@ module divider_cell_1_unq56 .I4_TO_LUT("FALSE")) \N20_1.fsub_3 ( .COUT (\N20_1.co [3] ), - .Z (_N19798), + .Z (_N19745), .CIN (\N20_1.co [2] ), .I0 (), .I1 (divisor[3]), @@ -20153,7 +20039,7 @@ module divider_cell_1_unq56 .I4_TO_LUT("FALSE")) \N20_1.fsub_4 ( .COUT (\N20_1.co [4] ), - .Z (_N19799), + .Z (_N19746), .CIN (\N20_1.co [3] ), .I0 (), .I1 (divisor[4]), @@ -20173,7 +20059,7 @@ module divider_cell_1_unq56 .I4_TO_LUT("FALSE")) \N20_1.fsub_5 ( .COUT (\N20_1.co [5] ), - .Z (_N19800), + .Z (_N19747), .CIN (\N20_1.co [4] ), .I0 (), .I1 (divisor[5]), @@ -20193,7 +20079,7 @@ module divider_cell_1_unq56 .I4_TO_LUT("FALSE")) \N20_1.fsub_6 ( .COUT (\N20_1.co [6] ), - .Z (_N19801), + .Z (_N19748), .CIN (\N20_1.co [5] ), .I0 (), .I1 (divisor[6]), @@ -20213,7 +20099,7 @@ module divider_cell_1_unq56 .I4_TO_LUT("FALSE")) \N20_1.fsub_7 ( .COUT (), - .Z (_N19802), + .Z (_N19749), .CIN (\N20_1.co [6] ), .I0 (), .I1 (divisor[7]), @@ -20303,7 +20189,7 @@ module divider_cell_1_unq56 \N45_2[16] ( .Z (N51[1]), .I0 (en), - .I1 (_N19796)); + .I1 (_N19743)); // LUT = I0&I1 ; GTP_LUT2 /* \N45_2[17] */ #( @@ -20311,7 +20197,7 @@ module divider_cell_1_unq56 \N45_2[17] ( .Z (N51[2]), .I0 (en), - .I1 (_N19797)); + .I1 (_N19744)); // LUT = I0&I1 ; GTP_LUT2 /* \N45_2[18] */ #( @@ -20319,7 +20205,7 @@ module divider_cell_1_unq56 \N45_2[18] ( .Z (N51[3]), .I0 (en), - .I1 (_N19798)); + .I1 (_N19745)); // LUT = I0&I1 ; GTP_LUT2 /* \N45_2[19] */ #( @@ -20327,7 +20213,7 @@ module divider_cell_1_unq56 \N45_2[19] ( .Z (N51[4]), .I0 (en), - .I1 (_N19799)); + .I1 (_N19746)); // LUT = I0&I1 ; GTP_LUT2 /* \N45_2[20] */ #( @@ -20335,7 +20221,7 @@ module divider_cell_1_unq56 \N45_2[20] ( .Z (N51[5]), .I0 (en), - .I1 (_N19800)); + .I1 (_N19747)); // LUT = I0&I1 ; GTP_LUT2 /* \N45_2[21] */ #( @@ -20343,7 +20229,7 @@ module divider_cell_1_unq56 \N45_2[21] ( .Z (N51[6]), .I0 (en), - .I1 (_N19801)); + .I1 (_N19748)); // LUT = I0&I1 ; GTP_LUT2 /* \N45_2[22] */ #( @@ -20351,7 +20237,7 @@ module divider_cell_1_unq56 \N45_2[22] ( .Z (N51[7]), .I0 (en), - .I1 (_N19802)); + .I1 (_N19749)); // LUT = I0&I1 ; GTP_LUT2 /* \N53[0]_1 */ #( @@ -20979,12 +20865,12 @@ module divider_cell_1_unq60 wire [7:0] N53; wire [14:0] N54; wire [7:0] N61; - wire _N107213; + wire _N108035; GTP_LUT5 /* N6_mux7_7 */ #( .INIT(32'b11111111111111111111111111110100)) N6_mux7_7 ( - .Z (_N107213), + .Z (_N108035), .I0 (dividend[0]), .I1 (divisor[0]), .I2 (divisor[5]), @@ -21000,7 +20886,7 @@ module divider_cell_1_unq60 .I1 (divisor[2]), .I2 (divisor[3]), .I3 (divisor[4]), - .I4 (_N107213)); + .I4 (_N108035)); // LUT = (I0)|(I1)|(I2)|(I3)|(I4) ; GTP_LUT5CARRY /* \N20.fsub_0 */ #( @@ -21566,27 +21452,11 @@ module divider_1 ( input [15:0] dividend, input [7:0] divisor, - input [15:0] \g_sqrt_stepx[8].u_divider_step/N45 , - input [15:0] \g_sqrt_stepx[9].u_divider_step/N45 , - input [15:0] \g_sqrt_stepx[10].u_divider_step/N45 , - input [15:0] \g_sqrt_stepx[11].u_divider_step/N45 , input [15:0] rdy_t, - input \adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N6 , - input \adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N6 , - input \adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N6 , - input \adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N6 , input clk, input in_valid, input sync_vg_100m, - output [12:0] \adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45 , - output [12:0] \adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45 , - output [12:0] \adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45 , - output [12:0] \adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45 , - output [15:0] quotient, - output \g_sqrt_stepx[8].u_divider_step/N6 , - output \g_sqrt_stepx[9].u_divider_step/N6 , - output \g_sqrt_stepx[10].u_divider_step/N6 , - output \g_sqrt_stepx[11].u_divider_step/N6 + output [15:0] quotient ); wire [14:0] \dividend_t[9] ; wire [14:0] \dividend_t[10] ; @@ -21718,18 +21588,6 @@ module divider_1 wire \g_sqrt_stepx[7].u_divider_step_quotient[13]_floating ; wire \g_sqrt_stepx[7].u_divider_step_quotient[14]_floating ; wire \g_sqrt_stepx[7].u_divider_step_quotient[15]_floating ; - wire \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[1]_floating ; - wire \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[2]_floating ; - wire \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[3]_floating ; - wire \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[4]_floating ; - wire \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[5]_floating ; - wire \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[6]_floating ; - wire \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[7]_floating ; - wire \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[8]_floating ; - wire \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[9]_floating ; - wire \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[10]_floating ; - wire \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[11]_floating ; - wire \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[12]_floating ; wire \g_sqrt_stepx[8].u_divider_step_quotient[2]_floating ; wire \g_sqrt_stepx[8].u_divider_step_quotient[3]_floating ; wire \g_sqrt_stepx[8].u_divider_step_quotient[4]_floating ; @@ -21744,18 +21602,6 @@ module divider_1 wire \g_sqrt_stepx[8].u_divider_step_quotient[13]_floating ; wire \g_sqrt_stepx[8].u_divider_step_quotient[14]_floating ; wire \g_sqrt_stepx[8].u_divider_step_quotient[15]_floating ; - wire \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[1]_floating ; - wire \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[2]_floating ; - wire \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[3]_floating ; - wire \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[4]_floating ; - wire \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[5]_floating ; - wire \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[6]_floating ; - wire \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[7]_floating ; - wire \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[8]_floating ; - wire \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[9]_floating ; - wire \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[10]_floating ; - wire \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[11]_floating ; - wire \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[12]_floating ; wire \g_sqrt_stepx[9].u_divider_step_quotient[3]_floating ; wire \g_sqrt_stepx[9].u_divider_step_quotient[4]_floating ; wire \g_sqrt_stepx[9].u_divider_step_quotient[5]_floating ; @@ -21769,18 +21615,6 @@ module divider_1 wire \g_sqrt_stepx[9].u_divider_step_quotient[13]_floating ; wire \g_sqrt_stepx[9].u_divider_step_quotient[14]_floating ; wire \g_sqrt_stepx[9].u_divider_step_quotient[15]_floating ; - wire \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[1]_floating ; - wire \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[2]_floating ; - wire \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[3]_floating ; - wire \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[4]_floating ; - wire \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[5]_floating ; - wire \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[6]_floating ; - wire \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[7]_floating ; - wire \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[8]_floating ; - wire \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[9]_floating ; - wire \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[10]_floating ; - wire \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[11]_floating ; - wire \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[12]_floating ; wire \g_sqrt_stepx[10].u_divider_step_quotient[4]_floating ; wire \g_sqrt_stepx[10].u_divider_step_quotient[5]_floating ; wire \g_sqrt_stepx[10].u_divider_step_quotient[6]_floating ; @@ -21793,18 +21627,6 @@ module divider_1 wire \g_sqrt_stepx[10].u_divider_step_quotient[13]_floating ; wire \g_sqrt_stepx[10].u_divider_step_quotient[14]_floating ; wire \g_sqrt_stepx[10].u_divider_step_quotient[15]_floating ; - wire \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[1]_floating ; - wire \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[2]_floating ; - wire \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[3]_floating ; - wire \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[4]_floating ; - wire \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[5]_floating ; - wire \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[6]_floating ; - wire \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[7]_floating ; - wire \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[8]_floating ; - wire \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[9]_floating ; - wire \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[10]_floating ; - wire \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[11]_floating ; - wire \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[12]_floating ; wire \g_sqrt_stepx[11].u_divider_step_quotient[5]_floating ; wire \g_sqrt_stepx[11].u_divider_step_quotient[6]_floating ; wire \g_sqrt_stepx[11].u_divider_step_quotient[7]_floating ; @@ -21955,64 +21777,48 @@ module divider_1 // ../../sources/designs/adjust_color/divider.v:54 divider_cell_1_unq44 \g_sqrt_stepx[8].u_divider_step ( - .\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45 ({\g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[12]_floating , \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[11]_floating , \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[10]_floating , \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[9]_floating , \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[8]_floating , \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[7]_floating , \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[6]_floating , \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[5]_floating , \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[4]_floating , \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[3]_floating , \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[2]_floating , \g_sqrt_stepx[8].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[1]_floating , \adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45 [0] }), .divisor_kp ({\divisor_t[7] [7] , \divisor_t[7] [6] , \divisor_t[7] [5] , \divisor_t[7] [4] , \divisor_t[7] [3] , \divisor_t[7] [2] , \divisor_t[7] [1] , \divisor_t[7] [0] }), .quotient ({\g_sqrt_stepx[8].u_divider_step_quotient[15]_floating , \g_sqrt_stepx[8].u_divider_step_quotient[14]_floating , \g_sqrt_stepx[8].u_divider_step_quotient[13]_floating , \g_sqrt_stepx[8].u_divider_step_quotient[12]_floating , \g_sqrt_stepx[8].u_divider_step_quotient[11]_floating , \g_sqrt_stepx[8].u_divider_step_quotient[10]_floating , \g_sqrt_stepx[8].u_divider_step_quotient[9]_floating , \g_sqrt_stepx[8].u_divider_step_quotient[8]_floating , \g_sqrt_stepx[8].u_divider_step_quotient[7]_floating , \g_sqrt_stepx[8].u_divider_step_quotient[6]_floating , \g_sqrt_stepx[8].u_divider_step_quotient[5]_floating , \g_sqrt_stepx[8].u_divider_step_quotient[4]_floating , \g_sqrt_stepx[8].u_divider_step_quotient[3]_floating , \g_sqrt_stepx[8].u_divider_step_quotient[2]_floating , \quotient_t[7] [1] , \quotient_t[7] [0] }), .remainder ({\remainder_t[7] [7] , \remainder_t[7] [6] , \remainder_t[7] [5] , \remainder_t[7] [4] , \remainder_t[7] [3] , \remainder_t[7] [2] , \remainder_t[7] [1] , \remainder_t[7] [0] }), - .N45 ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \g_sqrt_stepx[8].u_divider_step/N45 [0] }), .dividend ({\remainder_t[8] [7] , \remainder_t[8] [6] , \remainder_t[8] [5] , \remainder_t[8] [4] , \remainder_t[8] [3] , \remainder_t[8] [2] , \remainder_t[8] [1] , \remainder_t[8] [0] , 1'bx}), .divisor ({\divisor_t[8] [7] , \divisor_t[8] [6] , \divisor_t[8] [5] , \divisor_t[8] [4] , \divisor_t[8] [3] , \divisor_t[8] [2] , \divisor_t[8] [1] , \divisor_t[8] [0] }), .quotient_ci ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \quotient_t[8] [0] }), - .N6 (\g_sqrt_stepx[8].u_divider_step/N6 ), - .\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N6 (\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N6 ), .clk (clk), .en (rdy_t_alias[8]), .sync_vg_100m (sync_vg_100m)); // ../../sources/designs/adjust_color/divider.v:54 divider_cell_1_unq46 \g_sqrt_stepx[9].u_divider_step ( - .\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45 ({\g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[12]_floating , \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[11]_floating , \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[10]_floating , \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[9]_floating , \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[8]_floating , \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[7]_floating , \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[6]_floating , \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[5]_floating , \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[4]_floating , \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[3]_floating , \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[2]_floating , \g_sqrt_stepx[9].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[1]_floating , \adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45 [0] }), .divisor_kp ({\divisor_t[6] [7] , \divisor_t[6] [6] , \divisor_t[6] [5] , \divisor_t[6] [4] , \divisor_t[6] [3] , \divisor_t[6] [2] , \divisor_t[6] [1] , \divisor_t[6] [0] }), .quotient ({\g_sqrt_stepx[9].u_divider_step_quotient[15]_floating , \g_sqrt_stepx[9].u_divider_step_quotient[14]_floating , \g_sqrt_stepx[9].u_divider_step_quotient[13]_floating , \g_sqrt_stepx[9].u_divider_step_quotient[12]_floating , \g_sqrt_stepx[9].u_divider_step_quotient[11]_floating , \g_sqrt_stepx[9].u_divider_step_quotient[10]_floating , \g_sqrt_stepx[9].u_divider_step_quotient[9]_floating , \g_sqrt_stepx[9].u_divider_step_quotient[8]_floating , \g_sqrt_stepx[9].u_divider_step_quotient[7]_floating , \g_sqrt_stepx[9].u_divider_step_quotient[6]_floating , \g_sqrt_stepx[9].u_divider_step_quotient[5]_floating , \g_sqrt_stepx[9].u_divider_step_quotient[4]_floating , \g_sqrt_stepx[9].u_divider_step_quotient[3]_floating , \quotient_t[6] [2] , \quotient_t[6] [1] , \quotient_t[6] [0] }), .remainder ({\remainder_t[6] [7] , \remainder_t[6] [6] , \remainder_t[6] [5] , \remainder_t[6] [4] , \remainder_t[6] [3] , \remainder_t[6] [2] , \remainder_t[6] [1] , \remainder_t[6] [0] }), - .N45 ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \g_sqrt_stepx[9].u_divider_step/N45 [0] }), .dividend ({\remainder_t[7] [7] , \remainder_t[7] [6] , \remainder_t[7] [5] , \remainder_t[7] [4] , \remainder_t[7] [3] , \remainder_t[7] [2] , \remainder_t[7] [1] , \remainder_t[7] [0] , 1'bx}), .divisor ({\divisor_t[7] [7] , \divisor_t[7] [6] , \divisor_t[7] [5] , \divisor_t[7] [4] , \divisor_t[7] [3] , \divisor_t[7] [2] , \divisor_t[7] [1] , \divisor_t[7] [0] }), .quotient_ci ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \quotient_t[7] [1] , \quotient_t[7] [0] }), - .N6 (\g_sqrt_stepx[9].u_divider_step/N6 ), - .\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N6 (\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N6 ), .clk (clk), .en (rdy_t_alias[7]), .sync_vg_100m (sync_vg_100m)); // ../../sources/designs/adjust_color/divider.v:54 divider_cell_1_unq48 \g_sqrt_stepx[10].u_divider_step ( - .\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45 ({\g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[12]_floating , \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[11]_floating , \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[10]_floating , \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[9]_floating , \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[8]_floating , \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[7]_floating , \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[6]_floating , \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[5]_floating , \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[4]_floating , \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[3]_floating , \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[2]_floating , \g_sqrt_stepx[10].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[1]_floating , \adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45 [0] }), .divisor_kp ({\divisor_t[5] [7] , \divisor_t[5] [6] , \divisor_t[5] [5] , \divisor_t[5] [4] , \divisor_t[5] [3] , \divisor_t[5] [2] , \divisor_t[5] [1] , \divisor_t[5] [0] }), .quotient ({\g_sqrt_stepx[10].u_divider_step_quotient[15]_floating , \g_sqrt_stepx[10].u_divider_step_quotient[14]_floating , \g_sqrt_stepx[10].u_divider_step_quotient[13]_floating , \g_sqrt_stepx[10].u_divider_step_quotient[12]_floating , \g_sqrt_stepx[10].u_divider_step_quotient[11]_floating , \g_sqrt_stepx[10].u_divider_step_quotient[10]_floating , \g_sqrt_stepx[10].u_divider_step_quotient[9]_floating , \g_sqrt_stepx[10].u_divider_step_quotient[8]_floating , \g_sqrt_stepx[10].u_divider_step_quotient[7]_floating , \g_sqrt_stepx[10].u_divider_step_quotient[6]_floating , \g_sqrt_stepx[10].u_divider_step_quotient[5]_floating , \g_sqrt_stepx[10].u_divider_step_quotient[4]_floating , \quotient_t[5] [3] , \quotient_t[5] [2] , \quotient_t[5] [1] , \quotient_t[5] [0] }), .remainder ({\remainder_t[5] [7] , \remainder_t[5] [6] , \remainder_t[5] [5] , \remainder_t[5] [4] , \remainder_t[5] [3] , \remainder_t[5] [2] , \remainder_t[5] [1] , \remainder_t[5] [0] }), - .N45 ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \g_sqrt_stepx[10].u_divider_step/N45 [0] }), .dividend ({\remainder_t[6] [7] , \remainder_t[6] [6] , \remainder_t[6] [5] , \remainder_t[6] [4] , \remainder_t[6] [3] , \remainder_t[6] [2] , \remainder_t[6] [1] , \remainder_t[6] [0] , 1'bx}), .divisor ({\divisor_t[6] [7] , \divisor_t[6] [6] , \divisor_t[6] [5] , \divisor_t[6] [4] , \divisor_t[6] [3] , \divisor_t[6] [2] , \divisor_t[6] [1] , \divisor_t[6] [0] }), .quotient_ci ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \quotient_t[6] [2] , \quotient_t[6] [1] , \quotient_t[6] [0] }), - .N6 (\g_sqrt_stepx[10].u_divider_step/N6 ), - .\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N6 (\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N6 ), .clk (clk), .en (rdy_t_alias[6]), .sync_vg_100m (sync_vg_100m)); // ../../sources/designs/adjust_color/divider.v:54 divider_cell_1_unq50 \g_sqrt_stepx[11].u_divider_step ( - .\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45 ({\g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[12]_floating , \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[11]_floating , \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[10]_floating , \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[9]_floating , \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[8]_floating , \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[7]_floating , \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[6]_floating , \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[5]_floating , \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[4]_floating , \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[3]_floating , \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[2]_floating , \g_sqrt_stepx[11].u_divider_step_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[1]_floating , \adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45 [0] }), .divisor_kp ({\divisor_t[4] [7] , \divisor_t[4] [6] , \divisor_t[4] [5] , \divisor_t[4] [4] , \divisor_t[4] [3] , \divisor_t[4] [2] , \divisor_t[4] [1] , \divisor_t[4] [0] }), .quotient ({\g_sqrt_stepx[11].u_divider_step_quotient[15]_floating , \g_sqrt_stepx[11].u_divider_step_quotient[14]_floating , \g_sqrt_stepx[11].u_divider_step_quotient[13]_floating , \g_sqrt_stepx[11].u_divider_step_quotient[12]_floating , \g_sqrt_stepx[11].u_divider_step_quotient[11]_floating , \g_sqrt_stepx[11].u_divider_step_quotient[10]_floating , \g_sqrt_stepx[11].u_divider_step_quotient[9]_floating , \g_sqrt_stepx[11].u_divider_step_quotient[8]_floating , \g_sqrt_stepx[11].u_divider_step_quotient[7]_floating , \g_sqrt_stepx[11].u_divider_step_quotient[6]_floating , \g_sqrt_stepx[11].u_divider_step_quotient[5]_floating , \quotient_t[4] [4] , \quotient_t[4] [3] , \quotient_t[4] [2] , \quotient_t[4] [1] , \quotient_t[4] [0] }), .remainder ({\remainder_t[4] [7] , \remainder_t[4] [6] , \remainder_t[4] [5] , \remainder_t[4] [4] , \remainder_t[4] [3] , \remainder_t[4] [2] , \remainder_t[4] [1] , \remainder_t[4] [0] }), - .N45 ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \g_sqrt_stepx[11].u_divider_step/N45 [0] }), .dividend ({\remainder_t[5] [7] , \remainder_t[5] [6] , \remainder_t[5] [5] , \remainder_t[5] [4] , \remainder_t[5] [3] , \remainder_t[5] [2] , \remainder_t[5] [1] , \remainder_t[5] [0] , 1'bx}), .divisor ({\divisor_t[5] [7] , \divisor_t[5] [6] , \divisor_t[5] [5] , \divisor_t[5] [4] , \divisor_t[5] [3] , \divisor_t[5] [2] , \divisor_t[5] [1] , \divisor_t[5] [0] }), .quotient_ci ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \quotient_t[5] [3] , \quotient_t[5] [2] , \quotient_t[5] [1] , \quotient_t[5] [0] }), - .N6 (\g_sqrt_stepx[11].u_divider_step/N6 ), - .\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N6 (\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N6 ), .clk (clk), .en (rdy_t_alias[5]), .sync_vg_100m (sync_vg_100m)); @@ -22119,39 +21925,20 @@ module convert_rgb2hsv wire _N11; wire _N12; wire _N13; - wire _N13471; - wire _N13472; wire _N13473; wire _N13474; wire _N13475; wire _N13476; wire _N13477; - wire _N18755; - wire _N18761; - wire _N31924; - wire _N34494; - wire _N35096; - wire _N107206; + wire _N13478; + wire _N13479; + wire _N18737; + wire _N18743; + wire _N108028; wire [7:0] b; wire [7:0] diff_max_min; wire [7:0] diff_med_min; - wire \divider_inst_h/g_sqrt_stepx[8].u_divider_step/N6 ; - wire [12:0] \divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45 ; - wire \divider_inst_h/g_sqrt_stepx[9].u_divider_step/N6 ; - wire [12:0] \divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45 ; - wire \divider_inst_h/g_sqrt_stepx[10].u_divider_step/N6 ; - wire [12:0] \divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45 ; - wire \divider_inst_h/g_sqrt_stepx[11].u_divider_step/N6 ; - wire [12:0] \divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45 ; wire [12:0] \divider_inst_h/rdy_t ; - wire \divider_inst_s/g_sqrt_stepx[8].u_divider_step/N6 ; - wire [15:0] \divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45 ; - wire \divider_inst_s/g_sqrt_stepx[9].u_divider_step/N6 ; - wire [15:0] \divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45 ; - wire \divider_inst_s/g_sqrt_stepx[10].u_divider_step/N6 ; - wire [15:0] \divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45 ; - wire \divider_inst_s/g_sqrt_stepx[11].u_divider_step/N6 ; - wire [15:0] \divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45 ; wire [7:0] divisor_h; wire [2:0] flags; wire [2:0] flags_d0; @@ -22198,120 +21985,12 @@ module convert_rgb2hsv wire [7:0] \v_ff[14] ; wire [7:0] \v_ff[15] ; wire [2:0] valid_ff; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[1]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[2]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[3]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[4]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[5]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[6]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[7]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[8]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[9]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[10]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[11]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[12]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[13]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[14]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[15]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[1]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[2]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[3]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[4]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[5]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[6]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[7]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[8]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[9]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[10]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[11]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[12]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[13]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[14]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[15]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[1]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[2]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[3]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[4]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[5]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[6]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[7]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[8]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[9]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[10]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[11]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[12]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[13]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[14]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[15]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[1]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[2]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[3]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[4]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[5]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[6]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[7]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[8]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[9]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[10]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[11]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[12]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[13]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[14]_floating ; - wire \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[15]_floating ; wire \divider_inst_h_quotient[8]_floating ; wire \divider_inst_h_quotient[9]_floating ; wire \divider_inst_h_quotient[10]_floating ; wire \divider_inst_h_quotient[11]_floating ; wire \divider_inst_h_quotient[12]_floating ; wire \divider_inst_h_rdy_t[0]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[1]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[2]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[3]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[4]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[5]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[6]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[7]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[8]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[9]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[10]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[11]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[12]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[1]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[2]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[3]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[4]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[5]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[6]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[7]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[8]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[9]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[10]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[11]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[12]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[1]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[2]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[3]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[4]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[5]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[6]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[7]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[8]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[9]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[10]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[11]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[12]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[1]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[2]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[3]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[4]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[5]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[6]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[7]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[8]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[9]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[10]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[11]_floating ; - wire \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[12]_floating ; wire \divider_inst_s_quotient[9]_floating ; wire \divider_inst_s_quotient[10]_floating ; wire \divider_inst_s_quotient[11]_floating ; @@ -22963,7 +22642,7 @@ module convert_rgb2hsv GTP_LUT4 /* N133_7 */ #( .INIT(16'b1111111111111110)) N133_7 ( - .Z (_N107206), + .Z (_N108028), .I0 (\v_ff[15] [4] ), .I1 (\v_ff[15] [5] ), .I2 (\v_ff[15] [6] ), @@ -22978,7 +22657,7 @@ module convert_rgb2hsv .I1 (\v_ff[15] [1] ), .I2 (\v_ff[15] [2] ), .I3 (\v_ff[15] [3] ), - .I4 (_N107206)); + .I4 (_N108028)); // LUT = ~I0&~I1&~I2&~I3&~I4 ; GTP_LUT3 /* N140_7 */ #( @@ -23050,6 +22729,18 @@ module convert_rgb2hsv .ID (N7)); // LUT = (~ID&I3&~I4)|(ID&I2&~I4)|(~I0&I3&I4)|(I0&I1&I4) ; + GTP_LUT5M /* \N146_12[5] */ #( + .INIT(32'b11011101100010001111010110100000)) + \N146_12[5] ( + .Z (N146[5]), + .I0 (N15), + .I1 (b[0]), + .I2 (g[5]), + .I3 (r[0]), + .I4 (N23), + .ID (N7)); + // LUT = (~ID&I3&~I4)|(ID&I2&~I4)|(~I0&I3&I4)|(I0&I1&I4) ; + GTP_LUT5M /* \N146_12[6] */ #( .INIT(32'b11011101100010001111010110100000)) \N146_12[6] ( @@ -23077,7 +22768,7 @@ module convert_rgb2hsv GTP_LUT3 /* N153_6 */ #( .INIT(8'b01000010)) N153_6 ( - .Z (_N18755), + .Z (_N18737), .I0 (N7), .I1 (N15), .I2 (N23)); @@ -23086,7 +22777,7 @@ module convert_rgb2hsv GTP_LUT3 /* N153_12 */ #( .INIT(8'b00011000)) N153_12 ( - .Z (_N18761), + .Z (_N18743), .I0 (N7), .I1 (N15), .I2 (N23)); @@ -23099,8 +22790,8 @@ module convert_rgb2hsv .I0 (b[0]), .I1 (g[0]), .I2 (r[0]), - .I3 (_N18755), - .I4 (_N18761)); + .I3 (_N18737), + .I4 (_N18743)); // LUT = (I2&I3)|(I1&~I3&~I4)|(I0&~I3&I4) ; GTP_LUT5 /* \N153_14[1] */ #( @@ -23110,8 +22801,8 @@ module convert_rgb2hsv .I0 (b[1]), .I1 (g[1]), .I2 (r[1]), - .I3 (_N18755), - .I4 (_N18761)); + .I3 (_N18737), + .I4 (_N18743)); // LUT = (I2&I3)|(I1&~I3&~I4)|(I0&~I3&I4) ; GTP_LUT5 /* \N153_14[2] */ #( @@ -23121,8 +22812,8 @@ module convert_rgb2hsv .I0 (b[2]), .I1 (g[2]), .I2 (r[2]), - .I3 (_N18755), - .I4 (_N18761)); + .I3 (_N18737), + .I4 (_N18743)); // LUT = (I2&I3)|(I1&~I3&~I4)|(I0&~I3&I4) ; GTP_LUT5 /* \N153_14[3] */ #( @@ -23132,8 +22823,8 @@ module convert_rgb2hsv .I0 (b[3]), .I1 (g[3]), .I2 (r[3]), - .I3 (_N18755), - .I4 (_N18761)); + .I3 (_N18737), + .I4 (_N18743)); // LUT = (I2&I3)|(I1&~I3&~I4)|(I0&~I3&I4) ; GTP_LUT5 /* \N153_14[4] */ #( @@ -23143,8 +22834,8 @@ module convert_rgb2hsv .I0 (b[4]), .I1 (g[4]), .I2 (r[4]), - .I3 (_N18755), - .I4 (_N18761)); + .I3 (_N18737), + .I4 (_N18743)); // LUT = (I2&I3)|(I1&~I3&~I4)|(I0&~I3&I4) ; GTP_LUT5 /* \N153_14[5] */ #( @@ -23154,8 +22845,8 @@ module convert_rgb2hsv .I0 (b[0]), .I1 (g[5]), .I2 (r[0]), - .I3 (_N18755), - .I4 (_N18761)); + .I3 (_N18737), + .I4 (_N18743)); // LUT = (I2&I3)|(I1&~I3&~I4)|(I0&~I3&I4) ; GTP_LUT5 /* \N153_14[6] */ #( @@ -23165,8 +22856,8 @@ module convert_rgb2hsv .I0 (b[1]), .I1 (g[0]), .I2 (r[1]), - .I3 (_N18755), - .I4 (_N18761)); + .I3 (_N18737), + .I4 (_N18743)); // LUT = (I2&I3)|(I1&~I3&~I4)|(I0&~I3&I4) ; GTP_LUT5 /* \N153_14[7] */ #( @@ -23176,8 +22867,8 @@ module convert_rgb2hsv .I0 (b[2]), .I1 (g[1]), .I2 (r[2]), - .I3 (_N18755), - .I4 (_N18761)); + .I3 (_N18737), + .I4 (_N18743)); // LUT = (I2&I3)|(I1&~I3&~I4)|(I0&~I3&I4) ; GTP_LUT5M /* \N160_12[0] */ #( @@ -23204,6 +22895,18 @@ module convert_rgb2hsv .ID (N23)); // LUT = (ID&I2&~I4)|(~ID&I1&~I4)|(I0&I3&I4)|(~I0&I1&I4) ; + GTP_LUT5M /* \N160_12[2] */ #( + .INIT(32'b11101110010001001110010011100100)) + \N160_12[2] ( + .Z (N160[2]), + .I0 (N15), + .I1 (b[2]), + .I2 (g[2]), + .I3 (r[2]), + .I4 (N7), + .ID (N23)); + // LUT = (ID&I2&~I4)|(~ID&I1&~I4)|(I0&I3&I4)|(~I0&I1&I4) ; + GTP_LUT5M /* \N160_12[3] */ #( .INIT(32'b11101110010001001110010011100100)) \N160_12[3] ( @@ -23240,6 +22943,18 @@ module convert_rgb2hsv .ID (N23)); // LUT = (ID&I2&~I4)|(~ID&I1&~I4)|(I0&I3&I4)|(~I0&I1&I4) ; + GTP_LUT5M /* \N160_12[6] */ #( + .INIT(32'b11101110010001001110010011100100)) + \N160_12[6] ( + .Z (N160[6]), + .I0 (N15), + .I1 (b[1]), + .I2 (g[0]), + .I3 (r[1]), + .I4 (N7), + .ID (N23)); + // LUT = (ID&I2&~I4)|(~ID&I1&~I4)|(I0&I3&I4)|(~I0&I1&I4) ; + GTP_LUT5M /* \N160_12[7] */ #( .INIT(32'b11101110010001001110010011100100)) \N160_12[7] ( @@ -23286,7 +23001,7 @@ module convert_rgb2hsv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N167_3_1 ( - .COUT (_N13471), + .COUT (_N13473), .Z (), .CIN (), .I0 (\flags_ff[13] [0] ), @@ -23305,9 +23020,9 @@ module convert_rgb2hsv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N167_3_2 ( - .COUT (_N13472), + .COUT (_N13474), .Z (N167[1]), - .CIN (_N13471), + .CIN (_N13473), .I0 (\flags_ff[13] [0] ), .I1 (h_part2[0]), .I2 (h_part2[1]), @@ -23324,9 +23039,9 @@ module convert_rgb2hsv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N167_3_3 ( - .COUT (_N13473), + .COUT (_N13475), .Z (N167[2]), - .CIN (_N13472), + .CIN (_N13474), .I0 (), .I1 (\flags_ff[13] [0] ), .I2 (h_part2[2]), @@ -23343,9 +23058,9 @@ module convert_rgb2hsv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N167_3_4 ( - .COUT (_N13474), + .COUT (_N13476), .Z (N167[3]), - .CIN (_N13473), + .CIN (_N13475), .I0 (), .I1 (\flags_ff[13] [0] ), .I2 (h_part2[3]), @@ -23362,9 +23077,9 @@ module convert_rgb2hsv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N167_3_5 ( - .COUT (_N13475), + .COUT (_N13477), .Z (N167[4]), - .CIN (_N13474), + .CIN (_N13476), .I0 (), .I1 (\flags_ff[13] [0] ), .I2 (h_part2[4]), @@ -23381,9 +23096,9 @@ module convert_rgb2hsv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N167_3_6 ( - .COUT (_N13476), + .COUT (_N13478), .Z (N167[5]), - .CIN (_N13475), + .CIN (_N13477), .I0 (), .I1 (\flags_ff[13] [0] ), .I2 (h_part2[5]), @@ -23400,9 +23115,9 @@ module convert_rgb2hsv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N167_3_7 ( - .COUT (_N13477), + .COUT (_N13479), .Z (N167[6]), - .CIN (_N13476), + .CIN (_N13478), .I0 (), .I1 (h_part1[6]), .I2 (\flags_ff[13] [0] ), @@ -23421,7 +23136,7 @@ module convert_rgb2hsv N167_3_8 ( .COUT (), .Z (N167[7]), - .CIN (_N13477), + .CIN (_N13479), .I0 (), .I1 (h_part1[7]), .I2 (\flags_ff[13] [0] ), @@ -23621,52 +23336,20 @@ module convert_rgb2hsv // ../../sources/designs/adjust_color/convert_rgb2hsv.v:94 divider divider_inst_h ( - .\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45 ({\divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[15]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[14]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[13]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[12]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[11]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[10]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[9]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[8]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[7]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[6]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[5]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[4]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[3]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[2]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45[1]_floating , \divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45 [0] }), - .\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45 ({\divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[15]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[14]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[13]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[12]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[11]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[10]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[9]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[8]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[7]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[6]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[5]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[4]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[3]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[2]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45[1]_floating , \divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45 [0] }), - .\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45 ({\divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[15]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[14]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[13]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[12]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[11]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[10]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[9]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[8]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[7]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[6]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[5]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[4]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[3]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[2]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45[1]_floating , \divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45 [0] }), - .\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45 ({\divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[15]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[14]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[13]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[12]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[11]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[10]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[9]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[8]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[7]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[6]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[5]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[4]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[3]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[2]_floating , \divider_inst_h_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45[1]_floating , \divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45 [0] }), .quotient ({\divider_inst_h_quotient[12]_floating , \divider_inst_h_quotient[11]_floating , \divider_inst_h_quotient[10]_floating , \divider_inst_h_quotient[9]_floating , \divider_inst_h_quotient[8]_floating , quotient_h[7], quotient_h[6], quotient_h[5], quotient_h[4], quotient_h[3], quotient_h[2], quotient_h[1], quotient_h[0]}), .rdy_t ({\divider_inst_h/rdy_t [12] , \divider_inst_h/rdy_t [11] , \divider_inst_h/rdy_t [10] , \divider_inst_h/rdy_t [9] , \divider_inst_h/rdy_t [8] , \divider_inst_h/rdy_t [7] , \divider_inst_h/rdy_t [6] , \divider_inst_h/rdy_t [5] , \divider_inst_h/rdy_t [4] , \divider_inst_h/rdy_t [3] , \divider_inst_h/rdy_t [2] , \divider_inst_h/rdy_t [1] , \divider_inst_h_rdy_t[0]_floating }), .dividend ({diff_med_min[7], diff_med_min[6], diff_med_min[5], diff_med_min[4], diff_med_min[3], diff_med_min[2], diff_med_min[1], diff_med_min[0], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), .divisor (divisor_h), - .\g_sqrt_stepx[8].u_divider_step/N45 ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45 [0] }), - .\g_sqrt_stepx[9].u_divider_step/N45 ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45 [0] }), - .\g_sqrt_stepx[10].u_divider_step/N45 ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45 [0] }), - .\g_sqrt_stepx[11].u_divider_step/N45 ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45 [0] }), - .\g_sqrt_stepx[8].u_divider_step/N6 (\divider_inst_h/g_sqrt_stepx[8].u_divider_step/N6 ), - .\g_sqrt_stepx[9].u_divider_step/N6 (\divider_inst_h/g_sqrt_stepx[9].u_divider_step/N6 ), - .\g_sqrt_stepx[10].u_divider_step/N6 (\divider_inst_h/g_sqrt_stepx[10].u_divider_step/N6 ), - .\g_sqrt_stepx[11].u_divider_step/N6 (\divider_inst_h/g_sqrt_stepx[11].u_divider_step/N6 ), - .\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[8].u_divider_step/N6 (\divider_inst_s/g_sqrt_stepx[8].u_divider_step/N6 ), - .\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[9].u_divider_step/N6 (\divider_inst_s/g_sqrt_stepx[9].u_divider_step/N6 ), - .\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/N6 (\divider_inst_s/g_sqrt_stepx[10].u_divider_step/N6 ), - .\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/N6 (\divider_inst_s/g_sqrt_stepx[11].u_divider_step/N6 ), .clk (clk), .in_valid (valid_ff[2]), .sync_vg_100m (sync_vg_100m)); // ../../sources/designs/adjust_color/convert_rgb2hsv.v:136 divider_1 divider_inst_s ( - .\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45 ({\divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[12]_floating , \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[11]_floating , \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[10]_floating , \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[9]_floating , \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[8]_floating , \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[7]_floating , \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[6]_floating , \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[5]_floating , \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[4]_floating , \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[3]_floating , \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[2]_floating , \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45[1]_floating , \divider_inst_h/g_sqrt_stepx[8].u_divider_step/N45 [0] }), - .\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45 ({\divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[12]_floating , \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[11]_floating , \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[10]_floating , \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[9]_floating , \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[8]_floating , \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[7]_floating , \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[6]_floating , \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[5]_floating , \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[4]_floating , \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[3]_floating , \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[2]_floating , \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45[1]_floating , \divider_inst_h/g_sqrt_stepx[9].u_divider_step/N45 [0] }), - .\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45 ({\divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[12]_floating , \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[11]_floating , \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[10]_floating , \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[9]_floating , \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[8]_floating , \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[7]_floating , \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[6]_floating , \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[5]_floating , \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[4]_floating , \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[3]_floating , \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[2]_floating , \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45[1]_floating , \divider_inst_h/g_sqrt_stepx[10].u_divider_step/N45 [0] }), - .\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45 ({\divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[12]_floating , \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[11]_floating , \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[10]_floating , \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[9]_floating , \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[8]_floating , \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[7]_floating , \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[6]_floating , \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[5]_floating , \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[4]_floating , \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[3]_floating , \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[2]_floating , \divider_inst_s_adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45[1]_floating , \divider_inst_h/g_sqrt_stepx[11].u_divider_step/N45 [0] }), .quotient ({\divider_inst_s_quotient[15]_floating , \divider_inst_s_quotient[14]_floating , \divider_inst_s_quotient[13]_floating , \divider_inst_s_quotient[12]_floating , \divider_inst_s_quotient[11]_floating , \divider_inst_s_quotient[10]_floating , \divider_inst_s_quotient[9]_floating , quotient_s[8], quotient_s[7], quotient_s[6], quotient_s[5], quotient_s[4], quotient_s[3], quotient_s[2], quotient_s[1], quotient_s[0]}), .dividend ({diff_max_min[7], diff_max_min[6], diff_max_min[5], diff_max_min[4], diff_max_min[3], diff_max_min[2], diff_max_min[1], diff_max_min[0], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), .divisor (max_d0), - .\g_sqrt_stepx[8].u_divider_step/N45 ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \divider_inst_s/g_sqrt_stepx[8].u_divider_step/N45 [0] }), - .\g_sqrt_stepx[9].u_divider_step/N45 ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \divider_inst_s/g_sqrt_stepx[9].u_divider_step/N45 [0] }), - .\g_sqrt_stepx[10].u_divider_step/N45 ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \divider_inst_s/g_sqrt_stepx[10].u_divider_step/N45 [0] }), - .\g_sqrt_stepx[11].u_divider_step/N45 ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \divider_inst_s/g_sqrt_stepx[11].u_divider_step/N45 [0] }), .rdy_t ({\divider_inst_h/rdy_t [12] , \divider_inst_h/rdy_t [11] , \divider_inst_h/rdy_t [10] , \divider_inst_h/rdy_t [9] , \divider_inst_h/rdy_t [8] , \divider_inst_h/rdy_t [7] , \divider_inst_h/rdy_t [6] , \divider_inst_h/rdy_t [5] , \divider_inst_h/rdy_t [4] , \divider_inst_h/rdy_t [3] , \divider_inst_h/rdy_t [2] , \divider_inst_h/rdy_t [1] , 1'bx, 1'bx, 1'bx, 1'bx}), - .\g_sqrt_stepx[8].u_divider_step/N6 (\divider_inst_s/g_sqrt_stepx[8].u_divider_step/N6 ), - .\g_sqrt_stepx[9].u_divider_step/N6 (\divider_inst_s/g_sqrt_stepx[9].u_divider_step/N6 ), - .\g_sqrt_stepx[10].u_divider_step/N6 (\divider_inst_s/g_sqrt_stepx[10].u_divider_step/N6 ), - .\g_sqrt_stepx[11].u_divider_step/N6 (\divider_inst_s/g_sqrt_stepx[11].u_divider_step/N6 ), - .\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/N6 (\divider_inst_h/g_sqrt_stepx[8].u_divider_step/N6 ), - .\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/N6 (\divider_inst_h/g_sqrt_stepx[9].u_divider_step/N6 ), - .\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/N6 (\divider_inst_h/g_sqrt_stepx[10].u_divider_step/N6 ), - .\adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/N6 (\divider_inst_h/g_sqrt_stepx[11].u_divider_step/N6 ), .clk (clk), .in_valid (valid_ff[2]), .sync_vg_100m (sync_vg_100m)); @@ -24586,7 +24269,7 @@ module convert_rgb2hsv .Q (max[5]), .CE (N140), .CLK (clk), - .D (_N31924)); + .D (N146[5])); // ../../sources/designs/adjust_color/convert_rgb2hsv.v:38 GTP_DFF_E /* \max[6] */ #( @@ -24599,18 +24282,6 @@ module convert_rgb2hsv .D (N146[6])); // ../../sources/designs/adjust_color/convert_rgb2hsv.v:38 - GTP_LUT5M /* \max[7:0]_0 */ #( - .INIT(32'b11011101100010001111010110100000)) - \max[7:0]_0 ( - .Z (_N31924), - .I0 (N15), - .I1 (b[0]), - .I2 (g[5]), - .I3 (r[0]), - .I4 (N23), - .ID (N7)); - // LUT = (~ID&I3&~I4)|(ID&I2&~I4)|(~I0&I3&I4)|(I0&I1&I4) ; - GTP_DFF_E /* \max[7] */ #( .GRS_EN("TRUE"), .INIT(1'b0)) @@ -24800,7 +24471,7 @@ module convert_rgb2hsv .Q (min[2]), .CE (N140), .CLK (clk), - .D (_N34494)); + .D (N160[2])); // ../../sources/designs/adjust_color/convert_rgb2hsv.v:38 GTP_DFF_E /* \min[3] */ #( @@ -24840,33 +24511,9 @@ module convert_rgb2hsv .Q (min[6]), .CE (N140), .CLK (clk), - .D (_N35096)); + .D (N160[6])); // ../../sources/designs/adjust_color/convert_rgb2hsv.v:38 - GTP_LUT5M /* \min[7:0]_3 */ #( - .INIT(32'b11101110010001001110010011100100)) - \min[7:0]_3 ( - .Z (_N34494), - .I0 (N15), - .I1 (b[2]), - .I2 (g[2]), - .I3 (r[2]), - .I4 (N7), - .ID (N23)); - // LUT = (ID&I2&~I4)|(~ID&I1&~I4)|(I0&I3&I4)|(~I0&I1&I4) ; - - GTP_LUT5M /* \min[7:0]_325 */ #( - .INIT(32'b11101110010001001110010011100100)) - \min[7:0]_325 ( - .Z (_N35096), - .I0 (N15), - .I1 (b[1]), - .I2 (g[0]), - .I3 (r[1]), - .I4 (N7), - .ID (N23)); - // LUT = (ID&I2&~I4)|(~ID&I1&~I4)|(I0&I3&I4)|(~I0&I1&I4) ; - GTP_DFF_E /* \min[7] */ #( .GRS_EN("TRUE"), .INIT(1'b0)) @@ -26346,8 +25993,6 @@ module hsv_modify wire [7:0] N80; wire [7:0] N84; wire [7:0] N87; - wire _N13421; - wire _N13422; wire _N13423; wire _N13424; wire _N13425; @@ -26355,8 +26000,8 @@ module hsv_modify wire _N13427; wire _N13428; wire _N13429; - wire _N13432; - wire _N13433; + wire _N13430; + wire _N13431; wire _N13434; wire _N13435; wire _N13436; @@ -26364,8 +26009,8 @@ module hsv_modify wire _N13438; wire _N13439; wire _N13440; - wire _N13443; - wire _N13444; + wire _N13441; + wire _N13442; wire _N13445; wire _N13446; wire _N13447; @@ -26373,7 +26018,9 @@ module hsv_modify wire _N13449; wire _N13450; wire _N13451; - wire _N107220; + wire _N13452; + wire _N13453; + wire _N108042; wire [9:0] h_sum; wire [9:0] s_sum; wire [9:0] v_sum; @@ -26385,7 +26032,7 @@ module hsv_modify .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1 ( - .COUT (_N13421), + .COUT (_N13423), .Z (N17[0]), .CIN (), .I0 (raw_h_data[0]), @@ -26405,9 +26052,9 @@ module hsv_modify .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_2 ( - .COUT (_N13422), + .COUT (_N13424), .Z (N17[1]), - .CIN (_N13421), + .CIN (_N13423), .I0 (raw_h_data[0]), .I1 (modify_h[0]), .I2 (raw_h_data[1]), @@ -26425,9 +26072,9 @@ module hsv_modify .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_3 ( - .COUT (_N13423), + .COUT (_N13425), .Z (N17[2]), - .CIN (_N13422), + .CIN (_N13424), .I0 (), .I1 (raw_h_data[2]), .I2 (modify_h[2]), @@ -26445,9 +26092,9 @@ module hsv_modify .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_4 ( - .COUT (_N13424), + .COUT (_N13426), .Z (N17[3]), - .CIN (_N13423), + .CIN (_N13425), .I0 (), .I1 (raw_h_data[3]), .I2 (modify_h[3]), @@ -26465,9 +26112,9 @@ module hsv_modify .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_5 ( - .COUT (_N13425), + .COUT (_N13427), .Z (N17[4]), - .CIN (_N13424), + .CIN (_N13426), .I0 (), .I1 (raw_h_data[4]), .I2 (modify_h[4]), @@ -26485,9 +26132,9 @@ module hsv_modify .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_6 ( - .COUT (_N13426), + .COUT (_N13428), .Z (N17[5]), - .CIN (_N13425), + .CIN (_N13427), .I0 (), .I1 (raw_h_data[5]), .I2 (modify_h[5]), @@ -26505,9 +26152,9 @@ module hsv_modify .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_7 ( - .COUT (_N13427), + .COUT (_N13429), .Z (N17[6]), - .CIN (_N13426), + .CIN (_N13428), .I0 (), .I1 (raw_h_data[6]), .I2 (modify_h[6]), @@ -26525,9 +26172,9 @@ module hsv_modify .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_8 ( - .COUT (_N13428), + .COUT (_N13430), .Z (N17[7]), - .CIN (_N13427), + .CIN (_N13429), .I0 (), .I1 (raw_h_data[7]), .I2 (modify_h[7]), @@ -26545,9 +26192,9 @@ module hsv_modify .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_9 ( - .COUT (_N13429), + .COUT (_N13431), .Z (N17[8]), - .CIN (_N13428), + .CIN (_N13430), .I0 (), .I1 (modify_h[8]), .I2 (), @@ -26567,7 +26214,7 @@ module hsv_modify N17_10 ( .COUT (), .Z (N17[9]), - .CIN (_N13429), + .CIN (_N13431), .I0 (), .I1 (modify_h[8]), .I2 (), @@ -26585,7 +26232,7 @@ module hsv_modify .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N24_1 ( - .COUT (_N13432), + .COUT (_N13434), .Z (N24[0]), .CIN (), .I0 (raw_s_data[0]), @@ -26605,9 +26252,9 @@ module hsv_modify .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N24_2 ( - .COUT (_N13433), + .COUT (_N13435), .Z (N24[1]), - .CIN (_N13432), + .CIN (_N13434), .I0 (raw_s_data[0]), .I1 (modify_s[0]), .I2 (raw_s_data[1]), @@ -26625,9 +26272,9 @@ module hsv_modify .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N24_3 ( - .COUT (_N13434), + .COUT (_N13436), .Z (N24[2]), - .CIN (_N13433), + .CIN (_N13435), .I0 (), .I1 (raw_s_data[2]), .I2 (modify_s[2]), @@ -26645,9 +26292,9 @@ module hsv_modify .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N24_4 ( - .COUT (_N13435), + .COUT (_N13437), .Z (N24[3]), - .CIN (_N13434), + .CIN (_N13436), .I0 (), .I1 (raw_s_data[3]), .I2 (modify_s[3]), @@ -26665,9 +26312,9 @@ module hsv_modify .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N24_5 ( - .COUT (_N13436), + .COUT (_N13438), .Z (N24[4]), - .CIN (_N13435), + .CIN (_N13437), .I0 (), .I1 (raw_s_data[4]), .I2 (modify_s[4]), @@ -26685,9 +26332,9 @@ module hsv_modify .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N24_6 ( - .COUT (_N13437), + .COUT (_N13439), .Z (N24[5]), - .CIN (_N13436), + .CIN (_N13438), .I0 (), .I1 (raw_s_data[5]), .I2 (modify_s[5]), @@ -26705,9 +26352,9 @@ module hsv_modify .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N24_7 ( - .COUT (_N13438), + .COUT (_N13440), .Z (N24[6]), - .CIN (_N13437), + .CIN (_N13439), .I0 (), .I1 (raw_s_data[6]), .I2 (modify_s[6]), @@ -26725,9 +26372,9 @@ module hsv_modify .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N24_8 ( - .COUT (_N13439), + .COUT (_N13441), .Z (N24[7]), - .CIN (_N13438), + .CIN (_N13440), .I0 (), .I1 (raw_s_data[7]), .I2 (modify_s[7]), @@ -26745,9 +26392,9 @@ module hsv_modify .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N24_9 ( - .COUT (_N13440), + .COUT (_N13442), .Z (N24[8]), - .CIN (_N13439), + .CIN (_N13441), .I0 (), .I1 (modify_s[8]), .I2 (), @@ -26767,7 +26414,7 @@ module hsv_modify N24_10 ( .COUT (), .Z (N24[9]), - .CIN (_N13440), + .CIN (_N13442), .I0 (), .I1 (modify_s[8]), .I2 (), @@ -26785,7 +26432,7 @@ module hsv_modify .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_1 ( - .COUT (_N13443), + .COUT (_N13445), .Z (N26[0]), .CIN (), .I0 (raw_v_data[0]), @@ -26805,9 +26452,9 @@ module hsv_modify .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_2 ( - .COUT (_N13444), + .COUT (_N13446), .Z (N26[1]), - .CIN (_N13443), + .CIN (_N13445), .I0 (raw_v_data[0]), .I1 (modify_v[0]), .I2 (raw_v_data[1]), @@ -26825,9 +26472,9 @@ module hsv_modify .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_3 ( - .COUT (_N13445), + .COUT (_N13447), .Z (N26[2]), - .CIN (_N13444), + .CIN (_N13446), .I0 (), .I1 (raw_v_data[2]), .I2 (modify_v[2]), @@ -26845,9 +26492,9 @@ module hsv_modify .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_4 ( - .COUT (_N13446), + .COUT (_N13448), .Z (N26[3]), - .CIN (_N13445), + .CIN (_N13447), .I0 (), .I1 (raw_v_data[3]), .I2 (modify_v[3]), @@ -26865,9 +26512,9 @@ module hsv_modify .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_5 ( - .COUT (_N13447), + .COUT (_N13449), .Z (N26[4]), - .CIN (_N13446), + .CIN (_N13448), .I0 (), .I1 (raw_v_data[4]), .I2 (modify_v[4]), @@ -26885,9 +26532,9 @@ module hsv_modify .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_6 ( - .COUT (_N13448), + .COUT (_N13450), .Z (N26[5]), - .CIN (_N13447), + .CIN (_N13449), .I0 (), .I1 (raw_v_data[5]), .I2 (modify_v[5]), @@ -26905,9 +26552,9 @@ module hsv_modify .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_7 ( - .COUT (_N13449), + .COUT (_N13451), .Z (N26[6]), - .CIN (_N13448), + .CIN (_N13450), .I0 (), .I1 (raw_v_data[6]), .I2 (modify_v[6]), @@ -26925,9 +26572,9 @@ module hsv_modify .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_8 ( - .COUT (_N13450), + .COUT (_N13452), .Z (N26[7]), - .CIN (_N13449), + .CIN (_N13451), .I0 (), .I1 (raw_v_data[7]), .I2 (modify_v[7]), @@ -26945,9 +26592,9 @@ module hsv_modify .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_9 ( - .COUT (_N13451), + .COUT (_N13453), .Z (N26[8]), - .CIN (_N13450), + .CIN (_N13452), .I0 (), .I1 (modify_v[8]), .I2 (), @@ -26967,7 +26614,7 @@ module hsv_modify N26_10 ( .COUT (), .Z (N26[9]), - .CIN (_N13451), + .CIN (_N13453), .I0 (), .I1 (modify_v[8]), .I2 (), @@ -26997,7 +26644,7 @@ module hsv_modify GTP_LUT4 /* N76_7 */ #( .INIT(16'b1111111111111110)) N76_7 ( - .Z (_N107220), + .Z (_N108042), .I0 (raw_s_data[4]), .I1 (raw_s_data[5]), .I2 (raw_s_data[6]), @@ -27012,7 +26659,7 @@ module hsv_modify .I1 (raw_s_data[1]), .I2 (raw_s_data[2]), .I3 (raw_s_data[3]), - .I4 (_N107220)); + .I4 (_N108042)); // LUT = ~I0&~I1&~I2&~I3&~I4 ; GTP_LUT4 /* N80_6_sum0_1 */ #( @@ -28599,54 +28246,54 @@ module gaussian_conv wire [5:0] N72; wire [6:0] N77; wire [6:0] N78; - wire _N6626; - wire _N6634; - wire _N6639; - wire _N13904; - wire _N13905; - wire _N13906; - wire _N13907; - wire _N13908; - wire _N13909; - wire _N15231; - wire _N15232; - wire _N15233; - wire _N15234; - wire _N15235; - wire _N15236; - wire _N15239; - wire _N15240; - wire _N15241; - wire _N15242; - wire _N15243; - wire _N15244; - wire _N15338; - wire _N15339; - wire _N15340; - wire _N15341; - wire _N15342; - wire _N15343; - wire _N15344; - wire _N15367; - wire _N15368; - wire _N15369; - wire _N15370; - wire _N15371; - wire _N15382; - wire _N15383; - wire _N15384; - wire _N15385; - wire _N15386; - wire _N15409; - wire _N15410; - wire _N15411; - wire _N15412; - wire _N15413; - wire _N15424; - wire _N15425; - wire _N15426; - wire _N15427; - wire _N15428; + wire _N8303; + wire _N8311; + wire _N8316; + wire _N15460; + wire _N15461; + wire _N15462; + wire _N15463; + wire _N15464; + wire _N15465; + wire _N15498; + wire _N15499; + wire _N15500; + wire _N15501; + wire _N15502; + wire _N15503; + wire _N15506; + wire _N15507; + wire _N15508; + wire _N15509; + wire _N15510; + wire _N15511; + wire _N15534; + wire _N15535; + wire _N15536; + wire _N15537; + wire _N15538; + wire _N15539; + wire _N15540; + wire _N15543; + wire _N15544; + wire _N15545; + wire _N15546; + wire _N15547; + wire _N15550; + wire _N15551; + wire _N15552; + wire _N15553; + wire _N15554; + wire _N15557; + wire _N15558; + wire _N15559; + wire _N15560; + wire _N15561; + wire _N15596; + wire _N15597; + wire _N15598; + wire _N15599; + wire _N15600; wire [8:0] product4x2; wire [8:0] sum1x4; wire [8:0] sum4x1; @@ -28660,7 +28307,7 @@ module gaussian_conv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_1 ( - .COUT (_N15231), + .COUT (_N15498), .Z (), .CIN (), .I0 (), @@ -28680,9 +28327,9 @@ module gaussian_conv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_2 ( - .COUT (_N15232), + .COUT (_N15499), .Z (N78[1]), - .CIN (_N15231), + .CIN (_N15498), .I0 (N64[0]), .I1 (N61[0]), .I2 (N64[1]), @@ -28700,9 +28347,9 @@ module gaussian_conv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_3 ( - .COUT (_N15233), + .COUT (_N15500), .Z (N78[2]), - .CIN (_N15232), + .CIN (_N15499), .I0 (), .I1 (N64[2]), .I2 (N61[2]), @@ -28720,9 +28367,9 @@ module gaussian_conv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_4 ( - .COUT (_N15234), + .COUT (_N15501), .Z (N78[3]), - .CIN (_N15233), + .CIN (_N15500), .I0 (), .I1 (N64[3]), .I2 (N61[3]), @@ -28740,9 +28387,9 @@ module gaussian_conv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_5 ( - .COUT (_N15235), + .COUT (_N15502), .Z (N78[4]), - .CIN (_N15234), + .CIN (_N15501), .I0 (), .I1 (N64[4]), .I2 (N61[4]), @@ -28760,9 +28407,9 @@ module gaussian_conv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_6 ( - .COUT (_N15236), + .COUT (_N15503), .Z (N78[5]), - .CIN (_N15235), + .CIN (_N15502), .I0 (), .I1 (N64[5]), .I2 (N61[5]), @@ -28782,7 +28429,7 @@ module gaussian_conv N17_1_7 ( .COUT (), .Z (N78[6]), - .CIN (_N15236), + .CIN (_N15503), .I0 (), .I1 (), .I2 (), @@ -28800,7 +28447,7 @@ module gaussian_conv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_1_1 ( - .COUT (_N15239), + .COUT (_N15506), .Z (N77[0]), .CIN (), .I0 (N72[0]), @@ -28820,9 +28467,9 @@ module gaussian_conv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_1_2 ( - .COUT (_N15240), + .COUT (_N15507), .Z (N77[1]), - .CIN (_N15239), + .CIN (_N15506), .I0 (N72[0]), .I1 (N69[0]), .I2 (N72[1]), @@ -28840,9 +28487,9 @@ module gaussian_conv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_1_3 ( - .COUT (_N15241), + .COUT (_N15508), .Z (N77[2]), - .CIN (_N15240), + .CIN (_N15507), .I0 (), .I1 (N72[2]), .I2 (N69[2]), @@ -28860,9 +28507,9 @@ module gaussian_conv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_1_4 ( - .COUT (_N15242), + .COUT (_N15509), .Z (N77[3]), - .CIN (_N15241), + .CIN (_N15508), .I0 (), .I1 (N72[3]), .I2 (N69[3]), @@ -28880,9 +28527,9 @@ module gaussian_conv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_1_5 ( - .COUT (_N15243), + .COUT (_N15510), .Z (N77[4]), - .CIN (_N15242), + .CIN (_N15509), .I0 (), .I1 (N72[4]), .I2 (N69[4]), @@ -28900,9 +28547,9 @@ module gaussian_conv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_1_6 ( - .COUT (_N15244), + .COUT (_N15511), .Z (N77[5]), - .CIN (_N15243), + .CIN (_N15510), .I0 (), .I1 (N72[5]), .I2 (N69[5]), @@ -28922,7 +28569,7 @@ module gaussian_conv N26_1_7 ( .COUT (), .Z (N77[6]), - .CIN (_N15244), + .CIN (_N15511), .I0 (), .I1 (), .I2 (), @@ -28936,7 +28583,7 @@ module gaussian_conv GTP_LUT2 /* N39_0_ac4 */ #( .INIT(4'b1000)) N39_0_ac4 ( - .Z (_N6634), + .Z (_N8311), .I0 (sum1x4[4]), .I1 (sum4x1[4])); // LUT = I0&I1 ; @@ -28944,7 +28591,7 @@ module gaussian_conv GTP_LUT2 /* N39_0_ac5 */ #( .INIT(4'b1000)) N39_0_ac5 ( - .Z (_N6639), + .Z (_N8316), .I0 (sum1x4[5]), .I1 (sum4x1[5])); // LUT = I0&I1 ; @@ -28952,7 +28599,7 @@ module gaussian_conv GTP_LUT2 /* N39_0_maj3 */ #( .INIT(4'b1110)) N39_0_maj3 ( - .Z (_N6626), + .Z (_N8303), .I0 (sum1x4[3]), .I1 (sum4x1[3])); // LUT = (I0)|(I1) ; @@ -28964,7 +28611,7 @@ module gaussian_conv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_3_1 ( - .COUT (_N13904), + .COUT (_N15460), .Z (N59[2]), .CIN (), .I0 (sum4x1[2]), @@ -28983,9 +28630,9 @@ module gaussian_conv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_3_2 ( - .COUT (_N13905), + .COUT (_N15461), .Z (N59[3]), - .CIN (_N13904), + .CIN (_N15460), .I0 (sum4x1[2]), .I1 (sum1x4[2]), .I2 (sum1x4[3]), @@ -29002,14 +28649,14 @@ module gaussian_conv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_3_3 ( - .COUT (_N13906), + .COUT (_N15462), .Z (N59[4]), - .CIN (_N13905), + .CIN (_N15461), .I0 (), .I1 (sum1x4[4]), - .I2 (_N6626), + .I2 (_N8303), .I3 (sum4x1[4]), - .I4 (_N6626), + .I4 (_N8303), .ID ()); // LUT = I3^I2^I1^CIN ; // CARRY = (I3^I2^I1) ? CIN : (I4) ; @@ -29021,14 +28668,14 @@ module gaussian_conv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_3_4 ( - .COUT (_N13907), + .COUT (_N15463), .Z (N59[5]), - .CIN (_N13906), + .CIN (_N15462), .I0 (), .I1 (sum1x4[5]), - .I2 (_N6634), + .I2 (_N8311), .I3 (sum4x1[5]), - .I4 (_N6634), + .I4 (_N8311), .ID ()); // LUT = I3^I2^I1^CIN ; // CARRY = (I3^I2^I1) ? CIN : (I4) ; @@ -29040,14 +28687,14 @@ module gaussian_conv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_3_5 ( - .COUT (_N13908), + .COUT (_N15464), .Z (N59[6]), - .CIN (_N13907), + .CIN (_N15463), .I0 (), .I1 (sum1x4[6]), - .I2 (_N6639), + .I2 (_N8316), .I3 (sum4x1[6]), - .I4 (_N6639), + .I4 (_N8316), .ID ()); // LUT = I3^I2^I1^CIN ; // CARRY = (I3^I2^I1) ? CIN : (I4) ; @@ -29059,9 +28706,9 @@ module gaussian_conv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_3_6 ( - .COUT (_N13909), + .COUT (_N15465), .Z (N59[7]), - .CIN (_N13908), + .CIN (_N15464), .I0 (), .I1 (sum1x4[6]), .I2 (sum4x1[6]), @@ -29080,7 +28727,7 @@ module gaussian_conv N39_3_7 ( .COUT (), .Z (N59[8]), - .CIN (_N13909), + .CIN (_N15465), .I0 (), .I1 (), .I2 (), @@ -29097,7 +28744,7 @@ module gaussian_conv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N47_1_1 ( - .COUT (_N15338), + .COUT (_N15534), .Z (), .CIN (), .I0 (), @@ -29117,9 +28764,9 @@ module gaussian_conv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N47_1_2 ( - .COUT (_N15339), + .COUT (_N15535), .Z (), - .CIN (_N15338), + .CIN (_N15534), .I0 (sum8[1]), .I1 (product4x2[1]), .I2 (sum8[2]), @@ -29137,9 +28784,9 @@ module gaussian_conv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N47_1_3 ( - .COUT (_N15340), + .COUT (_N15536), .Z (), - .CIN (_N15339), + .CIN (_N15535), .I0 (), .I1 (sum8[3]), .I2 (product4x2[3]), @@ -29157,9 +28804,9 @@ module gaussian_conv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N47_1_4 ( - .COUT (_N15341), + .COUT (_N15537), .Z (N47[4]), - .CIN (_N15340), + .CIN (_N15536), .I0 (), .I1 (sum8[4]), .I2 (product4x2[4]), @@ -29177,9 +28824,9 @@ module gaussian_conv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N47_1_5 ( - .COUT (_N15342), + .COUT (_N15538), .Z (N47[5]), - .CIN (_N15341), + .CIN (_N15537), .I0 (), .I1 (sum8[5]), .I2 (product4x2[5]), @@ -29197,9 +28844,9 @@ module gaussian_conv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N47_1_6 ( - .COUT (_N15343), + .COUT (_N15539), .Z (N47[6]), - .CIN (_N15342), + .CIN (_N15538), .I0 (), .I1 (sum8[6]), .I2 (product4x2[6]), @@ -29217,9 +28864,9 @@ module gaussian_conv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N47_1_7 ( - .COUT (_N15344), + .COUT (_N15540), .Z (N47[7]), - .CIN (_N15343), + .CIN (_N15539), .I0 (), .I1 (sum8[7]), .I2 (product4x2[7]), @@ -29239,7 +28886,7 @@ module gaussian_conv N47_1_8 ( .COUT (), .Z (N47[8]), - .CIN (_N15344), + .CIN (_N15540), .I0 (), .I1 (sum8[8]), .I2 (), @@ -29257,7 +28904,7 @@ module gaussian_conv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N61_1 ( - .COUT (_N15367), + .COUT (_N15543), .Z (N61[0]), .CIN (), .I0 (\mat[0][2] [0] ), @@ -29277,9 +28924,9 @@ module gaussian_conv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N61_2 ( - .COUT (_N15368), + .COUT (_N15544), .Z (N61[1]), - .CIN (_N15367), + .CIN (_N15543), .I0 (\mat[0][2] [0] ), .I1 (\mat[0][0] [0] ), .I2 (\mat[0][2] [1] ), @@ -29297,9 +28944,9 @@ module gaussian_conv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N61_3 ( - .COUT (_N15369), + .COUT (_N15545), .Z (N61[2]), - .CIN (_N15368), + .CIN (_N15544), .I0 (), .I1 (\mat[0][2] [2] ), .I2 (\mat[0][0] [2] ), @@ -29317,9 +28964,9 @@ module gaussian_conv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N61_4 ( - .COUT (_N15370), + .COUT (_N15546), .Z (N61[3]), - .CIN (_N15369), + .CIN (_N15545), .I0 (), .I1 (\mat[0][2] [3] ), .I2 (\mat[0][0] [3] ), @@ -29337,9 +28984,9 @@ module gaussian_conv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N61_5 ( - .COUT (_N15371), + .COUT (_N15547), .Z (N61[4]), - .CIN (_N15370), + .CIN (_N15546), .I0 (), .I1 (\mat[0][2] [4] ), .I2 (\mat[0][0] [4] ), @@ -29359,7 +29006,7 @@ module gaussian_conv N61_6 ( .COUT (), .Z (N61[5]), - .CIN (_N15371), + .CIN (_N15547), .I0 (), .I1 (), .I2 (), @@ -29377,7 +29024,7 @@ module gaussian_conv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N64_1 ( - .COUT (_N15382), + .COUT (_N15550), .Z (N64[0]), .CIN (), .I0 (\mat[2][2] [0] ), @@ -29397,9 +29044,9 @@ module gaussian_conv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N64_2 ( - .COUT (_N15383), + .COUT (_N15551), .Z (N64[1]), - .CIN (_N15382), + .CIN (_N15550), .I0 (\mat[2][2] [0] ), .I1 (\mat[2][0] [0] ), .I2 (\mat[2][2] [1] ), @@ -29417,9 +29064,9 @@ module gaussian_conv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N64_3 ( - .COUT (_N15384), + .COUT (_N15552), .Z (N64[2]), - .CIN (_N15383), + .CIN (_N15551), .I0 (), .I1 (\mat[2][2] [2] ), .I2 (\mat[2][0] [2] ), @@ -29437,9 +29084,9 @@ module gaussian_conv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N64_4 ( - .COUT (_N15385), + .COUT (_N15553), .Z (N64[3]), - .CIN (_N15384), + .CIN (_N15552), .I0 (), .I1 (\mat[2][2] [3] ), .I2 (\mat[2][0] [3] ), @@ -29457,9 +29104,9 @@ module gaussian_conv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N64_5 ( - .COUT (_N15386), + .COUT (_N15554), .Z (N64[4]), - .CIN (_N15385), + .CIN (_N15553), .I0 (), .I1 (\mat[2][2] [4] ), .I2 (\mat[2][0] [4] ), @@ -29479,7 +29126,7 @@ module gaussian_conv N64_6 ( .COUT (), .Z (N64[5]), - .CIN (_N15386), + .CIN (_N15554), .I0 (), .I1 (), .I2 (), @@ -29497,7 +29144,7 @@ module gaussian_conv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_1 ( - .COUT (_N15409), + .COUT (_N15557), .Z (N69[0]), .CIN (), .I0 (\mat[1][0] [0] ), @@ -29517,9 +29164,9 @@ module gaussian_conv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_2 ( - .COUT (_N15410), + .COUT (_N15558), .Z (N69[1]), - .CIN (_N15409), + .CIN (_N15557), .I0 (\mat[1][0] [0] ), .I1 (\mat[0][1] [0] ), .I2 (\mat[1][0] [1] ), @@ -29537,9 +29184,9 @@ module gaussian_conv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_3 ( - .COUT (_N15411), + .COUT (_N15559), .Z (N69[2]), - .CIN (_N15410), + .CIN (_N15558), .I0 (), .I1 (\mat[1][0] [2] ), .I2 (\mat[0][1] [2] ), @@ -29557,9 +29204,9 @@ module gaussian_conv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_4 ( - .COUT (_N15412), + .COUT (_N15560), .Z (N69[3]), - .CIN (_N15411), + .CIN (_N15559), .I0 (), .I1 (\mat[1][0] [3] ), .I2 (\mat[0][1] [3] ), @@ -29577,9 +29224,9 @@ module gaussian_conv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_5 ( - .COUT (_N15413), + .COUT (_N15561), .Z (N69[4]), - .CIN (_N15412), + .CIN (_N15560), .I0 (), .I1 (\mat[1][0] [4] ), .I2 (\mat[0][1] [4] ), @@ -29599,7 +29246,7 @@ module gaussian_conv N69_6 ( .COUT (), .Z (N69[5]), - .CIN (_N15413), + .CIN (_N15561), .I0 (), .I1 (), .I2 (), @@ -29617,7 +29264,7 @@ module gaussian_conv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N72_1 ( - .COUT (_N15424), + .COUT (_N15596), .Z (N72[0]), .CIN (), .I0 (\mat[2][1] [0] ), @@ -29637,9 +29284,9 @@ module gaussian_conv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N72_2 ( - .COUT (_N15425), + .COUT (_N15597), .Z (N72[1]), - .CIN (_N15424), + .CIN (_N15596), .I0 (\mat[2][1] [0] ), .I1 (\mat[1][2] [0] ), .I2 (\mat[2][1] [1] ), @@ -29657,9 +29304,9 @@ module gaussian_conv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N72_3 ( - .COUT (_N15426), + .COUT (_N15598), .Z (N72[2]), - .CIN (_N15425), + .CIN (_N15597), .I0 (), .I1 (\mat[2][1] [2] ), .I2 (\mat[1][2] [2] ), @@ -29677,9 +29324,9 @@ module gaussian_conv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N72_4 ( - .COUT (_N15427), + .COUT (_N15599), .Z (N72[3]), - .CIN (_N15426), + .CIN (_N15598), .I0 (), .I1 (\mat[2][1] [3] ), .I2 (\mat[1][2] [3] ), @@ -29697,9 +29344,9 @@ module gaussian_conv .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N72_5 ( - .COUT (_N15428), + .COUT (_N15600), .Z (N72[4]), - .CIN (_N15427), + .CIN (_N15599), .I0 (), .I1 (\mat[2][1] [4] ), .I2 (\mat[1][2] [4] ), @@ -29719,7 +29366,7 @@ module gaussian_conv N72_6 ( .COUT (), .Z (N72[5]), - .CIN (_N15428), + .CIN (_N15600), .I0 (), .I1 (), .I2 (), @@ -30543,63 +30190,63 @@ module gaussian_conv_1 wire [6:0] N72; wire [7:0] N77; wire [7:0] N78; - wire _N8166; - wire _N8174; - wire _N8179; - wire _N8184; - wire _N14736; - wire _N14737; - wire _N14738; - wire _N14739; - wire _N14740; - wire _N14741; - wire _N14742; - wire _N15556; - wire _N15557; - wire _N15558; - wire _N15559; - wire _N15560; - wire _N15561; - wire _N15562; - wire _N15565; - wire _N15566; - wire _N15567; - wire _N15568; - wire _N15569; - wire _N15570; - wire _N15571; - wire _N15583; - wire _N15584; - wire _N15585; - wire _N15586; - wire _N15587; - wire _N15588; - wire _N15589; - wire _N15590; - wire _N15599; - wire _N15600; - wire _N15601; - wire _N15602; - wire _N15603; - wire _N15604; - wire _N15607; - wire _N15608; - wire _N15609; - wire _N15610; - wire _N15611; - wire _N15612; - wire _N15615; - wire _N15616; - wire _N15617; - wire _N15618; - wire _N15619; - wire _N15620; - wire _N15623; - wire _N15624; - wire _N15625; - wire _N15626; - wire _N15627; - wire _N15628; + wire _N5407; + wire _N5415; + wire _N5420; + wire _N5425; + wire _N14309; + wire _N14310; + wire _N14311; + wire _N14312; + wire _N14313; + wire _N14314; + wire _N14315; + wire _N14361; + wire _N14362; + wire _N14363; + wire _N14364; + wire _N14365; + wire _N14366; + wire _N14367; + wire _N14403; + wire _N14404; + wire _N14405; + wire _N14406; + wire _N14407; + wire _N14408; + wire _N14409; + wire _N14410; + wire _N14471; + wire _N14472; + wire _N14473; + wire _N14474; + wire _N14475; + wire _N14476; + wire _N14496; + wire _N14497; + wire _N14498; + wire _N14499; + wire _N14500; + wire _N14501; + wire _N14515; + wire _N14516; + wire _N14517; + wire _N14518; + wire _N14519; + wire _N14520; + wire _N14562; + wire _N14563; + wire _N14564; + wire _N14565; + wire _N14566; + wire _N14567; + wire _N15686; + wire _N15687; + wire _N15688; + wire _N15689; + wire _N15690; + wire _N15691; + wire _N15692; wire [9:0] product4x2; wire [9:0] sum1x4; wire [9:0] sum4x1; @@ -30613,7 +30260,7 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_1 ( - .COUT (_N15556), + .COUT (_N14309), .Z (), .CIN (), .I0 (), @@ -30633,9 +30280,9 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_2 ( - .COUT (_N15557), + .COUT (_N14310), .Z (N78[1]), - .CIN (_N15556), + .CIN (_N14309), .I0 (N64[0]), .I1 (N61[0]), .I2 (N64[1]), @@ -30653,9 +30300,9 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_3 ( - .COUT (_N15558), + .COUT (_N14311), .Z (N78[2]), - .CIN (_N15557), + .CIN (_N14310), .I0 (), .I1 (N64[2]), .I2 (N61[2]), @@ -30673,9 +30320,9 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_4 ( - .COUT (_N15559), + .COUT (_N14312), .Z (N78[3]), - .CIN (_N15558), + .CIN (_N14311), .I0 (), .I1 (N64[3]), .I2 (N61[3]), @@ -30693,9 +30340,9 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_5 ( - .COUT (_N15560), + .COUT (_N14313), .Z (N78[4]), - .CIN (_N15559), + .CIN (_N14312), .I0 (), .I1 (N64[4]), .I2 (N61[4]), @@ -30713,9 +30360,9 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_6 ( - .COUT (_N15561), + .COUT (_N14314), .Z (N78[5]), - .CIN (_N15560), + .CIN (_N14313), .I0 (), .I1 (N64[5]), .I2 (N61[5]), @@ -30733,9 +30380,9 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_7 ( - .COUT (_N15562), + .COUT (_N14315), .Z (N78[6]), - .CIN (_N15561), + .CIN (_N14314), .I0 (), .I1 (N64[6]), .I2 (N61[6]), @@ -30755,7 +30402,7 @@ module gaussian_conv_1 N17_1_8 ( .COUT (), .Z (N78[7]), - .CIN (_N15562), + .CIN (_N14315), .I0 (), .I1 (), .I2 (), @@ -30773,7 +30420,7 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_1_1 ( - .COUT (_N15565), + .COUT (_N14361), .Z (N77[0]), .CIN (), .I0 (N72[0]), @@ -30793,9 +30440,9 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_1_2 ( - .COUT (_N15566), + .COUT (_N14362), .Z (N77[1]), - .CIN (_N15565), + .CIN (_N14361), .I0 (N72[0]), .I1 (N69[0]), .I2 (N72[1]), @@ -30813,9 +30460,9 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_1_3 ( - .COUT (_N15567), + .COUT (_N14363), .Z (N77[2]), - .CIN (_N15566), + .CIN (_N14362), .I0 (), .I1 (N72[2]), .I2 (N69[2]), @@ -30833,9 +30480,9 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_1_4 ( - .COUT (_N15568), + .COUT (_N14364), .Z (N77[3]), - .CIN (_N15567), + .CIN (_N14363), .I0 (), .I1 (N72[3]), .I2 (N69[3]), @@ -30853,9 +30500,9 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_1_5 ( - .COUT (_N15569), + .COUT (_N14365), .Z (N77[4]), - .CIN (_N15568), + .CIN (_N14364), .I0 (), .I1 (N72[4]), .I2 (N69[4]), @@ -30873,9 +30520,9 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_1_6 ( - .COUT (_N15570), + .COUT (_N14366), .Z (N77[5]), - .CIN (_N15569), + .CIN (_N14365), .I0 (), .I1 (N72[5]), .I2 (N69[5]), @@ -30893,9 +30540,9 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_1_7 ( - .COUT (_N15571), + .COUT (_N14367), .Z (N77[6]), - .CIN (_N15570), + .CIN (_N14366), .I0 (), .I1 (N72[6]), .I2 (N69[6]), @@ -30915,7 +30562,7 @@ module gaussian_conv_1 N26_1_8 ( .COUT (), .Z (N77[7]), - .CIN (_N15571), + .CIN (_N14367), .I0 (), .I1 (), .I2 (), @@ -30929,7 +30576,7 @@ module gaussian_conv_1 GTP_LUT2 /* N39_0_ac4 */ #( .INIT(4'b1000)) N39_0_ac4 ( - .Z (_N8174), + .Z (_N5415), .I0 (sum1x4[4]), .I1 (sum4x1[4])); // LUT = I0&I1 ; @@ -30937,7 +30584,7 @@ module gaussian_conv_1 GTP_LUT2 /* N39_0_ac5 */ #( .INIT(4'b1000)) N39_0_ac5 ( - .Z (_N8179), + .Z (_N5420), .I0 (sum1x4[5]), .I1 (sum4x1[5])); // LUT = I0&I1 ; @@ -30945,7 +30592,7 @@ module gaussian_conv_1 GTP_LUT2 /* N39_0_ac6 */ #( .INIT(4'b1000)) N39_0_ac6 ( - .Z (_N8184), + .Z (_N5425), .I0 (sum1x4[6]), .I1 (sum4x1[6])); // LUT = I0&I1 ; @@ -30953,7 +30600,7 @@ module gaussian_conv_1 GTP_LUT2 /* N39_0_maj3 */ #( .INIT(4'b1110)) N39_0_maj3 ( - .Z (_N8166), + .Z (_N5407), .I0 (sum1x4[3]), .I1 (sum4x1[3])); // LUT = (I0)|(I1) ; @@ -30965,7 +30612,7 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_3_1 ( - .COUT (_N14736), + .COUT (_N15686), .Z (N59[2]), .CIN (), .I0 (sum4x1[2]), @@ -30984,9 +30631,9 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_3_2 ( - .COUT (_N14737), + .COUT (_N15687), .Z (N59[3]), - .CIN (_N14736), + .CIN (_N15686), .I0 (sum4x1[2]), .I1 (sum1x4[2]), .I2 (sum1x4[3]), @@ -31003,14 +30650,14 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_3_3 ( - .COUT (_N14738), + .COUT (_N15688), .Z (N59[4]), - .CIN (_N14737), + .CIN (_N15687), .I0 (), .I1 (sum1x4[4]), - .I2 (_N8166), + .I2 (_N5407), .I3 (sum4x1[4]), - .I4 (_N8166), + .I4 (_N5407), .ID ()); // LUT = I3^I2^I1^CIN ; // CARRY = (I3^I2^I1) ? CIN : (I4) ; @@ -31022,14 +30669,14 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_3_4 ( - .COUT (_N14739), + .COUT (_N15689), .Z (N59[5]), - .CIN (_N14738), + .CIN (_N15688), .I0 (), .I1 (sum1x4[5]), - .I2 (_N8174), + .I2 (_N5415), .I3 (sum4x1[5]), - .I4 (_N8174), + .I4 (_N5415), .ID ()); // LUT = I3^I2^I1^CIN ; // CARRY = (I3^I2^I1) ? CIN : (I4) ; @@ -31041,14 +30688,14 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_3_5 ( - .COUT (_N14740), + .COUT (_N15690), .Z (N59[6]), - .CIN (_N14739), + .CIN (_N15689), .I0 (), .I1 (sum1x4[6]), - .I2 (_N8179), + .I2 (_N5420), .I3 (sum4x1[6]), - .I4 (_N8179), + .I4 (_N5420), .ID ()); // LUT = I3^I2^I1^CIN ; // CARRY = (I3^I2^I1) ? CIN : (I4) ; @@ -31060,14 +30707,14 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_3_6 ( - .COUT (_N14741), + .COUT (_N15691), .Z (N59[7]), - .CIN (_N14740), + .CIN (_N15690), .I0 (), .I1 (sum1x4[7]), - .I2 (_N8184), + .I2 (_N5425), .I3 (sum4x1[7]), - .I4 (_N8184), + .I4 (_N5425), .ID ()); // LUT = I3^I2^I1^CIN ; // CARRY = (I3^I2^I1) ? CIN : (I4) ; @@ -31079,9 +30726,9 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_3_7 ( - .COUT (_N14742), + .COUT (_N15692), .Z (N59[8]), - .CIN (_N14741), + .CIN (_N15691), .I0 (), .I1 (sum1x4[7]), .I2 (sum4x1[7]), @@ -31100,7 +30747,7 @@ module gaussian_conv_1 N39_3_8 ( .COUT (), .Z (N59[9]), - .CIN (_N14742), + .CIN (_N15692), .I0 (), .I1 (), .I2 (), @@ -31117,7 +30764,7 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N47_1_1 ( - .COUT (_N15583), + .COUT (_N14403), .Z (), .CIN (), .I0 (), @@ -31137,9 +30784,9 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N47_1_2 ( - .COUT (_N15584), + .COUT (_N14404), .Z (), - .CIN (_N15583), + .CIN (_N14403), .I0 (sum8[1]), .I1 (product4x2[1]), .I2 (sum8[2]), @@ -31157,9 +30804,9 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N47_1_3 ( - .COUT (_N15585), + .COUT (_N14405), .Z (), - .CIN (_N15584), + .CIN (_N14404), .I0 (), .I1 (sum8[3]), .I2 (product4x2[3]), @@ -31177,9 +30824,9 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N47_1_4 ( - .COUT (_N15586), + .COUT (_N14406), .Z (N47[4]), - .CIN (_N15585), + .CIN (_N14405), .I0 (), .I1 (sum8[4]), .I2 (product4x2[4]), @@ -31197,9 +30844,9 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N47_1_5 ( - .COUT (_N15587), + .COUT (_N14407), .Z (N47[5]), - .CIN (_N15586), + .CIN (_N14406), .I0 (), .I1 (sum8[5]), .I2 (product4x2[5]), @@ -31217,9 +30864,9 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N47_1_6 ( - .COUT (_N15588), + .COUT (_N14408), .Z (N47[6]), - .CIN (_N15587), + .CIN (_N14407), .I0 (), .I1 (sum8[6]), .I2 (product4x2[6]), @@ -31237,9 +30884,9 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N47_1_7 ( - .COUT (_N15589), + .COUT (_N14409), .Z (N47[7]), - .CIN (_N15588), + .CIN (_N14408), .I0 (), .I1 (sum8[7]), .I2 (product4x2[7]), @@ -31257,9 +30904,9 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N47_1_8 ( - .COUT (_N15590), + .COUT (_N14410), .Z (N47[8]), - .CIN (_N15589), + .CIN (_N14409), .I0 (), .I1 (sum8[8]), .I2 (product4x2[8]), @@ -31279,7 +30926,7 @@ module gaussian_conv_1 N47_1_9 ( .COUT (), .Z (N47[9]), - .CIN (_N15590), + .CIN (_N14410), .I0 (), .I1 (sum8[9]), .I2 (), @@ -31297,7 +30944,7 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N61_1 ( - .COUT (_N15599), + .COUT (_N14471), .Z (N61[0]), .CIN (), .I0 (\mat[0][2] [0] ), @@ -31317,9 +30964,9 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N61_2 ( - .COUT (_N15600), + .COUT (_N14472), .Z (N61[1]), - .CIN (_N15599), + .CIN (_N14471), .I0 (\mat[0][2] [0] ), .I1 (\mat[0][0] [0] ), .I2 (\mat[0][2] [1] ), @@ -31337,9 +30984,9 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N61_3 ( - .COUT (_N15601), + .COUT (_N14473), .Z (N61[2]), - .CIN (_N15600), + .CIN (_N14472), .I0 (), .I1 (\mat[0][2] [2] ), .I2 (\mat[0][0] [2] ), @@ -31357,9 +31004,9 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N61_4 ( - .COUT (_N15602), + .COUT (_N14474), .Z (N61[3]), - .CIN (_N15601), + .CIN (_N14473), .I0 (), .I1 (\mat[0][2] [3] ), .I2 (\mat[0][0] [3] ), @@ -31377,9 +31024,9 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N61_5 ( - .COUT (_N15603), + .COUT (_N14475), .Z (N61[4]), - .CIN (_N15602), + .CIN (_N14474), .I0 (), .I1 (\mat[0][2] [4] ), .I2 (\mat[0][0] [4] ), @@ -31397,9 +31044,9 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N61_6 ( - .COUT (_N15604), + .COUT (_N14476), .Z (N61[5]), - .CIN (_N15603), + .CIN (_N14475), .I0 (), .I1 (\mat[0][2] [5] ), .I2 (\mat[0][0] [5] ), @@ -31419,7 +31066,7 @@ module gaussian_conv_1 N61_7 ( .COUT (), .Z (N61[6]), - .CIN (_N15604), + .CIN (_N14476), .I0 (), .I1 (), .I2 (), @@ -31437,7 +31084,7 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N64_1 ( - .COUT (_N15607), + .COUT (_N14496), .Z (N64[0]), .CIN (), .I0 (\mat[2][2] [0] ), @@ -31457,9 +31104,9 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N64_2 ( - .COUT (_N15608), + .COUT (_N14497), .Z (N64[1]), - .CIN (_N15607), + .CIN (_N14496), .I0 (\mat[2][2] [0] ), .I1 (\mat[2][0] [0] ), .I2 (\mat[2][2] [1] ), @@ -31477,9 +31124,9 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N64_3 ( - .COUT (_N15609), + .COUT (_N14498), .Z (N64[2]), - .CIN (_N15608), + .CIN (_N14497), .I0 (), .I1 (\mat[2][2] [2] ), .I2 (\mat[2][0] [2] ), @@ -31497,9 +31144,9 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N64_4 ( - .COUT (_N15610), + .COUT (_N14499), .Z (N64[3]), - .CIN (_N15609), + .CIN (_N14498), .I0 (), .I1 (\mat[2][2] [3] ), .I2 (\mat[2][0] [3] ), @@ -31517,9 +31164,9 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N64_5 ( - .COUT (_N15611), + .COUT (_N14500), .Z (N64[4]), - .CIN (_N15610), + .CIN (_N14499), .I0 (), .I1 (\mat[2][2] [4] ), .I2 (\mat[2][0] [4] ), @@ -31537,9 +31184,9 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N64_6 ( - .COUT (_N15612), + .COUT (_N14501), .Z (N64[5]), - .CIN (_N15611), + .CIN (_N14500), .I0 (), .I1 (\mat[2][2] [5] ), .I2 (\mat[2][0] [5] ), @@ -31559,7 +31206,7 @@ module gaussian_conv_1 N64_7 ( .COUT (), .Z (N64[6]), - .CIN (_N15612), + .CIN (_N14501), .I0 (), .I1 (), .I2 (), @@ -31577,7 +31224,7 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_1 ( - .COUT (_N15615), + .COUT (_N14515), .Z (N69[0]), .CIN (), .I0 (\mat[1][0] [0] ), @@ -31597,9 +31244,9 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_2 ( - .COUT (_N15616), + .COUT (_N14516), .Z (N69[1]), - .CIN (_N15615), + .CIN (_N14515), .I0 (\mat[1][0] [0] ), .I1 (\mat[0][1] [0] ), .I2 (\mat[1][0] [1] ), @@ -31617,9 +31264,9 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_3 ( - .COUT (_N15617), + .COUT (_N14517), .Z (N69[2]), - .CIN (_N15616), + .CIN (_N14516), .I0 (), .I1 (\mat[1][0] [2] ), .I2 (\mat[0][1] [2] ), @@ -31637,9 +31284,9 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_4 ( - .COUT (_N15618), + .COUT (_N14518), .Z (N69[3]), - .CIN (_N15617), + .CIN (_N14517), .I0 (), .I1 (\mat[1][0] [3] ), .I2 (\mat[0][1] [3] ), @@ -31657,9 +31304,9 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_5 ( - .COUT (_N15619), + .COUT (_N14519), .Z (N69[4]), - .CIN (_N15618), + .CIN (_N14518), .I0 (), .I1 (\mat[1][0] [4] ), .I2 (\mat[0][1] [4] ), @@ -31677,9 +31324,9 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_6 ( - .COUT (_N15620), + .COUT (_N14520), .Z (N69[5]), - .CIN (_N15619), + .CIN (_N14519), .I0 (), .I1 (\mat[1][0] [5] ), .I2 (\mat[0][1] [5] ), @@ -31699,7 +31346,7 @@ module gaussian_conv_1 N69_7 ( .COUT (), .Z (N69[6]), - .CIN (_N15620), + .CIN (_N14520), .I0 (), .I1 (), .I2 (), @@ -31717,7 +31364,7 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N72_1 ( - .COUT (_N15623), + .COUT (_N14562), .Z (N72[0]), .CIN (), .I0 (\mat[2][1] [0] ), @@ -31737,9 +31384,9 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N72_2 ( - .COUT (_N15624), + .COUT (_N14563), .Z (N72[1]), - .CIN (_N15623), + .CIN (_N14562), .I0 (\mat[2][1] [0] ), .I1 (\mat[1][2] [0] ), .I2 (\mat[2][1] [1] ), @@ -31757,9 +31404,9 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N72_3 ( - .COUT (_N15625), + .COUT (_N14564), .Z (N72[2]), - .CIN (_N15624), + .CIN (_N14563), .I0 (), .I1 (\mat[2][1] [2] ), .I2 (\mat[1][2] [2] ), @@ -31777,9 +31424,9 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N72_4 ( - .COUT (_N15626), + .COUT (_N14565), .Z (N72[3]), - .CIN (_N15625), + .CIN (_N14564), .I0 (), .I1 (\mat[2][1] [3] ), .I2 (\mat[1][2] [3] ), @@ -31797,9 +31444,9 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N72_5 ( - .COUT (_N15627), + .COUT (_N14566), .Z (N72[4]), - .CIN (_N15626), + .CIN (_N14565), .I0 (), .I1 (\mat[2][1] [4] ), .I2 (\mat[1][2] [4] ), @@ -31817,9 +31464,9 @@ module gaussian_conv_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N72_6 ( - .COUT (_N15628), + .COUT (_N14567), .Z (N72[5]), - .CIN (_N15627), + .CIN (_N14566), .I0 (), .I1 (\mat[2][1] [5] ), .I2 (\mat[1][2] [5] ), @@ -31839,7 +31486,7 @@ module gaussian_conv_1 N72_7 ( .COUT (), .Z (N72[6]), - .CIN (_N15628), + .CIN (_N14567), .I0 (), .I1 (), .I2 (), @@ -32804,54 +32451,54 @@ module gaussian_conv_unq8 wire [5:0] N72; wire [6:0] N77; wire [6:0] N78; - wire _N5330; - wire _N5338; - wire _N5343; - wire _N14315; - wire _N14316; - wire _N14317; - wire _N14318; - wire _N14319; - wire _N14320; - wire _N14397; - wire _N14398; - wire _N14399; - wire _N14400; - wire _N14401; - wire _N14402; - wire _N14405; - wire _N14406; - wire _N14407; - wire _N14408; - wire _N14409; - wire _N14410; - wire _N14411; - wire _N14424; - wire _N14425; - wire _N14426; - wire _N14427; - wire _N14428; - wire _N14469; - wire _N14470; - wire _N14471; - wire _N14472; - wire _N14473; - wire _N14502; - wire _N14503; - wire _N14504; - wire _N14505; - wire _N14506; - wire _N14535; - wire _N14536; - wire _N14537; - wire _N14538; - wire _N14539; - wire _N16983; - wire _N16984; - wire _N16985; - wire _N16986; - wire _N16987; - wire _N16988; + wire _N5804; + wire _N5812; + wire _N5817; + wire _N13784; + wire _N13785; + wire _N13786; + wire _N13787; + wire _N13788; + wire _N13789; + wire _N14770; + wire _N14771; + wire _N14772; + wire _N14773; + wire _N14774; + wire _N14775; + wire _N14778; + wire _N14779; + wire _N14780; + wire _N14781; + wire _N14782; + wire _N14783; + wire _N14800; + wire _N14801; + wire _N14802; + wire _N14803; + wire _N14804; + wire _N14805; + wire _N14806; + wire _N14848; + wire _N14849; + wire _N14850; + wire _N14851; + wire _N14852; + wire _N14855; + wire _N14856; + wire _N14857; + wire _N14858; + wire _N14859; + wire _N14862; + wire _N14863; + wire _N14864; + wire _N14865; + wire _N14866; + wire _N14869; + wire _N14870; + wire _N14871; + wire _N14872; + wire _N14873; wire [8:0] product4x2; wire [8:0] sum1x4; wire [8:0] sum4x1; @@ -32865,7 +32512,7 @@ module gaussian_conv_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_1 ( - .COUT (_N14315), + .COUT (_N14770), .Z (), .CIN (), .I0 (), @@ -32885,9 +32532,9 @@ module gaussian_conv_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_2 ( - .COUT (_N14316), + .COUT (_N14771), .Z (N78[1]), - .CIN (_N14315), + .CIN (_N14770), .I0 (N64[0]), .I1 (N61[0]), .I2 (N64[1]), @@ -32905,9 +32552,9 @@ module gaussian_conv_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_3 ( - .COUT (_N14317), + .COUT (_N14772), .Z (N78[2]), - .CIN (_N14316), + .CIN (_N14771), .I0 (), .I1 (N64[2]), .I2 (N61[2]), @@ -32925,9 +32572,9 @@ module gaussian_conv_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_4 ( - .COUT (_N14318), + .COUT (_N14773), .Z (N78[3]), - .CIN (_N14317), + .CIN (_N14772), .I0 (), .I1 (N64[3]), .I2 (N61[3]), @@ -32945,9 +32592,9 @@ module gaussian_conv_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_5 ( - .COUT (_N14319), + .COUT (_N14774), .Z (N78[4]), - .CIN (_N14318), + .CIN (_N14773), .I0 (), .I1 (N64[4]), .I2 (N61[4]), @@ -32965,9 +32612,9 @@ module gaussian_conv_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_6 ( - .COUT (_N14320), + .COUT (_N14775), .Z (N78[5]), - .CIN (_N14319), + .CIN (_N14774), .I0 (), .I1 (N64[5]), .I2 (N61[5]), @@ -32987,7 +32634,7 @@ module gaussian_conv_unq8 N17_1_7 ( .COUT (), .Z (N78[6]), - .CIN (_N14320), + .CIN (_N14775), .I0 (), .I1 (), .I2 (), @@ -33005,7 +32652,7 @@ module gaussian_conv_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_1_1 ( - .COUT (_N14397), + .COUT (_N14778), .Z (N77[0]), .CIN (), .I0 (N72[0]), @@ -33025,9 +32672,9 @@ module gaussian_conv_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_1_2 ( - .COUT (_N14398), + .COUT (_N14779), .Z (N77[1]), - .CIN (_N14397), + .CIN (_N14778), .I0 (N72[0]), .I1 (N69[0]), .I2 (N72[1]), @@ -33045,9 +32692,9 @@ module gaussian_conv_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_1_3 ( - .COUT (_N14399), + .COUT (_N14780), .Z (N77[2]), - .CIN (_N14398), + .CIN (_N14779), .I0 (), .I1 (N72[2]), .I2 (N69[2]), @@ -33065,9 +32712,9 @@ module gaussian_conv_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_1_4 ( - .COUT (_N14400), + .COUT (_N14781), .Z (N77[3]), - .CIN (_N14399), + .CIN (_N14780), .I0 (), .I1 (N72[3]), .I2 (N69[3]), @@ -33085,9 +32732,9 @@ module gaussian_conv_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_1_5 ( - .COUT (_N14401), + .COUT (_N14782), .Z (N77[4]), - .CIN (_N14400), + .CIN (_N14781), .I0 (), .I1 (N72[4]), .I2 (N69[4]), @@ -33105,9 +32752,9 @@ module gaussian_conv_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_1_6 ( - .COUT (_N14402), + .COUT (_N14783), .Z (N77[5]), - .CIN (_N14401), + .CIN (_N14782), .I0 (), .I1 (N72[5]), .I2 (N69[5]), @@ -33127,7 +32774,7 @@ module gaussian_conv_unq8 N26_1_7 ( .COUT (), .Z (N77[6]), - .CIN (_N14402), + .CIN (_N14783), .I0 (), .I1 (), .I2 (), @@ -33141,7 +32788,7 @@ module gaussian_conv_unq8 GTP_LUT2 /* N39_0_ac4 */ #( .INIT(4'b1000)) N39_0_ac4 ( - .Z (_N5338), + .Z (_N5812), .I0 (sum1x4[4]), .I1 (sum4x1[4])); // LUT = I0&I1 ; @@ -33149,7 +32796,7 @@ module gaussian_conv_unq8 GTP_LUT2 /* N39_0_ac5 */ #( .INIT(4'b1000)) N39_0_ac5 ( - .Z (_N5343), + .Z (_N5817), .I0 (sum1x4[5]), .I1 (sum4x1[5])); // LUT = I0&I1 ; @@ -33157,7 +32804,7 @@ module gaussian_conv_unq8 GTP_LUT2 /* N39_0_maj3 */ #( .INIT(4'b1110)) N39_0_maj3 ( - .Z (_N5330), + .Z (_N5804), .I0 (sum1x4[3]), .I1 (sum4x1[3])); // LUT = (I0)|(I1) ; @@ -33169,7 +32816,7 @@ module gaussian_conv_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_3_1 ( - .COUT (_N16983), + .COUT (_N13784), .Z (N59[2]), .CIN (), .I0 (sum4x1[2]), @@ -33188,9 +32835,9 @@ module gaussian_conv_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_3_2 ( - .COUT (_N16984), + .COUT (_N13785), .Z (N59[3]), - .CIN (_N16983), + .CIN (_N13784), .I0 (sum4x1[2]), .I1 (sum1x4[2]), .I2 (sum1x4[3]), @@ -33207,14 +32854,14 @@ module gaussian_conv_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_3_3 ( - .COUT (_N16985), + .COUT (_N13786), .Z (N59[4]), - .CIN (_N16984), + .CIN (_N13785), .I0 (), .I1 (sum1x4[4]), - .I2 (_N5330), + .I2 (_N5804), .I3 (sum4x1[4]), - .I4 (_N5330), + .I4 (_N5804), .ID ()); // LUT = I3^I2^I1^CIN ; // CARRY = (I3^I2^I1) ? CIN : (I4) ; @@ -33226,14 +32873,14 @@ module gaussian_conv_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_3_4 ( - .COUT (_N16986), + .COUT (_N13787), .Z (N59[5]), - .CIN (_N16985), + .CIN (_N13786), .I0 (), .I1 (sum1x4[5]), - .I2 (_N5338), + .I2 (_N5812), .I3 (sum4x1[5]), - .I4 (_N5338), + .I4 (_N5812), .ID ()); // LUT = I3^I2^I1^CIN ; // CARRY = (I3^I2^I1) ? CIN : (I4) ; @@ -33245,14 +32892,14 @@ module gaussian_conv_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_3_5 ( - .COUT (_N16987), + .COUT (_N13788), .Z (N59[6]), - .CIN (_N16986), + .CIN (_N13787), .I0 (), .I1 (sum1x4[6]), - .I2 (_N5343), + .I2 (_N5817), .I3 (sum4x1[6]), - .I4 (_N5343), + .I4 (_N5817), .ID ()); // LUT = I3^I2^I1^CIN ; // CARRY = (I3^I2^I1) ? CIN : (I4) ; @@ -33264,9 +32911,9 @@ module gaussian_conv_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_3_6 ( - .COUT (_N16988), + .COUT (_N13789), .Z (N59[7]), - .CIN (_N16987), + .CIN (_N13788), .I0 (), .I1 (sum1x4[6]), .I2 (sum4x1[6]), @@ -33285,7 +32932,7 @@ module gaussian_conv_unq8 N39_3_7 ( .COUT (), .Z (N59[8]), - .CIN (_N16988), + .CIN (_N13789), .I0 (), .I1 (), .I2 (), @@ -33302,7 +32949,7 @@ module gaussian_conv_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N47_1_1 ( - .COUT (_N14405), + .COUT (_N14800), .Z (), .CIN (), .I0 (), @@ -33322,9 +32969,9 @@ module gaussian_conv_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N47_1_2 ( - .COUT (_N14406), + .COUT (_N14801), .Z (), - .CIN (_N14405), + .CIN (_N14800), .I0 (sum8[1]), .I1 (product4x2[1]), .I2 (sum8[2]), @@ -33342,9 +32989,9 @@ module gaussian_conv_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N47_1_3 ( - .COUT (_N14407), + .COUT (_N14802), .Z (), - .CIN (_N14406), + .CIN (_N14801), .I0 (), .I1 (sum8[3]), .I2 (product4x2[3]), @@ -33362,9 +33009,9 @@ module gaussian_conv_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N47_1_4 ( - .COUT (_N14408), + .COUT (_N14803), .Z (N47[4]), - .CIN (_N14407), + .CIN (_N14802), .I0 (), .I1 (sum8[4]), .I2 (product4x2[4]), @@ -33382,9 +33029,9 @@ module gaussian_conv_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N47_1_5 ( - .COUT (_N14409), + .COUT (_N14804), .Z (N47[5]), - .CIN (_N14408), + .CIN (_N14803), .I0 (), .I1 (sum8[5]), .I2 (product4x2[5]), @@ -33402,9 +33049,9 @@ module gaussian_conv_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N47_1_6 ( - .COUT (_N14410), + .COUT (_N14805), .Z (N47[6]), - .CIN (_N14409), + .CIN (_N14804), .I0 (), .I1 (sum8[6]), .I2 (product4x2[6]), @@ -33422,9 +33069,9 @@ module gaussian_conv_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N47_1_7 ( - .COUT (_N14411), + .COUT (_N14806), .Z (N47[7]), - .CIN (_N14410), + .CIN (_N14805), .I0 (), .I1 (sum8[7]), .I2 (product4x2[7]), @@ -33444,7 +33091,7 @@ module gaussian_conv_unq8 N47_1_8 ( .COUT (), .Z (N47[8]), - .CIN (_N14411), + .CIN (_N14806), .I0 (), .I1 (sum8[8]), .I2 (), @@ -33462,7 +33109,7 @@ module gaussian_conv_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N61_1 ( - .COUT (_N14424), + .COUT (_N14848), .Z (N61[0]), .CIN (), .I0 (\mat[0][2] [0] ), @@ -33482,9 +33129,9 @@ module gaussian_conv_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N61_2 ( - .COUT (_N14425), + .COUT (_N14849), .Z (N61[1]), - .CIN (_N14424), + .CIN (_N14848), .I0 (\mat[0][2] [0] ), .I1 (\mat[0][0] [0] ), .I2 (\mat[0][2] [1] ), @@ -33502,9 +33149,9 @@ module gaussian_conv_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N61_3 ( - .COUT (_N14426), + .COUT (_N14850), .Z (N61[2]), - .CIN (_N14425), + .CIN (_N14849), .I0 (), .I1 (\mat[0][2] [2] ), .I2 (\mat[0][0] [2] ), @@ -33522,9 +33169,9 @@ module gaussian_conv_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N61_4 ( - .COUT (_N14427), + .COUT (_N14851), .Z (N61[3]), - .CIN (_N14426), + .CIN (_N14850), .I0 (), .I1 (\mat[0][2] [3] ), .I2 (\mat[0][0] [3] ), @@ -33542,9 +33189,9 @@ module gaussian_conv_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N61_5 ( - .COUT (_N14428), + .COUT (_N14852), .Z (N61[4]), - .CIN (_N14427), + .CIN (_N14851), .I0 (), .I1 (\mat[0][2] [4] ), .I2 (\mat[0][0] [4] ), @@ -33564,7 +33211,7 @@ module gaussian_conv_unq8 N61_6 ( .COUT (), .Z (N61[5]), - .CIN (_N14428), + .CIN (_N14852), .I0 (), .I1 (), .I2 (), @@ -33582,7 +33229,7 @@ module gaussian_conv_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N64_1 ( - .COUT (_N14469), + .COUT (_N14855), .Z (N64[0]), .CIN (), .I0 (\mat[2][2] [0] ), @@ -33602,9 +33249,9 @@ module gaussian_conv_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N64_2 ( - .COUT (_N14470), + .COUT (_N14856), .Z (N64[1]), - .CIN (_N14469), + .CIN (_N14855), .I0 (\mat[2][2] [0] ), .I1 (\mat[2][0] [0] ), .I2 (\mat[2][2] [1] ), @@ -33622,9 +33269,9 @@ module gaussian_conv_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N64_3 ( - .COUT (_N14471), + .COUT (_N14857), .Z (N64[2]), - .CIN (_N14470), + .CIN (_N14856), .I0 (), .I1 (\mat[2][2] [2] ), .I2 (\mat[2][0] [2] ), @@ -33642,9 +33289,9 @@ module gaussian_conv_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N64_4 ( - .COUT (_N14472), + .COUT (_N14858), .Z (N64[3]), - .CIN (_N14471), + .CIN (_N14857), .I0 (), .I1 (\mat[2][2] [3] ), .I2 (\mat[2][0] [3] ), @@ -33662,9 +33309,9 @@ module gaussian_conv_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N64_5 ( - .COUT (_N14473), + .COUT (_N14859), .Z (N64[4]), - .CIN (_N14472), + .CIN (_N14858), .I0 (), .I1 (\mat[2][2] [4] ), .I2 (\mat[2][0] [4] ), @@ -33684,7 +33331,7 @@ module gaussian_conv_unq8 N64_6 ( .COUT (), .Z (N64[5]), - .CIN (_N14473), + .CIN (_N14859), .I0 (), .I1 (), .I2 (), @@ -33702,7 +33349,7 @@ module gaussian_conv_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_1 ( - .COUT (_N14502), + .COUT (_N14862), .Z (N69[0]), .CIN (), .I0 (\mat[1][0] [0] ), @@ -33722,9 +33369,9 @@ module gaussian_conv_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_2 ( - .COUT (_N14503), + .COUT (_N14863), .Z (N69[1]), - .CIN (_N14502), + .CIN (_N14862), .I0 (\mat[1][0] [0] ), .I1 (\mat[0][1] [0] ), .I2 (\mat[1][0] [1] ), @@ -33742,9 +33389,9 @@ module gaussian_conv_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_3 ( - .COUT (_N14504), + .COUT (_N14864), .Z (N69[2]), - .CIN (_N14503), + .CIN (_N14863), .I0 (), .I1 (\mat[1][0] [2] ), .I2 (\mat[0][1] [2] ), @@ -33762,9 +33409,9 @@ module gaussian_conv_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_4 ( - .COUT (_N14505), + .COUT (_N14865), .Z (N69[3]), - .CIN (_N14504), + .CIN (_N14864), .I0 (), .I1 (\mat[1][0] [3] ), .I2 (\mat[0][1] [3] ), @@ -33782,9 +33429,9 @@ module gaussian_conv_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_5 ( - .COUT (_N14506), + .COUT (_N14866), .Z (N69[4]), - .CIN (_N14505), + .CIN (_N14865), .I0 (), .I1 (\mat[1][0] [4] ), .I2 (\mat[0][1] [4] ), @@ -33804,7 +33451,7 @@ module gaussian_conv_unq8 N69_6 ( .COUT (), .Z (N69[5]), - .CIN (_N14506), + .CIN (_N14866), .I0 (), .I1 (), .I2 (), @@ -33822,7 +33469,7 @@ module gaussian_conv_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N72_1 ( - .COUT (_N14535), + .COUT (_N14869), .Z (N72[0]), .CIN (), .I0 (\mat[2][1] [0] ), @@ -33842,9 +33489,9 @@ module gaussian_conv_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N72_2 ( - .COUT (_N14536), + .COUT (_N14870), .Z (N72[1]), - .CIN (_N14535), + .CIN (_N14869), .I0 (\mat[2][1] [0] ), .I1 (\mat[1][2] [0] ), .I2 (\mat[2][1] [1] ), @@ -33862,9 +33509,9 @@ module gaussian_conv_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N72_3 ( - .COUT (_N14537), + .COUT (_N14871), .Z (N72[2]), - .CIN (_N14536), + .CIN (_N14870), .I0 (), .I1 (\mat[2][1] [2] ), .I2 (\mat[1][2] [2] ), @@ -33882,9 +33529,9 @@ module gaussian_conv_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N72_4 ( - .COUT (_N14538), + .COUT (_N14872), .Z (N72[3]), - .CIN (_N14537), + .CIN (_N14871), .I0 (), .I1 (\mat[2][1] [3] ), .I2 (\mat[1][2] [3] ), @@ -33902,9 +33549,9 @@ module gaussian_conv_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N72_5 ( - .COUT (_N14539), + .COUT (_N14873), .Z (N72[4]), - .CIN (_N14538), + .CIN (_N14872), .I0 (), .I1 (\mat[2][1] [4] ), .I2 (\mat[1][2] [4] ), @@ -33924,7 +33571,7 @@ module gaussian_conv_unq8 N72_6 ( .COUT (), .Z (N72[5]), - .CIN (_N14539), + .CIN (_N14873), .I0 (), .I1 (), .I2 (), @@ -34743,10 +34390,10 @@ module sort_3 wire [4:0] N55; wire [4:0] N68; wire [4:0] N73; - wire _N23329; - wire _N23915; - wire _N23919; - wire _N96015; + wire _N17669; + wire _N24186; + wire _N24190; + wire _N96795; GTP_LUT5CARRY /* \N4.lt_0 */ #( .INIT(32'b00100000111100100000000000000000), @@ -34998,32 +34645,33 @@ module sort_3 // LUT = I0&I1 ; // ../../sources/designs/image_filiter/sort_3.v:38 - GTP_LUT4 /* N55_9 */ #( - .INIT(16'b1100101010101010)) - N55_9 ( - .Z (_N96015), + GTP_LUT4 /* N55_7 */ #( + .INIT(16'b0000101000101010)) + N55_7 ( + .Z (_N17669), .I0 (N4), .I1 (N5), .I2 (N8), .I3 (N15)); - // LUT = (I0&~I3)|(I0&~I2)|(I1&I2&I3) ; + // LUT = (I0&~I2)|(I0&~I1&~I3) ; + // ../../sources/designs/image_filiter/sort_3.v:23 - GTP_LUT4 /* N55_11_1 */ #( - .INIT(16'b0000101000101010)) - N55_11_1 ( - .Z (_N23329), + GTP_LUT4 /* N55_9 */ #( + .INIT(16'b1100101010101010)) + N55_9 ( + .Z (_N96795), .I0 (N4), .I1 (N5), .I2 (N8), .I3 (N15)); - // LUT = (I0&~I2)|(I0&~I1&~I3) ; + // LUT = (I0&~I3)|(I0&~I2)|(I1&I2&I3) ; GTP_LUT5 /* \N55_18[0] */ #( .INIT(32'b11111011010100011110101001000000)) \N55_18[0] ( .Z (N55[0]), - .I0 (_N23329), - .I1 (_N96015), + .I0 (_N17669), + .I1 (_N96795), .I2 (original_data[10]), .I3 (original_data[5]), .I4 (original_data[0])); @@ -35033,8 +34681,8 @@ module sort_3 .INIT(32'b11111011010100011110101001000000)) \N55_18[1] ( .Z (N55[1]), - .I0 (_N23329), - .I1 (_N96015), + .I0 (_N17669), + .I1 (_N96795), .I2 (original_data[11]), .I3 (original_data[6]), .I4 (original_data[1])); @@ -35044,8 +34692,8 @@ module sort_3 .INIT(32'b11111011010100011110101001000000)) \N55_18[2] ( .Z (N55[2]), - .I0 (_N23329), - .I1 (_N96015), + .I0 (_N17669), + .I1 (_N96795), .I2 (original_data[12]), .I3 (original_data[7]), .I4 (original_data[2])); @@ -35055,8 +34703,8 @@ module sort_3 .INIT(32'b11111011010100011110101001000000)) \N55_18[3] ( .Z (N55[3]), - .I0 (_N23329), - .I1 (_N96015), + .I0 (_N17669), + .I1 (_N96795), .I2 (original_data[13]), .I3 (original_data[8]), .I4 (original_data[3])); @@ -35066,8 +34714,8 @@ module sort_3 .INIT(32'b11111011010100011110101001000000)) \N55_18[4] ( .Z (N55[4]), - .I0 (_N23329), - .I1 (_N96015), + .I0 (_N17669), + .I1 (_N96795), .I2 (original_data[14]), .I3 (original_data[9]), .I4 (original_data[4])); @@ -35076,7 +34724,7 @@ module sort_3 GTP_LUT4 /* N68_10_1 */ #( .INIT(16'b0011100000001000)) N68_10_1 ( - .Z (_N23915), + .Z (_N24186), .I0 (N4), .I1 (N5), .I2 (N8), @@ -35086,7 +34734,7 @@ module sort_3 GTP_LUT4 /* N68_14_1 */ #( .INIT(16'b0100001000100010)) N68_14_1 ( - .Z (_N23919), + .Z (_N24190), .I0 (N4), .I1 (N5), .I2 (N8), @@ -35097,8 +34745,8 @@ module sort_3 .INIT(32'b11110101111001001011000110100000)) \N68_17[0] ( .Z (N68[0]), - .I0 (_N23915), - .I1 (_N23919), + .I0 (_N24186), + .I1 (_N24190), .I2 (original_data[10]), .I3 (original_data[5]), .I4 (original_data[0])); @@ -35108,8 +34756,8 @@ module sort_3 .INIT(32'b11110101111001001011000110100000)) \N68_17[1] ( .Z (N68[1]), - .I0 (_N23915), - .I1 (_N23919), + .I0 (_N24186), + .I1 (_N24190), .I2 (original_data[11]), .I3 (original_data[6]), .I4 (original_data[1])); @@ -35119,8 +34767,8 @@ module sort_3 .INIT(32'b11110101111001001011000110100000)) \N68_17[2] ( .Z (N68[2]), - .I0 (_N23915), - .I1 (_N23919), + .I0 (_N24186), + .I1 (_N24190), .I2 (original_data[12]), .I3 (original_data[7]), .I4 (original_data[2])); @@ -35130,8 +34778,8 @@ module sort_3 .INIT(32'b11110101111001001011000110100000)) \N68_17[3] ( .Z (N68[3]), - .I0 (_N23915), - .I1 (_N23919), + .I0 (_N24186), + .I1 (_N24190), .I2 (original_data[13]), .I3 (original_data[8]), .I4 (original_data[3])); @@ -35141,8 +34789,8 @@ module sort_3 .INIT(32'b11110101111001001011000110100000)) \N68_17[4] ( .Z (N68[4]), - .I0 (_N23915), - .I1 (_N23919), + .I0 (_N24186), + .I1 (_N24190), .I2 (original_data[14]), .I3 (original_data[9]), .I4 (original_data[4])); @@ -35381,10 +35029,10 @@ module sort_3_unq24 wire [4:0] N55; wire [4:0] N68; wire [4:0] N73; - wire _N25224; - wire _N25278; - wire _N25282; - wire _N96128; + wire _N17690; + wire _N17694; + wire _N23644; + wire _N96906; GTP_LUT5CARRY /* \N4.lt_0 */ #( .INIT(32'b00100000111100100000000000000000), @@ -35639,7 +35287,7 @@ module sort_3_unq24 GTP_LUT4 /* N55_9 */ #( .INIT(16'b1100101010101010)) N55_9 ( - .Z (_N96128), + .Z (_N96906), .I0 (N4), .I1 (N5), .I2 (N8), @@ -35649,7 +35297,7 @@ module sort_3_unq24 GTP_LUT4 /* N55_11_1 */ #( .INIT(16'b0000101000101010)) N55_11_1 ( - .Z (_N25224), + .Z (_N23644), .I0 (N4), .I1 (N5), .I2 (N8), @@ -35660,8 +35308,8 @@ module sort_3_unq24 .INIT(32'b11111011010100011110101001000000)) \N55_18[0] ( .Z (N55[0]), - .I0 (_N25224), - .I1 (_N96128), + .I0 (_N23644), + .I1 (_N96906), .I2 (original_data[10]), .I3 (original_data[5]), .I4 (original_data[0])); @@ -35671,8 +35319,8 @@ module sort_3_unq24 .INIT(32'b11111011010100011110101001000000)) \N55_18[1] ( .Z (N55[1]), - .I0 (_N25224), - .I1 (_N96128), + .I0 (_N23644), + .I1 (_N96906), .I2 (original_data[11]), .I3 (original_data[6]), .I4 (original_data[1])); @@ -35682,8 +35330,8 @@ module sort_3_unq24 .INIT(32'b11111011010100011110101001000000)) \N55_18[2] ( .Z (N55[2]), - .I0 (_N25224), - .I1 (_N96128), + .I0 (_N23644), + .I1 (_N96906), .I2 (original_data[12]), .I3 (original_data[7]), .I4 (original_data[2])); @@ -35693,8 +35341,8 @@ module sort_3_unq24 .INIT(32'b11111011010100011110101001000000)) \N55_18[3] ( .Z (N55[3]), - .I0 (_N25224), - .I1 (_N96128), + .I0 (_N23644), + .I1 (_N96906), .I2 (original_data[13]), .I3 (original_data[8]), .I4 (original_data[3])); @@ -35704,87 +35352,89 @@ module sort_3_unq24 .INIT(32'b11111011010100011110101001000000)) \N55_18[4] ( .Z (N55[4]), - .I0 (_N25224), - .I1 (_N96128), + .I0 (_N23644), + .I1 (_N96906), .I2 (original_data[14]), .I3 (original_data[9]), .I4 (original_data[4])); // LUT = (I0&I3)|(~I0&~I1&I4)|(~I0&I1&I2) ; - GTP_LUT4 /* N68_10_1 */ #( - .INIT(16'b0011100000001000)) - N68_10_1 ( - .Z (_N25278), + GTP_LUT4 /* N68_1 */ #( + .INIT(16'b0100001000100010)) + N68_1 ( + .Z (_N17690), .I0 (N4), .I1 (N5), .I2 (N8), .I3 (N15)); - // LUT = (I0&I1&~I2)|(~I1&I2&I3) ; + // LUT = (I0&~I1&~I3)|(I0&~I1&~I2)|(~I0&I1&I2&I3) ; + // ../../sources/designs/image_filiter/sort_3.v:23 - GTP_LUT4 /* N68_14_1 */ #( - .INIT(16'b0100001000100010)) - N68_14_1 ( - .Z (_N25282), + GTP_LUT4 /* N68_7 */ #( + .INIT(16'b0011100000001000)) + N68_7 ( + .Z (_N17694), .I0 (N4), .I1 (N5), .I2 (N8), .I3 (N15)); - // LUT = (I0&~I1&~I3)|(I0&~I1&~I2)|(~I0&I1&I2&I3) ; + // LUT = (I0&I1&~I2)|(~I1&I2&I3) ; + // ../../sources/designs/image_filiter/sort_3.v:23 GTP_LUT5 /* \N68_17[0] */ #( - .INIT(32'b11110101111001001011000110100000)) + .INIT(32'b11110011111000101101000111000000)) \N68_17[0] ( .Z (N68[0]), - .I0 (_N25278), - .I1 (_N25282), + .I0 (_N17690), + .I1 (_N17694), .I2 (original_data[10]), .I3 (original_data[5]), .I4 (original_data[0])); - // LUT = (I0&I2)|(~I0&~I1&I3)|(~I0&I1&I4) ; + // LUT = (I1&I2)|(~I0&~I1&I3)|(I0&~I1&I4) ; GTP_LUT5 /* \N68_17[1] */ #( - .INIT(32'b11110101111001001011000110100000)) + .INIT(32'b11110011111000101101000111000000)) \N68_17[1] ( .Z (N68[1]), - .I0 (_N25278), - .I1 (_N25282), + .I0 (_N17690), + .I1 (_N17694), .I2 (original_data[11]), .I3 (original_data[6]), .I4 (original_data[1])); - // LUT = (I0&I2)|(~I0&~I1&I3)|(~I0&I1&I4) ; + // LUT = (I1&I2)|(~I0&~I1&I3)|(I0&~I1&I4) ; GTP_LUT5 /* \N68_17[2] */ #( - .INIT(32'b11110101111001001011000110100000)) + .INIT(32'b11110011111000101101000111000000)) \N68_17[2] ( .Z (N68[2]), - .I0 (_N25278), - .I1 (_N25282), + .I0 (_N17690), + .I1 (_N17694), .I2 (original_data[12]), .I3 (original_data[7]), .I4 (original_data[2])); - // LUT = (I0&I2)|(~I0&~I1&I3)|(~I0&I1&I4) ; + // LUT = (I1&I2)|(~I0&~I1&I3)|(I0&~I1&I4) ; GTP_LUT5 /* \N68_17[3] */ #( - .INIT(32'b11110101111001001011000110100000)) + .INIT(32'b11110011111000101101000111000000)) \N68_17[3] ( .Z (N68[3]), - .I0 (_N25278), - .I1 (_N25282), + .I0 (_N17690), + .I1 (_N17694), .I2 (original_data[13]), .I3 (original_data[8]), .I4 (original_data[3])); - // LUT = (I0&I2)|(~I0&~I1&I3)|(~I0&I1&I4) ; + // LUT = (I1&I2)|(~I0&~I1&I3)|(I0&~I1&I4) ; GTP_LUT5 /* \N68_17[4] */ #( - .INIT(32'b11110101111001001011000110100000)) + .INIT(32'b11110011111000101101000111000000)) \N68_17[4] ( .Z (N68[4]), - .I0 (_N25278), - .I1 (_N25282), + .I0 (_N17690), + .I1 (_N17694), .I2 (original_data[14]), .I3 (original_data[9]), .I4 (original_data[4])); - // LUT = (I0&I2)|(~I0&~I1&I3)|(~I0&I1&I4) ; + // LUT = (I1&I2)|(~I0&~I1&I3)|(I0&~I1&I4) ; GTP_LUT5M /* \N73_6[0] */ #( .INIT(32'b11101010001010101110101000101010)) @@ -36020,9 +35670,9 @@ module sort_3_unq26 wire [4:0] N68; wire [4:0] N73; wire _N17703; + wire _N17707; wire _N17711; - wire _N25264; - wire _N96327; + wire _N97091; GTP_LUT5CARRY /* \N4.lt_0 */ #( .INIT(32'b00100000111100100000000000000000), @@ -36288,7 +35938,7 @@ module sort_3_unq26 GTP_LUT4 /* N55_9 */ #( .INIT(16'b1100101010101010)) N55_9 ( - .Z (_N96327), + .Z (_N97091), .I0 (N4), .I1 (N5), .I2 (N8), @@ -36300,7 +35950,7 @@ module sort_3_unq26 \N55_18[0] ( .Z (N55[0]), .I0 (_N17703), - .I1 (_N96327), + .I1 (_N97091), .I2 (original_data[10]), .I3 (original_data[5]), .I4 (original_data[0])); @@ -36311,7 +35961,7 @@ module sort_3_unq26 \N55_18[1] ( .Z (N55[1]), .I0 (_N17703), - .I1 (_N96327), + .I1 (_N97091), .I2 (original_data[11]), .I3 (original_data[6]), .I4 (original_data[1])); @@ -36322,7 +35972,7 @@ module sort_3_unq26 \N55_18[2] ( .Z (N55[2]), .I0 (_N17703), - .I1 (_N96327), + .I1 (_N97091), .I2 (original_data[12]), .I3 (original_data[7]), .I4 (original_data[2])); @@ -36333,7 +35983,7 @@ module sort_3_unq26 \N55_18[3] ( .Z (N55[3]), .I0 (_N17703), - .I1 (_N96327), + .I1 (_N97091), .I2 (original_data[13]), .I3 (original_data[8]), .I4 (original_data[3])); @@ -36344,87 +35994,88 @@ module sort_3_unq26 \N55_18[4] ( .Z (N55[4]), .I0 (_N17703), - .I1 (_N96327), + .I1 (_N97091), .I2 (original_data[14]), .I3 (original_data[9]), .I4 (original_data[4])); // LUT = (I0&I3)|(~I0&~I1&I4)|(~I0&I1&I2) ; - GTP_LUT4 /* N68_7 */ #( - .INIT(16'b0011100000001000)) - N68_7 ( - .Z (_N17711), + GTP_LUT4 /* N68_1 */ #( + .INIT(16'b0100001000100010)) + N68_1 ( + .Z (_N17707), .I0 (N4), .I1 (N5), .I2 (N8), .I3 (N15)); - // LUT = (I0&I1&~I2)|(~I1&I2&I3) ; + // LUT = (I0&~I1&~I3)|(I0&~I1&~I2)|(~I0&I1&I2&I3) ; // ../../sources/designs/image_filiter/sort_3.v:23 - GTP_LUT4 /* N68_14_1 */ #( - .INIT(16'b0100001000100010)) - N68_14_1 ( - .Z (_N25264), + GTP_LUT4 /* N68_7 */ #( + .INIT(16'b0011100000001000)) + N68_7 ( + .Z (_N17711), .I0 (N4), .I1 (N5), .I2 (N8), .I3 (N15)); - // LUT = (I0&~I1&~I3)|(I0&~I1&~I2)|(~I0&I1&I2&I3) ; + // LUT = (I0&I1&~I2)|(~I1&I2&I3) ; + // ../../sources/designs/image_filiter/sort_3.v:23 GTP_LUT5 /* \N68_17[0] */ #( - .INIT(32'b11110101111001001011000110100000)) + .INIT(32'b11110011111000101101000111000000)) \N68_17[0] ( .Z (N68[0]), - .I0 (_N17711), - .I1 (_N25264), + .I0 (_N17707), + .I1 (_N17711), .I2 (original_data[10]), .I3 (original_data[5]), .I4 (original_data[0])); - // LUT = (I0&I2)|(~I0&~I1&I3)|(~I0&I1&I4) ; + // LUT = (I1&I2)|(~I0&~I1&I3)|(I0&~I1&I4) ; GTP_LUT5 /* \N68_17[1] */ #( - .INIT(32'b11110101111001001011000110100000)) + .INIT(32'b11110011111000101101000111000000)) \N68_17[1] ( .Z (N68[1]), - .I0 (_N17711), - .I1 (_N25264), + .I0 (_N17707), + .I1 (_N17711), .I2 (original_data[11]), .I3 (original_data[6]), .I4 (original_data[1])); - // LUT = (I0&I2)|(~I0&~I1&I3)|(~I0&I1&I4) ; + // LUT = (I1&I2)|(~I0&~I1&I3)|(I0&~I1&I4) ; GTP_LUT5 /* \N68_17[2] */ #( - .INIT(32'b11110101111001001011000110100000)) + .INIT(32'b11110011111000101101000111000000)) \N68_17[2] ( .Z (N68[2]), - .I0 (_N17711), - .I1 (_N25264), + .I0 (_N17707), + .I1 (_N17711), .I2 (original_data[12]), .I3 (original_data[7]), .I4 (original_data[2])); - // LUT = (I0&I2)|(~I0&~I1&I3)|(~I0&I1&I4) ; + // LUT = (I1&I2)|(~I0&~I1&I3)|(I0&~I1&I4) ; GTP_LUT5 /* \N68_17[3] */ #( - .INIT(32'b11110101111001001011000110100000)) + .INIT(32'b11110011111000101101000111000000)) \N68_17[3] ( .Z (N68[3]), - .I0 (_N17711), - .I1 (_N25264), + .I0 (_N17707), + .I1 (_N17711), .I2 (original_data[13]), .I3 (original_data[8]), .I4 (original_data[3])); - // LUT = (I0&I2)|(~I0&~I1&I3)|(~I0&I1&I4) ; + // LUT = (I1&I2)|(~I0&~I1&I3)|(I0&~I1&I4) ; GTP_LUT5 /* \N68_17[4] */ #( - .INIT(32'b11110101111001001011000110100000)) + .INIT(32'b11110011111000101101000111000000)) \N68_17[4] ( .Z (N68[4]), - .I0 (_N17711), - .I1 (_N25264), + .I0 (_N17707), + .I1 (_N17711), .I2 (original_data[14]), .I3 (original_data[9]), .I4 (original_data[4])); - // LUT = (I0&I2)|(~I0&~I1&I3)|(~I0&I1&I4) ; + // LUT = (I1&I2)|(~I0&~I1&I3)|(I0&~I1&I4) ; GTP_LUT5M /* \N73_6[0] */ #( .INIT(32'b11101010001010101110101000101010)) @@ -36687,8 +36338,8 @@ module median_finder9 wire N167; wire [5:0] \N167.co ; wire [4:0] N188; - wire _N102188_1; - wire _N102685_1; + wire _N103145_1; + wire _N103223_1; wire [4:0] max_of_vector_max; wire [4:0] max_of_vector_min; wire [4:0] med_of_vector_med; @@ -37192,7 +36843,7 @@ module median_finder9 .I1 (\vector_med[1] [0] ), .I2 (N83), .I3 (N87), - .I4 (_N102188_1), + .I4 (_N103223_1), .ID (\vector_med[2] [0] )); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; @@ -37204,7 +36855,7 @@ module median_finder9 .I1 (\vector_med[1] [1] ), .I2 (N83), .I3 (N87), - .I4 (_N102188_1), + .I4 (_N103223_1), .ID (\vector_med[2] [1] )); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; @@ -37216,7 +36867,7 @@ module median_finder9 .I1 (\vector_med[1] [2] ), .I2 (N83), .I3 (N87), - .I4 (_N102188_1), + .I4 (_N103223_1), .ID (\vector_med[2] [2] )); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; @@ -37228,7 +36879,7 @@ module median_finder9 .I1 (\vector_med[1] [3] ), .I2 (N83), .I3 (N87), - .I4 (_N102188_1), + .I4 (_N103223_1), .ID (\vector_med[2] [3] )); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; @@ -37240,14 +36891,14 @@ module median_finder9 .I1 (\vector_med[1] [4] ), .I2 (N83), .I3 (N87), - .I4 (_N102188_1), + .I4 (_N103223_1), .ID (\vector_med[2] [4] )); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; GTP_LUT3 /* N104_40 */ #( .INIT(8'b11100111)) N104_40 ( - .Z (_N102188_1), + .Z (_N103223_1), .I0 (N83), .I1 (N85), .I2 (N87)); @@ -37741,7 +37392,7 @@ module median_finder9 .I1 (med_of_vector_med[0]), .I2 (N155), .I3 (N167), - .I4 (_N102685_1), + .I4 (_N103145_1), .ID (min_of_vector_max[0])); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; @@ -37753,7 +37404,7 @@ module median_finder9 .I1 (med_of_vector_med[1]), .I2 (N155), .I3 (N167), - .I4 (_N102685_1), + .I4 (_N103145_1), .ID (min_of_vector_max[1])); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; @@ -37765,7 +37416,7 @@ module median_finder9 .I1 (med_of_vector_med[2]), .I2 (N155), .I3 (N167), - .I4 (_N102685_1), + .I4 (_N103145_1), .ID (min_of_vector_max[2])); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; @@ -37777,7 +37428,7 @@ module median_finder9 .I1 (med_of_vector_med[3]), .I2 (N155), .I3 (N167), - .I4 (_N102685_1), + .I4 (_N103145_1), .ID (min_of_vector_max[3])); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; @@ -37789,14 +37440,14 @@ module median_finder9 .I1 (med_of_vector_med[4]), .I2 (N155), .I3 (N167), - .I4 (_N102685_1), + .I4 (_N103145_1), .ID (min_of_vector_max[4])); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; GTP_LUT3 /* N188_40 */ #( .INIT(8'b11100111)) N188_40 ( - .Z (_N102685_1), + .Z (_N103145_1), .I0 (N155), .I1 (N161), .I2 (N167)); @@ -38246,10 +37897,10 @@ module sort_3_1 wire [5:0] N55; wire [5:0] N68; wire [5:0] N73; - wire _N25337; - wire _N25654; - wire _N25658; - wire _N96681; + wire _N17724; + wire _N22527; + wire _N25169; + wire _N97438; GTP_LUT5CARRY /* \N4.lt_0 */ #( .INIT(32'b00100000111100100000000000000000), @@ -38504,7 +38155,7 @@ module sort_3_1 GTP_LUT4 /* N55_9 */ #( .INIT(16'b1100101010101010)) N55_9 ( - .Z (_N96681), + .Z (_N97438), .I0 (N4), .I1 (N5), .I2 (N8), @@ -38514,7 +38165,7 @@ module sort_3_1 GTP_LUT4 /* N55_11_1 */ #( .INIT(16'b0000101000101010)) N55_11_1 ( - .Z (_N25337), + .Z (_N22527), .I0 (N4), .I1 (N5), .I2 (N8), @@ -38525,8 +38176,8 @@ module sort_3_1 .INIT(32'b11111011010100011110101001000000)) \N55_18[0] ( .Z (N55[0]), - .I0 (_N25337), - .I1 (_N96681), + .I0 (_N22527), + .I1 (_N97438), .I2 (original_data[12]), .I3 (original_data[6]), .I4 (original_data[0])); @@ -38536,8 +38187,8 @@ module sort_3_1 .INIT(32'b11111011010100011110101001000000)) \N55_18[1] ( .Z (N55[1]), - .I0 (_N25337), - .I1 (_N96681), + .I0 (_N22527), + .I1 (_N97438), .I2 (original_data[13]), .I3 (original_data[7]), .I4 (original_data[1])); @@ -38547,8 +38198,8 @@ module sort_3_1 .INIT(32'b11111011010100011110101001000000)) \N55_18[2] ( .Z (N55[2]), - .I0 (_N25337), - .I1 (_N96681), + .I0 (_N22527), + .I1 (_N97438), .I2 (original_data[14]), .I3 (original_data[8]), .I4 (original_data[2])); @@ -38558,8 +38209,8 @@ module sort_3_1 .INIT(32'b11111011010100011110101001000000)) \N55_18[3] ( .Z (N55[3]), - .I0 (_N25337), - .I1 (_N96681), + .I0 (_N22527), + .I1 (_N97438), .I2 (original_data[15]), .I3 (original_data[9]), .I4 (original_data[3])); @@ -38569,8 +38220,8 @@ module sort_3_1 .INIT(32'b11111011010100011110101001000000)) \N55_18[4] ( .Z (N55[4]), - .I0 (_N25337), - .I1 (_N96681), + .I0 (_N22527), + .I1 (_N97438), .I2 (original_data[16]), .I3 (original_data[10]), .I4 (original_data[4])); @@ -38580,98 +38231,99 @@ module sort_3_1 .INIT(32'b11111011010100011110101001000000)) \N55_18[5] ( .Z (N55[5]), - .I0 (_N25337), - .I1 (_N96681), + .I0 (_N22527), + .I1 (_N97438), .I2 (original_data[17]), .I3 (original_data[11]), .I4 (original_data[5])); // LUT = (I0&I3)|(~I0&~I1&I4)|(~I0&I1&I2) ; - GTP_LUT4 /* N68_10_1 */ #( - .INIT(16'b0011100000001000)) - N68_10_1 ( - .Z (_N25654), + GTP_LUT4 /* N68_1 */ #( + .INIT(16'b0100001000100010)) + N68_1 ( + .Z (_N17724), .I0 (N4), .I1 (N5), .I2 (N8), .I3 (N15)); - // LUT = (I0&I1&~I2)|(~I1&I2&I3) ; + // LUT = (I0&~I1&~I3)|(I0&~I1&~I2)|(~I0&I1&I2&I3) ; + // ../../sources/designs/image_filiter/sort_3.v:23 - GTP_LUT4 /* N68_14_1 */ #( - .INIT(16'b0100001000100010)) - N68_14_1 ( - .Z (_N25658), + GTP_LUT4 /* N68_10_1 */ #( + .INIT(16'b0011100000001000)) + N68_10_1 ( + .Z (_N25169), .I0 (N4), .I1 (N5), .I2 (N8), .I3 (N15)); - // LUT = (I0&~I1&~I3)|(I0&~I1&~I2)|(~I0&I1&I2&I3) ; + // LUT = (I0&I1&~I2)|(~I1&I2&I3) ; GTP_LUT5 /* \N68_17[0] */ #( - .INIT(32'b11110101111001001011000110100000)) + .INIT(32'b11110011111000101101000111000000)) \N68_17[0] ( .Z (N68[0]), - .I0 (_N25654), - .I1 (_N25658), + .I0 (_N17724), + .I1 (_N25169), .I2 (original_data[12]), .I3 (original_data[6]), .I4 (original_data[0])); - // LUT = (I0&I2)|(~I0&~I1&I3)|(~I0&I1&I4) ; + // LUT = (I1&I2)|(~I0&~I1&I3)|(I0&~I1&I4) ; GTP_LUT5 /* \N68_17[1] */ #( - .INIT(32'b11110101111001001011000110100000)) + .INIT(32'b11110011111000101101000111000000)) \N68_17[1] ( .Z (N68[1]), - .I0 (_N25654), - .I1 (_N25658), + .I0 (_N17724), + .I1 (_N25169), .I2 (original_data[13]), .I3 (original_data[7]), .I4 (original_data[1])); - // LUT = (I0&I2)|(~I0&~I1&I3)|(~I0&I1&I4) ; + // LUT = (I1&I2)|(~I0&~I1&I3)|(I0&~I1&I4) ; GTP_LUT5 /* \N68_17[2] */ #( - .INIT(32'b11110101111001001011000110100000)) + .INIT(32'b11110011111000101101000111000000)) \N68_17[2] ( .Z (N68[2]), - .I0 (_N25654), - .I1 (_N25658), + .I0 (_N17724), + .I1 (_N25169), .I2 (original_data[14]), .I3 (original_data[8]), .I4 (original_data[2])); - // LUT = (I0&I2)|(~I0&~I1&I3)|(~I0&I1&I4) ; + // LUT = (I1&I2)|(~I0&~I1&I3)|(I0&~I1&I4) ; GTP_LUT5 /* \N68_17[3] */ #( - .INIT(32'b11110101111001001011000110100000)) + .INIT(32'b11110011111000101101000111000000)) \N68_17[3] ( .Z (N68[3]), - .I0 (_N25654), - .I1 (_N25658), + .I0 (_N17724), + .I1 (_N25169), .I2 (original_data[15]), .I3 (original_data[9]), .I4 (original_data[3])); - // LUT = (I0&I2)|(~I0&~I1&I3)|(~I0&I1&I4) ; + // LUT = (I1&I2)|(~I0&~I1&I3)|(I0&~I1&I4) ; GTP_LUT5 /* \N68_17[4] */ #( - .INIT(32'b11110101111001001011000110100000)) + .INIT(32'b11110011111000101101000111000000)) \N68_17[4] ( .Z (N68[4]), - .I0 (_N25654), - .I1 (_N25658), + .I0 (_N17724), + .I1 (_N25169), .I2 (original_data[16]), .I3 (original_data[10]), .I4 (original_data[4])); - // LUT = (I0&I2)|(~I0&~I1&I3)|(~I0&I1&I4) ; + // LUT = (I1&I2)|(~I0&~I1&I3)|(I0&~I1&I4) ; GTP_LUT5 /* \N68_17[5] */ #( - .INIT(32'b11110101111001001011000110100000)) + .INIT(32'b11110011111000101101000111000000)) \N68_17[5] ( .Z (N68[5]), - .I0 (_N25654), - .I1 (_N25658), + .I0 (_N17724), + .I1 (_N25169), .I2 (original_data[17]), .I3 (original_data[11]), .I4 (original_data[5])); - // LUT = (I0&I2)|(~I0&~I1&I3)|(~I0&I1&I4) ; + // LUT = (I1&I2)|(~I0&~I1&I3)|(I0&~I1&I4) ; GTP_LUT5M /* \N73_6[0] */ #( .INIT(32'b11101010001010101110101000101010)) @@ -38948,10 +38600,10 @@ module sort_3_1_unq12 wire [5:0] N55; wire [5:0] N68; wire [5:0] N73; - wire _N22609; - wire _N25472; - wire _N25476; - wire _N96683; + wire _N17741; + wire _N17745; + wire _N21069; + wire _N97440; GTP_LUT5CARRY /* \N4.lt_0 */ #( .INIT(32'b00100000111100100000000000000000), @@ -39206,7 +38858,7 @@ module sort_3_1_unq12 GTP_LUT4 /* N55_9 */ #( .INIT(16'b1100101010101010)) N55_9 ( - .Z (_N96683), + .Z (_N97440), .I0 (N4), .I1 (N5), .I2 (N8), @@ -39216,7 +38868,7 @@ module sort_3_1_unq12 GTP_LUT4 /* N55_11_1 */ #( .INIT(16'b0000101000101010)) N55_11_1 ( - .Z (_N22609), + .Z (_N21069), .I0 (N4), .I1 (N5), .I2 (N8), @@ -39227,8 +38879,8 @@ module sort_3_1_unq12 .INIT(32'b11111011010100011110101001000000)) \N55_18[0] ( .Z (N55[0]), - .I0 (_N22609), - .I1 (_N96683), + .I0 (_N21069), + .I1 (_N97440), .I2 (original_data[12]), .I3 (original_data[6]), .I4 (original_data[0])); @@ -39238,8 +38890,8 @@ module sort_3_1_unq12 .INIT(32'b11111011010100011110101001000000)) \N55_18[1] ( .Z (N55[1]), - .I0 (_N22609), - .I1 (_N96683), + .I0 (_N21069), + .I1 (_N97440), .I2 (original_data[13]), .I3 (original_data[7]), .I4 (original_data[1])); @@ -39249,8 +38901,8 @@ module sort_3_1_unq12 .INIT(32'b11111011010100011110101001000000)) \N55_18[2] ( .Z (N55[2]), - .I0 (_N22609), - .I1 (_N96683), + .I0 (_N21069), + .I1 (_N97440), .I2 (original_data[14]), .I3 (original_data[8]), .I4 (original_data[2])); @@ -39260,8 +38912,8 @@ module sort_3_1_unq12 .INIT(32'b11111011010100011110101001000000)) \N55_18[3] ( .Z (N55[3]), - .I0 (_N22609), - .I1 (_N96683), + .I0 (_N21069), + .I1 (_N97440), .I2 (original_data[15]), .I3 (original_data[9]), .I4 (original_data[3])); @@ -39271,8 +38923,8 @@ module sort_3_1_unq12 .INIT(32'b11111011010100011110101001000000)) \N55_18[4] ( .Z (N55[4]), - .I0 (_N22609), - .I1 (_N96683), + .I0 (_N21069), + .I1 (_N97440), .I2 (original_data[16]), .I3 (original_data[10]), .I4 (original_data[4])); @@ -39282,98 +38934,100 @@ module sort_3_1_unq12 .INIT(32'b11111011010100011110101001000000)) \N55_18[5] ( .Z (N55[5]), - .I0 (_N22609), - .I1 (_N96683), + .I0 (_N21069), + .I1 (_N97440), .I2 (original_data[17]), .I3 (original_data[11]), .I4 (original_data[5])); // LUT = (I0&I3)|(~I0&~I1&I4)|(~I0&I1&I2) ; - GTP_LUT4 /* N68_10_1 */ #( - .INIT(16'b0011100000001000)) - N68_10_1 ( - .Z (_N25472), + GTP_LUT4 /* N68_1 */ #( + .INIT(16'b0100001000100010)) + N68_1 ( + .Z (_N17741), .I0 (N4), .I1 (N5), .I2 (N8), .I3 (N15)); - // LUT = (I0&I1&~I2)|(~I1&I2&I3) ; + // LUT = (I0&~I1&~I3)|(I0&~I1&~I2)|(~I0&I1&I2&I3) ; + // ../../sources/designs/image_filiter/sort_3.v:23 - GTP_LUT4 /* N68_14_1 */ #( - .INIT(16'b0100001000100010)) - N68_14_1 ( - .Z (_N25476), + GTP_LUT4 /* N68_7 */ #( + .INIT(16'b0011100000001000)) + N68_7 ( + .Z (_N17745), .I0 (N4), .I1 (N5), .I2 (N8), .I3 (N15)); - // LUT = (I0&~I1&~I3)|(I0&~I1&~I2)|(~I0&I1&I2&I3) ; + // LUT = (I0&I1&~I2)|(~I1&I2&I3) ; + // ../../sources/designs/image_filiter/sort_3.v:23 GTP_LUT5 /* \N68_17[0] */ #( - .INIT(32'b11110101111001001011000110100000)) + .INIT(32'b11110011111000101101000111000000)) \N68_17[0] ( .Z (N68[0]), - .I0 (_N25472), - .I1 (_N25476), + .I0 (_N17741), + .I1 (_N17745), .I2 (original_data[12]), .I3 (original_data[6]), .I4 (original_data[0])); - // LUT = (I0&I2)|(~I0&~I1&I3)|(~I0&I1&I4) ; + // LUT = (I1&I2)|(~I0&~I1&I3)|(I0&~I1&I4) ; GTP_LUT5 /* \N68_17[1] */ #( - .INIT(32'b11110101111001001011000110100000)) + .INIT(32'b11110011111000101101000111000000)) \N68_17[1] ( .Z (N68[1]), - .I0 (_N25472), - .I1 (_N25476), + .I0 (_N17741), + .I1 (_N17745), .I2 (original_data[13]), .I3 (original_data[7]), .I4 (original_data[1])); - // LUT = (I0&I2)|(~I0&~I1&I3)|(~I0&I1&I4) ; + // LUT = (I1&I2)|(~I0&~I1&I3)|(I0&~I1&I4) ; GTP_LUT5 /* \N68_17[2] */ #( - .INIT(32'b11110101111001001011000110100000)) + .INIT(32'b11110011111000101101000111000000)) \N68_17[2] ( .Z (N68[2]), - .I0 (_N25472), - .I1 (_N25476), + .I0 (_N17741), + .I1 (_N17745), .I2 (original_data[14]), .I3 (original_data[8]), .I4 (original_data[2])); - // LUT = (I0&I2)|(~I0&~I1&I3)|(~I0&I1&I4) ; + // LUT = (I1&I2)|(~I0&~I1&I3)|(I0&~I1&I4) ; GTP_LUT5 /* \N68_17[3] */ #( - .INIT(32'b11110101111001001011000110100000)) + .INIT(32'b11110011111000101101000111000000)) \N68_17[3] ( .Z (N68[3]), - .I0 (_N25472), - .I1 (_N25476), + .I0 (_N17741), + .I1 (_N17745), .I2 (original_data[15]), .I3 (original_data[9]), .I4 (original_data[3])); - // LUT = (I0&I2)|(~I0&~I1&I3)|(~I0&I1&I4) ; + // LUT = (I1&I2)|(~I0&~I1&I3)|(I0&~I1&I4) ; GTP_LUT5 /* \N68_17[4] */ #( - .INIT(32'b11110101111001001011000110100000)) + .INIT(32'b11110011111000101101000111000000)) \N68_17[4] ( .Z (N68[4]), - .I0 (_N25472), - .I1 (_N25476), + .I0 (_N17741), + .I1 (_N17745), .I2 (original_data[16]), .I3 (original_data[10]), .I4 (original_data[4])); - // LUT = (I0&I2)|(~I0&~I1&I3)|(~I0&I1&I4) ; + // LUT = (I1&I2)|(~I0&~I1&I3)|(I0&~I1&I4) ; GTP_LUT5 /* \N68_17[5] */ #( - .INIT(32'b11110101111001001011000110100000)) + .INIT(32'b11110011111000101101000111000000)) \N68_17[5] ( .Z (N68[5]), - .I0 (_N25472), - .I1 (_N25476), + .I0 (_N17741), + .I1 (_N17745), .I2 (original_data[17]), .I3 (original_data[11]), .I4 (original_data[5])); - // LUT = (I0&I2)|(~I0&~I1&I3)|(~I0&I1&I4) ; + // LUT = (I1&I2)|(~I0&~I1&I3)|(I0&~I1&I4) ; GTP_LUT5M /* \N73_6[0] */ #( .INIT(32'b11101010001010101110101000101010)) @@ -39650,10 +39304,10 @@ module sort_3_1_unq14 wire [5:0] N55; wire [5:0] N68; wire [5:0] N73; - wire _N19938; - wire _N19942; - wire _N21084; - wire _N96685; + wire _N17754; + wire _N20579; + wire _N20583; + wire _N97442; GTP_LUT5CARRY /* \N4.lt_0 */ #( .INIT(32'b00100000111100100000000000000000), @@ -39905,32 +39559,33 @@ module sort_3_1_unq14 // LUT = I0&I1 ; // ../../sources/designs/image_filiter/sort_3.v:38 - GTP_LUT4 /* N55_9 */ #( - .INIT(16'b1100101010101010)) - N55_9 ( - .Z (_N96685), + GTP_LUT4 /* N55_7 */ #( + .INIT(16'b0000101000101010)) + N55_7 ( + .Z (_N17754), .I0 (N4), .I1 (N5), .I2 (N8), .I3 (N15)); - // LUT = (I0&~I3)|(I0&~I2)|(I1&I2&I3) ; + // LUT = (I0&~I2)|(I0&~I1&~I3) ; + // ../../sources/designs/image_filiter/sort_3.v:23 - GTP_LUT4 /* N55_11_1 */ #( - .INIT(16'b0000101000101010)) - N55_11_1 ( - .Z (_N21084), + GTP_LUT4 /* N55_9 */ #( + .INIT(16'b1100101010101010)) + N55_9 ( + .Z (_N97442), .I0 (N4), .I1 (N5), .I2 (N8), .I3 (N15)); - // LUT = (I0&~I2)|(I0&~I1&~I3) ; + // LUT = (I0&~I3)|(I0&~I2)|(I1&I2&I3) ; GTP_LUT5 /* \N55_18[0] */ #( .INIT(32'b11111011010100011110101001000000)) \N55_18[0] ( .Z (N55[0]), - .I0 (_N21084), - .I1 (_N96685), + .I0 (_N17754), + .I1 (_N97442), .I2 (original_data[12]), .I3 (original_data[6]), .I4 (original_data[0])); @@ -39940,8 +39595,8 @@ module sort_3_1_unq14 .INIT(32'b11111011010100011110101001000000)) \N55_18[1] ( .Z (N55[1]), - .I0 (_N21084), - .I1 (_N96685), + .I0 (_N17754), + .I1 (_N97442), .I2 (original_data[13]), .I3 (original_data[7]), .I4 (original_data[1])); @@ -39951,8 +39606,8 @@ module sort_3_1_unq14 .INIT(32'b11111011010100011110101001000000)) \N55_18[2] ( .Z (N55[2]), - .I0 (_N21084), - .I1 (_N96685), + .I0 (_N17754), + .I1 (_N97442), .I2 (original_data[14]), .I3 (original_data[8]), .I4 (original_data[2])); @@ -39962,8 +39617,8 @@ module sort_3_1_unq14 .INIT(32'b11111011010100011110101001000000)) \N55_18[3] ( .Z (N55[3]), - .I0 (_N21084), - .I1 (_N96685), + .I0 (_N17754), + .I1 (_N97442), .I2 (original_data[15]), .I3 (original_data[9]), .I4 (original_data[3])); @@ -39973,8 +39628,8 @@ module sort_3_1_unq14 .INIT(32'b11111011010100011110101001000000)) \N55_18[4] ( .Z (N55[4]), - .I0 (_N21084), - .I1 (_N96685), + .I0 (_N17754), + .I1 (_N97442), .I2 (original_data[16]), .I3 (original_data[10]), .I4 (original_data[4])); @@ -39984,8 +39639,8 @@ module sort_3_1_unq14 .INIT(32'b11111011010100011110101001000000)) \N55_18[5] ( .Z (N55[5]), - .I0 (_N21084), - .I1 (_N96685), + .I0 (_N17754), + .I1 (_N97442), .I2 (original_data[17]), .I3 (original_data[11]), .I4 (original_data[5])); @@ -39994,7 +39649,7 @@ module sort_3_1_unq14 GTP_LUT4 /* N68_10_1 */ #( .INIT(16'b0011100000001000)) N68_10_1 ( - .Z (_N19938), + .Z (_N20579), .I0 (N4), .I1 (N5), .I2 (N8), @@ -40004,7 +39659,7 @@ module sort_3_1_unq14 GTP_LUT4 /* N68_14_1 */ #( .INIT(16'b0100001000100010)) N68_14_1 ( - .Z (_N19942), + .Z (_N20583), .I0 (N4), .I1 (N5), .I2 (N8), @@ -40015,8 +39670,8 @@ module sort_3_1_unq14 .INIT(32'b11110101111001001011000110100000)) \N68_17[0] ( .Z (N68[0]), - .I0 (_N19938), - .I1 (_N19942), + .I0 (_N20579), + .I1 (_N20583), .I2 (original_data[12]), .I3 (original_data[6]), .I4 (original_data[0])); @@ -40026,8 +39681,8 @@ module sort_3_1_unq14 .INIT(32'b11110101111001001011000110100000)) \N68_17[1] ( .Z (N68[1]), - .I0 (_N19938), - .I1 (_N19942), + .I0 (_N20579), + .I1 (_N20583), .I2 (original_data[13]), .I3 (original_data[7]), .I4 (original_data[1])); @@ -40037,8 +39692,8 @@ module sort_3_1_unq14 .INIT(32'b11110101111001001011000110100000)) \N68_17[2] ( .Z (N68[2]), - .I0 (_N19938), - .I1 (_N19942), + .I0 (_N20579), + .I1 (_N20583), .I2 (original_data[14]), .I3 (original_data[8]), .I4 (original_data[2])); @@ -40048,8 +39703,8 @@ module sort_3_1_unq14 .INIT(32'b11110101111001001011000110100000)) \N68_17[3] ( .Z (N68[3]), - .I0 (_N19938), - .I1 (_N19942), + .I0 (_N20579), + .I1 (_N20583), .I2 (original_data[15]), .I3 (original_data[9]), .I4 (original_data[3])); @@ -40059,8 +39714,8 @@ module sort_3_1_unq14 .INIT(32'b11110101111001001011000110100000)) \N68_17[4] ( .Z (N68[4]), - .I0 (_N19938), - .I1 (_N19942), + .I0 (_N20579), + .I1 (_N20583), .I2 (original_data[16]), .I3 (original_data[10]), .I4 (original_data[4])); @@ -40070,8 +39725,8 @@ module sort_3_1_unq14 .INIT(32'b11110101111001001011000110100000)) \N68_17[5] ( .Z (N68[5]), - .I0 (_N19938), - .I1 (_N19942), + .I0 (_N20579), + .I1 (_N20583), .I2 (original_data[17]), .I3 (original_data[11]), .I4 (original_data[5])); @@ -40380,8 +40035,8 @@ module median_finder9_1 wire N167; wire [6:0] \N167.co ; wire [5:0] N188; - wire _N102853_1; - wire _N102855_1; + wire _N103692_1; + wire _N103702_1; wire [5:0] max_of_vector_max; wire [5:0] max_of_vector_min; wire [5:0] med_of_vector_med; @@ -40909,7 +40564,7 @@ module median_finder9_1 .I1 (\vector_med[1] [0] ), .I2 (N83), .I3 (N87), - .I4 (_N102853_1), + .I4 (_N103702_1), .ID (\vector_med[2] [0] )); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; @@ -40921,7 +40576,7 @@ module median_finder9_1 .I1 (\vector_med[1] [1] ), .I2 (N83), .I3 (N87), - .I4 (_N102853_1), + .I4 (_N103702_1), .ID (\vector_med[2] [1] )); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; @@ -40933,7 +40588,7 @@ module median_finder9_1 .I1 (\vector_med[1] [2] ), .I2 (N83), .I3 (N87), - .I4 (_N102853_1), + .I4 (_N103702_1), .ID (\vector_med[2] [2] )); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; @@ -40945,7 +40600,7 @@ module median_finder9_1 .I1 (\vector_med[1] [3] ), .I2 (N83), .I3 (N87), - .I4 (_N102853_1), + .I4 (_N103702_1), .ID (\vector_med[2] [3] )); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; @@ -40957,7 +40612,7 @@ module median_finder9_1 .I1 (\vector_med[1] [4] ), .I2 (N83), .I3 (N87), - .I4 (_N102853_1), + .I4 (_N103702_1), .ID (\vector_med[2] [4] )); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; @@ -40969,14 +40624,14 @@ module median_finder9_1 .I1 (\vector_med[1] [5] ), .I2 (N83), .I3 (N87), - .I4 (_N102853_1), + .I4 (_N103702_1), .ID (\vector_med[2] [5] )); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; GTP_LUT3 /* N104_40 */ #( .INIT(8'b11100111)) N104_40 ( - .Z (_N102853_1), + .Z (_N103702_1), .I0 (N83), .I1 (N85), .I2 (N87)); @@ -41494,7 +41149,7 @@ module median_finder9_1 .I1 (med_of_vector_med[0]), .I2 (N155), .I3 (N167), - .I4 (_N102855_1), + .I4 (_N103692_1), .ID (min_of_vector_max[0])); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; @@ -41506,7 +41161,7 @@ module median_finder9_1 .I1 (med_of_vector_med[1]), .I2 (N155), .I3 (N167), - .I4 (_N102855_1), + .I4 (_N103692_1), .ID (min_of_vector_max[1])); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; @@ -41518,7 +41173,7 @@ module median_finder9_1 .I1 (med_of_vector_med[2]), .I2 (N155), .I3 (N167), - .I4 (_N102855_1), + .I4 (_N103692_1), .ID (min_of_vector_max[2])); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; @@ -41530,7 +41185,7 @@ module median_finder9_1 .I1 (med_of_vector_med[3]), .I2 (N155), .I3 (N167), - .I4 (_N102855_1), + .I4 (_N103692_1), .ID (min_of_vector_max[3])); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; @@ -41542,7 +41197,7 @@ module median_finder9_1 .I1 (med_of_vector_med[4]), .I2 (N155), .I3 (N167), - .I4 (_N102855_1), + .I4 (_N103692_1), .ID (min_of_vector_max[4])); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; @@ -41554,14 +41209,14 @@ module median_finder9_1 .I1 (med_of_vector_med[5]), .I2 (N155), .I3 (N167), - .I4 (_N102855_1), + .I4 (_N103692_1), .ID (min_of_vector_max[5])); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; GTP_LUT3 /* N188_40 */ #( .INIT(8'b11100111)) N188_40 ( - .Z (_N102855_1), + .Z (_N103692_1), .I0 (N155), .I1 (N161), .I2 (N167)); @@ -42091,10 +41746,10 @@ module sort_3_unq28 wire [4:0] N55; wire [4:0] N68; wire [4:0] N73; - wire _N23948; - wire _N23966; - wire _N23970; - wire _N96682; + wire _N20522; + wire _N20924; + wire _N20928; + wire _N97439; GTP_LUT5CARRY /* \N4.lt_0 */ #( .INIT(32'b00100000111100100000000000000000), @@ -42349,7 +42004,7 @@ module sort_3_unq28 GTP_LUT4 /* N55_9 */ #( .INIT(16'b1100101010101010)) N55_9 ( - .Z (_N96682), + .Z (_N97439), .I0 (N4), .I1 (N5), .I2 (N8), @@ -42359,7 +42014,7 @@ module sort_3_unq28 GTP_LUT4 /* N55_11_1 */ #( .INIT(16'b0000101000101010)) N55_11_1 ( - .Z (_N23948), + .Z (_N20522), .I0 (N4), .I1 (N5), .I2 (N8), @@ -42370,8 +42025,8 @@ module sort_3_unq28 .INIT(32'b11111011010100011110101001000000)) \N55_18[0] ( .Z (N55[0]), - .I0 (_N23948), - .I1 (_N96682), + .I0 (_N20522), + .I1 (_N97439), .I2 (original_data[10]), .I3 (original_data[5]), .I4 (original_data[0])); @@ -42381,8 +42036,8 @@ module sort_3_unq28 .INIT(32'b11111011010100011110101001000000)) \N55_18[1] ( .Z (N55[1]), - .I0 (_N23948), - .I1 (_N96682), + .I0 (_N20522), + .I1 (_N97439), .I2 (original_data[11]), .I3 (original_data[6]), .I4 (original_data[1])); @@ -42392,8 +42047,8 @@ module sort_3_unq28 .INIT(32'b11111011010100011110101001000000)) \N55_18[2] ( .Z (N55[2]), - .I0 (_N23948), - .I1 (_N96682), + .I0 (_N20522), + .I1 (_N97439), .I2 (original_data[12]), .I3 (original_data[7]), .I4 (original_data[2])); @@ -42403,8 +42058,8 @@ module sort_3_unq28 .INIT(32'b11111011010100011110101001000000)) \N55_18[3] ( .Z (N55[3]), - .I0 (_N23948), - .I1 (_N96682), + .I0 (_N20522), + .I1 (_N97439), .I2 (original_data[13]), .I3 (original_data[8]), .I4 (original_data[3])); @@ -42414,8 +42069,8 @@ module sort_3_unq28 .INIT(32'b11111011010100011110101001000000)) \N55_18[4] ( .Z (N55[4]), - .I0 (_N23948), - .I1 (_N96682), + .I0 (_N20522), + .I1 (_N97439), .I2 (original_data[14]), .I3 (original_data[9]), .I4 (original_data[4])); @@ -42424,7 +42079,7 @@ module sort_3_unq28 GTP_LUT4 /* N68_10_1 */ #( .INIT(16'b0011100000001000)) N68_10_1 ( - .Z (_N23966), + .Z (_N20924), .I0 (N4), .I1 (N5), .I2 (N8), @@ -42434,7 +42089,7 @@ module sort_3_unq28 GTP_LUT4 /* N68_14_1 */ #( .INIT(16'b0100001000100010)) N68_14_1 ( - .Z (_N23970), + .Z (_N20928), .I0 (N4), .I1 (N5), .I2 (N8), @@ -42445,8 +42100,8 @@ module sort_3_unq28 .INIT(32'b11110101111001001011000110100000)) \N68_17[0] ( .Z (N68[0]), - .I0 (_N23966), - .I1 (_N23970), + .I0 (_N20924), + .I1 (_N20928), .I2 (original_data[10]), .I3 (original_data[5]), .I4 (original_data[0])); @@ -42456,8 +42111,8 @@ module sort_3_unq28 .INIT(32'b11110101111001001011000110100000)) \N68_17[1] ( .Z (N68[1]), - .I0 (_N23966), - .I1 (_N23970), + .I0 (_N20924), + .I1 (_N20928), .I2 (original_data[11]), .I3 (original_data[6]), .I4 (original_data[1])); @@ -42467,8 +42122,8 @@ module sort_3_unq28 .INIT(32'b11110101111001001011000110100000)) \N68_17[2] ( .Z (N68[2]), - .I0 (_N23966), - .I1 (_N23970), + .I0 (_N20924), + .I1 (_N20928), .I2 (original_data[12]), .I3 (original_data[7]), .I4 (original_data[2])); @@ -42478,8 +42133,8 @@ module sort_3_unq28 .INIT(32'b11110101111001001011000110100000)) \N68_17[3] ( .Z (N68[3]), - .I0 (_N23966), - .I1 (_N23970), + .I0 (_N20924), + .I1 (_N20928), .I2 (original_data[13]), .I3 (original_data[8]), .I4 (original_data[3])); @@ -42489,8 +42144,8 @@ module sort_3_unq28 .INIT(32'b11110101111001001011000110100000)) \N68_17[4] ( .Z (N68[4]), - .I0 (_N23966), - .I1 (_N23970), + .I0 (_N20924), + .I1 (_N20928), .I2 (original_data[14]), .I3 (original_data[9]), .I4 (original_data[4])); @@ -42729,10 +42384,10 @@ module sort_3_unq30 wire [4:0] N55; wire [4:0] N68; wire [4:0] N73; - wire _N20618; - wire _N21131; - wire _N21135; - wire _N96680; + wire _N20962; + wire _N23032; + wire _N23036; + wire _N97437; GTP_LUT5CARRY /* \N4.lt_0 */ #( .INIT(32'b00100000111100100000000000000000), @@ -42987,7 +42642,7 @@ module sort_3_unq30 GTP_LUT4 /* N55_9 */ #( .INIT(16'b1100101010101010)) N55_9 ( - .Z (_N96680), + .Z (_N97437), .I0 (N4), .I1 (N5), .I2 (N8), @@ -42997,7 +42652,7 @@ module sort_3_unq30 GTP_LUT4 /* N55_11_1 */ #( .INIT(16'b0000101000101010)) N55_11_1 ( - .Z (_N20618), + .Z (_N20962), .I0 (N4), .I1 (N5), .I2 (N8), @@ -43008,8 +42663,8 @@ module sort_3_unq30 .INIT(32'b11111011010100011110101001000000)) \N55_18[0] ( .Z (N55[0]), - .I0 (_N20618), - .I1 (_N96680), + .I0 (_N20962), + .I1 (_N97437), .I2 (original_data[10]), .I3 (original_data[5]), .I4 (original_data[0])); @@ -43019,8 +42674,8 @@ module sort_3_unq30 .INIT(32'b11111011010100011110101001000000)) \N55_18[1] ( .Z (N55[1]), - .I0 (_N20618), - .I1 (_N96680), + .I0 (_N20962), + .I1 (_N97437), .I2 (original_data[11]), .I3 (original_data[6]), .I4 (original_data[1])); @@ -43030,8 +42685,8 @@ module sort_3_unq30 .INIT(32'b11111011010100011110101001000000)) \N55_18[2] ( .Z (N55[2]), - .I0 (_N20618), - .I1 (_N96680), + .I0 (_N20962), + .I1 (_N97437), .I2 (original_data[12]), .I3 (original_data[7]), .I4 (original_data[2])); @@ -43041,8 +42696,8 @@ module sort_3_unq30 .INIT(32'b11111011010100011110101001000000)) \N55_18[3] ( .Z (N55[3]), - .I0 (_N20618), - .I1 (_N96680), + .I0 (_N20962), + .I1 (_N97437), .I2 (original_data[13]), .I3 (original_data[8]), .I4 (original_data[3])); @@ -43052,8 +42707,8 @@ module sort_3_unq30 .INIT(32'b11111011010100011110101001000000)) \N55_18[4] ( .Z (N55[4]), - .I0 (_N20618), - .I1 (_N96680), + .I0 (_N20962), + .I1 (_N97437), .I2 (original_data[14]), .I3 (original_data[9]), .I4 (original_data[4])); @@ -43062,7 +42717,7 @@ module sort_3_unq30 GTP_LUT4 /* N68_10_1 */ #( .INIT(16'b0011100000001000)) N68_10_1 ( - .Z (_N21131), + .Z (_N23032), .I0 (N4), .I1 (N5), .I2 (N8), @@ -43072,7 +42727,7 @@ module sort_3_unq30 GTP_LUT4 /* N68_14_1 */ #( .INIT(16'b0100001000100010)) N68_14_1 ( - .Z (_N21135), + .Z (_N23036), .I0 (N4), .I1 (N5), .I2 (N8), @@ -43083,8 +42738,8 @@ module sort_3_unq30 .INIT(32'b11110101111001001011000110100000)) \N68_17[0] ( .Z (N68[0]), - .I0 (_N21131), - .I1 (_N21135), + .I0 (_N23032), + .I1 (_N23036), .I2 (original_data[10]), .I3 (original_data[5]), .I4 (original_data[0])); @@ -43094,8 +42749,8 @@ module sort_3_unq30 .INIT(32'b11110101111001001011000110100000)) \N68_17[1] ( .Z (N68[1]), - .I0 (_N21131), - .I1 (_N21135), + .I0 (_N23032), + .I1 (_N23036), .I2 (original_data[11]), .I3 (original_data[6]), .I4 (original_data[1])); @@ -43105,8 +42760,8 @@ module sort_3_unq30 .INIT(32'b11110101111001001011000110100000)) \N68_17[2] ( .Z (N68[2]), - .I0 (_N21131), - .I1 (_N21135), + .I0 (_N23032), + .I1 (_N23036), .I2 (original_data[12]), .I3 (original_data[7]), .I4 (original_data[2])); @@ -43116,8 +42771,8 @@ module sort_3_unq30 .INIT(32'b11110101111001001011000110100000)) \N68_17[3] ( .Z (N68[3]), - .I0 (_N21131), - .I1 (_N21135), + .I0 (_N23032), + .I1 (_N23036), .I2 (original_data[13]), .I3 (original_data[8]), .I4 (original_data[3])); @@ -43127,8 +42782,8 @@ module sort_3_unq30 .INIT(32'b11110101111001001011000110100000)) \N68_17[4] ( .Z (N68[4]), - .I0 (_N21131), - .I1 (_N21135), + .I0 (_N23032), + .I1 (_N23036), .I2 (original_data[14]), .I3 (original_data[9]), .I4 (original_data[4])); @@ -43368,9 +43023,9 @@ module sort_3_unq32 wire [4:0] N68; wire [4:0] N73; wire _N17809; - wire _N21149; - wire _N25242; - wire _N96684; + wire _N17813; + wire _N23745; + wire _N97441; GTP_LUT5CARRY /* \N4.lt_0 */ #( .INIT(32'b00100000111100100000000000000000), @@ -43625,7 +43280,7 @@ module sort_3_unq32 GTP_LUT4 /* N55_9 */ #( .INIT(16'b1100101010101010)) N55_9 ( - .Z (_N96684), + .Z (_N97441), .I0 (N4), .I1 (N5), .I2 (N8), @@ -43635,7 +43290,7 @@ module sort_3_unq32 GTP_LUT4 /* N55_11_1 */ #( .INIT(16'b0000101000101010)) N55_11_1 ( - .Z (_N21149), + .Z (_N23745), .I0 (N4), .I1 (N5), .I2 (N8), @@ -43646,8 +43301,8 @@ module sort_3_unq32 .INIT(32'b11111011010100011110101001000000)) \N55_18[0] ( .Z (N55[0]), - .I0 (_N21149), - .I1 (_N96684), + .I0 (_N23745), + .I1 (_N97441), .I2 (original_data[10]), .I3 (original_data[5]), .I4 (original_data[0])); @@ -43657,8 +43312,8 @@ module sort_3_unq32 .INIT(32'b11111011010100011110101001000000)) \N55_18[1] ( .Z (N55[1]), - .I0 (_N21149), - .I1 (_N96684), + .I0 (_N23745), + .I1 (_N97441), .I2 (original_data[11]), .I3 (original_data[6]), .I4 (original_data[1])); @@ -43668,8 +43323,8 @@ module sort_3_unq32 .INIT(32'b11111011010100011110101001000000)) \N55_18[2] ( .Z (N55[2]), - .I0 (_N21149), - .I1 (_N96684), + .I0 (_N23745), + .I1 (_N97441), .I2 (original_data[12]), .I3 (original_data[7]), .I4 (original_data[2])); @@ -43679,8 +43334,8 @@ module sort_3_unq32 .INIT(32'b11111011010100011110101001000000)) \N55_18[3] ( .Z (N55[3]), - .I0 (_N21149), - .I1 (_N96684), + .I0 (_N23745), + .I1 (_N97441), .I2 (original_data[13]), .I3 (original_data[8]), .I4 (original_data[3])); @@ -43690,8 +43345,8 @@ module sort_3_unq32 .INIT(32'b11111011010100011110101001000000)) \N55_18[4] ( .Z (N55[4]), - .I0 (_N21149), - .I1 (_N96684), + .I0 (_N23745), + .I1 (_N97441), .I2 (original_data[14]), .I3 (original_data[9]), .I4 (original_data[4])); @@ -43708,22 +43363,23 @@ module sort_3_unq32 // LUT = (I0&~I1&~I3)|(I0&~I1&~I2)|(~I0&I1&I2&I3) ; // ../../sources/designs/image_filiter/sort_3.v:23 - GTP_LUT4 /* N68_10_1 */ #( + GTP_LUT4 /* N68_7 */ #( .INIT(16'b0011100000001000)) - N68_10_1 ( - .Z (_N25242), + N68_7 ( + .Z (_N17813), .I0 (N4), .I1 (N5), .I2 (N8), .I3 (N15)); // LUT = (I0&I1&~I2)|(~I1&I2&I3) ; + // ../../sources/designs/image_filiter/sort_3.v:23 GTP_LUT5 /* \N68_17[0] */ #( .INIT(32'b11110011111000101101000111000000)) \N68_17[0] ( .Z (N68[0]), .I0 (_N17809), - .I1 (_N25242), + .I1 (_N17813), .I2 (original_data[10]), .I3 (original_data[5]), .I4 (original_data[0])); @@ -43734,7 +43390,7 @@ module sort_3_unq32 \N68_17[1] ( .Z (N68[1]), .I0 (_N17809), - .I1 (_N25242), + .I1 (_N17813), .I2 (original_data[11]), .I3 (original_data[6]), .I4 (original_data[1])); @@ -43745,7 +43401,7 @@ module sort_3_unq32 \N68_17[2] ( .Z (N68[2]), .I0 (_N17809), - .I1 (_N25242), + .I1 (_N17813), .I2 (original_data[12]), .I3 (original_data[7]), .I4 (original_data[2])); @@ -43756,7 +43412,7 @@ module sort_3_unq32 \N68_17[3] ( .Z (N68[3]), .I0 (_N17809), - .I1 (_N25242), + .I1 (_N17813), .I2 (original_data[13]), .I3 (original_data[8]), .I4 (original_data[3])); @@ -43767,7 +43423,7 @@ module sort_3_unq32 \N68_17[4] ( .Z (N68[4]), .I0 (_N17809), - .I1 (_N25242), + .I1 (_N17813), .I2 (original_data[14]), .I3 (original_data[9]), .I4 (original_data[4])); @@ -44034,8 +43690,8 @@ module median_finder9_unq8 wire N167; wire [5:0] \N167.co ; wire [4:0] N188; - wire _N102870_1; - wire _N102889_1; + wire _N103349_1; + wire _N103407_1; wire [4:0] max_of_vector_max; wire [4:0] max_of_vector_min; wire [4:0] med_of_vector_med; @@ -44539,7 +44195,7 @@ module median_finder9_unq8 .I1 (\vector_med[1] [0] ), .I2 (N83), .I3 (N87), - .I4 (_N102870_1), + .I4 (_N103407_1), .ID (\vector_med[2] [0] )); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; @@ -44551,7 +44207,7 @@ module median_finder9_unq8 .I1 (\vector_med[1] [1] ), .I2 (N83), .I3 (N87), - .I4 (_N102870_1), + .I4 (_N103407_1), .ID (\vector_med[2] [1] )); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; @@ -44563,7 +44219,7 @@ module median_finder9_unq8 .I1 (\vector_med[1] [2] ), .I2 (N83), .I3 (N87), - .I4 (_N102870_1), + .I4 (_N103407_1), .ID (\vector_med[2] [2] )); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; @@ -44575,7 +44231,7 @@ module median_finder9_unq8 .I1 (\vector_med[1] [3] ), .I2 (N83), .I3 (N87), - .I4 (_N102870_1), + .I4 (_N103407_1), .ID (\vector_med[2] [3] )); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; @@ -44587,14 +44243,14 @@ module median_finder9_unq8 .I1 (\vector_med[1] [4] ), .I2 (N83), .I3 (N87), - .I4 (_N102870_1), + .I4 (_N103407_1), .ID (\vector_med[2] [4] )); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; GTP_LUT3 /* N104_40 */ #( .INIT(8'b11100111)) N104_40 ( - .Z (_N102870_1), + .Z (_N103407_1), .I0 (N83), .I1 (N85), .I2 (N87)); @@ -45088,7 +44744,7 @@ module median_finder9_unq8 .I1 (med_of_vector_med[0]), .I2 (N155), .I3 (N167), - .I4 (_N102889_1), + .I4 (_N103349_1), .ID (min_of_vector_max[0])); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; @@ -45100,7 +44756,7 @@ module median_finder9_unq8 .I1 (med_of_vector_med[1]), .I2 (N155), .I3 (N167), - .I4 (_N102889_1), + .I4 (_N103349_1), .ID (min_of_vector_max[1])); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; @@ -45112,7 +44768,7 @@ module median_finder9_unq8 .I1 (med_of_vector_med[2]), .I2 (N155), .I3 (N167), - .I4 (_N102889_1), + .I4 (_N103349_1), .ID (min_of_vector_max[2])); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; @@ -45124,7 +44780,7 @@ module median_finder9_unq8 .I1 (med_of_vector_med[3]), .I2 (N155), .I3 (N167), - .I4 (_N102889_1), + .I4 (_N103349_1), .ID (min_of_vector_max[3])); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; @@ -45136,14 +44792,14 @@ module median_finder9_unq8 .I1 (med_of_vector_med[4]), .I2 (N155), .I3 (N167), - .I4 (_N102889_1), + .I4 (_N103349_1), .ID (min_of_vector_max[4])); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; GTP_LUT3 /* N188_40 */ #( .INIT(8'b11100111)) N188_40 ( - .Z (_N102889_1), + .Z (_N103349_1), .I0 (N155), .I1 (N161), .I2 (N167)); @@ -45581,16 +45237,14 @@ module hybrid_filter input [143:0] s_matrix_data, input clk, input \param_manager_inst/param_filiter1_mode/changed_down , - input \param_manager_inst/param_filiter1_mode/changed_up , + input \param_manager_inst/param_filiter1_mode/pluse , input \param_manager_inst/param_filiter1_mode/pressed_down , - input \param_manager_inst/param_filiter1_mode/pressed_up , - input \param_manager_inst/param_modify_H/pluse , input rd3_rst, input s_matrix_valid, output [15:0] m_result_data, output m_result_valid, - output \param_manager_inst/param_modify_V/N140 , - output \param_manager_inst/param_rotate_A/N142 + output \param_manager_inst/param_filiter1_mode/N140 , + output \param_manager_inst/param_filiter2_mode/N140 ); wire N86; wire N90; @@ -45607,10 +45261,10 @@ module hybrid_filter wire [4:0] N155; wire [5:0] \N155.co ; wire [4:0] N162; - wire _N24436; - wire _N24466; - wire _N24793; - wire _N24903; + wire _N24623; + wire _N24800; + wire _N24830; + wire _N25044; wire [4:0] gauss_res_b; wire [5:0] gauss_res_g; wire [4:0] gauss_res_r; @@ -45780,9 +45434,9 @@ module hybrid_filter .Z (N106[0]), .I0 (median_res_r[0]), .I1 (gauss_res_r[0]), - .I2 (_N24466), + .I2 (_N24830), .I3 (raw_res_r[0]), - .I4 (_N24793), + .I4 (_N24623), .ID (N99[0])); // LUT = (I1&~I2&~I4)|(ID&I2&~I4)|(I2&I3&I4)|(I0&~I2&I4) ; @@ -45792,9 +45446,9 @@ module hybrid_filter .Z (N106[1]), .I0 (median_res_r[1]), .I1 (gauss_res_r[1]), - .I2 (_N24466), + .I2 (_N24830), .I3 (raw_res_r[1]), - .I4 (_N24793), + .I4 (_N24623), .ID (N99[1])); // LUT = (I1&~I2&~I4)|(ID&I2&~I4)|(I2&I3&I4)|(I0&~I2&I4) ; @@ -45804,9 +45458,9 @@ module hybrid_filter .Z (N106[2]), .I0 (median_res_r[2]), .I1 (gauss_res_r[2]), - .I2 (_N24466), + .I2 (_N24830), .I3 (raw_res_r[2]), - .I4 (_N24793), + .I4 (_N24623), .ID (N99[2])); // LUT = (I1&~I2&~I4)|(ID&I2&~I4)|(I2&I3&I4)|(I0&~I2&I4) ; @@ -45816,9 +45470,9 @@ module hybrid_filter .Z (N106[3]), .I0 (median_res_r[3]), .I1 (gauss_res_r[3]), - .I2 (_N24466), + .I2 (_N24830), .I3 (raw_res_r[3]), - .I4 (_N24793), + .I4 (_N24623), .ID (N99[3])); // LUT = (I1&~I2&~I4)|(ID&I2&~I4)|(I2&I3&I4)|(I0&~I2&I4) ; @@ -45828,16 +45482,16 @@ module hybrid_filter .Z (N106[4]), .I0 (median_res_r[4]), .I1 (gauss_res_r[4]), - .I2 (_N24466), + .I2 (_N24830), .I3 (raw_res_r[4]), - .I4 (_N24793), + .I4 (_N24623), .ID (N99[4])); // LUT = (I1&~I2&~I4)|(ID&I2&~I4)|(I2&I3&I4)|(I0&~I2&I4) ; - GTP_LUT5 /* N106_76 */ #( + GTP_LUT5 /* N106_72 */ #( .INIT(32'b11101101111011011110110111100101)) - N106_76 ( - .Z (_N24793), + N106_72 ( + .Z (_N24623), .I0 (mode[0]), .I1 (mode[1]), .I2 (mode[2]), @@ -45845,15 +45499,25 @@ module hybrid_filter .I4 (N90)); // LUT = (~I0&~I2)|(I0&I2)|(I1&I2)|(I1&I3)|(I1&I4) ; + GTP_LUT4 /* N106_90 */ #( + .INIT(16'b1010100000000000)) + N106_90 ( + .Z (\param_manager_inst/param_filiter1_mode/N140 ), + .I0 (\param_manager_inst/selected [0] ), + .I1 (\param_manager_inst/param_filiter1_mode/changed_down ), + .I2 (\param_manager_inst/param_filiter1_mode/pluse ), + .I3 (\param_manager_inst/param_filiter1_mode/pressed_down )); + // LUT = (I0&I1&I3)|(I0&I2&I3) ; + GTP_LUT4 /* N106_91 */ #( - .INIT(16'b1010000010000000)) + .INIT(16'b1010100000000000)) N106_91 ( - .Z (\param_manager_inst/param_modify_V/N140 ), - .I0 (\param_manager_inst/selected [13] ), + .Z (\param_manager_inst/param_filiter2_mode/N140 ), + .I0 (\param_manager_inst/selected [1] ), .I1 (\param_manager_inst/param_filiter1_mode/changed_down ), - .I2 (\param_manager_inst/param_filiter1_mode/pressed_down ), - .I3 (\param_manager_inst/param_modify_H/pluse )); - // LUT = (I0&I1&I2)|(I0&I2&I3) ; + .I2 (\param_manager_inst/param_filiter1_mode/pluse ), + .I3 (\param_manager_inst/param_filiter1_mode/pressed_down )); + // LUT = (I0&I1&I3)|(I0&I2&I3) ; GTP_LUT4 /* N114_mux5_4 */ #( .INIT(16'b1000000000000000)) @@ -46001,9 +45665,9 @@ module hybrid_filter .Z (N134[0]), .I0 (median_res_g[0]), .I1 (gauss_res_g[0]), - .I2 (_N24466), + .I2 (_N24830), .I3 (raw_res_g[0]), - .I4 (_N24903), + .I4 (_N24800), .ID (N127[0])); // LUT = (I1&~I2&~I4)|(ID&I2&~I4)|(I2&I3&I4)|(I0&~I2&I4) ; @@ -46013,9 +45677,9 @@ module hybrid_filter .Z (N134[1]), .I0 (median_res_g[1]), .I1 (gauss_res_g[1]), - .I2 (_N24466), + .I2 (_N24830), .I3 (raw_res_g[1]), - .I4 (_N24903), + .I4 (_N24800), .ID (N127[1])); // LUT = (I1&~I2&~I4)|(ID&I2&~I4)|(I2&I3&I4)|(I0&~I2&I4) ; @@ -46025,9 +45689,9 @@ module hybrid_filter .Z (N134[2]), .I0 (median_res_g[2]), .I1 (gauss_res_g[2]), - .I2 (_N24466), + .I2 (_N24830), .I3 (raw_res_g[2]), - .I4 (_N24903), + .I4 (_N24800), .ID (N127[2])); // LUT = (I1&~I2&~I4)|(ID&I2&~I4)|(I2&I3&I4)|(I0&~I2&I4) ; @@ -46037,9 +45701,9 @@ module hybrid_filter .Z (N134[3]), .I0 (median_res_g[3]), .I1 (gauss_res_g[3]), - .I2 (_N24466), + .I2 (_N24830), .I3 (raw_res_g[3]), - .I4 (_N24903), + .I4 (_N24800), .ID (N127[3])); // LUT = (I1&~I2&~I4)|(ID&I2&~I4)|(I2&I3&I4)|(I0&~I2&I4) ; @@ -46049,9 +45713,9 @@ module hybrid_filter .Z (N134[4]), .I0 (median_res_g[4]), .I1 (gauss_res_g[4]), - .I2 (_N24466), + .I2 (_N24830), .I3 (raw_res_g[4]), - .I4 (_N24903), + .I4 (_N24800), .ID (N127[4])); // LUT = (I1&~I2&~I4)|(ID&I2&~I4)|(I2&I3&I4)|(I0&~I2&I4) ; @@ -46061,16 +45725,16 @@ module hybrid_filter .Z (N134[5]), .I0 (median_res_g[5]), .I1 (gauss_res_g[5]), - .I2 (_N24466), + .I2 (_N24830), .I3 (raw_res_g[5]), - .I4 (_N24903), + .I4 (_N24800), .ID (N127[5])); // LUT = (I1&~I2&~I4)|(ID&I2&~I4)|(I2&I3&I4)|(I0&~I2&I4) ; GTP_LUT5 /* N134_72 */ #( .INIT(32'b11101101111011011110110111100101)) N134_72 ( - .Z (_N24903), + .Z (_N24800), .I0 (mode[0]), .I1 (mode[1]), .I2 (mode[2]), @@ -46078,6 +45742,15 @@ module hybrid_filter .I4 (N118)); // LUT = (~I0&~I2)|(I0&I2)|(I1&I2)|(I1&I3)|(I1&I4) ; + GTP_LUT3 /* N134_78 */ #( + .INIT(8'b11110001)) + N134_78 ( + .Z (_N24830), + .I0 (mode[0]), + .I1 (mode[1]), + .I2 (mode[2])); + // LUT = (I2)|(~I0&~I1) ; + GTP_LUT3 /* N142_mux4_3 */ #( .INIT(8'b10000000)) N142_mux4_3 ( @@ -46202,9 +45875,9 @@ module hybrid_filter .Z (N162[0]), .I0 (median_res_b[0]), .I1 (gauss_res_b[0]), - .I2 (_N24466), + .I2 (_N24830), .I3 (raw_res_b[0]), - .I4 (_N24436), + .I4 (_N25044), .ID (N155[0])); // LUT = (I1&~I2&~I4)|(ID&I2&~I4)|(I2&I3&I4)|(I0&~I2&I4) ; @@ -46214,9 +45887,9 @@ module hybrid_filter .Z (N162[1]), .I0 (median_res_b[1]), .I1 (gauss_res_b[1]), - .I2 (_N24466), + .I2 (_N24830), .I3 (raw_res_b[1]), - .I4 (_N24436), + .I4 (_N25044), .ID (N155[1])); // LUT = (I1&~I2&~I4)|(ID&I2&~I4)|(I2&I3&I4)|(I0&~I2&I4) ; @@ -46226,9 +45899,9 @@ module hybrid_filter .Z (N162[2]), .I0 (median_res_b[2]), .I1 (gauss_res_b[2]), - .I2 (_N24466), + .I2 (_N24830), .I3 (raw_res_b[2]), - .I4 (_N24436), + .I4 (_N25044), .ID (N155[2])); // LUT = (I1&~I2&~I4)|(ID&I2&~I4)|(I2&I3&I4)|(I0&~I2&I4) ; @@ -46238,9 +45911,9 @@ module hybrid_filter .Z (N162[3]), .I0 (median_res_b[3]), .I1 (gauss_res_b[3]), - .I2 (_N24466), + .I2 (_N24830), .I3 (raw_res_b[3]), - .I4 (_N24436), + .I4 (_N25044), .ID (N155[3])); // LUT = (I1&~I2&~I4)|(ID&I2&~I4)|(I2&I3&I4)|(I0&~I2&I4) ; @@ -46250,25 +45923,16 @@ module hybrid_filter .Z (N162[4]), .I0 (median_res_b[4]), .I1 (gauss_res_b[4]), - .I2 (_N24466), + .I2 (_N24830), .I3 (raw_res_b[4]), - .I4 (_N24436), + .I4 (_N25044), .ID (N155[4])); // LUT = (I1&~I2&~I4)|(ID&I2&~I4)|(I2&I3&I4)|(I0&~I2&I4) ; - GTP_LUT3 /* N162_72 */ #( - .INIT(8'b11110001)) - N162_72 ( - .Z (_N24466), - .I0 (mode[0]), - .I1 (mode[1]), - .I2 (mode[2])); - // LUT = (I2)|(~I0&~I1) ; - GTP_LUT5 /* N162_76 */ #( .INIT(32'b11101101111011011110110111100101)) N162_76 ( - .Z (_N24436), + .Z (_N25044), .I0 (mode[0]), .I1 (mode[1]), .I2 (mode[2]), @@ -46276,16 +45940,6 @@ module hybrid_filter .I4 (N146)); // LUT = (~I0&~I2)|(I0&I2)|(I1&I2)|(I1&I3)|(I1&I4) ; - GTP_LUT4 /* N162_89 */ #( - .INIT(16'b1010000010000000)) - N162_89 ( - .Z (\param_manager_inst/param_rotate_A/N142 ), - .I0 (\param_manager_inst/selected [8] ), - .I1 (\param_manager_inst/param_filiter1_mode/changed_up ), - .I2 (\param_manager_inst/param_filiter1_mode/pressed_up ), - .I3 (\param_manager_inst/param_modify_H/pluse )); - // LUT = (I0&I1&I2)|(I0&I2&I3) ; - gaussian_conv gaussian_conv_b ( .m_result_data (gauss_res_b), .\mat[0][0] ({\gaussian_conv_b/mat[0][0] [4] , \gaussian_conv_b/mat[0][0] [3] , \gaussian_conv_b/mat[0][0] [2] , \gaussian_conv_b/mat[0][0] [1] , \gaussian_conv_b/mat[0][0] [0] }), @@ -47258,28 +46912,28 @@ module ipml_fifo_ctrl_v1_3_1 wire N22; wire N24; wire [12:0] \N24.co ; - wire _N14068; - wire _N14069; - wire _N14070; - wire _N14071; - wire _N14072; - wire _N14073; - wire _N14074; - wire _N14075; - wire _N14076; - wire _N14077; - wire _N14078; - wire _N14118; - wire _N14119; - wire _N14120; - wire _N14121; - wire _N14122; - wire _N14123; - wire _N14124; - wire _N14125; - wire _N14126; - wire _N14127; - wire _N14128; + wire _N13862; + wire _N13863; + wire _N13864; + wire _N13865; + wire _N13866; + wire _N13867; + wire _N13868; + wire _N13869; + wire _N13870; + wire _N13871; + wire _N13872; + wire _N14458; + wire _N14459; + wire _N14460; + wire _N14461; + wire _N14462; + wire _N14463; + wire _N14464; + wire _N14465; + wire _N14466; + wire _N14467; + wire _N14468; wire [11:0] rbin; wire rempty; wire [11:0] rrptr; @@ -47299,7 +46953,7 @@ module ipml_fifo_ctrl_v1_3_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_1 ( - .COUT (_N14068), + .COUT (_N14458), .Z (N2[0]), .CIN (), .I0 (w_en), @@ -47319,9 +46973,9 @@ module ipml_fifo_ctrl_v1_3_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_2 ( - .COUT (_N14069), + .COUT (_N14459), .Z (N2[1]), - .CIN (_N14068), + .CIN (_N14458), .I0 (w_en), .I1 (waddr[0]), .I2 (waddr[1]), @@ -47339,9 +46993,9 @@ module ipml_fifo_ctrl_v1_3_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_3 ( - .COUT (_N14070), + .COUT (_N14460), .Z (N2[2]), - .CIN (_N14069), + .CIN (_N14459), .I0 (), .I1 (waddr[2]), .I2 (), @@ -47359,9 +47013,9 @@ module ipml_fifo_ctrl_v1_3_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_4 ( - .COUT (_N14071), + .COUT (_N14461), .Z (N2[3]), - .CIN (_N14070), + .CIN (_N14460), .I0 (), .I1 (waddr[3]), .I2 (), @@ -47379,9 +47033,9 @@ module ipml_fifo_ctrl_v1_3_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_5 ( - .COUT (_N14072), + .COUT (_N14462), .Z (N2[4]), - .CIN (_N14071), + .CIN (_N14461), .I0 (), .I1 (waddr[4]), .I2 (), @@ -47399,9 +47053,9 @@ module ipml_fifo_ctrl_v1_3_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_6 ( - .COUT (_N14073), + .COUT (_N14463), .Z (N2[5]), - .CIN (_N14072), + .CIN (_N14462), .I0 (), .I1 (waddr[5]), .I2 (), @@ -47419,9 +47073,9 @@ module ipml_fifo_ctrl_v1_3_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_7 ( - .COUT (_N14074), + .COUT (_N14464), .Z (N2[6]), - .CIN (_N14073), + .CIN (_N14463), .I0 (), .I1 (waddr[6]), .I2 (), @@ -47439,9 +47093,9 @@ module ipml_fifo_ctrl_v1_3_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_8 ( - .COUT (_N14075), + .COUT (_N14465), .Z (N2[7]), - .CIN (_N14074), + .CIN (_N14464), .I0 (), .I1 (waddr[7]), .I2 (), @@ -47459,9 +47113,9 @@ module ipml_fifo_ctrl_v1_3_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_9 ( - .COUT (_N14076), + .COUT (_N14466), .Z (N2[8]), - .CIN (_N14075), + .CIN (_N14465), .I0 (), .I1 (waddr[8]), .I2 (), @@ -47479,9 +47133,9 @@ module ipml_fifo_ctrl_v1_3_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_10 ( - .COUT (_N14077), + .COUT (_N14467), .Z (N2[9]), - .CIN (_N14076), + .CIN (_N14466), .I0 (), .I1 (waddr[9]), .I2 (), @@ -47499,9 +47153,9 @@ module ipml_fifo_ctrl_v1_3_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_11 ( - .COUT (_N14078), + .COUT (_N14468), .Z (N2[10]), - .CIN (_N14077), + .CIN (_N14467), .I0 (), .I1 (waddr[10]), .I2 (), @@ -47521,7 +47175,7 @@ module ipml_fifo_ctrl_v1_3_1 N2_12 ( .COUT (), .Z (N2[11]), - .CIN (_N14078), + .CIN (_N14468), .I0 (), .I1 (wbin[11]), .I2 (), @@ -47664,7 +47318,7 @@ module ipml_fifo_ctrl_v1_3_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_1 ( - .COUT (_N14118), + .COUT (_N13862), .Z (N11[0]), .CIN (), .I0 (r_en), @@ -47684,9 +47338,9 @@ module ipml_fifo_ctrl_v1_3_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_2 ( - .COUT (_N14119), + .COUT (_N13863), .Z (N11[1]), - .CIN (_N14118), + .CIN (_N13862), .I0 (r_en), .I1 (raddr[0]), .I2 (raddr[1]), @@ -47704,9 +47358,9 @@ module ipml_fifo_ctrl_v1_3_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_3 ( - .COUT (_N14120), + .COUT (_N13864), .Z (N11[2]), - .CIN (_N14119), + .CIN (_N13863), .I0 (), .I1 (raddr[2]), .I2 (), @@ -47724,9 +47378,9 @@ module ipml_fifo_ctrl_v1_3_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_4 ( - .COUT (_N14121), + .COUT (_N13865), .Z (N11[3]), - .CIN (_N14120), + .CIN (_N13864), .I0 (), .I1 (raddr[3]), .I2 (), @@ -47744,9 +47398,9 @@ module ipml_fifo_ctrl_v1_3_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_5 ( - .COUT (_N14122), + .COUT (_N13866), .Z (N11[4]), - .CIN (_N14121), + .CIN (_N13865), .I0 (), .I1 (raddr[4]), .I2 (), @@ -47764,9 +47418,9 @@ module ipml_fifo_ctrl_v1_3_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_6 ( - .COUT (_N14123), + .COUT (_N13867), .Z (N11[5]), - .CIN (_N14122), + .CIN (_N13866), .I0 (), .I1 (raddr[5]), .I2 (), @@ -47784,9 +47438,9 @@ module ipml_fifo_ctrl_v1_3_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_7 ( - .COUT (_N14124), + .COUT (_N13868), .Z (N11[6]), - .CIN (_N14123), + .CIN (_N13867), .I0 (), .I1 (raddr[6]), .I2 (), @@ -47804,9 +47458,9 @@ module ipml_fifo_ctrl_v1_3_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_8 ( - .COUT (_N14125), + .COUT (_N13869), .Z (N11[7]), - .CIN (_N14124), + .CIN (_N13868), .I0 (), .I1 (raddr[7]), .I2 (), @@ -47824,9 +47478,9 @@ module ipml_fifo_ctrl_v1_3_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_9 ( - .COUT (_N14126), + .COUT (_N13870), .Z (N11[8]), - .CIN (_N14125), + .CIN (_N13869), .I0 (), .I1 (raddr[8]), .I2 (), @@ -47844,9 +47498,9 @@ module ipml_fifo_ctrl_v1_3_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_10 ( - .COUT (_N14127), + .COUT (_N13871), .Z (N11[9]), - .CIN (_N14126), + .CIN (_N13870), .I0 (), .I1 (raddr[9]), .I2 (), @@ -47864,9 +47518,9 @@ module ipml_fifo_ctrl_v1_3_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_11 ( - .COUT (_N14128), + .COUT (_N13872), .Z (N11[10]), - .CIN (_N14127), + .CIN (_N13871), .I0 (), .I1 (raddr[10]), .I2 (), @@ -47886,7 +47540,7 @@ module ipml_fifo_ctrl_v1_3_1 N11_12 ( .COUT (), .Z (N11[11]), - .CIN (_N14128), + .CIN (_N13872), .I0 (), .I1 (rbin[11]), .I2 (), @@ -48873,28 +48527,28 @@ module ipml_fifo_ctrl_v1_3_1_unq10 wire N22; wire N24; wire [12:0] \N24.co ; - wire _N13965; - wire _N13966; - wire _N13967; - wire _N13968; - wire _N13969; - wire _N13970; - wire _N13971; - wire _N13972; - wire _N13973; - wire _N13974; - wire _N13975; - wire _N14007; - wire _N14008; - wire _N14009; - wire _N14010; - wire _N14011; - wire _N14012; - wire _N14013; - wire _N14014; - wire _N14015; - wire _N14016; - wire _N14017; + wire _N14122; + wire _N14123; + wire _N14124; + wire _N14125; + wire _N14126; + wire _N14127; + wire _N14128; + wire _N14129; + wire _N14130; + wire _N14131; + wire _N14132; + wire _N14177; + wire _N14178; + wire _N14179; + wire _N14180; + wire _N14181; + wire _N14182; + wire _N14183; + wire _N14184; + wire _N14185; + wire _N14186; + wire _N14187; wire [11:0] rbin; wire rempty; wire [11:0] rrptr; @@ -48914,7 +48568,7 @@ module ipml_fifo_ctrl_v1_3_1_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_1 ( - .COUT (_N13965), + .COUT (_N14122), .Z (N2[0]), .CIN (), .I0 (w_en), @@ -48934,9 +48588,9 @@ module ipml_fifo_ctrl_v1_3_1_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_2 ( - .COUT (_N13966), + .COUT (_N14123), .Z (N2[1]), - .CIN (_N13965), + .CIN (_N14122), .I0 (w_en), .I1 (waddr[0]), .I2 (waddr[1]), @@ -48954,9 +48608,9 @@ module ipml_fifo_ctrl_v1_3_1_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_3 ( - .COUT (_N13967), + .COUT (_N14124), .Z (N2[2]), - .CIN (_N13966), + .CIN (_N14123), .I0 (), .I1 (waddr[2]), .I2 (), @@ -48974,9 +48628,9 @@ module ipml_fifo_ctrl_v1_3_1_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_4 ( - .COUT (_N13968), + .COUT (_N14125), .Z (N2[3]), - .CIN (_N13967), + .CIN (_N14124), .I0 (), .I1 (waddr[3]), .I2 (), @@ -48994,9 +48648,9 @@ module ipml_fifo_ctrl_v1_3_1_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_5 ( - .COUT (_N13969), + .COUT (_N14126), .Z (N2[4]), - .CIN (_N13968), + .CIN (_N14125), .I0 (), .I1 (waddr[4]), .I2 (), @@ -49014,9 +48668,9 @@ module ipml_fifo_ctrl_v1_3_1_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_6 ( - .COUT (_N13970), + .COUT (_N14127), .Z (N2[5]), - .CIN (_N13969), + .CIN (_N14126), .I0 (), .I1 (waddr[5]), .I2 (), @@ -49034,9 +48688,9 @@ module ipml_fifo_ctrl_v1_3_1_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_7 ( - .COUT (_N13971), + .COUT (_N14128), .Z (N2[6]), - .CIN (_N13970), + .CIN (_N14127), .I0 (), .I1 (waddr[6]), .I2 (), @@ -49054,9 +48708,9 @@ module ipml_fifo_ctrl_v1_3_1_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_8 ( - .COUT (_N13972), + .COUT (_N14129), .Z (N2[7]), - .CIN (_N13971), + .CIN (_N14128), .I0 (), .I1 (waddr[7]), .I2 (), @@ -49074,9 +48728,9 @@ module ipml_fifo_ctrl_v1_3_1_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_9 ( - .COUT (_N13973), + .COUT (_N14130), .Z (N2[8]), - .CIN (_N13972), + .CIN (_N14129), .I0 (), .I1 (waddr[8]), .I2 (), @@ -49094,9 +48748,9 @@ module ipml_fifo_ctrl_v1_3_1_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_10 ( - .COUT (_N13974), + .COUT (_N14131), .Z (N2[9]), - .CIN (_N13973), + .CIN (_N14130), .I0 (), .I1 (waddr[9]), .I2 (), @@ -49114,9 +48768,9 @@ module ipml_fifo_ctrl_v1_3_1_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_11 ( - .COUT (_N13975), + .COUT (_N14132), .Z (N2[10]), - .CIN (_N13974), + .CIN (_N14131), .I0 (), .I1 (waddr[10]), .I2 (), @@ -49136,7 +48790,7 @@ module ipml_fifo_ctrl_v1_3_1_unq10 N2_12 ( .COUT (), .Z (N2[11]), - .CIN (_N13975), + .CIN (_N14132), .I0 (), .I1 (wbin[11]), .I2 (), @@ -49279,7 +48933,7 @@ module ipml_fifo_ctrl_v1_3_1_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_1 ( - .COUT (_N14007), + .COUT (_N14177), .Z (N11[0]), .CIN (), .I0 (r_en), @@ -49299,9 +48953,9 @@ module ipml_fifo_ctrl_v1_3_1_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_2 ( - .COUT (_N14008), + .COUT (_N14178), .Z (N11[1]), - .CIN (_N14007), + .CIN (_N14177), .I0 (r_en), .I1 (raddr[0]), .I2 (raddr[1]), @@ -49319,9 +48973,9 @@ module ipml_fifo_ctrl_v1_3_1_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_3 ( - .COUT (_N14009), + .COUT (_N14179), .Z (N11[2]), - .CIN (_N14008), + .CIN (_N14178), .I0 (), .I1 (raddr[2]), .I2 (), @@ -49339,9 +48993,9 @@ module ipml_fifo_ctrl_v1_3_1_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_4 ( - .COUT (_N14010), + .COUT (_N14180), .Z (N11[3]), - .CIN (_N14009), + .CIN (_N14179), .I0 (), .I1 (raddr[3]), .I2 (), @@ -49359,9 +49013,9 @@ module ipml_fifo_ctrl_v1_3_1_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_5 ( - .COUT (_N14011), + .COUT (_N14181), .Z (N11[4]), - .CIN (_N14010), + .CIN (_N14180), .I0 (), .I1 (raddr[4]), .I2 (), @@ -49379,9 +49033,9 @@ module ipml_fifo_ctrl_v1_3_1_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_6 ( - .COUT (_N14012), + .COUT (_N14182), .Z (N11[5]), - .CIN (_N14011), + .CIN (_N14181), .I0 (), .I1 (raddr[5]), .I2 (), @@ -49399,9 +49053,9 @@ module ipml_fifo_ctrl_v1_3_1_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_7 ( - .COUT (_N14013), + .COUT (_N14183), .Z (N11[6]), - .CIN (_N14012), + .CIN (_N14182), .I0 (), .I1 (raddr[6]), .I2 (), @@ -49419,9 +49073,9 @@ module ipml_fifo_ctrl_v1_3_1_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_8 ( - .COUT (_N14014), + .COUT (_N14184), .Z (N11[7]), - .CIN (_N14013), + .CIN (_N14183), .I0 (), .I1 (raddr[7]), .I2 (), @@ -49439,9 +49093,9 @@ module ipml_fifo_ctrl_v1_3_1_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_9 ( - .COUT (_N14015), + .COUT (_N14185), .Z (N11[8]), - .CIN (_N14014), + .CIN (_N14184), .I0 (), .I1 (raddr[8]), .I2 (), @@ -49459,9 +49113,9 @@ module ipml_fifo_ctrl_v1_3_1_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_10 ( - .COUT (_N14016), + .COUT (_N14186), .Z (N11[9]), - .CIN (_N14015), + .CIN (_N14185), .I0 (), .I1 (raddr[9]), .I2 (), @@ -49479,9 +49133,9 @@ module ipml_fifo_ctrl_v1_3_1_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_11 ( - .COUT (_N14017), + .COUT (_N14187), .Z (N11[10]), - .CIN (_N14016), + .CIN (_N14186), .I0 (), .I1 (raddr[10]), .I2 (), @@ -49501,7 +49155,7 @@ module ipml_fifo_ctrl_v1_3_1_unq10 N11_12 ( .COUT (), .Z (N11[11]), - .CIN (_N14017), + .CIN (_N14187), .I0 (), .I1 (rbin[11]), .I2 (), @@ -50473,8 +50127,8 @@ endmodule module multiline_buffer ( input [15:0] s_pixel_data, - input _N97340, - input _N103920, + input _N98107, + input _N104744, input clk, input \image_filiter_inst2/multiline_buffer_inst/N53 , input rd3_rst, @@ -50502,45 +50156,45 @@ module multiline_buffer wire [10:0] N281; wire [10:0] N285; wire [10:0] N287; - wire _N13480; - wire _N13481; - wire _N13482; - wire _N13483; - wire _N13484; - wire _N13485; - wire _N13486; - wire _N13487; - wire _N13488; - wire _N15451; - wire _N15452; - wire _N15453; - wire _N15454; - wire _N15455; - wire _N15456; - wire _N15457; - wire _N15458; - wire _N15459; - wire _N15533; - wire _N15534; - wire _N15535; - wire _N15536; - wire _N15537; - wire _N15538; - wire _N15539; - wire _N15550; - wire _N15551; - wire _N15552; - wire _N15553; - wire _N96962; - wire _N97331; - wire _N100510; - wire _N100855; - wire _N103774; - wire _N103775; - wire _N103784; - wire _N103785; - wire _N103894; - wire _N103908; + wire _N14413; + wire _N14414; + wire _N14415; + wire _N14416; + wire _N14417; + wire _N14418; + wire _N14419; + wire _N14754; + wire _N14755; + wire _N14756; + wire _N14757; + wire _N15850; + wire _N15851; + wire _N15852; + wire _N15853; + wire _N15854; + wire _N15855; + wire _N15856; + wire _N15857; + wire _N15858; + wire _N16465; + wire _N16466; + wire _N16467; + wire _N16468; + wire _N16469; + wire _N16470; + wire _N16471; + wire _N16472; + wire _N16473; + wire _N97635; + wire _N98108; + wire _N100307; + wire _N101008; + wire _N104597; + wire _N104598; + wire _N104607; + wire _N104608; + wire _N104718; + wire _N104732; wire [47:0] dout; wire [10:0] hor_cnt; wire \hor_cnt[0]_inv ; @@ -50559,7 +50213,7 @@ module multiline_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N12_1_1 ( - .COUT (_N15451), + .COUT (_N16465), .Z (N287[1]), .CIN (), .I0 (hor_cnt[0]), @@ -50579,9 +50233,9 @@ module multiline_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N12_1_2 ( - .COUT (_N15452), + .COUT (_N16466), .Z (N287[2]), - .CIN (_N15451), + .CIN (_N16465), .I0 (hor_cnt[0]), .I1 (hor_cnt[1]), .I2 (hor_cnt[2]), @@ -50599,9 +50253,9 @@ module multiline_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N12_1_3 ( - .COUT (_N15453), + .COUT (_N16467), .Z (N287[3]), - .CIN (_N15452), + .CIN (_N16466), .I0 (), .I1 (hor_cnt[3]), .I2 (), @@ -50619,9 +50273,9 @@ module multiline_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N12_1_4 ( - .COUT (_N15454), + .COUT (_N16468), .Z (N287[4]), - .CIN (_N15453), + .CIN (_N16467), .I0 (), .I1 (hor_cnt[4]), .I2 (), @@ -50639,9 +50293,9 @@ module multiline_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N12_1_5 ( - .COUT (_N15455), + .COUT (_N16469), .Z (N287[5]), - .CIN (_N15454), + .CIN (_N16468), .I0 (), .I1 (hor_cnt[5]), .I2 (), @@ -50659,9 +50313,9 @@ module multiline_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N12_1_6 ( - .COUT (_N15456), + .COUT (_N16470), .Z (N287[6]), - .CIN (_N15455), + .CIN (_N16469), .I0 (), .I1 (hor_cnt[6]), .I2 (), @@ -50679,9 +50333,9 @@ module multiline_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N12_1_7 ( - .COUT (_N15457), + .COUT (_N16471), .Z (N287[7]), - .CIN (_N15456), + .CIN (_N16470), .I0 (), .I1 (hor_cnt[7]), .I2 (), @@ -50699,9 +50353,9 @@ module multiline_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N12_1_8 ( - .COUT (_N15458), + .COUT (_N16472), .Z (N287[8]), - .CIN (_N15457), + .CIN (_N16471), .I0 (), .I1 (hor_cnt[8]), .I2 (), @@ -50719,9 +50373,9 @@ module multiline_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N12_1_9 ( - .COUT (_N15459), + .COUT (_N16473), .Z (N287[9]), - .CIN (_N15458), + .CIN (_N16472), .I0 (), .I1 (hor_cnt[9]), .I2 (), @@ -50741,7 +50395,7 @@ module multiline_buffer N12_1_10 ( .COUT (), .Z (N287[10]), - .CIN (_N15459), + .CIN (_N16473), .I0 (), .I1 (hor_cnt[10]), .I2 (), @@ -50777,7 +50431,7 @@ module multiline_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N33_1_1 ( - .COUT (_N15533), + .COUT (_N14413), .Z (N285[1]), .CIN (), .I0 (ver_cnt[0]), @@ -50797,9 +50451,9 @@ module multiline_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N33_1_2 ( - .COUT (_N15534), + .COUT (_N14414), .Z (N285[2]), - .CIN (_N15533), + .CIN (_N14413), .I0 (ver_cnt[0]), .I1 (ver_cnt[1]), .I2 (ver_cnt[2]), @@ -50817,9 +50471,9 @@ module multiline_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N33_1_3 ( - .COUT (_N15535), + .COUT (_N14415), .Z (N285[3]), - .CIN (_N15534), + .CIN (_N14414), .I0 (), .I1 (ver_cnt[3]), .I2 (), @@ -50837,9 +50491,9 @@ module multiline_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N33_1_4 ( - .COUT (_N15536), + .COUT (_N14416), .Z (N285[4]), - .CIN (_N15535), + .CIN (_N14415), .I0 (), .I1 (ver_cnt[4]), .I2 (), @@ -50857,9 +50511,9 @@ module multiline_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N33_1_5 ( - .COUT (_N15537), + .COUT (_N14417), .Z (N285[5]), - .CIN (_N15536), + .CIN (_N14416), .I0 (), .I1 (ver_cnt[5]), .I2 (), @@ -50877,9 +50531,9 @@ module multiline_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N33_1_6 ( - .COUT (_N15538), + .COUT (_N14418), .Z (N285[6]), - .CIN (_N15537), + .CIN (_N14417), .I0 (), .I1 (ver_cnt[6]), .I2 (), @@ -50897,9 +50551,9 @@ module multiline_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N33_1_7 ( - .COUT (_N15539), + .COUT (_N14419), .Z (N285[7]), - .CIN (_N15538), + .CIN (_N14418), .I0 (), .I1 (ver_cnt[7]), .I2 (), @@ -50919,7 +50573,7 @@ module multiline_buffer N33_1_8 ( .COUT (), .Z (N285[8]), - .CIN (_N15539), + .CIN (_N14419), .I0 (), .I1 (ver_cnt[8]), .I2 (), @@ -50934,8 +50588,8 @@ module multiline_buffer .INIT(32'b01110000111100001111000011110000)) \N34[0] ( .Z (N34[3]), - .I0 (_N96962), - .I1 (_N103775), + .I0 (_N97635), + .I1 (_N104598), .I2 (N285[3]), .I3 (ver_cnt[6]), .I4 (ver_cnt[5])); @@ -50946,8 +50600,8 @@ module multiline_buffer .INIT(32'b01110000111100001111000011110000)) \N34[1] ( .Z (N34[5]), - .I0 (_N96962), - .I1 (_N103775), + .I0 (_N97635), + .I1 (_N104598), .I2 (N285[5]), .I3 (ver_cnt[6]), .I4 (ver_cnt[5])); @@ -50958,8 +50612,8 @@ module multiline_buffer .INIT(32'b01110000111100001111000011110000)) \N34[2] ( .Z (N34[6]), - .I0 (_N96962), - .I1 (_N103775), + .I0 (_N97635), + .I1 (_N104598), .I2 (N285[6]), .I3 (ver_cnt[6]), .I4 (ver_cnt[5])); @@ -50970,8 +50624,8 @@ module multiline_buffer .INIT(32'b01110000111100001111000011110000)) \N34[3] ( .Z (N34[8]), - .I0 (_N96962), - .I1 (_N103775), + .I0 (_N97635), + .I1 (_N104598), .I2 (N285[8]), .I3 (ver_cnt[6]), .I4 (ver_cnt[5])); @@ -50982,8 +50636,8 @@ module multiline_buffer .INIT(32'b10000000000000000000000000000000)) N48_vname ( .Z (N48), - .I0 (_N96962), - .I1 (_N103775), + .I0 (_N97635), + .I1 (_N104598), .I2 (ver_cnt[6]), .I3 (ver_cnt[5]), .I4 (N21)); @@ -51008,7 +50662,7 @@ module multiline_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N66_1_1 ( - .COUT (_N15550), + .COUT (_N14754), .Z (N273[1]), .CIN (), .I0 (tail_ver_cnt[0]), @@ -51028,9 +50682,9 @@ module multiline_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N66_1_2 ( - .COUT (_N15551), + .COUT (_N14755), .Z (N273[2]), - .CIN (_N15550), + .CIN (_N14754), .I0 (tail_ver_cnt[0]), .I1 (tail_ver_cnt[1]), .I2 (rd3_rst), @@ -51048,9 +50702,9 @@ module multiline_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N66_1_3 ( - .COUT (_N15552), + .COUT (_N14756), .Z (N273[3]), - .CIN (_N15551), + .CIN (_N14755), .I0 (), .I1 (tail_ver_cnt[3]), .I2 (rd3_rst), @@ -51068,9 +50722,9 @@ module multiline_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N66_1_4 ( - .COUT (_N15553), + .COUT (_N14757), .Z (N273[4]), - .CIN (_N15552), + .CIN (_N14756), .I0 (), .I1 (tail_ver_cnt[4]), .I2 (rd3_rst), @@ -51090,7 +50744,7 @@ module multiline_buffer N66_1_5 ( .COUT (), .Z (N273[5]), - .CIN (_N15553), + .CIN (_N14757), .I0 (), .I1 (tail_ver_cnt[5]), .I2 (rd3_rst), @@ -51108,7 +50762,7 @@ module multiline_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_1_1 ( - .COUT (_N13480), + .COUT (_N15850), .Z (N281[1]), .CIN (), .I0 (tail_hor_cnt[0]), @@ -51128,9 +50782,9 @@ module multiline_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_1_2 ( - .COUT (_N13481), + .COUT (_N15851), .Z (N281[2]), - .CIN (_N13480), + .CIN (_N15850), .I0 (tail_hor_cnt[0]), .I1 (tail_hor_cnt[1]), .I2 (tail_hor_cnt[2]), @@ -51148,9 +50802,9 @@ module multiline_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_1_3 ( - .COUT (_N13482), + .COUT (_N15852), .Z (N281[3]), - .CIN (_N13481), + .CIN (_N15851), .I0 (), .I1 (tail_hor_cnt[3]), .I2 (), @@ -51168,9 +50822,9 @@ module multiline_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_1_4 ( - .COUT (_N13483), + .COUT (_N15853), .Z (N281[4]), - .CIN (_N13482), + .CIN (_N15852), .I0 (), .I1 (tail_hor_cnt[4]), .I2 (), @@ -51188,9 +50842,9 @@ module multiline_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_1_5 ( - .COUT (_N13484), + .COUT (_N15854), .Z (N281[5]), - .CIN (_N13483), + .CIN (_N15853), .I0 (), .I1 (tail_hor_cnt[5]), .I2 (), @@ -51208,9 +50862,9 @@ module multiline_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_1_6 ( - .COUT (_N13485), + .COUT (_N15855), .Z (N281[6]), - .CIN (_N13484), + .CIN (_N15854), .I0 (), .I1 (tail_hor_cnt[6]), .I2 (), @@ -51228,9 +50882,9 @@ module multiline_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_1_7 ( - .COUT (_N13486), + .COUT (_N15856), .Z (N281[7]), - .CIN (_N13485), + .CIN (_N15855), .I0 (), .I1 (tail_hor_cnt[7]), .I2 (), @@ -51248,9 +50902,9 @@ module multiline_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_1_8 ( - .COUT (_N13487), + .COUT (_N15857), .Z (N281[8]), - .CIN (_N13486), + .CIN (_N15856), .I0 (), .I1 (tail_hor_cnt[8]), .I2 (), @@ -51268,9 +50922,9 @@ module multiline_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_1_9 ( - .COUT (_N13488), + .COUT (_N15858), .Z (N281[9]), - .CIN (_N13487), + .CIN (_N15857), .I0 (), .I1 (tail_hor_cnt[9]), .I2 (), @@ -51290,7 +50944,7 @@ module multiline_buffer N69_1_10 ( .COUT (), .Z (N281[10]), - .CIN (_N13488), + .CIN (_N15858), .I0 (), .I1 (tail_hor_cnt[10]), .I2 (), @@ -51301,21 +50955,21 @@ module multiline_buffer // CARRY = (I1) ? CIN : (I4) ; // ../../sources/designs/image_filiter/multiline_buffer.v:111 - GTP_LUT4 /* N93_mux7_12 */ #( + GTP_LUT4 /* N93_mux7_11 */ #( .INIT(16'b1000000000000000)) - N93_mux7_12 ( - .Z (_N103894), + N93_mux7_11 ( + .Z (_N104718), .I0 (tail_hor_cnt[4]), .I1 (tail_hor_cnt[3]), .I2 (tail_hor_cnt[2]), .I3 (tail_hor_cnt[1])); // LUT = I0&I1&I2&I3 ; - GTP_LUT5 /* N93_mux7_14 */ #( + GTP_LUT5 /* N93_mux7_13 */ #( .INIT(32'b10000000000000000000000000000000)) - N93_mux7_14 ( - .Z (_N97331), - .I0 (_N103894), + N93_mux7_13 ( + .Z (_N98108), + .I0 (_N104718), .I1 (tail_hor_cnt[7]), .I2 (tail_hor_cnt[6]), .I3 (tail_hor_cnt[5]), @@ -51325,18 +50979,36 @@ module multiline_buffer GTP_LUT5 /* N96_2 */ #( .INIT(32'b00000000000000000011001100110111)) N96_2 ( - .Z (_N100855), - .I0 (_N97331), + .Z (_N100307), + .I0 (_N98108), .I1 (tail_hor_cnt[10]), .I2 (tail_hor_cnt[9]), .I3 (tail_hor_cnt[8]), .I4 (N53)); // LUT = (~I1&~I4)|(~I0&~I2&~I3&~I4) ; - GTP_LUT2 /* N122_2 */ #( + GTP_LUT1 /* N120_eq0_inv */ #( + .INIT(2'b01)) + N120_eq0_inv ( + .Z (N249), + .I0 (ver_cnt[0])); + // LUT = ~I0 ; + + GTP_LUT5 /* N122_10 */ #( + .INIT(32'b11111111111111111111111111111101)) + N122_10 ( + .Z (N179), + .I0 (_N101008), + .I1 (ver_cnt[8]), + .I2 (ver_cnt[7]), + .I3 (ver_cnt[4]), + .I4 (ver_cnt[3])); + // LUT = (~I0)|(I1)|(I2)|(I3)|(I4) ; + + GTP_LUT2 /* N122_11 */ #( .INIT(4'b1110)) - N122_2 ( - .Z (_N103908), + N122_11 ( + .Z (_N104732), .I0 (ver_cnt[0]), .I1 (N229)); // LUT = (I0)|(I1) ; @@ -51346,68 +51018,39 @@ module multiline_buffer \N130[0] ( .Z (rd_en[0]), .I0 (s_pixel_valid), - .I1 (_N100855), - .I2 (_N103908), + .I1 (_N100307), + .I2 (_N104732), .I3 (tail_ver_cnt[0]), .I4 (N179)); // LUT = (I1&~I3)|(I0&I2)|(I0&I4) ; // ../../sources/designs/image_filiter/multiline_buffer.v:154 - GTP_LUT4 /* N176_2 */ #( - .INIT(16'b0000000100000000)) - N176_2 ( - .Z (_N96962), - .I0 (ver_cnt[7]), - .I1 (ver_cnt[4]), - .I2 (ver_cnt[3]), - .I3 (ver_cnt[0])); - // LUT = ~I0&~I1&~I2&I3 ; - - GTP_LUT2 /* N176_3 */ #( - .INIT(4'b1000)) - N176_3 ( - .Z (N21), - .I0 (s_pixel_valid), - .I1 (N229)); - // LUT = I0&I1 ; - - GTP_LUT4 /* N176_12 */ #( + GTP_LUT4 /* N176_5 */ #( .INIT(16'b0000000000000001)) - N176_12 ( - .Z (_N100510), + N176_5 ( + .Z (_N101008), .I0 (ver_cnt[6]), .I1 (ver_cnt[5]), .I2 (ver_cnt[2]), .I3 (ver_cnt[1])); // LUT = ~I0&~I1&~I2&~I3 ; - GTP_LUT4 /* N176_15 */ #( + GTP_LUT4 /* N176_7 */ #( .INIT(16'b0000100000000000)) - N176_15 ( + N176_7 ( .Z (N176), - .I0 (_N96962), - .I1 (_N100510), + .I0 (_N97635), + .I1 (_N101008), .I2 (ver_cnt[8]), .I3 (N229)); // LUT = I0&I1&~I2&I3 ; - GTP_LUT5 /* N179_mux8_9 */ #( - .INIT(32'b11111111111111111111111111111101)) - N179_mux8_9 ( - .Z (N179), - .I0 (_N100510), - .I1 (ver_cnt[8]), - .I2 (ver_cnt[7]), - .I3 (ver_cnt[4]), - .I4 (ver_cnt[3])); - // LUT = (~I0)|(I1)|(I2)|(I3)|(I4) ; - GTP_LUT5 /* \N189[1]_4 */ #( .INIT(32'b11101110111011001111111111111111)) \N189[1]_4 ( .Z (rd_en[1]), .I0 (s_pixel_valid), - .I1 (_N100855), + .I1 (_N100307), .I2 (N176), .I3 (N179), .I4 (N199)); @@ -51752,7 +51395,7 @@ module multiline_buffer GTP_LUT4 /* N229_8 */ #( .INIT(16'b1000000000000000)) N229_8 ( - .Z (_N103784), + .Z (_N104607), .I0 (hor_cnt[4]), .I1 (hor_cnt[3]), .I2 (hor_cnt[2]), @@ -51762,7 +51405,7 @@ module multiline_buffer GTP_LUT4 /* N229_9 */ #( .INIT(16'b1000000000000000)) N229_9 ( - .Z (_N103785), + .Z (_N104608), .I0 (hor_cnt[10]), .I1 (hor_cnt[7]), .I2 (hor_cnt[6]), @@ -51773,43 +51416,53 @@ module multiline_buffer .INIT(32'b00000000000010000000000000000000)) N229_11 ( .Z (N229), - .I0 (_N103784), - .I1 (_N103785), + .I0 (_N104607), + .I1 (_N104608), .I2 (hor_cnt[9]), .I3 (hor_cnt[8]), .I4 (hor_cnt[0])); // LUT = I0&I1&~I2&~I3&I4 ; + GTP_LUT4 /* N236_2 */ #( + .INIT(16'b0000000100000000)) + N236_2 ( + .Z (_N97635), + .I0 (ver_cnt[7]), + .I1 (ver_cnt[4]), + .I2 (ver_cnt[3]), + .I3 (ver_cnt[0])); + // LUT = ~I0&~I1&~I2&I3 ; + GTP_LUT2 /* N236_3 */ #( .INIT(4'b1000)) N236_3 ( - .Z (_N103774), + .Z (N21), + .I0 (s_pixel_valid), + .I1 (N229)); + // LUT = I0&I1 ; + + GTP_LUT2 /* N236_10 */ #( + .INIT(4'b1000)) + N236_10 ( + .Z (_N104597), .I0 (ver_cnt[6]), .I1 (ver_cnt[5])); // LUT = I0&I1 ; - GTP_LUT3 /* N236_4 */ #( + GTP_LUT3 /* N236_11 */ #( .INIT(8'b10000000)) - N236_4 ( - .Z (_N103775), + N236_11 ( + .Z (_N104598), .I0 (ver_cnt[8]), .I1 (ver_cnt[2]), .I2 (ver_cnt[1])); // LUT = I0&I1&I2 ; - GTP_LUT1 /* N249 */ #( - .INIT(2'b01)) - N249_vname ( - .Z (N249), - .I0 (ver_cnt[0])); - // defparam N249_vname.orig_name = N249; - // LUT = ~I0 ; - - GTP_LUT5 /* N269_5 */ #( + GTP_LUT5 /* N269_9 */ #( .INIT(32'b00000000000000000000000000001000)) - N269_5 ( + N269_9 ( .Z (N269), - .I0 (_N97331), + .I0 (_N98108), .I1 (tail_hor_cnt[10]), .I2 (tail_hor_cnt[9]), .I3 (tail_hor_cnt[8]), @@ -51821,9 +51474,9 @@ module multiline_buffer N271_vname ( .Z (N271), .I0 (rd3_rst), - .I1 (_N96962), - .I2 (_N103774), - .I3 (_N103775), + .I1 (_N97635), + .I2 (_N104597), + .I3 (_N104598), .I4 (N21)); // defparam N271_vname.orig_name = N271; // LUT = ~I0&I1&I2&I3&I4 ; @@ -52139,8 +51792,8 @@ module multiline_buffer .Z (\image_filiter_inst2/multiline_buffer_inst/N272 ), .I0 (rd3_rst), .I1 (\image_filiter_inst2/multiline_buffer_inst/N53 ), - .I2 (_N97340), - .I3 (_N103920)); + .I2 (_N98107), + .I3 (_N104744)); // LUT = (I0)|(~I1&I2&I3) ; GTP_LUT4 /* \tail_hor_cnt[10:0]_or_7 */ #( @@ -53945,23 +53598,21 @@ module image_filiter input [2:0] mode, input [13:0] \param_manager_inst/selected , input [15:0] s_pixel_data, - input _N97340, - input _N103920, + input _N98107, + input _N104744, input clk, input \image_filiter_inst2/multiline_buffer_inst/N53 , input \param_manager_inst/param_filiter1_mode/changed_down , - input \param_manager_inst/param_filiter1_mode/changed_up , + input \param_manager_inst/param_filiter1_mode/pluse , input \param_manager_inst/param_filiter1_mode/pressed_down , - input \param_manager_inst/param_filiter1_mode/pressed_up , - input \param_manager_inst/param_modify_H/pluse , input rd3_rst, input s_pixel_valid, output [15:0] m_filtered_data, output \image_filiter_inst2/multiline_buffer_inst/N272 , output m_filtered_valid, output \multiline_buffer_inst/srst , - output \param_manager_inst/param_modify_V/N140 , - output \param_manager_inst/param_rotate_A/N142 + output \param_manager_inst/param_filiter1_mode/N140 , + output \param_manager_inst/param_filiter2_mode/N140 ); wire [143:0] matrix_data; wire matrix_valid; @@ -53971,17 +53622,15 @@ module image_filiter hybrid_filter hybrid_filter_inst ( .m_result_data (m_filtered_data), .mode (mode), - .\param_manager_inst/selected ({\param_manager_inst/selected [13] , 1'bx, 1'bx, 1'bx, 1'bx, \param_manager_inst/selected [8] , 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), + .\param_manager_inst/selected ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \param_manager_inst/selected [1] , \param_manager_inst/selected [0] }), .s_matrix_data (matrix_data), .m_result_valid (m_filtered_valid), - .\param_manager_inst/param_modify_V/N140 (\param_manager_inst/param_modify_V/N140 ), - .\param_manager_inst/param_rotate_A/N142 (\param_manager_inst/param_rotate_A/N142 ), + .\param_manager_inst/param_filiter1_mode/N140 (\param_manager_inst/param_filiter1_mode/N140 ), + .\param_manager_inst/param_filiter2_mode/N140 (\param_manager_inst/param_filiter2_mode/N140 ), .clk (clk), .\param_manager_inst/param_filiter1_mode/changed_down (\param_manager_inst/param_filiter1_mode/changed_down ), - .\param_manager_inst/param_filiter1_mode/changed_up (\param_manager_inst/param_filiter1_mode/changed_up ), + .\param_manager_inst/param_filiter1_mode/pluse (\param_manager_inst/param_filiter1_mode/pluse ), .\param_manager_inst/param_filiter1_mode/pressed_down (\param_manager_inst/param_filiter1_mode/pressed_down ), - .\param_manager_inst/param_filiter1_mode/pressed_up (\param_manager_inst/param_filiter1_mode/pressed_up ), - .\param_manager_inst/param_modify_H/pluse (\param_manager_inst/param_modify_H/pluse ), .rd3_rst (rd3_rst), .s_matrix_valid (matrix_valid)); // ../../sources/designs/image_filiter/image_filiter.v:69 @@ -53992,8 +53641,8 @@ module image_filiter .\image_filiter_inst2/multiline_buffer_inst/N272 (\image_filiter_inst2/multiline_buffer_inst/N272 ), .m_pixel_valid (pixel_valid), .srst (\multiline_buffer_inst/srst ), - ._N97340 (_N97340), - ._N103920 (_N103920), + ._N98107 (_N98107), + ._N104744 (_N104744), .clk (clk), .\image_filiter_inst2/multiline_buffer_inst/N53 (\image_filiter_inst2/multiline_buffer_inst/N53 ), .rd3_rst (rd3_rst), @@ -54037,54 +53686,54 @@ module gaussian_conv_unq10 wire [5:0] N72; wire [6:0] N77; wire [6:0] N78; - wire _N5626; - wire _N5634; - wire _N5639; - wire _N13897; - wire _N13898; - wire _N13899; - wire _N13900; - wire _N13901; - wire _N13958; - wire _N13959; - wire _N13960; - wire _N13961; - wire _N13962; - wire _N13992; - wire _N13993; - wire _N13994; - wire _N13995; - wire _N13996; - wire _N13997; - wire _N14000; - wire _N14001; - wire _N14002; - wire _N14003; - wire _N14004; - wire _N14029; - wire _N14030; - wire _N14031; - wire _N14032; - wire _N14033; - wire _N14519; - wire _N14520; - wire _N14521; - wire _N14522; - wire _N14523; - wire _N14524; - wire _N14527; - wire _N14528; - wire _N14529; - wire _N14530; - wire _N14531; - wire _N14532; - wire _N14855; - wire _N14856; - wire _N14857; - wire _N14858; - wire _N14859; - wire _N14860; - wire _N14861; + wire _N4751; + wire _N4759; + wire _N4764; + wire _N14089; + wire _N14090; + wire _N14091; + wire _N14092; + wire _N14093; + wire _N14094; + wire _N14145; + wire _N14146; + wire _N14147; + wire _N14148; + wire _N14149; + wire _N14150; + wire _N14489; + wire _N14490; + wire _N14491; + wire _N14492; + wire _N14493; + wire _N15249; + wire _N15250; + wire _N15251; + wire _N15252; + wire _N15253; + wire _N16902; + wire _N16903; + wire _N16904; + wire _N16905; + wire _N16906; + wire _N16907; + wire _N16908; + wire _N16931; + wire _N16932; + wire _N16933; + wire _N16934; + wire _N16935; + wire _N16938; + wire _N16939; + wire _N16940; + wire _N16941; + wire _N16942; + wire _N16945; + wire _N16946; + wire _N16947; + wire _N16948; + wire _N16949; + wire _N16950; wire [8:0] product4x2; wire [8:0] sum1x4; wire [8:0] sum4x1; @@ -54098,7 +53747,7 @@ module gaussian_conv_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_1 ( - .COUT (_N14519), + .COUT (_N14089), .Z (), .CIN (), .I0 (), @@ -54118,9 +53767,9 @@ module gaussian_conv_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_2 ( - .COUT (_N14520), + .COUT (_N14090), .Z (N78[1]), - .CIN (_N14519), + .CIN (_N14089), .I0 (N64[0]), .I1 (N61[0]), .I2 (N64[1]), @@ -54138,9 +53787,9 @@ module gaussian_conv_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_3 ( - .COUT (_N14521), + .COUT (_N14091), .Z (N78[2]), - .CIN (_N14520), + .CIN (_N14090), .I0 (), .I1 (N64[2]), .I2 (N61[2]), @@ -54158,9 +53807,9 @@ module gaussian_conv_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_4 ( - .COUT (_N14522), + .COUT (_N14092), .Z (N78[3]), - .CIN (_N14521), + .CIN (_N14091), .I0 (), .I1 (N64[3]), .I2 (N61[3]), @@ -54178,9 +53827,9 @@ module gaussian_conv_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_5 ( - .COUT (_N14523), + .COUT (_N14093), .Z (N78[4]), - .CIN (_N14522), + .CIN (_N14092), .I0 (), .I1 (N64[4]), .I2 (N61[4]), @@ -54198,9 +53847,9 @@ module gaussian_conv_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_6 ( - .COUT (_N14524), + .COUT (_N14094), .Z (N78[5]), - .CIN (_N14523), + .CIN (_N14093), .I0 (), .I1 (N64[5]), .I2 (N61[5]), @@ -54220,7 +53869,7 @@ module gaussian_conv_unq10 N17_1_7 ( .COUT (), .Z (N78[6]), - .CIN (_N14524), + .CIN (_N14094), .I0 (), .I1 (), .I2 (), @@ -54238,7 +53887,7 @@ module gaussian_conv_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_1_1 ( - .COUT (_N14527), + .COUT (_N14145), .Z (N77[0]), .CIN (), .I0 (N72[0]), @@ -54258,9 +53907,9 @@ module gaussian_conv_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_1_2 ( - .COUT (_N14528), + .COUT (_N14146), .Z (N77[1]), - .CIN (_N14527), + .CIN (_N14145), .I0 (N72[0]), .I1 (N69[0]), .I2 (N72[1]), @@ -54278,9 +53927,9 @@ module gaussian_conv_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_1_3 ( - .COUT (_N14529), + .COUT (_N14147), .Z (N77[2]), - .CIN (_N14528), + .CIN (_N14146), .I0 (), .I1 (N72[2]), .I2 (N69[2]), @@ -54298,9 +53947,9 @@ module gaussian_conv_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_1_4 ( - .COUT (_N14530), + .COUT (_N14148), .Z (N77[3]), - .CIN (_N14529), + .CIN (_N14147), .I0 (), .I1 (N72[3]), .I2 (N69[3]), @@ -54318,9 +53967,9 @@ module gaussian_conv_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_1_5 ( - .COUT (_N14531), + .COUT (_N14149), .Z (N77[4]), - .CIN (_N14530), + .CIN (_N14148), .I0 (), .I1 (N72[4]), .I2 (N69[4]), @@ -54338,9 +53987,9 @@ module gaussian_conv_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_1_6 ( - .COUT (_N14532), + .COUT (_N14150), .Z (N77[5]), - .CIN (_N14531), + .CIN (_N14149), .I0 (), .I1 (N72[5]), .I2 (N69[5]), @@ -54360,7 +54009,7 @@ module gaussian_conv_unq10 N26_1_7 ( .COUT (), .Z (N77[6]), - .CIN (_N14532), + .CIN (_N14150), .I0 (), .I1 (), .I2 (), @@ -54374,7 +54023,7 @@ module gaussian_conv_unq10 GTP_LUT2 /* N39_0_ac4 */ #( .INIT(4'b1000)) N39_0_ac4 ( - .Z (_N5634), + .Z (_N4759), .I0 (sum1x4[4]), .I1 (sum4x1[4])); // LUT = I0&I1 ; @@ -54382,7 +54031,7 @@ module gaussian_conv_unq10 GTP_LUT2 /* N39_0_ac5 */ #( .INIT(4'b1000)) N39_0_ac5 ( - .Z (_N5639), + .Z (_N4764), .I0 (sum1x4[5]), .I1 (sum4x1[5])); // LUT = I0&I1 ; @@ -54390,7 +54039,7 @@ module gaussian_conv_unq10 GTP_LUT2 /* N39_0_maj3 */ #( .INIT(4'b1110)) N39_0_maj3 ( - .Z (_N5626), + .Z (_N4751), .I0 (sum1x4[3]), .I1 (sum4x1[3])); // LUT = (I0)|(I1) ; @@ -54402,7 +54051,7 @@ module gaussian_conv_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_3_1 ( - .COUT (_N13992), + .COUT (_N16945), .Z (N59[2]), .CIN (), .I0 (sum4x1[2]), @@ -54421,9 +54070,9 @@ module gaussian_conv_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_3_2 ( - .COUT (_N13993), + .COUT (_N16946), .Z (N59[3]), - .CIN (_N13992), + .CIN (_N16945), .I0 (sum4x1[2]), .I1 (sum1x4[2]), .I2 (sum1x4[3]), @@ -54440,14 +54089,14 @@ module gaussian_conv_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_3_3 ( - .COUT (_N13994), + .COUT (_N16947), .Z (N59[4]), - .CIN (_N13993), + .CIN (_N16946), .I0 (), .I1 (sum1x4[4]), - .I2 (_N5626), + .I2 (_N4751), .I3 (sum4x1[4]), - .I4 (_N5626), + .I4 (_N4751), .ID ()); // LUT = I3^I2^I1^CIN ; // CARRY = (I3^I2^I1) ? CIN : (I4) ; @@ -54459,14 +54108,14 @@ module gaussian_conv_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_3_4 ( - .COUT (_N13995), + .COUT (_N16948), .Z (N59[5]), - .CIN (_N13994), + .CIN (_N16947), .I0 (), .I1 (sum1x4[5]), - .I2 (_N5634), + .I2 (_N4759), .I3 (sum4x1[5]), - .I4 (_N5634), + .I4 (_N4759), .ID ()); // LUT = I3^I2^I1^CIN ; // CARRY = (I3^I2^I1) ? CIN : (I4) ; @@ -54478,14 +54127,14 @@ module gaussian_conv_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_3_5 ( - .COUT (_N13996), + .COUT (_N16949), .Z (N59[6]), - .CIN (_N13995), + .CIN (_N16948), .I0 (), .I1 (sum1x4[6]), - .I2 (_N5639), + .I2 (_N4764), .I3 (sum4x1[6]), - .I4 (_N5639), + .I4 (_N4764), .ID ()); // LUT = I3^I2^I1^CIN ; // CARRY = (I3^I2^I1) ? CIN : (I4) ; @@ -54497,9 +54146,9 @@ module gaussian_conv_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_3_6 ( - .COUT (_N13997), + .COUT (_N16950), .Z (N59[7]), - .CIN (_N13996), + .CIN (_N16949), .I0 (), .I1 (sum1x4[6]), .I2 (sum4x1[6]), @@ -54518,7 +54167,7 @@ module gaussian_conv_unq10 N39_3_7 ( .COUT (), .Z (N59[8]), - .CIN (_N13997), + .CIN (_N16950), .I0 (), .I1 (), .I2 (), @@ -54535,7 +54184,7 @@ module gaussian_conv_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N47_1_1 ( - .COUT (_N14855), + .COUT (_N16902), .Z (), .CIN (), .I0 (), @@ -54555,9 +54204,9 @@ module gaussian_conv_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N47_1_2 ( - .COUT (_N14856), + .COUT (_N16903), .Z (), - .CIN (_N14855), + .CIN (_N16902), .I0 (sum8[1]), .I1 (product4x2[1]), .I2 (sum8[2]), @@ -54575,9 +54224,9 @@ module gaussian_conv_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N47_1_3 ( - .COUT (_N14857), + .COUT (_N16904), .Z (), - .CIN (_N14856), + .CIN (_N16903), .I0 (), .I1 (sum8[3]), .I2 (product4x2[3]), @@ -54595,9 +54244,9 @@ module gaussian_conv_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N47_1_4 ( - .COUT (_N14858), + .COUT (_N16905), .Z (N47[4]), - .CIN (_N14857), + .CIN (_N16904), .I0 (), .I1 (sum8[4]), .I2 (product4x2[4]), @@ -54615,9 +54264,9 @@ module gaussian_conv_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N47_1_5 ( - .COUT (_N14859), + .COUT (_N16906), .Z (N47[5]), - .CIN (_N14858), + .CIN (_N16905), .I0 (), .I1 (sum8[5]), .I2 (product4x2[5]), @@ -54635,9 +54284,9 @@ module gaussian_conv_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N47_1_6 ( - .COUT (_N14860), + .COUT (_N16907), .Z (N47[6]), - .CIN (_N14859), + .CIN (_N16906), .I0 (), .I1 (sum8[6]), .I2 (product4x2[6]), @@ -54655,9 +54304,9 @@ module gaussian_conv_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N47_1_7 ( - .COUT (_N14861), + .COUT (_N16908), .Z (N47[7]), - .CIN (_N14860), + .CIN (_N16907), .I0 (), .I1 (sum8[7]), .I2 (product4x2[7]), @@ -54677,7 +54326,7 @@ module gaussian_conv_unq10 N47_1_8 ( .COUT (), .Z (N47[8]), - .CIN (_N14861), + .CIN (_N16908), .I0 (), .I1 (sum8[8]), .I2 (), @@ -54695,7 +54344,7 @@ module gaussian_conv_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N61_1 ( - .COUT (_N13897), + .COUT (_N14489), .Z (N61[0]), .CIN (), .I0 (\mat[0][2] [0] ), @@ -54715,9 +54364,9 @@ module gaussian_conv_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N61_2 ( - .COUT (_N13898), + .COUT (_N14490), .Z (N61[1]), - .CIN (_N13897), + .CIN (_N14489), .I0 (\mat[0][2] [0] ), .I1 (\mat[0][0] [0] ), .I2 (\mat[0][2] [1] ), @@ -54735,9 +54384,9 @@ module gaussian_conv_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N61_3 ( - .COUT (_N13899), + .COUT (_N14491), .Z (N61[2]), - .CIN (_N13898), + .CIN (_N14490), .I0 (), .I1 (\mat[0][2] [2] ), .I2 (\mat[0][0] [2] ), @@ -54755,9 +54404,9 @@ module gaussian_conv_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N61_4 ( - .COUT (_N13900), + .COUT (_N14492), .Z (N61[3]), - .CIN (_N13899), + .CIN (_N14491), .I0 (), .I1 (\mat[0][2] [3] ), .I2 (\mat[0][0] [3] ), @@ -54775,9 +54424,9 @@ module gaussian_conv_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N61_5 ( - .COUT (_N13901), + .COUT (_N14493), .Z (N61[4]), - .CIN (_N13900), + .CIN (_N14492), .I0 (), .I1 (\mat[0][2] [4] ), .I2 (\mat[0][0] [4] ), @@ -54797,7 +54446,7 @@ module gaussian_conv_unq10 N61_6 ( .COUT (), .Z (N61[5]), - .CIN (_N13901), + .CIN (_N14493), .I0 (), .I1 (), .I2 (), @@ -54815,7 +54464,7 @@ module gaussian_conv_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N64_1 ( - .COUT (_N13958), + .COUT (_N16931), .Z (N64[0]), .CIN (), .I0 (\mat[2][2] [0] ), @@ -54835,9 +54484,9 @@ module gaussian_conv_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N64_2 ( - .COUT (_N13959), + .COUT (_N16932), .Z (N64[1]), - .CIN (_N13958), + .CIN (_N16931), .I0 (\mat[2][2] [0] ), .I1 (\mat[2][0] [0] ), .I2 (\mat[2][2] [1] ), @@ -54855,9 +54504,9 @@ module gaussian_conv_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N64_3 ( - .COUT (_N13960), + .COUT (_N16933), .Z (N64[2]), - .CIN (_N13959), + .CIN (_N16932), .I0 (), .I1 (\mat[2][2] [2] ), .I2 (\mat[2][0] [2] ), @@ -54875,9 +54524,9 @@ module gaussian_conv_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N64_4 ( - .COUT (_N13961), + .COUT (_N16934), .Z (N64[3]), - .CIN (_N13960), + .CIN (_N16933), .I0 (), .I1 (\mat[2][2] [3] ), .I2 (\mat[2][0] [3] ), @@ -54895,9 +54544,9 @@ module gaussian_conv_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N64_5 ( - .COUT (_N13962), + .COUT (_N16935), .Z (N64[4]), - .CIN (_N13961), + .CIN (_N16934), .I0 (), .I1 (\mat[2][2] [4] ), .I2 (\mat[2][0] [4] ), @@ -54917,7 +54566,7 @@ module gaussian_conv_unq10 N64_6 ( .COUT (), .Z (N64[5]), - .CIN (_N13962), + .CIN (_N16935), .I0 (), .I1 (), .I2 (), @@ -54935,7 +54584,7 @@ module gaussian_conv_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_1 ( - .COUT (_N14000), + .COUT (_N15249), .Z (N69[0]), .CIN (), .I0 (\mat[1][0] [0] ), @@ -54955,9 +54604,9 @@ module gaussian_conv_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_2 ( - .COUT (_N14001), + .COUT (_N15250), .Z (N69[1]), - .CIN (_N14000), + .CIN (_N15249), .I0 (\mat[1][0] [0] ), .I1 (\mat[0][1] [0] ), .I2 (\mat[1][0] [1] ), @@ -54975,9 +54624,9 @@ module gaussian_conv_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_3 ( - .COUT (_N14002), + .COUT (_N15251), .Z (N69[2]), - .CIN (_N14001), + .CIN (_N15250), .I0 (), .I1 (\mat[1][0] [2] ), .I2 (\mat[0][1] [2] ), @@ -54995,9 +54644,9 @@ module gaussian_conv_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_4 ( - .COUT (_N14003), + .COUT (_N15252), .Z (N69[3]), - .CIN (_N14002), + .CIN (_N15251), .I0 (), .I1 (\mat[1][0] [3] ), .I2 (\mat[0][1] [3] ), @@ -55015,9 +54664,9 @@ module gaussian_conv_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_5 ( - .COUT (_N14004), + .COUT (_N15253), .Z (N69[4]), - .CIN (_N14003), + .CIN (_N15252), .I0 (), .I1 (\mat[1][0] [4] ), .I2 (\mat[0][1] [4] ), @@ -55037,7 +54686,7 @@ module gaussian_conv_unq10 N69_6 ( .COUT (), .Z (N69[5]), - .CIN (_N14004), + .CIN (_N15253), .I0 (), .I1 (), .I2 (), @@ -55055,7 +54704,7 @@ module gaussian_conv_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N72_1 ( - .COUT (_N14029), + .COUT (_N16938), .Z (N72[0]), .CIN (), .I0 (\mat[2][1] [0] ), @@ -55075,9 +54724,9 @@ module gaussian_conv_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N72_2 ( - .COUT (_N14030), + .COUT (_N16939), .Z (N72[1]), - .CIN (_N14029), + .CIN (_N16938), .I0 (\mat[2][1] [0] ), .I1 (\mat[1][2] [0] ), .I2 (\mat[2][1] [1] ), @@ -55095,9 +54744,9 @@ module gaussian_conv_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N72_3 ( - .COUT (_N14031), + .COUT (_N16940), .Z (N72[2]), - .CIN (_N14030), + .CIN (_N16939), .I0 (), .I1 (\mat[2][1] [2] ), .I2 (\mat[1][2] [2] ), @@ -55115,9 +54764,9 @@ module gaussian_conv_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N72_4 ( - .COUT (_N14032), + .COUT (_N16941), .Z (N72[3]), - .CIN (_N14031), + .CIN (_N16940), .I0 (), .I1 (\mat[2][1] [3] ), .I2 (\mat[1][2] [3] ), @@ -55135,9 +54784,9 @@ module gaussian_conv_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N72_5 ( - .COUT (_N14033), + .COUT (_N16942), .Z (N72[4]), - .CIN (_N14032), + .CIN (_N16941), .I0 (), .I1 (\mat[2][1] [4] ), .I2 (\mat[1][2] [4] ), @@ -55157,7 +54806,7 @@ module gaussian_conv_unq10 N72_6 ( .COUT (), .Z (N72[5]), - .CIN (_N14033), + .CIN (_N16942), .I0 (), .I1 (), .I2 (), @@ -55981,63 +55630,63 @@ module gaussian_conv_1_unq4 wire [6:0] N72; wire [7:0] N77; wire [7:0] N78; - wire _N4428; - wire _N4436; - wire _N4441; - wire _N4446; - wire _N14081; - wire _N14082; - wire _N14083; - wire _N14084; - wire _N14085; - wire _N14086; - wire _N14087; - wire _N14131; - wire _N14132; - wire _N14133; - wire _N14134; - wire _N14135; - wire _N14136; - wire _N14137; - wire _N14140; - wire _N14141; - wire _N14142; - wire _N14143; - wire _N14144; - wire _N14145; - wire _N14146; - wire _N14167; - wire _N14168; - wire _N14169; - wire _N14170; - wire _N14171; - wire _N14172; - wire _N14173; - wire _N14174; - wire _N14218; - wire _N14219; - wire _N14220; - wire _N14221; - wire _N14222; - wire _N14223; - wire _N14755; - wire _N14756; - wire _N14757; - wire _N14758; - wire _N14759; - wire _N14760; - wire _N14814; - wire _N14815; - wire _N14816; - wire _N14817; - wire _N14818; - wire _N14819; - wire _N14894; - wire _N14895; - wire _N14896; - wire _N14897; - wire _N14898; - wire _N14899; + wire _N3302; + wire _N3310; + wire _N3315; + wire _N3320; + wire _N13875; + wire _N13876; + wire _N13877; + wire _N13878; + wire _N13879; + wire _N13880; + wire _N13881; + wire _N13902; + wire _N13903; + wire _N13904; + wire _N13905; + wire _N13906; + wire _N13907; + wire _N13908; + wire _N13911; + wire _N13912; + wire _N13913; + wire _N13914; + wire _N13915; + wire _N13916; + wire _N13917; + wire _N13918; + wire _N13937; + wire _N13938; + wire _N13939; + wire _N13940; + wire _N13941; + wire _N13942; + wire _N13943; + wire _N13946; + wire _N13947; + wire _N13948; + wire _N13949; + wire _N13950; + wire _N13951; + wire _N13954; + wire _N13955; + wire _N13956; + wire _N13957; + wire _N13958; + wire _N13959; + wire _N13971; + wire _N13972; + wire _N13973; + wire _N13974; + wire _N13975; + wire _N13976; + wire _N13979; + wire _N13980; + wire _N13981; + wire _N13982; + wire _N13983; + wire _N13984; wire [9:0] product4x2; wire [9:0] sum1x4; wire [9:0] sum4x1; @@ -56051,7 +55700,7 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_1 ( - .COUT (_N14081), + .COUT (_N13875), .Z (), .CIN (), .I0 (), @@ -56071,9 +55720,9 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_2 ( - .COUT (_N14082), + .COUT (_N13876), .Z (N78[1]), - .CIN (_N14081), + .CIN (_N13875), .I0 (N64[0]), .I1 (N61[0]), .I2 (N64[1]), @@ -56091,9 +55740,9 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_3 ( - .COUT (_N14083), + .COUT (_N13877), .Z (N78[2]), - .CIN (_N14082), + .CIN (_N13876), .I0 (), .I1 (N64[2]), .I2 (N61[2]), @@ -56111,9 +55760,9 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_4 ( - .COUT (_N14084), + .COUT (_N13878), .Z (N78[3]), - .CIN (_N14083), + .CIN (_N13877), .I0 (), .I1 (N64[3]), .I2 (N61[3]), @@ -56131,9 +55780,9 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_5 ( - .COUT (_N14085), + .COUT (_N13879), .Z (N78[4]), - .CIN (_N14084), + .CIN (_N13878), .I0 (), .I1 (N64[4]), .I2 (N61[4]), @@ -56151,9 +55800,9 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_6 ( - .COUT (_N14086), + .COUT (_N13880), .Z (N78[5]), - .CIN (_N14085), + .CIN (_N13879), .I0 (), .I1 (N64[5]), .I2 (N61[5]), @@ -56171,9 +55820,9 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_7 ( - .COUT (_N14087), + .COUT (_N13881), .Z (N78[6]), - .CIN (_N14086), + .CIN (_N13880), .I0 (), .I1 (N64[6]), .I2 (N61[6]), @@ -56193,7 +55842,7 @@ module gaussian_conv_1_unq4 N17_1_8 ( .COUT (), .Z (N78[7]), - .CIN (_N14087), + .CIN (_N13881), .I0 (), .I1 (), .I2 (), @@ -56211,7 +55860,7 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_1_1 ( - .COUT (_N14131), + .COUT (_N13902), .Z (N77[0]), .CIN (), .I0 (N72[0]), @@ -56231,9 +55880,9 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_1_2 ( - .COUT (_N14132), + .COUT (_N13903), .Z (N77[1]), - .CIN (_N14131), + .CIN (_N13902), .I0 (N72[0]), .I1 (N69[0]), .I2 (N72[1]), @@ -56251,9 +55900,9 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_1_3 ( - .COUT (_N14133), + .COUT (_N13904), .Z (N77[2]), - .CIN (_N14132), + .CIN (_N13903), .I0 (), .I1 (N72[2]), .I2 (N69[2]), @@ -56271,9 +55920,9 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_1_4 ( - .COUT (_N14134), + .COUT (_N13905), .Z (N77[3]), - .CIN (_N14133), + .CIN (_N13904), .I0 (), .I1 (N72[3]), .I2 (N69[3]), @@ -56291,9 +55940,9 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_1_5 ( - .COUT (_N14135), + .COUT (_N13906), .Z (N77[4]), - .CIN (_N14134), + .CIN (_N13905), .I0 (), .I1 (N72[4]), .I2 (N69[4]), @@ -56311,9 +55960,9 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_1_6 ( - .COUT (_N14136), + .COUT (_N13907), .Z (N77[5]), - .CIN (_N14135), + .CIN (_N13906), .I0 (), .I1 (N72[5]), .I2 (N69[5]), @@ -56331,9 +55980,9 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_1_7 ( - .COUT (_N14137), + .COUT (_N13908), .Z (N77[6]), - .CIN (_N14136), + .CIN (_N13907), .I0 (), .I1 (N72[6]), .I2 (N69[6]), @@ -56353,7 +56002,7 @@ module gaussian_conv_1_unq4 N26_1_8 ( .COUT (), .Z (N77[7]), - .CIN (_N14137), + .CIN (_N13908), .I0 (), .I1 (), .I2 (), @@ -56367,7 +56016,7 @@ module gaussian_conv_1_unq4 GTP_LUT2 /* N39_0_ac4 */ #( .INIT(4'b1000)) N39_0_ac4 ( - .Z (_N4436), + .Z (_N3310), .I0 (sum1x4[4]), .I1 (sum4x1[4])); // LUT = I0&I1 ; @@ -56375,7 +56024,7 @@ module gaussian_conv_1_unq4 GTP_LUT2 /* N39_0_ac5 */ #( .INIT(4'b1000)) N39_0_ac5 ( - .Z (_N4441), + .Z (_N3315), .I0 (sum1x4[5]), .I1 (sum4x1[5])); // LUT = I0&I1 ; @@ -56383,7 +56032,7 @@ module gaussian_conv_1_unq4 GTP_LUT2 /* N39_0_ac6 */ #( .INIT(4'b1000)) N39_0_ac6 ( - .Z (_N4446), + .Z (_N3320), .I0 (sum1x4[6]), .I1 (sum4x1[6])); // LUT = I0&I1 ; @@ -56391,7 +56040,7 @@ module gaussian_conv_1_unq4 GTP_LUT2 /* N39_0_maj3 */ #( .INIT(4'b1110)) N39_0_maj3 ( - .Z (_N4428), + .Z (_N3302), .I0 (sum1x4[3]), .I1 (sum4x1[3])); // LUT = (I0)|(I1) ; @@ -56403,7 +56052,7 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_3_1 ( - .COUT (_N14140), + .COUT (_N13937), .Z (N59[2]), .CIN (), .I0 (sum4x1[2]), @@ -56422,9 +56071,9 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_3_2 ( - .COUT (_N14141), + .COUT (_N13938), .Z (N59[3]), - .CIN (_N14140), + .CIN (_N13937), .I0 (sum4x1[2]), .I1 (sum1x4[2]), .I2 (sum1x4[3]), @@ -56441,14 +56090,14 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_3_3 ( - .COUT (_N14142), + .COUT (_N13939), .Z (N59[4]), - .CIN (_N14141), + .CIN (_N13938), .I0 (), .I1 (sum1x4[4]), - .I2 (_N4428), + .I2 (_N3302), .I3 (sum4x1[4]), - .I4 (_N4428), + .I4 (_N3302), .ID ()); // LUT = I3^I2^I1^CIN ; // CARRY = (I3^I2^I1) ? CIN : (I4) ; @@ -56460,14 +56109,14 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_3_4 ( - .COUT (_N14143), + .COUT (_N13940), .Z (N59[5]), - .CIN (_N14142), + .CIN (_N13939), .I0 (), .I1 (sum1x4[5]), - .I2 (_N4436), + .I2 (_N3310), .I3 (sum4x1[5]), - .I4 (_N4436), + .I4 (_N3310), .ID ()); // LUT = I3^I2^I1^CIN ; // CARRY = (I3^I2^I1) ? CIN : (I4) ; @@ -56479,14 +56128,14 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_3_5 ( - .COUT (_N14144), + .COUT (_N13941), .Z (N59[6]), - .CIN (_N14143), + .CIN (_N13940), .I0 (), .I1 (sum1x4[6]), - .I2 (_N4441), + .I2 (_N3315), .I3 (sum4x1[6]), - .I4 (_N4441), + .I4 (_N3315), .ID ()); // LUT = I3^I2^I1^CIN ; // CARRY = (I3^I2^I1) ? CIN : (I4) ; @@ -56498,14 +56147,14 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_3_6 ( - .COUT (_N14145), + .COUT (_N13942), .Z (N59[7]), - .CIN (_N14144), + .CIN (_N13941), .I0 (), .I1 (sum1x4[7]), - .I2 (_N4446), + .I2 (_N3320), .I3 (sum4x1[7]), - .I4 (_N4446), + .I4 (_N3320), .ID ()); // LUT = I3^I2^I1^CIN ; // CARRY = (I3^I2^I1) ? CIN : (I4) ; @@ -56517,9 +56166,9 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_3_7 ( - .COUT (_N14146), + .COUT (_N13943), .Z (N59[8]), - .CIN (_N14145), + .CIN (_N13942), .I0 (), .I1 (sum1x4[7]), .I2 (sum4x1[7]), @@ -56538,7 +56187,7 @@ module gaussian_conv_1_unq4 N39_3_8 ( .COUT (), .Z (N59[9]), - .CIN (_N14146), + .CIN (_N13943), .I0 (), .I1 (), .I2 (), @@ -56555,7 +56204,7 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N47_1_1 ( - .COUT (_N14167), + .COUT (_N13911), .Z (), .CIN (), .I0 (), @@ -56575,9 +56224,9 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N47_1_2 ( - .COUT (_N14168), + .COUT (_N13912), .Z (), - .CIN (_N14167), + .CIN (_N13911), .I0 (sum8[1]), .I1 (product4x2[1]), .I2 (sum8[2]), @@ -56595,9 +56244,9 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N47_1_3 ( - .COUT (_N14169), + .COUT (_N13913), .Z (), - .CIN (_N14168), + .CIN (_N13912), .I0 (), .I1 (sum8[3]), .I2 (product4x2[3]), @@ -56615,9 +56264,9 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N47_1_4 ( - .COUT (_N14170), + .COUT (_N13914), .Z (N47[4]), - .CIN (_N14169), + .CIN (_N13913), .I0 (), .I1 (sum8[4]), .I2 (product4x2[4]), @@ -56635,9 +56284,9 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N47_1_5 ( - .COUT (_N14171), + .COUT (_N13915), .Z (N47[5]), - .CIN (_N14170), + .CIN (_N13914), .I0 (), .I1 (sum8[5]), .I2 (product4x2[5]), @@ -56655,9 +56304,9 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N47_1_6 ( - .COUT (_N14172), + .COUT (_N13916), .Z (N47[6]), - .CIN (_N14171), + .CIN (_N13915), .I0 (), .I1 (sum8[6]), .I2 (product4x2[6]), @@ -56675,9 +56324,9 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N47_1_7 ( - .COUT (_N14173), + .COUT (_N13917), .Z (N47[7]), - .CIN (_N14172), + .CIN (_N13916), .I0 (), .I1 (sum8[7]), .I2 (product4x2[7]), @@ -56695,9 +56344,9 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N47_1_8 ( - .COUT (_N14174), + .COUT (_N13918), .Z (N47[8]), - .CIN (_N14173), + .CIN (_N13917), .I0 (), .I1 (sum8[8]), .I2 (product4x2[8]), @@ -56717,7 +56366,7 @@ module gaussian_conv_1_unq4 N47_1_9 ( .COUT (), .Z (N47[9]), - .CIN (_N14174), + .CIN (_N13918), .I0 (), .I1 (sum8[9]), .I2 (), @@ -56735,7 +56384,7 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N61_1 ( - .COUT (_N14218), + .COUT (_N13946), .Z (N61[0]), .CIN (), .I0 (\mat[0][2] [0] ), @@ -56755,9 +56404,9 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N61_2 ( - .COUT (_N14219), + .COUT (_N13947), .Z (N61[1]), - .CIN (_N14218), + .CIN (_N13946), .I0 (\mat[0][2] [0] ), .I1 (\mat[0][0] [0] ), .I2 (\mat[0][2] [1] ), @@ -56775,9 +56424,9 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N61_3 ( - .COUT (_N14220), + .COUT (_N13948), .Z (N61[2]), - .CIN (_N14219), + .CIN (_N13947), .I0 (), .I1 (\mat[0][2] [2] ), .I2 (\mat[0][0] [2] ), @@ -56795,9 +56444,9 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N61_4 ( - .COUT (_N14221), + .COUT (_N13949), .Z (N61[3]), - .CIN (_N14220), + .CIN (_N13948), .I0 (), .I1 (\mat[0][2] [3] ), .I2 (\mat[0][0] [3] ), @@ -56815,9 +56464,9 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N61_5 ( - .COUT (_N14222), + .COUT (_N13950), .Z (N61[4]), - .CIN (_N14221), + .CIN (_N13949), .I0 (), .I1 (\mat[0][2] [4] ), .I2 (\mat[0][0] [4] ), @@ -56835,9 +56484,9 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N61_6 ( - .COUT (_N14223), + .COUT (_N13951), .Z (N61[5]), - .CIN (_N14222), + .CIN (_N13950), .I0 (), .I1 (\mat[0][2] [5] ), .I2 (\mat[0][0] [5] ), @@ -56857,7 +56506,7 @@ module gaussian_conv_1_unq4 N61_7 ( .COUT (), .Z (N61[6]), - .CIN (_N14223), + .CIN (_N13951), .I0 (), .I1 (), .I2 (), @@ -56875,7 +56524,7 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N64_1 ( - .COUT (_N14755), + .COUT (_N13954), .Z (N64[0]), .CIN (), .I0 (\mat[2][2] [0] ), @@ -56895,9 +56544,9 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N64_2 ( - .COUT (_N14756), + .COUT (_N13955), .Z (N64[1]), - .CIN (_N14755), + .CIN (_N13954), .I0 (\mat[2][2] [0] ), .I1 (\mat[2][0] [0] ), .I2 (\mat[2][2] [1] ), @@ -56915,9 +56564,9 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N64_3 ( - .COUT (_N14757), + .COUT (_N13956), .Z (N64[2]), - .CIN (_N14756), + .CIN (_N13955), .I0 (), .I1 (\mat[2][2] [2] ), .I2 (\mat[2][0] [2] ), @@ -56935,9 +56584,9 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N64_4 ( - .COUT (_N14758), + .COUT (_N13957), .Z (N64[3]), - .CIN (_N14757), + .CIN (_N13956), .I0 (), .I1 (\mat[2][2] [3] ), .I2 (\mat[2][0] [3] ), @@ -56955,9 +56604,9 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N64_5 ( - .COUT (_N14759), + .COUT (_N13958), .Z (N64[4]), - .CIN (_N14758), + .CIN (_N13957), .I0 (), .I1 (\mat[2][2] [4] ), .I2 (\mat[2][0] [4] ), @@ -56975,9 +56624,9 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N64_6 ( - .COUT (_N14760), + .COUT (_N13959), .Z (N64[5]), - .CIN (_N14759), + .CIN (_N13958), .I0 (), .I1 (\mat[2][2] [5] ), .I2 (\mat[2][0] [5] ), @@ -56997,7 +56646,7 @@ module gaussian_conv_1_unq4 N64_7 ( .COUT (), .Z (N64[6]), - .CIN (_N14760), + .CIN (_N13959), .I0 (), .I1 (), .I2 (), @@ -57015,7 +56664,7 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_1 ( - .COUT (_N14814), + .COUT (_N13971), .Z (N69[0]), .CIN (), .I0 (\mat[1][0] [0] ), @@ -57035,9 +56684,9 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_2 ( - .COUT (_N14815), + .COUT (_N13972), .Z (N69[1]), - .CIN (_N14814), + .CIN (_N13971), .I0 (\mat[1][0] [0] ), .I1 (\mat[0][1] [0] ), .I2 (\mat[1][0] [1] ), @@ -57055,9 +56704,9 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_3 ( - .COUT (_N14816), + .COUT (_N13973), .Z (N69[2]), - .CIN (_N14815), + .CIN (_N13972), .I0 (), .I1 (\mat[1][0] [2] ), .I2 (\mat[0][1] [2] ), @@ -57075,9 +56724,9 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_4 ( - .COUT (_N14817), + .COUT (_N13974), .Z (N69[3]), - .CIN (_N14816), + .CIN (_N13973), .I0 (), .I1 (\mat[1][0] [3] ), .I2 (\mat[0][1] [3] ), @@ -57095,9 +56744,9 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_5 ( - .COUT (_N14818), + .COUT (_N13975), .Z (N69[4]), - .CIN (_N14817), + .CIN (_N13974), .I0 (), .I1 (\mat[1][0] [4] ), .I2 (\mat[0][1] [4] ), @@ -57115,9 +56764,9 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_6 ( - .COUT (_N14819), + .COUT (_N13976), .Z (N69[5]), - .CIN (_N14818), + .CIN (_N13975), .I0 (), .I1 (\mat[1][0] [5] ), .I2 (\mat[0][1] [5] ), @@ -57137,7 +56786,7 @@ module gaussian_conv_1_unq4 N69_7 ( .COUT (), .Z (N69[6]), - .CIN (_N14819), + .CIN (_N13976), .I0 (), .I1 (), .I2 (), @@ -57155,7 +56804,7 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N72_1 ( - .COUT (_N14894), + .COUT (_N13979), .Z (N72[0]), .CIN (), .I0 (\mat[2][1] [0] ), @@ -57175,9 +56824,9 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N72_2 ( - .COUT (_N14895), + .COUT (_N13980), .Z (N72[1]), - .CIN (_N14894), + .CIN (_N13979), .I0 (\mat[2][1] [0] ), .I1 (\mat[1][2] [0] ), .I2 (\mat[2][1] [1] ), @@ -57195,9 +56844,9 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N72_3 ( - .COUT (_N14896), + .COUT (_N13981), .Z (N72[2]), - .CIN (_N14895), + .CIN (_N13980), .I0 (), .I1 (\mat[2][1] [2] ), .I2 (\mat[1][2] [2] ), @@ -57215,9 +56864,9 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N72_4 ( - .COUT (_N14897), + .COUT (_N13982), .Z (N72[3]), - .CIN (_N14896), + .CIN (_N13981), .I0 (), .I1 (\mat[2][1] [3] ), .I2 (\mat[1][2] [3] ), @@ -57235,9 +56884,9 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N72_5 ( - .COUT (_N14898), + .COUT (_N13983), .Z (N72[4]), - .CIN (_N14897), + .CIN (_N13982), .I0 (), .I1 (\mat[2][1] [4] ), .I2 (\mat[1][2] [4] ), @@ -57255,9 +56904,9 @@ module gaussian_conv_1_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N72_6 ( - .COUT (_N14899), + .COUT (_N13984), .Z (N72[5]), - .CIN (_N14898), + .CIN (_N13983), .I0 (), .I1 (\mat[2][1] [5] ), .I2 (\mat[1][2] [5] ), @@ -57277,7 +56926,7 @@ module gaussian_conv_1_unq4 N72_7 ( .COUT (), .Z (N72[6]), - .CIN (_N14899), + .CIN (_N13984), .I0 (), .I1 (), .I2 (), @@ -58242,54 +57891,54 @@ module gaussian_conv_unq12 wire [5:0] N72; wire [6:0] N77; wire [6:0] N78; - wire _N3100; - wire _N3108; - wire _N3113; - wire _N13852; - wire _N13853; - wire _N13854; - wire _N13855; - wire _N13856; - wire _N13857; - wire _N13872; - wire _N13873; - wire _N13874; - wire _N13875; - wire _N13876; - wire _N13877; - wire _N13880; - wire _N13881; - wire _N13882; - wire _N13883; - wire _N13884; - wire _N13885; - wire _N13886; - wire _N13926; - wire _N13927; - wire _N13928; - wire _N13929; - wire _N13930; - wire _N13951; - wire _N13952; - wire _N13953; - wire _N13954; - wire _N13955; - wire _N13978; - wire _N13979; - wire _N13980; - wire _N13981; - wire _N13982; - wire _N13985; - wire _N13986; - wire _N13987; - wire _N13988; - wire _N13989; - wire _N14796; - wire _N14797; - wire _N14798; - wire _N14799; - wire _N14800; - wire _N14801; + wire _N4509; + wire _N4517; + wire _N4522; + wire _N14073; + wire _N14074; + wire _N14075; + wire _N14076; + wire _N14077; + wire _N14078; + wire _N14081; + wire _N14082; + wire _N14083; + wire _N14084; + wire _N14085; + wire _N14086; + wire _N14105; + wire _N14106; + wire _N14107; + wire _N14108; + wire _N14109; + wire _N14110; + wire _N14111; + wire _N14153; + wire _N14154; + wire _N14155; + wire _N14156; + wire _N14157; + wire _N14170; + wire _N14171; + wire _N14172; + wire _N14173; + wire _N14174; + wire _N14190; + wire _N14191; + wire _N14192; + wire _N14193; + wire _N14194; + wire _N14197; + wire _N14198; + wire _N14199; + wire _N14200; + wire _N14201; + wire _N14227; + wire _N14228; + wire _N14229; + wire _N14230; + wire _N14231; + wire _N14232; wire [8:0] product4x2; wire [8:0] sum1x4; wire [8:0] sum4x1; @@ -58303,7 +57952,7 @@ module gaussian_conv_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_1 ( - .COUT (_N13852), + .COUT (_N14073), .Z (), .CIN (), .I0 (), @@ -58323,9 +57972,9 @@ module gaussian_conv_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_2 ( - .COUT (_N13853), + .COUT (_N14074), .Z (N78[1]), - .CIN (_N13852), + .CIN (_N14073), .I0 (N64[0]), .I1 (N61[0]), .I2 (N64[1]), @@ -58343,9 +57992,9 @@ module gaussian_conv_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_3 ( - .COUT (_N13854), + .COUT (_N14075), .Z (N78[2]), - .CIN (_N13853), + .CIN (_N14074), .I0 (), .I1 (N64[2]), .I2 (N61[2]), @@ -58363,9 +58012,9 @@ module gaussian_conv_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_4 ( - .COUT (_N13855), + .COUT (_N14076), .Z (N78[3]), - .CIN (_N13854), + .CIN (_N14075), .I0 (), .I1 (N64[3]), .I2 (N61[3]), @@ -58383,9 +58032,9 @@ module gaussian_conv_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_5 ( - .COUT (_N13856), + .COUT (_N14077), .Z (N78[4]), - .CIN (_N13855), + .CIN (_N14076), .I0 (), .I1 (N64[4]), .I2 (N61[4]), @@ -58403,9 +58052,9 @@ module gaussian_conv_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_6 ( - .COUT (_N13857), + .COUT (_N14078), .Z (N78[5]), - .CIN (_N13856), + .CIN (_N14077), .I0 (), .I1 (N64[5]), .I2 (N61[5]), @@ -58425,7 +58074,7 @@ module gaussian_conv_unq12 N17_1_7 ( .COUT (), .Z (N78[6]), - .CIN (_N13857), + .CIN (_N14078), .I0 (), .I1 (), .I2 (), @@ -58443,7 +58092,7 @@ module gaussian_conv_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_1_1 ( - .COUT (_N13872), + .COUT (_N14081), .Z (N77[0]), .CIN (), .I0 (N72[0]), @@ -58463,9 +58112,9 @@ module gaussian_conv_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_1_2 ( - .COUT (_N13873), + .COUT (_N14082), .Z (N77[1]), - .CIN (_N13872), + .CIN (_N14081), .I0 (N72[0]), .I1 (N69[0]), .I2 (N72[1]), @@ -58483,9 +58132,9 @@ module gaussian_conv_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_1_3 ( - .COUT (_N13874), + .COUT (_N14083), .Z (N77[2]), - .CIN (_N13873), + .CIN (_N14082), .I0 (), .I1 (N72[2]), .I2 (N69[2]), @@ -58503,9 +58152,9 @@ module gaussian_conv_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_1_4 ( - .COUT (_N13875), + .COUT (_N14084), .Z (N77[3]), - .CIN (_N13874), + .CIN (_N14083), .I0 (), .I1 (N72[3]), .I2 (N69[3]), @@ -58523,9 +58172,9 @@ module gaussian_conv_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_1_5 ( - .COUT (_N13876), + .COUT (_N14085), .Z (N77[4]), - .CIN (_N13875), + .CIN (_N14084), .I0 (), .I1 (N72[4]), .I2 (N69[4]), @@ -58543,9 +58192,9 @@ module gaussian_conv_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N26_1_6 ( - .COUT (_N13877), + .COUT (_N14086), .Z (N77[5]), - .CIN (_N13876), + .CIN (_N14085), .I0 (), .I1 (N72[5]), .I2 (N69[5]), @@ -58565,7 +58214,7 @@ module gaussian_conv_unq12 N26_1_7 ( .COUT (), .Z (N77[6]), - .CIN (_N13877), + .CIN (_N14086), .I0 (), .I1 (), .I2 (), @@ -58579,7 +58228,7 @@ module gaussian_conv_unq12 GTP_LUT2 /* N39_0_ac4 */ #( .INIT(4'b1000)) N39_0_ac4 ( - .Z (_N3108), + .Z (_N4517), .I0 (sum1x4[4]), .I1 (sum4x1[4])); // LUT = I0&I1 ; @@ -58587,7 +58236,7 @@ module gaussian_conv_unq12 GTP_LUT2 /* N39_0_ac5 */ #( .INIT(4'b1000)) N39_0_ac5 ( - .Z (_N3113), + .Z (_N4522), .I0 (sum1x4[5]), .I1 (sum4x1[5])); // LUT = I0&I1 ; @@ -58595,7 +58244,7 @@ module gaussian_conv_unq12 GTP_LUT2 /* N39_0_maj3 */ #( .INIT(4'b1110)) N39_0_maj3 ( - .Z (_N3100), + .Z (_N4509), .I0 (sum1x4[3]), .I1 (sum4x1[3])); // LUT = (I0)|(I1) ; @@ -58607,7 +58256,7 @@ module gaussian_conv_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_3_1 ( - .COUT (_N14796), + .COUT (_N14227), .Z (N59[2]), .CIN (), .I0 (sum4x1[2]), @@ -58626,9 +58275,9 @@ module gaussian_conv_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_3_2 ( - .COUT (_N14797), + .COUT (_N14228), .Z (N59[3]), - .CIN (_N14796), + .CIN (_N14227), .I0 (sum4x1[2]), .I1 (sum1x4[2]), .I2 (sum1x4[3]), @@ -58645,14 +58294,14 @@ module gaussian_conv_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_3_3 ( - .COUT (_N14798), + .COUT (_N14229), .Z (N59[4]), - .CIN (_N14797), + .CIN (_N14228), .I0 (), .I1 (sum1x4[4]), - .I2 (_N3100), + .I2 (_N4509), .I3 (sum4x1[4]), - .I4 (_N3100), + .I4 (_N4509), .ID ()); // LUT = I3^I2^I1^CIN ; // CARRY = (I3^I2^I1) ? CIN : (I4) ; @@ -58664,14 +58313,14 @@ module gaussian_conv_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_3_4 ( - .COUT (_N14799), + .COUT (_N14230), .Z (N59[5]), - .CIN (_N14798), + .CIN (_N14229), .I0 (), .I1 (sum1x4[5]), - .I2 (_N3108), + .I2 (_N4517), .I3 (sum4x1[5]), - .I4 (_N3108), + .I4 (_N4517), .ID ()); // LUT = I3^I2^I1^CIN ; // CARRY = (I3^I2^I1) ? CIN : (I4) ; @@ -58683,14 +58332,14 @@ module gaussian_conv_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_3_5 ( - .COUT (_N14800), + .COUT (_N14231), .Z (N59[6]), - .CIN (_N14799), + .CIN (_N14230), .I0 (), .I1 (sum1x4[6]), - .I2 (_N3113), + .I2 (_N4522), .I3 (sum4x1[6]), - .I4 (_N3113), + .I4 (_N4522), .ID ()); // LUT = I3^I2^I1^CIN ; // CARRY = (I3^I2^I1) ? CIN : (I4) ; @@ -58702,9 +58351,9 @@ module gaussian_conv_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_3_6 ( - .COUT (_N14801), + .COUT (_N14232), .Z (N59[7]), - .CIN (_N14800), + .CIN (_N14231), .I0 (), .I1 (sum1x4[6]), .I2 (sum4x1[6]), @@ -58723,7 +58372,7 @@ module gaussian_conv_unq12 N39_3_7 ( .COUT (), .Z (N59[8]), - .CIN (_N14801), + .CIN (_N14232), .I0 (), .I1 (), .I2 (), @@ -58740,7 +58389,7 @@ module gaussian_conv_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N47_1_1 ( - .COUT (_N13880), + .COUT (_N14105), .Z (), .CIN (), .I0 (), @@ -58760,9 +58409,9 @@ module gaussian_conv_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N47_1_2 ( - .COUT (_N13881), + .COUT (_N14106), .Z (), - .CIN (_N13880), + .CIN (_N14105), .I0 (sum8[1]), .I1 (product4x2[1]), .I2 (sum8[2]), @@ -58780,9 +58429,9 @@ module gaussian_conv_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N47_1_3 ( - .COUT (_N13882), + .COUT (_N14107), .Z (), - .CIN (_N13881), + .CIN (_N14106), .I0 (), .I1 (sum8[3]), .I2 (product4x2[3]), @@ -58800,9 +58449,9 @@ module gaussian_conv_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N47_1_4 ( - .COUT (_N13883), + .COUT (_N14108), .Z (N47[4]), - .CIN (_N13882), + .CIN (_N14107), .I0 (), .I1 (sum8[4]), .I2 (product4x2[4]), @@ -58820,9 +58469,9 @@ module gaussian_conv_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N47_1_5 ( - .COUT (_N13884), + .COUT (_N14109), .Z (N47[5]), - .CIN (_N13883), + .CIN (_N14108), .I0 (), .I1 (sum8[5]), .I2 (product4x2[5]), @@ -58840,9 +58489,9 @@ module gaussian_conv_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N47_1_6 ( - .COUT (_N13885), + .COUT (_N14110), .Z (N47[6]), - .CIN (_N13884), + .CIN (_N14109), .I0 (), .I1 (sum8[6]), .I2 (product4x2[6]), @@ -58860,9 +58509,9 @@ module gaussian_conv_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N47_1_7 ( - .COUT (_N13886), + .COUT (_N14111), .Z (N47[7]), - .CIN (_N13885), + .CIN (_N14110), .I0 (), .I1 (sum8[7]), .I2 (product4x2[7]), @@ -58882,7 +58531,7 @@ module gaussian_conv_unq12 N47_1_8 ( .COUT (), .Z (N47[8]), - .CIN (_N13886), + .CIN (_N14111), .I0 (), .I1 (sum8[8]), .I2 (), @@ -58900,7 +58549,7 @@ module gaussian_conv_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N61_1 ( - .COUT (_N13926), + .COUT (_N14153), .Z (N61[0]), .CIN (), .I0 (\mat[0][2] [0] ), @@ -58920,9 +58569,9 @@ module gaussian_conv_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N61_2 ( - .COUT (_N13927), + .COUT (_N14154), .Z (N61[1]), - .CIN (_N13926), + .CIN (_N14153), .I0 (\mat[0][2] [0] ), .I1 (\mat[0][0] [0] ), .I2 (\mat[0][2] [1] ), @@ -58940,9 +58589,9 @@ module gaussian_conv_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N61_3 ( - .COUT (_N13928), + .COUT (_N14155), .Z (N61[2]), - .CIN (_N13927), + .CIN (_N14154), .I0 (), .I1 (\mat[0][2] [2] ), .I2 (\mat[0][0] [2] ), @@ -58960,9 +58609,9 @@ module gaussian_conv_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N61_4 ( - .COUT (_N13929), + .COUT (_N14156), .Z (N61[3]), - .CIN (_N13928), + .CIN (_N14155), .I0 (), .I1 (\mat[0][2] [3] ), .I2 (\mat[0][0] [3] ), @@ -58980,9 +58629,9 @@ module gaussian_conv_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N61_5 ( - .COUT (_N13930), + .COUT (_N14157), .Z (N61[4]), - .CIN (_N13929), + .CIN (_N14156), .I0 (), .I1 (\mat[0][2] [4] ), .I2 (\mat[0][0] [4] ), @@ -59002,7 +58651,7 @@ module gaussian_conv_unq12 N61_6 ( .COUT (), .Z (N61[5]), - .CIN (_N13930), + .CIN (_N14157), .I0 (), .I1 (), .I2 (), @@ -59020,7 +58669,7 @@ module gaussian_conv_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N64_1 ( - .COUT (_N13951), + .COUT (_N14170), .Z (N64[0]), .CIN (), .I0 (\mat[2][2] [0] ), @@ -59040,9 +58689,9 @@ module gaussian_conv_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N64_2 ( - .COUT (_N13952), + .COUT (_N14171), .Z (N64[1]), - .CIN (_N13951), + .CIN (_N14170), .I0 (\mat[2][2] [0] ), .I1 (\mat[2][0] [0] ), .I2 (\mat[2][2] [1] ), @@ -59060,9 +58709,9 @@ module gaussian_conv_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N64_3 ( - .COUT (_N13953), + .COUT (_N14172), .Z (N64[2]), - .CIN (_N13952), + .CIN (_N14171), .I0 (), .I1 (\mat[2][2] [2] ), .I2 (\mat[2][0] [2] ), @@ -59080,9 +58729,9 @@ module gaussian_conv_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N64_4 ( - .COUT (_N13954), + .COUT (_N14173), .Z (N64[3]), - .CIN (_N13953), + .CIN (_N14172), .I0 (), .I1 (\mat[2][2] [3] ), .I2 (\mat[2][0] [3] ), @@ -59100,9 +58749,9 @@ module gaussian_conv_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N64_5 ( - .COUT (_N13955), + .COUT (_N14174), .Z (N64[4]), - .CIN (_N13954), + .CIN (_N14173), .I0 (), .I1 (\mat[2][2] [4] ), .I2 (\mat[2][0] [4] ), @@ -59122,7 +58771,7 @@ module gaussian_conv_unq12 N64_6 ( .COUT (), .Z (N64[5]), - .CIN (_N13955), + .CIN (_N14174), .I0 (), .I1 (), .I2 (), @@ -59140,7 +58789,7 @@ module gaussian_conv_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_1 ( - .COUT (_N13978), + .COUT (_N14190), .Z (N69[0]), .CIN (), .I0 (\mat[1][0] [0] ), @@ -59160,9 +58809,9 @@ module gaussian_conv_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_2 ( - .COUT (_N13979), + .COUT (_N14191), .Z (N69[1]), - .CIN (_N13978), + .CIN (_N14190), .I0 (\mat[1][0] [0] ), .I1 (\mat[0][1] [0] ), .I2 (\mat[1][0] [1] ), @@ -59180,9 +58829,9 @@ module gaussian_conv_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_3 ( - .COUT (_N13980), + .COUT (_N14192), .Z (N69[2]), - .CIN (_N13979), + .CIN (_N14191), .I0 (), .I1 (\mat[1][0] [2] ), .I2 (\mat[0][1] [2] ), @@ -59200,9 +58849,9 @@ module gaussian_conv_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_4 ( - .COUT (_N13981), + .COUT (_N14193), .Z (N69[3]), - .CIN (_N13980), + .CIN (_N14192), .I0 (), .I1 (\mat[1][0] [3] ), .I2 (\mat[0][1] [3] ), @@ -59220,9 +58869,9 @@ module gaussian_conv_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_5 ( - .COUT (_N13982), + .COUT (_N14194), .Z (N69[4]), - .CIN (_N13981), + .CIN (_N14193), .I0 (), .I1 (\mat[1][0] [4] ), .I2 (\mat[0][1] [4] ), @@ -59242,7 +58891,7 @@ module gaussian_conv_unq12 N69_6 ( .COUT (), .Z (N69[5]), - .CIN (_N13982), + .CIN (_N14194), .I0 (), .I1 (), .I2 (), @@ -59260,7 +58909,7 @@ module gaussian_conv_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N72_1 ( - .COUT (_N13985), + .COUT (_N14197), .Z (N72[0]), .CIN (), .I0 (\mat[2][1] [0] ), @@ -59280,9 +58929,9 @@ module gaussian_conv_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N72_2 ( - .COUT (_N13986), + .COUT (_N14198), .Z (N72[1]), - .CIN (_N13985), + .CIN (_N14197), .I0 (\mat[2][1] [0] ), .I1 (\mat[1][2] [0] ), .I2 (\mat[2][1] [1] ), @@ -59300,9 +58949,9 @@ module gaussian_conv_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N72_3 ( - .COUT (_N13987), + .COUT (_N14199), .Z (N72[2]), - .CIN (_N13986), + .CIN (_N14198), .I0 (), .I1 (\mat[2][1] [2] ), .I2 (\mat[1][2] [2] ), @@ -59320,9 +58969,9 @@ module gaussian_conv_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N72_4 ( - .COUT (_N13988), + .COUT (_N14200), .Z (N72[3]), - .CIN (_N13987), + .CIN (_N14199), .I0 (), .I1 (\mat[2][1] [3] ), .I2 (\mat[1][2] [3] ), @@ -59340,9 +58989,9 @@ module gaussian_conv_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N72_5 ( - .COUT (_N13989), + .COUT (_N14201), .Z (N72[4]), - .CIN (_N13988), + .CIN (_N14200), .I0 (), .I1 (\mat[2][1] [4] ), .I2 (\mat[1][2] [4] ), @@ -59362,7 +59011,7 @@ module gaussian_conv_unq12 N72_6 ( .COUT (), .Z (N72[5]), - .CIN (_N13989), + .CIN (_N14201), .I0 (), .I1 (), .I2 (), @@ -60182,9 +59831,9 @@ module sort_3_unq34 wire [4:0] N68; wire [4:0] N73; wire _N17834; - wire _N17838; - wire _N17842; - wire _N96726; + wire _N20403; + wire _N20407; + wire _N97062; GTP_LUT5CARRY /* \N4.lt_0 */ #( .INIT(32'b00100000111100100000000000000000), @@ -60450,7 +60099,7 @@ module sort_3_unq34 GTP_LUT4 /* N55_9 */ #( .INIT(16'b1100101010101010)) N55_9 ( - .Z (_N96726), + .Z (_N97062), .I0 (N4), .I1 (N5), .I2 (N8), @@ -60462,7 +60111,7 @@ module sort_3_unq34 \N55_18[0] ( .Z (N55[0]), .I0 (_N17834), - .I1 (_N96726), + .I1 (_N97062), .I2 (original_data[10]), .I3 (original_data[5]), .I4 (original_data[0])); @@ -60473,7 +60122,7 @@ module sort_3_unq34 \N55_18[1] ( .Z (N55[1]), .I0 (_N17834), - .I1 (_N96726), + .I1 (_N97062), .I2 (original_data[11]), .I3 (original_data[6]), .I4 (original_data[1])); @@ -60484,7 +60133,7 @@ module sort_3_unq34 \N55_18[2] ( .Z (N55[2]), .I0 (_N17834), - .I1 (_N96726), + .I1 (_N97062), .I2 (original_data[12]), .I3 (original_data[7]), .I4 (original_data[2])); @@ -60495,7 +60144,7 @@ module sort_3_unq34 \N55_18[3] ( .Z (N55[3]), .I0 (_N17834), - .I1 (_N96726), + .I1 (_N97062), .I2 (original_data[13]), .I3 (original_data[8]), .I4 (original_data[3])); @@ -60506,88 +60155,86 @@ module sort_3_unq34 \N55_18[4] ( .Z (N55[4]), .I0 (_N17834), - .I1 (_N96726), + .I1 (_N97062), .I2 (original_data[14]), .I3 (original_data[9]), .I4 (original_data[4])); // LUT = (I0&I3)|(~I0&~I1&I4)|(~I0&I1&I2) ; - GTP_LUT4 /* N68_1 */ #( - .INIT(16'b0100001000100010)) - N68_1 ( - .Z (_N17838), + GTP_LUT4 /* N68_10_1 */ #( + .INIT(16'b0011100000001000)) + N68_10_1 ( + .Z (_N20403), .I0 (N4), .I1 (N5), .I2 (N8), .I3 (N15)); - // LUT = (I0&~I1&~I3)|(I0&~I1&~I2)|(~I0&I1&I2&I3) ; - // ../../sources/designs/image_filiter/sort_3.v:23 + // LUT = (I0&I1&~I2)|(~I1&I2&I3) ; - GTP_LUT4 /* N68_7 */ #( - .INIT(16'b0011100000001000)) - N68_7 ( - .Z (_N17842), + GTP_LUT4 /* N68_14_1 */ #( + .INIT(16'b0100001000100010)) + N68_14_1 ( + .Z (_N20407), .I0 (N4), .I1 (N5), .I2 (N8), .I3 (N15)); - // LUT = (I0&I1&~I2)|(~I1&I2&I3) ; - // ../../sources/designs/image_filiter/sort_3.v:23 + // LUT = (I0&~I1&~I3)|(I0&~I1&~I2)|(~I0&I1&I2&I3) ; GTP_LUT5 /* \N68_17[0] */ #( - .INIT(32'b11110011111000101101000111000000)) + .INIT(32'b11110101111001001011000110100000)) \N68_17[0] ( .Z (N68[0]), - .I0 (_N17838), - .I1 (_N17842), + .I0 (_N20403), + .I1 (_N20407), .I2 (original_data[10]), .I3 (original_data[5]), .I4 (original_data[0])); - // LUT = (I1&I2)|(~I0&~I1&I3)|(I0&~I1&I4) ; + // LUT = (I0&I2)|(~I0&~I1&I3)|(~I0&I1&I4) ; GTP_LUT5 /* \N68_17[1] */ #( - .INIT(32'b11110011111000101101000111000000)) + .INIT(32'b11110101111001001011000110100000)) \N68_17[1] ( .Z (N68[1]), - .I0 (_N17838), - .I1 (_N17842), + .I0 (_N20403), + .I1 (_N20407), .I2 (original_data[11]), .I3 (original_data[6]), .I4 (original_data[1])); - // LUT = (I1&I2)|(~I0&~I1&I3)|(I0&~I1&I4) ; + // LUT = (I0&I2)|(~I0&~I1&I3)|(~I0&I1&I4) ; GTP_LUT5 /* \N68_17[2] */ #( - .INIT(32'b11110011111000101101000111000000)) + .INIT(32'b11110101111001001011000110100000)) \N68_17[2] ( .Z (N68[2]), - .I0 (_N17838), - .I1 (_N17842), + .I0 (_N20403), + .I1 (_N20407), .I2 (original_data[12]), .I3 (original_data[7]), .I4 (original_data[2])); - // LUT = (I1&I2)|(~I0&~I1&I3)|(I0&~I1&I4) ; + // LUT = (I0&I2)|(~I0&~I1&I3)|(~I0&I1&I4) ; GTP_LUT5 /* \N68_17[3] */ #( - .INIT(32'b11110011111000101101000111000000)) + .INIT(32'b11110101111001001011000110100000)) \N68_17[3] ( .Z (N68[3]), - .I0 (_N17838), - .I1 (_N17842), + .I0 (_N20403), + .I1 (_N20407), .I2 (original_data[13]), .I3 (original_data[8]), .I4 (original_data[3])); - // LUT = (I1&I2)|(~I0&~I1&I3)|(I0&~I1&I4) ; + // LUT = (I0&I2)|(~I0&~I1&I3)|(~I0&I1&I4) ; GTP_LUT5 /* \N68_17[4] */ #( - .INIT(32'b11110011111000101101000111000000)) + .INIT(32'b11110101111001001011000110100000)) \N68_17[4] ( .Z (N68[4]), - .I0 (_N17838), - .I1 (_N17842), + .I0 (_N20403), + .I1 (_N20407), .I2 (original_data[14]), .I3 (original_data[9]), .I4 (original_data[4])); - // LUT = (I1&I2)|(~I0&~I1&I3)|(I0&~I1&I4) ; + // LUT = (I0&I2)|(~I0&~I1&I3)|(~I0&I1&I4) ; GTP_LUT5M /* \N73_6[0] */ #( .INIT(32'b11101010001010101110101000101010)) @@ -60822,10 +60469,10 @@ module sort_3_unq36 wire [4:0] N55; wire [4:0] N68; wire [4:0] N73; - wire _N20135; - wire _N20385; - wire _N20389; - wire _N95949; + wire _N22295; + wire _N22919; + wire _N22923; + wire _N96729; GTP_LUT5CARRY /* \N4.lt_0 */ #( .INIT(32'b00100000111100100000000000000000), @@ -61080,7 +60727,7 @@ module sort_3_unq36 GTP_LUT4 /* N55_9 */ #( .INIT(16'b1100101010101010)) N55_9 ( - .Z (_N95949), + .Z (_N96729), .I0 (N4), .I1 (N5), .I2 (N8), @@ -61090,7 +60737,7 @@ module sort_3_unq36 GTP_LUT4 /* N55_11_1 */ #( .INIT(16'b0000101000101010)) N55_11_1 ( - .Z (_N20135), + .Z (_N22295), .I0 (N4), .I1 (N5), .I2 (N8), @@ -61101,8 +60748,8 @@ module sort_3_unq36 .INIT(32'b11111011010100011110101001000000)) \N55_18[0] ( .Z (N55[0]), - .I0 (_N20135), - .I1 (_N95949), + .I0 (_N22295), + .I1 (_N96729), .I2 (original_data[10]), .I3 (original_data[5]), .I4 (original_data[0])); @@ -61112,8 +60759,8 @@ module sort_3_unq36 .INIT(32'b11111011010100011110101001000000)) \N55_18[1] ( .Z (N55[1]), - .I0 (_N20135), - .I1 (_N95949), + .I0 (_N22295), + .I1 (_N96729), .I2 (original_data[11]), .I3 (original_data[6]), .I4 (original_data[1])); @@ -61123,8 +60770,8 @@ module sort_3_unq36 .INIT(32'b11111011010100011110101001000000)) \N55_18[2] ( .Z (N55[2]), - .I0 (_N20135), - .I1 (_N95949), + .I0 (_N22295), + .I1 (_N96729), .I2 (original_data[12]), .I3 (original_data[7]), .I4 (original_data[2])); @@ -61134,8 +60781,8 @@ module sort_3_unq36 .INIT(32'b11111011010100011110101001000000)) \N55_18[3] ( .Z (N55[3]), - .I0 (_N20135), - .I1 (_N95949), + .I0 (_N22295), + .I1 (_N96729), .I2 (original_data[13]), .I3 (original_data[8]), .I4 (original_data[3])); @@ -61145,8 +60792,8 @@ module sort_3_unq36 .INIT(32'b11111011010100011110101001000000)) \N55_18[4] ( .Z (N55[4]), - .I0 (_N20135), - .I1 (_N95949), + .I0 (_N22295), + .I1 (_N96729), .I2 (original_data[14]), .I3 (original_data[9]), .I4 (original_data[4])); @@ -61155,7 +60802,7 @@ module sort_3_unq36 GTP_LUT4 /* N68_10_1 */ #( .INIT(16'b0011100000001000)) N68_10_1 ( - .Z (_N20385), + .Z (_N22919), .I0 (N4), .I1 (N5), .I2 (N8), @@ -61165,7 +60812,7 @@ module sort_3_unq36 GTP_LUT4 /* N68_14_1 */ #( .INIT(16'b0100001000100010)) N68_14_1 ( - .Z (_N20389), + .Z (_N22923), .I0 (N4), .I1 (N5), .I2 (N8), @@ -61176,8 +60823,8 @@ module sort_3_unq36 .INIT(32'b11110101111001001011000110100000)) \N68_17[0] ( .Z (N68[0]), - .I0 (_N20385), - .I1 (_N20389), + .I0 (_N22919), + .I1 (_N22923), .I2 (original_data[10]), .I3 (original_data[5]), .I4 (original_data[0])); @@ -61187,8 +60834,8 @@ module sort_3_unq36 .INIT(32'b11110101111001001011000110100000)) \N68_17[1] ( .Z (N68[1]), - .I0 (_N20385), - .I1 (_N20389), + .I0 (_N22919), + .I1 (_N22923), .I2 (original_data[11]), .I3 (original_data[6]), .I4 (original_data[1])); @@ -61198,8 +60845,8 @@ module sort_3_unq36 .INIT(32'b11110101111001001011000110100000)) \N68_17[2] ( .Z (N68[2]), - .I0 (_N20385), - .I1 (_N20389), + .I0 (_N22919), + .I1 (_N22923), .I2 (original_data[12]), .I3 (original_data[7]), .I4 (original_data[2])); @@ -61209,8 +60856,8 @@ module sort_3_unq36 .INIT(32'b11110101111001001011000110100000)) \N68_17[3] ( .Z (N68[3]), - .I0 (_N20385), - .I1 (_N20389), + .I0 (_N22919), + .I1 (_N22923), .I2 (original_data[13]), .I3 (original_data[8]), .I4 (original_data[3])); @@ -61220,8 +60867,8 @@ module sort_3_unq36 .INIT(32'b11110101111001001011000110100000)) \N68_17[4] ( .Z (N68[4]), - .I0 (_N20385), - .I1 (_N20389), + .I0 (_N22919), + .I1 (_N22923), .I2 (original_data[14]), .I3 (original_data[9]), .I4 (original_data[4])); @@ -61460,10 +61107,10 @@ module sort_3_unq38 wire [4:0] N55; wire [4:0] N68; wire [4:0] N73; - wire _N22487; - wire _N23706; - wire _N23710; - wire _N96423; + wire _N23680; + wire _N23727; + wire _N23731; + wire _N97185; GTP_LUT5CARRY /* \N4.lt_0 */ #( .INIT(32'b00100000111100100000000000000000), @@ -61718,7 +61365,7 @@ module sort_3_unq38 GTP_LUT4 /* N55_9 */ #( .INIT(16'b1100101010101010)) N55_9 ( - .Z (_N96423), + .Z (_N97185), .I0 (N4), .I1 (N5), .I2 (N8), @@ -61728,7 +61375,7 @@ module sort_3_unq38 GTP_LUT4 /* N55_11_1 */ #( .INIT(16'b0000101000101010)) N55_11_1 ( - .Z (_N22487), + .Z (_N23680), .I0 (N4), .I1 (N5), .I2 (N8), @@ -61739,8 +61386,8 @@ module sort_3_unq38 .INIT(32'b11111011010100011110101001000000)) \N55_18[0] ( .Z (N55[0]), - .I0 (_N22487), - .I1 (_N96423), + .I0 (_N23680), + .I1 (_N97185), .I2 (original_data[10]), .I3 (original_data[5]), .I4 (original_data[0])); @@ -61750,8 +61397,8 @@ module sort_3_unq38 .INIT(32'b11111011010100011110101001000000)) \N55_18[1] ( .Z (N55[1]), - .I0 (_N22487), - .I1 (_N96423), + .I0 (_N23680), + .I1 (_N97185), .I2 (original_data[11]), .I3 (original_data[6]), .I4 (original_data[1])); @@ -61761,8 +61408,8 @@ module sort_3_unq38 .INIT(32'b11111011010100011110101001000000)) \N55_18[2] ( .Z (N55[2]), - .I0 (_N22487), - .I1 (_N96423), + .I0 (_N23680), + .I1 (_N97185), .I2 (original_data[12]), .I3 (original_data[7]), .I4 (original_data[2])); @@ -61772,8 +61419,8 @@ module sort_3_unq38 .INIT(32'b11111011010100011110101001000000)) \N55_18[3] ( .Z (N55[3]), - .I0 (_N22487), - .I1 (_N96423), + .I0 (_N23680), + .I1 (_N97185), .I2 (original_data[13]), .I3 (original_data[8]), .I4 (original_data[3])); @@ -61783,8 +61430,8 @@ module sort_3_unq38 .INIT(32'b11111011010100011110101001000000)) \N55_18[4] ( .Z (N55[4]), - .I0 (_N22487), - .I1 (_N96423), + .I0 (_N23680), + .I1 (_N97185), .I2 (original_data[14]), .I3 (original_data[9]), .I4 (original_data[4])); @@ -61793,7 +61440,7 @@ module sort_3_unq38 GTP_LUT4 /* N68_10_1 */ #( .INIT(16'b0011100000001000)) N68_10_1 ( - .Z (_N23706), + .Z (_N23727), .I0 (N4), .I1 (N5), .I2 (N8), @@ -61803,7 +61450,7 @@ module sort_3_unq38 GTP_LUT4 /* N68_14_1 */ #( .INIT(16'b0100001000100010)) N68_14_1 ( - .Z (_N23710), + .Z (_N23731), .I0 (N4), .I1 (N5), .I2 (N8), @@ -61814,8 +61461,8 @@ module sort_3_unq38 .INIT(32'b11110101111001001011000110100000)) \N68_17[0] ( .Z (N68[0]), - .I0 (_N23706), - .I1 (_N23710), + .I0 (_N23727), + .I1 (_N23731), .I2 (original_data[10]), .I3 (original_data[5]), .I4 (original_data[0])); @@ -61825,8 +61472,8 @@ module sort_3_unq38 .INIT(32'b11110101111001001011000110100000)) \N68_17[1] ( .Z (N68[1]), - .I0 (_N23706), - .I1 (_N23710), + .I0 (_N23727), + .I1 (_N23731), .I2 (original_data[11]), .I3 (original_data[6]), .I4 (original_data[1])); @@ -61836,8 +61483,8 @@ module sort_3_unq38 .INIT(32'b11110101111001001011000110100000)) \N68_17[2] ( .Z (N68[2]), - .I0 (_N23706), - .I1 (_N23710), + .I0 (_N23727), + .I1 (_N23731), .I2 (original_data[12]), .I3 (original_data[7]), .I4 (original_data[2])); @@ -61847,8 +61494,8 @@ module sort_3_unq38 .INIT(32'b11110101111001001011000110100000)) \N68_17[3] ( .Z (N68[3]), - .I0 (_N23706), - .I1 (_N23710), + .I0 (_N23727), + .I1 (_N23731), .I2 (original_data[13]), .I3 (original_data[8]), .I4 (original_data[3])); @@ -61858,8 +61505,8 @@ module sort_3_unq38 .INIT(32'b11110101111001001011000110100000)) \N68_17[4] ( .Z (N68[4]), - .I0 (_N23706), - .I1 (_N23710), + .I0 (_N23727), + .I1 (_N23731), .I2 (original_data[14]), .I3 (original_data[9]), .I4 (original_data[4])); @@ -62126,8 +61773,8 @@ module median_finder9_unq10 wire N167; wire [5:0] \N167.co ; wire [4:0] N188; - wire _N102885_1; - wire _N102892_1; + wire _N103061_1; + wire _N103110_1; wire [4:0] max_of_vector_max; wire [4:0] max_of_vector_min; wire [4:0] med_of_vector_med; @@ -62631,7 +62278,7 @@ module median_finder9_unq10 .I1 (\vector_med[1] [0] ), .I2 (N83), .I3 (N87), - .I4 (_N102892_1), + .I4 (_N103061_1), .ID (\vector_med[2] [0] )); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; @@ -62643,7 +62290,7 @@ module median_finder9_unq10 .I1 (\vector_med[1] [1] ), .I2 (N83), .I3 (N87), - .I4 (_N102892_1), + .I4 (_N103061_1), .ID (\vector_med[2] [1] )); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; @@ -62655,7 +62302,7 @@ module median_finder9_unq10 .I1 (\vector_med[1] [2] ), .I2 (N83), .I3 (N87), - .I4 (_N102892_1), + .I4 (_N103061_1), .ID (\vector_med[2] [2] )); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; @@ -62667,7 +62314,7 @@ module median_finder9_unq10 .I1 (\vector_med[1] [3] ), .I2 (N83), .I3 (N87), - .I4 (_N102892_1), + .I4 (_N103061_1), .ID (\vector_med[2] [3] )); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; @@ -62679,14 +62326,14 @@ module median_finder9_unq10 .I1 (\vector_med[1] [4] ), .I2 (N83), .I3 (N87), - .I4 (_N102892_1), + .I4 (_N103061_1), .ID (\vector_med[2] [4] )); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; GTP_LUT3 /* N104_40 */ #( .INIT(8'b11100111)) N104_40 ( - .Z (_N102892_1), + .Z (_N103061_1), .I0 (N83), .I1 (N85), .I2 (N87)); @@ -63180,7 +62827,7 @@ module median_finder9_unq10 .I1 (med_of_vector_med[0]), .I2 (N155), .I3 (N167), - .I4 (_N102885_1), + .I4 (_N103110_1), .ID (min_of_vector_max[0])); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; @@ -63192,7 +62839,7 @@ module median_finder9_unq10 .I1 (med_of_vector_med[1]), .I2 (N155), .I3 (N167), - .I4 (_N102885_1), + .I4 (_N103110_1), .ID (min_of_vector_max[1])); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; @@ -63204,7 +62851,7 @@ module median_finder9_unq10 .I1 (med_of_vector_med[2]), .I2 (N155), .I3 (N167), - .I4 (_N102885_1), + .I4 (_N103110_1), .ID (min_of_vector_max[2])); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; @@ -63216,7 +62863,7 @@ module median_finder9_unq10 .I1 (med_of_vector_med[3]), .I2 (N155), .I3 (N167), - .I4 (_N102885_1), + .I4 (_N103110_1), .ID (min_of_vector_max[3])); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; @@ -63228,14 +62875,14 @@ module median_finder9_unq10 .I1 (med_of_vector_med[4]), .I2 (N155), .I3 (N167), - .I4 (_N102885_1), + .I4 (_N103110_1), .ID (min_of_vector_max[4])); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; GTP_LUT3 /* N188_40 */ #( .INIT(8'b11100111)) N188_40 ( - .Z (_N102885_1), + .Z (_N103110_1), .I0 (N155), .I1 (N161), .I2 (N167)); @@ -63685,10 +63332,10 @@ module sort_3_1_unq16 wire [5:0] N55; wire [5:0] N68; wire [5:0] N73; - wire _N23686; - wire _N23724; - wire _N23728; - wire _N96433; + wire _N17885; + wire _N20250; + wire _N20254; + wire _N97194; GTP_LUT5CARRY /* \N4.lt_0 */ #( .INIT(32'b00100000111100100000000000000000), @@ -63940,32 +63587,33 @@ module sort_3_1_unq16 // LUT = I0&I1 ; // ../../sources/designs/image_filiter/sort_3.v:38 - GTP_LUT4 /* N55_9 */ #( - .INIT(16'b1100101010101010)) - N55_9 ( - .Z (_N96433), + GTP_LUT4 /* N55_7 */ #( + .INIT(16'b0000101000101010)) + N55_7 ( + .Z (_N17885), .I0 (N4), .I1 (N5), .I2 (N8), .I3 (N15)); - // LUT = (I0&~I3)|(I0&~I2)|(I1&I2&I3) ; + // LUT = (I0&~I2)|(I0&~I1&~I3) ; + // ../../sources/designs/image_filiter/sort_3.v:23 - GTP_LUT4 /* N55_11_1 */ #( - .INIT(16'b0000101000101010)) - N55_11_1 ( - .Z (_N23686), + GTP_LUT4 /* N55_9 */ #( + .INIT(16'b1100101010101010)) + N55_9 ( + .Z (_N97194), .I0 (N4), .I1 (N5), .I2 (N8), .I3 (N15)); - // LUT = (I0&~I2)|(I0&~I1&~I3) ; + // LUT = (I0&~I3)|(I0&~I2)|(I1&I2&I3) ; GTP_LUT5 /* \N55_18[0] */ #( .INIT(32'b11111011010100011110101001000000)) \N55_18[0] ( .Z (N55[0]), - .I0 (_N23686), - .I1 (_N96433), + .I0 (_N17885), + .I1 (_N97194), .I2 (original_data[12]), .I3 (original_data[6]), .I4 (original_data[0])); @@ -63975,8 +63623,8 @@ module sort_3_1_unq16 .INIT(32'b11111011010100011110101001000000)) \N55_18[1] ( .Z (N55[1]), - .I0 (_N23686), - .I1 (_N96433), + .I0 (_N17885), + .I1 (_N97194), .I2 (original_data[13]), .I3 (original_data[7]), .I4 (original_data[1])); @@ -63986,8 +63634,8 @@ module sort_3_1_unq16 .INIT(32'b11111011010100011110101001000000)) \N55_18[2] ( .Z (N55[2]), - .I0 (_N23686), - .I1 (_N96433), + .I0 (_N17885), + .I1 (_N97194), .I2 (original_data[14]), .I3 (original_data[8]), .I4 (original_data[2])); @@ -63997,8 +63645,8 @@ module sort_3_1_unq16 .INIT(32'b11111011010100011110101001000000)) \N55_18[3] ( .Z (N55[3]), - .I0 (_N23686), - .I1 (_N96433), + .I0 (_N17885), + .I1 (_N97194), .I2 (original_data[15]), .I3 (original_data[9]), .I4 (original_data[3])); @@ -64008,8 +63656,8 @@ module sort_3_1_unq16 .INIT(32'b11111011010100011110101001000000)) \N55_18[4] ( .Z (N55[4]), - .I0 (_N23686), - .I1 (_N96433), + .I0 (_N17885), + .I1 (_N97194), .I2 (original_data[16]), .I3 (original_data[10]), .I4 (original_data[4])); @@ -64019,8 +63667,8 @@ module sort_3_1_unq16 .INIT(32'b11111011010100011110101001000000)) \N55_18[5] ( .Z (N55[5]), - .I0 (_N23686), - .I1 (_N96433), + .I0 (_N17885), + .I1 (_N97194), .I2 (original_data[17]), .I3 (original_data[11]), .I4 (original_data[5])); @@ -64029,7 +63677,7 @@ module sort_3_1_unq16 GTP_LUT4 /* N68_10_1 */ #( .INIT(16'b0011100000001000)) N68_10_1 ( - .Z (_N23724), + .Z (_N20250), .I0 (N4), .I1 (N5), .I2 (N8), @@ -64039,7 +63687,7 @@ module sort_3_1_unq16 GTP_LUT4 /* N68_14_1 */ #( .INIT(16'b0100001000100010)) N68_14_1 ( - .Z (_N23728), + .Z (_N20254), .I0 (N4), .I1 (N5), .I2 (N8), @@ -64050,8 +63698,8 @@ module sort_3_1_unq16 .INIT(32'b11110101111001001011000110100000)) \N68_17[0] ( .Z (N68[0]), - .I0 (_N23724), - .I1 (_N23728), + .I0 (_N20250), + .I1 (_N20254), .I2 (original_data[12]), .I3 (original_data[6]), .I4 (original_data[0])); @@ -64061,8 +63709,8 @@ module sort_3_1_unq16 .INIT(32'b11110101111001001011000110100000)) \N68_17[1] ( .Z (N68[1]), - .I0 (_N23724), - .I1 (_N23728), + .I0 (_N20250), + .I1 (_N20254), .I2 (original_data[13]), .I3 (original_data[7]), .I4 (original_data[1])); @@ -64072,8 +63720,8 @@ module sort_3_1_unq16 .INIT(32'b11110101111001001011000110100000)) \N68_17[2] ( .Z (N68[2]), - .I0 (_N23724), - .I1 (_N23728), + .I0 (_N20250), + .I1 (_N20254), .I2 (original_data[14]), .I3 (original_data[8]), .I4 (original_data[2])); @@ -64083,8 +63731,8 @@ module sort_3_1_unq16 .INIT(32'b11110101111001001011000110100000)) \N68_17[3] ( .Z (N68[3]), - .I0 (_N23724), - .I1 (_N23728), + .I0 (_N20250), + .I1 (_N20254), .I2 (original_data[15]), .I3 (original_data[9]), .I4 (original_data[3])); @@ -64094,8 +63742,8 @@ module sort_3_1_unq16 .INIT(32'b11110101111001001011000110100000)) \N68_17[4] ( .Z (N68[4]), - .I0 (_N23724), - .I1 (_N23728), + .I0 (_N20250), + .I1 (_N20254), .I2 (original_data[16]), .I3 (original_data[10]), .I4 (original_data[4])); @@ -64105,8 +63753,8 @@ module sort_3_1_unq16 .INIT(32'b11110101111001001011000110100000)) \N68_17[5] ( .Z (N68[5]), - .I0 (_N23724), - .I1 (_N23728), + .I0 (_N20250), + .I1 (_N20254), .I2 (original_data[17]), .I3 (original_data[11]), .I4 (original_data[5])); @@ -64387,10 +64035,10 @@ module sort_3_1_unq18 wire [5:0] N55; wire [5:0] N68; wire [5:0] N73; - wire _N20051; - wire _N20097; - wire _N20101; - wire _N95826; + wire _N20942; + wire _N25569; + wire _N25573; + wire _N96605; GTP_LUT5CARRY /* \N4.lt_0 */ #( .INIT(32'b00100000111100100000000000000000), @@ -64645,7 +64293,7 @@ module sort_3_1_unq18 GTP_LUT4 /* N55_9 */ #( .INIT(16'b1100101010101010)) N55_9 ( - .Z (_N95826), + .Z (_N96605), .I0 (N4), .I1 (N5), .I2 (N8), @@ -64655,7 +64303,7 @@ module sort_3_1_unq18 GTP_LUT4 /* N55_11_1 */ #( .INIT(16'b0000101000101010)) N55_11_1 ( - .Z (_N20051), + .Z (_N20942), .I0 (N4), .I1 (N5), .I2 (N8), @@ -64666,8 +64314,8 @@ module sort_3_1_unq18 .INIT(32'b11111011010100011110101001000000)) \N55_18[0] ( .Z (N55[0]), - .I0 (_N20051), - .I1 (_N95826), + .I0 (_N20942), + .I1 (_N96605), .I2 (original_data[12]), .I3 (original_data[6]), .I4 (original_data[0])); @@ -64677,8 +64325,8 @@ module sort_3_1_unq18 .INIT(32'b11111011010100011110101001000000)) \N55_18[1] ( .Z (N55[1]), - .I0 (_N20051), - .I1 (_N95826), + .I0 (_N20942), + .I1 (_N96605), .I2 (original_data[13]), .I3 (original_data[7]), .I4 (original_data[1])); @@ -64688,8 +64336,8 @@ module sort_3_1_unq18 .INIT(32'b11111011010100011110101001000000)) \N55_18[2] ( .Z (N55[2]), - .I0 (_N20051), - .I1 (_N95826), + .I0 (_N20942), + .I1 (_N96605), .I2 (original_data[14]), .I3 (original_data[8]), .I4 (original_data[2])); @@ -64699,8 +64347,8 @@ module sort_3_1_unq18 .INIT(32'b11111011010100011110101001000000)) \N55_18[3] ( .Z (N55[3]), - .I0 (_N20051), - .I1 (_N95826), + .I0 (_N20942), + .I1 (_N96605), .I2 (original_data[15]), .I3 (original_data[9]), .I4 (original_data[3])); @@ -64710,8 +64358,8 @@ module sort_3_1_unq18 .INIT(32'b11111011010100011110101001000000)) \N55_18[4] ( .Z (N55[4]), - .I0 (_N20051), - .I1 (_N95826), + .I0 (_N20942), + .I1 (_N96605), .I2 (original_data[16]), .I3 (original_data[10]), .I4 (original_data[4])); @@ -64721,8 +64369,8 @@ module sort_3_1_unq18 .INIT(32'b11111011010100011110101001000000)) \N55_18[5] ( .Z (N55[5]), - .I0 (_N20051), - .I1 (_N95826), + .I0 (_N20942), + .I1 (_N96605), .I2 (original_data[17]), .I3 (original_data[11]), .I4 (original_data[5])); @@ -64731,7 +64379,7 @@ module sort_3_1_unq18 GTP_LUT4 /* N68_10_1 */ #( .INIT(16'b0011100000001000)) N68_10_1 ( - .Z (_N20097), + .Z (_N25569), .I0 (N4), .I1 (N5), .I2 (N8), @@ -64741,7 +64389,7 @@ module sort_3_1_unq18 GTP_LUT4 /* N68_14_1 */ #( .INIT(16'b0100001000100010)) N68_14_1 ( - .Z (_N20101), + .Z (_N25573), .I0 (N4), .I1 (N5), .I2 (N8), @@ -64752,8 +64400,8 @@ module sort_3_1_unq18 .INIT(32'b11110101111001001011000110100000)) \N68_17[0] ( .Z (N68[0]), - .I0 (_N20097), - .I1 (_N20101), + .I0 (_N25569), + .I1 (_N25573), .I2 (original_data[12]), .I3 (original_data[6]), .I4 (original_data[0])); @@ -64763,8 +64411,8 @@ module sort_3_1_unq18 .INIT(32'b11110101111001001011000110100000)) \N68_17[1] ( .Z (N68[1]), - .I0 (_N20097), - .I1 (_N20101), + .I0 (_N25569), + .I1 (_N25573), .I2 (original_data[13]), .I3 (original_data[7]), .I4 (original_data[1])); @@ -64774,8 +64422,8 @@ module sort_3_1_unq18 .INIT(32'b11110101111001001011000110100000)) \N68_17[2] ( .Z (N68[2]), - .I0 (_N20097), - .I1 (_N20101), + .I0 (_N25569), + .I1 (_N25573), .I2 (original_data[14]), .I3 (original_data[8]), .I4 (original_data[2])); @@ -64785,8 +64433,8 @@ module sort_3_1_unq18 .INIT(32'b11110101111001001011000110100000)) \N68_17[3] ( .Z (N68[3]), - .I0 (_N20097), - .I1 (_N20101), + .I0 (_N25569), + .I1 (_N25573), .I2 (original_data[15]), .I3 (original_data[9]), .I4 (original_data[3])); @@ -64796,8 +64444,8 @@ module sort_3_1_unq18 .INIT(32'b11110101111001001011000110100000)) \N68_17[4] ( .Z (N68[4]), - .I0 (_N20097), - .I1 (_N20101), + .I0 (_N25569), + .I1 (_N25573), .I2 (original_data[16]), .I3 (original_data[10]), .I4 (original_data[4])); @@ -64807,8 +64455,8 @@ module sort_3_1_unq18 .INIT(32'b11110101111001001011000110100000)) \N68_17[5] ( .Z (N68[5]), - .I0 (_N20097), - .I1 (_N20101), + .I0 (_N25569), + .I1 (_N25573), .I2 (original_data[17]), .I3 (original_data[11]), .I4 (original_data[5])); @@ -65089,10 +64737,10 @@ module sort_3_1_unq20 wire [5:0] N55; wire [5:0] N68; wire [5:0] N73; - wire _N20794; - wire _N25634; - wire _N25638; - wire _N95820; + wire _N25589; + wire _N25609; + wire _N25613; + wire _N96597; GTP_LUT5CARRY /* \N4.lt_0 */ #( .INIT(32'b00100000111100100000000000000000), @@ -65347,7 +64995,7 @@ module sort_3_1_unq20 GTP_LUT4 /* N55_9 */ #( .INIT(16'b1100101010101010)) N55_9 ( - .Z (_N95820), + .Z (_N96597), .I0 (N4), .I1 (N5), .I2 (N8), @@ -65357,7 +65005,7 @@ module sort_3_1_unq20 GTP_LUT4 /* N55_11_1 */ #( .INIT(16'b0000101000101010)) N55_11_1 ( - .Z (_N20794), + .Z (_N25589), .I0 (N4), .I1 (N5), .I2 (N8), @@ -65368,8 +65016,8 @@ module sort_3_1_unq20 .INIT(32'b11111011010100011110101001000000)) \N55_18[0] ( .Z (N55[0]), - .I0 (_N20794), - .I1 (_N95820), + .I0 (_N25589), + .I1 (_N96597), .I2 (original_data[12]), .I3 (original_data[6]), .I4 (original_data[0])); @@ -65379,8 +65027,8 @@ module sort_3_1_unq20 .INIT(32'b11111011010100011110101001000000)) \N55_18[1] ( .Z (N55[1]), - .I0 (_N20794), - .I1 (_N95820), + .I0 (_N25589), + .I1 (_N96597), .I2 (original_data[13]), .I3 (original_data[7]), .I4 (original_data[1])); @@ -65390,8 +65038,8 @@ module sort_3_1_unq20 .INIT(32'b11111011010100011110101001000000)) \N55_18[2] ( .Z (N55[2]), - .I0 (_N20794), - .I1 (_N95820), + .I0 (_N25589), + .I1 (_N96597), .I2 (original_data[14]), .I3 (original_data[8]), .I4 (original_data[2])); @@ -65401,8 +65049,8 @@ module sort_3_1_unq20 .INIT(32'b11111011010100011110101001000000)) \N55_18[3] ( .Z (N55[3]), - .I0 (_N20794), - .I1 (_N95820), + .I0 (_N25589), + .I1 (_N96597), .I2 (original_data[15]), .I3 (original_data[9]), .I4 (original_data[3])); @@ -65412,8 +65060,8 @@ module sort_3_1_unq20 .INIT(32'b11111011010100011110101001000000)) \N55_18[4] ( .Z (N55[4]), - .I0 (_N20794), - .I1 (_N95820), + .I0 (_N25589), + .I1 (_N96597), .I2 (original_data[16]), .I3 (original_data[10]), .I4 (original_data[4])); @@ -65423,8 +65071,8 @@ module sort_3_1_unq20 .INIT(32'b11111011010100011110101001000000)) \N55_18[5] ( .Z (N55[5]), - .I0 (_N20794), - .I1 (_N95820), + .I0 (_N25589), + .I1 (_N96597), .I2 (original_data[17]), .I3 (original_data[11]), .I4 (original_data[5])); @@ -65433,7 +65081,7 @@ module sort_3_1_unq20 GTP_LUT4 /* N68_10_1 */ #( .INIT(16'b0011100000001000)) N68_10_1 ( - .Z (_N25634), + .Z (_N25609), .I0 (N4), .I1 (N5), .I2 (N8), @@ -65443,7 +65091,7 @@ module sort_3_1_unq20 GTP_LUT4 /* N68_14_1 */ #( .INIT(16'b0100001000100010)) N68_14_1 ( - .Z (_N25638), + .Z (_N25613), .I0 (N4), .I1 (N5), .I2 (N8), @@ -65454,8 +65102,8 @@ module sort_3_1_unq20 .INIT(32'b11110101111001001011000110100000)) \N68_17[0] ( .Z (N68[0]), - .I0 (_N25634), - .I1 (_N25638), + .I0 (_N25609), + .I1 (_N25613), .I2 (original_data[12]), .I3 (original_data[6]), .I4 (original_data[0])); @@ -65465,8 +65113,8 @@ module sort_3_1_unq20 .INIT(32'b11110101111001001011000110100000)) \N68_17[1] ( .Z (N68[1]), - .I0 (_N25634), - .I1 (_N25638), + .I0 (_N25609), + .I1 (_N25613), .I2 (original_data[13]), .I3 (original_data[7]), .I4 (original_data[1])); @@ -65476,8 +65124,8 @@ module sort_3_1_unq20 .INIT(32'b11110101111001001011000110100000)) \N68_17[2] ( .Z (N68[2]), - .I0 (_N25634), - .I1 (_N25638), + .I0 (_N25609), + .I1 (_N25613), .I2 (original_data[14]), .I3 (original_data[8]), .I4 (original_data[2])); @@ -65487,8 +65135,8 @@ module sort_3_1_unq20 .INIT(32'b11110101111001001011000110100000)) \N68_17[3] ( .Z (N68[3]), - .I0 (_N25634), - .I1 (_N25638), + .I0 (_N25609), + .I1 (_N25613), .I2 (original_data[15]), .I3 (original_data[9]), .I4 (original_data[3])); @@ -65498,8 +65146,8 @@ module sort_3_1_unq20 .INIT(32'b11110101111001001011000110100000)) \N68_17[4] ( .Z (N68[4]), - .I0 (_N25634), - .I1 (_N25638), + .I0 (_N25609), + .I1 (_N25613), .I2 (original_data[16]), .I3 (original_data[10]), .I4 (original_data[4])); @@ -65509,8 +65157,8 @@ module sort_3_1_unq20 .INIT(32'b11110101111001001011000110100000)) \N68_17[5] ( .Z (N68[5]), - .I0 (_N25634), - .I1 (_N25638), + .I0 (_N25609), + .I1 (_N25613), .I2 (original_data[17]), .I3 (original_data[11]), .I4 (original_data[5])); @@ -65819,8 +65467,8 @@ module median_finder9_1_unq4 wire N167; wire [6:0] \N167.co ; wire [5:0] N188; - wire _N102196_1; - wire _N102877_1; + wire _N103708_1; + wire _N103710_1; wire [5:0] max_of_vector_max; wire [5:0] max_of_vector_min; wire [5:0] med_of_vector_med; @@ -66348,7 +65996,7 @@ module median_finder9_1_unq4 .I1 (N87), .I2 (\vector_med[1] [0] ), .I3 (N83), - .I4 (_N102196_1), + .I4 (_N103708_1), .ID (\vector_med[2] [0] )); // LUT = (ID&I1&~I3&~I4)|(ID&~I1&I3&~I4)|(I0&I1&~I3&I4)|(I0&~I1&I3&I4)|(~I1&I2&~I3)|(I1&I2&I3) ; @@ -66360,7 +66008,7 @@ module median_finder9_1_unq4 .I1 (N87), .I2 (\vector_med[1] [1] ), .I3 (N83), - .I4 (_N102196_1), + .I4 (_N103708_1), .ID (\vector_med[2] [1] )); // LUT = (ID&I1&~I3&~I4)|(ID&~I1&I3&~I4)|(I0&I1&~I3&I4)|(I0&~I1&I3&I4)|(~I1&I2&~I3)|(I1&I2&I3) ; @@ -66372,7 +66020,7 @@ module median_finder9_1_unq4 .I1 (N87), .I2 (\vector_med[1] [2] ), .I3 (N83), - .I4 (_N102196_1), + .I4 (_N103708_1), .ID (\vector_med[2] [2] )); // LUT = (ID&I1&~I3&~I4)|(ID&~I1&I3&~I4)|(I0&I1&~I3&I4)|(I0&~I1&I3&I4)|(~I1&I2&~I3)|(I1&I2&I3) ; @@ -66384,7 +66032,7 @@ module median_finder9_1_unq4 .I1 (N87), .I2 (\vector_med[1] [3] ), .I3 (N83), - .I4 (_N102196_1), + .I4 (_N103708_1), .ID (\vector_med[2] [3] )); // LUT = (ID&I1&~I3&~I4)|(ID&~I1&I3&~I4)|(I0&I1&~I3&I4)|(I0&~I1&I3&I4)|(~I1&I2&~I3)|(I1&I2&I3) ; @@ -66396,7 +66044,7 @@ module median_finder9_1_unq4 .I1 (N87), .I2 (\vector_med[1] [4] ), .I3 (N83), - .I4 (_N102196_1), + .I4 (_N103708_1), .ID (\vector_med[2] [4] )); // LUT = (ID&I1&~I3&~I4)|(ID&~I1&I3&~I4)|(I0&I1&~I3&I4)|(I0&~I1&I3&I4)|(~I1&I2&~I3)|(I1&I2&I3) ; @@ -66408,14 +66056,14 @@ module median_finder9_1_unq4 .I1 (N87), .I2 (\vector_med[1] [5] ), .I3 (N83), - .I4 (_N102196_1), + .I4 (_N103708_1), .ID (\vector_med[2] [5] )); // LUT = (ID&I1&~I3&~I4)|(ID&~I1&I3&~I4)|(I0&I1&~I3&I4)|(I0&~I1&I3&I4)|(~I1&I2&~I3)|(I1&I2&I3) ; GTP_LUT3 /* N104_40 */ #( .INIT(8'b11100111)) N104_40 ( - .Z (_N102196_1), + .Z (_N103708_1), .I0 (N83), .I1 (N85), .I2 (N87)); @@ -66933,7 +66581,7 @@ module median_finder9_1_unq4 .I1 (N167), .I2 (med_of_vector_med[0]), .I3 (N155), - .I4 (_N102877_1), + .I4 (_N103710_1), .ID (min_of_vector_max[0])); // LUT = (ID&I1&~I3&~I4)|(ID&~I1&I3&~I4)|(I0&I1&~I3&I4)|(I0&~I1&I3&I4)|(~I1&I2&~I3)|(I1&I2&I3) ; @@ -66945,7 +66593,7 @@ module median_finder9_1_unq4 .I1 (N167), .I2 (med_of_vector_med[1]), .I3 (N155), - .I4 (_N102877_1), + .I4 (_N103710_1), .ID (min_of_vector_max[1])); // LUT = (ID&I1&~I3&~I4)|(ID&~I1&I3&~I4)|(I0&I1&~I3&I4)|(I0&~I1&I3&I4)|(~I1&I2&~I3)|(I1&I2&I3) ; @@ -66957,7 +66605,7 @@ module median_finder9_1_unq4 .I1 (N167), .I2 (med_of_vector_med[2]), .I3 (N155), - .I4 (_N102877_1), + .I4 (_N103710_1), .ID (min_of_vector_max[2])); // LUT = (ID&I1&~I3&~I4)|(ID&~I1&I3&~I4)|(I0&I1&~I3&I4)|(I0&~I1&I3&I4)|(~I1&I2&~I3)|(I1&I2&I3) ; @@ -66969,7 +66617,7 @@ module median_finder9_1_unq4 .I1 (N167), .I2 (med_of_vector_med[3]), .I3 (N155), - .I4 (_N102877_1), + .I4 (_N103710_1), .ID (min_of_vector_max[3])); // LUT = (ID&I1&~I3&~I4)|(ID&~I1&I3&~I4)|(I0&I1&~I3&I4)|(I0&~I1&I3&I4)|(~I1&I2&~I3)|(I1&I2&I3) ; @@ -66981,7 +66629,7 @@ module median_finder9_1_unq4 .I1 (N167), .I2 (med_of_vector_med[4]), .I3 (N155), - .I4 (_N102877_1), + .I4 (_N103710_1), .ID (min_of_vector_max[4])); // LUT = (ID&I1&~I3&~I4)|(ID&~I1&I3&~I4)|(I0&I1&~I3&I4)|(I0&~I1&I3&I4)|(~I1&I2&~I3)|(I1&I2&I3) ; @@ -66993,14 +66641,14 @@ module median_finder9_1_unq4 .I1 (N167), .I2 (med_of_vector_med[5]), .I3 (N155), - .I4 (_N102877_1), + .I4 (_N103710_1), .ID (min_of_vector_max[5])); // LUT = (ID&I1&~I3&~I4)|(ID&~I1&I3&~I4)|(I0&I1&~I3&I4)|(I0&~I1&I3&I4)|(~I1&I2&~I3)|(I1&I2&I3) ; GTP_LUT3 /* N188_40 */ #( .INIT(8'b11100111)) N188_40 ( - .Z (_N102877_1), + .Z (_N103710_1), .I0 (N155), .I1 (N161), .I2 (N167)); @@ -67530,10 +67178,10 @@ module sort_3_unq40 wire [4:0] N55; wire [4:0] N68; wire [4:0] N73; - wire _N17944; - wire _N25797; - wire _N25819; - wire _N95911; + wire _N25752; + wire _N26026; + wire _N26030; + wire _N96725; GTP_LUT5CARRY /* \N4.lt_0 */ #( .INIT(32'b00100000111100100000000000000000), @@ -67788,7 +67436,7 @@ module sort_3_unq40 GTP_LUT4 /* N55_9 */ #( .INIT(16'b1100101010101010)) N55_9 ( - .Z (_N95911), + .Z (_N96725), .I0 (N4), .I1 (N5), .I2 (N8), @@ -67798,7 +67446,7 @@ module sort_3_unq40 GTP_LUT4 /* N55_11_1 */ #( .INIT(16'b0000101000101010)) N55_11_1 ( - .Z (_N25797), + .Z (_N25752), .I0 (N4), .I1 (N5), .I2 (N8), @@ -67809,8 +67457,8 @@ module sort_3_unq40 .INIT(32'b11111011010100011110101001000000)) \N55_18[0] ( .Z (N55[0]), - .I0 (_N25797), - .I1 (_N95911), + .I0 (_N25752), + .I1 (_N96725), .I2 (original_data[10]), .I3 (original_data[5]), .I4 (original_data[0])); @@ -67820,8 +67468,8 @@ module sort_3_unq40 .INIT(32'b11111011010100011110101001000000)) \N55_18[1] ( .Z (N55[1]), - .I0 (_N25797), - .I1 (_N95911), + .I0 (_N25752), + .I1 (_N96725), .I2 (original_data[11]), .I3 (original_data[6]), .I4 (original_data[1])); @@ -67831,8 +67479,8 @@ module sort_3_unq40 .INIT(32'b11111011010100011110101001000000)) \N55_18[2] ( .Z (N55[2]), - .I0 (_N25797), - .I1 (_N95911), + .I0 (_N25752), + .I1 (_N96725), .I2 (original_data[12]), .I3 (original_data[7]), .I4 (original_data[2])); @@ -67842,8 +67490,8 @@ module sort_3_unq40 .INIT(32'b11111011010100011110101001000000)) \N55_18[3] ( .Z (N55[3]), - .I0 (_N25797), - .I1 (_N95911), + .I0 (_N25752), + .I1 (_N96725), .I2 (original_data[13]), .I3 (original_data[8]), .I4 (original_data[3])); @@ -67853,28 +67501,27 @@ module sort_3_unq40 .INIT(32'b11111011010100011110101001000000)) \N55_18[4] ( .Z (N55[4]), - .I0 (_N25797), - .I1 (_N95911), + .I0 (_N25752), + .I1 (_N96725), .I2 (original_data[14]), .I3 (original_data[9]), .I4 (original_data[4])); // LUT = (I0&I3)|(~I0&~I1&I4)|(~I0&I1&I2) ; - GTP_LUT4 /* N68_7 */ #( + GTP_LUT4 /* N68_10_1 */ #( .INIT(16'b0011100000001000)) - N68_7 ( - .Z (_N17944), + N68_10_1 ( + .Z (_N26026), .I0 (N4), .I1 (N5), .I2 (N8), .I3 (N15)); // LUT = (I0&I1&~I2)|(~I1&I2&I3) ; - // ../../sources/designs/image_filiter/sort_3.v:23 GTP_LUT4 /* N68_14_1 */ #( .INIT(16'b0100001000100010)) N68_14_1 ( - .Z (_N25819), + .Z (_N26030), .I0 (N4), .I1 (N5), .I2 (N8), @@ -67885,8 +67532,8 @@ module sort_3_unq40 .INIT(32'b11110101111001001011000110100000)) \N68_17[0] ( .Z (N68[0]), - .I0 (_N17944), - .I1 (_N25819), + .I0 (_N26026), + .I1 (_N26030), .I2 (original_data[10]), .I3 (original_data[5]), .I4 (original_data[0])); @@ -67896,8 +67543,8 @@ module sort_3_unq40 .INIT(32'b11110101111001001011000110100000)) \N68_17[1] ( .Z (N68[1]), - .I0 (_N17944), - .I1 (_N25819), + .I0 (_N26026), + .I1 (_N26030), .I2 (original_data[11]), .I3 (original_data[6]), .I4 (original_data[1])); @@ -67907,8 +67554,8 @@ module sort_3_unq40 .INIT(32'b11110101111001001011000110100000)) \N68_17[2] ( .Z (N68[2]), - .I0 (_N17944), - .I1 (_N25819), + .I0 (_N26026), + .I1 (_N26030), .I2 (original_data[12]), .I3 (original_data[7]), .I4 (original_data[2])); @@ -67918,8 +67565,8 @@ module sort_3_unq40 .INIT(32'b11110101111001001011000110100000)) \N68_17[3] ( .Z (N68[3]), - .I0 (_N17944), - .I1 (_N25819), + .I0 (_N26026), + .I1 (_N26030), .I2 (original_data[13]), .I3 (original_data[8]), .I4 (original_data[3])); @@ -67929,8 +67576,8 @@ module sort_3_unq40 .INIT(32'b11110101111001001011000110100000)) \N68_17[4] ( .Z (N68[4]), - .I0 (_N17944), - .I1 (_N25819), + .I0 (_N26026), + .I1 (_N26030), .I2 (original_data[14]), .I3 (original_data[9]), .I4 (original_data[4])); @@ -68169,10 +67816,10 @@ module sort_3_unq42 wire [4:0] N55; wire [4:0] N68; wire [4:0] N73; - wire _N22385; - wire _N22389; - wire _N26062; - wire _N95967; + wire _N17953; + wire _N17961; + wire _N25211; + wire _N96760; GTP_LUT5CARRY /* \N4.lt_0 */ #( .INIT(32'b00100000111100100000000000000000), @@ -68424,32 +68071,33 @@ module sort_3_unq42 // LUT = I0&I1 ; // ../../sources/designs/image_filiter/sort_3.v:38 - GTP_LUT4 /* N55_9 */ #( - .INIT(16'b1100101010101010)) - N55_9 ( - .Z (_N95967), + GTP_LUT4 /* N55_7 */ #( + .INIT(16'b0000101000101010)) + N55_7 ( + .Z (_N17953), .I0 (N4), .I1 (N5), .I2 (N8), .I3 (N15)); - // LUT = (I0&~I3)|(I0&~I2)|(I1&I2&I3) ; + // LUT = (I0&~I2)|(I0&~I1&~I3) ; + // ../../sources/designs/image_filiter/sort_3.v:23 - GTP_LUT4 /* N55_11_1 */ #( - .INIT(16'b0000101000101010)) - N55_11_1 ( - .Z (_N26062), + GTP_LUT4 /* N55_9 */ #( + .INIT(16'b1100101010101010)) + N55_9 ( + .Z (_N96760), .I0 (N4), .I1 (N5), .I2 (N8), .I3 (N15)); - // LUT = (I0&~I2)|(I0&~I1&~I3) ; + // LUT = (I0&~I3)|(I0&~I2)|(I1&I2&I3) ; GTP_LUT5 /* \N55_18[0] */ #( .INIT(32'b11111011010100011110101001000000)) \N55_18[0] ( .Z (N55[0]), - .I0 (_N26062), - .I1 (_N95967), + .I0 (_N17953), + .I1 (_N96760), .I2 (original_data[10]), .I3 (original_data[5]), .I4 (original_data[0])); @@ -68459,8 +68107,8 @@ module sort_3_unq42 .INIT(32'b11111011010100011110101001000000)) \N55_18[1] ( .Z (N55[1]), - .I0 (_N26062), - .I1 (_N95967), + .I0 (_N17953), + .I1 (_N96760), .I2 (original_data[11]), .I3 (original_data[6]), .I4 (original_data[1])); @@ -68470,8 +68118,8 @@ module sort_3_unq42 .INIT(32'b11111011010100011110101001000000)) \N55_18[2] ( .Z (N55[2]), - .I0 (_N26062), - .I1 (_N95967), + .I0 (_N17953), + .I1 (_N96760), .I2 (original_data[12]), .I3 (original_data[7]), .I4 (original_data[2])); @@ -68481,8 +68129,8 @@ module sort_3_unq42 .INIT(32'b11111011010100011110101001000000)) \N55_18[3] ( .Z (N55[3]), - .I0 (_N26062), - .I1 (_N95967), + .I0 (_N17953), + .I1 (_N96760), .I2 (original_data[13]), .I3 (original_data[8]), .I4 (original_data[3])); @@ -68492,27 +68140,28 @@ module sort_3_unq42 .INIT(32'b11111011010100011110101001000000)) \N55_18[4] ( .Z (N55[4]), - .I0 (_N26062), - .I1 (_N95967), + .I0 (_N17953), + .I1 (_N96760), .I2 (original_data[14]), .I3 (original_data[9]), .I4 (original_data[4])); // LUT = (I0&I3)|(~I0&~I1&I4)|(~I0&I1&I2) ; - GTP_LUT4 /* N68_10_1 */ #( + GTP_LUT4 /* N68_7 */ #( .INIT(16'b0011100000001000)) - N68_10_1 ( - .Z (_N22385), + N68_7 ( + .Z (_N17961), .I0 (N4), .I1 (N5), .I2 (N8), .I3 (N15)); // LUT = (I0&I1&~I2)|(~I1&I2&I3) ; + // ../../sources/designs/image_filiter/sort_3.v:23 GTP_LUT4 /* N68_14_1 */ #( .INIT(16'b0100001000100010)) N68_14_1 ( - .Z (_N22389), + .Z (_N25211), .I0 (N4), .I1 (N5), .I2 (N8), @@ -68523,8 +68172,8 @@ module sort_3_unq42 .INIT(32'b11110101111001001011000110100000)) \N68_17[0] ( .Z (N68[0]), - .I0 (_N22385), - .I1 (_N22389), + .I0 (_N17961), + .I1 (_N25211), .I2 (original_data[10]), .I3 (original_data[5]), .I4 (original_data[0])); @@ -68534,8 +68183,8 @@ module sort_3_unq42 .INIT(32'b11110101111001001011000110100000)) \N68_17[1] ( .Z (N68[1]), - .I0 (_N22385), - .I1 (_N22389), + .I0 (_N17961), + .I1 (_N25211), .I2 (original_data[11]), .I3 (original_data[6]), .I4 (original_data[1])); @@ -68545,8 +68194,8 @@ module sort_3_unq42 .INIT(32'b11110101111001001011000110100000)) \N68_17[2] ( .Z (N68[2]), - .I0 (_N22385), - .I1 (_N22389), + .I0 (_N17961), + .I1 (_N25211), .I2 (original_data[12]), .I3 (original_data[7]), .I4 (original_data[2])); @@ -68556,8 +68205,8 @@ module sort_3_unq42 .INIT(32'b11110101111001001011000110100000)) \N68_17[3] ( .Z (N68[3]), - .I0 (_N22385), - .I1 (_N22389), + .I0 (_N17961), + .I1 (_N25211), .I2 (original_data[13]), .I3 (original_data[8]), .I4 (original_data[3])); @@ -68567,8 +68216,8 @@ module sort_3_unq42 .INIT(32'b11110101111001001011000110100000)) \N68_17[4] ( .Z (N68[4]), - .I0 (_N22385), - .I1 (_N22389), + .I0 (_N17961), + .I1 (_N25211), .I2 (original_data[14]), .I3 (original_data[9]), .I4 (original_data[4])); @@ -68807,10 +68456,10 @@ module sort_3_unq44 wire [4:0] N55; wire [4:0] N68; wire [4:0] N73; - wire _N20433; - wire _N20437; - wire _N25357; - wire _N95892; + wire _N20027; + wire _N20031; + wire _N25461; + wire _N96724; GTP_LUT5CARRY /* \N4.lt_0 */ #( .INIT(32'b00100000111100100000000000000000), @@ -69065,7 +68714,7 @@ module sort_3_unq44 GTP_LUT4 /* N55_9 */ #( .INIT(16'b1100101010101010)) N55_9 ( - .Z (_N95892), + .Z (_N96724), .I0 (N4), .I1 (N5), .I2 (N8), @@ -69075,7 +68724,7 @@ module sort_3_unq44 GTP_LUT4 /* N55_11_1 */ #( .INIT(16'b0000101000101010)) N55_11_1 ( - .Z (_N25357), + .Z (_N25461), .I0 (N4), .I1 (N5), .I2 (N8), @@ -69086,8 +68735,8 @@ module sort_3_unq44 .INIT(32'b11111011010100011110101001000000)) \N55_18[0] ( .Z (N55[0]), - .I0 (_N25357), - .I1 (_N95892), + .I0 (_N25461), + .I1 (_N96724), .I2 (original_data[10]), .I3 (original_data[5]), .I4 (original_data[0])); @@ -69097,8 +68746,8 @@ module sort_3_unq44 .INIT(32'b11111011010100011110101001000000)) \N55_18[1] ( .Z (N55[1]), - .I0 (_N25357), - .I1 (_N95892), + .I0 (_N25461), + .I1 (_N96724), .I2 (original_data[11]), .I3 (original_data[6]), .I4 (original_data[1])); @@ -69108,8 +68757,8 @@ module sort_3_unq44 .INIT(32'b11111011010100011110101001000000)) \N55_18[2] ( .Z (N55[2]), - .I0 (_N25357), - .I1 (_N95892), + .I0 (_N25461), + .I1 (_N96724), .I2 (original_data[12]), .I3 (original_data[7]), .I4 (original_data[2])); @@ -69119,8 +68768,8 @@ module sort_3_unq44 .INIT(32'b11111011010100011110101001000000)) \N55_18[3] ( .Z (N55[3]), - .I0 (_N25357), - .I1 (_N95892), + .I0 (_N25461), + .I1 (_N96724), .I2 (original_data[13]), .I3 (original_data[8]), .I4 (original_data[3])); @@ -69130,8 +68779,8 @@ module sort_3_unq44 .INIT(32'b11111011010100011110101001000000)) \N55_18[4] ( .Z (N55[4]), - .I0 (_N25357), - .I1 (_N95892), + .I0 (_N25461), + .I1 (_N96724), .I2 (original_data[14]), .I3 (original_data[9]), .I4 (original_data[4])); @@ -69140,7 +68789,7 @@ module sort_3_unq44 GTP_LUT4 /* N68_10_1 */ #( .INIT(16'b0011100000001000)) N68_10_1 ( - .Z (_N20433), + .Z (_N20027), .I0 (N4), .I1 (N5), .I2 (N8), @@ -69150,7 +68799,7 @@ module sort_3_unq44 GTP_LUT4 /* N68_14_1 */ #( .INIT(16'b0100001000100010)) N68_14_1 ( - .Z (_N20437), + .Z (_N20031), .I0 (N4), .I1 (N5), .I2 (N8), @@ -69161,8 +68810,8 @@ module sort_3_unq44 .INIT(32'b11110101111001001011000110100000)) \N68_17[0] ( .Z (N68[0]), - .I0 (_N20433), - .I1 (_N20437), + .I0 (_N20027), + .I1 (_N20031), .I2 (original_data[10]), .I3 (original_data[5]), .I4 (original_data[0])); @@ -69172,8 +68821,8 @@ module sort_3_unq44 .INIT(32'b11110101111001001011000110100000)) \N68_17[1] ( .Z (N68[1]), - .I0 (_N20433), - .I1 (_N20437), + .I0 (_N20027), + .I1 (_N20031), .I2 (original_data[11]), .I3 (original_data[6]), .I4 (original_data[1])); @@ -69183,8 +68832,8 @@ module sort_3_unq44 .INIT(32'b11110101111001001011000110100000)) \N68_17[2] ( .Z (N68[2]), - .I0 (_N20433), - .I1 (_N20437), + .I0 (_N20027), + .I1 (_N20031), .I2 (original_data[12]), .I3 (original_data[7]), .I4 (original_data[2])); @@ -69194,8 +68843,8 @@ module sort_3_unq44 .INIT(32'b11110101111001001011000110100000)) \N68_17[3] ( .Z (N68[3]), - .I0 (_N20433), - .I1 (_N20437), + .I0 (_N20027), + .I1 (_N20031), .I2 (original_data[13]), .I3 (original_data[8]), .I4 (original_data[3])); @@ -69205,8 +68854,8 @@ module sort_3_unq44 .INIT(32'b11110101111001001011000110100000)) \N68_17[4] ( .Z (N68[4]), - .I0 (_N20433), - .I1 (_N20437), + .I0 (_N20027), + .I1 (_N20031), .I2 (original_data[14]), .I3 (original_data[9]), .I4 (original_data[4])); @@ -69473,8 +69122,8 @@ module median_finder9_unq12 wire N167; wire [5:0] \N167.co ; wire [4:0] N188; - wire _N102782_1; - wire _N102783_1; + wire _N103574_1; + wire _N103576_1; wire [4:0] max_of_vector_max; wire [4:0] max_of_vector_min; wire [4:0] med_of_vector_med; @@ -69671,124 +69320,124 @@ module median_finder9_unq12 // ../../sources/designs/image_filiter/median_finder9.v:84 GTP_LUT5M /* \N56_4[0] */ #( - .INIT(32'b11111010010100001110111001000100)) + .INIT(32'b11011000110110001101110110001000)) \N56_4[0] ( .Z (N56[0]), .I0 (N35), - .I1 (\vector_min[2] [0] ), + .I1 (\vector_min[0] [0] ), .I2 (\vector_min[1] [0] ), - .I3 (\vector_min[0] [0] ), + .I3 (\vector_min[2] [0] ), .I4 (N39), .ID (N37)); - // LUT = (ID&I3&~I4)|(~ID&I1&~I4)|(I0&I3&I4)|(~I0&I2&I4) ; + // LUT = (~ID&I3&~I4)|(ID&I1&~I4)|(~I0&I2&I4)|(I0&I1&I4) ; GTP_LUT5M /* \N56_4[1] */ #( - .INIT(32'b11111010010100001110111001000100)) + .INIT(32'b11011000110110001101110110001000)) \N56_4[1] ( .Z (N56[1]), .I0 (N35), - .I1 (\vector_min[2] [1] ), + .I1 (\vector_min[0] [1] ), .I2 (\vector_min[1] [1] ), - .I3 (\vector_min[0] [1] ), + .I3 (\vector_min[2] [1] ), .I4 (N39), .ID (N37)); - // LUT = (ID&I3&~I4)|(~ID&I1&~I4)|(I0&I3&I4)|(~I0&I2&I4) ; + // LUT = (~ID&I3&~I4)|(ID&I1&~I4)|(~I0&I2&I4)|(I0&I1&I4) ; GTP_LUT5M /* \N56_4[2] */ #( - .INIT(32'b11111010010100001110111001000100)) + .INIT(32'b11011000110110001101110110001000)) \N56_4[2] ( .Z (N56[2]), .I0 (N35), - .I1 (\vector_min[2] [2] ), + .I1 (\vector_min[0] [2] ), .I2 (\vector_min[1] [2] ), - .I3 (\vector_min[0] [2] ), + .I3 (\vector_min[2] [2] ), .I4 (N39), .ID (N37)); - // LUT = (ID&I3&~I4)|(~ID&I1&~I4)|(I0&I3&I4)|(~I0&I2&I4) ; + // LUT = (~ID&I3&~I4)|(ID&I1&~I4)|(~I0&I2&I4)|(I0&I1&I4) ; GTP_LUT5M /* \N56_4[3] */ #( - .INIT(32'b11111010010100001110111001000100)) + .INIT(32'b11011000110110001101110110001000)) \N56_4[3] ( .Z (N56[3]), .I0 (N35), - .I1 (\vector_min[2] [3] ), + .I1 (\vector_min[0] [3] ), .I2 (\vector_min[1] [3] ), - .I3 (\vector_min[0] [3] ), + .I3 (\vector_min[2] [3] ), .I4 (N39), .ID (N37)); - // LUT = (ID&I3&~I4)|(~ID&I1&~I4)|(I0&I3&I4)|(~I0&I2&I4) ; + // LUT = (~ID&I3&~I4)|(ID&I1&~I4)|(~I0&I2&I4)|(I0&I1&I4) ; GTP_LUT5M /* \N56_4[4] */ #( - .INIT(32'b11111010010100001110111001000100)) + .INIT(32'b11011000110110001101110110001000)) \N56_4[4] ( .Z (N56[4]), .I0 (N35), - .I1 (\vector_min[2] [4] ), + .I1 (\vector_min[0] [4] ), .I2 (\vector_min[1] [4] ), - .I3 (\vector_min[0] [4] ), + .I3 (\vector_min[2] [4] ), .I4 (N39), .ID (N37)); - // LUT = (ID&I3&~I4)|(~ID&I1&~I4)|(I0&I3&I4)|(~I0&I2&I4) ; + // LUT = (~ID&I3&~I4)|(ID&I1&~I4)|(~I0&I2&I4)|(I0&I1&I4) ; GTP_LUT5M /* \N80_4[0] */ #( - .INIT(32'b11110101101000001101110110001000)) + .INIT(32'b11101110010001001110010011100100)) \N80_4[0] ( .Z (N80[0]), .I0 (N37), - .I1 (\vector_min[1] [0] ), - .I2 (\vector_min[2] [0] ), - .I3 (\vector_min[0] [0] ), + .I1 (\vector_min[0] [0] ), + .I2 (\vector_min[1] [0] ), + .I3 (\vector_min[2] [0] ), .I4 (N39), .ID (N35)); - // LUT = (~ID&I3&~I4)|(ID&I1&~I4)|(~I0&I3&I4)|(I0&I2&I4) ; + // LUT = (ID&I2&~I4)|(~ID&I1&~I4)|(I0&I3&I4)|(~I0&I1&I4) ; GTP_LUT5M /* \N80_4[1] */ #( - .INIT(32'b11110101101000001101110110001000)) + .INIT(32'b11101110010001001110010011100100)) \N80_4[1] ( .Z (N80[1]), .I0 (N37), - .I1 (\vector_min[1] [1] ), - .I2 (\vector_min[2] [1] ), - .I3 (\vector_min[0] [1] ), + .I1 (\vector_min[0] [1] ), + .I2 (\vector_min[1] [1] ), + .I3 (\vector_min[2] [1] ), .I4 (N39), .ID (N35)); - // LUT = (~ID&I3&~I4)|(ID&I1&~I4)|(~I0&I3&I4)|(I0&I2&I4) ; + // LUT = (ID&I2&~I4)|(~ID&I1&~I4)|(I0&I3&I4)|(~I0&I1&I4) ; GTP_LUT5M /* \N80_4[2] */ #( - .INIT(32'b11110101101000001101110110001000)) + .INIT(32'b11101110010001001110010011100100)) \N80_4[2] ( .Z (N80[2]), .I0 (N37), - .I1 (\vector_min[1] [2] ), - .I2 (\vector_min[2] [2] ), - .I3 (\vector_min[0] [2] ), + .I1 (\vector_min[0] [2] ), + .I2 (\vector_min[1] [2] ), + .I3 (\vector_min[2] [2] ), .I4 (N39), .ID (N35)); - // LUT = (~ID&I3&~I4)|(ID&I1&~I4)|(~I0&I3&I4)|(I0&I2&I4) ; + // LUT = (ID&I2&~I4)|(~ID&I1&~I4)|(I0&I3&I4)|(~I0&I1&I4) ; GTP_LUT5M /* \N80_4[3] */ #( - .INIT(32'b11110101101000001101110110001000)) + .INIT(32'b11101110010001001110010011100100)) \N80_4[3] ( .Z (N80[3]), .I0 (N37), - .I1 (\vector_min[1] [3] ), - .I2 (\vector_min[2] [3] ), - .I3 (\vector_min[0] [3] ), + .I1 (\vector_min[0] [3] ), + .I2 (\vector_min[1] [3] ), + .I3 (\vector_min[2] [3] ), .I4 (N39), .ID (N35)); - // LUT = (~ID&I3&~I4)|(ID&I1&~I4)|(~I0&I3&I4)|(I0&I2&I4) ; + // LUT = (ID&I2&~I4)|(~ID&I1&~I4)|(I0&I3&I4)|(~I0&I1&I4) ; GTP_LUT5M /* \N80_4[4] */ #( - .INIT(32'b11110101101000001101110110001000)) + .INIT(32'b11101110010001001110010011100100)) \N80_4[4] ( .Z (N80[4]), .I0 (N37), - .I1 (\vector_min[1] [4] ), - .I2 (\vector_min[2] [4] ), - .I3 (\vector_min[0] [4] ), + .I1 (\vector_min[0] [4] ), + .I2 (\vector_min[1] [4] ), + .I3 (\vector_min[2] [4] ), .I4 (N39), .ID (N35)); - // LUT = (~ID&I3&~I4)|(ID&I1&~I4)|(~I0&I3&I4)|(I0&I2&I4) ; + // LUT = (ID&I2&~I4)|(~ID&I1&~I4)|(I0&I3&I4)|(~I0&I1&I4) ; GTP_LUT5CARRY /* \N83.lt_0 */ #( .INIT(32'b00100000111100100000000000000000), @@ -69976,9 +69625,9 @@ module median_finder9_unq12 .Z (N104[0]), .I0 (\vector_med[0] [0] ), .I1 (\vector_med[1] [0] ), - .I2 (N83), - .I3 (N87), - .I4 (_N102782_1), + .I2 (N87), + .I3 (N83), + .I4 (_N103576_1), .ID (\vector_med[2] [0] )); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; @@ -69988,9 +69637,9 @@ module median_finder9_unq12 .Z (N104[1]), .I0 (\vector_med[0] [1] ), .I1 (\vector_med[1] [1] ), - .I2 (N83), - .I3 (N87), - .I4 (_N102782_1), + .I2 (N87), + .I3 (N83), + .I4 (_N103576_1), .ID (\vector_med[2] [1] )); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; @@ -70000,9 +69649,9 @@ module median_finder9_unq12 .Z (N104[2]), .I0 (\vector_med[0] [2] ), .I1 (\vector_med[1] [2] ), - .I2 (N83), - .I3 (N87), - .I4 (_N102782_1), + .I2 (N87), + .I3 (N83), + .I4 (_N103576_1), .ID (\vector_med[2] [2] )); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; @@ -70012,9 +69661,9 @@ module median_finder9_unq12 .Z (N104[3]), .I0 (\vector_med[0] [3] ), .I1 (\vector_med[1] [3] ), - .I2 (N83), - .I3 (N87), - .I4 (_N102782_1), + .I2 (N87), + .I3 (N83), + .I4 (_N103576_1), .ID (\vector_med[2] [3] )); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; @@ -70024,16 +69673,16 @@ module median_finder9_unq12 .Z (N104[4]), .I0 (\vector_med[0] [4] ), .I1 (\vector_med[1] [4] ), - .I2 (N83), - .I3 (N87), - .I4 (_N102782_1), + .I2 (N87), + .I3 (N83), + .I4 (_N103576_1), .ID (\vector_med[2] [4] )); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; GTP_LUT3 /* N104_40 */ #( .INIT(8'b11100111)) N104_40 ( - .Z (_N102782_1), + .Z (_N103576_1), .I0 (N83), .I1 (N85), .I2 (N87)); @@ -70220,124 +69869,124 @@ module median_finder9_unq12 // ../../sources/designs/image_filiter/median_finder9.v:147 GTP_LUT5M /* \N128_4[0] */ #( - .INIT(32'b11111010010100001101100011011000)) + .INIT(32'b11101110010001001110010011100100)) \N128_4[0] ( .Z (N128[0]), .I0 (N111), - .I1 (\vector_max[1] [0] ), - .I2 (\vector_max[0] [0] ), + .I1 (\vector_max[0] [0] ), + .I2 (\vector_max[1] [0] ), .I3 (\vector_max[2] [0] ), .I4 (N109), .ID (N107)); - // LUT = (~ID&I2&~I4)|(ID&I1&~I4)|(I0&I3&I4)|(~I0&I2&I4) ; + // LUT = (ID&I2&~I4)|(~ID&I1&~I4)|(I0&I3&I4)|(~I0&I1&I4) ; GTP_LUT5M /* \N128_4[1] */ #( - .INIT(32'b11111010010100001101100011011000)) + .INIT(32'b11101110010001001110010011100100)) \N128_4[1] ( .Z (N128[1]), .I0 (N111), - .I1 (\vector_max[1] [1] ), - .I2 (\vector_max[0] [1] ), + .I1 (\vector_max[0] [1] ), + .I2 (\vector_max[1] [1] ), .I3 (\vector_max[2] [1] ), .I4 (N109), .ID (N107)); - // LUT = (~ID&I2&~I4)|(ID&I1&~I4)|(I0&I3&I4)|(~I0&I2&I4) ; + // LUT = (ID&I2&~I4)|(~ID&I1&~I4)|(I0&I3&I4)|(~I0&I1&I4) ; GTP_LUT5M /* \N128_4[2] */ #( - .INIT(32'b11111010010100001101100011011000)) + .INIT(32'b11101110010001001110010011100100)) \N128_4[2] ( .Z (N128[2]), .I0 (N111), - .I1 (\vector_max[1] [2] ), - .I2 (\vector_max[0] [2] ), + .I1 (\vector_max[0] [2] ), + .I2 (\vector_max[1] [2] ), .I3 (\vector_max[2] [2] ), .I4 (N109), .ID (N107)); - // LUT = (~ID&I2&~I4)|(ID&I1&~I4)|(I0&I3&I4)|(~I0&I2&I4) ; + // LUT = (ID&I2&~I4)|(~ID&I1&~I4)|(I0&I3&I4)|(~I0&I1&I4) ; GTP_LUT5M /* \N128_4[3] */ #( - .INIT(32'b11111010010100001101100011011000)) + .INIT(32'b11101110010001001110010011100100)) \N128_4[3] ( .Z (N128[3]), .I0 (N111), - .I1 (\vector_max[1] [3] ), - .I2 (\vector_max[0] [3] ), + .I1 (\vector_max[0] [3] ), + .I2 (\vector_max[1] [3] ), .I3 (\vector_max[2] [3] ), .I4 (N109), .ID (N107)); - // LUT = (~ID&I2&~I4)|(ID&I1&~I4)|(I0&I3&I4)|(~I0&I2&I4) ; + // LUT = (ID&I2&~I4)|(~ID&I1&~I4)|(I0&I3&I4)|(~I0&I1&I4) ; GTP_LUT5M /* \N128_4[4] */ #( - .INIT(32'b11111010010100001101100011011000)) + .INIT(32'b11101110010001001110010011100100)) \N128_4[4] ( .Z (N128[4]), .I0 (N111), - .I1 (\vector_max[1] [4] ), - .I2 (\vector_max[0] [4] ), + .I1 (\vector_max[0] [4] ), + .I2 (\vector_max[1] [4] ), .I3 (\vector_max[2] [4] ), .I4 (N109), .ID (N107)); - // LUT = (~ID&I2&~I4)|(ID&I1&~I4)|(I0&I3&I4)|(~I0&I2&I4) ; + // LUT = (ID&I2&~I4)|(~ID&I1&~I4)|(I0&I3&I4)|(~I0&I1&I4) ; GTP_LUT5M /* \N152_4[0] */ #( - .INIT(32'b11110101101000001110010011100100)) + .INIT(32'b11011000110110001101110110001000)) \N152_4[0] ( .Z (N152[0]), .I0 (N107), - .I1 (\vector_max[2] [0] ), - .I2 (\vector_max[0] [0] ), - .I3 (\vector_max[1] [0] ), + .I1 (\vector_max[0] [0] ), + .I2 (\vector_max[1] [0] ), + .I3 (\vector_max[2] [0] ), .I4 (N109), .ID (N111)); - // LUT = (ID&I2&~I4)|(~ID&I1&~I4)|(~I0&I3&I4)|(I0&I2&I4) ; + // LUT = (~ID&I3&~I4)|(ID&I1&~I4)|(~I0&I2&I4)|(I0&I1&I4) ; GTP_LUT5M /* \N152_4[1] */ #( - .INIT(32'b11110101101000001110010011100100)) + .INIT(32'b11011000110110001101110110001000)) \N152_4[1] ( .Z (N152[1]), .I0 (N107), - .I1 (\vector_max[2] [1] ), - .I2 (\vector_max[0] [1] ), - .I3 (\vector_max[1] [1] ), + .I1 (\vector_max[0] [1] ), + .I2 (\vector_max[1] [1] ), + .I3 (\vector_max[2] [1] ), .I4 (N109), .ID (N111)); - // LUT = (ID&I2&~I4)|(~ID&I1&~I4)|(~I0&I3&I4)|(I0&I2&I4) ; + // LUT = (~ID&I3&~I4)|(ID&I1&~I4)|(~I0&I2&I4)|(I0&I1&I4) ; GTP_LUT5M /* \N152_4[2] */ #( - .INIT(32'b11110101101000001110010011100100)) + .INIT(32'b11011000110110001101110110001000)) \N152_4[2] ( .Z (N152[2]), .I0 (N107), - .I1 (\vector_max[2] [2] ), - .I2 (\vector_max[0] [2] ), - .I3 (\vector_max[1] [2] ), + .I1 (\vector_max[0] [2] ), + .I2 (\vector_max[1] [2] ), + .I3 (\vector_max[2] [2] ), .I4 (N109), .ID (N111)); - // LUT = (ID&I2&~I4)|(~ID&I1&~I4)|(~I0&I3&I4)|(I0&I2&I4) ; + // LUT = (~ID&I3&~I4)|(ID&I1&~I4)|(~I0&I2&I4)|(I0&I1&I4) ; GTP_LUT5M /* \N152_4[3] */ #( - .INIT(32'b11110101101000001110010011100100)) + .INIT(32'b11011000110110001101110110001000)) \N152_4[3] ( .Z (N152[3]), .I0 (N107), - .I1 (\vector_max[2] [3] ), - .I2 (\vector_max[0] [3] ), - .I3 (\vector_max[1] [3] ), + .I1 (\vector_max[0] [3] ), + .I2 (\vector_max[1] [3] ), + .I3 (\vector_max[2] [3] ), .I4 (N109), .ID (N111)); - // LUT = (ID&I2&~I4)|(~ID&I1&~I4)|(~I0&I3&I4)|(I0&I2&I4) ; + // LUT = (~ID&I3&~I4)|(ID&I1&~I4)|(~I0&I2&I4)|(I0&I1&I4) ; GTP_LUT5M /* \N152_4[4] */ #( - .INIT(32'b11110101101000001110010011100100)) + .INIT(32'b11011000110110001101110110001000)) \N152_4[4] ( .Z (N152[4]), .I0 (N107), - .I1 (\vector_max[2] [4] ), - .I2 (\vector_max[0] [4] ), - .I3 (\vector_max[1] [4] ), + .I1 (\vector_max[0] [4] ), + .I2 (\vector_max[1] [4] ), + .I3 (\vector_max[2] [4] ), .I4 (N109), .ID (N111)); - // LUT = (ID&I2&~I4)|(~ID&I1&~I4)|(~I0&I3&I4)|(I0&I2&I4) ; + // LUT = (~ID&I3&~I4)|(ID&I1&~I4)|(~I0&I2&I4)|(I0&I1&I4) ; GTP_LUT5CARRY /* \N155.lt_0 */ #( .INIT(32'b00100000111100100000000000000000), @@ -70525,9 +70174,9 @@ module median_finder9_unq12 .Z (N188[0]), .I0 (max_of_vector_min[0]), .I1 (med_of_vector_med[0]), - .I2 (N155), - .I3 (N167), - .I4 (_N102783_1), + .I2 (N167), + .I3 (N155), + .I4 (_N103574_1), .ID (min_of_vector_max[0])); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; @@ -70537,9 +70186,9 @@ module median_finder9_unq12 .Z (N188[1]), .I0 (max_of_vector_min[1]), .I1 (med_of_vector_med[1]), - .I2 (N155), - .I3 (N167), - .I4 (_N102783_1), + .I2 (N167), + .I3 (N155), + .I4 (_N103574_1), .ID (min_of_vector_max[1])); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; @@ -70549,9 +70198,9 @@ module median_finder9_unq12 .Z (N188[2]), .I0 (max_of_vector_min[2]), .I1 (med_of_vector_med[2]), - .I2 (N155), - .I3 (N167), - .I4 (_N102783_1), + .I2 (N167), + .I3 (N155), + .I4 (_N103574_1), .ID (min_of_vector_max[2])); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; @@ -70561,9 +70210,9 @@ module median_finder9_unq12 .Z (N188[3]), .I0 (max_of_vector_min[3]), .I1 (med_of_vector_med[3]), - .I2 (N155), - .I3 (N167), - .I4 (_N102783_1), + .I2 (N167), + .I3 (N155), + .I4 (_N103574_1), .ID (min_of_vector_max[3])); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; @@ -70573,16 +70222,16 @@ module median_finder9_unq12 .Z (N188[4]), .I0 (max_of_vector_min[4]), .I1 (med_of_vector_med[4]), - .I2 (N155), - .I3 (N167), - .I4 (_N102783_1), + .I2 (N167), + .I3 (N155), + .I4 (_N103574_1), .ID (min_of_vector_max[4])); // LUT = (ID&I2&~I3&~I4)|(ID&~I2&I3&~I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(I1&~I2&~I3)|(I1&I2&I3) ; GTP_LUT3 /* N188_40 */ #( .INIT(8'b11100111)) N188_40 ( - .Z (_N102783_1), + .Z (_N103574_1), .I0 (N155), .I1 (N161), .I2 (N167)); @@ -71016,17 +70665,12 @@ endmodule module hybrid_filter_unq4 ( input [2:0] mode, - input [13:0] \param_manager_inst/selected , input [143:0] s_matrix_data, input clk, - input \param_manager_inst/param_filiter1_mode/changed_up , - input \param_manager_inst/param_filiter1_mode/pressed_up , - input \param_manager_inst/param_modify_H/pluse , input rd3_rst, input s_matrix_valid, output [15:0] m_result_data, - output m_result_valid, - output \param_manager_inst/param_zoom/N142 + output m_result_valid ); wire N86; wire N90; @@ -71043,10 +70687,10 @@ module hybrid_filter_unq4 wire [4:0] N155; wire [5:0] \N155.co ; wire [4:0] N162; - wire _N20217; - wire _N20734; - wire _N23791; - wire _N23821; + wire _N20118; + wire _N21009; + wire _N22342; + wire _N22372; wire [4:0] gauss_res_b; wire [5:0] gauss_res_g; wire [4:0] gauss_res_r; @@ -71216,9 +70860,9 @@ module hybrid_filter_unq4 .Z (N106[0]), .I0 (median_res_r[0]), .I1 (gauss_res_r[0]), - .I2 (_N23821), + .I2 (_N22372), .I3 (raw_res_r[0]), - .I4 (_N23791), + .I4 (_N21009), .ID (N99[0])); // LUT = (I1&~I2&~I4)|(ID&I2&~I4)|(I2&I3&I4)|(I0&~I2&I4) ; @@ -71228,9 +70872,9 @@ module hybrid_filter_unq4 .Z (N106[1]), .I0 (median_res_r[1]), .I1 (gauss_res_r[1]), - .I2 (_N23821), + .I2 (_N22372), .I3 (raw_res_r[1]), - .I4 (_N23791), + .I4 (_N21009), .ID (N99[1])); // LUT = (I1&~I2&~I4)|(ID&I2&~I4)|(I2&I3&I4)|(I0&~I2&I4) ; @@ -71240,9 +70884,9 @@ module hybrid_filter_unq4 .Z (N106[2]), .I0 (median_res_r[2]), .I1 (gauss_res_r[2]), - .I2 (_N23821), + .I2 (_N22372), .I3 (raw_res_r[2]), - .I4 (_N23791), + .I4 (_N21009), .ID (N99[2])); // LUT = (I1&~I2&~I4)|(ID&I2&~I4)|(I2&I3&I4)|(I0&~I2&I4) ; @@ -71252,9 +70896,9 @@ module hybrid_filter_unq4 .Z (N106[3]), .I0 (median_res_r[3]), .I1 (gauss_res_r[3]), - .I2 (_N23821), + .I2 (_N22372), .I3 (raw_res_r[3]), - .I4 (_N23791), + .I4 (_N21009), .ID (N99[3])); // LUT = (I1&~I2&~I4)|(ID&I2&~I4)|(I2&I3&I4)|(I0&~I2&I4) ; @@ -71264,16 +70908,16 @@ module hybrid_filter_unq4 .Z (N106[4]), .I0 (median_res_r[4]), .I1 (gauss_res_r[4]), - .I2 (_N23821), + .I2 (_N22372), .I3 (raw_res_r[4]), - .I4 (_N23791), + .I4 (_N21009), .ID (N99[4])); // LUT = (I1&~I2&~I4)|(ID&I2&~I4)|(I2&I3&I4)|(I0&~I2&I4) ; GTP_LUT5 /* N106_72 */ #( .INIT(32'b11101101111011011110110111100101)) N106_72 ( - .Z (_N23791), + .Z (_N21009), .I0 (mode[0]), .I1 (mode[1]), .I2 (mode[2]), @@ -71281,25 +70925,6 @@ module hybrid_filter_unq4 .I4 (N90)); // LUT = (~I0&~I2)|(I0&I2)|(I1&I2)|(I1&I3)|(I1&I4) ; - GTP_LUT3 /* N106_78 */ #( - .INIT(8'b11110001)) - N106_78 ( - .Z (_N23821), - .I0 (mode[0]), - .I1 (mode[1]), - .I2 (mode[2])); - // LUT = (I2)|(~I0&~I1) ; - - GTP_LUT4 /* N106_91 */ #( - .INIT(16'b1010000010000000)) - N106_91 ( - .Z (\param_manager_inst/param_zoom/N142 ), - .I0 (\param_manager_inst/selected [2] ), - .I1 (\param_manager_inst/param_filiter1_mode/changed_up ), - .I2 (\param_manager_inst/param_filiter1_mode/pressed_up ), - .I3 (\param_manager_inst/param_modify_H/pluse )); - // LUT = (I0&I1&I2)|(I0&I2&I3) ; - GTP_LUT4 /* N114_mux5_4 */ #( .INIT(16'b1000000000000000)) N114_mux5_4 ( @@ -71446,9 +71071,9 @@ module hybrid_filter_unq4 .Z (N134[0]), .I0 (median_res_g[0]), .I1 (gauss_res_g[0]), - .I2 (_N23821), + .I2 (_N22372), .I3 (raw_res_g[0]), - .I4 (_N20217), + .I4 (_N22342), .ID (N127[0])); // LUT = (I1&~I2&~I4)|(ID&I2&~I4)|(I2&I3&I4)|(I0&~I2&I4) ; @@ -71458,9 +71083,9 @@ module hybrid_filter_unq4 .Z (N134[1]), .I0 (median_res_g[1]), .I1 (gauss_res_g[1]), - .I2 (_N23821), + .I2 (_N22372), .I3 (raw_res_g[1]), - .I4 (_N20217), + .I4 (_N22342), .ID (N127[1])); // LUT = (I1&~I2&~I4)|(ID&I2&~I4)|(I2&I3&I4)|(I0&~I2&I4) ; @@ -71470,9 +71095,9 @@ module hybrid_filter_unq4 .Z (N134[2]), .I0 (median_res_g[2]), .I1 (gauss_res_g[2]), - .I2 (_N23821), + .I2 (_N22372), .I3 (raw_res_g[2]), - .I4 (_N20217), + .I4 (_N22342), .ID (N127[2])); // LUT = (I1&~I2&~I4)|(ID&I2&~I4)|(I2&I3&I4)|(I0&~I2&I4) ; @@ -71482,9 +71107,9 @@ module hybrid_filter_unq4 .Z (N134[3]), .I0 (median_res_g[3]), .I1 (gauss_res_g[3]), - .I2 (_N23821), + .I2 (_N22372), .I3 (raw_res_g[3]), - .I4 (_N20217), + .I4 (_N22342), .ID (N127[3])); // LUT = (I1&~I2&~I4)|(ID&I2&~I4)|(I2&I3&I4)|(I0&~I2&I4) ; @@ -71494,9 +71119,9 @@ module hybrid_filter_unq4 .Z (N134[4]), .I0 (median_res_g[4]), .I1 (gauss_res_g[4]), - .I2 (_N23821), + .I2 (_N22372), .I3 (raw_res_g[4]), - .I4 (_N20217), + .I4 (_N22342), .ID (N127[4])); // LUT = (I1&~I2&~I4)|(ID&I2&~I4)|(I2&I3&I4)|(I0&~I2&I4) ; @@ -71506,16 +71131,16 @@ module hybrid_filter_unq4 .Z (N134[5]), .I0 (median_res_g[5]), .I1 (gauss_res_g[5]), - .I2 (_N23821), + .I2 (_N22372), .I3 (raw_res_g[5]), - .I4 (_N20217), + .I4 (_N22342), .ID (N127[5])); // LUT = (I1&~I2&~I4)|(ID&I2&~I4)|(I2&I3&I4)|(I0&~I2&I4) ; GTP_LUT5 /* N134_72 */ #( .INIT(32'b11101101111011011110110111100101)) N134_72 ( - .Z (_N20217), + .Z (_N22342), .I0 (mode[0]), .I1 (mode[1]), .I2 (mode[2]), @@ -71523,6 +71148,15 @@ module hybrid_filter_unq4 .I4 (N118)); // LUT = (~I0&~I2)|(I0&I2)|(I1&I2)|(I1&I3)|(I1&I4) ; + GTP_LUT3 /* N134_78 */ #( + .INIT(8'b11110001)) + N134_78 ( + .Z (_N22372), + .I0 (mode[0]), + .I1 (mode[1]), + .I2 (mode[2])); + // LUT = (I2)|(~I0&~I1) ; + GTP_LUT3 /* N142_mux4_3 */ #( .INIT(8'b10000000)) N142_mux4_3 ( @@ -71647,9 +71281,9 @@ module hybrid_filter_unq4 .Z (N162[0]), .I0 (median_res_b[0]), .I1 (gauss_res_b[0]), - .I2 (_N23821), + .I2 (_N22372), .I3 (raw_res_b[0]), - .I4 (_N20734), + .I4 (_N20118), .ID (N155[0])); // LUT = (I1&~I2&~I4)|(ID&I2&~I4)|(I2&I3&I4)|(I0&~I2&I4) ; @@ -71659,9 +71293,9 @@ module hybrid_filter_unq4 .Z (N162[1]), .I0 (median_res_b[1]), .I1 (gauss_res_b[1]), - .I2 (_N23821), + .I2 (_N22372), .I3 (raw_res_b[1]), - .I4 (_N20734), + .I4 (_N20118), .ID (N155[1])); // LUT = (I1&~I2&~I4)|(ID&I2&~I4)|(I2&I3&I4)|(I0&~I2&I4) ; @@ -71671,9 +71305,9 @@ module hybrid_filter_unq4 .Z (N162[2]), .I0 (median_res_b[2]), .I1 (gauss_res_b[2]), - .I2 (_N23821), + .I2 (_N22372), .I3 (raw_res_b[2]), - .I4 (_N20734), + .I4 (_N20118), .ID (N155[2])); // LUT = (I1&~I2&~I4)|(ID&I2&~I4)|(I2&I3&I4)|(I0&~I2&I4) ; @@ -71683,9 +71317,9 @@ module hybrid_filter_unq4 .Z (N162[3]), .I0 (median_res_b[3]), .I1 (gauss_res_b[3]), - .I2 (_N23821), + .I2 (_N22372), .I3 (raw_res_b[3]), - .I4 (_N20734), + .I4 (_N20118), .ID (N155[3])); // LUT = (I1&~I2&~I4)|(ID&I2&~I4)|(I2&I3&I4)|(I0&~I2&I4) ; @@ -71695,16 +71329,16 @@ module hybrid_filter_unq4 .Z (N162[4]), .I0 (median_res_b[4]), .I1 (gauss_res_b[4]), - .I2 (_N23821), + .I2 (_N22372), .I3 (raw_res_b[4]), - .I4 (_N20734), + .I4 (_N20118), .ID (N155[4])); // LUT = (I1&~I2&~I4)|(ID&I2&~I4)|(I2&I3&I4)|(I0&~I2&I4) ; GTP_LUT5 /* N162_72 */ #( .INIT(32'b11101101111011011110110111100101)) N162_72 ( - .Z (_N20734), + .Z (_N20118), .I0 (mode[0]), .I1 (mode[1]), .I2 (mode[2]), @@ -72684,8 +72318,6 @@ module ipml_fifo_ctrl_v1_3_1_unq12 wire N22; wire N24; wire [12:0] \N24.co ; - wire _N13395; - wire _N13396; wire _N13397; wire _N13398; wire _N13399; @@ -72695,8 +72327,8 @@ module ipml_fifo_ctrl_v1_3_1_unq12 wire _N13403; wire _N13404; wire _N13405; - wire _N13408; - wire _N13409; + wire _N13406; + wire _N13407; wire _N13410; wire _N13411; wire _N13412; @@ -72706,6 +72338,8 @@ module ipml_fifo_ctrl_v1_3_1_unq12 wire _N13416; wire _N13417; wire _N13418; + wire _N13419; + wire _N13420; wire [11:0] rbin; wire rempty; wire [11:0] rrptr; @@ -72725,7 +72359,7 @@ module ipml_fifo_ctrl_v1_3_1_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_1 ( - .COUT (_N13395), + .COUT (_N13397), .Z (N2[0]), .CIN (), .I0 (w_en), @@ -72745,9 +72379,9 @@ module ipml_fifo_ctrl_v1_3_1_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_2 ( - .COUT (_N13396), + .COUT (_N13398), .Z (N2[1]), - .CIN (_N13395), + .CIN (_N13397), .I0 (w_en), .I1 (waddr[0]), .I2 (waddr[1]), @@ -72765,9 +72399,9 @@ module ipml_fifo_ctrl_v1_3_1_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_3 ( - .COUT (_N13397), + .COUT (_N13399), .Z (N2[2]), - .CIN (_N13396), + .CIN (_N13398), .I0 (), .I1 (waddr[2]), .I2 (), @@ -72785,9 +72419,9 @@ module ipml_fifo_ctrl_v1_3_1_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_4 ( - .COUT (_N13398), + .COUT (_N13400), .Z (N2[3]), - .CIN (_N13397), + .CIN (_N13399), .I0 (), .I1 (waddr[3]), .I2 (), @@ -72805,9 +72439,9 @@ module ipml_fifo_ctrl_v1_3_1_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_5 ( - .COUT (_N13399), + .COUT (_N13401), .Z (N2[4]), - .CIN (_N13398), + .CIN (_N13400), .I0 (), .I1 (waddr[4]), .I2 (), @@ -72825,9 +72459,9 @@ module ipml_fifo_ctrl_v1_3_1_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_6 ( - .COUT (_N13400), + .COUT (_N13402), .Z (N2[5]), - .CIN (_N13399), + .CIN (_N13401), .I0 (), .I1 (waddr[5]), .I2 (), @@ -72845,9 +72479,9 @@ module ipml_fifo_ctrl_v1_3_1_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_7 ( - .COUT (_N13401), + .COUT (_N13403), .Z (N2[6]), - .CIN (_N13400), + .CIN (_N13402), .I0 (), .I1 (waddr[6]), .I2 (), @@ -72865,9 +72499,9 @@ module ipml_fifo_ctrl_v1_3_1_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_8 ( - .COUT (_N13402), + .COUT (_N13404), .Z (N2[7]), - .CIN (_N13401), + .CIN (_N13403), .I0 (), .I1 (waddr[7]), .I2 (), @@ -72885,9 +72519,9 @@ module ipml_fifo_ctrl_v1_3_1_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_9 ( - .COUT (_N13403), + .COUT (_N13405), .Z (N2[8]), - .CIN (_N13402), + .CIN (_N13404), .I0 (), .I1 (waddr[8]), .I2 (), @@ -72905,9 +72539,9 @@ module ipml_fifo_ctrl_v1_3_1_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_10 ( - .COUT (_N13404), + .COUT (_N13406), .Z (N2[9]), - .CIN (_N13403), + .CIN (_N13405), .I0 (), .I1 (waddr[9]), .I2 (), @@ -72925,9 +72559,9 @@ module ipml_fifo_ctrl_v1_3_1_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_11 ( - .COUT (_N13405), + .COUT (_N13407), .Z (N2[10]), - .CIN (_N13404), + .CIN (_N13406), .I0 (), .I1 (waddr[10]), .I2 (), @@ -72947,7 +72581,7 @@ module ipml_fifo_ctrl_v1_3_1_unq12 N2_12 ( .COUT (), .Z (N2[11]), - .CIN (_N13405), + .CIN (_N13407), .I0 (), .I1 (wbin[11]), .I2 (), @@ -73090,7 +72724,7 @@ module ipml_fifo_ctrl_v1_3_1_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_1 ( - .COUT (_N13408), + .COUT (_N13410), .Z (N11[0]), .CIN (), .I0 (r_en), @@ -73110,9 +72744,9 @@ module ipml_fifo_ctrl_v1_3_1_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_2 ( - .COUT (_N13409), + .COUT (_N13411), .Z (N11[1]), - .CIN (_N13408), + .CIN (_N13410), .I0 (r_en), .I1 (raddr[0]), .I2 (raddr[1]), @@ -73130,9 +72764,9 @@ module ipml_fifo_ctrl_v1_3_1_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_3 ( - .COUT (_N13410), + .COUT (_N13412), .Z (N11[2]), - .CIN (_N13409), + .CIN (_N13411), .I0 (), .I1 (raddr[2]), .I2 (), @@ -73150,9 +72784,9 @@ module ipml_fifo_ctrl_v1_3_1_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_4 ( - .COUT (_N13411), + .COUT (_N13413), .Z (N11[3]), - .CIN (_N13410), + .CIN (_N13412), .I0 (), .I1 (raddr[3]), .I2 (), @@ -73170,9 +72804,9 @@ module ipml_fifo_ctrl_v1_3_1_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_5 ( - .COUT (_N13412), + .COUT (_N13414), .Z (N11[4]), - .CIN (_N13411), + .CIN (_N13413), .I0 (), .I1 (raddr[4]), .I2 (), @@ -73190,9 +72824,9 @@ module ipml_fifo_ctrl_v1_3_1_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_6 ( - .COUT (_N13413), + .COUT (_N13415), .Z (N11[5]), - .CIN (_N13412), + .CIN (_N13414), .I0 (), .I1 (raddr[5]), .I2 (), @@ -73210,9 +72844,9 @@ module ipml_fifo_ctrl_v1_3_1_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_7 ( - .COUT (_N13414), + .COUT (_N13416), .Z (N11[6]), - .CIN (_N13413), + .CIN (_N13415), .I0 (), .I1 (raddr[6]), .I2 (), @@ -73230,9 +72864,9 @@ module ipml_fifo_ctrl_v1_3_1_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_8 ( - .COUT (_N13415), + .COUT (_N13417), .Z (N11[7]), - .CIN (_N13414), + .CIN (_N13416), .I0 (), .I1 (raddr[7]), .I2 (), @@ -73250,9 +72884,9 @@ module ipml_fifo_ctrl_v1_3_1_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_9 ( - .COUT (_N13416), + .COUT (_N13418), .Z (N11[8]), - .CIN (_N13415), + .CIN (_N13417), .I0 (), .I1 (raddr[8]), .I2 (), @@ -73270,9 +72904,9 @@ module ipml_fifo_ctrl_v1_3_1_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_10 ( - .COUT (_N13417), + .COUT (_N13419), .Z (N11[9]), - .CIN (_N13416), + .CIN (_N13418), .I0 (), .I1 (raddr[9]), .I2 (), @@ -73290,9 +72924,9 @@ module ipml_fifo_ctrl_v1_3_1_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_11 ( - .COUT (_N13418), + .COUT (_N13420), .Z (N11[10]), - .CIN (_N13417), + .CIN (_N13419), .I0 (), .I1 (raddr[10]), .I2 (), @@ -73312,7 +72946,7 @@ module ipml_fifo_ctrl_v1_3_1_unq12 N11_12 ( .COUT (), .Z (N11[11]), - .CIN (_N13418), + .CIN (_N13420), .I0 (), .I1 (rbin[11]), .I2 (), @@ -74299,28 +73933,28 @@ module ipml_fifo_ctrl_v1_3_1_unq14 wire N22; wire N24; wire [12:0] \N24.co ; - wire _N16357; - wire _N16358; - wire _N16359; - wire _N16360; - wire _N16361; - wire _N16362; - wire _N16363; - wire _N16364; - wire _N16365; - wire _N16366; - wire _N16367; - wire _N16370; - wire _N16371; - wire _N16372; - wire _N16373; - wire _N16374; - wire _N16375; - wire _N16376; - wire _N16377; - wire _N16378; - wire _N16379; - wire _N16380; + wire _N16528; + wire _N16529; + wire _N16530; + wire _N16531; + wire _N16532; + wire _N16533; + wire _N16534; + wire _N16535; + wire _N16536; + wire _N16537; + wire _N16538; + wire _N16541; + wire _N16542; + wire _N16543; + wire _N16544; + wire _N16545; + wire _N16546; + wire _N16547; + wire _N16548; + wire _N16549; + wire _N16550; + wire _N16551; wire [11:0] rbin; wire rempty; wire [11:0] rrptr; @@ -74340,7 +73974,7 @@ module ipml_fifo_ctrl_v1_3_1_unq14 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_1 ( - .COUT (_N16357), + .COUT (_N16528), .Z (N2[0]), .CIN (), .I0 (w_en), @@ -74360,9 +73994,9 @@ module ipml_fifo_ctrl_v1_3_1_unq14 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_2 ( - .COUT (_N16358), + .COUT (_N16529), .Z (N2[1]), - .CIN (_N16357), + .CIN (_N16528), .I0 (w_en), .I1 (waddr[0]), .I2 (waddr[1]), @@ -74380,9 +74014,9 @@ module ipml_fifo_ctrl_v1_3_1_unq14 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_3 ( - .COUT (_N16359), + .COUT (_N16530), .Z (N2[2]), - .CIN (_N16358), + .CIN (_N16529), .I0 (), .I1 (waddr[2]), .I2 (), @@ -74400,9 +74034,9 @@ module ipml_fifo_ctrl_v1_3_1_unq14 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_4 ( - .COUT (_N16360), + .COUT (_N16531), .Z (N2[3]), - .CIN (_N16359), + .CIN (_N16530), .I0 (), .I1 (waddr[3]), .I2 (), @@ -74420,9 +74054,9 @@ module ipml_fifo_ctrl_v1_3_1_unq14 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_5 ( - .COUT (_N16361), + .COUT (_N16532), .Z (N2[4]), - .CIN (_N16360), + .CIN (_N16531), .I0 (), .I1 (waddr[4]), .I2 (), @@ -74440,9 +74074,9 @@ module ipml_fifo_ctrl_v1_3_1_unq14 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_6 ( - .COUT (_N16362), + .COUT (_N16533), .Z (N2[5]), - .CIN (_N16361), + .CIN (_N16532), .I0 (), .I1 (waddr[5]), .I2 (), @@ -74460,9 +74094,9 @@ module ipml_fifo_ctrl_v1_3_1_unq14 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_7 ( - .COUT (_N16363), + .COUT (_N16534), .Z (N2[6]), - .CIN (_N16362), + .CIN (_N16533), .I0 (), .I1 (waddr[6]), .I2 (), @@ -74480,9 +74114,9 @@ module ipml_fifo_ctrl_v1_3_1_unq14 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_8 ( - .COUT (_N16364), + .COUT (_N16535), .Z (N2[7]), - .CIN (_N16363), + .CIN (_N16534), .I0 (), .I1 (waddr[7]), .I2 (), @@ -74500,9 +74134,9 @@ module ipml_fifo_ctrl_v1_3_1_unq14 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_9 ( - .COUT (_N16365), + .COUT (_N16536), .Z (N2[8]), - .CIN (_N16364), + .CIN (_N16535), .I0 (), .I1 (waddr[8]), .I2 (), @@ -74520,9 +74154,9 @@ module ipml_fifo_ctrl_v1_3_1_unq14 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_10 ( - .COUT (_N16366), + .COUT (_N16537), .Z (N2[9]), - .CIN (_N16365), + .CIN (_N16536), .I0 (), .I1 (waddr[9]), .I2 (), @@ -74540,9 +74174,9 @@ module ipml_fifo_ctrl_v1_3_1_unq14 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_11 ( - .COUT (_N16367), + .COUT (_N16538), .Z (N2[10]), - .CIN (_N16366), + .CIN (_N16537), .I0 (), .I1 (waddr[10]), .I2 (), @@ -74562,7 +74196,7 @@ module ipml_fifo_ctrl_v1_3_1_unq14 N2_12 ( .COUT (), .Z (N2[11]), - .CIN (_N16367), + .CIN (_N16538), .I0 (), .I1 (wbin[11]), .I2 (), @@ -74705,7 +74339,7 @@ module ipml_fifo_ctrl_v1_3_1_unq14 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_1 ( - .COUT (_N16370), + .COUT (_N16541), .Z (N11[0]), .CIN (), .I0 (r_en), @@ -74725,9 +74359,9 @@ module ipml_fifo_ctrl_v1_3_1_unq14 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_2 ( - .COUT (_N16371), + .COUT (_N16542), .Z (N11[1]), - .CIN (_N16370), + .CIN (_N16541), .I0 (r_en), .I1 (raddr[0]), .I2 (raddr[1]), @@ -74745,9 +74379,9 @@ module ipml_fifo_ctrl_v1_3_1_unq14 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_3 ( - .COUT (_N16372), + .COUT (_N16543), .Z (N11[2]), - .CIN (_N16371), + .CIN (_N16542), .I0 (), .I1 (raddr[2]), .I2 (), @@ -74765,9 +74399,9 @@ module ipml_fifo_ctrl_v1_3_1_unq14 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_4 ( - .COUT (_N16373), + .COUT (_N16544), .Z (N11[3]), - .CIN (_N16372), + .CIN (_N16543), .I0 (), .I1 (raddr[3]), .I2 (), @@ -74785,9 +74419,9 @@ module ipml_fifo_ctrl_v1_3_1_unq14 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_5 ( - .COUT (_N16374), + .COUT (_N16545), .Z (N11[4]), - .CIN (_N16373), + .CIN (_N16544), .I0 (), .I1 (raddr[4]), .I2 (), @@ -74805,9 +74439,9 @@ module ipml_fifo_ctrl_v1_3_1_unq14 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_6 ( - .COUT (_N16375), + .COUT (_N16546), .Z (N11[5]), - .CIN (_N16374), + .CIN (_N16545), .I0 (), .I1 (raddr[5]), .I2 (), @@ -74825,9 +74459,9 @@ module ipml_fifo_ctrl_v1_3_1_unq14 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_7 ( - .COUT (_N16376), + .COUT (_N16547), .Z (N11[6]), - .CIN (_N16375), + .CIN (_N16546), .I0 (), .I1 (raddr[6]), .I2 (), @@ -74845,9 +74479,9 @@ module ipml_fifo_ctrl_v1_3_1_unq14 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_8 ( - .COUT (_N16377), + .COUT (_N16548), .Z (N11[7]), - .CIN (_N16376), + .CIN (_N16547), .I0 (), .I1 (raddr[7]), .I2 (), @@ -74865,9 +74499,9 @@ module ipml_fifo_ctrl_v1_3_1_unq14 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_9 ( - .COUT (_N16378), + .COUT (_N16549), .Z (N11[8]), - .CIN (_N16377), + .CIN (_N16548), .I0 (), .I1 (raddr[8]), .I2 (), @@ -74885,9 +74519,9 @@ module ipml_fifo_ctrl_v1_3_1_unq14 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_10 ( - .COUT (_N16379), + .COUT (_N16550), .Z (N11[9]), - .CIN (_N16378), + .CIN (_N16549), .I0 (), .I1 (raddr[9]), .I2 (), @@ -74905,9 +74539,9 @@ module ipml_fifo_ctrl_v1_3_1_unq14 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_11 ( - .COUT (_N16380), + .COUT (_N16551), .Z (N11[10]), - .CIN (_N16379), + .CIN (_N16550), .I0 (), .I1 (raddr[10]), .I2 (), @@ -74927,7 +74561,7 @@ module ipml_fifo_ctrl_v1_3_1_unq14 N11_12 ( .COUT (), .Z (N11[11]), - .CIN (_N16380), + .CIN (_N16551), .I0 (), .I1 (rbin[11]), .I2 (), @@ -75906,8 +75540,8 @@ module multiline_buffer_unq4 input srst, output [47:0] m_multiline_pixel_data, output N53, - output _N97340, - output _N103920, + output _N98107, + output _N104744, output m_pixel_valid ); wire [10:0] N13; @@ -75926,42 +75560,42 @@ module multiline_buffer_unq4 wire [10:0] N281; wire [10:0] N285; wire [10:0] N287; + wire _N13613; + wire _N13614; + wire _N13615; wire _N13616; wire _N13617; wire _N13618; wire _N13619; wire _N13620; wire _N13621; - wire _N13622; - wire _N13623; wire _N13624; - wire _N13634; - wire _N13635; - wire _N13636; - wire _N13637; - wire _N13638; - wire _N13639; - wire _N13640; - wire _N13641; - wire _N13642; - wire _N15737; - wire _N15738; - wire _N15739; - wire _N15740; - wire _N15741; - wire _N15742; - wire _N15743; - wire _N15959; - wire _N15960; - wire _N15961; - wire _N15962; - wire _N84159; - wire _N97104; - wire _N98270; - wire _N103753; - wire _N103754; - wire _N103759; - wire _N103916; + wire _N13625; + wire _N13626; + wire _N13627; + wire _N13628; + wire _N13629; + wire _N13630; + wire _N13631; + wire _N13632; + wire _N15982; + wire _N15983; + wire _N15984; + wire _N15985; + wire _N15986; + wire _N15987; + wire _N15988; + wire _N15991; + wire _N15992; + wire _N15993; + wire _N15994; + wire _N84996; + wire _N97883; + wire _N101318; + wire _N104576; + wire _N104577; + wire _N104582; + wire _N104740; wire [47:0] dout; wire [10:0] hor_cnt; wire \hor_cnt[0]_inv ; @@ -75979,7 +75613,7 @@ module multiline_buffer_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N12_1_1 ( - .COUT (_N13616), + .COUT (_N13613), .Z (N287[1]), .CIN (), .I0 (hor_cnt[0]), @@ -75999,9 +75633,9 @@ module multiline_buffer_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N12_1_2 ( - .COUT (_N13617), + .COUT (_N13614), .Z (N287[2]), - .CIN (_N13616), + .CIN (_N13613), .I0 (hor_cnt[0]), .I1 (hor_cnt[1]), .I2 (hor_cnt[2]), @@ -76019,9 +75653,9 @@ module multiline_buffer_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N12_1_3 ( - .COUT (_N13618), + .COUT (_N13615), .Z (N287[3]), - .CIN (_N13617), + .CIN (_N13614), .I0 (), .I1 (hor_cnt[3]), .I2 (), @@ -76039,9 +75673,9 @@ module multiline_buffer_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N12_1_4 ( - .COUT (_N13619), + .COUT (_N13616), .Z (N287[4]), - .CIN (_N13618), + .CIN (_N13615), .I0 (), .I1 (hor_cnt[4]), .I2 (), @@ -76059,9 +75693,9 @@ module multiline_buffer_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N12_1_5 ( - .COUT (_N13620), + .COUT (_N13617), .Z (N287[5]), - .CIN (_N13619), + .CIN (_N13616), .I0 (), .I1 (hor_cnt[5]), .I2 (), @@ -76079,9 +75713,9 @@ module multiline_buffer_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N12_1_6 ( - .COUT (_N13621), + .COUT (_N13618), .Z (N287[6]), - .CIN (_N13620), + .CIN (_N13617), .I0 (), .I1 (hor_cnt[6]), .I2 (), @@ -76099,9 +75733,9 @@ module multiline_buffer_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N12_1_7 ( - .COUT (_N13622), + .COUT (_N13619), .Z (N287[7]), - .CIN (_N13621), + .CIN (_N13618), .I0 (), .I1 (hor_cnt[7]), .I2 (), @@ -76119,9 +75753,9 @@ module multiline_buffer_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N12_1_8 ( - .COUT (_N13623), + .COUT (_N13620), .Z (N287[8]), - .CIN (_N13622), + .CIN (_N13619), .I0 (), .I1 (hor_cnt[8]), .I2 (), @@ -76139,9 +75773,9 @@ module multiline_buffer_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N12_1_9 ( - .COUT (_N13624), + .COUT (_N13621), .Z (N287[9]), - .CIN (_N13623), + .CIN (_N13620), .I0 (), .I1 (hor_cnt[9]), .I2 (), @@ -76161,7 +75795,7 @@ module multiline_buffer_unq4 N12_1_10 ( .COUT (), .Z (N287[10]), - .CIN (_N13624), + .CIN (_N13621), .I0 (), .I1 (hor_cnt[10]), .I2 (), @@ -76197,7 +75831,7 @@ module multiline_buffer_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N33_1_1 ( - .COUT (_N15737), + .COUT (_N15982), .Z (N285[1]), .CIN (), .I0 (ver_cnt[0]), @@ -76217,9 +75851,9 @@ module multiline_buffer_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N33_1_2 ( - .COUT (_N15738), + .COUT (_N15983), .Z (N285[2]), - .CIN (_N15737), + .CIN (_N15982), .I0 (ver_cnt[0]), .I1 (ver_cnt[1]), .I2 (ver_cnt[2]), @@ -76237,9 +75871,9 @@ module multiline_buffer_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N33_1_3 ( - .COUT (_N15739), + .COUT (_N15984), .Z (N285[3]), - .CIN (_N15738), + .CIN (_N15983), .I0 (), .I1 (ver_cnt[3]), .I2 (), @@ -76257,9 +75891,9 @@ module multiline_buffer_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N33_1_4 ( - .COUT (_N15740), + .COUT (_N15985), .Z (N285[4]), - .CIN (_N15739), + .CIN (_N15984), .I0 (), .I1 (ver_cnt[4]), .I2 (), @@ -76277,9 +75911,9 @@ module multiline_buffer_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N33_1_5 ( - .COUT (_N15741), + .COUT (_N15986), .Z (N285[5]), - .CIN (_N15740), + .CIN (_N15985), .I0 (), .I1 (ver_cnt[5]), .I2 (), @@ -76297,9 +75931,9 @@ module multiline_buffer_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N33_1_6 ( - .COUT (_N15742), + .COUT (_N15987), .Z (N285[6]), - .CIN (_N15741), + .CIN (_N15986), .I0 (), .I1 (ver_cnt[6]), .I2 (), @@ -76317,9 +75951,9 @@ module multiline_buffer_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N33_1_7 ( - .COUT (_N15743), + .COUT (_N15988), .Z (N285[7]), - .CIN (_N15742), + .CIN (_N15987), .I0 (), .I1 (ver_cnt[7]), .I2 (), @@ -76339,7 +75973,7 @@ module multiline_buffer_unq4 N33_1_8 ( .COUT (), .Z (N285[8]), - .CIN (_N15743), + .CIN (_N15988), .I0 (), .I1 (ver_cnt[8]), .I2 (), @@ -76357,8 +75991,8 @@ module multiline_buffer_unq4 .I0 (N285[3]), .I1 (ver_cnt[6]), .I2 (ver_cnt[8]), - .I3 (_N97104), - .I4 (_N103759)); + .I3 (_N97883), + .I4 (_N104582)); // LUT = (I0&~I4)|(I0&~I3)|(I0&~I2)|(I0&~I1) ; // ../../sources/designs/image_filiter/multiline_buffer.v:89 @@ -76369,8 +76003,8 @@ module multiline_buffer_unq4 .I0 (N285[5]), .I1 (ver_cnt[6]), .I2 (ver_cnt[8]), - .I3 (_N97104), - .I4 (_N103759)); + .I3 (_N97883), + .I4 (_N104582)); // LUT = (I0&~I4)|(I0&~I3)|(I0&~I2)|(I0&~I1) ; // ../../sources/designs/image_filiter/multiline_buffer.v:89 @@ -76381,8 +76015,8 @@ module multiline_buffer_unq4 .I0 (N285[6]), .I1 (ver_cnt[6]), .I2 (ver_cnt[8]), - .I3 (_N97104), - .I4 (_N103759)); + .I3 (_N97883), + .I4 (_N104582)); // LUT = (I0&~I4)|(I0&~I3)|(I0&~I2)|(I0&~I1) ; // ../../sources/designs/image_filiter/multiline_buffer.v:89 @@ -76393,8 +76027,8 @@ module multiline_buffer_unq4 .I0 (N285[8]), .I1 (ver_cnt[6]), .I2 (ver_cnt[8]), - .I3 (_N97104), - .I4 (_N103759)); + .I3 (_N97883), + .I4 (_N104582)); // LUT = (I0&~I4)|(I0&~I3)|(I0&~I2)|(I0&~I1) ; // ../../sources/designs/image_filiter/multiline_buffer.v:89 @@ -76405,11 +76039,22 @@ module multiline_buffer_unq4 .I0 (N21), .I1 (ver_cnt[6]), .I2 (ver_cnt[8]), - .I3 (_N97104), - .I4 (_N103759)); + .I3 (_N97883), + .I4 (_N104582)); // defparam N48_vname.orig_name = N48; // LUT = I0&I1&I2&I3&I4 ; + GTP_LUT5 /* N53_mux5_8 */ #( + .INIT(32'b11111111111111111111111111111110)) + N53_mux5_8 ( + .Z (N53), + .I0 (tail_ver_cnt[1]), + .I1 (tail_ver_cnt[2]), + .I2 (tail_ver_cnt[3]), + .I3 (tail_ver_cnt[4]), + .I4 (tail_ver_cnt[5])); + // LUT = (I0)|(I1)|(I2)|(I3)|(I4) ; + GTP_LUT5CARRY /* N66_1_1 */ #( .INIT(32'b11110110111101100000000000000000), .ID_TO_LUT("FALSE"), @@ -76417,7 +76062,7 @@ module multiline_buffer_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N66_1_1 ( - .COUT (_N15959), + .COUT (_N15991), .Z (N273[1]), .CIN (), .I0 (tail_ver_cnt[0]), @@ -76437,9 +76082,9 @@ module multiline_buffer_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N66_1_2 ( - .COUT (_N15960), + .COUT (_N15992), .Z (N273[2]), - .CIN (_N15959), + .CIN (_N15991), .I0 (tail_ver_cnt[0]), .I1 (tail_ver_cnt[1]), .I2 (rd3_rst), @@ -76457,9 +76102,9 @@ module multiline_buffer_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N66_1_3 ( - .COUT (_N15961), + .COUT (_N15993), .Z (N273[3]), - .CIN (_N15960), + .CIN (_N15992), .I0 (), .I1 (tail_ver_cnt[3]), .I2 (rd3_rst), @@ -76477,9 +76122,9 @@ module multiline_buffer_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N66_1_4 ( - .COUT (_N15962), + .COUT (_N15994), .Z (N273[4]), - .CIN (_N15961), + .CIN (_N15993), .I0 (), .I1 (tail_ver_cnt[4]), .I2 (rd3_rst), @@ -76499,7 +76144,7 @@ module multiline_buffer_unq4 N66_1_5 ( .COUT (), .Z (N273[5]), - .CIN (_N15962), + .CIN (_N15994), .I0 (), .I1 (tail_ver_cnt[5]), .I2 (rd3_rst), @@ -76517,7 +76162,7 @@ module multiline_buffer_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_1_1 ( - .COUT (_N13634), + .COUT (_N13624), .Z (N281[1]), .CIN (), .I0 (tail_hor_cnt[0]), @@ -76537,9 +76182,9 @@ module multiline_buffer_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_1_2 ( - .COUT (_N13635), + .COUT (_N13625), .Z (N281[2]), - .CIN (_N13634), + .CIN (_N13624), .I0 (tail_hor_cnt[0]), .I1 (tail_hor_cnt[1]), .I2 (tail_hor_cnt[2]), @@ -76557,9 +76202,9 @@ module multiline_buffer_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_1_3 ( - .COUT (_N13636), + .COUT (_N13626), .Z (N281[3]), - .CIN (_N13635), + .CIN (_N13625), .I0 (), .I1 (tail_hor_cnt[3]), .I2 (), @@ -76577,9 +76222,9 @@ module multiline_buffer_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_1_4 ( - .COUT (_N13637), + .COUT (_N13627), .Z (N281[4]), - .CIN (_N13636), + .CIN (_N13626), .I0 (), .I1 (tail_hor_cnt[4]), .I2 (), @@ -76597,9 +76242,9 @@ module multiline_buffer_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_1_5 ( - .COUT (_N13638), + .COUT (_N13628), .Z (N281[5]), - .CIN (_N13637), + .CIN (_N13627), .I0 (), .I1 (tail_hor_cnt[5]), .I2 (), @@ -76617,9 +76262,9 @@ module multiline_buffer_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_1_6 ( - .COUT (_N13639), + .COUT (_N13629), .Z (N281[6]), - .CIN (_N13638), + .CIN (_N13628), .I0 (), .I1 (tail_hor_cnt[6]), .I2 (), @@ -76637,9 +76282,9 @@ module multiline_buffer_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_1_7 ( - .COUT (_N13640), + .COUT (_N13630), .Z (N281[7]), - .CIN (_N13639), + .CIN (_N13629), .I0 (), .I1 (tail_hor_cnt[7]), .I2 (), @@ -76657,9 +76302,9 @@ module multiline_buffer_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_1_8 ( - .COUT (_N13641), + .COUT (_N13631), .Z (N281[8]), - .CIN (_N13640), + .CIN (_N13630), .I0 (), .I1 (tail_hor_cnt[8]), .I2 (), @@ -76677,9 +76322,9 @@ module multiline_buffer_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_1_9 ( - .COUT (_N13642), + .COUT (_N13632), .Z (N281[9]), - .CIN (_N13641), + .CIN (_N13631), .I0 (), .I1 (tail_hor_cnt[9]), .I2 (), @@ -76699,7 +76344,7 @@ module multiline_buffer_unq4 N69_1_10 ( .COUT (), .Z (N281[10]), - .CIN (_N13642), + .CIN (_N13632), .I0 (), .I1 (tail_hor_cnt[10]), .I2 (), @@ -76713,7 +76358,7 @@ module multiline_buffer_unq4 GTP_LUT4 /* N93_mux7_12 */ #( .INIT(16'b1000000000000000)) N93_mux7_12 ( - .Z (_N103916), + .Z (_N104740), .I0 (tail_hor_cnt[1]), .I1 (tail_hor_cnt[2]), .I2 (tail_hor_cnt[3]), @@ -76723,23 +76368,23 @@ module multiline_buffer_unq4 GTP_LUT5 /* N93_mux7_14 */ #( .INIT(32'b10000000000000000000000000000000)) N93_mux7_14 ( - .Z (_N97340), + .Z (_N98107), .I0 (tail_hor_cnt[0]), .I1 (tail_hor_cnt[5]), .I2 (tail_hor_cnt[6]), .I3 (tail_hor_cnt[7]), - .I4 (_N103916)); + .I4 (_N104740)); // LUT = I0&I1&I2&I3&I4 ; - GTP_LUT5 /* N96_3 */ #( + GTP_LUT5 /* N96_1 */ #( .INIT(32'b00000000010101010000000101010101)) - N96_3 ( + N96_1 ( .Z (N96), .I0 (N199), .I1 (tail_hor_cnt[8]), .I2 (tail_hor_cnt[9]), .I3 (tail_hor_cnt[10]), - .I4 (_N97340)); + .I4 (_N98107)); // LUT = (~I0&~I3)|(~I0&~I1&~I2&~I4) ; GTP_LUT1 /* N120_eq0_inv */ #( @@ -76764,7 +76409,7 @@ module multiline_buffer_unq4 GTP_LUT4 /* N176_2 */ #( .INIT(16'b0000000000000010)) N176_2 ( - .Z (_N97104), + .Z (_N97883), .I0 (ver_cnt[0]), .I1 (ver_cnt[3]), .I2 (ver_cnt[4]), @@ -76782,7 +76427,7 @@ module multiline_buffer_unq4 GTP_LUT4 /* N176_12 */ #( .INIT(16'b0000000000000001)) N176_12 ( - .Z (_N98270), + .Z (_N101318), .I0 (ver_cnt[2]), .I1 (ver_cnt[5]), .I2 (ver_cnt[6]), @@ -76795,8 +76440,8 @@ module multiline_buffer_unq4 .Z (N176), .I0 (N229), .I1 (ver_cnt[1]), - .I2 (_N97104), - .I3 (_N98270)); + .I2 (_N97883), + .I3 (_N101318)); // LUT = I0&~I1&I2&I3 ; GTP_LUT5 /* N179_mux8_9 */ #( @@ -76807,7 +76452,7 @@ module multiline_buffer_unq4 .I1 (ver_cnt[3]), .I2 (ver_cnt[4]), .I3 (ver_cnt[7]), - .I4 (_N98270)); + .I4 (_N101318)); // LUT = (~I4)|(I0)|(I1)|(I2)|(I3) ; GTP_LUT5 /* \N189[1]_1 */ #( @@ -76818,18 +76463,18 @@ module multiline_buffer_unq4 .I1 (N53), .I2 (N176), .I3 (N179), - .I4 (_N84159)); + .I4 (_N84996)); // LUT = (~I1&I4)|(I0&I2)|(I0&I3) ; GTP_LUT5 /* \N189[1]_8 */ #( .INIT(32'b00001111111111110001111111111111)) \N189[1]_8 ( - .Z (_N84159), + .Z (_N84996), .I0 (tail_hor_cnt[8]), .I1 (tail_hor_cnt[9]), .I2 (tail_hor_cnt[10]), .I3 (tail_ver_cnt[0]), - .I4 (_N97340)); + .I4 (_N98107)); // LUT = (~I3)|(~I2)|(~I0&~I1&~I4) ; GTP_LUT2 /* N199_mux5 */ #( @@ -76840,17 +76485,6 @@ module multiline_buffer_unq4 .I1 (tail_ver_cnt[0])); // LUT = (I0)|(I1) ; - GTP_LUT5 /* N199_mux5_8 */ #( - .INIT(32'b11111111111111111111111111111110)) - N199_mux5_8 ( - .Z (N53), - .I0 (tail_ver_cnt[1]), - .I1 (tail_ver_cnt[2]), - .I2 (tail_ver_cnt[3]), - .I3 (tail_ver_cnt[4]), - .I4 (tail_ver_cnt[5])); - // LUT = (I0)|(I1)|(I2)|(I3)|(I4) ; - GTP_LUT3 /* \N204[0] */ #( .INIT(8'b11100100)) \N204[0] ( @@ -77182,7 +76816,7 @@ module multiline_buffer_unq4 GTP_LUT4 /* N229_8 */ #( .INIT(16'b1000000000000000)) N229_8 ( - .Z (_N103753), + .Z (_N104576), .I0 (hor_cnt[1]), .I1 (hor_cnt[2]), .I2 (hor_cnt[3]), @@ -77192,7 +76826,7 @@ module multiline_buffer_unq4 GTP_LUT4 /* N229_9 */ #( .INIT(16'b1000000000000000)) N229_9 ( - .Z (_N103754), + .Z (_N104577), .I0 (hor_cnt[5]), .I1 (hor_cnt[6]), .I2 (hor_cnt[7]), @@ -77206,14 +76840,14 @@ module multiline_buffer_unq4 .I0 (hor_cnt[0]), .I1 (hor_cnt[8]), .I2 (hor_cnt[9]), - .I3 (_N103753), - .I4 (_N103754)); + .I3 (_N104576), + .I4 (_N104577)); // LUT = I0&~I1&~I2&I3&I4 ; GTP_LUT3 /* N236_4 */ #( .INIT(8'b10000000)) N236_4 ( - .Z (_N103759), + .Z (_N104582), .I0 (ver_cnt[1]), .I1 (ver_cnt[2]), .I2 (ver_cnt[5])); @@ -77222,7 +76856,7 @@ module multiline_buffer_unq4 GTP_LUT3 /* N269_3 */ #( .INIT(8'b00010000)) N269_3 ( - .Z (_N103920), + .Z (_N104744), .I0 (tail_hor_cnt[8]), .I1 (tail_hor_cnt[9]), .I2 (tail_hor_cnt[10])); @@ -79309,22 +78943,17 @@ endmodule module image_filiter_unq4 ( input [2:0] mode, - input [13:0] \param_manager_inst/selected , input [15:0] s_pixel_data, input clk, input \image_filiter_inst/multiline_buffer_inst/srst , input \multiline_buffer_inst/N272 , - input \param_manager_inst/param_filiter1_mode/changed_up , - input \param_manager_inst/param_filiter1_mode/pressed_up , - input \param_manager_inst/param_modify_H/pluse , input rd3_rst, input s_pixel_valid, output [15:0] m_filtered_data, - output _N97340, - output _N103920, + output _N98107, + output _N104744, output m_filtered_valid, - output \multiline_buffer_inst/N53 , - output \param_manager_inst/param_zoom/N142 + output \multiline_buffer_inst/N53 ); wire [143:0] matrix_data; wire matrix_valid; @@ -79334,14 +78963,9 @@ module image_filiter_unq4 hybrid_filter_unq4 hybrid_filter_inst ( .m_result_data (m_filtered_data), .mode (mode), - .\param_manager_inst/selected ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \param_manager_inst/selected [2] , 1'bx, 1'bx}), .s_matrix_data (matrix_data), .m_result_valid (m_filtered_valid), - .\param_manager_inst/param_zoom/N142 (\param_manager_inst/param_zoom/N142 ), .clk (clk), - .\param_manager_inst/param_filiter1_mode/changed_up (\param_manager_inst/param_filiter1_mode/changed_up ), - .\param_manager_inst/param_filiter1_mode/pressed_up (\param_manager_inst/param_filiter1_mode/pressed_up ), - .\param_manager_inst/param_modify_H/pluse (\param_manager_inst/param_modify_H/pluse ), .rd3_rst (rd3_rst), .s_matrix_valid (matrix_valid)); // ../../sources/designs/image_filiter/image_filiter.v:69 @@ -79350,8 +78974,8 @@ module image_filiter_unq4 .m_multiline_pixel_data (multiline_pixel_data), .s_pixel_data (s_pixel_data), .N53 (\multiline_buffer_inst/N53 ), - ._N97340 (_N97340), - ._N103920 (_N103920), + ._N98107 (_N98107), + ._N104744 (_N104744), .m_pixel_valid (pixel_valid), .N272 (\multiline_buffer_inst/N272 ), .clk (clk), @@ -79377,9 +79001,11 @@ module iic_dri ( input [15:0] addr, input [7:0] data_in, + input [6:0] \ms72xx_ctl/iic_dri_tx/state_reg , input [2:0] \ms72xx_ctl/iic_dri_tx/trans_bit , + input [3:0] \ms72xx_ctl/iic_dri_tx/trans_byte , input _N8, - input _N95852, + input _N96626, input clk, input pluse, input rstn, @@ -79392,6 +79018,7 @@ module iic_dri output N0_1, output N72, output N80, + output _N96740, output busy, output byte_over, output dsu, @@ -79432,31 +79059,31 @@ module iic_dri wire _N17985; wire _N17986; wire _N17987; - wire _N19828; - wire _N19831; - wire _N29346; - wire _N29348; + wire _N19775; + wire _N19778; + wire _N29321; + wire _N29323; wire _N30788; wire _N30794; wire _N30799; wire _N30805; wire _N30810; - wire _N81582; - wire _N81586; - wire _N81608; - wire _N95846; - wire _N96754; - wire _N102144_2; - wire _N103285; - wire _N103287; - wire _N103288; - wire _N103289; - wire _N103296; - wire _N103488; - wire _N103986; - wire _N104016; - wire _N104046; - wire _N104065; + wire _N82353; + wire _N82357; + wire _N82374; + wire _N96619; + wire _N97518; + wire _N102965_2; + wire _N104097; + wire _N104099; + wire _N104100; + wire _N104101; + wire _N104108; + wire _N104300; + wire _N104811; + wire _N104841; + wire _N104871; + wire _N104890; wire [20:0] fre_cnt; wire pluse_1d; wire pluse_2d; @@ -79616,7 +79243,7 @@ module iic_dri GTP_LUT5M /* N120_4 */ #( .INIT(32'b11001010110010101111101000001010)) N120_4 ( - .Z (_N19828), + .Z (_N19775), .I0 (send_data[4]), .I1 (send_data[0]), .I2 (trans_bit[2]), @@ -79628,7 +79255,7 @@ module iic_dri GTP_LUT5M /* N120_7 */ #( .INIT(32'b11001010110010101111101000001010)) N120_7 ( - .Z (_N19831), + .Z (_N19778), .I0 (send_data[5]), .I1 (send_data[1]), .I2 (trans_bit[2]), @@ -79811,7 +79438,7 @@ module iic_dri GTP_LUT2 /* N345_2 */ #( .INIT(4'b0010)) N345_2 ( - .Z (_N104065), + .Z (_N104890), .I0 (twr_cnt[3]), .I1 (twr_cnt[2])); // LUT = I0&~I1 ; @@ -79819,7 +79446,7 @@ module iic_dri GTP_LUT2 /* N357_2 */ #( .INIT(4'b1000)) N357_2 ( - .Z (_N96754), + .Z (_N97518), .I0 (trans_byte[1]), .I1 (trans_byte[0])); // LUT = I0&I1 ; @@ -79856,7 +79483,7 @@ module iic_dri .Z (_N17987), .I0 (full_cycle), .I1 (start_en), - .I2 (_N102144_2)); + .I2 (_N102965_2)); // LUT = (~I1&I2)|(~I0&I2) ; // ../../sources/designs/hdmi/ms72xx_ctrl/iic_dri.v:204 @@ -79867,7 +79494,7 @@ module iic_dri .I0 (data_in[3]), .I1 (full_cycle), .I2 (start_en), - .I3 (_N102144_2)); + .I3 (_N102965_2)); // LUT = (I0&~I2&I3)|(I0&~I1&I3) ; GTP_LUT4 /* \N461_8_and[5][3] */ #( @@ -79877,7 +79504,7 @@ module iic_dri .I0 (data_in[5]), .I1 (full_cycle), .I2 (start_en), - .I3 (_N102144_2)); + .I3 (_N102965_2)); // LUT = (I0&~I2&I3)|(I0&~I1&I3) ; GTP_LUT5 /* \N461_8_inv[1] */ #( @@ -79927,12 +79554,12 @@ module iic_dri GTP_LUT5 /* \N461_8_or[0]_3 */ #( .INIT(32'b10101110000011001010101000000000)) \N461_8_or[0]_3 ( - .Z (_N104016), + .Z (_N104841), .I0 (addr[8]), .I1 (data_in[0]), .I2 (start), .I3 (_N17986), - .I4 (_N102144_2)); + .I4 (_N102965_2)); // LUT = (I0&I3)|(I1&~I2&I4) ; GTP_LUT5 /* \N461_8_or[0]_4 */ #( @@ -79942,8 +79569,8 @@ module iic_dri .I0 (addr[0]), .I1 (start), .I2 (_N17985), - .I3 (_N95846), - .I4 (_N104016)); + .I3 (_N96619), + .I4 (_N104841)); // LUT = (I4)|(~I1&I3)|(I0&I2) ; GTP_LUT4 /* \N461_8_or[1][3] */ #( @@ -79953,7 +79580,7 @@ module iic_dri .I0 (data_in[1]), .I1 (full_cycle), .I2 (start_en), - .I3 (_N102144_2)); + .I3 (_N102965_2)); // LUT = (~I0&~I2&I3)|(~I0&~I1&I3) ; GTP_LUT4 /* \N461_8_or[2][3] */ #( @@ -79963,7 +79590,7 @@ module iic_dri .I0 (data_in[2]), .I1 (full_cycle), .I2 (start_en), - .I3 (_N102144_2)); + .I3 (_N102965_2)); // LUT = (~I0&~I2&I3)|(~I0&~I1&I3) ; GTP_LUT5 /* \N461_8_or[3]_3 */ #( @@ -79984,7 +79611,7 @@ module iic_dri .I0 (data_in[4]), .I1 (full_cycle), .I2 (start_en), - .I3 (_N102144_2)); + .I3 (_N102965_2)); // LUT = (~I0&~I2&I3)|(~I0&~I1&I3) ; GTP_LUT5 /* \N461_8_or[5]_3 */ #( @@ -80006,7 +79633,7 @@ module iic_dri .I1 (data_in[7]), .I2 (start), .I3 (_N17985), - .I4 (_N102144_2)); + .I4 (_N102965_2)); // LUT = (I0&I3)|(I1&~I2&I4) ; GTP_LUT5 /* N461_9 */ #( @@ -80044,33 +79671,44 @@ module iic_dri GTP_LUT5M /* \N493_and[0][2] */ #( .INIT(32'b10101000101000001010100010100000)) \N493_and[0][2] ( - .Z (_N29346), - .I0 (_N19828), + .Z (_N29321), + .I0 (_N19775), .I1 (dsu), .I2 (state_reg[2]), .I3 (state_reg[1]), .I4 (trans_bit[0]), - .ID (_N19831)); + .ID (_N19778)); // LUT = (ID&I1&I3&~I4)|(ID&I2&~I4)|(I0&I1&I3&I4)|(I0&I2&I4) ; GTP_LUT3 /* \N493_and[0][4] */ #( .INIT(8'b00000100)) \N493_and[0][4] ( - .Z (_N29348), + .Z (_N29323), .I0 (N519[6]), .I1 (state_reg[5]), .I2 (dsu)); // LUT = ~I0&I1&~I2 ; + GTP_LUT5 /* \N493_and[0][4]_1 */ #( + .INIT(32'b10101010101010101010101010000000)) + \N493_and[0][4]_1 ( + .Z (_N96740), + .I0 (\ms72xx_ctl/iic_dri_tx/state_reg [3] ), + .I1 (\ms72xx_ctl/iic_dri_tx/trans_byte [0] ), + .I2 (\ms72xx_ctl/iic_dri_tx/trans_byte [1] ), + .I3 (\ms72xx_ctl/iic_dri_tx/trans_byte [2] ), + .I4 (\ms72xx_ctl/iic_dri_tx/trans_byte [3] )); + // LUT = (I0&I3)|(I0&I4)|(I0&I1&I2) ; + GTP_LUT5 /* \N493_or[0]_4 */ #( .INIT(32'b11111111111111111111111011111100)) \N493_or[0]_4 ( - .Z (_N104046), + .Z (_N104871), .I0 (state_reg[6]), .I1 (state_reg[4]), .I2 (state_reg[0]), .I3 (start_h), - .I4 (_N29348)); + .I4 (_N29323)); // LUT = (I1)|(I2)|(I4)|(I0&I3) ; GTP_INV N495 ( @@ -80085,13 +79723,13 @@ module iic_dri .I1 (trans_bit[1]), .I2 (trans_bit[0]), .I3 (dsu), - .I4 (_N102144_2)); + .I4 (_N102965_2)); // LUT = I0&I1&I2&I3&I4 ; GTP_LUT5 /* N498_2 */ #( .INIT(32'b11111110111011101110111011101110)) N498_2 ( - .Z (_N102144_2), + .Z (_N102965_2), .I0 (trans_byte[3]), .I1 (trans_byte[2]), .I2 (trans_byte[1]), @@ -80124,19 +79762,19 @@ module iic_dri busy_vname ( .Q (busy), .CLK (clk), - .D (_N103285)); + .D (_N104097)); // defparam busy_vname.orig_name = busy; // ../../sources/designs/hdmi/ms72xx_ctrl/iic_dri.v:184 GTP_LUT5 /* busy_rs_mux */ #( .INIT(32'b11111111101000101111111110101010)) busy_rs_mux ( - .Z (_N103285), + .Z (_N104097), .I0 (busy), .I1 (twr_cnt[1]), .I2 (twr_cnt[0]), .I3 (start_en), - .I4 (_N104065)); + .I4 (_N104890)); // LUT = (I3)|(I0&~I4)|(I0&~I1)|(I0&I2) ; GTP_DFF /* byte_over */ #( @@ -80417,7 +80055,7 @@ module iic_dri sda_out_vname ( .Q (sda_out), .CLK (clk), - .D (_N103296), + .D (_N104108), .S (1'b0)); // defparam sda_out_vname.orig_name = sda_out; // ../../sources/designs/hdmi/ms72xx_ctrl/iic_dri.v:237 @@ -80425,13 +80063,13 @@ module iic_dri GTP_LUT5M /* sda_out_ce_mux */ #( .INIT(32'b10101010101010101111111111101010)) sda_out_ce_mux ( - .Z (_N103296), + .Z (_N104108), .I0 (sda_out), - .I1 (_N95846), - .I2 (_N103986), - .I3 (_N29346), + .I1 (_N96619), + .I2 (_N104811), + .I3 (_N29321), .I4 (N489), - .ID (_N104046)); + .ID (_N104871)); // LUT = (I3&~I4)|(I1&I2&~I4)|(ID&~I4)|(I0&I4) ; GTP_DFF_E /* \send_data[0] */ #( @@ -80520,14 +80158,14 @@ module iic_dri start_en_vname ( .Q (start_en), .CLK (clk), - .D (_N103488)); + .D (_N104300)); // defparam start_en_vname.orig_name = start_en; // ../../sources/designs/hdmi/ms72xx_ctrl/iic_dri.v:96 GTP_LUT5 /* start_en_rs_mux */ #( .INIT(32'b00100010001000100000000010100000)) start_en_rs_mux ( - .Z (_N103488), + .Z (_N104300), .I0 (rstn), .I1 (full_cycle), .I2 (pluse_2d), @@ -80550,7 +80188,7 @@ module iic_dri GTP_LUT2 /* \state_fsm[2:0]_7_2 */ #( .INIT(4'b1000)) \state_fsm[2:0]_7_2 ( - .Z (_N103986), + .Z (_N104811), .I0 (state_reg[3]), .I1 (dsu)); // LUT = I0&I1 ; @@ -80562,7 +80200,7 @@ module iic_dri .I0 (state_reg[3]), .I1 (state_reg[0]), .I2 (start), - .I3 (_N95846), + .I3 (_N96619), .I4 (dsu), .ID (state_reg[1])); // LUT = (ID&~I4)|(I0&I3&I4)|(I1&I2) ; @@ -80587,7 +80225,7 @@ module iic_dri .I1 (_N9), .I2 (state_reg[3]), .I3 (dsu), - .I4 (_N81608)); + .I4 (_N82374)); // LUT = (I1)|(I0&I3)|(I2&I3&I4) ; GTP_LUT5M /* \state_fsm[2:0]_19 */ #( @@ -80623,14 +80261,14 @@ module iic_dri .I0 (N519[6]), .I1 (state_reg[5]), .I2 (dsu), - .I3 (_N81582), - .I4 (_N81586)); + .I3 (_N82353), + .I4 (_N82357)); // LUT = (I3)|(I2&I4)|(I0&I1&I2) ; GTP_LUT5 /* \state_fsm[2:0]_31 */ #( .INIT(32'b01111111000000001111111100000000)) \state_fsm[2:0]_31 ( - .Z (_N81582), + .Z (_N82353), .I0 (trans_bit[2]), .I1 (trans_bit[1]), .I2 (trans_bit[0]), @@ -80641,7 +80279,7 @@ module iic_dri GTP_LUT4 /* \state_fsm[2:0]_39_3 */ #( .INIT(16'b0000000011100000)) \state_fsm[2:0]_39_3 ( - .Z (_N81586), + .Z (_N82357), .I0 (trans_byte[3]), .I1 (trans_byte[2]), .I2 (state_reg[3]), @@ -80655,7 +80293,7 @@ module iic_dri .I0 (N519[6]), .I1 (state_reg[5]), .I2 (w_r_2d), - .I3 (_N95852), + .I3 (_N96626), .I4 (dsu), .ID (state_reg[6])); // LUT = (ID&~I4)|(~I0&I2&I3&I4)|(~I0&I1&I4) ; @@ -80663,12 +80301,12 @@ module iic_dri GTP_LUT5 /* \state_fsm[2:0]_53 */ #( .INIT(32'b10101010000000001010101100000011)) \state_fsm[2:0]_53 ( - .Z (_N81608), + .Z (_N82374), .I0 (N519[6]), .I1 (trans_byte[3]), .I2 (trans_byte[2]), .I3 (w_r_2d), - .I4 (_N96754)); + .I4 (_N97518)); // LUT = (I0&I3)|(~I1&~I2&~I4) ; GTP_LUT4 /* \state_fsm[2:0]_70 */ #( @@ -80684,7 +80322,7 @@ module iic_dri GTP_LUT5 /* \state_fsm[2:0]_71 */ #( .INIT(32'b00000000000000000001000000000000)) \state_fsm[2:0]_71 ( - .Z (_N95846), + .Z (_N96619), .I0 (trans_byte[3]), .I1 (trans_byte[2]), .I2 (trans_byte[1]), @@ -80872,14 +80510,14 @@ module iic_dri trans_en_vname ( .Q (trans_en), .CLK (clk), - .D (_N103287)); + .D (_N104099)); // defparam trans_en_vname.orig_name = trans_en; // ../../sources/designs/hdmi/ms72xx_ctrl/iic_dri.v:146 GTP_LUT5 /* trans_en_rs_mux */ #( .INIT(32'b11010101111111111100000011000000)) trans_en_rs_mux ( - .Z (_N103287), + .Z (_N104099), .I0 (state_reg[6]), .I1 (full_cycle), .I2 (start_en), @@ -80933,14 +80571,14 @@ module iic_dri twr_en_vname ( .Q (twr_en), .CLK (clk), - .D (_N103289)); + .D (_N104101)); // defparam twr_en_vname.orig_name = twr_en; // ../../sources/designs/hdmi/ms72xx_ctrl/iic_dri.v:168 GTP_LUT5 /* twr_en_ce_mux */ #( .INIT(32'b11111111110111110000000000000000)) twr_en_ce_mux ( - .Z (_N103288), + .Z (_N104100), .I0 (twr_cnt[3]), .I1 (twr_cnt[2]), .I2 (twr_cnt[1]), @@ -80951,10 +80589,10 @@ module iic_dri GTP_LUT3 /* twr_en_rs_mux */ #( .INIT(8'b11111000)) twr_en_rs_mux ( - .Z (_N103289), + .Z (_N104101), .I0 (state_reg[6]), .I1 (dsu), - .I2 (_N103288)); + .I2 (_N104100)); // LUT = (I2)|(I0&I1) ; GTP_DFF_R /* w_r_1d */ #( @@ -80992,6 +80630,7 @@ module iic_dri_unq4 input [3:0] \ms72xx_ctl/iic_dri_rx/trans_byte , input N72, input _N9_rnms, + input _N96740, input clk, input dsu, input full_cycle, @@ -81002,9 +80641,11 @@ module iic_dri_unq4 input start_h, input w_r, output [7:0] data_out, + output [6:0] state_reg, output [2:0] trans_bit, + output [3:0] trans_byte, output N80, - output _N95852, + output _N96626, output busy, output byte_over, output scl, @@ -81041,27 +80682,26 @@ module iic_dri_unq4 wire _N17994; wire _N17995; wire _N17996; - wire _N19849; - wire _N19852; + wire _N19797; + wire _N19800; wire _N30831; - wire _N81617; - wire _N81621; - wire _N81641; - wire _N95847; - wire _N96238; - wire _N103291; - wire _N103293; - wire _N103294; - wire _N103295; - wire _N103297; - wire _N103490; - wire _N104381; - wire _N104416; - wire _N104421; - wire _N104427; - wire _N104432; - wire _N104434; - wire _N104463; + wire _N82383; + wire _N82387; + wire _N82418; + wire _N96620; + wire _N104103; + wire _N104105; + wire _N104106; + wire _N104107; + wire _N104109; + wire _N104302; + wire _N105220; + wire _N105255; + wire _N105260; + wire _N105266; + wire _N105271; + wire _N105273; + wire _N105300; wire pluse_1d; wire pluse_2d; wire pluse_3d; @@ -81069,8 +80709,6 @@ module iic_dri_unq4 wire [7:0] send_data; wire start; wire start_en; - wire [6:0] state_reg; - wire [3:0] trans_byte; wire [3:0] trans_byte_max; wire trans_en; wire [26:0] twr_cnt; @@ -81158,7 +80796,7 @@ module iic_dri_unq4 GTP_LUT5M /* N120_4 */ #( .INIT(32'b10101010111100001010101011001100)) N120_4 ( - .Z (_N19849), + .Z (_N19797), .I0 (send_data[0]), .I1 (send_data[6]), .I2 (send_data[4]), @@ -81170,7 +80808,7 @@ module iic_dri_unq4 GTP_LUT5M /* N120_7 */ #( .INIT(32'b10101010111100001010101011001100)) N120_7 ( - .Z (_N19852), + .Z (_N19800), .I0 (send_data[1]), .I1 (send_data[7]), .I2 (send_data[5]), @@ -81181,8 +80819,8 @@ module iic_dri_unq4 GTP_MUX2LUT6 N120_8 ( .Z (N120), - .I0 (_N19852), - .I1 (_N19849), + .I0 (_N19800), + .I1 (_N19797), .S (trans_bit[0])); GTP_LUT1 /* N132 */ #( @@ -81236,7 +80874,7 @@ module iic_dri_unq4 GTP_LUT5 /* N165_1 */ #( .INIT(32'b00000000000000000000000001000000)) N165_1 ( - .Z (_N95847), + .Z (_N96620), .I0 (w_r_2d), .I1 (trans_byte[0]), .I2 (trans_byte[1]), @@ -81317,7 +80955,7 @@ module iic_dri_unq4 GTP_LUT2 /* N345_2 */ #( .INIT(4'b0100)) N345_2 ( - .Z (_N104463), + .Z (_N105300), .I0 (twr_cnt[2]), .I1 (twr_cnt[3])); // LUT = ~I0&I1 ; @@ -81397,7 +81035,7 @@ module iic_dri_unq4 GTP_LUT5M /* \N461_8_or[0]_2 */ #( .INIT(32'b00000001000000000000001000000000)) \N461_8_or[0]_2 ( - .Z (_N104416), + .Z (_N105255), .I0 (w_r_2d), .I1 (start), .I2 (N177), @@ -81414,7 +81052,7 @@ module iic_dri_unq4 .I1 (data_in[0]), .I2 (_N17994), .I3 (_N17996), - .I4 (_N104416)); + .I4 (_N105255)); // LUT = (I4)|(I0&I2)|(I1&I3) ; GTP_LUT5 /* \N461_8_or[1][2] */ #( @@ -81431,7 +81069,7 @@ module iic_dri_unq4 GTP_LUT5M /* \N461_8_or[2]_2 */ #( .INIT(32'b00000000000000100000001000000000)) \N461_8_or[2]_2 ( - .Z (_N104421), + .Z (_N105260), .I0 (addr[2]), .I1 (start), .I2 (N177), @@ -81446,13 +81084,13 @@ module iic_dri_unq4 .Z (N461[2]), .I0 (data_in[2]), .I1 (_N17996), - .I2 (_N104421)); + .I2 (_N105260)); // LUT = (I2)|(I0&I1) ; GTP_LUT5M /* \N461_8_or[3]_2 */ #( .INIT(32'b00000000000000100000001000000000)) \N461_8_or[3]_2 ( - .Z (_N104427), + .Z (_N105266), .I0 (addr[3]), .I1 (start), .I2 (N177), @@ -81467,7 +81105,7 @@ module iic_dri_unq4 .Z (N461[3]), .I0 (data_in[3]), .I1 (_N17996), - .I2 (_N104427)); + .I2 (_N105266)); // LUT = (I2)|(I0&I1) ; GTP_LUT4 /* \N461_8_or[6] */ #( @@ -81515,7 +81153,7 @@ module iic_dri_unq4 GTP_LUT4 /* \N493_or[0]_3 */ #( .INIT(16'b1111111111111000)) \N493_or[0]_3 ( - .Z (_N104432), + .Z (_N105271), .I0 (start_h), .I1 (state_reg[6]), .I2 (state_reg[4]), @@ -81525,7 +81163,7 @@ module iic_dri_unq4 GTP_LUT5M /* \N493_or[0]_5 */ #( .INIT(32'b11100000111000001100000011101010)) \N493_or[0]_5 ( - .Z (_N104434), + .Z (_N105273), .I0 (state_reg[1]), .I1 (state_reg[2]), .I2 (N120), @@ -81574,19 +81212,19 @@ module iic_dri_unq4 busy_vname ( .Q (busy), .CLK (clk), - .D (_N103291)); + .D (_N104103)); // defparam busy_vname.orig_name = busy; // ../../sources/designs/hdmi/ms72xx_ctrl/iic_dri.v:184 GTP_LUT5 /* busy_rs_mux */ #( .INIT(32'b11101100111011101110111011101110)) busy_rs_mux ( - .Z (_N103291), + .Z (_N104103), .I0 (busy), .I1 (start_en), .I2 (twr_cnt[0]), .I3 (twr_cnt[1]), - .I4 (_N104463)); + .I4 (_N105300)); // LUT = (I1)|(I0&~I4)|(I0&~I3)|(I0&I2) ; GTP_DFF /* byte_over */ #( @@ -81817,7 +81455,7 @@ module iic_dri_unq4 sda_out_vname ( .Q (sda_out), .CLK (clk), - .D (_N103297), + .D (_N104109), .S (1'b0)); // defparam sda_out_vname.orig_name = sda_out; // ../../sources/designs/hdmi/ms72xx_ctrl/iic_dri.v:237 @@ -81825,13 +81463,13 @@ module iic_dri_unq4 GTP_LUT5M /* sda_out_ce_mux */ #( .INIT(32'b10101010101010101111111011111010)) sda_out_ce_mux ( - .Z (_N103297), + .Z (_N104109), .I0 (sda_out), - .I1 (_N104381), - .I2 (_N104432), + .I1 (_N105220), + .I2 (_N105271), .I3 (dsu), .I4 (N489), - .ID (_N104434)); + .ID (_N105273)); // LUT = (I1&I3&~I4)|(I2&~I4)|(ID&~I4)|(I0&I4) ; GTP_DFF_E /* \send_data[0] */ #( @@ -81920,14 +81558,14 @@ module iic_dri_unq4 start_en_vname ( .Q (start_en), .CLK (clk), - .D (_N103490)); + .D (_N104302)); // defparam start_en_vname.orig_name = start_en; // ../../sources/designs/hdmi/ms72xx_ctrl/iic_dri.v:96 GTP_LUT5 /* start_en_rs_mux */ #( .INIT(32'b00100010001000100000000010100000)) start_en_rs_mux ( - .Z (_N103490), + .Z (_N104302), .I0 (rstn), .I1 (full_cycle), .I2 (pluse_2d), @@ -81950,7 +81588,7 @@ module iic_dri_unq4 GTP_LUT5 /* \state_fsm[2:0]_7_2 */ #( .INIT(32'b00000100000000000000000000000000)) \state_fsm[2:0]_7_2 ( - .Z (_N104381), + .Z (_N105220), .I0 (N177), .I1 (state_reg[3]), .I2 (w_r_2d), @@ -81965,7 +81603,7 @@ module iic_dri_unq4 .I0 (state_reg[3]), .I1 (start), .I2 (state_reg[0]), - .I3 (_N95847), + .I3 (_N96620), .I4 (dsu), .ID (state_reg[1])); // LUT = (ID&~I4)|(I0&I3&I4)|(I1&I2) ; @@ -81990,7 +81628,7 @@ module iic_dri_unq4 .I1 (_N9), .I2 (state_reg[3]), .I3 (state_reg[1]), - .I4 (_N81641)); + .I4 (_N82418)); // LUT = (I1)|(I0&I3)|(I0&I2&I4) ; GTP_LUT5M /* \state_fsm[2:0]_19 */ #( @@ -82026,14 +81664,14 @@ module iic_dri_unq4 .I0 (dsu), .I1 (state_reg[5]), .I2 (N519_alias[6]), - .I3 (_N81617), - .I4 (_N81621)); + .I3 (_N82383), + .I4 (_N82387)); // LUT = (I3)|(I0&I4)|(I0&I1&I2) ; GTP_LUT5 /* \state_fsm[2:0]_31 */ #( .INIT(32'b01001100110011001100110011001100)) \state_fsm[2:0]_31 ( - .Z (_N81617), + .Z (_N82383), .I0 (dsu), .I1 (state_reg[4]), .I2 (trans_bit[0]), @@ -82044,7 +81682,7 @@ module iic_dri_unq4 GTP_LUT3 /* \state_fsm[2:0]_39_3 */ #( .INIT(8'b00001000)) \state_fsm[2:0]_39_3 ( - .Z (_N81621), + .Z (_N82387), .I0 (N177), .I1 (state_reg[3]), .I2 (w_r_2d)); @@ -82057,7 +81695,7 @@ module iic_dri_unq4 .I0 (state_reg[5]), .I1 (w_r_2d), .I2 (N519_alias[6]), - .I3 (_N96238), + .I3 (_N96740), .I4 (dsu), .ID (state_reg[6])); // LUT = (ID&~I4)|(I1&~I2&I3&I4)|(I0&~I2&I4) ; @@ -82065,7 +81703,7 @@ module iic_dri_unq4 GTP_LUT5 /* \state_fsm[2:0]_53 */ #( .INIT(32'b11000000110101011101010111010101)) \state_fsm[2:0]_53 ( - .Z (_N81641), + .Z (_N82418), .I0 (N177), .I1 (w_r_2d), .I2 (N519_alias[6]), @@ -82076,7 +81714,7 @@ module iic_dri_unq4 GTP_LUT5 /* \state_fsm[2:0]_70 */ #( .INIT(32'b11111110111011100000000000000000)) \state_fsm[2:0]_70 ( - .Z (_N95852), + .Z (_N96626), .I0 (\ms72xx_ctl/iic_dri_rx/trans_byte [3] ), .I1 (\ms72xx_ctl/iic_dri_rx/trans_byte [2] ), .I2 (\ms72xx_ctl/iic_dri_rx/trans_byte [1] ), @@ -82084,17 +81722,6 @@ module iic_dri_unq4 .I4 (\ms72xx_ctl/iic_dri_rx/state_reg [3] )); // LUT = (I0&I4)|(I1&I4)|(I2&I3&I4) ; - GTP_LUT5 /* \state_fsm[2:0]_71 */ #( - .INIT(32'b10101010101010101010101010000000)) - \state_fsm[2:0]_71 ( - .Z (_N96238), - .I0 (state_reg[3]), - .I1 (trans_byte[0]), - .I2 (trans_byte[1]), - .I3 (trans_byte[2]), - .I4 (trans_byte[3])); - // LUT = (I0&I3)|(I0&I4)|(I0&I1&I2) ; - (* syn_encoding="onehot" *) GTP_DFF_S /* \state_reg[0] */ #( .GRS_EN("TRUE"), .INIT(1'b1)) @@ -82275,14 +81902,14 @@ module iic_dri_unq4 trans_en_vname ( .Q (trans_en), .CLK (clk), - .D (_N103293)); + .D (_N104105)); // defparam trans_en_vname.orig_name = trans_en; // ../../sources/designs/hdmi/ms72xx_ctrl/iic_dri.v:146 GTP_LUT5 /* trans_en_rs_mux */ #( .INIT(32'b10111111001111111010101000000000)) trans_en_rs_mux ( - .Z (_N103293), + .Z (_N104105), .I0 (full_cycle), .I1 (start_h), .I2 (state_reg[6]), @@ -82336,14 +81963,14 @@ module iic_dri_unq4 twr_en_vname ( .Q (twr_en), .CLK (clk), - .D (_N103295)); + .D (_N104107)); // defparam twr_en_vname.orig_name = twr_en; // ../../sources/designs/hdmi/ms72xx_ctrl/iic_dri.v:168 GTP_LUT5 /* twr_en_ce_mux */ #( .INIT(32'b10101010100010101010101010101010)) twr_en_ce_mux ( - .Z (_N103294), + .Z (_N104106), .I0 (twr_en), .I1 (twr_cnt[0]), .I2 (twr_cnt[1]), @@ -82354,10 +81981,10 @@ module iic_dri_unq4 GTP_LUT3 /* twr_en_rs_mux */ #( .INIT(8'b11111000)) twr_en_rs_mux ( - .Z (_N103295), + .Z (_N104107), .I0 (dsu), .I1 (state_reg[6]), - .I2 (_N103294)); + .I2 (_N104106)); // LUT = (I2)|(I0&I1) ; GTP_DFF_R /* w_r_1d */ #( @@ -82404,7 +82031,7 @@ module ms7200_ctl output [15:0] \ms72xx_ctl/addr_rx , output [6:0] state, output N1918, - output _N96143, + output _N96633, output iic_trig, output init_over, output w_r @@ -82414,6 +82041,7 @@ module ms7200_ctl wire N176; wire N261; wire N1321; + wire N1359; wire N1366; wire N1386; wire N1388; @@ -82422,6 +82050,7 @@ module ms7200_ctl wire [8:0] N1844; wire N1845; wire N1872; + wire N1873; wire N1879; wire [8:0] N1894; wire N1895; @@ -82438,13 +82067,13 @@ module ms7200_ctl wire N2083; wire N2085; wire [4:0] N2093; - wire _N13804; - wire _N13805; - wire _N13806; - wire _N13807; - wire _N13808; - wire _N13809; - wire _N13810; + wire _N13822; + wire _N13823; + wire _N13824; + wire _N13825; + wire _N13826; + wire _N13827; + wire _N13828; wire _N17170; wire _N17171; wire _N17172; @@ -82453,37 +82082,37 @@ module ms7200_ctl wire _N17175; wire _N17176; wire _N17177; - wire _N18000; - wire _N18002; - wire _N38814; - wire _N38839; - wire _N38866; - wire _N38901; - wire _N38948; - wire _N39000; - wire _N39062; - wire _N39102; - wire _N84747; - wire _N95810; - wire _N95853; - wire _N95857; - wire _N95866; - wire _N96041; - wire _N96431; - wire _N96695; - wire _N100381; - wire _N103298; - wire _N103299; - wire _N103492; - wire _N103976; - wire _N103981; - wire _N104002; - wire _N104013; - wire _N104061; - wire _N104063; - wire _N104071; - wire _N104076; - wire _N104081; + wire _N36149; + wire _N36175; + wire _N36201; + wire _N36237; + wire _N36285; + wire _N36328; + wire _N36395; + wire _N36413; + wire _N36448; + wire _N36470; + wire _N96603; + wire _N96627; + wire _N96632; + wire _N96696; + wire _N96761; + wire _N97453; + wire _N104110; + wire _N104111; + wire _N104304; + wire _N104787; + wire _N104790; + wire _N104793; + wire _N104806; + wire _N104827; + wire _N104838; + wire _N104861; + wire _N104886; + wire _N104888; + wire _N104896; + wire _N104901; + wire _N104906; wire busy_1d; wire busy_falling; wire [23:0] cmd_iic; @@ -82523,7 +82152,7 @@ module ms7200_ctl GTP_LUT3 /* N8_3 */ #( .INIT(8'b00000001)) N8_3 ( - .Z (_N95853), + .Z (_N96627), .I0 (dri_cnt[4]), .I1 (dri_cnt[6]), .I2 (dri_cnt[7])); @@ -82532,7 +82161,7 @@ module ms7200_ctl GTP_LUT5 /* N8_5 */ #( .INIT(32'b00000000000000000000010000000000)) N8_5 ( - .Z (_N104076), + .Z (_N104901), .I0 (busy), .I1 (busy_1d), .I2 (state[2]), @@ -82548,13 +82177,13 @@ module ms7200_ctl .I1 (dri_cnt[0]), .I2 (dri_cnt[1]), .I3 (state_n[1]), - .I4 (_N104076)); + .I4 (_N104901)); // LUT = I0&~I1&I2&~I3&I4 ; GTP_LUT4 /* N24_4 */ #( .INIT(16'b0000000000000100)) N24_4 ( - .Z (_N104081), + .Z (_N104906), .I0 (freq_rec_1d[16]), .I1 (freq_rec_1d[17]), .I2 (freq_rec_2d[16]), @@ -82564,7 +82193,7 @@ module ms7200_ctl GTP_LUT4 /* N40_6 */ #( .INIT(16'b1000000000000000)) N40_6 ( - .Z (_N104061), + .Z (_N104886), .I0 (data_out[1]), .I1 (data_out[3]), .I2 (data_out[4]), @@ -82574,12 +82203,12 @@ module ms7200_ctl GTP_LUT5 /* N40_8 */ #( .INIT(32'b00000000000000010000000000000000)) N40_8 ( - .Z (_N104063), + .Z (_N104888), .I0 (data_out[0]), .I1 (data_out[2]), .I2 (data_out[5]), .I3 (data_out[7]), - .I4 (_N104061)); + .I4 (_N104886)); // LUT = ~I0&~I1&~I2&~I3&I4 ; GTP_LUT5 /* N40_9 */ #( @@ -82590,7 +82219,7 @@ module ms7200_ctl .I1 (busy_falling), .I2 (dri_cnt[0]), .I3 (dri_cnt[1]), - .I4 (_N104063)); + .I4 (_N104888)); // LUT = I0&I1&I2&~I3&I4 ; GTP_LUT5 /* N63_5 */ #( @@ -82611,7 +82240,7 @@ module ms7200_ctl .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N101_1_1 ( - .COUT (_N13804), + .COUT (_N13822), .Z (N101[1]), .CIN (), .I0 (dri_cnt[0]), @@ -82631,9 +82260,9 @@ module ms7200_ctl .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N101_1_2 ( - .COUT (_N13805), + .COUT (_N13823), .Z (N101[2]), - .CIN (_N13804), + .CIN (_N13822), .I0 (dri_cnt[0]), .I1 (dri_cnt[1]), .I2 (dri_cnt[2]), @@ -82651,9 +82280,9 @@ module ms7200_ctl .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N101_1_3 ( - .COUT (_N13806), + .COUT (_N13824), .Z (N101[3]), - .CIN (_N13805), + .CIN (_N13823), .I0 (), .I1 (dri_cnt[3]), .I2 (), @@ -82671,9 +82300,9 @@ module ms7200_ctl .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N101_1_4 ( - .COUT (_N13807), + .COUT (_N13825), .Z (N101[4]), - .CIN (_N13806), + .CIN (_N13824), .I0 (), .I1 (dri_cnt[4]), .I2 (), @@ -82691,9 +82320,9 @@ module ms7200_ctl .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N101_1_5 ( - .COUT (_N13808), + .COUT (_N13826), .Z (N101[5]), - .CIN (_N13807), + .CIN (_N13825), .I0 (), .I1 (dri_cnt[5]), .I2 (), @@ -82711,9 +82340,9 @@ module ms7200_ctl .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N101_1_6 ( - .COUT (_N13809), + .COUT (_N13827), .Z (N101[6]), - .CIN (_N13808), + .CIN (_N13826), .I0 (), .I1 (dri_cnt[6]), .I2 (), @@ -82731,9 +82360,9 @@ module ms7200_ctl .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N101_1_7 ( - .COUT (_N13810), + .COUT (_N13828), .Z (N101[7]), - .CIN (_N13809), + .CIN (_N13827), .I0 (), .I1 (dri_cnt[7]), .I2 (), @@ -82753,7 +82382,7 @@ module ms7200_ctl N101_1_8 ( .COUT (), .Z (N101[8]), - .CIN (_N13810), + .CIN (_N13828), .I0 (), .I1 (dri_cnt[8]), .I2 (), @@ -83063,6 +82692,17 @@ module ms7200_ctl .WEA (1'b0), .WEB (1'b0)); + GTP_LUT3 /* N1359 */ #( + .INIT(8'b00001000)) + N1359_vname ( + .Z (N1359), + .I0 (N261), + .I1 (dri_cnt[0]), + .I2 (dri_cnt[1])); + // defparam N1359_vname.orig_name = N1359; + // LUT = I0&I1&~I2 ; + // ../../sources/designs/hdmi/ms72xx_ctrl/ms7200_ctl.v:420 + GTP_LUT3 /* N1359_1 */ #( .INIT(8'b10000000)) N1359_1 ( @@ -83073,26 +82713,26 @@ module ms7200_ctl // LUT = I0&I1&I2 ; GTP_LUT5 /* N1366_5 */ #( - .INIT(32'b00000000000000010000000000000000)) + .INIT(32'b00000000000000000000000000001000)) N1366_5 ( - .Z (_N104071), - .I0 (dri_cnt[2]), - .I1 (dri_cnt[4]), - .I2 (dri_cnt[6]), - .I3 (dri_cnt[7]), - .I4 (dri_cnt[8])); - // LUT = ~I0&~I1&~I2&~I3&I4 ; + .Z (_N104896), + .I0 (dri_cnt[0]), + .I1 (dri_cnt[1]), + .I2 (dri_cnt[4]), + .I3 (dri_cnt[6]), + .I4 (dri_cnt[7])); + // LUT = I0&I1&~I2&~I3&~I4 ; GTP_LUT5 /* N1366_6 */ #( - .INIT(32'b10000000000000000000000000000000)) + .INIT(32'b01000000000000000000000000000000)) N1366_6 ( .Z (N1366), - .I0 (dri_cnt[0]), - .I1 (dri_cnt[1]), - .I2 (dri_cnt[3]), - .I3 (dri_cnt[5]), - .I4 (_N104071)); - // LUT = I0&I1&I2&I3&I4 ; + .I0 (dri_cnt[2]), + .I1 (dri_cnt[3]), + .I2 (dri_cnt[5]), + .I3 (dri_cnt[8]), + .I4 (_N104896)); + // LUT = ~I0&I1&I2&I3&I4 ; GTP_LUT4 /* N1388 */ #( .INIT(16'b0100000000000000)) @@ -83101,7 +82741,7 @@ module ms7200_ctl .I0 (dri_cnt[0]), .I1 (dri_cnt[1]), .I2 (dri_cnt[2]), - .I3 (_N95857)); + .I3 (_N96632)); // defparam N1388_vname.orig_name = N1388; // LUT = ~I0&I1&I2&I3 ; // ../../sources/designs/hdmi/ms72xx_ctrl/ms7200_ctl.v:439 @@ -83119,91 +82759,17 @@ module ms7200_ctl // LUT = (~I0)|(~I1&~I2&~I3&I4) ; // ../../sources/designs/hdmi/ms72xx_ctrl/ms7200_ctl.v:393 - GTP_LUT4 /* N1844_2 */ #( - .INIT(16'b0001000000000000)) - N1844_2 ( - .Z (_N18000), + GTP_LUT4 /* N1844_1 */ #( + .INIT(16'b0100000000000000)) + N1844_1 ( + .Z (N1873), .I0 (busy), .I1 (N1366), .I2 (busy_1d), .I3 (state[2])); - // LUT = ~I0&~I1&I2&I3 ; + // LUT = ~I0&I1&I2&I3 ; // ../../sources/designs/hdmi/ms72xx_ctrl/ms7200_ctl.v:457 - GTP_LUT4 /* N1844_5_1 */ #( - .INIT(16'b0001000000000000)) - N1844_5_1 ( - .Z (_N18002), - .I0 (busy), - .I1 (N1388), - .I2 (busy_1d), - .I3 (state[5])); - // LUT = ~I0&~I1&I2&I3 ; - - GTP_LUT3 /* N1844_5_2 */ #( - .INIT(8'b01000000)) - N1844_5_2 ( - .Z (_N100381), - .I0 (busy), - .I1 (busy_1d), - .I2 (state[5])); - // LUT = ~I0&I1&I2 ; - - GTP_LUT5 /* \N1844_7_or[1]_1 */ #( - .INIT(32'b10101010101010101010101010101000)) - \N1844_7_or[1]_1 ( - .Z (N1844[1]), - .I0 (N101[1]), - .I1 (_N18000), - .I2 (_N18002), - .I3 (_N84747), - .I4 (_N103976)); - // LUT = (I0&I1)|(I0&I2)|(I0&I3)|(I0&I4) ; - - GTP_LUT5 /* \N1844_7_or[1]_2_2 */ #( - .INIT(32'b01010000010100000100000000000000)) - \N1844_7_or[1]_2_2 ( - .Z (_N103976), - .I0 (busy), - .I1 (N1366), - .I2 (busy_1d), - .I3 (state[2]), - .I4 (state[4])); - // LUT = (~I0&I2&I4)|(~I0&I1&I2&I3) ; - - GTP_LUT5 /* \N1844_7_or[1]_3 */ #( - .INIT(32'b11001100010011000000000000000000)) - \N1844_7_or[1]_3 ( - .Z (_N84747), - .I0 (N261), - .I1 (busy_falling), - .I2 (dri_cnt[0]), - .I3 (dri_cnt[1]), - .I4 (state[1])); - // LUT = (I1&~I2&I4)|(~I0&I1&I4)|(I1&I3&I4) ; - - GTP_LUT5 /* \N1844_7_or[1]_5 */ #( - .INIT(32'b00111011000000000000101000000000)) - \N1844_7_or[1]_5 ( - .Z (_N96143), - .I0 (\ms72xx_ctl/ms7210_ctl/state_reg [4] ), - .I1 (\ms72xx_ctl/ms7210_ctl/N390 ), - .I2 (\ms72xx_ctl/ms7210_ctl/N405 ), - .I3 (\ms72xx_ctl/ms7210_ctl/busy_falling ), - .I4 (\ms72xx_ctl/ms7210_ctl/state_reg [2] )); - // LUT = (I0&~I2&I3)|(~I1&I3&I4) ; - - GTP_LUT5 /* \N1844_7_or[2]_1 */ #( - .INIT(32'b11110000111100000100000000000000)) - \N1844_7_or[2]_1 ( - .Z (N1844[2]), - .I0 (N1386), - .I1 (busy_falling), - .I2 (N101[2]), - .I3 (state[4]), - .I4 (_N95866)); - // LUT = (I2&I4)|(~I0&I1&I2&I3) ; - GTP_LUT5 /* \N1844_7_or[3]_1 */ #( .INIT(32'b11110000111100001110000010100000)) \N1844_7_or[3]_1 ( @@ -83211,32 +82777,32 @@ module ms7200_ctl .I0 (N1321), .I1 (busy_falling), .I2 (N101[3]), - .I3 (state[4]), - .I4 (_N95866)); + .I3 (state[1]), + .I4 (_N96603)); // LUT = (I0&I2)|(I2&I4)|(I1&I2&I3) ; - GTP_LUT5 /* \N1844_7_or[6]_1 */ #( - .INIT(32'b11001100110011001100110010000000)) - \N1844_7_or[6]_1 ( - .Z (N1844[6]), - .I0 (busy_falling), - .I1 (N101[6]), - .I2 (state[4]), - .I3 (_N95810), - .I4 (_N95866)); - // LUT = (I1&I3)|(I1&I4)|(I0&I1&I2) ; - GTP_LUT5 /* \N1844_7_or[7]_1 */ #( .INIT(32'b11001100110011001100110010000000)) \N1844_7_or[7]_1 ( .Z (N1844[7]), .I0 (busy_falling), .I1 (N101[7]), - .I2 (state[4]), - .I3 (_N95810), - .I4 (_N95866)); + .I2 (state[1]), + .I3 (_N96603), + .I4 (_N96696)); // LUT = (I1&I3)|(I1&I4)|(I0&I1&I2) ; + GTP_LUT5 /* \N1844_7_or[8]_1 */ #( + .INIT(32'b11110000111100001110000010100000)) + \N1844_7_or[8]_1 ( + .Z (N1844[8]), + .I0 (N1321), + .I1 (busy_falling), + .I2 (N101[8]), + .I3 (state[1]), + .I4 (_N96603)); + // LUT = (I0&I2)|(I2&I4)|(I1&I2&I3) ; + GTP_LUT5 /* N1845_1 */ #( .INIT(32'b10101010101010101010101010101011)) N1845_1 ( @@ -83248,22 +82814,14 @@ module ms7200_ctl .I4 (state[5])); // LUT = (I0)|(~I1&~I2&~I3&~I4) ; - GTP_LUT2 /* N1845_3 */ #( - .INIT(4'b1000)) - N1845_3 ( - .Z (_N96431), - .I0 (N261), - .I1 (state[4])); - // LUT = I0&I1 ; - GTP_LUT4 /* N1872_5 */ #( .INIT(16'b0000000100000000)) N1872_5 ( - .Z (_N95857), + .Z (_N96632), .I0 (dri_cnt[3]), .I1 (dri_cnt[5]), .I2 (dri_cnt[8]), - .I3 (_N95853)); + .I3 (_N96627)); // LUT = ~I0&~I1&~I2&I3 ; GTP_LUT4 /* N1872_7 */ #( @@ -83288,9 +82846,20 @@ module ms7200_ctl // ../../sources/designs/hdmi/ms72xx_ctrl/ms7200_ctl.v:517 GTP_LUT5 /* N1879_5 */ #( - .INIT(32'b01111111001111110101111100000000)) + .INIT(32'b00111011000000000000101000000000)) N1879_5 ( - .Z (_N103981), + .Z (_N96633), + .I0 (\ms72xx_ctl/ms7210_ctl/state_reg [4] ), + .I1 (\ms72xx_ctl/ms7210_ctl/N390 ), + .I2 (\ms72xx_ctl/ms7210_ctl/N405 ), + .I3 (\ms72xx_ctl/ms7210_ctl/busy_falling ), + .I4 (\ms72xx_ctl/ms7210_ctl/state_reg [2] )); + // LUT = (I0&~I2&I3)|(~I1&I3&I4) ; + + GTP_LUT5 /* N1879_9 */ #( + .INIT(32'b01111111001111110101111100000000)) + N1879_9 ( + .Z (_N104806), .I0 (N1366), .I1 (N1388), .I2 (busy_falling), @@ -83298,14 +82867,14 @@ module ms7200_ctl .I4 (state[5])); // LUT = (~I2&I3)|(~I2&I4)|(~I1&I4)|(~I0&I3) ; - GTP_LUT4 /* N1879_7 */ #( + GTP_LUT4 /* N1879_11 */ #( .INIT(16'b1111111110111010)) - N1879_7 ( + N1879_11 ( .Z (N1879), .I0 (N1872), .I1 (N2093[2]), .I2 (state[4]), - .I3 (_N103981)); + .I3 (_N104806)); // LUT = (I0)|(I3)|(~I1&I2) ; GTP_LUT3 /* \N1894_1[0]_1 */ #( @@ -83360,15 +82929,13 @@ module ms7200_ctl // defparam N1953_vname.orig_name = N1953; // LUT = (I2)|(I0&I1) ; - GTP_LUT4 /* \N1954_1_and[2]_1 */ #( - .INIT(16'b1111010011110000)) + GTP_LUT2 /* \N1954_1_and[2]_1 */ #( + .INIT(4'b1110)) \N1954_1_and[2]_1 ( - .Z (_N96041), - .I0 (busy), - .I1 (busy_1d), - .I2 (state[1]), - .I3 (state[4])); - // LUT = (I2)|(~I0&I1&I3) ; + .Z (_N96696), + .I0 (N1321), + .I1 (N1873)); + // LUT = (I0)|(I1) ; GTP_LUT5 /* \N1954_1_inv[2] */ #( .INIT(32'b00000000000000000101000111110011)) @@ -83378,7 +82945,7 @@ module ms7200_ctl .I1 (N1953), .I2 (cmd_iic[10]), .I3 (state[5]), - .I4 (_N96695)); + .I4 (_N97453)); // LUT = (~I1&~I3&~I4)|(I2&~I3&~I4)|(~I0&~I1&~I4)|(~I0&I2&~I4) ; GTP_LUT4 /* \N1954_1_inv[4] */ #( @@ -83388,13 +82955,23 @@ module ms7200_ctl .I0 (N1953), .I1 (N2083), .I2 (cmd_iic[12]), - .I3 (_N96695)); + .I3 (_N97453)); // LUT = (~I0&~I1&~I3)|(~I1&I2&~I3) ; + GTP_LUT4 /* \N1954_1_or[0]_1 */ #( + .INIT(16'b1111111101000000)) + \N1954_1_or[0]_1 ( + .Z (_N96603), + .I0 (busy), + .I1 (busy_1d), + .I2 (state[4]), + .I3 (_N96761)); + // LUT = (I3)|(~I0&I1&I2) ; + GTP_LUT5 /* \N1954_1_or[0]_6 */ #( .INIT(32'b11111111111011001111111111001100)) \N1954_1_or[0]_6 ( - .Z (_N104013), + .Z (_N104838), .I0 (N261), .I1 (N2085), .I2 (dri_cnt[0]), @@ -83408,19 +82985,27 @@ module ms7200_ctl .Z (N1954[0]), .I0 (N1953), .I1 (cmd_iic[8]), - .I2 (_N104013)); + .I2 (_N104838)); // LUT = (I2)|(I0&I1) ; - GTP_LUT5 /* \N1954_1_or[1]_6 */ #( - .INIT(32'b11111111111110001111111110001000)) + GTP_LUT4 /* \N1954_1_or[1]_6 */ #( + .INIT(16'b1111100011110000)) \N1954_1_or[1]_6 ( + .Z (_N104861), + .I0 (N261), + .I1 (dri_cnt[1]), + .I2 (state[0]), + .I3 (state[4])); + // LUT = (I2)|(I0&I1&I3) ; + + GTP_LUT3 /* \N1954_1_or[1]_7 */ #( + .INIT(8'b11111000)) + \N1954_1_or[1]_7 ( .Z (N1954[1]), .I0 (N1953), .I1 (cmd_iic[9]), - .I2 (dri_cnt[1]), - .I3 (state[0]), - .I4 (_N96431)); - // LUT = (I3)|(I0&I1)|(I2&I4) ; + .I2 (_N104861)); + // LUT = (I2)|(I0&I1) ; GTP_LUT4 /* \N1954_1_or[3] */ #( .INIT(16'b1110101011000000)) @@ -83462,17 +83047,6 @@ module ms7200_ctl .I4 (state[5])); // LUT = (I2)|(I0&I3)|(I1&I4) ; - GTP_LUT5 /* \N1954_1_or[10]_3 */ #( - .INIT(32'b11111101111111001111010111110000)) - \N1954_1_or[10]_3 ( - .Z (_N96695), - .I0 (N261), - .I1 (N2070), - .I2 (state[0]), - .I3 (state[4]), - .I4 (state[5])); - // LUT = (I2)|(~I0&I3)|(I1&I4) ; - GTP_LUT5 /* \N1954_1_or[10]_5 */ #( .INIT(32'b11111110111110101111110011110000)) \N1954_1_or[10]_5 ( @@ -83506,12 +83080,12 @@ module ms7200_ctl GTP_LUT5 /* \N1989_1_or[0]_4 */ #( .INIT(32'b00110001000000000000000000000000)) \N1989_1_or[0]_4 ( - .Z (_N104002), + .Z (_N104827), .I0 (dri_cnt[0]), .I1 (dri_cnt[1]), .I2 (dri_cnt[2]), .I3 (state[5]), - .I4 (_N95857)); + .I4 (_N96632)); // LUT = (~I0&~I1&I3&I4)|(~I1&I2&I3&I4) ; GTP_LUT3 /* \N1989_1_or[0]_5 */ #( @@ -83520,7 +83094,7 @@ module ms7200_ctl .Z (N1989[0]), .I0 (N1953), .I1 (cmd_iic[0]), - .I2 (_N104002)); + .I2 (_N104827)); // LUT = (I2)|(I0&I1) ; GTP_LUT4 /* \N1989_1_or[1]_5 */ #( @@ -83553,6 +83127,17 @@ module ms7200_ctl .I4 (state[5])); // LUT = (I3)|(I0&I4)|(I1&I2) ; + GTP_LUT5 /* \N1989_1_or[4]_3 */ #( + .INIT(32'b11111101111111001111010111110000)) + \N1989_1_or[4]_3 ( + .Z (_N97453), + .I0 (N261), + .I1 (N2070), + .I2 (state[0]), + .I3 (state[4]), + .I4 (state[5])); + // LUT = (I2)|(~I0&I3)|(I1&I4) ; + GTP_LUT4 /* \N1989_1_or[5] */ #( .INIT(16'b1110101011000000)) \N1989_1_or[5] ( @@ -83574,17 +83159,6 @@ module ms7200_ctl .I4 (state[5])); // LUT = (I3)|(I0&I4)|(I1&I2) ; - GTP_LUT5 /* \N1989_1_or[6]_1 */ #( - .INIT(32'b11100000110000001010000000000000)) - \N1989_1_or[6]_1 ( - .Z (_N95810), - .I0 (N1366), - .I1 (N1388), - .I2 (busy_falling), - .I3 (state[2]), - .I4 (state[5])); - // LUT = (I0&I2&I3)|(I1&I2&I4) ; - GTP_LUT5 /* N2009 */ #( .INIT(32'b10000000000000000000000000000000)) N2009 ( @@ -83623,7 +83197,7 @@ module ms7200_ctl N2053_1 ( .Z (N261), .I0 (dri_cnt[2]), - .I1 (_N95857)); + .I1 (_N96632)); // LUT = ~I0&I1 ; GTP_LUT4 /* N2071_1 */ #( @@ -83633,7 +83207,7 @@ module ms7200_ctl .I0 (dri_cnt[0]), .I1 (dri_cnt[1]), .I2 (dri_cnt[2]), - .I3 (_N95857)); + .I3 (_N96632)); // LUT = (~I0&I1&~I2&I3)|(~I0&~I1&I2&I3) ; GTP_LUT5 /* N2076 */ #( @@ -83644,7 +83218,7 @@ module ms7200_ctl .I1 (dri_cnt[1]), .I2 (dri_cnt[2]), .I3 (state[5]), - .I4 (_N95857)); + .I4 (_N96632)); // defparam N2076_vname.orig_name = N2076; // LUT = ~I0&~I1&I2&I3&I4 ; // ../../sources/designs/hdmi/ms72xx_ctrl/ms7200_ctl.v:615 @@ -83676,7 +83250,7 @@ module ms7200_ctl .I1 (dri_cnt[1]), .I2 (dri_cnt[2]), .I3 (state[5]), - .I4 (_N95857)); + .I4 (_N96632)); // defparam N2085_vname.orig_name = N2085; // LUT = (I3&~I4)|(I0&I2&I3)|(I1&I2&I3) ; // ../../sources/designs/hdmi/ms72xx_ctrl/ms7200_ctl.v:615 @@ -83754,7 +83328,7 @@ module ms7200_ctl .Q (addr[6]), .CE (N1955), .CLK (clk), - .D (_N38814), + .D (_N36149), .R (\ms72xx_ctl/iic_dri_rx/N0_1 )); // ../../sources/designs/hdmi/ms72xx_ctrl/ms7200_ctl.v:610 @@ -83776,7 +83350,7 @@ module ms7200_ctl .Q (\ms72xx_ctl/addr_rx [8] ), .CE (N1955), .CLK (clk), - .D (_N38839), + .D (_N36175), .R (\ms72xx_ctl/iic_dri_rx/N0_1 )); // ../../sources/designs/hdmi/ms72xx_ctrl/ms7200_ctl.v:610 @@ -83816,7 +83390,7 @@ module ms7200_ctl GTP_LUT3 /* \addr[15:0]_0 */ #( .INIT(8'b10101000)) \addr[15:0]_0 ( - .Z (_N38814), + .Z (_N36149), .I0 (cmd_iic[14]), .I1 (state[1]), .I2 (state[2])); @@ -83825,7 +83399,7 @@ module ms7200_ctl GTP_LUT3 /* \addr[15:0]_2 */ #( .INIT(8'b10101000)) \addr[15:0]_2 ( - .Z (_N38839), + .Z (_N36175), .I0 (cmd_iic[16]), .I1 (state[1]), .I2 (state[2])); @@ -83980,7 +83554,7 @@ module ms7200_ctl .Q (data_in[3]), .CE (N1955), .CLK (clk), - .D (_N38866), + .D (_N36201), .R (\ms72xx_ctl/iic_dri_rx/N0_1 )); // ../../sources/designs/hdmi/ms72xx_ctrl/ms7200_ctl.v:610 @@ -84020,7 +83594,7 @@ module ms7200_ctl GTP_LUT4 /* \data_in[7:0]_0 */ #( .INIT(16'b1110111011101100)) \data_in[7:0]_0 ( - .Z (_N38866), + .Z (_N36201), .I0 (cmd_iic[3]), .I1 (state[0]), .I2 (state[1]), @@ -84030,7 +83604,7 @@ module ms7200_ctl GTP_LUT3 /* \data_in[7:0]_3 */ #( .INIT(8'b10101000)) \data_in[7:0]_3 ( - .Z (_N38901), + .Z (_N36237), .I0 (cmd_iic[7]), .I1 (state[1]), .I2 (state[2])); @@ -84043,7 +83617,7 @@ module ms7200_ctl .Q (data_in[7]), .CE (N1955), .CLK (clk), - .D (_N38901), + .D (_N36237), .R (\ms72xx_ctl/iic_dri_rx/N0_1 )); // ../../sources/designs/hdmi/ms72xx_ctrl/ms7200_ctl.v:610 @@ -84054,7 +83628,7 @@ module ms7200_ctl .Q (dri_cnt[0]), .CE (N1845), .CLK (clk), - .D (_N38948), + .D (_N36285), .R (\ms72xx_ctl/iic_dri_rx/N0_1 )); // ../../sources/designs/hdmi/ms72xx_ctrl/ms7200_ctl.v:454 @@ -84065,7 +83639,7 @@ module ms7200_ctl .Q (dri_cnt[1]), .CE (N1845), .CLK (clk), - .D (N1844[1]), + .D (_N36328), .R (\ms72xx_ctl/iic_dri_rx/N0_1 )); // ../../sources/designs/hdmi/ms72xx_ctrl/ms7200_ctl.v:454 @@ -84076,7 +83650,7 @@ module ms7200_ctl .Q (dri_cnt[2]), .CE (N1845), .CLK (clk), - .D (N1844[2]), + .D (_N36395), .R (\ms72xx_ctl/iic_dri_rx/N0_1 )); // ../../sources/designs/hdmi/ms72xx_ctrl/ms7200_ctl.v:454 @@ -84098,7 +83672,7 @@ module ms7200_ctl .Q (dri_cnt[4]), .CE (N1845), .CLK (clk), - .D (_N39000), + .D (_N36413), .R (\ms72xx_ctl/iic_dri_rx/N0_1 )); // ../../sources/designs/hdmi/ms72xx_ctrl/ms7200_ctl.v:454 @@ -84109,7 +83683,7 @@ module ms7200_ctl .Q (dri_cnt[5]), .CE (N1845), .CLK (clk), - .D (_N39062), + .D (_N36448), .R (\ms72xx_ctl/iic_dri_rx/N0_1 )); // ../../sources/designs/hdmi/ms72xx_ctrl/ms7200_ctl.v:454 @@ -84120,7 +83694,7 @@ module ms7200_ctl .Q (dri_cnt[6]), .CE (N1845), .CLK (clk), - .D (N1844[6]), + .D (_N36470), .R (\ms72xx_ctl/iic_dri_rx/N0_1 )); // ../../sources/designs/hdmi/ms72xx_ctrl/ms7200_ctl.v:454 @@ -84136,59 +83710,110 @@ module ms7200_ctl // ../../sources/designs/hdmi/ms72xx_ctrl/ms7200_ctl.v:454 GTP_LUT5 /* \dri_cnt[8:0]_0 */ #( - .INIT(32'b10101010101010101010101010101000)) + .INIT(32'b11001100110011001100010011000000)) \dri_cnt[8:0]_0 ( - .Z (_N39000), - .I0 (N101[4]), - .I1 (_N18000), - .I2 (_N18002), - .I3 (_N95810), - .I4 (_N96041)); - // LUT = (I0&I1)|(I0&I2)|(I0&I3)|(I0&I4) ; + .Z (_N36395), + .I0 (N1386), + .I1 (N101[2]), + .I2 (state[1]), + .I3 (state[4]), + .I4 (_N96761)); + // LUT = (I1&I2)|(I1&I4)|(~I0&I1&I3) ; - GTP_LUT5 /* \dri_cnt[8:0]_1 */ #( - .INIT(32'b11001100110011001100110011001000)) + GTP_LUT4 /* \dri_cnt[8:0]_1 */ #( + .INIT(16'b1100110011001000)) \dri_cnt[8:0]_1 ( - .Z (_N39062), + .Z (_N36413), .I0 (N1321), - .I1 (N101[5]), - .I2 (_N18000), - .I3 (_N18002), - .I4 (_N96041)); - // LUT = (I0&I1)|(I1&I2)|(I1&I3)|(I1&I4) ; - - GTP_LUT5 /* \dri_cnt[8:0]_112 */ #( - .INIT(32'b10101010101010101010101010101000)) - \dri_cnt[8:0]_112 ( - .Z (_N39102), - .I0 (N101[8]), - .I1 (state[1]), - .I2 (state[4]), - .I3 (_N18000), - .I4 (_N100381)); - // LUT = (I0&I1)|(I0&I2)|(I0&I3)|(I0&I4) ; + .I1 (N101[4]), + .I2 (_N96761), + .I3 (_N104793)); + // LUT = (I0&I1)|(I1&I2)|(I1&I3) ; + + GTP_LUT5 /* \dri_cnt[8:0]_4 */ #( + .INIT(32'b01110000001100000101000000000000)) + \dri_cnt[8:0]_4 ( + .Z (_N96761), + .I0 (N1366), + .I1 (N1388), + .I2 (busy_falling), + .I3 (state[2]), + .I4 (state[5])); + // LUT = (~I1&I2&I4)|(~I0&I2&I3) ; - GTP_LUT5 /* \dri_cnt[8:0]_130 */ #( - .INIT(32'b11111111111111111100010011000000)) - \dri_cnt[8:0]_130 ( - .Z (_N95866), - .I0 (N1388), + GTP_LUT5 /* \dri_cnt[8:0]_6 */ #( + .INIT(32'b11110000111100000100000000000000)) + \dri_cnt[8:0]_6 ( + .Z (_N36448), + .I0 (N1366), .I1 (busy_falling), + .I2 (N101[5]), + .I3 (state[2]), + .I4 (_N104790)); + // LUT = (I2&I4)|(~I0&I1&I2&I3) ; + + GTP_LUT5 /* \dri_cnt[8:0]_9 */ #( + .INIT(32'b11110100111101001111010011110000)) + \dri_cnt[8:0]_9 ( + .Z (_N104793), + .I0 (busy), + .I1 (busy_1d), .I2 (state[1]), - .I3 (state[5]), - .I4 (_N18000)); - // LUT = (I4)|(I1&I2)|(~I0&I1&I3) ; + .I3 (state[2]), + .I4 (state[4])); + // LUT = (I2)|(~I0&I1&I3)|(~I0&I1&I4) ; + + GTP_LUT5 /* \dri_cnt[8:0]_28 */ #( + .INIT(32'b11110000111100001101000011000000)) + \dri_cnt[8:0]_28 ( + .Z (_N36328), + .I0 (N1359), + .I1 (N1873), + .I2 (N101[1]), + .I3 (state[1]), + .I4 (_N96603)); + // LUT = (I1&I2)|(I2&I4)|(~I0&I2&I3) ; - GTP_LUT5 /* \dri_cnt[8:0]_1091 */ #( - .INIT(32'b00110011001100110011001100100000)) - \dri_cnt[8:0]_1091 ( - .Z (_N38948), - .I0 (busy_falling), - .I1 (dri_cnt[0]), - .I2 (state[2]), - .I3 (_N18002), - .I4 (_N96041)); - // LUT = (~I1&I3)|(~I1&I4)|(I0&~I1&I2) ; + GTP_LUT5 /* \dri_cnt[8:0]_115 */ #( + .INIT(32'b11110000111100001111000011100000)) + \dri_cnt[8:0]_115 ( + .Z (_N36470), + .I0 (N1321), + .I1 (N1873), + .I2 (N101[6]), + .I3 (_N96761), + .I4 (_N104787)); + // LUT = (I0&I2)|(I1&I2)|(I2&I3)|(I2&I4) ; + + GTP_LUT4 /* \dri_cnt[8:0]_116_3 */ #( + .INIT(16'b1111010011110000)) + \dri_cnt[8:0]_116_3 ( + .Z (_N104787), + .I0 (busy), + .I1 (busy_1d), + .I2 (state[1]), + .I3 (state[4])); + // LUT = (I2)|(~I0&I1&I3) ; + + GTP_LUT5 /* \dri_cnt[8:0]_168 */ #( + .INIT(32'b11111111111101001111111111110000)) + \dri_cnt[8:0]_168 ( + .Z (_N104790), + .I0 (busy), + .I1 (busy_1d), + .I2 (state[1]), + .I3 (state[4]), + .I4 (state[5])); + // LUT = (I2)|(I3)|(~I0&I1&I4) ; + + GTP_LUT3 /* \dri_cnt[8:0]_678 */ #( + .INIT(8'b01010100)) + \dri_cnt[8:0]_678 ( + .Z (_N36285), + .I0 (dri_cnt[0]), + .I1 (state[1]), + .I2 (_N96603)); + // LUT = (~I0&I1)|(~I0&I2) ; GTP_DFF_RE /* \dri_cnt[8] */ #( .GRS_EN("TRUE"), @@ -84197,7 +83822,7 @@ module ms7200_ctl .Q (dri_cnt[8]), .CE (N1845), .CLK (clk), - .D (_N39102), + .D (N1844[8]), .R (\ms72xx_ctl/iic_dri_rx/N0_1 )); // ../../sources/designs/hdmi/ms72xx_ctrl/ms7200_ctl.v:454 @@ -84207,18 +83832,18 @@ module ms7200_ctl freq_ensure_vname ( .Q (freq_ensure), .CLK (clk), - .D (_N103492)); + .D (_N104304)); // defparam freq_ensure_vname.orig_name = freq_ensure; // ../../sources/designs/hdmi/ms72xx_ctrl/ms7200_ctl.v:396 GTP_LUT4 /* freq_ensure_rs_mux */ #( .INIT(16'b0011001000110000)) freq_ensure_rs_mux ( - .Z (_N103492), + .Z (_N104304), .I0 (N8), .I1 (N1797), .I2 (freq_ensure), - .I3 (_N104081)); + .I3 (_N104906)); // LUT = (~I1&I2)|(I0&~I1&I3) ; GTP_DFF_RE /* \freq_rec[0] */ #( @@ -85198,21 +84823,18 @@ module ms7200_ctl init_over_vname ( .Q (init_over), .CLK (clk), - .D (_N103298), + .D (_N104110), .R (\ms72xx_ctl/iic_dri_rx/N0_1 )); // defparam init_over_vname.orig_name = init_over; // ../../sources/designs/hdmi/ms72xx_ctrl/ms7200_ctl.v:701 - GTP_LUT5 /* init_over_ce_mux */ #( - .INIT(32'b10111010101010101010101010101010)) + GTP_LUT2 /* init_over_ce_mux */ #( + .INIT(4'b1110)) init_over_ce_mux ( - .Z (_N103298), + .Z (_N104110), .I0 (init_over), - .I1 (busy), - .I2 (N1388), - .I3 (busy_1d), - .I4 (state[5])); - // LUT = (I0)|(~I1&I2&I3&I4) ; + .I1 (N1321)); + // LUT = (I0)|(I1) ; GTP_LUT3 /* \state_fsm[6:0]_2 */ #( .INIT(8'b11011100)) @@ -85236,14 +84858,15 @@ module ms7200_ctl // LUT = (~I1&I4)|(~I0&I4)|(I2&I3) ; // ../../sources/designs/hdmi/ms72xx_ctrl/ms7200_ctl.v:406 - GTP_LUT3 /* \state_fsm[6:0]_9 */ #( - .INIT(8'b11110100)) + GTP_LUT4 /* \state_fsm[6:0]_9 */ #( + .INIT(16'b1110111111101110)) \state_fsm[6:0]_9 ( .Z (state_n[4]), - .I0 (N2093[2]), - .I1 (state[4]), - .I2 (_N95810)); - // LUT = (I2)|(~I0&I1) ; + .I0 (N1321), + .I1 (N1873), + .I2 (N2093[2]), + .I3 (state[4])); + // LUT = (I0)|(I1)|(~I2&I3) ; // ../../sources/designs/hdmi/ms72xx_ctrl/ms7200_ctl.v:406 GTP_LUT5 /* \state_fsm[6:0]_12 */ #( @@ -85314,22 +84937,22 @@ module ms7200_ctl w_r_vname ( .Q (w_r), .CLK (clk), - .D (_N103299), + .D (_N104111), .S (\ms72xx_ctl/iic_dri_rx/N0_1 )); // defparam w_r_vname.orig_name = w_r; // ../../sources/designs/hdmi/ms72xx_ctrl/ms7200_ctl.v:514 GTP_LUT5M /* w_r_ce_mux */ #( - .INIT(32'b10101010101010100000000001111111)) + .INIT(32'b10101010101010100001010101010101)) w_r_ce_mux ( - .Z (_N103299), + .Z (_N104111), .I0 (w_r), .I1 (busy_falling), .I2 (state[1]), - .I3 (_N95810), + .I3 (N1415), .I4 (N1879), - .ID (N1415)); - // LUT = (~I2&~I3&~I4)|(~I1&~I3&~I4)|(~ID&~I3&~I4)|(I0&I4) ; + .ID (_N96696)); + // LUT = (~ID&~I3&~I4)|(~ID&~I2&~I4)|(~ID&~I1&~I4)|(I0&I4) ; endmodule @@ -85340,7 +84963,7 @@ module ms7210_ctl input [7:0] data_out, input [5:0] state_reg, input N581, - input _N96143, + input _N96633, input busy, input byte_over, input clk, @@ -85357,7 +84980,6 @@ module ms7210_ctl output \state_reg[4]_dirfix , output w_r ); - wire [4:0] N62; wire [21:0] N98; wire N118; wire N124; @@ -85379,11 +85001,12 @@ module ms7210_ctl wire _N11; wire _N14; wire _N17; - wire _N13829; - wire _N13830; - wire _N13831; - wire _N13832; - wire _N13833; + wire _N2723; + wire _N14010; + wire _N14011; + wire _N14012; + wire _N14013; + wire _N14014; wire _N17180; wire _N17181; wire _N17182; @@ -85404,31 +85027,32 @@ module ms7210_ctl wire _N17197; wire _N17198; wire _N17199; - wire _N38010; - wire _N38053; - wire _N38099; - wire _N38143; - wire _N39120; - wire _N39167; - wire _N39213; - wire _N39259; - wire _N39299; - wire _N39343; - wire _N39388; - wire _N39434; - wire _N39516; - wire _N95867; - wire _N103300; - wire _N103301; - wire _N103302; - wire _N104392; - wire _N104397; - wire _N104401; - wire _N104405; - wire _N104406; - wire _N104446; - wire _N104448; - wire _N104459; + wire _N35697; + wire _N35742; + wire _N35787; + wire _N35828; + wire _N36516; + wire _N36557; + wire _N36602; + wire _N36642; + wire _N36683; + wire _N36728; + wire _N36772; + wire _N36818; + wire _N36904; + wire _N37365; + wire _N96642; + wire _N104112; + wire _N104113; + wire _N104114; + wire _N105231; + wire _N105236; + wire _N105240; + wire _N105244; + wire _N105245; + wire _N105283; + wire _N105285; + wire _N105296; wire busy_1d; wire [23:0] cmd_iic; wire [5:0] cmd_index; @@ -85466,7 +85090,7 @@ module ms7210_ctl GTP_LUT4 /* N14_6 */ #( .INIT(16'b1000000000000000)) N14_6 ( - .Z (_N104446), + .Z (_N105283), .I0 (data_out[1]), .I1 (data_out[3]), .I2 (data_out[4]), @@ -85476,12 +85100,12 @@ module ms7210_ctl GTP_LUT5 /* N14_8 */ #( .INIT(32'b00000000000000010000000000000000)) N14_8 ( - .Z (_N104448), + .Z (_N105285), .I0 (data_out[0]), .I1 (data_out[2]), .I2 (data_out[5]), .I3 (data_out[7]), - .I4 (_N104446)); + .I4 (_N105283)); // LUT = ~I0&~I1&~I2&~I3&I4 ; GTP_LUT3 /* N36 */ #( @@ -85494,26 +85118,14 @@ module ms7210_ctl // LUT = ~I0&I1&I2 ; // ../../sources/designs/hdmi/ms72xx_ctrl/ms7210_ctl.v:144 - GTP_LUT4 /* N62_sum3 */ #( - .INIT(16'b0111111110000000)) - N62_sum3 ( - .Z (N62[3]), - .I0 (dri_cnt[0]), - .I1 (dri_cnt[1]), - .I2 (dri_cnt[2]), - .I3 (dri_cnt[3])); - // LUT = (~I2&I3)|(~I1&I3)|(~I0&I3)|(I0&I1&I2&~I3) ; - - GTP_LUT5 /* N62_sum4 */ #( - .INIT(32'b01111111111111111000000000000000)) - N62_sum4 ( - .Z (N62[4]), + GTP_LUT3 /* N62_ac2 */ #( + .INIT(8'b10000000)) + N62_ac2 ( + .Z (_N2723), .I0 (dri_cnt[0]), .I1 (dri_cnt[1]), - .I2 (dri_cnt[2]), - .I3 (dri_cnt[3]), - .I4 (dri_cnt[4])); - // LUT = (~I3&I4)|(~I2&I4)|(~I1&I4)|(~I0&I4)|(I0&I1&I2&I3&~I4) ; + .I2 (dri_cnt[2])); + // LUT = I0&I1&I2 ; GTP_LUT5CARRY /* N98_1_1 */ #( .INIT(32'b01100110011001100000000000000000), @@ -85954,7 +85566,7 @@ module ms7210_ctl .I1 (busy_1d), .I2 (dri_cnt[1]), .I3 (dri_cnt[4]), - .I4 (_N95867)); + .I4 (_N96642)); // LUT = ~I0&I1&~I2&~I3&I4 ; GTP_LUT5CARRY /* N156_1_0 */ #( @@ -85964,7 +85576,7 @@ module ms7210_ctl .I4_TO_CARRY("FALSE"), .I4_TO_LUT("FALSE")) N156_1_0 ( - .COUT (_N13829), + .COUT (_N14010), .Z (), .CIN (), .I0 (), @@ -85984,9 +85596,9 @@ module ms7210_ctl .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N156_1_1 ( - .COUT (_N13830), + .COUT (_N14011), .Z (N579[1]), - .CIN (_N13829), + .CIN (_N14010), .I0 (), .I1 (cmd_index[1]), .I2 (state_reg_alias[0]), @@ -86004,9 +85616,9 @@ module ms7210_ctl .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N156_1_2 ( - .COUT (_N13831), + .COUT (_N14012), .Z (N579[2]), - .CIN (_N13830), + .CIN (_N14011), .I0 (), .I1 (cmd_index[2]), .I2 (state_reg_alias[0]), @@ -86024,9 +85636,9 @@ module ms7210_ctl .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N156_1_3 ( - .COUT (_N13832), + .COUT (_N14013), .Z (N579[3]), - .CIN (_N13831), + .CIN (_N14012), .I0 (), .I1 (cmd_index[3]), .I2 (state_reg_alias[0]), @@ -86044,9 +85656,9 @@ module ms7210_ctl .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N156_1_4 ( - .COUT (_N13833), + .COUT (_N14014), .Z (N579[4]), - .CIN (_N13832), + .CIN (_N14013), .I0 (), .I1 (cmd_index[4]), .I2 (state_reg_alias[0]), @@ -86066,7 +85678,7 @@ module ms7210_ctl N156_1_5 ( .COUT (), .Z (N579[5]), - .CIN (_N13833), + .CIN (_N14014), .I0 (), .I1 (cmd_index[5]), .I2 (state_reg_alias[0]), @@ -86173,7 +85785,7 @@ module ms7210_ctl GTP_LUT3 /* N403_5 */ #( .INIT(8'b00000001)) N403_5 ( - .Z (_N104392), + .Z (_N105231), .I0 (delay_cnt[5]), .I1 (delay_cnt[6]), .I2 (delay_cnt[13])); @@ -86182,7 +85794,7 @@ module ms7210_ctl GTP_LUT5 /* N403_10 */ #( .INIT(32'b00000000000000000000000000000010)) N403_10 ( - .Z (_N104397), + .Z (_N105236), .I0 (delay_cnt[3]), .I1 (delay_cnt[16]), .I2 (delay_cnt[17]), @@ -86193,7 +85805,7 @@ module ms7210_ctl GTP_LUT5 /* N403_14 */ #( .INIT(32'b10000000000000000000000000000000)) N403_14 ( - .Z (_N104401), + .Z (_N105240), .I0 (delay_cnt[4]), .I1 (delay_cnt[7]), .I2 (delay_cnt[8]), @@ -86204,7 +85816,7 @@ module ms7210_ctl GTP_LUT5 /* N403_18 */ #( .INIT(32'b10000000000000000000000000000000)) N403_18 ( - .Z (_N104405), + .Z (_N105244), .I0 (delay_cnt[0]), .I1 (delay_cnt[14]), .I2 (delay_cnt[15]), @@ -86215,22 +85827,22 @@ module ms7210_ctl GTP_LUT5 /* N403_19 */ #( .INIT(32'b00000000000000010000000000000000)) N403_19 ( - .Z (_N104406), + .Z (_N105245), .I0 (delay_cnt[1]), .I1 (delay_cnt[2]), .I2 (delay_cnt[10]), .I3 (delay_cnt[11]), - .I4 (_N104392)); + .I4 (_N105231)); // LUT = ~I0&~I1&~I2&~I3&I4 ; GTP_LUT4 /* N403_22 */ #( .INIT(16'b1000000000000000)) N403_22 ( .Z (N612[0]), - .I0 (_N104397), - .I1 (_N104401), - .I2 (_N104405), - .I3 (_N104406)); + .I0 (_N105236), + .I1 (_N105240), + .I2 (_N105244), + .I3 (_N105245)); // LUT = I0&I1&I2&I3 ; GTP_LUT5 /* N405_9 */ #( @@ -86263,7 +85875,7 @@ module ms7210_ctl .I1 (N527), .I2 (dri_cnt[0]), .I3 (dri_cnt[1]), - .I4 (_N96143)); + .I4 (_N96633)); // LUT = (I2&~I3&I4)|(~I2&I3&I4)|(~I0&I1&I2&~I3)|(~I0&I1&~I2&I3) ; GTP_LUT5 /* \N536_7_or[2]_1 */ #( @@ -86274,30 +85886,19 @@ module ms7210_ctl .I1 (dri_cnt[0]), .I2 (dri_cnt[1]), .I3 (dri_cnt[2]), - .I4 (_N96143)); + .I4 (_N96633)); // LUT = (I0&~I2&I3)|(~I2&I3&I4)|(I0&~I1&I3)|(~I1&I3&I4)|(I0&I1&I2&~I3)|(I1&I2&~I3&I4) ; GTP_LUT5 /* \N536_7_or[3]_1 */ #( - .INIT(32'b11110000111100000100000000000000)) + .INIT(32'b01010101101010100100000010000000)) \N536_7_or[3]_1 ( .Z (N536[3]), - .I0 (busy), - .I1 (busy_1d), - .I2 (N62[3]), - .I3 (state_reg_alias[1]), - .I4 (_N96143)); - // LUT = (I2&I4)|(~I0&I1&I2&I3) ; - - GTP_LUT5 /* \N536_7_or[4]_1 */ #( - .INIT(32'b11110000111100000100000000000000)) - \N536_7_or[4]_1 ( - .Z (N536[4]), - .I0 (busy), - .I1 (busy_1d), - .I2 (N62[4]), - .I3 (state_reg_alias[1]), - .I4 (_N96143)); - // LUT = (I2&I4)|(~I0&I1&I2&I3) ; + .I0 (_N2723), + .I1 (busy_falling), + .I2 (state_reg_alias[1]), + .I3 (dri_cnt[3]), + .I4 (_N96633)); + // LUT = (I0&~I3&I4)|(~I0&I3&I4)|(I0&I1&I2&~I3)|(~I0&I1&I2&I3) ; GTP_LUT5 /* N537_1 */ #( .INIT(32'b01010000010100000101000001110011)) @@ -86323,7 +85924,7 @@ module ms7210_ctl GTP_LUT3 /* N556_1 */ #( .INIT(8'b00000001)) N556_1 ( - .Z (_N95867), + .Z (_N96642), .I0 (dri_cnt[0]), .I1 (dri_cnt[2]), .I2 (dri_cnt[3])); @@ -86332,7 +85933,7 @@ module ms7210_ctl GTP_LUT5 /* N559_6 */ #( .INIT(32'b11111111111110101111111111111110)) N559_6 ( - .Z (_N104459), + .Z (_N105296), .I0 (state_reg_alias[5]), .I1 (\state_reg[4]_dirfix ), .I2 (state_reg_alias[3]), @@ -86348,7 +85949,7 @@ module ms7210_ctl .I1 (N382), .I2 (busy_falling), .I3 (state_reg_alias[1]), - .I4 (_N104459)); + .I4 (_N105296)); // LUT = (I4)|(~I0&~I2&I3)|(~I0&~I1&I3) ; GTP_LUT3 /* \N579_1[0]_1 */ #( @@ -86381,7 +85982,7 @@ module ms7210_ctl .I1 (N382), .I2 (busy_1d), .I3 (state_reg_alias[1]), - .I4 (_N104448)); + .I4 (_N105285)); // defparam N586_vname.orig_name = N586; // LUT = ~I0&I1&I2&I3&I4 ; // ../../sources/designs/hdmi/ms72xx_ctrl/ms7210_ctl.v:254 @@ -86476,7 +86077,7 @@ module ms7210_ctl .I1 (N382), .I2 (busy_1d), .I3 (state_reg_alias[1]), - .I4 (_N104448)); + .I4 (_N105285)); // defparam N591_vname.orig_name = N591; // LUT = (~I3)|(~I0&I1&I2&I4) ; @@ -86509,7 +86110,7 @@ module ms7210_ctl .Q (addr[2]), .CE (N591), .CLK (clk), - .D (_N39120), + .D (_N36516), .R (\ms72xx_ctl/iic_dri_rx/N0_1 )); // ../../sources/designs/hdmi/ms72xx_ctrl/ms7210_ctl.v:249 @@ -86520,7 +86121,7 @@ module ms7210_ctl .Q (addr[3]), .CE (N591), .CLK (clk), - .D (_N39167), + .D (_N36557), .R (\ms72xx_ctl/iic_dri_rx/N0_1 )); // ../../sources/designs/hdmi/ms72xx_ctrl/ms7210_ctl.v:249 @@ -86531,7 +86132,7 @@ module ms7210_ctl .Q (addr[4]), .CE (N591), .CLK (clk), - .D (_N39213), + .D (_N36602), .R (\ms72xx_ctl/iic_dri_rx/N0_1 )); // ../../sources/designs/hdmi/ms72xx_ctrl/ms7210_ctl.v:249 @@ -86542,7 +86143,7 @@ module ms7210_ctl .Q (addr[5]), .CE (N591), .CLK (clk), - .D (_N39259), + .D (_N36642), .R (\ms72xx_ctl/iic_dri_rx/N0_1 )); // ../../sources/designs/hdmi/ms72xx_ctrl/ms7210_ctl.v:249 @@ -86553,7 +86154,7 @@ module ms7210_ctl .Q (addr[6]), .CE (N591), .CLK (clk), - .D (_N39299), + .D (_N36683), .R (\ms72xx_ctl/iic_dri_rx/N0_1 )); // ../../sources/designs/hdmi/ms72xx_ctrl/ms7210_ctl.v:249 @@ -86564,7 +86165,7 @@ module ms7210_ctl .Q (addr[7]), .CE (N591), .CLK (clk), - .D (_N39343), + .D (_N36728), .R (\ms72xx_ctl/iic_dri_rx/N0_1 )); // ../../sources/designs/hdmi/ms72xx_ctrl/ms7210_ctl.v:249 @@ -86586,7 +86187,7 @@ module ms7210_ctl .Q (\ms72xx_ctl/addr_tx [9] ), .CE (N591), .CLK (clk), - .D (_N39388), + .D (_N36772), .R (\ms72xx_ctl/iic_dri_rx/N0_1 )); // ../../sources/designs/hdmi/ms72xx_ctrl/ms7210_ctl.v:249 @@ -86608,14 +86209,14 @@ module ms7210_ctl .Q (addr[11]), .CE (N591), .CLK (clk), - .D (_N39434), + .D (_N36818), .R (\ms72xx_ctl/iic_dri_rx/N0_1 )); // ../../sources/designs/hdmi/ms72xx_ctrl/ms7210_ctl.v:249 GTP_LUT5 /* \addr[15:0]_0 */ #( .INIT(32'b11111111111111100000000000000000)) \addr[15:0]_0 ( - .Z (_N39120), + .Z (_N36516), .I0 (\state_reg[4]_dirfix ), .I1 (state_reg_alias[3]), .I2 (\state_reg[2]_dirfix ), @@ -86626,7 +86227,7 @@ module ms7210_ctl GTP_LUT5 /* \addr[15:0]_4 */ #( .INIT(32'b11111111111111100000000000000000)) \addr[15:0]_4 ( - .Z (_N39167), + .Z (_N36557), .I0 (\state_reg[4]_dirfix ), .I1 (state_reg_alias[3]), .I2 (\state_reg[2]_dirfix ), @@ -86637,7 +86238,7 @@ module ms7210_ctl GTP_LUT5 /* \addr[15:0]_8 */ #( .INIT(32'b11111111111111100000000000000000)) \addr[15:0]_8 ( - .Z (_N39213), + .Z (_N36602), .I0 (\state_reg[4]_dirfix ), .I1 (state_reg_alias[3]), .I2 (\state_reg[2]_dirfix ), @@ -86645,10 +86246,10 @@ module ms7210_ctl .I4 (cmd_iic[12])); // LUT = (I0&I4)|(I1&I4)|(I2&I4)|(I3&I4) ; - GTP_LUT5 /* \addr[15:0]_81 */ #( + GTP_LUT5 /* \addr[15:0]_74 */ #( .INIT(32'b11111111111111100000000000000000)) - \addr[15:0]_81 ( - .Z (_N39259), + \addr[15:0]_74 ( + .Z (_N36642), .I0 (\state_reg[4]_dirfix ), .I1 (state_reg_alias[3]), .I2 (\state_reg[2]_dirfix ), @@ -86656,10 +86257,10 @@ module ms7210_ctl .I4 (cmd_iic[13])); // LUT = (I0&I4)|(I1&I4)|(I2&I4)|(I3&I4) ; - GTP_LUT5 /* \addr[15:0]_121 */ #( + GTP_LUT5 /* \addr[15:0]_115 */ #( .INIT(32'b11111111111111100000000000000000)) - \addr[15:0]_121 ( - .Z (_N39299), + \addr[15:0]_115 ( + .Z (_N36683), .I0 (\state_reg[4]_dirfix ), .I1 (state_reg_alias[3]), .I2 (\state_reg[2]_dirfix ), @@ -86667,10 +86268,10 @@ module ms7210_ctl .I4 (cmd_iic[14])); // LUT = (I0&I4)|(I1&I4)|(I2&I4)|(I3&I4) ; - GTP_LUT5 /* \addr[15:0]_165 */ #( + GTP_LUT5 /* \addr[15:0]_160 */ #( .INIT(32'b11111111111111100000000000000000)) - \addr[15:0]_165 ( - .Z (_N39343), + \addr[15:0]_160 ( + .Z (_N36728), .I0 (\state_reg[4]_dirfix ), .I1 (state_reg_alias[3]), .I2 (\state_reg[2]_dirfix ), @@ -86678,10 +86279,10 @@ module ms7210_ctl .I4 (cmd_iic[15])); // LUT = (I0&I4)|(I1&I4)|(I2&I4)|(I3&I4) ; - GTP_LUT5 /* \addr[15:0]_210 */ #( + GTP_LUT5 /* \addr[15:0]_204 */ #( .INIT(32'b11111111111111100000000000000000)) - \addr[15:0]_210 ( - .Z (_N39388), + \addr[15:0]_204 ( + .Z (_N36772), .I0 (\state_reg[4]_dirfix ), .I1 (state_reg_alias[3]), .I2 (\state_reg[2]_dirfix ), @@ -86689,10 +86290,10 @@ module ms7210_ctl .I4 (cmd_iic[17])); // LUT = (I0&I4)|(I1&I4)|(I2&I4)|(I3&I4) ; - GTP_LUT5 /* \addr[15:0]_256 */ #( + GTP_LUT5 /* \addr[15:0]_250 */ #( .INIT(32'b11111111111111100000000000000000)) - \addr[15:0]_256 ( - .Z (_N39434), + \addr[15:0]_250 ( + .Z (_N36818), .I0 (\state_reg[4]_dirfix ), .I1 (state_reg_alias[3]), .I2 (\state_reg[2]_dirfix ), @@ -86783,7 +86384,7 @@ module ms7210_ctl .Q (data_in[0]), .CE (N591), .CLK (clk), - .D (_N38010), + .D (_N35697), .R (\ms72xx_ctl/iic_dri_rx/N0_1 )); // ../../sources/designs/hdmi/ms72xx_ctrl/ms7210_ctl.v:249 @@ -86805,7 +86406,7 @@ module ms7210_ctl .Q (data_in[2]), .CE (N591), .CLK (clk), - .D (_N38053), + .D (_N35742), .R (\ms72xx_ctl/iic_dri_rx/N0_1 )); // ../../sources/designs/hdmi/ms72xx_ctrl/ms7210_ctl.v:249 @@ -86838,7 +86439,7 @@ module ms7210_ctl .Q (data_in[5]), .CE (N591), .CLK (clk), - .D (_N38099), + .D (_N35787), .R (\ms72xx_ctl/iic_dri_rx/N0_1 )); // ../../sources/designs/hdmi/ms72xx_ctrl/ms7210_ctl.v:249 @@ -86856,7 +86457,7 @@ module ms7210_ctl GTP_LUT5 /* \data_in[7:0]_0 */ #( .INIT(32'b11111111111111100000000000000000)) \data_in[7:0]_0 ( - .Z (_N38010), + .Z (_N35697), .I0 (\state_reg[4]_dirfix ), .I1 (state_reg_alias[3]), .I2 (\state_reg[2]_dirfix ), @@ -86867,7 +86468,7 @@ module ms7210_ctl GTP_LUT5 /* \data_in[7:0]_4 */ #( .INIT(32'b11111111111111100000000000000000)) \data_in[7:0]_4 ( - .Z (_N38053), + .Z (_N35742), .I0 (\state_reg[4]_dirfix ), .I1 (state_reg_alias[3]), .I2 (\state_reg[2]_dirfix ), @@ -86878,7 +86479,7 @@ module ms7210_ctl GTP_LUT5 /* \data_in[7:0]_8 */ #( .INIT(32'b11111111111111100000000000000000)) \data_in[7:0]_8 ( - .Z (_N38099), + .Z (_N35787), .I0 (\state_reg[4]_dirfix ), .I1 (state_reg_alias[3]), .I2 (\state_reg[2]_dirfix ), @@ -86886,10 +86487,10 @@ module ms7210_ctl .I4 (cmd_iic[5])); // LUT = (I0&I4)|(I1&I4)|(I2&I4)|(I3&I4) ; - GTP_LUT5 /* \data_in[7:0]_79 */ #( + GTP_LUT5 /* \data_in[7:0]_75 */ #( .INIT(32'b11111111111111100000000000000000)) - \data_in[7:0]_79 ( - .Z (_N38143), + \data_in[7:0]_75 ( + .Z (_N35828), .I0 (\state_reg[4]_dirfix ), .I1 (state_reg_alias[3]), .I2 (\state_reg[2]_dirfix ), @@ -86904,7 +86505,7 @@ module ms7210_ctl .Q (data_in[7]), .CE (N591), .CLK (clk), - .D (_N38143), + .D (_N35828), .R (\ms72xx_ctl/iic_dri_rx/N0_1 )); // ../../sources/designs/hdmi/ms72xx_ctrl/ms7210_ctl.v:249 @@ -87142,7 +86743,7 @@ module ms7210_ctl .Q (dri_cnt[0]), .CE (N537), .CLK (clk), - .D (_N39516), + .D (_N36904), .R (\ms72xx_ctl/iic_dri_rx/N0_1 )); // ../../sources/designs/hdmi/ms72xx_ctrl/ms7210_ctl.v:158 @@ -87179,17 +86780,28 @@ module ms7210_ctl .R (\ms72xx_ctl/iic_dri_rx/N0_1 )); // ../../sources/designs/hdmi/ms72xx_ctrl/ms7210_ctl.v:158 - GTP_LUT5 /* \dri_cnt[4:0]_1107 */ #( + GTP_LUT5 /* \dri_cnt[4:0]_690 */ #( .INIT(32'b00000000111111110000000011101100)) - \dri_cnt[4:0]_1107 ( - .Z (_N39516), + \dri_cnt[4:0]_690 ( + .Z (_N36904), .I0 (\state_reg[4]_dirfix ), .I1 (state_reg_alias[1]), .I2 (N612[1]), .I3 (dri_cnt[0]), - .I4 (_N96143)); + .I4 (_N96633)); // LUT = (I1&~I3)|(~I3&I4)|(I0&I2&~I3) ; + GTP_LUT5 /* \dri_cnt[4:0]_795 */ #( + .INIT(32'b01011111101000000100110010000000)) + \dri_cnt[4:0]_795 ( + .Z (_N37365), + .I0 (_N2723), + .I1 (state_reg_alias[1]), + .I2 (dri_cnt[3]), + .I3 (dri_cnt[4]), + .I4 (_N96633)); + // LUT = (I1&~I2&I3)|(~I2&I3&I4)|(~I0&I1&I3)|(~I0&I3&I4)|(I0&I1&I2&~I3)|(I0&I2&~I3&I4) ; + GTP_DFF_RE /* \dri_cnt[4] */ #( .GRS_EN("TRUE"), .INIT(1'b0)) @@ -87197,7 +86809,7 @@ module ms7210_ctl .Q (dri_cnt[4]), .CE (N537), .CLK (clk), - .D (N536[4]), + .D (_N37365), .R (\ms72xx_ctl/iic_dri_rx/N0_1 )); // ../../sources/designs/hdmi/ms72xx_ctrl/ms7210_ctl.v:158 @@ -87218,7 +86830,7 @@ module ms7210_ctl init_over_vname ( .Q (init_over), .CLK (clk), - .D (_N103300), + .D (_N104112), .R (\ms72xx_ctl/iic_dri_rx/N0_1 )); // defparam init_over_vname.orig_name = init_over; // ../../sources/designs/hdmi/ms72xx_ctrl/ms7210_ctl.v:284 @@ -87226,7 +86838,7 @@ module ms7210_ctl GTP_LUT2 /* init_over_ce_mux */ #( .INIT(4'b1110)) init_over_ce_mux ( - .Z (_N103300), + .Z (_N104112), .I0 (init_over), .I1 (state_reg_alias[5])); // LUT = (I0)|(I1) ; @@ -87239,7 +86851,7 @@ module ms7210_ctl .I1 (N382), .I2 (busy_falling), .I3 (state_reg_alias[1]), - .I4 (_N104448)); + .I4 (_N105285)); // LUT = (I0)|(I3&~I4)|(~I2&I3)|(~I1&I3) ; // ../../sources/designs/hdmi/ms72xx_ctrl/ms7210_ctl.v:117 @@ -87325,14 +86937,14 @@ module ms7210_ctl \state_reg[5] ( .Q (state_reg_alias[5]), .CLK (clk), - .D (_N103301), + .D (_N104113), .R (\ms72xx_ctl/iic_dri_rx/N0_1 )); // ../../sources/designs/hdmi/ms72xx_ctrl/ms7210_ctl.v:117 GTP_LUT5 /* \state_reg_ce_mux[5] */ #( .INIT(32'b11011100110011001100110011001100)) \state_reg_ce_mux[5] ( - .Z (_N103301), + .Z (_N104113), .I0 (busy), .I1 (state_reg_alias[5]), .I2 (\state_reg[4]_dirfix ), @@ -87346,7 +86958,7 @@ module ms7210_ctl w_r_vname ( .Q (w_r), .CLK (clk), - .D (_N103302), + .D (_N104114), .S (\ms72xx_ctl/iic_dri_rx/N0_1 )); // defparam w_r_vname.orig_name = w_r; // ../../sources/designs/hdmi/ms72xx_ctrl/ms7210_ctl.v:205 @@ -87354,7 +86966,7 @@ module ms7210_ctl GTP_LUT5 /* w_r_ce_mux */ #( .INIT(32'b10101010000000111010101000001111)) w_r_ce_mux ( - .Z (_N103302), + .Z (_N104114), .I0 (w_r), .I1 (N124), .I2 (\state_reg[4]_dirfix ), @@ -87382,8 +86994,9 @@ module ms72xx_ctl output sda_tx_out ); wire N0; - wire _N95852; - wire _N96143; + wire _N96626; + wire _N96633; + wire _N96740; wire [15:0] addr_rx; wire [15:0] addr_tx; wire busy_rx; @@ -87404,7 +87017,9 @@ module ms72xx_ctl wire [6:0] \iic_dri_rx/state_reg ; wire [3:0] \iic_dri_rx/trans_byte ; wire [6:0] \iic_dri_tx/N519 ; + wire [6:0] \iic_dri_tx/state_reg ; wire [2:0] \iic_dri_tx/trans_bit ; + wire [3:0] \iic_dri_tx/trans_byte ; wire iic_trig_rx; wire iic_trig_tx; wire \ms7200_ctl/N1918 ; @@ -87432,6 +87047,12 @@ module ms72xx_ctl wire \iic_dri_rx_state_reg[4]_floating ; wire \iic_dri_rx_state_reg[5]_floating ; wire \iic_dri_rx_state_reg[6]_floating ; + wire \iic_dri_tx_state_reg[0]_floating ; + wire \iic_dri_tx_state_reg[1]_floating ; + wire \iic_dri_tx_state_reg[2]_floating ; + wire \iic_dri_tx_state_reg[4]_floating ; + wire \iic_dri_tx_state_reg[5]_floating ; + wire \iic_dri_tx_state_reg[6]_floating ; wire \ms7200_ctl_addr[8]_floating ; wire \ms7200_ctl_addr[10]_floating ; wire \ms7200_ctl_addr[11]_floating ; @@ -87491,11 +87112,14 @@ module ms72xx_ctl .trans_byte ({\iic_dri_rx/trans_byte [3] , \iic_dri_rx/trans_byte [2] , \iic_dri_rx/trans_byte [1] , \iic_dri_rx/trans_byte [0] }), .addr ({1'bx, 1'bx, addr_rx[13], addr_rx[12], 1'bx, 1'bx, addr_rx[9], addr_rx[8], addr_rx[7], addr_rx[6], addr_rx[5], addr_rx[4], addr_rx[3], addr_rx[2], addr_rx[1], addr_rx[0]}), .data_in (data_in_rx), + .\ms72xx_ctl/iic_dri_tx/state_reg ({1'bx, 1'bx, 1'bx, \iic_dri_tx/state_reg [3] , 1'bx, 1'bx, 1'bx}), .\ms72xx_ctl/iic_dri_tx/trans_bit ({\iic_dri_tx/trans_bit [2] , \iic_dri_tx/trans_bit [1] , \iic_dri_tx/trans_bit [0] }), + .\ms72xx_ctl/iic_dri_tx/trans_byte ({\iic_dri_tx/trans_byte [3] , \iic_dri_tx/trans_byte [2] , \iic_dri_tx/trans_byte [1] , \iic_dri_tx/trans_byte [0] }), .N0 (\iic_dri_rx/N0 ), .N0_1 (\iic_dri_rx/N0_1 ), .N72 (\iic_dri_rx/N72 ), .N80 (\iic_dri_rx/N80 ), + ._N96740 (_N96740), .busy (busy_rx), .byte_over (byte_over_rx), .dsu (\iic_dri_rx/dsu ), @@ -87506,7 +87130,7 @@ module ms72xx_ctl .sda_out_en (sda_out_en), .start_h (\iic_dri_rx/start_h ), ._N8 (_N8), - ._N95852 (_N95852), + ._N96626 (_N96626), .clk (clk), .pluse (iic_trig_rx), .rstn (rstn), @@ -87515,14 +87139,16 @@ module ms72xx_ctl iic_dri_unq4 iic_dri_tx ( .data_out (data_out_tx), + .state_reg ({\iic_dri_tx_state_reg[6]_floating , \iic_dri_tx_state_reg[5]_floating , \iic_dri_tx_state_reg[4]_floating , \iic_dri_tx/state_reg [3] , \iic_dri_tx_state_reg[2]_floating , \iic_dri_tx_state_reg[1]_floating , \iic_dri_tx_state_reg[0]_floating }), .trans_bit ({\iic_dri_tx/trans_bit [2] , \iic_dri_tx/trans_bit [1] , \iic_dri_tx/trans_bit [0] }), + .trans_byte ({\iic_dri_tx/trans_byte [3] , \iic_dri_tx/trans_byte [2] , \iic_dri_tx/trans_byte [1] , \iic_dri_tx/trans_byte [0] }), .N519 ({1'bx, \iic_dri_tx/N519 [5] , 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), .addr ({1'bx, 1'bx, 1'bx, 1'bx, addr_tx[11], addr_tx[10], addr_tx[9], addr_tx[8], addr_tx[7], addr_tx[6], addr_tx[5], addr_tx[4], addr_tx[3], addr_tx[2], addr_tx[1], addr_tx[0]}), .data_in (data_in_tx), .\ms72xx_ctl/iic_dri_rx/state_reg ({1'bx, 1'bx, 1'bx, \iic_dri_rx/state_reg [3] , 1'bx, 1'bx, 1'bx}), .\ms72xx_ctl/iic_dri_rx/trans_byte ({\iic_dri_rx/trans_byte [3] , \iic_dri_rx/trans_byte [2] , \iic_dri_rx/trans_byte [1] , \iic_dri_rx/trans_byte [0] }), .N80 (\iic_dri_tx/N80 ), - ._N95852 (_N95852), + ._N96626 (_N96626), .busy (busy_tx), .byte_over (byte_over_tx), .scl (iic_tx_scl), @@ -87530,6 +87156,7 @@ module ms72xx_ctl .sda_out_en (sda_tx_out_en), .N72 (\iic_dri_rx/N72 ), ._N9_rnms (_N9), + ._N96740 (_N96740), .clk (clk), .dsu (\iic_dri_rx/dsu ), .full_cycle (\iic_dri_rx/full_cycle ), @@ -87549,7 +87176,7 @@ module ms72xx_ctl .data_out (data_out_rx), .\ms72xx_ctl/ms7210_ctl/state_reg ({1'bx, \ms7210_ctl/state_reg [4] , 1'bx, \ms7210_ctl/state_reg [2] , 1'bx, 1'bx}), .N1918 (\ms7200_ctl/N1918 ), - ._N96143 (_N96143), + ._N96633 (_N96633), .iic_trig (iic_trig_rx), .init_over (init_over_rx), .w_r (w_r_rx), @@ -87579,7 +87206,7 @@ module ms72xx_ctl .\state_reg[4]_dirfix (\ms7210_ctl/state_reg [4] ), .w_r (w_r_tx), .N581 (\ms7200_ctl/N1918 ), - ._N96143 (_N96143), + ._N96633 (_N96633), .busy (busy_tx), .byte_over (byte_over_tx), .clk (clk), @@ -87641,10 +87268,10 @@ module key_debounce_unq64 wire N88; wire [23:0] N89; wire N92; - wire _N2843; + wire _N2839; wire _N26996; - wire _N103502; - wire _N104367; + wire _N104314; + wire _N105206; wire clk_ms_ff0; wire clk_ms_ff1; wire [23:0] cnt; @@ -87664,7 +87291,7 @@ module key_debounce_unq64 GTP_LUT3 /* N20_mux2 */ #( .INIT(8'b11111110)) N20_mux2 ( - .Z (_N2843), + .Z (_N2839), .I0 (cnt[2]), .I1 (cnt[1]), .I2 (cnt[0])); @@ -87693,7 +87320,7 @@ module key_debounce_unq64 GTP_LUT4 /* N47_12 */ #( .INIT(16'b0001000000000000)) N47_12 ( - .Z (_N104367), + .Z (_N105206), .I0 (cnt[4]), .I1 (cnt[3]), .I2 (cnt[0]), @@ -87708,7 +87335,7 @@ module key_debounce_unq64 .I1 (cnt[1]), .I2 (key_ff0), .I3 (key_ff1), - .I4 (_N104367)); + .I4 (_N105206)); // LUT = (~I0&~I1&~I2&~I3&I4)|(~I0&~I1&I2&I3&I4) ; GTP_LUT3 /* N87 */ #( @@ -87778,7 +87405,7 @@ module key_debounce_unq64 .INIT(32'b10100100000000001010010010100100)) \N89_6[3] ( .Z (N89[3]), - .I0 (_N2843), + .I0 (_N2839), .I1 (cnt[4]), .I2 (cnt[3]), .I3 (key_ff0), @@ -87789,7 +87416,7 @@ module key_debounce_unq64 .INIT(32'b11001000111111111100100011001000)) \N89_6[4] ( .Z (N89[4]), - .I0 (_N2843), + .I0 (_N2839), .I1 (cnt[4]), .I2 (cnt[3]), .I3 (key_ff0), @@ -87932,14 +87559,14 @@ module key_debounce_unq64 pressed_vname ( .Q (pressed), .CLK (clk), - .D (_N103502)); + .D (_N104314)); // defparam pressed_vname.orig_name = pressed; // ../../sources/designs/others/key_debounce.v:63 GTP_LUT5 /* pressed_rs_mux */ #( .INIT(32'b01010100010101000000000001010100)) pressed_rs_mux ( - .Z (_N103502), + .Z (_N104314), .I0 (rd2_rst), .I1 (pressed), .I2 (N47), @@ -87964,10 +87591,10 @@ module key_debounce_unq66 wire N87; wire N88; wire [23:0] N89; - wire _N2892; + wire _N2888; wire _N27008; - wire _N103504; - wire _N104374; + wire _N104316; + wire _N105213; wire [23:0] cnt; wire key_ff0; wire key_ff1; @@ -87975,7 +87602,7 @@ module key_debounce_unq66 GTP_LUT3 /* N20_mux2 */ #( .INIT(8'b11111110)) N20_mux2 ( - .Z (_N2892), + .Z (_N2888), .I0 (cnt[2]), .I1 (cnt[1]), .I2 (cnt[0])); @@ -87995,7 +87622,7 @@ module key_debounce_unq66 GTP_LUT4 /* N47_5 */ #( .INIT(16'b0001000000000001)) N47_5 ( - .Z (_N104374), + .Z (_N105213), .I0 (cnt[2]), .I1 (cnt[1]), .I2 (key_ff0), @@ -88010,7 +87637,7 @@ module key_debounce_unq66 .I1 (cnt[4]), .I2 (cnt[3]), .I3 (cnt[0]), - .I4 (_N104374)); + .I4 (_N105213)); // LUT = I0&~I1&~I2&I3&I4 ; GTP_LUT3 /* N87 */ #( @@ -88080,7 +87707,7 @@ module key_debounce_unq66 .INIT(32'b10100100000000001010010010100100)) \N89_6[3] ( .Z (N89[3]), - .I0 (_N2892), + .I0 (_N2888), .I1 (cnt[4]), .I2 (cnt[3]), .I3 (key_ff0), @@ -88091,7 +87718,7 @@ module key_debounce_unq66 .INIT(32'b11001000111111111100100011001000)) \N89_6[4] ( .Z (N89[4]), - .I0 (_N2892), + .I0 (_N2888), .I1 (cnt[4]), .I2 (cnt[3]), .I3 (key_ff0), @@ -88181,14 +87808,14 @@ module key_debounce_unq66 pressed_vname ( .Q (pressed), .CLK (clk), - .D (_N103504)); + .D (_N104316)); // defparam pressed_vname.orig_name = pressed; // ../../sources/designs/others/key_debounce.v:63 GTP_LUT5 /* pressed_rs_mux */ #( .INIT(32'b01010100010101000000000001010100)) pressed_rs_mux ( - .Z (_N103504), + .Z (_N104316), .I0 (rd2_rst), .I1 (pressed), .I2 (N47), @@ -88215,10 +87842,10 @@ module key_debounce_unq68 wire N88; wire [23:0] N89; wire N92; - wire _N2941; + wire _N2937; wire _N27020; - wire _N103506; - wire _N104359; + wire _N104318; + wire _N105198; wire [23:0] cnt; wire key_ff0; wire key_ff1; @@ -88226,7 +87853,7 @@ module key_debounce_unq68 GTP_LUT3 /* N20_mux2 */ #( .INIT(8'b11111110)) N20_mux2 ( - .Z (_N2941), + .Z (_N2937), .I0 (cnt[2]), .I1 (cnt[1]), .I2 (cnt[0])); @@ -88246,7 +87873,7 @@ module key_debounce_unq68 GTP_LUT4 /* N47_6 */ #( .INIT(16'b0000001000000000)) N47_6 ( - .Z (_N104359), + .Z (_N105198), .I0 (pluse_ms), .I1 (cnt[4]), .I2 (cnt[3]), @@ -88261,7 +87888,7 @@ module key_debounce_unq68 .I1 (cnt[1]), .I2 (key_ff0), .I3 (key_ff1), - .I4 (_N104359)); + .I4 (_N105198)); // LUT = (~I0&~I1&~I2&~I3&I4)|(~I0&~I1&I2&I3&I4) ; GTP_LUT3 /* N87 */ #( @@ -88331,7 +87958,7 @@ module key_debounce_unq68 .INIT(32'b10100100000000001010010010100100)) \N89_6[3] ( .Z (N89[3]), - .I0 (_N2941), + .I0 (_N2937), .I1 (cnt[4]), .I2 (cnt[3]), .I3 (key_ff0), @@ -88342,7 +87969,7 @@ module key_debounce_unq68 .INIT(32'b11001000111111111100100011001000)) \N89_6[4] ( .Z (N89[4]), - .I0 (_N2941), + .I0 (_N2937), .I1 (cnt[4]), .I2 (cnt[3]), .I3 (key_ff0), @@ -88455,14 +88082,14 @@ module key_debounce_unq68 pressed_vname ( .Q (pressed), .CLK (clk), - .D (_N103506)); + .D (_N104318)); // defparam pressed_vname.orig_name = pressed; // ../../sources/designs/others/key_debounce.v:63 GTP_LUT5 /* pressed_rs_mux */ #( .INIT(32'b01010100010101000000000001010100)) pressed_rs_mux ( - .Z (_N103506), + .Z (_N104318), .I0 (rd2_rst), .I1 (pressed), .I2 (N47), @@ -88489,10 +88116,10 @@ module key_debounce wire N88; wire [23:0] N89; wire N92; - wire _N3006; + wire _N3002; wire _N27038; - wire _N103508; - wire _N104474; + wire _N104320; + wire _N105311; wire [23:0] cnt; wire key_ff0; wire key_ff1; @@ -88500,7 +88127,7 @@ module key_debounce GTP_LUT3 /* N20_mux2 */ #( .INIT(8'b11111110)) N20_mux2 ( - .Z (_N3006), + .Z (_N3002), .I0 (cnt[2]), .I1 (cnt[1]), .I2 (cnt[0])); @@ -88520,7 +88147,7 @@ module key_debounce GTP_LUT4 /* N47_6 */ #( .INIT(16'b0000001000000000)) N47_6 ( - .Z (_N104474), + .Z (_N105311), .I0 (pluse_ms), .I1 (cnt[4]), .I2 (cnt[3]), @@ -88535,7 +88162,7 @@ module key_debounce .I1 (cnt[1]), .I2 (key_ff0), .I3 (key_ff1), - .I4 (_N104474)); + .I4 (_N105311)); // LUT = (~I0&~I1&~I2&~I3&I4)|(~I0&~I1&I2&I3&I4) ; GTP_LUT3 /* N87 */ #( @@ -88605,7 +88232,7 @@ module key_debounce .INIT(32'b10100100000000001010010010100100)) \N89_6[3] ( .Z (N89[3]), - .I0 (_N3006), + .I0 (_N3002), .I1 (cnt[4]), .I2 (cnt[3]), .I3 (key_ff0), @@ -88616,7 +88243,7 @@ module key_debounce .INIT(32'b11001000111111111100100011001000)) \N89_6[4] ( .Z (N89[4]), - .I0 (_N3006), + .I0 (_N3002), .I1 (cnt[4]), .I2 (cnt[3]), .I3 (key_ff0), @@ -88729,14 +88356,14 @@ module key_debounce pressed_vname ( .Q (pressed), .CLK (clk), - .D (_N103508)); + .D (_N104320)); // defparam pressed_vname.orig_name = pressed; // ../../sources/designs/others/key_debounce.v:63 GTP_LUT5 /* pressed_rs_mux */ #( .INIT(32'b01010100010101000000000001010100)) pressed_rs_mux ( - .Z (_N103508), + .Z (_N104320), .I0 (rd2_rst), .I1 (pressed), .I2 (N47), @@ -88763,10 +88390,10 @@ module key_debounce_unq62 wire N88; wire [23:0] N89; wire N92; - wire _N3055; + wire _N3051; wire _N27050; - wire _N103510; - wire _N104491; + wire _N104322; + wire _N105328; wire [23:0] cnt; wire key_ff0; wire key_ff1; @@ -88774,7 +88401,7 @@ module key_debounce_unq62 GTP_LUT3 /* N20_mux2 */ #( .INIT(8'b11111110)) N20_mux2 ( - .Z (_N3055), + .Z (_N3051), .I0 (cnt[2]), .I1 (cnt[1]), .I2 (cnt[0])); @@ -88794,7 +88421,7 @@ module key_debounce_unq62 GTP_LUT4 /* N47_6 */ #( .INIT(16'b0000001000000000)) N47_6 ( - .Z (_N104491), + .Z (_N105328), .I0 (pluse_ms), .I1 (cnt[4]), .I2 (cnt[3]), @@ -88809,7 +88436,7 @@ module key_debounce_unq62 .I1 (cnt[1]), .I2 (key_ff0), .I3 (key_ff1), - .I4 (_N104491)); + .I4 (_N105328)); // LUT = (~I0&~I1&~I2&~I3&I4)|(~I0&~I1&I2&I3&I4) ; GTP_LUT3 /* N87 */ #( @@ -88879,7 +88506,7 @@ module key_debounce_unq62 .INIT(32'b10100100000000001010010010100100)) \N89_6[3] ( .Z (N89[3]), - .I0 (_N3055), + .I0 (_N3051), .I1 (cnt[4]), .I2 (cnt[3]), .I3 (key_ff0), @@ -88890,7 +88517,7 @@ module key_debounce_unq62 .INIT(32'b11001000111111111100100011001000)) \N89_6[4] ( .Z (N89[4]), - .I0 (_N3055), + .I0 (_N3051), .I1 (cnt[4]), .I2 (cnt[3]), .I3 (key_ff0), @@ -89003,14 +88630,14 @@ module key_debounce_unq62 pressed_vname ( .Q (pressed), .CLK (clk), - .D (_N103510)); + .D (_N104322)); // defparam pressed_vname.orig_name = pressed; // ../../sources/designs/others/key_debounce.v:63 GTP_LUT5 /* pressed_rs_mux */ #( .INIT(32'b01010100010101000000000001010100)) pressed_rs_mux ( - .Z (_N103510), + .Z (_N104322), .I0 (rd2_rst), .I1 (pressed), .I2 (N47), @@ -89025,25 +88652,28 @@ endmodule module param_cell_unsigned_loop ( input [2:0] load_data, - input [13:0] \param_manager_inst/selected , input N111, input N140, + input _N108109, + input _N108110, input akey_down, input akey_up, input clk, input \key_debounce_inst2/pluse_ms , input load_valid, - input \param_manager_inst/param_modify_H/pluse , + input \param_manager_inst/modify_S_load , + input \param_manager_inst/param_modify_S/N140 , input rd2_rst, input restore, input selected, output [2:0] value, + output N59, output N116, output N119, output N161, output changed_down, output changed_up, - output \param_manager_inst/param_modify_H/N140 , + output \param_manager_inst/param_modify_S/N153 , output pluse, output pressed_down, output pressed_up @@ -89058,9 +88688,11 @@ module param_cell_unsigned_loop wire N153; wire [2:0] N154; wire [11:0] N167; - wire _N81667; - wire _N105304; - wire _N105307; + wire _N37746; + wire _N37753; + wire _N82454; + wire _N106117; + wire _N106120; wire [11:0] cnt; GTP_LUT5CARRY /* \N26_1.fsub_1 */ #( @@ -89293,10 +88925,21 @@ module param_cell_unsigned_loop // LUT = I0&I1 ; // ../../sources/designs/others/param_cell_unsigned_loop.v:94 + GTP_LUT3 /* N59 */ #( + .INIT(8'b11100000)) + N59_vname ( + .Z (N59), + .I0 (changed_down), + .I1 (pluse), + .I2 (pressed_down)); + // defparam N59_vname.orig_name = N59; + // LUT = (I0&I2)|(I1&I2) ; + // ../../sources/designs/others/param_cell_unsigned_loop.v:118 + GTP_LUT4 /* N102_8 */ #( .INIT(16'b0000000000000001)) N102_8 ( - .Z (_N105304), + .Z (_N106117), .I0 (cnt[3]), .I1 (cnt[2]), .I2 (cnt[1]), @@ -89306,12 +88949,12 @@ module param_cell_unsigned_loop GTP_LUT5 /* N102_11 */ #( .INIT(32'b00000000000000010000000000000000)) N102_11 ( - .Z (_N105307), + .Z (_N106120), .I0 (cnt[7]), .I1 (cnt[6]), .I2 (cnt[5]), .I3 (cnt[4]), - .I4 (_N105304)); + .I4 (_N106117)); // LUT = ~I0&~I1&~I2&~I3&I4 ; GTP_LUT5 /* N102_12 */ #( @@ -89322,7 +88965,7 @@ module param_cell_unsigned_loop .I1 (cnt[10]), .I2 (cnt[9]), .I3 (cnt[8]), - .I4 (_N105307)); + .I4 (_N106120)); // LUT = ~I0&~I1&~I2&~I3&I4 ; GTP_LUT2 /* N116 */ #( @@ -89468,13 +89111,13 @@ module param_cell_unsigned_loop .I1 (load_valid), .I2 (restore), .I3 (selected), - .I4 (_N81667)); + .I4 (_N82454)); // LUT = (I0)|(I3&I4)|(~I1&I2&I3) ; GTP_LUT5 /* N152_5_3 */ #( .INIT(32'b00100010001000000000000000000000)) N152_5_3 ( - .Z (_N81667), + .Z (_N82454), .I0 (value[2]), .I1 (N149), .I2 (changed_up), @@ -89482,16 +89125,6 @@ module param_cell_unsigned_loop .I4 (pressed_up)); // LUT = (I0&~I1&I2&I4)|(I0&~I1&I3&I4) ; - GTP_LUT4 /* N152_6 */ #( - .INIT(16'b1010000010000000)) - N152_6 ( - .Z (\param_manager_inst/param_modify_H/N140 ), - .I0 (\param_manager_inst/selected [11] ), - .I1 (changed_down), - .I2 (pressed_down), - .I3 (\param_manager_inst/param_modify_H/pluse )); - // LUT = (I0&I1&I2)|(I0&I2&I3) ; - GTP_LUT5 /* N153 */ #( .INIT(32'b11101110111011001100110011001100)) N153_vname ( @@ -89516,18 +89149,6 @@ module param_cell_unsigned_loop .I4 (pressed_down)); // LUT = (I0)|(I1&I2&I4)|(I1&I3&I4) ; - GTP_LUT5M /* \N154_10[0] */ #( - .INIT(32'b10101010101010100000000011111101)) - \N154_10[0] ( - .Z (N154[0]), - .I0 (load_data[0]), - .I1 (value[2]), - .I2 (value[1]), - .I3 (value[0]), - .I4 (load_valid), - .ID (N140)); - // LUT = (I2&~I3&~I4)|(I1&~I3&~I4)|(~ID&~I3&~I4)|(I0&I4) ; - GTP_LUT5M /* \N154_10[1] */ #( .INIT(32'b10101010101010101010010101011000)) \N154_10[1] ( @@ -89552,6 +89173,16 @@ module param_cell_unsigned_loop .ID (N140)); // LUT = (ID&~I1&~I2&~I3&~I4)|(~ID&I1&~I3&~I4)|(~ID&~I1&I2&I3&~I4)|(ID&I1&I3&~I4)|(~ID&I1&~I2&~I4)|(ID&I1&I2&~I4)|(I0&I4) ; + GTP_LUT4 /* N157_2 */ #( + .INIT(16'b0101010101010001)) + N157_2 ( + .Z (\param_manager_inst/param_modify_S/N153 ), + .I0 (\param_manager_inst/modify_S_load ), + .I1 (\param_manager_inst/param_modify_S/N140 ), + .I2 (_N108109), + .I3 (_N108110)); + // LUT = (~I0&~I1)|(~I0&I2)|(~I0&I3) ; + GTP_LUT5 /* N161_1 */ #( .INIT(32'b11111110111110101110111011111111)) N161_1 ( @@ -89719,7 +89350,7 @@ module param_cell_unsigned_loop .Q (value[0]), .CE (N153), .CLK (clk), - .D (N154[0]), + .D (_N37746), .R (N152)); // ../../sources/designs/others/param_cell_unsigned_loop.v:101 @@ -89734,6 +89365,28 @@ module param_cell_unsigned_loop .R (N152)); // ../../sources/designs/others/param_cell_unsigned_loop.v:101 + GTP_LUT5 /* \value[2:0]_0 */ #( + .INIT(32'b10100011101000111010000010100011)) + \value[2:0]_0 ( + .Z (_N37746), + .I0 (load_data[0]), + .I1 (value[0]), + .I2 (load_valid), + .I3 (pressed_down), + .I4 (_N37753)); + // LUT = (I0&I2)|(~I1&~I2&~I3)|(~I1&~I2&I4) ; + + GTP_LUT5 /* \value[2:0]_5 */ #( + .INIT(32'b11111110111111101111111011111111)) + \value[2:0]_5 ( + .Z (_N37753), + .I0 (value[0]), + .I1 (value[1]), + .I2 (value[2]), + .I3 (changed_down), + .I4 (pluse)); + // LUT = (I0)|(I1)|(I2)|(~I3&~I4) ; + GTP_DFF_RE /* \value[2] */ #( .GRS_EN("TRUE"), .INIT(1'b0)) @@ -89752,13 +89405,16 @@ endmodule module param_cell_unsigned_loop_unq4 ( input [2:0] load_data, - input [13:0] \param_manager_inst/selected , + input N59, input N140, + input _N108087, + input _N108088, input changed_down, input changed_up, input clk, input load_valid, - input \param_manager_inst/param_modify_H/pluse , + input \param_manager_inst/modify_V_load , + input \param_manager_inst/param_modify_V/N140 , input pluse, input pressed_down, input pressed_up, @@ -89766,13 +89422,14 @@ module param_cell_unsigned_loop_unq4 input restore, input selected, output [2:0] value, - output \param_manager_inst/param_modify_S/N140 + output \param_manager_inst/param_modify_V/N153 ); wire N149; wire N152; wire N153; wire [2:0] N154; - wire _N81678; + wire _N38000; + wire _N82459; GTP_LUT5 /* N152_1 */ #( .INIT(32'b11111111101010101011101010101010)) @@ -89782,13 +89439,13 @@ module param_cell_unsigned_loop_unq4 .I1 (load_valid), .I2 (restore), .I3 (selected), - .I4 (_N81678)); + .I4 (_N82459)); // LUT = (I0)|(I3&I4)|(~I1&I2&I3) ; GTP_LUT5 /* N152_5_3 */ #( .INIT(32'b00000000000000001010100000000000)) N152_5_3 ( - .Z (_N81678), + .Z (_N82459), .I0 (value[2]), .I1 (changed_up), .I2 (pluse), @@ -89796,16 +89453,6 @@ module param_cell_unsigned_loop_unq4 .I4 (N149)); // LUT = (I0&I1&I3&~I4)|(I0&I2&I3&~I4) ; - GTP_LUT4 /* N152_6 */ #( - .INIT(16'b1010000010000000)) - N152_6 ( - .Z (\param_manager_inst/param_modify_S/N140 ), - .I0 (\param_manager_inst/selected [12] ), - .I1 (changed_down), - .I2 (pressed_down), - .I3 (\param_manager_inst/param_modify_H/pluse )); - // LUT = (I0&I1&I2)|(I0&I2&I3) ; - GTP_LUT5 /* N153 */ #( .INIT(32'b11111111111111111010100000000000)) N153_vname ( @@ -89830,18 +89477,6 @@ module param_cell_unsigned_loop_unq4 .I4 (pressed_down)); // LUT = (I0)|(I1&I2&I4)|(I1&I3&I4) ; - GTP_LUT5M /* \N154_10[0] */ #( - .INIT(32'b10101010101010100000000011111101)) - \N154_10[0] ( - .Z (N154[0]), - .I0 (load_data[0]), - .I1 (value[2]), - .I2 (value[1]), - .I3 (value[0]), - .I4 (load_valid), - .ID (N140)); - // LUT = (I2&~I3&~I4)|(I1&~I3&~I4)|(~ID&~I3&~I4)|(I0&I4) ; - GTP_LUT5M /* \N154_10[1] */ #( .INIT(32'b10101010101010101010010101011000)) \N154_10[1] ( @@ -89866,6 +89501,16 @@ module param_cell_unsigned_loop_unq4 .ID (N140)); // LUT = (ID&~I1&~I2&~I3&~I4)|(~ID&I1&~I3&~I4)|(~ID&~I1&I2&I3&~I4)|(ID&I1&I3&~I4)|(~ID&I1&~I2&~I4)|(ID&I1&I2&~I4)|(I0&I4) ; + GTP_LUT4 /* N157_2 */ #( + .INIT(16'b0101010101010001)) + N157_2 ( + .Z (\param_manager_inst/param_modify_V/N153 ), + .I0 (\param_manager_inst/modify_V_load ), + .I1 (\param_manager_inst/param_modify_V/N140 ), + .I2 (_N108087), + .I3 (_N108088)); + // LUT = (~I0&~I1)|(~I0&I2)|(~I0&I3) ; + GTP_DFF_RE /* \value[0] */ #( .GRS_EN("TRUE"), .INIT(1'b0)) @@ -89873,7 +89518,7 @@ module param_cell_unsigned_loop_unq4 .Q (value[0]), .CE (N153), .CLK (clk), - .D (N154[0]), + .D (_N38000), .R (N152)); // ../../sources/designs/others/param_cell_unsigned_loop.v:101 @@ -89888,6 +89533,18 @@ module param_cell_unsigned_loop_unq4 .R (N152)); // ../../sources/designs/others/param_cell_unsigned_loop.v:101 + GTP_LUT5M /* \value[2:0]_0 */ #( + .INIT(32'b10101010101010100000000011111101)) + \value[2:0]_0 ( + .Z (_N38000), + .I0 (load_data[0]), + .I1 (value[2]), + .I2 (value[1]), + .I3 (value[0]), + .I4 (load_valid), + .ID (N59)); + // LUT = (I2&~I3&~I4)|(I1&~I3&~I4)|(~ID&~I3&~I4)|(I0&I4) ; + GTP_DFF_RE /* \value[2] */ #( .GRS_EN("TRUE"), .INIT(1'b0)) @@ -89906,54 +89563,69 @@ endmodule module param_cell_signed_loop ( input [8:0] load_data, + input [13:0] \param_manager_inst/selected , + input [11:0] param_offsetX, + input [11:0] param_offsetY, input N111, input N116, input N119, input N140, + input N153, input N160, + input _N3669, + input _N3811, + input _N105338, + input changed_down, input changed_up, input clk, input \key_debounce_inst2/pluse_ms , input load_valid, + input \param_manager_inst/offsetX_load , + input \param_manager_inst/offsetY_load , + input \param_manager_inst/param_offsetX/N140 , + input \param_manager_inst/param_offsetY/N140 , + input \param_manager_inst/param_osd_startX/pluse , + input pressed_down, input pressed_up, input rd2_rst, input restore, input selected, output [8:0] value, output N72, + output _N3230, + output \param_manager_inst/param_offsetX/N153 , + output \param_manager_inst/param_offsetY/N153 , + output \param_manager_inst/param_osd_startX/N140 , output pluse ); wire [11:0] \N26_1.co ; wire N37; - wire N76; wire [11:0] N117; wire N120; wire N122; wire N149; wire N150; wire [8:0] N151; - wire N153; wire N154; wire _N3248; - wire _N13933; - wire _N13934; - wire _N13935; - wire _N13936; - wire _N13937; - wire _N13938; - wire _N13939; + wire _N13884; + wire _N13885; + wire _N13886; + wire _N13887; + wire _N13888; + wire _N13889; + wire _N13890; wire _N27073_inv; - wire _N29675; - wire _N29678; - wire _N29681; - wire _N29684; - wire _N104546; - wire _N104547; - wire _N104548; - wire _N107227; - wire _N107229; - wire _N107234; - wire _N107236; + wire _N29625; + wire _N29628; + wire _N29631; + wire _N29634; + wire _N105381; + wire _N105382; + wire _N105383; + wire _N108049; + wire _N108056; + wire _N108060; wire [11:0] cnt; wire [8:0] nb0; @@ -89985,7 +89657,7 @@ module param_cell_signed_loop .I4_TO_LUT("FALSE")) \N26_1.fsub_2 ( .COUT (\N26_1.co [2] ), - .Z (_N29675), + .Z (_N29625), .CIN (\N26_1.co [1] ), .I0 (cnt[0]), .I1 (cnt[1]), @@ -90005,7 +89677,7 @@ module param_cell_signed_loop .I4_TO_LUT("FALSE")) \N26_1.fsub_3 ( .COUT (\N26_1.co [3] ), - .Z (_N29678), + .Z (_N29628), .CIN (\N26_1.co [2] ), .I0 (), .I1 (cnt[3]), @@ -90025,7 +89697,7 @@ module param_cell_signed_loop .I4_TO_LUT("FALSE")) \N26_1.fsub_4 ( .COUT (\N26_1.co [4] ), - .Z (_N29681), + .Z (_N29631), .CIN (\N26_1.co [3] ), .I0 (), .I1 (cnt[4]), @@ -90045,7 +89717,7 @@ module param_cell_signed_loop .I4_TO_LUT("FALSE")) \N26_1.fsub_5 ( .COUT (\N26_1.co [5] ), - .Z (_N29684), + .Z (_N29634), .CIN (\N26_1.co [4] ), .I0 (), .I1 (cnt[5]), @@ -90182,9 +89854,9 @@ module param_cell_signed_loop N37_vname ( .Z (N37), .I0 (\key_debounce_inst2/pluse_ms ), - .I1 (_N104546), - .I2 (_N104547), - .I3 (_N104548)); + .I1 (_N105381), + .I2 (_N105382), + .I3 (_N105383)); // defparam N37_vname.orig_name = N37; // LUT = I0&I1&I2&I3 ; // ../../sources/designs/others/param_cell_signed_loop.v:94 @@ -90192,29 +89864,22 @@ module param_cell_signed_loop GTP_LUT4 /* N63_mux5_5 */ #( .INIT(16'b1111111111111110)) N63_mux5_5 ( - .Z (_N107227), + .Z (_N108049), .I0 (value[0]), .I1 (value[1]), .I2 (value[2]), .I3 (value[3])); // LUT = (I0)|(I1)|(I2)|(I3) ; - GTP_LUT3 /* N63_mux5_6 */ #( - .INIT(8'b11111110)) - N63_mux5_6 ( - .Z (_N3248), + GTP_LUT4 /* N63_mux6 */ #( + .INIT(16'b1111000011100000)) + N63_mux6 ( + .Z (_N3230), .I0 (value[4]), .I1 (value[5]), - .I2 (_N107227)); - // LUT = (I0)|(I1)|(I2) ; - - GTP_LUT2 /* N63_mux8_2 */ #( - .INIT(4'b1011)) - N63_mux8_2 ( - .Z (_N107229), - .I0 (value[7]), - .I1 (value[8])); - // LUT = (~I1)|(I0) ; + .I2 (value[6]), + .I3 (_N108049)); + // LUT = (I0&I2)|(I1&I2)|(I2&I3) ; GTP_LUT3 /* N72 */ #( .INIT(8'b11001000)) @@ -90230,36 +89895,27 @@ module param_cell_signed_loop GTP_LUT4 /* N76_mux5_5 */ #( .INIT(16'b0111111111111111)) N76_mux5_5 ( - .Z (_N107234), + .Z (_N108056), .I0 (value[0]), .I1 (value[1]), .I2 (value[2]), .I3 (value[3])); // LUT = (~I3)|(~I2)|(~I1)|(~I0) ; - GTP_LUT2 /* N76_mux8_2 */ #( - .INIT(4'b1101)) - N76_mux8_2 ( - .Z (_N107236), - .I0 (value[7]), - .I1 (value[8])); - // LUT = (~I0)|(I1) ; - - GTP_LUT5 /* N76_mux8_3 */ #( - .INIT(32'b11111111111111110000111100000111)) - N76_mux8_3 ( - .Z (N76), + GTP_LUT4 /* N76_mux6 */ #( + .INIT(16'b0000111100000111)) + N76_mux6 ( + .Z (_N3248), .I0 (value[4]), .I1 (value[5]), .I2 (value[6]), - .I3 (_N107234), - .I4 (_N107236)); - // LUT = (I4)|(~I1&~I2)|(~I0&~I2)|(~I2&I3) ; + .I3 (_N108056)); + // LUT = (~I1&~I2)|(~I0&~I2)|(~I2&I3) ; GTP_LUT4 /* N102_8 */ #( .INIT(16'b0000000000000001)) N102_8 ( - .Z (_N104546), + .Z (_N105381), .I0 (cnt[0]), .I1 (cnt[1]), .I2 (cnt[2]), @@ -90269,7 +89925,7 @@ module param_cell_signed_loop GTP_LUT4 /* N102_9 */ #( .INIT(16'b0000000000000001)) N102_9 ( - .Z (_N104547), + .Z (_N105382), .I0 (cnt[4]), .I1 (cnt[5]), .I2 (cnt[6]), @@ -90279,7 +89935,7 @@ module param_cell_signed_loop GTP_LUT4 /* N102_10 */ #( .INIT(16'b0000000000000001)) N102_10 ( - .Z (_N104548), + .Z (_N105383), .I0 (cnt[8]), .I1 (cnt[9]), .I2 (cnt[10]), @@ -90299,7 +89955,7 @@ module param_cell_signed_loop \N117_or[2] ( .Z (N117[2]), .I0 (N120), - .I1 (_N29675)); + .I1 (_N29625)); // LUT = (I0)|(I1) ; GTP_LUT2 /* \N117_or[3] */ #( @@ -90307,7 +89963,7 @@ module param_cell_signed_loop \N117_or[3] ( .Z (N117[3]), .I0 (N160), - .I1 (_N29678)); + .I1 (_N29628)); // LUT = (I0)|(I1) ; GTP_LUT2 /* \N117_or[4] */ #( @@ -90315,7 +89971,7 @@ module param_cell_signed_loop \N117_or[4] ( .Z (N117[4]), .I0 (N120), - .I1 (_N29681)); + .I1 (_N29631)); // LUT = (I0)|(I1) ; GTP_LUT2 /* \N117_or[5] */ #( @@ -90323,7 +89979,7 @@ module param_cell_signed_loop \N117_or[5] ( .Z (N117[5]), .I0 (N160), - .I1 (_N29684)); + .I1 (_N29634)); // LUT = (I0)|(I1) ; GTP_LUT5 /* N120 */ #( @@ -90332,9 +89988,9 @@ module param_cell_signed_loop .Z (N120), .I0 (N111), .I1 (N119), - .I2 (_N104546), - .I3 (_N104547), - .I4 (_N104548)); + .I2 (_N105381), + .I3 (_N105382), + .I4 (_N105383)); // defparam N120_vname.orig_name = N120; // LUT = I0&I1&I2&I3&I4 ; // ../../sources/designs/others/param_cell_signed_loop.v:71 @@ -90345,12 +90001,34 @@ module param_cell_signed_loop .Z (N122), .I0 (N111), .I1 (N119), - .I2 (_N104546), - .I3 (_N104547), - .I4 (_N104548)); + .I2 (_N105381), + .I3 (_N105382), + .I4 (_N105383)); // defparam N122_vname.orig_name = N122; // LUT = (I0&I1&~I4)|(I0&I1&~I3)|(I0&I1&~I2) ; + GTP_LUT5 /* N139_1 */ #( + .INIT(32'b00001111000011110000100000001111)) + N139_1 ( + .Z (\param_manager_inst/param_offsetX/N153 ), + .I0 (param_offsetX[7]), + .I1 (_N3669), + .I2 (\param_manager_inst/offsetX_load ), + .I3 (\param_manager_inst/param_offsetX/N140 ), + .I4 (_N105338)); + // LUT = (~I2&~I3)|(~I2&I4)|(I0&I1&~I2) ; + + GTP_LUT5 /* N148_1 */ #( + .INIT(32'b00000000111110110000000011111111)) + N148_1 ( + .Z (\param_manager_inst/param_offsetY/N153 ), + .I0 (param_offsetY[10]), + .I1 (param_offsetY[11]), + .I2 (_N3811), + .I3 (\param_manager_inst/offsetY_load ), + .I4 (\param_manager_inst/param_offsetY/N140 )); + // LUT = (~I3&~I4)|(~I1&~I3)|(I0&~I3)|(I2&~I3) ; + GTP_LUT4 /* N149 */ #( .INIT(16'b1011101010101010)) N149_vname ( @@ -90363,9 +90041,9 @@ module param_cell_signed_loop // LUT = (I0)|(~I1&I2&I3) ; // ../../sources/designs/others/param_cell_signed_loop.v:22 - GTP_LUT4 /* N150_1 */ #( + GTP_LUT4 /* N150_3 */ #( .INIT(16'b1111111111101010)) - N150_1 ( + N150_3 ( .Z (N150), .I0 (load_valid), .I1 (selected), @@ -90380,7 +90058,7 @@ module param_cell_signed_loop .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N151_10_1 ( - .COUT (_N13933), + .COUT (_N13884), .Z (nb0[1]), .CIN (), .I0 (value[0]), @@ -90399,9 +90077,9 @@ module param_cell_signed_loop .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N151_10_2 ( - .COUT (_N13934), + .COUT (_N13885), .Z (nb0[2]), - .CIN (_N13933), + .CIN (_N13884), .I0 (value[0]), .I1 (N154), .I2 (value[1]), @@ -90418,9 +90096,9 @@ module param_cell_signed_loop .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N151_10_3 ( - .COUT (_N13935), + .COUT (_N13886), .Z (nb0[3]), - .CIN (_N13934), + .CIN (_N13885), .I0 (), .I1 (N154), .I2 (value[3]), @@ -90437,9 +90115,9 @@ module param_cell_signed_loop .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N151_10_4 ( - .COUT (_N13936), + .COUT (_N13887), .Z (nb0[4]), - .CIN (_N13935), + .CIN (_N13886), .I0 (), .I1 (N154), .I2 (value[4]), @@ -90456,9 +90134,9 @@ module param_cell_signed_loop .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N151_10_5 ( - .COUT (_N13937), + .COUT (_N13888), .Z (nb0[5]), - .CIN (_N13936), + .CIN (_N13887), .I0 (), .I1 (N154), .I2 (value[5]), @@ -90475,9 +90153,9 @@ module param_cell_signed_loop .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N151_10_6 ( - .COUT (_N13938), + .COUT (_N13889), .Z (nb0[6]), - .CIN (_N13937), + .CIN (_N13888), .I0 (), .I1 (N154), .I2 (value[6]), @@ -90494,9 +90172,9 @@ module param_cell_signed_loop .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N151_10_7 ( - .COUT (_N13939), + .COUT (_N13890), .Z (nb0[7]), - .CIN (_N13938), + .CIN (_N13889), .I0 (), .I1 (N154), .I2 (value[7]), @@ -90515,7 +90193,7 @@ module param_cell_signed_loop N151_10_8 ( .COUT (), .Z (nb0[8]), - .CIN (_N13939), + .CIN (_N13890), .I0 (), .I1 (N154), .I2 (value[8]), @@ -90525,16 +90203,15 @@ module param_cell_signed_loop // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - GTP_LUT5 /* N151_19 */ #( - .INIT(32'b10101010101010101010101011101010)) + GTP_LUT4 /* N151_19 */ #( + .INIT(16'b1011101010101010)) N151_19 ( .Z (_N27073_inv), .I0 (load_valid), - .I1 (selected), - .I2 (N72), - .I3 (N76), - .I4 (N140)); - // LUT = (I0)|(I1&I2&~I3&~I4) ; + .I1 (N140), + .I2 (N153), + .I3 (_N108060)); + // LUT = (I0)|(~I1&I2&I3) ; GTP_LUT4 /* \N151_30[0] */ #( .INIT(16'b0000101000111111)) @@ -90626,27 +90303,39 @@ module param_cell_signed_loop .I3 (_N27073_inv)); // LUT = (I0&I3)|(I1&I2)|(I1&I3) ; - GTP_LUT5 /* N154_2 */ #( - .INIT(32'b00001111000000000000100000000000)) - N154_2 ( + GTP_LUT5 /* N154 */ #( + .INIT(32'b10100000000000001000000000000000)) + N154_vname ( .Z (N154), - .I0 (value[6]), - .I1 (_N3248), - .I2 (load_valid), - .I3 (N140), - .I4 (_N107229)); - // LUT = (~I2&I3&I4)|(I0&I1&~I2&I3) ; + .I0 (selected), + .I1 (changed_down), + .I2 (pressed_down), + .I3 (N153), + .I4 (pluse)); + // defparam N154_vname.orig_name = N154; + // LUT = (I0&I1&I2&I3)|(I0&I2&I3&I4) ; + // ../../sources/designs/others/param_cell_signed_loop.v:101 - GTP_LUT5 /* N156_1 */ #( - .INIT(32'b00001111000011110000100000001111)) - N156_1 ( - .Z (N153), - .I0 (value[6]), - .I1 (_N3248), - .I2 (load_valid), - .I3 (N140), - .I4 (_N107229)); - // LUT = (~I2&~I3)|(~I2&I4)|(I0&I1&~I2) ; + GTP_LUT4 /* N156_3 */ #( + .INIT(16'b1010000010000000)) + N156_3 ( + .Z (\param_manager_inst/param_osd_startX/N140 ), + .I0 (\param_manager_inst/selected [4] ), + .I1 (changed_down), + .I2 (pressed_down), + .I3 (\param_manager_inst/param_osd_startX/pluse )); + // LUT = (I0&I1&I2)|(I0&I2&I3) ; + + GTP_LUT5 /* N156_6 */ #( + .INIT(32'b00000010000000000000000000000000)) + N156_6 ( + .Z (_N108060), + .I0 (value[7]), + .I1 (value[8]), + .I2 (_N3248), + .I3 (selected), + .I4 (N72)); + // LUT = I0&~I1&~I2&I3&I4 ; GTP_DFF_E /* \cnt[0] */ #( .GRS_EN("TRUE"), @@ -90885,52 +90574,54 @@ endmodule module param_cell_signed_2 ( input [8:0] load_data, - input [11:0] param_offsetX, + input [13:0] \param_manager_inst/selected , + input [8:0] param_modify_H, input N72, - input N140, - input _N3647, - input _N104501, - input _N107262, - input _N107263, + input N153, + input _N3230, input changed_down, + input changed_up, input clk, input load_valid, - input \param_manager_inst/modify_V_load , - input \param_manager_inst/offsetX_load , - input \param_manager_inst/param_modify_V/N140 , - input \param_manager_inst/param_offsetX/N140 , + input \param_manager_inst/modify_H_load , + input \param_manager_inst/param_modify_H/N140 , + input \param_manager_inst/param_offsetX/pluse , + input \param_manager_inst/param_osd_startX/pluse , input pluse, input pressed_down, + input pressed_up, input rd2_rst, input restore, input selected, output [8:0] value, - output \param_manager_inst/param_modify_V/N153 , - output \param_manager_inst/param_offsetX/N153 + output N140, + output _N108109, + output _N108110, + output \param_manager_inst/param_modify_H/N153 , + output \param_manager_inst/param_offsetX/N140 , + output \param_manager_inst/param_osd_startX/N142 ); wire N76; + wire N142; wire N149; wire N150; wire [8:0] N151; - wire N153; wire N154; - wire _N13942; - wire _N13943; - wire _N13944; - wire _N13945; - wire _N13946; - wire _N13947; - wire _N13948; + wire _N13893; + wire _N13894; + wire _N13895; + wire _N13896; + wire _N13897; + wire _N13898; + wire _N13899; wire _N27116_inv; - wire _N107281; - wire _N107282; - wire _N107290; + wire _N108118; wire [8:0] nb0; GTP_LUT4 /* N63_mux8_6 */ #( .INIT(16'b1111111111111110)) N63_mux8_6 ( - .Z (_N107281), + .Z (_N108109), .I0 (value[1]), .I1 (value[2]), .I2 (value[3]), @@ -90940,7 +90631,7 @@ module param_cell_signed_2 GTP_LUT4 /* N63_mux8_7 */ #( .INIT(16'b1111111011111111)) N63_mux8_7 ( - .Z (_N107282), + .Z (_N108110), .I0 (value[5]), .I1 (value[6]), .I2 (value[7]), @@ -90950,7 +90641,7 @@ module param_cell_signed_2 GTP_LUT5 /* N76_mux8_8 */ #( .INIT(32'b11111111111111110111111111111111)) N76_mux8_8 ( - .Z (_N107290), + .Z (_N108118), .I0 (value[0]), .I1 (value[1]), .I2 (value[6]), @@ -90966,28 +90657,52 @@ module param_cell_signed_2 .I1 (value[3]), .I2 (value[4]), .I3 (value[5]), - .I4 (_N107290)); + .I4 (_N108118)); // LUT = (~I3)|(~I2)|(~I1)|(~I0)|(I4) ; - GTP_LUT4 /* N139_2 */ #( - .INIT(16'b0101010101010001)) - N139_2 ( - .Z (N153), - .I0 (load_valid), - .I1 (N140), - .I2 (_N107281), - .I3 (_N107282)); - // LUT = (~I0&~I1)|(~I0&I2)|(~I0&I3) ; + GTP_LUT4 /* N139_4 */ #( + .INIT(16'b1010000010000000)) + N139_4 ( + .Z (\param_manager_inst/param_osd_startX/N142 ), + .I0 (\param_manager_inst/selected [4] ), + .I1 (changed_up), + .I2 (pressed_up), + .I3 (\param_manager_inst/param_osd_startX/pluse )); + // LUT = (I0&I1&I2)|(I0&I2&I3) ; - GTP_LUT4 /* N148_2 */ #( - .INIT(16'b0101010101010001)) - N148_2 ( - .Z (\param_manager_inst/param_modify_V/N153 ), - .I0 (\param_manager_inst/modify_V_load ), - .I1 (\param_manager_inst/param_modify_V/N140 ), - .I2 (_N107262), - .I3 (_N107263)); - // LUT = (~I0&~I1)|(~I0&I2)|(~I0&I3) ; + GTP_LUT4 /* N140 */ #( + .INIT(16'b1010000010000000)) + N140_vname ( + .Z (N140), + .I0 (selected), + .I1 (changed_down), + .I2 (pressed_down), + .I3 (pluse)); + // defparam N140_vname.orig_name = N140; + // LUT = (I0&I1&I2)|(I0&I2&I3) ; + // ../../sources/designs/others/param_cell_signed.v:123 + + GTP_LUT4 /* N142 */ #( + .INIT(16'b1010000010000000)) + N142_vname ( + .Z (N142), + .I0 (selected), + .I1 (changed_up), + .I2 (pressed_up), + .I3 (pluse)); + // defparam N142_vname.orig_name = N142; + // LUT = (I0&I1&I2)|(I0&I2&I3) ; + // ../../sources/designs/others/param_cell_signed.v:130 + + GTP_LUT4 /* N148_1 */ #( + .INIT(16'b1010000010000000)) + N148_1 ( + .Z (\param_manager_inst/param_offsetX/N140 ), + .I0 (\param_manager_inst/selected [9] ), + .I1 (changed_down), + .I2 (pressed_down), + .I3 (\param_manager_inst/param_offsetX/pluse )); + // LUT = (I0&I1&I2)|(I0&I2&I3) ; GTP_LUT4 /* N149 */ #( .INIT(16'b1011101010101010)) @@ -91001,9 +90716,9 @@ module param_cell_signed_2 // LUT = (I0)|(~I1&I2&I3) ; // ../../sources/designs/others/param_cell_signed.v:22 - GTP_LUT4 /* N150_1 */ #( + GTP_LUT4 /* N150_3 */ #( .INIT(16'b1111111111101010)) - N150_1 ( + N150_3 ( .Z (N150), .I0 (load_valid), .I1 (selected), @@ -91018,7 +90733,7 @@ module param_cell_signed_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N151_10_1 ( - .COUT (_N13942), + .COUT (_N13893), .Z (nb0[1]), .CIN (), .I0 (value[0]), @@ -91037,9 +90752,9 @@ module param_cell_signed_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N151_10_2 ( - .COUT (_N13943), + .COUT (_N13894), .Z (nb0[2]), - .CIN (_N13942), + .CIN (_N13893), .I0 (value[0]), .I1 (N154), .I2 (value[1]), @@ -91056,9 +90771,9 @@ module param_cell_signed_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N151_10_3 ( - .COUT (_N13944), + .COUT (_N13895), .Z (nb0[3]), - .CIN (_N13943), + .CIN (_N13894), .I0 (), .I1 (N154), .I2 (value[3]), @@ -91075,9 +90790,9 @@ module param_cell_signed_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N151_10_4 ( - .COUT (_N13945), + .COUT (_N13896), .Z (nb0[4]), - .CIN (_N13944), + .CIN (_N13895), .I0 (), .I1 (N154), .I2 (value[4]), @@ -91094,9 +90809,9 @@ module param_cell_signed_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N151_10_5 ( - .COUT (_N13946), + .COUT (_N13897), .Z (nb0[5]), - .CIN (_N13945), + .CIN (_N13896), .I0 (), .I1 (N154), .I2 (value[5]), @@ -91113,9 +90828,9 @@ module param_cell_signed_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N151_10_6 ( - .COUT (_N13947), + .COUT (_N13898), .Z (nb0[6]), - .CIN (_N13946), + .CIN (_N13897), .I0 (), .I1 (N154), .I2 (value[6]), @@ -91132,9 +90847,9 @@ module param_cell_signed_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N151_10_7 ( - .COUT (_N13948), + .COUT (_N13899), .Z (nb0[7]), - .CIN (_N13947), + .CIN (_N13898), .I0 (), .I1 (N154), .I2 (value[7]), @@ -91153,7 +90868,7 @@ module param_cell_signed_2 N151_10_8 ( .COUT (), .Z (nb0[8]), - .CIN (_N13948), + .CIN (_N13899), .I0 (), .I1 (N154), .I2 (value[8]), @@ -91164,15 +90879,15 @@ module param_cell_signed_2 // CARRY = (I2^I1) ? CIN : (I4) ; GTP_LUT5 /* N151_19 */ #( - .INIT(32'b10101010101010101010101011101010)) + .INIT(32'b10101011101010101010101010101010)) N151_19 ( .Z (_N27116_inv), .I0 (load_valid), - .I1 (selected), - .I2 (N72), - .I3 (N76), - .I4 (N140)); - // LUT = (I0)|(I1&I2&~I3&~I4) ; + .I1 (N76), + .I2 (N140), + .I3 (N142), + .I4 (N153)); + // LUT = (I0)|(~I1&~I2&I3&I4) ; GTP_LUT4 /* \N151_30[0] */ #( .INIT(16'b1111101000111111)) @@ -91264,6 +90979,17 @@ module param_cell_signed_2 .I3 (_N27116_inv)); // LUT = (~I1&~I3)|(I2&~I3)|(I0&~I1) ; + GTP_LUT5 /* N151_32 */ #( + .INIT(32'b00000000111110110000000011111111)) + N151_32 ( + .Z (\param_manager_inst/param_modify_H/N153 ), + .I0 (param_modify_H[7]), + .I1 (param_modify_H[8]), + .I2 (_N3230), + .I3 (\param_manager_inst/modify_H_load ), + .I4 (\param_manager_inst/param_modify_H/N140 )); + // LUT = (~I3&~I4)|(~I1&~I3)|(I0&~I3)|(I2&~I3) ; + GTP_LUT5 /* N154 */ #( .INIT(32'b10100000100000000000000000000000)) N154_vname ( @@ -91277,17 +91003,6 @@ module param_cell_signed_2 // LUT = (I0&I1&I2&I4)|(I0&I2&I3&I4) ; // ../../sources/designs/others/param_cell_signed.v:101 - GTP_LUT5 /* N156_1 */ #( - .INIT(32'b00001111000011110000100000001111)) - N156_1 ( - .Z (\param_manager_inst/param_offsetX/N153 ), - .I0 (param_offsetX[7]), - .I1 (_N3647), - .I2 (\param_manager_inst/offsetX_load ), - .I3 (\param_manager_inst/param_offsetX/N140 ), - .I4 (_N104501)); - // LUT = (~I2&~I3)|(~I2&I4)|(I0&I1&~I2) ; - GTP_DFF_RE /* \value[0] */ #( .GRS_EN("TRUE"), .INIT(1'b0)) @@ -91395,49 +91110,48 @@ module param_cell_signed_2_unq4 ( input [8:0] load_data, input [13:0] \param_manager_inst/selected , - input [11:0] param_offsetY, input N72, - input N140, input N153, - input _N3793, input changed_down, + input changed_up, input clk, input load_valid, - input \param_manager_inst/offsetY_load , - input \param_manager_inst/param_filiter1_mode/pluse , - input \param_manager_inst/param_offsetY/N140 , + input \param_manager_inst/param_offsetX/pluse , + input \param_manager_inst/param_osd_char_height/pluse , input pluse, input pressed_down, + input pressed_up, input rd2_rst, input restore, input selected, output [8:0] value, - output _N107262, - output _N107263, - output \param_manager_inst/param_filiter1_mode/N140 , - output \param_manager_inst/param_filiter2_mode/N140 , - output \param_manager_inst/param_offsetY/N153 + output N140, + output _N108087, + output _N108088, + output \param_manager_inst/param_offsetY/N140 , + output \param_manager_inst/param_osd_startY/N140 ); wire N76; + wire N142; wire N149; wire N150; wire [8:0] N151; wire N154; - wire _N14020; - wire _N14021; - wire _N14022; - wire _N14023; - wire _N14024; - wire _N14025; - wire _N14026; + wire _N13962; + wire _N13963; + wire _N13964; + wire _N13965; + wire _N13966; + wire _N13967; + wire _N13968; wire _N27159_inv; - wire _N107271; + wire _N108096; wire [8:0] nb0; GTP_LUT4 /* N63_mux8_6 */ #( .INIT(16'b1111111111111110)) N63_mux8_6 ( - .Z (_N107262), + .Z (_N108087), .I0 (value[1]), .I1 (value[2]), .I2 (value[3]), @@ -91447,7 +91161,7 @@ module param_cell_signed_2_unq4 GTP_LUT4 /* N63_mux8_7 */ #( .INIT(16'b1111111011111111)) N63_mux8_7 ( - .Z (_N107263), + .Z (_N108088), .I0 (value[5]), .I1 (value[6]), .I2 (value[7]), @@ -91457,7 +91171,7 @@ module param_cell_signed_2_unq4 GTP_LUT5 /* N76_mux8_8 */ #( .INIT(32'b11111111111111110111111111111111)) N76_mux8_8 ( - .Z (_N107271), + .Z (_N108096), .I0 (value[0]), .I1 (value[1]), .I2 (value[6]), @@ -91473,29 +91187,42 @@ module param_cell_signed_2_unq4 .I1 (value[3]), .I2 (value[4]), .I3 (value[5]), - .I4 (_N107271)); + .I4 (_N108096)); // LUT = (~I3)|(~I2)|(~I1)|(~I0)|(I4) ; - GTP_LUT5 /* N139_1 */ #( - .INIT(32'b00000000111110110000000011111111)) + GTP_LUT4 /* N139_1 */ #( + .INIT(16'b1010000010000000)) N139_1 ( - .Z (\param_manager_inst/param_offsetY/N153 ), - .I0 (param_offsetY[10]), - .I1 (param_offsetY[11]), - .I2 (_N3793), - .I3 (\param_manager_inst/offsetY_load ), - .I4 (\param_manager_inst/param_offsetY/N140 )); - // LUT = (~I3&~I4)|(~I1&~I3)|(I0&~I3)|(I2&~I3) ; + .Z (\param_manager_inst/param_offsetY/N140 ), + .I0 (\param_manager_inst/selected [10] ), + .I1 (changed_down), + .I2 (pressed_down), + .I3 (\param_manager_inst/param_offsetX/pluse )); + // LUT = (I0&I1&I2)|(I0&I2&I3) ; - GTP_LUT4 /* N148_1 */ #( - .INIT(16'b1010100000000000)) - N148_1 ( - .Z (\param_manager_inst/param_filiter1_mode/N140 ), - .I0 (\param_manager_inst/selected [0] ), + GTP_LUT4 /* N140 */ #( + .INIT(16'b1010000010000000)) + N140_vname ( + .Z (N140), + .I0 (selected), .I1 (changed_down), - .I2 (\param_manager_inst/param_filiter1_mode/pluse ), - .I3 (pressed_down)); - // LUT = (I0&I1&I3)|(I0&I2&I3) ; + .I2 (pressed_down), + .I3 (pluse)); + // defparam N140_vname.orig_name = N140; + // LUT = (I0&I1&I2)|(I0&I2&I3) ; + // ../../sources/designs/others/param_cell_signed.v:123 + + GTP_LUT4 /* N142 */ #( + .INIT(16'b1010000010000000)) + N142_vname ( + .Z (N142), + .I0 (selected), + .I1 (changed_up), + .I2 (pressed_up), + .I3 (pluse)); + // defparam N142_vname.orig_name = N142; + // LUT = (I0&I1&I2)|(I0&I2&I3) ; + // ../../sources/designs/others/param_cell_signed.v:130 GTP_LUT4 /* N149 */ #( .INIT(16'b1011101010101010)) @@ -91509,9 +91236,9 @@ module param_cell_signed_2_unq4 // LUT = (I0)|(~I1&I2&I3) ; // ../../sources/designs/others/param_cell_signed.v:22 - GTP_LUT4 /* N150_1 */ #( + GTP_LUT4 /* N150_3 */ #( .INIT(16'b1111111111101010)) - N150_1 ( + N150_3 ( .Z (N150), .I0 (load_valid), .I1 (selected), @@ -91526,7 +91253,7 @@ module param_cell_signed_2_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N151_10_1 ( - .COUT (_N14020), + .COUT (_N13962), .Z (nb0[1]), .CIN (), .I0 (value[0]), @@ -91545,9 +91272,9 @@ module param_cell_signed_2_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N151_10_2 ( - .COUT (_N14021), + .COUT (_N13963), .Z (nb0[2]), - .CIN (_N14020), + .CIN (_N13962), .I0 (value[0]), .I1 (N154), .I2 (value[1]), @@ -91564,9 +91291,9 @@ module param_cell_signed_2_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N151_10_3 ( - .COUT (_N14022), + .COUT (_N13964), .Z (nb0[3]), - .CIN (_N14021), + .CIN (_N13963), .I0 (), .I1 (N154), .I2 (value[3]), @@ -91583,9 +91310,9 @@ module param_cell_signed_2_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N151_10_4 ( - .COUT (_N14023), + .COUT (_N13965), .Z (nb0[4]), - .CIN (_N14022), + .CIN (_N13964), .I0 (), .I1 (N154), .I2 (value[4]), @@ -91602,9 +91329,9 @@ module param_cell_signed_2_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N151_10_5 ( - .COUT (_N14024), + .COUT (_N13966), .Z (nb0[5]), - .CIN (_N14023), + .CIN (_N13965), .I0 (), .I1 (N154), .I2 (value[5]), @@ -91621,9 +91348,9 @@ module param_cell_signed_2_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N151_10_6 ( - .COUT (_N14025), + .COUT (_N13967), .Z (nb0[6]), - .CIN (_N14024), + .CIN (_N13966), .I0 (), .I1 (N154), .I2 (value[6]), @@ -91640,9 +91367,9 @@ module param_cell_signed_2_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N151_10_7 ( - .COUT (_N14026), + .COUT (_N13968), .Z (nb0[7]), - .CIN (_N14025), + .CIN (_N13967), .I0 (), .I1 (N154), .I2 (value[7]), @@ -91661,7 +91388,7 @@ module param_cell_signed_2_unq4 N151_10_8 ( .COUT (), .Z (nb0[8]), - .CIN (_N14026), + .CIN (_N13968), .I0 (), .I1 (N154), .I2 (value[8]), @@ -91672,15 +91399,15 @@ module param_cell_signed_2_unq4 // CARRY = (I2^I1) ? CIN : (I4) ; GTP_LUT5 /* N151_19 */ #( - .INIT(32'b10101010101010101010101011101010)) + .INIT(32'b10101011101010101010101010101010)) N151_19 ( .Z (_N27159_inv), .I0 (load_valid), - .I1 (selected), - .I2 (N72), - .I3 (N76), - .I4 (N140)); - // LUT = (I0)|(I1&I2&~I3&~I4) ; + .I1 (N76), + .I2 (N140), + .I3 (N142), + .I4 (N153)); + // LUT = (I0)|(~I1&~I2&I3&I4) ; GTP_LUT4 /* \N151_30[0] */ #( .INIT(16'b1111101000111111)) @@ -91786,14 +91513,14 @@ module param_cell_signed_2_unq4 // ../../sources/designs/others/param_cell_signed.v:101 GTP_LUT4 /* N156_1 */ #( - .INIT(16'b1010100000000000)) + .INIT(16'b1010000010000000)) N156_1 ( - .Z (\param_manager_inst/param_filiter2_mode/N140 ), - .I0 (\param_manager_inst/selected [1] ), + .Z (\param_manager_inst/param_osd_startY/N140 ), + .I0 (\param_manager_inst/selected [5] ), .I1 (changed_down), - .I2 (\param_manager_inst/param_filiter1_mode/pluse ), - .I3 (pressed_down)); - // LUT = (I0&I1&I3)|(I0&I2&I3) ; + .I2 (pressed_down), + .I3 (\param_manager_inst/param_osd_char_height/pluse )); + // LUT = (I0&I1&I2)|(I0&I2&I3) ; GTP_DFF_RE /* \value[0] */ #( .GRS_EN("TRUE"), @@ -91904,6 +91631,7 @@ module param_cell_signed input [13:0] \param_manager_inst/selected , input N116, input N119, + input N140, input N153, input N160, input changed_down, @@ -91911,7 +91639,7 @@ module param_cell_signed input clk, input \key_debounce_inst2/pluse_ms , input load_valid, - input \param_manager_inst/param_osd_startX/pluse , + input \param_manager_inst/param_osd_char_height/pluse , input pressed_down, input pressed_up, input rd2_rst, @@ -91919,11 +91647,9 @@ module param_cell_signed input selected, output [11:0] value, output N72, - output N140, - output _N3647, - output _N104501, - output \param_manager_inst/param_osd_startX/N140 , - output \param_manager_inst/param_osd_startX/N142 , + output _N3669, + output _N105338, + output \param_manager_inst/param_osd_char_width/N140 , output pluse ); wire [11:0] \N26_1.co ; @@ -91937,21 +91663,21 @@ module param_cell_signed wire [11:0] N151; wire N154; wire [11:0] N166; - wire _N15151; - wire _N15152; - wire _N15153; - wire _N15154; - wire _N15155; - wire _N15156; - wire _N15157; - wire _N15158; - wire _N15159; - wire _N15160; + wire _N15356; + wire _N15357; + wire _N15358; + wire _N15359; + wire _N15360; + wire _N15361; + wire _N15362; + wire _N15363; + wire _N15364; + wire _N15365; wire _N27202_inv; - wire _N29719; - wire _N104483; - wire _N104485; - wire _N104496; + wire _N29694; + wire _N105320; + wire _N105322; + wire _N105333; wire [11:0] cnt; wire [11:0] nb0; @@ -92023,7 +91749,7 @@ module param_cell_signed .I4_TO_LUT("FALSE")) \N26_1.fsub_4 ( .COUT (\N26_1.co [4] ), - .Z (_N29719), + .Z (_N29694), .CIN (\N26_1.co [3] ), .I0 (), .I1 (cnt[4]), @@ -92188,7 +91914,7 @@ module param_cell_signed GTP_LUT3 /* N63_mux6_5 */ #( .INIT(8'b11111110)) N63_mux6_5 ( - .Z (_N104496), + .Z (_N105333), .I0 (value[0]), .I1 (value[1]), .I2 (value[6])); @@ -92197,18 +91923,18 @@ module param_cell_signed GTP_LUT5 /* N63_mux6_7 */ #( .INIT(32'b11111111111111111111111111111110)) N63_mux6_7 ( - .Z (_N3647), + .Z (_N3669), .I0 (value[2]), .I1 (value[3]), .I2 (value[4]), .I3 (value[5]), - .I4 (_N104496)); + .I4 (_N105333)); // LUT = (I0)|(I1)|(I2)|(I3)|(I4) ; GTP_LUT4 /* N63_mux11_4 */ #( .INIT(16'b1111111011111111)) N63_mux11_4 ( - .Z (_N104501), + .Z (_N105338), .I0 (value[8]), .I1 (value[9]), .I2 (value[10]), @@ -92240,7 +91966,7 @@ module param_cell_signed GTP_LUT4 /* N102_9 */ #( .INIT(16'b0000000000000001)) N102_9 ( - .Z (_N104483), + .Z (_N105320), .I0 (cnt[4]), .I1 (cnt[5]), .I2 (cnt[6]), @@ -92250,12 +91976,12 @@ module param_cell_signed GTP_LUT5 /* N102_11 */ #( .INIT(32'b00000000000000010000000000000000)) N102_11 ( - .Z (_N104485), + .Z (_N105322), .I0 (cnt[0]), .I1 (cnt[1]), .I2 (cnt[2]), .I3 (cnt[3]), - .I4 (_N104483)); + .I4 (_N105320)); // LUT = ~I0&~I1&~I2&~I3&I4 ; GTP_LUT5 /* N102_12 */ #( @@ -92266,7 +91992,7 @@ module param_cell_signed .I1 (cnt[9]), .I2 (cnt[10]), .I3 (cnt[11]), - .I4 (_N104485)); + .I4 (_N105322)); // LUT = ~I0&~I1&~I2&~I3&I4 ; GTP_LUT2 /* \N117_and[0][2] */ #( @@ -92307,7 +92033,7 @@ module param_cell_signed \N117_or[4] ( .Z (N117[4]), .I0 (N160), - .I1 (_N29719)); + .I1 (_N29694)); // LUT = (I0)|(I1) ; GTP_LUT5 /* N122 */ #( @@ -92322,24 +92048,14 @@ module param_cell_signed // defparam N122_vname.orig_name = N122; // LUT = (I0&I1&I2&~I4)|(I0&I1&I3&~I4) ; - GTP_LUT4 /* N139_3 */ #( + GTP_LUT4 /* N148_1 */ #( .INIT(16'b1010000010000000)) - N139_3 ( - .Z (\param_manager_inst/param_osd_startX/N140 ), - .I0 (\param_manager_inst/selected [4] ), + N148_1 ( + .Z (\param_manager_inst/param_osd_char_width/N140 ), + .I0 (\param_manager_inst/selected [6] ), .I1 (changed_down), .I2 (pressed_down), - .I3 (\param_manager_inst/param_osd_startX/pluse )); - // LUT = (I0&I1&I2)|(I0&I2&I3) ; - - GTP_LUT4 /* N148_3 */ #( - .INIT(16'b1010000010000000)) - N148_3 ( - .Z (\param_manager_inst/param_osd_startX/N142 ), - .I0 (\param_manager_inst/selected [4] ), - .I1 (changed_up), - .I2 (pressed_up), - .I3 (\param_manager_inst/param_osd_startX/pluse )); + .I3 (\param_manager_inst/param_osd_char_height/pluse )); // LUT = (I0&I1&I2)|(I0&I2&I3) ; GTP_LUT4 /* N149 */ #( @@ -92371,7 +92087,7 @@ module param_cell_signed .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N151_10_1 ( - .COUT (_N15151), + .COUT (_N15356), .Z (nb0[1]), .CIN (), .I0 (value[0]), @@ -92390,9 +92106,9 @@ module param_cell_signed .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N151_10_2 ( - .COUT (_N15152), + .COUT (_N15357), .Z (nb0[2]), - .CIN (_N15151), + .CIN (_N15356), .I0 (value[0]), .I1 (N154), .I2 (value[1]), @@ -92409,9 +92125,9 @@ module param_cell_signed .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N151_10_3 ( - .COUT (_N15153), + .COUT (_N15358), .Z (nb0[3]), - .CIN (_N15152), + .CIN (_N15357), .I0 (), .I1 (N154), .I2 (value[3]), @@ -92428,9 +92144,9 @@ module param_cell_signed .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N151_10_4 ( - .COUT (_N15154), + .COUT (_N15359), .Z (nb0[4]), - .CIN (_N15153), + .CIN (_N15358), .I0 (), .I1 (N154), .I2 (value[4]), @@ -92447,9 +92163,9 @@ module param_cell_signed .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N151_10_5 ( - .COUT (_N15155), + .COUT (_N15360), .Z (nb0[5]), - .CIN (_N15154), + .CIN (_N15359), .I0 (), .I1 (N154), .I2 (value[5]), @@ -92466,9 +92182,9 @@ module param_cell_signed .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N151_10_6 ( - .COUT (_N15156), + .COUT (_N15361), .Z (nb0[6]), - .CIN (_N15155), + .CIN (_N15360), .I0 (), .I1 (N154), .I2 (value[6]), @@ -92485,9 +92201,9 @@ module param_cell_signed .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N151_10_7 ( - .COUT (_N15157), + .COUT (_N15362), .Z (nb0[7]), - .CIN (_N15156), + .CIN (_N15361), .I0 (), .I1 (N154), .I2 (value[7]), @@ -92504,9 +92220,9 @@ module param_cell_signed .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N151_10_8 ( - .COUT (_N15158), + .COUT (_N15363), .Z (nb0[8]), - .CIN (_N15157), + .CIN (_N15362), .I0 (), .I1 (N154), .I2 (value[8]), @@ -92523,9 +92239,9 @@ module param_cell_signed .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N151_10_9 ( - .COUT (_N15159), + .COUT (_N15364), .Z (nb0[9]), - .CIN (_N15158), + .CIN (_N15363), .I0 (), .I1 (N154), .I2 (value[9]), @@ -92542,9 +92258,9 @@ module param_cell_signed .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N151_10_10 ( - .COUT (_N15160), + .COUT (_N15365), .Z (nb0[10]), - .CIN (_N15159), + .CIN (_N15364), .I0 (), .I1 (N154), .I2 (value[10]), @@ -92563,7 +92279,7 @@ module param_cell_signed N151_10_11 ( .COUT (), .Z (nb0[11]), - .CIN (_N15160), + .CIN (_N15365), .I0 (), .I1 (N154), .I2 (value[11]), @@ -92709,22 +92425,12 @@ module param_cell_signed N154_2 ( .Z (N154), .I0 (value[7]), - .I1 (_N3647), + .I1 (_N3669), .I2 (load_valid), .I3 (N140), - .I4 (_N104501)); + .I4 (_N105338)); // LUT = (~I2&I3&I4)|(I0&I1&~I2&I3) ; - GTP_LUT4 /* N156_1 */ #( - .INIT(16'b1010000010000000)) - N156_1 ( - .Z (N140), - .I0 (selected), - .I1 (changed_down), - .I2 (pressed_down), - .I3 (pluse)); - // LUT = (I0&I1&I2)|(I0&I2&I3) ; - GTP_DFF_E /* \cnt[0] */ #( .GRS_EN("TRUE"), .INIT(1'b0)) @@ -92995,45 +92701,47 @@ endmodule module param_cell_signed_1 ( input [11:0] load_data, + input [13:0] \param_manager_inst/selected , input N72, + input N140, input N153, input changed_down, input clk, input load_valid, - input pluse, + input \param_manager_inst/param_osd_char_height/pluse , input pressed_down, input rd2_rst, input restore, input selected, output [11:0] value, - output N140, - output _N3793 + output _N3811, + output \param_manager_inst/param_osd_char_height/N140 ); wire N76; wire N149; wire N150; wire [11:0] N151; wire N154; - wire _N3781; - wire _N3785; - wire _N15247; - wire _N15248; - wire _N15249; - wire _N15250; - wire _N15251; - wire _N15252; - wire _N15253; - wire _N15254; - wire _N15255; - wire _N15256; + wire _N3799; + wire _N3803; + wire _N15514; + wire _N15515; + wire _N15516; + wire _N15517; + wire _N15518; + wire _N15519; + wire _N15520; + wire _N15521; + wire _N15522; + wire _N15523; wire _N27254_inv; - wire _N104598; + wire _N105433; wire [11:0] nb0; GTP_LUT4 /* N63_mux3 */ #( .INIT(16'b1111111000000000)) N63_mux3 ( - .Z (_N3781), + .Z (_N3799), .I0 (value[0]), .I1 (value[1]), .I2 (value[2]), @@ -93043,27 +92751,27 @@ module param_cell_signed_1 GTP_LUT3 /* N63_mux5_3 */ #( .INIT(8'b11111110)) N63_mux5_3 ( - .Z (_N3785), + .Z (_N3803), .I0 (value[4]), .I1 (value[5]), - .I2 (_N3781)); + .I2 (_N3799)); // LUT = (I0)|(I1)|(I2) ; GTP_LUT5 /* N63_mux9_5 */ #( .INIT(32'b10000000000000000000000000000000)) N63_mux9_5 ( - .Z (_N3793), + .Z (_N3811), .I0 (value[6]), .I1 (value[7]), .I2 (value[8]), .I3 (value[9]), - .I4 (_N3785)); + .I4 (_N3803)); // LUT = I0&I1&I2&I3&I4 ; GTP_LUT5 /* N76_mux6_4 */ #( .INIT(32'b00000000000000000000000001111111)) N76_mux6_4 ( - .Z (_N104598), + .Z (_N105433), .I0 (value[3]), .I1 (value[4]), .I2 (value[5]), @@ -93079,17 +92787,17 @@ module param_cell_signed_1 .I1 (value[9]), .I2 (value[10]), .I3 (value[11]), - .I4 (_N104598)); + .I4 (_N105433)); // LUT = (~I2)|(I3)|(~I0&~I1&I4) ; GTP_LUT4 /* N148_1 */ #( .INIT(16'b1010000010000000)) N148_1 ( - .Z (N140), - .I0 (selected), + .Z (\param_manager_inst/param_osd_char_height/N140 ), + .I0 (\param_manager_inst/selected [7] ), .I1 (changed_down), .I2 (pressed_down), - .I3 (pluse)); + .I3 (\param_manager_inst/param_osd_char_height/pluse )); // LUT = (I0&I1&I2)|(I0&I2&I3) ; GTP_LUT4 /* N149 */ #( @@ -93121,7 +92829,7 @@ module param_cell_signed_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N151_10_1 ( - .COUT (_N15247), + .COUT (_N15514), .Z (nb0[1]), .CIN (), .I0 (value[0]), @@ -93140,9 +92848,9 @@ module param_cell_signed_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N151_10_2 ( - .COUT (_N15248), + .COUT (_N15515), .Z (nb0[2]), - .CIN (_N15247), + .CIN (_N15514), .I0 (value[0]), .I1 (N154), .I2 (value[1]), @@ -93159,9 +92867,9 @@ module param_cell_signed_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N151_10_3 ( - .COUT (_N15249), + .COUT (_N15516), .Z (nb0[3]), - .CIN (_N15248), + .CIN (_N15515), .I0 (), .I1 (N154), .I2 (value[3]), @@ -93178,9 +92886,9 @@ module param_cell_signed_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N151_10_4 ( - .COUT (_N15250), + .COUT (_N15517), .Z (nb0[4]), - .CIN (_N15249), + .CIN (_N15516), .I0 (), .I1 (N154), .I2 (value[4]), @@ -93197,9 +92905,9 @@ module param_cell_signed_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N151_10_5 ( - .COUT (_N15251), + .COUT (_N15518), .Z (nb0[5]), - .CIN (_N15250), + .CIN (_N15517), .I0 (), .I1 (N154), .I2 (value[5]), @@ -93216,9 +92924,9 @@ module param_cell_signed_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N151_10_6 ( - .COUT (_N15252), + .COUT (_N15519), .Z (nb0[6]), - .CIN (_N15251), + .CIN (_N15518), .I0 (), .I1 (N154), .I2 (value[6]), @@ -93235,9 +92943,9 @@ module param_cell_signed_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N151_10_7 ( - .COUT (_N15253), + .COUT (_N15520), .Z (nb0[7]), - .CIN (_N15252), + .CIN (_N15519), .I0 (), .I1 (N154), .I2 (value[7]), @@ -93254,9 +92962,9 @@ module param_cell_signed_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N151_10_8 ( - .COUT (_N15254), + .COUT (_N15521), .Z (nb0[8]), - .CIN (_N15253), + .CIN (_N15520), .I0 (), .I1 (N154), .I2 (value[8]), @@ -93273,9 +92981,9 @@ module param_cell_signed_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N151_10_9 ( - .COUT (_N15255), + .COUT (_N15522), .Z (nb0[9]), - .CIN (_N15254), + .CIN (_N15521), .I0 (), .I1 (N154), .I2 (value[9]), @@ -93292,9 +93000,9 @@ module param_cell_signed_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N151_10_10 ( - .COUT (_N15256), + .COUT (_N15523), .Z (nb0[10]), - .CIN (_N15255), + .CIN (_N15522), .I0 (), .I1 (N154), .I2 (value[10]), @@ -93313,7 +93021,7 @@ module param_cell_signed_1 N151_10_11 ( .COUT (), .Z (nb0[11]), - .CIN (_N15256), + .CIN (_N15523), .I0 (), .I1 (N154), .I2 (value[11]), @@ -93460,7 +93168,7 @@ module param_cell_signed_1 .Z (N154), .I0 (value[10]), .I1 (value[11]), - .I2 (_N3793), + .I2 (_N3811), .I3 (load_valid), .I4 (N140)); // LUT = (~I1&~I3&I4)|(I0&~I3&I4)|(I2&~I3&I4) ; @@ -93604,14 +93312,12 @@ endmodule module param_cell_unsigned_4 ( input [10:0] load_data, - input [13:0] \param_manager_inst/selected , input N111, input N116, input N119, input N140, input N142, input N161, - input changed_down, input changed_up, input clk, input \key_debounce_inst2/pluse_ms , @@ -93623,8 +93329,6 @@ module param_cell_unsigned_4 input selected, output [10:0] value, output N72, - output \param_manager_inst/param_osd_char_width/N140 , - output \param_manager_inst/param_osd_startY/N140 , output pluse ); wire [11:0] \N26_1.co ; @@ -93639,22 +93343,22 @@ module param_cell_unsigned_4 wire N153; wire N154; wire [11:0] N167; - wire _N3927; - wire _N3949; - wire _N15506; - wire _N15507; - wire _N15508; - wire _N15509; - wire _N15510; - wire _N15511; - wire _N15512; - wire _N15513; - wire _N15514; - wire _N95979_inv; - wire _N107054; - wire _N107056; - wire _N107151; - wire _N107154; + wire _N3939; + wire _N3961; + wire _N15664; + wire _N15665; + wire _N15666; + wire _N15667; + wire _N15668; + wire _N15669; + wire _N15670; + wire _N15671; + wire _N15672; + wire _N97022_inv; + wire _N107876; + wire _N107878; + wire _N107973; + wire _N107976; wire [11:0] cnt; wire [10:0] nb0; @@ -93891,7 +93595,7 @@ module param_cell_unsigned_4 GTP_LUT5 /* N63_mux4 */ #( .INIT(32'b11111111111110000000000000000000)) N63_mux4 ( - .Z (_N3927), + .Z (_N3939), .I0 (value[0]), .I1 (value[1]), .I2 (value[2]), @@ -93902,7 +93606,7 @@ module param_cell_unsigned_4 GTP_LUT2 /* N63_mux10_4 */ #( .INIT(4'b1110)) N63_mux10_4 ( - .Z (_N107151), + .Z (_N107973), .I0 (value[9]), .I1 (value[10])); // LUT = (I0)|(I1) ; @@ -93910,12 +93614,12 @@ module param_cell_unsigned_4 GTP_LUT5 /* N63_mux10_6 */ #( .INIT(32'b11111111111111111111111111111110)) N63_mux10_6 ( - .Z (_N107154), + .Z (_N107976), .I0 (value[5]), .I1 (value[6]), .I2 (value[7]), .I3 (value[8]), - .I4 (_N107151)); + .I4 (_N107973)); // LUT = (I0)|(I1)|(I2)|(I3)|(I4) ; GTP_LUT3 /* N72 */ #( @@ -93932,7 +93636,7 @@ module param_cell_unsigned_4 GTP_LUT5 /* N76_mux4_3 */ #( .INIT(32'b00000001111111111111111111111111)) N76_mux4_3 ( - .Z (_N3949), + .Z (_N3961), .I0 (value[2]), .I1 (value[3]), .I2 (value[4]), @@ -93948,13 +93652,13 @@ module param_cell_unsigned_4 .I1 (value[8]), .I2 (value[9]), .I3 (value[10]), - .I4 (_N3949)); + .I4 (_N3961)); // LUT = ~I0&~I1&~I2&~I3&I4 ; GTP_LUT4 /* N102_9 */ #( .INIT(16'b0000000000000001)) N102_9 ( - .Z (_N107054), + .Z (_N107876), .I0 (cnt[4]), .I1 (cnt[5]), .I2 (cnt[6]), @@ -93964,12 +93668,12 @@ module param_cell_unsigned_4 GTP_LUT5 /* N102_11 */ #( .INIT(32'b00000000000000010000000000000000)) N102_11 ( - .Z (_N107056), + .Z (_N107878), .I0 (cnt[0]), .I1 (cnt[1]), .I2 (cnt[2]), .I3 (cnt[3]), - .I4 (_N107054)); + .I4 (_N107876)); // LUT = ~I0&~I1&~I2&~I3&I4 ; GTP_LUT5 /* N102_12 */ #( @@ -93980,7 +93684,7 @@ module param_cell_unsigned_4 .I1 (cnt[9]), .I2 (cnt[10]), .I3 (cnt[11]), - .I4 (_N107056)); + .I4 (_N107878)); // LUT = ~I0&~I1&~I2&~I3&I4 ; GTP_LUT2 /* \N117_and[0][2] */ #( @@ -94064,16 +93768,6 @@ module param_cell_unsigned_4 // defparam N138_vname.orig_name = N138; // LUT = I0&I1 ; - GTP_LUT4 /* N139_1 */ #( - .INIT(16'b1010000010000000)) - N139_1 ( - .Z (\param_manager_inst/param_osd_startY/N140 ), - .I0 (\param_manager_inst/selected [5] ), - .I1 (changed_down), - .I2 (pressed_down), - .I3 (pluse)); - // LUT = (I0&I1&I2)|(I0&I2&I3) ; - GTP_LUT5 /* N148_4 */ #( .INIT(32'b11111111111111111111101011101010)) N148_4 ( @@ -94092,7 +93786,7 @@ module param_cell_unsigned_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_8_1 ( - .COUT (_N15506), + .COUT (_N15664), .Z (nb0[1]), .CIN (), .I0 (value[0]), @@ -94111,9 +93805,9 @@ module param_cell_unsigned_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_8_2 ( - .COUT (_N15507), + .COUT (_N15665), .Z (nb0[2]), - .CIN (_N15506), + .CIN (_N15664), .I0 (value[0]), .I1 (N154), .I2 (value[1]), @@ -94130,9 +93824,9 @@ module param_cell_unsigned_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_8_3 ( - .COUT (_N15508), + .COUT (_N15666), .Z (nb0[3]), - .CIN (_N15507), + .CIN (_N15665), .I0 (), .I1 (N154), .I2 (value[3]), @@ -94149,9 +93843,9 @@ module param_cell_unsigned_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_8_4 ( - .COUT (_N15509), + .COUT (_N15667), .Z (nb0[4]), - .CIN (_N15508), + .CIN (_N15666), .I0 (), .I1 (N154), .I2 (value[4]), @@ -94168,9 +93862,9 @@ module param_cell_unsigned_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_8_5 ( - .COUT (_N15510), + .COUT (_N15668), .Z (nb0[5]), - .CIN (_N15509), + .CIN (_N15667), .I0 (), .I1 (N154), .I2 (value[5]), @@ -94187,9 +93881,9 @@ module param_cell_unsigned_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_8_6 ( - .COUT (_N15511), + .COUT (_N15669), .Z (nb0[6]), - .CIN (_N15510), + .CIN (_N15668), .I0 (), .I1 (N154), .I2 (value[6]), @@ -94206,9 +93900,9 @@ module param_cell_unsigned_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_8_7 ( - .COUT (_N15512), + .COUT (_N15670), .Z (nb0[7]), - .CIN (_N15511), + .CIN (_N15669), .I0 (), .I1 (N154), .I2 (value[7]), @@ -94225,9 +93919,9 @@ module param_cell_unsigned_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_8_8 ( - .COUT (_N15513), + .COUT (_N15671), .Z (nb0[8]), - .CIN (_N15512), + .CIN (_N15670), .I0 (), .I1 (N154), .I2 (value[8]), @@ -94244,9 +93938,9 @@ module param_cell_unsigned_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_8_9 ( - .COUT (_N15514), + .COUT (_N15672), .Z (nb0[9]), - .CIN (_N15513), + .CIN (_N15671), .I0 (), .I1 (N154), .I2 (value[9]), @@ -94265,7 +93959,7 @@ module param_cell_unsigned_4 N149_8_10 ( .COUT (), .Z (nb0[10]), - .CIN (_N15514), + .CIN (_N15672), .I0 (), .I1 (N154), .I2 (value[10]), @@ -94282,7 +93976,7 @@ module param_cell_unsigned_4 .I0 (load_data[0]), .I1 (value[0]), .I2 (N153), - .I3 (_N95979_inv)); + .I3 (_N97022_inv)); // LUT = (~I1&I2&~I3)|(I0&~I2&I3) ; GTP_LUT4 /* \N149_27[1] */ #( @@ -94292,7 +93986,7 @@ module param_cell_unsigned_4 .I0 (load_data[1]), .I1 (N153), .I2 (nb0[1]), - .I3 (_N95979_inv)); + .I3 (_N97022_inv)); // LUT = (~I1&~I3)|(I2&~I3)|(I0&~I1) ; GTP_LUT4 /* \N149_27[2] */ #( @@ -94302,7 +93996,7 @@ module param_cell_unsigned_4 .I0 (load_data[2]), .I1 (N153), .I2 (nb0[2]), - .I3 (_N95979_inv)); + .I3 (_N97022_inv)); // LUT = (I0&I3)|(I1&I2)|(I1&I3) ; GTP_LUT4 /* \N149_27[3] */ #( @@ -94312,7 +94006,7 @@ module param_cell_unsigned_4 .I0 (load_data[3]), .I1 (N153), .I2 (nb0[3]), - .I3 (_N95979_inv)); + .I3 (_N97022_inv)); // LUT = (I1&I2&~I3)|(I0&~I1&I3) ; GTP_LUT4 /* \N149_27[4] */ #( @@ -94322,7 +94016,7 @@ module param_cell_unsigned_4 .I0 (load_data[4]), .I1 (N153), .I2 (nb0[4]), - .I3 (_N95979_inv)); + .I3 (_N97022_inv)); // LUT = (~I1&~I3)|(I2&~I3)|(I0&~I1) ; GTP_LUT4 /* \N149_27[5] */ #( @@ -94332,7 +94026,7 @@ module param_cell_unsigned_4 .I0 (load_data[5]), .I1 (N153), .I2 (nb0[5]), - .I3 (_N95979_inv)); + .I3 (_N97022_inv)); // LUT = (I0&I3)|(I1&I2)|(I1&I3) ; GTP_LUT4 /* \N149_27[6] */ #( @@ -94342,7 +94036,7 @@ module param_cell_unsigned_4 .I0 (load_data[6]), .I1 (N153), .I2 (nb0[6]), - .I3 (_N95979_inv)); + .I3 (_N97022_inv)); // LUT = (I0&I3)|(I1&I2)|(I1&I3) ; GTP_LUT4 /* \N149_27[7] */ #( @@ -94352,7 +94046,7 @@ module param_cell_unsigned_4 .I0 (load_data[7]), .I1 (N153), .I2 (nb0[7]), - .I3 (_N95979_inv)); + .I3 (_N97022_inv)); // LUT = (I1&I2&~I3)|(I0&~I1&I3) ; GTP_LUT4 /* \N149_27[8] */ #( @@ -94362,7 +94056,7 @@ module param_cell_unsigned_4 .I0 (load_data[8]), .I1 (N153), .I2 (nb0[8]), - .I3 (_N95979_inv)); + .I3 (_N97022_inv)); // LUT = (I1&I2&~I3)|(I0&~I1&I3) ; GTP_LUT4 /* \N149_27[9] */ #( @@ -94372,7 +94066,7 @@ module param_cell_unsigned_4 .I0 (load_data[9]), .I1 (N153), .I2 (nb0[9]), - .I3 (_N95979_inv)); + .I3 (_N97022_inv)); // LUT = (I1&I2&~I3)|(I0&~I1&I3) ; GTP_LUT4 /* \N149_27[10] */ #( @@ -94382,13 +94076,13 @@ module param_cell_unsigned_4 .I0 (load_data[10]), .I1 (N153), .I2 (nb0[10]), - .I3 (_N95979_inv)); + .I3 (_N97022_inv)); // LUT = (I1&I2&~I3)|(I0&~I1&I3) ; GTP_LUT5 /* N149_28 */ #( .INIT(32'b10101011101010101010101010101010)) N149_28 ( - .Z (_N95979_inv), + .Z (_N97022_inv), .I0 (load_valid), .I1 (N76), .I2 (N140), @@ -94400,11 +94094,11 @@ module param_cell_unsigned_4 .INIT(32'b00000011000000110000001000000011)) N153_vname ( .Z (N153), - .I0 (_N3927), + .I0 (_N3939), .I1 (load_valid), .I2 (N138), .I3 (N140), - .I4 (_N107154)); + .I4 (_N107976)); // defparam N153_vname.orig_name = N153; // LUT = (~I1&~I2&~I3)|(I0&~I1&~I2)|(~I1&~I2&I4) ; @@ -94412,23 +94106,13 @@ module param_cell_unsigned_4 .INIT(32'b00000011000000000000001000000000)) N154_2 ( .Z (N154), - .I0 (_N3927), + .I0 (_N3939), .I1 (load_valid), .I2 (N138), .I3 (N140), - .I4 (_N107154)); + .I4 (_N107976)); // LUT = (I0&~I1&~I2&I3)|(~I1&~I2&I3&I4) ; - GTP_LUT4 /* N156_1 */ #( - .INIT(16'b1010000010000000)) - N156_1 ( - .Z (\param_manager_inst/param_osd_char_width/N140 ), - .I0 (\param_manager_inst/selected [6] ), - .I1 (changed_down), - .I2 (pressed_down), - .I3 (pluse)); - // LUT = (I0&I1&I2)|(I0&I2&I3) ; - GTP_DFF_E /* \cnt[0] */ #( .GRS_EN("TRUE"), .INIT(1'b0)) @@ -94688,78 +94372,79 @@ endmodule module param_cell_unsigned_3 ( input [10:0] load_data, - input [13:0] \param_manager_inst/selected , input N72, input N140, - input N142, input changed_down, + input changed_up, input clk, input load_valid, input pluse, input pressed_down, + input pressed_up, input rd2_rst, input restore, input selected, - output [10:0] value, - output \param_manager_inst/param_osd_char_height/N140 + output [10:0] value ); wire N63; wire N76; + wire N139; + wire N142; wire N148; wire [10:0] N149; wire N153; wire N154; - wire _N4061; - wire _N4085; - wire _N15631; - wire _N15632; - wire _N15633; - wire _N15634; - wire _N15635; - wire _N15636; - wire _N15637; - wire _N15638; - wire _N15639; - wire _N95823_inv; - wire _N107060; - wire _N107067; + wire _N4097; + wire _N15675; + wire _N15676; + wire _N15677; + wire _N15678; + wire _N15679; + wire _N15680; + wire _N15681; + wire _N15682; + wire _N15683; + wire _N97127_inv; + wire _N107881; + wire _N107883; + wire _N107889; wire [10:0] nb0; - GTP_LUT4 /* N63_mux3 */ #( - .INIT(16'b1111100000000000)) - N63_mux3 ( - .Z (_N4061), + GTP_LUT3 /* N63_mux10_3 */ #( + .INIT(8'b11111110)) + N63_mux10_3 ( + .Z (_N107881), + .I0 (value[6]), + .I1 (value[7]), + .I2 (value[10])); + // LUT = (I0)|(I1)|(I2) ; + + GTP_LUT5 /* N63_mux10_7 */ #( + .INIT(32'b11111111111111111111100000000000)) + N63_mux10_7 ( + .Z (_N107883), .I0 (value[0]), .I1 (value[1]), .I2 (value[2]), - .I3 (value[3])); - // LUT = (I2&I3)|(I0&I1&I3) ; - - GTP_LUT4 /* N63_mux10_4 */ #( - .INIT(16'b1111111111111110)) - N63_mux10_4 ( - .Z (_N107060), - .I0 (value[4]), - .I1 (value[5]), - .I2 (value[8]), - .I3 (value[9])); - // LUT = (I0)|(I1)|(I2)|(I3) ; + .I3 (value[3]), + .I4 (_N107881)); + // LUT = (I4)|(I2&I3)|(I0&I1&I3) ; GTP_LUT5 /* N63_mux10_8 */ #( .INIT(32'b11111111111111111111111111111110)) N63_mux10_8 ( .Z (N63), - .I0 (value[6]), - .I1 (value[7]), - .I2 (value[10]), - .I3 (_N4061), - .I4 (_N107060)); + .I0 (value[4]), + .I1 (value[5]), + .I2 (value[8]), + .I3 (value[9]), + .I4 (_N107883)); // LUT = (I0)|(I1)|(I2)|(I3)|(I4) ; GTP_LUT5 /* N76_mux4_3 */ #( .INIT(32'b00000001111111111111111111111111)) N76_mux4_3 ( - .Z (_N4085), + .Z (_N4097), .I0 (value[1]), .I1 (value[2]), .I2 (value[3]), @@ -94770,7 +94455,7 @@ module param_cell_unsigned_3 GTP_LUT3 /* N76_mux9_2 */ #( .INIT(8'b00000001)) N76_mux9_2 ( - .Z (_N107067), + .Z (_N107889), .I0 (value[6]), .I1 (value[7]), .I2 (value[10])); @@ -94782,10 +94467,22 @@ module param_cell_unsigned_3 .Z (N76), .I0 (value[8]), .I1 (value[9]), - .I2 (_N4085), - .I3 (_N107067)); + .I2 (_N4097), + .I3 (_N107889)); // LUT = ~I0&~I1&I2&I3 ; + GTP_LUT5 /* N139 */ #( + .INIT(32'b00000000000000001010000010000000)) + N139_vname ( + .Z (N139), + .I0 (selected), + .I1 (changed_down), + .I2 (pressed_down), + .I3 (pluse), + .I4 (N63)); + // defparam N139_vname.orig_name = N139; + // LUT = (I0&I1&I2&~I4)|(I0&I2&I3&~I4) ; + GTP_LUT5 /* N148_4 */ #( .INIT(32'b11111111111111111111101011101010)) N148_4 ( @@ -94804,7 +94501,7 @@ module param_cell_unsigned_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_8_1 ( - .COUT (_N15631), + .COUT (_N15675), .Z (nb0[1]), .CIN (), .I0 (value[0]), @@ -94823,9 +94520,9 @@ module param_cell_unsigned_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_8_2 ( - .COUT (_N15632), + .COUT (_N15676), .Z (nb0[2]), - .CIN (_N15631), + .CIN (_N15675), .I0 (value[0]), .I1 (N154), .I2 (value[1]), @@ -94842,9 +94539,9 @@ module param_cell_unsigned_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_8_3 ( - .COUT (_N15633), + .COUT (_N15677), .Z (nb0[3]), - .CIN (_N15632), + .CIN (_N15676), .I0 (), .I1 (N154), .I2 (value[3]), @@ -94861,9 +94558,9 @@ module param_cell_unsigned_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_8_4 ( - .COUT (_N15634), + .COUT (_N15678), .Z (nb0[4]), - .CIN (_N15633), + .CIN (_N15677), .I0 (), .I1 (N154), .I2 (value[4]), @@ -94880,9 +94577,9 @@ module param_cell_unsigned_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_8_5 ( - .COUT (_N15635), + .COUT (_N15679), .Z (nb0[5]), - .CIN (_N15634), + .CIN (_N15678), .I0 (), .I1 (N154), .I2 (value[5]), @@ -94899,9 +94596,9 @@ module param_cell_unsigned_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_8_6 ( - .COUT (_N15636), + .COUT (_N15680), .Z (nb0[6]), - .CIN (_N15635), + .CIN (_N15679), .I0 (), .I1 (N154), .I2 (value[6]), @@ -94918,9 +94615,9 @@ module param_cell_unsigned_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_8_7 ( - .COUT (_N15637), + .COUT (_N15681), .Z (nb0[7]), - .CIN (_N15636), + .CIN (_N15680), .I0 (), .I1 (N154), .I2 (value[7]), @@ -94937,9 +94634,9 @@ module param_cell_unsigned_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_8_8 ( - .COUT (_N15638), + .COUT (_N15682), .Z (nb0[8]), - .CIN (_N15637), + .CIN (_N15681), .I0 (), .I1 (N154), .I2 (value[8]), @@ -94956,9 +94653,9 @@ module param_cell_unsigned_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_8_9 ( - .COUT (_N15639), + .COUT (_N15683), .Z (nb0[9]), - .CIN (_N15638), + .CIN (_N15682), .I0 (), .I1 (N154), .I2 (value[9]), @@ -94977,7 +94674,7 @@ module param_cell_unsigned_3 N149_8_10 ( .COUT (), .Z (nb0[10]), - .CIN (_N15639), + .CIN (_N15683), .I0 (), .I1 (N154), .I2 (value[10]), @@ -94994,7 +94691,7 @@ module param_cell_unsigned_3 .I0 (load_data[0]), .I1 (value[0]), .I2 (N153), - .I3 (_N95823_inv)); + .I3 (_N97127_inv)); // LUT = (~I1&I2&~I3)|(I0&~I2&I3) ; GTP_LUT4 /* \N149_27[1] */ #( @@ -95004,7 +94701,7 @@ module param_cell_unsigned_3 .I0 (load_data[1]), .I1 (N153), .I2 (nb0[1]), - .I3 (_N95823_inv)); + .I3 (_N97127_inv)); // LUT = (~I1&~I3)|(I0&I2)|(I0&I3)|(I1&I2)|(I1&I3) ; GTP_LUT4 /* \N149_27[2] */ #( @@ -95014,7 +94711,7 @@ module param_cell_unsigned_3 .I0 (load_data[2]), .I1 (N153), .I2 (nb0[2]), - .I3 (_N95823_inv)); + .I3 (_N97127_inv)); // LUT = (I1&I2&~I3)|(I0&~I1&I3) ; GTP_LUT4 /* \N149_27[3] */ #( @@ -95024,7 +94721,7 @@ module param_cell_unsigned_3 .I0 (load_data[3]), .I1 (N153), .I2 (nb0[3]), - .I3 (_N95823_inv)); + .I3 (_N97127_inv)); // LUT = (~I1&~I3)|(I2&~I3)|(I0&~I1) ; GTP_LUT4 /* \N149_27[4] */ #( @@ -95034,7 +94731,7 @@ module param_cell_unsigned_3 .I0 (load_data[4]), .I1 (N153), .I2 (nb0[4]), - .I3 (_N95823_inv)); + .I3 (_N97127_inv)); // LUT = (I0&I3)|(I1&I2)|(I1&I3) ; GTP_LUT4 /* \N149_27[5] */ #( @@ -95044,7 +94741,7 @@ module param_cell_unsigned_3 .I0 (load_data[5]), .I1 (N153), .I2 (nb0[5]), - .I3 (_N95823_inv)); + .I3 (_N97127_inv)); // LUT = (I0&I3)|(I1&I2)|(I1&I3) ; GTP_LUT4 /* \N149_27[6] */ #( @@ -95054,7 +94751,7 @@ module param_cell_unsigned_3 .I0 (load_data[6]), .I1 (N153), .I2 (nb0[6]), - .I3 (_N95823_inv)); + .I3 (_N97127_inv)); // LUT = (I1&I2&~I3)|(I0&~I1&I3) ; GTP_LUT4 /* \N149_27[7] */ #( @@ -95064,7 +94761,7 @@ module param_cell_unsigned_3 .I0 (load_data[7]), .I1 (N153), .I2 (nb0[7]), - .I3 (_N95823_inv)); + .I3 (_N97127_inv)); // LUT = (I1&I2&~I3)|(I0&~I1&I3) ; GTP_LUT4 /* \N149_27[8] */ #( @@ -95074,7 +94771,7 @@ module param_cell_unsigned_3 .I0 (load_data[8]), .I1 (N153), .I2 (nb0[8]), - .I3 (_N95823_inv)); + .I3 (_N97127_inv)); // LUT = (I1&I2&~I3)|(I0&~I1&I3) ; GTP_LUT4 /* \N149_27[9] */ #( @@ -95084,7 +94781,7 @@ module param_cell_unsigned_3 .I0 (load_data[9]), .I1 (N153), .I2 (nb0[9]), - .I3 (_N95823_inv)); + .I3 (_N97127_inv)); // LUT = (I1&I2&~I3)|(I0&~I1&I3) ; GTP_LUT4 /* \N149_27[10] */ #( @@ -95094,13 +94791,13 @@ module param_cell_unsigned_3 .I0 (load_data[10]), .I1 (N153), .I2 (nb0[10]), - .I3 (_N95823_inv)); + .I3 (_N97127_inv)); // LUT = (I1&I2&~I3)|(I0&~I1&I3) ; GTP_LUT5 /* N149_28 */ #( .INIT(32'b10101011101010101010101010101010)) N149_28 ( - .Z (_N95823_inv), + .Z (_N97127_inv), .I0 (load_valid), .I1 (N76), .I2 (N140), @@ -95108,39 +94805,35 @@ module param_cell_unsigned_3 .I4 (N153)); // LUT = (I0)|(~I1&~I2&I3&I4) ; - GTP_LUT5 /* N153 */ #( - .INIT(32'b00010101000000000001010100010101)) + GTP_LUT4 /* N153 */ #( + .INIT(16'b0000000000010101)) N153_vname ( .Z (N153), .I0 (load_valid), .I1 (restore), .I2 (selected), - .I3 (N63), - .I4 (N140)); + .I3 (N139)); // defparam N153_vname.orig_name = N153; - // LUT = (~I0&~I2&~I4)|(~I0&~I1&~I4)|(~I0&~I2&I3)|(~I0&~I1&I3) ; - // ../../sources/designs/others/param_cell_unsigned.v:101 + // LUT = (~I0&~I2&~I3)|(~I0&~I1&~I3) ; - GTP_LUT5 /* N154 */ #( - .INIT(32'b10100000100000000000000000000000)) - N154_vname ( + GTP_LUT5 /* N154_2 */ #( + .INIT(32'b00000000000101010000000000000000)) + N154_2 ( .Z (N154), - .I0 (selected), - .I1 (changed_down), - .I2 (pressed_down), - .I3 (pluse), - .I4 (N153)); - // defparam N154_vname.orig_name = N154; - // LUT = (I0&I1&I2&I4)|(I0&I2&I3&I4) ; - // ../../sources/designs/others/param_cell_unsigned.v:101 + .I0 (load_valid), + .I1 (restore), + .I2 (selected), + .I3 (N139), + .I4 (N140)); + // LUT = (~I0&~I2&~I3&I4)|(~I0&~I1&~I3&I4) ; GTP_LUT4 /* N156_1 */ #( .INIT(16'b1010000010000000)) N156_1 ( - .Z (\param_manager_inst/param_osd_char_height/N140 ), - .I0 (\param_manager_inst/selected [7] ), - .I1 (changed_down), - .I2 (pressed_down), + .Z (N142), + .I0 (selected), + .I1 (changed_up), + .I2 (pressed_up), .I3 (pluse)); // LUT = (I0&I1&I2)|(I0&I2&I3) ; @@ -95300,26 +94993,26 @@ module param_cell_unsigned_1 wire N153; wire N154; wire [11:0] N166; - wire _N4233; - wire _N15726; - wire _N15727; - wire _N15728; - wire _N15729; - wire _N15730; - wire _N15731; - wire _N15732; - wire _N15733; - wire _N15734; + wire _N4235; + wire _N15695; + wire _N15696; + wire _N15697; + wire _N15698; + wire _N15699; + wire _N15700; + wire _N15701; + wire _N15702; + wire _N15703; wire _N27413; wire _N27422; wire _N27427_inv; - wire _N29798; - wire _N107081; - wire _N107083; - wire _N107084; - wire _N107093; - wire _N107094; - wire _N107107; + wire _N29773; + wire _N107904; + wire _N107906; + wire _N107907; + wire _N107916; + wire _N107917; + wire _N107930; wire [11:0] cnt; wire [10:0] nb0; @@ -95411,7 +95104,7 @@ module param_cell_unsigned_1 .I4_TO_LUT("FALSE")) \N26_1.fsub_5 ( .COUT (\N26_1.co [5] ), - .Z (_N29798), + .Z (_N29773), .CIN (\N26_1.co [4] ), .I0 (), .I1 (cnt[5]), @@ -95548,8 +95241,8 @@ module param_cell_unsigned_1 N37_vname ( .Z (N37), .I0 (\key_debounce_inst2/pluse_ms ), - .I1 (_N107083), - .I2 (_N107084)); + .I1 (_N107906), + .I2 (_N107907)); // defparam N37_vname.orig_name = N37; // LUT = I0&I1&I2 ; // ../../sources/designs/others/param_cell_unsigned.v:94 @@ -95557,7 +95250,7 @@ module param_cell_unsigned_1 GTP_LUT4 /* N63_mux10_7 */ #( .INIT(16'b1111111111111110)) N63_mux10_7 ( - .Z (_N107093), + .Z (_N107916), .I0 (value[1]), .I1 (value[2]), .I2 (value[3]), @@ -95567,7 +95260,7 @@ module param_cell_unsigned_1 GTP_LUT4 /* N63_mux10_8 */ #( .INIT(16'b1111111111111110)) N63_mux10_8 ( - .Z (_N107094), + .Z (_N107917), .I0 (value[5]), .I1 (value[6]), .I2 (value[7]), @@ -95577,7 +95270,7 @@ module param_cell_unsigned_1 GTP_LUT5 /* N76_mux4_3 */ #( .INIT(32'b00000111111111111111111111111111)) N76_mux4_3 ( - .Z (_N4233), + .Z (_N4235), .I0 (value[2]), .I1 (value[3]), .I2 (value[4]), @@ -95593,13 +95286,13 @@ module param_cell_unsigned_1 .I1 (value[8]), .I2 (value[9]), .I3 (value[10]), - .I4 (_N4233)); + .I4 (_N4235)); // LUT = (~I3)|(~I2)|(~I1)|(~I0&I4) ; GTP_LUT4 /* N102_8 */ #( .INIT(16'b0000000000000001)) N102_8 ( - .Z (_N107081), + .Z (_N107904), .I0 (cnt[0]), .I1 (cnt[1]), .I2 (cnt[2]), @@ -95609,7 +95302,7 @@ module param_cell_unsigned_1 GTP_LUT4 /* N102_10 */ #( .INIT(16'b0000000000000001)) N102_10 ( - .Z (_N107083), + .Z (_N107906), .I0 (cnt[8]), .I1 (cnt[9]), .I2 (cnt[10]), @@ -95619,12 +95312,12 @@ module param_cell_unsigned_1 GTP_LUT5 /* N102_11 */ #( .INIT(32'b00000000000000010000000000000000)) N102_11 ( - .Z (_N107084), + .Z (_N107907), .I0 (cnt[4]), .I1 (cnt[5]), .I2 (cnt[6]), .I3 (cnt[7]), - .I4 (_N107081)); + .I4 (_N107904)); // LUT = ~I0&~I1&~I2&~I3&I4 ; GTP_LUT2 /* \N117_and[0][2] */ #( @@ -95658,8 +95351,8 @@ module param_cell_unsigned_1 .I0 (N111), .I1 (N119), .I2 (N166[2]), - .I3 (_N107083), - .I4 (_N107084)); + .I3 (_N107906), + .I4 (_N107907)); // LUT = (I0&I1&I2)|(I0&I1&I3&I4) ; GTP_LUT5 /* \N117_or[3] */ #( @@ -95669,8 +95362,8 @@ module param_cell_unsigned_1 .I0 (N111), .I1 (N119), .I2 (N166[3]), - .I3 (_N107083), - .I4 (_N107084)); + .I3 (_N107906), + .I4 (_N107907)); // LUT = (I0&I1&I2)|(I0&I1&I3&I4) ; GTP_LUT2 /* \N117_or[5] */ #( @@ -95678,7 +95371,7 @@ module param_cell_unsigned_1 \N117_or[5] ( .Z (N117[5]), .I0 (N160), - .I1 (_N29798)); + .I1 (_N29773)); // LUT = (I0)|(I1) ; GTP_LUT4 /* N122 */ #( @@ -95687,8 +95380,8 @@ module param_cell_unsigned_1 .Z (N122), .I0 (N111), .I1 (N119), - .I2 (_N107083), - .I3 (_N107084)); + .I2 (_N107906), + .I3 (_N107907)); // defparam N122_vname.orig_name = N122; // LUT = (I0&I1&~I3)|(I0&I1&~I2) ; @@ -95699,8 +95392,8 @@ module param_cell_unsigned_1 .I0 (value[9]), .I1 (value[10]), .I2 (N140), - .I3 (_N107093), - .I4 (_N107094)); + .I3 (_N107916), + .I4 (_N107917)); // defparam N139_vname.orig_name = N139; // LUT = ~I0&~I1&I2&~I3&~I4 ; @@ -95722,7 +95415,7 @@ module param_cell_unsigned_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_10_1 ( - .COUT (_N15726), + .COUT (_N15695), .Z (nb0[1]), .CIN (), .I0 (value[0]), @@ -95741,9 +95434,9 @@ module param_cell_unsigned_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_10_2 ( - .COUT (_N15727), + .COUT (_N15696), .Z (nb0[2]), - .CIN (_N15726), + .CIN (_N15695), .I0 (value[0]), .I1 (N154), .I2 (value[1]), @@ -95760,9 +95453,9 @@ module param_cell_unsigned_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_10_3 ( - .COUT (_N15728), + .COUT (_N15697), .Z (nb0[3]), - .CIN (_N15727), + .CIN (_N15696), .I0 (), .I1 (N154), .I2 (value[3]), @@ -95779,9 +95472,9 @@ module param_cell_unsigned_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_10_4 ( - .COUT (_N15729), + .COUT (_N15698), .Z (nb0[4]), - .CIN (_N15728), + .CIN (_N15697), .I0 (), .I1 (N154), .I2 (value[4]), @@ -95798,9 +95491,9 @@ module param_cell_unsigned_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_10_5 ( - .COUT (_N15730), + .COUT (_N15699), .Z (nb0[5]), - .CIN (_N15729), + .CIN (_N15698), .I0 (), .I1 (N154), .I2 (value[5]), @@ -95817,9 +95510,9 @@ module param_cell_unsigned_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_10_6 ( - .COUT (_N15731), + .COUT (_N15700), .Z (nb0[6]), - .CIN (_N15730), + .CIN (_N15699), .I0 (), .I1 (N154), .I2 (value[6]), @@ -95836,9 +95529,9 @@ module param_cell_unsigned_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_10_7 ( - .COUT (_N15732), + .COUT (_N15701), .Z (nb0[7]), - .CIN (_N15731), + .CIN (_N15700), .I0 (), .I1 (N154), .I2 (value[7]), @@ -95855,9 +95548,9 @@ module param_cell_unsigned_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_10_8 ( - .COUT (_N15733), + .COUT (_N15702), .Z (nb0[8]), - .CIN (_N15732), + .CIN (_N15701), .I0 (), .I1 (N154), .I2 (value[8]), @@ -95874,9 +95567,9 @@ module param_cell_unsigned_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_10_9 ( - .COUT (_N15734), + .COUT (_N15703), .Z (nb0[9]), - .CIN (_N15733), + .CIN (_N15702), .I0 (), .I1 (N154), .I2 (value[9]), @@ -95895,7 +95588,7 @@ module param_cell_unsigned_1 N149_10_10 ( .COUT (), .Z (nb0[10]), - .CIN (_N15734), + .CIN (_N15703), .I0 (), .I1 (N154), .I2 (value[10]), @@ -95913,7 +95606,7 @@ module param_cell_unsigned_1 .I1 (restore), .I2 (selected), .I3 (N139), - .I4 (_N107107)); + .I4 (_N107930)); // LUT = (~I0&~I1&I3)|(~I0&~I1&I4)|(~I0&~I2&~I3&I4) ; GTP_LUT2 /* N149_43_1 */ #( @@ -95921,7 +95614,7 @@ module param_cell_unsigned_1 N149_43_1 ( .Z (_N27427_inv), .I0 (N153), - .I1 (_N107107)); + .I1 (_N107930)); // LUT = (~I0)|(I1) ; GTP_LUT5 /* \N149_48[0] */ #( @@ -96051,7 +95744,7 @@ module param_cell_unsigned_1 .Z (_N27413), .I0 (load_valid), .I1 (N153), - .I2 (_N107107)); + .I2 (_N107930)); // LUT = (I0)|(I1&I2) ; GTP_LUT4 /* N153_1 */ #( @@ -96080,7 +95773,7 @@ module param_cell_unsigned_1 GTP_LUT3 /* N156_3 */ #( .INIT(8'b00010000)) N156_3 ( - .Z (_N107107), + .Z (_N107930), .I0 (N76), .I1 (N140), .I2 (N142)); @@ -96358,29 +96051,29 @@ module param_cell_unsigned_2 wire N148; wire [10:0] N149; wire N154; - wire _N4375; - wire _N15965; - wire _N15966; - wire _N15967; - wire _N15968; - wire _N15969; - wire _N15970; - wire _N15971; - wire _N15972; - wire _N15973; + wire _N4377; + wire _N15947; + wire _N15948; + wire _N15949; + wire _N15950; + wire _N15951; + wire _N15952; + wire _N15953; + wire _N15954; + wire _N15955; wire _N27489; wire _N27498; wire _N27503_inv; - wire _N107135; - wire _N107136; - wire _N107143; - wire _N107146; + wire _N107957; + wire _N107958; + wire _N107965; + wire _N107968; wire [10:0] nb0; GTP_LUT4 /* N63_mux10_6 */ #( .INIT(16'b1111111111111110)) N63_mux10_6 ( - .Z (_N107135), + .Z (_N107957), .I0 (value[1]), .I1 (value[2]), .I2 (value[3]), @@ -96390,7 +96083,7 @@ module param_cell_unsigned_2 GTP_LUT4 /* N63_mux10_7 */ #( .INIT(16'b1111111111111110)) N63_mux10_7 ( - .Z (_N107136), + .Z (_N107958), .I0 (value[5]), .I1 (value[6]), .I2 (value[7]), @@ -96400,7 +96093,7 @@ module param_cell_unsigned_2 GTP_LUT4 /* N76_mux7_4 */ #( .INIT(16'b0000000000000001)) N76_mux7_4 ( - .Z (_N107143), + .Z (_N107965), .I0 (value[6]), .I1 (value[7]), .I2 (value[8]), @@ -96410,12 +96103,12 @@ module param_cell_unsigned_2 GTP_LUT5 /* N76_mux7_5 */ #( .INIT(32'b00000001111111110000000000000000)) N76_mux7_5 ( - .Z (_N4375), + .Z (_N4377), .I0 (value[2]), .I1 (value[3]), .I2 (value[4]), .I3 (value[5]), - .I4 (_N107143)); + .I4 (_N107965)); // LUT = (~I3&I4)|(~I0&~I1&~I2&I4) ; GTP_LUT5 /* N139 */ #( @@ -96425,8 +96118,8 @@ module param_cell_unsigned_2 .I0 (value[9]), .I1 (value[10]), .I2 (N140), - .I3 (_N107135), - .I4 (_N107136)); + .I3 (_N107957), + .I4 (_N107958)); // defparam N139_vname.orig_name = N139; // LUT = ~I0&~I1&I2&~I3&~I4 ; @@ -96448,7 +96141,7 @@ module param_cell_unsigned_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_10_1 ( - .COUT (_N15965), + .COUT (_N15947), .Z (nb0[1]), .CIN (), .I0 (value[0]), @@ -96467,9 +96160,9 @@ module param_cell_unsigned_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_10_2 ( - .COUT (_N15966), + .COUT (_N15948), .Z (nb0[2]), - .CIN (_N15965), + .CIN (_N15947), .I0 (value[0]), .I1 (N154), .I2 (value[1]), @@ -96486,9 +96179,9 @@ module param_cell_unsigned_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_10_3 ( - .COUT (_N15967), + .COUT (_N15949), .Z (nb0[3]), - .CIN (_N15966), + .CIN (_N15948), .I0 (), .I1 (N154), .I2 (value[3]), @@ -96505,9 +96198,9 @@ module param_cell_unsigned_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_10_4 ( - .COUT (_N15968), + .COUT (_N15950), .Z (nb0[4]), - .CIN (_N15967), + .CIN (_N15949), .I0 (), .I1 (N154), .I2 (value[4]), @@ -96524,9 +96217,9 @@ module param_cell_unsigned_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_10_5 ( - .COUT (_N15969), + .COUT (_N15951), .Z (nb0[5]), - .CIN (_N15968), + .CIN (_N15950), .I0 (), .I1 (N154), .I2 (value[5]), @@ -96543,9 +96236,9 @@ module param_cell_unsigned_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_10_6 ( - .COUT (_N15970), + .COUT (_N15952), .Z (nb0[6]), - .CIN (_N15969), + .CIN (_N15951), .I0 (), .I1 (N154), .I2 (value[6]), @@ -96562,9 +96255,9 @@ module param_cell_unsigned_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_10_7 ( - .COUT (_N15971), + .COUT (_N15953), .Z (nb0[7]), - .CIN (_N15970), + .CIN (_N15952), .I0 (), .I1 (N154), .I2 (value[7]), @@ -96581,9 +96274,9 @@ module param_cell_unsigned_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_10_8 ( - .COUT (_N15972), + .COUT (_N15954), .Z (nb0[8]), - .CIN (_N15971), + .CIN (_N15953), .I0 (), .I1 (N154), .I2 (value[8]), @@ -96600,9 +96293,9 @@ module param_cell_unsigned_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_10_9 ( - .COUT (_N15973), + .COUT (_N15955), .Z (nb0[9]), - .CIN (_N15972), + .CIN (_N15954), .I0 (), .I1 (N154), .I2 (value[9]), @@ -96621,7 +96314,7 @@ module param_cell_unsigned_2 N149_10_10 ( .COUT (), .Z (nb0[10]), - .CIN (_N15973), + .CIN (_N15955), .I0 (), .I1 (N154), .I2 (value[10]), @@ -96639,7 +96332,7 @@ module param_cell_unsigned_2 .I1 (restore), .I2 (selected), .I3 (N139), - .I4 (_N107146)); + .I4 (_N107968)); // LUT = (~I0&~I1&I3)|(~I0&~I1&I4)|(~I0&~I2&~I3&I4) ; GTP_LUT5 /* N149_43_1 */ #( @@ -96650,7 +96343,7 @@ module param_cell_unsigned_2 .I1 (restore), .I2 (selected), .I3 (N139), - .I4 (_N107146)); + .I4 (_N107968)); // LUT = (I0)|(I3)|(I4)|(I1&I2) ; GTP_LUT5 /* \N149_48[0] */ #( @@ -96782,7 +96475,7 @@ module param_cell_unsigned_2 .I1 (restore), .I2 (selected), .I3 (N139), - .I4 (_N107146)); + .I4 (_N107968)); // LUT = (I0)|(~I2&~I3&I4)|(~I1&~I3&I4) ; GTP_LUT5 /* N154 */ #( @@ -96798,12 +96491,12 @@ module param_cell_unsigned_2 // LUT = (~I0&~I2&~I3&I4)|(~I0&~I1&~I3&I4) ; // ../../sources/designs/others/param_cell_unsigned.v:101 - GTP_LUT5 /* N156_6 */ #( + GTP_LUT5 /* N156_3 */ #( .INIT(32'b00000000000000000010000000000000)) - N156_6 ( - .Z (_N107146), + N156_3 ( + .Z (_N107968), .I0 (value[10]), - .I1 (_N4375), + .I1 (_N4377), .I2 (selected), .I3 (N72), .I4 (N140)); @@ -96937,6 +96630,7 @@ endmodule module param_cell_unsigned_loop_1 ( input [7:0] load_data, + input [13:0] \param_manager_inst/selected , input N111, input N116, input N119, @@ -96946,17 +96640,19 @@ module param_cell_unsigned_loop_1 input clk, input \key_debounce_inst2/pluse_ms , input load_valid, + input \param_manager_inst/param_modify_H/pluse , input pressed_down, input pressed_up, input rd2_rst, input restore, input selected, - output [7:0] value + output [7:0] value, + output \param_manager_inst/param_modify_H/N140 ); wire [11:0] \N26_1.co ; wire N37; - wire N58; wire N63; + wire N72; wire N102; wire [11:0] N117; wire N122; @@ -96965,30 +96661,31 @@ module param_cell_unsigned_loop_1 wire N156; wire [11:0] N166; wire _N0; - wire _N2; - wire _N3; - wire _N4; - wire _N6; wire _N8; - wire _N14149; - wire _N14150; - wire _N14151; - wire _N14152; - wire _N14153; - wire _N14154; - wire _N29826; - wire _N29832; - wire _N29835; - wire _N29838; - wire _N40710; - wire _N41237; - wire _N41419; - wire _N81754; - wire _N104516; - wire _N104518; - wire _N104527; - wire _N104535; - wire _N104538; + wire _N14097; + wire _N14098; + wire _N14099; + wire _N14100; + wire _N14101; + wire _N14102; + wire _N29801; + wire _N29807; + wire _N29810; + wire _N29813; + wire _N38658; + wire _N38793; + wire _N38920; + wire _N38957; + wire _N39086; + wire _N39152; + wire _N39317; + wire _N82541; + wire _N105353; + wire _N105355; + wire _N105362; + wire _N105364; + wire _N105372; + wire _N105373; wire [11:0] cnt; wire [7:0] nb0; wire pluse; @@ -97021,7 +96718,7 @@ module param_cell_unsigned_loop_1 .I4_TO_LUT("FALSE")) \N26_1.fsub_2 ( .COUT (\N26_1.co [2] ), - .Z (_N29826), + .Z (_N29801), .CIN (\N26_1.co [1] ), .I0 (cnt[0]), .I1 (cnt[1]), @@ -97061,7 +96758,7 @@ module param_cell_unsigned_loop_1 .I4_TO_LUT("FALSE")) \N26_1.fsub_4 ( .COUT (\N26_1.co [4] ), - .Z (_N29832), + .Z (_N29807), .CIN (\N26_1.co [3] ), .I0 (), .I1 (cnt[4]), @@ -97081,7 +96778,7 @@ module param_cell_unsigned_loop_1 .I4_TO_LUT("FALSE")) \N26_1.fsub_5 ( .COUT (\N26_1.co [5] ), - .Z (_N29835), + .Z (_N29810), .CIN (\N26_1.co [4] ), .I0 (), .I1 (cnt[5]), @@ -97101,7 +96798,7 @@ module param_cell_unsigned_loop_1 .I4_TO_LUT("FALSE")) \N26_1.fsub_6 ( .COUT (\N26_1.co [6] ), - .Z (_N29838), + .Z (_N29813), .CIN (\N26_1.co [5] ), .I0 (), .I1 (cnt[6]), @@ -97223,20 +96920,10 @@ module param_cell_unsigned_loop_1 // LUT = I0&I1 ; // ../../sources/designs/others/param_cell_unsigned_loop.v:94 - GTP_LUT2 /* N58 */ #( - .INIT(4'b1110)) - N58_vname ( - .Z (N58), - .I0 (changed_down), - .I1 (pluse)); - // defparam N58_vname.orig_name = N58; - // LUT = (I0)|(I1) ; - // ../../sources/designs/others/param_cell_unsigned_loop.v:118 - GTP_LUT4 /* N63_mux7_7 */ #( .INIT(16'b1111111111111110)) N63_mux7_7 ( - .Z (_N104527), + .Z (_N105362), .I0 (value[4]), .I1 (value[5]), .I2 (value[6]), @@ -97251,13 +96938,24 @@ module param_cell_unsigned_loop_1 .I1 (value[1]), .I2 (value[2]), .I3 (value[3]), - .I4 (_N104527)); + .I4 (_N105362)); // LUT = (I0)|(I1)|(I2)|(I3)|(I4) ; + GTP_LUT3 /* N72 */ #( + .INIT(8'b11001000)) + N72_vname ( + .Z (N72), + .I0 (changed_up), + .I1 (pressed_up), + .I2 (pluse)); + // defparam N72_vname.orig_name = N72; + // LUT = (I0&I1)|(I1&I2) ; + // ../../sources/designs/others/param_cell_unsigned_loop.v:125 + GTP_LUT4 /* N102_9 */ #( .INIT(16'b0000000000000001)) N102_9 ( - .Z (_N104516), + .Z (_N105353), .I0 (cnt[4]), .I1 (cnt[5]), .I2 (cnt[6]), @@ -97267,12 +96965,12 @@ module param_cell_unsigned_loop_1 GTP_LUT5 /* N102_11 */ #( .INIT(32'b00000000000000010000000000000000)) N102_11 ( - .Z (_N104518), + .Z (_N105355), .I0 (cnt[0]), .I1 (cnt[1]), .I2 (cnt[2]), .I3 (cnt[3]), - .I4 (_N104516)); + .I4 (_N105353)); // LUT = ~I0&~I1&~I2&~I3&I4 ; GTP_LUT5 /* N102_12 */ #( @@ -97283,7 +96981,7 @@ module param_cell_unsigned_loop_1 .I1 (cnt[9]), .I2 (cnt[10]), .I3 (cnt[11]), - .I4 (_N104518)); + .I4 (_N105355)); // LUT = ~I0&~I1&~I2&~I3&I4 ; GTP_LUT2 /* \N117_and[0][2] */ #( @@ -97307,7 +97005,7 @@ module param_cell_unsigned_loop_1 \N117_or[2] ( .Z (N117[2]), .I0 (N160), - .I1 (_N29826)); + .I1 (_N29801)); // LUT = (I0)|(I1) ; GTP_LUT4 /* \N117_or[4] */ #( @@ -97317,7 +97015,7 @@ module param_cell_unsigned_loop_1 .I0 (N111), .I1 (N119), .I2 (N102), - .I3 (_N29832)); + .I3 (_N29807)); // LUT = (I3)|(I0&I1&I2) ; GTP_LUT4 /* \N117_or[5] */ #( @@ -97327,7 +97025,7 @@ module param_cell_unsigned_loop_1 .I0 (N111), .I1 (N119), .I2 (N102), - .I3 (_N29835)); + .I3 (_N29810)); // LUT = (I3)|(I0&I1&I2) ; GTP_LUT2 /* \N117_or[6] */ #( @@ -97335,7 +97033,7 @@ module param_cell_unsigned_loop_1 \N117_or[6] ( .Z (N117[6]), .I0 (N160), - .I1 (_N29838)); + .I1 (_N29813)); // LUT = (I0)|(I1) ; GTP_LUT5 /* N122 */ #( @@ -97351,47 +97049,55 @@ module param_cell_unsigned_loop_1 // LUT = (I0&I1&I2&~I4)|(I0&I1&I3&~I4) ; GTP_LUT5 /* N152_1 */ #( - .INIT(32'b11111111101010101010111010101010)) + .INIT(32'b11101110101011101110111010101010)) N152_1 ( .Z (N152), .I0 (rd2_rst), - .I1 (restore), - .I2 (load_valid), - .I3 (selected), - .I4 (_N81754)); - // LUT = (I0)|(I3&I4)|(I1&~I2&I3) ; + .I1 (selected), + .I2 (N149), + .I3 (_N82541), + .I4 (_N105373)); + // LUT = (I0)|(I1&I3)|(I1&~I2&I4) ; - GTP_LUT4 /* N152_5_6 */ #( - .INIT(16'b1000000000000000)) - N152_5_6 ( - .Z (_N104535), + GTP_LUT2 /* N152_4 */ #( + .INIT(4'b0010)) + N152_4 ( + .Z (_N82541), + .I0 (restore), + .I1 (load_valid)); + // LUT = I0&~I1 ; + + GTP_LUT5 /* N152_5_8 */ #( + .INIT(32'b10000000000000000000000000000000)) + N152_5_8 ( + .Z (_N105372), .I0 (value[0]), .I1 (value[1]), .I2 (value[2]), - .I3 (value[3])); - // LUT = I0&I1&I2&I3 ; + .I3 (value[3]), + .I4 (N72)); + // LUT = I0&I1&I2&I3&I4 ; GTP_LUT5 /* N152_5_9 */ #( - .INIT(32'b00000000000000001000000000000000)) + .INIT(32'b10000000000000000000000000000000)) N152_5_9 ( - .Z (_N104538), + .Z (_N105373), .I0 (value[4]), .I1 (value[5]), .I2 (value[6]), .I3 (value[7]), - .I4 (N149)); - // LUT = I0&I1&I2&I3&~I4 ; + .I4 (_N105372)); + // LUT = I0&I1&I2&I3&I4 ; - GTP_LUT5 /* N152_5_10 */ #( - .INIT(32'b11001000000000000000000000000000)) - N152_5_10 ( - .Z (_N81754), - .I0 (changed_up), - .I1 (pressed_up), - .I2 (pluse), - .I3 (_N104535), - .I4 (_N104538)); - // LUT = (I0&I1&I3&I4)|(I1&I2&I3&I4) ; + GTP_LUT4 /* N153_1 */ #( + .INIT(16'b1010000010000000)) + N153_1 ( + .Z (\param_manager_inst/param_modify_H/N140 ), + .I0 (\param_manager_inst/selected [11] ), + .I1 (changed_down), + .I2 (pressed_down), + .I3 (\param_manager_inst/param_modify_H/pluse )); + // LUT = (I0&I1&I2)|(I0&I2&I3) ; GTP_LUT5CARRY /* N155_8_1 */ #( .INIT(32'b10010110100101100000000000000000), @@ -97400,7 +97106,7 @@ module param_cell_unsigned_loop_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N155_8_1 ( - .COUT (_N14149), + .COUT (_N14097), .Z (nb0[1]), .CIN (), .I0 (value[0]), @@ -97419,9 +97125,9 @@ module param_cell_unsigned_loop_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N155_8_2 ( - .COUT (_N14150), + .COUT (_N14098), .Z (nb0[2]), - .CIN (_N14149), + .CIN (_N14097), .I0 (value[0]), .I1 (N156), .I2 (value[1]), @@ -97438,9 +97144,9 @@ module param_cell_unsigned_loop_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N155_8_3 ( - .COUT (_N14151), + .COUT (_N14099), .Z (nb0[3]), - .CIN (_N14150), + .CIN (_N14098), .I0 (), .I1 (N156), .I2 (value[3]), @@ -97457,9 +97163,9 @@ module param_cell_unsigned_loop_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N155_8_4 ( - .COUT (_N14152), + .COUT (_N14100), .Z (nb0[4]), - .CIN (_N14151), + .CIN (_N14099), .I0 (), .I1 (N156), .I2 (value[4]), @@ -97476,9 +97182,9 @@ module param_cell_unsigned_loop_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N155_8_5 ( - .COUT (_N14153), + .COUT (_N14101), .Z (nb0[5]), - .CIN (_N14152), + .CIN (_N14100), .I0 (), .I1 (N156), .I2 (value[5]), @@ -97495,9 +97201,9 @@ module param_cell_unsigned_loop_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N155_8_6 ( - .COUT (_N14154), + .COUT (_N14102), .Z (nb0[6]), - .CIN (_N14153), + .CIN (_N14101), .I0 (), .I1 (N156), .I2 (value[6]), @@ -97516,7 +97222,7 @@ module param_cell_unsigned_loop_1 N155_8_7 ( .COUT (), .Z (nb0[7]), - .CIN (_N14154), + .CIN (_N14102), .I0 (), .I1 (N156), .I2 (value[7]), @@ -97677,7 +97383,7 @@ module param_cell_unsigned_loop_1 .Q (value[0]), .CE (_N0), .CLK (clk), - .D (_N40710), + .D (_N38658), .R (N152)); // ../../sources/designs/others/param_cell_unsigned_loop.v:101 @@ -97688,7 +97394,7 @@ module param_cell_unsigned_loop_1 .Q (value[1]), .CE (_N0), .CLK (clk), - .D (_N2), + .D (_N38793), .R (N152)); // ../../sources/designs/others/param_cell_unsigned_loop.v:101 @@ -97699,7 +97405,7 @@ module param_cell_unsigned_loop_1 .Q (value[2]), .CE (_N0), .CLK (clk), - .D (_N3), + .D (_N38920), .R (N152)); // ../../sources/designs/others/param_cell_unsigned_loop.v:101 @@ -97710,7 +97416,7 @@ module param_cell_unsigned_loop_1 .Q (value[3]), .CE (_N0), .CLK (clk), - .D (_N4), + .D (_N38957), .R (N152)); // ../../sources/designs/others/param_cell_unsigned_loop.v:101 @@ -97721,7 +97427,7 @@ module param_cell_unsigned_loop_1 .Q (value[4]), .CE (_N0), .CLK (clk), - .D (_N41237), + .D (_N39086), .R (N152)); // ../../sources/designs/others/param_cell_unsigned_loop.v:101 @@ -97732,7 +97438,7 @@ module param_cell_unsigned_loop_1 .Q (value[5]), .CE (_N0), .CLK (clk), - .D (_N6), + .D (_N39152), .R (N152)); // ../../sources/designs/others/param_cell_unsigned_loop.v:101 @@ -97743,86 +97449,93 @@ module param_cell_unsigned_loop_1 .Q (value[6]), .CE (_N0), .CLK (clk), - .D (_N41419), + .D (_N39317), .R (N152)); // ../../sources/designs/others/param_cell_unsigned_loop.v:101 - GTP_LUT5M /* \value[7:0]_0 */ #( - .INIT(32'b10101010101010101010111010101010)) - \value[7:0]_0 ( - .Z (_N41237), - .I0 (load_data[4]), - .I1 (N58), - .I2 (N63), - .I3 (pressed_down), - .I4 (load_valid), - .ID (nb0[4])); - // LUT = (I1&~I2&I3&~I4)|(ID&~I4)|(I0&I4) ; - - GTP_LUT5M /* \value[7:0]_1 */ #( - .INIT(32'b10101010101010101010111010101010)) - \value[7:0]_1 ( - .Z (_N41419), - .I0 (load_data[6]), - .I1 (N58), - .I2 (N63), - .I3 (pressed_down), - .I4 (load_valid), - .ID (nb0[6])); - // LUT = (I1&~I2&I3&~I4)|(ID&~I4)|(I0&I4) ; - - GTP_LUT3 /* \value[7:0]_7 */ #( + GTP_LUT3 /* \value[7:0]_3 */ #( .INIT(8'b10100011)) - \value[7:0]_7 ( - .Z (_N40710), + \value[7:0]_3 ( + .Z (_N38658), .I0 (load_data[0]), .I1 (value[0]), .I2 (load_valid)); // LUT = (~I1&~I2)|(I0&I2) ; - GTP_LUT5 /* \value[7:0]_d[1] */ #( - .INIT(32'b10111111101110111000111110001000)) - \value[7:0]_d[1] ( - .Z (_N2), + GTP_LUT3 /* \value[7:0]_5 */ #( + .INIT(8'b00110111)) + \value[7:0]_5 ( + .Z (_N105364), + .I0 (changed_down), + .I1 (pressed_down), + .I2 (pluse)); + // LUT = (~I1)|(~I0&~I2) ; + + GTP_LUT5 /* \value[7:0]_6 */ #( + .INIT(32'b10111011100010001011101110001011)) + \value[7:0]_6 ( + .Z (_N38793), .I0 (load_data[1]), .I1 (load_valid), .I2 (N63), - .I3 (N156), - .I4 (nb0[1])); - // LUT = (~I2&I3)|(~I1&I4)|(I0&I1) ; + .I3 (nb0[1]), + .I4 (_N105364)); + // LUT = (~I1&I3)|(I0&I1)|(~I1&~I2&~I4) ; - GTP_LUT5 /* \value[7:0]_d[2] */ #( - .INIT(32'b10111111101110111000111110001000)) - \value[7:0]_d[2] ( - .Z (_N3), + GTP_LUT5 /* \value[7:0]_7 */ #( + .INIT(32'b10111011100010001011101110001011)) + \value[7:0]_7 ( + .Z (_N38920), .I0 (load_data[2]), .I1 (load_valid), .I2 (N63), - .I3 (N156), - .I4 (nb0[2])); - // LUT = (~I2&I3)|(~I1&I4)|(I0&I1) ; - - GTP_LUT5 /* \value[7:0]_d[3] */ #( - .INIT(32'b10111111101110111000111110001000)) - \value[7:0]_d[3] ( - .Z (_N4), + .I3 (nb0[2]), + .I4 (_N105364)); + // LUT = (~I1&I3)|(I0&I1)|(~I1&~I2&~I4) ; + + GTP_LUT5 /* \value[7:0]_9 */ #( + .INIT(32'b10111011100010001011101110001011)) + \value[7:0]_9 ( + .Z (_N38957), .I0 (load_data[3]), .I1 (load_valid), .I2 (N63), - .I3 (N156), - .I4 (nb0[3])); - // LUT = (~I2&I3)|(~I1&I4)|(I0&I1) ; - - GTP_LUT5 /* \value[7:0]_d[5] */ #( - .INIT(32'b10111111101110111000111110001000)) - \value[7:0]_d[5] ( - .Z (_N6), + .I3 (nb0[3]), + .I4 (_N105364)); + // LUT = (~I1&I3)|(I0&I1)|(~I1&~I2&~I4) ; + + GTP_LUT5 /* \value[7:0]_267 */ #( + .INIT(32'b10111011100010001011101110001011)) + \value[7:0]_267 ( + .Z (_N39086), + .I0 (load_data[4]), + .I1 (load_valid), + .I2 (N63), + .I3 (nb0[4]), + .I4 (_N105364)); + // LUT = (~I1&I3)|(I0&I1)|(~I1&~I2&~I4) ; + + GTP_LUT5 /* \value[7:0]_323 */ #( + .INIT(32'b10111011100010001011101110001011)) + \value[7:0]_323 ( + .Z (_N39152), .I0 (load_data[5]), .I1 (load_valid), .I2 (N63), - .I3 (N156), - .I4 (nb0[5])); - // LUT = (~I2&I3)|(~I1&I4)|(I0&I1) ; + .I3 (nb0[5]), + .I4 (_N105364)); + // LUT = (~I1&I3)|(I0&I1)|(~I1&~I2&~I4) ; + + GTP_LUT5 /* \value[7:0]_446 */ #( + .INIT(32'b10111011100010001011101110001011)) + \value[7:0]_446 ( + .Z (_N39317), + .I0 (load_data[6]), + .I1 (load_valid), + .I2 (N63), + .I3 (nb0[6]), + .I4 (_N105364)); + // LUT = (~I1&I3)|(I0&I1)|(~I1&~I2&~I4) ; GTP_LUT5 /* \value[7:0]_d[7] */ #( .INIT(32'b10111111101110111000111110001000)) @@ -97878,46 +97591,49 @@ module param_cell_unsigned input [13:0] \param_manager_inst/selected , input N72, input N140, - input N142, + input changed_down, input changed_up, input clk, input load_valid, input \param_manager_inst/param_osd_char_height/pluse , + input pluse, + input pressed_down, input pressed_up, input rd2_rst, input restore, input selected, output [9:0] value, output \param_manager_inst/param_osd_char_height/N142 , - output \param_manager_inst/param_osd_char_width/N142 + output \param_manager_inst/param_zoom/N140 ); wire N63; + wire N142; wire N148; wire [9:0] N149; wire N154; wire N156; - wire _N14157; - wire _N14158; - wire _N14159; - wire _N14160; - wire _N14161; - wire _N14162; - wire _N14163; - wire _N14164; + wire _N14135; + wire _N14136; + wire _N14137; + wire _N14138; + wire _N14139; + wire _N14140; + wire _N14141; + wire _N14142; wire _N27565; wire _N27574; wire _N27579_inv; - wire _N95999; - wire _N104557; - wire _N104566; - wire _N104568; - wire _N104569; + wire _N96779; + wire _N105392; + wire _N105401; + wire _N105403; + wire _N105404; wire [9:0] nb0; GTP_LUT5 /* N63_mux9_8 */ #( .INIT(32'b11111111111111111111111111111110)) N63_mux9_8 ( - .Z (_N104557), + .Z (_N105392), .I0 (value[1]), .I1 (value[2]), .I2 (value[7]), @@ -97933,23 +97649,35 @@ module param_cell_unsigned .I1 (value[4]), .I2 (value[5]), .I3 (value[6]), - .I4 (_N104557)); + .I4 (_N105392)); // LUT = (I0)|(I1)|(I2)|(I3)|(I4) ; GTP_LUT4 /* N139_1 */ #( .INIT(16'b1010000010000000)) N139_1 ( - .Z (\param_manager_inst/param_osd_char_width/N142 ), - .I0 (\param_manager_inst/selected [6] ), + .Z (\param_manager_inst/param_osd_char_height/N142 ), + .I0 (\param_manager_inst/selected [7] ), .I1 (changed_up), .I2 (pressed_up), .I3 (\param_manager_inst/param_osd_char_height/pluse )); // LUT = (I0&I1&I2)|(I0&I2&I3) ; + GTP_LUT4 /* N142 */ #( + .INIT(16'b1010000010000000)) + N142_vname ( + .Z (N142), + .I0 (selected), + .I1 (changed_up), + .I2 (pressed_up), + .I3 (pluse)); + // defparam N142_vname.orig_name = N142; + // LUT = (I0&I1&I2)|(I0&I2&I3) ; + // ../../sources/designs/others/param_cell_unsigned.v:130 + GTP_LUT3 /* N148_1 */ #( .INIT(8'b11101100)) N148_1 ( - .Z (_N95999), + .Z (_N96779), .I0 (restore), .I1 (load_valid), .I2 (selected)); @@ -97973,7 +97701,7 @@ module param_cell_unsigned .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_10_1 ( - .COUT (_N14157), + .COUT (_N14135), .Z (nb0[1]), .CIN (), .I0 (value[0]), @@ -97992,9 +97720,9 @@ module param_cell_unsigned .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_10_2 ( - .COUT (_N14158), + .COUT (_N14136), .Z (nb0[2]), - .CIN (_N14157), + .CIN (_N14135), .I0 (value[0]), .I1 (N154), .I2 (value[1]), @@ -98011,9 +97739,9 @@ module param_cell_unsigned .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_10_3 ( - .COUT (_N14159), + .COUT (_N14137), .Z (nb0[3]), - .CIN (_N14158), + .CIN (_N14136), .I0 (), .I1 (N154), .I2 (value[3]), @@ -98030,9 +97758,9 @@ module param_cell_unsigned .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_10_4 ( - .COUT (_N14160), + .COUT (_N14138), .Z (nb0[4]), - .CIN (_N14159), + .CIN (_N14137), .I0 (), .I1 (N154), .I2 (value[4]), @@ -98049,9 +97777,9 @@ module param_cell_unsigned .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_10_5 ( - .COUT (_N14161), + .COUT (_N14139), .Z (nb0[5]), - .CIN (_N14160), + .CIN (_N14138), .I0 (), .I1 (N154), .I2 (value[5]), @@ -98068,9 +97796,9 @@ module param_cell_unsigned .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_10_6 ( - .COUT (_N14162), + .COUT (_N14140), .Z (nb0[6]), - .CIN (_N14161), + .CIN (_N14139), .I0 (), .I1 (N154), .I2 (value[6]), @@ -98087,9 +97815,9 @@ module param_cell_unsigned .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_10_7 ( - .COUT (_N14163), + .COUT (_N14141), .Z (nb0[7]), - .CIN (_N14162), + .CIN (_N14140), .I0 (), .I1 (N154), .I2 (value[7]), @@ -98106,9 +97834,9 @@ module param_cell_unsigned .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_10_8 ( - .COUT (_N14164), + .COUT (_N14142), .Z (nb0[8]), - .CIN (_N14163), + .CIN (_N14141), .I0 (), .I1 (N154), .I2 (value[8]), @@ -98127,7 +97855,7 @@ module param_cell_unsigned N149_10_9 ( .COUT (), .Z (nb0[9]), - .CIN (_N14164), + .CIN (_N14142), .I0 (), .I1 (N154), .I2 (value[9]), @@ -98155,7 +97883,7 @@ module param_cell_unsigned .I0 (N63), .I1 (N140), .I2 (N156), - .I3 (_N95999)); + .I3 (_N96779)); // LUT = (I2)|(I3)|(~I0&I1) ; GTP_LUT5 /* \N149_48[0] */ #( @@ -98292,36 +98020,36 @@ module param_cell_unsigned GTP_LUT4 /* N156_1 */ #( .INIT(16'b1010000010000000)) N156_1 ( - .Z (\param_manager_inst/param_osd_char_height/N142 ), - .I0 (\param_manager_inst/selected [7] ), - .I1 (changed_up), - .I2 (pressed_up), - .I3 (\param_manager_inst/param_osd_char_height/pluse )); + .Z (\param_manager_inst/param_zoom/N140 ), + .I0 (\param_manager_inst/selected [2] ), + .I1 (changed_down), + .I2 (pressed_down), + .I3 (pluse)); // LUT = (I0&I1&I2)|(I0&I2&I3) ; - GTP_LUT4 /* N156_19 */ #( + GTP_LUT4 /* N156_20 */ #( .INIT(16'b1000000000000000)) - N156_19 ( - .Z (_N104566), + N156_20 ( + .Z (_N105401), .I0 (value[0]), .I1 (value[1]), .I2 (value[2]), .I3 (value[3])); // LUT = I0&I1&I2&I3 ; - GTP_LUT3 /* N156_21 */ #( + GTP_LUT3 /* N156_22 */ #( .INIT(8'b10000000)) - N156_21 ( - .Z (_N104568), + N156_22 ( + .Z (_N105403), .I0 (value[8]), .I1 (value[9]), - .I2 (_N104566)); + .I2 (_N105401)); // LUT = I0&I1&I2 ; - GTP_LUT5 /* N156_22 */ #( + GTP_LUT5 /* N156_23 */ #( .INIT(32'b10000000000000000000000000000000)) - N156_22 ( - .Z (_N104569), + N156_23 ( + .Z (_N105404), .I0 (value[4]), .I1 (value[5]), .I2 (value[6]), @@ -98329,14 +98057,14 @@ module param_cell_unsigned .I4 (N142)); // LUT = I0&I1&I2&I3&I4 ; - GTP_LUT4 /* N156_25 */ #( + GTP_LUT4 /* N156_26 */ #( .INIT(16'b0001000000000000)) - N156_25 ( + N156_26 ( .Z (N156), .I0 (N140), - .I1 (_N95999), - .I2 (_N104568), - .I3 (_N104569)); + .I1 (_N96779), + .I2 (_N105403), + .I3 (_N105404)); // LUT = ~I0&~I1&I2&I3 ; GTP_DFF_RE /* \value[0] */ #( @@ -98458,12 +98186,14 @@ module param_cell_unsigned_unq4 input [9:0] load_data, input [13:0] \param_manager_inst/selected , input N72, - input N142, + input N140, input changed_down, + input changed_up, input clk, input load_valid, input pluse, input pressed_down, + input pressed_up, input rd2_rst, input restore, input selected, @@ -98471,33 +98201,33 @@ module param_cell_unsigned_unq4 output \param_manager_inst/param_rotate_A/N140 ); wire N63; - wire N140; + wire N142; wire N148; wire [9:0] N149; wire N154; wire N156; - wire _N14185; - wire _N14186; - wire _N14187; - wire _N14188; - wire _N14189; - wire _N14190; - wire _N14191; - wire _N14192; + wire _N14160; + wire _N14161; + wire _N14162; + wire _N14163; + wire _N14164; + wire _N14165; + wire _N14166; + wire _N14167; wire _N27637; wire _N27646; wire _N27651_inv; - wire _N96009; - wire _N104680; - wire _N104689; - wire _N104691; - wire _N104692; + wire _N96788; + wire _N105515; + wire _N105524; + wire _N105526; + wire _N105527; wire [9:0] nb0; GTP_LUT5 /* N63_mux9_8 */ #( .INIT(32'b11111111111111111111111111111110)) N63_mux9_8 ( - .Z (_N104680), + .Z (_N105515), .I0 (value[1]), .I1 (value[2]), .I2 (value[7]), @@ -98513,23 +98243,25 @@ module param_cell_unsigned_unq4 .I1 (value[4]), .I2 (value[5]), .I3 (value[6]), - .I4 (_N104680)); + .I4 (_N105515)); // LUT = (I0)|(I1)|(I2)|(I3)|(I4) ; - GTP_LUT4 /* N139_1 */ #( + GTP_LUT4 /* N142 */ #( .INIT(16'b1010000010000000)) - N139_1 ( - .Z (N140), + N142_vname ( + .Z (N142), .I0 (selected), - .I1 (changed_down), - .I2 (pressed_down), + .I1 (changed_up), + .I2 (pressed_up), .I3 (pluse)); + // defparam N142_vname.orig_name = N142; // LUT = (I0&I1&I2)|(I0&I2&I3) ; + // ../../sources/designs/others/param_cell_unsigned.v:130 GTP_LUT3 /* N148_1 */ #( .INIT(8'b11101100)) N148_1 ( - .Z (_N96009), + .Z (_N96788), .I0 (restore), .I1 (load_valid), .I2 (selected)); @@ -98553,7 +98285,7 @@ module param_cell_unsigned_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_10_1 ( - .COUT (_N14185), + .COUT (_N14160), .Z (nb0[1]), .CIN (), .I0 (value[0]), @@ -98572,9 +98304,9 @@ module param_cell_unsigned_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_10_2 ( - .COUT (_N14186), + .COUT (_N14161), .Z (nb0[2]), - .CIN (_N14185), + .CIN (_N14160), .I0 (value[0]), .I1 (N154), .I2 (value[1]), @@ -98591,9 +98323,9 @@ module param_cell_unsigned_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_10_3 ( - .COUT (_N14187), + .COUT (_N14162), .Z (nb0[3]), - .CIN (_N14186), + .CIN (_N14161), .I0 (), .I1 (N154), .I2 (value[3]), @@ -98610,9 +98342,9 @@ module param_cell_unsigned_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_10_4 ( - .COUT (_N14188), + .COUT (_N14163), .Z (nb0[4]), - .CIN (_N14187), + .CIN (_N14162), .I0 (), .I1 (N154), .I2 (value[4]), @@ -98629,9 +98361,9 @@ module param_cell_unsigned_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_10_5 ( - .COUT (_N14189), + .COUT (_N14164), .Z (nb0[5]), - .CIN (_N14188), + .CIN (_N14163), .I0 (), .I1 (N154), .I2 (value[5]), @@ -98648,9 +98380,9 @@ module param_cell_unsigned_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_10_6 ( - .COUT (_N14190), + .COUT (_N14165), .Z (nb0[6]), - .CIN (_N14189), + .CIN (_N14164), .I0 (), .I1 (N154), .I2 (value[6]), @@ -98667,9 +98399,9 @@ module param_cell_unsigned_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_10_7 ( - .COUT (_N14191), + .COUT (_N14166), .Z (nb0[7]), - .CIN (_N14190), + .CIN (_N14165), .I0 (), .I1 (N154), .I2 (value[7]), @@ -98686,9 +98418,9 @@ module param_cell_unsigned_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N149_10_8 ( - .COUT (_N14192), + .COUT (_N14167), .Z (nb0[8]), - .CIN (_N14191), + .CIN (_N14166), .I0 (), .I1 (N154), .I2 (value[8]), @@ -98707,7 +98439,7 @@ module param_cell_unsigned_unq4 N149_10_9 ( .COUT (), .Z (nb0[9]), - .CIN (_N14192), + .CIN (_N14167), .I0 (), .I1 (N154), .I2 (value[9]), @@ -98735,7 +98467,7 @@ module param_cell_unsigned_unq4 .I0 (N63), .I1 (N140), .I2 (N156), - .I3 (_N96009)); + .I3 (_N96788)); // LUT = (I2)|(I3)|(~I0&I1) ; GTP_LUT5 /* \N149_48[0] */ #( @@ -98879,29 +98611,29 @@ module param_cell_unsigned_unq4 .I3 (pluse)); // LUT = (I0&I1&I2)|(I0&I2&I3) ; - GTP_LUT4 /* N156_19 */ #( + GTP_LUT4 /* N156_20 */ #( .INIT(16'b1000000000000000)) - N156_19 ( - .Z (_N104689), + N156_20 ( + .Z (_N105524), .I0 (value[0]), .I1 (value[1]), .I2 (value[2]), .I3 (value[3])); // LUT = I0&I1&I2&I3 ; - GTP_LUT3 /* N156_21 */ #( + GTP_LUT3 /* N156_22 */ #( .INIT(8'b10000000)) - N156_21 ( - .Z (_N104691), + N156_22 ( + .Z (_N105526), .I0 (value[8]), .I1 (value[9]), - .I2 (_N104689)); + .I2 (_N105524)); // LUT = I0&I1&I2 ; - GTP_LUT5 /* N156_22 */ #( + GTP_LUT5 /* N156_23 */ #( .INIT(32'b10000000000000000000000000000000)) - N156_22 ( - .Z (_N104692), + N156_23 ( + .Z (_N105527), .I0 (value[4]), .I1 (value[5]), .I2 (value[6]), @@ -98909,14 +98641,14 @@ module param_cell_unsigned_unq4 .I4 (N142)); // LUT = I0&I1&I2&I3&I4 ; - GTP_LUT4 /* N156_25 */ #( + GTP_LUT4 /* N156_26 */ #( .INIT(16'b0001000000000000)) - N156_25 ( + N156_26 ( .Z (N156), .I0 (N140), - .I1 (_N96009), - .I2 (_N104691), - .I3 (_N104692)); + .I1 (_N96788), + .I2 (_N105526), + .I3 (_N105527)); // LUT = ~I0&~I1&I2&I3 ; GTP_DFF_RE /* \value[0] */ #( @@ -99043,9 +98775,8 @@ module param_manager input akey_right, input akey_up, input clk, - input \param_modify_V/N140 , - input \param_rotate_A/N142 , - input \param_zoom/N142 , + input \param_filiter1_mode/N140 , + input \param_filiter2_mode/N140 , input rd2_rst, output [2:0] filiter1_mode, output [2:0] filiter2_mode, @@ -99064,10 +98795,8 @@ module param_manager output [13:0] selected, output [9:0] zoom, output \param_filiter1_mode/changed_down , - output \param_filiter1_mode/changed_up , - output \param_filiter1_mode/pressed_down , - output \param_filiter1_mode/pressed_up , - output \param_modify_H/pluse + output \param_filiter1_mode/pluse , + output \param_filiter1_mode/pressed_down ); wire N30; wire N33; @@ -99105,36 +98834,39 @@ module param_manager wire [3:0] N346; wire [29:0] N408; wire _N1; - wire _N2742; - wire _N2756; + wire _N2738; + wire _N2752; + wire _N2797; + wire _N2798; wire _N2801; - wire _N2802; - wire _N2805; - wire _N3647; - wire _N3793; - wire _N13813; - wire _N13814; - wire _N13815; - wire _N13816; - wire _N13817; - wire _N13818; - wire _N13819; - wire _N13820; - wire _N13821; - wire _N13822; - wire _N13823; - wire _N13824; - wire _N13825; - wire _N13826; - wire _N13827; - wire _N96763; - wire _N104340; - wire _N104342; - wire _N104344; - wire _N104351; - wire _N104501; - wire _N107262; - wire _N107263; + wire _N3230; + wire _N3669; + wire _N3811; + wire _N13831; + wire _N13832; + wire _N13833; + wire _N13834; + wire _N13835; + wire _N13836; + wire _N13837; + wire _N13838; + wire _N13839; + wire _N13840; + wire _N13841; + wire _N13842; + wire _N13843; + wire _N13844; + wire _N13845; + wire _N97529; + wire _N105179; + wire _N105181; + wire _N105183; + wire _N105190; + wire _N105338; + wire _N108087; + wire _N108088; + wire _N108109; + wire _N108110; wire changed_left; wire changed_right; wire clk_ms; @@ -99192,16 +98924,20 @@ module param_manager wire osd_startY_flags_ff2; wire osd_startY_flags_ff3; wire osd_startY_load; + wire \param_filiter1_mode/N59 ; wire \param_filiter1_mode/N111 ; wire \param_filiter1_mode/N116 ; wire \param_filiter1_mode/N119 ; - wire \param_filiter1_mode/N140 ; wire \param_filiter1_mode/N161 ; - wire \param_filiter1_mode/pluse ; - wire \param_filiter2_mode/N140 ; + wire \param_filiter1_mode/changed_up ; + wire \param_filiter1_mode/pressed_up ; wire \param_modify_H/N72 ; wire \param_modify_H/N140 ; + wire \param_modify_H/N153 ; + wire \param_modify_H/pluse ; wire \param_modify_S/N140 ; + wire \param_modify_S/N153 ; + wire \param_modify_V/N140 ; wire \param_modify_V/N153 ; wire \param_offsetX/N72 ; wire \param_offsetX/N140 ; @@ -99214,12 +98950,12 @@ module param_manager wire \param_osd_char_height/N142 ; wire \param_osd_char_height/pluse ; wire \param_osd_char_width/N140 ; - wire \param_osd_char_width/N142 ; wire \param_osd_startX/N140 ; wire \param_osd_startX/N142 ; wire \param_osd_startX/pluse ; wire \param_osd_startY/N140 ; wire \param_rotate_A/N140 ; + wire \param_zoom/N140 ; wire pressed_left; wire pressed_restore; wire pressed_right; @@ -99240,7 +98976,7 @@ module param_manager GTP_LUT5 /* N9_mux4_3 */ #( .INIT(32'b11111111111111111111111111100000)) N9_mux4_3 ( - .Z (_N2742), + .Z (_N2738), .I0 (ms_cnt[0]), .I1 (ms_cnt[1]), .I2 (ms_cnt[2]), @@ -99251,7 +98987,7 @@ module param_manager GTP_LUT4 /* N9_mux9_4 */ #( .INIT(16'b1111111111111110)) N9_mux9_4 ( - .Z (_N104351), + .Z (_N105190), .I0 (ms_cnt[6]), .I1 (ms_cnt[7]), .I2 (ms_cnt[8]), @@ -99261,18 +98997,18 @@ module param_manager GTP_LUT5 /* N9_mux11 */ #( .INIT(32'b11111111111100001111111110000000)) N9_mux11 ( - .Z (_N2756), - .I0 (_N2742), + .Z (_N2752), + .I0 (_N2738), .I1 (ms_cnt[5]), .I2 (ms_cnt[10]), .I3 (ms_cnt[11]), - .I4 (_N104351)); + .I4 (_N105190)); // LUT = (I3)|(I2&I4)|(I0&I1&I2) ; GTP_LUT3 /* N9_mux15_4 */ #( .INIT(8'b10000000)) N9_mux15_4 ( - .Z (_N96763), + .Z (_N97529), .I0 (ms_cnt[13]), .I1 (ms_cnt[14]), .I2 (ms_cnt[15])); @@ -99285,7 +99021,7 @@ module param_manager .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N13_1_1 ( - .COUT (_N13813), + .COUT (_N13831), .Z (N408[1]), .CIN (), .I0 (ms_cnt[0]), @@ -99296,7 +99032,7 @@ module param_manager .ID ()); // LUT = I1^I0 ; // CARRY = (1'b0) ? CIN : (I4) ; - // ../../sources/designs/others/param_manager.v:57 + // ../../sources/designs/others/param_manager.v:81 GTP_LUT5CARRY /* N13_1_2 */ #( .INIT(32'b01111000011110001000000010000000), @@ -99305,9 +99041,9 @@ module param_manager .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N13_1_2 ( - .COUT (_N13814), + .COUT (_N13832), .Z (N408[2]), - .CIN (_N13813), + .CIN (_N13831), .I0 (ms_cnt[0]), .I1 (ms_cnt[1]), .I2 (ms_cnt[2]), @@ -99316,7 +99052,7 @@ module param_manager .ID ()); // LUT = (I0&I1&~I2)|(~I1&I2)|(~I0&I2) ; // CARRY = (I0&I1&I2) ? CIN : (I4) ; - // ../../sources/designs/others/param_manager.v:57 + // ../../sources/designs/others/param_manager.v:81 GTP_LUT5CARRY /* N13_1_3 */ #( .INIT(32'b01100110011001101100110011001100), @@ -99325,9 +99061,9 @@ module param_manager .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N13_1_3 ( - .COUT (_N13815), + .COUT (_N13833), .Z (N408[3]), - .CIN (_N13814), + .CIN (_N13832), .I0 (), .I1 (ms_cnt[3]), .I2 (), @@ -99336,7 +99072,7 @@ module param_manager .ID ()); // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/others/param_manager.v:57 + // ../../sources/designs/others/param_manager.v:81 GTP_LUT5CARRY /* N13_1_4 */ #( .INIT(32'b01100110011001101100110011001100), @@ -99345,9 +99081,9 @@ module param_manager .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N13_1_4 ( - .COUT (_N13816), + .COUT (_N13834), .Z (N408[4]), - .CIN (_N13815), + .CIN (_N13833), .I0 (), .I1 (ms_cnt[4]), .I2 (), @@ -99356,7 +99092,7 @@ module param_manager .ID ()); // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/others/param_manager.v:57 + // ../../sources/designs/others/param_manager.v:81 GTP_LUT5CARRY /* N13_1_5 */ #( .INIT(32'b01100110011001101100110011001100), @@ -99365,9 +99101,9 @@ module param_manager .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N13_1_5 ( - .COUT (_N13817), + .COUT (_N13835), .Z (N408[5]), - .CIN (_N13816), + .CIN (_N13834), .I0 (), .I1 (ms_cnt[5]), .I2 (), @@ -99376,7 +99112,7 @@ module param_manager .ID ()); // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/others/param_manager.v:57 + // ../../sources/designs/others/param_manager.v:81 GTP_LUT5CARRY /* N13_1_6 */ #( .INIT(32'b01100110011001101100110011001100), @@ -99385,9 +99121,9 @@ module param_manager .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N13_1_6 ( - .COUT (_N13818), + .COUT (_N13836), .Z (N408[6]), - .CIN (_N13817), + .CIN (_N13835), .I0 (), .I1 (ms_cnt[6]), .I2 (), @@ -99396,7 +99132,7 @@ module param_manager .ID ()); // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/others/param_manager.v:57 + // ../../sources/designs/others/param_manager.v:81 GTP_LUT5CARRY /* N13_1_7 */ #( .INIT(32'b01100110011001101100110011001100), @@ -99405,9 +99141,9 @@ module param_manager .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N13_1_7 ( - .COUT (_N13819), + .COUT (_N13837), .Z (N408[7]), - .CIN (_N13818), + .CIN (_N13836), .I0 (), .I1 (ms_cnt[7]), .I2 (), @@ -99416,7 +99152,7 @@ module param_manager .ID ()); // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/others/param_manager.v:57 + // ../../sources/designs/others/param_manager.v:81 GTP_LUT5CARRY /* N13_1_8 */ #( .INIT(32'b01100110011001101100110011001100), @@ -99425,9 +99161,9 @@ module param_manager .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N13_1_8 ( - .COUT (_N13820), + .COUT (_N13838), .Z (N408[8]), - .CIN (_N13819), + .CIN (_N13837), .I0 (), .I1 (ms_cnt[8]), .I2 (), @@ -99436,7 +99172,7 @@ module param_manager .ID ()); // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/others/param_manager.v:57 + // ../../sources/designs/others/param_manager.v:81 GTP_LUT5CARRY /* N13_1_9 */ #( .INIT(32'b01100110011001101100110011001100), @@ -99445,9 +99181,9 @@ module param_manager .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N13_1_9 ( - .COUT (_N13821), + .COUT (_N13839), .Z (N408[9]), - .CIN (_N13820), + .CIN (_N13838), .I0 (), .I1 (ms_cnt[9]), .I2 (), @@ -99456,7 +99192,7 @@ module param_manager .ID ()); // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/others/param_manager.v:57 + // ../../sources/designs/others/param_manager.v:81 GTP_LUT5CARRY /* N13_1_10 */ #( .INIT(32'b01100110011001101100110011001100), @@ -99465,9 +99201,9 @@ module param_manager .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N13_1_10 ( - .COUT (_N13822), + .COUT (_N13840), .Z (N408[10]), - .CIN (_N13821), + .CIN (_N13839), .I0 (), .I1 (ms_cnt[10]), .I2 (), @@ -99476,7 +99212,7 @@ module param_manager .ID ()); // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/others/param_manager.v:57 + // ../../sources/designs/others/param_manager.v:81 GTP_LUT5CARRY /* N13_1_11 */ #( .INIT(32'b01100110011001101100110011001100), @@ -99485,9 +99221,9 @@ module param_manager .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N13_1_11 ( - .COUT (_N13823), + .COUT (_N13841), .Z (N408[11]), - .CIN (_N13822), + .CIN (_N13840), .I0 (), .I1 (ms_cnt[11]), .I2 (), @@ -99496,7 +99232,7 @@ module param_manager .ID ()); // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/others/param_manager.v:57 + // ../../sources/designs/others/param_manager.v:81 GTP_LUT5CARRY /* N13_1_12 */ #( .INIT(32'b01100110011001101100110011001100), @@ -99505,9 +99241,9 @@ module param_manager .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N13_1_12 ( - .COUT (_N13824), + .COUT (_N13842), .Z (N408[12]), - .CIN (_N13823), + .CIN (_N13841), .I0 (), .I1 (ms_cnt[12]), .I2 (), @@ -99516,7 +99252,7 @@ module param_manager .ID ()); // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/others/param_manager.v:57 + // ../../sources/designs/others/param_manager.v:81 GTP_LUT5CARRY /* N13_1_13 */ #( .INIT(32'b01100110011001101100110011001100), @@ -99525,9 +99261,9 @@ module param_manager .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N13_1_13 ( - .COUT (_N13825), + .COUT (_N13843), .Z (N408[13]), - .CIN (_N13824), + .CIN (_N13842), .I0 (), .I1 (ms_cnt[13]), .I2 (), @@ -99536,7 +99272,7 @@ module param_manager .ID ()); // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/others/param_manager.v:57 + // ../../sources/designs/others/param_manager.v:81 GTP_LUT5CARRY /* N13_1_14 */ #( .INIT(32'b01100110011001101100110011001100), @@ -99545,9 +99281,9 @@ module param_manager .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N13_1_14 ( - .COUT (_N13826), + .COUT (_N13844), .Z (N408[14]), - .CIN (_N13825), + .CIN (_N13843), .I0 (), .I1 (ms_cnt[14]), .I2 (), @@ -99556,7 +99292,7 @@ module param_manager .ID ()); // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/others/param_manager.v:57 + // ../../sources/designs/others/param_manager.v:81 GTP_LUT5CARRY /* N13_1_15 */ #( .INIT(32'b01100110011001101100110011001100), @@ -99565,9 +99301,9 @@ module param_manager .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N13_1_15 ( - .COUT (_N13827), + .COUT (_N13845), .Z (N408[15]), - .CIN (_N13826), + .CIN (_N13844), .I0 (), .I1 (ms_cnt[15]), .I2 (), @@ -99576,7 +99312,7 @@ module param_manager .ID ()); // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/others/param_manager.v:57 + // ../../sources/designs/others/param_manager.v:81 GTP_LUT5CARRY /* N13_1_16 */ #( .INIT(32'b01100110011001101100110011001100), @@ -99587,7 +99323,7 @@ module param_manager N13_1_16 ( .COUT (), .Z (N408[16]), - .CIN (_N13827), + .CIN (_N13845), .I0 (), .I1 (ms_cnt[16]), .I2 (), @@ -99596,7 +99332,7 @@ module param_manager .ID ()); // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/others/param_manager.v:57 + // ../../sources/designs/others/param_manager.v:81 GTP_LUT2 /* N30 */ #( .INIT(4'b1000)) @@ -99606,7 +99342,7 @@ module param_manager .I1 (pressed_right)); // defparam N30_vname.orig_name = N30; // LUT = I0&I1 ; - // ../../sources/designs/others/param_manager.v:116 + // ../../sources/designs/others/param_manager.v:140 GTP_LUT4 /* N33_mux3_1 */ #( .INIT(16'b0001111111111111)) @@ -99621,7 +99357,7 @@ module param_manager GTP_LUT2 /* N180_eq0 */ #( .INIT(4'b0110)) N180_eq0 ( - .Z (_N2801), + .Z (_N2797), .I0 (filiter1_mode_flags_ff0), .I1 (filiter1_mode_flags_ff1)); // LUT = (I0&~I1)|(~I0&I1) ; @@ -99629,7 +99365,7 @@ module param_manager GTP_LUT2 /* N184_eq0 */ #( .INIT(4'b0110)) N184_eq0 ( - .Z (_N2802), + .Z (_N2798), .I0 (filiter2_mode_flags_ff0), .I1 (filiter2_mode_flags_ff1)); // LUT = (I0&~I1)|(~I0&I1) ; @@ -99644,12 +99380,12 @@ module param_manager .I3 (zoom_flags_ff3)); // defparam N192_vname.orig_name = N192; // LUT = (I2&~I3)|(~I2&I3)|(I0&~I1)|(~I0&I1) ; - // ../../sources/designs/others/param_manager.v:225 + // ../../sources/designs/others/param_manager.v:249 GTP_LUT2 /* N197_eq0 */ #( .INIT(4'b0110)) N197_eq0 ( - .Z (_N2805), + .Z (_N2801), .I0 (rotate_flags_ff0), .I1 (rotate_flags_ff1)); // LUT = (I0&~I1)|(~I0&I1) ; @@ -99664,7 +99400,7 @@ module param_manager .I3 (osd_startX_flags_ff3)); // defparam N205_vname.orig_name = N205; // LUT = (I2&~I3)|(~I2&I3)|(I0&~I1)|(~I0&I1) ; - // ../../sources/designs/others/param_manager.v:294 + // ../../sources/designs/others/param_manager.v:318 GTP_LUT4 /* N214 */ #( .INIT(16'b0110111111110110)) @@ -99676,7 +99412,7 @@ module param_manager .I3 (osd_startY_flags_ff3)); // defparam N214_vname.orig_name = N214; // LUT = (I2&~I3)|(~I2&I3)|(I0&~I1)|(~I0&I1) ; - // ../../sources/designs/others/param_manager.v:330 + // ../../sources/designs/others/param_manager.v:354 GTP_LUT4 /* N223 */ #( .INIT(16'b0110111111110110)) @@ -99688,7 +99424,7 @@ module param_manager .I3 (osd_char_width_flags_ff3)); // defparam N223_vname.orig_name = N223; // LUT = (I2&~I3)|(~I2&I3)|(I0&~I1)|(~I0&I1) ; - // ../../sources/designs/others/param_manager.v:366 + // ../../sources/designs/others/param_manager.v:390 GTP_LUT4 /* N232 */ #( .INIT(16'b0110111111110110)) @@ -99700,7 +99436,7 @@ module param_manager .I3 (osd_char_height_flags_ff3)); // defparam N232_vname.orig_name = N232; // LUT = (I2&~I3)|(~I2&I3)|(I0&~I1)|(~I0&I1) ; - // ../../sources/designs/others/param_manager.v:403 + // ../../sources/designs/others/param_manager.v:427 GTP_LUT4 /* N241 */ #( .INIT(16'b0110111111110110)) @@ -99712,7 +99448,7 @@ module param_manager .I3 (rotate_A_flags_ff3)); // defparam N241_vname.orig_name = N241; // LUT = (I2&~I3)|(~I2&I3)|(I0&~I1)|(~I0&I1) ; - // ../../sources/designs/others/param_manager.v:439 + // ../../sources/designs/others/param_manager.v:463 GTP_LUT4 /* N250 */ #( .INIT(16'b0110111111110110)) @@ -99724,7 +99460,7 @@ module param_manager .I3 (offsetX_flags_ff3)); // defparam N250_vname.orig_name = N250; // LUT = (I2&~I3)|(~I2&I3)|(I0&~I1)|(~I0&I1) ; - // ../../sources/designs/others/param_manager.v:476 + // ../../sources/designs/others/param_manager.v:500 GTP_LUT4 /* N259 */ #( .INIT(16'b0110111111110110)) @@ -99736,7 +99472,7 @@ module param_manager .I3 (offsetY_flags_ff3)); // defparam N259_vname.orig_name = N259; // LUT = (I2&~I3)|(~I2&I3)|(I0&~I1)|(~I0&I1) ; - // ../../sources/designs/others/param_manager.v:511 + // ../../sources/designs/others/param_manager.v:535 GTP_LUT4 /* N268 */ #( .INIT(16'b0110111111110110)) @@ -99748,7 +99484,7 @@ module param_manager .I3 (modify_H_flags_ff3)); // defparam N268_vname.orig_name = N268; // LUT = (I2&~I3)|(~I2&I3)|(I0&~I1)|(~I0&I1) ; - // ../../sources/designs/others/param_manager.v:547 + // ../../sources/designs/others/param_manager.v:571 GTP_LUT4 /* N277 */ #( .INIT(16'b0110111111110110)) @@ -99760,7 +99496,7 @@ module param_manager .I3 (modify_S_flags_ff3)); // defparam N277_vname.orig_name = N277; // LUT = (I2&~I3)|(~I2&I3)|(I0&~I1)|(~I0&I1) ; - // ../../sources/designs/others/param_manager.v:584 + // ../../sources/designs/others/param_manager.v:608 GTP_LUT4 /* N286 */ #( .INIT(16'b0110111111110110)) @@ -99772,7 +99508,7 @@ module param_manager .I3 (modify_V_flags_ff3)); // defparam N286_vname.orig_name = N286; // LUT = (I2&~I3)|(~I2&I3)|(I0&~I1)|(~I0&I1) ; - // ../../sources/designs/others/param_manager.v:621 + // ../../sources/designs/others/param_manager.v:645 GTP_LUT1 /* N291 */ #( .INIT(2'b01)) @@ -99785,7 +99521,7 @@ module param_manager GTP_LUT4 /* N314_22 */ #( .INIT(16'b0000000000000001)) N314_22 ( - .Z (_N104340), + .Z (_N105179), .I0 (ms_cnt[0]), .I1 (ms_cnt[1]), .I2 (ms_cnt[2]), @@ -99795,7 +99531,7 @@ module param_manager GTP_LUT4 /* N314_24 */ #( .INIT(16'b0000000000001000)) N314_24 ( - .Z (_N104342), + .Z (_N105181), .I0 (ms_cnt[3]), .I1 (ms_cnt[6]), .I2 (ms_cnt[10]), @@ -99805,12 +99541,12 @@ module param_manager GTP_LUT5 /* N314_26 */ #( .INIT(32'b00000000000000010000000000000000)) N314_26 ( - .Z (_N104344), + .Z (_N105183), .I0 (ms_cnt[5]), .I1 (ms_cnt[7]), .I2 (ms_cnt[8]), .I3 (ms_cnt[9]), - .I4 (_N104340)); + .I4 (_N105179)); // LUT = ~I0&~I1&~I2&~I3&I4 ; GTP_LUT5 /* N314_28 */ #( @@ -99819,9 +99555,9 @@ module param_manager .Z (N314), .I0 (ms_cnt[11]), .I1 (ms_cnt[16]), - .I2 (_N96763), - .I3 (_N104342), - .I4 (_N104344)); + .I2 (_N97529), + .I3 (_N105181), + .I4 (_N105183)); // LUT = I0&I1&I2&I3&I4 ; GTP_LUT1 /* N315 */ #( @@ -99842,7 +99578,7 @@ module param_manager .I3 (index[3])); // defparam N319_vname.orig_name = N319; // LUT = ~I0&~I1&~I2&~I3 ; - // ../../sources/designs/others/param_manager.v:123 + // ../../sources/designs/others/param_manager.v:147 GTP_LUT4 /* N321 */ #( .INIT(16'b0000000000000010)) @@ -99854,7 +99590,7 @@ module param_manager .I3 (index[3])); // defparam N321_vname.orig_name = N321; // LUT = I0&~I1&~I2&~I3 ; - // ../../sources/designs/others/param_manager.v:139 + // ../../sources/designs/others/param_manager.v:163 GTP_LUT4 /* N322 */ #( .INIT(16'b0000000000000100)) @@ -99866,7 +99602,7 @@ module param_manager .I3 (index[3])); // defparam N322_vname.orig_name = N322; // LUT = ~I0&I1&~I2&~I3 ; - // ../../sources/designs/others/param_manager.v:139 + // ../../sources/designs/others/param_manager.v:163 GTP_LUT4 /* N323 */ #( .INIT(16'b0000000000001000)) @@ -99878,7 +99614,7 @@ module param_manager .I3 (index[3])); // defparam N323_vname.orig_name = N323; // LUT = I0&I1&~I2&~I3 ; - // ../../sources/designs/others/param_manager.v:139 + // ../../sources/designs/others/param_manager.v:163 GTP_LUT4 /* N324 */ #( .INIT(16'b0000000000010000)) @@ -99890,7 +99626,7 @@ module param_manager .I3 (index[3])); // defparam N324_vname.orig_name = N324; // LUT = ~I0&~I1&I2&~I3 ; - // ../../sources/designs/others/param_manager.v:139 + // ../../sources/designs/others/param_manager.v:163 GTP_LUT4 /* N325 */ #( .INIT(16'b0000000000100000)) @@ -99902,7 +99638,7 @@ module param_manager .I3 (index[3])); // defparam N325_vname.orig_name = N325; // LUT = I0&~I1&I2&~I3 ; - // ../../sources/designs/others/param_manager.v:139 + // ../../sources/designs/others/param_manager.v:163 GTP_LUT4 /* N326 */ #( .INIT(16'b0000000001000000)) @@ -99914,7 +99650,7 @@ module param_manager .I3 (index[3])); // defparam N326_vname.orig_name = N326; // LUT = ~I0&I1&I2&~I3 ; - // ../../sources/designs/others/param_manager.v:139 + // ../../sources/designs/others/param_manager.v:163 GTP_LUT4 /* N327 */ #( .INIT(16'b0000000010000000)) @@ -99926,7 +99662,7 @@ module param_manager .I3 (index[3])); // defparam N327_vname.orig_name = N327; // LUT = I0&I1&I2&~I3 ; - // ../../sources/designs/others/param_manager.v:139 + // ../../sources/designs/others/param_manager.v:163 GTP_LUT4 /* N328 */ #( .INIT(16'b0000000100000000)) @@ -99938,7 +99674,7 @@ module param_manager .I3 (index[3])); // defparam N328_vname.orig_name = N328; // LUT = ~I0&~I1&~I2&I3 ; - // ../../sources/designs/others/param_manager.v:139 + // ../../sources/designs/others/param_manager.v:163 GTP_LUT4 /* N329 */ #( .INIT(16'b0000001000000000)) @@ -99950,7 +99686,7 @@ module param_manager .I3 (index[3])); // defparam N329_vname.orig_name = N329; // LUT = I0&~I1&~I2&I3 ; - // ../../sources/designs/others/param_manager.v:139 + // ../../sources/designs/others/param_manager.v:163 GTP_LUT4 /* N330 */ #( .INIT(16'b0000010000000000)) @@ -99962,7 +99698,7 @@ module param_manager .I3 (index[3])); // defparam N330_vname.orig_name = N330; // LUT = ~I0&I1&~I2&I3 ; - // ../../sources/designs/others/param_manager.v:139 + // ../../sources/designs/others/param_manager.v:163 GTP_LUT4 /* N331 */ #( .INIT(16'b0000100000000000)) @@ -99974,7 +99710,7 @@ module param_manager .I3 (index[3])); // defparam N331_vname.orig_name = N331; // LUT = I0&I1&~I2&I3 ; - // ../../sources/designs/others/param_manager.v:139 + // ../../sources/designs/others/param_manager.v:163 GTP_LUT4 /* N332 */ #( .INIT(16'b0001000000000000)) @@ -99986,7 +99722,7 @@ module param_manager .I3 (index[3])); // defparam N332_vname.orig_name = N332; // LUT = ~I0&~I1&I2&I3 ; - // ../../sources/designs/others/param_manager.v:139 + // ../../sources/designs/others/param_manager.v:163 GTP_LUT4 /* N333 */ #( .INIT(16'b0010000000000000)) @@ -99998,7 +99734,7 @@ module param_manager .I3 (index[3])); // defparam N333_vname.orig_name = N333; // LUT = I0&~I1&I2&I3 ; - // ../../sources/designs/others/param_manager.v:139 + // ../../sources/designs/others/param_manager.v:163 GTP_LUT2 /* N335 */ #( .INIT(4'b1110)) @@ -100008,7 +99744,7 @@ module param_manager .I1 (N314)); // defparam N335_vname.orig_name = N335; // LUT = (I0)|(I1) ; - // ../../sources/designs/others/param_manager.v:47 + // ../../sources/designs/others/param_manager.v:71 GTP_LUT4 /* N344 */ #( .INIT(16'b1011101010101010)) @@ -100020,7 +99756,7 @@ module param_manager .I3 (pressed_right)); // defparam N344_vname.orig_name = N344; // LUT = (I0)|(~I1&I2&I3) ; - // ../../sources/designs/others/param_manager.v:26 + // ../../sources/designs/others/param_manager.v:36 GTP_LUT4 /* N345 */ #( .INIT(16'b1110110010100000)) @@ -100032,7 +99768,7 @@ module param_manager .I3 (pressed_right)); // defparam N345_vname.orig_name = N345; // LUT = (I0&I2)|(I1&I3) ; - // ../../sources/designs/others/param_manager.v:113 + // ../../sources/designs/others/param_manager.v:137 GTP_LUT4 /* \N346_2[0] */ #( .INIT(16'b0111100011100001)) @@ -100075,17 +99811,17 @@ module param_manager .D (_N1), .R (rd2_rst)); // defparam clk_ms_vname.orig_name = clk_ms; - // ../../sources/designs/others/param_manager.v:48 + // ../../sources/designs/others/param_manager.v:72 GTP_LUT5 /* \clk_ms_d[0] */ #( .INIT(32'b11001100110111111100110011111111)) \clk_ms_d[0] ( .Z (_N1), - .I0 (_N2756), + .I0 (_N2752), .I1 (N314), .I2 (ms_cnt[12]), .I3 (ms_cnt[16]), - .I4 (_N96763)); + .I4 (_N97529)); // LUT = (I1)|(~I3&~I4)|(~I2&~I3)|(~I0&~I3) ; GTP_DFF /* filiter1_mode_flags_ff0 */ #( @@ -100096,7 +99832,7 @@ module param_manager .CLK (clk), .D (mem_flags[0])); // defparam filiter1_mode_flags_ff0_vname.orig_name = filiter1_mode_flags_ff0; - // ../../sources/designs/others/param_manager.v:155 + // ../../sources/designs/others/param_manager.v:179 GTP_DFF /* filiter1_mode_flags_ff1 */ #( .GRS_EN("TRUE"), @@ -100106,7 +99842,7 @@ module param_manager .CLK (clk), .D (filiter1_mode_flags_ff0)); // defparam filiter1_mode_flags_ff1_vname.orig_name = filiter1_mode_flags_ff1; - // ../../sources/designs/others/param_manager.v:155 + // ../../sources/designs/others/param_manager.v:179 GTP_DFF /* filiter1_mode_load */ #( .GRS_EN("TRUE"), @@ -100114,9 +99850,9 @@ module param_manager filiter1_mode_load_vname ( .Q (filiter1_mode_load), .CLK (clk), - .D (_N2801)); + .D (_N2797)); // defparam filiter1_mode_load_vname.orig_name = filiter1_mode_load; - // ../../sources/designs/others/param_manager.v:155 + // ../../sources/designs/others/param_manager.v:179 GTP_DFF /* filiter2_mode_flags_ff0 */ #( .GRS_EN("TRUE"), @@ -100126,7 +99862,7 @@ module param_manager .CLK (clk), .D (mem_flags[1])); // defparam filiter2_mode_flags_ff0_vname.orig_name = filiter2_mode_flags_ff0; - // ../../sources/designs/others/param_manager.v:187 + // ../../sources/designs/others/param_manager.v:211 GTP_DFF /* filiter2_mode_flags_ff1 */ #( .GRS_EN("TRUE"), @@ -100136,7 +99872,7 @@ module param_manager .CLK (clk), .D (filiter2_mode_flags_ff0)); // defparam filiter2_mode_flags_ff1_vname.orig_name = filiter2_mode_flags_ff1; - // ../../sources/designs/others/param_manager.v:187 + // ../../sources/designs/others/param_manager.v:211 GTP_DFF /* filiter2_mode_load */ #( .GRS_EN("TRUE"), @@ -100144,9 +99880,9 @@ module param_manager filiter2_mode_load_vname ( .Q (filiter2_mode_load), .CLK (clk), - .D (_N2802)); + .D (_N2798)); // defparam filiter2_mode_load_vname.orig_name = filiter2_mode_load; - // ../../sources/designs/others/param_manager.v:187 + // ../../sources/designs/others/param_manager.v:211 GTP_DFF_RE /* \index[0] */ #( .GRS_EN("TRUE"), @@ -100157,7 +99893,7 @@ module param_manager .CLK (clk), .D (N315), .R (N344)); - // ../../sources/designs/others/param_manager.v:113 + // ../../sources/designs/others/param_manager.v:137 GTP_DFF_RE /* \index[1] */ #( .GRS_EN("TRUE"), @@ -100168,7 +99904,7 @@ module param_manager .CLK (clk), .D (nb0[1]), .R (N344)); - // ../../sources/designs/others/param_manager.v:113 + // ../../sources/designs/others/param_manager.v:137 GTP_DFF_RE /* \index[2] */ #( .GRS_EN("TRUE"), @@ -100179,7 +99915,7 @@ module param_manager .CLK (clk), .D (N346[2]), .R (N344)); - // ../../sources/designs/others/param_manager.v:113 + // ../../sources/designs/others/param_manager.v:137 GTP_DFF_RE /* \index[3] */ #( .GRS_EN("TRUE"), @@ -100190,7 +99926,7 @@ module param_manager .CLK (clk), .D (N346[3]), .R (N344)); - // ../../sources/designs/others/param_manager.v:113 + // ../../sources/designs/others/param_manager.v:137 key_debounce_unq64 key_debounce_key_left ( .change (changed_left), @@ -100203,7 +99939,7 @@ module param_manager .\param_manager_inst/param_filiter1_mode/pressed_down (\param_filiter1_mode/pressed_down ), .\param_manager_inst/param_filiter1_mode/pressed_up (\param_filiter1_mode/pressed_up ), .rd2_rst (rd2_rst)); - // ../../sources/designs/others/param_manager.v:78 + // ../../sources/designs/others/param_manager.v:102 key_debounce_unq66 key_debounce_key_restore ( .pressed (pressed_restore), @@ -100211,7 +99947,7 @@ module param_manager .key_in (akey_restore), .pluse_ms (\key_debounce_key_left/pluse_ms ), .rd2_rst (rd2_rst)); - // ../../sources/designs/others/param_manager.v:102 + // ../../sources/designs/others/param_manager.v:126 key_debounce_unq68 key_debounce_key_right ( .change (changed_right), @@ -100220,7 +99956,7 @@ module param_manager .key_in (akey_right), .pluse_ms (\key_debounce_key_left/pluse_ms ), .rd2_rst (rd2_rst)); - // ../../sources/designs/others/param_manager.v:90 + // ../../sources/designs/others/param_manager.v:114 GTP_DFF /* modify_H_flags_ff0 */ #( .GRS_EN("TRUE"), @@ -100230,7 +99966,7 @@ module param_manager .CLK (clk), .D (mem_flags[19])); // defparam modify_H_flags_ff0_vname.orig_name = modify_H_flags_ff0; - // ../../sources/designs/others/param_manager.v:542 + // ../../sources/designs/others/param_manager.v:566 GTP_DFF /* modify_H_flags_ff1 */ #( .GRS_EN("TRUE"), @@ -100240,7 +99976,7 @@ module param_manager .CLK (clk), .D (modify_H_flags_ff0)); // defparam modify_H_flags_ff1_vname.orig_name = modify_H_flags_ff1; - // ../../sources/designs/others/param_manager.v:542 + // ../../sources/designs/others/param_manager.v:566 GTP_DFF /* modify_H_flags_ff2 */ #( .GRS_EN("TRUE"), @@ -100250,7 +99986,7 @@ module param_manager .CLK (clk), .D (mem_flags[20])); // defparam modify_H_flags_ff2_vname.orig_name = modify_H_flags_ff2; - // ../../sources/designs/others/param_manager.v:542 + // ../../sources/designs/others/param_manager.v:566 GTP_DFF /* modify_H_flags_ff3 */ #( .GRS_EN("TRUE"), @@ -100260,7 +99996,7 @@ module param_manager .CLK (clk), .D (modify_H_flags_ff2)); // defparam modify_H_flags_ff3_vname.orig_name = modify_H_flags_ff3; - // ../../sources/designs/others/param_manager.v:542 + // ../../sources/designs/others/param_manager.v:566 GTP_DFF /* modify_H_load */ #( .GRS_EN("TRUE"), @@ -100270,7 +100006,7 @@ module param_manager .CLK (clk), .D (N268)); // defparam modify_H_load_vname.orig_name = modify_H_load; - // ../../sources/designs/others/param_manager.v:542 + // ../../sources/designs/others/param_manager.v:566 GTP_DFF /* modify_S_flags_ff0 */ #( .GRS_EN("TRUE"), @@ -100280,7 +100016,7 @@ module param_manager .CLK (clk), .D (mem_flags[21])); // defparam modify_S_flags_ff0_vname.orig_name = modify_S_flags_ff0; - // ../../sources/designs/others/param_manager.v:579 + // ../../sources/designs/others/param_manager.v:603 GTP_DFF /* modify_S_flags_ff1 */ #( .GRS_EN("TRUE"), @@ -100290,7 +100026,7 @@ module param_manager .CLK (clk), .D (modify_S_flags_ff0)); // defparam modify_S_flags_ff1_vname.orig_name = modify_S_flags_ff1; - // ../../sources/designs/others/param_manager.v:579 + // ../../sources/designs/others/param_manager.v:603 GTP_DFF /* modify_S_flags_ff2 */ #( .GRS_EN("TRUE"), @@ -100300,7 +100036,7 @@ module param_manager .CLK (clk), .D (mem_flags[22])); // defparam modify_S_flags_ff2_vname.orig_name = modify_S_flags_ff2; - // ../../sources/designs/others/param_manager.v:579 + // ../../sources/designs/others/param_manager.v:603 GTP_DFF /* modify_S_flags_ff3 */ #( .GRS_EN("TRUE"), @@ -100310,7 +100046,7 @@ module param_manager .CLK (clk), .D (modify_S_flags_ff2)); // defparam modify_S_flags_ff3_vname.orig_name = modify_S_flags_ff3; - // ../../sources/designs/others/param_manager.v:579 + // ../../sources/designs/others/param_manager.v:603 GTP_DFF /* modify_S_load */ #( .GRS_EN("TRUE"), @@ -100320,7 +100056,7 @@ module param_manager .CLK (clk), .D (N277)); // defparam modify_S_load_vname.orig_name = modify_S_load; - // ../../sources/designs/others/param_manager.v:579 + // ../../sources/designs/others/param_manager.v:603 GTP_DFF /* modify_V_flags_ff0 */ #( .GRS_EN("TRUE"), @@ -100330,7 +100066,7 @@ module param_manager .CLK (clk), .D (mem_flags[23])); // defparam modify_V_flags_ff0_vname.orig_name = modify_V_flags_ff0; - // ../../sources/designs/others/param_manager.v:616 + // ../../sources/designs/others/param_manager.v:640 GTP_DFF /* modify_V_flags_ff1 */ #( .GRS_EN("TRUE"), @@ -100340,7 +100076,7 @@ module param_manager .CLK (clk), .D (modify_V_flags_ff0)); // defparam modify_V_flags_ff1_vname.orig_name = modify_V_flags_ff1; - // ../../sources/designs/others/param_manager.v:616 + // ../../sources/designs/others/param_manager.v:640 GTP_DFF /* modify_V_flags_ff2 */ #( .GRS_EN("TRUE"), @@ -100350,7 +100086,7 @@ module param_manager .CLK (clk), .D (mem_flags[24])); // defparam modify_V_flags_ff2_vname.orig_name = modify_V_flags_ff2; - // ../../sources/designs/others/param_manager.v:616 + // ../../sources/designs/others/param_manager.v:640 GTP_DFF /* modify_V_flags_ff3 */ #( .GRS_EN("TRUE"), @@ -100360,7 +100096,7 @@ module param_manager .CLK (clk), .D (modify_V_flags_ff2)); // defparam modify_V_flags_ff3_vname.orig_name = modify_V_flags_ff3; - // ../../sources/designs/others/param_manager.v:616 + // ../../sources/designs/others/param_manager.v:640 GTP_DFF /* modify_V_load */ #( .GRS_EN("TRUE"), @@ -100370,7 +100106,7 @@ module param_manager .CLK (clk), .D (N286)); // defparam modify_V_load_vname.orig_name = modify_V_load; - // ../../sources/designs/others/param_manager.v:616 + // ../../sources/designs/others/param_manager.v:640 GTP_DFF_R /* \ms_cnt[0] */ #( .GRS_EN("TRUE"), @@ -100380,7 +100116,7 @@ module param_manager .CLK (clk), .D (N291), .R (N335)); - // ../../sources/designs/others/param_manager.v:48 + // ../../sources/designs/others/param_manager.v:72 GTP_DFF_R /* \ms_cnt[1] */ #( .GRS_EN("TRUE"), @@ -100390,7 +100126,7 @@ module param_manager .CLK (clk), .D (N408[1]), .R (N335)); - // ../../sources/designs/others/param_manager.v:48 + // ../../sources/designs/others/param_manager.v:72 GTP_DFF_R /* \ms_cnt[2] */ #( .GRS_EN("TRUE"), @@ -100400,7 +100136,7 @@ module param_manager .CLK (clk), .D (N408[2]), .R (N335)); - // ../../sources/designs/others/param_manager.v:48 + // ../../sources/designs/others/param_manager.v:72 GTP_DFF_R /* \ms_cnt[3] */ #( .GRS_EN("TRUE"), @@ -100410,7 +100146,7 @@ module param_manager .CLK (clk), .D (N408[3]), .R (N335)); - // ../../sources/designs/others/param_manager.v:48 + // ../../sources/designs/others/param_manager.v:72 GTP_DFF_R /* \ms_cnt[4] */ #( .GRS_EN("TRUE"), @@ -100420,7 +100156,7 @@ module param_manager .CLK (clk), .D (N408[4]), .R (N335)); - // ../../sources/designs/others/param_manager.v:48 + // ../../sources/designs/others/param_manager.v:72 GTP_DFF_R /* \ms_cnt[5] */ #( .GRS_EN("TRUE"), @@ -100430,7 +100166,7 @@ module param_manager .CLK (clk), .D (N408[5]), .R (N335)); - // ../../sources/designs/others/param_manager.v:48 + // ../../sources/designs/others/param_manager.v:72 GTP_DFF_R /* \ms_cnt[6] */ #( .GRS_EN("TRUE"), @@ -100440,7 +100176,7 @@ module param_manager .CLK (clk), .D (N408[6]), .R (N335)); - // ../../sources/designs/others/param_manager.v:48 + // ../../sources/designs/others/param_manager.v:72 GTP_DFF_R /* \ms_cnt[7] */ #( .GRS_EN("TRUE"), @@ -100450,7 +100186,7 @@ module param_manager .CLK (clk), .D (N408[7]), .R (N335)); - // ../../sources/designs/others/param_manager.v:48 + // ../../sources/designs/others/param_manager.v:72 GTP_DFF_R /* \ms_cnt[8] */ #( .GRS_EN("TRUE"), @@ -100460,7 +100196,7 @@ module param_manager .CLK (clk), .D (N408[8]), .R (N335)); - // ../../sources/designs/others/param_manager.v:48 + // ../../sources/designs/others/param_manager.v:72 GTP_DFF_R /* \ms_cnt[9] */ #( .GRS_EN("TRUE"), @@ -100470,7 +100206,7 @@ module param_manager .CLK (clk), .D (N408[9]), .R (N335)); - // ../../sources/designs/others/param_manager.v:48 + // ../../sources/designs/others/param_manager.v:72 GTP_DFF_R /* \ms_cnt[10] */ #( .GRS_EN("TRUE"), @@ -100480,7 +100216,7 @@ module param_manager .CLK (clk), .D (N408[10]), .R (N335)); - // ../../sources/designs/others/param_manager.v:48 + // ../../sources/designs/others/param_manager.v:72 GTP_DFF_R /* \ms_cnt[11] */ #( .GRS_EN("TRUE"), @@ -100490,7 +100226,7 @@ module param_manager .CLK (clk), .D (N408[11]), .R (N335)); - // ../../sources/designs/others/param_manager.v:48 + // ../../sources/designs/others/param_manager.v:72 GTP_DFF_R /* \ms_cnt[12] */ #( .GRS_EN("TRUE"), @@ -100500,7 +100236,7 @@ module param_manager .CLK (clk), .D (N408[12]), .R (N335)); - // ../../sources/designs/others/param_manager.v:48 + // ../../sources/designs/others/param_manager.v:72 GTP_DFF_R /* \ms_cnt[13] */ #( .GRS_EN("TRUE"), @@ -100510,7 +100246,7 @@ module param_manager .CLK (clk), .D (N408[13]), .R (N335)); - // ../../sources/designs/others/param_manager.v:48 + // ../../sources/designs/others/param_manager.v:72 GTP_DFF_R /* \ms_cnt[14] */ #( .GRS_EN("TRUE"), @@ -100520,7 +100256,7 @@ module param_manager .CLK (clk), .D (N408[14]), .R (N335)); - // ../../sources/designs/others/param_manager.v:48 + // ../../sources/designs/others/param_manager.v:72 GTP_DFF_R /* \ms_cnt[15] */ #( .GRS_EN("TRUE"), @@ -100530,7 +100266,7 @@ module param_manager .CLK (clk), .D (N408[15]), .R (N335)); - // ../../sources/designs/others/param_manager.v:48 + // ../../sources/designs/others/param_manager.v:72 GTP_DFF_R /* \ms_cnt[16] */ #( .GRS_EN("TRUE"), @@ -100540,7 +100276,7 @@ module param_manager .CLK (clk), .D (N408[16]), .R (N335)); - // ../../sources/designs/others/param_manager.v:48 + // ../../sources/designs/others/param_manager.v:72 GTP_DFF /* offsetX_flags_ff0 */ #( .GRS_EN("TRUE"), @@ -100550,7 +100286,7 @@ module param_manager .CLK (clk), .D (mem_flags[15])); // defparam offsetX_flags_ff0_vname.orig_name = offsetX_flags_ff0; - // ../../sources/designs/others/param_manager.v:471 + // ../../sources/designs/others/param_manager.v:495 GTP_DFF /* offsetX_flags_ff1 */ #( .GRS_EN("TRUE"), @@ -100560,7 +100296,7 @@ module param_manager .CLK (clk), .D (offsetX_flags_ff0)); // defparam offsetX_flags_ff1_vname.orig_name = offsetX_flags_ff1; - // ../../sources/designs/others/param_manager.v:471 + // ../../sources/designs/others/param_manager.v:495 GTP_DFF /* offsetX_flags_ff2 */ #( .GRS_EN("TRUE"), @@ -100570,7 +100306,7 @@ module param_manager .CLK (clk), .D (mem_flags[16])); // defparam offsetX_flags_ff2_vname.orig_name = offsetX_flags_ff2; - // ../../sources/designs/others/param_manager.v:471 + // ../../sources/designs/others/param_manager.v:495 GTP_DFF /* offsetX_flags_ff3 */ #( .GRS_EN("TRUE"), @@ -100580,7 +100316,7 @@ module param_manager .CLK (clk), .D (offsetX_flags_ff2)); // defparam offsetX_flags_ff3_vname.orig_name = offsetX_flags_ff3; - // ../../sources/designs/others/param_manager.v:471 + // ../../sources/designs/others/param_manager.v:495 GTP_DFF /* offsetX_load */ #( .GRS_EN("TRUE"), @@ -100590,7 +100326,7 @@ module param_manager .CLK (clk), .D (N250)); // defparam offsetX_load_vname.orig_name = offsetX_load; - // ../../sources/designs/others/param_manager.v:471 + // ../../sources/designs/others/param_manager.v:495 GTP_DFF /* offsetY_flags_ff0 */ #( .GRS_EN("TRUE"), @@ -100600,7 +100336,7 @@ module param_manager .CLK (clk), .D (mem_flags[17])); // defparam offsetY_flags_ff0_vname.orig_name = offsetY_flags_ff0; - // ../../sources/designs/others/param_manager.v:506 + // ../../sources/designs/others/param_manager.v:530 GTP_DFF /* offsetY_flags_ff1 */ #( .GRS_EN("TRUE"), @@ -100610,7 +100346,7 @@ module param_manager .CLK (clk), .D (offsetY_flags_ff0)); // defparam offsetY_flags_ff1_vname.orig_name = offsetY_flags_ff1; - // ../../sources/designs/others/param_manager.v:506 + // ../../sources/designs/others/param_manager.v:530 GTP_DFF /* offsetY_flags_ff2 */ #( .GRS_EN("TRUE"), @@ -100620,7 +100356,7 @@ module param_manager .CLK (clk), .D (mem_flags[18])); // defparam offsetY_flags_ff2_vname.orig_name = offsetY_flags_ff2; - // ../../sources/designs/others/param_manager.v:506 + // ../../sources/designs/others/param_manager.v:530 GTP_DFF /* offsetY_flags_ff3 */ #( .GRS_EN("TRUE"), @@ -100630,7 +100366,7 @@ module param_manager .CLK (clk), .D (offsetY_flags_ff2)); // defparam offsetY_flags_ff3_vname.orig_name = offsetY_flags_ff3; - // ../../sources/designs/others/param_manager.v:506 + // ../../sources/designs/others/param_manager.v:530 GTP_DFF /* offsetY_load */ #( .GRS_EN("TRUE"), @@ -100640,7 +100376,7 @@ module param_manager .CLK (clk), .D (N259)); // defparam offsetY_load_vname.orig_name = offsetY_load; - // ../../sources/designs/others/param_manager.v:506 + // ../../sources/designs/others/param_manager.v:530 GTP_DFF /* osd_char_height_flags_ff0 */ #( .GRS_EN("TRUE"), @@ -100650,7 +100386,7 @@ module param_manager .CLK (clk), .D (mem_flags[11])); // defparam osd_char_height_flags_ff0_vname.orig_name = osd_char_height_flags_ff0; - // ../../sources/designs/others/param_manager.v:398 + // ../../sources/designs/others/param_manager.v:422 GTP_DFF /* osd_char_height_flags_ff1 */ #( .GRS_EN("TRUE"), @@ -100660,7 +100396,7 @@ module param_manager .CLK (clk), .D (osd_char_height_flags_ff0)); // defparam osd_char_height_flags_ff1_vname.orig_name = osd_char_height_flags_ff1; - // ../../sources/designs/others/param_manager.v:398 + // ../../sources/designs/others/param_manager.v:422 GTP_DFF /* osd_char_height_flags_ff2 */ #( .GRS_EN("TRUE"), @@ -100670,7 +100406,7 @@ module param_manager .CLK (clk), .D (mem_flags[12])); // defparam osd_char_height_flags_ff2_vname.orig_name = osd_char_height_flags_ff2; - // ../../sources/designs/others/param_manager.v:398 + // ../../sources/designs/others/param_manager.v:422 GTP_DFF /* osd_char_height_flags_ff3 */ #( .GRS_EN("TRUE"), @@ -100680,7 +100416,7 @@ module param_manager .CLK (clk), .D (osd_char_height_flags_ff2)); // defparam osd_char_height_flags_ff3_vname.orig_name = osd_char_height_flags_ff3; - // ../../sources/designs/others/param_manager.v:398 + // ../../sources/designs/others/param_manager.v:422 GTP_DFF /* osd_char_height_load */ #( .GRS_EN("TRUE"), @@ -100690,7 +100426,7 @@ module param_manager .CLK (clk), .D (N232)); // defparam osd_char_height_load_vname.orig_name = osd_char_height_load; - // ../../sources/designs/others/param_manager.v:398 + // ../../sources/designs/others/param_manager.v:422 GTP_DFF /* osd_char_width_flags_ff0 */ #( .GRS_EN("TRUE"), @@ -100700,7 +100436,7 @@ module param_manager .CLK (clk), .D (mem_flags[9])); // defparam osd_char_width_flags_ff0_vname.orig_name = osd_char_width_flags_ff0; - // ../../sources/designs/others/param_manager.v:361 + // ../../sources/designs/others/param_manager.v:385 GTP_DFF /* osd_char_width_flags_ff1 */ #( .GRS_EN("TRUE"), @@ -100710,7 +100446,7 @@ module param_manager .CLK (clk), .D (osd_char_width_flags_ff0)); // defparam osd_char_width_flags_ff1_vname.orig_name = osd_char_width_flags_ff1; - // ../../sources/designs/others/param_manager.v:361 + // ../../sources/designs/others/param_manager.v:385 GTP_DFF /* osd_char_width_flags_ff2 */ #( .GRS_EN("TRUE"), @@ -100720,7 +100456,7 @@ module param_manager .CLK (clk), .D (mem_flags[10])); // defparam osd_char_width_flags_ff2_vname.orig_name = osd_char_width_flags_ff2; - // ../../sources/designs/others/param_manager.v:361 + // ../../sources/designs/others/param_manager.v:385 GTP_DFF /* osd_char_width_flags_ff3 */ #( .GRS_EN("TRUE"), @@ -100730,7 +100466,7 @@ module param_manager .CLK (clk), .D (osd_char_width_flags_ff2)); // defparam osd_char_width_flags_ff3_vname.orig_name = osd_char_width_flags_ff3; - // ../../sources/designs/others/param_manager.v:361 + // ../../sources/designs/others/param_manager.v:385 GTP_DFF /* osd_char_width_load */ #( .GRS_EN("TRUE"), @@ -100740,7 +100476,7 @@ module param_manager .CLK (clk), .D (N223)); // defparam osd_char_width_load_vname.orig_name = osd_char_width_load; - // ../../sources/designs/others/param_manager.v:361 + // ../../sources/designs/others/param_manager.v:385 GTP_DFF /* osd_startX_flags_ff0 */ #( .GRS_EN("TRUE"), @@ -100750,7 +100486,7 @@ module param_manager .CLK (clk), .D (mem_flags[5])); // defparam osd_startX_flags_ff0_vname.orig_name = osd_startX_flags_ff0; - // ../../sources/designs/others/param_manager.v:289 + // ../../sources/designs/others/param_manager.v:313 GTP_DFF /* osd_startX_flags_ff1 */ #( .GRS_EN("TRUE"), @@ -100760,7 +100496,7 @@ module param_manager .CLK (clk), .D (osd_startX_flags_ff0)); // defparam osd_startX_flags_ff1_vname.orig_name = osd_startX_flags_ff1; - // ../../sources/designs/others/param_manager.v:289 + // ../../sources/designs/others/param_manager.v:313 GTP_DFF /* osd_startX_flags_ff2 */ #( .GRS_EN("TRUE"), @@ -100770,7 +100506,7 @@ module param_manager .CLK (clk), .D (mem_flags[6])); // defparam osd_startX_flags_ff2_vname.orig_name = osd_startX_flags_ff2; - // ../../sources/designs/others/param_manager.v:289 + // ../../sources/designs/others/param_manager.v:313 GTP_DFF /* osd_startX_flags_ff3 */ #( .GRS_EN("TRUE"), @@ -100780,7 +100516,7 @@ module param_manager .CLK (clk), .D (osd_startX_flags_ff2)); // defparam osd_startX_flags_ff3_vname.orig_name = osd_startX_flags_ff3; - // ../../sources/designs/others/param_manager.v:289 + // ../../sources/designs/others/param_manager.v:313 GTP_DFF /* osd_startX_load */ #( .GRS_EN("TRUE"), @@ -100790,7 +100526,7 @@ module param_manager .CLK (clk), .D (N205)); // defparam osd_startX_load_vname.orig_name = osd_startX_load; - // ../../sources/designs/others/param_manager.v:289 + // ../../sources/designs/others/param_manager.v:313 GTP_DFF /* osd_startY_flags_ff0 */ #( .GRS_EN("TRUE"), @@ -100800,7 +100536,7 @@ module param_manager .CLK (clk), .D (mem_flags[7])); // defparam osd_startY_flags_ff0_vname.orig_name = osd_startY_flags_ff0; - // ../../sources/designs/others/param_manager.v:325 + // ../../sources/designs/others/param_manager.v:349 GTP_DFF /* osd_startY_flags_ff1 */ #( .GRS_EN("TRUE"), @@ -100810,7 +100546,7 @@ module param_manager .CLK (clk), .D (osd_startY_flags_ff0)); // defparam osd_startY_flags_ff1_vname.orig_name = osd_startY_flags_ff1; - // ../../sources/designs/others/param_manager.v:325 + // ../../sources/designs/others/param_manager.v:349 GTP_DFF /* osd_startY_flags_ff2 */ #( .GRS_EN("TRUE"), @@ -100820,7 +100556,7 @@ module param_manager .CLK (clk), .D (mem_flags[8])); // defparam osd_startY_flags_ff2_vname.orig_name = osd_startY_flags_ff2; - // ../../sources/designs/others/param_manager.v:325 + // ../../sources/designs/others/param_manager.v:349 GTP_DFF /* osd_startY_flags_ff3 */ #( .GRS_EN("TRUE"), @@ -100830,7 +100566,7 @@ module param_manager .CLK (clk), .D (osd_startY_flags_ff2)); // defparam osd_startY_flags_ff3_vname.orig_name = osd_startY_flags_ff3; - // ../../sources/designs/others/param_manager.v:325 + // ../../sources/designs/others/param_manager.v:349 GTP_DFF /* osd_startY_load */ #( .GRS_EN("TRUE"), @@ -100840,139 +100576,164 @@ module param_manager .CLK (clk), .D (N214)); // defparam osd_startY_load_vname.orig_name = osd_startY_load; - // ../../sources/designs/others/param_manager.v:325 + // ../../sources/designs/others/param_manager.v:349 param_cell_unsigned_loop param_filiter1_mode ( .value (filiter1_mode), .load_data ({mem[2], mem[1], mem[0]}), - .\param_manager_inst/selected ({1'bx, 1'bx, selected[11], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), + .N59 (\param_filiter1_mode/N59 ), .N116 (\param_filiter1_mode/N116 ), .N119 (\param_filiter1_mode/N119 ), .N161 (\param_filiter1_mode/N161 ), .changed_down (\param_filiter1_mode/changed_down ), .changed_up (\param_filiter1_mode/changed_up ), - .\param_manager_inst/param_modify_H/N140 (\param_modify_H/N140 ), + .\param_manager_inst/param_modify_S/N153 (\param_modify_S/N153 ), .pluse (\param_filiter1_mode/pluse ), .pressed_down (\param_filiter1_mode/pressed_down ), .pressed_up (\param_filiter1_mode/pressed_up ), .N111 (\param_filiter1_mode/N111 ), .N140 (\param_filiter1_mode/N140 ), + ._N108109 (_N108109), + ._N108110 (_N108110), .akey_down (akey_down), .akey_up (akey_up), .clk (clk), .\key_debounce_inst2/pluse_ms (\key_debounce_key_left/pluse_ms ), .load_valid (filiter1_mode_load), - .\param_manager_inst/param_modify_H/pluse (\param_modify_H/pluse ), + .\param_manager_inst/modify_S_load (modify_S_load), + .\param_manager_inst/param_modify_S/N140 (\param_modify_S/N140 ), .rd2_rst (rd2_rst), .restore (pressed_restore), .selected (selected[0])); - // ../../sources/designs/others/param_manager.v:171 + // ../../sources/designs/others/param_manager.v:195 param_cell_unsigned_loop_unq4 param_filiter2_mode ( .value (filiter2_mode), .load_data ({mem[10], mem[9], mem[8]}), - .\param_manager_inst/selected ({1'bx, selected[12], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), - .\param_manager_inst/param_modify_S/N140 (\param_modify_S/N140 ), + .\param_manager_inst/param_modify_V/N153 (\param_modify_V/N153 ), + .N59 (\param_filiter1_mode/N59 ), .N140 (\param_filiter2_mode/N140 ), + ._N108087 (_N108087), + ._N108088 (_N108088), .changed_down (\param_filiter1_mode/changed_down ), .changed_up (\param_filiter1_mode/changed_up ), .clk (clk), .load_valid (filiter2_mode_load), - .\param_manager_inst/param_modify_H/pluse (\param_modify_H/pluse ), + .\param_manager_inst/modify_V_load (modify_V_load), + .\param_manager_inst/param_modify_V/N140 (\param_modify_V/N140 ), .pluse (\param_filiter1_mode/pluse ), .pressed_down (\param_filiter1_mode/pressed_down ), .pressed_up (\param_filiter1_mode/pressed_up ), .rd2_rst (rd2_rst), .restore (pressed_restore), .selected (selected[1])); - // ../../sources/designs/others/param_manager.v:203 + // ../../sources/designs/others/param_manager.v:227 param_cell_signed_loop param_modify_H ( .value (modify_H), .load_data ({mem[160], mem[159], mem[158], mem[157], mem[156], mem[155], mem[154], mem[153], mem[152]}), + .\param_manager_inst/selected ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, selected[4], 1'bx, 1'bx, 1'bx, 1'bx}), + .param_offsetX ({1'bx, 1'bx, 1'bx, 1'bx, offsetX[7], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), + .param_offsetY ({offsetY[11], offsetY[10], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), .N72 (\param_modify_H/N72 ), + ._N3230 (_N3230), + .\param_manager_inst/param_offsetX/N153 (\param_offsetX/N153 ), + .\param_manager_inst/param_offsetY/N153 (\param_offsetY/N153 ), + .\param_manager_inst/param_osd_startX/N140 (\param_osd_startX/N140 ), .pluse (\param_modify_H/pluse ), .N111 (\param_filiter1_mode/N111 ), .N116 (\param_filiter1_mode/N116 ), .N119 (\param_filiter1_mode/N119 ), .N140 (\param_modify_H/N140 ), + .N153 (\param_modify_H/N153 ), .N160 (\param_filiter1_mode/N161 ), + ._N3669 (_N3669), + ._N3811 (_N3811), + ._N105338 (_N105338), + .changed_down (\param_filiter1_mode/changed_down ), .changed_up (\param_filiter1_mode/changed_up ), .clk (clk), .\key_debounce_inst2/pluse_ms (\key_debounce_key_left/pluse_ms ), .load_valid (modify_H_load), + .\param_manager_inst/offsetX_load (offsetX_load), + .\param_manager_inst/offsetY_load (offsetY_load), + .\param_manager_inst/param_offsetX/N140 (\param_offsetX/N140 ), + .\param_manager_inst/param_offsetY/N140 (\param_offsetY/N140 ), + .\param_manager_inst/param_osd_startX/pluse (\param_osd_startX/pluse ), + .pressed_down (\param_filiter1_mode/pressed_down ), .pressed_up (\param_filiter1_mode/pressed_up ), .rd2_rst (rd2_rst), .restore (pressed_restore), .selected (selected[11])); - // ../../sources/designs/others/param_manager.v:561 + // ../../sources/designs/others/param_manager.v:585 param_cell_signed_2 param_modify_S ( .value (modify_S), .load_data ({mem[176], mem[175], mem[174], mem[173], mem[172], mem[171], mem[170], mem[169], mem[168]}), - .param_offsetX ({1'bx, 1'bx, 1'bx, 1'bx, offsetX[7], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), - .\param_manager_inst/param_modify_V/N153 (\param_modify_V/N153 ), - .\param_manager_inst/param_offsetX/N153 (\param_offsetX/N153 ), - .N72 (\param_modify_H/N72 ), + .\param_manager_inst/selected ({1'bx, 1'bx, 1'bx, 1'bx, selected[9], 1'bx, 1'bx, 1'bx, 1'bx, selected[4], 1'bx, 1'bx, 1'bx, 1'bx}), + .param_modify_H ({modify_H[8], modify_H[7], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), .N140 (\param_modify_S/N140 ), - ._N3647 (_N3647), - ._N104501 (_N104501), - ._N107262 (_N107262), - ._N107263 (_N107263), + ._N108109 (_N108109), + ._N108110 (_N108110), + .\param_manager_inst/param_modify_H/N153 (\param_modify_H/N153 ), + .\param_manager_inst/param_offsetX/N140 (\param_offsetX/N140 ), + .\param_manager_inst/param_osd_startX/N142 (\param_osd_startX/N142 ), + .N72 (\param_modify_H/N72 ), + .N153 (\param_modify_S/N153 ), + ._N3230 (_N3230), .changed_down (\param_filiter1_mode/changed_down ), + .changed_up (\param_filiter1_mode/changed_up ), .clk (clk), .load_valid (modify_S_load), - .\param_manager_inst/modify_V_load (modify_V_load), - .\param_manager_inst/offsetX_load (offsetX_load), - .\param_manager_inst/param_modify_V/N140 (\param_modify_V/N140 ), - .\param_manager_inst/param_offsetX/N140 (\param_offsetX/N140 ), + .\param_manager_inst/modify_H_load (modify_H_load), + .\param_manager_inst/param_modify_H/N140 (\param_modify_H/N140 ), + .\param_manager_inst/param_offsetX/pluse (\param_offsetX/pluse ), + .\param_manager_inst/param_osd_startX/pluse (\param_osd_startX/pluse ), .pluse (\param_modify_H/pluse ), .pressed_down (\param_filiter1_mode/pressed_down ), + .pressed_up (\param_filiter1_mode/pressed_up ), .rd2_rst (rd2_rst), .restore (pressed_restore), .selected (selected[12])); - // ../../sources/designs/others/param_manager.v:598 + // ../../sources/designs/others/param_manager.v:622 param_cell_signed_2_unq4 param_modify_V ( .value (modify_V), .load_data ({mem[192], mem[191], mem[190], mem[189], mem[188], mem[187], mem[186], mem[185], mem[184]}), - .\param_manager_inst/selected ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, selected[1], selected[0]}), - .param_offsetY ({offsetY[11], offsetY[10], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), - ._N107262 (_N107262), - ._N107263 (_N107263), - .\param_manager_inst/param_filiter1_mode/N140 (\param_filiter1_mode/N140 ), - .\param_manager_inst/param_filiter2_mode/N140 (\param_filiter2_mode/N140 ), - .\param_manager_inst/param_offsetY/N153 (\param_offsetY/N153 ), - .N72 (\param_modify_H/N72 ), + .\param_manager_inst/selected ({1'bx, 1'bx, 1'bx, selected[10], 1'bx, 1'bx, 1'bx, 1'bx, selected[5], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), .N140 (\param_modify_V/N140 ), + ._N108087 (_N108087), + ._N108088 (_N108088), + .\param_manager_inst/param_offsetY/N140 (\param_offsetY/N140 ), + .\param_manager_inst/param_osd_startY/N140 (\param_osd_startY/N140 ), + .N72 (\param_modify_H/N72 ), .N153 (\param_modify_V/N153 ), - ._N3793 (_N3793), .changed_down (\param_filiter1_mode/changed_down ), + .changed_up (\param_filiter1_mode/changed_up ), .clk (clk), .load_valid (modify_V_load), - .\param_manager_inst/offsetY_load (offsetY_load), - .\param_manager_inst/param_filiter1_mode/pluse (\param_filiter1_mode/pluse ), - .\param_manager_inst/param_offsetY/N140 (\param_offsetY/N140 ), + .\param_manager_inst/param_offsetX/pluse (\param_offsetX/pluse ), + .\param_manager_inst/param_osd_char_height/pluse (\param_osd_char_height/pluse ), .pluse (\param_modify_H/pluse ), .pressed_down (\param_filiter1_mode/pressed_down ), + .pressed_up (\param_filiter1_mode/pressed_up ), .rd2_rst (rd2_rst), .restore (pressed_restore), .selected (selected[13])); - // ../../sources/designs/others/param_manager.v:635 + // ../../sources/designs/others/param_manager.v:659 param_cell_signed param_offsetX ( .value (offsetX), .load_data ({mem[131], mem[130], mem[129], mem[128], mem[127], mem[126], mem[125], mem[124], mem[123], mem[122], mem[121], mem[120]}), - .\param_manager_inst/selected ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, selected[4], 1'bx, 1'bx, 1'bx, 1'bx}), + .\param_manager_inst/selected ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, selected[6], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), .N72 (\param_offsetX/N72 ), - .N140 (\param_offsetX/N140 ), - ._N3647 (_N3647), - ._N104501 (_N104501), - .\param_manager_inst/param_osd_startX/N140 (\param_osd_startX/N140 ), - .\param_manager_inst/param_osd_startX/N142 (\param_osd_startX/N142 ), + ._N3669 (_N3669), + ._N105338 (_N105338), + .\param_manager_inst/param_osd_char_width/N140 (\param_osd_char_width/N140 ), .pluse (\param_offsetX/pluse ), .N116 (\param_filiter1_mode/N116 ), .N119 (\param_filiter1_mode/N119 ), + .N140 (\param_offsetX/N140 ), .N153 (\param_offsetX/N153 ), .N160 (\param_filiter1_mode/N161 ), .changed_down (\param_filiter1_mode/changed_down ), @@ -100980,38 +100741,37 @@ module param_manager .clk (clk), .\key_debounce_inst2/pluse_ms (\key_debounce_key_left/pluse_ms ), .load_valid (offsetX_load), - .\param_manager_inst/param_osd_startX/pluse (\param_osd_startX/pluse ), + .\param_manager_inst/param_osd_char_height/pluse (\param_osd_char_height/pluse ), .pressed_down (\param_filiter1_mode/pressed_down ), .pressed_up (\param_filiter1_mode/pressed_up ), .rd2_rst (rd2_rst), .restore (pressed_restore), .selected (selected[9])); - // ../../sources/designs/others/param_manager.v:489 + // ../../sources/designs/others/param_manager.v:513 param_cell_signed_1 param_offsetY ( .value (offsetY), .load_data ({mem[147], mem[146], mem[145], mem[144], mem[143], mem[142], mem[141], mem[140], mem[139], mem[138], mem[137], mem[136]}), - .N140 (\param_offsetY/N140 ), - ._N3793 (_N3793), + .\param_manager_inst/selected ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, selected[7], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), + ._N3811 (_N3811), + .\param_manager_inst/param_osd_char_height/N140 (\param_osd_char_height/N140 ), .N72 (\param_offsetX/N72 ), + .N140 (\param_offsetY/N140 ), .N153 (\param_offsetY/N153 ), .changed_down (\param_filiter1_mode/changed_down ), .clk (clk), .load_valid (offsetY_load), - .pluse (\param_offsetX/pluse ), + .\param_manager_inst/param_osd_char_height/pluse (\param_osd_char_height/pluse ), .pressed_down (\param_filiter1_mode/pressed_down ), .rd2_rst (rd2_rst), .restore (pressed_restore), .selected (selected[10])); - // ../../sources/designs/others/param_manager.v:524 + // ../../sources/designs/others/param_manager.v:548 param_cell_unsigned_4 param_osd_char_height ( .value (osd_char_height), .load_data ({mem[98], mem[97], mem[96], mem[95], mem[94], mem[93], mem[92], mem[91], mem[90], mem[89], mem[88]}), - .\param_manager_inst/selected ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, selected[6], selected[5], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), .N72 (\param_osd_char_height/N72 ), - .\param_manager_inst/param_osd_char_width/N140 (\param_osd_char_width/N140 ), - .\param_manager_inst/param_osd_startY/N140 (\param_osd_startY/N140 ), .pluse (\param_osd_char_height/pluse ), .N111 (\param_filiter1_mode/N111 ), .N116 (\param_filiter1_mode/N116 ), @@ -101019,7 +100779,6 @@ module param_manager .N140 (\param_osd_char_height/N140 ), .N142 (\param_osd_char_height/N142 ), .N161 (\param_filiter1_mode/N161 ), - .changed_down (\param_filiter1_mode/changed_down ), .changed_up (\param_filiter1_mode/changed_up ), .clk (clk), .\key_debounce_inst2/pluse_ms (\key_debounce_key_left/pluse_ms ), @@ -101029,25 +100788,24 @@ module param_manager .rd2_rst (rd2_rst), .restore (pressed_restore), .selected (selected[7])); - // ../../sources/designs/others/param_manager.v:417 + // ../../sources/designs/others/param_manager.v:441 param_cell_unsigned_3 param_osd_char_width ( .value (osd_char_width), .load_data ({mem[82], mem[81], mem[80], mem[79], mem[78], mem[77], mem[76], mem[75], mem[74], mem[73], mem[72]}), - .\param_manager_inst/selected ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, selected[7], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), - .\param_manager_inst/param_osd_char_height/N140 (\param_osd_char_height/N140 ), .N72 (\param_osd_char_height/N72 ), .N140 (\param_osd_char_width/N140 ), - .N142 (\param_osd_char_width/N142 ), .changed_down (\param_filiter1_mode/changed_down ), + .changed_up (\param_filiter1_mode/changed_up ), .clk (clk), .load_valid (osd_char_width_load), .pluse (\param_osd_char_height/pluse ), .pressed_down (\param_filiter1_mode/pressed_down ), + .pressed_up (\param_filiter1_mode/pressed_up ), .rd2_rst (rd2_rst), .restore (pressed_restore), .selected (selected[6])); - // ../../sources/designs/others/param_manager.v:380 + // ../../sources/designs/others/param_manager.v:404 param_cell_unsigned_1 param_osd_startX ( .value (osd_startX), @@ -101067,7 +100825,7 @@ module param_manager .rd2_rst (rd2_rst), .restore (pressed_restore), .selected (selected[4])); - // ../../sources/designs/others/param_manager.v:308 + // ../../sources/designs/others/param_manager.v:332 param_cell_unsigned_2 param_osd_startY ( .value (osd_startY), @@ -101079,11 +100837,13 @@ module param_manager .rd2_rst (rd2_rst), .restore (pressed_restore), .selected (selected[5])); - // ../../sources/designs/others/param_manager.v:344 + // ../../sources/designs/others/param_manager.v:368 param_cell_unsigned_loop_1 param_rotate ( .value (rotate), .load_data ({mem[39], mem[38], mem[37], mem[36], mem[35], mem[34], mem[33], mem[32]}), + .\param_manager_inst/selected ({1'bx, 1'bx, selected[11], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), + .\param_manager_inst/param_modify_H/N140 (\param_modify_H/N140 ), .N111 (\param_filiter1_mode/N111 ), .N116 (\param_filiter1_mode/N116 ), .N119 (\param_filiter1_mode/N119 ), @@ -101093,31 +100853,34 @@ module param_manager .clk (clk), .\key_debounce_inst2/pluse_ms (\key_debounce_key_left/pluse_ms ), .load_valid (rotate_load), + .\param_manager_inst/param_modify_H/pluse (\param_modify_H/pluse ), .pressed_down (\param_filiter1_mode/pressed_down ), .pressed_up (\param_filiter1_mode/pressed_up ), .rd2_rst (rd2_rst), .restore (pressed_restore), .selected (selected[3])); - // ../../sources/designs/others/param_manager.v:271 + // ../../sources/designs/others/param_manager.v:295 param_cell_unsigned param_rotate_A ( .value (rotate_A), .load_data ({mem[113], mem[112], mem[111], mem[110], mem[109], mem[108], mem[107], mem[106], mem[105], mem[104]}), - .\param_manager_inst/selected ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, selected[7], selected[6], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), + .\param_manager_inst/selected ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, selected[7], 1'bx, 1'bx, 1'bx, 1'bx, selected[2], 1'bx, 1'bx}), .\param_manager_inst/param_osd_char_height/N142 (\param_osd_char_height/N142 ), - .\param_manager_inst/param_osd_char_width/N142 (\param_osd_char_width/N142 ), + .\param_manager_inst/param_zoom/N140 (\param_zoom/N140 ), .N72 (\param_modify_H/N72 ), .N140 (\param_rotate_A/N140 ), - .N142 (\param_rotate_A/N142 ), + .changed_down (\param_filiter1_mode/changed_down ), .changed_up (\param_filiter1_mode/changed_up ), .clk (clk), .load_valid (rotate_A_load), .\param_manager_inst/param_osd_char_height/pluse (\param_osd_char_height/pluse ), + .pluse (\param_modify_H/pluse ), + .pressed_down (\param_filiter1_mode/pressed_down ), .pressed_up (\param_filiter1_mode/pressed_up ), .rd2_rst (rd2_rst), .restore (pressed_restore), .selected (selected[8])); - // ../../sources/designs/others/param_manager.v:453 + // ../../sources/designs/others/param_manager.v:477 param_cell_unsigned_unq4 param_zoom ( .value (zoom), @@ -101125,16 +100888,18 @@ module param_manager .\param_manager_inst/selected ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, selected[8], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), .\param_manager_inst/param_rotate_A/N140 (\param_rotate_A/N140 ), .N72 (\param_modify_H/N72 ), - .N142 (\param_zoom/N142 ), + .N140 (\param_zoom/N140 ), .changed_down (\param_filiter1_mode/changed_down ), + .changed_up (\param_filiter1_mode/changed_up ), .clk (clk), .load_valid (zoom_load), .pluse (\param_modify_H/pluse ), .pressed_down (\param_filiter1_mode/pressed_down ), + .pressed_up (\param_filiter1_mode/pressed_up ), .rd2_rst (rd2_rst), .restore (pressed_restore), .selected (selected[2])); - // ../../sources/designs/others/param_manager.v:238 + // ../../sources/designs/others/param_manager.v:262 GTP_DFF /* rotate_A_flags_ff0 */ #( .GRS_EN("TRUE"), @@ -101144,7 +100909,7 @@ module param_manager .CLK (clk), .D (mem_flags[13])); // defparam rotate_A_flags_ff0_vname.orig_name = rotate_A_flags_ff0; - // ../../sources/designs/others/param_manager.v:434 + // ../../sources/designs/others/param_manager.v:458 GTP_DFF /* rotate_A_flags_ff1 */ #( .GRS_EN("TRUE"), @@ -101154,7 +100919,7 @@ module param_manager .CLK (clk), .D (rotate_A_flags_ff0)); // defparam rotate_A_flags_ff1_vname.orig_name = rotate_A_flags_ff1; - // ../../sources/designs/others/param_manager.v:434 + // ../../sources/designs/others/param_manager.v:458 GTP_DFF /* rotate_A_flags_ff2 */ #( .GRS_EN("TRUE"), @@ -101164,7 +100929,7 @@ module param_manager .CLK (clk), .D (mem_flags[14])); // defparam rotate_A_flags_ff2_vname.orig_name = rotate_A_flags_ff2; - // ../../sources/designs/others/param_manager.v:434 + // ../../sources/designs/others/param_manager.v:458 GTP_DFF /* rotate_A_flags_ff3 */ #( .GRS_EN("TRUE"), @@ -101174,7 +100939,7 @@ module param_manager .CLK (clk), .D (rotate_A_flags_ff2)); // defparam rotate_A_flags_ff3_vname.orig_name = rotate_A_flags_ff3; - // ../../sources/designs/others/param_manager.v:434 + // ../../sources/designs/others/param_manager.v:458 GTP_DFF /* rotate_A_load */ #( .GRS_EN("TRUE"), @@ -101184,7 +100949,7 @@ module param_manager .CLK (clk), .D (N241)); // defparam rotate_A_load_vname.orig_name = rotate_A_load; - // ../../sources/designs/others/param_manager.v:434 + // ../../sources/designs/others/param_manager.v:458 GTP_DFF /* rotate_flags_ff0 */ #( .GRS_EN("TRUE"), @@ -101194,7 +100959,7 @@ module param_manager .CLK (clk), .D (mem_flags[4])); // defparam rotate_flags_ff0_vname.orig_name = rotate_flags_ff0; - // ../../sources/designs/others/param_manager.v:255 + // ../../sources/designs/others/param_manager.v:279 GTP_DFF /* rotate_flags_ff1 */ #( .GRS_EN("TRUE"), @@ -101204,7 +100969,7 @@ module param_manager .CLK (clk), .D (rotate_flags_ff0)); // defparam rotate_flags_ff1_vname.orig_name = rotate_flags_ff1; - // ../../sources/designs/others/param_manager.v:255 + // ../../sources/designs/others/param_manager.v:279 GTP_DFF /* rotate_load */ #( .GRS_EN("TRUE"), @@ -101212,9 +100977,9 @@ module param_manager rotate_load_vname ( .Q (rotate_load), .CLK (clk), - .D (_N2805)); + .D (_N2801)); // defparam rotate_load_vname.orig_name = rotate_load; - // ../../sources/designs/others/param_manager.v:255 + // ../../sources/designs/others/param_manager.v:279 GTP_DFF_R /* \selected[0] */ #( .GRS_EN("TRUE"), @@ -101224,7 +100989,7 @@ module param_manager .CLK (clk), .D (N319), .R (rd2_rst)); - // ../../sources/designs/others/param_manager.v:136 + // ../../sources/designs/others/param_manager.v:160 GTP_DFF_R /* \selected[1] */ #( .GRS_EN("TRUE"), @@ -101234,7 +100999,7 @@ module param_manager .CLK (clk), .D (N321), .R (rd2_rst)); - // ../../sources/designs/others/param_manager.v:136 + // ../../sources/designs/others/param_manager.v:160 GTP_DFF_R /* \selected[2] */ #( .GRS_EN("TRUE"), @@ -101244,7 +101009,7 @@ module param_manager .CLK (clk), .D (N322), .R (rd2_rst)); - // ../../sources/designs/others/param_manager.v:136 + // ../../sources/designs/others/param_manager.v:160 GTP_DFF_R /* \selected[3] */ #( .GRS_EN("TRUE"), @@ -101254,7 +101019,7 @@ module param_manager .CLK (clk), .D (N323), .R (rd2_rst)); - // ../../sources/designs/others/param_manager.v:136 + // ../../sources/designs/others/param_manager.v:160 GTP_DFF_R /* \selected[4] */ #( .GRS_EN("TRUE"), @@ -101264,7 +101029,7 @@ module param_manager .CLK (clk), .D (N324), .R (rd2_rst)); - // ../../sources/designs/others/param_manager.v:136 + // ../../sources/designs/others/param_manager.v:160 GTP_DFF_R /* \selected[5] */ #( .GRS_EN("TRUE"), @@ -101274,7 +101039,7 @@ module param_manager .CLK (clk), .D (N325), .R (rd2_rst)); - // ../../sources/designs/others/param_manager.v:136 + // ../../sources/designs/others/param_manager.v:160 GTP_DFF_R /* \selected[6] */ #( .GRS_EN("TRUE"), @@ -101284,7 +101049,7 @@ module param_manager .CLK (clk), .D (N326), .R (rd2_rst)); - // ../../sources/designs/others/param_manager.v:136 + // ../../sources/designs/others/param_manager.v:160 GTP_DFF_R /* \selected[7] */ #( .GRS_EN("TRUE"), @@ -101294,7 +101059,7 @@ module param_manager .CLK (clk), .D (N327), .R (rd2_rst)); - // ../../sources/designs/others/param_manager.v:136 + // ../../sources/designs/others/param_manager.v:160 GTP_DFF_R /* \selected[8] */ #( .GRS_EN("TRUE"), @@ -101304,7 +101069,7 @@ module param_manager .CLK (clk), .D (N328), .R (rd2_rst)); - // ../../sources/designs/others/param_manager.v:136 + // ../../sources/designs/others/param_manager.v:160 GTP_DFF_R /* \selected[9] */ #( .GRS_EN("TRUE"), @@ -101314,7 +101079,7 @@ module param_manager .CLK (clk), .D (N329), .R (rd2_rst)); - // ../../sources/designs/others/param_manager.v:136 + // ../../sources/designs/others/param_manager.v:160 GTP_DFF_R /* \selected[10] */ #( .GRS_EN("TRUE"), @@ -101324,7 +101089,7 @@ module param_manager .CLK (clk), .D (N330), .R (rd2_rst)); - // ../../sources/designs/others/param_manager.v:136 + // ../../sources/designs/others/param_manager.v:160 GTP_DFF_R /* \selected[11] */ #( .GRS_EN("TRUE"), @@ -101334,7 +101099,7 @@ module param_manager .CLK (clk), .D (N331), .R (rd2_rst)); - // ../../sources/designs/others/param_manager.v:136 + // ../../sources/designs/others/param_manager.v:160 GTP_DFF_R /* \selected[12] */ #( .GRS_EN("TRUE"), @@ -101344,7 +101109,7 @@ module param_manager .CLK (clk), .D (N332), .R (rd2_rst)); - // ../../sources/designs/others/param_manager.v:136 + // ../../sources/designs/others/param_manager.v:160 GTP_DFF_R /* \selected[13] */ #( .GRS_EN("TRUE"), @@ -101354,7 +101119,7 @@ module param_manager .CLK (clk), .D (N333), .R (rd2_rst)); - // ../../sources/designs/others/param_manager.v:136 + // ../../sources/designs/others/param_manager.v:160 GTP_DFF /* zoom_flags_ff0 */ #( .GRS_EN("TRUE"), @@ -101364,7 +101129,7 @@ module param_manager .CLK (clk), .D (mem_flags[2])); // defparam zoom_flags_ff0_vname.orig_name = zoom_flags_ff0; - // ../../sources/designs/others/param_manager.v:220 + // ../../sources/designs/others/param_manager.v:244 GTP_DFF /* zoom_flags_ff1 */ #( .GRS_EN("TRUE"), @@ -101374,7 +101139,7 @@ module param_manager .CLK (clk), .D (zoom_flags_ff0)); // defparam zoom_flags_ff1_vname.orig_name = zoom_flags_ff1; - // ../../sources/designs/others/param_manager.v:220 + // ../../sources/designs/others/param_manager.v:244 GTP_DFF /* zoom_flags_ff2 */ #( .GRS_EN("TRUE"), @@ -101384,7 +101149,7 @@ module param_manager .CLK (clk), .D (mem_flags[3])); // defparam zoom_flags_ff2_vname.orig_name = zoom_flags_ff2; - // ../../sources/designs/others/param_manager.v:220 + // ../../sources/designs/others/param_manager.v:244 GTP_DFF /* zoom_flags_ff3 */ #( .GRS_EN("TRUE"), @@ -101394,7 +101159,7 @@ module param_manager .CLK (clk), .D (zoom_flags_ff2)); // defparam zoom_flags_ff3_vname.orig_name = zoom_flags_ff3; - // ../../sources/designs/others/param_manager.v:220 + // ../../sources/designs/others/param_manager.v:244 GTP_DFF /* zoom_load */ #( .GRS_EN("TRUE"), @@ -101404,7 +101169,7 @@ module param_manager .CLK (clk), .D (N192)); // defparam zoom_load_vname.orig_name = zoom_load; - // ../../sources/designs/others/param_manager.v:220 + // ../../sources/designs/others/param_manager.v:244 endmodule @@ -102036,6 +101801,13 @@ module ipsxb_ddrphy_init_v1_0 wire _N28; wire _N30; wire _N31; + wire _N14235; + wire _N14236; + wire _N14237; + wire _N14238; + wire _N14239; + wire _N14240; + wire _N14241; wire _N14242; wire _N14243; wire _N14244; @@ -102043,15 +101815,20 @@ module ipsxb_ddrphy_init_v1_0 wire _N14246; wire _N14247; wire _N14248; - wire _N14249; - wire _N14250; - wire _N14251; - wire _N14252; - wire _N14253; - wire _N14254; - wire _N14255; - wire _N14271; - wire _N14272; + wire _N14257; + wire _N14258; + wire _N14259; + wire _N14260; + wire _N14261; + wire _N14262; + wire _N14263; + wire _N14264; + wire _N14265; + wire _N14266; + wire _N14267; + wire _N14268; + wire _N14269; + wire _N14270; wire _N14273; wire _N14274; wire _N14275; @@ -102060,40 +101837,28 @@ module ipsxb_ddrphy_init_v1_0 wire _N14278; wire _N14279; wire _N14280; - wire _N14281; - wire _N14282; - wire _N14283; - wire _N14284; - wire _N14287; - wire _N14288; - wire _N14289; - wire _N14290; - wire _N14291; - wire _N14292; - wire _N14293; - wire _N14294; - wire _N16307; - wire _N16308; - wire _N16309; - wire _N16310; - wire _N16311; - wire _N16312; + wire _N17001; + wire _N17002; + wire _N17003; + wire _N17004; + wire _N17005; + wire _N17006; wire _N18071_inv; - wire _N19653; - wire _N19654; - wire _N19655; - wire _N19656; - wire _N19657; - wire _N19658; - wire _N19659; - wire _N19660; - wire _N19661; - wire _N19662; - wire _N19663; - wire _N19664; - wire _N19665; - wire _N19666; - wire _N19667; + wire _N19600; + wire _N19601; + wire _N19602; + wire _N19603; + wire _N19604; + wire _N19605; + wire _N19606; + wire _N19607; + wire _N19608; + wire _N19609; + wire _N19610; + wire _N19611; + wire _N19612; + wire _N19613; + wire _N19614; wire _N27699; wire _N27704; wire _N27705; @@ -102103,24 +101868,24 @@ module ipsxb_ddrphy_init_v1_0 wire _N27715; wire _N27717; wire _N27719; - wire _N41672; - wire _N41712; - wire _N41775; - wire _N81834; - wire _N97036; - wire _N103327; - wire _N103328; - wire _N103565; - wire _N103569; - wire _N103573; - wire _N103576; - wire _N103595; - wire _N103599; - wire _N103603; - wire _N103606; - wire _N103614; - wire _N103626; - wire _N103627; + wire _N39531; + wire _N39567; + wire _N39627; + wire _N82622; + wire _N97805; + wire _N104139; + wire _N104140; + wire _N104377; + wire _N104381; + wire _N104385; + wire _N104388; + wire _N104407; + wire _N104411; + wire _N104415; + wire _N104418; + wire _N104426; + wire _N104438; + wire _N104439; wire cnt_cke_pass; wire [7:0] cnt_cmd; wire cnt_pwron_pass; @@ -102143,7 +101908,7 @@ module ipsxb_ddrphy_init_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3_1_1 ( - .COUT (_N14242), + .COUT (_N14235), .Z (N268[1]), .CIN (), .I0 (cnt_t200us[0]), @@ -102163,9 +101928,9 @@ module ipsxb_ddrphy_init_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3_1_2 ( - .COUT (_N14243), + .COUT (_N14236), .Z (N268[2]), - .CIN (_N14242), + .CIN (_N14235), .I0 (cnt_t200us[0]), .I1 (cnt_t200us[1]), .I2 (init_start), @@ -102183,9 +101948,9 @@ module ipsxb_ddrphy_init_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3_1_3 ( - .COUT (_N14244), + .COUT (_N14237), .Z (N268[3]), - .CIN (_N14243), + .CIN (_N14236), .I0 (), .I1 (cnt_t200us[3]), .I2 (init_start), @@ -102203,9 +101968,9 @@ module ipsxb_ddrphy_init_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3_1_4 ( - .COUT (_N14245), + .COUT (_N14238), .Z (N268[4]), - .CIN (_N14244), + .CIN (_N14237), .I0 (), .I1 (cnt_t200us[4]), .I2 (init_start), @@ -102223,9 +101988,9 @@ module ipsxb_ddrphy_init_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3_1_5 ( - .COUT (_N14246), + .COUT (_N14239), .Z (N268[5]), - .CIN (_N14245), + .CIN (_N14238), .I0 (), .I1 (cnt_t200us[5]), .I2 (init_start), @@ -102243,9 +102008,9 @@ module ipsxb_ddrphy_init_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3_1_6 ( - .COUT (_N14247), + .COUT (_N14240), .Z (N268[6]), - .CIN (_N14246), + .CIN (_N14239), .I0 (), .I1 (cnt_t200us[6]), .I2 (init_start), @@ -102263,9 +102028,9 @@ module ipsxb_ddrphy_init_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3_1_7 ( - .COUT (_N14248), + .COUT (_N14241), .Z (N268[7]), - .CIN (_N14247), + .CIN (_N14240), .I0 (), .I1 (cnt_t200us[7]), .I2 (init_start), @@ -102283,9 +102048,9 @@ module ipsxb_ddrphy_init_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3_1_8 ( - .COUT (_N14249), + .COUT (_N14242), .Z (N268[8]), - .CIN (_N14248), + .CIN (_N14241), .I0 (), .I1 (cnt_t200us[8]), .I2 (init_start), @@ -102303,9 +102068,9 @@ module ipsxb_ddrphy_init_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3_1_9 ( - .COUT (_N14250), + .COUT (_N14243), .Z (N268[9]), - .CIN (_N14249), + .CIN (_N14242), .I0 (), .I1 (cnt_t200us[9]), .I2 (init_start), @@ -102323,9 +102088,9 @@ module ipsxb_ddrphy_init_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3_1_10 ( - .COUT (_N14251), + .COUT (_N14244), .Z (N268[10]), - .CIN (_N14250), + .CIN (_N14243), .I0 (), .I1 (cnt_t200us[10]), .I2 (init_start), @@ -102343,9 +102108,9 @@ module ipsxb_ddrphy_init_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3_1_11 ( - .COUT (_N14252), + .COUT (_N14245), .Z (N268[11]), - .CIN (_N14251), + .CIN (_N14244), .I0 (), .I1 (cnt_t200us[11]), .I2 (init_start), @@ -102363,9 +102128,9 @@ module ipsxb_ddrphy_init_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3_1_12 ( - .COUT (_N14253), + .COUT (_N14246), .Z (N268[12]), - .CIN (_N14252), + .CIN (_N14245), .I0 (), .I1 (cnt_t200us[12]), .I2 (init_start), @@ -102383,9 +102148,9 @@ module ipsxb_ddrphy_init_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3_1_13 ( - .COUT (_N14254), + .COUT (_N14247), .Z (N268[13]), - .CIN (_N14253), + .CIN (_N14246), .I0 (), .I1 (cnt_t200us[13]), .I2 (init_start), @@ -102403,9 +102168,9 @@ module ipsxb_ddrphy_init_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3_1_14 ( - .COUT (_N14255), + .COUT (_N14248), .Z (N268[14]), - .CIN (_N14254), + .CIN (_N14247), .I0 (), .I1 (cnt_t200us[14]), .I2 (init_start), @@ -102425,7 +102190,7 @@ module ipsxb_ddrphy_init_v1_0 N3_1_15 ( .COUT (), .Z (N268[15]), - .CIN (_N14255), + .CIN (_N14248), .I0 (), .I1 (cnt_t200us[15]), .I2 (init_start), @@ -102453,7 +102218,7 @@ module ipsxb_ddrphy_init_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N23_1_1 ( - .COUT (_N14271), + .COUT (_N14257), .Z (N275[1]), .CIN (), .I0 (cnt_t500us[0]), @@ -102473,9 +102238,9 @@ module ipsxb_ddrphy_init_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N23_1_2 ( - .COUT (_N14272), + .COUT (_N14258), .Z (N275[2]), - .CIN (_N14271), + .CIN (_N14257), .I0 (cnt_t500us[0]), .I1 (cnt_t500us[1]), .I2 (init_state_reg[0]), @@ -102493,9 +102258,9 @@ module ipsxb_ddrphy_init_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N23_1_3 ( - .COUT (_N14273), + .COUT (_N14259), .Z (N275[3]), - .CIN (_N14272), + .CIN (_N14258), .I0 (), .I1 (cnt_t500us[3]), .I2 (init_state_reg[0]), @@ -102513,9 +102278,9 @@ module ipsxb_ddrphy_init_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N23_1_4 ( - .COUT (_N14274), + .COUT (_N14260), .Z (N275[4]), - .CIN (_N14273), + .CIN (_N14259), .I0 (), .I1 (cnt_t500us[4]), .I2 (init_state_reg[0]), @@ -102533,9 +102298,9 @@ module ipsxb_ddrphy_init_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N23_1_5 ( - .COUT (_N14275), + .COUT (_N14261), .Z (N275[5]), - .CIN (_N14274), + .CIN (_N14260), .I0 (), .I1 (cnt_t500us[5]), .I2 (init_state_reg[0]), @@ -102553,9 +102318,9 @@ module ipsxb_ddrphy_init_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N23_1_6 ( - .COUT (_N14276), + .COUT (_N14262), .Z (N275[6]), - .CIN (_N14275), + .CIN (_N14261), .I0 (), .I1 (cnt_t500us[6]), .I2 (init_state_reg[0]), @@ -102573,9 +102338,9 @@ module ipsxb_ddrphy_init_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N23_1_7 ( - .COUT (_N14277), + .COUT (_N14263), .Z (N275[7]), - .CIN (_N14276), + .CIN (_N14262), .I0 (), .I1 (cnt_t500us[7]), .I2 (init_state_reg[0]), @@ -102593,9 +102358,9 @@ module ipsxb_ddrphy_init_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N23_1_8 ( - .COUT (_N14278), + .COUT (_N14264), .Z (N275[8]), - .CIN (_N14277), + .CIN (_N14263), .I0 (), .I1 (cnt_t500us[8]), .I2 (init_state_reg[0]), @@ -102613,9 +102378,9 @@ module ipsxb_ddrphy_init_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N23_1_9 ( - .COUT (_N14279), + .COUT (_N14265), .Z (N275[9]), - .CIN (_N14278), + .CIN (_N14264), .I0 (), .I1 (cnt_t500us[9]), .I2 (init_state_reg[0]), @@ -102633,9 +102398,9 @@ module ipsxb_ddrphy_init_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N23_1_10 ( - .COUT (_N14280), + .COUT (_N14266), .Z (N275[10]), - .CIN (_N14279), + .CIN (_N14265), .I0 (), .I1 (cnt_t500us[10]), .I2 (init_state_reg[0]), @@ -102653,9 +102418,9 @@ module ipsxb_ddrphy_init_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N23_1_11 ( - .COUT (_N14281), + .COUT (_N14267), .Z (N275[11]), - .CIN (_N14280), + .CIN (_N14266), .I0 (), .I1 (cnt_t500us[11]), .I2 (init_state_reg[0]), @@ -102673,9 +102438,9 @@ module ipsxb_ddrphy_init_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N23_1_12 ( - .COUT (_N14282), + .COUT (_N14268), .Z (N275[12]), - .CIN (_N14281), + .CIN (_N14267), .I0 (), .I1 (cnt_t500us[12]), .I2 (init_state_reg[0]), @@ -102693,9 +102458,9 @@ module ipsxb_ddrphy_init_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N23_1_13 ( - .COUT (_N14283), + .COUT (_N14269), .Z (N275[13]), - .CIN (_N14282), + .CIN (_N14268), .I0 (), .I1 (cnt_t500us[13]), .I2 (init_state_reg[0]), @@ -102713,9 +102478,9 @@ module ipsxb_ddrphy_init_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N23_1_14 ( - .COUT (_N14284), + .COUT (_N14270), .Z (N275[14]), - .CIN (_N14283), + .CIN (_N14269), .I0 (), .I1 (cnt_t500us[14]), .I2 (init_state_reg[0]), @@ -102735,7 +102500,7 @@ module ipsxb_ddrphy_init_v1_0 N23_1_15 ( .COUT (), .Z (N275[15]), - .CIN (_N14284), + .CIN (_N14270), .I0 (), .I1 (cnt_t500us[15]), .I2 (init_state_reg[0]), @@ -102753,7 +102518,7 @@ module ipsxb_ddrphy_init_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N41_1_1 ( - .COUT (_N16307), + .COUT (_N17001), .Z (N282[1]), .CIN (), .I0 (cnt_cmd[0]), @@ -102773,9 +102538,9 @@ module ipsxb_ddrphy_init_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N41_1_2 ( - .COUT (_N16308), + .COUT (_N17002), .Z (N282[2]), - .CIN (_N16307), + .CIN (_N17001), .I0 (cnt_cmd[0]), .I1 (cnt_cmd[1]), .I2 (_N18071_inv), @@ -102793,9 +102558,9 @@ module ipsxb_ddrphy_init_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N41_1_3 ( - .COUT (_N16309), + .COUT (_N17003), .Z (N282[3]), - .CIN (_N16308), + .CIN (_N17002), .I0 (), .I1 (cnt_cmd[3]), .I2 (_N18071_inv), @@ -102813,9 +102578,9 @@ module ipsxb_ddrphy_init_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N41_1_4 ( - .COUT (_N16310), + .COUT (_N17004), .Z (N282[4]), - .CIN (_N16309), + .CIN (_N17003), .I0 (), .I1 (cnt_cmd[4]), .I2 (_N18071_inv), @@ -102833,9 +102598,9 @@ module ipsxb_ddrphy_init_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N41_1_5 ( - .COUT (_N16311), + .COUT (_N17005), .Z (N282[5]), - .CIN (_N16310), + .CIN (_N17004), .I0 (), .I1 (cnt_cmd[5]), .I2 (_N18071_inv), @@ -102853,9 +102618,9 @@ module ipsxb_ddrphy_init_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N41_1_6 ( - .COUT (_N16312), + .COUT (_N17006), .Z (N282[6]), - .CIN (_N16311), + .CIN (_N17005), .I0 (), .I1 (cnt_cmd[6]), .I2 (_N18071_inv), @@ -102875,7 +102640,7 @@ module ipsxb_ddrphy_init_v1_0 N41_1_7 ( .COUT (), .Z (N282[7]), - .CIN (_N16312), + .CIN (_N17006), .I0 (), .I1 (cnt_cmd[7]), .I2 (_N18071_inv), @@ -102893,7 +102658,7 @@ module ipsxb_ddrphy_init_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N79_1_1 ( - .COUT (_N14287), + .COUT (_N14273), .Z (N290[1]), .CIN (), .I0 (cnt_tzqinit[0]), @@ -102913,9 +102678,9 @@ module ipsxb_ddrphy_init_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N79_1_2 ( - .COUT (_N14288), + .COUT (_N14274), .Z (N290[2]), - .CIN (_N14287), + .CIN (_N14273), .I0 (cnt_tzqinit[0]), .I1 (cnt_tzqinit[1]), .I2 (N235), @@ -102933,9 +102698,9 @@ module ipsxb_ddrphy_init_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N79_1_3 ( - .COUT (_N14289), + .COUT (_N14275), .Z (N290[3]), - .CIN (_N14288), + .CIN (_N14274), .I0 (), .I1 (cnt_tzqinit[3]), .I2 (N235), @@ -102953,9 +102718,9 @@ module ipsxb_ddrphy_init_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N79_1_4 ( - .COUT (_N14290), + .COUT (_N14276), .Z (N290[4]), - .CIN (_N14289), + .CIN (_N14275), .I0 (), .I1 (cnt_tzqinit[4]), .I2 (N235), @@ -102973,9 +102738,9 @@ module ipsxb_ddrphy_init_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N79_1_5 ( - .COUT (_N14291), + .COUT (_N14277), .Z (N290[5]), - .CIN (_N14290), + .CIN (_N14276), .I0 (), .I1 (cnt_tzqinit[5]), .I2 (N235), @@ -102993,9 +102758,9 @@ module ipsxb_ddrphy_init_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N79_1_6 ( - .COUT (_N14292), + .COUT (_N14278), .Z (N290[6]), - .CIN (_N14291), + .CIN (_N14277), .I0 (), .I1 (cnt_tzqinit[6]), .I2 (N235), @@ -103013,9 +102778,9 @@ module ipsxb_ddrphy_init_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N79_1_7 ( - .COUT (_N14293), + .COUT (_N14279), .Z (N290[7]), - .CIN (_N14292), + .CIN (_N14278), .I0 (), .I1 (cnt_tzqinit[7]), .I2 (N235), @@ -103033,9 +102798,9 @@ module ipsxb_ddrphy_init_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N79_1_8 ( - .COUT (_N14294), + .COUT (_N14280), .Z (N290[8]), - .CIN (_N14293), + .CIN (_N14279), .I0 (), .I1 (cnt_tzqinit[8]), .I2 (N235), @@ -103055,7 +102820,7 @@ module ipsxb_ddrphy_init_v1_0 N79_1_9 ( .COUT (), .Z (N290[9]), - .CIN (_N14294), + .CIN (_N14280), .I0 (), .I1 (cnt_tzqinit[9]), .I2 (N235), @@ -103106,7 +102871,7 @@ module ipsxb_ddrphy_init_v1_0 GTP_LUT5M /* \N175_8[0] */ #( .INIT(32'b10101010110011001010101011110000)) \N175_8[0] ( - .Z (_N19653), + .Z (_N19600), .I0 (mr0_ddr3[0]), .I1 (mr3_ddr3[0]), .I2 (mr2_ddr3[0]), @@ -103118,7 +102883,7 @@ module ipsxb_ddrphy_init_v1_0 GTP_LUT5M /* \N175_8[1] */ #( .INIT(32'b10101010110011001010101011110000)) \N175_8[1] ( - .Z (_N19654), + .Z (_N19601), .I0 (mr0_ddr3[1]), .I1 (mr3_ddr3[1]), .I2 (mr2_ddr3[1]), @@ -103130,7 +102895,7 @@ module ipsxb_ddrphy_init_v1_0 GTP_LUT5M /* \N175_8[2] */ #( .INIT(32'b10101010110011001010101011110000)) \N175_8[2] ( - .Z (_N19655), + .Z (_N19602), .I0 (mr0_ddr3[2]), .I1 (mr3_ddr3[2]), .I2 (mr2_ddr3[2]), @@ -103142,7 +102907,7 @@ module ipsxb_ddrphy_init_v1_0 GTP_LUT5M /* \N175_8[3] */ #( .INIT(32'b10101010110011001010101011110000)) \N175_8[3] ( - .Z (_N19656), + .Z (_N19603), .I0 (mr0_ddr3[3]), .I1 (mr3_ddr3[3]), .I2 (mr2_ddr3[3]), @@ -103154,7 +102919,7 @@ module ipsxb_ddrphy_init_v1_0 GTP_LUT5M /* \N175_8[4] */ #( .INIT(32'b10101010110011001010101011110000)) \N175_8[4] ( - .Z (_N19657), + .Z (_N19604), .I0 (mr0_ddr3[4]), .I1 (mr3_ddr3[4]), .I2 (mr2_ddr3[4]), @@ -103166,7 +102931,7 @@ module ipsxb_ddrphy_init_v1_0 GTP_LUT5M /* \N175_8[5] */ #( .INIT(32'b10101010110011001010101011110000)) \N175_8[5] ( - .Z (_N19658), + .Z (_N19605), .I0 (mr0_ddr3[5]), .I1 (mr3_ddr3[5]), .I2 (mr2_ddr3[5]), @@ -103178,7 +102943,7 @@ module ipsxb_ddrphy_init_v1_0 GTP_LUT5M /* \N175_8[6] */ #( .INIT(32'b10101010110011001010101011110000)) \N175_8[6] ( - .Z (_N19659), + .Z (_N19606), .I0 (mr0_ddr3[6]), .I1 (mr3_ddr3[6]), .I2 (mr2_ddr3[6]), @@ -103190,7 +102955,7 @@ module ipsxb_ddrphy_init_v1_0 GTP_LUT5M /* \N175_8[7] */ #( .INIT(32'b10101010110011001010101011110000)) \N175_8[7] ( - .Z (_N19660), + .Z (_N19607), .I0 (mr0_ddr3[7]), .I1 (mr3_ddr3[7]), .I2 (mr2_ddr3[7]), @@ -103202,7 +102967,7 @@ module ipsxb_ddrphy_init_v1_0 GTP_LUT5M /* \N175_8[8] */ #( .INIT(32'b10101010110011001010101011110000)) \N175_8[8] ( - .Z (_N19661), + .Z (_N19608), .I0 (mr0_ddr3[8]), .I1 (mr3_ddr3[8]), .I2 (mr2_ddr3[8]), @@ -103214,7 +102979,7 @@ module ipsxb_ddrphy_init_v1_0 GTP_LUT5M /* \N175_8[9] */ #( .INIT(32'b10101010110011001010101011110000)) \N175_8[9] ( - .Z (_N19662), + .Z (_N19609), .I0 (mr0_ddr3[9]), .I1 (mr3_ddr3[9]), .I2 (mr2_ddr3[9]), @@ -103226,7 +102991,7 @@ module ipsxb_ddrphy_init_v1_0 GTP_LUT5M /* \N175_8[10] */ #( .INIT(32'b10101010110011001010101011110000)) \N175_8[10] ( - .Z (_N19663), + .Z (_N19610), .I0 (mr0_ddr3[10]), .I1 (mr3_ddr3[10]), .I2 (mr2_ddr3[10]), @@ -103238,7 +103003,7 @@ module ipsxb_ddrphy_init_v1_0 GTP_LUT5M /* \N175_8[11] */ #( .INIT(32'b10101010110011001010101011110000)) \N175_8[11] ( - .Z (_N19664), + .Z (_N19611), .I0 (mr0_ddr3[11]), .I1 (mr3_ddr3[11]), .I2 (mr2_ddr3[11]), @@ -103250,7 +103015,7 @@ module ipsxb_ddrphy_init_v1_0 GTP_LUT5M /* \N175_8[12] */ #( .INIT(32'b10101010110011001010101011110000)) \N175_8[12] ( - .Z (_N19665), + .Z (_N19612), .I0 (mr0_ddr3[12]), .I1 (mr3_ddr3[12]), .I2 (mr2_ddr3[12]), @@ -103262,7 +103027,7 @@ module ipsxb_ddrphy_init_v1_0 GTP_LUT5M /* \N175_8[13] */ #( .INIT(32'b10101010110011001010101011110000)) \N175_8[13] ( - .Z (_N19666), + .Z (_N19613), .I0 (mr0_ddr3[13]), .I1 (mr3_ddr3[13]), .I2 (mr2_ddr3[13]), @@ -103274,7 +103039,7 @@ module ipsxb_ddrphy_init_v1_0 GTP_LUT5M /* \N175_8[14] */ #( .INIT(32'b10101010110011001010101011110000)) \N175_8[14] ( - .Z (_N19667), + .Z (_N19614), .I0 (mr0_ddr3[14]), .I1 (mr3_ddr3[14]), .I2 (mr2_ddr3[14]), @@ -103288,7 +103053,7 @@ module ipsxb_ddrphy_init_v1_0 \N175_9[0] ( .Z (N175[0]), .I0 (N233), - .I1 (_N19653)); + .I1 (_N19600)); // LUT = I0&I1 ; GTP_LUT2 /* \N175_9[1] */ #( @@ -103296,7 +103061,7 @@ module ipsxb_ddrphy_init_v1_0 \N175_9[1] ( .Z (N175[1]), .I0 (N233), - .I1 (_N19654)); + .I1 (_N19601)); // LUT = I0&I1 ; GTP_LUT2 /* \N175_9[2] */ #( @@ -103304,7 +103069,7 @@ module ipsxb_ddrphy_init_v1_0 \N175_9[2] ( .Z (N175[2]), .I0 (N233), - .I1 (_N19655)); + .I1 (_N19602)); // LUT = I0&I1 ; GTP_LUT2 /* \N175_9[3] */ #( @@ -103312,7 +103077,7 @@ module ipsxb_ddrphy_init_v1_0 \N175_9[3] ( .Z (N175[3]), .I0 (N233), - .I1 (_N19656)); + .I1 (_N19603)); // LUT = I0&I1 ; GTP_LUT2 /* \N175_9[4] */ #( @@ -103320,7 +103085,7 @@ module ipsxb_ddrphy_init_v1_0 \N175_9[4] ( .Z (N175[4]), .I0 (N233), - .I1 (_N19657)); + .I1 (_N19604)); // LUT = I0&I1 ; GTP_LUT2 /* \N175_9[5] */ #( @@ -103328,7 +103093,7 @@ module ipsxb_ddrphy_init_v1_0 \N175_9[5] ( .Z (N175[5]), .I0 (N233), - .I1 (_N19658)); + .I1 (_N19605)); // LUT = I0&I1 ; GTP_LUT2 /* \N175_9[6] */ #( @@ -103336,7 +103101,7 @@ module ipsxb_ddrphy_init_v1_0 \N175_9[6] ( .Z (N175[6]), .I0 (N233), - .I1 (_N19659)); + .I1 (_N19606)); // LUT = I0&I1 ; GTP_LUT2 /* \N175_9[7] */ #( @@ -103344,7 +103109,7 @@ module ipsxb_ddrphy_init_v1_0 \N175_9[7] ( .Z (N175[7]), .I0 (N233), - .I1 (_N19660)); + .I1 (_N19607)); // LUT = I0&I1 ; GTP_LUT2 /* \N175_9[8] */ #( @@ -103352,7 +103117,7 @@ module ipsxb_ddrphy_init_v1_0 \N175_9[8] ( .Z (N175[8]), .I0 (N233), - .I1 (_N19661)); + .I1 (_N19608)); // LUT = I0&I1 ; GTP_LUT2 /* \N175_9[9] */ #( @@ -103360,7 +103125,7 @@ module ipsxb_ddrphy_init_v1_0 \N175_9[9] ( .Z (N175[9]), .I0 (N233), - .I1 (_N19662)); + .I1 (_N19609)); // LUT = I0&I1 ; GTP_LUT2 /* \N175_9[11] */ #( @@ -103368,7 +103133,7 @@ module ipsxb_ddrphy_init_v1_0 \N175_9[11] ( .Z (N175[11]), .I0 (N233), - .I1 (_N19664)); + .I1 (_N19611)); // LUT = I0&I1 ; GTP_LUT2 /* \N175_9[12] */ #( @@ -103376,7 +103141,7 @@ module ipsxb_ddrphy_init_v1_0 \N175_9[12] ( .Z (N175[12]), .I0 (N233), - .I1 (_N19665)); + .I1 (_N19612)); // LUT = I0&I1 ; GTP_LUT2 /* \N175_9[13] */ #( @@ -103384,7 +103149,7 @@ module ipsxb_ddrphy_init_v1_0 \N175_9[13] ( .Z (N175[13]), .I0 (N233), - .I1 (_N19666)); + .I1 (_N19613)); // LUT = I0&I1 ; GTP_LUT2 /* \N175_9[14] */ #( @@ -103392,7 +103157,7 @@ module ipsxb_ddrphy_init_v1_0 \N175_9[14] ( .Z (N175[14]), .I0 (N233), - .I1 (_N19667)); + .I1 (_N19614)); // LUT = I0&I1 ; GTP_LUT5 /* \N175_10[10] */ #( @@ -103401,7 +103166,7 @@ module ipsxb_ddrphy_init_v1_0 .Z (N175[10]), .I0 (init_next_state[2]), .I1 (init_state_reg[8]), - .I2 (_N19663), + .I2 (_N19610), .I3 (_N27705), .I4 (_N27706)); // LUT = (I0&~I1&I3&I4)|(I0&~I1&I2&~I3&~I4) ; @@ -103409,7 +103174,7 @@ module ipsxb_ddrphy_init_v1_0 GTP_LUT4 /* N225_6 */ #( .INIT(16'b0000000000000010)) N225_6 ( - .Z (_N97036), + .Z (_N97805), .I0 (cnt_cmd[0]), .I1 (cnt_cmd[5]), .I2 (cnt_cmd[6]), @@ -103424,7 +103189,7 @@ module ipsxb_ddrphy_init_v1_0 .I1 (cnt_cmd[2]), .I2 (cnt_cmd[3]), .I3 (cnt_cmd[4]), - .I4 (_N97036)); + .I4 (_N97805)); // LUT = I0&I1&I2&I3&I4 ; GTP_LUT5 /* N230 */ #( @@ -103435,7 +103200,7 @@ module ipsxb_ddrphy_init_v1_0 .I1 (cnt_cmd[2]), .I2 (cnt_cmd[3]), .I3 (cnt_cmd[4]), - .I4 (_N97036)); + .I4 (_N97805)); // defparam N230_vname.orig_name = N230; // LUT = ~I0&~I1&~I2&~I3&I4 ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_init_v1_0.vp:393 @@ -103448,7 +103213,7 @@ module ipsxb_ddrphy_init_v1_0 .I1 (cnt_cmd[2]), .I2 (cnt_cmd[3]), .I3 (cnt_cmd[4]), - .I4 (_N97036)); + .I4 (_N97805)); // defparam N231_vname.orig_name = N231; // LUT = I0&~I1&~I2&~I3&I4 ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_init_v1_0.vp:401 @@ -103456,7 +103221,7 @@ module ipsxb_ddrphy_init_v1_0 GTP_LUT3 /* N232_2 */ #( .INIT(8'b00000001)) N232_2 ( - .Z (_N103614), + .Z (_N104426), .I0 (init_state_reg[7]), .I1 (init_state_reg[8]), .I2 (_N27719)); @@ -103507,7 +103272,7 @@ module ipsxb_ddrphy_init_v1_0 GTP_LUT5 /* N271_5 */ #( .INIT(32'b00000000000000000000000000000001)) N271_5 ( - .Z (_N103565), + .Z (_N104377), .I0 (cnt_t200us[1]), .I1 (cnt_t200us[2]), .I2 (cnt_t200us[3]), @@ -103518,7 +103283,7 @@ module ipsxb_ddrphy_init_v1_0 GTP_LUT5 /* N271_9 */ #( .INIT(32'b00000000000000000000000000000001)) N271_9 ( - .Z (_N103569), + .Z (_N104381), .I0 (cnt_t200us[7]), .I1 (cnt_t200us[8]), .I2 (cnt_t200us[12]), @@ -103529,7 +103294,7 @@ module ipsxb_ddrphy_init_v1_0 GTP_LUT5 /* N271_13 */ #( .INIT(32'b10000000000000000000000000000000)) N271_13 ( - .Z (_N103573), + .Z (_N104385), .I0 (cnt_t200us[5]), .I1 (cnt_t200us[9]), .I2 (cnt_t200us[10]), @@ -103540,9 +103305,9 @@ module ipsxb_ddrphy_init_v1_0 GTP_LUT2 /* N271_16 */ #( .INIT(4'b1000)) N271_16 ( - .Z (_N103576), - .I0 (_N103569), - .I1 (_N103573)); + .Z (_N104388), + .I0 (_N104381), + .I1 (_N104385)); // LUT = I0&I1 ; GTP_LUT5 /* N274 */ #( @@ -103570,7 +103335,7 @@ module ipsxb_ddrphy_init_v1_0 GTP_LUT5 /* N277_5 */ #( .INIT(32'b00000000000000000000000000000001)) N277_5 ( - .Z (_N103595), + .Z (_N104407), .I0 (cnt_t500us[1]), .I1 (cnt_t500us[2]), .I2 (cnt_t500us[3]), @@ -103581,7 +103346,7 @@ module ipsxb_ddrphy_init_v1_0 GTP_LUT5 /* N277_9 */ #( .INIT(32'b00000000000000000000000000000010)) N277_9 ( - .Z (_N103599), + .Z (_N104411), .I0 (cnt_t500us[4]), .I1 (cnt_t500us[10]), .I2 (cnt_t500us[11]), @@ -103592,7 +103357,7 @@ module ipsxb_ddrphy_init_v1_0 GTP_LUT5 /* N277_13 */ #( .INIT(32'b10000000000000000000000000000000)) N277_13 ( - .Z (_N103603), + .Z (_N104415), .I0 (cnt_t500us[6]), .I1 (cnt_t500us[8]), .I2 (cnt_t500us[9]), @@ -103603,9 +103368,9 @@ module ipsxb_ddrphy_init_v1_0 GTP_LUT2 /* N277_16 */ #( .INIT(4'b1000)) N277_16 ( - .Z (_N103606), - .I0 (_N103599), - .I1 (_N103603)); + .Z (_N104418), + .I0 (_N104411), + .I1 (_N104415)); // LUT = I0&I1 ; GTP_LUT5 /* N282_6_inv */ #( @@ -103614,7 +103379,7 @@ module ipsxb_ddrphy_init_v1_0 .Z (_N18071_inv), .I0 (init_next_state[1]), .I1 (init_next_state[3]), - .I2 (_N81834), + .I2 (_N82622), .I3 (_N27711), .I4 (_N27713)); // LUT = (~I1&I2)|(I0&~I1&I3&~I4) ; @@ -103636,7 +103401,7 @@ module ipsxb_ddrphy_init_v1_0 .I1 (init_state_reg[9]), .I2 (_N27715), .I3 (_N27717), - .I4 (_N103614)); + .I4 (_N104426)); // defparam N285_vname.orig_name = N285; // LUT = (I0)|(~I2&~I3&I4)|(I1&~I3&I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_init_v1_0.vp:404 @@ -103652,7 +103417,7 @@ module ipsxb_ddrphy_init_v1_0 GTP_LUT5 /* N291_17 */ #( .INIT(32'b00000000000000000000000000010000)) N291_17 ( - .Z (_N103626), + .Z (_N104438), .I0 (cnt_tzqinit[1]), .I1 (cnt_tzqinit[2]), .I2 (cnt_tzqinit[7]), @@ -103663,12 +103428,12 @@ module ipsxb_ddrphy_init_v1_0 GTP_LUT5 /* N291_18 */ #( .INIT(32'b00000000000000010000000000000000)) N291_18 ( - .Z (_N103627), + .Z (_N104439), .I0 (cnt_tzqinit[3]), .I1 (cnt_tzqinit[4]), .I2 (cnt_tzqinit[5]), .I3 (cnt_tzqinit[6]), - .I4 (_N103626)); + .I4 (_N104438)); // LUT = ~I0&~I1&~I2&~I3&I4 ; GTP_LUT3 /* N291_19 */ #( @@ -103677,13 +103442,13 @@ module ipsxb_ddrphy_init_v1_0 .Z (N291), .I0 (N235), .I1 (cnt_tzqinit[0]), - .I2 (_N103627)); + .I2 (_N104439)); // LUT = I0&~I1&I2 ; GTP_LUT4 /* N309_3 */ #( .INIT(16'b0001010000000000)) N309_3 ( - .Z (_N81834), + .Z (_N82622), .I0 (init_state_reg[7]), .I1 (_N27705), .I2 (_N27706), @@ -103697,19 +103462,19 @@ module ipsxb_ddrphy_init_v1_0 .Q (cnt_cke_pass), .C (N0), .CLK (ddrphy_clkin), - .D (_N103328)); + .D (_N104140)); // defparam cnt_cke_pass_vname.orig_name = cnt_cke_pass; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_init_v1_0.vp:355 GTP_LUT5 /* cnt_cke_pass_ce_mux */ #( .INIT(32'b01000101010001000100010001000100)) cnt_cke_pass_ce_mux ( - .Z (_N103328), + .Z (_N104140), .I0 (N9), .I1 (cnt_cke_pass), .I2 (cnt_t500us[0]), - .I3 (_N103595), - .I4 (_N103606)); + .I3 (_N104407), + .I4 (_N104418)); // LUT = (~I0&I1)|(~I0&~I2&I3&I4) ; GTP_DFF_C /* \cnt_cmd[0] */ #( @@ -103799,19 +103564,19 @@ module ipsxb_ddrphy_init_v1_0 .Q (cnt_pwron_pass), .C (N0), .CLK (ddrphy_clkin), - .D (_N103327)); + .D (_N104139)); // defparam cnt_pwron_pass_vname.orig_name = cnt_pwron_pass; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_init_v1_0.vp:335 GTP_LUT5 /* cnt_pwron_pass_ce_mux */ #( .INIT(32'b01000101010001000100010001000100)) cnt_pwron_pass_ce_mux ( - .Z (_N103327), + .Z (_N104139), .I0 (N9), .I1 (cnt_pwron_pass), .I2 (cnt_t200us[0]), - .I3 (_N103565), - .I4 (_N103576)); + .I3 (_N104377), + .I4 (_N104388)); // LUT = (~I0&I1)|(~I0&~I2&I3&I4) ; GTP_DFF_C /* \cnt_t200us[0] */ #( @@ -104871,22 +104636,22 @@ module ipsxb_ddrphy_init_v1_0 .C (N0), .CE (N285), .CLK (ddrphy_clkin), - .D (_N41672)); + .D (_N39531)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_init_v1_0.vp:404 - GTP_LUT3 /* \mr_load_cnt[1:0]_1528 */ #( + GTP_LUT3 /* \mr_load_cnt[1:0]_1146 */ #( .INIT(8'b00010000)) - \mr_load_cnt[1:0]_1528 ( - .Z (_N41672), + \mr_load_cnt[1:0]_1146 ( + .Z (_N39531), .I0 (mr_load_cnt[0]), .I1 (init_state_reg[7]), .I2 (_N27719)); // LUT = ~I0&~I1&I2 ; - GTP_LUT4 /* \mr_load_cnt[1:0]_1544 */ #( + GTP_LUT4 /* \mr_load_cnt[1:0]_1158 */ #( .INIT(16'b0000011000000000)) - \mr_load_cnt[1:0]_1544 ( - .Z (_N41712), + \mr_load_cnt[1:0]_1158 ( + .Z (_N39567), .I0 (mr_load_cnt[0]), .I1 (mr_load_cnt[1]), .I2 (init_state_reg[7]), @@ -104901,7 +104666,7 @@ module ipsxb_ddrphy_init_v1_0 .C (N0), .CE (N285), .CLK (ddrphy_clkin), - .D (_N41712)); + .D (_N39567)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_init_v1_0.vp:404 GTP_DFF_CE /* mr_load_done */ #( @@ -104912,14 +104677,14 @@ module ipsxb_ddrphy_init_v1_0 .C (N0), .CE (N285), .CLK (ddrphy_clkin), - .D (_N41775)); + .D (_N39627)); // defparam mr_load_done_vname.orig_name = mr_load_done; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_init_v1_0.vp:404 GTP_LUT4 /* mr_load_done_0 */ #( .INIT(16'b0000100000000000)) mr_load_done_0 ( - .Z (_N41775), + .Z (_N39627), .I0 (mr_load_cnt[0]), .I1 (mr_load_cnt[1]), .I2 (init_state_reg[7]), @@ -104949,7 +104714,7 @@ module ipsxb_ddrphy_main_ctrl_v1_3 wire _N2; wire _N5; wire _N11; - wire _N96030; + wire _N96815; wire [2:0] main_next_state; wire [5:0] main_state_reg; @@ -104973,7 +104738,7 @@ module ipsxb_ddrphy_main_ctrl_v1_3 .I1 (wrlvl_done), .I2 (main_state_reg[1]), .I3 (main_state_reg[2]), - .I4 (_N96030)); + .I4 (_N96815)); // defparam N68_vname.orig_name = N68; // LUT = (~I1&I3&I4)|(I0&I2&I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_main_ctrl_v1_3.vp:216 @@ -104981,7 +104746,7 @@ module ipsxb_ddrphy_main_ctrl_v1_3 GTP_LUT5M /* N68_1 */ #( .INIT(32'b00000000010101010000000011101100)) N68_1 ( - .Z (_N96030), + .Z (_N96815), .I0 (rdcal_done), .I1 (main_state_reg[2]), .I2 (main_state_reg[1]), @@ -104998,7 +104763,7 @@ module ipsxb_ddrphy_main_ctrl_v1_3 .I1 (wrlvl_done), .I2 (main_state_reg[1]), .I3 (main_state_reg[2]), - .I4 (_N96030)); + .I4 (_N96815)); // defparam N69_vname.orig_name = N69; // LUT = (~I2&~I3&I4)|(~I0&~I3&I4)|(I1&~I2&I4)|(~I0&I1&I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_main_ctrl_v1_3.vp:226 @@ -105182,19 +104947,19 @@ module ipsxb_ddrphy_wrlvl_v1_0 wire _N12; wire _N18; wire _N21; - wire _N16315; - wire _N16316; - wire _N16317; - wire _N16318; - wire _N16319; - wire _N16320; - wire _N96032; - wire _N103329; - wire _N103330; - wire _N103331; - wire _N103632; - wire _N106835; - wire _N106841; + wire _N17009; + wire _N17010; + wire _N17011; + wire _N17012; + wire _N17013; + wire _N17014; + wire _N96819; + wire _N104141; + wire _N104142; + wire _N104143; + wire _N104444; + wire _N107664; + wire _N107670; wire [7:0] cmd_cnt; wire cnt_tmod_pass; wire cnt_twldqsen_pass; @@ -105209,7 +104974,7 @@ module ipsxb_ddrphy_wrlvl_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N8_1_1 ( - .COUT (_N16315), + .COUT (_N17009), .Z (N15[1]), .CIN (), .I0 (cmd_cnt[0]), @@ -105229,9 +104994,9 @@ module ipsxb_ddrphy_wrlvl_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N8_1_2 ( - .COUT (_N16316), + .COUT (_N17010), .Z (N15[2]), - .CIN (_N16315), + .CIN (_N17009), .I0 (cmd_cnt[0]), .I1 (cmd_cnt[1]), .I2 (N176), @@ -105249,9 +105014,9 @@ module ipsxb_ddrphy_wrlvl_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N8_1_3 ( - .COUT (_N16317), + .COUT (_N17011), .Z (N15[3]), - .CIN (_N16316), + .CIN (_N17010), .I0 (), .I1 (cmd_cnt[3]), .I2 (N176), @@ -105269,9 +105034,9 @@ module ipsxb_ddrphy_wrlvl_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N8_1_4 ( - .COUT (_N16318), + .COUT (_N17012), .Z (N15[4]), - .CIN (_N16317), + .CIN (_N17011), .I0 (), .I1 (cmd_cnt[4]), .I2 (N176), @@ -105289,9 +105054,9 @@ module ipsxb_ddrphy_wrlvl_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N8_1_5 ( - .COUT (_N16319), + .COUT (_N17013), .Z (N15[5]), - .CIN (_N16318), + .CIN (_N17012), .I0 (), .I1 (cmd_cnt[5]), .I2 (N176), @@ -105309,9 +105074,9 @@ module ipsxb_ddrphy_wrlvl_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N8_1_6 ( - .COUT (_N16320), + .COUT (_N17014), .Z (N15[6]), - .CIN (_N16319), + .CIN (_N17013), .I0 (), .I1 (cmd_cnt[6]), .I2 (N176), @@ -105331,7 +105096,7 @@ module ipsxb_ddrphy_wrlvl_v1_0 N8_1_7 ( .COUT (), .Z (N15[7]), - .CIN (_N16320), + .CIN (_N17014), .I0 (), .I1 (cmd_cnt[7]), .I2 (N176), @@ -105362,7 +105127,7 @@ module ipsxb_ddrphy_wrlvl_v1_0 GTP_LUT4 /* N113_2 */ #( .INIT(16'b0101010101010100)) N113_2 ( - .Z (_N96032), + .Z (_N96819), .I0 (dbg_wrlvl[0]), .I1 (wrlvl_state_reg[6]), .I2 (wrlvl_state_reg[2]), @@ -105383,7 +105148,7 @@ module ipsxb_ddrphy_wrlvl_v1_0 GTP_LUT4 /* N124_6 */ #( .INIT(16'b0000000000000001)) N124_6 ( - .Z (_N106841), + .Z (_N107670), .I0 (cmd_cnt[2]), .I1 (cmd_cnt[3]), .I2 (cmd_cnt[6]), @@ -105398,13 +105163,13 @@ module ipsxb_ddrphy_wrlvl_v1_0 .I1 (cmd_cnt[1]), .I2 (cmd_cnt[4]), .I3 (cmd_cnt[5]), - .I4 (_N106841)); + .I4 (_N107670)); // LUT = I0&I1&~I2&~I3&I4 ; GTP_LUT4 /* N141_2 */ #( .INIT(16'b0111011101110100)) N141_2 ( - .Z (_N103632), + .Z (_N104444), .I0 (cnt_tmod_pass), .I1 (wrlvl_state_reg[6]), .I2 (wrlvl_state_reg[2]), @@ -105653,7 +105418,7 @@ module ipsxb_ddrphy_wrlvl_v1_0 GTP_LUT5 /* \dbg_wrlvl_or[0]_8 */ #( .INIT(32'b11111110111111001111101011110000)) \dbg_wrlvl_or[0]_8 ( - .Z (_N106835), + .Z (_N107664), .I0 (wrlvl_dqs_resp), .I1 (cnt_twldqsen_pass), .I2 (wrlvl_state_reg[5]), @@ -105669,7 +105434,7 @@ module ipsxb_ddrphy_wrlvl_v1_0 .I1 (wrlvl_state_reg[0]), .I2 (cnt_tmod_pass), .I3 (wrlvl_state_reg[6]), - .I4 (_N106835)); + .I4 (_N107664)); // LUT = (I4)|(I0&I1)|(I2&I3) ; GTP_LUT3 /* \dbg_wrlvl_or[1]_3 */ #( @@ -105871,19 +105636,19 @@ module ipsxb_ddrphy_wrlvl_v1_0 .Q (wrlvl_dqs_req), .C (N0), .CLK (ddrphy_clkin), - .D (_N103331)); + .D (_N104143)); // defparam wrlvl_dqs_req_vname.orig_name = wrlvl_dqs_req; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_wrlvl_v1_0.vp:380 GTP_LUT5 /* wrlvl_dqs_req_ce_mux */ #( .INIT(32'b00000000111101000000000011110000)) wrlvl_dqs_req_ce_mux ( - .Z (_N103331), + .Z (_N104143), .I0 (dbg_wrlvl[2]), .I1 (dbg_wrlvl[0]), .I2 (wrlvl_dqs_req), .I3 (wrlvl_dqs_resp), - .I4 (_N103632)); + .I4 (_N104444)); // LUT = (I2&~I3)|(~I0&I1&~I3&I4) ; GTP_DFF_C /* wrlvl_dqs_resp_r */ #( @@ -105893,14 +105658,14 @@ module ipsxb_ddrphy_wrlvl_v1_0 .Q (wrlvl_dqs_resp_r), .C (N0), .CLK (ddrphy_clkin), - .D (_N103329)); + .D (_N104141)); // defparam wrlvl_dqs_resp_r_vname.orig_name = wrlvl_dqs_resp_r; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_wrlvl_v1_0.vp:246 GTP_LUT5 /* wrlvl_dqs_resp_r_ce_mux */ #( .INIT(32'b11111110111111101111111000000000)) wrlvl_dqs_resp_r_ce_mux ( - .Z (_N103329), + .Z (_N104141), .I0 (dbg_wrlvl[2]), .I1 (dbg_wrlvl[1]), .I2 (dbg_wrlvl[0]), @@ -105915,19 +105680,19 @@ module ipsxb_ddrphy_wrlvl_v1_0 .Q (wrlvl_odt), .C (N0), .CLK (ddrphy_clkin), - .D (_N103330)); + .D (_N104142)); // defparam wrlvl_odt_vname.orig_name = wrlvl_odt; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_wrlvl_v1_0.vp:332 GTP_LUT5 /* wrlvl_odt_ce_mux */ #( .INIT(32'b01110101001100000011000000110000)) wrlvl_odt_ce_mux ( - .Z (_N103330), + .Z (_N104142), .I0 (dbg_wrlvl[2]), .I1 (wrlvl_dqs_resp), .I2 (wrlvl_odt), .I3 (N124), - .I4 (_N96032)); + .I4 (_N96819)); // LUT = (~I1&I2)|(~I0&I3&I4) ; GTP_LUT3 /* \wrlvl_state_fsm[4:0]_2 */ #( @@ -106091,8 +105856,8 @@ module ipsxb_ddrphy_rdcal_v1_2 input [3:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/gate_cal_error_tmp , input [3:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/rdel_calib_done_tmp , input N0, - input _N97037, - input _N105439, + input _N97806, + input _N106213, input adj_rdel_done, input ddrphy_clkin, input ddrphy_rst_ack, @@ -106171,57 +105936,57 @@ module ipsxb_ddrphy_rdcal_v1_2 wire _N303; wire _N307; wire _N312; + wire _N14283; + wire _N14284; + wire _N14285; + wire _N14286; + wire _N14287; + wire _N14288; + wire _N14289; + wire _N14290; + wire _N14291; + wire _N14292; + wire _N14293; + wire _N14294; + wire _N14295; + wire _N14296; wire _N14297; wire _N14298; - wire _N14299; - wire _N14300; - wire _N14301; - wire _N14302; - wire _N14303; - wire _N14304; - wire _N14305; - wire _N14306; - wire _N14307; - wire _N14308; - wire _N14309; - wire _N14310; - wire _N14311; - wire _N14312; wire _N18095_inv; - wire _N22258; - wire _N29921; - wire _N95983; - wire _N95994; - wire _N96039; - wire _N96040; - wire _N96049; - wire _N96053; - wire _N96797; - wire _N97033; - wire _N97144; - wire _N97145; - wire _N103332; - wire _N103333; - wire _N103334; - wire _N103335; - wire _N105426; - wire _N105430; - wire _N106546; - wire _N106549; - wire _N106550; - wire _N106551; - wire _N106574; - wire _N106577; - wire _N106578; - wire _N106581; - wire _N106583; - wire _N106584; - wire _N106586; - wire _N106588; - wire _N106592; - wire _N106598; - wire _N106607; - wire _N108364; + wire _N22198; + wire _N29896; + wire _N96759; + wire _N96828; + wire _N96830; + wire _N96833; + wire _N96838; + wire _N96842; + wire _N97576; + wire _N97803; + wire _N97917; + wire _N97918; + wire _N104144; + wire _N104145; + wire _N104146; + wire _N104147; + wire _N106361; + wire _N106365; + wire _N107364; + wire _N107367; + wire _N107368; + wire _N107369; + wire _N107392; + wire _N107395; + wire _N107396; + wire _N107399; + wire _N107401; + wire _N107402; + wire _N107404; + wire _N107406; + wire _N107410; + wire _N107416; + wire _N107425; + wire _N109250; wire cnt_trfc_pass; wire [1:0] ddrphy_rst_ack_r; wire [19:0] rdcal_state_reg; @@ -106255,7 +106020,7 @@ module ipsxb_ddrphy_rdcal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N33_1_1 ( - .COUT (_N14297), + .COUT (_N14283), .Z (N33[1]), .CIN (), .I0 (cnt[0]), @@ -106275,9 +106040,9 @@ module ipsxb_ddrphy_rdcal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N33_1_2 ( - .COUT (_N14298), + .COUT (_N14284), .Z (N758[2]), - .CIN (_N14297), + .CIN (_N14283), .I0 (cnt[0]), .I1 (cnt[1]), .I2 (cnt[2]), @@ -106295,9 +106060,9 @@ module ipsxb_ddrphy_rdcal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N33_1_3 ( - .COUT (_N14299), + .COUT (_N14285), .Z (N758[3]), - .CIN (_N14298), + .CIN (_N14284), .I0 (), .I1 (cnt[3]), .I2 (_N18095_inv), @@ -106315,9 +106080,9 @@ module ipsxb_ddrphy_rdcal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N33_1_4 ( - .COUT (_N14300), + .COUT (_N14286), .Z (N758[4]), - .CIN (_N14299), + .CIN (_N14285), .I0 (), .I1 (cnt[4]), .I2 (_N18095_inv), @@ -106335,9 +106100,9 @@ module ipsxb_ddrphy_rdcal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N33_1_5 ( - .COUT (_N14301), + .COUT (_N14287), .Z (N758[5]), - .CIN (_N14300), + .CIN (_N14286), .I0 (), .I1 (cnt[5]), .I2 (_N18095_inv), @@ -106355,9 +106120,9 @@ module ipsxb_ddrphy_rdcal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N33_1_6 ( - .COUT (_N14302), + .COUT (_N14288), .Z (N758[6]), - .CIN (_N14301), + .CIN (_N14287), .I0 (), .I1 (cnt[6]), .I2 (_N18095_inv), @@ -106375,9 +106140,9 @@ module ipsxb_ddrphy_rdcal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N33_1_7 ( - .COUT (_N14303), + .COUT (_N14289), .Z (N758[7]), - .CIN (_N14302), + .CIN (_N14288), .I0 (), .I1 (cnt[7]), .I2 (_N18095_inv), @@ -106395,9 +106160,9 @@ module ipsxb_ddrphy_rdcal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N33_1_8 ( - .COUT (_N14304), + .COUT (_N14290), .Z (N758[8]), - .CIN (_N14303), + .CIN (_N14289), .I0 (), .I1 (cnt[8]), .I2 (_N18095_inv), @@ -106415,9 +106180,9 @@ module ipsxb_ddrphy_rdcal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N33_1_9 ( - .COUT (_N14305), + .COUT (_N14291), .Z (N758[9]), - .CIN (_N14304), + .CIN (_N14290), .I0 (), .I1 (cnt[9]), .I2 (_N18095_inv), @@ -106435,9 +106200,9 @@ module ipsxb_ddrphy_rdcal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N33_1_10 ( - .COUT (_N14306), + .COUT (_N14292), .Z (N758[10]), - .CIN (_N14305), + .CIN (_N14291), .I0 (), .I1 (cnt[10]), .I2 (_N18095_inv), @@ -106455,9 +106220,9 @@ module ipsxb_ddrphy_rdcal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N33_1_11 ( - .COUT (_N14307), + .COUT (_N14293), .Z (N758[11]), - .CIN (_N14306), + .CIN (_N14292), .I0 (), .I1 (cnt[11]), .I2 (_N18095_inv), @@ -106475,9 +106240,9 @@ module ipsxb_ddrphy_rdcal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N33_1_12 ( - .COUT (_N14308), + .COUT (_N14294), .Z (N758[12]), - .CIN (_N14307), + .CIN (_N14293), .I0 (), .I1 (cnt[12]), .I2 (_N18095_inv), @@ -106495,9 +106260,9 @@ module ipsxb_ddrphy_rdcal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N33_1_13 ( - .COUT (_N14309), + .COUT (_N14295), .Z (N758[13]), - .CIN (_N14308), + .CIN (_N14294), .I0 (), .I1 (cnt[13]), .I2 (_N18095_inv), @@ -106515,9 +106280,9 @@ module ipsxb_ddrphy_rdcal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N33_1_14 ( - .COUT (_N14310), + .COUT (_N14296), .Z (N758[14]), - .CIN (_N14309), + .CIN (_N14295), .I0 (), .I1 (cnt[14]), .I2 (_N18095_inv), @@ -106535,9 +106300,9 @@ module ipsxb_ddrphy_rdcal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N33_1_15 ( - .COUT (_N14311), + .COUT (_N14297), .Z (N758[15]), - .CIN (_N14310), + .CIN (_N14296), .I0 (), .I1 (cnt[15]), .I2 (_N18095_inv), @@ -106555,9 +106320,9 @@ module ipsxb_ddrphy_rdcal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N33_1_16 ( - .COUT (_N14312), + .COUT (_N14298), .Z (N758[16]), - .CIN (_N14311), + .CIN (_N14297), .I0 (), .I1 (cnt[16]), .I2 (_N18095_inv), @@ -106577,7 +106342,7 @@ module ipsxb_ddrphy_rdcal_v1_2 N33_1_17 ( .COUT (), .Z (N758[17]), - .CIN (_N14312), + .CIN (_N14298), .I0 (), .I1 (cnt[17]), .I2 (_N18095_inv), @@ -106591,7 +106356,7 @@ module ipsxb_ddrphy_rdcal_v1_2 GTP_LUT4 /* N124_6 */ #( .INIT(16'b0000000000010000)) N124_6 ( - .Z (_N106581), + .Z (_N107399), .I0 (cnt[1]), .I1 (cnt[5]), .I2 (cnt[6]), @@ -106667,7 +106432,7 @@ module ipsxb_ddrphy_rdcal_v1_2 GTP_LUT5 /* N313_mux16_21 */ #( .INIT(32'b11111111111111111111111111111110)) N313_mux16_21 ( - .Z (_N105426), + .Z (_N106361), .I0 (cnt[11]), .I1 (cnt[12]), .I2 (cnt[13]), @@ -106678,7 +106443,7 @@ module ipsxb_ddrphy_rdcal_v1_2 GTP_LUT5 /* N313_mux16_25 */ #( .INIT(32'b11111111111111111111111111111110)) N313_mux16_25 ( - .Z (_N105430), + .Z (_N106365), .I0 (cnt[1]), .I1 (cnt[2]), .I2 (cnt[6]), @@ -106692,9 +106457,9 @@ module ipsxb_ddrphy_rdcal_v1_2 .Z (N313_inv), .I0 (cnt[5]), .I1 (cnt[3]), - .I2 (_N108364), - .I3 (_N105426), - .I4 (_N105430)); + .I2 (_N109250), + .I3 (_N106361), + .I4 (_N106365)); // LUT = (I0)|(I1)|(I2)|(I3)|(I4) ; GTP_LUT4 /* \N370_2_or[0] */ #( @@ -106704,13 +106469,13 @@ module ipsxb_ddrphy_rdcal_v1_2 .I0 (N238), .I1 (N813), .I2 (rdcal_state_reg[7]), - .I3 (_N97144)); + .I3 (_N97917)); // LUT = (I3)|(I0&I1)|(I0&I2) ; GTP_LUT3 /* \N370_2_or[0]_1 */ #( .INIT(8'b11111110)) \N370_2_or[0]_1 ( - .Z (_N95983), + .Z (_N96759), .I0 (rdcal_state_reg[16]), .I1 (rdcal_state_reg[11]), .I2 (rdcal_state_reg[4])); @@ -106723,7 +106488,7 @@ module ipsxb_ddrphy_rdcal_v1_2 .I0 (rdel_move_done), .I1 (rdcal_state_reg[12]), .I2 (cnt[4]), - .I3 (_N96053)); + .I3 (_N96842)); // LUT = (I0&I3)|(I1&I2) ; GTP_LUT5 /* \N371_1_or[0]_8 */ #( @@ -106733,8 +106498,8 @@ module ipsxb_ddrphy_rdcal_v1_2 .I0 (N238), .I1 (N813), .I2 (rdcal_state_reg[13]), - .I3 (_N95994), - .I4 (_N96797)); + .I3 (_N96828), + .I4 (_N97576)); // LUT = (I2)|(I3)|(I4)|(I0&I1) ; GTP_LUT5 /* \N372_2_or[0]_6 */ #( @@ -106744,8 +106509,8 @@ module ipsxb_ddrphy_rdcal_v1_2 .I0 (N238), .I1 (rdcal_state_reg[12]), .I2 (rdcal_state_reg[7]), - .I3 (_N95983), - .I4 (_N97144)); + .I3 (_N96759), + .I4 (_N97917)); // LUT = (I3)|(I4)|(I0&I1)|(I0&I2) ; GTP_LUT5 /* \N373_1_inv[0] */ #( @@ -106756,13 +106521,13 @@ module ipsxb_ddrphy_rdcal_v1_2 .I1 (N530), .I2 (rdcal_state_reg[15]), .I3 (rdcal_state_reg[5]), - .I4 (_N29921)); + .I4 (_N29896)); // LUT = (~I2&~I3&~I4)|(~I1&~I3&~I4)|(~I0&~I2&~I4)|(~I0&~I1&~I4) ; GTP_LUT4 /* \N373_1_or[0][2] */ #( .INIT(16'b0101010101010100)) \N373_1_or[0][2] ( - .Z (_N29921), + .Z (_N29896), .I0 (N238), .I1 (rdcal_state_reg[16]), .I2 (rdcal_state_reg[12]), @@ -106799,12 +106564,12 @@ module ipsxb_ddrphy_rdcal_v1_2 GTP_LUT5 /* \N406_3[0]_1 */ #( .INIT(32'b10000100001000010000000000000000)) \N406_3[0]_1 ( - .Z (_N22258), + .Z (_N22198), .I0 (mc_wl[2]), .I1 (mc_wl[3]), .I2 (cnt[0]), .I3 (cnt[1]), - .I4 (_N96040)); + .I4 (_N96830)); // LUT = (~I0&~I1&~I2&~I3&I4)|(I0&~I1&I2&~I3&I4)|(~I0&I1&~I2&I3&I4)|(I0&I1&I2&I3&I4) ; GTP_LUT3 /* \N431_1[0] */ #( @@ -106852,17 +106617,6 @@ module ipsxb_ddrphy_rdcal_v1_2 .I1 (mc_wl[1])); // LUT = (I0&~I1)|(~I0&I1) ; - GTP_LUT5 /* N440_2 */ #( - .INIT(32'b11111111111111111111111111111110)) - N440_2 ( - .Z (_N108364), - .I0 (cnt[4]), - .I1 (cnt[7]), - .I2 (cnt[8]), - .I3 (cnt[9]), - .I4 (cnt[10])); - // LUT = (I0)|(I1)|(I2)|(I3)|(I4) ; - GTP_LUT5 /* N440_5 */ #( .INIT(32'b01000000000000000000000000000000)) N440_5 ( @@ -106871,13 +106625,24 @@ module ipsxb_ddrphy_rdcal_v1_2 .I1 (cnt[2]), .I2 (cnt[3]), .I3 (cnt[4]), - .I4 (_N97037)); + .I4 (_N97806)); // LUT = ~I0&I1&I2&I3&I4 ; + GTP_LUT5 /* N465_2 */ #( + .INIT(32'b11111111111111111111111111111110)) + N465_2 ( + .Z (_N109250), + .I0 (cnt[4]), + .I1 (cnt[7]), + .I2 (cnt[8]), + .I3 (cnt[9]), + .I4 (cnt[10])); + // LUT = (I0)|(I1)|(I2)|(I3)|(I4) ; + GTP_LUT3 /* N530_1 */ #( .INIT(8'b00000001)) N530_1 ( - .Z (_N96040), + .Z (_N96830), .I0 (cnt[2]), .I1 (cnt[3]), .I2 (cnt[4])); @@ -106891,13 +106656,13 @@ module ipsxb_ddrphy_rdcal_v1_2 .I1 (cnt[2]), .I2 (cnt[4]), .I3 (cnt[5]), - .I4 (_N105439)); + .I4 (_N106213)); // LUT = ~I0&I1&~I2&~I3&I4 ; GTP_LUT2 /* N542_6 */ #( .INIT(4'b0001)) N542_6 ( - .Z (_N106574), + .Z (_N107392), .I0 (cnt[16]), .I1 (cnt[17])); // LUT = ~I0&~I1 ; @@ -106905,23 +106670,23 @@ module ipsxb_ddrphy_rdcal_v1_2 GTP_LUT5 /* N542_9 */ #( .INIT(32'b00000000000000010000000000000000)) N542_9 ( - .Z (_N106577), + .Z (_N107395), .I0 (cnt[8]), .I1 (cnt[9]), .I2 (cnt[10]), .I3 (cnt[11]), - .I4 (_N106574)); + .I4 (_N107392)); // LUT = ~I0&~I1&~I2&~I3&I4 ; GTP_LUT5 /* N542_10 */ #( .INIT(32'b00000000000000010000000000000000)) N542_10 ( - .Z (_N106578), + .Z (_N107396), .I0 (cnt[12]), .I1 (cnt[13]), .I2 (cnt[14]), .I3 (cnt[15]), - .I4 (_N96049)); + .I4 (_N96838)); // LUT = ~I0&~I1&~I2&~I3&I4 ; GTP_LUT1 /* N544 */ #( @@ -106977,9 +106742,9 @@ module ipsxb_ddrphy_rdcal_v1_2 N671_vname ( .Z (N671), .I0 (rdcal_state_reg[13]), - .I1 (_N106577), - .I2 (_N106578), - .I3 (_N106581)); + .I1 (_N107395), + .I2 (_N107396), + .I3 (_N107399)); // defparam N671_vname.orig_name = N671; // LUT = (I0&~I3)|(I0&~I2)|(I0&~I1) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_rdcal_v1_2.vp:627 @@ -107015,20 +106780,29 @@ module ipsxb_ddrphy_rdcal_v1_2 // LUT = I0&I1 ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_rdcal_v1_2.vp:627 - GTP_LUT4 /* N679_1 */ #( - .INIT(16'b1111000111110000)) + GTP_LUT3 /* N679_1 */ #( + .INIT(8'b10111010)) N679_1 ( - .Z (_N97145), + .Z (_N96833), + .I0 (N671), + .I1 (cnt_trfc_pass), + .I2 (rdcal_state_reg[3])); + // LUT = (I0)|(~I1&I2) ; + + GTP_LUT4 /* N679_2 */ #( + .INIT(16'b1111000111110000)) + N679_2 ( + .Z (_N97918), .I0 (rdel_move_done), .I1 (cnt[5]), - .I2 (_N96039), - .I3 (_N96053)); + .I2 (_N96833), + .I3 (_N96842)); // LUT = (I2)|(~I0&~I1&I3) ; - GTP_LUT5 /* N679_8 */ #( + GTP_LUT5 /* N679_9 */ #( .INIT(32'b11011101110011001111110111111100)) - N679_8 ( - .Z (_N106607), + N679_9 ( + .Z (_N107425), .I0 (rdcal_start), .I1 (N247), .I2 (rdcal_state_reg[5]), @@ -107041,22 +106815,22 @@ module ipsxb_ddrphy_rdcal_v1_2 N685_vname ( .Z (N685), .I0 (rdel_move_done), - .I1 (_N96039), - .I2 (_N96053), - .I3 (_N97033), - .I4 (_N106607)); + .I1 (_N96833), + .I2 (_N96842), + .I3 (_N97803), + .I4 (_N107425)); // defparam N685_vname.orig_name = N685; // LUT = (~I1&~I2&~I3&~I4)|(I0&~I1&~I3&~I4) ; GTP_LUT5 /* N752_8 */ #( .INIT(32'b11111111111111111111111011111100)) N752_8 ( - .Z (_N106592), + .Z (_N107410), .I0 (rdel_move_done), .I1 (N813), .I2 (rdcal_state_reg[15]), - .I3 (_N96053), - .I4 (_N96797)); + .I3 (_N96842), + .I4 (_N97576)); // LUT = (I1)|(I2)|(I4)|(I0&I3) ; GTP_LUT5 /* N752_10 */ #( @@ -107065,15 +106839,15 @@ module ipsxb_ddrphy_rdcal_v1_2 .Z (N752), .I0 (N672), .I1 (rdcal_state_reg[17]), - .I2 (_N97145), - .I3 (_N106546), - .I4 (_N106592)); + .I2 (_N97918), + .I3 (_N107364), + .I4 (_N107410)); // LUT = (I0)|(I1)|(I2)|(I3)|(I4) ; GTP_LUT5 /* N758_44_3 */ #( .INIT(32'b11111110111110101100110000000000)) N758_44_3 ( - .Z (_N106549), + .Z (_N107367), .I0 (rdcal_state_reg[11]), .I1 (rdcal_state_reg[7]), .I2 (rdcal_state_reg[5]), @@ -107084,7 +106858,7 @@ module ipsxb_ddrphy_rdcal_v1_2 GTP_LUT5 /* N758_44_4 */ #( .INIT(32'b11111111111011001110110011101100)) N758_44_4 ( - .Z (_N106550), + .Z (_N107368), .I0 (adj_rdel_done), .I1 (N675), .I2 (rdcal_state_reg[17]), @@ -107095,11 +106869,11 @@ module ipsxb_ddrphy_rdcal_v1_2 GTP_LUT4 /* N758_44_5 */ #( .INIT(16'b1111111111001000)) N758_44_5 ( - .Z (_N106551), + .Z (_N107369), .I0 (rddata_check_pass), .I1 (rdcal_state_reg[10]), .I2 (cnt[5]), - .I3 (_N106549)); + .I3 (_N107367)); // LUT = (I3)|(I0&I1)|(I1&I2) ; GTP_LUT5 /* N758_44_inv */ #( @@ -107108,15 +106882,15 @@ module ipsxb_ddrphy_rdcal_v1_2 .Z (_N18095_inv), .I0 (N672), .I1 (_N303), - .I2 (_N106546), - .I3 (_N106550), - .I4 (_N106551)); + .I2 (_N107364), + .I3 (_N107368), + .I4 (_N107369)); // LUT = ~I0&~I1&~I2&~I3&~I4 ; GTP_LUT4 /* N758_45_2 */ #( .INIT(16'b1010101011111110)) N758_45_2 ( - .Z (_N106588), + .Z (_N107406), .I0 (_N294), .I1 (rdcal_state_reg[11]), .I2 (rdcal_state_reg[5]), @@ -107128,9 +106902,9 @@ module ipsxb_ddrphy_rdcal_v1_2 N758_46 ( .Z (N758[0]), .I0 (cnt[0]), - .I1 (_N97033), - .I2 (_N97145), - .I3 (_N106588)); + .I1 (_N97803), + .I2 (_N97918), + .I3 (_N107406)); // LUT = (~I0&I1)|(~I0&I2)|(~I0&I3) ; GTP_LUT4 /* N758_47 */ #( @@ -107138,38 +106912,26 @@ module ipsxb_ddrphy_rdcal_v1_2 N758_47 ( .Z (N758[1]), .I0 (N33[1]), - .I1 (_N97033), - .I2 (_N97145), - .I3 (_N106588)); + .I1 (_N97803), + .I2 (_N97918), + .I3 (_N107406)); // LUT = (I0&I1)|(I0&I2)|(I0&I3) ; - GTP_LUT5M /* N758_68 */ #( - .INIT(32'b01010101010101010000000000000001)) - N758_68 ( - .Z (_N95994), - .I0 (N530), - .I1 (rdcal_state_reg[13]), - .I2 (rdcal_state_reg[2]), - .I3 (_N96797), - .I4 (rdcal_state_reg[15]), - .ID (N813)); - // LUT = (~ID&~I1&~I2&~I3&~I4)|(~I0&I4) ; - - GTP_LUT5 /* N758_77 */ #( + GTP_LUT5 /* N758_76 */ #( .INIT(32'b11111111111111111101110001010000)) - N758_77 ( - .Z (_N97144), + N758_76 ( + .Z (_N97917), .I0 (N297), .I1 (rdcal_state_reg[10]), .I2 (rdcal_state_reg[5]), .I3 (N313_inv), - .I4 (_N95994)); + .I4 (_N96828)); // LUT = (I4)|(~I0&I2)|(I1&I3) ; - GTP_LUT5 /* N758_79 */ #( + GTP_LUT5 /* N758_78 */ #( .INIT(32'b11111111111111111111111110000000)) - N758_79 ( - .Z (_N106546), + N758_78 ( + .Z (_N107364), .I0 (cnt_trfc_pass), .I1 (ref_cnt_done), .I2 (rdcal_state_reg[3]), @@ -107177,19 +106939,22 @@ module ipsxb_ddrphy_rdcal_v1_2 .I4 (rdcal_state_reg[0])); // LUT = (I3)|(I4)|(I0&I1&I2) ; - GTP_LUT3 /* N760_1 */ #( - .INIT(8'b10111010)) + GTP_LUT5M /* N760_1 */ #( + .INIT(32'b01010101010101010000000000000001)) N760_1 ( - .Z (_N96039), - .I0 (N671), - .I1 (cnt_trfc_pass), - .I2 (rdcal_state_reg[3])); - // LUT = (I0)|(~I1&I2) ; + .Z (_N96828), + .I0 (N530), + .I1 (rdcal_state_reg[13]), + .I2 (rdcal_state_reg[2]), + .I3 (_N97576), + .I4 (rdcal_state_reg[15]), + .ID (N813)); + // LUT = (~ID&~I1&~I2&~I3&~I4)|(~I0&I4) ; GTP_LUT4 /* N781_1 */ #( .INIT(16'b0000000000000001)) N781_1 ( - .Z (_N96049), + .Z (_N96838), .I0 (cnt[0]), .I1 (cnt[2]), .I2 (cnt[3]), @@ -107202,7 +106967,7 @@ module ipsxb_ddrphy_rdcal_v1_2 .Z (N805), .I0 (mc_wl[4]), .I1 (rdcal_state_reg[5]), - .I2 (_N22258)); + .I2 (_N22198)); // LUT = ~I0&I1&I2 ; GTP_LUT4 /* N813_1 */ #( @@ -107218,7 +106983,7 @@ module ipsxb_ddrphy_rdcal_v1_2 GTP_LUT4 /* N813_3 */ #( .INIT(16'b0000101011001110)) N813_3 ( - .Z (_N106583), + .Z (_N107401), .I0 (rdcal_state_reg[16]), .I1 (rdcal_state_reg[12]), .I2 (cnt[3]), @@ -107228,7 +106993,7 @@ module ipsxb_ddrphy_rdcal_v1_2 GTP_LUT4 /* N813_4 */ #( .INIT(16'b0000110010101110)) N813_4 ( - .Z (_N106584), + .Z (_N107402), .I0 (rdcal_state_reg[15]), .I1 (rdcal_state_reg[7]), .I2 (cnt[1]), @@ -107238,28 +107003,28 @@ module ipsxb_ddrphy_rdcal_v1_2 GTP_LUT4 /* N813_6 */ #( .INIT(16'b1111111111110100)) N813_6 ( - .Z (_N106586), + .Z (_N107404), .I0 (adj_rdel_done), .I1 (rdcal_state_reg[17]), - .I2 (_N106583), - .I3 (_N106584)); + .I2 (_N107401), + .I3 (_N107402)); // LUT = (I2)|(I3)|(~I0&I1) ; GTP_LUT5 /* N813_7 */ #( .INIT(32'b11111111111111110010101010101010)) N813_7 ( - .Z (_N97033), + .Z (_N97803), .I0 (rdcal_state_reg[4]), - .I1 (_N97037), - .I2 (_N106577), - .I3 (_N106578), - .I4 (_N106586)); + .I1 (_N97806), + .I2 (_N107395), + .I3 (_N107396), + .I4 (_N107404)); // LUT = (I4)|(I0&~I3)|(I0&~I2)|(I0&~I1) ; GTP_LUT3 /* N819_3 */ #( .INIT(8'b11111110)) N819_3 ( - .Z (_N96797), + .Z (_N97576), .I0 (rdcal_state_reg[10]), .I1 (rdcal_state_reg[7]), .I2 (rdcal_state_reg[5])); @@ -107523,14 +107288,14 @@ module ipsxb_ddrphy_rdcal_v1_2 .Q (gatecal_start), .C (N0), .CLK (ddrphy_clkin), - .D (_N103333)); + .D (_N104145)); // defparam gatecal_start_vname.orig_name = gatecal_start; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_rdcal_v1_2.vp:830 GTP_LUT5 /* gatecal_start_ce_mux */ #( .INIT(32'b00000101000001000000111100001100)) gatecal_start_ce_mux ( - .Z (_N103333), + .Z (_N104145), .I0 (gate_check_pass), .I1 (gatecal_start), .I2 (rdcal_state_reg[17]), @@ -107618,14 +107383,14 @@ module ipsxb_ddrphy_rdcal_v1_2 .Q (rdcal_done), .C (N0), .CLK (ddrphy_clkin), - .D (_N103335)); + .D (_N104147)); // defparam rdcal_done_vname.orig_name = rdcal_done; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_rdcal_v1_2.vp:915 GTP_LUT5 /* rdcal_done_ce_mux */ #( .INIT(32'b11001000100010001000100010001000)) rdcal_done_ce_mux ( - .Z (_N103335), + .Z (_N104147), .I0 (rdcal_done), .I1 (rdcal_state_reg[16]), .I2 (cnt[0]), @@ -107678,7 +107443,7 @@ module ipsxb_ddrphy_rdcal_v1_2 GTP_LUT5 /* \rdcal_state_fsm[4:0]_9 */ #( .INIT(32'b00101010101010101010101010101010)) \rdcal_state_fsm[4:0]_9 ( - .Z (_N96053), + .Z (_N96842), .I0 (rdcal_state_reg[14]), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/rdel_calib_done_tmp [0] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/rdel_calib_done_tmp [1] ), @@ -107724,7 +107489,7 @@ module ipsxb_ddrphy_rdcal_v1_2 .I0 (gate_adj_done), .I1 (rdcal_state_reg[7]), .I2 (cnt[1]), - .I3 (_N106598)); + .I3 (_N107416)); // LUT = (~I0&I3)|(I1&I2) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_rdcal_v1_2.vp:620 @@ -107812,7 +107577,7 @@ module ipsxb_ddrphy_rdcal_v1_2 GTP_LUT5 /* \rdcal_state_fsm[4:0]_64 */ #( .INIT(32'b00000000000000000000000000000010)) \rdcal_state_fsm[4:0]_64 ( - .Z (_N106598), + .Z (_N107416), .I0 (rdcal_state_reg[8]), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/gate_cal_error_tmp [0] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/gate_cal_error_tmp [1] ), @@ -108025,14 +107790,14 @@ module ipsxb_ddrphy_rdcal_v1_2 .Q (rdcal_success), .C (N0), .CLK (ddrphy_clkin), - .D (_N103332)); + .D (_N104144)); // defparam rdcal_success_vname.orig_name = rdcal_success; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_rdcal_v1_2.vp:820 GTP_LUT4 /* rdcal_success_ce_mux */ #( .INIT(16'b1111000011110010)) rdcal_success_ce_mux ( - .Z (_N103332), + .Z (_N104144), .I0 (rdcal_success), .I1 (rdcal_state_reg[17]), .I2 (rdcal_state_reg[13]), @@ -108177,14 +107942,14 @@ module ipsxb_ddrphy_rdcal_v1_2 .Q (rddata_cal), .C (N0), .CLK (ddrphy_clkin), - .D (_N103334)); + .D (_N104146)); // defparam rddata_cal_vname.orig_name = rddata_cal; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_rdcal_v1_2.vp:866 GTP_LUT4 /* rddata_cal_ce_mux */ #( .INIT(16'b0011000010110000)) rddata_cal_ce_mux ( - .Z (_N103334), + .Z (_N104146), .I0 (rddata_cal), .I1 (N238), .I2 (rdcal_state_reg[10]), @@ -108283,14 +108048,14 @@ endmodule module ipsxb_ddrphy_upcal_v1_4 ( input [17:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt , - output _N97037, - output _N105439 + output _N97806, + output _N106213 ); GTP_LUT4 /* \N84_10[1]_4 */ #( .INIT(16'b0000000000000010)) \N84_10[1]_4 ( - .Z (_N97037), + .Z (_N97806), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt [1] ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt [5] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt [6] ), @@ -108300,7 +108065,7 @@ module ipsxb_ddrphy_upcal_v1_4 GTP_LUT2 /* \N84_10[2]_3 */ #( .INIT(4'b0100)) \N84_10[2]_3 ( - .Z (_N105439), + .Z (_N106213), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt [0] ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt [3] )); // LUT = ~I0&I1 ; @@ -108353,8 +108118,8 @@ module ipsxb_ddrphy_calib_top_v1_3 output wrlvl_cke, output wrlvl_dqs_req ); - wire _N97037; - wire _N105439; + wire _N97806; + wire _N106213; wire [14:0] init_address; wire [2:0] init_ba; wire init_cke; @@ -108765,8 +108530,8 @@ module ipsxb_ddrphy_calib_top_v1_3 .rdel_move_en (rdel_move_en), .reinit_adj_rdel (reinit_adj_rdel), .N0 (\calib_mux/N0 ), - ._N97037 (_N97037), - ._N105439 (_N105439), + ._N97806 (_N97806), + ._N106213 (_N106213), .adj_rdel_done (adj_rdel_done), .ddrphy_clkin (ddrphy_clkin), .ddrphy_rst_ack (ddrphy_rst_ack), @@ -108780,8 +108545,8 @@ module ipsxb_ddrphy_calib_top_v1_3 ipsxb_ddrphy_upcal_v1_4 upcal ( .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \rdcal/cnt [7] , \rdcal/cnt [6] , \rdcal/cnt [5] , 1'bx, \rdcal/cnt [3] , 1'bx, \rdcal/cnt [1] , \rdcal/cnt [0] }), - ._N97037 (_N97037), - ._N105439 (_N105439)); + ._N97806 (_N97806), + ._N106213 (_N106213)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_calib_top_v1_3.vp:689 @@ -108834,7 +108599,7 @@ module ipsxb_ddrphy_dfi_v1_4 output init_calib_complete, output phy_rst ); - wire _N103326; + wire _N104138; wire calib_done_r; wire [59:0] phy_addr_d; wire [11:0] phy_ba_d; @@ -114511,13 +114276,13 @@ module ipsxb_ddrphy_dfi_v1_4 .Q (init_calib_complete), .C (N0), .CLK (ddrphy_clkin), - .D (_N103326)); + .D (_N104138)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dfi_v1_4.vp:484 GTP_LUT2 /* dfi_init_complete_ce_mux */ #( .INIT(4'b1110)) dfi_init_complete_ce_mux ( - .Z (_N103326), + .Z (_N104138), .I0 (init_calib_complete), .I1 (calib_done)); // LUT = (I0)|(I1) ; @@ -120932,86 +120697,89 @@ module ipsxb_ddrphy_info_v1_0 wire N382; wire N457; wire N532; - wire _N14573; - wire _N14574; - wire _N14575; - wire _N14576; - wire _N14578; - wire _N14579; - wire _N14580; - wire _N14581; - wire _N14582; + wire _N14531; + wire _N14532; + wire _N14533; + wire _N14534; + wire _N14536; + wire _N14537; + wire _N14538; + wire _N14539; + wire _N14540; wire _N28526; - wire _N55654; - wire _N55657; - wire _N55816; - wire _N55850; - wire _N55955; - wire _N56052; - wire _N56168; - wire _N56277; - wire _N56406; - wire _N56412; - wire _N56462; - wire _N56572; - wire _N56674; - wire _N56792; - wire _N56894; - wire _N56996; - wire _N57173; - wire _N57213; - wire _N57216; - wire _N57314; - wire _N57475; - wire _N57585; - wire _N57630; + wire _N53492; + wire _N53495; + wire _N53605; + wire _N53705; + wire _N53823; + wire _N53924; + wire _N54046; + wire _N54163; + wire _N54312; + wire _N54367; + wire _N54476; + wire _N54592; + wire _N54705; + wire _N54913; + wire _N54922; + wire _N55028; + wire _N55144; + wire _N55147; + wire _N55238; + wire _N55353; + wire _N55469; + wire _N55577; + wire _N55682; + wire _N55803; + wire _N55903; + wire _N56007; + wire _N56131; + wire _N56225; + wire _N56340; + wire _N56440; + wire _N56601; + wire _N56633; + wire _N56770; + wire _N56796; + wire _N56841; + wire _N56880; + wire _N56910; + wire _N56936; + wire _N56942; + wire _N57010; + wire _N57112; + wire _N57176; + wire _N57215; + wire _N57271; + wire _N57335; + wire _N57393; + wire _N57434; + wire _N57454; + wire _N57529; + wire _N57731; wire _N57742; - wire _N57858; - wire _N57964; - wire _N58069; - wire _N58264; - wire _N58274; - wire _N58384; - wire _N58492; - wire _N58585; - wire _N58693; - wire _N58796; - wire _N58842; - wire _N58866; - wire _N58869; - wire _N58954; - wire _N58996; - wire _N59061; - wire _N59105; - wire _N59130; - wire _N59175; - wire _N59208; - wire _N59302; - wire _N59313; - wire _N59356; - wire _N59407; - wire _N59427; - wire _N59497; - wire _N59500; - wire _N59602; - wire _N59714; - wire _N59817; - wire _N59912; - wire _N60056; - wire _N60111; - wire _N60217; - wire _N60317; - wire _N60426; - wire _N60528; - wire _N60641; - wire _N60744; - wire _N60867; - wire _N60960; - wire _N82045; - wire _N96265; - wire _N97065; - wire _N97066; - wire _N105455; + wire _N57841; + wire _N58040; + wire _N58045; + wire _N58048; + wire _N58051; + wire _N58143; + wire _N58245; + wire _N58344; + wire _N58439; + wire _N58543; + wire _N58653; + wire _N58759; + wire _N58877; + wire _N58990; + wire _N82844; + wire _N82848; + wire _N82855; + wire _N82859; + wire _N97038; + wire _N97836; + wire _N97837; + wire _N106264; wire [3:0] mc_al; wire [4:0] \mc_al_6.co ; wire [3:0] mc_cl; @@ -121068,38 +120836,51 @@ module ipsxb_ddrphy_info_v1_0 // LUT = I0&I1&~I2 ; GTP_LUT5 /* N307_1 */ #( - .INIT(32'b01001100000000000100010000000000)) + .INIT(32'b10100000001000001010000000000000)) N307_1 ( .Z (N307), - .I0 (_N58869), - .I1 (calib_done), - .I2 (phy_ba[7]), - .I3 (phy_cke[0]), - .I4 (_N97065)); - // LUT = (~I0&I1&I3)|(I1&~I2&I3&I4) ; + .I0 (calib_done), + .I1 (phy_ba[7]), + .I2 (phy_cke[0]), + .I3 (_N82844), + .I4 (_N97836)); + // LUT = (I0&I2&I3)|(I0&~I1&I2&I4) ; - GTP_LUT3 /* N307_10 */ #( - .INIT(8'b01000000)) - N307_10 ( - .Z (_N97065), - .I0 (phy_ba[6]), - .I1 (N18), - .I2 (_N105455)); - // LUT = ~I0&I1&I2 ; + GTP_LUT5 /* N307_3 */ #( + .INIT(32'b00000000000000000000000000000001)) + N307_3 ( + .Z (_N82844), + .I0 (_N58048), + .I1 (phy_ba[0]), + .I2 (phy_ba[1]), + .I3 (phy_ba[2]), + .I4 (phy_we_n[0])); + // LUT = ~I0&~I1&~I2&~I3&~I4 ; - GTP_LUT3 /* N307_11 */ #( - .INIT(8'b10000000)) - N307_11 ( - .Z (_N97066), - .I0 (phy_ba[6]), - .I1 (N18), - .I2 (_N105455)); - // LUT = I0&I1&I2 ; + GTP_LUT4 /* N307_8 */ #( + .INIT(16'b0011001000000000)) + N307_8 ( + .Z (_N97836), + .I0 (_N58048), + .I1 (phy_ba[6]), + .I2 (phy_we_n[0]), + .I3 (_N106264)); + // LUT = (I0&~I1&I3)|(~I1&I2&I3) ; - GTP_LUT5 /* N307_12 */ #( + GTP_LUT4 /* N307_9 */ #( + .INIT(16'b1100100000000000)) + N307_9 ( + .Z (_N97837), + .I0 (_N58048), + .I1 (phy_ba[6]), + .I2 (phy_we_n[0]), + .I3 (_N106264)); + // LUT = (I0&I1&I3)|(I1&I2&I3) ; + + GTP_LUT5 /* N307_10 */ #( .INIT(32'b00000000000000000000000000000001)) - N307_12 ( - .Z (_N105455), + N307_10 ( + .Z (_N106264), .I0 (phy_ba[8]), .I1 (phy_cas_n[2]), .I2 (phy_cs_n[2]), @@ -121108,15 +120889,26 @@ module ipsxb_ddrphy_info_v1_0 // LUT = ~I0&~I1&~I2&~I3&~I4 ; GTP_LUT5 /* N382_1 */ #( - .INIT(32'b01001100000000000100010000000000)) + .INIT(32'b10100000001000001010000000000000)) N382_1 ( .Z (N382), - .I0 (_N59500), - .I1 (calib_done), - .I2 (phy_ba[7]), - .I3 (phy_cke[0]), - .I4 (_N97066)); - // LUT = (~I0&I1&I3)|(I1&~I2&I3&I4) ; + .I0 (calib_done), + .I1 (phy_ba[7]), + .I2 (phy_cke[0]), + .I3 (_N82848), + .I4 (_N97837)); + // LUT = (I0&I2&I3)|(I0&~I1&I2&I4) ; + + GTP_LUT5 /* N382_3 */ #( + .INIT(32'b00000000000000000000000000000100)) + N382_3 ( + .Z (_N82848), + .I0 (_N58048), + .I1 (phy_ba[0]), + .I2 (phy_ba[1]), + .I3 (phy_ba[2]), + .I4 (phy_we_n[0])); + // LUT = ~I0&I1&~I2&~I3&~I4 ; GTP_LUT5 /* N457_1 */ #( .INIT(32'b10100000100000001010000000000000)) @@ -121125,30 +120917,42 @@ module ipsxb_ddrphy_info_v1_0 .I0 (calib_done), .I1 (phy_ba[7]), .I2 (phy_cke[0]), - .I3 (_N82045), - .I4 (_N97065)); + .I3 (_N82855), + .I4 (_N97836)); // LUT = (I0&I2&I3)|(I0&I1&I2&I4) ; - GTP_LUT4 /* N457_3 */ #( - .INIT(16'b0000000000000100)) + GTP_LUT5 /* N457_3 */ #( + .INIT(32'b00000000000000000000000000010000)) N457_3 ( - .Z (_N82045), - .I0 (phy_ba[0]), - .I1 (phy_ba[1]), - .I2 (phy_ba[2]), - .I3 (N18)); - // LUT = ~I0&I1&~I2&~I3 ; + .Z (_N82855), + .I0 (_N58048), + .I1 (phy_ba[0]), + .I2 (phy_ba[1]), + .I3 (phy_ba[2]), + .I4 (phy_we_n[0])); + // LUT = ~I0&~I1&I2&~I3&~I4 ; GTP_LUT5 /* N532_1 */ #( - .INIT(32'b11000100000000000100010000000000)) + .INIT(32'b10100000100000001010000000000000)) N532_1 ( .Z (N532), - .I0 (_N57216), - .I1 (calib_done), - .I2 (phy_ba[7]), - .I3 (phy_cke[0]), - .I4 (_N97066)); - // LUT = (~I0&I1&I3)|(I1&I2&I3&I4) ; + .I0 (calib_done), + .I1 (phy_ba[7]), + .I2 (phy_cke[0]), + .I3 (_N82859), + .I4 (_N97837)); + // LUT = (I0&I2&I3)|(I0&I1&I2&I4) ; + + GTP_LUT5 /* N532_3 */ #( + .INIT(32'b00000000000000000000000001000000)) + N532_3 ( + .Z (_N82859), + .I0 (_N58048), + .I1 (phy_ba[0]), + .I2 (phy_ba[1]), + .I3 (phy_ba[2]), + .I4 (phy_we_n[0])); + // LUT = ~I0&I1&I2&~I3&~I4 ; GTP_LUT3 /* \mc_al_1[0] */ #( .INIT(8'b01100000)) @@ -121277,7 +121081,7 @@ module ipsxb_ddrphy_info_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) mc_rl_1 ( - .COUT (_N14573), + .COUT (_N14531), .Z (mc_rl[0]), .CIN (), .I0 (mc_cl[0]), @@ -121297,9 +121101,9 @@ module ipsxb_ddrphy_info_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) mc_rl_2 ( - .COUT (_N14574), + .COUT (_N14532), .Z (mc_rl[1]), - .CIN (_N14573), + .CIN (_N14531), .I0 (mc_cl[0]), .I1 (mc_al[0]), .I2 (mc_cl[1]), @@ -121317,9 +121121,9 @@ module ipsxb_ddrphy_info_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) mc_rl_3 ( - .COUT (_N14575), + .COUT (_N14533), .Z (mc_rl[2]), - .CIN (_N14574), + .CIN (_N14532), .I0 (), .I1 (mc_cl[2]), .I2 (mc_al[2]), @@ -121337,9 +121141,9 @@ module ipsxb_ddrphy_info_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) mc_rl_4 ( - .COUT (_N14576), + .COUT (_N14534), .Z (mc_rl[3]), - .CIN (_N14575), + .CIN (_N14533), .I0 (), .I1 (mc_cl[3]), .I2 (mc_al[3]), @@ -121359,7 +121163,7 @@ module ipsxb_ddrphy_info_v1_0 mc_rl_5 ( .COUT (), .Z (mc_rl[4]), - .CIN (_N14576), + .CIN (_N14534), .I0 (), .I1 (), .I2 (), @@ -121377,7 +121181,7 @@ module ipsxb_ddrphy_info_v1_0 .I4_TO_CARRY("FALSE"), .I4_TO_LUT("FALSE")) mc_wl_0 ( - .COUT (_N14578), + .COUT (_N14536), .Z (), .CIN (), .I0 (), @@ -121397,9 +121201,9 @@ module ipsxb_ddrphy_info_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) mc_wl_1 ( - .COUT (_N14579), + .COUT (_N14537), .Z (mc_wl[0]), - .CIN (_N14578), + .CIN (_N14536), .I0 (), .I1 (mr2_ddr3[3]), .I2 (mc_al[0]), @@ -121417,9 +121221,9 @@ module ipsxb_ddrphy_info_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) mc_wl_2 ( - .COUT (_N14580), + .COUT (_N14538), .Z (mc_wl[1]), - .CIN (_N14579), + .CIN (_N14537), .I0 (), .I1 (mr2_ddr3[5]), .I2 (mc_al[1]), @@ -121437,9 +121241,9 @@ module ipsxb_ddrphy_info_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) mc_wl_3 ( - .COUT (_N14581), + .COUT (_N14539), .Z (mc_wl[2]), - .CIN (_N14580), + .CIN (_N14538), .I0 (), .I1 (mc_cwl[3]), .I2 (mc_al[2]), @@ -121457,9 +121261,9 @@ module ipsxb_ddrphy_info_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) mc_wl_4 ( - .COUT (_N14582), + .COUT (_N14540), .Z (mc_wl[3]), - .CIN (_N14581), + .CIN (_N14539), .I0 (), .I1 (mc_cwl[3]), .I2 (mc_al[3]), @@ -121479,7 +121283,7 @@ module ipsxb_ddrphy_info_v1_0 mc_wl_5 ( .COUT (), .Z (mc_wl[4]), - .CIN (_N14582), + .CIN (_N14540), .I0 (), .I1 (), .I2 (), @@ -121498,7 +121302,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N307), .CLK (ddrphy_clkin), - .D (_N58796)); + .D (_N56770)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_CE /* \mr0_ddr3[1] */ #( @@ -121509,7 +121313,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N307), .CLK (ddrphy_clkin), - .D (_N58842)); + .D (_N56796)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_CE /* \mr0_ddr3[2] */ #( @@ -121520,7 +121324,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N307), .CLK (ddrphy_clkin), - .D (_N58866)); + .D (_N56841)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_CE /* \mr0_ddr3[3] */ #( @@ -121531,7 +121335,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N307), .CLK (ddrphy_clkin), - .D (_N58954)); + .D (_N56880)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_CE /* \mr0_ddr3[4] */ #( @@ -121542,7 +121346,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N307), .CLK (ddrphy_clkin), - .D (_N58996)); + .D (_N56910)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_PE /* \mr0_ddr3[5] */ #( @@ -121552,7 +121356,7 @@ module ipsxb_ddrphy_info_v1_0 .Q (mr0_ddr3[5]), .CE (N307), .CLK (ddrphy_clkin), - .D (_N59061), + .D (_N56936), .P (N4)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 @@ -121564,7 +121368,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N307), .CLK (ddrphy_clkin), - .D (_N59105)); + .D (_N57010)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_CE /* \mr0_ddr3[7] */ #( @@ -121575,7 +121379,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N307), .CLK (ddrphy_clkin), - .D (_N59130)); + .D (_N57112)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_PE /* \mr0_ddr3[8] */ #( @@ -121585,7 +121389,7 @@ module ipsxb_ddrphy_info_v1_0 .Q (mr0_ddr3[8]), .CE (N307), .CLK (ddrphy_clkin), - .D (_N59175), + .D (_N57176), .P (N4)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 @@ -121597,7 +121401,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N307), .CLK (ddrphy_clkin), - .D (_N59208)); + .D (_N57215)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_PE /* \mr0_ddr3[10] */ #( @@ -121607,7 +121411,7 @@ module ipsxb_ddrphy_info_v1_0 .Q (mr0_ddr3[10]), .CE (N307), .CLK (ddrphy_clkin), - .D (_N59302), + .D (_N57271), .P (N4)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 @@ -121619,7 +121423,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N307), .CLK (ddrphy_clkin), - .D (_N59313)); + .D (_N57335)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_PE /* \mr0_ddr3[12] */ #( @@ -121629,7 +121433,7 @@ module ipsxb_ddrphy_info_v1_0 .Q (mr0_ddr3[12]), .CE (N307), .CLK (ddrphy_clkin), - .D (_N59356), + .D (_N57393), .P (N4)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 @@ -121641,7 +121445,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N307), .CLK (ddrphy_clkin), - .D (_N59407)); + .D (_N57434)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_CE /* \mr0_ddr3[14] */ #( @@ -121652,157 +121456,170 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N307), .CLK (ddrphy_clkin), - .D (_N59427)); + .D (_N57454)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_LUT5 /* \mr0_ddr3[15:0]_0 */ #( - .INIT(32'b11001100110011001100110011001010)) + .INIT(32'b11110000111100001111000011100100)) \mr0_ddr3[15:0]_0 ( - .Z (_N58866), - .I0 (phy_addr[2]), - .I1 (phy_addr[32]), - .I2 (phy_ba[0]), - .I3 (phy_ba[1]), - .I4 (_N96265)); - // LUT = (I1&I2)|(I1&I3)|(I1&I4)|(I0&~I2&~I3&~I4) ; + .Z (_N56936), + .I0 (_N56942), + .I1 (phy_addr[5]), + .I2 (phy_addr[35]), + .I3 (phy_ba[0]), + .I4 (phy_ba[1])); + // LUT = (I0&I2)|(I2&I3)|(I2&I4)|(~I0&I1&~I3&~I4) ; - GTP_LUT4 /* \mr0_ddr3[15:0]_3 */ #( - .INIT(16'b1111111111111110)) - \mr0_ddr3[15:0]_3 ( - .Z (_N58869), - .I0 (phy_ba[0]), - .I1 (phy_ba[1]), - .I2 (phy_ba[2]), - .I3 (N18)); - // LUT = (I0)|(I1)|(I2)|(I3) ; + GTP_LUT3 /* \mr0_ddr3[15:0]_5 */ #( + .INIT(8'b11111110)) + \mr0_ddr3[15:0]_5 ( + .Z (_N56942), + .I0 (_N58048), + .I1 (phy_ba[2]), + .I2 (phy_we_n[0])); + // LUT = (I0)|(I1)|(I2) ; GTP_LUT5 /* \mr0_ddr3[15:0]_6 */ #( - .INIT(32'b11001100110011001100110011001010)) + .INIT(32'b11110000111100001111000011100100)) \mr0_ddr3[15:0]_6 ( - .Z (_N59427), - .I0 (phy_addr[14]), - .I1 (phy_addr[41]), - .I2 (phy_ba[0]), - .I3 (phy_ba[1]), - .I4 (_N96265)); - // LUT = (I1&I2)|(I1&I3)|(I1&I4)|(I0&~I2&~I3&~I4) ; + .Z (_N57010), + .I0 (_N56942), + .I1 (phy_addr[6]), + .I2 (phy_addr[36]), + .I3 (phy_ba[0]), + .I4 (phy_ba[1])); + // LUT = (I0&I2)|(I2&I3)|(I2&I4)|(~I0&I1&~I3&~I4) ; - GTP_LUT3 /* \mr0_ddr3[15:0]_7 */ #( - .INIT(8'b11001010)) + GTP_LUT4 /* \mr0_ddr3[15:0]_7 */ #( + .INIT(16'b1111000011100100)) \mr0_ddr3[15:0]_7 ( - .Z (_N58796), - .I0 (phy_addr[0]), - .I1 (phy_addr[30]), - .I2 (N18)); - // LUT = (I0&~I2)|(I1&I2) ; + .Z (_N56770), + .I0 (_N58048), + .I1 (phy_addr[0]), + .I2 (phy_addr[30]), + .I3 (phy_we_n[0])); + // LUT = (I0&I2)|(I2&I3)|(~I0&I1&~I3) ; - GTP_LUT3 /* \mr0_ddr3[15:0]_8 */ #( - .INIT(8'b11001010)) + GTP_LUT4 /* \mr0_ddr3[15:0]_8 */ #( + .INIT(16'b1111000011100100)) \mr0_ddr3[15:0]_8 ( - .Z (_N58842), - .I0 (phy_addr[1]), - .I1 (phy_addr[31]), - .I2 (N18)); - // LUT = (I0&~I2)|(I1&I2) ; + .Z (_N56796), + .I0 (_N58048), + .I1 (phy_addr[1]), + .I2 (phy_addr[31]), + .I3 (phy_we_n[0])); + // LUT = (I0&I2)|(I2&I3)|(~I0&I1&~I3) ; - GTP_LUT3 /* \mr0_ddr3[15:0]_71 */ #( - .INIT(8'b11001010)) - \mr0_ddr3[15:0]_71 ( - .Z (_N58954), - .I0 (phy_addr[3]), - .I1 (phy_addr[33]), - .I2 (N18)); - // LUT = (I0&~I2)|(I1&I2) ; + GTP_LUT4 /* \mr0_ddr3[15:0]_9 */ #( + .INIT(16'b1111000011100100)) + \mr0_ddr3[15:0]_9 ( + .Z (_N56841), + .I0 (_N58048), + .I1 (phy_addr[2]), + .I2 (phy_addr[32]), + .I3 (phy_we_n[0])); + // LUT = (I0&I2)|(I2&I3)|(~I0&I1&~I3) ; - GTP_LUT3 /* \mr0_ddr3[15:0]_88 */ #( - .INIT(8'b11001010)) - \mr0_ddr3[15:0]_88 ( - .Z (_N58996), - .I0 (phy_addr[4]), - .I1 (phy_addr[34]), - .I2 (N18)); - // LUT = (I0&~I2)|(I1&I2) ; + GTP_LUT4 /* \mr0_ddr3[15:0]_10 */ #( + .INIT(16'b1111000011100100)) + \mr0_ddr3[15:0]_10 ( + .Z (_N56880), + .I0 (_N58048), + .I1 (phy_addr[3]), + .I2 (phy_addr[33]), + .I3 (phy_we_n[0])); + // LUT = (I0&I2)|(I2&I3)|(~I0&I1&~I3) ; - GTP_LUT3 /* \mr0_ddr3[15:0]_129 */ #( - .INIT(8'b11001010)) - \mr0_ddr3[15:0]_129 ( - .Z (_N59061), - .I0 (phy_addr[5]), - .I1 (phy_addr[35]), - .I2 (N18)); - // LUT = (I0&~I2)|(I1&I2) ; + GTP_LUT4 /* \mr0_ddr3[15:0]_37 */ #( + .INIT(16'b1111000011100100)) + \mr0_ddr3[15:0]_37 ( + .Z (_N56910), + .I0 (_N58048), + .I1 (phy_addr[4]), + .I2 (phy_addr[34]), + .I3 (phy_we_n[0])); + // LUT = (I0&I2)|(I2&I3)|(~I0&I1&~I3) ; - GTP_LUT3 /* \mr0_ddr3[15:0]_155 */ #( - .INIT(8'b11001010)) - \mr0_ddr3[15:0]_155 ( - .Z (_N59105), - .I0 (phy_addr[6]), - .I1 (phy_addr[36]), - .I2 (N18)); - // LUT = (I0&~I2)|(I1&I2) ; + GTP_LUT4 /* \mr0_ddr3[15:0]_189 */ #( + .INIT(16'b1111000011100100)) + \mr0_ddr3[15:0]_189 ( + .Z (_N57112), + .I0 (_N58048), + .I1 (phy_addr[7]), + .I2 (phy_addr[37]), + .I3 (phy_we_n[0])); + // LUT = (I0&I2)|(I2&I3)|(~I0&I1&~I3) ; - GTP_LUT3 /* \mr0_ddr3[15:0]_164 */ #( - .INIT(8'b11001010)) - \mr0_ddr3[15:0]_164 ( - .Z (_N59130), - .I0 (phy_addr[7]), - .I1 (phy_addr[37]), - .I2 (N18)); - // LUT = (I0&~I2)|(I1&I2) ; + GTP_LUT4 /* \mr0_ddr3[15:0]_246 */ #( + .INIT(16'b1111000011100100)) + \mr0_ddr3[15:0]_246 ( + .Z (_N57176), + .I0 (_N58048), + .I1 (phy_addr[8]), + .I2 (phy_addr[38]), + .I3 (phy_we_n[0])); + // LUT = (I0&I2)|(I2&I3)|(~I0&I1&~I3) ; - GTP_LUT3 /* \mr0_ddr3[15:0]_184 */ #( - .INIT(8'b11001010)) - \mr0_ddr3[15:0]_184 ( - .Z (_N59175), - .I0 (phy_addr[8]), - .I1 (phy_addr[38]), - .I2 (N18)); - // LUT = (I0&~I2)|(I1&I2) ; + GTP_LUT4 /* \mr0_ddr3[15:0]_281 */ #( + .INIT(16'b1111000011100100)) + \mr0_ddr3[15:0]_281 ( + .Z (_N57215), + .I0 (_N58048), + .I1 (phy_addr[9]), + .I2 (phy_addr[39]), + .I3 (phy_we_n[0])); + // LUT = (I0&I2)|(I2&I3)|(~I0&I1&~I3) ; - GTP_LUT3 /* \mr0_ddr3[15:0]_196 */ #( - .INIT(8'b11001010)) - \mr0_ddr3[15:0]_196 ( - .Z (_N59208), - .I0 (phy_addr[9]), - .I1 (phy_addr[39]), - .I2 (N18)); - // LUT = (I0&~I2)|(I1&I2) ; + GTP_LUT4 /* \mr0_ddr3[15:0]_332 */ #( + .INIT(16'b1111000011100100)) + \mr0_ddr3[15:0]_332 ( + .Z (_N57271), + .I0 (_N58048), + .I1 (phy_addr[10]), + .I2 (phy_addr[40]), + .I3 (phy_we_n[0])); + // LUT = (I0&I2)|(I2&I3)|(~I0&I1&~I3) ; - GTP_LUT3 /* \mr0_ddr3[15:0]_260 */ #( - .INIT(8'b11001010)) - \mr0_ddr3[15:0]_260 ( - .Z (_N59302), - .I0 (phy_addr[10]), - .I1 (phy_addr[40]), - .I2 (N18)); - // LUT = (I0&~I2)|(I1&I2) ; + GTP_LUT4 /* \mr0_ddr3[15:0]_390 */ #( + .INIT(16'b1111000011100100)) + \mr0_ddr3[15:0]_390 ( + .Z (_N57335), + .I0 (_N58048), + .I1 (phy_addr[11]), + .I2 (phy_addr[41]), + .I3 (phy_we_n[0])); + // LUT = (I0&I2)|(I2&I3)|(~I0&I1&~I3) ; - GTP_LUT3 /* \mr0_ddr3[15:0]_267 */ #( - .INIT(8'b11001010)) - \mr0_ddr3[15:0]_267 ( - .Z (_N59313), - .I0 (phy_addr[11]), - .I1 (phy_addr[41]), - .I2 (N18)); - // LUT = (I0&~I2)|(I1&I2) ; + GTP_LUT4 /* \mr0_ddr3[15:0]_442 */ #( + .INIT(16'b1111000011100100)) + \mr0_ddr3[15:0]_442 ( + .Z (_N57393), + .I0 (_N58048), + .I1 (phy_addr[12]), + .I2 (phy_addr[41]), + .I3 (phy_we_n[0])); + // LUT = (I0&I2)|(I2&I3)|(~I0&I1&~I3) ; - GTP_LUT3 /* \mr0_ddr3[15:0]_285 */ #( - .INIT(8'b11001010)) - \mr0_ddr3[15:0]_285 ( - .Z (_N59356), - .I0 (phy_addr[12]), - .I1 (phy_addr[41]), - .I2 (N18)); - // LUT = (I0&~I2)|(I1&I2) ; + GTP_LUT4 /* \mr0_ddr3[15:0]_479 */ #( + .INIT(16'b1111000011100100)) + \mr0_ddr3[15:0]_479 ( + .Z (_N57434), + .I0 (_N58048), + .I1 (phy_addr[13]), + .I2 (phy_addr[41]), + .I3 (phy_we_n[0])); + // LUT = (I0&I2)|(I2&I3)|(~I0&I1&~I3) ; - GTP_LUT3 /* \mr0_ddr3[15:0]_312 */ #( - .INIT(8'b11001010)) - \mr0_ddr3[15:0]_312 ( - .Z (_N59407), - .I0 (phy_addr[13]), - .I1 (phy_addr[41]), - .I2 (N18)); - // LUT = (I0&~I2)|(I1&I2) ; + GTP_LUT5 /* \mr0_ddr3[15:0]_497 */ #( + .INIT(32'b11110000111100001111000011100100)) + \mr0_ddr3[15:0]_497 ( + .Z (_N57454), + .I0 (_N56942), + .I1 (phy_addr[14]), + .I2 (phy_addr[41]), + .I3 (phy_ba[0]), + .I4 (phy_ba[1])); + // LUT = (I0&I2)|(I2&I3)|(I2&I4)|(~I0&I1&~I3&~I4) ; GTP_DFF_CE /* \mr1_ddr3[0] */ #( .GRS_EN("TRUE"), @@ -121812,7 +121629,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N382), .CLK (ddrphy_clkin), - .D (_N59497)); + .D (_N57529)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_CE /* \mr1_ddr3[1] */ #( @@ -121823,7 +121640,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N382), .CLK (ddrphy_clkin), - .D (_N59602)); + .D (_N57731)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_PE /* \mr1_ddr3[2] */ #( @@ -121833,7 +121650,7 @@ module ipsxb_ddrphy_info_v1_0 .Q (mr1_ddr3[2]), .CE (N382), .CLK (ddrphy_clkin), - .D (_N59714), + .D (_N57742), .P (N4)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 @@ -121845,7 +121662,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N382), .CLK (ddrphy_clkin), - .D (_N59817)); + .D (_N57841)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_PE /* \mr1_ddr3[4] */ #( @@ -121855,7 +121672,7 @@ module ipsxb_ddrphy_info_v1_0 .Q (mr1_ddr3[4]), .CE (N382), .CLK (ddrphy_clkin), - .D (_N59912), + .D (_N58040), .P (N4)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 @@ -121867,7 +121684,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N382), .CLK (ddrphy_clkin), - .D (_N60056)); + .D (_N58051)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_CE /* \mr1_ddr3[6] */ #( @@ -121878,7 +121695,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N382), .CLK (ddrphy_clkin), - .D (_N60111)); + .D (_N58143)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_CE /* \mr1_ddr3[7] */ #( @@ -121889,7 +121706,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N382), .CLK (ddrphy_clkin), - .D (_N60217)); + .D (_N58245)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_CE /* \mr1_ddr3[8] */ #( @@ -121900,7 +121717,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N382), .CLK (ddrphy_clkin), - .D (_N60317)); + .D (_N58344)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_CE /* \mr1_ddr3[9] */ #( @@ -121911,7 +121728,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N382), .CLK (ddrphy_clkin), - .D (_N60426)); + .D (_N58439)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_CE /* \mr1_ddr3[10] */ #( @@ -121922,7 +121739,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N382), .CLK (ddrphy_clkin), - .D (_N60528)); + .D (_N58543)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_CE /* \mr1_ddr3[11] */ #( @@ -121933,7 +121750,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N382), .CLK (ddrphy_clkin), - .D (_N60641)); + .D (_N58653)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_CE /* \mr1_ddr3[12] */ #( @@ -121944,7 +121761,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N382), .CLK (ddrphy_clkin), - .D (_N60744)); + .D (_N58759)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_CE /* \mr1_ddr3[13] */ #( @@ -121955,7 +121772,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N382), .CLK (ddrphy_clkin), - .D (_N60867)); + .D (_N58877)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_CE /* \mr1_ddr3[14] */ #( @@ -121966,165 +121783,197 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N382), .CLK (ddrphy_clkin), - .D (_N60960)); + .D (_N58990)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 - GTP_LUT3 /* \mr1_ddr3[15:0]_0 */ #( - .INIT(8'b11100100)) + GTP_LUT5 /* \mr1_ddr3[15:0]_0 */ #( + .INIT(32'b11110000111100001110010011110000)) \mr1_ddr3[15:0]_0 ( - .Z (_N59497), - .I0 (_N59500), + .Z (_N57529), + .I0 (_N56942), .I1 (phy_addr[0]), - .I2 (phy_addr[30])); - // LUT = (~I0&I1)|(I0&I2) ; - - GTP_LUT4 /* \mr1_ddr3[15:0]_3 */ #( - .INIT(16'b1111111111111101)) - \mr1_ddr3[15:0]_3 ( - .Z (_N59500), - .I0 (phy_ba[0]), - .I1 (phy_ba[1]), - .I2 (phy_ba[2]), - .I3 (N18)); - // LUT = (~I0)|(I1)|(I2)|(I3) ; + .I2 (phy_addr[30]), + .I3 (phy_ba[0]), + .I4 (phy_ba[1])); + // LUT = (I2&~I3)|(I0&I2)|(I2&I4)|(~I0&I1&I3&~I4) ; - GTP_LUT3 /* \mr1_ddr3[15:0]_9 */ #( - .INIT(8'b11100100)) + GTP_LUT5 /* \mr1_ddr3[15:0]_9 */ #( + .INIT(32'b11110000111100001110010011110000)) \mr1_ddr3[15:0]_9 ( - .Z (_N59602), - .I0 (_N59500), - .I1 (phy_addr[1]), - .I2 (phy_addr[31])); - // LUT = (~I0&I1)|(I0&I2) ; - - GTP_LUT3 /* \mr1_ddr3[15:0]_165 */ #( - .INIT(8'b11100100)) - \mr1_ddr3[15:0]_165 ( - .Z (_N59714), - .I0 (_N59500), + .Z (_N57742), + .I0 (_N56942), .I1 (phy_addr[2]), - .I2 (phy_addr[32])); - // LUT = (~I0&I1)|(I0&I2) ; + .I2 (phy_addr[32]), + .I3 (phy_ba[0]), + .I4 (phy_ba[1])); + // LUT = (I2&~I3)|(I0&I2)|(I2&I4)|(~I0&I1&I3&~I4) ; - GTP_LUT3 /* \mr1_ddr3[15:0]_251 */ #( - .INIT(8'b11100100)) + GTP_LUT5 /* \mr1_ddr3[15:0]_251 */ #( + .INIT(32'b11110000111100001110010011110000)) \mr1_ddr3[15:0]_251 ( - .Z (_N59817), - .I0 (_N59500), + .Z (_N57841), + .I0 (_N56942), .I1 (phy_addr[3]), - .I2 (phy_addr[33])); - // LUT = (~I0&I1)|(I0&I2) ; + .I2 (phy_addr[33]), + .I3 (phy_ba[0]), + .I4 (phy_ba[1])); + // LUT = (I2&~I3)|(I0&I2)|(I2&I4)|(~I0&I1&I3&~I4) ; - GTP_LUT3 /* \mr1_ddr3[15:0]_338 */ #( - .INIT(8'b11100100)) - \mr1_ddr3[15:0]_338 ( - .Z (_N59912), - .I0 (_N59500), + GTP_LUT4 /* \mr1_ddr3[15:0]_411 */ #( + .INIT(16'b1111000011100100)) + \mr1_ddr3[15:0]_411 ( + .Z (_N58040), + .I0 (_N58045), .I1 (phy_addr[4]), - .I2 (phy_addr[34])); - // LUT = (~I0&I1)|(I0&I2) ; + .I2 (phy_addr[34]), + .I3 (phy_we_n[0])); + // LUT = (I0&I2)|(I2&I3)|(~I0&I1&~I3) ; - GTP_LUT3 /* \mr1_ddr3[15:0]_502 */ #( - .INIT(8'b11100100)) - \mr1_ddr3[15:0]_502 ( - .Z (_N60111), - .I0 (_N59500), - .I1 (phy_addr[6]), - .I2 (phy_addr[36])); - // LUT = (~I0&I1)|(I0&I2) ; + GTP_LUT3 /* \mr1_ddr3[15:0]_416_3 */ #( + .INIT(8'b11111110)) + \mr1_ddr3[15:0]_416_3 ( + .Z (_N58045), + .I0 (_N58048), + .I1 (phy_ba[1]), + .I2 (phy_ba[2])); + // LUT = (I0)|(I1)|(I2) ; - GTP_LUT3 /* \mr1_ddr3[15:0]_588 */ #( - .INIT(8'b11100100)) - \mr1_ddr3[15:0]_588 ( - .Z (_N60217), - .I0 (_N59500), - .I1 (phy_addr[7]), - .I2 (phy_addr[37])); - // LUT = (~I0&I1)|(I0&I2) ; + GTP_LUT3 /* \mr1_ddr3[15:0]_418_3 */ #( + .INIT(8'b11111110)) + \mr1_ddr3[15:0]_418_3 ( + .Z (_N58048), + .I0 (phy_cas_n[0]), + .I1 (phy_cs_n[0]), + .I2 (phy_ras_n[0])); + // LUT = (I0)|(I1)|(I2) ; - GTP_LUT3 /* \mr1_ddr3[15:0]_673 */ #( - .INIT(8'b11100100)) - \mr1_ddr3[15:0]_673 ( - .Z (_N60317), - .I0 (_N59500), + GTP_LUT5 /* \mr1_ddr3[15:0]_421 */ #( + .INIT(32'b11110000111100001110010011110000)) + \mr1_ddr3[15:0]_421 ( + .Z (_N58051), + .I0 (_N56942), + .I1 (phy_addr[5]), + .I2 (phy_addr[35]), + .I3 (phy_ba[0]), + .I4 (phy_ba[1])); + // LUT = (I2&~I3)|(I0&I2)|(I2&I4)|(~I0&I1&I3&~I4) ; + + GTP_LUT5 /* \mr1_ddr3[15:0]_505 */ #( + .INIT(32'b11110000111100001110010011110000)) + \mr1_ddr3[15:0]_505 ( + .Z (_N58143), + .I0 (_N56942), + .I1 (phy_addr[6]), + .I2 (phy_addr[36]), + .I3 (phy_ba[0]), + .I4 (phy_ba[1])); + // LUT = (I2&~I3)|(I0&I2)|(I2&I4)|(~I0&I1&I3&~I4) ; + + GTP_LUT5 /* \mr1_ddr3[15:0]_592 */ #( + .INIT(32'b11110000111100001110010011110000)) + \mr1_ddr3[15:0]_592 ( + .Z (_N58245), + .I0 (_N56942), + .I1 (phy_addr[7]), + .I2 (phy_addr[37]), + .I3 (phy_ba[0]), + .I4 (phy_ba[1])); + // LUT = (I2&~I3)|(I0&I2)|(I2&I4)|(~I0&I1&I3&~I4) ; + + GTP_LUT5 /* \mr1_ddr3[15:0]_678 */ #( + .INIT(32'b11110000111100001110010011110000)) + \mr1_ddr3[15:0]_678 ( + .Z (_N58344), + .I0 (_N56942), .I1 (phy_addr[8]), - .I2 (phy_addr[38])); - // LUT = (~I0&I1)|(I0&I2) ; - - GTP_LUT3 /* \mr1_ddr3[15:0]_760 */ #( - .INIT(8'b11100100)) - \mr1_ddr3[15:0]_760 ( - .Z (_N60426), - .I0 (_N59500), + .I2 (phy_addr[38]), + .I3 (phy_ba[0]), + .I4 (phy_ba[1])); + // LUT = (I2&~I3)|(I0&I2)|(I2&I4)|(~I0&I1&I3&~I4) ; + + GTP_LUT5 /* \mr1_ddr3[15:0]_765 */ #( + .INIT(32'b11110000111100001110010011110000)) + \mr1_ddr3[15:0]_765 ( + .Z (_N58439), + .I0 (_N56942), .I1 (phy_addr[9]), - .I2 (phy_addr[39])); - // LUT = (~I0&I1)|(I0&I2) ; - - GTP_LUT3 /* \mr1_ddr3[15:0]_847 */ #( - .INIT(8'b11100100)) - \mr1_ddr3[15:0]_847 ( - .Z (_N60528), - .I0 (_N59500), + .I2 (phy_addr[39]), + .I3 (phy_ba[0]), + .I4 (phy_ba[1])); + // LUT = (I2&~I3)|(I0&I2)|(I2&I4)|(~I0&I1&I3&~I4) ; + + GTP_LUT5 /* \mr1_ddr3[15:0]_851 */ #( + .INIT(32'b11110000111100001110010011110000)) + \mr1_ddr3[15:0]_851 ( + .Z (_N58543), + .I0 (_N56942), .I1 (phy_addr[10]), - .I2 (phy_addr[40])); - // LUT = (~I0&I1)|(I0&I2) ; - - GTP_LUT3 /* \mr1_ddr3[15:0]_934 */ #( - .INIT(8'b11100100)) - \mr1_ddr3[15:0]_934 ( - .Z (_N60641), - .I0 (_N59500), + .I2 (phy_addr[40]), + .I3 (phy_ba[0]), + .I4 (phy_ba[1])); + // LUT = (I2&~I3)|(I0&I2)|(I2&I4)|(~I0&I1&I3&~I4) ; + + GTP_LUT5 /* \mr1_ddr3[15:0]_938 */ #( + .INIT(32'b11110000111100001110010011110000)) + \mr1_ddr3[15:0]_938 ( + .Z (_N58653), + .I0 (_N56942), .I1 (phy_addr[11]), - .I2 (phy_addr[41])); - // LUT = (~I0&I1)|(I0&I2) ; - - GTP_LUT3 /* \mr1_ddr3[15:0]_1020 */ #( - .INIT(8'b11100100)) - \mr1_ddr3[15:0]_1020 ( - .Z (_N60744), - .I0 (_N59500), + .I2 (phy_addr[41]), + .I3 (phy_ba[0]), + .I4 (phy_ba[1])); + // LUT = (I2&~I3)|(I0&I2)|(I2&I4)|(~I0&I1&I3&~I4) ; + + GTP_LUT5 /* \mr1_ddr3[15:0]_1024 */ #( + .INIT(32'b11110000111100001110010011110000)) + \mr1_ddr3[15:0]_1024 ( + .Z (_N58759), + .I0 (_N56942), .I1 (phy_addr[12]), - .I2 (phy_addr[41])); - // LUT = (~I0&I1)|(I0&I2) ; - - GTP_LUT3 /* \mr1_ddr3[15:0]_1107 */ #( - .INIT(8'b11100100)) - \mr1_ddr3[15:0]_1107 ( - .Z (_N60867), - .I0 (_N59500), + .I2 (phy_addr[41]), + .I3 (phy_ba[0]), + .I4 (phy_ba[1])); + // LUT = (I2&~I3)|(I0&I2)|(I2&I4)|(~I0&I1&I3&~I4) ; + + GTP_LUT5 /* \mr1_ddr3[15:0]_1111 */ #( + .INIT(32'b11110000111100001110010011110000)) + \mr1_ddr3[15:0]_1111 ( + .Z (_N58877), + .I0 (_N56942), .I1 (phy_addr[13]), - .I2 (phy_addr[41])); - // LUT = (~I0&I1)|(I0&I2) ; - - GTP_LUT3 /* \mr1_ddr3[15:0]_1192 */ #( - .INIT(8'b11100100)) - \mr1_ddr3[15:0]_1192 ( - .Z (_N60960), - .I0 (_N59500), + .I2 (phy_addr[41]), + .I3 (phy_ba[0]), + .I4 (phy_ba[1])); + // LUT = (I2&~I3)|(I0&I2)|(I2&I4)|(~I0&I1&I3&~I4) ; + + GTP_LUT5 /* \mr1_ddr3[15:0]_1197 */ #( + .INIT(32'b11110000111100001110010011110000)) + \mr1_ddr3[15:0]_1197 ( + .Z (_N58990), + .I0 (_N56942), .I1 (phy_addr[14]), - .I2 (phy_addr[41])); - // LUT = (~I0&I1)|(I0&I2) ; + .I2 (phy_addr[41]), + .I3 (phy_ba[0]), + .I4 (phy_ba[1])); + // LUT = (I2&~I3)|(I0&I2)|(I2&I4)|(~I0&I1&I3&~I4) ; - GTP_LUT4 /* \mr1_ddr3[15:0]_1278 */ #( - .INIT(16'b1111111111111110)) - \mr1_ddr3[15:0]_1278 ( - .Z (N18), - .I0 (phy_cas_n[0]), - .I1 (phy_cs_n[0]), - .I2 (phy_ras_n[0]), - .I3 (phy_we_n[0])); - // LUT = (I0)|(I1)|(I2)|(I3) ; + GTP_LUT2 /* \mr1_ddr3[15:0]_1285 */ #( + .INIT(4'b1011)) + \mr1_ddr3[15:0]_1285 ( + .Z (_N97038), + .I0 (phy_ba[0]), + .I1 (phy_ba[1])); + // LUT = (~I1)|(I0) ; - GTP_LUT5 /* \mr1_ddr3[15:0]_1294 */ #( - .INIT(32'b11001100110011001100110011001010)) - \mr1_ddr3[15:0]_1294 ( - .Z (_N60056), - .I0 (phy_addr[5]), - .I1 (phy_addr[35]), - .I2 (phy_ba[1]), - .I3 (phy_ba[2]), - .I4 (N18)); - // LUT = (I1&I2)|(I1&I3)|(I1&I4)|(I0&~I2&~I3&~I4) ; + GTP_LUT4 /* \mr1_ddr3[15:0]_1308 */ #( + .INIT(16'b1111000011100100)) + \mr1_ddr3[15:0]_1308 ( + .Z (_N57731), + .I0 (_N58045), + .I1 (phy_addr[1]), + .I2 (phy_addr[31]), + .I3 (phy_we_n[0])); + // LUT = (I0&I2)|(I2&I3)|(~I0&I1&~I3) ; GTP_DFF_CE /* \mr2_ddr3[0] */ #( .GRS_EN("TRUE"), @@ -122134,7 +121983,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N457), .CLK (ddrphy_clkin), - .D (_N55654)); + .D (_N53492)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_CE /* \mr2_ddr3[1] */ #( @@ -122145,7 +121994,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N457), .CLK (ddrphy_clkin), - .D (_N55816)); + .D (_N53605)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_CE /* \mr2_ddr3[2] */ #( @@ -122156,7 +122005,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N457), .CLK (ddrphy_clkin), - .D (_N55850)); + .D (_N53705)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_CE /* \mr2_ddr3[3] */ #( @@ -122167,7 +122016,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N457), .CLK (ddrphy_clkin), - .D (_N55955)); + .D (_N53823)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_CE /* \mr2_ddr3[4] */ #( @@ -122178,7 +122027,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N457), .CLK (ddrphy_clkin), - .D (_N56052)); + .D (_N53924)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_CE /* \mr2_ddr3[5] */ #( @@ -122189,7 +122038,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N457), .CLK (ddrphy_clkin), - .D (_N56168)); + .D (_N54046)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_CE /* \mr2_ddr3[6] */ #( @@ -122200,7 +122049,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N457), .CLK (ddrphy_clkin), - .D (_N56277)); + .D (_N54163)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_CE /* \mr2_ddr3[7] */ #( @@ -122211,7 +122060,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N457), .CLK (ddrphy_clkin), - .D (_N56406)); + .D (_N54312)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_CE /* \mr2_ddr3[8] */ #( @@ -122222,7 +122071,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N457), .CLK (ddrphy_clkin), - .D (_N56462)); + .D (_N54367)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_CE /* \mr2_ddr3[9] */ #( @@ -122233,7 +122082,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N457), .CLK (ddrphy_clkin), - .D (_N56572)); + .D (_N54476)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_CE /* \mr2_ddr3[10] */ #( @@ -122244,7 +122093,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N457), .CLK (ddrphy_clkin), - .D (_N56674)); + .D (_N54592)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_CE /* \mr2_ddr3[11] */ #( @@ -122255,7 +122104,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N457), .CLK (ddrphy_clkin), - .D (_N56792)); + .D (_N54705)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_CE /* \mr2_ddr3[12] */ #( @@ -122266,7 +122115,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N457), .CLK (ddrphy_clkin), - .D (_N56894)); + .D (_N54913)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_CE /* \mr2_ddr3[13] */ #( @@ -122277,7 +122126,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N457), .CLK (ddrphy_clkin), - .D (_N56996)); + .D (_N54922)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_CE /* \mr2_ddr3[14] */ #( @@ -122288,177 +122137,158 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N457), .CLK (ddrphy_clkin), - .D (_N57173)); + .D (_N55028)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_LUT3 /* \mr2_ddr3[15:0]_0 */ #( .INIT(8'b11001010)) \mr2_ddr3[15:0]_0 ( - .Z (_N55654), + .Z (_N53492), .I0 (phy_addr[0]), .I1 (phy_addr[30]), - .I2 (_N55657)); + .I2 (_N53495)); // LUT = (I0&~I2)|(I1&I2) ; - GTP_LUT4 /* \mr2_ddr3[15:0]_3 */ #( - .INIT(16'b1111111111111011)) + GTP_LUT5 /* \mr2_ddr3[15:0]_3 */ #( + .INIT(32'b11111111111111111111111111101111)) \mr2_ddr3[15:0]_3 ( - .Z (_N55657), - .I0 (phy_ba[0]), - .I1 (phy_ba[1]), - .I2 (phy_ba[2]), - .I3 (N18)); - // LUT = (~I1)|(I0)|(I2)|(I3) ; + .Z (_N53495), + .I0 (_N58048), + .I1 (phy_ba[0]), + .I2 (phy_ba[1]), + .I3 (phy_ba[2]), + .I4 (phy_we_n[0])); + // LUT = (~I2)|(I0)|(I1)|(I3)|(I4) ; - GTP_LUT5 /* \mr2_ddr3[15:0]_9 */ #( - .INIT(32'b11001100110011001100110011001010)) + GTP_LUT3 /* \mr2_ddr3[15:0]_9 */ #( + .INIT(8'b11001010)) \mr2_ddr3[15:0]_9 ( - .Z (_N55816), + .Z (_N53605), .I0 (phy_addr[1]), .I1 (phy_addr[31]), - .I2 (phy_ba[0]), - .I3 (phy_ba[2]), - .I4 (N18)); - // LUT = (I1&I2)|(I1&I3)|(I1&I4)|(I0&~I2&~I3&~I4) ; + .I2 (_N53495)); + // LUT = (I0&~I2)|(I1&I2) ; - GTP_LUT3 /* \mr2_ddr3[15:0]_155 */ #( + GTP_LUT3 /* \mr2_ddr3[15:0]_168 */ #( .INIT(8'b11001010)) - \mr2_ddr3[15:0]_155 ( - .Z (_N55850), + \mr2_ddr3[15:0]_168 ( + .Z (_N53705), .I0 (phy_addr[2]), .I1 (phy_addr[32]), - .I2 (_N55657)); + .I2 (_N53495)); // LUT = (I0&~I2)|(I1&I2) ; - GTP_LUT3 /* \mr2_ddr3[15:0]_242 */ #( + GTP_LUT3 /* \mr2_ddr3[15:0]_254 */ #( .INIT(8'b11001010)) - \mr2_ddr3[15:0]_242 ( - .Z (_N55955), + \mr2_ddr3[15:0]_254 ( + .Z (_N53823), .I0 (phy_addr[3]), .I1 (phy_addr[33]), - .I2 (_N55657)); + .I2 (_N53495)); // LUT = (I0&~I2)|(I1&I2) ; - GTP_LUT3 /* \mr2_ddr3[15:0]_328 */ #( + GTP_LUT3 /* \mr2_ddr3[15:0]_339 */ #( .INIT(8'b11001010)) - \mr2_ddr3[15:0]_328 ( - .Z (_N56052), + \mr2_ddr3[15:0]_339 ( + .Z (_N53924), .I0 (phy_addr[4]), .I1 (phy_addr[34]), - .I2 (_N55657)); + .I2 (_N53495)); // LUT = (I0&~I2)|(I1&I2) ; - GTP_LUT3 /* \mr2_ddr3[15:0]_414 */ #( + GTP_LUT3 /* \mr2_ddr3[15:0]_425 */ #( .INIT(8'b11001010)) - \mr2_ddr3[15:0]_414 ( - .Z (_N56168), + \mr2_ddr3[15:0]_425 ( + .Z (_N54046), .I0 (phy_addr[5]), .I1 (phy_addr[35]), - .I2 (_N55657)); + .I2 (_N53495)); // LUT = (I0&~I2)|(I1&I2) ; - GTP_LUT3 /* \mr2_ddr3[15:0]_500 */ #( + GTP_LUT3 /* \mr2_ddr3[15:0]_512 */ #( .INIT(8'b11001010)) - \mr2_ddr3[15:0]_500 ( - .Z (_N56277), + \mr2_ddr3[15:0]_512 ( + .Z (_N54163), .I0 (phy_addr[6]), .I1 (phy_addr[36]), - .I2 (_N55657)); + .I2 (_N53495)); // LUT = (I0&~I2)|(I1&I2) ; - GTP_LUT5 /* \mr2_ddr3[15:0]_622_3 */ #( - .INIT(32'b11111111111111111111111111111011)) - \mr2_ddr3[15:0]_622_3 ( - .Z (_N56412), - .I0 (phy_ba[0]), - .I1 (phy_ba[1]), - .I2 (phy_cas_n[0]), - .I3 (phy_cs_n[0]), - .I4 (phy_ras_n[0])); - // LUT = (~I1)|(I0)|(I2)|(I3)|(I4) ; - - GTP_LUT3 /* \mr2_ddr3[15:0]_668 */ #( + GTP_LUT3 /* \mr2_ddr3[15:0]_681 */ #( .INIT(8'b11001010)) - \mr2_ddr3[15:0]_668 ( - .Z (_N56462), + \mr2_ddr3[15:0]_681 ( + .Z (_N54367), .I0 (phy_addr[8]), .I1 (phy_addr[38]), - .I2 (_N55657)); + .I2 (_N53495)); // LUT = (I0&~I2)|(I1&I2) ; - GTP_LUT3 /* \mr2_ddr3[15:0]_755 */ #( + GTP_LUT3 /* \mr2_ddr3[15:0]_767 */ #( .INIT(8'b11001010)) - \mr2_ddr3[15:0]_755 ( - .Z (_N56572), + \mr2_ddr3[15:0]_767 ( + .Z (_N54476), .I0 (phy_addr[9]), .I1 (phy_addr[39]), - .I2 (_N55657)); + .I2 (_N53495)); // LUT = (I0&~I2)|(I1&I2) ; - GTP_LUT3 /* \mr2_ddr3[15:0]_842 */ #( + GTP_LUT3 /* \mr2_ddr3[15:0]_853 */ #( .INIT(8'b11001010)) - \mr2_ddr3[15:0]_842 ( - .Z (_N56674), + \mr2_ddr3[15:0]_853 ( + .Z (_N54592), .I0 (phy_addr[10]), .I1 (phy_addr[40]), - .I2 (_N55657)); + .I2 (_N53495)); // LUT = (I0&~I2)|(I1&I2) ; - GTP_LUT3 /* \mr2_ddr3[15:0]_928 */ #( + GTP_LUT3 /* \mr2_ddr3[15:0]_939 */ #( .INIT(8'b11001010)) - \mr2_ddr3[15:0]_928 ( - .Z (_N56792), + \mr2_ddr3[15:0]_939 ( + .Z (_N54705), .I0 (phy_addr[11]), .I1 (phy_addr[41]), - .I2 (_N55657)); + .I2 (_N53495)); // LUT = (I0&~I2)|(I1&I2) ; - GTP_LUT3 /* \mr2_ddr3[15:0]_1012 */ #( - .INIT(8'b11001010)) - \mr2_ddr3[15:0]_1012 ( - .Z (_N56894), - .I0 (phy_addr[12]), - .I1 (phy_addr[41]), - .I2 (_N55657)); - // LUT = (I0&~I2)|(I1&I2) ; + GTP_LUT5 /* \mr2_ddr3[15:0]_1100 */ #( + .INIT(32'b11110000111100001111000011100100)) + \mr2_ddr3[15:0]_1100 ( + .Z (_N54913), + .I0 (_N58048), + .I1 (phy_addr[12]), + .I2 (phy_addr[41]), + .I3 (phy_ba[2]), + .I4 (phy_we_n[0])); + // LUT = (I0&I2)|(I2&I3)|(I2&I4)|(~I0&I1&~I3&~I4) ; - GTP_LUT3 /* \mr2_ddr3[15:0]_1099 */ #( + GTP_LUT3 /* \mr2_ddr3[15:0]_1108 */ #( .INIT(8'b11001010)) - \mr2_ddr3[15:0]_1099 ( - .Z (_N56996), + \mr2_ddr3[15:0]_1108 ( + .Z (_N54922), .I0 (phy_addr[13]), .I1 (phy_addr[41]), - .I2 (_N55657)); + .I2 (_N53495)); // LUT = (I0&~I2)|(I1&I2) ; - GTP_LUT5 /* \mr2_ddr3[15:0]_1237 */ #( - .INIT(32'b11001100110011001100110011001010)) - \mr2_ddr3[15:0]_1237 ( - .Z (_N57173), + GTP_LUT3 /* \mr2_ddr3[15:0]_1195 */ #( + .INIT(8'b11001010)) + \mr2_ddr3[15:0]_1195 ( + .Z (_N55028), .I0 (phy_addr[14]), .I1 (phy_addr[41]), - .I2 (phy_ba[0]), - .I3 (phy_ba[2]), - .I4 (N18)); - // LUT = (I1&I2)|(I1&I3)|(I1&I4)|(I0&~I2&~I3&~I4) ; - - GTP_LUT2 /* \mr2_ddr3[15:0]_1268 */ #( - .INIT(4'b1110)) - \mr2_ddr3[15:0]_1268 ( - .Z (_N96265), - .I0 (phy_ba[2]), - .I1 (N18)); - // LUT = (I0)|(I1) ; + .I2 (_N53495)); + // LUT = (I0&~I2)|(I1&I2) ; - GTP_LUT4 /* \mr2_ddr3[15:0]_1269 */ #( - .INIT(16'b1111000011100100)) - \mr2_ddr3[15:0]_1269 ( - .Z (_N56406), - .I0 (_N56412), + GTP_LUT5 /* \mr2_ddr3[15:0]_1288 */ #( + .INIT(32'b11110000111100001111000011100100)) + \mr2_ddr3[15:0]_1288 ( + .Z (_N54312), + .I0 (_N58048), .I1 (phy_addr[7]), .I2 (phy_addr[37]), - .I3 (phy_we_n[0])); - // LUT = (I0&I2)|(I2&I3)|(~I0&I1&~I3) ; + .I3 (phy_we_n[0]), + .I4 (_N97038)); + // LUT = (I0&I2)|(I2&I3)|(I2&I4)|(~I0&I1&~I3&~I4) ; GTP_DFF_CE /* \mr3_ddr3[0] */ #( .GRS_EN("TRUE"), @@ -122468,7 +122298,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N532), .CLK (ddrphy_clkin), - .D (_N57213)); + .D (_N55144)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_CE /* \mr3_ddr3[1] */ #( @@ -122479,7 +122309,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N532), .CLK (ddrphy_clkin), - .D (_N57314)); + .D (_N55238)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_CE /* \mr3_ddr3[2] */ #( @@ -122490,7 +122320,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N532), .CLK (ddrphy_clkin), - .D (_N57475)); + .D (_N55353)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_CE /* \mr3_ddr3[3] */ #( @@ -122501,7 +122331,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N532), .CLK (ddrphy_clkin), - .D (_N57585)); + .D (_N55469)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_CE /* \mr3_ddr3[4] */ #( @@ -122512,7 +122342,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N532), .CLK (ddrphy_clkin), - .D (_N57630)); + .D (_N55577)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_CE /* \mr3_ddr3[5] */ #( @@ -122523,7 +122353,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N532), .CLK (ddrphy_clkin), - .D (_N57742)); + .D (_N55682)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_CE /* \mr3_ddr3[6] */ #( @@ -122534,7 +122364,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N532), .CLK (ddrphy_clkin), - .D (_N57858)); + .D (_N55803)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_CE /* \mr3_ddr3[7] */ #( @@ -122545,7 +122375,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N532), .CLK (ddrphy_clkin), - .D (_N57964)); + .D (_N55903)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_CE /* \mr3_ddr3[8] */ #( @@ -122556,7 +122386,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N532), .CLK (ddrphy_clkin), - .D (_N58069)); + .D (_N56007)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_CE /* \mr3_ddr3[9] */ #( @@ -122567,7 +122397,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N532), .CLK (ddrphy_clkin), - .D (_N58264)); + .D (_N56131)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_CE /* \mr3_ddr3[10] */ #( @@ -122578,7 +122408,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N532), .CLK (ddrphy_clkin), - .D (_N58274)); + .D (_N56225)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_CE /* \mr3_ddr3[11] */ #( @@ -122589,7 +122419,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N532), .CLK (ddrphy_clkin), - .D (_N58384)); + .D (_N56340)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_CE /* \mr3_ddr3[12] */ #( @@ -122600,7 +122430,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N532), .CLK (ddrphy_clkin), - .D (_N58492)); + .D (_N56440)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_CE /* \mr3_ddr3[13] */ #( @@ -122611,7 +122441,7 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N532), .CLK (ddrphy_clkin), - .D (_N58585)); + .D (_N56601)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_DFF_CE /* \mr3_ddr3[14] */ #( @@ -122622,159 +122452,164 @@ module ipsxb_ddrphy_info_v1_0 .C (N4), .CE (N532), .CLK (ddrphy_clkin), - .D (_N58693)); + .D (_N56633)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_info_v1_0.vp:177 GTP_LUT3 /* \mr3_ddr3[15:0]_0 */ #( - .INIT(8'b11100100)) + .INIT(8'b11001010)) \mr3_ddr3[15:0]_0 ( - .Z (_N57213), - .I0 (_N57216), - .I1 (phy_addr[0]), - .I2 (phy_addr[30])); - // LUT = (~I0&I1)|(I0&I2) ; + .Z (_N55144), + .I0 (phy_addr[0]), + .I1 (phy_addr[30]), + .I2 (_N55147)); + // LUT = (I0&~I2)|(I1&I2) ; - GTP_LUT4 /* \mr3_ddr3[15:0]_3 */ #( - .INIT(16'b1111111111110111)) + GTP_LUT5 /* \mr3_ddr3[15:0]_3 */ #( + .INIT(32'b11111111111111111111111110111111)) \mr3_ddr3[15:0]_3 ( - .Z (_N57216), - .I0 (phy_ba[0]), - .I1 (phy_ba[1]), - .I2 (phy_ba[2]), - .I3 (N18)); - // LUT = (~I1)|(~I0)|(I2)|(I3) ; + .Z (_N55147), + .I0 (_N58048), + .I1 (phy_ba[0]), + .I2 (phy_ba[1]), + .I3 (phy_ba[2]), + .I4 (phy_we_n[0])); + // LUT = (~I2)|(~I1)|(I0)|(I3)|(I4) ; GTP_LUT3 /* \mr3_ddr3[15:0]_9 */ #( - .INIT(8'b11100100)) + .INIT(8'b11001010)) \mr3_ddr3[15:0]_9 ( - .Z (_N57314), - .I0 (_N57216), - .I1 (phy_addr[1]), - .I2 (phy_addr[31])); - // LUT = (~I0&I1)|(I0&I2) ; + .Z (_N55238), + .I0 (phy_addr[1]), + .I1 (phy_addr[31]), + .I2 (_N55147)); + // LUT = (I0&~I2)|(I1&I2) ; - GTP_LUT5 /* \mr3_ddr3[15:0]_195 */ #( - .INIT(32'b11001100110011001100110010101100)) - \mr3_ddr3[15:0]_195 ( - .Z (_N57475), + GTP_LUT3 /* \mr3_ddr3[15:0]_164 */ #( + .INIT(8'b11001010)) + \mr3_ddr3[15:0]_164 ( + .Z (_N55353), .I0 (phy_addr[2]), .I1 (phy_addr[32]), - .I2 (phy_ba[1]), - .I3 (phy_ba[2]), - .I4 (N18)); - // LUT = (I1&~I2)|(I1&I3)|(I1&I4)|(I0&I2&~I3&~I4) ; + .I2 (_N55147)); + // LUT = (I0&~I2)|(I1&I2) ; - GTP_LUT5 /* \mr3_ddr3[15:0]_287 */ #( - .INIT(32'b11001100110011001010110011001100)) - \mr3_ddr3[15:0]_287 ( - .Z (_N57585), + GTP_LUT3 /* \mr3_ddr3[15:0]_249 */ #( + .INIT(8'b11001010)) + \mr3_ddr3[15:0]_249 ( + .Z (_N55469), .I0 (phy_addr[3]), .I1 (phy_addr[33]), - .I2 (phy_ba[0]), - .I3 (phy_ba[1]), - .I4 (N18)); - // LUT = (I1&~I3)|(I1&~I2)|(I1&I4)|(I0&I2&I3&~I4) ; + .I2 (_N55147)); + // LUT = (I0&~I2)|(I1&I2) ; - GTP_LUT3 /* \mr3_ddr3[15:0]_328 */ #( - .INIT(8'b11100100)) - \mr3_ddr3[15:0]_328 ( - .Z (_N57630), - .I0 (_N57216), - .I1 (phy_addr[4]), - .I2 (phy_addr[34])); - // LUT = (~I0&I1)|(I0&I2) ; + GTP_LUT3 /* \mr3_ddr3[15:0]_333 */ #( + .INIT(8'b11001010)) + \mr3_ddr3[15:0]_333 ( + .Z (_N55577), + .I0 (phy_addr[4]), + .I1 (phy_addr[34]), + .I2 (_N55147)); + // LUT = (I0&~I2)|(I1&I2) ; - GTP_LUT3 /* \mr3_ddr3[15:0]_415 */ #( - .INIT(8'b11100100)) - \mr3_ddr3[15:0]_415 ( - .Z (_N57742), - .I0 (_N57216), - .I1 (phy_addr[5]), - .I2 (phy_addr[35])); - // LUT = (~I0&I1)|(I0&I2) ; + GTP_LUT3 /* \mr3_ddr3[15:0]_420 */ #( + .INIT(8'b11001010)) + \mr3_ddr3[15:0]_420 ( + .Z (_N55682), + .I0 (phy_addr[5]), + .I1 (phy_addr[35]), + .I2 (_N55147)); + // LUT = (I0&~I2)|(I1&I2) ; - GTP_LUT3 /* \mr3_ddr3[15:0]_502 */ #( - .INIT(8'b11100100)) - \mr3_ddr3[15:0]_502 ( - .Z (_N57858), - .I0 (_N57216), - .I1 (phy_addr[6]), - .I2 (phy_addr[36])); - // LUT = (~I0&I1)|(I0&I2) ; + GTP_LUT3 /* \mr3_ddr3[15:0]_507 */ #( + .INIT(8'b11001010)) + \mr3_ddr3[15:0]_507 ( + .Z (_N55803), + .I0 (phy_addr[6]), + .I1 (phy_addr[36]), + .I2 (_N55147)); + // LUT = (I0&~I2)|(I1&I2) ; - GTP_LUT3 /* \mr3_ddr3[15:0]_588 */ #( - .INIT(8'b11100100)) - \mr3_ddr3[15:0]_588 ( - .Z (_N57964), - .I0 (_N57216), - .I1 (phy_addr[7]), - .I2 (phy_addr[37])); - // LUT = (~I0&I1)|(I0&I2) ; + GTP_LUT3 /* \mr3_ddr3[15:0]_594 */ #( + .INIT(8'b11001010)) + \mr3_ddr3[15:0]_594 ( + .Z (_N55903), + .I0 (phy_addr[7]), + .I1 (phy_addr[37]), + .I2 (_N55147)); + // LUT = (I0&~I2)|(I1&I2) ; - GTP_LUT3 /* \mr3_ddr3[15:0]_673 */ #( - .INIT(8'b11100100)) - \mr3_ddr3[15:0]_673 ( - .Z (_N58069), - .I0 (_N57216), - .I1 (phy_addr[8]), - .I2 (phy_addr[38])); - // LUT = (~I0&I1)|(I0&I2) ; + GTP_LUT3 /* \mr3_ddr3[15:0]_679 */ #( + .INIT(8'b11001010)) + \mr3_ddr3[15:0]_679 ( + .Z (_N56007), + .I0 (phy_addr[8]), + .I1 (phy_addr[38]), + .I2 (_N55147)); + // LUT = (I0&~I2)|(I1&I2) ; - GTP_LUT5 /* \mr3_ddr3[15:0]_832 */ #( - .INIT(32'b11001100110011001010110011001100)) - \mr3_ddr3[15:0]_832 ( - .Z (_N58264), + GTP_LUT3 /* \mr3_ddr3[15:0]_765 */ #( + .INIT(8'b11001010)) + \mr3_ddr3[15:0]_765 ( + .Z (_N56131), .I0 (phy_addr[9]), .I1 (phy_addr[39]), + .I2 (_N55147)); + // LUT = (I0&~I2)|(I1&I2) ; + + GTP_LUT3 /* \mr3_ddr3[15:0]_851 */ #( + .INIT(8'b11001010)) + \mr3_ddr3[15:0]_851 ( + .Z (_N56225), + .I0 (phy_addr[10]), + .I1 (phy_addr[40]), + .I2 (_N55147)); + // LUT = (I0&~I2)|(I1&I2) ; + + GTP_LUT3 /* \mr3_ddr3[15:0]_938 */ #( + .INIT(8'b11001010)) + \mr3_ddr3[15:0]_938 ( + .Z (_N56340), + .I0 (phy_addr[11]), + .I1 (phy_addr[41]), + .I2 (_N55147)); + // LUT = (I0&~I2)|(I1&I2) ; + + GTP_LUT3 /* \mr3_ddr3[15:0]_1019 */ #( + .INIT(8'b11001010)) + \mr3_ddr3[15:0]_1019 ( + .Z (_N56440), + .I0 (phy_addr[12]), + .I1 (phy_addr[41]), + .I2 (_N55147)); + // LUT = (I0&~I2)|(I1&I2) ; + + GTP_LUT5 /* \mr3_ddr3[15:0]_1156 */ #( + .INIT(32'b11001100110011001010110011001100)) + \mr3_ddr3[15:0]_1156 ( + .Z (_N56601), + .I0 (phy_addr[13]), + .I1 (phy_addr[41]), .I2 (phy_ba[0]), .I3 (phy_ba[1]), .I4 (N18)); // LUT = (I1&~I3)|(I1&~I2)|(I1&I4)|(I0&I2&I3&~I4) ; - GTP_LUT3 /* \mr3_ddr3[15:0]_841 */ #( - .INIT(8'b11100100)) - \mr3_ddr3[15:0]_841 ( - .Z (_N58274), - .I0 (_N57216), - .I1 (phy_addr[10]), - .I2 (phy_addr[40])); - // LUT = (~I0&I1)|(I0&I2) ; - - GTP_LUT3 /* \mr3_ddr3[15:0]_927 */ #( - .INIT(8'b11100100)) - \mr3_ddr3[15:0]_927 ( - .Z (_N58384), - .I0 (_N57216), - .I1 (phy_addr[11]), - .I2 (phy_addr[41])); - // LUT = (~I0&I1)|(I0&I2) ; - - GTP_LUT3 /* \mr3_ddr3[15:0]_1014 */ #( - .INIT(8'b11100100)) - \mr3_ddr3[15:0]_1014 ( - .Z (_N58492), - .I0 (_N57216), - .I1 (phy_addr[12]), - .I2 (phy_addr[41])); - // LUT = (~I0&I1)|(I0&I2) ; - - GTP_LUT3 /* \mr3_ddr3[15:0]_1098 */ #( - .INIT(8'b11100100)) - \mr3_ddr3[15:0]_1098 ( - .Z (_N58585), - .I0 (_N57216), - .I1 (phy_addr[13]), - .I2 (phy_addr[41])); - // LUT = (~I0&I1)|(I0&I2) ; + GTP_LUT2 /* \mr3_ddr3[15:0]_1161 */ #( + .INIT(4'b1110)) + \mr3_ddr3[15:0]_1161 ( + .Z (N18), + .I0 (_N58048), + .I1 (phy_we_n[0])); + // LUT = (I0)|(I1) ; - GTP_LUT3 /* \mr3_ddr3[15:0]_1183 */ #( - .INIT(8'b11100100)) - \mr3_ddr3[15:0]_1183 ( - .Z (_N58693), - .I0 (_N57216), - .I1 (phy_addr[14]), - .I2 (phy_addr[41])); - // LUT = (~I0&I1)|(I0&I2) ; + GTP_LUT3 /* \mr3_ddr3[15:0]_1185 */ #( + .INIT(8'b11001010)) + \mr3_ddr3[15:0]_1185 ( + .Z (_N56633), + .I0 (phy_addr[14]), + .I1 (phy_addr[41]), + .I2 (_N55147)); + // LUT = (I0&~I2)|(I1&I2) ; endmodule @@ -122791,28 +122626,29 @@ module ipsxb_ddrphy_rst_debounce_v1_0 wire [18:0] N11; wire N43; wire [18:0] N44; - wire _N14585; - wire _N14586; - wire _N14587; - wire _N14588; - wire _N14589; - wire _N14590; - wire _N14591; - wire _N14592; - wire _N14593; - wire _N14594; - wire _N14595; - wire _N14596; - wire _N14597; - wire _N14598; - wire _N14599; - wire _N14600; - wire _N14601; - wire _N103471; - wire _N106328; - wire _N106332; - wire _N106336; - wire _N106339; + wire _N14543; + wire _N14544; + wire _N14545; + wire _N14546; + wire _N14547; + wire _N14548; + wire _N14549; + wire _N14550; + wire _N14551; + wire _N14552; + wire _N14553; + wire _N14554; + wire _N14555; + wire _N14556; + wire _N14557; + wire _N14558; + wire _N14559; + wire _N104283; + wire _N107146; + wire _N107150; + wire _N107154; + wire _N107157; + wire _N107157_cpy; wire [18:0] rise_cnt; wire signal_b_ff; wire signal_b_neg; @@ -122834,7 +122670,7 @@ module ipsxb_ddrphy_rst_debounce_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_1_1 ( - .COUT (_N14585), + .COUT (_N14543), .Z (N11[1]), .CIN (), .I0 (rise_cnt[0]), @@ -122854,9 +122690,9 @@ module ipsxb_ddrphy_rst_debounce_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_1_2 ( - .COUT (_N14586), + .COUT (_N14544), .Z (N11[2]), - .CIN (_N14585), + .CIN (_N14543), .I0 (rise_cnt[0]), .I1 (rise_cnt[1]), .I2 (rise_cnt[2]), @@ -122874,9 +122710,9 @@ module ipsxb_ddrphy_rst_debounce_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_1_3 ( - .COUT (_N14587), + .COUT (_N14545), .Z (N11[3]), - .CIN (_N14586), + .CIN (_N14544), .I0 (), .I1 (rise_cnt[3]), .I2 (), @@ -122894,9 +122730,9 @@ module ipsxb_ddrphy_rst_debounce_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_1_4 ( - .COUT (_N14588), + .COUT (_N14546), .Z (N11[4]), - .CIN (_N14587), + .CIN (_N14545), .I0 (), .I1 (rise_cnt[4]), .I2 (), @@ -122914,9 +122750,9 @@ module ipsxb_ddrphy_rst_debounce_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_1_5 ( - .COUT (_N14589), + .COUT (_N14547), .Z (N11[5]), - .CIN (_N14588), + .CIN (_N14546), .I0 (), .I1 (rise_cnt[5]), .I2 (), @@ -122934,9 +122770,9 @@ module ipsxb_ddrphy_rst_debounce_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_1_6 ( - .COUT (_N14590), + .COUT (_N14548), .Z (N11[6]), - .CIN (_N14589), + .CIN (_N14547), .I0 (), .I1 (rise_cnt[6]), .I2 (), @@ -122954,9 +122790,9 @@ module ipsxb_ddrphy_rst_debounce_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_1_7 ( - .COUT (_N14591), + .COUT (_N14549), .Z (N11[7]), - .CIN (_N14590), + .CIN (_N14548), .I0 (), .I1 (rise_cnt[7]), .I2 (), @@ -122974,9 +122810,9 @@ module ipsxb_ddrphy_rst_debounce_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_1_8 ( - .COUT (_N14592), + .COUT (_N14550), .Z (N11[8]), - .CIN (_N14591), + .CIN (_N14549), .I0 (), .I1 (rise_cnt[8]), .I2 (), @@ -122994,9 +122830,9 @@ module ipsxb_ddrphy_rst_debounce_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_1_9 ( - .COUT (_N14593), + .COUT (_N14551), .Z (N11[9]), - .CIN (_N14592), + .CIN (_N14550), .I0 (), .I1 (rise_cnt[9]), .I2 (), @@ -123014,9 +122850,9 @@ module ipsxb_ddrphy_rst_debounce_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_1_10 ( - .COUT (_N14594), + .COUT (_N14552), .Z (N11[10]), - .CIN (_N14593), + .CIN (_N14551), .I0 (), .I1 (rise_cnt[10]), .I2 (), @@ -123034,9 +122870,9 @@ module ipsxb_ddrphy_rst_debounce_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_1_11 ( - .COUT (_N14595), + .COUT (_N14553), .Z (N11[11]), - .CIN (_N14594), + .CIN (_N14552), .I0 (), .I1 (rise_cnt[11]), .I2 (), @@ -123054,9 +122890,9 @@ module ipsxb_ddrphy_rst_debounce_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_1_12 ( - .COUT (_N14596), + .COUT (_N14554), .Z (N11[12]), - .CIN (_N14595), + .CIN (_N14553), .I0 (), .I1 (rise_cnt[12]), .I2 (), @@ -123074,9 +122910,9 @@ module ipsxb_ddrphy_rst_debounce_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_1_13 ( - .COUT (_N14597), + .COUT (_N14555), .Z (N11[13]), - .CIN (_N14596), + .CIN (_N14554), .I0 (), .I1 (rise_cnt[13]), .I2 (), @@ -123094,9 +122930,9 @@ module ipsxb_ddrphy_rst_debounce_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_1_14 ( - .COUT (_N14598), + .COUT (_N14556), .Z (N11[14]), - .CIN (_N14597), + .CIN (_N14555), .I0 (), .I1 (rise_cnt[14]), .I2 (), @@ -123114,9 +122950,9 @@ module ipsxb_ddrphy_rst_debounce_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_1_15 ( - .COUT (_N14599), + .COUT (_N14557), .Z (N11[15]), - .CIN (_N14598), + .CIN (_N14556), .I0 (), .I1 (rise_cnt[15]), .I2 (), @@ -123134,9 +122970,9 @@ module ipsxb_ddrphy_rst_debounce_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_1_16 ( - .COUT (_N14600), + .COUT (_N14558), .Z (N11[16]), - .CIN (_N14599), + .CIN (_N14557), .I0 (), .I1 (rise_cnt[16]), .I2 (), @@ -123154,9 +122990,9 @@ module ipsxb_ddrphy_rst_debounce_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_1_17 ( - .COUT (_N14601), + .COUT (_N14559), .Z (N11[17]), - .CIN (_N14600), + .CIN (_N14558), .I0 (), .I1 (rise_cnt[17]), .I2 (), @@ -123176,7 +123012,7 @@ module ipsxb_ddrphy_rst_debounce_v1_0 N11_1_18 ( .COUT (), .Z (N11[18]), - .CIN (_N14601), + .CIN (_N14559), .I0 (), .I1 (rise_cnt[18]), .I2 (), @@ -123187,10 +123023,10 @@ module ipsxb_ddrphy_rst_debounce_v1_0 // CARRY = (I1) ? CIN : (I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_rst_debounce_v1_0.vp:102 - GTP_LUT5 /* N39_7 */ #( + GTP_LUT5 /* N39_25 */ #( .INIT(32'b00000000000000000000000000000001)) - N39_7 ( - .Z (_N106328), + N39_25 ( + .Z (_N107146), .I0 (rise_cnt[4]), .I1 (rise_cnt[5]), .I2 (rise_cnt[6]), @@ -123198,10 +123034,10 @@ module ipsxb_ddrphy_rst_debounce_v1_0 .I4 (rise_cnt[8])); // LUT = ~I0&~I1&~I2&~I3&~I4 ; - GTP_LUT5 /* N39_11 */ #( + GTP_LUT5 /* N39_29 */ #( .INIT(32'b00000000000000000000000000000001)) - N39_11 ( - .Z (_N106332), + N39_29 ( + .Z (_N107150), .I0 (rise_cnt[9]), .I1 (rise_cnt[10]), .I2 (rise_cnt[11]), @@ -123209,10 +123045,10 @@ module ipsxb_ddrphy_rst_debounce_v1_0 .I4 (rise_cnt[13])); // LUT = ~I0&~I1&~I2&~I3&~I4 ; - GTP_LUT5 /* N39_15 */ #( + GTP_LUT5 /* N39_33 */ #( .INIT(32'b00000000000000010000000000000000)) - N39_15 ( - .Z (_N106336), + N39_33 ( + .Z (_N107154), .I0 (rise_cnt[14]), .I1 (rise_cnt[15]), .I2 (rise_cnt[16]), @@ -123220,39 +123056,48 @@ module ipsxb_ddrphy_rst_debounce_v1_0 .I4 (rise_cnt[18])); // LUT = ~I0&~I1&~I2&~I3&I4 ; - GTP_LUT5 /* N39_18 */ #( + GTP_LUT5 /* N39_36 */ #( + .INIT(32'b00000000000000010000000000000000)) + N39_36 ( + .Z (_N107157), + .I0 (rise_cnt[0]), + .I1 (rise_cnt[1]), + .I2 (rise_cnt[2]), + .I3 (rise_cnt[3]), + .I4 (_N107154)); + // LUT = ~I0&~I1&~I2&~I3&I4 ; + + GTP_LUT5 /* N39_36_cpy */ #( .INIT(32'b00000000000000010000000000000000)) - N39_18 ( - .Z (_N106339), + N39_36_cpy ( + .Z (_N107157_cpy), .I0 (rise_cnt[0]), .I1 (rise_cnt[1]), .I2 (rise_cnt[2]), .I3 (rise_cnt[3]), - .I4 (_N106336)); + .I4 (_N107154)); // LUT = ~I0&~I1&~I2&~I3&I4 ; - GTP_LUT5 /* N43 */ #( + GTP_LUT5 /* N43_3 */ #( .INIT(32'b11111110111011101110111011101110)) - N43_vname ( + N43_3 ( .Z (N43), .I0 (signal_b), .I1 (signal_b_neg), - .I2 (_N106328), - .I3 (_N106332), - .I4 (_N106339)); - // defparam N43_vname.orig_name = N43; + .I2 (_N107146), + .I3 (_N107150), + .I4 (_N107157)); // LUT = (I0)|(I1)|(I2&I3&I4) ; - // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_rst_debounce_v1_0.vp:93 - GTP_LUT5 /* \N44_3[0] */ #( + GTP_LUT5 /* \N44_3[0]_3 */ #( .INIT(32'b00000001000100010001000100010001)) - \N44_3[0] ( + \N44_3[0]_3 ( .Z (N44[0]), .I0 (signal_b_neg), .I1 (rise_cnt[0]), - .I2 (_N106328), - .I3 (_N106332), - .I4 (_N106339)); + .I2 (_N107146), + .I3 (_N107150), + .I4 (_N107157_cpy)); // LUT = (~I0&~I1&~I4)|(~I0&~I1&~I3)|(~I0&~I1&~I2) ; GTP_LUT5 /* \N44_3[1] */ #( @@ -123261,9 +123106,9 @@ module ipsxb_ddrphy_rst_debounce_v1_0 .Z (N44[1]), .I0 (signal_b_neg), .I1 (N11[1]), - .I2 (_N106328), - .I3 (_N106332), - .I4 (_N106339)); + .I2 (_N107146), + .I3 (_N107150), + .I4 (_N107157_cpy)); // LUT = (~I0&I1&~I4)|(~I0&I1&~I3)|(~I0&I1&~I2) ; GTP_LUT5 /* \N44_3[2] */ #( @@ -123272,9 +123117,9 @@ module ipsxb_ddrphy_rst_debounce_v1_0 .Z (N44[2]), .I0 (signal_b_neg), .I1 (N11[2]), - .I2 (_N106328), - .I3 (_N106332), - .I4 (_N106339)); + .I2 (_N107146), + .I3 (_N107150), + .I4 (_N107157_cpy)); // LUT = (~I0&I1&~I4)|(~I0&I1&~I3)|(~I0&I1&~I2) ; GTP_LUT5 /* \N44_3[3] */ #( @@ -123283,9 +123128,9 @@ module ipsxb_ddrphy_rst_debounce_v1_0 .Z (N44[3]), .I0 (signal_b_neg), .I1 (N11[3]), - .I2 (_N106328), - .I3 (_N106332), - .I4 (_N106339)); + .I2 (_N107146), + .I3 (_N107150), + .I4 (_N107157_cpy)); // LUT = (~I0&I1&~I4)|(~I0&I1&~I3)|(~I0&I1&~I2) ; GTP_LUT5 /* \N44_3[4] */ #( @@ -123294,9 +123139,9 @@ module ipsxb_ddrphy_rst_debounce_v1_0 .Z (N44[4]), .I0 (signal_b_neg), .I1 (N11[4]), - .I2 (_N106328), - .I3 (_N106332), - .I4 (_N106339)); + .I2 (_N107146), + .I3 (_N107150), + .I4 (_N107157_cpy)); // LUT = (~I0&I1&~I4)|(~I0&I1&~I3)|(~I0&I1&~I2) ; GTP_LUT5 /* \N44_3[5] */ #( @@ -123305,9 +123150,9 @@ module ipsxb_ddrphy_rst_debounce_v1_0 .Z (N44[5]), .I0 (signal_b_neg), .I1 (N11[5]), - .I2 (_N106328), - .I3 (_N106332), - .I4 (_N106339)); + .I2 (_N107146), + .I3 (_N107150), + .I4 (_N107157_cpy)); // LUT = (~I0&I1&~I4)|(~I0&I1&~I3)|(~I0&I1&~I2) ; GTP_LUT5 /* \N44_3[6] */ #( @@ -123316,9 +123161,9 @@ module ipsxb_ddrphy_rst_debounce_v1_0 .Z (N44[6]), .I0 (signal_b_neg), .I1 (N11[6]), - .I2 (_N106328), - .I3 (_N106332), - .I4 (_N106339)); + .I2 (_N107146), + .I3 (_N107150), + .I4 (_N107157_cpy)); // LUT = (~I0&I1&~I4)|(~I0&I1&~I3)|(~I0&I1&~I2) ; GTP_LUT5 /* \N44_3[7] */ #( @@ -123327,9 +123172,9 @@ module ipsxb_ddrphy_rst_debounce_v1_0 .Z (N44[7]), .I0 (signal_b_neg), .I1 (N11[7]), - .I2 (_N106328), - .I3 (_N106332), - .I4 (_N106339)); + .I2 (_N107146), + .I3 (_N107150), + .I4 (_N107157_cpy)); // LUT = (~I0&I1&~I4)|(~I0&I1&~I3)|(~I0&I1&~I2) ; GTP_LUT5 /* \N44_3[8] */ #( @@ -123338,9 +123183,9 @@ module ipsxb_ddrphy_rst_debounce_v1_0 .Z (N44[8]), .I0 (signal_b_neg), .I1 (N11[8]), - .I2 (_N106328), - .I3 (_N106332), - .I4 (_N106339)); + .I2 (_N107146), + .I3 (_N107150), + .I4 (_N107157_cpy)); // LUT = (~I0&I1&~I4)|(~I0&I1&~I3)|(~I0&I1&~I2) ; GTP_LUT5 /* \N44_3[9] */ #( @@ -123349,9 +123194,9 @@ module ipsxb_ddrphy_rst_debounce_v1_0 .Z (N44[9]), .I0 (signal_b_neg), .I1 (N11[9]), - .I2 (_N106328), - .I3 (_N106332), - .I4 (_N106339)); + .I2 (_N107146), + .I3 (_N107150), + .I4 (_N107157_cpy)); // LUT = (~I0&I1&~I4)|(~I0&I1&~I3)|(~I0&I1&~I2) ; GTP_LUT5 /* \N44_3[10] */ #( @@ -123360,9 +123205,9 @@ module ipsxb_ddrphy_rst_debounce_v1_0 .Z (N44[10]), .I0 (signal_b_neg), .I1 (N11[10]), - .I2 (_N106328), - .I3 (_N106332), - .I4 (_N106339)); + .I2 (_N107146), + .I3 (_N107150), + .I4 (_N107157_cpy)); // LUT = (~I0&I1&~I4)|(~I0&I1&~I3)|(~I0&I1&~I2) ; GTP_LUT5 /* \N44_3[11] */ #( @@ -123371,9 +123216,9 @@ module ipsxb_ddrphy_rst_debounce_v1_0 .Z (N44[11]), .I0 (signal_b_neg), .I1 (N11[11]), - .I2 (_N106328), - .I3 (_N106332), - .I4 (_N106339)); + .I2 (_N107146), + .I3 (_N107150), + .I4 (_N107157_cpy)); // LUT = (~I0&I1&~I4)|(~I0&I1&~I3)|(~I0&I1&~I2) ; GTP_LUT5 /* \N44_3[12] */ #( @@ -123382,9 +123227,9 @@ module ipsxb_ddrphy_rst_debounce_v1_0 .Z (N44[12]), .I0 (signal_b_neg), .I1 (N11[12]), - .I2 (_N106328), - .I3 (_N106332), - .I4 (_N106339)); + .I2 (_N107146), + .I3 (_N107150), + .I4 (_N107157_cpy)); // LUT = (~I0&I1&~I4)|(~I0&I1&~I3)|(~I0&I1&~I2) ; GTP_LUT5 /* \N44_3[13] */ #( @@ -123393,9 +123238,9 @@ module ipsxb_ddrphy_rst_debounce_v1_0 .Z (N44[13]), .I0 (signal_b_neg), .I1 (N11[13]), - .I2 (_N106328), - .I3 (_N106332), - .I4 (_N106339)); + .I2 (_N107146), + .I3 (_N107150), + .I4 (_N107157_cpy)); // LUT = (~I0&I1&~I4)|(~I0&I1&~I3)|(~I0&I1&~I2) ; GTP_LUT5 /* \N44_3[14] */ #( @@ -123404,9 +123249,9 @@ module ipsxb_ddrphy_rst_debounce_v1_0 .Z (N44[14]), .I0 (signal_b_neg), .I1 (N11[14]), - .I2 (_N106328), - .I3 (_N106332), - .I4 (_N106339)); + .I2 (_N107146), + .I3 (_N107150), + .I4 (_N107157_cpy)); // LUT = (~I0&I1&~I4)|(~I0&I1&~I3)|(~I0&I1&~I2) ; GTP_LUT5 /* \N44_3[15] */ #( @@ -123415,9 +123260,9 @@ module ipsxb_ddrphy_rst_debounce_v1_0 .Z (N44[15]), .I0 (signal_b_neg), .I1 (N11[15]), - .I2 (_N106328), - .I3 (_N106332), - .I4 (_N106339)); + .I2 (_N107146), + .I3 (_N107150), + .I4 (_N107157_cpy)); // LUT = (~I0&I1&~I4)|(~I0&I1&~I3)|(~I0&I1&~I2) ; GTP_LUT5 /* \N44_3[16] */ #( @@ -123426,9 +123271,9 @@ module ipsxb_ddrphy_rst_debounce_v1_0 .Z (N44[16]), .I0 (signal_b_neg), .I1 (N11[16]), - .I2 (_N106328), - .I3 (_N106332), - .I4 (_N106339)); + .I2 (_N107146), + .I3 (_N107150), + .I4 (_N107157_cpy)); // LUT = (~I0&I1&~I4)|(~I0&I1&~I3)|(~I0&I1&~I2) ; GTP_LUT5 /* \N44_3[17] */ #( @@ -123437,9 +123282,9 @@ module ipsxb_ddrphy_rst_debounce_v1_0 .Z (N44[17]), .I0 (signal_b_neg), .I1 (N11[17]), - .I2 (_N106328), - .I3 (_N106332), - .I4 (_N106339)); + .I2 (_N107146), + .I3 (_N107150), + .I4 (_N107157_cpy)); // LUT = (~I0&I1&~I4)|(~I0&I1&~I3)|(~I0&I1&~I2) ; GTP_LUT5 /* \N44_3[18] */ #( @@ -123448,9 +123293,9 @@ module ipsxb_ddrphy_rst_debounce_v1_0 .Z (N44[18]), .I0 (signal_b_neg), .I1 (N11[18]), - .I2 (_N106328), - .I3 (_N106332), - .I4 (_N106339)); + .I2 (_N107146), + .I3 (_N107150), + .I4 (_N107157_cpy)); // LUT = (~I0&I1)|(~I0&I2&I3&I4) ; GTP_DFF_CE /* \rise_cnt[0] */ #( @@ -123691,18 +123536,18 @@ module ipsxb_ddrphy_rst_debounce_v1_0 .Q (signal_deb), .C (N0), .CLK (clk), - .D (_N103471)); + .D (_N104283)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_rst_debounce_v1_0.vp:105 GTP_LUT5 /* signal_deb_pre_ce_mux */ #( .INIT(32'b00110010001000100010001000100010)) signal_deb_pre_ce_mux ( - .Z (_N103471), + .Z (_N104283), .I0 (signal_deb), .I1 (signal_b_neg), - .I2 (_N106328), - .I3 (_N106332), - .I4 (_N106339)); + .I2 (_N107146), + .I3 (_N107150), + .I4 (_N107157_cpy)); // LUT = (I0&~I1)|(~I1&I2&I3&I4) ; @@ -123782,7 +123627,6 @@ endmodule module ipsxb_ddrphy_reset_ctrl_v1_4 ( input N0, - input _N18115, input ddr_rstn, input ddrphy_clkin, input dll_lock, @@ -123793,12 +123637,7 @@ module ipsxb_ddrphy_reset_ctrl_v1_4 input ref_clk, input training_error, input wrlvl_ck_dly_start_rst, - output [7:0] cnt, - output [8:0] state_reg, output N17, - output N137, - output _N97085, - output _N106355, output ddrphy_dll_rst, output ddrphy_dqs_rst, output ddrphy_ioclk_gate, @@ -123807,8 +123646,10 @@ module ipsxb_ddrphy_reset_ctrl_v1_4 output dll_update_req_rst_ctrl, output logic_rstn ); + wire [7:0] N29; wire N115; wire N126; + wire N137; wire N219; wire N240; wire [7:0] N241; @@ -123823,23 +123664,28 @@ module ipsxb_ddrphy_reset_ctrl_v1_4 wire _N38; wire _N43; wire _N48; - wire _N14542; - wire _N14543; - wire _N14544; - wire _N14545; - wire _N14546; - wire _N14547; - wire _N97086; - wire _N106342; - wire _N106347; - wire _N106349; - wire _N106378; + wire _N14523; + wire _N14524; + wire _N14525; + wire _N14526; + wire _N14527; + wire _N14528; + wire _N84886; + wire _N97845; + wire _N97846; + wire _N107160; + wire _N107164; + wire _N107167; + wire _N107173; + wire _N107196; + wire [7:0] cnt; wire ddrphy_dll_rst_rg; wire ddrphy_rst_n_rg; wire [1:0] dll_lock_d; wire [1:0] dll_update_ack_rst_ctrl_d; wire [1:0] pll_lock_d; wire pll_lock_deb; + wire [8:0] state_reg; wire [1:0] training_error_d; wire wrlvl_ck_dly_start_rst_d1; wire wrlvl_ck_dly_start_rst_d2; @@ -123850,142 +123696,142 @@ module ipsxb_ddrphy_reset_ctrl_v1_4 // defparam N17_vname.orig_name = N17; GTP_LUT5CARRY /* N29_1_1 */ #( - .INIT(32'b01100000011000000000000000000000), + .INIT(32'b01100110011001100000000000000000), .ID_TO_LUT("FALSE"), .CIN_TO_LUT("FALSE"), .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N29_1_1 ( - .COUT (_N14542), - .Z (N241[1]), + .COUT (_N14523), + .Z (N29[1]), .CIN (), .I0 (cnt[0]), .I1 (cnt[1]), - .I2 (_N18115), + .I2 (), .I3 (), .I4 (1'b1), .ID ()); - // LUT = (I0&~I1&I2)|(~I0&I1&I2) ; + // LUT = I1^I0 ; // CARRY = (1'b0) ? CIN : (I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_reset_ctrl_v1_4.vp:286 GTP_LUT5CARRY /* N29_1_2 */ #( - .INIT(32'b01110000100000001000100000000000), + .INIT(32'b01111000011110001000000010000000), .ID_TO_LUT("FALSE"), .CIN_TO_LUT("FALSE"), .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N29_1_2 ( - .COUT (_N14543), - .Z (N241[2]), - .CIN (_N14542), + .COUT (_N14524), + .Z (N29[2]), + .CIN (_N14523), .I0 (cnt[0]), .I1 (cnt[1]), - .I2 (_N18115), - .I3 (cnt[2]), + .I2 (cnt[2]), + .I3 (), .I4 (1'b0), .ID ()); - // LUT = (I0&I1&I2&~I3)|(~I1&I2&I3)|(~I0&I2&I3) ; - // CARRY = (I0&I1&I3) ? CIN : (I4) ; + // LUT = (I0&I1&~I2)|(~I1&I2)|(~I0&I2) ; + // CARRY = (I0&I1&I2) ? CIN : (I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_reset_ctrl_v1_4.vp:286 GTP_LUT5CARRY /* N29_1_3 */ #( - .INIT(32'b01100000011000001100110011001100), + .INIT(32'b01100110011001101100110011001100), .ID_TO_LUT("FALSE"), .CIN_TO_LUT("TRUE"), .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N29_1_3 ( - .COUT (_N14544), - .Z (N241[3]), - .CIN (_N14543), + .COUT (_N14525), + .Z (N29[3]), + .CIN (_N14524), .I0 (), .I1 (cnt[3]), - .I2 (_N18115), + .I2 (), .I3 (), .I4 (1'b0), .ID ()); - // LUT = (CIN&~I1&I2)|(~CIN&I1&I2) ; + // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_reset_ctrl_v1_4.vp:286 GTP_LUT5CARRY /* N29_1_4 */ #( - .INIT(32'b01100000011000001100110011001100), + .INIT(32'b01100110011001101100110011001100), .ID_TO_LUT("FALSE"), .CIN_TO_LUT("TRUE"), .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N29_1_4 ( - .COUT (_N14545), - .Z (N241[4]), - .CIN (_N14544), + .COUT (_N14526), + .Z (N29[4]), + .CIN (_N14525), .I0 (), .I1 (cnt[4]), - .I2 (_N18115), + .I2 (), .I3 (), .I4 (1'b0), .ID ()); - // LUT = (CIN&~I1&I2)|(~CIN&I1&I2) ; + // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_reset_ctrl_v1_4.vp:286 GTP_LUT5CARRY /* N29_1_5 */ #( - .INIT(32'b01100000011000001100110011001100), + .INIT(32'b01100110011001101100110011001100), .ID_TO_LUT("FALSE"), .CIN_TO_LUT("TRUE"), .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N29_1_5 ( - .COUT (_N14546), - .Z (N241[5]), - .CIN (_N14545), + .COUT (_N14527), + .Z (N29[5]), + .CIN (_N14526), .I0 (), .I1 (cnt[5]), - .I2 (_N18115), + .I2 (), .I3 (), .I4 (1'b0), .ID ()); - // LUT = (CIN&~I1&I2)|(~CIN&I1&I2) ; + // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_reset_ctrl_v1_4.vp:286 GTP_LUT5CARRY /* N29_1_6 */ #( - .INIT(32'b01100000011000001100110011001100), + .INIT(32'b01100110011001101100110011001100), .ID_TO_LUT("FALSE"), .CIN_TO_LUT("TRUE"), .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N29_1_6 ( - .COUT (_N14547), - .Z (N241[6]), - .CIN (_N14546), + .COUT (_N14528), + .Z (N29[6]), + .CIN (_N14527), .I0 (), .I1 (cnt[6]), - .I2 (_N18115), + .I2 (), .I3 (), .I4 (1'b0), .ID ()); - // LUT = (CIN&~I1&I2)|(~CIN&I1&I2) ; + // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_reset_ctrl_v1_4.vp:286 GTP_LUT5CARRY /* N29_1_7 */ #( - .INIT(32'b01100000011000001100110011001100), + .INIT(32'b01100110011001101100110011001100), .ID_TO_LUT("FALSE"), .CIN_TO_LUT("TRUE"), .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N29_1_7 ( .COUT (), - .Z (N241[7]), - .CIN (_N14547), + .Z (N29[7]), + .CIN (_N14528), .I0 (), .I1 (cnt[7]), - .I2 (_N18115), + .I2 (), .I3 (), .I4 (1'b0), .ID ()); - // LUT = (CIN&~I1&I2)|(~CIN&I1&I2) ; + // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_reset_ctrl_v1_4.vp:286 @@ -124015,17 +123861,15 @@ module ipsxb_ddrphy_reset_ctrl_v1_4 // defparam N126_vname.orig_name = N126; // LUT = ~I0 ; - GTP_LUT4 /* N219 */ #( + GTP_LUT4 /* N219_2 */ #( .INIT(16'b1111101111111111)) - N219_vname ( + N219_2 ( .Z (N219), .I0 (gate_check_error), .I1 (cnt[7]), .I2 (dll_lock_d[1]), .I3 (state_reg[2])); - // defparam N219_vname.orig_name = N219; // LUT = (~I3)|(~I1)|(I0)|(I2) ; - // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_reset_ctrl_v1_4.vp:267 GTP_LUT3 /* N240_5 */ #( .INIT(8'b10111111)) @@ -124039,7 +123883,7 @@ module ipsxb_ddrphy_reset_ctrl_v1_4 GTP_LUT5 /* N241_4_4 */ #( .INIT(32'b11111111111111111111111111111110)) N241_4_4 ( - .Z (_N106355), + .Z (_N107173), .I0 (gate_check_error), .I1 (state_reg[1]), .I2 (state_reg[3]), @@ -124047,13 +123891,102 @@ module ipsxb_ddrphy_reset_ctrl_v1_4 .I4 (state_reg[8])); // LUT = (I0)|(I1)|(I2)|(I3)|(I4) ; - GTP_LUT2 /* \N241_7[0]_1 */ #( - .INIT(4'b0100)) + GTP_LUT4 /* N241_6_3 */ #( + .INIT(16'b1111111111111110)) + N241_6_3 ( + .Z (_N84886), + .I0 (state_reg[5]), + .I1 (state_reg[6]), + .I2 (state_reg[7]), + .I3 (_N97845)); + // LUT = (I0)|(I1)|(I2)|(I3) ; + + GTP_LUT4 /* \N241_7[0]_1 */ #( + .INIT(16'b0000000000010101)) \N241_7[0]_1 ( .Z (N241[0]), .I0 (cnt[0]), - .I1 (_N18115)); - // LUT = ~I0&I1 ; + .I1 (cnt[3]), + .I2 (_N84886), + .I3 (_N107173)); + // LUT = (~I0&~I2&~I3)|(~I0&~I1&~I3) ; + // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_reset_ctrl_v1_4.vp:267 + + GTP_LUT4 /* \N241_7[1]_1 */ #( + .INIT(16'b0000000000101010)) + \N241_7[1]_1 ( + .Z (N241[1]), + .I0 (N29[1]), + .I1 (cnt[3]), + .I2 (_N84886), + .I3 (_N107173)); + // LUT = (I0&~I2&~I3)|(I0&~I1&~I3) ; + // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_reset_ctrl_v1_4.vp:267 + + GTP_LUT4 /* \N241_7[2]_1 */ #( + .INIT(16'b0000000000101010)) + \N241_7[2]_1 ( + .Z (N241[2]), + .I0 (N29[2]), + .I1 (cnt[3]), + .I2 (_N84886), + .I3 (_N107173)); + // LUT = (I0&~I2&~I3)|(I0&~I1&~I3) ; + // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_reset_ctrl_v1_4.vp:267 + + GTP_LUT4 /* \N241_7[3]_1 */ #( + .INIT(16'b0000000000101010)) + \N241_7[3]_1 ( + .Z (N241[3]), + .I0 (N29[3]), + .I1 (cnt[3]), + .I2 (_N84886), + .I3 (_N107173)); + // LUT = (I0&~I2&~I3)|(I0&~I1&~I3) ; + // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_reset_ctrl_v1_4.vp:267 + + GTP_LUT4 /* \N241_7[4]_1 */ #( + .INIT(16'b0000000000101010)) + \N241_7[4]_1 ( + .Z (N241[4]), + .I0 (N29[4]), + .I1 (cnt[3]), + .I2 (_N84886), + .I3 (_N107173)); + // LUT = (I0&~I2&~I3)|(I0&~I1&~I3) ; + // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_reset_ctrl_v1_4.vp:267 + + GTP_LUT4 /* \N241_7[5]_1 */ #( + .INIT(16'b0000000000101010)) + \N241_7[5]_1 ( + .Z (N241[5]), + .I0 (N29[5]), + .I1 (cnt[3]), + .I2 (_N84886), + .I3 (_N107173)); + // LUT = (I0&~I2&~I3)|(I0&~I1&~I3) ; + // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_reset_ctrl_v1_4.vp:267 + + GTP_LUT4 /* \N241_7[6]_1 */ #( + .INIT(16'b0000000000101010)) + \N241_7[6]_1 ( + .Z (N241[6]), + .I0 (N29[6]), + .I1 (cnt[3]), + .I2 (_N84886), + .I3 (_N107173)); + // LUT = (I0&~I2&~I3)|(I0&~I1&~I3) ; + // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_reset_ctrl_v1_4.vp:267 + + GTP_LUT4 /* \N241_7[7]_1 */ #( + .INIT(16'b0000000000101010)) + \N241_7[7]_1 ( + .Z (N241[7]), + .I0 (N29[7]), + .I1 (cnt[3]), + .I2 (_N84886), + .I3 (_N107173)); + // LUT = (I0&~I2&~I3)|(I0&~I1&~I3) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_reset_ctrl_v1_4.vp:267 GTP_LUT2 /* N241_8 */ #( @@ -124299,7 +124232,7 @@ module ipsxb_ddrphy_reset_ctrl_v1_4 GTP_LUT4 /* \state_fsm[3:0]_1_4 */ #( .INIT(16'b1101111111111111)) \state_fsm[3:0]_1_4 ( - .Z (_N106378), + .Z (_N107196), .I0 (cnt[1]), .I1 (cnt[2]), .I2 (cnt[5]), @@ -124314,7 +124247,7 @@ module ipsxb_ddrphy_reset_ctrl_v1_4 .I1 (cnt[3]), .I2 (cnt[4]), .I3 (cnt[7]), - .I4 (_N106378)); + .I4 (_N107196)); // LUT = (~I3)|(~I2)|(~I1)|(I0)|(I4) ; GTP_LUT5 /* \state_fsm[3:0]_4_3 */ #( @@ -124336,13 +124269,13 @@ module ipsxb_ddrphy_reset_ctrl_v1_4 .I1 (pll_lock_deb), .I2 (cnt[3]), .I3 (state_reg[1]), - .I4 (_N97085)); + .I4 (_N97845)); // LUT = (~I0&~I1&I3)|(~I0&I2&I4) ; GTP_LUT5 /* \state_fsm[3:0]_34_2 */ #( .INIT(32'b00010101000100010000010100000000)) \state_fsm[3:0]_34_2 ( - .Z (_N106349), + .Z (_N107167), .I0 (gate_check_error), .I1 (cnt[3]), .I2 (dll_update_ack_rst_ctrl_d[1]), @@ -124358,7 +124291,7 @@ module ipsxb_ddrphy_reset_ctrl_v1_4 .I1 (wrlvl_ck_dly_start_rst_d2), .I2 (N262[13]), .I3 (state_reg[8]), - .I4 (_N106349)); + .I4 (_N107167)); // LUT = (I4)|(~I0&I1&~I2&I3) ; GTP_LUT4 /* \state_fsm[3:0]_39 */ #( @@ -124391,7 +124324,7 @@ module ipsxb_ddrphy_reset_ctrl_v1_4 .I1 (wrlvl_ck_dly_start_rst_d2), .I2 (cnt[3]), .I3 (state_reg[7]), - .I4 (_N97086)); + .I4 (_N97846)); // LUT = (~I1&I4)|(~I0&I2&I3) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_reset_ctrl_v1_4.vp:267 @@ -124414,13 +124347,13 @@ module ipsxb_ddrphy_reset_ctrl_v1_4 .I1 (dll_update_ack_rst_ctrl_d[1]), .I2 (state_reg[2]), .I3 (state_reg[3]), - .I4 (_N106342)); + .I4 (_N107160)); // LUT = (I2&I4)|(~I0&~I1&I3)|(~I1&I3&I4) ; GTP_LUT3 /* \state_fsm[3:0]_65_3 */ #( .INIT(8'b01000000)) \state_fsm[3:0]_65_3 ( - .Z (_N106342), + .Z (_N107160), .I0 (gate_check_error), .I1 (cnt[7]), .I2 (dll_lock_d[1])); @@ -124439,33 +124372,33 @@ module ipsxb_ddrphy_reset_ctrl_v1_4 GTP_LUT4 /* \state_fsm[3:0]_101 */ #( .INIT(16'b0000010000000000)) \state_fsm[3:0]_101 ( - .Z (_N97086), + .Z (_N97846), .I0 (gate_check_error), .I1 (pll_lock_deb), .I2 (training_error_d[1]), .I3 (state_reg[8])); // LUT = ~I0&I1&~I2&I3 ; - GTP_LUT4 /* \state_fsm[3:0]_105 */ #( - .INIT(16'b0100000000000000)) - \state_fsm[3:0]_105 ( - .Z (_N106347), - .I0 (cnt[0]), - .I1 (cnt[4]), - .I2 (cnt[7]), - .I3 (state_reg[0])); - // LUT = ~I0&I1&I2&I3 ; - - GTP_LUT5 /* \state_fsm[3:0]_106 */ #( - .INIT(32'b00100000000000000000000000000000)) - \state_fsm[3:0]_106 ( - .Z (_N97085), + GTP_LUT4 /* \state_fsm[3:0]_104 */ #( + .INIT(16'b0010000000000000)) + \state_fsm[3:0]_104 ( + .Z (_N107164), .I0 (cnt[1]), .I1 (cnt[2]), .I2 (cnt[5]), - .I3 (cnt[6]), - .I4 (_N106347)); - // LUT = I0&~I1&I2&I3&I4 ; + .I3 (cnt[6])); + // LUT = I0&~I1&I2&I3 ; + + GTP_LUT5 /* \state_fsm[3:0]_106 */ #( + .INIT(32'b01000000000000000000000000000000)) + \state_fsm[3:0]_106 ( + .Z (_N97845), + .I0 (cnt[0]), + .I1 (cnt[4]), + .I2 (cnt[7]), + .I3 (state_reg[0]), + .I4 (_N107164)); + // LUT = ~I0&I1&I2&I3&I4 ; (* syn_encoding="onehot" *) GTP_DFF_PE /* \state_reg[0] */ #( .GRS_EN("TRUE"), @@ -124661,81 +124594,81 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3 wire N194_inv; wire N213; wire [4:0] N227; - wire _N5587; - wire _N22871; - wire _N22873; - wire _N22875; - wire _N22876; - wire _N22877; + wire _N5581; + wire _N22846; + wire _N22848; + wire _N22850; + wire _N22851; + wire _N22852; + wire _N22853; + wire _N22862; + wire _N22864; wire _N22878; - wire _N22887; - wire _N22889; - wire _N22903; - wire _N22905; - wire _N22906; - wire _N24127; + wire _N22880; + wire _N22881; + wire _N23906; + wire _N23929; + wire _N23953; + wire _N23975; + wire _N23976; + wire _N23977; + wire _N23978; + wire _N23979; + wire _N23980; + wire _N23981; + wire _N23982; + wire _N23983; + wire _N23984; + wire _N23985; + wire _N23986; + wire _N23987; + wire _N23988; + wire _N23989; + wire _N23990; + wire _N23991; + wire _N24024; + wire _N24025; + wire _N24026; + wire _N24027; + wire _N24028; + wire _N24029; + wire _N24030; + wire _N24031; + wire _N24032; + wire _N24033; + wire _N24034; + wire _N24035; + wire _N24036; + wire _N24037; + wire _N24038; + wire _N24039; + wire _N24088; + wire _N24089; + wire _N24092; + wire _N24093; + wire _N24096; + wire _N24097; + wire _N24100; + wire _N24101; + wire _N24136; + wire _N24137; + wire _N24138; + wire _N24139; + wire _N24140; + wire _N24141; + wire _N24142; + wire _N24143; + wire _N24144; + wire _N24145; + wire _N24146; + wire _N24147; + wire _N24148; + wire _N24149; wire _N24150; - wire _N24174; - wire _N24196; - wire _N24197; - wire _N24198; - wire _N24199; - wire _N24200; - wire _N24201; - wire _N24202; - wire _N24203; - wire _N24204; - wire _N24205; - wire _N24206; - wire _N24207; - wire _N24208; - wire _N24209; - wire _N24210; - wire _N24211; - wire _N24212; - wire _N24245; - wire _N24246; - wire _N24247; - wire _N24248; - wire _N24249; - wire _N24250; - wire _N24251; - wire _N24252; - wire _N24253; - wire _N24254; - wire _N24255; - wire _N24256; - wire _N24257; - wire _N24258; - wire _N24259; - wire _N24260; - wire _N24309; - wire _N24310; - wire _N24313; - wire _N24314; - wire _N24317; - wire _N24318; - wire _N24321; - wire _N24322; - wire _N24357; - wire _N24358; - wire _N24359; - wire _N24360; - wire _N24361; - wire _N24362; - wire _N24363; - wire _N24364; - wire _N24365; - wire _N24366; - wire _N24367; - wire _N24368; - wire _N24369; - wire _N24370; - wire _N24371; - wire _N24372; - wire _N95788; - wire _N96702; - wire _N103362; + wire _N24151; + wire _N96568; + wire _N97460; + wire _N104174; wire [4:0] cnt; wire [3:0] dqs_gate_ctrl_adj; wire [3:0] dqs_gate_pulse_r1; @@ -124779,7 +124712,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3 GTP_LUT3 /* N144_ac2 */ #( .INIT(8'b10000000)) N144_ac2 ( - .Z (_N5587), + .Z (_N5581), .I0 (cnt[2]), .I1 (cnt[1]), .I2 (cnt[0])); @@ -124798,7 +124731,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3 GTP_LUT5 /* N205_1_5 */ #( .INIT(32'b00000000000000000000010000000000)) N205_1_5 ( - .Z (_N95788), + .Z (_N96568), .I0 (cnt[4]), .I1 (cnt[3]), .I2 (cnt[2]), @@ -124813,7 +124746,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3 .I0 (gatecal_start), .I1 (rddata_cal), .I2 (N194_inv), - .I3 (_N95788)); + .I3 (_N96568)); // LUT = (I2)|(I3)|(~I0&~I1) ; GTP_LUT5 /* \N227[0]_1 */ #( @@ -124824,7 +124757,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3 .I1 (rddata_cal), .I2 (cnt[0]), .I3 (N194_inv), - .I4 (_N95788)); + .I4 (_N96568)); // LUT = (I0&~I2&~I3&~I4)|(I1&~I2&~I3&~I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3.vp:346 @@ -124865,7 +124798,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3 .INIT(16'b0000000001101100)) \N227[4]_1 ( .Z (N227[4]), - .I0 (_N5587), + .I0 (_N5581), .I1 (cnt[4]), .I2 (cnt[3]), .I3 (N213)); @@ -124878,7 +124811,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3 .Z (dqs_gate_pulse_src_nxt[2]), .I0 (read_en_slipped[3]), .I1 (read_en_slipped[2]), - .I2 (_N96702)); + .I2 (_N97460)); // LUT = I0&~I1&~I2 ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3.vp:255 @@ -124888,7 +124821,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3 .Z (dqs_gate_pulse_src[3]), .I0 (read_en_slipped[3]), .I1 (read_en_slipped[2]), - .I2 (_N96702)); + .I2 (_N97460)); // LUT = (I0)|(I1)|(I2) ; GTP_LUT4 /* N261_inv */ #( @@ -124898,7 +124831,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3 .I0 (read_en_slipped[3]), .I1 (read_en_slipped[2]), .I2 (read_en_slipped[0]), - .I3 (_N96702)); + .I3 (_N97460)); // LUT = (I0&~I2)|(I1&~I2)|(~I2&I3) ; GTP_DFF_C /* \cnt[0] */ #( @@ -124954,7 +124887,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3 GTP_LUT5 /* dqs_gate_ctrl_adj_113_5 */ #( .INIT(32'b00000000000000011001100110000000)) dqs_gate_ctrl_adj_113_5 ( - .Z (_N24150), + .Z (_N23929), .I0 (mc_rl[0]), .I1 (mc_rl[1]), .I2 (mc_rl[2]), @@ -124965,7 +124898,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3 GTP_LUT5 /* dqs_gate_ctrl_adj_137_5 */ #( .INIT(32'b00000000000001100001111000000000)) dqs_gate_ctrl_adj_137_5 ( - .Z (_N24174), + .Z (_N23953), .I0 (mc_rl[0]), .I1 (mc_rl[1]), .I2 (mc_rl[2]), @@ -124976,7 +124909,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3 GTP_LUT5 /* dqs_gate_ctrl_adj_159_5 */ #( .INIT(32'b00000000000001111110000000000000)) dqs_gate_ctrl_adj_159_5 ( - .Z (_N24196), + .Z (_N23975), .I0 (mc_rl[0]), .I1 (mc_rl[1]), .I2 (mc_rl[2]), @@ -124987,116 +124920,116 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3 GTP_LUT3 /* \dqs_gate_ctrl_adj_160[0] */ #( .INIT(8'b11001010)) \dqs_gate_ctrl_adj_160[0] ( - .Z (_N24197), + .Z (_N23976), .I0 (dqs_gate_pulse_r2[2]), .I1 (dqs_gate_pulse_r2[1]), - .I2 (_N24127)); + .I2 (_N23906)); // LUT = (I0&~I2)|(I1&I2) ; GTP_LUT3 /* \dqs_gate_ctrl_adj_160[1] */ #( .INIT(8'b11001010)) \dqs_gate_ctrl_adj_160[1] ( - .Z (_N24198), + .Z (_N23977), .I0 (dqs_gate_pulse_r2[3]), .I1 (dqs_gate_pulse_r2[2]), - .I2 (_N24127)); + .I2 (_N23906)); // LUT = (I0&~I2)|(I1&I2) ; GTP_LUT3 /* \dqs_gate_ctrl_adj_160[2] */ #( .INIT(8'b11001010)) \dqs_gate_ctrl_adj_160[2] ( - .Z (_N24199), + .Z (_N23978), .I0 (dqs_gate_pulse_r1[0]), .I1 (dqs_gate_pulse_r2[3]), - .I2 (_N24127)); + .I2 (_N23906)); // LUT = (I0&~I2)|(I1&I2) ; GTP_LUT3 /* \dqs_gate_ctrl_adj_160[3] */ #( .INIT(8'b11001010)) \dqs_gate_ctrl_adj_160[3] ( - .Z (_N24200), + .Z (_N23979), .I0 (dqs_gate_pulse_r1[1]), .I1 (dqs_gate_pulse_r1[0]), - .I2 (_N24127)); + .I2 (_N23906)); // LUT = (I0&~I2)|(I1&I2) ; GTP_LUT3 /* \dqs_gate_ctrl_adj_160[4] */ #( .INIT(8'b11001010)) \dqs_gate_ctrl_adj_160[4] ( - .Z (_N24201), + .Z (_N23980), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [2] ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [1] ), - .I2 (_N24127)); + .I2 (_N23906)); // LUT = (I0&~I2)|(I1&I2) ; GTP_LUT3 /* \dqs_gate_ctrl_adj_160[5] */ #( .INIT(8'b11001010)) \dqs_gate_ctrl_adj_160[5] ( - .Z (_N24202), + .Z (_N23981), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [3] ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [2] ), - .I2 (_N24127)); + .I2 (_N23906)); // LUT = (I0&~I2)|(I1&I2) ; GTP_LUT3 /* \dqs_gate_ctrl_adj_160[6] */ #( .INIT(8'b11001010)) \dqs_gate_ctrl_adj_160[6] ( - .Z (_N24203), + .Z (_N23982), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 [0] ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [3] ), - .I2 (_N24127)); + .I2 (_N23906)); // LUT = (I0&~I2)|(I1&I2) ; GTP_LUT3 /* \dqs_gate_ctrl_adj_160[7] */ #( .INIT(8'b11001010)) \dqs_gate_ctrl_adj_160[7] ( - .Z (_N24204), + .Z (_N23983), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 [1] ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 [0] ), - .I2 (_N24127)); + .I2 (_N23906)); // LUT = (I0&~I2)|(I1&I2) ; GTP_LUT3 /* \dqs_gate_ctrl_adj_160[8] */ #( .INIT(8'b11001010)) \dqs_gate_ctrl_adj_160[8] ( - .Z (_N24205), + .Z (_N23984), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [2] ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [1] ), - .I2 (_N24127)); + .I2 (_N23906)); // LUT = (I0&~I2)|(I1&I2) ; GTP_LUT3 /* \dqs_gate_ctrl_adj_160[9] */ #( .INIT(8'b11001010)) \dqs_gate_ctrl_adj_160[9] ( - .Z (_N24206), + .Z (_N23985), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [3] ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [2] ), - .I2 (_N24127)); + .I2 (_N23906)); // LUT = (I0&~I2)|(I1&I2) ; GTP_LUT3 /* \dqs_gate_ctrl_adj_160[10] */ #( .INIT(8'b11001010)) \dqs_gate_ctrl_adj_160[10] ( - .Z (_N24207), + .Z (_N23986), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 [0] ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [3] ), - .I2 (_N24127)); + .I2 (_N23906)); // LUT = (I0&~I2)|(I1&I2) ; GTP_LUT3 /* \dqs_gate_ctrl_adj_160[11] */ #( .INIT(8'b11001010)) \dqs_gate_ctrl_adj_160[11] ( - .Z (_N24208), + .Z (_N23987), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 [1] ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 [0] ), - .I2 (_N24127)); + .I2 (_N23906)); // LUT = (I0&~I2)|(I1&I2) ; GTP_LUT3 /* \dqs_gate_ctrl_adj_160[12] */ #( .INIT(8'b11011000)) \dqs_gate_ctrl_adj_160[12] ( - .Z (_N24209), - .I0 (_N24127), + .Z (_N23988), + .I0 (_N23906), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [1] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [2] )); // LUT = (~I0&I2)|(I0&I1) ; @@ -125104,8 +125037,8 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3 GTP_LUT3 /* \dqs_gate_ctrl_adj_160[13] */ #( .INIT(8'b11011000)) \dqs_gate_ctrl_adj_160[13] ( - .Z (_N24210), - .I0 (_N24127), + .Z (_N23989), + .I0 (_N23906), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [2] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [3] )); // LUT = (~I0&I2)|(I0&I1) ; @@ -125113,8 +125046,8 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3 GTP_LUT3 /* \dqs_gate_ctrl_adj_160[14] */ #( .INIT(8'b11100100)) \dqs_gate_ctrl_adj_160[14] ( - .Z (_N24211), - .I0 (_N24127), + .Z (_N23990), + .I0 (_N23906), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 [0] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [3] )); // LUT = (~I0&I1)|(I0&I2) ; @@ -125122,8 +125055,8 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3 GTP_LUT3 /* \dqs_gate_ctrl_adj_160[15] */ #( .INIT(8'b11011000)) \dqs_gate_ctrl_adj_160[15] ( - .Z (_N24212), - .I0 (_N24127), + .Z (_N23991), + .I0 (_N23906), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 [0] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 [1] )); // LUT = (~I0&I2)|(I0&I1) ; @@ -125131,480 +125064,480 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3 GTP_LUT5M /* \dqs_gate_ctrl_adj_163[0] */ #( .INIT(32'b11001100101010101111000010101010)) \dqs_gate_ctrl_adj_163[0] ( - .Z (_N24245), + .Z (_N24024), .I0 (dqs_gate_pulse_r1[1]), .I1 (dqs_gate_pulse_r3[1]), .I2 (dqs_gate_pulse_r3[2]), - .I3 (_N24196), - .I4 (_N24127), + .I3 (_N23975), + .I4 (_N23906), .ID (dqs_gate_pulse_r1[2])); // LUT = (ID&~I3&~I4)|(I2&I3&~I4)|(I0&~I3&I4)|(I1&I3&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_163[1] */ #( .INIT(32'b11001100101010101111000010101010)) \dqs_gate_ctrl_adj_163[1] ( - .Z (_N24246), + .Z (_N24025), .I0 (dqs_gate_pulse_r1[2]), .I1 (dqs_gate_pulse_r3[2]), .I2 (dqs_gate_pulse_r3[3]), - .I3 (_N24196), - .I4 (_N24127), + .I3 (_N23975), + .I4 (_N23906), .ID (dqs_gate_pulse_r1[3])); // LUT = (ID&~I3&~I4)|(I2&I3&~I4)|(I0&~I3&I4)|(I1&I3&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_163[2] */ #( .INIT(32'b11110000101010101010101011001100)) \dqs_gate_ctrl_adj_163[2] ( - .Z (_N24247), + .Z (_N24026), .I0 (dqs_gate_pulse_r1[3]), .I1 (dqs_gate_pulse_src[0]), .I2 (dqs_gate_pulse_r3[3]), - .I3 (_N24196), - .I4 (_N24127), + .I3 (_N23975), + .I4 (_N23906), .ID (dqs_gate_pulse_r2[0])); // LUT = (I1&~I3&~I4)|(ID&I3&~I4)|(I0&~I3&I4)|(I2&I3&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_163[3] */ #( .INIT(32'b10101010110011001010101011110000)) \dqs_gate_ctrl_adj_163[3] ( - .Z (_N24248), + .Z (_N24027), .I0 (dqs_gate_pulse_r2[0]), .I1 (dqs_gate_pulse_src[0]), .I2 (dqs_gate_pulse_src[1]), - .I3 (_N24196), - .I4 (_N24127), + .I3 (_N23975), + .I4 (_N23906), .ID (dqs_gate_pulse_r2[1])); // LUT = (I2&~I3&~I4)|(ID&I3&~I4)|(I1&~I3&I4)|(I0&I3&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_163[4] */ #( .INIT(32'b11001100101010101111000010101010)) \dqs_gate_ctrl_adj_163[4] ( - .Z (_N24249), + .Z (_N24028), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 [1] ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3 [1] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3 [2] ), - .I3 (_N24196), - .I4 (_N24127), + .I3 (_N23975), + .I4 (_N23906), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 [2] )); // LUT = (ID&~I3&~I4)|(I2&I3&~I4)|(I0&~I3&I4)|(I1&I3&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_163[5] */ #( .INIT(32'b11001100101010101111000010101010)) \dqs_gate_ctrl_adj_163[5] ( - .Z (_N24250), + .Z (_N24029), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 [2] ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3 [2] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3 [3] ), - .I3 (_N24196), - .I4 (_N24127), + .I3 (_N23975), + .I4 (_N23906), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 [3] )); // LUT = (ID&~I3&~I4)|(I2&I3&~I4)|(I0&~I3&I4)|(I1&I3&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_163[6] */ #( .INIT(32'b11110000101010101010101011001100)) \dqs_gate_ctrl_adj_163[6] ( - .Z (_N24251), + .Z (_N24030), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 [3] ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [0] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3 [3] ), - .I3 (_N24196), - .I4 (_N24127), + .I3 (_N23975), + .I4 (_N23906), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [0] )); // LUT = (I1&~I3&~I4)|(ID&I3&~I4)|(I0&~I3&I4)|(I2&I3&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_163[7] */ #( .INIT(32'b10101010110011001010101011110000)) \dqs_gate_ctrl_adj_163[7] ( - .Z (_N24252), + .Z (_N24031), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [0] ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [0] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [1] ), - .I3 (_N24196), - .I4 (_N24127), + .I3 (_N23975), + .I4 (_N23906), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [1] )); // LUT = (I2&~I3&~I4)|(ID&I3&~I4)|(I1&~I3&I4)|(I0&I3&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_163[8] */ #( .INIT(32'b11001100101010101111000010101010)) \dqs_gate_ctrl_adj_163[8] ( - .Z (_N24253), + .Z (_N24032), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 [1] ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3 [1] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3 [2] ), - .I3 (_N24196), - .I4 (_N24127), + .I3 (_N23975), + .I4 (_N23906), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 [2] )); // LUT = (ID&~I3&~I4)|(I2&I3&~I4)|(I0&~I3&I4)|(I1&I3&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_163[9] */ #( .INIT(32'b11001100101010101111000010101010)) \dqs_gate_ctrl_adj_163[9] ( - .Z (_N24254), + .Z (_N24033), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 [2] ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3 [2] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3 [3] ), - .I3 (_N24196), - .I4 (_N24127), + .I3 (_N23975), + .I4 (_N23906), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 [3] )); // LUT = (ID&~I3&~I4)|(I2&I3&~I4)|(I0&~I3&I4)|(I1&I3&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_163[10] */ #( .INIT(32'b11110000101010101010101011001100)) \dqs_gate_ctrl_adj_163[10] ( - .Z (_N24255), + .Z (_N24034), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 [3] ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [0] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3 [3] ), - .I3 (_N24196), - .I4 (_N24127), + .I3 (_N23975), + .I4 (_N23906), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [0] )); // LUT = (I1&~I3&~I4)|(ID&I3&~I4)|(I0&~I3&I4)|(I2&I3&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_163[11] */ #( .INIT(32'b10101010110011001010101011110000)) \dqs_gate_ctrl_adj_163[11] ( - .Z (_N24256), + .Z (_N24035), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [0] ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [0] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [1] ), - .I3 (_N24196), - .I4 (_N24127), + .I3 (_N23975), + .I4 (_N23906), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [1] )); // LUT = (I2&~I3&~I4)|(ID&I3&~I4)|(I1&~I3&I4)|(I0&I3&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_163[12] */ #( .INIT(32'b11100010111000101110111000100010)) \dqs_gate_ctrl_adj_163[12] ( - .Z (_N24257), + .Z (_N24036), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 [1] ), - .I1 (_N24196), + .I1 (_N23975), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3 [1] ), .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3 [2] ), - .I4 (_N24127), + .I4 (_N23906), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 [2] )); // LUT = (I1&I3&~I4)|(ID&~I1&~I4)|(I1&I2&I4)|(I0&~I1&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_163[13] */ #( .INIT(32'b11100010111000101110111000100010)) \dqs_gate_ctrl_adj_163[13] ( - .Z (_N24258), + .Z (_N24037), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 [2] ), - .I1 (_N24196), + .I1 (_N23975), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3 [2] ), .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3 [3] ), - .I4 (_N24127), + .I4 (_N23906), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 [3] )); // LUT = (I1&I3&~I4)|(ID&~I1&~I4)|(I1&I2&I4)|(I0&~I1&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_163[14] */ #( .INIT(32'b11100010111000101011101110001000)) \dqs_gate_ctrl_adj_163[14] ( - .Z (_N24259), + .Z (_N24038), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 [3] ), - .I1 (_N24196), + .I1 (_N23975), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3 [3] ), .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [0] ), - .I4 (_N24127), + .I4 (_N23906), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [0] )); // LUT = (~I1&I3&~I4)|(ID&I1&~I4)|(I1&I2&I4)|(I0&~I1&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_163[15] */ #( .INIT(32'b10111000101110001011101110001000)) \dqs_gate_ctrl_adj_163[15] ( - .Z (_N24260), + .Z (_N24039), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [0] ), - .I1 (_N24196), + .I1 (_N23975), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [0] ), .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [1] ), - .I4 (_N24127), + .I4 (_N23906), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [1] )); // LUT = (~I1&I3&~I4)|(ID&I1&~I4)|(~I1&I2&I4)|(I0&I1&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_167[0] */ #( .INIT(32'b11001100101010101111000010101010)) \dqs_gate_ctrl_adj_167[0] ( - .Z (_N24309), + .Z (_N24088), .I0 (dqs_gate_pulse_r2[3]), .I1 (dqs_gate_pulse_r4[3]), .I2 (dqs_gate_pulse_r3[0]), - .I3 (_N24196), - .I4 (_N24127), + .I3 (_N23975), + .I4 (_N23906), .ID (dqs_gate_pulse_r1[0])); // LUT = (ID&~I3&~I4)|(I2&I3&~I4)|(I0&~I3&I4)|(I1&I3&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_167[1] */ #( .INIT(32'b11001100101010101111000010101010)) \dqs_gate_ctrl_adj_167[1] ( - .Z (_N24310), + .Z (_N24089), .I0 (dqs_gate_pulse_r1[0]), .I1 (dqs_gate_pulse_r3[0]), .I2 (dqs_gate_pulse_r3[1]), - .I3 (_N24196), - .I4 (_N24127), + .I3 (_N23975), + .I4 (_N23906), .ID (dqs_gate_pulse_r1[1])); // LUT = (ID&~I3&~I4)|(I2&I3&~I4)|(I0&~I3&I4)|(I1&I3&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_167[4] */ #( .INIT(32'b11001100101010101111000010101010)) \dqs_gate_ctrl_adj_167[4] ( - .Z (_N24313), + .Z (_N24092), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [3] ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4 [3] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3 [0] ), - .I3 (_N24196), - .I4 (_N24127), + .I3 (_N23975), + .I4 (_N23906), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 [0] )); // LUT = (ID&~I3&~I4)|(I2&I3&~I4)|(I0&~I3&I4)|(I1&I3&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_167[5] */ #( .INIT(32'b11001100101010101111000010101010)) \dqs_gate_ctrl_adj_167[5] ( - .Z (_N24314), + .Z (_N24093), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 [0] ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3 [0] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3 [1] ), - .I3 (_N24196), - .I4 (_N24127), + .I3 (_N23975), + .I4 (_N23906), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 [1] )); // LUT = (ID&~I3&~I4)|(I2&I3&~I4)|(I0&~I3&I4)|(I1&I3&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_167[8] */ #( .INIT(32'b11001100101010101111000010101010)) \dqs_gate_ctrl_adj_167[8] ( - .Z (_N24317), + .Z (_N24096), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [3] ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4 [3] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3 [0] ), - .I3 (_N24196), - .I4 (_N24127), + .I3 (_N23975), + .I4 (_N23906), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 [0] )); // LUT = (ID&~I3&~I4)|(I2&I3&~I4)|(I0&~I3&I4)|(I1&I3&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_167[9] */ #( .INIT(32'b11001100101010101111000010101010)) \dqs_gate_ctrl_adj_167[9] ( - .Z (_N24318), + .Z (_N24097), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 [0] ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3 [0] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3 [1] ), - .I3 (_N24196), - .I4 (_N24127), + .I3 (_N23975), + .I4 (_N23906), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 [1] )); // LUT = (ID&~I3&~I4)|(I2&I3&~I4)|(I0&~I3&I4)|(I1&I3&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_167[12] */ #( .INIT(32'b11101110001000101110001011100010)) \dqs_gate_ctrl_adj_167[12] ( - .Z (_N24321), + .Z (_N24100), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [3] ), - .I1 (_N24196), + .I1 (_N23975), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3 [0] ), .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4 [3] ), - .I4 (_N24127), + .I4 (_N23906), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 [0] )); // LUT = (I1&I2&~I4)|(ID&~I1&~I4)|(I1&I3&I4)|(I0&~I1&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_167[13] */ #( .INIT(32'b11100010111000101110111000100010)) \dqs_gate_ctrl_adj_167[13] ( - .Z (_N24322), + .Z (_N24101), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 [0] ), - .I1 (_N24196), + .I1 (_N23975), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3 [0] ), .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3 [1] ), - .I4 (_N24127), + .I4 (_N23906), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 [1] )); // LUT = (I1&I3&~I4)|(ID&~I1&~I4)|(I1&I2&I4)|(I0&~I1&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_170[0] */ #( .INIT(32'b10101010110011001111000010101010)) \dqs_gate_ctrl_adj_170[0] ( - .Z (_N24357), + .Z (_N24136), .I0 (dqs_gate_pulse_r3[3]), .I1 (dqs_gate_pulse_src[0]), .I2 (dqs_gate_pulse_r2[0]), - .I3 (_N24196), - .I4 (_N24127), + .I3 (_N23975), + .I4 (_N23906), .ID (dqs_gate_pulse_r1[3])); // LUT = (ID&~I3&~I4)|(I2&I3&~I4)|(I1&~I3&I4)|(I0&I3&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_170[1] */ #( .INIT(32'b10101010111100001010101011001100)) \dqs_gate_ctrl_adj_170[1] ( - .Z (_N24358), + .Z (_N24137), .I0 (dqs_gate_pulse_r2[0]), .I1 (dqs_gate_pulse_src[0]), .I2 (dqs_gate_pulse_src[1]), - .I3 (_N24196), - .I4 (_N24127), + .I3 (_N23975), + .I4 (_N23906), .ID (dqs_gate_pulse_r2[1])); // LUT = (I1&~I3&~I4)|(ID&I3&~I4)|(I2&~I3&I4)|(I0&I3&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_170[2] */ #( .INIT(32'b10101010111100001010101011001100)) \dqs_gate_ctrl_adj_170[2] ( - .Z (_N24359), + .Z (_N24138), .I0 (dqs_gate_pulse_r2[1]), .I1 (dqs_gate_pulse_src[1]), .I2 (dqs_gate_pulse_src[2]), - .I3 (_N24196), - .I4 (_N24127), + .I3 (_N23975), + .I4 (_N23906), .ID (dqs_gate_pulse_r2[2])); // LUT = (I1&~I3&~I4)|(ID&I3&~I4)|(I2&~I3&I4)|(I0&I3&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_170[3] */ #( .INIT(32'b10101010111100001010101011001100)) \dqs_gate_ctrl_adj_170[3] ( - .Z (_N24360), + .Z (_N24139), .I0 (dqs_gate_pulse_r2[2]), .I1 (dqs_gate_pulse_src[2]), .I2 (dqs_gate_pulse_src[3]), - .I3 (_N24196), - .I4 (_N24127), + .I3 (_N23975), + .I4 (_N23906), .ID (dqs_gate_pulse_r2[3])); // LUT = (I1&~I3&~I4)|(ID&I3&~I4)|(I2&~I3&I4)|(I0&I3&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_170[4] */ #( .INIT(32'b10101010110011001111000010101010)) \dqs_gate_ctrl_adj_170[4] ( - .Z (_N24361), + .Z (_N24140), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3 [3] ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [0] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [0] ), - .I3 (_N24196), - .I4 (_N24127), + .I3 (_N23975), + .I4 (_N23906), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 [3] )); // LUT = (ID&~I3&~I4)|(I2&I3&~I4)|(I1&~I3&I4)|(I0&I3&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_170[5] */ #( .INIT(32'b10101010111100001010101011001100)) \dqs_gate_ctrl_adj_170[5] ( - .Z (_N24362), + .Z (_N24141), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [0] ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [0] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [1] ), - .I3 (_N24196), - .I4 (_N24127), + .I3 (_N23975), + .I4 (_N23906), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [1] )); // LUT = (I1&~I3&~I4)|(ID&I3&~I4)|(I2&~I3&I4)|(I0&I3&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_170[6] */ #( .INIT(32'b10101010111100001010101011001100)) \dqs_gate_ctrl_adj_170[6] ( - .Z (_N24363), + .Z (_N24142), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [1] ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [1] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [2] ), - .I3 (_N24196), - .I4 (_N24127), + .I3 (_N23975), + .I4 (_N23906), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [2] )); // LUT = (I1&~I3&~I4)|(ID&I3&~I4)|(I2&~I3&I4)|(I0&I3&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_170[7] */ #( .INIT(32'b10101010111100001010101011001100)) \dqs_gate_ctrl_adj_170[7] ( - .Z (_N24364), + .Z (_N24143), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [2] ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [2] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [3] ), - .I3 (_N24196), - .I4 (_N24127), + .I3 (_N23975), + .I4 (_N23906), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [3] )); // LUT = (I1&~I3&~I4)|(ID&I3&~I4)|(I2&~I3&I4)|(I0&I3&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_170[8] */ #( .INIT(32'b10101010110011001111000010101010)) \dqs_gate_ctrl_adj_170[8] ( - .Z (_N24365), + .Z (_N24144), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3 [3] ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [0] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [0] ), - .I3 (_N24196), - .I4 (_N24127), + .I3 (_N23975), + .I4 (_N23906), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 [3] )); // LUT = (ID&~I3&~I4)|(I2&I3&~I4)|(I1&~I3&I4)|(I0&I3&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_170[9] */ #( .INIT(32'b10101010111100001010101011001100)) \dqs_gate_ctrl_adj_170[9] ( - .Z (_N24366), + .Z (_N24145), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [0] ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [0] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [1] ), - .I3 (_N24196), - .I4 (_N24127), + .I3 (_N23975), + .I4 (_N23906), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [1] )); // LUT = (I1&~I3&~I4)|(ID&I3&~I4)|(I2&~I3&I4)|(I0&I3&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_170[10] */ #( .INIT(32'b10101010111100001010101011001100)) \dqs_gate_ctrl_adj_170[10] ( - .Z (_N24367), + .Z (_N24146), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [1] ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [1] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [2] ), - .I3 (_N24196), - .I4 (_N24127), + .I3 (_N23975), + .I4 (_N23906), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [2] )); // LUT = (I1&~I3&~I4)|(ID&I3&~I4)|(I2&~I3&I4)|(I0&I3&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_170[11] */ #( .INIT(32'b10101010111100001010101011001100)) \dqs_gate_ctrl_adj_170[11] ( - .Z (_N24368), + .Z (_N24147), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [2] ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [2] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [3] ), - .I3 (_N24196), - .I4 (_N24127), + .I3 (_N23975), + .I4 (_N23906), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [3] )); // LUT = (I1&~I3&~I4)|(ID&I3&~I4)|(I2&~I3&I4)|(I0&I3&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_170[12] */ #( .INIT(32'b10101111101000001100101011001010)) \dqs_gate_ctrl_adj_170[12] ( - .Z (_N24369), + .Z (_N24148), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3 [3] ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [0] ), - .I2 (_N24196), + .I2 (_N23975), .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [0] ), - .I4 (_N24127), + .I4 (_N23906), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 [3] )); // LUT = (ID&~I2&~I4)|(I1&I2&~I4)|(~I2&I3&I4)|(I0&I2&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_170[13] */ #( .INIT(32'b10111011100010001011100010111000)) \dqs_gate_ctrl_adj_170[13] ( - .Z (_N24370), + .Z (_N24149), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [0] ), - .I1 (_N24196), + .I1 (_N23975), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [0] ), .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [1] ), - .I4 (_N24127), + .I4 (_N23906), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [1] )); // LUT = (~I1&I2&~I4)|(ID&I1&~I4)|(~I1&I3&I4)|(I0&I1&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_170[14] */ #( .INIT(32'b10111011100010001011100010111000)) \dqs_gate_ctrl_adj_170[14] ( - .Z (_N24371), + .Z (_N24150), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [1] ), - .I1 (_N24196), + .I1 (_N23975), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [1] ), .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [2] ), - .I4 (_N24127), + .I4 (_N23906), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [2] )); // LUT = (~I1&I2&~I4)|(ID&I1&~I4)|(~I1&I3&I4)|(I0&I1&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_170[15] */ #( .INIT(32'b10111011100010001011100010111000)) \dqs_gate_ctrl_adj_170[15] ( - .Z (_N24372), + .Z (_N24151), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [2] ), - .I1 (_N24196), + .I1 (_N23975), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [2] ), .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [3] ), - .I4 (_N24127), + .I4 (_N23906), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [3] )); // LUT = (~I1&I2&~I4)|(ID&I1&~I4)|(~I1&I3&I4)|(I0&I1&I4) ; @@ -125612,198 +125545,198 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3 .INIT(32'b11001010110010101010111110100000)) \dqs_gate_ctrl_adj_172[0] ( .Z (dqs_gate_ctrl_adj[0]), - .I0 (_N24245), - .I1 (_N24197), - .I2 (_N24174), - .I3 (_N24357), - .I4 (_N24150), - .ID (_N24309)); + .I0 (_N24024), + .I1 (_N23976), + .I2 (_N23953), + .I3 (_N24136), + .I4 (_N23929), + .ID (_N24088)); // LUT = (~I2&I3&~I4)|(ID&I2&~I4)|(I0&~I2&I4)|(I1&I2&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_172[1] */ #( .INIT(32'b11001010110010101010111110100000)) \dqs_gate_ctrl_adj_172[1] ( .Z (dqs_gate_ctrl_adj[1]), - .I0 (_N24246), - .I1 (_N24198), - .I2 (_N24174), - .I3 (_N24358), - .I4 (_N24150), - .ID (_N24310)); + .I0 (_N24025), + .I1 (_N23977), + .I2 (_N23953), + .I3 (_N24137), + .I4 (_N23929), + .ID (_N24089)); // LUT = (~I2&I3&~I4)|(ID&I2&~I4)|(I0&~I2&I4)|(I1&I2&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_172[2] */ #( .INIT(32'b11100010111000101011101110001000)) \dqs_gate_ctrl_adj_172[2] ( .Z (dqs_gate_ctrl_adj[2]), - .I0 (_N24247), - .I1 (_N24174), - .I2 (_N24199), - .I3 (_N24359), - .I4 (_N24150), - .ID (_N24245)); + .I0 (_N24026), + .I1 (_N23953), + .I2 (_N23978), + .I3 (_N24138), + .I4 (_N23929), + .ID (_N24024)); // LUT = (~I1&I3&~I4)|(ID&I1&~I4)|(I1&I2&I4)|(I0&~I1&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_172[3] */ #( .INIT(32'b11100010111000101011101110001000)) \dqs_gate_ctrl_adj_172[3] ( .Z (dqs_gate_ctrl_adj[3]), - .I0 (_N24248), - .I1 (_N24174), - .I2 (_N24200), - .I3 (_N24360), - .I4 (_N24150), - .ID (_N24246)); + .I0 (_N24027), + .I1 (_N23953), + .I2 (_N23979), + .I3 (_N24139), + .I4 (_N23929), + .ID (_N24025)); // LUT = (~I1&I3&~I4)|(ID&I1&~I4)|(I1&I2&I4)|(I0&~I1&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_172[4] */ #( .INIT(32'b11001010110010101010111110100000)) \dqs_gate_ctrl_adj_172[4] ( .Z (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj [0] ), - .I0 (_N24249), - .I1 (_N24201), - .I2 (_N24174), - .I3 (_N24361), - .I4 (_N24150), - .ID (_N24313)); + .I0 (_N24028), + .I1 (_N23980), + .I2 (_N23953), + .I3 (_N24140), + .I4 (_N23929), + .ID (_N24092)); // LUT = (~I2&I3&~I4)|(ID&I2&~I4)|(I0&~I2&I4)|(I1&I2&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_172[5] */ #( .INIT(32'b11001010110010101010111110100000)) \dqs_gate_ctrl_adj_172[5] ( .Z (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj [1] ), - .I0 (_N24250), - .I1 (_N24202), - .I2 (_N24174), - .I3 (_N24362), - .I4 (_N24150), - .ID (_N24314)); + .I0 (_N24029), + .I1 (_N23981), + .I2 (_N23953), + .I3 (_N24141), + .I4 (_N23929), + .ID (_N24093)); // LUT = (~I2&I3&~I4)|(ID&I2&~I4)|(I0&~I2&I4)|(I1&I2&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_172[6] */ #( .INIT(32'b11100010111000101011101110001000)) \dqs_gate_ctrl_adj_172[6] ( .Z (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj [2] ), - .I0 (_N24251), - .I1 (_N24174), - .I2 (_N24203), - .I3 (_N24363), - .I4 (_N24150), - .ID (_N24249)); + .I0 (_N24030), + .I1 (_N23953), + .I2 (_N23982), + .I3 (_N24142), + .I4 (_N23929), + .ID (_N24028)); // LUT = (~I1&I3&~I4)|(ID&I1&~I4)|(I1&I2&I4)|(I0&~I1&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_172[7] */ #( .INIT(32'b11100010111000101011101110001000)) \dqs_gate_ctrl_adj_172[7] ( .Z (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj [3] ), - .I0 (_N24252), - .I1 (_N24174), - .I2 (_N24204), - .I3 (_N24364), - .I4 (_N24150), - .ID (_N24250)); + .I0 (_N24031), + .I1 (_N23953), + .I2 (_N23983), + .I3 (_N24143), + .I4 (_N23929), + .ID (_N24029)); // LUT = (~I1&I3&~I4)|(ID&I1&~I4)|(I1&I2&I4)|(I0&~I1&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_172[8] */ #( .INIT(32'b11001010110010101010111110100000)) \dqs_gate_ctrl_adj_172[8] ( .Z (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj [0] ), - .I0 (_N24253), - .I1 (_N24205), - .I2 (_N24174), - .I3 (_N24365), - .I4 (_N24150), - .ID (_N24317)); + .I0 (_N24032), + .I1 (_N23984), + .I2 (_N23953), + .I3 (_N24144), + .I4 (_N23929), + .ID (_N24096)); // LUT = (~I2&I3&~I4)|(ID&I2&~I4)|(I0&~I2&I4)|(I1&I2&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_172[9] */ #( .INIT(32'b11001010110010101010111110100000)) \dqs_gate_ctrl_adj_172[9] ( .Z (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj [1] ), - .I0 (_N24254), - .I1 (_N24206), - .I2 (_N24174), - .I3 (_N24366), - .I4 (_N24150), - .ID (_N24318)); + .I0 (_N24033), + .I1 (_N23985), + .I2 (_N23953), + .I3 (_N24145), + .I4 (_N23929), + .ID (_N24097)); // LUT = (~I2&I3&~I4)|(ID&I2&~I4)|(I0&~I2&I4)|(I1&I2&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_172[10] */ #( .INIT(32'b11100010111000101011101110001000)) \dqs_gate_ctrl_adj_172[10] ( .Z (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj [2] ), - .I0 (_N24255), - .I1 (_N24174), - .I2 (_N24207), - .I3 (_N24367), - .I4 (_N24150), - .ID (_N24253)); + .I0 (_N24034), + .I1 (_N23953), + .I2 (_N23986), + .I3 (_N24146), + .I4 (_N23929), + .ID (_N24032)); // LUT = (~I1&I3&~I4)|(ID&I1&~I4)|(I1&I2&I4)|(I0&~I1&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_172[11] */ #( .INIT(32'b11100010111000101011101110001000)) \dqs_gate_ctrl_adj_172[11] ( .Z (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj [3] ), - .I0 (_N24256), - .I1 (_N24174), - .I2 (_N24208), - .I3 (_N24368), - .I4 (_N24150), - .ID (_N24254)); + .I0 (_N24035), + .I1 (_N23953), + .I2 (_N23987), + .I3 (_N24147), + .I4 (_N23929), + .ID (_N24033)); // LUT = (~I1&I3&~I4)|(ID&I1&~I4)|(I1&I2&I4)|(I0&~I1&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_172[12] */ #( .INIT(32'b11001010110010101010111110100000)) \dqs_gate_ctrl_adj_172[12] ( .Z (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj [0] ), - .I0 (_N24257), - .I1 (_N24209), - .I2 (_N24174), - .I3 (_N24369), - .I4 (_N24150), - .ID (_N24321)); + .I0 (_N24036), + .I1 (_N23988), + .I2 (_N23953), + .I3 (_N24148), + .I4 (_N23929), + .ID (_N24100)); // LUT = (~I2&I3&~I4)|(ID&I2&~I4)|(I0&~I2&I4)|(I1&I2&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_172[13] */ #( .INIT(32'b11001010110010101010111110100000)) \dqs_gate_ctrl_adj_172[13] ( .Z (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj [1] ), - .I0 (_N24258), - .I1 (_N24210), - .I2 (_N24174), - .I3 (_N24370), - .I4 (_N24150), - .ID (_N24322)); + .I0 (_N24037), + .I1 (_N23989), + .I2 (_N23953), + .I3 (_N24149), + .I4 (_N23929), + .ID (_N24101)); // LUT = (~I2&I3&~I4)|(ID&I2&~I4)|(I0&~I2&I4)|(I1&I2&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_172[14] */ #( .INIT(32'b11100010111000101011101110001000)) \dqs_gate_ctrl_adj_172[14] ( .Z (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj [2] ), - .I0 (_N24259), - .I1 (_N24174), - .I2 (_N24211), - .I3 (_N24371), - .I4 (_N24150), - .ID (_N24257)); + .I0 (_N24038), + .I1 (_N23953), + .I2 (_N23990), + .I3 (_N24150), + .I4 (_N23929), + .ID (_N24036)); // LUT = (~I1&I3&~I4)|(ID&I1&~I4)|(I1&I2&I4)|(I0&~I1&I4) ; GTP_LUT5M /* \dqs_gate_ctrl_adj_172[15] */ #( .INIT(32'b11100010111000101011101110001000)) \dqs_gate_ctrl_adj_172[15] ( .Z (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj [3] ), - .I0 (_N24260), - .I1 (_N24174), - .I2 (_N24212), - .I3 (_N24372), - .I4 (_N24150), - .ID (_N24258)); + .I0 (_N24039), + .I1 (_N23953), + .I2 (_N23991), + .I3 (_N24151), + .I4 (_N23929), + .ID (_N24037)); // LUT = (~I1&I3&~I4)|(ID&I1&~I4)|(I1&I2&I4)|(I0&~I1&I4) ; GTP_LUT5 /* dqs_gate_ctrl_adj_198_5 */ #( .INIT(32'b11111111111111010101010100111111)) dqs_gate_ctrl_adj_198_5 ( - .Z (_N24127), + .Z (_N23906), .I0 (mc_rl[0]), .I1 (mc_rl[1]), .I2 (mc_rl[2]), @@ -125994,17 +125927,17 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3 \dqs_gate_pulse_src_4[1] ( .Z (dqs_gate_pulse_src[1]), .I0 (dqs_gate_pulse_src_nxt_r[1]), - .I1 (_N96702)); + .I1 (_N97460)); // LUT = (I0)|(I1) ; GTP_LUT4 /* \dqs_gate_pulse_src_4[1]_1 */ #( .INIT(16'b1111110111101100)) \dqs_gate_pulse_src_4[1]_1 ( - .Z (_N96702), + .Z (_N97460), .I0 (coarse_slip_step[1]), .I1 (read_en_slipped[0]), - .I2 (_N22876), - .I3 (_N22878)); + .I2 (_N22851), + .I3 (_N22853)); // LUT = (I1)|(~I0&I3)|(I0&I2) ; GTP_LUT3 /* \dqs_gate_pulse_src_4[2]_3 */ #( @@ -126013,7 +125946,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3 .Z (dqs_gate_pulse_src[2]), .I0 (dqs_gate_pulse_src_nxt_r[2]), .I1 (read_en_slipped[2]), - .I2 (_N96702)); + .I2 (_N97460)); // LUT = (I0)|(I1)|(I2) ; GTP_LUT3 /* dqs_gate_pulse_src_nxt_4 */ #( @@ -126022,7 +125955,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3 .Z (dqs_gate_pulse_src_nxt[1]), .I0 (read_en_slipped[3]), .I1 (read_en_slipped[2]), - .I2 (_N96702)); + .I2 (_N97460)); // LUT = (I0&~I2)|(I1&~I2) ; GTP_DFF_C /* \dqs_gate_pulse_src_nxt_r[0] */ #( @@ -126062,19 +125995,19 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3 .Q (dqs_gate_vld), .C (N1), .CLK (ddrphy_clkin), - .D (_N103362)); + .D (_N104174)); // defparam dqs_gate_vld_vname.orig_name = dqs_gate_vld; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3.vp:346 GTP_LUT5 /* dqs_gate_vld_ce_mux */ #( .INIT(32'b11101110000000001110111011100000)) dqs_gate_vld_ce_mux ( - .Z (_N103362), + .Z (_N104174), .I0 (gatecal_start), .I1 (rddata_cal), .I2 (dqs_gate_vld), .I3 (N194_inv), - .I4 (_N95788)); + .I4 (_N96568)); // LUT = (I0&I3)|(I1&I3)|(I0&I2&~I4)|(I1&I2&~I4) ; GTP_DFF_C /* \read_cmd_comb_r[0] */ #( @@ -126160,7 +126093,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3 GTP_LUT4 /* \read_en_slipped_5[0] */ #( .INIT(16'b0011001000010000)) \read_en_slipped_5[0] ( - .Z (_N22871), + .Z (_N22846), .I0 (coarse_slip_step[3]), .I1 (coarse_slip_step[0]), .I2 (read_cmd_mux_r1[2]), @@ -126170,7 +126103,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3 GTP_LUT4 /* \read_en_slipped_5[2]_1 */ #( .INIT(16'b0011001000010000)) \read_en_slipped_5[2]_1 ( - .Z (_N22873), + .Z (_N22848), .I0 (coarse_slip_step[3]), .I1 (coarse_slip_step[0]), .I2 (read_cmd_mux[0]), @@ -126180,11 +126113,11 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3 GTP_LUT5M /* \read_en_slipped_6[0] */ #( .INIT(32'b10111011100010000111001101000000)) \read_en_slipped_6[0] ( - .Z (_N22875), + .Z (_N22850), .I0 (read_cmd_mux[0]), .I1 (coarse_slip_step[2]), .I2 (read_cmd_mux_r2[2]), - .I3 (_N22871), + .I3 (_N22846), .I4 (coarse_slip_step[3]), .ID (coarse_slip_step[0])); // LUT = (~ID&I1&I2&~I4)|(I0&I1&I4)|(~I1&I3) ; @@ -126192,7 +126125,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3 GTP_LUT5M /* \read_en_slipped_6[1] */ #( .INIT(32'b00100010000000001110001000000000)) \read_en_slipped_6[1] ( - .Z (_N22876), + .Z (_N22851), .I0 (read_cmd_mux_r3[2]), .I1 (coarse_slip_step[2]), .I2 (read_cmd_mux_r2[2]), @@ -126204,19 +126137,19 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3 GTP_LUT5M /* \read_en_slipped_6[2] */ #( .INIT(32'b10001000110110001010101010101010)) \read_en_slipped_6[2] ( - .Z (_N22877), + .Z (_N22852), .I0 (coarse_slip_step[3]), .I1 (read_cmd_mux[2]), .I2 (read_cmd_mux_r1[0]), .I3 (coarse_slip_step[0]), .I4 (coarse_slip_step[2]), - .ID (_N22873)); + .ID (_N22848)); // LUT = (ID&~I4)|(~I0&I2&~I3&I4)|(I0&I1&I4) ; GTP_LUT5M /* \read_en_slipped_6[3]_1 */ #( .INIT(32'b00100010000000001110001000000000)) \read_en_slipped_6[3]_1 ( - .Z (_N22878), + .Z (_N22853), .I0 (read_cmd_mux_r2[0]), .I1 (coarse_slip_step[2]), .I2 (read_cmd_mux_r1[0]), @@ -126228,7 +126161,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3 GTP_LUT5 /* \read_en_slipped_9[0] */ #( .INIT(32'b10110011101000101001000110000000)) \read_en_slipped_9[0] ( - .Z (_N22887), + .Z (_N22862), .I0 (coarse_slip_step[3]), .I1 (coarse_slip_step[0]), .I2 (read_cmd_mux[0]), @@ -126239,7 +126172,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3 GTP_LUT5 /* \read_en_slipped_9[2] */ #( .INIT(32'b10110011101000101001000110000000)) \read_en_slipped_9[2] ( - .Z (_N22889), + .Z (_N22864), .I0 (coarse_slip_step[3]), .I1 (coarse_slip_step[0]), .I2 (read_cmd_mux[2]), @@ -126250,8 +126183,8 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3 GTP_LUT5M /* \read_en_slipped_13[0] */ #( .INIT(32'b10101010101010100000000011100100)) \read_en_slipped_13[0] ( - .Z (_N22903), - .I0 (_N22887), + .Z (_N22878), + .I0 (_N22862), .I1 (read_cmd_mux[0]), .I2 (read_cmd_mux_r2[0]), .I3 (coarse_slip_step[0]), @@ -126262,8 +126195,8 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3 GTP_LUT5M /* \read_en_slipped_13[2] */ #( .INIT(32'b10101010101010100000000011100100)) \read_en_slipped_13[2] ( - .Z (_N22905), - .I0 (_N22889), + .Z (_N22880), + .I0 (_N22864), .I1 (read_cmd_mux[2]), .I2 (read_cmd_mux_r2[2]), .I3 (coarse_slip_step[0]), @@ -126274,7 +126207,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3 GTP_LUT5M /* \read_en_slipped_13[3] */ #( .INIT(32'b00100010000000001110001000000000)) \read_en_slipped_13[3] ( - .Z (_N22906), + .Z (_N22881), .I0 (read_cmd_mux_r2[2]), .I1 (coarse_slip_step[2]), .I2 (read_cmd_mux_r1[2]), @@ -126285,14 +126218,14 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3 GTP_MUX2LUT6 \read_en_slipped_14[0] ( .Z (read_en_slipped[0]), - .I0 (_N22903), - .I1 (_N22875), + .I0 (_N22878), + .I1 (_N22850), .S (coarse_slip_step[1])); GTP_MUX2LUT6 \read_en_slipped_14[2] ( .Z (read_en_slipped[2]), - .I0 (_N22905), - .I1 (_N22877), + .I0 (_N22880), + .I1 (_N22852), .S (coarse_slip_step[1])); GTP_LUT3 /* \read_en_slipped_14[3] */ #( @@ -126300,8 +126233,8 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3 \read_en_slipped_14[3] ( .Z (read_en_slipped[3]), .I0 (coarse_slip_step[1]), - .I1 (_N22878), - .I2 (_N22906)); + .I1 (_N22853), + .I2 (_N22881)); // LUT = (~I0&I2)|(I0&I1) ; @@ -126313,8 +126246,8 @@ module ipsxb_ddrphy_gatecal_v1_3 input [5:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg , input [5:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg , input N1, - input _N95825, - input _N96106, + input _N96676, + input _N96884, input ddrphy_clkin, input dqs_gate_check_pass, input dqs_gate_vld, @@ -126327,11 +126260,11 @@ module ipsxb_ddrphy_gatecal_v1_3 input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_gate_vld , output [2:0] N22, output [3:0] coarse_slip_step, - output [2:0] gate_state_next, output [5:0] gate_state_reg, output [2:0] read_clk_ctrl, - output _N96109, - output _N96110, + output _N25006, + output _N96887, + output _N96888, output dqs_gate_vld_r, output gate_adj_done, output gate_cal_error, @@ -126340,13 +126273,14 @@ module ipsxb_ddrphy_gatecal_v1_3 ); wire N70; wire [5:0] N81; - wire N139; + wire N138; wire [2:0] N281; wire N301; wire N327; wire [5:0] N328; wire [5:0] N389; wire [5:0] \N389_8.co ; + wire N431; wire N538; wire [2:0] N539; wire [6:0] N567; @@ -126355,32 +126289,27 @@ module ipsxb_ddrphy_gatecal_v1_3 wire _N6; wire _N10; wire _N17; - wire _N15881; - wire _N15882; - wire _N15883; - wire _N15884; - wire _N15885; - wire _N22668; - wire _N22669; - wire _N22670; - wire _N22671; - wire _N25192; - wire _N25195; - wire _N25196; - wire _N25197; - wire _N61697; - wire _N82115; - wire _N96583; - wire _N103340; - wire _N103341; - wire _N103342; + wire _N16436; + wire _N16437; + wire _N16438; + wire _N16439; + wire _N25001; + wire _N25004; + wire _N25005; + wire _N62726; + wire _N62811; + wire _N63109; + wire _N82919; + wire _N104152; + wire _N104153; + wire _N104154; wire [2:0] dgts_cnt; wire dqs_gate_vld_n; wire gate_check_pass_d; + wire [2:0] gate_state_next; wire [5:0] gate_value_lock; wire [2:0] gate_win_size; wire [5:0] golden_value; - wire [5:0] nb0; GTP_LUT4 /* \N22_10[2] */ #( .INIT(16'b0011001000000000)) @@ -126405,7 +126334,7 @@ module ipsxb_ddrphy_gatecal_v1_3 GTP_LUT5 /* \N52_6[0] */ #( .INIT(32'b01010101110000000101010111111111)) \N52_6[0] ( - .Z (_N25192), + .Z (_N25001), .I0 (gate_move_en), .I1 (gatecal_start), .I2 (N567[6]), @@ -126416,18 +126345,18 @@ module ipsxb_ddrphy_gatecal_v1_3 GTP_LUT5 /* \N52_7[0] */ #( .INIT(32'b00110011011100110000000001000000)) \N52_7[0] ( - .Z (_N25195), + .Z (_N25004), .I0 (dqs_gate_vld), .I1 (gate_state_reg[2]), .I2 (dqs_gate_vld_r), - .I3 (_N82115), - .I4 (_N25192)); + .I3 (_N82919), + .I4 (_N25001)); // LUT = (~I1&I4)|(~I0&I1&I2&~I3) ; GTP_LUT5M /* \N52_7[1] */ #( .INIT(32'b11111111000111111010101010101010)) \N52_7[1] ( - .Z (_N25196), + .Z (_N25005), .I0 (coarse_slip_step[3]), .I1 (dgts_cnt[2]), .I2 (dqs_gate_vld_r), @@ -126439,7 +126368,7 @@ module ipsxb_ddrphy_gatecal_v1_3 GTP_LUT5 /* \N52_7[2] */ #( .INIT(32'b11000000110010101100000011001111)) \N52_7[2] ( - .Z (_N25197), + .Z (_N25006), .I0 (gatecal_start), .I1 (N22[2]), .I2 (gate_state_reg[2]), @@ -126454,7 +126383,7 @@ module ipsxb_ddrphy_gatecal_v1_3 .I0 (gatecal_start), .I1 (gate_state_reg[1]), .I2 (gate_state_reg[0]), - .I3 (_N25195)); + .I3 (_N25004)); // LUT = (I0&I2)|(~I1&~I2&I3) ; GTP_LUT3 /* \N52_9[2]_2 */ #( @@ -126463,7 +126392,7 @@ module ipsxb_ddrphy_gatecal_v1_3 .Z (gate_state_next[2]), .I0 (gate_state_reg[1]), .I1 (gate_state_reg[0]), - .I2 (_N25197)); + .I2 (_N25006)); // LUT = ~I0&~I1&I2 ; GTP_LUT2 /* N55 */ #( @@ -126478,7 +126407,7 @@ module ipsxb_ddrphy_gatecal_v1_3 GTP_LUT3 /* N70_1 */ #( .INIT(8'b01000000)) N70_1 ( - .Z (_N96109), + .Z (_N96887), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_gate_vld ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg [2] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r )); @@ -126491,142 +126420,119 @@ module ipsxb_ddrphy_gatecal_v1_3 .I0 (coarse_slip_step[3]), .I1 (gate_state_reg[1]), .I2 (gate_state_reg[0]), - .I3 (_N25195), - .I4 (_N25196)); + .I3 (_N25004), + .I4 (_N25005)); // LUT = (I0&I1&~I2)|(I0&~I2&~I3&I4) ; - GTP_LUT5CARRY /* N81_1_0 */ #( - .INIT(32'b11001100110011000000000000000000), - .ID_TO_LUT("FALSE"), - .CIN_TO_LUT("FALSE"), - .I4_TO_CARRY("FALSE"), - .I4_TO_LUT("FALSE")) - N81_1_0 ( - .COUT (_N15881), - .Z (), - .CIN (), - .I0 (), - .I1 (read_clk_ctrl[0]), - .I2 (), - .I3 (), - .I4 (), - .ID ()); - // LUT = I1 ; - // CARRY = (1'b0) ? CIN : (I1) ; - // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_gatecal_v1_3.vp:443 - GTP_LUT5CARRY /* N81_1_1 */ #( - .INIT(32'b01100110011001101100110011001100), + .INIT(32'b01100110011001100000000000000000), .ID_TO_LUT("FALSE"), - .CIN_TO_LUT("TRUE"), + .CIN_TO_LUT("FALSE"), .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N81_1_1 ( - .COUT (_N15882), + .COUT (_N16436), .Z (N81[1]), - .CIN (_N15881), - .I0 (), + .CIN (), + .I0 (read_clk_ctrl[0]), .I1 (read_clk_ctrl[1]), .I2 (), .I3 (), - .I4 (1'b0), + .I4 (1'b1), .ID ()); - // LUT = I1^CIN ; - // CARRY = (I1) ? CIN : (I4) ; + // LUT = I1^I0 ; + // CARRY = (1'b0) ? CIN : (I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_gatecal_v1_3.vp:443 GTP_LUT5CARRY /* N81_1_2 */ #( - .INIT(32'b01101111011000001100110011001100), + .INIT(32'b01111000011110001000000010000000), .ID_TO_LUT("FALSE"), - .CIN_TO_LUT("TRUE"), + .CIN_TO_LUT("FALSE"), .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N81_1_2 ( - .COUT (_N15883), - .Z (_N22668), - .CIN (_N15882), - .I0 (), - .I1 (coarse_slip_step[0]), - .I2 (_N96583), - .I3 (golden_value[2]), + .COUT (_N16437), + .Z (N81[2]), + .CIN (_N16436), + .I0 (read_clk_ctrl[0]), + .I1 (read_clk_ctrl[1]), + .I2 (coarse_slip_step[0]), + .I3 (), .I4 (1'b0), .ID ()); - // LUT = (~I2&I3)|(CIN&~I1&I2)|(~CIN&I1&I2) ; - // CARRY = (I1) ? CIN : (I4) ; + // LUT = (I0&I1&~I2)|(~I1&I2)|(~I0&I2) ; + // CARRY = (I0&I1&I2) ? CIN : (I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_gatecal_v1_3.vp:443 GTP_LUT5CARRY /* N81_1_3 */ #( - .INIT(32'b01101111011000001100110011001100), + .INIT(32'b01100110011001101100110011001100), .ID_TO_LUT("FALSE"), .CIN_TO_LUT("TRUE"), .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N81_1_3 ( - .COUT (_N15884), - .Z (_N22669), - .CIN (_N15883), + .COUT (_N16438), + .Z (N81[3]), + .CIN (_N16437), .I0 (), .I1 (coarse_slip_step[1]), - .I2 (_N96583), - .I3 (golden_value[3]), + .I2 (), + .I3 (), .I4 (1'b0), .ID ()); - // LUT = (~I2&I3)|(CIN&~I1&I2)|(~CIN&I1&I2) ; + // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_gatecal_v1_3.vp:443 GTP_LUT5CARRY /* N81_1_4 */ #( - .INIT(32'b01101111011000001100110011001100), + .INIT(32'b01100110011001101100110011001100), .ID_TO_LUT("FALSE"), .CIN_TO_LUT("TRUE"), .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N81_1_4 ( - .COUT (_N15885), - .Z (_N22670), - .CIN (_N15884), + .COUT (_N16439), + .Z (N81[4]), + .CIN (_N16438), .I0 (), .I1 (coarse_slip_step[2]), - .I2 (_N96583), - .I3 (golden_value[4]), + .I2 (), + .I3 (), .I4 (1'b0), .ID ()); - // LUT = (~I2&I3)|(CIN&~I1&I2)|(~CIN&I1&I2) ; + // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_gatecal_v1_3.vp:443 GTP_LUT5CARRY /* N81_1_5 */ #( - .INIT(32'b01101111011000001100110011001100), + .INIT(32'b01100110011001101100110011001100), .ID_TO_LUT("FALSE"), .CIN_TO_LUT("TRUE"), .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N81_1_5 ( .COUT (), - .Z (_N22671), - .CIN (_N15885), + .Z (N81[5]), + .CIN (_N16439), .I0 (), .I1 (coarse_slip_step[3]), - .I2 (_N96583), - .I3 (golden_value[5]), + .I2 (), + .I3 (), .I4 (1'b0), .ID ()); - // LUT = (~I2&I3)|(CIN&~I1&I2)|(~CIN&I1&I2) ; + // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_gatecal_v1_3.vp:443 - GTP_LUT5 /* N139 */ #( - .INIT(32'b00000000000000001110101000000000)) - N139_vname ( - .Z (N139), + GTP_LUT3 /* N138 */ #( + .INIT(8'b11101010)) + N138_vname ( + .Z (N138), .I0 (gate_win_size[2]), .I1 (gate_win_size[1]), - .I2 (gate_win_size[0]), - .I3 (gate_state_next[2]), - .I4 (_N25195)); - // defparam N139_vname.orig_name = N139; - // LUT = (I0&I3&~I4)|(I1&I2&I3&~I4) ; - // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_gatecal_v1_3.vp:543 + .I2 (gate_win_size[0])); + // defparam N138_vname.orig_name = N138; + // LUT = (I0)|(I1&I2) ; GTP_LUT2 /* \N281[0]_1 */ #( .INIT(4'b1000)) @@ -126658,23 +126564,20 @@ module ipsxb_ddrphy_gatecal_v1_3 GTP_LUT3 /* N294_1 */ #( .INIT(8'b01000000)) N294_1 ( - .Z (_N96110), + .Z (_N96888), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_gate_vld ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg [2] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r )); // LUT = ~I0&I1&I2 ; - GTP_LUT5 /* N301 */ #( - .INIT(32'b01011100010111110000000000000000)) + GTP_LUT2 /* N301 */ #( + .INIT(4'b0100)) N301_vname ( .Z (N301), - .I0 (gatecal_start), - .I1 (gate_state_reg[1]), - .I2 (gate_state_reg[0]), - .I3 (_N25195), - .I4 (_N95825)); + .I0 (gate_state_next[0]), + .I1 (_N96676)); // defparam N301_vname.orig_name = N301; - // LUT = (~I2&~I3&I4)|(I1&~I2&I4)|(~I0&I2&I4) ; + // LUT = ~I0&I1 ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_gatecal_v1_3.vp:410 GTP_LUT2 /* N327 */ #( @@ -126682,175 +126585,177 @@ module ipsxb_ddrphy_gatecal_v1_3 N327_vname ( .Z (N327), .I0 (gate_move_en), - .I1 (_N95825)); + .I1 (_N96676)); // defparam N327_vname.orig_name = N327; // LUT = (I0)|(I1) ; - GTP_LUT5M /* N328_10 */ #( - .INIT(32'b01000100110011001000110011001100)) - N328_10 ( - .Z (_N96583), - .I0 (gatecal_start), - .I1 (gate_move_en), - .I2 (_N25195), - .I3 (_N95825), - .I4 (gate_state_reg[0]), - .ID (gate_state_reg[1])); - // LUT = (I1&~I2&~I4)|(ID&I1&~I4)|(~I0&I1&I4)|(I1&~I3) ; - GTP_LUT5 /* \N328_17[0] */ #( - .INIT(32'b01010101010101010011000000000000)) + .INIT(32'b00000111000001000100010001000100)) \N328_17[0] ( .Z (N328[0]), .I0 (read_clk_ctrl[0]), .I1 (gate_move_en), - .I2 (golden_value[0]), - .I3 (N301), - .I4 (_N96583)); - // LUT = (~I0&I4)|(~I1&I2&I3&~I4) ; + .I2 (gate_state_next[0]), + .I3 (golden_value[0]), + .I4 (_N96676)); + // LUT = (~I0&I1&~I4)|(~I0&I1&~I2)|(~I1&~I2&I3&I4) ; - GTP_LUT4 /* \N328_17[2] */ #( - .INIT(16'b1111000001000000)) + GTP_LUT5 /* \N328_17[2] */ #( + .INIT(32'b00001101000010001000100010001000)) \N328_17[2] ( .Z (N328[2]), .I0 (gate_move_en), - .I1 (N301), - .I2 (_N22668), - .I3 (_N96583)); - // LUT = (I2&I3)|(~I0&I1&I2) ; - - GTP_LUT4 /* \N328_17[3] */ #( - .INIT(16'b1111000001000000)) - \N328_17[3] ( - .Z (N328[3]), - .I0 (gate_move_en), - .I1 (N301), - .I2 (_N22669), - .I3 (_N96583)); - // LUT = (I2&I3)|(~I0&I1&I2) ; + .I1 (N81[2]), + .I2 (gate_state_next[0]), + .I3 (golden_value[2]), + .I4 (_N96676)); + // LUT = (I0&I1&~I4)|(I0&I1&~I2)|(~I0&~I2&I3&I4) ; - GTP_LUT4 /* \N328_17[4] */ #( - .INIT(16'b1111000001000000)) + GTP_LUT5 /* \N328_17[4] */ #( + .INIT(32'b00001101000010001000100010001000)) \N328_17[4] ( .Z (N328[4]), .I0 (gate_move_en), - .I1 (N301), - .I2 (_N22670), - .I3 (_N96583)); - // LUT = (I2&I3)|(~I0&I1&I2) ; - - GTP_LUT4 /* \N328_17[5] */ #( - .INIT(16'b1111000001000000)) - \N328_17[5] ( - .Z (N328[5]), - .I0 (gate_move_en), - .I1 (N301), - .I2 (_N22671), - .I3 (_N96583)); - // LUT = (I2&I3)|(~I0&I1&I2) ; + .I1 (N81[4]), + .I2 (gate_state_next[0]), + .I3 (golden_value[4]), + .I4 (_N96676)); + // LUT = (I0&I1&~I4)|(I0&I1&~I2)|(~I0&~I2&I3&I4) ; - GTP_LUT1 /* N389_4_inv */ #( - .INIT(2'b01)) - N389_4_inv ( - .Z (N389[0]), - .I0 (gate_value_lock[0])); - // LUT = ~I0 ; + GTP_LUT5CARRY /* \N389_8.fsub_0 */ #( + .INIT(32'b10101010101010100000000000000000), + .ID_TO_LUT("FALSE"), + .CIN_TO_LUT("FALSE"), + .I4_TO_CARRY("FALSE"), + .I4_TO_LUT("FALSE")) + \N389_8.fsub_0 ( + .COUT (\N389_8.co [0] ), + .Z (), + .CIN (), + .I0 (gate_value_lock[0]), + .I1 (), + .I2 (), + .I3 (), + .I4 (), + .ID ()); + // LUT = I0 ; + // CARRY = (1'b0) ? CIN : (I0) ; GTP_LUT5CARRY /* \N389_8.fsub_1 */ #( - .INIT(32'b10011001100110010000000000000000), + .INIT(32'b00001001100110010011001100110011), .ID_TO_LUT("FALSE"), - .CIN_TO_LUT("FALSE"), + .CIN_TO_LUT("TRUE"), .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) \N389_8.fsub_1 ( .COUT (\N389_8.co [1] ), - .Z (nb0[1]), - .CIN (), - .I0 (gate_value_lock[0]), + .Z (N389[1]), + .CIN (\N389_8.co [0] ), + .I0 (), .I1 (gate_value_lock[1]), - .I2 (), - .I3 (), - .I4 (1'b1), + .I2 (gatecal_start), + .I3 (N301), + .I4 (gate_value_lock[1]), .ID ()); - // LUT = ~I1^I0 ; - // CARRY = (1'b0) ? CIN : (I4) ; + // LUT = (~CIN&~I1&~I3)|(CIN&I1&~I3)|(~CIN&~I1&~I2)|(CIN&I1&~I2) ; + // CARRY = (~I1) ? CIN : (I4) ; GTP_LUT5CARRY /* \N389_8.fsub_2 */ #( - .INIT(32'b11100001111000011111111011111110), + .INIT(32'b00001001100110010011001100110011), .ID_TO_LUT("FALSE"), - .CIN_TO_LUT("FALSE"), + .CIN_TO_LUT("TRUE"), .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) \N389_8.fsub_2 ( .COUT (\N389_8.co [2] ), - .Z (nb0[2]), + .Z (N389[2]), .CIN (\N389_8.co [1] ), - .I0 (gate_value_lock[0]), - .I1 (gate_value_lock[1]), - .I2 (gate_value_lock[2]), - .I3 (), - .I4 (1'b0), + .I0 (), + .I1 (gate_value_lock[2]), + .I2 (gatecal_start), + .I3 (N301), + .I4 (gate_value_lock[2]), .ID ()); - // LUT = (~I0&~I1&~I2)|(I1&I2)|(I0&I2) ; - // CARRY = ((I2)|(I1)|(I0)) ? CIN : (I4) ; + // LUT = (~CIN&~I1&~I3)|(CIN&I1&~I3)|(~CIN&~I1&~I2)|(CIN&I1&~I2) ; + // CARRY = (~I1) ? CIN : (I4) ; GTP_LUT5CARRY /* \N389_8.fsub_3 */ #( - .INIT(32'b10011001100110010011001100110011), + .INIT(32'b00001001100110010011001100110011), .ID_TO_LUT("FALSE"), .CIN_TO_LUT("TRUE"), .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) \N389_8.fsub_3 ( .COUT (\N389_8.co [3] ), - .Z (nb0[3]), + .Z (N389[3]), .CIN (\N389_8.co [2] ), .I0 (), .I1 (gate_value_lock[3]), - .I2 (), - .I3 (), + .I2 (gatecal_start), + .I3 (N301), .I4 (gate_value_lock[3]), .ID ()); - // LUT = ~I1^CIN ; + // LUT = (~CIN&~I1&~I3)|(CIN&I1&~I3)|(~CIN&~I1&~I2)|(CIN&I1&~I2) ; // CARRY = (~I1) ? CIN : (I4) ; GTP_LUT5CARRY /* \N389_8.fsub_4 */ #( - .INIT(32'b10011001100110010011001100110011), + .INIT(32'b00001001100110010011001100110011), .ID_TO_LUT("FALSE"), .CIN_TO_LUT("TRUE"), .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) \N389_8.fsub_4 ( .COUT (\N389_8.co [4] ), - .Z (nb0[4]), + .Z (N389[4]), .CIN (\N389_8.co [3] ), .I0 (), .I1 (gate_value_lock[4]), - .I2 (), - .I3 (), + .I2 (gatecal_start), + .I3 (N301), .I4 (gate_value_lock[4]), .ID ()); - // LUT = ~I1^CIN ; + // LUT = (~CIN&~I1&~I3)|(CIN&I1&~I3)|(~CIN&~I1&~I2)|(CIN&I1&~I2) ; // CARRY = (~I1) ? CIN : (I4) ; GTP_LUT5CARRY /* \N389_8.fsub_5 */ #( - .INIT(32'b10011001100110010011001100110011), + .INIT(32'b00001001100110010011001100110011), .ID_TO_LUT("FALSE"), .CIN_TO_LUT("TRUE"), .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) \N389_8.fsub_5 ( .COUT (), - .Z (nb0[5]), + .Z (N389[5]), .CIN (\N389_8.co [4] ), .I0 (), .I1 (gate_value_lock[5]), - .I2 (), - .I3 (), + .I2 (gatecal_start), + .I3 (N301), .I4 (gate_value_lock[5]), .ID ()); - // LUT = ~I1^CIN ; + // LUT = (~CIN&~I1&~I3)|(CIN&I1&~I3)|(~CIN&~I1&~I2)|(CIN&I1&~I2) ; // CARRY = (~I1) ? CIN : (I4) ; + GTP_LUT3 /* \N389_50[0] */ #( + .INIT(8'b00010011)) + \N389_50[0] ( + .Z (N389[0]), + .I0 (gatecal_start), + .I1 (gate_value_lock[0]), + .I2 (N301)); + // LUT = (~I1&~I2)|(~I0&~I1) ; + + GTP_LUT5 /* N431_1 */ #( + .INIT(32'b10101010000000001110101011000000)) + N431_1 ( + .Z (N431), + .I0 (gatecal_start), + .I1 (gate_state_next[2]), + .I2 (N138), + .I3 (N301), + .I4 (_N25004)); + // LUT = (I0&I3)|(I1&I2&~I4) ; + GTP_LUT3 /* N538_5 */ #( .INIT(8'b11111110)) N538_5 ( @@ -126941,14 +126846,14 @@ module ipsxb_ddrphy_gatecal_v1_3 .Q (gate_adj_done), .C (N1), .CLK (ddrphy_clkin), - .D (_N103341)); + .D (_N104153)); // defparam gate_adj_done_vname.orig_name = gate_adj_done; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_gatecal_v1_3.vp:406 GTP_LUT5 /* gate_adj_done_ce_mux */ #( .INIT(32'b00000000010001010000000001000100)) gate_adj_done_ce_mux ( - .Z (_N103341), + .Z (_N104153), .I0 (gate_move_en), .I1 (gate_adj_done), .I2 (dqs_gate_vld), @@ -126963,18 +126868,20 @@ module ipsxb_ddrphy_gatecal_v1_3 .Q (gate_cal_error), .C (N1), .CLK (ddrphy_clkin), - .D (_N103340)); + .D (_N104152)); // defparam gate_cal_error_vname.orig_name = gate_cal_error; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_gatecal_v1_3.vp:416 - GTP_LUT3 /* gate_cal_error_ce_mux */ #( - .INIT(8'b11101010)) + GTP_LUT5 /* gate_cal_error_ce_mux */ #( + .INIT(32'b10101011101010101010101010101010)) gate_cal_error_ce_mux ( - .Z (_N103340), + .Z (_N104152), .I0 (gate_cal_error), - .I1 (gate_state_next[2]), - .I2 (_N25195)); - // LUT = (I0)|(I1&I2) ; + .I1 (gate_state_reg[1]), + .I2 (gate_state_reg[0]), + .I3 (_N25004), + .I4 (_N25006)); + // LUT = (I0)|(~I1&~I2&I3&I4) ; GTP_DFF_C /* gate_check_error */ #( .GRS_EN("TRUE"), @@ -126994,18 +126901,18 @@ module ipsxb_ddrphy_gatecal_v1_3 .Q (gate_check_pass), .C (N1), .CLK (ddrphy_clkin), - .D (_N103342)); + .D (_N104154)); // defparam gate_check_pass_vname.orig_name = gate_check_pass; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_gatecal_v1_3.vp:620 GTP_LUT4 /* gate_check_pass_ce_mux */ #( .INIT(16'b1100101011001110)) gate_check_pass_ce_mux ( - .Z (_N103342), + .Z (_N104154), .I0 (gate_check_pass), .I1 (gate_state_next[2]), .I2 (N301), - .I3 (_N25195)); + .I3 (_N25004)); // LUT = (I1&~I3)|(I0&~I2)|(I1&I2) ; GTP_DFF_C /* gate_check_pass_d */ #( @@ -127057,7 +126964,7 @@ module ipsxb_ddrphy_gatecal_v1_3 .I1 (gate_move_en), .I2 (dgts_cnt[2]), .I3 (gate_state_reg[3]), - .I4 (_N96106)); + .I4 (_N96884)); // LUT = (~I1&I3)|(~I0&~I2&I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_gatecal_v1_3.vp:336 @@ -127068,15 +126975,15 @@ module ipsxb_ddrphy_gatecal_v1_3 .I0 (gatecal_start), .I1 (N567[6]), .I2 (gate_state_reg[4]), - .I3 (_N82115), - .I4 (_N96106)); + .I3 (_N82919), + .I4 (_N96884)); // LUT = (I3&I4)|(I0&~I1&I2) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_gatecal_v1_3.vp:336 GTP_LUT4 /* \gate_state_fsm[2:0]_36 */ #( .INIT(16'b1110110011001100)) \gate_state_fsm[2:0]_36 ( - .Z (_N82115), + .Z (_N82919), .I0 (coarse_slip_step[3]), .I1 (dgts_cnt[2]), .I2 (dgts_cnt[1]), @@ -127152,7 +127059,7 @@ module ipsxb_ddrphy_gatecal_v1_3 .C (N1), .CE (N327), .CLK (ddrphy_clkin), - .D (_N61697)); + .D (_N62726)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_gatecal_v1_3.vp:434 GTP_DFF_CE /* \gate_value[2] */ #( @@ -127174,7 +127081,7 @@ module ipsxb_ddrphy_gatecal_v1_3 .C (N1), .CE (N327), .CLK (ddrphy_clkin), - .D (N328[3])); + .D (_N62811)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_gatecal_v1_3.vp:434 GTP_DFF_CE /* \gate_value[4] */ #( @@ -127191,12 +127098,34 @@ module ipsxb_ddrphy_gatecal_v1_3 GTP_LUT5 /* \gate_value[5:0]_0 */ #( .INIT(32'b00001101000010001000110110001000)) \gate_value[5:0]_0 ( - .Z (_N61697), + .Z (_N62726), .I0 (gate_move_en), .I1 (N81[1]), .I2 (gate_state_next[0]), .I3 (golden_value[1]), - .I4 (_N95825)); + .I4 (_N96676)); + // LUT = (I0&I1&~I4)|(~I0&~I2&I3)|(I0&I1&~I2) ; + + GTP_LUT5 /* \gate_value[5:0]_6 */ #( + .INIT(32'b00001101000010001000110110001000)) + \gate_value[5:0]_6 ( + .Z (_N62811), + .I0 (gate_move_en), + .I1 (N81[3]), + .I2 (gate_state_next[0]), + .I3 (golden_value[3]), + .I4 (_N96676)); + // LUT = (I0&I1&~I4)|(~I0&~I2&I3)|(I0&I1&~I2) ; + + GTP_LUT5 /* \gate_value[5:0]_266 */ #( + .INIT(32'b00001101000010001000110110001000)) + \gate_value[5:0]_266 ( + .Z (_N63109), + .I0 (gate_move_en), + .I1 (N81[5]), + .I2 (gate_state_next[0]), + .I3 (golden_value[5]), + .I4 (_N96676)); // LUT = (I0&I1&~I4)|(~I0&~I2&I3)|(I0&I1&~I2) ; GTP_DFF_CE /* \gate_value[5] */ #( @@ -127207,7 +127136,7 @@ module ipsxb_ddrphy_gatecal_v1_3 .C (N1), .CE (N327), .CLK (ddrphy_clkin), - .D (N328[5])); + .D (_N63109)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_gatecal_v1_3.vp:434 GTP_DFF_CE /* \gate_value_lock[0] */ #( @@ -127315,7 +127244,7 @@ module ipsxb_ddrphy_gatecal_v1_3 \golden_value[0] ( .Q (golden_value[0]), .C (N1), - .CE (N139), + .CE (N431), .CLK (ddrphy_clkin), .D (N389[0])); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_gatecal_v1_3.vp:532 @@ -127326,9 +127255,9 @@ module ipsxb_ddrphy_gatecal_v1_3 \golden_value[1] ( .Q (golden_value[1]), .C (N1), - .CE (N139), + .CE (N431), .CLK (ddrphy_clkin), - .D (nb0[1])); + .D (N389[1])); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_gatecal_v1_3.vp:532 GTP_DFF_CE /* \golden_value[2] */ #( @@ -127337,9 +127266,9 @@ module ipsxb_ddrphy_gatecal_v1_3 \golden_value[2] ( .Q (golden_value[2]), .C (N1), - .CE (N139), + .CE (N431), .CLK (ddrphy_clkin), - .D (nb0[2])); + .D (N389[2])); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_gatecal_v1_3.vp:532 GTP_DFF_CE /* \golden_value[3] */ #( @@ -127348,9 +127277,9 @@ module ipsxb_ddrphy_gatecal_v1_3 \golden_value[3] ( .Q (golden_value[3]), .C (N1), - .CE (N139), + .CE (N431), .CLK (ddrphy_clkin), - .D (nb0[3])); + .D (N389[3])); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_gatecal_v1_3.vp:532 GTP_DFF_CE /* \golden_value[4] */ #( @@ -127359,9 +127288,9 @@ module ipsxb_ddrphy_gatecal_v1_3 \golden_value[4] ( .Q (golden_value[4]), .C (N1), - .CE (N139), + .CE (N431), .CLK (ddrphy_clkin), - .D (nb0[4])); + .D (N389[4])); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_gatecal_v1_3.vp:532 GTP_DFF_CE /* \golden_value[5] */ #( @@ -127370,9 +127299,9 @@ module ipsxb_ddrphy_gatecal_v1_3 \golden_value[5] ( .Q (golden_value[5]), .C (N1), - .CE (N139), + .CE (N431), .CLK (ddrphy_clkin), - .D (nb0[5])); + .D (N389[5])); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_gatecal_v1_3.vp:532 @@ -127400,8 +127329,8 @@ module ipsxb_ddrphy_data_slice_dqs_gate_cal_v1_3 input [3:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4 , input [3:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src , input [5:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg , - input _N95825, - input _N96106, + input _N96676, + input _N96884, input ddrphy_clkin, input dqs_gate_check_pass, input gate_check, @@ -127419,14 +127348,14 @@ module ipsxb_ddrphy_data_slice_dqs_gate_cal_v1_3 output [3:0] \dqs_gate_coarse_cal/read_cmd_mux_r3 , output [3:0] dqs_gate_ctrl, output [2:0] \gatecal/N22 , - output [2:0] \gatecal/gate_state_next , output [5:0] \gatecal/gate_state_reg , output [2:0] read_clk_ctrl, output [3:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj , output [3:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj , output [3:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj , - output _N96109, - output _N96110, + output _N25006, + output _N96887, + output _N96888, output dqs_gate_vld, output gate_adj_done, output gate_cal_error, @@ -127445,8 +127374,6 @@ module ipsxb_ddrphy_data_slice_dqs_gate_cal_v1_3 wire \dqs_gate_coarse_cal_read_cmd_mux_r3[3]_floating ; wire \gatecal_N22[0]_floating ; wire \gatecal_N22[1]_floating ; - wire \gatecal_gate_state_next[0]_floating ; - wire \gatecal_gate_state_next[1]_floating ; wire \gatecal_gate_state_reg[4]_floating ; wire \gatecal_gate_state_reg[5]_floating ; wire \gatecal_read_clk_ctrl[2]_floating ; @@ -127488,21 +127415,21 @@ module ipsxb_ddrphy_data_slice_dqs_gate_cal_v1_3 ipsxb_ddrphy_gatecal_v1_3 gatecal ( .N22 ({\gatecal/N22 [2] , \gatecal_N22[1]_floating , \gatecal_N22[0]_floating }), .coarse_slip_step (coarse_slip_step), - .gate_state_next ({\gatecal/gate_state_next [2] , \gatecal_gate_state_next[1]_floating , \gatecal_gate_state_next[0]_floating }), .gate_state_reg ({\gatecal_gate_state_reg[5]_floating , \gatecal_gate_state_reg[4]_floating , \gatecal/gate_state_reg [3] , \gatecal/gate_state_reg [2] , \gatecal/gate_state_reg [1] , \gatecal/gate_state_reg [0] }), .read_clk_ctrl ({\gatecal_read_clk_ctrl[2]_floating , read_clk_ctrl[1], read_clk_ctrl[0]}), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg ({1'bx, 1'bx, 1'bx, \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg [2] , 1'bx, 1'bx}), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg ({1'bx, 1'bx, 1'bx, \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg [2] , 1'bx, 1'bx}), - ._N96109 (_N96109), - ._N96110 (_N96110), + ._N25006 (_N25006), + ._N96887 (_N96887), + ._N96888 (_N96888), .dqs_gate_vld_r (\gatecal/dqs_gate_vld_r ), .gate_adj_done (gate_adj_done), .gate_cal_error (gate_cal_error), .gate_check_error (gate_check_error), .gate_check_pass (gate_check_pass), .N1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/N0 ), - ._N95825 (_N95825), - ._N96106 (_N96106), + ._N96676 (_N96676), + ._N96884 (_N96884), .ddrphy_clkin (ddrphy_clkin), .dqs_gate_check_pass (dqs_gate_check_pass), .dqs_gate_vld (dqs_gate_vld), @@ -127529,42 +127456,39 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 input [6:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg , input [4:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt , input [6:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg , - input [3:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_flag_tmp , input N0, input N449, - input _N96271, - input _N96318, - input _N96883, - input _N105949, + input _N97478, + input _N97660, + input _N106767, input ddrphy_clkin, - input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N165 , - input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld , - input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N165 , + input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld , input wrlvl_ck_dly_done, + input wrlvl_ck_dly_start, input wrlvl_dqs_req, output [7:0] ck_dly_set_bin_tra, output [4:0] cnt, output [7:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/adj_wrdqs , output [6:0] wl_state_reg, output [7:0] wrlvl_step, - output _N96120, - output _N96124, - output _N96886, - output _N96887, - output _N106288, + output _N96898, + output _N96900, + output _N96902, + output _N97080, + output _N97662, + output _N97663, + output _N104452, output ck_check_done, output ddrphy_gatei, output dq_vld, - output \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N449 , - output \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N449 , - output wrlvl_ck_dly_start, + output wrlvl_ck_dly_flag, output wrlvl_dqs, output wrlvl_dqs_en, output wrlvl_dqs_resp, output wrlvl_error ); wire N56; - wire N63; + wire N72; wire N136; wire [7:0] N141; wire N165; @@ -127595,50 +127519,49 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 wire _N12; wire _N15; wire _N22; - wire _N5513; - wire _N14036; - wire _N14037; - wire _N14038; - wire _N14039; - wire _N14040; - wire _N14041; - wire _N14620; - wire _N14621; - wire _N14622; - wire _N14623; - wire _N14624; - wire _N14625; - wire _N17020; - wire _N17021; - wire _N17022; - wire _N17023; - wire _N17024; - wire _N17025; - wire _N17026; - wire _N22696; - wire _N62167; - wire _N62824; - wire _N62890; - wire _N62891; - wire _N62986; - wire _N63087; - wire _N103346; - wire _N103347; - wire _N103348; - wire _N103349; - wire _N103350; - wire _N103351; - wire _N103352; - wire _N105908; - wire _N105909; - wire _N105917; - wire _N105928; - wire _N105929; - wire _N105932; - wire _N105937; - wire _N105945; - wire _N105962; - wire _N105979; + wire _N5539; + wire _N14576; + wire _N14577; + wire _N14578; + wire _N14579; + wire _N14580; + wire _N14581; + wire _N17028; + wire _N17029; + wire _N17030; + wire _N17031; + wire _N17032; + wire _N17033; + wire _N17034; + wire _N17071; + wire _N17072; + wire _N17073; + wire _N17074; + wire _N17075; + wire _N17076; + wire _N22668; + wire _N63173; + wire _N63878; + wire _N63922; + wire _N64018; + wire _N64198; + wire _N104158; + wire _N104159; + wire _N104160; + wire _N104161; + wire _N104162; + wire _N104163; + wire _N104164; + wire _N106728; + wire _N106729; + wire _N106737; + wire _N106746; + wire _N106747; + wire _N106750; + wire _N106755; + wire _N106763; + wire _N106782; + wire _N106799; wire [7:0] ck_dly_step; wire dq_rising; wire [7:0] step_cnt; @@ -127646,11 +127569,19 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 wire wl_done_flag; wire [2:0] wl_next_state; wire [5:0] wrlvl_ck_check_seq; - wire wrlvl_ck_dly_flag; wire wrlvl_ck_dly_pass; wire [2:0] wrlvl_dq_r; wire [3:0] wrlvl_dq_seq; + GTP_LUT3 /* \N53_4_and[1][4]_1 */ #( + .INIT(8'b10000000)) + \N53_4_and[1][4]_1 ( + .Z (_N97080), + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [0] ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] )); + // LUT = I0&I1&I2 ; + GTP_LUT4 /* \N53_4_or[0]_1 */ #( .INIT(16'b1111111111100000)) \N53_4_or[0]_1 ( @@ -127711,24 +127642,28 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 // defparam N56_vname.orig_name = N56; // LUT = ~I0 ; - GTP_LUT2 /* N63 */ #( - .INIT(4'b0100)) - N63_vname ( - .Z (N63), - .I0 (wl_done_flag), - .I1 (wl_state_reg[0])); - // defparam N63_vname.orig_name = N63; - // LUT = ~I0&I1 ; - // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:364 - GTP_LUT2 /* N66_ac1 */ #( .INIT(4'b1000)) N66_ac1 ( - .Z (_N5513), + .Z (_N5539), .I0 (cnt[1]), .I1 (cnt[0])); // LUT = I0&I1 ; + GTP_LUT5M /* N72 */ #( + .INIT(32'b00010001000100010011000100110000)) + N72_vname ( + .Z (N72), + .I0 (wl_next_state[2]), + .I1 (wl_next_state[0]), + .I2 (wl_state_reg[3]), + .I3 (wl_state_reg[4]), + .I4 (wl_next_state[1]), + .ID (N484[4])); + // defparam N72_vname.orig_name = N72; + // LUT = (~ID&~I1&I3&~I4)|(~I1&I2&~I4)|(~I0&~I1&I4) ; + // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:369 + GTP_LUT5CARRY /* N102_1_0 */ #( .INIT(32'b11001100110011000000000000000000), .ID_TO_LUT("FALSE"), @@ -127736,7 +127671,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 .I4_TO_CARRY("FALSE"), .I4_TO_LUT("FALSE")) N102_1_0 ( - .COUT (_N17020), + .COUT (_N17028), .Z (), .CIN (), .I0 (), @@ -127756,9 +127691,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N102_1_1 ( - .COUT (_N17021), + .COUT (_N17029), .Z (N378[1]), - .CIN (_N17020), + .CIN (_N17028), .I0 (), .I1 (step_cnt[1]), .I2 (wrlvl_ck_dly_start), @@ -127776,9 +127711,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N102_1_2 ( - .COUT (_N17022), + .COUT (_N17030), .Z (N378[2]), - .CIN (_N17021), + .CIN (_N17029), .I0 (), .I1 (step_cnt[2]), .I2 (wrlvl_ck_dly_start), @@ -127796,9 +127731,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N102_1_3 ( - .COUT (_N17023), + .COUT (_N17031), .Z (N378[3]), - .CIN (_N17022), + .CIN (_N17030), .I0 (), .I1 (step_cnt[3]), .I2 (wrlvl_ck_dly_start), @@ -127816,9 +127751,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N102_1_4 ( - .COUT (_N17024), + .COUT (_N17032), .Z (N378[4]), - .CIN (_N17023), + .CIN (_N17031), .I0 (), .I1 (step_cnt[4]), .I2 (wrlvl_ck_dly_start), @@ -127836,9 +127771,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N102_1_5 ( - .COUT (_N17025), + .COUT (_N17033), .Z (N378[5]), - .CIN (_N17024), + .CIN (_N17032), .I0 (), .I1 (step_cnt[5]), .I2 (wrlvl_ck_dly_start), @@ -127856,9 +127791,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N102_1_6 ( - .COUT (_N17026), + .COUT (_N17034), .Z (N378[6]), - .CIN (_N17025), + .CIN (_N17033), .I0 (), .I1 (step_cnt[6]), .I2 (wrlvl_ck_dly_start), @@ -127878,7 +127813,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 N102_1_7 ( .COUT (), .Z (N378[7]), - .CIN (_N17026), + .CIN (_N17034), .I0 (), .I1 (step_cnt[7]), .I2 (wrlvl_ck_dly_start), @@ -127896,7 +127831,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_1 ( - .COUT (_N14620), + .COUT (_N14576), .Z (N387[1]), .CIN (), .I0 (ck_dly_step[0]), @@ -127916,9 +127851,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_2 ( - .COUT (_N14621), + .COUT (_N14577), .Z (N387[2]), - .CIN (_N14620), + .CIN (_N14576), .I0 (ck_dly_step[0]), .I1 (ck_dly_step[1]), .I2 (N296), @@ -127936,9 +127871,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_3 ( - .COUT (_N14622), + .COUT (_N14578), .Z (N387[3]), - .CIN (_N14621), + .CIN (_N14577), .I0 (), .I1 (ck_dly_step[3]), .I2 (N296), @@ -127956,9 +127891,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_4 ( - .COUT (_N14623), + .COUT (_N14579), .Z (N387[4]), - .CIN (_N14622), + .CIN (_N14578), .I0 (), .I1 (ck_dly_step[4]), .I2 (N296), @@ -127976,9 +127911,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_5 ( - .COUT (_N14624), + .COUT (_N14580), .Z (N387[5]), - .CIN (_N14623), + .CIN (_N14579), .I0 (), .I1 (ck_dly_step[5]), .I2 (N296), @@ -127996,9 +127931,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_6 ( - .COUT (_N14625), + .COUT (_N14581), .Z (N387[6]), - .CIN (_N14624), + .CIN (_N14580), .I0 (), .I1 (ck_dly_step[6]), .I2 (N296), @@ -128018,7 +127953,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 N104_1_7 ( .COUT (), .Z (N387[7]), - .CIN (_N14625), + .CIN (_N14581), .I0 (), .I1 (ck_dly_step[7]), .I2 (N296), @@ -128032,7 +127967,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 GTP_LUT2 /* N124_1 */ #( .INIT(4'b0001)) N124_1 ( - .Z (_N96120), + .Z (_N96898), .I0 (cnt[4]), .I1 (cnt[0])); // LUT = ~I0&~I1 ; @@ -128040,7 +127975,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 GTP_LUT5 /* N124_8 */ #( .INIT(32'b00000000000000000000010000000000)) N124_8 ( - .Z (_N105979), + .Z (_N106799), .I0 (cnt[4]), .I1 (cnt[3]), .I2 (cnt[2]), @@ -128051,10 +127986,10 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 GTP_LUT3 /* N136_1 */ #( .INIT(8'b10000000)) N136_1 ( - .Z (_N96886), - .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg [4] )); + .Z (_N97662), + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg [4] )); // LUT = I0&I1&I2 ; GTP_LUT5 /* N136_7 */ #( @@ -128065,7 +128000,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 .I1 (cnt[2]), .I2 (cnt[1]), .I3 (wl_state_reg[2]), - .I4 (_N96120)); + .I4 (_N96898)); // LUT = ~I0&I1&~I2&I3&I4 ; GTP_LUT2 /* \N141[0]_1 */ #( @@ -128140,20 +128075,19 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 // LUT = ~I0&I1 ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:446 - GTP_LUT4 /* N151_1 */ #( - .INIT(16'b0000000100000000)) + GTP_LUT3 /* N151_1 */ #( + .INIT(8'b10000000)) N151_1 ( - .Z (_N96887), - .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [0] ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [1] ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [4] ), - .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg [4] )); - // LUT = ~I0&~I1&~I2&I3 ; + .Z (_N97663), + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg [4] )); + // LUT = I0&I1&I2 ; GTP_LUT3 /* N151_4 */ #( .INIT(8'b00100000)) N151_4 ( - .Z (_N105932), + .Z (_N106750), .I0 (cnt[3]), .I1 (cnt[2]), .I2 (wl_state_reg[4])); @@ -128172,7 +128106,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 GTP_LUT5 /* N173_8 */ #( .INIT(32'b00000000000000010000000000000000)) N173_8 ( - .Z (_N105945), + .Z (_N106763), .I0 (vld_init_cnt[5]), .I1 (vld_init_cnt[4]), .I2 (vld_init_cnt[3]), @@ -128188,7 +128122,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 .I1 (vld_init_cnt[6]), .I2 (vld_init_cnt[2]), .I3 (vld_init_cnt[0]), - .I4 (_N105945)); + .I4 (_N106763)); // LUT = ~I0&~I1&I2&I3&I4 ; GTP_LUT5CARRY /* N201_1_1 */ #( @@ -128198,7 +128132,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N201_1_1 ( - .COUT (_N14036), + .COUT (_N17071), .Z (N440[1]), .CIN (), .I0 (vld_init_cnt[0]), @@ -128218,9 +128152,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N201_1_2 ( - .COUT (_N14037), + .COUT (_N17072), .Z (N440[2]), - .CIN (_N14036), + .CIN (_N17071), .I0 (vld_init_cnt[0]), .I1 (vld_init_cnt[1]), .I2 (wl_state_reg[6]), @@ -128238,9 +128172,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N201_1_3 ( - .COUT (_N14038), + .COUT (_N17073), .Z (N440[3]), - .CIN (_N14037), + .CIN (_N17072), .I0 (), .I1 (vld_init_cnt[3]), .I2 (wl_state_reg[6]), @@ -128258,9 +128192,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N201_1_4 ( - .COUT (_N14039), + .COUT (_N17074), .Z (N440[4]), - .CIN (_N14038), + .CIN (_N17073), .I0 (), .I1 (vld_init_cnt[4]), .I2 (wl_state_reg[6]), @@ -128278,9 +128212,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N201_1_5 ( - .COUT (_N14040), + .COUT (_N17075), .Z (N440[5]), - .CIN (_N14039), + .CIN (_N17074), .I0 (), .I1 (vld_init_cnt[5]), .I2 (wl_state_reg[6]), @@ -128298,9 +128232,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N201_1_6 ( - .COUT (_N14041), + .COUT (_N17076), .Z (N440[6]), - .CIN (_N14040), + .CIN (_N17075), .I0 (), .I1 (vld_init_cnt[6]), .I2 (wl_state_reg[6]), @@ -128320,7 +128254,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 N201_1_7 ( .COUT (), .Z (N440[7]), - .CIN (_N14041), + .CIN (_N17076), .I0 (), .I1 (vld_init_cnt[7]), .I2 (wl_state_reg[6]), @@ -128331,21 +128265,29 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 // CARRY = (I1) ? CIN : (I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:516 - GTP_LUT5 /* N228_11 */ #( + GTP_LUT2 /* N228_1 */ #( + .INIT(4'b0001)) + N228_1 ( + .Z (_N96900), + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [4] ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [0] )); + // LUT = ~I0&~I1 ; + + GTP_LUT5 /* N228_10 */ #( .INIT(32'b00010000000000000000000000000000)) - N228_11 ( + N228_10 ( .Z (N228), .I0 (cnt[4]), .I1 (cnt[1]), .I2 (cnt[0]), .I3 (dq_vld), - .I4 (_N96883)); + .I4 (_N97660)); // LUT = ~I0&~I1&I2&I3&I4 ; GTP_LUT2 /* N232_1 */ #( .INIT(4'b0001)) N232_1 ( - .Z (_N96124), + .Z (_N96902), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt [4] ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt [0] )); // LUT = ~I0&~I1 ; @@ -128353,7 +128295,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 GTP_LUT5 /* N265_11 */ #( .INIT(32'b00000001000000000000000000000000)) N265_11 ( - .Z (_N105962), + .Z (_N106782), .I0 (wrlvl_dq_seq[3]), .I1 (wrlvl_dq_seq[2]), .I2 (wrlvl_dq_seq[1]), @@ -128364,7 +128306,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 GTP_LUT4 /* N279_6 */ #( .INIT(16'b1000000000000000)) N279_6 ( - .Z (_N105917), + .Z (_N106737), .I0 (step_cnt[4]), .I1 (step_cnt[3]), .I2 (step_cnt[2]), @@ -128379,13 +128321,13 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 .I1 (step_cnt[6]), .I2 (step_cnt[5]), .I3 (step_cnt[0]), - .I4 (_N105917)); + .I4 (_N106737)); // LUT = I0&I1&I2&I3&I4 ; GTP_LUT2 /* N286_9 */ #( .INIT(4'b0001)) N286_9 ( - .Z (_N105908), + .Z (_N106728), .I0 (ck_dly_step[7]), .I1 (ck_dly_step[0])); // LUT = ~I0&~I1 ; @@ -128393,7 +128335,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 GTP_LUT4 /* N286_10 */ #( .INIT(16'b0000000000000001)) N286_10 ( - .Z (_N105909), + .Z (_N106729), .I0 (ck_dly_step[5]), .I1 (ck_dly_step[4]), .I2 (ck_dly_step[2]), @@ -128408,7 +128350,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 .I1 (ck_dly_step[6]), .I2 (ck_dly_step[3]), .I3 (ck_dly_step[0]), - .I4 (_N105909)); + .I4 (_N106729)); // LUT = ~I0&I1&I2&~I3&I4 ; GTP_LUT5 /* N296 */ #( @@ -128438,7 +128380,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 GTP_LUT4 /* N334_5 */ #( .INIT(16'b0000000000000001)) N334_5 ( - .Z (_N105937), + .Z (_N106755), .I0 (wrlvl_ck_check_seq[5]), .I1 (wrlvl_ck_check_seq[2]), .I2 (wrlvl_ck_check_seq[1]), @@ -128451,7 +128393,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 .Z (N334), .I0 (wrlvl_ck_check_seq[4]), .I1 (wrlvl_ck_check_seq[3]), - .I2 (_N105937)); + .I2 (_N106755)); // LUT = ~I0&~I1&I2 ; GTP_LUT3 /* N359 */ #( @@ -128501,7 +128443,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 .INIT(32'b01101100110011000000000000000000)) \N367_1[4] ( .Z (N367[4]), - .I0 (_N5513), + .I0 (_N5539), .I1 (cnt[4]), .I2 (cnt[3]), .I3 (cnt[2]), @@ -128557,12 +128499,12 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 GTP_LUT5 /* N395_2 */ #( .INIT(32'b01010111010101010101010101010101)) N395_2 ( - .Z (_N22696), + .Z (_N22668), .I0 (wrlvl_ck_dly_start), .I1 (ck_dly_step[6]), .I2 (ck_dly_step[3]), - .I3 (_N105908), - .I4 (_N105909)); + .I3 (_N106728), + .I4 (_N106729)); // LUT = (~I0)|(~I1&~I2&I3&I4) ; GTP_LUT2 /* N409 */ #( @@ -128577,7 +128519,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 GTP_LUT4 /* \N417[0]_14 */ #( .INIT(16'b1111111111111110)) \N417[0]_14 ( - .Z (_N105928), + .Z (_N106746), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_in_dly [3] ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_in_dly [2] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_in_dly [1] ), @@ -128587,7 +128529,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 GTP_LUT4 /* \N417[0]_15 */ #( .INIT(16'b1111111111111110)) \N417[0]_15 ( - .Z (_N105929), + .Z (_N106747), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_in_dly [7] ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_in_dly [6] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_in_dly [5] ), @@ -128600,8 +128542,8 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 .Z (N417[0]), .I0 (wrlvl_dqs_en), .I1 (dq_vld), - .I2 (_N105928), - .I3 (_N105929)); + .I2 (_N106746), + .I3 (_N106747)); // LUT = (~I1)|(~I0)|(I2)|(I3) ; GTP_LUT3 /* \N417[1] */ #( @@ -128632,7 +128574,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 .I1 (cnt[1]), .I2 (cnt[0]), .I3 (wl_state_reg[6]), - .I4 (_N96883)); + .I4 (_N97660)); // defparam N439_vname.orig_name = N439; // LUT = (I3)|(~I0&~I1&~I2&I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:509 @@ -128722,17 +128664,17 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 // LUT = (I0)|(I1) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:545 - GTP_LUT5M /* N475_1 */ #( - .INIT(32'b01010101010101010001010100010000)) - N475_1 ( + GTP_LUT4 /* N475 */ #( + .INIT(16'b1100010111001100)) + N475_vname ( .Z (N475), .I0 (N484[4]), - .I1 (wl_next_state[2]), - .I2 (wl_next_state[1]), - .I3 (_N12), - .I4 (N63), - .ID (wl_next_state[0])); - // LUT = (~ID&~I2&I3&~I4)|(~ID&~I1&I2&~I4)|(~I0&I4) ; + .I1 (N72), + .I2 (wl_done_flag), + .I3 (wl_state_reg[0])); + // defparam N475_vname.orig_name = N475; + // LUT = (I1&~I3)|(I1&I2)|(~I0&~I2&I3) ; + // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:360 GTP_DFF_C /* ck_check_done */ #( .GRS_EN("TRUE"), @@ -128741,14 +128683,14 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 .Q (ck_check_done), .C (N0), .CLK (ddrphy_clkin), - .D (_N103351)); + .D (_N104163)); // defparam ck_check_done_vname.orig_name = ck_check_done; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:535 GTP_LUT5 /* ck_check_done_ce_mux */ #( .INIT(32'b00000000000000001110110011001100)) ck_check_done_ce_mux ( - .Z (_N103351), + .Z (_N104163), .I0 (wrlvl_ck_dly_start), .I1 (ck_check_done), .I2 (N228), @@ -128940,7 +128882,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 .C (N0), .CE (N359), .CLK (ddrphy_clkin), - .D (_N62167)); + .D (_N63173)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:360 GTP_DFF_CE /* \cnt[1] */ #( @@ -128976,17 +128918,15 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 .D (N367[3])); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:360 - GTP_LUT5M /* \cnt[4:0]_3431 */ #( - .INIT(32'b00000000111100010000000011110010)) - \cnt[4:0]_3431 ( - .Z (_N62167), - .I0 (wl_next_state[2]), - .I1 (wl_next_state[0]), - .I2 (N63), - .I3 (cnt[0]), - .I4 (wl_next_state[1]), - .ID (_N12)); - // LUT = (ID&~I1&~I3&~I4)|(~I0&~I1&~I3&I4)|(I2&~I3) ; + GTP_LUT4 /* \cnt[4:0]_3508 */ #( + .INIT(16'b0100010101000100)) + \cnt[4:0]_3508 ( + .Z (_N63173), + .I0 (cnt[0]), + .I1 (N72), + .I2 (wl_done_flag), + .I3 (wl_state_reg[0])); + // LUT = (~I0&I1)|(~I0&~I2&I3) ; GTP_DFF_CE /* \cnt[4] */ #( .GRS_EN("TRUE"), @@ -129006,20 +128946,20 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 .Q (ddrphy_gatei), .C (N0), .CLK (ddrphy_clkin), - .D (_N103346)); + .D (_N104158)); // defparam ddrphy_gatei_vname.orig_name = ddrphy_gatei; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:413 GTP_LUT5M /* ddrphy_gatei_ce_mux */ #( .INIT(32'b11001100110010101100110001001100)) ddrphy_gatei_ce_mux ( - .Z (_N103346), - .I0 (_N22696), + .Z (_N104158), + .I0 (_N22668), .I1 (ddrphy_gatei), .I2 (wl_next_state[1]), .I3 (wl_next_state[2]), .I4 (wl_next_state[0]), - .ID (_N105979)); + .ID (_N106799)); // LUT = (I1&~I2&~I4)|(I0&~I2&~I3&I4)|(I1&I2&I4)|(I1&I3)|(~ID&I1&I2) ; GTP_DFF_C /* dq_rising */ #( @@ -129029,18 +128969,18 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 .Q (dq_rising), .C (N0), .CLK (ddrphy_clkin), - .D (_N103352)); + .D (_N104164)); // defparam dq_rising_vname.orig_name = dq_rising; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:559 GTP_LUT4 /* dq_rising_ce_mux */ #( .INIT(16'b0000111000001100)) dq_rising_ce_mux ( - .Z (_N103352), + .Z (_N104164), .I0 (N228), .I1 (dq_rising), .I2 (wl_state_reg[6]), - .I3 (_N105962)); + .I3 (_N106782)); // LUT = (I1&~I2)|(I0&~I2&I3) ; GTP_DFF_C /* dq_vld */ #( @@ -129050,19 +128990,19 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 .Q (dq_vld), .C (N0), .CLK (ddrphy_clkin), - .D (_N103347)); + .D (_N104159)); // defparam dq_vld_vname.orig_name = dq_vld; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:453 GTP_LUT5 /* dq_vld_ce_mux */ #( .INIT(32'b00001101000011000000110000001100)) dq_vld_ce_mux ( - .Z (_N103347), + .Z (_N104159), .I0 (cnt[1]), .I1 (dq_vld), .I2 (wl_state_reg[6]), - .I3 (_N96120), - .I4 (_N105932)); + .I3 (_N96898), + .I4 (_N106750)); // LUT = (I1&~I2)|(~I0&~I2&I3&I4) ; GTP_DFF_CE /* \step_cnt[0] */ #( @@ -129248,14 +129188,14 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 .Q (wl_done_flag), .C (N0), .CLK (ddrphy_clkin), - .D (_N103348)); + .D (_N104160)); // defparam wl_done_flag_vname.orig_name = wl_done_flag; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:463 GTP_LUT3 /* wl_done_flag_ce_mux */ #( .INIT(8'b01010100)) wl_done_flag_ce_mux ( - .Z (_N103348), + .Z (_N104160), .I0 (wrlvl_dqs_req), .I1 (wl_done_flag), .I2 (wl_state_reg[6])); @@ -129456,18 +129396,18 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 .Q (wrlvl_ck_dly_flag), .C (N0), .CLK (ddrphy_clkin), - .D (_N103349)); + .D (_N104161)); // defparam wrlvl_ck_dly_flag_vname.orig_name = wrlvl_ck_dly_flag; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:483 GTP_LUT5M /* wrlvl_ck_dly_flag_ce_mux */ #( .INIT(32'b11111110111111110101000001010000)) wrlvl_ck_dly_flag_ce_mux ( - .Z (_N103349), + .Z (_N104161), .I0 (wrlvl_ck_check_seq[4]), .I1 (wrlvl_ck_check_seq[3]), .I2 (wrlvl_ck_dly_flag), - .I3 (_N105937), + .I3 (_N106755), .I4 (N173), .ID (wrlvl_ck_dly_done)); // LUT = (~I3&I4)|(I2&I4)|(I1&I4)|(I0&I4)|(~ID&I2) ; @@ -129479,19 +129419,19 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 .Q (wrlvl_ck_dly_pass), .C (N0), .CLK (ddrphy_clkin), - .D (_N103350)); + .D (_N104162)); // defparam wrlvl_ck_dly_pass_vname.orig_name = wrlvl_ck_dly_pass; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:483 GTP_LUT5 /* wrlvl_ck_dly_pass_ce_mux */ #( .INIT(32'b11111111000100001111111100000000)) wrlvl_ck_dly_pass_ce_mux ( - .Z (_N103350), + .Z (_N104162), .I0 (wrlvl_ck_check_seq[4]), .I1 (wrlvl_ck_check_seq[3]), .I2 (N173), .I3 (wrlvl_ck_dly_pass), - .I4 (_N105937)); + .I4 (_N106755)); // LUT = (I3)|(~I0&~I1&I2&I4) ; GTP_DFF_P /* \wrlvl_dq_r[0] */ #( @@ -129531,7 +129471,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 .Q (wrlvl_dq_seq[0]), .CE (N466), .CLK (ddrphy_clkin), - .D (_N62824), + .D (_N63878), .P (N0)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:545 @@ -129542,7 +129482,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 .Q (wrlvl_dq_seq[1]), .CE (N466), .CLK (ddrphy_clkin), - .D (_N62890), + .D (_N63922), .P (N0)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:545 @@ -129553,96 +129493,61 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 .Q (wrlvl_dq_seq[2]), .CE (N466), .CLK (ddrphy_clkin), - .D (_N62986), + .D (_N64018), .P (N0)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:545 - GTP_LUT2 /* \wrlvl_dq_seq[3:0]_0 */ #( - .INIT(4'b1110)) + GTP_LUT5 /* \wrlvl_dq_seq[3:0]_0 */ #( + .INIT(32'b11111111111111111111111111111011)) \wrlvl_dq_seq[3:0]_0 ( - .Z (_N62890), - .I0 (_N62891), - .I1 (wrlvl_dq_seq[0])); - // LUT = (I0)|(I1) ; - - GTP_LUT5 /* \wrlvl_dq_seq[3:0]_1_3 */ #( - .INIT(32'b11111111111111111111101111111111)) - \wrlvl_dq_seq[3:0]_1_3 ( - .Z (_N62891), + .Z (_N63922), .I0 (wrlvl_ck_dly_start), - .I1 (wrlvl_dqs_en), - .I2 (cnt[4]), - .I3 (wl_state_reg[4]), - .I4 (_N105949)); - // LUT = (~I3)|(~I1)|(I0)|(I2)|(I4) ; - - GTP_LUT4 /* \wrlvl_dq_seq[3:0]_5 */ #( - .INIT(16'b1111111111111110)) - \wrlvl_dq_seq[3:0]_5 ( - .Z (wrlvl_ck_dly_start), - .I0 (wrlvl_ck_dly_flag), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_flag_tmp [1] ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_flag_tmp [2] ), - .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_flag_tmp [3] )); - // LUT = (I0)|(I1)|(I2)|(I3) ; + .I1 (cnt[3]), + .I2 (wrlvl_dq_seq[0]), + .I3 (_N97478), + .I4 (_N106767)); + // LUT = (~I1)|(I0)|(I2)|(I3)|(I4) ; - GTP_LUT5 /* \wrlvl_dq_seq[3:0]_10 */ #( - .INIT(32'b11010101010101010101010101010101)) - \wrlvl_dq_seq[3:0]_10 ( - .Z (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N449 ), - .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N165 ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] ), - .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg [4] ), - .I4 (_N96271)); - // LUT = (~I0)|(I1&I2&I3&I4) ; + GTP_LUT5 /* \wrlvl_dq_seq[3:0]_48_3 */ #( + .INIT(32'b11111111111111111111111111101111)) + \wrlvl_dq_seq[3:0]_48_3 ( + .Z (_N63878), + .I0 (wrlvl_ck_dly_start), + .I1 (cnt[4]), + .I2 (cnt[2]), + .I3 (wrlvl_dq_r[2]), + .I4 (_N97478)); + // LUT = (~I2)|(I0)|(I1)|(I3)|(I4) ; - GTP_LUT5 /* \wrlvl_dq_seq[3:0]_24_3 */ #( + GTP_LUT5 /* \wrlvl_dq_seq[3:0]_143 */ #( .INIT(32'b11111111111111111111111111111011)) - \wrlvl_dq_seq[3:0]_24_3 ( - .Z (_N62824), + \wrlvl_dq_seq[3:0]_143 ( + .Z (_N64018), .I0 (wrlvl_ck_dly_start), - .I1 (wrlvl_dqs_en), - .I2 (cnt[4]), - .I3 (wrlvl_dq_r[2]), - .I4 (_N105949)); + .I1 (cnt[3]), + .I2 (wrlvl_dq_seq[1]), + .I3 (_N97478), + .I4 (_N106767)); // LUT = (~I1)|(I0)|(I2)|(I3)|(I4) ; - GTP_LUT2 /* \wrlvl_dq_seq[3:0]_119 */ #( - .INIT(4'b1110)) - \wrlvl_dq_seq[3:0]_119 ( - .Z (_N62986), - .I0 (_N62891), - .I1 (wrlvl_dq_seq[1])); - // LUT = (I0)|(I1) ; - - GTP_LUT2 /* \wrlvl_dq_seq[3:0]_214 */ #( - .INIT(4'b1110)) - \wrlvl_dq_seq[3:0]_214 ( - .Z (_N63087), - .I0 (_N62891), - .I1 (wrlvl_dq_seq[2])); - // LUT = (I0)|(I1) ; - - GTP_LUT5 /* \wrlvl_dq_seq[3:0]_313 */ #( - .INIT(32'b10001111000011110000111100001111)) - \wrlvl_dq_seq[3:0]_313 ( - .Z (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N449 ), - .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N165 ), - .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg [4] ), - .I4 (_N96318)); - // LUT = (~I2)|(I0&I1&I3&I4) ; + GTP_LUT4 /* \wrlvl_dq_seq[3:0]_321_4 */ #( + .INIT(16'b1111111111111011)) + \wrlvl_dq_seq[3:0]_321_4 ( + .Z (_N64198), + .I0 (wrlvl_ck_dly_start), + .I1 (cnt[3]), + .I2 (wrlvl_dq_seq[2]), + .I3 (_N97478)); + // LUT = (~I1)|(I0)|(I2)|(I3) ; - GTP_LUT4 /* \wrlvl_dq_seq[3:0]_316 */ #( + GTP_LUT4 /* \wrlvl_dq_seq[3:0]_335 */ #( .INIT(16'b0111111111111111)) - \wrlvl_dq_seq[3:0]_316 ( - .Z (_N106288), - .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld ), - .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg [4] )); + \wrlvl_dq_seq[3:0]_335 ( + .Z (_N104452), + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] ), + .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg [4] )); // LUT = (~I3)|(~I2)|(~I1)|(~I0) ; GTP_DFF_PE /* \wrlvl_dq_seq[3] */ #( @@ -129652,7 +129557,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4 .Q (wrlvl_dq_seq[3]), .CE (N466), .CLK (ddrphy_clkin), - .D (_N63087), + .D (_N64198), .P (N0)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:545 @@ -129824,41 +129729,41 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3 wire _N16; wire _N19; wire _N21; - wire _N97659; - wire _N97664; - wire _N103354; - wire _N103355; - wire _N105840; - wire _N105844; - wire _N105848; - wire _N105852; - wire _N105856; - wire _N105860; - wire _N105864; - wire _N105868; - wire _N105872; - wire _N105875; - wire _N105985; - wire _N105989; - wire _N105993; - wire _N105997; - wire _N106001; - wire _N106012; - wire _N106016; - wire _N106020; - wire _N106024; - wire _N106028; - wire _N106032; - wire _N106036; - wire _N106037; - wire _N106043; - wire _N106047; - wire _N106068; - wire _N106072; - wire _N106076; - wire _N106080; - wire _N106083; - wire _N106087; + wire _N98457; + wire _N98462; + wire _N104166; + wire _N104167; + wire _N106662; + wire _N106666; + wire _N106670; + wire _N106674; + wire _N106678; + wire _N106682; + wire _N106686; + wire _N106690; + wire _N106694; + wire _N106697; + wire _N106805; + wire _N106809; + wire _N106813; + wire _N106817; + wire _N106821; + wire _N106832; + wire _N106836; + wire _N106840; + wire _N106844; + wire _N106848; + wire _N106852; + wire _N106856; + wire _N106857; + wire _N106863; + wire _N106867; + wire _N106888; + wire _N106892; + wire _N106896; + wire _N106900; + wire _N106903; + wire _N106907; wire [2:0] gdet_next_state; wire [5:0] gdet_state_reg; @@ -129867,8 +129772,8 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3 N21_2 ( .Z (N328[2]), .I0 (read_valid), - .I1 (_N97659), - .I2 (_N97664)); + .I1 (_N98457), + .I2 (_N98462)); // LUT = I0&I1&I2 ; GTP_LUT3 /* \N57_12_or[1] */ #( @@ -129892,7 +129797,7 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3 GTP_LUT5 /* N118_5 */ #( .INIT(32'b10000000000000000000000000000000)) N118_5 ( - .Z (_N106068), + .Z (_N106888), .I0 (read_data[6]), .I1 (read_data[12]), .I2 (read_data[14]), @@ -129903,7 +129808,7 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3 GTP_LUT5 /* N118_9 */ #( .INIT(32'b10000000000000000000000000000000)) N118_9 ( - .Z (_N106072), + .Z (_N106892), .I0 (read_data[28]), .I1 (read_data[30]), .I2 (read_data[36]), @@ -129914,7 +129819,7 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3 GTP_LUT5 /* N118_13 */ #( .INIT(32'b10000000000000000000000000000000)) N118_13 ( - .Z (_N106076), + .Z (_N106896), .I0 (read_data[46]), .I1 (read_data[52]), .I2 (read_data[54]), @@ -129925,7 +129830,7 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3 GTP_LUT5 /* N118_17 */ #( .INIT(32'b00000000000000000000000000000001)) N118_17 ( - .Z (_N106080), + .Z (_N106900), .I0 (read_data[3]), .I1 (read_data[11]), .I2 (read_data[19]), @@ -129936,7 +129841,7 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3 GTP_LUT5 /* N118_20 */ #( .INIT(32'b00000000000000100000000000000000)) N118_20 ( - .Z (_N106083), + .Z (_N106903), .I0 (read_data[4]), .I1 (read_data[43]), .I2 (read_data[51]), @@ -129947,26 +129852,26 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3 GTP_LUT4 /* N118_24 */ #( .INIT(16'b1000000000000000)) N118_24 ( - .Z (_N106087), - .I0 (_N106068), - .I1 (_N106072), - .I2 (_N106076), - .I3 (_N106080)); + .Z (_N106907), + .I0 (_N106888), + .I1 (_N106892), + .I2 (_N106896), + .I3 (_N106900)); // LUT = I0&I1&I2&I3 ; GTP_LUT3 /* N118_25 */ #( .INIT(8'b10000000)) N118_25 ( .Z (N118), - .I0 (_N97659), - .I1 (_N106083), - .I2 (_N106087)); + .I0 (_N98457), + .I1 (_N106903), + .I2 (_N106907)); // LUT = I0&I1&I2 ; - GTP_LUT5 /* N172_64 */ #( + GTP_LUT5 /* N172_62 */ #( .INIT(32'b10000000000000000000000000000000)) - N172_64 ( - .Z (_N105840), + N172_62 ( + .Z (_N106662), .I0 (read_data[1]), .I1 (read_data[5]), .I2 (read_data[7]), @@ -129974,10 +129879,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3 .I4 (read_data[13])); // LUT = I0&I1&I2&I3&I4 ; - GTP_LUT5 /* N172_68 */ #( + GTP_LUT5 /* N172_66 */ #( .INIT(32'b10000000000000000000000000000000)) - N172_68 ( - .Z (_N105844), + N172_66 ( + .Z (_N106666), .I0 (read_data[15]), .I1 (read_data[17]), .I2 (read_data[21]), @@ -129985,10 +129890,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3 .I4 (read_data[25])); // LUT = I0&I1&I2&I3&I4 ; - GTP_LUT5 /* N172_72 */ #( + GTP_LUT5 /* N172_70 */ #( .INIT(32'b10000000000000000000000000000000)) - N172_72 ( - .Z (_N105848), + N172_70 ( + .Z (_N106670), .I0 (read_data[29]), .I1 (read_data[31]), .I2 (read_data[33]), @@ -129996,10 +129901,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3 .I4 (read_data[39])); // LUT = I0&I1&I2&I3&I4 ; - GTP_LUT5 /* N172_76 */ #( + GTP_LUT5 /* N172_74 */ #( .INIT(32'b10000000000000000000000000000000)) - N172_76 ( - .Z (_N105852), + N172_74 ( + .Z (_N106674), .I0 (read_data[41]), .I1 (read_data[45]), .I2 (read_data[47]), @@ -130007,10 +129912,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3 .I4 (read_data[53])); // LUT = I0&I1&I2&I3&I4 ; - GTP_LUT5 /* N172_80 */ #( + GTP_LUT5 /* N172_78 */ #( .INIT(32'b01000000000000000000000000000000)) - N172_80 ( - .Z (_N105856), + N172_78 ( + .Z (_N106678), .I0 (read_data[0]), .I1 (read_data[55]), .I2 (read_data[57]), @@ -130018,10 +129923,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3 .I4 (read_data[63])); // LUT = ~I0&I1&I2&I3&I4 ; - GTP_LUT5 /* N172_84 */ #( + GTP_LUT5 /* N172_82 */ #( .INIT(32'b00000000000000000000000000000001)) - N172_84 ( - .Z (_N105860), + N172_82 ( + .Z (_N106682), .I0 (read_data[2]), .I1 (read_data[8]), .I2 (read_data[10]), @@ -130029,10 +129934,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3 .I4 (read_data[18])); // LUT = ~I0&~I1&~I2&~I3&~I4 ; - GTP_LUT5 /* N172_88 */ #( + GTP_LUT5 /* N172_86 */ #( .INIT(32'b00000000000000000000000000000001)) - N172_88 ( - .Z (_N105864), + N172_86 ( + .Z (_N106686), .I0 (read_data[24]), .I1 (read_data[26]), .I2 (read_data[32]), @@ -130040,10 +129945,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3 .I4 (read_data[40])); // LUT = ~I0&~I1&~I2&~I3&~I4 ; - GTP_LUT5 /* N172_92 */ #( + GTP_LUT5 /* N172_90 */ #( .INIT(32'b00000000000000000000000000000001)) - N172_92 ( - .Z (_N105868), + N172_90 ( + .Z (_N106690), .I0 (read_data[42]), .I1 (read_data[48]), .I2 (read_data[50]), @@ -130051,96 +129956,31 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3 .I4 (read_data[58])); // LUT = ~I0&~I1&~I2&~I3&~I4 ; - GTP_LUT5 /* N172_96 */ #( + GTP_LUT5 /* N172_94 */ #( .INIT(32'b10000000000000000000000000000000)) - N172_96 ( - .Z (_N105872), - .I0 (_N97664), - .I1 (_N105840), - .I2 (_N105844), - .I3 (_N105848), - .I4 (_N105852)); + N172_94 ( + .Z (_N106694), + .I0 (_N98462), + .I1 (_N106662), + .I2 (_N106666), + .I3 (_N106670), + .I4 (_N106674)); // LUT = I0&I1&I2&I3&I4 ; - GTP_LUT4 /* N172_99 */ #( - .INIT(16'b1000000000000000)) - N172_99 ( - .Z (_N105875), - .I0 (_N105856), - .I1 (_N105860), - .I2 (_N105864), - .I3 (_N105868)); - // LUT = I0&I1&I2&I3 ; - - GTP_LUT4 /* N172_103 */ #( + GTP_LUT4 /* N172_97 */ #( .INIT(16'b1000000000000000)) - N172_103 ( - .Z (_N105985), - .I0 (read_data[3]), - .I1 (read_data[11]), - .I2 (read_data[19]), - .I3 (read_data[27])); + N172_97 ( + .Z (_N106697), + .I0 (_N106678), + .I1 (_N106682), + .I2 (_N106686), + .I3 (_N106690)); // LUT = I0&I1&I2&I3 ; - GTP_LUT5 /* N172_107 */ #( - .INIT(32'b01000000000000000000000000000000)) - N172_107 ( - .Z (_N105989), - .I0 (read_data[4]), - .I1 (read_data[35]), - .I2 (read_data[43]), - .I3 (read_data[51]), - .I4 (read_data[59])); - // LUT = ~I0&I1&I2&I3&I4 ; - - GTP_LUT5 /* N172_111 */ #( - .INIT(32'b00000000000000000000000000000001)) - N172_111 ( - .Z (_N105993), - .I0 (read_data[6]), - .I1 (read_data[12]), - .I2 (read_data[14]), - .I3 (read_data[20]), - .I4 (read_data[22])); - // LUT = ~I0&~I1&~I2&~I3&~I4 ; - - GTP_LUT5 /* N172_115 */ #( - .INIT(32'b00000000000000000000000000000001)) - N172_115 ( - .Z (_N105997), - .I0 (read_data[28]), - .I1 (read_data[30]), - .I2 (read_data[36]), - .I3 (read_data[38]), - .I4 (read_data[44])); - // LUT = ~I0&~I1&~I2&~I3&~I4 ; - - GTP_LUT5 /* N172_119 */ #( - .INIT(32'b00000000000000000000000000000001)) - N172_119 ( - .Z (_N106001), - .I0 (read_data[46]), - .I1 (read_data[52]), - .I2 (read_data[54]), - .I3 (read_data[60]), - .I4 (read_data[62])); - // LUT = ~I0&~I1&~I2&~I3&~I4 ; - - GTP_LUT5 /* N172_123 */ #( - .INIT(32'b10000000000000000000000000000000)) - N172_123 ( - .Z (_N97664), - .I0 (_N105985), - .I1 (_N105989), - .I2 (_N105993), - .I3 (_N105997), - .I4 (_N106001)); - // LUT = I0&I1&I2&I3&I4 ; - - GTP_LUT5 /* N257_44 */ #( + GTP_LUT5 /* N172_105 */ #( .INIT(32'b10000000000000000000000000000000)) - N257_44 ( - .Z (_N106012), + N172_105 ( + .Z (_N106832), .I0 (read_data[16]), .I1 (read_data[18]), .I2 (read_data[24]), @@ -130148,10 +129988,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3 .I4 (read_data[32])); // LUT = I0&I1&I2&I3&I4 ; - GTP_LUT5 /* N257_48 */ #( + GTP_LUT5 /* N172_109 */ #( .INIT(32'b10000000000000000000000000000000)) - N257_48 ( - .Z (_N106016), + N172_109 ( + .Z (_N106836), .I0 (read_data[34]), .I1 (read_data[40]), .I2 (read_data[42]), @@ -130159,10 +129999,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3 .I4 (read_data[50])); // LUT = I0&I1&I2&I3&I4 ; - GTP_LUT5 /* N257_52 */ #( + GTP_LUT5 /* N172_113 */ #( .INIT(32'b00000001000000000000000000000000)) - N257_52 ( - .Z (_N106020), + N172_113 ( + .Z (_N106840), .I0 (read_data[1]), .I1 (read_data[5]), .I2 (read_data[7]), @@ -130170,10 +130010,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3 .I4 (read_data[58])); // LUT = ~I0&~I1&~I2&I3&I4 ; - GTP_LUT5 /* N257_56 */ #( + GTP_LUT5 /* N172_117 */ #( .INIT(32'b00000000000000000000000000000001)) - N257_56 ( - .Z (_N106024), + N172_117 ( + .Z (_N106844), .I0 (read_data[9]), .I1 (read_data[13]), .I2 (read_data[15]), @@ -130181,10 +130021,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3 .I4 (read_data[21])); // LUT = ~I0&~I1&~I2&~I3&~I4 ; - GTP_LUT5 /* N257_60 */ #( + GTP_LUT5 /* N172_121 */ #( .INIT(32'b00000000000000000000000000000001)) - N257_60 ( - .Z (_N106028), + N172_121 ( + .Z (_N106848), .I0 (read_data[23]), .I1 (read_data[25]), .I2 (read_data[29]), @@ -130192,10 +130032,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3 .I4 (read_data[33])); // LUT = ~I0&~I1&~I2&~I3&~I4 ; - GTP_LUT5 /* N257_64 */ #( + GTP_LUT5 /* N172_125 */ #( .INIT(32'b00000000000000000000000000000001)) - N257_64 ( - .Z (_N106032), + N172_125 ( + .Z (_N106852), .I0 (read_data[37]), .I1 (read_data[39]), .I2 (read_data[41]), @@ -130203,10 +130043,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3 .I4 (read_data[47])); // LUT = ~I0&~I1&~I2&~I3&~I4 ; - GTP_LUT5 /* N257_68 */ #( + GTP_LUT5 /* N172_129 */ #( .INIT(32'b00000000000000000000000000000001)) - N257_68 ( - .Z (_N106036), + N172_129 ( + .Z (_N106856), .I0 (read_data[49]), .I1 (read_data[53]), .I2 (read_data[55]), @@ -130214,10 +130054,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3 .I4 (read_data[61])); // LUT = ~I0&~I1&~I2&~I3&~I4 ; - GTP_LUT5 /* N257_69 */ #( + GTP_LUT5 /* N172_130 */ #( .INIT(32'b00000000000000001000000000000000)) - N257_69 ( - .Z (_N106037), + N172_130 ( + .Z (_N106857), .I0 (read_data[0]), .I1 (read_data[2]), .I2 (read_data[8]), @@ -130225,25 +130065,90 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3 .I4 (read_data[63])); // LUT = I0&I1&I2&I3&~I4 ; - GTP_LUT4 /* N257_75 */ #( + GTP_LUT4 /* N172_136 */ #( .INIT(16'b1000000000000000)) - N257_75 ( - .Z (_N106043), - .I0 (_N106024), - .I1 (_N106028), - .I2 (_N106032), - .I3 (_N106036)); + N172_136 ( + .Z (_N106863), + .I0 (_N106844), + .I1 (_N106848), + .I2 (_N106852), + .I3 (_N106856)); // LUT = I0&I1&I2&I3 ; - GTP_LUT5 /* N257_76 */ #( + GTP_LUT5 /* N172_137 */ #( .INIT(32'b10000000000000000000000000000000)) - N257_76 ( - .Z (_N97659), - .I0 (_N106012), - .I1 (_N106016), - .I2 (_N106020), - .I3 (_N106037), - .I4 (_N106043)); + N172_137 ( + .Z (_N98457), + .I0 (_N106832), + .I1 (_N106836), + .I2 (_N106840), + .I3 (_N106857), + .I4 (_N106863)); + // LUT = I0&I1&I2&I3&I4 ; + + GTP_LUT4 /* N202_35 */ #( + .INIT(16'b1000000000000000)) + N202_35 ( + .Z (_N106805), + .I0 (read_data[3]), + .I1 (read_data[11]), + .I2 (read_data[19]), + .I3 (read_data[27])); + // LUT = I0&I1&I2&I3 ; + + GTP_LUT5 /* N202_39 */ #( + .INIT(32'b01000000000000000000000000000000)) + N202_39 ( + .Z (_N106809), + .I0 (read_data[4]), + .I1 (read_data[35]), + .I2 (read_data[43]), + .I3 (read_data[51]), + .I4 (read_data[59])); + // LUT = ~I0&I1&I2&I3&I4 ; + + GTP_LUT5 /* N202_43 */ #( + .INIT(32'b00000000000000000000000000000001)) + N202_43 ( + .Z (_N106813), + .I0 (read_data[6]), + .I1 (read_data[12]), + .I2 (read_data[14]), + .I3 (read_data[20]), + .I4 (read_data[22])); + // LUT = ~I0&~I1&~I2&~I3&~I4 ; + + GTP_LUT5 /* N202_47 */ #( + .INIT(32'b00000000000000000000000000000001)) + N202_47 ( + .Z (_N106817), + .I0 (read_data[28]), + .I1 (read_data[30]), + .I2 (read_data[36]), + .I3 (read_data[38]), + .I4 (read_data[44])); + // LUT = ~I0&~I1&~I2&~I3&~I4 ; + + GTP_LUT5 /* N202_51 */ #( + .INIT(32'b00000000000000000000000000000001)) + N202_51 ( + .Z (_N106821), + .I0 (read_data[46]), + .I1 (read_data[52]), + .I2 (read_data[54]), + .I3 (read_data[60]), + .I4 (read_data[62])); + // LUT = ~I0&~I1&~I2&~I3&~I4 ; + + GTP_LUT5 /* N202_55 */ #( + .INIT(32'b10000000000000000000000000000000)) + N202_55 ( + .Z (_N98462), + .I0 (_N106805), + .I1 (_N106809), + .I2 (_N106813), + .I3 (_N106817), + .I4 (_N106821)); // LUT = I0&I1&I2&I3&I4 ; GTP_LUT2 /* N306_1 */ #( @@ -130327,13 +130232,13 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3 .I1 (dqs_gate_vld), .I2 (gdet_state_reg[0]), .I3 (gdet_state_reg[2]), - .I4 (_N106047)); + .I4 (_N106867)); // LUT = (~I1&I2)|(I0&I3)|(I0&I4) ; GTP_LUT2 /* \gdet_state_fsm[2:0]_39_2 */ #( .INIT(4'b1110)) \gdet_state_fsm[2:0]_39_2 ( - .Z (_N106047), + .Z (_N106867), .I0 (gdet_state_reg[1]), .I1 (gdet_state_reg[4])); // LUT = (I0)|(I1) ; @@ -130395,14 +130300,14 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3 .Q (rddata_check_pass), .C (N0), .CLK (ddrphy_clkin), - .D (_N103355)); + .D (_N104167)); // defparam rddata_check_pass_vname.orig_name = rddata_check_pass; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqs_rddata_align_v1_3.vp:416 GTP_LUT5 /* rddata_check_pass_ce_mux */ #( .INIT(32'b11111111111111001010101010101000)) rddata_check_pass_ce_mux ( - .Z (_N103355), + .Z (_N104167), .I0 (rddata_check_pass), .I1 (gdet_next_state[2]), .I2 (gdet_next_state[1]), @@ -131056,7 +130961,7 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3 rdel_rvalid_vname ( .Q (rdel_rvalid), .CLK (ddrphy_clkin), - .D (_N103354), + .D (_N104166), .P (N0)); // defparam rdel_rvalid_vname.orig_name = rdel_rvalid; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqs_rddata_align_v1_3.vp:427 @@ -131064,12 +130969,12 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3 GTP_LUT5 /* rdel_rvalid_ce_mux */ #( .INIT(32'b11110011011100110111001101110011)) rdel_rvalid_ce_mux ( - .Z (_N103354), + .Z (_N104166), .I0 (read_valid), .I1 (rdel_cal_vld), .I2 (rdel_rvalid), - .I3 (_N105872), - .I4 (_N105875)); + .I3 (_N106694), + .I4 (_N106697)); // LUT = (~I1)|(~I0&I2)|(I2&I3&I4) ; GTP_DFF_C /* rdvalid_r1 */ #( @@ -131089,13 +130994,12 @@ endmodule module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 ( input [7:0] dll_step, - input [9:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt , + input [9:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt , input [9:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt , input N0, input _N538, - input _N83022, - input _N83332, - input _N105278, + input _N84178, + input _N106091, input ddrphy_clkin, input init_adj_rdel, input rdel_calibration, @@ -131108,12 +131012,11 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 output [7:0] default_samp_position, output [2:0] rdel_ctrl_wire, output [7:0] total_margin_div2, - output _N81412_3, - output _N81412_5, - output _N96160, - output _N96167, - output _N105817, - output _N106624, + output _N82185_3, + output _N82185_5, + output _N96937, + output _N96942, + output _N106639, output adj_rdel_done, output rdel_cal_vld, output rdel_calib_done, @@ -131165,83 +131068,87 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 wire _N276; wire _N278; wire _N280; - wire _N5568; - wire _N14176; - wire _N14177; - wire _N14178; - wire _N14179; - wire _N14180; - wire _N14181; - wire _N14182; - wire _N14639; - wire _N14640; + wire _N5562; + wire _N13986; + wire _N13987; + wire _N13988; + wire _N13989; + wire _N13990; + wire _N13991; + wire _N13992; + wire _N14598; + wire _N14599; + wire _N14600; + wire _N14601; + wire _N14602; + wire _N14603; + wire _N14622; + wire _N14623; + wire _N14624; + wire _N14625; + wire _N14626; + wire _N14627; + wire _N14628; + wire _N14629; + wire _N14632; + wire _N14633; + wire _N14634; + wire _N14635; + wire _N14636; + wire _N14637; + wire _N14638; wire _N14641; wire _N14642; wire _N14643; wire _N14644; - wire _N14663; - wire _N14664; - wire _N14665; - wire _N14666; - wire _N14667; - wire _N14668; - wire _N14669; - wire _N14670; - wire _N14673; - wire _N14674; - wire _N14675; - wire _N14676; - wire _N14677; - wire _N14678; - wire _N14679; - wire _N14682; - wire _N14683; - wire _N14684; - wire _N14685; - wire _N14686; - wire _N14687; - wire _N14688; - wire _N14689; - wire _N16998; - wire _N16999; - wire _N17000; - wire _N17001; - wire _N17002; - wire _N17003; - wire _N17004; - wire _N22748; - wire _N22793; - wire _N22819; - wire _N22825_inv; - wire _N22828; - wire _N22829; - wire _N22830; - wire _N22831; - wire _N22832; - wire _N22833; - wire _N30142; - wire _N82537; - wire _N86995; - wire _N96148; - wire _N98671; - wire _N103356; - wire _N103357; - wire _N103358; - wire _N103359; - wire _N103360; - wire _N103361; - wire _N105812; - wire _N105823; - wire _N105824; - wire _N105825; - wire _N105826; - wire _N105830; - wire _N105832; - wire _N105880; - wire _N105881; - wire _N105884; - wire _N106534; - wire _N106564; + wire _N14645; + wire _N14646; + wire _N14647; + wire _N14648; + wire _N16968; + wire _N16969; + wire _N16970; + wire _N16971; + wire _N16972; + wire _N16973; + wire _N16974; + wire _N22723; + wire _N22768; + wire _N22794; + wire _N22800_inv; + wire _N22803; + wire _N22804; + wire _N22805; + wire _N22806; + wire _N22807; + wire _N22808; + wire _N30245; + wire _N84099; + wire _N87783; + wire _N96930; + wire _N101396; + wire _N104168; + wire _N104169; + wire _N104170; + wire _N104171; + wire _N104172; + wire _N104173; + wire _N106097; + wire _N106098; + wire _N106099; + wire _N106100; + wire _N106634; + wire _N106645; + wire _N106646; + wire _N106647; + wire _N106648; + wire _N106652; + wire _N106654; + wire _N106702; + wire _N106703; + wire _N106706; + wire _N107352; + wire _N107382; wire [7:0] adj_cnt; wire adj_inc_dec_n; wire [7:0] init_dqsi_value; @@ -131320,11 +131227,11 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_LUT("FALSE")) \N28_1.fsub_1 ( .COUT (\N28_1.co [1] ), - .Z (_N22828), + .Z (_N22803), .CIN (\N28_1.co [0] ), .I0 (), .I1 (default_samp_position[1]), - .I2 (_N22793), + .I2 (_N22768), .I3 (N716[1]), .I4 (default_samp_position[1]), .ID ()); @@ -131340,11 +131247,11 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_LUT("FALSE")) \N28_1.fsub_2 ( .COUT (\N28_1.co [2] ), - .Z (_N22829), + .Z (_N22804), .CIN (\N28_1.co [1] ), .I0 (), .I1 (default_samp_position[2]), - .I2 (_N22793), + .I2 (_N22768), .I3 (N716[2]), .I4 (default_samp_position[2]), .ID ()); @@ -131360,11 +131267,11 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_LUT("FALSE")) \N28_1.fsub_3 ( .COUT (\N28_1.co [3] ), - .Z (_N22830), + .Z (_N22805), .CIN (\N28_1.co [2] ), .I0 (), .I1 (default_samp_position[3]), - .I2 (_N22793), + .I2 (_N22768), .I3 (N716[3]), .I4 (default_samp_position[3]), .ID ()); @@ -131380,11 +131287,11 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_LUT("FALSE")) \N28_1.fsub_4 ( .COUT (\N28_1.co [4] ), - .Z (_N22831), + .Z (_N22806), .CIN (\N28_1.co [3] ), .I0 (), .I1 (default_samp_position[4]), - .I2 (_N22793), + .I2 (_N22768), .I3 (N716[4]), .I4 (default_samp_position[4]), .ID ()); @@ -131400,11 +131307,11 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_LUT("FALSE")) \N28_1.fsub_5 ( .COUT (\N28_1.co [5] ), - .Z (_N22832), + .Z (_N22807), .CIN (\N28_1.co [4] ), .I0 (), .I1 (default_samp_position[5]), - .I2 (_N22793), + .I2 (_N22768), .I3 (N716[5]), .I4 (default_samp_position[5]), .ID ()); @@ -131420,11 +131327,11 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_LUT("FALSE")) \N28_1.fsub_6 ( .COUT (), - .Z (_N22833), + .Z (_N22808), .CIN (\N28_1.co [5] ), .I0 (), .I1 (default_samp_position[6]), - .I2 (_N22793), + .I2 (_N22768), .I3 (N716[6]), .I4 (default_samp_position[6]), .ID ()); @@ -131439,7 +131346,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N33_1_1 ( - .COUT (_N14639), + .COUT (_N14598), .Z (N716[1]), .CIN (), .I0 (default_samp_position[0]), @@ -131459,9 +131366,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N33_1_2 ( - .COUT (_N14640), + .COUT (_N14599), .Z (N716[2]), - .CIN (_N14639), + .CIN (_N14598), .I0 (default_samp_position[0]), .I1 (default_samp_position[1]), .I2 (default_samp_position[2]), @@ -131479,9 +131386,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N33_1_3 ( - .COUT (_N14641), + .COUT (_N14600), .Z (N716[3]), - .CIN (_N14640), + .CIN (_N14599), .I0 (), .I1 (default_samp_position[3]), .I2 (), @@ -131499,9 +131406,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N33_1_4 ( - .COUT (_N14642), + .COUT (_N14601), .Z (N716[4]), - .CIN (_N14641), + .CIN (_N14600), .I0 (), .I1 (default_samp_position[4]), .I2 (), @@ -131519,9 +131426,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N33_1_5 ( - .COUT (_N14643), + .COUT (_N14602), .Z (N716[5]), - .CIN (_N14642), + .CIN (_N14601), .I0 (), .I1 (default_samp_position[5]), .I2 (), @@ -131539,9 +131446,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N33_1_6 ( - .COUT (_N14644), + .COUT (_N14603), .Z (N716[6]), - .CIN (_N14643), + .CIN (_N14602), .I0 (), .I1 (default_samp_position[6]), .I2 (), @@ -131561,7 +131468,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 N33_1_7 ( .COUT (), .Z (N716[7]), - .CIN (_N14644), + .CIN (_N14603), .I0 (), .I1 (default_samp_position[7]), .I2 (), @@ -131810,7 +131717,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N85_1 ( - .COUT (_N14673), + .COUT (_N14632), .Z (total_margin_div2[0]), .CIN (), .I0 (samp_win_size[0]), @@ -131830,9 +131737,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N85_2 ( - .COUT (_N14674), + .COUT (_N14633), .Z (total_margin_div2[1]), - .CIN (_N14673), + .CIN (_N14632), .I0 (samp_win_size[0]), .I1 (samp_win_size[1]), .I2 (samp_win_size[2]), @@ -131850,9 +131757,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N85_3 ( - .COUT (_N14675), + .COUT (_N14634), .Z (total_margin_div2[2]), - .CIN (_N14674), + .CIN (_N14633), .I0 (), .I1 (samp_win_size[3]), .I2 (), @@ -131870,9 +131777,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N85_4 ( - .COUT (_N14676), + .COUT (_N14635), .Z (total_margin_div2[3]), - .CIN (_N14675), + .CIN (_N14634), .I0 (), .I1 (samp_win_size[4]), .I2 (), @@ -131890,9 +131797,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N85_5 ( - .COUT (_N14677), + .COUT (_N14636), .Z (total_margin_div2[4]), - .CIN (_N14676), + .CIN (_N14635), .I0 (), .I1 (samp_win_size[5]), .I2 (), @@ -131910,9 +131817,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N85_6 ( - .COUT (_N14678), + .COUT (_N14637), .Z (total_margin_div2[5]), - .CIN (_N14677), + .CIN (_N14636), .I0 (), .I1 (samp_win_size[6]), .I2 (), @@ -131930,9 +131837,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N85_7 ( - .COUT (_N14679), + .COUT (_N14638), .Z (total_margin_div2[6]), - .CIN (_N14678), + .CIN (_N14637), .I0 (), .I1 (samp_win_size[7]), .I2 (), @@ -131952,7 +131859,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 N85_8 ( .COUT (), .Z (total_margin_div2[7]), - .CIN (_N14679), + .CIN (_N14638), .I0 (), .I1 (total_margin[8]), .I2 (), @@ -131970,7 +131877,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_1 ( - .COUT (_N14663), + .COUT (_N14622), .Z (N604[1]), .CIN (), .I0 (cnt[0]), @@ -131990,9 +131897,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_2 ( - .COUT (_N14664), + .COUT (_N14623), .Z (N604[2]), - .CIN (_N14663), + .CIN (_N14622), .I0 (cnt[0]), .I1 (cnt[1]), .I2 (N694_inv), @@ -132010,9 +131917,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_3 ( - .COUT (_N14665), + .COUT (_N14624), .Z (N604[3]), - .CIN (_N14664), + .CIN (_N14623), .I0 (), .I1 (cnt[3]), .I2 (N694_inv), @@ -132030,9 +131937,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_4 ( - .COUT (_N14666), + .COUT (_N14625), .Z (N604[4]), - .CIN (_N14665), + .CIN (_N14624), .I0 (), .I1 (cnt[4]), .I2 (N694_inv), @@ -132050,9 +131957,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_5 ( - .COUT (_N14667), + .COUT (_N14626), .Z (N604[5]), - .CIN (_N14666), + .CIN (_N14625), .I0 (), .I1 (cnt[5]), .I2 (N694_inv), @@ -132070,9 +131977,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_6 ( - .COUT (_N14668), + .COUT (_N14627), .Z (N604[6]), - .CIN (_N14667), + .CIN (_N14626), .I0 (), .I1 (cnt[6]), .I2 (N694_inv), @@ -132090,9 +131997,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_7 ( - .COUT (_N14669), + .COUT (_N14628), .Z (N604[7]), - .CIN (_N14668), + .CIN (_N14627), .I0 (), .I1 (cnt[7]), .I2 (N694_inv), @@ -132110,9 +132017,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_8 ( - .COUT (_N14670), + .COUT (_N14629), .Z (N604[8]), - .CIN (_N14669), + .CIN (_N14628), .I0 (), .I1 (cnt[8]), .I2 (N694_inv), @@ -132132,7 +132039,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 N104_1_9 ( .COUT (), .Z (N604[9]), - .CIN (_N14670), + .CIN (_N14629), .I0 (), .I1 (cnt[9]), .I2 (N694_inv), @@ -132362,19 +132269,27 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I1 (state_reg[2]), .I2 (state_reg[7]), .I3 (state_reg[10]), - .I4 (_N82537)); + .I4 (_N84099)); // LUT = (I0&I1)|(I0&I2)|(I0&I3)|(I0&I4) ; GTP_LUT4 /* \N247_1_1_or[0]_3 */ #( .INIT(16'b0001000100010000)) \N247_1_1_or[0]_3 ( - .Z (_N82537), + .Z (_N84099), .I0 (cnt[3]), .I1 (cnt[2]), .I2 (state_reg[5]), .I3 (state_reg[9])); // LUT = (~I0&~I1&I2)|(~I0&~I1&I3) ; + GTP_LUT2 /* \N247_1_1_or[0]_4 */ #( + .INIT(4'b1110)) + \N247_1_1_or[0]_4 ( + .Z (N679), + .I0 (state_reg[5]), + .I1 (state_reg[9])); + // LUT = (I0)|(I1) ; + GTP_LUT1 /* N249 */ #( .INIT(2'b01)) N249 ( @@ -132398,7 +132313,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_CARRY("FALSE"), .I4_TO_LUT("FALSE")) N264_1_0 ( - .COUT (_N16998), + .COUT (_N13986), .Z (), .CIN (), .I0 (), @@ -132418,9 +132333,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N264_1_1 ( - .COUT (_N16999), + .COUT (_N13987), .Z (N608[1]), - .CIN (_N16998), + .CIN (_N13986), .I0 (), .I1 (left_margin[1]), .I2 (rdel_calibration), @@ -132438,9 +132353,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N264_1_2 ( - .COUT (_N17000), + .COUT (_N13988), .Z (N608[2]), - .CIN (_N16999), + .CIN (_N13987), .I0 (), .I1 (left_margin[2]), .I2 (rdel_calibration), @@ -132458,9 +132373,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N264_1_3 ( - .COUT (_N17001), + .COUT (_N13989), .Z (N608[3]), - .CIN (_N17000), + .CIN (_N13988), .I0 (), .I1 (left_margin[3]), .I2 (rdel_calibration), @@ -132478,9 +132393,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N264_1_4 ( - .COUT (_N17002), + .COUT (_N13990), .Z (N608[4]), - .CIN (_N17001), + .CIN (_N13989), .I0 (), .I1 (left_margin[4]), .I2 (rdel_calibration), @@ -132498,9 +132413,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N264_1_5 ( - .COUT (_N17003), + .COUT (_N13991), .Z (N608[5]), - .CIN (_N17002), + .CIN (_N13990), .I0 (), .I1 (left_margin[5]), .I2 (rdel_calibration), @@ -132518,9 +132433,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N264_1_6 ( - .COUT (_N17004), + .COUT (_N13992), .Z (N608[6]), - .CIN (_N17003), + .CIN (_N13991), .I0 (), .I1 (left_margin[6]), .I2 (rdel_calibration), @@ -132540,7 +132455,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 N264_1_7 ( .COUT (), .Z (N608[7]), - .CIN (_N17004), + .CIN (_N13992), .I0 (), .I1 (left_margin[7]), .I2 (rdel_calibration), @@ -132558,7 +132473,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_CARRY("FALSE"), .I4_TO_LUT("FALSE")) N280_1_0 ( - .COUT (_N14176), + .COUT (_N16968), .Z (), .CIN (), .I0 (), @@ -132578,9 +132493,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N280_1_1 ( - .COUT (_N14177), + .COUT (_N16969), .Z (N611[1]), - .CIN (_N14176), + .CIN (_N16968), .I0 (), .I1 (right_margin[1]), .I2 (rdel_calibration), @@ -132598,9 +132513,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N280_1_2 ( - .COUT (_N14178), + .COUT (_N16970), .Z (N611[2]), - .CIN (_N14177), + .CIN (_N16969), .I0 (), .I1 (right_margin[2]), .I2 (rdel_calibration), @@ -132618,9 +132533,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N280_1_3 ( - .COUT (_N14179), + .COUT (_N16971), .Z (N611[3]), - .CIN (_N14178), + .CIN (_N16970), .I0 (), .I1 (right_margin[3]), .I2 (rdel_calibration), @@ -132638,9 +132553,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N280_1_4 ( - .COUT (_N14180), + .COUT (_N16972), .Z (N611[4]), - .CIN (_N14179), + .CIN (_N16971), .I0 (), .I1 (right_margin[4]), .I2 (rdel_calibration), @@ -132658,9 +132573,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N280_1_5 ( - .COUT (_N14181), + .COUT (_N16973), .Z (N611[5]), - .CIN (_N14180), + .CIN (_N16972), .I0 (), .I1 (right_margin[5]), .I2 (rdel_calibration), @@ -132678,9 +132593,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N280_1_6 ( - .COUT (_N14182), + .COUT (_N16974), .Z (N611[6]), - .CIN (_N14181), + .CIN (_N16973), .I0 (), .I1 (right_margin[6]), .I2 (rdel_calibration), @@ -132700,7 +132615,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 N280_1_7 ( .COUT (), .Z (N611[7]), - .CIN (_N14182), + .CIN (_N16974), .I0 (), .I1 (right_margin[7]), .I2 (rdel_calibration), @@ -132718,7 +132633,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N285_1_1 ( - .COUT (_N14682), + .COUT (_N14641), .Z (N285[0]), .CIN (), .I0 (right_margin[0]), @@ -132738,9 +132653,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N285_1_2 ( - .COUT (_N14683), + .COUT (_N14642), .Z (N285[1]), - .CIN (_N14682), + .CIN (_N14641), .I0 (right_margin[0]), .I1 (left_margin[0]), .I2 (right_margin[1]), @@ -132758,9 +132673,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N285_1_3 ( - .COUT (_N14684), + .COUT (_N14643), .Z (N285[2]), - .CIN (_N14683), + .CIN (_N14642), .I0 (), .I1 (right_margin[2]), .I2 (left_margin[2]), @@ -132778,9 +132693,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N285_1_4 ( - .COUT (_N14685), + .COUT (_N14644), .Z (N285[3]), - .CIN (_N14684), + .CIN (_N14643), .I0 (), .I1 (right_margin[3]), .I2 (left_margin[3]), @@ -132798,9 +132713,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N285_1_5 ( - .COUT (_N14686), + .COUT (_N14645), .Z (N285[4]), - .CIN (_N14685), + .CIN (_N14644), .I0 (), .I1 (right_margin[4]), .I2 (left_margin[4]), @@ -132818,9 +132733,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N285_1_6 ( - .COUT (_N14687), + .COUT (_N14646), .Z (N285[5]), - .CIN (_N14686), + .CIN (_N14645), .I0 (), .I1 (right_margin[5]), .I2 (left_margin[5]), @@ -132838,9 +132753,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N285_1_7 ( - .COUT (_N14688), + .COUT (_N14647), .Z (N285[6]), - .CIN (_N14687), + .CIN (_N14646), .I0 (), .I1 (right_margin[6]), .I2 (left_margin[6]), @@ -132858,9 +132773,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N285_1_8 ( - .COUT (_N14689), + .COUT (_N14648), .Z (N285[7]), - .CIN (_N14688), + .CIN (_N14647), .I0 (), .I1 (right_margin[7]), .I2 (left_margin[7]), @@ -132880,7 +132795,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 N285_1_9 ( .COUT (), .Z (N285[8]), - .CIN (_N14689), + .CIN (_N14648), .I0 (), .I1 (), .I2 (), @@ -132894,7 +132809,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 GTP_LUT3 /* N295_mux2 */ #( .INIT(8'b01010111)) N295_mux2 ( - .Z (_N5568), + .Z (_N5562), .I0 (samp_win_size[3]), .I1 (samp_win_size[2]), .I2 (samp_win_size[1])); @@ -132953,21 +132868,13 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 GTP_LUT4 /* \N451_and[0][2] */ #( .INIT(16'b1010101010101000)) \N451_and[0][2] ( - .Z (_N30142), + .Z (_N30245), .I0 (default_samp_position[7]), .I1 (state_reg[1]), .I2 (state_reg[6]), .I3 (state_reg[7])); // LUT = (I0&I1)|(I0&I2)|(I0&I3) ; - GTP_LUT2 /* \N451_or[0]_1 */ #( - .INIT(4'b1110)) - \N451_or[0]_1 ( - .Z (N679), - .I0 (state_reg[5]), - .I1 (state_reg[9])); - // LUT = (I0)|(I1) ; - GTP_LUT3 /* N456 */ #( .INIT(8'b10101110)) N456_vname ( @@ -133145,7 +133052,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 GTP_LUT5M /* N564_20_3 */ #( .INIT(32'b10101010100010001111111111111110)) N564_20_3 ( - .Z (_N105880), + .Z (_N106702), .I0 (rdel_move_en), .I1 (state_reg[5]), .I2 (state_reg[6]), @@ -133157,11 +133064,11 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 GTP_LUT5M /* N564_20_4 */ #( .INIT(32'b11111111101010101111111100000100)) N564_20_4 ( - .Z (_N105881), + .Z (_N106703), .I0 (state_reg[11]), .I1 (state_reg[0]), .I2 (reinit_adj_rdel), - .I3 (_N86995), + .I3 (_N87783), .I4 (rdel_calibration), .ID (init_adj_rdel)); // LUT = (~ID&I1&~I2&~I4)|(I0&I4)|(I3) ; @@ -133169,11 +133076,11 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 GTP_LUT5M /* N564_20_7 */ #( .INIT(32'b11111111111110001111111111111110)) N564_20_7 ( - .Z (_N105884), + .Z (_N106706), .I0 (rdel_move_en), .I1 (state_reg[7]), - .I2 (_N105880), - .I3 (_N105881), + .I2 (_N106702), + .I3 (_N106703), .I4 (N108), .ID (state_reg[2])); // LUT = (I1&~I4)|(ID&~I4)|(I3)|(I2)|(I0&I1) ; @@ -133181,7 +133088,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 GTP_LUT3 /* N564_25 */ #( .INIT(8'b01010100)) N564_25 ( - .Z (_N86995), + .Z (_N87783), .I0 (rdel_move_en), .I1 (state_reg[4]), .I2 (state_reg[8])); @@ -133194,14 +133101,14 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I0 (rdel_move_en), .I1 (N167), .I2 (state_reg[10]), - .I3 (_N105884)); + .I3 (_N106706)); // defparam N570_vname.orig_name = N570; // LUT = (~I2&~I3)|(~I0&I1&~I3) ; GTP_LUT5 /* N598_1_2 */ #( .INIT(32'b11111111111111111111111111111110)) N598_1_2 ( - .Z (_N105830), + .Z (_N106652), .I0 (state_reg[0]), .I1 (state_reg[1]), .I2 (state_reg[4]), @@ -133212,12 +133119,12 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 GTP_LUT5 /* N598_1_4 */ #( .INIT(32'b11111111111111110111001101010000)) N598_1_4 ( - .Z (_N105832), + .Z (_N106654), .I0 (cnt[3]), .I1 (N108), .I2 (N679), .I3 (state_reg[7]), - .I4 (_N105830)); + .I4 (_N106652)); // LUT = (I4)|(~I1&I3)|(~I0&I2) ; GTP_LUT5 /* N598_1_6 */ #( @@ -133228,7 +133135,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I1 (N167), .I2 (state_reg[2]), .I3 (state_reg[10]), - .I4 (_N105832)); + .I4 (_N106654)); // LUT = (I4)|(~I1&I3)|(~I0&I2) ; GTP_LUT2 /* \N604_1[0]_1 */ #( @@ -133289,7 +133196,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 GTP_LUT4 /* N614_1_4 */ #( .INIT(16'b0000000000000001)) N614_1_4 ( - .Z (_N106534), + .Z (_N107352), .I0 (samp_win_size[7]), .I1 (samp_win_size[6]), .I2 (samp_win_size[5]), @@ -133299,7 +133206,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 GTP_LUT4 /* N621_1_2 */ #( .INIT(16'b1110111011101010)) N621_1_2 ( - .Z (_N106564), + .Z (_N107382), .I0 (rdel_calib_done), .I1 (cnt[3]), .I2 (state_reg[5]), @@ -133314,7 +133221,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I1 (N167), .I2 (state_reg[7]), .I3 (state_reg[10]), - .I4 (_N106564)); + .I4 (_N107382)); // LUT = (I4)|(I0&I2)|(I1&I3) ; GTP_LUT5 /* N633_3 */ #( @@ -133324,92 +133231,41 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I0 (default_samp_position[7]), .I1 (default_samp_position[0]), .I2 (adj_inc_dec_n), - .I3 (_N98671), - .I4 (_N105278)); + .I3 (_N101396), + .I4 (_N106091)); // LUT = I0&I1&I2&~I3&I4 ; - GTP_LUT4 /* N637_4 */ #( - .INIT(16'b1000010000100001)) - N637_4 ( - .Z (_N105823), - .I0 (cnt[8]), - .I1 (cnt[7]), - .I2 (default_samp_position[6]), - .I3 (default_samp_position[5])); - // LUT = (~I0&~I1&~I2&~I3)|(I0&~I1&I2&~I3)|(~I0&I1&~I2&I3)|(I0&I1&I2&I3) ; - - GTP_LUT4 /* N637_5 */ #( - .INIT(16'b1000010000100001)) - N637_5 ( - .Z (_N105824), - .I0 (cnt[6]), - .I1 (cnt[5]), - .I2 (default_samp_position[4]), - .I3 (default_samp_position[3])); - // LUT = (~I0&~I1&~I2&~I3)|(I0&~I1&I2&~I3)|(~I0&I1&~I2&I3)|(I0&I1&I2&I3) ; - - GTP_LUT4 /* N637_6 */ #( - .INIT(16'b1000010000100001)) - N637_6 ( - .Z (_N105825), - .I0 (cnt[4]), - .I1 (cnt[3]), - .I2 (default_samp_position[2]), - .I3 (default_samp_position[1])); - // LUT = (~I0&~I1&~I2&~I3)|(I0&~I1&I2&~I3)|(~I0&I1&~I2&I3)|(I0&I1&I2&I3) ; - - GTP_LUT5 /* N637_7 */ #( - .INIT(32'b00000000000001000000000000000001)) - N637_7 ( - .Z (_N105826), - .I0 (cnt[9]), - .I1 (cnt[2]), - .I2 (cnt[1]), - .I3 (cnt[0]), - .I4 (default_samp_position[0])); - // LUT = (~I0&~I1&~I2&~I3&~I4)|(~I0&I1&~I2&~I3&I4) ; - - GTP_LUT4 /* N637_10 */ #( - .INIT(16'b1000000000000000)) - N637_10 ( - .Z (_N96148), - .I0 (_N105823), - .I1 (_N105824), - .I2 (_N105825), - .I3 (_N105826)); - // LUT = I0&I1&I2&I3 ; - GTP_LUT5 /* N645_1 */ #( .INIT(32'b10101010101010111010101010101010)) N645_1 ( - .Z (_N22748), + .Z (_N22723), .I0 (N714[7]), .I1 (default_samp_position[6]), .I2 (default_samp_position[5]), .I3 (default_samp_position[0]), - .I4 (_N105278)); + .I4 (_N106091)); // LUT = (I0)|(~I1&~I2&~I3&I4) ; GTP_LUT5 /* N669_42 */ #( .INIT(32'b01011010110110100101101001011010)) N669_42 ( - .Z (_N22793), + .Z (_N22768), .I0 (default_samp_position[7]), .I1 (default_samp_position[0]), .I2 (adj_inc_dec_n), - .I3 (_N98671), - .I4 (_N105278)); + .I3 (_N101396), + .I4 (_N106091)); // LUT = (I0&~I2)|(~I0&I2)|(I1&I2&~I3&I4) ; GTP_LUT5 /* N669_74_1 */ #( .INIT(32'b11111010111110111111101011111010)) N669_74_1 ( - .Z (_N22825_inv), + .Z (_N22800_inv), .I0 (default_samp_position[7]), .I1 (default_samp_position[0]), .I2 (adj_inc_dec_n), - .I3 (_N98671), - .I4 (_N105278)); + .I3 (_N101396), + .I4 (_N106091)); // LUT = (I0)|(I2)|(~I1&~I3&I4) ; GTP_LUT1 /* \N669_79[0] */ #( @@ -133424,9 +133280,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 \N669_79[1] ( .Z (N669[1]), .I0 (N714[1]), - .I1 (_N22819), - .I2 (_N22828), - .I3 (_N22825_inv)); + .I1 (_N22794), + .I2 (_N22803), + .I3 (_N22800_inv)); // LUT = (I1&I2)|(I0&~I1&~I3) ; GTP_LUT4 /* \N669_79[2] */ #( @@ -133434,9 +133290,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 \N669_79[2] ( .Z (N669[2]), .I0 (N714[2]), - .I1 (_N22819), - .I2 (_N22829), - .I3 (_N22825_inv)); + .I1 (_N22794), + .I2 (_N22804), + .I3 (_N22800_inv)); // LUT = (I1&I2)|(I0&~I1&~I3) ; GTP_LUT4 /* \N669_79[3] */ #( @@ -133444,9 +133300,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 \N669_79[3] ( .Z (N669[3]), .I0 (N714[3]), - .I1 (_N22819), - .I2 (_N22830), - .I3 (_N22825_inv)); + .I1 (_N22794), + .I2 (_N22805), + .I3 (_N22800_inv)); // LUT = (I1&I2)|(I0&~I1&~I3) ; GTP_LUT4 /* \N669_79[4] */ #( @@ -133454,9 +133310,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 \N669_79[4] ( .Z (N669[4]), .I0 (N714[4]), - .I1 (_N22819), - .I2 (_N22831), - .I3 (_N22825_inv)); + .I1 (_N22794), + .I2 (_N22806), + .I3 (_N22800_inv)); // LUT = (I1&I2)|(I0&~I1&~I3) ; GTP_LUT4 /* \N669_79[5] */ #( @@ -133464,9 +133320,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 \N669_79[5] ( .Z (N669[5]), .I0 (N714[5]), - .I1 (_N22819), - .I2 (_N22832), - .I3 (_N22825_inv)); + .I1 (_N22794), + .I2 (_N22807), + .I3 (_N22800_inv)); // LUT = (I1&I2)|(I0&~I1&~I3) ; GTP_LUT4 /* \N669_79[6] */ #( @@ -133474,20 +133330,20 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 \N669_79[6] ( .Z (N669[6]), .I0 (N714[6]), - .I1 (_N22819), - .I2 (_N22833), - .I3 (_N22825_inv)); + .I1 (_N22794), + .I2 (_N22808), + .I3 (_N22800_inv)); // LUT = (I1&I2)|(I0&~I1&~I3) ; GTP_LUT5 /* N669_80 */ #( .INIT(32'b11111010011110101111101011111010)) N669_80 ( - .Z (_N22819), + .Z (_N22794), .I0 (default_samp_position[7]), .I1 (default_samp_position[0]), .I2 (adj_inc_dec_n), - .I3 (_N98671), - .I4 (_N105278)); + .I3 (_N101396), + .I4 (_N106091)); // LUT = (I2&~I4)|(I0&~I2)|(~I1&I2)|(~I0&I2)|(I2&I3) ; GTP_LUT4 /* N683_2 */ #( @@ -133515,7 +133371,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 GTP_LUT2 /* N701_7 */ #( .INIT(4'b1110)) N701_7 ( - .Z (_N98671), + .Z (_N101396), .I0 (default_samp_position[6]), .I1 (default_samp_position[5])); // LUT = (I0)|(I1) ; @@ -133582,14 +133438,14 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .Q (adj_inc_dec_n), .C (N0), .CLK (ddrphy_clkin), - .D (_N103358)); + .D (_N104170)); // defparam adj_inc_dec_n_vname.orig_name = adj_inc_dec_n; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqsi_rdel_cal_v1_2.vp:425 GTP_LUT5 /* adj_inc_dec_n_ce_mux */ #( .INIT(32'b00000101111111110101010000000000)) adj_inc_dec_n_ce_mux ( - .Z (_N103358), + .Z (_N104170), .I0 (init_adj_rdel), .I1 (N53), .I2 (N384), @@ -133604,14 +133460,14 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .Q (adj_rdel_done), .C (N0), .CLK (ddrphy_clkin), - .D (_N103360)); + .D (_N104172)); // defparam adj_rdel_done_vname.orig_name = adj_rdel_done; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqsi_rdel_cal_v1_2.vp:660 GTP_LUT5 /* adj_rdel_done_ce_mux */ #( .INIT(32'b11111111111000001110000011100000)) adj_rdel_done_ce_mux ( - .Z (_N103360), + .Z (_N104172), .I0 (init_adj_rdel), .I1 (reinit_adj_rdel), .I2 (adj_rdel_done), @@ -133982,19 +133838,19 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .Q (next_default_samp_position[7]), .C (N0), .CLK (ddrphy_clkin), - .D (_N103361)); + .D (_N104173)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqsi_rdel_cal_v1_2.vp:396 GTP_LUT5M /* \next_default_samp_position_ce_mux[7] */ #( .INIT(32'b00100011001000000011001000000010)) \next_default_samp_position_ce_mux[7] ( - .Z (_N103361), + .Z (_N104173), .I0 (next_default_samp_position[7]), .I1 (N633), .I2 (adj_inc_dec_n), .I3 (N716[7]), .I4 (default_samp_position[7]), - .ID (_N22748)); + .ID (_N22723)); // LUT = (~I1&I2&I3&~I4)|(ID&~I1&~I2&~I4)|(~I1&~I2&I3&I4)|(I0&~I1&I2&I4) ; GTP_DFF_C /* rdel_cal_vld */ #( @@ -134026,17 +133882,17 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .Q (rdel_calib_error), .C (N0), .CLK (ddrphy_clkin), - .D (_N103359)); + .D (_N104171)); // defparam rdel_calib_error_vname.orig_name = rdel_calib_error; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqsi_rdel_cal_v1_2.vp:650 GTP_LUT5M /* rdel_calib_error_ce_mux */ #( .INIT(32'b00100000101000000010001010101010)) rdel_calib_error_ce_mux ( - .Z (_N103359), - .I0 (_N106534), + .Z (_N104171), + .I0 (_N107352), .I1 (state_reg[0]), - .I2 (_N5568), + .I2 (_N5562), .I3 (rdel_calibration), .I4 (state_reg[11]), .ID (rdel_calib_error)); @@ -134080,18 +133936,18 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .Q (rdel_ctrl_wire[2]), .C (N0), .CLK (ddrphy_clkin), - .D (_N103357)); + .D (_N104169)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqsi_rdel_cal_v1_2.vp:564 GTP_LUT5 /* \rdel_ctrl_ce_mux[2] */ #( .INIT(32'b11101110111011101110111011100010)) \rdel_ctrl_ce_mux[2] ( - .Z (_N103357), + .Z (_N104169), .I0 (rdel_ctrl_wire[2]), .I1 (N446), .I2 (state_reg[5]), .I3 (state_reg[10]), - .I4 (_N30142)); + .I4 (_N30245)); // LUT = (I0&~I1)|(I1&I2)|(I1&I3)|(I1&I4) ; GTP_DFF_C /* rdel_move_done */ #( @@ -134152,14 +134008,14 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .Q (rdel_ov_sync), .C (N0), .CLK (ddrphy_clkin), - .D (_N103356)); + .D (_N104168)); // defparam rdel_ov_sync_vname.orig_name = rdel_ov_sync; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqsi_rdel_cal_v1_2.vp:369 GTP_LUT3 /* rdel_ov_sync_ce_mux */ #( .INIT(8'b11101000)) rdel_ov_sync_ce_mux ( - .Z (_N103356), + .Z (_N104168), .I0 (rdel_ov_d[3]), .I1 (rdel_ov_d[2]), .I2 (rdel_ov_sync)); @@ -134289,7 +134145,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 \state_fsm[3:0]_135 ( .Z (_N134), .I0 (state_reg[2]), - .I1 (_N96148)); + .I1 (_N96930)); // LUT = I0&I1 ; GTP_LUT5 /* \state_fsm[3:0]_139 */ #( @@ -134332,7 +134188,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 .I1 (cnt[3]), .I2 (state_reg[7]), .I3 (state_reg[9]), - .I4 (_N96148)); + .I4 (_N96930)); // LUT = (~I0&I1&I3)|(~I0&I2&I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqsi_rdel_cal_v1_2.vp:459 @@ -134359,7 +134215,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 GTP_LUT5 /* \state_fsm[3:0]_540_4 */ #( .INIT(32'b11111101111111101111111111111111)) \state_fsm[3:0]_540_4 ( - .Z (_N105817), + .Z (_N106639), .I0 (cnt[8]), .I1 (cnt[1]), .I2 (cnt[0]), @@ -134370,7 +134226,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 GTP_LUT4 /* \state_fsm[3:0]_542_2 */ #( .INIT(16'b1000010000100001)) \state_fsm[3:0]_542_2 ( - .Z (_N105812), + .Z (_N106634), .I0 (cnt[3]), .I1 (cnt[2]), .I2 (total_margin_div2[1]), @@ -134380,52 +134236,135 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2 GTP_LUT5 /* \state_fsm[3:0]_542_4 */ #( .INIT(32'b10000100001000010000000000000000)) \state_fsm[3:0]_542_4 ( - .Z (_N81412_3), + .Z (_N82185_3), .I0 (cnt[5]), .I1 (cnt[4]), .I2 (total_margin_div2[3]), .I3 (total_margin_div2[2]), - .I4 (_N105812)); + .I4 (_N106634)); // LUT = (~I0&~I1&~I2&~I3&I4)|(I0&~I1&I2&~I3&I4)|(~I0&I1&~I2&I3&I4)|(I0&I1&I2&I3&I4) ; GTP_LUT4 /* \state_fsm[3:0]_544 */ #( .INIT(16'b1000010000100001)) \state_fsm[3:0]_544 ( - .Z (_N81412_5), + .Z (_N82185_5), .I0 (cnt[7]), .I1 (cnt[6]), .I2 (total_margin_div2[5]), .I3 (total_margin_div2[4])); // LUT = (~I0&~I1&~I2&~I3)|(I0&~I1&I2&~I3)|(~I0&I1&~I2&I3)|(I0&I1&I2&I3) ; - GTP_LUT4 /* \state_fsm[3:0]_3383 */ #( - .INIT(16'b0000000000000010)) - \state_fsm[3:0]_3383 ( - .Z (_N96167), - .I0 (_N83332), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [0] ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [1] ), - .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [9] )); - // LUT = I0&~I1&~I2&~I3 ; + GTP_LUT4 /* \state_fsm[3:0]_3384 */ #( + .INIT(16'b1000010000100001)) + \state_fsm[3:0]_3384 ( + .Z (_N106097), + .I0 (default_samp_position[6]), + .I1 (default_samp_position[5]), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [8] ), + .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [7] )); + // LUT = (~I0&~I1&~I2&~I3)|(I0&~I1&I2&~I3)|(~I0&I1&~I2&I3)|(I0&I1&I2&I3) ; - GTP_LUT3 /* \state_fsm[3:0]_3385 */ #( - .INIT(8'b00000001)) + GTP_LUT4 /* \state_fsm[3:0]_3385 */ #( + .INIT(16'b1000010000100001)) \state_fsm[3:0]_3385 ( - .Z (_N106624), - .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [9] ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [1] ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [0] )); - // LUT = ~I0&~I1&~I2 ; + .Z (_N106098), + .I0 (default_samp_position[4]), + .I1 (default_samp_position[3]), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [6] ), + .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [5] )); + // LUT = (~I0&~I1&~I2&~I3)|(I0&~I1&I2&~I3)|(~I0&I1&~I2&I3)|(I0&I1&I2&I3) ; GTP_LUT4 /* \state_fsm[3:0]_3386 */ #( - .INIT(16'b1001000000000000)) + .INIT(16'b1000010000100001)) \state_fsm[3:0]_3386 ( - .Z (_N96160), - .I0 (default_samp_position[1]), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [3] ), - .I2 (_N83022), - .I3 (_N106624)); - // LUT = (~I0&~I1&I2&I3)|(I0&I1&I2&I3) ; + .Z (_N106099), + .I0 (default_samp_position[2]), + .I1 (default_samp_position[1]), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [4] ), + .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [3] )); + // LUT = (~I0&~I1&~I2&~I3)|(I0&~I1&I2&~I3)|(~I0&I1&~I2&I3)|(I0&I1&I2&I3) ; + + GTP_LUT5 /* \state_fsm[3:0]_3387 */ #( + .INIT(32'b00000000000000000000000000100001)) + \state_fsm[3:0]_3387 ( + .Z (_N106100), + .I0 (default_samp_position[0]), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [9] ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [2] ), + .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [1] ), + .I4 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [0] )); + // LUT = (~I0&~I1&~I2&~I3&~I4)|(I0&~I1&I2&~I3&~I4) ; + + GTP_LUT4 /* \state_fsm[3:0]_3390 */ #( + .INIT(16'b1000000000000000)) + \state_fsm[3:0]_3390 ( + .Z (_N96937), + .I0 (_N106097), + .I1 (_N106098), + .I2 (_N106099), + .I3 (_N106100)); + // LUT = I0&I1&I2&I3 ; + + GTP_LUT4 /* \state_fsm[3:0]_3393 */ #( + .INIT(16'b1000010000100001)) + \state_fsm[3:0]_3393 ( + .Z (_N106645), + .I0 (cnt[8]), + .I1 (cnt[7]), + .I2 (default_samp_position[6]), + .I3 (default_samp_position[5])); + // LUT = (~I0&~I1&~I2&~I3)|(I0&~I1&I2&~I3)|(~I0&I1&~I2&I3)|(I0&I1&I2&I3) ; + + GTP_LUT4 /* \state_fsm[3:0]_3394 */ #( + .INIT(16'b1000010000100001)) + \state_fsm[3:0]_3394 ( + .Z (_N106646), + .I0 (cnt[6]), + .I1 (cnt[5]), + .I2 (default_samp_position[4]), + .I3 (default_samp_position[3])); + // LUT = (~I0&~I1&~I2&~I3)|(I0&~I1&I2&~I3)|(~I0&I1&~I2&I3)|(I0&I1&I2&I3) ; + + GTP_LUT4 /* \state_fsm[3:0]_3395 */ #( + .INIT(16'b1000010000100001)) + \state_fsm[3:0]_3395 ( + .Z (_N106647), + .I0 (cnt[4]), + .I1 (cnt[3]), + .I2 (default_samp_position[2]), + .I3 (default_samp_position[1])); + // LUT = (~I0&~I1&~I2&~I3)|(I0&~I1&I2&~I3)|(~I0&I1&~I2&I3)|(I0&I1&I2&I3) ; + + GTP_LUT5 /* \state_fsm[3:0]_3396 */ #( + .INIT(32'b00000000000001000000000000000001)) + \state_fsm[3:0]_3396 ( + .Z (_N106648), + .I0 (cnt[9]), + .I1 (cnt[2]), + .I2 (cnt[1]), + .I3 (cnt[0]), + .I4 (default_samp_position[0])); + // LUT = (~I0&~I1&~I2&~I3&~I4)|(~I0&I1&~I2&~I3&I4) ; + + GTP_LUT4 /* \state_fsm[3:0]_3399 */ #( + .INIT(16'b1000000000000000)) + \state_fsm[3:0]_3399 ( + .Z (_N96930), + .I0 (_N106645), + .I1 (_N106646), + .I2 (_N106647), + .I3 (_N106648)); + // LUT = I0&I1&I2&I3 ; + + GTP_LUT4 /* \state_fsm[3:0]_3402 */ #( + .INIT(16'b0000000000000010)) + \state_fsm[3:0]_3402 ( + .Z (_N96942), + .I0 (_N84178), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [0] ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [1] ), + .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [9] )); + // LUT = I0&~I1&~I2&~I3 ; (* syn_encoding="onehot" *) GTP_DFF_PE /* \state_reg[0] */ #( .GRS_EN("TRUE"), @@ -134814,6 +134753,7 @@ module ipsxb_ddrphy_data_slice_v1_4 input [4:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt , input [6:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg , input [5:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg , + input [9:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt , input [3:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 , input [3:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 , input [3:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3 , @@ -134822,7 +134762,6 @@ module ipsxb_ddrphy_data_slice_v1_4 input [5:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg , input [4:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt , input [6:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg , - input [9:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt , input [3:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 , input [3:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 , input [3:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3 , @@ -134832,17 +134771,14 @@ module ipsxb_ddrphy_data_slice_v1_4 input [4:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt , input [6:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg , input [9:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt , - input [3:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_flag_tmp , input [31:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/phy_wrdata_mask , - input _N83022, - input _N83332, - input _N95825, - input _N96106, - input _N96271, - input _N96318, - input _N96883, - input _N105278, - input _N105949, + input _N84178, + input _N96676, + input _N96884, + input _N97478, + input _N97660, + input _N106091, + input _N106767, input \data_slice_dqs_gate_cal/gatecal/N1 , input \data_slice_wrlvl/N449 , input ddrphy_clkin, @@ -134857,15 +134793,14 @@ module ipsxb_ddrphy_data_slice_v1_4 input rdel_calibration, input rdel_move_en, input reinit_adj_rdel, - input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N165 , input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_gate_vld , input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r , - input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld , input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_gate_vld , input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r , - input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N165 , + input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld , input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_gate_vld , input wrlvl_ck_dly_done, + input wrlvl_ck_dly_start, input wrlvl_dqs_req, output [3:0] adj_wrdq_en, output [7:0] ck_dly_set_bin_tra, @@ -134874,7 +134809,6 @@ module ipsxb_ddrphy_data_slice_v1_4 output [3:0] \data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r2 , output [3:0] \data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r3 , output [2:0] \data_slice_dqs_gate_cal/gatecal/N22 , - output [2:0] \data_slice_dqs_gate_cal/gatecal/gate_state_next , output [5:0] \data_slice_dqs_gate_cal/gatecal/gate_state_reg , output [4:0] \data_slice_wrlvl/cnt , output [6:0] \data_slice_wrlvl/wl_state_reg , @@ -134888,19 +134822,21 @@ module ipsxb_ddrphy_data_slice_v1_4 output [3:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj , output [3:0] \wdata_path_adj/phy_wrdata_en_r2 , output [3:0] \wdata_path_adj/phy_wrdata_en_slip4 , - output _N81412_3, - output _N81412_5, - output _N96109, - output _N96110, - output _N96120, - output _N96124, - output _N96160, - output _N96167, - output _N96886, + output _N25006, + output _N82185_3, + output _N82185_5, output _N96887, - output _N105817, - output _N106288, - output _N106624, + output _N96888, + output _N96898, + output _N96900, + output _N96902, + output _N96937, + output _N96942, + output _N97080, + output _N97662, + output _N97663, + output _N104452, + output _N106639, output adj_rdel_done, output ck_check_done, output \data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r , @@ -134919,10 +134855,8 @@ module ipsxb_ddrphy_data_slice_v1_4 output rdel_calib_error, output rdel_move_done, output read_valid, - output \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N449 , output \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N11 , - output \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N449 , - output wrlvl_ck_dly_start, + output wrlvl_ck_dly_flag, output wrlvl_dqs_en, output wrlvl_dqs_resp, output wrlvl_error, @@ -134970,8 +134904,6 @@ module ipsxb_ddrphy_data_slice_v1_4 wire \data_slice_dqs_gate_cal_dqs_gate_coarse_cal/read_cmd_mux_r3[3]_floating ; wire \data_slice_dqs_gate_cal_gatecal/N22[0]_floating ; wire \data_slice_dqs_gate_cal_gatecal/N22[1]_floating ; - wire \data_slice_dqs_gate_cal_gatecal/gate_state_next[0]_floating ; - wire \data_slice_dqs_gate_cal_gatecal/gate_state_next[1]_floating ; wire \data_slice_dqs_gate_cal_gatecal/gate_state_reg[4]_floating ; wire \data_slice_dqs_gate_cal_gatecal/gate_state_reg[5]_floating ; wire \data_slice_dqs_gate_cal_read_clk_ctrl[2]_floating ; @@ -135051,7 +134983,6 @@ module ipsxb_ddrphy_data_slice_v1_4 .\dqs_gate_coarse_cal/read_cmd_mux_r3 ({\data_slice_dqs_gate_cal_dqs_gate_coarse_cal/read_cmd_mux_r3[3]_floating , \data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r3 [2] , \data_slice_dqs_gate_cal_dqs_gate_coarse_cal/read_cmd_mux_r3[1]_floating , \data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r3 [0] }), .dqs_gate_ctrl (dqs_gate_ctrl), .\gatecal/N22 ({\data_slice_dqs_gate_cal/gatecal/N22 [2] , \data_slice_dqs_gate_cal_gatecal/N22[1]_floating , \data_slice_dqs_gate_cal_gatecal/N22[0]_floating }), - .\gatecal/gate_state_next ({\data_slice_dqs_gate_cal/gatecal/gate_state_next [2] , \data_slice_dqs_gate_cal_gatecal/gate_state_next[1]_floating , \data_slice_dqs_gate_cal_gatecal/gate_state_next[0]_floating }), .\gatecal/gate_state_reg ({\data_slice_dqs_gate_cal_gatecal/gate_state_reg[5]_floating , \data_slice_dqs_gate_cal_gatecal/gate_state_reg[4]_floating , \data_slice_dqs_gate_cal/gatecal/gate_state_reg [3] , \data_slice_dqs_gate_cal/gatecal/gate_state_reg [2] , \data_slice_dqs_gate_cal/gatecal/gate_state_reg [1] , \data_slice_dqs_gate_cal/gatecal/gate_state_reg [0] }), .read_clk_ctrl ({\data_slice_dqs_gate_cal_read_clk_ctrl[2]_floating , debug_data[5], debug_data[4]}), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj ({\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj [3] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj [2] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj [1] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj [0] }), @@ -135076,16 +135007,17 @@ module ipsxb_ddrphy_data_slice_v1_4 .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4 ({\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4 [3] , 1'bx, 1'bx, 1'bx}), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src ({\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [3] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [2] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [1] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [0] }), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg ({1'bx, 1'bx, 1'bx, \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg [2] , 1'bx, 1'bx}), - ._N96109 (_N96109), - ._N96110 (_N96110), + ._N25006 (_N25006), + ._N96887 (_N96887), + ._N96888 (_N96888), .dqs_gate_vld (dqs_gate_vld), .gate_adj_done (gate_adj_done), .gate_cal_error (gate_cal_error), .gate_check_error (gate_check_error), .gate_check_pass (gate_check_pass), .\gatecal/dqs_gate_vld_r (\data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r ), - ._N95825 (_N95825), - ._N96106 (_N96106), + ._N96676 (_N96676), + ._N96884 (_N96884), .ddrphy_clkin (ddrphy_clkin), .dqs_gate_check_pass (dqs_gate_check_pass), .gate_check (gate_check), @@ -135107,39 +135039,36 @@ module ipsxb_ddrphy_data_slice_v1_4 .wrlvl_step ({debug_data[33], debug_data[32], debug_data[31], debug_data[30], debug_data[29], debug_data[28], debug_data[27], debug_data[26]}), .N484 ({\data_slice_wrlvl/N484 [4] , 1'bx, 1'bx, 1'bx, 1'bx}), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_in_dly (dq_in_dly), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt ({1'bx, \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] , 1'bx, 1'bx}), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt ({\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [4] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] , 1'bx, \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [0] }), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg ({1'bx, 1'bx, \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg [4] , 1'bx, 1'bx, 1'bx, 1'bx}), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt ({\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt [4] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] , 1'bx, \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt [0] }), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg ({1'bx, 1'bx, \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg [4] , 1'bx, 1'bx, 1'bx, 1'bx}), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt ({\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [4] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [1] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [0] }), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt ({1'bx, \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] , 1'bx, \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [0] }), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg ({1'bx, 1'bx, \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg [4] , 1'bx, 1'bx, 1'bx, 1'bx}), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_flag_tmp ({\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_flag_tmp [3] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_flag_tmp [2] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_flag_tmp [1] , 1'bx}), - ._N96120 (_N96120), - ._N96124 (_N96124), - ._N96886 (_N96886), - ._N96887 (_N96887), - ._N106288 (_N106288), + ._N96898 (_N96898), + ._N96900 (_N96900), + ._N96902 (_N96902), + ._N97080 (_N97080), + ._N97662 (_N97662), + ._N97663 (_N97663), + ._N104452 (_N104452), .ck_check_done (ck_check_done), .ddrphy_gatei (ddrphy_gatei), .dq_vld (\data_slice_wrlvl/dq_vld ), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N449 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N449 ), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N449 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N449 ), - .wrlvl_ck_dly_start (wrlvl_ck_dly_start), + .wrlvl_ck_dly_flag (wrlvl_ck_dly_flag), .wrlvl_dqs (wrlvl_dqs), .wrlvl_dqs_en (wrlvl_dqs_en), .wrlvl_dqs_resp (wrlvl_dqs_resp), .wrlvl_error (wrlvl_error), .N0 (\data_slice_dqs_gate_cal/gatecal/N1 ), .N449 (\data_slice_wrlvl/N449 ), - ._N96271 (_N96271), - ._N96318 (_N96318), - ._N96883 (_N96883), - ._N105949 (_N105949), + ._N97478 (_N97478), + ._N97660 (_N97660), + ._N106767 (_N106767), .ddrphy_clkin (ddrphy_clkin), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N165 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N165 ), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld ), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N165 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N165 ), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld ), .wrlvl_ck_dly_done (wrlvl_ck_dly_done), + .wrlvl_ck_dly_start (wrlvl_ck_dly_start), .wrlvl_dqs_req (wrlvl_dqs_req)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_v1_4.vp:521 @@ -135617,14 +135546,13 @@ module ipsxb_ddrphy_data_slice_v1_4 .rdel_ctrl_wire (rdel_ctrl), .total_margin_div2 ({\dqsi_rdel_cal/total_margin_div2 [7] , \dqsi_rdel_cal_total_margin_div2[6]_floating , \dqsi_rdel_cal_total_margin_div2[5]_floating , \dqsi_rdel_cal_total_margin_div2[4]_floating , \dqsi_rdel_cal_total_margin_div2[3]_floating , \dqsi_rdel_cal_total_margin_div2[2]_floating , \dqsi_rdel_cal_total_margin_div2[1]_floating , \dqsi_rdel_cal_total_margin_div2[0]_floating }), .dll_step (dll_step), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt ({\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [9] , 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [3] , 1'bx, \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [1] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [0] }), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt ({\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [9] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [8] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [7] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [6] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [5] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [4] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [3] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [2] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [1] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [0] }), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt ({\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [9] , 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [1] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [0] }), - ._N81412_3 (_N81412_3), - ._N81412_5 (_N81412_5), - ._N96160 (_N96160), - ._N96167 (_N96167), - ._N105817 (_N105817), - ._N106624 (_N106624), + ._N82185_3 (_N82185_3), + ._N82185_5 (_N82185_5), + ._N96937 (_N96937), + ._N96942 (_N96942), + ._N106639 (_N106639), .adj_rdel_done (adj_rdel_done), .rdel_cal_vld (rdel_cal_vld), .rdel_calib_done (rdel_calib_done), @@ -135634,9 +135562,8 @@ module ipsxb_ddrphy_data_slice_v1_4 .rdel_move_done (rdel_move_done), .N0 (\data_slice_dqs_gate_cal/gatecal/N1 ), ._N538 (\dqsi_rdel_cal/_N538 ), - ._N83022 (_N83022), - ._N83332 (_N83332), - ._N105278 (_N105278), + ._N84178 (_N84178), + ._N106091 (_N106091), .ddrphy_clkin (ddrphy_clkin), .init_adj_rdel (init_adj_rdel), .rdel_calibration (rdel_calibration), @@ -135790,21 +135717,21 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq8 wire N194_inv; wire N213; wire [4:0] N227; - wire _N5676; - wire _N23156; - wire _N23158; - wire _N23160; - wire _N23161; - wire _N23162; - wire _N23163; - wire _N23172; - wire _N23174; - wire _N23188; - wire _N23190; - wire _N23191; - wire _N95789; - wire _N96179; - wire _N103382; + wire _N5644; + wire _N23064; + wire _N23066; + wire _N23068; + wire _N23069; + wire _N23070; + wire _N23071; + wire _N23080; + wire _N23082; + wire _N23096; + wire _N23098; + wire _N23099; + wire _N96569; + wire _N97491; + wire _N104194; wire [4:0] cnt; wire [3:0] dqs_gate_pulse_src_nxt; wire [3:0] dqs_gate_pulse_src_nxt_r; @@ -135813,7 +135740,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq8 GTP_LUT3 /* N144_ac2 */ #( .INIT(8'b10000000)) N144_ac2 ( - .Z (_N5676), + .Z (_N5644), .I0 (cnt[2]), .I1 (cnt[1]), .I2 (cnt[0])); @@ -135832,7 +135759,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq8 GTP_LUT5 /* N205_1_5 */ #( .INIT(32'b00000000000000000000010000000000)) N205_1_5 ( - .Z (_N95789), + .Z (_N96569), .I0 (cnt[4]), .I1 (cnt[3]), .I2 (cnt[2]), @@ -135847,7 +135774,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq8 .I0 (gatecal_start), .I1 (rddata_cal), .I2 (N194_inv), - .I3 (_N95789)); + .I3 (_N96569)); // LUT = (I2)|(I3)|(~I0&~I1) ; GTP_LUT5 /* \N227[0]_1 */ #( @@ -135858,7 +135785,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq8 .I1 (rddata_cal), .I2 (cnt[0]), .I3 (N194_inv), - .I4 (_N95789)); + .I4 (_N96569)); // LUT = (I0&~I2&~I3&~I4)|(I1&~I2&~I3&~I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3.vp:346 @@ -135899,7 +135826,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq8 .INIT(16'b0000000001101100)) \N227[4]_1 ( .Z (N227[4]), - .I0 (_N5676), + .I0 (_N5644), .I1 (cnt[4]), .I2 (cnt[3]), .I3 (N213)); @@ -135912,7 +135839,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq8 .Z (dqs_gate_pulse_src_nxt[2]), .I0 (read_en_slipped[3]), .I1 (read_en_slipped[2]), - .I2 (_N96179)); + .I2 (_N97491)); // LUT = I0&~I1&~I2 ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3.vp:255 @@ -135922,7 +135849,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq8 .Z (dqs_gate_pulse_src[3]), .I0 (read_en_slipped[3]), .I1 (read_en_slipped[2]), - .I2 (_N96179)); + .I2 (_N97491)); // LUT = (I0)|(I1)|(I2) ; GTP_LUT4 /* N261_inv */ #( @@ -135932,7 +135859,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq8 .I0 (read_en_slipped[3]), .I1 (read_en_slipped[2]), .I2 (read_en_slipped[0]), - .I3 (_N96179)); + .I3 (_N97491)); // LUT = (I0&~I2)|(I1&~I2)|(~I2&I3) ; GTP_DFF_C /* \cnt[0] */ #( @@ -136168,17 +136095,17 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq8 \dqs_gate_pulse_src_4[1] ( .Z (dqs_gate_pulse_src[1]), .I0 (dqs_gate_pulse_src_nxt_r[1]), - .I1 (_N96179)); + .I1 (_N97491)); // LUT = (I0)|(I1) ; GTP_LUT4 /* \dqs_gate_pulse_src_4[1]_1 */ #( .INIT(16'b1111110111101100)) \dqs_gate_pulse_src_4[1]_1 ( - .Z (_N96179), + .Z (_N97491), .I0 (coarse_slip_step[1]), .I1 (read_en_slipped[0]), - .I2 (_N23161), - .I3 (_N23163)); + .I2 (_N23069), + .I3 (_N23071)); // LUT = (I1)|(~I0&I3)|(I0&I2) ; GTP_LUT3 /* \dqs_gate_pulse_src_4[2]_3 */ #( @@ -136187,7 +136114,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq8 .Z (dqs_gate_pulse_src[2]), .I0 (dqs_gate_pulse_src_nxt_r[2]), .I1 (read_en_slipped[2]), - .I2 (_N96179)); + .I2 (_N97491)); // LUT = (I0)|(I1)|(I2) ; GTP_LUT3 /* dqs_gate_pulse_src_nxt_4 */ #( @@ -136196,7 +136123,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq8 .Z (dqs_gate_pulse_src_nxt[1]), .I0 (read_en_slipped[3]), .I1 (read_en_slipped[2]), - .I2 (_N96179)); + .I2 (_N97491)); // LUT = (I0&~I2)|(I1&~I2) ; GTP_DFF_C /* \dqs_gate_pulse_src_nxt_r[0] */ #( @@ -136236,25 +136163,25 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq8 .Q (dqs_gate_vld), .C (N1), .CLK (ddrphy_clkin), - .D (_N103382)); + .D (_N104194)); // defparam dqs_gate_vld_vname.orig_name = dqs_gate_vld; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3.vp:346 GTP_LUT5 /* dqs_gate_vld_ce_mux */ #( .INIT(32'b11101110000000001110111011100000)) dqs_gate_vld_ce_mux ( - .Z (_N103382), + .Z (_N104194), .I0 (gatecal_start), .I1 (rddata_cal), .I2 (dqs_gate_vld), .I3 (N194_inv), - .I4 (_N95789)); + .I4 (_N96569)); // LUT = (I0&I3)|(I1&I3)|(I0&I2&~I4)|(I1&I2&~I4) ; GTP_LUT4 /* \read_en_slipped_5[0] */ #( .INIT(16'b0011001000010000)) \read_en_slipped_5[0] ( - .Z (_N23156), + .Z (_N23064), .I0 (coarse_slip_step[3]), .I1 (coarse_slip_step[0]), .I2 (read_cmd_mux_r1[2]), @@ -136264,7 +136191,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq8 GTP_LUT4 /* \read_en_slipped_5[2]_1 */ #( .INIT(16'b0011001000010000)) \read_en_slipped_5[2]_1 ( - .Z (_N23158), + .Z (_N23066), .I0 (coarse_slip_step[3]), .I1 (coarse_slip_step[0]), .I2 (read_cmd_mux[0]), @@ -136274,11 +136201,11 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq8 GTP_LUT5M /* \read_en_slipped_6[0] */ #( .INIT(32'b10111011100010000111001101000000)) \read_en_slipped_6[0] ( - .Z (_N23160), + .Z (_N23068), .I0 (read_cmd_mux[0]), .I1 (coarse_slip_step[2]), .I2 (read_cmd_mux_r2[2]), - .I3 (_N23156), + .I3 (_N23064), .I4 (coarse_slip_step[3]), .ID (coarse_slip_step[0])); // LUT = (~ID&I1&I2&~I4)|(I0&I1&I4)|(~I1&I3) ; @@ -136286,7 +136213,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq8 GTP_LUT5M /* \read_en_slipped_6[1] */ #( .INIT(32'b00100010000000001110001000000000)) \read_en_slipped_6[1] ( - .Z (_N23161), + .Z (_N23069), .I0 (read_cmd_mux_r3[2]), .I1 (coarse_slip_step[2]), .I2 (read_cmd_mux_r2[2]), @@ -136298,19 +136225,19 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq8 GTP_LUT5M /* \read_en_slipped_6[2] */ #( .INIT(32'b10001000110110001010101010101010)) \read_en_slipped_6[2] ( - .Z (_N23162), + .Z (_N23070), .I0 (coarse_slip_step[3]), .I1 (read_cmd_mux[2]), .I2 (read_cmd_mux_r1[0]), .I3 (coarse_slip_step[0]), .I4 (coarse_slip_step[2]), - .ID (_N23158)); + .ID (_N23066)); // LUT = (ID&~I4)|(~I0&I2&~I3&I4)|(I0&I1&I4) ; GTP_LUT5M /* \read_en_slipped_6[3]_1 */ #( .INIT(32'b00100010000000001110001000000000)) \read_en_slipped_6[3]_1 ( - .Z (_N23163), + .Z (_N23071), .I0 (read_cmd_mux_r2[0]), .I1 (coarse_slip_step[2]), .I2 (read_cmd_mux_r1[0]), @@ -136322,7 +136249,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq8 GTP_LUT5 /* \read_en_slipped_9[0] */ #( .INIT(32'b10110011101000101001000110000000)) \read_en_slipped_9[0] ( - .Z (_N23172), + .Z (_N23080), .I0 (coarse_slip_step[3]), .I1 (coarse_slip_step[0]), .I2 (read_cmd_mux[0]), @@ -136333,7 +136260,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq8 GTP_LUT5 /* \read_en_slipped_9[2] */ #( .INIT(32'b10110011101000101001000110000000)) \read_en_slipped_9[2] ( - .Z (_N23174), + .Z (_N23082), .I0 (coarse_slip_step[3]), .I1 (coarse_slip_step[0]), .I2 (read_cmd_mux[2]), @@ -136344,8 +136271,8 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq8 GTP_LUT5M /* \read_en_slipped_13[0] */ #( .INIT(32'b10101010101010100000000011100100)) \read_en_slipped_13[0] ( - .Z (_N23188), - .I0 (_N23172), + .Z (_N23096), + .I0 (_N23080), .I1 (read_cmd_mux[0]), .I2 (read_cmd_mux_r2[0]), .I3 (coarse_slip_step[0]), @@ -136356,8 +136283,8 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq8 GTP_LUT5M /* \read_en_slipped_13[2] */ #( .INIT(32'b10101010101010100000000011100100)) \read_en_slipped_13[2] ( - .Z (_N23190), - .I0 (_N23174), + .Z (_N23098), + .I0 (_N23082), .I1 (read_cmd_mux[2]), .I2 (read_cmd_mux_r2[2]), .I3 (coarse_slip_step[0]), @@ -136368,7 +136295,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq8 GTP_LUT5M /* \read_en_slipped_13[3] */ #( .INIT(32'b00100010000000001110001000000000)) \read_en_slipped_13[3] ( - .Z (_N23191), + .Z (_N23099), .I0 (read_cmd_mux_r2[2]), .I1 (coarse_slip_step[2]), .I2 (read_cmd_mux_r1[2]), @@ -136379,14 +136306,14 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq8 GTP_MUX2LUT6 \read_en_slipped_14[0] ( .Z (read_en_slipped[0]), - .I0 (_N23188), - .I1 (_N23160), + .I0 (_N23096), + .I1 (_N23068), .S (coarse_slip_step[1])); GTP_MUX2LUT6 \read_en_slipped_14[2] ( .Z (read_en_slipped[2]), - .I0 (_N23190), - .I1 (_N23162), + .I0 (_N23098), + .I1 (_N23070), .S (coarse_slip_step[1])); GTP_LUT3 /* \read_en_slipped_14[3] */ #( @@ -136394,8 +136321,8 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq8 \read_en_slipped_14[3] ( .Z (read_en_slipped[3]), .I0 (coarse_slip_step[1]), - .I1 (_N23163), - .I2 (_N23191)); + .I1 (_N23071), + .I2 (_N23099)); // LUT = (~I0&I2)|(I0&I1) ; @@ -136405,10 +136332,10 @@ endmodule module ipsxb_ddrphy_gatecal_v1_3_unq8 ( input [2:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N22 , - input [2:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_next , input [5:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg , input N1, - input _N96107, + input _N25006, + input _N96885, input ddrphy_clkin, input dqs_gate_check_pass, input dqs_gate_vld, @@ -136418,7 +136345,7 @@ module ipsxb_ddrphy_gatecal_v1_3_unq8 output [3:0] coarse_slip_step, output [5:0] gate_state_reg, output [2:0] read_clk_ctrl, - output _N95825, + output _N96676, output dqs_gate_vld_r, output gate_adj_done, output gate_cal_error, @@ -136442,26 +136369,26 @@ module ipsxb_ddrphy_gatecal_v1_3_unq8 wire _N6; wire _N10; wire _N17; - wire _N17014; - wire _N17015; - wire _N17016; - wire _N17017; - wire _N17018; - wire _N22940; - wire _N22941; - wire _N22942; - wire _N22943; - wire _N22944; - wire _N23872; - wire _N23875; - wire _N23876; - wire _N23877; - wire _N82515; - wire _N95827; - wire _N96189; - wire _N103363; - wire _N103364; - wire _N103365; + wire _N13791; + wire _N13792; + wire _N13793; + wire _N13794; + wire _N13795; + wire _N22906; + wire _N22907; + wire _N22908; + wire _N22909; + wire _N22910; + wire _N23666; + wire _N23669; + wire _N23670; + wire _N23671; + wire _N83337; + wire _N96678; + wire _N96953; + wire _N104175; + wire _N104176; + wire _N104177; wire [2:0] dgts_cnt; wire dqs_gate_vld_n; wire gate_check_pass_d; @@ -136494,7 +136421,7 @@ module ipsxb_ddrphy_gatecal_v1_3_unq8 GTP_LUT5 /* \N52_6[0] */ #( .INIT(32'b01010101110000000101010111111111)) \N52_6[0] ( - .Z (_N23872), + .Z (_N23666), .I0 (gate_move_en), .I1 (gatecal_start), .I2 (N567[6]), @@ -136505,18 +136432,18 @@ module ipsxb_ddrphy_gatecal_v1_3_unq8 GTP_LUT5 /* \N52_7[0] */ #( .INIT(32'b00110011011100110000000001000000)) \N52_7[0] ( - .Z (_N23875), + .Z (_N23669), .I0 (dqs_gate_vld), .I1 (gate_state_reg[2]), .I2 (dqs_gate_vld_r), - .I3 (_N82515), - .I4 (_N23872)); + .I3 (_N83337), + .I4 (_N23666)); // LUT = (~I1&I4)|(~I0&I1&I2&~I3) ; GTP_LUT5M /* \N52_7[1] */ #( .INIT(32'b11111111000111111010101010101010)) \N52_7[1] ( - .Z (_N23876), + .Z (_N23670), .I0 (coarse_slip_step[3]), .I1 (dgts_cnt[2]), .I2 (dqs_gate_vld_r), @@ -136528,7 +136455,7 @@ module ipsxb_ddrphy_gatecal_v1_3_unq8 GTP_LUT5 /* \N52_7[2] */ #( .INIT(32'b11000000110010101100000011001111)) \N52_7[2] ( - .Z (_N23877), + .Z (_N23671), .I0 (gatecal_start), .I1 (N22[2]), .I2 (gate_state_reg[2]), @@ -136542,7 +136469,7 @@ module ipsxb_ddrphy_gatecal_v1_3_unq8 .Z (gate_state_next[2]), .I0 (gate_state_reg[1]), .I1 (gate_state_reg[0]), - .I2 (_N23877)); + .I2 (_N23671)); // LUT = ~I0&~I1&I2 ; GTP_LUT2 /* N55 */ #( @@ -136561,8 +136488,8 @@ module ipsxb_ddrphy_gatecal_v1_3_unq8 .I0 (coarse_slip_step[3]), .I1 (gate_state_reg[1]), .I2 (gate_state_reg[0]), - .I3 (_N23875), - .I4 (_N23876)); + .I3 (_N23669), + .I4 (_N23670)); // LUT = (I0&I1&~I2)|(I0&~I2&~I3&I4) ; GTP_LUT5CARRY /* N81_1_0 */ #( @@ -136572,7 +136499,7 @@ module ipsxb_ddrphy_gatecal_v1_3_unq8 .I4_TO_CARRY("FALSE"), .I4_TO_LUT("FALSE")) N81_1_0 ( - .COUT (_N17014), + .COUT (_N13791), .Z (), .CIN (), .I0 (), @@ -136592,12 +136519,12 @@ module ipsxb_ddrphy_gatecal_v1_3_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N81_1_1 ( - .COUT (_N17015), - .Z (_N22940), - .CIN (_N17014), + .COUT (_N13792), + .Z (_N22906), + .CIN (_N13791), .I0 (), .I1 (read_clk_ctrl[1]), - .I2 (_N95827), + .I2 (_N96678), .I3 (golden_value[1]), .I4 (1'b0), .ID ()); @@ -136612,12 +136539,12 @@ module ipsxb_ddrphy_gatecal_v1_3_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N81_1_2 ( - .COUT (_N17016), - .Z (_N22941), - .CIN (_N17015), + .COUT (_N13793), + .Z (_N22907), + .CIN (_N13792), .I0 (), .I1 (coarse_slip_step[0]), - .I2 (_N95827), + .I2 (_N96678), .I3 (golden_value[2]), .I4 (1'b0), .ID ()); @@ -136632,12 +136559,12 @@ module ipsxb_ddrphy_gatecal_v1_3_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N81_1_3 ( - .COUT (_N17017), - .Z (_N22942), - .CIN (_N17016), + .COUT (_N13794), + .Z (_N22908), + .CIN (_N13793), .I0 (), .I1 (coarse_slip_step[1]), - .I2 (_N95827), + .I2 (_N96678), .I3 (golden_value[3]), .I4 (1'b0), .ID ()); @@ -136652,12 +136579,12 @@ module ipsxb_ddrphy_gatecal_v1_3_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N81_1_4 ( - .COUT (_N17018), - .Z (_N22943), - .CIN (_N17017), + .COUT (_N13795), + .Z (_N22909), + .CIN (_N13794), .I0 (), .I1 (coarse_slip_step[2]), - .I2 (_N95827), + .I2 (_N96678), .I3 (golden_value[4]), .I4 (1'b0), .ID ()); @@ -136673,11 +136600,11 @@ module ipsxb_ddrphy_gatecal_v1_3_unq8 .I4_TO_LUT("FALSE")) N81_1_5 ( .COUT (), - .Z (_N22944), - .CIN (_N17018), + .Z (_N22910), + .CIN (_N13795), .I0 (), .I1 (coarse_slip_step[3]), - .I2 (_N95827), + .I2 (_N96678), .I3 (golden_value[5]), .I4 (1'b0), .ID ()); @@ -136693,7 +136620,7 @@ module ipsxb_ddrphy_gatecal_v1_3_unq8 .I1 (gate_win_size[1]), .I2 (gate_win_size[0]), .I3 (gate_state_next[2]), - .I4 (_N23875)); + .I4 (_N23669)); // defparam N139_vname.orig_name = N139; // LUT = (I0&I3&~I4)|(I1&I2&I3&~I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_gatecal_v1_3.vp:543 @@ -136732,8 +136659,8 @@ module ipsxb_ddrphy_gatecal_v1_3_unq8 .I0 (gatecal_start), .I1 (gate_state_reg[1]), .I2 (gate_state_reg[0]), - .I3 (_N23875), - .I4 (_N96189)); + .I3 (_N23669), + .I4 (_N96953)); // defparam N301_vname.orig_name = N301; // LUT = (~I2&~I3&I4)|(I1&~I2&I4)|(~I0&I2&I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_gatecal_v1_3.vp:410 @@ -136741,7 +136668,7 @@ module ipsxb_ddrphy_gatecal_v1_3_unq8 GTP_LUT5M /* N301_1 */ #( .INIT(32'b00000000111100100000000011110001)) N301_1 ( - .Z (_N96189), + .Z (_N96953), .I0 (N22[2]), .I1 (gate_state_reg[1]), .I2 (gate_state_reg[0]), @@ -136755,30 +136682,30 @@ module ipsxb_ddrphy_gatecal_v1_3_unq8 N327_vname ( .Z (N327), .I0 (gate_move_en), - .I1 (_N96189)); + .I1 (_N96953)); // defparam N327_vname.orig_name = N327; // LUT = (I0)|(I1) ; GTP_LUT5M /* N328_7 */ #( - .INIT(32'b00000000111100100000000011110001)) + .INIT(32'b11001100110011101100110011001101)) N328_7 ( - .Z (_N95825), + .Z (_N96676), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N22 [2] ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg [1] ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg [0] ), - .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_next [2] ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg [0] ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg [1] ), + .I3 (_N25006), .I4 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg [2] ), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg [3] )); - // LUT = (~ID&~I1&~I3&~I4)|(I0&~I1&~I3&I4)|(I2&~I3) ; + // LUT = (~ID&~I2&~I3&~I4)|(I0&~I2&~I3&I4)|(I1) ; GTP_LUT5M /* N328_10 */ #( .INIT(32'b01000100110011001000110011001100)) N328_10 ( - .Z (_N95827), + .Z (_N96678), .I0 (gatecal_start), .I1 (gate_move_en), - .I2 (_N23875), - .I3 (_N96189), + .I2 (_N23669), + .I3 (_N96953), .I4 (gate_state_reg[0]), .ID (gate_state_reg[1])); // LUT = (I1&~I2&~I4)|(ID&I1&~I4)|(~I0&I1&I4)|(I1&~I3) ; @@ -136791,7 +136718,7 @@ module ipsxb_ddrphy_gatecal_v1_3_unq8 .I1 (gate_move_en), .I2 (golden_value[0]), .I3 (N301), - .I4 (_N95827)); + .I4 (_N96678)); // LUT = (~I0&I4)|(~I1&I2&I3&~I4) ; GTP_LUT4 /* \N328_17[1]_1 */ #( @@ -136800,8 +136727,8 @@ module ipsxb_ddrphy_gatecal_v1_3_unq8 .Z (N328[1]), .I0 (gate_move_en), .I1 (N301), - .I2 (_N22940), - .I3 (_N95827)); + .I2 (_N22906), + .I3 (_N96678)); // LUT = (I2&I3)|(~I0&I1&I2) ; GTP_LUT4 /* \N328_17[2]_1 */ #( @@ -136810,8 +136737,8 @@ module ipsxb_ddrphy_gatecal_v1_3_unq8 .Z (N328[2]), .I0 (gate_move_en), .I1 (N301), - .I2 (_N22941), - .I3 (_N95827)); + .I2 (_N22907), + .I3 (_N96678)); // LUT = (I2&I3)|(~I0&I1&I2) ; GTP_LUT4 /* \N328_17[3]_1 */ #( @@ -136820,8 +136747,8 @@ module ipsxb_ddrphy_gatecal_v1_3_unq8 .Z (N328[3]), .I0 (gate_move_en), .I1 (N301), - .I2 (_N22942), - .I3 (_N95827)); + .I2 (_N22908), + .I3 (_N96678)); // LUT = (I2&I3)|(~I0&I1&I2) ; GTP_LUT4 /* \N328_17[4]_1 */ #( @@ -136830,8 +136757,8 @@ module ipsxb_ddrphy_gatecal_v1_3_unq8 .Z (N328[4]), .I0 (gate_move_en), .I1 (N301), - .I2 (_N22943), - .I3 (_N95827)); + .I2 (_N22909), + .I3 (_N96678)); // LUT = (I2&I3)|(~I0&I1&I2) ; GTP_LUT4 /* \N328_17[5]_1 */ #( @@ -136840,8 +136767,8 @@ module ipsxb_ddrphy_gatecal_v1_3_unq8 .Z (N328[5]), .I0 (gate_move_en), .I1 (N301), - .I2 (_N22944), - .I3 (_N95827)); + .I2 (_N22910), + .I3 (_N96678)); // LUT = (I2&I3)|(~I0&I1&I2) ; GTP_LUT1 /* N389_4_inv */ #( @@ -137036,14 +136963,14 @@ module ipsxb_ddrphy_gatecal_v1_3_unq8 .Q (gate_adj_done), .C (N1), .CLK (ddrphy_clkin), - .D (_N103364)); + .D (_N104176)); // defparam gate_adj_done_vname.orig_name = gate_adj_done; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_gatecal_v1_3.vp:406 GTP_LUT5 /* gate_adj_done_ce_mux */ #( .INIT(32'b00000000010001010000000001000100)) gate_adj_done_ce_mux ( - .Z (_N103364), + .Z (_N104176), .I0 (gate_move_en), .I1 (gate_adj_done), .I2 (dqs_gate_vld), @@ -137058,17 +136985,17 @@ module ipsxb_ddrphy_gatecal_v1_3_unq8 .Q (gate_cal_error), .C (N1), .CLK (ddrphy_clkin), - .D (_N103363)); + .D (_N104175)); // defparam gate_cal_error_vname.orig_name = gate_cal_error; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_gatecal_v1_3.vp:416 GTP_LUT3 /* gate_cal_error_ce_mux */ #( .INIT(8'b11101010)) gate_cal_error_ce_mux ( - .Z (_N103363), + .Z (_N104175), .I0 (gate_cal_error), .I1 (gate_state_next[2]), - .I2 (_N23875)); + .I2 (_N23669)); // LUT = (I0)|(I1&I2) ; GTP_DFF_C /* gate_check_error */ #( @@ -137089,18 +137016,18 @@ module ipsxb_ddrphy_gatecal_v1_3_unq8 .Q (gate_check_pass), .C (N1), .CLK (ddrphy_clkin), - .D (_N103365)); + .D (_N104177)); // defparam gate_check_pass_vname.orig_name = gate_check_pass; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_gatecal_v1_3.vp:620 GTP_LUT4 /* gate_check_pass_ce_mux */ #( .INIT(16'b1100101011001110)) gate_check_pass_ce_mux ( - .Z (_N103365), + .Z (_N104177), .I0 (gate_check_pass), .I1 (gate_state_next[2]), .I2 (N301), - .I3 (_N23875)); + .I3 (_N23669)); // LUT = (I1&~I3)|(I0&~I2)|(I1&I2) ; GTP_DFF_C /* gate_check_pass_d */ #( @@ -137152,7 +137079,7 @@ module ipsxb_ddrphy_gatecal_v1_3_unq8 .I1 (gate_move_en), .I2 (dgts_cnt[2]), .I3 (gate_state_reg[3]), - .I4 (_N96107)); + .I4 (_N96885)); // LUT = (~I1&I3)|(~I0&~I2&I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_gatecal_v1_3.vp:336 @@ -137163,15 +137090,15 @@ module ipsxb_ddrphy_gatecal_v1_3_unq8 .I0 (gatecal_start), .I1 (N567[6]), .I2 (gate_state_reg[4]), - .I3 (_N82515), - .I4 (_N96107)); + .I3 (_N83337), + .I4 (_N96885)); // LUT = (I3&I4)|(I0&~I1&I2) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_gatecal_v1_3.vp:336 GTP_LUT4 /* \gate_state_fsm[2:0]_36 */ #( .INIT(16'b1110110011001100)) \gate_state_fsm[2:0]_36 ( - .Z (_N82515), + .Z (_N83337), .I0 (coarse_slip_step[3]), .I1 (dgts_cnt[2]), .I2 (dgts_cnt[1]), @@ -137471,9 +137398,9 @@ module ipsxb_ddrphy_data_slice_dqs_gate_cal_v1_3_unq8 input [3:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r2 , input [3:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r3 , input [2:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N22 , - input [2:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_next , input [5:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg , - input _N96107, + input _N25006, + input _N96885, input ddrphy_clkin, input dqs_gate_check_pass, input gate_check, @@ -137489,7 +137416,7 @@ module ipsxb_ddrphy_data_slice_dqs_gate_cal_v1_3_unq8 output [3:0] dqs_gate_ctrl, output [5:0] \gatecal/gate_state_reg , output [2:0] read_clk_ctrl, - output _N95825, + output _N96676, output dqs_gate_vld, output gate_adj_done, output gate_cal_error, @@ -137533,16 +137460,16 @@ module ipsxb_ddrphy_data_slice_dqs_gate_cal_v1_3_unq8 .gate_state_reg ({\gatecal_gate_state_reg[5]_floating , \gatecal_gate_state_reg[4]_floating , \gatecal_gate_state_reg[3]_floating , \gatecal/gate_state_reg [2] , \gatecal_gate_state_reg[1]_floating , \gatecal_gate_state_reg[0]_floating }), .read_clk_ctrl ({\gatecal_read_clk_ctrl[2]_floating , read_clk_ctrl[1], read_clk_ctrl[0]}), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N22 ({\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N22 [2] , 1'bx, 1'bx}), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_next ({\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_next [2] , 1'bx, 1'bx}), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg ({1'bx, 1'bx, \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg [3] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg [2] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg [1] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg [0] }), - ._N95825 (_N95825), + ._N96676 (_N96676), .dqs_gate_vld_r (\gatecal/dqs_gate_vld_r ), .gate_adj_done (gate_adj_done), .gate_cal_error (gate_cal_error), .gate_check_error (gate_check_error), .gate_check_pass (gate_check_pass), .N1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/N0 ), - ._N96107 (_N96107), + ._N25006 (_N25006), + ._N96885 (_N96885), .ddrphy_clkin (ddrphy_clkin), .dqs_gate_check_pass (dqs_gate_check_pass), .dqs_gate_vld (dqs_gate_vld), @@ -137558,44 +137485,45 @@ endmodule module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 ( input [4:0] N484, + input [4:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt , + input [6:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg , input [7:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_in_dly , - input [4:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt , + input [4:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt , + input [6:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg , + input [3:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_flag_tmp , input N0, - input N449, - input _N96124, - input _N96272, - input _N96318, - input _N96884, - input _N96886, - input _N106218, + input _N96898, + input _N96900, + input _N97660, + input _N97662, + input _N107042, input ddrphy_clkin, - input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld , - input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/wrlvl_dqs_en , + input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld , + input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wrlvl_dqs_en , input wrlvl_ck_dly_done, - input wrlvl_ck_dly_start, input wrlvl_dqs_req, output [4:0] cnt, + output [4:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484 , output [7:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/adj_wrdqs , - output [4:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N484 , output [6:0] wl_state_reg, output [7:0] wrlvl_step, - output N165, - output _N106303, + output _N97478, + output _N97672, output ck_check_done, output ddrphy_gatei, output dq_vld, - output \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N449 , - output wrlvl_ck_dly_flag, + output \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N449 , + output wrlvl_ck_dly_start, output wrlvl_dqs, output wrlvl_dqs_en, output wrlvl_dqs_resp, output wrlvl_error ); - wire N14; wire N56; wire N63; wire N136; wire [7:0] N141; + wire N165; wire N173; wire N228; wire N279; @@ -137612,6 +137540,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 wire [2:0] N417; wire N439; wire [7:0] N440; + wire N449; wire [5:0] N450; wire N466; wire N475; @@ -137622,48 +137551,50 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 wire _N12; wire _N15; wire _N22; - wire _N5611; + wire _N5601; + wire _N14668; + wire _N14669; + wire _N14670; + wire _N14671; + wire _N14672; + wire _N14673; + wire _N14705; + wire _N14706; + wire _N14707; + wire _N14708; wire _N14709; wire _N14710; - wire _N14711; - wire _N14712; - wire _N14713; - wire _N14714; - wire _N15009; - wire _N15010; - wire _N15011; - wire _N15012; - wire _N15013; - wire _N15014; - wire _N16023; - wire _N16024; - wire _N16025; - wire _N16026; - wire _N16027; - wire _N16028; - wire _N16029; - wire _N23001; - wire _N63901; - wire _N63902; - wire _N63997; - wire _N64153; - wire _N64186; - wire _N103368; - wire _N103369; - wire _N103370; - wire _N103371; - wire _N103372; - wire _N103373; - wire _N103374; - wire _N106180; - wire _N106181; - wire _N106189; - wire _N106200; - wire _N106201; - wire _N106207; - wire _N106215; - wire _N106229; - wire _N106246; + wire _N15525; + wire _N15526; + wire _N15527; + wire _N15528; + wire _N15529; + wire _N15530; + wire _N15531; + wire _N22935; + wire _N64257; + wire _N64884; + wire _N64885; + wire _N65016; + wire _N65071; + wire _N65170; + wire _N104180; + wire _N104181; + wire _N104182; + wire _N104183; + wire _N104184; + wire _N104185; + wire _N104186; + wire _N107000; + wire _N107001; + wire _N107009; + wire _N107020; + wire _N107021; + wire _N107024; + wire _N107029; + wire _N107037; + wire _N107055; + wire _N107072; wire [7:0] ck_dly_step; wire dq_rising; wire [7:0] step_cnt; @@ -137671,60 +137602,52 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 wire wl_done_flag; wire [2:0] wl_next_state; wire [5:0] wrlvl_ck_check_seq; + wire wrlvl_ck_dly_flag; wire wrlvl_ck_dly_pass; wire [2:0] wrlvl_dq_r; wire [3:0] wrlvl_dq_seq; - GTP_LUT2 /* N14 */ #( - .INIT(4'b1110)) - N14_vname ( - .Z (N14), - .I0 (N279), - .I1 (N286)); - // defparam N14_vname.orig_name = N14; - // LUT = (I0)|(I1) ; - // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:309 - - GTP_LUT3 /* \N53_4_or[0]_1 */ #( - .INIT(8'b11111000)) + GTP_LUT4 /* \N53_4_or[0]_1 */ #( + .INIT(16'b1111111111100000)) \N53_4_or[0]_1 ( .Z (_N15), - .I0 (N14), - .I1 (wl_state_reg[1]), - .I2 (wl_state_reg[5])); - // LUT = (I2)|(I0&I1) ; + .I0 (N279), + .I1 (N286), + .I2 (wl_state_reg[1]), + .I3 (wl_state_reg[5])); + // LUT = (I3)|(I0&I2)|(I1&I2) ; - GTP_LUT5 /* \N53_4_or[0]_5 */ #( - .INIT(32'b11111111111111111111111111111000)) + GTP_LUT4 /* \N53_4_or[0]_5 */ #( + .INIT(16'b1111111111111000)) \N53_4_or[0]_5 ( .Z (wl_next_state[0]), - .I0 (N14), - .I1 (wl_state_reg[1]), - .I2 (wl_state_reg[5]), - .I3 (_N6), - .I4 (_N10)); - // LUT = (I2)|(I3)|(I4)|(I0&I1) ; + .I0 (cnt[4]), + .I1 (wl_state_reg[2]), + .I2 (_N6), + .I3 (_N15)); + // LUT = (I2)|(I3)|(I0&I1) ; - GTP_LUT4 /* \N53_4_or[1]_3 */ #( - .INIT(16'b1111111111110100)) + GTP_LUT5 /* \N53_4_or[1]_3 */ #( + .INIT(32'b11111111111111111111111100010000)) \N53_4_or[1]_3 ( .Z (wl_next_state[1]), - .I0 (N14), - .I1 (wl_state_reg[1]), - .I2 (wl_state_reg[2]), - .I3 (_N22)); - // LUT = (I2)|(I3)|(~I0&I1) ; + .I0 (N279), + .I1 (N286), + .I2 (wl_state_reg[1]), + .I3 (wl_state_reg[2]), + .I4 (_N22)); + // LUT = (I3)|(I4)|(~I0&~I1&I2) ; GTP_LUT5 /* \N53_4_or[2]_3 */ #( - .INIT(32'b11111111111111111111111111111000)) + .INIT(32'b11111111111111111111111111011100)) \N53_4_or[2]_3 ( .Z (wl_next_state[2]), - .I0 (N14), - .I1 (wl_state_reg[1]), - .I2 (wl_state_reg[5]), - .I3 (_N12), + .I0 (N484[4]), + .I1 (wl_state_reg[3]), + .I2 (wl_state_reg[4]), + .I3 (_N15), .I4 (_N22)); - // LUT = (I2)|(I3)|(I4)|(I0&I1) ; + // LUT = (I1)|(I3)|(I4)|(~I0&I2) ; GTP_LUT3 /* N53_5 */ #( .INIT(8'b11011100)) @@ -137754,14 +137677,13 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 // LUT = ~I0&I1 ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:364 - GTP_LUT3 /* N66_ac2 */ #( - .INIT(8'b10000000)) - N66_ac2 ( - .Z (_N5611), - .I0 (cnt[2]), - .I1 (cnt[1]), - .I2 (cnt[0])); - // LUT = I0&I1&I2 ; + GTP_LUT2 /* N66_ac1 */ #( + .INIT(4'b1000)) + N66_ac1 ( + .Z (_N5601), + .I0 (cnt[1]), + .I1 (cnt[0])); + // LUT = I0&I1 ; GTP_LUT5CARRY /* N102_1_0 */ #( .INIT(32'b11001100110011000000000000000000), @@ -137770,7 +137692,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 .I4_TO_CARRY("FALSE"), .I4_TO_LUT("FALSE")) N102_1_0 ( - .COUT (_N16023), + .COUT (_N15525), .Z (), .CIN (), .I0 (), @@ -137790,9 +137712,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N102_1_1 ( - .COUT (_N16024), + .COUT (_N15526), .Z (N378[1]), - .CIN (_N16023), + .CIN (_N15525), .I0 (), .I1 (step_cnt[1]), .I2 (wrlvl_ck_dly_start), @@ -137810,9 +137732,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N102_1_2 ( - .COUT (_N16025), + .COUT (_N15527), .Z (N378[2]), - .CIN (_N16024), + .CIN (_N15526), .I0 (), .I1 (step_cnt[2]), .I2 (wrlvl_ck_dly_start), @@ -137830,9 +137752,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N102_1_3 ( - .COUT (_N16026), + .COUT (_N15528), .Z (N378[3]), - .CIN (_N16025), + .CIN (_N15527), .I0 (), .I1 (step_cnt[3]), .I2 (wrlvl_ck_dly_start), @@ -137850,9 +137772,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N102_1_4 ( - .COUT (_N16027), + .COUT (_N15529), .Z (N378[4]), - .CIN (_N16026), + .CIN (_N15528), .I0 (), .I1 (step_cnt[4]), .I2 (wrlvl_ck_dly_start), @@ -137870,9 +137792,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N102_1_5 ( - .COUT (_N16028), + .COUT (_N15530), .Z (N378[5]), - .CIN (_N16027), + .CIN (_N15529), .I0 (), .I1 (step_cnt[5]), .I2 (wrlvl_ck_dly_start), @@ -137890,9 +137812,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N102_1_6 ( - .COUT (_N16029), + .COUT (_N15531), .Z (N378[6]), - .CIN (_N16028), + .CIN (_N15530), .I0 (), .I1 (step_cnt[6]), .I2 (wrlvl_ck_dly_start), @@ -137912,7 +137834,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 N102_1_7 ( .COUT (), .Z (N378[7]), - .CIN (_N16029), + .CIN (_N15531), .I0 (), .I1 (step_cnt[7]), .I2 (wrlvl_ck_dly_start), @@ -137930,7 +137852,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_1 ( - .COUT (_N14709), + .COUT (_N14668), .Z (N387[1]), .CIN (), .I0 (ck_dly_step[0]), @@ -137950,9 +137872,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_2 ( - .COUT (_N14710), + .COUT (_N14669), .Z (N387[2]), - .CIN (_N14709), + .CIN (_N14668), .I0 (ck_dly_step[0]), .I1 (ck_dly_step[1]), .I2 (N296), @@ -137970,9 +137892,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_3 ( - .COUT (_N14711), + .COUT (_N14670), .Z (N387[3]), - .CIN (_N14710), + .CIN (_N14669), .I0 (), .I1 (ck_dly_step[3]), .I2 (N296), @@ -137990,9 +137912,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_4 ( - .COUT (_N14712), + .COUT (_N14671), .Z (N387[4]), - .CIN (_N14711), + .CIN (_N14670), .I0 (), .I1 (ck_dly_step[4]), .I2 (N296), @@ -138010,9 +137932,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_5 ( - .COUT (_N14713), + .COUT (_N14672), .Z (N387[5]), - .CIN (_N14712), + .CIN (_N14671), .I0 (), .I1 (ck_dly_step[5]), .I2 (N296), @@ -138030,9 +137952,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_6 ( - .COUT (_N14714), + .COUT (_N14673), .Z (N387[6]), - .CIN (_N14713), + .CIN (_N14672), .I0 (), .I1 (ck_dly_step[6]), .I2 (N296), @@ -138052,7 +137974,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 N104_1_7 ( .COUT (), .Z (N387[7]), - .CIN (_N14714), + .CIN (_N14673), .I0 (), .I1 (ck_dly_step[7]), .I2 (N296), @@ -138063,29 +137985,21 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 // CARRY = (I1) ? CIN : (I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:407 - GTP_LUT2 /* N124_2 */ #( - .INIT(4'b1000)) - N124_2 ( - .Z (_N106303), - .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt [1] ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt [0] )); - // LUT = I0&I1 ; - - GTP_LUT5 /* N124_4 */ #( + GTP_LUT5 /* N124_5 */ #( .INIT(32'b10000000000000000000000000000000)) - N124_4 ( - .Z (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N484 [4] ), - .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt [4] ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] ), - .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt [1] ), - .I4 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt [0] )); + N124_5 ( + .Z (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484 [4] ), + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [4] ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] ), + .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [1] ), + .I4 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [0] )); // LUT = I0&I1&I2&I3&I4 ; - GTP_LUT5 /* N124_8 */ #( + GTP_LUT5 /* N124_7 */ #( .INIT(32'b00000000000000000000010000000000)) - N124_8 ( - .Z (_N106246), + N124_7 ( + .Z (_N107072), .I0 (cnt[4]), .I1 (cnt[3]), .I2 (cnt[2]), @@ -138093,15 +138007,26 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 .I4 (cnt[0])); // LUT = ~I0&I1&~I2&I3&~I4 ; - GTP_LUT4 /* N136_4 */ #( - .INIT(16'b0100000000000000)) - N136_4 ( + GTP_LUT4 /* N136_1 */ #( + .INIT(16'b0000000100000000)) + N136_1 ( + .Z (_N97672), + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [0] ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [1] ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [4] ), + .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg [4] )); + // LUT = ~I0&~I1&~I2&I3 ; + + GTP_LUT5 /* N136_7 */ #( + .INIT(32'b00000100000000000000000000000000)) + N136_7 ( .Z (N136), .I0 (cnt[3]), .I1 (cnt[2]), - .I2 (wl_state_reg[2]), - .I3 (_N96318)); - // LUT = ~I0&I1&I2&I3 ; + .I2 (cnt[1]), + .I3 (wl_state_reg[2]), + .I4 (_N96900)); + // LUT = ~I0&I1&~I2&I3&I4 ; GTP_LUT2 /* \N141[0]_1 */ #( .INIT(4'b0100)) @@ -138175,6 +138100,15 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 // LUT = ~I0&I1 ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:446 + GTP_LUT3 /* N151_2 */ #( + .INIT(8'b00100000)) + N151_2 ( + .Z (_N107024), + .I0 (cnt[3]), + .I1 (cnt[2]), + .I2 (wl_state_reg[4])); + // LUT = I0&~I1&I2 ; + GTP_LUT2 /* N165 */ #( .INIT(4'b1000)) N165_vname ( @@ -138188,7 +138122,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 GTP_LUT5 /* N173_8 */ #( .INIT(32'b00000000000000010000000000000000)) N173_8 ( - .Z (_N106215), + .Z (_N107037), .I0 (vld_init_cnt[5]), .I1 (vld_init_cnt[4]), .I2 (vld_init_cnt[3]), @@ -138204,7 +138138,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 .I1 (vld_init_cnt[6]), .I2 (vld_init_cnt[2]), .I3 (vld_init_cnt[0]), - .I4 (_N106215)); + .I4 (_N107037)); // LUT = ~I0&~I1&I2&I3&I4 ; GTP_LUT5CARRY /* N201_1_1 */ #( @@ -138214,7 +138148,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N201_1_1 ( - .COUT (_N15009), + .COUT (_N14705), .Z (N440[1]), .CIN (), .I0 (vld_init_cnt[0]), @@ -138234,9 +138168,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N201_1_2 ( - .COUT (_N15010), + .COUT (_N14706), .Z (N440[2]), - .CIN (_N15009), + .CIN (_N14705), .I0 (vld_init_cnt[0]), .I1 (vld_init_cnt[1]), .I2 (wl_state_reg[6]), @@ -138254,9 +138188,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N201_1_3 ( - .COUT (_N15011), + .COUT (_N14707), .Z (N440[3]), - .CIN (_N15010), + .CIN (_N14706), .I0 (), .I1 (vld_init_cnt[3]), .I2 (wl_state_reg[6]), @@ -138274,9 +138208,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N201_1_4 ( - .COUT (_N15012), + .COUT (_N14708), .Z (N440[4]), - .CIN (_N15011), + .CIN (_N14707), .I0 (), .I1 (vld_init_cnt[4]), .I2 (wl_state_reg[6]), @@ -138294,9 +138228,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N201_1_5 ( - .COUT (_N15013), + .COUT (_N14709), .Z (N440[5]), - .CIN (_N15012), + .CIN (_N14708), .I0 (), .I1 (vld_init_cnt[5]), .I2 (wl_state_reg[6]), @@ -138314,9 +138248,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N201_1_6 ( - .COUT (_N15014), + .COUT (_N14710), .Z (N440[6]), - .CIN (_N15013), + .CIN (_N14709), .I0 (), .I1 (vld_init_cnt[6]), .I2 (wl_state_reg[6]), @@ -138336,7 +138270,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 N201_1_7 ( .COUT (), .Z (N440[7]), - .CIN (_N15014), + .CIN (_N14710), .I0 (), .I1 (vld_init_cnt[7]), .I2 (wl_state_reg[6]), @@ -138347,21 +138281,21 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 // CARRY = (I1) ? CIN : (I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:516 - GTP_LUT5 /* N228_4 */ #( + GTP_LUT5 /* N228_9 */ #( .INIT(32'b00010000000000000000000000000000)) - N228_4 ( + N228_9 ( .Z (N228), .I0 (cnt[4]), .I1 (cnt[1]), - .I2 (dq_vld), - .I3 (wl_state_reg[4]), - .I4 (_N96272)); + .I2 (cnt[0]), + .I3 (dq_vld), + .I4 (_N97662)); // LUT = ~I0&~I1&I2&I3&I4 ; GTP_LUT5 /* N265_11 */ #( .INIT(32'b00000001000000000000000000000000)) N265_11 ( - .Z (_N106229), + .Z (_N107055), .I0 (wrlvl_dq_seq[3]), .I1 (wrlvl_dq_seq[2]), .I2 (wrlvl_dq_seq[1]), @@ -138372,7 +138306,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 GTP_LUT4 /* N279_6 */ #( .INIT(16'b1000000000000000)) N279_6 ( - .Z (_N106189), + .Z (_N107009), .I0 (step_cnt[4]), .I1 (step_cnt[3]), .I2 (step_cnt[2]), @@ -138387,13 +138321,13 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 .I1 (step_cnt[6]), .I2 (step_cnt[5]), .I3 (step_cnt[0]), - .I4 (_N106189)); + .I4 (_N107009)); // LUT = I0&I1&I2&I3&I4 ; GTP_LUT2 /* N286_9 */ #( .INIT(4'b0001)) N286_9 ( - .Z (_N106180), + .Z (_N107000), .I0 (ck_dly_step[7]), .I1 (ck_dly_step[0])); // LUT = ~I0&~I1 ; @@ -138401,7 +138335,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 GTP_LUT4 /* N286_10 */ #( .INIT(16'b0000000000000001)) N286_10 ( - .Z (_N106181), + .Z (_N107001), .I0 (ck_dly_step[5]), .I1 (ck_dly_step[4]), .I2 (ck_dly_step[2]), @@ -138416,7 +138350,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 .I1 (ck_dly_step[6]), .I2 (ck_dly_step[3]), .I3 (ck_dly_step[0]), - .I4 (_N106181)); + .I4 (_N107001)); // LUT = ~I0&I1&I2&~I3&I4 ; GTP_LUT5 /* N296 */ #( @@ -138446,7 +138380,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 GTP_LUT4 /* N334_5 */ #( .INIT(16'b0000000000000001)) N334_5 ( - .Z (_N106207), + .Z (_N107029), .I0 (wrlvl_ck_check_seq[5]), .I1 (wrlvl_ck_check_seq[2]), .I2 (wrlvl_ck_check_seq[1]), @@ -138459,7 +138393,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 .Z (N334), .I0 (wrlvl_ck_check_seq[4]), .I1 (wrlvl_ck_check_seq[3]), - .I2 (_N106207)); + .I2 (_N107029)); // LUT = ~I0&~I1&I2 ; GTP_LUT3 /* N359 */ #( @@ -138472,18 +138406,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 // defparam N359_vname.orig_name = N359; // LUT = (~I2)|(~I0)|(I1) ; - GTP_LUT2 /* \N367_1[0]_1 */ #( - .INIT(4'b0100)) - \N367_1[0]_1 ( - .Z (N367[0]), - .I0 (cnt[0]), - .I1 (N475)); - // LUT = ~I0&I1 ; - // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:360 - - GTP_LUT3 /* \N367_1[1]_1 */ #( + GTP_LUT3 /* \N367_1[1] */ #( .INIT(8'b01100000)) - \N367_1[1]_1 ( + \N367_1[1] ( .Z (N367[1]), .I0 (cnt[1]), .I1 (cnt[0]), @@ -138491,9 +138416,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 // LUT = (I0&~I1&I2)|(~I0&I1&I2) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:360 - GTP_LUT4 /* \N367_1[2]_1 */ #( + GTP_LUT4 /* \N367_1[2] */ #( .INIT(16'b0110101000000000)) - \N367_1[2]_1 ( + \N367_1[2] ( .Z (N367[2]), .I0 (cnt[2]), .I1 (cnt[1]), @@ -138502,9 +138427,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 // LUT = (I0&~I2&I3)|(I0&~I1&I3)|(~I0&I1&I2&I3) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:360 - GTP_LUT5 /* \N367_1[3]_1 */ #( + GTP_LUT5 /* \N367_1[3] */ #( .INIT(32'b01101010101010100000000000000000)) - \N367_1[3]_1 ( + \N367_1[3] ( .Z (N367[3]), .I0 (cnt[3]), .I1 (cnt[2]), @@ -138514,15 +138439,16 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 // LUT = (I0&~I3&I4)|(I0&~I2&I4)|(I0&~I1&I4)|(~I0&I1&I2&I3&I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:360 - GTP_LUT4 /* \N367_1[4]_1 */ #( - .INIT(16'b0110110000000000)) - \N367_1[4]_1 ( + GTP_LUT5 /* \N367_1[4] */ #( + .INIT(32'b01101100110011000000000000000000)) + \N367_1[4] ( .Z (N367[4]), - .I0 (_N5611), + .I0 (_N5601), .I1 (cnt[4]), .I2 (cnt[3]), - .I3 (N475)); - // LUT = (I1&~I2&I3)|(~I0&I1&I3)|(I0&~I1&I2&I3) ; + .I3 (cnt[2]), + .I4 (N475)); + // LUT = (I1&~I3&I4)|(I1&~I2&I4)|(~I0&I1&I4)|(I0&~I1&I2&I3&I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:360 GTP_LUT5M /* N377 */ #( @@ -138573,18 +138499,18 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 GTP_LUT5 /* N395_2 */ #( .INIT(32'b01010111010101010101010101010101)) N395_2 ( - .Z (_N23001), + .Z (_N22935), .I0 (wrlvl_ck_dly_start), .I1 (ck_dly_step[6]), .I2 (ck_dly_step[3]), - .I3 (_N106180), - .I4 (_N106181)); + .I3 (_N107000), + .I4 (_N107001)); // LUT = (~I0)|(~I1&~I2&I3&I4) ; GTP_LUT4 /* \N417[0]_14 */ #( .INIT(16'b1111111111111110)) \N417[0]_14 ( - .Z (_N106200), + .Z (_N107020), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_in_dly [3] ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_in_dly [2] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_in_dly [1] ), @@ -138594,7 +138520,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 GTP_LUT4 /* \N417[0]_15 */ #( .INIT(16'b1111111111111110)) \N417[0]_15 ( - .Z (_N106201), + .Z (_N107021), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_in_dly [7] ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_in_dly [6] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_in_dly [5] ), @@ -138607,8 +138533,8 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 .Z (N417[0]), .I0 (wrlvl_dqs_en), .I1 (dq_vld), - .I2 (_N106200), - .I3 (_N106201)); + .I2 (_N107020), + .I3 (_N107021)); // LUT = (~I1)|(~I0)|(I2)|(I3) ; GTP_LUT3 /* \N417[1] */ #( @@ -138632,16 +138558,16 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:473 GTP_LUT5 /* N439 */ #( - .INIT(32'b11111111100000001111111100000000)) + .INIT(32'b11111111000000011111111100000000)) N439_vname ( .Z (N439), - .I0 (cnt[3]), - .I1 (cnt[2]), - .I2 (wl_state_reg[4]), + .I0 (cnt[4]), + .I1 (cnt[1]), + .I2 (cnt[0]), .I3 (wl_state_reg[6]), - .I4 (_N96318)); + .I4 (_N97662)); // defparam N439_vname.orig_name = N439; - // LUT = (I3)|(I0&I1&I2&I4) ; + // LUT = (I3)|(~I0&~I1&~I2&I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:509 GTP_LUT2 /* \N440_1[0]_1 */ #( @@ -138729,17 +138655,27 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 // LUT = (I0)|(I1) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:545 + GTP_LUT4 /* N466_4 */ #( + .INIT(16'b1111111111111110)) + N466_4 ( + .Z (wrlvl_ck_dly_start), + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_flag_tmp [0] ), + .I1 (wrlvl_ck_dly_flag), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_flag_tmp [2] ), + .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_flag_tmp [3] )); + // LUT = (I0)|(I1)|(I2)|(I3) ; + GTP_LUT5M /* N475_1 */ #( - .INIT(32'b00000001111100010000001011110010)) + .INIT(32'b01010101010101010001010100010000)) N475_1 ( .Z (N475), - .I0 (wl_next_state[2]), - .I1 (wl_next_state[0]), - .I2 (N63), - .I3 (N484[4]), - .I4 (wl_next_state[1]), - .ID (_N12)); - // LUT = (ID&~I1&~I2&~I4)|(~I0&~I1&~I2&I4)|(I2&~I3) ; + .I0 (N484[4]), + .I1 (wl_next_state[2]), + .I2 (wl_next_state[1]), + .I3 (_N12), + .I4 (N63), + .ID (wl_next_state[0])); + // LUT = (~ID&~I2&I3&~I4)|(~ID&~I1&I2&~I4)|(~I0&I4) ; GTP_DFF_C /* ck_check_done */ #( .GRS_EN("TRUE"), @@ -138748,14 +138684,14 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 .Q (ck_check_done), .C (N0), .CLK (ddrphy_clkin), - .D (_N103373)); + .D (_N104185)); // defparam ck_check_done_vname.orig_name = ck_check_done; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:535 GTP_LUT5 /* ck_check_done_ce_mux */ #( .INIT(32'b00000000000000001110110011001100)) ck_check_done_ce_mux ( - .Z (_N103373), + .Z (_N104185), .I0 (wrlvl_ck_dly_start), .I1 (ck_check_done), .I2 (N228), @@ -138859,7 +138795,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 .C (N0), .CE (N359), .CLK (ddrphy_clkin), - .D (N367[0])); + .D (_N64257)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:360 GTP_DFF_CE /* \cnt[1] */ #( @@ -138895,6 +138831,18 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 .D (N367[3])); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:360 + GTP_LUT5M /* \cnt[4:0]_3628 */ #( + .INIT(32'b00000000111100010000000011110010)) + \cnt[4:0]_3628 ( + .Z (_N64257), + .I0 (wl_next_state[2]), + .I1 (wl_next_state[0]), + .I2 (N63), + .I3 (cnt[0]), + .I4 (wl_next_state[1]), + .ID (_N12)); + // LUT = (ID&~I1&~I3&~I4)|(~I0&~I1&~I3&I4)|(I2&~I3) ; + GTP_DFF_CE /* \cnt[4] */ #( .GRS_EN("TRUE"), .INIT(1'b0)) @@ -138913,21 +138861,21 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 .Q (ddrphy_gatei), .C (N0), .CLK (ddrphy_clkin), - .D (_N103368)); + .D (_N104180)); // defparam ddrphy_gatei_vname.orig_name = ddrphy_gatei; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:413 GTP_LUT5M /* ddrphy_gatei_ce_mux */ #( - .INIT(32'b11111101000000001111101100001000)) + .INIT(32'b11001100110010101100110001001100)) ddrphy_gatei_ce_mux ( - .Z (_N103368), - .I0 (_N106246), - .I1 (wl_next_state[0]), - .I2 (wl_next_state[2]), - .I3 (ddrphy_gatei), - .I4 (wl_next_state[1]), - .ID (_N23001)); - // LUT = (~I1&I3&~I4)|(ID&I1&~I2&~I4)|(I1&I3&I4)|(I2&I3)|(~I0&~I1&I3) ; + .Z (_N104180), + .I0 (_N22935), + .I1 (ddrphy_gatei), + .I2 (wl_next_state[1]), + .I3 (wl_next_state[2]), + .I4 (wl_next_state[0]), + .ID (_N107072)); + // LUT = (I1&~I2&~I4)|(I0&~I2&~I3&I4)|(I1&I2&I4)|(I1&I3)|(~ID&I1&I2) ; GTP_DFF_C /* dq_rising */ #( .GRS_EN("TRUE"), @@ -138936,18 +138884,18 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 .Q (dq_rising), .C (N0), .CLK (ddrphy_clkin), - .D (_N103374)); + .D (_N104186)); // defparam dq_rising_vname.orig_name = dq_rising; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:559 GTP_LUT4 /* dq_rising_ce_mux */ #( .INIT(16'b0000111000001100)) dq_rising_ce_mux ( - .Z (_N103374), + .Z (_N104186), .I0 (N228), .I1 (dq_rising), .I2 (wl_state_reg[6]), - .I3 (_N106229)); + .I3 (_N107055)); // LUT = (I1&~I2)|(I0&~I2&I3) ; GTP_DFF_C /* dq_vld */ #( @@ -138957,20 +138905,20 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 .Q (dq_vld), .C (N0), .CLK (ddrphy_clkin), - .D (_N103369)); + .D (_N104181)); // defparam dq_vld_vname.orig_name = dq_vld; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:453 GTP_LUT5 /* dq_vld_ce_mux */ #( - .INIT(32'b00000000111100100000000011110000)) + .INIT(32'b00001101000011000000110000001100)) dq_vld_ce_mux ( - .Z (_N103369), - .I0 (cnt[3]), - .I1 (cnt[2]), - .I2 (dq_vld), - .I3 (wl_state_reg[6]), - .I4 (_N96884)); - // LUT = (I2&~I3)|(I0&~I1&~I3&I4) ; + .Z (_N104181), + .I0 (cnt[1]), + .I1 (dq_vld), + .I2 (wl_state_reg[6]), + .I3 (_N96900), + .I4 (_N107024)); + // LUT = (I1&~I2)|(~I0&~I2&I3&I4) ; GTP_DFF_CE /* \step_cnt[0] */ #( .GRS_EN("TRUE"), @@ -139155,14 +139103,14 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 .Q (wl_done_flag), .C (N0), .CLK (ddrphy_clkin), - .D (_N103370)); + .D (_N104182)); // defparam wl_done_flag_vname.orig_name = wl_done_flag; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:463 GTP_LUT3 /* wl_done_flag_ce_mux */ #( .INIT(8'b01010100)) wl_done_flag_ce_mux ( - .Z (_N103370), + .Z (_N104182), .I0 (wrlvl_dqs_req), .I1 (wl_done_flag), .I2 (wl_state_reg[6])); @@ -139177,15 +139125,16 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 .I2 (wl_state_reg[6])); // LUT = (~I0&I1)|(~I0&I2) ; - GTP_LUT4 /* \wl_state_fsm[2:0]_10 */ #( - .INIT(16'b0111010100110000)) + GTP_LUT5 /* \wl_state_fsm[2:0]_10 */ #( + .INIT(32'b01010111010101010000001100000000)) \wl_state_fsm[2:0]_10 ( .Z (_N9), .I0 (cnt[4]), - .I1 (N14), - .I2 (wl_state_reg[1]), - .I3 (wl_state_reg[2])); - // LUT = (~I1&I2)|(~I0&I3) ; + .I1 (N279), + .I2 (N286), + .I3 (wl_state_reg[1]), + .I4 (wl_state_reg[2])); + // LUT = (~I0&I4)|(~I1&~I2&I3) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:287 GTP_LUT2 /* \wl_state_fsm[2:0]_11 */ #( @@ -139362,18 +139311,18 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 .Q (wrlvl_ck_dly_flag), .C (N0), .CLK (ddrphy_clkin), - .D (_N103371)); + .D (_N104183)); // defparam wrlvl_ck_dly_flag_vname.orig_name = wrlvl_ck_dly_flag; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:483 GTP_LUT5M /* wrlvl_ck_dly_flag_ce_mux */ #( .INIT(32'b11111110111111110101000001010000)) wrlvl_ck_dly_flag_ce_mux ( - .Z (_N103371), + .Z (_N104183), .I0 (wrlvl_ck_check_seq[4]), .I1 (wrlvl_ck_check_seq[3]), .I2 (wrlvl_ck_dly_flag), - .I3 (_N106207), + .I3 (_N107029), .I4 (N173), .ID (wrlvl_ck_dly_done)); // LUT = (~I3&I4)|(I2&I4)|(I1&I4)|(I0&I4)|(~ID&I2) ; @@ -139385,19 +139334,19 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 .Q (wrlvl_ck_dly_pass), .C (N0), .CLK (ddrphy_clkin), - .D (_N103372)); + .D (_N104184)); // defparam wrlvl_ck_dly_pass_vname.orig_name = wrlvl_ck_dly_pass; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:483 GTP_LUT5 /* wrlvl_ck_dly_pass_ce_mux */ #( .INIT(32'b11111111000100001111111100000000)) wrlvl_ck_dly_pass_ce_mux ( - .Z (_N103372), + .Z (_N104184), .I0 (wrlvl_ck_check_seq[4]), .I1 (wrlvl_ck_check_seq[3]), .I2 (N173), .I3 (wrlvl_ck_dly_pass), - .I4 (_N106207)); + .I4 (_N107029)); // LUT = (I3)|(~I0&~I1&I2&I4) ; GTP_DFF_P /* \wrlvl_dq_r[0] */ #( @@ -139437,7 +139386,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 .Q (wrlvl_dq_seq[0]), .CE (N466), .CLK (ddrphy_clkin), - .D (_N63901), + .D (_N64884), .P (N0)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:545 @@ -139448,7 +139397,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 .Q (wrlvl_dq_seq[1]), .CE (N466), .CLK (ddrphy_clkin), - .D (_N63997), + .D (_N65016), .P (N0)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:545 @@ -139459,65 +139408,86 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 .Q (wrlvl_dq_seq[2]), .CE (N466), .CLK (ddrphy_clkin), - .D (_N64153), + .D (_N65071), .P (N0)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:545 GTP_LUT2 /* \wrlvl_dq_seq[3:0]_0 */ #( .INIT(4'b1110)) \wrlvl_dq_seq[3:0]_0 ( - .Z (_N63901), - .I0 (_N63902), + .Z (_N64884), + .I0 (_N64885), .I1 (wrlvl_dq_r[2])); // LUT = (I0)|(I1) ; GTP_LUT5 /* \wrlvl_dq_seq[3:0]_1_3 */ #( - .INIT(32'b11111111111111111011111111111111)) + .INIT(32'b11111111111111111111101111111111)) \wrlvl_dq_seq[3:0]_1_3 ( - .Z (_N63902), + .Z (_N64885), .I0 (wrlvl_ck_dly_start), .I1 (wrlvl_dqs_en), - .I2 (cnt[3]), + .I2 (cnt[4]), .I3 (cnt[2]), - .I4 (_N106218)); - // LUT = (~I3)|(~I2)|(~I1)|(I0)|(I4) ; + .I4 (_N107042)); + // LUT = (~I3)|(~I1)|(I0)|(I2)|(I4) ; - GTP_LUT2 /* \wrlvl_dq_seq[3:0]_96 */ #( - .INIT(4'b1110)) - \wrlvl_dq_seq[3:0]_96 ( - .Z (_N63997), - .I0 (_N63902), - .I1 (wrlvl_dq_seq[0])); - // LUT = (I0)|(I1) ; + GTP_LUT5 /* \wrlvl_dq_seq[3:0]_4 */ #( + .INIT(32'b01111111010111110101111101011111)) + \wrlvl_dq_seq[3:0]_4 ( + .Z (N449), + .I0 (wrlvl_dqs_en), + .I1 (cnt[1]), + .I2 (dq_vld), + .I3 (_N96900), + .I4 (_N97662)); + // LUT = (~I2)|(~I0)|(~I1&I3&I4) ; - GTP_LUT5 /* \wrlvl_dq_seq[3:0]_250_3 */ #( - .INIT(32'b11111111111111111111111110111111)) - \wrlvl_dq_seq[3:0]_250_3 ( - .Z (_N64153), + GTP_LUT4 /* \wrlvl_dq_seq[3:0]_5 */ #( + .INIT(16'b1101111111111111)) + \wrlvl_dq_seq[3:0]_5 ( + .Z (_N97478), + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wrlvl_dqs_en ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [1] ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld ), + .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg [4] )); + // LUT = (~I3)|(~I2)|(~I0)|(I1) ; + + GTP_LUT5 /* \wrlvl_dq_seq[3:0]_131_3 */ #( + .INIT(32'b11111111111111111111111111111011)) + \wrlvl_dq_seq[3:0]_131_3 ( + .Z (_N65016), .I0 (wrlvl_ck_dly_start), .I1 (wrlvl_dqs_en), - .I2 (cnt[2]), - .I3 (wrlvl_dq_seq[1]), - .I4 (_N106218)); - // LUT = (~I2)|(~I1)|(I0)|(I3)|(I4) ; + .I2 (cnt[4]), + .I3 (wrlvl_dq_seq[0]), + .I4 (_N107042)); + // LUT = (~I1)|(I0)|(I2)|(I3)|(I4) ; + + GTP_LUT2 /* \wrlvl_dq_seq[3:0]_186 */ #( + .INIT(4'b1110)) + \wrlvl_dq_seq[3:0]_186 ( + .Z (_N65071), + .I0 (_N64885), + .I1 (wrlvl_dq_seq[1])); + // LUT = (I0)|(I1) ; - GTP_LUT2 /* \wrlvl_dq_seq[3:0]_283 */ #( + GTP_LUT2 /* \wrlvl_dq_seq[3:0]_281 */ #( .INIT(4'b1110)) - \wrlvl_dq_seq[3:0]_283 ( - .Z (_N64186), - .I0 (_N63902), + \wrlvl_dq_seq[3:0]_281 ( + .Z (_N65170), + .I0 (_N64885), .I1 (wrlvl_dq_seq[2])); // LUT = (I0)|(I1) ; - GTP_LUT5 /* \wrlvl_dq_seq[3:0]_378 */ #( + GTP_LUT5 /* \wrlvl_dq_seq[3:0]_377 */ #( .INIT(32'b01111111010111110101111101011111)) - \wrlvl_dq_seq[3:0]_378 ( - .Z (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N449 ), - .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/wrlvl_dqs_en ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt [1] ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld ), - .I3 (_N96124), - .I4 (_N96886)); + \wrlvl_dq_seq[3:0]_377 ( + .Z (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N449 ), + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wrlvl_dqs_en ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [1] ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld ), + .I3 (_N96898), + .I4 (_N97660)); // LUT = (~I2)|(~I0)|(~I1&I3&I4) ; GTP_DFF_PE /* \wrlvl_dq_seq[3] */ #( @@ -139527,7 +139497,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 .Q (wrlvl_dq_seq[3]), .CE (N466), .CLK (ddrphy_clkin), - .D (_N64186), + .D (_N65170), .P (N0)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:545 @@ -139677,6 +139647,7 @@ endmodule module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq8 ( input [63:0] ddrphy_rdata, + input [5:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg , input N0, input _N11, input ddrphy_clkin, @@ -139684,63 +139655,65 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq8 input dqs_gate_vld, input gate_adj_done, input rdel_cal_vld, + input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_gate_vld , output [5:0] gdet_state_reg, output [63:0] read_data, output dqs_gate_check_pass, output gate_check, output rddata_check_pass, output rdel_rvalid, - output read_valid + output read_valid, + output \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N11 ); wire N118; wire _N9; wire _N16; wire _N19; wire _N21; - wire _N97687; - wire _N97690; - wire _N103376; - wire _N103377; - wire _N105732; - wire _N105736; - wire _N105740; - wire _N105744; - wire _N105748; - wire _N105752; - wire _N105756; - wire _N105757; - wire _N105760; - wire _N105765; - wire _N105767; - wire _N105787; - wire _N105791; - wire _N105795; - wire _N105799; - wire _N105802; - wire _N105806; - wire _N106100; - wire _N106104; - wire _N106108; - wire _N106112; - wire _N106116; - wire _N106124; - wire _N106128; - wire _N106132; - wire _N106136; - wire _N106140; - wire _N106144; - wire _N106148; - wire _N106152; - wire _N106156; - wire _N106159; + wire _N98465; + wire _N98468; + wire _N104188; + wire _N104189; + wire _N106554; + wire _N106558; + wire _N106562; + wire _N106566; + wire _N106570; + wire _N106574; + wire _N106578; + wire _N106579; + wire _N106582; + wire _N106587; + wire _N106589; + wire _N106609; + wire _N106613; + wire _N106617; + wire _N106621; + wire _N106624; + wire _N106628; + wire _N106920; + wire _N106924; + wire _N106928; + wire _N106932; + wire _N106936; + wire _N106944; + wire _N106948; + wire _N106952; + wire _N106956; + wire _N106960; + wire _N106964; + wire _N106968; + wire _N106972; + wire _N106976; + wire _N106979; wire [2:0] gdet_next_state; GTP_LUT2 /* N21_1 */ #( .INIT(4'b1000)) N21_1 ( - .Z (_N105765), + .Z (_N106587), .I0 (read_valid), - .I1 (_N97690)); + .I1 (_N98468)); // LUT = I0&I1 ; GTP_LUT3 /* \N57_12_or[1] */ #( @@ -139764,7 +139737,7 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq8 GTP_LUT5 /* N118_5 */ #( .INIT(32'b10000000000000000000000000000000)) N118_5 ( - .Z (_N105787), + .Z (_N106609), .I0 (read_data[6]), .I1 (read_data[12]), .I2 (read_data[14]), @@ -139775,7 +139748,7 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq8 GTP_LUT5 /* N118_9 */ #( .INIT(32'b10000000000000000000000000000000)) N118_9 ( - .Z (_N105791), + .Z (_N106613), .I0 (read_data[28]), .I1 (read_data[30]), .I2 (read_data[36]), @@ -139786,7 +139759,7 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq8 GTP_LUT5 /* N118_13 */ #( .INIT(32'b10000000000000000000000000000000)) N118_13 ( - .Z (_N105795), + .Z (_N106617), .I0 (read_data[46]), .I1 (read_data[52]), .I2 (read_data[54]), @@ -139797,7 +139770,7 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq8 GTP_LUT5 /* N118_17 */ #( .INIT(32'b00000000000000000000000000000001)) N118_17 ( - .Z (_N105799), + .Z (_N106621), .I0 (read_data[3]), .I1 (read_data[11]), .I2 (read_data[19]), @@ -139808,7 +139781,7 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq8 GTP_LUT5 /* N118_20 */ #( .INIT(32'b00000000000000100000000000000000)) N118_20 ( - .Z (_N105802), + .Z (_N106624), .I0 (read_data[4]), .I1 (read_data[43]), .I2 (read_data[51]), @@ -139819,135 +139792,26 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq8 GTP_LUT4 /* N118_24 */ #( .INIT(16'b1000000000000000)) N118_24 ( - .Z (_N105806), - .I0 (_N105787), - .I1 (_N105791), - .I2 (_N105795), - .I3 (_N105799)); + .Z (_N106628), + .I0 (_N106609), + .I1 (_N106613), + .I2 (_N106617), + .I3 (_N106621)); // LUT = I0&I1&I2&I3 ; GTP_LUT3 /* N118_25 */ #( .INIT(8'b10000000)) N118_25 ( .Z (N118), - .I0 (_N97687), - .I1 (_N105802), - .I2 (_N105806)); + .I0 (_N98465), + .I1 (_N106624), + .I2 (_N106628)); // LUT = I0&I1&I2 ; - GTP_LUT5 /* N172_65 */ #( - .INIT(32'b10000000000000000000000000000000)) - N172_65 ( - .Z (_N105732), - .I0 (read_data[16]), - .I1 (read_data[18]), - .I2 (read_data[24]), - .I3 (read_data[26]), - .I4 (read_data[32])); - // LUT = I0&I1&I2&I3&I4 ; - - GTP_LUT5 /* N172_69 */ #( - .INIT(32'b10000000000000000000000000000000)) - N172_69 ( - .Z (_N105736), - .I0 (read_data[34]), - .I1 (read_data[40]), - .I2 (read_data[42]), - .I3 (read_data[48]), - .I4 (read_data[50])); - // LUT = I0&I1&I2&I3&I4 ; - - GTP_LUT5 /* N172_73 */ #( - .INIT(32'b00000001000000000000000000000000)) - N172_73 ( - .Z (_N105740), - .I0 (read_data[1]), - .I1 (read_data[5]), - .I2 (read_data[7]), - .I3 (read_data[56]), - .I4 (read_data[58])); - // LUT = ~I0&~I1&~I2&I3&I4 ; - - GTP_LUT5 /* N172_77 */ #( - .INIT(32'b00000000000000000000000000000001)) - N172_77 ( - .Z (_N105744), - .I0 (read_data[9]), - .I1 (read_data[13]), - .I2 (read_data[15]), - .I3 (read_data[17]), - .I4 (read_data[21])); - // LUT = ~I0&~I1&~I2&~I3&~I4 ; - - GTP_LUT5 /* N172_81 */ #( - .INIT(32'b00000000000000000000000000000001)) - N172_81 ( - .Z (_N105748), - .I0 (read_data[23]), - .I1 (read_data[25]), - .I2 (read_data[29]), - .I3 (read_data[31]), - .I4 (read_data[33])); - // LUT = ~I0&~I1&~I2&~I3&~I4 ; - - GTP_LUT5 /* N172_85 */ #( - .INIT(32'b00000000000000000000000000000001)) - N172_85 ( - .Z (_N105752), - .I0 (read_data[37]), - .I1 (read_data[39]), - .I2 (read_data[41]), - .I3 (read_data[45]), - .I4 (read_data[47])); - // LUT = ~I0&~I1&~I2&~I3&~I4 ; - - GTP_LUT5 /* N172_89 */ #( - .INIT(32'b00000000000000000000000000000001)) - N172_89 ( - .Z (_N105756), - .I0 (read_data[49]), - .I1 (read_data[53]), - .I2 (read_data[55]), - .I3 (read_data[57]), - .I4 (read_data[61])); - // LUT = ~I0&~I1&~I2&~I3&~I4 ; - - GTP_LUT5 /* N172_90 */ #( - .INIT(32'b00000000000000001000000000000000)) - N172_90 ( - .Z (_N105757), - .I0 (read_data[0]), - .I1 (read_data[2]), - .I2 (read_data[8]), - .I3 (read_data[10]), - .I4 (read_data[63])); - // LUT = I0&I1&I2&I3&~I4 ; - - GTP_LUT4 /* N172_93 */ #( - .INIT(16'b1000000000000000)) - N172_93 ( - .Z (_N105760), - .I0 (_N105732), - .I1 (_N105736), - .I2 (_N105740), - .I3 (_N105757)); - // LUT = I0&I1&I2&I3 ; - - GTP_LUT5 /* N172_97 */ #( + GTP_LUT5 /* N172_63 */ #( .INIT(32'b10000000000000000000000000000000)) - N172_97 ( - .Z (_N97687), - .I0 (_N105744), - .I1 (_N105748), - .I2 (_N105752), - .I3 (_N105756), - .I4 (_N105760)); - // LUT = I0&I1&I2&I3&I4 ; - - GTP_LUT5 /* N172_101 */ #( - .INIT(32'b10000000000000000000000000000000)) - N172_101 ( - .Z (_N106124), + N172_63 ( + .Z (_N106944), .I0 (read_data[1]), .I1 (read_data[5]), .I2 (read_data[7]), @@ -139955,10 +139819,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq8 .I4 (read_data[13])); // LUT = I0&I1&I2&I3&I4 ; - GTP_LUT5 /* N172_105 */ #( + GTP_LUT5 /* N172_67 */ #( .INIT(32'b10000000000000000000000000000000)) - N172_105 ( - .Z (_N106128), + N172_67 ( + .Z (_N106948), .I0 (read_data[15]), .I1 (read_data[17]), .I2 (read_data[21]), @@ -139966,10 +139830,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq8 .I4 (read_data[25])); // LUT = I0&I1&I2&I3&I4 ; - GTP_LUT5 /* N172_109 */ #( + GTP_LUT5 /* N172_71 */ #( .INIT(32'b10000000000000000000000000000000)) - N172_109 ( - .Z (_N106132), + N172_71 ( + .Z (_N106952), .I0 (read_data[29]), .I1 (read_data[31]), .I2 (read_data[33]), @@ -139977,10 +139841,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq8 .I4 (read_data[39])); // LUT = I0&I1&I2&I3&I4 ; - GTP_LUT5 /* N172_113 */ #( + GTP_LUT5 /* N172_75 */ #( .INIT(32'b10000000000000000000000000000000)) - N172_113 ( - .Z (_N106136), + N172_75 ( + .Z (_N106956), .I0 (read_data[41]), .I1 (read_data[45]), .I2 (read_data[47]), @@ -139988,10 +139852,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq8 .I4 (read_data[53])); // LUT = I0&I1&I2&I3&I4 ; - GTP_LUT5 /* N172_117 */ #( + GTP_LUT5 /* N172_79 */ #( .INIT(32'b01000000000000000000000000000000)) - N172_117 ( - .Z (_N106140), + N172_79 ( + .Z (_N106960), .I0 (read_data[0]), .I1 (read_data[55]), .I2 (read_data[57]), @@ -139999,10 +139863,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq8 .I4 (read_data[63])); // LUT = ~I0&I1&I2&I3&I4 ; - GTP_LUT5 /* N172_121 */ #( + GTP_LUT5 /* N172_83 */ #( .INIT(32'b00000000000000000000000000000001)) - N172_121 ( - .Z (_N106144), + N172_83 ( + .Z (_N106964), .I0 (read_data[2]), .I1 (read_data[8]), .I2 (read_data[10]), @@ -140010,10 +139874,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq8 .I4 (read_data[18])); // LUT = ~I0&~I1&~I2&~I3&~I4 ; - GTP_LUT5 /* N172_125 */ #( + GTP_LUT5 /* N172_87 */ #( .INIT(32'b00000000000000000000000000000001)) - N172_125 ( - .Z (_N106148), + N172_87 ( + .Z (_N106968), .I0 (read_data[24]), .I1 (read_data[26]), .I2 (read_data[32]), @@ -140021,10 +139885,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq8 .I4 (read_data[40])); // LUT = ~I0&~I1&~I2&~I3&~I4 ; - GTP_LUT5 /* N172_129 */ #( + GTP_LUT5 /* N172_91 */ #( .INIT(32'b00000000000000000000000000000001)) - N172_129 ( - .Z (_N106152), + N172_91 ( + .Z (_N106972), .I0 (read_data[42]), .I1 (read_data[48]), .I2 (read_data[50]), @@ -140032,41 +139896,150 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq8 .I4 (read_data[58])); // LUT = ~I0&~I1&~I2&~I3&~I4 ; - GTP_LUT5 /* N172_133 */ #( + GTP_LUT5 /* N172_95 */ #( .INIT(32'b10000000000000000000000000000000)) - N172_133 ( - .Z (_N106156), - .I0 (_N97690), - .I1 (_N106124), - .I2 (_N106128), - .I3 (_N106132), - .I4 (_N106136)); + N172_95 ( + .Z (_N106976), + .I0 (_N98468), + .I1 (_N106944), + .I2 (_N106948), + .I3 (_N106952), + .I4 (_N106956)); // LUT = I0&I1&I2&I3&I4 ; - GTP_LUT4 /* N172_136 */ #( + GTP_LUT4 /* N172_98 */ #( .INIT(16'b1000000000000000)) - N172_136 ( - .Z (_N106159), - .I0 (_N106140), - .I1 (_N106144), - .I2 (_N106148), - .I3 (_N106152)); + N172_98 ( + .Z (_N106979), + .I0 (_N106960), + .I1 (_N106964), + .I2 (_N106968), + .I3 (_N106972)); // LUT = I0&I1&I2&I3 ; - GTP_LUT4 /* N202_37 */ #( + GTP_LUT5 /* N202_40 */ #( + .INIT(32'b10000000000000000000000000000000)) + N202_40 ( + .Z (_N106554), + .I0 (read_data[16]), + .I1 (read_data[18]), + .I2 (read_data[24]), + .I3 (read_data[26]), + .I4 (read_data[32])); + // LUT = I0&I1&I2&I3&I4 ; + + GTP_LUT5 /* N202_44 */ #( + .INIT(32'b10000000000000000000000000000000)) + N202_44 ( + .Z (_N106558), + .I0 (read_data[34]), + .I1 (read_data[40]), + .I2 (read_data[42]), + .I3 (read_data[48]), + .I4 (read_data[50])); + // LUT = I0&I1&I2&I3&I4 ; + + GTP_LUT5 /* N202_48 */ #( + .INIT(32'b00000001000000000000000000000000)) + N202_48 ( + .Z (_N106562), + .I0 (read_data[1]), + .I1 (read_data[5]), + .I2 (read_data[7]), + .I3 (read_data[56]), + .I4 (read_data[58])); + // LUT = ~I0&~I1&~I2&I3&I4 ; + + GTP_LUT5 /* N202_52 */ #( + .INIT(32'b00000000000000000000000000000001)) + N202_52 ( + .Z (_N106566), + .I0 (read_data[9]), + .I1 (read_data[13]), + .I2 (read_data[15]), + .I3 (read_data[17]), + .I4 (read_data[21])); + // LUT = ~I0&~I1&~I2&~I3&~I4 ; + + GTP_LUT5 /* N202_56 */ #( + .INIT(32'b00000000000000000000000000000001)) + N202_56 ( + .Z (_N106570), + .I0 (read_data[23]), + .I1 (read_data[25]), + .I2 (read_data[29]), + .I3 (read_data[31]), + .I4 (read_data[33])); + // LUT = ~I0&~I1&~I2&~I3&~I4 ; + + GTP_LUT5 /* N202_60 */ #( + .INIT(32'b00000000000000000000000000000001)) + N202_60 ( + .Z (_N106574), + .I0 (read_data[37]), + .I1 (read_data[39]), + .I2 (read_data[41]), + .I3 (read_data[45]), + .I4 (read_data[47])); + // LUT = ~I0&~I1&~I2&~I3&~I4 ; + + GTP_LUT5 /* N202_64 */ #( + .INIT(32'b00000000000000000000000000000001)) + N202_64 ( + .Z (_N106578), + .I0 (read_data[49]), + .I1 (read_data[53]), + .I2 (read_data[55]), + .I3 (read_data[57]), + .I4 (read_data[61])); + // LUT = ~I0&~I1&~I2&~I3&~I4 ; + + GTP_LUT5 /* N202_65 */ #( + .INIT(32'b00000000000000001000000000000000)) + N202_65 ( + .Z (_N106579), + .I0 (read_data[0]), + .I1 (read_data[2]), + .I2 (read_data[8]), + .I3 (read_data[10]), + .I4 (read_data[63])); + // LUT = I0&I1&I2&I3&~I4 ; + + GTP_LUT4 /* N202_68 */ #( .INIT(16'b1000000000000000)) - N202_37 ( - .Z (_N106100), + N202_68 ( + .Z (_N106582), + .I0 (_N106554), + .I1 (_N106558), + .I2 (_N106562), + .I3 (_N106579)); + // LUT = I0&I1&I2&I3 ; + + GTP_LUT5 /* N202_72 */ #( + .INIT(32'b10000000000000000000000000000000)) + N202_72 ( + .Z (_N98465), + .I0 (_N106566), + .I1 (_N106570), + .I2 (_N106574), + .I3 (_N106578), + .I4 (_N106582)); + // LUT = I0&I1&I2&I3&I4 ; + + GTP_LUT4 /* N202_75 */ #( + .INIT(16'b1000000000000000)) + N202_75 ( + .Z (_N106920), .I0 (read_data[3]), .I1 (read_data[11]), .I2 (read_data[19]), .I3 (read_data[27])); // LUT = I0&I1&I2&I3 ; - GTP_LUT5 /* N202_41 */ #( + GTP_LUT5 /* N202_79 */ #( .INIT(32'b01000000000000000000000000000000)) - N202_41 ( - .Z (_N106104), + N202_79 ( + .Z (_N106924), .I0 (read_data[4]), .I1 (read_data[35]), .I2 (read_data[43]), @@ -140074,10 +140047,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq8 .I4 (read_data[59])); // LUT = ~I0&I1&I2&I3&I4 ; - GTP_LUT5 /* N202_45 */ #( + GTP_LUT5 /* N202_83 */ #( .INIT(32'b00000000000000000000000000000001)) - N202_45 ( - .Z (_N106108), + N202_83 ( + .Z (_N106928), .I0 (read_data[6]), .I1 (read_data[12]), .I2 (read_data[14]), @@ -140085,10 +140058,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq8 .I4 (read_data[22])); // LUT = ~I0&~I1&~I2&~I3&~I4 ; - GTP_LUT5 /* N202_49 */ #( + GTP_LUT5 /* N202_87 */ #( .INIT(32'b00000000000000000000000000000001)) - N202_49 ( - .Z (_N106112), + N202_87 ( + .Z (_N106932), .I0 (read_data[28]), .I1 (read_data[30]), .I2 (read_data[36]), @@ -140096,10 +140069,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq8 .I4 (read_data[44])); // LUT = ~I0&~I1&~I2&~I3&~I4 ; - GTP_LUT5 /* N202_53 */ #( + GTP_LUT5 /* N202_91 */ #( .INIT(32'b00000000000000000000000000000001)) - N202_53 ( - .Z (_N106116), + N202_91 ( + .Z (_N106936), .I0 (read_data[46]), .I1 (read_data[52]), .I2 (read_data[54]), @@ -140107,17 +140080,25 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq8 .I4 (read_data[62])); // LUT = ~I0&~I1&~I2&~I3&~I4 ; - GTP_LUT5 /* N202_57 */ #( + GTP_LUT5 /* N202_95 */ #( .INIT(32'b10000000000000000000000000000000)) - N202_57 ( - .Z (_N97690), - .I0 (_N106100), - .I1 (_N106104), - .I2 (_N106108), - .I3 (_N106112), - .I4 (_N106116)); + N202_95 ( + .Z (_N98468), + .I0 (_N106920), + .I1 (_N106924), + .I2 (_N106928), + .I3 (_N106932), + .I4 (_N106936)); // LUT = I0&I1&I2&I3&I4 ; + GTP_LUT2 /* N306_1 */ #( + .INIT(4'b1000)) + N306_1 ( + .Z (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N11 ), + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_gate_vld ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg [0] )); + // LUT = I0&I1 ; + GTP_DFF_C /* dqs_gate_check_pass */ #( .GRS_EN("TRUE"), .INIT(1'b0)) @@ -140147,8 +140128,8 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq8 .I0 (gate_adj_done), .I1 (gdet_state_reg[1]), .I2 (_N11), - .I3 (_N97687), - .I4 (_N105765)); + .I3 (_N98465), + .I4 (_N106587)); // LUT = (I2)|(~I0&I1&~I4)|(~I0&I1&~I3) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqs_rddata_align_v1_3.vp:270 @@ -140158,8 +140139,8 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq8 .Z (_N16), .I0 (gate_adj_done), .I1 (gdet_state_reg[1]), - .I2 (_N97687), - .I3 (_N105765)); + .I2 (_N98465), + .I3 (_N106587)); // LUT = ~I0&I1&I2&I3 ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqs_rddata_align_v1_3.vp:270 @@ -140170,8 +140151,8 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq8 .I0 (gate_adj_done), .I1 (gdet_state_reg[1]), .I2 (gdet_state_reg[2]), - .I3 (_N97687), - .I4 (_N105765)); + .I3 (_N98465), + .I4 (_N106587)); // LUT = (~I0&I2&~I4)|(~I0&I2&~I3)|(~I0&I1&I3&I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqs_rddata_align_v1_3.vp:270 @@ -140181,8 +140162,8 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq8 .Z (_N21), .I0 (gate_adj_done), .I1 (gdet_state_reg[2]), - .I2 (_N97687), - .I3 (_N105765)); + .I2 (_N98465), + .I3 (_N106587)); // LUT = ~I0&I1&I2&I3 ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqs_rddata_align_v1_3.vp:270 @@ -140194,13 +140175,13 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq8 .I1 (dqs_gate_vld), .I2 (gdet_state_reg[0]), .I3 (gdet_state_reg[2]), - .I4 (_N105767)); + .I4 (_N106589)); // LUT = (~I1&I2)|(I0&I3)|(I0&I4) ; GTP_LUT2 /* \gdet_state_fsm[2:0]_39_2 */ #( .INIT(4'b1110)) \gdet_state_fsm[2:0]_39_2 ( - .Z (_N105767), + .Z (_N106589), .I0 (gdet_state_reg[1]), .I1 (gdet_state_reg[4])); // LUT = (I0)|(I1) ; @@ -140262,14 +140243,14 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq8 .Q (rddata_check_pass), .C (N0), .CLK (ddrphy_clkin), - .D (_N103377)); + .D (_N104189)); // defparam rddata_check_pass_vname.orig_name = rddata_check_pass; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqs_rddata_align_v1_3.vp:416 GTP_LUT5 /* rddata_check_pass_ce_mux */ #( .INIT(32'b11111111111111001010101010101000)) rddata_check_pass_ce_mux ( - .Z (_N103377), + .Z (_N104189), .I0 (rddata_check_pass), .I1 (gdet_next_state[2]), .I2 (gdet_next_state[1]), @@ -140923,7 +140904,7 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq8 rdel_rvalid_vname ( .Q (rdel_rvalid), .CLK (ddrphy_clkin), - .D (_N103376), + .D (_N104188), .P (N0)); // defparam rdel_rvalid_vname.orig_name = rdel_rvalid; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqs_rddata_align_v1_3.vp:427 @@ -140931,12 +140912,12 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq8 GTP_LUT5 /* rdel_rvalid_ce_mux */ #( .INIT(32'b11110011011100110111001101110011)) rdel_rvalid_ce_mux ( - .Z (_N103376), + .Z (_N104188), .I0 (read_valid), .I1 (rdel_cal_vld), .I2 (rdel_rvalid), - .I3 (_N106156), - .I4 (_N106159)); + .I3 (_N106976), + .I4 (_N106979)); // LUT = (~I1)|(~I0&I2)|(I2&I3&I4) ; GTP_DFF_C /* rdvalid_r1 */ #( @@ -140959,7 +140940,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 input [7:0] default_samp_position, input N0, input _N538, - input _N96158, + input _N96937, input ddrphy_clkin, input init_adj_rdel, input rdel_calibration, @@ -140972,10 +140953,10 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 output [9:0] cnt, output [2:0] rdel_ctrl_wire, output [7:0] total_margin_div2, - output _N81413_3, - output _N81413_5, - output _N105268, - output _N105278, + output _N82186_3, + output _N82186_5, + output _N106081, + output _N106091, output adj_rdel_done, output rdel_calib_done, output rdel_calib_error, @@ -141009,59 +140990,59 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 wire _N276; wire _N278; wire _N280; - wire _N5656; - wire _N14717; - wire _N14718; - wire _N14719; - wire _N14720; - wire _N14721; - wire _N14722; - wire _N14723; - wire _N14724; - wire _N14727; - wire _N14728; - wire _N14729; - wire _N14730; - wire _N14731; - wire _N14732; - wire _N14733; - wire _N14745; - wire _N14746; - wire _N14747; - wire _N14748; - wire _N14749; - wire _N14750; - wire _N14751; - wire _N14752; - wire _N15541; - wire _N15542; - wire _N15543; - wire _N15544; - wire _N15545; - wire _N15546; - wire _N15547; - wire _N17006; - wire _N17007; - wire _N17008; - wire _N17009; - wire _N17010; - wire _N17011; - wire _N17012; - wire _N30199; - wire _N82925; - wire _N87573; - wire _N103378; - wire _N103379; - wire _N103380; - wire _N103381; - wire _N105263; - wire _N105291; - wire _N105293; - wire _N106164; - wire _N106165; - wire _N106168; - wire _N106529; - wire _N106561; + wire _N5624; + wire _N14676; + wire _N14677; + wire _N14678; + wire _N14679; + wire _N14680; + wire _N14681; + wire _N14682; + wire _N14683; + wire _N14686; + wire _N14687; + wire _N14688; + wire _N14689; + wire _N14690; + wire _N14691; + wire _N14692; + wire _N14695; + wire _N14696; + wire _N14697; + wire _N14698; + wire _N14699; + wire _N14700; + wire _N14701; + wire _N14702; + wire _N14977; + wire _N14978; + wire _N14979; + wire _N14980; + wire _N14981; + wire _N14982; + wire _N14983; + wire _N17096; + wire _N17097; + wire _N17098; + wire _N17099; + wire _N17100; + wire _N17101; + wire _N17102; + wire _N30302; + wire _N84168; + wire _N88361; + wire _N104190; + wire _N104191; + wire _N104192; + wire _N104193; + wire _N106076; + wire _N106104; + wire _N106106; + wire _N106984; + wire _N106985; + wire _N106988; + wire _N107347; + wire _N107379; wire [7:0] left_margin; wire [2:0] rdel_ctrl; wire [3:0] rdel_ov_d; @@ -141078,7 +141059,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N85_1 ( - .COUT (_N14727), + .COUT (_N14686), .Z (total_margin_div2[0]), .CIN (), .I0 (samp_win_size[0]), @@ -141098,9 +141079,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N85_2 ( - .COUT (_N14728), + .COUT (_N14687), .Z (total_margin_div2[1]), - .CIN (_N14727), + .CIN (_N14686), .I0 (samp_win_size[0]), .I1 (samp_win_size[1]), .I2 (samp_win_size[2]), @@ -141118,9 +141099,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N85_3 ( - .COUT (_N14729), + .COUT (_N14688), .Z (total_margin_div2[2]), - .CIN (_N14728), + .CIN (_N14687), .I0 (), .I1 (samp_win_size[3]), .I2 (), @@ -141138,9 +141119,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N85_4 ( - .COUT (_N14730), + .COUT (_N14689), .Z (total_margin_div2[3]), - .CIN (_N14729), + .CIN (_N14688), .I0 (), .I1 (samp_win_size[4]), .I2 (), @@ -141158,9 +141139,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N85_5 ( - .COUT (_N14731), + .COUT (_N14690), .Z (total_margin_div2[4]), - .CIN (_N14730), + .CIN (_N14689), .I0 (), .I1 (samp_win_size[5]), .I2 (), @@ -141178,9 +141159,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N85_6 ( - .COUT (_N14732), + .COUT (_N14691), .Z (total_margin_div2[5]), - .CIN (_N14731), + .CIN (_N14690), .I0 (), .I1 (samp_win_size[6]), .I2 (), @@ -141198,9 +141179,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N85_7 ( - .COUT (_N14733), + .COUT (_N14692), .Z (total_margin_div2[6]), - .CIN (_N14732), + .CIN (_N14691), .I0 (), .I1 (samp_win_size[7]), .I2 (), @@ -141220,7 +141201,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 N85_8 ( .COUT (), .Z (total_margin_div2[7]), - .CIN (_N14733), + .CIN (_N14692), .I0 (), .I1 (total_margin[8]), .I2 (), @@ -141238,7 +141219,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_1 ( - .COUT (_N14717), + .COUT (_N14676), .Z (N604[1]), .CIN (), .I0 (cnt[0]), @@ -141258,9 +141239,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_2 ( - .COUT (_N14718), + .COUT (_N14677), .Z (N604[2]), - .CIN (_N14717), + .CIN (_N14676), .I0 (cnt[0]), .I1 (cnt[1]), .I2 (N694_inv), @@ -141278,9 +141259,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_3 ( - .COUT (_N14719), + .COUT (_N14678), .Z (N604[3]), - .CIN (_N14718), + .CIN (_N14677), .I0 (), .I1 (cnt[3]), .I2 (N694_inv), @@ -141298,9 +141279,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_4 ( - .COUT (_N14720), + .COUT (_N14679), .Z (N604[4]), - .CIN (_N14719), + .CIN (_N14678), .I0 (), .I1 (cnt[4]), .I2 (N694_inv), @@ -141318,9 +141299,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_5 ( - .COUT (_N14721), + .COUT (_N14680), .Z (N604[5]), - .CIN (_N14720), + .CIN (_N14679), .I0 (), .I1 (cnt[5]), .I2 (N694_inv), @@ -141338,9 +141319,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_6 ( - .COUT (_N14722), + .COUT (_N14681), .Z (N604[6]), - .CIN (_N14721), + .CIN (_N14680), .I0 (), .I1 (cnt[6]), .I2 (N694_inv), @@ -141358,9 +141339,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_7 ( - .COUT (_N14723), + .COUT (_N14682), .Z (N604[7]), - .CIN (_N14722), + .CIN (_N14681), .I0 (), .I1 (cnt[7]), .I2 (N694_inv), @@ -141378,9 +141359,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_8 ( - .COUT (_N14724), + .COUT (_N14683), .Z (N604[8]), - .CIN (_N14723), + .CIN (_N14682), .I0 (), .I1 (cnt[8]), .I2 (N694_inv), @@ -141400,7 +141381,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 N104_1_9 ( .COUT (), .Z (N604[9]), - .CIN (_N14724), + .CIN (_N14683), .I0 (), .I1 (cnt[9]), .I2 (N694_inv), @@ -141630,19 +141611,27 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .I1 (state_reg[2]), .I2 (state_reg[7]), .I3 (state_reg[10]), - .I4 (_N82925)); + .I4 (_N84168)); // LUT = (I0&I1)|(I0&I2)|(I0&I3)|(I0&I4) ; GTP_LUT4 /* \N247_1_1_or[0]_3 */ #( .INIT(16'b0001000100010000)) \N247_1_1_or[0]_3 ( - .Z (_N82925), + .Z (_N84168), .I0 (cnt[3]), .I1 (cnt[2]), .I2 (state_reg[5]), .I3 (state_reg[9])); // LUT = (~I0&~I1&I2)|(~I0&~I1&I3) ; + GTP_LUT2 /* \N247_1_1_or[0]_5 */ #( + .INIT(4'b1110)) + \N247_1_1_or[0]_5 ( + .Z (N679), + .I0 (state_reg[5]), + .I1 (state_reg[9])); + // LUT = (I0)|(I1) ; + GTP_LUT1 /* N249 */ #( .INIT(2'b01)) N249 ( @@ -141657,7 +141646,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .I4_TO_CARRY("FALSE"), .I4_TO_LUT("FALSE")) N264_1_0 ( - .COUT (_N15541), + .COUT (_N14977), .Z (), .CIN (), .I0 (), @@ -141677,9 +141666,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N264_1_1 ( - .COUT (_N15542), + .COUT (_N14978), .Z (N608[1]), - .CIN (_N15541), + .CIN (_N14977), .I0 (), .I1 (left_margin[1]), .I2 (rdel_calibration), @@ -141697,9 +141686,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N264_1_2 ( - .COUT (_N15543), + .COUT (_N14979), .Z (N608[2]), - .CIN (_N15542), + .CIN (_N14978), .I0 (), .I1 (left_margin[2]), .I2 (rdel_calibration), @@ -141717,9 +141706,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N264_1_3 ( - .COUT (_N15544), + .COUT (_N14980), .Z (N608[3]), - .CIN (_N15543), + .CIN (_N14979), .I0 (), .I1 (left_margin[3]), .I2 (rdel_calibration), @@ -141737,9 +141726,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N264_1_4 ( - .COUT (_N15545), + .COUT (_N14981), .Z (N608[4]), - .CIN (_N15544), + .CIN (_N14980), .I0 (), .I1 (left_margin[4]), .I2 (rdel_calibration), @@ -141757,9 +141746,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N264_1_5 ( - .COUT (_N15546), + .COUT (_N14982), .Z (N608[5]), - .CIN (_N15545), + .CIN (_N14981), .I0 (), .I1 (left_margin[5]), .I2 (rdel_calibration), @@ -141777,9 +141766,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N264_1_6 ( - .COUT (_N15547), + .COUT (_N14983), .Z (N608[6]), - .CIN (_N15546), + .CIN (_N14982), .I0 (), .I1 (left_margin[6]), .I2 (rdel_calibration), @@ -141799,7 +141788,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 N264_1_7 ( .COUT (), .Z (N608[7]), - .CIN (_N15547), + .CIN (_N14983), .I0 (), .I1 (left_margin[7]), .I2 (rdel_calibration), @@ -141817,7 +141806,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .I4_TO_CARRY("FALSE"), .I4_TO_LUT("FALSE")) N280_1_0 ( - .COUT (_N17006), + .COUT (_N17096), .Z (), .CIN (), .I0 (), @@ -141837,9 +141826,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N280_1_1 ( - .COUT (_N17007), + .COUT (_N17097), .Z (N611[1]), - .CIN (_N17006), + .CIN (_N17096), .I0 (), .I1 (right_margin[1]), .I2 (rdel_calibration), @@ -141857,9 +141846,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N280_1_2 ( - .COUT (_N17008), + .COUT (_N17098), .Z (N611[2]), - .CIN (_N17007), + .CIN (_N17097), .I0 (), .I1 (right_margin[2]), .I2 (rdel_calibration), @@ -141877,9 +141866,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N280_1_3 ( - .COUT (_N17009), + .COUT (_N17099), .Z (N611[3]), - .CIN (_N17008), + .CIN (_N17098), .I0 (), .I1 (right_margin[3]), .I2 (rdel_calibration), @@ -141897,9 +141886,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N280_1_4 ( - .COUT (_N17010), + .COUT (_N17100), .Z (N611[4]), - .CIN (_N17009), + .CIN (_N17099), .I0 (), .I1 (right_margin[4]), .I2 (rdel_calibration), @@ -141917,9 +141906,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N280_1_5 ( - .COUT (_N17011), + .COUT (_N17101), .Z (N611[5]), - .CIN (_N17010), + .CIN (_N17100), .I0 (), .I1 (right_margin[5]), .I2 (rdel_calibration), @@ -141937,9 +141926,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N280_1_6 ( - .COUT (_N17012), + .COUT (_N17102), .Z (N611[6]), - .CIN (_N17011), + .CIN (_N17101), .I0 (), .I1 (right_margin[6]), .I2 (rdel_calibration), @@ -141959,7 +141948,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 N280_1_7 ( .COUT (), .Z (N611[7]), - .CIN (_N17012), + .CIN (_N17102), .I0 (), .I1 (right_margin[7]), .I2 (rdel_calibration), @@ -141977,7 +141966,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N285_1_1 ( - .COUT (_N14745), + .COUT (_N14695), .Z (N285[0]), .CIN (), .I0 (right_margin[0]), @@ -141997,9 +141986,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N285_1_2 ( - .COUT (_N14746), + .COUT (_N14696), .Z (N285[1]), - .CIN (_N14745), + .CIN (_N14695), .I0 (right_margin[0]), .I1 (left_margin[0]), .I2 (right_margin[1]), @@ -142017,9 +142006,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N285_1_3 ( - .COUT (_N14747), + .COUT (_N14697), .Z (N285[2]), - .CIN (_N14746), + .CIN (_N14696), .I0 (), .I1 (right_margin[2]), .I2 (left_margin[2]), @@ -142037,9 +142026,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N285_1_4 ( - .COUT (_N14748), + .COUT (_N14698), .Z (N285[3]), - .CIN (_N14747), + .CIN (_N14697), .I0 (), .I1 (right_margin[3]), .I2 (left_margin[3]), @@ -142057,9 +142046,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N285_1_5 ( - .COUT (_N14749), + .COUT (_N14699), .Z (N285[4]), - .CIN (_N14748), + .CIN (_N14698), .I0 (), .I1 (right_margin[4]), .I2 (left_margin[4]), @@ -142077,9 +142066,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N285_1_6 ( - .COUT (_N14750), + .COUT (_N14700), .Z (N285[5]), - .CIN (_N14749), + .CIN (_N14699), .I0 (), .I1 (right_margin[5]), .I2 (left_margin[5]), @@ -142097,9 +142086,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N285_1_7 ( - .COUT (_N14751), + .COUT (_N14701), .Z (N285[6]), - .CIN (_N14750), + .CIN (_N14700), .I0 (), .I1 (right_margin[6]), .I2 (left_margin[6]), @@ -142117,9 +142106,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N285_1_8 ( - .COUT (_N14752), + .COUT (_N14702), .Z (N285[7]), - .CIN (_N14751), + .CIN (_N14701), .I0 (), .I1 (right_margin[7]), .I2 (left_margin[7]), @@ -142139,7 +142128,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 N285_1_9 ( .COUT (), .Z (N285[8]), - .CIN (_N14752), + .CIN (_N14702), .I0 (), .I1 (), .I2 (), @@ -142153,7 +142142,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 GTP_LUT3 /* N295_mux2 */ #( .INIT(8'b01010111)) N295_mux2 ( - .Z (_N5656), + .Z (_N5624), .I0 (samp_win_size[3]), .I1 (samp_win_size[2]), .I2 (samp_win_size[1])); @@ -142180,36 +142169,20 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .I4 (state_reg[10])); // LUT = (I0)|(I1)|(I2)|(I3)|(I4) ; - GTP_LUT2 /* N446_1 */ #( - .INIT(4'b1110)) - N446_1 ( - .Z (N603), - .I0 (state_reg[1]), - .I1 (state_reg[6])); - // LUT = (I0)|(I1) ; - GTP_LUT4 /* \N451_and[0][2] */ #( .INIT(16'b1010101010101000)) \N451_and[0][2] ( - .Z (_N30199), + .Z (_N30302), .I0 (default_samp_position[7]), .I1 (state_reg[1]), .I2 (state_reg[6]), .I3 (state_reg[7])); // LUT = (I0&I1)|(I0&I2)|(I0&I3) ; - GTP_LUT2 /* \N451_or[0]_1 */ #( - .INIT(4'b1110)) - \N451_or[0]_1 ( - .Z (N679), - .I0 (state_reg[5]), - .I1 (state_reg[9])); - // LUT = (I0)|(I1) ; - GTP_LUT5M /* N564_20_3 */ #( .INIT(32'b10101010100010001111111111111110)) N564_20_3 ( - .Z (_N106164), + .Z (_N106984), .I0 (rdel_move_en), .I1 (state_reg[5]), .I2 (state_reg[6]), @@ -142221,11 +142194,11 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 GTP_LUT5M /* N564_20_4 */ #( .INIT(32'b11111111101010101111111100000100)) N564_20_4 ( - .Z (_N106165), + .Z (_N106985), .I0 (state_reg[11]), .I1 (state_reg[0]), .I2 (reinit_adj_rdel), - .I3 (_N87573), + .I3 (_N88361), .I4 (rdel_calibration), .ID (init_adj_rdel)); // LUT = (~ID&I1&~I2&~I4)|(I0&I4)|(I3) ; @@ -142233,11 +142206,11 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 GTP_LUT5M /* N564_20_7 */ #( .INIT(32'b11111111111110001111111111111110)) N564_20_7 ( - .Z (_N106168), + .Z (_N106988), .I0 (rdel_move_en), .I1 (state_reg[7]), - .I2 (_N106164), - .I3 (_N106165), + .I2 (_N106984), + .I3 (_N106985), .I4 (N108), .ID (state_reg[2])); // LUT = (I1&~I4)|(ID&~I4)|(I3)|(I2)|(I0&I1) ; @@ -142245,7 +142218,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 GTP_LUT3 /* N564_25 */ #( .INIT(8'b01010100)) N564_25 ( - .Z (_N87573), + .Z (_N88361), .I0 (rdel_move_en), .I1 (state_reg[4]), .I2 (state_reg[8])); @@ -142258,14 +142231,14 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .I0 (rdel_move_en), .I1 (N167), .I2 (state_reg[10]), - .I3 (_N106168)); + .I3 (_N106988)); // defparam N570_vname.orig_name = N570; // LUT = (~I2&~I3)|(~I0&I1&~I3) ; GTP_LUT5 /* N598_1_2 */ #( .INIT(32'b11111111111111111111111111111110)) N598_1_2 ( - .Z (_N105291), + .Z (_N106104), .I0 (state_reg[0]), .I1 (state_reg[1]), .I2 (state_reg[4]), @@ -142276,12 +142249,12 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 GTP_LUT5 /* N598_1_4 */ #( .INIT(32'b11111111111111110111001101010000)) N598_1_4 ( - .Z (_N105293), + .Z (_N106106), .I0 (cnt[3]), .I1 (N108), .I2 (N679), .I3 (state_reg[7]), - .I4 (_N105291)); + .I4 (_N106104)); // LUT = (I4)|(~I1&I3)|(~I0&I2) ; GTP_LUT5 /* N598_1_6 */ #( @@ -142292,9 +142265,17 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .I1 (N167), .I2 (state_reg[2]), .I3 (state_reg[10]), - .I4 (_N105293)); + .I4 (_N106106)); // LUT = (I4)|(~I1&I3)|(~I0&I2) ; + GTP_LUT2 /* N598_5 */ #( + .INIT(4'b1110)) + N598_5 ( + .Z (N603), + .I0 (state_reg[1]), + .I1 (state_reg[6])); + // LUT = (I0)|(I1) ; + GTP_LUT2 /* \N604_1[0]_1 */ #( .INIT(4'b0100)) \N604_1[0]_1 ( @@ -142353,7 +142334,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 GTP_LUT4 /* N614_1_4 */ #( .INIT(16'b0000000000000001)) N614_1_4 ( - .Z (_N106529), + .Z (_N107347), .I0 (samp_win_size[7]), .I1 (samp_win_size[6]), .I2 (samp_win_size[5]), @@ -142363,7 +142344,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 GTP_LUT4 /* N621_1_2 */ #( .INIT(16'b1110111011101010)) N621_1_2 ( - .Z (_N106561), + .Z (_N107379), .I0 (rdel_calib_done), .I1 (cnt[3]), .I2 (state_reg[5]), @@ -142378,7 +142359,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .I1 (N167), .I2 (state_reg[7]), .I3 (state_reg[10]), - .I4 (_N106561)); + .I4 (_N107379)); // LUT = (I4)|(I0&I2)|(I1&I3) ; GTP_LUT5 /* N694_inv */ #( @@ -142400,14 +142381,14 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .Q (adj_rdel_done), .C (N0), .CLK (ddrphy_clkin), - .D (_N103381)); + .D (_N104193)); // defparam adj_rdel_done_vname.orig_name = adj_rdel_done; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqsi_rdel_cal_v1_2.vp:660 GTP_LUT5 /* adj_rdel_done_ce_mux */ #( .INIT(32'b11111111111000001110000011100000)) adj_rdel_done_ce_mux ( - .Z (_N103381), + .Z (_N104193), .I0 (init_adj_rdel), .I1 (reinit_adj_rdel), .I2 (adj_rdel_done), @@ -142631,17 +142612,17 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .Q (rdel_calib_error), .C (N0), .CLK (ddrphy_clkin), - .D (_N103380)); + .D (_N104192)); // defparam rdel_calib_error_vname.orig_name = rdel_calib_error; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqsi_rdel_cal_v1_2.vp:650 GTP_LUT5M /* rdel_calib_error_ce_mux */ #( .INIT(32'b00100000101000000010001010101010)) rdel_calib_error_ce_mux ( - .Z (_N103380), - .I0 (_N106529), + .Z (_N104192), + .I0 (_N107347), .I1 (state_reg[0]), - .I2 (_N5656), + .I2 (_N5624), .I3 (rdel_calibration), .I4 (state_reg[11]), .ID (rdel_calib_error)); @@ -142674,18 +142655,18 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .Q (rdel_ctrl_wire[2]), .C (N0), .CLK (ddrphy_clkin), - .D (_N103379)); + .D (_N104191)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqsi_rdel_cal_v1_2.vp:564 GTP_LUT5 /* \rdel_ctrl_ce_mux[2] */ #( .INIT(32'b11101110111011101110111011100010)) \rdel_ctrl_ce_mux[2] ( - .Z (_N103379), + .Z (_N104191), .I0 (rdel_ctrl_wire[2]), .I1 (N446), .I2 (state_reg[5]), .I3 (state_reg[10]), - .I4 (_N30199)); + .I4 (_N30302)); // LUT = (I0&~I1)|(I1&I2)|(I1&I3)|(I1&I4) ; GTP_DFF_C /* rdel_move_done */ #( @@ -142746,14 +142727,14 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .Q (rdel_ov_sync), .C (N0), .CLK (ddrphy_clkin), - .D (_N103378)); + .D (_N104190)); // defparam rdel_ov_sync_vname.orig_name = rdel_ov_sync; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqsi_rdel_cal_v1_2.vp:369 GTP_LUT3 /* rdel_ov_sync_ce_mux */ #( .INIT(8'b11101000)) rdel_ov_sync_ce_mux ( - .Z (_N103378), + .Z (_N104190), .I0 (rdel_ov_d[3]), .I1 (rdel_ov_d[2]), .I2 (rdel_ov_sync)); @@ -142872,7 +142853,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 \state_fsm[3:0]_135 ( .Z (_N134), .I0 (state_reg[2]), - .I1 (_N96158)); + .I1 (_N96937)); // LUT = I0&I1 ; GTP_LUT5 /* \state_fsm[3:0]_139 */ #( @@ -142915,7 +142896,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 .I1 (cnt[3]), .I2 (state_reg[7]), .I3 (state_reg[9]), - .I4 (_N96158)); + .I4 (_N96937)); // LUT = (~I0&I1&I3)|(~I0&I2&I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqsi_rdel_cal_v1_2.vp:459 @@ -142942,7 +142923,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 GTP_LUT5 /* \state_fsm[3:0]_540_4 */ #( .INIT(32'b11111101111111101111111111111111)) \state_fsm[3:0]_540_4 ( - .Z (_N105268), + .Z (_N106081), .I0 (cnt[8]), .I1 (cnt[1]), .I2 (cnt[0]), @@ -142953,7 +142934,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 GTP_LUT4 /* \state_fsm[3:0]_542_2 */ #( .INIT(16'b1000010000100001)) \state_fsm[3:0]_542_2 ( - .Z (_N105263), + .Z (_N106076), .I0 (cnt[3]), .I1 (cnt[2]), .I2 (total_margin_div2[1]), @@ -142963,28 +142944,28 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 GTP_LUT5 /* \state_fsm[3:0]_542_4 */ #( .INIT(32'b10000100001000010000000000000000)) \state_fsm[3:0]_542_4 ( - .Z (_N81413_3), + .Z (_N82186_3), .I0 (cnt[5]), .I1 (cnt[4]), .I2 (total_margin_div2[3]), .I3 (total_margin_div2[2]), - .I4 (_N105263)); + .I4 (_N106076)); // LUT = (~I0&~I1&~I2&~I3&I4)|(I0&~I1&I2&~I3&I4)|(~I0&I1&~I2&I3&I4)|(I0&I1&I2&I3&I4) ; GTP_LUT4 /* \state_fsm[3:0]_544 */ #( .INIT(16'b1000010000100001)) \state_fsm[3:0]_544 ( - .Z (_N81413_5), + .Z (_N82186_5), .I0 (cnt[7]), .I1 (cnt[6]), .I2 (total_margin_div2[5]), .I3 (total_margin_div2[4])); // LUT = (~I0&~I1&~I2&~I3)|(I0&~I1&I2&~I3)|(~I0&I1&~I2&I3)|(I0&I1&I2&I3) ; - GTP_LUT4 /* \state_fsm[3:0]_3377 */ #( + GTP_LUT4 /* \state_fsm[3:0]_3376 */ #( .INIT(16'b0000000000000001)) - \state_fsm[3:0]_3377 ( - .Z (_N105278), + \state_fsm[3:0]_3376 ( + .Z (_N106091), .I0 (default_samp_position[4]), .I1 (default_samp_position[3]), .I2 (default_samp_position[2]), @@ -143291,22 +143272,25 @@ module ipsxb_ddrphy_data_slice_v1_4_unq8 input [29:0] \dqsi_rdel_cal/N734 , input [7:0] \dqsi_rdel_cal/default_samp_position , input [2:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N22 , - input [2:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_next , input [5:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg , - input [4:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt , + input [4:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt , + input [6:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg , + input [5:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg , + input [4:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt , + input [6:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg , + input [3:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_flag_tmp , input [31:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/phy_wrdata_mask , input [3:0] \wdata_path_adj/phy_wrdata_en_r2 , input [3:0] \wdata_path_adj/phy_wrdata_en_slip4 , - input _N96107, - input _N96124, - input _N96158, - input _N96272, - input _N96318, - input _N96884, - input _N96886, - input _N106218, + input _N25006, + input _N96885, + input _N96898, + input _N96900, + input _N96937, + input _N97660, + input _N97662, + input _N107042, input \data_slice_dqs_gate_cal/gatecal/N1 , - input \data_slice_wrlvl/N449 , input ddrphy_clkin, input ddrphy_dqs_rst, input ddrphy_dqs_training_rstn, @@ -143323,10 +143307,10 @@ module ipsxb_ddrphy_data_slice_v1_4_unq8 input rdel_calibration, input rdel_move_en, input reinit_adj_rdel, - input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld , - input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/wrlvl_dqs_en , + input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld , + input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wrlvl_dqs_en , + input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_gate_vld , input wrlvl_ck_dly_done, - input wrlvl_ck_dly_start, input wrlvl_dqs_req, output [3:0] \data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 , output [3:0] \data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 , @@ -143340,17 +143324,17 @@ module ipsxb_ddrphy_data_slice_v1_4_unq8 output [9:0] \dqsi_rdel_cal/cnt , output [7:0] \dqsi_rdel_cal/total_margin_div2 , output [63:0] read_data, - output [4:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N484 , - output _N81413_3, - output _N81413_5, - output _N95825, - output _N105268, - output _N105278, - output _N106303, + output [4:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484 , + output _N82186_3, + output _N82186_5, + output _N96676, + output _N97478, + output _N97672, + output _N106081, + output _N106091, output adj_rdel_done, output ck_check_done, output \data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r , - output \data_slice_wrlvl/N165 , output \data_slice_wrlvl/dq_vld , output dm, output dqs_gate_vld, @@ -143363,8 +143347,9 @@ module ipsxb_ddrphy_data_slice_v1_4_unq8 output rdel_calib_error, output rdel_move_done, output read_valid, - output \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N449 , - output wrlvl_ck_dly_flag, + output \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N449 , + output \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N11 , + output wrlvl_ck_dly_start, output wrlvl_dqs_resp, output wrlvl_error, inout [7:0] dq, @@ -143411,6 +143396,10 @@ module ipsxb_ddrphy_data_slice_v1_4_unq8 wire \data_slice_dqs_gate_cal_gatecal/gate_state_reg[4]_floating ; wire \data_slice_dqs_gate_cal_gatecal/gate_state_reg[5]_floating ; wire \data_slice_dqs_gate_cal_read_clk_ctrl[2]_floating ; + wire \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484[0]_floating ; + wire \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484[1]_floating ; + wire \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484[2]_floating ; + wire \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484[3]_floating ; wire \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/adj_wrdqs[0]_floating ; wire \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/adj_wrdqs[1]_floating ; wire \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/adj_wrdqs[3]_floating ; @@ -143418,10 +143407,6 @@ module ipsxb_ddrphy_data_slice_v1_4_unq8 wire \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/adj_wrdqs[5]_floating ; wire \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/adj_wrdqs[6]_floating ; wire \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/adj_wrdqs[7]_floating ; - wire \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N484[0]_floating ; - wire \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N484[1]_floating ; - wire \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N484[2]_floating ; - wire \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N484[3]_floating ; wire \data_slice_wrlvl_wl_state_reg[0]_floating ; wire \data_slice_wrlvl_wl_state_reg[1]_floating ; wire \data_slice_wrlvl_wl_state_reg[2]_floating ; @@ -143463,16 +143448,16 @@ module ipsxb_ddrphy_data_slice_v1_4_unq8 .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r2 ({1'bx, \data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r2 [2] , 1'bx, \data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r2 [0] }), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r3 ({1'bx, \data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r3 [2] , 1'bx, \data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r3 [0] }), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N22 ({\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N22 [2] , 1'bx, 1'bx}), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_next ({\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_next [2] , 1'bx, 1'bx}), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg ({1'bx, 1'bx, \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg [3] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg [2] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg [1] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg [0] }), - ._N95825 (_N95825), + ._N96676 (_N96676), .dqs_gate_vld (dqs_gate_vld), .gate_adj_done (gate_adj_done), .gate_cal_error (gate_cal_error), .gate_check_error (gate_check_error), .gate_check_pass (gate_check_pass), .\gatecal/dqs_gate_vld_r (\data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r ), - ._N96107 (_N96107), + ._N25006 (_N25006), + ._N96885 (_N96885), .ddrphy_clkin (ddrphy_clkin), .dqs_gate_check_pass (dqs_gate_check_pass), .gate_check (gate_check), @@ -143484,37 +143469,38 @@ module ipsxb_ddrphy_data_slice_v1_4_unq8 ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq8 data_slice_wrlvl ( .cnt ({\data_slice_wrlvl/cnt [4] , \data_slice_wrlvl/cnt [3] , \data_slice_wrlvl/cnt [2] , \data_slice_wrlvl/cnt [1] , \data_slice_wrlvl/cnt [0] }), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484 ({\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484 [4] , \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484[3]_floating , \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484[2]_floating , \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484[1]_floating , \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484[0]_floating }), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/adj_wrdqs ({\data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/adj_wrdqs[7]_floating , \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/adj_wrdqs[6]_floating , \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/adj_wrdqs[5]_floating , \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/adj_wrdqs[4]_floating , \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/adj_wrdqs[3]_floating , adj_wrdqs[2], \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/adj_wrdqs[1]_floating , \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/adj_wrdqs[0]_floating }), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N484 ({\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N484 [4] , \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N484[3]_floating , \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N484[2]_floating , \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N484[1]_floating , \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N484[0]_floating }), .wl_state_reg ({\data_slice_wrlvl_wl_state_reg[6]_floating , \data_slice_wrlvl_wl_state_reg[5]_floating , \data_slice_wrlvl/wl_state_reg [4] , \data_slice_wrlvl_wl_state_reg[3]_floating , \data_slice_wrlvl_wl_state_reg[2]_floating , \data_slice_wrlvl_wl_state_reg[1]_floating , \data_slice_wrlvl_wl_state_reg[0]_floating }), .wrlvl_step ({debug_data[33], debug_data[32], debug_data[31], debug_data[30], debug_data[29], debug_data[28], debug_data[27], debug_data[26]}), .N484 ({\data_slice_wrlvl/N484 [4] , 1'bx, 1'bx, 1'bx, 1'bx}), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt ({\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [4] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [1] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [0] }), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg ({1'bx, 1'bx, \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg [4] , 1'bx, 1'bx, 1'bx, 1'bx}), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_in_dly (dq_in_dly), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt ({\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt [4] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt [1] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt [0] }), - .N165 (\data_slice_wrlvl/N165 ), - ._N106303 (_N106303), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt ({\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [4] , 1'bx, 1'bx, \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [1] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [0] }), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg ({1'bx, 1'bx, \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg [4] , 1'bx, 1'bx, 1'bx, 1'bx}), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_flag_tmp ({\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_flag_tmp [3] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_flag_tmp [2] , 1'bx, \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_flag_tmp [0] }), + ._N97478 (_N97478), + ._N97672 (_N97672), .ck_check_done (ck_check_done), .ddrphy_gatei (ddrphy_gatei), .dq_vld (\data_slice_wrlvl/dq_vld ), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N449 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N449 ), - .wrlvl_ck_dly_flag (wrlvl_ck_dly_flag), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N449 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N449 ), + .wrlvl_ck_dly_start (wrlvl_ck_dly_start), .wrlvl_dqs (wrlvl_dqs), .wrlvl_dqs_en (wrlvl_dqs_en), .wrlvl_dqs_resp (wrlvl_dqs_resp), .wrlvl_error (wrlvl_error), .N0 (\data_slice_dqs_gate_cal/gatecal/N1 ), - .N449 (\data_slice_wrlvl/N449 ), - ._N96124 (_N96124), - ._N96272 (_N96272), - ._N96318 (_N96318), - ._N96884 (_N96884), - ._N96886 (_N96886), - ._N106218 (_N106218), + ._N96898 (_N96898), + ._N96900 (_N96900), + ._N97660 (_N97660), + ._N97662 (_N97662), + ._N107042 (_N107042), .ddrphy_clkin (ddrphy_clkin), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld ), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/wrlvl_dqs_en (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/wrlvl_dqs_en ), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld ), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wrlvl_dqs_en (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wrlvl_dqs_en ), .wrlvl_ck_dly_done (wrlvl_ck_dly_done), - .wrlvl_ck_dly_start (wrlvl_ck_dly_start), .wrlvl_dqs_req (wrlvl_dqs_req)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_v1_4.vp:521 @@ -143970,18 +143956,21 @@ module ipsxb_ddrphy_data_slice_v1_4_unq8 .gdet_state_reg ({\dqs_rddata_align_gdet_state_reg[5]_floating , \dqs_rddata_align_gdet_state_reg[4]_floating , \dqs_rddata_align_gdet_state_reg[3]_floating , \dqs_rddata_align_gdet_state_reg[2]_floating , \dqs_rddata_align_gdet_state_reg[1]_floating , \dqs_rddata_align/gdet_state_reg [0] }), .read_data (read_data), .ddrphy_rdata (ddrphy_rdata), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg [0] }), .dqs_gate_check_pass (dqs_gate_check_pass), .gate_check (gate_check), .rddata_check_pass (rddata_check_pass), .rdel_rvalid (read_data_valid), .read_valid (read_valid), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N11 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N11 ), .N0 (\data_slice_dqs_gate_cal/gatecal/N1 ), ._N11 (\dqs_rddata_align/_N11 ), .ddrphy_clkin (ddrphy_clkin), .ddrphy_read_valid (ddrphy_read_valid), .dqs_gate_vld (dqs_gate_vld), .gate_adj_done (gate_adj_done), - .rdel_cal_vld (rdel_cal_vld)); + .rdel_cal_vld (rdel_cal_vld), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_gate_vld (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_gate_vld )); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_v1_4.vp:613 ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq8 dqsi_rdel_cal ( @@ -143990,17 +143979,17 @@ module ipsxb_ddrphy_data_slice_v1_4_unq8 .total_margin_div2 ({\dqsi_rdel_cal/total_margin_div2 [7] , \dqsi_rdel_cal_total_margin_div2[6]_floating , \dqsi_rdel_cal_total_margin_div2[5]_floating , \dqsi_rdel_cal_total_margin_div2[4]_floating , \dqsi_rdel_cal_total_margin_div2[3]_floating , \dqsi_rdel_cal_total_margin_div2[2]_floating , \dqsi_rdel_cal_total_margin_div2[1]_floating , \dqsi_rdel_cal_total_margin_div2[0]_floating }), .N734 ({1'bx, 1'bx, 1'bx, \dqsi_rdel_cal/N734 [26] , 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), .default_samp_position ({\dqsi_rdel_cal/default_samp_position [7] , \dqsi_rdel_cal/default_samp_position [6] , \dqsi_rdel_cal/default_samp_position [5] , \dqsi_rdel_cal/default_samp_position [4] , \dqsi_rdel_cal/default_samp_position [3] , \dqsi_rdel_cal/default_samp_position [2] , \dqsi_rdel_cal/default_samp_position [1] , \dqsi_rdel_cal/default_samp_position [0] }), - ._N81413_3 (_N81413_3), - ._N81413_5 (_N81413_5), - ._N105268 (_N105268), - ._N105278 (_N105278), + ._N82186_3 (_N82186_3), + ._N82186_5 (_N82186_5), + ._N106081 (_N106081), + ._N106091 (_N106091), .adj_rdel_done (adj_rdel_done), .rdel_calib_done (rdel_calib_done), .rdel_calib_error (rdel_calib_error), .rdel_move_done (rdel_move_done), .N0 (\data_slice_dqs_gate_cal/gatecal/N1 ), ._N538 (\dqsi_rdel_cal/_N538 ), - ._N96158 (_N96158), + ._N96937 (_N96937), .ddrphy_clkin (ddrphy_clkin), .init_adj_rdel (init_adj_rdel), .rdel_calibration (rdel_calibration), @@ -144152,21 +144141,21 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq10 wire N194_inv; wire N213; wire [4:0] N227; - wire _N5777; - wire _N23364; - wire _N23366; - wire _N23368; - wire _N23369; - wire _N23370; - wire _N23371; - wire _N23380; - wire _N23382; - wire _N23396; - wire _N23398; - wire _N23399; - wire _N95790; - wire _N96699; - wire _N103402; + wire _N5767; + wire _N23521; + wire _N23523; + wire _N23525; + wire _N23526; + wire _N23527; + wire _N23528; + wire _N23537; + wire _N23539; + wire _N23553; + wire _N23555; + wire _N23556; + wire _N96570; + wire _N97454; + wire _N104214; wire [4:0] cnt; wire [3:0] dqs_gate_pulse_src_nxt; wire [3:0] dqs_gate_pulse_src_nxt_r; @@ -144175,7 +144164,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq10 GTP_LUT3 /* N144_ac2 */ #( .INIT(8'b10000000)) N144_ac2 ( - .Z (_N5777), + .Z (_N5767), .I0 (cnt[2]), .I1 (cnt[1]), .I2 (cnt[0])); @@ -144194,7 +144183,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq10 GTP_LUT5 /* N205_1_5 */ #( .INIT(32'b00000000000000000000010000000000)) N205_1_5 ( - .Z (_N95790), + .Z (_N96570), .I0 (cnt[4]), .I1 (cnt[3]), .I2 (cnt[2]), @@ -144209,7 +144198,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq10 .I0 (gatecal_start), .I1 (rddata_cal), .I2 (N194_inv), - .I3 (_N95790)); + .I3 (_N96570)); // LUT = (I2)|(I3)|(~I0&~I1) ; GTP_LUT5 /* \N227[0]_1 */ #( @@ -144220,7 +144209,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq10 .I1 (rddata_cal), .I2 (cnt[0]), .I3 (N194_inv), - .I4 (_N95790)); + .I4 (_N96570)); // LUT = (I0&~I2&~I3&~I4)|(I1&~I2&~I3&~I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3.vp:346 @@ -144261,7 +144250,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq10 .INIT(16'b0000000001101100)) \N227[4]_1 ( .Z (N227[4]), - .I0 (_N5777), + .I0 (_N5767), .I1 (cnt[4]), .I2 (cnt[3]), .I3 (N213)); @@ -144274,7 +144263,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq10 .Z (dqs_gate_pulse_src_nxt[2]), .I0 (read_en_slipped[3]), .I1 (read_en_slipped[2]), - .I2 (_N96699)); + .I2 (_N97454)); // LUT = I0&~I1&~I2 ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3.vp:255 @@ -144284,7 +144273,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq10 .Z (dqs_gate_pulse_src[3]), .I0 (read_en_slipped[3]), .I1 (read_en_slipped[2]), - .I2 (_N96699)); + .I2 (_N97454)); // LUT = (I0)|(I1)|(I2) ; GTP_LUT4 /* N261_inv */ #( @@ -144294,7 +144283,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq10 .I0 (read_en_slipped[3]), .I1 (read_en_slipped[2]), .I2 (read_en_slipped[0]), - .I3 (_N96699)); + .I3 (_N97454)); // LUT = (I0&~I2)|(I1&~I2)|(~I2&I3) ; GTP_DFF_C /* \cnt[0] */ #( @@ -144530,17 +144519,17 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq10 \dqs_gate_pulse_src_4[1] ( .Z (dqs_gate_pulse_src[1]), .I0 (dqs_gate_pulse_src_nxt_r[1]), - .I1 (_N96699)); + .I1 (_N97454)); // LUT = (I0)|(I1) ; GTP_LUT4 /* \dqs_gate_pulse_src_4[1]_1 */ #( .INIT(16'b1111110111101100)) \dqs_gate_pulse_src_4[1]_1 ( - .Z (_N96699), + .Z (_N97454), .I0 (coarse_slip_step[1]), .I1 (read_en_slipped[0]), - .I2 (_N23369), - .I3 (_N23371)); + .I2 (_N23526), + .I3 (_N23528)); // LUT = (I1)|(~I0&I3)|(I0&I2) ; GTP_LUT3 /* \dqs_gate_pulse_src_4[2]_3 */ #( @@ -144549,7 +144538,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq10 .Z (dqs_gate_pulse_src[2]), .I0 (dqs_gate_pulse_src_nxt_r[2]), .I1 (read_en_slipped[2]), - .I2 (_N96699)); + .I2 (_N97454)); // LUT = (I0)|(I1)|(I2) ; GTP_LUT3 /* dqs_gate_pulse_src_nxt_4 */ #( @@ -144558,7 +144547,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq10 .Z (dqs_gate_pulse_src_nxt[1]), .I0 (read_en_slipped[3]), .I1 (read_en_slipped[2]), - .I2 (_N96699)); + .I2 (_N97454)); // LUT = (I0&~I2)|(I1&~I2) ; GTP_DFF_C /* \dqs_gate_pulse_src_nxt_r[0] */ #( @@ -144598,25 +144587,25 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq10 .Q (dqs_gate_vld), .C (N1), .CLK (ddrphy_clkin), - .D (_N103402)); + .D (_N104214)); // defparam dqs_gate_vld_vname.orig_name = dqs_gate_vld; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3.vp:346 GTP_LUT5 /* dqs_gate_vld_ce_mux */ #( .INIT(32'b11101110000000001110111011100000)) dqs_gate_vld_ce_mux ( - .Z (_N103402), + .Z (_N104214), .I0 (gatecal_start), .I1 (rddata_cal), .I2 (dqs_gate_vld), .I3 (N194_inv), - .I4 (_N95790)); + .I4 (_N96570)); // LUT = (I0&I3)|(I1&I3)|(I0&I2&~I4)|(I1&I2&~I4) ; GTP_LUT4 /* \read_en_slipped_5[0] */ #( .INIT(16'b0101010000010000)) \read_en_slipped_5[0] ( - .Z (_N23364), + .Z (_N23521), .I0 (coarse_slip_step[0]), .I1 (coarse_slip_step[3]), .I2 (read_cmd_mux_r1[2]), @@ -144626,7 +144615,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq10 GTP_LUT4 /* \read_en_slipped_5[2]_1 */ #( .INIT(16'b0101010000010000)) \read_en_slipped_5[2]_1 ( - .Z (_N23366), + .Z (_N23523), .I0 (coarse_slip_step[0]), .I1 (coarse_slip_step[3]), .I2 (read_cmd_mux[0]), @@ -144636,19 +144625,19 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq10 GTP_LUT5M /* \read_en_slipped_6[0] */ #( .INIT(32'b10001000101110001010101010101010)) \read_en_slipped_6[0] ( - .Z (_N23368), + .Z (_N23525), .I0 (read_cmd_mux[0]), .I1 (coarse_slip_step[3]), .I2 (read_cmd_mux_r2[2]), .I3 (coarse_slip_step[0]), .I4 (coarse_slip_step[2]), - .ID (_N23364)); + .ID (_N23521)); // LUT = (ID&~I4)|(~I1&I2&~I3&I4)|(I0&I1&I4) ; GTP_LUT5M /* \read_en_slipped_6[1] */ #( .INIT(32'b00001000000010001100100000001000)) \read_en_slipped_6[1] ( - .Z (_N23369), + .Z (_N23526), .I0 (read_cmd_mux_r2[2]), .I1 (coarse_slip_step[0]), .I2 (coarse_slip_step[3]), @@ -144660,19 +144649,19 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq10 GTP_LUT5M /* \read_en_slipped_6[2] */ #( .INIT(32'b11001100010100001010101010101010)) \read_en_slipped_6[2] ( - .Z (_N23370), + .Z (_N23527), .I0 (coarse_slip_step[0]), .I1 (read_cmd_mux[2]), .I2 (read_cmd_mux_r1[0]), .I3 (coarse_slip_step[3]), .I4 (coarse_slip_step[2]), - .ID (_N23366)); + .ID (_N23523)); // LUT = (ID&~I4)|(~I0&I2&~I3&I4)|(I1&I3&I4) ; GTP_LUT5M /* \read_en_slipped_6[3]_1 */ #( .INIT(32'b00001000000010001100100000001000)) \read_en_slipped_6[3]_1 ( - .Z (_N23371), + .Z (_N23528), .I0 (read_cmd_mux_r1[0]), .I1 (coarse_slip_step[0]), .I2 (coarse_slip_step[3]), @@ -144684,7 +144673,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq10 GTP_LUT5 /* \read_en_slipped_9[0] */ #( .INIT(32'b11010101110001001001000110000000)) \read_en_slipped_9[0] ( - .Z (_N23380), + .Z (_N23537), .I0 (coarse_slip_step[0]), .I1 (coarse_slip_step[3]), .I2 (read_cmd_mux[0]), @@ -144695,7 +144684,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq10 GTP_LUT5 /* \read_en_slipped_9[2] */ #( .INIT(32'b11010101110001001001000110000000)) \read_en_slipped_9[2] ( - .Z (_N23382), + .Z (_N23539), .I0 (coarse_slip_step[0]), .I1 (coarse_slip_step[3]), .I2 (read_cmd_mux[2]), @@ -144706,8 +144695,8 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq10 GTP_LUT5M /* \read_en_slipped_13[0] */ #( .INIT(32'b10101010101010100101000001000100)) \read_en_slipped_13[0] ( - .Z (_N23396), - .I0 (_N23380), + .Z (_N23553), + .I0 (_N23537), .I1 (read_cmd_mux[0]), .I2 (read_cmd_mux_r2[0]), .I3 (coarse_slip_step[3]), @@ -144718,8 +144707,8 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq10 GTP_LUT5M /* \read_en_slipped_13[2] */ #( .INIT(32'b10101010101010100101000001000100)) \read_en_slipped_13[2] ( - .Z (_N23398), - .I0 (_N23382), + .Z (_N23555), + .I0 (_N23539), .I1 (read_cmd_mux[2]), .I2 (read_cmd_mux_r2[2]), .I3 (coarse_slip_step[3]), @@ -144730,7 +144719,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq10 GTP_LUT5M /* \read_en_slipped_13[3] */ #( .INIT(32'b00001000000010001100100000001000)) \read_en_slipped_13[3] ( - .Z (_N23399), + .Z (_N23556), .I0 (read_cmd_mux_r1[2]), .I1 (coarse_slip_step[0]), .I2 (coarse_slip_step[3]), @@ -144741,14 +144730,14 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq10 GTP_MUX2LUT6 \read_en_slipped_14[0] ( .Z (read_en_slipped[0]), - .I0 (_N23396), - .I1 (_N23368), + .I0 (_N23553), + .I1 (_N23525), .S (coarse_slip_step[1])); GTP_MUX2LUT6 \read_en_slipped_14[2] ( .Z (read_en_slipped[2]), - .I0 (_N23398), - .I1 (_N23370), + .I0 (_N23555), + .I1 (_N23527), .S (coarse_slip_step[1])); GTP_LUT3 /* \read_en_slipped_14[3] */ #( @@ -144756,8 +144745,8 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq10 \read_en_slipped_14[3] ( .Z (read_en_slipped[3]), .I0 (coarse_slip_step[1]), - .I1 (_N23371), - .I2 (_N23399)); + .I1 (_N23528), + .I2 (_N23556)); // LUT = (~I0&I2)|(I0&I1) ; @@ -144767,7 +144756,7 @@ endmodule module ipsxb_ddrphy_gatecal_v1_3_unq10 ( input N1, - input _N96109, + input _N96887, input ddrphy_clkin, input dqs_gate_check_pass, input dqs_gate_vld, @@ -144800,25 +144789,26 @@ module ipsxb_ddrphy_gatecal_v1_3_unq10 wire _N6; wire _N10; wire _N17; - wire _N17028; - wire _N17029; - wire _N17030; - wire _N17031; - wire _N17032; - wire _N22242; - wire _N22245; - wire _N22246; - wire _N22247; - wire _N23275; - wire _N23276; - wire _N23277; - wire _N23278; - wire _N23279; - wire _N82905; - wire _N96023; - wire _N103383; - wire _N103384; - wire _N103385; + wire _N17044; + wire _N17045; + wire _N17046; + wire _N17047; + wire _N17048; + wire _N22182; + wire _N22185; + wire _N22186; + wire _N22187; + wire _N23183; + wire _N23184; + wire _N23185; + wire _N23186; + wire _N23187; + wire _N83739; + wire _N96948; + wire _N97026; + wire _N104195; + wire _N104196; + wire _N104197; wire [2:0] dgts_cnt; wire dqs_gate_vld_n; wire gate_check_pass_d; @@ -144851,7 +144841,7 @@ module ipsxb_ddrphy_gatecal_v1_3_unq10 GTP_LUT5 /* \N52_6[0] */ #( .INIT(32'b01010101110000000101010111111111)) \N52_6[0] ( - .Z (_N22242), + .Z (_N22182), .I0 (gate_move_en), .I1 (gatecal_start), .I2 (N567[6]), @@ -144860,20 +144850,20 @@ module ipsxb_ddrphy_gatecal_v1_3_unq10 // LUT = (~I3&~I4)|(~I0&I3)|(I1&I2&~I3) ; GTP_LUT5 /* \N52_7[0] */ #( - .INIT(32'b00110011011100110000000001000000)) + .INIT(32'b00110011000000000111001101000000)) \N52_7[0] ( - .Z (_N22245), + .Z (_N22185), .I0 (dqs_gate_vld), .I1 (gate_state_reg[2]), .I2 (dqs_gate_vld_r), - .I3 (_N82905), - .I4 (_N22242)); - // LUT = (~I1&I4)|(~I0&I1&I2&~I3) ; + .I3 (_N22182), + .I4 (_N83739)); + // LUT = (~I1&I3)|(~I0&I1&I2&~I4) ; GTP_LUT5M /* \N52_7[1] */ #( .INIT(32'b11111111000111111010101010101010)) \N52_7[1] ( - .Z (_N22246), + .Z (_N22186), .I0 (coarse_slip_step[3]), .I1 (dgts_cnt[2]), .I2 (dqs_gate_vld_r), @@ -144885,7 +144875,7 @@ module ipsxb_ddrphy_gatecal_v1_3_unq10 GTP_LUT5 /* \N52_7[2] */ #( .INIT(32'b11000000110010101100000011001111)) \N52_7[2] ( - .Z (_N22247), + .Z (_N22187), .I0 (gatecal_start), .I1 (N22[2]), .I2 (gate_state_reg[2]), @@ -144899,7 +144889,7 @@ module ipsxb_ddrphy_gatecal_v1_3_unq10 .Z (gate_state_next[2]), .I0 (gate_state_reg[1]), .I1 (gate_state_reg[0]), - .I2 (_N22247)); + .I2 (_N22187)); // LUT = ~I0&~I1&I2 ; GTP_LUT2 /* N55 */ #( @@ -144918,8 +144908,8 @@ module ipsxb_ddrphy_gatecal_v1_3_unq10 .I0 (coarse_slip_step[3]), .I1 (gate_state_reg[1]), .I2 (gate_state_reg[0]), - .I3 (_N22245), - .I4 (_N22246)); + .I3 (_N22185), + .I4 (_N22186)); // LUT = (I0&I1&~I2)|(I0&~I2&~I3&I4) ; GTP_LUT5CARRY /* N81_1_0 */ #( @@ -144929,7 +144919,7 @@ module ipsxb_ddrphy_gatecal_v1_3_unq10 .I4_TO_CARRY("FALSE"), .I4_TO_LUT("FALSE")) N81_1_0 ( - .COUT (_N17028), + .COUT (_N17044), .Z (), .CIN (), .I0 (), @@ -144949,12 +144939,12 @@ module ipsxb_ddrphy_gatecal_v1_3_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N81_1_1 ( - .COUT (_N17029), - .Z (_N23275), - .CIN (_N17028), + .COUT (_N17045), + .Z (_N23183), + .CIN (_N17044), .I0 (), .I1 (read_clk_ctrl[1]), - .I2 (_N96023), + .I2 (_N96948), .I3 (golden_value[1]), .I4 (1'b0), .ID ()); @@ -144969,12 +144959,12 @@ module ipsxb_ddrphy_gatecal_v1_3_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N81_1_2 ( - .COUT (_N17030), - .Z (_N23276), - .CIN (_N17029), + .COUT (_N17046), + .Z (_N23184), + .CIN (_N17045), .I0 (), .I1 (coarse_slip_step[0]), - .I2 (_N96023), + .I2 (_N96948), .I3 (golden_value[2]), .I4 (1'b0), .ID ()); @@ -144989,12 +144979,12 @@ module ipsxb_ddrphy_gatecal_v1_3_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N81_1_3 ( - .COUT (_N17031), - .Z (_N23277), - .CIN (_N17030), + .COUT (_N17047), + .Z (_N23185), + .CIN (_N17046), .I0 (), .I1 (coarse_slip_step[1]), - .I2 (_N96023), + .I2 (_N96948), .I3 (golden_value[3]), .I4 (1'b0), .ID ()); @@ -145009,12 +144999,12 @@ module ipsxb_ddrphy_gatecal_v1_3_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N81_1_4 ( - .COUT (_N17032), - .Z (_N23278), - .CIN (_N17031), + .COUT (_N17048), + .Z (_N23186), + .CIN (_N17047), .I0 (), .I1 (coarse_slip_step[2]), - .I2 (_N96023), + .I2 (_N96948), .I3 (golden_value[4]), .I4 (1'b0), .ID ()); @@ -145030,11 +145020,11 @@ module ipsxb_ddrphy_gatecal_v1_3_unq10 .I4_TO_LUT("FALSE")) N81_1_5 ( .COUT (), - .Z (_N23279), - .CIN (_N17032), + .Z (_N23187), + .CIN (_N17048), .I0 (), .I1 (coarse_slip_step[3]), - .I2 (_N96023), + .I2 (_N96948), .I3 (golden_value[5]), .I4 (1'b0), .ID ()); @@ -145050,7 +145040,7 @@ module ipsxb_ddrphy_gatecal_v1_3_unq10 .I1 (gate_win_size[1]), .I2 (gate_win_size[2]), .I3 (gate_state_next[2]), - .I4 (_N22245)); + .I4 (_N22185)); // defparam N139_vname.orig_name = N139; // LUT = (I2&I3&~I4)|(I0&I1&I3&~I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_gatecal_v1_3.vp:543 @@ -145082,105 +145072,112 @@ module ipsxb_ddrphy_gatecal_v1_3_unq10 // LUT = I0&I1 ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_gatecal_v1_3.vp:659 - GTP_LUT5M /* N301_2 */ #( - .INIT(32'b00000101000001010000000000000001)) - N301_2 ( + GTP_LUT5 /* N301 */ #( + .INIT(32'b01011100010111110000000000000000)) + N301_vname ( .Z (N301), .I0 (gatecal_start), .I1 (gate_state_reg[1]), - .I2 (gate_state_next[2]), - .I3 (_N22246), - .I4 (gate_state_reg[0]), - .ID (_N22245)); - // LUT = (~ID&~I1&~I2&~I3&~I4)|(~I0&~I2&I4) ; + .I2 (gate_state_reg[0]), + .I3 (_N22185), + .I4 (_N97026)); + // defparam N301_vname.orig_name = N301; + // LUT = (~I2&~I3&I4)|(I1&~I2&I4)|(~I0&I2&I4) ; + // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_gatecal_v1_3.vp:410 - GTP_LUT4 /* N327 */ #( - .INIT(16'b1111111011111010)) + GTP_LUT5M /* N301_1 */ #( + .INIT(32'b00000000111100100000000011110001)) + N301_1 ( + .Z (_N97026), + .I0 (N22[2]), + .I1 (gate_state_reg[1]), + .I2 (gate_state_reg[0]), + .I3 (gate_state_next[2]), + .I4 (gate_state_reg[2]), + .ID (gate_state_reg[3])); + // LUT = (~ID&~I1&~I3&~I4)|(I0&~I1&~I3&I4)|(I2&~I3) ; + + GTP_LUT2 /* N327 */ #( + .INIT(4'b1110)) N327_vname ( .Z (N327), .I0 (gate_move_en), - .I1 (gatecal_start), - .I2 (N301), - .I3 (gate_state_reg[0])); + .I1 (_N97026)); // defparam N327_vname.orig_name = N327; - // LUT = (I0)|(I2)|(I1&I3) ; - // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_gatecal_v1_3.vp:434 + // LUT = (I0)|(I1) ; - GTP_LUT3 /* N328_10 */ #( - .INIT(8'b00101010)) + GTP_LUT5M /* N328_10 */ #( + .INIT(32'b01000100110011001000110011001100)) N328_10 ( - .Z (_N96023), - .I0 (gate_move_en), - .I1 (gatecal_start), - .I2 (gate_state_reg[0])); - // LUT = (I0&~I2)|(I0&~I1) ; + .Z (_N96948), + .I0 (gatecal_start), + .I1 (gate_move_en), + .I2 (_N22185), + .I3 (_N97026), + .I4 (gate_state_reg[0]), + .ID (gate_state_reg[1])); + // LUT = (I1&~I2&~I4)|(ID&I1&~I4)|(~I0&I1&I4)|(I1&~I3) ; - GTP_LUT5M /* \N328_17[0]_1 */ #( - .INIT(32'b00000101010101011000100010001000)) + GTP_LUT5 /* \N328_17[0]_1 */ #( + .INIT(32'b01010101010101010011000000000000)) \N328_17[0]_1 ( .Z (N328[0]), .I0 (read_clk_ctrl[0]), - .I1 (golden_value[0]), - .I2 (gatecal_start), - .I3 (gate_state_reg[0]), - .I4 (gate_move_en), - .ID (N301)); - // LUT = (ID&I1&~I4)|(~I0&~I3&I4)|(~I0&~I2&I4) ; + .I1 (gate_move_en), + .I2 (golden_value[0]), + .I3 (N301), + .I4 (_N96948)); + // LUT = (~I0&I4)|(~I1&I2&I3&~I4) ; - GTP_LUT5 /* \N328_17[1]_1 */ #( - .INIT(32'b01110010111110100000000000000000)) + GTP_LUT4 /* \N328_17[1]_1 */ #( + .INIT(16'b1111000001000000)) \N328_17[1]_1 ( .Z (N328[1]), .I0 (gate_move_en), - .I1 (gatecal_start), - .I2 (N301), - .I3 (gate_state_reg[0]), - .I4 (_N23275)); - // LUT = (I0&~I3&I4)|(I0&~I1&I4)|(~I0&I2&I4) ; + .I1 (N301), + .I2 (_N23183), + .I3 (_N96948)); + // LUT = (I2&I3)|(~I0&I1&I2) ; - GTP_LUT5 /* \N328_17[2]_1 */ #( - .INIT(32'b01110010111110100000000000000000)) + GTP_LUT4 /* \N328_17[2]_1 */ #( + .INIT(16'b1111000001000000)) \N328_17[2]_1 ( .Z (N328[2]), .I0 (gate_move_en), - .I1 (gatecal_start), - .I2 (N301), - .I3 (gate_state_reg[0]), - .I4 (_N23276)); - // LUT = (I0&~I3&I4)|(I0&~I1&I4)|(~I0&I2&I4) ; + .I1 (N301), + .I2 (_N23184), + .I3 (_N96948)); + // LUT = (I2&I3)|(~I0&I1&I2) ; - GTP_LUT5 /* \N328_17[3]_1 */ #( - .INIT(32'b01110010111110100000000000000000)) + GTP_LUT4 /* \N328_17[3]_1 */ #( + .INIT(16'b1111000001000000)) \N328_17[3]_1 ( .Z (N328[3]), .I0 (gate_move_en), - .I1 (gatecal_start), - .I2 (N301), - .I3 (gate_state_reg[0]), - .I4 (_N23277)); - // LUT = (I0&~I3&I4)|(I0&~I1&I4)|(~I0&I2&I4) ; + .I1 (N301), + .I2 (_N23185), + .I3 (_N96948)); + // LUT = (I2&I3)|(~I0&I1&I2) ; - GTP_LUT5 /* \N328_17[4]_1 */ #( - .INIT(32'b01110010111110100000000000000000)) + GTP_LUT4 /* \N328_17[4]_1 */ #( + .INIT(16'b1111000001000000)) \N328_17[4]_1 ( .Z (N328[4]), .I0 (gate_move_en), - .I1 (gatecal_start), - .I2 (N301), - .I3 (gate_state_reg[0]), - .I4 (_N23278)); - // LUT = (I0&~I3&I4)|(I0&~I1&I4)|(~I0&I2&I4) ; + .I1 (N301), + .I2 (_N23186), + .I3 (_N96948)); + // LUT = (I2&I3)|(~I0&I1&I2) ; - GTP_LUT5 /* \N328_17[5]_1 */ #( - .INIT(32'b01110010111110100000000000000000)) + GTP_LUT4 /* \N328_17[5]_1 */ #( + .INIT(16'b1111000001000000)) \N328_17[5]_1 ( .Z (N328[5]), .I0 (gate_move_en), - .I1 (gatecal_start), - .I2 (N301), - .I3 (gate_state_reg[0]), - .I4 (_N23279)); - // LUT = (I0&~I3&I4)|(I0&~I1&I4)|(~I0&I2&I4) ; + .I1 (N301), + .I2 (_N23187), + .I3 (_N96948)); + // LUT = (I2&I3)|(~I0&I1&I2) ; GTP_LUT1 /* N389_4_inv */ #( .INIT(2'b01)) @@ -145374,14 +145371,14 @@ module ipsxb_ddrphy_gatecal_v1_3_unq10 .Q (gate_adj_done), .C (N1), .CLK (ddrphy_clkin), - .D (_N103384)); + .D (_N104196)); // defparam gate_adj_done_vname.orig_name = gate_adj_done; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_gatecal_v1_3.vp:406 GTP_LUT5 /* gate_adj_done_ce_mux */ #( .INIT(32'b00000000010001010000000001000100)) gate_adj_done_ce_mux ( - .Z (_N103384), + .Z (_N104196), .I0 (gate_move_en), .I1 (gate_adj_done), .I2 (dqs_gate_vld), @@ -145396,17 +145393,17 @@ module ipsxb_ddrphy_gatecal_v1_3_unq10 .Q (gate_cal_error), .C (N1), .CLK (ddrphy_clkin), - .D (_N103383)); + .D (_N104195)); // defparam gate_cal_error_vname.orig_name = gate_cal_error; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_gatecal_v1_3.vp:416 GTP_LUT3 /* gate_cal_error_ce_mux */ #( .INIT(8'b11101010)) gate_cal_error_ce_mux ( - .Z (_N103383), + .Z (_N104195), .I0 (gate_cal_error), .I1 (gate_state_next[2]), - .I2 (_N22245)); + .I2 (_N22185)); // LUT = (I0)|(I1&I2) ; GTP_DFF_C /* gate_check_error */ #( @@ -145427,18 +145424,18 @@ module ipsxb_ddrphy_gatecal_v1_3_unq10 .Q (gate_check_pass), .C (N1), .CLK (ddrphy_clkin), - .D (_N103385)); + .D (_N104197)); // defparam gate_check_pass_vname.orig_name = gate_check_pass; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_gatecal_v1_3.vp:620 GTP_LUT4 /* gate_check_pass_ce_mux */ #( .INIT(16'b1100101011001110)) gate_check_pass_ce_mux ( - .Z (_N103385), + .Z (_N104197), .I0 (gate_check_pass), .I1 (gate_state_next[2]), .I2 (N301), - .I3 (_N22245)); + .I3 (_N22185)); // LUT = (I1&~I3)|(I0&~I2)|(I1&I2) ; GTP_DFF_C /* gate_check_pass_d */ #( @@ -145490,7 +145487,7 @@ module ipsxb_ddrphy_gatecal_v1_3_unq10 .I1 (gate_move_en), .I2 (dgts_cnt[2]), .I3 (gate_state_reg[3]), - .I4 (_N96109)); + .I4 (_N96887)); // LUT = (~I1&I3)|(~I0&~I2&I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_gatecal_v1_3.vp:336 @@ -145501,15 +145498,15 @@ module ipsxb_ddrphy_gatecal_v1_3_unq10 .I0 (gatecal_start), .I1 (N567[6]), .I2 (gate_state_reg[4]), - .I3 (_N82905), - .I4 (_N96109)); + .I3 (_N83739), + .I4 (_N96887)); // LUT = (I3&I4)|(I0&~I1&I2) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_gatecal_v1_3.vp:336 GTP_LUT4 /* \gate_state_fsm[2:0]_36 */ #( .INIT(16'b1110110011001100)) \gate_state_fsm[2:0]_36 ( - .Z (_N82905), + .Z (_N83739), .I0 (coarse_slip_step[3]), .I1 (dgts_cnt[2]), .I2 (dgts_cnt[1]), @@ -145808,7 +145805,7 @@ module ipsxb_ddrphy_data_slice_dqs_gate_cal_v1_3_unq10 input [3:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r1 , input [3:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r2 , input [3:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r3 , - input _N96109, + input _N96887, input ddrphy_clkin, input dqs_gate_check_pass, input gate_check, @@ -145872,7 +145869,7 @@ module ipsxb_ddrphy_data_slice_dqs_gate_cal_v1_3_unq10 .gate_check_error (gate_check_error), .gate_check_pass (gate_check_pass), .N1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/N0 ), - ._N96109 (_N96109), + ._N96887 (_N96887), .ddrphy_clkin (ddrphy_clkin), .dqs_gate_check_pass (dqs_gate_check_pass), .dqs_gate_vld (dqs_gate_vld), @@ -145887,43 +145884,29 @@ endmodule module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 ( - input [4:0] N484, input [4:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt , - input [6:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg , input [4:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt , - input [6:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg , input [7:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_in_dly , input [4:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt , + input [6:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg , input N0, - input N449, - input _N96120, - input _N96124, - input _N96886, - input _N106288, - input _N106303, + input _N96902, + input _N97663, input ddrphy_clkin, - input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld , - input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wrlvl_dqs_en , - input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld , + input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N165 , input wrlvl_ck_dly_done, input wrlvl_ck_dly_start, input wrlvl_dqs_req, output [4:0] cnt, - output [4:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484 , + output [4:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484 , output [7:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/adj_wrdqs , output [6:0] wl_state_reg, output [7:0] wrlvl_step, - output _N96271, - output _N96272, - output _N96274, - output _N96318, - output _N96883, - output _N105949, - output _N106218, + output _N97033, + output _N106767, output ck_check_done, output ddrphy_gatei, - output dq_vld, - output \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N449 , + output \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N449 , output wrlvl_ck_dly_flag, output wrlvl_dqs, output wrlvl_dqs_en, @@ -145951,9 +145934,11 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 wire [2:0] N417; wire N439; wire [7:0] N440; + wire N449; wire [5:0] N450; wire N466; wire N475; + wire [4:0] N484; wire _N2; wire _N6; wire _N9; @@ -145961,51 +145946,54 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 wire _N12; wire _N15; wire _N22; - wire _N14060; - wire _N14061; - wire _N14062; - wire _N14063; - wire _N14064; - wire _N14065; - wire _N14769; - wire _N14770; - wire _N14771; - wire _N14772; - wire _N14773; - wire _N14774; - wire _N16990; - wire _N16991; - wire _N16992; - wire _N16993; - wire _N16994; - wire _N16995; - wire _N16996; - wire _N23286; - wire _N64325; - wire _N64932; - wire _N64933; - wire _N65028; - wire _N65124; - wire _N65304; - wire _N103388; - wire _N103389; - wire _N103390; - wire _N103391; - wire _N103392; - wire _N103393; - wire _N103394; - wire _N105253; - wire _N105261; - wire _N106260; - wire _N106261; - wire _N106267; - wire _N106274; - wire _N106275; - wire _N106283; - wire _N106301; - wire _N106700; + wire _N5686; + wire _N14727; + wire _N14728; + wire _N14729; + wire _N14730; + wire _N14731; + wire _N14732; + wire _N16953; + wire _N16954; + wire _N16955; + wire _N16956; + wire _N16957; + wire _N16958; + wire _N17062; + wire _N17063; + wire _N17064; + wire _N17065; + wire _N17066; + wire _N17067; + wire _N17068; + wire _N23194; + wire _N65317; + wire _N65977; + wire _N65978; + wire _N66121; + wire _N66165; + wire _N66261; + wire _N104200; + wire _N104201; + wire _N104202; + wire _N104203; + wire _N104204; + wire _N104205; + wire _N104206; + wire _N106060; + wire _N106061; + wire _N106069; + wire _N107086; + wire _N107087; + wire _N107090; + wire _N107095; + wire _N107103; + wire _N107107; + wire _N107120; + wire _N107512; wire [7:0] ck_dly_step; wire dq_rising; + wire dq_vld; wire [7:0] step_cnt; wire [7:0] vld_init_cnt; wire wl_done_flag; @@ -146015,15 +146003,6 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 wire [2:0] wrlvl_dq_r; wire [3:0] wrlvl_dq_seq; - GTP_LUT3 /* \N53_4_and[1][4]_1 */ #( - .INIT(8'b00000001)) - \N53_4_and[1][4]_1 ( - .Z (_N96318), - .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [4] ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [1] ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [0] )); - // LUT = ~I0&~I1&~I2 ; - GTP_LUT4 /* \N53_4_or[0]_1 */ #( .INIT(16'b1111111111100000)) \N53_4_or[0]_1 ( @@ -146094,6 +146073,14 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 // LUT = ~I0&I1 ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:364 + GTP_LUT2 /* N66_ac1 */ #( + .INIT(4'b1000)) + N66_ac1 ( + .Z (_N5686), + .I0 (cnt[1]), + .I1 (cnt[0])); + // LUT = I0&I1 ; + GTP_LUT5CARRY /* N102_1_0 */ #( .INIT(32'b11001100110011000000000000000000), .ID_TO_LUT("FALSE"), @@ -146101,7 +146088,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 .I4_TO_CARRY("FALSE"), .I4_TO_LUT("FALSE")) N102_1_0 ( - .COUT (_N16990), + .COUT (_N17062), .Z (), .CIN (), .I0 (), @@ -146121,9 +146108,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N102_1_1 ( - .COUT (_N16991), + .COUT (_N17063), .Z (N378[1]), - .CIN (_N16990), + .CIN (_N17062), .I0 (), .I1 (step_cnt[1]), .I2 (wrlvl_ck_dly_start), @@ -146141,9 +146128,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N102_1_2 ( - .COUT (_N16992), + .COUT (_N17064), .Z (N378[2]), - .CIN (_N16991), + .CIN (_N17063), .I0 (), .I1 (step_cnt[2]), .I2 (wrlvl_ck_dly_start), @@ -146161,9 +146148,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N102_1_3 ( - .COUT (_N16993), + .COUT (_N17065), .Z (N378[3]), - .CIN (_N16992), + .CIN (_N17064), .I0 (), .I1 (step_cnt[3]), .I2 (wrlvl_ck_dly_start), @@ -146181,9 +146168,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N102_1_4 ( - .COUT (_N16994), + .COUT (_N17066), .Z (N378[4]), - .CIN (_N16993), + .CIN (_N17065), .I0 (), .I1 (step_cnt[4]), .I2 (wrlvl_ck_dly_start), @@ -146201,9 +146188,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N102_1_5 ( - .COUT (_N16995), + .COUT (_N17067), .Z (N378[5]), - .CIN (_N16994), + .CIN (_N17066), .I0 (), .I1 (step_cnt[5]), .I2 (wrlvl_ck_dly_start), @@ -146221,9 +146208,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N102_1_6 ( - .COUT (_N16996), + .COUT (_N17068), .Z (N378[6]), - .CIN (_N16995), + .CIN (_N17067), .I0 (), .I1 (step_cnt[6]), .I2 (wrlvl_ck_dly_start), @@ -146243,7 +146230,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 N102_1_7 ( .COUT (), .Z (N378[7]), - .CIN (_N16996), + .CIN (_N17068), .I0 (), .I1 (step_cnt[7]), .I2 (wrlvl_ck_dly_start), @@ -146261,7 +146248,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_1 ( - .COUT (_N14769), + .COUT (_N14727), .Z (N387[1]), .CIN (), .I0 (ck_dly_step[0]), @@ -146281,9 +146268,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_2 ( - .COUT (_N14770), + .COUT (_N14728), .Z (N387[2]), - .CIN (_N14769), + .CIN (_N14727), .I0 (ck_dly_step[0]), .I1 (ck_dly_step[1]), .I2 (N296), @@ -146301,9 +146288,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_3 ( - .COUT (_N14771), + .COUT (_N14729), .Z (N387[3]), - .CIN (_N14770), + .CIN (_N14728), .I0 (), .I1 (ck_dly_step[3]), .I2 (N296), @@ -146321,9 +146308,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_4 ( - .COUT (_N14772), + .COUT (_N14730), .Z (N387[4]), - .CIN (_N14771), + .CIN (_N14729), .I0 (), .I1 (ck_dly_step[4]), .I2 (N296), @@ -146341,9 +146328,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_5 ( - .COUT (_N14773), + .COUT (_N14731), .Z (N387[5]), - .CIN (_N14772), + .CIN (_N14730), .I0 (), .I1 (ck_dly_step[5]), .I2 (N296), @@ -146361,9 +146348,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_6 ( - .COUT (_N14774), + .COUT (_N14732), .Z (N387[6]), - .CIN (_N14773), + .CIN (_N14731), .I0 (), .I1 (ck_dly_step[6]), .I2 (N296), @@ -146383,7 +146370,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 N104_1_7 ( .COUT (), .Z (N387[7]), - .CIN (_N14774), + .CIN (_N14732), .I0 (), .I1 (ck_dly_step[7]), .I2 (N296), @@ -146394,19 +146381,21 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 // CARRY = (I1) ? CIN : (I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:407 - GTP_LUT3 /* N124_1 */ #( - .INIT(8'b10000000)) - N124_1 ( - .Z (_N96883), - .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg [4] )); - // LUT = I0&I1&I2 ; + GTP_LUT5 /* N124_5 */ #( + .INIT(32'b10000000000000000000000000000000)) + N124_5 ( + .Z (N484[4]), + .I0 (cnt[4]), + .I1 (cnt[3]), + .I2 (cnt[2]), + .I3 (cnt[1]), + .I4 (cnt[0])); + // LUT = I0&I1&I2&I3&I4 ; - GTP_LUT5 /* N124_6 */ #( + GTP_LUT5 /* N124_7 */ #( .INIT(32'b00000000000000000000010000000000)) - N124_6 ( - .Z (_N106700), + N124_7 ( + .Z (_N107512), .I0 (cnt[4]), .I1 (cnt[3]), .I2 (cnt[2]), @@ -146422,7 +146411,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 .I1 (cnt[2]), .I2 (cnt[1]), .I3 (wl_state_reg[2]), - .I4 (_N96124)); + .I4 (_N96902)); // LUT = ~I0&I1&~I2&I3&I4 ; GTP_LUT2 /* \N141[0]_1 */ #( @@ -146500,7 +146489,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 GTP_LUT3 /* N151_2 */ #( .INIT(8'b00100000)) N151_2 ( - .Z (_N105253), + .Z (_N107090), .I0 (cnt[3]), .I1 (cnt[2]), .I2 (wl_state_reg[4])); @@ -146519,7 +146508,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 GTP_LUT5 /* N173_8 */ #( .INIT(32'b00000000000000010000000000000000)) N173_8 ( - .Z (_N105261), + .Z (_N107103), .I0 (vld_init_cnt[5]), .I1 (vld_init_cnt[4]), .I2 (vld_init_cnt[3]), @@ -146535,7 +146524,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 .I1 (vld_init_cnt[6]), .I2 (vld_init_cnt[2]), .I3 (vld_init_cnt[0]), - .I4 (_N105261)); + .I4 (_N107103)); // LUT = ~I0&~I1&I2&I3&I4 ; GTP_LUT5CARRY /* N201_1_1 */ #( @@ -146545,7 +146534,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N201_1_1 ( - .COUT (_N14060), + .COUT (_N16953), .Z (N440[1]), .CIN (), .I0 (vld_init_cnt[0]), @@ -146565,9 +146554,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N201_1_2 ( - .COUT (_N14061), + .COUT (_N16954), .Z (N440[2]), - .CIN (_N14060), + .CIN (_N16953), .I0 (vld_init_cnt[0]), .I1 (vld_init_cnt[1]), .I2 (wl_state_reg[6]), @@ -146585,9 +146574,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N201_1_3 ( - .COUT (_N14062), + .COUT (_N16955), .Z (N440[3]), - .CIN (_N14061), + .CIN (_N16954), .I0 (), .I1 (vld_init_cnt[3]), .I2 (wl_state_reg[6]), @@ -146605,9 +146594,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N201_1_4 ( - .COUT (_N14063), + .COUT (_N16956), .Z (N440[4]), - .CIN (_N14062), + .CIN (_N16955), .I0 (), .I1 (vld_init_cnt[4]), .I2 (wl_state_reg[6]), @@ -146625,9 +146614,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N201_1_5 ( - .COUT (_N14064), + .COUT (_N16957), .Z (N440[5]), - .CIN (_N14063), + .CIN (_N16956), .I0 (), .I1 (vld_init_cnt[5]), .I2 (wl_state_reg[6]), @@ -146645,9 +146634,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N201_1_6 ( - .COUT (_N14065), + .COUT (_N16958), .Z (N440[6]), - .CIN (_N14064), + .CIN (_N16957), .I0 (), .I1 (vld_init_cnt[6]), .I2 (wl_state_reg[6]), @@ -146667,7 +146656,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 N201_1_7 ( .COUT (), .Z (N440[7]), - .CIN (_N14065), + .CIN (_N16958), .I0 (), .I1 (vld_init_cnt[7]), .I2 (wl_state_reg[6]), @@ -146681,12 +146670,12 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 GTP_LUT5 /* N228_4 */ #( .INIT(32'b10000000000000000000000000000000)) N228_4 ( - .Z (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484 [4] ), - .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [4] ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] ), - .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [1] ), - .I4 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [0] )); + .Z (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484 [4] ), + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [4] ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] ), + .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [1] ), + .I4 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [0] )); // LUT = I0&I1&I2&I3&I4 ; GTP_LUT5 /* N228_9 */ #( @@ -146697,31 +146686,13 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 .I1 (cnt[1]), .I2 (cnt[0]), .I3 (dq_vld), - .I4 (_N96886)); + .I4 (_N97663)); // LUT = ~I0&~I1&I2&I3&I4 ; - GTP_LUT3 /* N232_1 */ #( - .INIT(8'b00000001)) - N232_1 ( - .Z (_N96271), - .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [0] ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [1] ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [4] )); - // LUT = ~I0&~I1&~I2 ; - - GTP_LUT3 /* N265_1 */ #( - .INIT(8'b10000000)) - N265_1 ( - .Z (_N96272), - .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [0] )); - // LUT = I0&I1&I2 ; - GTP_LUT5 /* N265_10 */ #( .INIT(32'b00000001000000000000000000000000)) N265_10 ( - .Z (_N106301), + .Z (_N107120), .I0 (wrlvl_dq_seq[3]), .I1 (wrlvl_dq_seq[2]), .I2 (wrlvl_dq_seq[1]), @@ -146732,7 +146703,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 GTP_LUT4 /* N279_6 */ #( .INIT(16'b1000000000000000)) N279_6 ( - .Z (_N106283), + .Z (_N106069), .I0 (step_cnt[4]), .I1 (step_cnt[3]), .I2 (step_cnt[2]), @@ -146747,13 +146718,13 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 .I1 (step_cnt[6]), .I2 (step_cnt[5]), .I3 (step_cnt[0]), - .I4 (_N106283)); + .I4 (_N106069)); // LUT = I0&I1&I2&I3&I4 ; GTP_LUT2 /* N286_9 */ #( .INIT(4'b0001)) N286_9 ( - .Z (_N106274), + .Z (_N106060), .I0 (ck_dly_step[7]), .I1 (ck_dly_step[0])); // LUT = ~I0&~I1 ; @@ -146761,7 +146732,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 GTP_LUT4 /* N286_10 */ #( .INIT(16'b0000000000000001)) N286_10 ( - .Z (_N106275), + .Z (_N106061), .I0 (ck_dly_step[5]), .I1 (ck_dly_step[4]), .I2 (ck_dly_step[2]), @@ -146776,7 +146747,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 .I1 (ck_dly_step[6]), .I2 (ck_dly_step[3]), .I3 (ck_dly_step[0]), - .I4 (_N106275)); + .I4 (_N106061)); // LUT = ~I0&I1&I2&~I3&I4 ; GTP_LUT5 /* N296 */ #( @@ -146806,7 +146777,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 GTP_LUT4 /* N334_5 */ #( .INIT(16'b0000000000000001)) N334_5 ( - .Z (_N106267), + .Z (_N107095), .I0 (wrlvl_ck_check_seq[5]), .I1 (wrlvl_ck_check_seq[2]), .I2 (wrlvl_ck_check_seq[1]), @@ -146819,7 +146790,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 .Z (N334), .I0 (wrlvl_ck_check_seq[4]), .I1 (wrlvl_ck_check_seq[3]), - .I2 (_N106267)); + .I2 (_N107095)); // LUT = ~I0&~I1&I2 ; GTP_LUT3 /* N359 */ #( @@ -146866,15 +146837,15 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:360 GTP_LUT5 /* \N367_1[4] */ #( - .INIT(32'b01101010000000001010101000000000)) + .INIT(32'b01101100110011000000000000000000)) \N367_1[4] ( .Z (N367[4]), - .I0 (cnt[4]), - .I1 (cnt[3]), - .I2 (cnt[2]), - .I3 (N475), - .I4 (_N106303)); - // LUT = (I0&I3&~I4)|(I0&~I2&I3)|(I0&~I1&I3)|(~I0&I1&I2&I3&I4) ; + .I0 (_N5686), + .I1 (cnt[4]), + .I2 (cnt[3]), + .I3 (cnt[2]), + .I4 (N475)); + // LUT = (I1&~I3&I4)|(I1&~I2&I4)|(~I0&I1&I4)|(I0&~I1&I2&I3&I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:360 GTP_LUT5M /* N377 */ #( @@ -146925,18 +146896,18 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 GTP_LUT5 /* N395_2 */ #( .INIT(32'b01010111010101010101010101010101)) N395_2 ( - .Z (_N23286), + .Z (_N23194), .I0 (wrlvl_ck_dly_start), .I1 (ck_dly_step[6]), .I2 (ck_dly_step[3]), - .I3 (_N106274), - .I4 (_N106275)); + .I3 (_N106060), + .I4 (_N106061)); // LUT = (~I0)|(~I1&~I2&I3&I4) ; GTP_LUT4 /* \N417[0]_14 */ #( .INIT(16'b1111111111111110)) \N417[0]_14 ( - .Z (_N106260), + .Z (_N107086), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_in_dly [3] ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_in_dly [2] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_in_dly [1] ), @@ -146946,7 +146917,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 GTP_LUT4 /* \N417[0]_15 */ #( .INIT(16'b1111111111111110)) \N417[0]_15 ( - .Z (_N106261), + .Z (_N107087), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_in_dly [7] ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_in_dly [6] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_in_dly [5] ), @@ -146959,8 +146930,8 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 .Z (N417[0]), .I0 (wrlvl_dqs_en), .I1 (dq_vld), - .I2 (_N106260), - .I3 (_N106261)); + .I2 (_N107086), + .I3 (_N107087)); // LUT = (~I1)|(~I0)|(I2)|(I3) ; GTP_LUT3 /* \N417[1] */ #( @@ -146991,7 +146962,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 .I1 (cnt[1]), .I2 (cnt[0]), .I3 (wl_state_reg[6]), - .I4 (_N96886)); + .I4 (_N97663)); // defparam N439_vname.orig_name = N439; // LUT = (I3)|(~I0&~I1&~I2&I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:509 @@ -147100,14 +147071,14 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 .Q (ck_check_done), .C (N0), .CLK (ddrphy_clkin), - .D (_N103393)); + .D (_N104205)); // defparam ck_check_done_vname.orig_name = ck_check_done; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:535 GTP_LUT5 /* ck_check_done_ce_mux */ #( .INIT(32'b00000000000000001110110011001100)) ck_check_done_ce_mux ( - .Z (_N103393), + .Z (_N104205), .I0 (wrlvl_ck_dly_start), .I1 (ck_check_done), .I2 (N228), @@ -147211,7 +147182,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 .C (N0), .CE (N359), .CLK (ddrphy_clkin), - .D (_N64325)); + .D (_N65317)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:360 GTP_DFF_CE /* \cnt[1] */ #( @@ -147247,10 +147218,10 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 .D (N367[3])); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:360 - GTP_LUT5M /* \cnt[4:0]_3692 */ #( + GTP_LUT5M /* \cnt[4:0]_3743 */ #( .INIT(32'b00000000111100010000000011110010)) - \cnt[4:0]_3692 ( - .Z (_N64325), + \cnt[4:0]_3743 ( + .Z (_N65317), .I0 (wl_next_state[2]), .I1 (wl_next_state[0]), .I2 (N63), @@ -147277,20 +147248,20 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 .Q (ddrphy_gatei), .C (N0), .CLK (ddrphy_clkin), - .D (_N103388)); + .D (_N104200)); // defparam ddrphy_gatei_vname.orig_name = ddrphy_gatei; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:413 GTP_LUT5M /* ddrphy_gatei_ce_mux */ #( .INIT(32'b11001100110010101100110001001100)) ddrphy_gatei_ce_mux ( - .Z (_N103388), - .I0 (_N23286), + .Z (_N104200), + .I0 (_N23194), .I1 (ddrphy_gatei), .I2 (wl_next_state[1]), .I3 (wl_next_state[2]), .I4 (wl_next_state[0]), - .ID (_N106700)); + .ID (_N107512)); // LUT = (I1&~I2&~I4)|(I0&~I2&~I3&I4)|(I1&I2&I4)|(I1&I3)|(~ID&I1&I2) ; GTP_DFF_C /* dq_rising */ #( @@ -147300,18 +147271,18 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 .Q (dq_rising), .C (N0), .CLK (ddrphy_clkin), - .D (_N103394)); + .D (_N104206)); // defparam dq_rising_vname.orig_name = dq_rising; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:559 GTP_LUT4 /* dq_rising_ce_mux */ #( .INIT(16'b0000111000001100)) dq_rising_ce_mux ( - .Z (_N103394), + .Z (_N104206), .I0 (N228), .I1 (dq_rising), .I2 (wl_state_reg[6]), - .I3 (_N106301)); + .I3 (_N107120)); // LUT = (I1&~I2)|(I0&~I2&I3) ; GTP_DFF_C /* dq_vld */ #( @@ -147321,19 +147292,19 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 .Q (dq_vld), .C (N0), .CLK (ddrphy_clkin), - .D (_N103389)); + .D (_N104201)); // defparam dq_vld_vname.orig_name = dq_vld; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:453 GTP_LUT5 /* dq_vld_ce_mux */ #( .INIT(32'b00001101000011000000110000001100)) dq_vld_ce_mux ( - .Z (_N103389), + .Z (_N104201), .I0 (cnt[1]), .I1 (dq_vld), .I2 (wl_state_reg[6]), - .I3 (_N96124), - .I4 (_N105253)); + .I3 (_N96902), + .I4 (_N107090)); // LUT = (I1&~I2)|(~I0&~I2&I3&I4) ; GTP_DFF_CE /* \step_cnt[0] */ #( @@ -147519,14 +147490,14 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 .Q (wl_done_flag), .C (N0), .CLK (ddrphy_clkin), - .D (_N103390)); + .D (_N104202)); // defparam wl_done_flag_vname.orig_name = wl_done_flag; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:463 GTP_LUT3 /* wl_done_flag_ce_mux */ #( .INIT(8'b01010100)) wl_done_flag_ce_mux ( - .Z (_N103390), + .Z (_N104202), .I0 (wrlvl_dqs_req), .I1 (wl_done_flag), .I2 (wl_state_reg[6])); @@ -147563,13 +147534,13 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:287 GTP_LUT3 /* \wl_state_fsm[2:0]_13 */ #( - .INIT(8'b10000000)) + .INIT(8'b00000001)) \wl_state_fsm[2:0]_13 ( - .Z (_N96274), + .Z (_N97033), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [0] ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] )); - // LUT = I0&I1&I2 ; + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [1] ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [4] )); + // LUT = ~I0&~I1&~I2 ; GTP_LUT5 /* \wl_state_fsm[2:0]_14 */ #( .INIT(32'b11101010101010101100000000000000)) @@ -147736,18 +147707,18 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 .Q (wrlvl_ck_dly_flag), .C (N0), .CLK (ddrphy_clkin), - .D (_N103391)); + .D (_N104203)); // defparam wrlvl_ck_dly_flag_vname.orig_name = wrlvl_ck_dly_flag; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:483 GTP_LUT5M /* wrlvl_ck_dly_flag_ce_mux */ #( .INIT(32'b11111110111111110101000001010000)) wrlvl_ck_dly_flag_ce_mux ( - .Z (_N103391), + .Z (_N104203), .I0 (wrlvl_ck_check_seq[4]), .I1 (wrlvl_ck_check_seq[3]), .I2 (wrlvl_ck_dly_flag), - .I3 (_N106267), + .I3 (_N107095), .I4 (N173), .ID (wrlvl_ck_dly_done)); // LUT = (~I3&I4)|(I2&I4)|(I1&I4)|(I0&I4)|(~ID&I2) ; @@ -147759,19 +147730,19 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 .Q (wrlvl_ck_dly_pass), .C (N0), .CLK (ddrphy_clkin), - .D (_N103392)); + .D (_N104204)); // defparam wrlvl_ck_dly_pass_vname.orig_name = wrlvl_ck_dly_pass; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:483 GTP_LUT5 /* wrlvl_ck_dly_pass_ce_mux */ #( .INIT(32'b11111111000100001111111100000000)) wrlvl_ck_dly_pass_ce_mux ( - .Z (_N103392), + .Z (_N104204), .I0 (wrlvl_ck_check_seq[4]), .I1 (wrlvl_ck_check_seq[3]), .I2 (N173), .I3 (wrlvl_ck_dly_pass), - .I4 (_N106267)); + .I4 (_N107095)); // LUT = (I3)|(~I0&~I1&I2&I4) ; GTP_DFF_P /* \wrlvl_dq_r[0] */ #( @@ -147811,7 +147782,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 .Q (wrlvl_dq_seq[0]), .CE (N466), .CLK (ddrphy_clkin), - .D (_N64932), + .D (_N65977), .P (N0)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:545 @@ -147822,7 +147793,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 .Q (wrlvl_dq_seq[1]), .CE (N466), .CLK (ddrphy_clkin), - .D (_N65028), + .D (_N66121), .P (N0)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:545 @@ -147833,86 +147804,95 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 .Q (wrlvl_dq_seq[2]), .CE (N466), .CLK (ddrphy_clkin), - .D (_N65124), + .D (_N66165), .P (N0)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:545 GTP_LUT2 /* \wrlvl_dq_seq[3:0]_0 */ #( .INIT(4'b1110)) \wrlvl_dq_seq[3:0]_0 ( - .Z (_N64932), - .I0 (_N64933), + .Z (_N65977), + .I0 (_N65978), .I1 (wrlvl_dq_r[2])); // LUT = (I0)|(I1) ; GTP_LUT5 /* \wrlvl_dq_seq[3:0]_1_3 */ #( - .INIT(32'b11111111111111111111111111111011)) + .INIT(32'b11111111111111111111101111111111)) \wrlvl_dq_seq[3:0]_1_3 ( - .Z (_N64933), + .Z (_N65978), .I0 (wrlvl_ck_dly_start), .I1 (wrlvl_dqs_en), .I2 (cnt[4]), - .I3 (cnt[1]), - .I4 (_N106288)); - // LUT = (~I1)|(I0)|(I2)|(I3)|(I4) ; + .I3 (wl_state_reg[4]), + .I4 (_N107107)); + // LUT = (~I3)|(~I1)|(I0)|(I2)|(I4) ; GTP_LUT5 /* \wrlvl_dq_seq[3:0]_4 */ #( .INIT(32'b01111111010111110101111101011111)) \wrlvl_dq_seq[3:0]_4 ( - .Z (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N449 ), - .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wrlvl_dqs_en ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [1] ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld ), - .I3 (_N96120), - .I4 (_N96883)); + .Z (N449), + .I0 (wrlvl_dqs_en), + .I1 (cnt[1]), + .I2 (dq_vld), + .I3 (_N96902), + .I4 (_N97663)); // LUT = (~I2)|(~I0)|(~I1&I3&I4) ; - GTP_LUT4 /* \wrlvl_dq_seq[3:0]_7 */ #( - .INIT(16'b1111011111111111)) - \wrlvl_dq_seq[3:0]_7 ( - .Z (_N105949), - .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [1] ), - .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld )); - // LUT = (~I3)|(~I1)|(~I0)|(I2) ; + GTP_LUT2 /* \wrlvl_dq_seq[3:0]_5 */ #( + .INIT(4'b1011)) + \wrlvl_dq_seq[3:0]_5 ( + .Z (_N106767), + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [4] ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] )); + // LUT = (~I1)|(I0) ; + + GTP_LUT5 /* \wrlvl_dq_seq[3:0]_143_3 */ #( + .INIT(32'b11111111111111111111111111111011)) + \wrlvl_dq_seq[3:0]_143_3 ( + .Z (_N66121), + .I0 (wrlvl_ck_dly_start), + .I1 (wrlvl_dqs_en), + .I2 (cnt[4]), + .I3 (wrlvl_dq_seq[0]), + .I4 (_N107107)); + // LUT = (~I1)|(I0)|(I2)|(I3)|(I4) ; - GTP_LUT2 /* \wrlvl_dq_seq[3:0]_96 */ #( + GTP_LUT2 /* \wrlvl_dq_seq[3:0]_187 */ #( .INIT(4'b1110)) - \wrlvl_dq_seq[3:0]_96 ( - .Z (_N65028), - .I0 (_N64933), - .I1 (wrlvl_dq_seq[0])); + \wrlvl_dq_seq[3:0]_187 ( + .Z (_N66165), + .I0 (_N65978), + .I1 (wrlvl_dq_seq[1])); // LUT = (I0)|(I1) ; - GTP_LUT2 /* \wrlvl_dq_seq[3:0]_191 */ #( + GTP_LUT2 /* \wrlvl_dq_seq[3:0]_282 */ #( .INIT(4'b1110)) - \wrlvl_dq_seq[3:0]_191 ( - .Z (_N65124), - .I0 (_N64933), - .I1 (wrlvl_dq_seq[1])); + \wrlvl_dq_seq[3:0]_282 ( + .Z (_N66261), + .I0 (_N65978), + .I1 (wrlvl_dq_seq[2])); // LUT = (I0)|(I1) ; - GTP_LUT5 /* \wrlvl_dq_seq[3:0]_369_3 */ #( - .INIT(32'b11111111111111111111111111111011)) - \wrlvl_dq_seq[3:0]_369_3 ( - .Z (_N65304), - .I0 (wrlvl_ck_dly_start), - .I1 (wrlvl_dqs_en), - .I2 (cnt[4]), - .I3 (wrlvl_dq_seq[2]), - .I4 (_N106288)); - // LUT = (~I1)|(I0)|(I2)|(I3)|(I4) ; + GTP_LUT5 /* \wrlvl_dq_seq[3:0]_378 */ #( + .INIT(32'b11010101010101010101010101010101)) + \wrlvl_dq_seq[3:0]_378 ( + .Z (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N449 ), + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N165 ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] ), + .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg [4] ), + .I4 (_N97033)); + // LUT = (~I0)|(I1&I2&I3&I4) ; - GTP_LUT4 /* \wrlvl_dq_seq[3:0]_382 */ #( - .INIT(16'b1110111111111111)) - \wrlvl_dq_seq[3:0]_382 ( - .Z (_N106218), - .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [4] ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [1] ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld ), - .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg [4] )); - // LUT = (~I3)|(~I2)|(I0)|(I1) ; + GTP_LUT4 /* \wrlvl_dq_seq[3:0]_381 */ #( + .INIT(16'b1111011111111111)) + \wrlvl_dq_seq[3:0]_381 ( + .Z (_N107107), + .I0 (cnt[3]), + .I1 (cnt[2]), + .I2 (cnt[1]), + .I3 (dq_vld)); + // LUT = (~I3)|(~I1)|(~I0)|(I2) ; GTP_DFF_PE /* \wrlvl_dq_seq[3] */ #( .GRS_EN("TRUE"), @@ -147921,7 +147901,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 .Q (wrlvl_dq_seq[3]), .CE (N466), .CLK (ddrphy_clkin), - .D (_N65304), + .D (_N66261), .P (N0)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:545 @@ -148072,11 +148052,13 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq10 ( input [63:0] ddrphy_rdata, input N0, + input _N11, input ddrphy_clkin, input ddrphy_read_valid, input dqs_gate_vld, input gate_adj_done, input rdel_cal_vld, + output [5:0] gdet_state_reg, output [63:0] read_data, output dqs_gate_check_pass, output gate_check, @@ -148085,57 +148067,55 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq10 output read_valid ); wire N118; - wire [3:0] N328; wire _N9; wire _N16; wire _N19; wire _N21; - wire _N97684; - wire _N97688; - wire _N103396; - wire _N103397; - wire _N105612; - wire _N105616; - wire _N105620; - wire _N105624; - wire _N105628; - wire _N105639; - wire _N105643; - wire _N105647; - wire _N105651; - wire _N105655; - wire _N105659; - wire _N105663; - wire _N105664; - wire _N105670; - wire _N105674; - wire _N105696; - wire _N105700; - wire _N105704; - wire _N105708; - wire _N105711; - wire _N105715; - wire _N106636; - wire _N106640; - wire _N106644; - wire _N106648; - wire _N106652; - wire _N106656; - wire _N106660; - wire _N106664; - wire _N106668; - wire _N106671; + wire _N98454; + wire _N98466; + wire _N104208; + wire _N104209; + wire _N106440; + wire _N106444; + wire _N106448; + wire _N106452; + wire _N106456; + wire _N106460; + wire _N106464; + wire _N106465; + wire _N106468; + wire _N106475; + wire _N106479; + wire _N106483; + wire _N106487; + wire _N106491; + wire _N106496; + wire _N106498; + wire _N106518; + wire _N106522; + wire _N106526; + wire _N106530; + wire _N106533; + wire _N106537; + wire _N107448; + wire _N107452; + wire _N107456; + wire _N107460; + wire _N107464; + wire _N107468; + wire _N107472; + wire _N107476; + wire _N107480; + wire _N107483; wire [2:0] gdet_next_state; - wire [5:0] gdet_state_reg; - GTP_LUT3 /* N21_2 */ #( - .INIT(8'b10000000)) - N21_2 ( - .Z (N328[2]), + GTP_LUT2 /* N21_1 */ #( + .INIT(4'b1000)) + N21_1 ( + .Z (_N106496), .I0 (read_valid), - .I1 (_N97684), - .I2 (_N97688)); - // LUT = I0&I1&I2 ; + .I1 (_N98454)); + // LUT = I0&I1 ; GTP_LUT3 /* \N57_12_or[1] */ #( .INIT(8'b11110100)) @@ -148158,7 +148138,7 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq10 GTP_LUT5 /* N118_5 */ #( .INIT(32'b10000000000000000000000000000000)) N118_5 ( - .Z (_N105696), + .Z (_N106518), .I0 (read_data[6]), .I1 (read_data[12]), .I2 (read_data[14]), @@ -148169,7 +148149,7 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq10 GTP_LUT5 /* N118_9 */ #( .INIT(32'b10000000000000000000000000000000)) N118_9 ( - .Z (_N105700), + .Z (_N106522), .I0 (read_data[28]), .I1 (read_data[30]), .I2 (read_data[36]), @@ -148180,7 +148160,7 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq10 GTP_LUT5 /* N118_13 */ #( .INIT(32'b10000000000000000000000000000000)) N118_13 ( - .Z (_N105704), + .Z (_N106526), .I0 (read_data[46]), .I1 (read_data[52]), .I2 (read_data[54]), @@ -148191,7 +148171,7 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq10 GTP_LUT5 /* N118_17 */ #( .INIT(32'b00000000000000000000000000000001)) N118_17 ( - .Z (_N105708), + .Z (_N106530), .I0 (read_data[3]), .I1 (read_data[11]), .I2 (read_data[19]), @@ -148202,7 +148182,7 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq10 GTP_LUT5 /* N118_20 */ #( .INIT(32'b00000000000000100000000000000000)) N118_20 ( - .Z (_N105711), + .Z (_N106533), .I0 (read_data[4]), .I1 (read_data[43]), .I2 (read_data[51]), @@ -148213,135 +148193,91 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq10 GTP_LUT4 /* N118_24 */ #( .INIT(16'b1000000000000000)) N118_24 ( - .Z (_N105715), - .I0 (_N105696), - .I1 (_N105700), - .I2 (_N105704), - .I3 (_N105708)); + .Z (_N106537), + .I0 (_N106518), + .I1 (_N106522), + .I2 (_N106526), + .I3 (_N106530)); // LUT = I0&I1&I2&I3 ; GTP_LUT3 /* N118_25 */ #( .INIT(8'b10000000)) N118_25 ( .Z (N118), - .I0 (_N97684), - .I1 (_N105711), - .I2 (_N105715)); + .I0 (_N98466), + .I1 (_N106533), + .I2 (_N106537)); // LUT = I0&I1&I2 ; + GTP_LUT4 /* N172_63 */ #( + .INIT(16'b1000000000000000)) + N172_63 ( + .Z (_N106475), + .I0 (read_data[3]), + .I1 (read_data[11]), + .I2 (read_data[19]), + .I3 (read_data[27])); + // LUT = I0&I1&I2&I3 ; + GTP_LUT5 /* N172_67 */ #( - .INIT(32'b10000000000000000000000000000000)) + .INIT(32'b01000000000000000000000000000000)) N172_67 ( - .Z (_N105639), - .I0 (read_data[16]), - .I1 (read_data[18]), - .I2 (read_data[24]), - .I3 (read_data[26]), - .I4 (read_data[32])); - // LUT = I0&I1&I2&I3&I4 ; + .Z (_N106479), + .I0 (read_data[4]), + .I1 (read_data[35]), + .I2 (read_data[43]), + .I3 (read_data[51]), + .I4 (read_data[59])); + // LUT = ~I0&I1&I2&I3&I4 ; GTP_LUT5 /* N172_71 */ #( - .INIT(32'b10000000000000000000000000000000)) + .INIT(32'b00000000000000000000000000000001)) N172_71 ( - .Z (_N105643), - .I0 (read_data[34]), - .I1 (read_data[40]), - .I2 (read_data[42]), - .I3 (read_data[48]), - .I4 (read_data[50])); - // LUT = I0&I1&I2&I3&I4 ; + .Z (_N106483), + .I0 (read_data[6]), + .I1 (read_data[12]), + .I2 (read_data[14]), + .I3 (read_data[20]), + .I4 (read_data[22])); + // LUT = ~I0&~I1&~I2&~I3&~I4 ; GTP_LUT5 /* N172_75 */ #( - .INIT(32'b00000001000000000000000000000000)) + .INIT(32'b00000000000000000000000000000001)) N172_75 ( - .Z (_N105647), - .I0 (read_data[1]), - .I1 (read_data[5]), - .I2 (read_data[7]), - .I3 (read_data[56]), - .I4 (read_data[58])); - // LUT = ~I0&~I1&~I2&I3&I4 ; + .Z (_N106487), + .I0 (read_data[28]), + .I1 (read_data[30]), + .I2 (read_data[36]), + .I3 (read_data[38]), + .I4 (read_data[44])); + // LUT = ~I0&~I1&~I2&~I3&~I4 ; GTP_LUT5 /* N172_79 */ #( .INIT(32'b00000000000000000000000000000001)) N172_79 ( - .Z (_N105651), - .I0 (read_data[9]), - .I1 (read_data[13]), - .I2 (read_data[15]), - .I3 (read_data[17]), - .I4 (read_data[21])); + .Z (_N106491), + .I0 (read_data[46]), + .I1 (read_data[52]), + .I2 (read_data[54]), + .I3 (read_data[60]), + .I4 (read_data[62])); // LUT = ~I0&~I1&~I2&~I3&~I4 ; GTP_LUT5 /* N172_83 */ #( - .INIT(32'b00000000000000000000000000000001)) - N172_83 ( - .Z (_N105655), - .I0 (read_data[23]), - .I1 (read_data[25]), - .I2 (read_data[29]), - .I3 (read_data[31]), - .I4 (read_data[33])); - // LUT = ~I0&~I1&~I2&~I3&~I4 ; - - GTP_LUT5 /* N172_87 */ #( - .INIT(32'b00000000000000000000000000000001)) - N172_87 ( - .Z (_N105659), - .I0 (read_data[37]), - .I1 (read_data[39]), - .I2 (read_data[41]), - .I3 (read_data[45]), - .I4 (read_data[47])); - // LUT = ~I0&~I1&~I2&~I3&~I4 ; - - GTP_LUT5 /* N172_91 */ #( - .INIT(32'b00000000000000000000000000000001)) - N172_91 ( - .Z (_N105663), - .I0 (read_data[49]), - .I1 (read_data[53]), - .I2 (read_data[55]), - .I3 (read_data[57]), - .I4 (read_data[61])); - // LUT = ~I0&~I1&~I2&~I3&~I4 ; - - GTP_LUT5 /* N172_92 */ #( - .INIT(32'b00000000000000001000000000000000)) - N172_92 ( - .Z (_N105664), - .I0 (read_data[0]), - .I1 (read_data[2]), - .I2 (read_data[8]), - .I3 (read_data[10]), - .I4 (read_data[63])); - // LUT = I0&I1&I2&I3&~I4 ; - - GTP_LUT4 /* N172_98 */ #( - .INIT(16'b1000000000000000)) - N172_98 ( - .Z (_N105670), - .I0 (_N105651), - .I1 (_N105655), - .I2 (_N105659), - .I3 (_N105663)); - // LUT = I0&I1&I2&I3 ; - - GTP_LUT5 /* N172_99 */ #( .INIT(32'b10000000000000000000000000000000)) - N172_99 ( - .Z (_N97684), - .I0 (_N105639), - .I1 (_N105643), - .I2 (_N105647), - .I3 (_N105664), - .I4 (_N105670)); + N172_83 ( + .Z (_N98454), + .I0 (_N106475), + .I1 (_N106479), + .I2 (_N106483), + .I3 (_N106487), + .I4 (_N106491)); // LUT = I0&I1&I2&I3&I4 ; - GTP_LUT5 /* N172_103 */ #( + GTP_LUT5 /* N172_87 */ #( .INIT(32'b10000000000000000000000000000000)) - N172_103 ( - .Z (_N106636), + N172_87 ( + .Z (_N107448), .I0 (read_data[1]), .I1 (read_data[5]), .I2 (read_data[7]), @@ -148349,10 +148285,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq10 .I4 (read_data[13])); // LUT = I0&I1&I2&I3&I4 ; - GTP_LUT5 /* N172_107 */ #( + GTP_LUT5 /* N172_91 */ #( .INIT(32'b10000000000000000000000000000000)) - N172_107 ( - .Z (_N106640), + N172_91 ( + .Z (_N107452), .I0 (read_data[15]), .I1 (read_data[17]), .I2 (read_data[21]), @@ -148360,10 +148296,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq10 .I4 (read_data[25])); // LUT = I0&I1&I2&I3&I4 ; - GTP_LUT5 /* N172_111 */ #( + GTP_LUT5 /* N172_95 */ #( .INIT(32'b10000000000000000000000000000000)) - N172_111 ( - .Z (_N106644), + N172_95 ( + .Z (_N107456), .I0 (read_data[29]), .I1 (read_data[31]), .I2 (read_data[33]), @@ -148371,10 +148307,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq10 .I4 (read_data[39])); // LUT = I0&I1&I2&I3&I4 ; - GTP_LUT5 /* N172_115 */ #( + GTP_LUT5 /* N172_99 */ #( .INIT(32'b10000000000000000000000000000000)) - N172_115 ( - .Z (_N106648), + N172_99 ( + .Z (_N107460), .I0 (read_data[41]), .I1 (read_data[45]), .I2 (read_data[47]), @@ -148382,10 +148318,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq10 .I4 (read_data[53])); // LUT = I0&I1&I2&I3&I4 ; - GTP_LUT5 /* N172_119 */ #( + GTP_LUT5 /* N172_103 */ #( .INIT(32'b01000000000000000000000000000000)) - N172_119 ( - .Z (_N106652), + N172_103 ( + .Z (_N107464), .I0 (read_data[0]), .I1 (read_data[55]), .I2 (read_data[57]), @@ -148393,10 +148329,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq10 .I4 (read_data[63])); // LUT = ~I0&I1&I2&I3&I4 ; - GTP_LUT5 /* N172_123 */ #( + GTP_LUT5 /* N172_107 */ #( .INIT(32'b00000000000000000000000000000001)) - N172_123 ( - .Z (_N106656), + N172_107 ( + .Z (_N107468), .I0 (read_data[2]), .I1 (read_data[8]), .I2 (read_data[10]), @@ -148404,10 +148340,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq10 .I4 (read_data[18])); // LUT = ~I0&~I1&~I2&~I3&~I4 ; - GTP_LUT5 /* N172_127 */ #( + GTP_LUT5 /* N172_111 */ #( .INIT(32'b00000000000000000000000000000001)) - N172_127 ( - .Z (_N106660), + N172_111 ( + .Z (_N107472), .I0 (read_data[24]), .I1 (read_data[26]), .I2 (read_data[32]), @@ -148415,10 +148351,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq10 .I4 (read_data[40])); // LUT = ~I0&~I1&~I2&~I3&~I4 ; - GTP_LUT5 /* N172_131 */ #( + GTP_LUT5 /* N172_115 */ #( .INIT(32'b00000000000000000000000000000001)) - N172_131 ( - .Z (_N106664), + N172_115 ( + .Z (_N107476), .I0 (read_data[42]), .I1 (read_data[48]), .I2 (read_data[50]), @@ -148426,90 +148362,134 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq10 .I4 (read_data[58])); // LUT = ~I0&~I1&~I2&~I3&~I4 ; - GTP_LUT5 /* N172_135 */ #( + GTP_LUT5 /* N172_119 */ #( .INIT(32'b10000000000000000000000000000000)) - N172_135 ( - .Z (_N106668), - .I0 (_N97688), - .I1 (_N106636), - .I2 (_N106640), - .I3 (_N106644), - .I4 (_N106648)); + N172_119 ( + .Z (_N107480), + .I0 (_N98454), + .I1 (_N107448), + .I2 (_N107452), + .I3 (_N107456), + .I4 (_N107460)); // LUT = I0&I1&I2&I3&I4 ; - GTP_LUT4 /* N172_138 */ #( + GTP_LUT4 /* N172_122 */ #( .INIT(16'b1000000000000000)) - N172_138 ( - .Z (_N106671), - .I0 (_N106652), - .I1 (_N106656), - .I2 (_N106660), - .I3 (_N106664)); - // LUT = I0&I1&I2&I3 ; - - GTP_LUT4 /* N202_34 */ #( - .INIT(16'b1000000000000000)) - N202_34 ( - .Z (_N105612), - .I0 (read_data[3]), - .I1 (read_data[11]), - .I2 (read_data[19]), - .I3 (read_data[27])); + N172_122 ( + .Z (_N107483), + .I0 (_N107464), + .I1 (_N107468), + .I2 (_N107472), + .I3 (_N107476)); // LUT = I0&I1&I2&I3 ; GTP_LUT5 /* N202_38 */ #( - .INIT(32'b01000000000000000000000000000000)) + .INIT(32'b10000000000000000000000000000000)) N202_38 ( - .Z (_N105616), - .I0 (read_data[4]), - .I1 (read_data[35]), - .I2 (read_data[43]), - .I3 (read_data[51]), - .I4 (read_data[59])); - // LUT = ~I0&I1&I2&I3&I4 ; + .Z (_N106440), + .I0 (read_data[16]), + .I1 (read_data[18]), + .I2 (read_data[24]), + .I3 (read_data[26]), + .I4 (read_data[32])); + // LUT = I0&I1&I2&I3&I4 ; GTP_LUT5 /* N202_42 */ #( - .INIT(32'b00000000000000000000000000000001)) + .INIT(32'b10000000000000000000000000000000)) N202_42 ( - .Z (_N105620), - .I0 (read_data[6]), - .I1 (read_data[12]), - .I2 (read_data[14]), - .I3 (read_data[20]), - .I4 (read_data[22])); - // LUT = ~I0&~I1&~I2&~I3&~I4 ; + .Z (_N106444), + .I0 (read_data[34]), + .I1 (read_data[40]), + .I2 (read_data[42]), + .I3 (read_data[48]), + .I4 (read_data[50])); + // LUT = I0&I1&I2&I3&I4 ; GTP_LUT5 /* N202_46 */ #( - .INIT(32'b00000000000000000000000000000001)) + .INIT(32'b00000001000000000000000000000000)) N202_46 ( - .Z (_N105624), - .I0 (read_data[28]), - .I1 (read_data[30]), - .I2 (read_data[36]), - .I3 (read_data[38]), - .I4 (read_data[44])); - // LUT = ~I0&~I1&~I2&~I3&~I4 ; + .Z (_N106448), + .I0 (read_data[1]), + .I1 (read_data[5]), + .I2 (read_data[7]), + .I3 (read_data[56]), + .I4 (read_data[58])); + // LUT = ~I0&~I1&~I2&I3&I4 ; GTP_LUT5 /* N202_50 */ #( .INIT(32'b00000000000000000000000000000001)) N202_50 ( - .Z (_N105628), - .I0 (read_data[46]), - .I1 (read_data[52]), - .I2 (read_data[54]), - .I3 (read_data[60]), - .I4 (read_data[62])); + .Z (_N106452), + .I0 (read_data[9]), + .I1 (read_data[13]), + .I2 (read_data[15]), + .I3 (read_data[17]), + .I4 (read_data[21])); // LUT = ~I0&~I1&~I2&~I3&~I4 ; GTP_LUT5 /* N202_54 */ #( - .INIT(32'b10000000000000000000000000000000)) + .INIT(32'b00000000000000000000000000000001)) N202_54 ( - .Z (_N97688), - .I0 (_N105612), - .I1 (_N105616), - .I2 (_N105620), - .I3 (_N105624), - .I4 (_N105628)); + .Z (_N106456), + .I0 (read_data[23]), + .I1 (read_data[25]), + .I2 (read_data[29]), + .I3 (read_data[31]), + .I4 (read_data[33])); + // LUT = ~I0&~I1&~I2&~I3&~I4 ; + + GTP_LUT5 /* N202_58 */ #( + .INIT(32'b00000000000000000000000000000001)) + N202_58 ( + .Z (_N106460), + .I0 (read_data[37]), + .I1 (read_data[39]), + .I2 (read_data[41]), + .I3 (read_data[45]), + .I4 (read_data[47])); + // LUT = ~I0&~I1&~I2&~I3&~I4 ; + + GTP_LUT5 /* N202_62 */ #( + .INIT(32'b00000000000000000000000000000001)) + N202_62 ( + .Z (_N106464), + .I0 (read_data[49]), + .I1 (read_data[53]), + .I2 (read_data[55]), + .I3 (read_data[57]), + .I4 (read_data[61])); + // LUT = ~I0&~I1&~I2&~I3&~I4 ; + + GTP_LUT5 /* N202_63 */ #( + .INIT(32'b00000000000000001000000000000000)) + N202_63 ( + .Z (_N106465), + .I0 (read_data[0]), + .I1 (read_data[2]), + .I2 (read_data[8]), + .I3 (read_data[10]), + .I4 (read_data[63])); + // LUT = I0&I1&I2&I3&~I4 ; + + GTP_LUT4 /* N202_66 */ #( + .INIT(16'b1000000000000000)) + N202_66 ( + .Z (_N106468), + .I0 (_N106440), + .I1 (_N106444), + .I2 (_N106448), + .I3 (_N106465)); + // LUT = I0&I1&I2&I3 ; + + GTP_LUT5 /* N202_70 */ #( + .INIT(32'b10000000000000000000000000000000)) + N202_70 ( + .Z (_N98466), + .I0 (_N106452), + .I1 (_N106456), + .I2 (_N106460), + .I3 (_N106464), + .I4 (_N106468)); // LUT = I0&I1&I2&I3&I4 ; GTP_DFF_C /* dqs_gate_check_pass */ #( @@ -148535,46 +148515,49 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq10 // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqs_rddata_align_v1_3.vp:389 GTP_LUT5 /* \gdet_state_fsm[2:0]_15 */ #( - .INIT(32'b11001101000001011100110000000000)) + .INIT(32'b11110000111101001111010011110100)) \gdet_state_fsm[2:0]_15 ( .Z (gdet_next_state[0]), .I0 (gate_adj_done), - .I1 (dqs_gate_vld), - .I2 (N328[2]), - .I3 (gdet_state_reg[0]), - .I4 (gdet_state_reg[1])); - // LUT = (I1&I3)|(~I0&~I2&I4) ; + .I1 (gdet_state_reg[1]), + .I2 (_N11), + .I3 (_N98466), + .I4 (_N106496)); + // LUT = (I2)|(~I0&I1&~I4)|(~I0&I1&~I3) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqs_rddata_align_v1_3.vp:270 - GTP_LUT3 /* \gdet_state_fsm[2:0]_17 */ #( - .INIT(8'b01000000)) + GTP_LUT4 /* \gdet_state_fsm[2:0]_17 */ #( + .INIT(16'b0100000000000000)) \gdet_state_fsm[2:0]_17 ( .Z (_N16), .I0 (gate_adj_done), - .I1 (N328[2]), - .I2 (gdet_state_reg[1])); - // LUT = ~I0&I1&I2 ; + .I1 (gdet_state_reg[1]), + .I2 (_N98466), + .I3 (_N106496)); + // LUT = ~I0&I1&I2&I3 ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqs_rddata_align_v1_3.vp:270 - GTP_LUT4 /* \gdet_state_fsm[2:0]_20 */ #( - .INIT(16'b0101000101000000)) + GTP_LUT5 /* \gdet_state_fsm[2:0]_20 */ #( + .INIT(32'b01000100010100000101000001010000)) \gdet_state_fsm[2:0]_20 ( .Z (_N19), .I0 (gate_adj_done), - .I1 (N328[2]), - .I2 (gdet_state_reg[1]), - .I3 (gdet_state_reg[2])); - // LUT = (~I0&~I1&I3)|(~I0&I1&I2) ; + .I1 (gdet_state_reg[1]), + .I2 (gdet_state_reg[2]), + .I3 (_N98466), + .I4 (_N106496)); + // LUT = (~I0&I2&~I4)|(~I0&I2&~I3)|(~I0&I1&I3&I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqs_rddata_align_v1_3.vp:270 - GTP_LUT3 /* \gdet_state_fsm[2:0]_22 */ #( - .INIT(8'b01000000)) + GTP_LUT4 /* \gdet_state_fsm[2:0]_22 */ #( + .INIT(16'b0100000000000000)) \gdet_state_fsm[2:0]_22 ( .Z (_N21), .I0 (gate_adj_done), - .I1 (N328[2]), - .I2 (gdet_state_reg[2])); - // LUT = ~I0&I1&I2 ; + .I1 (gdet_state_reg[2]), + .I2 (_N98466), + .I3 (_N106496)); + // LUT = ~I0&I1&I2&I3 ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqs_rddata_align_v1_3.vp:270 GTP_LUT5 /* \gdet_state_fsm[2:0]_36 */ #( @@ -148585,13 +148568,13 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq10 .I1 (dqs_gate_vld), .I2 (gdet_state_reg[0]), .I3 (gdet_state_reg[2]), - .I4 (_N105674)); + .I4 (_N106498)); // LUT = (~I1&I2)|(I0&I3)|(I0&I4) ; GTP_LUT2 /* \gdet_state_fsm[2:0]_39_2 */ #( .INIT(4'b1110)) \gdet_state_fsm[2:0]_39_2 ( - .Z (_N105674), + .Z (_N106498), .I0 (gdet_state_reg[1]), .I1 (gdet_state_reg[4])); // LUT = (I0)|(I1) ; @@ -148653,14 +148636,14 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq10 .Q (rddata_check_pass), .C (N0), .CLK (ddrphy_clkin), - .D (_N103397)); + .D (_N104209)); // defparam rddata_check_pass_vname.orig_name = rddata_check_pass; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqs_rddata_align_v1_3.vp:416 GTP_LUT5 /* rddata_check_pass_ce_mux */ #( .INIT(32'b11111111111111001010101010101000)) rddata_check_pass_ce_mux ( - .Z (_N103397), + .Z (_N104209), .I0 (rddata_check_pass), .I1 (gdet_next_state[2]), .I2 (gdet_next_state[1]), @@ -149314,7 +149297,7 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq10 rdel_rvalid_vname ( .Q (rdel_rvalid), .CLK (ddrphy_clkin), - .D (_N103396), + .D (_N104208), .P (N0)); // defparam rdel_rvalid_vname.orig_name = rdel_rvalid; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqs_rddata_align_v1_3.vp:427 @@ -149322,12 +149305,12 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq10 GTP_LUT5 /* rdel_rvalid_ce_mux */ #( .INIT(32'b11110011011100110111001101110011)) rdel_rvalid_ce_mux ( - .Z (_N103396), + .Z (_N104208), .I0 (read_valid), .I1 (rdel_cal_vld), .I2 (rdel_rvalid), - .I3 (_N106668), - .I4 (_N106671)); + .I3 (_N107480), + .I4 (_N107483)); // LUT = (~I1)|(~I0&I2)|(I2&I3&I4) ; GTP_DFF_C /* rdvalid_r1 */ #( @@ -149350,8 +149333,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 input [7:0] default_samp_position, input N0, input _N538, - input _N96160, - input _N106624, + input _N96939, input ddrphy_clkin, input init_adj_rdel, input rdel_calibration, @@ -149364,10 +149346,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 output [9:0] cnt, output [2:0] rdel_ctrl_wire, output [7:0] total_margin_div2, - output _N81414_3, - output _N81414_5, - output _N83022, - output _N106518, + output _N82187_3, + output _N82187_5, + output _N107336, output adj_rdel_done, output rdel_calib_done, output rdel_calib_error, @@ -149401,62 +149382,59 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 wire _N276; wire _N278; wire _N280; - wire _N5735; - wire _N14777; - wire _N14778; - wire _N14779; - wire _N14780; - wire _N14781; - wire _N14782; - wire _N14783; - wire _N14784; - wire _N14787; - wire _N14788; - wire _N14789; - wire _N14790; - wire _N14791; - wire _N14792; - wire _N14793; - wire _N14804; - wire _N14805; - wire _N14806; - wire _N14807; - wire _N14808; - wire _N14809; - wire _N14810; - wire _N14811; - wire _N15016; - wire _N15017; - wire _N15018; - wire _N15019; - wire _N15020; - wire _N15021; - wire _N15022; - wire _N15933; - wire _N15934; - wire _N15935; - wire _N15936; - wire _N15937; - wire _N15938; - wire _N15939; - wire _N30276; - wire _N83291; - wire _N88151; - wire _N103398; - wire _N103399; - wire _N103400; - wire _N103401; - wire _N106513; - wire _N106524; - wire _N106558; - wire _N106611; - wire _N106614; - wire _N106616; - wire _N106626; - wire _N106628; - wire _N106676; - wire _N106677; - wire _N106680; + wire _N5725; + wire _N14735; + wire _N14736; + wire _N14737; + wire _N14738; + wire _N14739; + wire _N14740; + wire _N14741; + wire _N14742; + wire _N14745; + wire _N14746; + wire _N14747; + wire _N14748; + wire _N14749; + wire _N14750; + wire _N14751; + wire _N14760; + wire _N14761; + wire _N14762; + wire _N14763; + wire _N14764; + wire _N14765; + wire _N14766; + wire _N14767; + wire _N15080; + wire _N15081; + wire _N15082; + wire _N15083; + wire _N15084; + wire _N15085; + wire _N15086; + wire _N17104; + wire _N17105; + wire _N17106; + wire _N17107; + wire _N17108; + wire _N17109; + wire _N17110; + wire _N30395; + wire _N84859; + wire _N88943; + wire _N104210; + wire _N104211; + wire _N104212; + wire _N104213; + wire _N107331; + wire _N107342; + wire _N107376; + wire _N107438; + wire _N107440; + wire _N107488; + wire _N107489; + wire _N107492; wire [7:0] left_margin; wire [2:0] rdel_ctrl; wire [3:0] rdel_ov_d; @@ -149473,7 +149451,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N85_1 ( - .COUT (_N14787), + .COUT (_N14745), .Z (total_margin_div2[0]), .CIN (), .I0 (samp_win_size[0]), @@ -149493,9 +149471,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N85_2 ( - .COUT (_N14788), + .COUT (_N14746), .Z (total_margin_div2[1]), - .CIN (_N14787), + .CIN (_N14745), .I0 (samp_win_size[0]), .I1 (samp_win_size[1]), .I2 (samp_win_size[2]), @@ -149513,9 +149491,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N85_3 ( - .COUT (_N14789), + .COUT (_N14747), .Z (total_margin_div2[2]), - .CIN (_N14788), + .CIN (_N14746), .I0 (), .I1 (samp_win_size[3]), .I2 (), @@ -149533,9 +149511,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N85_4 ( - .COUT (_N14790), + .COUT (_N14748), .Z (total_margin_div2[3]), - .CIN (_N14789), + .CIN (_N14747), .I0 (), .I1 (samp_win_size[4]), .I2 (), @@ -149553,9 +149531,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N85_5 ( - .COUT (_N14791), + .COUT (_N14749), .Z (total_margin_div2[4]), - .CIN (_N14790), + .CIN (_N14748), .I0 (), .I1 (samp_win_size[5]), .I2 (), @@ -149573,9 +149551,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N85_6 ( - .COUT (_N14792), + .COUT (_N14750), .Z (total_margin_div2[5]), - .CIN (_N14791), + .CIN (_N14749), .I0 (), .I1 (samp_win_size[6]), .I2 (), @@ -149593,9 +149571,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N85_7 ( - .COUT (_N14793), + .COUT (_N14751), .Z (total_margin_div2[6]), - .CIN (_N14792), + .CIN (_N14750), .I0 (), .I1 (samp_win_size[7]), .I2 (), @@ -149615,7 +149593,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 N85_8 ( .COUT (), .Z (total_margin_div2[7]), - .CIN (_N14793), + .CIN (_N14751), .I0 (), .I1 (total_margin[8]), .I2 (), @@ -149633,7 +149611,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_1 ( - .COUT (_N14777), + .COUT (_N14735), .Z (N604[1]), .CIN (), .I0 (cnt[0]), @@ -149653,9 +149631,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_2 ( - .COUT (_N14778), + .COUT (_N14736), .Z (N604[2]), - .CIN (_N14777), + .CIN (_N14735), .I0 (cnt[0]), .I1 (cnt[1]), .I2 (N694_inv), @@ -149673,9 +149651,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_3 ( - .COUT (_N14779), + .COUT (_N14737), .Z (N604[3]), - .CIN (_N14778), + .CIN (_N14736), .I0 (), .I1 (cnt[3]), .I2 (N694_inv), @@ -149693,9 +149671,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_4 ( - .COUT (_N14780), + .COUT (_N14738), .Z (N604[4]), - .CIN (_N14779), + .CIN (_N14737), .I0 (), .I1 (cnt[4]), .I2 (N694_inv), @@ -149713,9 +149691,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_5 ( - .COUT (_N14781), + .COUT (_N14739), .Z (N604[5]), - .CIN (_N14780), + .CIN (_N14738), .I0 (), .I1 (cnt[5]), .I2 (N694_inv), @@ -149733,9 +149711,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_6 ( - .COUT (_N14782), + .COUT (_N14740), .Z (N604[6]), - .CIN (_N14781), + .CIN (_N14739), .I0 (), .I1 (cnt[6]), .I2 (N694_inv), @@ -149753,9 +149731,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_7 ( - .COUT (_N14783), + .COUT (_N14741), .Z (N604[7]), - .CIN (_N14782), + .CIN (_N14740), .I0 (), .I1 (cnt[7]), .I2 (N694_inv), @@ -149773,9 +149751,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_8 ( - .COUT (_N14784), + .COUT (_N14742), .Z (N604[8]), - .CIN (_N14783), + .CIN (_N14741), .I0 (), .I1 (cnt[8]), .I2 (N694_inv), @@ -149795,7 +149773,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 N104_1_9 ( .COUT (), .Z (N604[9]), - .CIN (_N14784), + .CIN (_N14742), .I0 (), .I1 (cnt[9]), .I2 (N694_inv), @@ -150025,13 +150003,13 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .I1 (state_reg[2]), .I2 (state_reg[7]), .I3 (state_reg[10]), - .I4 (_N83291)); + .I4 (_N84859)); // LUT = (I0&I1)|(I0&I2)|(I0&I3)|(I0&I4) ; GTP_LUT4 /* \N247_1_1_or[0]_3 */ #( .INIT(16'b0001000100010000)) \N247_1_1_or[0]_3 ( - .Z (_N83291), + .Z (_N84859), .I0 (cnt[3]), .I1 (cnt[2]), .I2 (state_reg[5]), @@ -150060,7 +150038,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .I4_TO_CARRY("FALSE"), .I4_TO_LUT("FALSE")) N264_1_0 ( - .COUT (_N15016), + .COUT (_N17104), .Z (), .CIN (), .I0 (), @@ -150080,9 +150058,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N264_1_1 ( - .COUT (_N15017), + .COUT (_N17105), .Z (N608[1]), - .CIN (_N15016), + .CIN (_N17104), .I0 (), .I1 (left_margin[1]), .I2 (rdel_calibration), @@ -150100,9 +150078,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N264_1_2 ( - .COUT (_N15018), + .COUT (_N17106), .Z (N608[2]), - .CIN (_N15017), + .CIN (_N17105), .I0 (), .I1 (left_margin[2]), .I2 (rdel_calibration), @@ -150120,9 +150098,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N264_1_3 ( - .COUT (_N15019), + .COUT (_N17107), .Z (N608[3]), - .CIN (_N15018), + .CIN (_N17106), .I0 (), .I1 (left_margin[3]), .I2 (rdel_calibration), @@ -150140,9 +150118,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N264_1_4 ( - .COUT (_N15020), + .COUT (_N17108), .Z (N608[4]), - .CIN (_N15019), + .CIN (_N17107), .I0 (), .I1 (left_margin[4]), .I2 (rdel_calibration), @@ -150160,9 +150138,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N264_1_5 ( - .COUT (_N15021), + .COUT (_N17109), .Z (N608[5]), - .CIN (_N15020), + .CIN (_N17108), .I0 (), .I1 (left_margin[5]), .I2 (rdel_calibration), @@ -150180,9 +150158,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N264_1_6 ( - .COUT (_N15022), + .COUT (_N17110), .Z (N608[6]), - .CIN (_N15021), + .CIN (_N17109), .I0 (), .I1 (left_margin[6]), .I2 (rdel_calibration), @@ -150202,7 +150180,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 N264_1_7 ( .COUT (), .Z (N608[7]), - .CIN (_N15022), + .CIN (_N17110), .I0 (), .I1 (left_margin[7]), .I2 (rdel_calibration), @@ -150220,7 +150198,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .I4_TO_CARRY("FALSE"), .I4_TO_LUT("FALSE")) N280_1_0 ( - .COUT (_N15933), + .COUT (_N15080), .Z (), .CIN (), .I0 (), @@ -150240,9 +150218,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N280_1_1 ( - .COUT (_N15934), + .COUT (_N15081), .Z (N611[1]), - .CIN (_N15933), + .CIN (_N15080), .I0 (), .I1 (right_margin[1]), .I2 (rdel_calibration), @@ -150260,9 +150238,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N280_1_2 ( - .COUT (_N15935), + .COUT (_N15082), .Z (N611[2]), - .CIN (_N15934), + .CIN (_N15081), .I0 (), .I1 (right_margin[2]), .I2 (rdel_calibration), @@ -150280,9 +150258,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N280_1_3 ( - .COUT (_N15936), + .COUT (_N15083), .Z (N611[3]), - .CIN (_N15935), + .CIN (_N15082), .I0 (), .I1 (right_margin[3]), .I2 (rdel_calibration), @@ -150300,9 +150278,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N280_1_4 ( - .COUT (_N15937), + .COUT (_N15084), .Z (N611[4]), - .CIN (_N15936), + .CIN (_N15083), .I0 (), .I1 (right_margin[4]), .I2 (rdel_calibration), @@ -150320,9 +150298,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N280_1_5 ( - .COUT (_N15938), + .COUT (_N15085), .Z (N611[5]), - .CIN (_N15937), + .CIN (_N15084), .I0 (), .I1 (right_margin[5]), .I2 (rdel_calibration), @@ -150340,9 +150318,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N280_1_6 ( - .COUT (_N15939), + .COUT (_N15086), .Z (N611[6]), - .CIN (_N15938), + .CIN (_N15085), .I0 (), .I1 (right_margin[6]), .I2 (rdel_calibration), @@ -150362,7 +150340,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 N280_1_7 ( .COUT (), .Z (N611[7]), - .CIN (_N15939), + .CIN (_N15086), .I0 (), .I1 (right_margin[7]), .I2 (rdel_calibration), @@ -150380,7 +150358,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N285_1_1 ( - .COUT (_N14804), + .COUT (_N14760), .Z (N285[0]), .CIN (), .I0 (right_margin[0]), @@ -150400,9 +150378,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N285_1_2 ( - .COUT (_N14805), + .COUT (_N14761), .Z (N285[1]), - .CIN (_N14804), + .CIN (_N14760), .I0 (right_margin[0]), .I1 (left_margin[0]), .I2 (right_margin[1]), @@ -150420,9 +150398,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N285_1_3 ( - .COUT (_N14806), + .COUT (_N14762), .Z (N285[2]), - .CIN (_N14805), + .CIN (_N14761), .I0 (), .I1 (right_margin[2]), .I2 (left_margin[2]), @@ -150440,9 +150418,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N285_1_4 ( - .COUT (_N14807), + .COUT (_N14763), .Z (N285[3]), - .CIN (_N14806), + .CIN (_N14762), .I0 (), .I1 (right_margin[3]), .I2 (left_margin[3]), @@ -150460,9 +150438,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N285_1_5 ( - .COUT (_N14808), + .COUT (_N14764), .Z (N285[4]), - .CIN (_N14807), + .CIN (_N14763), .I0 (), .I1 (right_margin[4]), .I2 (left_margin[4]), @@ -150480,9 +150458,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N285_1_6 ( - .COUT (_N14809), + .COUT (_N14765), .Z (N285[5]), - .CIN (_N14808), + .CIN (_N14764), .I0 (), .I1 (right_margin[5]), .I2 (left_margin[5]), @@ -150500,9 +150478,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N285_1_7 ( - .COUT (_N14810), + .COUT (_N14766), .Z (N285[6]), - .CIN (_N14809), + .CIN (_N14765), .I0 (), .I1 (right_margin[6]), .I2 (left_margin[6]), @@ -150520,9 +150498,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N285_1_8 ( - .COUT (_N14811), + .COUT (_N14767), .Z (N285[7]), - .CIN (_N14810), + .CIN (_N14766), .I0 (), .I1 (right_margin[7]), .I2 (left_margin[7]), @@ -150542,7 +150520,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 N285_1_9 ( .COUT (), .Z (N285[8]), - .CIN (_N14811), + .CIN (_N14767), .I0 (), .I1 (), .I2 (), @@ -150556,7 +150534,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 GTP_LUT3 /* N295_mux2 */ #( .INIT(8'b00011111)) N295_mux2 ( - .Z (_N5735), + .Z (_N5725), .I0 (samp_win_size[1]), .I1 (samp_win_size[2]), .I2 (samp_win_size[3])); @@ -150583,10 +150561,18 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .I4 (state_reg[10])); // LUT = (I0)|(I1)|(I2)|(I3)|(I4) ; + GTP_LUT2 /* N446_1 */ #( + .INIT(4'b1110)) + N446_1 ( + .Z (N603), + .I0 (state_reg[1]), + .I1 (state_reg[6])); + // LUT = (I0)|(I1) ; + GTP_LUT4 /* \N451_and[0][2] */ #( .INIT(16'b1010101010101000)) \N451_and[0][2] ( - .Z (_N30276), + .Z (_N30395), .I0 (default_samp_position[7]), .I1 (state_reg[1]), .I2 (state_reg[6]), @@ -150596,7 +150582,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 GTP_LUT5M /* N564_20_3 */ #( .INIT(32'b10101010100010001111111111111110)) N564_20_3 ( - .Z (_N106676), + .Z (_N107488), .I0 (rdel_move_en), .I1 (state_reg[5]), .I2 (state_reg[6]), @@ -150608,11 +150594,11 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 GTP_LUT5M /* N564_20_4 */ #( .INIT(32'b11111111101010101111111100000100)) N564_20_4 ( - .Z (_N106677), + .Z (_N107489), .I0 (state_reg[11]), .I1 (state_reg[0]), .I2 (reinit_adj_rdel), - .I3 (_N88151), + .I3 (_N88943), .I4 (rdel_calibration), .ID (init_adj_rdel)); // LUT = (~ID&I1&~I2&~I4)|(I0&I4)|(I3) ; @@ -150620,11 +150606,11 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 GTP_LUT5M /* N564_20_7 */ #( .INIT(32'b11111111111110001111111111111110)) N564_20_7 ( - .Z (_N106680), + .Z (_N107492), .I0 (rdel_move_en), .I1 (state_reg[7]), - .I2 (_N106676), - .I3 (_N106677), + .I2 (_N107488), + .I3 (_N107489), .I4 (N108), .ID (state_reg[2])); // LUT = (I1&~I4)|(ID&~I4)|(I3)|(I2)|(I0&I1) ; @@ -150632,20 +150618,12 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 GTP_LUT3 /* N564_25 */ #( .INIT(8'b01010100)) N564_25 ( - .Z (_N88151), + .Z (_N88943), .I0 (rdel_move_en), .I1 (state_reg[4]), .I2 (state_reg[8])); // LUT = (~I0&I1)|(~I0&I2) ; - GTP_LUT2 /* N564_35 */ #( - .INIT(4'b1110)) - N564_35 ( - .Z (N603), - .I0 (state_reg[1]), - .I1 (state_reg[6])); - // LUT = (I0)|(I1) ; - GTP_LUT4 /* N570 */ #( .INIT(16'b0000000001001111)) N570_vname ( @@ -150653,14 +150631,14 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .I0 (rdel_move_en), .I1 (N167), .I2 (state_reg[10]), - .I3 (_N106680)); + .I3 (_N107492)); // defparam N570_vname.orig_name = N570; // LUT = (~I2&~I3)|(~I0&I1&~I3) ; GTP_LUT5 /* N598_1_2 */ #( .INIT(32'b11111111111111111111111111111110)) N598_1_2 ( - .Z (_N106626), + .Z (_N107438), .I0 (state_reg[0]), .I1 (state_reg[1]), .I2 (state_reg[4]), @@ -150671,12 +150649,12 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 GTP_LUT5 /* N598_1_4 */ #( .INIT(32'b11111111111111110111001101010000)) N598_1_4 ( - .Z (_N106628), + .Z (_N107440), .I0 (cnt[3]), .I1 (N108), .I2 (N679), .I3 (state_reg[7]), - .I4 (_N106626)); + .I4 (_N107438)); // LUT = (I4)|(~I1&I3)|(~I0&I2) ; GTP_LUT5 /* N598_1_6 */ #( @@ -150687,7 +150665,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .I1 (N167), .I2 (state_reg[2]), .I3 (state_reg[10]), - .I4 (_N106628)); + .I4 (_N107440)); // LUT = (I4)|(~I1&I3)|(~I0&I2) ; GTP_LUT2 /* \N604_1[0]_1 */ #( @@ -150748,7 +150726,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 GTP_LUT4 /* N614_1_4 */ #( .INIT(16'b0000000000000001)) N614_1_4 ( - .Z (_N106524), + .Z (_N107342), .I0 (samp_win_size[4]), .I1 (samp_win_size[5]), .I2 (samp_win_size[6]), @@ -150758,7 +150736,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 GTP_LUT4 /* N621_1_2 */ #( .INIT(16'b1110111011101010)) N621_1_2 ( - .Z (_N106558), + .Z (_N107376), .I0 (rdel_calib_done), .I1 (cnt[3]), .I2 (state_reg[5]), @@ -150773,7 +150751,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .I1 (N167), .I2 (state_reg[7]), .I3 (state_reg[10]), - .I4 (_N106558)); + .I4 (_N107376)); // LUT = (I4)|(I0&I2)|(I1&I3) ; GTP_LUT5 /* N694_inv */ #( @@ -150795,14 +150773,14 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .Q (adj_rdel_done), .C (N0), .CLK (ddrphy_clkin), - .D (_N103401)); + .D (_N104213)); // defparam adj_rdel_done_vname.orig_name = adj_rdel_done; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqsi_rdel_cal_v1_2.vp:660 GTP_LUT5 /* adj_rdel_done_ce_mux */ #( .INIT(32'b11111111111000001110000011100000)) adj_rdel_done_ce_mux ( - .Z (_N103401), + .Z (_N104213), .I0 (init_adj_rdel), .I1 (reinit_adj_rdel), .I2 (adj_rdel_done), @@ -151026,17 +151004,17 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .Q (rdel_calib_error), .C (N0), .CLK (ddrphy_clkin), - .D (_N103400)); + .D (_N104212)); // defparam rdel_calib_error_vname.orig_name = rdel_calib_error; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqsi_rdel_cal_v1_2.vp:650 GTP_LUT5M /* rdel_calib_error_ce_mux */ #( .INIT(32'b00100000101000000010001010101010)) rdel_calib_error_ce_mux ( - .Z (_N103400), - .I0 (_N106524), + .Z (_N104212), + .I0 (_N107342), .I1 (state_reg[0]), - .I2 (_N5735), + .I2 (_N5725), .I3 (rdel_calibration), .I4 (state_reg[11]), .ID (rdel_calib_error)); @@ -151069,18 +151047,18 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .Q (rdel_ctrl_wire[2]), .C (N0), .CLK (ddrphy_clkin), - .D (_N103399)); + .D (_N104211)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqsi_rdel_cal_v1_2.vp:564 GTP_LUT5 /* \rdel_ctrl_ce_mux[2] */ #( .INIT(32'b11101110111011101110111011100010)) \rdel_ctrl_ce_mux[2] ( - .Z (_N103399), + .Z (_N104211), .I0 (rdel_ctrl_wire[2]), .I1 (N446), .I2 (state_reg[5]), .I3 (state_reg[10]), - .I4 (_N30276)); + .I4 (_N30395)); // LUT = (I0&~I1)|(I1&I2)|(I1&I3)|(I1&I4) ; GTP_DFF_C /* rdel_move_done */ #( @@ -151141,14 +151119,14 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .Q (rdel_ov_sync), .C (N0), .CLK (ddrphy_clkin), - .D (_N103398)); + .D (_N104210)); // defparam rdel_ov_sync_vname.orig_name = rdel_ov_sync; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqsi_rdel_cal_v1_2.vp:369 GTP_LUT3 /* rdel_ov_sync_ce_mux */ #( .INIT(8'b11101000)) rdel_ov_sync_ce_mux ( - .Z (_N103398), + .Z (_N104210), .I0 (rdel_ov_d[3]), .I1 (rdel_ov_d[2]), .I2 (rdel_ov_sync)); @@ -151262,16 +151240,13 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 // LUT = (I0&I2)|(I1&I2) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqsi_rdel_cal_v1_2.vp:459 - GTP_LUT5 /* \state_fsm[3:0]_135 */ #( - .INIT(32'b10010000000000000000000000000000)) + GTP_LUT2 /* \state_fsm[3:0]_135 */ #( + .INIT(4'b1000)) \state_fsm[3:0]_135 ( .Z (_N134), - .I0 (default_samp_position[1]), - .I1 (cnt[3]), - .I2 (_N83022), - .I3 (state_reg[2]), - .I4 (_N106624)); - // LUT = (~I0&~I1&I2&I3&I4)|(I0&I1&I2&I3&I4) ; + .I0 (state_reg[2]), + .I1 (_N96939)); + // LUT = I0&I1 ; GTP_LUT5 /* \state_fsm[3:0]_139 */ #( .INIT(32'b11011100010100001100110000000000)) @@ -151313,7 +151288,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 .I1 (cnt[3]), .I2 (state_reg[7]), .I3 (state_reg[9]), - .I4 (_N96160)); + .I4 (_N96939)); // LUT = (~I0&I1&I3)|(~I0&I2&I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqsi_rdel_cal_v1_2.vp:459 @@ -151340,7 +151315,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 GTP_LUT5 /* \state_fsm[3:0]_540_4 */ #( .INIT(32'b11111101111111101111111111111111)) \state_fsm[3:0]_540_4 ( - .Z (_N106518), + .Z (_N107336), .I0 (cnt[8]), .I1 (cnt[1]), .I2 (cnt[0]), @@ -151351,7 +151326,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 GTP_LUT4 /* \state_fsm[3:0]_542_2 */ #( .INIT(16'b1000010000100001)) \state_fsm[3:0]_542_2 ( - .Z (_N106513), + .Z (_N107331), .I0 (cnt[3]), .I1 (cnt[2]), .I2 (total_margin_div2[1]), @@ -151361,65 +151336,24 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 GTP_LUT5 /* \state_fsm[3:0]_542_4 */ #( .INIT(32'b10000100001000010000000000000000)) \state_fsm[3:0]_542_4 ( - .Z (_N81414_3), + .Z (_N82187_3), .I0 (cnt[5]), .I1 (cnt[4]), .I2 (total_margin_div2[3]), .I3 (total_margin_div2[2]), - .I4 (_N106513)); + .I4 (_N107331)); // LUT = (~I0&~I1&~I2&~I3&I4)|(I0&~I1&I2&~I3&I4)|(~I0&I1&~I2&I3&I4)|(I0&I1&I2&I3&I4) ; GTP_LUT4 /* \state_fsm[3:0]_544 */ #( .INIT(16'b1000010000100001)) \state_fsm[3:0]_544 ( - .Z (_N81414_5), + .Z (_N82187_5), .I0 (cnt[7]), .I1 (cnt[6]), .I2 (total_margin_div2[5]), .I3 (total_margin_div2[4])); // LUT = (~I0&~I1&~I2&~I3)|(I0&~I1&I2&~I3)|(~I0&I1&~I2&I3)|(I0&I1&I2&I3) ; - GTP_LUT4 /* \state_fsm[3:0]_3419 */ #( - .INIT(16'b1000110000100011)) - \state_fsm[3:0]_3419 ( - .Z (_N106611), - .I0 (default_samp_position[4]), - .I1 (default_samp_position[0]), - .I2 (cnt[6]), - .I3 (cnt[2])); - // LUT = (~I1&~I2&~I3)|(I0&~I1&~I3)|(I1&~I2&I3)|(I0&I1&I3) ; - - GTP_LUT4 /* \state_fsm[3:0]_3422 */ #( - .INIT(16'b1010010100100001)) - \state_fsm[3:0]_3422 ( - .Z (_N106614), - .I0 (default_samp_position[6]), - .I1 (default_samp_position[4]), - .I2 (cnt[8]), - .I3 (cnt[6])); - // LUT = (~I0&~I1&~I2)|(~I0&~I2&I3)|(I0&~I1&I2)|(I0&I2&I3) ; - - GTP_LUT4 /* \state_fsm[3:0]_3424 */ #( - .INIT(16'b1000010000100001)) - \state_fsm[3:0]_3424 ( - .Z (_N106616), - .I0 (default_samp_position[3]), - .I1 (default_samp_position[2]), - .I2 (cnt[5]), - .I3 (cnt[4])); - // LUT = (~I0&~I1&~I2&~I3)|(I0&~I1&I2&~I3)|(~I0&I1&~I2&I3)|(I0&I1&I2&I3) ; - - GTP_LUT5 /* \state_fsm[3:0]_3426 */ #( - .INIT(32'b10010000000000000000000000000000)) - \state_fsm[3:0]_3426 ( - .Z (_N83022), - .I0 (default_samp_position[5]), - .I1 (cnt[7]), - .I2 (_N106611), - .I3 (_N106614), - .I4 (_N106616)); - // LUT = (~I0&~I1&I2&I3&I4)|(I0&I1&I2&I3&I4) ; - (* syn_encoding="onehot" *) GTP_DFF_PE /* \state_reg[0] */ #( .GRS_EN("TRUE"), .INIT(1'b1)) @@ -151715,32 +151649,26 @@ module ipsxb_ddrphy_data_slice_v1_4_unq10 input [3:0] \data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r1 , input [3:0] \data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r2 , input [3:0] \data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r3 , - input [4:0] \data_slice_wrlvl/N484 , input [7:0] dll_step, input [29:0] \dqsi_rdel_cal/N734 , input [7:0] \dqsi_rdel_cal/default_samp_position , input [4:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt , - input [6:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg , input [4:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt , - input [6:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg , input [4:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt , + input [6:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg , input [31:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/phy_wrdata_mask , input [3:0] \wdata_path_adj/phy_wrdata_en_r2 , input [3:0] \wdata_path_adj/phy_wrdata_en_slip4 , - input _N96109, - input _N96120, - input _N96124, - input _N96160, - input _N96886, - input _N106288, - input _N106303, - input _N106624, + input _N96887, + input _N96902, + input _N96939, + input _N97663, input \data_slice_dqs_gate_cal/gatecal/N1 , - input \data_slice_wrlvl/N449 , input ddrphy_clkin, input ddrphy_dqs_rst, input ddrphy_dqs_training_rstn, input ddrphy_ioclk, + input \dqs_rddata_align/_N11 , input \dqsi_rdel_cal/_N538 , input \dqsi_rdel_cal/rdel_calibration_d , input \dqsi_rdel_cal/rdel_calibration_rising , @@ -151752,9 +151680,7 @@ module ipsxb_ddrphy_data_slice_v1_4_unq10 input rdel_calibration, input rdel_move_en, input reinit_adj_rdel, - input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld , - input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wrlvl_dqs_en , - input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld , + input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N165 , input wrlvl_ck_dly_done, input wrlvl_ck_dly_start, input wrlvl_dqs_req, @@ -151766,25 +151692,19 @@ module ipsxb_ddrphy_data_slice_v1_4_unq10 output [5:0] \data_slice_dqs_gate_cal/gatecal/gate_state_reg , output [4:0] \data_slice_wrlvl/cnt , output [6:0] \data_slice_wrlvl/wl_state_reg , + output [5:0] \dqs_rddata_align/gdet_state_reg , output [9:0] \dqsi_rdel_cal/cnt , output [7:0] \dqsi_rdel_cal/total_margin_div2 , output [63:0] read_data, - output [4:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484 , - output _N81414_3, - output _N81414_5, - output _N83022, - output _N96271, - output _N96272, - output _N96274, - output _N96318, - output _N96883, - output _N105949, - output _N106218, - output _N106518, + output [4:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484 , + output _N82187_3, + output _N82187_5, + output _N97033, + output _N106767, + output _N107336, output adj_rdel_done, output ck_check_done, output \data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r , - output \data_slice_wrlvl/dq_vld , output dm, output dqs_gate_vld, output gate_adj_done, @@ -151796,9 +151716,8 @@ module ipsxb_ddrphy_data_slice_v1_4_unq10 output rdel_calib_error, output rdel_move_done, output read_valid, - output \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N449 , + output \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N449 , output wrlvl_ck_dly_flag, - output wrlvl_dqs_en, output wrlvl_dqs_resp, output wrlvl_error, inout [7:0] dq, @@ -151835,6 +151754,7 @@ module ipsxb_ddrphy_data_slice_v1_4_unq10 (* PAP_TIM_MASK_CLOCK_ATTR="TRUE" *) wire wclk; (* PAP_TIM_MASK_CLOCK_ATTR="TRUE" *) wire wclk_del; wire wrlvl_dqs; + wire wrlvl_dqs_en; wire \data_slice_dqs_gate_cal_dqs_gate_coarse_cal/dqs_gate_pulse_r4[0]_floating ; wire \data_slice_dqs_gate_cal_dqs_gate_coarse_cal/dqs_gate_pulse_r4[1]_floating ; wire \data_slice_dqs_gate_cal_dqs_gate_coarse_cal/dqs_gate_pulse_r4[2]_floating ; @@ -151844,10 +151764,11 @@ module ipsxb_ddrphy_data_slice_v1_4_unq10 wire \data_slice_dqs_gate_cal_gatecal/gate_state_reg[4]_floating ; wire \data_slice_dqs_gate_cal_gatecal/gate_state_reg[5]_floating ; wire \data_slice_dqs_gate_cal_read_clk_ctrl[2]_floating ; - wire \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484[0]_floating ; - wire \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484[1]_floating ; - wire \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484[2]_floating ; - wire \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484[3]_floating ; + wire \data_slice_wrlvl_cnt[1]_floating ; + wire \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484[0]_floating ; + wire \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484[1]_floating ; + wire \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484[2]_floating ; + wire \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484[3]_floating ; wire \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/adj_wrdqs[0]_floating ; wire \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/adj_wrdqs[1]_floating ; wire \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/adj_wrdqs[3]_floating ; @@ -151861,12 +151782,11 @@ module ipsxb_ddrphy_data_slice_v1_4_unq10 wire \data_slice_wrlvl_wl_state_reg[3]_floating ; wire \data_slice_wrlvl_wl_state_reg[5]_floating ; wire \data_slice_wrlvl_wl_state_reg[6]_floating ; - wire \dqsi_rdel_cal_cnt[2]_floating ; - wire \dqsi_rdel_cal_cnt[4]_floating ; - wire \dqsi_rdel_cal_cnt[5]_floating ; - wire \dqsi_rdel_cal_cnt[6]_floating ; - wire \dqsi_rdel_cal_cnt[7]_floating ; - wire \dqsi_rdel_cal_cnt[8]_floating ; + wire \dqs_rddata_align_gdet_state_reg[1]_floating ; + wire \dqs_rddata_align_gdet_state_reg[2]_floating ; + wire \dqs_rddata_align_gdet_state_reg[3]_floating ; + wire \dqs_rddata_align_gdet_state_reg[4]_floating ; + wire \dqs_rddata_align_gdet_state_reg[5]_floating ; wire \dqsi_rdel_cal_total_margin_div2[0]_floating ; wire \dqsi_rdel_cal_total_margin_div2[1]_floating ; wire \dqsi_rdel_cal_total_margin_div2[2]_floating ; @@ -151902,7 +151822,7 @@ module ipsxb_ddrphy_data_slice_v1_4_unq10 .gate_check_error (gate_check_error), .gate_check_pass (gate_check_pass), .\gatecal/dqs_gate_vld_r (\data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r ), - ._N96109 (_N96109), + ._N96887 (_N96887), .ddrphy_clkin (ddrphy_clkin), .dqs_gate_check_pass (dqs_gate_check_pass), .gate_check (gate_check), @@ -151913,45 +151833,31 @@ module ipsxb_ddrphy_data_slice_v1_4_unq10 // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_v1_4.vp:546 ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq10 data_slice_wrlvl ( - .cnt ({\data_slice_wrlvl/cnt [4] , \data_slice_wrlvl/cnt [3] , \data_slice_wrlvl/cnt [2] , \data_slice_wrlvl/cnt [1] , \data_slice_wrlvl/cnt [0] }), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484 ({\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484 [4] , \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484[3]_floating , \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484[2]_floating , \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484[1]_floating , \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484[0]_floating }), + .cnt ({\data_slice_wrlvl/cnt [4] , \data_slice_wrlvl/cnt [3] , \data_slice_wrlvl/cnt [2] , \data_slice_wrlvl_cnt[1]_floating , \data_slice_wrlvl/cnt [0] }), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484 ({\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484 [4] , \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484[3]_floating , \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484[2]_floating , \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484[1]_floating , \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484[0]_floating }), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/adj_wrdqs ({\data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/adj_wrdqs[7]_floating , \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/adj_wrdqs[6]_floating , \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/adj_wrdqs[5]_floating , \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/adj_wrdqs[4]_floating , \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/adj_wrdqs[3]_floating , adj_wrdqs[2], \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/adj_wrdqs[1]_floating , \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/adj_wrdqs[0]_floating }), .wl_state_reg ({\data_slice_wrlvl_wl_state_reg[6]_floating , \data_slice_wrlvl_wl_state_reg[5]_floating , \data_slice_wrlvl/wl_state_reg [4] , \data_slice_wrlvl_wl_state_reg[3]_floating , \data_slice_wrlvl_wl_state_reg[2]_floating , \data_slice_wrlvl_wl_state_reg[1]_floating , \data_slice_wrlvl_wl_state_reg[0]_floating }), .wrlvl_step ({debug_data[33], debug_data[32], debug_data[31], debug_data[30], debug_data[29], debug_data[28], debug_data[27], debug_data[26]}), - .N484 ({\data_slice_wrlvl/N484 [4] , 1'bx, 1'bx, 1'bx, 1'bx}), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt ({\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [4] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [1] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [0] }), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg ({1'bx, 1'bx, \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg [4] , 1'bx, 1'bx, 1'bx, 1'bx}), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt ({\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [4] , 1'bx, \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] , 1'bx, 1'bx}), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt ({\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [4] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [1] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [0] }), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg ({1'bx, 1'bx, \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg [4] , 1'bx, 1'bx, 1'bx, 1'bx}), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_in_dly (dq_in_dly), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt ({\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [4] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [1] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [0] }), - ._N96271 (_N96271), - ._N96272 (_N96272), - ._N96274 (_N96274), - ._N96318 (_N96318), - ._N96883 (_N96883), - ._N105949 (_N105949), - ._N106218 (_N106218), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg ({1'bx, 1'bx, \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg [4] , 1'bx, 1'bx, 1'bx, 1'bx}), + ._N97033 (_N97033), + ._N106767 (_N106767), .ck_check_done (ck_check_done), .ddrphy_gatei (ddrphy_gatei), - .dq_vld (\data_slice_wrlvl/dq_vld ), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N449 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N449 ), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N449 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N449 ), .wrlvl_ck_dly_flag (wrlvl_ck_dly_flag), .wrlvl_dqs (wrlvl_dqs), .wrlvl_dqs_en (wrlvl_dqs_en), .wrlvl_dqs_resp (wrlvl_dqs_resp), .wrlvl_error (wrlvl_error), .N0 (\data_slice_dqs_gate_cal/gatecal/N1 ), - .N449 (\data_slice_wrlvl/N449 ), - ._N96120 (_N96120), - ._N96124 (_N96124), - ._N96886 (_N96886), - ._N106288 (_N106288), - ._N106303 (_N106303), + ._N96902 (_N96902), + ._N97663 (_N97663), .ddrphy_clkin (ddrphy_clkin), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld ), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wrlvl_dqs_en (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wrlvl_dqs_en ), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld ), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N165 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N165 ), .wrlvl_ck_dly_done (wrlvl_ck_dly_done), .wrlvl_ck_dly_start (wrlvl_ck_dly_start), .wrlvl_dqs_req (wrlvl_dqs_req)); @@ -152406,6 +152312,7 @@ module ipsxb_ddrphy_data_slice_v1_4_unq10 // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_v1_4.vp:740 ipsxb_ddrphy_dqs_rddata_align_v1_3_unq10 dqs_rddata_align ( + .gdet_state_reg ({\dqs_rddata_align_gdet_state_reg[5]_floating , \dqs_rddata_align_gdet_state_reg[4]_floating , \dqs_rddata_align_gdet_state_reg[3]_floating , \dqs_rddata_align_gdet_state_reg[2]_floating , \dqs_rddata_align_gdet_state_reg[1]_floating , \dqs_rddata_align/gdet_state_reg [0] }), .read_data (read_data), .ddrphy_rdata (ddrphy_rdata), .dqs_gate_check_pass (dqs_gate_check_pass), @@ -152414,6 +152321,7 @@ module ipsxb_ddrphy_data_slice_v1_4_unq10 .rdel_rvalid (read_data_valid), .read_valid (read_valid), .N0 (\data_slice_dqs_gate_cal/gatecal/N1 ), + ._N11 (\dqs_rddata_align/_N11 ), .ddrphy_clkin (ddrphy_clkin), .ddrphy_read_valid (ddrphy_read_valid), .dqs_gate_vld (dqs_gate_vld), @@ -152422,23 +152330,21 @@ module ipsxb_ddrphy_data_slice_v1_4_unq10 // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_v1_4.vp:613 ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq10 dqsi_rdel_cal ( - .cnt ({\dqsi_rdel_cal/cnt [9] , \dqsi_rdel_cal_cnt[8]_floating , \dqsi_rdel_cal_cnt[7]_floating , \dqsi_rdel_cal_cnt[6]_floating , \dqsi_rdel_cal_cnt[5]_floating , \dqsi_rdel_cal_cnt[4]_floating , \dqsi_rdel_cal/cnt [3] , \dqsi_rdel_cal_cnt[2]_floating , \dqsi_rdel_cal/cnt [1] , \dqsi_rdel_cal/cnt [0] }), + .cnt ({\dqsi_rdel_cal/cnt [9] , \dqsi_rdel_cal/cnt [8] , \dqsi_rdel_cal/cnt [7] , \dqsi_rdel_cal/cnt [6] , \dqsi_rdel_cal/cnt [5] , \dqsi_rdel_cal/cnt [4] , \dqsi_rdel_cal/cnt [3] , \dqsi_rdel_cal/cnt [2] , \dqsi_rdel_cal/cnt [1] , \dqsi_rdel_cal/cnt [0] }), .rdel_ctrl_wire (rdel_ctrl), .total_margin_div2 ({\dqsi_rdel_cal/total_margin_div2 [7] , \dqsi_rdel_cal_total_margin_div2[6]_floating , \dqsi_rdel_cal_total_margin_div2[5]_floating , \dqsi_rdel_cal_total_margin_div2[4]_floating , \dqsi_rdel_cal_total_margin_div2[3]_floating , \dqsi_rdel_cal_total_margin_div2[2]_floating , \dqsi_rdel_cal_total_margin_div2[1]_floating , \dqsi_rdel_cal_total_margin_div2[0]_floating }), .N734 ({1'bx, 1'bx, 1'bx, \dqsi_rdel_cal/N734 [26] , 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), .default_samp_position ({\dqsi_rdel_cal/default_samp_position [7] , \dqsi_rdel_cal/default_samp_position [6] , \dqsi_rdel_cal/default_samp_position [5] , \dqsi_rdel_cal/default_samp_position [4] , \dqsi_rdel_cal/default_samp_position [3] , \dqsi_rdel_cal/default_samp_position [2] , \dqsi_rdel_cal/default_samp_position [1] , \dqsi_rdel_cal/default_samp_position [0] }), - ._N81414_3 (_N81414_3), - ._N81414_5 (_N81414_5), - ._N83022 (_N83022), - ._N106518 (_N106518), + ._N82187_3 (_N82187_3), + ._N82187_5 (_N82187_5), + ._N107336 (_N107336), .adj_rdel_done (adj_rdel_done), .rdel_calib_done (rdel_calib_done), .rdel_calib_error (rdel_calib_error), .rdel_move_done (rdel_move_done), .N0 (\data_slice_dqs_gate_cal/gatecal/N1 ), ._N538 (\dqsi_rdel_cal/_N538 ), - ._N96160 (_N96160), - ._N106624 (_N106624), + ._N96939 (_N96939), .ddrphy_clkin (ddrphy_clkin), .init_adj_rdel (init_adj_rdel), .rdel_calibration (rdel_calibration), @@ -152590,21 +152496,21 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq12 wire N194_inv; wire N213; wire [4:0] N227; - wire _N5851; - wire _N23998; - wire _N24000; - wire _N24002; - wire _N24003; - wire _N24004; - wire _N24005; - wire _N24014; - wire _N24016; - wire _N24030; - wire _N24032; - wire _N24033; - wire _N95791; - wire _N96708; - wire _N103422; + wire _N5877; + wire _N23777; + wire _N23779; + wire _N23781; + wire _N23782; + wire _N23783; + wire _N23784; + wire _N23793; + wire _N23795; + wire _N23809; + wire _N23811; + wire _N23812; + wire _N96571; + wire _N97476; + wire _N104234; wire [4:0] cnt; wire [3:0] dqs_gate_pulse_src_nxt; wire [3:0] dqs_gate_pulse_src_nxt_r; @@ -152613,7 +152519,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq12 GTP_LUT3 /* N144_ac2 */ #( .INIT(8'b10000000)) N144_ac2 ( - .Z (_N5851), + .Z (_N5877), .I0 (cnt[0]), .I1 (cnt[1]), .I2 (cnt[2])); @@ -152632,7 +152538,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq12 GTP_LUT5 /* N205_1_5 */ #( .INIT(32'b00000000000000000000010000000000)) N205_1_5 ( - .Z (_N95791), + .Z (_N96571), .I0 (cnt[0]), .I1 (cnt[1]), .I2 (cnt[2]), @@ -152647,7 +152553,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq12 .I0 (gatecal_start), .I1 (rddata_cal), .I2 (N194_inv), - .I3 (_N95791)); + .I3 (_N96571)); // LUT = (I2)|(I3)|(~I0&~I1) ; GTP_LUT5 /* \N227[0]_1 */ #( @@ -152658,7 +152564,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq12 .I1 (rddata_cal), .I2 (cnt[0]), .I3 (N194_inv), - .I4 (_N95791)); + .I4 (_N96571)); // LUT = (I0&~I2&~I3&~I4)|(I1&~I2&~I3&~I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3.vp:346 @@ -152699,7 +152605,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq12 .INIT(16'b0001001100100000)) \N227[4]_1 ( .Z (N227[4]), - .I0 (_N5851), + .I0 (_N5877), .I1 (N213), .I2 (cnt[3]), .I3 (cnt[4])); @@ -152712,7 +152618,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq12 .Z (dqs_gate_pulse_src_nxt[2]), .I0 (read_en_slipped[2]), .I1 (read_en_slipped[3]), - .I2 (_N96708)); + .I2 (_N97476)); // LUT = ~I0&I1&~I2 ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3.vp:255 @@ -152722,7 +152628,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq12 .Z (dqs_gate_pulse_src[3]), .I0 (read_en_slipped[2]), .I1 (read_en_slipped[3]), - .I2 (_N96708)); + .I2 (_N97476)); // LUT = (I0)|(I1)|(I2) ; GTP_LUT4 /* N261_inv */ #( @@ -152732,7 +152638,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq12 .I0 (read_en_slipped[0]), .I1 (read_en_slipped[2]), .I2 (read_en_slipped[3]), - .I3 (_N96708)); + .I3 (_N97476)); // LUT = (~I0&I1)|(~I0&I2)|(~I0&I3) ; GTP_DFF_C /* \cnt[0] */ #( @@ -152968,16 +152874,16 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq12 \dqs_gate_pulse_src_4[1] ( .Z (dqs_gate_pulse_src[1]), .I0 (dqs_gate_pulse_src_nxt_r[1]), - .I1 (_N96708)); + .I1 (_N97476)); // LUT = (I0)|(I1) ; GTP_LUT4 /* \dqs_gate_pulse_src_4[1]_1 */ #( .INIT(16'b1111111111011000)) \dqs_gate_pulse_src_4[1]_1 ( - .Z (_N96708), + .Z (_N97476), .I0 (coarse_slip_step[1]), - .I1 (_N24003), - .I2 (_N24005), + .I1 (_N23782), + .I2 (_N23784), .I3 (read_en_slipped[0])); // LUT = (I3)|(~I0&I2)|(I0&I1) ; @@ -152987,7 +152893,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq12 .Z (dqs_gate_pulse_src[2]), .I0 (dqs_gate_pulse_src_nxt_r[2]), .I1 (read_en_slipped[2]), - .I2 (_N96708)); + .I2 (_N97476)); // LUT = (I0)|(I1)|(I2) ; GTP_LUT3 /* dqs_gate_pulse_src_nxt_4 */ #( @@ -152996,7 +152902,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq12 .Z (dqs_gate_pulse_src_nxt[1]), .I0 (read_en_slipped[2]), .I1 (read_en_slipped[3]), - .I2 (_N96708)); + .I2 (_N97476)); // LUT = (I0&~I2)|(I1&~I2) ; GTP_DFF_C /* \dqs_gate_pulse_src_nxt_r[0] */ #( @@ -153036,25 +152942,25 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq12 .Q (dqs_gate_vld), .C (N1), .CLK (ddrphy_clkin), - .D (_N103422)); + .D (_N104234)); // defparam dqs_gate_vld_vname.orig_name = dqs_gate_vld; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3.vp:346 GTP_LUT5 /* dqs_gate_vld_ce_mux */ #( .INIT(32'b11101110000000001110111011100000)) dqs_gate_vld_ce_mux ( - .Z (_N103422), + .Z (_N104234), .I0 (gatecal_start), .I1 (rddata_cal), .I2 (dqs_gate_vld), .I3 (N194_inv), - .I4 (_N95791)); + .I4 (_N96571)); // LUT = (I0&I3)|(I1&I3)|(I0&I2&~I4)|(I1&I2&~I4) ; GTP_LUT4 /* \read_en_slipped_5[0] */ #( .INIT(16'b0101010000010000)) \read_en_slipped_5[0] ( - .Z (_N23998), + .Z (_N23777), .I0 (coarse_slip_step[0]), .I1 (coarse_slip_step[3]), .I2 (read_cmd_mux_r1[2]), @@ -153064,7 +152970,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq12 GTP_LUT4 /* \read_en_slipped_5[2]_1 */ #( .INIT(16'b0101010000010000)) \read_en_slipped_5[2]_1 ( - .Z (_N24000), + .Z (_N23779), .I0 (coarse_slip_step[0]), .I1 (coarse_slip_step[3]), .I2 (read_cmd_mux[0]), @@ -153074,19 +152980,19 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq12 GTP_LUT5M /* \read_en_slipped_6[0] */ #( .INIT(32'b10001000101110001010101010101010)) \read_en_slipped_6[0] ( - .Z (_N24002), + .Z (_N23781), .I0 (read_cmd_mux[0]), .I1 (coarse_slip_step[3]), .I2 (read_cmd_mux_r2[2]), .I3 (coarse_slip_step[0]), .I4 (coarse_slip_step[2]), - .ID (_N23998)); + .ID (_N23777)); // LUT = (ID&~I4)|(~I1&I2&~I3&I4)|(I0&I1&I4) ; GTP_LUT5M /* \read_en_slipped_6[1] */ #( .INIT(32'b00001000000010001100100000001000)) \read_en_slipped_6[1] ( - .Z (_N24003), + .Z (_N23782), .I0 (read_cmd_mux_r2[2]), .I1 (coarse_slip_step[0]), .I2 (coarse_slip_step[3]), @@ -153098,19 +153004,19 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq12 GTP_LUT5M /* \read_en_slipped_6[2] */ #( .INIT(32'b11001100010100001010101010101010)) \read_en_slipped_6[2] ( - .Z (_N24004), + .Z (_N23783), .I0 (coarse_slip_step[0]), .I1 (read_cmd_mux[2]), .I2 (read_cmd_mux_r1[0]), .I3 (coarse_slip_step[3]), .I4 (coarse_slip_step[2]), - .ID (_N24000)); + .ID (_N23779)); // LUT = (ID&~I4)|(~I0&I2&~I3&I4)|(I1&I3&I4) ; GTP_LUT5M /* \read_en_slipped_6[3]_1 */ #( .INIT(32'b00001000000010001100100000001000)) \read_en_slipped_6[3]_1 ( - .Z (_N24005), + .Z (_N23784), .I0 (read_cmd_mux_r1[0]), .I1 (coarse_slip_step[0]), .I2 (coarse_slip_step[3]), @@ -153122,7 +153028,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq12 GTP_LUT5 /* \read_en_slipped_9[0] */ #( .INIT(32'b11010101110001001001000110000000)) \read_en_slipped_9[0] ( - .Z (_N24014), + .Z (_N23793), .I0 (coarse_slip_step[0]), .I1 (coarse_slip_step[3]), .I2 (read_cmd_mux[0]), @@ -153133,7 +153039,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq12 GTP_LUT5 /* \read_en_slipped_9[2] */ #( .INIT(32'b11010101110001001001000110000000)) \read_en_slipped_9[2] ( - .Z (_N24016), + .Z (_N23795), .I0 (coarse_slip_step[0]), .I1 (coarse_slip_step[3]), .I2 (read_cmd_mux[2]), @@ -153144,8 +153050,8 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq12 GTP_LUT5M /* \read_en_slipped_13[0] */ #( .INIT(32'b10101010101010100101000001000100)) \read_en_slipped_13[0] ( - .Z (_N24030), - .I0 (_N24014), + .Z (_N23809), + .I0 (_N23793), .I1 (read_cmd_mux[0]), .I2 (read_cmd_mux_r2[0]), .I3 (coarse_slip_step[3]), @@ -153156,8 +153062,8 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq12 GTP_LUT5M /* \read_en_slipped_13[2] */ #( .INIT(32'b10101010101010100101000001000100)) \read_en_slipped_13[2] ( - .Z (_N24032), - .I0 (_N24016), + .Z (_N23811), + .I0 (_N23795), .I1 (read_cmd_mux[2]), .I2 (read_cmd_mux_r2[2]), .I3 (coarse_slip_step[3]), @@ -153168,7 +153074,7 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq12 GTP_LUT5M /* \read_en_slipped_13[3] */ #( .INIT(32'b00001000000010001100100000001000)) \read_en_slipped_13[3] ( - .Z (_N24033), + .Z (_N23812), .I0 (read_cmd_mux_r1[2]), .I1 (coarse_slip_step[0]), .I2 (coarse_slip_step[3]), @@ -153179,14 +153085,14 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq12 GTP_MUX2LUT6 \read_en_slipped_14[0] ( .Z (read_en_slipped[0]), - .I0 (_N24030), - .I1 (_N24002), + .I0 (_N23809), + .I1 (_N23781), .S (coarse_slip_step[1])); GTP_MUX2LUT6 \read_en_slipped_14[2] ( .Z (read_en_slipped[2]), - .I0 (_N24032), - .I1 (_N24004), + .I0 (_N23811), + .I1 (_N23783), .S (coarse_slip_step[1])); GTP_LUT3 /* \read_en_slipped_14[3] */ #( @@ -153194,8 +153100,8 @@ module ipsxb_ddrphy_dqs_gate_coarse_cal_v1_3_unq12 \read_en_slipped_14[3] ( .Z (read_en_slipped[3]), .I0 (coarse_slip_step[1]), - .I1 (_N24005), - .I2 (_N24033)); + .I1 (_N23784), + .I2 (_N23812)); // LUT = (~I0&I2)|(I0&I1) ; @@ -153205,7 +153111,7 @@ endmodule module ipsxb_ddrphy_gatecal_v1_3_unq12 ( input N1, - input _N96110, + input _N96888, input ddrphy_clkin, input dqs_gate_check_pass, input dqs_gate_vld, @@ -153238,26 +153144,26 @@ module ipsxb_ddrphy_gatecal_v1_3_unq12 wire _N6; wire _N10; wire _N17; - wire _N16083; - wire _N16084; - wire _N16085; - wire _N16086; - wire _N16087; - wire _N22684; - wire _N22687; - wire _N22688; - wire _N22689; - wire _N23673; - wire _N23674; - wire _N23675; - wire _N23676; - wire _N23677; - wire _N83280; - wire _N96259; - wire _N96322; - wire _N103403; - wire _N103404; - wire _N103405; + wire _N15001; + wire _N15002; + wire _N15003; + wire _N15004; + wire _N15005; + wire _N22628; + wire _N22631; + wire _N22632; + wire _N22633; + wire _N23590; + wire _N23591; + wire _N23592; + wire _N23593; + wire _N23594; + wire _N84115; + wire _N97084; + wire _N97098; + wire _N104215; + wire _N104216; + wire _N104217; wire [2:0] dgts_cnt; wire dqs_gate_vld_n; wire gate_check_pass_d; @@ -153290,7 +153196,7 @@ module ipsxb_ddrphy_gatecal_v1_3_unq12 GTP_LUT5 /* \N52_6[0] */ #( .INIT(32'b01010101110000000101010111111111)) \N52_6[0] ( - .Z (_N22684), + .Z (_N22628), .I0 (gate_move_en), .I1 (gatecal_start), .I2 (N567[6]), @@ -153299,20 +153205,20 @@ module ipsxb_ddrphy_gatecal_v1_3_unq12 // LUT = (~I3&~I4)|(~I0&I3)|(I1&I2&~I3) ; GTP_LUT5 /* \N52_7[0] */ #( - .INIT(32'b00010001111100000000000011110000)) + .INIT(32'b00001100000011000101110000001100)) \N52_7[0] ( - .Z (_N22687), - .I0 (_N83280), - .I1 (dqs_gate_vld), - .I2 (_N22684), - .I3 (gate_state_reg[2]), - .I4 (dqs_gate_vld_r)); - // LUT = (I2&~I3)|(~I0&~I1&I3&I4) ; + .Z (_N22631), + .I0 (dqs_gate_vld), + .I1 (_N22628), + .I2 (gate_state_reg[2]), + .I3 (dqs_gate_vld_r), + .I4 (_N84115)); + // LUT = (I1&~I2)|(~I0&I2&I3&~I4) ; GTP_LUT5M /* \N52_7[1] */ #( .INIT(32'b11111111001101111010101010101010)) \N52_7[1] ( - .Z (_N22688), + .Z (_N22632), .I0 (coarse_slip_step[3]), .I1 (dqs_gate_vld_r), .I2 (dgts_cnt[2]), @@ -153324,7 +153230,7 @@ module ipsxb_ddrphy_gatecal_v1_3_unq12 GTP_LUT5 /* \N52_7[2] */ #( .INIT(32'b11000000111000101100000011110011)) \N52_7[2] ( - .Z (_N22689), + .Z (_N22633), .I0 (gatecal_start), .I1 (gate_state_reg[2]), .I2 (N22[2]), @@ -153336,7 +153242,7 @@ module ipsxb_ddrphy_gatecal_v1_3_unq12 .INIT(8'b00000010)) \N52_9[2]_2 ( .Z (gate_state_next[2]), - .I0 (_N22689), + .I0 (_N22633), .I1 (gate_state_reg[1]), .I2 (gate_state_reg[0])); // LUT = I0&~I1&~I2 ; @@ -153355,8 +153261,8 @@ module ipsxb_ddrphy_gatecal_v1_3_unq12 N70_6 ( .Z (N70), .I0 (coarse_slip_step[3]), - .I1 (_N22687), - .I2 (_N22688), + .I1 (_N22631), + .I2 (_N22632), .I3 (gate_state_reg[1]), .I4 (gate_state_reg[0])); // LUT = (I0&I3&~I4)|(I0&~I1&I2&~I4) ; @@ -153368,7 +153274,7 @@ module ipsxb_ddrphy_gatecal_v1_3_unq12 .I4_TO_CARRY("FALSE"), .I4_TO_LUT("FALSE")) N81_1_0 ( - .COUT (_N16083), + .COUT (_N15001), .Z (), .CIN (), .I0 (), @@ -153388,12 +153294,12 @@ module ipsxb_ddrphy_gatecal_v1_3_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N81_1_1 ( - .COUT (_N16084), - .Z (_N23673), - .CIN (_N16083), + .COUT (_N15002), + .Z (_N23590), + .CIN (_N15001), .I0 (), .I1 (read_clk_ctrl[1]), - .I2 (_N96259), + .I2 (_N97098), .I3 (golden_value[1]), .I4 (1'b0), .ID ()); @@ -153408,12 +153314,12 @@ module ipsxb_ddrphy_gatecal_v1_3_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N81_1_2 ( - .COUT (_N16085), - .Z (_N23674), - .CIN (_N16084), + .COUT (_N15003), + .Z (_N23591), + .CIN (_N15002), .I0 (), .I1 (coarse_slip_step[0]), - .I2 (_N96259), + .I2 (_N97098), .I3 (golden_value[2]), .I4 (1'b0), .ID ()); @@ -153428,12 +153334,12 @@ module ipsxb_ddrphy_gatecal_v1_3_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N81_1_3 ( - .COUT (_N16086), - .Z (_N23675), - .CIN (_N16085), + .COUT (_N15004), + .Z (_N23592), + .CIN (_N15003), .I0 (), .I1 (coarse_slip_step[1]), - .I2 (_N96259), + .I2 (_N97098), .I3 (golden_value[3]), .I4 (1'b0), .ID ()); @@ -153448,12 +153354,12 @@ module ipsxb_ddrphy_gatecal_v1_3_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N81_1_4 ( - .COUT (_N16087), - .Z (_N23676), - .CIN (_N16086), + .COUT (_N15005), + .Z (_N23593), + .CIN (_N15004), .I0 (), .I1 (coarse_slip_step[2]), - .I2 (_N96259), + .I2 (_N97098), .I3 (golden_value[4]), .I4 (1'b0), .ID ()); @@ -153469,11 +153375,11 @@ module ipsxb_ddrphy_gatecal_v1_3_unq12 .I4_TO_LUT("FALSE")) N81_1_5 ( .COUT (), - .Z (_N23677), - .CIN (_N16087), + .Z (_N23594), + .CIN (_N15005), .I0 (), .I1 (coarse_slip_step[3]), - .I2 (_N96259), + .I2 (_N97098), .I3 (golden_value[5]), .I4 (1'b0), .ID ()); @@ -153488,7 +153394,7 @@ module ipsxb_ddrphy_gatecal_v1_3_unq12 .I0 (gate_win_size[0]), .I1 (gate_win_size[1]), .I2 (gate_win_size[2]), - .I3 (_N22687), + .I3 (_N22631), .I4 (gate_state_next[2])); // defparam N139_vname.orig_name = N139; // LUT = (I2&~I3&I4)|(I0&I1&~I3&I4) ; @@ -153526,10 +153432,10 @@ module ipsxb_ddrphy_gatecal_v1_3_unq12 N301_vname ( .Z (N301), .I0 (gatecal_start), - .I1 (_N22687), + .I1 (_N22631), .I2 (gate_state_reg[1]), .I3 (gate_state_reg[0]), - .I4 (_N96322)); + .I4 (_N97084)); // defparam N301_vname.orig_name = N301; // LUT = (~I1&~I3&I4)|(I2&~I3&I4)|(~I0&I3&I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_gatecal_v1_3.vp:410 @@ -153537,7 +153443,7 @@ module ipsxb_ddrphy_gatecal_v1_3_unq12 GTP_LUT5M /* N301_1 */ #( .INIT(32'b00001100000011100000110000001101)) N301_1 ( - .Z (_N96322), + .Z (_N97084), .I0 (N22[2]), .I1 (gate_state_reg[0]), .I2 (gate_state_next[2]), @@ -153551,20 +153457,20 @@ module ipsxb_ddrphy_gatecal_v1_3_unq12 N327_vname ( .Z (N327), .I0 (gate_move_en), - .I1 (_N96322)); + .I1 (_N97084)); // defparam N327_vname.orig_name = N327; // LUT = (I0)|(I1) ; GTP_LUT5M /* N328_10 */ #( .INIT(32'b01010000111100001101000011110000)) N328_10 ( - .Z (_N96259), + .Z (_N97098), .I0 (gatecal_start), .I1 (gate_state_reg[1]), .I2 (gate_move_en), - .I3 (_N96322), + .I3 (_N97084), .I4 (gate_state_reg[0]), - .ID (_N22687)); + .ID (_N22631)); // LUT = (I1&I2&~I4)|(~ID&I2&~I4)|(~I0&I2&I4)|(I2&~I3) ; GTP_LUT5 /* \N328_17[0]_1 */ #( @@ -153575,7 +153481,7 @@ module ipsxb_ddrphy_gatecal_v1_3_unq12 .I1 (gate_move_en), .I2 (N301), .I3 (golden_value[0]), - .I4 (_N96259)); + .I4 (_N97098)); // LUT = (~I0&I4)|(~I1&I2&I3&~I4) ; GTP_LUT4 /* \N328_17[1]_1 */ #( @@ -153584,8 +153490,8 @@ module ipsxb_ddrphy_gatecal_v1_3_unq12 .Z (N328[1]), .I0 (gate_move_en), .I1 (N301), - .I2 (_N23673), - .I3 (_N96259)); + .I2 (_N23590), + .I3 (_N97098)); // LUT = (I2&I3)|(~I0&I1&I2) ; GTP_LUT4 /* \N328_17[2]_1 */ #( @@ -153594,8 +153500,8 @@ module ipsxb_ddrphy_gatecal_v1_3_unq12 .Z (N328[2]), .I0 (gate_move_en), .I1 (N301), - .I2 (_N23674), - .I3 (_N96259)); + .I2 (_N23591), + .I3 (_N97098)); // LUT = (I2&I3)|(~I0&I1&I2) ; GTP_LUT4 /* \N328_17[3]_1 */ #( @@ -153604,8 +153510,8 @@ module ipsxb_ddrphy_gatecal_v1_3_unq12 .Z (N328[3]), .I0 (gate_move_en), .I1 (N301), - .I2 (_N23675), - .I3 (_N96259)); + .I2 (_N23592), + .I3 (_N97098)); // LUT = (I2&I3)|(~I0&I1&I2) ; GTP_LUT4 /* \N328_17[4]_1 */ #( @@ -153614,8 +153520,8 @@ module ipsxb_ddrphy_gatecal_v1_3_unq12 .Z (N328[4]), .I0 (gate_move_en), .I1 (N301), - .I2 (_N23676), - .I3 (_N96259)); + .I2 (_N23593), + .I3 (_N97098)); // LUT = (I2&I3)|(~I0&I1&I2) ; GTP_LUT4 /* \N328_17[5]_1 */ #( @@ -153624,8 +153530,8 @@ module ipsxb_ddrphy_gatecal_v1_3_unq12 .Z (N328[5]), .I0 (gate_move_en), .I1 (N301), - .I2 (_N23677), - .I3 (_N96259)); + .I2 (_N23594), + .I3 (_N97098)); // LUT = (I2&I3)|(~I0&I1&I2) ; GTP_LUT1 /* N389_4_inv */ #( @@ -153820,14 +153726,14 @@ module ipsxb_ddrphy_gatecal_v1_3_unq12 .Q (gate_adj_done), .C (N1), .CLK (ddrphy_clkin), - .D (_N103404)); + .D (_N104216)); // defparam gate_adj_done_vname.orig_name = gate_adj_done; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_gatecal_v1_3.vp:406 GTP_LUT5 /* gate_adj_done_ce_mux */ #( .INIT(32'b00000000010001010000000001000100)) gate_adj_done_ce_mux ( - .Z (_N103404), + .Z (_N104216), .I0 (gate_move_en), .I1 (gate_adj_done), .I2 (dqs_gate_vld), @@ -153842,16 +153748,16 @@ module ipsxb_ddrphy_gatecal_v1_3_unq12 .Q (gate_cal_error), .C (N1), .CLK (ddrphy_clkin), - .D (_N103403)); + .D (_N104215)); // defparam gate_cal_error_vname.orig_name = gate_cal_error; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_gatecal_v1_3.vp:416 GTP_LUT3 /* gate_cal_error_ce_mux */ #( .INIT(8'b11101010)) gate_cal_error_ce_mux ( - .Z (_N103403), + .Z (_N104215), .I0 (gate_cal_error), - .I1 (_N22687), + .I1 (_N22631), .I2 (gate_state_next[2])); // LUT = (I0)|(I1&I2) ; @@ -153873,16 +153779,16 @@ module ipsxb_ddrphy_gatecal_v1_3_unq12 .Q (gate_check_pass), .C (N1), .CLK (ddrphy_clkin), - .D (_N103405)); + .D (_N104217)); // defparam gate_check_pass_vname.orig_name = gate_check_pass; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_gatecal_v1_3.vp:620 GTP_LUT4 /* gate_check_pass_ce_mux */ #( .INIT(16'b1111101100001010)) gate_check_pass_ce_mux ( - .Z (_N103405), + .Z (_N104217), .I0 (gate_check_pass), - .I1 (_N22687), + .I1 (_N22631), .I2 (N301), .I3 (gate_state_next[2])); // LUT = (I0&~I2)|(~I1&I3)|(I2&I3) ; @@ -153936,7 +153842,7 @@ module ipsxb_ddrphy_gatecal_v1_3_unq12 .I1 (gate_move_en), .I2 (dgts_cnt[2]), .I3 (gate_state_reg[3]), - .I4 (_N96110)); + .I4 (_N96888)); // LUT = (~I1&I3)|(~I0&~I2&I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_gatecal_v1_3.vp:336 @@ -153945,17 +153851,17 @@ module ipsxb_ddrphy_gatecal_v1_3_unq12 \gate_state_fsm[2:0]_18 ( .Z (_N17), .I0 (gatecal_start), - .I1 (_N83280), + .I1 (_N84115), .I2 (N567[6]), .I3 (gate_state_reg[4]), - .I4 (_N96110)); + .I4 (_N96888)); // LUT = (I1&I4)|(I0&~I2&I3) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_gatecal_v1_3.vp:336 GTP_LUT4 /* \gate_state_fsm[2:0]_36 */ #( .INIT(16'b1111111110000000)) \gate_state_fsm[2:0]_36 ( - .Z (_N83280), + .Z (_N84115), .I0 (coarse_slip_step[3]), .I1 (dgts_cnt[0]), .I2 (dgts_cnt[1]), @@ -154254,7 +154160,7 @@ module ipsxb_ddrphy_data_slice_dqs_gate_cal_v1_3_unq12 input [3:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r1 , input [3:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r2 , input [3:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r3 , - input _N96110, + input _N96888, input ddrphy_clkin, input dqs_gate_check_pass, input gate_check, @@ -154318,7 +154224,7 @@ module ipsxb_ddrphy_data_slice_dqs_gate_cal_v1_3_unq12 .gate_check_error (gate_check_error), .gate_check_pass (gate_check_pass), .N1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/N0 ), - ._N96110 (_N96110), + ._N96888 (_N96888), .ddrphy_clkin (ddrphy_clkin), .dqs_gate_check_pass (dqs_gate_check_pass), .dqs_gate_vld (dqs_gate_vld), @@ -154333,27 +154239,32 @@ endmodule module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 ( + input [4:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt , + input [6:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg , input [4:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt , input [6:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg , input [7:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_in_dly , input N0, input N449, - input _N96271, - input _N96274, - input _N96887, + input _N97033, + input _N97080, + input _N97672, + input _N104452, input ddrphy_clkin, + input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld , input wrlvl_ck_dly_done, input wrlvl_ck_dly_start, input wrlvl_dqs_req, output [4:0] cnt, - output [4:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484 , output [7:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/adj_wrdqs , output [6:0] wl_state_reg, output [7:0] wrlvl_step, output N165, - output _N96884, + output _N97660, + output _N107042, output ck_check_done, output ddrphy_gatei, + output dq_vld, output wrlvl_ck_dly_flag, output wrlvl_dqs, output wrlvl_dqs_en, @@ -154362,13 +154273,15 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 ); wire N14; wire N56; - wire N72; + wire N63; wire N136; wire [7:0] N141; wire N173; + wire N228; wire N286; wire N296; wire N301; + wire N334; wire N359; wire [4:0] N367; wire N377; @@ -154389,56 +154302,52 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 wire _N12; wire _N15; wire _N22; - wire _N5801; - wire _N13889; - wire _N13890; - wire _N13891; - wire _N13892; - wire _N13893; - wire _N13894; - wire _N14828; - wire _N14829; - wire _N14830; - wire _N14831; - wire _N14832; - wire _N14833; - wire _N15919; - wire _N15920; - wire _N15921; - wire _N15922; - wire _N15923; - wire _N15924; - wire _N15925; - wire _N23837; - wire _N65355; - wire _N65990; - wire _N65991; - wire _N66086; - wire _N66182; - wire _N66278; - wire _N103408; - wire _N103409; - wire _N103410; - wire _N103411; - wire _N103412; - wire _N103413; - wire _N103414; - wire _N105242; - wire _N105247; - wire _N106316; - wire _N106361; - wire _N106362; - wire _N106370; - wire _N106371; - wire _N106796; - wire _N106804; - wire _N106805; - wire _N106810; - wire _N106813; - wire _N106818; + wire _N5839; + wire _N14713; + wire _N14714; + wire _N14715; + wire _N14716; + wire _N14717; + wire _N14718; + wire _N14792; + wire _N14793; + wire _N14794; + wire _N14795; + wire _N14796; + wire _N14797; + wire _N17036; + wire _N17037; + wire _N17038; + wire _N17039; + wire _N17040; + wire _N17041; + wire _N17042; + wire _N23628; + wire _N66399; + wire _N67053; + wire _N67086; + wire _N67087; + wire _N67182; + wire _N67278; + wire _N104220; + wire _N104221; + wire _N104222; + wire _N104223; + wire _N104224; + wire _N104225; + wire _N104226; + wire _N106050; + wire _N107179; + wire _N107180; + wire _N107188; + wire _N107189; + wire _N107615; + wire _N107623; + wire _N107624; + wire _N107633; + wire _N107647; wire [7:0] ck_dly_step; wire dq_rising; - wire dq_vld; wire [7:0] step_cnt; wire [7:0] vld_init_cnt; wire wl_done_flag; @@ -154452,10 +154361,10 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 .INIT(16'b1111100010001000)) N14_vname ( .Z (N14), - .I0 (_N106370), - .I1 (_N106371), + .I0 (_N107188), + .I1 (_N107189), .I2 (N286), - .I3 (_N106362)); + .I3 (_N107180)); // defparam N14_vname.orig_name = N14; // LUT = (I0&I1)|(I2&I3) ; @@ -154517,29 +154426,25 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 // defparam N56_vname.orig_name = N56; // LUT = ~I0 ; + GTP_LUT2 /* N63 */ #( + .INIT(4'b0100)) + N63_vname ( + .Z (N63), + .I0 (wl_done_flag), + .I1 (wl_state_reg[0])); + // defparam N63_vname.orig_name = N63; + // LUT = ~I0&I1 ; + // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:364 + GTP_LUT3 /* N66_ac2 */ #( .INIT(8'b10000000)) N66_ac2 ( - .Z (_N5801), + .Z (_N5839), .I0 (cnt[0]), .I1 (cnt[1]), .I2 (cnt[2])); // LUT = I0&I1&I2 ; - GTP_LUT5M /* N72 */ #( - .INIT(32'b00010001000100010011000100110000)) - N72_vname ( - .Z (N72), - .I0 (wl_next_state[2]), - .I1 (wl_next_state[0]), - .I2 (wl_state_reg[3]), - .I3 (wl_state_reg[4]), - .I4 (wl_next_state[1]), - .ID (N484[4])); - // defparam N72_vname.orig_name = N72; - // LUT = (~ID&~I1&I3&~I4)|(~I1&I2&~I4)|(~I0&~I1&I4) ; - // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:369 - GTP_LUT5CARRY /* N102_1_0 */ #( .INIT(32'b11001100110011000000000000000000), .ID_TO_LUT("FALSE"), @@ -154547,7 +154452,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 .I4_TO_CARRY("FALSE"), .I4_TO_LUT("FALSE")) N102_1_0 ( - .COUT (_N15919), + .COUT (_N17036), .Z (), .CIN (), .I0 (), @@ -154567,9 +154472,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N102_1_1 ( - .COUT (_N15920), + .COUT (_N17037), .Z (N378[1]), - .CIN (_N15919), + .CIN (_N17036), .I0 (), .I1 (step_cnt[1]), .I2 (wrlvl_ck_dly_start), @@ -154587,9 +154492,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N102_1_2 ( - .COUT (_N15921), + .COUT (_N17038), .Z (N378[2]), - .CIN (_N15920), + .CIN (_N17037), .I0 (), .I1 (step_cnt[2]), .I2 (wrlvl_ck_dly_start), @@ -154607,9 +154512,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N102_1_3 ( - .COUT (_N15922), + .COUT (_N17039), .Z (N378[3]), - .CIN (_N15921), + .CIN (_N17038), .I0 (), .I1 (step_cnt[3]), .I2 (wrlvl_ck_dly_start), @@ -154627,9 +154532,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N102_1_4 ( - .COUT (_N15923), + .COUT (_N17040), .Z (N378[4]), - .CIN (_N15922), + .CIN (_N17039), .I0 (), .I1 (step_cnt[4]), .I2 (wrlvl_ck_dly_start), @@ -154647,9 +154552,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N102_1_5 ( - .COUT (_N15924), + .COUT (_N17041), .Z (N378[5]), - .CIN (_N15923), + .CIN (_N17040), .I0 (), .I1 (step_cnt[5]), .I2 (wrlvl_ck_dly_start), @@ -154667,9 +154572,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N102_1_6 ( - .COUT (_N15925), + .COUT (_N17042), .Z (N378[6]), - .CIN (_N15924), + .CIN (_N17041), .I0 (), .I1 (step_cnt[6]), .I2 (wrlvl_ck_dly_start), @@ -154689,7 +154594,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 N102_1_7 ( .COUT (), .Z (N378[7]), - .CIN (_N15925), + .CIN (_N17042), .I0 (), .I1 (step_cnt[7]), .I2 (wrlvl_ck_dly_start), @@ -154707,7 +154612,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_1 ( - .COUT (_N14828), + .COUT (_N14792), .Z (N387[1]), .CIN (), .I0 (ck_dly_step[0]), @@ -154727,9 +154632,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_2 ( - .COUT (_N14829), + .COUT (_N14793), .Z (N387[2]), - .CIN (_N14828), + .CIN (_N14792), .I0 (ck_dly_step[0]), .I1 (ck_dly_step[1]), .I2 (N296), @@ -154747,9 +154652,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_3 ( - .COUT (_N14830), + .COUT (_N14794), .Z (N387[3]), - .CIN (_N14829), + .CIN (_N14793), .I0 (), .I1 (ck_dly_step[3]), .I2 (N296), @@ -154767,9 +154672,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_4 ( - .COUT (_N14831), + .COUT (_N14795), .Z (N387[4]), - .CIN (_N14830), + .CIN (_N14794), .I0 (), .I1 (ck_dly_step[4]), .I2 (N296), @@ -154787,9 +154692,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_5 ( - .COUT (_N14832), + .COUT (_N14796), .Z (N387[5]), - .CIN (_N14831), + .CIN (_N14795), .I0 (), .I1 (ck_dly_step[5]), .I2 (N296), @@ -154807,9 +154712,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_6 ( - .COUT (_N14833), + .COUT (_N14797), .Z (N387[6]), - .CIN (_N14832), + .CIN (_N14796), .I0 (), .I1 (ck_dly_step[6]), .I2 (N296), @@ -154829,7 +154734,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 N104_1_7 ( .COUT (), .Z (N387[7]), - .CIN (_N14833), + .CIN (_N14797), .I0 (), .I1 (ck_dly_step[7]), .I2 (N296), @@ -154840,20 +154745,19 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 // CARRY = (I1) ? CIN : (I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:407 - GTP_LUT4 /* N124_1 */ #( - .INIT(16'b0000000100000000)) + GTP_LUT3 /* N124_1 */ #( + .INIT(8'b10000000)) N124_1 ( - .Z (_N96884), - .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [4] ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [1] ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [0] ), - .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg [4] )); - // LUT = ~I0&~I1&~I2&I3 ; + .Z (_N97660), + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg [4] )); + // LUT = I0&I1&I2 ; GTP_LUT5 /* N124_8 */ #( .INIT(32'b00000000000000000000010000000000)) N124_8 ( - .Z (_N106796), + .Z (_N107615), .I0 (cnt[0]), .I1 (cnt[1]), .I2 (cnt[2]), @@ -154868,7 +154772,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 .I0 (cnt[2]), .I1 (cnt[3]), .I2 (wl_state_reg[2]), - .I3 (_N96271)); + .I3 (_N97033)); // LUT = I0&~I1&I2&I3 ; GTP_LUT2 /* \N141[0]_1 */ #( @@ -154956,7 +154860,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 GTP_LUT5 /* N173_8 */ #( .INIT(32'b00000000000000000000000000000010)) N173_8 ( - .Z (_N105242), + .Z (_N107633), .I0 (N165), .I1 (vld_init_cnt[1]), .I2 (vld_init_cnt[3]), @@ -154972,7 +154876,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 .I1 (vld_init_cnt[2]), .I2 (vld_init_cnt[6]), .I3 (vld_init_cnt[7]), - .I4 (_N105242)); + .I4 (_N107633)); // LUT = I0&I1&~I2&~I3&I4 ; GTP_LUT5CARRY /* N201_1_1 */ #( @@ -154982,7 +154886,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N201_1_1 ( - .COUT (_N13889), + .COUT (_N14713), .Z (N440[1]), .CIN (), .I0 (vld_init_cnt[0]), @@ -155002,9 +154906,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N201_1_2 ( - .COUT (_N13890), + .COUT (_N14714), .Z (N440[2]), - .CIN (_N13889), + .CIN (_N14713), .I0 (vld_init_cnt[0]), .I1 (vld_init_cnt[1]), .I2 (wl_state_reg[6]), @@ -155022,9 +154926,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N201_1_3 ( - .COUT (_N13891), + .COUT (_N14715), .Z (N440[3]), - .CIN (_N13890), + .CIN (_N14714), .I0 (), .I1 (vld_init_cnt[3]), .I2 (wl_state_reg[6]), @@ -155042,9 +154946,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N201_1_4 ( - .COUT (_N13892), + .COUT (_N14716), .Z (N440[4]), - .CIN (_N13891), + .CIN (_N14715), .I0 (), .I1 (vld_init_cnt[4]), .I2 (wl_state_reg[6]), @@ -155062,9 +154966,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N201_1_5 ( - .COUT (_N13893), + .COUT (_N14717), .Z (N440[5]), - .CIN (_N13892), + .CIN (_N14716), .I0 (), .I1 (vld_init_cnt[5]), .I2 (wl_state_reg[6]), @@ -155082,9 +154986,9 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N201_1_6 ( - .COUT (_N13894), + .COUT (_N14718), .Z (N440[6]), - .CIN (_N13893), + .CIN (_N14717), .I0 (), .I1 (vld_init_cnt[6]), .I2 (wl_state_reg[6]), @@ -155104,7 +155008,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 N201_1_7 ( .COUT (), .Z (N440[7]), - .CIN (_N13894), + .CIN (_N14718), .I0 (), .I1 (vld_init_cnt[7]), .I2 (wl_state_reg[6]), @@ -155115,40 +155019,20 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 // CARRY = (I1) ? CIN : (I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:516 - GTP_LUT4 /* N228_2 */ #( - .INIT(16'b0000001000000000)) - N228_2 ( - .Z (_N106813), + GTP_LUT5 /* N228_4 */ #( + .INIT(32'b00000010000000000000000000000000)) + N228_4 ( + .Z (N228), .I0 (dq_vld), .I1 (cnt[1]), .I2 (cnt[4]), - .I3 (wl_state_reg[4])); - // LUT = I0&~I1&~I2&I3 ; + .I3 (wl_state_reg[4]), + .I4 (_N97080)); + // LUT = I0&~I1&~I2&I3&I4 ; GTP_LUT5 /* N232_4 */ #( .INIT(32'b10000000000000000000000000000000)) N232_4 ( - .Z (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484 [4] ), - .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [4] ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] ), - .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [1] ), - .I4 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [0] )); - // LUT = I0&I1&I2&I3&I4 ; - - GTP_LUT4 /* N232_5 */ #( - .INIT(16'b0000001000000000)) - N232_5 ( - .Z (_N106316), - .I0 (wrlvl_ck_dly_start), - .I1 (wrlvl_ck_check_seq[3]), - .I2 (wrlvl_ck_check_seq[4]), - .I3 (_N105247)); - // LUT = I0&~I1&~I2&I3 ; - - GTP_LUT5 /* N265_3 */ #( - .INIT(32'b10000000000000000000000000000000)) - N265_3 ( .Z (N484[4]), .I0 (cnt[0]), .I1 (cnt[1]), @@ -155160,7 +155044,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 GTP_LUT5 /* N265_10 */ #( .INIT(32'b00000000000000000000000000001000)) N265_10 ( - .Z (_N106818), + .Z (_N107647), .I0 (wrlvl_ck_dly_pass), .I1 (wrlvl_dq_seq[0]), .I2 (wrlvl_dq_seq[1]), @@ -155171,7 +155055,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 GTP_LUT4 /* N279_6 */ #( .INIT(16'b1000000000000000)) N279_6 ( - .Z (_N106370), + .Z (_N107188), .I0 (step_cnt[1]), .I1 (step_cnt[2]), .I2 (step_cnt[3]), @@ -155181,7 +155065,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 GTP_LUT4 /* N279_7 */ #( .INIT(16'b1000000000000000)) N279_7 ( - .Z (_N106371), + .Z (_N107189), .I0 (step_cnt[0]), .I1 (step_cnt[5]), .I2 (step_cnt[6]), @@ -155191,7 +155075,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 GTP_LUT2 /* N286_9 */ #( .INIT(4'b0001)) N286_9 ( - .Z (_N106361), + .Z (_N107179), .I0 (ck_dly_step[0]), .I1 (ck_dly_step[7])); // LUT = ~I0&~I1 ; @@ -155199,7 +155083,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 GTP_LUT4 /* N286_10 */ #( .INIT(16'b0000000000000001)) N286_10 ( - .Z (_N106362), + .Z (_N107180), .I0 (ck_dly_step[1]), .I1 (ck_dly_step[2]), .I2 (ck_dly_step[4]), @@ -155243,13 +155127,22 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 GTP_LUT4 /* N334_5 */ #( .INIT(16'b0000000000000001)) N334_5 ( - .Z (_N105247), + .Z (_N106050), .I0 (wrlvl_ck_check_seq[0]), .I1 (wrlvl_ck_check_seq[1]), .I2 (wrlvl_ck_check_seq[2]), .I3 (wrlvl_ck_check_seq[5])); // LUT = ~I0&~I1&~I2&~I3 ; + GTP_LUT3 /* N334_6 */ #( + .INIT(8'b00010000)) + N334_6 ( + .Z (N334), + .I0 (wrlvl_ck_check_seq[3]), + .I1 (wrlvl_ck_check_seq[4]), + .I2 (_N106050)); + // LUT = ~I0&~I1&I2 ; + GTP_LUT3 /* N359 */ #( .INIT(8'b10111111)) N359_vname ( @@ -155297,7 +155190,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 .INIT(16'b0100110010000000)) \N367_1[4] ( .Z (N367[4]), - .I0 (_N5801), + .I0 (_N5839), .I1 (N475), .I2 (cnt[3]), .I3 (cnt[4])); @@ -155352,18 +155245,18 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 GTP_LUT5 /* N395_2 */ #( .INIT(32'b01010111010101010101010101010101)) N395_2 ( - .Z (_N23837), + .Z (_N23628), .I0 (wrlvl_ck_dly_start), .I1 (ck_dly_step[3]), .I2 (ck_dly_step[6]), - .I3 (_N106361), - .I4 (_N106362)); + .I3 (_N107179), + .I4 (_N107180)); // LUT = (~I0)|(~I1&~I2&I3&I4) ; GTP_LUT4 /* \N417[0]_14 */ #( .INIT(16'b1111111111111110)) \N417[0]_14 ( - .Z (_N106804), + .Z (_N107623), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_in_dly [0] ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_in_dly [1] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_in_dly [2] ), @@ -155373,7 +155266,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 GTP_LUT4 /* \N417[0]_15 */ #( .INIT(16'b1111111111111110)) \N417[0]_15 ( - .Z (_N106805), + .Z (_N107624), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_in_dly [4] ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_in_dly [5] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_in_dly [6] ), @@ -155386,8 +155279,8 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 .Z (N417[0]), .I0 (wrlvl_dqs_en), .I1 (dq_vld), - .I2 (_N106804), - .I3 (_N106805)); + .I2 (_N107623), + .I3 (_N107624)); // LUT = (~I1)|(~I0)|(I2)|(I3) ; GTP_LUT3 /* \N417[1] */ #( @@ -155418,7 +155311,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 .I1 (cnt[3]), .I2 (wl_state_reg[4]), .I3 (wl_state_reg[6]), - .I4 (_N96271)); + .I4 (_N97033)); // defparam N439_vname.orig_name = N439; // LUT = (I3)|(I0&I1&I2&I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:509 @@ -155508,17 +155401,17 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 // LUT = (I0)|(I1) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:545 - GTP_LUT4 /* N475 */ #( - .INIT(16'b1000101110101010)) - N475_vname ( + GTP_LUT5M /* N475_1 */ #( + .INIT(32'b01010101010101010001010100000100)) + N475_1 ( .Z (N475), - .I0 (N72), - .I1 (wl_done_flag), - .I2 (N484[4]), - .I3 (wl_state_reg[0])); - // defparam N475_vname.orig_name = N475; - // LUT = (I0&~I3)|(I0&I1)|(~I1&~I2&I3) ; - // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:360 + .I0 (N484[4]), + .I1 (wl_next_state[1]), + .I2 (wl_next_state[2]), + .I3 (_N12), + .I4 (N63), + .ID (wl_next_state[0])); + // LUT = (~ID&~I1&I3&~I4)|(~ID&I1&~I2&~I4)|(~I0&I4) ; GTP_DFF_C /* ck_check_done */ #( .GRS_EN("TRUE"), @@ -155527,20 +155420,20 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 .Q (ck_check_done), .C (N0), .CLK (ddrphy_clkin), - .D (_N103413)); + .D (_N104225)); // defparam ck_check_done_vname.orig_name = ck_check_done; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:535 GTP_LUT5 /* ck_check_done_ce_mux */ #( - .INIT(32'b00110010001000100010001000100010)) + .INIT(32'b00000000000000001110110011001100)) ck_check_done_ce_mux ( - .Z (_N103413), - .I0 (ck_check_done), - .I1 (wl_state_reg[6]), - .I2 (_N96274), - .I3 (_N106316), - .I4 (_N106813)); - // LUT = (I0&~I1)|(~I1&I2&I3&I4) ; + .Z (_N104225), + .I0 (wrlvl_ck_dly_start), + .I1 (ck_check_done), + .I2 (N228), + .I3 (N334), + .I4 (wl_state_reg[6])); + // LUT = (I1&~I4)|(I0&I2&I3&~I4) ; GTP_DFF_CE /* \ck_dly_step[0] */ #( .GRS_EN("TRUE"), @@ -155638,7 +155531,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 .C (N0), .CE (N359), .CLK (ddrphy_clkin), - .D (_N65355)); + .D (_N66399)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:360 GTP_DFF_CE /* \cnt[1] */ #( @@ -155674,15 +155567,17 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 .D (N367[3])); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:360 - GTP_LUT4 /* \cnt[4:0]_3813 */ #( - .INIT(16'b0000101100001010)) - \cnt[4:0]_3813 ( - .Z (_N65355), - .I0 (N72), - .I1 (wl_done_flag), - .I2 (cnt[0]), - .I3 (wl_state_reg[0])); - // LUT = (I0&~I2)|(~I1&~I2&I3) ; + GTP_LUT5M /* \cnt[4:0]_3868 */ #( + .INIT(32'b00000000110011010000000011001110)) + \cnt[4:0]_3868 ( + .Z (_N66399), + .I0 (wl_next_state[2]), + .I1 (N63), + .I2 (wl_next_state[0]), + .I3 (cnt[0]), + .I4 (wl_next_state[1]), + .ID (_N12)); + // LUT = (ID&~I2&~I3&~I4)|(~I0&~I2&~I3&I4)|(I1&~I3) ; GTP_DFF_CE /* \cnt[4] */ #( .GRS_EN("TRUE"), @@ -155702,20 +155597,20 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 .Q (ddrphy_gatei), .C (N0), .CLK (ddrphy_clkin), - .D (_N103408)); + .D (_N104220)); // defparam ddrphy_gatei_vname.orig_name = ddrphy_gatei; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:413 GTP_LUT5M /* ddrphy_gatei_ce_mux */ #( .INIT(32'b11111110000000101101111100000000)) ddrphy_gatei_ce_mux ( - .Z (_N103408), - .I0 (_N23837), + .Z (_N104220), + .I0 (_N23628), .I1 (wl_next_state[2]), .I2 (wl_next_state[1]), .I3 (ddrphy_gatei), .I4 (wl_next_state[0]), - .ID (_N106796)); + .ID (_N107615)); // LUT = (~I2&I3&~I4)|(I2&I3&I4)|(I0&~I1&~I2&I4)|(~ID&I2&I3)|(I1&I3) ; GTP_DFF_C /* dq_rising */ #( @@ -155725,20 +155620,19 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 .Q (dq_rising), .C (N0), .CLK (ddrphy_clkin), - .D (_N103414)); + .D (_N104226)); // defparam dq_rising_vname.orig_name = dq_rising; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:559 - GTP_LUT5 /* dq_rising_ce_mux */ #( - .INIT(32'b00110010001000100010001000100010)) + GTP_LUT4 /* dq_rising_ce_mux */ #( + .INIT(16'b0000111000001100)) dq_rising_ce_mux ( - .Z (_N103414), - .I0 (dq_rising), - .I1 (wl_state_reg[6]), - .I2 (_N96274), - .I3 (_N106813), - .I4 (_N106818)); - // LUT = (I0&~I1)|(~I1&I2&I3&I4) ; + .Z (_N104226), + .I0 (N228), + .I1 (dq_rising), + .I2 (wl_state_reg[6]), + .I3 (_N107647)); + // LUT = (I1&~I2)|(I0&~I2&I3) ; GTP_DFF_C /* dq_vld */ #( .GRS_EN("TRUE"), @@ -155747,19 +155641,19 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 .Q (dq_vld), .C (N0), .CLK (ddrphy_clkin), - .D (_N103409)); + .D (_N104221)); // defparam dq_vld_vname.orig_name = dq_vld; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:453 GTP_LUT5 /* dq_vld_ce_mux */ #( .INIT(32'b00000000101110100000000010101010)) dq_vld_ce_mux ( - .Z (_N103409), + .Z (_N104221), .I0 (dq_vld), .I1 (cnt[2]), .I2 (cnt[3]), .I3 (wl_state_reg[6]), - .I4 (_N96887)); + .I4 (_N97672)); // LUT = (I0&~I3)|(~I1&I2&~I3&I4) ; GTP_DFF_CE /* \step_cnt[0] */ #( @@ -155945,14 +155839,14 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 .Q (wl_done_flag), .C (N0), .CLK (ddrphy_clkin), - .D (_N103410)); + .D (_N104222)); // defparam wl_done_flag_vname.orig_name = wl_done_flag; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:463 GTP_LUT3 /* wl_done_flag_ce_mux */ #( .INIT(8'b01010100)) wl_done_flag_ce_mux ( - .Z (_N103410), + .Z (_N104222), .I0 (wrlvl_dqs_req), .I1 (wl_done_flag), .I2 (wl_state_reg[6])); @@ -156152,18 +156046,18 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 .Q (wrlvl_ck_dly_flag), .C (N0), .CLK (ddrphy_clkin), - .D (_N103411)); + .D (_N104223)); // defparam wrlvl_ck_dly_flag_vname.orig_name = wrlvl_ck_dly_flag; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:483 GTP_LUT5M /* wrlvl_ck_dly_flag_ce_mux */ #( .INIT(32'b11111110111111110100010001000100)) wrlvl_ck_dly_flag_ce_mux ( - .Z (_N103411), + .Z (_N104223), .I0 (wrlvl_ck_check_seq[3]), .I1 (wrlvl_ck_dly_flag), .I2 (wrlvl_ck_check_seq[4]), - .I3 (_N105247), + .I3 (_N106050), .I4 (N173), .ID (wrlvl_ck_dly_done)); // LUT = (~I3&I4)|(I2&I4)|(I1&I4)|(I0&I4)|(~ID&I1) ; @@ -156175,19 +156069,19 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 .Q (wrlvl_ck_dly_pass), .C (N0), .CLK (ddrphy_clkin), - .D (_N103412)); + .D (_N104224)); // defparam wrlvl_ck_dly_pass_vname.orig_name = wrlvl_ck_dly_pass; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:483 GTP_LUT5 /* wrlvl_ck_dly_pass_ce_mux */ #( .INIT(32'b11001100110011101100110011001100)) wrlvl_ck_dly_pass_ce_mux ( - .Z (_N103412), + .Z (_N104224), .I0 (N173), .I1 (wrlvl_ck_dly_pass), .I2 (wrlvl_ck_check_seq[3]), .I3 (wrlvl_ck_check_seq[4]), - .I4 (_N105247)); + .I4 (_N106050)); // LUT = (I1)|(I0&~I2&~I3&I4) ; GTP_DFF_P /* \wrlvl_dq_r[0] */ #( @@ -156227,7 +156121,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 .Q (wrlvl_dq_seq[0]), .CE (N466), .CLK (ddrphy_clkin), - .D (_N65990), + .D (_N67053), .P (N0)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:545 @@ -156238,7 +156132,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 .Q (wrlvl_dq_seq[1]), .CE (N466), .CLK (ddrphy_clkin), - .D (_N66086), + .D (_N67086), .P (N0)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:545 @@ -156249,63 +156143,66 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 .Q (wrlvl_dq_seq[2]), .CE (N466), .CLK (ddrphy_clkin), - .D (_N66182), + .D (_N67182), .P (N0)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:545 GTP_LUT2 /* \wrlvl_dq_seq[3:0]_0 */ #( .INIT(4'b1110)) \wrlvl_dq_seq[3:0]_0 ( - .Z (_N65990), - .I0 (_N65991), - .I1 (wrlvl_dq_r[2])); + .Z (_N67086), + .I0 (_N67087), + .I1 (wrlvl_dq_seq[0])); // LUT = (I0)|(I1) ; - GTP_LUT4 /* \wrlvl_dq_seq[3:0]_1_4 */ #( - .INIT(16'b1110111111111111)) - \wrlvl_dq_seq[3:0]_1_4 ( - .Z (_N106810), - .I0 (cnt[0]), - .I1 (cnt[1]), - .I2 (cnt[2]), - .I3 (cnt[3])); - // LUT = (~I3)|(~I2)|(I0)|(I1) ; - - GTP_LUT5 /* \wrlvl_dq_seq[3:0]_1_6 */ #( - .INIT(32'b11111111111111111011111111111111)) - \wrlvl_dq_seq[3:0]_1_6 ( - .Z (_N65991), + GTP_LUT5 /* \wrlvl_dq_seq[3:0]_1_3 */ #( + .INIT(32'b11111111111111111111111111111011)) + \wrlvl_dq_seq[3:0]_1_3 ( + .Z (_N67087), .I0 (wrlvl_ck_dly_start), .I1 (wrlvl_dqs_en), - .I2 (dq_vld), - .I3 (wl_state_reg[4]), - .I4 (_N106810)); - // LUT = (~I3)|(~I2)|(~I1)|(I0)|(I4) ; + .I2 (cnt[0]), + .I3 (cnt[1]), + .I4 (_N104452)); + // LUT = (~I1)|(I0)|(I2)|(I3)|(I4) ; - GTP_LUT2 /* \wrlvl_dq_seq[3:0]_96 */ #( - .INIT(4'b1110)) - \wrlvl_dq_seq[3:0]_96 ( - .Z (_N66086), - .I0 (_N65991), - .I1 (wrlvl_dq_seq[0])); - // LUT = (I0)|(I1) ; + GTP_LUT5 /* \wrlvl_dq_seq[3:0]_60_3 */ #( + .INIT(32'b11111111111111111111111111111011)) + \wrlvl_dq_seq[3:0]_60_3 ( + .Z (_N67053), + .I0 (wrlvl_ck_dly_start), + .I1 (wrlvl_dqs_en), + .I2 (cnt[0]), + .I3 (wrlvl_dq_r[2]), + .I4 (_N104452)); + // LUT = (~I1)|(I0)|(I2)|(I3)|(I4) ; - GTP_LUT2 /* \wrlvl_dq_seq[3:0]_191 */ #( + GTP_LUT2 /* \wrlvl_dq_seq[3:0]_155 */ #( .INIT(4'b1110)) - \wrlvl_dq_seq[3:0]_191 ( - .Z (_N66182), - .I0 (_N65991), + \wrlvl_dq_seq[3:0]_155 ( + .Z (_N67182), + .I0 (_N67087), .I1 (wrlvl_dq_seq[1])); // LUT = (I0)|(I1) ; - GTP_LUT2 /* \wrlvl_dq_seq[3:0]_286 */ #( + GTP_LUT2 /* \wrlvl_dq_seq[3:0]_250 */ #( .INIT(4'b1110)) - \wrlvl_dq_seq[3:0]_286 ( - .Z (_N66278), - .I0 (_N65991), + \wrlvl_dq_seq[3:0]_250 ( + .Z (_N67278), + .I0 (_N67087), .I1 (wrlvl_dq_seq[2])); // LUT = (I0)|(I1) ; + GTP_LUT4 /* \wrlvl_dq_seq[3:0]_350 */ #( + .INIT(16'b1101111111111111)) + \wrlvl_dq_seq[3:0]_350 ( + .Z (_N107042), + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [1] ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld ), + .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg [4] )); + // LUT = (~I3)|(~I2)|(~I0)|(I1) ; + GTP_DFF_PE /* \wrlvl_dq_seq[3] */ #( .GRS_EN("TRUE"), .INIT(1'b1)) @@ -156313,7 +156210,7 @@ module ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 .Q (wrlvl_dq_seq[3]), .CE (N466), .CLK (ddrphy_clkin), - .D (_N66278), + .D (_N67278), .P (N0)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_data_slice_wrlvl_v1_4.vp:545 @@ -156482,41 +156379,41 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq12 wire _N9; wire _N19; wire _N21; - wire _N84566; - wire _N97685; - wire _N97689; - wire _N103416; - wire _N103417; - wire _N105487; - wire _N105491; - wire _N105495; - wire _N105499; - wire _N105503; - wire _N105507; - wire _N105511; - wire _N105512; - wire _N105518; - wire _N105580; - wire _N105584; - wire _N105588; - wire _N105592; - wire _N105595; - wire _N105599; - wire _N106398; - wire _N106402; - wire _N106406; - wire _N106410; - wire _N106414; - wire _N106422; - wire _N106426; - wire _N106430; - wire _N106434; - wire _N106438; - wire _N106442; - wire _N106446; - wire _N106450; - wire _N106454; - wire _N106457; + wire _N85377; + wire _N98467; + wire _N98469; + wire _N104228; + wire _N104229; + wire _N106296; + wire _N106300; + wire _N106304; + wire _N106308; + wire _N106312; + wire _N106316; + wire _N106320; + wire _N106321; + wire _N106327; + wire _N106404; + wire _N106408; + wire _N106412; + wire _N106416; + wire _N106419; + wire _N106423; + wire _N107216; + wire _N107220; + wire _N107224; + wire _N107228; + wire _N107232; + wire _N107240; + wire _N107244; + wire _N107248; + wire _N107252; + wire _N107256; + wire _N107260; + wire _N107264; + wire _N107268; + wire _N107272; + wire _N107275; wire [2:0] gdet_next_state; wire [5:0] gdet_state_reg; @@ -156525,8 +156422,8 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq12 N21_2 ( .Z (N328[2]), .I0 (read_valid), - .I1 (_N97685), - .I2 (_N97689)); + .I1 (_N98467), + .I2 (_N98469)); // LUT = I0&I1&I2 ; GTP_LUT3 /* \N57_12_and[1][2] */ #( @@ -156559,7 +156456,7 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq12 GTP_LUT5 /* N118_5 */ #( .INIT(32'b10000000000000000000000000000000)) N118_5 ( - .Z (_N105580), + .Z (_N106404), .I0 (read_data[6]), .I1 (read_data[12]), .I2 (read_data[14]), @@ -156570,7 +156467,7 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq12 GTP_LUT5 /* N118_9 */ #( .INIT(32'b10000000000000000000000000000000)) N118_9 ( - .Z (_N105584), + .Z (_N106408), .I0 (read_data[28]), .I1 (read_data[30]), .I2 (read_data[36]), @@ -156581,7 +156478,7 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq12 GTP_LUT5 /* N118_13 */ #( .INIT(32'b10000000000000000000000000000000)) N118_13 ( - .Z (_N105588), + .Z (_N106412), .I0 (read_data[46]), .I1 (read_data[52]), .I2 (read_data[54]), @@ -156592,7 +156489,7 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq12 GTP_LUT5 /* N118_17 */ #( .INIT(32'b00000000000000000000000000000001)) N118_17 ( - .Z (_N105592), + .Z (_N106416), .I0 (read_data[3]), .I1 (read_data[11]), .I2 (read_data[19]), @@ -156603,7 +156500,7 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq12 GTP_LUT5 /* N118_20 */ #( .INIT(32'b00000000000000100000000000000000)) N118_20 ( - .Z (_N105595), + .Z (_N106419), .I0 (read_data[4]), .I1 (read_data[43]), .I2 (read_data[51]), @@ -156614,26 +156511,26 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq12 GTP_LUT4 /* N118_24 */ #( .INIT(16'b1000000000000000)) N118_24 ( - .Z (_N105599), - .I0 (_N105580), - .I1 (_N105584), - .I2 (_N105588), - .I3 (_N105592)); + .Z (_N106423), + .I0 (_N106404), + .I1 (_N106408), + .I2 (_N106412), + .I3 (_N106416)); // LUT = I0&I1&I2&I3 ; GTP_LUT3 /* N118_25 */ #( .INIT(8'b10000000)) N118_25 ( .Z (N118), - .I0 (_N97689), - .I1 (_N105595), - .I2 (_N105599)); + .I0 (_N98467), + .I1 (_N106419), + .I2 (_N106423)); // LUT = I0&I1&I2 ; - GTP_LUT5 /* N172_67 */ #( + GTP_LUT5 /* N172_66 */ #( .INIT(32'b10000000000000000000000000000000)) - N172_67 ( - .Z (_N105487), + N172_66 ( + .Z (_N106296), .I0 (read_data[16]), .I1 (read_data[18]), .I2 (read_data[24]), @@ -156641,10 +156538,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq12 .I4 (read_data[32])); // LUT = I0&I1&I2&I3&I4 ; - GTP_LUT5 /* N172_71 */ #( + GTP_LUT5 /* N172_70 */ #( .INIT(32'b10000000000000000000000000000000)) - N172_71 ( - .Z (_N105491), + N172_70 ( + .Z (_N106300), .I0 (read_data[34]), .I1 (read_data[40]), .I2 (read_data[42]), @@ -156652,10 +156549,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq12 .I4 (read_data[50])); // LUT = I0&I1&I2&I3&I4 ; - GTP_LUT5 /* N172_75 */ #( + GTP_LUT5 /* N172_74 */ #( .INIT(32'b00000001000000000000000000000000)) - N172_75 ( - .Z (_N105495), + N172_74 ( + .Z (_N106304), .I0 (read_data[1]), .I1 (read_data[5]), .I2 (read_data[7]), @@ -156663,10 +156560,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq12 .I4 (read_data[58])); // LUT = ~I0&~I1&~I2&I3&I4 ; - GTP_LUT5 /* N172_79 */ #( + GTP_LUT5 /* N172_78 */ #( .INIT(32'b00000000000000000000000000000001)) - N172_79 ( - .Z (_N105499), + N172_78 ( + .Z (_N106308), .I0 (read_data[9]), .I1 (read_data[13]), .I2 (read_data[15]), @@ -156674,10 +156571,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq12 .I4 (read_data[21])); // LUT = ~I0&~I1&~I2&~I3&~I4 ; - GTP_LUT5 /* N172_83 */ #( + GTP_LUT5 /* N172_82 */ #( .INIT(32'b00000000000000000000000000000001)) - N172_83 ( - .Z (_N105503), + N172_82 ( + .Z (_N106312), .I0 (read_data[23]), .I1 (read_data[25]), .I2 (read_data[29]), @@ -156685,10 +156582,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq12 .I4 (read_data[33])); // LUT = ~I0&~I1&~I2&~I3&~I4 ; - GTP_LUT5 /* N172_87 */ #( + GTP_LUT5 /* N172_86 */ #( .INIT(32'b00000000000000000000000000000001)) - N172_87 ( - .Z (_N105507), + N172_86 ( + .Z (_N106316), .I0 (read_data[37]), .I1 (read_data[39]), .I2 (read_data[41]), @@ -156696,10 +156593,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq12 .I4 (read_data[47])); // LUT = ~I0&~I1&~I2&~I3&~I4 ; - GTP_LUT5 /* N172_91 */ #( + GTP_LUT5 /* N172_90 */ #( .INIT(32'b00000000000000000000000000000001)) - N172_91 ( - .Z (_N105511), + N172_90 ( + .Z (_N106320), .I0 (read_data[49]), .I1 (read_data[53]), .I2 (read_data[55]), @@ -156707,10 +156604,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq12 .I4 (read_data[61])); // LUT = ~I0&~I1&~I2&~I3&~I4 ; - GTP_LUT5 /* N172_92 */ #( + GTP_LUT5 /* N172_91 */ #( .INIT(32'b00000000000000001000000000000000)) - N172_92 ( - .Z (_N105512), + N172_91 ( + .Z (_N106321), .I0 (read_data[0]), .I1 (read_data[2]), .I2 (read_data[8]), @@ -156718,31 +156615,31 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq12 .I4 (read_data[63])); // LUT = I0&I1&I2&I3&~I4 ; - GTP_LUT4 /* N172_98 */ #( + GTP_LUT4 /* N172_97 */ #( .INIT(16'b1000000000000000)) - N172_98 ( - .Z (_N105518), - .I0 (_N105499), - .I1 (_N105503), - .I2 (_N105507), - .I3 (_N105511)); + N172_97 ( + .Z (_N106327), + .I0 (_N106308), + .I1 (_N106312), + .I2 (_N106316), + .I3 (_N106320)); // LUT = I0&I1&I2&I3 ; - GTP_LUT5 /* N172_99 */ #( + GTP_LUT5 /* N172_98 */ #( .INIT(32'b10000000000000000000000000000000)) - N172_99 ( - .Z (_N97689), - .I0 (_N105487), - .I1 (_N105491), - .I2 (_N105495), - .I3 (_N105512), - .I4 (_N105518)); + N172_98 ( + .Z (_N98467), + .I0 (_N106296), + .I1 (_N106300), + .I2 (_N106304), + .I3 (_N106321), + .I4 (_N106327)); // LUT = I0&I1&I2&I3&I4 ; - GTP_LUT5 /* N172_103 */ #( + GTP_LUT5 /* N172_102 */ #( .INIT(32'b10000000000000000000000000000000)) - N172_103 ( - .Z (_N106422), + N172_102 ( + .Z (_N107240), .I0 (read_data[1]), .I1 (read_data[5]), .I2 (read_data[7]), @@ -156750,10 +156647,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq12 .I4 (read_data[13])); // LUT = I0&I1&I2&I3&I4 ; - GTP_LUT5 /* N172_107 */ #( + GTP_LUT5 /* N172_106 */ #( .INIT(32'b10000000000000000000000000000000)) - N172_107 ( - .Z (_N106426), + N172_106 ( + .Z (_N107244), .I0 (read_data[15]), .I1 (read_data[17]), .I2 (read_data[21]), @@ -156761,10 +156658,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq12 .I4 (read_data[25])); // LUT = I0&I1&I2&I3&I4 ; - GTP_LUT5 /* N172_111 */ #( + GTP_LUT5 /* N172_110 */ #( .INIT(32'b10000000000000000000000000000000)) - N172_111 ( - .Z (_N106430), + N172_110 ( + .Z (_N107248), .I0 (read_data[29]), .I1 (read_data[31]), .I2 (read_data[33]), @@ -156772,10 +156669,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq12 .I4 (read_data[39])); // LUT = I0&I1&I2&I3&I4 ; - GTP_LUT5 /* N172_115 */ #( + GTP_LUT5 /* N172_114 */ #( .INIT(32'b10000000000000000000000000000000)) - N172_115 ( - .Z (_N106434), + N172_114 ( + .Z (_N107252), .I0 (read_data[41]), .I1 (read_data[45]), .I2 (read_data[47]), @@ -156783,10 +156680,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq12 .I4 (read_data[53])); // LUT = I0&I1&I2&I3&I4 ; - GTP_LUT5 /* N172_119 */ #( + GTP_LUT5 /* N172_118 */ #( .INIT(32'b01000000000000000000000000000000)) - N172_119 ( - .Z (_N106438), + N172_118 ( + .Z (_N107256), .I0 (read_data[0]), .I1 (read_data[55]), .I2 (read_data[57]), @@ -156794,10 +156691,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq12 .I4 (read_data[63])); // LUT = ~I0&I1&I2&I3&I4 ; - GTP_LUT5 /* N172_123 */ #( + GTP_LUT5 /* N172_122 */ #( .INIT(32'b00000000000000000000000000000001)) - N172_123 ( - .Z (_N106442), + N172_122 ( + .Z (_N107260), .I0 (read_data[2]), .I1 (read_data[8]), .I2 (read_data[10]), @@ -156805,10 +156702,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq12 .I4 (read_data[18])); // LUT = ~I0&~I1&~I2&~I3&~I4 ; - GTP_LUT5 /* N172_127 */ #( + GTP_LUT5 /* N172_126 */ #( .INIT(32'b00000000000000000000000000000001)) - N172_127 ( - .Z (_N106446), + N172_126 ( + .Z (_N107264), .I0 (read_data[24]), .I1 (read_data[26]), .I2 (read_data[32]), @@ -156816,10 +156713,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq12 .I4 (read_data[40])); // LUT = ~I0&~I1&~I2&~I3&~I4 ; - GTP_LUT5 /* N172_131 */ #( + GTP_LUT5 /* N172_130 */ #( .INIT(32'b00000000000000000000000000000001)) - N172_131 ( - .Z (_N106450), + N172_130 ( + .Z (_N107268), .I0 (read_data[42]), .I1 (read_data[48]), .I2 (read_data[50]), @@ -156827,41 +156724,41 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq12 .I4 (read_data[58])); // LUT = ~I0&~I1&~I2&~I3&~I4 ; - GTP_LUT5 /* N172_135 */ #( + GTP_LUT5 /* N172_134 */ #( .INIT(32'b10000000000000000000000000000000)) - N172_135 ( - .Z (_N106454), - .I0 (_N97685), - .I1 (_N106422), - .I2 (_N106426), - .I3 (_N106430), - .I4 (_N106434)); + N172_134 ( + .Z (_N107272), + .I0 (_N98469), + .I1 (_N107240), + .I2 (_N107244), + .I3 (_N107248), + .I4 (_N107252)); // LUT = I0&I1&I2&I3&I4 ; - GTP_LUT4 /* N172_138 */ #( + GTP_LUT4 /* N172_137 */ #( .INIT(16'b1000000000000000)) - N172_138 ( - .Z (_N106457), - .I0 (_N106438), - .I1 (_N106442), - .I2 (_N106446), - .I3 (_N106450)); + N172_137 ( + .Z (_N107275), + .I0 (_N107256), + .I1 (_N107260), + .I2 (_N107264), + .I3 (_N107268)); // LUT = I0&I1&I2&I3 ; - GTP_LUT4 /* N202_34 */ #( + GTP_LUT4 /* N202_36 */ #( .INIT(16'b1000000000000000)) - N202_34 ( - .Z (_N106398), + N202_36 ( + .Z (_N107216), .I0 (read_data[3]), .I1 (read_data[11]), .I2 (read_data[19]), .I3 (read_data[27])); // LUT = I0&I1&I2&I3 ; - GTP_LUT5 /* N202_38 */ #( + GTP_LUT5 /* N202_40 */ #( .INIT(32'b01000000000000000000000000000000)) - N202_38 ( - .Z (_N106402), + N202_40 ( + .Z (_N107220), .I0 (read_data[4]), .I1 (read_data[35]), .I2 (read_data[43]), @@ -156869,10 +156766,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq12 .I4 (read_data[59])); // LUT = ~I0&I1&I2&I3&I4 ; - GTP_LUT5 /* N202_42 */ #( + GTP_LUT5 /* N202_44 */ #( .INIT(32'b00000000000000000000000000000001)) - N202_42 ( - .Z (_N106406), + N202_44 ( + .Z (_N107224), .I0 (read_data[6]), .I1 (read_data[12]), .I2 (read_data[14]), @@ -156880,10 +156777,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq12 .I4 (read_data[22])); // LUT = ~I0&~I1&~I2&~I3&~I4 ; - GTP_LUT5 /* N202_46 */ #( + GTP_LUT5 /* N202_48 */ #( .INIT(32'b00000000000000000000000000000001)) - N202_46 ( - .Z (_N106410), + N202_48 ( + .Z (_N107228), .I0 (read_data[28]), .I1 (read_data[30]), .I2 (read_data[36]), @@ -156891,10 +156788,10 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq12 .I4 (read_data[44])); // LUT = ~I0&~I1&~I2&~I3&~I4 ; - GTP_LUT5 /* N202_50 */ #( + GTP_LUT5 /* N202_52 */ #( .INIT(32'b00000000000000000000000000000001)) - N202_50 ( - .Z (_N106414), + N202_52 ( + .Z (_N107232), .I0 (read_data[46]), .I1 (read_data[52]), .I2 (read_data[54]), @@ -156902,15 +156799,15 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq12 .I4 (read_data[62])); // LUT = ~I0&~I1&~I2&~I3&~I4 ; - GTP_LUT5 /* N202_54 */ #( + GTP_LUT5 /* N202_56 */ #( .INIT(32'b10000000000000000000000000000000)) - N202_54 ( - .Z (_N97685), - .I0 (_N106398), - .I1 (_N106402), - .I2 (_N106406), - .I3 (_N106410), - .I4 (_N106414)); + N202_56 ( + .Z (_N98469), + .I0 (_N107216), + .I1 (_N107220), + .I2 (_N107224), + .I3 (_N107228), + .I4 (_N107232)); // LUT = I0&I1&I2&I3&I4 ; GTP_DFF_C /* dqs_gate_check_pass */ #( @@ -156968,20 +156865,20 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq12 // LUT = ~I0&I1&I2 ; GTP_LUT5 /* \gdet_state_fsm[2:0]_34 */ #( - .INIT(32'b11101110111011101110111011101100)) + .INIT(32'b11111111111111111010101010101000)) \gdet_state_fsm[2:0]_34 ( .Z (_N9), .I0 (gate_adj_done), - .I1 (_N84566), - .I2 (gdet_state_reg[1]), - .I3 (gdet_state_reg[2]), - .I4 (gdet_state_reg[4])); - // LUT = (I1)|(I0&I2)|(I0&I3)|(I0&I4) ; + .I1 (gdet_state_reg[1]), + .I2 (gdet_state_reg[2]), + .I3 (gdet_state_reg[4]), + .I4 (_N85377)); + // LUT = (I4)|(I0&I1)|(I0&I2)|(I0&I3) ; GTP_LUT2 /* \gdet_state_fsm[2:0]_35 */ #( .INIT(4'b0100)) \gdet_state_fsm[2:0]_35 ( - .Z (_N84566), + .Z (_N85377), .I0 (dqs_gate_vld), .I1 (gdet_state_reg[0])); // LUT = ~I0&I1 ; @@ -157043,14 +156940,14 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq12 .Q (rddata_check_pass), .C (N0), .CLK (ddrphy_clkin), - .D (_N103417)); + .D (_N104229)); // defparam rddata_check_pass_vname.orig_name = rddata_check_pass; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqs_rddata_align_v1_3.vp:416 GTP_LUT5 /* rddata_check_pass_ce_mux */ #( .INIT(32'b11101110111011101110111011100000)) rddata_check_pass_ce_mux ( - .Z (_N103417), + .Z (_N104229), .I0 (rddata_check_pass), .I1 (N118), .I2 (gdet_next_state[0]), @@ -157704,7 +157601,7 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq12 rdel_rvalid_vname ( .Q (rdel_rvalid), .CLK (ddrphy_clkin), - .D (_N103416), + .D (_N104228), .P (N0)); // defparam rdel_rvalid_vname.orig_name = rdel_rvalid; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqs_rddata_align_v1_3.vp:427 @@ -157712,12 +157609,12 @@ module ipsxb_ddrphy_dqs_rddata_align_v1_3_unq12 GTP_LUT5 /* rdel_rvalid_ce_mux */ #( .INIT(32'b11110011011100110111001101110011)) rdel_rvalid_ce_mux ( - .Z (_N103416), + .Z (_N104228), .I0 (read_valid), .I1 (rdel_cal_vld), .I2 (rdel_rvalid), - .I3 (_N106454), - .I4 (_N106457)); + .I3 (_N107272), + .I4 (_N107275)); // LUT = (~I1)|(~I0&I2)|(I2&I3&I4) ; GTP_DFF_C /* rdvalid_r1 */ #( @@ -157738,10 +157635,10 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 ( input [29:0] N734, input [7:0] default_samp_position, - input [9:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt , + input [9:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt , input N0, input _N538, - input _N96167, + input _N96942, input ddrphy_clkin, input init_adj_rdel, input rdel_calibration, @@ -157754,11 +157651,11 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 output [9:0] cnt, output [2:0] rdel_ctrl_wire, output [7:0] total_margin_div2, - output _N81415_3, - output _N81415_5, - output _N83332, - output _N96158, - output _N106490, + output _N82188_3, + output _N82188_5, + output _N84178, + output _N96939, + output _N107308, output adj_rdel_done, output rdel_calib_done, output rdel_calib_error, @@ -157792,67 +157689,67 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 wire _N276; wire _N278; wire _N280; - wire _N5820; - wire _N14836; - wire _N14837; + wire _N5858; + wire _N14809; + wire _N14810; + wire _N14811; + wire _N14812; + wire _N14813; + wire _N14814; + wire _N14815; + wire _N14816; + wire _N14819; + wire _N14820; + wire _N14821; + wire _N14822; + wire _N14823; + wire _N14824; + wire _N14825; wire _N14838; wire _N14839; wire _N14840; wire _N14841; wire _N14842; wire _N14843; - wire _N14846; - wire _N14847; - wire _N14848; - wire _N14849; - wire _N14850; - wire _N14851; - wire _N14852; - wire _N14864; - wire _N14865; - wire _N14866; - wire _N14867; - wire _N14868; - wire _N14869; - wire _N14870; - wire _N14871; - wire _N15479; - wire _N15480; - wire _N15481; - wire _N15482; - wire _N15483; - wire _N15484; - wire _N15485; - wire _N15761; - wire _N15762; - wire _N15763; - wire _N15764; - wire _N15765; - wire _N15766; - wire _N15767; - wire _N30323; - wire _N83434; - wire _N83645; - wire _N88729; - wire _N103418; - wire _N103419; - wire _N103420; - wire _N103421; - wire _N105284; - wire _N105285; - wire _N105286; - wire _N105287; - wire _N106461; - wire _N106462; - wire _N106465; - wire _N106480; - wire _N106482; - wire _N106485; - wire _N106495; - wire _N106496; - wire _N106499; - wire _N106510; - wire _N106555; + wire _N14844; + wire _N14845; + wire _N16278; + wire _N16279; + wire _N16280; + wire _N16281; + wire _N16282; + wire _N16283; + wire _N16284; + wire _N16960; + wire _N16961; + wire _N16962; + wire _N16963; + wire _N16964; + wire _N16965; + wire _N16966; + wire _N30422; + wire _N84280; + wire _N84865; + wire _N89521; + wire _N104230; + wire _N104231; + wire _N104232; + wire _N104233; + wire _N107279; + wire _N107280; + wire _N107283; + wire _N107298; + wire _N107300; + wire _N107303; + wire _N107313; + wire _N107314; + wire _N107317; + wire _N107328; + wire _N107373; + wire _N107431; + wire _N107432; + wire _N107433; + wire _N107434; wire [7:0] left_margin; wire [2:0] rdel_ctrl; wire [3:0] rdel_ov_d; @@ -157869,7 +157766,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N85_1 ( - .COUT (_N14846), + .COUT (_N14819), .Z (total_margin_div2[0]), .CIN (), .I0 (samp_win_size[0]), @@ -157889,9 +157786,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N85_2 ( - .COUT (_N14847), + .COUT (_N14820), .Z (total_margin_div2[1]), - .CIN (_N14846), + .CIN (_N14819), .I0 (samp_win_size[0]), .I1 (samp_win_size[1]), .I2 (samp_win_size[2]), @@ -157909,9 +157806,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N85_3 ( - .COUT (_N14848), + .COUT (_N14821), .Z (total_margin_div2[2]), - .CIN (_N14847), + .CIN (_N14820), .I0 (), .I1 (samp_win_size[3]), .I2 (), @@ -157929,9 +157826,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N85_4 ( - .COUT (_N14849), + .COUT (_N14822), .Z (total_margin_div2[3]), - .CIN (_N14848), + .CIN (_N14821), .I0 (), .I1 (samp_win_size[4]), .I2 (), @@ -157949,9 +157846,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N85_5 ( - .COUT (_N14850), + .COUT (_N14823), .Z (total_margin_div2[4]), - .CIN (_N14849), + .CIN (_N14822), .I0 (), .I1 (samp_win_size[5]), .I2 (), @@ -157969,9 +157866,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N85_6 ( - .COUT (_N14851), + .COUT (_N14824), .Z (total_margin_div2[5]), - .CIN (_N14850), + .CIN (_N14823), .I0 (), .I1 (samp_win_size[6]), .I2 (), @@ -157989,9 +157886,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N85_7 ( - .COUT (_N14852), + .COUT (_N14825), .Z (total_margin_div2[6]), - .CIN (_N14851), + .CIN (_N14824), .I0 (), .I1 (samp_win_size[7]), .I2 (), @@ -158011,7 +157908,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 N85_8 ( .COUT (), .Z (total_margin_div2[7]), - .CIN (_N14852), + .CIN (_N14825), .I0 (), .I1 (total_margin[8]), .I2 (), @@ -158029,7 +157926,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_1 ( - .COUT (_N14836), + .COUT (_N14809), .Z (N604[1]), .CIN (), .I0 (cnt[0]), @@ -158049,9 +157946,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_2 ( - .COUT (_N14837), + .COUT (_N14810), .Z (N604[2]), - .CIN (_N14836), + .CIN (_N14809), .I0 (cnt[0]), .I1 (cnt[1]), .I2 (N694_inv), @@ -158069,9 +157966,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_3 ( - .COUT (_N14838), + .COUT (_N14811), .Z (N604[3]), - .CIN (_N14837), + .CIN (_N14810), .I0 (), .I1 (cnt[3]), .I2 (N694_inv), @@ -158089,9 +157986,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_4 ( - .COUT (_N14839), + .COUT (_N14812), .Z (N604[4]), - .CIN (_N14838), + .CIN (_N14811), .I0 (), .I1 (cnt[4]), .I2 (N694_inv), @@ -158109,9 +158006,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_5 ( - .COUT (_N14840), + .COUT (_N14813), .Z (N604[5]), - .CIN (_N14839), + .CIN (_N14812), .I0 (), .I1 (cnt[5]), .I2 (N694_inv), @@ -158129,9 +158026,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_6 ( - .COUT (_N14841), + .COUT (_N14814), .Z (N604[6]), - .CIN (_N14840), + .CIN (_N14813), .I0 (), .I1 (cnt[6]), .I2 (N694_inv), @@ -158149,9 +158046,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_7 ( - .COUT (_N14842), + .COUT (_N14815), .Z (N604[7]), - .CIN (_N14841), + .CIN (_N14814), .I0 (), .I1 (cnt[7]), .I2 (N694_inv), @@ -158169,9 +158066,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1_8 ( - .COUT (_N14843), + .COUT (_N14816), .Z (N604[8]), - .CIN (_N14842), + .CIN (_N14815), .I0 (), .I1 (cnt[8]), .I2 (N694_inv), @@ -158191,7 +158088,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 N104_1_9 ( .COUT (), .Z (N604[9]), - .CIN (_N14843), + .CIN (_N14816), .I0 (), .I1 (cnt[9]), .I2 (N694_inv), @@ -158417,7 +158314,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .INIT(32'b11001100110011001100110011001000)) \N247_1_1_or[0]_1 ( .Z (N247[1]), - .I0 (_N83645), + .I0 (_N84865), .I1 (cnt[1]), .I2 (state_reg[2]), .I3 (state_reg[7]), @@ -158427,13 +158324,21 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 GTP_LUT4 /* \N247_1_1_or[0]_3 */ #( .INIT(16'b0001000100010000)) \N247_1_1_or[0]_3 ( - .Z (_N83645), + .Z (_N84865), .I0 (cnt[2]), .I1 (cnt[3]), .I2 (state_reg[5]), .I3 (state_reg[9])); // LUT = (~I0&~I1&I2)|(~I0&~I1&I3) ; + GTP_LUT2 /* \N247_1_1_or[0]_4 */ #( + .INIT(4'b1110)) + \N247_1_1_or[0]_4 ( + .Z (N679), + .I0 (state_reg[5]), + .I1 (state_reg[9])); + // LUT = (I0)|(I1) ; + GTP_LUT1 /* N249 */ #( .INIT(2'b01)) N249 ( @@ -158448,7 +158353,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .I4_TO_CARRY("FALSE"), .I4_TO_LUT("FALSE")) N264_1_0 ( - .COUT (_N15479), + .COUT (_N16278), .Z (), .CIN (), .I0 (), @@ -158468,9 +158373,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N264_1_1 ( - .COUT (_N15480), + .COUT (_N16279), .Z (N608[1]), - .CIN (_N15479), + .CIN (_N16278), .I0 (), .I1 (left_margin[1]), .I2 (rdel_calibration), @@ -158488,9 +158393,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N264_1_2 ( - .COUT (_N15481), + .COUT (_N16280), .Z (N608[2]), - .CIN (_N15480), + .CIN (_N16279), .I0 (), .I1 (left_margin[2]), .I2 (rdel_calibration), @@ -158508,9 +158413,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N264_1_3 ( - .COUT (_N15482), + .COUT (_N16281), .Z (N608[3]), - .CIN (_N15481), + .CIN (_N16280), .I0 (), .I1 (left_margin[3]), .I2 (rdel_calibration), @@ -158528,9 +158433,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N264_1_4 ( - .COUT (_N15483), + .COUT (_N16282), .Z (N608[4]), - .CIN (_N15482), + .CIN (_N16281), .I0 (), .I1 (left_margin[4]), .I2 (rdel_calibration), @@ -158548,9 +158453,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N264_1_5 ( - .COUT (_N15484), + .COUT (_N16283), .Z (N608[5]), - .CIN (_N15483), + .CIN (_N16282), .I0 (), .I1 (left_margin[5]), .I2 (rdel_calibration), @@ -158568,9 +158473,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N264_1_6 ( - .COUT (_N15485), + .COUT (_N16284), .Z (N608[6]), - .CIN (_N15484), + .CIN (_N16283), .I0 (), .I1 (left_margin[6]), .I2 (rdel_calibration), @@ -158590,7 +158495,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 N264_1_7 ( .COUT (), .Z (N608[7]), - .CIN (_N15485), + .CIN (_N16284), .I0 (), .I1 (left_margin[7]), .I2 (rdel_calibration), @@ -158608,7 +158513,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .I4_TO_CARRY("FALSE"), .I4_TO_LUT("FALSE")) N280_1_0 ( - .COUT (_N15761), + .COUT (_N16960), .Z (), .CIN (), .I0 (), @@ -158628,9 +158533,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N280_1_1 ( - .COUT (_N15762), + .COUT (_N16961), .Z (N611[1]), - .CIN (_N15761), + .CIN (_N16960), .I0 (), .I1 (right_margin[1]), .I2 (rdel_calibration), @@ -158648,9 +158553,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N280_1_2 ( - .COUT (_N15763), + .COUT (_N16962), .Z (N611[2]), - .CIN (_N15762), + .CIN (_N16961), .I0 (), .I1 (right_margin[2]), .I2 (rdel_calibration), @@ -158668,9 +158573,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N280_1_3 ( - .COUT (_N15764), + .COUT (_N16963), .Z (N611[3]), - .CIN (_N15763), + .CIN (_N16962), .I0 (), .I1 (right_margin[3]), .I2 (rdel_calibration), @@ -158688,9 +158593,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N280_1_4 ( - .COUT (_N15765), + .COUT (_N16964), .Z (N611[4]), - .CIN (_N15764), + .CIN (_N16963), .I0 (), .I1 (right_margin[4]), .I2 (rdel_calibration), @@ -158708,9 +158613,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N280_1_5 ( - .COUT (_N15766), + .COUT (_N16965), .Z (N611[5]), - .CIN (_N15765), + .CIN (_N16964), .I0 (), .I1 (right_margin[5]), .I2 (rdel_calibration), @@ -158728,9 +158633,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N280_1_6 ( - .COUT (_N15767), + .COUT (_N16966), .Z (N611[6]), - .CIN (_N15766), + .CIN (_N16965), .I0 (), .I1 (right_margin[6]), .I2 (rdel_calibration), @@ -158750,7 +158655,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 N280_1_7 ( .COUT (), .Z (N611[7]), - .CIN (_N15767), + .CIN (_N16966), .I0 (), .I1 (right_margin[7]), .I2 (rdel_calibration), @@ -158768,7 +158673,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N285_1_1 ( - .COUT (_N14864), + .COUT (_N14838), .Z (N285[0]), .CIN (), .I0 (right_margin[0]), @@ -158788,9 +158693,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N285_1_2 ( - .COUT (_N14865), + .COUT (_N14839), .Z (N285[1]), - .CIN (_N14864), + .CIN (_N14838), .I0 (right_margin[0]), .I1 (left_margin[0]), .I2 (right_margin[1]), @@ -158808,9 +158713,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N285_1_3 ( - .COUT (_N14866), + .COUT (_N14840), .Z (N285[2]), - .CIN (_N14865), + .CIN (_N14839), .I0 (), .I1 (right_margin[2]), .I2 (left_margin[2]), @@ -158828,9 +158733,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N285_1_4 ( - .COUT (_N14867), + .COUT (_N14841), .Z (N285[3]), - .CIN (_N14866), + .CIN (_N14840), .I0 (), .I1 (right_margin[3]), .I2 (left_margin[3]), @@ -158848,9 +158753,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N285_1_5 ( - .COUT (_N14868), + .COUT (_N14842), .Z (N285[4]), - .CIN (_N14867), + .CIN (_N14841), .I0 (), .I1 (right_margin[4]), .I2 (left_margin[4]), @@ -158868,9 +158773,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N285_1_6 ( - .COUT (_N14869), + .COUT (_N14843), .Z (N285[5]), - .CIN (_N14868), + .CIN (_N14842), .I0 (), .I1 (right_margin[5]), .I2 (left_margin[5]), @@ -158888,9 +158793,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N285_1_7 ( - .COUT (_N14870), + .COUT (_N14844), .Z (N285[6]), - .CIN (_N14869), + .CIN (_N14843), .I0 (), .I1 (right_margin[6]), .I2 (left_margin[6]), @@ -158908,9 +158813,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N285_1_8 ( - .COUT (_N14871), + .COUT (_N14845), .Z (N285[7]), - .CIN (_N14870), + .CIN (_N14844), .I0 (), .I1 (right_margin[7]), .I2 (left_margin[7]), @@ -158930,7 +158835,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 N285_1_9 ( .COUT (), .Z (N285[8]), - .CIN (_N14871), + .CIN (_N14845), .I0 (), .I1 (), .I2 (), @@ -158944,7 +158849,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 GTP_LUT3 /* N295_mux2 */ #( .INIT(8'b00011111)) N295_mux2 ( - .Z (_N5820), + .Z (_N5858), .I0 (samp_win_size[1]), .I1 (samp_win_size[2]), .I2 (samp_win_size[3])); @@ -158974,7 +158879,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 GTP_LUT4 /* \N451_and[0][2] */ #( .INIT(16'b1010101010101000)) \N451_and[0][2] ( - .Z (_N30323), + .Z (_N30422), .I0 (default_samp_position[7]), .I1 (state_reg[1]), .I2 (state_reg[6]), @@ -158984,7 +158889,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 GTP_LUT5M /* N564_20_3 */ #( .INIT(32'b10101010100010001111111111111110)) N564_20_3 ( - .Z (_N106495), + .Z (_N107313), .I0 (rdel_move_en), .I1 (state_reg[5]), .I2 (state_reg[6]), @@ -158996,11 +158901,11 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 GTP_LUT5M /* N564_20_4 */ #( .INIT(32'b11111111101010101111111100000100)) N564_20_4 ( - .Z (_N106496), + .Z (_N107314), .I0 (state_reg[11]), .I1 (state_reg[0]), .I2 (reinit_adj_rdel), - .I3 (_N88729), + .I3 (_N89521), .I4 (rdel_calibration), .ID (init_adj_rdel)); // LUT = (~ID&I1&~I2&~I4)|(I0&I4)|(I3) ; @@ -159008,11 +158913,11 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 GTP_LUT5M /* N564_20_7 */ #( .INIT(32'b11111111111110001111111111111110)) N564_20_7 ( - .Z (_N106499), + .Z (_N107317), .I0 (rdel_move_en), .I1 (state_reg[7]), - .I2 (_N106495), - .I3 (_N106496), + .I2 (_N107313), + .I3 (_N107314), .I4 (N108), .ID (state_reg[2])); // LUT = (I1&~I4)|(ID&~I4)|(I3)|(I2)|(I0&I1) ; @@ -159020,7 +158925,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 GTP_LUT3 /* N564_25 */ #( .INIT(8'b01010100)) N564_25 ( - .Z (_N88729), + .Z (_N89521), .I0 (rdel_move_en), .I1 (state_reg[4]), .I2 (state_reg[8])); @@ -159029,9 +158934,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 GTP_LUT2 /* N564_35 */ #( .INIT(4'b1110)) N564_35 ( - .Z (N679), - .I0 (state_reg[5]), - .I1 (state_reg[9])); + .Z (N603), + .I0 (state_reg[1]), + .I1 (state_reg[6])); // LUT = (I0)|(I1) ; GTP_LUT4 /* N570 */ #( @@ -159041,14 +158946,14 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .I0 (rdel_move_en), .I1 (N167), .I2 (state_reg[10]), - .I3 (_N106499)); + .I3 (_N107317)); // defparam N570_vname.orig_name = N570; // LUT = (~I2&~I3)|(~I0&I1&~I3) ; GTP_LUT5 /* N598_1_2 */ #( .INIT(32'b11111111111111111111111111111110)) N598_1_2 ( - .Z (_N106480), + .Z (_N107298), .I0 (state_reg[0]), .I1 (state_reg[1]), .I2 (state_reg[4]), @@ -159059,12 +158964,12 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 GTP_LUT5 /* N598_1_4 */ #( .INIT(32'b11111111111111110101110100001100)) N598_1_4 ( - .Z (_N106482), + .Z (_N107300), .I0 (N108), .I1 (N679), .I2 (cnt[3]), .I3 (state_reg[7]), - .I4 (_N106480)); + .I4 (_N107298)); // LUT = (I4)|(I1&~I2)|(~I0&I3) ; GTP_LUT5 /* N598_1_6 */ #( @@ -159075,17 +158980,9 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .I1 (N167), .I2 (state_reg[2]), .I3 (state_reg[10]), - .I4 (_N106482)); + .I4 (_N107300)); // LUT = (I4)|(~I1&I3)|(~I0&I2) ; - GTP_LUT2 /* N598_5 */ #( - .INIT(4'b1110)) - N598_5 ( - .Z (N603), - .I0 (state_reg[1]), - .I1 (state_reg[6])); - // LUT = (I0)|(I1) ; - GTP_LUT2 /* \N604_1[0]_1 */ #( .INIT(4'b0100)) \N604_1[0]_1 ( @@ -159144,7 +159041,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 GTP_LUT4 /* N614_1_4 */ #( .INIT(16'b0000000000000001)) N614_1_4 ( - .Z (_N106510), + .Z (_N107328), .I0 (samp_win_size[4]), .I1 (samp_win_size[5]), .I2 (samp_win_size[6]), @@ -159154,7 +159051,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 GTP_LUT4 /* N621_1_2 */ #( .INIT(16'b1110111011101010)) N621_1_2 ( - .Z (_N106555), + .Z (_N107373), .I0 (rdel_calib_done), .I1 (cnt[3]), .I2 (state_reg[5]), @@ -159169,7 +159066,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .I1 (N167), .I2 (state_reg[7]), .I3 (state_reg[10]), - .I4 (_N106555)); + .I4 (_N107373)); // LUT = (I4)|(I0&I2)|(I1&I3) ; GTP_LUT5 /* N694_inv */ #( @@ -159191,14 +159088,14 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .Q (adj_rdel_done), .C (N0), .CLK (ddrphy_clkin), - .D (_N103421)); + .D (_N104233)); // defparam adj_rdel_done_vname.orig_name = adj_rdel_done; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqsi_rdel_cal_v1_2.vp:660 GTP_LUT5 /* adj_rdel_done_ce_mux */ #( .INIT(32'b11111111111000001110000011100000)) adj_rdel_done_ce_mux ( - .Z (_N103421), + .Z (_N104233), .I0 (init_adj_rdel), .I1 (reinit_adj_rdel), .I2 (adj_rdel_done), @@ -159422,17 +159319,17 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .Q (rdel_calib_error), .C (N0), .CLK (ddrphy_clkin), - .D (_N103420)); + .D (_N104232)); // defparam rdel_calib_error_vname.orig_name = rdel_calib_error; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqsi_rdel_cal_v1_2.vp:650 GTP_LUT5M /* rdel_calib_error_ce_mux */ #( .INIT(32'b00100000101000000010001010101010)) rdel_calib_error_ce_mux ( - .Z (_N103420), - .I0 (_N106510), + .Z (_N104232), + .I0 (_N107328), .I1 (state_reg[0]), - .I2 (_N5820), + .I2 (_N5858), .I3 (rdel_calibration), .I4 (state_reg[11]), .ID (rdel_calib_error)); @@ -159465,18 +159362,18 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .Q (rdel_ctrl_wire[2]), .C (N0), .CLK (ddrphy_clkin), - .D (_N103419)); + .D (_N104231)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqsi_rdel_cal_v1_2.vp:564 GTP_LUT5 /* \rdel_ctrl_ce_mux[2] */ #( .INIT(32'b11101110111011101110111011100010)) \rdel_ctrl_ce_mux[2] ( - .Z (_N103419), + .Z (_N104231), .I0 (rdel_ctrl_wire[2]), .I1 (N446), .I2 (state_reg[5]), .I3 (state_reg[10]), - .I4 (_N30323)); + .I4 (_N30422)); // LUT = (I0&~I1)|(I1&I2)|(I1&I3)|(I1&I4) ; GTP_DFF_C /* rdel_move_done */ #( @@ -159537,14 +159434,14 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .Q (rdel_ov_sync), .C (N0), .CLK (ddrphy_clkin), - .D (_N103418)); + .D (_N104230)); // defparam rdel_ov_sync_vname.orig_name = rdel_ov_sync; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqsi_rdel_cal_v1_2.vp:369 GTP_LUT3 /* rdel_ov_sync_ce_mux */ #( .INIT(8'b11101000)) rdel_ov_sync_ce_mux ( - .Z (_N103418), + .Z (_N104230), .I0 (rdel_ov_sync), .I1 (rdel_ov_d[2]), .I2 (rdel_ov_d[3])); @@ -159663,7 +159560,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 \state_fsm[3:0]_135 ( .Z (_N134), .I0 (state_reg[2]), - .I1 (_N96167)); + .I1 (_N96942)); // LUT = I0&I1 ; GTP_LUT5 /* \state_fsm[3:0]_139 */ #( @@ -159706,7 +159603,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 .I1 (cnt[3]), .I2 (state_reg[7]), .I3 (state_reg[9]), - .I4 (_N96167)); + .I4 (_N96942)); // LUT = (~I0&I1&I3)|(~I0&I2&I4) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_dqsi_rdel_cal_v1_2.vp:459 @@ -159733,7 +159630,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 GTP_LUT5 /* \state_fsm[3:0]_540_4 */ #( .INIT(32'b11101111111111101111111111111111)) \state_fsm[3:0]_540_4 ( - .Z (_N106490), + .Z (_N107308), .I0 (cnt[0]), .I1 (cnt[1]), .I2 (cnt[8]), @@ -159744,7 +159641,7 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 GTP_LUT4 /* \state_fsm[3:0]_542_2 */ #( .INIT(16'b1000010000100001)) \state_fsm[3:0]_542_2 ( - .Z (_N106485), + .Z (_N107303), .I0 (cnt[2]), .I1 (cnt[3]), .I2 (total_margin_div2[0]), @@ -159754,18 +159651,18 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 GTP_LUT5 /* \state_fsm[3:0]_542_4 */ #( .INIT(32'b10000100001000010000000000000000)) \state_fsm[3:0]_542_4 ( - .Z (_N81415_3), + .Z (_N82188_3), .I0 (cnt[4]), .I1 (cnt[5]), .I2 (total_margin_div2[2]), .I3 (total_margin_div2[3]), - .I4 (_N106485)); + .I4 (_N107303)); // LUT = (~I0&~I1&~I2&~I3&I4)|(I0&~I1&I2&~I3&I4)|(~I0&I1&~I2&I3&I4)|(I0&I1&I2&I3&I4) ; GTP_LUT4 /* \state_fsm[3:0]_544 */ #( .INIT(16'b1000010000100001)) \state_fsm[3:0]_544 ( - .Z (_N81415_5), + .Z (_N82188_5), .I0 (cnt[6]), .I1 (cnt[7]), .I2 (total_margin_div2[4]), @@ -159775,104 +159672,104 @@ module ipsxb_ddrphy_dqsi_rdel_cal_v1_2_unq12 GTP_LUT5 /* \state_fsm[3:0]_865 */ #( .INIT(32'b10000000001000000100000000010000)) \state_fsm[3:0]_865 ( - .Z (_N83332), + .Z (_N84178), .I0 (default_samp_position[2]), .I1 (default_samp_position[1]), - .I2 (_N83434), + .I2 (_N84280), .I3 (cnt[3]), .I4 (cnt[4])); // LUT = (~I0&~I1&I2&~I3&~I4)|(~I0&I1&I2&I3&~I4)|(I0&~I1&I2&~I3&I4)|(I0&I1&I2&I3&I4) ; - GTP_LUT4 /* \state_fsm[3:0]_3446 */ #( - .INIT(16'b1000010000100001)) - \state_fsm[3:0]_3446 ( - .Z (_N105284), - .I0 (default_samp_position[6]), - .I1 (default_samp_position[5]), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [8] ), - .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [7] )); - // LUT = (~I0&~I1&~I2&~I3)|(I0&~I1&I2&~I3)|(~I0&I1&~I2&I3)|(I0&I1&I2&I3) ; - - GTP_LUT4 /* \state_fsm[3:0]_3447 */ #( - .INIT(16'b1000010000100001)) - \state_fsm[3:0]_3447 ( - .Z (_N105285), - .I0 (default_samp_position[4]), - .I1 (default_samp_position[3]), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [6] ), - .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [5] )); - // LUT = (~I0&~I1&~I2&~I3)|(I0&~I1&I2&~I3)|(~I0&I1&~I2&I3)|(I0&I1&I2&I3) ; - - GTP_LUT4 /* \state_fsm[3:0]_3448 */ #( - .INIT(16'b1000010000100001)) - \state_fsm[3:0]_3448 ( - .Z (_N105286), - .I0 (default_samp_position[2]), - .I1 (default_samp_position[1]), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [4] ), - .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [3] )); - // LUT = (~I0&~I1&~I2&~I3)|(I0&~I1&I2&~I3)|(~I0&I1&~I2&I3)|(I0&I1&I2&I3) ; - - GTP_LUT5 /* \state_fsm[3:0]_3449 */ #( - .INIT(32'b00000000000000000000000000100001)) - \state_fsm[3:0]_3449 ( - .Z (_N105287), - .I0 (default_samp_position[0]), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [9] ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [2] ), - .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [1] ), - .I4 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [0] )); - // LUT = (~I0&~I1&~I2&~I3&~I4)|(I0&~I1&I2&~I3&~I4) ; - - GTP_LUT4 /* \state_fsm[3:0]_3452 */ #( - .INIT(16'b1000000000000000)) - \state_fsm[3:0]_3452 ( - .Z (_N96158), - .I0 (_N105284), - .I1 (_N105285), - .I2 (_N105286), - .I3 (_N105287)); - // LUT = I0&I1&I2&I3 ; - - GTP_LUT4 /* \state_fsm[3:0]_3453 */ #( + GTP_LUT4 /* \state_fsm[3:0]_3409 */ #( .INIT(16'b1000001011000011)) - \state_fsm[3:0]_3453 ( - .Z (_N106461), + \state_fsm[3:0]_3409 ( + .Z (_N107279), .I0 (default_samp_position[4]), .I1 (default_samp_position[0]), .I2 (cnt[2]), .I3 (cnt[6])); // LUT = (~I1&~I2&~I3)|(I1&I2&~I3)|(I0&~I1&~I2)|(I0&I1&I2) ; - GTP_LUT2 /* \state_fsm[3:0]_3454 */ #( + GTP_LUT2 /* \state_fsm[3:0]_3410 */ #( .INIT(4'b1001)) - \state_fsm[3:0]_3454 ( - .Z (_N106462), + \state_fsm[3:0]_3410 ( + .Z (_N107280), .I0 (default_samp_position[3]), .I1 (cnt[5])); // LUT = (~I0&~I1)|(I0&I1) ; - GTP_LUT5 /* \state_fsm[3:0]_3457 */ #( + GTP_LUT5 /* \state_fsm[3:0]_3413 */ #( .INIT(32'b10100010010100010000000000000000)) - \state_fsm[3:0]_3457 ( - .Z (_N106465), + \state_fsm[3:0]_3413 ( + .Z (_N107283), .I0 (default_samp_position[6]), .I1 (default_samp_position[4]), .I2 (cnt[6]), .I3 (cnt[8]), - .I4 (_N106462)); + .I4 (_N107280)); // LUT = (~I0&~I1&~I3&I4)|(~I0&I2&~I3&I4)|(I0&~I1&I3&I4)|(I0&I2&I3&I4) ; - GTP_LUT4 /* \state_fsm[3:0]_3458 */ #( + GTP_LUT4 /* \state_fsm[3:0]_3414 */ #( .INIT(16'b1001000000000000)) - \state_fsm[3:0]_3458 ( - .Z (_N83434), + \state_fsm[3:0]_3414 ( + .Z (_N84280), .I0 (default_samp_position[5]), .I1 (cnt[7]), - .I2 (_N106461), - .I3 (_N106465)); + .I2 (_N107279), + .I3 (_N107283)); // LUT = (~I0&~I1&I2&I3)|(I0&I1&I2&I3) ; + GTP_LUT4 /* \state_fsm[3:0]_3417 */ #( + .INIT(16'b1000010000100001)) + \state_fsm[3:0]_3417 ( + .Z (_N107431), + .I0 (default_samp_position[4]), + .I1 (default_samp_position[3]), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [6] ), + .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [5] )); + // LUT = (~I0&~I1&~I2&~I3)|(I0&~I1&I2&~I3)|(~I0&I1&~I2&I3)|(I0&I1&I2&I3) ; + + GTP_LUT4 /* \state_fsm[3:0]_3418 */ #( + .INIT(16'b1000010000100001)) + \state_fsm[3:0]_3418 ( + .Z (_N107432), + .I0 (default_samp_position[2]), + .I1 (default_samp_position[1]), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [4] ), + .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [3] )); + // LUT = (~I0&~I1&~I2&~I3)|(I0&~I1&I2&~I3)|(~I0&I1&~I2&I3)|(I0&I1&I2&I3) ; + + GTP_LUT4 /* \state_fsm[3:0]_3419 */ #( + .INIT(16'b1000010000100001)) + \state_fsm[3:0]_3419 ( + .Z (_N107433), + .I0 (default_samp_position[6]), + .I1 (default_samp_position[5]), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [8] ), + .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [7] )); + // LUT = (~I0&~I1&~I2&~I3)|(I0&~I1&I2&~I3)|(~I0&I1&~I2&I3)|(I0&I1&I2&I3) ; + + GTP_LUT5 /* \state_fsm[3:0]_3420 */ #( + .INIT(32'b00000000000000000000000000100001)) + \state_fsm[3:0]_3420 ( + .Z (_N107434), + .I0 (default_samp_position[0]), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [9] ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [2] ), + .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [1] ), + .I4 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [0] )); + // LUT = (~I0&~I1&~I2&~I3&~I4)|(I0&~I1&I2&~I3&~I4) ; + + GTP_LUT4 /* \state_fsm[3:0]_3423 */ #( + .INIT(16'b1000000000000000)) + \state_fsm[3:0]_3423 ( + .Z (_N96939), + .I0 (_N107431), + .I1 (_N107432), + .I2 (_N107433), + .I3 (_N107434)); + // LUT = I0&I1&I2&I3 ; + (* syn_encoding="onehot" *) GTP_DFF_PE /* \state_reg[0] */ #( .GRS_EN("TRUE"), .INIT(1'b1)) @@ -160171,17 +160068,20 @@ module ipsxb_ddrphy_data_slice_v1_4_unq12 input [7:0] dll_step, input [29:0] \dqsi_rdel_cal/N734 , input [7:0] \dqsi_rdel_cal/default_samp_position , + input [4:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt , + input [6:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg , input [4:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt , input [6:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg , - input [9:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt , + input [9:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt , input [31:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/phy_wrdata_mask , input [3:0] \wdata_path_adj/phy_wrdata_en_r2 , input [3:0] \wdata_path_adj/phy_wrdata_en_slip4 , - input _N96110, - input _N96167, - input _N96271, - input _N96274, - input _N96887, + input _N96888, + input _N96942, + input _N97033, + input _N97080, + input _N97672, + input _N104452, input \data_slice_dqs_gate_cal/gatecal/N1 , input \data_slice_wrlvl/N449 , input ddrphy_clkin, @@ -160199,6 +160099,7 @@ module ipsxb_ddrphy_data_slice_v1_4_unq12 input rdel_calibration, input rdel_move_en, input reinit_adj_rdel, + input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld , input wrlvl_ck_dly_done, input wrlvl_ck_dly_start, input wrlvl_dqs_req, @@ -160213,17 +160114,18 @@ module ipsxb_ddrphy_data_slice_v1_4_unq12 output [9:0] \dqsi_rdel_cal/cnt , output [7:0] \dqsi_rdel_cal/total_margin_div2 , output [63:0] read_data, - output [4:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484 , - output _N81415_3, - output _N81415_5, - output _N83332, - output _N96158, - output _N96884, - output _N106490, + output _N82188_3, + output _N82188_5, + output _N84178, + output _N96939, + output _N97660, + output _N107042, + output _N107308, output adj_rdel_done, output ck_check_done, output \data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r , output \data_slice_wrlvl/N165 , + output \data_slice_wrlvl/dq_vld , output dm, output dqs_gate_vld, output gate_adj_done, @@ -160282,10 +160184,6 @@ module ipsxb_ddrphy_data_slice_v1_4_unq12 wire \data_slice_dqs_gate_cal_gatecal/gate_state_reg[4]_floating ; wire \data_slice_dqs_gate_cal_gatecal/gate_state_reg[5]_floating ; wire \data_slice_dqs_gate_cal_read_clk_ctrl[2]_floating ; - wire \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484[0]_floating ; - wire \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484[1]_floating ; - wire \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484[2]_floating ; - wire \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484[3]_floating ; wire \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/adj_wrdqs[0]_floating ; wire \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/adj_wrdqs[1]_floating ; wire \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/adj_wrdqs[3]_floating ; @@ -160341,7 +160239,7 @@ module ipsxb_ddrphy_data_slice_v1_4_unq12 .gate_check_error (gate_check_error), .gate_check_pass (gate_check_pass), .\gatecal/dqs_gate_vld_r (\data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r ), - ._N96110 (_N96110), + ._N96888 (_N96888), .ddrphy_clkin (ddrphy_clkin), .dqs_gate_check_pass (dqs_gate_check_pass), .gate_check (gate_check), @@ -160353,17 +160251,20 @@ module ipsxb_ddrphy_data_slice_v1_4_unq12 ipsxb_ddrphy_data_slice_wrlvl_v1_4_unq12 data_slice_wrlvl ( .cnt ({\data_slice_wrlvl/cnt [4] , \data_slice_wrlvl/cnt [3] , \data_slice_wrlvl/cnt [2] , \data_slice_wrlvl/cnt [1] , \data_slice_wrlvl/cnt [0] }), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484 ({\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484 [4] , \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484[3]_floating , \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484[2]_floating , \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484[1]_floating , \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484[0]_floating }), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/adj_wrdqs ({\data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/adj_wrdqs[7]_floating , \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/adj_wrdqs[6]_floating , \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/adj_wrdqs[5]_floating , \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/adj_wrdqs[4]_floating , \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/adj_wrdqs[3]_floating , adj_wrdqs[2], \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/adj_wrdqs[1]_floating , \data_slice_wrlvl_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/adj_wrdqs[0]_floating }), .wl_state_reg ({\data_slice_wrlvl_wl_state_reg[6]_floating , \data_slice_wrlvl_wl_state_reg[5]_floating , \data_slice_wrlvl/wl_state_reg [4] , \data_slice_wrlvl_wl_state_reg[3]_floating , \data_slice_wrlvl_wl_state_reg[2]_floating , \data_slice_wrlvl_wl_state_reg[1]_floating , \data_slice_wrlvl_wl_state_reg[0]_floating }), .wrlvl_step ({debug_data[33], debug_data[32], debug_data[31], debug_data[30], debug_data[29], debug_data[28], debug_data[27], debug_data[26]}), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt ({\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [4] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [1] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [0] }), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt ({1'bx, \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] , 1'bx, 1'bx}), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg ({1'bx, 1'bx, \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg [4] , 1'bx, 1'bx, 1'bx, 1'bx}), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt ({1'bx, \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] , 1'bx, \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [1] , 1'bx}), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg ({1'bx, 1'bx, \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg [4] , 1'bx, 1'bx, 1'bx, 1'bx}), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_in_dly (dq_in_dly), .N165 (\data_slice_wrlvl/N165 ), - ._N96884 (_N96884), + ._N97660 (_N97660), + ._N107042 (_N107042), .ck_check_done (ck_check_done), .ddrphy_gatei (ddrphy_gatei), + .dq_vld (\data_slice_wrlvl/dq_vld ), .wrlvl_ck_dly_flag (wrlvl_ck_dly_flag), .wrlvl_dqs (wrlvl_dqs), .wrlvl_dqs_en (wrlvl_dqs_en), @@ -160371,10 +160272,12 @@ module ipsxb_ddrphy_data_slice_v1_4_unq12 .wrlvl_error (wrlvl_error), .N0 (\data_slice_dqs_gate_cal/gatecal/N1 ), .N449 (\data_slice_wrlvl/N449 ), - ._N96271 (_N96271), - ._N96274 (_N96274), - ._N96887 (_N96887), + ._N97033 (_N97033), + ._N97080 (_N97080), + ._N97672 (_N97672), + ._N104452 (_N104452), .ddrphy_clkin (ddrphy_clkin), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld ), .wrlvl_ck_dly_done (wrlvl_ck_dly_done), .wrlvl_ck_dly_start (wrlvl_ck_dly_start), .wrlvl_dqs_req (wrlvl_dqs_req)); @@ -160850,19 +160753,19 @@ module ipsxb_ddrphy_data_slice_v1_4_unq12 .total_margin_div2 ({\dqsi_rdel_cal/total_margin_div2 [7] , \dqsi_rdel_cal_total_margin_div2[6]_floating , \dqsi_rdel_cal_total_margin_div2[5]_floating , \dqsi_rdel_cal_total_margin_div2[4]_floating , \dqsi_rdel_cal_total_margin_div2[3]_floating , \dqsi_rdel_cal_total_margin_div2[2]_floating , \dqsi_rdel_cal_total_margin_div2[1]_floating , \dqsi_rdel_cal_total_margin_div2[0]_floating }), .N734 ({1'bx, 1'bx, 1'bx, \dqsi_rdel_cal/N734 [26] , 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), .default_samp_position ({\dqsi_rdel_cal/default_samp_position [7] , \dqsi_rdel_cal/default_samp_position [6] , \dqsi_rdel_cal/default_samp_position [5] , \dqsi_rdel_cal/default_samp_position [4] , \dqsi_rdel_cal/default_samp_position [3] , \dqsi_rdel_cal/default_samp_position [2] , \dqsi_rdel_cal/default_samp_position [1] , \dqsi_rdel_cal/default_samp_position [0] }), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt ({\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [9] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [8] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [7] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [6] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [5] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [4] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [3] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [2] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [1] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [0] }), - ._N81415_3 (_N81415_3), - ._N81415_5 (_N81415_5), - ._N83332 (_N83332), - ._N96158 (_N96158), - ._N106490 (_N106490), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt ({\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [9] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [8] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [7] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [6] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [5] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [4] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [3] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [2] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [1] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [0] }), + ._N82188_3 (_N82188_3), + ._N82188_5 (_N82188_5), + ._N84178 (_N84178), + ._N96939 (_N96939), + ._N107308 (_N107308), .adj_rdel_done (adj_rdel_done), .rdel_calib_done (rdel_calib_done), .rdel_calib_error (rdel_calib_error), .rdel_move_done (rdel_move_done), .N0 (\data_slice_dqs_gate_cal/gatecal/N1 ), ._N538 (\dqsi_rdel_cal/_N538 ), - ._N96167 (_N96167), + ._N96942 (_N96942), .ddrphy_clkin (ddrphy_clkin), .init_adj_rdel (init_adj_rdel), .rdel_calibration (rdel_calibration), @@ -163793,18 +163696,18 @@ module ipsxb_ddrphy_slice_top_v1_4 output [3:0] rdel_calib_done_tmp, output [255:0] \u_slice_rddata_align/dqs_read_data_r , output [3:0] \u_slice_rddata_align/dqs_read_valid_r , - output _N81412_3, - output _N81412_5, - output _N81413_3, - output _N81413_5, - output _N81414_3, - output _N81414_5, - output _N81415_3, - output _N81415_5, - output _N105268, - output _N105817, - output _N106490, - output _N106518, + output _N82185_3, + output _N82185_5, + output _N82186_3, + output _N82186_5, + output _N82187_3, + output _N82187_5, + output _N82188_3, + output _N82188_5, + output _N106081, + output _N106639, + output _N107308, + output _N107336, output adj_rdel_done, output gate_adj_done, output gate_check_error, @@ -163834,47 +163737,39 @@ module ipsxb_ddrphy_slice_top_v1_4 wire [7:0] N48; wire N1814; wire [7:0] N1815; - wire _N15389; - wire _N15390; - wire _N15391; - wire _N15392; - wire _N15393; - wire _N15394; - wire _N61124; - wire _N61162; - wire _N61204; - wire _N61345; - wire _N61387; - wire _N61475; - wire _N61483; - wire _N83022; - wire _N83332; - wire _N95825; - wire _N96106; - wire _N96107; - wire _N96109; - wire _N96110; - wire _N96120; - wire _N96124; - wire _N96158; - wire _N96160; - wire _N96167; - wire _N96271; - wire _N96272; - wire _N96274; - wire _N96318; - wire _N96883; + wire _N15903; + wire _N15904; + wire _N15905; + wire _N15906; + wire _N15907; + wire _N15908; + wire _N25006; + wire _N59859; + wire _N59860; + wire _N84178; + wire _N96676; wire _N96884; - wire _N96886; + wire _N96885; wire _N96887; - wire _N96913; - wire _N103339; - wire _N105278; - wire _N105949; - wire _N106218; - wire _N106288; - wire _N106303; - wire _N106624; + wire _N96888; + wire _N96898; + wire _N96900; + wire _N96902; + wire _N96937; + wire _N96939; + wire _N96942; + wire _N97033; + wire _N97080; + wire _N97478; + wire _N97660; + wire _N97662; + wire _N97663; + wire _N97672; + wire _N104151; + wire _N104452; + wire _N106091; + wire _N106767; + wire _N107042; wire [119:0] adj_addr_alias; wire [7:0] adj_cke_alias; wire [7:0] adj_odt_alias; @@ -163893,7 +163788,6 @@ module ipsxb_ddrphy_slice_top_v1_4 wire [3:0] \i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r3 ; wire [2:0] \i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N22 ; wire \i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r ; - wire [2:0] \i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_next ; wire [5:0] \i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg ; wire \i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N449 ; wire [4:0] \i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484 ; @@ -163917,8 +163811,6 @@ module ipsxb_ddrphy_slice_top_v1_4 wire [3:0] \i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src ; wire \i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r ; wire [5:0] \i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg ; - wire \i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N165 ; - wire \i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N449 ; wire [4:0] \i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484 ; wire [4:0] \i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt ; wire \i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld ; @@ -163934,13 +163826,11 @@ module ipsxb_ddrphy_slice_top_v1_4 wire [3:0] \i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src ; wire \i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r ; wire [5:0] \i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg ; - wire \i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N449 ; - wire [4:0] \i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N484 ; wire [4:0] \i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt ; - wire \i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld ; wire [6:0] \i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg ; wire \i_dqs_group[2].u_ddrphy_data_slice/dqs_gate_vld ; - wire \i_dqs_group[2].u_ddrphy_data_slice/wrlvl_dqs_en ; + wire \i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N11 ; + wire [5:0] \i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg ; wire [3:0] \i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj ; wire [3:0] \i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 ; wire [3:0] \i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 ; @@ -163952,6 +163842,7 @@ module ipsxb_ddrphy_slice_top_v1_4 wire \i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N165 ; wire \i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N449 ; wire [4:0] \i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt ; + wire \i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld ; wire [6:0] \i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg ; wire \i_dqs_group[3].u_ddrphy_data_slice/dqs_gate_vld ; wire [3:0] ioclk_ca; @@ -164025,8 +163916,6 @@ module ipsxb_ddrphy_slice_top_v1_4 wire \i_dqs_group[0].u_ddrphy_data_slice_data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r3[3]_floating ; wire \i_dqs_group[0].u_ddrphy_data_slice_data_slice_dqs_gate_cal/gatecal/N22[0]_floating ; wire \i_dqs_group[0].u_ddrphy_data_slice_data_slice_dqs_gate_cal/gatecal/N22[1]_floating ; - wire \i_dqs_group[0].u_ddrphy_data_slice_data_slice_dqs_gate_cal/gatecal/gate_state_next[0]_floating ; - wire \i_dqs_group[0].u_ddrphy_data_slice_data_slice_dqs_gate_cal/gatecal/gate_state_next[1]_floating ; wire \i_dqs_group[0].u_ddrphy_data_slice_data_slice_dqs_gate_cal/gatecal/gate_state_reg[4]_floating ; wire \i_dqs_group[0].u_ddrphy_data_slice_data_slice_dqs_gate_cal/gatecal/gate_state_reg[5]_floating ; wire \i_dqs_group[0].u_ddrphy_data_slice_data_slice_wrlvl/wl_state_reg[0]_floating ; @@ -164109,10 +163998,10 @@ module ipsxb_ddrphy_slice_top_v1_4 wire \i_dqs_group[1].u_ddrphy_data_slice_dqsi_rdel_cal/total_margin_div2[4]_floating ; wire \i_dqs_group[1].u_ddrphy_data_slice_dqsi_rdel_cal/total_margin_div2[5]_floating ; wire \i_dqs_group[1].u_ddrphy_data_slice_dqsi_rdel_cal/total_margin_div2[6]_floating ; - wire \i_dqs_group[1].u_ddrphy_data_slice_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N484[0]_floating ; - wire \i_dqs_group[1].u_ddrphy_data_slice_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N484[1]_floating ; - wire \i_dqs_group[1].u_ddrphy_data_slice_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N484[2]_floating ; - wire \i_dqs_group[1].u_ddrphy_data_slice_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N484[3]_floating ; + wire \i_dqs_group[1].u_ddrphy_data_slice_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484[0]_floating ; + wire \i_dqs_group[1].u_ddrphy_data_slice_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484[1]_floating ; + wire \i_dqs_group[1].u_ddrphy_data_slice_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484[2]_floating ; + wire \i_dqs_group[1].u_ddrphy_data_slice_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484[3]_floating ; wire \i_dqs_group[2].u_ddrphy_data_slice_data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4[0]_floating ; wire \i_dqs_group[2].u_ddrphy_data_slice_data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4[1]_floating ; wire \i_dqs_group[2].u_ddrphy_data_slice_data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4[2]_floating ; @@ -164121,18 +164010,18 @@ module ipsxb_ddrphy_slice_top_v1_4 wire \i_dqs_group[2].u_ddrphy_data_slice_data_slice_dqs_gate_cal/gatecal/gate_state_reg[3]_floating ; wire \i_dqs_group[2].u_ddrphy_data_slice_data_slice_dqs_gate_cal/gatecal/gate_state_reg[4]_floating ; wire \i_dqs_group[2].u_ddrphy_data_slice_data_slice_dqs_gate_cal/gatecal/gate_state_reg[5]_floating ; + wire \i_dqs_group[2].u_ddrphy_data_slice_data_slice_wrlvl/cnt[1]_floating ; wire \i_dqs_group[2].u_ddrphy_data_slice_data_slice_wrlvl/wl_state_reg[0]_floating ; wire \i_dqs_group[2].u_ddrphy_data_slice_data_slice_wrlvl/wl_state_reg[1]_floating ; wire \i_dqs_group[2].u_ddrphy_data_slice_data_slice_wrlvl/wl_state_reg[2]_floating ; wire \i_dqs_group[2].u_ddrphy_data_slice_data_slice_wrlvl/wl_state_reg[3]_floating ; wire \i_dqs_group[2].u_ddrphy_data_slice_data_slice_wrlvl/wl_state_reg[5]_floating ; wire \i_dqs_group[2].u_ddrphy_data_slice_data_slice_wrlvl/wl_state_reg[6]_floating ; - wire \i_dqs_group[2].u_ddrphy_data_slice_dqsi_rdel_cal/cnt[2]_floating ; - wire \i_dqs_group[2].u_ddrphy_data_slice_dqsi_rdel_cal/cnt[4]_floating ; - wire \i_dqs_group[2].u_ddrphy_data_slice_dqsi_rdel_cal/cnt[5]_floating ; - wire \i_dqs_group[2].u_ddrphy_data_slice_dqsi_rdel_cal/cnt[6]_floating ; - wire \i_dqs_group[2].u_ddrphy_data_slice_dqsi_rdel_cal/cnt[7]_floating ; - wire \i_dqs_group[2].u_ddrphy_data_slice_dqsi_rdel_cal/cnt[8]_floating ; + wire \i_dqs_group[2].u_ddrphy_data_slice_dqs_rddata_align/gdet_state_reg[1]_floating ; + wire \i_dqs_group[2].u_ddrphy_data_slice_dqs_rddata_align/gdet_state_reg[2]_floating ; + wire \i_dqs_group[2].u_ddrphy_data_slice_dqs_rddata_align/gdet_state_reg[3]_floating ; + wire \i_dqs_group[2].u_ddrphy_data_slice_dqs_rddata_align/gdet_state_reg[4]_floating ; + wire \i_dqs_group[2].u_ddrphy_data_slice_dqs_rddata_align/gdet_state_reg[5]_floating ; wire \i_dqs_group[2].u_ddrphy_data_slice_dqsi_rdel_cal/total_margin_div2[0]_floating ; wire \i_dqs_group[2].u_ddrphy_data_slice_dqsi_rdel_cal/total_margin_div2[1]_floating ; wire \i_dqs_group[2].u_ddrphy_data_slice_dqsi_rdel_cal/total_margin_div2[2]_floating ; @@ -164140,10 +164029,10 @@ module ipsxb_ddrphy_slice_top_v1_4 wire \i_dqs_group[2].u_ddrphy_data_slice_dqsi_rdel_cal/total_margin_div2[4]_floating ; wire \i_dqs_group[2].u_ddrphy_data_slice_dqsi_rdel_cal/total_margin_div2[5]_floating ; wire \i_dqs_group[2].u_ddrphy_data_slice_dqsi_rdel_cal/total_margin_div2[6]_floating ; - wire \i_dqs_group[2].u_ddrphy_data_slice_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484[0]_floating ; - wire \i_dqs_group[2].u_ddrphy_data_slice_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484[1]_floating ; - wire \i_dqs_group[2].u_ddrphy_data_slice_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484[2]_floating ; - wire \i_dqs_group[2].u_ddrphy_data_slice_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484[3]_floating ; + wire \i_dqs_group[2].u_ddrphy_data_slice_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484[0]_floating ; + wire \i_dqs_group[2].u_ddrphy_data_slice_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484[1]_floating ; + wire \i_dqs_group[2].u_ddrphy_data_slice_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484[2]_floating ; + wire \i_dqs_group[2].u_ddrphy_data_slice_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484[3]_floating ; wire \i_dqs_group[3].u_ddrphy_data_slice_data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4[0]_floating ; wire \i_dqs_group[3].u_ddrphy_data_slice_data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4[1]_floating ; wire \i_dqs_group[3].u_ddrphy_data_slice_data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4[2]_floating ; @@ -164172,10 +164061,6 @@ module ipsxb_ddrphy_slice_top_v1_4 wire \i_dqs_group[3].u_ddrphy_data_slice_dqsi_rdel_cal/total_margin_div2[4]_floating ; wire \i_dqs_group[3].u_ddrphy_data_slice_dqsi_rdel_cal/total_margin_div2[5]_floating ; wire \i_dqs_group[3].u_ddrphy_data_slice_dqsi_rdel_cal/total_margin_div2[6]_floating ; - wire \i_dqs_group[3].u_ddrphy_data_slice_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484[0]_floating ; - wire \i_dqs_group[3].u_ddrphy_data_slice_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484[1]_floating ; - wire \i_dqs_group[3].u_ddrphy_data_slice_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484[2]_floating ; - wire \i_dqs_group[3].u_ddrphy_data_slice_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484[3]_floating ; wire \u_control_path_adj_adj_addr[1]_floating ; wire \u_control_path_adj_adj_addr[2]_floating ; wire \u_control_path_adj_adj_addr[3]_floating ; @@ -164351,6 +164236,16 @@ module ipsxb_ddrphy_slice_top_v1_4 .I3 (wrlvl_dqs_resp_tmp[3])); // LUT = I0&I1&I2&I3 ; + GTP_LUT4 /* N12_4 */ #( + .INIT(16'b1000000000000000)) + N12_4 ( + .Z (wrlvl_ck_dly_done), + .I0 (ck_check_done_tmp[0]), + .I1 (ck_check_done_tmp[1]), + .I2 (ck_check_done_tmp[2]), + .I3 (ck_check_done_tmp[3])); + // LUT = I0&I1&I2&I3 ; + GTP_LUT4 /* N13_4 */ #( .INIT(16'b1000000000000000)) N13_4 ( @@ -164384,7 +164279,7 @@ module ipsxb_ddrphy_slice_top_v1_4 GTP_LUT3 /* N17_1 */ #( .INIT(8'b01000000)) N17_1 ( - .Z (_N96106), + .Z (_N96884), .I0 (\i_dqs_group[0].u_ddrphy_data_slice/dqs_gate_vld ), .I1 (\i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg [2] ), .I2 (\i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r )); @@ -164433,7 +164328,7 @@ module ipsxb_ddrphy_slice_top_v1_4 GTP_LUT3 /* N24_1 */ #( .INIT(8'b01000000)) N24_1 ( - .Z (_N96107), + .Z (_N96885), .I0 (\i_dqs_group[1].u_ddrphy_data_slice/dqs_gate_vld ), .I1 (\i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg [2] ), .I2 (\i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r )); @@ -164479,7 +164374,7 @@ module ipsxb_ddrphy_slice_top_v1_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N48_1_1 ( - .COUT (_N15389), + .COUT (_N15903), .Z (N48[1]), .CIN (), .I0 (ck_dly_set_bin[0]), @@ -164499,9 +164394,9 @@ module ipsxb_ddrphy_slice_top_v1_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N48_1_2 ( - .COUT (_N15390), + .COUT (_N15904), .Z (N48[2]), - .CIN (_N15389), + .CIN (_N15903), .I0 (ck_dly_set_bin[0]), .I1 (ck_dly_set_bin[1]), .I2 (ck_dly_set_bin[2]), @@ -164519,9 +164414,9 @@ module ipsxb_ddrphy_slice_top_v1_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N48_1_3 ( - .COUT (_N15391), + .COUT (_N15905), .Z (N48[3]), - .CIN (_N15390), + .CIN (_N15904), .I0 (), .I1 (ck_dly_set_bin[3]), .I2 (), @@ -164539,9 +164434,9 @@ module ipsxb_ddrphy_slice_top_v1_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N48_1_4 ( - .COUT (_N15392), + .COUT (_N15906), .Z (N48[4]), - .CIN (_N15391), + .CIN (_N15905), .I0 (), .I1 (ck_dly_set_bin[4]), .I2 (), @@ -164559,9 +164454,9 @@ module ipsxb_ddrphy_slice_top_v1_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N48_1_5 ( - .COUT (_N15393), + .COUT (_N15907), .Z (N48[5]), - .CIN (_N15392), + .CIN (_N15906), .I0 (), .I1 (ck_dly_set_bin[5]), .I2 (), @@ -164579,9 +164474,9 @@ module ipsxb_ddrphy_slice_top_v1_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N48_1_6 ( - .COUT (_N15394), + .COUT (_N15908), .Z (N48[6]), - .CIN (_N15393), + .CIN (_N15907), .I0 (), .I1 (ck_dly_set_bin[6]), .I2 (), @@ -164601,7 +164496,7 @@ module ipsxb_ddrphy_slice_top_v1_4 N48_1_7 ( .COUT (), .Z (N48[7]), - .CIN (_N15394), + .CIN (_N15908), .I0 (), .I1 (ck_dly_set_bin[7]), .I2 (), @@ -164624,6 +164519,72 @@ module ipsxb_ddrphy_slice_top_v1_4 // LUT = (I0&~I3)|(I0&~I2)|(~I0&I1) ; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_slice_top_v1_4.v:469 + GTP_LUT4 /* \N1815_2[0] */ #( + .INIT(16'b0111010101000101)) + \N1815_2[0] ( + .Z (N1815[0]), + .I0 (ck_dly_set_bin[0]), + .I1 (wrlvl_ck_dly_done), + .I2 (wrlvl_ck_dly_start), + .I3 (ck_dly_set_bin_tmp[0])); + // LUT = (~I0&~I2)|(~I0&I1)|(~I1&I2&I3) ; + // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_slice_top_v1_4.v:469 + + GTP_LUT4 /* \N1815_2[1] */ #( + .INIT(16'b1111010010110000)) + \N1815_2[1] ( + .Z (N1815[1]), + .I0 (wrlvl_ck_dly_done), + .I1 (wrlvl_ck_dly_start), + .I2 (N48[1]), + .I3 (ck_dly_set_bin_tmp[1])); + // LUT = (~I1&I2)|(I0&I2)|(~I0&I1&I3) ; + // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_slice_top_v1_4.v:469 + + GTP_LUT4 /* \N1815_2[2] */ #( + .INIT(16'b1111010010110000)) + \N1815_2[2] ( + .Z (N1815[2]), + .I0 (wrlvl_ck_dly_done), + .I1 (wrlvl_ck_dly_start), + .I2 (N48[2]), + .I3 (ck_dly_set_bin_tmp[2])); + // LUT = (~I1&I2)|(I0&I2)|(~I0&I1&I3) ; + // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_slice_top_v1_4.v:469 + + GTP_LUT4 /* \N1815_2[3] */ #( + .INIT(16'b1111010010110000)) + \N1815_2[3] ( + .Z (N1815[3]), + .I0 (wrlvl_ck_dly_done), + .I1 (wrlvl_ck_dly_start), + .I2 (N48[3]), + .I3 (ck_dly_set_bin_tmp[3])); + // LUT = (~I1&I2)|(I0&I2)|(~I0&I1&I3) ; + // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_slice_top_v1_4.v:469 + + GTP_LUT4 /* \N1815_2[4] */ #( + .INIT(16'b1111010010110000)) + \N1815_2[4] ( + .Z (N1815[4]), + .I0 (wrlvl_ck_dly_done), + .I1 (wrlvl_ck_dly_start), + .I2 (N48[4]), + .I3 (ck_dly_set_bin_tmp[4])); + // LUT = (~I1&I2)|(I0&I2)|(~I0&I1&I3) ; + // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_slice_top_v1_4.v:469 + + GTP_LUT4 /* \N1815_2[5] */ #( + .INIT(16'b1111010010110000)) + \N1815_2[5] ( + .Z (N1815[5]), + .I0 (wrlvl_ck_dly_done), + .I1 (wrlvl_ck_dly_start), + .I2 (N48[5]), + .I3 (ck_dly_set_bin_tmp[5])); + // LUT = (~I1&I2)|(I0&I2)|(~I0&I1&I3) ; + // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_slice_top_v1_4.v:469 + GTP_LUT4 /* \N1815_2[7] */ #( .INIT(16'b1111010010110000)) \N1815_2[7] ( @@ -164676,7 +164637,7 @@ module ipsxb_ddrphy_slice_top_v1_4 .C (N43), .CE (N1814), .CLK (ddrphy_clkin), - .D (_N61124)); + .D (N1815[0])); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_slice_top_v1_4.v:469 GTP_DFF_CE /* \ck_dly_set_bin[1] */ #( @@ -164687,7 +164648,7 @@ module ipsxb_ddrphy_slice_top_v1_4 .C (N43), .CE (N1814), .CLK (ddrphy_clkin), - .D (_N61162)); + .D (N1815[1])); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_slice_top_v1_4.v:469 GTP_DFF_CE /* \ck_dly_set_bin[2] */ #( @@ -164698,7 +164659,7 @@ module ipsxb_ddrphy_slice_top_v1_4 .C (N43), .CE (N1814), .CLK (ddrphy_clkin), - .D (_N61204)); + .D (N1815[2])); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_slice_top_v1_4.v:469 GTP_DFF_CE /* \ck_dly_set_bin[3] */ #( @@ -164709,7 +164670,7 @@ module ipsxb_ddrphy_slice_top_v1_4 .C (N43), .CE (N1814), .CLK (ddrphy_clkin), - .D (_N61345)); + .D (N1815[3])); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_slice_top_v1_4.v:469 GTP_DFF_CE /* \ck_dly_set_bin[4] */ #( @@ -164720,7 +164681,7 @@ module ipsxb_ddrphy_slice_top_v1_4 .C (N43), .CE (N1814), .CLK (ddrphy_clkin), - .D (_N61387)); + .D (N1815[4])); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_slice_top_v1_4.v:469 GTP_DFF_CE /* \ck_dly_set_bin[5] */ #( @@ -164731,7 +164692,7 @@ module ipsxb_ddrphy_slice_top_v1_4 .C (N43), .CE (N1814), .CLK (ddrphy_clkin), - .D (_N61475)); + .D (N1815[5])); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_slice_top_v1_4.v:469 GTP_DFF_CE /* \ck_dly_set_bin[6] */ #( @@ -164742,91 +164703,28 @@ module ipsxb_ddrphy_slice_top_v1_4 .C (N43), .CE (N1814), .CLK (ddrphy_clkin), - .D (_N61483)); + .D (_N59859)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_slice_top_v1_4.v:469 - GTP_LUT4 /* \ck_dly_set_bin[7:0]_3 */ #( - .INIT(16'b1000000000000000)) - \ck_dly_set_bin[7:0]_3 ( - .Z (wrlvl_ck_dly_done), - .I0 (ck_check_done_tmp[0]), - .I1 (ck_check_done_tmp[1]), - .I2 (ck_check_done_tmp[2]), - .I3 (ck_check_done_tmp[3])); - // LUT = I0&I1&I2&I3 ; - - GTP_LUT3 /* \ck_dly_set_bin[7:0]_9 */ #( - .INIT(8'b11011000)) - \ck_dly_set_bin[7:0]_9 ( - .Z (_N61162), - .I0 (wrlvl_ck_dly_done), - .I1 (N48[1]), - .I2 (ck_dly_set_bin_tmp[1])); - // LUT = (~I0&I2)|(I0&I1) ; - - GTP_LUT3 /* \ck_dly_set_bin[7:0]_54 */ #( - .INIT(8'b11011000)) - \ck_dly_set_bin[7:0]_54 ( - .Z (_N61204), - .I0 (wrlvl_ck_dly_done), - .I1 (N48[2]), - .I2 (ck_dly_set_bin_tmp[2])); - // LUT = (~I0&I2)|(I0&I1) ; - - GTP_LUT3 /* \ck_dly_set_bin[7:0]_255 */ #( - .INIT(8'b11011000)) - \ck_dly_set_bin[7:0]_255 ( - .Z (_N61483), - .I0 (wrlvl_ck_dly_done), - .I1 (N48[6]), - .I2 (ck_dly_set_bin_tmp[6])); - // LUT = (~I0&I2)|(I0&I1) ; - - GTP_LUT3 /* \ck_dly_set_bin[7:0]_383 */ #( - .INIT(8'b11011000)) - \ck_dly_set_bin[7:0]_383 ( - .Z (_N61345), - .I0 (wrlvl_ck_dly_done), - .I1 (N48[3]), - .I2 (ck_dly_set_bin_tmp[3])); - // LUT = (~I0&I2)|(I0&I1) ; - - GTP_LUT4 /* \ck_dly_set_bin[7:0]_384 */ #( - .INIT(16'b1011100011110000)) - \ck_dly_set_bin[7:0]_384 ( - .Z (_N61387), - .I0 (N48[4]), + GTP_LUT3 /* \ck_dly_set_bin[7:0]_0 */ #( + .INIT(8'b10111000)) + \ck_dly_set_bin[7:0]_0 ( + .Z (_N59859), + .I0 (_N59860), .I1 (ck_check_done_tmp[3]), - .I2 (ck_dly_set_bin_tmp[4]), - .I3 (_N96913)); - // LUT = (I2&~I3)|(~I1&I2)|(I0&I1&I3) ; - - GTP_LUT3 /* \ck_dly_set_bin[7:0]_386 */ #( - .INIT(8'b11011000)) - \ck_dly_set_bin[7:0]_386 ( - .Z (_N61475), - .I0 (wrlvl_ck_dly_done), - .I1 (N48[5]), - .I2 (ck_dly_set_bin_tmp[5])); - // LUT = (~I0&I2)|(I0&I1) ; - - GTP_LUT3 /* \ck_dly_set_bin[7:0]_388 */ #( - .INIT(8'b10000000)) - \ck_dly_set_bin[7:0]_388 ( - .Z (_N96913), - .I0 (ck_check_done_tmp[0]), - .I1 (ck_check_done_tmp[1]), - .I2 (ck_check_done_tmp[2])); - // LUT = I0&I1&I2 ; + .I2 (ck_dly_set_bin_tmp[6])); + // LUT = (~I1&I2)|(I0&I1) ; - GTP_LUT3 /* \ck_dly_set_bin[7:0]_3372 */ #( - .INIT(8'b01110100)) - \ck_dly_set_bin[7:0]_3372 ( - .Z (_N61124), - .I0 (ck_dly_set_bin[0]), - .I1 (wrlvl_ck_dly_done), - .I2 (ck_dly_set_bin_tmp[0])); - // LUT = (~I1&I2)|(~I0&I1) ; + GTP_LUT5 /* \ck_dly_set_bin[7:0]_1 */ #( + .INIT(32'b10111111111111111000000000000000)) + \ck_dly_set_bin[7:0]_1 ( + .Z (_N59860), + .I0 (N48[6]), + .I1 (ck_check_done_tmp[0]), + .I2 (ck_check_done_tmp[1]), + .I3 (ck_check_done_tmp[2]), + .I4 (ck_dly_set_bin_tmp[6])); + // LUT = (~I3&I4)|(~I2&I4)|(~I1&I4)|(I0&I1&I2&I3) ; GTP_DFF_CE /* \ck_dly_set_bin[7] */ #( .GRS_EN("TRUE"), @@ -165044,7 +164942,6 @@ module ipsxb_ddrphy_slice_top_v1_4 .\data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r2 ({\i_dqs_group[0].u_ddrphy_data_slice_data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r2[3]_floating , \i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r2 [2] , \i_dqs_group[0].u_ddrphy_data_slice_data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r2[1]_floating , \i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r2 [0] }), .\data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r3 ({\i_dqs_group[0].u_ddrphy_data_slice_data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r3[3]_floating , \i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r3 [2] , \i_dqs_group[0].u_ddrphy_data_slice_data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r3[1]_floating , \i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r3 [0] }), .\data_slice_dqs_gate_cal/gatecal/N22 ({\i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N22 [2] , \i_dqs_group[0].u_ddrphy_data_slice_data_slice_dqs_gate_cal/gatecal/N22[1]_floating , \i_dqs_group[0].u_ddrphy_data_slice_data_slice_dqs_gate_cal/gatecal/N22[0]_floating }), - .\data_slice_dqs_gate_cal/gatecal/gate_state_next ({\i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_next [2] , \i_dqs_group[0].u_ddrphy_data_slice_data_slice_dqs_gate_cal/gatecal/gate_state_next[1]_floating , \i_dqs_group[0].u_ddrphy_data_slice_data_slice_dqs_gate_cal/gatecal/gate_state_next[0]_floating }), .\data_slice_dqs_gate_cal/gatecal/gate_state_reg ({\i_dqs_group[0].u_ddrphy_data_slice_data_slice_dqs_gate_cal/gatecal/gate_state_reg[5]_floating , \i_dqs_group[0].u_ddrphy_data_slice_data_slice_dqs_gate_cal/gatecal/gate_state_reg[4]_floating , \i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg [3] , \i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg [2] , \i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg [1] , \i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg [0] }), .\data_slice_wrlvl/cnt ({\i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [4] , \i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] , \i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] , \i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [1] , \i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [0] }), .\data_slice_wrlvl/wl_state_reg ({\i_dqs_group[0].u_ddrphy_data_slice_data_slice_wrlvl/wl_state_reg[6]_floating , \i_dqs_group[0].u_ddrphy_data_slice_data_slice_wrlvl/wl_state_reg[5]_floating , \i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg [4] , \i_dqs_group[0].u_ddrphy_data_slice_data_slice_wrlvl/wl_state_reg[3]_floating , \i_dqs_group[0].u_ddrphy_data_slice_data_slice_wrlvl/wl_state_reg[2]_floating , \i_dqs_group[0].u_ddrphy_data_slice_data_slice_wrlvl/wl_state_reg[1]_floating , \i_dqs_group[0].u_ddrphy_data_slice_data_slice_wrlvl/wl_state_reg[0]_floating }), @@ -165069,9 +164966,10 @@ module ipsxb_ddrphy_slice_top_v1_4 .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3 ({\i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3 [3] , \i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3 [2] , \i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3 [1] , \i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3 [0] }), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4 ({\i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4 [3] , 1'bx, 1'bx, 1'bx}), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src ({\i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [3] , \i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [2] , \i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [1] , \i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [0] }), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt ({1'bx, \i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] , \i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] , 1'bx, 1'bx}), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt ({\i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [4] , \i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] , \i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] , 1'bx, \i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [0] }), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg ({1'bx, 1'bx, \i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg [4] , 1'bx, 1'bx, 1'bx, 1'bx}), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg [0] }), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt ({\i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [9] , \i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [8] , \i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [7] , \i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [6] , \i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [5] , \i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [4] , \i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [3] , \i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [2] , \i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [1] , \i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [0] }), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 ({\i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 [3] , \i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 [2] , \i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 [1] , \i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 [0] }), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 ({\i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [3] , \i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [2] , \i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [1] , \i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [0] }), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3 ({\i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3 [3] , \i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3 [2] , \i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3 [1] , \i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3 [0] }), @@ -165080,33 +164978,33 @@ module ipsxb_ddrphy_slice_top_v1_4 .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg ({1'bx, 1'bx, 1'bx, \i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg [2] , 1'bx, 1'bx}), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt ({\i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt [4] , \i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] , \i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] , 1'bx, \i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt [0] }), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg ({1'bx, 1'bx, \i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg [4] , 1'bx, 1'bx, 1'bx, 1'bx}), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt ({\i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [9] , 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [3] , 1'bx, \i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [1] , \i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [0] }), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 ({\i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 [3] , \i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 [2] , \i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 [1] , \i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1 [0] }), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 ({\i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [3] , \i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [2] , \i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [1] , \i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2 [0] }), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3 ({\i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3 [3] , \i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3 [2] , \i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3 [1] , \i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3 [0] }), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4 ({\i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4 [3] , 1'bx, 1'bx, 1'bx}), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src ({\i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [3] , \i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [2] , \i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [1] , \i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [0] }), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg ({1'bx, 1'bx, 1'bx, \i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg [2] , 1'bx, 1'bx}), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt ({\i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [4] , \i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] , \i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] , \i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [1] , \i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [0] }), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt ({1'bx, \i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] , \i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] , 1'bx, \i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [0] }), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg ({1'bx, 1'bx, \i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg [4] , 1'bx, 1'bx, 1'bx, 1'bx}), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt ({\i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [9] , 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [1] , \i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [0] }), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_flag_tmp ({wrlvl_ck_dly_flag_tmp[3], wrlvl_ck_dly_flag_tmp[2], wrlvl_ck_dly_flag_tmp[1], 1'bx}), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/phy_wrdata_mask ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, adj_wrdata_mask[6], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, adj_wrdata_mask[2], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, adj_wrdata_mask[0]}), .dqs (mem_dqs[0]), .dqs_n (mem_dqs_n[0]), - ._N81412_3 (_N81412_3), - ._N81412_5 (_N81412_5), - ._N96109 (_N96109), - ._N96110 (_N96110), - ._N96120 (_N96120), - ._N96124 (_N96124), - ._N96160 (_N96160), - ._N96167 (_N96167), - ._N96886 (_N96886), + ._N25006 (_N25006), + ._N82185_3 (_N82185_3), + ._N82185_5 (_N82185_5), ._N96887 (_N96887), - ._N105817 (_N105817), - ._N106288 (_N106288), - ._N106624 (_N106624), + ._N96888 (_N96888), + ._N96898 (_N96898), + ._N96900 (_N96900), + ._N96902 (_N96902), + ._N96937 (_N96937), + ._N96942 (_N96942), + ._N97080 (_N97080), + ._N97662 (_N97662), + ._N97663 (_N97663), + ._N104452 (_N104452), + ._N106639 (_N106639), .adj_rdel_done (adj_rdel_done_tmp[0]), .ck_check_done (ck_check_done_tmp[0]), .\data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r (\i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r ), @@ -165125,22 +165023,18 @@ module ipsxb_ddrphy_slice_top_v1_4 .rdel_calib_error (rdel_calib_error_tmp[0]), .rdel_move_done (rdel_move_done_tmp[0]), .read_valid (dqs_read_valid[0]), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N449 (\i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N449 ), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N11 (\i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/_N11 ), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N449 (\i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N449 ), - .wrlvl_ck_dly_start (wrlvl_ck_dly_start), + .wrlvl_ck_dly_flag (wrlvl_ck_dly_flag_tmp[0]), .wrlvl_dqs_en (\i_dqs_group[0].u_ddrphy_data_slice/wrlvl_dqs_en ), .wrlvl_dqs_resp (wrlvl_dqs_resp_tmp[0]), .wrlvl_error (wrlvl_error_tmp[0]), - ._N83022 (_N83022), - ._N83332 (_N83332), - ._N95825 (_N95825), - ._N96106 (_N96106), - ._N96271 (_N96271), - ._N96318 (_N96318), - ._N96883 (_N96883), - ._N105278 (_N105278), - ._N105949 (_N105949), + ._N84178 (_N84178), + ._N96676 (_N96676), + ._N96884 (_N96884), + ._N97478 (_N97478), + ._N97660 (_N97660), + ._N106091 (_N106091), + ._N106767 (_N106767), .\data_slice_dqs_gate_cal/gatecal/N1 (N25), .\data_slice_wrlvl/N449 (\i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N449 ), .ddrphy_clkin (ddrphy_clkin), @@ -165155,15 +165049,14 @@ module ipsxb_ddrphy_slice_top_v1_4 .rdel_calibration (rdel_calibration), .rdel_move_en (rdel_move_en), .reinit_adj_rdel (reinit_adj_rdel), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N165 (\i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N165 ), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_gate_vld (\i_dqs_group[1].u_ddrphy_data_slice/dqs_gate_vld ), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r (\i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r ), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld (\i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld ), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_gate_vld (\i_dqs_group[2].u_ddrphy_data_slice/dqs_gate_vld ), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r (\i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r ), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N165 (\i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N165 ), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld (\i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld ), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_gate_vld (\i_dqs_group[3].u_ddrphy_data_slice/dqs_gate_vld ), .wrlvl_ck_dly_done (wrlvl_ck_dly_done), + .wrlvl_ck_dly_start (wrlvl_ck_dly_start), .wrlvl_dqs_req (wrlvl_dqs_req)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_slice_top_v1_4.v:544 @@ -165181,7 +165074,7 @@ module ipsxb_ddrphy_slice_top_v1_4 .\dqsi_rdel_cal/cnt ({\i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [9] , \i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [8] , \i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [7] , \i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [6] , \i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [5] , \i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [4] , \i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [3] , \i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [2] , \i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [1] , \i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [0] }), .\dqsi_rdel_cal/total_margin_div2 ({\i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin_div2 [7] , \i_dqs_group[1].u_ddrphy_data_slice_dqsi_rdel_cal/total_margin_div2[6]_floating , \i_dqs_group[1].u_ddrphy_data_slice_dqsi_rdel_cal/total_margin_div2[5]_floating , \i_dqs_group[1].u_ddrphy_data_slice_dqsi_rdel_cal/total_margin_div2[4]_floating , \i_dqs_group[1].u_ddrphy_data_slice_dqsi_rdel_cal/total_margin_div2[3]_floating , \i_dqs_group[1].u_ddrphy_data_slice_dqsi_rdel_cal/total_margin_div2[2]_floating , \i_dqs_group[1].u_ddrphy_data_slice_dqsi_rdel_cal/total_margin_div2[1]_floating , \i_dqs_group[1].u_ddrphy_data_slice_dqsi_rdel_cal/total_margin_div2[0]_floating }), .read_data ({dqs_read_data[127], dqs_read_data[126], dqs_read_data[125], dqs_read_data[124], dqs_read_data[123], dqs_read_data[122], dqs_read_data[121], dqs_read_data[120], dqs_read_data[119], dqs_read_data[118], dqs_read_data[117], dqs_read_data[116], dqs_read_data[115], dqs_read_data[114], dqs_read_data[113], dqs_read_data[112], dqs_read_data[111], dqs_read_data[110], dqs_read_data[109], dqs_read_data[108], dqs_read_data[107], dqs_read_data[106], dqs_read_data[105], dqs_read_data[104], dqs_read_data[103], dqs_read_data[102], dqs_read_data[101], dqs_read_data[100], dqs_read_data[99], dqs_read_data[98], dqs_read_data[97], dqs_read_data[96], dqs_read_data[95], dqs_read_data[94], dqs_read_data[93], dqs_read_data[92], dqs_read_data[91], dqs_read_data[90], dqs_read_data[89], dqs_read_data[88], dqs_read_data[87], dqs_read_data[86], dqs_read_data[85], dqs_read_data[84], dqs_read_data[83], dqs_read_data[82], dqs_read_data[81], dqs_read_data[80], dqs_read_data[79], dqs_read_data[78], dqs_read_data[77], dqs_read_data[76], dqs_read_data[75], dqs_read_data[74], dqs_read_data[73], dqs_read_data[72], dqs_read_data[71], dqs_read_data[70], dqs_read_data[69], dqs_read_data[68], dqs_read_data[67], dqs_read_data[66], dqs_read_data[65], dqs_read_data[64]}), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N484 ({\i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N484 [4] , \i_dqs_group[1].u_ddrphy_data_slice_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N484[3]_floating , \i_dqs_group[1].u_ddrphy_data_slice_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N484[2]_floating , \i_dqs_group[1].u_ddrphy_data_slice_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N484[1]_floating , \i_dqs_group[1].u_ddrphy_data_slice_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N484[0]_floating }), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484 ({\i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484 [4] , \i_dqs_group[1].u_ddrphy_data_slice_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484[3]_floating , \i_dqs_group[1].u_ddrphy_data_slice_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484[2]_floating , \i_dqs_group[1].u_ddrphy_data_slice_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484[1]_floating , \i_dqs_group[1].u_ddrphy_data_slice_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484[0]_floating }), .adj_wrdata_mask ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, adj_wrdata_mask[2], 1'bx, 1'bx}), .adj_wrdq ({phy_wrdata[239], phy_wrdata[207], phy_wrdata[175], phy_wrdata[143], phy_wrdata[111], phy_wrdata[79], phy_wrdata[47], phy_wrdata[15], phy_wrdata[238], phy_wrdata[206], phy_wrdata[174], phy_wrdata[142], phy_wrdata[110], phy_wrdata[78], phy_wrdata[46], phy_wrdata[14], phy_wrdata[237], phy_wrdata[205], phy_wrdata[173], phy_wrdata[141], phy_wrdata[109], phy_wrdata[77], phy_wrdata[45], phy_wrdata[13], phy_wrdata[236], phy_wrdata[204], phy_wrdata[172], phy_wrdata[140], phy_wrdata[108], phy_wrdata[76], phy_wrdata[44], phy_wrdata[12], phy_wrdata[235], phy_wrdata[203], phy_wrdata[171], phy_wrdata[139], phy_wrdata[107], phy_wrdata[75], phy_wrdata[43], phy_wrdata[11], phy_wrdata[234], phy_wrdata[202], phy_wrdata[170], phy_wrdata[138], phy_wrdata[106], phy_wrdata[74], phy_wrdata[42], phy_wrdata[10], phy_wrdata[233], phy_wrdata[201], phy_wrdata[169], phy_wrdata[137], phy_wrdata[105], phy_wrdata[73], phy_wrdata[41], phy_wrdata[9], phy_wrdata[232], phy_wrdata[200], phy_wrdata[168], phy_wrdata[136], phy_wrdata[104], phy_wrdata[72], phy_wrdata[40], phy_wrdata[8]}), .adj_wrdq_en ({\i_dqs_group[0].u_ddrphy_data_slice/adj_wrdq_en [3] , \i_dqs_group[0].u_ddrphy_data_slice/adj_wrdq_en [2] , \i_dqs_group[0].u_ddrphy_data_slice/adj_wrdq_en [1] , \i_dqs_group[0].u_ddrphy_data_slice/adj_wrdq_en [0] }), @@ -165195,24 +165088,28 @@ module ipsxb_ddrphy_slice_top_v1_4 .\dqsi_rdel_cal/N734 ({1'bx, 1'bx, 1'bx, \i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N734 [26] , 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), .\dqsi_rdel_cal/default_samp_position ({\i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position [7] , \i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position [6] , \i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position [5] , \i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position [4] , \i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position [3] , \i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position [2] , \i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position [1] , \i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position [0] }), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N22 ({\i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/N22 [2] , 1'bx, 1'bx}), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_next ({\i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_next [2] , 1'bx, 1'bx}), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg ({1'bx, 1'bx, \i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg [3] , \i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg [2] , \i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg [1] , \i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg [0] }), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt ({\i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt [4] , \i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] , \i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] , \i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt [1] , \i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt [0] }), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt ({\i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [4] , \i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] , \i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] , \i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [1] , \i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [0] }), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg ({1'bx, 1'bx, \i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg [4] , 1'bx, 1'bx, 1'bx, 1'bx}), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg [0] }), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt ({\i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [4] , 1'bx, 1'bx, \i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [1] , \i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [0] }), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg ({1'bx, 1'bx, \i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg [4] , 1'bx, 1'bx, 1'bx, 1'bx}), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_flag_tmp ({wrlvl_ck_dly_flag_tmp[3], wrlvl_ck_dly_flag_tmp[2], 1'bx, wrlvl_ck_dly_flag_tmp[0]}), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/phy_wrdata_mask ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, adj_wrdata_mask[6], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, adj_wrdata_mask[0]}), .\wdata_path_adj/phy_wrdata_en_r2 ({\i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_r2 [3] , 1'bx, 1'bx, 1'bx}), .\wdata_path_adj/phy_wrdata_en_slip4 ({\i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_slip4 [3] , \i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_slip4 [2] , \i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_slip4 [1] , \i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_slip4 [0] }), .dqs (mem_dqs[1]), .dqs_n (mem_dqs_n[1]), - ._N81413_3 (_N81413_3), - ._N81413_5 (_N81413_5), - ._N95825 (_N95825), - ._N105268 (_N105268), - ._N105278 (_N105278), - ._N106303 (_N106303), + ._N82186_3 (_N82186_3), + ._N82186_5 (_N82186_5), + ._N96676 (_N96676), + ._N97478 (_N97478), + ._N97672 (_N97672), + ._N106081 (_N106081), + ._N106091 (_N106091), .adj_rdel_done (adj_rdel_done_tmp[1]), .ck_check_done (ck_check_done_tmp[1]), .\data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r (\i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r ), - .\data_slice_wrlvl/N165 (\i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N165 ), .\data_slice_wrlvl/dq_vld (\i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld ), .dm (mem_dm[1]), .dqs_gate_vld (\i_dqs_group[1].u_ddrphy_data_slice/dqs_gate_vld ), @@ -165225,20 +165122,20 @@ module ipsxb_ddrphy_slice_top_v1_4 .rdel_calib_error (rdel_calib_error_tmp[1]), .rdel_move_done (rdel_move_done_tmp[1]), .read_valid (dqs_read_valid[1]), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N449 (\i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N449 ), - .wrlvl_ck_dly_flag (wrlvl_ck_dly_flag_tmp[1]), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N449 (\i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N449 ), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N11 (\i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N11 ), + .wrlvl_ck_dly_start (wrlvl_ck_dly_start), .wrlvl_dqs_resp (wrlvl_dqs_resp_tmp[1]), .wrlvl_error (wrlvl_error_tmp[1]), - ._N96107 (_N96107), - ._N96124 (_N96124), - ._N96158 (_N96158), - ._N96272 (_N96272), - ._N96318 (_N96318), - ._N96884 (_N96884), - ._N96886 (_N96886), - ._N106218 (_N106218), + ._N25006 (_N25006), + ._N96885 (_N96885), + ._N96898 (_N96898), + ._N96900 (_N96900), + ._N96937 (_N96937), + ._N97660 (_N97660), + ._N97662 (_N97662), + ._N107042 (_N107042), .\data_slice_dqs_gate_cal/gatecal/N1 (N25), - .\data_slice_wrlvl/N449 (\i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N449 ), .ddrphy_clkin (ddrphy_clkin), .ddrphy_dqs_rst (ddrphy_dqs_rst), .ddrphy_dqs_training_rstn (ddrphy_dqs_training_rstn), @@ -165255,10 +165152,10 @@ module ipsxb_ddrphy_slice_top_v1_4 .rdel_calibration (rdel_calibration), .rdel_move_en (rdel_move_en), .reinit_adj_rdel (reinit_adj_rdel), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld (\i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld ), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/wrlvl_dqs_en (\i_dqs_group[2].u_ddrphy_data_slice/wrlvl_dqs_en ), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld (\i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld ), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wrlvl_dqs_en (\i_dqs_group[0].u_ddrphy_data_slice/wrlvl_dqs_en ), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_gate_vld (\i_dqs_group[2].u_ddrphy_data_slice/dqs_gate_vld ), .wrlvl_ck_dly_done (wrlvl_ck_dly_done), - .wrlvl_ck_dly_start (wrlvl_ck_dly_start), .wrlvl_dqs_req (wrlvl_dqs_req)); // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_slice_top_v1_4.v:544 @@ -165270,12 +165167,13 @@ module ipsxb_ddrphy_slice_top_v1_4 .\data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4 ({\i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4 [3] , \i_dqs_group[2].u_ddrphy_data_slice_data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4[2]_floating , \i_dqs_group[2].u_ddrphy_data_slice_data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4[1]_floating , \i_dqs_group[2].u_ddrphy_data_slice_data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4[0]_floating }), .\data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src ({\i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [3] , \i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [2] , \i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [1] , \i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src [0] }), .\data_slice_dqs_gate_cal/gatecal/gate_state_reg ({\i_dqs_group[2].u_ddrphy_data_slice_data_slice_dqs_gate_cal/gatecal/gate_state_reg[5]_floating , \i_dqs_group[2].u_ddrphy_data_slice_data_slice_dqs_gate_cal/gatecal/gate_state_reg[4]_floating , \i_dqs_group[2].u_ddrphy_data_slice_data_slice_dqs_gate_cal/gatecal/gate_state_reg[3]_floating , \i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg [2] , \i_dqs_group[2].u_ddrphy_data_slice_data_slice_dqs_gate_cal/gatecal/gate_state_reg[1]_floating , \i_dqs_group[2].u_ddrphy_data_slice_data_slice_dqs_gate_cal/gatecal/gate_state_reg[0]_floating }), - .\data_slice_wrlvl/cnt ({\i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt [4] , \i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] , \i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] , \i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt [1] , \i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt [0] }), + .\data_slice_wrlvl/cnt ({\i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt [4] , \i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] , \i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] , \i_dqs_group[2].u_ddrphy_data_slice_data_slice_wrlvl/cnt[1]_floating , \i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt [0] }), .\data_slice_wrlvl/wl_state_reg ({\i_dqs_group[2].u_ddrphy_data_slice_data_slice_wrlvl/wl_state_reg[6]_floating , \i_dqs_group[2].u_ddrphy_data_slice_data_slice_wrlvl/wl_state_reg[5]_floating , \i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg [4] , \i_dqs_group[2].u_ddrphy_data_slice_data_slice_wrlvl/wl_state_reg[3]_floating , \i_dqs_group[2].u_ddrphy_data_slice_data_slice_wrlvl/wl_state_reg[2]_floating , \i_dqs_group[2].u_ddrphy_data_slice_data_slice_wrlvl/wl_state_reg[1]_floating , \i_dqs_group[2].u_ddrphy_data_slice_data_slice_wrlvl/wl_state_reg[0]_floating }), - .\dqsi_rdel_cal/cnt ({\i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [9] , \i_dqs_group[2].u_ddrphy_data_slice_dqsi_rdel_cal/cnt[8]_floating , \i_dqs_group[2].u_ddrphy_data_slice_dqsi_rdel_cal/cnt[7]_floating , \i_dqs_group[2].u_ddrphy_data_slice_dqsi_rdel_cal/cnt[6]_floating , \i_dqs_group[2].u_ddrphy_data_slice_dqsi_rdel_cal/cnt[5]_floating , \i_dqs_group[2].u_ddrphy_data_slice_dqsi_rdel_cal/cnt[4]_floating , \i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [3] , \i_dqs_group[2].u_ddrphy_data_slice_dqsi_rdel_cal/cnt[2]_floating , \i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [1] , \i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [0] }), + .\dqs_rddata_align/gdet_state_reg ({\i_dqs_group[2].u_ddrphy_data_slice_dqs_rddata_align/gdet_state_reg[5]_floating , \i_dqs_group[2].u_ddrphy_data_slice_dqs_rddata_align/gdet_state_reg[4]_floating , \i_dqs_group[2].u_ddrphy_data_slice_dqs_rddata_align/gdet_state_reg[3]_floating , \i_dqs_group[2].u_ddrphy_data_slice_dqs_rddata_align/gdet_state_reg[2]_floating , \i_dqs_group[2].u_ddrphy_data_slice_dqs_rddata_align/gdet_state_reg[1]_floating , \i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg [0] }), + .\dqsi_rdel_cal/cnt ({\i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [9] , \i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [8] , \i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [7] , \i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [6] , \i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [5] , \i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [4] , \i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [3] , \i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [2] , \i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [1] , \i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [0] }), .\dqsi_rdel_cal/total_margin_div2 ({\i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin_div2 [7] , \i_dqs_group[2].u_ddrphy_data_slice_dqsi_rdel_cal/total_margin_div2[6]_floating , \i_dqs_group[2].u_ddrphy_data_slice_dqsi_rdel_cal/total_margin_div2[5]_floating , \i_dqs_group[2].u_ddrphy_data_slice_dqsi_rdel_cal/total_margin_div2[4]_floating , \i_dqs_group[2].u_ddrphy_data_slice_dqsi_rdel_cal/total_margin_div2[3]_floating , \i_dqs_group[2].u_ddrphy_data_slice_dqsi_rdel_cal/total_margin_div2[2]_floating , \i_dqs_group[2].u_ddrphy_data_slice_dqsi_rdel_cal/total_margin_div2[1]_floating , \i_dqs_group[2].u_ddrphy_data_slice_dqsi_rdel_cal/total_margin_div2[0]_floating }), .read_data ({dqs_read_data[191], dqs_read_data[190], dqs_read_data[189], dqs_read_data[188], dqs_read_data[187], dqs_read_data[186], dqs_read_data[185], dqs_read_data[184], dqs_read_data[183], dqs_read_data[182], dqs_read_data[181], dqs_read_data[180], dqs_read_data[179], dqs_read_data[178], dqs_read_data[177], dqs_read_data[176], dqs_read_data[175], dqs_read_data[174], dqs_read_data[173], dqs_read_data[172], dqs_read_data[171], dqs_read_data[170], dqs_read_data[169], dqs_read_data[168], dqs_read_data[167], dqs_read_data[166], dqs_read_data[165], dqs_read_data[164], dqs_read_data[163], dqs_read_data[162], dqs_read_data[161], dqs_read_data[160], dqs_read_data[159], dqs_read_data[158], dqs_read_data[157], dqs_read_data[156], dqs_read_data[155], dqs_read_data[154], dqs_read_data[153], dqs_read_data[152], dqs_read_data[151], dqs_read_data[150], dqs_read_data[149], dqs_read_data[148], dqs_read_data[147], dqs_read_data[146], dqs_read_data[145], dqs_read_data[144], dqs_read_data[143], dqs_read_data[142], dqs_read_data[141], dqs_read_data[140], dqs_read_data[139], dqs_read_data[138], dqs_read_data[137], dqs_read_data[136], dqs_read_data[135], dqs_read_data[134], dqs_read_data[133], dqs_read_data[132], dqs_read_data[131], dqs_read_data[130], dqs_read_data[129], dqs_read_data[128]}), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484 ({\i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484 [4] , \i_dqs_group[2].u_ddrphy_data_slice_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484[3]_floating , \i_dqs_group[2].u_ddrphy_data_slice_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484[2]_floating , \i_dqs_group[2].u_ddrphy_data_slice_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484[1]_floating , \i_dqs_group[2].u_ddrphy_data_slice_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N484[0]_floating }), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484 ({\i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484 [4] , \i_dqs_group[2].u_ddrphy_data_slice_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484[3]_floating , \i_dqs_group[2].u_ddrphy_data_slice_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484[2]_floating , \i_dqs_group[2].u_ddrphy_data_slice_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484[1]_floating , \i_dqs_group[2].u_ddrphy_data_slice_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484[0]_floating }), .adj_wrdata_mask ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, adj_wrdata_mask[0]}), .adj_wrdq ({phy_wrdata[247], phy_wrdata[215], phy_wrdata[183], phy_wrdata[151], phy_wrdata[119], phy_wrdata[87], phy_wrdata[55], phy_wrdata[23], phy_wrdata[246], phy_wrdata[214], phy_wrdata[182], phy_wrdata[150], phy_wrdata[118], phy_wrdata[86], phy_wrdata[54], phy_wrdata[22], phy_wrdata[245], phy_wrdata[213], phy_wrdata[181], phy_wrdata[149], phy_wrdata[117], phy_wrdata[85], phy_wrdata[53], phy_wrdata[21], phy_wrdata[244], phy_wrdata[212], phy_wrdata[180], phy_wrdata[148], phy_wrdata[116], phy_wrdata[84], phy_wrdata[52], phy_wrdata[20], phy_wrdata[243], phy_wrdata[211], phy_wrdata[179], phy_wrdata[147], phy_wrdata[115], phy_wrdata[83], phy_wrdata[51], phy_wrdata[19], phy_wrdata[242], phy_wrdata[210], phy_wrdata[178], phy_wrdata[146], phy_wrdata[114], phy_wrdata[82], phy_wrdata[50], phy_wrdata[18], phy_wrdata[241], phy_wrdata[209], phy_wrdata[177], phy_wrdata[145], phy_wrdata[113], phy_wrdata[81], phy_wrdata[49], phy_wrdata[17], phy_wrdata[240], phy_wrdata[208], phy_wrdata[176], phy_wrdata[144], phy_wrdata[112], phy_wrdata[80], phy_wrdata[48], phy_wrdata[16]}), .adj_wrdq_en ({\i_dqs_group[0].u_ddrphy_data_slice/adj_wrdq_en [3] , \i_dqs_group[0].u_ddrphy_data_slice/adj_wrdq_en [2] , \i_dqs_group[0].u_ddrphy_data_slice/adj_wrdq_en [1] , \i_dqs_group[0].u_ddrphy_data_slice/adj_wrdq_en [0] }), @@ -165284,35 +165182,26 @@ module ipsxb_ddrphy_slice_top_v1_4 .\data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r1 ({1'bx, \i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r1 [2] , 1'bx, \i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r1 [0] }), .\data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r2 ({1'bx, \i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r2 [2] , 1'bx, \i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r2 [0] }), .\data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r3 ({1'bx, \i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r3 [2] , 1'bx, \i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r3 [0] }), - .\data_slice_wrlvl/N484 ({\i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N484 [4] , 1'bx, 1'bx, 1'bx, 1'bx}), .dll_step (dll_step), .\dqsi_rdel_cal/N734 ({1'bx, 1'bx, 1'bx, \i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N734 [26] , 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), .\dqsi_rdel_cal/default_samp_position ({\i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position [7] , \i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position [6] , \i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position [5] , \i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position [4] , \i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position [3] , \i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position [2] , \i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position [1] , \i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position [0] }), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt ({\i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [4] , \i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] , \i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] , \i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [1] , \i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [0] }), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg ({1'bx, 1'bx, \i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg [4] , 1'bx, 1'bx, 1'bx, 1'bx}), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt ({\i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [4] , 1'bx, \i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] , 1'bx, 1'bx}), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt ({\i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [4] , \i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] , \i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] , \i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [1] , \i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [0] }), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg ({1'bx, 1'bx, \i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg [4] , 1'bx, 1'bx, 1'bx, 1'bx}), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt ({\i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [4] , \i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] , \i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] , \i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [1] , \i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt [0] }), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg ({1'bx, 1'bx, \i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg [4] , 1'bx, 1'bx, 1'bx, 1'bx}), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/phy_wrdata_mask ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, adj_wrdata_mask[6], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, adj_wrdata_mask[2], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), .\wdata_path_adj/phy_wrdata_en_r2 ({\i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_r2 [3] , 1'bx, 1'bx, 1'bx}), .\wdata_path_adj/phy_wrdata_en_slip4 ({\i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_slip4 [3] , \i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_slip4 [2] , \i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_slip4 [1] , \i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_slip4 [0] }), .dqs (mem_dqs[2]), .dqs_n (mem_dqs_n[2]), - ._N81414_3 (_N81414_3), - ._N81414_5 (_N81414_5), - ._N83022 (_N83022), - ._N96271 (_N96271), - ._N96272 (_N96272), - ._N96274 (_N96274), - ._N96318 (_N96318), - ._N96883 (_N96883), - ._N105949 (_N105949), - ._N106218 (_N106218), - ._N106518 (_N106518), + ._N82187_3 (_N82187_3), + ._N82187_5 (_N82187_5), + ._N97033 (_N97033), + ._N106767 (_N106767), + ._N107336 (_N107336), .adj_rdel_done (adj_rdel_done_tmp[2]), .ck_check_done (ck_check_done_tmp[2]), .\data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r (\i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r ), - .\data_slice_wrlvl/dq_vld (\i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld ), .dm (mem_dm[2]), .dqs_gate_vld (\i_dqs_group[2].u_ddrphy_data_slice/dqs_gate_vld ), .gate_adj_done (gate_adj_done_tmp[2]), @@ -165324,25 +165213,20 @@ module ipsxb_ddrphy_slice_top_v1_4 .rdel_calib_error (rdel_calib_error_tmp[2]), .rdel_move_done (rdel_move_done_tmp[2]), .read_valid (dqs_read_valid[2]), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N449 (\i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/N449 ), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N449 (\i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N449 ), .wrlvl_ck_dly_flag (wrlvl_ck_dly_flag_tmp[2]), - .wrlvl_dqs_en (\i_dqs_group[2].u_ddrphy_data_slice/wrlvl_dqs_en ), .wrlvl_dqs_resp (wrlvl_dqs_resp_tmp[2]), .wrlvl_error (wrlvl_error_tmp[2]), - ._N96109 (_N96109), - ._N96120 (_N96120), - ._N96124 (_N96124), - ._N96160 (_N96160), - ._N96886 (_N96886), - ._N106288 (_N106288), - ._N106303 (_N106303), - ._N106624 (_N106624), + ._N96887 (_N96887), + ._N96902 (_N96902), + ._N96939 (_N96939), + ._N97663 (_N97663), .\data_slice_dqs_gate_cal/gatecal/N1 (N25), - .\data_slice_wrlvl/N449 (\i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/N449 ), .ddrphy_clkin (ddrphy_clkin), .ddrphy_dqs_rst (ddrphy_dqs_rst), .ddrphy_dqs_training_rstn (ddrphy_dqs_training_rstn), .ddrphy_ioclk (ddrphy_ioclk[3]), + .\dqs_rddata_align/_N11 (\i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/_N11 ), .\dqsi_rdel_cal/_N538 (\i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N538 ), .\dqsi_rdel_cal/rdel_calibration_d (\i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calibration_d ), .\dqsi_rdel_cal/rdel_calibration_rising (\i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calibration_rising ), @@ -165354,9 +165238,7 @@ module ipsxb_ddrphy_slice_top_v1_4 .rdel_calibration (rdel_calibration), .rdel_move_en (rdel_move_en), .reinit_adj_rdel (reinit_adj_rdel), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld (\i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld ), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wrlvl_dqs_en (\i_dqs_group[0].u_ddrphy_data_slice/wrlvl_dqs_en ), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld (\i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld ), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N165 (\i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N165 ), .wrlvl_ck_dly_done (wrlvl_ck_dly_done), .wrlvl_ck_dly_start (wrlvl_ck_dly_start), .wrlvl_dqs_req (wrlvl_dqs_req)); @@ -165375,7 +165257,6 @@ module ipsxb_ddrphy_slice_top_v1_4 .\dqsi_rdel_cal/cnt ({\i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [9] , \i_dqs_group[3].u_ddrphy_data_slice_dqsi_rdel_cal/cnt[8]_floating , \i_dqs_group[3].u_ddrphy_data_slice_dqsi_rdel_cal/cnt[7]_floating , \i_dqs_group[3].u_ddrphy_data_slice_dqsi_rdel_cal/cnt[6]_floating , \i_dqs_group[3].u_ddrphy_data_slice_dqsi_rdel_cal/cnt[5]_floating , \i_dqs_group[3].u_ddrphy_data_slice_dqsi_rdel_cal/cnt[4]_floating , \i_dqs_group[3].u_ddrphy_data_slice_dqsi_rdel_cal/cnt[3]_floating , \i_dqs_group[3].u_ddrphy_data_slice_dqsi_rdel_cal/cnt[2]_floating , \i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [1] , \i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [0] }), .\dqsi_rdel_cal/total_margin_div2 ({\i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin_div2 [7] , \i_dqs_group[3].u_ddrphy_data_slice_dqsi_rdel_cal/total_margin_div2[6]_floating , \i_dqs_group[3].u_ddrphy_data_slice_dqsi_rdel_cal/total_margin_div2[5]_floating , \i_dqs_group[3].u_ddrphy_data_slice_dqsi_rdel_cal/total_margin_div2[4]_floating , \i_dqs_group[3].u_ddrphy_data_slice_dqsi_rdel_cal/total_margin_div2[3]_floating , \i_dqs_group[3].u_ddrphy_data_slice_dqsi_rdel_cal/total_margin_div2[2]_floating , \i_dqs_group[3].u_ddrphy_data_slice_dqsi_rdel_cal/total_margin_div2[1]_floating , \i_dqs_group[3].u_ddrphy_data_slice_dqsi_rdel_cal/total_margin_div2[0]_floating }), .read_data ({dqs_read_data[255], dqs_read_data[254], dqs_read_data[253], dqs_read_data[252], dqs_read_data[251], dqs_read_data[250], dqs_read_data[249], dqs_read_data[248], dqs_read_data[247], dqs_read_data[246], dqs_read_data[245], dqs_read_data[244], dqs_read_data[243], dqs_read_data[242], dqs_read_data[241], dqs_read_data[240], dqs_read_data[239], dqs_read_data[238], dqs_read_data[237], dqs_read_data[236], dqs_read_data[235], dqs_read_data[234], dqs_read_data[233], dqs_read_data[232], dqs_read_data[231], dqs_read_data[230], dqs_read_data[229], dqs_read_data[228], dqs_read_data[227], dqs_read_data[226], dqs_read_data[225], dqs_read_data[224], dqs_read_data[223], dqs_read_data[222], dqs_read_data[221], dqs_read_data[220], dqs_read_data[219], dqs_read_data[218], dqs_read_data[217], dqs_read_data[216], dqs_read_data[215], dqs_read_data[214], dqs_read_data[213], dqs_read_data[212], dqs_read_data[211], dqs_read_data[210], dqs_read_data[209], dqs_read_data[208], dqs_read_data[207], dqs_read_data[206], dqs_read_data[205], dqs_read_data[204], dqs_read_data[203], dqs_read_data[202], dqs_read_data[201], dqs_read_data[200], dqs_read_data[199], dqs_read_data[198], dqs_read_data[197], dqs_read_data[196], dqs_read_data[195], dqs_read_data[194], dqs_read_data[193], dqs_read_data[192]}), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484 ({\i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484 [4] , \i_dqs_group[3].u_ddrphy_data_slice_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484[3]_floating , \i_dqs_group[3].u_ddrphy_data_slice_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484[2]_floating , \i_dqs_group[3].u_ddrphy_data_slice_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484[1]_floating , \i_dqs_group[3].u_ddrphy_data_slice_u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/N484[0]_floating }), .adj_wrdata_mask ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, adj_wrdata_mask[0]}), .adj_wrdq ({phy_wrdata[255], phy_wrdata[223], phy_wrdata[191], phy_wrdata[159], phy_wrdata[127], phy_wrdata[95], phy_wrdata[63], phy_wrdata[31], phy_wrdata[254], phy_wrdata[222], phy_wrdata[190], phy_wrdata[158], phy_wrdata[126], phy_wrdata[94], phy_wrdata[62], phy_wrdata[30], phy_wrdata[253], phy_wrdata[221], phy_wrdata[189], phy_wrdata[157], phy_wrdata[125], phy_wrdata[93], phy_wrdata[61], phy_wrdata[29], phy_wrdata[252], phy_wrdata[220], phy_wrdata[188], phy_wrdata[156], phy_wrdata[124], phy_wrdata[92], phy_wrdata[60], phy_wrdata[28], phy_wrdata[251], phy_wrdata[219], phy_wrdata[187], phy_wrdata[155], phy_wrdata[123], phy_wrdata[91], phy_wrdata[59], phy_wrdata[27], phy_wrdata[250], phy_wrdata[218], phy_wrdata[186], phy_wrdata[154], phy_wrdata[122], phy_wrdata[90], phy_wrdata[58], phy_wrdata[26], phy_wrdata[249], phy_wrdata[217], phy_wrdata[185], phy_wrdata[153], phy_wrdata[121], phy_wrdata[89], phy_wrdata[57], phy_wrdata[25], phy_wrdata[248], phy_wrdata[216], phy_wrdata[184], phy_wrdata[152], phy_wrdata[120], phy_wrdata[88], phy_wrdata[56], phy_wrdata[24]}), .adj_wrdq_en ({\i_dqs_group[0].u_ddrphy_data_slice/adj_wrdq_en [3] , \i_dqs_group[0].u_ddrphy_data_slice/adj_wrdq_en [2] , \i_dqs_group[0].u_ddrphy_data_slice/adj_wrdq_en [1] , \i_dqs_group[0].u_ddrphy_data_slice/adj_wrdq_en [0] }), @@ -165387,24 +165268,28 @@ module ipsxb_ddrphy_slice_top_v1_4 .dll_step (dll_step), .\dqsi_rdel_cal/N734 ({1'bx, 1'bx, 1'bx, \i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N734 [26] , 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), .\dqsi_rdel_cal/default_samp_position ({\i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position [7] , \i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position [6] , \i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position [5] , \i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position [4] , \i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position [3] , \i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position [2] , \i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position [1] , \i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position [0] }), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt ({\i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [4] , \i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] , \i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] , \i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [1] , \i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [0] }), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt ({1'bx, \i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] , \i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt [2] , 1'bx, 1'bx}), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg ({1'bx, 1'bx, \i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg [4] , 1'bx, 1'bx, 1'bx, 1'bx}), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt ({1'bx, \i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [3] , 1'bx, \i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt [1] , 1'bx}), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg ({1'bx, 1'bx, \i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg [4] , 1'bx, 1'bx, 1'bx, 1'bx}), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt ({\i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [9] , \i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [8] , \i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [7] , \i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [6] , \i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [5] , \i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [4] , \i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [3] , \i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [2] , \i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [1] , \i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [0] }), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt ({\i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [9] , \i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [8] , \i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [7] , \i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [6] , \i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [5] , \i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [4] , \i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [3] , \i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [2] , \i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [1] , \i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [0] }), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/phy_wrdata_mask ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, adj_wrdata_mask[6], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, adj_wrdata_mask[2], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), .\wdata_path_adj/phy_wrdata_en_r2 ({\i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_r2 [3] , 1'bx, 1'bx, 1'bx}), .\wdata_path_adj/phy_wrdata_en_slip4 ({\i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_slip4 [3] , \i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_slip4 [2] , \i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_slip4 [1] , \i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_slip4 [0] }), .dqs (mem_dqs[3]), .dqs_n (mem_dqs_n[3]), - ._N81415_3 (_N81415_3), - ._N81415_5 (_N81415_5), - ._N83332 (_N83332), - ._N96158 (_N96158), - ._N96884 (_N96884), - ._N106490 (_N106490), + ._N82188_3 (_N82188_3), + ._N82188_5 (_N82188_5), + ._N84178 (_N84178), + ._N96939 (_N96939), + ._N97660 (_N97660), + ._N107042 (_N107042), + ._N107308 (_N107308), .adj_rdel_done (adj_rdel_done_tmp[3]), .ck_check_done (ck_check_done_tmp[3]), .\data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r (\i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r ), .\data_slice_wrlvl/N165 (\i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N165 ), + .\data_slice_wrlvl/dq_vld (\i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld ), .dm (mem_dm[3]), .dqs_gate_vld (\i_dqs_group[3].u_ddrphy_data_slice/dqs_gate_vld ), .gate_adj_done (gate_adj_done_tmp[3]), @@ -165419,11 +165304,12 @@ module ipsxb_ddrphy_slice_top_v1_4 .wrlvl_ck_dly_flag (wrlvl_ck_dly_flag_tmp[3]), .wrlvl_dqs_resp (wrlvl_dqs_resp_tmp[3]), .wrlvl_error (wrlvl_error_tmp[3]), - ._N96110 (_N96110), - ._N96167 (_N96167), - ._N96271 (_N96271), - ._N96274 (_N96274), - ._N96887 (_N96887), + ._N96888 (_N96888), + ._N96942 (_N96942), + ._N97033 (_N97033), + ._N97080 (_N97080), + ._N97672 (_N97672), + ._N104452 (_N104452), .\data_slice_dqs_gate_cal/gatecal/N1 (N25), .\data_slice_wrlvl/N449 (\i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/N449 ), .ddrphy_clkin (ddrphy_clkin), @@ -165441,6 +165327,7 @@ module ipsxb_ddrphy_slice_top_v1_4 .rdel_calibration (rdel_calibration), .rdel_move_en (rdel_move_en), .reinit_adj_rdel (reinit_adj_rdel), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld (\i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld ), .wrlvl_ck_dly_done (wrlvl_ck_dly_done), .wrlvl_ck_dly_start (wrlvl_ck_dly_start), .wrlvl_dqs_req (wrlvl_dqs_req)); @@ -166154,14 +166041,14 @@ module ipsxb_ddrphy_slice_top_v1_4 .Q (wrlvl_ck_dly_start_rst), .C (N25), .CLK (ddrphy_clkin), - .D (_N103339)); + .D (_N104151)); // defparam wrlvl_ck_dly_start_rst_vname.orig_name = wrlvl_ck_dly_start_rst; // ../ipcore/axi_ddr/rtl/ddrphy/ipsxb_ddrphy_slice_top_v1_4.v:451 GTP_LUT5 /* wrlvl_ck_dly_start_rst_ce_mux */ #( .INIT(32'b10101110101010101010101010101010)) wrlvl_ck_dly_start_rst_ce_mux ( - .Z (_N103339), + .Z (_N104151), .I0 (wrlvl_ck_dly_start_rst), .I1 (wrlvl_ck_dly_done), .I2 (ck_dly_cnt[0]), @@ -166357,7 +166244,6 @@ module axi_ddr_ddrphy_top input [255:0] dfi_wrdata, input [3:0] dfi_wrdata_en, input [31:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/wr_strb , - input _N18115, input ddr_rstn, input ddrphy_clkin, input \ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N538 , @@ -166367,8 +166253,6 @@ module axi_ddr_ddrphy_top input ioclk_gate_clk, input pll_lock, input ref_clk, - output [7:0] \ddrphy_reset_ctrl/cnt , - output [8:0] \ddrphy_reset_ctrl/state_reg , output [9:0] \ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt , output [7:0] \ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin_div2 , output [9:0] \ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt , @@ -166381,27 +166265,24 @@ module axi_ddr_ddrphy_top output [2:0] mem_ba, output [3:0] mem_dm, output [255:0] \u_axi_ddr_top/s_axi_rdata , - output _N81412_3, - output _N81412_5, - output _N81413_3, - output _N81413_5, - output _N81414_3, - output _N81414_5, - output _N81415_3, - output _N81415_5, - output _N97085, - output _N105268, - output _N105817, - output _N106355, - output _N106490, - output _N106518, + output _N82185_3, + output _N82185_5, + output _N82186_3, + output _N82186_5, + output _N82187_3, + output _N82187_5, + output _N82188_3, + output _N82188_5, + output _N106081, + output _N106639, + output _N107308, + output _N107336, output calib_done, output ddrphy_dqs_rst, output \ddrphy_gate_update_ctrl/drift_dqs_group[0].ddrphy_drift_ctrl/dqs_drift_start , output ddrphy_ioclk_gate, output ddrphy_pll_rst, output \ddrphy_reset_ctrl/N17 , - output \ddrphy_reset_ctrl/N137 , output mem_cas_n, output mem_ck, output mem_ck_n, @@ -166818,21 +166699,6 @@ module axi_ddr_ddrphy_top wire \ddrphy_info_mr1_ddr3[15]_floating ; wire \ddrphy_info_mr2_ddr3[15]_floating ; wire \ddrphy_info_mr3_ddr3[15]_floating ; - wire \ddrphy_reset_ctrl_cnt[0]_floating ; - wire \ddrphy_reset_ctrl_cnt[1]_floating ; - wire \ddrphy_reset_ctrl_cnt[2]_floating ; - wire \ddrphy_reset_ctrl_cnt[4]_floating ; - wire \ddrphy_reset_ctrl_cnt[5]_floating ; - wire \ddrphy_reset_ctrl_cnt[6]_floating ; - wire \ddrphy_reset_ctrl_cnt[7]_floating ; - wire \ddrphy_reset_ctrl_state_reg[0]_floating ; - wire \ddrphy_reset_ctrl_state_reg[1]_floating ; - wire \ddrphy_reset_ctrl_state_reg[2]_floating ; - wire \ddrphy_reset_ctrl_state_reg[3]_floating ; - wire \ddrphy_reset_ctrl_state_reg[4]_floating ; - wire \ddrphy_reset_ctrl_state_reg[5]_floating ; - wire \ddrphy_reset_ctrl_state_reg[6]_floating ; - wire \ddrphy_reset_ctrl_state_reg[8]_floating ; wire \ddrphy_slice_top_i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]_floating ; wire \ddrphy_slice_top_i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[1]_floating ; wire \ddrphy_slice_top_i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[2]_floating ; @@ -167030,12 +166896,7 @@ module axi_ddr_ddrphy_top // ../ipcore/axi_ddr/axi_ddr_ddrphy_top.v:582 ipsxb_ddrphy_reset_ctrl_v1_4 ddrphy_reset_ctrl ( - .cnt ({\ddrphy_reset_ctrl_cnt[7]_floating , \ddrphy_reset_ctrl_cnt[6]_floating , \ddrphy_reset_ctrl_cnt[5]_floating , \ddrphy_reset_ctrl_cnt[4]_floating , \ddrphy_reset_ctrl/cnt [3] , \ddrphy_reset_ctrl_cnt[2]_floating , \ddrphy_reset_ctrl_cnt[1]_floating , \ddrphy_reset_ctrl_cnt[0]_floating }), - .state_reg ({\ddrphy_reset_ctrl_state_reg[8]_floating , \ddrphy_reset_ctrl/state_reg [7] , \ddrphy_reset_ctrl_state_reg[6]_floating , \ddrphy_reset_ctrl_state_reg[5]_floating , \ddrphy_reset_ctrl_state_reg[4]_floating , \ddrphy_reset_ctrl_state_reg[3]_floating , \ddrphy_reset_ctrl_state_reg[2]_floating , \ddrphy_reset_ctrl_state_reg[1]_floating , \ddrphy_reset_ctrl_state_reg[0]_floating }), .N17 (\ddrphy_reset_ctrl/N17 ), - .N137 (\ddrphy_reset_ctrl/N137 ), - ._N97085 (_N97085), - ._N106355 (_N106355), .ddrphy_dll_rst (ddrphy_dll_rst), .ddrphy_dqs_rst (ddrphy_dqs_rst), .ddrphy_ioclk_gate (ddrphy_ioclk_gate), @@ -167044,7 +166905,6 @@ module axi_ddr_ddrphy_top .dll_update_req_rst_ctrl (dll_update_req_rst_ctrl), .logic_rstn (logic_rstn), .N0 (\ddrphy_dll_update_ctrl/N0 ), - ._N18115 (_N18115), .ddr_rstn (ddr_rstn), .ddrphy_clkin (ddrphy_clkin), .dll_lock (dll_lock), @@ -167096,18 +166956,18 @@ module axi_ddr_ddrphy_top .phy_wrdata (phy_wrdata), .phy_wrdata_en (phy_wrdata_en), .read_cmd ({1'bx, read_cmd[2], 1'bx, read_cmd[0]}), - ._N81412_3 (_N81412_3), - ._N81412_5 (_N81412_5), - ._N81413_3 (_N81413_3), - ._N81413_5 (_N81413_5), - ._N81414_3 (_N81414_3), - ._N81414_5 (_N81414_5), - ._N81415_3 (_N81415_3), - ._N81415_5 (_N81415_5), - ._N105268 (_N105268), - ._N105817 (_N105817), - ._N106490 (_N106490), - ._N106518 (_N106518), + ._N82185_3 (_N82185_3), + ._N82185_5 (_N82185_5), + ._N82186_3 (_N82186_3), + ._N82186_5 (_N82186_5), + ._N82187_3 (_N82187_3), + ._N82187_5 (_N82187_5), + ._N82188_3 (_N82188_3), + ._N82188_5 (_N82188_5), + ._N106081 (_N106081), + ._N106639 (_N106639), + ._N107308 (_N107308), + ._N107336 (_N107336), .adj_rdel_done (adj_rdel_done), .gate_adj_done (gate_adj_done), .gate_check_error (gate_check_error), @@ -167665,37 +167525,33 @@ endmodule module ipsxb_mcdq_dcd_rowaddr_v1_2 ( - input [6:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg , input [54:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 , input [54:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 , input [2:0] user_bank_addr, input N0, + input _N96998, + input _N96999, + input _N97000, + input _N97001, input clk, - input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/dec_done , - input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/dec_new_valid , input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/dec_refresh , input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/r_init , input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_valid_0 , input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_valid_1 , input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr , input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/user_cmd_ready , - output _N24867, - output _N24870, - output _N96029, + output _N24587, + output _N24590, output rowaddr_check_diff ); wire N28; wire [7:0] N29; - wire _N96290; - wire _N96291; - wire _N96292; - wire _N96293; wire [7:0] old_row_addr_valid; GTP_LUT5M /* N8_4 */ #( .INIT(32'b11111010000010101100101011001010)) N8_4 ( - .Z (_N24867), + .Z (_N24587), .I0 (old_row_addr_valid[5]), .I1 (old_row_addr_valid[3]), .I2 (user_bank_addr[1]), @@ -167707,7 +167563,7 @@ module ipsxb_mcdq_dcd_rowaddr_v1_2 GTP_LUT5M /* N8_7 */ #( .INIT(32'b11111010000010101100101011001010)) N8_7 ( - .Z (_N24870), + .Z (_N24590), .I0 (old_row_addr_valid[4]), .I1 (old_row_addr_valid[2]), .I2 (user_bank_addr[1]), @@ -167720,12 +167576,12 @@ module ipsxb_mcdq_dcd_rowaddr_v1_2 .INIT(32'b10101000001000001010100000100000)) N9 ( .Z (rowaddr_check_diff), - .I0 (_N24867), + .I0 (_N24587), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [39] ), .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [39] ), .I4 (user_bank_addr[0]), - .ID (_N24870)); + .ID (_N24590)); // LUT = (ID&I1&I3&~I4)|(ID&~I1&I2&~I4)|(I0&I1&I3&I4)|(I0&~I1&I2&I4) ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcd_rowaddr_v1_2.vp:109 @@ -167750,7 +167606,7 @@ module ipsxb_mcdq_dcd_rowaddr_v1_2 .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/dec_refresh ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/r_init ), .I3 (old_row_addr_valid[0]), - .I4 (_N96290)); + .I4 (_N96998)); // LUT = (~I1&~I2&I3)|(~I0&~I1&~I2&I4) ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcd_rowaddr_v1_2.vp:97 @@ -167762,7 +167618,7 @@ module ipsxb_mcdq_dcd_rowaddr_v1_2 .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/dec_refresh ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/r_init ), .I3 (old_row_addr_valid[1]), - .I4 (_N96291)); + .I4 (_N96999)); // LUT = (~I1&~I2&I3)|(~I0&~I1&~I2&I4) ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcd_rowaddr_v1_2.vp:97 @@ -167774,7 +167630,7 @@ module ipsxb_mcdq_dcd_rowaddr_v1_2 .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/dec_refresh ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/r_init ), .I3 (old_row_addr_valid[2]), - .I4 (_N96292)); + .I4 (_N97000)); // LUT = (~I1&~I2&I3)|(~I0&~I1&~I2&I4) ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcd_rowaddr_v1_2.vp:97 @@ -167786,7 +167642,7 @@ module ipsxb_mcdq_dcd_rowaddr_v1_2 .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/dec_refresh ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/r_init ), .I3 (old_row_addr_valid[3]), - .I4 (_N96293)); + .I4 (_N97001)); // LUT = (~I1&~I2&I3)|(~I0&~I1&~I2&I4) ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcd_rowaddr_v1_2.vp:97 @@ -167798,7 +167654,7 @@ module ipsxb_mcdq_dcd_rowaddr_v1_2 .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/dec_refresh ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/r_init ), .I3 (old_row_addr_valid[4]), - .I4 (_N96290)); + .I4 (_N96998)); // LUT = (~I1&~I2&I3)|(I0&~I1&~I2&I4) ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcd_rowaddr_v1_2.vp:97 @@ -167810,7 +167666,7 @@ module ipsxb_mcdq_dcd_rowaddr_v1_2 .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/dec_refresh ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/r_init ), .I3 (old_row_addr_valid[5]), - .I4 (_N96291)); + .I4 (_N96999)); // LUT = (~I1&~I2&I3)|(I0&~I1&~I2&I4) ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcd_rowaddr_v1_2.vp:97 @@ -167822,7 +167678,7 @@ module ipsxb_mcdq_dcd_rowaddr_v1_2 .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/dec_refresh ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/r_init ), .I3 (old_row_addr_valid[6]), - .I4 (_N96292)); + .I4 (_N97000)); // LUT = (~I1&~I2&I3)|(I0&~I1&~I2&I4) ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcd_rowaddr_v1_2.vp:97 @@ -167834,64 +167690,10 @@ module ipsxb_mcdq_dcd_rowaddr_v1_2 .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/dec_refresh ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/r_init ), .I3 (old_row_addr_valid[7]), - .I4 (_N96293)); + .I4 (_N97001)); // LUT = (~I1&~I2&I3)|(I0&~I1&~I2&I4) ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcd_rowaddr_v1_2.vp:97 - GTP_LUT5 /* \ND1[1]_1 */ #( - .INIT(32'b00000001000000010000000110101011)) - \ND1[1]_1 ( - .Z (_N96290), - .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [18] ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [19] ), - .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [18] ), - .I4 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [19] )); - // LUT = (I0&~I3&~I4)|(~I0&~I1&~I2) ; - - GTP_LUT5 /* \ND1[1]_2 */ #( - .INIT(32'b00000100000001001010111000000100)) - \ND1[1]_2 ( - .Z (_N96291), - .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [18] ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [19] ), - .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [18] ), - .I4 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [19] )); - // LUT = (I0&I3&~I4)|(~I0&I1&~I2) ; - - GTP_LUT5 /* \ND1[1]_3 */ #( - .INIT(32'b00010000101110100001000000010000)) - \ND1[1]_3 ( - .Z (_N96292), - .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [18] ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [19] ), - .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [18] ), - .I4 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [19] )); - // LUT = (I0&~I3&I4)|(~I0&~I1&I2) ; - - GTP_LUT5 /* \ND1[1]_4 */ #( - .INIT(32'b11101010010000000100000001000000)) - \ND1[1]_4 ( - .Z (_N96293), - .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [18] ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [19] ), - .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [18] ), - .I4 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [19] )); - // LUT = (~I0&I1&I2)|(I0&I3&I4) ; - - GTP_LUT4 /* \ND1[2]_1 */ #( - .INIT(16'b0000010000000000)) - \ND1[2]_1 ( - .Z (_N96029), - .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/dec_done ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/dec_new_valid ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/dec_refresh ), - .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg [0] )); - // LUT = ~I0&I1&~I2&I3 ; - GTP_DFF_CE /* \old_row_addr_valid[0] */ #( .GRS_EN("TRUE"), .INIT(1'b0)) @@ -167992,7 +167794,7 @@ module ipsxb_mcdq_dcd_bm_v1_2 input [27:0] user_addr, input [3:0] user_len, input N27, - input _N96341, + input _N97168, input clk, input dec_done, input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/ddrc_init_done , @@ -168003,7 +167805,7 @@ module ipsxb_mcdq_dcd_bm_v1_2 output [3:0] dec_id, output [3:0] dec_len, output N62, - output _N96029, + output _N97165, output dec_new_row, output dec_new_valid, output dec_pre_row, @@ -168031,39 +167833,43 @@ module ipsxb_mcdq_dcd_bm_v1_2 wire [3:0] N314; wire N317; wire [14:0] N318; - wire _N6205; - wire _N13491; - wire _N13492; - wire _N13493; - wire _N13494; - wire _N13495; - wire _N13496; - wire _N13497; - wire _N13498; - wire _N13499; - wire _N13500; - wire _N13501; - wire _N24498; - wire _N24507; - wire _N24508; - wire _N24509; - wire _N24510; - wire _N24511; - wire _N24512; - wire _N24513; - wire _N24514; - wire _N24515; - wire _N24516; - wire _N24517; - wire _N24518; - wire _N24519; - wire _N24520; - wire _N24521; - wire _N24867; - wire _N24870; - wire _N74589; - wire _N103436; - wire _N105211; + wire _N6298; + wire _N15890; + wire _N15891; + wire _N15892; + wire _N15893; + wire _N15894; + wire _N15895; + wire _N15896; + wire _N15897; + wire _N15898; + wire _N15899; + wire _N15900; + wire _N24218; + wire _N24227; + wire _N24228; + wire _N24229; + wire _N24230; + wire _N24231; + wire _N24232; + wire _N24233; + wire _N24234; + wire _N24235; + wire _N24236; + wire _N24237; + wire _N24238; + wire _N24239; + wire _N24240; + wire _N24241; + wire _N24587; + wire _N24590; + wire _N75550; + wire _N96998; + wire _N96999; + wire _N97000; + wire _N97001; + wire _N104248; + wire _N106247; wire r_init; wire [12:0] refresh_cnt; wire refresh_req; @@ -168073,7 +167879,7 @@ module ipsxb_mcdq_dcd_bm_v1_2 GTP_LUT4 /* N33_mux5_5 */ #( .INIT(16'b0111111111111111)) N33_mux5_5 ( - .Z (_N105211), + .Z (_N106247), .I0 (refresh_cnt[5]), .I1 (refresh_cnt[6]), .I2 (refresh_cnt[7]), @@ -168088,7 +167894,7 @@ module ipsxb_mcdq_dcd_bm_v1_2 .I1 (refresh_cnt[10]), .I2 (refresh_cnt[11]), .I3 (refresh_cnt[12]), - .I4 (_N105211)); + .I4 (_N106247)); // LUT = (~I3)|(~I1&~I2)|(~I0&~I2)|(~I2&I4) ; GTP_LUT5CARRY /* N37_1_1 */ #( @@ -168098,7 +167904,7 @@ module ipsxb_mcdq_dcd_bm_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N37_1_1 ( - .COUT (_N13491), + .COUT (_N15890), .Z (N37[1]), .CIN (), .I0 (refresh_cnt[0]), @@ -168118,9 +167924,9 @@ module ipsxb_mcdq_dcd_bm_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N37_1_2 ( - .COUT (_N13492), + .COUT (_N15891), .Z (N37[2]), - .CIN (_N13491), + .CIN (_N15890), .I0 (refresh_cnt[0]), .I1 (refresh_cnt[1]), .I2 (refresh_cnt[2]), @@ -168138,9 +167944,9 @@ module ipsxb_mcdq_dcd_bm_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N37_1_3 ( - .COUT (_N13493), + .COUT (_N15892), .Z (N37[3]), - .CIN (_N13492), + .CIN (_N15891), .I0 (), .I1 (refresh_cnt[3]), .I2 (), @@ -168158,9 +167964,9 @@ module ipsxb_mcdq_dcd_bm_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N37_1_4 ( - .COUT (_N13494), + .COUT (_N15893), .Z (N37[4]), - .CIN (_N13493), + .CIN (_N15892), .I0 (), .I1 (refresh_cnt[4]), .I2 (), @@ -168178,9 +167984,9 @@ module ipsxb_mcdq_dcd_bm_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N37_1_5 ( - .COUT (_N13495), + .COUT (_N15894), .Z (N37[5]), - .CIN (_N13494), + .CIN (_N15893), .I0 (), .I1 (refresh_cnt[5]), .I2 (), @@ -168198,9 +168004,9 @@ module ipsxb_mcdq_dcd_bm_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N37_1_6 ( - .COUT (_N13496), + .COUT (_N15895), .Z (N37[6]), - .CIN (_N13495), + .CIN (_N15894), .I0 (), .I1 (refresh_cnt[6]), .I2 (), @@ -168218,9 +168024,9 @@ module ipsxb_mcdq_dcd_bm_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N37_1_7 ( - .COUT (_N13497), + .COUT (_N15896), .Z (N37[7]), - .CIN (_N13496), + .CIN (_N15895), .I0 (), .I1 (refresh_cnt[7]), .I2 (), @@ -168238,9 +168044,9 @@ module ipsxb_mcdq_dcd_bm_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N37_1_8 ( - .COUT (_N13498), + .COUT (_N15897), .Z (N37[8]), - .CIN (_N13497), + .CIN (_N15896), .I0 (), .I1 (refresh_cnt[8]), .I2 (), @@ -168258,9 +168064,9 @@ module ipsxb_mcdq_dcd_bm_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N37_1_9 ( - .COUT (_N13499), + .COUT (_N15898), .Z (N37[9]), - .CIN (_N13498), + .CIN (_N15897), .I0 (), .I1 (refresh_cnt[9]), .I2 (), @@ -168278,9 +168084,9 @@ module ipsxb_mcdq_dcd_bm_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N37_1_10 ( - .COUT (_N13500), + .COUT (_N15899), .Z (N37[10]), - .CIN (_N13499), + .CIN (_N15898), .I0 (), .I1 (refresh_cnt[10]), .I2 (), @@ -168298,9 +168104,9 @@ module ipsxb_mcdq_dcd_bm_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N37_1_11 ( - .COUT (_N13501), + .COUT (_N15900), .Z (N37[11]), - .CIN (_N13500), + .CIN (_N15899), .I0 (), .I1 (refresh_cnt[11]), .I2 (), @@ -168320,7 +168126,7 @@ module ipsxb_mcdq_dcd_bm_v1_2 N37_1_12 ( .COUT (), .Z (N37[12]), - .CIN (_N13501), + .CIN (_N15900), .I0 (), .I1 (refresh_cnt[12]), .I2 (), @@ -168355,7 +168161,7 @@ module ipsxb_mcdq_dcd_bm_v1_2 GTP_LUT5 /* N84_ac1 */ #( .INIT(32'b11101010010000000100000001000000)) N84_ac1 ( - .Z (_N6205), + .Z (_N6298), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [0] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [1] ), @@ -168363,9 +168169,9 @@ module ipsxb_mcdq_dcd_bm_v1_2 .I4 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [1] )); // LUT = (~I0&I1&I2)|(I0&I3&I4) ; - GTP_LUT4 /* N164_3 */ #( + GTP_LUT4 /* N164_5 */ #( .INIT(16'b0000000000000001)) - N164_3 ( + N164_5 ( .Z (N164), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/ddrc_init_done ), .I1 (user_cmd_ready), @@ -168566,14 +168372,58 @@ module ipsxb_mcdq_dcd_bm_v1_2 .INIT(32'b00110011000100000011001100010000)) \N267_or[0]_1 ( .Z (N267), - .I0 (_N24867), + .I0 (_N24587), .I1 (dec_done), .I2 (N62), .I3 (N80), .I4 (user_addr[10]), - .ID (_N24870)); + .ID (_N24590)); // LUT = (~ID&~I1&I2&~I4)|(~I0&~I1&I2&I4)|(~I1&I3) ; + GTP_LUT5 /* \N267_or[0]_4 */ #( + .INIT(32'b00000001000000010000000110101011)) + \N267_or[0]_4 ( + .Z (_N96998), + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [18] ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [19] ), + .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [18] ), + .I4 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [19] )); + // LUT = (I0&~I3&~I4)|(~I0&~I1&~I2) ; + + GTP_LUT5 /* \N267_or[0]_5 */ #( + .INIT(32'b00000100000001001010111000000100)) + \N267_or[0]_5 ( + .Z (_N96999), + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [18] ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [19] ), + .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [18] ), + .I4 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [19] )); + // LUT = (I0&I3&~I4)|(~I0&I1&~I2) ; + + GTP_LUT5 /* \N267_or[0]_6 */ #( + .INIT(32'b00010000101110100001000000010000)) + \N267_or[0]_6 ( + .Z (_N97000), + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [18] ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [19] ), + .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [18] ), + .I4 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [19] )); + // LUT = (I0&~I3&I4)|(~I0&~I1&I2) ; + + GTP_LUT5 /* \N267_or[0]_7 */ #( + .INIT(32'b11101010010000000100000001000000)) + \N267_or[0]_7 ( + .Z (_N97001), + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [18] ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [19] ), + .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [18] ), + .I4 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [19] )); + // LUT = (~I0&I1&I2)|(I0&I3&I4) ; + GTP_LUT4 /* N281 */ #( .INIT(16'b1011111110101010)) N281_vname ( @@ -168626,7 +168476,7 @@ module ipsxb_mcdq_dcd_bm_v1_2 .INIT(32'b00010001000100100010000100100010)) \N292[2]_1 ( .Z (N292[2]), - .I0 (_N6205), + .I0 (_N6298), .I1 (dec_done), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr ), .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [2] ), @@ -168639,7 +168489,7 @@ module ipsxb_mcdq_dcd_bm_v1_2 \N292[3]_1 ( .Z (N292[3]), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [3] ), - .I1 (_N6205), + .I1 (_N6298), .I2 (user_len[2]), .I3 (dec_done), .I4 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr ), @@ -168851,183 +168701,183 @@ module ipsxb_mcdq_dcd_bm_v1_2 N318_28 ( .Z (N304), .I0 (rowaddr_check_diff), - .I1 (_N96341)); + .I1 (_N97168)); // LUT = I0&I1 ; GTP_LUT5 /* \N318_30[0] */ #( .INIT(32'b11100100111001001111111100000000)) \N318_30[0] ( - .Z (_N24507), + .Z (_N24227), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [21] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [21] ), .I3 (user_addr_d[13]), - .I4 (_N96341)); + .I4 (_N97168)); // LUT = (I3&~I4)|(~I0&I1&I4)|(I0&I2&I4) ; GTP_LUT5 /* \N318_30[1] */ #( .INIT(32'b11100100111001001111111100000000)) \N318_30[1] ( - .Z (_N24508), + .Z (_N24228), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [22] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [22] ), .I3 (user_addr_d[14]), - .I4 (_N96341)); + .I4 (_N97168)); // LUT = (I3&~I4)|(~I0&I1&I4)|(I0&I2&I4) ; GTP_LUT5 /* \N318_30[2] */ #( .INIT(32'b11100100111001001111111100000000)) \N318_30[2] ( - .Z (_N24509), + .Z (_N24229), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [23] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [23] ), .I3 (user_addr_d[15]), - .I4 (_N96341)); + .I4 (_N97168)); // LUT = (I3&~I4)|(~I0&I1&I4)|(I0&I2&I4) ; GTP_LUT5 /* \N318_30[3] */ #( .INIT(32'b11100100111001001111111100000000)) \N318_30[3] ( - .Z (_N24510), + .Z (_N24230), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [24] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [24] ), .I3 (user_addr_d[16]), - .I4 (_N96341)); + .I4 (_N97168)); // LUT = (I3&~I4)|(~I0&I1&I4)|(I0&I2&I4) ; GTP_LUT5 /* \N318_30[4] */ #( .INIT(32'b11100100111001001111111100000000)) \N318_30[4] ( - .Z (_N24511), + .Z (_N24231), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [25] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [25] ), .I3 (user_addr_d[17]), - .I4 (_N96341)); + .I4 (_N97168)); // LUT = (I3&~I4)|(~I0&I1&I4)|(I0&I2&I4) ; GTP_LUT5 /* \N318_30[5] */ #( .INIT(32'b11100100111001001111111100000000)) \N318_30[5] ( - .Z (_N24512), + .Z (_N24232), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [26] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [26] ), .I3 (user_addr_d[18]), - .I4 (_N96341)); + .I4 (_N97168)); // LUT = (I3&~I4)|(~I0&I1&I4)|(I0&I2&I4) ; GTP_LUT5 /* \N318_30[6] */ #( .INIT(32'b11100100111001001111111100000000)) \N318_30[6] ( - .Z (_N24513), + .Z (_N24233), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [27] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [27] ), .I3 (user_addr_d[19]), - .I4 (_N96341)); + .I4 (_N97168)); // LUT = (I3&~I4)|(~I0&I1&I4)|(I0&I2&I4) ; GTP_LUT5 /* \N318_30[7] */ #( .INIT(32'b11100100111001001111111100000000)) \N318_30[7] ( - .Z (_N24514), + .Z (_N24234), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [28] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [28] ), .I3 (user_addr_d[20]), - .I4 (_N96341)); + .I4 (_N97168)); // LUT = (I3&~I4)|(~I0&I1&I4)|(I0&I2&I4) ; GTP_LUT5 /* \N318_30[8] */ #( .INIT(32'b11100100111001001111111100000000)) \N318_30[8] ( - .Z (_N24515), + .Z (_N24235), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [29] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [29] ), .I3 (user_addr_d[21]), - .I4 (_N96341)); + .I4 (_N97168)); // LUT = (I3&~I4)|(~I0&I1&I4)|(I0&I2&I4) ; GTP_LUT5 /* \N318_30[9] */ #( .INIT(32'b11100100111001001111111100000000)) \N318_30[9] ( - .Z (_N24516), + .Z (_N24236), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [30] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [30] ), .I3 (user_addr_d[22]), - .I4 (_N96341)); + .I4 (_N97168)); // LUT = (I3&~I4)|(~I0&I1&I4)|(I0&I2&I4) ; GTP_LUT5 /* \N318_30[10] */ #( .INIT(32'b11100100111001001111111100000000)) \N318_30[10] ( - .Z (_N24517), + .Z (_N24237), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [31] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [31] ), .I3 (user_addr_d[23]), - .I4 (_N96341)); + .I4 (_N97168)); // LUT = (I3&~I4)|(~I0&I1&I4)|(I0&I2&I4) ; GTP_LUT5 /* \N318_30[11] */ #( .INIT(32'b11100100111001001111111100000000)) \N318_30[11] ( - .Z (_N24518), + .Z (_N24238), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [32] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [32] ), .I3 (user_addr_d[24]), - .I4 (_N96341)); + .I4 (_N97168)); // LUT = (I3&~I4)|(~I0&I1&I4)|(I0&I2&I4) ; GTP_LUT5 /* \N318_30[12] */ #( .INIT(32'b11100100111001001111111100000000)) \N318_30[12] ( - .Z (_N24519), + .Z (_N24239), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [33] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [33] ), .I3 (user_addr_d[25]), - .I4 (_N96341)); + .I4 (_N97168)); // LUT = (I3&~I4)|(~I0&I1&I4)|(I0&I2&I4) ; GTP_LUT5 /* \N318_30[13] */ #( .INIT(32'b11100100111001001111111100000000)) \N318_30[13] ( - .Z (_N24520), + .Z (_N24240), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [34] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [34] ), .I3 (user_addr_d[26]), - .I4 (_N96341)); + .I4 (_N97168)); // LUT = (I3&~I4)|(~I0&I1&I4)|(I0&I2&I4) ; GTP_LUT5 /* \N318_30[14] */ #( .INIT(32'b11100100111001001111111100000000)) \N318_30[14] ( - .Z (_N24521), + .Z (_N24241), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [35] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [35] ), .I3 (user_addr_d[27]), - .I4 (_N96341)); + .I4 (_N97168)); // LUT = (I3&~I4)|(~I0&I1&I4)|(I0&I2&I4) ; GTP_LUT5M /* \N318_32[0] */ #( .INIT(32'b10101010101010101110010000000000)) \N318_32[0] ( .Z (N318[0]), - .I0 (_N24507), + .I0 (_N24227), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [40] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [40] ), - .I3 (_N96341), - .I4 (_N24498), + .I3 (_N97168), + .I4 (_N24218), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr )); // LUT = (ID&I2&I3&~I4)|(~ID&I1&I3&~I4)|(I0&I4) ; @@ -169035,11 +168885,11 @@ module ipsxb_mcdq_dcd_bm_v1_2 .INIT(32'b10101010101010101110010000000000)) \N318_32[1] ( .Z (N318[1]), - .I0 (_N24508), + .I0 (_N24228), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [41] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [41] ), - .I3 (_N96341), - .I4 (_N24498), + .I3 (_N97168), + .I4 (_N24218), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr )); // LUT = (ID&I2&I3&~I4)|(~ID&I1&I3&~I4)|(I0&I4) ; @@ -169047,11 +168897,11 @@ module ipsxb_mcdq_dcd_bm_v1_2 .INIT(32'b10101010101010101110010000000000)) \N318_32[2] ( .Z (N318[2]), - .I0 (_N24509), + .I0 (_N24229), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [42] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [42] ), - .I3 (_N96341), - .I4 (_N24498), + .I3 (_N97168), + .I4 (_N24218), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr )); // LUT = (ID&I2&I3&~I4)|(~ID&I1&I3&~I4)|(I0&I4) ; @@ -169059,11 +168909,11 @@ module ipsxb_mcdq_dcd_bm_v1_2 .INIT(32'b10101010101010101110010000000000)) \N318_32[3] ( .Z (N318[3]), - .I0 (_N24510), + .I0 (_N24230), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [43] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [43] ), - .I3 (_N96341), - .I4 (_N24498), + .I3 (_N97168), + .I4 (_N24218), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr )); // LUT = (ID&I2&I3&~I4)|(~ID&I1&I3&~I4)|(I0&I4) ; @@ -169071,11 +168921,11 @@ module ipsxb_mcdq_dcd_bm_v1_2 .INIT(32'b10101010101010101110010000000000)) \N318_32[4] ( .Z (N318[4]), - .I0 (_N24511), + .I0 (_N24231), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [44] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [44] ), - .I3 (_N96341), - .I4 (_N24498), + .I3 (_N97168), + .I4 (_N24218), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr )); // LUT = (ID&I2&I3&~I4)|(~ID&I1&I3&~I4)|(I0&I4) ; @@ -169083,11 +168933,11 @@ module ipsxb_mcdq_dcd_bm_v1_2 .INIT(32'b10101010101010101110010000000000)) \N318_32[5] ( .Z (N318[5]), - .I0 (_N24512), + .I0 (_N24232), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [45] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [45] ), - .I3 (_N96341), - .I4 (_N24498), + .I3 (_N97168), + .I4 (_N24218), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr )); // LUT = (ID&I2&I3&~I4)|(~ID&I1&I3&~I4)|(I0&I4) ; @@ -169095,11 +168945,11 @@ module ipsxb_mcdq_dcd_bm_v1_2 .INIT(32'b10101010101010101110010000000000)) \N318_32[6] ( .Z (N318[6]), - .I0 (_N24513), + .I0 (_N24233), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [46] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [46] ), - .I3 (_N96341), - .I4 (_N24498), + .I3 (_N97168), + .I4 (_N24218), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr )); // LUT = (ID&I2&I3&~I4)|(~ID&I1&I3&~I4)|(I0&I4) ; @@ -169107,11 +168957,11 @@ module ipsxb_mcdq_dcd_bm_v1_2 .INIT(32'b10101010101010101110010000000000)) \N318_32[7] ( .Z (N318[7]), - .I0 (_N24514), + .I0 (_N24234), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [47] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [47] ), - .I3 (_N96341), - .I4 (_N24498), + .I3 (_N97168), + .I4 (_N24218), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr )); // LUT = (ID&I2&I3&~I4)|(~ID&I1&I3&~I4)|(I0&I4) ; @@ -169119,11 +168969,11 @@ module ipsxb_mcdq_dcd_bm_v1_2 .INIT(32'b10101010101010101110010000000000)) \N318_32[8] ( .Z (N318[8]), - .I0 (_N24515), + .I0 (_N24235), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [48] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [48] ), - .I3 (_N96341), - .I4 (_N24498), + .I3 (_N97168), + .I4 (_N24218), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr )); // LUT = (ID&I2&I3&~I4)|(~ID&I1&I3&~I4)|(I0&I4) ; @@ -169131,11 +168981,11 @@ module ipsxb_mcdq_dcd_bm_v1_2 .INIT(32'b10101010101010101110010000000000)) \N318_32[9] ( .Z (N318[9]), - .I0 (_N24516), + .I0 (_N24236), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [49] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [49] ), - .I3 (_N96341), - .I4 (_N24498), + .I3 (_N97168), + .I4 (_N24218), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr )); // LUT = (ID&I2&I3&~I4)|(~ID&I1&I3&~I4)|(I0&I4) ; @@ -169143,11 +168993,11 @@ module ipsxb_mcdq_dcd_bm_v1_2 .INIT(32'b10101010101010101110010000000000)) \N318_32[10] ( .Z (N318[10]), - .I0 (_N24517), + .I0 (_N24237), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [50] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [50] ), - .I3 (_N96341), - .I4 (_N24498), + .I3 (_N97168), + .I4 (_N24218), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr )); // LUT = (ID&I2&I3&~I4)|(~ID&I1&I3&~I4)|(I0&I4) ; @@ -169155,11 +169005,11 @@ module ipsxb_mcdq_dcd_bm_v1_2 .INIT(32'b10101010101010101110010000000000)) \N318_32[11] ( .Z (N318[11]), - .I0 (_N24518), + .I0 (_N24238), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [51] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [51] ), - .I3 (_N96341), - .I4 (_N24498), + .I3 (_N97168), + .I4 (_N24218), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr )); // LUT = (ID&I2&I3&~I4)|(~ID&I1&I3&~I4)|(I0&I4) ; @@ -169167,11 +169017,11 @@ module ipsxb_mcdq_dcd_bm_v1_2 .INIT(32'b10101010101010101110010000000000)) \N318_32[12] ( .Z (N318[12]), - .I0 (_N24519), + .I0 (_N24239), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [52] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [52] ), - .I3 (_N96341), - .I4 (_N24498), + .I3 (_N97168), + .I4 (_N24218), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr )); // LUT = (ID&I2&I3&~I4)|(~ID&I1&I3&~I4)|(I0&I4) ; @@ -169179,11 +169029,11 @@ module ipsxb_mcdq_dcd_bm_v1_2 .INIT(32'b10101010101010101110010000000000)) \N318_32[13] ( .Z (N318[13]), - .I0 (_N24520), + .I0 (_N24240), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [53] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [53] ), - .I3 (_N96341), - .I4 (_N24498), + .I3 (_N97168), + .I4 (_N24218), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr )); // LUT = (ID&I2&I3&~I4)|(~ID&I1&I3&~I4)|(I0&I4) ; @@ -169191,25 +169041,34 @@ module ipsxb_mcdq_dcd_bm_v1_2 .INIT(32'b10101010101010101110010000000000)) \N318_32[14] ( .Z (N318[14]), - .I0 (_N24521), + .I0 (_N24241), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [54] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [54] ), - .I3 (_N96341), - .I4 (_N24498), + .I3 (_N97168), + .I4 (_N24218), .ID (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr )); // LUT = (ID&I2&I3&~I4)|(~ID&I1&I3&~I4)|(I0&I4) ; GTP_LUT5 /* N318_36 */ #( .INIT(32'b01000000111111110100000001000000)) N318_36 ( - .Z (_N24498), + .Z (_N24218), .I0 (dec_done), .I1 (dec_new_valid), .I2 (dec_pre_row), .I3 (rowaddr_check_diff), - .I4 (_N96341)); + .I4 (_N97168)); // LUT = (~I3&I4)|(~I0&I1&I2) ; + GTP_LUT3 /* N335_3 */ #( + .INIT(8'b11101111)) + N335_3 ( + .Z (_N97165), + .I0 (dec_pre_row), + .I1 (dec_refresh), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg [0] )); + // LUT = (~I2)|(I0)|(I1) ; + GTP_DFF_CE /* \dec_addr[0] */ #( .GRS_EN("TRUE"), .INIT(1'b0)) @@ -169650,14 +169509,14 @@ module ipsxb_mcdq_dcd_bm_v1_2 .C (N27), .CE (N201), .CLK (clk), - .D (_N74589)); + .D (_N75550)); // defparam dec_refresh_vname.orig_name = dec_refresh; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcd_bm_v1_2.vp:414 - GTP_LUT4 /* dec_refresh_4890 */ #( + GTP_LUT4 /* dec_refresh_4904 */ #( .INIT(16'b0001000100010011)) - dec_refresh_4890 ( - .Z (_N74589), + dec_refresh_4904 ( + .Z (_N75550), .I0 (user_cmd_ready), .I1 (dec_done), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_valid_0 ), @@ -169677,18 +169536,18 @@ module ipsxb_mcdq_dcd_bm_v1_2 // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcd_bm_v1_2.vp:414 ipsxb_mcdq_dcd_rowaddr_v1_2 mcdq_dcd_rowaddr ( - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg [0] }), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [39] , 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [19] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [18] , 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [39] , 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [19] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [18] , 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0 [39] , 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), + .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1 [39] , 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), .user_bank_addr ({user_addr[12], user_addr[11], user_addr[10]}), - ._N24867 (_N24867), - ._N24870 (_N24870), - ._N96029 (_N96029), + ._N24587 (_N24587), + ._N24590 (_N24590), .rowaddr_check_diff (rowaddr_check_diff), .N0 (N27), + ._N96998 (_N96998), + ._N96999 (_N96999), + ._N97000 (_N97000), + ._N97001 (_N97001), .clk (clk), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/dec_done (dec_done), - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/dec_new_valid (dec_new_valid), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/dec_refresh (dec_refresh), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/r_init (r_init), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_valid_0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_valid_0 ), @@ -169858,14 +169717,14 @@ module ipsxb_mcdq_dcd_bm_v1_2 .Q (refresh_req), .C (N27), .CLK (clk), - .D (_N103436)); + .D (_N104248)); // defparam refresh_req_vname.orig_name = refresh_req; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcd_bm_v1_2.vp:329 GTP_LUT3 /* refresh_req_ce_mux */ #( .INIT(8'b01010001)) refresh_req_ce_mux ( - .Z (_N103436), + .Z (_N104248), .I0 (dec_refresh), .I1 (N33), .I2 (refresh_req)); @@ -170058,7 +169917,7 @@ module ipsxb_mcdq_dcd_sm_v1_2 input [3:0] dec_len, input [9:0] nb2, input N0, - input _N96029, + input _N97165, input buffer_almost_full, input clk, input dec_new_row, @@ -170073,7 +169932,7 @@ module ipsxb_mcdq_dcd_sm_v1_2 output [3:0] dcd_wr_cmd, output [3:0] dcd_wr_id, output [6:0] state_reg, - output _N96341, + output _N97168, output dcd_wr_en, output dcd_wr_tworw, output dec_done @@ -170085,7 +169944,6 @@ module ipsxb_mcdq_dcd_sm_v1_2 wire [27:0] N162; wire N258; wire N371; - wire N404; wire N410; wire N416; wire [3:0] N417; @@ -170099,25 +169957,28 @@ module ipsxb_mcdq_dcd_sm_v1_2 wire [7:0] N499; wire _N7; wire _N9; - wire _N18; wire _N22; - wire _N15215; - wire _N15216; - wire _N15217; - wire _N15218; - wire _N15219; - wire _N15220; - wire _N24960; - wire _N24969; - wire _N24973; - wire _N24977; - wire _N75400; - wire _N75622; - wire _N75683; - wire _N84037; - wire _N95818; - wire _N96157; - wire _N103437; + wire _N15256; + wire _N15257; + wire _N15258; + wire _N15259; + wire _N15260; + wire _N15261; + wire _N24686; + wire _N24695; + wire _N24699; + wire _N24703; + wire _N75927; + wire _N75990; + wire _N76080; + wire _N76284; + wire _N76437; + wire _N76472; + wire _N76576; + wire _N84823; + wire _N96670; + wire _N104249; + wire _N107589; wire [3:0] cnt; wire [27:0] dec_addr_d; wire rw_diff; @@ -170155,7 +170016,7 @@ module ipsxb_mcdq_dcd_sm_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) \N162_6_0[9:0]_1 ( - .COUT (_N15215), + .COUT (_N15256), .Z (N162[3]), .CIN (), .I0 (dcd_wr_tworw), @@ -170174,9 +170035,9 @@ module ipsxb_mcdq_dcd_sm_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) \N162_6_1[9:0] ( - .COUT (_N15216), + .COUT (_N15257), .Z (N162[4]), - .CIN (_N15215), + .CIN (_N15256), .I0 (dcd_wr_tworw), .I1 (dcd_wr_addr[3]), .I2 (nb2[4]), @@ -170193,9 +170054,9 @@ module ipsxb_mcdq_dcd_sm_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) \N162_6_2[9:0] ( - .COUT (_N15217), + .COUT (_N15258), .Z (N162[5]), - .CIN (_N15216), + .CIN (_N15257), .I0 (), .I1 (nb2[5]), .I2 (), @@ -170212,9 +170073,9 @@ module ipsxb_mcdq_dcd_sm_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) \N162_6_3[9:0] ( - .COUT (_N15218), + .COUT (_N15259), .Z (N162[6]), - .CIN (_N15217), + .CIN (_N15258), .I0 (), .I1 (nb2[6]), .I2 (), @@ -170231,9 +170092,9 @@ module ipsxb_mcdq_dcd_sm_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) \N162_6_4[9:0] ( - .COUT (_N15219), + .COUT (_N15260), .Z (N162[7]), - .CIN (_N15218), + .CIN (_N15259), .I0 (), .I1 (nb2[7]), .I2 (), @@ -170250,9 +170111,9 @@ module ipsxb_mcdq_dcd_sm_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) \N162_6_5[9:0] ( - .COUT (_N15220), + .COUT (_N15261), .Z (N162[8]), - .CIN (_N15219), + .CIN (_N15260), .I0 (), .I1 (nb2[8]), .I2 (), @@ -170271,7 +170132,7 @@ module ipsxb_mcdq_dcd_sm_v1_2 \N162_6_6[9:0] ( .COUT (), .Z (N162[9]), - .CIN (_N15220), + .CIN (_N15261), .I0 (), .I1 (nb2[9]), .I2 (), @@ -170310,23 +170171,10 @@ module ipsxb_mcdq_dcd_sm_v1_2 .I2 (state_reg[4]), .I3 (dec_refresh), .I4 (N491), - .ID (_N96157)); + .ID (_N96670)); // defparam N371_vname.orig_name = N371; // LUT = (~I1&I3&~I4)|(~I1&~I2&~I4)|(~ID&~I2&~I4)|(I0&~I1&I3)|(I0&~I1&~I2) ; - GTP_LUT5 /* N404 */ #( - .INIT(32'b01010101010101010101010101010001)) - N404_vname ( - .Z (N404), - .I0 (buffer_almost_full), - .I1 (dec_len[0]), - .I2 (dec_len[1]), - .I3 (dec_len[2]), - .I4 (dec_len[3])); - // defparam N404_vname.orig_name = N404; - // LUT = (~I0&~I1)|(~I0&I2)|(~I0&I3)|(~I0&I4) ; - // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcd_sm_v1_2.vp:301 - GTP_LUT4 /* N410 */ #( .INIT(16'b0000000000000100)) N410_vname ( @@ -170342,7 +170190,7 @@ module ipsxb_mcdq_dcd_sm_v1_2 GTP_LUT5 /* N414_3 */ #( .INIT(32'b11111100111111001111110010101000)) N414_3 ( - .Z (_N84037), + .Z (_N84823), .I0 (N258), .I1 (state_reg[3]), .I2 (state_reg[5]), @@ -170350,14 +170198,6 @@ module ipsxb_mcdq_dcd_sm_v1_2 .I4 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/buffer_almost_full_b )); // LUT = (I0&I1)|(I0&I2)|(I1&I3)|(I1&I4)|(I2&I3)|(I2&I4) ; - GTP_LUT2 /* N414_4 */ #( - .INIT(4'b1110)) - N414_4 ( - .Z (_N96157), - .I0 (state_reg[2]), - .I1 (state_reg[1])); - // LUT = (I0)|(I1) ; - GTP_LUT5 /* N416 */ #( .INIT(32'b00000101010001010000000001000100)) N416_vname ( @@ -170374,7 +170214,7 @@ module ipsxb_mcdq_dcd_sm_v1_2 GTP_LUT5 /* N417_14 */ #( .INIT(32'b00000000000000110000000010111000)) N417_14 ( - .Z (_N24960), + .Z (_N24686), .I0 (N39), .I1 (N410), .I2 (N416), @@ -170385,7 +170225,7 @@ module ipsxb_mcdq_dcd_sm_v1_2 GTP_LUT5 /* N417_23 */ #( .INIT(32'b00000000000000110000000000000100)) N417_23 ( - .Z (_N24969), + .Z (_N24695), .I0 (N39), .I1 (N410), .I2 (N416), @@ -170396,8 +170236,8 @@ module ipsxb_mcdq_dcd_sm_v1_2 GTP_LUT5 /* \N417_24[3] */ #( .INIT(32'b11111111111111101010101010101011)) \N417_24[3] ( - .Z (_N24973), - .I0 (_N24969), + .Z (_N24699), + .I0 (_N24695), .I1 (cnt[0]), .I2 (cnt[1]), .I3 (cnt[2]), @@ -170407,8 +170247,8 @@ module ipsxb_mcdq_dcd_sm_v1_2 GTP_LUT5 /* \N417_25[3] */ #( .INIT(32'b11101110111001000100010001001110)) \N417_25[3] ( - .Z (_N24977), - .I0 (_N24969), + .Z (_N24703), + .I0 (_N24695), .I1 (dec_len[3]), .I2 (cnt[1]), .I3 (cnt[2]), @@ -170419,8 +170259,8 @@ module ipsxb_mcdq_dcd_sm_v1_2 .INIT(16'b0101010000110010)) \N417_26[0] ( .Z (N417[0]), - .I0 (_N24960), - .I1 (_N24969), + .I0 (_N24686), + .I1 (_N24695), .I2 (dec_len[0]), .I3 (cnt[0])); // LUT = (I0&~I1&~I3)|(~I0&~I1&I2)|(~I0&I1&I3) ; @@ -170429,8 +170269,8 @@ module ipsxb_mcdq_dcd_sm_v1_2 .INIT(32'b00110010000100000101010001110110)) \N417_26[1] ( .Z (N417[1]), - .I0 (_N24960), - .I1 (_N24969), + .I0 (_N24686), + .I1 (_N24695), .I2 (dec_len[1]), .I3 (cnt[0]), .I4 (cnt[1])); @@ -170441,38 +170281,30 @@ module ipsxb_mcdq_dcd_sm_v1_2 \N417_26[2] ( .Z (N417[2]), .I0 (cnt[0]), - .I1 (_N24969), + .I1 (_N24695), .I2 (cnt[1]), .I3 (cnt[2]), - .I4 (_N24960), + .I4 (_N24686), .ID (dec_len[2])); // LUT = (I1&~I2&~I3&~I4)|(I1&I2&I3&~I4)|(ID&~I1&~I4)|(~I0&~I1&~I2&~I3&I4)|(~I1&I2&I3&I4)|(I0&~I1&I3&I4) ; GTP_MUX2LUT6 \N417_26[3] ( .Z (N417[3]), - .I0 (_N24977), - .I1 (_N24973), - .S (_N24960)); + .I0 (_N24703), + .I1 (_N24699), + .S (_N24686)); - GTP_LUT3 /* N417_27 */ #( - .INIT(8'b01000000)) - N417_27 ( - .Z (_N95818), - .I0 (dec_done), - .I1 (dec_new_valid), - .I2 (state_reg[0])); - // LUT = ~I0&I1&I2 ; - - GTP_LUT4 /* N418 */ #( - .INIT(16'b0000000001010001)) + GTP_LUT5 /* N418 */ #( + .INIT(32'b00000000000001010000000000010101)) N418_vname ( .Z (N418), - .I0 (_N84037), - .I1 (state_reg[2]), - .I2 (N404), - .I3 (state_reg[1])); + .I0 (_N84823), + .I1 (buffer_almost_full), + .I2 (state_reg[2]), + .I3 (state_reg[1]), + .I4 (N499[5])); // defparam N418_vname.orig_name = N418; - // LUT = (~I0&~I1&~I3)|(~I0&I2&~I3) ; + // LUT = (~I0&~I2&~I3)|(~I0&~I1&~I3&~I4) ; GTP_LUT5 /* \N442_10[0] */ #( .INIT(32'b01010101011101000101010101110111)) @@ -170521,7 +170353,7 @@ module ipsxb_mcdq_dcd_sm_v1_2 .I1 (rw_diff), .I2 (state_reg[0]), .I3 (state_reg[3]), - .I4 (_N96157)); + .I4 (_N96670)); // LUT = (I2)|(I4)|(~I0&I1&I3) ; GTP_LUT3 /* \N462_1[0] */ #( @@ -170554,36 +170386,6 @@ module ipsxb_mcdq_dcd_sm_v1_2 // LUT = (I0&~I1)|(I1&I2) ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcd_sm_v1_2.vp:373 - GTP_LUT3 /* \N462_1[3] */ #( - .INIT(8'b11100100)) - \N462_1[3] ( - .Z (N462[3]), - .I0 (N461), - .I1 (N162[3]), - .I2 (dec_addr_d[3])); - // LUT = (~I0&I1)|(I0&I2) ; - // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcd_sm_v1_2.vp:373 - - GTP_LUT3 /* \N462_1[4] */ #( - .INIT(8'b11100100)) - \N462_1[4] ( - .Z (N462[4]), - .I0 (N461), - .I1 (N162[4]), - .I2 (dec_addr_d[4])); - // LUT = (~I0&I1)|(I0&I2) ; - // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcd_sm_v1_2.vp:373 - - GTP_LUT3 /* \N462_1[5] */ #( - .INIT(8'b11100100)) - \N462_1[5] ( - .Z (N462[5]), - .I0 (N461), - .I1 (N162[5]), - .I2 (dec_addr_d[5])); - // LUT = (~I0&I1)|(I0&I2) ; - // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcd_sm_v1_2.vp:373 - GTP_LUT3 /* \N462_1[6] */ #( .INIT(8'b11100100)) \N462_1[6] ( @@ -170710,7 +170512,7 @@ module ipsxb_mcdq_dcd_sm_v1_2 .C (N0), .CE (N458), .CLK (clk), - .D (N462[3])); + .D (_N75927)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcd_sm_v1_2.vp:358 GTP_DFF_CE /* \dcd_wr_addr[4] */ #( @@ -170721,7 +170523,7 @@ module ipsxb_mcdq_dcd_sm_v1_2 .C (N0), .CE (N458), .CLK (clk), - .D (N462[4])); + .D (_N75990)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcd_sm_v1_2.vp:358 GTP_DFF_CE /* \dcd_wr_addr[5] */ #( @@ -170732,7 +170534,7 @@ module ipsxb_mcdq_dcd_sm_v1_2 .C (N0), .CE (N458), .CLK (clk), - .D (N462[5])); + .D (_N76080)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcd_sm_v1_2.vp:358 GTP_DFF_CE /* \dcd_wr_addr[6] */ #( @@ -170754,7 +170556,7 @@ module ipsxb_mcdq_dcd_sm_v1_2 .C (N0), .CE (N458), .CLK (clk), - .D (_N75400)); + .D (_N76284)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcd_sm_v1_2.vp:358 GTP_DFF_CE /* \dcd_wr_addr[8] */ #( @@ -170771,23 +170573,64 @@ module ipsxb_mcdq_dcd_sm_v1_2 GTP_LUT5 /* \dcd_wr_addr[9:0]_0 */ #( .INIT(32'b11111111000000001111110100100000)) \dcd_wr_addr[9:0]_0 ( - .Z (_N75400), + .Z (_N75927), .I0 (dcd_wr_en), .I1 (state_reg[0]), - .I2 (N162[7]), - .I3 (dec_addr_d[7]), - .I4 (_N96157)); + .I2 (N162[3]), + .I3 (dec_addr_d[3]), + .I4 (_N96670)); // LUT = (~I0&I3)|(I1&I3)|(I3&I4)|(I0&~I1&I2&~I4) ; + GTP_LUT2 /* \dcd_wr_addr[9:0]_4 */ #( + .INIT(4'b1110)) + \dcd_wr_addr[9:0]_4 ( + .Z (_N96670), + .I0 (state_reg[2]), + .I1 (state_reg[1])); + // LUT = (I0)|(I1) ; + GTP_LUT5 /* \dcd_wr_addr[9:0]_6 */ #( .INIT(32'b11111111000000001111110100100000)) \dcd_wr_addr[9:0]_6 ( - .Z (_N75622), + .Z (_N75990), + .I0 (dcd_wr_en), + .I1 (state_reg[0]), + .I2 (N162[4]), + .I3 (dec_addr_d[4]), + .I4 (_N96670)); + // LUT = (~I0&I3)|(I1&I3)|(I3&I4)|(I0&~I1&I2&~I4) ; + + GTP_LUT5 /* \dcd_wr_addr[9:0]_98 */ #( + .INIT(32'b11111111000000001111110100100000)) + \dcd_wr_addr[9:0]_98 ( + .Z (_N76080), + .I0 (dcd_wr_en), + .I1 (state_reg[0]), + .I2 (N162[5]), + .I3 (dec_addr_d[5]), + .I4 (_N96670)); + // LUT = (~I0&I3)|(I1&I3)|(I3&I4)|(I0&~I1&I2&~I4) ; + + GTP_LUT5 /* \dcd_wr_addr[9:0]_421 */ #( + .INIT(32'b11111111000000001111110100100000)) + \dcd_wr_addr[9:0]_421 ( + .Z (_N76437), .I0 (dcd_wr_en), .I1 (state_reg[0]), .I2 (N162[9]), .I3 (dec_addr_d[9]), - .I4 (_N96157)); + .I4 (_N96670)); + // LUT = (~I0&I3)|(I1&I3)|(I3&I4)|(I0&~I1&I2&~I4) ; + + GTP_LUT5 /* \dcd_wr_addr[9:0]_423 */ #( + .INIT(32'b11111111000000001111110100100000)) + \dcd_wr_addr[9:0]_423 ( + .Z (_N76284), + .I0 (dcd_wr_en), + .I1 (state_reg[0]), + .I2 (N162[7]), + .I3 (dec_addr_d[7]), + .I4 (_N96670)); // LUT = (~I0&I3)|(I1&I3)|(I3&I4)|(I0&~I1&I2&~I4) ; GTP_DFF_CE /* \dcd_wr_addr[9] */ #( @@ -170798,7 +170641,7 @@ module ipsxb_mcdq_dcd_sm_v1_2 .C (N0), .CE (N458), .CLK (clk), - .D (_N75622)); + .D (_N76437)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcd_sm_v1_2.vp:358 GTP_DFF_CE /* \dcd_wr_addr[10] */ #( @@ -171406,7 +171249,7 @@ module ipsxb_mcdq_dcd_sm_v1_2 rw_diff_vname ( .Q (rw_diff), .CLK (clk), - .D (_N103437), + .D (_N104249), .P (N0)); // defparam rw_diff_vname.orig_name = rw_diff; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcd_sm_v1_2.vp:358 @@ -171414,12 +171257,22 @@ module ipsxb_mcdq_dcd_sm_v1_2 GTP_LUT3 /* rw_diff_ce_mux */ #( .INIT(8'b11001110)) rw_diff_ce_mux ( - .Z (_N103437), + .Z (_N104249), .I0 (rw_diff), .I1 (state_reg[0]), .I2 (state_reg[3])); // LUT = (I1)|(I0&~I2) ; + GTP_LUT4 /* \state_fsm[2:0]_7 */ #( + .INIT(16'b0001010100000000)) + \state_fsm[2:0]_7 ( + .Z (_N97168), + .I0 (dec_done), + .I1 (dec_new_valid), + .I2 (dec_pre_row), + .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N62 )); + // LUT = (~I0&~I2&I3)|(~I0&~I1&I3) ; + GTP_LUT4 /* \state_fsm[2:0]_9 */ #( .INIT(16'b1111101111110000)) \state_fsm[2:0]_9 ( @@ -171430,9 +171283,9 @@ module ipsxb_mcdq_dcd_sm_v1_2 .I3 (state_reg[0])); // LUT = (I2)|(~I1&I3)|(I0&I3) ; - GTP_LUT5 /* \state_fsm[2:0]_10 */ #( + GTP_LUT5 /* \state_fsm[2:0]_10_3 */ #( .INIT(32'b00000000010000000000000000000000)) - \state_fsm[2:0]_10 ( + \state_fsm[2:0]_10_3 ( .Z (_N9), .I0 (dec_done), .I1 (dec_new_valid), @@ -171441,9 +171294,9 @@ module ipsxb_mcdq_dcd_sm_v1_2 .I4 (state_reg[0])); // LUT = ~I0&I1&I2&~I3&I4 ; - GTP_LUT5 /* \state_fsm[2:0]_18 */ #( + GTP_LUT5 /* \state_fsm[2:0]_17 */ #( .INIT(32'b01010100010001000101000000000000)) - \state_fsm[2:0]_18 ( + \state_fsm[2:0]_17 ( .Z (N89), .I0 (buffer_almost_full), .I1 (state_reg[2]), @@ -171452,18 +171305,6 @@ module ipsxb_mcdq_dcd_sm_v1_2 .I4 (N499[5])); // LUT = (~I0&I1&I4)|(~I0&I2&I3) ; - GTP_LUT5 /* \state_fsm[2:0]_19 */ #( - .INIT(32'b11110001000100011111000000000000)) - \state_fsm[2:0]_19 ( - .Z (_N18), - .I0 (dec_new_row), - .I1 (dec_pre_row), - .I2 (state_reg[2]), - .I3 (N404), - .I4 (_N96029)); - // LUT = (I2&I3)|(~I0&~I1&I4) ; - // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcd_sm_v1_2.vp:272 - GTP_LUT4 /* \state_fsm[2:0]_23 */ #( .INIT(16'b0100000000000000)) \state_fsm[2:0]_23 ( @@ -171504,9 +171345,19 @@ module ipsxb_mcdq_dcd_sm_v1_2 .C (N0), .CE (N371), .CLK (clk), - .D (_N75683)); + .D (_N76472)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcd_sm_v1_2.vp:272 + GTP_LUT4 /* state_reg_2_2 */ #( + .INIT(16'b1111111011111111)) + state_reg_2_2 ( + .Z (_N107589), + .I0 (dec_new_row), + .I1 (dec_pre_row), + .I2 (dec_refresh), + .I3 (state_reg[0])); + // LUT = (~I3)|(I0)|(I1)|(I2) ; + (* syn_encoding="onehot" *) GTP_DFF_CE /* \state_reg[3] */ #( .GRS_EN("TRUE"), .INIT(1'b0)) @@ -171515,7 +171366,7 @@ module ipsxb_mcdq_dcd_sm_v1_2 .C (N0), .CE (N371), .CLK (clk), - .D (_N18)); + .D (_N76576)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcd_sm_v1_2.vp:272 (* syn_encoding="onehot" *) GTP_DFF_CE /* \state_reg[4] */ #( @@ -171541,25 +171392,26 @@ module ipsxb_mcdq_dcd_sm_v1_2 // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcd_sm_v1_2.vp:272 GTP_LUT5 /* state_reg_8 */ #( - .INIT(32'b11111111000000101111111100000000)) + .INIT(32'b11111111000000001111111101000000)) state_reg_8 ( - .Z (_N75683), - .I0 (dec_new_row), - .I1 (dec_pre_row), - .I2 (dec_refresh), + .Z (_N76472), + .I0 (dec_done), + .I1 (dec_new_row), + .I2 (dec_new_valid), .I3 (state_reg[1]), - .I4 (_N95818)); - // LUT = (I3)|(I0&~I1&~I2&I4) ; + .I4 (_N97165)); + // LUT = (I3)|(~I0&I1&I2&~I4) ; - GTP_LUT4 /* state_reg_46 */ #( - .INIT(16'b0001010100000000)) - state_reg_46 ( - .Z (_N96341), + GTP_LUT5 /* state_reg_5061 */ #( + .INIT(32'b00000000111100000100010011110100)) + state_reg_5061 ( + .Z (_N76576), .I0 (dec_done), .I1 (dec_new_valid), - .I2 (dec_pre_row), - .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/N62 )); - // LUT = (~I0&~I2&I3)|(~I0&~I1&I3) ; + .I2 (state_reg[2]), + .I3 (N499[5]), + .I4 (_N107589)); + // LUT = (I2&~I3)|(~I0&I1&~I4) ; endmodule @@ -171588,8 +171440,8 @@ module ipsxb_mcdq_dcd_top_v1_2 output dcd_wr_tworw, output user_cmd_ready ); - wire _N96029; - wire _N96341; + wire _N97165; + wire _N97168; wire [27:0] dec_addr; wire dec_done; wire [3:0] dec_id; @@ -171618,7 +171470,7 @@ module ipsxb_mcdq_dcd_top_v1_2 .user_addr ({user_addr[27], user_addr[26], user_addr[25], user_addr[24], user_addr[23], user_addr[22], user_addr[21], user_addr[20], user_addr[19], user_addr[18], user_addr[17], user_addr[16], user_addr[15], user_addr[14], user_addr[13], user_addr[12], user_addr[11], user_addr[10], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), .user_len ({1'bx, user_len[2], 1'bx, 1'bx}), .N62 (\mcdq_dcd_bm/N62 ), - ._N96029 (_N96029), + ._N97165 (_N97165), .dec_new_row (dec_new_row), .dec_new_valid (dec_new_valid), .dec_pre_row (dec_pre_row), @@ -171626,7 +171478,7 @@ module ipsxb_mcdq_dcd_top_v1_2 .dec_write (dec_write), .user_cmd_ready (user_cmd_ready), .N27 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/rst ), - ._N96341 (_N96341), + ._N97168 (_N97168), .clk (clk), .dec_done (dec_done), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/ddrc_init_done (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/ddrc_init_done ), @@ -171644,12 +171496,12 @@ module ipsxb_mcdq_dcd_top_v1_2 .dec_id (dec_id), .dec_len (dec_len), .nb2 ({\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/dcd_wr_col [9] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/dcd_wr_col [8] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/dcd_wr_col [7] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/dcd_wr_col [6] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/dcd_wr_col [5] , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/dcd_wr_col [4] , 1'bx, 1'bx, 1'bx, 1'bx}), - ._N96341 (_N96341), + ._N97168 (_N97168), .dcd_wr_en (dcd_wr_en), .dcd_wr_tworw (dcd_wr_tworw), .dec_done (dec_done), .N0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/rst ), - ._N96029 (_N96029), + ._N97165 (_N97165), .buffer_almost_full (buffer_almost_full), .clk (clk), .dec_new_row (dec_new_row), @@ -171668,7 +171520,6 @@ endmodule module ipsxb_mcdq_timing_pre_pass_v1_2 ( - input [42:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata , input N12, input clk, input cmd_wr_l, @@ -171691,9 +171542,9 @@ module ipsxb_mcdq_timing_pre_pass_v1_2 wire N97; wire N99; wire _N3_inv_1; - wire _N6888; - wire _N104959; - wire _N104965; + wire _N6961; + wire _N105977; + wire _N105983; wire cmd_wr; wire [4:0] nb0; wire [5:0] timing_cnt0; @@ -171703,7 +171554,7 @@ module ipsxb_mcdq_timing_pre_pass_v1_2 GTP_LUT4 /* N50_4 */ #( .INIT(16'b1010101010101000)) N50_4 ( - .Z (_N104959), + .Z (_N105977), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1199 ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_act ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_rd ), @@ -171721,21 +171572,10 @@ module ipsxb_mcdq_timing_pre_pass_v1_2 .I4 (timing_cnt1[0])); // LUT = (I0)|(I1)|(I2&I3)|(I2&I4) ; - GTP_LUT5 /* N55_mux6_1 */ #( - .INIT(32'b00000000000000000000000000001110)) - N55_mux6_1 ( - .Z (cmd_wr), - .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wr ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wr ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [15] ), - .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [16] ), - .I4 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [17] )); - // LUT = (I0&~I2&~I3&~I4)|(I1&~I2&~I3&~I4) ; - GTP_LUT3 /* N59_mux2 */ #( .INIT(8'b10101000)) N59_mux2 ( - .Z (_N6888), + .Z (_N6961), .I0 (timing_cnt2[2]), .I1 (timing_cnt2[1]), .I2 (timing_cnt2[0])); @@ -171745,7 +171585,7 @@ module ipsxb_mcdq_timing_pre_pass_v1_2 .INIT(32'b00000000000000000000000000010101)) N61_3 ( .Z (N61), - .I0 (_N6888), + .I0 (_N6961), .I1 (timing_cnt0[2]), .I2 (timing_cnt0[1]), .I3 (timing_cnt2[3]), @@ -171848,6 +171688,15 @@ module ipsxb_mcdq_timing_pre_pass_v1_2 .I4 (timing_cnt1[2])); // LUT = (~I0&I1)|(~I0&I2&I3)|(~I0&I2&I4) ; + GTP_LUT3 /* \N91_9[4]_1 */ #( + .INIT(8'b10101000)) + \N91_9[4]_1 ( + .Z (cmd_wr), + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1199 ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wr ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wr )); + // LUT = (I0&I1)|(I0&I2) ; + GTP_LUT5 /* \N94_2[0] */ #( .INIT(32'b11111111111110001000100010001000)) \N94_2[0] ( @@ -171898,7 +171747,7 @@ module ipsxb_mcdq_timing_pre_pass_v1_2 .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wr ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wr ), .I3 (N61), - .I4 (_N104959)); + .I4 (_N105977)); // defparam N97_vname.orig_name = N97; // LUT = (~I0&I3&~I4)|(~I1&~I2&I3&~I4) ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_timing_pre_pass_v1_2.vp:222 @@ -171906,7 +171755,7 @@ module ipsxb_mcdq_timing_pre_pass_v1_2 GTP_LUT5 /* N99_2 */ #( .INIT(32'b00000000000000000001010101010101)) N99_2 ( - .Z (_N104965), + .Z (_N105983), .I0 (timing_cnt2[3]), .I1 (timing_cnt2[2]), .I2 (timing_cnt2[1]), @@ -171920,8 +171769,8 @@ module ipsxb_mcdq_timing_pre_pass_v1_2 .Z (N99), .I0 (N61), .I1 (cmd_wr), - .I2 (_N104959), - .I3 (_N104965)); + .I2 (_N105977), + .I3 (_N105983)); // LUT = ~I0&~I1&~I2&I3 ; GTP_DFF_C /* r_cnt_almost_pass */ #( @@ -172060,7 +171909,6 @@ endmodule module ipsxb_mcdq_timing_pre_pass_v1_2_unq18 ( - input [42:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata , input N12, input clk, input cmd_wr_l, @@ -172083,9 +171931,9 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq18 wire N97; wire N99; wire _N3_inv_1; - wire _N7000; - wire _N104895; - wire _N104901; + wire _N7073; + wire _N105913; + wire _N105919; wire cmd_wr; wire [4:0] nb0; wire [5:0] timing_cnt0; @@ -172095,7 +171943,7 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq18 GTP_LUT4 /* N50_4 */ #( .INIT(16'b1010101010101000)) N50_4 ( - .Z (_N104895), + .Z (_N105913), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1200 ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_act ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_rd ), @@ -172116,7 +171964,7 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq18 GTP_LUT3 /* N59_mux2 */ #( .INIT(8'b10101000)) N59_mux2 ( - .Z (_N7000), + .Z (_N7073), .I0 (timing_cnt2[2]), .I1 (timing_cnt2[1]), .I2 (timing_cnt2[0])); @@ -172126,7 +171974,7 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq18 .INIT(32'b00000000000000000000000000010101)) N61_3 ( .Z (N61), - .I0 (_N7000), + .I0 (_N7073), .I1 (timing_cnt0[2]), .I2 (timing_cnt0[1]), .I3 (timing_cnt2[3]), @@ -172144,9 +171992,9 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq18 .I4 (timing_cnt1[0])); // LUT = (I0)|(I1)|(I2&I3&I4) ; - GTP_LUT5 /* \N88_2[1]_3 */ #( + GTP_LUT5 /* \N88_2[1]_5 */ #( .INIT(32'b01110111001000000010000000100000)) - \N88_2[1]_3 ( + \N88_2[1]_5 ( .Z (N88[1]), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1200 ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_rd ), @@ -172229,16 +172077,14 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq18 .I4 (timing_cnt1[2])); // LUT = (~I0&I1)|(~I0&I2&I3)|(~I0&I2&I4) ; - GTP_LUT5 /* \N91_9[4]_1 */ #( - .INIT(32'b00000000000000000000000011100000)) + GTP_LUT3 /* \N91_9[4]_1 */ #( + .INIT(8'b10101000)) \N91_9[4]_1 ( .Z (cmd_wr), - .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wr ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wr ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [15] ), - .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [16] ), - .I4 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [17] )); - // LUT = (I0&I2&~I3&~I4)|(I1&I2&~I3&~I4) ; + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1200 ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wr ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wr )); + // LUT = (I0&I1)|(I0&I2) ; GTP_LUT5 /* \N94_2[0] */ #( .INIT(32'b11111111111110001000100010001000)) @@ -172290,7 +172136,7 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq18 .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wr ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wr ), .I3 (N61), - .I4 (_N104895)); + .I4 (_N105913)); // defparam N97_vname.orig_name = N97; // LUT = (~I0&I3&~I4)|(~I1&~I2&I3&~I4) ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_timing_pre_pass_v1_2.vp:222 @@ -172298,7 +172144,7 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq18 GTP_LUT5 /* N99_2 */ #( .INIT(32'b00000000000000000001010101010101)) N99_2 ( - .Z (_N104901), + .Z (_N105919), .I0 (timing_cnt2[3]), .I1 (timing_cnt2[2]), .I2 (timing_cnt2[1]), @@ -172312,8 +172158,8 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq18 .Z (N99), .I0 (N61), .I1 (cmd_wr), - .I2 (_N104895), - .I3 (_N104901)); + .I2 (_N105913), + .I3 (_N105919)); // LUT = ~I0&~I1&~I2&I3 ; GTP_DFF_C /* r_cnt_almost_pass */ #( @@ -172452,7 +172298,6 @@ endmodule module ipsxb_mcdq_timing_pre_pass_v1_2_unq20 ( - input [42:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata , input N12, input clk, input cmd_wr_l, @@ -172475,9 +172320,9 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq20 wire N97; wire N99; wire _N3_inv_1; - wire _N7112; - wire _N104927; - wire _N104933; + wire _N7185; + wire _N105945; + wire _N105951; wire cmd_wr; wire [4:0] nb0; wire [5:0] timing_cnt0; @@ -172487,7 +172332,7 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq20 GTP_LUT4 /* N50_4 */ #( .INIT(16'b1010101010101000)) N50_4 ( - .Z (_N104927), + .Z (_N105945), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1201 ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_act ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_rd ), @@ -172508,7 +172353,7 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq20 GTP_LUT3 /* N59_mux2 */ #( .INIT(8'b10101000)) N59_mux2 ( - .Z (_N7112), + .Z (_N7185), .I0 (timing_cnt2[2]), .I1 (timing_cnt2[1]), .I2 (timing_cnt2[0])); @@ -172518,7 +172363,7 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq20 .INIT(32'b00000000000000000000000000010101)) N61_3 ( .Z (N61), - .I0 (_N7112), + .I0 (_N7185), .I1 (timing_cnt0[2]), .I2 (timing_cnt0[1]), .I3 (timing_cnt2[3]), @@ -172536,6 +172381,15 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq20 .I4 (timing_cnt1[0])); // LUT = (I0)|(I1)|(I2&I3&I4) ; + GTP_LUT3 /* N69_mux6_1 */ #( + .INIT(8'b10101000)) + N69_mux6_1 ( + .Z (cmd_wr), + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1201 ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wr ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wr )); + // LUT = (I0&I1)|(I0&I2) ; + GTP_LUT5 /* \N88_2[1]_3 */ #( .INIT(32'b01110111001000000010000000100000)) \N88_2[1]_3 ( @@ -172621,17 +172475,6 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq20 .I4 (timing_cnt1[2])); // LUT = (~I0&I1)|(~I0&I2&I3)|(~I0&I2&I4) ; - GTP_LUT5 /* \N91_9[4]_1 */ #( - .INIT(32'b00000000000000000000111000000000)) - \N91_9[4]_1 ( - .Z (cmd_wr), - .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wr ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wr ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [15] ), - .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [16] ), - .I4 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [17] )); - // LUT = (I0&~I2&I3&~I4)|(I1&~I2&I3&~I4) ; - GTP_LUT5 /* \N94_2[0] */ #( .INIT(32'b11111111111110001000100010001000)) \N94_2[0] ( @@ -172682,7 +172525,7 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq20 .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wr ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wr ), .I3 (N61), - .I4 (_N104927)); + .I4 (_N105945)); // defparam N97_vname.orig_name = N97; // LUT = (~I0&I3&~I4)|(~I1&~I2&I3&~I4) ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_timing_pre_pass_v1_2.vp:222 @@ -172690,7 +172533,7 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq20 GTP_LUT5 /* N99_2 */ #( .INIT(32'b00000000000000000001010101010101)) N99_2 ( - .Z (_N104933), + .Z (_N105951), .I0 (timing_cnt2[3]), .I1 (timing_cnt2[2]), .I2 (timing_cnt2[1]), @@ -172704,8 +172547,8 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq20 .Z (N99), .I0 (N61), .I1 (cmd_wr), - .I2 (_N104927), - .I3 (_N104933)); + .I2 (_N105945), + .I3 (_N105951)); // LUT = ~I0&~I1&~I2&I3 ; GTP_DFF_C /* r_cnt_almost_pass */ #( @@ -172844,7 +172687,6 @@ endmodule module ipsxb_mcdq_timing_pre_pass_v1_2_unq22 ( - input [42:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata , input N12, input clk, input cmd_wr_l, @@ -172867,9 +172709,9 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq22 wire N97; wire N99; wire _N3_inv_1; - wire _N7224; - wire _N104863; - wire _N104869; + wire _N7297; + wire _N105881; + wire _N105887; wire cmd_wr; wire [4:0] nb0; wire [5:0] timing_cnt0; @@ -172879,7 +172721,7 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq22 GTP_LUT4 /* N50_4 */ #( .INIT(16'b1010101010101000)) N50_4 ( - .Z (_N104863), + .Z (_N105881), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1202 ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_act ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_rd ), @@ -172897,21 +172739,10 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq22 .I4 (timing_cnt1[0])); // LUT = (I0)|(I1)|(I2&I3)|(I2&I4) ; - GTP_LUT5 /* N55_mux6_1 */ #( - .INIT(32'b00000000000000001110000000000000)) - N55_mux6_1 ( - .Z (cmd_wr), - .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wr ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wr ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [15] ), - .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [16] ), - .I4 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [17] )); - // LUT = (I0&I2&I3&~I4)|(I1&I2&I3&~I4) ; - GTP_LUT3 /* N59_mux2 */ #( .INIT(8'b10101000)) N59_mux2 ( - .Z (_N7224), + .Z (_N7297), .I0 (timing_cnt2[2]), .I1 (timing_cnt2[1]), .I2 (timing_cnt2[0])); @@ -172921,7 +172752,7 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq22 .INIT(32'b00000000000000000000000000010101)) N61_3 ( .Z (N61), - .I0 (_N7224), + .I0 (_N7297), .I1 (timing_cnt0[2]), .I2 (timing_cnt0[1]), .I3 (timing_cnt2[3]), @@ -172939,6 +172770,15 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq22 .I4 (timing_cnt1[0])); // LUT = (I0)|(I1)|(I2&I3&I4) ; + GTP_LUT3 /* N69_mux6_1 */ #( + .INIT(8'b10101000)) + N69_mux6_1 ( + .Z (cmd_wr), + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1202 ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wr ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wr )); + // LUT = (I0&I1)|(I0&I2) ; + GTP_LUT5 /* \N88_2[1]_3 */ #( .INIT(32'b01110111001000000010000000100000)) \N88_2[1]_3 ( @@ -173074,7 +172914,7 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq22 .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wr ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wr ), .I3 (N61), - .I4 (_N104863)); + .I4 (_N105881)); // defparam N97_vname.orig_name = N97; // LUT = (~I0&I3&~I4)|(~I1&~I2&I3&~I4) ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_timing_pre_pass_v1_2.vp:222 @@ -173082,7 +172922,7 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq22 GTP_LUT5 /* N99_2 */ #( .INIT(32'b00000000000000000001010101010101)) N99_2 ( - .Z (_N104869), + .Z (_N105887), .I0 (timing_cnt2[3]), .I1 (timing_cnt2[2]), .I2 (timing_cnt2[1]), @@ -173096,8 +172936,8 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq22 .Z (N99), .I0 (N61), .I1 (cmd_wr), - .I2 (_N104863), - .I3 (_N104869)); + .I2 (_N105881), + .I3 (_N105887)); // LUT = ~I0&~I1&~I2&I3 ; GTP_DFF_C /* r_cnt_almost_pass */ #( @@ -173236,7 +173076,6 @@ endmodule module ipsxb_mcdq_timing_pre_pass_v1_2_unq24 ( - input [42:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata , input N12, input clk, input cmd_wr_l, @@ -173259,30 +173098,19 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq24 wire N97; wire N99; wire _N3_inv_1; - wire _N7336; - wire _N104943; - wire _N104949; + wire _N7409; + wire _N105961; + wire _N105967; wire cmd_wr; wire [4:0] nb0; wire [5:0] timing_cnt0; wire [6:0] timing_cnt1; wire [4:0] timing_cnt2; - GTP_LUT5 /* N50_1 */ #( - .INIT(32'b00000000000011100000000000000000)) - N50_1 ( - .Z (cmd_wr), - .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wr ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wr ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [15] ), - .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [16] ), - .I4 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [17] )); - // LUT = (I0&~I2&~I3&I4)|(I1&~I2&~I3&I4) ; - GTP_LUT4 /* N50_4 */ #( .INIT(16'b1010101010101000)) N50_4 ( - .Z (_N104943), + .Z (_N105961), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1203 ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_act ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_rd ), @@ -173303,7 +173131,7 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq24 GTP_LUT3 /* N59_mux2 */ #( .INIT(8'b10101000)) N59_mux2 ( - .Z (_N7336), + .Z (_N7409), .I0 (timing_cnt2[2]), .I1 (timing_cnt2[1]), .I2 (timing_cnt2[0])); @@ -173313,7 +173141,7 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq24 .INIT(32'b00000000000000000000000000010101)) N61_3 ( .Z (N61), - .I0 (_N7336), + .I0 (_N7409), .I1 (timing_cnt0[2]), .I2 (timing_cnt0[1]), .I3 (timing_cnt2[3]), @@ -173416,6 +173244,15 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq24 .I4 (timing_cnt1[2])); // LUT = (~I0&I1)|(~I0&I2&I3)|(~I0&I2&I4) ; + GTP_LUT3 /* \N91_9[0]_1 */ #( + .INIT(8'b10101000)) + \N91_9[0]_1 ( + .Z (cmd_wr), + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1203 ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wr ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wr )); + // LUT = (I0&I1)|(I0&I2) ; + GTP_LUT5 /* \N94_2[0] */ #( .INIT(32'b11111111111110001000100010001000)) \N94_2[0] ( @@ -173466,7 +173303,7 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq24 .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wr ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wr ), .I3 (N61), - .I4 (_N104943)); + .I4 (_N105961)); // defparam N97_vname.orig_name = N97; // LUT = (~I0&I3&~I4)|(~I1&~I2&I3&~I4) ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_timing_pre_pass_v1_2.vp:222 @@ -173474,7 +173311,7 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq24 GTP_LUT5 /* N99_2 */ #( .INIT(32'b00000000000000000001010101010101)) N99_2 ( - .Z (_N104949), + .Z (_N105967), .I0 (timing_cnt2[3]), .I1 (timing_cnt2[2]), .I2 (timing_cnt2[1]), @@ -173488,8 +173325,8 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq24 .Z (N99), .I0 (N61), .I1 (cmd_wr), - .I2 (_N104943), - .I3 (_N104949)); + .I2 (_N105961), + .I3 (_N105967)); // LUT = ~I0&~I1&~I2&I3 ; GTP_DFF_C /* r_cnt_almost_pass */ #( @@ -173628,7 +173465,6 @@ endmodule module ipsxb_mcdq_timing_pre_pass_v1_2_unq26 ( - input [42:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata , input N12, input clk, input cmd_wr_l, @@ -173651,30 +173487,19 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq26 wire N97; wire N99; wire _N3_inv_1; - wire _N7448; - wire _N104879; - wire _N104885; + wire _N7521; + wire _N105897; + wire _N105903; wire cmd_wr; wire [4:0] nb0; wire [5:0] timing_cnt0; wire [6:0] timing_cnt1; wire [4:0] timing_cnt2; - GTP_LUT5 /* N50_1 */ #( - .INIT(32'b00000000111000000000000000000000)) - N50_1 ( - .Z (cmd_wr), - .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wr ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wr ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [15] ), - .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [16] ), - .I4 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [17] )); - // LUT = (I0&I2&~I3&I4)|(I1&I2&~I3&I4) ; - GTP_LUT4 /* N50_4 */ #( .INIT(16'b1010101010101000)) N50_4 ( - .Z (_N104879), + .Z (_N105897), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1204 ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_act ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_rd ), @@ -173695,7 +173520,7 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq26 GTP_LUT3 /* N59_mux2 */ #( .INIT(8'b10101000)) N59_mux2 ( - .Z (_N7448), + .Z (_N7521), .I0 (timing_cnt2[2]), .I1 (timing_cnt2[1]), .I2 (timing_cnt2[0])); @@ -173705,7 +173530,7 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq26 .INIT(32'b00000000000000000000000000010101)) N61_3 ( .Z (N61), - .I0 (_N7448), + .I0 (_N7521), .I1 (timing_cnt0[2]), .I2 (timing_cnt0[1]), .I3 (timing_cnt2[3]), @@ -173808,6 +173633,15 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq26 .I4 (timing_cnt1[2])); // LUT = (~I0&I1)|(~I0&I2&I3)|(~I0&I2&I4) ; + GTP_LUT3 /* \N91_9[4]_1 */ #( + .INIT(8'b10101000)) + \N91_9[4]_1 ( + .Z (cmd_wr), + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1204 ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wr ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wr )); + // LUT = (I0&I1)|(I0&I2) ; + GTP_LUT5 /* \N94_2[0] */ #( .INIT(32'b11111111111110001000100010001000)) \N94_2[0] ( @@ -173858,7 +173692,7 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq26 .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wr ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wr ), .I3 (N61), - .I4 (_N104879)); + .I4 (_N105897)); // defparam N97_vname.orig_name = N97; // LUT = (~I0&I3&~I4)|(~I1&~I2&I3&~I4) ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_timing_pre_pass_v1_2.vp:222 @@ -173866,7 +173700,7 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq26 GTP_LUT5 /* N99_2 */ #( .INIT(32'b00000000000000000001010101010101)) N99_2 ( - .Z (_N104885), + .Z (_N105903), .I0 (timing_cnt2[3]), .I1 (timing_cnt2[2]), .I2 (timing_cnt2[1]), @@ -173880,8 +173714,8 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq26 .Z (N99), .I0 (N61), .I1 (cmd_wr), - .I2 (_N104879), - .I3 (_N104885)); + .I2 (_N105897), + .I3 (_N105903)); // LUT = ~I0&~I1&~I2&I3 ; GTP_DFF_C /* r_cnt_almost_pass */ #( @@ -174020,7 +173854,6 @@ endmodule module ipsxb_mcdq_timing_pre_pass_v1_2_unq28 ( - input [42:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata , input N12, input clk, input cmd_wr_l, @@ -174043,9 +173876,9 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq28 wire N97; wire N99; wire _N3_inv_1; - wire _N7560; - wire _N104911; - wire _N104917; + wire _N7633; + wire _N105929; + wire _N105935; wire cmd_wr; wire [4:0] nb0; wire [5:0] timing_cnt0; @@ -174055,7 +173888,7 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq28 GTP_LUT4 /* N50_4 */ #( .INIT(16'b1010101010101000)) N50_4 ( - .Z (_N104911), + .Z (_N105929), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1205 ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_act ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_rd ), @@ -174073,10 +173906,19 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq28 .I4 (timing_cnt1[0])); // LUT = (I0)|(I1)|(I2&I3)|(I2&I4) ; + GTP_LUT3 /* N55_mux6_1 */ #( + .INIT(8'b10101000)) + N55_mux6_1 ( + .Z (cmd_wr), + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1205 ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wr ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wr )); + // LUT = (I0&I1)|(I0&I2) ; + GTP_LUT3 /* N59_mux2 */ #( .INIT(8'b10101000)) N59_mux2 ( - .Z (_N7560), + .Z (_N7633), .I0 (timing_cnt2[2]), .I1 (timing_cnt2[1]), .I2 (timing_cnt2[0])); @@ -174086,7 +173928,7 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq28 .INIT(32'b00000000000000000000000000010101)) N61_3 ( .Z (N61), - .I0 (_N7560), + .I0 (_N7633), .I1 (timing_cnt0[2]), .I2 (timing_cnt0[1]), .I3 (timing_cnt2[3]), @@ -174104,17 +173946,6 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq28 .I4 (timing_cnt1[0])); // LUT = (I0)|(I1)|(I2&I3&I4) ; - GTP_LUT5 /* N69_mux6_1 */ #( - .INIT(32'b00001110000000000000000000000000)) - N69_mux6_1 ( - .Z (cmd_wr), - .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wr ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wr ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [15] ), - .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [16] ), - .I4 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [17] )); - // LUT = (I0&~I2&I3&I4)|(I1&~I2&I3&I4) ; - GTP_LUT5 /* \N88_2[1]_3 */ #( .INIT(32'b01110111001000000010000000100000)) \N88_2[1]_3 ( @@ -174250,7 +174081,7 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq28 .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wr ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wr ), .I3 (N61), - .I4 (_N104911)); + .I4 (_N105929)); // defparam N97_vname.orig_name = N97; // LUT = (~I0&I3&~I4)|(~I1&~I2&I3&~I4) ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_timing_pre_pass_v1_2.vp:222 @@ -174258,7 +174089,7 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq28 GTP_LUT5 /* N99_2 */ #( .INIT(32'b00000000000000000001010101010101)) N99_2 ( - .Z (_N104917), + .Z (_N105935), .I0 (timing_cnt2[3]), .I1 (timing_cnt2[2]), .I2 (timing_cnt2[1]), @@ -174272,8 +174103,8 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq28 .Z (N99), .I0 (N61), .I1 (cmd_wr), - .I2 (_N104911), - .I3 (_N104917)); + .I2 (_N105929), + .I3 (_N105935)); // LUT = ~I0&~I1&~I2&I3 ; GTP_DFF_C /* r_cnt_almost_pass */ #( @@ -174412,7 +174243,6 @@ endmodule module ipsxb_mcdq_timing_pre_pass_v1_2_unq30 ( - input [42:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata , input N12, input clk, input cmd_wr_l, @@ -174435,9 +174265,9 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq30 wire N97; wire N99; wire _N3_inv_1; - wire _N7672; - wire _N104847; - wire _N104853; + wire _N7745; + wire _N105865; + wire _N105871; wire cmd_wr; wire [4:0] nb0; wire [5:0] timing_cnt0; @@ -174447,7 +174277,7 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq30 GTP_LUT4 /* N50_4 */ #( .INIT(16'b1010101010101000)) N50_4 ( - .Z (_N104847), + .Z (_N105865), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1206 ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_act ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_rd ), @@ -174465,21 +174295,10 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq30 .I4 (timing_cnt1[0])); // LUT = (I0)|(I1)|(I2&I3)|(I2&I4) ; - GTP_LUT5 /* N55_mux6_1 */ #( - .INIT(32'b11100000000000000000000000000000)) - N55_mux6_1 ( - .Z (cmd_wr), - .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wr ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wr ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [15] ), - .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [16] ), - .I4 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [17] )); - // LUT = (I0&I2&I3&I4)|(I1&I2&I3&I4) ; - GTP_LUT3 /* N59_mux2 */ #( .INIT(8'b10101000)) N59_mux2 ( - .Z (_N7672), + .Z (_N7745), .I0 (timing_cnt2[2]), .I1 (timing_cnt2[1]), .I2 (timing_cnt2[0])); @@ -174489,7 +174308,7 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq30 .INIT(32'b00000000000000000000000000010101)) N61_3 ( .Z (N61), - .I0 (_N7672), + .I0 (_N7745), .I1 (timing_cnt0[2]), .I2 (timing_cnt0[1]), .I3 (timing_cnt2[3]), @@ -174592,6 +174411,15 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq30 .I4 (timing_cnt1[2])); // LUT = (~I0&I1)|(~I0&I2&I3)|(~I0&I2&I4) ; + GTP_LUT3 /* \N91_9[4]_1 */ #( + .INIT(8'b10101000)) + \N91_9[4]_1 ( + .Z (cmd_wr), + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1206 ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wr ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wr )); + // LUT = (I0&I1)|(I0&I2) ; + GTP_LUT5 /* \N94_2[0] */ #( .INIT(32'b11111111111110001000100010001000)) \N94_2[0] ( @@ -174642,7 +174470,7 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq30 .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wr ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wr ), .I3 (N61), - .I4 (_N104847)); + .I4 (_N105865)); // defparam N97_vname.orig_name = N97; // LUT = (~I0&I3&~I4)|(~I1&~I2&I3&~I4) ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_timing_pre_pass_v1_2.vp:222 @@ -174650,7 +174478,7 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq30 GTP_LUT5 /* N99_2 */ #( .INIT(32'b00000000000000000001010101010101)) N99_2 ( - .Z (_N104853), + .Z (_N105871), .I0 (timing_cnt2[3]), .I1 (timing_cnt2[2]), .I2 (timing_cnt2[1]), @@ -174664,8 +174492,8 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq30 .Z (N99), .I0 (N61), .I1 (cmd_wr), - .I2 (_N104847), - .I3 (_N104853)); + .I2 (_N105865), + .I3 (_N105871)); // LUT = ~I0&~I1&~I2&I3 ; GTP_DFF_C /* r_cnt_almost_pass */ #( @@ -174811,7 +174639,7 @@ module ipsxb_mcdq_trc_timing_v1_2 output cnt_pass ); wire [4:0] N19; - wire _N103442; + wire _N104254; wire [4:0] timing_cnt; GTP_LUT5 /* \N19_6[0] */ #( @@ -174854,13 +174682,13 @@ module ipsxb_mcdq_trc_timing_v1_2 .Q (cnt_pass), .C (N0), .CLK (clk), - .D (_N103442)); + .D (_N104254)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_trc_timing_v1_2.vp:179 GTP_LUT5 /* r_cnt_pass_ce_mux */ #( .INIT(32'b01110000011100000111000001110111)) r_cnt_pass_ce_mux ( - .Z (_N103442), + .Z (_N104254), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1199 ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_act ), .I2 (cnt_pass), @@ -174911,7 +174739,7 @@ module ipsxb_mcdq_trc_timing_v1_2_unq16 output cnt_pass ); wire [4:0] N19; - wire _N103443; + wire _N104255; wire [4:0] timing_cnt; GTP_LUT5 /* \N19_6[0] */ #( @@ -174954,13 +174782,13 @@ module ipsxb_mcdq_trc_timing_v1_2_unq16 .Q (cnt_pass), .C (N0), .CLK (clk), - .D (_N103443)); + .D (_N104255)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_trc_timing_v1_2.vp:179 GTP_LUT5 /* r_cnt_pass_ce_mux */ #( .INIT(32'b01110000011100000111000001110111)) r_cnt_pass_ce_mux ( - .Z (_N103443), + .Z (_N104255), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1200 ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_act ), .I2 (cnt_pass), @@ -175011,7 +174839,7 @@ module ipsxb_mcdq_trc_timing_v1_2_unq18 output cnt_pass ); wire [4:0] N19; - wire _N103444; + wire _N104256; wire [4:0] timing_cnt; GTP_LUT5 /* \N19_6[0] */ #( @@ -175054,13 +174882,13 @@ module ipsxb_mcdq_trc_timing_v1_2_unq18 .Q (cnt_pass), .C (N0), .CLK (clk), - .D (_N103444)); + .D (_N104256)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_trc_timing_v1_2.vp:179 GTP_LUT5 /* r_cnt_pass_ce_mux */ #( .INIT(32'b01110000011100000111000001110111)) r_cnt_pass_ce_mux ( - .Z (_N103444), + .Z (_N104256), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1201 ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_act ), .I2 (cnt_pass), @@ -175111,7 +174939,7 @@ module ipsxb_mcdq_trc_timing_v1_2_unq20 output cnt_pass ); wire [4:0] N19; - wire _N103445; + wire _N104257; wire [4:0] timing_cnt; GTP_LUT5 /* \N19_6[0] */ #( @@ -175154,13 +174982,13 @@ module ipsxb_mcdq_trc_timing_v1_2_unq20 .Q (cnt_pass), .C (N0), .CLK (clk), - .D (_N103445)); + .D (_N104257)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_trc_timing_v1_2.vp:179 GTP_LUT5 /* r_cnt_pass_ce_mux */ #( .INIT(32'b01110000011100000111000001110111)) r_cnt_pass_ce_mux ( - .Z (_N103445), + .Z (_N104257), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1202 ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_act ), .I2 (cnt_pass), @@ -175211,7 +175039,7 @@ module ipsxb_mcdq_trc_timing_v1_2_unq22 output cnt_pass ); wire [4:0] N19; - wire _N103446; + wire _N104258; wire [4:0] timing_cnt; GTP_LUT5 /* \N19_6[0] */ #( @@ -175254,13 +175082,13 @@ module ipsxb_mcdq_trc_timing_v1_2_unq22 .Q (cnt_pass), .C (N0), .CLK (clk), - .D (_N103446)); + .D (_N104258)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_trc_timing_v1_2.vp:179 GTP_LUT5 /* r_cnt_pass_ce_mux */ #( .INIT(32'b01110000011100000111000001110111)) r_cnt_pass_ce_mux ( - .Z (_N103446), + .Z (_N104258), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1203 ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_act ), .I2 (cnt_pass), @@ -175311,7 +175139,7 @@ module ipsxb_mcdq_trc_timing_v1_2_unq24 output cnt_pass ); wire [4:0] N19; - wire _N103447; + wire _N104259; wire [4:0] timing_cnt; GTP_LUT5 /* \N19_6[0] */ #( @@ -175354,13 +175182,13 @@ module ipsxb_mcdq_trc_timing_v1_2_unq24 .Q (cnt_pass), .C (N0), .CLK (clk), - .D (_N103447)); + .D (_N104259)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_trc_timing_v1_2.vp:179 GTP_LUT5 /* r_cnt_pass_ce_mux */ #( .INIT(32'b01110000011100000111000001110111)) r_cnt_pass_ce_mux ( - .Z (_N103447), + .Z (_N104259), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1204 ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_act ), .I2 (cnt_pass), @@ -175411,7 +175239,7 @@ module ipsxb_mcdq_trc_timing_v1_2_unq26 output cnt_pass ); wire [4:0] N19; - wire _N103448; + wire _N104260; wire [4:0] timing_cnt; GTP_LUT5 /* \N19_6[0] */ #( @@ -175454,13 +175282,13 @@ module ipsxb_mcdq_trc_timing_v1_2_unq26 .Q (cnt_pass), .C (N0), .CLK (clk), - .D (_N103448)); + .D (_N104260)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_trc_timing_v1_2.vp:179 GTP_LUT5 /* r_cnt_pass_ce_mux */ #( .INIT(32'b01110000011100000111000001110111)) r_cnt_pass_ce_mux ( - .Z (_N103448), + .Z (_N104260), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1205 ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_act ), .I2 (cnt_pass), @@ -175511,7 +175339,7 @@ module ipsxb_mcdq_trc_timing_v1_2_unq28 output cnt_pass ); wire [4:0] N19; - wire _N103449; + wire _N104261; wire [4:0] timing_cnt; GTP_LUT5 /* \N19_6[0] */ #( @@ -175554,13 +175382,13 @@ module ipsxb_mcdq_trc_timing_v1_2_unq28 .Q (cnt_pass), .C (N0), .CLK (clk), - .D (_N103449)); + .D (_N104261)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_trc_timing_v1_2.vp:179 GTP_LUT5 /* r_cnt_pass_ce_mux */ #( .INIT(32'b01110000011100000111000001110111)) r_cnt_pass_ce_mux ( - .Z (_N103449), + .Z (_N104261), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1206 ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_act ), .I2 (cnt_pass), @@ -175604,7 +175432,6 @@ endmodule module ipsxb_mcdq_com_timing_v1_2_1 ( - input [42:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata , input N5, input clk, input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1199 , @@ -175612,26 +175439,12 @@ module ipsxb_mcdq_com_timing_v1_2_1 input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_rda , output cnt_pass ); - wire N7; wire N25; wire [5:0] N31; - wire _N103450; - wire _N104755; + wire _N104262; + wire _N105799; wire [5:0] timing_cnt; - GTP_LUT5 /* N7 */ #( - .INIT(32'b00000000000000000000000000001110)) - N7_vname ( - .Z (N7), - .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_rda ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_rda ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [15] ), - .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [16] ), - .I4 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [17] )); - // defparam N7_vname.orig_name = N7; - // LUT = (I0&~I2&~I3&~I4)|(I1&~I2&~I3&~I4) ; - // ../ipcore/axi_ddr/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_com_timing_v1_2.vp:128 - GTP_LUT4 /* N25_mux5 */ #( .INIT(16'b1110111011101010)) N25_mux5 ( @@ -175645,20 +175458,21 @@ module ipsxb_mcdq_com_timing_v1_2_1 GTP_LUT2 /* N31_0_2_2 */ #( .INIT(4'b1110)) N31_0_2_2 ( - .Z (_N104755), + .Z (_N105799), .I0 (timing_cnt[3]), .I1 (timing_cnt[2])); // LUT = (I0)|(I1) ; - GTP_LUT4 /* \N31_2[0]_1 */ #( - .INIT(16'b1111111111100000)) + GTP_LUT5 /* \N31_2[0]_1 */ #( + .INIT(32'b11111111101010001010100010101000)) \N31_2[0]_1 ( .Z (N31[0]), - .I0 (timing_cnt[3]), - .I1 (timing_cnt[2]), - .I2 (timing_cnt[0]), - .I3 (N7)); - // LUT = (I3)|(I0&I2)|(I1&I2) ; + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1199 ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_rda ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_rda ), + .I3 (timing_cnt[0]), + .I4 (_N105799)); + // LUT = (I0&I1)|(I0&I2)|(I3&I4) ; GTP_LUT5 /* \N31_2[1]_1 */ #( .INIT(32'b11011111100010001000100010001000)) @@ -175668,7 +175482,7 @@ module ipsxb_mcdq_com_timing_v1_2_1 .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_rda ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_rda ), .I3 (timing_cnt[1]), - .I4 (_N104755)); + .I4 (_N105799)); // LUT = (I0&I1)|(~I2&I3&I4)|(~I0&I3&I4) ; GTP_LUT5 /* \N31_2[2]_1 */ #( @@ -175699,14 +175513,14 @@ module ipsxb_mcdq_com_timing_v1_2_1 r_cnt_pass ( .Q (cnt_pass), .CLK (clk), - .D (_N103450), + .D (_N104262), .P (N5)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_com_timing_v1_2.vp:135 GTP_LUT5 /* r_cnt_pass_ce_mux */ #( .INIT(32'b01010111000000000101011101010111)) r_cnt_pass_ce_mux ( - .Z (_N103450), + .Z (_N104262), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1199 ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_rda ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_rda ), @@ -175769,8 +175583,8 @@ module ipsxb_mcdq_com_timing_v1_2_1_unq16 ); wire N25; wire [5:0] N31; - wire _N103451; - wire _N104747; + wire _N104263; + wire _N105791; wire [5:0] timing_cnt; GTP_LUT4 /* N25_mux5 */ #( @@ -175786,7 +175600,7 @@ module ipsxb_mcdq_com_timing_v1_2_1_unq16 GTP_LUT2 /* N31_0_2_2 */ #( .INIT(4'b1110)) N31_0_2_2 ( - .Z (_N104747), + .Z (_N105791), .I0 (timing_cnt[3]), .I1 (timing_cnt[2])); // LUT = (I0)|(I1) ; @@ -175799,7 +175613,7 @@ module ipsxb_mcdq_com_timing_v1_2_1_unq16 .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_rda ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_rda ), .I3 (timing_cnt[0]), - .I4 (_N104747)); + .I4 (_N105791)); // LUT = (I0&I1)|(I0&I2)|(I3&I4) ; GTP_LUT5 /* \N31_2[1]_1 */ #( @@ -175810,7 +175624,7 @@ module ipsxb_mcdq_com_timing_v1_2_1_unq16 .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_rda ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_rda ), .I3 (timing_cnt[1]), - .I4 (_N104747)); + .I4 (_N105791)); // LUT = (I0&I1)|(~I2&I3&I4)|(~I0&I3&I4) ; GTP_LUT5 /* \N31_2[2]_1 */ #( @@ -175841,14 +175655,14 @@ module ipsxb_mcdq_com_timing_v1_2_1_unq16 r_cnt_pass ( .Q (cnt_pass), .CLK (clk), - .D (_N103451), + .D (_N104263), .P (N5)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_com_timing_v1_2.vp:135 GTP_LUT5 /* r_cnt_pass_ce_mux */ #( .INIT(32'b01010111000000000101011101010111)) r_cnt_pass_ce_mux ( - .Z (_N103451), + .Z (_N104263), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1200 ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_rda ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_rda ), @@ -175911,8 +175725,8 @@ module ipsxb_mcdq_com_timing_v1_2_1_unq18 ); wire N25; wire [5:0] N31; - wire _N103452; - wire _N104751; + wire _N104264; + wire _N105795; wire [5:0] timing_cnt; GTP_LUT4 /* N25_mux5 */ #( @@ -175928,7 +175742,7 @@ module ipsxb_mcdq_com_timing_v1_2_1_unq18 GTP_LUT2 /* N31_0_2_2 */ #( .INIT(4'b1110)) N31_0_2_2 ( - .Z (_N104751), + .Z (_N105795), .I0 (timing_cnt[3]), .I1 (timing_cnt[2])); // LUT = (I0)|(I1) ; @@ -175941,7 +175755,7 @@ module ipsxb_mcdq_com_timing_v1_2_1_unq18 .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_rda ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_rda ), .I3 (timing_cnt[0]), - .I4 (_N104751)); + .I4 (_N105795)); // LUT = (I0&I1)|(I0&I2)|(I3&I4) ; GTP_LUT5 /* \N31_2[1]_1 */ #( @@ -175952,7 +175766,7 @@ module ipsxb_mcdq_com_timing_v1_2_1_unq18 .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_rda ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_rda ), .I3 (timing_cnt[1]), - .I4 (_N104751)); + .I4 (_N105795)); // LUT = (I0&I1)|(~I2&I3&I4)|(~I0&I3&I4) ; GTP_LUT5 /* \N31_2[2]_1 */ #( @@ -175983,14 +175797,14 @@ module ipsxb_mcdq_com_timing_v1_2_1_unq18 r_cnt_pass ( .Q (cnt_pass), .CLK (clk), - .D (_N103452), + .D (_N104264), .P (N5)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_com_timing_v1_2.vp:135 GTP_LUT5 /* r_cnt_pass_ce_mux */ #( .INIT(32'b01010111000000000101011101010111)) r_cnt_pass_ce_mux ( - .Z (_N103452), + .Z (_N104264), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1201 ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_rda ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_rda ), @@ -176053,8 +175867,8 @@ module ipsxb_mcdq_com_timing_v1_2_1_unq20 ); wire N25; wire [5:0] N31; - wire _N103453; - wire _N104743; + wire _N104265; + wire _N105787; wire [5:0] timing_cnt; GTP_LUT4 /* N25_mux5 */ #( @@ -176070,7 +175884,7 @@ module ipsxb_mcdq_com_timing_v1_2_1_unq20 GTP_LUT2 /* N31_0_2_2 */ #( .INIT(4'b1110)) N31_0_2_2 ( - .Z (_N104743), + .Z (_N105787), .I0 (timing_cnt[3]), .I1 (timing_cnt[2])); // LUT = (I0)|(I1) ; @@ -176083,7 +175897,7 @@ module ipsxb_mcdq_com_timing_v1_2_1_unq20 .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_rda ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_rda ), .I3 (timing_cnt[0]), - .I4 (_N104743)); + .I4 (_N105787)); // LUT = (I0&I1)|(I0&I2)|(I3&I4) ; GTP_LUT5 /* \N31_2[1]_1 */ #( @@ -176094,7 +175908,7 @@ module ipsxb_mcdq_com_timing_v1_2_1_unq20 .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_rda ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_rda ), .I3 (timing_cnt[1]), - .I4 (_N104743)); + .I4 (_N105787)); // LUT = (I0&I1)|(~I2&I3&I4)|(~I0&I3&I4) ; GTP_LUT5 /* \N31_2[2]_1 */ #( @@ -176125,14 +175939,14 @@ module ipsxb_mcdq_com_timing_v1_2_1_unq20 r_cnt_pass ( .Q (cnt_pass), .CLK (clk), - .D (_N103453), + .D (_N104265), .P (N5)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_com_timing_v1_2.vp:135 GTP_LUT5 /* r_cnt_pass_ce_mux */ #( .INIT(32'b01010111000000000101011101010111)) r_cnt_pass_ce_mux ( - .Z (_N103453), + .Z (_N104265), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1202 ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_rda ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_rda ), @@ -176195,8 +176009,8 @@ module ipsxb_mcdq_com_timing_v1_2_1_unq22 ); wire N25; wire [5:0] N31; - wire _N103454; - wire _N104753; + wire _N104266; + wire _N105797; wire [5:0] timing_cnt; GTP_LUT4 /* N25_mux5 */ #( @@ -176212,7 +176026,7 @@ module ipsxb_mcdq_com_timing_v1_2_1_unq22 GTP_LUT2 /* N31_0_2_2 */ #( .INIT(4'b1110)) N31_0_2_2 ( - .Z (_N104753), + .Z (_N105797), .I0 (timing_cnt[3]), .I1 (timing_cnt[2])); // LUT = (I0)|(I1) ; @@ -176225,7 +176039,7 @@ module ipsxb_mcdq_com_timing_v1_2_1_unq22 .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_rda ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_rda ), .I3 (timing_cnt[0]), - .I4 (_N104753)); + .I4 (_N105797)); // LUT = (I0&I1)|(I0&I2)|(I3&I4) ; GTP_LUT5 /* \N31_2[1]_1 */ #( @@ -176236,7 +176050,7 @@ module ipsxb_mcdq_com_timing_v1_2_1_unq22 .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_rda ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_rda ), .I3 (timing_cnt[1]), - .I4 (_N104753)); + .I4 (_N105797)); // LUT = (I0&I1)|(~I2&I3&I4)|(~I0&I3&I4) ; GTP_LUT5 /* \N31_2[2]_1 */ #( @@ -176267,14 +176081,14 @@ module ipsxb_mcdq_com_timing_v1_2_1_unq22 r_cnt_pass ( .Q (cnt_pass), .CLK (clk), - .D (_N103454), + .D (_N104266), .P (N5)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_com_timing_v1_2.vp:135 GTP_LUT5 /* r_cnt_pass_ce_mux */ #( .INIT(32'b01010111000000000101011101010111)) r_cnt_pass_ce_mux ( - .Z (_N103454), + .Z (_N104266), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1203 ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_rda ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_rda ), @@ -176337,8 +176151,8 @@ module ipsxb_mcdq_com_timing_v1_2_1_unq24 ); wire N25; wire [5:0] N31; - wire _N103455; - wire _N104745; + wire _N104267; + wire _N105789; wire [5:0] timing_cnt; GTP_LUT4 /* N25_mux5 */ #( @@ -176354,7 +176168,7 @@ module ipsxb_mcdq_com_timing_v1_2_1_unq24 GTP_LUT2 /* N31_0_2_2 */ #( .INIT(4'b1110)) N31_0_2_2 ( - .Z (_N104745), + .Z (_N105789), .I0 (timing_cnt[3]), .I1 (timing_cnt[2])); // LUT = (I0)|(I1) ; @@ -176367,7 +176181,7 @@ module ipsxb_mcdq_com_timing_v1_2_1_unq24 .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_rda ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_rda ), .I3 (timing_cnt[0]), - .I4 (_N104745)); + .I4 (_N105789)); // LUT = (I0&I1)|(I0&I2)|(I3&I4) ; GTP_LUT5 /* \N31_2[1]_1 */ #( @@ -176378,7 +176192,7 @@ module ipsxb_mcdq_com_timing_v1_2_1_unq24 .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_rda ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_rda ), .I3 (timing_cnt[1]), - .I4 (_N104745)); + .I4 (_N105789)); // LUT = (I0&I1)|(~I2&I3&I4)|(~I0&I3&I4) ; GTP_LUT5 /* \N31_2[2]_1 */ #( @@ -176409,14 +176223,14 @@ module ipsxb_mcdq_com_timing_v1_2_1_unq24 r_cnt_pass ( .Q (cnt_pass), .CLK (clk), - .D (_N103455), + .D (_N104267), .P (N5)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_com_timing_v1_2.vp:135 GTP_LUT5 /* r_cnt_pass_ce_mux */ #( .INIT(32'b01010111000000000101011101010111)) r_cnt_pass_ce_mux ( - .Z (_N103455), + .Z (_N104267), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1204 ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_rda ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_rda ), @@ -176479,8 +176293,8 @@ module ipsxb_mcdq_com_timing_v1_2_1_unq26 ); wire N25; wire [5:0] N31; - wire _N103456; - wire _N104749; + wire _N104268; + wire _N105793; wire [5:0] timing_cnt; GTP_LUT4 /* N25_mux5 */ #( @@ -176496,7 +176310,7 @@ module ipsxb_mcdq_com_timing_v1_2_1_unq26 GTP_LUT2 /* N31_0_2_2 */ #( .INIT(4'b1110)) N31_0_2_2 ( - .Z (_N104749), + .Z (_N105793), .I0 (timing_cnt[3]), .I1 (timing_cnt[2])); // LUT = (I0)|(I1) ; @@ -176509,7 +176323,7 @@ module ipsxb_mcdq_com_timing_v1_2_1_unq26 .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_rda ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_rda ), .I3 (timing_cnt[0]), - .I4 (_N104749)); + .I4 (_N105793)); // LUT = (I0&I1)|(I0&I2)|(I3&I4) ; GTP_LUT5 /* \N31_2[1]_1 */ #( @@ -176520,7 +176334,7 @@ module ipsxb_mcdq_com_timing_v1_2_1_unq26 .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_rda ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_rda ), .I3 (timing_cnt[1]), - .I4 (_N104749)); + .I4 (_N105793)); // LUT = (I0&I1)|(~I2&I3&I4)|(~I0&I3&I4) ; GTP_LUT5 /* \N31_2[2]_1 */ #( @@ -176551,14 +176365,14 @@ module ipsxb_mcdq_com_timing_v1_2_1_unq26 r_cnt_pass ( .Q (cnt_pass), .CLK (clk), - .D (_N103456), + .D (_N104268), .P (N5)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_com_timing_v1_2.vp:135 GTP_LUT5 /* r_cnt_pass_ce_mux */ #( .INIT(32'b01010111000000000101011101010111)) r_cnt_pass_ce_mux ( - .Z (_N103456), + .Z (_N104268), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1205 ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_rda ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_rda ), @@ -176621,8 +176435,8 @@ module ipsxb_mcdq_com_timing_v1_2_1_unq28 ); wire N25; wire [5:0] N31; - wire _N103457; - wire _N104741; + wire _N104269; + wire _N105785; wire [5:0] timing_cnt; GTP_LUT4 /* N25_mux5 */ #( @@ -176638,7 +176452,7 @@ module ipsxb_mcdq_com_timing_v1_2_1_unq28 GTP_LUT2 /* N31_0_2_2 */ #( .INIT(4'b1110)) N31_0_2_2 ( - .Z (_N104741), + .Z (_N105785), .I0 (timing_cnt[2]), .I1 (timing_cnt[3])); // LUT = (I0)|(I1) ; @@ -176651,7 +176465,7 @@ module ipsxb_mcdq_com_timing_v1_2_1_unq28 .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_rda ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_rda ), .I3 (timing_cnt[0]), - .I4 (_N104741)); + .I4 (_N105785)); // LUT = (I0&I1)|(I0&I2)|(I3&I4) ; GTP_LUT5 /* \N31_2[1]_1 */ #( @@ -176662,7 +176476,7 @@ module ipsxb_mcdq_com_timing_v1_2_1_unq28 .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_rda ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_rda ), .I3 (timing_cnt[1]), - .I4 (_N104741)); + .I4 (_N105785)); // LUT = (I0&I1)|(~I2&I3&I4)|(~I0&I3&I4) ; GTP_LUT5 /* \N31_2[2]_1 */ #( @@ -176693,14 +176507,14 @@ module ipsxb_mcdq_com_timing_v1_2_1_unq28 r_cnt_pass ( .Q (cnt_pass), .CLK (clk), - .D (_N103457), + .D (_N104269), .P (N5)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_com_timing_v1_2.vp:135 GTP_LUT5 /* r_cnt_pass_ce_mux */ #( .INIT(32'b01010111000000000101011101010111)) r_cnt_pass_ce_mux ( - .Z (_N103457), + .Z (_N104269), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1206 ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_rda ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_rda ), @@ -176754,7 +176568,6 @@ endmodule module ipsxb_mcdq_com_timing_v1_2 ( - input [42:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata , input N5, input clk, input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1199 , @@ -176765,8 +176578,8 @@ module ipsxb_mcdq_com_timing_v1_2 wire N7; wire N25; wire [6:0] N31; - wire _N103458; - wire _N104787; + wire _N104270; + wire _N105831; wire [6:0] timing_cnt; GTP_LUT5 /* N25_mux6 */ #( @@ -176783,22 +176596,20 @@ module ipsxb_mcdq_com_timing_v1_2 GTP_LUT3 /* N31_0_2_2 */ #( .INIT(8'b11111110)) N31_0_2_2 ( - .Z (_N104787), + .Z (_N105831), .I0 (timing_cnt[4]), .I1 (timing_cnt[3]), .I2 (timing_cnt[2])); // LUT = (I0)|(I1)|(I2) ; - GTP_LUT5 /* N31_0_3 */ #( - .INIT(32'b00000000000000000000000000001110)) + GTP_LUT3 /* N31_0_3 */ #( + .INIT(8'b10101000)) N31_0_3 ( .Z (N7), - .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wra ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wra ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [15] ), - .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [16] ), - .I4 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [17] )); - // LUT = (I0&~I2&~I3&~I4)|(I1&~I2&~I3&~I4) ; + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1199 ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wra ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wra )); + // LUT = (I0&I1)|(I0&I2) ; GTP_LUT5 /* \N31_2[0]_1 */ #( .INIT(32'b11111111111111111111111000000000)) @@ -176811,15 +176622,15 @@ module ipsxb_mcdq_com_timing_v1_2 .I4 (N7)); // LUT = (I4)|(I0&I3)|(I1&I3)|(I2&I3) ; - GTP_LUT5 /* \N31_2[1]_7 */ #( + GTP_LUT5 /* \N31_2[1]_6 */ #( .INIT(32'b01110111001000000010000000100000)) - \N31_2[1]_7 ( + \N31_2[1]_6 ( .Z (N31[1]), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1199 ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wra ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wra ), .I3 (timing_cnt[1]), - .I4 (_N104787)); + .I4 (_N105831)); // LUT = (I0&~I1&I2)|(~I1&I3&I4)|(~I0&I3&I4) ; GTP_LUT4 /* \N31_2[2]_1 */ #( @@ -176858,18 +176669,20 @@ module ipsxb_mcdq_com_timing_v1_2 r_cnt_pass ( .Q (cnt_pass), .CLK (clk), - .D (_N103458), + .D (_N104270), .P (N5)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_com_timing_v1_2.vp:135 - GTP_LUT3 /* r_cnt_pass_ce_mux */ #( - .INIT(8'b00100011)) + GTP_LUT5 /* r_cnt_pass_ce_mux */ #( + .INIT(32'b01010111000000000101011101010111)) r_cnt_pass_ce_mux ( - .Z (_N103458), - .I0 (cnt_pass), - .I1 (N7), - .I2 (N25)); - // LUT = (~I1&~I2)|(I0&~I1) ; + .Z (_N104270), + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1199 ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wra ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wra ), + .I3 (cnt_pass), + .I4 (N25)); + // LUT = (~I0&~I4)|(~I0&I3)|(~I1&~I2&~I4)|(~I1&~I2&I3) ; GTP_DFF_C /* \timing_cnt[0] */ #( .GRS_EN("TRUE"), @@ -176927,7 +176740,6 @@ endmodule module ipsxb_mcdq_com_timing_v1_2_unq16 ( - input [42:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata , input N5, input clk, input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1200 , @@ -176938,8 +176750,8 @@ module ipsxb_mcdq_com_timing_v1_2_unq16 wire N7; wire N25; wire [6:0] N31; - wire _N103459; - wire _N104771; + wire _N104271; + wire _N105815; wire [6:0] timing_cnt; GTP_LUT5 /* N25_mux6 */ #( @@ -176956,22 +176768,20 @@ module ipsxb_mcdq_com_timing_v1_2_unq16 GTP_LUT3 /* N31_0_2_2 */ #( .INIT(8'b11111110)) N31_0_2_2 ( - .Z (_N104771), + .Z (_N105815), .I0 (timing_cnt[4]), .I1 (timing_cnt[3]), .I2 (timing_cnt[2])); // LUT = (I0)|(I1)|(I2) ; - GTP_LUT5 /* N31_0_3 */ #( - .INIT(32'b00000000000000000000000011100000)) + GTP_LUT3 /* N31_0_3 */ #( + .INIT(8'b10101000)) N31_0_3 ( .Z (N7), - .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wra ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wra ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [15] ), - .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [16] ), - .I4 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [17] )); - // LUT = (I0&I2&~I3&~I4)|(I1&I2&~I3&~I4) ; + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1200 ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wra ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wra )); + // LUT = (I0&I1)|(I0&I2) ; GTP_LUT5 /* \N31_2[0]_1 */ #( .INIT(32'b11111111111111111111111000000000)) @@ -176992,7 +176802,7 @@ module ipsxb_mcdq_com_timing_v1_2_unq16 .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wra ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wra ), .I3 (timing_cnt[1]), - .I4 (_N104771)); + .I4 (_N105815)); // LUT = (I0&~I1&I2)|(~I1&I3&I4)|(~I0&I3&I4) ; GTP_LUT4 /* \N31_2[2]_1 */ #( @@ -177031,18 +176841,20 @@ module ipsxb_mcdq_com_timing_v1_2_unq16 r_cnt_pass ( .Q (cnt_pass), .CLK (clk), - .D (_N103459), + .D (_N104271), .P (N5)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_com_timing_v1_2.vp:135 - GTP_LUT3 /* r_cnt_pass_ce_mux */ #( - .INIT(8'b00100011)) + GTP_LUT5 /* r_cnt_pass_ce_mux */ #( + .INIT(32'b01010111000000000101011101010111)) r_cnt_pass_ce_mux ( - .Z (_N103459), - .I0 (cnt_pass), - .I1 (N7), - .I2 (N25)); - // LUT = (~I1&~I2)|(I0&~I1) ; + .Z (_N104271), + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1200 ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wra ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wra ), + .I3 (cnt_pass), + .I4 (N25)); + // LUT = (~I0&~I4)|(~I0&I3)|(~I1&~I2&~I4)|(~I1&~I2&I3) ; GTP_DFF_C /* \timing_cnt[0] */ #( .GRS_EN("TRUE"), @@ -177100,7 +176912,6 @@ endmodule module ipsxb_mcdq_com_timing_v1_2_unq18 ( - input [42:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata , input N5, input clk, input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1201 , @@ -177111,8 +176922,8 @@ module ipsxb_mcdq_com_timing_v1_2_unq18 wire N7; wire N25; wire [6:0] N31; - wire _N103460; - wire _N104779; + wire _N104272; + wire _N105823; wire [6:0] timing_cnt; GTP_LUT5 /* N25_mux6 */ #( @@ -177126,21 +176937,19 @@ module ipsxb_mcdq_com_timing_v1_2_unq18 .I4 (timing_cnt[0])); // LUT = (I0)|(I1)|(I2&I3)|(I2&I4) ; - GTP_LUT5 /* N25_mux6_1 */ #( - .INIT(32'b00000000000000000000111000000000)) + GTP_LUT3 /* N25_mux6_1 */ #( + .INIT(8'b10101000)) N25_mux6_1 ( .Z (N7), - .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wra ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wra ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [15] ), - .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [16] ), - .I4 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [17] )); - // LUT = (I0&~I2&I3&~I4)|(I1&~I2&I3&~I4) ; + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1201 ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wra ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wra )); + // LUT = (I0&I1)|(I0&I2) ; GTP_LUT3 /* N31_0_2_2 */ #( .INIT(8'b11111110)) N31_0_2_2 ( - .Z (_N104779), + .Z (_N105823), .I0 (timing_cnt[4]), .I1 (timing_cnt[3]), .I2 (timing_cnt[2])); @@ -177165,7 +176974,7 @@ module ipsxb_mcdq_com_timing_v1_2_unq18 .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wra ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wra ), .I3 (timing_cnt[1]), - .I4 (_N104779)); + .I4 (_N105823)); // LUT = (I0&~I1&I2)|(~I1&I3&I4)|(~I0&I3&I4) ; GTP_LUT4 /* \N31_2[2]_1 */ #( @@ -177204,18 +177013,20 @@ module ipsxb_mcdq_com_timing_v1_2_unq18 r_cnt_pass ( .Q (cnt_pass), .CLK (clk), - .D (_N103460), + .D (_N104272), .P (N5)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_com_timing_v1_2.vp:135 - GTP_LUT3 /* r_cnt_pass_ce_mux */ #( - .INIT(8'b00100011)) + GTP_LUT5 /* r_cnt_pass_ce_mux */ #( + .INIT(32'b01010111000000000101011101010111)) r_cnt_pass_ce_mux ( - .Z (_N103460), - .I0 (cnt_pass), - .I1 (N7), - .I2 (N25)); - // LUT = (~I1&~I2)|(I0&~I1) ; + .Z (_N104272), + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1201 ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wra ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wra ), + .I3 (cnt_pass), + .I4 (N25)); + // LUT = (~I0&~I4)|(~I0&I3)|(~I1&~I2&~I4)|(~I1&~I2&I3) ; GTP_DFF_C /* \timing_cnt[0] */ #( .GRS_EN("TRUE"), @@ -177273,7 +177084,6 @@ endmodule module ipsxb_mcdq_com_timing_v1_2_unq20 ( - input [42:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata , input N5, input clk, input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1202 , @@ -177284,8 +177094,8 @@ module ipsxb_mcdq_com_timing_v1_2_unq20 wire N7; wire N25; wire [6:0] N31; - wire _N103461; - wire _N104763; + wire _N104273; + wire _N105807; wire [6:0] timing_cnt; GTP_LUT5 /* N25_mux6 */ #( @@ -177302,22 +177112,20 @@ module ipsxb_mcdq_com_timing_v1_2_unq20 GTP_LUT3 /* N31_0_2_2 */ #( .INIT(8'b11111110)) N31_0_2_2 ( - .Z (_N104763), + .Z (_N105807), .I0 (timing_cnt[4]), .I1 (timing_cnt[3]), .I2 (timing_cnt[2])); // LUT = (I0)|(I1)|(I2) ; - GTP_LUT5 /* N31_0_3 */ #( - .INIT(32'b00000000000000001110000000000000)) + GTP_LUT3 /* N31_0_3 */ #( + .INIT(8'b10101000)) N31_0_3 ( .Z (N7), - .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wra ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wra ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [15] ), - .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [16] ), - .I4 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [17] )); - // LUT = (I0&I2&I3&~I4)|(I1&I2&I3&~I4) ; + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1202 ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wra ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wra )); + // LUT = (I0&I1)|(I0&I2) ; GTP_LUT5 /* \N31_2[0]_1 */ #( .INIT(32'b11111111111111111111111000000000)) @@ -177338,7 +177146,7 @@ module ipsxb_mcdq_com_timing_v1_2_unq20 .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wra ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wra ), .I3 (timing_cnt[1]), - .I4 (_N104763)); + .I4 (_N105807)); // LUT = (I0&~I1&I2)|(~I1&I3&I4)|(~I0&I3&I4) ; GTP_LUT4 /* \N31_2[2]_1 */ #( @@ -177377,18 +177185,20 @@ module ipsxb_mcdq_com_timing_v1_2_unq20 r_cnt_pass ( .Q (cnt_pass), .CLK (clk), - .D (_N103461), + .D (_N104273), .P (N5)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_com_timing_v1_2.vp:135 - GTP_LUT3 /* r_cnt_pass_ce_mux */ #( - .INIT(8'b00100011)) + GTP_LUT5 /* r_cnt_pass_ce_mux */ #( + .INIT(32'b01010111000000000101011101010111)) r_cnt_pass_ce_mux ( - .Z (_N103461), - .I0 (cnt_pass), - .I1 (N7), - .I2 (N25)); - // LUT = (~I1&~I2)|(I0&~I1) ; + .Z (_N104273), + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1202 ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wra ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wra ), + .I3 (cnt_pass), + .I4 (N25)); + // LUT = (~I0&~I4)|(~I0&I3)|(~I1&~I2&~I4)|(~I1&~I2&I3) ; GTP_DFF_C /* \timing_cnt[0] */ #( .GRS_EN("TRUE"), @@ -177446,7 +177256,6 @@ endmodule module ipsxb_mcdq_com_timing_v1_2_unq22 ( - input [42:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata , input N5, input clk, input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1203 , @@ -177457,8 +177266,8 @@ module ipsxb_mcdq_com_timing_v1_2_unq22 wire N7; wire N25; wire [6:0] N31; - wire _N103462; - wire _N104783; + wire _N104274; + wire _N105827; wire [6:0] timing_cnt; GTP_LUT5 /* N25_mux6 */ #( @@ -177472,26 +177281,24 @@ module ipsxb_mcdq_com_timing_v1_2_unq22 .I4 (timing_cnt[0])); // LUT = (I0)|(I1)|(I2&I3)|(I2&I4) ; - GTP_LUT5 /* N25_mux6_1 */ #( - .INIT(32'b00000000000011100000000000000000)) - N25_mux6_1 ( - .Z (N7), - .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wra ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wra ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [15] ), - .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [16] ), - .I4 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [17] )); - // LUT = (I0&~I2&~I3&I4)|(I1&~I2&~I3&I4) ; - GTP_LUT3 /* N31_0_2_2 */ #( .INIT(8'b11111110)) N31_0_2_2 ( - .Z (_N104783), + .Z (_N105827), .I0 (timing_cnt[4]), .I1 (timing_cnt[3]), .I2 (timing_cnt[2])); // LUT = (I0)|(I1)|(I2) ; + GTP_LUT3 /* N31_0_3 */ #( + .INIT(8'b10101000)) + N31_0_3 ( + .Z (N7), + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1203 ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wra ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wra )); + // LUT = (I0&I1)|(I0&I2) ; + GTP_LUT5 /* \N31_2[0]_1 */ #( .INIT(32'b11111111111111111111111000000000)) \N31_2[0]_1 ( @@ -177511,7 +177318,7 @@ module ipsxb_mcdq_com_timing_v1_2_unq22 .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wra ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wra ), .I3 (timing_cnt[1]), - .I4 (_N104783)); + .I4 (_N105827)); // LUT = (I0&~I1&I2)|(~I1&I3&I4)|(~I0&I3&I4) ; GTP_LUT4 /* \N31_2[2]_1 */ #( @@ -177550,18 +177357,20 @@ module ipsxb_mcdq_com_timing_v1_2_unq22 r_cnt_pass ( .Q (cnt_pass), .CLK (clk), - .D (_N103462), + .D (_N104274), .P (N5)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_com_timing_v1_2.vp:135 - GTP_LUT3 /* r_cnt_pass_ce_mux */ #( - .INIT(8'b00100011)) + GTP_LUT5 /* r_cnt_pass_ce_mux */ #( + .INIT(32'b01010111000000000101011101010111)) r_cnt_pass_ce_mux ( - .Z (_N103462), - .I0 (cnt_pass), - .I1 (N7), - .I2 (N25)); - // LUT = (~I1&~I2)|(I0&~I1) ; + .Z (_N104274), + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1203 ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wra ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wra ), + .I3 (cnt_pass), + .I4 (N25)); + // LUT = (~I0&~I4)|(~I0&I3)|(~I1&~I2&~I4)|(~I1&~I2&I3) ; GTP_DFF_C /* \timing_cnt[0] */ #( .GRS_EN("TRUE"), @@ -177619,7 +177428,6 @@ endmodule module ipsxb_mcdq_com_timing_v1_2_unq24 ( - input [42:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata , input N5, input clk, input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1204 , @@ -177630,8 +177438,8 @@ module ipsxb_mcdq_com_timing_v1_2_unq24 wire N7; wire N25; wire [6:0] N31; - wire _N103463; - wire _N104767; + wire _N104275; + wire _N105811; wire [6:0] timing_cnt; GTP_LUT5 /* N25_mux6 */ #( @@ -177648,22 +177456,20 @@ module ipsxb_mcdq_com_timing_v1_2_unq24 GTP_LUT3 /* N31_0_2_2 */ #( .INIT(8'b11111110)) N31_0_2_2 ( - .Z (_N104767), + .Z (_N105811), .I0 (timing_cnt[4]), .I1 (timing_cnt[3]), .I2 (timing_cnt[2])); // LUT = (I0)|(I1)|(I2) ; - GTP_LUT5 /* N31_0_3 */ #( - .INIT(32'b00000000111000000000000000000000)) + GTP_LUT3 /* N31_0_3 */ #( + .INIT(8'b10101000)) N31_0_3 ( .Z (N7), - .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wra ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wra ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [15] ), - .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [16] ), - .I4 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [17] )); - // LUT = (I0&I2&~I3&I4)|(I1&I2&~I3&I4) ; + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1204 ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wra ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wra )); + // LUT = (I0&I1)|(I0&I2) ; GTP_LUT5 /* \N31_2[0]_1 */ #( .INIT(32'b11111111111111111111111000000000)) @@ -177684,7 +177490,7 @@ module ipsxb_mcdq_com_timing_v1_2_unq24 .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wra ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wra ), .I3 (timing_cnt[1]), - .I4 (_N104767)); + .I4 (_N105811)); // LUT = (I0&~I1&I2)|(~I1&I3&I4)|(~I0&I3&I4) ; GTP_LUT4 /* \N31_2[2]_1 */ #( @@ -177723,18 +177529,20 @@ module ipsxb_mcdq_com_timing_v1_2_unq24 r_cnt_pass ( .Q (cnt_pass), .CLK (clk), - .D (_N103463), + .D (_N104275), .P (N5)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_com_timing_v1_2.vp:135 - GTP_LUT3 /* r_cnt_pass_ce_mux */ #( - .INIT(8'b00100011)) + GTP_LUT5 /* r_cnt_pass_ce_mux */ #( + .INIT(32'b01010111000000000101011101010111)) r_cnt_pass_ce_mux ( - .Z (_N103463), - .I0 (cnt_pass), - .I1 (N7), - .I2 (N25)); - // LUT = (~I1&~I2)|(I0&~I1) ; + .Z (_N104275), + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1204 ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wra ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wra ), + .I3 (cnt_pass), + .I4 (N25)); + // LUT = (~I0&~I4)|(~I0&I3)|(~I1&~I2&~I4)|(~I1&~I2&I3) ; GTP_DFF_C /* \timing_cnt[0] */ #( .GRS_EN("TRUE"), @@ -177792,7 +177600,6 @@ endmodule module ipsxb_mcdq_com_timing_v1_2_unq26 ( - input [42:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata , input N5, input clk, input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1205 , @@ -177803,8 +177610,8 @@ module ipsxb_mcdq_com_timing_v1_2_unq26 wire N7; wire N25; wire [6:0] N31; - wire _N103464; - wire _N104775; + wire _N104276; + wire _N105819; wire [6:0] timing_cnt; GTP_LUT5 /* N25_mux6 */ #( @@ -177818,21 +177625,19 @@ module ipsxb_mcdq_com_timing_v1_2_unq26 .I4 (timing_cnt[0])); // LUT = (I0)|(I1)|(I2&I3)|(I2&I4) ; - GTP_LUT5 /* N25_mux6_1 */ #( - .INIT(32'b00001110000000000000000000000000)) + GTP_LUT3 /* N25_mux6_1 */ #( + .INIT(8'b10101000)) N25_mux6_1 ( .Z (N7), - .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wra ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wra ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [15] ), - .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [16] ), - .I4 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [17] )); - // LUT = (I0&~I2&I3&I4)|(I1&~I2&I3&I4) ; + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1205 ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wra ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wra )); + // LUT = (I0&I1)|(I0&I2) ; GTP_LUT3 /* N31_0_2_2 */ #( .INIT(8'b11111110)) N31_0_2_2 ( - .Z (_N104775), + .Z (_N105819), .I0 (timing_cnt[4]), .I1 (timing_cnt[3]), .I2 (timing_cnt[2])); @@ -177857,7 +177662,7 @@ module ipsxb_mcdq_com_timing_v1_2_unq26 .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wra ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wra ), .I3 (timing_cnt[1]), - .I4 (_N104775)); + .I4 (_N105819)); // LUT = (I0&~I1&I2)|(~I1&I3&I4)|(~I0&I3&I4) ; GTP_LUT4 /* \N31_2[2]_1 */ #( @@ -177896,18 +177701,20 @@ module ipsxb_mcdq_com_timing_v1_2_unq26 r_cnt_pass ( .Q (cnt_pass), .CLK (clk), - .D (_N103464), + .D (_N104276), .P (N5)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_com_timing_v1_2.vp:135 - GTP_LUT3 /* r_cnt_pass_ce_mux */ #( - .INIT(8'b00100011)) + GTP_LUT5 /* r_cnt_pass_ce_mux */ #( + .INIT(32'b01010111000000000101011101010111)) r_cnt_pass_ce_mux ( - .Z (_N103464), - .I0 (cnt_pass), - .I1 (N7), - .I2 (N25)); - // LUT = (~I1&~I2)|(I0&~I1) ; + .Z (_N104276), + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1205 ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wra ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wra ), + .I3 (cnt_pass), + .I4 (N25)); + // LUT = (~I0&~I4)|(~I0&I3)|(~I1&~I2&~I4)|(~I1&~I2&I3) ; GTP_DFF_C /* \timing_cnt[0] */ #( .GRS_EN("TRUE"), @@ -177965,7 +177772,6 @@ endmodule module ipsxb_mcdq_com_timing_v1_2_unq28 ( - input [42:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata , input N5, input clk, input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1206 , @@ -177976,8 +177782,8 @@ module ipsxb_mcdq_com_timing_v1_2_unq28 wire N7; wire N25; wire [6:0] N31; - wire _N103465; - wire _N104757; + wire _N104277; + wire _N105801; wire [6:0] timing_cnt; GTP_LUT5 /* N25_mux6 */ #( @@ -177994,22 +177800,20 @@ module ipsxb_mcdq_com_timing_v1_2_unq28 GTP_LUT3 /* N31_0_2_2 */ #( .INIT(8'b11111110)) N31_0_2_2 ( - .Z (_N104757), + .Z (_N105801), .I0 (timing_cnt[2]), .I1 (timing_cnt[3]), .I2 (timing_cnt[4])); // LUT = (I0)|(I1)|(I2) ; - GTP_LUT5 /* N31_0_3 */ #( - .INIT(32'b11100000000000000000000000000000)) + GTP_LUT3 /* N31_0_3 */ #( + .INIT(8'b10101000)) N31_0_3 ( .Z (N7), - .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wra ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wra ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [15] ), - .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [16] ), - .I4 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [17] )); - // LUT = (I0&I2&I3&I4)|(I1&I2&I3&I4) ; + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1206 ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wra ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wra )); + // LUT = (I0&I1)|(I0&I2) ; GTP_LUT5 /* \N31_2[0]_1 */ #( .INIT(32'b11101110111011101110111011101010)) @@ -178030,7 +177834,7 @@ module ipsxb_mcdq_com_timing_v1_2_unq28 .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wra ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wra ), .I3 (timing_cnt[1]), - .I4 (_N104757)); + .I4 (_N105801)); // LUT = (I0&~I1&I2)|(~I1&I3&I4)|(~I0&I3&I4) ; GTP_LUT4 /* \N31_2[2]_1 */ #( @@ -178069,18 +177873,20 @@ module ipsxb_mcdq_com_timing_v1_2_unq28 r_cnt_pass ( .Q (cnt_pass), .CLK (clk), - .D (_N103465), + .D (_N104277), .P (N5)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_com_timing_v1_2.vp:135 - GTP_LUT3 /* r_cnt_pass_ce_mux */ #( - .INIT(8'b00100011)) + GTP_LUT5 /* r_cnt_pass_ce_mux */ #( + .INIT(32'b01010111000000000101011101010111)) r_cnt_pass_ce_mux ( - .Z (_N103465), - .I0 (cnt_pass), - .I1 (N7), - .I2 (N25)); - // LUT = (~I1&~I2)|(I0&~I1) ; + .Z (_N104277), + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N1206 ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_wra ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_m_wra ), + .I3 (cnt_pass), + .I4 (N25)); + // LUT = (~I0&~I4)|(~I0&I3)|(~I1&~I2&~I4)|(~I1&~I2&I3) ; GTP_DFF_C /* \timing_cnt[0] */ #( .GRS_EN("TRUE"), @@ -178144,21 +177950,21 @@ module ipsxb_mcdq_timing_rd_pass_v1_2 input clk, input cmd_rd_l, input cmd_rd_m, + input cmd_wr, input cmd_wr_l, input cmd_wr_m, input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N210 , - output _N96772, + output _N97564, output cmd_rd_pass, output cmd_rd_pass_l, - output cmd_rd_pass_m, - output cmd_wr + output cmd_rd_pass_m ); wire N27; wire N97; wire N104; wire N106; wire [6:0] N110; - wire _N103466; + wire _N104278; wire [6:0] timing_cnt1; GTP_LUT4 /* N27_mux6 */ #( @@ -178171,14 +177977,6 @@ module ipsxb_mcdq_timing_rd_pass_v1_2 .I3 (timing_cnt1[3])); // LUT = (I3)|(I0&I2)|(I1&I2) ; - GTP_LUT2 /* N27_mux6_1 */ #( - .INIT(4'b1110)) - N27_mux6_1 ( - .Z (cmd_wr), - .I0 (cmd_wr_l), - .I1 (cmd_wr_m)); - // LUT = (I0)|(I1) ; - GTP_LUT5M /* N97 */ #( .INIT(32'b10001000100010001111111100000101)) N97_vname ( @@ -178225,9 +178023,9 @@ module ipsxb_mcdq_timing_rd_pass_v1_2 .I4 (timing_cnt1[3])); // LUT = (I0)|(I1)|(I2&I3)|(I2&I4) ; - GTP_LUT5 /* \N110_2[1]_6 */ #( + GTP_LUT5 /* \N110_2[1]_7 */ #( .INIT(32'b01010100010101000101010001000100)) - \N110_2[1]_6 ( + \N110_2[1]_7 ( .Z (N110[1]), .I0 (cmd_wr_l), .I1 (cmd_wr_m), @@ -178259,7 +178057,7 @@ module ipsxb_mcdq_timing_rd_pass_v1_2 GTP_LUT2 /* \N110_9[2]_1 */ #( .INIT(4'b1110)) \N110_9[2]_1 ( - .Z (_N96772), + .Z (_N97564), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1 [3] ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1 [4] )); // LUT = (I0)|(I1) ; @@ -178271,14 +178069,14 @@ module ipsxb_mcdq_timing_rd_pass_v1_2 .Q (cmd_rd_pass), .C (N12), .CLK (clk), - .D (_N103466)); + .D (_N104278)); // defparam cmd_rd_pass_vname.orig_name = cmd_rd_pass; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_timing_rd_pass_v1_2.vp:231 GTP_LUT5M /* cmd_rd_pass_ce_mux */ #( .INIT(32'b10101010101010101101110111001101)) cmd_rd_pass_ce_mux ( - .Z (_N103466), + .Z (_N104278), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N210 ), .I1 (cmd_rd_l), .I2 (N27), @@ -178363,7 +178161,7 @@ module ipsxb_mcdq_tfaw_v1_2 wire N12; wire N19; wire [4:0] N20; - wire _N103438; + wire _N104250; wire [4:0] timing_cnt; GTP_LUT4 /* N12_mux4 */ #( @@ -178376,9 +178174,9 @@ module ipsxb_mcdq_tfaw_v1_2 .I3 (timing_cnt[1])); // LUT = (I0)|(I1)|(I2&I3) ; - GTP_LUT5 /* N19_3 */ #( + GTP_LUT5 /* N19_5 */ #( .INIT(32'b11111111111111111111111111111000)) - N19_3 ( + N19_5 ( .Z (N19), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_act ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/N52 [0] ), @@ -178439,7 +178237,7 @@ module ipsxb_mcdq_tfaw_v1_2 r_cnt_pass_vname ( .Q (r_cnt_pass), .CLK (clk), - .D (_N103438), + .D (_N104250), .P (N0)); // defparam r_cnt_pass_vname.orig_name = r_cnt_pass; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_tfaw_v1_2.vp:94 @@ -178447,7 +178245,7 @@ module ipsxb_mcdq_tfaw_v1_2 GTP_LUT5 /* r_cnt_pass_ce_mux */ #( .INIT(32'b11111101111111010000000011111101)) r_cnt_pass_ce_mux ( - .Z (_N103438), + .Z (_N104250), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_act ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/cnt [0] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/cnt [1] ), @@ -178515,7 +178313,7 @@ module ipsxb_mcdq_tfaw_v1_2_unq6 wire N12; wire N19; wire [4:0] N20; - wire _N103439; + wire _N104251; wire [4:0] timing_cnt; GTP_LUT4 /* N12_mux4 */ #( @@ -178591,7 +178389,7 @@ module ipsxb_mcdq_tfaw_v1_2_unq6 r_cnt_pass_vname ( .Q (r_cnt_pass), .CLK (clk), - .D (_N103439), + .D (_N104251), .P (N0)); // defparam r_cnt_pass_vname.orig_name = r_cnt_pass; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_tfaw_v1_2.vp:94 @@ -178599,7 +178397,7 @@ module ipsxb_mcdq_tfaw_v1_2_unq6 GTP_LUT5 /* r_cnt_pass_ce_mux */ #( .INIT(32'b11110111111101110000000011110111)) r_cnt_pass_ce_mux ( - .Z (_N103439), + .Z (_N104251), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_act ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/cnt [0] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/cnt [1] ), @@ -178667,7 +178465,7 @@ module ipsxb_mcdq_tfaw_v1_2_unq8 wire N12; wire N19; wire [4:0] N20; - wire _N103440; + wire _N104252; wire [4:0] timing_cnt; GTP_LUT4 /* N12_mux4 */ #( @@ -178680,9 +178478,9 @@ module ipsxb_mcdq_tfaw_v1_2_unq8 .I3 (timing_cnt[4])); // LUT = (I2)|(I3)|(I0&I1) ; - GTP_LUT4 /* N19_3 */ #( + GTP_LUT4 /* N19_5 */ #( .INIT(16'b1111111111111110)) - N19_3 ( + N19_5 ( .Z (N19), .I0 (restart), .I1 (timing_cnt[2]), @@ -178741,7 +178539,7 @@ module ipsxb_mcdq_tfaw_v1_2_unq8 r_cnt_pass_vname ( .Q (r_cnt_pass), .CLK (clk), - .D (_N103440), + .D (_N104252), .P (N0)); // defparam r_cnt_pass_vname.orig_name = r_cnt_pass; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_tfaw_v1_2.vp:94 @@ -178749,7 +178547,7 @@ module ipsxb_mcdq_tfaw_v1_2_unq8 GTP_LUT5 /* r_cnt_pass_ce_mux */ #( .INIT(32'b11011111110111110000000011011111)) r_cnt_pass_ce_mux ( - .Z (_N103440), + .Z (_N104252), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_act ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/cnt [0] ), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/cnt [1] ), @@ -178818,7 +178616,7 @@ module ipsxb_mcdq_tfaw_timing_v1_2 wire \TFAW_LOOP[0].mcdq_tfaw/r_cnt_pass ; wire \TFAW_LOOP[1].mcdq_tfaw/r_cnt_pass ; wire \TFAW_LOOP[2].mcdq_tfaw/r_cnt_pass ; - wire _N104805; + wire _N105849; wire [2:0] start; GTP_LUT3 /* \N35[2]_3 */ #( @@ -178833,7 +178631,7 @@ module ipsxb_mcdq_tfaw_timing_v1_2 GTP_LUT5 /* N43_2 */ #( .INIT(32'b11111111111101111111110100000000)) N43_2 ( - .Z (_N104805), + .Z (_N105849), .I0 (restart), .I1 (cnt[0]), .I2 (cnt[1]), @@ -178849,7 +178647,7 @@ module ipsxb_mcdq_tfaw_timing_v1_2 .I1 (cnt[0]), .I2 (cnt[1]), .I3 (\TFAW_LOOP[2].mcdq_tfaw/r_cnt_pass ), - .I4 (_N104805)); + .I4 (_N105849)); // LUT = (I4)|(~I2&I3)|(~I0&I3)|(I1&I3) ; ipsxb_mcdq_tfaw_v1_2 \TFAW_LOOP[0].mcdq_tfaw ( @@ -178920,9 +178718,9 @@ module ipsxb_mcdq_timing_act_pass_v1_2 ( input [42:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata , input N6, - input _N96417, - input _N96417_cpy, - input _N104834, + input _N97179, + input _N97179_cpy, + input _N105852, input clk, input cmd_pre_l, input cmd_ref, @@ -178934,20 +178732,20 @@ module ipsxb_mcdq_timing_act_pass_v1_2 wire N31; wire [7:0] \N31.co ; wire N45; - wire N47; wire N71; wire [6:0] N77; wire _N3; - wire _N6430; - wire _N15659; - wire _N17324; - wire _N17326; - wire _N25124; - wire _N25139; - wire _N96430; - wire _N103199_2; - wire _N104968; - wire _N104973; + wire _N6513; + wire _N15350; + wire _N17302; + wire _N17304; + wire _N24930; + wire _N24945; + wire _N97061; + wire _N97072; + wire _N103967_2; + wire _N105986; + wire _N105991; wire cmd_pre; wire [6:0] timing_cnt; wire [6:0] w_cnt_init0; @@ -178958,7 +178756,7 @@ module ipsxb_mcdq_timing_act_pass_v1_2 .Z (cmd_pre), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/cmd_pre_pass_m ), .I1 (cmd_pre_l), - .I2 (_N96417_cpy)); + .I2 (_N97179_cpy)); // LUT = (I1)|(I0&I2) ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_timing_act_pass_v1_2.vp:118 @@ -178968,14 +178766,14 @@ module ipsxb_mcdq_timing_act_pass_v1_2 .Z (w_cnt_init0[3]), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/cmd_pre_pass_l ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/cmd_pre_pass_m ), - .I2 (_N96417)); + .I2 (_N97179)); // LUT = ~I0&I1&I2 ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_timing_act_pass_v1_2.vp:119 GTP_LUT4 /* N8_mux3 */ #( .INIT(16'b1111111000000000)) N8_mux3 ( - .Z (_N6430), + .Z (_N6513), .I0 (timing_cnt[0]), .I1 (timing_cnt[1]), .I2 (timing_cnt[2]), @@ -178995,7 +178793,7 @@ module ipsxb_mcdq_timing_act_pass_v1_2 .I0 (timing_cnt[0]), .I1 (timing_cnt[1]), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/cmd_pre_pass_l ), - .I3 (_N96417_cpy), + .I3 (_N97179_cpy), .I4 (), .ID ()); // LUT = (I1&~I3)|(I0&~I3)|(I1&~I2)|(I0&~I2)|(I0&I1) ; @@ -179065,7 +178863,7 @@ module ipsxb_mcdq_timing_act_pass_v1_2 GTP_LUT3 /* N38_mux6_3 */ #( .INIT(8'b10000000)) N38_mux6_3 ( - .Z (_N104968), + .Z (_N105986), .I0 (timing_cnt[4]), .I1 (timing_cnt[5]), .I2 (timing_cnt[6])); @@ -179082,45 +178880,22 @@ module ipsxb_mcdq_timing_act_pass_v1_2 .I4 (timing_cnt[6])); // LUT = (I2&I4)|(I3&I4)|(I0&I1&I4) ; - GTP_LUT4 /* N47 */ #( - .INIT(16'b0000100000000000)) - N47_vname ( - .Z (N47), - .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [3] ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [4] ), - .I2 (N45), - .I3 (_N104834)); - // defparam N47_vname.orig_name = N47; - // LUT = I0&I1&~I2&I3 ; - // ../ipcore/axi_ddr/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_timing_act_pass_v1_2.vp:146 - GTP_LUT5 /* N71 */ #( .INIT(32'b00000000000000010000000000000000)) N71_vname ( .Z (N71), - .I0 (_N6430), + .I0 (_N6513), .I1 (timing_cnt[4]), .I2 (timing_cnt[5]), .I3 (timing_cnt[6]), - .I4 (_N96430)); + .I4 (_N97072)); // defparam N71_vname.orig_name = N71; // LUT = ~I0&~I1&~I2&~I3&I4 ; - GTP_LUT5 /* N71_1 */ #( - .INIT(32'b11111101011111111111111111111111)) - N71_1 ( - .Z (_N96430), - .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N221 ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [1] ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [2] ), - .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [3] ), - .I4 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [4] )); - // LUT = (~I4)|(~I0)|(~I2&~I3)|(~I1&I2)|(I1&I3) ; - GTP_LUT5 /* N77_0_8 */ #( .INIT(32'b00000000000000000000000000000001)) N77_0_8 ( - .Z (_N104973), + .Z (_N105991), .I0 (timing_cnt[2]), .I1 (timing_cnt[3]), .I2 (timing_cnt[4]), @@ -179134,16 +178909,16 @@ module ipsxb_mcdq_timing_act_pass_v1_2 .Z (_N3), .I0 (N31), .I1 (cmd_pre), - .I2 (_N96430), - .I3 (_N104973)); + .I2 (_N97072), + .I3 (_N105991)); // LUT = (~I1&I2&I3)|(I0&I2&I3) ; GTP_LUT4 /* \N77_2[0]_1 */ #( .INIT(16'b0000000010011000)) \N77_2[0]_1 ( .Z (N77[0]), - .I0 (_N25124), - .I1 (_N25139), + .I0 (_N24930), + .I1 (_N24945), .I2 (timing_cnt[0]), .I3 (_N3)); // LUT = (I0&I1&~I3)|(~I0&~I1&I2&~I3) ; @@ -179152,8 +178927,8 @@ module ipsxb_mcdq_timing_act_pass_v1_2 .INIT(32'b00000000000000001011100110101000)) \N77_2[1]_1 ( .Z (N77[1]), - .I0 (_N25124), - .I1 (_N25139), + .I0 (_N24930), + .I1 (_N24945), .I2 (cmd_pre_l), .I3 (timing_cnt[1]), .I4 (_N3)); @@ -179163,8 +178938,8 @@ module ipsxb_mcdq_timing_act_pass_v1_2 .INIT(32'b00000000000000000100111001011111)) \N77_2[2]_1 ( .Z (N77[2]), - .I0 (_N25124), - .I1 (_N25139), + .I0 (_N24930), + .I1 (_N24945), .I2 (cmd_pre_l), .I3 (timing_cnt[2]), .I4 (_N3)); @@ -179175,10 +178950,10 @@ module ipsxb_mcdq_timing_act_pass_v1_2 \N77_2[3]_1 ( .Z (N77[3]), .I0 (cmd_pre_l), - .I1 (_N25139), + .I1 (_N24945), .I2 (_N3), - .I3 (_N103199_2), - .I4 (_N25124), + .I3 (_N103967_2), + .I4 (_N24930), .ID (timing_cnt[2])); // LUT = (~ID&~I1&~I2&~I3&~I4)|(ID&~I1&~I2&I3&~I4)|(~I0&~I1&~I2&~I3&I4)|(I0&~I2&I3&I4)|(I0&I1&~I2&I4) ; @@ -179186,7 +178961,7 @@ module ipsxb_mcdq_timing_act_pass_v1_2 .INIT(4'b0001)) \N77_2[4]_1 ( .Z (N77[4]), - .I0 (_N17324), + .I0 (_N17302), .I1 (_N3)); // LUT = ~I0&~I1 ; @@ -179194,9 +178969,9 @@ module ipsxb_mcdq_timing_act_pass_v1_2 .INIT(32'b00000000000000000110011001100101)) \N77_2[5]_1 ( .Z (N77[5]), - .I0 (_N15659), - .I1 (_N25124), - .I2 (_N25139), + .I0 (_N15350), + .I1 (_N24930), + .I2 (_N24945), .I3 (timing_cnt[5]), .I4 (_N3)); // LUT = (~I0&I1&~I4)|(~I0&~I2&~I3&~I4)|(I0&~I1&I2&~I4)|(I0&~I1&I3&~I4) ; @@ -179205,41 +178980,41 @@ module ipsxb_mcdq_timing_act_pass_v1_2 .INIT(4'b0001)) \N77_2[6]_1 ( .Z (N77[6]), - .I0 (_N17326), + .I0 (_N17304), .I1 (_N3)); // LUT = ~I0&~I1 ; GTP_LUT5M /* N77_8_maj1_1 */ #( .INIT(32'b11111111111011101111111111111110)) N77_8_maj1_1 ( - .Z (_N15659), + .Z (_N15350), .I0 (cmd_pre_l), - .I1 (_N25139), + .I1 (_N24945), .I2 (timing_cnt[4]), - .I3 (_N103199_2), - .I4 (_N25124), + .I3 (_N103967_2), + .I4 (_N24930), .ID (timing_cnt[2])); // LUT = (I2&~I4)|(ID&~I4)|(I0&I4)|(I3)|(I1) ; GTP_LUT5M /* N77_8_sum1 */ #( .INIT(32'b11111111111011100000001100010010)) N77_8_sum1 ( - .Z (_N17324), + .Z (_N17302), .I0 (cmd_pre_l), - .I1 (_N25139), + .I1 (_N24945), .I2 (timing_cnt[4]), - .I3 (_N103199_2), - .I4 (_N25124), + .I3 (_N103967_2), + .I4 (_N24930), .ID (timing_cnt[2])); // LUT = (~ID&~I1&I2&~I3&~I4)|(ID&~I1&~I2&~I4)|(I3&I4)|(I1&I4)|(I0&I4)|(~I1&~I2&I3) ; GTP_LUT5 /* N77_8_sum3_6 */ #( .INIT(32'b01001000010010010100101101001010)) N77_8_sum3_6 ( - .Z (_N17326), - .I0 (_N15659), - .I1 (_N25124), - .I2 (_N25139), + .Z (_N17304), + .I0 (_N15350), + .I1 (_N24930), + .I2 (_N24945), .I3 (timing_cnt[5]), .I4 (timing_cnt[6])); // LUT = (I0&~I2&~I4)|(I0&I1&~I2)|(~I0&I1&I2)|(~I1&~I2&I3&~I4)|(~I0&~I1&~I2&~I3&I4) ; @@ -179247,33 +179022,54 @@ module ipsxb_mcdq_timing_act_pass_v1_2 GTP_LUT4 /* N77_47_1 */ #( .INIT(16'b1111010011111100)) N77_47_1 ( - .Z (_N25139), - .I0 (_N6430), + .Z (_N24945), + .I0 (_N6513), .I1 (cmd_ref), - .I2 (N47), - .I3 (_N104968)); + .I2 (_N97061), + .I3 (_N105986)); // LUT = (I2)|(I1&~I3)|(~I0&I1) ; GTP_LUT3 /* \N77_50[3]_2 */ #( .INIT(8'b11100100)) \N77_50[3]_2 ( - .Z (_N103199_2), - .I0 (_N25124), + .Z (_N103967_2), + .I0 (_N24930), .I1 (timing_cnt[3]), .I2 (w_cnt_init0[3])); // LUT = (~I0&I1)|(I0&I2) ; - GTP_LUT5 /* N77_54 */ #( + GTP_LUT5 /* N77_51 */ #( .INIT(32'b11111111000011101111111100001100)) - N77_54 ( - .Z (_N25124), + N77_51 ( + .Z (_N24930), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/cmd_pre_pass_m ), .I1 (cmd_pre_l), .I2 (N31), - .I3 (N47), - .I4 (_N96417_cpy)); + .I3 (_N97061), + .I4 (_N97179_cpy)); // LUT = (I3)|(I1&~I2)|(I0&~I2&I4) ; + GTP_LUT4 /* N77_62 */ #( + .INIT(16'b0000100000000000)) + N77_62 ( + .Z (_N97061), + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [3] ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [4] ), + .I2 (N45), + .I3 (_N105852)); + // LUT = I0&I1&~I2&I3 ; + + GTP_LUT5 /* N77_63 */ #( + .INIT(32'b11111101011111111111111111111111)) + N77_63 ( + .Z (_N97072), + .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N221 ), + .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [1] ), + .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [2] ), + .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [3] ), + .I4 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [4] )); + // LUT = (~I4)|(~I0)|(~I2&~I3)|(~I1&I2)|(I1&I3) ; + GTP_DFF_C /* r_cnt_pass */ #( .GRS_EN("TRUE"), .INIT(1'b0)) @@ -179362,18 +179158,18 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq32 ( input [42:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata , input N12, - input _N96772, + input _N97564, input clk, input cmd_act, input cmd_rd_l, input cmd_rd_m, - input cmd_wr, input cmd_wr_l, input cmd_wr_m, input \u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/cmd_rd_pass_l , output [5:0] timing_cnt0, output [6:0] timing_cnt1, - output cmd_pre_pass_l + output cmd_pre_pass_l, + output cmd_wr ); wire N50; wire N55; @@ -179397,6 +179193,14 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq32 // defparam N50_vname.orig_name = N50; // LUT = (I0)|(I1)|(I2)|(I3)|(I4) ; + GTP_LUT2 /* N52_mux5_1 */ #( + .INIT(4'b1110)) + N52_mux5_1 ( + .Z (cmd_wr), + .I0 (cmd_wr_l), + .I1 (cmd_wr_m)); + // LUT = (I0)|(I1) ; + GTP_LUT5 /* N55_mux6 */ #( .INIT(32'b11111111111111111111111111100000)) N55_mux6 ( @@ -179457,7 +179261,7 @@ module ipsxb_mcdq_timing_pre_pass_v1_2_unq32 .I1 (cmd_wr_m), .I2 (timing_cnt1[1]), .I3 (timing_cnt1[2]), - .I4 (_N96772)); + .I4 (_N97564)); // LUT = (I0)|(~I1&I2&I3)|(~I1&I2&I4) ; GTP_LUT5 /* \N91_2[2]_1 */ #( @@ -179684,12 +179488,12 @@ module ipsxb_mcdq_timing_ref_pass_v1_2 wire N35_inv_1; wire N46; wire [6:0] N50; - wire _N6672; - wire _N15265; - wire _N22538; - wire _N96352; - wire _N96653; - wire _N97011; + wire _N6745; + wire _N15294; + wire _N22394; + wire _N96730; + wire _N97405; + wire _N97780; wire [6:0] timing_cnt; GTP_LUT4 /* N7_mux6_3 */ #( @@ -179699,13 +179503,13 @@ module ipsxb_mcdq_timing_ref_pass_v1_2 .I0 (timing_cnt[0]), .I1 (timing_cnt[2]), .I2 (timing_cnt[3]), - .I3 (_N96653)); + .I3 (_N97405)); // LUT = (I2)|(I3)|(I0&I1) ; GTP_LUT3 /* N13_mux3 */ #( .INIT(8'b11100000)) N13_mux3 ( - .Z (_N6672), + .Z (_N6745), .I0 (timing_cnt[0]), .I1 (timing_cnt[2]), .I2 (timing_cnt[3])); @@ -179714,7 +179518,7 @@ module ipsxb_mcdq_timing_ref_pass_v1_2 GTP_LUT2 /* N13_mux6_2 */ #( .INIT(4'b1110)) N13_mux6_2 ( - .Z (_N97011), + .Z (_N97780), .I0 (timing_cnt[2]), .I1 (timing_cnt[3])); // LUT = (I0)|(I1) ; @@ -179723,7 +179527,7 @@ module ipsxb_mcdq_timing_ref_pass_v1_2 .INIT(32'b00000000000000000000000000000100)) N15_vname ( .Z (N15), - .I0 (_N6672), + .I0 (_N6745), .I1 (cmd_prea), .I2 (timing_cnt[4]), .I3 (timing_cnt[5]), @@ -179736,7 +179540,7 @@ module ipsxb_mcdq_timing_ref_pass_v1_2 .INIT(32'b01001100110011001100110011001100)) N22_vname ( .Z (N22), - .I0 (_N6672), + .I0 (_N6745), .I1 (cmd_ref), .I2 (timing_cnt[4]), .I3 (timing_cnt[5]), @@ -179748,7 +179552,7 @@ module ipsxb_mcdq_timing_ref_pass_v1_2 GTP_LUT3 /* N27_mux3_1 */ #( .INIT(8'b11111110)) N27_mux3_1 ( - .Z (_N96653), + .Z (_N97405), .I0 (timing_cnt[4]), .I1 (timing_cnt[5]), .I2 (timing_cnt[6])); @@ -179803,7 +179607,7 @@ module ipsxb_mcdq_timing_ref_pass_v1_2 GTP_LUT5 /* \N50_10[3] */ #( .INIT(32'b10011001100110011001100110011000)) \N50_10[3] ( - .Z (_N22538), + .Z (_N22394), .I0 (timing_cnt[2]), .I1 (timing_cnt[3]), .I2 (timing_cnt[4]), @@ -179814,7 +179618,7 @@ module ipsxb_mcdq_timing_ref_pass_v1_2 GTP_LUT3 /* N50_12_maj1_1 */ #( .INIT(8'b11111110)) N50_12_maj1_1 ( - .Z (_N15265), + .Z (_N15294), .I0 (timing_cnt[2]), .I1 (timing_cnt[3]), .I2 (timing_cnt[4])); @@ -179831,15 +179635,6 @@ module ipsxb_mcdq_timing_ref_pass_v1_2 .I4 (timing_cnt[0])); // LUT = (~I1&~I2&I3)|(I0&~I1&~I2&I4) ; - GTP_LUT3 /* \N50_15[0]_3 */ #( - .INIT(8'b00000010)) - \N50_15[0]_3 ( - .Z (_N96352), - .I0 (N35_inv_1), - .I1 (N15), - .I2 (N29)); - // LUT = I0&~I1&~I2 ; - GTP_LUT5 /* \N50_15[2]_4 */ #( .INIT(32'b11111111111111001111111111111110)) \N50_15[2]_4 ( @@ -179855,12 +179650,21 @@ module ipsxb_mcdq_timing_ref_pass_v1_2 .INIT(16'b0000001100000010)) \N50_15[3] ( .Z (N50[3]), - .I0 (_N22538), + .I0 (_N22394), .I1 (N15), .I2 (N22), .I3 (N29)); // LUT = (I0&~I1&~I2)|(~I1&~I2&I3) ; + GTP_LUT3 /* \N50_15[3]_3 */ #( + .INIT(8'b00000010)) + \N50_15[3]_3 ( + .Z (_N96730), + .I0 (N35_inv_1), + .I1 (N15), + .I2 (N29)); + // LUT = I0&~I1&~I2 ; + GTP_LUT5 /* \N50_15[4] */ #( .INIT(32'b11111110101010111010101010101010)) \N50_15[4] ( @@ -179869,7 +179673,7 @@ module ipsxb_mcdq_timing_ref_pass_v1_2 .I1 (timing_cnt[2]), .I2 (timing_cnt[3]), .I3 (timing_cnt[4]), - .I4 (_N96352)); + .I4 (_N96730)); // LUT = (I0)|(I1&I3&I4)|(I2&I3&I4)|(~I1&~I2&~I3&I4) ; GTP_LUT5 /* \N50_15[5] */ #( @@ -179879,19 +179683,19 @@ module ipsxb_mcdq_timing_ref_pass_v1_2 .I0 (N22), .I1 (timing_cnt[4]), .I2 (timing_cnt[5]), - .I3 (_N96352), - .I4 (_N97011)); + .I3 (_N96730), + .I4 (_N97780)); // LUT = (I0)|(I1&I2&I3)|(I2&I3&I4)|(~I1&~I2&I3&~I4) ; GTP_LUT5 /* \N50_15[6] */ #( .INIT(32'b11111110110011011100110011001100)) \N50_15[6] ( .Z (N50[6]), - .I0 (_N15265), + .I0 (_N15294), .I1 (N22), .I2 (timing_cnt[5]), .I3 (timing_cnt[6]), - .I4 (_N96352)); + .I4 (_N96730)); // LUT = (I1)|(I0&I3&I4)|(I2&I3&I4)|(~I0&~I2&~I3&I4) ; GTP_DFF_C /* r_cnt_pass */ #( @@ -179986,11 +179790,10 @@ module ipsxb_mcdq_timing_wr_pass_v1_2 wire N14; wire N27; wire N97; - wire N98; wire N104; wire N106; wire [5:0] N110; - wire _N103441; + wire _N104253; wire [5:0] timing_cnt1_alias; assign timing_cnt1_alias[2] = timing_cnt1[2]; @@ -180013,29 +179816,16 @@ module ipsxb_mcdq_timing_wr_pass_v1_2 // LUT = (I0&I2)|(I1&I2) ; GTP_LUT5 /* N97 */ #( - .INIT(32'b10101111000011111010110000001100)) + .INIT(32'b00001111000011110000000000010001)) N97_vname ( .Z (N97), - .I0 (cmd_wr_pass_l), - .I1 (cmd_wr_l), - .I2 (cmd_wr_m), - .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [38] ), - .I4 (N98)); - // defparam N97_vname.orig_name = N97; - // LUT = (I1&~I2)|(~I2&I4)|(I0&I2&I3) ; - // ../ipcore/axi_ddr/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_timing_wr_pass_v1_2.vp:169 - - GTP_LUT5 /* N98 */ #( - .INIT(32'b00000000000000010001000100010001)) - N98_vname ( - .Z (N98), .I0 (cmd_rd_l), .I1 (cmd_rd_m), - .I2 (timing_cnt1_alias[0]), - .I3 (timing_cnt1_alias[1]), - .I4 (timing_cnt1_alias[2])); - // defparam N98_vname.orig_name = N98; - // LUT = (~I0&~I1&~I4)|(~I0&~I1&~I2&~I3) ; + .I2 (N14), + .I3 (N27), + .I4 (cmd_wr)); + // defparam N97_vname.orig_name = N97; + // LUT = (~I2&I4)|(~I0&~I1&~I3&~I4) ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_timing_wr_pass_v1_2.vp:169 GTP_LUT3 /* N104_2 */ #( @@ -180085,14 +179875,14 @@ module ipsxb_mcdq_timing_wr_pass_v1_2 .Q (cmd_wr_pass), .C (N12), .CLK (clk), - .D (_N103441)); + .D (_N104253)); // defparam cmd_wr_pass_vname.orig_name = cmd_wr_pass; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/syn_mod/ipsxb_mcdq_timing_wr_pass_v1_2.vp:231 GTP_LUT5M /* cmd_wr_pass_ce_mux */ #( .INIT(32'b01010101010101010000000000100011)) cmd_wr_pass_ce_mux ( - .Z (_N103441), + .Z (_N104253), .I0 (N14), .I1 (cmd_rd_m), .I2 (N27), @@ -180177,32 +179967,32 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 wire N1205; wire N1206; wire N1332; - wire _N24992; - wire _N24993; - wire _N24995; - wire _N25007; - wire _N25008; - wire _N25010; - wire _N25024; - wire _N25031; - wire _N25035; - wire _N25040; - wire _N25041; - wire _N84089; - wire _N96409; - wire _N96411; - wire _N96414; - wire _N96417; - wire _N96417_cpy; - wire _N96772; - wire _N102308_2; - wire _N102308_3; - wire _N102308_4; - wire _N102308_5; - wire _N102308_6; - wire _N102308_7; - wire _N104834; - wire _N104986; + wire _N24718; + wire _N24719; + wire _N24721; + wire _N24733; + wire _N24734; + wire _N24736; + wire _N24750; + wire _N24757; + wire _N24761; + wire _N24766; + wire _N24767; + wire _N84881; + wire _N97171; + wire _N97173; + wire _N97176; + wire _N97179; + wire _N97179_cpy; + wire _N97564; + wire _N103547_2; + wire _N103547_3; + wire _N103547_4; + wire _N103547_5; + wire _N103547_6; + wire _N103547_7; + wire _N105852; + wire _N106004; wire [42:0] back_rdata_d1; wire back_valid_d1; wire cmd_accepted_l; @@ -180681,8 +180471,8 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 .INIT(16'b1111101011111100)) N104_vname ( .Z (N104), - .I0 (_N25035), - .I1 (_N25041), + .I0 (_N24761), + .I1 (_N24767), .I2 (cmd_accepted_l), .I3 (req_rdata[3])); // defparam N104_vname.orig_name = N104; @@ -180692,42 +180482,42 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 GTP_LUT5M /* \N136_1_or[0]_1_4 */ #( .INIT(32'b00100000000000000010000000000000)) \N136_1_or[0]_1_4 ( - .Z (_N104986), - .I0 (_N102308_2), + .Z (_N106004), + .I0 (_N103547_2), .I1 (cmd_act_pass), .I2 (tfaw_pass), .I3 (cmd_act_timing_pass), .I4 (req_rdata[15]), - .ID (_N102308_3)); + .ID (_N103547_3)); // LUT = (ID&~I1&I2&I3&~I4)|(I0&~I1&I2&I3&I4) ; GTP_LUT5 /* \N136_1_or[0]_1_6 */ #( .INIT(32'b10001000101000000000000000000000)) \N136_1_or[0]_1_6 ( .Z (N136), - .I0 (_N84089), - .I1 (_N24995), - .I2 (_N25010), + .I0 (_N84881), + .I1 (_N24721), + .I2 (_N24736), .I3 (req_rdata[15]), - .I4 (_N104986)); + .I4 (_N106004)); // LUT = (I0&I2&~I3&I4)|(I0&I1&I3&I4) ; GTP_MUX2LUT6 \N136_1_or[0]_1_8 ( - .Z (_N102308_2), - .I0 (_N102308_5), - .I1 (_N102308_4), + .Z (_N103547_2), + .I0 (_N103547_5), + .I1 (_N103547_4), .S (req_rdata[16])); GTP_MUX2LUT6 \N136_1_or[0]_1_9 ( - .Z (_N102308_3), - .I0 (_N102308_7), - .I1 (_N102308_6), + .Z (_N103547_3), + .I0 (_N103547_7), + .I1 (_N103547_6), .S (req_rdata[16])); GTP_LUT5 /* \N136_1_or[0]_1_10 */ #( .INIT(32'b11100100101000000100010000000000)) \N136_1_or[0]_1_10 ( - .Z (_N102308_4), + .Z (_N103547_4), .I0 (req_rdata[17]), .I1 (trc_pass_match[3]), .I2 (trc_pass_match[7]), @@ -180738,7 +180528,7 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 GTP_LUT5 /* \N136_1_or[0]_1_11 */ #( .INIT(32'b11100100101000000100010000000000)) \N136_1_or[0]_1_11 ( - .Z (_N102308_5), + .Z (_N103547_5), .I0 (req_rdata[17]), .I1 (trc_pass_match[1]), .I2 (trc_pass_match[5]), @@ -180749,7 +180539,7 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 GTP_LUT5 /* \N136_1_or[0]_1_12 */ #( .INIT(32'b11100100101000000100010000000000)) \N136_1_or[0]_1_12 ( - .Z (_N102308_6), + .Z (_N103547_6), .I0 (req_rdata[17]), .I1 (trc_pass_match[2]), .I2 (trc_pass_match[6]), @@ -180760,7 +180550,7 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 GTP_LUT5 /* \N136_1_or[0]_1_13 */ #( .INIT(32'b11100100101000000100010000000000)) \N136_1_or[0]_1_13 ( - .Z (_N102308_7), + .Z (_N103547_7), .I0 (req_rdata[17]), .I1 (trc_pass_match[0]), .I2 (trc_pass_match[4]), @@ -180771,7 +180561,7 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 GTP_LUT5M /* \N136_1_or[0]_7 */ #( .INIT(32'b00000000101000000000010010000000)) \N136_1_or[0]_7 ( - .Z (_N84089), + .Z (_N84881), .I0 (cmd_rd_pass), .I1 (cmd_wr_pass), .I2 (req_rdata[3]), @@ -180794,8 +180584,8 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 .INIT(16'b1010000011000000)) N194_vname ( .Z (N194), - .I0 (_N25035), - .I1 (_N25041), + .I0 (_N24761), + .I1 (_N24767), .I2 (req_valid), .I3 (req_rdata[3])); // defparam N194_vname.orig_name = N194; @@ -180845,7 +180635,7 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 GTP_LUT2 /* N220_1 */ #( .INIT(4'b0100)) N220_1 ( - .Z (_N96409), + .Z (_N97171), .I0 (req_rdata[3]), .I1 (req_rdata[4])); // LUT = ~I0&I1 ; @@ -180858,7 +180648,7 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 .I1 (req_valid), .I2 (req_rdata[1]), .I3 (req_rdata[2]), - .I4 (_N96409)); + .I4 (_N97171)); // LUT = I0&I1&~I2&I3&I4 ; GTP_LUT2 /* N221 */ #( @@ -180879,13 +180669,13 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 .I1 (req_valid), .I2 (req_rdata[1]), .I3 (req_rdata[2]), - .I4 (_N96409)); + .I4 (_N97171)); // LUT = I0&I1&I2&I3&I4 ; GTP_LUT2 /* N232_1 */ #( .INIT(4'b1000)) N232_1 ( - .Z (_N96411), + .Z (_N97173), .I0 (req_rdata[1]), .I1 (req_rdata[2])); // LUT = I0&I1 ; @@ -180893,7 +180683,7 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 GTP_LUT2 /* N232_4 */ #( .INIT(4'b0001)) N232_4 ( - .Z (_N96414), + .Z (_N97176), .I0 (req_rdata[1]), .I1 (req_rdata[2])); // LUT = ~I0&~I1 ; @@ -180906,7 +180696,7 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 .I1 (req_valid), .I2 (req_rdata[3]), .I3 (req_rdata[4]), - .I4 (_N96411)); + .I4 (_N97173)); // LUT = I0&I1&~I2&~I3&I4 ; GTP_LUT2 /* N240_1 */ #( @@ -180939,13 +180729,13 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 N244 ( .Z (norm_cmd_l_pre), .I0 (cmd_pre_pass_l), - .I1 (_N96417)); + .I1 (_N97179)); // LUT = I0&I1 ; GTP_LUT5 /* N244_4 */ #( .INIT(32'b00000000000010000000000000000000)) N244_4 ( - .Z (_N96417), + .Z (_N97179), .I0 (req_valid), .I1 (req_rdata[1]), .I2 (req_rdata[2]), @@ -180956,7 +180746,7 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 GTP_LUT5 /* N244_4_cpy */ #( .INIT(32'b00000000000010000000000000000000)) N244_4_cpy ( - .Z (_N96417_cpy), + .Z (_N97179_cpy), .I0 (req_valid), .I1 (req_rdata[1]), .I2 (req_rdata[2]), @@ -180995,7 +180785,7 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 .I0 (norm_cmd_l_act), .I1 (req_valid), .I2 (req_rdata[4]), - .I3 (_N96411), + .I3 (_N97173), .I4 (req_rdata[3]), .ID (cmd_rd_pass_m)); // LUT = (ID&I1&~I2&I3&~I4)|(I0&I1&~I2&I3&I4) ; @@ -181008,7 +180798,7 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 .I0 (norm_cmd_l_act), .I1 (req_rdata[3]), .I2 (req_valid), - .I3 (_N96414), + .I3 (_N97176), .I4 (req_rdata[4]), .ID (cmd_wr_pass_m)); // LUT = (ID&I1&I2&I3&~I4)|(I0&~I1&I2&I3&I4) ; @@ -181017,193 +180807,161 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 GTP_LUT4 /* N276_3 */ #( .INIT(16'b0000000000001000)) N276_3 ( - .Z (_N104834), + .Z (_N105852), .I0 (cmd_ref_pass), .I1 (req_valid), .I2 (req_rdata[1]), .I3 (req_rdata[2])); // LUT = I0&I1&~I2&~I3 ; - GTP_LUT4 /* \N516[0] */ #( - .INIT(16'b0000000000000010)) + GTP_LUT2 /* \N516[0] */ #( + .INIT(4'b1000)) \N516[0] ( .Z (pre_cmd_wr_l[0]), - .I0 (norm_cmd_l_wr), - .I1 (req_rdata[15]), - .I2 (req_rdata[16]), - .I3 (req_rdata[17])); - // LUT = I0&~I1&~I2&~I3 ; + .I0 (N1199), + .I1 (norm_cmd_l_wr)); + // LUT = I0&I1 ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcp_back_ctrl_v1_2.vp:1115 - GTP_LUT4 /* \N525[1] */ #( - .INIT(16'b0000000000001000)) + GTP_LUT2 /* \N525[1] */ #( + .INIT(4'b1000)) \N525[1] ( .Z (pre_cmd_wr_l[1]), - .I0 (norm_cmd_l_wr), - .I1 (req_rdata[15]), - .I2 (req_rdata[16]), - .I3 (req_rdata[17])); - // LUT = I0&I1&~I2&~I3 ; + .I0 (N1200), + .I1 (norm_cmd_l_wr)); + // LUT = I0&I1 ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcp_back_ctrl_v1_2.vp:1115 - GTP_LUT4 /* \N534[2] */ #( - .INIT(16'b0000000000100000)) + GTP_LUT2 /* \N534[2] */ #( + .INIT(4'b1000)) \N534[2] ( .Z (pre_cmd_wr_l[2]), - .I0 (norm_cmd_l_wr), - .I1 (req_rdata[15]), - .I2 (req_rdata[16]), - .I3 (req_rdata[17])); - // LUT = I0&~I1&I2&~I3 ; + .I0 (N1201), + .I1 (norm_cmd_l_wr)); + // LUT = I0&I1 ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcp_back_ctrl_v1_2.vp:1115 - GTP_LUT4 /* \N543[3] */ #( - .INIT(16'b0000000010000000)) + GTP_LUT2 /* \N543[3] */ #( + .INIT(4'b1000)) \N543[3] ( .Z (pre_cmd_wr_l[3]), - .I0 (norm_cmd_l_wr), - .I1 (req_rdata[15]), - .I2 (req_rdata[16]), - .I3 (req_rdata[17])); - // LUT = I0&I1&I2&~I3 ; + .I0 (N1202), + .I1 (norm_cmd_l_wr)); + // LUT = I0&I1 ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcp_back_ctrl_v1_2.vp:1115 - GTP_LUT4 /* \N552[4] */ #( - .INIT(16'b0000001000000000)) + GTP_LUT2 /* \N552[4] */ #( + .INIT(4'b1000)) \N552[4] ( .Z (pre_cmd_wr_l[4]), - .I0 (norm_cmd_l_wr), - .I1 (req_rdata[15]), - .I2 (req_rdata[16]), - .I3 (req_rdata[17])); - // LUT = I0&~I1&~I2&I3 ; + .I0 (N1203), + .I1 (norm_cmd_l_wr)); + // LUT = I0&I1 ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcp_back_ctrl_v1_2.vp:1115 - GTP_LUT4 /* \N561[5] */ #( - .INIT(16'b0000100000000000)) + GTP_LUT2 /* \N561[5] */ #( + .INIT(4'b1000)) \N561[5] ( .Z (pre_cmd_wr_l[5]), - .I0 (norm_cmd_l_wr), - .I1 (req_rdata[15]), - .I2 (req_rdata[16]), - .I3 (req_rdata[17])); - // LUT = I0&I1&~I2&I3 ; + .I0 (N1204), + .I1 (norm_cmd_l_wr)); + // LUT = I0&I1 ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcp_back_ctrl_v1_2.vp:1115 - GTP_LUT4 /* \N570[6] */ #( - .INIT(16'b0010000000000000)) + GTP_LUT2 /* \N570[6] */ #( + .INIT(4'b1000)) \N570[6] ( .Z (pre_cmd_wr_l[6]), - .I0 (norm_cmd_l_wr), - .I1 (req_rdata[15]), - .I2 (req_rdata[16]), - .I3 (req_rdata[17])); - // LUT = I0&~I1&I2&I3 ; + .I0 (N1205), + .I1 (norm_cmd_l_wr)); + // LUT = I0&I1 ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcp_back_ctrl_v1_2.vp:1115 - GTP_LUT4 /* \N579[7] */ #( - .INIT(16'b1000000000000000)) + GTP_LUT2 /* \N579[7] */ #( + .INIT(4'b1000)) \N579[7] ( .Z (pre_cmd_wr_l[7]), - .I0 (norm_cmd_l_wr), - .I1 (req_rdata[15]), - .I2 (req_rdata[16]), - .I3 (req_rdata[17])); - // LUT = I0&I1&I2&I3 ; + .I0 (N1206), + .I1 (norm_cmd_l_wr)); + // LUT = I0&I1 ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcp_back_ctrl_v1_2.vp:1115 - GTP_LUT4 /* \N589[0] */ #( - .INIT(16'b0000000000000010)) + GTP_LUT2 /* \N589[0] */ #( + .INIT(4'b1000)) \N589[0] ( .Z (pre_cmd_wr_m[0]), - .I0 (norm_cmd_m_wr), - .I1 (req_rdata[15]), - .I2 (req_rdata[16]), - .I3 (req_rdata[17])); - // LUT = I0&~I1&~I2&~I3 ; + .I0 (N1199), + .I1 (norm_cmd_m_wr)); + // LUT = I0&I1 ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcp_back_ctrl_v1_2.vp:1123 - GTP_LUT4 /* \N598[1] */ #( - .INIT(16'b0000000000001000)) + GTP_LUT2 /* \N598[1] */ #( + .INIT(4'b1000)) \N598[1] ( .Z (pre_cmd_wr_m[1]), - .I0 (norm_cmd_m_wr), - .I1 (req_rdata[15]), - .I2 (req_rdata[16]), - .I3 (req_rdata[17])); - // LUT = I0&I1&~I2&~I3 ; + .I0 (N1200), + .I1 (norm_cmd_m_wr)); + // LUT = I0&I1 ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcp_back_ctrl_v1_2.vp:1123 - GTP_LUT4 /* \N607[2] */ #( - .INIT(16'b0000000000100000)) + GTP_LUT2 /* \N607[2] */ #( + .INIT(4'b1000)) \N607[2] ( .Z (pre_cmd_wr_m[2]), - .I0 (norm_cmd_m_wr), - .I1 (req_rdata[15]), - .I2 (req_rdata[16]), - .I3 (req_rdata[17])); - // LUT = I0&~I1&I2&~I3 ; + .I0 (N1201), + .I1 (norm_cmd_m_wr)); + // LUT = I0&I1 ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcp_back_ctrl_v1_2.vp:1123 - GTP_LUT4 /* \N616[3] */ #( - .INIT(16'b0000000010000000)) + GTP_LUT2 /* \N616[3] */ #( + .INIT(4'b1000)) \N616[3] ( .Z (pre_cmd_wr_m[3]), - .I0 (norm_cmd_m_wr), - .I1 (req_rdata[15]), - .I2 (req_rdata[16]), - .I3 (req_rdata[17])); - // LUT = I0&I1&I2&~I3 ; + .I0 (N1202), + .I1 (norm_cmd_m_wr)); + // LUT = I0&I1 ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcp_back_ctrl_v1_2.vp:1123 - GTP_LUT4 /* \N625[4] */ #( - .INIT(16'b0000001000000000)) + GTP_LUT2 /* \N625[4] */ #( + .INIT(4'b1000)) \N625[4] ( .Z (pre_cmd_wr_m[4]), - .I0 (norm_cmd_m_wr), - .I1 (req_rdata[15]), - .I2 (req_rdata[16]), - .I3 (req_rdata[17])); - // LUT = I0&~I1&~I2&I3 ; + .I0 (N1203), + .I1 (norm_cmd_m_wr)); + // LUT = I0&I1 ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcp_back_ctrl_v1_2.vp:1123 - GTP_LUT4 /* \N634[5] */ #( - .INIT(16'b0000100000000000)) + GTP_LUT2 /* \N634[5] */ #( + .INIT(4'b1000)) \N634[5] ( .Z (pre_cmd_wr_m[5]), - .I0 (norm_cmd_m_wr), - .I1 (req_rdata[15]), - .I2 (req_rdata[16]), - .I3 (req_rdata[17])); - // LUT = I0&I1&~I2&I3 ; + .I0 (N1204), + .I1 (norm_cmd_m_wr)); + // LUT = I0&I1 ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcp_back_ctrl_v1_2.vp:1123 - GTP_LUT4 /* \N643[6] */ #( - .INIT(16'b0010000000000000)) + GTP_LUT2 /* \N643[6] */ #( + .INIT(4'b1000)) \N643[6] ( .Z (pre_cmd_wr_m[6]), - .I0 (norm_cmd_m_wr), - .I1 (req_rdata[15]), - .I2 (req_rdata[16]), - .I3 (req_rdata[17])); - // LUT = I0&~I1&I2&I3 ; + .I0 (N1205), + .I1 (norm_cmd_m_wr)); + // LUT = I0&I1 ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcp_back_ctrl_v1_2.vp:1123 - GTP_LUT4 /* \N652[7] */ #( - .INIT(16'b1000000000000000)) + GTP_LUT2 /* \N652[7] */ #( + .INIT(4'b1000)) \N652[7] ( .Z (pre_cmd_wr_m[7]), - .I0 (norm_cmd_m_wr), - .I1 (req_rdata[15]), - .I2 (req_rdata[16]), - .I3 (req_rdata[17])); - // LUT = I0&I1&I2&I3 ; + .I0 (N1206), + .I1 (norm_cmd_m_wr)); + // LUT = I0&I1 ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcp_back_ctrl_v1_2.vp:1123 GTP_LUT5M /* \N702_4[0] */ #( .INIT(32'b11001010110010101111101000001010)) \N702_4[0] ( - .Z (_N24992), + .Z (_N24718), .I0 (cmd_pre_pass_match[5]), .I1 (cmd_pre_pass_match[7]), .I2 (req_rdata[16]), @@ -181215,7 +180973,7 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 GTP_LUT5M /* \N702_4[1] */ #( .INIT(32'b11001010110010101111101000001010)) \N702_4[1] ( - .Z (_N24993), + .Z (_N24719), .I0 (cmd_pre_almost_match[5]), .I1 (cmd_pre_almost_match[7]), .I2 (req_rdata[16]), @@ -181227,7 +180985,7 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 GTP_LUT5M /* \N702_4[3] */ #( .INIT(32'b11111010000010101100101011001010)) \N702_4[3] ( - .Z (_N24995), + .Z (_N24721), .I0 (twra2act_match[5]), .I1 (twra2act_match[3]), .I2 (req_rdata[16]), @@ -181239,7 +180997,7 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 GTP_LUT5M /* \N702_7[0] */ #( .INIT(32'b11001010110010101111101000001010)) \N702_7[0] ( - .Z (_N25007), + .Z (_N24733), .I0 (cmd_pre_pass_match[4]), .I1 (cmd_pre_pass_match[6]), .I2 (req_rdata[16]), @@ -181251,7 +181009,7 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 GTP_LUT5M /* \N702_7[1] */ #( .INIT(32'b11001010110010101111101000001010)) \N702_7[1] ( - .Z (_N25008), + .Z (_N24734), .I0 (cmd_pre_almost_match[4]), .I1 (cmd_pre_almost_match[6]), .I2 (req_rdata[16]), @@ -181263,7 +181021,7 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 GTP_LUT5M /* \N702_7[3] */ #( .INIT(32'b11111010000010101100101011001010)) \N702_7[3] ( - .Z (_N25010), + .Z (_N24736), .I0 (twra2act_match[4]), .I1 (twra2act_match[2]), .I2 (req_rdata[16]), @@ -181274,14 +181032,14 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 GTP_MUX2LUT6 \N702_8[0] ( .Z (cmd_pre_pass_l), - .I0 (_N25007), - .I1 (_N24992), + .I0 (_N24733), + .I1 (_N24718), .S (req_rdata[15])); GTP_MUX2LUT6 \N702_8[1] ( .Z (cmd_pre_pass_m), - .I0 (_N25008), - .I1 (_N24993), + .I0 (_N24734), + .I1 (_N24719), .S (req_rdata[15])); GTP_LUT4 /* N1169 */ #( @@ -181396,7 +181154,6 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcp_back_ctrl_v1_2.vp:987 ipsxb_mcdq_timing_pre_pass_v1_2 \PRE_PASS_LOOP[0].timing_pre_pass ( - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, req_rdata[17], req_rdata[16], req_rdata[15], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), .cmd_pre_pass_l (cmd_pre_pass_match[0]), .cmd_pre_pass_m (cmd_pre_almost_match[0]), .N12 (N97), @@ -181412,7 +181169,6 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcp_back_ctrl_v1_2.vp:1133 ipsxb_mcdq_timing_pre_pass_v1_2_unq18 \PRE_PASS_LOOP[1].timing_pre_pass ( - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, req_rdata[17], req_rdata[16], req_rdata[15], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), .cmd_pre_pass_l (cmd_pre_pass_match[1]), .cmd_pre_pass_m (cmd_pre_almost_match[1]), .N12 (N97), @@ -181428,7 +181184,6 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcp_back_ctrl_v1_2.vp:1133 ipsxb_mcdq_timing_pre_pass_v1_2_unq20 \PRE_PASS_LOOP[2].timing_pre_pass ( - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, req_rdata[17], req_rdata[16], req_rdata[15], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), .cmd_pre_pass_l (cmd_pre_pass_match[2]), .cmd_pre_pass_m (cmd_pre_almost_match[2]), .N12 (N97), @@ -181444,7 +181199,6 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcp_back_ctrl_v1_2.vp:1133 ipsxb_mcdq_timing_pre_pass_v1_2_unq22 \PRE_PASS_LOOP[3].timing_pre_pass ( - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, req_rdata[17], req_rdata[16], req_rdata[15], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), .cmd_pre_pass_l (cmd_pre_pass_match[3]), .cmd_pre_pass_m (cmd_pre_almost_match[3]), .N12 (N97), @@ -181460,7 +181214,6 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcp_back_ctrl_v1_2.vp:1133 ipsxb_mcdq_timing_pre_pass_v1_2_unq24 \PRE_PASS_LOOP[4].timing_pre_pass ( - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, req_rdata[17], req_rdata[16], req_rdata[15], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), .cmd_pre_pass_l (cmd_pre_pass_match[4]), .cmd_pre_pass_m (cmd_pre_almost_match[4]), .N12 (N97), @@ -181476,7 +181229,6 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcp_back_ctrl_v1_2.vp:1133 ipsxb_mcdq_timing_pre_pass_v1_2_unq26 \PRE_PASS_LOOP[5].timing_pre_pass ( - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, req_rdata[17], req_rdata[16], req_rdata[15], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), .cmd_pre_pass_l (cmd_pre_pass_match[5]), .cmd_pre_pass_m (cmd_pre_almost_match[5]), .N12 (N97), @@ -181492,7 +181244,6 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcp_back_ctrl_v1_2.vp:1133 ipsxb_mcdq_timing_pre_pass_v1_2_unq28 \PRE_PASS_LOOP[6].timing_pre_pass ( - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, req_rdata[17], req_rdata[16], req_rdata[15], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), .cmd_pre_pass_l (cmd_pre_pass_match[6]), .cmd_pre_pass_m (cmd_pre_almost_match[6]), .N12 (N97), @@ -181508,7 +181259,6 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcp_back_ctrl_v1_2.vp:1133 ipsxb_mcdq_timing_pre_pass_v1_2_unq30 \PRE_PASS_LOOP[7].timing_pre_pass ( - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, req_rdata[17], req_rdata[16], req_rdata[15], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), .cmd_pre_pass_l (cmd_pre_pass_match[7]), .cmd_pre_pass_m (cmd_pre_almost_match[7]), .N12 (N97), @@ -181588,7 +181338,6 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcp_back_ctrl_v1_2.vp:1211 ipsxb_mcdq_com_timing_v1_2_1 \TRDA2ACT_LOOP[0].trda2act_timing ( - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, req_rdata[17], req_rdata[16], req_rdata[15], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), .cnt_pass (trda2act_match[0]), .N5 (N97), .clk (clk), @@ -181661,7 +181410,6 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcp_back_ctrl_v1_2.vp:1313 ipsxb_mcdq_com_timing_v1_2 \TWRA2ACT_LOOP[0].twra2act_timing ( - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, req_rdata[17], req_rdata[16], req_rdata[15], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), .cnt_pass (twra2act_match[0]), .N5 (N97), .clk (clk), @@ -181671,7 +181419,6 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcp_back_ctrl_v1_2.vp:1278 ipsxb_mcdq_com_timing_v1_2_unq16 \TWRA2ACT_LOOP[1].twra2act_timing ( - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, req_rdata[17], req_rdata[16], req_rdata[15], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), .cnt_pass (twra2act_match[1]), .N5 (N97), .clk (clk), @@ -181681,7 +181428,6 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcp_back_ctrl_v1_2.vp:1278 ipsxb_mcdq_com_timing_v1_2_unq18 \TWRA2ACT_LOOP[2].twra2act_timing ( - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, req_rdata[17], req_rdata[16], req_rdata[15], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), .cnt_pass (twra2act_match[2]), .N5 (N97), .clk (clk), @@ -181691,7 +181437,6 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcp_back_ctrl_v1_2.vp:1278 ipsxb_mcdq_com_timing_v1_2_unq20 \TWRA2ACT_LOOP[3].twra2act_timing ( - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, req_rdata[17], req_rdata[16], req_rdata[15], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), .cnt_pass (twra2act_match[3]), .N5 (N97), .clk (clk), @@ -181701,7 +181446,6 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcp_back_ctrl_v1_2.vp:1278 ipsxb_mcdq_com_timing_v1_2_unq22 \TWRA2ACT_LOOP[4].twra2act_timing ( - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, req_rdata[17], req_rdata[16], req_rdata[15], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), .cnt_pass (twra2act_match[4]), .N5 (N97), .clk (clk), @@ -181711,7 +181455,6 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcp_back_ctrl_v1_2.vp:1278 ipsxb_mcdq_com_timing_v1_2_unq24 \TWRA2ACT_LOOP[5].twra2act_timing ( - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, req_rdata[17], req_rdata[16], req_rdata[15], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), .cnt_pass (twra2act_match[5]), .N5 (N97), .clk (clk), @@ -181721,7 +181464,6 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcp_back_ctrl_v1_2.vp:1278 ipsxb_mcdq_com_timing_v1_2_unq26 \TWRA2ACT_LOOP[6].twra2act_timing ( - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, req_rdata[17], req_rdata[16], req_rdata[15], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), .cnt_pass (twra2act_match[6]), .N5 (N97), .clk (clk), @@ -181731,7 +181473,6 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcp_back_ctrl_v1_2.vp:1278 ipsxb_mcdq_com_timing_v1_2_unq28 \TWRA2ACT_LOOP[7].twra2act_timing ( - .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, req_rdata[17], req_rdata[16], req_rdata[15], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), .cnt_pass (twra2act_match[7]), .N5 (N97), .clk (clk), @@ -182206,7 +181947,7 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 GTP_LUT5M /* cmd_accepted_l_4 */ #( .INIT(32'b11111110111100100000101000001010)) cmd_accepted_l_4 ( - .Z (_N25024), + .Z (_N24750), .I0 (cmd_pre_pass_l), .I1 (req_rdata[2]), .I2 (req_rdata[3]), @@ -182218,7 +181959,7 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 GTP_LUT5M /* cmd_accepted_l_11 */ #( .INIT(32'b11111010000011001010000011001111)) cmd_accepted_l_11 ( - .Z (_N25031), + .Z (_N24757), .I0 (cmd_prea_pass), .I1 (cmd_wr_pass_l), .I2 (req_rdata[3]), @@ -182229,14 +181970,14 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 GTP_MUX2LUT6 cmd_accepted_l_12 ( .Z (cmd_accepted_l), - .I0 (_N25031), - .I1 (_N25024), + .I0 (_N24757), + .I1 (_N24750), .S (req_rdata[1])); GTP_LUT5 /* cmd_accepted_m_3 */ #( .INIT(32'b00000000000000001100110011001010)) cmd_accepted_m_3 ( - .Z (_N25035), + .Z (_N24761), .I0 (cmd_wr_pass_m), .I1 (norm_cmd_l_act), .I2 (req_rdata[1]), @@ -182247,7 +181988,7 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 GTP_LUT4 /* cmd_accepted_m_8 */ #( .INIT(16'b1010110010100000)) cmd_accepted_m_8 ( - .Z (_N25040), + .Z (_N24766), .I0 (cmd_rd_pass_m), .I1 (cmd_wr_pass_m), .I2 (req_rdata[1]), @@ -182257,13 +181998,13 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 GTP_LUT5M /* cmd_accepted_m_9 */ #( .INIT(32'b00001110000000101010101010101010)) cmd_accepted_m_9 ( - .Z (_N25041), + .Z (_N24767), .I0 (norm_cmd_l_act), .I1 (req_rdata[1]), .I2 (req_rdata[2]), .I3 (cmd_pre_pass_m), .I4 (req_rdata[4]), - .ID (_N25040)); + .ID (_N24766)); // LUT = (ID&~I4)|(I1&~I2&I3&I4)|(I0&~I1&~I2&I4) ; GTP_DFF_C /* cmd_act_pass */ #( @@ -182291,15 +182032,15 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 ipsxb_mcdq_timing_rd_pass_v1_2 mcdq_timing_rd_pass ( .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata ({1'bx, 1'bx, 1'bx, req_rdata[39], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1 ({1'bx, 1'bx, \timing_prea_pass/timing_cnt1 [4] , \timing_prea_pass/timing_cnt1 [3] , 1'bx, 1'bx, 1'bx}), - ._N96772 (_N96772), + ._N97564 (_N97564), .cmd_rd_pass (cmd_rd_pass), .cmd_rd_pass_l (cmd_rd_pass_l), .cmd_rd_pass_m (cmd_rd_pass_m), - .cmd_wr (\mcdq_timing_rd_pass/cmd_wr ), .N12 (N97), .clk (clk), .cmd_rd_l (norm_cmd_l_rd), .cmd_rd_m (norm_cmd_m_rd), + .cmd_wr (\mcdq_timing_rd_pass/cmd_wr ), .cmd_wr_l (norm_cmd_l_wr), .cmd_wr_m (norm_cmd_m_wr), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N210 (N210)); @@ -183174,9 +182915,9 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, req_rdata[4], req_rdata[3], req_rdata[2], req_rdata[1], 1'bx}), .cmd_act_pass (cmd_act_timing_pass), .N6 (N97), - ._N96417 (_N96417), - ._N96417_cpy (_N96417_cpy), - ._N104834 (_N104834), + ._N97179 (_N97179), + ._N97179_cpy (_N97179_cpy), + ._N105852 (_N105852), .clk (clk), .cmd_pre_l (norm_cmd_l_pre), .cmd_ref (norm_cmd_l_ref), @@ -183190,13 +182931,13 @@ module ipsxb_mcdq_dcp_back_ctrl_v1_2 .timing_cnt1 ({\timing_prea_pass_timing_cnt1[6]_floating , \timing_prea_pass_timing_cnt1[5]_floating , \timing_prea_pass/timing_cnt1 [4] , \timing_prea_pass/timing_cnt1 [3] , \timing_prea_pass_timing_cnt1[2]_floating , \timing_prea_pass_timing_cnt1[1]_floating , \timing_prea_pass_timing_cnt1[0]_floating }), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata ({1'bx, 1'bx, 1'bx, req_rdata[39], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), .cmd_pre_pass_l (cmd_prea_pass), + .cmd_wr (\mcdq_timing_rd_pass/cmd_wr ), .N12 (N97), - ._N96772 (_N96772), + ._N97564 (_N97564), .clk (clk), .cmd_act (norm_cmd_l_act), .cmd_rd_l (norm_cmd_l_rd), .cmd_rd_m (norm_cmd_m_rd), - .cmd_wr (\mcdq_timing_rd_pass/cmd_wr ), .cmd_wr_l (norm_cmd_l_wr), .cmd_wr_m (norm_cmd_m_wr), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/cmd_rd_pass_l (cmd_rd_pass_l)); @@ -183724,14 +183465,14 @@ module ipsxb_distributed_fifo_ctr_v1_0_2 wire N36; wire [5:0] \N36.co ; wire N76; - wire _N15088; - wire _N15089; - wire _N15090; - wire _N15091; - wire _N15094; - wire _N15095; - wire _N15096; - wire _N15097; + wire _N15117; + wire _N15118; + wire _N15119; + wire _N15120; + wire _N15123; + wire _N15124; + wire _N15125; + wire _N15126; wire [4:0] rgnext; wire [4:0] rwptr2_b; wire [4:0] wgnext; @@ -183744,7 +183485,7 @@ module ipsxb_distributed_fifo_ctr_v1_0_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_1 ( - .COUT (_N15088), + .COUT (_N15117), .Z (N2[0]), .CIN (), .I0 (w_en), @@ -183764,9 +183505,9 @@ module ipsxb_distributed_fifo_ctr_v1_0_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_2 ( - .COUT (_N15089), + .COUT (_N15118), .Z (N2[1]), - .CIN (_N15088), + .CIN (_N15117), .I0 (w_en), .I1 (wr_addr[0]), .I2 (wr_addr[1]), @@ -183784,9 +183525,9 @@ module ipsxb_distributed_fifo_ctr_v1_0_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_3 ( - .COUT (_N15090), + .COUT (_N15119), .Z (N2[2]), - .CIN (_N15089), + .CIN (_N15118), .I0 (), .I1 (wr_addr[2]), .I2 (), @@ -183804,9 +183545,9 @@ module ipsxb_distributed_fifo_ctr_v1_0_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_4 ( - .COUT (_N15091), + .COUT (_N15120), .Z (N2[3]), - .CIN (_N15090), + .CIN (_N15119), .I0 (), .I1 (rwptr2_b[3]), .I2 (), @@ -183826,7 +183567,7 @@ module ipsxb_distributed_fifo_ctr_v1_0_2 N2_5 ( .COUT (), .Z (N2[4]), - .CIN (_N15091), + .CIN (_N15120), .I0 (), .I1 (rwptr2_b[4]), .I2 (), @@ -183899,7 +183640,7 @@ module ipsxb_distributed_fifo_ctr_v1_0_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N9_1 ( - .COUT (_N15094), + .COUT (_N15123), .Z (N9[0]), .CIN (), .I0 (r_en), @@ -183919,9 +183660,9 @@ module ipsxb_distributed_fifo_ctr_v1_0_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N9_2 ( - .COUT (_N15095), + .COUT (_N15124), .Z (N9[1]), - .CIN (_N15094), + .CIN (_N15123), .I0 (r_en), .I1 (rd_addr[0]), .I2 (rd_addr[1]), @@ -183939,9 +183680,9 @@ module ipsxb_distributed_fifo_ctr_v1_0_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N9_3 ( - .COUT (_N15096), + .COUT (_N15125), .Z (N9[2]), - .CIN (_N15095), + .CIN (_N15124), .I0 (), .I1 (rd_addr[2]), .I2 (), @@ -183959,9 +183700,9 @@ module ipsxb_distributed_fifo_ctr_v1_0_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N9_4 ( - .COUT (_N15097), + .COUT (_N15126), .Z (N9[3]), - .CIN (_N15096), + .CIN (_N15125), .I0 (), .I1 (wrptr2_b[3]), .I2 (), @@ -183981,7 +183722,7 @@ module ipsxb_distributed_fifo_ctr_v1_0_2 N9_5 ( .COUT (), .Z (N9[4]), - .CIN (_N15097), + .CIN (_N15126), .I0 (), .I1 (wrptr2_b[4]), .I2 (), @@ -185193,14 +184934,14 @@ module ipsxb_distributed_fifo_ctr_v1_0_2_unq4 wire N36; wire [5:0] \N36.co ; wire N76; - wire _N14985; - wire _N14986; - wire _N14987; - wire _N14988; - wire _N14991; - wire _N14992; - wire _N14993; - wire _N14994; + wire _N14932; + wire _N14933; + wire _N14934; + wire _N14935; + wire _N14938; + wire _N14939; + wire _N14940; + wire _N14941; wire [4:0] rgnext; wire [4:0] rwptr2_b; wire [4:0] wgnext; @@ -185213,7 +184954,7 @@ module ipsxb_distributed_fifo_ctr_v1_0_2_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_1 ( - .COUT (_N14985), + .COUT (_N14932), .Z (N2[0]), .CIN (), .I0 (w_en), @@ -185233,9 +184974,9 @@ module ipsxb_distributed_fifo_ctr_v1_0_2_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_2 ( - .COUT (_N14986), + .COUT (_N14933), .Z (N2[1]), - .CIN (_N14985), + .CIN (_N14932), .I0 (w_en), .I1 (wr_addr[0]), .I2 (wr_addr[1]), @@ -185253,9 +184994,9 @@ module ipsxb_distributed_fifo_ctr_v1_0_2_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_3 ( - .COUT (_N14987), + .COUT (_N14934), .Z (N2[2]), - .CIN (_N14986), + .CIN (_N14933), .I0 (), .I1 (wr_addr[2]), .I2 (), @@ -185273,9 +185014,9 @@ module ipsxb_distributed_fifo_ctr_v1_0_2_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_4 ( - .COUT (_N14988), + .COUT (_N14935), .Z (N2[3]), - .CIN (_N14987), + .CIN (_N14934), .I0 (), .I1 (rwptr2_b[3]), .I2 (), @@ -185295,7 +185036,7 @@ module ipsxb_distributed_fifo_ctr_v1_0_2_unq4 N2_5 ( .COUT (), .Z (N2[4]), - .CIN (_N14988), + .CIN (_N14935), .I0 (), .I1 (rwptr2_b[4]), .I2 (), @@ -185368,7 +185109,7 @@ module ipsxb_distributed_fifo_ctr_v1_0_2_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N9_1 ( - .COUT (_N14991), + .COUT (_N14938), .Z (N9[0]), .CIN (), .I0 (r_en), @@ -185388,9 +185129,9 @@ module ipsxb_distributed_fifo_ctr_v1_0_2_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N9_2 ( - .COUT (_N14992), + .COUT (_N14939), .Z (N9[1]), - .CIN (_N14991), + .CIN (_N14938), .I0 (r_en), .I1 (rd_addr[0]), .I2 (rd_addr[1]), @@ -185408,9 +185149,9 @@ module ipsxb_distributed_fifo_ctr_v1_0_2_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N9_3 ( - .COUT (_N14993), + .COUT (_N14940), .Z (N9[2]), - .CIN (_N14992), + .CIN (_N14939), .I0 (), .I1 (rd_addr[2]), .I2 (), @@ -185428,9 +185169,9 @@ module ipsxb_distributed_fifo_ctr_v1_0_2_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N9_4 ( - .COUT (_N14994), + .COUT (_N14941), .Z (N9[3]), - .CIN (_N14993), + .CIN (_N14940), .I0 (), .I1 (wrptr2_b[3]), .I2 (), @@ -185450,7 +185191,7 @@ module ipsxb_distributed_fifo_ctr_v1_0_2_unq4 N9_5 ( .COUT (), .Z (N9[4]), - .CIN (_N14994), + .CIN (_N14941), .I0 (), .I1 (wrptr2_b[4]), .I2 (), @@ -186192,15 +185933,15 @@ module ipsxb_mcdq_dcp_buf_v1_2 wire N197; wire N198; wire [42:0] N227; - wire _N15642; - wire _N15643; - wire _N15644; - wire _N15645; - wire _N15646; - wire _N103467; - wire _N103468; - wire _N103469; - wire _N103470; + wire _N15564; + wire _N15565; + wire _N15566; + wire _N15567; + wire _N15568; + wire _N104279; + wire _N104280; + wire _N104281; + wire _N104282; wire cmd_act; wire cmd_act2rd; wire cmd_act2wr; @@ -186329,7 +186070,7 @@ module ipsxb_mcdq_dcp_buf_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N46_1_1 ( - .COUT (_N15642), + .COUT (_N15564), .Z (dcd_wr_col[4]), .CIN (), .I0 (dcd_wr_addr[3]), @@ -186349,9 +186090,9 @@ module ipsxb_mcdq_dcp_buf_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N46_1_2 ( - .COUT (_N15643), + .COUT (_N15565), .Z (dcd_wr_col[5]), - .CIN (_N15642), + .CIN (_N15564), .I0 (dcd_wr_addr[3]), .I1 (dcd_wr_addr[4]), .I2 (dcd_wr_addr[5]), @@ -186369,9 +186110,9 @@ module ipsxb_mcdq_dcp_buf_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N46_1_3 ( - .COUT (_N15644), + .COUT (_N15566), .Z (dcd_wr_col[6]), - .CIN (_N15643), + .CIN (_N15565), .I0 (), .I1 (dcd_wr_addr[6]), .I2 (), @@ -186389,9 +186130,9 @@ module ipsxb_mcdq_dcp_buf_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N46_1_4 ( - .COUT (_N15645), + .COUT (_N15567), .Z (dcd_wr_col[7]), - .CIN (_N15644), + .CIN (_N15566), .I0 (), .I1 (dcd_wr_addr[7]), .I2 (), @@ -186409,9 +186150,9 @@ module ipsxb_mcdq_dcp_buf_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N46_1_5 ( - .COUT (_N15646), + .COUT (_N15568), .Z (dcd_wr_col[8]), - .CIN (_N15645), + .CIN (_N15567), .I0 (), .I1 (dcd_wr_addr[8]), .I2 (), @@ -186431,7 +186172,7 @@ module ipsxb_mcdq_dcp_buf_v1_2 N46_1_6 ( .COUT (), .Z (dcd_wr_col[9]), - .CIN (_N15646), + .CIN (_N15568), .I0 (), .I1 (dcd_wr_addr[9]), .I2 (), @@ -187089,14 +186830,14 @@ module ipsxb_mcdq_dcp_buf_v1_2 .Q (fifo_a_valid), .C (N36), .CLK (clk), - .D (_N103468)); + .D (_N104280)); // defparam fifo_a_valid_vname.orig_name = fifo_a_valid; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcp_buf_v1_2.vp:435 GTP_LUT5M /* fifo_a_valid_ce_mux */ #( .INIT(32'b11111111001000100000101000001010)) fifo_a_valid_ce_mux ( - .Z (_N103468), + .Z (_N104280), .I0 (req_valid), .I1 (rd_en), .I2 (fifo_empty_a), @@ -187112,14 +186853,14 @@ module ipsxb_mcdq_dcp_buf_v1_2 .Q (fifo_b_valid), .C (N36), .CLK (clk), - .D (_N103469)); + .D (_N104281)); // defparam fifo_b_valid_vname.orig_name = fifo_b_valid; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcp_buf_v1_2.vp:484 GTP_LUT5 /* fifo_b_valid_ce_mux */ #( .INIT(32'b00110000001100101111000001110010)) fifo_b_valid_ce_mux ( - .Z (_N103469), + .Z (_N104281), .I0 (N126), .I1 (N193), .I2 (fifo_b_valid), @@ -188036,14 +187777,14 @@ module ipsxb_mcdq_dcp_buf_v1_2 .Q (poll), .C (N36), .CLK (clk), - .D (_N103467)); + .D (_N104279)); // defparam poll_vname.orig_name = poll; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcp_buf_v1_2.vp:372 GTP_LUT3 /* poll_ce_mux */ #( .INIT(8'b11010010)) poll_ce_mux ( - .Z (_N103467), + .Z (_N104279), .I0 (dcd_wr_en), .I1 (dcd_wr_tworw), .I2 (poll)); @@ -188056,14 +187797,14 @@ module ipsxb_mcdq_dcp_buf_v1_2 .Q (rd_poll), .C (N36), .CLK (clk), - .D (_N103470)); + .D (_N104282)); // defparam rd_poll_vname.orig_name = rd_poll; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dcp_buf_v1_2.vp:498 GTP_LUT5 /* rd_poll_ce_mux */ #( .INIT(32'b00100010111111111101000011010000)) rd_poll_ce_mux ( - .Z (_N103470), + .Z (_N104282), .I0 (req_valid), .I1 (rd_en), .I2 (fifo_a_valid), @@ -188580,8 +188321,8 @@ module ipsxb_mcdq_dcp_out_v1_2 wire [3:0] N261; wire [7:0] N262; wire [14:0] N263; - wire _N96921; - wire _N97074; + wire _N97701; + wire _N97841; wire [3:0] norm_id_l; wire [3:0] norm_id_m; wire [3:0] rid; @@ -188597,13 +188338,13 @@ module ipsxb_mcdq_dcp_out_v1_2 .I1 (norm_cmd_l[2]), .I2 (norm_cmd_l[3]), .I3 (norm_cmd_l[4]), - .I4 (_N97074)); + .I4 (_N97841)); // LUT = (I0&~I1&~I2&~I3&I4)|(~I0&~I1&I2&~I3&I4) ; GTP_LUT4 /* N100_6 */ #( .INIT(16'b0000000000000001)) N100_6 ( - .Z (_N97074), + .Z (_N97841), .I0 (norm_cmd_l[0]), .I1 (norm_cmd_l[5]), .I2 (norm_cmd_l[6]), @@ -188618,7 +188359,7 @@ module ipsxb_mcdq_dcp_out_v1_2 .I1 (norm_cmd_m[2]), .I2 (norm_cmd_m[3]), .I3 (norm_cmd_m[4]), - .I4 (_N96921)); + .I4 (_N97701)); // LUT = (I0&~I1&~I2&~I3&I4)|(~I0&~I1&I2&~I3&I4) ; GTP_LUT5 /* N148_1_4 */ #( @@ -188629,7 +188370,7 @@ module ipsxb_mcdq_dcp_out_v1_2 .I1 (norm_cmd_l[2]), .I2 (norm_cmd_l[3]), .I3 (norm_cmd_l[4]), - .I4 (_N97074)); + .I4 (_N97841)); // LUT = (~I0&I1&~I2&~I3&I4)|(~I0&~I1&~I2&I3&I4) ; GTP_LUT4 /* \N160_6[0] */ #( @@ -188688,13 +188429,13 @@ module ipsxb_mcdq_dcp_out_v1_2 .I1 (norm_cmd_m[2]), .I2 (norm_cmd_m[3]), .I3 (norm_cmd_m[4]), - .I4 (_N96921)); + .I4 (_N97701)); // LUT = (~I0&I1&~I2&~I3&I4)|(~I0&~I1&~I2&I3&I4) ; - GTP_LUT3 /* N238_4 */ #( + GTP_LUT3 /* N238_5 */ #( .INIT(8'b00000001)) - N238_4 ( - .Z (_N96921), + N238_5 ( + .Z (_N97701), .I0 (norm_cmd_m[0]), .I1 (norm_cmd_m[6]), .I2 (norm_cmd_m[7])); @@ -188890,6 +188631,14 @@ module ipsxb_mcdq_dcp_out_v1_2 .I2 (pipe_req_addr[23])); // LUT = ~I0&I1&I2 ; + GTP_LUT2 /* \N252_6[10]_1 */ #( + .INIT(4'b0100)) + \N252_6[10]_1 ( + .Z (N250[5]), + .I0 (pipe_cmd_accepted_l), + .I1 (pipe_cmd_act)); + // LUT = ~I0&I1 ; + GTP_LUT3 /* \N252_6[11] */ #( .INIT(8'b01000000)) \N252_6[11] ( @@ -188908,14 +188657,6 @@ module ipsxb_mcdq_dcp_out_v1_2 .I2 (pipe_req_addr[25])); // LUT = ~I0&I1&I2 ; - GTP_LUT2 /* \N252_6[12]_1 */ #( - .INIT(4'b0100)) - \N252_6[12]_1 ( - .Z (N250[5]), - .I0 (pipe_cmd_accepted_l), - .I1 (pipe_cmd_act)); - // LUT = ~I0&I1 ; - GTP_LUT3 /* \N252_6[13] */ #( .INIT(8'b01000000)) \N252_6[13] ( @@ -190005,28 +189746,28 @@ module ipsxb_mcdq_dfi_v1_2 wire N2200; wire N2202; wire _N3; - wire _N96386; - wire _N96387; - wire _N96389; - wire _N96391; - wire _N96393; - wire _N96934; - wire _N96936; - wire _N97093; - wire _N97094; - wire _N97097; - wire _N97177; - wire _N97181; - wire _N103423; - wire _N103424; - wire _N103425; - wire _N103426; - wire _N105384; - wire _N105386; - wire _N105392; - wire _N105406; - wire _N107940; - wire _N107946; + wire _N97142; + wire _N97143; + wire _N97146; + wire _N97148; + wire _N97150; + wire _N97705; + wire _N97707; + wire _N97860; + wire _N97861; + wire _N97864; + wire _N97939; + wire _N97943; + wire _N104235; + wire _N104236; + wire _N104237; + wire _N104238; + wire _N106222; + wire _N106224; + wire _N106230; + wire _N106240; + wire _N108770; + wire _N108776; wire [29:0] dcp2dfi_address; wire [5:0] dcp2dfi_bank; wire [1:0] dcp2dfi_cas_n; @@ -190044,7 +189785,7 @@ module ipsxb_mcdq_dfi_v1_2 N149_2_inv ( .Z (N2195), .I0 (N366), - .I1 (_N96391)); + .I1 (_N97148)); // LUT = ~I0&~I1 ; GTP_LUT5 /* N149_5 */ #( @@ -190055,7 +189796,7 @@ module ipsxb_mcdq_dfi_v1_2 .I1 (N366), .I2 (N524), .I3 (N532), - .I4 (_N96391)); + .I4 (_N97148)); // LUT = (I0)|(I1)|(I2)|(I3)|(I4) ; GTP_LUT1 /* N150 */ #( @@ -190074,7 +189815,7 @@ module ipsxb_mcdq_dfi_v1_2 .I1 (norm_cmd_l[5]), .I2 (norm_cmd_l[6]), .I3 (norm_cmd_l[7]), - .I4 (_N97093)); + .I4 (_N97860)); // LUT = (~I4)|(I0&I1)|(I0&I2)|(I0&I3)|(I1&I2)|(I1&I3)|(I2&I3)|(~I0&~I1&~I2&~I3) ; GTP_LUT2 /* N311_2_inv */ #( @@ -190082,7 +189823,7 @@ module ipsxb_mcdq_dfi_v1_2 N311_2_inv ( .Z (N2202), .I0 (N338), - .I1 (_N96393)); + .I1 (_N97150)); // LUT = ~I0&~I1 ; GTP_LUT4 /* N312 */ #( @@ -190092,7 +189833,7 @@ module ipsxb_mcdq_dfi_v1_2 .I0 (N329), .I1 (N338), .I2 (N549), - .I3 (_N96393)); + .I3 (_N97150)); // defparam N312_vname.orig_name = N312; // LUT = ~I0&~I1&~I2&~I3 ; @@ -190103,8 +189844,8 @@ module ipsxb_mcdq_dfi_v1_2 .I0 (norm_cmd_m[0]), .I1 (norm_cmd_m[6]), .I2 (norm_cmd_m[7]), - .I3 (_N96386), - .I4 (_N96387)); + .I3 (_N97142), + .I4 (_N97143)); // LUT = (~I4)|(~I3)|(I0&I1)|(I0&I2)|(I1&I2)|(~I0&~I1&~I2) ; GTP_LUT5 /* N524_7 */ #( @@ -190115,13 +189856,13 @@ module ipsxb_mcdq_dfi_v1_2 .I1 (norm_cmd_l[5]), .I2 (norm_cmd_l[6]), .I3 (norm_cmd_l[7]), - .I4 (_N97093)); + .I4 (_N97860)); // LUT = ~I0&I1&~I2&~I3&I4 ; GTP_LUT4 /* N526_2 */ #( .INIT(16'b0000000000000001)) N526_2 ( - .Z (_N97094), + .Z (_N97861), .I0 (norm_cmd_l[0]), .I1 (norm_cmd_l[5]), .I2 (norm_cmd_l[6]), @@ -190131,7 +189872,7 @@ module ipsxb_mcdq_dfi_v1_2 GTP_LUT4 /* N530_1 */ #( .INIT(16'b0000000000000001)) N530_1 ( - .Z (_N97093), + .Z (_N97860), .I0 (norm_cmd_l[1]), .I1 (norm_cmd_l[2]), .I2 (norm_cmd_l[3]), @@ -190141,10 +189882,10 @@ module ipsxb_mcdq_dfi_v1_2 GTP_LUT3 /* N531_1 */ #( .INIT(8'b00010000)) N531_1 ( - .Z (_N97177), + .Z (_N97939), .I0 (norm_cmd_l[0]), .I1 (norm_cmd_l[6]), - .I2 (_N97093)); + .I2 (_N97860)); // LUT = ~I0&~I1&I2 ; GTP_LUT5 /* N532_3 */ #( @@ -190155,13 +189896,13 @@ module ipsxb_mcdq_dfi_v1_2 .I1 (norm_cmd_l[5]), .I2 (norm_cmd_l[6]), .I3 (norm_cmd_l[7]), - .I4 (_N97093)); + .I4 (_N97860)); // LUT = ~I0&~I1&I2&~I3&I4 ; GTP_LUT2 /* N543_1 */ #( .INIT(4'b0001)) N543_1 ( - .Z (_N96386), + .Z (_N97142), .I0 (norm_cmd_m[1]), .I1 (norm_cmd_m[2])); // LUT = ~I0&~I1 ; @@ -190169,7 +189910,7 @@ module ipsxb_mcdq_dfi_v1_2 GTP_LUT2 /* N543_2 */ #( .INIT(4'b0001)) N543_2 ( - .Z (_N96934), + .Z (_N97705), .I0 (norm_cmd_m[0]), .I1 (norm_cmd_m[6])); // LUT = ~I0&~I1 ; @@ -190177,7 +189918,7 @@ module ipsxb_mcdq_dfi_v1_2 GTP_LUT2 /* N543_6 */ #( .INIT(4'b0100)) N543_6 ( - .Z (_N105386), + .Z (_N106224), .I0 (norm_cmd_m[3]), .I1 (norm_cmd_m[4])); // LUT = ~I0&I1 ; @@ -190185,7 +189926,7 @@ module ipsxb_mcdq_dfi_v1_2 GTP_LUT5 /* N544_1 */ #( .INIT(32'b00000000000000000000000000000001)) N544_1 ( - .Z (_N97097), + .Z (_N97864), .I0 (norm_cmd_m[0]), .I1 (norm_cmd_m[1]), .I2 (norm_cmd_m[2]), @@ -190196,7 +189937,7 @@ module ipsxb_mcdq_dfi_v1_2 GTP_LUT2 /* N544_4 */ #( .INIT(4'b0010)) N544_4 ( - .Z (_N105384), + .Z (_N106222), .I0 (norm_cmd_m[3]), .I1 (norm_cmd_m[4])); // LUT = I0&~I1 ; @@ -190204,7 +189945,7 @@ module ipsxb_mcdq_dfi_v1_2 GTP_LUT2 /* N545_1 */ #( .INIT(4'b0001)) N545_1 ( - .Z (_N96387), + .Z (_N97143), .I0 (norm_cmd_m[3]), .I1 (norm_cmd_m[4])); // LUT = ~I0&~I1 ; @@ -190212,12 +189953,12 @@ module ipsxb_mcdq_dfi_v1_2 GTP_LUT5 /* N547_2 */ #( .INIT(32'b00000000000000100000000000000000)) N547_2 ( - .Z (_N97181), + .Z (_N97943), .I0 (norm_cmd_m[0]), .I1 (norm_cmd_m[1]), .I2 (norm_cmd_m[2]), .I3 (norm_cmd_m[7]), - .I4 (_N96387)); + .I4 (_N97143)); // LUT = I0&~I1&~I2&~I3&I4 ; GTP_LUT5 /* N549_3 */ #( @@ -190227,8 +189968,8 @@ module ipsxb_mcdq_dfi_v1_2 .I0 (norm_cmd_m[0]), .I1 (norm_cmd_m[6]), .I2 (norm_cmd_m[7]), - .I3 (_N96386), - .I4 (_N96387)); + .I3 (_N97142), + .I4 (_N97143)); // LUT = ~I0&I1&~I2&I3&I4 ; GTP_LUT5 /* N749 */ #( @@ -190238,8 +189979,8 @@ module ipsxb_mcdq_dfi_v1_2 .I0 (norm_cmd_m[0]), .I1 (norm_cmd_m[6]), .I2 (norm_cmd_m[7]), - .I3 (_N96386), - .I4 (_N96387)); + .I3 (_N97142), + .I4 (_N97143)); // defparam N749_vname.orig_name = N749; // LUT = (~I4)|(~I3)|(I0&I2)|(I1&I2)|(~I0&~I1&~I2) ; @@ -190247,12 +189988,12 @@ module ipsxb_mcdq_dfi_v1_2 .INIT(32'b00000000001000000000000000100000)) N750_1 ( .Z (N329), - .I0 (_N96387), + .I0 (_N97143), .I1 (norm_cmd_m[7]), - .I2 (_N96934), + .I2 (_N97705), .I3 (norm_cmd_m[1]), .I4 (norm_cmd_m[2]), - .ID (_N105386)); + .ID (_N106224)); // LUT = (ID&~I1&I2&~I3&~I4)|(I0&~I1&I2&~I3&I4) ; GTP_LUT5 /* \N753_1[0]_1 */ #( @@ -190263,7 +190004,7 @@ module ipsxb_mcdq_dfi_v1_2 .I1 (N329), .I2 (N338), .I3 (N549), - .I4 (_N96393)); + .I4 (_N97150)); // LUT = (I0&I1)|(I0&I2)|(I0&I3)|(I0&I4) ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dfi_v1_2.vp:614 @@ -190275,7 +190016,7 @@ module ipsxb_mcdq_dfi_v1_2 .I1 (N329), .I2 (N338), .I3 (N549), - .I4 (_N96393)); + .I4 (_N97150)); // LUT = (I0&I1)|(I0&I2)|(I0&I3)|(I0&I4) ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dfi_v1_2.vp:614 @@ -190287,7 +190028,7 @@ module ipsxb_mcdq_dfi_v1_2 .I1 (N329), .I2 (N338), .I3 (N549), - .I4 (_N96393)); + .I4 (_N97150)); // LUT = (I0&I1)|(I0&I2)|(I0&I3)|(I0&I4) ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dfi_v1_2.vp:614 @@ -190298,15 +190039,15 @@ module ipsxb_mcdq_dfi_v1_2 .I0 (norm_cmd_m[0]), .I1 (norm_cmd_m[6]), .I2 (norm_cmd_m[7]), - .I3 (_N96386), - .I4 (_N96387)); + .I3 (_N97142), + .I4 (_N97143)); // defparam N754_vname.orig_name = N754; // LUT = (~I4)|(~I3)|(~I1&~I2)|(I0&I2)|(I1&I2) ; GTP_LUT2 /* N761_1 */ #( .INIT(4'b1110)) N761_1 ( - .Z (_N96389), + .Z (_N97146), .I0 (N348), .I1 (r_brd_m)); // LUT = (I0)|(I1) ; @@ -190314,7 +190055,7 @@ module ipsxb_mcdq_dfi_v1_2 GTP_LUT3 /* N771_3 */ #( .INIT(8'b00000010)) N771_3 ( - .Z (_N107946), + .Z (_N108776), .I0 (N338), .I1 (N366), .I2 (r_bwr_m)); @@ -190323,12 +190064,12 @@ module ipsxb_mcdq_dfi_v1_2 GTP_LUT5 /* N1025_1_2 */ #( .INIT(32'b00000110000000000000000000000000)) N1025_1_2 ( - .Z (_N105392), + .Z (_N106230), .I0 (norm_cmd_m[1]), .I1 (norm_cmd_m[2]), .I2 (norm_cmd_m[7]), - .I3 (_N96387), - .I4 (_N96934)); + .I3 (_N97143), + .I4 (_N97705)); // LUT = (I0&~I1&~I2&I3&I4)|(~I0&I1&~I2&I3&I4) ; GTP_LUT4 /* N1025_1_3 */ #( @@ -190337,8 +190078,8 @@ module ipsxb_mcdq_dfi_v1_2 .Z (_N3), .I0 (norm_cmd_m[3]), .I1 (norm_cmd_m[4]), - .I2 (_N97097), - .I3 (_N105392)); + .I2 (_N97864), + .I3 (_N106230)); // LUT = (I3)|(I0&~I1&I2)|(~I0&I1&I2) ; GTP_LUT4 /* N1025_1_inv */ #( @@ -190347,20 +190088,20 @@ module ipsxb_mcdq_dfi_v1_2 .Z (N748[0]), .I0 (norm_cmd_m[3]), .I1 (norm_cmd_m[4]), - .I2 (_N97097), - .I3 (_N105392)); + .I2 (_N97864), + .I3 (_N106230)); // LUT = (~I2&~I3)|(~I0&~I1&~I3)|(I0&I1&~I3) ; GTP_LUT5M /* N1025_2 */ #( .INIT(32'b00000000001000000000000000100000)) N1025_2 ( .Z (N338), - .I0 (_N96387), + .I0 (_N97143), .I1 (norm_cmd_m[7]), - .I2 (_N96934), + .I2 (_N97705), .I3 (norm_cmd_m[2]), .I4 (norm_cmd_m[1]), - .ID (_N105384)); + .ID (_N106222)); // LUT = (ID&~I1&I2&~I3&~I4)|(I0&~I1&I2&~I3&I4) ; GTP_LUT2 /* \N1025_2[0] */ #( @@ -190456,7 +190197,7 @@ module ipsxb_mcdq_dfi_v1_2 GTP_LUT2 /* N1286_4 */ #( .INIT(4'b1110)) N1286_4 ( - .Z (_N96936), + .Z (_N97707), .I0 (N366), .I1 (r_bwr_m)); // LUT = (I0)|(I1) ; @@ -190469,7 +190210,7 @@ module ipsxb_mcdq_dfi_v1_2 .I1 (norm_cmd_l[2]), .I2 (norm_cmd_l[3]), .I3 (norm_cmd_l[4]), - .I4 (_N97094)); + .I4 (_N97861)); // LUT = (~I0&I1&~I2&~I3&I4)|(~I0&~I1&~I2&I3&I4) ; GTP_LUT2 /* \N1795_1[0]_1 */ #( @@ -190507,19 +190248,19 @@ module ipsxb_mcdq_dfi_v1_2 .I1 (norm_cmd_l[5]), .I2 (norm_cmd_l[6]), .I3 (norm_cmd_l[7]), - .I4 (_N97093)); + .I4 (_N97860)); // defparam N1796_vname.orig_name = N1796; // LUT = (~I4)|(I1)|(~I2&~I3)|(I0&I3)|(I2&I3) ; GTP_LUT5 /* N2048_2 */ #( .INIT(32'b00000001000100000000000000000000)) N2048_2 ( - .Z (_N105406), + .Z (_N106240), .I0 (norm_cmd_l[1]), .I1 (norm_cmd_l[2]), .I2 (norm_cmd_l[3]), .I3 (norm_cmd_l[4]), - .I4 (_N97094)); + .I4 (_N97861)); // LUT = (~I0&~I1&I2&~I3&I4)|(~I0&~I1&~I2&I3&I4) ; GTP_LUT5 /* N2051 */ #( @@ -190530,7 +190271,7 @@ module ipsxb_mcdq_dfi_v1_2 .I1 (norm_cmd_l[2]), .I2 (norm_cmd_l[3]), .I3 (norm_cmd_l[4]), - .I4 (_N97094)); + .I4 (_N97861)); // defparam N2051_vname.orig_name = N2051; // LUT = (I0&~I1&~I2&~I3&I4)|(~I0&I1&~I2&~I3&I4) ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dfi_v1_2.vp:550 @@ -190543,7 +190284,7 @@ module ipsxb_mcdq_dfi_v1_2 .I1 (norm_cmd_l[5]), .I2 (norm_cmd_l[6]), .I3 (norm_cmd_l[7]), - .I4 (_N97093)); + .I4 (_N97860)); // defparam N2053_vname.orig_name = N2053; // LUT = (~I4)|(I1)|(I0&I3)|(I2&I3)|(~I0&~I2&~I3) ; @@ -190555,7 +190296,7 @@ module ipsxb_mcdq_dfi_v1_2 .I1 (norm_addr_l[11]), .I2 (N524), .I3 (N2051), - .I4 (_N105406)); + .I4 (_N106240)); // LUT = (I0&~I2)|(I0&I1)|(~I2&~I3&~I4)|(I1&~I3&~I4) ; GTP_LUT3 /* \N2058_0_or[1] */ #( @@ -190588,23 +190329,23 @@ module ipsxb_mcdq_dfi_v1_2 GTP_LUT5 /* \N2065_1_or[0]_6 */ #( .INIT(32'b11111111001110001111111100000000)) \N2065_1_or[0]_6 ( - .Z (_N107940), + .Z (_N108770), .I0 (norm_addr_l[10]), .I1 (norm_cmd_l[5]), .I2 (norm_cmd_l[7]), .I3 (N2051), - .I4 (_N97177)); + .I4 (_N97939)); // LUT = (I3)|(~I1&I2&I4)|(I0&I1&~I2&I4) ; GTP_LUT5 /* N2070_2 */ #( .INIT(32'b00000001001000100000000000000000)) N2070_2 ( - .Z (_N96391), + .Z (_N97148), .I0 (norm_cmd_l[0]), .I1 (norm_cmd_l[5]), .I2 (norm_cmd_l[6]), .I3 (norm_cmd_l[7]), - .I4 (_N97093)); + .I4 (_N97860)); // LUT = (I0&~I1&~I3&I4)|(~I0&~I1&~I2&I3&I4) ; GTP_LUT4 /* \N2070_2[0] */ #( @@ -190614,7 +190355,7 @@ module ipsxb_mcdq_dfi_v1_2 .I0 (norm_addr_l[0]), .I1 (N524), .I2 (N2051), - .I3 (_N105406)); + .I3 (_N106240)); // LUT = (I0)|(~I1&~I2&~I3) ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dfi_v1_2.vp:550 @@ -190625,7 +190366,7 @@ module ipsxb_mcdq_dfi_v1_2 .I0 (norm_addr_l[1]), .I1 (N524), .I2 (N2051), - .I3 (_N105406)); + .I3 (_N106240)); // LUT = (I0)|(~I1&~I2&~I3) ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dfi_v1_2.vp:550 @@ -190636,7 +190377,7 @@ module ipsxb_mcdq_dfi_v1_2 .I0 (norm_addr_l[2]), .I1 (N524), .I2 (N2051), - .I3 (_N105406)); + .I3 (_N106240)); // LUT = (I0)|(~I1&~I2&~I3) ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dfi_v1_2.vp:550 @@ -190647,7 +190388,7 @@ module ipsxb_mcdq_dfi_v1_2 .I0 (norm_addr_l[3]), .I1 (N524), .I2 (N2051), - .I3 (_N105406)); + .I3 (_N106240)); // LUT = (I0)|(~I1&~I2&~I3) ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dfi_v1_2.vp:550 @@ -190658,7 +190399,7 @@ module ipsxb_mcdq_dfi_v1_2 .I0 (norm_addr_l[4]), .I1 (N524), .I2 (N2051), - .I3 (_N105406)); + .I3 (_N106240)); // LUT = (I0)|(~I1&~I2&~I3) ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dfi_v1_2.vp:550 @@ -190669,7 +190410,7 @@ module ipsxb_mcdq_dfi_v1_2 .I0 (norm_addr_l[5]), .I1 (N524), .I2 (N2051), - .I3 (_N105406)); + .I3 (_N106240)); // LUT = (I0)|(~I1&~I2&~I3) ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dfi_v1_2.vp:550 @@ -190680,7 +190421,7 @@ module ipsxb_mcdq_dfi_v1_2 .I0 (norm_addr_l[6]), .I1 (N524), .I2 (N2051), - .I3 (_N105406)); + .I3 (_N106240)); // LUT = (I0)|(~I1&~I2&~I3) ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dfi_v1_2.vp:550 @@ -190691,7 +190432,7 @@ module ipsxb_mcdq_dfi_v1_2 .I0 (norm_addr_l[7]), .I1 (N524), .I2 (N2051), - .I3 (_N105406)); + .I3 (_N106240)); // LUT = (I0)|(~I1&~I2&~I3) ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dfi_v1_2.vp:550 @@ -190702,7 +190443,7 @@ module ipsxb_mcdq_dfi_v1_2 .I0 (norm_addr_l[8]), .I1 (N524), .I2 (N2051), - .I3 (_N105406)); + .I3 (_N106240)); // LUT = (I0)|(~I1&~I2&~I3) ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dfi_v1_2.vp:550 @@ -190713,7 +190454,7 @@ module ipsxb_mcdq_dfi_v1_2 .I0 (norm_addr_l[9]), .I1 (N524), .I2 (N2051), - .I3 (_N105406)); + .I3 (_N106240)); // LUT = (I0)|(~I1&~I2&~I3) ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dfi_v1_2.vp:550 @@ -190725,7 +190466,7 @@ module ipsxb_mcdq_dfi_v1_2 .I1 (norm_cmd_l[2]), .I2 (norm_cmd_l[3]), .I3 (norm_cmd_l[4]), - .I4 (_N97094)); + .I4 (_N97861)); // LUT = (I0&~I1&~I2&~I3&I4)|(~I0&~I1&I2&~I3&I4) ; GTP_LUT3 /* N2193_5 */ #( @@ -190734,7 +190475,7 @@ module ipsxb_mcdq_dfi_v1_2 .Z (N2193), .I0 (N150), .I1 (N524), - .I2 (_N96391)); + .I2 (_N97148)); // LUT = (I0)|(I1)|(I2) ; GTP_LUT4 /* N2200 */ #( @@ -190744,7 +190485,7 @@ module ipsxb_mcdq_dfi_v1_2 .I0 (N329), .I1 (N338), .I2 (N549), - .I3 (_N96393)); + .I3 (_N97150)); // defparam N2200_vname.orig_name = N2200; // LUT = (I3)|(~I0&~I1&~I2) ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dfi_v1_2.vp:614 @@ -190752,12 +190493,12 @@ module ipsxb_mcdq_dfi_v1_2 GTP_LUT5 /* N2207_1 */ #( .INIT(32'b00011010000000000000000000000000)) N2207_1 ( - .Z (_N96393), + .Z (_N97150), .I0 (norm_cmd_m[0]), .I1 (norm_cmd_m[6]), .I2 (norm_cmd_m[7]), - .I3 (_N96386), - .I4 (_N96387)); + .I3 (_N97142), + .I4 (_N97143)); // LUT = (I0&~I2&I3&I4)|(~I0&~I1&I2&I3&I4) ; GTP_DFF_PE /* \dcp2dfi_address[0] */ #( @@ -190876,7 +190617,7 @@ module ipsxb_mcdq_dfi_v1_2 \dcp2dfi_address[10] ( .Q (dcp2dfi_address[10]), .CLK (clk), - .D (_N103425), + .D (_N104237), .P (N0)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dfi_v1_2.vp:543 @@ -191040,7 +190781,7 @@ module ipsxb_mcdq_dfi_v1_2 \dcp2dfi_address[25] ( .Q (dcp2dfi_address[25]), .CLK (clk), - .D (_N103423), + .D (_N104235), .P (N0)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dfi_v1_2.vp:607 @@ -191058,23 +190799,23 @@ module ipsxb_mcdq_dfi_v1_2 GTP_LUT4 /* \dcp2dfi_address_ce_mux[10] */ #( .INIT(16'b1111001111100010)) \dcp2dfi_address_ce_mux[10] ( - .Z (_N103425), + .Z (_N104237), .I0 (N150), .I1 (N532), .I2 (dcp2dfi_address[10]), - .I3 (_N107940)); + .I3 (_N108770)); // LUT = (I0&~I1)|(~I1&I3)|(I1&I2) ; GTP_LUT5M /* \dcp2dfi_address_ce_mux[25] */ #( .INIT(32'b10101010101010100100010100010101)) \dcp2dfi_address_ce_mux[25] ( - .Z (_N103423), + .Z (_N104235), .I0 (dcp2dfi_address[25]), .I1 (norm_cmd_m[3]), - .I2 (_N97097), + .I2 (_N97864), .I3 (norm_cmd_m[4]), .I4 (N549), - .ID (_N97181)); + .ID (_N97943)); // LUT = (~ID&~I1&~I3&~I4)|(~ID&I1&I3&~I4)|(~ID&~I2&~I4)|(I0&I4) ; GTP_DFF_CE /* \dcp2dfi_bank[0] */ #( @@ -191190,7 +190931,7 @@ module ipsxb_mcdq_dfi_v1_2 .Q (dcp2dfi_odt_reg[0]), .C (N0), .CLK (clk), - .D (_N103426)); + .D (_N104238)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dfi_v1_2.vp:691 GTP_LUT1 /* \dcp2dfi_odt_reg[0]_inv */ #( @@ -191207,7 +190948,7 @@ module ipsxb_mcdq_dfi_v1_2 .Q (dcp2dfi_odt_reg_1[0]), .C (N0), .CLK (clk), - .D (_N103424)); + .D (_N104236)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_dfi_v1_2.vp:691 GTP_LUT1 /* \dcp2dfi_odt_reg_1[0]_inv */ #( @@ -191220,10 +190961,10 @@ module ipsxb_mcdq_dfi_v1_2 GTP_LUT5M /* \dcp2dfi_odt_reg_1_ce_mux[0] */ #( .INIT(32'b11111111110011011111111011001110)) \dcp2dfi_odt_reg_1_ce_mux[0] ( - .Z (_N103424), - .I0 (_N107946), - .I1 (_N96389), - .I2 (_N96936), + .Z (_N104236), + .I0 (_N108776), + .I1 (_N97146), + .I2 (_N97707), .I3 (N329), .I4 (_N3), .ID (dcp2dfi_odt_reg_1[0])); @@ -191232,12 +190973,12 @@ module ipsxb_mcdq_dfi_v1_2 GTP_LUT5 /* \dcp2dfi_odt_reg_ce_mux[0] */ #( .INIT(32'b11111111111111111010101100000000)) \dcp2dfi_odt_reg_ce_mux[0] ( - .Z (_N103426), + .Z (_N104238), .I0 (N329), .I1 (N366), .I2 (r_bwr_m), .I3 (dcp2dfi_odt_reg[0]), - .I4 (_N96389)); + .I4 (_N97146)); // LUT = (I4)|(I0&I3)|(~I1&~I2&I3) ; GTP_DFF_P /* \dcp2dfi_ras_n[0] */ #( @@ -191824,16 +191565,16 @@ module ipsxb_distributed_fifo_ctr_v1_0_1 wire N17; wire N36; wire [6:0] \N36.co ; - wire _N15168; - wire _N15169; - wire _N15170; - wire _N15171; - wire _N15172; - wire _N15175; - wire _N15176; - wire _N15177; - wire _N15178; - wire _N15179; + wire _N15214; + wire _N15215; + wire _N15216; + wire _N15217; + wire _N15218; + wire _N15221; + wire _N15222; + wire _N15223; + wire _N15224; + wire _N15225; wire [5:0] rgnext; wire [5:0] rwptr2_b; wire [5:0] wgnext; @@ -191846,7 +191587,7 @@ module ipsxb_distributed_fifo_ctr_v1_0_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_1 ( - .COUT (_N15168), + .COUT (_N15214), .Z (N2[0]), .CIN (), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/rvld ), @@ -191866,9 +191607,9 @@ module ipsxb_distributed_fifo_ctr_v1_0_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_2 ( - .COUT (_N15169), + .COUT (_N15215), .Z (N2[1]), - .CIN (_N15168), + .CIN (_N15214), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/rvld ), .I1 (wr_addr[0]), .I2 (wfull), @@ -191886,9 +191627,9 @@ module ipsxb_distributed_fifo_ctr_v1_0_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_3 ( - .COUT (_N15170), + .COUT (_N15216), .Z (N2[2]), - .CIN (_N15169), + .CIN (_N15215), .I0 (), .I1 (wr_addr[2]), .I2 (), @@ -191906,9 +191647,9 @@ module ipsxb_distributed_fifo_ctr_v1_0_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_4 ( - .COUT (_N15171), + .COUT (_N15217), .Z (N2[3]), - .CIN (_N15170), + .CIN (_N15216), .I0 (), .I1 (wr_addr[3]), .I2 (), @@ -191926,9 +191667,9 @@ module ipsxb_distributed_fifo_ctr_v1_0_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_5 ( - .COUT (_N15172), + .COUT (_N15218), .Z (N2[4]), - .CIN (_N15171), + .CIN (_N15217), .I0 (), .I1 (rwptr2_b[4]), .I2 (), @@ -191948,7 +191689,7 @@ module ipsxb_distributed_fifo_ctr_v1_0_1 N2_6 ( .COUT (), .Z (N2[5]), - .CIN (_N15172), + .CIN (_N15218), .I0 (), .I1 (rwptr2_b[5]), .I2 (), @@ -192026,7 +191767,7 @@ module ipsxb_distributed_fifo_ctr_v1_0_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N9_1 ( - .COUT (_N15175), + .COUT (_N15221), .Z (N9[0]), .CIN (), .I0 (r_en), @@ -192046,9 +191787,9 @@ module ipsxb_distributed_fifo_ctr_v1_0_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N9_2 ( - .COUT (_N15176), + .COUT (_N15222), .Z (N9[1]), - .CIN (_N15175), + .CIN (_N15221), .I0 (r_en), .I1 (rd_addr[0]), .I2 (rd_addr[1]), @@ -192066,9 +191807,9 @@ module ipsxb_distributed_fifo_ctr_v1_0_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N9_3 ( - .COUT (_N15177), + .COUT (_N15223), .Z (N9[2]), - .CIN (_N15176), + .CIN (_N15222), .I0 (), .I1 (rd_addr[2]), .I2 (), @@ -192086,9 +191827,9 @@ module ipsxb_distributed_fifo_ctr_v1_0_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N9_4 ( - .COUT (_N15178), + .COUT (_N15224), .Z (N9[3]), - .CIN (_N15177), + .CIN (_N15223), .I0 (), .I1 (rd_addr[3]), .I2 (), @@ -192106,9 +191847,9 @@ module ipsxb_distributed_fifo_ctr_v1_0_1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N9_5 ( - .COUT (_N15179), + .COUT (_N15225), .Z (N9[4]), - .CIN (_N15178), + .CIN (_N15224), .I0 (), .I1 (wrptr2_b[4]), .I2 (), @@ -192128,7 +191869,7 @@ module ipsxb_distributed_fifo_ctr_v1_0_1 N9_6 ( .COUT (), .Z (N9[5]), - .CIN (_N15179), + .CIN (_N15225), .I0 (), .I1 (wrptr2_b[5]), .I2 (), @@ -192597,7 +192338,7 @@ module ipsxb_mcdq_prefetch_fifo_v1_2 output [4:0] data_out ); wire N3_1; - wire _N103427; + wire _N104239; wire data_out_valid; wire empty; wire full; @@ -192643,13 +192384,13 @@ module ipsxb_mcdq_prefetch_fifo_v1_2 .Q (data_out_valid), .C (rst), .CLK (clk), - .D (_N103427)); + .D (_N104239)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_prefetch_fifo_v1_2.vp:138 GTP_LUT4 /* fifo_vld_ce_mux */ #( .INIT(16'b0111000011111111)) fifo_vld_ce_mux ( - .Z (_N103427), + .Z (_N104239), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/calib_done ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/read_valid ), .I2 (data_out_valid), @@ -192768,68 +192509,67 @@ module ipsxb_mcdq_reg_fifo2_v1_2 wire N6; wire N10; wire N14; - wire _N70708; - wire _N70736; - wire _N70773; - wire _N70815; - wire _N70856; - wire _N70916; - wire _N70941; - wire _N71015; - wire _N71090; - wire _N71119; - wire _N71149; - wire _N71219; - wire _N71285; - wire _N71418; - wire _N71485; - wire _N71732; - wire _N71783; + wire _N71663; + wire _N71684; + wire _N71711; + wire _N71742; + wire _N71799; + wire _N71831; wire _N71861; - wire _N71876; - wire _N72051; - wire _N72139; - wire _N72326; - wire _N72421; - wire _N72463; - wire _N72524; - wire _N72572; - wire _N72617; - wire _N72646; - wire _N72691; - wire _N72723; - wire _N72762; - wire _N72799; - wire _N72834; - wire _N72889; - wire _N72951; - wire _N73006; - wire _N73067; - wire _N73134; - wire _N73194; - wire _N73253; - wire _N73324; - wire _N73383; - wire _N73446; - wire _N73510; - wire _N73574; - wire _N73640; + wire _N71931; + wire _N71997; + wire _N72130; + wire _N72197; + wire _N72444; + wire _N72495; + wire _N72573; + wire _N72588; + wire _N72763; + wire _N72851; + wire _N73038; + wire _N73133; + wire _N73175; + wire _N73236; + wire _N73284; + wire _N73329; + wire _N73426; + wire _N73437; + wire _N73588; + wire _N73630; + wire _N73670; wire _N73702; - wire _N73768; - wire _N73827; - wire _N73892; - wire _N73958; - wire _N74021; - wire _N74085; - wire _N74148; - wire _N74208; - wire _N74272; - wire _N74340; - wire _N74398; - wire _N74463; - wire _N74527; - wire _N103431; - wire _N103432; + wire _N73735; + wire _N73772; + wire _N73809; + wire _N73872; + wire _N73937; + wire _N73999; + wire _N74056; + wire _N74121; + wire _N74185; + wire _N74242; + wire _N74299; + wire _N74353; + wire _N74417; + wire _N74486; + wire _N74545; + wire _N74607; + wire _N74667; + wire _N74731; + wire _N74796; + wire _N74857; + wire _N74921; + wire _N74984; + wire _N75044; + wire _N75111; + wire _N75173; + wire _N75242; + wire _N75306; + wire _N75363; + wire _N75429; + wire _N75496; + wire _N104243; + wire _N104244; wire \u_axi_ddr_top/s_axi_arvalid_inv ; GTP_LUT1 /* N6 */ #( @@ -193154,7 +192894,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N10), .CLK (clk), - .D (_N70708)); + .D (_N71663)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:126 GTP_DFF_CE /* \data_0[4] */ #( @@ -193165,7 +192905,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N10), .CLK (clk), - .D (_N70736)); + .D (_N71684)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:126 GTP_DFF_CE /* \data_0[5] */ #( @@ -193176,7 +192916,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N10), .CLK (clk), - .D (_N70773)); + .D (_N71711)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:126 GTP_DFF_CE /* \data_0[6] */ #( @@ -193187,7 +192927,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N10), .CLK (clk), - .D (_N70815)); + .D (_N71742)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:126 GTP_DFF_CE /* \data_0[7] */ #( @@ -193198,7 +192938,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N10), .CLK (clk), - .D (_N70856)); + .D (_N71799)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:126 GTP_DFF_CE /* \data_0[8] */ #( @@ -193209,7 +192949,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N10), .CLK (clk), - .D (_N70916)); + .D (_N71831)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:126 GTP_DFF_CE /* \data_0[9] */ #( @@ -193220,7 +192960,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N10), .CLK (clk), - .D (_N70941)); + .D (_N71861)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:126 GTP_DFF_CE /* \data_0[10] */ #( @@ -193231,7 +192971,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N10), .CLK (clk), - .D (_N71015)); + .D (_N71931)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:126 GTP_DFF_CE /* \data_0[11] */ #( @@ -193242,7 +192982,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N10), .CLK (clk), - .D (_N71090)); + .D (_N71997)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:126 GTP_DFF_CE /* \data_0[12] */ #( @@ -193253,7 +192993,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N10), .CLK (clk), - .D (_N71119)); + .D (data_in[12])); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:126 GTP_DFF_CE /* \data_0[13] */ #( @@ -193264,7 +193004,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N10), .CLK (clk), - .D (_N71149)); + .D (_N72130)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:126 GTP_DFF_CE /* \data_0[14] */ #( @@ -193275,7 +193015,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N10), .CLK (clk), - .D (_N71219)); + .D (_N72197)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:126 GTP_DFF_CE /* \data_0[15] */ #( @@ -193286,7 +193026,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N10), .CLK (clk), - .D (_N71285)); + .D (data_in[15])); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:126 GTP_DFF_CE /* \data_0[16] */ #( @@ -193308,7 +193048,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N10), .CLK (clk), - .D (_N71418)); + .D (_N72444)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:126 GTP_DFF_CE /* \data_0[18] */ #( @@ -193319,7 +193059,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N10), .CLK (clk), - .D (_N71485)); + .D (_N72495)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:126 GTP_DFF_CE /* \data_0[19] */ #( @@ -193330,7 +193070,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N10), .CLK (clk), - .D (data_in[19])); + .D (_N72573)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:126 GTP_DFF_CE /* \data_0[20] */ #( @@ -193341,7 +193081,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N10), .CLK (clk), - .D (data_in[20])); + .D (_N72588)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:126 GTP_DFF_CE /* \data_0[21] */ #( @@ -193352,7 +193092,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N10), .CLK (clk), - .D (_N71732)); + .D (data_in[21])); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:126 GTP_DFF_CE /* \data_0[22] */ #( @@ -193363,7 +193103,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N10), .CLK (clk), - .D (_N71783)); + .D (_N72763)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:126 GTP_DFF_CE /* \data_0[23] */ #( @@ -193374,7 +193114,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N10), .CLK (clk), - .D (_N71861)); + .D (_N72851)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:126 GTP_DFF_CE /* \data_0[24] */ #( @@ -193385,7 +193125,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N10), .CLK (clk), - .D (_N71876)); + .D (data_in[24])); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:126 GTP_DFF_CE /* \data_0[25] */ #( @@ -193407,7 +193147,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N10), .CLK (clk), - .D (_N72051)); + .D (_N73038)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:126 GTP_DFF_CE /* \data_0[27] */ #( @@ -193418,7 +193158,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N10), .CLK (clk), - .D (_N72139)); + .D (_N73133)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:126 GTP_DFF_CE /* \data_0[28] */ #( @@ -193429,7 +193169,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N10), .CLK (clk), - .D (data_in[28])); + .D (_N73175)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:126 GTP_DFF_CE /* \data_0[29] */ #( @@ -193440,7 +193180,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N10), .CLK (clk), - .D (data_in[29])); + .D (_N73236)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:126 GTP_DFF_CE /* \data_0[30] */ #( @@ -193451,7 +193191,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N10), .CLK (clk), - .D (_N72326)); + .D (_N73284)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:126 GTP_DFF_CE /* \data_0[31] */ #( @@ -193462,7 +193202,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N10), .CLK (clk), - .D (_N72421)); + .D (_N73329)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:126 GTP_DFF_CE /* \data_0[32] */ #( @@ -193473,7 +193213,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N10), .CLK (clk), - .D (_N72463)); + .D (_N73426)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:126 GTP_DFF_CE /* \data_0[33] */ #( @@ -193484,7 +193224,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N10), .CLK (clk), - .D (_N72524)); + .D (_N73437)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:126 GTP_DFF_CE /* \data_0[34] */ #( @@ -193495,7 +193235,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N10), .CLK (clk), - .D (_N72572)); + .D (data_in[34])); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:126 GTP_DFF_CE /* \data_0[35] */ #( @@ -193506,13 +193246,13 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N10), .CLK (clk), - .D (_N72617)); + .D (_N73588)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:126 GTP_LUT2 /* \data_0[37:0]_0 */ #( .INIT(4'b1110)) \data_0[37:0]_0 ( - .Z (_N70708), + .Z (_N71663), .I0 (\u_axi_ddr_top/s_axi_awvalid ), .I1 (\u_axi_ddr_top/s_axi_arlen [0] )); // LUT = (I0)|(I1) ; @@ -193520,7 +193260,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 GTP_LUT2 /* \data_0[37:0]_5 */ #( .INIT(4'b1000)) \data_0[37:0]_5 ( - .Z (_N70916), + .Z (_N71831), .I0 (\u_axi_ddr_top/s_axi_awvalid ), .I1 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [2] )); // LUT = I0&I1 ; @@ -193528,7 +193268,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 GTP_LUT2 /* \data_0[37:0]_6 */ #( .INIT(4'b1000)) \data_0[37:0]_6 ( - .Z (_N70941), + .Z (_N71861), .I0 (\u_axi_ddr_top/s_axi_awvalid ), .I1 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [3] )); // LUT = I0&I1 ; @@ -193536,7 +193276,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 GTP_LUT2 /* \data_0[37:0]_7 */ #( .INIT(4'b1000)) \data_0[37:0]_7 ( - .Z (_N71015), + .Z (_N71931), .I0 (\u_axi_ddr_top/s_axi_awvalid ), .I1 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [4] )); // LUT = I0&I1 ; @@ -193544,7 +193284,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 GTP_LUT3 /* \data_0[37:0]_8 */ #( .INIT(8'b11011000)) \data_0[37:0]_8 ( - .Z (_N71090), + .Z (_N71997), .I0 (\u_axi_ddr_top/s_axi_awvalid ), .I1 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [5] ), .I2 (\u_axi_ddr_top/s_axi_araddr [5] )); @@ -193553,193 +193293,184 @@ module ipsxb_mcdq_reg_fifo2_v1_2 GTP_LUT3 /* \data_0[37:0]_9 */ #( .INIT(8'b11011000)) \data_0[37:0]_9 ( - .Z (_N71119), - .I0 (\u_axi_ddr_top/s_axi_awvalid ), - .I1 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [6] ), - .I2 (\u_axi_ddr_top/s_axi_araddr [6] )); - // LUT = (~I0&I2)|(I0&I1) ; - - GTP_LUT3 /* \data_0[37:0]_10 */ #( - .INIT(8'b11011000)) - \data_0[37:0]_10 ( - .Z (_N71149), + .Z (_N72130), .I0 (\u_axi_ddr_top/s_axi_awvalid ), .I1 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [7] ), .I2 (\u_axi_ddr_top/s_axi_araddr [7] )); // LUT = (~I0&I2)|(I0&I1) ; - GTP_LUT3 /* \data_0[37:0]_207 */ #( + GTP_LUT3 /* \data_0[37:0]_10 */ #( .INIT(8'b11011000)) - \data_0[37:0]_207 ( - .Z (_N71219), + \data_0[37:0]_10 ( + .Z (_N72197), .I0 (\u_axi_ddr_top/s_axi_awvalid ), .I1 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [8] ), .I2 (\u_axi_ddr_top/s_axi_araddr [8] )); // LUT = (~I0&I2)|(I0&I1) ; - GTP_LUT3 /* \data_0[37:0]_267 */ #( + GTP_LUT3 /* \data_0[37:0]_446 */ #( .INIT(8'b11011000)) - \data_0[37:0]_267 ( - .Z (_N71285), - .I0 (\u_axi_ddr_top/s_axi_awvalid ), - .I1 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [9] ), - .I2 (\u_axi_ddr_top/s_axi_araddr [9] )); - // LUT = (~I0&I2)|(I0&I1) ; - - GTP_LUT3 /* \data_0[37:0]_382 */ #( - .INIT(8'b11011000)) - \data_0[37:0]_382 ( - .Z (_N71418), + \data_0[37:0]_446 ( + .Z (_N72444), .I0 (\u_axi_ddr_top/s_axi_awvalid ), .I1 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [11] ), .I2 (\u_axi_ddr_top/s_axi_araddr [11] )); // LUT = (~I0&I2)|(I0&I1) ; - GTP_LUT3 /* \data_0[37:0]_440 */ #( + GTP_LUT3 /* \data_0[37:0]_491 */ #( .INIT(8'b11011000)) - \data_0[37:0]_440 ( - .Z (_N71485), + \data_0[37:0]_491 ( + .Z (_N72495), .I0 (\u_axi_ddr_top/s_axi_awvalid ), .I1 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [12] ), .I2 (\u_axi_ddr_top/s_axi_araddr [12] )); // LUT = (~I0&I2)|(I0&I1) ; - GTP_LUT3 /* \data_0[37:0]_655 */ #( + GTP_LUT3 /* \data_0[37:0]_557 */ #( .INIT(8'b11011000)) - \data_0[37:0]_655 ( - .Z (_N71732), + \data_0[37:0]_557 ( + .Z (_N72573), .I0 (\u_axi_ddr_top/s_axi_awvalid ), - .I1 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [15] ), - .I2 (\u_axi_ddr_top/s_axi_araddr [15] )); + .I1 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [13] ), + .I2 (\u_axi_ddr_top/s_axi_araddr [13] )); // LUT = (~I0&I2)|(I0&I1) ; - GTP_LUT3 /* \data_0[37:0]_700 */ #( + GTP_LUT3 /* \data_0[37:0]_571 */ #( .INIT(8'b11011000)) - \data_0[37:0]_700 ( - .Z (_N71783), + \data_0[37:0]_571 ( + .Z (_N72588), .I0 (\u_axi_ddr_top/s_axi_awvalid ), - .I1 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [16] ), - .I2 (\u_axi_ddr_top/s_axi_araddr [16] )); + .I1 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [14] ), + .I2 (\u_axi_ddr_top/s_axi_araddr [14] )); // LUT = (~I0&I2)|(I0&I1) ; - GTP_LUT3 /* \data_0[37:0]_766 */ #( + GTP_LUT3 /* \data_0[37:0]_724 */ #( .INIT(8'b11011000)) - \data_0[37:0]_766 ( - .Z (_N71861), + \data_0[37:0]_724 ( + .Z (_N72763), .I0 (\u_axi_ddr_top/s_axi_awvalid ), - .I1 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [17] ), - .I2 (\u_axi_ddr_top/s_axi_araddr [17] )); + .I1 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [16] ), + .I2 (\u_axi_ddr_top/s_axi_araddr [16] )); // LUT = (~I0&I2)|(I0&I1) ; - GTP_LUT3 /* \data_0[37:0]_780 */ #( + GTP_LUT3 /* \data_0[37:0]_799 */ #( .INIT(8'b11011000)) - \data_0[37:0]_780 ( - .Z (_N71876), + \data_0[37:0]_799 ( + .Z (_N72851), .I0 (\u_axi_ddr_top/s_axi_awvalid ), - .I1 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [18] ), - .I2 (\u_axi_ddr_top/s_axi_araddr [18] )); + .I1 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [17] ), + .I2 (\u_axi_ddr_top/s_axi_araddr [17] )); // LUT = (~I0&I2)|(I0&I1) ; - GTP_LUT3 /* \data_0[37:0]_933 */ #( + GTP_LUT3 /* \data_0[37:0]_960 */ #( .INIT(8'b11011000)) - \data_0[37:0]_933 ( - .Z (_N72051), + \data_0[37:0]_960 ( + .Z (_N73038), .I0 (\u_axi_ddr_top/s_axi_awvalid ), .I1 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [20] ), .I2 (\u_axi_ddr_top/s_axi_araddr [20] )); // LUT = (~I0&I2)|(I0&I1) ; - GTP_LUT3 /* \data_0[37:0]_1008 */ #( + GTP_LUT3 /* \data_0[37:0]_1044 */ #( .INIT(8'b11011000)) - \data_0[37:0]_1008 ( - .Z (_N72139), + \data_0[37:0]_1044 ( + .Z (_N73133), .I0 (\u_axi_ddr_top/s_axi_awvalid ), .I1 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [21] ), .I2 (\u_axi_ddr_top/s_axi_araddr [21] )); // LUT = (~I0&I2)|(I0&I1) ; - GTP_LUT3 /* \data_0[37:0]_1169 */ #( + GTP_LUT3 /* \data_0[37:0]_1080 */ #( + .INIT(8'b11011000)) + \data_0[37:0]_1080 ( + .Z (_N73175), + .I0 (\u_axi_ddr_top/s_axi_awvalid ), + .I1 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [22] ), + .I2 (\u_axi_ddr_top/s_axi_araddr [22] )); + // LUT = (~I0&I2)|(I0&I1) ; + + GTP_LUT3 /* \data_0[37:0]_1133 */ #( + .INIT(8'b11011000)) + \data_0[37:0]_1133 ( + .Z (_N73236), + .I0 (\u_axi_ddr_top/s_axi_awvalid ), + .I1 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [23] ), + .I2 (\u_axi_ddr_top/s_axi_araddr [23] )); + // LUT = (~I0&I2)|(I0&I1) ; + + GTP_LUT3 /* \data_0[37:0]_1174 */ #( .INIT(8'b11011000)) - \data_0[37:0]_1169 ( - .Z (_N72326), + \data_0[37:0]_1174 ( + .Z (_N73284), .I0 (\u_axi_ddr_top/s_axi_awvalid ), .I1 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [24] ), .I2 (\u_axi_ddr_top/s_axi_araddr [24] )); // LUT = (~I0&I2)|(I0&I1) ; - GTP_LUT3 /* \data_0[37:0]_1253 */ #( + GTP_LUT3 /* \data_0[37:0]_1213 */ #( .INIT(8'b11011000)) - \data_0[37:0]_1253 ( - .Z (_N72421), + \data_0[37:0]_1213 ( + .Z (_N73329), .I0 (\u_axi_ddr_top/s_axi_awvalid ), .I1 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [25] ), .I2 (\u_axi_ddr_top/s_axi_araddr [25] )); // LUT = (~I0&I2)|(I0&I1) ; - GTP_LUT3 /* \data_0[37:0]_1289 */ #( + GTP_LUT3 /* \data_0[37:0]_1298 */ #( .INIT(8'b11011000)) - \data_0[37:0]_1289 ( - .Z (_N72463), + \data_0[37:0]_1298 ( + .Z (_N73426), .I0 (\u_axi_ddr_top/s_axi_awvalid ), .I1 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [26] ), .I2 (\u_axi_ddr_top/s_axi_araddr [26] )); // LUT = (~I0&I2)|(I0&I1) ; - GTP_LUT3 /* \data_0[37:0]_1342 */ #( + GTP_LUT3 /* \data_0[37:0]_1308 */ #( .INIT(8'b11011000)) - \data_0[37:0]_1342 ( - .Z (_N72524), + \data_0[37:0]_1308 ( + .Z (_N73437), .I0 (\u_axi_ddr_top/s_axi_awvalid ), .I1 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [27] ), .I2 (\u_axi_ddr_top/s_axi_araddr [27] )); // LUT = (~I0&I2)|(I0&I1) ; - GTP_LUT3 /* \data_0[37:0]_1383 */ #( - .INIT(8'b11011000)) - \data_0[37:0]_1383 ( - .Z (_N72572), - .I0 (\u_axi_ddr_top/s_axi_awvalid ), - .I1 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [28] ), - .I2 (\u_axi_ddr_top/s_axi_araddr [28] )); - // LUT = (~I0&I2)|(I0&I1) ; - - GTP_LUT3 /* \data_0[37:0]_1422 */ #( + GTP_LUT3 /* \data_0[37:0]_1440 */ #( .INIT(8'b11011000)) - \data_0[37:0]_1422 ( - .Z (_N72617), + \data_0[37:0]_1440 ( + .Z (_N73588), .I0 (\u_axi_ddr_top/s_axi_awvalid ), .I1 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [29] ), .I2 (\u_axi_ddr_top/s_axi_araddr [29] )); // LUT = (~I0&I2)|(I0&I1) ; - GTP_LUT2 /* \data_0[37:0]_4426 */ #( + GTP_LUT2 /* \data_0[37:0]_4446 */ #( .INIT(4'b0100)) - \data_0[37:0]_4426 ( - .Z (_N70736), + \data_0[37:0]_4446 ( + .Z (_N71684), .I0 (\u_axi_ddr_top/s_axi_awvalid ), .I1 (\u_axi_ddr_top/s_axi_arid [0] )); // LUT = ~I0&I1 ; - GTP_LUT2 /* \data_0[37:0]_4437 */ #( + GTP_LUT2 /* \data_0[37:0]_4456 */ #( .INIT(4'b0100)) - \data_0[37:0]_4437 ( - .Z (_N70773), + \data_0[37:0]_4456 ( + .Z (_N71711), .I0 (\u_axi_ddr_top/s_axi_awvalid ), .I1 (\u_axi_ddr_top/s_axi_arid [1] )); // LUT = ~I0&I1 ; - GTP_LUT2 /* \data_0[37:0]_4449 */ #( + GTP_LUT2 /* \data_0[37:0]_4468 */ #( .INIT(4'b0100)) - \data_0[37:0]_4449 ( - .Z (_N70815), + \data_0[37:0]_4468 ( + .Z (_N71742), .I0 (\u_axi_ddr_top/s_axi_awvalid ), .I1 (\u_axi_ddr_top/s_axi_arid [2] )); // LUT = ~I0&I1 ; - GTP_LUT2 /* \data_0[37:0]_4459 */ #( + GTP_LUT2 /* \data_0[37:0]_4484 */ #( .INIT(4'b0100)) - \data_0[37:0]_4459 ( - .Z (_N70856), + \data_0[37:0]_4484 ( + .Z (_N71799), .I0 (\u_axi_ddr_top/s_axi_awvalid ), .I1 (\u_axi_ddr_top/s_axi_arid [3] )); // LUT = ~I0&I1 ; @@ -193763,7 +193494,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N14), .CLK (clk), - .D (_N72646)); + .D (_N73630)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:134 GTP_DFF_CE /* \data_1[4] */ #( @@ -193774,7 +193505,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N14), .CLK (clk), - .D (_N72691)); + .D (_N73670)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:134 GTP_DFF_CE /* \data_1[5] */ #( @@ -193785,7 +193516,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N14), .CLK (clk), - .D (_N72723)); + .D (_N73702)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:134 GTP_DFF_CE /* \data_1[6] */ #( @@ -193796,7 +193527,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N14), .CLK (clk), - .D (_N72762)); + .D (_N73735)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:134 GTP_DFF_CE /* \data_1[7] */ #( @@ -193807,7 +193538,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N14), .CLK (clk), - .D (_N72799)); + .D (_N73772)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:134 GTP_DFF_CE /* \data_1[8] */ #( @@ -193818,7 +193549,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N14), .CLK (clk), - .D (_N72834)); + .D (_N73809)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:134 GTP_DFF_CE /* \data_1[9] */ #( @@ -193829,7 +193560,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N14), .CLK (clk), - .D (_N72889)); + .D (_N73872)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:134 GTP_DFF_CE /* \data_1[10] */ #( @@ -193840,7 +193571,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N14), .CLK (clk), - .D (_N72951)); + .D (_N73937)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:134 GTP_DFF_CE /* \data_1[11] */ #( @@ -193851,7 +193582,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N14), .CLK (clk), - .D (_N73006)); + .D (_N73999)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:134 GTP_DFF_CE /* \data_1[12] */ #( @@ -193862,7 +193593,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N14), .CLK (clk), - .D (_N73067)); + .D (_N74056)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:134 GTP_DFF_CE /* \data_1[13] */ #( @@ -193873,7 +193604,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N14), .CLK (clk), - .D (_N73134)); + .D (_N74121)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:134 GTP_DFF_CE /* \data_1[14] */ #( @@ -193884,7 +193615,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N14), .CLK (clk), - .D (_N73194)); + .D (_N74185)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:134 GTP_DFF_CE /* \data_1[15] */ #( @@ -193895,7 +193626,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N14), .CLK (clk), - .D (_N73253)); + .D (_N74242)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:134 GTP_DFF_CE /* \data_1[16] */ #( @@ -193906,7 +193637,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N14), .CLK (clk), - .D (_N73324)); + .D (_N74299)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:134 GTP_DFF_CE /* \data_1[17] */ #( @@ -193917,7 +193648,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N14), .CLK (clk), - .D (_N73383)); + .D (_N74353)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:134 GTP_DFF_CE /* \data_1[18] */ #( @@ -193928,7 +193659,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N14), .CLK (clk), - .D (_N73446)); + .D (_N74417)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:134 GTP_DFF_CE /* \data_1[19] */ #( @@ -193939,7 +193670,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N14), .CLK (clk), - .D (_N73510)); + .D (_N74486)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:134 GTP_DFF_CE /* \data_1[20] */ #( @@ -193950,7 +193681,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N14), .CLK (clk), - .D (_N73574)); + .D (_N74545)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:134 GTP_DFF_CE /* \data_1[21] */ #( @@ -193961,7 +193692,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N14), .CLK (clk), - .D (_N73640)); + .D (_N74607)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:134 GTP_DFF_CE /* \data_1[22] */ #( @@ -193972,7 +193703,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N14), .CLK (clk), - .D (_N73702)); + .D (_N74667)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:134 GTP_DFF_CE /* \data_1[23] */ #( @@ -193983,7 +193714,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N14), .CLK (clk), - .D (_N73768)); + .D (_N74731)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:134 GTP_DFF_CE /* \data_1[24] */ #( @@ -193994,7 +193725,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N14), .CLK (clk), - .D (_N73827)); + .D (_N74796)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:134 GTP_DFF_CE /* \data_1[25] */ #( @@ -194005,7 +193736,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N14), .CLK (clk), - .D (_N73892)); + .D (_N74857)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:134 GTP_DFF_CE /* \data_1[26] */ #( @@ -194016,7 +193747,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N14), .CLK (clk), - .D (_N73958)); + .D (_N74921)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:134 GTP_DFF_CE /* \data_1[27] */ #( @@ -194027,7 +193758,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N14), .CLK (clk), - .D (_N74021)); + .D (_N74984)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:134 GTP_DFF_CE /* \data_1[28] */ #( @@ -194038,7 +193769,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N14), .CLK (clk), - .D (_N74085)); + .D (_N75044)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:134 GTP_DFF_CE /* \data_1[29] */ #( @@ -194049,7 +193780,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N14), .CLK (clk), - .D (_N74148)); + .D (_N75111)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:134 GTP_DFF_CE /* \data_1[30] */ #( @@ -194060,7 +193791,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N14), .CLK (clk), - .D (_N74208)); + .D (_N75173)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:134 GTP_DFF_CE /* \data_1[31] */ #( @@ -194071,7 +193802,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N14), .CLK (clk), - .D (_N74272)); + .D (_N75242)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:134 GTP_DFF_CE /* \data_1[32] */ #( @@ -194082,7 +193813,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N14), .CLK (clk), - .D (_N74340)); + .D (_N75306)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:134 GTP_DFF_CE /* \data_1[33] */ #( @@ -194093,7 +193824,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N14), .CLK (clk), - .D (_N74398)); + .D (_N75363)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:134 GTP_DFF_CE /* \data_1[34] */ #( @@ -194104,7 +193835,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N14), .CLK (clk), - .D (_N74463)); + .D (_N75429)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:134 GTP_DFF_CE /* \data_1[35] */ #( @@ -194115,13 +193846,13 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .C (N2), .CE (N14), .CLK (clk), - .D (_N74527)); + .D (_N75496)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:134 GTP_LUT4 /* \data_1[37:0]_0 */ #( .INIT(16'b1111111100000001)) \data_1[37:0]_0 ( - .Z (_N72646), + .Z (_N73630), .I0 (\u_axi_ddr_top/rd_sta [1] ), .I1 (\u_axi_ddr_top/rd_sta [3] ), .I2 (\u_axi_ddr_top/rd_sta [7] ), @@ -194140,7 +193871,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 GTP_LUT4 /* \data_1[37:0]_3 */ #( .INIT(16'b1111111000000000)) \data_1[37:0]_3 ( - .Z (_N72691), + .Z (_N73670), .I0 (\u_axi_ddr_top/rd_sta [1] ), .I1 (\u_axi_ddr_top/rd_sta [3] ), .I2 (\u_axi_ddr_top/rd_sta [7] ), @@ -194150,7 +193881,7 @@ module ipsxb_mcdq_reg_fifo2_v1_2 GTP_LUT4 /* \data_1[37:0]_6 */ #( .INIT(16'b1111111000000000)) \data_1[37:0]_6 ( - .Z (_N72723), + .Z (_N73702), .I0 (\u_axi_ddr_top/rd_sta [1] ), .I1 (\u_axi_ddr_top/rd_sta [3] ), .I2 (\u_axi_ddr_top/rd_sta [7] ), @@ -194160,234 +193891,244 @@ module ipsxb_mcdq_reg_fifo2_v1_2 GTP_LUT4 /* \data_1[37:0]_9 */ #( .INIT(16'b1111111000000000)) \data_1[37:0]_9 ( - .Z (_N72762), + .Z (_N73735), .I0 (\u_axi_ddr_top/rd_sta [1] ), .I1 (\u_axi_ddr_top/rd_sta [3] ), .I2 (\u_axi_ddr_top/rd_sta [7] ), .I3 (\u_axi_ddr_top/s_axi_arid [2] )); // LUT = (I0&I3)|(I1&I3)|(I2&I3) ; - GTP_LUT4 /* \data_1[37:0]_74 */ #( + GTP_LUT4 /* \data_1[37:0]_68 */ #( .INIT(16'b1111111000000000)) - \data_1[37:0]_74 ( - .Z (_N72799), + \data_1[37:0]_68 ( + .Z (_N73772), .I0 (\u_axi_ddr_top/rd_sta [1] ), .I1 (\u_axi_ddr_top/rd_sta [3] ), .I2 (\u_axi_ddr_top/rd_sta [7] ), .I3 (\u_axi_ddr_top/s_axi_arid [3] )); // LUT = (I0&I3)|(I1&I3)|(I2&I3) ; - GTP_LUT5 /* \data_1[37:0]_1678 */ #( + GTP_LUT5 /* \data_1[37:0]_1668 */ #( .INIT(32'b11111111111111100000000000000010)) - \data_1[37:0]_1678 ( - .Z (_N73324), - .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [10] ), + \data_1[37:0]_1668 ( + .Z (_N75044), + .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [22] ), .I1 (\u_axi_ddr_top/rd_sta [1] ), .I2 (\u_axi_ddr_top/rd_sta [3] ), .I3 (\u_axi_ddr_top/rd_sta [7] ), - .I4 (\u_axi_ddr_top/s_axi_araddr [10] )); + .I4 (\u_axi_ddr_top/s_axi_araddr [22] )); // LUT = (I1&I4)|(I2&I4)|(I3&I4)|(I0&~I1&~I2&~I3) ; - GTP_LUT4 /* \data_1[37:0]_1679 */ #( + GTP_LUT5 /* \data_1[37:0]_1669 */ #( + .INIT(32'b11111111111111100000000000000010)) + \data_1[37:0]_1669 ( + .Z (_N74984), + .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [21] ), + .I1 (\u_axi_ddr_top/rd_sta [1] ), + .I2 (\u_axi_ddr_top/rd_sta [3] ), + .I3 (\u_axi_ddr_top/rd_sta [7] ), + .I4 (\u_axi_ddr_top/s_axi_araddr [21] )); + // LUT = (I1&I4)|(I2&I4)|(I3&I4)|(I0&~I1&~I2&~I3) ; + + GTP_LUT4 /* \data_1[37:0]_1670 */ #( .INIT(16'b0000000000000010)) - \data_1[37:0]_1679 ( - .Z (_N72889), - .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [3] ), + \data_1[37:0]_1670 ( + .Z (_N73937), + .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [4] ), .I1 (\u_axi_ddr_top/rd_sta [1] ), .I2 (\u_axi_ddr_top/rd_sta [3] ), .I3 (\u_axi_ddr_top/rd_sta [7] )); // LUT = I0&~I1&~I2&~I3 ; - GTP_LUT5 /* \data_1[37:0]_1680 */ #( + GTP_LUT5 /* \data_1[37:0]_1671 */ #( .INIT(32'b11111111111111100000000000000010)) - \data_1[37:0]_1680 ( - .Z (_N74527), - .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [29] ), + \data_1[37:0]_1671 ( + .Z (_N74056), + .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [6] ), .I1 (\u_axi_ddr_top/rd_sta [1] ), .I2 (\u_axi_ddr_top/rd_sta [3] ), .I3 (\u_axi_ddr_top/rd_sta [7] ), - .I4 (\u_axi_ddr_top/s_axi_araddr [29] )); + .I4 (\u_axi_ddr_top/s_axi_araddr [6] )); // LUT = (I1&I4)|(I2&I4)|(I3&I4)|(I0&~I1&~I2&~I3) ; - GTP_LUT5 /* \data_1[37:0]_1681 */ #( - .INIT(32'b11111111111111100000000000000010)) - \data_1[37:0]_1681 ( - .Z (_N74398), - .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [27] ), + GTP_LUT4 /* \data_1[37:0]_1672 */ #( + .INIT(16'b0000000000000010)) + \data_1[37:0]_1672 ( + .Z (_N73872), + .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [3] ), .I1 (\u_axi_ddr_top/rd_sta [1] ), .I2 (\u_axi_ddr_top/rd_sta [3] ), - .I3 (\u_axi_ddr_top/rd_sta [7] ), - .I4 (\u_axi_ddr_top/s_axi_araddr [27] )); - // LUT = (I1&I4)|(I2&I4)|(I3&I4)|(I0&~I1&~I2&~I3) ; + .I3 (\u_axi_ddr_top/rd_sta [7] )); + // LUT = I0&~I1&~I2&~I3 ; - GTP_LUT5 /* \data_1[37:0]_1682 */ #( + GTP_LUT5 /* \data_1[37:0]_1673 */ #( .INIT(32'b11111111111111100000000000000010)) - \data_1[37:0]_1682 ( - .Z (_N73383), - .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [11] ), + \data_1[37:0]_1673 ( + .Z (_N73999), + .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [5] ), .I1 (\u_axi_ddr_top/rd_sta [1] ), .I2 (\u_axi_ddr_top/rd_sta [3] ), .I3 (\u_axi_ddr_top/rd_sta [7] ), - .I4 (\u_axi_ddr_top/s_axi_araddr [11] )); + .I4 (\u_axi_ddr_top/s_axi_araddr [5] )); // LUT = (I1&I4)|(I2&I4)|(I3&I4)|(I0&~I1&~I2&~I3) ; - GTP_LUT5 /* \data_1[37:0]_1683 */ #( + GTP_LUT5 /* \data_1[37:0]_1674 */ #( .INIT(32'b11111111111111100000000000000010)) - \data_1[37:0]_1683 ( - .Z (_N73892), - .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [19] ), + \data_1[37:0]_1674 ( + .Z (_N74667), + .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [16] ), .I1 (\u_axi_ddr_top/rd_sta [1] ), .I2 (\u_axi_ddr_top/rd_sta [3] ), .I3 (\u_axi_ddr_top/rd_sta [7] ), - .I4 (\u_axi_ddr_top/s_axi_araddr [19] )); + .I4 (\u_axi_ddr_top/s_axi_araddr [16] )); // LUT = (I1&I4)|(I2&I4)|(I3&I4)|(I0&~I1&~I2&~I3) ; - GTP_LUT5 /* \data_1[37:0]_1684 */ #( + GTP_LUT5 /* \data_1[37:0]_1675 */ #( .INIT(32'b11111111111111100000000000000010)) - \data_1[37:0]_1684 ( - .Z (_N74148), - .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [23] ), + \data_1[37:0]_1675 ( + .Z (_N74607), + .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [15] ), .I1 (\u_axi_ddr_top/rd_sta [1] ), .I2 (\u_axi_ddr_top/rd_sta [3] ), .I3 (\u_axi_ddr_top/rd_sta [7] ), - .I4 (\u_axi_ddr_top/s_axi_araddr [23] )); + .I4 (\u_axi_ddr_top/s_axi_araddr [15] )); // LUT = (I1&I4)|(I2&I4)|(I3&I4)|(I0&~I1&~I2&~I3) ; - GTP_LUT5 /* \data_1[37:0]_1685 */ #( + GTP_LUT5 /* \data_1[37:0]_1676 */ #( .INIT(32'b11111111111111100000000000000010)) - \data_1[37:0]_1685 ( - .Z (_N73067), - .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [6] ), + \data_1[37:0]_1676 ( + .Z (_N74857), + .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [19] ), .I1 (\u_axi_ddr_top/rd_sta [1] ), .I2 (\u_axi_ddr_top/rd_sta [3] ), .I3 (\u_axi_ddr_top/rd_sta [7] ), - .I4 (\u_axi_ddr_top/s_axi_araddr [6] )); + .I4 (\u_axi_ddr_top/s_axi_araddr [19] )); // LUT = (I1&I4)|(I2&I4)|(I3&I4)|(I0&~I1&~I2&~I3) ; - GTP_LUT4 /* \data_1[37:0]_1686 */ #( - .INIT(16'b0000000000000010)) - \data_1[37:0]_1686 ( - .Z (_N72834), - .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [2] ), - .I1 (\u_axi_ddr_top/rd_sta [1] ), - .I2 (\u_axi_ddr_top/rd_sta [3] ), - .I3 (\u_axi_ddr_top/rd_sta [7] )); - // LUT = I0&~I1&~I2&~I3 ; - - GTP_LUT5 /* \data_1[37:0]_1687 */ #( + GTP_LUT5 /* \data_1[37:0]_1677 */ #( .INIT(32'b11111111111111100000000000000010)) - \data_1[37:0]_1687 ( - .Z (_N73446), - .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [12] ), + \data_1[37:0]_1677 ( + .Z (_N74486), + .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [13] ), .I1 (\u_axi_ddr_top/rd_sta [1] ), .I2 (\u_axi_ddr_top/rd_sta [3] ), .I3 (\u_axi_ddr_top/rd_sta [7] ), - .I4 (\u_axi_ddr_top/s_axi_araddr [12] )); + .I4 (\u_axi_ddr_top/s_axi_araddr [13] )); // LUT = (I1&I4)|(I2&I4)|(I3&I4)|(I0&~I1&~I2&~I3) ; - GTP_LUT5 /* \data_1[37:0]_1688 */ #( + GTP_LUT5 /* \data_1[37:0]_1678 */ #( .INIT(32'b11111111111111100000000000000010)) - \data_1[37:0]_1688 ( - .Z (_N74021), - .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [21] ), + \data_1[37:0]_1678 ( + .Z (_N74545), + .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [14] ), .I1 (\u_axi_ddr_top/rd_sta [1] ), .I2 (\u_axi_ddr_top/rd_sta [3] ), .I3 (\u_axi_ddr_top/rd_sta [7] ), - .I4 (\u_axi_ddr_top/s_axi_araddr [21] )); + .I4 (\u_axi_ddr_top/s_axi_araddr [14] )); // LUT = (I1&I4)|(I2&I4)|(I3&I4)|(I0&~I1&~I2&~I3) ; - GTP_LUT5 /* \data_1[37:0]_1689 */ #( + GTP_LUT5 /* \data_1[37:0]_1679 */ #( .INIT(32'b11111111111111100000000000000010)) - \data_1[37:0]_1689 ( - .Z (_N73827), - .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [18] ), + \data_1[37:0]_1679 ( + .Z (_N75306), + .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [26] ), .I1 (\u_axi_ddr_top/rd_sta [1] ), .I2 (\u_axi_ddr_top/rd_sta [3] ), .I3 (\u_axi_ddr_top/rd_sta [7] ), - .I4 (\u_axi_ddr_top/s_axi_araddr [18] )); + .I4 (\u_axi_ddr_top/s_axi_araddr [26] )); // LUT = (I1&I4)|(I2&I4)|(I3&I4)|(I0&~I1&~I2&~I3) ; - GTP_LUT5 /* \data_1[37:0]_1690 */ #( + GTP_LUT5 /* \data_1[37:0]_1680 */ #( .INIT(32'b11111111111111100000000000000010)) - \data_1[37:0]_1690 ( - .Z (_N74208), - .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [24] ), + \data_1[37:0]_1680 ( + .Z (_N75496), + .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [29] ), .I1 (\u_axi_ddr_top/rd_sta [1] ), .I2 (\u_axi_ddr_top/rd_sta [3] ), .I3 (\u_axi_ddr_top/rd_sta [7] ), - .I4 (\u_axi_ddr_top/s_axi_araddr [24] )); + .I4 (\u_axi_ddr_top/s_axi_araddr [29] )); // LUT = (I1&I4)|(I2&I4)|(I3&I4)|(I0&~I1&~I2&~I3) ; - GTP_LUT5 /* \data_1[37:0]_1691 */ #( + GTP_LUT5 /* \data_1[37:0]_1681 */ #( .INIT(32'b11111111111111100000000000000010)) - \data_1[37:0]_1691 ( - .Z (_N73574), - .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [14] ), + \data_1[37:0]_1681 ( + .Z (_N74796), + .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [18] ), .I1 (\u_axi_ddr_top/rd_sta [1] ), .I2 (\u_axi_ddr_top/rd_sta [3] ), .I3 (\u_axi_ddr_top/rd_sta [7] ), - .I4 (\u_axi_ddr_top/s_axi_araddr [14] )); + .I4 (\u_axi_ddr_top/s_axi_araddr [18] )); // LUT = (I1&I4)|(I2&I4)|(I3&I4)|(I0&~I1&~I2&~I3) ; - GTP_LUT5 /* \data_1[37:0]_1692 */ #( + GTP_LUT5 /* \data_1[37:0]_1682 */ #( .INIT(32'b11111111111111100000000000000010)) - \data_1[37:0]_1692 ( - .Z (_N73253), - .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [9] ), + \data_1[37:0]_1682 ( + .Z (_N74299), + .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [10] ), .I1 (\u_axi_ddr_top/rd_sta [1] ), .I2 (\u_axi_ddr_top/rd_sta [3] ), .I3 (\u_axi_ddr_top/rd_sta [7] ), - .I4 (\u_axi_ddr_top/s_axi_araddr [9] )); + .I4 (\u_axi_ddr_top/s_axi_araddr [10] )); // LUT = (I1&I4)|(I2&I4)|(I3&I4)|(I0&~I1&~I2&~I3) ; - GTP_LUT5 /* \data_1[37:0]_1693 */ #( + GTP_LUT5 /* \data_1[37:0]_1683 */ #( .INIT(32'b11111111111111100000000000000010)) - \data_1[37:0]_1693 ( - .Z (_N74340), - .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [26] ), + \data_1[37:0]_1683 ( + .Z (_N75242), + .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [25] ), .I1 (\u_axi_ddr_top/rd_sta [1] ), .I2 (\u_axi_ddr_top/rd_sta [3] ), .I3 (\u_axi_ddr_top/rd_sta [7] ), - .I4 (\u_axi_ddr_top/s_axi_araddr [26] )); + .I4 (\u_axi_ddr_top/s_axi_araddr [25] )); // LUT = (I1&I4)|(I2&I4)|(I3&I4)|(I0&~I1&~I2&~I3) ; - GTP_LUT5 /* \data_1[37:0]_1694 */ #( + GTP_LUT5 /* \data_1[37:0]_1684 */ #( .INIT(32'b11111111111111100000000000000010)) - \data_1[37:0]_1694 ( - .Z (_N73006), - .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [5] ), + \data_1[37:0]_1684 ( + .Z (_N74353), + .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [11] ), .I1 (\u_axi_ddr_top/rd_sta [1] ), .I2 (\u_axi_ddr_top/rd_sta [3] ), .I3 (\u_axi_ddr_top/rd_sta [7] ), - .I4 (\u_axi_ddr_top/s_axi_araddr [5] )); + .I4 (\u_axi_ddr_top/s_axi_araddr [11] )); // LUT = (I1&I4)|(I2&I4)|(I3&I4)|(I0&~I1&~I2&~I3) ; - GTP_LUT5 /* \data_1[37:0]_1695 */ #( + GTP_LUT4 /* \data_1[37:0]_1685 */ #( + .INIT(16'b0000000000000010)) + \data_1[37:0]_1685 ( + .Z (_N73809), + .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [2] ), + .I1 (\u_axi_ddr_top/rd_sta [1] ), + .I2 (\u_axi_ddr_top/rd_sta [3] ), + .I3 (\u_axi_ddr_top/rd_sta [7] )); + // LUT = I0&~I1&~I2&~I3 ; + + GTP_LUT5 /* \data_1[37:0]_1686 */ #( .INIT(32'b11111111111111100000000000000010)) - \data_1[37:0]_1695 ( - .Z (_N73958), - .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [20] ), + \data_1[37:0]_1686 ( + .Z (_N74417), + .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [12] ), .I1 (\u_axi_ddr_top/rd_sta [1] ), .I2 (\u_axi_ddr_top/rd_sta [3] ), .I3 (\u_axi_ddr_top/rd_sta [7] ), - .I4 (\u_axi_ddr_top/s_axi_araddr [20] )); + .I4 (\u_axi_ddr_top/s_axi_araddr [12] )); // LUT = (I1&I4)|(I2&I4)|(I3&I4)|(I0&~I1&~I2&~I3) ; - GTP_LUT5 /* \data_1[37:0]_1696 */ #( + GTP_LUT5 /* \data_1[37:0]_1687 */ #( .INIT(32'b11111111111111100000000000000010)) - \data_1[37:0]_1696 ( - .Z (_N74272), - .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [25] ), + \data_1[37:0]_1687 ( + .Z (_N75111), + .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [23] ), .I1 (\u_axi_ddr_top/rd_sta [1] ), .I2 (\u_axi_ddr_top/rd_sta [3] ), .I3 (\u_axi_ddr_top/rd_sta [7] ), - .I4 (\u_axi_ddr_top/s_axi_araddr [25] )); + .I4 (\u_axi_ddr_top/s_axi_araddr [23] )); // LUT = (I1&I4)|(I2&I4)|(I3&I4)|(I0&~I1&~I2&~I3) ; - GTP_LUT5 /* \data_1[37:0]_1697 */ #( + GTP_LUT5 /* \data_1[37:0]_1688 */ #( .INIT(32'b11111111111111100000000000000010)) - \data_1[37:0]_1697 ( - .Z (_N73134), + \data_1[37:0]_1688 ( + .Z (_N74121), .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [7] ), .I1 (\u_axi_ddr_top/rd_sta [1] ), .I2 (\u_axi_ddr_top/rd_sta [3] ), @@ -194395,42 +194136,32 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .I4 (\u_axi_ddr_top/s_axi_araddr [7] )); // LUT = (I1&I4)|(I2&I4)|(I3&I4)|(I0&~I1&~I2&~I3) ; - GTP_LUT5 /* \data_1[37:0]_1698 */ #( + GTP_LUT5 /* \data_1[37:0]_1689 */ #( .INIT(32'b11111111111111100000000000000010)) - \data_1[37:0]_1698 ( - .Z (_N73702), - .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [16] ), + \data_1[37:0]_1689 ( + .Z (_N74921), + .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [20] ), .I1 (\u_axi_ddr_top/rd_sta [1] ), .I2 (\u_axi_ddr_top/rd_sta [3] ), .I3 (\u_axi_ddr_top/rd_sta [7] ), - .I4 (\u_axi_ddr_top/s_axi_araddr [16] )); + .I4 (\u_axi_ddr_top/s_axi_araddr [20] )); // LUT = (I1&I4)|(I2&I4)|(I3&I4)|(I0&~I1&~I2&~I3) ; - GTP_LUT5 /* \data_1[37:0]_1699 */ #( + GTP_LUT5 /* \data_1[37:0]_1690 */ #( .INIT(32'b11111111111111100000000000000010)) - \data_1[37:0]_1699 ( - .Z (_N73768), - .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [17] ), + \data_1[37:0]_1690 ( + .Z (_N74185), + .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [8] ), .I1 (\u_axi_ddr_top/rd_sta [1] ), .I2 (\u_axi_ddr_top/rd_sta [3] ), .I3 (\u_axi_ddr_top/rd_sta [7] ), - .I4 (\u_axi_ddr_top/s_axi_araddr [17] )); + .I4 (\u_axi_ddr_top/s_axi_araddr [8] )); // LUT = (I1&I4)|(I2&I4)|(I3&I4)|(I0&~I1&~I2&~I3) ; - GTP_LUT4 /* \data_1[37:0]_1700 */ #( - .INIT(16'b0000000000000010)) - \data_1[37:0]_1700 ( - .Z (_N72951), - .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [4] ), - .I1 (\u_axi_ddr_top/rd_sta [1] ), - .I2 (\u_axi_ddr_top/rd_sta [3] ), - .I3 (\u_axi_ddr_top/rd_sta [7] )); - // LUT = I0&~I1&~I2&~I3 ; - - GTP_LUT5 /* \data_1[37:0]_1701 */ #( + GTP_LUT5 /* \data_1[37:0]_1691 */ #( .INIT(32'b11111111111111100000000000000010)) - \data_1[37:0]_1701 ( - .Z (_N74463), + \data_1[37:0]_1691 ( + .Z (_N75429), .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [28] ), .I1 (\u_axi_ddr_top/rd_sta [1] ), .I2 (\u_axi_ddr_top/rd_sta [3] ), @@ -194438,53 +194169,53 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .I4 (\u_axi_ddr_top/s_axi_araddr [28] )); // LUT = (I1&I4)|(I2&I4)|(I3&I4)|(I0&~I1&~I2&~I3) ; - GTP_LUT5 /* \data_1[37:0]_1702 */ #( + GTP_LUT5 /* \data_1[37:0]_1692 */ #( .INIT(32'b11111111111111100000000000000010)) - \data_1[37:0]_1702 ( - .Z (_N73640), - .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [15] ), + \data_1[37:0]_1692 ( + .Z (_N74731), + .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [17] ), .I1 (\u_axi_ddr_top/rd_sta [1] ), .I2 (\u_axi_ddr_top/rd_sta [3] ), .I3 (\u_axi_ddr_top/rd_sta [7] ), - .I4 (\u_axi_ddr_top/s_axi_araddr [15] )); + .I4 (\u_axi_ddr_top/s_axi_araddr [17] )); // LUT = (I1&I4)|(I2&I4)|(I3&I4)|(I0&~I1&~I2&~I3) ; - GTP_LUT5 /* \data_1[37:0]_1703 */ #( + GTP_LUT5 /* \data_1[37:0]_1693 */ #( .INIT(32'b11111111111111100000000000000010)) - \data_1[37:0]_1703 ( - .Z (_N73194), - .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [8] ), + \data_1[37:0]_1693 ( + .Z (_N75363), + .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [27] ), .I1 (\u_axi_ddr_top/rd_sta [1] ), .I2 (\u_axi_ddr_top/rd_sta [3] ), .I3 (\u_axi_ddr_top/rd_sta [7] ), - .I4 (\u_axi_ddr_top/s_axi_araddr [8] )); + .I4 (\u_axi_ddr_top/s_axi_araddr [27] )); // LUT = (I1&I4)|(I2&I4)|(I3&I4)|(I0&~I1&~I2&~I3) ; - GTP_LUT5 /* \data_1[37:0]_1704 */ #( + GTP_LUT5 /* \data_1[37:0]_1694 */ #( .INIT(32'b11111111111111100000000000000010)) - \data_1[37:0]_1704 ( - .Z (_N74085), - .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [22] ), + \data_1[37:0]_1694 ( + .Z (_N75173), + .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [24] ), .I1 (\u_axi_ddr_top/rd_sta [1] ), .I2 (\u_axi_ddr_top/rd_sta [3] ), .I3 (\u_axi_ddr_top/rd_sta [7] ), - .I4 (\u_axi_ddr_top/s_axi_araddr [22] )); + .I4 (\u_axi_ddr_top/s_axi_araddr [24] )); // LUT = (I1&I4)|(I2&I4)|(I3&I4)|(I0&~I1&~I2&~I3) ; - GTP_LUT5 /* \data_1[37:0]_1705 */ #( + GTP_LUT5 /* \data_1[37:0]_1695 */ #( .INIT(32'b11111111111111100000000000000010)) - \data_1[37:0]_1705 ( - .Z (_N73510), - .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [13] ), + \data_1[37:0]_1695 ( + .Z (_N74242), + .I0 (\u_axi_ddr_top/awaddr_ddr_fifo_dout [9] ), .I1 (\u_axi_ddr_top/rd_sta [1] ), .I2 (\u_axi_ddr_top/rd_sta [3] ), .I3 (\u_axi_ddr_top/rd_sta [7] ), - .I4 (\u_axi_ddr_top/s_axi_araddr [13] )); + .I4 (\u_axi_ddr_top/s_axi_araddr [9] )); // LUT = (I1&I4)|(I2&I4)|(I3&I4)|(I0&~I1&~I2&~I3) ; - GTP_LUT3 /* \data_1[37:0]_4696 */ #( + GTP_LUT3 /* \data_1[37:0]_4721 */ #( .INIT(8'b00000001)) - \data_1[37:0]_4696 ( + \data_1[37:0]_4721 ( .Z (\u_axi_ddr_top/s_axi_arvalid_inv ), .I0 (\u_axi_ddr_top/rd_sta [1] ), .I1 (\u_axi_ddr_top/rd_sta [3] ), @@ -194509,14 +194240,14 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .Q (data_valid_0), .C (N2), .CLK (clk), - .D (_N103432)); + .D (_N104244)); // defparam data_valid_0_vname.orig_name = data_valid_0; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:145 GTP_LUT4 /* data_valid_0_ce_mux */ #( .INIT(16'b1111111111010000)) data_valid_0_ce_mux ( - .Z (_N103432), + .Z (_N104244), .I0 (fifo_read), .I1 (rptr), .I2 (data_valid_0), @@ -194530,14 +194261,14 @@ module ipsxb_mcdq_reg_fifo2_v1_2 .Q (data_valid_1), .C (N2), .CLK (clk), - .D (_N103431)); + .D (_N104243)); // defparam data_valid_1_vname.orig_name = data_valid_1; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:155 GTP_LUT4 /* data_valid_1_ce_mux */ #( .INIT(16'b1111111101110000)) data_valid_1_ce_mux ( - .Z (_N103431), + .Z (_N104243), .I0 (fifo_read), .I1 (rptr), .I2 (data_valid_1), @@ -194570,16 +194301,17 @@ module ipsxb_mcdq_reg_fifo2_v1_2_1 output [54:0] data_0, output [54:0] data_1, output [54:0] data_out, + output data_in_ready, output data_valid_0, output data_valid_1, output rptr ); wire N10; wire N14; - wire _N103429; - wire _N103433; - wire _N103434; - wire _N103435; + wire _N104241; + wire _N104245; + wire _N104246; + wire _N104247; wire wptr; GTP_LUT4 /* N10 */ #( @@ -194606,6 +194338,15 @@ module ipsxb_mcdq_reg_fifo2_v1_2_1 // LUT = (I0&~I2&I3)|(I0&~I1&I3) ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:138 + GTP_LUT2 /* N20 */ #( + .INIT(4'b0111)) + N20 ( + .Z (data_in_ready), + .I0 (data_valid_0), + .I1 (data_valid_1)); + // LUT = (~I1)|(~I0) ; + // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:144 + GTP_LUT3 /* N35_2 */ #( .INIT(8'b11100100)) N35_2 ( @@ -195969,14 +195710,14 @@ module ipsxb_mcdq_reg_fifo2_v1_2_1 .Q (data_valid_0), .C (N2), .CLK (clk), - .D (_N103433)); + .D (_N104245)); // defparam data_valid_0_vname.orig_name = data_valid_0; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:145 GTP_LUT4 /* data_valid_0_ce_mux */ #( .INIT(16'b1111110011011100)) data_valid_0_ce_mux ( - .Z (_N103433), + .Z (_N104245), .I0 (data_out_ready), .I1 (N10), .I2 (data_valid_0), @@ -195990,14 +195731,14 @@ module ipsxb_mcdq_reg_fifo2_v1_2_1 .Q (data_valid_1), .C (N2), .CLK (clk), - .D (_N103434)); + .D (_N104246)); // defparam data_valid_1_vname.orig_name = data_valid_1; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:155 GTP_LUT4 /* data_valid_1_ce_mux */ #( .INIT(16'b1101110011111100)) data_valid_1_ce_mux ( - .Z (_N103434), + .Z (_N104246), .I0 (data_out_ready), .I1 (N14), .I2 (data_valid_1), @@ -196011,14 +195752,14 @@ module ipsxb_mcdq_reg_fifo2_v1_2_1 .Q (rptr), .C (N2), .CLK (clk), - .D (_N103435)); + .D (_N104247)); // defparam rptr_vname.orig_name = rptr; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:118 GTP_LUT4 /* rptr_ce_mux */ #( .INIT(16'b0101011110101000)) rptr_ce_mux ( - .Z (_N103435), + .Z (_N104247), .I0 (data_out_ready), .I1 (data_valid_0), .I2 (data_valid_1), @@ -196032,14 +195773,14 @@ module ipsxb_mcdq_reg_fifo2_v1_2_1 .Q (wptr), .C (N2), .CLK (clk), - .D (_N103429)); + .D (_N104241)); // defparam wptr_vname.orig_name = wptr; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_reg_fifo2_v1_2.vp:110 GTP_LUT4 /* wptr_ce_mux */ #( .INIT(16'b1101010100101010)) wptr_ce_mux ( - .Z (_N103429), + .Z (_N104241), .I0 (data_in_valid), .I1 (data_valid_0), .I2 (data_valid_1), @@ -196088,74 +195829,73 @@ module ipsxb_mcdq_ui_axi_v1_2 wire N274; wire N278; wire N282; - wire _N6167; - wire _N6171; - wire _N15125; - wire _N15126; - wire _N15127; - wire _N15128; - wire _N15129; - wire _N15130; - wire _N15131; - wire _N15132; - wire _N15133; - wire _N15134; - wire _N15135; - wire _N15136; - wire _N15137; - wire _N15138; - wire _N15139; - wire _N15140; - wire _N15141; - wire _N15142; - wire _N15143; - wire _N15144; - wire _N15145; - wire _N15146; - wire _N15147; - wire _N15148; - wire _N15195; - wire _N15196; - wire _N15197; - wire _N15198; - wire _N15199; - wire _N24679; - wire _N24680; - wire _N24681; - wire _N24682; - wire _N24683; - wire _N24684; - wire _N24685; - wire _N24686; - wire _N24687; - wire _N24688; - wire _N24689; - wire _N24690; - wire _N24691; - wire _N24692; - wire _N24693; - wire _N24724; - wire _N24725; - wire _N24726; - wire _N24727; - wire _N24728; - wire _N24729; - wire _N24730; - wire _N24731; - wire _N24732; - wire _N24733; - wire _N24734; - wire _N24735; - wire _N24736; - wire _N24737; - wire _N24738; - wire _N66672; - wire _N70208; - wire _N70258; - wire _N70674; - wire _N102415_2; - wire _N103428; - wire _N103430; + wire _N6254; + wire _N6258; + wire _N15167; + wire _N15168; + wire _N15169; + wire _N15170; + wire _N15171; + wire _N15172; + wire _N15173; + wire _N15174; + wire _N15175; + wire _N15176; + wire _N15177; + wire _N15178; + wire _N15179; + wire _N15180; + wire _N15181; + wire _N15182; + wire _N15183; + wire _N15184; + wire _N15185; + wire _N15186; + wire _N15187; + wire _N15188; + wire _N15189; + wire _N15190; + wire _N15241; + wire _N15242; + wire _N15243; + wire _N15244; + wire _N15245; + wire _N24440; + wire _N24441; + wire _N24442; + wire _N24443; + wire _N24444; + wire _N24445; + wire _N24446; + wire _N24447; + wire _N24448; + wire _N24449; + wire _N24450; + wire _N24451; + wire _N24452; + wire _N24453; + wire _N24454; + wire _N24485; + wire _N24486; + wire _N24487; + wire _N24488; + wire _N24489; + wire _N24490; + wire _N24491; + wire _N24492; + wire _N24493; + wire _N24494; + wire _N24495; + wire _N24496; + wire _N24497; + wire _N24498; + wire _N24499; + wire _N67679; + wire _N71475; + wire _N71602; + wire _N103130_2; + wire _N104240; + wire _N104242; wire axi_arvalid; wire [10:0] column_addr_end; wire [37:0] data_out; @@ -196176,6 +195916,7 @@ module ipsxb_mcdq_ui_axi_v1_2 wire [14:0] \old_row_addr_array[6] ; wire [14:0] \old_row_addr_array[7] ; wire [27:0] pre_addr; + wire pre_data_in_ready; wire pre_data_in_valid; wire [3:0] pre_id; wire [3:0] pre_len; @@ -196310,6 +196051,30 @@ module ipsxb_mcdq_ui_axi_v1_2 .I4 (\mcdq_reg_fifo2/data_valid_0 )); // LUT = (I1&~I2&~I4)|(~I0&I1&~I4)|(I1&~I2&~I3)|(~I0&I1&~I3) ; + GTP_LUT5 /* \N27_1[4] */ #( + .INIT(32'b11111010010100001111001011010000)) + \N27_1[4] ( + .Z (ui_addr[4]), + .I0 (axi_arvalid), + .I1 (axi_awvalid), + .I2 (axi_awaddr[4]), + .I3 (axi_araddr[4]), + .I4 (ptr)); + // LUT = (~I0&I2)|(I1&I2&~I4)|(I0&~I1&I3)|(I0&I3&I4) ; + // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_ui_axi_v1_2.vp:397 + + GTP_LUT5 /* \N27_1[7] */ #( + .INIT(32'b11111010010100001111001011010000)) + \N27_1[7] ( + .Z (ui_addr[7]), + .I0 (axi_arvalid), + .I1 (axi_awvalid), + .I2 (axi_awaddr[7]), + .I3 (axi_araddr[7]), + .I4 (ptr)); + // LUT = (~I0&I2)|(I1&I2&~I4)|(I0&~I1&I3)|(I0&I3&I4) ; + // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_ui_axi_v1_2.vp:397 + GTP_LUT5 /* \N27_1[8] */ #( .INIT(32'b11111010010100001111001011010000)) \N27_1[8] ( @@ -196322,26 +196087,26 @@ module ipsxb_mcdq_ui_axi_v1_2 // LUT = (~I0&I2)|(I1&I2&~I4)|(I0&~I1&I3)|(I0&I3&I4) ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_ui_axi_v1_2.vp:397 - GTP_LUT5 /* \N27_1[11] */ #( + GTP_LUT5 /* \N27_1[13] */ #( .INIT(32'b11111010010100001111001011010000)) - \N27_1[11] ( - .Z (ui_addr[11]), + \N27_1[13] ( + .Z (ui_addr[13]), .I0 (axi_arvalid), .I1 (axi_awvalid), - .I2 (axi_awaddr[11]), - .I3 (axi_araddr[11]), + .I2 (axi_awaddr[13]), + .I3 (axi_araddr[13]), .I4 (ptr)); // LUT = (~I0&I2)|(I1&I2&~I4)|(I0&~I1&I3)|(I0&I3&I4) ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_ui_axi_v1_2.vp:397 - GTP_LUT5 /* \N27_1[12] */ #( + GTP_LUT5 /* \N27_1[16] */ #( .INIT(32'b11111010010100001111001011010000)) - \N27_1[12] ( - .Z (ui_addr[12]), + \N27_1[16] ( + .Z (ui_addr[16]), .I0 (axi_arvalid), .I1 (axi_awvalid), - .I2 (axi_awaddr[12]), - .I3 (axi_araddr[12]), + .I2 (axi_awaddr[16]), + .I3 (axi_araddr[16]), .I4 (ptr)); // LUT = (~I0&I2)|(I1&I2&~I4)|(I0&~I1&I3)|(I0&I3&I4) ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_ui_axi_v1_2.vp:397 @@ -196358,26 +196123,14 @@ module ipsxb_mcdq_ui_axi_v1_2 // LUT = (~I0&I2)|(I1&I2&~I4)|(I0&~I1&I3)|(I0&I3&I4) ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_ui_axi_v1_2.vp:397 - GTP_LUT5 /* \N27_1[20] */ #( - .INIT(32'b11111010010100001111001011010000)) - \N27_1[20] ( - .Z (ui_addr[20]), - .I0 (axi_arvalid), - .I1 (axi_awvalid), - .I2 (axi_awaddr[20]), - .I3 (axi_araddr[20]), - .I4 (ptr)); - // LUT = (~I0&I2)|(I1&I2&~I4)|(I0&~I1&I3)|(I0&I3&I4) ; - // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_ui_axi_v1_2.vp:397 - - GTP_LUT5 /* \N27_1[21] */ #( + GTP_LUT5 /* \N27_1[26] */ #( .INIT(32'b11111010010100001111001011010000)) - \N27_1[21] ( - .Z (ui_addr[21]), + \N27_1[26] ( + .Z (ui_addr[26]), .I0 (axi_arvalid), .I1 (axi_awvalid), - .I2 (axi_awaddr[21]), - .I3 (axi_araddr[21]), + .I2 (axi_awaddr[26]), + .I3 (axi_araddr[26]), .I4 (ptr)); // LUT = (~I0&I2)|(I1&I2&~I4)|(I0&~I1&I3)|(I0&I3&I4) ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_ui_axi_v1_2.vp:397 @@ -196396,13 +196149,13 @@ module ipsxb_mcdq_ui_axi_v1_2 GTP_LUT5M /* N59_1_sum3_6 */ #( .INIT(32'b11001100110010001100110011001000)) N59_1_sum3_6 ( - .Z (_N102415_2), - .I0 (\mcdq_reg_fifo2/data_1 [12] ), + .Z (_N103130_2), + .I0 (\mcdq_reg_fifo2/data_1 [11] ), .I1 (data_out[0]), - .I2 (data_out[11]), + .I2 (data_out[12]), .I3 (data_out[13]), .I4 (\mcdq_reg_fifo2/rptr ), - .ID (\mcdq_reg_fifo2/data_0 [12] )); + .ID (\mcdq_reg_fifo2/data_0 [11] )); // LUT = (ID&I1&~I4)|(I0&I1&I4)|(I1&I3)|(I1&I2) ; GTP_LUT5M /* \N61[0]_1 */ #( @@ -196419,16 +196172,16 @@ module ipsxb_mcdq_ui_axi_v1_2 // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_ui_axi_v1_2.vp:474 GTP_LUT5M /* \N61[1]_1 */ #( - .INIT(32'b10001000010010001000100001001000)) + .INIT(32'b10001100010000001000110001000000)) \N61[1]_1 ( .Z (N61[1]), - .I0 (\mcdq_reg_fifo2/data_1 [12] ), + .I0 (\mcdq_reg_fifo2/data_1 [11] ), .I1 (column_addr_end[10]), .I2 (data_out[0]), - .I3 (data_out[11]), + .I3 (data_out[12]), .I4 (\mcdq_reg_fifo2/rptr ), - .ID (\mcdq_reg_fifo2/data_0 [12] )); - // LUT = (~ID&I1&I2&~I3&~I4)|(ID&I1&I3&~I4)|(ID&I1&~I2&~I4)|(~I0&I1&I2&~I3&I4)|(I0&I1&I3&I4)|(I0&I1&~I2&I4) ; + .ID (\mcdq_reg_fifo2/data_0 [11] )); + // LUT = (~ID&I1&I2&~I3&~I4)|(ID&I1&I3&~I4)|(~I0&I1&I2&~I3&I4)|(I0&I1&I3&I4)|(I1&~I2&I3) ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_ui_axi_v1_2.vp:474 GTP_LUT5 /* \N61[2]_1 */ #( @@ -196451,7 +196204,7 @@ module ipsxb_mcdq_ui_axi_v1_2 .I1 (\mcdq_reg_fifo2/rptr ), .I2 (\mcdq_reg_fifo2/data_0 [14] ), .I3 (\mcdq_reg_fifo2/data_1 [14] ), - .I4 (_N102415_2)); + .I4 (_N103130_2)); // LUT = (I0&~I1&I2&~I4)|(I0&I1&I3&~I4)|(I0&I1&~I3&I4)|(I0&~I1&~I2&I4) ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_ui_axi_v1_2.vp:474 @@ -196469,7 +196222,7 @@ module ipsxb_mcdq_ui_axi_v1_2 GTP_LUT2 /* N69_0_ac4 */ #( .INIT(4'b1000)) N69_0_ac4 ( - .Z (_N6167), + .Z (_N6254), .I0 (pre_len[0]), .I1 (pre_len[1])); // LUT = I0&I1 ; @@ -196477,7 +196230,7 @@ module ipsxb_mcdq_ui_axi_v1_2 GTP_LUT3 /* N69_0_ac5 */ #( .INIT(8'b10000000)) N69_0_ac5 ( - .Z (_N6171), + .Z (_N6258), .I0 (pre_len[0]), .I1 (pre_len[1]), .I2 (pre_len[2])); @@ -196490,7 +196243,7 @@ module ipsxb_mcdq_ui_axi_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_2_1 ( - .COUT (_N15125), + .COUT (_N15167), .Z (N69[3]), .CIN (), .I0 (pre_len[0]), @@ -196509,9 +196262,9 @@ module ipsxb_mcdq_ui_axi_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_2_2 ( - .COUT (_N15126), + .COUT (_N15168), .Z (N69[4]), - .CIN (_N15125), + .CIN (_N15167), .I0 (pre_len[0]), .I1 (pre_addr[3]), .I2 (pre_addr[4]), @@ -196528,11 +196281,11 @@ module ipsxb_mcdq_ui_axi_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_2_3 ( - .COUT (_N15127), + .COUT (_N15169), .Z (N69[5]), - .CIN (_N15126), + .CIN (_N15168), .I0 (), - .I1 (_N6167), + .I1 (_N6254), .I2 (pre_addr[5]), .I3 (pre_len[2]), .I4 (pre_addr[5]), @@ -196547,11 +196300,11 @@ module ipsxb_mcdq_ui_axi_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_2_4 ( - .COUT (_N15128), + .COUT (_N15170), .Z (N69[6]), - .CIN (_N15127), + .CIN (_N15169), .I0 (), - .I1 (_N6171), + .I1 (_N6258), .I2 (pre_addr[6]), .I3 (pre_len[3]), .I4 (pre_addr[6]), @@ -196566,11 +196319,11 @@ module ipsxb_mcdq_ui_axi_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_2_5 ( - .COUT (_N15129), + .COUT (_N15171), .Z (N69[7]), - .CIN (_N15128), + .CIN (_N15170), .I0 (), - .I1 (_N6171), + .I1 (_N6258), .I2 (pre_addr[7]), .I3 (pre_len[3]), .I4 (pre_addr[7]), @@ -196585,9 +196338,9 @@ module ipsxb_mcdq_ui_axi_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_2_6 ( - .COUT (_N15130), + .COUT (_N15172), .Z (N229[8]), - .CIN (_N15129), + .CIN (_N15171), .I0 (), .I1 (pre_addr[8]), .I2 (N54), @@ -196604,9 +196357,9 @@ module ipsxb_mcdq_ui_axi_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_2_7 ( - .COUT (_N15131), + .COUT (_N15173), .Z (N229[9]), - .CIN (_N15130), + .CIN (_N15172), .I0 (), .I1 (pre_addr[9]), .I2 (N54), @@ -196623,9 +196376,9 @@ module ipsxb_mcdq_ui_axi_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_2_8 ( - .COUT (_N15132), + .COUT (_N15174), .Z (N229[10]), - .CIN (_N15131), + .CIN (_N15173), .I0 (), .I1 (pre_addr[10]), .I2 (N54), @@ -196642,9 +196395,9 @@ module ipsxb_mcdq_ui_axi_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_2_9 ( - .COUT (_N15133), + .COUT (_N15175), .Z (N229[11]), - .CIN (_N15132), + .CIN (_N15174), .I0 (), .I1 (pre_addr[11]), .I2 (N54), @@ -196661,9 +196414,9 @@ module ipsxb_mcdq_ui_axi_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_2_10 ( - .COUT (_N15134), + .COUT (_N15176), .Z (N229[12]), - .CIN (_N15133), + .CIN (_N15175), .I0 (), .I1 (pre_addr[12]), .I2 (N54), @@ -196680,9 +196433,9 @@ module ipsxb_mcdq_ui_axi_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_2_11 ( - .COUT (_N15135), + .COUT (_N15177), .Z (N229[13]), - .CIN (_N15134), + .CIN (_N15176), .I0 (), .I1 (pre_addr[13]), .I2 (N54), @@ -196699,9 +196452,9 @@ module ipsxb_mcdq_ui_axi_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_2_12 ( - .COUT (_N15136), + .COUT (_N15178), .Z (N229[14]), - .CIN (_N15135), + .CIN (_N15177), .I0 (), .I1 (pre_addr[14]), .I2 (N54), @@ -196718,9 +196471,9 @@ module ipsxb_mcdq_ui_axi_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_2_13 ( - .COUT (_N15137), + .COUT (_N15179), .Z (N229[15]), - .CIN (_N15136), + .CIN (_N15178), .I0 (), .I1 (pre_addr[15]), .I2 (N54), @@ -196737,9 +196490,9 @@ module ipsxb_mcdq_ui_axi_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_2_14 ( - .COUT (_N15138), + .COUT (_N15180), .Z (N229[16]), - .CIN (_N15137), + .CIN (_N15179), .I0 (), .I1 (pre_addr[16]), .I2 (N54), @@ -196756,9 +196509,9 @@ module ipsxb_mcdq_ui_axi_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_2_15 ( - .COUT (_N15139), + .COUT (_N15181), .Z (N229[17]), - .CIN (_N15138), + .CIN (_N15180), .I0 (), .I1 (pre_addr[17]), .I2 (N54), @@ -196775,9 +196528,9 @@ module ipsxb_mcdq_ui_axi_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_2_16 ( - .COUT (_N15140), + .COUT (_N15182), .Z (N229[18]), - .CIN (_N15139), + .CIN (_N15181), .I0 (), .I1 (pre_addr[18]), .I2 (N54), @@ -196794,9 +196547,9 @@ module ipsxb_mcdq_ui_axi_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_2_17 ( - .COUT (_N15141), + .COUT (_N15183), .Z (N229[19]), - .CIN (_N15140), + .CIN (_N15182), .I0 (), .I1 (pre_addr[19]), .I2 (N54), @@ -196813,9 +196566,9 @@ module ipsxb_mcdq_ui_axi_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_2_18 ( - .COUT (_N15142), + .COUT (_N15184), .Z (N229[20]), - .CIN (_N15141), + .CIN (_N15183), .I0 (), .I1 (pre_addr[20]), .I2 (N54), @@ -196832,9 +196585,9 @@ module ipsxb_mcdq_ui_axi_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_2_19 ( - .COUT (_N15143), + .COUT (_N15185), .Z (N229[21]), - .CIN (_N15142), + .CIN (_N15184), .I0 (), .I1 (pre_addr[21]), .I2 (N54), @@ -196851,9 +196604,9 @@ module ipsxb_mcdq_ui_axi_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_2_20 ( - .COUT (_N15144), + .COUT (_N15186), .Z (N229[22]), - .CIN (_N15143), + .CIN (_N15185), .I0 (), .I1 (pre_addr[22]), .I2 (N54), @@ -196870,9 +196623,9 @@ module ipsxb_mcdq_ui_axi_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_2_21 ( - .COUT (_N15145), + .COUT (_N15187), .Z (N229[23]), - .CIN (_N15144), + .CIN (_N15186), .I0 (), .I1 (pre_addr[23]), .I2 (N54), @@ -196889,9 +196642,9 @@ module ipsxb_mcdq_ui_axi_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_2_22 ( - .COUT (_N15146), + .COUT (_N15188), .Z (N229[24]), - .CIN (_N15145), + .CIN (_N15187), .I0 (), .I1 (pre_addr[24]), .I2 (N54), @@ -196908,9 +196661,9 @@ module ipsxb_mcdq_ui_axi_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_2_23 ( - .COUT (_N15147), + .COUT (_N15189), .Z (N229[25]), - .CIN (_N15146), + .CIN (_N15188), .I0 (), .I1 (pre_addr[25]), .I2 (N54), @@ -196927,9 +196680,9 @@ module ipsxb_mcdq_ui_axi_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_2_24 ( - .COUT (_N15148), + .COUT (_N15190), .Z (N229[26]), - .CIN (_N15147), + .CIN (_N15189), .I0 (), .I1 (pre_addr[26]), .I2 (N54), @@ -196948,7 +196701,7 @@ module ipsxb_mcdq_ui_axi_v1_2 N69_2_25 ( .COUT (), .Z (N229[27]), - .CIN (_N15148), + .CIN (_N15190), .I0 (), .I1 (pre_addr[27]), .I2 (N54), @@ -196961,7 +196714,7 @@ module ipsxb_mcdq_ui_axi_v1_2 GTP_LUT5M /* \N184_4[0] */ #( .INIT(32'b11001010110010101111101000001010)) \N184_4[0] ( - .Z (_N24679), + .Z (_N24440), .I0 (\old_row_addr_array[5] [0] ), .I1 (\old_row_addr_array[7] [0] ), .I2 (pre_addr[25]), @@ -196973,7 +196726,7 @@ module ipsxb_mcdq_ui_axi_v1_2 GTP_LUT5M /* \N184_4[1] */ #( .INIT(32'b11001010110010101111101000001010)) \N184_4[1] ( - .Z (_N24680), + .Z (_N24441), .I0 (\old_row_addr_array[5] [1] ), .I1 (\old_row_addr_array[7] [1] ), .I2 (pre_addr[25]), @@ -196985,7 +196738,7 @@ module ipsxb_mcdq_ui_axi_v1_2 GTP_LUT5M /* \N184_4[2] */ #( .INIT(32'b11001010110010101111101000001010)) \N184_4[2] ( - .Z (_N24681), + .Z (_N24442), .I0 (\old_row_addr_array[5] [2] ), .I1 (\old_row_addr_array[7] [2] ), .I2 (pre_addr[25]), @@ -196997,7 +196750,7 @@ module ipsxb_mcdq_ui_axi_v1_2 GTP_LUT5M /* \N184_4[3] */ #( .INIT(32'b11001010110010101111101000001010)) \N184_4[3] ( - .Z (_N24682), + .Z (_N24443), .I0 (\old_row_addr_array[5] [3] ), .I1 (\old_row_addr_array[7] [3] ), .I2 (pre_addr[25]), @@ -197009,7 +196762,7 @@ module ipsxb_mcdq_ui_axi_v1_2 GTP_LUT5M /* \N184_4[4] */ #( .INIT(32'b11001010110010101111101000001010)) \N184_4[4] ( - .Z (_N24683), + .Z (_N24444), .I0 (\old_row_addr_array[5] [4] ), .I1 (\old_row_addr_array[7] [4] ), .I2 (pre_addr[25]), @@ -197021,7 +196774,7 @@ module ipsxb_mcdq_ui_axi_v1_2 GTP_LUT5M /* \N184_4[5] */ #( .INIT(32'b11001010110010101111101000001010)) \N184_4[5] ( - .Z (_N24684), + .Z (_N24445), .I0 (\old_row_addr_array[5] [5] ), .I1 (\old_row_addr_array[7] [5] ), .I2 (pre_addr[25]), @@ -197033,7 +196786,7 @@ module ipsxb_mcdq_ui_axi_v1_2 GTP_LUT5M /* \N184_4[6] */ #( .INIT(32'b11001010110010101111101000001010)) \N184_4[6] ( - .Z (_N24685), + .Z (_N24446), .I0 (\old_row_addr_array[5] [6] ), .I1 (\old_row_addr_array[7] [6] ), .I2 (pre_addr[25]), @@ -197045,7 +196798,7 @@ module ipsxb_mcdq_ui_axi_v1_2 GTP_LUT5M /* \N184_4[7] */ #( .INIT(32'b11001010110010101111101000001010)) \N184_4[7] ( - .Z (_N24686), + .Z (_N24447), .I0 (\old_row_addr_array[5] [7] ), .I1 (\old_row_addr_array[7] [7] ), .I2 (pre_addr[25]), @@ -197057,7 +196810,7 @@ module ipsxb_mcdq_ui_axi_v1_2 GTP_LUT5M /* \N184_4[8] */ #( .INIT(32'b11001010110010101111101000001010)) \N184_4[8] ( - .Z (_N24687), + .Z (_N24448), .I0 (\old_row_addr_array[5] [8] ), .I1 (\old_row_addr_array[7] [8] ), .I2 (pre_addr[25]), @@ -197069,7 +196822,7 @@ module ipsxb_mcdq_ui_axi_v1_2 GTP_LUT5M /* \N184_4[9] */ #( .INIT(32'b11001010110010101111101000001010)) \N184_4[9] ( - .Z (_N24688), + .Z (_N24449), .I0 (\old_row_addr_array[5] [9] ), .I1 (\old_row_addr_array[7] [9] ), .I2 (pre_addr[25]), @@ -197081,7 +196834,7 @@ module ipsxb_mcdq_ui_axi_v1_2 GTP_LUT5M /* \N184_4[10] */ #( .INIT(32'b11001010110010101111101000001010)) \N184_4[10] ( - .Z (_N24689), + .Z (_N24450), .I0 (\old_row_addr_array[5] [10] ), .I1 (\old_row_addr_array[7] [10] ), .I2 (pre_addr[25]), @@ -197093,7 +196846,7 @@ module ipsxb_mcdq_ui_axi_v1_2 GTP_LUT5M /* \N184_4[11] */ #( .INIT(32'b11001010110010101111101000001010)) \N184_4[11] ( - .Z (_N24690), + .Z (_N24451), .I0 (\old_row_addr_array[5] [11] ), .I1 (\old_row_addr_array[7] [11] ), .I2 (pre_addr[25]), @@ -197105,7 +196858,7 @@ module ipsxb_mcdq_ui_axi_v1_2 GTP_LUT5M /* \N184_4[12] */ #( .INIT(32'b11001010110010101111101000001010)) \N184_4[12] ( - .Z (_N24691), + .Z (_N24452), .I0 (\old_row_addr_array[5] [12] ), .I1 (\old_row_addr_array[7] [12] ), .I2 (pre_addr[25]), @@ -197117,7 +196870,7 @@ module ipsxb_mcdq_ui_axi_v1_2 GTP_LUT5M /* \N184_4[13] */ #( .INIT(32'b11001010110010101111101000001010)) \N184_4[13] ( - .Z (_N24692), + .Z (_N24453), .I0 (\old_row_addr_array[5] [13] ), .I1 (\old_row_addr_array[7] [13] ), .I2 (pre_addr[25]), @@ -197129,7 +196882,7 @@ module ipsxb_mcdq_ui_axi_v1_2 GTP_LUT5M /* \N184_4[14] */ #( .INIT(32'b11001010110010101111101000001010)) \N184_4[14] ( - .Z (_N24693), + .Z (_N24454), .I0 (\old_row_addr_array[5] [14] ), .I1 (\old_row_addr_array[7] [14] ), .I2 (pre_addr[25]), @@ -197141,7 +196894,7 @@ module ipsxb_mcdq_ui_axi_v1_2 GTP_LUT5M /* \N184_7[0] */ #( .INIT(32'b11001010110010101111101000001010)) \N184_7[0] ( - .Z (_N24724), + .Z (_N24485), .I0 (\old_row_addr_array[4] [0] ), .I1 (\old_row_addr_array[6] [0] ), .I2 (pre_addr[25]), @@ -197153,7 +196906,7 @@ module ipsxb_mcdq_ui_axi_v1_2 GTP_LUT5M /* \N184_7[1] */ #( .INIT(32'b11001010110010101111101000001010)) \N184_7[1] ( - .Z (_N24725), + .Z (_N24486), .I0 (\old_row_addr_array[4] [1] ), .I1 (\old_row_addr_array[6] [1] ), .I2 (pre_addr[25]), @@ -197165,7 +196918,7 @@ module ipsxb_mcdq_ui_axi_v1_2 GTP_LUT5M /* \N184_7[2] */ #( .INIT(32'b11001010110010101111101000001010)) \N184_7[2] ( - .Z (_N24726), + .Z (_N24487), .I0 (\old_row_addr_array[4] [2] ), .I1 (\old_row_addr_array[6] [2] ), .I2 (pre_addr[25]), @@ -197177,7 +196930,7 @@ module ipsxb_mcdq_ui_axi_v1_2 GTP_LUT5M /* \N184_7[3] */ #( .INIT(32'b11001010110010101111101000001010)) \N184_7[3] ( - .Z (_N24727), + .Z (_N24488), .I0 (\old_row_addr_array[4] [3] ), .I1 (\old_row_addr_array[6] [3] ), .I2 (pre_addr[25]), @@ -197189,7 +196942,7 @@ module ipsxb_mcdq_ui_axi_v1_2 GTP_LUT5M /* \N184_7[4] */ #( .INIT(32'b11001010110010101111101000001010)) \N184_7[4] ( - .Z (_N24728), + .Z (_N24489), .I0 (\old_row_addr_array[4] [4] ), .I1 (\old_row_addr_array[6] [4] ), .I2 (pre_addr[25]), @@ -197201,7 +196954,7 @@ module ipsxb_mcdq_ui_axi_v1_2 GTP_LUT5M /* \N184_7[5] */ #( .INIT(32'b11001010110010101111101000001010)) \N184_7[5] ( - .Z (_N24729), + .Z (_N24490), .I0 (\old_row_addr_array[4] [5] ), .I1 (\old_row_addr_array[6] [5] ), .I2 (pre_addr[25]), @@ -197213,7 +196966,7 @@ module ipsxb_mcdq_ui_axi_v1_2 GTP_LUT5M /* \N184_7[6] */ #( .INIT(32'b11001010110010101111101000001010)) \N184_7[6] ( - .Z (_N24730), + .Z (_N24491), .I0 (\old_row_addr_array[4] [6] ), .I1 (\old_row_addr_array[6] [6] ), .I2 (pre_addr[25]), @@ -197225,7 +196978,7 @@ module ipsxb_mcdq_ui_axi_v1_2 GTP_LUT5M /* \N184_7[7] */ #( .INIT(32'b11001010110010101111101000001010)) \N184_7[7] ( - .Z (_N24731), + .Z (_N24492), .I0 (\old_row_addr_array[4] [7] ), .I1 (\old_row_addr_array[6] [7] ), .I2 (pre_addr[25]), @@ -197237,7 +196990,7 @@ module ipsxb_mcdq_ui_axi_v1_2 GTP_LUT5M /* \N184_7[8] */ #( .INIT(32'b11001010110010101111101000001010)) \N184_7[8] ( - .Z (_N24732), + .Z (_N24493), .I0 (\old_row_addr_array[4] [8] ), .I1 (\old_row_addr_array[6] [8] ), .I2 (pre_addr[25]), @@ -197249,7 +197002,7 @@ module ipsxb_mcdq_ui_axi_v1_2 GTP_LUT5M /* \N184_7[9] */ #( .INIT(32'b11001010110010101111101000001010)) \N184_7[9] ( - .Z (_N24733), + .Z (_N24494), .I0 (\old_row_addr_array[4] [9] ), .I1 (\old_row_addr_array[6] [9] ), .I2 (pre_addr[25]), @@ -197261,7 +197014,7 @@ module ipsxb_mcdq_ui_axi_v1_2 GTP_LUT5M /* \N184_7[10] */ #( .INIT(32'b11001010110010101111101000001010)) \N184_7[10] ( - .Z (_N24734), + .Z (_N24495), .I0 (\old_row_addr_array[4] [10] ), .I1 (\old_row_addr_array[6] [10] ), .I2 (pre_addr[25]), @@ -197273,7 +197026,7 @@ module ipsxb_mcdq_ui_axi_v1_2 GTP_LUT5M /* \N184_7[11] */ #( .INIT(32'b11001010110010101111101000001010)) \N184_7[11] ( - .Z (_N24735), + .Z (_N24496), .I0 (\old_row_addr_array[4] [11] ), .I1 (\old_row_addr_array[6] [11] ), .I2 (pre_addr[25]), @@ -197285,7 +197038,7 @@ module ipsxb_mcdq_ui_axi_v1_2 GTP_LUT5M /* \N184_7[12] */ #( .INIT(32'b11001010110010101111101000001010)) \N184_7[12] ( - .Z (_N24736), + .Z (_N24497), .I0 (\old_row_addr_array[4] [12] ), .I1 (\old_row_addr_array[6] [12] ), .I2 (pre_addr[25]), @@ -197297,7 +197050,7 @@ module ipsxb_mcdq_ui_axi_v1_2 GTP_LUT5M /* \N184_7[13] */ #( .INIT(32'b11001010110010101111101000001010)) \N184_7[13] ( - .Z (_N24737), + .Z (_N24498), .I0 (\old_row_addr_array[4] [13] ), .I1 (\old_row_addr_array[6] [13] ), .I2 (pre_addr[25]), @@ -197309,7 +197062,7 @@ module ipsxb_mcdq_ui_axi_v1_2 GTP_LUT5M /* \N184_7[14] */ #( .INIT(32'b11001010110010101111101000001010)) \N184_7[14] ( - .Z (_N24738), + .Z (_N24499), .I0 (\old_row_addr_array[4] [14] ), .I1 (\old_row_addr_array[6] [14] ), .I2 (pre_addr[25]), @@ -197320,92 +197073,92 @@ module ipsxb_mcdq_ui_axi_v1_2 GTP_MUX2LUT6 \N184_8[0] ( .Z (old_row_addr[0]), - .I0 (_N24724), - .I1 (_N24679), + .I0 (_N24485), + .I1 (_N24440), .S (pre_addr[24])); GTP_MUX2LUT6 \N184_8[1] ( .Z (old_row_addr[1]), - .I0 (_N24725), - .I1 (_N24680), + .I0 (_N24486), + .I1 (_N24441), .S (pre_addr[24])); GTP_MUX2LUT6 \N184_8[2] ( .Z (old_row_addr[2]), - .I0 (_N24726), - .I1 (_N24681), + .I0 (_N24487), + .I1 (_N24442), .S (pre_addr[24])); GTP_MUX2LUT6 \N184_8[3] ( .Z (old_row_addr[3]), - .I0 (_N24727), - .I1 (_N24682), + .I0 (_N24488), + .I1 (_N24443), .S (pre_addr[24])); GTP_MUX2LUT6 \N184_8[4] ( .Z (old_row_addr[4]), - .I0 (_N24728), - .I1 (_N24683), + .I0 (_N24489), + .I1 (_N24444), .S (pre_addr[24])); GTP_MUX2LUT6 \N184_8[5] ( .Z (old_row_addr[5]), - .I0 (_N24729), - .I1 (_N24684), + .I0 (_N24490), + .I1 (_N24445), .S (pre_addr[24])); GTP_MUX2LUT6 \N184_8[6] ( .Z (old_row_addr[6]), - .I0 (_N24730), - .I1 (_N24685), + .I0 (_N24491), + .I1 (_N24446), .S (pre_addr[24])); GTP_MUX2LUT6 \N184_8[7] ( .Z (old_row_addr[7]), - .I0 (_N24731), - .I1 (_N24686), + .I0 (_N24492), + .I1 (_N24447), .S (pre_addr[24])); GTP_MUX2LUT6 \N184_8[8] ( .Z (old_row_addr[8]), - .I0 (_N24732), - .I1 (_N24687), + .I0 (_N24493), + .I1 (_N24448), .S (pre_addr[24])); GTP_MUX2LUT6 \N184_8[9] ( .Z (old_row_addr[9]), - .I0 (_N24733), - .I1 (_N24688), + .I0 (_N24494), + .I1 (_N24449), .S (pre_addr[24])); GTP_MUX2LUT6 \N184_8[10] ( .Z (old_row_addr[10]), - .I0 (_N24734), - .I1 (_N24689), + .I0 (_N24495), + .I1 (_N24450), .S (pre_addr[24])); GTP_MUX2LUT6 \N184_8[11] ( .Z (old_row_addr[11]), - .I0 (_N24735), - .I1 (_N24690), + .I0 (_N24496), + .I1 (_N24451), .S (pre_addr[24])); GTP_MUX2LUT6 \N184_8[12] ( .Z (old_row_addr[12]), - .I0 (_N24736), - .I1 (_N24691), + .I0 (_N24497), + .I1 (_N24452), .S (pre_addr[24])); GTP_MUX2LUT6 \N184_8[13] ( .Z (old_row_addr[13]), - .I0 (_N24737), - .I1 (_N24692), + .I0 (_N24498), + .I1 (_N24453), .S (pre_addr[24])); GTP_MUX2LUT6 \N184_8[14] ( .Z (old_row_addr[14]), - .I0 (_N24738), - .I1 (_N24693), + .I0 (_N24499), + .I1 (_N24454), .S (pre_addr[24])); GTP_LUT5CARRY /* \N185.eq_0 */ #( @@ -197684,117 +197437,125 @@ module ipsxb_mcdq_ui_axi_v1_2 // LUT = (~I0&I1)|(I0&~I2&I3)|(I0&I2&I4) ; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_ui_axi_v1_2.vp:448 - GTP_LUT5M /* \N239_3[1] */ #( + GTP_LUT5M /* \N239_3[0] */ #( .INIT(32'b11010101000101011110101000101010)) - \N239_3[1] ( - .Z (N239[1]), - .I0 (data_out[12]), + \N239_3[0] ( + .Z (N239[0]), + .I0 (data_out[11]), .I1 (double_wr), .I2 (N63), - .I3 (next_len[1]), + .I3 (next_len[0]), .I4 (column_addr_end[10]), .ID (data_out[0])); // LUT = (ID&~I2&~I4)|(ID&~I1&~I4)|(~I0&~I2&I4)|(~I0&~I1&I4)|(I1&I2&I3) ; - GTP_LUT5M /* \N239_3[2] */ #( + GTP_LUT5M /* \N239_3[1] */ #( .INIT(32'b11010101000101011110101000101010)) - \N239_3[2] ( - .Z (N239[2]), - .I0 (data_out[13]), + \N239_3[1] ( + .Z (N239[1]), + .I0 (data_out[12]), .I1 (double_wr), .I2 (N63), - .I3 (next_len[2]), + .I3 (next_len[1]), .I4 (column_addr_end[10]), .ID (data_out[0])); // LUT = (ID&~I2&~I4)|(ID&~I1&~I4)|(~I0&~I2&I4)|(~I0&~I1&I4)|(I1&I2&I3) ; - GTP_LUT4 /* N254 */ #( - .INIT(16'b0000000000001000)) + GTP_LUT5 /* N254 */ #( + .INIT(32'b00000000000000000000000010000000)) N254_vname ( .Z (N254), - .I0 (N63), - .I1 (pre_addr[24]), - .I2 (pre_addr[25]), - .I3 (pre_addr[26])); + .I0 (pre_data_in_ready), + .I1 (pre_data_in_valid), + .I2 (pre_addr[24]), + .I3 (pre_addr[25]), + .I4 (pre_addr[26])); // defparam N254_vname.orig_name = N254; - // LUT = I0&I1&~I2&~I3 ; + // LUT = I0&I1&I2&~I3&~I4 ; - GTP_LUT4 /* N258 */ #( - .INIT(16'b0000000000100000)) + GTP_LUT5 /* N258 */ #( + .INIT(32'b00000000000000000000100000000000)) N258_vname ( .Z (N258), - .I0 (N63), - .I1 (pre_addr[24]), - .I2 (pre_addr[25]), - .I3 (pre_addr[26])); + .I0 (pre_data_in_ready), + .I1 (pre_data_in_valid), + .I2 (pre_addr[24]), + .I3 (pre_addr[25]), + .I4 (pre_addr[26])); // defparam N258_vname.orig_name = N258; - // LUT = I0&~I1&I2&~I3 ; + // LUT = I0&I1&~I2&I3&~I4 ; - GTP_LUT4 /* N262 */ #( - .INIT(16'b0000000010000000)) + GTP_LUT5 /* N262 */ #( + .INIT(32'b00000000000000001000000000000000)) N262_vname ( .Z (N262), - .I0 (N63), - .I1 (pre_addr[24]), - .I2 (pre_addr[25]), - .I3 (pre_addr[26])); + .I0 (pre_data_in_ready), + .I1 (pre_data_in_valid), + .I2 (pre_addr[24]), + .I3 (pre_addr[25]), + .I4 (pre_addr[26])); // defparam N262_vname.orig_name = N262; - // LUT = I0&I1&I2&~I3 ; + // LUT = I0&I1&I2&I3&~I4 ; - GTP_LUT4 /* N266 */ #( - .INIT(16'b0000001000000000)) + GTP_LUT5 /* N266 */ #( + .INIT(32'b00000000000010000000000000000000)) N266_vname ( .Z (N266), - .I0 (N63), - .I1 (pre_addr[24]), - .I2 (pre_addr[25]), - .I3 (pre_addr[26])); + .I0 (pre_data_in_ready), + .I1 (pre_data_in_valid), + .I2 (pre_addr[24]), + .I3 (pre_addr[25]), + .I4 (pre_addr[26])); // defparam N266_vname.orig_name = N266; - // LUT = I0&~I1&~I2&I3 ; + // LUT = I0&I1&~I2&~I3&I4 ; - GTP_LUT4 /* N270 */ #( - .INIT(16'b0000100000000000)) + GTP_LUT5 /* N270 */ #( + .INIT(32'b00000000100000000000000000000000)) N270_vname ( .Z (N270), - .I0 (N63), - .I1 (pre_addr[24]), - .I2 (pre_addr[25]), - .I3 (pre_addr[26])); + .I0 (pre_data_in_ready), + .I1 (pre_data_in_valid), + .I2 (pre_addr[24]), + .I3 (pre_addr[25]), + .I4 (pre_addr[26])); // defparam N270_vname.orig_name = N270; - // LUT = I0&I1&~I2&I3 ; + // LUT = I0&I1&I2&~I3&I4 ; - GTP_LUT4 /* N274 */ #( - .INIT(16'b0010000000000000)) + GTP_LUT5 /* N274 */ #( + .INIT(32'b00001000000000000000000000000000)) N274_vname ( .Z (N274), - .I0 (N63), - .I1 (pre_addr[24]), - .I2 (pre_addr[25]), - .I3 (pre_addr[26])); + .I0 (pre_data_in_ready), + .I1 (pre_data_in_valid), + .I2 (pre_addr[24]), + .I3 (pre_addr[25]), + .I4 (pre_addr[26])); // defparam N274_vname.orig_name = N274; - // LUT = I0&~I1&I2&I3 ; + // LUT = I0&I1&~I2&I3&I4 ; - GTP_LUT4 /* N278 */ #( - .INIT(16'b1000000000000000)) + GTP_LUT5 /* N278 */ #( + .INIT(32'b10000000000000000000000000000000)) N278_vname ( .Z (N278), - .I0 (N63), - .I1 (pre_addr[24]), - .I2 (pre_addr[25]), - .I3 (pre_addr[26])); + .I0 (pre_data_in_ready), + .I1 (pre_data_in_valid), + .I2 (pre_addr[24]), + .I3 (pre_addr[25]), + .I4 (pre_addr[26])); // defparam N278_vname.orig_name = N278; - // LUT = I0&I1&I2&I3 ; + // LUT = I0&I1&I2&I3&I4 ; - GTP_LUT4 /* N282 */ #( - .INIT(16'b0000000000000010)) + GTP_LUT5 /* N282 */ #( + .INIT(32'b00000000000000000000000000001000)) N282_vname ( .Z (N282), - .I0 (N63), - .I1 (pre_addr[24]), - .I2 (pre_addr[25]), - .I3 (pre_addr[26])); + .I0 (pre_data_in_ready), + .I1 (pre_data_in_valid), + .I2 (pre_addr[24]), + .I3 (pre_addr[25]), + .I4 (pre_addr[26])); // defparam N282_vname.orig_name = N282; - // LUT = I0&~I1&~I2&~I3 ; + // LUT = I0&I1&~I2&~I3&~I4 ; GTP_LUT5CARRY /* column_addr_end_1_2 */ #( .INIT(32'b00000000000000000000000000000000), @@ -197803,7 +197564,7 @@ module ipsxb_mcdq_ui_axi_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) column_addr_end_1_2 ( - .COUT (_N15195), + .COUT (_N15241), .Z (), .CIN (), .I0 (), @@ -197823,9 +197584,9 @@ module ipsxb_mcdq_ui_axi_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) column_addr_end_1_3 ( - .COUT (_N15196), + .COUT (_N15242), .Z (), - .CIN (_N15195), + .CIN (_N15241), .I0 (data_out[0]), .I1 (data_out[11]), .I2 (data_out[12]), @@ -197843,9 +197604,9 @@ module ipsxb_mcdq_ui_axi_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) column_addr_end_1_4 ( - .COUT (_N15197), + .COUT (_N15243), .Z (), - .CIN (_N15196), + .CIN (_N15242), .I0 (), .I1 (\mcdq_reg_fifo2/rptr ), .I2 (\mcdq_reg_fifo2/data_0 [14] ), @@ -197863,9 +197624,9 @@ module ipsxb_mcdq_ui_axi_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) column_addr_end_1_5 ( - .COUT (_N15198), + .COUT (_N15244), .Z (), - .CIN (_N15197), + .CIN (_N15243), .I0 (), .I1 (\mcdq_reg_fifo2/rptr ), .I2 (\mcdq_reg_fifo2/data_0 [15] ), @@ -197883,9 +197644,9 @@ module ipsxb_mcdq_ui_axi_v1_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) column_addr_end_1_6 ( - .COUT (_N15199), + .COUT (_N15245), .Z (), - .CIN (_N15198), + .CIN (_N15244), .I0 (), .I1 (\mcdq_reg_fifo2/rptr ), .I2 (\mcdq_reg_fifo2/data_0 [16] ), @@ -197905,7 +197666,7 @@ module ipsxb_mcdq_ui_axi_v1_2 column_addr_end_1_7 ( .COUT (column_addr_end[10]), .Z (), - .CIN (_N15199), + .CIN (_N15245), .I0 (), .I1 (\mcdq_reg_fifo2/rptr ), .I2 (\mcdq_reg_fifo2/data_0 [17] ), @@ -197924,14 +197685,14 @@ module ipsxb_mcdq_ui_axi_v1_2 .C (N1), .CE (N228), .CLK (clk), - .D (_N66672)); + .D (_N67679)); // defparam double_wr_vname.orig_name = double_wr; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_ui_axi_v1_2.vp:448 - GTP_LUT2 /* double_wr_4002 */ #( + GTP_LUT2 /* double_wr_4041 */ #( .INIT(4'b0100)) - double_wr_4002 ( - .Z (_N66672), + double_wr_4041 ( + .Z (_N67679), .I0 (double_wr), .I1 (column_addr_end[10])); // LUT = ~I0&I1 ; @@ -197940,7 +197701,7 @@ module ipsxb_mcdq_ui_axi_v1_2 .data_0 ({\mcdq_reg_fifo2_data_0[37]_floating , \mcdq_reg_fifo2_data_0[36]_floating , \mcdq_reg_fifo2_data_0[35]_floating , \mcdq_reg_fifo2_data_0[34]_floating , \mcdq_reg_fifo2_data_0[33]_floating , \mcdq_reg_fifo2_data_0[32]_floating , \mcdq_reg_fifo2_data_0[31]_floating , \mcdq_reg_fifo2_data_0[30]_floating , \mcdq_reg_fifo2_data_0[29]_floating , \mcdq_reg_fifo2_data_0[28]_floating , \mcdq_reg_fifo2_data_0[27]_floating , \mcdq_reg_fifo2_data_0[26]_floating , \mcdq_reg_fifo2_data_0[25]_floating , \mcdq_reg_fifo2_data_0[24]_floating , \mcdq_reg_fifo2_data_0[23]_floating , \mcdq_reg_fifo2_data_0[22]_floating , \mcdq_reg_fifo2_data_0[21]_floating , \mcdq_reg_fifo2_data_0[20]_floating , \mcdq_reg_fifo2_data_0[19]_floating , \mcdq_reg_fifo2_data_0[18]_floating , \mcdq_reg_fifo2/data_0 [17] , \mcdq_reg_fifo2/data_0 [16] , \mcdq_reg_fifo2/data_0 [15] , \mcdq_reg_fifo2/data_0 [14] , \mcdq_reg_fifo2/data_0 [13] , \mcdq_reg_fifo2/data_0 [12] , \mcdq_reg_fifo2/data_0 [11] , \mcdq_reg_fifo2/data_0 [10] , \mcdq_reg_fifo2/data_0 [9] , \mcdq_reg_fifo2/data_0 [8] , \mcdq_reg_fifo2_data_0[7]_floating , \mcdq_reg_fifo2_data_0[6]_floating , \mcdq_reg_fifo2_data_0[5]_floating , \mcdq_reg_fifo2_data_0[4]_floating , \mcdq_reg_fifo2_data_0[3]_floating , \mcdq_reg_fifo2_data_0[2]_floating , \mcdq_reg_fifo2_data_0[1]_floating , \mcdq_reg_fifo2/data_0 [0] }), .data_1 ({\mcdq_reg_fifo2_data_1[37]_floating , \mcdq_reg_fifo2_data_1[36]_floating , \mcdq_reg_fifo2_data_1[35]_floating , \mcdq_reg_fifo2_data_1[34]_floating , \mcdq_reg_fifo2_data_1[33]_floating , \mcdq_reg_fifo2_data_1[32]_floating , \mcdq_reg_fifo2_data_1[31]_floating , \mcdq_reg_fifo2_data_1[30]_floating , \mcdq_reg_fifo2_data_1[29]_floating , \mcdq_reg_fifo2_data_1[28]_floating , \mcdq_reg_fifo2_data_1[27]_floating , \mcdq_reg_fifo2_data_1[26]_floating , \mcdq_reg_fifo2_data_1[25]_floating , \mcdq_reg_fifo2_data_1[24]_floating , \mcdq_reg_fifo2_data_1[23]_floating , \mcdq_reg_fifo2_data_1[22]_floating , \mcdq_reg_fifo2_data_1[21]_floating , \mcdq_reg_fifo2_data_1[20]_floating , \mcdq_reg_fifo2_data_1[19]_floating , \mcdq_reg_fifo2_data_1[18]_floating , \mcdq_reg_fifo2/data_1 [17] , \mcdq_reg_fifo2/data_1 [16] , \mcdq_reg_fifo2/data_1 [15] , \mcdq_reg_fifo2/data_1 [14] , \mcdq_reg_fifo2/data_1 [13] , \mcdq_reg_fifo2/data_1 [12] , \mcdq_reg_fifo2/data_1 [11] , \mcdq_reg_fifo2/data_1 [10] , \mcdq_reg_fifo2/data_1 [9] , \mcdq_reg_fifo2/data_1 [8] , \mcdq_reg_fifo2_data_1[7]_floating , \mcdq_reg_fifo2_data_1[6]_floating , \mcdq_reg_fifo2_data_1[5]_floating , \mcdq_reg_fifo2_data_1[4]_floating , \mcdq_reg_fifo2_data_1[3]_floating , \mcdq_reg_fifo2_data_1[2]_floating , \mcdq_reg_fifo2_data_1[1]_floating , \mcdq_reg_fifo2/data_1 [0] }), .data_out ({data_out[37], \mcdq_reg_fifo2_data_out[36]_floating , data_out[35], data_out[34], data_out[33], data_out[32], data_out[31], data_out[30], data_out[29], data_out[28], data_out[27], data_out[26], data_out[25], data_out[24], data_out[23], data_out[22], data_out[21], data_out[20], data_out[19], data_out[18], data_out[17], data_out[16], \mcdq_reg_fifo2_data_out[15]_floating , \mcdq_reg_fifo2_data_out[14]_floating , data_out[13], data_out[12], data_out[11], \mcdq_reg_fifo2_data_out[10]_floating , \mcdq_reg_fifo2_data_out[9]_floating , \mcdq_reg_fifo2_data_out[8]_floating , data_out[7], data_out[6], data_out[5], data_out[4], \mcdq_reg_fifo2_data_out[3]_floating , \mcdq_reg_fifo2_data_out[2]_floating , \mcdq_reg_fifo2_data_out[1]_floating , \mcdq_reg_fifo2_data_out[0]_floating }), - .data_in ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, ui_addr[21], ui_addr[20], 1'bx, 1'bx, ui_addr[17], 1'bx, 1'bx, 1'bx, 1'bx, ui_addr[12], ui_addr[11], 1'bx, 1'bx, ui_addr[8], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), + .data_in ({1'bx, 1'bx, 1'bx, ui_addr[26], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, ui_addr[17], ui_addr[16], 1'bx, 1'bx, ui_addr[13], 1'bx, 1'bx, 1'bx, 1'bx, ui_addr[8], ui_addr[7], 1'bx, 1'bx, ui_addr[4], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), .\u_axi_ddr_top/awaddr_ddr_fifo_dout ({1'bx, 1'bx, axi_awaddr[27], axi_awaddr[26], axi_awaddr[25], axi_awaddr[24], axi_awaddr[23], axi_awaddr[22], axi_awaddr[21], axi_awaddr[20], axi_awaddr[19], axi_awaddr[18], axi_awaddr[17], axi_awaddr[16], axi_awaddr[15], axi_awaddr[14], axi_awaddr[13], axi_awaddr[12], axi_awaddr[11], axi_awaddr[10], axi_awaddr[9], axi_awaddr[8], axi_awaddr[7], axi_awaddr[6], axi_awaddr[5], axi_awaddr[4], axi_awaddr[3], axi_awaddr[2], axi_awaddr[1], axi_awaddr[0], 1'bx, 1'bx}), .\u_axi_ddr_top/rd_sta ({1'bx, \u_axi_ddr_top/rd_sta [7] , 1'bx, 1'bx, 1'bx, \u_axi_ddr_top/rd_sta [3] , 1'bx, \u_axi_ddr_top/rd_sta [1] , 1'bx}), .\u_axi_ddr_top/s_axi_araddr ({axi_araddr[27], axi_araddr[26], axi_araddr[25], axi_araddr[24], axi_araddr[23], axi_araddr[22], axi_araddr[21], axi_araddr[20], axi_araddr[19], axi_araddr[18], axi_araddr[17], axi_araddr[16], axi_araddr[15], axi_araddr[14], axi_araddr[13], axi_araddr[12], axi_araddr[11], axi_araddr[10], axi_araddr[9], axi_araddr[8], axi_araddr[7], axi_araddr[6], axi_araddr[5], axi_araddr[4], axi_araddr[3], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), @@ -199636,29 +199397,20 @@ module ipsxb_mcdq_ui_axi_v1_2 .Q (pre_data_in_valid), .C (N1), .CLK (clk), - .D (_N103430)); + .D (_N104242)); // defparam pre_data_in_valid_vname.orig_name = pre_data_in_valid; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_ui_axi_v1_2.vp:448 - GTP_LUT3 /* pre_data_in_valid_0 */ #( - .INIT(8'b11111110)) - pre_data_in_valid_0 ( - .Z (_N70208), - .I0 (double_wr), - .I1 (\mcdq_reg_fifo2/data_valid_1 ), - .I2 (\mcdq_reg_fifo2/data_valid_0 )); - // LUT = (I0)|(I1)|(I2) ; - GTP_LUT5 /* pre_data_in_valid_ce_mux */ #( - .INIT(32'b10111000101010001010100010101000)) + .INIT(32'b11110100111101001111010010110000)) pre_data_in_valid_ce_mux ( - .Z (_N103430), - .I0 (_N70208), - .I1 (N54), + .Z (_N104242), + .I0 (double_wr), + .I1 (pre_data_in_ready), .I2 (pre_data_in_valid), - .I3 (\u_user_cmd_fifo/data_valid_0 ), - .I4 (\u_user_cmd_fifo/data_valid_1 )); - // LUT = (I0&I1)|(I0&I2)|(~I1&I2&I3&I4) ; + .I3 (\mcdq_reg_fifo2/data_valid_1 ), + .I4 (\mcdq_reg_fifo2/data_valid_0 )); + // LUT = (~I1&I2)|(I0&I2)|(~I0&I1&I3)|(~I0&I1&I4) ; GTP_DFF_CE /* \pre_id[0] */ #( .GRS_EN("TRUE"), @@ -199712,7 +199464,7 @@ module ipsxb_mcdq_ui_axi_v1_2 .C (N1), .CE (N228), .CLK (clk), - .D (_N70258)); + .D (N239[0])); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_ui_axi_v1_2.vp:448 GTP_DFF_CE /* \pre_len[1] */ #( @@ -199734,24 +199486,24 @@ module ipsxb_mcdq_ui_axi_v1_2 .C (N1), .CE (N228), .CLK (clk), - .D (N239[2])); + .D (_N71475)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_ui_axi_v1_2.vp:448 GTP_LUT5 /* \pre_len[3:0]_0 */ #( .INIT(32'b10111010111111100001000001010100)) \pre_len[3:0]_0 ( - .Z (_N70258), + .Z (_N71475), .I0 (double_wr), .I1 (column_addr_end[10]), .I2 (data_out[0]), - .I3 (data_out[11]), - .I4 (next_len[0])); + .I3 (data_out[13]), + .I4 (next_len[2])); // LUT = (I0&I4)|(~I0&I1&~I3)|(~I0&~I1&I2) ; GTP_LUT5M /* \pre_len[3:0]_1 */ #( .INIT(32'b10101010101010100000001010001010)) \pre_len[3:0]_1 ( - .Z (_N70674), + .Z (_N71602), .I0 (next_len[3]), .I1 (\mcdq_reg_fifo2/rptr ), .I2 (\mcdq_reg_fifo2/data_0 [14] ), @@ -199777,7 +199529,7 @@ module ipsxb_mcdq_ui_axi_v1_2 .C (N1), .CE (N228), .CLK (clk), - .D (_N70674)); + .D (_N71602)); // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_ui_axi_v1_2.vp:448 GTP_DFF_CE /* pre_write */ #( @@ -199799,14 +199551,14 @@ module ipsxb_mcdq_ui_axi_v1_2 .Q (ptr), .C (N1), .CLK (clk), - .D (_N103428)); + .D (_N104240)); // defparam ptr_vname.orig_name = ptr; // ../ipcore/axi_ddr/rtl/mcdq_ctrl/ipsxb_mcdq_ui_axi_v1_2.vp:362 GTP_LUT5 /* ptr_ce_mux */ #( .INIT(32'b11110000000111100001111000011110)) ptr_ce_mux ( - .Z (_N103428), + .Z (_N104240), .I0 (axi_arvalid), .I1 (axi_awvalid), .I2 (ptr), @@ -199819,6 +199571,7 @@ module ipsxb_mcdq_ui_axi_v1_2 .data_1 ({\u_user_cmd_fifo/data_1 [54] , \u_user_cmd_fifo/data_1 [53] , \u_user_cmd_fifo/data_1 [52] , \u_user_cmd_fifo/data_1 [51] , \u_user_cmd_fifo/data_1 [50] , \u_user_cmd_fifo/data_1 [49] , \u_user_cmd_fifo/data_1 [48] , \u_user_cmd_fifo/data_1 [47] , \u_user_cmd_fifo/data_1 [46] , \u_user_cmd_fifo/data_1 [45] , \u_user_cmd_fifo/data_1 [44] , \u_user_cmd_fifo/data_1 [43] , \u_user_cmd_fifo/data_1 [42] , \u_user_cmd_fifo/data_1 [41] , \u_user_cmd_fifo/data_1 [40] , \u_user_cmd_fifo/data_1 [39] , \u_user_cmd_fifo_data_1[38]_floating , \u_user_cmd_fifo/data_1 [37] , \u_user_cmd_fifo_data_1[36]_floating , \u_user_cmd_fifo/data_1 [35] , \u_user_cmd_fifo/data_1 [34] , \u_user_cmd_fifo/data_1 [33] , \u_user_cmd_fifo/data_1 [32] , \u_user_cmd_fifo/data_1 [31] , \u_user_cmd_fifo/data_1 [30] , \u_user_cmd_fifo/data_1 [29] , \u_user_cmd_fifo/data_1 [28] , \u_user_cmd_fifo/data_1 [27] , \u_user_cmd_fifo/data_1 [26] , \u_user_cmd_fifo/data_1 [25] , \u_user_cmd_fifo/data_1 [24] , \u_user_cmd_fifo/data_1 [23] , \u_user_cmd_fifo/data_1 [22] , \u_user_cmd_fifo/data_1 [21] , \u_user_cmd_fifo/data_1 [20] , \u_user_cmd_fifo/data_1 [19] , \u_user_cmd_fifo/data_1 [18] , \u_user_cmd_fifo/data_1 [17] , \u_user_cmd_fifo/data_1 [16] , \u_user_cmd_fifo/data_1 [15] , \u_user_cmd_fifo/data_1 [14] , \u_user_cmd_fifo/data_1 [13] , \u_user_cmd_fifo/data_1 [12] , \u_user_cmd_fifo/data_1 [11] , \u_user_cmd_fifo/data_1 [10] , \u_user_cmd_fifo/data_1 [9] , \u_user_cmd_fifo/data_1 [8] , \u_user_cmd_fifo/data_1 [7] , \u_user_cmd_fifo/data_1 [6] , \u_user_cmd_fifo/data_1 [5] , \u_user_cmd_fifo/data_1 [4] , \u_user_cmd_fifo/data_1 [3] , \u_user_cmd_fifo/data_1 [2] , \u_user_cmd_fifo/data_1 [1] , \u_user_cmd_fifo/data_1 [0] }), .data_out ({\u_user_cmd_fifo_data_out[54]_floating , \u_user_cmd_fifo_data_out[53]_floating , \u_user_cmd_fifo_data_out[52]_floating , \u_user_cmd_fifo_data_out[51]_floating , \u_user_cmd_fifo_data_out[50]_floating , \u_user_cmd_fifo_data_out[49]_floating , \u_user_cmd_fifo_data_out[48]_floating , \u_user_cmd_fifo_data_out[47]_floating , \u_user_cmd_fifo_data_out[46]_floating , \u_user_cmd_fifo_data_out[45]_floating , \u_user_cmd_fifo_data_out[44]_floating , \u_user_cmd_fifo_data_out[43]_floating , \u_user_cmd_fifo_data_out[42]_floating , \u_user_cmd_fifo_data_out[41]_floating , \u_user_cmd_fifo_data_out[40]_floating , \u_user_cmd_fifo_data_out[39]_floating , \u_user_cmd_fifo_data_out[38]_floating , \u_user_cmd_fifo_data_out[37]_floating , \u_user_cmd_fifo_data_out[36]_floating , user_addr[27], user_addr[26], user_addr[25], user_addr[24], user_addr[23], user_addr[22], user_addr[21], user_addr[20], user_addr[19], user_addr[18], user_addr[17], user_addr[16], user_addr[15], user_addr[14], user_addr[13], user_addr[12], user_addr[11], user_addr[10], \u_user_cmd_fifo_data_out[17]_floating , \u_user_cmd_fifo_data_out[16]_floating , \u_user_cmd_fifo_data_out[15]_floating , \u_user_cmd_fifo_data_out[14]_floating , \u_user_cmd_fifo_data_out[13]_floating , \u_user_cmd_fifo_data_out[12]_floating , \u_user_cmd_fifo_data_out[11]_floating , \u_user_cmd_fifo_data_out[10]_floating , \u_user_cmd_fifo_data_out[9]_floating , \u_user_cmd_fifo_data_out[8]_floating , \u_user_cmd_fifo_data_out[7]_floating , \u_user_cmd_fifo_data_out[6]_floating , \u_user_cmd_fifo_data_out[5]_floating , \u_user_cmd_fifo_data_out[4]_floating , \u_user_cmd_fifo_data_out[3]_floating , user_len[2], \u_user_cmd_fifo_data_out[1]_floating , \u_user_cmd_fifo_data_out[0]_floating }), .data_in ({old_row_addr[14], old_row_addr[13], old_row_addr[12], old_row_addr[11], old_row_addr[10], old_row_addr[9], old_row_addr[8], old_row_addr[7], old_row_addr[6], old_row_addr[5], old_row_addr[4], old_row_addr[3], old_row_addr[2], old_row_addr[1], old_row_addr[0], row_addr_diff, 1'bx, pre_write, 1'bx, pre_addr[23], pre_addr[22], pre_addr[21], pre_addr[20], pre_addr[19], pre_addr[18], pre_addr[17], pre_addr[16], pre_addr[15], pre_addr[14], pre_addr[13], pre_addr[12], pre_addr[11], pre_addr[10], pre_addr[27], pre_addr[26], pre_addr[25], pre_addr[24], pre_addr[9], pre_addr[8], pre_addr[7], pre_addr[6], pre_addr[5], pre_addr[4], pre_addr[3], pre_addr[2], pre_addr[1], pre_addr[0], pre_id[3], pre_id[2], pre_id[1], pre_id[0], pre_len[3], pre_len[2], pre_len[1], pre_len[0]}), + .data_in_ready (pre_data_in_ready), .data_valid_0 (\u_user_cmd_fifo/data_valid_0 ), .data_valid_1 (\u_user_cmd_fifo/data_valid_1 ), .rptr (\u_user_cmd_fifo/rptr ), @@ -199887,14 +199640,14 @@ module ipsxb_distributed_fifo_ctr_v1_0 wire N17; wire N36; wire [5:0] \N36.co ; - wire _N15025; - wire _N15026; - wire _N15027; - wire _N15028; - wire _N15031; - wire _N15032; - wire _N15033; - wire _N15034; + wire _N15008; + wire _N15009; + wire _N15010; + wire _N15011; + wire _N15014; + wire _N15015; + wire _N15016; + wire _N15017; wire rempty; wire [4:0] rgnext; wire [4:0] rwptr2_b; @@ -199908,7 +199661,7 @@ module ipsxb_distributed_fifo_ctr_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_1 ( - .COUT (_N15025), + .COUT (_N15008), .Z (N2[0]), .CIN (), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/wvld_l ), @@ -199928,9 +199681,9 @@ module ipsxb_distributed_fifo_ctr_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_2 ( - .COUT (_N15026), + .COUT (_N15009), .Z (N2[1]), - .CIN (_N15025), + .CIN (_N15008), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/wvld_l ), .I1 (wr_addr[0]), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/wvld_m ), @@ -199948,9 +199701,9 @@ module ipsxb_distributed_fifo_ctr_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_3 ( - .COUT (_N15027), + .COUT (_N15010), .Z (N2[2]), - .CIN (_N15026), + .CIN (_N15009), .I0 (), .I1 (wr_addr[2]), .I2 (), @@ -199968,9 +199721,9 @@ module ipsxb_distributed_fifo_ctr_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_4 ( - .COUT (_N15028), + .COUT (_N15011), .Z (N2[3]), - .CIN (_N15027), + .CIN (_N15010), .I0 (), .I1 (rwptr2_b[3]), .I2 (), @@ -199990,7 +199743,7 @@ module ipsxb_distributed_fifo_ctr_v1_0 N2_5 ( .COUT (), .Z (N2[4]), - .CIN (_N15028), + .CIN (_N15011), .I0 (), .I1 (rwptr2_b[4]), .I2 (), @@ -200063,7 +199816,7 @@ module ipsxb_distributed_fifo_ctr_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N9_1 ( - .COUT (_N15031), + .COUT (_N15014), .Z (N9[0]), .CIN (), .I0 (r_en), @@ -200083,9 +199836,9 @@ module ipsxb_distributed_fifo_ctr_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N9_2 ( - .COUT (_N15032), + .COUT (_N15015), .Z (N9[1]), - .CIN (_N15031), + .CIN (_N15014), .I0 (r_en), .I1 (rd_addr[0]), .I2 (rd_addr[1]), @@ -200103,9 +199856,9 @@ module ipsxb_distributed_fifo_ctr_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N9_3 ( - .COUT (_N15033), + .COUT (_N15016), .Z (N9[2]), - .CIN (_N15032), + .CIN (_N15015), .I0 (), .I1 (rd_addr[2]), .I2 (), @@ -200123,9 +199876,9 @@ module ipsxb_distributed_fifo_ctr_v1_0 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N9_4 ( - .COUT (_N15034), + .COUT (_N15017), .Z (N9[3]), - .CIN (_N15033), + .CIN (_N15016), .I0 (), .I1 (wrptr2_b[3]), .I2 (), @@ -200145,7 +199898,7 @@ module ipsxb_distributed_fifo_ctr_v1_0 N9_5 ( .COUT (), .Z (N9[4]), - .CIN (_N15034), + .CIN (_N15017), .I0 (), .I1 (wrptr2_b[4]), .I2 (), @@ -208574,7 +208327,6 @@ module axi_ddr input [27:0] axi_awaddr, input [255:0] axi_wdata, input [8:0] \u_axi_ddr_top/rd_sta , - input _N18115, input axi_awvalid, input ddr_rst, input ref_clk, @@ -208587,8 +208339,6 @@ module axi_ddr output [14:0] mem_a, output [2:0] mem_ba, output [3:0] mem_dm, - output [7:0] \u_ddrphy_top/ddrphy_reset_ctrl/cnt , - output [8:0] \u_ddrphy_top/ddrphy_reset_ctrl/state_reg , output [9:0] \u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt , output [7:0] \u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin_div2 , output [9:0] \u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt , @@ -208597,20 +208347,18 @@ module axi_ddr output [7:0] \u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin_div2 , output [9:0] \u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt , output [7:0] \u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin_div2 , - output _N81412_3, - output _N81412_5, - output _N81413_3, - output _N81413_5, - output _N81414_3, - output _N81414_5, - output _N81415_3, - output _N81415_5, - output _N97085, - output _N105268, - output _N105817, - output _N106355, - output _N106490, - output _N106518, + output _N82185_3, + output _N82185_5, + output _N82186_3, + output _N82186_5, + output _N82187_3, + output _N82187_5, + output _N82188_3, + output _N82188_5, + output _N106081, + output _N106639, + output _N107308, + output _N107336, output axi_arready, output axi_awready, output axi_wready, @@ -208626,7 +208374,6 @@ module axi_ddr output mem_rst_n, output mem_we_n, output \u_ddrphy_top/calib_done , - output \u_ddrphy_top/ddrphy_reset_ctrl/N137 , output \u_ddrphy_top/read_valid , inout [31:0] mem_dq, inout [3:0] mem_dqs, @@ -208657,21 +208404,6 @@ module axi_ddr wire \u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/rst ; wire [3:0] \u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wdin_en_dly ; wire [31:0] \u_ipsxb_ddrc_top/mcdq_wdatapath/wr_strb ; - wire \u_ddrphy_top_ddrphy_reset_ctrl/cnt[0]_floating ; - wire \u_ddrphy_top_ddrphy_reset_ctrl/cnt[1]_floating ; - wire \u_ddrphy_top_ddrphy_reset_ctrl/cnt[2]_floating ; - wire \u_ddrphy_top_ddrphy_reset_ctrl/cnt[4]_floating ; - wire \u_ddrphy_top_ddrphy_reset_ctrl/cnt[5]_floating ; - wire \u_ddrphy_top_ddrphy_reset_ctrl/cnt[6]_floating ; - wire \u_ddrphy_top_ddrphy_reset_ctrl/cnt[7]_floating ; - wire \u_ddrphy_top_ddrphy_reset_ctrl/state_reg[0]_floating ; - wire \u_ddrphy_top_ddrphy_reset_ctrl/state_reg[1]_floating ; - wire \u_ddrphy_top_ddrphy_reset_ctrl/state_reg[2]_floating ; - wire \u_ddrphy_top_ddrphy_reset_ctrl/state_reg[3]_floating ; - wire \u_ddrphy_top_ddrphy_reset_ctrl/state_reg[4]_floating ; - wire \u_ddrphy_top_ddrphy_reset_ctrl/state_reg[5]_floating ; - wire \u_ddrphy_top_ddrphy_reset_ctrl/state_reg[6]_floating ; - wire \u_ddrphy_top_ddrphy_reset_ctrl/state_reg[8]_floating ; wire \u_ddrphy_top_ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]_floating ; wire \u_ddrphy_top_ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[1]_floating ; wire \u_ddrphy_top_ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[2]_floating ; @@ -208898,8 +208630,6 @@ module axi_ddr .mem_dq (mem_dq), .mem_dqs (mem_dqs), .mem_dqs_n (mem_dqs_n), - .\ddrphy_reset_ctrl/cnt ({\u_ddrphy_top_ddrphy_reset_ctrl/cnt[7]_floating , \u_ddrphy_top_ddrphy_reset_ctrl/cnt[6]_floating , \u_ddrphy_top_ddrphy_reset_ctrl/cnt[5]_floating , \u_ddrphy_top_ddrphy_reset_ctrl/cnt[4]_floating , \u_ddrphy_top/ddrphy_reset_ctrl/cnt [3] , \u_ddrphy_top_ddrphy_reset_ctrl/cnt[2]_floating , \u_ddrphy_top_ddrphy_reset_ctrl/cnt[1]_floating , \u_ddrphy_top_ddrphy_reset_ctrl/cnt[0]_floating }), - .\ddrphy_reset_ctrl/state_reg ({\u_ddrphy_top_ddrphy_reset_ctrl/state_reg[8]_floating , \u_ddrphy_top/ddrphy_reset_ctrl/state_reg [7] , \u_ddrphy_top_ddrphy_reset_ctrl/state_reg[6]_floating , \u_ddrphy_top_ddrphy_reset_ctrl/state_reg[5]_floating , \u_ddrphy_top_ddrphy_reset_ctrl/state_reg[4]_floating , \u_ddrphy_top_ddrphy_reset_ctrl/state_reg[3]_floating , \u_ddrphy_top_ddrphy_reset_ctrl/state_reg[2]_floating , \u_ddrphy_top_ddrphy_reset_ctrl/state_reg[1]_floating , \u_ddrphy_top_ddrphy_reset_ctrl/state_reg[0]_floating }), .\ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt ({\u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [9] , \u_ddrphy_top_ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[8]_floating , \u_ddrphy_top_ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[7]_floating , \u_ddrphy_top_ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[6]_floating , \u_ddrphy_top_ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[5]_floating , \u_ddrphy_top_ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[4]_floating , \u_ddrphy_top_ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[3]_floating , \u_ddrphy_top_ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[2]_floating , \u_ddrphy_top_ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[1]_floating , \u_ddrphy_top_ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]_floating }), .\ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin_div2 ({\u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin_div2 [7] , \u_ddrphy_top_ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin_div2[6]_floating , \u_ddrphy_top_ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin_div2[5]_floating , \u_ddrphy_top_ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin_div2[4]_floating , \u_ddrphy_top_ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin_div2[3]_floating , \u_ddrphy_top_ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin_div2[2]_floating , \u_ddrphy_top_ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin_div2[1]_floating , \u_ddrphy_top_ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin_div2[0]_floating }), .\ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt ({\u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [9] , \u_ddrphy_top_ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[8]_floating , \u_ddrphy_top_ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[7]_floating , \u_ddrphy_top_ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[6]_floating , \u_ddrphy_top_ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[5]_floating , \u_ddrphy_top_ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[4]_floating , \u_ddrphy_top_ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[3]_floating , \u_ddrphy_top_ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[2]_floating , \u_ddrphy_top_ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[1]_floating , \u_ddrphy_top_ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]_floating }), @@ -208924,27 +208654,24 @@ module axi_ddr .dfi_wrdata (dfi_wrdata), .dfi_wrdata_en ({\u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wdin_en_dly [2] , 1'bx, dfi_wrdata_en[1], dfi_wrdata_en[0]}), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/wr_strb ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \u_ipsxb_ddrc_top/mcdq_wdatapath/wr_strb [24] , 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \u_ipsxb_ddrc_top/mcdq_wdatapath/wr_strb [8] , 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \u_ipsxb_ddrc_top/mcdq_wdatapath/wr_strb [0] }), - ._N81412_3 (_N81412_3), - ._N81412_5 (_N81412_5), - ._N81413_3 (_N81413_3), - ._N81413_5 (_N81413_5), - ._N81414_3 (_N81414_3), - ._N81414_5 (_N81414_5), - ._N81415_3 (_N81415_3), - ._N81415_5 (_N81415_5), - ._N97085 (_N97085), - ._N105268 (_N105268), - ._N105817 (_N105817), - ._N106355 (_N106355), - ._N106490 (_N106490), - ._N106518 (_N106518), + ._N82185_3 (_N82185_3), + ._N82185_5 (_N82185_5), + ._N82186_3 (_N82186_3), + ._N82186_5 (_N82186_5), + ._N82187_3 (_N82187_3), + ._N82187_5 (_N82187_5), + ._N82188_3 (_N82188_3), + ._N82188_5 (_N82188_5), + ._N106081 (_N106081), + ._N106639 (_N106639), + ._N107308 (_N107308), + ._N107336 (_N107336), .calib_done (\u_ddrphy_top/calib_done ), .ddrphy_dqs_rst (ddrphy_dqs_rst), .\ddrphy_gate_update_ctrl/drift_dqs_group[0].ddrphy_drift_ctrl/dqs_drift_start (ddr_init_done), .ddrphy_ioclk_gate (ddrphy_ioclk_gate), .ddrphy_pll_rst (ddrphy_pll_rst), .\ddrphy_reset_ctrl/N17 (\u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/rst ), - .\ddrphy_reset_ctrl/N137 (\u_ddrphy_top/ddrphy_reset_ctrl/N137 ), .mem_cas_n (mem_cas_n), .mem_ck (mem_ck), .mem_ck_n (mem_ck_n), @@ -208955,7 +208682,6 @@ module axi_ddr .mem_we_n (mem_we_n), .phy_rst (mem_rst_n), .read_valid (\u_ddrphy_top/read_valid ), - ._N18115 (_N18115), .ddr_rstn (ddr_rstn), .ddrphy_clkin (ddrphy_clkin), .\ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N538 (\u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N538 ), @@ -209039,28 +208765,28 @@ module ipml_fifo_ctrl_v1_3_4_unq10 wire N168; wire N170; wire [12:0] \N170.co ; + wire _N15068; + wire _N15069; + wire _N15070; + wire _N15071; + wire _N15072; + wire _N15073; + wire _N15074; wire _N15075; wire _N15076; wire _N15077; wire _N15078; - wire _N15079; - wire _N15080; - wire _N15081; - wire _N15082; - wire _N15083; - wire _N15084; - wire _N15085; - wire _N15687; - wire _N15688; - wire _N15689; - wire _N15690; - wire _N15691; - wire _N15692; - wire _N15693; - wire _N15694; - wire _N15695; - wire _N15696; - wire _N15697; + wire _N15625; + wire _N15626; + wire _N15627; + wire _N15628; + wire _N15629; + wire _N15630; + wire _N15631; + wire _N15632; + wire _N15633; + wire _N15634; + wire _N15635; wire [11:0] rbin; wire [11:0] rgnext; wire [11:0] rptr; @@ -209853,7 +209579,7 @@ module ipml_fifo_ctrl_v1_3_4_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_1 ( - .COUT (_N15075), + .COUT (_N15068), .Z (N2[0]), .CIN (), .I0 (w_en), @@ -209873,9 +209599,9 @@ module ipml_fifo_ctrl_v1_3_4_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_2 ( - .COUT (_N15076), + .COUT (_N15069), .Z (N2[1]), - .CIN (_N15075), + .CIN (_N15068), .I0 (w_en), .I1 (waddr[0]), .I2 (waddr[1]), @@ -209893,9 +209619,9 @@ module ipml_fifo_ctrl_v1_3_4_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_3 ( - .COUT (_N15077), + .COUT (_N15070), .Z (N2[2]), - .CIN (_N15076), + .CIN (_N15069), .I0 (), .I1 (waddr[2]), .I2 (), @@ -209913,9 +209639,9 @@ module ipml_fifo_ctrl_v1_3_4_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_4 ( - .COUT (_N15078), + .COUT (_N15071), .Z (N2[3]), - .CIN (_N15077), + .CIN (_N15070), .I0 (), .I1 (waddr[3]), .I2 (), @@ -209933,9 +209659,9 @@ module ipml_fifo_ctrl_v1_3_4_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_5 ( - .COUT (_N15079), + .COUT (_N15072), .Z (N2[4]), - .CIN (_N15078), + .CIN (_N15071), .I0 (), .I1 (waddr[4]), .I2 (), @@ -209953,9 +209679,9 @@ module ipml_fifo_ctrl_v1_3_4_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_6 ( - .COUT (_N15080), + .COUT (_N15073), .Z (N2[5]), - .CIN (_N15079), + .CIN (_N15072), .I0 (), .I1 (waddr[5]), .I2 (), @@ -209973,9 +209699,9 @@ module ipml_fifo_ctrl_v1_3_4_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_7 ( - .COUT (_N15081), + .COUT (_N15074), .Z (N2[6]), - .CIN (_N15080), + .CIN (_N15073), .I0 (), .I1 (waddr[6]), .I2 (), @@ -209993,9 +209719,9 @@ module ipml_fifo_ctrl_v1_3_4_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_8 ( - .COUT (_N15082), + .COUT (_N15075), .Z (N2[7]), - .CIN (_N15081), + .CIN (_N15074), .I0 (), .I1 (waddr[7]), .I2 (), @@ -210013,9 +209739,9 @@ module ipml_fifo_ctrl_v1_3_4_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_9 ( - .COUT (_N15083), + .COUT (_N15076), .Z (N2[8]), - .CIN (_N15082), + .CIN (_N15075), .I0 (), .I1 (waddr[8]), .I2 (), @@ -210033,9 +209759,9 @@ module ipml_fifo_ctrl_v1_3_4_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_10 ( - .COUT (_N15084), + .COUT (_N15077), .Z (N2[9]), - .CIN (_N15083), + .CIN (_N15076), .I0 (), .I1 (waddr[9]), .I2 (), @@ -210053,9 +209779,9 @@ module ipml_fifo_ctrl_v1_3_4_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_11 ( - .COUT (_N15085), + .COUT (_N15078), .Z (N2[10]), - .CIN (_N15084), + .CIN (_N15077), .I0 (), .I1 (waddr[10]), .I2 (), @@ -210075,7 +209801,7 @@ module ipml_fifo_ctrl_v1_3_4_unq10 N2_12 ( .COUT (), .Z (N2[11]), - .CIN (_N15085), + .CIN (_N15078), .I0 (), .I1 (wbin[11]), .I2 (), @@ -210394,7 +210120,7 @@ module ipml_fifo_ctrl_v1_3_4_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_1 ( - .COUT (_N15687), + .COUT (_N15625), .Z (N84[0]), .CIN (), .I0 (r_en), @@ -210414,9 +210140,9 @@ module ipml_fifo_ctrl_v1_3_4_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_2 ( - .COUT (_N15688), + .COUT (_N15626), .Z (N84[1]), - .CIN (_N15687), + .CIN (_N15625), .I0 (r_en), .I1 (raddr[0]), .I2 (raddr[1]), @@ -210434,9 +210160,9 @@ module ipml_fifo_ctrl_v1_3_4_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_3 ( - .COUT (_N15689), + .COUT (_N15627), .Z (N84[2]), - .CIN (_N15688), + .CIN (_N15626), .I0 (), .I1 (raddr[2]), .I2 (), @@ -210454,9 +210180,9 @@ module ipml_fifo_ctrl_v1_3_4_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_4 ( - .COUT (_N15690), + .COUT (_N15628), .Z (N84[3]), - .CIN (_N15689), + .CIN (_N15627), .I0 (), .I1 (raddr[3]), .I2 (), @@ -210474,9 +210200,9 @@ module ipml_fifo_ctrl_v1_3_4_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_5 ( - .COUT (_N15691), + .COUT (_N15629), .Z (N84[4]), - .CIN (_N15690), + .CIN (_N15628), .I0 (), .I1 (raddr[4]), .I2 (), @@ -210494,9 +210220,9 @@ module ipml_fifo_ctrl_v1_3_4_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_6 ( - .COUT (_N15692), + .COUT (_N15630), .Z (N84[5]), - .CIN (_N15691), + .CIN (_N15629), .I0 (), .I1 (raddr[5]), .I2 (), @@ -210514,9 +210240,9 @@ module ipml_fifo_ctrl_v1_3_4_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_7 ( - .COUT (_N15693), + .COUT (_N15631), .Z (N84[6]), - .CIN (_N15692), + .CIN (_N15630), .I0 (), .I1 (raddr[6]), .I2 (), @@ -210534,9 +210260,9 @@ module ipml_fifo_ctrl_v1_3_4_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_8 ( - .COUT (_N15694), + .COUT (_N15632), .Z (N84[7]), - .CIN (_N15693), + .CIN (_N15631), .I0 (), .I1 (raddr[7]), .I2 (), @@ -210554,9 +210280,9 @@ module ipml_fifo_ctrl_v1_3_4_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_9 ( - .COUT (_N15695), + .COUT (_N15633), .Z (N84[8]), - .CIN (_N15694), + .CIN (_N15632), .I0 (), .I1 (raddr[8]), .I2 (), @@ -210574,9 +210300,9 @@ module ipml_fifo_ctrl_v1_3_4_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_10 ( - .COUT (_N15696), + .COUT (_N15634), .Z (N84[9]), - .CIN (_N15695), + .CIN (_N15633), .I0 (), .I1 (raddr[9]), .I2 (), @@ -210594,9 +210320,9 @@ module ipml_fifo_ctrl_v1_3_4_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_11 ( - .COUT (_N15697), + .COUT (_N15635), .Z (N84[10]), - .CIN (_N15696), + .CIN (_N15634), .I0 (), .I1 (raddr[10]), .I2 (), @@ -210616,7 +210342,7 @@ module ipml_fifo_ctrl_v1_3_4_unq10 N84_12 ( .COUT (), .Z (N84[11]), - .CIN (_N15697), + .CIN (_N15635), .I0 (), .I1 (rbin[11]), .I2 (), @@ -211989,24 +211715,24 @@ module ipml_fifo_ctrl_v1_3_8 wire N22; wire N24; wire [10:0] \N24.co ; - wire _N15665; - wire _N15666; - wire _N15667; - wire _N15668; - wire _N15669; - wire _N15670; - wire _N15671; - wire _N15672; - wire _N15673; - wire _N15676; - wire _N15677; - wire _N15678; - wire _N15679; - wire _N15680; - wire _N15681; - wire _N15682; - wire _N15683; - wire _N15684; + wire _N15603; + wire _N15604; + wire _N15605; + wire _N15606; + wire _N15607; + wire _N15608; + wire _N15609; + wire _N15610; + wire _N15611; + wire _N15614; + wire _N15615; + wire _N15616; + wire _N15617; + wire _N15618; + wire _N15619; + wire _N15620; + wire _N15621; + wire _N15622; wire [9:0] rbin; wire [9:0] rrptr; wire [9:0] rwptr; @@ -212025,7 +211751,7 @@ module ipml_fifo_ctrl_v1_3_8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_1 ( - .COUT (_N15665), + .COUT (_N15603), .Z (N2[0]), .CIN (), .I0 (w_en), @@ -212045,9 +211771,9 @@ module ipml_fifo_ctrl_v1_3_8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_2 ( - .COUT (_N15666), + .COUT (_N15604), .Z (N2[1]), - .CIN (_N15665), + .CIN (_N15603), .I0 (w_en), .I1 (waddr[0]), .I2 (waddr[1]), @@ -212065,9 +211791,9 @@ module ipml_fifo_ctrl_v1_3_8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_3 ( - .COUT (_N15667), + .COUT (_N15605), .Z (N2[2]), - .CIN (_N15666), + .CIN (_N15604), .I0 (), .I1 (waddr[2]), .I2 (), @@ -212085,9 +211811,9 @@ module ipml_fifo_ctrl_v1_3_8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_4 ( - .COUT (_N15668), + .COUT (_N15606), .Z (N2[3]), - .CIN (_N15667), + .CIN (_N15605), .I0 (), .I1 (waddr[3]), .I2 (), @@ -212105,9 +211831,9 @@ module ipml_fifo_ctrl_v1_3_8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_5 ( - .COUT (_N15669), + .COUT (_N15607), .Z (N2[4]), - .CIN (_N15668), + .CIN (_N15606), .I0 (), .I1 (waddr[4]), .I2 (), @@ -212125,9 +211851,9 @@ module ipml_fifo_ctrl_v1_3_8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_6 ( - .COUT (_N15670), + .COUT (_N15608), .Z (N2[5]), - .CIN (_N15669), + .CIN (_N15607), .I0 (), .I1 (waddr[5]), .I2 (), @@ -212145,9 +211871,9 @@ module ipml_fifo_ctrl_v1_3_8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_7 ( - .COUT (_N15671), + .COUT (_N15609), .Z (N2[6]), - .CIN (_N15670), + .CIN (_N15608), .I0 (), .I1 (waddr[6]), .I2 (), @@ -212165,9 +211891,9 @@ module ipml_fifo_ctrl_v1_3_8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_8 ( - .COUT (_N15672), + .COUT (_N15610), .Z (N2[7]), - .CIN (_N15671), + .CIN (_N15609), .I0 (), .I1 (waddr[7]), .I2 (), @@ -212185,9 +211911,9 @@ module ipml_fifo_ctrl_v1_3_8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_9 ( - .COUT (_N15673), + .COUT (_N15611), .Z (N2[8]), - .CIN (_N15672), + .CIN (_N15610), .I0 (), .I1 (waddr[8]), .I2 (), @@ -212207,7 +211933,7 @@ module ipml_fifo_ctrl_v1_3_8 N2_10 ( .COUT (), .Z (N2[9]), - .CIN (_N15673), + .CIN (_N15611), .I0 (), .I1 (wbin[9]), .I2 (), @@ -212325,7 +212051,7 @@ module ipml_fifo_ctrl_v1_3_8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_1 ( - .COUT (_N15676), + .COUT (_N15614), .Z (N11[0]), .CIN (), .I0 (r_en), @@ -212345,9 +212071,9 @@ module ipml_fifo_ctrl_v1_3_8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_2 ( - .COUT (_N15677), + .COUT (_N15615), .Z (N11[1]), - .CIN (_N15676), + .CIN (_N15614), .I0 (r_en), .I1 (raddr[0]), .I2 (raddr[1]), @@ -212365,9 +212091,9 @@ module ipml_fifo_ctrl_v1_3_8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_3 ( - .COUT (_N15678), + .COUT (_N15616), .Z (N11[2]), - .CIN (_N15677), + .CIN (_N15615), .I0 (), .I1 (raddr[2]), .I2 (), @@ -212385,9 +212111,9 @@ module ipml_fifo_ctrl_v1_3_8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_4 ( - .COUT (_N15679), + .COUT (_N15617), .Z (N11[3]), - .CIN (_N15678), + .CIN (_N15616), .I0 (), .I1 (raddr[3]), .I2 (), @@ -212405,9 +212131,9 @@ module ipml_fifo_ctrl_v1_3_8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_5 ( - .COUT (_N15680), + .COUT (_N15618), .Z (N11[4]), - .CIN (_N15679), + .CIN (_N15617), .I0 (), .I1 (raddr[4]), .I2 (), @@ -212425,9 +212151,9 @@ module ipml_fifo_ctrl_v1_3_8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_6 ( - .COUT (_N15681), + .COUT (_N15619), .Z (N11[5]), - .CIN (_N15680), + .CIN (_N15618), .I0 (), .I1 (raddr[5]), .I2 (), @@ -212445,9 +212171,9 @@ module ipml_fifo_ctrl_v1_3_8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_7 ( - .COUT (_N15682), + .COUT (_N15620), .Z (N11[6]), - .CIN (_N15681), + .CIN (_N15619), .I0 (), .I1 (raddr[6]), .I2 (), @@ -212465,9 +212191,9 @@ module ipml_fifo_ctrl_v1_3_8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_8 ( - .COUT (_N15683), + .COUT (_N15621), .Z (N11[7]), - .CIN (_N15682), + .CIN (_N15620), .I0 (), .I1 (raddr[7]), .I2 (), @@ -212485,9 +212211,9 @@ module ipml_fifo_ctrl_v1_3_8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_9 ( - .COUT (_N15684), + .COUT (_N15622), .Z (N11[8]), - .CIN (_N15683), + .CIN (_N15621), .I0 (), .I1 (raddr[8]), .I2 (), @@ -212507,7 +212233,7 @@ module ipml_fifo_ctrl_v1_3_8 N11_10 ( .COUT (), .Z (N11[9]), - .CIN (_N15684), + .CIN (_N15622), .I0 (), .I1 (rbin[9]), .I2 (), @@ -213295,26 +213021,26 @@ module ipml_fifo_ctrl_v1_3_2 wire N22; wire N24; wire [11:0] \N24.co ; - wire _N15823; - wire _N15824; - wire _N15825; - wire _N15826; - wire _N15827; - wire _N15828; - wire _N15829; - wire _N15830; - wire _N15831; - wire _N15832; - wire _N15835; - wire _N15836; - wire _N15837; - wire _N15838; - wire _N15839; - wire _N15840; - wire _N15841; - wire _N15842; - wire _N15843; - wire _N15844; + wire _N15759; + wire _N15760; + wire _N15761; + wire _N15762; + wire _N15763; + wire _N15764; + wire _N15765; + wire _N15766; + wire _N15767; + wire _N15768; + wire _N15771; + wire _N15772; + wire _N15773; + wire _N15774; + wire _N15775; + wire _N15776; + wire _N15777; + wire _N15778; + wire _N15779; + wire _N15780; wire [10:0] rbin; wire rempty; wire [10:0] rrptr; @@ -213334,7 +213060,7 @@ module ipml_fifo_ctrl_v1_3_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_1 ( - .COUT (_N15823), + .COUT (_N15759), .Z (N2[0]), .CIN (), .I0 (w_en), @@ -213354,9 +213080,9 @@ module ipml_fifo_ctrl_v1_3_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_2 ( - .COUT (_N15824), + .COUT (_N15760), .Z (N2[1]), - .CIN (_N15823), + .CIN (_N15759), .I0 (w_en), .I1 (waddr[0]), .I2 (waddr[1]), @@ -213374,9 +213100,9 @@ module ipml_fifo_ctrl_v1_3_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_3 ( - .COUT (_N15825), + .COUT (_N15761), .Z (N2[2]), - .CIN (_N15824), + .CIN (_N15760), .I0 (), .I1 (waddr[2]), .I2 (), @@ -213394,9 +213120,9 @@ module ipml_fifo_ctrl_v1_3_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_4 ( - .COUT (_N15826), + .COUT (_N15762), .Z (N2[3]), - .CIN (_N15825), + .CIN (_N15761), .I0 (), .I1 (waddr[3]), .I2 (), @@ -213414,9 +213140,9 @@ module ipml_fifo_ctrl_v1_3_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_5 ( - .COUT (_N15827), + .COUT (_N15763), .Z (N2[4]), - .CIN (_N15826), + .CIN (_N15762), .I0 (), .I1 (waddr[4]), .I2 (), @@ -213434,9 +213160,9 @@ module ipml_fifo_ctrl_v1_3_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_6 ( - .COUT (_N15828), + .COUT (_N15764), .Z (N2[5]), - .CIN (_N15827), + .CIN (_N15763), .I0 (), .I1 (waddr[5]), .I2 (), @@ -213454,9 +213180,9 @@ module ipml_fifo_ctrl_v1_3_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_7 ( - .COUT (_N15829), + .COUT (_N15765), .Z (N2[6]), - .CIN (_N15828), + .CIN (_N15764), .I0 (), .I1 (waddr[6]), .I2 (), @@ -213474,9 +213200,9 @@ module ipml_fifo_ctrl_v1_3_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_8 ( - .COUT (_N15830), + .COUT (_N15766), .Z (N2[7]), - .CIN (_N15829), + .CIN (_N15765), .I0 (), .I1 (waddr[7]), .I2 (), @@ -213494,9 +213220,9 @@ module ipml_fifo_ctrl_v1_3_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_9 ( - .COUT (_N15831), + .COUT (_N15767), .Z (N2[8]), - .CIN (_N15830), + .CIN (_N15766), .I0 (), .I1 (waddr[8]), .I2 (), @@ -213514,9 +213240,9 @@ module ipml_fifo_ctrl_v1_3_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_10 ( - .COUT (_N15832), + .COUT (_N15768), .Z (N2[9]), - .CIN (_N15831), + .CIN (_N15767), .I0 (), .I1 (waddr[9]), .I2 (), @@ -213536,7 +213262,7 @@ module ipml_fifo_ctrl_v1_3_2 N2_11 ( .COUT (), .Z (N2[10]), - .CIN (_N15832), + .CIN (_N15768), .I0 (), .I1 (wbin[10]), .I2 (), @@ -213669,7 +213395,7 @@ module ipml_fifo_ctrl_v1_3_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_1 ( - .COUT (_N15835), + .COUT (_N15771), .Z (N11[0]), .CIN (), .I0 (r_en), @@ -213689,9 +213415,9 @@ module ipml_fifo_ctrl_v1_3_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_2 ( - .COUT (_N15836), + .COUT (_N15772), .Z (N11[1]), - .CIN (_N15835), + .CIN (_N15771), .I0 (r_en), .I1 (raddr[0]), .I2 (raddr[1]), @@ -213709,9 +213435,9 @@ module ipml_fifo_ctrl_v1_3_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_3 ( - .COUT (_N15837), + .COUT (_N15773), .Z (N11[2]), - .CIN (_N15836), + .CIN (_N15772), .I0 (), .I1 (raddr[2]), .I2 (), @@ -213729,9 +213455,9 @@ module ipml_fifo_ctrl_v1_3_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_4 ( - .COUT (_N15838), + .COUT (_N15774), .Z (N11[3]), - .CIN (_N15837), + .CIN (_N15773), .I0 (), .I1 (raddr[3]), .I2 (), @@ -213749,9 +213475,9 @@ module ipml_fifo_ctrl_v1_3_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_5 ( - .COUT (_N15839), + .COUT (_N15775), .Z (N11[4]), - .CIN (_N15838), + .CIN (_N15774), .I0 (), .I1 (raddr[4]), .I2 (), @@ -213769,9 +213495,9 @@ module ipml_fifo_ctrl_v1_3_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_6 ( - .COUT (_N15840), + .COUT (_N15776), .Z (N11[5]), - .CIN (_N15839), + .CIN (_N15775), .I0 (), .I1 (raddr[5]), .I2 (), @@ -213789,9 +213515,9 @@ module ipml_fifo_ctrl_v1_3_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_7 ( - .COUT (_N15841), + .COUT (_N15777), .Z (N11[6]), - .CIN (_N15840), + .CIN (_N15776), .I0 (), .I1 (raddr[6]), .I2 (), @@ -213809,9 +213535,9 @@ module ipml_fifo_ctrl_v1_3_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_8 ( - .COUT (_N15842), + .COUT (_N15778), .Z (N11[7]), - .CIN (_N15841), + .CIN (_N15777), .I0 (), .I1 (raddr[7]), .I2 (), @@ -213829,9 +213555,9 @@ module ipml_fifo_ctrl_v1_3_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_9 ( - .COUT (_N15843), + .COUT (_N15779), .Z (N11[8]), - .CIN (_N15842), + .CIN (_N15778), .I0 (), .I1 (raddr[8]), .I2 (), @@ -213849,9 +213575,9 @@ module ipml_fifo_ctrl_v1_3_2 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_10 ( - .COUT (_N15844), + .COUT (_N15780), .Z (N11[9]), - .CIN (_N15843), + .CIN (_N15779), .I0 (), .I1 (raddr[9]), .I2 (), @@ -213871,7 +213597,7 @@ module ipml_fifo_ctrl_v1_3_2 N11_11 ( .COUT (), .Z (N11[10]), - .CIN (_N15844), + .CIN (_N15780), .I0 (), .I1 (rbin[10]), .I2 (), @@ -214547,7 +214273,7 @@ endmodule module ipml_fifo_ctrl_v1_3_10 ( input [3:0] \u_axi_ddr_top/u_axi_rd_connect/rid_dout0 , - input N241_0, + input N242_0, input rclk, input rrst, input \u_axi_ddr_top/u_axi_rd_connect/rd_ddr_valid , @@ -214565,26 +214291,26 @@ module ipml_fifo_ctrl_v1_3_10 wire [12:0] \N161.co ; wire [9:0] N287; wire [10:0] \N287_5.co ; - wire _N15847; - wire _N15848; - wire _N15849; - wire _N15850; - wire _N15851; - wire _N15852; - wire _N15853; - wire _N15854; - wire _N15855; - wire _N15858; - wire _N15859; - wire _N15860; - wire _N15861; - wire _N15862; - wire _N15863; - wire _N15864; - wire _N15865; - wire _N15866; - wire _N15867; - wire _N15868; + wire _N15783; + wire _N15784; + wire _N15785; + wire _N15786; + wire _N15787; + wire _N15788; + wire _N15789; + wire _N15790; + wire _N15791; + wire _N15794; + wire _N15795; + wire _N15796; + wire _N15797; + wire _N15798; + wire _N15799; + wire _N15800; + wire _N15801; + wire _N15802; + wire _N15803; + wire _N15804; wire [9:0] nb2; wire [10:0] raddr; wire [11:0] rbin; @@ -214630,7 +214356,7 @@ module ipml_fifo_ctrl_v1_3_10 \ASYN_CTRL.rbin[0] ( .Q (raddr[0]), .C (rrst), - .CE (N241_0), + .CE (N242_0), .CLK (rclk), .D (N84[0])); // ../ipcore/image_in_fifo/rtl/ipml_fifo_ctrl_v1_3.v:154 @@ -214641,7 +214367,7 @@ module ipml_fifo_ctrl_v1_3_10 \ASYN_CTRL.rbin[1] ( .Q (raddr[1]), .C (rrst), - .CE (N241_0), + .CE (N242_0), .CLK (rclk), .D (N84[1])); // ../ipcore/image_in_fifo/rtl/ipml_fifo_ctrl_v1_3.v:154 @@ -214652,7 +214378,7 @@ module ipml_fifo_ctrl_v1_3_10 \ASYN_CTRL.rbin[2] ( .Q (raddr[2]), .C (rrst), - .CE (N241_0), + .CE (N242_0), .CLK (rclk), .D (N84[2])); // ../ipcore/image_in_fifo/rtl/ipml_fifo_ctrl_v1_3.v:154 @@ -214663,7 +214389,7 @@ module ipml_fifo_ctrl_v1_3_10 \ASYN_CTRL.rbin[3] ( .Q (raddr[3]), .C (rrst), - .CE (N241_0), + .CE (N242_0), .CLK (rclk), .D (N84[3])); // ../ipcore/image_in_fifo/rtl/ipml_fifo_ctrl_v1_3.v:154 @@ -214674,7 +214400,7 @@ module ipml_fifo_ctrl_v1_3_10 \ASYN_CTRL.rbin[4] ( .Q (raddr[4]), .C (rrst), - .CE (N241_0), + .CE (N242_0), .CLK (rclk), .D (N84[4])); // ../ipcore/image_in_fifo/rtl/ipml_fifo_ctrl_v1_3.v:154 @@ -214685,7 +214411,7 @@ module ipml_fifo_ctrl_v1_3_10 \ASYN_CTRL.rbin[5] ( .Q (raddr[5]), .C (rrst), - .CE (N241_0), + .CE (N242_0), .CLK (rclk), .D (N84[5])); // ../ipcore/image_in_fifo/rtl/ipml_fifo_ctrl_v1_3.v:154 @@ -214696,7 +214422,7 @@ module ipml_fifo_ctrl_v1_3_10 \ASYN_CTRL.rbin[6] ( .Q (raddr[6]), .C (rrst), - .CE (N241_0), + .CE (N242_0), .CLK (rclk), .D (N84[6])); // ../ipcore/image_in_fifo/rtl/ipml_fifo_ctrl_v1_3.v:154 @@ -214707,7 +214433,7 @@ module ipml_fifo_ctrl_v1_3_10 \ASYN_CTRL.rbin[7] ( .Q (raddr[7]), .C (rrst), - .CE (N241_0), + .CE (N242_0), .CLK (rclk), .D (N84[7])); // ../ipcore/image_in_fifo/rtl/ipml_fifo_ctrl_v1_3.v:154 @@ -214718,7 +214444,7 @@ module ipml_fifo_ctrl_v1_3_10 \ASYN_CTRL.rbin[8] ( .Q (raddr[8]), .C (rrst), - .CE (N241_0), + .CE (N242_0), .CLK (rclk), .D (N84[8])); // ../ipcore/image_in_fifo/rtl/ipml_fifo_ctrl_v1_3.v:154 @@ -214729,7 +214455,7 @@ module ipml_fifo_ctrl_v1_3_10 \ASYN_CTRL.rbin[9] ( .Q (raddr[9]), .C (rrst), - .CE (N241_0), + .CE (N242_0), .CLK (rclk), .D (N84[9])); // ../ipcore/image_in_fifo/rtl/ipml_fifo_ctrl_v1_3.v:154 @@ -214740,7 +214466,7 @@ module ipml_fifo_ctrl_v1_3_10 \ASYN_CTRL.rbin[10] ( .Q (raddr[10]), .C (rrst), - .CE (N241_0), + .CE (N242_0), .CLK (rclk), .D (N84[10])); // ../ipcore/image_in_fifo/rtl/ipml_fifo_ctrl_v1_3.v:154 @@ -214751,7 +214477,7 @@ module ipml_fifo_ctrl_v1_3_10 \ASYN_CTRL.rbin[11] ( .Q (rbin[11]), .C (rrst), - .CE (N241_0), + .CE (N242_0), .CLK (rclk), .D (N84[11])); // ../ipcore/image_in_fifo/rtl/ipml_fifo_ctrl_v1_3.v:154 @@ -215278,7 +215004,7 @@ module ipml_fifo_ctrl_v1_3_10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_1 ( - .COUT (_N15847), + .COUT (_N15783), .Z (N2[0]), .CIN (), .I0 (\u_axi_ddr_top/u_axi_rd_connect/rd_ddr_valid ), @@ -215298,9 +215024,9 @@ module ipml_fifo_ctrl_v1_3_10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_2 ( - .COUT (_N15848), + .COUT (_N15784), .Z (N2[1]), - .CIN (_N15847), + .CIN (_N15783), .I0 (\u_axi_ddr_top/u_axi_rd_connect/rd_ddr_valid ), .I1 (waddr[0]), .I2 (\u_axi_ddr_top/u_axi_rd_connect/rid_dout0 [0] ), @@ -215318,9 +215044,9 @@ module ipml_fifo_ctrl_v1_3_10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_3 ( - .COUT (_N15849), + .COUT (_N15785), .Z (N2[2]), - .CIN (_N15848), + .CIN (_N15784), .I0 (), .I1 (waddr[2]), .I2 (), @@ -215338,9 +215064,9 @@ module ipml_fifo_ctrl_v1_3_10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_4 ( - .COUT (_N15850), + .COUT (_N15786), .Z (N2[3]), - .CIN (_N15849), + .CIN (_N15785), .I0 (), .I1 (waddr[3]), .I2 (), @@ -215358,9 +215084,9 @@ module ipml_fifo_ctrl_v1_3_10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_5 ( - .COUT (_N15851), + .COUT (_N15787), .Z (N2[4]), - .CIN (_N15850), + .CIN (_N15786), .I0 (), .I1 (waddr[4]), .I2 (), @@ -215378,9 +215104,9 @@ module ipml_fifo_ctrl_v1_3_10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_6 ( - .COUT (_N15852), + .COUT (_N15788), .Z (N2[5]), - .CIN (_N15851), + .CIN (_N15787), .I0 (), .I1 (waddr[5]), .I2 (), @@ -215398,9 +215124,9 @@ module ipml_fifo_ctrl_v1_3_10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_7 ( - .COUT (_N15853), + .COUT (_N15789), .Z (N2[6]), - .CIN (_N15852), + .CIN (_N15788), .I0 (), .I1 (waddr[6]), .I2 (), @@ -215418,9 +215144,9 @@ module ipml_fifo_ctrl_v1_3_10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_8 ( - .COUT (_N15854), + .COUT (_N15790), .Z (N2[7]), - .CIN (_N15853), + .CIN (_N15789), .I0 (), .I1 (waddr[7]), .I2 (), @@ -215438,9 +215164,9 @@ module ipml_fifo_ctrl_v1_3_10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_9 ( - .COUT (_N15855), + .COUT (_N15791), .Z (N2[8]), - .CIN (_N15854), + .CIN (_N15790), .I0 (), .I1 (waddr[8]), .I2 (), @@ -215460,7 +215186,7 @@ module ipml_fifo_ctrl_v1_3_10 N2_10 ( .COUT (), .Z (N2[9]), - .CIN (_N15855), + .CIN (_N15791), .I0 (), .I1 (wbin[9]), .I2 (), @@ -215746,7 +215472,7 @@ module ipml_fifo_ctrl_v1_3_10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_1 ( - .COUT (_N15858), + .COUT (_N15794), .Z (N84[0]), .CIN (), .I0 (rempty), @@ -215766,9 +215492,9 @@ module ipml_fifo_ctrl_v1_3_10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_2 ( - .COUT (_N15859), + .COUT (_N15795), .Z (N84[1]), - .CIN (_N15858), + .CIN (_N15794), .I0 (rempty), .I1 (raddr[0]), .I2 (raddr[1]), @@ -215786,9 +215512,9 @@ module ipml_fifo_ctrl_v1_3_10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_3 ( - .COUT (_N15860), + .COUT (_N15796), .Z (N84[2]), - .CIN (_N15859), + .CIN (_N15795), .I0 (), .I1 (raddr[2]), .I2 (), @@ -215806,9 +215532,9 @@ module ipml_fifo_ctrl_v1_3_10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_4 ( - .COUT (_N15861), + .COUT (_N15797), .Z (N84[3]), - .CIN (_N15860), + .CIN (_N15796), .I0 (), .I1 (raddr[3]), .I2 (), @@ -215826,9 +215552,9 @@ module ipml_fifo_ctrl_v1_3_10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_5 ( - .COUT (_N15862), + .COUT (_N15798), .Z (N84[4]), - .CIN (_N15861), + .CIN (_N15797), .I0 (), .I1 (raddr[4]), .I2 (), @@ -215846,9 +215572,9 @@ module ipml_fifo_ctrl_v1_3_10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_6 ( - .COUT (_N15863), + .COUT (_N15799), .Z (N84[5]), - .CIN (_N15862), + .CIN (_N15798), .I0 (), .I1 (raddr[5]), .I2 (), @@ -215866,9 +215592,9 @@ module ipml_fifo_ctrl_v1_3_10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_7 ( - .COUT (_N15864), + .COUT (_N15800), .Z (N84[6]), - .CIN (_N15863), + .CIN (_N15799), .I0 (), .I1 (raddr[6]), .I2 (), @@ -215886,9 +215612,9 @@ module ipml_fifo_ctrl_v1_3_10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_8 ( - .COUT (_N15865), + .COUT (_N15801), .Z (N84[7]), - .CIN (_N15864), + .CIN (_N15800), .I0 (), .I1 (raddr[7]), .I2 (), @@ -215906,9 +215632,9 @@ module ipml_fifo_ctrl_v1_3_10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_9 ( - .COUT (_N15866), + .COUT (_N15802), .Z (N84[8]), - .CIN (_N15865), + .CIN (_N15801), .I0 (), .I1 (raddr[8]), .I2 (), @@ -215926,9 +215652,9 @@ module ipml_fifo_ctrl_v1_3_10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_10 ( - .COUT (_N15867), + .COUT (_N15803), .Z (N84[9]), - .CIN (_N15866), + .CIN (_N15802), .I0 (), .I1 (raddr[9]), .I2 (), @@ -215946,9 +215672,9 @@ module ipml_fifo_ctrl_v1_3_10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_11 ( - .COUT (_N15868), + .COUT (_N15804), .Z (N84[10]), - .CIN (_N15867), + .CIN (_N15803), .I0 (), .I1 (raddr[10]), .I2 (), @@ -215968,7 +215694,7 @@ module ipml_fifo_ctrl_v1_3_10 N84_12 ( .COUT (), .Z (N84[11]), - .CIN (_N15868), + .CIN (_N15804), .I0 (), .I1 (rbin[11]), .I2 (), @@ -216977,7 +216703,7 @@ endmodule module ipml_fifo_v1_6_rd0_fifo ( input [3:0] \u_axi_ddr_top/u_axi_rd_connect/rid_dout0 , - input N241_0, + input N242_0, input rd_clk, input rd_rst, input \u_axi_ddr_top/u_axi_rd_connect/rd_ddr_valid , @@ -216990,7 +216716,7 @@ module ipml_fifo_v1_6_rd0_fifo .wr_water_level (wr_water_level), .\u_axi_ddr_top/u_axi_rd_connect/rid_dout0 ({1'bx, 1'bx, 1'bx, \u_axi_ddr_top/u_axi_rd_connect/rid_dout0 [0] }), .rempty (rd_empty), - .N241_0 (N241_0), + .N242_0 (N242_0), .rclk (rd_clk), .rrst (rd_rst), .\u_axi_ddr_top/u_axi_rd_connect/rd_ddr_valid (\u_axi_ddr_top/u_axi_rd_connect/rd_ddr_valid ), @@ -217004,7 +216730,7 @@ endmodule module rd0_fifo ( input [3:0] \u_axi_ddr_top/u_axi_rd_connect/rid_dout0 , - input N241_0, + input N242_0, input rd_clk, input rd_rst, input \u_axi_ddr_top/u_axi_rd_connect/rd_ddr_valid , @@ -217017,7 +216743,7 @@ module rd0_fifo .wr_water_level (wr_water_level), .\u_axi_ddr_top/u_axi_rd_connect/rid_dout0 ({1'bx, 1'bx, 1'bx, \u_axi_ddr_top/u_axi_rd_connect/rid_dout0 [0] }), .rd_empty (rd_empty), - .N241_0 (N241_0), + .N242_0 (N242_0), .rd_clk (rd_clk), .rd_rst (rd_rst), .\u_axi_ddr_top/u_axi_rd_connect/rd_ddr_valid (\u_axi_ddr_top/u_axi_rd_connect/rd_ddr_valid ), @@ -217051,26 +216777,26 @@ module ipml_fifo_ctrl_v1_3_10_unq6 wire [12:0] \N161.co ; wire [9:0] N287; wire [10:0] \N287_5.co ; - wire _N15786; - wire _N15787; - wire _N15788; - wire _N15789; - wire _N15790; - wire _N15791; - wire _N15792; - wire _N15793; - wire _N15794; - wire _N15795; - wire _N15796; - wire _N15871; - wire _N15872; - wire _N15873; - wire _N15874; - wire _N15875; - wire _N15876; - wire _N15877; - wire _N15878; - wire _N15879; + wire _N15722; + wire _N15723; + wire _N15724; + wire _N15725; + wire _N15726; + wire _N15727; + wire _N15728; + wire _N15729; + wire _N15730; + wire _N15731; + wire _N15732; + wire _N15807; + wire _N15808; + wire _N15809; + wire _N15810; + wire _N15811; + wire _N15812; + wire _N15813; + wire _N15814; + wire _N15815; wire [9:0] nb2; wire [11:0] rbin; wire [11:0] rgnext; @@ -217762,7 +217488,7 @@ module ipml_fifo_ctrl_v1_3_10_unq6 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_1 ( - .COUT (_N15871), + .COUT (_N15807), .Z (N2[0]), .CIN (), .I0 (\u_axi_ddr_top/u_axi_rd_connect/rd_ddr_valid ), @@ -217782,9 +217508,9 @@ module ipml_fifo_ctrl_v1_3_10_unq6 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_2 ( - .COUT (_N15872), + .COUT (_N15808), .Z (N2[1]), - .CIN (_N15871), + .CIN (_N15807), .I0 (\u_axi_ddr_top/u_axi_rd_connect/rd_ddr_valid ), .I1 (waddr[0]), .I2 (\u_axi_ddr_top/u_axi_rd_connect/rid_dout0 [1] ), @@ -217802,9 +217528,9 @@ module ipml_fifo_ctrl_v1_3_10_unq6 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_3 ( - .COUT (_N15873), + .COUT (_N15809), .Z (N2[2]), - .CIN (_N15872), + .CIN (_N15808), .I0 (), .I1 (waddr[2]), .I2 (), @@ -217822,9 +217548,9 @@ module ipml_fifo_ctrl_v1_3_10_unq6 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_4 ( - .COUT (_N15874), + .COUT (_N15810), .Z (N2[3]), - .CIN (_N15873), + .CIN (_N15809), .I0 (), .I1 (waddr[3]), .I2 (), @@ -217842,9 +217568,9 @@ module ipml_fifo_ctrl_v1_3_10_unq6 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_5 ( - .COUT (_N15875), + .COUT (_N15811), .Z (N2[4]), - .CIN (_N15874), + .CIN (_N15810), .I0 (), .I1 (waddr[4]), .I2 (), @@ -217862,9 +217588,9 @@ module ipml_fifo_ctrl_v1_3_10_unq6 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_6 ( - .COUT (_N15876), + .COUT (_N15812), .Z (N2[5]), - .CIN (_N15875), + .CIN (_N15811), .I0 (), .I1 (waddr[5]), .I2 (), @@ -217882,9 +217608,9 @@ module ipml_fifo_ctrl_v1_3_10_unq6 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_7 ( - .COUT (_N15877), + .COUT (_N15813), .Z (N2[6]), - .CIN (_N15876), + .CIN (_N15812), .I0 (), .I1 (waddr[6]), .I2 (), @@ -217902,9 +217628,9 @@ module ipml_fifo_ctrl_v1_3_10_unq6 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_8 ( - .COUT (_N15878), + .COUT (_N15814), .Z (N2[7]), - .CIN (_N15877), + .CIN (_N15813), .I0 (), .I1 (waddr[7]), .I2 (), @@ -217922,9 +217648,9 @@ module ipml_fifo_ctrl_v1_3_10_unq6 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_9 ( - .COUT (_N15879), + .COUT (_N15815), .Z (N2[8]), - .CIN (_N15878), + .CIN (_N15814), .I0 (), .I1 (waddr[8]), .I2 (), @@ -217944,7 +217670,7 @@ module ipml_fifo_ctrl_v1_3_10_unq6 N2_10 ( .COUT (), .Z (N2[9]), - .CIN (_N15879), + .CIN (_N15815), .I0 (), .I1 (wbin[9]), .I2 (), @@ -218230,7 +217956,7 @@ module ipml_fifo_ctrl_v1_3_10_unq6 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_1 ( - .COUT (_N15786), + .COUT (_N15722), .Z (N84[0]), .CIN (), .I0 (rempty), @@ -218250,9 +217976,9 @@ module ipml_fifo_ctrl_v1_3_10_unq6 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_2 ( - .COUT (_N15787), + .COUT (_N15723), .Z (N84[1]), - .CIN (_N15786), + .CIN (_N15722), .I0 (rempty), .I1 (raddr[0]), .I2 (raddr[1]), @@ -218270,9 +217996,9 @@ module ipml_fifo_ctrl_v1_3_10_unq6 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_3 ( - .COUT (_N15788), + .COUT (_N15724), .Z (N84[2]), - .CIN (_N15787), + .CIN (_N15723), .I0 (), .I1 (raddr[2]), .I2 (), @@ -218290,9 +218016,9 @@ module ipml_fifo_ctrl_v1_3_10_unq6 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_4 ( - .COUT (_N15789), + .COUT (_N15725), .Z (N84[3]), - .CIN (_N15788), + .CIN (_N15724), .I0 (), .I1 (raddr[3]), .I2 (), @@ -218310,9 +218036,9 @@ module ipml_fifo_ctrl_v1_3_10_unq6 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_5 ( - .COUT (_N15790), + .COUT (_N15726), .Z (N84[4]), - .CIN (_N15789), + .CIN (_N15725), .I0 (), .I1 (raddr[4]), .I2 (), @@ -218330,9 +218056,9 @@ module ipml_fifo_ctrl_v1_3_10_unq6 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_6 ( - .COUT (_N15791), + .COUT (_N15727), .Z (N84[5]), - .CIN (_N15790), + .CIN (_N15726), .I0 (), .I1 (raddr[5]), .I2 (), @@ -218350,9 +218076,9 @@ module ipml_fifo_ctrl_v1_3_10_unq6 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_7 ( - .COUT (_N15792), + .COUT (_N15728), .Z (N84[6]), - .CIN (_N15791), + .CIN (_N15727), .I0 (), .I1 (raddr[6]), .I2 (), @@ -218370,9 +218096,9 @@ module ipml_fifo_ctrl_v1_3_10_unq6 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_8 ( - .COUT (_N15793), + .COUT (_N15729), .Z (N84[7]), - .CIN (_N15792), + .CIN (_N15728), .I0 (), .I1 (raddr[7]), .I2 (), @@ -218390,9 +218116,9 @@ module ipml_fifo_ctrl_v1_3_10_unq6 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_9 ( - .COUT (_N15794), + .COUT (_N15730), .Z (N84[8]), - .CIN (_N15793), + .CIN (_N15729), .I0 (), .I1 (raddr[8]), .I2 (), @@ -218410,9 +218136,9 @@ module ipml_fifo_ctrl_v1_3_10_unq6 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_10 ( - .COUT (_N15795), + .COUT (_N15731), .Z (N84[9]), - .CIN (_N15794), + .CIN (_N15730), .I0 (), .I1 (raddr[9]), .I2 (), @@ -218430,9 +218156,9 @@ module ipml_fifo_ctrl_v1_3_10_unq6 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_11 ( - .COUT (_N15796), + .COUT (_N15732), .Z (N84[10]), - .CIN (_N15795), + .CIN (_N15731), .I0 (), .I1 (raddr[10]), .I2 (), @@ -218452,7 +218178,7 @@ module ipml_fifo_ctrl_v1_3_10_unq6 N84_12 ( .COUT (), .Z (N84[11]), - .CIN (_N15796), + .CIN (_N15732), .I0 (), .I1 (rbin[11]), .I2 (), @@ -219734,26 +219460,26 @@ module ipml_fifo_ctrl_v1_3_9 wire [12:0] \N25.co ; wire [9:0] N139; wire [10:0] \N139_5.co ; - wire _N15799; - wire _N15800; - wire _N15801; - wire _N15802; - wire _N15803; - wire _N15804; - wire _N15805; - wire _N15806; - wire _N15807; - wire _N15810; - wire _N15811; - wire _N15812; - wire _N15813; - wire _N15814; - wire _N15815; - wire _N15816; - wire _N15817; - wire _N15818; - wire _N15819; - wire _N15820; + wire _N15735; + wire _N15736; + wire _N15737; + wire _N15738; + wire _N15739; + wire _N15740; + wire _N15741; + wire _N15742; + wire _N15743; + wire _N15746; + wire _N15747; + wire _N15748; + wire _N15749; + wire _N15750; + wire _N15751; + wire _N15752; + wire _N15753; + wire _N15754; + wire _N15755; + wire _N15756; wire [9:0] nb2; wire [11:0] rbin; wire [11:0] rrptr; @@ -219773,7 +219499,7 @@ module ipml_fifo_ctrl_v1_3_9 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_1 ( - .COUT (_N15799), + .COUT (_N15735), .Z (N2[0]), .CIN (), .I0 (w_en), @@ -219793,9 +219519,9 @@ module ipml_fifo_ctrl_v1_3_9 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_2 ( - .COUT (_N15800), + .COUT (_N15736), .Z (N2[1]), - .CIN (_N15799), + .CIN (_N15735), .I0 (w_en), .I1 (waddr[0]), .I2 (waddr[1]), @@ -219813,9 +219539,9 @@ module ipml_fifo_ctrl_v1_3_9 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_3 ( - .COUT (_N15801), + .COUT (_N15737), .Z (N2[2]), - .CIN (_N15800), + .CIN (_N15736), .I0 (), .I1 (waddr[2]), .I2 (), @@ -219833,9 +219559,9 @@ module ipml_fifo_ctrl_v1_3_9 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_4 ( - .COUT (_N15802), + .COUT (_N15738), .Z (N2[3]), - .CIN (_N15801), + .CIN (_N15737), .I0 (), .I1 (waddr[3]), .I2 (), @@ -219853,9 +219579,9 @@ module ipml_fifo_ctrl_v1_3_9 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_5 ( - .COUT (_N15803), + .COUT (_N15739), .Z (N2[4]), - .CIN (_N15802), + .CIN (_N15738), .I0 (), .I1 (waddr[4]), .I2 (), @@ -219873,9 +219599,9 @@ module ipml_fifo_ctrl_v1_3_9 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_6 ( - .COUT (_N15804), + .COUT (_N15740), .Z (N2[5]), - .CIN (_N15803), + .CIN (_N15739), .I0 (), .I1 (waddr[5]), .I2 (), @@ -219893,9 +219619,9 @@ module ipml_fifo_ctrl_v1_3_9 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_7 ( - .COUT (_N15805), + .COUT (_N15741), .Z (N2[6]), - .CIN (_N15804), + .CIN (_N15740), .I0 (), .I1 (waddr[6]), .I2 (), @@ -219913,9 +219639,9 @@ module ipml_fifo_ctrl_v1_3_9 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_8 ( - .COUT (_N15806), + .COUT (_N15742), .Z (N2[7]), - .CIN (_N15805), + .CIN (_N15741), .I0 (), .I1 (waddr[7]), .I2 (), @@ -219933,9 +219659,9 @@ module ipml_fifo_ctrl_v1_3_9 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_9 ( - .COUT (_N15807), + .COUT (_N15743), .Z (N2[8]), - .CIN (_N15806), + .CIN (_N15742), .I0 (), .I1 (waddr[8]), .I2 (), @@ -219955,7 +219681,7 @@ module ipml_fifo_ctrl_v1_3_9 N2_10 ( .COUT (), .Z (N2[9]), - .CIN (_N15807), + .CIN (_N15743), .I0 (), .I1 (wbin[9]), .I2 (), @@ -220073,7 +219799,7 @@ module ipml_fifo_ctrl_v1_3_9 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_1 ( - .COUT (_N15810), + .COUT (_N15746), .Z (N11[0]), .CIN (), .I0 (r_en), @@ -220093,9 +219819,9 @@ module ipml_fifo_ctrl_v1_3_9 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_2 ( - .COUT (_N15811), + .COUT (_N15747), .Z (N11[1]), - .CIN (_N15810), + .CIN (_N15746), .I0 (r_en), .I1 (raddr[0]), .I2 (raddr[1]), @@ -220113,9 +219839,9 @@ module ipml_fifo_ctrl_v1_3_9 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_3 ( - .COUT (_N15812), + .COUT (_N15748), .Z (N11[2]), - .CIN (_N15811), + .CIN (_N15747), .I0 (), .I1 (raddr[2]), .I2 (), @@ -220133,9 +219859,9 @@ module ipml_fifo_ctrl_v1_3_9 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_4 ( - .COUT (_N15813), + .COUT (_N15749), .Z (N11[3]), - .CIN (_N15812), + .CIN (_N15748), .I0 (), .I1 (raddr[3]), .I2 (), @@ -220153,9 +219879,9 @@ module ipml_fifo_ctrl_v1_3_9 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_5 ( - .COUT (_N15814), + .COUT (_N15750), .Z (N11[4]), - .CIN (_N15813), + .CIN (_N15749), .I0 (), .I1 (raddr[4]), .I2 (), @@ -220173,9 +219899,9 @@ module ipml_fifo_ctrl_v1_3_9 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_6 ( - .COUT (_N15815), + .COUT (_N15751), .Z (N11[5]), - .CIN (_N15814), + .CIN (_N15750), .I0 (), .I1 (raddr[5]), .I2 (), @@ -220193,9 +219919,9 @@ module ipml_fifo_ctrl_v1_3_9 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_7 ( - .COUT (_N15816), + .COUT (_N15752), .Z (N11[6]), - .CIN (_N15815), + .CIN (_N15751), .I0 (), .I1 (raddr[6]), .I2 (), @@ -220213,9 +219939,9 @@ module ipml_fifo_ctrl_v1_3_9 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_8 ( - .COUT (_N15817), + .COUT (_N15753), .Z (N11[7]), - .CIN (_N15816), + .CIN (_N15752), .I0 (), .I1 (raddr[7]), .I2 (), @@ -220233,9 +219959,9 @@ module ipml_fifo_ctrl_v1_3_9 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_9 ( - .COUT (_N15818), + .COUT (_N15754), .Z (N11[8]), - .CIN (_N15817), + .CIN (_N15753), .I0 (), .I1 (raddr[8]), .I2 (), @@ -220253,9 +219979,9 @@ module ipml_fifo_ctrl_v1_3_9 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_10 ( - .COUT (_N15819), + .COUT (_N15755), .Z (N11[9]), - .CIN (_N15818), + .CIN (_N15754), .I0 (), .I1 (raddr[9]), .I2 (), @@ -220273,9 +219999,9 @@ module ipml_fifo_ctrl_v1_3_9 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_11 ( - .COUT (_N15820), + .COUT (_N15756), .Z (N11[10]), - .CIN (_N15819), + .CIN (_N15755), .I0 (), .I1 (raddr[10]), .I2 (), @@ -220295,7 +220021,7 @@ module ipml_fifo_ctrl_v1_3_9 N11_12 ( .COUT (), .Z (N11[11]), - .CIN (_N15820), + .CIN (_N15756), .I0 (), .I1 (rbin[11]), .I2 (), @@ -222184,7 +221910,7 @@ module axi_rd_connect input [3:0] axi_rid, input N78, input N78_1, - input N241_0, + input N242_0, input clk, input rd0_clk, input rd1_clk, @@ -222215,16 +221941,16 @@ module axi_rd_connect wire _N3; wire _N5; wire _N6; - wire _N13608; - wire _N13609; - wire _N13610; - wire _N13611; - wire _N13612; - wire _N13613; - wire _N104664; - wire _N104672; - wire _N106741; - wire _N106742; + wire _N13598; + wire _N13599; + wire _N13600; + wire _N13601; + wire _N13602; + wire _N13603; + wire _N105499; + wire _N105507; + wire _N107553; + wire _N107554; wire [7:0] cnt_times; wire \cnt_times[0]_inv ; wire [9:0] ddr_wr_count; @@ -222328,7 +222054,7 @@ module axi_rd_connect GTP_LUT5 /* N32_mux8_8 */ #( .INIT(32'b00000000000000000000000000000001)) N32_mux8_8 ( - .Z (_N104672), + .Z (_N105507), .I0 (ddr_wr_count[2]), .I1 (ddr_wr_count[3]), .I2 (ddr_wr_count[7]), @@ -222344,13 +222070,13 @@ module axi_rd_connect .I1 (ddr_wr_count[4]), .I2 (ddr_wr_count[5]), .I3 (ddr_wr_count[6]), - .I4 (_N104672)); + .I4 (_N105507)); // LUT = ~I0&~I1&~I2&~I3&I4 ; GTP_LUT5 /* N45_8 */ #( .INIT(32'b00000000000000000000000001000000)) N45_8 ( - .Z (_N104664), + .Z (_N105499), .I0 (rd_ddr_empty), .I1 (cnt_times[0]), .I2 (cnt_times[4]), @@ -222366,7 +222092,7 @@ module axi_rd_connect .I1 (cnt_times[2]), .I2 (cnt_times[3]), .I3 (cnt_times[7]), - .I4 (_N104664)); + .I4 (_N105499)); // LUT = I0&I1&I2&~I3&I4 ; GTP_LUT5CARRY /* N69_1_1 */ #( @@ -222376,7 +222102,7 @@ module axi_rd_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_1_1 ( - .COUT (_N13608), + .COUT (_N13598), .Z (N69[1]), .CIN (), .I0 (cnt_times[0]), @@ -222396,9 +222122,9 @@ module axi_rd_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_1_2 ( - .COUT (_N13609), + .COUT (_N13599), .Z (N69[2]), - .CIN (_N13608), + .CIN (_N13598), .I0 (cnt_times[0]), .I1 (cnt_times[1]), .I2 (cnt_times[2]), @@ -222416,9 +222142,9 @@ module axi_rd_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_1_3 ( - .COUT (_N13610), + .COUT (_N13600), .Z (N69[3]), - .CIN (_N13609), + .CIN (_N13599), .I0 (), .I1 (cnt_times[3]), .I2 (), @@ -222436,9 +222162,9 @@ module axi_rd_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_1_4 ( - .COUT (_N13611), + .COUT (_N13601), .Z (N69[4]), - .CIN (_N13610), + .CIN (_N13600), .I0 (), .I1 (cnt_times[4]), .I2 (), @@ -222456,9 +222182,9 @@ module axi_rd_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_1_5 ( - .COUT (_N13612), + .COUT (_N13602), .Z (N69[5]), - .CIN (_N13611), + .CIN (_N13601), .I0 (), .I1 (cnt_times[5]), .I2 (), @@ -222476,9 +222202,9 @@ module axi_rd_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N69_1_6 ( - .COUT (_N13613), + .COUT (_N13603), .Z (N69[6]), - .CIN (_N13612), + .CIN (_N13602), .I0 (), .I1 (cnt_times[6]), .I2 (), @@ -222498,7 +222224,7 @@ module axi_rd_connect N69_1_7 ( .COUT (), .Z (N69[7]), - .CIN (_N13613), + .CIN (_N13603), .I0 (), .I1 (cnt_times[7]), .I2 (), @@ -222537,7 +222263,7 @@ module axi_rd_connect GTP_LUT4 /* N117_mux7_6 */ #( .INIT(16'b1111111111111110)) N117_mux7_6 ( - .Z (_N106741), + .Z (_N107553), .I0 (wr0_data_count[0]), .I1 (wr0_data_count[1]), .I2 (wr0_data_count[2]), @@ -222547,7 +222273,7 @@ module axi_rd_connect GTP_LUT4 /* N117_mux7_7 */ #( .INIT(16'b1111111111111110)) N117_mux7_7 ( - .Z (_N106742), + .Z (_N107554), .I0 (wr0_data_count[4]), .I1 (wr0_data_count[5]), .I2 (wr0_data_count[6]), @@ -222560,8 +222286,8 @@ module axi_rd_connect .Z (N119), .I0 (wr0_data_count[8]), .I1 (wr0_data_count[9]), - .I2 (_N106741), - .I3 (_N106742)); + .I2 (_N107553), + .I3 (_N107554)); // defparam N119_vname.orig_name = N119; // LUT = (~I0&~I1)|(~I1&~I2&~I3) ; @@ -222869,7 +222595,7 @@ module axi_rd_connect .wr_water_level (wr0_data_count), .\u_axi_ddr_top/u_axi_rd_connect/rid_dout0 ({1'bx, 1'bx, 1'bx, rid_dout0[0]}), .rd_empty (rd0_empty), - .N241_0 (N241_0), + .N242_0 (N242_0), .rd_clk (rd0_clk), .rd_rst (rst), .\u_axi_ddr_top/u_axi_rd_connect/rd_ddr_valid (rd_ddr_valid), @@ -222929,26 +222655,26 @@ module ipml_fifo_ctrl_v1_3_6 wire [10:0] \N161.co ; wire [9:0] N323; wire [10:0] \N323_5.co ; - wire _N15976; - wire _N15977; - wire _N15978; - wire _N15979; - wire _N15980; - wire _N15981; - wire _N15982; - wire _N15983; - wire _N15984; - wire _N15985; - wire _N15986; - wire _N15989; - wire _N15990; - wire _N15991; - wire _N15992; - wire _N15993; - wire _N15994; - wire _N15995; - wire _N15996; - wire _N15997; + wire _N15911; + wire _N15912; + wire _N15913; + wire _N15914; + wire _N15915; + wire _N15916; + wire _N15917; + wire _N15918; + wire _N15919; + wire _N15920; + wire _N15921; + wire _N15924; + wire _N15925; + wire _N15926; + wire _N15927; + wire _N15928; + wire _N15929; + wire _N15930; + wire _N15931; + wire _N15932; wire [9:0] nb0; wire [9:0] rbin; wire rempty; @@ -223641,7 +223367,7 @@ module ipml_fifo_ctrl_v1_3_6 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_1 ( - .COUT (_N15976), + .COUT (_N15911), .Z (N2[0]), .CIN (), .I0 (w_en), @@ -223661,9 +223387,9 @@ module ipml_fifo_ctrl_v1_3_6 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_2 ( - .COUT (_N15977), + .COUT (_N15912), .Z (N2[1]), - .CIN (_N15976), + .CIN (_N15911), .I0 (w_en), .I1 (waddr[0]), .I2 (waddr[1]), @@ -223681,9 +223407,9 @@ module ipml_fifo_ctrl_v1_3_6 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_3 ( - .COUT (_N15978), + .COUT (_N15913), .Z (N2[2]), - .CIN (_N15977), + .CIN (_N15912), .I0 (), .I1 (waddr[2]), .I2 (), @@ -223701,9 +223427,9 @@ module ipml_fifo_ctrl_v1_3_6 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_4 ( - .COUT (_N15979), + .COUT (_N15914), .Z (N2[3]), - .CIN (_N15978), + .CIN (_N15913), .I0 (), .I1 (waddr[3]), .I2 (), @@ -223721,9 +223447,9 @@ module ipml_fifo_ctrl_v1_3_6 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_5 ( - .COUT (_N15980), + .COUT (_N15915), .Z (N2[4]), - .CIN (_N15979), + .CIN (_N15914), .I0 (), .I1 (waddr[4]), .I2 (), @@ -223741,9 +223467,9 @@ module ipml_fifo_ctrl_v1_3_6 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_6 ( - .COUT (_N15981), + .COUT (_N15916), .Z (N2[5]), - .CIN (_N15980), + .CIN (_N15915), .I0 (), .I1 (waddr[5]), .I2 (), @@ -223761,9 +223487,9 @@ module ipml_fifo_ctrl_v1_3_6 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_7 ( - .COUT (_N15982), + .COUT (_N15917), .Z (N2[6]), - .CIN (_N15981), + .CIN (_N15916), .I0 (), .I1 (waddr[6]), .I2 (), @@ -223781,9 +223507,9 @@ module ipml_fifo_ctrl_v1_3_6 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_8 ( - .COUT (_N15983), + .COUT (_N15918), .Z (N2[7]), - .CIN (_N15982), + .CIN (_N15917), .I0 (), .I1 (waddr[7]), .I2 (), @@ -223801,9 +223527,9 @@ module ipml_fifo_ctrl_v1_3_6 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_9 ( - .COUT (_N15984), + .COUT (_N15919), .Z (N2[8]), - .CIN (_N15983), + .CIN (_N15918), .I0 (), .I1 (waddr[8]), .I2 (), @@ -223821,9 +223547,9 @@ module ipml_fifo_ctrl_v1_3_6 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_10 ( - .COUT (_N15985), + .COUT (_N15920), .Z (N2[9]), - .CIN (_N15984), + .CIN (_N15919), .I0 (), .I1 (waddr[9]), .I2 (), @@ -223841,9 +223567,9 @@ module ipml_fifo_ctrl_v1_3_6 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_11 ( - .COUT (_N15986), + .COUT (_N15921), .Z (N2[10]), - .CIN (_N15985), + .CIN (_N15920), .I0 (), .I1 (waddr[10]), .I2 (), @@ -223863,7 +223589,7 @@ module ipml_fifo_ctrl_v1_3_6 N2_12 ( .COUT (), .Z (N2[11]), - .CIN (_N15986), + .CIN (_N15921), .I0 (), .I1 (wbin[11]), .I2 (), @@ -224144,7 +223870,7 @@ module ipml_fifo_ctrl_v1_3_6 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_1 ( - .COUT (_N15989), + .COUT (_N15924), .Z (N74[0]), .CIN (), .I0 (r_en), @@ -224164,9 +223890,9 @@ module ipml_fifo_ctrl_v1_3_6 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_2 ( - .COUT (_N15990), + .COUT (_N15925), .Z (N74[1]), - .CIN (_N15989), + .CIN (_N15924), .I0 (r_en), .I1 (raddr[0]), .I2 (raddr[1]), @@ -224184,9 +223910,9 @@ module ipml_fifo_ctrl_v1_3_6 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_3 ( - .COUT (_N15991), + .COUT (_N15926), .Z (N74[2]), - .CIN (_N15990), + .CIN (_N15925), .I0 (), .I1 (raddr[2]), .I2 (), @@ -224204,9 +223930,9 @@ module ipml_fifo_ctrl_v1_3_6 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_4 ( - .COUT (_N15992), + .COUT (_N15927), .Z (N74[3]), - .CIN (_N15991), + .CIN (_N15926), .I0 (), .I1 (raddr[3]), .I2 (), @@ -224224,9 +223950,9 @@ module ipml_fifo_ctrl_v1_3_6 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_5 ( - .COUT (_N15993), + .COUT (_N15928), .Z (N74[4]), - .CIN (_N15992), + .CIN (_N15927), .I0 (), .I1 (raddr[4]), .I2 (), @@ -224244,9 +223970,9 @@ module ipml_fifo_ctrl_v1_3_6 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_6 ( - .COUT (_N15994), + .COUT (_N15929), .Z (N74[5]), - .CIN (_N15993), + .CIN (_N15928), .I0 (), .I1 (raddr[5]), .I2 (), @@ -224264,9 +223990,9 @@ module ipml_fifo_ctrl_v1_3_6 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_7 ( - .COUT (_N15995), + .COUT (_N15930), .Z (N74[6]), - .CIN (_N15994), + .CIN (_N15929), .I0 (), .I1 (raddr[6]), .I2 (), @@ -224284,9 +224010,9 @@ module ipml_fifo_ctrl_v1_3_6 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_8 ( - .COUT (_N15996), + .COUT (_N15931), .Z (N74[7]), - .CIN (_N15995), + .CIN (_N15930), .I0 (), .I1 (raddr[7]), .I2 (), @@ -224304,9 +224030,9 @@ module ipml_fifo_ctrl_v1_3_6 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_9 ( - .COUT (_N15997), + .COUT (_N15932), .Z (N74[8]), - .CIN (_N15996), + .CIN (_N15931), .I0 (), .I1 (raddr[8]), .I2 (), @@ -224326,7 +224052,7 @@ module ipml_fifo_ctrl_v1_3_6 N74_10 ( .COUT (), .Z (N74[9]), - .CIN (_N15997), + .CIN (_N15932), .I0 (), .I1 (rbin[9]), .I2 (), @@ -225656,27 +225382,27 @@ module ipml_fifo_ctrl_v1_3_6_unq8 wire [10:0] \N161.co ; wire [9:0] N323; wire [10:0] \N323_5.co ; - wire _N16000; - wire _N16001; - wire _N16002; - wire _N16003; - wire _N16004; - wire _N16005; - wire _N16006; - wire _N16007; - wire _N16008; - wire _N16009; - wire _N16010; - wire _N16013; - wire _N16014; - wire _N16015; - wire _N16016; - wire _N16017; - wire _N16018; - wire _N16019; - wire _N16020; - wire _N16021; - wire _N108381; + wire _N15958; + wire _N15959; + wire _N15960; + wire _N15961; + wire _N15962; + wire _N15963; + wire _N15964; + wire _N15965; + wire _N15966; + wire _N15967; + wire _N15968; + wire _N15971; + wire _N15972; + wire _N15973; + wire _N15974; + wire _N15975; + wire _N15976; + wire _N15977; + wire _N15978; + wire _N15979; + wire _N109251; wire [9:0] nb0; wire [9:0] rbin; wire rempty; @@ -226369,7 +226095,7 @@ module ipml_fifo_ctrl_v1_3_6_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_1 ( - .COUT (_N16000), + .COUT (_N15958), .Z (N2[0]), .CIN (), .I0 (w_en), @@ -226389,9 +226115,9 @@ module ipml_fifo_ctrl_v1_3_6_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_2 ( - .COUT (_N16001), + .COUT (_N15959), .Z (N2[1]), - .CIN (_N16000), + .CIN (_N15958), .I0 (w_en), .I1 (waddr[0]), .I2 (waddr[1]), @@ -226409,9 +226135,9 @@ module ipml_fifo_ctrl_v1_3_6_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_3 ( - .COUT (_N16002), + .COUT (_N15960), .Z (N2[2]), - .CIN (_N16001), + .CIN (_N15959), .I0 (), .I1 (waddr[2]), .I2 (), @@ -226429,9 +226155,9 @@ module ipml_fifo_ctrl_v1_3_6_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_4 ( - .COUT (_N16003), + .COUT (_N15961), .Z (N2[3]), - .CIN (_N16002), + .CIN (_N15960), .I0 (), .I1 (waddr[3]), .I2 (), @@ -226449,9 +226175,9 @@ module ipml_fifo_ctrl_v1_3_6_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_5 ( - .COUT (_N16004), + .COUT (_N15962), .Z (N2[4]), - .CIN (_N16003), + .CIN (_N15961), .I0 (), .I1 (waddr[4]), .I2 (), @@ -226469,9 +226195,9 @@ module ipml_fifo_ctrl_v1_3_6_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_6 ( - .COUT (_N16005), + .COUT (_N15963), .Z (N2[5]), - .CIN (_N16004), + .CIN (_N15962), .I0 (), .I1 (waddr[5]), .I2 (), @@ -226489,9 +226215,9 @@ module ipml_fifo_ctrl_v1_3_6_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_7 ( - .COUT (_N16006), + .COUT (_N15964), .Z (N2[6]), - .CIN (_N16005), + .CIN (_N15963), .I0 (), .I1 (waddr[6]), .I2 (), @@ -226509,9 +226235,9 @@ module ipml_fifo_ctrl_v1_3_6_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_8 ( - .COUT (_N16007), + .COUT (_N15965), .Z (N2[7]), - .CIN (_N16006), + .CIN (_N15964), .I0 (), .I1 (waddr[7]), .I2 (), @@ -226529,9 +226255,9 @@ module ipml_fifo_ctrl_v1_3_6_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_9 ( - .COUT (_N16008), + .COUT (_N15966), .Z (N2[8]), - .CIN (_N16007), + .CIN (_N15965), .I0 (), .I1 (waddr[8]), .I2 (), @@ -226549,9 +226275,9 @@ module ipml_fifo_ctrl_v1_3_6_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_10 ( - .COUT (_N16009), + .COUT (_N15967), .Z (N2[9]), - .CIN (_N16008), + .CIN (_N15966), .I0 (), .I1 (waddr[9]), .I2 (), @@ -226569,9 +226295,9 @@ module ipml_fifo_ctrl_v1_3_6_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_11 ( - .COUT (_N16010), + .COUT (_N15968), .Z (N2[10]), - .CIN (_N16009), + .CIN (_N15967), .I0 (), .I1 (waddr[10]), .I2 (), @@ -226591,7 +226317,7 @@ module ipml_fifo_ctrl_v1_3_6_unq8 N2_12 ( .COUT (), .Z (N2[11]), - .CIN (_N16010), + .CIN (_N15968), .I0 (), .I1 (wbin[11]), .I2 (), @@ -226645,7 +226371,7 @@ module ipml_fifo_ctrl_v1_3_6_unq8 GTP_LUT4 /* \N3[5]_1 */ #( .INIT(16'b1101100000100111)) \N3[5]_1 ( - .Z (_N108381), + .Z (_N109251), .I0 (wfull), .I1 (waddr[5]), .I2 (N2[5]), @@ -226893,7 +226619,7 @@ module ipml_fifo_ctrl_v1_3_6_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_1 ( - .COUT (_N16013), + .COUT (_N15971), .Z (N74[0]), .CIN (), .I0 (r_en), @@ -226913,9 +226639,9 @@ module ipml_fifo_ctrl_v1_3_6_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_2 ( - .COUT (_N16014), + .COUT (_N15972), .Z (N74[1]), - .CIN (_N16013), + .CIN (_N15971), .I0 (r_en), .I1 (raddr[0]), .I2 (raddr[1]), @@ -226933,9 +226659,9 @@ module ipml_fifo_ctrl_v1_3_6_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_3 ( - .COUT (_N16015), + .COUT (_N15973), .Z (N74[2]), - .CIN (_N16014), + .CIN (_N15972), .I0 (), .I1 (raddr[2]), .I2 (), @@ -226953,9 +226679,9 @@ module ipml_fifo_ctrl_v1_3_6_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_4 ( - .COUT (_N16016), + .COUT (_N15974), .Z (N74[3]), - .CIN (_N16015), + .CIN (_N15973), .I0 (), .I1 (raddr[3]), .I2 (), @@ -226973,9 +226699,9 @@ module ipml_fifo_ctrl_v1_3_6_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_5 ( - .COUT (_N16017), + .COUT (_N15975), .Z (N74[4]), - .CIN (_N16016), + .CIN (_N15974), .I0 (), .I1 (raddr[4]), .I2 (), @@ -226993,9 +226719,9 @@ module ipml_fifo_ctrl_v1_3_6_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_6 ( - .COUT (_N16018), + .COUT (_N15976), .Z (N74[5]), - .CIN (_N16017), + .CIN (_N15975), .I0 (), .I1 (raddr[5]), .I2 (), @@ -227013,9 +226739,9 @@ module ipml_fifo_ctrl_v1_3_6_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_7 ( - .COUT (_N16019), + .COUT (_N15977), .Z (N74[6]), - .CIN (_N16018), + .CIN (_N15976), .I0 (), .I1 (raddr[6]), .I2 (), @@ -227033,9 +226759,9 @@ module ipml_fifo_ctrl_v1_3_6_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_8 ( - .COUT (_N16020), + .COUT (_N15978), .Z (N74[7]), - .CIN (_N16019), + .CIN (_N15977), .I0 (), .I1 (raddr[7]), .I2 (), @@ -227053,9 +226779,9 @@ module ipml_fifo_ctrl_v1_3_6_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_9 ( - .COUT (_N16021), + .COUT (_N15979), .Z (N74[8]), - .CIN (_N16020), + .CIN (_N15978), .I0 (), .I1 (raddr[8]), .I2 (), @@ -227075,7 +226801,7 @@ module ipml_fifo_ctrl_v1_3_6_unq8 N74_10 ( .COUT (), .Z (N74[9]), - .CIN (_N16021), + .CIN (_N15979), .I0 (), .I1 (rbin[9]), .I2 (), @@ -227432,7 +227158,7 @@ module ipml_fifo_ctrl_v1_3_6_unq8 .I0 (wwptr[4]), .I1 (wrptr2_b[2]), .I2 (wrptr2[3]), - .I3 (_N108381), + .I3 (_N109251), .I4 (), .ID ()); // LUT = 1'b0 ; @@ -228405,6 +228131,19 @@ module ipml_fifo_ctrl_v1_3_6_unq10 wire [10:0] \N161.co ; wire [9:0] N323; wire [10:0] \N323_5.co ; + wire _N16045; + wire _N16046; + wire _N16047; + wire _N16048; + wire _N16049; + wire _N16050; + wire _N16051; + wire _N16052; + wire _N16053; + wire _N16054; + wire _N16055; + wire _N16058; + wire _N16059; wire _N16060; wire _N16061; wire _N16062; @@ -228412,19 +228151,6 @@ module ipml_fifo_ctrl_v1_3_6_unq10 wire _N16064; wire _N16065; wire _N16066; - wire _N16067; - wire _N16068; - wire _N16069; - wire _N16070; - wire _N16073; - wire _N16074; - wire _N16075; - wire _N16076; - wire _N16077; - wire _N16078; - wire _N16079; - wire _N16080; - wire _N16081; wire [9:0] nb0; wire [9:0] rbin; wire rempty; @@ -229117,7 +228843,7 @@ module ipml_fifo_ctrl_v1_3_6_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_1 ( - .COUT (_N16060), + .COUT (_N16045), .Z (N2[0]), .CIN (), .I0 (w_en), @@ -229137,9 +228863,9 @@ module ipml_fifo_ctrl_v1_3_6_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_2 ( - .COUT (_N16061), + .COUT (_N16046), .Z (N2[1]), - .CIN (_N16060), + .CIN (_N16045), .I0 (w_en), .I1 (waddr[0]), .I2 (waddr[1]), @@ -229157,9 +228883,9 @@ module ipml_fifo_ctrl_v1_3_6_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_3 ( - .COUT (_N16062), + .COUT (_N16047), .Z (N2[2]), - .CIN (_N16061), + .CIN (_N16046), .I0 (), .I1 (waddr[2]), .I2 (), @@ -229177,9 +228903,9 @@ module ipml_fifo_ctrl_v1_3_6_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_4 ( - .COUT (_N16063), + .COUT (_N16048), .Z (N2[3]), - .CIN (_N16062), + .CIN (_N16047), .I0 (), .I1 (waddr[3]), .I2 (), @@ -229197,9 +228923,9 @@ module ipml_fifo_ctrl_v1_3_6_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_5 ( - .COUT (_N16064), + .COUT (_N16049), .Z (N2[4]), - .CIN (_N16063), + .CIN (_N16048), .I0 (), .I1 (waddr[4]), .I2 (), @@ -229217,9 +228943,9 @@ module ipml_fifo_ctrl_v1_3_6_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_6 ( - .COUT (_N16065), + .COUT (_N16050), .Z (N2[5]), - .CIN (_N16064), + .CIN (_N16049), .I0 (), .I1 (waddr[5]), .I2 (), @@ -229237,9 +228963,9 @@ module ipml_fifo_ctrl_v1_3_6_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_7 ( - .COUT (_N16066), + .COUT (_N16051), .Z (N2[6]), - .CIN (_N16065), + .CIN (_N16050), .I0 (), .I1 (waddr[6]), .I2 (), @@ -229257,9 +228983,9 @@ module ipml_fifo_ctrl_v1_3_6_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_8 ( - .COUT (_N16067), + .COUT (_N16052), .Z (N2[7]), - .CIN (_N16066), + .CIN (_N16051), .I0 (), .I1 (waddr[7]), .I2 (), @@ -229277,9 +229003,9 @@ module ipml_fifo_ctrl_v1_3_6_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_9 ( - .COUT (_N16068), + .COUT (_N16053), .Z (N2[8]), - .CIN (_N16067), + .CIN (_N16052), .I0 (), .I1 (waddr[8]), .I2 (), @@ -229297,9 +229023,9 @@ module ipml_fifo_ctrl_v1_3_6_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_10 ( - .COUT (_N16069), + .COUT (_N16054), .Z (N2[9]), - .CIN (_N16068), + .CIN (_N16053), .I0 (), .I1 (waddr[9]), .I2 (), @@ -229317,9 +229043,9 @@ module ipml_fifo_ctrl_v1_3_6_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_11 ( - .COUT (_N16070), + .COUT (_N16055), .Z (N2[10]), - .CIN (_N16069), + .CIN (_N16054), .I0 (), .I1 (waddr[10]), .I2 (), @@ -229339,7 +229065,7 @@ module ipml_fifo_ctrl_v1_3_6_unq10 N2_12 ( .COUT (), .Z (N2[11]), - .CIN (_N16070), + .CIN (_N16055), .I0 (), .I1 (wbin[11]), .I2 (), @@ -229620,7 +229346,7 @@ module ipml_fifo_ctrl_v1_3_6_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_1 ( - .COUT (_N16073), + .COUT (_N16058), .Z (N74[0]), .CIN (), .I0 (r_en), @@ -229640,9 +229366,9 @@ module ipml_fifo_ctrl_v1_3_6_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_2 ( - .COUT (_N16074), + .COUT (_N16059), .Z (N74[1]), - .CIN (_N16073), + .CIN (_N16058), .I0 (r_en), .I1 (raddr[0]), .I2 (raddr[1]), @@ -229660,9 +229386,9 @@ module ipml_fifo_ctrl_v1_3_6_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_3 ( - .COUT (_N16075), + .COUT (_N16060), .Z (N74[2]), - .CIN (_N16074), + .CIN (_N16059), .I0 (), .I1 (raddr[2]), .I2 (), @@ -229680,9 +229406,9 @@ module ipml_fifo_ctrl_v1_3_6_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_4 ( - .COUT (_N16076), + .COUT (_N16061), .Z (N74[3]), - .CIN (_N16075), + .CIN (_N16060), .I0 (), .I1 (raddr[3]), .I2 (), @@ -229700,9 +229426,9 @@ module ipml_fifo_ctrl_v1_3_6_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_5 ( - .COUT (_N16077), + .COUT (_N16062), .Z (N74[4]), - .CIN (_N16076), + .CIN (_N16061), .I0 (), .I1 (raddr[4]), .I2 (), @@ -229720,9 +229446,9 @@ module ipml_fifo_ctrl_v1_3_6_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_6 ( - .COUT (_N16078), + .COUT (_N16063), .Z (N74[5]), - .CIN (_N16077), + .CIN (_N16062), .I0 (), .I1 (raddr[5]), .I2 (), @@ -229740,9 +229466,9 @@ module ipml_fifo_ctrl_v1_3_6_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_7 ( - .COUT (_N16079), + .COUT (_N16064), .Z (N74[6]), - .CIN (_N16078), + .CIN (_N16063), .I0 (), .I1 (raddr[6]), .I2 (), @@ -229760,9 +229486,9 @@ module ipml_fifo_ctrl_v1_3_6_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_8 ( - .COUT (_N16080), + .COUT (_N16065), .Z (N74[7]), - .CIN (_N16079), + .CIN (_N16064), .I0 (), .I1 (raddr[7]), .I2 (), @@ -229780,9 +229506,9 @@ module ipml_fifo_ctrl_v1_3_6_unq10 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_9 ( - .COUT (_N16081), + .COUT (_N16066), .Z (N74[8]), - .CIN (_N16080), + .CIN (_N16065), .I0 (), .I1 (raddr[8]), .I2 (), @@ -229802,7 +229528,7 @@ module ipml_fifo_ctrl_v1_3_6_unq10 N74_10 ( .COUT (), .Z (N74[9]), - .CIN (_N16081), + .CIN (_N16066), .I0 (), .I1 (rbin[9]), .I2 (), @@ -231184,103 +230910,103 @@ module axi_wr_connect wire _N55; wire _N56; wire _N57; - wire _N8651_inv; - wire _N8667_inv; - wire _N8699_inv; - wire _N13627; - wire _N13628; - wire _N13629; - wire _N13630; - wire _N13631; - wire _N15770; - wire _N15771; - wire _N15772; - wire _N15773; - wire _N15774; - wire _N15775; - wire _N15776; - wire _N15777; - wire _N15778; - wire _N15779; - wire _N15780; - wire _N15781; - wire _N15782; - wire _N15783; - wire _N15888; - wire _N15889; - wire _N15890; - wire _N15891; - wire _N15892; - wire _N15893; - wire _N15894; - wire _N15895; - wire _N15896; - wire _N15897; - wire _N15898; - wire _N15899; - wire _N15900; - wire _N15901; - wire _N15904; - wire _N15905; - wire _N15906; - wire _N15907; - wire _N15908; - wire _N15909; - wire _N15910; - wire _N15911; - wire _N15912; - wire _N15913; - wire _N15914; - wire _N15915; - wire _N15916; - wire _N15917; - wire _N15941; - wire _N15942; - wire _N15943; - wire _N15944; - wire _N15945; - wire _N15946; - wire _N15947; - wire _N15948; - wire _N15949; - wire _N15950; - wire _N15951; - wire _N15952; - wire _N15953; - wire _N15954; - wire _N15955; - wire _N15956; - wire _N22101; - wire _N25394; - wire _N25395; - wire _N25396; - wire _N25397; - wire _N25398; - wire _N25399; - wire _N25400; - wire _N25401; - wire _N25402; - wire _N25410; - wire _N25411; - wire _N97111; - wire _N97193; - wire _N103323; - wire _N103538; - wire _N103540; - wire _N103542; - wire _N103655; - wire _N103659; - wire _N103660; - wire _N103661; - wire _N103693; - wire _N103697; - wire _N103698; - wire _N103699; - wire _N103941; - wire _N103945; - wire _N103946; - wire _N103947; - wire _N104099; + wire _N8685_inv; + wire _N8701_inv; + wire _N8733_inv; + wire _N13606; + wire _N13607; + wire _N13608; + wire _N13609; + wire _N13610; + wire _N15706; + wire _N15707; + wire _N15708; + wire _N15709; + wire _N15710; + wire _N15711; + wire _N15712; + wire _N15713; + wire _N15714; + wire _N15715; + wire _N15716; + wire _N15717; + wire _N15718; + wire _N15719; + wire _N15818; + wire _N15819; + wire _N15820; + wire _N15821; + wire _N15822; + wire _N15823; + wire _N15824; + wire _N15825; + wire _N15826; + wire _N15827; + wire _N15828; + wire _N15829; + wire _N15830; + wire _N15831; + wire _N15834; + wire _N15835; + wire _N15836; + wire _N15837; + wire _N15838; + wire _N15839; + wire _N15840; + wire _N15841; + wire _N15842; + wire _N15843; + wire _N15844; + wire _N15845; + wire _N15846; + wire _N15847; + wire _N15872; + wire _N15873; + wire _N15874; + wire _N15875; + wire _N15876; + wire _N15877; + wire _N15878; + wire _N15879; + wire _N15880; + wire _N15881; + wire _N15882; + wire _N15883; + wire _N15884; + wire _N15885; + wire _N15886; + wire _N15887; + wire _N22037; + wire _N25244; + wire _N25245; + wire _N25246; + wire _N25247; + wire _N25248; + wire _N25249; + wire _N25250; + wire _N25251; + wire _N25252; + wire _N25260; + wire _N25261; + wire _N97877; + wire _N97954; + wire _N104135; + wire _N104350; + wire _N104352; + wire _N104354; + wire _N104472; + wire _N104476; + wire _N104477; + wire _N104478; + wire _N104512; + wire _N104516; + wire _N104517; + wire _N104518; + wire _N104765; + wire _N104769; + wire _N104770; + wire _N104771; + wire _N104928; wire [6:0] cnt_times; wire \cnt_times[0]_inv ; wire ddr0_valid_fall; @@ -231409,7 +231135,7 @@ module axi_wr_connect GTP_LUT5 /* N196_4 */ #( .INIT(32'b01010000000000001100110011001100)) N196_4 ( - .Z (_N22101), + .Z (_N22037), .I0 (axi_fifo_full), .I1 (N244), .I2 (fifo3_data_full), @@ -231424,7 +231150,7 @@ module axi_wr_connect .I0 (N471), .I1 (rd_sta0[1]), .I2 (rd_sta0[7]), - .I3 (_N97193)); + .I3 (_N97954)); // LUT = (I0)|(I1&~I2&I3)|(~I1&I2&I3) ; GTP_LUT4 /* N244 */ #( @@ -231445,7 +231171,7 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N248_1_1 ( - .COUT (_N15770), + .COUT (_N15706), .Z (N248[1]), .CIN (), .I0 (wr0_cnt_num[0]), @@ -231465,9 +231191,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N248_1_2 ( - .COUT (_N15771), + .COUT (_N15707), .Z (N248[2]), - .CIN (_N15770), + .CIN (_N15706), .I0 (wr0_cnt_num[0]), .I1 (wr0_cnt_num[1]), .I2 (wr0_cnt_num[2]), @@ -231485,9 +231211,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N248_1_3 ( - .COUT (_N15772), + .COUT (_N15708), .Z (N248[3]), - .CIN (_N15771), + .CIN (_N15707), .I0 (), .I1 (wr0_cnt_num[3]), .I2 (), @@ -231505,9 +231231,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N248_1_4 ( - .COUT (_N15773), + .COUT (_N15709), .Z (N248[4]), - .CIN (_N15772), + .CIN (_N15708), .I0 (), .I1 (wr0_cnt_num[4]), .I2 (), @@ -231525,9 +231251,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N248_1_5 ( - .COUT (_N15774), + .COUT (_N15710), .Z (N248[5]), - .CIN (_N15773), + .CIN (_N15709), .I0 (), .I1 (wr0_cnt_num[5]), .I2 (), @@ -231545,9 +231271,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N248_1_6 ( - .COUT (_N15775), + .COUT (_N15711), .Z (N248[6]), - .CIN (_N15774), + .CIN (_N15710), .I0 (), .I1 (wr0_cnt_num[6]), .I2 (), @@ -231565,9 +231291,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N248_1_7 ( - .COUT (_N15776), + .COUT (_N15712), .Z (N248[7]), - .CIN (_N15775), + .CIN (_N15711), .I0 (), .I1 (wr0_cnt_num[7]), .I2 (), @@ -231585,9 +231311,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N248_1_8 ( - .COUT (_N15777), + .COUT (_N15713), .Z (N248[8]), - .CIN (_N15776), + .CIN (_N15712), .I0 (), .I1 (wr0_cnt_num[8]), .I2 (), @@ -231605,9 +231331,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N248_1_9 ( - .COUT (_N15778), + .COUT (_N15714), .Z (N248[9]), - .CIN (_N15777), + .CIN (_N15713), .I0 (), .I1 (wr0_cnt_num[9]), .I2 (), @@ -231625,9 +231351,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N248_1_10 ( - .COUT (_N15779), + .COUT (_N15715), .Z (N248[10]), - .CIN (_N15778), + .CIN (_N15714), .I0 (), .I1 (wr0_cnt_num[10]), .I2 (), @@ -231645,9 +231371,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N248_1_11 ( - .COUT (_N15780), + .COUT (_N15716), .Z (N248[11]), - .CIN (_N15779), + .CIN (_N15715), .I0 (), .I1 (wr0_cnt_num[11]), .I2 (), @@ -231665,9 +231391,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N248_1_12 ( - .COUT (_N15781), + .COUT (_N15717), .Z (N248[12]), - .CIN (_N15780), + .CIN (_N15716), .I0 (), .I1 (wr0_cnt_num[12]), .I2 (), @@ -231685,9 +231411,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N248_1_13 ( - .COUT (_N15782), + .COUT (_N15718), .Z (N248[13]), - .CIN (_N15781), + .CIN (_N15717), .I0 (), .I1 (wr0_cnt_num[13]), .I2 (), @@ -231705,9 +231431,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N248_1_14 ( - .COUT (_N15783), + .COUT (_N15719), .Z (N248[14]), - .CIN (_N15782), + .CIN (_N15718), .I0 (), .I1 (wr0_cnt_num[14]), .I2 (), @@ -231727,7 +231453,7 @@ module axi_wr_connect N248_1_15 ( .COUT (), .Z (N248[15]), - .CIN (_N15783), + .CIN (_N15719), .I0 (), .I1 (wr0_cnt_num[15]), .I2 (), @@ -231741,7 +231467,7 @@ module axi_wr_connect GTP_LUT5 /* N249_8 */ #( .INIT(32'b00000000000000000000000000000001)) N249_8 ( - .Z (_N103693), + .Z (_N104512), .I0 (wr0_cnt_num[6]), .I1 (wr0_cnt_num[7]), .I2 (wr0_cnt_num[8]), @@ -231752,7 +231478,7 @@ module axi_wr_connect GTP_LUT5 /* N249_12 */ #( .INIT(32'b00000000000000000000000010000000)) N249_12 ( - .Z (_N103697), + .Z (_N104516), .I0 (wr0_cnt_num[4]), .I1 (wr0_cnt_num[9]), .I2 (wr0_cnt_num[10]), @@ -231763,7 +231489,7 @@ module axi_wr_connect GTP_LUT2 /* N249_13 */ #( .INIT(4'b0100)) N249_13 ( - .Z (_N103698), + .Z (_N104517), .I0 (wr0_cnt_num[0]), .I1 (wr0_cnt_num[11])); // LUT = ~I0&I1 ; @@ -231771,18 +231497,18 @@ module axi_wr_connect GTP_LUT5 /* N249_14 */ #( .INIT(32'b00000000000000010000000000000000)) N249_14 ( - .Z (_N103699), + .Z (_N104518), .I0 (wr0_cnt_num[1]), .I1 (wr0_cnt_num[2]), .I2 (wr0_cnt_num[3]), .I3 (wr0_cnt_num[5]), - .I4 (_N103698)); + .I4 (_N104517)); // LUT = ~I0&~I1&~I2&~I3&I4 ; GTP_LUT1 /* N249_eq0_inv */ #( .INIT(2'b01)) N249_eq0_inv ( - .Z (_N8651_inv), + .Z (_N8685_inv), .I0 (wr0_cnt_num[0])); // LUT = ~I0 ; @@ -231804,7 +231530,7 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N263_1_1 ( - .COUT (_N15888), + .COUT (_N15818), .Z (N263[1]), .CIN (), .I0 (wr1_cnt_num[0]), @@ -231824,9 +231550,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N263_1_2 ( - .COUT (_N15889), + .COUT (_N15819), .Z (N263[2]), - .CIN (_N15888), + .CIN (_N15818), .I0 (wr1_cnt_num[0]), .I1 (wr1_cnt_num[1]), .I2 (wr1_cnt_num[2]), @@ -231844,9 +231570,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N263_1_3 ( - .COUT (_N15890), + .COUT (_N15820), .Z (N263[3]), - .CIN (_N15889), + .CIN (_N15819), .I0 (), .I1 (wr1_cnt_num[3]), .I2 (), @@ -231864,9 +231590,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N263_1_4 ( - .COUT (_N15891), + .COUT (_N15821), .Z (N263[4]), - .CIN (_N15890), + .CIN (_N15820), .I0 (), .I1 (wr1_cnt_num[4]), .I2 (), @@ -231884,9 +231610,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N263_1_5 ( - .COUT (_N15892), + .COUT (_N15822), .Z (N263[5]), - .CIN (_N15891), + .CIN (_N15821), .I0 (), .I1 (wr1_cnt_num[5]), .I2 (), @@ -231904,9 +231630,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N263_1_6 ( - .COUT (_N15893), + .COUT (_N15823), .Z (N263[6]), - .CIN (_N15892), + .CIN (_N15822), .I0 (), .I1 (wr1_cnt_num[6]), .I2 (), @@ -231924,9 +231650,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N263_1_7 ( - .COUT (_N15894), + .COUT (_N15824), .Z (N263[7]), - .CIN (_N15893), + .CIN (_N15823), .I0 (), .I1 (wr1_cnt_num[7]), .I2 (), @@ -231944,9 +231670,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N263_1_8 ( - .COUT (_N15895), + .COUT (_N15825), .Z (N263[8]), - .CIN (_N15894), + .CIN (_N15824), .I0 (), .I1 (wr1_cnt_num[8]), .I2 (), @@ -231964,9 +231690,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N263_1_9 ( - .COUT (_N15896), + .COUT (_N15826), .Z (N263[9]), - .CIN (_N15895), + .CIN (_N15825), .I0 (), .I1 (wr1_cnt_num[9]), .I2 (), @@ -231984,9 +231710,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N263_1_10 ( - .COUT (_N15897), + .COUT (_N15827), .Z (N263[10]), - .CIN (_N15896), + .CIN (_N15826), .I0 (), .I1 (wr1_cnt_num[10]), .I2 (), @@ -232004,9 +231730,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N263_1_11 ( - .COUT (_N15898), + .COUT (_N15828), .Z (N263[11]), - .CIN (_N15897), + .CIN (_N15827), .I0 (), .I1 (wr1_cnt_num[11]), .I2 (), @@ -232024,9 +231750,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N263_1_12 ( - .COUT (_N15899), + .COUT (_N15829), .Z (N263[12]), - .CIN (_N15898), + .CIN (_N15828), .I0 (), .I1 (wr1_cnt_num[12]), .I2 (), @@ -232044,9 +231770,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N263_1_13 ( - .COUT (_N15900), + .COUT (_N15830), .Z (N263[13]), - .CIN (_N15899), + .CIN (_N15829), .I0 (), .I1 (wr1_cnt_num[13]), .I2 (), @@ -232064,9 +231790,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N263_1_14 ( - .COUT (_N15901), + .COUT (_N15831), .Z (N263[14]), - .CIN (_N15900), + .CIN (_N15830), .I0 (), .I1 (wr1_cnt_num[14]), .I2 (), @@ -232086,7 +231812,7 @@ module axi_wr_connect N263_1_15 ( .COUT (), .Z (N263[15]), - .CIN (_N15901), + .CIN (_N15831), .I0 (), .I1 (wr1_cnt_num[15]), .I2 (), @@ -232100,7 +231826,7 @@ module axi_wr_connect GTP_LUT5 /* N264_8 */ #( .INIT(32'b00000000000000000000000000000001)) N264_8 ( - .Z (_N103941), + .Z (_N104765), .I0 (wr1_cnt_num[6]), .I1 (wr1_cnt_num[7]), .I2 (wr1_cnt_num[11]), @@ -232111,7 +231837,7 @@ module axi_wr_connect GTP_LUT5 /* N264_12 */ #( .INIT(32'b00000000000000000000000010000000)) N264_12 ( - .Z (_N103945), + .Z (_N104769), .I0 (wr1_cnt_num[3]), .I1 (wr1_cnt_num[8]), .I2 (wr1_cnt_num[9]), @@ -232122,7 +231848,7 @@ module axi_wr_connect GTP_LUT2 /* N264_13 */ #( .INIT(4'b0100)) N264_13 ( - .Z (_N103946), + .Z (_N104770), .I0 (wr1_cnt_num[0]), .I1 (wr1_cnt_num[10])); // LUT = ~I0&I1 ; @@ -232130,18 +231856,18 @@ module axi_wr_connect GTP_LUT5 /* N264_14 */ #( .INIT(32'b00000000000000010000000000000000)) N264_14 ( - .Z (_N103947), + .Z (_N104771), .I0 (wr1_cnt_num[1]), .I1 (wr1_cnt_num[2]), .I2 (wr1_cnt_num[4]), .I3 (wr1_cnt_num[5]), - .I4 (_N103946)); + .I4 (_N104770)); // LUT = ~I0&~I1&~I2&~I3&I4 ; GTP_LUT1 /* N264_eq0_inv */ #( .INIT(2'b01)) N264_eq0_inv ( - .Z (_N8667_inv), + .Z (_N8701_inv), .I0 (wr1_cnt_num[0])); // LUT = ~I0 ; @@ -232152,7 +231878,7 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N293_1_1 ( - .COUT (_N15904), + .COUT (_N15834), .Z (N293[1]), .CIN (), .I0 (wr3_cnt_num[0]), @@ -232172,9 +231898,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N293_1_2 ( - .COUT (_N15905), + .COUT (_N15835), .Z (N293[2]), - .CIN (_N15904), + .CIN (_N15834), .I0 (wr3_cnt_num[0]), .I1 (wr3_cnt_num[1]), .I2 (wr3_cnt_num[2]), @@ -232192,9 +231918,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N293_1_3 ( - .COUT (_N15906), + .COUT (_N15836), .Z (N293[3]), - .CIN (_N15905), + .CIN (_N15835), .I0 (), .I1 (wr3_cnt_num[3]), .I2 (), @@ -232212,9 +231938,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N293_1_4 ( - .COUT (_N15907), + .COUT (_N15837), .Z (N293[4]), - .CIN (_N15906), + .CIN (_N15836), .I0 (), .I1 (wr3_cnt_num[4]), .I2 (), @@ -232232,9 +231958,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N293_1_5 ( - .COUT (_N15908), + .COUT (_N15838), .Z (N293[5]), - .CIN (_N15907), + .CIN (_N15837), .I0 (), .I1 (wr3_cnt_num[5]), .I2 (), @@ -232252,9 +231978,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N293_1_6 ( - .COUT (_N15909), + .COUT (_N15839), .Z (N293[6]), - .CIN (_N15908), + .CIN (_N15838), .I0 (), .I1 (wr3_cnt_num[6]), .I2 (), @@ -232272,9 +231998,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N293_1_7 ( - .COUT (_N15910), + .COUT (_N15840), .Z (N293[7]), - .CIN (_N15909), + .CIN (_N15839), .I0 (), .I1 (wr3_cnt_num[7]), .I2 (), @@ -232292,9 +232018,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N293_1_8 ( - .COUT (_N15911), + .COUT (_N15841), .Z (N293[8]), - .CIN (_N15910), + .CIN (_N15840), .I0 (), .I1 (wr3_cnt_num[8]), .I2 (), @@ -232312,9 +232038,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N293_1_9 ( - .COUT (_N15912), + .COUT (_N15842), .Z (N293[9]), - .CIN (_N15911), + .CIN (_N15841), .I0 (), .I1 (wr3_cnt_num[9]), .I2 (), @@ -232332,9 +232058,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N293_1_10 ( - .COUT (_N15913), + .COUT (_N15843), .Z (N293[10]), - .CIN (_N15912), + .CIN (_N15842), .I0 (), .I1 (wr3_cnt_num[10]), .I2 (), @@ -232352,9 +232078,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N293_1_11 ( - .COUT (_N15914), + .COUT (_N15844), .Z (N293[11]), - .CIN (_N15913), + .CIN (_N15843), .I0 (), .I1 (wr3_cnt_num[11]), .I2 (), @@ -232372,9 +232098,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N293_1_12 ( - .COUT (_N15915), + .COUT (_N15845), .Z (N293[12]), - .CIN (_N15914), + .CIN (_N15844), .I0 (), .I1 (wr3_cnt_num[12]), .I2 (), @@ -232392,9 +232118,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N293_1_13 ( - .COUT (_N15916), + .COUT (_N15846), .Z (N293[13]), - .CIN (_N15915), + .CIN (_N15845), .I0 (), .I1 (wr3_cnt_num[13]), .I2 (), @@ -232412,9 +232138,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N293_1_14 ( - .COUT (_N15917), + .COUT (_N15847), .Z (N293[14]), - .CIN (_N15916), + .CIN (_N15846), .I0 (), .I1 (wr3_cnt_num[14]), .I2 (), @@ -232434,7 +232160,7 @@ module axi_wr_connect N293_1_15 ( .COUT (), .Z (N293[15]), - .CIN (_N15917), + .CIN (_N15847), .I0 (), .I1 (wr3_cnt_num[15]), .I2 (), @@ -232448,7 +232174,7 @@ module axi_wr_connect GTP_LUT5 /* N294_8 */ #( .INIT(32'b00000000000000000000000000000001)) N294_8 ( - .Z (_N103655), + .Z (_N104472), .I0 (wr3_cnt_num[6]), .I1 (wr3_cnt_num[7]), .I2 (wr3_cnt_num[8]), @@ -232459,7 +232185,7 @@ module axi_wr_connect GTP_LUT5 /* N294_12 */ #( .INIT(32'b00000000000000000000000010000000)) N294_12 ( - .Z (_N103659), + .Z (_N104476), .I0 (wr3_cnt_num[5]), .I1 (wr3_cnt_num[10]), .I2 (wr3_cnt_num[11]), @@ -232470,7 +232196,7 @@ module axi_wr_connect GTP_LUT2 /* N294_13 */ #( .INIT(4'b0100)) N294_13 ( - .Z (_N103660), + .Z (_N104477), .I0 (wr3_cnt_num[0]), .I1 (wr3_cnt_num[12])); // LUT = ~I0&I1 ; @@ -232478,18 +232204,18 @@ module axi_wr_connect GTP_LUT5 /* N294_14 */ #( .INIT(32'b00000000000000010000000000000000)) N294_14 ( - .Z (_N103661), + .Z (_N104478), .I0 (wr3_cnt_num[1]), .I1 (wr3_cnt_num[2]), .I2 (wr3_cnt_num[3]), .I3 (wr3_cnt_num[4]), - .I4 (_N103660)); + .I4 (_N104477)); // LUT = ~I0&~I1&~I2&~I3&I4 ; GTP_LUT1 /* N294_eq0_inv */ #( .INIT(2'b01)) N294_eq0_inv ( - .Z (_N8699_inv), + .Z (_N8733_inv), .I0 (wr3_cnt_num[0])); // LUT = ~I0 ; @@ -232498,9 +232224,9 @@ module axi_wr_connect N301_vname ( .Z (N301), .I0 (rx0_addr_valid), - .I1 (_N103693), - .I2 (_N103697), - .I3 (_N103699)); + .I1 (_N104512), + .I2 (_N104516), + .I3 (_N104518)); // defparam N301_vname.orig_name = N301; // LUT = I0&I1&I2&I3 ; // ../../sources/designs/ddr/rd_wr_ctrl/axi_wr_connect.v:481 @@ -232510,9 +232236,9 @@ module axi_wr_connect N315_vname ( .Z (N315), .I0 (rx1_addr_valid), - .I1 (_N103941), - .I2 (_N103945), - .I3 (_N103947)); + .I1 (_N104765), + .I2 (_N104769), + .I3 (_N104771)); // defparam N315_vname.orig_name = N315; // LUT = I0&I1&I2&I3 ; // ../../sources/designs/ddr/rd_wr_ctrl/axi_wr_connect.v:484 @@ -232522,13 +232248,31 @@ module axi_wr_connect N343_vname ( .Z (N343), .I0 (rx3_addr_valid), - .I1 (_N103655), - .I2 (_N103659), - .I3 (_N103661)); + .I1 (_N104472), + .I2 (_N104476), + .I3 (_N104478)); // defparam N343_vname.orig_name = N343; // LUT = I0&I1&I2&I3 ; // ../../sources/designs/ddr/rd_wr_ctrl/axi_wr_connect.v:490 + GTP_LUT3 /* N362_mux2_3 */ #( + .INIT(8'b11111110)) + N362_mux2_3 ( + .Z (N362), + .I0 (delay_cnt1[0]), + .I1 (delay_cnt1[1]), + .I2 (delay_cnt1[2])); + // LUT = (I0)|(I1)|(I2) ; + + GTP_LUT3 /* N372_mux2_3 */ #( + .INIT(8'b11111110)) + N372_mux2_3 ( + .Z (N372), + .I0 (delay_cnt3[0]), + .I1 (delay_cnt3[1]), + .I2 (delay_cnt3[2])); + // LUT = (I0)|(I1)|(I2) ; + GTP_LUT2 /* N376 */ #( .INIT(4'b0100)) N376 ( @@ -232563,7 +232307,7 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N429_1_1 ( - .COUT (_N13627), + .COUT (_N13606), .Z (N429[1]), .CIN (), .I0 (cnt_times[0]), @@ -232583,9 +232327,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N429_1_2 ( - .COUT (_N13628), + .COUT (_N13607), .Z (N429[2]), - .CIN (_N13627), + .CIN (_N13606), .I0 (cnt_times[0]), .I1 (cnt_times[1]), .I2 (cnt_times[2]), @@ -232603,9 +232347,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N429_1_3 ( - .COUT (_N13629), + .COUT (_N13608), .Z (N429[3]), - .CIN (_N13628), + .CIN (_N13607), .I0 (), .I1 (cnt_times[3]), .I2 (), @@ -232623,9 +232367,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N429_1_4 ( - .COUT (_N13630), + .COUT (_N13609), .Z (N429[4]), - .CIN (_N13629), + .CIN (_N13608), .I0 (), .I1 (cnt_times[4]), .I2 (), @@ -232643,9 +232387,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N429_1_5 ( - .COUT (_N13631), + .COUT (_N13610), .Z (N429[5]), - .CIN (_N13630), + .CIN (_N13609), .I0 (), .I1 (cnt_times[5]), .I2 (), @@ -232665,7 +232409,7 @@ module axi_wr_connect N429_1_6 ( .COUT (), .Z (N429[6]), - .CIN (_N13631), + .CIN (_N13610), .I0 (), .I1 (cnt_times[6]), .I2 (), @@ -232679,7 +232423,7 @@ module axi_wr_connect GTP_LUT4 /* N448_6 */ #( .INIT(16'b1000000000000000)) N448_6 ( - .Z (_N104099), + .Z (_N104928), .I0 (cnt_times[1]), .I1 (cnt_times[2]), .I2 (cnt_times[3]), @@ -232693,13 +232437,13 @@ module axi_wr_connect .I0 (cnt_times[0]), .I1 (cnt_times[5]), .I2 (cnt_times[6]), - .I3 (_N104099)); + .I3 (_N104928)); // LUT = I0&~I1&~I2&I3 ; GTP_LUT5 /* N469_4 */ #( .INIT(32'b00000000000000000000000000000001)) N469_4 ( - .Z (_N97193), + .Z (_N97954), .I0 (rd_sta0[0]), .I1 (rd_sta0[2]), .I2 (rd_sta0[3]), @@ -232710,7 +232454,7 @@ module axi_wr_connect GTP_LUT4 /* N469_8 */ #( .INIT(16'b0000000000000001)) N469_8 ( - .Z (_N97111), + .Z (_N97877), .I0 (rd_sta0[0]), .I1 (rd_sta0[2]), .I2 (rd_sta0[4]), @@ -232724,7 +232468,7 @@ module axi_wr_connect .I0 (rd_sta0[1]), .I1 (rd_sta0[3]), .I2 (rd_sta0[7]), - .I3 (_N97111)); + .I3 (_N97877)); // LUT = ~I0&I1&~I2&I3 ; GTP_LUT3 /* N473_3 */ #( @@ -232733,36 +232477,18 @@ module axi_wr_connect .Z (N473), .I0 (rd_sta0[1]), .I1 (rd_sta0[7]), - .I2 (_N97193)); + .I2 (_N97954)); // LUT = ~I0&I1&I2 ; - GTP_LUT3 /* N481_1 */ #( + GTP_LUT3 /* N481_3 */ #( .INIT(8'b11111110)) - N481_1 ( + N481_3 ( .Z (N357), .I0 (delay_cnt0[0]), .I1 (delay_cnt0[1]), .I2 (delay_cnt0[2])); // LUT = (I0)|(I1)|(I2) ; - GTP_LUT3 /* N485_1 */ #( - .INIT(8'b11111110)) - N485_1 ( - .Z (N362), - .I0 (delay_cnt1[0]), - .I1 (delay_cnt1[1]), - .I2 (delay_cnt1[2])); - // LUT = (I0)|(I1)|(I2) ; - - GTP_LUT3 /* N493_1 */ #( - .INIT(8'b11111110)) - N493_1 ( - .Z (N372), - .I0 (delay_cnt3[0]), - .I1 (delay_cnt3[1]), - .I2 (delay_cnt3[2])); - // LUT = (I0)|(I1)|(I2) ; - GTP_LUT4 /* N565 */ #( .INIT(16'b0100000000000000)) N565 ( @@ -232801,7 +232527,7 @@ module axi_wr_connect .I4_TO_CARRY("FALSE"), .I4_TO_LUT("FALSE")) N574_4_0 ( - .COUT (_N15941), + .COUT (_N15872), .Z (), .CIN (), .I0 (), @@ -232820,12 +232546,12 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N574_4_1 ( - .COUT (_N15942), + .COUT (_N15873), .Z (N574[4]), - .CIN (_N15941), + .CIN (_N15872), .I0 (), .I1 (nb1[4]), - .I2 (_N25394), + .I2 (_N25244), .I3 (wr1_cnt_num[4]), .I4 (nb1[4]), .ID ()); @@ -232839,11 +232565,11 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N574_4_2 ( - .COUT (_N15943), + .COUT (_N15874), .Z (N574[5]), - .CIN (_N15942), + .CIN (_N15873), .I0 (), - .I1 (_N25395), + .I1 (_N25245), .I2 (wr1_cnt_num[5]), .I3 (nb1[4]), .I4 (1'b0), @@ -232858,11 +232584,11 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N574_4_3 ( - .COUT (_N15944), + .COUT (_N15875), .Z (N574[6]), - .CIN (_N15943), + .CIN (_N15874), .I0 (), - .I1 (_N25396), + .I1 (_N25246), .I2 (wr1_cnt_num[6]), .I3 (nb1[4]), .I4 (1'b0), @@ -232877,11 +232603,11 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N574_4_4 ( - .COUT (_N15945), + .COUT (_N15876), .Z (N574[7]), - .CIN (_N15944), + .CIN (_N15875), .I0 (), - .I1 (_N25397), + .I1 (_N25247), .I2 (wr1_cnt_num[7]), .I3 (nb1[4]), .I4 (1'b0), @@ -232896,11 +232622,11 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N574_4_5 ( - .COUT (_N15946), + .COUT (_N15877), .Z (N574[8]), - .CIN (_N15945), + .CIN (_N15876), .I0 (), - .I1 (_N25398), + .I1 (_N25248), .I2 (wr1_cnt_num[8]), .I3 (nb1[4]), .I4 (1'b0), @@ -232915,12 +232641,12 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N574_4_6 ( - .COUT (_N15947), + .COUT (_N15878), .Z (N574[9]), - .CIN (_N15946), + .CIN (_N15877), .I0 (), .I1 (nb1[4]), - .I2 (_N25399), + .I2 (_N25249), .I3 (wr1_cnt_num[9]), .I4 (nb1[4]), .ID ()); @@ -232934,12 +232660,12 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N574_4_7 ( - .COUT (_N15948), + .COUT (_N15879), .Z (N574[10]), - .CIN (_N15947), + .CIN (_N15878), .I0 (), .I1 (nb1[4]), - .I2 (_N25400), + .I2 (_N25250), .I3 (wr1_cnt_num[10]), .I4 (nb1[4]), .ID ()); @@ -232953,12 +232679,12 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N574_4_8 ( - .COUT (_N15949), + .COUT (_N15880), .Z (N574[11]), - .CIN (_N15948), + .CIN (_N15879), .I0 (), .I1 (nb1[4]), - .I2 (_N25401), + .I2 (_N25251), .I3 (wr1_cnt_num[11]), .I4 (nb1[4]), .ID ()); @@ -232972,11 +232698,11 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N574_4_9 ( - .COUT (_N15950), + .COUT (_N15881), .Z (N574[12]), - .CIN (_N15949), + .CIN (_N15880), .I0 (), - .I1 (_N25402), + .I1 (_N25252), .I2 (wr1_cnt_num[12]), .I3 (nb1[4]), .I4 (1'b0), @@ -232991,9 +232717,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N574_4_10 ( - .COUT (_N15951), + .COUT (_N15882), .Z (N574[13]), - .CIN (_N15950), + .CIN (_N15881), .I0 (), .I1 (nb1[13]), .I2 (nb0[13]), @@ -233010,9 +232736,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N574_4_11 ( - .COUT (_N15952), + .COUT (_N15883), .Z (N574[14]), - .CIN (_N15951), + .CIN (_N15882), .I0 (), .I1 (nb1[14]), .I2 (nb0[14]), @@ -233029,9 +232755,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N574_4_12 ( - .COUT (_N15953), + .COUT (_N15884), .Z (N574[15]), - .CIN (_N15952), + .CIN (_N15883), .I0 (), .I1 (nb1[15]), .I2 (nb0[15]), @@ -233048,11 +232774,11 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N574_4_13 ( - .COUT (_N15954), + .COUT (_N15885), .Z (N574[16]), - .CIN (_N15953), + .CIN (_N15884), .I0 (), - .I1 (_N25410), + .I1 (_N25260), .I2 (wr1_ddr_sart_addr2[16]), .I3 (nb1[4]), .I4 (1'b0), @@ -233067,11 +232793,11 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N574_4_14 ( - .COUT (_N15955), + .COUT (_N15886), .Z (N574[17]), - .CIN (_N15954), + .CIN (_N15885), .I0 (), - .I1 (_N25411), + .I1 (_N25261), .I2 (wr1_ddr_sart_addr2[17]), .I3 (nb1[4]), .I4 (1'b0), @@ -233086,9 +232812,9 @@ module axi_wr_connect .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N574_4_15 ( - .COUT (_N15956), + .COUT (_N15887), .Z (N574[18]), - .CIN (_N15955), + .CIN (_N15886), .I0 (), .I1 (N244), .I2 (N259), @@ -233107,7 +232833,7 @@ module axi_wr_connect N574_4_16 ( .COUT (), .Z (N574[19]), - .CIN (_N15956), + .CIN (_N15887), .I0 (), .I1 (), .I2 (), @@ -233129,7 +232855,7 @@ module axi_wr_connect GTP_LUT3 /* \N574_9[4] */ #( .INIT(8'b11001010)) \N574_9[4] ( - .Z (_N25394), + .Z (_N25244), .I0 (wr0_cnt_num[4]), .I1 (wr3_cnt_num[4]), .I2 (nb1[18])); @@ -233138,7 +232864,7 @@ module axi_wr_connect GTP_LUT3 /* \N574_9[5] */ #( .INIT(8'b11001010)) \N574_9[5] ( - .Z (_N25395), + .Z (_N25245), .I0 (wr0_cnt_num[5]), .I1 (wr3_cnt_num[5]), .I2 (nb1[18])); @@ -233147,7 +232873,7 @@ module axi_wr_connect GTP_LUT3 /* \N574_9[6] */ #( .INIT(8'b11001010)) \N574_9[6] ( - .Z (_N25396), + .Z (_N25246), .I0 (wr0_cnt_num[6]), .I1 (wr3_cnt_num[6]), .I2 (nb1[18])); @@ -233156,7 +232882,7 @@ module axi_wr_connect GTP_LUT3 /* \N574_9[7] */ #( .INIT(8'b11001010)) \N574_9[7] ( - .Z (_N25397), + .Z (_N25247), .I0 (wr0_cnt_num[7]), .I1 (wr3_cnt_num[7]), .I2 (nb1[18])); @@ -233165,7 +232891,7 @@ module axi_wr_connect GTP_LUT3 /* \N574_9[8] */ #( .INIT(8'b11001010)) \N574_9[8] ( - .Z (_N25398), + .Z (_N25248), .I0 (wr0_cnt_num[8]), .I1 (wr3_cnt_num[8]), .I2 (nb1[18])); @@ -233174,7 +232900,7 @@ module axi_wr_connect GTP_LUT3 /* \N574_9[9] */ #( .INIT(8'b11001010)) \N574_9[9] ( - .Z (_N25399), + .Z (_N25249), .I0 (wr0_cnt_num[9]), .I1 (wr3_cnt_num[9]), .I2 (nb1[18])); @@ -233183,7 +232909,7 @@ module axi_wr_connect GTP_LUT3 /* \N574_9[10] */ #( .INIT(8'b11001010)) \N574_9[10] ( - .Z (_N25400), + .Z (_N25250), .I0 (wr0_cnt_num[10]), .I1 (wr3_cnt_num[10]), .I2 (nb1[18])); @@ -233192,7 +232918,7 @@ module axi_wr_connect GTP_LUT3 /* \N574_9[11] */ #( .INIT(8'b11001010)) \N574_9[11] ( - .Z (_N25401), + .Z (_N25251), .I0 (wr0_cnt_num[11]), .I1 (wr3_cnt_num[11]), .I2 (nb1[18])); @@ -233201,7 +232927,7 @@ module axi_wr_connect GTP_LUT3 /* \N574_9[12] */ #( .INIT(8'b11001010)) \N574_9[12] ( - .Z (_N25402), + .Z (_N25252), .I0 (wr0_cnt_num[12]), .I1 (wr3_cnt_num[12]), .I2 (nb1[18])); @@ -233210,7 +232936,7 @@ module axi_wr_connect GTP_LUT2 /* \N574_9[19] */ #( .INIT(4'b0010)) \N574_9[19] ( - .Z (_N25410), + .Z (_N25260), .I0 (wr0_ddr_sart_addr2[16]), .I1 (nb1[18])); // LUT = I0&~I1 ; @@ -233218,7 +232944,7 @@ module axi_wr_connect GTP_LUT2 /* \N574_9[20] */ #( .INIT(4'b1110)) \N574_9[20] ( - .Z (_N25411), + .Z (_N25261), .I0 (wr0_ddr_sart_addr2[17]), .I1 (nb1[18])); // LUT = (I0)|(I1) ; @@ -234074,9 +233800,9 @@ module axi_wr_connect .Z (N592), .I0 (rst), .I1 (N244), - .I2 (_N103693), - .I3 (_N103697), - .I4 (_N103699)); + .I2 (_N104512), + .I3 (_N104516), + .I4 (_N104518)); // defparam N592_vname.orig_name = N592; // LUT = (I0)|(~I1&I2&I3&I4) ; // ../../sources/designs/ddr/rd_wr_ctrl/axi_wr_connect.v:284 @@ -234087,9 +233813,9 @@ module axi_wr_connect .Z (N598), .I0 (rst), .I1 (N259), - .I2 (_N103941), - .I3 (_N103945), - .I4 (_N103947)); + .I2 (_N104765), + .I3 (_N104769), + .I4 (_N104771)); // defparam N598_vname.orig_name = N598; // LUT = (I0)|(~I1&I2&I3&I4) ; // ../../sources/designs/ddr/rd_wr_ctrl/axi_wr_connect.v:285 @@ -234100,9 +233826,9 @@ module axi_wr_connect .Z (N610), .I0 (rst), .I1 (N289), - .I2 (_N103655), - .I3 (_N103659), - .I4 (_N103661)); + .I2 (_N104472), + .I3 (_N104476), + .I4 (_N104478)); // defparam N610_vname.orig_name = N610; // LUT = (I0)|(~I1&I2&I3&I4) ; // ../../sources/designs/ddr/rd_wr_ctrl/axi_wr_connect.v:287 @@ -234313,16 +234039,16 @@ module axi_wr_connect axi_addr_valid0 ( .Q (axi_addr_valid), .CLK (clk), - .D (_N103323)); + .D (_N104135)); // ../../sources/designs/ddr/rd_wr_ctrl/axi_wr_connect.v:361 GTP_LUT5 /* axi_addr_valid0_ce_mux */ #( .INIT(32'b10111011100010001011100010111000)) axi_addr_valid0_ce_mux ( - .Z (_N103323), + .Z (_N104135), .I0 (axi_addr_valid), .I1 (rst), - .I2 (_N22101), + .I2 (_N22037), .I3 (N258), .I4 (rd_sta[2])); // LUT = (I0&I1)|(~I1&I2&~I4)|(~I1&I3&I4) ; @@ -235611,14 +235337,14 @@ module axi_wr_connect rx0_addr_valid_vname ( .Q (rx0_addr_valid), .CLK (clk), - .D (_N103538)); + .D (_N104350)); // defparam rx0_addr_valid_vname.orig_name = rx0_addr_valid; // ../../sources/designs/ddr/rd_wr_ctrl/axi_wr_connect.v:581 GTP_LUT4 /* rx0_addr_valid_rs_mux */ #( .INIT(16'b0100010001010100)) rx0_addr_valid_rs_mux ( - .Z (_N103538), + .Z (_N104350), .I0 (rst), .I1 (ddr0_valid_fall2), .I2 (rx0_addr_valid), @@ -235631,14 +235357,14 @@ module axi_wr_connect rx1_addr_valid_vname ( .Q (rx1_addr_valid), .CLK (clk), - .D (_N103540)); + .D (_N104352)); // defparam rx1_addr_valid_vname.orig_name = rx1_addr_valid; // ../../sources/designs/ddr/rd_wr_ctrl/axi_wr_connect.v:581 GTP_LUT4 /* rx1_addr_valid_rs_mux */ #( .INIT(16'b0100010001010100)) rx1_addr_valid_rs_mux ( - .Z (_N103540), + .Z (_N104352), .I0 (rst), .I1 (ddr1_valid_fall2), .I2 (rx1_addr_valid), @@ -235651,14 +235377,14 @@ module axi_wr_connect rx3_addr_valid_vname ( .Q (rx3_addr_valid), .CLK (clk), - .D (_N103542)); + .D (_N104354)); // defparam rx3_addr_valid_vname.orig_name = rx3_addr_valid; // ../../sources/designs/ddr/rd_wr_ctrl/axi_wr_connect.v:581 GTP_LUT4 /* rx3_addr_valid_rs_mux */ #( .INIT(16'b0100010001010100)) rx3_addr_valid_rs_mux ( - .Z (_N103542), + .Z (_N104354), .I0 (rst), .I1 (ddr3_valid_fall2), .I2 (rx3_addr_valid), @@ -235672,7 +235398,7 @@ module axi_wr_connect .Q (wr0_cnt_num[0]), .CE (N244), .CLK (clk), - .D (_N8651_inv), + .D (_N8685_inv), .R (N592)); // ../../sources/designs/ddr/rd_wr_ctrl/axi_wr_connect.v:448 @@ -236037,7 +235763,7 @@ module axi_wr_connect .Q (wr1_cnt_num[0]), .CE (N259), .CLK (clk), - .D (_N8667_inv), + .D (_N8701_inv), .R (N598)); // ../../sources/designs/ddr/rd_wr_ctrl/axi_wr_connect.v:448 @@ -236402,7 +236128,7 @@ module axi_wr_connect .Q (wr3_cnt_num[0]), .CE (N289), .CLK (clk), - .D (_N8699_inv), + .D (_N8733_inv), .R (N610)); // ../../sources/designs/ddr/rd_wr_ctrl/axi_wr_connect.v:448 @@ -236727,28 +236453,28 @@ module ipml_fifo_ctrl_v1_3_12 wire N168; wire N170; wire [12:0] \N170.co ; - wire _N15700; - wire _N15701; - wire _N15702; - wire _N15703; - wire _N15704; - wire _N15705; - wire _N15706; - wire _N15707; - wire _N15708; - wire _N15709; - wire _N15710; - wire _N15713; - wire _N15714; - wire _N15715; - wire _N15716; - wire _N15717; - wire _N15718; - wire _N15719; - wire _N15720; - wire _N15721; - wire _N15722; - wire _N15723; + wire _N15638; + wire _N15639; + wire _N15640; + wire _N15641; + wire _N15642; + wire _N15643; + wire _N15644; + wire _N15645; + wire _N15646; + wire _N15647; + wire _N15648; + wire _N15651; + wire _N15652; + wire _N15653; + wire _N15654; + wire _N15655; + wire _N15656; + wire _N15657; + wire _N15658; + wire _N15659; + wire _N15660; + wire _N15661; wire [11:0] rbin; wire rempty; wire [11:0] rgnext; @@ -237542,7 +237268,7 @@ module ipml_fifo_ctrl_v1_3_12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_1 ( - .COUT (_N15700), + .COUT (_N15638), .Z (N2[0]), .CIN (), .I0 (w_en), @@ -237562,9 +237288,9 @@ module ipml_fifo_ctrl_v1_3_12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_2 ( - .COUT (_N15701), + .COUT (_N15639), .Z (N2[1]), - .CIN (_N15700), + .CIN (_N15638), .I0 (w_en), .I1 (waddr[0]), .I2 (waddr[1]), @@ -237582,9 +237308,9 @@ module ipml_fifo_ctrl_v1_3_12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_3 ( - .COUT (_N15702), + .COUT (_N15640), .Z (N2[2]), - .CIN (_N15701), + .CIN (_N15639), .I0 (), .I1 (waddr[2]), .I2 (), @@ -237602,9 +237328,9 @@ module ipml_fifo_ctrl_v1_3_12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_4 ( - .COUT (_N15703), + .COUT (_N15641), .Z (N2[3]), - .CIN (_N15702), + .CIN (_N15640), .I0 (), .I1 (waddr[3]), .I2 (), @@ -237622,9 +237348,9 @@ module ipml_fifo_ctrl_v1_3_12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_5 ( - .COUT (_N15704), + .COUT (_N15642), .Z (N2[4]), - .CIN (_N15703), + .CIN (_N15641), .I0 (), .I1 (waddr[4]), .I2 (), @@ -237642,9 +237368,9 @@ module ipml_fifo_ctrl_v1_3_12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_6 ( - .COUT (_N15705), + .COUT (_N15643), .Z (N2[5]), - .CIN (_N15704), + .CIN (_N15642), .I0 (), .I1 (waddr[5]), .I2 (), @@ -237662,9 +237388,9 @@ module ipml_fifo_ctrl_v1_3_12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_7 ( - .COUT (_N15706), + .COUT (_N15644), .Z (N2[6]), - .CIN (_N15705), + .CIN (_N15643), .I0 (), .I1 (waddr[6]), .I2 (), @@ -237682,9 +237408,9 @@ module ipml_fifo_ctrl_v1_3_12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_8 ( - .COUT (_N15707), + .COUT (_N15645), .Z (N2[7]), - .CIN (_N15706), + .CIN (_N15644), .I0 (), .I1 (waddr[7]), .I2 (), @@ -237702,9 +237428,9 @@ module ipml_fifo_ctrl_v1_3_12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_9 ( - .COUT (_N15708), + .COUT (_N15646), .Z (N2[8]), - .CIN (_N15707), + .CIN (_N15645), .I0 (), .I1 (waddr[8]), .I2 (), @@ -237722,9 +237448,9 @@ module ipml_fifo_ctrl_v1_3_12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_10 ( - .COUT (_N15709), + .COUT (_N15647), .Z (N2[9]), - .CIN (_N15708), + .CIN (_N15646), .I0 (), .I1 (waddr[9]), .I2 (), @@ -237742,9 +237468,9 @@ module ipml_fifo_ctrl_v1_3_12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_11 ( - .COUT (_N15710), + .COUT (_N15648), .Z (N2[10]), - .CIN (_N15709), + .CIN (_N15647), .I0 (), .I1 (waddr[10]), .I2 (), @@ -237764,7 +237490,7 @@ module ipml_fifo_ctrl_v1_3_12 N2_12 ( .COUT (), .Z (N2[11]), - .CIN (_N15710), + .CIN (_N15648), .I0 (), .I1 (wbin[11]), .I2 (), @@ -238088,7 +237814,7 @@ module ipml_fifo_ctrl_v1_3_12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_1 ( - .COUT (_N15713), + .COUT (_N15651), .Z (N84[0]), .CIN (), .I0 (r_en), @@ -238108,9 +237834,9 @@ module ipml_fifo_ctrl_v1_3_12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_2 ( - .COUT (_N15714), + .COUT (_N15652), .Z (N84[1]), - .CIN (_N15713), + .CIN (_N15651), .I0 (r_en), .I1 (raddr[0]), .I2 (raddr[1]), @@ -238128,9 +237854,9 @@ module ipml_fifo_ctrl_v1_3_12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_3 ( - .COUT (_N15715), + .COUT (_N15653), .Z (N84[2]), - .CIN (_N15714), + .CIN (_N15652), .I0 (), .I1 (raddr[2]), .I2 (), @@ -238148,9 +237874,9 @@ module ipml_fifo_ctrl_v1_3_12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_4 ( - .COUT (_N15716), + .COUT (_N15654), .Z (N84[3]), - .CIN (_N15715), + .CIN (_N15653), .I0 (), .I1 (raddr[3]), .I2 (), @@ -238168,9 +237894,9 @@ module ipml_fifo_ctrl_v1_3_12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_5 ( - .COUT (_N15717), + .COUT (_N15655), .Z (N84[4]), - .CIN (_N15716), + .CIN (_N15654), .I0 (), .I1 (raddr[4]), .I2 (), @@ -238188,9 +237914,9 @@ module ipml_fifo_ctrl_v1_3_12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_6 ( - .COUT (_N15718), + .COUT (_N15656), .Z (N84[5]), - .CIN (_N15717), + .CIN (_N15655), .I0 (), .I1 (raddr[5]), .I2 (), @@ -238208,9 +237934,9 @@ module ipml_fifo_ctrl_v1_3_12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_7 ( - .COUT (_N15719), + .COUT (_N15657), .Z (N84[6]), - .CIN (_N15718), + .CIN (_N15656), .I0 (), .I1 (raddr[6]), .I2 (), @@ -238228,9 +237954,9 @@ module ipml_fifo_ctrl_v1_3_12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_8 ( - .COUT (_N15720), + .COUT (_N15658), .Z (N84[7]), - .CIN (_N15719), + .CIN (_N15657), .I0 (), .I1 (raddr[7]), .I2 (), @@ -238248,9 +237974,9 @@ module ipml_fifo_ctrl_v1_3_12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_9 ( - .COUT (_N15721), + .COUT (_N15659), .Z (N84[8]), - .CIN (_N15720), + .CIN (_N15658), .I0 (), .I1 (raddr[8]), .I2 (), @@ -238268,9 +237994,9 @@ module ipml_fifo_ctrl_v1_3_12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_10 ( - .COUT (_N15722), + .COUT (_N15660), .Z (N84[9]), - .CIN (_N15721), + .CIN (_N15659), .I0 (), .I1 (raddr[9]), .I2 (), @@ -238288,9 +238014,9 @@ module ipml_fifo_ctrl_v1_3_12 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_11 ( - .COUT (_N15723), + .COUT (_N15661), .Z (N84[10]), - .CIN (_N15722), + .CIN (_N15660), .I0 (), .I1 (raddr[10]), .I2 (), @@ -238310,7 +238036,7 @@ module ipml_fifo_ctrl_v1_3_12 N84_12 ( .COUT (), .Z (N84[11]), - .CIN (_N15723), + .CIN (_N15661), .I0 (), .I1 (rbin[11]), .I2 (), @@ -239284,7 +239010,7 @@ module ipml_fifo_ctrl_v1_3_11 output [8:0] raddr, output [8:0] waddr, output [9:0] wr_water_level, - output _N104649, + output _N105484, output rempty ); wire N0_1; @@ -239297,24 +239023,24 @@ module ipml_fifo_ctrl_v1_3_11 wire [10:0] \N150.co ; wire [9:0] N276; wire [10:0] \N276_5.co ; - wire _N14550; - wire _N14551; - wire _N14552; - wire _N14553; - wire _N14554; - wire _N14555; - wire _N14556; - wire _N14557; - wire _N14558; - wire _N14692; - wire _N14693; - wire _N14694; - wire _N14695; - wire _N14696; - wire _N14697; - wire _N14698; - wire _N14699; - wire _N14700; + wire _N14504; + wire _N14505; + wire _N14506; + wire _N14507; + wire _N14508; + wire _N14509; + wire _N14510; + wire _N14511; + wire _N14512; + wire _N14651; + wire _N14652; + wire _N14653; + wire _N14654; + wire _N14655; + wire _N14656; + wire _N14657; + wire _N14658; + wire _N14659; wire [9:0] nb2; wire [9:0] rbin; wire [9:0] rgnext; @@ -239984,7 +239710,7 @@ module ipml_fifo_ctrl_v1_3_11 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_1 ( - .COUT (_N14550), + .COUT (_N14504), .Z (N2[0]), .CIN (), .I0 (w_en), @@ -240004,9 +239730,9 @@ module ipml_fifo_ctrl_v1_3_11 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_2 ( - .COUT (_N14551), + .COUT (_N14505), .Z (N2[1]), - .CIN (_N14550), + .CIN (_N14504), .I0 (w_en), .I1 (waddr[0]), .I2 (waddr[1]), @@ -240024,9 +239750,9 @@ module ipml_fifo_ctrl_v1_3_11 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_3 ( - .COUT (_N14552), + .COUT (_N14506), .Z (N2[2]), - .CIN (_N14551), + .CIN (_N14505), .I0 (), .I1 (waddr[2]), .I2 (), @@ -240044,9 +239770,9 @@ module ipml_fifo_ctrl_v1_3_11 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_4 ( - .COUT (_N14553), + .COUT (_N14507), .Z (N2[3]), - .CIN (_N14552), + .CIN (_N14506), .I0 (), .I1 (waddr[3]), .I2 (), @@ -240064,9 +239790,9 @@ module ipml_fifo_ctrl_v1_3_11 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_5 ( - .COUT (_N14554), + .COUT (_N14508), .Z (N2[4]), - .CIN (_N14553), + .CIN (_N14507), .I0 (), .I1 (waddr[4]), .I2 (), @@ -240084,9 +239810,9 @@ module ipml_fifo_ctrl_v1_3_11 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_6 ( - .COUT (_N14555), + .COUT (_N14509), .Z (N2[5]), - .CIN (_N14554), + .CIN (_N14508), .I0 (), .I1 (waddr[5]), .I2 (), @@ -240104,9 +239830,9 @@ module ipml_fifo_ctrl_v1_3_11 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_7 ( - .COUT (_N14556), + .COUT (_N14510), .Z (N2[6]), - .CIN (_N14555), + .CIN (_N14509), .I0 (), .I1 (waddr[6]), .I2 (), @@ -240124,9 +239850,9 @@ module ipml_fifo_ctrl_v1_3_11 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_8 ( - .COUT (_N14557), + .COUT (_N14511), .Z (N2[7]), - .CIN (_N14556), + .CIN (_N14510), .I0 (), .I1 (waddr[7]), .I2 (), @@ -240144,9 +239870,9 @@ module ipml_fifo_ctrl_v1_3_11 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_9 ( - .COUT (_N14558), + .COUT (_N14512), .Z (N2[8]), - .CIN (_N14557), + .CIN (_N14511), .I0 (), .I1 (waddr[8]), .I2 (), @@ -240166,7 +239892,7 @@ module ipml_fifo_ctrl_v1_3_11 N2_10 ( .COUT (), .Z (N2[9]), - .CIN (_N14558), + .CIN (_N14512), .I0 (), .I1 (wbin[9]), .I2 (), @@ -240452,7 +240178,7 @@ module ipml_fifo_ctrl_v1_3_11 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_1 ( - .COUT (_N14692), + .COUT (_N14651), .Z (N74[0]), .CIN (), .I0 (rempty), @@ -240472,9 +240198,9 @@ module ipml_fifo_ctrl_v1_3_11 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_2 ( - .COUT (_N14693), + .COUT (_N14652), .Z (N74[1]), - .CIN (_N14692), + .CIN (_N14651), .I0 (rempty), .I1 (raddr[0]), .I2 (raddr[1]), @@ -240492,9 +240218,9 @@ module ipml_fifo_ctrl_v1_3_11 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_3 ( - .COUT (_N14694), + .COUT (_N14653), .Z (N74[2]), - .CIN (_N14693), + .CIN (_N14652), .I0 (), .I1 (raddr[2]), .I2 (), @@ -240512,9 +240238,9 @@ module ipml_fifo_ctrl_v1_3_11 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_4 ( - .COUT (_N14695), + .COUT (_N14654), .Z (N74[3]), - .CIN (_N14694), + .CIN (_N14653), .I0 (), .I1 (raddr[3]), .I2 (), @@ -240532,9 +240258,9 @@ module ipml_fifo_ctrl_v1_3_11 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_5 ( - .COUT (_N14696), + .COUT (_N14655), .Z (N74[4]), - .CIN (_N14695), + .CIN (_N14654), .I0 (), .I1 (raddr[4]), .I2 (), @@ -240552,9 +240278,9 @@ module ipml_fifo_ctrl_v1_3_11 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_6 ( - .COUT (_N14697), + .COUT (_N14656), .Z (N74[5]), - .CIN (_N14696), + .CIN (_N14655), .I0 (), .I1 (raddr[5]), .I2 (), @@ -240572,9 +240298,9 @@ module ipml_fifo_ctrl_v1_3_11 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_7 ( - .COUT (_N14698), + .COUT (_N14657), .Z (N74[6]), - .CIN (_N14697), + .CIN (_N14656), .I0 (), .I1 (raddr[6]), .I2 (), @@ -240592,9 +240318,9 @@ module ipml_fifo_ctrl_v1_3_11 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_8 ( - .COUT (_N14699), + .COUT (_N14658), .Z (N74[7]), - .CIN (_N14698), + .CIN (_N14657), .I0 (), .I1 (raddr[7]), .I2 (), @@ -240612,9 +240338,9 @@ module ipml_fifo_ctrl_v1_3_11 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_9 ( - .COUT (_N14700), + .COUT (_N14659), .Z (N74[8]), - .CIN (_N14699), + .CIN (_N14658), .I0 (), .I1 (raddr[8]), .I2 (), @@ -240634,7 +240360,7 @@ module ipml_fifo_ctrl_v1_3_11 N74_10 ( .COUT (), .Z (N74[9]), - .CIN (_N14700), + .CIN (_N14659), .I0 (), .I1 (rbin[9]), .I2 (), @@ -241109,7 +240835,7 @@ module ipml_fifo_ctrl_v1_3_11 GTP_LUT4 /* N154_mux6_6 */ #( .INIT(16'b0111111111111111)) N154_mux6_6 ( - .Z (_N104649), + .Z (_N105484), .I0 (wr_water_level[4]), .I1 (wr_water_level[5]), .I2 (wr_water_level[6]), @@ -241701,7 +241427,7 @@ module ipml_fifo_v1_6_rdata3_fifo input wr_en, output [15:0] rd_data, output [9:0] wr_water_level, - output _N104649, + output _N105484, output rd_empty ); wire [8:0] rd_addr; @@ -241717,7 +241443,7 @@ module ipml_fifo_v1_6_rdata3_fifo .raddr (rd_addr), .waddr (wr_addr), .wr_water_level ({wr_water_level[9], wr_water_level[8], \U_ipml_fifo_ctrl_wr_water_level[7]_floating , \U_ipml_fifo_ctrl_wr_water_level[6]_floating , \U_ipml_fifo_ctrl_wr_water_level[5]_floating , \U_ipml_fifo_ctrl_wr_water_level[4]_floating , wr_water_level[3], wr_water_level[2], \U_ipml_fifo_ctrl_wr_water_level[1]_floating , \U_ipml_fifo_ctrl_wr_water_level[0]_floating }), - ._N104649 (_N104649), + ._N105484 (_N105484), .rempty (rd_empty), .rclk (rd_clk), .rrst (rd_rst), @@ -241752,7 +241478,7 @@ module rdata3_fifo input wr_en, output [15:0] rd_data, output [9:0] wr_water_level, - output _N104649, + output _N105484, output rd_empty ); wire \U_ipml_fifo_rdata3_fifo_wr_water_level[0]_floating ; @@ -241766,7 +241492,7 @@ module rdata3_fifo .rd_data (rd_data), .wr_water_level ({wr_water_level[9], wr_water_level[8], \U_ipml_fifo_rdata3_fifo_wr_water_level[7]_floating , \U_ipml_fifo_rdata3_fifo_wr_water_level[6]_floating , \U_ipml_fifo_rdata3_fifo_wr_water_level[5]_floating , \U_ipml_fifo_rdata3_fifo_wr_water_level[4]_floating , wr_water_level[3], wr_water_level[2], \U_ipml_fifo_rdata3_fifo_wr_water_level[1]_floating , \U_ipml_fifo_rdata3_fifo_wr_water_level[0]_floating }), .wr_data (wr_data), - ._N104649 (_N104649), + ._N105484 (_N105484), .rd_empty (rd_empty), .rd_clk (rd_clk), .rd_rst (rd_rst), @@ -241801,26 +241527,26 @@ module ipml_fifo_ctrl_v1_3_7 wire [10:0] \N25.co ; wire [11:0] N139; wire [10:0] \N139_6.co ; + wire _N15020; + wire _N15021; + wire _N15022; + wire _N15023; + wire _N15024; + wire _N15025; + wire _N15026; + wire _N15027; + wire _N15028; + wire _N15029; + wire _N15030; + wire _N15033; + wire _N15034; + wire _N15035; + wire _N15036; wire _N15037; wire _N15038; wire _N15039; wire _N15040; wire _N15041; - wire _N15042; - wire _N15043; - wire _N15044; - wire _N15045; - wire _N15046; - wire _N15047; - wire _N15050; - wire _N15051; - wire _N15052; - wire _N15053; - wire _N15054; - wire _N15055; - wire _N15056; - wire _N15057; - wire _N15058; wire [11:0] nb2; wire [9:0] rbin; wire [9:0] rrptr; @@ -241840,7 +241566,7 @@ module ipml_fifo_ctrl_v1_3_7 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_1 ( - .COUT (_N15037), + .COUT (_N15020), .Z (N2[0]), .CIN (), .I0 (w_en), @@ -241860,9 +241586,9 @@ module ipml_fifo_ctrl_v1_3_7 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_2 ( - .COUT (_N15038), + .COUT (_N15021), .Z (N2[1]), - .CIN (_N15037), + .CIN (_N15020), .I0 (w_en), .I1 (waddr[0]), .I2 (waddr[1]), @@ -241880,9 +241606,9 @@ module ipml_fifo_ctrl_v1_3_7 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_3 ( - .COUT (_N15039), + .COUT (_N15022), .Z (N2[2]), - .CIN (_N15038), + .CIN (_N15021), .I0 (), .I1 (waddr[2]), .I2 (), @@ -241900,9 +241626,9 @@ module ipml_fifo_ctrl_v1_3_7 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_4 ( - .COUT (_N15040), + .COUT (_N15023), .Z (N2[3]), - .CIN (_N15039), + .CIN (_N15022), .I0 (), .I1 (waddr[3]), .I2 (), @@ -241920,9 +241646,9 @@ module ipml_fifo_ctrl_v1_3_7 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_5 ( - .COUT (_N15041), + .COUT (_N15024), .Z (N2[4]), - .CIN (_N15040), + .CIN (_N15023), .I0 (), .I1 (waddr[4]), .I2 (), @@ -241940,9 +241666,9 @@ module ipml_fifo_ctrl_v1_3_7 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_6 ( - .COUT (_N15042), + .COUT (_N15025), .Z (N2[5]), - .CIN (_N15041), + .CIN (_N15024), .I0 (), .I1 (waddr[5]), .I2 (), @@ -241960,9 +241686,9 @@ module ipml_fifo_ctrl_v1_3_7 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_7 ( - .COUT (_N15043), + .COUT (_N15026), .Z (N2[6]), - .CIN (_N15042), + .CIN (_N15025), .I0 (), .I1 (waddr[6]), .I2 (), @@ -241980,9 +241706,9 @@ module ipml_fifo_ctrl_v1_3_7 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_8 ( - .COUT (_N15044), + .COUT (_N15027), .Z (N2[7]), - .CIN (_N15043), + .CIN (_N15026), .I0 (), .I1 (waddr[7]), .I2 (), @@ -242000,9 +241726,9 @@ module ipml_fifo_ctrl_v1_3_7 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_9 ( - .COUT (_N15045), + .COUT (_N15028), .Z (N2[8]), - .CIN (_N15044), + .CIN (_N15027), .I0 (), .I1 (waddr[8]), .I2 (), @@ -242020,9 +241746,9 @@ module ipml_fifo_ctrl_v1_3_7 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_10 ( - .COUT (_N15046), + .COUT (_N15029), .Z (N2[9]), - .CIN (_N15045), + .CIN (_N15028), .I0 (), .I1 (waddr[9]), .I2 (), @@ -242040,9 +241766,9 @@ module ipml_fifo_ctrl_v1_3_7 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_11 ( - .COUT (_N15047), + .COUT (_N15030), .Z (N2[10]), - .CIN (_N15046), + .CIN (_N15029), .I0 (), .I1 (waddr[10]), .I2 (), @@ -242062,7 +241788,7 @@ module ipml_fifo_ctrl_v1_3_7 N2_12 ( .COUT (), .Z (N2[11]), - .CIN (_N15047), + .CIN (_N15030), .I0 (), .I1 (wbin[11]), .I2 (), @@ -242190,7 +241916,7 @@ module ipml_fifo_ctrl_v1_3_7 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_1 ( - .COUT (_N15050), + .COUT (_N15033), .Z (N11[0]), .CIN (), .I0 (r_en), @@ -242210,9 +241936,9 @@ module ipml_fifo_ctrl_v1_3_7 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_2 ( - .COUT (_N15051), + .COUT (_N15034), .Z (N11[1]), - .CIN (_N15050), + .CIN (_N15033), .I0 (r_en), .I1 (raddr[0]), .I2 (raddr[1]), @@ -242230,9 +241956,9 @@ module ipml_fifo_ctrl_v1_3_7 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_3 ( - .COUT (_N15052), + .COUT (_N15035), .Z (N11[2]), - .CIN (_N15051), + .CIN (_N15034), .I0 (), .I1 (raddr[2]), .I2 (), @@ -242250,9 +241976,9 @@ module ipml_fifo_ctrl_v1_3_7 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_4 ( - .COUT (_N15053), + .COUT (_N15036), .Z (N11[3]), - .CIN (_N15052), + .CIN (_N15035), .I0 (), .I1 (raddr[3]), .I2 (), @@ -242270,9 +241996,9 @@ module ipml_fifo_ctrl_v1_3_7 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_5 ( - .COUT (_N15054), + .COUT (_N15037), .Z (N11[4]), - .CIN (_N15053), + .CIN (_N15036), .I0 (), .I1 (raddr[4]), .I2 (), @@ -242290,9 +242016,9 @@ module ipml_fifo_ctrl_v1_3_7 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_6 ( - .COUT (_N15055), + .COUT (_N15038), .Z (N11[5]), - .CIN (_N15054), + .CIN (_N15037), .I0 (), .I1 (raddr[5]), .I2 (), @@ -242310,9 +242036,9 @@ module ipml_fifo_ctrl_v1_3_7 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_7 ( - .COUT (_N15056), + .COUT (_N15039), .Z (N11[6]), - .CIN (_N15055), + .CIN (_N15038), .I0 (), .I1 (raddr[6]), .I2 (), @@ -242330,9 +242056,9 @@ module ipml_fifo_ctrl_v1_3_7 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_8 ( - .COUT (_N15057), + .COUT (_N15040), .Z (N11[7]), - .CIN (_N15056), + .CIN (_N15039), .I0 (), .I1 (raddr[7]), .I2 (), @@ -242350,9 +242076,9 @@ module ipml_fifo_ctrl_v1_3_7 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_9 ( - .COUT (_N15058), + .COUT (_N15041), .Z (N11[8]), - .CIN (_N15057), + .CIN (_N15040), .I0 (), .I1 (raddr[8]), .I2 (), @@ -242372,7 +242098,7 @@ module ipml_fifo_ctrl_v1_3_7 N11_10 ( .COUT (), .Z (N11[9]), - .CIN (_N15058), + .CIN (_N15041), .I0 (), .I1 (rbin[9]), .I2 (), @@ -244269,14 +243995,14 @@ module axi_ddr_top input \I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N538 , input \I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N538 , input \I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N538 , - input N241_0, - input _N18115, + input N242_0, input axi_rst, input ddr_clk, input ddr_rst, input rd0_addr_start_valid, input rd0_clk, input rd1_addr_start_valid, + input rd1_clk, input rd3_ddr_addr_valid, input \u_axi_rd_connect/N78 , input \u_axi_rd_connect/N78_1 , @@ -244287,8 +244013,6 @@ module axi_ddr_top input wr1_ddr_sart_addr_valid, input wr3_data_in_valid, input wr3_ddr_sart_addr_valid, - output [7:0] \I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt , - output [8:0] \I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg , output [9:0] \I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt , output [7:0] \I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin_div2 , output [9:0] \I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt , @@ -244302,21 +244026,18 @@ module axi_ddr_top output [3:0] mem_dm, output [15:0] rd1_data, output [15:0] rd3_data, - output \I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N137 , - output _N81412_3, - output _N81412_5, - output _N81413_3, - output _N81413_5, - output _N81414_3, - output _N81414_5, - output _N81415_3, - output _N81415_5, - output _N97085, - output _N105268, - output _N105817, - output _N106355, - output _N106490, - output _N106518, + output _N82185_3, + output _N82185_5, + output _N82186_3, + output _N82186_5, + output _N82187_3, + output _N82187_5, + output _N82188_3, + output _N82188_5, + output _N106081, + output _N106639, + output _N107308, + output _N107336, output init_calib_complete, output mem_cas_n, output mem_ck, @@ -244408,16 +244129,7 @@ module axi_ddr_top wire _N50; wire _N51; wire _N52; - wire _N14194; - wire _N14196; - wire _N14197; - wire _N14198; - wire _N14199; - wire _N14200; - wire _N14201; - wire _N14202; wire _N14203; - wire _N14204; wire _N14205; wire _N14206; wire _N14207; @@ -244429,34 +244141,61 @@ module axi_ddr_top wire _N14213; wire _N14214; wire _N14215; - wire _N16122; - wire _N16123; - wire _N16124; - wire _N16125; - wire _N16126; - wire _N16127; - wire _N16128; - wire _N16129; - wire _N16130; - wire _N16131; - wire _N16132; - wire _N16133; - wire _N16134; - wire _N16135; - wire _N16275; - wire _N16276; - wire _N16277; - wire _N16278; - wire _N16279; - wire _N16280; - wire _N16281; - wire _N16282; - wire _N16283; - wire _N16284; - wire _N16285; - wire _N16286; - wire _N16287; - wire _N16288; + wire _N14216; + wire _N14217; + wire _N14218; + wire _N14219; + wire _N14220; + wire _N14221; + wire _N14222; + wire _N14223; + wire _N14224; + wire _N16201; + wire _N16202; + wire _N16203; + wire _N16204; + wire _N16205; + wire _N16206; + wire _N16207; + wire _N16208; + wire _N16209; + wire _N16210; + wire _N16211; + wire _N16212; + wire _N16213; + wire _N16214; + wire _N16217; + wire _N16218; + wire _N16219; + wire _N16220; + wire _N16221; + wire _N16222; + wire _N16223; + wire _N16224; + wire _N16225; + wire _N16226; + wire _N16227; + wire _N16228; + wire _N16229; + wire _N16230; + wire _N21147; + wire _N21148; + wire _N21149; + wire _N21150; + wire _N21151; + wire _N21152; + wire _N21153; + wire _N21154; + wire _N21155; + wire _N21156; + wire _N21157; + wire _N21158; + wire _N21159; + wire _N21160; + wire _N21161; + wire _N21162; + wire _N21195; + wire _N21196; wire _N21197; wire _N21198; wire _N21199; @@ -244473,20 +244212,20 @@ module axi_ddr_top wire _N21210; wire _N21211; wire _N21212; - wire _N21245; - wire _N21246; - wire _N21247; - wire _N21248; - wire _N21249; - wire _N21250; - wire _N21251; - wire _N21252; - wire _N21253; - wire _N21254; - wire _N21255; - wire _N21256; - wire _N21257; - wire _N21258; + wire _N21213; + wire _N21214; + wire _N21215; + wire _N21216; + wire _N21217; + wire _N21218; + wire _N21219; + wire _N21220; + wire _N21221; + wire _N21222; + wire _N21223; + wire _N21224; + wire _N21225; + wire _N21226; wire _N21259; wire _N21260; wire _N21261; @@ -244503,8 +244242,8 @@ module axi_ddr_top wire _N21272; wire _N21273; wire _N21274; - wire _N21275; - wire _N21276; + wire _N21307; + wire _N21308; wire _N21309; wire _N21310; wire _N21311; @@ -244521,75 +244260,57 @@ module axi_ddr_top wire _N21322; wire _N21323; wire _N21324; - wire _N21357; - wire _N21358; - wire _N21359; - wire _N21360; - wire _N21361; - wire _N21362; - wire _N21363; - wire _N21364; - wire _N21365; - wire _N21366; - wire _N21367; - wire _N21368; - wire _N21369; - wire _N21370; - wire _N21371; - wire _N21372; - wire _N21373; - wire _N21374; - wire _N21375; - wire _N21376; - wire _N21377; - wire _N21378; - wire _N21379; - wire _N21380; - wire _N21381; - wire _N21382; - wire _N21383; - wire _N21384; - wire _N21385; - wire _N21386; - wire _N21387; - wire _N21388; - wire _N30074; - wire _N41595; - wire _N96017; - wire _N103324; - wire _N103325; - wire _N103532; - wire _N103534; - wire _N103536; - wire _N104649; - wire _N104653; - wire _N104712; - wire _N104713; - wire _N105152; - wire _N105153; - wire _N105155; - wire _N105157; - wire _N105164; - wire _N105165; - wire _N105174; - wire _N105184; - wire _N105185; - wire _N105194; - wire _N106734; - wire _N108367; - wire _N108368; - wire _N108369; - wire _N108370; - wire _N108371; - wire _N108372; - wire _N108373; - wire _N108374; - wire _N108375; - wire _N108376; - wire _N108377; - wire _N108378; - wire _N108379; - wire _N108380; + wire _N21325; + wire _N21326; + wire _N21327; + wire _N21328; + wire _N21329; + wire _N21330; + wire _N21331; + wire _N21332; + wire _N21333; + wire _N21334; + wire _N21335; + wire _N21336; + wire _N21337; + wire _N21338; + wire _N30044; + wire _N39473; + wire _N96799; + wire _N104136; + wire _N104137; + wire _N104344; + wire _N104346; + wire _N104348; + wire _N105484; + wire _N105488; + wire _N105699; + wire _N105700; + wire _N105702; + wire _N105704; + wire _N105711; + wire _N105712; + wire _N105721; + wire _N105745; + wire _N105746; + wire _N105753; + wire _N105754; + wire _N105763; + wire _N107546; + wire _N109252; + wire _N109253; + wire _N109254; + wire _N109255; + wire _N109256; + wire _N109257; + wire _N109258; + wire _N109259; + wire _N109260; + wire _N109261; + wire _N109262; + wire _N109263; + wire _N109264; + wire _N109265; wire araddr_empty; wire [31:0] araddr_fifo_dout; wire [31:0] awaddr_ddr_fifo_dout; @@ -244678,21 +244399,6 @@ module axi_ddr_top wire [11:0] wr_ddr_count; wire wr_sta_idle; wire [3:0] wr_sta_reg; - wire \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_reset_ctrl/cnt[0]_floating ; - wire \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_reset_ctrl/cnt[1]_floating ; - wire \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_reset_ctrl/cnt[2]_floating ; - wire \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_reset_ctrl/cnt[4]_floating ; - wire \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_reset_ctrl/cnt[5]_floating ; - wire \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_reset_ctrl/cnt[6]_floating ; - wire \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_reset_ctrl/cnt[7]_floating ; - wire \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_reset_ctrl/state_reg[0]_floating ; - wire \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_reset_ctrl/state_reg[1]_floating ; - wire \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_reset_ctrl/state_reg[2]_floating ; - wire \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_reset_ctrl/state_reg[3]_floating ; - wire \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]_floating ; - wire \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_reset_ctrl/state_reg[5]_floating ; - wire \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_reset_ctrl/state_reg[6]_floating ; - wire \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_reset_ctrl/state_reg[8]_floating ; wire \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]_floating ; wire \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[1]_floating ; wire \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[2]_floating ; @@ -244796,8 +244502,6 @@ module axi_ddr_top .mem_a (mem_a), .mem_ba (mem_ba), .mem_dm (mem_dm), - .\u_ddrphy_top/ddrphy_reset_ctrl/cnt ({\I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_reset_ctrl/cnt[7]_floating , \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_reset_ctrl/cnt[6]_floating , \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_reset_ctrl/cnt[5]_floating , \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_reset_ctrl/cnt[4]_floating , \I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt [3] , \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_reset_ctrl/cnt[2]_floating , \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_reset_ctrl/cnt[1]_floating , \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_reset_ctrl/cnt[0]_floating }), - .\u_ddrphy_top/ddrphy_reset_ctrl/state_reg ({\I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_reset_ctrl/state_reg[8]_floating , \I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg [7] , \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_reset_ctrl/state_reg[6]_floating , \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_reset_ctrl/state_reg[5]_floating , \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]_floating , \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_reset_ctrl/state_reg[3]_floating , \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_reset_ctrl/state_reg[2]_floating , \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_reset_ctrl/state_reg[1]_floating , \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_reset_ctrl/state_reg[0]_floating }), .\u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt ({\I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [9] , \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[8]_floating , \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[7]_floating , \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[6]_floating , \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[5]_floating , \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[4]_floating , \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[3]_floating , \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[2]_floating , \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[1]_floating , \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]_floating }), .\u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin_div2 ({\I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin_div2 [7] , \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin_div2[6]_floating , \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin_div2[5]_floating , \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin_div2[4]_floating , \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin_div2[3]_floating , \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin_div2[2]_floating , \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin_div2[1]_floating , \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin_div2[0]_floating }), .\u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt ({\I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [9] , \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[8]_floating , \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[7]_floating , \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[6]_floating , \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[5]_floating , \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[4]_floating , \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[3]_floating , \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[2]_floating , \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[1]_floating , \I_ipsxb_ddr_top_u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]_floating }), @@ -244812,20 +244516,18 @@ module axi_ddr_top .axi_awaddr ({awaddr_ddr_fifo_dout[29], awaddr_ddr_fifo_dout[28], awaddr_ddr_fifo_dout[27], awaddr_ddr_fifo_dout[26], awaddr_ddr_fifo_dout[25], awaddr_ddr_fifo_dout[24], awaddr_ddr_fifo_dout[23], awaddr_ddr_fifo_dout[22], awaddr_ddr_fifo_dout[21], awaddr_ddr_fifo_dout[20], awaddr_ddr_fifo_dout[19], awaddr_ddr_fifo_dout[18], awaddr_ddr_fifo_dout[17], awaddr_ddr_fifo_dout[16], awaddr_ddr_fifo_dout[15], awaddr_ddr_fifo_dout[14], awaddr_ddr_fifo_dout[13], awaddr_ddr_fifo_dout[12], awaddr_ddr_fifo_dout[11], awaddr_ddr_fifo_dout[10], awaddr_ddr_fifo_dout[9], awaddr_ddr_fifo_dout[8], awaddr_ddr_fifo_dout[7], awaddr_ddr_fifo_dout[6], awaddr_ddr_fifo_dout[5], awaddr_ddr_fifo_dout[4], awaddr_ddr_fifo_dout[3], awaddr_ddr_fifo_dout[2]}), .axi_wdata (s_axi_wdata), .\u_axi_ddr_top/rd_sta ({1'bx, rd_sta[7], 1'bx, 1'bx, 1'bx, rd_sta[3], 1'bx, rd_sta[1], 1'bx}), - ._N81412_3 (_N81412_3), - ._N81412_5 (_N81412_5), - ._N81413_3 (_N81413_3), - ._N81413_5 (_N81413_5), - ._N81414_3 (_N81414_3), - ._N81414_5 (_N81414_5), - ._N81415_3 (_N81415_3), - ._N81415_5 (_N81415_5), - ._N97085 (_N97085), - ._N105268 (_N105268), - ._N105817 (_N105817), - ._N106355 (_N106355), - ._N106490 (_N106490), - ._N106518 (_N106518), + ._N82185_3 (_N82185_3), + ._N82185_5 (_N82185_5), + ._N82186_3 (_N82186_3), + ._N82186_5 (_N82186_5), + ._N82187_3 (_N82187_3), + ._N82187_5 (_N82187_5), + ._N82188_3 (_N82188_3), + ._N82188_5 (_N82188_5), + ._N106081 (_N106081), + ._N106639 (_N106639), + ._N107308 (_N107308), + ._N107336 (_N107336), .axi_arready (s_axi_arready), .axi_awready (s_axi_awready), .axi_wready (s_axi_wready), @@ -244841,9 +244543,7 @@ module axi_ddr_top .mem_rst_n (mem_rst_n), .mem_we_n (mem_we_n), .\u_ddrphy_top/calib_done (\I_ipsxb_ddr_top/u_ddrphy_top/calib_done ), - .\u_ddrphy_top/ddrphy_reset_ctrl/N137 (\I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N137 ), .\u_ddrphy_top/read_valid (\I_ipsxb_ddr_top/u_ddrphy_top/read_valid ), - ._N18115 (_N18115), .axi_awvalid (s_axi_awvalid), .ddr_rst (ddr_rst), .ref_clk (ddr_clk), @@ -244866,7 +244566,7 @@ module axi_ddr_top GTP_LUT5 /* N93_mux8_5 */ #( .INIT(32'b00000000000000000000000000011111)) N93_mux8_5 ( - .Z (_N106734), + .Z (_N107546), .I0 (wr_ddr_count[3]), .I1 (wr_ddr_count[4]), .I2 (wr_ddr_count[5]), @@ -244882,7 +244582,7 @@ module axi_ddr_top .I1 (wr_ddr_count[9]), .I2 (wr_ddr_count[10]), .I3 (wr_ddr_count[11]), - .I4 (_N106734)); + .I4 (_N107546)); // LUT = ~I0&~I1&~I2&~I3&I4 ; GTP_LUT5CARRY /* \N104.lt_0 */ #( @@ -245079,7 +244779,7 @@ module axi_ddr_top GTP_LUT4 /* N296_8 */ #( .INIT(16'b0000000010000000)) N296_8 ( - .Z (_N104653), + .Z (_N105488), .I0 (rd_all_full), .I1 (record_araddr_valid), .I2 (wr_sta_idle), @@ -245093,8 +244793,8 @@ module axi_ddr_top .I0 (\u_rdata3_fifo/wr_water_level [2] ), .I1 (\u_rdata3_fifo/wr_water_level [3] ), .I2 (\u_rdata3_fifo/wr_water_level [8] ), - .I3 (_N104649), - .I4 (_N104653)); + .I3 (_N105484), + .I4 (_N105488)); // LUT = (~I2&I4)|(~I1&I4)|(~I0&I4)|(I3&I4) ; GTP_LUT5CARRY /* N398_1_1 */ #( @@ -245104,7 +244804,7 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N398_1_1 ( - .COUT (_N16122), + .COUT (_N16201), .Z (N398[1]), .CIN (), .I0 (rd0_cnt_num[0]), @@ -245124,9 +244824,9 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N398_1_2 ( - .COUT (_N16123), + .COUT (_N16202), .Z (N398[2]), - .CIN (_N16122), + .CIN (_N16201), .I0 (rd0_cnt_num[0]), .I1 (rd0_cnt_num[1]), .I2 (rd0_cnt_num[2]), @@ -245144,9 +244844,9 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N398_1_3 ( - .COUT (_N16124), + .COUT (_N16203), .Z (N398[3]), - .CIN (_N16123), + .CIN (_N16202), .I0 (), .I1 (rd0_cnt_num[3]), .I2 (), @@ -245164,9 +244864,9 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N398_1_4 ( - .COUT (_N16125), + .COUT (_N16204), .Z (N398[4]), - .CIN (_N16124), + .CIN (_N16203), .I0 (), .I1 (rd0_cnt_num[4]), .I2 (), @@ -245184,9 +244884,9 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N398_1_5 ( - .COUT (_N16126), + .COUT (_N16205), .Z (N398[5]), - .CIN (_N16125), + .CIN (_N16204), .I0 (), .I1 (rd0_cnt_num[5]), .I2 (), @@ -245204,9 +244904,9 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N398_1_6 ( - .COUT (_N16127), + .COUT (_N16206), .Z (N398[6]), - .CIN (_N16126), + .CIN (_N16205), .I0 (), .I1 (rd0_cnt_num[6]), .I2 (), @@ -245224,9 +244924,9 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N398_1_7 ( - .COUT (_N16128), + .COUT (_N16207), .Z (N398[7]), - .CIN (_N16127), + .CIN (_N16206), .I0 (), .I1 (rd0_cnt_num[7]), .I2 (), @@ -245244,9 +244944,9 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N398_1_8 ( - .COUT (_N16129), + .COUT (_N16208), .Z (N398[8]), - .CIN (_N16128), + .CIN (_N16207), .I0 (), .I1 (rd0_cnt_num[8]), .I2 (), @@ -245264,9 +244964,9 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N398_1_9 ( - .COUT (_N16130), + .COUT (_N16209), .Z (N398[9]), - .CIN (_N16129), + .CIN (_N16208), .I0 (), .I1 (rd0_cnt_num[9]), .I2 (), @@ -245284,9 +244984,9 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N398_1_10 ( - .COUT (_N16131), + .COUT (_N16210), .Z (N398[10]), - .CIN (_N16130), + .CIN (_N16209), .I0 (), .I1 (rd0_cnt_num[10]), .I2 (), @@ -245304,9 +245004,9 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N398_1_11 ( - .COUT (_N16132), + .COUT (_N16211), .Z (N398[11]), - .CIN (_N16131), + .CIN (_N16210), .I0 (), .I1 (rd0_cnt_num[11]), .I2 (), @@ -245324,9 +245024,9 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N398_1_12 ( - .COUT (_N16133), + .COUT (_N16212), .Z (N398[12]), - .CIN (_N16132), + .CIN (_N16211), .I0 (), .I1 (rd0_cnt_num[12]), .I2 (), @@ -245344,9 +245044,9 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N398_1_13 ( - .COUT (_N16134), + .COUT (_N16213), .Z (N398[13]), - .CIN (_N16133), + .CIN (_N16212), .I0 (), .I1 (rd0_cnt_num[13]), .I2 (), @@ -245364,9 +245064,9 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N398_1_14 ( - .COUT (_N16135), + .COUT (_N16214), .Z (N398[14]), - .CIN (_N16134), + .CIN (_N16213), .I0 (), .I1 (rd0_cnt_num[14]), .I2 (), @@ -245386,7 +245086,7 @@ module axi_ddr_top N398_1_15 ( .COUT (), .Z (N398[15]), - .CIN (_N16135), + .CIN (_N16214), .I0 (), .I1 (rd0_cnt_num[15]), .I2 (), @@ -245400,7 +245100,7 @@ module axi_ddr_top GTP_LUT3 /* N400_mux15_5 */ #( .INIT(8'b11111110)) N400_mux15_5 ( - .Z (_N104712), + .Z (_N105745), .I0 (rd0_cnt_num[9]), .I1 (rd0_cnt_num[10]), .I2 (rd0_cnt_num[15])); @@ -245409,7 +245109,7 @@ module axi_ddr_top GTP_LUT4 /* N400_mux15_6 */ #( .INIT(16'b1111111111111110)) N400_mux15_6 ( - .Z (_N104713), + .Z (_N105746), .I0 (rd0_cnt_num[11]), .I1 (rd0_cnt_num[12]), .I2 (rd0_cnt_num[13]), @@ -245423,7 +245123,7 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N410_1_1 ( - .COUT (_N16275), + .COUT (_N16217), .Z (N410[1]), .CIN (), .I0 (rd1_cnt_num[0]), @@ -245443,9 +245143,9 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N410_1_2 ( - .COUT (_N16276), + .COUT (_N16218), .Z (N410[2]), - .CIN (_N16275), + .CIN (_N16217), .I0 (rd1_cnt_num[0]), .I1 (rd1_cnt_num[1]), .I2 (rd1_cnt_num[2]), @@ -245463,9 +245163,9 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N410_1_3 ( - .COUT (_N16277), + .COUT (_N16219), .Z (N410[3]), - .CIN (_N16276), + .CIN (_N16218), .I0 (), .I1 (rd1_cnt_num[3]), .I2 (), @@ -245483,9 +245183,9 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N410_1_4 ( - .COUT (_N16278), + .COUT (_N16220), .Z (N410[4]), - .CIN (_N16277), + .CIN (_N16219), .I0 (), .I1 (rd1_cnt_num[4]), .I2 (), @@ -245503,9 +245203,9 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N410_1_5 ( - .COUT (_N16279), + .COUT (_N16221), .Z (N410[5]), - .CIN (_N16278), + .CIN (_N16220), .I0 (), .I1 (rd1_cnt_num[5]), .I2 (), @@ -245523,9 +245223,9 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N410_1_6 ( - .COUT (_N16280), + .COUT (_N16222), .Z (N410[6]), - .CIN (_N16279), + .CIN (_N16221), .I0 (), .I1 (rd1_cnt_num[6]), .I2 (), @@ -245543,9 +245243,9 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N410_1_7 ( - .COUT (_N16281), + .COUT (_N16223), .Z (N410[7]), - .CIN (_N16280), + .CIN (_N16222), .I0 (), .I1 (rd1_cnt_num[7]), .I2 (), @@ -245563,9 +245263,9 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N410_1_8 ( - .COUT (_N16282), + .COUT (_N16224), .Z (N410[8]), - .CIN (_N16281), + .CIN (_N16223), .I0 (), .I1 (rd1_cnt_num[8]), .I2 (), @@ -245583,9 +245283,9 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N410_1_9 ( - .COUT (_N16283), + .COUT (_N16225), .Z (N410[9]), - .CIN (_N16282), + .CIN (_N16224), .I0 (), .I1 (rd1_cnt_num[9]), .I2 (), @@ -245603,9 +245303,9 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N410_1_10 ( - .COUT (_N16284), + .COUT (_N16226), .Z (N410[10]), - .CIN (_N16283), + .CIN (_N16225), .I0 (), .I1 (rd1_cnt_num[10]), .I2 (), @@ -245623,9 +245323,9 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N410_1_11 ( - .COUT (_N16285), + .COUT (_N16227), .Z (N410[11]), - .CIN (_N16284), + .CIN (_N16226), .I0 (), .I1 (rd1_cnt_num[11]), .I2 (), @@ -245643,9 +245343,9 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N410_1_12 ( - .COUT (_N16286), + .COUT (_N16228), .Z (N410[12]), - .CIN (_N16285), + .CIN (_N16227), .I0 (), .I1 (rd1_cnt_num[12]), .I2 (), @@ -245663,9 +245363,9 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N410_1_13 ( - .COUT (_N16287), + .COUT (_N16229), .Z (N410[13]), - .CIN (_N16286), + .CIN (_N16228), .I0 (), .I1 (rd1_cnt_num[13]), .I2 (), @@ -245683,9 +245383,9 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N410_1_14 ( - .COUT (_N16288), + .COUT (_N16230), .Z (N410[14]), - .CIN (_N16287), + .CIN (_N16229), .I0 (), .I1 (rd1_cnt_num[14]), .I2 (), @@ -245705,7 +245405,7 @@ module axi_ddr_top N410_1_15 ( .COUT (), .Z (N410[15]), - .CIN (_N16288), + .CIN (_N16230), .I0 (), .I1 (rd1_cnt_num[15]), .I2 (), @@ -245719,7 +245419,7 @@ module axi_ddr_top GTP_LUT2 /* N412_mux15_7 */ #( .INIT(4'b0001)) N412_mux15_7 ( - .Z (_N105152), + .Z (_N105699), .I0 (rd1_cnt_num[14]), .I1 (rd1_cnt_num[15])); // LUT = ~I0&~I1 ; @@ -245727,7 +245427,7 @@ module axi_ddr_top GTP_LUT5 /* N412_mux15_8 */ #( .INIT(32'b00000000000000000000000000011111)) N412_mux15_8 ( - .Z (_N105153), + .Z (_N105700), .I0 (rd1_cnt_num[1]), .I1 (rd1_cnt_num[2]), .I2 (rd1_cnt_num[3]), @@ -245738,7 +245438,7 @@ module axi_ddr_top GTP_LUT4 /* N412_mux15_10 */ #( .INIT(16'b0000000000000001)) N412_mux15_10 ( - .Z (_N105155), + .Z (_N105702), .I0 (rd1_cnt_num[10]), .I1 (rd1_cnt_num[11]), .I2 (rd1_cnt_num[12]), @@ -245748,12 +245448,12 @@ module axi_ddr_top GTP_LUT5 /* N412_mux15_12 */ #( .INIT(32'b00000000000000010000000000000000)) N412_mux15_12 ( - .Z (_N105157), + .Z (_N105704), .I0 (rd1_cnt_num[6]), .I1 (rd1_cnt_num[7]), .I2 (rd1_cnt_num[8]), .I3 (rd1_cnt_num[9]), - .I4 (_N105155)); + .I4 (_N105702)); // LUT = ~I0&~I1&~I2&~I3&I4 ; GTP_LUT2 /* N434 */ #( @@ -245819,7 +245519,7 @@ module axi_ddr_top .I1 (rd0_cnt_num[9]), .I2 (rd0_cnt_num[10]), .I3 (rd0_cnt_num[15]), - .I4 (_N104713)); + .I4 (_N105746)); // defparam N461_vname.orig_name = N461; // LUT = (I0&I1)|(I0&I2)|(I0&I3)|(I0&I4) ; // ../../sources/designs/ddr/rd_wr_ctrl/axi_ddr_top.v:802 @@ -245831,8 +245531,8 @@ module axi_ddr_top .I0 (rx_rd1_addr_valid), .I1 (rd1_cnt_num[14]), .I2 (rd1_cnt_num[15]), - .I3 (_N105153), - .I4 (_N105157)); + .I3 (_N105700), + .I4 (_N105704)); // defparam N465_vname.orig_name = N465; // LUT = (I0&~I4)|(I0&~I3)|(I0&I1)|(I0&I2) ; // ../../sources/designs/ddr/rd_wr_ctrl/axi_ddr_top.v:803 @@ -246251,7 +245951,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_3[0] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_3[0] ( - .Z (_N21197), + .Z (_N21147), .I0 (s_axi_rdata1[176]), .I1 (s_axi_rdata1[240]), .I2 (switch_data0[2]), @@ -246263,7 +245963,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_3[1] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_3[1] ( - .Z (_N21198), + .Z (_N21148), .I0 (s_axi_rdata1[177]), .I1 (s_axi_rdata1[241]), .I2 (switch_data0[2]), @@ -246275,7 +245975,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_3[2] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_3[2] ( - .Z (_N21199), + .Z (_N21149), .I0 (s_axi_rdata1[178]), .I1 (s_axi_rdata1[242]), .I2 (switch_data0[2]), @@ -246287,7 +245987,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_3[3] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_3[3] ( - .Z (_N21200), + .Z (_N21150), .I0 (s_axi_rdata1[179]), .I1 (s_axi_rdata1[243]), .I2 (switch_data0[2]), @@ -246299,7 +245999,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_3[4] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_3[4] ( - .Z (_N21201), + .Z (_N21151), .I0 (s_axi_rdata1[180]), .I1 (s_axi_rdata1[244]), .I2 (switch_data0[2]), @@ -246311,7 +246011,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_3[5] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_3[5] ( - .Z (_N21202), + .Z (_N21152), .I0 (s_axi_rdata1[181]), .I1 (s_axi_rdata1[245]), .I2 (switch_data0[2]), @@ -246323,7 +246023,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_3[6] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_3[6] ( - .Z (_N21203), + .Z (_N21153), .I0 (s_axi_rdata1[182]), .I1 (s_axi_rdata1[246]), .I2 (switch_data0[2]), @@ -246335,7 +246035,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_3[7] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_3[7] ( - .Z (_N21204), + .Z (_N21154), .I0 (s_axi_rdata1[183]), .I1 (s_axi_rdata1[247]), .I2 (switch_data0[2]), @@ -246347,7 +246047,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_3[8] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_3[8] ( - .Z (_N21205), + .Z (_N21155), .I0 (s_axi_rdata1[184]), .I1 (s_axi_rdata1[248]), .I2 (switch_data0[2]), @@ -246359,7 +246059,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_3[9] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_3[9] ( - .Z (_N21206), + .Z (_N21156), .I0 (s_axi_rdata1[185]), .I1 (s_axi_rdata1[249]), .I2 (switch_data0[2]), @@ -246371,7 +246071,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_3[10] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_3[10] ( - .Z (_N21207), + .Z (_N21157), .I0 (s_axi_rdata1[186]), .I1 (s_axi_rdata1[250]), .I2 (switch_data0[2]), @@ -246383,7 +246083,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_3[11] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_3[11] ( - .Z (_N21208), + .Z (_N21158), .I0 (s_axi_rdata1[187]), .I1 (s_axi_rdata1[251]), .I2 (switch_data0[2]), @@ -246395,7 +246095,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_3[12] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_3[12] ( - .Z (_N21209), + .Z (_N21159), .I0 (s_axi_rdata1[188]), .I1 (s_axi_rdata1[252]), .I2 (switch_data0[2]), @@ -246407,7 +246107,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_3[13] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_3[13] ( - .Z (_N21210), + .Z (_N21160), .I0 (s_axi_rdata1[189]), .I1 (s_axi_rdata1[253]), .I2 (switch_data0[2]), @@ -246419,7 +246119,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_3[14] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_3[14] ( - .Z (_N21211), + .Z (_N21161), .I0 (s_axi_rdata1[190]), .I1 (s_axi_rdata1[254]), .I2 (switch_data0[2]), @@ -246431,7 +246131,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_3[15] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_3[15] ( - .Z (_N21212), + .Z (_N21162), .I0 (s_axi_rdata1[191]), .I1 (s_axi_rdata1[255]), .I2 (switch_data0[2]), @@ -246443,7 +246143,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_6[0] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_6[0] ( - .Z (_N21245), + .Z (_N21195), .I0 (s_axi_rdata1[144]), .I1 (s_axi_rdata1[208]), .I2 (switch_data0[2]), @@ -246455,7 +246155,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_6[1] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_6[1] ( - .Z (_N21246), + .Z (_N21196), .I0 (s_axi_rdata1[145]), .I1 (s_axi_rdata1[209]), .I2 (switch_data0[2]), @@ -246467,7 +246167,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_6[2] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_6[2] ( - .Z (_N21247), + .Z (_N21197), .I0 (s_axi_rdata1[146]), .I1 (s_axi_rdata1[210]), .I2 (switch_data0[2]), @@ -246479,7 +246179,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_6[3] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_6[3] ( - .Z (_N21248), + .Z (_N21198), .I0 (s_axi_rdata1[147]), .I1 (s_axi_rdata1[211]), .I2 (switch_data0[2]), @@ -246491,7 +246191,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_6[4] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_6[4] ( - .Z (_N21249), + .Z (_N21199), .I0 (s_axi_rdata1[148]), .I1 (s_axi_rdata1[212]), .I2 (switch_data0[2]), @@ -246503,7 +246203,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_6[5] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_6[5] ( - .Z (_N21250), + .Z (_N21200), .I0 (s_axi_rdata1[149]), .I1 (s_axi_rdata1[213]), .I2 (switch_data0[2]), @@ -246515,7 +246215,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_6[6] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_6[6] ( - .Z (_N21251), + .Z (_N21201), .I0 (s_axi_rdata1[150]), .I1 (s_axi_rdata1[214]), .I2 (switch_data0[2]), @@ -246527,7 +246227,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_6[7] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_6[7] ( - .Z (_N21252), + .Z (_N21202), .I0 (s_axi_rdata1[151]), .I1 (s_axi_rdata1[215]), .I2 (switch_data0[2]), @@ -246539,7 +246239,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_6[8] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_6[8] ( - .Z (_N21253), + .Z (_N21203), .I0 (s_axi_rdata1[152]), .I1 (s_axi_rdata1[216]), .I2 (switch_data0[2]), @@ -246551,7 +246251,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_6[9] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_6[9] ( - .Z (_N21254), + .Z (_N21204), .I0 (s_axi_rdata1[153]), .I1 (s_axi_rdata1[217]), .I2 (switch_data0[2]), @@ -246563,7 +246263,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_6[10] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_6[10] ( - .Z (_N21255), + .Z (_N21205), .I0 (s_axi_rdata1[154]), .I1 (s_axi_rdata1[218]), .I2 (switch_data0[2]), @@ -246575,7 +246275,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_6[11] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_6[11] ( - .Z (_N21256), + .Z (_N21206), .I0 (s_axi_rdata1[155]), .I1 (s_axi_rdata1[219]), .I2 (switch_data0[2]), @@ -246587,7 +246287,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_6[12] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_6[12] ( - .Z (_N21257), + .Z (_N21207), .I0 (s_axi_rdata1[156]), .I1 (s_axi_rdata1[220]), .I2 (switch_data0[2]), @@ -246599,7 +246299,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_6[13] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_6[13] ( - .Z (_N21258), + .Z (_N21208), .I0 (s_axi_rdata1[157]), .I1 (s_axi_rdata1[221]), .I2 (switch_data0[2]), @@ -246611,7 +246311,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_6[14] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_6[14] ( - .Z (_N21259), + .Z (_N21209), .I0 (s_axi_rdata1[158]), .I1 (s_axi_rdata1[222]), .I2 (switch_data0[2]), @@ -246623,7 +246323,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_6[15] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_6[15] ( - .Z (_N21260), + .Z (_N21210), .I0 (s_axi_rdata1[159]), .I1 (s_axi_rdata1[223]), .I2 (switch_data0[2]), @@ -246633,105 +246333,105 @@ module axi_ddr_top // LUT = (I2&I3&~I4)|(ID&~I2&~I4)|(I0&~I2&I4)|(I1&I2&I4) ; GTP_MUX2LUT6 \N638_7[0] ( - .Z (_N21261), - .I0 (_N21245), - .I1 (_N21197), + .Z (_N21211), + .I0 (_N21195), + .I1 (_N21147), .S (switch_data0[1])); GTP_MUX2LUT6 \N638_7[1] ( - .Z (_N21262), - .I0 (_N21246), - .I1 (_N21198), + .Z (_N21212), + .I0 (_N21196), + .I1 (_N21148), .S (switch_data0[1])); GTP_MUX2LUT6 \N638_7[2] ( - .Z (_N21263), - .I0 (_N21247), - .I1 (_N21199), + .Z (_N21213), + .I0 (_N21197), + .I1 (_N21149), .S (switch_data0[1])); GTP_MUX2LUT6 \N638_7[3] ( - .Z (_N21264), - .I0 (_N21248), - .I1 (_N21200), + .Z (_N21214), + .I0 (_N21198), + .I1 (_N21150), .S (switch_data0[1])); GTP_MUX2LUT6 \N638_7[4] ( - .Z (_N21265), - .I0 (_N21249), - .I1 (_N21201), + .Z (_N21215), + .I0 (_N21199), + .I1 (_N21151), .S (switch_data0[1])); GTP_MUX2LUT6 \N638_7[5] ( - .Z (_N21266), - .I0 (_N21250), - .I1 (_N21202), + .Z (_N21216), + .I0 (_N21200), + .I1 (_N21152), .S (switch_data0[1])); GTP_MUX2LUT6 \N638_7[6] ( - .Z (_N21267), - .I0 (_N21251), - .I1 (_N21203), + .Z (_N21217), + .I0 (_N21201), + .I1 (_N21153), .S (switch_data0[1])); GTP_MUX2LUT6 \N638_7[7] ( - .Z (_N21268), - .I0 (_N21252), - .I1 (_N21204), + .Z (_N21218), + .I0 (_N21202), + .I1 (_N21154), .S (switch_data0[1])); GTP_MUX2LUT6 \N638_7[8] ( - .Z (_N21269), - .I0 (_N21253), - .I1 (_N21205), + .Z (_N21219), + .I0 (_N21203), + .I1 (_N21155), .S (switch_data0[1])); GTP_MUX2LUT6 \N638_7[9] ( - .Z (_N21270), - .I0 (_N21254), - .I1 (_N21206), + .Z (_N21220), + .I0 (_N21204), + .I1 (_N21156), .S (switch_data0[1])); GTP_MUX2LUT6 \N638_7[10] ( - .Z (_N21271), - .I0 (_N21255), - .I1 (_N21207), + .Z (_N21221), + .I0 (_N21205), + .I1 (_N21157), .S (switch_data0[1])); GTP_MUX2LUT6 \N638_7[11] ( - .Z (_N21272), - .I0 (_N21256), - .I1 (_N21208), + .Z (_N21222), + .I0 (_N21206), + .I1 (_N21158), .S (switch_data0[1])); GTP_MUX2LUT6 \N638_7[12] ( - .Z (_N21273), - .I0 (_N21257), - .I1 (_N21209), + .Z (_N21223), + .I0 (_N21207), + .I1 (_N21159), .S (switch_data0[1])); GTP_MUX2LUT6 \N638_7[13] ( - .Z (_N21274), - .I0 (_N21258), - .I1 (_N21210), + .Z (_N21224), + .I0 (_N21208), + .I1 (_N21160), .S (switch_data0[1])); GTP_MUX2LUT6 \N638_7[14] ( - .Z (_N21275), - .I0 (_N21259), - .I1 (_N21211), + .Z (_N21225), + .I0 (_N21209), + .I1 (_N21161), .S (switch_data0[1])); GTP_MUX2LUT6 \N638_7[15] ( - .Z (_N21276), - .I0 (_N21260), - .I1 (_N21212), + .Z (_N21226), + .I0 (_N21210), + .I1 (_N21162), .S (switch_data0[1])); GTP_LUT5M /* \N638_10[0] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_10[0] ( - .Z (_N21309), + .Z (_N21259), .I0 (s_axi_rdata1[160]), .I1 (s_axi_rdata1[224]), .I2 (switch_data0[2]), @@ -246743,7 +246443,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_10[1] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_10[1] ( - .Z (_N21310), + .Z (_N21260), .I0 (s_axi_rdata1[161]), .I1 (s_axi_rdata1[225]), .I2 (switch_data0[2]), @@ -246755,7 +246455,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_10[2] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_10[2] ( - .Z (_N21311), + .Z (_N21261), .I0 (s_axi_rdata1[162]), .I1 (s_axi_rdata1[226]), .I2 (switch_data0[2]), @@ -246767,7 +246467,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_10[3] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_10[3] ( - .Z (_N21312), + .Z (_N21262), .I0 (s_axi_rdata1[163]), .I1 (s_axi_rdata1[227]), .I2 (switch_data0[2]), @@ -246779,7 +246479,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_10[4] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_10[4] ( - .Z (_N21313), + .Z (_N21263), .I0 (s_axi_rdata1[164]), .I1 (s_axi_rdata1[228]), .I2 (switch_data0[2]), @@ -246791,7 +246491,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_10[5] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_10[5] ( - .Z (_N21314), + .Z (_N21264), .I0 (s_axi_rdata1[165]), .I1 (s_axi_rdata1[229]), .I2 (switch_data0[2]), @@ -246803,7 +246503,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_10[6] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_10[6] ( - .Z (_N21315), + .Z (_N21265), .I0 (s_axi_rdata1[166]), .I1 (s_axi_rdata1[230]), .I2 (switch_data0[2]), @@ -246815,7 +246515,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_10[7] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_10[7] ( - .Z (_N21316), + .Z (_N21266), .I0 (s_axi_rdata1[167]), .I1 (s_axi_rdata1[231]), .I2 (switch_data0[2]), @@ -246827,7 +246527,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_10[8] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_10[8] ( - .Z (_N21317), + .Z (_N21267), .I0 (s_axi_rdata1[168]), .I1 (s_axi_rdata1[232]), .I2 (switch_data0[2]), @@ -246839,7 +246539,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_10[9] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_10[9] ( - .Z (_N21318), + .Z (_N21268), .I0 (s_axi_rdata1[169]), .I1 (s_axi_rdata1[233]), .I2 (switch_data0[2]), @@ -246851,7 +246551,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_10[10] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_10[10] ( - .Z (_N21319), + .Z (_N21269), .I0 (s_axi_rdata1[170]), .I1 (s_axi_rdata1[234]), .I2 (switch_data0[2]), @@ -246863,7 +246563,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_10[11] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_10[11] ( - .Z (_N21320), + .Z (_N21270), .I0 (s_axi_rdata1[171]), .I1 (s_axi_rdata1[235]), .I2 (switch_data0[2]), @@ -246875,7 +246575,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_10[12] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_10[12] ( - .Z (_N21321), + .Z (_N21271), .I0 (s_axi_rdata1[172]), .I1 (s_axi_rdata1[236]), .I2 (switch_data0[2]), @@ -246887,7 +246587,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_10[13] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_10[13] ( - .Z (_N21322), + .Z (_N21272), .I0 (s_axi_rdata1[173]), .I1 (s_axi_rdata1[237]), .I2 (switch_data0[2]), @@ -246899,7 +246599,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_10[14] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_10[14] ( - .Z (_N21323), + .Z (_N21273), .I0 (s_axi_rdata1[174]), .I1 (s_axi_rdata1[238]), .I2 (switch_data0[2]), @@ -246911,7 +246611,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_10[15] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_10[15] ( - .Z (_N21324), + .Z (_N21274), .I0 (s_axi_rdata1[175]), .I1 (s_axi_rdata1[239]), .I2 (switch_data0[2]), @@ -246923,7 +246623,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_13[0] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_13[0] ( - .Z (_N21357), + .Z (_N21307), .I0 (s_axi_rdata1[128]), .I1 (s_axi_rdata1[192]), .I2 (switch_data0[2]), @@ -246935,7 +246635,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_13[1] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_13[1] ( - .Z (_N21358), + .Z (_N21308), .I0 (s_axi_rdata1[129]), .I1 (s_axi_rdata1[193]), .I2 (switch_data0[2]), @@ -246947,7 +246647,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_13[2] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_13[2] ( - .Z (_N21359), + .Z (_N21309), .I0 (s_axi_rdata1[130]), .I1 (s_axi_rdata1[194]), .I2 (switch_data0[2]), @@ -246959,7 +246659,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_13[3] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_13[3] ( - .Z (_N21360), + .Z (_N21310), .I0 (s_axi_rdata1[131]), .I1 (s_axi_rdata1[195]), .I2 (switch_data0[2]), @@ -246971,7 +246671,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_13[4] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_13[4] ( - .Z (_N21361), + .Z (_N21311), .I0 (s_axi_rdata1[132]), .I1 (s_axi_rdata1[196]), .I2 (switch_data0[2]), @@ -246983,7 +246683,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_13[5] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_13[5] ( - .Z (_N21362), + .Z (_N21312), .I0 (s_axi_rdata1[133]), .I1 (s_axi_rdata1[197]), .I2 (switch_data0[2]), @@ -246995,7 +246695,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_13[6] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_13[6] ( - .Z (_N21363), + .Z (_N21313), .I0 (s_axi_rdata1[134]), .I1 (s_axi_rdata1[198]), .I2 (switch_data0[2]), @@ -247007,7 +246707,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_13[7] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_13[7] ( - .Z (_N21364), + .Z (_N21314), .I0 (s_axi_rdata1[135]), .I1 (s_axi_rdata1[199]), .I2 (switch_data0[2]), @@ -247019,7 +246719,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_13[8] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_13[8] ( - .Z (_N21365), + .Z (_N21315), .I0 (s_axi_rdata1[136]), .I1 (s_axi_rdata1[200]), .I2 (switch_data0[2]), @@ -247031,7 +246731,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_13[9] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_13[9] ( - .Z (_N21366), + .Z (_N21316), .I0 (s_axi_rdata1[137]), .I1 (s_axi_rdata1[201]), .I2 (switch_data0[2]), @@ -247043,7 +246743,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_13[10] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_13[10] ( - .Z (_N21367), + .Z (_N21317), .I0 (s_axi_rdata1[138]), .I1 (s_axi_rdata1[202]), .I2 (switch_data0[2]), @@ -247055,7 +246755,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_13[11] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_13[11] ( - .Z (_N21368), + .Z (_N21318), .I0 (s_axi_rdata1[139]), .I1 (s_axi_rdata1[203]), .I2 (switch_data0[2]), @@ -247067,7 +246767,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_13[12] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_13[12] ( - .Z (_N21369), + .Z (_N21319), .I0 (s_axi_rdata1[140]), .I1 (s_axi_rdata1[204]), .I2 (switch_data0[2]), @@ -247079,7 +246779,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_13[13] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_13[13] ( - .Z (_N21370), + .Z (_N21320), .I0 (s_axi_rdata1[141]), .I1 (s_axi_rdata1[205]), .I2 (switch_data0[2]), @@ -247091,7 +246791,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_13[14] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_13[14] ( - .Z (_N21371), + .Z (_N21321), .I0 (s_axi_rdata1[142]), .I1 (s_axi_rdata1[206]), .I2 (switch_data0[2]), @@ -247103,7 +246803,7 @@ module axi_ddr_top GTP_LUT5M /* \N638_13[15] */ #( .INIT(32'b11001010110010101111101000001010)) \N638_13[15] ( - .Z (_N21372), + .Z (_N21322), .I0 (s_axi_rdata1[143]), .I1 (s_axi_rdata1[207]), .I2 (switch_data0[2]), @@ -247113,195 +246813,195 @@ module axi_ddr_top // LUT = (I2&I3&~I4)|(ID&~I2&~I4)|(I0&~I2&I4)|(I1&I2&I4) ; GTP_MUX2LUT6 \N638_14[0] ( - .Z (_N21373), - .I0 (_N21357), - .I1 (_N21309), + .Z (_N21323), + .I0 (_N21307), + .I1 (_N21259), .S (switch_data0[1])); GTP_MUX2LUT6 \N638_14[1] ( - .Z (_N21374), - .I0 (_N21358), - .I1 (_N21310), + .Z (_N21324), + .I0 (_N21308), + .I1 (_N21260), .S (switch_data0[1])); GTP_MUX2LUT6 \N638_14[2] ( - .Z (_N21375), - .I0 (_N21359), - .I1 (_N21311), + .Z (_N21325), + .I0 (_N21309), + .I1 (_N21261), .S (switch_data0[1])); GTP_MUX2LUT6 \N638_14[3] ( - .Z (_N21376), - .I0 (_N21360), - .I1 (_N21312), + .Z (_N21326), + .I0 (_N21310), + .I1 (_N21262), .S (switch_data0[1])); GTP_MUX2LUT6 \N638_14[4] ( - .Z (_N21377), - .I0 (_N21361), - .I1 (_N21313), + .Z (_N21327), + .I0 (_N21311), + .I1 (_N21263), .S (switch_data0[1])); GTP_MUX2LUT6 \N638_14[5] ( - .Z (_N21378), - .I0 (_N21362), - .I1 (_N21314), + .Z (_N21328), + .I0 (_N21312), + .I1 (_N21264), .S (switch_data0[1])); GTP_MUX2LUT6 \N638_14[6] ( - .Z (_N21379), - .I0 (_N21363), - .I1 (_N21315), + .Z (_N21329), + .I0 (_N21313), + .I1 (_N21265), .S (switch_data0[1])); GTP_MUX2LUT6 \N638_14[7] ( - .Z (_N21380), - .I0 (_N21364), - .I1 (_N21316), + .Z (_N21330), + .I0 (_N21314), + .I1 (_N21266), .S (switch_data0[1])); GTP_MUX2LUT6 \N638_14[8] ( - .Z (_N21381), - .I0 (_N21365), - .I1 (_N21317), + .Z (_N21331), + .I0 (_N21315), + .I1 (_N21267), .S (switch_data0[1])); GTP_MUX2LUT6 \N638_14[9] ( - .Z (_N21382), - .I0 (_N21366), - .I1 (_N21318), + .Z (_N21332), + .I0 (_N21316), + .I1 (_N21268), .S (switch_data0[1])); GTP_MUX2LUT6 \N638_14[10] ( - .Z (_N21383), - .I0 (_N21367), - .I1 (_N21319), + .Z (_N21333), + .I0 (_N21317), + .I1 (_N21269), .S (switch_data0[1])); GTP_MUX2LUT6 \N638_14[11] ( - .Z (_N21384), - .I0 (_N21368), - .I1 (_N21320), + .Z (_N21334), + .I0 (_N21318), + .I1 (_N21270), .S (switch_data0[1])); GTP_MUX2LUT6 \N638_14[12] ( - .Z (_N21385), - .I0 (_N21369), - .I1 (_N21321), + .Z (_N21335), + .I0 (_N21319), + .I1 (_N21271), .S (switch_data0[1])); GTP_MUX2LUT6 \N638_14[13] ( - .Z (_N21386), - .I0 (_N21370), - .I1 (_N21322), + .Z (_N21336), + .I0 (_N21320), + .I1 (_N21272), .S (switch_data0[1])); GTP_MUX2LUT6 \N638_14[14] ( - .Z (_N21387), - .I0 (_N21371), - .I1 (_N21323), + .Z (_N21337), + .I0 (_N21321), + .I1 (_N21273), .S (switch_data0[1])); GTP_MUX2LUT6 \N638_14[15] ( - .Z (_N21388), - .I0 (_N21372), - .I1 (_N21324), + .Z (_N21338), + .I0 (_N21322), + .I1 (_N21274), .S (switch_data0[1])); GTP_MUX2LUT7 \N638_15[0] ( .Z (N638[0]), - .I0 (_N21373), - .I1 (_N21261), + .I0 (_N21323), + .I1 (_N21211), .S (switch_data0[0])); GTP_MUX2LUT7 \N638_15[1] ( .Z (N638[1]), - .I0 (_N21374), - .I1 (_N21262), + .I0 (_N21324), + .I1 (_N21212), .S (switch_data0[0])); GTP_MUX2LUT7 \N638_15[2] ( .Z (N638[2]), - .I0 (_N21375), - .I1 (_N21263), + .I0 (_N21325), + .I1 (_N21213), .S (switch_data0[0])); GTP_MUX2LUT7 \N638_15[3] ( .Z (N638[3]), - .I0 (_N21376), - .I1 (_N21264), + .I0 (_N21326), + .I1 (_N21214), .S (switch_data0[0])); GTP_MUX2LUT7 \N638_15[4] ( .Z (N638[4]), - .I0 (_N21377), - .I1 (_N21265), + .I0 (_N21327), + .I1 (_N21215), .S (switch_data0[0])); GTP_MUX2LUT7 \N638_15[5] ( .Z (N638[5]), - .I0 (_N21378), - .I1 (_N21266), + .I0 (_N21328), + .I1 (_N21216), .S (switch_data0[0])); GTP_MUX2LUT7 \N638_15[6] ( .Z (N638[6]), - .I0 (_N21379), - .I1 (_N21267), + .I0 (_N21329), + .I1 (_N21217), .S (switch_data0[0])); GTP_MUX2LUT7 \N638_15[7] ( .Z (N638[7]), - .I0 (_N21380), - .I1 (_N21268), + .I0 (_N21330), + .I1 (_N21218), .S (switch_data0[0])); GTP_MUX2LUT7 \N638_15[8] ( .Z (N638[8]), - .I0 (_N21381), - .I1 (_N21269), + .I0 (_N21331), + .I1 (_N21219), .S (switch_data0[0])); GTP_MUX2LUT7 \N638_15[9] ( .Z (N638[9]), - .I0 (_N21382), - .I1 (_N21270), + .I0 (_N21332), + .I1 (_N21220), .S (switch_data0[0])); GTP_MUX2LUT7 \N638_15[10] ( .Z (N638[10]), - .I0 (_N21383), - .I1 (_N21271), + .I0 (_N21333), + .I1 (_N21221), .S (switch_data0[0])); GTP_MUX2LUT7 \N638_15[11] ( .Z (N638[11]), - .I0 (_N21384), - .I1 (_N21272), + .I0 (_N21334), + .I1 (_N21222), .S (switch_data0[0])); GTP_MUX2LUT7 \N638_15[12] ( .Z (N638[12]), - .I0 (_N21385), - .I1 (_N21273), + .I0 (_N21335), + .I1 (_N21223), .S (switch_data0[0])); GTP_MUX2LUT7 \N638_15[13] ( .Z (N638[13]), - .I0 (_N21386), - .I1 (_N21274), + .I0 (_N21336), + .I1 (_N21224), .S (switch_data0[0])); GTP_MUX2LUT7 \N638_15[14] ( .Z (N638[14]), - .I0 (_N21387), - .I1 (_N21275), + .I0 (_N21337), + .I1 (_N21225), .S (switch_data0[0])); GTP_MUX2LUT7 \N638_15[15] ( .Z (N638[15]), - .I0 (_N21388), - .I1 (_N21276), + .I0 (_N21338), + .I1 (_N21226), .S (switch_data0[0])); GTP_LUT2 /* N655_sum1 */ #( @@ -247355,7 +247055,7 @@ module axi_ddr_top GTP_LUT5 /* N733_8 */ #( .INIT(32'b00000000000000000000000000000001)) N733_8 ( - .Z (_N105194), + .Z (_N105763), .I0 (cnt0_times[0]), .I1 (cnt0_times[1]), .I2 (cnt0_times[6]), @@ -247371,13 +247071,13 @@ module axi_ddr_top .I1 (cnt0_times[3]), .I2 (cnt0_times[4]), .I3 (cnt0_times[5]), - .I4 (_N105194)); + .I4 (_N105763)); // LUT = ~I0&~I1&~I2&~I3&I4 ; GTP_LUT5 /* N743_8 */ #( .INIT(32'b00000000000000000000000000000001)) N743_8 ( - .Z (_N105174), + .Z (_N105721), .I0 (cnt1_times[0]), .I1 (cnt1_times[1]), .I2 (cnt1_times[6]), @@ -247393,7 +247093,7 @@ module axi_ddr_top .I1 (cnt1_times[3]), .I2 (cnt1_times[4]), .I3 (cnt1_times[5]), - .I4 (_N105174)); + .I4 (_N105721)); // LUT = ~I0&~I1&~I2&~I3&I4 ; GTP_INV N783_1_vname ( @@ -247680,7 +247380,7 @@ module axi_ddr_top GTP_LUT4 /* \N866_2_and[24][0]_1 */ #( .INIT(16'b1111100010001000)) \N866_2_and[24][0]_1 ( - .Z (_N108367), + .Z (_N109252), .I0 (rd0_ddr_sart_addr2[10]), .I1 (rd_sta[0]), .I2 (rd1_ddr_sart_addr2[10]), @@ -247690,7 +247390,7 @@ module axi_ddr_top GTP_LUT4 /* \N866_2_and[25][0]_1 */ #( .INIT(16'b1111100010001000)) \N866_2_and[25][0]_1 ( - .Z (_N108368), + .Z (_N109253), .I0 (rd0_ddr_sart_addr2[11]), .I1 (rd_sta[0]), .I2 (rd1_ddr_sart_addr2[11]), @@ -247700,7 +247400,7 @@ module axi_ddr_top GTP_LUT4 /* \N866_2_and[26][0]_1 */ #( .INIT(16'b1111100010001000)) \N866_2_and[26][0]_1 ( - .Z (_N108369), + .Z (_N109254), .I0 (rd0_ddr_sart_addr2[12]), .I1 (rd_sta[0]), .I2 (rd1_ddr_sart_addr2[12]), @@ -247710,7 +247410,7 @@ module axi_ddr_top GTP_LUT4 /* \N866_2_and[27][0]_1 */ #( .INIT(16'b1111100010001000)) \N866_2_and[27][0]_1 ( - .Z (_N108370), + .Z (_N109255), .I0 (rd0_ddr_sart_addr2[13]), .I1 (rd_sta[0]), .I2 (rd1_ddr_sart_addr2[13]), @@ -247720,7 +247420,7 @@ module axi_ddr_top GTP_LUT4 /* \N866_2_and[28][0]_1 */ #( .INIT(16'b1111100010001000)) \N866_2_and[28][0]_1 ( - .Z (_N108371), + .Z (_N109256), .I0 (rd0_ddr_sart_addr2[14]), .I1 (rd_sta[0]), .I2 (rd1_ddr_sart_addr2[14]), @@ -247730,7 +247430,7 @@ module axi_ddr_top GTP_LUT4 /* \N866_2_and[29][0]_1 */ #( .INIT(16'b1111100010001000)) \N866_2_and[29][0]_1 ( - .Z (_N108372), + .Z (_N109257), .I0 (rd0_ddr_sart_addr2[15]), .I1 (rd_sta[0]), .I2 (rd1_ddr_sart_addr2[15]), @@ -247740,7 +247440,7 @@ module axi_ddr_top GTP_LUT4 /* \N866_2_and[30][0]_1 */ #( .INIT(16'b1111100010001000)) \N866_2_and[30][0]_1 ( - .Z (_N108373), + .Z (_N109258), .I0 (rd0_ddr_sart_addr2[16]), .I1 (rd_sta[0]), .I2 (rd1_ddr_sart_addr2[16]), @@ -247750,7 +247450,7 @@ module axi_ddr_top GTP_LUT4 /* \N866_2_and[31][0]_1 */ #( .INIT(16'b1111100010001000)) \N866_2_and[31][0]_1 ( - .Z (_N108374), + .Z (_N109259), .I0 (rd0_ddr_sart_addr2[17]), .I1 (rd_sta[0]), .I2 (rd1_ddr_sart_addr2[17]), @@ -247760,7 +247460,7 @@ module axi_ddr_top GTP_LUT4 /* \N866_2_and[32][0]_1 */ #( .INIT(16'b1111100010001000)) \N866_2_and[32][0]_1 ( - .Z (_N108375), + .Z (_N109260), .I0 (rd0_ddr_sart_addr2[18]), .I1 (rd_sta[0]), .I2 (rd1_ddr_sart_addr2[18]), @@ -247770,7 +247470,7 @@ module axi_ddr_top GTP_LUT4 /* \N866_2_and[33][0]_1 */ #( .INIT(16'b1111100010001000)) \N866_2_and[33][0]_1 ( - .Z (_N108376), + .Z (_N109261), .I0 (rd0_ddr_sart_addr2[19]), .I1 (rd_sta[0]), .I2 (rd1_ddr_sart_addr2[19]), @@ -247780,7 +247480,7 @@ module axi_ddr_top GTP_LUT4 /* \N866_2_and[34][0]_1 */ #( .INIT(16'b1111100010001000)) \N866_2_and[34][0]_1 ( - .Z (_N108377), + .Z (_N109262), .I0 (rd0_ddr_sart_addr2[20]), .I1 (rd_sta[0]), .I2 (rd1_ddr_sart_addr2[20]), @@ -247790,7 +247490,7 @@ module axi_ddr_top GTP_LUT4 /* \N866_2_and[35][0]_1 */ #( .INIT(16'b1111100010001000)) \N866_2_and[35][0]_1 ( - .Z (_N108378), + .Z (_N109263), .I0 (rd0_ddr_sart_addr2[21]), .I1 (rd_sta[0]), .I2 (rd1_ddr_sart_addr2[21]), @@ -247800,7 +247500,7 @@ module axi_ddr_top GTP_LUT4 /* \N866_2_and[36][0]_1 */ #( .INIT(16'b1111100010001000)) \N866_2_and[36][0]_1 ( - .Z (_N108379), + .Z (_N109264), .I0 (rd0_ddr_sart_addr2[22]), .I1 (rd_sta[0]), .I2 (rd1_ddr_sart_addr2[22]), @@ -247810,7 +247510,7 @@ module axi_ddr_top GTP_LUT4 /* \N866_2_and[37][0]_1 */ #( .INIT(16'b1111100010001000)) \N866_2_and[37][0]_1 ( - .Z (_N108380), + .Z (_N109265), .I0 (rd0_ddr_sart_addr2[23]), .I1 (rd_sta[0]), .I2 (rd1_ddr_sart_addr2[23]), @@ -247820,7 +247520,7 @@ module axi_ddr_top GTP_LUT2 /* \N866_2_and[38][1] */ #( .INIT(4'b1000)) \N866_2_and[38][1] ( - .Z (_N30074), + .Z (_N30044), .I0 (rd1_ddr_sart_addr2[24]), .I1 (rd_sta[2])); // LUT = I0&I1 ; @@ -247982,7 +247682,7 @@ module axi_ddr_top .I4_TO_CARRY("FALSE"), .I4_TO_LUT("FALSE")) N866_6_0 ( - .COUT (_N14194), + .COUT (_N14203), .Z (), .CIN (), .I0 (), @@ -248001,9 +247701,9 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N866_6_2 ( - .COUT (_N14196), + .COUT (_N14205), .Z (nb0[9]), - .CIN (_N14194), + .CIN (_N14203), .I0 (), .I1 (rd1_ddr_sart_addr2[9]), .I2 (nb1[9]), @@ -248020,13 +247720,13 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N866_6_3 ( - .COUT (_N14197), + .COUT (_N14206), .Z (nb0[10]), - .CIN (_N14196), + .CIN (_N14205), .I0 (), .I1 (), .I2 (nb1[10]), - .I3 (_N108367), + .I3 (_N109252), .I4 (nb1[10]), .ID ()); // LUT = I3^I2^CIN ; @@ -248039,13 +247739,13 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N866_6_4 ( - .COUT (_N14198), + .COUT (_N14207), .Z (nb0[11]), - .CIN (_N14197), + .CIN (_N14206), .I0 (), .I1 (), .I2 (nb1[11]), - .I3 (_N108368), + .I3 (_N109253), .I4 (nb1[11]), .ID ()); // LUT = I3^I2^CIN ; @@ -248058,13 +247758,13 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N866_6_5 ( - .COUT (_N14199), + .COUT (_N14208), .Z (nb0[12]), - .CIN (_N14198), + .CIN (_N14207), .I0 (), .I1 (), .I2 (nb1[12]), - .I3 (_N108369), + .I3 (_N109254), .I4 (nb1[12]), .ID ()); // LUT = I3^I2^CIN ; @@ -248077,13 +247777,13 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N866_6_6 ( - .COUT (_N14200), + .COUT (_N14209), .Z (nb0[13]), - .CIN (_N14199), + .CIN (_N14208), .I0 (), .I1 (), .I2 (nb1[13]), - .I3 (_N108370), + .I3 (_N109255), .I4 (nb1[13]), .ID ()); // LUT = I3^I2^CIN ; @@ -248096,13 +247796,13 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N866_6_7 ( - .COUT (_N14201), + .COUT (_N14210), .Z (nb0[14]), - .CIN (_N14200), + .CIN (_N14209), .I0 (), .I1 (), .I2 (nb1[14]), - .I3 (_N108371), + .I3 (_N109256), .I4 (nb1[14]), .ID ()); // LUT = I3^I2^CIN ; @@ -248115,13 +247815,13 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N866_6_8 ( - .COUT (_N14202), + .COUT (_N14211), .Z (nb0[15]), - .CIN (_N14201), + .CIN (_N14210), .I0 (), .I1 (), .I2 (nb1[15]), - .I3 (_N108372), + .I3 (_N109257), .I4 (nb1[15]), .ID ()); // LUT = I3^I2^CIN ; @@ -248134,13 +247834,13 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N866_6_9 ( - .COUT (_N14203), + .COUT (_N14212), .Z (nb0[16]), - .CIN (_N14202), + .CIN (_N14211), .I0 (), .I1 (), .I2 (nb1[16]), - .I3 (_N108373), + .I3 (_N109258), .I4 (nb1[16]), .ID ()); // LUT = I3^I2^CIN ; @@ -248153,13 +247853,13 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N866_6_10 ( - .COUT (_N14204), + .COUT (_N14213), .Z (nb0[17]), - .CIN (_N14203), + .CIN (_N14212), .I0 (), .I1 (), .I2 (nb1[17]), - .I3 (_N108374), + .I3 (_N109259), .I4 (nb1[17]), .ID ()); // LUT = I3^I2^CIN ; @@ -248172,13 +247872,13 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N866_6_11 ( - .COUT (_N14205), + .COUT (_N14214), .Z (nb0[18]), - .CIN (_N14204), + .CIN (_N14213), .I0 (), .I1 (), .I2 (nb1[18]), - .I3 (_N108375), + .I3 (_N109260), .I4 (nb1[18]), .ID ()); // LUT = I3^I2^CIN ; @@ -248191,13 +247891,13 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N866_6_12 ( - .COUT (_N14206), + .COUT (_N14215), .Z (nb0[19]), - .CIN (_N14205), + .CIN (_N14214), .I0 (), .I1 (), .I2 (nb1[19]), - .I3 (_N108376), + .I3 (_N109261), .I4 (nb1[19]), .ID ()); // LUT = I3^I2^CIN ; @@ -248210,13 +247910,13 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N866_6_13 ( - .COUT (_N14207), + .COUT (_N14216), .Z (nb0[20]), - .CIN (_N14206), + .CIN (_N14215), .I0 (), .I1 (), .I2 (nb1[20]), - .I3 (_N108377), + .I3 (_N109262), .I4 (nb1[20]), .ID ()); // LUT = I3^I2^CIN ; @@ -248229,13 +247929,13 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N866_6_14 ( - .COUT (_N14208), + .COUT (_N14217), .Z (nb0[21]), - .CIN (_N14207), + .CIN (_N14216), .I0 (), .I1 (), .I2 (nb1[21]), - .I3 (_N108378), + .I3 (_N109263), .I4 (nb1[21]), .ID ()); // LUT = I3^I2^CIN ; @@ -248248,13 +247948,13 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N866_6_15 ( - .COUT (_N14209), + .COUT (_N14218), .Z (nb0[22]), - .CIN (_N14208), + .CIN (_N14217), .I0 (), .I1 (), .I2 (nb1[22]), - .I3 (_N108379), + .I3 (_N109264), .I4 (nb1[22]), .ID ()); // LUT = I3^I2^CIN ; @@ -248267,13 +247967,13 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N866_6_16 ( - .COUT (_N14210), + .COUT (_N14219), .Z (nb0[23]), - .CIN (_N14209), + .CIN (_N14218), .I0 (), .I1 (), .I2 (nb1[23]), - .I3 (_N108380), + .I3 (_N109265), .I4 (nb1[23]), .ID ()); // LUT = I3^I2^CIN ; @@ -248286,12 +247986,12 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N866_6_17 ( - .COUT (_N14211), + .COUT (_N14220), .Z (nb0[24]), - .CIN (_N14210), + .CIN (_N14219), .I0 (), .I1 (rd0_ddr_sart_addr2[24]), - .I2 (_N30074), + .I2 (_N30044), .I3 (rd_sta[0]), .I4 (1'b0), .ID ()); @@ -248305,9 +248005,9 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N866_6_18 ( - .COUT (_N14212), + .COUT (_N14221), .Z (nb0[25]), - .CIN (_N14211), + .CIN (_N14220), .I0 (), .I1 (rd_sta[2]), .I2 (rd0_ddr_sart_addr2[25]), @@ -248324,9 +248024,9 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N866_6_19 ( - .COUT (_N14213), + .COUT (_N14222), .Z (nb0[26]), - .CIN (_N14212), + .CIN (_N14221), .I0 (), .I1 (rd_sta[2]), .I2 (rd0_ddr_sart_addr2[26]), @@ -248343,9 +248043,9 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N866_6_20 ( - .COUT (_N14214), + .COUT (_N14223), .Z (nb0[27]), - .CIN (_N14213), + .CIN (_N14222), .I0 (), .I1 (rd0_ddr_sart_addr2[27]), .I2 (rd_sta[0]), @@ -248362,9 +248062,9 @@ module axi_ddr_top .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N866_6_21 ( - .COUT (_N14215), + .COUT (_N14224), .Z (nb0[28]), - .CIN (_N14214), + .CIN (_N14223), .I0 (), .I1 (rd0_ddr_sart_addr2[28]), .I2 (rd_sta[0]), @@ -248383,7 +248083,7 @@ module axi_ddr_top N866_6_22 ( .COUT (), .Z (nb0[29]), - .CIN (_N14215), + .CIN (_N14224), .I0 (), .I1 (rd0_ddr_sart_addr2[29]), .I2 (rd_sta[0]), @@ -248422,8 +248122,8 @@ module axi_ddr_top .Z (N878), .I0 (rd0_addr_start_fall), .I1 (rd_sta[1]), - .I2 (_N104712), - .I3 (_N104713)); + .I2 (_N105745), + .I3 (_N105746)); // defparam N878_vname.orig_name = N878; // LUT = (I0&~I1)|(~I1&I2)|(~I1&I3) ; @@ -248443,16 +248143,16 @@ module axi_ddr_top .Z (N889), .I0 (rd1_addr_start_fall), .I1 (rd_sta[3]), - .I2 (_N105152), - .I3 (_N105153), - .I4 (_N105157)); + .I2 (_N105699), + .I3 (_N105700), + .I4 (_N105704)); // defparam N889_vname.orig_name = N889; // LUT = (~I1&~I4)|(~I1&~I3)|(~I1&~I2)|(I0&~I1) ; GTP_LUT4 /* N924_7 */ #( .INIT(16'b1111111111111110)) N924_7 ( - .Z (_N105184), + .Z (_N105753), .I0 (cnt0_times[2]), .I1 (cnt0_times[3]), .I2 (cnt0_times[4]), @@ -248462,7 +248162,7 @@ module axi_ddr_top GTP_LUT4 /* N924_8 */ #( .INIT(16'b1111111111110100)) N924_8 ( - .Z (_N105185), + .Z (_N105754), .I0 (rd_sta0_reg0), .I1 (rd_sta0_reg1), .I2 (cnt0_times[6]), @@ -248476,8 +248176,8 @@ module axi_ddr_top .I0 (cnt0_times[0]), .I1 (cnt0_times[1]), .I2 (cnt0_times[8]), - .I3 (_N105184), - .I4 (_N105185)); + .I3 (_N105753), + .I4 (_N105754)); // LUT = (I0)|(I1)|(I2)|(I3)|(I4) ; GTP_LUT3 /* \N925[0] */ #( @@ -248493,7 +248193,7 @@ module axi_ddr_top GTP_LUT4 /* N928_7 */ #( .INIT(16'b1111111111111110)) N928_7 ( - .Z (_N105164), + .Z (_N105711), .I0 (cnt1_times[2]), .I1 (cnt1_times[3]), .I2 (cnt1_times[4]), @@ -248503,7 +248203,7 @@ module axi_ddr_top GTP_LUT4 /* N928_8 */ #( .INIT(16'b1111111111110100)) N928_8 ( - .Z (_N105165), + .Z (_N105712), .I0 (rd_sta2_reg0), .I1 (rd_sta2_reg1), .I2 (cnt1_times[6]), @@ -248517,8 +248217,8 @@ module axi_ddr_top .I0 (cnt1_times[0]), .I1 (cnt1_times[1]), .I2 (cnt1_times[8]), - .I3 (_N105164), - .I4 (_N105165)); + .I3 (_N105711), + .I4 (_N105712)); // LUT = (I0)|(I1)|(I2)|(I3)|(I4) ; GTP_LUT3 /* \N929[0] */ #( @@ -250417,7 +250117,7 @@ module axi_ddr_top GTP_LUT4 /* \rd1_done_cnt[2:0]_0 */ #( .INIT(16'b1111111010101010)) \rd1_done_cnt[2:0]_0 ( - .Z (_N41595), + .Z (_N39473), .I0 (rd1_ddr_done0), .I1 (rd1_done_cnt[0]), .I2 (rd1_done_cnt[1]), @@ -250458,7 +250158,7 @@ module axi_ddr_top .Q (rd1_done_cnt[2]), .CE (_N50), .CLK (clk), - .D (_N41595), + .D (_N39473), .R (rst)); // ../../sources/designs/ddr/rd_wr_ctrl/axi_ddr_top.v:801 @@ -250898,7 +250598,7 @@ module axi_ddr_top record_addr_valid_vname ( .Q (record_addr_valid), .CLK (clk), - .D (_N103325), + .D (_N104137), .R (rst)); // defparam record_addr_valid_vname.orig_name = record_addr_valid; // ../../sources/designs/ddr/rd_wr_ctrl/axi_ddr_top.v:455 @@ -250906,7 +250606,7 @@ module axi_ddr_top GTP_LUT4 /* record_addr_valid_ce_mux */ #( .INIT(16'b1011101011111010)) record_addr_valid_ce_mux ( - .Z (_N103325), + .Z (_N104137), .I0 (wr_sta_reg[1]), .I1 (araddr_empty), .I2 (record_addr_valid), @@ -250919,14 +250619,14 @@ module axi_ddr_top record_araddr_valid_vname ( .Q (record_araddr_valid), .CLK (clk), - .D (_N103532)); + .D (_N104344)); // defparam record_araddr_valid_vname.orig_name = record_araddr_valid; // ../../sources/designs/ddr/rd_wr_ctrl/axi_ddr_top.v:736 GTP_LUT5 /* record_araddr_valid_rs_mux */ #( .INIT(32'b00001010000011100000111000001110)) record_araddr_valid_rs_mux ( - .Z (_N103532), + .Z (_N104344), .I0 (N440), .I1 (record_araddr_valid), .I2 (rst), @@ -250940,7 +250640,7 @@ module axi_ddr_top record_data_valid_vname ( .Q (record_data_valid), .CLK (clk), - .D (_N103324), + .D (_N104136), .R (rst)); // defparam record_data_valid_vname.orig_name = record_data_valid; // ../../sources/designs/ddr/rd_wr_ctrl/axi_ddr_top.v:455 @@ -250948,7 +250648,7 @@ module axi_ddr_top GTP_LUT4 /* record_data_valid_ce_mux */ #( .INIT(16'b1010111011101110)) record_data_valid_ce_mux ( - .Z (_N103324), + .Z (_N104136), .I0 (wr_sta_reg[1]), .I1 (record_data_valid), .I2 (wdata_empty), @@ -250970,14 +250670,14 @@ module axi_ddr_top rx_rd0_addr_valid_vname ( .Q (rx_rd0_addr_valid), .CLK (clk), - .D (_N103534)); + .D (_N104346)); // defparam rx_rd0_addr_valid_vname.orig_name = rx_rd0_addr_valid; // ../../sources/designs/ddr/rd_wr_ctrl/axi_ddr_top.v:826 GTP_LUT4 /* rx_rd0_addr_valid_rs_mux */ #( .INIT(16'b0000101100001010)) rx_rd0_addr_valid_rs_mux ( - .Z (_N103534), + .Z (_N104346), .I0 (rd0_addr_start_fall), .I1 (rd0_ddr_done0), .I2 (rst), @@ -250990,14 +250690,14 @@ module axi_ddr_top rx_rd1_addr_valid_vname ( .Q (rx_rd1_addr_valid), .CLK (clk), - .D (_N103536)); + .D (_N104348)); // defparam rx_rd1_addr_valid_vname.orig_name = rx_rd1_addr_valid; // ../../sources/designs/ddr/rd_wr_ctrl/axi_ddr_top.v:826 GTP_LUT4 /* rx_rd1_addr_valid_rs_mux */ #( .INIT(16'b0000101100001010)) rx_rd1_addr_valid_rs_mux ( - .Z (_N103536), + .Z (_N104348), .I0 (rd1_addr_start_fall), .I1 (rd1_ddr_done0), .I2 (rst), @@ -255984,10 +255684,10 @@ module axi_ddr_top .rd1_fifo_full (rd1_fifo_full), .N78 (\u_axi_rd_connect/N78 ), .N78_1 (\u_axi_rd_connect/N78_1 ), - .N241_0 (N241_0), + .N242_0 (N242_0), .clk (clk), .rd0_clk (rd0_clk), - .rd1_clk (ddr_clk), + .rd1_clk (rd1_clk), .rst (rst), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/calib_done (\I_ipsxb_ddr_top/u_ddrphy_top/calib_done ), .\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/read_valid (\I_ipsxb_ddr_top/u_ddrphy_top/read_valid )); @@ -256034,7 +255734,7 @@ module axi_ddr_top .rd_data (rd3_data), .wr_water_level ({\u_rdata3_fifo/wr_water_level [9] , \u_rdata3_fifo/wr_water_level [8] , \u_rdata3_fifo_wr_water_level[7]_floating , \u_rdata3_fifo_wr_water_level[6]_floating , \u_rdata3_fifo_wr_water_level[5]_floating , \u_rdata3_fifo_wr_water_level[4]_floating , \u_rdata3_fifo/wr_water_level [3] , \u_rdata3_fifo/wr_water_level [2] , \u_rdata3_fifo_wr_water_level[1]_floating , \u_rdata3_fifo_wr_water_level[0]_floating }), .wr_data (rd3_ddr_data), - ._N104649 (_N104649), + ._N105484 (_N105484), .rd_empty (rd3_data_empty), .rd_clk (rd0_clk), .rd_rst (rst), @@ -256074,7 +255774,7 @@ module axi_ddr_top .I1 (rd_wr_fifo_empty), .I2 (record_addr_valid), .I3 (_N36), - .I4 (_N96017)); + .I4 (_N96799)); // LUT = (I3)|(~I2&I4)|(I0&I4)|(I1&I4) ; // ../../sources/designs/ddr/rd_wr_ctrl/axi_ddr_top.v:428 @@ -256092,7 +255792,7 @@ module axi_ddr_top GTP_LUT5 /* \wr_sta_fsm[3:0]_7 */ #( .INIT(32'b10000000000000000000000000000000)) \wr_sta_fsm[3:0]_7 ( - .Z (_N96017), + .Z (_N96799), .I0 (s_axi_wready), .I1 (cnt_wr_num[0]), .I2 (cnt_wr_num[1]), @@ -256108,7 +255808,7 @@ module axi_ddr_top .I1 (s_axi_awready), .I2 (s_axi_awvalid), .I3 (N984[1]), - .I4 (_N96017)); + .I4 (_N96799)); // LUT = (I0)|(~I3&I4)|(~I1&I2) ; GTP_LUT3 /* \wr_sta_fsm[3:0]_12 */ #( @@ -256321,41 +256021,41 @@ module rd0_addr_ctr wire N152; wire [2:0] N157; wire _N8; - wire _N13667; - wire _N13668; - wire _N13669; - wire _N13670; - wire _N13671; - wire _N13672; - wire _N13675; - wire _N13676; - wire _N13677; - wire _N13678; - wire _N13679; - wire _N13680; - wire _N13681; - wire _N13682; - wire _N13683; - wire _N13684; - wire _N13685; - wire _N13686; - wire _N13687; - wire _N13688; - wire _N13689; - wire _N13690; - wire _N13691; - wire _N13692; - wire _N76175; - wire _N76199; - wire _N76203; - wire _N76211; - wire _N76225; - wire _N76233; - wire _N76245; - wire _N76259; - wire _N103317; - wire _N103318; - wire _N104723; + wire _N13635; + wire _N13636; + wire _N13637; + wire _N13638; + wire _N13639; + wire _N13640; + wire _N13643; + wire _N13644; + wire _N13645; + wire _N13646; + wire _N13647; + wire _N13648; + wire _N13649; + wire _N13650; + wire _N13651; + wire _N13652; + wire _N13653; + wire _N13654; + wire _N13655; + wire _N13656; + wire _N13657; + wire _N13658; + wire _N13659; + wire _N13660; + wire _N76967; + wire _N76991; + wire _N77005; + wire _N77013; + wire _N77027; + wire _N77035; + wire _N77047; + wire _N77059; + wire _N104129; + wire _N104130; + wire _N105736; wire image_perimt; wire image_perimt0; wire image_perimt1; @@ -256378,7 +256078,7 @@ module rd0_addr_ctr GTP_LUT5 /* N20_8 */ #( .INIT(32'b10000000000000000000000000000000)) N20_8 ( - .Z (_N104723), + .Z (_N105736), .I0 (rd_ddr_done_rise), .I1 (rd_done_cnt[0]), .I2 (rd_done_cnt[1]), @@ -256394,7 +256094,7 @@ module rd0_addr_ctr .I1 (rd_done_cnt[4]), .I2 (rd_done_cnt[5]), .I3 (rd_done_cnt[6]), - .I4 (_N104723)); + .I4 (_N105736)); // LUT = I0&I1&I2&I3&I4 ; GTP_LUT5CARRY /* N56_1_1 */ #( @@ -256404,8 +256104,8 @@ module rd0_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N56_1_1 ( - .COUT (_N13667), - .Z (_N76199), + .COUT (_N13635), + .Z (_N76991), .CIN (), .I0 (rd_done_cnt[0]), .I1 (rd_done_cnt[1]), @@ -256424,9 +256124,9 @@ module rd0_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N56_1_2 ( - .COUT (_N13668), - .Z (_N76203), - .CIN (_N13667), + .COUT (_N13636), + .Z (_N77005), + .CIN (_N13635), .I0 (rd_done_cnt[0]), .I1 (rd_done_cnt[1]), .I2 (rd0_sta_reg[1]), @@ -256444,9 +256144,9 @@ module rd0_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N56_1_3 ( - .COUT (_N13669), - .Z (_N76211), - .CIN (_N13668), + .COUT (_N13637), + .Z (_N77013), + .CIN (_N13636), .I0 (), .I1 (rd_done_cnt[3]), .I2 (rd0_sta_reg[1]), @@ -256464,9 +256164,9 @@ module rd0_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N56_1_4 ( - .COUT (_N13670), - .Z (_N76225), - .CIN (_N13669), + .COUT (_N13638), + .Z (_N77027), + .CIN (_N13637), .I0 (), .I1 (rd_done_cnt[4]), .I2 (rd0_sta_reg[1]), @@ -256484,9 +256184,9 @@ module rd0_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N56_1_5 ( - .COUT (_N13671), - .Z (_N76233), - .CIN (_N13670), + .COUT (_N13639), + .Z (_N77035), + .CIN (_N13638), .I0 (), .I1 (rd_done_cnt[5]), .I2 (rd0_sta_reg[1]), @@ -256504,9 +256204,9 @@ module rd0_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N56_1_6 ( - .COUT (_N13672), - .Z (_N76245), - .CIN (_N13671), + .COUT (_N13640), + .Z (_N77047), + .CIN (_N13639), .I0 (), .I1 (rd_done_cnt[6]), .I2 (rd0_sta_reg[1]), @@ -256525,8 +256225,8 @@ module rd0_addr_ctr .I4_TO_LUT("FALSE")) N56_1_7 ( .COUT (), - .Z (_N76259), - .CIN (_N13672), + .Z (_N77059), + .CIN (_N13640), .I0 (), .I1 (rd_done_cnt[7]), .I2 (rd0_sta_reg[1]), @@ -256544,7 +256244,7 @@ module rd0_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N60_1_1 ( - .COUT (_N13675), + .COUT (_N13643), .Z (N150[9]), .CIN (), .I0 (rd_ddr_addr[10]), @@ -256564,9 +256264,9 @@ module rd0_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N60_1_2 ( - .COUT (_N13676), + .COUT (_N13644), .Z (N150[10]), - .CIN (_N13675), + .CIN (_N13643), .I0 (rd_ddr_addr[10]), .I1 (rd_ddr_addr[11]), .I2 (rd0_sta_reg[0]), @@ -256584,9 +256284,9 @@ module rd0_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N60_1_3 ( - .COUT (_N13677), + .COUT (_N13645), .Z (N150[11]), - .CIN (_N13676), + .CIN (_N13644), .I0 (), .I1 (rd_ddr_addr[13]), .I2 (rd0_sta_reg[0]), @@ -256604,9 +256304,9 @@ module rd0_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N60_1_4 ( - .COUT (_N13678), + .COUT (_N13646), .Z (N150[12]), - .CIN (_N13677), + .CIN (_N13645), .I0 (), .I1 (rd_ddr_addr[14]), .I2 (rd0_sta_reg[0]), @@ -256624,9 +256324,9 @@ module rd0_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N60_1_5 ( - .COUT (_N13679), + .COUT (_N13647), .Z (N150[13]), - .CIN (_N13678), + .CIN (_N13646), .I0 (), .I1 (rd_ddr_addr[15]), .I2 (rd0_sta_reg[0]), @@ -256644,9 +256344,9 @@ module rd0_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N60_1_6 ( - .COUT (_N13680), + .COUT (_N13648), .Z (N150[14]), - .CIN (_N13679), + .CIN (_N13647), .I0 (), .I1 (rd_ddr_addr[16]), .I2 (rd0_sta_reg[0]), @@ -256664,9 +256364,9 @@ module rd0_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N60_1_7 ( - .COUT (_N13681), + .COUT (_N13649), .Z (N150[15]), - .CIN (_N13680), + .CIN (_N13648), .I0 (), .I1 (rd_ddr_addr[17]), .I2 (rd0_sta_reg[0]), @@ -256684,9 +256384,9 @@ module rd0_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N60_1_8 ( - .COUT (_N13682), + .COUT (_N13650), .Z (N150[16]), - .CIN (_N13681), + .CIN (_N13649), .I0 (), .I1 (rd_ddr_addr[18]), .I2 (rd0_sta_reg[0]), @@ -256704,9 +256404,9 @@ module rd0_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N60_1_9 ( - .COUT (_N13683), + .COUT (_N13651), .Z (N150[17]), - .CIN (_N13682), + .CIN (_N13650), .I0 (), .I1 (rd_ddr_addr[19]), .I2 (rd0_sta_reg[0]), @@ -256724,9 +256424,9 @@ module rd0_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N60_1_10 ( - .COUT (_N13684), + .COUT (_N13652), .Z (N150[18]), - .CIN (_N13683), + .CIN (_N13651), .I0 (), .I1 (rd_ddr_addr[20]), .I2 (rd0_sta_reg[0]), @@ -256744,9 +256444,9 @@ module rd0_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N60_1_11 ( - .COUT (_N13685), + .COUT (_N13653), .Z (N150[19]), - .CIN (_N13684), + .CIN (_N13652), .I0 (), .I1 (rd_ddr_addr[21]), .I2 (rd0_sta_reg[0]), @@ -256764,9 +256464,9 @@ module rd0_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N60_1_12 ( - .COUT (_N13686), + .COUT (_N13654), .Z (N150[20]), - .CIN (_N13685), + .CIN (_N13653), .I0 (), .I1 (rd_ddr_addr[22]), .I2 (rd0_sta_reg[0]), @@ -256784,9 +256484,9 @@ module rd0_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N60_1_13 ( - .COUT (_N13687), + .COUT (_N13655), .Z (N150[21]), - .CIN (_N13686), + .CIN (_N13654), .I0 (), .I1 (rd_ddr_addr[23]), .I2 (rd0_sta_reg[0]), @@ -256804,9 +256504,9 @@ module rd0_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N60_1_14 ( - .COUT (_N13688), + .COUT (_N13656), .Z (N150[22]), - .CIN (_N13687), + .CIN (_N13655), .I0 (), .I1 (rd_ddr_addr[24]), .I2 (rd0_sta_reg[0]), @@ -256824,9 +256524,9 @@ module rd0_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N60_1_15 ( - .COUT (_N13689), + .COUT (_N13657), .Z (N150[23]), - .CIN (_N13688), + .CIN (_N13656), .I0 (), .I1 (rd_ddr_addr[25]), .I2 (rd0_sta_reg[0]), @@ -256844,9 +256544,9 @@ module rd0_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N60_1_16 ( - .COUT (_N13690), + .COUT (_N13658), .Z (N150[24]), - .CIN (_N13689), + .CIN (_N13657), .I0 (), .I1 (rd_ddr_addr[26]), .I2 (rd0_sta_reg[0]), @@ -256864,9 +256564,9 @@ module rd0_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N60_1_17 ( - .COUT (_N13691), + .COUT (_N13659), .Z (N150[25]), - .CIN (_N13690), + .CIN (_N13658), .I0 (), .I1 (rd_ddr_addr[27]), .I2 (rd0_sta_reg[0]), @@ -256884,9 +256584,9 @@ module rd0_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N60_1_18 ( - .COUT (_N13692), + .COUT (_N13660), .Z (N150[26]), - .CIN (_N13691), + .CIN (_N13659), .I0 (), .I1 (rd_ddr_addr[28]), .I2 (rd0_sta_reg[0]), @@ -256906,7 +256606,7 @@ module rd0_addr_ctr N60_1_19 ( .COUT (), .Z (N150[27]), - .CIN (_N13692), + .CIN (_N13660), .I0 (), .I1 (rd_ddr_addr[29]), .I2 (rd0_sta_reg[0]), @@ -257014,7 +256714,7 @@ module rd0_addr_ctr \rd0_sta_reg[0] ( .Q (rd0_sta_reg[0]), .CLK (clk), - .D (_N103317), + .D (_N104129), .S (rst)); // ../../sources/designs/ddr/addr_ctrl/rd0_addr_ctr.v:50 @@ -257034,14 +256734,14 @@ module rd0_addr_ctr \rd0_sta_reg[2] ( .Q (rd0_sta_reg[2]), .CLK (clk), - .D (_N103318), + .D (_N104130), .R (rst)); // ../../sources/designs/ddr/addr_ctrl/rd0_addr_ctr.v:50 GTP_LUT3 /* \rd0_sta_reg_ce_mux[0] */ #( .INIT(8'b11010000)) \rd0_sta_reg_ce_mux[0] ( - .Z (_N103317), + .Z (_N104129), .I0 (image_perimt0), .I1 (image_perimt1), .I2 (rd0_sta_reg[0])); @@ -257050,7 +256750,7 @@ module rd0_addr_ctr GTP_LUT3 /* \rd0_sta_reg_ce_mux[2] */ #( .INIT(8'b11101100)) \rd0_sta_reg_ce_mux[2] ( - .Z (_N103318), + .Z (_N104130), .I0 (N157[2]), .I1 (rd0_sta_reg[2]), .I2 (rd0_sta_reg[1])); @@ -257303,7 +257003,7 @@ module rd0_addr_ctr .Q (rd_done_cnt[0]), .CE (N131), .CLK (clk), - .D (_N76175)); + .D (_N76967)); // ../../sources/designs/ddr/addr_ctrl/rd0_addr_ctr.v:82 GTP_DFF_E /* \rd_done_cnt[1] */ #( @@ -257313,7 +257013,7 @@ module rd0_addr_ctr .Q (rd_done_cnt[1]), .CE (N131), .CLK (clk), - .D (_N76199)); + .D (_N76991)); // ../../sources/designs/ddr/addr_ctrl/rd0_addr_ctr.v:82 GTP_DFF_E /* \rd_done_cnt[2] */ #( @@ -257323,7 +257023,7 @@ module rd0_addr_ctr .Q (rd_done_cnt[2]), .CE (N131), .CLK (clk), - .D (_N76203)); + .D (_N77005)); // ../../sources/designs/ddr/addr_ctrl/rd0_addr_ctr.v:82 GTP_DFF_E /* \rd_done_cnt[3] */ #( @@ -257333,7 +257033,7 @@ module rd0_addr_ctr .Q (rd_done_cnt[3]), .CE (N131), .CLK (clk), - .D (_N76211)); + .D (_N77013)); // ../../sources/designs/ddr/addr_ctrl/rd0_addr_ctr.v:82 GTP_DFF_E /* \rd_done_cnt[4] */ #( @@ -257343,7 +257043,7 @@ module rd0_addr_ctr .Q (rd_done_cnt[4]), .CE (N131), .CLK (clk), - .D (_N76225)); + .D (_N77027)); // ../../sources/designs/ddr/addr_ctrl/rd0_addr_ctr.v:82 GTP_DFF_E /* \rd_done_cnt[5] */ #( @@ -257353,7 +257053,7 @@ module rd0_addr_ctr .Q (rd_done_cnt[5]), .CE (N131), .CLK (clk), - .D (_N76233)); + .D (_N77035)); // ../../sources/designs/ddr/addr_ctrl/rd0_addr_ctr.v:82 GTP_DFF_E /* \rd_done_cnt[6] */ #( @@ -257363,13 +257063,13 @@ module rd0_addr_ctr .Q (rd_done_cnt[6]), .CE (N131), .CLK (clk), - .D (_N76245)); + .D (_N77047)); // ../../sources/designs/ddr/addr_ctrl/rd0_addr_ctr.v:82 - GTP_LUT2 /* \rd_done_cnt[7:0]_5084 */ #( + GTP_LUT2 /* \rd_done_cnt[7:0]_5109 */ #( .INIT(4'b0010)) - \rd_done_cnt[7:0]_5084 ( - .Z (_N76175), + \rd_done_cnt[7:0]_5109 ( + .Z (_N76967), .I0 (rd0_sta_reg[1]), .I1 (rd_done_cnt[0])); // LUT = I0&~I1 ; @@ -257381,7 +257081,7 @@ module rd0_addr_ctr .Q (rd_done_cnt[7]), .CE (N131), .CLK (clk), - .D (_N76259)); + .D (_N77059)); // ../../sources/designs/ddr/addr_ctrl/rd0_addr_ctr.v:82 GTP_DFF /* \wr_image_cnt0[0] */ #( @@ -257451,22 +257151,22 @@ module ipml_fifo_ctrl_v1_3_5 wire N22; wire N24; wire [9:0] \N24.co ; - wire _N16176; - wire _N16177; - wire _N16178; - wire _N16179; - wire _N16180; - wire _N16181; - wire _N16182; - wire _N16183; - wire _N16186; - wire _N16187; - wire _N16188; - wire _N16189; - wire _N16190; - wire _N16191; - wire _N16192; - wire _N16193; + wire _N16138; + wire _N16139; + wire _N16140; + wire _N16141; + wire _N16142; + wire _N16143; + wire _N16144; + wire _N16145; + wire _N16148; + wire _N16149; + wire _N16150; + wire _N16151; + wire _N16152; + wire _N16153; + wire _N16154; + wire _N16155; wire [8:0] rbin; wire [8:0] rrptr; wire [8:0] rwptr; @@ -257485,7 +257185,7 @@ module ipml_fifo_ctrl_v1_3_5 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_1 ( - .COUT (_N16176), + .COUT (_N16138), .Z (N2[0]), .CIN (), .I0 (w_en), @@ -257505,9 +257205,9 @@ module ipml_fifo_ctrl_v1_3_5 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_2 ( - .COUT (_N16177), + .COUT (_N16139), .Z (N2[1]), - .CIN (_N16176), + .CIN (_N16138), .I0 (w_en), .I1 (waddr[0]), .I2 (waddr[1]), @@ -257525,9 +257225,9 @@ module ipml_fifo_ctrl_v1_3_5 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_3 ( - .COUT (_N16178), + .COUT (_N16140), .Z (N2[2]), - .CIN (_N16177), + .CIN (_N16139), .I0 (), .I1 (waddr[2]), .I2 (), @@ -257545,9 +257245,9 @@ module ipml_fifo_ctrl_v1_3_5 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_4 ( - .COUT (_N16179), + .COUT (_N16141), .Z (N2[3]), - .CIN (_N16178), + .CIN (_N16140), .I0 (), .I1 (waddr[3]), .I2 (), @@ -257565,9 +257265,9 @@ module ipml_fifo_ctrl_v1_3_5 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_5 ( - .COUT (_N16180), + .COUT (_N16142), .Z (N2[4]), - .CIN (_N16179), + .CIN (_N16141), .I0 (), .I1 (waddr[4]), .I2 (), @@ -257585,9 +257285,9 @@ module ipml_fifo_ctrl_v1_3_5 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_6 ( - .COUT (_N16181), + .COUT (_N16143), .Z (N2[5]), - .CIN (_N16180), + .CIN (_N16142), .I0 (), .I1 (waddr[5]), .I2 (), @@ -257605,9 +257305,9 @@ module ipml_fifo_ctrl_v1_3_5 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_7 ( - .COUT (_N16182), + .COUT (_N16144), .Z (N2[6]), - .CIN (_N16181), + .CIN (_N16143), .I0 (), .I1 (waddr[6]), .I2 (), @@ -257625,9 +257325,9 @@ module ipml_fifo_ctrl_v1_3_5 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_8 ( - .COUT (_N16183), + .COUT (_N16145), .Z (N2[7]), - .CIN (_N16182), + .CIN (_N16144), .I0 (), .I1 (waddr[7]), .I2 (), @@ -257647,7 +257347,7 @@ module ipml_fifo_ctrl_v1_3_5 N2_9 ( .COUT (), .Z (N2[8]), - .CIN (_N16183), + .CIN (_N16145), .I0 (), .I1 (wbin[8]), .I2 (), @@ -257755,7 +257455,7 @@ module ipml_fifo_ctrl_v1_3_5 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_1 ( - .COUT (_N16186), + .COUT (_N16148), .Z (N11[0]), .CIN (), .I0 (rempty), @@ -257775,9 +257475,9 @@ module ipml_fifo_ctrl_v1_3_5 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_2 ( - .COUT (_N16187), + .COUT (_N16149), .Z (N11[1]), - .CIN (_N16186), + .CIN (_N16148), .I0 (rempty), .I1 (raddr[0]), .I2 (\u_ddr_addr_ctr/u_rd1_addr_ctr/rd1_sta_reg [0] ), @@ -257795,9 +257495,9 @@ module ipml_fifo_ctrl_v1_3_5 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_3 ( - .COUT (_N16188), + .COUT (_N16150), .Z (N11[2]), - .CIN (_N16187), + .CIN (_N16149), .I0 (), .I1 (raddr[2]), .I2 (), @@ -257815,9 +257515,9 @@ module ipml_fifo_ctrl_v1_3_5 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_4 ( - .COUT (_N16189), + .COUT (_N16151), .Z (N11[3]), - .CIN (_N16188), + .CIN (_N16150), .I0 (), .I1 (raddr[3]), .I2 (), @@ -257835,9 +257535,9 @@ module ipml_fifo_ctrl_v1_3_5 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_5 ( - .COUT (_N16190), + .COUT (_N16152), .Z (N11[4]), - .CIN (_N16189), + .CIN (_N16151), .I0 (), .I1 (raddr[4]), .I2 (), @@ -257855,9 +257555,9 @@ module ipml_fifo_ctrl_v1_3_5 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_6 ( - .COUT (_N16191), + .COUT (_N16153), .Z (N11[5]), - .CIN (_N16190), + .CIN (_N16152), .I0 (), .I1 (raddr[5]), .I2 (), @@ -257875,9 +257575,9 @@ module ipml_fifo_ctrl_v1_3_5 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_7 ( - .COUT (_N16192), + .COUT (_N16154), .Z (N11[6]), - .CIN (_N16191), + .CIN (_N16153), .I0 (), .I1 (raddr[6]), .I2 (), @@ -257895,9 +257595,9 @@ module ipml_fifo_ctrl_v1_3_5 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_8 ( - .COUT (_N16193), + .COUT (_N16155), .Z (N11[7]), - .CIN (_N16192), + .CIN (_N16154), .I0 (), .I1 (raddr[7]), .I2 (), @@ -257917,7 +257617,7 @@ module ipml_fifo_ctrl_v1_3_5 N11_9 ( .COUT (), .Z (N11[8]), - .CIN (_N16193), + .CIN (_N16155), .I0 (), .I1 (rbin[8]), .I2 (), @@ -258733,16 +258433,16 @@ module rd1_addr_ctr wire _N61; wire _N67; wire _N73; - wire _N16091; - wire _N16092; - wire _N16093; - wire _N16094; - wire _N16095; - wire _N16096; - wire _N16097; - wire _N16098; - wire _N16099; - wire _N16100; + wire _N16070; + wire _N16071; + wire _N16072; + wire _N16073; + wire _N16074; + wire _N16075; + wire _N16076; + wire _N16077; + wire _N16078; + wire _N16079; wire [2:0] delay_cnt; wire [9:0] dout; wire empty; @@ -258832,7 +258532,7 @@ module rd1_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N115_1_2 ( - .COUT (_N16091), + .COUT (_N16070), .Z (N305[3]), .CIN (), .I0 (mult_h[3]), @@ -258851,9 +258551,9 @@ module rd1_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N115_1_3 ( - .COUT (_N16092), + .COUT (_N16071), .Z (N305[4]), - .CIN (_N16091), + .CIN (_N16070), .I0 (mult_h[3]), .I1 (mult_h[1]), .I2 (mult_h[4]), @@ -258870,9 +258570,9 @@ module rd1_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N115_1_4 ( - .COUT (_N16093), + .COUT (_N16072), .Z (N305[5]), - .CIN (_N16092), + .CIN (_N16071), .I0 (), .I1 (mult_h[5]), .I2 (mult_h[3]), @@ -258889,9 +258589,9 @@ module rd1_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N115_1_5 ( - .COUT (_N16094), + .COUT (_N16073), .Z (N305[6]), - .CIN (_N16093), + .CIN (_N16072), .I0 (), .I1 (mult_h[6]), .I2 (mult_h[4]), @@ -258908,9 +258608,9 @@ module rd1_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N115_1_6 ( - .COUT (_N16095), + .COUT (_N16074), .Z (N305[7]), - .CIN (_N16094), + .CIN (_N16073), .I0 (), .I1 (mult_h[7]), .I2 (mult_h[5]), @@ -258927,9 +258627,9 @@ module rd1_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N115_1_7 ( - .COUT (_N16096), + .COUT (_N16075), .Z (N305[8]), - .CIN (_N16095), + .CIN (_N16074), .I0 (), .I1 (mult_h[8]), .I2 (mult_h[6]), @@ -258946,9 +258646,9 @@ module rd1_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N115_1_8 ( - .COUT (_N16097), + .COUT (_N16076), .Z (N305[9]), - .CIN (_N16096), + .CIN (_N16075), .I0 (), .I1 (mult_h[9]), .I2 (mult_h[7]), @@ -258965,9 +258665,9 @@ module rd1_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N115_1_9 ( - .COUT (_N16098), + .COUT (_N16077), .Z (N305[10]), - .CIN (_N16097), + .CIN (_N16076), .I0 (), .I1 (mult_h[10]), .I2 (mult_h[8]), @@ -258984,9 +258684,9 @@ module rd1_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N115_1_10 ( - .COUT (_N16099), + .COUT (_N16078), .Z (N305[11]), - .CIN (_N16098), + .CIN (_N16077), .I0 (), .I1 (mult_h[9]), .I2 (), @@ -259003,9 +258703,9 @@ module rd1_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N115_1_11 ( - .COUT (_N16100), + .COUT (_N16079), .Z (N305[12]), - .CIN (_N16099), + .CIN (_N16078), .I0 (), .I1 (mult_h[10]), .I2 (), @@ -259024,7 +258724,7 @@ module rd1_addr_ctr N115_1_12 ( .COUT (), .Z (N305[13]), - .CIN (_N16100), + .CIN (_N16079), .I0 (), .I1 (), .I2 (), @@ -260058,25 +259758,33 @@ module rd3_addr_ctr wire [29:0] N93; wire [29:0] N94; wire [13:0] N108; - wire _N9428; - wire _N9446; - wire _N14441; - wire _N14442; - wire _N14443; - wire _N14444; - wire _N14445; - wire _N14446; - wire _N14447; - wire _N14448; - wire _N14449; - wire _N14450; - wire _N14451; - wire _N14452; - wire _N14453; - wire _N14454; - wire _N16155; - wire _N16156; - wire _N16157; + wire _N9458; + wire _N9476; + wire _N15089; + wire _N15090; + wire _N15091; + wire _N15092; + wire _N15093; + wire _N15094; + wire _N15095; + wire _N15096; + wire _N15097; + wire _N15098; + wire _N15099; + wire _N15100; + wire _N15101; + wire _N15102; + wire _N16117; + wire _N16118; + wire _N16119; + wire _N16120; + wire _N16121; + wire _N16122; + wire _N16123; + wire _N16124; + wire _N16125; + wire _N16126; + wire _N16127; wire _N16158; wire _N16159; wire _N16160; @@ -260085,23 +259793,15 @@ module rd3_addr_ctr wire _N16163; wire _N16164; wire _N16165; - wire _N16208; - wire _N16209; - wire _N16210; - wire _N16211; - wire _N16212; - wire _N16213; - wire _N16214; - wire _N16215; - wire _N16216; - wire _N16217; - wire _N16218; - wire _N16219; - wire _N16220; - wire _N16221; - wire _N16222; - wire _N103485; - wire _N103486; + wire _N16166; + wire _N16167; + wire _N16168; + wire _N16169; + wire _N16170; + wire _N16171; + wire _N16172; + wire _N104297; + wire _N104298; wire [10:0] act_h; wire [10:0] act_w; wire [10:0] act_w0; @@ -260176,7 +259876,7 @@ module rd3_addr_ctr GTP_LUT4 /* N34_mux3_3 */ #( .INIT(16'b0001111111111111)) N34_mux3_3 ( - .Z (_N9428), + .Z (_N9458), .I0 (image_h0[3]), .I1 (image_h0[4]), .I2 (image_h0[5]), @@ -260187,7 +259887,7 @@ module rd3_addr_ctr .INIT(32'b00000000000000000000000000101111)) N34_mux7_3 ( .Z (N34), - .I0 (_N9428), + .I0 (_N9458), .I1 (image_h0[7]), .I2 (image_h0[8]), .I3 (image_h0[9]), @@ -260197,7 +259897,7 @@ module rd3_addr_ctr GTP_LUT5 /* N44_mux4 */ #( .INIT(32'b00000000000000000001111111111111)) N44_mux4 ( - .Z (_N9446), + .Z (_N9476), .I0 (image_h1[3]), .I1 (image_h1[4]), .I2 (image_h1[5]), @@ -260209,7 +259909,7 @@ module rd3_addr_ctr .INIT(16'b0000000000001011)) N44_mux7_3 ( .Z (N44), - .I0 (_N9446), + .I0 (_N9476), .I1 (image_h1[8]), .I2 (image_h1[9]), .I3 (image_h1[10])); @@ -260230,7 +259930,7 @@ module rd3_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N56_1_1 ( - .COUT (_N16155), + .COUT (_N16117), .Z (N108[2]), .CIN (), .I0 (act_h[2]), @@ -260249,9 +259949,9 @@ module rd3_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N56_1_2 ( - .COUT (_N16156), + .COUT (_N16118), .Z (N108[3]), - .CIN (_N16155), + .CIN (_N16117), .I0 (act_h[2]), .I1 (act_h[0]), .I2 (act_h[3]), @@ -260268,9 +259968,9 @@ module rd3_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N56_1_3 ( - .COUT (_N16157), + .COUT (_N16119), .Z (N108[4]), - .CIN (_N16156), + .CIN (_N16118), .I0 (), .I1 (act_h[4]), .I2 (act_h[2]), @@ -260287,9 +259987,9 @@ module rd3_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N56_1_4 ( - .COUT (_N16158), + .COUT (_N16120), .Z (N108[5]), - .CIN (_N16157), + .CIN (_N16119), .I0 (), .I1 (act_h[5]), .I2 (act_h[3]), @@ -260306,9 +260006,9 @@ module rd3_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N56_1_5 ( - .COUT (_N16159), + .COUT (_N16121), .Z (N108[6]), - .CIN (_N16158), + .CIN (_N16120), .I0 (), .I1 (act_h[6]), .I2 (act_h[4]), @@ -260325,9 +260025,9 @@ module rd3_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N56_1_6 ( - .COUT (_N16160), + .COUT (_N16122), .Z (N108[7]), - .CIN (_N16159), + .CIN (_N16121), .I0 (), .I1 (act_h[7]), .I2 (act_h[5]), @@ -260344,9 +260044,9 @@ module rd3_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N56_1_7 ( - .COUT (_N16161), + .COUT (_N16123), .Z (N108[8]), - .CIN (_N16160), + .CIN (_N16122), .I0 (), .I1 (act_h[8]), .I2 (act_h[6]), @@ -260363,9 +260063,9 @@ module rd3_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N56_1_8 ( - .COUT (_N16162), + .COUT (_N16124), .Z (N108[9]), - .CIN (_N16161), + .CIN (_N16123), .I0 (), .I1 (act_h[9]), .I2 (act_h[7]), @@ -260382,9 +260082,9 @@ module rd3_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N56_1_9 ( - .COUT (_N16163), + .COUT (_N16125), .Z (N108[10]), - .CIN (_N16162), + .CIN (_N16124), .I0 (), .I1 (act_h[10]), .I2 (act_h[8]), @@ -260401,9 +260101,9 @@ module rd3_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N56_1_10 ( - .COUT (_N16164), + .COUT (_N16126), .Z (N108[11]), - .CIN (_N16163), + .CIN (_N16125), .I0 (), .I1 (act_h[9]), .I2 (), @@ -260420,9 +260120,9 @@ module rd3_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N56_1_11 ( - .COUT (_N16165), + .COUT (_N16127), .Z (N108[12]), - .CIN (_N16164), + .CIN (_N16126), .I0 (), .I1 (act_h[10]), .I2 (), @@ -260441,7 +260141,7 @@ module rd3_addr_ctr N56_1_12 ( .COUT (), .Z (N108[13]), - .CIN (_N16165), + .CIN (_N16127), .I0 (), .I1 (), .I2 (), @@ -260458,7 +260158,7 @@ module rd3_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_1_1 ( - .COUT (_N16208), + .COUT (_N16158), .Z (N94[8]), .CIN (), .I0 (act_w0[7]), @@ -260478,9 +260178,9 @@ module rd3_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_1_2 ( - .COUT (_N16209), + .COUT (_N16159), .Z (N94[9]), - .CIN (_N16208), + .CIN (_N16158), .I0 (act_w0[7]), .I1 (now_image_addr0[8]), .I2 (act_w0[8]), @@ -260498,9 +260198,9 @@ module rd3_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_1_3 ( - .COUT (_N16210), + .COUT (_N16160), .Z (N94[10]), - .CIN (_N16209), + .CIN (_N16159), .I0 (), .I1 (act_w0[9]), .I2 (now_image_addr0[10]), @@ -260518,9 +260218,9 @@ module rd3_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_1_4 ( - .COUT (_N16211), + .COUT (_N16161), .Z (N94[11]), - .CIN (_N16210), + .CIN (_N16160), .I0 (), .I1 (act_w0[10]), .I2 (now_image_addr0[11]), @@ -260538,9 +260238,9 @@ module rd3_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_1_5 ( - .COUT (_N16212), + .COUT (_N16162), .Z (N94[12]), - .CIN (_N16211), + .CIN (_N16161), .I0 (), .I1 (now_image_addr0[12]), .I2 (), @@ -260558,9 +260258,9 @@ module rd3_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_1_6 ( - .COUT (_N16213), + .COUT (_N16163), .Z (N94[13]), - .CIN (_N16212), + .CIN (_N16162), .I0 (), .I1 (now_image_addr0[13]), .I2 (), @@ -260578,9 +260278,9 @@ module rd3_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_1_7 ( - .COUT (_N16214), + .COUT (_N16164), .Z (N94[14]), - .CIN (_N16213), + .CIN (_N16163), .I0 (), .I1 (now_image_addr0[14]), .I2 (), @@ -260598,9 +260298,9 @@ module rd3_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_1_8 ( - .COUT (_N16215), + .COUT (_N16165), .Z (N94[15]), - .CIN (_N16214), + .CIN (_N16164), .I0 (), .I1 (now_image_addr0[15]), .I2 (), @@ -260618,9 +260318,9 @@ module rd3_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_1_9 ( - .COUT (_N16216), + .COUT (_N16166), .Z (N94[16]), - .CIN (_N16215), + .CIN (_N16165), .I0 (), .I1 (now_image_addr0[16]), .I2 (), @@ -260638,9 +260338,9 @@ module rd3_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_1_10 ( - .COUT (_N16217), + .COUT (_N16167), .Z (N94[17]), - .CIN (_N16216), + .CIN (_N16166), .I0 (), .I1 (now_image_addr0[17]), .I2 (), @@ -260658,9 +260358,9 @@ module rd3_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_1_11 ( - .COUT (_N16218), + .COUT (_N16168), .Z (N94[18]), - .CIN (_N16217), + .CIN (_N16167), .I0 (), .I1 (now_image_addr0[18]), .I2 (), @@ -260678,9 +260378,9 @@ module rd3_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_1_12 ( - .COUT (_N16219), + .COUT (_N16169), .Z (N94[19]), - .CIN (_N16218), + .CIN (_N16168), .I0 (), .I1 (now_image_addr0[19]), .I2 (), @@ -260698,9 +260398,9 @@ module rd3_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_1_13 ( - .COUT (_N16220), + .COUT (_N16170), .Z (N94[20]), - .CIN (_N16219), + .CIN (_N16169), .I0 (), .I1 (now_image_addr0[20]), .I2 (), @@ -260718,9 +260418,9 @@ module rd3_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_1_14 ( - .COUT (_N16221), + .COUT (_N16171), .Z (N94[21]), - .CIN (_N16220), + .CIN (_N16170), .I0 (), .I1 (now_image_addr0[21]), .I2 (), @@ -260738,9 +260438,9 @@ module rd3_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N74_1_15 ( - .COUT (_N16222), + .COUT (_N16172), .Z (N94[22]), - .CIN (_N16221), + .CIN (_N16171), .I0 (), .I1 (now_image_addr0[22]), .I2 (), @@ -260760,7 +260460,7 @@ module rd3_addr_ctr N74_1_16 ( .COUT (), .Z (N94[23]), - .CIN (_N16222), + .CIN (_N16172), .I0 (), .I1 (), .I2 (), @@ -260778,7 +260478,7 @@ module rd3_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N75_2_1 ( - .COUT (_N14441), + .COUT (_N15089), .Z (N75[12]), .CIN (), .I0 (now_image_addr1[12]), @@ -260798,9 +260498,9 @@ module rd3_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N75_2_2 ( - .COUT (_N14442), + .COUT (_N15090), .Z (N75[13]), - .CIN (_N14441), + .CIN (_N15089), .I0 (now_image_addr1[12]), .I1 (gen_start_addr3[12]), .I2 (now_image_addr1[13]), @@ -260818,9 +260518,9 @@ module rd3_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N75_2_3 ( - .COUT (_N14443), + .COUT (_N15091), .Z (N75[14]), - .CIN (_N14442), + .CIN (_N15090), .I0 (), .I1 (now_image_addr1[14]), .I2 (), @@ -260838,9 +260538,9 @@ module rd3_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N75_2_4 ( - .COUT (_N14444), + .COUT (_N15092), .Z (N75[15]), - .CIN (_N14443), + .CIN (_N15091), .I0 (), .I1 (now_image_addr1[15]), .I2 (), @@ -260858,9 +260558,9 @@ module rd3_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N75_2_5 ( - .COUT (_N14445), + .COUT (_N15093), .Z (N75[16]), - .CIN (_N14444), + .CIN (_N15092), .I0 (), .I1 (now_image_addr1[16]), .I2 (), @@ -260878,9 +260578,9 @@ module rd3_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N75_2_6 ( - .COUT (_N14446), + .COUT (_N15094), .Z (N75[17]), - .CIN (_N14445), + .CIN (_N15093), .I0 (), .I1 (now_image_addr1[17]), .I2 (gen_start_addr3[12]), @@ -260898,9 +260598,9 @@ module rd3_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N75_2_7 ( - .COUT (_N14447), + .COUT (_N15095), .Z (N75[18]), - .CIN (_N14446), + .CIN (_N15094), .I0 (), .I1 (now_image_addr1[18]), .I2 (gen_start_addr3[12]), @@ -260918,9 +260618,9 @@ module rd3_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N75_2_8 ( - .COUT (_N14448), + .COUT (_N15096), .Z (N75[19]), - .CIN (_N14447), + .CIN (_N15095), .I0 (), .I1 (now_image_addr1[19]), .I2 (gen_start_addr3[12]), @@ -260938,9 +260638,9 @@ module rd3_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N75_2_9 ( - .COUT (_N14449), + .COUT (_N15097), .Z (N75[20]), - .CIN (_N14448), + .CIN (_N15096), .I0 (), .I1 (now_image_addr1[20]), .I2 (), @@ -260958,9 +260658,9 @@ module rd3_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N75_2_10 ( - .COUT (_N14450), + .COUT (_N15098), .Z (N75[21]), - .CIN (_N14449), + .CIN (_N15097), .I0 (), .I1 (now_image_addr1[21]), .I2 (gen_start_addr3[21]), @@ -260978,9 +260678,9 @@ module rd3_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N75_2_11 ( - .COUT (_N14451), + .COUT (_N15099), .Z (N75[22]), - .CIN (_N14450), + .CIN (_N15098), .I0 (), .I1 (now_image_addr1[22]), .I2 (gen_start_addr3[22]), @@ -260998,9 +260698,9 @@ module rd3_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N75_2_12 ( - .COUT (_N14452), + .COUT (_N15100), .Z (N75[23]), - .CIN (_N14451), + .CIN (_N15099), .I0 (), .I1 (now_image_addr1[23]), .I2 (gen_start_addr3[23]), @@ -261018,9 +260718,9 @@ module rd3_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N75_2_13 ( - .COUT (_N14453), + .COUT (_N15101), .Z (N75[24]), - .CIN (_N14452), + .CIN (_N15100), .I0 (), .I1 (gen_start_addr3[24]), .I2 (), @@ -261038,9 +260738,9 @@ module rd3_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N75_2_14 ( - .COUT (_N14454), + .COUT (_N15102), .Z (N75[25]), - .CIN (_N14453), + .CIN (_N15101), .I0 (), .I1 (gen_start_addr3[25]), .I2 (), @@ -261060,7 +260760,7 @@ module rd3_addr_ctr N75_2_15 ( .COUT (), .Z (N75[26]), - .CIN (_N14454), + .CIN (_N15102), .I0 (), .I1 (), .I2 (), @@ -262318,7 +262018,7 @@ module rd3_addr_ctr \now_image_addr0[8] ( .Q (now_image_addr0[8]), .CLK (clk), - .D (_N103485)); + .D (_N104297)); // ../../sources/designs/ddr/addr_ctrl/rd3_addr_ctr.v:66 GTP_DFF /* \now_image_addr0[9] */ #( @@ -262444,13 +262144,13 @@ module rd3_addr_ctr \now_image_addr0[22] ( .Q (now_image_addr0[22]), .CLK (clk), - .D (_N103486)); + .D (_N104298)); // ../../sources/designs/ddr/addr_ctrl/rd3_addr_ctr.v:66 GTP_LUT2 /* \now_image_addr0_rs_mux[8] */ #( .INIT(4'b0100)) \now_image_addr0_rs_mux[8] ( - .Z (_N103485), + .Z (_N104297), .I0 (N44), .I1 (act_h[0])); // LUT = ~I0&I1 ; @@ -262458,7 +262158,7 @@ module rd3_addr_ctr GTP_LUT2 /* \now_image_addr0_rs_mux[22] */ #( .INIT(4'b1000)) \now_image_addr0_rs_mux[22] ( - .Z (_N103486), + .Z (_N104298), .I0 (N44), .I1 (N108[13])); // LUT = I0&I1 ; @@ -262889,8 +262589,8 @@ module wr0_addr_ctr wire _N24; wire _N30; wire _N33; - wire _N103319; - wire _N103320; + wire _N104131; + wire _N104132; wire [3:0] delay_cnt; wire wr_ddr_done0; wire wr_ddr_done1; @@ -263118,14 +262818,14 @@ module wr0_addr_ctr wr_addr_valid0 ( .Q (wr_addr_valid), .CLK (clk), - .D (_N103320), + .D (_N104132), .R (rst)); // ../../sources/designs/ddr/addr_ctrl/wr0_addr_ctr.v:67 GTP_LUT5 /* wr_addr_valid0_ce_mux */ #( .INIT(32'b10101010101010101111110000000000)) wr_addr_valid0_ce_mux ( - .Z (_N103320), + .Z (_N104132), .I0 (wr_addr_valid), .I1 (delay_cnt[2]), .I2 (delay_cnt[3]), @@ -263314,7 +263014,7 @@ module wr0_addr_ctr wr_vs_flag_vname ( .Q (wr_vs_flag), .CLK (clk), - .D (_N103319), + .D (_N104131), .R (rst)); // defparam wr_vs_flag_vname.orig_name = wr_vs_flag; // ../../sources/designs/ddr/addr_ctrl/wr0_addr_ctr.v:67 @@ -263322,7 +263022,7 @@ module wr0_addr_ctr GTP_LUT5 /* wr_vs_flag_ce_mux */ #( .INIT(32'b00000000000000001111001011110000)) wr_vs_flag_ce_mux ( - .Z (_N103319), + .Z (_N104131), .I0 (wr_vs1), .I1 (wr_vs2), .I2 (wr_vs_flag), @@ -263640,8 +263340,8 @@ module wr1_addr_ctr wire _N4; wire _N10; wire _N13; - wire _N103309; - wire _N103310; + wire _N104121; + wire _N104122; wire [3:0] delay_cnt; wire [4:0] image_fram_cnt0; wire [4:0] image_fram_cnt1; @@ -263869,13 +263569,13 @@ module wr1_addr_ctr wr_addr_valid0 ( .Q (wr_addr_valid), .CLK (clk), - .D (_N103309)); + .D (_N104121)); // ../../sources/designs/ddr/addr_ctrl/wr1_addr_ctr.v:82 GTP_LUT5 /* wr_addr_valid0_ce_mux */ #( .INIT(32'b10111011101110001000100010001000)) wr_addr_valid0_ce_mux ( - .Z (_N103309), + .Z (_N104121), .I0 (wr_addr_valid), .I1 (rst), .I2 (delay_cnt[2]), @@ -264064,7 +263764,7 @@ module wr1_addr_ctr wr_vs_flag_vname ( .Q (wr_vs_flag), .CLK (clk), - .D (_N103310), + .D (_N104122), .R (rst)); // defparam wr_vs_flag_vname.orig_name = wr_vs_flag; // ../../sources/designs/ddr/addr_ctrl/wr1_addr_ctr.v:82 @@ -264072,7 +263772,7 @@ module wr1_addr_ctr GTP_LUT5 /* wr_vs_flag_ce_mux */ #( .INIT(32'b00000000000000001111001011110000)) wr_vs_flag_ce_mux ( - .Z (_N103310), + .Z (_N104122), .I0 (wr_vs1), .I1 (wr_vs2), .I2 (wr_vs_flag), @@ -264103,8 +263803,8 @@ module wr3_addr_ctr wire _N3; wire _N9; wire _N12; - wire _N84166; - wire _N103321; + wire _N85000; + wire _N104133; wire [3:0] delay_cnt; wire wr_ddr_done0; wire wr_ddr_done1; @@ -264294,13 +263994,13 @@ module wr3_addr_ctr wr_addr_valid0 ( .Q (wr_addr_valid), .CLK (clk), - .D (_N103321)); + .D (_N104133)); // ../../sources/designs/ddr/addr_ctrl/wr3_addr_ctr.v:66 GTP_LUT4 /* wr_addr_valid0_ce_mux */ #( .INIT(16'b1100110111001000)) wr_addr_valid0_ce_mux ( - .Z (_N103321), + .Z (_N104133), .I0 (rst), .I1 (wr_addr_valid), .I2 (wr_sta_reg[0]), @@ -264394,7 +264094,7 @@ module wr3_addr_ctr .INIT(32'b11001100110011111100110011001110)) \wr_sta_fsm[1:0]_13 ( .Z (_N9), - .I0 (_N84166), + .I0 (_N85000), .I1 (N73), .I2 (delay_cnt[2]), .I3 (delay_cnt[3]), @@ -264404,7 +264104,7 @@ module wr3_addr_ctr GTP_LUT3 /* \wr_sta_fsm[1:0]_16 */ #( .INIT(8'b00000010)) \wr_sta_fsm[1:0]_16 ( - .Z (_N84166), + .Z (_N85000), .I0 (wr_vs1), .I1 (wr_vs2), .I2 (wr_sta[1])); @@ -264522,36 +264222,33 @@ module ddr_addr_ctr output wr3_addr_valid ); wire [31:0] N7; - wire N69; - wire N73; - wire _N13645; - wire _N13646; - wire _N13647; - wire _N13648; - wire _N13649; - wire _N13650; - wire _N13651; - wire _N13652; - wire _N13653; - wire _N13654; - wire _N13655; - wire _N13656; - wire _N13657; - wire _N13658; - wire _N13659; - wire _N13660; - wire _N13661; - wire _N13662; - wire _N13663; - wire _N13664; - wire _N103316; - wire _N103666; - wire _N103670; - wire _N103674; - wire _N103678; - wire _N103682; + wire N51; + wire N72; + wire N76; + wire _N15997; + wire _N15998; + wire _N15999; + wire _N16000; + wire _N16001; + wire _N16002; + wire _N16003; + wire _N16004; + wire _N16005; + wire _N16006; + wire _N16007; + wire _N16008; + wire _N16009; + wire _N16010; + wire _N16011; + wire _N16012; + wire _N16013; + wire _N16014; + wire _N104128; + wire _N104489; + wire _N104493; + wire _N104497; + wire _N104498; wire [31:0] clk_cnt; - wire \clk_cnt[0]_inv ; wire rd1_vs0; wire [4:0] \u_rd0_addr_ctr/wr_image_cnt0 ; wire vs_15hz; @@ -264671,7 +264368,7 @@ module ddr_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N7_1_1 ( - .COUT (_N13645), + .COUT (_N15997), .Z (N7[1]), .CIN (), .I0 (clk_cnt[0]), @@ -264691,9 +264388,9 @@ module ddr_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N7_1_2 ( - .COUT (_N13646), + .COUT (_N15998), .Z (N7[2]), - .CIN (_N13645), + .CIN (_N15997), .I0 (clk_cnt[0]), .I1 (clk_cnt[1]), .I2 (clk_cnt[2]), @@ -264711,9 +264408,9 @@ module ddr_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N7_1_3 ( - .COUT (_N13647), + .COUT (_N15999), .Z (N7[3]), - .CIN (_N13646), + .CIN (_N15998), .I0 (), .I1 (clk_cnt[3]), .I2 (), @@ -264731,9 +264428,9 @@ module ddr_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N7_1_4 ( - .COUT (_N13648), + .COUT (_N16000), .Z (N7[4]), - .CIN (_N13647), + .CIN (_N15999), .I0 (), .I1 (clk_cnt[4]), .I2 (), @@ -264751,9 +264448,9 @@ module ddr_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N7_1_5 ( - .COUT (_N13649), + .COUT (_N16001), .Z (N7[5]), - .CIN (_N13648), + .CIN (_N16000), .I0 (), .I1 (clk_cnt[5]), .I2 (), @@ -264771,9 +264468,9 @@ module ddr_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N7_1_6 ( - .COUT (_N13650), + .COUT (_N16002), .Z (N7[6]), - .CIN (_N13649), + .CIN (_N16001), .I0 (), .I1 (clk_cnt[6]), .I2 (), @@ -264791,9 +264488,9 @@ module ddr_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N7_1_7 ( - .COUT (_N13651), + .COUT (_N16003), .Z (N7[7]), - .CIN (_N13650), + .CIN (_N16002), .I0 (), .I1 (clk_cnt[7]), .I2 (), @@ -264811,9 +264508,9 @@ module ddr_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N7_1_8 ( - .COUT (_N13652), + .COUT (_N16004), .Z (N7[8]), - .CIN (_N13651), + .CIN (_N16003), .I0 (), .I1 (clk_cnt[8]), .I2 (), @@ -264831,9 +264528,9 @@ module ddr_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N7_1_9 ( - .COUT (_N13653), + .COUT (_N16005), .Z (N7[9]), - .CIN (_N13652), + .CIN (_N16004), .I0 (), .I1 (clk_cnt[9]), .I2 (), @@ -264851,9 +264548,9 @@ module ddr_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N7_1_10 ( - .COUT (_N13654), + .COUT (_N16006), .Z (N7[10]), - .CIN (_N13653), + .CIN (_N16005), .I0 (), .I1 (clk_cnt[10]), .I2 (), @@ -264871,9 +264568,9 @@ module ddr_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N7_1_11 ( - .COUT (_N13655), + .COUT (_N16007), .Z (N7[11]), - .CIN (_N13654), + .CIN (_N16006), .I0 (), .I1 (clk_cnt[11]), .I2 (), @@ -264891,9 +264588,9 @@ module ddr_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N7_1_12 ( - .COUT (_N13656), + .COUT (_N16008), .Z (N7[12]), - .CIN (_N13655), + .CIN (_N16007), .I0 (), .I1 (clk_cnt[12]), .I2 (), @@ -264911,9 +264608,9 @@ module ddr_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N7_1_13 ( - .COUT (_N13657), + .COUT (_N16009), .Z (N7[13]), - .CIN (_N13656), + .CIN (_N16008), .I0 (), .I1 (clk_cnt[13]), .I2 (), @@ -264931,9 +264628,9 @@ module ddr_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N7_1_14 ( - .COUT (_N13658), + .COUT (_N16010), .Z (N7[14]), - .CIN (_N13657), + .CIN (_N16009), .I0 (), .I1 (clk_cnt[14]), .I2 (), @@ -264951,9 +264648,9 @@ module ddr_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N7_1_15 ( - .COUT (_N13659), + .COUT (_N16011), .Z (N7[15]), - .CIN (_N13658), + .CIN (_N16010), .I0 (), .I1 (clk_cnt[15]), .I2 (), @@ -264971,9 +264668,9 @@ module ddr_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N7_1_16 ( - .COUT (_N13660), + .COUT (_N16012), .Z (N7[16]), - .CIN (_N13659), + .CIN (_N16011), .I0 (), .I1 (clk_cnt[16]), .I2 (), @@ -264991,9 +264688,9 @@ module ddr_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N7_1_17 ( - .COUT (_N13661), + .COUT (_N16013), .Z (N7[17]), - .CIN (_N13660), + .CIN (_N16012), .I0 (), .I1 (clk_cnt[17]), .I2 (), @@ -265011,9 +264708,9 @@ module ddr_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N7_1_18 ( - .COUT (_N13662), + .COUT (_N16014), .Z (N7[18]), - .CIN (_N13661), + .CIN (_N16013), .I0 (), .I1 (clk_cnt[18]), .I2 (), @@ -265031,9 +264728,9 @@ module ddr_addr_ctr .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N7_1_19 ( - .COUT (_N13663), + .COUT (), .Z (N7[19]), - .CIN (_N13662), + .CIN (_N16014), .I0 (), .I1 (clk_cnt[19]), .I2 (), @@ -265044,116 +264741,75 @@ module ddr_addr_ctr // CARRY = (I1) ? CIN : (I4) ; // ../../sources/designs/ddr/addr_ctrl/ddr_addr_ctr.v:99 - GTP_LUT5CARRY /* N7_1_20 */ #( - .INIT(32'b01100110011001101100110011001100), - .ID_TO_LUT("FALSE"), - .CIN_TO_LUT("TRUE"), - .I4_TO_CARRY("TRUE"), - .I4_TO_LUT("FALSE")) - N7_1_20 ( - .COUT (_N13664), - .Z (N7[20]), - .CIN (_N13663), - .I0 (), - .I1 (clk_cnt[20]), - .I2 (), - .I3 (), - .I4 (1'b0), - .ID ()); - // LUT = I1^CIN ; - // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/ddr/addr_ctrl/ddr_addr_ctr.v:99 - - GTP_LUT5CARRY /* N7_1_21 */ #( - .INIT(32'b01100110011001101100110011001100), - .ID_TO_LUT("FALSE"), - .CIN_TO_LUT("TRUE"), - .I4_TO_CARRY("TRUE"), - .I4_TO_LUT("FALSE")) - N7_1_21 ( - .COUT (), - .Z (N7[21]), - .CIN (_N13664), - .I0 (), - .I1 (clk_cnt[21]), - .I2 (), - .I3 (), - .I4 (1'b0), - .ID ()); - // LUT = I1^CIN ; - // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/ddr/addr_ctrl/ddr_addr_ctr.v:99 - - GTP_LUT2 /* N69_2 */ #( - .INIT(4'b0001)) - N69_2 ( - .Z (_N103666), - .I0 (clk_cnt[3]), - .I1 (clk_cnt[4])); - // LUT = ~I0&~I1 ; + GTP_LUT1 /* N51 */ #( + .INIT(2'b01)) + N51_vname ( + .Z (N51), + .I0 (clk_cnt[0])); + // defparam N51_vname.orig_name = N51; + // LUT = ~I0 ; - GTP_LUT5 /* N69_6 */ #( - .INIT(32'b00000000000000000000000000000001)) - N69_6 ( - .Z (_N103670), - .I0 (clk_cnt[5]), - .I1 (clk_cnt[6]), - .I2 (clk_cnt[7]), - .I3 (clk_cnt[12]), - .I4 (clk_cnt[14])); - // LUT = ~I0&~I1&~I2&~I3&~I4 ; + GTP_LUT5 /* N72_8 */ #( + .INIT(32'b00000000000000000000000000000010)) + N72_8 ( + .Z (_N104489), + .I0 (clk_cnt[2]), + .I1 (clk_cnt[11]), + .I2 (clk_cnt[14]), + .I3 (clk_cnt[16]), + .I4 (clk_cnt[17])); + // LUT = I0&~I1&~I2&~I3&~I4 ; - GTP_LUT5 /* N69_10 */ #( - .INIT(32'b00000000000000001000000000000000)) - N69_10 ( - .Z (_N103674), - .I0 (clk_cnt[1]), - .I1 (clk_cnt[2]), + GTP_LUT5 /* N72_12 */ #( + .INIT(32'b10000000000000000000000000000000)) + N72_12 ( + .Z (_N104493), + .I0 (clk_cnt[4]), + .I1 (clk_cnt[5]), .I2 (clk_cnt[8]), .I3 (clk_cnt[9]), - .I4 (clk_cnt[20])); - // LUT = I0&I1&I2&I3&~I4 ; + .I4 (clk_cnt[10])); + // LUT = I0&I1&I2&I3&I4 ; - GTP_LUT5 /* N69_14 */ #( + GTP_LUT5 /* N72_16 */ #( .INIT(32'b10000000000000000000000000000000)) - N69_14 ( - .Z (_N103678), - .I0 (clk_cnt[10]), - .I1 (clk_cnt[11]), - .I2 (clk_cnt[13]), - .I3 (clk_cnt[15]), - .I4 (clk_cnt[16])); + N72_16 ( + .Z (_N104497), + .I0 (clk_cnt[12]), + .I1 (clk_cnt[13]), + .I2 (clk_cnt[15]), + .I3 (clk_cnt[18]), + .I4 (clk_cnt[19])); // LUT = I0&I1&I2&I3&I4 ; - GTP_LUT5 /* N69_18 */ #( - .INIT(32'b10000000000000000000000000000000)) - N69_18 ( - .Z (_N103682), + GTP_LUT5 /* N72_17 */ #( + .INIT(32'b00000000000000000000000000000001)) + N72_17 ( + .Z (_N104498), .I0 (clk_cnt[0]), - .I1 (clk_cnt[17]), - .I2 (clk_cnt[18]), - .I3 (clk_cnt[19]), - .I4 (clk_cnt[21])); - // LUT = I0&I1&I2&I3&I4 ; + .I1 (clk_cnt[1]), + .I2 (clk_cnt[3]), + .I3 (clk_cnt[6]), + .I4 (clk_cnt[7])); + // LUT = ~I0&~I1&~I2&~I3&~I4 ; - GTP_LUT5 /* N69_22 */ #( - .INIT(32'b10000000000000000000000000000000)) - N69_22 ( - .Z (N69), - .I0 (_N103666), - .I1 (_N103670), - .I2 (_N103674), - .I3 (_N103678), - .I4 (_N103682)); - // LUT = I0&I1&I2&I3&I4 ; + GTP_LUT4 /* N72_20 */ #( + .INIT(16'b1000000000000000)) + N72_20 ( + .Z (N72), + .I0 (_N104489), + .I1 (_N104493), + .I2 (_N104497), + .I3 (_N104498)); + // LUT = I0&I1&I2&I3 ; - GTP_LUT3 /* N73_5 */ #( + GTP_LUT3 /* N76_5 */ #( .INIT(8'b11111101)) - N73_5 ( - .Z (N73), + N76_5 ( + .Z (N76), .I0 (init_calib_complete), .I1 (rd0_rst), - .I2 (N69)); + .I2 (N72)); // LUT = (~I0)|(I1)|(I2) ; GTP_DFF_R /* \clk_cnt[0] */ #( @@ -265162,8 +264818,8 @@ module ddr_addr_ctr \clk_cnt[0] ( .Q (clk_cnt[0]), .CLK (clk), - .D (\clk_cnt[0]_inv ), - .R (N73)); + .D (N51), + .R (N76)); // ../../sources/designs/ddr/addr_ctrl/ddr_addr_ctr.v:95 GTP_DFF_R /* \clk_cnt[1] */ #( @@ -265173,7 +264829,7 @@ module ddr_addr_ctr .Q (clk_cnt[1]), .CLK (clk), .D (N7[1]), - .R (N73)); + .R (N76)); // ../../sources/designs/ddr/addr_ctrl/ddr_addr_ctr.v:95 GTP_DFF_R /* \clk_cnt[2] */ #( @@ -265183,7 +264839,7 @@ module ddr_addr_ctr .Q (clk_cnt[2]), .CLK (clk), .D (N7[2]), - .R (N73)); + .R (N76)); // ../../sources/designs/ddr/addr_ctrl/ddr_addr_ctr.v:95 GTP_DFF_R /* \clk_cnt[3] */ #( @@ -265193,7 +264849,7 @@ module ddr_addr_ctr .Q (clk_cnt[3]), .CLK (clk), .D (N7[3]), - .R (N73)); + .R (N76)); // ../../sources/designs/ddr/addr_ctrl/ddr_addr_ctr.v:95 GTP_DFF_R /* \clk_cnt[4] */ #( @@ -265203,7 +264859,7 @@ module ddr_addr_ctr .Q (clk_cnt[4]), .CLK (clk), .D (N7[4]), - .R (N73)); + .R (N76)); // ../../sources/designs/ddr/addr_ctrl/ddr_addr_ctr.v:95 GTP_DFF_R /* \clk_cnt[5] */ #( @@ -265213,7 +264869,7 @@ module ddr_addr_ctr .Q (clk_cnt[5]), .CLK (clk), .D (N7[5]), - .R (N73)); + .R (N76)); // ../../sources/designs/ddr/addr_ctrl/ddr_addr_ctr.v:95 GTP_DFF_R /* \clk_cnt[6] */ #( @@ -265223,7 +264879,7 @@ module ddr_addr_ctr .Q (clk_cnt[6]), .CLK (clk), .D (N7[6]), - .R (N73)); + .R (N76)); // ../../sources/designs/ddr/addr_ctrl/ddr_addr_ctr.v:95 GTP_DFF_R /* \clk_cnt[7] */ #( @@ -265233,7 +264889,7 @@ module ddr_addr_ctr .Q (clk_cnt[7]), .CLK (clk), .D (N7[7]), - .R (N73)); + .R (N76)); // ../../sources/designs/ddr/addr_ctrl/ddr_addr_ctr.v:95 GTP_DFF_R /* \clk_cnt[8] */ #( @@ -265243,7 +264899,7 @@ module ddr_addr_ctr .Q (clk_cnt[8]), .CLK (clk), .D (N7[8]), - .R (N73)); + .R (N76)); // ../../sources/designs/ddr/addr_ctrl/ddr_addr_ctr.v:95 GTP_DFF_R /* \clk_cnt[9] */ #( @@ -265253,7 +264909,7 @@ module ddr_addr_ctr .Q (clk_cnt[9]), .CLK (clk), .D (N7[9]), - .R (N73)); + .R (N76)); // ../../sources/designs/ddr/addr_ctrl/ddr_addr_ctr.v:95 GTP_DFF_R /* \clk_cnt[10] */ #( @@ -265263,7 +264919,7 @@ module ddr_addr_ctr .Q (clk_cnt[10]), .CLK (clk), .D (N7[10]), - .R (N73)); + .R (N76)); // ../../sources/designs/ddr/addr_ctrl/ddr_addr_ctr.v:95 GTP_DFF_R /* \clk_cnt[11] */ #( @@ -265273,7 +264929,7 @@ module ddr_addr_ctr .Q (clk_cnt[11]), .CLK (clk), .D (N7[11]), - .R (N73)); + .R (N76)); // ../../sources/designs/ddr/addr_ctrl/ddr_addr_ctr.v:95 GTP_DFF_R /* \clk_cnt[12] */ #( @@ -265283,7 +264939,7 @@ module ddr_addr_ctr .Q (clk_cnt[12]), .CLK (clk), .D (N7[12]), - .R (N73)); + .R (N76)); // ../../sources/designs/ddr/addr_ctrl/ddr_addr_ctr.v:95 GTP_DFF_R /* \clk_cnt[13] */ #( @@ -265293,7 +264949,7 @@ module ddr_addr_ctr .Q (clk_cnt[13]), .CLK (clk), .D (N7[13]), - .R (N73)); + .R (N76)); // ../../sources/designs/ddr/addr_ctrl/ddr_addr_ctr.v:95 GTP_DFF_R /* \clk_cnt[14] */ #( @@ -265303,7 +264959,7 @@ module ddr_addr_ctr .Q (clk_cnt[14]), .CLK (clk), .D (N7[14]), - .R (N73)); + .R (N76)); // ../../sources/designs/ddr/addr_ctrl/ddr_addr_ctr.v:95 GTP_DFF_R /* \clk_cnt[15] */ #( @@ -265313,7 +264969,7 @@ module ddr_addr_ctr .Q (clk_cnt[15]), .CLK (clk), .D (N7[15]), - .R (N73)); + .R (N76)); // ../../sources/designs/ddr/addr_ctrl/ddr_addr_ctr.v:95 GTP_DFF_R /* \clk_cnt[16] */ #( @@ -265323,7 +264979,7 @@ module ddr_addr_ctr .Q (clk_cnt[16]), .CLK (clk), .D (N7[16]), - .R (N73)); + .R (N76)); // ../../sources/designs/ddr/addr_ctrl/ddr_addr_ctr.v:95 GTP_DFF_R /* \clk_cnt[17] */ #( @@ -265333,7 +264989,7 @@ module ddr_addr_ctr .Q (clk_cnt[17]), .CLK (clk), .D (N7[17]), - .R (N73)); + .R (N76)); // ../../sources/designs/ddr/addr_ctrl/ddr_addr_ctr.v:95 GTP_DFF_R /* \clk_cnt[18] */ #( @@ -265343,7 +264999,7 @@ module ddr_addr_ctr .Q (clk_cnt[18]), .CLK (clk), .D (N7[18]), - .R (N73)); + .R (N76)); // ../../sources/designs/ddr/addr_ctrl/ddr_addr_ctr.v:95 GTP_DFF_R /* \clk_cnt[19] */ #( @@ -265353,36 +265009,9 @@ module ddr_addr_ctr .Q (clk_cnt[19]), .CLK (clk), .D (N7[19]), - .R (N73)); - // ../../sources/designs/ddr/addr_ctrl/ddr_addr_ctr.v:95 - - GTP_DFF_R /* \clk_cnt[20] */ #( - .GRS_EN("TRUE"), - .INIT(1'b0)) - \clk_cnt[20] ( - .Q (clk_cnt[20]), - .CLK (clk), - .D (N7[20]), - .R (N73)); - // ../../sources/designs/ddr/addr_ctrl/ddr_addr_ctr.v:95 - - GTP_DFF_R /* \clk_cnt[21] */ #( - .GRS_EN("TRUE"), - .INIT(1'b0)) - \clk_cnt[21] ( - .Q (clk_cnt[21]), - .CLK (clk), - .D (N7[21]), - .R (N73)); + .R (N76)); // ../../sources/designs/ddr/addr_ctrl/ddr_addr_ctr.v:95 - GTP_LUT1 /* \clk_cnt[31:0]_inv */ #( - .INIT(2'b01)) - \clk_cnt[31:0]_inv ( - .Z (\clk_cnt[0]_inv ), - .I0 (clk_cnt[0])); - // LUT = ~I0 ; - GTP_DFF /* rd1_vs0 */ #( .GRS_EN("TRUE"), .INIT(1'b0)) @@ -265464,7 +265093,7 @@ module ddr_addr_ctr vs_15hz_vname ( .Q (vs_15hz), .CLK (clk), - .D (_N103316), + .D (_N104128), .R (rd0_rst)); // defparam vs_15hz_vname.orig_name = vs_15hz; // ../../sources/designs/ddr/addr_ctrl/ddr_addr_ctr.v:108 @@ -265472,7 +265101,7 @@ module ddr_addr_ctr GTP_LUT2 /* vs_15hz_ce_mux */ #( .INIT(4'b0110)) vs_15hz_ce_mux ( - .Z (_N103316), + .Z (_N104128), .I0 (vs_15hz), .I1 (vs_30hz)); // LUT = (I0&~I1)|(~I0&I1) ; @@ -265483,7 +265112,7 @@ module ddr_addr_ctr vs_30hz_vname ( .Q (vs_30hz), .CLK (clk), - .D (N69)); + .D (N72)); // defparam vs_30hz_vname.orig_name = vs_30hz; // ../../sources/designs/ddr/addr_ctrl/ddr_addr_ctr.v:102 @@ -265646,7 +265275,7 @@ module hdmi_in_top wire N28; wire N46; wire N55; - wire _N103311; + wire _N104123; wire [7:0] b_in0; wire [7:0] b_in1; wire [7:0] b_in2; @@ -266203,14 +265832,14 @@ module hdmi_in_top hdmi_in_en ( .Q (hdmi_vs_out), .CLK (clk), - .D (_N103311), + .D (_N104123), .R (rst)); // ../../sources/designs/hdmi/hdmi_in/hdmi_in_top.v:103 GTP_LUT3 /* hdmi_in_en_ce_mux */ #( .INIT(8'b10100110)) hdmi_in_en_ce_mux ( - .Z (_N103311), + .Z (_N104123), .I0 (hdmi_vs_out), .I1 (vs_in1), .I2 (vs_in2)); @@ -266565,8 +266194,8 @@ module cmos_8_16bit output vs_in1 ); wire N18; - wire _N103482; - wire _N103494; + wire _N104294; + wire _N104306; wire de_cnt; wire de_in0; wire de_in1; @@ -266590,14 +266219,14 @@ module cmos_8_16bit de_cnt_vname ( .Q (de_cnt), .CLK (nt_cmos1_pclk), - .D (_N103482)); + .D (_N104294)); // defparam de_cnt_vname.orig_name = de_cnt; // ../../sources/designs/ov5640/cmos_8_16bit.v:70 GTP_LUT2 /* de_cnt_rs_mux */ #( .INIT(4'b0100)) de_cnt_rs_mux ( - .Z (_N103482), + .Z (_N104294), .I0 (de_cnt), .I1 (de_in1)); // LUT = ~I0&I1 ; @@ -266797,14 +266426,14 @@ module cmos_8_16bit image_in_en_vname ( .Q (image_in_en), .CLK (nt_cmos1_pclk), - .D (_N103494)); + .D (_N104306)); // defparam image_in_en_vname.orig_name = image_in_en; // ../../sources/designs/ov5640/cmos_8_16bit.v:74 GTP_LUT3 /* image_in_en_rs_mux */ #( .INIT(8'b10101000)) image_in_en_rs_mux ( - .Z (_N103494), + .Z (_N104306), .I0 (\u_ov5640/cmos_init_done [0] ), .I1 (image_in_en), .I2 (vs_in1)); @@ -267063,8 +266692,8 @@ module cmos_8_16bit_unq4 output vs_in1 ); wire N18; - wire _N103483; - wire _N103498; + wire _N104295; + wire _N104310; wire de_cnt; wire de_in0; wire de_in1; @@ -267088,14 +266717,14 @@ module cmos_8_16bit_unq4 de_cnt_vname ( .Q (de_cnt), .CLK (nt_cmos2_pclk), - .D (_N103483)); + .D (_N104295)); // defparam de_cnt_vname.orig_name = de_cnt; // ../../sources/designs/ov5640/cmos_8_16bit.v:70 GTP_LUT2 /* de_cnt_rs_mux */ #( .INIT(4'b0100)) de_cnt_rs_mux ( - .Z (_N103483), + .Z (_N104295), .I0 (de_cnt), .I1 (de_in1)); // LUT = ~I0&I1 ; @@ -267295,14 +266924,14 @@ module cmos_8_16bit_unq4 image_in_en_vname ( .Q (image_in_en), .CLK (nt_cmos2_pclk), - .D (_N103498)); + .D (_N104310)); // defparam image_in_en_vname.orig_name = image_in_en; // ../../sources/designs/ov5640/cmos_8_16bit.v:74 GTP_LUT3 /* image_in_en_rs_mux */ #( .INIT(8'b10101000)) image_in_en_rs_mux ( - .Z (_N103498), + .Z (_N104310), .I0 (\u_ov5640/cmos_init_done [1] ), .I1 (image_in_en), .I2 (vs_in1)); @@ -267562,40 +267191,40 @@ module i2c_com wire N195; wire [5:0] N196; wire N239; - wire _N16392; - wire _N16393; - wire _N16394; - wire _N16395; - wire _N25438; - wire _N25441; - wire _N25442; - wire _N25445; - wire _N25448; - wire _N25449; - wire _N25450; - wire _N25453; - wire _N25456; - wire _N25461; - wire _N25467; - wire _N25468; - wire _N84271; - wire _N95900; - wire _N95931; - wire _N96534; - wire _N96769; - wire _N98079; - wire _N103474; - wire _N103475; - wire _N103476; - wire _N103821; - wire _N106880; + wire _N16296; + wire _N16297; + wire _N16298; + wire _N16299; + wire _N25288; + wire _N25291; + wire _N25292; + wire _N25295; + wire _N25298; + wire _N25299; + wire _N25300; + wire _N25303; + wire _N25306; + wire _N25311; + wire _N25317; + wire _N25318; + wire _N85071; + wire _N96805; + wire _N97112; + wire _N97234; + wire _N97669; + wire _N99985; + wire _N104286; + wire _N104287; + wire _N104288; + wire _N104644; + wire _N107709; wire [5:0] cyc_count; wire sclk; GTP_LUT2 /* N8_mux3_1 */ #( .INIT(4'b1110)) N8_mux3_1 ( - .Z (_N96534), + .Z (_N97234), .I0 (cyc_count[3]), .I1 (cyc_count[4])); // LUT = (I0)|(I1) ; @@ -267604,7 +267233,7 @@ module i2c_com .INIT(32'b11111111111111110100010011001000)) \N25[0] ( .Z (i2c_sclk), - .I0 (_N96534), + .I0 (_N97234), .I1 (clock_i2c_opposite), .I2 (cyc_count[2]), .I3 (cyc_count[5]), @@ -267619,7 +267248,7 @@ module i2c_com .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N36_1_1 ( - .COUT (_N16392), + .COUT (_N16296), .Z (N196[1]), .CIN (), .I0 (cyc_count[0]), @@ -267639,9 +267268,9 @@ module i2c_com .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N36_1_2 ( - .COUT (_N16393), + .COUT (_N16297), .Z (N196[2]), - .CIN (_N16392), + .CIN (_N16296), .I0 (cyc_count[0]), .I1 (cyc_count[1]), .I2 (start), @@ -267659,9 +267288,9 @@ module i2c_com .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N36_1_3 ( - .COUT (_N16394), + .COUT (_N16298), .Z (N196[3]), - .CIN (_N16393), + .CIN (_N16297), .I0 (), .I1 (cyc_count[3]), .I2 (start), @@ -267679,9 +267308,9 @@ module i2c_com .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N36_1_4 ( - .COUT (_N16395), + .COUT (_N16299), .Z (N196[4]), - .CIN (_N16394), + .CIN (_N16298), .I0 (), .I1 (cyc_count[4]), .I2 (start), @@ -267701,7 +267330,7 @@ module i2c_com N36_1_5 ( .COUT (), .Z (N196[5]), - .CIN (_N16395), + .CIN (_N16299), .I0 (), .I1 (cyc_count[5]), .I2 (start), @@ -267715,7 +267344,7 @@ module i2c_com GTP_LUT4 /* N187_4 */ #( .INIT(16'b0000000000010000)) N187_4 ( - .Z (_N103821), + .Z (_N104644), .I0 (cyc_count[1]), .I1 (cyc_count[2]), .I2 (cyc_count[3]), @@ -267726,7 +267355,7 @@ module i2c_com .INIT(32'b01111111111111111111111111111111)) N195_inv ( .Z (N195), - .I0 (_N95931), + .I0 (_N97112), .I1 (start), .I2 (cyc_count[3]), .I3 (cyc_count[4]), @@ -267746,7 +267375,7 @@ module i2c_com .INIT(32'b00000000100000000000000000000010)) N239_vname ( .Z (N239), - .I0 (_N96769), + .I0 (_N97669), .I1 (cyc_count[0]), .I2 (cyc_count[3]), .I3 (cyc_count[4]), @@ -267758,7 +267387,7 @@ module i2c_com GTP_LUT2 /* N256_2_2 */ #( .INIT(4'b0001)) N256_2_2 ( - .Z (_N98079), + .Z (_N99985), .I0 (cyc_count[0]), .I1 (cyc_count[2])); // LUT = ~I0&~I1 ; @@ -267766,8 +267395,8 @@ module i2c_com GTP_LUT5 /* N256_2_4 */ #( .INIT(32'b00000000001000000000000000001000)) N256_2_4 ( - .Z (_N84271), - .I0 (_N98079), + .Z (_N85071), + .I0 (_N99985), .I1 (cyc_count[1]), .I2 (cyc_count[3]), .I3 (cyc_count[4]), @@ -267777,8 +267406,8 @@ module i2c_com GTP_LUT5 /* N256_3 */ #( .INIT(32'b01000000000000000000000000000001)) N256_3 ( - .Z (_N95900), - .I0 (_N96534), + .Z (_N96805), + .I0 (_N97234), .I1 (cyc_count[0]), .I2 (cyc_count[1]), .I3 (cyc_count[2]), @@ -267788,7 +267417,7 @@ module i2c_com GTP_LUT3 /* N256_4 */ #( .INIT(8'b10000000)) N256_4 ( - .Z (_N95931), + .Z (_N97112), .I0 (cyc_count[0]), .I1 (cyc_count[1]), .I2 (cyc_count[2])); @@ -267797,11 +267426,11 @@ module i2c_com GTP_LUT5M /* N262_46_3 */ #( .INIT(32'b10101111101111110000111000111110)) N262_46_3 ( - .Z (_N106880), - .I0 (_N103821), - .I1 (_N96534), + .Z (_N107709), + .I0 (_N104644), + .I1 (_N97234), .I2 (cyc_count[5]), - .I3 (_N95931), + .I3 (_N97112), .I4 (cyc_count[0]), .ID (cyc_count[2])); // LUT = (~I2&I4)|(I0&I4)|(~I1&I2&~I3)|(I1&~I2)|(ID&~I2) ; @@ -267809,7 +267438,7 @@ module i2c_com GTP_LUT2 /* N262_198 */ #( .INIT(4'b0001)) N262_198 ( - .Z (_N96769), + .Z (_N97669), .I0 (cyc_count[1]), .I1 (cyc_count[2])); // LUT = ~I0&~I1 ; @@ -267817,7 +267446,7 @@ module i2c_com GTP_LUT5 /* N267_6 */ #( .INIT(32'b10101010110011001111111111110000)) N267_6 ( - .Z (_N25438), + .Z (_N25288), .I0 (i2c_data[6]), .I1 (i2c_data[7]), .I2 (i2c_data[8]), @@ -267828,7 +267457,7 @@ module i2c_com GTP_LUT5 /* N267_9 */ #( .INIT(32'b10101010110011001111000011111111)) N267_9 ( - .Z (_N25441), + .Z (_N25291), .I0 (i2c_data[13]), .I1 (i2c_data[14]), .I2 (i2c_data[15]), @@ -267837,15 +267466,15 @@ module i2c_com // LUT = (~I3&~I4)|(I2&~I4)|(I1&~I3)|(I0&I3&I4) ; GTP_MUX2LUT6 N267_10 ( - .Z (_N25442), - .I0 (_N25441), - .I1 (_N25438), + .Z (_N25292), + .I0 (_N25291), + .I1 (_N25288), .S (cyc_count[3])); GTP_LUT5M /* N267_13 */ #( .INIT(32'b10101010111100001010101011001100)) N267_13 ( - .Z (_N25445), + .Z (_N25295), .I0 (i2c_data[9]), .I1 (i2c_data[12]), .I2 (i2c_data[11]), @@ -267857,7 +267486,7 @@ module i2c_com GTP_LUT5M /* N267_16 */ #( .INIT(32'b10101010111100001010101011001100)) N267_16 ( - .Z (_N25448), + .Z (_N25298), .I0 (i2c_data[16]), .I1 (i2c_data[19]), .I2 (i2c_data[18]), @@ -267867,21 +267496,21 @@ module i2c_com // LUT = (I1&~I3&~I4)|(ID&I3&~I4)|(I2&~I3&I4)|(I0&I3&I4) ; GTP_MUX2LUT6 N267_17 ( - .Z (_N25449), - .I0 (_N25448), - .I1 (_N25445), + .Z (_N25299), + .I0 (_N25298), + .I1 (_N25295), .S (cyc_count[3])); GTP_MUX2LUT7 N267_18 ( - .Z (_N25450), - .I0 (_N25449), - .I1 (_N25442), + .Z (_N25300), + .I0 (_N25299), + .I1 (_N25292), .S (cyc_count[2])); GTP_LUT4 /* N267_21 */ #( .INIT(16'b0000111110101100)) N267_21 ( - .Z (_N25453), + .Z (_N25303), .I0 (i2c_data[0]), .I1 (i2c_data[1]), .I2 (cyc_count[0]), @@ -267891,7 +267520,7 @@ module i2c_com GTP_LUT5M /* N267_24 */ #( .INIT(32'b10101010111100001010101011001100)) N267_24 ( - .Z (_N25456), + .Z (_N25306), .I0 (i2c_data[2]), .I1 (i2c_data[5]), .I2 (i2c_data[4]), @@ -267903,7 +267532,7 @@ module i2c_com GTP_LUT5M /* N267_29 */ #( .INIT(32'b10101010111100001010101011001100)) N267_29 ( - .Z (_N25461), + .Z (_N25311), .I0 (i2c_data[20]), .I1 (i2c_data[23]), .I2 (i2c_data[22]), @@ -267915,8 +267544,8 @@ module i2c_com GTP_LUT5 /* N267_35 */ #( .INIT(32'b10101010110000001111111100110011)) N267_35 ( - .Z (_N25467), - .I0 (_N25461), + .Z (_N25317), + .I0 (_N25311), .I1 (cyc_count[0]), .I2 (cyc_count[1]), .I3 (cyc_count[2]), @@ -267926,13 +267555,13 @@ module i2c_com GTP_LUT5M /* N267_36 */ #( .INIT(32'b10111011101110001010101010101010)) N267_36 ( - .Z (_N25468), - .I0 (_N25453), + .Z (_N25318), + .I0 (_N25303), .I1 (cyc_count[2]), .I2 (cyc_count[3]), - .I3 (_N25456), + .I3 (_N25306), .I4 (cyc_count[5]), - .ID (_N25467)); + .ID (_N25317)); // LUT = (ID&~I4)|(~I1&I3&I4)|(~I1&I2&I4)|(I0&I1&I4) ; GTP_DFF_SE /* \cyc_count[0] */ #( @@ -268007,7 +267636,7 @@ module i2c_com reg_sdat_vname ( .Q (reg_sdat), .CLK (clock_i2c), - .D (_N103476), + .D (_N104288), .S (N26)); // defparam reg_sdat_vname.orig_name = reg_sdat; // ../../sources/designs/ov5640/i2c_com.v:76 @@ -268015,13 +267644,13 @@ module i2c_com GTP_LUT5M /* reg_sdat_ce_mux */ #( .INIT(32'b10101010101110001010101010111000)) reg_sdat_ce_mux ( - .Z (_N103476), - .I0 (_N25450), - .I1 (_N95900), + .Z (_N104288), + .I0 (_N25300), + .I1 (_N96805), .I2 (reg_sdat), - .I3 (_N106880), + .I3 (_N107709), .I4 (cyc_count[4]), - .ID (_N25468)); + .ID (_N25318)); // LUT = (ID&I3&~I4)|(ID&I1&~I4)|(I0&I3&I4)|(I0&I1&I4)|(~I1&I2&~I3) ; GTP_DFF_S /* sclk */ #( @@ -268030,7 +267659,7 @@ module i2c_com sclk_vname ( .Q (sclk), .CLK (clock_i2c), - .D (_N103475), + .D (_N104287), .S (N26)); // defparam sclk_vname.orig_name = sclk; // ../../sources/designs/ov5640/i2c_com.v:76 @@ -268038,9 +267667,9 @@ module i2c_com GTP_LUT5 /* sclk_ce_mux */ #( .INIT(32'b11111111000111111110111000001110)) sclk_ce_mux ( - .Z (_N103475), - .I0 (_N84271), - .I1 (_N95900), + .Z (_N104287), + .I0 (_N85071), + .I1 (_N96805), .I2 (cyc_count[1]), .I3 (cyc_count[3]), .I4 (sclk)); @@ -268052,7 +267681,7 @@ module i2c_com tr_end_vname ( .Q (tr_end), .CLK (clock_i2c), - .D (_N103474), + .D (_N104286), .R (N26)); // defparam tr_end_vname.orig_name = tr_end; // ../../sources/designs/ov5640/i2c_com.v:76 @@ -268060,7 +267689,7 @@ module i2c_com GTP_LUT3 /* tr_end_ce_mux */ #( .INIT(8'b11001010)) tr_end_ce_mux ( - .Z (_N103474), + .Z (_N104286), .I0 (tr_end), .I1 (cyc_count[5]), .I2 (N239)); @@ -268087,29 +267716,29 @@ module reg_config wire N1134; wire N1169; wire N1193; - wire _N9664; - wire _N9682; - wire _N9690; - wire _N16245; - wire _N16246; - wire _N16247; - wire _N16248; - wire _N16249; - wire _N16250; - wire _N16251; - wire _N16252; - wire _N16253; - wire _N16383; - wire _N16384; - wire _N16385; - wire _N16386; - wire _N16387; - wire _N16388; - wire _N16389; - wire _N96528; - wire _N103472; - wire _N103473; - wire _N106873; + wire _N9677; + wire _N9695; + wire _N9703; + wire _N16267; + wire _N16268; + wire _N16269; + wire _N16270; + wire _N16271; + wire _N16272; + wire _N16273; + wire _N16274; + wire _N16275; + wire _N16287; + wire _N16288; + wire _N16289; + wire _N16290; + wire _N16291; + wire _N16292; + wire _N16293; + wire _N97285; + wire _N104284; + wire _N104285; + wire _N107702; wire clk_20k_regdiv; wire clk_20k_regdiv_opposite; wire clock_20k; @@ -268141,7 +267770,7 @@ module reg_config GTP_LUT5 /* N8_mux4_5 */ #( .INIT(32'b00000000000000000000000000000001)) N8_mux4_5 ( - .Z (_N9664), + .Z (_N9677), .I0 (clock_20k_cnt[0]), .I1 (clock_20k_cnt[1]), .I2 (clock_20k_cnt[2]), @@ -268152,7 +267781,7 @@ module reg_config GTP_LUT3 /* N8_mux7_3 */ #( .INIT(8'b01111111)) N8_mux7_3 ( - .Z (_N106873), + .Z (_N107702), .I0 (clock_20k_cnt[5]), .I1 (clock_20k_cnt[6]), .I2 (clock_20k_cnt[7])); @@ -268162,11 +267791,11 @@ module reg_config .INIT(32'b00000011111111110000001011111111)) N8_mux10 ( .Z (N8), - .I0 (_N9664), + .I0 (_N9677), .I1 (clock_20k_cnt[8]), .I2 (clock_20k_cnt[9]), .I3 (clock_20k_cnt[10]), - .I4 (_N106873)); + .I4 (_N107702)); // LUT = (~I3)|(I0&~I1&~I2)|(~I1&~I2&I4) ; GTP_LUT5CARRY /* N11_2_1 */ #( @@ -268176,7 +267805,7 @@ module reg_config .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_2_1 ( - .COUT (_N16245), + .COUT (_N16267), .Z (N1114[1]), .CIN (), .I0 (clock_20k_cnt[0]), @@ -268196,9 +267825,9 @@ module reg_config .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_2_2 ( - .COUT (_N16246), + .COUT (_N16268), .Z (N1114[2]), - .CIN (_N16245), + .CIN (_N16267), .I0 (clock_20k_cnt[0]), .I1 (clock_20k_cnt[1]), .I2 (N8), @@ -268216,9 +267845,9 @@ module reg_config .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_2_3 ( - .COUT (_N16247), + .COUT (_N16269), .Z (N1114[3]), - .CIN (_N16246), + .CIN (_N16268), .I0 (), .I1 (clock_20k_cnt[3]), .I2 (N8), @@ -268236,9 +267865,9 @@ module reg_config .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_2_4 ( - .COUT (_N16248), + .COUT (_N16270), .Z (N1114[4]), - .CIN (_N16247), + .CIN (_N16269), .I0 (), .I1 (clock_20k_cnt[4]), .I2 (N8), @@ -268256,9 +267885,9 @@ module reg_config .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_2_5 ( - .COUT (_N16249), + .COUT (_N16271), .Z (N1114[5]), - .CIN (_N16248), + .CIN (_N16270), .I0 (), .I1 (clock_20k_cnt[5]), .I2 (N8), @@ -268276,9 +267905,9 @@ module reg_config .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_2_6 ( - .COUT (_N16250), + .COUT (_N16272), .Z (N1114[6]), - .CIN (_N16249), + .CIN (_N16271), .I0 (), .I1 (clock_20k_cnt[6]), .I2 (N8), @@ -268296,9 +267925,9 @@ module reg_config .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_2_7 ( - .COUT (_N16251), + .COUT (_N16273), .Z (N1114[7]), - .CIN (_N16250), + .CIN (_N16272), .I0 (), .I1 (clock_20k_cnt[7]), .I2 (N8), @@ -268316,9 +267945,9 @@ module reg_config .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_2_8 ( - .COUT (_N16252), + .COUT (_N16274), .Z (N1114[8]), - .CIN (_N16251), + .CIN (_N16273), .I0 (), .I1 (clock_20k_cnt[8]), .I2 (N8), @@ -268336,9 +267965,9 @@ module reg_config .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_2_9 ( - .COUT (_N16253), + .COUT (_N16275), .Z (N1114[9]), - .CIN (_N16252), + .CIN (_N16274), .I0 (), .I1 (clock_20k_cnt[9]), .I2 (N8), @@ -268358,7 +267987,7 @@ module reg_config N11_2_10 ( .COUT (), .Z (N1114[10]), - .CIN (_N16253), + .CIN (_N16275), .I0 (), .I1 (clock_20k_cnt[10]), .I2 (N8), @@ -268380,7 +268009,7 @@ module reg_config GTP_LUT3 /* N26_mux2 */ #( .INIT(8'b00011111)) N26_mux2 ( - .Z (_N9682), + .Z (_N9695), .I0 (reg_index[0]), .I1 (reg_index[1]), .I2 (reg_index[2])); @@ -268389,8 +268018,8 @@ module reg_config GTP_LUT5 /* N26_mux6_3 */ #( .INIT(32'b00000010111111111111111111111111)) N26_mux6_3 ( - .Z (_N9690), - .I0 (_N9682), + .Z (_N9703), + .I0 (_N9695), .I1 (reg_index[3]), .I2 (reg_index[4]), .I3 (reg_index[5]), @@ -268404,7 +268033,7 @@ module reg_config .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_1_1 ( - .COUT (_N16383), + .COUT (_N16287), .Z (N39[1]), .CIN (), .I0 (reg_index[0]), @@ -268424,9 +268053,9 @@ module reg_config .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_1_2 ( - .COUT (_N16384), + .COUT (_N16288), .Z (N39[2]), - .CIN (_N16383), + .CIN (_N16287), .I0 (reg_index[0]), .I1 (reg_index[1]), .I2 (reg_index[2]), @@ -268444,9 +268073,9 @@ module reg_config .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_1_3 ( - .COUT (_N16385), + .COUT (_N16289), .Z (N39[3]), - .CIN (_N16384), + .CIN (_N16288), .I0 (), .I1 (reg_index[3]), .I2 (), @@ -268464,9 +268093,9 @@ module reg_config .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_1_4 ( - .COUT (_N16386), + .COUT (_N16290), .Z (N39[4]), - .CIN (_N16385), + .CIN (_N16289), .I0 (), .I1 (reg_index[4]), .I2 (), @@ -268484,9 +268113,9 @@ module reg_config .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_1_5 ( - .COUT (_N16387), + .COUT (_N16291), .Z (N39[5]), - .CIN (_N16386), + .CIN (_N16290), .I0 (), .I1 (reg_index[5]), .I2 (), @@ -268504,9 +268133,9 @@ module reg_config .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_1_6 ( - .COUT (_N16388), + .COUT (_N16292), .Z (N39[6]), - .CIN (_N16387), + .CIN (_N16291), .I0 (), .I1 (reg_index[6]), .I2 (), @@ -268524,9 +268153,9 @@ module reg_config .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_1_7 ( - .COUT (_N16389), + .COUT (_N16293), .Z (N39[7]), - .CIN (_N16388), + .CIN (_N16292), .I0 (), .I1 (reg_index[7]), .I2 (), @@ -268546,7 +268175,7 @@ module reg_config N39_1_8 ( .COUT (), .Z (N39[8]), - .CIN (_N16389), + .CIN (_N16293), .I0 (), .I1 (reg_index[8]), .I2 (), @@ -268575,7 +268204,7 @@ module reg_config .INIT(8'b10001010)) N1134_vname ( .Z (N1134), - .I0 (_N96528), + .I0 (_N97285), .I1 (tr_end), .I2 (config_step_reg[1])); // defparam N1134_vname.orig_name = N1134; @@ -268585,8 +268214,8 @@ module reg_config GTP_LUT4 /* N1134_1 */ #( .INIT(16'b0000001000110011)) N1134_1 ( - .Z (_N96528), - .I0 (_N9690), + .Z (_N97285), + .I0 (_N9703), .I1 (reg_conf_done), .I2 (reg_index[7]), .I3 (reg_index[8])); @@ -268596,7 +268225,7 @@ module reg_config .INIT(4'b1000)) N1169_vname ( .Z (N1169), - .I0 (_N96528), + .I0 (_N97285), .I1 (config_step_reg[2])); // defparam N1169_vname.orig_name = N1169; // LUT = I0&I1 ; @@ -268607,7 +268236,7 @@ module reg_config N1193_3 ( .Z (N1193), .I0 (nt_cmos1_reset), - .I1 (_N96528), + .I1 (_N97285), .I2 (config_step_reg[0])); // LUT = I0&I1&I2 ; @@ -268803,15 +268432,15 @@ module reg_config reg_conf_done_reg ( .Q (reg_conf_done), .CLK (clock_20k), - .D (_N103473), + .D (_N104285), .R (N4)); // ../../sources/designs/ov5640/reg_config.v:76 GTP_LUT4 /* reg_conf_done_reg_ce_mux */ #( .INIT(16'b1111110111001100)) reg_conf_done_reg_ce_mux ( - .Z (_N103473), - .I0 (_N9690), + .Z (_N104285), + .I0 (_N9703), .I1 (reg_conf_done), .I2 (reg_index[7]), .I3 (reg_index[8])); @@ -269039,7 +268668,7 @@ module reg_config start_vname ( .Q (start), .CLK (clock_20k), - .D (_N103472), + .D (_N104284), .R (N4)); // defparam start_vname.orig_name = start; // ../../sources/designs/ov5640/reg_config.v:76 @@ -269047,8 +268676,8 @@ module reg_config GTP_LUT5 /* start_ce_mux */ #( .INIT(32'b11101110010011001110111011001100)) start_ce_mux ( - .Z (_N103472), - .I0 (_N96528), + .Z (_N104284), + .I0 (_N97285), .I1 (start), .I2 (tr_end), .I3 (config_step_reg[0]), @@ -269081,43 +268710,43 @@ module i2c_com_unq4 output reg_sdat, output tr_end ); - wire N146; - wire N185; - wire N187; wire N195; wire [5:0] N196; - wire _N16419; - wire _N16420; - wire _N16421; - wire _N16422; - wire _N25881; - wire _N25884; - wire _N25885; - wire _N25888; - wire _N25891; - wire _N25892; - wire _N25893; - wire _N25896; - wire _N25899; - wire _N25904; - wire _N25910; - wire _N25911; - wire _N84324; - wire _N96487; - wire _N96610; - wire _N96977; - wire _N103479; - wire _N103480; - wire _N103481; - wire _N106895; - wire _N106896; + wire N239; + wire N256; + wire N267; + wire _N16323; + wire _N16324; + wire _N16325; + wire _N16326; + wire _N25830; + wire _N25833; + wire _N25837; + wire _N25840; + wire _N25842; + wire _N25845; + wire _N25848; + wire _N25853; + wire _N25859; + wire _N25860; + wire _N85124; + wire _N87597; + wire _N97064; + wire _N97132; + wire _N97333; + wire _N97590; + wire _N97699; + wire _N104291; + wire _N104292; + wire _N104293; + wire _N104685; wire [5:0] cyc_count; wire sclk; GTP_LUT2 /* N8_mux3_1 */ #( .INIT(4'b1110)) N8_mux3_1 ( - .Z (_N96610), + .Z (_N97333), .I0 (cyc_count[3]), .I1 (cyc_count[4])); // LUT = (I0)|(I1) ; @@ -269126,7 +268755,7 @@ module i2c_com_unq4 .INIT(32'b11110100111101001111110011111000)) \N25[0] ( .Z (i2c_sclk), - .I0 (_N96610), + .I0 (_N97333), .I1 (clock_i2c_opposite), .I2 (sclk), .I3 (cyc_count[2]), @@ -269141,7 +268770,7 @@ module i2c_com_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N36_1_1 ( - .COUT (_N16419), + .COUT (_N16323), .Z (N196[1]), .CIN (), .I0 (cyc_count[0]), @@ -269161,9 +268790,9 @@ module i2c_com_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N36_1_2 ( - .COUT (_N16420), + .COUT (_N16324), .Z (N196[2]), - .CIN (_N16419), + .CIN (_N16323), .I0 (cyc_count[0]), .I1 (cyc_count[1]), .I2 (start), @@ -269181,9 +268810,9 @@ module i2c_com_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N36_1_3 ( - .COUT (_N16421), + .COUT (_N16325), .Z (N196[3]), - .CIN (_N16420), + .CIN (_N16324), .I0 (), .I1 (cyc_count[3]), .I2 (start), @@ -269201,9 +268830,9 @@ module i2c_com_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N36_1_4 ( - .COUT (_N16422), + .COUT (_N16326), .Z (N196[4]), - .CIN (_N16421), + .CIN (_N16325), .I0 (), .I1 (cyc_count[4]), .I2 (start), @@ -269223,7 +268852,7 @@ module i2c_com_unq4 N36_1_5 ( .COUT (), .Z (N196[5]), - .CIN (_N16422), + .CIN (_N16326), .I0 (), .I1 (cyc_count[5]), .I2 (start), @@ -269234,45 +268863,29 @@ module i2c_com_unq4 // CARRY = (I1) ? CIN : (I4) ; // ../../sources/designs/ov5640/i2c_com.v:71 - GTP_LUT5 /* N146_8 */ #( - .INIT(32'b00000000000000000000000000000001)) - N146_8 ( - .Z (N146), - .I0 (_N96610), - .I1 (cyc_count[0]), - .I2 (cyc_count[1]), - .I3 (cyc_count[2]), - .I4 (cyc_count[5])); - // LUT = ~I0&~I1&~I2&~I3&~I4 ; - - GTP_LUT5 /* N185 */ #( - .INIT(32'b01000000000000000000000000000000)) - N185_vname ( - .Z (N185), - .I0 (_N96610), - .I1 (cyc_count[0]), - .I2 (cyc_count[1]), - .I3 (cyc_count[2]), - .I4 (cyc_count[5])); - // defparam N185_vname.orig_name = N185; - // LUT = ~I0&I1&I2&I3&I4 ; - // ../../sources/designs/ov5640/i2c_com.v:141 + GTP_LUT3 /* N146_1 */ #( + .INIT(8'b00010000)) + N146_1 ( + .Z (_N97590), + .I0 (cyc_count[3]), + .I1 (cyc_count[4]), + .I2 (cyc_count[5])); + // LUT = ~I0&~I1&I2 ; - GTP_LUT5 /* N187_3 */ #( - .INIT(32'b00001000000000000000000000000000)) - N187_3 ( - .Z (N187), - .I0 (_N96977), - .I1 (cyc_count[0]), - .I2 (cyc_count[1]), - .I3 (cyc_count[3]), - .I4 (cyc_count[5])); - // LUT = I0&I1&~I2&I3&I4 ; + GTP_LUT4 /* N146_8 */ #( + .INIT(16'b0000000000000001)) + N146_8 ( + .Z (_N104685), + .I0 (cyc_count[2]), + .I1 (cyc_count[3]), + .I2 (cyc_count[4]), + .I3 (cyc_count[5])); + // LUT = ~I0&~I1&~I2&~I3 ; GTP_LUT2 /* N195_1 */ #( .INIT(4'b0001)) N195_1 ( - .Z (_N96977), + .Z (_N97699), .I0 (cyc_count[2]), .I1 (cyc_count[4])); // LUT = ~I0&~I1 ; @@ -269281,7 +268894,7 @@ module i2c_com_unq4 .INIT(32'b01111111111111111111111111111111)) N195_inv ( .Z (N195), - .I0 (_N96487), + .I0 (_N97132), .I1 (start), .I2 (cyc_count[3]), .I3 (cyc_count[4]), @@ -269297,53 +268910,73 @@ module i2c_com_unq4 // LUT = I0&~I1 ; // ../../sources/designs/ov5640/i2c_com.v:67 + GTP_LUT5M /* N256_1_3 */ #( + .INIT(32'b11111111100000001111111100100010)) + N256_1_3 ( + .Z (N256), + .I0 (_N97590), + .I1 (cyc_count[1]), + .I2 (cyc_count[2]), + .I3 (_N85124), + .I4 (cyc_count[0]), + .ID (_N104685)); + // LUT = (ID&~I1&~I4)|(I0&I1&I2&I4)|(I3) ; + GTP_LUT5 /* N256_2_3 */ #( .INIT(32'b00000010000000000000000000100000)) N256_2_3 ( - .Z (_N84324), - .I0 (_N96977), + .Z (_N85124), + .I0 (_N97699), .I1 (cyc_count[0]), .I2 (cyc_count[1]), .I3 (cyc_count[3]), .I4 (cyc_count[5])); // LUT = (I0&~I1&I2&~I3&~I4)|(I0&~I1&~I2&I3&I4) ; + GTP_LUT5M /* N256_3 */ #( + .INIT(32'b00000000000000100000000010101010)) + N256_3 ( + .Z (N239), + .I0 (_N97064), + .I1 (cyc_count[2]), + .I2 (cyc_count[4]), + .I3 (cyc_count[1]), + .I4 (cyc_count[0]), + .ID (_N104685)); + // LUT = (ID&~I3&~I4)|(I0&~I1&~I2&~I3&I4) ; + + GTP_LUT2 /* N256_4 */ #( + .INIT(4'b1000)) + N256_4 ( + .Z (_N97064), + .I0 (cyc_count[3]), + .I1 (cyc_count[5])); + // LUT = I0&I1 ; + GTP_LUT3 /* N256_9 */ #( .INIT(8'b10000000)) N256_9 ( - .Z (_N96487), + .Z (_N97132), .I0 (cyc_count[0]), .I1 (cyc_count[1]), .I2 (cyc_count[2])); // LUT = I0&I1&I2 ; - GTP_LUT5M /* N262_46_2 */ #( - .INIT(32'b00000001000000011111111111111110)) - N262_46_2 ( - .Z (_N106895), - .I0 (_N96487), - .I1 (cyc_count[3]), - .I2 (cyc_count[4]), - .I3 (cyc_count[2]), - .I4 (cyc_count[5]), - .ID (cyc_count[0])); - // LUT = (I3&~I4)|(I2&~I4)|(I1&~I4)|(ID&~I4)|(~I0&~I1&~I2&I4) ; - - GTP_LUT5 /* N262_46_3 */ #( - .INIT(32'b11111111111100101111111111110000)) - N262_46_3 ( - .Z (_N106896), - .I0 (_N96487), - .I1 (_N96610), - .I2 (N187), - .I3 (N146), + GTP_LUT5 /* N262_47 */ #( + .INIT(32'b00000000000000001111111111111110)) + N262_47 ( + .Z (_N87597), + .I0 (cyc_count[0]), + .I1 (cyc_count[2]), + .I2 (cyc_count[3]), + .I3 (cyc_count[4]), .I4 (cyc_count[5])); - // LUT = (I2)|(I3)|(I0&~I1&I4) ; + // LUT = (I0&~I4)|(I1&~I4)|(I2&~I4)|(I3&~I4) ; GTP_LUT5 /* N267_6 */ #( .INIT(32'b11110000110011001111111110101010)) N267_6 ( - .Z (_N25881), + .Z (_N25830), .I0 (i2c_data[8]), .I1 (i2c_data[7]), .I2 (i2c_data[6]), @@ -269354,7 +268987,7 @@ module i2c_com_unq4 GTP_LUT5 /* N267_9 */ #( .INIT(32'b11110000110011001010101011111111)) N267_9 ( - .Z (_N25884), + .Z (_N25833), .I0 (i2c_data[15]), .I1 (i2c_data[14]), .I2 (i2c_data[13]), @@ -269362,16 +268995,10 @@ module i2c_com_unq4 .I4 (cyc_count[1])); // LUT = (~I3&~I4)|(I0&~I4)|(I1&~I3)|(I2&I3&I4) ; - GTP_MUX2LUT6 N267_10 ( - .Z (_N25885), - .I0 (_N25884), - .I1 (_N25881), - .S (cyc_count[3])); - GTP_LUT5M /* N267_13 */ #( .INIT(32'b11001100101010101111000010101010)) N267_13 ( - .Z (_N25888), + .Z (_N25837), .I0 (i2c_data[11]), .I1 (i2c_data[9]), .I2 (i2c_data[10]), @@ -269383,7 +269010,7 @@ module i2c_com_unq4 GTP_LUT5M /* N267_16 */ #( .INIT(32'b11001100101010101111000010101010)) N267_16 ( - .Z (_N25891), + .Z (_N25840), .I0 (i2c_data[18]), .I1 (i2c_data[16]), .I2 (i2c_data[17]), @@ -269392,22 +269019,22 @@ module i2c_com_unq4 .ID (i2c_data[19])); // LUT = (ID&~I3&~I4)|(I2&I3&~I4)|(I0&~I3&I4)|(I1&I3&I4) ; - GTP_MUX2LUT6 N267_17 ( - .Z (_N25892), - .I0 (_N25891), - .I1 (_N25888), - .S (cyc_count[3])); - - GTP_MUX2LUT7 N267_18 ( - .Z (_N25893), - .I0 (_N25892), - .I1 (_N25885), - .S (cyc_count[2])); + GTP_LUT5M /* N267_18 */ #( + .INIT(32'b10101010111100001010101011001100)) + N267_18 ( + .Z (_N25842), + .I0 (_N25830), + .I1 (_N25840), + .I2 (_N25833), + .I3 (cyc_count[3]), + .I4 (cyc_count[2]), + .ID (_N25837)); + // LUT = (I1&~I3&~I4)|(ID&I3&~I4)|(I2&~I3&I4)|(I0&I3&I4) ; GTP_LUT4 /* N267_21 */ #( .INIT(16'b0000111111001010)) N267_21 ( - .Z (_N25896), + .Z (_N25845), .I0 (i2c_data[1]), .I1 (i2c_data[0]), .I2 (cyc_count[0]), @@ -269417,7 +269044,7 @@ module i2c_com_unq4 GTP_LUT5M /* N267_24 */ #( .INIT(32'b11001100101010101111000010101010)) N267_24 ( - .Z (_N25899), + .Z (_N25848), .I0 (i2c_data[4]), .I1 (i2c_data[2]), .I2 (i2c_data[3]), @@ -269429,7 +269056,7 @@ module i2c_com_unq4 GTP_LUT5M /* N267_29 */ #( .INIT(32'b11001100101010101111000010101010)) N267_29 ( - .Z (_N25904), + .Z (_N25853), .I0 (i2c_data[22]), .I1 (i2c_data[20]), .I2 (i2c_data[21]), @@ -269441,8 +269068,8 @@ module i2c_com_unq4 GTP_LUT5 /* N267_35 */ #( .INIT(32'b10101010110000001111111100110011)) N267_35 ( - .Z (_N25910), - .I0 (_N25904), + .Z (_N25859), + .I0 (_N25853), .I1 (cyc_count[0]), .I2 (cyc_count[1]), .I3 (cyc_count[2]), @@ -269452,15 +269079,21 @@ module i2c_com_unq4 GTP_LUT5M /* N267_36 */ #( .INIT(32'b10111011101110001010101010101010)) N267_36 ( - .Z (_N25911), - .I0 (_N25896), + .Z (_N25860), + .I0 (_N25845), .I1 (cyc_count[2]), .I2 (cyc_count[3]), - .I3 (_N25899), + .I3 (_N25848), .I4 (cyc_count[5]), - .ID (_N25910)); + .ID (_N25859)); // LUT = (ID&~I4)|(~I1&I3&I4)|(~I1&I2&I4)|(I0&I1&I4) ; + GTP_MUX2LUT6 N267_37 ( + .Z (N267), + .I0 (_N25860), + .I1 (_N25842), + .S (cyc_count[4])); + GTP_DFF_SE /* \cyc_count[0] */ #( .GRS_EN("TRUE"), .INIT(1'b1)) @@ -269533,22 +269166,21 @@ module i2c_com_unq4 reg_sdat_vname ( .Q (reg_sdat), .CLK (clock_i2c), - .D (_N103481), + .D (_N104293), .S (N26)); // defparam reg_sdat_vname.orig_name = reg_sdat; // ../../sources/designs/ov5640/i2c_com.v:76 - GTP_LUT5M /* reg_sdat_ce_mux */ #( - .INIT(32'b10101010101011001010101010101100)) + GTP_LUT5 /* reg_sdat_ce_mux */ #( + .INIT(32'b11110000111100001111000111100000)) reg_sdat_ce_mux ( - .Z (_N103481), - .I0 (_N25893), - .I1 (reg_sdat), - .I2 (_N106895), - .I3 (_N106896), - .I4 (cyc_count[4]), - .ID (_N25911)); - // LUT = (ID&I3&~I4)|(ID&I2&~I4)|(I0&I3&I4)|(I0&I2&I4)|(I1&~I2&~I3) ; + .Z (_N104293), + .I0 (_N87597), + .I1 (N239), + .I2 (N267), + .I3 (reg_sdat), + .I4 (_N97590)); + // LUT = (I0&I2)|(I1&I2)|(I2&I4)|(~I0&~I1&I3&~I4) ; GTP_DFF_S /* sclk */ #( .GRS_EN("TRUE"), @@ -269556,21 +269188,19 @@ module i2c_com_unq4 sclk_vname ( .Q (sclk), .CLK (clock_i2c), - .D (_N103480), + .D (_N104292), .S (N26)); // defparam sclk_vname.orig_name = sclk; // ../../sources/designs/ov5640/i2c_com.v:76 - GTP_LUT5 /* sclk_ce_mux */ #( - .INIT(32'b00000001000000001111111111111110)) + GTP_LUT3 /* sclk_ce_mux */ #( + .INIT(8'b01001110)) sclk_ce_mux ( - .Z (_N103480), - .I0 (_N84324), - .I1 (N185), - .I2 (N146), - .I3 (sclk), - .I4 (cyc_count[1])); - // LUT = (I0&~I4)|(I1&~I4)|(I2&~I4)|(~I0&~I1&~I2&I3) ; + .Z (_N104292), + .I0 (N256), + .I1 (sclk), + .I2 (cyc_count[1])); + // LUT = (I0&~I2)|(~I0&I1) ; GTP_DFF_R /* tr_end */ #( .GRS_EN("TRUE"), @@ -269578,20 +269208,19 @@ module i2c_com_unq4 tr_end_vname ( .Q (tr_end), .CLK (clock_i2c), - .D (_N103479), + .D (_N104291), .R (N26)); // defparam tr_end_vname.orig_name = tr_end; // ../../sources/designs/ov5640/i2c_com.v:76 - GTP_LUT4 /* tr_end_ce_mux */ #( - .INIT(16'b1111111000000100)) + GTP_LUT3 /* tr_end_ce_mux */ #( + .INIT(8'b11100010)) tr_end_ce_mux ( - .Z (_N103479), - .I0 (N187), - .I1 (tr_end), - .I2 (N146), - .I3 (cyc_count[5])); - // LUT = (I0&I3)|(I2&I3)|(~I0&I1&~I2) ; + .Z (_N104291), + .I0 (tr_end), + .I1 (N239), + .I2 (cyc_count[5])); + // LUT = (I0&~I1)|(I1&I2) ; endmodule @@ -269614,29 +269243,29 @@ module reg_config_unq4 wire N1134; wire N1169; wire N1193; - wire _N9736; - wire _N9754; - wire _N9762; - wire _N16398; - wire _N16399; - wire _N16400; - wire _N16401; - wire _N16402; - wire _N16403; - wire _N16404; - wire _N16405; - wire _N16406; - wire _N16410; - wire _N16411; - wire _N16412; - wire _N16413; - wire _N16414; - wire _N16415; - wire _N16416; - wire _N96531; - wire _N103477; - wire _N103478; - wire _N103874; + wire _N9749; + wire _N9767; + wire _N9775; + wire _N16302; + wire _N16303; + wire _N16304; + wire _N16305; + wire _N16306; + wire _N16307; + wire _N16308; + wire _N16309; + wire _N16310; + wire _N16314; + wire _N16315; + wire _N16316; + wire _N16317; + wire _N16318; + wire _N16319; + wire _N16320; + wire _N97290; + wire _N104289; + wire _N104290; + wire _N104698; wire clk_20k_regdiv; wire clk_20k_regdiv_opposite; wire clock_20k; @@ -269663,7 +269292,7 @@ module reg_config_unq4 GTP_LUT5 /* N8_mux4_5 */ #( .INIT(32'b00000000000000000000000000000001)) N8_mux4_5 ( - .Z (_N9736), + .Z (_N9749), .I0 (clock_20k_cnt[4]), .I1 (clock_20k_cnt[3]), .I2 (clock_20k_cnt[2]), @@ -269674,7 +269303,7 @@ module reg_config_unq4 GTP_LUT3 /* N8_mux7_3 */ #( .INIT(8'b01111111)) N8_mux7_3 ( - .Z (_N103874), + .Z (_N104698), .I0 (clock_20k_cnt[7]), .I1 (clock_20k_cnt[6]), .I2 (clock_20k_cnt[5])); @@ -269684,11 +269313,11 @@ module reg_config_unq4 .INIT(32'b00110011001111110011001100111011)) N8_mux10 ( .Z (N8), - .I0 (_N9736), + .I0 (_N9749), .I1 (clock_20k_cnt[10]), .I2 (clock_20k_cnt[9]), .I3 (clock_20k_cnt[8]), - .I4 (_N103874)); + .I4 (_N104698)); // LUT = (~I1)|(I0&~I2&~I3)|(~I2&~I3&I4) ; GTP_LUT5CARRY /* N11_2_1 */ #( @@ -269698,7 +269327,7 @@ module reg_config_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_2_1 ( - .COUT (_N16398), + .COUT (_N16302), .Z (N1114[1]), .CIN (), .I0 (clock_20k_cnt[0]), @@ -269718,9 +269347,9 @@ module reg_config_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_2_2 ( - .COUT (_N16399), + .COUT (_N16303), .Z (N1114[2]), - .CIN (_N16398), + .CIN (_N16302), .I0 (clock_20k_cnt[0]), .I1 (clock_20k_cnt[1]), .I2 (N8), @@ -269738,9 +269367,9 @@ module reg_config_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_2_3 ( - .COUT (_N16400), + .COUT (_N16304), .Z (N1114[3]), - .CIN (_N16399), + .CIN (_N16303), .I0 (), .I1 (clock_20k_cnt[3]), .I2 (N8), @@ -269758,9 +269387,9 @@ module reg_config_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_2_4 ( - .COUT (_N16401), + .COUT (_N16305), .Z (N1114[4]), - .CIN (_N16400), + .CIN (_N16304), .I0 (), .I1 (clock_20k_cnt[4]), .I2 (N8), @@ -269778,9 +269407,9 @@ module reg_config_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_2_5 ( - .COUT (_N16402), + .COUT (_N16306), .Z (N1114[5]), - .CIN (_N16401), + .CIN (_N16305), .I0 (), .I1 (clock_20k_cnt[5]), .I2 (N8), @@ -269798,9 +269427,9 @@ module reg_config_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_2_6 ( - .COUT (_N16403), + .COUT (_N16307), .Z (N1114[6]), - .CIN (_N16402), + .CIN (_N16306), .I0 (), .I1 (clock_20k_cnt[6]), .I2 (N8), @@ -269818,9 +269447,9 @@ module reg_config_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_2_7 ( - .COUT (_N16404), + .COUT (_N16308), .Z (N1114[7]), - .CIN (_N16403), + .CIN (_N16307), .I0 (), .I1 (clock_20k_cnt[7]), .I2 (N8), @@ -269838,9 +269467,9 @@ module reg_config_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_2_8 ( - .COUT (_N16405), + .COUT (_N16309), .Z (N1114[8]), - .CIN (_N16404), + .CIN (_N16308), .I0 (), .I1 (clock_20k_cnt[8]), .I2 (N8), @@ -269858,9 +269487,9 @@ module reg_config_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_2_9 ( - .COUT (_N16406), + .COUT (_N16310), .Z (N1114[9]), - .CIN (_N16405), + .CIN (_N16309), .I0 (), .I1 (clock_20k_cnt[9]), .I2 (N8), @@ -269880,7 +269509,7 @@ module reg_config_unq4 N11_2_10 ( .COUT (), .Z (N1114[10]), - .CIN (_N16406), + .CIN (_N16310), .I0 (), .I1 (clock_20k_cnt[10]), .I2 (N8), @@ -269902,7 +269531,7 @@ module reg_config_unq4 GTP_LUT3 /* N26_mux2 */ #( .INIT(8'b01010111)) N26_mux2 ( - .Z (_N9754), + .Z (_N9767), .I0 (reg_index[2]), .I1 (reg_index[1]), .I2 (reg_index[0])); @@ -269911,8 +269540,8 @@ module reg_config_unq4 GTP_LUT5 /* N26_mux6_3 */ #( .INIT(32'b00111111001111110011111110111111)) N26_mux6_3 ( - .Z (_N9762), - .I0 (_N9754), + .Z (_N9775), + .I0 (_N9767), .I1 (reg_index[6]), .I2 (reg_index[5]), .I3 (reg_index[4]), @@ -269926,7 +269555,7 @@ module reg_config_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_1_1 ( - .COUT (_N16410), + .COUT (_N16314), .Z (N39[1]), .CIN (), .I0 (reg_index[0]), @@ -269946,9 +269575,9 @@ module reg_config_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_1_2 ( - .COUT (_N16411), + .COUT (_N16315), .Z (N39[2]), - .CIN (_N16410), + .CIN (_N16314), .I0 (reg_index[0]), .I1 (reg_index[1]), .I2 (reg_index[2]), @@ -269966,9 +269595,9 @@ module reg_config_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_1_3 ( - .COUT (_N16412), + .COUT (_N16316), .Z (N39[3]), - .CIN (_N16411), + .CIN (_N16315), .I0 (), .I1 (reg_index[3]), .I2 (), @@ -269986,9 +269615,9 @@ module reg_config_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_1_4 ( - .COUT (_N16413), + .COUT (_N16317), .Z (N39[4]), - .CIN (_N16412), + .CIN (_N16316), .I0 (), .I1 (reg_index[4]), .I2 (), @@ -270006,9 +269635,9 @@ module reg_config_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_1_5 ( - .COUT (_N16414), + .COUT (_N16318), .Z (N39[5]), - .CIN (_N16413), + .CIN (_N16317), .I0 (), .I1 (reg_index[5]), .I2 (), @@ -270026,9 +269655,9 @@ module reg_config_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_1_6 ( - .COUT (_N16415), + .COUT (_N16319), .Z (N39[6]), - .CIN (_N16414), + .CIN (_N16318), .I0 (), .I1 (reg_index[6]), .I2 (), @@ -270046,9 +269675,9 @@ module reg_config_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N39_1_7 ( - .COUT (_N16416), + .COUT (_N16320), .Z (N39[7]), - .CIN (_N16415), + .CIN (_N16319), .I0 (), .I1 (reg_index[7]), .I2 (), @@ -270068,7 +269697,7 @@ module reg_config_unq4 N39_1_8 ( .COUT (), .Z (N39[8]), - .CIN (_N16416), + .CIN (_N16320), .I0 (), .I1 (reg_index[8]), .I2 (), @@ -270097,7 +269726,7 @@ module reg_config_unq4 .INIT(8'b10001010)) N1134_vname ( .Z (N1134), - .I0 (_N96531), + .I0 (_N97290), .I1 (tr_end), .I2 (config_step_reg[1])); // defparam N1134_vname.orig_name = N1134; @@ -270107,8 +269736,8 @@ module reg_config_unq4 GTP_LUT4 /* N1134_1 */ #( .INIT(16'b0000001100100011)) N1134_1 ( - .Z (_N96531), - .I0 (_N9762), + .Z (_N97290), + .I0 (_N9775), .I1 (reg_conf_done), .I2 (reg_index[8]), .I3 (reg_index[7])); @@ -270118,7 +269747,7 @@ module reg_config_unq4 .INIT(4'b1000)) N1169_vname ( .Z (N1169), - .I0 (_N96531), + .I0 (_N97290), .I1 (config_step_reg[2])); // defparam N1169_vname.orig_name = N1169; // LUT = I0&I1 ; @@ -270129,7 +269758,7 @@ module reg_config_unq4 N1193_3 ( .Z (N1193), .I0 (nt_cmos1_reset), - .I1 (_N96531), + .I1 (_N97290), .I2 (config_step_reg[0])); // LUT = I0&I1&I2 ; @@ -270325,15 +269954,15 @@ module reg_config_unq4 reg_conf_done_reg ( .Q (reg_conf_done), .CLK (clock_20k), - .D (_N103478), + .D (_N104290), .R (N4)); // ../../sources/designs/ov5640/reg_config.v:76 GTP_LUT4 /* reg_conf_done_reg_ce_mux */ #( .INIT(16'b1111110011011100)) reg_conf_done_reg_ce_mux ( - .Z (_N103478), - .I0 (_N9762), + .Z (_N104290), + .I0 (_N9775), .I1 (reg_conf_done), .I2 (reg_index[8]), .I3 (reg_index[7])); @@ -270561,7 +270190,7 @@ module reg_config_unq4 start_vname ( .Q (start), .CLK (clock_20k), - .D (_N103477), + .D (_N104289), .R (N4)); // defparam start_vname.orig_name = start; // ../../sources/designs/ov5640/reg_config.v:76 @@ -270569,8 +270198,8 @@ module reg_config_unq4 GTP_LUT5 /* start_ce_mux */ #( .INIT(32'b11101110010011001110111011001100)) start_ce_mux ( - .Z (_N103477), - .I0 (_N96531), + .Z (_N104289), + .I0 (_N97290), .I1 (start), .I2 (tr_end), .I3 (config_step_reg[0]), @@ -270604,40 +270233,40 @@ module power_on_delay wire N15; wire N15_inv; wire [15:0] N17; - wire _N13708; - wire _N13709; - wire _N13710; - wire _N13711; - wire _N13712; - wire _N13713; - wire _N13714; - wire _N13715; - wire _N13716; - wire _N13717; - wire _N13718; - wire _N13719; - wire _N13720; - wire _N13721; - wire _N13722; - wire _N13723; - wire _N13724; - wire _N16425; - wire _N16426; - wire _N16427; - wire _N16428; - wire _N16429; - wire _N16430; - wire _N16431; - wire _N16432; - wire _N16433; - wire _N16434; - wire _N16435; - wire _N16436; - wire _N16437; - wire _N16438; - wire _N106851; - wire _N106855; - wire _N106859; + wire _N13677; + wire _N13678; + wire _N13679; + wire _N13680; + wire _N13681; + wire _N13682; + wire _N13683; + wire _N13684; + wire _N13685; + wire _N13686; + wire _N13687; + wire _N13688; + wire _N13689; + wire _N13690; + wire _N13691; + wire _N13692; + wire _N13693; + wire _N16329; + wire _N16330; + wire _N16331; + wire _N16332; + wire _N16333; + wire _N16334; + wire _N16335; + wire _N16336; + wire _N16337; + wire _N16338; + wire _N16339; + wire _N16340; + wire _N16341; + wire _N16342; + wire _N107680; + wire _N107684; + wire _N107688; wire camera_pwnd; wire [18:0] cnt1; wire \cnt1[0]_inv ; @@ -270651,7 +270280,7 @@ module power_on_delay .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N5_1_1 ( - .COUT (_N13708), + .COUT (_N13677), .Z (N5[1]), .CIN (), .I0 (cnt1[0]), @@ -270671,9 +270300,9 @@ module power_on_delay .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N5_1_2 ( - .COUT (_N13709), + .COUT (_N13678), .Z (N5[2]), - .CIN (_N13708), + .CIN (_N13677), .I0 (cnt1[0]), .I1 (cnt1[1]), .I2 (cnt1[2]), @@ -270691,9 +270320,9 @@ module power_on_delay .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N5_1_3 ( - .COUT (_N13710), + .COUT (_N13679), .Z (N5[3]), - .CIN (_N13709), + .CIN (_N13678), .I0 (), .I1 (cnt1[3]), .I2 (), @@ -270711,9 +270340,9 @@ module power_on_delay .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N5_1_4 ( - .COUT (_N13711), + .COUT (_N13680), .Z (N5[4]), - .CIN (_N13710), + .CIN (_N13679), .I0 (), .I1 (cnt1[4]), .I2 (), @@ -270731,9 +270360,9 @@ module power_on_delay .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N5_1_5 ( - .COUT (_N13712), + .COUT (_N13681), .Z (N5[5]), - .CIN (_N13711), + .CIN (_N13680), .I0 (), .I1 (cnt1[5]), .I2 (), @@ -270751,9 +270380,9 @@ module power_on_delay .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N5_1_6 ( - .COUT (_N13713), + .COUT (_N13682), .Z (N5[6]), - .CIN (_N13712), + .CIN (_N13681), .I0 (), .I1 (cnt1[6]), .I2 (), @@ -270771,9 +270400,9 @@ module power_on_delay .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N5_1_7 ( - .COUT (_N13714), + .COUT (_N13683), .Z (N5[7]), - .CIN (_N13713), + .CIN (_N13682), .I0 (), .I1 (cnt1[7]), .I2 (), @@ -270791,9 +270420,9 @@ module power_on_delay .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N5_1_8 ( - .COUT (_N13715), + .COUT (_N13684), .Z (N5[8]), - .CIN (_N13714), + .CIN (_N13683), .I0 (), .I1 (cnt1[8]), .I2 (), @@ -270811,9 +270440,9 @@ module power_on_delay .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N5_1_9 ( - .COUT (_N13716), + .COUT (_N13685), .Z (N5[9]), - .CIN (_N13715), + .CIN (_N13684), .I0 (), .I1 (cnt1[9]), .I2 (), @@ -270831,9 +270460,9 @@ module power_on_delay .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N5_1_10 ( - .COUT (_N13717), + .COUT (_N13686), .Z (N5[10]), - .CIN (_N13716), + .CIN (_N13685), .I0 (), .I1 (cnt1[10]), .I2 (), @@ -270851,9 +270480,9 @@ module power_on_delay .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N5_1_11 ( - .COUT (_N13718), + .COUT (_N13687), .Z (N5[11]), - .CIN (_N13717), + .CIN (_N13686), .I0 (), .I1 (cnt1[11]), .I2 (), @@ -270871,9 +270500,9 @@ module power_on_delay .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N5_1_12 ( - .COUT (_N13719), + .COUT (_N13688), .Z (N5[12]), - .CIN (_N13718), + .CIN (_N13687), .I0 (), .I1 (cnt1[12]), .I2 (), @@ -270891,9 +270520,9 @@ module power_on_delay .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N5_1_13 ( - .COUT (_N13720), + .COUT (_N13689), .Z (N5[13]), - .CIN (_N13719), + .CIN (_N13688), .I0 (), .I1 (cnt1[13]), .I2 (), @@ -270911,9 +270540,9 @@ module power_on_delay .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N5_1_14 ( - .COUT (_N13721), + .COUT (_N13690), .Z (N5[14]), - .CIN (_N13720), + .CIN (_N13689), .I0 (), .I1 (cnt1[14]), .I2 (), @@ -270931,9 +270560,9 @@ module power_on_delay .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N5_1_15 ( - .COUT (_N13722), + .COUT (_N13691), .Z (N5[15]), - .CIN (_N13721), + .CIN (_N13690), .I0 (), .I1 (cnt1[15]), .I2 (), @@ -270951,9 +270580,9 @@ module power_on_delay .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N5_1_16 ( - .COUT (_N13723), + .COUT (_N13692), .Z (N5[16]), - .CIN (_N13722), + .CIN (_N13691), .I0 (), .I1 (cnt1[16]), .I2 (), @@ -270971,9 +270600,9 @@ module power_on_delay .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N5_1_17 ( - .COUT (_N13724), + .COUT (_N13693), .Z (N5[17]), - .CIN (_N13723), + .CIN (_N13692), .I0 (), .I1 (cnt1[17]), .I2 (), @@ -270993,7 +270622,7 @@ module power_on_delay N5_1_18 ( .COUT (), .Z (N5[18]), - .CIN (_N13724), + .CIN (_N13693), .I0 (), .I1 (cnt1[18]), .I2 (), @@ -271010,16 +270639,16 @@ module power_on_delay .Z (N15), .I0 (cnt2[0]), .I1 (cnt2[15]), - .I2 (_N106851), - .I3 (_N106855), - .I4 (_N106859)); + .I2 (_N107680), + .I3 (_N107684), + .I4 (_N107688)); // defparam N15_inv_vname.orig_name = N15_inv; // LUT = (~I4)|(~I3)|(~I2)|(~I1)|(~I0) ; GTP_LUT4 /* N15_mux15_4 */ #( .INIT(16'b1000000000000000)) N15_mux15_4 ( - .Z (_N106851), + .Z (_N107680), .I0 (cnt2[1]), .I1 (cnt2[2]), .I2 (cnt2[3]), @@ -271029,7 +270658,7 @@ module power_on_delay GTP_LUT5 /* N15_mux15_8 */ #( .INIT(32'b10000000000000000000000000000000)) N15_mux15_8 ( - .Z (_N106855), + .Z (_N107684), .I0 (cnt2[5]), .I1 (cnt2[6]), .I2 (cnt2[7]), @@ -271040,7 +270669,7 @@ module power_on_delay GTP_LUT5 /* N15_mux15_12 */ #( .INIT(32'b10000000000000000000000000000000)) N15_mux15_12 ( - .Z (_N106859), + .Z (_N107688), .I0 (cnt2[10]), .I1 (cnt2[11]), .I2 (cnt2[12]), @@ -271054,9 +270683,9 @@ module power_on_delay .Z (N15_inv), .I0 (cnt2[0]), .I1 (cnt2[15]), - .I2 (_N106851), - .I3 (_N106855), - .I4 (_N106859)); + .I2 (_N107680), + .I3 (_N107684), + .I4 (_N107688)); // LUT = I0&I1&I2&I3&I4 ; GTP_LUT5CARRY /* N17_1_1 */ #( @@ -271066,7 +270695,7 @@ module power_on_delay .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_1 ( - .COUT (_N16425), + .COUT (_N16329), .Z (N17[1]), .CIN (), .I0 (cnt2[0]), @@ -271086,9 +270715,9 @@ module power_on_delay .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_2 ( - .COUT (_N16426), + .COUT (_N16330), .Z (N17[2]), - .CIN (_N16425), + .CIN (_N16329), .I0 (cnt2[0]), .I1 (cnt2[1]), .I2 (cnt2[2]), @@ -271106,9 +270735,9 @@ module power_on_delay .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_3 ( - .COUT (_N16427), + .COUT (_N16331), .Z (N17[3]), - .CIN (_N16426), + .CIN (_N16330), .I0 (), .I1 (cnt2[3]), .I2 (), @@ -271126,9 +270755,9 @@ module power_on_delay .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_4 ( - .COUT (_N16428), + .COUT (_N16332), .Z (N17[4]), - .CIN (_N16427), + .CIN (_N16331), .I0 (), .I1 (cnt2[4]), .I2 (), @@ -271146,9 +270775,9 @@ module power_on_delay .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_5 ( - .COUT (_N16429), + .COUT (_N16333), .Z (N17[5]), - .CIN (_N16428), + .CIN (_N16332), .I0 (), .I1 (cnt2[5]), .I2 (), @@ -271166,9 +270795,9 @@ module power_on_delay .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_6 ( - .COUT (_N16430), + .COUT (_N16334), .Z (N17[6]), - .CIN (_N16429), + .CIN (_N16333), .I0 (), .I1 (cnt2[6]), .I2 (), @@ -271186,9 +270815,9 @@ module power_on_delay .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_7 ( - .COUT (_N16431), + .COUT (_N16335), .Z (N17[7]), - .CIN (_N16430), + .CIN (_N16334), .I0 (), .I1 (cnt2[7]), .I2 (), @@ -271206,9 +270835,9 @@ module power_on_delay .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_8 ( - .COUT (_N16432), + .COUT (_N16336), .Z (N17[8]), - .CIN (_N16431), + .CIN (_N16335), .I0 (), .I1 (cnt2[8]), .I2 (), @@ -271226,9 +270855,9 @@ module power_on_delay .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_9 ( - .COUT (_N16433), + .COUT (_N16337), .Z (N17[9]), - .CIN (_N16432), + .CIN (_N16336), .I0 (), .I1 (cnt2[9]), .I2 (), @@ -271246,9 +270875,9 @@ module power_on_delay .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_10 ( - .COUT (_N16434), + .COUT (_N16338), .Z (N17[10]), - .CIN (_N16433), + .CIN (_N16337), .I0 (), .I1 (cnt2[10]), .I2 (), @@ -271266,9 +270895,9 @@ module power_on_delay .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_11 ( - .COUT (_N16435), + .COUT (_N16339), .Z (N17[11]), - .CIN (_N16434), + .CIN (_N16338), .I0 (), .I1 (cnt2[11]), .I2 (), @@ -271286,9 +270915,9 @@ module power_on_delay .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_12 ( - .COUT (_N16436), + .COUT (_N16340), .Z (N17[12]), - .CIN (_N16435), + .CIN (_N16339), .I0 (), .I1 (cnt2[12]), .I2 (), @@ -271306,9 +270935,9 @@ module power_on_delay .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_13 ( - .COUT (_N16437), + .COUT (_N16341), .Z (N17[13]), - .CIN (_N16436), + .CIN (_N16340), .I0 (), .I1 (cnt2[13]), .I2 (), @@ -271326,9 +270955,9 @@ module power_on_delay .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_14 ( - .COUT (_N16438), + .COUT (_N16342), .Z (N17[14]), - .CIN (_N16437), + .CIN (_N16341), .I0 (), .I1 (cnt2[14]), .I2 (), @@ -271348,7 +270977,7 @@ module power_on_delay N17_1_15 ( .COUT (), .Z (N17[15]), - .CIN (_N16438), + .CIN (_N16342), .I0 (), .I1 (cnt2[15]), .I2 (), @@ -271813,27 +271442,27 @@ module ipml_fifo_ctrl_v1_3 wire N158; wire N160; wire [11:0] \N160.co ; - wire _N16508; - wire _N16509; - wire _N16510; - wire _N16511; - wire _N16512; - wire _N16513; - wire _N16514; - wire _N16515; - wire _N16516; - wire _N16517; - wire _N16520; - wire _N16521; - wire _N16522; - wire _N16523; - wire _N16524; - wire _N16525; - wire _N16526; - wire _N16527; - wire _N16528; - wire _N16529; - wire _N108362; + wire _N16412; + wire _N16413; + wire _N16414; + wire _N16415; + wire _N16416; + wire _N16417; + wire _N16418; + wire _N16419; + wire _N16420; + wire _N16421; + wire _N16424; + wire _N16425; + wire _N16426; + wire _N16427; + wire _N16428; + wire _N16429; + wire _N16430; + wire _N16431; + wire _N16432; + wire _N16433; + wire _N109247; wire [10:0] rbin; wire [10:0] rgnext; wire [10:0] rptr; @@ -272564,7 +272193,7 @@ module ipml_fifo_ctrl_v1_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_1 ( - .COUT (_N16508), + .COUT (_N16412), .Z (N2[0]), .CIN (), .I0 (w_en), @@ -272584,9 +272213,9 @@ module ipml_fifo_ctrl_v1_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_2 ( - .COUT (_N16509), + .COUT (_N16413), .Z (N2[1]), - .CIN (_N16508), + .CIN (_N16412), .I0 (w_en), .I1 (waddr[0]), .I2 (waddr[1]), @@ -272604,9 +272233,9 @@ module ipml_fifo_ctrl_v1_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_3 ( - .COUT (_N16510), + .COUT (_N16414), .Z (N2[2]), - .CIN (_N16509), + .CIN (_N16413), .I0 (), .I1 (waddr[2]), .I2 (), @@ -272624,9 +272253,9 @@ module ipml_fifo_ctrl_v1_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_4 ( - .COUT (_N16511), + .COUT (_N16415), .Z (N2[3]), - .CIN (_N16510), + .CIN (_N16414), .I0 (), .I1 (waddr[3]), .I2 (), @@ -272644,9 +272273,9 @@ module ipml_fifo_ctrl_v1_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_5 ( - .COUT (_N16512), + .COUT (_N16416), .Z (N2[4]), - .CIN (_N16511), + .CIN (_N16415), .I0 (), .I1 (waddr[4]), .I2 (), @@ -272664,9 +272293,9 @@ module ipml_fifo_ctrl_v1_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_6 ( - .COUT (_N16513), + .COUT (_N16417), .Z (N2[5]), - .CIN (_N16512), + .CIN (_N16416), .I0 (), .I1 (waddr[5]), .I2 (), @@ -272684,9 +272313,9 @@ module ipml_fifo_ctrl_v1_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_7 ( - .COUT (_N16514), + .COUT (_N16418), .Z (N2[6]), - .CIN (_N16513), + .CIN (_N16417), .I0 (), .I1 (waddr[6]), .I2 (), @@ -272704,9 +272333,9 @@ module ipml_fifo_ctrl_v1_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_8 ( - .COUT (_N16515), + .COUT (_N16419), .Z (N2[7]), - .CIN (_N16514), + .CIN (_N16418), .I0 (), .I1 (waddr[7]), .I2 (), @@ -272724,9 +272353,9 @@ module ipml_fifo_ctrl_v1_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_9 ( - .COUT (_N16516), + .COUT (_N16420), .Z (N2[8]), - .CIN (_N16515), + .CIN (_N16419), .I0 (), .I1 (waddr[8]), .I2 (), @@ -272744,9 +272373,9 @@ module ipml_fifo_ctrl_v1_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_10 ( - .COUT (_N16517), + .COUT (_N16421), .Z (N2[9]), - .CIN (_N16516), + .CIN (_N16420), .I0 (), .I1 (waddr[9]), .I2 (), @@ -272766,7 +272395,7 @@ module ipml_fifo_ctrl_v1_3 N2_11 ( .COUT (), .Z (N2[10]), - .CIN (_N16517), + .CIN (_N16421), .I0 (), .I1 (wbin[10]), .I2 (), @@ -272810,7 +272439,7 @@ module ipml_fifo_ctrl_v1_3 GTP_LUT5 /* \N3[3]_1 */ #( .INIT(32'b00011101111000101110001000011101)) \N3[3]_1 ( - .Z (_N108362), + .Z (_N109247), .I0 (N2[3]), .I1 (wfull), .I2 (waddr[3]), @@ -273064,7 +272693,7 @@ module ipml_fifo_ctrl_v1_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N79_1 ( - .COUT (_N16520), + .COUT (_N16424), .Z (N79[0]), .CIN (), .I0 (rempty), @@ -273084,9 +272713,9 @@ module ipml_fifo_ctrl_v1_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N79_2 ( - .COUT (_N16521), + .COUT (_N16425), .Z (N79[1]), - .CIN (_N16520), + .CIN (_N16424), .I0 (rempty), .I1 (raddr[0]), .I2 (\u_ov5640/u_mix_image/rd_sta [1] ), @@ -273104,9 +272733,9 @@ module ipml_fifo_ctrl_v1_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N79_3 ( - .COUT (_N16522), + .COUT (_N16426), .Z (N79[2]), - .CIN (_N16521), + .CIN (_N16425), .I0 (), .I1 (raddr[2]), .I2 (), @@ -273124,9 +272753,9 @@ module ipml_fifo_ctrl_v1_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N79_4 ( - .COUT (_N16523), + .COUT (_N16427), .Z (N79[3]), - .CIN (_N16522), + .CIN (_N16426), .I0 (), .I1 (raddr[3]), .I2 (), @@ -273144,9 +272773,9 @@ module ipml_fifo_ctrl_v1_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N79_5 ( - .COUT (_N16524), + .COUT (_N16428), .Z (N79[4]), - .CIN (_N16523), + .CIN (_N16427), .I0 (), .I1 (raddr[4]), .I2 (), @@ -273164,9 +272793,9 @@ module ipml_fifo_ctrl_v1_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N79_6 ( - .COUT (_N16525), + .COUT (_N16429), .Z (N79[5]), - .CIN (_N16524), + .CIN (_N16428), .I0 (), .I1 (raddr[5]), .I2 (), @@ -273184,9 +272813,9 @@ module ipml_fifo_ctrl_v1_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N79_7 ( - .COUT (_N16526), + .COUT (_N16430), .Z (N79[6]), - .CIN (_N16525), + .CIN (_N16429), .I0 (), .I1 (raddr[6]), .I2 (), @@ -273204,9 +272833,9 @@ module ipml_fifo_ctrl_v1_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N79_8 ( - .COUT (_N16527), + .COUT (_N16431), .Z (N79[7]), - .CIN (_N16526), + .CIN (_N16430), .I0 (), .I1 (raddr[7]), .I2 (), @@ -273224,9 +272853,9 @@ module ipml_fifo_ctrl_v1_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N79_9 ( - .COUT (_N16528), + .COUT (_N16432), .Z (N79[8]), - .CIN (_N16527), + .CIN (_N16431), .I0 (), .I1 (raddr[8]), .I2 (), @@ -273244,9 +272873,9 @@ module ipml_fifo_ctrl_v1_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N79_10 ( - .COUT (_N16529), + .COUT (_N16433), .Z (N79[9]), - .CIN (_N16528), + .CIN (_N16432), .I0 (), .I1 (raddr[9]), .I2 (), @@ -273266,7 +272895,7 @@ module ipml_fifo_ctrl_v1_3 N79_11 ( .COUT (), .Z (N79[10]), - .CIN (_N16529), + .CIN (_N16433), .I0 (), .I1 (rbin[10]), .I2 (), @@ -273587,7 +273216,7 @@ module ipml_fifo_ctrl_v1_3 .I0 (wwptr[2]), .I1 (wrptr[2]), .I2 (wrptr[5]), - .I3 (_N108362), + .I3 (_N109247), .I4 (), .ID ()); // LUT = 1'b0 ; @@ -274235,27 +273864,27 @@ module ipml_fifo_ctrl_v1_3_unq4 wire N158; wire N160; wire [11:0] \N160.co ; - wire _N16452; - wire _N16453; - wire _N16454; - wire _N16455; - wire _N16456; - wire _N16457; - wire _N16458; - wire _N16459; - wire _N16460; - wire _N16461; - wire _N16532; - wire _N16533; - wire _N16534; - wire _N16535; - wire _N16536; - wire _N16537; - wire _N16538; - wire _N16539; - wire _N16540; - wire _N16541; - wire _N108363; + wire _N16356; + wire _N16357; + wire _N16358; + wire _N16359; + wire _N16360; + wire _N16361; + wire _N16362; + wire _N16363; + wire _N16364; + wire _N16365; + wire _N16442; + wire _N16443; + wire _N16444; + wire _N16445; + wire _N16446; + wire _N16447; + wire _N16448; + wire _N16449; + wire _N16450; + wire _N16451; + wire _N109248; wire [10:0] rbin; wire [10:0] rgnext; wire [10:0] rptr; @@ -274986,7 +274615,7 @@ module ipml_fifo_ctrl_v1_3_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_1 ( - .COUT (_N16532), + .COUT (_N16442), .Z (N2[0]), .CIN (), .I0 (w_en), @@ -275006,9 +274635,9 @@ module ipml_fifo_ctrl_v1_3_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_2 ( - .COUT (_N16533), + .COUT (_N16443), .Z (N2[1]), - .CIN (_N16532), + .CIN (_N16442), .I0 (w_en), .I1 (waddr[0]), .I2 (waddr[1]), @@ -275026,9 +274655,9 @@ module ipml_fifo_ctrl_v1_3_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_3 ( - .COUT (_N16534), + .COUT (_N16444), .Z (N2[2]), - .CIN (_N16533), + .CIN (_N16443), .I0 (), .I1 (waddr[2]), .I2 (), @@ -275046,9 +274675,9 @@ module ipml_fifo_ctrl_v1_3_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_4 ( - .COUT (_N16535), + .COUT (_N16445), .Z (N2[3]), - .CIN (_N16534), + .CIN (_N16444), .I0 (), .I1 (waddr[3]), .I2 (), @@ -275066,9 +274695,9 @@ module ipml_fifo_ctrl_v1_3_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_5 ( - .COUT (_N16536), + .COUT (_N16446), .Z (N2[4]), - .CIN (_N16535), + .CIN (_N16445), .I0 (), .I1 (waddr[4]), .I2 (), @@ -275086,9 +274715,9 @@ module ipml_fifo_ctrl_v1_3_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_6 ( - .COUT (_N16537), + .COUT (_N16447), .Z (N2[5]), - .CIN (_N16536), + .CIN (_N16446), .I0 (), .I1 (waddr[5]), .I2 (), @@ -275106,9 +274735,9 @@ module ipml_fifo_ctrl_v1_3_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_7 ( - .COUT (_N16538), + .COUT (_N16448), .Z (N2[6]), - .CIN (_N16537), + .CIN (_N16447), .I0 (), .I1 (waddr[6]), .I2 (), @@ -275126,9 +274755,9 @@ module ipml_fifo_ctrl_v1_3_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_8 ( - .COUT (_N16539), + .COUT (_N16449), .Z (N2[7]), - .CIN (_N16538), + .CIN (_N16448), .I0 (), .I1 (waddr[7]), .I2 (), @@ -275146,9 +274775,9 @@ module ipml_fifo_ctrl_v1_3_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_9 ( - .COUT (_N16540), + .COUT (_N16450), .Z (N2[8]), - .CIN (_N16539), + .CIN (_N16449), .I0 (), .I1 (waddr[8]), .I2 (), @@ -275166,9 +274795,9 @@ module ipml_fifo_ctrl_v1_3_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_10 ( - .COUT (_N16541), + .COUT (_N16451), .Z (N2[9]), - .CIN (_N16540), + .CIN (_N16450), .I0 (), .I1 (waddr[9]), .I2 (), @@ -275188,7 +274817,7 @@ module ipml_fifo_ctrl_v1_3_unq4 N2_11 ( .COUT (), .Z (N2[10]), - .CIN (_N16541), + .CIN (_N16451), .I0 (), .I1 (wbin[10]), .I2 (), @@ -275232,7 +274861,7 @@ module ipml_fifo_ctrl_v1_3_unq4 GTP_LUT5 /* \N3[3]_1 */ #( .INIT(32'b00100111110110001101100000100111)) \N3[3]_1 ( - .Z (_N108363), + .Z (_N109248), .I0 (wfull), .I1 (waddr[3]), .I2 (N2[3]), @@ -275486,7 +275115,7 @@ module ipml_fifo_ctrl_v1_3_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N79_1 ( - .COUT (_N16452), + .COUT (_N16356), .Z (N79[0]), .CIN (), .I0 (rempty), @@ -275506,9 +275135,9 @@ module ipml_fifo_ctrl_v1_3_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N79_2 ( - .COUT (_N16453), + .COUT (_N16357), .Z (N79[1]), - .CIN (_N16452), + .CIN (_N16356), .I0 (rempty), .I1 (raddr[0]), .I2 (\u_ov5640/u_mix_image/rd_sta [2] ), @@ -275526,9 +275155,9 @@ module ipml_fifo_ctrl_v1_3_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N79_3 ( - .COUT (_N16454), + .COUT (_N16358), .Z (N79[2]), - .CIN (_N16453), + .CIN (_N16357), .I0 (), .I1 (raddr[2]), .I2 (), @@ -275546,9 +275175,9 @@ module ipml_fifo_ctrl_v1_3_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N79_4 ( - .COUT (_N16455), + .COUT (_N16359), .Z (N79[3]), - .CIN (_N16454), + .CIN (_N16358), .I0 (), .I1 (raddr[3]), .I2 (), @@ -275566,9 +275195,9 @@ module ipml_fifo_ctrl_v1_3_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N79_5 ( - .COUT (_N16456), + .COUT (_N16360), .Z (N79[4]), - .CIN (_N16455), + .CIN (_N16359), .I0 (), .I1 (raddr[4]), .I2 (), @@ -275586,9 +275215,9 @@ module ipml_fifo_ctrl_v1_3_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N79_6 ( - .COUT (_N16457), + .COUT (_N16361), .Z (N79[5]), - .CIN (_N16456), + .CIN (_N16360), .I0 (), .I1 (raddr[5]), .I2 (), @@ -275606,9 +275235,9 @@ module ipml_fifo_ctrl_v1_3_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N79_7 ( - .COUT (_N16458), + .COUT (_N16362), .Z (N79[6]), - .CIN (_N16457), + .CIN (_N16361), .I0 (), .I1 (raddr[6]), .I2 (), @@ -275626,9 +275255,9 @@ module ipml_fifo_ctrl_v1_3_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N79_8 ( - .COUT (_N16459), + .COUT (_N16363), .Z (N79[7]), - .CIN (_N16458), + .CIN (_N16362), .I0 (), .I1 (raddr[7]), .I2 (), @@ -275646,9 +275275,9 @@ module ipml_fifo_ctrl_v1_3_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N79_9 ( - .COUT (_N16460), + .COUT (_N16364), .Z (N79[8]), - .CIN (_N16459), + .CIN (_N16363), .I0 (), .I1 (raddr[8]), .I2 (), @@ -275666,9 +275295,9 @@ module ipml_fifo_ctrl_v1_3_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N79_10 ( - .COUT (_N16461), + .COUT (_N16365), .Z (N79[9]), - .CIN (_N16460), + .CIN (_N16364), .I0 (), .I1 (raddr[9]), .I2 (), @@ -275688,7 +275317,7 @@ module ipml_fifo_ctrl_v1_3_unq4 N79_11 ( .COUT (), .Z (N79[10]), - .CIN (_N16461), + .CIN (_N16365), .I0 (), .I1 (rbin[10]), .I2 (), @@ -276009,7 +275638,7 @@ module ipml_fifo_ctrl_v1_3_unq4 .I0 (wwptr[2]), .I1 (wrptr[2]), .I2 (wrptr[5]), - .I3 (_N108363), + .I3 (_N109248), .I4 (), .ID ()); // LUT = 1'b0 ; @@ -276684,73 +276313,73 @@ module mix_image wire _N9; wire _N12; wire _N13; - wire _N13727; - wire _N13728; - wire _N13729; - wire _N13730; - wire _N13731; - wire _N13732; - wire _N13733; - wire _N13734; - wire _N13735; - wire _N16441; - wire _N16442; - wire _N16443; - wire _N16444; - wire _N16445; - wire _N16446; - wire _N16447; - wire _N16448; - wire _N16449; - wire _N16475; - wire _N16476; - wire _N16477; - wire _N16478; - wire _N16479; - wire _N16480; - wire _N16481; - wire _N16482; - wire _N16483; - wire _N16497; - wire _N16498; - wire _N16499; - wire _N16500; - wire _N16501; - wire _N16502; - wire _N16503; - wire _N16504; - wire _N16505; - wire _N76589; - wire _N76642; - wire _N76788; - wire _N76810; - wire _N76927; - wire _N76977; - wire _N77119; - wire _N77189; - wire _N77253; - wire _N77378; - wire _N77417; - wire _N77511; - wire _N77652; - wire _N77693; - wire _N77807; - wire _N77875; - wire _N96537; - wire _N96993; - wire _N103303; - wire _N103304; - wire _N103496; - wire _N103500; - wire _N103792; - wire _N103793; - wire _N103802; - wire _N103803; - wire _N103812; - wire _N103813; - wire _N103845; - wire _N103853; - wire _N103854; + wire _N13696; + wire _N13697; + wire _N13698; + wire _N13699; + wire _N13700; + wire _N13701; + wire _N13702; + wire _N13703; + wire _N13704; + wire _N16345; + wire _N16346; + wire _N16347; + wire _N16348; + wire _N16349; + wire _N16350; + wire _N16351; + wire _N16352; + wire _N16353; + wire _N16379; + wire _N16380; + wire _N16381; + wire _N16382; + wire _N16383; + wire _N16384; + wire _N16385; + wire _N16386; + wire _N16387; + wire _N16401; + wire _N16402; + wire _N16403; + wire _N16404; + wire _N16405; + wire _N16406; + wire _N16407; + wire _N16408; + wire _N16409; + wire _N77174; + wire _N77271; + wire _N77314; + wire _N77433; + wire _N77517; + wire _N77607; + wire _N77640; + wire _N77752; + wire _N77847; + wire _N77902; + wire _N78015; + wire _N78107; + wire _N78218; + wire _N78294; + wire _N78320; + wire _N78412; + wire _N97291; + wire _N97559; + wire _N104115; + wire _N104116; + wire _N104308; + wire _N104312; + wire _N104615; + wire _N104616; + wire _N104625; + wire _N104626; + wire _N104635; + wire _N104636; + wire _N104668; + wire _N104676; + wire _N104677; wire cmos1_vsync_rise; wire cmos2_vsync_rise; wire [10:0] cnt0_h; @@ -276795,7 +276424,7 @@ module mix_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N12_1_1 ( - .COUT (_N16441), + .COUT (_N16345), .Z (N12[1]), .CIN (), .I0 (cnt0_w[0]), @@ -276815,9 +276444,9 @@ module mix_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N12_1_2 ( - .COUT (_N16442), + .COUT (_N16346), .Z (N12[2]), - .CIN (_N16441), + .CIN (_N16345), .I0 (cnt0_w[0]), .I1 (cnt0_w[1]), .I2 (cnt0_w[2]), @@ -276835,9 +276464,9 @@ module mix_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N12_1_3 ( - .COUT (_N16443), + .COUT (_N16347), .Z (N12[3]), - .CIN (_N16442), + .CIN (_N16346), .I0 (), .I1 (cnt0_w[3]), .I2 (), @@ -276855,9 +276484,9 @@ module mix_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N12_1_4 ( - .COUT (_N16444), + .COUT (_N16348), .Z (N12[4]), - .CIN (_N16443), + .CIN (_N16347), .I0 (), .I1 (cnt0_w[4]), .I2 (), @@ -276875,9 +276504,9 @@ module mix_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N12_1_5 ( - .COUT (_N16445), + .COUT (_N16349), .Z (N12[5]), - .CIN (_N16444), + .CIN (_N16348), .I0 (), .I1 (cnt0_w[5]), .I2 (), @@ -276895,9 +276524,9 @@ module mix_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N12_1_6 ( - .COUT (_N16446), + .COUT (_N16350), .Z (N12[6]), - .CIN (_N16445), + .CIN (_N16349), .I0 (), .I1 (cnt0_w[6]), .I2 (), @@ -276915,9 +276544,9 @@ module mix_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N12_1_7 ( - .COUT (_N16447), + .COUT (_N16351), .Z (N12[7]), - .CIN (_N16446), + .CIN (_N16350), .I0 (), .I1 (cnt0_w[7]), .I2 (), @@ -276935,9 +276564,9 @@ module mix_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N12_1_8 ( - .COUT (_N16448), + .COUT (_N16352), .Z (N12[8]), - .CIN (_N16447), + .CIN (_N16351), .I0 (), .I1 (cnt0_w[8]), .I2 (), @@ -276955,9 +276584,9 @@ module mix_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N12_1_9 ( - .COUT (_N16449), + .COUT (_N16353), .Z (N12[9]), - .CIN (_N16448), + .CIN (_N16352), .I0 (), .I1 (cnt0_w[9]), .I2 (), @@ -276977,7 +276606,7 @@ module mix_image N12_1_10 ( .COUT (), .Z (N12[10]), - .CIN (_N16449), + .CIN (_N16353), .I0 (), .I1 (cnt0_w[10]), .I2 (), @@ -277022,7 +276651,7 @@ module mix_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N42_1_1 ( - .COUT (_N16475), + .COUT (_N16379), .Z (N42[1]), .CIN (), .I0 (cnt1_w[0]), @@ -277042,9 +276671,9 @@ module mix_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N42_1_2 ( - .COUT (_N16476), + .COUT (_N16380), .Z (N42[2]), - .CIN (_N16475), + .CIN (_N16379), .I0 (cnt1_w[0]), .I1 (cnt1_w[1]), .I2 (cnt1_w[2]), @@ -277062,9 +276691,9 @@ module mix_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N42_1_3 ( - .COUT (_N16477), + .COUT (_N16381), .Z (N42[3]), - .CIN (_N16476), + .CIN (_N16380), .I0 (), .I1 (cnt1_w[3]), .I2 (), @@ -277082,9 +276711,9 @@ module mix_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N42_1_4 ( - .COUT (_N16478), + .COUT (_N16382), .Z (N42[4]), - .CIN (_N16477), + .CIN (_N16381), .I0 (), .I1 (cnt1_w[4]), .I2 (), @@ -277102,9 +276731,9 @@ module mix_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N42_1_5 ( - .COUT (_N16479), + .COUT (_N16383), .Z (N42[5]), - .CIN (_N16478), + .CIN (_N16382), .I0 (), .I1 (cnt1_w[5]), .I2 (), @@ -277122,9 +276751,9 @@ module mix_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N42_1_6 ( - .COUT (_N16480), + .COUT (_N16384), .Z (N42[6]), - .CIN (_N16479), + .CIN (_N16383), .I0 (), .I1 (cnt1_w[6]), .I2 (), @@ -277142,9 +276771,9 @@ module mix_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N42_1_7 ( - .COUT (_N16481), + .COUT (_N16385), .Z (N42[7]), - .CIN (_N16480), + .CIN (_N16384), .I0 (), .I1 (cnt1_w[7]), .I2 (), @@ -277162,9 +276791,9 @@ module mix_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N42_1_8 ( - .COUT (_N16482), + .COUT (_N16386), .Z (N42[8]), - .CIN (_N16481), + .CIN (_N16385), .I0 (), .I1 (cnt1_w[8]), .I2 (), @@ -277182,9 +276811,9 @@ module mix_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N42_1_9 ( - .COUT (_N16483), + .COUT (_N16387), .Z (N42[9]), - .CIN (_N16482), + .CIN (_N16386), .I0 (), .I1 (cnt1_w[9]), .I2 (), @@ -277204,7 +276833,7 @@ module mix_image N42_1_10 ( .COUT (), .Z (N42[10]), - .CIN (_N16483), + .CIN (_N16387), .I0 (), .I1 (cnt1_w[10]), .I2 (), @@ -277305,10 +276934,10 @@ module mix_image // LUT = I0&~I1 ; // ../../sources/designs/ov5640/mix_image.v:228 - GTP_LUT5 /* N123_6 */ #( + GTP_LUT5 /* N123_14 */ #( .INIT(32'b00000000000000000000000000000001)) - N123_6 ( - .Z (_N103792), + N123_14 ( + .Z (_N104615), .I0 (rd_w[1]), .I1 (rd_w[2]), .I2 (rd_w[7]), @@ -277316,24 +276945,24 @@ module mix_image .I4 (rd_w[10])); // LUT = ~I0&~I1&~I2&~I3&~I4 ; - GTP_LUT4 /* N123_7 */ #( + GTP_LUT4 /* N123_15 */ #( .INIT(16'b0000000000000001)) - N123_7 ( - .Z (_N103793), + N123_15 ( + .Z (_N104616), .I0 (rd_w[3]), .I1 (rd_w[4]), .I2 (rd_w[5]), .I3 (rd_w[6])); // LUT = ~I0&~I1&~I2&~I3 ; - GTP_LUT4 /* N123_9 */ #( + GTP_LUT4 /* N123_17 */ #( .INIT(16'b0001000000000000)) - N123_9 ( + N123_17 ( .Z (N440[1]), .I0 (rd_w[0]), .I1 (rd_w[9]), - .I2 (_N103792), - .I3 (_N103793)); + .I2 (_N104615), + .I3 (_N104616)); // LUT = ~I0&~I1&I2&I3 ; GTP_LUT5CARRY /* N154_1_1 */ #( @@ -277343,7 +276972,7 @@ module mix_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N154_1_1 ( - .COUT (_N16497), + .COUT (_N16401), .Z (N154[1]), .CIN (), .I0 (rd_w[0]), @@ -277363,9 +276992,9 @@ module mix_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N154_1_2 ( - .COUT (_N16498), + .COUT (_N16402), .Z (N154[2]), - .CIN (_N16497), + .CIN (_N16401), .I0 (rd_w[0]), .I1 (rd_w[1]), .I2 (rd_w[2]), @@ -277383,9 +277012,9 @@ module mix_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N154_1_3 ( - .COUT (_N16499), + .COUT (_N16403), .Z (N154[3]), - .CIN (_N16498), + .CIN (_N16402), .I0 (), .I1 (rd_w[3]), .I2 (), @@ -277403,9 +277032,9 @@ module mix_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N154_1_4 ( - .COUT (_N16500), + .COUT (_N16404), .Z (N154[4]), - .CIN (_N16499), + .CIN (_N16403), .I0 (), .I1 (rd_w[4]), .I2 (), @@ -277423,9 +277052,9 @@ module mix_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N154_1_5 ( - .COUT (_N16501), + .COUT (_N16405), .Z (N154[5]), - .CIN (_N16500), + .CIN (_N16404), .I0 (), .I1 (rd_w[5]), .I2 (), @@ -277443,9 +277072,9 @@ module mix_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N154_1_6 ( - .COUT (_N16502), + .COUT (_N16406), .Z (N154[6]), - .CIN (_N16501), + .CIN (_N16405), .I0 (), .I1 (rd_w[6]), .I2 (), @@ -277463,9 +277092,9 @@ module mix_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N154_1_7 ( - .COUT (_N16503), + .COUT (_N16407), .Z (N154[7]), - .CIN (_N16502), + .CIN (_N16406), .I0 (), .I1 (rd_w[7]), .I2 (), @@ -277483,9 +277112,9 @@ module mix_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N154_1_8 ( - .COUT (_N16504), + .COUT (_N16408), .Z (N154[8]), - .CIN (_N16503), + .CIN (_N16407), .I0 (), .I1 (rd_w[8]), .I2 (), @@ -277503,9 +277132,9 @@ module mix_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N154_1_9 ( - .COUT (_N16505), + .COUT (_N16409), .Z (N154[9]), - .CIN (_N16504), + .CIN (_N16408), .I0 (), .I1 (rd_w[9]), .I2 (), @@ -277525,7 +277154,7 @@ module mix_image N154_1_10 ( .COUT (), .Z (N154[10]), - .CIN (_N16505), + .CIN (_N16409), .I0 (), .I1 (rd_w[10]), .I2 (), @@ -277543,7 +277172,7 @@ module mix_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N187_1_1 ( - .COUT (_N13727), + .COUT (_N13696), .Z (N187[1]), .CIN (), .I0 (rd_h[0]), @@ -277563,9 +277192,9 @@ module mix_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N187_1_2 ( - .COUT (_N13728), + .COUT (_N13697), .Z (N187[2]), - .CIN (_N13727), + .CIN (_N13696), .I0 (rd_h[0]), .I1 (rd_h[1]), .I2 (rd_h[2]), @@ -277583,9 +277212,9 @@ module mix_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N187_1_3 ( - .COUT (_N13729), + .COUT (_N13698), .Z (N187[3]), - .CIN (_N13728), + .CIN (_N13697), .I0 (), .I1 (rd_h[3]), .I2 (), @@ -277603,9 +277232,9 @@ module mix_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N187_1_4 ( - .COUT (_N13730), + .COUT (_N13699), .Z (N187[4]), - .CIN (_N13729), + .CIN (_N13698), .I0 (), .I1 (rd_h[4]), .I2 (), @@ -277623,9 +277252,9 @@ module mix_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N187_1_5 ( - .COUT (_N13731), + .COUT (_N13700), .Z (N187[5]), - .CIN (_N13730), + .CIN (_N13699), .I0 (), .I1 (rd_h[5]), .I2 (), @@ -277643,9 +277272,9 @@ module mix_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N187_1_6 ( - .COUT (_N13732), + .COUT (_N13701), .Z (N187[6]), - .CIN (_N13731), + .CIN (_N13700), .I0 (), .I1 (rd_h[6]), .I2 (), @@ -277663,9 +277292,9 @@ module mix_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N187_1_7 ( - .COUT (_N13733), + .COUT (_N13702), .Z (N187[7]), - .CIN (_N13732), + .CIN (_N13701), .I0 (), .I1 (rd_h[7]), .I2 (), @@ -277683,9 +277312,9 @@ module mix_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N187_1_8 ( - .COUT (_N13734), + .COUT (_N13703), .Z (N187[8]), - .CIN (_N13733), + .CIN (_N13702), .I0 (), .I1 (rd_h[8]), .I2 (), @@ -277703,9 +277332,9 @@ module mix_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N187_1_9 ( - .COUT (_N13735), + .COUT (_N13704), .Z (N187[9]), - .CIN (_N13734), + .CIN (_N13703), .I0 (), .I1 (rd_h[9]), .I2 (), @@ -277725,7 +277354,7 @@ module mix_image N187_1_10 ( .COUT (), .Z (N187[10]), - .CIN (_N13735), + .CIN (_N13704), .I0 (), .I1 (rd_h[10]), .I2 (), @@ -277739,7 +277368,7 @@ module mix_image GTP_LUT4 /* N311_8 */ #( .INIT(16'b1000000000000000)) N311_8 ( - .Z (_N103812), + .Z (_N104635), .I0 (cnt0_w[1]), .I1 (cnt0_w[2]), .I2 (cnt0_w[3]), @@ -277749,7 +277378,7 @@ module mix_image GTP_LUT4 /* N311_9 */ #( .INIT(16'b1000000000000000)) N311_9 ( - .Z (_N103813), + .Z (_N104636), .I0 (cnt0_w[5]), .I1 (cnt0_w[6]), .I2 (cnt0_w[7]), @@ -277763,14 +277392,14 @@ module mix_image .I0 (cnt0_w[0]), .I1 (cnt0_w[8]), .I2 (cnt0_w[9]), - .I3 (_N103812), - .I4 (_N103813)); + .I3 (_N104635), + .I4 (_N104636)); // LUT = I0&~I1&~I2&I3&I4 ; GTP_LUT4 /* N315_8 */ #( .INIT(16'b1000000000000000)) N315_8 ( - .Z (_N103853), + .Z (_N104676), .I0 (cnt1_w[1]), .I1 (cnt1_w[2]), .I2 (cnt1_w[3]), @@ -277780,7 +277409,7 @@ module mix_image GTP_LUT4 /* N315_9 */ #( .INIT(16'b1000000000000000)) N315_9 ( - .Z (_N103854), + .Z (_N104677), .I0 (cnt1_w[5]), .I1 (cnt1_w[6]), .I2 (cnt1_w[7]), @@ -277794,45 +277423,45 @@ module mix_image .I0 (cnt1_w[0]), .I1 (cnt1_w[8]), .I2 (cnt1_w[9]), - .I3 (_N103853), - .I4 (_N103854)); + .I3 (_N104676), + .I4 (_N104677)); // LUT = I0&~I1&~I2&I3&I4 ; - GTP_LUT3 /* N329_4 */ #( + GTP_LUT3 /* N329_3 */ #( .INIT(8'b00000001)) - N329_4 ( - .Z (_N96993), + N329_3 ( + .Z (_N97559), .I0 (rd_w[7]), .I1 (rd_w[8]), .I2 (rd_w[10])); // LUT = ~I0&~I1&~I2 ; - GTP_LUT5 /* N329_17 */ #( + GTP_LUT5 /* N329_16 */ #( .INIT(32'b10000000000000000000000000000000)) - N329_17 ( - .Z (_N103845), - .I0 (_N96993), + N329_16 ( + .Z (_N104668), + .I0 (_N97559), .I1 (rd_w[1]), .I2 (rd_w[2]), .I3 (rd_w[3]), .I4 (rd_w[4])); // LUT = I0&I1&I2&I3&I4 ; - GTP_LUT5 /* N329_18 */ #( + GTP_LUT5 /* N329_17 */ #( .INIT(32'b10000000000000000000000000000000)) - N329_18 ( + N329_17 ( .Z (N329), .I0 (rd_w[0]), .I1 (rd_w[5]), .I2 (rd_w[6]), .I3 (rd_w[9]), - .I4 (_N103845)); + .I4 (_N104668)); // LUT = I0&I1&I2&I3&I4 ; GTP_LUT4 /* N339_8 */ #( .INIT(16'b0000000000000010)) N339_8 ( - .Z (_N103802), + .Z (_N104625), .I0 (rd_h[1]), .I1 (rd_h[7]), .I2 (rd_h[9]), @@ -277842,7 +277471,7 @@ module mix_image GTP_LUT4 /* N339_9 */ #( .INIT(16'b1000000000000000)) N339_9 ( - .Z (_N103803), + .Z (_N104626), .I0 (rd_h[2]), .I1 (rd_h[5]), .I2 (rd_h[6]), @@ -277856,14 +277485,14 @@ module mix_image .I0 (rd_h[0]), .I1 (rd_h[3]), .I2 (rd_h[4]), - .I3 (_N103802), - .I4 (_N103803)); + .I3 (_N104625), + .I4 (_N104626)); // LUT = I0&~I1&~I2&I3&I4 ; GTP_LUT2 /* N365_1 */ #( .INIT(4'b0001)) N365_1 ( - .Z (_N96537), + .Z (_N97291), .I0 (rd_sta0[0]), .I1 (rd_sta0[4])); // LUT = ~I0&~I1 ; @@ -278019,7 +277648,7 @@ module mix_image N427_vname ( .Z (N427), .I0 (rst), - .I1 (_N96537), + .I1 (_N97291), .I2 (rd_sta0[1]), .I3 (rd_sta0[2]), .I4 (rd_sta0[3])); @@ -278033,13 +277662,13 @@ module mix_image \cnt0_h[0] ( .Q (cnt0_h[0]), .CLK (cmos1_pclk), - .D (_N103496)); + .D (_N104308)); // ../../sources/designs/ov5640/mix_image.v:85 GTP_LUT5 /* \cnt0_h_rs_mux[0] */ #( .INIT(32'b01010001111100111010001000000000)) \cnt0_h_rs_mux[0] ( - .Z (_N103496), + .Z (_N104308), .I0 (cmos1_href), .I1 (cmos1_vsync0), .I2 (cmos1_vsync1), @@ -278174,13 +277803,13 @@ module mix_image \cnt1_h[0] ( .Q (cnt1_h[0]), .CLK (cmos2_pclk), - .D (_N103500)); + .D (_N104312)); // ../../sources/designs/ov5640/mix_image.v:121 GTP_LUT5 /* \cnt1_h_rs_mux[0] */ #( .INIT(32'b01010001111100111010001000000000)) \cnt1_h_rs_mux[0] ( - .Z (_N103500), + .Z (_N104312), .I0 (cmos2_href), .I1 (cmos2_vsync0), .I2 (cmos2_vsync1), @@ -278316,7 +277945,7 @@ module mix_image .Q (data_out[0]), .CE (N427), .CLK (clk), - .D (_N76589)); + .D (_N77174)); // ../../sources/designs/ov5640/mix_image.v:368 GTP_DFF_E /* \data_out1[1] */ #( @@ -278326,7 +277955,7 @@ module mix_image .Q (data_out[1]), .CE (N427), .CLK (clk), - .D (_N76642)); + .D (_N77271)); // ../../sources/designs/ov5640/mix_image.v:368 GTP_DFF_E /* \data_out1[2] */ #( @@ -278336,7 +277965,7 @@ module mix_image .Q (data_out[2]), .CE (N427), .CLK (clk), - .D (_N76788)); + .D (_N77314)); // ../../sources/designs/ov5640/mix_image.v:368 GTP_DFF_E /* \data_out1[3] */ #( @@ -278346,7 +277975,7 @@ module mix_image .Q (data_out[3]), .CE (N427), .CLK (clk), - .D (_N76810)); + .D (_N77433)); // ../../sources/designs/ov5640/mix_image.v:368 GTP_DFF_E /* \data_out1[4] */ #( @@ -278356,7 +277985,7 @@ module mix_image .Q (data_out[4]), .CE (N427), .CLK (clk), - .D (_N76927)); + .D (_N77517)); // ../../sources/designs/ov5640/mix_image.v:368 GTP_DFF_E /* \data_out1[5] */ #( @@ -278366,7 +277995,7 @@ module mix_image .Q (data_out[5]), .CE (N427), .CLK (clk), - .D (_N76977)); + .D (_N77607)); // ../../sources/designs/ov5640/mix_image.v:368 GTP_DFF_E /* \data_out1[6] */ #( @@ -278376,7 +278005,7 @@ module mix_image .Q (data_out[6]), .CE (N427), .CLK (clk), - .D (_N77119)); + .D (_N77640)); // ../../sources/designs/ov5640/mix_image.v:368 GTP_DFF_E /* \data_out1[7] */ #( @@ -278386,7 +278015,7 @@ module mix_image .Q (data_out[7]), .CE (N427), .CLK (clk), - .D (_N77189)); + .D (_N77752)); // ../../sources/designs/ov5640/mix_image.v:368 GTP_DFF_E /* \data_out1[8] */ #( @@ -278396,7 +278025,7 @@ module mix_image .Q (data_out[8]), .CE (N427), .CLK (clk), - .D (_N77253)); + .D (_N77847)); // ../../sources/designs/ov5640/mix_image.v:368 GTP_DFF_E /* \data_out1[9] */ #( @@ -278406,7 +278035,7 @@ module mix_image .Q (data_out[9]), .CE (N427), .CLK (clk), - .D (_N77378)); + .D (_N77902)); // ../../sources/designs/ov5640/mix_image.v:368 GTP_DFF_E /* \data_out1[10] */ #( @@ -278416,7 +278045,7 @@ module mix_image .Q (data_out[10]), .CE (N427), .CLK (clk), - .D (_N77417)); + .D (_N78015)); // ../../sources/designs/ov5640/mix_image.v:368 GTP_DFF_E /* \data_out1[11] */ #( @@ -278426,7 +278055,7 @@ module mix_image .Q (data_out[11]), .CE (N427), .CLK (clk), - .D (_N77511)); + .D (_N78107)); // ../../sources/designs/ov5640/mix_image.v:368 GTP_DFF_E /* \data_out1[12] */ #( @@ -278436,7 +278065,7 @@ module mix_image .Q (data_out[12]), .CE (N427), .CLK (clk), - .D (_N77652)); + .D (_N78218)); // ../../sources/designs/ov5640/mix_image.v:368 GTP_DFF_E /* \data_out1[13] */ #( @@ -278446,7 +278075,7 @@ module mix_image .Q (data_out[13]), .CE (N427), .CLK (clk), - .D (_N77693)); + .D (_N78294)); // ../../sources/designs/ov5640/mix_image.v:368 GTP_DFF_E /* \data_out1[14] */ #( @@ -278456,13 +278085,13 @@ module mix_image .Q (data_out[14]), .CE (N427), .CLK (clk), - .D (_N77807)); + .D (_N78320)); // ../../sources/designs/ov5640/mix_image.v:368 GTP_LUT4 /* \data_out1[15:0]_0 */ #( .INIT(16'b1011000110100000)) \data_out1[15:0]_0 ( - .Z (_N76589), + .Z (_N77174), .I0 (N365), .I1 (N367), .I2 (dout1[0]), @@ -278472,152 +278101,152 @@ module mix_image GTP_LUT4 /* \data_out1[15:0]_1 */ #( .INIT(16'b1011000110100000)) \data_out1[15:0]_1 ( - .Z (_N76642), + .Z (_N77271), .I0 (N365), .I1 (N367), .I2 (dout1[1]), .I3 (dout2[1])); // LUT = (I0&I2)|(~I0&~I1&I3) ; - GTP_LUT4 /* \data_out1[15:0]_6 */ #( + GTP_LUT4 /* \data_out1[15:0]_4 */ #( .INIT(16'b1011000110100000)) - \data_out1[15:0]_6 ( - .Z (_N76788), + \data_out1[15:0]_4 ( + .Z (_N77314), .I0 (N365), .I1 (N367), .I2 (dout1[2]), .I3 (dout2[2])); // LUT = (I0&I2)|(~I0&~I1&I3) ; - GTP_LUT4 /* \data_out1[15:0]_10 */ #( - .INIT(16'b0011000100100000)) - \data_out1[15:0]_10 ( - .Z (_N76927), + GTP_LUT4 /* \data_out1[15:0]_9 */ #( + .INIT(16'b1011000110100000)) + \data_out1[15:0]_9 ( + .Z (_N77433), .I0 (N365), .I1 (N367), - .I2 (dout1[4]), - .I3 (dout2[4])); - // LUT = (~I0&~I1&I3)|(I0&~I1&I2) ; + .I2 (dout1[3]), + .I3 (dout2[3])); + // LUT = (I0&I2)|(~I0&~I1&I3) ; - GTP_LUT4 /* \data_out1[15:0]_152 */ #( + GTP_LUT4 /* \data_out1[15:0]_245 */ #( .INIT(16'b1011000110100000)) - \data_out1[15:0]_152 ( - .Z (_N76810), + \data_out1[15:0]_245 ( + .Z (_N77517), .I0 (N365), .I1 (N367), - .I2 (dout1[3]), - .I3 (dout2[3])); + .I2 (dout1[4]), + .I3 (dout2[4])); // LUT = (I0&I2)|(~I0&~I1&I3) ; - GTP_LUT4 /* \data_out1[15:0]_287 */ #( + GTP_LUT4 /* \data_out1[15:0]_317 */ #( .INIT(16'b0011000100100000)) - \data_out1[15:0]_287 ( - .Z (_N76977), + \data_out1[15:0]_317 ( + .Z (_N77607), .I0 (N365), .I1 (N367), .I2 (dout1[5]), .I3 (dout2[5])); // LUT = (~I0&~I1&I3)|(I0&~I1&I2) ; - GTP_LUT4 /* \data_out1[15:0]_405 */ #( - .INIT(16'b0011000100100000)) - \data_out1[15:0]_405 ( - .Z (_N77119), + GTP_LUT4 /* \data_out1[15:0]_343 */ #( + .INIT(16'b1011000110100000)) + \data_out1[15:0]_343 ( + .Z (_N77640), .I0 (N365), .I1 (N367), .I2 (dout1[6]), .I3 (dout2[6])); - // LUT = (~I0&~I1&I3)|(I0&~I1&I2) ; + // LUT = (I0&I2)|(~I0&~I1&I3) ; - GTP_LUT4 /* \data_out1[15:0]_464 */ #( + GTP_LUT4 /* \data_out1[15:0]_435 */ #( .INIT(16'b0011000100100000)) - \data_out1[15:0]_464 ( - .Z (_N77189), + \data_out1[15:0]_435 ( + .Z (_N77752), .I0 (N365), .I1 (N367), .I2 (dout1[7]), .I3 (dout2[7])); // LUT = (~I0&~I1&I3)|(I0&~I1&I2) ; - GTP_LUT4 /* \data_out1[15:0]_516 */ #( + GTP_LUT4 /* \data_out1[15:0]_506 */ #( .INIT(16'b0011000100100000)) - \data_out1[15:0]_516 ( - .Z (_N77253), + \data_out1[15:0]_506 ( + .Z (_N77847), .I0 (N365), .I1 (N367), .I2 (dout1[8]), .I3 (dout2[8])); // LUT = (~I0&~I1&I3)|(I0&~I1&I2) ; - GTP_LUT4 /* \data_out1[15:0]_622 */ #( + GTP_LUT4 /* \data_out1[15:0]_550 */ #( .INIT(16'b1011000110100000)) - \data_out1[15:0]_622 ( - .Z (_N77378), + \data_out1[15:0]_550 ( + .Z (_N77902), .I0 (N365), .I1 (N367), .I2 (dout1[9]), .I3 (dout2[9])); // LUT = (I0&I2)|(~I0&~I1&I3) ; - GTP_LUT4 /* \data_out1[15:0]_656 */ #( - .INIT(16'b1011000110100000)) - \data_out1[15:0]_656 ( - .Z (_N77417), + GTP_LUT4 /* \data_out1[15:0]_638 */ #( + .INIT(16'b0011000100100000)) + \data_out1[15:0]_638 ( + .Z (_N78015), .I0 (N365), .I1 (N367), .I2 (dout1[10]), .I3 (dout2[10])); - // LUT = (I0&I2)|(~I0&~I1&I3) ; + // LUT = (~I0&~I1&I3)|(I0&~I1&I2) ; - GTP_LUT4 /* \data_out1[15:0]_736 */ #( + GTP_LUT4 /* \data_out1[15:0]_713 */ #( .INIT(16'b0011000100100000)) - \data_out1[15:0]_736 ( - .Z (_N77511), + \data_out1[15:0]_713 ( + .Z (_N78107), .I0 (N365), .I1 (N367), .I2 (dout1[11]), .I3 (dout2[11])); // LUT = (~I0&~I1&I3)|(I0&~I1&I2) ; - GTP_LUT4 /* \data_out1[15:0]_852 */ #( - .INIT(16'b0011000100100000)) - \data_out1[15:0]_852 ( - .Z (_N77652), + GTP_LUT4 /* \data_out1[15:0]_807 */ #( + .INIT(16'b1011000110100000)) + \data_out1[15:0]_807 ( + .Z (_N78218), .I0 (N365), .I1 (N367), .I2 (dout1[12]), .I3 (dout2[12])); - // LUT = (~I0&~I1&I3)|(I0&~I1&I2) ; + // LUT = (I0&I2)|(~I0&~I1&I3) ; - GTP_LUT4 /* \data_out1[15:0]_886 */ #( - .INIT(16'b1011000110100000)) - \data_out1[15:0]_886 ( - .Z (_N77693), + GTP_LUT4 /* \data_out1[15:0]_866 */ #( + .INIT(16'b0011000100100000)) + \data_out1[15:0]_866 ( + .Z (_N78294), .I0 (N365), .I1 (N367), .I2 (dout1[13]), .I3 (dout2[13])); - // LUT = (I0&I2)|(~I0&~I1&I3) ; + // LUT = (~I0&~I1&I3)|(I0&~I1&I2) ; - GTP_LUT4 /* \data_out1[15:0]_986 */ #( - .INIT(16'b0011000100100000)) - \data_out1[15:0]_986 ( - .Z (_N77807), + GTP_LUT4 /* \data_out1[15:0]_889 */ #( + .INIT(16'b1011000110100000)) + \data_out1[15:0]_889 ( + .Z (_N78320), .I0 (N365), .I1 (N367), .I2 (dout1[14]), .I3 (dout2[14])); - // LUT = (~I0&~I1&I3)|(I0&~I1&I2) ; + // LUT = (I0&I2)|(~I0&~I1&I3) ; - GTP_LUT4 /* \data_out1[15:0]_1041 */ #( - .INIT(16'b0011000100100000)) - \data_out1[15:0]_1041 ( - .Z (_N77875), + GTP_LUT4 /* \data_out1[15:0]_969 */ #( + .INIT(16'b1011000110100000)) + \data_out1[15:0]_969 ( + .Z (_N78412), .I0 (N365), .I1 (N367), .I2 (dout1[15]), .I3 (dout2[15])); - // LUT = (~I0&~I1&I3)|(I0&~I1&I2) ; + // LUT = (I0&I2)|(~I0&~I1&I3) ; GTP_DFF_E /* \data_out1[15] */ #( .GRS_EN("TRUE"), @@ -278626,7 +278255,7 @@ module mix_image .Q (data_out[15]), .CE (N427), .CLK (clk), - .D (_N77875)); + .D (_N78412)); // ../../sources/designs/ov5640/mix_image.v:368 GTP_DFF_E /* data_out_valid0 */ #( @@ -278666,14 +278295,14 @@ module mix_image .Q (image1_en), .C (rst), .CLK (cmos1_pclk), - .D (_N103303)); + .D (_N104115)); // defparam image1_en_vname.orig_name = image1_en; // ../../sources/designs/ov5640/mix_image.v:63 GTP_LUT3 /* image1_en_ce_mux */ #( .INIT(8'b11110010)) image1_en_ce_mux ( - .Z (_N103303), + .Z (_N104115), .I0 (cmos1_vsync0), .I1 (cmos1_vsync1), .I2 (image1_en)); @@ -278686,14 +278315,14 @@ module mix_image .Q (image2_en), .C (rst), .CLK (cmos2_pclk), - .D (_N103304)); + .D (_N104116)); // defparam image2_en_vname.orig_name = image2_en; // ../../sources/designs/ov5640/mix_image.v:99 GTP_LUT3 /* image2_en_ce_mux */ #( .INIT(8'b11110010)) image2_en_ce_mux ( - .Z (_N103304), + .Z (_N104116), .I0 (cmos2_vsync0), .I1 (cmos2_vsync1), .I2 (image2_en)); @@ -278939,8 +278568,8 @@ module mix_image .I0 (rd_sta[3]), .I1 (rd_w[0]), .I2 (rd_w[9]), - .I3 (_N103792), - .I4 (_N103793)); + .I3 (_N104615), + .I4 (_N104616)); // LUT = I0&~I1&~I2&I3&I4 ; // ../../sources/designs/ov5640/mix_image.v:237 @@ -279230,7 +278859,7 @@ module ov5640 .de_i (cmos1_href_d1), .nt_cmos1_pclk (pclk1), .vs_i (cmos1_vsync_d1)); - // ../../sources/designs/ov5640/ov5640.v:148 + // ../../sources/designs/ov5640/ov5640.v:129 GTP_DFF /* \cmos1_d_d0[0] */ #( .GRS_EN("TRUE"), @@ -279239,7 +278868,7 @@ module ov5640 .Q (cmos1_d_d0[0]), .CLK (pclk1), .D (cmos1_data[0])); - // ../../sources/designs/ov5640/ov5640.v:113 + // ../../sources/designs/ov5640/ov5640.v:94 GTP_DFF /* \cmos1_d_d0[1] */ #( .GRS_EN("TRUE"), @@ -279248,7 +278877,7 @@ module ov5640 .Q (cmos1_d_d0[1]), .CLK (pclk1), .D (cmos1_data[1])); - // ../../sources/designs/ov5640/ov5640.v:113 + // ../../sources/designs/ov5640/ov5640.v:94 GTP_DFF /* \cmos1_d_d0[2] */ #( .GRS_EN("TRUE"), @@ -279257,7 +278886,7 @@ module ov5640 .Q (cmos1_d_d0[2]), .CLK (pclk1), .D (cmos1_data[2])); - // ../../sources/designs/ov5640/ov5640.v:113 + // ../../sources/designs/ov5640/ov5640.v:94 GTP_DFF /* \cmos1_d_d0[3] */ #( .GRS_EN("TRUE"), @@ -279266,7 +278895,7 @@ module ov5640 .Q (cmos1_d_d0[3]), .CLK (pclk1), .D (cmos1_data[3])); - // ../../sources/designs/ov5640/ov5640.v:113 + // ../../sources/designs/ov5640/ov5640.v:94 GTP_DFF /* \cmos1_d_d0[4] */ #( .GRS_EN("TRUE"), @@ -279275,7 +278904,7 @@ module ov5640 .Q (cmos1_d_d0[4]), .CLK (pclk1), .D (cmos1_data[4])); - // ../../sources/designs/ov5640/ov5640.v:113 + // ../../sources/designs/ov5640/ov5640.v:94 GTP_DFF /* \cmos1_d_d0[5] */ #( .GRS_EN("TRUE"), @@ -279284,7 +278913,7 @@ module ov5640 .Q (cmos1_d_d0[5]), .CLK (pclk1), .D (cmos1_data[5])); - // ../../sources/designs/ov5640/ov5640.v:113 + // ../../sources/designs/ov5640/ov5640.v:94 GTP_DFF /* \cmos1_d_d0[6] */ #( .GRS_EN("TRUE"), @@ -279293,7 +278922,7 @@ module ov5640 .Q (cmos1_d_d0[6]), .CLK (pclk1), .D (cmos1_data[6])); - // ../../sources/designs/ov5640/ov5640.v:113 + // ../../sources/designs/ov5640/ov5640.v:94 GTP_DFF /* \cmos1_d_d0[7] */ #( .GRS_EN("TRUE"), @@ -279302,7 +278931,7 @@ module ov5640 .Q (cmos1_d_d0[7]), .CLK (pclk1), .D (cmos1_data[7])); - // ../../sources/designs/ov5640/ov5640.v:113 + // ../../sources/designs/ov5640/ov5640.v:94 GTP_DFF /* \cmos1_d_d1[0] */ #( .GRS_EN("TRUE"), @@ -279311,7 +278940,7 @@ module ov5640 .Q (cmos1_d_d1[0]), .CLK (pclk1), .D (cmos1_d_d0[0])); - // ../../sources/designs/ov5640/ov5640.v:113 + // ../../sources/designs/ov5640/ov5640.v:94 GTP_DFF /* \cmos1_d_d1[1] */ #( .GRS_EN("TRUE"), @@ -279320,7 +278949,7 @@ module ov5640 .Q (cmos1_d_d1[1]), .CLK (pclk1), .D (cmos1_d_d0[1])); - // ../../sources/designs/ov5640/ov5640.v:113 + // ../../sources/designs/ov5640/ov5640.v:94 GTP_DFF /* \cmos1_d_d1[2] */ #( .GRS_EN("TRUE"), @@ -279329,7 +278958,7 @@ module ov5640 .Q (cmos1_d_d1[2]), .CLK (pclk1), .D (cmos1_d_d0[2])); - // ../../sources/designs/ov5640/ov5640.v:113 + // ../../sources/designs/ov5640/ov5640.v:94 GTP_DFF /* \cmos1_d_d1[3] */ #( .GRS_EN("TRUE"), @@ -279338,7 +278967,7 @@ module ov5640 .Q (cmos1_d_d1[3]), .CLK (pclk1), .D (cmos1_d_d0[3])); - // ../../sources/designs/ov5640/ov5640.v:113 + // ../../sources/designs/ov5640/ov5640.v:94 GTP_DFF /* \cmos1_d_d1[4] */ #( .GRS_EN("TRUE"), @@ -279347,7 +278976,7 @@ module ov5640 .Q (cmos1_d_d1[4]), .CLK (pclk1), .D (cmos1_d_d0[4])); - // ../../sources/designs/ov5640/ov5640.v:113 + // ../../sources/designs/ov5640/ov5640.v:94 GTP_DFF /* \cmos1_d_d1[5] */ #( .GRS_EN("TRUE"), @@ -279356,7 +278985,7 @@ module ov5640 .Q (cmos1_d_d1[5]), .CLK (pclk1), .D (cmos1_d_d0[5])); - // ../../sources/designs/ov5640/ov5640.v:113 + // ../../sources/designs/ov5640/ov5640.v:94 GTP_DFF /* \cmos1_d_d1[6] */ #( .GRS_EN("TRUE"), @@ -279365,7 +278994,7 @@ module ov5640 .Q (cmos1_d_d1[6]), .CLK (pclk1), .D (cmos1_d_d0[6])); - // ../../sources/designs/ov5640/ov5640.v:113 + // ../../sources/designs/ov5640/ov5640.v:94 GTP_DFF /* \cmos1_d_d1[7] */ #( .GRS_EN("TRUE"), @@ -279374,7 +279003,7 @@ module ov5640 .Q (cmos1_d_d1[7]), .CLK (pclk1), .D (cmos1_d_d0[7])); - // ../../sources/designs/ov5640/ov5640.v:113 + // ../../sources/designs/ov5640/ov5640.v:94 GTP_DFF /* cmos1_href_d0 */ #( .GRS_EN("TRUE"), @@ -279384,7 +279013,7 @@ module ov5640 .CLK (pclk1), .D (cmos1_href)); // defparam cmos1_href_d0_vname.orig_name = cmos1_href_d0; - // ../../sources/designs/ov5640/ov5640.v:113 + // ../../sources/designs/ov5640/ov5640.v:94 GTP_DFF /* cmos1_href_d1 */ #( .GRS_EN("TRUE"), @@ -279394,7 +279023,7 @@ module ov5640 .CLK (pclk1), .D (cmos1_href_d0)); // defparam cmos1_href_d1_vname.orig_name = cmos1_href_d1; - // ../../sources/designs/ov5640/ov5640.v:113 + // ../../sources/designs/ov5640/ov5640.v:94 GTP_DFF /* cmos1_vsync_d0 */ #( .GRS_EN("TRUE"), @@ -279404,7 +279033,7 @@ module ov5640 .CLK (pclk1), .D (cmos1_vsync)); // defparam cmos1_vsync_d0_vname.orig_name = cmos1_vsync_d0; - // ../../sources/designs/ov5640/ov5640.v:113 + // ../../sources/designs/ov5640/ov5640.v:94 GTP_DFF /* cmos1_vsync_d1 */ #( .GRS_EN("TRUE"), @@ -279414,7 +279043,7 @@ module ov5640 .CLK (pclk1), .D (cmos1_vsync_d0)); // defparam cmos1_vsync_d1_vname.orig_name = cmos1_vsync_d1; - // ../../sources/designs/ov5640/ov5640.v:113 + // ../../sources/designs/ov5640/ov5640.v:94 cmos_8_16bit_unq4 cmos2_8_16bit ( .image_data (cmos2_d_16bit), @@ -279426,7 +279055,7 @@ module ov5640 .de_i (cmos2_href_d1), .nt_cmos2_pclk (pclk2), .vs_i (cmos2_vsync_d1)); - // ../../sources/designs/ov5640/ov5640.v:161 + // ../../sources/designs/ov5640/ov5640.v:142 GTP_DFF /* \cmos2_d_d0[0] */ #( .GRS_EN("TRUE"), @@ -279435,7 +279064,7 @@ module ov5640 .Q (cmos2_d_d0[0]), .CLK (pclk2), .D (cmos2_data[0])); - // ../../sources/designs/ov5640/ov5640.v:140 + // ../../sources/designs/ov5640/ov5640.v:121 GTP_DFF /* \cmos2_d_d0[1] */ #( .GRS_EN("TRUE"), @@ -279444,7 +279073,7 @@ module ov5640 .Q (cmos2_d_d0[1]), .CLK (pclk2), .D (cmos2_data[1])); - // ../../sources/designs/ov5640/ov5640.v:140 + // ../../sources/designs/ov5640/ov5640.v:121 GTP_DFF /* \cmos2_d_d0[2] */ #( .GRS_EN("TRUE"), @@ -279453,7 +279082,7 @@ module ov5640 .Q (cmos2_d_d0[2]), .CLK (pclk2), .D (cmos2_data[2])); - // ../../sources/designs/ov5640/ov5640.v:140 + // ../../sources/designs/ov5640/ov5640.v:121 GTP_DFF /* \cmos2_d_d0[3] */ #( .GRS_EN("TRUE"), @@ -279462,7 +279091,7 @@ module ov5640 .Q (cmos2_d_d0[3]), .CLK (pclk2), .D (cmos2_data[3])); - // ../../sources/designs/ov5640/ov5640.v:140 + // ../../sources/designs/ov5640/ov5640.v:121 GTP_DFF /* \cmos2_d_d0[4] */ #( .GRS_EN("TRUE"), @@ -279471,7 +279100,7 @@ module ov5640 .Q (cmos2_d_d0[4]), .CLK (pclk2), .D (cmos2_data[4])); - // ../../sources/designs/ov5640/ov5640.v:140 + // ../../sources/designs/ov5640/ov5640.v:121 GTP_DFF /* \cmos2_d_d0[5] */ #( .GRS_EN("TRUE"), @@ -279480,7 +279109,7 @@ module ov5640 .Q (cmos2_d_d0[5]), .CLK (pclk2), .D (cmos2_data[5])); - // ../../sources/designs/ov5640/ov5640.v:140 + // ../../sources/designs/ov5640/ov5640.v:121 GTP_DFF /* \cmos2_d_d0[6] */ #( .GRS_EN("TRUE"), @@ -279489,7 +279118,7 @@ module ov5640 .Q (cmos2_d_d0[6]), .CLK (pclk2), .D (cmos2_data[6])); - // ../../sources/designs/ov5640/ov5640.v:140 + // ../../sources/designs/ov5640/ov5640.v:121 GTP_DFF /* \cmos2_d_d0[7] */ #( .GRS_EN("TRUE"), @@ -279498,7 +279127,7 @@ module ov5640 .Q (cmos2_d_d0[7]), .CLK (pclk2), .D (cmos2_data[7])); - // ../../sources/designs/ov5640/ov5640.v:140 + // ../../sources/designs/ov5640/ov5640.v:121 GTP_DFF /* \cmos2_d_d1[0] */ #( .GRS_EN("TRUE"), @@ -279507,7 +279136,7 @@ module ov5640 .Q (cmos2_d_d1[0]), .CLK (pclk2), .D (cmos2_d_d0[0])); - // ../../sources/designs/ov5640/ov5640.v:140 + // ../../sources/designs/ov5640/ov5640.v:121 GTP_DFF /* \cmos2_d_d1[1] */ #( .GRS_EN("TRUE"), @@ -279516,7 +279145,7 @@ module ov5640 .Q (cmos2_d_d1[1]), .CLK (pclk2), .D (cmos2_d_d0[1])); - // ../../sources/designs/ov5640/ov5640.v:140 + // ../../sources/designs/ov5640/ov5640.v:121 GTP_DFF /* \cmos2_d_d1[2] */ #( .GRS_EN("TRUE"), @@ -279525,7 +279154,7 @@ module ov5640 .Q (cmos2_d_d1[2]), .CLK (pclk2), .D (cmos2_d_d0[2])); - // ../../sources/designs/ov5640/ov5640.v:140 + // ../../sources/designs/ov5640/ov5640.v:121 GTP_DFF /* \cmos2_d_d1[3] */ #( .GRS_EN("TRUE"), @@ -279534,7 +279163,7 @@ module ov5640 .Q (cmos2_d_d1[3]), .CLK (pclk2), .D (cmos2_d_d0[3])); - // ../../sources/designs/ov5640/ov5640.v:140 + // ../../sources/designs/ov5640/ov5640.v:121 GTP_DFF /* \cmos2_d_d1[4] */ #( .GRS_EN("TRUE"), @@ -279543,7 +279172,7 @@ module ov5640 .Q (cmos2_d_d1[4]), .CLK (pclk2), .D (cmos2_d_d0[4])); - // ../../sources/designs/ov5640/ov5640.v:140 + // ../../sources/designs/ov5640/ov5640.v:121 GTP_DFF /* \cmos2_d_d1[5] */ #( .GRS_EN("TRUE"), @@ -279552,7 +279181,7 @@ module ov5640 .Q (cmos2_d_d1[5]), .CLK (pclk2), .D (cmos2_d_d0[5])); - // ../../sources/designs/ov5640/ov5640.v:140 + // ../../sources/designs/ov5640/ov5640.v:121 GTP_DFF /* \cmos2_d_d1[6] */ #( .GRS_EN("TRUE"), @@ -279561,7 +279190,7 @@ module ov5640 .Q (cmos2_d_d1[6]), .CLK (pclk2), .D (cmos2_d_d0[6])); - // ../../sources/designs/ov5640/ov5640.v:140 + // ../../sources/designs/ov5640/ov5640.v:121 GTP_DFF /* \cmos2_d_d1[7] */ #( .GRS_EN("TRUE"), @@ -279570,7 +279199,7 @@ module ov5640 .Q (cmos2_d_d1[7]), .CLK (pclk2), .D (cmos2_d_d0[7])); - // ../../sources/designs/ov5640/ov5640.v:140 + // ../../sources/designs/ov5640/ov5640.v:121 GTP_DFF /* cmos2_href_d0 */ #( .GRS_EN("TRUE"), @@ -279580,7 +279209,7 @@ module ov5640 .CLK (pclk2), .D (cmos2_href)); // defparam cmos2_href_d0_vname.orig_name = cmos2_href_d0; - // ../../sources/designs/ov5640/ov5640.v:140 + // ../../sources/designs/ov5640/ov5640.v:121 GTP_DFF /* cmos2_href_d1 */ #( .GRS_EN("TRUE"), @@ -279590,7 +279219,7 @@ module ov5640 .CLK (pclk2), .D (cmos2_href_d0)); // defparam cmos2_href_d1_vname.orig_name = cmos2_href_d1; - // ../../sources/designs/ov5640/ov5640.v:140 + // ../../sources/designs/ov5640/ov5640.v:121 GTP_DFF /* cmos2_vsync_d0 */ #( .GRS_EN("TRUE"), @@ -279600,7 +279229,7 @@ module ov5640 .CLK (pclk2), .D (cmos2_vsync)); // defparam cmos2_vsync_d0_vname.orig_name = cmos2_vsync_d0; - // ../../sources/designs/ov5640/ov5640.v:140 + // ../../sources/designs/ov5640/ov5640.v:121 GTP_DFF /* cmos2_vsync_d1 */ #( .GRS_EN("TRUE"), @@ -279610,7 +279239,7 @@ module ov5640 .CLK (pclk2), .D (cmos2_vsync_d0)); // defparam cmos2_vsync_d1_vname.orig_name = cmos2_vsync_d1; - // ../../sources/designs/ov5640/ov5640.v:140 + // ../../sources/designs/ov5640/ov5640.v:121 reg_config coms1_reg_config ( .N4 (\coms1_reg_config/N4 ), @@ -279619,7 +279248,7 @@ module ov5640 .\u1/reg_sdat (\coms1_reg_config/u1/reg_sdat ), .clk_25M (clk_25M), .nt_cmos1_reset (nt_cmos1_reset)); - // ../../sources/designs/ov5640/ov5640.v:71 + // ../../sources/designs/ov5640/ov5640.v:52 reg_config_unq4 coms2_reg_config ( .i2c_sclk (cmos2_scl), @@ -279628,13 +279257,13 @@ module ov5640 .N4 (\coms1_reg_config/N4 ), .clk_25M (clk_25M), .nt_cmos1_reset (nt_cmos1_reset)); - // ../../sources/designs/ov5640/ov5640.v:83 + // ../../sources/designs/ov5640/ov5640.v:64 power_on_delay power_on_delay_inst ( .nt_cmos1_reset (nt_cmos1_reset), .clk_50M (clk_50M), .rd3_rst (rst)); - // ../../sources/designs/ov5640/ov5640.v:62 + // ../../sources/designs/ov5640/ov5640.v:43 mix_image u_mix_image ( .data_out (data_out), @@ -279654,7 +279283,7 @@ module ov5640 .cmos2_vsync0 (\cmos2_8_16bit/vs_in0 ), .cmos2_vsync1 (\cmos2_8_16bit/vs_in1 ), .rst (rst)); - // ../../sources/designs/ov5640/ov5640.v:201 + // ../../sources/designs/ov5640/ov5640.v:182 endmodule @@ -279663,12 +279292,10 @@ endmodule module rotate_mult0_1 ( input [12:0] B, - input [10:0] \u_rotate_image/N290 , + input [10:0] \u_rotate_image/N338 , input [23:0] \u_rotate_image/mult_p0[1] , input CLK, input N139_0, - input _N12940, - input _N12941, input _N12942, input _N12943, input _N12944, @@ -279692,10 +279319,10 @@ module rotate_mult0_1 input _N12962, input _N12963, input _N12964, + input _N12965, + input _N12966, output [24:0] \u_rotate_image/w_mult_add ); - wire _N12556; - wire _N12557; wire _N12558; wire _N12559; wire _N12560; @@ -279717,6 +279344,8 @@ module rotate_mult0_1 wire _N12576; wire _N12577; wire _N12578; + wire _N12579; + wire _N12580; wire \N2_CPO[0]_floating ; wire \N2_CPO[1]_floating ; wire \N2_CPO[2]_floating ; @@ -279830,14 +279459,14 @@ module rotate_mult0_1 .CPO (), .CXBO (), .CXO (), - .P ({_N12578, _N12577, _N12576, _N12575, _N12574, _N12573, _N12572, _N12571, _N12570, _N12569, _N12568, _N12567, _N12566, _N12565, _N12564, _N12563, _N12562, _N12561, _N12560, _N12559, _N12558, _N12557, _N12556, \u_rotate_image/w_mult_add [24] , \u_rotate_image/w_mult_add [23] , \u_rotate_image/w_mult_add [22] , \u_rotate_image/w_mult_add [21] , \u_rotate_image/w_mult_add [20] , \u_rotate_image/w_mult_add [19] , \u_rotate_image/w_mult_add [18] , \u_rotate_image/w_mult_add [17] , \u_rotate_image/w_mult_add [16] , \u_rotate_image/w_mult_add [15] , \u_rotate_image/w_mult_add [14] , \u_rotate_image/w_mult_add [13] , \u_rotate_image/w_mult_add [12] , \u_rotate_image/w_mult_add [11] , \u_rotate_image/w_mult_add [10] , \u_rotate_image/w_mult_add [9] , \u_rotate_image/w_mult_add [8] , \u_rotate_image/w_mult_add [7] , \u_rotate_image/w_mult_add [6] , \u_rotate_image/w_mult_add [5] , \u_rotate_image/w_mult_add [4] , \u_rotate_image/w_mult_add [3] , \u_rotate_image/w_mult_add [2] , \u_rotate_image/w_mult_add [1] , \u_rotate_image/w_mult_add [0] }), - .CPI ({_N12964, _N12963, _N12962, _N12961, _N12960, _N12959, _N12958, _N12957, _N12956, _N12955, _N12954, _N12953, _N12952, _N12951, _N12950, _N12949, _N12948, _N12947, _N12946, _N12945, _N12944, _N12943, _N12942, _N12941, _N12940, \u_rotate_image/mult_p0[1] [22] , \u_rotate_image/mult_p0[1] [21] , \u_rotate_image/mult_p0[1] [20] , \u_rotate_image/mult_p0[1] [19] , \u_rotate_image/mult_p0[1] [18] , \u_rotate_image/mult_p0[1] [17] , \u_rotate_image/mult_p0[1] [16] , \u_rotate_image/mult_p0[1] [15] , \u_rotate_image/mult_p0[1] [14] , \u_rotate_image/mult_p0[1] [13] , \u_rotate_image/mult_p0[1] [12] , \u_rotate_image/mult_p0[1] [11] , \u_rotate_image/mult_p0[1] [10] , \u_rotate_image/mult_p0[1] [9] , \u_rotate_image/mult_p0[1] [8] , \u_rotate_image/mult_p0[1] [7] , \u_rotate_image/mult_p0[1] [6] , \u_rotate_image/mult_p0[1] [5] , \u_rotate_image/mult_p0[1] [4] , \u_rotate_image/mult_p0[1] [3] , \u_rotate_image/mult_p0[1] [2] , \u_rotate_image/mult_p0[1] [1] , \u_rotate_image/mult_p0[1] [0] }), + .P ({_N12580, _N12579, _N12578, _N12577, _N12576, _N12575, _N12574, _N12573, _N12572, _N12571, _N12570, _N12569, _N12568, _N12567, _N12566, _N12565, _N12564, _N12563, _N12562, _N12561, _N12560, _N12559, _N12558, \u_rotate_image/w_mult_add [24] , \u_rotate_image/w_mult_add [23] , \u_rotate_image/w_mult_add [22] , \u_rotate_image/w_mult_add [21] , \u_rotate_image/w_mult_add [20] , \u_rotate_image/w_mult_add [19] , \u_rotate_image/w_mult_add [18] , \u_rotate_image/w_mult_add [17] , \u_rotate_image/w_mult_add [16] , \u_rotate_image/w_mult_add [15] , \u_rotate_image/w_mult_add [14] , \u_rotate_image/w_mult_add [13] , \u_rotate_image/w_mult_add [12] , \u_rotate_image/w_mult_add [11] , \u_rotate_image/w_mult_add [10] , \u_rotate_image/w_mult_add [9] , \u_rotate_image/w_mult_add [8] , \u_rotate_image/w_mult_add [7] , \u_rotate_image/w_mult_add [6] , \u_rotate_image/w_mult_add [5] , \u_rotate_image/w_mult_add [4] , \u_rotate_image/w_mult_add [3] , \u_rotate_image/w_mult_add [2] , \u_rotate_image/w_mult_add [1] , \u_rotate_image/w_mult_add [0] }), + .CPI ({_N12966, _N12965, _N12964, _N12963, _N12962, _N12961, _N12960, _N12959, _N12958, _N12957, _N12956, _N12955, _N12954, _N12953, _N12952, _N12951, _N12950, _N12949, _N12948, _N12947, _N12946, _N12945, _N12944, _N12943, _N12942, \u_rotate_image/mult_p0[1] [22] , \u_rotate_image/mult_p0[1] [21] , \u_rotate_image/mult_p0[1] [20] , \u_rotate_image/mult_p0[1] [19] , \u_rotate_image/mult_p0[1] [18] , \u_rotate_image/mult_p0[1] [17] , \u_rotate_image/mult_p0[1] [16] , \u_rotate_image/mult_p0[1] [15] , \u_rotate_image/mult_p0[1] [14] , \u_rotate_image/mult_p0[1] [13] , \u_rotate_image/mult_p0[1] [12] , \u_rotate_image/mult_p0[1] [11] , \u_rotate_image/mult_p0[1] [10] , \u_rotate_image/mult_p0[1] [9] , \u_rotate_image/mult_p0[1] [8] , \u_rotate_image/mult_p0[1] [7] , \u_rotate_image/mult_p0[1] [6] , \u_rotate_image/mult_p0[1] [5] , \u_rotate_image/mult_p0[1] [4] , \u_rotate_image/mult_p0[1] [3] , \u_rotate_image/mult_p0[1] [2] , \u_rotate_image/mult_p0[1] [1] , \u_rotate_image/mult_p0[1] [0] }), .CXBI (), .CXI (), .MODEY ({1'b0, 1'b0, 1'b0}), .MODEZ ({1'b0, 1'b1, 1'b1, 1'b0}), .X ({B[11], B[11], B[11], B[11], B[11], B[11], B[11], B[10], B[9], B[8], B[7], B[6], B[5], B[4], B[3], B[2], B[1], B[0]}), - .Y ({\u_rotate_image/N290 [10] , \u_rotate_image/N290 [10] , \u_rotate_image/N290 [10] , \u_rotate_image/N290 [10] , \u_rotate_image/N290 [10] , \u_rotate_image/N290 [10] , \u_rotate_image/N290 [10] , \u_rotate_image/N290 [10] , \u_rotate_image/N290 [9] , \u_rotate_image/N290 [8] , \u_rotate_image/N290 [7] , \u_rotate_image/N290 [6] , \u_rotate_image/N290 [5] , \u_rotate_image/N290 [4] , \u_rotate_image/N290 [3] , \u_rotate_image/N290 [2] , \u_rotate_image/N290 [1] , \u_rotate_image/N290 [0] }), + .Y ({\u_rotate_image/N338 [10] , \u_rotate_image/N338 [10] , \u_rotate_image/N338 [10] , \u_rotate_image/N338 [10] , \u_rotate_image/N338 [10] , \u_rotate_image/N338 [10] , \u_rotate_image/N338 [10] , \u_rotate_image/N338 [10] , \u_rotate_image/N338 [9] , \u_rotate_image/N338 [8] , \u_rotate_image/N338 [7] , \u_rotate_image/N338 [6] , \u_rotate_image/N338 [5] , \u_rotate_image/N338 [4] , \u_rotate_image/N338 [3] , \u_rotate_image/N338 [2] , \u_rotate_image/N338 [1] , \u_rotate_image/N338 [0] }), .Z (), .COUT (), .CEM (1'b1), @@ -279870,12 +279499,10 @@ endmodule module rotate_mult0_1_unq8 ( input [12:0] B, - input [10:0] \u_rotate_image/N301 , + input [10:0] \u_rotate_image/N349 , input CLK, - input \u_rotate_image/N302 , + input \u_rotate_image/N350 , output [23:0] P, - output _N12940, - output _N12941, output _N12942, output _N12943, output _N12944, @@ -279898,10 +279525,10 @@ module rotate_mult0_1_unq8 output _N12961, output _N12962, output _N12963, - output _N12964 + output _N12964, + output _N12965, + output _N12966 ); - wire _N11545; - wire _N11546; wire _N11547; wire _N11548; wire _N11549; @@ -279925,6 +279552,8 @@ module rotate_mult0_1_unq8 wire _N11567; wire _N11568; wire _N11569; + wire _N11570; + wire _N11571; wire \N2_CXBO[0]_floating ; wire \N2_CXBO[1]_floating ; wire \N2_CXBO[2]_floating ; @@ -280010,17 +279639,17 @@ module rotate_mult0_1_unq8 .USE_POSTADD(0), .Z_INIT(48'b000000000000000000000000000000000000000000000000)) N2 ( - .CPO ({_N12964, _N12963, _N12962, _N12961, _N12960, _N12959, _N12958, _N12957, _N12956, _N12955, _N12954, _N12953, _N12952, _N12951, _N12950, _N12949, _N12948, _N12947, _N12946, _N12945, _N12944, _N12943, _N12942, _N12941, _N12940, P[22], P[21], P[20], P[19], P[18], P[17], P[16], P[15], P[14], P[13], P[12], P[11], P[10], P[9], P[8], P[7], P[6], P[5], P[4], P[3], P[2], P[1], P[0]}), + .CPO ({_N12966, _N12965, _N12964, _N12963, _N12962, _N12961, _N12960, _N12959, _N12958, _N12957, _N12956, _N12955, _N12954, _N12953, _N12952, _N12951, _N12950, _N12949, _N12948, _N12947, _N12946, _N12945, _N12944, _N12943, _N12942, P[22], P[21], P[20], P[19], P[18], P[17], P[16], P[15], P[14], P[13], P[12], P[11], P[10], P[9], P[8], P[7], P[6], P[5], P[4], P[3], P[2], P[1], P[0]}), .CXBO (), .CXO (), - .P ({_N11569, _N11568, _N11567, _N11566, _N11565, _N11564, _N11563, _N11562, _N11561, _N11560, _N11559, _N11558, _N11557, _N11556, _N11555, _N11554, _N11553, _N11552, _N11551, _N11550, _N11549, _N11548, _N11547, _N11546, _N11545, \N2_P[22]_floating , \N2_P[21]_floating , \N2_P[20]_floating , \N2_P[19]_floating , \N2_P[18]_floating , \N2_P[17]_floating , \N2_P[16]_floating , \N2_P[15]_floating , \N2_P[14]_floating , \N2_P[13]_floating , \N2_P[12]_floating , \N2_P[11]_floating , \N2_P[10]_floating , \N2_P[9]_floating , \N2_P[8]_floating , \N2_P[7]_floating , \N2_P[6]_floating , \N2_P[5]_floating , \N2_P[4]_floating , \N2_P[3]_floating , \N2_P[2]_floating , \N2_P[1]_floating , \N2_P[0]_floating }), + .P ({_N11571, _N11570, _N11569, _N11568, _N11567, _N11566, _N11565, _N11564, _N11563, _N11562, _N11561, _N11560, _N11559, _N11558, _N11557, _N11556, _N11555, _N11554, _N11553, _N11552, _N11551, _N11550, _N11549, _N11548, _N11547, \N2_P[22]_floating , \N2_P[21]_floating , \N2_P[20]_floating , \N2_P[19]_floating , \N2_P[18]_floating , \N2_P[17]_floating , \N2_P[16]_floating , \N2_P[15]_floating , \N2_P[14]_floating , \N2_P[13]_floating , \N2_P[12]_floating , \N2_P[11]_floating , \N2_P[10]_floating , \N2_P[9]_floating , \N2_P[8]_floating , \N2_P[7]_floating , \N2_P[6]_floating , \N2_P[5]_floating , \N2_P[4]_floating , \N2_P[3]_floating , \N2_P[2]_floating , \N2_P[1]_floating , \N2_P[0]_floating }), .CPI (), .CXBI (), .CXI (), .MODEY ({1'b0, 1'b0, 1'b0}), .MODEZ ({1'b0, 1'b0, 1'b0, 1'b0}), .X ({B[11], B[11], B[11], B[11], B[11], B[11], B[11], B[10], B[9], B[8], B[7], B[6], B[5], B[4], B[3], B[2], B[1], B[0]}), - .Y ({\u_rotate_image/N301 [10] , \u_rotate_image/N301 [10] , \u_rotate_image/N301 [10] , \u_rotate_image/N301 [10] , \u_rotate_image/N301 [10] , \u_rotate_image/N301 [10] , \u_rotate_image/N301 [10] , \u_rotate_image/N301 [10] , \u_rotate_image/N301 [9] , \u_rotate_image/N301 [8] , \u_rotate_image/N301 [7] , \u_rotate_image/N301 [6] , \u_rotate_image/N301 [5] , \u_rotate_image/N301 [4] , \u_rotate_image/N301 [3] , \u_rotate_image/N301 [2] , \u_rotate_image/N301 [1] , \u_rotate_image/N301 [0] }), + .Y ({\u_rotate_image/N349 [10] , \u_rotate_image/N349 [10] , \u_rotate_image/N349 [10] , \u_rotate_image/N349 [10] , \u_rotate_image/N349 [10] , \u_rotate_image/N349 [10] , \u_rotate_image/N349 [10] , \u_rotate_image/N349 [10] , \u_rotate_image/N349 [9] , \u_rotate_image/N349 [8] , \u_rotate_image/N349 [7] , \u_rotate_image/N349 [6] , \u_rotate_image/N349 [5] , \u_rotate_image/N349 [4] , \u_rotate_image/N349 [3] , \u_rotate_image/N349 [2] , \u_rotate_image/N349 [1] , \u_rotate_image/N349 [0] }), .Z (), .COUT (), .CEM (1'b1), @@ -280030,7 +279659,7 @@ module rotate_mult0_1_unq8 .CEP (), .CEPRE (), .CEX (), - .CEY (\u_rotate_image/N302 ), + .CEY (\u_rotate_image/N350 ), .CEZ (), .CIN (), .CLK (CLK), @@ -280053,12 +279682,10 @@ endmodule module rotate_mult0_1_unq10 ( input [12:0] B, - input [10:0] \u_rotate_image/N290 , + input [10:0] \u_rotate_image/N338 , input CLK, input N139_0, output [23:0] P, - output _N12915, - output _N12916, output _N12917, output _N12918, output _N12919, @@ -280081,10 +279708,10 @@ module rotate_mult0_1_unq10 output _N12936, output _N12937, output _N12938, - output _N12939 + output _N12939, + output _N12940, + output _N12941 ); - wire _N11594; - wire _N11595; wire _N11596; wire _N11597; wire _N11598; @@ -280108,6 +279735,8 @@ module rotate_mult0_1_unq10 wire _N11616; wire _N11617; wire _N11618; + wire _N11619; + wire _N11620; wire \N2_CXBO[0]_floating ; wire \N2_CXBO[1]_floating ; wire \N2_CXBO[2]_floating ; @@ -280193,17 +279822,17 @@ module rotate_mult0_1_unq10 .USE_POSTADD(0), .Z_INIT(48'b000000000000000000000000000000000000000000000000)) N2 ( - .CPO ({_N12939, _N12938, _N12937, _N12936, _N12935, _N12934, _N12933, _N12932, _N12931, _N12930, _N12929, _N12928, _N12927, _N12926, _N12925, _N12924, _N12923, _N12922, _N12921, _N12920, _N12919, _N12918, _N12917, _N12916, _N12915, P[22], P[21], P[20], P[19], P[18], P[17], P[16], P[15], P[14], P[13], P[12], P[11], P[10], P[9], P[8], P[7], P[6], P[5], P[4], P[3], P[2], P[1], P[0]}), + .CPO ({_N12941, _N12940, _N12939, _N12938, _N12937, _N12936, _N12935, _N12934, _N12933, _N12932, _N12931, _N12930, _N12929, _N12928, _N12927, _N12926, _N12925, _N12924, _N12923, _N12922, _N12921, _N12920, _N12919, _N12918, _N12917, P[22], P[21], P[20], P[19], P[18], P[17], P[16], P[15], P[14], P[13], P[12], P[11], P[10], P[9], P[8], P[7], P[6], P[5], P[4], P[3], P[2], P[1], P[0]}), .CXBO (), .CXO (), - .P ({_N11618, _N11617, _N11616, _N11615, _N11614, _N11613, _N11612, _N11611, _N11610, _N11609, _N11608, _N11607, _N11606, _N11605, _N11604, _N11603, _N11602, _N11601, _N11600, _N11599, _N11598, _N11597, _N11596, _N11595, _N11594, \N2_P[22]_floating , \N2_P[21]_floating , \N2_P[20]_floating , \N2_P[19]_floating , \N2_P[18]_floating , \N2_P[17]_floating , \N2_P[16]_floating , \N2_P[15]_floating , \N2_P[14]_floating , \N2_P[13]_floating , \N2_P[12]_floating , \N2_P[11]_floating , \N2_P[10]_floating , \N2_P[9]_floating , \N2_P[8]_floating , \N2_P[7]_floating , \N2_P[6]_floating , \N2_P[5]_floating , \N2_P[4]_floating , \N2_P[3]_floating , \N2_P[2]_floating , \N2_P[1]_floating , \N2_P[0]_floating }), + .P ({_N11620, _N11619, _N11618, _N11617, _N11616, _N11615, _N11614, _N11613, _N11612, _N11611, _N11610, _N11609, _N11608, _N11607, _N11606, _N11605, _N11604, _N11603, _N11602, _N11601, _N11600, _N11599, _N11598, _N11597, _N11596, \N2_P[22]_floating , \N2_P[21]_floating , \N2_P[20]_floating , \N2_P[19]_floating , \N2_P[18]_floating , \N2_P[17]_floating , \N2_P[16]_floating , \N2_P[15]_floating , \N2_P[14]_floating , \N2_P[13]_floating , \N2_P[12]_floating , \N2_P[11]_floating , \N2_P[10]_floating , \N2_P[9]_floating , \N2_P[8]_floating , \N2_P[7]_floating , \N2_P[6]_floating , \N2_P[5]_floating , \N2_P[4]_floating , \N2_P[3]_floating , \N2_P[2]_floating , \N2_P[1]_floating , \N2_P[0]_floating }), .CPI (), .CXBI (), .CXI (), .MODEY ({1'b0, 1'b0, 1'b0}), .MODEZ ({1'b0, 1'b0, 1'b0, 1'b0}), .X ({B[11], B[11], B[11], B[11], B[11], B[11], B[11], B[10], B[9], B[8], B[7], B[6], B[5], B[4], B[3], B[2], B[1], B[0]}), - .Y ({\u_rotate_image/N290 [10] , \u_rotate_image/N290 [10] , \u_rotate_image/N290 [10] , \u_rotate_image/N290 [10] , \u_rotate_image/N290 [10] , \u_rotate_image/N290 [10] , \u_rotate_image/N290 [10] , \u_rotate_image/N290 [10] , \u_rotate_image/N290 [9] , \u_rotate_image/N290 [8] , \u_rotate_image/N290 [7] , \u_rotate_image/N290 [6] , \u_rotate_image/N290 [5] , \u_rotate_image/N290 [4] , \u_rotate_image/N290 [3] , \u_rotate_image/N290 [2] , \u_rotate_image/N290 [1] , \u_rotate_image/N290 [0] }), + .Y ({\u_rotate_image/N338 [10] , \u_rotate_image/N338 [10] , \u_rotate_image/N338 [10] , \u_rotate_image/N338 [10] , \u_rotate_image/N338 [10] , \u_rotate_image/N338 [10] , \u_rotate_image/N338 [10] , \u_rotate_image/N338 [10] , \u_rotate_image/N338 [9] , \u_rotate_image/N338 [8] , \u_rotate_image/N338 [7] , \u_rotate_image/N338 [6] , \u_rotate_image/N338 [5] , \u_rotate_image/N338 [4] , \u_rotate_image/N338 [3] , \u_rotate_image/N338 [2] , \u_rotate_image/N338 [1] , \u_rotate_image/N338 [0] }), .Z (), .COUT (), .CEM (1'b1), @@ -280236,11 +279865,9 @@ endmodule module rotate_mult0_1_unq12 ( input [12:0] B, - input [10:0] \u_rotate_image/N301 , + input [10:0] \u_rotate_image/N349 , input [23:0] \u_rotate_image/mult_p0[2] , input CLK, - input _N12915, - input _N12916, input _N12917, input _N12918, input _N12919, @@ -280264,11 +279891,11 @@ module rotate_mult0_1_unq12 input _N12937, input _N12938, input _N12939, - input \u_rotate_image/N302 , + input _N12940, + input _N12941, + input \u_rotate_image/N350 , output [24:0] \u_rotate_image/h_mult_add ); - wire _N12508; - wire _N12509; wire _N12510; wire _N12511; wire _N12512; @@ -280290,6 +279917,8 @@ module rotate_mult0_1_unq12 wire _N12528; wire _N12529; wire _N12530; + wire _N12531; + wire _N12532; wire \N2_CPO[0]_floating ; wire \N2_CPO[1]_floating ; wire \N2_CPO[2]_floating ; @@ -280403,14 +280032,14 @@ module rotate_mult0_1_unq12 .CPO (), .CXBO (), .CXO (), - .P ({_N12530, _N12529, _N12528, _N12527, _N12526, _N12525, _N12524, _N12523, _N12522, _N12521, _N12520, _N12519, _N12518, _N12517, _N12516, _N12515, _N12514, _N12513, _N12512, _N12511, _N12510, _N12509, _N12508, \u_rotate_image/h_mult_add [24] , \u_rotate_image/h_mult_add [23] , \u_rotate_image/h_mult_add [22] , \u_rotate_image/h_mult_add [21] , \u_rotate_image/h_mult_add [20] , \u_rotate_image/h_mult_add [19] , \u_rotate_image/h_mult_add [18] , \u_rotate_image/h_mult_add [17] , \u_rotate_image/h_mult_add [16] , \u_rotate_image/h_mult_add [15] , \u_rotate_image/h_mult_add [14] , \u_rotate_image/h_mult_add [13] , \u_rotate_image/h_mult_add [12] , \u_rotate_image/h_mult_add [11] , \u_rotate_image/h_mult_add [10] , \u_rotate_image/h_mult_add [9] , \u_rotate_image/h_mult_add [8] , \u_rotate_image/h_mult_add [7] , \u_rotate_image/h_mult_add [6] , \u_rotate_image/h_mult_add [5] , \u_rotate_image/h_mult_add [4] , \u_rotate_image/h_mult_add [3] , \u_rotate_image/h_mult_add [2] , \u_rotate_image/h_mult_add [1] , \u_rotate_image/h_mult_add [0] }), - .CPI ({_N12939, _N12938, _N12937, _N12936, _N12935, _N12934, _N12933, _N12932, _N12931, _N12930, _N12929, _N12928, _N12927, _N12926, _N12925, _N12924, _N12923, _N12922, _N12921, _N12920, _N12919, _N12918, _N12917, _N12916, _N12915, \u_rotate_image/mult_p0[2] [22] , \u_rotate_image/mult_p0[2] [21] , \u_rotate_image/mult_p0[2] [20] , \u_rotate_image/mult_p0[2] [19] , \u_rotate_image/mult_p0[2] [18] , \u_rotate_image/mult_p0[2] [17] , \u_rotate_image/mult_p0[2] [16] , \u_rotate_image/mult_p0[2] [15] , \u_rotate_image/mult_p0[2] [14] , \u_rotate_image/mult_p0[2] [13] , \u_rotate_image/mult_p0[2] [12] , \u_rotate_image/mult_p0[2] [11] , \u_rotate_image/mult_p0[2] [10] , \u_rotate_image/mult_p0[2] [9] , \u_rotate_image/mult_p0[2] [8] , \u_rotate_image/mult_p0[2] [7] , \u_rotate_image/mult_p0[2] [6] , \u_rotate_image/mult_p0[2] [5] , \u_rotate_image/mult_p0[2] [4] , \u_rotate_image/mult_p0[2] [3] , \u_rotate_image/mult_p0[2] [2] , \u_rotate_image/mult_p0[2] [1] , \u_rotate_image/mult_p0[2] [0] }), + .P ({_N12532, _N12531, _N12530, _N12529, _N12528, _N12527, _N12526, _N12525, _N12524, _N12523, _N12522, _N12521, _N12520, _N12519, _N12518, _N12517, _N12516, _N12515, _N12514, _N12513, _N12512, _N12511, _N12510, \u_rotate_image/h_mult_add [24] , \u_rotate_image/h_mult_add [23] , \u_rotate_image/h_mult_add [22] , \u_rotate_image/h_mult_add [21] , \u_rotate_image/h_mult_add [20] , \u_rotate_image/h_mult_add [19] , \u_rotate_image/h_mult_add [18] , \u_rotate_image/h_mult_add [17] , \u_rotate_image/h_mult_add [16] , \u_rotate_image/h_mult_add [15] , \u_rotate_image/h_mult_add [14] , \u_rotate_image/h_mult_add [13] , \u_rotate_image/h_mult_add [12] , \u_rotate_image/h_mult_add [11] , \u_rotate_image/h_mult_add [10] , \u_rotate_image/h_mult_add [9] , \u_rotate_image/h_mult_add [8] , \u_rotate_image/h_mult_add [7] , \u_rotate_image/h_mult_add [6] , \u_rotate_image/h_mult_add [5] , \u_rotate_image/h_mult_add [4] , \u_rotate_image/h_mult_add [3] , \u_rotate_image/h_mult_add [2] , \u_rotate_image/h_mult_add [1] , \u_rotate_image/h_mult_add [0] }), + .CPI ({_N12941, _N12940, _N12939, _N12938, _N12937, _N12936, _N12935, _N12934, _N12933, _N12932, _N12931, _N12930, _N12929, _N12928, _N12927, _N12926, _N12925, _N12924, _N12923, _N12922, _N12921, _N12920, _N12919, _N12918, _N12917, \u_rotate_image/mult_p0[2] [22] , \u_rotate_image/mult_p0[2] [21] , \u_rotate_image/mult_p0[2] [20] , \u_rotate_image/mult_p0[2] [19] , \u_rotate_image/mult_p0[2] [18] , \u_rotate_image/mult_p0[2] [17] , \u_rotate_image/mult_p0[2] [16] , \u_rotate_image/mult_p0[2] [15] , \u_rotate_image/mult_p0[2] [14] , \u_rotate_image/mult_p0[2] [13] , \u_rotate_image/mult_p0[2] [12] , \u_rotate_image/mult_p0[2] [11] , \u_rotate_image/mult_p0[2] [10] , \u_rotate_image/mult_p0[2] [9] , \u_rotate_image/mult_p0[2] [8] , \u_rotate_image/mult_p0[2] [7] , \u_rotate_image/mult_p0[2] [6] , \u_rotate_image/mult_p0[2] [5] , \u_rotate_image/mult_p0[2] [4] , \u_rotate_image/mult_p0[2] [3] , \u_rotate_image/mult_p0[2] [2] , \u_rotate_image/mult_p0[2] [1] , \u_rotate_image/mult_p0[2] [0] }), .CXBI (), .CXI (), .MODEY ({1'b0, 1'b0, 1'b0}), .MODEZ ({1'b1, 1'b1, 1'b1, 1'b0}), .X ({B[11], B[11], B[11], B[11], B[11], B[11], B[11], B[10], B[9], B[8], B[7], B[6], B[5], B[4], B[3], B[2], B[1], B[0]}), - .Y ({\u_rotate_image/N301 [10] , \u_rotate_image/N301 [10] , \u_rotate_image/N301 [10] , \u_rotate_image/N301 [10] , \u_rotate_image/N301 [10] , \u_rotate_image/N301 [10] , \u_rotate_image/N301 [10] , \u_rotate_image/N301 [10] , \u_rotate_image/N301 [9] , \u_rotate_image/N301 [8] , \u_rotate_image/N301 [7] , \u_rotate_image/N301 [6] , \u_rotate_image/N301 [5] , \u_rotate_image/N301 [4] , \u_rotate_image/N301 [3] , \u_rotate_image/N301 [2] , \u_rotate_image/N301 [1] , \u_rotate_image/N301 [0] }), + .Y ({\u_rotate_image/N349 [10] , \u_rotate_image/N349 [10] , \u_rotate_image/N349 [10] , \u_rotate_image/N349 [10] , \u_rotate_image/N349 [10] , \u_rotate_image/N349 [10] , \u_rotate_image/N349 [10] , \u_rotate_image/N349 [10] , \u_rotate_image/N349 [9] , \u_rotate_image/N349 [8] , \u_rotate_image/N349 [7] , \u_rotate_image/N349 [6] , \u_rotate_image/N349 [5] , \u_rotate_image/N349 [4] , \u_rotate_image/N349 [3] , \u_rotate_image/N349 [2] , \u_rotate_image/N349 [1] , \u_rotate_image/N349 [0] }), .Z (), .COUT (), .CEM (1'b1), @@ -280420,7 +280049,7 @@ module rotate_mult0_1_unq12 .CEP (1'b1), .CEPRE (), .CEX (), - .CEY (\u_rotate_image/N302 ), + .CEY (\u_rotate_image/N350 ), .CEZ (), .CIN (), .CLK (CLK), @@ -280447,15 +280076,13 @@ module rotate_mult0 input CLK, output [19:0] P ); - wire _N11327; - wire _N11328; wire _N11329; wire _N11330; wire _N11331; wire _N11332; wire _N11333; - wire _N11346; - wire _N11347; + wire _N11334; + wire _N11335; wire _N11348; wire _N11349; wire _N11350; @@ -280483,6 +280110,8 @@ module rotate_mult0 wire _N11372; wire _N11373; wire _N11374; + wire _N11375; + wire _N11376; wire \N2_CPO[0]_floating ; wire \N2_CPO[1]_floating ; wire \N2_CPO[2]_floating ; @@ -280596,7 +280225,7 @@ module rotate_mult0 .CPO (), .CXBO (), .CXO (), - .P ({_N11374, _N11373, _N11372, _N11371, _N11370, _N11369, _N11368, _N11367, _N11366, _N11365, _N11364, _N11363, _N11362, _N11361, _N11360, _N11359, _N11358, _N11357, _N11356, _N11355, _N11354, _N11353, _N11352, _N11351, _N11350, _N11349, _N11348, _N11347, _N11346, P[18], P[17], P[16], P[15], P[14], P[13], P[12], P[11], P[10], P[9], P[8], P[7], _N11333, _N11332, _N11331, _N11330, _N11329, _N11328, _N11327}), + .P ({_N11376, _N11375, _N11374, _N11373, _N11372, _N11371, _N11370, _N11369, _N11368, _N11367, _N11366, _N11365, _N11364, _N11363, _N11362, _N11361, _N11360, _N11359, _N11358, _N11357, _N11356, _N11355, _N11354, _N11353, _N11352, _N11351, _N11350, _N11349, _N11348, P[18], P[17], P[16], P[15], P[14], P[13], P[12], P[11], P[10], P[9], P[8], P[7], _N11335, _N11334, _N11333, _N11332, _N11331, _N11330, _N11329}), .CPI (), .CXBI (), .CXI (), @@ -280640,15 +280269,13 @@ module rotate_mult0_unq4 input CLK, output [19:0] P ); - wire _N11375; - wire _N11376; wire _N11377; wire _N11378; wire _N11379; wire _N11380; wire _N11381; - wire _N11394; - wire _N11395; + wire _N11382; + wire _N11383; wire _N11396; wire _N11397; wire _N11398; @@ -280676,6 +280303,8 @@ module rotate_mult0_unq4 wire _N11420; wire _N11421; wire _N11422; + wire _N11423; + wire _N11424; wire \N2_CPO[0]_floating ; wire \N2_CPO[1]_floating ; wire \N2_CPO[2]_floating ; @@ -280789,7 +280418,7 @@ module rotate_mult0_unq4 .CPO (), .CXBO (), .CXO (), - .P ({_N11422, _N11421, _N11420, _N11419, _N11418, _N11417, _N11416, _N11415, _N11414, _N11413, _N11412, _N11411, _N11410, _N11409, _N11408, _N11407, _N11406, _N11405, _N11404, _N11403, _N11402, _N11401, _N11400, _N11399, _N11398, _N11397, _N11396, _N11395, _N11394, P[18], P[17], P[16], P[15], P[14], P[13], P[12], P[11], P[10], P[9], P[8], P[7], _N11381, _N11380, _N11379, _N11378, _N11377, _N11376, _N11375}), + .P ({_N11424, _N11423, _N11422, _N11421, _N11420, _N11419, _N11418, _N11417, _N11416, _N11415, _N11414, _N11413, _N11412, _N11411, _N11410, _N11409, _N11408, _N11407, _N11406, _N11405, _N11404, _N11403, _N11402, _N11401, _N11400, _N11399, _N11398, _N11397, _N11396, P[18], P[17], P[16], P[15], P[14], P[13], P[12], P[11], P[10], P[9], P[8], P[7], _N11383, _N11382, _N11381, _N11380, _N11379, _N11378, _N11377}), .CPI (), .CXBI (), .CXI (), @@ -280966,28 +280595,28 @@ module ipml_fifo_ctrl_v1_3_1_unq16 wire [12:0] \N24.co ; wire [11:0] N138; wire [12:0] \N138_5.co ; - wire _N16623; - wire _N16624; - wire _N16625; - wire _N16626; - wire _N16627; - wire _N16628; - wire _N16629; - wire _N16630; - wire _N16631; - wire _N16632; - wire _N16633; - wire _N16636; - wire _N16637; - wire _N16638; - wire _N16639; - wire _N16640; - wire _N16641; - wire _N16642; - wire _N16643; - wire _N16644; - wire _N16645; - wire _N16646; + wire _N16562; + wire _N16563; + wire _N16564; + wire _N16565; + wire _N16566; + wire _N16567; + wire _N16568; + wire _N16569; + wire _N16570; + wire _N16571; + wire _N16572; + wire _N16575; + wire _N16576; + wire _N16577; + wire _N16578; + wire _N16579; + wire _N16580; + wire _N16581; + wire _N16582; + wire _N16583; + wire _N16584; + wire _N16585; wire [11:0] nb0; wire [11:0] rbin; wire [11:0] rrptr; @@ -281007,7 +280636,7 @@ module ipml_fifo_ctrl_v1_3_1_unq16 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_1 ( - .COUT (_N16623), + .COUT (_N16562), .Z (N2[0]), .CIN (), .I0 (w_en), @@ -281027,9 +280656,9 @@ module ipml_fifo_ctrl_v1_3_1_unq16 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_2 ( - .COUT (_N16624), + .COUT (_N16563), .Z (N2[1]), - .CIN (_N16623), + .CIN (_N16562), .I0 (w_en), .I1 (waddr[0]), .I2 (waddr[1]), @@ -281047,9 +280676,9 @@ module ipml_fifo_ctrl_v1_3_1_unq16 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_3 ( - .COUT (_N16625), + .COUT (_N16564), .Z (N2[2]), - .CIN (_N16624), + .CIN (_N16563), .I0 (), .I1 (waddr[2]), .I2 (), @@ -281067,9 +280696,9 @@ module ipml_fifo_ctrl_v1_3_1_unq16 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_4 ( - .COUT (_N16626), + .COUT (_N16565), .Z (N2[3]), - .CIN (_N16625), + .CIN (_N16564), .I0 (), .I1 (waddr[3]), .I2 (), @@ -281087,9 +280716,9 @@ module ipml_fifo_ctrl_v1_3_1_unq16 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_5 ( - .COUT (_N16627), + .COUT (_N16566), .Z (N2[4]), - .CIN (_N16626), + .CIN (_N16565), .I0 (), .I1 (waddr[4]), .I2 (), @@ -281107,9 +280736,9 @@ module ipml_fifo_ctrl_v1_3_1_unq16 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_6 ( - .COUT (_N16628), + .COUT (_N16567), .Z (N2[5]), - .CIN (_N16627), + .CIN (_N16566), .I0 (), .I1 (waddr[5]), .I2 (), @@ -281127,9 +280756,9 @@ module ipml_fifo_ctrl_v1_3_1_unq16 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_7 ( - .COUT (_N16629), + .COUT (_N16568), .Z (N2[6]), - .CIN (_N16628), + .CIN (_N16567), .I0 (), .I1 (waddr[6]), .I2 (), @@ -281147,9 +280776,9 @@ module ipml_fifo_ctrl_v1_3_1_unq16 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_8 ( - .COUT (_N16630), + .COUT (_N16569), .Z (N2[7]), - .CIN (_N16629), + .CIN (_N16568), .I0 (), .I1 (waddr[7]), .I2 (), @@ -281167,9 +280796,9 @@ module ipml_fifo_ctrl_v1_3_1_unq16 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_9 ( - .COUT (_N16631), + .COUT (_N16570), .Z (N2[8]), - .CIN (_N16630), + .CIN (_N16569), .I0 (), .I1 (waddr[8]), .I2 (), @@ -281187,9 +280816,9 @@ module ipml_fifo_ctrl_v1_3_1_unq16 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_10 ( - .COUT (_N16632), + .COUT (_N16571), .Z (N2[9]), - .CIN (_N16631), + .CIN (_N16570), .I0 (), .I1 (waddr[9]), .I2 (), @@ -281207,9 +280836,9 @@ module ipml_fifo_ctrl_v1_3_1_unq16 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_11 ( - .COUT (_N16633), + .COUT (_N16572), .Z (N2[10]), - .CIN (_N16632), + .CIN (_N16571), .I0 (), .I1 (waddr[10]), .I2 (), @@ -281229,7 +280858,7 @@ module ipml_fifo_ctrl_v1_3_1_unq16 N2_12 ( .COUT (), .Z (N2[11]), - .CIN (_N16633), + .CIN (_N16572), .I0 (), .I1 (wbin[11]), .I2 (), @@ -281367,7 +280996,7 @@ module ipml_fifo_ctrl_v1_3_1_unq16 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_1 ( - .COUT (_N16636), + .COUT (_N16575), .Z (N11[0]), .CIN (), .I0 (r_en), @@ -281387,9 +281016,9 @@ module ipml_fifo_ctrl_v1_3_1_unq16 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_2 ( - .COUT (_N16637), + .COUT (_N16576), .Z (N11[1]), - .CIN (_N16636), + .CIN (_N16575), .I0 (r_en), .I1 (raddr[0]), .I2 (raddr[1]), @@ -281407,9 +281036,9 @@ module ipml_fifo_ctrl_v1_3_1_unq16 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_3 ( - .COUT (_N16638), + .COUT (_N16577), .Z (N11[2]), - .CIN (_N16637), + .CIN (_N16576), .I0 (), .I1 (raddr[2]), .I2 (), @@ -281427,9 +281056,9 @@ module ipml_fifo_ctrl_v1_3_1_unq16 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_4 ( - .COUT (_N16639), + .COUT (_N16578), .Z (N11[3]), - .CIN (_N16638), + .CIN (_N16577), .I0 (), .I1 (raddr[3]), .I2 (), @@ -281447,9 +281076,9 @@ module ipml_fifo_ctrl_v1_3_1_unq16 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_5 ( - .COUT (_N16640), + .COUT (_N16579), .Z (N11[4]), - .CIN (_N16639), + .CIN (_N16578), .I0 (), .I1 (raddr[4]), .I2 (), @@ -281467,9 +281096,9 @@ module ipml_fifo_ctrl_v1_3_1_unq16 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_6 ( - .COUT (_N16641), + .COUT (_N16580), .Z (N11[5]), - .CIN (_N16640), + .CIN (_N16579), .I0 (), .I1 (raddr[5]), .I2 (), @@ -281487,9 +281116,9 @@ module ipml_fifo_ctrl_v1_3_1_unq16 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_7 ( - .COUT (_N16642), + .COUT (_N16581), .Z (N11[6]), - .CIN (_N16641), + .CIN (_N16580), .I0 (), .I1 (raddr[6]), .I2 (), @@ -281507,9 +281136,9 @@ module ipml_fifo_ctrl_v1_3_1_unq16 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_8 ( - .COUT (_N16643), + .COUT (_N16582), .Z (N11[7]), - .CIN (_N16642), + .CIN (_N16581), .I0 (), .I1 (raddr[7]), .I2 (), @@ -281527,9 +281156,9 @@ module ipml_fifo_ctrl_v1_3_1_unq16 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_9 ( - .COUT (_N16644), + .COUT (_N16583), .Z (N11[8]), - .CIN (_N16643), + .CIN (_N16582), .I0 (), .I1 (raddr[8]), .I2 (), @@ -281547,9 +281176,9 @@ module ipml_fifo_ctrl_v1_3_1_unq16 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_10 ( - .COUT (_N16645), + .COUT (_N16584), .Z (N11[9]), - .CIN (_N16644), + .CIN (_N16583), .I0 (), .I1 (raddr[9]), .I2 (), @@ -281567,9 +281196,9 @@ module ipml_fifo_ctrl_v1_3_1_unq16 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_11 ( - .COUT (_N16646), + .COUT (_N16585), .Z (N11[10]), - .CIN (_N16645), + .CIN (_N16584), .I0 (), .I1 (raddr[10]), .I2 (), @@ -281589,7 +281218,7 @@ module ipml_fifo_ctrl_v1_3_1_unq16 N11_12 ( .COUT (), .Z (N11[11]), - .CIN (_N16646), + .CIN (_N16585), .I0 (), .I1 (rbin[11]), .I2 (), @@ -282790,7 +282419,7 @@ module ipml_fifo_ctrl_v1_3_2_unq4 input r_en, input rclk, input rrst, - input \u_rotate_image/N339_2 , + input \u_rotate_image/N395_2 , input w_en, output [9:0] raddr, output [9:0] waddr, @@ -282803,26 +282432,26 @@ module ipml_fifo_ctrl_v1_3_2_unq4 wire N22; wire N24; wire [11:0] \N24.co ; - wire _N16649; - wire _N16650; - wire _N16651; - wire _N16652; - wire _N16653; - wire _N16654; - wire _N16655; - wire _N16656; - wire _N16657; - wire _N16658; - wire _N16661; - wire _N16662; - wire _N16663; - wire _N16664; - wire _N16665; - wire _N16666; - wire _N16667; - wire _N16668; - wire _N16669; - wire _N16670; + wire _N16588; + wire _N16589; + wire _N16590; + wire _N16591; + wire _N16592; + wire _N16593; + wire _N16594; + wire _N16595; + wire _N16596; + wire _N16597; + wire _N16600; + wire _N16601; + wire _N16602; + wire _N16603; + wire _N16604; + wire _N16605; + wire _N16606; + wire _N16607; + wire _N16608; + wire _N16609; wire [10:0] rbin; wire [10:0] rrptr; wire [10:0] rwptr; @@ -282841,7 +282470,7 @@ module ipml_fifo_ctrl_v1_3_2_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_1 ( - .COUT (_N16649), + .COUT (_N16588), .Z (N2[0]), .CIN (), .I0 (w_en), @@ -282861,9 +282490,9 @@ module ipml_fifo_ctrl_v1_3_2_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_2 ( - .COUT (_N16650), + .COUT (_N16589), .Z (N2[1]), - .CIN (_N16649), + .CIN (_N16588), .I0 (w_en), .I1 (waddr[0]), .I2 (waddr[1]), @@ -282881,9 +282510,9 @@ module ipml_fifo_ctrl_v1_3_2_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_3 ( - .COUT (_N16651), + .COUT (_N16590), .Z (N2[2]), - .CIN (_N16650), + .CIN (_N16589), .I0 (), .I1 (waddr[2]), .I2 (), @@ -282901,9 +282530,9 @@ module ipml_fifo_ctrl_v1_3_2_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_4 ( - .COUT (_N16652), + .COUT (_N16591), .Z (N2[3]), - .CIN (_N16651), + .CIN (_N16590), .I0 (), .I1 (waddr[3]), .I2 (), @@ -282921,9 +282550,9 @@ module ipml_fifo_ctrl_v1_3_2_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_5 ( - .COUT (_N16653), + .COUT (_N16592), .Z (N2[4]), - .CIN (_N16652), + .CIN (_N16591), .I0 (), .I1 (waddr[4]), .I2 (), @@ -282941,9 +282570,9 @@ module ipml_fifo_ctrl_v1_3_2_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_6 ( - .COUT (_N16654), + .COUT (_N16593), .Z (N2[5]), - .CIN (_N16653), + .CIN (_N16592), .I0 (), .I1 (waddr[5]), .I2 (), @@ -282961,9 +282590,9 @@ module ipml_fifo_ctrl_v1_3_2_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_7 ( - .COUT (_N16655), + .COUT (_N16594), .Z (N2[6]), - .CIN (_N16654), + .CIN (_N16593), .I0 (), .I1 (waddr[6]), .I2 (), @@ -282981,9 +282610,9 @@ module ipml_fifo_ctrl_v1_3_2_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_8 ( - .COUT (_N16656), + .COUT (_N16595), .Z (N2[7]), - .CIN (_N16655), + .CIN (_N16594), .I0 (), .I1 (waddr[7]), .I2 (), @@ -283001,9 +282630,9 @@ module ipml_fifo_ctrl_v1_3_2_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_9 ( - .COUT (_N16657), + .COUT (_N16596), .Z (N2[8]), - .CIN (_N16656), + .CIN (_N16595), .I0 (), .I1 (waddr[8]), .I2 (), @@ -283021,9 +282650,9 @@ module ipml_fifo_ctrl_v1_3_2_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_10 ( - .COUT (_N16658), + .COUT (_N16597), .Z (N2[9]), - .CIN (_N16657), + .CIN (_N16596), .I0 (), .I1 (waddr[9]), .I2 (), @@ -283043,7 +282672,7 @@ module ipml_fifo_ctrl_v1_3_2_unq4 N2_11 ( .COUT (), .Z (N2[10]), - .CIN (_N16658), + .CIN (_N16597), .I0 (), .I1 (wbin[10]), .I2 (), @@ -283171,7 +282800,7 @@ module ipml_fifo_ctrl_v1_3_2_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_1 ( - .COUT (_N16661), + .COUT (_N16600), .Z (N11[0]), .CIN (), .I0 (r_en), @@ -283191,9 +282820,9 @@ module ipml_fifo_ctrl_v1_3_2_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_2 ( - .COUT (_N16662), + .COUT (_N16601), .Z (N11[1]), - .CIN (_N16661), + .CIN (_N16600), .I0 (r_en), .I1 (raddr[0]), .I2 (raddr[1]), @@ -283211,9 +282840,9 @@ module ipml_fifo_ctrl_v1_3_2_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_3 ( - .COUT (_N16663), + .COUT (_N16602), .Z (N11[2]), - .CIN (_N16662), + .CIN (_N16601), .I0 (), .I1 (raddr[2]), .I2 (), @@ -283231,9 +282860,9 @@ module ipml_fifo_ctrl_v1_3_2_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_4 ( - .COUT (_N16664), + .COUT (_N16603), .Z (N11[3]), - .CIN (_N16663), + .CIN (_N16602), .I0 (), .I1 (raddr[3]), .I2 (), @@ -283251,9 +282880,9 @@ module ipml_fifo_ctrl_v1_3_2_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_5 ( - .COUT (_N16665), + .COUT (_N16604), .Z (N11[4]), - .CIN (_N16664), + .CIN (_N16603), .I0 (), .I1 (raddr[4]), .I2 (), @@ -283271,9 +282900,9 @@ module ipml_fifo_ctrl_v1_3_2_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_6 ( - .COUT (_N16666), + .COUT (_N16605), .Z (N11[5]), - .CIN (_N16665), + .CIN (_N16604), .I0 (), .I1 (raddr[5]), .I2 (), @@ -283291,9 +282920,9 @@ module ipml_fifo_ctrl_v1_3_2_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_7 ( - .COUT (_N16667), + .COUT (_N16606), .Z (N11[6]), - .CIN (_N16666), + .CIN (_N16605), .I0 (), .I1 (raddr[6]), .I2 (), @@ -283311,9 +282940,9 @@ module ipml_fifo_ctrl_v1_3_2_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_8 ( - .COUT (_N16668), + .COUT (_N16607), .Z (N11[7]), - .CIN (_N16667), + .CIN (_N16606), .I0 (), .I1 (raddr[7]), .I2 (), @@ -283331,9 +282960,9 @@ module ipml_fifo_ctrl_v1_3_2_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_9 ( - .COUT (_N16669), + .COUT (_N16608), .Z (N11[8]), - .CIN (_N16668), + .CIN (_N16607), .I0 (), .I1 (raddr[8]), .I2 (), @@ -283351,9 +282980,9 @@ module ipml_fifo_ctrl_v1_3_2_unq4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N11_10 ( - .COUT (_N16670), + .COUT (_N16609), .Z (N11[9]), - .CIN (_N16669), + .CIN (_N16608), .I0 (), .I1 (raddr[9]), .I2 (), @@ -283373,7 +283002,7 @@ module ipml_fifo_ctrl_v1_3_2_unq4 N11_11 ( .COUT (), .Z (N11[10]), - .CIN (_N16670), + .CIN (_N16609), .I0 (), .I1 (rbin[10]), .I2 (), @@ -283633,7 +283262,7 @@ module ipml_fifo_ctrl_v1_3_2_unq4 \SYN_CTRL.rbin[0] ( .Q (raddr[0]), .C (rrst), - .CE (\u_rotate_image/N339_2 ), + .CE (\u_rotate_image/N395_2 ), .CLK (rclk), .D (N11[0])); // ../ipcore/image_in_fifo/rtl/ipml_fifo_ctrl_v1_3.v:280 @@ -283644,7 +283273,7 @@ module ipml_fifo_ctrl_v1_3_2_unq4 \SYN_CTRL.rbin[1] ( .Q (raddr[1]), .C (rrst), - .CE (\u_rotate_image/N339_2 ), + .CE (\u_rotate_image/N395_2 ), .CLK (rclk), .D (N11[1])); // ../ipcore/image_in_fifo/rtl/ipml_fifo_ctrl_v1_3.v:280 @@ -283655,7 +283284,7 @@ module ipml_fifo_ctrl_v1_3_2_unq4 \SYN_CTRL.rbin[2] ( .Q (raddr[2]), .C (rrst), - .CE (\u_rotate_image/N339_2 ), + .CE (\u_rotate_image/N395_2 ), .CLK (rclk), .D (N11[2])); // ../ipcore/image_in_fifo/rtl/ipml_fifo_ctrl_v1_3.v:280 @@ -283666,7 +283295,7 @@ module ipml_fifo_ctrl_v1_3_2_unq4 \SYN_CTRL.rbin[3] ( .Q (raddr[3]), .C (rrst), - .CE (\u_rotate_image/N339_2 ), + .CE (\u_rotate_image/N395_2 ), .CLK (rclk), .D (N11[3])); // ../ipcore/image_in_fifo/rtl/ipml_fifo_ctrl_v1_3.v:280 @@ -283677,7 +283306,7 @@ module ipml_fifo_ctrl_v1_3_2_unq4 \SYN_CTRL.rbin[4] ( .Q (raddr[4]), .C (rrst), - .CE (\u_rotate_image/N339_2 ), + .CE (\u_rotate_image/N395_2 ), .CLK (rclk), .D (N11[4])); // ../ipcore/image_in_fifo/rtl/ipml_fifo_ctrl_v1_3.v:280 @@ -283688,7 +283317,7 @@ module ipml_fifo_ctrl_v1_3_2_unq4 \SYN_CTRL.rbin[5] ( .Q (raddr[5]), .C (rrst), - .CE (\u_rotate_image/N339_2 ), + .CE (\u_rotate_image/N395_2 ), .CLK (rclk), .D (N11[5])); // ../ipcore/image_in_fifo/rtl/ipml_fifo_ctrl_v1_3.v:280 @@ -283699,7 +283328,7 @@ module ipml_fifo_ctrl_v1_3_2_unq4 \SYN_CTRL.rbin[6] ( .Q (raddr[6]), .C (rrst), - .CE (\u_rotate_image/N339_2 ), + .CE (\u_rotate_image/N395_2 ), .CLK (rclk), .D (N11[6])); // ../ipcore/image_in_fifo/rtl/ipml_fifo_ctrl_v1_3.v:280 @@ -283710,7 +283339,7 @@ module ipml_fifo_ctrl_v1_3_2_unq4 \SYN_CTRL.rbin[7] ( .Q (raddr[7]), .C (rrst), - .CE (\u_rotate_image/N339_2 ), + .CE (\u_rotate_image/N395_2 ), .CLK (rclk), .D (N11[7])); // ../ipcore/image_in_fifo/rtl/ipml_fifo_ctrl_v1_3.v:280 @@ -283721,7 +283350,7 @@ module ipml_fifo_ctrl_v1_3_2_unq4 \SYN_CTRL.rbin[8] ( .Q (raddr[8]), .C (rrst), - .CE (\u_rotate_image/N339_2 ), + .CE (\u_rotate_image/N395_2 ), .CLK (rclk), .D (N11[8])); // ../ipcore/image_in_fifo/rtl/ipml_fifo_ctrl_v1_3.v:280 @@ -283732,7 +283361,7 @@ module ipml_fifo_ctrl_v1_3_2_unq4 \SYN_CTRL.rbin[9] ( .Q (raddr[9]), .C (rrst), - .CE (\u_rotate_image/N339_2 ), + .CE (\u_rotate_image/N395_2 ), .CLK (rclk), .D (N11[9])); // ../ipcore/image_in_fifo/rtl/ipml_fifo_ctrl_v1_3.v:280 @@ -283743,7 +283372,7 @@ module ipml_fifo_ctrl_v1_3_2_unq4 \SYN_CTRL.rbin[10] ( .Q (rbin[10]), .C (rrst), - .CE (\u_rotate_image/N339_2 ), + .CE (\u_rotate_image/N395_2 ), .CLK (rclk), .D (N11[10])); // ../ipcore/image_in_fifo/rtl/ipml_fifo_ctrl_v1_3.v:280 @@ -284027,7 +283656,7 @@ module ipml_fifo_v1_6_store_image_data input rd_clk, input rd_en, input rd_rst, - input \u_rotate_image/N339_2 , + input \u_rotate_image/N395_2 , input wr_en, output [15:0] rd_data, output rd_empty @@ -284042,7 +283671,7 @@ module ipml_fifo_v1_6_store_image_data .r_en (rd_en), .rclk (rd_clk), .rrst (rd_rst), - .\u_rotate_image/N339_2 (\u_rotate_image/N339_2 ), + .\u_rotate_image/N395_2 (\u_rotate_image/N395_2 ), .w_en (wr_en)); // ../ipcore/store_image_data/rtl/ipml_fifo_v1_6_store_image_data.v:119 @@ -284067,7 +283696,7 @@ module store_image_data input clk, input rd_en, input rst, - input \u_rotate_image/N339_2 , + input \u_rotate_image/N395_2 , input wr_en, output [15:0] rd_data, output rd_empty @@ -284080,7 +283709,7 @@ module store_image_data .rd_clk (clk), .rd_en (rd_en), .rd_rst (rst), - .\u_rotate_image/N339_2 (\u_rotate_image/N339_2 ), + .\u_rotate_image/N395_2 (\u_rotate_image/N395_2 ), .wr_en (wr_en)); // ../ipcore/store_image_data/store_image_data.v:152 @@ -284117,14 +283746,14 @@ module rotate_image wire N170; wire N226; wire N230; - wire [10:0] N290; - wire [10:0] N301; - wire N302; - wire N316; - wire [11:0] N321; - wire [11:0] N326; - wire N339_2; - wire [3:0] N340; + wire [10:0] N338; + wire [10:0] N349; + wire N350; + wire N365; + wire [11:0] N375; + wire [11:0] N380; + wire N395_2; + wire [3:0] N396; wire _N7; wire _N13; wire _N16; @@ -284132,14 +283761,12 @@ module rotate_image wire _N20; wire _N25; wire _N28; - wire _N9883; - wire _N9905; - wire _N9923; - wire _N9933; - wire _N9939; - wire _N9967; - wire _N12915; - wire _N12916; + wire _N9918; + wire _N9940; + wire _N9958; + wire _N9968; + wire _N9974; + wire _N10002; wire _N12917; wire _N12918; wire _N12919; @@ -284188,73 +283815,75 @@ module rotate_image wire _N12962; wire _N12963; wire _N12964; - wire _N16224; - wire _N16225; - wire _N16226; - wire _N16227; - wire _N16228; - wire _N16229; - wire _N16230; - wire _N16231; - wire _N16232; - wire _N16233; - wire _N16234; - wire _N16235; - wire _N16236; - wire _N16237; - wire _N16238; - wire _N16239; - wire _N16240; - wire _N16241; - wire _N16242; - wire _N16544; - wire _N16545; - wire _N16546; - wire _N16547; - wire _N16548; - wire _N16549; - wire _N16550; - wire _N16551; - wire _N16552; - wire _N16571; - wire _N16572; - wire _N16573; - wire _N16574; - wire _N16575; - wire _N16576; - wire _N16577; - wire _N16578; - wire _N16579; - wire _N16591; - wire _N16592; - wire _N16593; - wire _N16594; - wire _N16595; - wire _N16596; - wire _N16597; - wire _N16598; - wire _N16599; - wire _N16600; - wire _N16601; - wire _N16602; - wire _N16603; - wire _N16604; - wire _N16605; - wire _N16606; - wire _N16607; - wire _N16608; - wire _N16609; - wire _N104107; - wire _N104578; - wire _N104579; - wire _N104610; - wire _N104611; - wire _N104621; - wire _N104622; - wire _N104623; - wire _N104630; - wire _N104632; - wire _N104639; + wire _N12965; + wire _N12966; + wire _N16174; + wire _N16175; + wire _N16176; + wire _N16177; + wire _N16178; + wire _N16179; + wire _N16180; + wire _N16181; + wire _N16182; + wire _N16183; + wire _N16184; + wire _N16185; + wire _N16186; + wire _N16187; + wire _N16188; + wire _N16189; + wire _N16190; + wire _N16191; + wire _N16192; + wire _N16454; + wire _N16455; + wire _N16456; + wire _N16457; + wire _N16458; + wire _N16459; + wire _N16460; + wire _N16461; + wire _N16462; + wire _N16476; + wire _N16477; + wire _N16478; + wire _N16479; + wire _N16480; + wire _N16481; + wire _N16482; + wire _N16483; + wire _N16484; + wire _N16496; + wire _N16497; + wire _N16498; + wire _N16499; + wire _N16500; + wire _N16501; + wire _N16502; + wire _N16503; + wire _N16504; + wire _N16505; + wire _N16506; + wire _N16507; + wire _N16508; + wire _N16509; + wire _N16510; + wire _N16511; + wire _N16512; + wire _N16513; + wire _N16514; + wire _N104946; + wire _N105413; + wire _N105414; + wire _N105445; + wire _N105446; + wire _N105456; + wire _N105457; + wire _N105458; + wire _N105465; + wire _N105467; + wire _N105474; wire addr_fifo_empty; wire addr_fifo_rd_en; wire addr_fifo_valid; @@ -284338,7 +283967,7 @@ module rotate_image .I4_TO_LUT("FALSE")) \N14_1.fsub_1 ( .COUT (\N14_1.co [1] ), - .Z (N321[1]), + .Z (N375[1]), .CIN (), .I0 (offsetX_ff[0]), .I1 (offsetX_ff[1]), @@ -284348,7 +283977,7 @@ module rotate_image .ID ()); // LUT = I1^I0 ; // CARRY = (1'b0) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:89 + // ../../sources/designs/rotate/rotate_image.v:92 GTP_LUT5CARRY /* \N14_1.fsub_2 */ #( .INIT(32'b00011110000111100000000100000001), @@ -284358,7 +283987,7 @@ module rotate_image .I4_TO_LUT("FALSE")) \N14_1.fsub_2 ( .COUT (\N14_1.co [2] ), - .Z (N321[2]), + .Z (N375[2]), .CIN (\N14_1.co [1] ), .I0 (offsetX_ff[0]), .I1 (offsetX_ff[1]), @@ -284368,7 +283997,7 @@ module rotate_image .ID ()); // LUT = (I1&~I2)|(I0&~I2)|(~I0&~I1&I2) ; // CARRY = (~I0&~I1&~I2) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:89 + // ../../sources/designs/rotate/rotate_image.v:92 GTP_LUT5CARRY /* \N14_1.fsub_3 */ #( .INIT(32'b10011001100110010011001100110011), @@ -284378,7 +284007,7 @@ module rotate_image .I4_TO_LUT("FALSE")) \N14_1.fsub_3 ( .COUT (\N14_1.co [3] ), - .Z (N321[3]), + .Z (N375[3]), .CIN (\N14_1.co [2] ), .I0 (), .I1 (offsetX_ff[3]), @@ -284388,7 +284017,7 @@ module rotate_image .ID ()); // LUT = ~I1^CIN ; // CARRY = (~I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:89 + // ../../sources/designs/rotate/rotate_image.v:92 GTP_LUT5CARRY /* \N14_1.fsub_4 */ #( .INIT(32'b10011001100110010011001100110011), @@ -284398,7 +284027,7 @@ module rotate_image .I4_TO_LUT("FALSE")) \N14_1.fsub_4 ( .COUT (\N14_1.co [4] ), - .Z (N321[4]), + .Z (N375[4]), .CIN (\N14_1.co [3] ), .I0 (), .I1 (offsetX_ff[4]), @@ -284408,7 +284037,7 @@ module rotate_image .ID ()); // LUT = ~I1^CIN ; // CARRY = (~I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:89 + // ../../sources/designs/rotate/rotate_image.v:92 GTP_LUT5CARRY /* \N14_1.fsub_5 */ #( .INIT(32'b10011001100110010011001100110011), @@ -284418,7 +284047,7 @@ module rotate_image .I4_TO_LUT("FALSE")) \N14_1.fsub_5 ( .COUT (\N14_1.co [5] ), - .Z (N321[5]), + .Z (N375[5]), .CIN (\N14_1.co [4] ), .I0 (), .I1 (offsetX_ff[5]), @@ -284428,7 +284057,7 @@ module rotate_image .ID ()); // LUT = ~I1^CIN ; // CARRY = (~I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:89 + // ../../sources/designs/rotate/rotate_image.v:92 GTP_LUT5CARRY /* \N14_1.fsub_6 */ #( .INIT(32'b10011001100110010011001100110011), @@ -284438,7 +284067,7 @@ module rotate_image .I4_TO_LUT("FALSE")) \N14_1.fsub_6 ( .COUT (\N14_1.co [6] ), - .Z (N321[6]), + .Z (N375[6]), .CIN (\N14_1.co [5] ), .I0 (), .I1 (offsetX_ff[6]), @@ -284448,7 +284077,7 @@ module rotate_image .ID ()); // LUT = ~I1^CIN ; // CARRY = (~I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:89 + // ../../sources/designs/rotate/rotate_image.v:92 GTP_LUT5CARRY /* \N14_1.fsub_7 */ #( .INIT(32'b01100110011001101100110011001100), @@ -284458,7 +284087,7 @@ module rotate_image .I4_TO_LUT("FALSE")) \N14_1.fsub_7 ( .COUT (\N14_1.co [7] ), - .Z (N321[7]), + .Z (N375[7]), .CIN (\N14_1.co [6] ), .I0 (), .I1 (offsetX_ff[7]), @@ -284468,7 +284097,7 @@ module rotate_image .ID ()); // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:89 + // ../../sources/designs/rotate/rotate_image.v:92 GTP_LUT5CARRY /* \N14_1.fsub_8 */ #( .INIT(32'b10011001100110010011001100110011), @@ -284478,7 +284107,7 @@ module rotate_image .I4_TO_LUT("FALSE")) \N14_1.fsub_8 ( .COUT (\N14_1.co [8] ), - .Z (N321[8]), + .Z (N375[8]), .CIN (\N14_1.co [7] ), .I0 (), .I1 (offsetX_ff[8]), @@ -284488,7 +284117,7 @@ module rotate_image .ID ()); // LUT = ~I1^CIN ; // CARRY = (~I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:89 + // ../../sources/designs/rotate/rotate_image.v:92 GTP_LUT5CARRY /* \N14_1.fsub_9 */ #( .INIT(32'b01100110011001101100110011001100), @@ -284498,7 +284127,7 @@ module rotate_image .I4_TO_LUT("FALSE")) \N14_1.fsub_9 ( .COUT (\N14_1.co [9] ), - .Z (N321[9]), + .Z (N375[9]), .CIN (\N14_1.co [8] ), .I0 (), .I1 (offsetX_ff[9]), @@ -284508,7 +284137,7 @@ module rotate_image .ID ()); // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:89 + // ../../sources/designs/rotate/rotate_image.v:92 GTP_LUT5CARRY /* \N14_1.fsub_10 */ #( .INIT(32'b10011001100110010011001100110011), @@ -284518,7 +284147,7 @@ module rotate_image .I4_TO_LUT("FALSE")) \N14_1.fsub_10 ( .COUT (\N14_1.co [10] ), - .Z (N321[10]), + .Z (N375[10]), .CIN (\N14_1.co [9] ), .I0 (), .I1 (offsetX_ff[10]), @@ -284528,7 +284157,7 @@ module rotate_image .ID ()); // LUT = ~I1^CIN ; // CARRY = (~I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:89 + // ../../sources/designs/rotate/rotate_image.v:92 GTP_LUT5CARRY /* \N14_1.fsub_11 */ #( .INIT(32'b10011001100110010011001100110011), @@ -284538,7 +284167,7 @@ module rotate_image .I4_TO_LUT("FALSE")) \N14_1.fsub_11 ( .COUT (), - .Z (N321[11]), + .Z (N375[11]), .CIN (\N14_1.co [10] ), .I0 (), .I1 (offsetX_ff[11]), @@ -284548,7 +284177,7 @@ module rotate_image .ID ()); // LUT = ~I1^CIN ; // CARRY = (~I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:89 + // ../../sources/designs/rotate/rotate_image.v:92 GTP_LUT5CARRY /* \N17_1.fsub_1 */ #( .INIT(32'b01100110011001100000000000000000), @@ -284558,7 +284187,7 @@ module rotate_image .I4_TO_LUT("FALSE")) \N17_1.fsub_1 ( .COUT (\N17_1.co [1] ), - .Z (N326[1]), + .Z (N380[1]), .CIN (), .I0 (offsetY_ff[0]), .I1 (offsetY_ff[1]), @@ -284568,7 +284197,7 @@ module rotate_image .ID ()); // LUT = I1^I0 ; // CARRY = (1'b0) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:90 + // ../../sources/designs/rotate/rotate_image.v:93 GTP_LUT5CARRY /* \N17_1.fsub_2 */ #( .INIT(32'b00011110000111100000000100000001), @@ -284578,7 +284207,7 @@ module rotate_image .I4_TO_LUT("FALSE")) \N17_1.fsub_2 ( .COUT (\N17_1.co [2] ), - .Z (N326[2]), + .Z (N380[2]), .CIN (\N17_1.co [1] ), .I0 (offsetY_ff[0]), .I1 (offsetY_ff[1]), @@ -284588,7 +284217,7 @@ module rotate_image .ID ()); // LUT = (I1&~I2)|(I0&~I2)|(~I0&~I1&I2) ; // CARRY = (~I0&~I1&~I2) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:90 + // ../../sources/designs/rotate/rotate_image.v:93 GTP_LUT5CARRY /* \N17_1.fsub_3 */ #( .INIT(32'b01100110011001101100110011001100), @@ -284598,7 +284227,7 @@ module rotate_image .I4_TO_LUT("FALSE")) \N17_1.fsub_3 ( .COUT (\N17_1.co [3] ), - .Z (N326[3]), + .Z (N380[3]), .CIN (\N17_1.co [2] ), .I0 (), .I1 (offsetY_ff[3]), @@ -284608,7 +284237,7 @@ module rotate_image .ID ()); // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:90 + // ../../sources/designs/rotate/rotate_image.v:93 GTP_LUT5CARRY /* \N17_1.fsub_4 */ #( .INIT(32'b10011001100110010011001100110011), @@ -284618,7 +284247,7 @@ module rotate_image .I4_TO_LUT("FALSE")) \N17_1.fsub_4 ( .COUT (\N17_1.co [4] ), - .Z (N326[4]), + .Z (N380[4]), .CIN (\N17_1.co [3] ), .I0 (), .I1 (offsetY_ff[4]), @@ -284628,7 +284257,7 @@ module rotate_image .ID ()); // LUT = ~I1^CIN ; // CARRY = (~I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:90 + // ../../sources/designs/rotate/rotate_image.v:93 GTP_LUT5CARRY /* \N17_1.fsub_5 */ #( .INIT(32'b01100110011001101100110011001100), @@ -284638,7 +284267,7 @@ module rotate_image .I4_TO_LUT("FALSE")) \N17_1.fsub_5 ( .COUT (\N17_1.co [5] ), - .Z (N326[5]), + .Z (N380[5]), .CIN (\N17_1.co [4] ), .I0 (), .I1 (offsetY_ff[5]), @@ -284648,7 +284277,7 @@ module rotate_image .ID ()); // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:90 + // ../../sources/designs/rotate/rotate_image.v:93 GTP_LUT5CARRY /* \N17_1.fsub_6 */ #( .INIT(32'b01100110011001101100110011001100), @@ -284658,7 +284287,7 @@ module rotate_image .I4_TO_LUT("FALSE")) \N17_1.fsub_6 ( .COUT (\N17_1.co [6] ), - .Z (N326[6]), + .Z (N380[6]), .CIN (\N17_1.co [5] ), .I0 (), .I1 (offsetY_ff[6]), @@ -284668,7 +284297,7 @@ module rotate_image .ID ()); // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:90 + // ../../sources/designs/rotate/rotate_image.v:93 GTP_LUT5CARRY /* \N17_1.fsub_7 */ #( .INIT(32'b10011001100110010011001100110011), @@ -284678,7 +284307,7 @@ module rotate_image .I4_TO_LUT("FALSE")) \N17_1.fsub_7 ( .COUT (\N17_1.co [7] ), - .Z (N326[7]), + .Z (N380[7]), .CIN (\N17_1.co [6] ), .I0 (), .I1 (offsetY_ff[7]), @@ -284688,7 +284317,7 @@ module rotate_image .ID ()); // LUT = ~I1^CIN ; // CARRY = (~I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:90 + // ../../sources/designs/rotate/rotate_image.v:93 GTP_LUT5CARRY /* \N17_1.fsub_8 */ #( .INIT(32'b01100110011001101100110011001100), @@ -284698,7 +284327,7 @@ module rotate_image .I4_TO_LUT("FALSE")) \N17_1.fsub_8 ( .COUT (\N17_1.co [8] ), - .Z (N326[8]), + .Z (N380[8]), .CIN (\N17_1.co [7] ), .I0 (), .I1 (offsetY_ff[8]), @@ -284708,7 +284337,7 @@ module rotate_image .ID ()); // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:90 + // ../../sources/designs/rotate/rotate_image.v:93 GTP_LUT5CARRY /* \N17_1.fsub_9 */ #( .INIT(32'b10011001100110010011001100110011), @@ -284718,7 +284347,7 @@ module rotate_image .I4_TO_LUT("FALSE")) \N17_1.fsub_9 ( .COUT (\N17_1.co [9] ), - .Z (N326[9]), + .Z (N380[9]), .CIN (\N17_1.co [8] ), .I0 (), .I1 (offsetY_ff[9]), @@ -284728,7 +284357,7 @@ module rotate_image .ID ()); // LUT = ~I1^CIN ; // CARRY = (~I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:90 + // ../../sources/designs/rotate/rotate_image.v:93 GTP_LUT5CARRY /* \N17_1.fsub_10 */ #( .INIT(32'b10011001100110010011001100110011), @@ -284738,7 +284367,7 @@ module rotate_image .I4_TO_LUT("FALSE")) \N17_1.fsub_10 ( .COUT (\N17_1.co [10] ), - .Z (N326[10]), + .Z (N380[10]), .CIN (\N17_1.co [9] ), .I0 (), .I1 (offsetY_ff[10]), @@ -284748,7 +284377,7 @@ module rotate_image .ID ()); // LUT = ~I1^CIN ; // CARRY = (~I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:90 + // ../../sources/designs/rotate/rotate_image.v:93 GTP_LUT5CARRY /* \N17_1.fsub_11 */ #( .INIT(32'b10011001100110010011001100110011), @@ -284758,7 +284387,7 @@ module rotate_image .I4_TO_LUT("FALSE")) \N17_1.fsub_11 ( .COUT (), - .Z (N326[11]), + .Z (N380[11]), .CIN (\N17_1.co [10] ), .I0 (), .I1 (offsetY_ff[11]), @@ -284768,12 +284397,12 @@ module rotate_image .ID ()); // LUT = ~I1^CIN ; // CARRY = (~I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:90 + // ../../sources/designs/rotate/rotate_image.v:93 GTP_LUT4 /* N44_mux7_7 */ #( .INIT(16'b0111111111111111)) N44_mux7_7 ( - .Z (_N104639), + .Z (_N105474), .I0 (wr_count[4]), .I1 (wr_count[5]), .I2 (wr_count[6]), @@ -284783,19 +284412,19 @@ module rotate_image GTP_LUT5 /* N44_mux7_8 */ #( .INIT(32'b11111111111111110111111111111111)) N44_mux7_8 ( - .Z (_N9883), + .Z (_N9918), .I0 (wr_count[0]), .I1 (wr_count[1]), .I2 (wr_count[2]), .I3 (wr_count[3]), - .I4 (_N104639)); + .I4 (_N105474)); // LUT = (~I3)|(~I2)|(~I1)|(~I0)|(I4) ; GTP_LUT5 /* N44_mux11_3 */ #( .INIT(32'b00000000000000000000000000101111)) N44_mux11_3 ( - .Z (N340[2]), - .I0 (_N9883), + .Z (N396[2]), + .I0 (_N9918), .I1 (wr_count[8]), .I2 (wr_count[9]), .I3 (wr_count[10]), @@ -284805,7 +284434,7 @@ module rotate_image GTP_LUT4 /* N52_mux6_6 */ #( .INIT(16'b0111111111111111)) N52_mux6_6 ( - .Z (_N104107), + .Z (_N104946), .I0 (cnt_w[3]), .I1 (cnt_w[4]), .I2 (cnt_w[5]), @@ -284815,18 +284444,18 @@ module rotate_image GTP_LUT4 /* N52_mux6_7 */ #( .INIT(16'b1111111101111111)) N52_mux6_7 ( - .Z (_N9905), + .Z (_N9940), .I0 (cnt_w[0]), .I1 (cnt_w[1]), .I2 (cnt_w[2]), - .I3 (_N104107)); + .I3 (_N104946)); // LUT = (~I2)|(~I1)|(~I0)|(I3) ; GTP_LUT5 /* N52_mux10_3 */ #( .INIT(32'b11111111111111110000001011111111)) N52_mux10_3 ( .Z (N52), - .I0 (_N9905), + .I0 (_N9940), .I1 (cnt_w[7]), .I2 (cnt_w[8]), .I3 (cnt_w[9]), @@ -284836,7 +284465,7 @@ module rotate_image GTP_LUT5 /* N57_mux4_3 */ #( .INIT(32'b00000000000000000000000001111111)) N57_mux4_3 ( - .Z (_N9923), + .Z (_N9958), .I0 (cnt_h[0]), .I1 (cnt_h[1]), .I2 (cnt_h[2]), @@ -284847,7 +284476,7 @@ module rotate_image GTP_LUT2 /* N57_mux6_2 */ #( .INIT(4'b0111)) N57_mux6_2 ( - .Z (_N104630), + .Z (_N105465), .I0 (cnt_h[5]), .I1 (cnt_h[6])); // LUT = (~I1)|(~I0) ; @@ -284855,12 +284484,12 @@ module rotate_image GTP_LUT5 /* N57_mux9 */ #( .INIT(32'b00000000001111110000000000101111)) N57_mux9 ( - .Z (_N9933), - .I0 (_N9923), + .Z (_N9968), + .I0 (_N9958), .I1 (cnt_h[7]), .I2 (cnt_h[8]), .I3 (cnt_h[9]), - .I4 (_N104630)); + .I4 (_N105465)); // LUT = (~I2&~I3)|(I0&~I1&~I3)|(~I1&~I3&I4) ; GTP_LUT5CARRY /* N80_1_1 */ #( @@ -284870,8 +284499,8 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N80_1_1 ( - .COUT (_N16544), - .Z (N290[1]), + .COUT (_N16454), + .Z (N338[1]), .CIN (), .I0 (cnt_w[0]), .I1 (cnt_w[1]), @@ -284881,7 +284510,7 @@ module rotate_image .ID ()); // LUT = (I0&~I1&I2)|(~I0&I1&I2) ; // CARRY = (1'b0) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:173 + // ../../sources/designs/rotate/rotate_image.v:176 GTP_LUT5CARRY /* N80_1_2 */ #( .INIT(32'b01110000100000001000100000000000), @@ -284890,9 +284519,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N80_1_2 ( - .COUT (_N16545), - .Z (N290[2]), - .CIN (_N16544), + .COUT (_N16455), + .Z (N338[2]), + .CIN (_N16454), .I0 (cnt_w[0]), .I1 (cnt_w[1]), .I2 (image_w_valid), @@ -284901,7 +284530,7 @@ module rotate_image .ID ()); // LUT = (I0&I1&I2&~I3)|(~I1&I2&I3)|(~I0&I2&I3) ; // CARRY = (I0&I1&I3) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:173 + // ../../sources/designs/rotate/rotate_image.v:176 GTP_LUT5CARRY /* N80_1_3 */ #( .INIT(32'b01100000011000001100110011001100), @@ -284910,9 +284539,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N80_1_3 ( - .COUT (_N16546), - .Z (N290[3]), - .CIN (_N16545), + .COUT (_N16456), + .Z (N338[3]), + .CIN (_N16455), .I0 (), .I1 (cnt_w[3]), .I2 (image_w_valid), @@ -284921,7 +284550,7 @@ module rotate_image .ID ()); // LUT = (CIN&~I1&I2)|(~CIN&I1&I2) ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:173 + // ../../sources/designs/rotate/rotate_image.v:176 GTP_LUT5CARRY /* N80_1_4 */ #( .INIT(32'b01100000011000001100110011001100), @@ -284930,9 +284559,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N80_1_4 ( - .COUT (_N16547), - .Z (N290[4]), - .CIN (_N16546), + .COUT (_N16457), + .Z (N338[4]), + .CIN (_N16456), .I0 (), .I1 (cnt_w[4]), .I2 (image_w_valid), @@ -284941,7 +284570,7 @@ module rotate_image .ID ()); // LUT = (CIN&~I1&I2)|(~CIN&I1&I2) ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:173 + // ../../sources/designs/rotate/rotate_image.v:176 GTP_LUT5CARRY /* N80_1_5 */ #( .INIT(32'b01100000011000001100110011001100), @@ -284950,9 +284579,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N80_1_5 ( - .COUT (_N16548), - .Z (N290[5]), - .CIN (_N16547), + .COUT (_N16458), + .Z (N338[5]), + .CIN (_N16457), .I0 (), .I1 (cnt_w[5]), .I2 (image_w_valid), @@ -284961,7 +284590,7 @@ module rotate_image .ID ()); // LUT = (CIN&~I1&I2)|(~CIN&I1&I2) ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:173 + // ../../sources/designs/rotate/rotate_image.v:176 GTP_LUT5CARRY /* N80_1_6 */ #( .INIT(32'b01100000011000001100110011001100), @@ -284970,9 +284599,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N80_1_6 ( - .COUT (_N16549), - .Z (N290[6]), - .CIN (_N16548), + .COUT (_N16459), + .Z (N338[6]), + .CIN (_N16458), .I0 (), .I1 (cnt_w[6]), .I2 (image_w_valid), @@ -284981,7 +284610,7 @@ module rotate_image .ID ()); // LUT = (CIN&~I1&I2)|(~CIN&I1&I2) ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:173 + // ../../sources/designs/rotate/rotate_image.v:176 GTP_LUT5CARRY /* N80_1_7 */ #( .INIT(32'b01101111011011111100110011001100), @@ -284990,9 +284619,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N80_1_7 ( - .COUT (_N16550), - .Z (N290[7]), - .CIN (_N16549), + .COUT (_N16460), + .Z (N338[7]), + .CIN (_N16459), .I0 (), .I1 (cnt_w[7]), .I2 (image_w_valid), @@ -285001,7 +284630,7 @@ module rotate_image .ID ()); // LUT = (~I2)|(CIN&~I1)|(~CIN&I1) ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:173 + // ../../sources/designs/rotate/rotate_image.v:176 GTP_LUT5CARRY /* N80_1_8 */ #( .INIT(32'b01101111011011111100110011001100), @@ -285010,9 +284639,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N80_1_8 ( - .COUT (_N16551), - .Z (N290[8]), - .CIN (_N16550), + .COUT (_N16461), + .Z (N338[8]), + .CIN (_N16460), .I0 (), .I1 (cnt_w[8]), .I2 (image_w_valid), @@ -285021,7 +284650,7 @@ module rotate_image .ID ()); // LUT = (~I2)|(CIN&~I1)|(~CIN&I1) ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:173 + // ../../sources/designs/rotate/rotate_image.v:176 GTP_LUT5CARRY /* N80_1_9 */ #( .INIT(32'b01100000011000001100110011001100), @@ -285030,9 +284659,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N80_1_9 ( - .COUT (_N16552), - .Z (N290[9]), - .CIN (_N16551), + .COUT (_N16462), + .Z (N338[9]), + .CIN (_N16461), .I0 (), .I1 (cnt_w[9]), .I2 (image_w_valid), @@ -285041,7 +284670,7 @@ module rotate_image .ID ()); // LUT = (CIN&~I1&I2)|(~CIN&I1&I2) ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:173 + // ../../sources/designs/rotate/rotate_image.v:176 GTP_LUT5CARRY /* N80_1_10 */ #( .INIT(32'b01101111011011111100110011001100), @@ -285051,8 +284680,8 @@ module rotate_image .I4_TO_LUT("FALSE")) N80_1_10 ( .COUT (), - .Z (N290[10]), - .CIN (_N16552), + .Z (N338[10]), + .CIN (_N16462), .I0 (), .I1 (cnt_w[10]), .I2 (image_w_valid), @@ -285061,7 +284690,7 @@ module rotate_image .ID ()); // LUT = (~I2)|(CIN&~I1)|(~CIN&I1) ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:173 + // ../../sources/designs/rotate/rotate_image.v:176 GTP_LUT5CARRY /* N86_1_1 */ #( .INIT(32'b00000110000001100000000000000000), @@ -285070,8 +284699,8 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N86_1_1 ( - .COUT (_N16571), - .Z (N301[1]), + .COUT (_N16476), + .Z (N349[1]), .CIN (), .I0 (cnt_h[0]), .I1 (cnt_h[1]), @@ -285081,7 +284710,7 @@ module rotate_image .ID ()); // LUT = (I0&~I1&~I2)|(~I0&I1&~I2) ; // CARRY = (1'b0) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:174 + // ../../sources/designs/rotate/rotate_image.v:177 GTP_LUT5CARRY /* N86_1_2 */ #( .INIT(32'b00000111000010001000100000000000), @@ -285090,9 +284719,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N86_1_2 ( - .COUT (_N16572), - .Z (N301[2]), - .CIN (_N16571), + .COUT (_N16477), + .Z (N349[2]), + .CIN (_N16476), .I0 (cnt_h[0]), .I1 (cnt_h[1]), .I2 (rotate_sta_reg[0]), @@ -285101,7 +284730,7 @@ module rotate_image .ID ()); // LUT = (I0&I1&~I2&~I3)|(~I1&~I2&I3)|(~I0&~I2&I3) ; // CARRY = (I0&I1&I3) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:174 + // ../../sources/designs/rotate/rotate_image.v:177 GTP_LUT5CARRY /* N86_1_3 */ #( .INIT(32'b11110110111101101100110011001100), @@ -285110,9 +284739,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N86_1_3 ( - .COUT (_N16573), - .Z (N301[3]), - .CIN (_N16572), + .COUT (_N16478), + .Z (N349[3]), + .CIN (_N16477), .I0 (), .I1 (cnt_h[3]), .I2 (rotate_sta_reg[0]), @@ -285121,7 +284750,7 @@ module rotate_image .ID ()); // LUT = (I2)|(CIN&~I1)|(~CIN&I1) ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:174 + // ../../sources/designs/rotate/rotate_image.v:177 GTP_LUT5CARRY /* N86_1_4 */ #( .INIT(32'b11110110111101101100110011001100), @@ -285130,9 +284759,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N86_1_4 ( - .COUT (_N16574), - .Z (N301[4]), - .CIN (_N16573), + .COUT (_N16479), + .Z (N349[4]), + .CIN (_N16478), .I0 (), .I1 (cnt_h[4]), .I2 (rotate_sta_reg[0]), @@ -285141,7 +284770,7 @@ module rotate_image .ID ()); // LUT = (I2)|(CIN&~I1)|(~CIN&I1) ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:174 + // ../../sources/designs/rotate/rotate_image.v:177 GTP_LUT5CARRY /* N86_1_5 */ #( .INIT(32'b00000110000001101100110011001100), @@ -285150,9 +284779,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N86_1_5 ( - .COUT (_N16575), - .Z (N301[5]), - .CIN (_N16574), + .COUT (_N16480), + .Z (N349[5]), + .CIN (_N16479), .I0 (), .I1 (cnt_h[5]), .I2 (rotate_sta_reg[0]), @@ -285161,7 +284790,7 @@ module rotate_image .ID ()); // LUT = (CIN&~I1&~I2)|(~CIN&I1&~I2) ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:174 + // ../../sources/designs/rotate/rotate_image.v:177 GTP_LUT5CARRY /* N86_1_6 */ #( .INIT(32'b00000110000001101100110011001100), @@ -285170,9 +284799,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N86_1_6 ( - .COUT (_N16576), - .Z (N301[6]), - .CIN (_N16575), + .COUT (_N16481), + .Z (N349[6]), + .CIN (_N16480), .I0 (), .I1 (cnt_h[6]), .I2 (rotate_sta_reg[0]), @@ -285181,7 +284810,7 @@ module rotate_image .ID ()); // LUT = (CIN&~I1&~I2)|(~CIN&I1&~I2) ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:174 + // ../../sources/designs/rotate/rotate_image.v:177 GTP_LUT5CARRY /* N86_1_7 */ #( .INIT(32'b11110110111101101100110011001100), @@ -285190,9 +284819,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N86_1_7 ( - .COUT (_N16577), - .Z (N301[7]), - .CIN (_N16576), + .COUT (_N16482), + .Z (N349[7]), + .CIN (_N16481), .I0 (), .I1 (cnt_h[7]), .I2 (rotate_sta_reg[0]), @@ -285201,7 +284830,7 @@ module rotate_image .ID ()); // LUT = (I2)|(CIN&~I1)|(~CIN&I1) ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:174 + // ../../sources/designs/rotate/rotate_image.v:177 GTP_LUT5CARRY /* N86_1_8 */ #( .INIT(32'b00000110000001101100110011001100), @@ -285210,9 +284839,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N86_1_8 ( - .COUT (_N16578), - .Z (N301[8]), - .CIN (_N16577), + .COUT (_N16483), + .Z (N349[8]), + .CIN (_N16482), .I0 (), .I1 (cnt_h[8]), .I2 (rotate_sta_reg[0]), @@ -285221,7 +284850,7 @@ module rotate_image .ID ()); // LUT = (CIN&~I1&~I2)|(~CIN&I1&~I2) ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:174 + // ../../sources/designs/rotate/rotate_image.v:177 GTP_LUT5CARRY /* N86_1_9 */ #( .INIT(32'b11110110111101101100110011001100), @@ -285230,9 +284859,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N86_1_9 ( - .COUT (_N16579), - .Z (N301[9]), - .CIN (_N16578), + .COUT (_N16484), + .Z (N349[9]), + .CIN (_N16483), .I0 (), .I1 (cnt_h[9]), .I2 (rotate_sta_reg[0]), @@ -285241,7 +284870,7 @@ module rotate_image .ID ()); // LUT = (I2)|(CIN&~I1)|(~CIN&I1) ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:174 + // ../../sources/designs/rotate/rotate_image.v:177 GTP_LUT5CARRY /* N86_1_10 */ #( .INIT(32'b11110110111101101100110011001100), @@ -285251,8 +284880,8 @@ module rotate_image .I4_TO_LUT("FALSE")) N86_1_10 ( .COUT (), - .Z (N301[10]), - .CIN (_N16579), + .Z (N349[10]), + .CIN (_N16484), .I0 (), .I1 (cnt_h[10]), .I2 (rotate_sta_reg[0]), @@ -285261,7 +284890,7 @@ module rotate_image .ID ()); // LUT = (I2)|(CIN&~I1)|(~CIN&I1) ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:174 + // ../../sources/designs/rotate/rotate_image.v:177 GTP_LUT5CARRY /* N119_1_0 */ #( .INIT(32'b11001100110011000000000000000000), @@ -285270,7 +284899,7 @@ module rotate_image .I4_TO_CARRY("FALSE"), .I4_TO_LUT("FALSE")) N119_1_0 ( - .COUT (_N16224), + .COUT (_N16174), .Z (), .CIN (), .I0 (), @@ -285281,7 +284910,7 @@ module rotate_image .ID ()); // LUT = I1 ; // CARRY = (1'b0) ? CIN : (I1) ; - // ../../sources/designs/rotate/rotate_image.v:269 + // ../../sources/designs/rotate/rotate_image.v:272 GTP_LUT5CARRY /* N119_1_1 */ #( .INIT(32'b10010110100101100011110000111100), @@ -285290,9 +284919,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N119_1_1 ( - .COUT (_N16225), + .COUT (_N16175), .Z (N119[7]), - .CIN (_N16224), + .CIN (_N16174), .I0 (), .I1 (w_mult_add[7]), .I2 (image_w_add_addr[7]), @@ -285301,7 +284930,7 @@ module rotate_image .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:269 + // ../../sources/designs/rotate/rotate_image.v:272 GTP_LUT5CARRY /* N119_1_2 */ #( .INIT(32'b10010110100101100011110000111100), @@ -285310,9 +284939,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N119_1_2 ( - .COUT (_N16226), + .COUT (_N16176), .Z (N119[8]), - .CIN (_N16225), + .CIN (_N16175), .I0 (), .I1 (w_mult_add[8]), .I2 (image_w_add_addr[8]), @@ -285321,7 +284950,7 @@ module rotate_image .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:269 + // ../../sources/designs/rotate/rotate_image.v:272 GTP_LUT5CARRY /* N119_1_3 */ #( .INIT(32'b10010110100101100011110000111100), @@ -285330,9 +284959,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N119_1_3 ( - .COUT (_N16227), + .COUT (_N16177), .Z (N119[9]), - .CIN (_N16226), + .CIN (_N16176), .I0 (), .I1 (w_mult_add[9]), .I2 (image_w_add_addr[9]), @@ -285341,7 +284970,7 @@ module rotate_image .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:269 + // ../../sources/designs/rotate/rotate_image.v:272 GTP_LUT5CARRY /* N119_1_4 */ #( .INIT(32'b10010110100101100011110000111100), @@ -285350,9 +284979,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N119_1_4 ( - .COUT (_N16228), + .COUT (_N16178), .Z (N119[10]), - .CIN (_N16227), + .CIN (_N16177), .I0 (), .I1 (w_mult_add[10]), .I2 (image_w_add_addr[10]), @@ -285361,7 +284990,7 @@ module rotate_image .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:269 + // ../../sources/designs/rotate/rotate_image.v:272 GTP_LUT5CARRY /* N119_1_5 */ #( .INIT(32'b10010110100101100011110000111100), @@ -285370,9 +284999,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N119_1_5 ( - .COUT (_N16229), + .COUT (_N16179), .Z (N119[11]), - .CIN (_N16228), + .CIN (_N16178), .I0 (), .I1 (w_mult_add[11]), .I2 (image_w_add_addr[11]), @@ -285381,7 +285010,7 @@ module rotate_image .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:269 + // ../../sources/designs/rotate/rotate_image.v:272 GTP_LUT5CARRY /* N119_1_6 */ #( .INIT(32'b10010110100101100011110000111100), @@ -285390,9 +285019,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N119_1_6 ( - .COUT (_N16230), + .COUT (_N16180), .Z (N119[12]), - .CIN (_N16229), + .CIN (_N16179), .I0 (), .I1 (w_mult_add[12]), .I2 (image_w_add_addr[12]), @@ -285401,7 +285030,7 @@ module rotate_image .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:269 + // ../../sources/designs/rotate/rotate_image.v:272 GTP_LUT5CARRY /* N119_1_7 */ #( .INIT(32'b10010110100101100011110000111100), @@ -285410,9 +285039,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N119_1_7 ( - .COUT (_N16231), + .COUT (_N16181), .Z (N119[13]), - .CIN (_N16230), + .CIN (_N16180), .I0 (), .I1 (w_mult_add[13]), .I2 (image_w_add_addr[13]), @@ -285421,7 +285050,7 @@ module rotate_image .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:269 + // ../../sources/designs/rotate/rotate_image.v:272 GTP_LUT5CARRY /* N119_1_8 */ #( .INIT(32'b10010110100101100011110000111100), @@ -285430,9 +285059,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N119_1_8 ( - .COUT (_N16232), + .COUT (_N16182), .Z (N119[14]), - .CIN (_N16231), + .CIN (_N16181), .I0 (), .I1 (w_mult_add[14]), .I2 (image_w_add_addr[14]), @@ -285441,7 +285070,7 @@ module rotate_image .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:269 + // ../../sources/designs/rotate/rotate_image.v:272 GTP_LUT5CARRY /* N119_1_9 */ #( .INIT(32'b10010110100101100011110000111100), @@ -285450,9 +285079,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N119_1_9 ( - .COUT (_N16233), + .COUT (_N16183), .Z (N119[15]), - .CIN (_N16232), + .CIN (_N16182), .I0 (), .I1 (w_mult_add[15]), .I2 (image_w_add_addr[15]), @@ -285461,7 +285090,7 @@ module rotate_image .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:269 + // ../../sources/designs/rotate/rotate_image.v:272 GTP_LUT5CARRY /* N119_1_10 */ #( .INIT(32'b10010110100101100011110000111100), @@ -285470,9 +285099,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N119_1_10 ( - .COUT (_N16234), + .COUT (_N16184), .Z (N119[16]), - .CIN (_N16233), + .CIN (_N16183), .I0 (), .I1 (w_mult_add[16]), .I2 (image_w_add_addr[16]), @@ -285481,7 +285110,7 @@ module rotate_image .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:269 + // ../../sources/designs/rotate/rotate_image.v:272 GTP_LUT5CARRY /* N119_1_11 */ #( .INIT(32'b10010110100101100011110000111100), @@ -285490,9 +285119,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N119_1_11 ( - .COUT (_N16235), + .COUT (_N16185), .Z (N119[17]), - .CIN (_N16234), + .CIN (_N16184), .I0 (), .I1 (w_mult_add[17]), .I2 (image_w_add_addr[17]), @@ -285501,7 +285130,7 @@ module rotate_image .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:269 + // ../../sources/designs/rotate/rotate_image.v:272 GTP_LUT5CARRY /* N119_1_12 */ #( .INIT(32'b10010110100101100011110000111100), @@ -285510,9 +285139,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N119_1_12 ( - .COUT (_N16236), + .COUT (_N16186), .Z (N119[18]), - .CIN (_N16235), + .CIN (_N16185), .I0 (), .I1 (w_mult_add[18]), .I2 (image_w_add_addr[18]), @@ -285521,7 +285150,7 @@ module rotate_image .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:269 + // ../../sources/designs/rotate/rotate_image.v:272 GTP_LUT5CARRY /* N119_1_13 */ #( .INIT(32'b10010110100101100011110000111100), @@ -285530,9 +285159,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N119_1_13 ( - .COUT (_N16237), + .COUT (_N16187), .Z (N119[19]), - .CIN (_N16236), + .CIN (_N16186), .I0 (), .I1 (w_mult_add[19]), .I2 (image_w_add_addr[18]), @@ -285541,7 +285170,7 @@ module rotate_image .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:269 + // ../../sources/designs/rotate/rotate_image.v:272 GTP_LUT5CARRY /* N119_1_14 */ #( .INIT(32'b10010110100101100011110000111100), @@ -285550,9 +285179,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N119_1_14 ( - .COUT (_N16238), + .COUT (_N16188), .Z (N119[20]), - .CIN (_N16237), + .CIN (_N16187), .I0 (), .I1 (w_mult_add[20]), .I2 (image_w_add_addr[18]), @@ -285561,7 +285190,7 @@ module rotate_image .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:269 + // ../../sources/designs/rotate/rotate_image.v:272 GTP_LUT5CARRY /* N119_1_15 */ #( .INIT(32'b10010110100101100011110000111100), @@ -285570,9 +285199,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N119_1_15 ( - .COUT (_N16239), + .COUT (_N16189), .Z (N119[21]), - .CIN (_N16238), + .CIN (_N16188), .I0 (), .I1 (w_mult_add[21]), .I2 (image_w_add_addr[18]), @@ -285581,7 +285210,7 @@ module rotate_image .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:269 + // ../../sources/designs/rotate/rotate_image.v:272 GTP_LUT5CARRY /* N119_1_16 */ #( .INIT(32'b10010110100101100011110000111100), @@ -285590,9 +285219,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N119_1_16 ( - .COUT (_N16240), + .COUT (_N16190), .Z (N119[22]), - .CIN (_N16239), + .CIN (_N16189), .I0 (), .I1 (w_mult_add[22]), .I2 (image_w_add_addr[18]), @@ -285601,7 +285230,7 @@ module rotate_image .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:269 + // ../../sources/designs/rotate/rotate_image.v:272 GTP_LUT5CARRY /* N119_1_17 */ #( .INIT(32'b10010110100101100011110000111100), @@ -285610,9 +285239,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N119_1_17 ( - .COUT (_N16241), + .COUT (_N16191), .Z (N119[23]), - .CIN (_N16240), + .CIN (_N16190), .I0 (), .I1 (w_mult_add[23]), .I2 (image_w_add_addr[18]), @@ -285621,7 +285250,7 @@ module rotate_image .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:269 + // ../../sources/designs/rotate/rotate_image.v:272 GTP_LUT5CARRY /* N119_1_18 */ #( .INIT(32'b10010110100101100011110000111100), @@ -285630,9 +285259,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N119_1_18 ( - .COUT (_N16242), + .COUT (_N16192), .Z (N119[24]), - .CIN (_N16241), + .CIN (_N16191), .I0 (), .I1 (w_mult_add[24]), .I2 (image_w_add_addr[18]), @@ -285641,7 +285270,7 @@ module rotate_image .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:269 + // ../../sources/designs/rotate/rotate_image.v:272 GTP_LUT5CARRY /* N119_1_19 */ #( .INIT(32'b10010110100101100011110000111100), @@ -285652,7 +285281,7 @@ module rotate_image N119_1_19 ( .COUT (), .Z (N119[25]), - .CIN (_N16242), + .CIN (_N16192), .I0 (), .I1 (w_mult_add[24]), .I2 (image_w_add_addr[18]), @@ -285661,7 +285290,7 @@ module rotate_image .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:269 + // ../../sources/designs/rotate/rotate_image.v:272 GTP_LUT5CARRY /* N122_1_0 */ #( .INIT(32'b11001100110011000000000000000000), @@ -285670,7 +285299,7 @@ module rotate_image .I4_TO_CARRY("FALSE"), .I4_TO_LUT("FALSE")) N122_1_0 ( - .COUT (_N16591), + .COUT (_N16496), .Z (), .CIN (), .I0 (), @@ -285681,7 +285310,7 @@ module rotate_image .ID ()); // LUT = I1 ; // CARRY = (1'b0) ? CIN : (I1) ; - // ../../sources/designs/rotate/rotate_image.v:270 + // ../../sources/designs/rotate/rotate_image.v:273 GTP_LUT5CARRY /* N122_1_1 */ #( .INIT(32'b10010110100101100011110000111100), @@ -285690,9 +285319,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N122_1_1 ( - .COUT (_N16592), + .COUT (_N16497), .Z (N122[7]), - .CIN (_N16591), + .CIN (_N16496), .I0 (), .I1 (image_h_add_addr[7]), .I2 (h_mult_add[7]), @@ -285701,7 +285330,7 @@ module rotate_image .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:270 + // ../../sources/designs/rotate/rotate_image.v:273 GTP_LUT5CARRY /* N122_1_2 */ #( .INIT(32'b10010110100101100011110000111100), @@ -285710,9 +285339,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N122_1_2 ( - .COUT (_N16593), + .COUT (_N16498), .Z (N122[8]), - .CIN (_N16592), + .CIN (_N16497), .I0 (), .I1 (image_h_add_addr[8]), .I2 (h_mult_add[8]), @@ -285721,7 +285350,7 @@ module rotate_image .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:270 + // ../../sources/designs/rotate/rotate_image.v:273 GTP_LUT5CARRY /* N122_1_3 */ #( .INIT(32'b10010110100101100011110000111100), @@ -285730,9 +285359,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N122_1_3 ( - .COUT (_N16594), + .COUT (_N16499), .Z (N122[9]), - .CIN (_N16593), + .CIN (_N16498), .I0 (), .I1 (image_h_add_addr[9]), .I2 (h_mult_add[9]), @@ -285741,7 +285370,7 @@ module rotate_image .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:270 + // ../../sources/designs/rotate/rotate_image.v:273 GTP_LUT5CARRY /* N122_1_4 */ #( .INIT(32'b10010110100101100011110000111100), @@ -285750,9 +285379,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N122_1_4 ( - .COUT (_N16595), + .COUT (_N16500), .Z (N122[10]), - .CIN (_N16594), + .CIN (_N16499), .I0 (), .I1 (image_h_add_addr[10]), .I2 (h_mult_add[10]), @@ -285761,7 +285390,7 @@ module rotate_image .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:270 + // ../../sources/designs/rotate/rotate_image.v:273 GTP_LUT5CARRY /* N122_1_5 */ #( .INIT(32'b10010110100101100011110000111100), @@ -285770,9 +285399,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N122_1_5 ( - .COUT (_N16596), + .COUT (_N16501), .Z (N122[11]), - .CIN (_N16595), + .CIN (_N16500), .I0 (), .I1 (image_h_add_addr[11]), .I2 (h_mult_add[11]), @@ -285781,7 +285410,7 @@ module rotate_image .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:270 + // ../../sources/designs/rotate/rotate_image.v:273 GTP_LUT5CARRY /* N122_1_6 */ #( .INIT(32'b10010110100101100011110000111100), @@ -285790,9 +285419,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N122_1_6 ( - .COUT (_N16597), + .COUT (_N16502), .Z (N122[12]), - .CIN (_N16596), + .CIN (_N16501), .I0 (), .I1 (image_h_add_addr[12]), .I2 (h_mult_add[12]), @@ -285801,7 +285430,7 @@ module rotate_image .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:270 + // ../../sources/designs/rotate/rotate_image.v:273 GTP_LUT5CARRY /* N122_1_7 */ #( .INIT(32'b10010110100101100011110000111100), @@ -285810,9 +285439,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N122_1_7 ( - .COUT (_N16598), + .COUT (_N16503), .Z (N122[13]), - .CIN (_N16597), + .CIN (_N16502), .I0 (), .I1 (image_h_add_addr[13]), .I2 (h_mult_add[13]), @@ -285821,7 +285450,7 @@ module rotate_image .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:270 + // ../../sources/designs/rotate/rotate_image.v:273 GTP_LUT5CARRY /* N122_1_8 */ #( .INIT(32'b10010110100101100011110000111100), @@ -285830,9 +285459,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N122_1_8 ( - .COUT (_N16599), + .COUT (_N16504), .Z (N122[14]), - .CIN (_N16598), + .CIN (_N16503), .I0 (), .I1 (image_h_add_addr[14]), .I2 (h_mult_add[14]), @@ -285841,7 +285470,7 @@ module rotate_image .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:270 + // ../../sources/designs/rotate/rotate_image.v:273 GTP_LUT5CARRY /* N122_1_9 */ #( .INIT(32'b10010110100101100011110000111100), @@ -285850,9 +285479,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N122_1_9 ( - .COUT (_N16600), + .COUT (_N16505), .Z (N122[15]), - .CIN (_N16599), + .CIN (_N16504), .I0 (), .I1 (image_h_add_addr[15]), .I2 (h_mult_add[15]), @@ -285861,7 +285490,7 @@ module rotate_image .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:270 + // ../../sources/designs/rotate/rotate_image.v:273 GTP_LUT5CARRY /* N122_1_10 */ #( .INIT(32'b10010110100101100011110000111100), @@ -285870,9 +285499,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N122_1_10 ( - .COUT (_N16601), + .COUT (_N16506), .Z (N122[16]), - .CIN (_N16600), + .CIN (_N16505), .I0 (), .I1 (image_h_add_addr[16]), .I2 (h_mult_add[16]), @@ -285881,7 +285510,7 @@ module rotate_image .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:270 + // ../../sources/designs/rotate/rotate_image.v:273 GTP_LUT5CARRY /* N122_1_11 */ #( .INIT(32'b10010110100101100011110000111100), @@ -285890,9 +285519,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N122_1_11 ( - .COUT (_N16602), + .COUT (_N16507), .Z (N122[17]), - .CIN (_N16601), + .CIN (_N16506), .I0 (), .I1 (image_h_add_addr[17]), .I2 (h_mult_add[17]), @@ -285901,7 +285530,7 @@ module rotate_image .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:270 + // ../../sources/designs/rotate/rotate_image.v:273 GTP_LUT5CARRY /* N122_1_12 */ #( .INIT(32'b10010110100101100011110000111100), @@ -285910,9 +285539,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N122_1_12 ( - .COUT (_N16603), + .COUT (_N16508), .Z (N122[18]), - .CIN (_N16602), + .CIN (_N16507), .I0 (), .I1 (image_h_add_addr[18]), .I2 (h_mult_add[18]), @@ -285921,7 +285550,7 @@ module rotate_image .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:270 + // ../../sources/designs/rotate/rotate_image.v:273 GTP_LUT5CARRY /* N122_1_13 */ #( .INIT(32'b10010110100101100011110000111100), @@ -285930,9 +285559,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N122_1_13 ( - .COUT (_N16604), + .COUT (_N16509), .Z (N122[19]), - .CIN (_N16603), + .CIN (_N16508), .I0 (), .I1 (image_h_add_addr[18]), .I2 (h_mult_add[19]), @@ -285941,7 +285570,7 @@ module rotate_image .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:270 + // ../../sources/designs/rotate/rotate_image.v:273 GTP_LUT5CARRY /* N122_1_14 */ #( .INIT(32'b10010110100101100011110000111100), @@ -285950,9 +285579,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N122_1_14 ( - .COUT (_N16605), + .COUT (_N16510), .Z (N122[20]), - .CIN (_N16604), + .CIN (_N16509), .I0 (), .I1 (image_h_add_addr[18]), .I2 (h_mult_add[20]), @@ -285961,7 +285590,7 @@ module rotate_image .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:270 + // ../../sources/designs/rotate/rotate_image.v:273 GTP_LUT5CARRY /* N122_1_15 */ #( .INIT(32'b10010110100101100011110000111100), @@ -285970,9 +285599,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N122_1_15 ( - .COUT (_N16606), + .COUT (_N16511), .Z (N122[21]), - .CIN (_N16605), + .CIN (_N16510), .I0 (), .I1 (image_h_add_addr[18]), .I2 (h_mult_add[21]), @@ -285981,7 +285610,7 @@ module rotate_image .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:270 + // ../../sources/designs/rotate/rotate_image.v:273 GTP_LUT5CARRY /* N122_1_16 */ #( .INIT(32'b10010110100101100011110000111100), @@ -285990,9 +285619,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N122_1_16 ( - .COUT (_N16607), + .COUT (_N16512), .Z (N122[22]), - .CIN (_N16606), + .CIN (_N16511), .I0 (), .I1 (image_h_add_addr[18]), .I2 (h_mult_add[22]), @@ -286001,7 +285630,7 @@ module rotate_image .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:270 + // ../../sources/designs/rotate/rotate_image.v:273 GTP_LUT5CARRY /* N122_1_17 */ #( .INIT(32'b10010110100101100011110000111100), @@ -286010,9 +285639,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N122_1_17 ( - .COUT (_N16608), + .COUT (_N16513), .Z (N122[23]), - .CIN (_N16607), + .CIN (_N16512), .I0 (), .I1 (image_h_add_addr[18]), .I2 (h_mult_add[23]), @@ -286021,7 +285650,7 @@ module rotate_image .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:270 + // ../../sources/designs/rotate/rotate_image.v:273 GTP_LUT5CARRY /* N122_1_18 */ #( .INIT(32'b10010110100101100011110000111100), @@ -286030,9 +285659,9 @@ module rotate_image .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N122_1_18 ( - .COUT (_N16609), + .COUT (_N16514), .Z (N122[24]), - .CIN (_N16608), + .CIN (_N16513), .I0 (), .I1 (image_h_add_addr[18]), .I2 (h_mult_add[24]), @@ -286041,7 +285670,7 @@ module rotate_image .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:270 + // ../../sources/designs/rotate/rotate_image.v:273 GTP_LUT5CARRY /* N122_1_19 */ #( .INIT(32'b10010110100101100011110000111100), @@ -286052,7 +285681,7 @@ module rotate_image N122_1_19 ( .COUT (), .Z (N122[25]), - .CIN (_N16609), + .CIN (_N16514), .I0 (), .I1 (image_h_add_addr[18]), .I2 (h_mult_add[24]), @@ -286061,7 +285690,7 @@ module rotate_image .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/rotate/rotate_image.v:270 + // ../../sources/designs/rotate/rotate_image.v:273 GTP_LUT3 /* N126_1 */ #( .INIT(8'b00010000)) @@ -286075,7 +285704,7 @@ module rotate_image GTP_LUT2 /* N131_mux1 */ #( .INIT(4'b0001)) N131_mux1 ( - .Z (_N9939), + .Z (_N9974), .I0 (image_w_add0[15]), .I1 (image_w_add0[16])); // LUT = ~I0&~I1 ; @@ -286083,7 +285712,7 @@ module rotate_image GTP_LUT3 /* N131_mux9_5 */ #( .INIT(8'b00000001)) N131_mux9_5 ( - .Z (_N104578), + .Z (_N105413), .I0 (image_w_add0[18]), .I1 (image_w_add0[19]), .I2 (image_w_add0[24])); @@ -286092,7 +285721,7 @@ module rotate_image GTP_LUT4 /* N131_mux9_6 */ #( .INIT(16'b0000000000000001)) N131_mux9_6 ( - .Z (_N104579), + .Z (_N105414), .I0 (image_w_add0[20]), .I1 (image_w_add0[21]), .I2 (image_w_add0[22]), @@ -286103,19 +285732,19 @@ module rotate_image .INIT(32'b11110100111111111111111111111111)) N134_vname ( .Z (N134), - .I0 (_N9939), + .I0 (_N9974), .I1 (image_w_add0[17]), .I2 (image_w_add0[25]), - .I3 (_N104578), - .I4 (_N104579)); + .I3 (_N105413), + .I4 (_N105414)); // defparam N134_vname.orig_name = N134; // LUT = (~I4)|(~I3)|(I2)|(~I0&I1) ; - // ../../sources/designs/rotate/rotate_image.v:278 + // ../../sources/designs/rotate/rotate_image.v:281 GTP_LUT5 /* N144_mux4 */ #( .INIT(32'b00000000000000000001111111111111)) N144_mux4 ( - .Z (_N9967), + .Z (_N10002), .I0 (image_h_add0[11]), .I1 (image_h_add0[12]), .I2 (image_h_add0[13]), @@ -286126,7 +285755,7 @@ module rotate_image GTP_LUT4 /* N144_mux13_6 */ #( .INIT(16'b0000000000000001)) N144_mux13_6 ( - .Z (_N104610), + .Z (_N105445), .I0 (image_h_add0[18]), .I1 (image_h_add0[19]), .I2 (image_h_add0[20]), @@ -286136,7 +285765,7 @@ module rotate_image GTP_LUT4 /* N144_mux13_7 */ #( .INIT(16'b0000000000000001)) N144_mux13_7 ( - .Z (_N104611), + .Z (_N105446), .I0 (image_h_add0[17]), .I1 (image_h_add0[22]), .I2 (image_h_add0[23]), @@ -286147,14 +285776,14 @@ module rotate_image .INIT(32'b11110100111111111111111111111111)) N147_vname ( .Z (N147), - .I0 (_N9967), + .I0 (_N10002), .I1 (image_h_add0[16]), .I2 (image_h_add0[25]), - .I3 (_N104610), - .I4 (_N104611)); + .I3 (_N105445), + .I4 (_N105446)); // defparam N147_vname.orig_name = N147; // LUT = (~I4)|(~I3)|(I2)|(~I0&I1) ; - // ../../sources/designs/rotate/rotate_image.v:281 + // ../../sources/designs/rotate/rotate_image.v:284 GTP_LUT2 /* N154 */ #( .INIT(4'b1110)) @@ -286164,7 +285793,7 @@ module rotate_image .I1 (image_w_blank_valid)); // defparam N154_vname.orig_name = N154; // LUT = (I0)|(I1) ; - // ../../sources/designs/rotate/rotate_image.v:284 + // ../../sources/designs/rotate/rotate_image.v:287 GTP_INV N164_1_vname ( .Z (N164_1), @@ -286172,7 +285801,7 @@ module rotate_image // defparam N164_1_vname.orig_name = N164_1; GTP_INV N169_1 ( - .Z (N339_2), + .Z (N395_2), .I (data_empty)); GTP_LUT4 /* N170_5 */ #( @@ -286204,7 +285833,7 @@ module rotate_image .I1 (data_empty), .I2 (rd_sta_reg[2])); // LUT = I0&~I1&I2 ; - // ../../sources/designs/rotate/rotate_image.v:387 + // ../../sources/designs/rotate/rotate_image.v:390 GTP_LUT2 /* N228 */ #( .INIT(4'b1000)) @@ -286213,7 +285842,7 @@ module rotate_image .I0 (addr_fifo_valid), .I1 (dout[0])); // LUT = I0&I1 ; - // ../../sources/designs/rotate/rotate_image.v:419 + // ../../sources/designs/rotate/rotate_image.v:422 GTP_LUT2 /* N230 */ #( .INIT(4'b1110)) @@ -286223,73 +285852,73 @@ module rotate_image .I1 (fifo_data_valid)); // defparam N230_vname.orig_name = N230; // LUT = (I0)|(I1) ; - // ../../sources/designs/rotate/rotate_image.v:422 + // ../../sources/designs/rotate/rotate_image.v:425 - GTP_LUT2 /* \N290_1[0] */ #( + GTP_LUT2 /* \N338_1[0] */ #( .INIT(4'b0010)) - \N290_1[0] ( - .Z (N290[0]), + \N338_1[0] ( + .Z (N338[0]), .I0 (image_w_valid), .I1 (cnt_w[0])); // LUT = I0&~I1 ; - // ../../sources/designs/rotate/rotate_image.v:163 + // ../../sources/designs/rotate/rotate_image.v:166 - GTP_LUT4 /* N296_7 */ #( + GTP_LUT4 /* N344_7 */ #( .INIT(16'b0000000000000010)) - N296_7 ( - .Z (_N104621), + N344_7 ( + .Z (_N105456), .I0 (cnt_w[1]), .I1 (cnt_w[7]), .I2 (cnt_w[8]), .I3 (cnt_w[10])); // LUT = I0&~I1&~I2&~I3 ; - GTP_LUT4 /* N296_8 */ #( + GTP_LUT4 /* N344_8 */ #( .INIT(16'b1000000000000000)) - N296_8 ( - .Z (_N104622), + N344_8 ( + .Z (_N105457), .I0 (cnt_w[2]), .I1 (cnt_w[3]), .I2 (cnt_w[4]), .I3 (cnt_w[5])); // LUT = I0&I1&I2&I3 ; - GTP_LUT4 /* N296_9 */ #( + GTP_LUT4 /* N344_9 */ #( .INIT(16'b1000000000000000)) - N296_9 ( - .Z (_N104623), + N344_9 ( + .Z (_N105458), .I0 (image_w_valid), .I1 (cnt_w[0]), .I2 (cnt_w[6]), .I3 (cnt_w[9])); // LUT = I0&I1&I2&I3 ; - GTP_LUT2 /* \N301_1[0] */ #( + GTP_LUT2 /* \N349_1[0] */ #( .INIT(4'b0001)) - \N301_1[0] ( - .Z (N301[0]), + \N349_1[0] ( + .Z (N349[0]), .I0 (cnt_h[0]), .I1 (rotate_sta_reg[0])); // LUT = ~I0&~I1 ; - // ../../sources/designs/rotate/rotate_image.v:163 + // ../../sources/designs/rotate/rotate_image.v:166 - GTP_LUT5 /* N302 */ #( + GTP_LUT5 /* N350 */ #( .INIT(32'b01010100010001000100010001000100)) - N302_vname ( - .Z (N302), + N350_vname ( + .Z (N350), .I0 (rst), .I1 (rotate_sta_reg[0]), - .I2 (_N104621), - .I3 (_N104622), - .I4 (_N104623)); - // defparam N302_vname.orig_name = N302; + .I2 (_N105456), + .I3 (_N105457), + .I4 (_N105458)); + // defparam N350_vname.orig_name = N350; // LUT = (~I0&I1)|(~I0&I2&I3&I4) ; // ../../sources/designs/rotate/rotate_image.v:30 - GTP_INV N316_vname ( - .Z (N316), + GTP_INV N365_vname ( + .Z (N365), .I (fifo_data_valid)); - // defparam N316_vname.orig_name = N316; + // defparam N365_vname.orig_name = N365; GTP_DFF /* addr_fifo_valid */ #( .GRS_EN("TRUE"), @@ -286299,7 +285928,7 @@ module rotate_image .CLK (clk), .D (addr_fifo_rd_en)); // defparam addr_fifo_valid_vname.orig_name = addr_fifo_valid; - // ../../sources/designs/rotate/rotate_image.v:332 + // ../../sources/designs/rotate/rotate_image.v:335 GTP_DFF /* \centerX[0] */ #( .GRS_EN("TRUE"), @@ -286308,7 +285937,7 @@ module rotate_image .Q (centerX[0]), .CLK (clk), .D (offsetX_ff[0])); - // ../../sources/designs/rotate/rotate_image.v:88 + // ../../sources/designs/rotate/rotate_image.v:91 GTP_DFF /* \centerX[1] */ #( .GRS_EN("TRUE"), @@ -286316,8 +285945,8 @@ module rotate_image \centerX[1] ( .Q (centerX[1]), .CLK (clk), - .D (N321[1])); - // ../../sources/designs/rotate/rotate_image.v:88 + .D (N375[1])); + // ../../sources/designs/rotate/rotate_image.v:91 GTP_DFF /* \centerX[2] */ #( .GRS_EN("TRUE"), @@ -286325,8 +285954,8 @@ module rotate_image \centerX[2] ( .Q (centerX[2]), .CLK (clk), - .D (N321[2])); - // ../../sources/designs/rotate/rotate_image.v:88 + .D (N375[2])); + // ../../sources/designs/rotate/rotate_image.v:91 GTP_DFF /* \centerX[3] */ #( .GRS_EN("TRUE"), @@ -286334,8 +285963,8 @@ module rotate_image \centerX[3] ( .Q (centerX[3]), .CLK (clk), - .D (N321[3])); - // ../../sources/designs/rotate/rotate_image.v:88 + .D (N375[3])); + // ../../sources/designs/rotate/rotate_image.v:91 GTP_DFF /* \centerX[4] */ #( .GRS_EN("TRUE"), @@ -286343,8 +285972,8 @@ module rotate_image \centerX[4] ( .Q (centerX[4]), .CLK (clk), - .D (N321[4])); - // ../../sources/designs/rotate/rotate_image.v:88 + .D (N375[4])); + // ../../sources/designs/rotate/rotate_image.v:91 GTP_DFF /* \centerX[5] */ #( .GRS_EN("TRUE"), @@ -286352,8 +285981,8 @@ module rotate_image \centerX[5] ( .Q (centerX[5]), .CLK (clk), - .D (N321[5])); - // ../../sources/designs/rotate/rotate_image.v:88 + .D (N375[5])); + // ../../sources/designs/rotate/rotate_image.v:91 GTP_DFF /* \centerX[6] */ #( .GRS_EN("TRUE"), @@ -286361,8 +285990,8 @@ module rotate_image \centerX[6] ( .Q (centerX[6]), .CLK (clk), - .D (N321[6])); - // ../../sources/designs/rotate/rotate_image.v:88 + .D (N375[6])); + // ../../sources/designs/rotate/rotate_image.v:91 GTP_DFF /* \centerX[7] */ #( .GRS_EN("TRUE"), @@ -286370,8 +285999,8 @@ module rotate_image \centerX[7] ( .Q (centerX[7]), .CLK (clk), - .D (N321[7])); - // ../../sources/designs/rotate/rotate_image.v:88 + .D (N375[7])); + // ../../sources/designs/rotate/rotate_image.v:91 GTP_DFF /* \centerX[8] */ #( .GRS_EN("TRUE"), @@ -286379,8 +286008,8 @@ module rotate_image \centerX[8] ( .Q (centerX[8]), .CLK (clk), - .D (N321[8])); - // ../../sources/designs/rotate/rotate_image.v:88 + .D (N375[8])); + // ../../sources/designs/rotate/rotate_image.v:91 GTP_DFF /* \centerX[9] */ #( .GRS_EN("TRUE"), @@ -286388,8 +286017,8 @@ module rotate_image \centerX[9] ( .Q (centerX[9]), .CLK (clk), - .D (N321[9])); - // ../../sources/designs/rotate/rotate_image.v:88 + .D (N375[9])); + // ../../sources/designs/rotate/rotate_image.v:91 GTP_DFF /* \centerX[10] */ #( .GRS_EN("TRUE"), @@ -286397,8 +286026,8 @@ module rotate_image \centerX[10] ( .Q (centerX[10]), .CLK (clk), - .D (N321[10])); - // ../../sources/designs/rotate/rotate_image.v:88 + .D (N375[10])); + // ../../sources/designs/rotate/rotate_image.v:91 GTP_DFF /* \centerX[11] */ #( .GRS_EN("TRUE"), @@ -286406,8 +286035,8 @@ module rotate_image \centerX[11] ( .Q (centerX[11]), .CLK (clk), - .D (N321[11])); - // ../../sources/designs/rotate/rotate_image.v:88 + .D (N375[11])); + // ../../sources/designs/rotate/rotate_image.v:91 GTP_DFF /* \centerY[0] */ #( .GRS_EN("TRUE"), @@ -286416,7 +286045,7 @@ module rotate_image .Q (centerY[0]), .CLK (clk), .D (offsetY_ff[0])); - // ../../sources/designs/rotate/rotate_image.v:88 + // ../../sources/designs/rotate/rotate_image.v:91 GTP_DFF /* \centerY[1] */ #( .GRS_EN("TRUE"), @@ -286424,8 +286053,8 @@ module rotate_image \centerY[1] ( .Q (centerY[1]), .CLK (clk), - .D (N326[1])); - // ../../sources/designs/rotate/rotate_image.v:88 + .D (N380[1])); + // ../../sources/designs/rotate/rotate_image.v:91 GTP_DFF /* \centerY[2] */ #( .GRS_EN("TRUE"), @@ -286433,8 +286062,8 @@ module rotate_image \centerY[2] ( .Q (centerY[2]), .CLK (clk), - .D (N326[2])); - // ../../sources/designs/rotate/rotate_image.v:88 + .D (N380[2])); + // ../../sources/designs/rotate/rotate_image.v:91 GTP_DFF /* \centerY[3] */ #( .GRS_EN("TRUE"), @@ -286442,8 +286071,8 @@ module rotate_image \centerY[3] ( .Q (centerY[3]), .CLK (clk), - .D (N326[3])); - // ../../sources/designs/rotate/rotate_image.v:88 + .D (N380[3])); + // ../../sources/designs/rotate/rotate_image.v:91 GTP_DFF /* \centerY[4] */ #( .GRS_EN("TRUE"), @@ -286451,8 +286080,8 @@ module rotate_image \centerY[4] ( .Q (centerY[4]), .CLK (clk), - .D (N326[4])); - // ../../sources/designs/rotate/rotate_image.v:88 + .D (N380[4])); + // ../../sources/designs/rotate/rotate_image.v:91 GTP_DFF /* \centerY[5] */ #( .GRS_EN("TRUE"), @@ -286460,8 +286089,8 @@ module rotate_image \centerY[5] ( .Q (centerY[5]), .CLK (clk), - .D (N326[5])); - // ../../sources/designs/rotate/rotate_image.v:88 + .D (N380[5])); + // ../../sources/designs/rotate/rotate_image.v:91 GTP_DFF /* \centerY[6] */ #( .GRS_EN("TRUE"), @@ -286469,8 +286098,8 @@ module rotate_image \centerY[6] ( .Q (centerY[6]), .CLK (clk), - .D (N326[6])); - // ../../sources/designs/rotate/rotate_image.v:88 + .D (N380[6])); + // ../../sources/designs/rotate/rotate_image.v:91 GTP_DFF /* \centerY[7] */ #( .GRS_EN("TRUE"), @@ -286478,8 +286107,8 @@ module rotate_image \centerY[7] ( .Q (centerY[7]), .CLK (clk), - .D (N326[7])); - // ../../sources/designs/rotate/rotate_image.v:88 + .D (N380[7])); + // ../../sources/designs/rotate/rotate_image.v:91 GTP_DFF /* \centerY[8] */ #( .GRS_EN("TRUE"), @@ -286487,8 +286116,8 @@ module rotate_image \centerY[8] ( .Q (centerY[8]), .CLK (clk), - .D (N326[8])); - // ../../sources/designs/rotate/rotate_image.v:88 + .D (N380[8])); + // ../../sources/designs/rotate/rotate_image.v:91 GTP_DFF /* \centerY[9] */ #( .GRS_EN("TRUE"), @@ -286496,8 +286125,8 @@ module rotate_image \centerY[9] ( .Q (centerY[9]), .CLK (clk), - .D (N326[9])); - // ../../sources/designs/rotate/rotate_image.v:88 + .D (N380[9])); + // ../../sources/designs/rotate/rotate_image.v:91 GTP_DFF /* \centerY[10] */ #( .GRS_EN("TRUE"), @@ -286505,8 +286134,8 @@ module rotate_image \centerY[10] ( .Q (centerY[10]), .CLK (clk), - .D (N326[10])); - // ../../sources/designs/rotate/rotate_image.v:88 + .D (N380[10])); + // ../../sources/designs/rotate/rotate_image.v:91 GTP_DFF /* \centerY[11] */ #( .GRS_EN("TRUE"), @@ -286514,118 +286143,118 @@ module rotate_image \centerY[11] ( .Q (centerY[11]), .CLK (clk), - .D (N326[11])); - // ../../sources/designs/rotate/rotate_image.v:88 + .D (N380[11])); + // ../../sources/designs/rotate/rotate_image.v:91 GTP_DFF_E /* \cnt_h[0] */ #( .GRS_EN("TRUE"), .INIT(1'b0)) \cnt_h[0] ( .Q (cnt_h[0]), - .CE (N302), + .CE (N350), .CLK (clk), - .D (N301[0])); - // ../../sources/designs/rotate/rotate_image.v:159 + .D (N349[0])); + // ../../sources/designs/rotate/rotate_image.v:162 GTP_DFF_E /* \cnt_h[1] */ #( .GRS_EN("TRUE"), .INIT(1'b0)) \cnt_h[1] ( .Q (cnt_h[1]), - .CE (N302), + .CE (N350), .CLK (clk), - .D (N301[1])); - // ../../sources/designs/rotate/rotate_image.v:159 + .D (N349[1])); + // ../../sources/designs/rotate/rotate_image.v:162 GTP_DFF_E /* \cnt_h[2] */ #( .GRS_EN("TRUE"), .INIT(1'b0)) \cnt_h[2] ( .Q (cnt_h[2]), - .CE (N302), + .CE (N350), .CLK (clk), - .D (N301[2])); - // ../../sources/designs/rotate/rotate_image.v:159 + .D (N349[2])); + // ../../sources/designs/rotate/rotate_image.v:162 GTP_DFF_E /* \cnt_h[3] */ #( .GRS_EN("TRUE"), .INIT(1'b0)) \cnt_h[3] ( .Q (cnt_h[3]), - .CE (N302), + .CE (N350), .CLK (clk), - .D (N301[3])); - // ../../sources/designs/rotate/rotate_image.v:159 + .D (N349[3])); + // ../../sources/designs/rotate/rotate_image.v:162 GTP_DFF_E /* \cnt_h[4] */ #( .GRS_EN("TRUE"), .INIT(1'b0)) \cnt_h[4] ( .Q (cnt_h[4]), - .CE (N302), + .CE (N350), .CLK (clk), - .D (N301[4])); - // ../../sources/designs/rotate/rotate_image.v:159 + .D (N349[4])); + // ../../sources/designs/rotate/rotate_image.v:162 GTP_DFF_E /* \cnt_h[5] */ #( .GRS_EN("TRUE"), .INIT(1'b0)) \cnt_h[5] ( .Q (cnt_h[5]), - .CE (N302), + .CE (N350), .CLK (clk), - .D (N301[5])); - // ../../sources/designs/rotate/rotate_image.v:159 + .D (N349[5])); + // ../../sources/designs/rotate/rotate_image.v:162 GTP_DFF_E /* \cnt_h[6] */ #( .GRS_EN("TRUE"), .INIT(1'b0)) \cnt_h[6] ( .Q (cnt_h[6]), - .CE (N302), + .CE (N350), .CLK (clk), - .D (N301[6])); - // ../../sources/designs/rotate/rotate_image.v:159 + .D (N349[6])); + // ../../sources/designs/rotate/rotate_image.v:162 GTP_DFF_E /* \cnt_h[7] */ #( .GRS_EN("TRUE"), .INIT(1'b0)) \cnt_h[7] ( .Q (cnt_h[7]), - .CE (N302), + .CE (N350), .CLK (clk), - .D (N301[7])); - // ../../sources/designs/rotate/rotate_image.v:159 + .D (N349[7])); + // ../../sources/designs/rotate/rotate_image.v:162 GTP_DFF_E /* \cnt_h[8] */ #( .GRS_EN("TRUE"), .INIT(1'b0)) \cnt_h[8] ( .Q (cnt_h[8]), - .CE (N302), + .CE (N350), .CLK (clk), - .D (N301[8])); - // ../../sources/designs/rotate/rotate_image.v:159 + .D (N349[8])); + // ../../sources/designs/rotate/rotate_image.v:162 GTP_DFF_E /* \cnt_h[9] */ #( .GRS_EN("TRUE"), .INIT(1'b0)) \cnt_h[9] ( .Q (cnt_h[9]), - .CE (N302), + .CE (N350), .CLK (clk), - .D (N301[9])); - // ../../sources/designs/rotate/rotate_image.v:159 + .D (N349[9])); + // ../../sources/designs/rotate/rotate_image.v:162 GTP_DFF_E /* \cnt_h[10] */ #( .GRS_EN("TRUE"), .INIT(1'b0)) \cnt_h[10] ( .Q (cnt_h[10]), - .CE (N302), + .CE (N350), .CLK (clk), - .D (N301[10])); - // ../../sources/designs/rotate/rotate_image.v:159 + .D (N349[10])); + // ../../sources/designs/rotate/rotate_image.v:162 GTP_DFF_E /* \cnt_w[0] */ #( .GRS_EN("TRUE"), @@ -286634,8 +286263,8 @@ module rotate_image .Q (cnt_w[0]), .CE (N139_0), .CLK (clk), - .D (N290[0])); - // ../../sources/designs/rotate/rotate_image.v:159 + .D (N338[0])); + // ../../sources/designs/rotate/rotate_image.v:162 GTP_DFF_E /* \cnt_w[1] */ #( .GRS_EN("TRUE"), @@ -286644,8 +286273,8 @@ module rotate_image .Q (cnt_w[1]), .CE (N139_0), .CLK (clk), - .D (N290[1])); - // ../../sources/designs/rotate/rotate_image.v:159 + .D (N338[1])); + // ../../sources/designs/rotate/rotate_image.v:162 GTP_DFF_E /* \cnt_w[2] */ #( .GRS_EN("TRUE"), @@ -286654,8 +286283,8 @@ module rotate_image .Q (cnt_w[2]), .CE (N139_0), .CLK (clk), - .D (N290[2])); - // ../../sources/designs/rotate/rotate_image.v:159 + .D (N338[2])); + // ../../sources/designs/rotate/rotate_image.v:162 GTP_DFF_E /* \cnt_w[3] */ #( .GRS_EN("TRUE"), @@ -286664,8 +286293,8 @@ module rotate_image .Q (cnt_w[3]), .CE (N139_0), .CLK (clk), - .D (N290[3])); - // ../../sources/designs/rotate/rotate_image.v:159 + .D (N338[3])); + // ../../sources/designs/rotate/rotate_image.v:162 GTP_DFF_E /* \cnt_w[4] */ #( .GRS_EN("TRUE"), @@ -286674,8 +286303,8 @@ module rotate_image .Q (cnt_w[4]), .CE (N139_0), .CLK (clk), - .D (N290[4])); - // ../../sources/designs/rotate/rotate_image.v:159 + .D (N338[4])); + // ../../sources/designs/rotate/rotate_image.v:162 GTP_DFF_E /* \cnt_w[5] */ #( .GRS_EN("TRUE"), @@ -286684,8 +286313,8 @@ module rotate_image .Q (cnt_w[5]), .CE (N139_0), .CLK (clk), - .D (N290[5])); - // ../../sources/designs/rotate/rotate_image.v:159 + .D (N338[5])); + // ../../sources/designs/rotate/rotate_image.v:162 GTP_DFF_E /* \cnt_w[6] */ #( .GRS_EN("TRUE"), @@ -286694,8 +286323,8 @@ module rotate_image .Q (cnt_w[6]), .CE (N139_0), .CLK (clk), - .D (N290[6])); - // ../../sources/designs/rotate/rotate_image.v:159 + .D (N338[6])); + // ../../sources/designs/rotate/rotate_image.v:162 GTP_DFF_E /* \cnt_w[7] */ #( .GRS_EN("TRUE"), @@ -286704,8 +286333,8 @@ module rotate_image .Q (cnt_w[7]), .CE (N139_0), .CLK (clk), - .D (N290[7])); - // ../../sources/designs/rotate/rotate_image.v:159 + .D (N338[7])); + // ../../sources/designs/rotate/rotate_image.v:162 GTP_DFF_E /* \cnt_w[8] */ #( .GRS_EN("TRUE"), @@ -286714,8 +286343,8 @@ module rotate_image .Q (cnt_w[8]), .CE (N139_0), .CLK (clk), - .D (N290[8])); - // ../../sources/designs/rotate/rotate_image.v:159 + .D (N338[8])); + // ../../sources/designs/rotate/rotate_image.v:162 GTP_DFF_E /* \cnt_w[9] */ #( .GRS_EN("TRUE"), @@ -286724,8 +286353,8 @@ module rotate_image .Q (cnt_w[9]), .CE (N139_0), .CLK (clk), - .D (N290[9])); - // ../../sources/designs/rotate/rotate_image.v:159 + .D (N338[9])); + // ../../sources/designs/rotate/rotate_image.v:162 GTP_DFF_E /* \cnt_w[10] */ #( .GRS_EN("TRUE"), @@ -286734,8 +286363,8 @@ module rotate_image .Q (cnt_w[10]), .CE (N139_0), .CLK (clk), - .D (N290[10])); - // ../../sources/designs/rotate/rotate_image.v:159 + .D (N338[10])); + // ../../sources/designs/rotate/rotate_image.v:162 GTP_DFF_R /* \data_out2[0] */ #( .GRS_EN("TRUE"), @@ -286744,8 +286373,8 @@ module rotate_image .Q (data_out[0]), .CLK (clk), .D (image_data[0]), - .R (N316)); - // ../../sources/designs/rotate/rotate_image.v:420 + .R (N365)); + // ../../sources/designs/rotate/rotate_image.v:423 GTP_DFF_R /* \data_out2[1] */ #( .GRS_EN("TRUE"), @@ -286754,8 +286383,8 @@ module rotate_image .Q (data_out[1]), .CLK (clk), .D (image_data[1]), - .R (N316)); - // ../../sources/designs/rotate/rotate_image.v:420 + .R (N365)); + // ../../sources/designs/rotate/rotate_image.v:423 GTP_DFF_R /* \data_out2[2] */ #( .GRS_EN("TRUE"), @@ -286764,8 +286393,8 @@ module rotate_image .Q (data_out[2]), .CLK (clk), .D (image_data[2]), - .R (N316)); - // ../../sources/designs/rotate/rotate_image.v:420 + .R (N365)); + // ../../sources/designs/rotate/rotate_image.v:423 GTP_DFF_R /* \data_out2[3] */ #( .GRS_EN("TRUE"), @@ -286774,8 +286403,8 @@ module rotate_image .Q (data_out[3]), .CLK (clk), .D (image_data[3]), - .R (N316)); - // ../../sources/designs/rotate/rotate_image.v:420 + .R (N365)); + // ../../sources/designs/rotate/rotate_image.v:423 GTP_DFF_R /* \data_out2[4] */ #( .GRS_EN("TRUE"), @@ -286784,8 +286413,8 @@ module rotate_image .Q (data_out[4]), .CLK (clk), .D (image_data[4]), - .R (N316)); - // ../../sources/designs/rotate/rotate_image.v:420 + .R (N365)); + // ../../sources/designs/rotate/rotate_image.v:423 GTP_DFF_R /* \data_out2[5] */ #( .GRS_EN("TRUE"), @@ -286794,8 +286423,8 @@ module rotate_image .Q (data_out[5]), .CLK (clk), .D (image_data[5]), - .R (N316)); - // ../../sources/designs/rotate/rotate_image.v:420 + .R (N365)); + // ../../sources/designs/rotate/rotate_image.v:423 GTP_DFF_R /* \data_out2[6] */ #( .GRS_EN("TRUE"), @@ -286804,8 +286433,8 @@ module rotate_image .Q (data_out[6]), .CLK (clk), .D (image_data[6]), - .R (N316)); - // ../../sources/designs/rotate/rotate_image.v:420 + .R (N365)); + // ../../sources/designs/rotate/rotate_image.v:423 GTP_DFF_R /* \data_out2[7] */ #( .GRS_EN("TRUE"), @@ -286814,8 +286443,8 @@ module rotate_image .Q (data_out[7]), .CLK (clk), .D (image_data[7]), - .R (N316)); - // ../../sources/designs/rotate/rotate_image.v:420 + .R (N365)); + // ../../sources/designs/rotate/rotate_image.v:423 GTP_DFF_R /* \data_out2[8] */ #( .GRS_EN("TRUE"), @@ -286824,8 +286453,8 @@ module rotate_image .Q (data_out[8]), .CLK (clk), .D (image_data[8]), - .R (N316)); - // ../../sources/designs/rotate/rotate_image.v:420 + .R (N365)); + // ../../sources/designs/rotate/rotate_image.v:423 GTP_DFF_R /* \data_out2[9] */ #( .GRS_EN("TRUE"), @@ -286834,8 +286463,8 @@ module rotate_image .Q (data_out[9]), .CLK (clk), .D (image_data[9]), - .R (N316)); - // ../../sources/designs/rotate/rotate_image.v:420 + .R (N365)); + // ../../sources/designs/rotate/rotate_image.v:423 GTP_DFF_R /* \data_out2[10] */ #( .GRS_EN("TRUE"), @@ -286844,8 +286473,8 @@ module rotate_image .Q (data_out[10]), .CLK (clk), .D (image_data[10]), - .R (N316)); - // ../../sources/designs/rotate/rotate_image.v:420 + .R (N365)); + // ../../sources/designs/rotate/rotate_image.v:423 GTP_DFF_R /* \data_out2[11] */ #( .GRS_EN("TRUE"), @@ -286854,8 +286483,8 @@ module rotate_image .Q (data_out[11]), .CLK (clk), .D (image_data[11]), - .R (N316)); - // ../../sources/designs/rotate/rotate_image.v:420 + .R (N365)); + // ../../sources/designs/rotate/rotate_image.v:423 GTP_DFF_R /* \data_out2[12] */ #( .GRS_EN("TRUE"), @@ -286864,8 +286493,8 @@ module rotate_image .Q (data_out[12]), .CLK (clk), .D (image_data[12]), - .R (N316)); - // ../../sources/designs/rotate/rotate_image.v:420 + .R (N365)); + // ../../sources/designs/rotate/rotate_image.v:423 GTP_DFF_R /* \data_out2[13] */ #( .GRS_EN("TRUE"), @@ -286874,8 +286503,8 @@ module rotate_image .Q (data_out[13]), .CLK (clk), .D (image_data[13]), - .R (N316)); - // ../../sources/designs/rotate/rotate_image.v:420 + .R (N365)); + // ../../sources/designs/rotate/rotate_image.v:423 GTP_DFF_R /* \data_out2[14] */ #( .GRS_EN("TRUE"), @@ -286884,8 +286513,8 @@ module rotate_image .Q (data_out[14]), .CLK (clk), .D (image_data[14]), - .R (N316)); - // ../../sources/designs/rotate/rotate_image.v:420 + .R (N365)); + // ../../sources/designs/rotate/rotate_image.v:423 GTP_DFF_R /* \data_out2[15] */ #( .GRS_EN("TRUE"), @@ -286894,8 +286523,8 @@ module rotate_image .Q (data_out[15]), .CLK (clk), .D (image_data[15]), - .R (N316)); - // ../../sources/designs/rotate/rotate_image.v:420 + .R (N365)); + // ../../sources/designs/rotate/rotate_image.v:423 GTP_DFF /* data_out_valid1 */ #( .GRS_EN("TRUE"), @@ -286905,7 +286534,7 @@ module rotate_image .CLK (clk), .D (data_out_valid0)); // defparam data_out_valid1_vname.orig_name = data_out_valid1; - // ../../sources/designs/rotate/rotate_image.v:420 + // ../../sources/designs/rotate/rotate_image.v:423 GTP_DFF /* data_out_valid2 */ #( .GRS_EN("TRUE"), @@ -286914,7 +286543,7 @@ module rotate_image .Q (data_out_valid), .CLK (clk), .D (N230)); - // ../../sources/designs/rotate/rotate_image.v:420 + // ../../sources/designs/rotate/rotate_image.v:423 GTP_DFF /* \ddr_data_in0[0] */ #( .GRS_EN("TRUE"), @@ -286923,7 +286552,7 @@ module rotate_image .Q (ddr_data_in0[0]), .CLK (clk), .D (ddr_data_in[0])); - // ../../sources/designs/rotate/rotate_image.v:339 + // ../../sources/designs/rotate/rotate_image.v:342 GTP_DFF /* \ddr_data_in0[1] */ #( .GRS_EN("TRUE"), @@ -286932,7 +286561,7 @@ module rotate_image .Q (ddr_data_in0[1]), .CLK (clk), .D (ddr_data_in[1])); - // ../../sources/designs/rotate/rotate_image.v:339 + // ../../sources/designs/rotate/rotate_image.v:342 GTP_DFF /* \ddr_data_in0[2] */ #( .GRS_EN("TRUE"), @@ -286941,7 +286570,7 @@ module rotate_image .Q (ddr_data_in0[2]), .CLK (clk), .D (ddr_data_in[2])); - // ../../sources/designs/rotate/rotate_image.v:339 + // ../../sources/designs/rotate/rotate_image.v:342 GTP_DFF /* \ddr_data_in0[3] */ #( .GRS_EN("TRUE"), @@ -286950,7 +286579,7 @@ module rotate_image .Q (ddr_data_in0[3]), .CLK (clk), .D (ddr_data_in[3])); - // ../../sources/designs/rotate/rotate_image.v:339 + // ../../sources/designs/rotate/rotate_image.v:342 GTP_DFF /* \ddr_data_in0[4] */ #( .GRS_EN("TRUE"), @@ -286959,7 +286588,7 @@ module rotate_image .Q (ddr_data_in0[4]), .CLK (clk), .D (ddr_data_in[4])); - // ../../sources/designs/rotate/rotate_image.v:339 + // ../../sources/designs/rotate/rotate_image.v:342 GTP_DFF /* \ddr_data_in0[5] */ #( .GRS_EN("TRUE"), @@ -286968,7 +286597,7 @@ module rotate_image .Q (ddr_data_in0[5]), .CLK (clk), .D (ddr_data_in[5])); - // ../../sources/designs/rotate/rotate_image.v:339 + // ../../sources/designs/rotate/rotate_image.v:342 GTP_DFF /* \ddr_data_in0[6] */ #( .GRS_EN("TRUE"), @@ -286977,7 +286606,7 @@ module rotate_image .Q (ddr_data_in0[6]), .CLK (clk), .D (ddr_data_in[6])); - // ../../sources/designs/rotate/rotate_image.v:339 + // ../../sources/designs/rotate/rotate_image.v:342 GTP_DFF /* \ddr_data_in0[7] */ #( .GRS_EN("TRUE"), @@ -286986,7 +286615,7 @@ module rotate_image .Q (ddr_data_in0[7]), .CLK (clk), .D (ddr_data_in[7])); - // ../../sources/designs/rotate/rotate_image.v:339 + // ../../sources/designs/rotate/rotate_image.v:342 GTP_DFF /* \ddr_data_in0[8] */ #( .GRS_EN("TRUE"), @@ -286995,7 +286624,7 @@ module rotate_image .Q (ddr_data_in0[8]), .CLK (clk), .D (ddr_data_in[8])); - // ../../sources/designs/rotate/rotate_image.v:339 + // ../../sources/designs/rotate/rotate_image.v:342 GTP_DFF /* \ddr_data_in0[9] */ #( .GRS_EN("TRUE"), @@ -287004,7 +286633,7 @@ module rotate_image .Q (ddr_data_in0[9]), .CLK (clk), .D (ddr_data_in[9])); - // ../../sources/designs/rotate/rotate_image.v:339 + // ../../sources/designs/rotate/rotate_image.v:342 GTP_DFF /* \ddr_data_in0[10] */ #( .GRS_EN("TRUE"), @@ -287013,7 +286642,7 @@ module rotate_image .Q (ddr_data_in0[10]), .CLK (clk), .D (ddr_data_in[10])); - // ../../sources/designs/rotate/rotate_image.v:339 + // ../../sources/designs/rotate/rotate_image.v:342 GTP_DFF /* \ddr_data_in0[11] */ #( .GRS_EN("TRUE"), @@ -287022,7 +286651,7 @@ module rotate_image .Q (ddr_data_in0[11]), .CLK (clk), .D (ddr_data_in[11])); - // ../../sources/designs/rotate/rotate_image.v:339 + // ../../sources/designs/rotate/rotate_image.v:342 GTP_DFF /* \ddr_data_in0[12] */ #( .GRS_EN("TRUE"), @@ -287031,7 +286660,7 @@ module rotate_image .Q (ddr_data_in0[12]), .CLK (clk), .D (ddr_data_in[12])); - // ../../sources/designs/rotate/rotate_image.v:339 + // ../../sources/designs/rotate/rotate_image.v:342 GTP_DFF /* \ddr_data_in0[13] */ #( .GRS_EN("TRUE"), @@ -287040,7 +286669,7 @@ module rotate_image .Q (ddr_data_in0[13]), .CLK (clk), .D (ddr_data_in[13])); - // ../../sources/designs/rotate/rotate_image.v:339 + // ../../sources/designs/rotate/rotate_image.v:342 GTP_DFF /* \ddr_data_in0[14] */ #( .GRS_EN("TRUE"), @@ -287049,7 +286678,7 @@ module rotate_image .Q (ddr_data_in0[14]), .CLK (clk), .D (ddr_data_in[14])); - // ../../sources/designs/rotate/rotate_image.v:339 + // ../../sources/designs/rotate/rotate_image.v:342 GTP_DFF /* \ddr_data_in0[15] */ #( .GRS_EN("TRUE"), @@ -287058,7 +286687,7 @@ module rotate_image .Q (ddr_data_in0[15]), .CLK (clk), .D (ddr_data_in[15])); - // ../../sources/designs/rotate/rotate_image.v:339 + // ../../sources/designs/rotate/rotate_image.v:342 GTP_DFF /* ddr_data_in_valid0 */ #( .GRS_EN("TRUE"), @@ -287068,7 +286697,7 @@ module rotate_image .CLK (clk), .D (ddr_data_in_valid)); // defparam ddr_data_in_valid0_vname.orig_name = ddr_data_in_valid0; - // ../../sources/designs/rotate/rotate_image.v:339 + // ../../sources/designs/rotate/rotate_image.v:342 GTP_DFF /* fifo_data_valid */ #( .GRS_EN("TRUE"), @@ -287078,7 +286707,7 @@ module rotate_image .CLK (clk), .D (N170)); // defparam fifo_data_valid_vname.orig_name = fifo_data_valid; - // ../../sources/designs/rotate/rotate_image.v:371 + // ../../sources/designs/rotate/rotate_image.v:374 GTP_DFF /* image_blank_valid */ #( .GRS_EN("TRUE"), @@ -287088,7 +286717,7 @@ module rotate_image .CLK (clk), .D (N154)); // defparam image_blank_valid_vname.orig_name = image_blank_valid; - // ../../sources/designs/rotate/rotate_image.v:277 + // ../../sources/designs/rotate/rotate_image.v:280 GTP_DFF /* \image_h_add0[7] */ #( .GRS_EN("TRUE"), @@ -287097,7 +286726,7 @@ module rotate_image .Q (image_h_add0[7]), .CLK (clk), .D (N122[7])); - // ../../sources/designs/rotate/rotate_image.v:268 + // ../../sources/designs/rotate/rotate_image.v:271 GTP_DFF /* \image_h_add0[8] */ #( .GRS_EN("TRUE"), @@ -287106,7 +286735,7 @@ module rotate_image .Q (image_h_add0[8]), .CLK (clk), .D (N122[8])); - // ../../sources/designs/rotate/rotate_image.v:268 + // ../../sources/designs/rotate/rotate_image.v:271 GTP_DFF /* \image_h_add0[9] */ #( .GRS_EN("TRUE"), @@ -287115,7 +286744,7 @@ module rotate_image .Q (image_h_add0[9]), .CLK (clk), .D (N122[9])); - // ../../sources/designs/rotate/rotate_image.v:268 + // ../../sources/designs/rotate/rotate_image.v:271 GTP_DFF /* \image_h_add0[10] */ #( .GRS_EN("TRUE"), @@ -287124,7 +286753,7 @@ module rotate_image .Q (image_h_add0[10]), .CLK (clk), .D (N122[10])); - // ../../sources/designs/rotate/rotate_image.v:268 + // ../../sources/designs/rotate/rotate_image.v:271 GTP_DFF /* \image_h_add0[11] */ #( .GRS_EN("TRUE"), @@ -287133,7 +286762,7 @@ module rotate_image .Q (image_h_add0[11]), .CLK (clk), .D (N122[11])); - // ../../sources/designs/rotate/rotate_image.v:268 + // ../../sources/designs/rotate/rotate_image.v:271 GTP_DFF /* \image_h_add0[12] */ #( .GRS_EN("TRUE"), @@ -287142,7 +286771,7 @@ module rotate_image .Q (image_h_add0[12]), .CLK (clk), .D (N122[12])); - // ../../sources/designs/rotate/rotate_image.v:268 + // ../../sources/designs/rotate/rotate_image.v:271 GTP_DFF /* \image_h_add0[13] */ #( .GRS_EN("TRUE"), @@ -287151,7 +286780,7 @@ module rotate_image .Q (image_h_add0[13]), .CLK (clk), .D (N122[13])); - // ../../sources/designs/rotate/rotate_image.v:268 + // ../../sources/designs/rotate/rotate_image.v:271 GTP_DFF /* \image_h_add0[14] */ #( .GRS_EN("TRUE"), @@ -287160,7 +286789,7 @@ module rotate_image .Q (image_h_add0[14]), .CLK (clk), .D (N122[14])); - // ../../sources/designs/rotate/rotate_image.v:268 + // ../../sources/designs/rotate/rotate_image.v:271 GTP_DFF /* \image_h_add0[15] */ #( .GRS_EN("TRUE"), @@ -287169,7 +286798,7 @@ module rotate_image .Q (image_h_add0[15]), .CLK (clk), .D (N122[15])); - // ../../sources/designs/rotate/rotate_image.v:268 + // ../../sources/designs/rotate/rotate_image.v:271 GTP_DFF /* \image_h_add0[16] */ #( .GRS_EN("TRUE"), @@ -287178,7 +286807,7 @@ module rotate_image .Q (image_h_add0[16]), .CLK (clk), .D (N122[16])); - // ../../sources/designs/rotate/rotate_image.v:268 + // ../../sources/designs/rotate/rotate_image.v:271 GTP_DFF /* \image_h_add0[17] */ #( .GRS_EN("TRUE"), @@ -287187,7 +286816,7 @@ module rotate_image .Q (image_h_add0[17]), .CLK (clk), .D (N122[17])); - // ../../sources/designs/rotate/rotate_image.v:268 + // ../../sources/designs/rotate/rotate_image.v:271 GTP_DFF /* \image_h_add0[18] */ #( .GRS_EN("TRUE"), @@ -287196,7 +286825,7 @@ module rotate_image .Q (image_h_add0[18]), .CLK (clk), .D (N122[18])); - // ../../sources/designs/rotate/rotate_image.v:268 + // ../../sources/designs/rotate/rotate_image.v:271 GTP_DFF /* \image_h_add0[19] */ #( .GRS_EN("TRUE"), @@ -287205,7 +286834,7 @@ module rotate_image .Q (image_h_add0[19]), .CLK (clk), .D (N122[19])); - // ../../sources/designs/rotate/rotate_image.v:268 + // ../../sources/designs/rotate/rotate_image.v:271 GTP_DFF /* \image_h_add0[20] */ #( .GRS_EN("TRUE"), @@ -287214,7 +286843,7 @@ module rotate_image .Q (image_h_add0[20]), .CLK (clk), .D (N122[20])); - // ../../sources/designs/rotate/rotate_image.v:268 + // ../../sources/designs/rotate/rotate_image.v:271 GTP_DFF /* \image_h_add0[21] */ #( .GRS_EN("TRUE"), @@ -287223,7 +286852,7 @@ module rotate_image .Q (image_h_add0[21]), .CLK (clk), .D (N122[21])); - // ../../sources/designs/rotate/rotate_image.v:268 + // ../../sources/designs/rotate/rotate_image.v:271 GTP_DFF /* \image_h_add0[22] */ #( .GRS_EN("TRUE"), @@ -287232,7 +286861,7 @@ module rotate_image .Q (image_h_add0[22]), .CLK (clk), .D (N122[22])); - // ../../sources/designs/rotate/rotate_image.v:268 + // ../../sources/designs/rotate/rotate_image.v:271 GTP_DFF /* \image_h_add0[23] */ #( .GRS_EN("TRUE"), @@ -287241,7 +286870,7 @@ module rotate_image .Q (image_h_add0[23]), .CLK (clk), .D (N122[23])); - // ../../sources/designs/rotate/rotate_image.v:268 + // ../../sources/designs/rotate/rotate_image.v:271 GTP_DFF /* \image_h_add0[24] */ #( .GRS_EN("TRUE"), @@ -287250,7 +286879,7 @@ module rotate_image .Q (image_h_add0[24]), .CLK (clk), .D (N122[24])); - // ../../sources/designs/rotate/rotate_image.v:268 + // ../../sources/designs/rotate/rotate_image.v:271 GTP_DFF /* \image_h_add0[25] */ #( .GRS_EN("TRUE"), @@ -287259,7 +286888,7 @@ module rotate_image .Q (image_h_add0[25]), .CLK (clk), .D (N122[25])); - // ../../sources/designs/rotate/rotate_image.v:268 + // ../../sources/designs/rotate/rotate_image.v:271 GTP_DFF /* \image_h_add1[0] */ #( .GRS_EN("TRUE"), @@ -287268,7 +286897,7 @@ module rotate_image .Q (image_h_add1[0]), .CLK (clk), .D (image_h_add0[7])); - // ../../sources/designs/rotate/rotate_image.v:288 + // ../../sources/designs/rotate/rotate_image.v:291 GTP_DFF /* \image_h_add1[1] */ #( .GRS_EN("TRUE"), @@ -287277,7 +286906,7 @@ module rotate_image .Q (image_h_add1[1]), .CLK (clk), .D (image_h_add0[8])); - // ../../sources/designs/rotate/rotate_image.v:288 + // ../../sources/designs/rotate/rotate_image.v:291 GTP_DFF /* \image_h_add1[2] */ #( .GRS_EN("TRUE"), @@ -287286,7 +286915,7 @@ module rotate_image .Q (image_h_add1[2]), .CLK (clk), .D (image_h_add0[9])); - // ../../sources/designs/rotate/rotate_image.v:288 + // ../../sources/designs/rotate/rotate_image.v:291 GTP_DFF /* \image_h_add1[3] */ #( .GRS_EN("TRUE"), @@ -287295,7 +286924,7 @@ module rotate_image .Q (image_h_add1[3]), .CLK (clk), .D (image_h_add0[10])); - // ../../sources/designs/rotate/rotate_image.v:288 + // ../../sources/designs/rotate/rotate_image.v:291 GTP_DFF /* \image_h_add1[4] */ #( .GRS_EN("TRUE"), @@ -287304,7 +286933,7 @@ module rotate_image .Q (image_h_add1[4]), .CLK (clk), .D (image_h_add0[11])); - // ../../sources/designs/rotate/rotate_image.v:288 + // ../../sources/designs/rotate/rotate_image.v:291 GTP_DFF /* \image_h_add1[5] */ #( .GRS_EN("TRUE"), @@ -287313,7 +286942,7 @@ module rotate_image .Q (image_h_add1[5]), .CLK (clk), .D (image_h_add0[12])); - // ../../sources/designs/rotate/rotate_image.v:288 + // ../../sources/designs/rotate/rotate_image.v:291 GTP_DFF /* \image_h_add1[6] */ #( .GRS_EN("TRUE"), @@ -287322,7 +286951,7 @@ module rotate_image .Q (image_h_add1[6]), .CLK (clk), .D (image_h_add0[13])); - // ../../sources/designs/rotate/rotate_image.v:288 + // ../../sources/designs/rotate/rotate_image.v:291 GTP_DFF /* \image_h_add1[7] */ #( .GRS_EN("TRUE"), @@ -287331,7 +286960,7 @@ module rotate_image .Q (image_h_add1[7]), .CLK (clk), .D (image_h_add0[14])); - // ../../sources/designs/rotate/rotate_image.v:288 + // ../../sources/designs/rotate/rotate_image.v:291 GTP_DFF /* \image_h_add1[8] */ #( .GRS_EN("TRUE"), @@ -287340,7 +286969,7 @@ module rotate_image .Q (image_h_add1[8]), .CLK (clk), .D (image_h_add0[15])); - // ../../sources/designs/rotate/rotate_image.v:288 + // ../../sources/designs/rotate/rotate_image.v:291 GTP_DFF /* \image_h_add1[9] */ #( .GRS_EN("TRUE"), @@ -287349,7 +286978,7 @@ module rotate_image .Q (image_h_add1[9]), .CLK (clk), .D (image_h_add0[16])); - // ../../sources/designs/rotate/rotate_image.v:288 + // ../../sources/designs/rotate/rotate_image.v:291 GTP_DFF /* \image_h_add1[10] */ #( .GRS_EN("TRUE"), @@ -287358,7 +286987,7 @@ module rotate_image .Q (image_h_add1[10]), .CLK (clk), .D (image_h_add0[17])); - // ../../sources/designs/rotate/rotate_image.v:288 + // ../../sources/designs/rotate/rotate_image.v:291 GTP_DFF /* \image_h_add2[0] */ #( .GRS_EN("TRUE"), @@ -287367,7 +286996,7 @@ module rotate_image .Q (rd_ddr_addr[0]), .CLK (clk), .D (image_h_add1[0])); - // ../../sources/designs/rotate/rotate_image.v:288 + // ../../sources/designs/rotate/rotate_image.v:291 GTP_DFF /* \image_h_add2[1] */ #( .GRS_EN("TRUE"), @@ -287376,7 +287005,7 @@ module rotate_image .Q (rd_ddr_addr[1]), .CLK (clk), .D (image_h_add1[1])); - // ../../sources/designs/rotate/rotate_image.v:288 + // ../../sources/designs/rotate/rotate_image.v:291 GTP_DFF /* \image_h_add2[2] */ #( .GRS_EN("TRUE"), @@ -287385,7 +287014,7 @@ module rotate_image .Q (rd_ddr_addr[2]), .CLK (clk), .D (image_h_add1[2])); - // ../../sources/designs/rotate/rotate_image.v:288 + // ../../sources/designs/rotate/rotate_image.v:291 GTP_DFF /* \image_h_add2[3] */ #( .GRS_EN("TRUE"), @@ -287394,7 +287023,7 @@ module rotate_image .Q (rd_ddr_addr[3]), .CLK (clk), .D (image_h_add1[3])); - // ../../sources/designs/rotate/rotate_image.v:288 + // ../../sources/designs/rotate/rotate_image.v:291 GTP_DFF /* \image_h_add2[4] */ #( .GRS_EN("TRUE"), @@ -287403,7 +287032,7 @@ module rotate_image .Q (rd_ddr_addr[4]), .CLK (clk), .D (image_h_add1[4])); - // ../../sources/designs/rotate/rotate_image.v:288 + // ../../sources/designs/rotate/rotate_image.v:291 GTP_DFF /* \image_h_add2[5] */ #( .GRS_EN("TRUE"), @@ -287412,7 +287041,7 @@ module rotate_image .Q (rd_ddr_addr[5]), .CLK (clk), .D (image_h_add1[5])); - // ../../sources/designs/rotate/rotate_image.v:288 + // ../../sources/designs/rotate/rotate_image.v:291 GTP_DFF /* \image_h_add2[6] */ #( .GRS_EN("TRUE"), @@ -287421,7 +287050,7 @@ module rotate_image .Q (rd_ddr_addr[6]), .CLK (clk), .D (image_h_add1[6])); - // ../../sources/designs/rotate/rotate_image.v:288 + // ../../sources/designs/rotate/rotate_image.v:291 GTP_DFF /* \image_h_add2[7] */ #( .GRS_EN("TRUE"), @@ -287430,7 +287059,7 @@ module rotate_image .Q (rd_ddr_addr[7]), .CLK (clk), .D (image_h_add1[7])); - // ../../sources/designs/rotate/rotate_image.v:288 + // ../../sources/designs/rotate/rotate_image.v:291 GTP_DFF /* \image_h_add2[8] */ #( .GRS_EN("TRUE"), @@ -287439,7 +287068,7 @@ module rotate_image .Q (rd_ddr_addr[8]), .CLK (clk), .D (image_h_add1[8])); - // ../../sources/designs/rotate/rotate_image.v:288 + // ../../sources/designs/rotate/rotate_image.v:291 GTP_DFF /* \image_h_add2[9] */ #( .GRS_EN("TRUE"), @@ -287448,7 +287077,7 @@ module rotate_image .Q (rd_ddr_addr[9]), .CLK (clk), .D (image_h_add1[9])); - // ../../sources/designs/rotate/rotate_image.v:288 + // ../../sources/designs/rotate/rotate_image.v:291 GTP_DFF /* \image_h_add2[10] */ #( .GRS_EN("TRUE"), @@ -287457,7 +287086,7 @@ module rotate_image .Q (rd_ddr_addr[10]), .CLK (clk), .D (image_h_add1[10])); - // ../../sources/designs/rotate/rotate_image.v:288 + // ../../sources/designs/rotate/rotate_image.v:291 GTP_DFF /* \image_h_add_addr[7] */ #( .GRS_EN("TRUE"), @@ -287466,7 +287095,7 @@ module rotate_image .Q (image_h_add_addr[7]), .CLK (clk), .D (centerY[0])); - // ../../sources/designs/rotate/rotate_image.v:93 + // ../../sources/designs/rotate/rotate_image.v:96 GTP_DFF /* \image_h_add_addr[8] */ #( .GRS_EN("TRUE"), @@ -287475,7 +287104,7 @@ module rotate_image .Q (image_h_add_addr[8]), .CLK (clk), .D (centerY[1])); - // ../../sources/designs/rotate/rotate_image.v:93 + // ../../sources/designs/rotate/rotate_image.v:96 GTP_DFF /* \image_h_add_addr[9] */ #( .GRS_EN("TRUE"), @@ -287484,7 +287113,7 @@ module rotate_image .Q (image_h_add_addr[9]), .CLK (clk), .D (centerY[2])); - // ../../sources/designs/rotate/rotate_image.v:93 + // ../../sources/designs/rotate/rotate_image.v:96 GTP_DFF /* \image_h_add_addr[10] */ #( .GRS_EN("TRUE"), @@ -287493,7 +287122,7 @@ module rotate_image .Q (image_h_add_addr[10]), .CLK (clk), .D (centerY[3])); - // ../../sources/designs/rotate/rotate_image.v:93 + // ../../sources/designs/rotate/rotate_image.v:96 GTP_DFF /* \image_h_add_addr[11] */ #( .GRS_EN("TRUE"), @@ -287502,7 +287131,7 @@ module rotate_image .Q (image_h_add_addr[11]), .CLK (clk), .D (centerY[4])); - // ../../sources/designs/rotate/rotate_image.v:93 + // ../../sources/designs/rotate/rotate_image.v:96 GTP_DFF /* \image_h_add_addr[12] */ #( .GRS_EN("TRUE"), @@ -287511,7 +287140,7 @@ module rotate_image .Q (image_h_add_addr[12]), .CLK (clk), .D (centerY[5])); - // ../../sources/designs/rotate/rotate_image.v:93 + // ../../sources/designs/rotate/rotate_image.v:96 GTP_DFF /* \image_h_add_addr[13] */ #( .GRS_EN("TRUE"), @@ -287520,7 +287149,7 @@ module rotate_image .Q (image_h_add_addr[13]), .CLK (clk), .D (centerY[6])); - // ../../sources/designs/rotate/rotate_image.v:93 + // ../../sources/designs/rotate/rotate_image.v:96 GTP_DFF /* \image_h_add_addr[14] */ #( .GRS_EN("TRUE"), @@ -287529,7 +287158,7 @@ module rotate_image .Q (image_h_add_addr[14]), .CLK (clk), .D (centerY[7])); - // ../../sources/designs/rotate/rotate_image.v:93 + // ../../sources/designs/rotate/rotate_image.v:96 GTP_DFF /* \image_h_add_addr[15] */ #( .GRS_EN("TRUE"), @@ -287538,7 +287167,7 @@ module rotate_image .Q (image_h_add_addr[15]), .CLK (clk), .D (centerY[8])); - // ../../sources/designs/rotate/rotate_image.v:93 + // ../../sources/designs/rotate/rotate_image.v:96 GTP_DFF /* \image_h_add_addr[16] */ #( .GRS_EN("TRUE"), @@ -287547,7 +287176,7 @@ module rotate_image .Q (image_h_add_addr[16]), .CLK (clk), .D (centerY[9])); - // ../../sources/designs/rotate/rotate_image.v:93 + // ../../sources/designs/rotate/rotate_image.v:96 GTP_DFF /* \image_h_add_addr[17] */ #( .GRS_EN("TRUE"), @@ -287556,7 +287185,7 @@ module rotate_image .Q (image_h_add_addr[17]), .CLK (clk), .D (centerY[10])); - // ../../sources/designs/rotate/rotate_image.v:93 + // ../../sources/designs/rotate/rotate_image.v:96 GTP_DFF /* \image_h_add_addr[18] */ #( .GRS_EN("TRUE"), @@ -287565,7 +287194,7 @@ module rotate_image .Q (image_h_add_addr[18]), .CLK (clk), .D (centerY[11])); - // ../../sources/designs/rotate/rotate_image.v:93 + // ../../sources/designs/rotate/rotate_image.v:96 GTP_DFF /* image_h_blank_valid */ #( .GRS_EN("TRUE"), @@ -287575,7 +287204,7 @@ module rotate_image .CLK (clk), .D (N147)); // defparam image_h_blank_valid_vname.orig_name = image_h_blank_valid; - // ../../sources/designs/rotate/rotate_image.v:277 + // ../../sources/designs/rotate/rotate_image.v:280 GTP_DFF /* \image_w_add0[7] */ #( .GRS_EN("TRUE"), @@ -287584,7 +287213,7 @@ module rotate_image .Q (image_w_add0[7]), .CLK (clk), .D (N119[7])); - // ../../sources/designs/rotate/rotate_image.v:268 + // ../../sources/designs/rotate/rotate_image.v:271 GTP_DFF /* \image_w_add0[8] */ #( .GRS_EN("TRUE"), @@ -287593,7 +287222,7 @@ module rotate_image .Q (image_w_add0[8]), .CLK (clk), .D (N119[8])); - // ../../sources/designs/rotate/rotate_image.v:268 + // ../../sources/designs/rotate/rotate_image.v:271 GTP_DFF /* \image_w_add0[9] */ #( .GRS_EN("TRUE"), @@ -287602,7 +287231,7 @@ module rotate_image .Q (image_w_add0[9]), .CLK (clk), .D (N119[9])); - // ../../sources/designs/rotate/rotate_image.v:268 + // ../../sources/designs/rotate/rotate_image.v:271 GTP_DFF /* \image_w_add0[10] */ #( .GRS_EN("TRUE"), @@ -287611,7 +287240,7 @@ module rotate_image .Q (image_w_add0[10]), .CLK (clk), .D (N119[10])); - // ../../sources/designs/rotate/rotate_image.v:268 + // ../../sources/designs/rotate/rotate_image.v:271 GTP_DFF /* \image_w_add0[11] */ #( .GRS_EN("TRUE"), @@ -287620,7 +287249,7 @@ module rotate_image .Q (image_w_add0[11]), .CLK (clk), .D (N119[11])); - // ../../sources/designs/rotate/rotate_image.v:268 + // ../../sources/designs/rotate/rotate_image.v:271 GTP_DFF /* \image_w_add0[12] */ #( .GRS_EN("TRUE"), @@ -287629,7 +287258,7 @@ module rotate_image .Q (image_w_add0[12]), .CLK (clk), .D (N119[12])); - // ../../sources/designs/rotate/rotate_image.v:268 + // ../../sources/designs/rotate/rotate_image.v:271 GTP_DFF /* \image_w_add0[13] */ #( .GRS_EN("TRUE"), @@ -287638,7 +287267,7 @@ module rotate_image .Q (image_w_add0[13]), .CLK (clk), .D (N119[13])); - // ../../sources/designs/rotate/rotate_image.v:268 + // ../../sources/designs/rotate/rotate_image.v:271 GTP_DFF /* \image_w_add0[14] */ #( .GRS_EN("TRUE"), @@ -287647,7 +287276,7 @@ module rotate_image .Q (image_w_add0[14]), .CLK (clk), .D (N119[14])); - // ../../sources/designs/rotate/rotate_image.v:268 + // ../../sources/designs/rotate/rotate_image.v:271 GTP_DFF /* \image_w_add0[15] */ #( .GRS_EN("TRUE"), @@ -287656,7 +287285,7 @@ module rotate_image .Q (image_w_add0[15]), .CLK (clk), .D (N119[15])); - // ../../sources/designs/rotate/rotate_image.v:268 + // ../../sources/designs/rotate/rotate_image.v:271 GTP_DFF /* \image_w_add0[16] */ #( .GRS_EN("TRUE"), @@ -287665,7 +287294,7 @@ module rotate_image .Q (image_w_add0[16]), .CLK (clk), .D (N119[16])); - // ../../sources/designs/rotate/rotate_image.v:268 + // ../../sources/designs/rotate/rotate_image.v:271 GTP_DFF /* \image_w_add0[17] */ #( .GRS_EN("TRUE"), @@ -287674,7 +287303,7 @@ module rotate_image .Q (image_w_add0[17]), .CLK (clk), .D (N119[17])); - // ../../sources/designs/rotate/rotate_image.v:268 + // ../../sources/designs/rotate/rotate_image.v:271 GTP_DFF /* \image_w_add0[18] */ #( .GRS_EN("TRUE"), @@ -287683,7 +287312,7 @@ module rotate_image .Q (image_w_add0[18]), .CLK (clk), .D (N119[18])); - // ../../sources/designs/rotate/rotate_image.v:268 + // ../../sources/designs/rotate/rotate_image.v:271 GTP_DFF /* \image_w_add0[19] */ #( .GRS_EN("TRUE"), @@ -287692,7 +287321,7 @@ module rotate_image .Q (image_w_add0[19]), .CLK (clk), .D (N119[19])); - // ../../sources/designs/rotate/rotate_image.v:268 + // ../../sources/designs/rotate/rotate_image.v:271 GTP_DFF /* \image_w_add0[20] */ #( .GRS_EN("TRUE"), @@ -287701,7 +287330,7 @@ module rotate_image .Q (image_w_add0[20]), .CLK (clk), .D (N119[20])); - // ../../sources/designs/rotate/rotate_image.v:268 + // ../../sources/designs/rotate/rotate_image.v:271 GTP_DFF /* \image_w_add0[21] */ #( .GRS_EN("TRUE"), @@ -287710,7 +287339,7 @@ module rotate_image .Q (image_w_add0[21]), .CLK (clk), .D (N119[21])); - // ../../sources/designs/rotate/rotate_image.v:268 + // ../../sources/designs/rotate/rotate_image.v:271 GTP_DFF /* \image_w_add0[22] */ #( .GRS_EN("TRUE"), @@ -287719,7 +287348,7 @@ module rotate_image .Q (image_w_add0[22]), .CLK (clk), .D (N119[22])); - // ../../sources/designs/rotate/rotate_image.v:268 + // ../../sources/designs/rotate/rotate_image.v:271 GTP_DFF /* \image_w_add0[23] */ #( .GRS_EN("TRUE"), @@ -287728,7 +287357,7 @@ module rotate_image .Q (image_w_add0[23]), .CLK (clk), .D (N119[23])); - // ../../sources/designs/rotate/rotate_image.v:268 + // ../../sources/designs/rotate/rotate_image.v:271 GTP_DFF /* \image_w_add0[24] */ #( .GRS_EN("TRUE"), @@ -287737,7 +287366,7 @@ module rotate_image .Q (image_w_add0[24]), .CLK (clk), .D (N119[24])); - // ../../sources/designs/rotate/rotate_image.v:268 + // ../../sources/designs/rotate/rotate_image.v:271 GTP_DFF /* \image_w_add0[25] */ #( .GRS_EN("TRUE"), @@ -287746,7 +287375,7 @@ module rotate_image .Q (image_w_add0[25]), .CLK (clk), .D (N119[25])); - // ../../sources/designs/rotate/rotate_image.v:268 + // ../../sources/designs/rotate/rotate_image.v:271 GTP_DFF /* \image_w_add1[0] */ #( .GRS_EN("TRUE"), @@ -287755,7 +287384,7 @@ module rotate_image .Q (image_w_add1[0]), .CLK (clk), .D (image_w_add0[7])); - // ../../sources/designs/rotate/rotate_image.v:288 + // ../../sources/designs/rotate/rotate_image.v:291 GTP_DFF /* \image_w_add1[1] */ #( .GRS_EN("TRUE"), @@ -287764,7 +287393,7 @@ module rotate_image .Q (image_w_add1[1]), .CLK (clk), .D (image_w_add0[8])); - // ../../sources/designs/rotate/rotate_image.v:288 + // ../../sources/designs/rotate/rotate_image.v:291 GTP_DFF /* \image_w_add1[2] */ #( .GRS_EN("TRUE"), @@ -287773,7 +287402,7 @@ module rotate_image .Q (image_w_add1[2]), .CLK (clk), .D (image_w_add0[9])); - // ../../sources/designs/rotate/rotate_image.v:288 + // ../../sources/designs/rotate/rotate_image.v:291 GTP_DFF /* \image_w_add1[3] */ #( .GRS_EN("TRUE"), @@ -287782,7 +287411,7 @@ module rotate_image .Q (image_w_add1[3]), .CLK (clk), .D (image_w_add0[10])); - // ../../sources/designs/rotate/rotate_image.v:288 + // ../../sources/designs/rotate/rotate_image.v:291 GTP_DFF /* \image_w_add1[4] */ #( .GRS_EN("TRUE"), @@ -287791,7 +287420,7 @@ module rotate_image .Q (image_w_add1[4]), .CLK (clk), .D (image_w_add0[11])); - // ../../sources/designs/rotate/rotate_image.v:288 + // ../../sources/designs/rotate/rotate_image.v:291 GTP_DFF /* \image_w_add1[5] */ #( .GRS_EN("TRUE"), @@ -287800,7 +287429,7 @@ module rotate_image .Q (image_w_add1[5]), .CLK (clk), .D (image_w_add0[12])); - // ../../sources/designs/rotate/rotate_image.v:288 + // ../../sources/designs/rotate/rotate_image.v:291 GTP_DFF /* \image_w_add1[6] */ #( .GRS_EN("TRUE"), @@ -287809,7 +287438,7 @@ module rotate_image .Q (image_w_add1[6]), .CLK (clk), .D (image_w_add0[13])); - // ../../sources/designs/rotate/rotate_image.v:288 + // ../../sources/designs/rotate/rotate_image.v:291 GTP_DFF /* \image_w_add1[7] */ #( .GRS_EN("TRUE"), @@ -287818,7 +287447,7 @@ module rotate_image .Q (image_w_add1[7]), .CLK (clk), .D (image_w_add0[14])); - // ../../sources/designs/rotate/rotate_image.v:288 + // ../../sources/designs/rotate/rotate_image.v:291 GTP_DFF /* \image_w_add1[8] */ #( .GRS_EN("TRUE"), @@ -287827,7 +287456,7 @@ module rotate_image .Q (image_w_add1[8]), .CLK (clk), .D (image_w_add0[15])); - // ../../sources/designs/rotate/rotate_image.v:288 + // ../../sources/designs/rotate/rotate_image.v:291 GTP_DFF /* \image_w_add1[9] */ #( .GRS_EN("TRUE"), @@ -287836,7 +287465,7 @@ module rotate_image .Q (image_w_add1[9]), .CLK (clk), .D (image_w_add0[16])); - // ../../sources/designs/rotate/rotate_image.v:288 + // ../../sources/designs/rotate/rotate_image.v:291 GTP_DFF /* \image_w_add1[10] */ #( .GRS_EN("TRUE"), @@ -287845,7 +287474,7 @@ module rotate_image .Q (image_w_add1[10]), .CLK (clk), .D (image_w_add0[17])); - // ../../sources/designs/rotate/rotate_image.v:288 + // ../../sources/designs/rotate/rotate_image.v:291 GTP_DFF /* \image_w_add2[0] */ #( .GRS_EN("TRUE"), @@ -287854,7 +287483,7 @@ module rotate_image .Q (rd_ddr_addr[16]), .CLK (clk), .D (image_w_add1[0])); - // ../../sources/designs/rotate/rotate_image.v:288 + // ../../sources/designs/rotate/rotate_image.v:291 GTP_DFF /* \image_w_add2[1] */ #( .GRS_EN("TRUE"), @@ -287863,7 +287492,7 @@ module rotate_image .Q (rd_ddr_addr[17]), .CLK (clk), .D (image_w_add1[1])); - // ../../sources/designs/rotate/rotate_image.v:288 + // ../../sources/designs/rotate/rotate_image.v:291 GTP_DFF /* \image_w_add2[2] */ #( .GRS_EN("TRUE"), @@ -287872,7 +287501,7 @@ module rotate_image .Q (rd_ddr_addr[18]), .CLK (clk), .D (image_w_add1[2])); - // ../../sources/designs/rotate/rotate_image.v:288 + // ../../sources/designs/rotate/rotate_image.v:291 GTP_DFF /* \image_w_add2[3] */ #( .GRS_EN("TRUE"), @@ -287881,7 +287510,7 @@ module rotate_image .Q (rd_ddr_addr[19]), .CLK (clk), .D (image_w_add1[3])); - // ../../sources/designs/rotate/rotate_image.v:288 + // ../../sources/designs/rotate/rotate_image.v:291 GTP_DFF /* \image_w_add2[4] */ #( .GRS_EN("TRUE"), @@ -287890,7 +287519,7 @@ module rotate_image .Q (rd_ddr_addr[20]), .CLK (clk), .D (image_w_add1[4])); - // ../../sources/designs/rotate/rotate_image.v:288 + // ../../sources/designs/rotate/rotate_image.v:291 GTP_DFF /* \image_w_add2[5] */ #( .GRS_EN("TRUE"), @@ -287899,7 +287528,7 @@ module rotate_image .Q (rd_ddr_addr[21]), .CLK (clk), .D (image_w_add1[5])); - // ../../sources/designs/rotate/rotate_image.v:288 + // ../../sources/designs/rotate/rotate_image.v:291 GTP_DFF /* \image_w_add2[6] */ #( .GRS_EN("TRUE"), @@ -287908,7 +287537,7 @@ module rotate_image .Q (rd_ddr_addr[22]), .CLK (clk), .D (image_w_add1[6])); - // ../../sources/designs/rotate/rotate_image.v:288 + // ../../sources/designs/rotate/rotate_image.v:291 GTP_DFF /* \image_w_add2[7] */ #( .GRS_EN("TRUE"), @@ -287917,7 +287546,7 @@ module rotate_image .Q (rd_ddr_addr[23]), .CLK (clk), .D (image_w_add1[7])); - // ../../sources/designs/rotate/rotate_image.v:288 + // ../../sources/designs/rotate/rotate_image.v:291 GTP_DFF /* \image_w_add2[8] */ #( .GRS_EN("TRUE"), @@ -287926,7 +287555,7 @@ module rotate_image .Q (rd_ddr_addr[24]), .CLK (clk), .D (image_w_add1[8])); - // ../../sources/designs/rotate/rotate_image.v:288 + // ../../sources/designs/rotate/rotate_image.v:291 GTP_DFF /* \image_w_add2[9] */ #( .GRS_EN("TRUE"), @@ -287935,7 +287564,7 @@ module rotate_image .Q (rd_ddr_addr[25]), .CLK (clk), .D (image_w_add1[9])); - // ../../sources/designs/rotate/rotate_image.v:288 + // ../../sources/designs/rotate/rotate_image.v:291 GTP_DFF /* \image_w_add2[10] */ #( .GRS_EN("TRUE"), @@ -287944,7 +287573,7 @@ module rotate_image .Q (rd_ddr_addr[26]), .CLK (clk), .D (image_w_add1[10])); - // ../../sources/designs/rotate/rotate_image.v:288 + // ../../sources/designs/rotate/rotate_image.v:291 GTP_DFF /* \image_w_add_addr[7] */ #( .GRS_EN("TRUE"), @@ -287953,7 +287582,7 @@ module rotate_image .Q (image_w_add_addr[7]), .CLK (clk), .D (centerX[0])); - // ../../sources/designs/rotate/rotate_image.v:93 + // ../../sources/designs/rotate/rotate_image.v:96 GTP_DFF /* \image_w_add_addr[8] */ #( .GRS_EN("TRUE"), @@ -287962,7 +287591,7 @@ module rotate_image .Q (image_w_add_addr[8]), .CLK (clk), .D (centerX[1])); - // ../../sources/designs/rotate/rotate_image.v:93 + // ../../sources/designs/rotate/rotate_image.v:96 GTP_DFF /* \image_w_add_addr[9] */ #( .GRS_EN("TRUE"), @@ -287971,7 +287600,7 @@ module rotate_image .Q (image_w_add_addr[9]), .CLK (clk), .D (centerX[2])); - // ../../sources/designs/rotate/rotate_image.v:93 + // ../../sources/designs/rotate/rotate_image.v:96 GTP_DFF /* \image_w_add_addr[10] */ #( .GRS_EN("TRUE"), @@ -287980,7 +287609,7 @@ module rotate_image .Q (image_w_add_addr[10]), .CLK (clk), .D (centerX[3])); - // ../../sources/designs/rotate/rotate_image.v:93 + // ../../sources/designs/rotate/rotate_image.v:96 GTP_DFF /* \image_w_add_addr[11] */ #( .GRS_EN("TRUE"), @@ -287989,7 +287618,7 @@ module rotate_image .Q (image_w_add_addr[11]), .CLK (clk), .D (centerX[4])); - // ../../sources/designs/rotate/rotate_image.v:93 + // ../../sources/designs/rotate/rotate_image.v:96 GTP_DFF /* \image_w_add_addr[12] */ #( .GRS_EN("TRUE"), @@ -287998,7 +287627,7 @@ module rotate_image .Q (image_w_add_addr[12]), .CLK (clk), .D (centerX[5])); - // ../../sources/designs/rotate/rotate_image.v:93 + // ../../sources/designs/rotate/rotate_image.v:96 GTP_DFF /* \image_w_add_addr[13] */ #( .GRS_EN("TRUE"), @@ -288007,7 +287636,7 @@ module rotate_image .Q (image_w_add_addr[13]), .CLK (clk), .D (centerX[6])); - // ../../sources/designs/rotate/rotate_image.v:93 + // ../../sources/designs/rotate/rotate_image.v:96 GTP_DFF /* \image_w_add_addr[14] */ #( .GRS_EN("TRUE"), @@ -288016,7 +287645,7 @@ module rotate_image .Q (image_w_add_addr[14]), .CLK (clk), .D (centerX[7])); - // ../../sources/designs/rotate/rotate_image.v:93 + // ../../sources/designs/rotate/rotate_image.v:96 GTP_DFF /* \image_w_add_addr[15] */ #( .GRS_EN("TRUE"), @@ -288025,7 +287654,7 @@ module rotate_image .Q (image_w_add_addr[15]), .CLK (clk), .D (centerX[8])); - // ../../sources/designs/rotate/rotate_image.v:93 + // ../../sources/designs/rotate/rotate_image.v:96 GTP_DFF /* \image_w_add_addr[16] */ #( .GRS_EN("TRUE"), @@ -288034,7 +287663,7 @@ module rotate_image .Q (image_w_add_addr[16]), .CLK (clk), .D (centerX[9])); - // ../../sources/designs/rotate/rotate_image.v:93 + // ../../sources/designs/rotate/rotate_image.v:96 GTP_DFF /* \image_w_add_addr[17] */ #( .GRS_EN("TRUE"), @@ -288043,7 +287672,7 @@ module rotate_image .Q (image_w_add_addr[17]), .CLK (clk), .D (centerX[10])); - // ../../sources/designs/rotate/rotate_image.v:93 + // ../../sources/designs/rotate/rotate_image.v:96 GTP_DFF /* \image_w_add_addr[18] */ #( .GRS_EN("TRUE"), @@ -288052,7 +287681,7 @@ module rotate_image .Q (image_w_add_addr[18]), .CLK (clk), .D (centerX[11])); - // ../../sources/designs/rotate/rotate_image.v:93 + // ../../sources/designs/rotate/rotate_image.v:96 GTP_DFF /* image_w_blank_valid */ #( .GRS_EN("TRUE"), @@ -288062,7 +287691,7 @@ module rotate_image .CLK (clk), .D (N134)); // defparam image_w_blank_valid_vname.orig_name = image_w_blank_valid; - // ../../sources/designs/rotate/rotate_image.v:277 + // ../../sources/designs/rotate/rotate_image.v:280 GTP_DFF_R /* \image_w_valid0[0] */ #( .GRS_EN("TRUE"), @@ -288072,7 +287701,7 @@ module rotate_image .CLK (clk), .D (image_w_valid), .R (rst)); - // ../../sources/designs/rotate/rotate_image.v:255 + // ../../sources/designs/rotate/rotate_image.v:258 GTP_DFF_R /* \image_w_valid0[1] */ #( .GRS_EN("TRUE"), @@ -288082,7 +287711,7 @@ module rotate_image .CLK (clk), .D (image_w_valid0[0]), .R (rst)); - // ../../sources/designs/rotate/rotate_image.v:255 + // ../../sources/designs/rotate/rotate_image.v:258 GTP_DFF_R /* \image_w_valid0[2] */ #( .GRS_EN("TRUE"), @@ -288092,7 +287721,7 @@ module rotate_image .CLK (clk), .D (image_w_valid0[1]), .R (rst)); - // ../../sources/designs/rotate/rotate_image.v:255 + // ../../sources/designs/rotate/rotate_image.v:258 GTP_DFF_R /* \image_w_valid0[3] */ #( .GRS_EN("TRUE"), @@ -288102,7 +287731,7 @@ module rotate_image .CLK (clk), .D (image_w_valid0[2]), .R (rst)); - // ../../sources/designs/rotate/rotate_image.v:255 + // ../../sources/designs/rotate/rotate_image.v:258 GTP_DFF_R /* \image_w_valid0[4] */ #( .GRS_EN("TRUE"), @@ -288112,7 +287741,7 @@ module rotate_image .CLK (clk), .D (image_w_valid0[3]), .R (rst)); - // ../../sources/designs/rotate/rotate_image.v:255 + // ../../sources/designs/rotate/rotate_image.v:258 GTP_DFF_RE /* \offsetX_ff[0] */ #( .GRS_EN("TRUE"), @@ -288123,7 +287752,7 @@ module rotate_image .CLK (clk), .D (offsetX[0]), .R (rst)); - // ../../sources/designs/rotate/rotate_image.v:75 + // ../../sources/designs/rotate/rotate_image.v:78 GTP_DFF_RE /* \offsetX_ff[1] */ #( .GRS_EN("TRUE"), @@ -288134,7 +287763,7 @@ module rotate_image .CLK (clk), .D (offsetX[1]), .R (rst)); - // ../../sources/designs/rotate/rotate_image.v:75 + // ../../sources/designs/rotate/rotate_image.v:78 GTP_DFF_RE /* \offsetX_ff[2] */ #( .GRS_EN("TRUE"), @@ -288145,7 +287774,7 @@ module rotate_image .CLK (clk), .D (offsetX[2]), .R (rst)); - // ../../sources/designs/rotate/rotate_image.v:75 + // ../../sources/designs/rotate/rotate_image.v:78 GTP_DFF_RE /* \offsetX_ff[3] */ #( .GRS_EN("TRUE"), @@ -288156,7 +287785,7 @@ module rotate_image .CLK (clk), .D (offsetX[3]), .R (rst)); - // ../../sources/designs/rotate/rotate_image.v:75 + // ../../sources/designs/rotate/rotate_image.v:78 GTP_DFF_RE /* \offsetX_ff[4] */ #( .GRS_EN("TRUE"), @@ -288167,7 +287796,7 @@ module rotate_image .CLK (clk), .D (offsetX[4]), .R (rst)); - // ../../sources/designs/rotate/rotate_image.v:75 + // ../../sources/designs/rotate/rotate_image.v:78 GTP_DFF_RE /* \offsetX_ff[5] */ #( .GRS_EN("TRUE"), @@ -288178,7 +287807,7 @@ module rotate_image .CLK (clk), .D (offsetX[5]), .R (rst)); - // ../../sources/designs/rotate/rotate_image.v:75 + // ../../sources/designs/rotate/rotate_image.v:78 GTP_DFF_RE /* \offsetX_ff[6] */ #( .GRS_EN("TRUE"), @@ -288189,7 +287818,7 @@ module rotate_image .CLK (clk), .D (offsetX[6]), .R (rst)); - // ../../sources/designs/rotate/rotate_image.v:75 + // ../../sources/designs/rotate/rotate_image.v:78 GTP_DFF_RE /* \offsetX_ff[7] */ #( .GRS_EN("TRUE"), @@ -288200,7 +287829,7 @@ module rotate_image .CLK (clk), .D (offsetX[7]), .R (rst)); - // ../../sources/designs/rotate/rotate_image.v:75 + // ../../sources/designs/rotate/rotate_image.v:78 GTP_DFF_RE /* \offsetX_ff[8] */ #( .GRS_EN("TRUE"), @@ -288211,7 +287840,7 @@ module rotate_image .CLK (clk), .D (offsetX[8]), .R (rst)); - // ../../sources/designs/rotate/rotate_image.v:75 + // ../../sources/designs/rotate/rotate_image.v:78 GTP_DFF_RE /* \offsetX_ff[9] */ #( .GRS_EN("TRUE"), @@ -288222,7 +287851,7 @@ module rotate_image .CLK (clk), .D (offsetX[9]), .R (rst)); - // ../../sources/designs/rotate/rotate_image.v:75 + // ../../sources/designs/rotate/rotate_image.v:78 GTP_DFF_RE /* \offsetX_ff[10] */ #( .GRS_EN("TRUE"), @@ -288233,7 +287862,7 @@ module rotate_image .CLK (clk), .D (offsetX[10]), .R (rst)); - // ../../sources/designs/rotate/rotate_image.v:75 + // ../../sources/designs/rotate/rotate_image.v:78 GTP_DFF_RE /* \offsetX_ff[11] */ #( .GRS_EN("TRUE"), @@ -288244,7 +287873,7 @@ module rotate_image .CLK (clk), .D (offsetX[11]), .R (rst)); - // ../../sources/designs/rotate/rotate_image.v:75 + // ../../sources/designs/rotate/rotate_image.v:78 GTP_DFF_RE /* \offsetY_ff[0] */ #( .GRS_EN("TRUE"), @@ -288255,7 +287884,7 @@ module rotate_image .CLK (clk), .D (offsetY[0]), .R (rst)); - // ../../sources/designs/rotate/rotate_image.v:75 + // ../../sources/designs/rotate/rotate_image.v:78 GTP_DFF_RE /* \offsetY_ff[1] */ #( .GRS_EN("TRUE"), @@ -288266,7 +287895,7 @@ module rotate_image .CLK (clk), .D (offsetY[1]), .R (rst)); - // ../../sources/designs/rotate/rotate_image.v:75 + // ../../sources/designs/rotate/rotate_image.v:78 GTP_DFF_RE /* \offsetY_ff[2] */ #( .GRS_EN("TRUE"), @@ -288277,7 +287906,7 @@ module rotate_image .CLK (clk), .D (offsetY[2]), .R (rst)); - // ../../sources/designs/rotate/rotate_image.v:75 + // ../../sources/designs/rotate/rotate_image.v:78 GTP_DFF_RE /* \offsetY_ff[3] */ #( .GRS_EN("TRUE"), @@ -288288,7 +287917,7 @@ module rotate_image .CLK (clk), .D (offsetY[3]), .R (rst)); - // ../../sources/designs/rotate/rotate_image.v:75 + // ../../sources/designs/rotate/rotate_image.v:78 GTP_DFF_RE /* \offsetY_ff[4] */ #( .GRS_EN("TRUE"), @@ -288299,7 +287928,7 @@ module rotate_image .CLK (clk), .D (offsetY[4]), .R (rst)); - // ../../sources/designs/rotate/rotate_image.v:75 + // ../../sources/designs/rotate/rotate_image.v:78 GTP_DFF_RE /* \offsetY_ff[5] */ #( .GRS_EN("TRUE"), @@ -288310,7 +287939,7 @@ module rotate_image .CLK (clk), .D (offsetY[5]), .R (rst)); - // ../../sources/designs/rotate/rotate_image.v:75 + // ../../sources/designs/rotate/rotate_image.v:78 GTP_DFF_RE /* \offsetY_ff[6] */ #( .GRS_EN("TRUE"), @@ -288321,7 +287950,7 @@ module rotate_image .CLK (clk), .D (offsetY[6]), .R (rst)); - // ../../sources/designs/rotate/rotate_image.v:75 + // ../../sources/designs/rotate/rotate_image.v:78 GTP_DFF_RE /* \offsetY_ff[7] */ #( .GRS_EN("TRUE"), @@ -288332,7 +287961,7 @@ module rotate_image .CLK (clk), .D (offsetY[7]), .R (rst)); - // ../../sources/designs/rotate/rotate_image.v:75 + // ../../sources/designs/rotate/rotate_image.v:78 GTP_DFF_RE /* \offsetY_ff[8] */ #( .GRS_EN("TRUE"), @@ -288343,7 +287972,7 @@ module rotate_image .CLK (clk), .D (offsetY[8]), .R (rst)); - // ../../sources/designs/rotate/rotate_image.v:75 + // ../../sources/designs/rotate/rotate_image.v:78 GTP_DFF_RE /* \offsetY_ff[9] */ #( .GRS_EN("TRUE"), @@ -288354,7 +287983,7 @@ module rotate_image .CLK (clk), .D (offsetY[9]), .R (rst)); - // ../../sources/designs/rotate/rotate_image.v:75 + // ../../sources/designs/rotate/rotate_image.v:78 GTP_DFF_RE /* \offsetY_ff[10] */ #( .GRS_EN("TRUE"), @@ -288365,7 +287994,7 @@ module rotate_image .CLK (clk), .D (offsetY[10]), .R (rst)); - // ../../sources/designs/rotate/rotate_image.v:75 + // ../../sources/designs/rotate/rotate_image.v:78 GTP_DFF_RE /* \offsetY_ff[11] */ #( .GRS_EN("TRUE"), @@ -288376,7 +288005,7 @@ module rotate_image .CLK (clk), .D (offsetY[11]), .R (rst)); - // ../../sources/designs/rotate/rotate_image.v:75 + // ../../sources/designs/rotate/rotate_image.v:78 GTP_DFF_E /* \rd_addr[0] */ #( .GRS_EN("TRUE"), @@ -288386,7 +288015,7 @@ module rotate_image .CE (rotate_sta_reg[0]), .CLK (clk), .D (rotate_angle[0])); - // ../../sources/designs/rotate/rotate_image.v:67 + // ../../sources/designs/rotate/rotate_image.v:70 GTP_DFF_E /* \rd_addr[1] */ #( .GRS_EN("TRUE"), @@ -288396,7 +288025,7 @@ module rotate_image .CE (rotate_sta_reg[0]), .CLK (clk), .D (rotate_angle[1])); - // ../../sources/designs/rotate/rotate_image.v:67 + // ../../sources/designs/rotate/rotate_image.v:70 GTP_DFF_E /* \rd_addr[2] */ #( .GRS_EN("TRUE"), @@ -288406,7 +288035,7 @@ module rotate_image .CE (rotate_sta_reg[0]), .CLK (clk), .D (rotate_angle[2])); - // ../../sources/designs/rotate/rotate_image.v:67 + // ../../sources/designs/rotate/rotate_image.v:70 GTP_DFF_E /* \rd_addr[3] */ #( .GRS_EN("TRUE"), @@ -288416,7 +288045,7 @@ module rotate_image .CE (rotate_sta_reg[0]), .CLK (clk), .D (rotate_angle[3])); - // ../../sources/designs/rotate/rotate_image.v:67 + // ../../sources/designs/rotate/rotate_image.v:70 GTP_DFF_E /* \rd_addr[4] */ #( .GRS_EN("TRUE"), @@ -288426,7 +288055,7 @@ module rotate_image .CE (rotate_sta_reg[0]), .CLK (clk), .D (rotate_angle[4])); - // ../../sources/designs/rotate/rotate_image.v:67 + // ../../sources/designs/rotate/rotate_image.v:70 GTP_DFF_E /* \rd_addr[5] */ #( .GRS_EN("TRUE"), @@ -288436,7 +288065,7 @@ module rotate_image .CE (rotate_sta_reg[0]), .CLK (clk), .D (rotate_angle[5])); - // ../../sources/designs/rotate/rotate_image.v:67 + // ../../sources/designs/rotate/rotate_image.v:70 GTP_DFF_E /* \rd_addr[6] */ #( .GRS_EN("TRUE"), @@ -288446,7 +288075,7 @@ module rotate_image .CE (rotate_sta_reg[0]), .CLK (clk), .D (rotate_angle[6])); - // ../../sources/designs/rotate/rotate_image.v:67 + // ../../sources/designs/rotate/rotate_image.v:70 GTP_DFF_E /* \rd_addr[7] */ #( .GRS_EN("TRUE"), @@ -288456,7 +288085,7 @@ module rotate_image .CE (rotate_sta_reg[0]), .CLK (clk), .D (rotate_angle[7])); - // ../../sources/designs/rotate/rotate_image.v:67 + // ../../sources/designs/rotate/rotate_image.v:70 GTP_DFF /* rd_ddr_addr_valid1 */ #( .GRS_EN("TRUE"), @@ -288465,7 +288094,7 @@ module rotate_image .Q (rd_ddr_addr_valid), .CLK (clk), .D (rd_ddr_addr_valid0)); - // ../../sources/designs/rotate/rotate_image.v:277 + // ../../sources/designs/rotate/rotate_image.v:280 GTP_LUT5M /* \rd_sta_fsm[2:0]_10 */ #( .INIT(32'b11000000110010001100010011001100)) @@ -288488,7 +288117,7 @@ module rotate_image .I2 (rd_sta_reg[1]), .I3 (rd_sta_reg[2])); // LUT = (I0&I3)|(I0&~I1&I2) ; - // ../../sources/designs/rotate/rotate_image.v:387 + // ../../sources/designs/rotate/rotate_image.v:390 GTP_LUT5M /* \rd_sta_fsm[2:0]_20 */ #( .INIT(32'b00000000111110000000000011111110)) @@ -288510,7 +288139,7 @@ module rotate_image .CLK (clk), .D (_N7), .S (rst)); - // ../../sources/designs/rotate/rotate_image.v:387 + // ../../sources/designs/rotate/rotate_image.v:390 (* syn_encoding="onehot" *) GTP_DFF_R /* \rd_sta_reg[1] */ #( .GRS_EN("TRUE"), @@ -288520,7 +288149,7 @@ module rotate_image .CLK (clk), .D (_N13), .R (rst)); - // ../../sources/designs/rotate/rotate_image.v:387 + // ../../sources/designs/rotate/rotate_image.v:390 (* syn_encoding="onehot" *) GTP_DFF_R /* \rd_sta_reg[2] */ #( .GRS_EN("TRUE"), @@ -288530,7 +288159,7 @@ module rotate_image .CLK (clk), .D (_N16), .R (rst)); - // ../../sources/designs/rotate/rotate_image.v:387 + // ../../sources/designs/rotate/rotate_image.v:390 GTP_DFF /* rd_sta_s2 */ #( .GRS_EN("TRUE"), @@ -288540,7 +288169,7 @@ module rotate_image .CLK (clk), .D (N226)); // defparam rd_sta_s2_vname.orig_name = rd_sta_s2; - // ../../sources/designs/rotate/rotate_image.v:411 + // ../../sources/designs/rotate/rotate_image.v:414 GTP_LUT3 /* \rotate_sta_fsm[2:0]_1 */ #( .INIT(8'b01110000)) @@ -288550,27 +288179,27 @@ module rotate_image .I1 (addr_fifo_empty), .I2 (rotate_sta_reg[0])); // LUT = (~I1&I2)|(~I0&I2) ; - // ../../sources/designs/rotate/rotate_image.v:135 + // ../../sources/designs/rotate/rotate_image.v:138 GTP_LUT5 /* \rotate_sta_fsm[2:0]_4 */ #( .INIT(32'b11111111111111110000000000010000)) \rotate_sta_fsm[2:0]_4 ( .Z (_N20), - .I0 (_N9933), + .I0 (_N9968), .I1 (N52), .I2 (image_w_valid), .I3 (cnt_h[10]), .I4 (_N17)); // LUT = (I4)|(~I0&~I1&I2&~I3) ; - // ../../sources/designs/rotate/rotate_image.v:135 + // ../../sources/designs/rotate/rotate_image.v:138 GTP_LUT5 /* \rotate_sta_fsm[2:0]_9_2 */ #( .INIT(32'b10001111000011111000100000000000)) \rotate_sta_fsm[2:0]_9_2 ( - .Z (_N104632), + .Z (_N105467), .I0 (rotate_en), .I1 (addr_fifo_empty), - .I2 (N340[2]), + .I2 (N396[2]), .I3 (rotate_sta_reg[0]), .I4 (rotate_sta_reg[1])); // LUT = (~I2&I4)|(I0&I1&I3) ; @@ -288579,11 +288208,11 @@ module rotate_image .INIT(32'b11111111111111110011000000100000)) \rotate_sta_fsm[2:0]_9_3 ( .Z (_N25), - .I0 (_N9933), + .I0 (_N9968), .I1 (N52), .I2 (image_w_valid), .I3 (cnt_h[10]), - .I4 (_N104632)); + .I4 (_N105467)); // LUT = (I4)|(I0&~I1&I2)|(~I1&I2&I3) ; GTP_LUT4 /* \rotate_sta_fsm[2:0]_12 */ #( @@ -288592,10 +288221,10 @@ module rotate_image .Z (_N28), .I0 (N52), .I1 (image_w_valid), - .I2 (N340[2]), + .I2 (N396[2]), .I3 (rotate_sta_reg[1])); // LUT = (I0&I1)|(I2&I3) ; - // ../../sources/designs/rotate/rotate_image.v:135 + // ../../sources/designs/rotate/rotate_image.v:138 (* syn_encoding="onehot" *) GTP_DFF_S /* \rotate_sta_reg[0] */ #( .GRS_EN("TRUE"), @@ -288605,7 +288234,7 @@ module rotate_image .CLK (clk), .D (_N20), .S (rst)); - // ../../sources/designs/rotate/rotate_image.v:135 + // ../../sources/designs/rotate/rotate_image.v:138 (* syn_encoding="onehot" *) GTP_DFF_R /* \rotate_sta_reg[1] */ #( .GRS_EN("TRUE"), @@ -288615,7 +288244,7 @@ module rotate_image .CLK (clk), .D (_N25), .R (rst)); - // ../../sources/designs/rotate/rotate_image.v:135 + // ../../sources/designs/rotate/rotate_image.v:138 (* syn_encoding="onehot" *) GTP_DFF_R /* \rotate_sta_reg[2] */ #( .GRS_EN("TRUE"), @@ -288625,17 +288254,15 @@ module rotate_image .CLK (clk), .D (_N28), .R (rst)); - // ../../sources/designs/rotate/rotate_image.v:135 + // ../../sources/designs/rotate/rotate_image.v:138 rotate_mult0_1 u_rotate_mult0 ( .\u_rotate_image/w_mult_add ({w_mult_add[24], w_mult_add[23], w_mult_add[22], w_mult_add[21], w_mult_add[20], w_mult_add[19], w_mult_add[18], w_mult_add[17], w_mult_add[16], w_mult_add[15], w_mult_add[14], w_mult_add[13], w_mult_add[12], w_mult_add[11], w_mult_add[10], w_mult_add[9], w_mult_add[8], w_mult_add[7], w_mult_add[6], \u_rotate_mult0_u_rotate_image/w_mult_add[5]_floating , \u_rotate_mult0_u_rotate_image/w_mult_add[4]_floating , \u_rotate_mult0_u_rotate_image/w_mult_add[3]_floating , \u_rotate_mult0_u_rotate_image/w_mult_add[2]_floating , \u_rotate_mult0_u_rotate_image/w_mult_add[1]_floating , \u_rotate_mult0_u_rotate_image/w_mult_add[0]_floating }), .B ({1'bx, cos_data_multed[18], cos_data_multed[17], cos_data_multed[16], cos_data_multed[15], cos_data_multed[14], cos_data_multed[13], cos_data_multed[12], cos_data_multed[11], cos_data_multed[10], cos_data_multed[9], cos_data_multed[8], cos_data_multed[7]}), - .\u_rotate_image/N290 (N290), + .\u_rotate_image/N338 (N338), .\u_rotate_image/mult_p0[1] ({1'bx, \mult_p0[1] [22] , \mult_p0[1] [21] , \mult_p0[1] [20] , \mult_p0[1] [19] , \mult_p0[1] [18] , \mult_p0[1] [17] , \mult_p0[1] [16] , \mult_p0[1] [15] , \mult_p0[1] [14] , \mult_p0[1] [13] , \mult_p0[1] [12] , \mult_p0[1] [11] , \mult_p0[1] [10] , \mult_p0[1] [9] , \mult_p0[1] [8] , \mult_p0[1] [7] , \mult_p0[1] [6] , \mult_p0[1] [5] , \mult_p0[1] [4] , \mult_p0[1] [3] , \mult_p0[1] [2] , \mult_p0[1] [1] , \mult_p0[1] [0] }), .CLK (clk), .N139_0 (N139_0), - ._N12940 (_N12940), - ._N12941 (_N12941), ._N12942 (_N12942), ._N12943 (_N12943), ._N12944 (_N12944), @@ -288658,15 +288285,15 @@ module rotate_image ._N12961 (_N12961), ._N12962 (_N12962), ._N12963 (_N12963), - ._N12964 (_N12964)); - // ../../sources/designs/rotate/rotate_image.v:187 + ._N12964 (_N12964), + ._N12965 (_N12965), + ._N12966 (_N12966)); + // ../../sources/designs/rotate/rotate_image.v:190 rotate_mult0_1_unq8 u_rotate_mult1 ( .P ({\u_rotate_mult1_P[23]_floating , \mult_p0[1] [22] , \mult_p0[1] [21] , \mult_p0[1] [20] , \mult_p0[1] [19] , \mult_p0[1] [18] , \mult_p0[1] [17] , \mult_p0[1] [16] , \mult_p0[1] [15] , \mult_p0[1] [14] , \mult_p0[1] [13] , \mult_p0[1] [12] , \mult_p0[1] [11] , \mult_p0[1] [10] , \mult_p0[1] [9] , \mult_p0[1] [8] , \mult_p0[1] [7] , \mult_p0[1] [6] , \mult_p0[1] [5] , \mult_p0[1] [4] , \mult_p0[1] [3] , \mult_p0[1] [2] , \mult_p0[1] [1] , \mult_p0[1] [0] }), .B ({1'bx, sin_data_multed[18], sin_data_multed[17], sin_data_multed[16], sin_data_multed[15], sin_data_multed[14], sin_data_multed[13], sin_data_multed[12], sin_data_multed[11], sin_data_multed[10], sin_data_multed[9], sin_data_multed[8], sin_data_multed[7]}), - .\u_rotate_image/N301 (N301), - ._N12940 (_N12940), - ._N12941 (_N12941), + .\u_rotate_image/N349 (N349), ._N12942 (_N12942), ._N12943 (_N12943), ._N12944 (_N12944), @@ -288690,16 +288317,16 @@ module rotate_image ._N12962 (_N12962), ._N12963 (_N12963), ._N12964 (_N12964), + ._N12965 (_N12965), + ._N12966 (_N12966), .CLK (clk), - .\u_rotate_image/N302 (N302)); - // ../../sources/designs/rotate/rotate_image.v:196 + .\u_rotate_image/N350 (N350)); + // ../../sources/designs/rotate/rotate_image.v:199 rotate_mult0_1_unq10 u_rotate_mult2 ( .P ({\u_rotate_mult2_P[23]_floating , \mult_p0[2] [22] , \mult_p0[2] [21] , \mult_p0[2] [20] , \mult_p0[2] [19] , \mult_p0[2] [18] , \mult_p0[2] [17] , \mult_p0[2] [16] , \mult_p0[2] [15] , \mult_p0[2] [14] , \mult_p0[2] [13] , \mult_p0[2] [12] , \mult_p0[2] [11] , \mult_p0[2] [10] , \mult_p0[2] [9] , \mult_p0[2] [8] , \mult_p0[2] [7] , \mult_p0[2] [6] , \mult_p0[2] [5] , \mult_p0[2] [4] , \mult_p0[2] [3] , \mult_p0[2] [2] , \mult_p0[2] [1] , \mult_p0[2] [0] }), .B ({1'bx, sin_data_multed[18], sin_data_multed[17], sin_data_multed[16], sin_data_multed[15], sin_data_multed[14], sin_data_multed[13], sin_data_multed[12], sin_data_multed[11], sin_data_multed[10], sin_data_multed[9], sin_data_multed[8], sin_data_multed[7]}), - .\u_rotate_image/N290 (N290), - ._N12915 (_N12915), - ._N12916 (_N12916), + .\u_rotate_image/N338 (N338), ._N12917 (_N12917), ._N12918 (_N12918), ._N12919 (_N12919), @@ -288723,18 +288350,18 @@ module rotate_image ._N12937 (_N12937), ._N12938 (_N12938), ._N12939 (_N12939), + ._N12940 (_N12940), + ._N12941 (_N12941), .CLK (clk), .N139_0 (N139_0)); - // ../../sources/designs/rotate/rotate_image.v:205 + // ../../sources/designs/rotate/rotate_image.v:208 rotate_mult0_1_unq12 u_rotate_mult3 ( .\u_rotate_image/h_mult_add ({h_mult_add[24], h_mult_add[23], h_mult_add[22], h_mult_add[21], h_mult_add[20], h_mult_add[19], h_mult_add[18], h_mult_add[17], h_mult_add[16], h_mult_add[15], h_mult_add[14], h_mult_add[13], h_mult_add[12], h_mult_add[11], h_mult_add[10], h_mult_add[9], h_mult_add[8], h_mult_add[7], h_mult_add[6], \u_rotate_mult3_u_rotate_image/h_mult_add[5]_floating , \u_rotate_mult3_u_rotate_image/h_mult_add[4]_floating , \u_rotate_mult3_u_rotate_image/h_mult_add[3]_floating , \u_rotate_mult3_u_rotate_image/h_mult_add[2]_floating , \u_rotate_mult3_u_rotate_image/h_mult_add[1]_floating , \u_rotate_mult3_u_rotate_image/h_mult_add[0]_floating }), .B ({1'bx, cos_data_multed[18], cos_data_multed[17], cos_data_multed[16], cos_data_multed[15], cos_data_multed[14], cos_data_multed[13], cos_data_multed[12], cos_data_multed[11], cos_data_multed[10], cos_data_multed[9], cos_data_multed[8], cos_data_multed[7]}), - .\u_rotate_image/N301 (N301), + .\u_rotate_image/N349 (N349), .\u_rotate_image/mult_p0[2] ({1'bx, \mult_p0[2] [22] , \mult_p0[2] [21] , \mult_p0[2] [20] , \mult_p0[2] [19] , \mult_p0[2] [18] , \mult_p0[2] [17] , \mult_p0[2] [16] , \mult_p0[2] [15] , \mult_p0[2] [14] , \mult_p0[2] [13] , \mult_p0[2] [12] , \mult_p0[2] [11] , \mult_p0[2] [10] , \mult_p0[2] [9] , \mult_p0[2] [8] , \mult_p0[2] [7] , \mult_p0[2] [6] , \mult_p0[2] [5] , \mult_p0[2] [4] , \mult_p0[2] [3] , \mult_p0[2] [2] , \mult_p0[2] [1] , \mult_p0[2] [0] }), .CLK (clk), - ._N12915 (_N12915), - ._N12916 (_N12916), ._N12917 (_N12917), ._N12918 (_N12918), ._N12919 (_N12919), @@ -288758,28 +288385,30 @@ module rotate_image ._N12937 (_N12937), ._N12938 (_N12938), ._N12939 (_N12939), - .\u_rotate_image/N302 (N302)); - // ../../sources/designs/rotate/rotate_image.v:214 + ._N12940 (_N12940), + ._N12941 (_N12941), + .\u_rotate_image/N350 (N350)); + // ../../sources/designs/rotate/rotate_image.v:217 rotate_mult0 u_rotate_mult_zoom0 ( .P ({\u_rotate_mult_zoom0_P[19]_floating , cos_data_multed[18], cos_data_multed[17], cos_data_multed[16], cos_data_multed[15], cos_data_multed[14], cos_data_multed[13], cos_data_multed[12], cos_data_multed[11], cos_data_multed[10], cos_data_multed[9], cos_data_multed[8], cos_data_multed[7], \u_rotate_mult_zoom0_P[6]_floating , \u_rotate_mult_zoom0_P[5]_floating , \u_rotate_mult_zoom0_P[4]_floating , \u_rotate_mult_zoom0_P[3]_floating , \u_rotate_mult_zoom0_P[2]_floating , \u_rotate_mult_zoom0_P[1]_floating , \u_rotate_mult_zoom0_P[0]_floating }), .A ({douta[17], douta[16], douta[15], douta[14], douta[13], douta[12], douta[11], douta[10], douta[9]}), .B ({1'bx, rotate_amplitude[9], rotate_amplitude[8], rotate_amplitude[7], rotate_amplitude[6], rotate_amplitude[5], rotate_amplitude[4], rotate_amplitude[3], rotate_amplitude[2], rotate_amplitude[1], rotate_amplitude[0]}), .CLK (clk)); - // ../../sources/designs/rotate/rotate_image.v:110 + // ../../sources/designs/rotate/rotate_image.v:113 rotate_mult0_unq4 u_rotate_mult_zoom1 ( .P ({\u_rotate_mult_zoom1_P[19]_floating , sin_data_multed[18], sin_data_multed[17], sin_data_multed[16], sin_data_multed[15], sin_data_multed[14], sin_data_multed[13], sin_data_multed[12], sin_data_multed[11], sin_data_multed[10], sin_data_multed[9], sin_data_multed[8], sin_data_multed[7], \u_rotate_mult_zoom1_P[6]_floating , \u_rotate_mult_zoom1_P[5]_floating , \u_rotate_mult_zoom1_P[4]_floating , \u_rotate_mult_zoom1_P[3]_floating , \u_rotate_mult_zoom1_P[2]_floating , \u_rotate_mult_zoom1_P[1]_floating , \u_rotate_mult_zoom1_P[0]_floating }), .A ({douta[8], douta[7], douta[6], douta[5], douta[4], douta[3], douta[2], douta[1], douta[0]}), .B ({1'bx, rotate_amplitude[9], rotate_amplitude[8], rotate_amplitude[7], rotate_amplitude[6], rotate_amplitude[5], rotate_amplitude[4], rotate_amplitude[3], rotate_amplitude[2], rotate_amplitude[1], rotate_amplitude[0]}), .CLK (clk)); - // ../../sources/designs/rotate/rotate_image.v:119 + // ../../sources/designs/rotate/rotate_image.v:122 rotate_rom u_rotate_rom ( .rd_data (douta), .addr (rd_addr), .clk (clk)); - // ../../sources/designs/rotate/rotate_image.v:99 + // ../../sources/designs/rotate/rotate_image.v:102 store_addr u_store_addr ( .rd_data ({\u_store_addr_rd_data[3]_floating , \u_store_addr_rd_data[2]_floating , \u_store_addr_rd_data[1]_floating , dout[0]}), @@ -288791,7 +288420,7 @@ module rotate_image .rst (rst), .\u_rotate_image/N164_1 (N164_1), .wr_en (image_w_valid0[4])); - // ../../sources/designs/rotate/rotate_image.v:318 + // ../../sources/designs/rotate/rotate_image.v:321 store_image_data u_store_image_data ( .rd_data (image_data), @@ -288800,9 +288429,9 @@ module rotate_image .clk (clk), .rd_en (N170), .rst (rst), - .\u_rotate_image/N339_2 (N339_2), + .\u_rotate_image/N395_2 (N395_2), .wr_en (ddr_data_in_valid0)); - // ../../sources/designs/rotate/rotate_image.v:358 + // ../../sources/designs/rotate/rotate_image.v:361 endmodule @@ -288839,44 +288468,44 @@ module sync_vg wire [7:0] \N218_1.co ; wire [11:0] N224; wire [11:0] N226; - wire _N10003; - wire _N10011; wire _N10039; - wire _N10041; - wire _N10071; - wire _N10093; - wire _N10113; - wire _N10145; - wire _N16582; - wire _N16583; - wire _N16584; - wire _N16585; - wire _N16586; - wire _N16587; - wire _N16588; - wire _N16589; - wire _N16673; - wire _N16674; - wire _N16675; - wire _N16676; - wire _N16677; - wire _N16678; - wire _N16679; - wire _N16680; - wire _N16681; - wire _N16682; - wire _N96762; - wire _N97008; - wire _N97010; - wire _N97018; - wire _N97211; - wire _N103514; - wire _N105053; - wire _N105054; - wire _N105066; - wire _N105067; - wire _N105074; - wire _N107935; + wire _N10047; + wire _N10075; + wire _N10077; + wire _N10107; + wire _N10129; + wire _N10149; + wire _N10165; + wire _N16487; + wire _N16488; + wire _N16489; + wire _N16490; + wire _N16491; + wire _N16492; + wire _N16493; + wire _N16494; + wire _N16612; + wire _N16613; + wire _N16614; + wire _N16615; + wire _N16616; + wire _N16617; + wire _N16618; + wire _N16619; + wire _N16620; + wire _N16621; + wire _N97573; + wire _N97773; + wire _N97778; + wire _N97979; + wire _N104326; + wire _N105600; + wire _N105601; + wire _N105613; + wire _N105614; + wire _N105622; + wire _N105624; + wire _N108767; wire de_re1; wire de_re2; wire [11:0] h_count; @@ -288901,8 +288530,8 @@ module sync_vg GTP_LUT4 /* N3_mux6_4 */ #( .INIT(16'b1011111111111111)) N3_mux6_4 ( - .Z (_N10003), - .I0 (_N96762), + .Z (_N10039), + .I0 (_N97573), .I1 (h_count[4]), .I2 (h_count[5]), .I3 (h_count[6])); @@ -288911,8 +288540,8 @@ module sync_vg GTP_LUT5 /* N3_mux10 */ #( .INIT(32'b00000010111111111111111111111111)) N3_mux10 ( - .Z (_N10011), - .I0 (_N10003), + .Z (_N10047), + .I0 (_N10039), .I1 (h_count[7]), .I2 (h_count[8]), .I3 (h_count[9]), @@ -288926,7 +288555,7 @@ module sync_vg .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N23_1_1 ( - .COUT (_N16582), + .COUT (_N16487), .Z (N226[1]), .CIN (), .I0 (v_count[0]), @@ -288937,7 +288566,7 @@ module sync_vg .ID ()); // LUT = I1^I0 ; // CARRY = (1'b0) ? CIN : (I4) ; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:99 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:101 GTP_LUT5CARRY /* N23_1_2 */ #( .INIT(32'b01111000011110001000000010000000), @@ -288946,9 +288575,9 @@ module sync_vg .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N23_1_2 ( - .COUT (_N16583), + .COUT (_N16488), .Z (N226[2]), - .CIN (_N16582), + .CIN (_N16487), .I0 (v_count[0]), .I1 (v_count[1]), .I2 (v_count[2]), @@ -288957,7 +288586,7 @@ module sync_vg .ID ()); // LUT = (I0&I1&~I2)|(~I1&I2)|(~I0&I2) ; // CARRY = (I0&I1&I2) ? CIN : (I4) ; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:99 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:101 GTP_LUT5CARRY /* N23_1_3 */ #( .INIT(32'b01100110011001101100110011001100), @@ -288966,9 +288595,9 @@ module sync_vg .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N23_1_3 ( - .COUT (_N16584), + .COUT (_N16489), .Z (N226[3]), - .CIN (_N16583), + .CIN (_N16488), .I0 (), .I1 (v_count[3]), .I2 (), @@ -288977,7 +288606,7 @@ module sync_vg .ID ()); // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:99 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:101 GTP_LUT5CARRY /* N23_1_4 */ #( .INIT(32'b01100110011001101100110011001100), @@ -288986,9 +288615,9 @@ module sync_vg .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N23_1_4 ( - .COUT (_N16585), + .COUT (_N16490), .Z (N226[4]), - .CIN (_N16584), + .CIN (_N16489), .I0 (), .I1 (v_count[4]), .I2 (), @@ -288997,7 +288626,7 @@ module sync_vg .ID ()); // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:99 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:101 GTP_LUT5CARRY /* N23_1_5 */ #( .INIT(32'b01100110011001101100110011001100), @@ -289006,9 +288635,9 @@ module sync_vg .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N23_1_5 ( - .COUT (_N16586), + .COUT (_N16491), .Z (N226[5]), - .CIN (_N16585), + .CIN (_N16490), .I0 (), .I1 (v_count[5]), .I2 (), @@ -289017,7 +288646,7 @@ module sync_vg .ID ()); // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:99 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:101 GTP_LUT5CARRY /* N23_1_6 */ #( .INIT(32'b01100110011001101100110011001100), @@ -289026,9 +288655,9 @@ module sync_vg .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N23_1_6 ( - .COUT (_N16587), + .COUT (_N16492), .Z (N226[6]), - .CIN (_N16586), + .CIN (_N16491), .I0 (), .I1 (v_count[6]), .I2 (), @@ -289037,7 +288666,7 @@ module sync_vg .ID ()); // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:99 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:101 GTP_LUT5CARRY /* N23_1_7 */ #( .INIT(32'b01100110011001101100110011001100), @@ -289046,9 +288675,9 @@ module sync_vg .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N23_1_7 ( - .COUT (_N16588), + .COUT (_N16493), .Z (N226[7]), - .CIN (_N16587), + .CIN (_N16492), .I0 (), .I1 (v_count[7]), .I2 (), @@ -289057,7 +288686,7 @@ module sync_vg .ID ()); // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:99 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:101 GTP_LUT5CARRY /* N23_1_8 */ #( .INIT(32'b01100110011001101100110011001100), @@ -289066,9 +288695,9 @@ module sync_vg .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N23_1_8 ( - .COUT (_N16589), + .COUT (_N16494), .Z (N226[8]), - .CIN (_N16588), + .CIN (_N16493), .I0 (), .I1 (v_count[8]), .I2 (), @@ -289077,7 +288706,7 @@ module sync_vg .ID ()); // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:99 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:101 GTP_LUT5CARRY /* N23_1_9 */ #( .INIT(32'b01100110011001101100110011001100), @@ -289088,7 +288717,7 @@ module sync_vg N23_1_9 ( .COUT (), .Z (N226[9]), - .CIN (_N16589), + .CIN (_N16494), .I0 (), .I1 (v_count[9]), .I2 (), @@ -289097,7 +288726,7 @@ module sync_vg .ID ()); // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:99 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:101 GTP_LUT5 /* \N24[0] */ #( .INIT(32'b00101010101010101010101010101010)) @@ -289106,10 +288735,10 @@ module sync_vg .I0 (N226[1]), .I1 (v_count[7]), .I2 (v_count[9]), - .I3 (_N105053), - .I4 (_N105054)); + .I3 (_N105600), + .I4 (_N105601)); // LUT = (I0&~I4)|(I0&~I3)|(I0&~I2)|(I0&~I1) ; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:99 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:101 GTP_LUT5 /* \N24[1] */ #( .INIT(32'b00101010101010101010101010101010)) @@ -289118,10 +288747,10 @@ module sync_vg .I0 (N226[2]), .I1 (v_count[7]), .I2 (v_count[9]), - .I3 (_N105053), - .I4 (_N105054)); + .I3 (_N105600), + .I4 (_N105601)); // LUT = (I0&~I4)|(I0&~I3)|(I0&~I2)|(I0&~I1) ; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:99 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:101 GTP_LUT5 /* \N24[2] */ #( .INIT(32'b00101010101010101010101010101010)) @@ -289130,10 +288759,10 @@ module sync_vg .I0 (N226[3]), .I1 (v_count[7]), .I2 (v_count[9]), - .I3 (_N105053), - .I4 (_N105054)); + .I3 (_N105600), + .I4 (_N105601)); // LUT = (I0&~I4)|(I0&~I3)|(I0&~I2)|(I0&~I1) ; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:99 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:101 GTP_LUT5 /* \N24[3] */ #( .INIT(32'b00101010101010101010101010101010)) @@ -289142,10 +288771,10 @@ module sync_vg .I0 (N226[5]), .I1 (v_count[7]), .I2 (v_count[9]), - .I3 (_N105053), - .I4 (_N105054)); + .I3 (_N105600), + .I4 (_N105601)); // LUT = (I0&~I4)|(I0&~I3)|(I0&~I2)|(I0&~I1) ; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:99 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:101 GTP_LUT5 /* \N24[4] */ #( .INIT(32'b00101010101010101010101010101010)) @@ -289154,10 +288783,10 @@ module sync_vg .I0 (N226[6]), .I1 (v_count[7]), .I2 (v_count[9]), - .I3 (_N105053), - .I4 (_N105054)); + .I3 (_N105600), + .I4 (_N105601)); // LUT = (I0&~I4)|(I0&~I3)|(I0&~I2)|(I0&~I1) ; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:99 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:101 GTP_LUT5 /* \N24[5] */ #( .INIT(32'b00101010101010101010101010101010)) @@ -289166,10 +288795,10 @@ module sync_vg .I0 (N226[7]), .I1 (v_count[7]), .I2 (v_count[9]), - .I3 (_N105053), - .I4 (_N105054)); + .I3 (_N105600), + .I4 (_N105601)); // LUT = (I0&~I4)|(I0&~I3)|(I0&~I2)|(I0&~I1) ; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:99 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:101 GTP_LUT5 /* \N24[6] */ #( .INIT(32'b00101010101010101010101010101010)) @@ -289178,25 +288807,15 @@ module sync_vg .I0 (N226[9]), .I1 (v_count[7]), .I2 (v_count[9]), - .I3 (_N105053), - .I4 (_N105054)); + .I3 (_N105600), + .I4 (_N105601)); // LUT = (I0&~I4)|(I0&~I3)|(I0&~I2)|(I0&~I1) ; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:99 - - GTP_LUT4 /* N28_mux8_2 */ #( - .INIT(16'b0000000000000001)) - N28_mux8_2 ( - .Z (_N97018), - .I0 (h_count[8]), - .I1 (h_count[9]), - .I2 (h_count[10]), - .I3 (h_count[11])); - // LUT = ~I0&~I1&~I2&~I3 ; + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:101 - GTP_LUT5 /* N28_mux8_5 */ #( + GTP_LUT5 /* N28_mux8_4 */ #( .INIT(32'b00000000000000000000000000011111)) - N28_mux8_5 ( - .Z (_N107935), + N28_mux8_4 ( + .Z (_N108767), .I0 (h_count[3]), .I1 (h_count[4]), .I2 (h_count[5]), @@ -289204,41 +288823,54 @@ module sync_vg .I4 (h_count[7])); // LUT = (~I2&~I3&~I4)|(~I0&~I1&~I3&~I4) ; - GTP_LUT5 /* N28_mux8_6 */ #( + GTP_LUT5 /* N28_mux8_5 */ #( .INIT(32'b00000000000000010000000000000000)) - N28_mux8_6 ( + N28_mux8_5 ( .Z (N28), .I0 (h_count[8]), .I1 (h_count[9]), .I2 (h_count[10]), .I3 (h_count[11]), - .I4 (_N107935)); + .I4 (_N108767)); // LUT = ~I0&~I1&~I2&~I3&I4 ; - GTP_LUT3 /* N50_mux2_3 */ #( - .INIT(8'b00000001)) - N50_mux2_3 ( - .Z (_N105074), - .I0 (v_count[1]), - .I1 (v_count[3]), - .I2 (v_count[4])); - // LUT = ~I0&~I1&~I2 ; + GTP_LUT5 /* N50_mux2_4 */ #( + .INIT(32'b00000000000000000000000000000010)) + N50_mux2_4 ( + .Z (_N105622), + .I0 (_N97778), + .I1 (h_count[8]), + .I2 (h_count[9]), + .I3 (h_count[10]), + .I4 (h_count[11])); + // LUT = I0&~I1&~I2&~I3&~I4 ; + + GTP_LUT5 /* N50_mux2_6 */ #( + .INIT(32'b00000000000000010000000000000000)) + N50_mux2_6 ( + .Z (_N105624), + .I0 (h_count[4]), + .I1 (h_count[5]), + .I2 (h_count[6]), + .I3 (h_count[7]), + .I4 (_N105622)); + // LUT = ~I0&~I1&~I2&~I3&I4 ; GTP_LUT5 /* N50_mux2_7 */ #( - .INIT(32'b10000000000000000000000000000000)) + .INIT(32'b00000000000000100000000000000000)) N50_mux2_7 ( - .Z (_N97211), - .I0 (_N96762), - .I1 (_N97008), - .I2 (_N97010), - .I3 (_N97018), - .I4 (_N105074)); - // LUT = I0&I1&I2&I3&I4 ; + .Z (_N97979), + .I0 (_N97573), + .I1 (v_count[1]), + .I2 (v_count[3]), + .I3 (v_count[4]), + .I4 (_N105624)); + // LUT = I0&~I1&~I2&~I3&I4 ; GTP_LUT4 /* N50_mux3 */ #( .INIT(16'b0000000111111111)) N50_mux3 ( - .Z (_N10039), + .Z (_N10075), .I0 (v_count[0]), .I1 (v_count[1]), .I2 (v_count[2]), @@ -289248,7 +288880,7 @@ module sync_vg GTP_LUT5 /* N50_mux4 */ #( .INIT(32'b00000001111111111111111111111111)) N50_mux4 ( - .Z (_N10041), + .Z (_N10077), .I0 (v_count[0]), .I1 (v_count[1]), .I2 (v_count[2]), @@ -289256,10 +288888,10 @@ module sync_vg .I4 (v_count[4])); // LUT = (~I4)|(~I3)|(~I0&~I1&~I2) ; - GTP_LUT5 /* N50_mux9_7 */ #( + GTP_LUT5 /* N50_mux9_8 */ #( .INIT(32'b00000000000000000000000000000001)) - N50_mux9_7 ( - .Z (_N97008), + N50_mux9_8 ( + .Z (_N97778), .I0 (v_count[5]), .I1 (v_count[6]), .I2 (v_count[7]), @@ -289270,8 +288902,8 @@ module sync_vg GTP_LUT5 /* N53_mux7_4 */ #( .INIT(32'b00101111111111111111111111111111)) N53_mux7_4 ( - .Z (_N10071), - .I0 (_N10039), + .Z (_N10107), + .I0 (_N10075), .I1 (v_count[4]), .I2 (v_count[5]), .I3 (v_count[6]), @@ -289282,19 +288914,19 @@ module sync_vg .INIT(32'b00000000010011000101111101011111)) N54_vname ( .Z (N54), - .I0 (_N10041), - .I1 (_N10071), - .I2 (_N97008), + .I0 (_N10077), + .I1 (_N10107), + .I2 (_N97778), .I3 (v_count[8]), .I4 (v_count[9])); // defparam N54_vname.orig_name = N54; // LUT = (~I2&~I4)|(~I0&~I4)|(I1&~I2&~I3)|(~I0&I1&~I3) ; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:121 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:123 - GTP_LUT4 /* N56_mux5_2 */ #( + GTP_LUT4 /* N56_mux5_1 */ #( .INIT(16'b0000000000000001)) - N56_mux5_2 ( - .Z (_N97010), + N56_mux5_1 ( + .Z (_N97773), .I0 (h_count[4]), .I1 (h_count[5]), .I2 (h_count[6]), @@ -289304,28 +288936,18 @@ module sync_vg GTP_LUT4 /* N56_mux6 */ #( .INIT(16'b0000001011111111)) N56_mux6 ( - .Z (_N10093), - .I0 (_N97010), + .Z (_N10129), + .I0 (_N97773), .I1 (h_count[2]), .I2 (h_count[3]), .I3 (h_count[8])); // LUT = (~I3)|(I0&~I1&~I2) ; - GTP_LUT4 /* N56_mux8_1 */ #( - .INIT(16'b0000000000000001)) - N56_mux8_1 ( - .Z (_N96762), - .I0 (h_count[0]), - .I1 (h_count[1]), - .I2 (h_count[2]), - .I3 (h_count[3])); - // LUT = ~I0&~I1&~I2&~I3 ; - GTP_LUT4 /* N59_mux6 */ #( .INIT(16'b0000000000000010)) N59_mux6 ( - .Z (_N10113), - .I0 (_N97010), + .Z (_N10149), + .I0 (_N97773), .I1 (h_count[2]), .I2 (h_count[3]), .I3 (h_count[8])); @@ -289335,12 +288957,12 @@ module sync_vg .INIT(32'b00000000100011000000000011000100)) N61_7 ( .Z (N61), - .I0 (_N10113), + .I0 (_N10149), .I1 (N54), .I2 (h_count[10]), .I3 (h_count[11]), .I4 (h_count[9]), - .ID (_N10093)); + .ID (_N10129)); // LUT = (I1&I2&~I3&~I4)|(I1&~I2&~I3&I4)|(~ID&I1&~I2&~I3)|(I0&I1&I2&~I3) ; GTP_LUT1 /* N115 */ #( @@ -289362,7 +288984,7 @@ module sync_vg GTP_LUT5 /* N138_mux4 */ #( .INIT(32'b00000000000000000000000000000001)) N138_mux4 ( - .Z (_N10145), + .Z (_N10165), .I0 (h_count[3]), .I1 (h_count[4]), .I2 (h_count[5]), @@ -289370,11 +288992,21 @@ module sync_vg .I4 (h_count[7])); // LUT = ~I0&~I1&~I2&~I3&~I4 ; + GTP_LUT4 /* N138_mux7_1 */ #( + .INIT(16'b0000000000000001)) + N138_mux7_1 ( + .Z (_N97573), + .I0 (h_count[0]), + .I1 (h_count[1]), + .I2 (h_count[2]), + .I3 (h_count[3])); + // LUT = ~I0&~I1&~I2&~I3 ; + GTP_LUT5 /* N145_5 */ #( .INIT(32'b00000000000000000010111111110100)) N145_5 ( .Z (N145), - .I0 (_N10145), + .I0 (_N10165), .I1 (h_count[8]), .I2 (h_count[9]), .I3 (h_count[10]), @@ -289399,7 +289031,7 @@ module sync_vg .ID ()); // LUT = ~I1^I0 ; // CARRY = (1'b0) ? CIN : (I4) ; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:196 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:198 GTP_LUT5CARRY /* \N169_2.fsub_2 */ #( .INIT(32'b11100001111000011111111011111110), @@ -289419,7 +289051,7 @@ module sync_vg .ID ()); // LUT = (~I0&~I1&~I2)|(I1&I2)|(I0&I2) ; // CARRY = ((I2)|(I1)|(I0)) ? CIN : (I4) ; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:196 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:198 GTP_LUT5CARRY /* \N169_2.fsub_3 */ #( .INIT(32'b01100110011001101100110011001100), @@ -289439,7 +289071,7 @@ module sync_vg .ID ()); // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:196 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:198 GTP_LUT5CARRY /* \N169_2.fsub_4 */ #( .INIT(32'b01100110011001101100110011001100), @@ -289459,7 +289091,7 @@ module sync_vg .ID ()); // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:196 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:198 GTP_LUT5CARRY /* \N169_2.fsub_5 */ #( .INIT(32'b10011001100110010011001100110011), @@ -289479,7 +289111,7 @@ module sync_vg .ID ()); // LUT = ~I1^CIN ; // CARRY = (~I1) ? CIN : (I4) ; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:196 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:198 GTP_LUT5CARRY /* \N169_2.fsub_6 */ #( .INIT(32'b10011001100110010011001100110011), @@ -289499,7 +289131,7 @@ module sync_vg .ID ()); // LUT = ~I1^CIN ; // CARRY = (~I1) ? CIN : (I4) ; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:196 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:198 GTP_LUT5CARRY /* \N169_2.fsub_7 */ #( .INIT(32'b10011001100110010011001100110011), @@ -289519,7 +289151,7 @@ module sync_vg .ID ()); // LUT = ~I1^CIN ; // CARRY = (~I1) ? CIN : (I4) ; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:196 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:198 GTP_LUT5CARRY /* \N169_2.fsub_8 */ #( .INIT(32'b10011001100110010011001100110011), @@ -289539,7 +289171,7 @@ module sync_vg .ID ()); // LUT = ~I1^CIN ; // CARRY = (~I1) ? CIN : (I4) ; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:196 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:198 GTP_LUT5CARRY /* \N169_2.fsub_9 */ #( .INIT(32'b10011001100110010011001100110011), @@ -289559,7 +289191,7 @@ module sync_vg .ID ()); // LUT = ~I1^CIN ; // CARRY = (~I1) ? CIN : (I4) ; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:196 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:198 GTP_LUT5CARRY /* \N169_2.fsub_10 */ #( .INIT(32'b01010101010101011111111111111111), @@ -289579,12 +289211,12 @@ module sync_vg .ID ()); // LUT = ~CIN ; // CARRY = (1'b1) ? CIN : (I4) ; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:196 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:198 GTP_LUT4 /* N178_6 */ #( .INIT(16'b0000100000000000)) N178_6 ( - .Z (_N105066), + .Z (_N105613), .I0 (h_count[0]), .I1 (h_count[6]), .I2 (h_count[7]), @@ -289594,7 +289226,7 @@ module sync_vg GTP_LUT5 /* N178_7 */ #( .INIT(32'b00000001000000000000000000000000)) N178_7 ( - .Z (_N105067), + .Z (_N105614), .I0 (h_count[1]), .I1 (h_count[2]), .I2 (h_count[3]), @@ -289609,14 +289241,14 @@ module sync_vg .I0 (h_count[5]), .I1 (h_count[8]), .I2 (h_count[11]), - .I3 (_N105066), - .I4 (_N105067)); + .I3 (_N105613), + .I4 (_N105614)); // LUT = I0&~I1&~I2&I3&I4 ; GTP_LUT4 /* N184_13 */ #( .INIT(16'b0000000000100000)) N184_13 ( - .Z (_N105053), + .Z (_N105600), .I0 (v_count[0]), .I1 (v_count[1]), .I2 (v_count[2]), @@ -289626,7 +289258,7 @@ module sync_vg GTP_LUT4 /* N184_14 */ #( .INIT(16'b0000000010000000)) N184_14 ( - .Z (_N105054), + .Z (_N105601), .I0 (v_count[3]), .I1 (v_count[5]), .I2 (v_count[6]), @@ -289667,7 +289299,7 @@ module sync_vg .ID ()); // LUT = ~I1^I0 ; // CARRY = (1'b0) ? CIN : (I4) ; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:188 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:190 GTP_LUT5CARRY /* \N218_1.fsub_2 */ #( .INIT(32'b11100001111000011111111011111110), @@ -289687,7 +289319,7 @@ module sync_vg .ID ()); // LUT = (~I0&~I1&~I2)|(I1&I2)|(I0&I2) ; // CARRY = ((I2)|(I1)|(I0)) ? CIN : (I4) ; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:188 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:190 GTP_LUT5CARRY /* \N218_1.fsub_3 */ #( .INIT(32'b10011001100110010011001100110011), @@ -289707,7 +289339,7 @@ module sync_vg .ID ()); // LUT = ~I1^CIN ; // CARRY = (~I1) ? CIN : (I4) ; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:188 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:190 GTP_LUT5CARRY /* \N218_1.fsub_4 */ #( .INIT(32'b10011001100110010011001100110011), @@ -289727,7 +289359,7 @@ module sync_vg .ID ()); // LUT = ~I1^CIN ; // CARRY = (~I1) ? CIN : (I4) ; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:188 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:190 GTP_LUT5CARRY /* \N218_1.fsub_5 */ #( .INIT(32'b01100110011001101100110011001100), @@ -289747,7 +289379,7 @@ module sync_vg .ID ()); // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:188 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:190 GTP_LUT5CARRY /* \N218_1.fsub_6 */ #( .INIT(32'b10011001100110010011001100110011), @@ -289767,7 +289399,7 @@ module sync_vg .ID ()); // LUT = ~I1^CIN ; // CARRY = (~I1) ? CIN : (I4) ; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:188 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:190 GTP_LUT5CARRY /* \N218_1.fsub_7 */ #( .INIT(32'b10011001100110010011001100110011), @@ -289787,7 +289419,7 @@ module sync_vg .ID ()); // LUT = ~I1^CIN ; // CARRY = (~I1) ? CIN : (I4) ; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:188 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:190 GTP_LUT5CARRY /* N224_1_1 */ #( .INIT(32'b01100110011001100000000000000000), @@ -289796,7 +289428,7 @@ module sync_vg .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N224_1_1 ( - .COUT (_N16673), + .COUT (_N16612), .Z (N224[1]), .CIN (), .I0 (h_count[0]), @@ -289807,7 +289439,7 @@ module sync_vg .ID ()); // LUT = I1^I0 ; // CARRY = (1'b0) ? CIN : (I4) ; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:89 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:91 GTP_LUT5CARRY /* N224_1_2 */ #( .INIT(32'b01111000011110001000000010000000), @@ -289816,9 +289448,9 @@ module sync_vg .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N224_1_2 ( - .COUT (_N16674), + .COUT (_N16613), .Z (N224[2]), - .CIN (_N16673), + .CIN (_N16612), .I0 (h_count[0]), .I1 (h_count[1]), .I2 (h_count[2]), @@ -289827,7 +289459,7 @@ module sync_vg .ID ()); // LUT = (I0&I1&~I2)|(~I1&I2)|(~I0&I2) ; // CARRY = (I0&I1&I2) ? CIN : (I4) ; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:89 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:91 GTP_LUT5CARRY /* N224_1_3 */ #( .INIT(32'b01100110011001101100110011001100), @@ -289836,9 +289468,9 @@ module sync_vg .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N224_1_3 ( - .COUT (_N16675), + .COUT (_N16614), .Z (N224[3]), - .CIN (_N16674), + .CIN (_N16613), .I0 (), .I1 (h_count[3]), .I2 (), @@ -289847,7 +289479,7 @@ module sync_vg .ID ()); // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:89 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:91 GTP_LUT5CARRY /* N224_1_4 */ #( .INIT(32'b01100110011001101100110011001100), @@ -289856,9 +289488,9 @@ module sync_vg .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N224_1_4 ( - .COUT (_N16676), + .COUT (_N16615), .Z (N224[4]), - .CIN (_N16675), + .CIN (_N16614), .I0 (), .I1 (h_count[4]), .I2 (), @@ -289867,7 +289499,7 @@ module sync_vg .ID ()); // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:89 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:91 GTP_LUT5CARRY /* N224_1_5 */ #( .INIT(32'b01100110011001101100110011001100), @@ -289876,9 +289508,9 @@ module sync_vg .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N224_1_5 ( - .COUT (_N16677), + .COUT (_N16616), .Z (N224[5]), - .CIN (_N16676), + .CIN (_N16615), .I0 (), .I1 (h_count[5]), .I2 (), @@ -289887,7 +289519,7 @@ module sync_vg .ID ()); // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:89 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:91 GTP_LUT5CARRY /* N224_1_6 */ #( .INIT(32'b01100110011001101100110011001100), @@ -289896,9 +289528,9 @@ module sync_vg .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N224_1_6 ( - .COUT (_N16678), + .COUT (_N16617), .Z (N224[6]), - .CIN (_N16677), + .CIN (_N16616), .I0 (), .I1 (h_count[6]), .I2 (), @@ -289907,7 +289539,7 @@ module sync_vg .ID ()); // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:89 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:91 GTP_LUT5CARRY /* N224_1_7 */ #( .INIT(32'b01100110011001101100110011001100), @@ -289916,9 +289548,9 @@ module sync_vg .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N224_1_7 ( - .COUT (_N16679), + .COUT (_N16618), .Z (N224[7]), - .CIN (_N16678), + .CIN (_N16617), .I0 (), .I1 (h_count[7]), .I2 (), @@ -289927,7 +289559,7 @@ module sync_vg .ID ()); // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:89 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:91 GTP_LUT5CARRY /* N224_1_8 */ #( .INIT(32'b01100110011001101100110011001100), @@ -289936,9 +289568,9 @@ module sync_vg .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N224_1_8 ( - .COUT (_N16680), + .COUT (_N16619), .Z (N224[8]), - .CIN (_N16679), + .CIN (_N16618), .I0 (), .I1 (h_count[8]), .I2 (), @@ -289947,7 +289579,7 @@ module sync_vg .ID ()); // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:89 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:91 GTP_LUT5CARRY /* N224_1_9 */ #( .INIT(32'b01100110011001101100110011001100), @@ -289956,9 +289588,9 @@ module sync_vg .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N224_1_9 ( - .COUT (_N16681), + .COUT (_N16620), .Z (N224[9]), - .CIN (_N16680), + .CIN (_N16619), .I0 (), .I1 (h_count[9]), .I2 (), @@ -289967,7 +289599,7 @@ module sync_vg .ID ()); // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:89 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:91 GTP_LUT5CARRY /* N224_1_10 */ #( .INIT(32'b01100110011001101100110011001100), @@ -289976,9 +289608,9 @@ module sync_vg .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N224_1_10 ( - .COUT (_N16682), + .COUT (_N16621), .Z (N224[10]), - .CIN (_N16681), + .CIN (_N16620), .I0 (), .I1 (h_count[10]), .I2 (), @@ -289987,7 +289619,7 @@ module sync_vg .ID ()); // LUT = I1^CIN ; // CARRY = (I1) ? CIN : (I4) ; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:89 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:91 GTP_LUT5CARRY /* N224_1_11 */ #( .INIT(32'b10101010101010100000000000000000), @@ -289998,7 +289630,7 @@ module sync_vg N224_1_11 ( .COUT (), .Z (N224[11]), - .CIN (_N16682), + .CIN (_N16621), .I0 (), .I1 (), .I2 (), @@ -290007,7 +289639,7 @@ module sync_vg .ID ()); // LUT = CIN ; // CARRY = (1'b0) ? CIN : (I4) ; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:89 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:91 GTP_DFF_R /* de_re0 */ #( .GRS_EN("TRUE"), @@ -290018,7 +289650,7 @@ module sync_vg .D (N61), .R (rst)); // defparam de_re0_vname.orig_name = de_re0; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:118 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:120 GTP_DFF_R /* de_re1 */ #( .GRS_EN("TRUE"), @@ -290029,7 +289661,7 @@ module sync_vg .D (de_re0), .R (rst)); // defparam de_re1_vname.orig_name = de_re1; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:161 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:163 GTP_DFF_R /* de_re2 */ #( .GRS_EN("TRUE"), @@ -290040,7 +289672,7 @@ module sync_vg .D (de_re1), .R (rst)); // defparam de_re2_vname.orig_name = de_re2; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:161 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:163 GTP_DFF_R /* de_re3 */ #( .GRS_EN("TRUE"), @@ -290050,7 +289682,7 @@ module sync_vg .CLK (clk), .D (de_re2), .R (rst)); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:161 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:163 GTP_DFF_R /* \h_count[0] */ #( .GRS_EN("TRUE"), @@ -290060,7 +289692,7 @@ module sync_vg .CLK (clk), .D (N193), .R (\h_count[11:0]_or )); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:86 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:88 GTP_DFF_R /* \h_count[1] */ #( .GRS_EN("TRUE"), @@ -290070,7 +289702,7 @@ module sync_vg .CLK (clk), .D (N224[1]), .R (\h_count[11:0]_or )); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:86 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:88 GTP_DFF_R /* \h_count[2] */ #( .GRS_EN("TRUE"), @@ -290080,7 +289712,7 @@ module sync_vg .CLK (clk), .D (N224[2]), .R (\h_count[11:0]_or )); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:86 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:88 GTP_DFF_R /* \h_count[3] */ #( .GRS_EN("TRUE"), @@ -290090,7 +289722,7 @@ module sync_vg .CLK (clk), .D (N224[3]), .R (\h_count[11:0]_or )); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:86 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:88 GTP_DFF_R /* \h_count[4] */ #( .GRS_EN("TRUE"), @@ -290100,7 +289732,7 @@ module sync_vg .CLK (clk), .D (N224[4]), .R (\h_count[11:0]_or )); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:86 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:88 GTP_DFF_R /* \h_count[5] */ #( .GRS_EN("TRUE"), @@ -290110,7 +289742,7 @@ module sync_vg .CLK (clk), .D (N224[5]), .R (\h_count[11:0]_or )); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:86 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:88 GTP_DFF_R /* \h_count[6] */ #( .GRS_EN("TRUE"), @@ -290120,7 +289752,7 @@ module sync_vg .CLK (clk), .D (N224[6]), .R (\h_count[11:0]_or )); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:86 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:88 GTP_DFF_R /* \h_count[7] */ #( .GRS_EN("TRUE"), @@ -290130,7 +289762,7 @@ module sync_vg .CLK (clk), .D (N224[7]), .R (\h_count[11:0]_or )); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:86 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:88 GTP_DFF_R /* \h_count[8] */ #( .GRS_EN("TRUE"), @@ -290140,7 +289772,7 @@ module sync_vg .CLK (clk), .D (N224[8]), .R (\h_count[11:0]_or )); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:86 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:88 GTP_DFF_R /* \h_count[9] */ #( .GRS_EN("TRUE"), @@ -290150,7 +289782,7 @@ module sync_vg .CLK (clk), .D (N224[9]), .R (\h_count[11:0]_or )); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:86 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:88 GTP_DFF_R /* \h_count[10] */ #( .GRS_EN("TRUE"), @@ -290160,14 +289792,14 @@ module sync_vg .CLK (clk), .D (N224[10]), .R (\h_count[11:0]_or )); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:86 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:88 GTP_LUT3 /* \h_count[11:0]_or */ #( .INIT(8'b11111011)) \h_count[11:0]_or_vname ( .Z (\h_count[11:0]_or ), .I0 (rst), - .I1 (_N10011), + .I1 (_N10047), .I2 (h_count[11])); // defparam \h_count[11:0]_or_vname .orig_name = \h_count[11:0]_or ; // LUT = (~I1)|(I0)|(I2) ; @@ -290180,7 +289812,7 @@ module sync_vg .CLK (clk), .D (N224[11]), .R (\h_count[11:0]_or )); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:86 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:88 GTP_DFF_S /* \hdmi_image_data0[0] */ #( .GRS_EN("TRUE"), @@ -290190,7 +289822,7 @@ module sync_vg .CLK (clk), .D (ddr_image_data[0]), .S (pixel_show_en1)); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:143 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:145 GTP_DFF_S /* \hdmi_image_data0[1] */ #( .GRS_EN("TRUE"), @@ -290200,7 +289832,7 @@ module sync_vg .CLK (clk), .D (ddr_image_data[1]), .S (pixel_show_en1)); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:143 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:145 GTP_DFF_S /* \hdmi_image_data0[2] */ #( .GRS_EN("TRUE"), @@ -290210,7 +289842,7 @@ module sync_vg .CLK (clk), .D (ddr_image_data[2]), .S (pixel_show_en1)); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:143 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:145 GTP_DFF_S /* \hdmi_image_data0[3] */ #( .GRS_EN("TRUE"), @@ -290220,7 +289852,7 @@ module sync_vg .CLK (clk), .D (ddr_image_data[3]), .S (pixel_show_en1)); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:143 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:145 GTP_DFF_S /* \hdmi_image_data0[4] */ #( .GRS_EN("TRUE"), @@ -290230,7 +289862,7 @@ module sync_vg .CLK (clk), .D (ddr_image_data[4]), .S (pixel_show_en1)); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:143 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:145 GTP_DFF_S /* \hdmi_image_data0[5] */ #( .GRS_EN("TRUE"), @@ -290240,7 +289872,7 @@ module sync_vg .CLK (clk), .D (ddr_image_data[5]), .S (pixel_show_en1)); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:143 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:145 GTP_DFF_S /* \hdmi_image_data0[6] */ #( .GRS_EN("TRUE"), @@ -290250,7 +289882,7 @@ module sync_vg .CLK (clk), .D (ddr_image_data[6]), .S (pixel_show_en1)); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:143 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:145 GTP_DFF_S /* \hdmi_image_data0[7] */ #( .GRS_EN("TRUE"), @@ -290260,7 +289892,7 @@ module sync_vg .CLK (clk), .D (ddr_image_data[7]), .S (pixel_show_en1)); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:143 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:145 GTP_DFF_S /* \hdmi_image_data0[8] */ #( .GRS_EN("TRUE"), @@ -290270,7 +289902,7 @@ module sync_vg .CLK (clk), .D (ddr_image_data[8]), .S (pixel_show_en1)); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:143 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:145 GTP_DFF_S /* \hdmi_image_data0[9] */ #( .GRS_EN("TRUE"), @@ -290280,7 +289912,7 @@ module sync_vg .CLK (clk), .D (ddr_image_data[9]), .S (pixel_show_en1)); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:143 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:145 GTP_DFF_S /* \hdmi_image_data0[10] */ #( .GRS_EN("TRUE"), @@ -290290,7 +289922,7 @@ module sync_vg .CLK (clk), .D (ddr_image_data[10]), .S (pixel_show_en1)); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:143 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:145 GTP_DFF_S /* \hdmi_image_data0[11] */ #( .GRS_EN("TRUE"), @@ -290300,7 +289932,7 @@ module sync_vg .CLK (clk), .D (ddr_image_data[11]), .S (pixel_show_en1)); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:143 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:145 GTP_DFF_S /* \hdmi_image_data0[12] */ #( .GRS_EN("TRUE"), @@ -290310,7 +289942,7 @@ module sync_vg .CLK (clk), .D (ddr_image_data[12]), .S (pixel_show_en1)); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:143 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:145 GTP_DFF_S /* \hdmi_image_data0[13] */ #( .GRS_EN("TRUE"), @@ -290320,7 +289952,7 @@ module sync_vg .CLK (clk), .D (ddr_image_data[13]), .S (pixel_show_en1)); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:143 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:145 GTP_DFF_S /* \hdmi_image_data0[14] */ #( .GRS_EN("TRUE"), @@ -290330,7 +289962,7 @@ module sync_vg .CLK (clk), .D (ddr_image_data[14]), .S (pixel_show_en1)); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:143 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:145 GTP_DFF_S /* \hdmi_image_data0[15] */ #( .GRS_EN("TRUE"), @@ -290340,7 +289972,7 @@ module sync_vg .CLK (clk), .D (ddr_image_data[15]), .S (pixel_show_en1)); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:143 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:145 GTP_DFF /* \hdmi_image_data1[0] */ #( .GRS_EN("TRUE"), @@ -290349,7 +289981,7 @@ module sync_vg .Q (hdmi_image_data[0]), .CLK (clk), .D (hdmi_image_data0[0])); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:161 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:163 GTP_DFF /* \hdmi_image_data1[1] */ #( .GRS_EN("TRUE"), @@ -290358,7 +289990,7 @@ module sync_vg .Q (hdmi_image_data[1]), .CLK (clk), .D (hdmi_image_data0[1])); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:161 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:163 GTP_DFF /* \hdmi_image_data1[2] */ #( .GRS_EN("TRUE"), @@ -290367,7 +289999,7 @@ module sync_vg .Q (hdmi_image_data[2]), .CLK (clk), .D (hdmi_image_data0[2])); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:161 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:163 GTP_DFF /* \hdmi_image_data1[3] */ #( .GRS_EN("TRUE"), @@ -290376,7 +290008,7 @@ module sync_vg .Q (hdmi_image_data[3]), .CLK (clk), .D (hdmi_image_data0[3])); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:161 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:163 GTP_DFF /* \hdmi_image_data1[4] */ #( .GRS_EN("TRUE"), @@ -290385,7 +290017,7 @@ module sync_vg .Q (hdmi_image_data[4]), .CLK (clk), .D (hdmi_image_data0[4])); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:161 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:163 GTP_DFF /* \hdmi_image_data1[5] */ #( .GRS_EN("TRUE"), @@ -290394,7 +290026,7 @@ module sync_vg .Q (hdmi_image_data[5]), .CLK (clk), .D (hdmi_image_data0[5])); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:161 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:163 GTP_DFF /* \hdmi_image_data1[6] */ #( .GRS_EN("TRUE"), @@ -290403,7 +290035,7 @@ module sync_vg .Q (hdmi_image_data[6]), .CLK (clk), .D (hdmi_image_data0[6])); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:161 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:163 GTP_DFF /* \hdmi_image_data1[7] */ #( .GRS_EN("TRUE"), @@ -290412,7 +290044,7 @@ module sync_vg .Q (hdmi_image_data[7]), .CLK (clk), .D (hdmi_image_data0[7])); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:161 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:163 GTP_DFF /* \hdmi_image_data1[8] */ #( .GRS_EN("TRUE"), @@ -290421,7 +290053,7 @@ module sync_vg .Q (hdmi_image_data[8]), .CLK (clk), .D (hdmi_image_data0[8])); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:161 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:163 GTP_DFF /* \hdmi_image_data1[9] */ #( .GRS_EN("TRUE"), @@ -290430,7 +290062,7 @@ module sync_vg .Q (hdmi_image_data[9]), .CLK (clk), .D (hdmi_image_data0[9])); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:161 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:163 GTP_DFF /* \hdmi_image_data1[10] */ #( .GRS_EN("TRUE"), @@ -290439,7 +290071,7 @@ module sync_vg .Q (hdmi_image_data[10]), .CLK (clk), .D (hdmi_image_data0[10])); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:161 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:163 GTP_DFF /* \hdmi_image_data1[11] */ #( .GRS_EN("TRUE"), @@ -290448,7 +290080,7 @@ module sync_vg .Q (hdmi_image_data[11]), .CLK (clk), .D (hdmi_image_data0[11])); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:161 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:163 GTP_DFF /* \hdmi_image_data1[12] */ #( .GRS_EN("TRUE"), @@ -290457,7 +290089,7 @@ module sync_vg .Q (hdmi_image_data[12]), .CLK (clk), .D (hdmi_image_data0[12])); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:161 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:163 GTP_DFF /* \hdmi_image_data1[13] */ #( .GRS_EN("TRUE"), @@ -290466,7 +290098,7 @@ module sync_vg .Q (hdmi_image_data[13]), .CLK (clk), .D (hdmi_image_data0[13])); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:161 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:163 GTP_DFF /* \hdmi_image_data1[14] */ #( .GRS_EN("TRUE"), @@ -290475,7 +290107,7 @@ module sync_vg .Q (hdmi_image_data[14]), .CLK (clk), .D (hdmi_image_data0[14])); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:161 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:163 GTP_DFF /* \hdmi_image_data1[15] */ #( .GRS_EN("TRUE"), @@ -290484,7 +290116,7 @@ module sync_vg .Q (hdmi_image_data[15]), .CLK (clk), .D (hdmi_image_data0[15])); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:161 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:163 GTP_DFF_R /* hs_out0 */ #( .GRS_EN("TRUE"), @@ -290495,7 +290127,7 @@ module sync_vg .D (N28), .R (rst)); // defparam hs_out0_vname.orig_name = hs_out0; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:103 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:105 GTP_DFF_R /* hs_out1 */ #( .GRS_EN("TRUE"), @@ -290506,7 +290138,7 @@ module sync_vg .D (hs_out0), .R (rst)); // defparam hs_out1_vname.orig_name = hs_out1; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:161 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:163 GTP_DFF_R /* hs_out2 */ #( .GRS_EN("TRUE"), @@ -290517,7 +290149,7 @@ module sync_vg .D (hs_out1), .R (rst)); // defparam hs_out2_vname.orig_name = hs_out2; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:161 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:163 GTP_DFF_R /* hs_out3 */ #( .GRS_EN("TRUE"), @@ -290527,7 +290159,7 @@ module sync_vg .CLK (clk), .D (hs_out2), .R (rst)); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:161 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:163 GTP_DFF /* pixel_show_en0 */ #( .GRS_EN("TRUE"), @@ -290537,7 +290169,7 @@ module sync_vg .CLK (clk), .D (N61)); // defparam pixel_show_en0_vname.orig_name = pixel_show_en0; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:131 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:133 GTP_DFF /* pixel_show_en1 */ #( .GRS_EN("TRUE"), @@ -290547,7 +290179,7 @@ module sync_vg .CLK (clk), .D (N115)); // defparam pixel_show_en1_vname.orig_name = pixel_show_en1; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:131 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:133 GTP_DFF_E /* \pos_x[0] */ #( .GRS_EN("TRUE"), @@ -290557,7 +290189,7 @@ module sync_vg .CE (N145), .CLK (clk), .D (h_count[0])); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:186 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:188 GTP_DFF_E /* \pos_x[1] */ #( .GRS_EN("TRUE"), @@ -290567,7 +290199,7 @@ module sync_vg .CE (N145), .CLK (clk), .D (h_count[1])); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:186 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:188 GTP_DFF_E /* \pos_x[2] */ #( .GRS_EN("TRUE"), @@ -290577,7 +290209,7 @@ module sync_vg .CE (N145), .CLK (clk), .D (h_count[2])); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:186 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:188 GTP_DFF_E /* \pos_x[3] */ #( .GRS_EN("TRUE"), @@ -290587,7 +290219,7 @@ module sync_vg .CE (N145), .CLK (clk), .D (N174)); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:186 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:188 GTP_DFF_E /* \pos_x[4] */ #( .GRS_EN("TRUE"), @@ -290597,7 +290229,7 @@ module sync_vg .CE (N145), .CLK (clk), .D (N218[4])); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:186 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:188 GTP_DFF_E /* \pos_x[5] */ #( .GRS_EN("TRUE"), @@ -290607,7 +290239,7 @@ module sync_vg .CE (N145), .CLK (clk), .D (N218[5])); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:186 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:188 GTP_DFF_E /* \pos_x[6] */ #( .GRS_EN("TRUE"), @@ -290617,7 +290249,7 @@ module sync_vg .CE (N145), .CLK (clk), .D (N218[6])); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:186 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:188 GTP_DFF_E /* \pos_x[7] */ #( .GRS_EN("TRUE"), @@ -290627,7 +290259,7 @@ module sync_vg .CE (N145), .CLK (clk), .D (N218[7])); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:186 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:188 GTP_DFF_E /* \pos_x[8] */ #( .GRS_EN("TRUE"), @@ -290637,7 +290269,7 @@ module sync_vg .CE (N145), .CLK (clk), .D (N218[8])); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:186 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:188 GTP_DFF_E /* \pos_x[9] */ #( .GRS_EN("TRUE"), @@ -290647,7 +290279,7 @@ module sync_vg .CE (N145), .CLK (clk), .D (N218[9])); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:186 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:188 GTP_DFF_E /* \pos_x[10] */ #( .GRS_EN("TRUE"), @@ -290657,7 +290289,7 @@ module sync_vg .CE (N145), .CLK (clk), .D (N218[10])); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:186 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:188 GTP_DFF_E /* \pos_y[0] */ #( .GRS_EN("TRUE"), @@ -290667,7 +290299,7 @@ module sync_vg .CE (N54), .CLK (clk), .D (N185)); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:194 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:196 GTP_DFF_E /* \pos_y[1] */ #( .GRS_EN("TRUE"), @@ -290677,7 +290309,7 @@ module sync_vg .CE (N54), .CLK (clk), .D (N169[1])); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:194 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:196 GTP_DFF_E /* \pos_y[2] */ #( .GRS_EN("TRUE"), @@ -290687,7 +290319,7 @@ module sync_vg .CE (N54), .CLK (clk), .D (N169[2])); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:194 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:196 GTP_DFF_E /* \pos_y[3] */ #( .GRS_EN("TRUE"), @@ -290697,7 +290329,7 @@ module sync_vg .CE (N54), .CLK (clk), .D (N169[3])); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:194 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:196 GTP_DFF_E /* \pos_y[4] */ #( .GRS_EN("TRUE"), @@ -290707,7 +290339,7 @@ module sync_vg .CE (N54), .CLK (clk), .D (N169[4])); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:194 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:196 GTP_DFF_E /* \pos_y[5] */ #( .GRS_EN("TRUE"), @@ -290717,7 +290349,7 @@ module sync_vg .CE (N54), .CLK (clk), .D (N169[5])); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:194 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:196 GTP_DFF_E /* \pos_y[6] */ #( .GRS_EN("TRUE"), @@ -290727,7 +290359,7 @@ module sync_vg .CE (N54), .CLK (clk), .D (N169[6])); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:194 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:196 GTP_DFF_E /* \pos_y[7] */ #( .GRS_EN("TRUE"), @@ -290737,7 +290369,7 @@ module sync_vg .CE (N54), .CLK (clk), .D (N169[7])); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:194 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:196 GTP_DFF_E /* \pos_y[8] */ #( .GRS_EN("TRUE"), @@ -290747,7 +290379,7 @@ module sync_vg .CE (N54), .CLK (clk), .D (N169[8])); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:194 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:196 GTP_DFF_E /* \pos_y[9] */ #( .GRS_EN("TRUE"), @@ -290757,7 +290389,7 @@ module sync_vg .CE (N54), .CLK (clk), .D (N169[9])); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:194 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:196 GTP_DFF_E /* \pos_y[10] */ #( .GRS_EN("TRUE"), @@ -290767,7 +290399,7 @@ module sync_vg .CE (N54), .CLK (clk), .D (N169[10])); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:194 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:196 GTP_DFF_RE /* \v_count[0] */ #( .GRS_EN("TRUE"), @@ -290778,7 +290410,7 @@ module sync_vg .CLK (clk), .D (N185), .R (rst)); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:95 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:97 GTP_DFF_RE /* \v_count[1] */ #( .GRS_EN("TRUE"), @@ -290789,7 +290421,7 @@ module sync_vg .CLK (clk), .D (N24[1]), .R (rst)); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:95 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:97 GTP_DFF_RE /* \v_count[2] */ #( .GRS_EN("TRUE"), @@ -290800,7 +290432,7 @@ module sync_vg .CLK (clk), .D (N24[2]), .R (rst)); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:95 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:97 GTP_DFF_RE /* \v_count[3] */ #( .GRS_EN("TRUE"), @@ -290811,7 +290443,7 @@ module sync_vg .CLK (clk), .D (N24[3]), .R (rst)); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:95 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:97 GTP_DFF_RE /* \v_count[4] */ #( .GRS_EN("TRUE"), @@ -290822,7 +290454,7 @@ module sync_vg .CLK (clk), .D (N226[4]), .R (rst)); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:95 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:97 GTP_DFF_RE /* \v_count[5] */ #( .GRS_EN("TRUE"), @@ -290833,7 +290465,7 @@ module sync_vg .CLK (clk), .D (N24[5]), .R (rst)); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:95 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:97 GTP_DFF_RE /* \v_count[6] */ #( .GRS_EN("TRUE"), @@ -290844,7 +290476,7 @@ module sync_vg .CLK (clk), .D (N24[6]), .R (rst)); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:95 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:97 GTP_DFF_RE /* \v_count[7] */ #( .GRS_EN("TRUE"), @@ -290855,7 +290487,7 @@ module sync_vg .CLK (clk), .D (N24[7]), .R (rst)); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:95 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:97 GTP_DFF_RE /* \v_count[8] */ #( .GRS_EN("TRUE"), @@ -290866,7 +290498,7 @@ module sync_vg .CLK (clk), .D (N226[8]), .R (rst)); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:95 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:97 GTP_DFF_RE /* \v_count[9] */ #( .GRS_EN("TRUE"), @@ -290877,7 +290509,7 @@ module sync_vg .CLK (clk), .D (N24[9]), .R (rst)); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:95 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:97 GTP_DFF /* vs_out0 */ #( .GRS_EN("TRUE"), @@ -290885,16 +290517,16 @@ module sync_vg vs_out0_vname ( .Q (vs_out0), .CLK (clk), - .D (_N103514)); + .D (_N104326)); // defparam vs_out0_vname.orig_name = vs_out0; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:108 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:110 GTP_LUT5 /* vs_out0_rs_mux */ #( .INIT(32'b00010000010100000101000001010100)) vs_out0_rs_mux ( - .Z (_N103514), + .Z (_N104326), .I0 (rst), - .I1 (_N97211), + .I1 (_N97979), .I2 (vs_out0), .I3 (v_count[0]), .I4 (v_count[2])); @@ -290909,7 +290541,7 @@ module sync_vg .D (vs_out0), .R (rst)); // defparam vs_out1_vname.orig_name = vs_out1; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:161 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:163 GTP_DFF_R /* vs_out2 */ #( .GRS_EN("TRUE"), @@ -290920,7 +290552,7 @@ module sync_vg .D (vs_out1), .R (rst)); // defparam vs_out2_vname.orig_name = vs_out2; - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:161 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:163 GTP_DFF_R /* vs_out3 */ #( .GRS_EN("TRUE"), @@ -290930,7 +290562,7 @@ module sync_vg .CLK (clk), .D (vs_out2), .R (rst)); - // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:161 + // ../../sources/designs/hdmi/hdmi_out/sync_vg.v:163 endmodule @@ -291102,56 +290734,39 @@ module ipml_fifo_ctrl_v1_3_3 wire [16:0] \N210.co ; wire [15:0] N336; wire [16:0] \N336_7.co ; - wire _N16323; - wire _N16324; - wire _N16325; - wire _N16326; - wire _N16327; - wire _N16328; - wire _N16329; - wire _N16330; - wire _N16331; - wire _N16332; - wire _N16333; - wire _N16334; - wire _N16335; - wire _N16336; - wire _N16337; - wire _N16340; - wire _N16341; - wire _N16342; - wire _N16343; - wire _N16344; - wire _N16345; - wire _N16346; - wire _N16347; - wire _N16348; - wire _N16349; - wire _N16350; - wire _N16351; - wire _N16352; - wire _N16353; - wire _N16354; - wire _N25836; - wire _N25837; - wire _N25838; - wire _N25839; - wire _N25840; - wire _N25841; - wire _N25842; - wire _N25843; - wire _N25852; - wire _N25853; - wire _N25854; - wire _N25855; - wire _N25856; - wire _N25857; - wire _N25858; - wire _N25859; - wire _N108007; - wire _N108010; - wire _N108011; - wire _N108384; + wire _N16233; + wire _N16234; + wire _N16235; + wire _N16236; + wire _N16237; + wire _N16238; + wire _N16239; + wire _N16240; + wire _N16241; + wire _N16242; + wire _N16243; + wire _N16244; + wire _N16245; + wire _N16246; + wire _N16247; + wire _N16250; + wire _N16251; + wire _N16252; + wire _N16253; + wire _N16254; + wire _N16255; + wire _N16256; + wire _N16257; + wire _N16258; + wire _N16259; + wire _N16260; + wire _N16261; + wire _N16262; + wire _N16263; + wire _N16264; + wire _N108841; + wire _N109268; + wire _N109269; wire [15:0] nb6; wire [15:0] rbin; wire rempty; @@ -291168,6 +290783,7 @@ module ipml_fifo_ctrl_v1_3_3 wire [15:0] wrptr; wire [15:0] wrptr1; wire [15:0] wrptr2; + wire \wrptr[11]_cpy ; wire [15:0] wwptr; GTP_DFF_P /* \ASYN_CTRL.asyn_rempty */ #( @@ -292194,7 +291810,7 @@ module ipml_fifo_ctrl_v1_3_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_1 ( - .COUT (_N16323), + .COUT (_N16233), .Z (N2[0]), .CIN (), .I0 (w_en), @@ -292214,9 +291830,9 @@ module ipml_fifo_ctrl_v1_3_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_2 ( - .COUT (_N16324), + .COUT (_N16234), .Z (N2[1]), - .CIN (_N16323), + .CIN (_N16233), .I0 (w_en), .I1 (waddr[0]), .I2 (waddr[1]), @@ -292234,9 +291850,9 @@ module ipml_fifo_ctrl_v1_3_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_3 ( - .COUT (_N16325), + .COUT (_N16235), .Z (N2[2]), - .CIN (_N16324), + .CIN (_N16234), .I0 (), .I1 (waddr[2]), .I2 (), @@ -292254,9 +291870,9 @@ module ipml_fifo_ctrl_v1_3_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_4 ( - .COUT (_N16326), + .COUT (_N16236), .Z (N2[3]), - .CIN (_N16325), + .CIN (_N16235), .I0 (), .I1 (waddr[3]), .I2 (), @@ -292274,9 +291890,9 @@ module ipml_fifo_ctrl_v1_3_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_5 ( - .COUT (_N16327), + .COUT (_N16237), .Z (N2[4]), - .CIN (_N16326), + .CIN (_N16236), .I0 (), .I1 (waddr[4]), .I2 (), @@ -292294,9 +291910,9 @@ module ipml_fifo_ctrl_v1_3_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_6 ( - .COUT (_N16328), + .COUT (_N16238), .Z (N2[5]), - .CIN (_N16327), + .CIN (_N16237), .I0 (), .I1 (waddr[5]), .I2 (), @@ -292314,9 +291930,9 @@ module ipml_fifo_ctrl_v1_3_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_7 ( - .COUT (_N16329), + .COUT (_N16239), .Z (N2[6]), - .CIN (_N16328), + .CIN (_N16238), .I0 (), .I1 (waddr[6]), .I2 (), @@ -292334,9 +291950,9 @@ module ipml_fifo_ctrl_v1_3_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_8 ( - .COUT (_N16330), + .COUT (_N16240), .Z (N2[7]), - .CIN (_N16329), + .CIN (_N16239), .I0 (), .I1 (waddr[7]), .I2 (), @@ -292354,9 +291970,9 @@ module ipml_fifo_ctrl_v1_3_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_9 ( - .COUT (_N16331), + .COUT (_N16241), .Z (N2[8]), - .CIN (_N16330), + .CIN (_N16240), .I0 (), .I1 (waddr[8]), .I2 (), @@ -292374,9 +291990,9 @@ module ipml_fifo_ctrl_v1_3_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_10 ( - .COUT (_N16332), + .COUT (_N16242), .Z (N2[9]), - .CIN (_N16331), + .CIN (_N16241), .I0 (), .I1 (waddr[9]), .I2 (), @@ -292394,9 +292010,9 @@ module ipml_fifo_ctrl_v1_3_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_11 ( - .COUT (_N16333), + .COUT (_N16243), .Z (N2[10]), - .CIN (_N16332), + .CIN (_N16242), .I0 (), .I1 (waddr[10]), .I2 (), @@ -292414,9 +292030,9 @@ module ipml_fifo_ctrl_v1_3_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_12 ( - .COUT (_N16334), + .COUT (_N16244), .Z (N2[11]), - .CIN (_N16333), + .CIN (_N16243), .I0 (), .I1 (waddr[11]), .I2 (), @@ -292434,9 +292050,9 @@ module ipml_fifo_ctrl_v1_3_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_13 ( - .COUT (_N16335), + .COUT (_N16245), .Z (N2[12]), - .CIN (_N16334), + .CIN (_N16244), .I0 (), .I1 (waddr[12]), .I2 (), @@ -292454,9 +292070,9 @@ module ipml_fifo_ctrl_v1_3_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_14 ( - .COUT (_N16336), + .COUT (_N16246), .Z (N2[13]), - .CIN (_N16335), + .CIN (_N16245), .I0 (), .I1 (waddr[13]), .I2 (), @@ -292474,9 +292090,9 @@ module ipml_fifo_ctrl_v1_3_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_15 ( - .COUT (_N16337), + .COUT (_N16247), .Z (N2[14]), - .CIN (_N16336), + .CIN (_N16246), .I0 (), .I1 (waddr[14]), .I2 (), @@ -292496,7 +292112,7 @@ module ipml_fifo_ctrl_v1_3_3 N2_16 ( .COUT (), .Z (N2[15]), - .CIN (_N16337), + .CIN (_N16247), .I0 (), .I1 (wbin[15]), .I2 (), @@ -292866,24 +292482,14 @@ module ipml_fifo_ctrl_v1_3_3 .I3 (wrptr2[15])); // LUT = (I0&~I1&~I2&~I3)|(~I0&I1&~I2&~I3)|(~I0&~I1&I2&~I3)|(I0&I1&I2&~I3)|(~I0&~I1&~I2&I3)|(I0&I1&~I2&I3)|(I0&~I1&I2&I3)|(~I0&I1&I2&I3) ; - GTP_LUT3 /* N24_9 */ #( + GTP_LUT3 /* N24_14 */ #( .INIT(8'b10010110)) - N24_9 ( - .Z (wrptr[6]), - .I0 (wrptr[11]), - .I1 (wrptr2[6]), - .I2 (_N108007)); - // LUT = (I0&~I1&~I2)|(~I0&I1&~I2)|(~I0&~I1&I2)|(I0&I1&I2) ; - - GTP_LUT4 /* N24_14 */ #( - .INIT(16'b0110100110010110)) N24_14 ( .Z (wrptr[1]), - .I0 (wrptr[11]), + .I0 (wrptr[7]), .I1 (wrptr2[1]), - .I2 (_N108007), - .I3 (_N108011)); - // LUT = (I0&~I1&~I2&~I3)|(~I0&I1&~I2&~I3)|(~I0&~I1&I2&~I3)|(I0&I1&I2&~I3)|(~I0&~I1&~I2&I3)|(I0&I1&~I2&I3)|(I0&~I1&I2&I3)|(~I0&I1&I2&I3) ; + .I2 (_N108841)); + // LUT = (I0&~I1&~I2)|(~I0&I1&~I2)|(~I0&~I1&I2)|(I0&I1&I2) ; GTP_LUT5 /* N24_16 */ #( .INIT(32'b10010110011010010110100110010110)) @@ -292896,11 +292502,22 @@ module ipml_fifo_ctrl_v1_3_3 .I4 (wrptr2[15])); // LUT = (I0&~I1&~I2&~I3&~I4)|(~I0&I1&~I2&~I3&~I4)|(~I0&~I1&I2&~I3&~I4)|(I0&I1&I2&~I3&~I4)|(~I0&~I1&~I2&I3&~I4)|(I0&I1&~I2&I3&~I4)|(I0&~I1&I2&I3&~I4)|(~I0&I1&I2&I3&~I4)|(~I0&~I1&~I2&~I3&I4)|(I0&I1&~I2&~I3&I4)|(I0&~I1&I2&~I3&I4)|(~I0&I1&I2&~I3&I4)|(I0&~I1&~I2&I3&I4)|(~I0&I1&~I2&I3&I4)|(~I0&~I1&I2&I3&I4)|(I0&I1&I2&I3&I4) ; + GTP_LUT5 /* N24_16_cpy */ #( + .INIT(32'b10010110011010010110100110010110)) + N24_16_cpy ( + .Z (\wrptr[11]_cpy ), + .I0 (wrptr2[11]), + .I1 (wrptr2[12]), + .I2 (wrptr2[13]), + .I3 (wrptr2[14]), + .I4 (wrptr2[15])); + // LUT = (I0&~I1&~I2&~I3&~I4)|(~I0&I1&~I2&~I3&~I4)|(~I0&~I1&I2&~I3&~I4)|(I0&I1&I2&~I3&~I4)|(~I0&~I1&~I2&I3&~I4)|(I0&I1&~I2&I3&~I4)|(I0&~I1&I2&I3&~I4)|(~I0&I1&I2&I3&~I4)|(~I0&~I1&~I2&~I3&I4)|(I0&I1&~I2&~I3&I4)|(I0&~I1&I2&~I3&I4)|(~I0&I1&I2&~I3&I4)|(I0&~I1&~I2&I3&I4)|(~I0&I1&~I2&I3&I4)|(~I0&~I1&I2&I3&I4)|(I0&I1&I2&I3&I4) ; + GTP_LUT3 /* N24_18 */ #( .INIT(8'b10010110)) N24_18 ( .Z (wrptr[9]), - .I0 (wrptr[11]), + .I0 (\wrptr[11]_cpy ), .I1 (wrptr2[9]), .I2 (wrptr2[10])); // LUT = (I0&~I1&~I2)|(~I0&I1&~I2)|(~I0&~I1&I2)|(I0&I1&I2) ; @@ -292909,17 +292526,7 @@ module ipml_fifo_ctrl_v1_3_3 .INIT(16'b0110100110010110)) N24_20 ( .Z (wrptr[8]), - .I0 (wrptr[11]), - .I1 (wrptr2[8]), - .I2 (wrptr2[9]), - .I3 (wrptr2[10])); - // LUT = (I0&~I1&~I2&~I3)|(~I0&I1&~I2&~I3)|(~I0&~I1&I2&~I3)|(I0&I1&I2&~I3)|(~I0&~I1&~I2&I3)|(I0&I1&~I2&I3)|(I0&~I1&I2&I3)|(~I0&I1&I2&I3) ; - - GTP_LUT4 /* N24_21 */ #( - .INIT(16'b0110100110010110)) - N24_21 ( - .Z (_N108007), - .I0 (wrptr2[7]), + .I0 (\wrptr[11]_cpy ), .I1 (wrptr2[8]), .I2 (wrptr2[9]), .I3 (wrptr2[10])); @@ -292936,50 +292543,40 @@ module ipml_fifo_ctrl_v1_3_3 .I4 (wrptr2[10])); // LUT = (I0&~I1&~I2&~I3&~I4)|(~I0&I1&~I2&~I3&~I4)|(~I0&~I1&I2&~I3&~I4)|(I0&I1&I2&~I3&~I4)|(~I0&~I1&~I2&I3&~I4)|(I0&I1&~I2&I3&~I4)|(I0&~I1&I2&I3&~I4)|(~I0&I1&I2&I3&~I4)|(~I0&~I1&~I2&~I3&I4)|(I0&I1&~I2&~I3&I4)|(I0&~I1&I2&~I3&I4)|(~I0&I1&I2&~I3&I4)|(I0&~I1&~I2&I3&I4)|(~I0&I1&~I2&I3&I4)|(~I0&~I1&I2&I3&I4)|(I0&I1&I2&I3&I4) ; - GTP_LUT4 /* N24_24 */ #( - .INIT(16'b0110100110010110)) + GTP_LUT3 /* N24_24 */ #( + .INIT(8'b10010110)) N24_24 ( .Z (wrptr[5]), - .I0 (wrptr[11]), + .I0 (wrptr[7]), .I1 (wrptr2[5]), - .I2 (wrptr2[6]), - .I3 (_N108007)); - // LUT = (I0&~I1&~I2&~I3)|(~I0&I1&~I2&~I3)|(~I0&~I1&I2&~I3)|(I0&I1&I2&~I3)|(~I0&~I1&~I2&I3)|(I0&I1&~I2&I3)|(I0&~I1&I2&I3)|(~I0&I1&I2&I3) ; + .I2 (wrptr2[6])); + // LUT = (I0&~I1&~I2)|(~I0&I1&~I2)|(~I0&~I1&I2)|(I0&I1&I2) ; - GTP_LUT5 /* N24_26 */ #( - .INIT(32'b10010110011010010110100110010110)) + GTP_LUT4 /* N24_26 */ #( + .INIT(16'b0110100110010110)) N24_26 ( .Z (wrptr[4]), - .I0 (wrptr[11]), - .I1 (wrptr2[4]), - .I2 (wrptr2[5]), - .I3 (wrptr2[6]), - .I4 (_N108007)); - // LUT = (I0&~I1&~I2&~I3&~I4)|(~I0&I1&~I2&~I3&~I4)|(~I0&~I1&I2&~I3&~I4)|(I0&I1&I2&~I3&~I4)|(~I0&~I1&~I2&I3&~I4)|(I0&I1&~I2&I3&~I4)|(I0&~I1&I2&I3&~I4)|(~I0&I1&I2&I3&~I4)|(~I0&~I1&~I2&~I3&I4)|(I0&I1&~I2&~I3&I4)|(I0&~I1&I2&~I3&I4)|(~I0&I1&I2&~I3&I4)|(I0&~I1&~I2&I3&I4)|(~I0&I1&~I2&I3&I4)|(~I0&~I1&I2&I3&I4)|(I0&I1&I2&I3&I4) ; - - GTP_LUT4 /* N24_27 */ #( - .INIT(16'b0110100110010110)) - N24_27 ( - .Z (_N108010), - .I0 (wrptr2[3]), + .I0 (wrptr[7]), .I1 (wrptr2[4]), .I2 (wrptr2[5]), .I3 (wrptr2[6])); // LUT = (I0&~I1&~I2&~I3)|(~I0&I1&~I2&~I3)|(~I0&~I1&I2&~I3)|(I0&I1&I2&~I3)|(~I0&~I1&~I2&I3)|(I0&I1&~I2&I3)|(I0&~I1&I2&I3)|(~I0&I1&I2&I3) ; - GTP_LUT3 /* N24_28 */ #( - .INIT(8'b10010110)) + GTP_LUT5 /* N24_28 */ #( + .INIT(32'b10010110011010010110100110010110)) N24_28 ( .Z (wrptr[3]), - .I0 (wrptr[11]), - .I1 (_N108007), - .I2 (_N108010)); - // LUT = (I0&~I1&~I2)|(~I0&I1&~I2)|(~I0&~I1&I2)|(I0&I1&I2) ; + .I0 (wrptr[7]), + .I1 (wrptr2[3]), + .I2 (wrptr2[4]), + .I3 (wrptr2[5]), + .I4 (wrptr2[6])); + // LUT = (I0&~I1&~I2&~I3&~I4)|(~I0&I1&~I2&~I3&~I4)|(~I0&~I1&I2&~I3&~I4)|(I0&I1&I2&~I3&~I4)|(~I0&~I1&~I2&I3&~I4)|(I0&I1&~I2&I3&~I4)|(I0&~I1&I2&I3&~I4)|(~I0&I1&I2&I3&~I4)|(~I0&~I1&~I2&~I3&I4)|(I0&I1&~I2&~I3&I4)|(I0&~I1&I2&~I3&I4)|(~I0&I1&I2&~I3&I4)|(I0&~I1&~I2&I3&I4)|(~I0&I1&~I2&I3&I4)|(~I0&~I1&I2&I3&I4)|(I0&I1&I2&I3&I4) ; GTP_LUT5 /* N24_29 */ #( .INIT(32'b10010110011010010110100110010110)) N24_29 ( - .Z (_N108011), + .Z (_N108841), .I0 (wrptr2[2]), .I1 (wrptr2[3]), .I2 (wrptr2[4]), @@ -292987,26 +292584,23 @@ module ipml_fifo_ctrl_v1_3_3 .I4 (wrptr2[6])); // LUT = (I0&~I1&~I2&~I3&~I4)|(~I0&I1&~I2&~I3&~I4)|(~I0&~I1&I2&~I3&~I4)|(I0&I1&I2&~I3&~I4)|(~I0&~I1&~I2&I3&~I4)|(I0&I1&~I2&I3&~I4)|(I0&~I1&I2&I3&~I4)|(~I0&I1&I2&I3&~I4)|(~I0&~I1&~I2&~I3&I4)|(I0&I1&~I2&~I3&I4)|(I0&~I1&I2&~I3&I4)|(~I0&I1&I2&~I3&I4)|(I0&~I1&~I2&I3&I4)|(~I0&I1&~I2&I3&I4)|(~I0&~I1&I2&I3&I4)|(I0&I1&I2&I3&I4) ; - GTP_LUT4 /* N24_30 */ #( - .INIT(16'b0110100110010110)) + GTP_LUT2 /* N24_30 */ #( + .INIT(4'b0110)) N24_30 ( .Z (wrptr[2]), - .I0 (wrptr[11]), - .I1 (wrptr2[2]), - .I2 (_N108007), - .I3 (_N108010)); - // LUT = (I0&~I1&~I2&~I3)|(~I0&I1&~I2&~I3)|(~I0&~I1&I2&~I3)|(I0&I1&I2&~I3)|(~I0&~I1&~I2&I3)|(I0&I1&~I2&I3)|(I0&~I1&I2&I3)|(~I0&I1&I2&I3) ; + .I0 (wrptr[7]), + .I1 (_N108841)); + // LUT = (I0&~I1)|(~I0&I1) ; - GTP_LUT5 /* N24_32 */ #( - .INIT(32'b10010110011010010110100110010110)) + GTP_LUT4 /* N24_32 */ #( + .INIT(16'b0110100110010110)) N24_32 ( .Z (wrptr[0]), - .I0 (wrptr[11]), + .I0 (wrptr[7]), .I1 (wrptr2[0]), .I2 (wrptr2[1]), - .I3 (_N108007), - .I4 (_N108011)); - // LUT = (I0&~I1&~I2&~I3&~I4)|(~I0&I1&~I2&~I3&~I4)|(~I0&~I1&I2&~I3&~I4)|(I0&I1&I2&~I3&~I4)|(~I0&~I1&~I2&I3&~I4)|(I0&I1&~I2&I3&~I4)|(I0&~I1&I2&I3&~I4)|(~I0&I1&I2&I3&~I4)|(~I0&~I1&~I2&~I3&I4)|(I0&I1&~I2&~I3&I4)|(I0&~I1&I2&~I3&I4)|(~I0&I1&I2&~I3&I4)|(I0&~I1&~I2&I3&I4)|(~I0&I1&~I2&I3&I4)|(~I0&~I1&I2&I3&I4)|(I0&I1&I2&I3&I4) ; + .I3 (_N108841)); + // LUT = (I0&~I1&~I2&~I3)|(~I0&I1&~I2&~I3)|(~I0&~I1&I2&~I3)|(I0&I1&I2&~I3)|(~I0&~I1&~I2&I3)|(I0&I1&~I2&I3)|(I0&~I1&I2&I3)|(~I0&I1&I2&I3) ; GTP_INV N102_1_vname ( .Z (N102_1), @@ -293020,7 +292614,7 @@ module ipml_fifo_ctrl_v1_3_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_1 ( - .COUT (_N16340), + .COUT (_N16250), .Z (N104[0]), .CIN (), .I0 (\u_sync_vg/de_re0 ), @@ -293040,9 +292634,9 @@ module ipml_fifo_ctrl_v1_3_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_2 ( - .COUT (_N16341), + .COUT (_N16251), .Z (N104[1]), - .CIN (_N16340), + .CIN (_N16250), .I0 (\u_sync_vg/de_re0 ), .I1 (raddr[0]), .I2 (\u_sync_vg/pixel_show_en0 ), @@ -293060,9 +292654,9 @@ module ipml_fifo_ctrl_v1_3_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_3 ( - .COUT (_N16342), + .COUT (_N16252), .Z (N104[2]), - .CIN (_N16341), + .CIN (_N16251), .I0 (), .I1 (raddr[2]), .I2 (), @@ -293080,9 +292674,9 @@ module ipml_fifo_ctrl_v1_3_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_4 ( - .COUT (_N16343), + .COUT (_N16253), .Z (N104[3]), - .CIN (_N16342), + .CIN (_N16252), .I0 (), .I1 (raddr[3]), .I2 (), @@ -293100,9 +292694,9 @@ module ipml_fifo_ctrl_v1_3_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_5 ( - .COUT (_N16344), + .COUT (_N16254), .Z (N104[4]), - .CIN (_N16343), + .CIN (_N16253), .I0 (), .I1 (raddr[4]), .I2 (), @@ -293120,9 +292714,9 @@ module ipml_fifo_ctrl_v1_3_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_6 ( - .COUT (_N16345), + .COUT (_N16255), .Z (N104[5]), - .CIN (_N16344), + .CIN (_N16254), .I0 (), .I1 (raddr[5]), .I2 (), @@ -293140,9 +292734,9 @@ module ipml_fifo_ctrl_v1_3_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_7 ( - .COUT (_N16346), + .COUT (_N16256), .Z (N104[6]), - .CIN (_N16345), + .CIN (_N16255), .I0 (), .I1 (raddr[6]), .I2 (), @@ -293160,9 +292754,9 @@ module ipml_fifo_ctrl_v1_3_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_8 ( - .COUT (_N16347), + .COUT (_N16257), .Z (N104[7]), - .CIN (_N16346), + .CIN (_N16256), .I0 (), .I1 (raddr[7]), .I2 (), @@ -293180,9 +292774,9 @@ module ipml_fifo_ctrl_v1_3_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_9 ( - .COUT (_N16348), + .COUT (_N16258), .Z (N104[8]), - .CIN (_N16347), + .CIN (_N16257), .I0 (), .I1 (raddr[8]), .I2 (), @@ -293200,9 +292794,9 @@ module ipml_fifo_ctrl_v1_3_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_10 ( - .COUT (_N16349), + .COUT (_N16259), .Z (N104[9]), - .CIN (_N16348), + .CIN (_N16258), .I0 (), .I1 (raddr[9]), .I2 (), @@ -293220,9 +292814,9 @@ module ipml_fifo_ctrl_v1_3_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_11 ( - .COUT (_N16350), + .COUT (_N16260), .Z (N104[10]), - .CIN (_N16349), + .CIN (_N16259), .I0 (), .I1 (raddr[10]), .I2 (), @@ -293240,9 +292834,9 @@ module ipml_fifo_ctrl_v1_3_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_12 ( - .COUT (_N16351), + .COUT (_N16261), .Z (N104[11]), - .CIN (_N16350), + .CIN (_N16260), .I0 (), .I1 (raddr[11]), .I2 (), @@ -293260,9 +292854,9 @@ module ipml_fifo_ctrl_v1_3_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_13 ( - .COUT (_N16352), + .COUT (_N16262), .Z (N104[12]), - .CIN (_N16351), + .CIN (_N16261), .I0 (), .I1 (raddr[12]), .I2 (), @@ -293280,9 +292874,9 @@ module ipml_fifo_ctrl_v1_3_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_14 ( - .COUT (_N16353), + .COUT (_N16263), .Z (N104[13]), - .CIN (_N16352), + .CIN (_N16262), .I0 (), .I1 (raddr[13]), .I2 (), @@ -293300,9 +292894,9 @@ module ipml_fifo_ctrl_v1_3_3 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N104_15 ( - .COUT (_N16354), + .COUT (_N16264), .Z (N104[14]), - .CIN (_N16353), + .CIN (_N16263), .I0 (), .I1 (raddr[14]), .I2 (), @@ -293322,7 +292916,7 @@ module ipml_fifo_ctrl_v1_3_3 N104_16 ( .COUT (), .Z (N104[15]), - .CIN (_N16354), + .CIN (_N16264), .I0 (), .I1 (rbin[15]), .I2 (), @@ -293383,16 +292977,6 @@ module ipml_fifo_ctrl_v1_3_3 // LUT = (~I0&I2)|(I0&I1) ; // ../ipcore/image_in_fifo/rtl/ipml_fifo_ctrl_v1_3.v:150 - GTP_LUT3 /* \N105[5] */ #( - .INIT(8'b11011000)) - \N105[5] ( - .Z (rrptr[5]), - .I0 (rempty), - .I1 (raddr[5]), - .I2 (N104[5])); - // LUT = (~I0&I2)|(I0&I1) ; - // ../ipcore/image_in_fifo/rtl/ipml_fifo_ctrl_v1_3.v:150 - GTP_LUT3 /* \N105[6] */ #( .INIT(8'b11011000)) \N105[6] ( @@ -293686,21 +293270,13 @@ module ipml_fifo_ctrl_v1_3_3 GTP_LUT4 /* N126_7 */ #( .INIT(16'b1010011010010101)) N126_7 ( - .Z (_N108384), + .Z (_N109269), .I0 (rwptr2[9]), .I1 (rempty), .I2 (raddr[9]), .I3 (N104[9])); // LUT = (~I0&~I1&~I3)|(~I0&I1&~I2)|(I0&~I1&I3)|(I0&I1&I2) ; - GTP_LUT2 /* N126_10 */ #( - .INIT(4'b0110)) - N126_10 ( - .Z (rwptr[5]), - .I0 (rwptr[6]), - .I1 (rwptr2[5])); - // LUT = (I0&~I1)|(~I0&I1) ; - GTP_LUT4 /* N126_12 */ #( .INIT(16'b0110100110010110)) N126_12 ( @@ -293760,6 +293336,25 @@ module ipml_fifo_ctrl_v1_3_3 .I4 (rwptr2[9])); // LUT = (I0&~I1&~I2&~I3&~I4)|(~I0&I1&~I2&~I3&~I4)|(~I0&~I1&I2&~I3&~I4)|(I0&I1&I2&~I3&~I4)|(~I0&~I1&~I2&I3&~I4)|(I0&I1&~I2&I3&~I4)|(I0&~I1&I2&I3&~I4)|(~I0&I1&I2&I3&~I4)|(~I0&~I1&~I2&~I3&I4)|(I0&I1&~I2&~I3&I4)|(I0&~I1&I2&~I3&I4)|(~I0&I1&I2&~I3&I4)|(I0&~I1&~I2&I3&I4)|(~I0&I1&~I2&I3&I4)|(~I0&~I1&I2&I3&I4)|(I0&I1&I2&I3&I4) ; + GTP_LUT3 /* N126_24 */ #( + .INIT(8'b10010110)) + N126_24 ( + .Z (rwptr[4]), + .I0 (rwptr[6]), + .I1 (rwptr2[4]), + .I2 (rwptr2[5])); + // LUT = (I0&~I1&~I2)|(~I0&I1&~I2)|(~I0&~I1&I2)|(I0&I1&I2) ; + + GTP_LUT4 /* N126_25 */ #( + .INIT(16'b1010011010010101)) + N126_25 ( + .Z (_N109268), + .I0 (rwptr2[5]), + .I1 (rempty), + .I2 (raddr[5]), + .I3 (N104[5])); + // LUT = (~I0&~I1&~I3)|(~I0&I1&~I2)|(I0&~I1&I3)|(I0&I1&I2) ; + GTP_LUT5CARRY /* \N207.eq_0 */ #( .INIT(32'b10010000000010010000000000000000), .ID_TO_LUT("FALSE"), @@ -293873,7 +293468,7 @@ module ipml_fifo_ctrl_v1_3_3 .I0 (wwptr[10]), .I1 (wrptr2[10]), .I2 (wwptr[11]), - .I3 (wrptr[11]), + .I3 (\wrptr[11]_cpy ), .I4 (), .ID ()); // LUT = 1'b0 ; @@ -293974,7 +293569,7 @@ module ipml_fifo_ctrl_v1_3_3 // ../ipcore/image_in_fifo/rtl/ipml_fifo_ctrl_v1_3.v:216 GTP_LUT5CARRY /* \N210.eq_2 */ #( - .INIT(32'b00000000000000000110000000001001), + .INIT(32'b00000000000000000000100110010000), .ID_TO_LUT("FALSE"), .CIN_TO_LUT("FALSE"), .I4_TO_CARRY("FALSE"), @@ -293983,14 +293578,14 @@ module ipml_fifo_ctrl_v1_3_3 .COUT (\N210.co [4] ), .Z (), .CIN (\N210.co [2] ), - .I0 (rwptr2[4]), + .I0 (rwptr[4]), .I1 (rrptr[4]), - .I2 (rwptr[5]), - .I3 (rrptr[5]), + .I2 (rwptr[6]), + .I3 (_N109268), .I4 (), .ID ()); // LUT = 1'b0 ; - // CARRY = ((~I0&~I1&~I2&~I3)|(I0&I1&~I2&~I3)|(I0&~I1&I2&I3)|(~I0&I1&I2&I3)) ? CIN : (1'b0) ; + // CARRY = ((~I0&~I1&I2&~I3)|(I0&I1&I2&~I3)|(~I0&~I1&~I2&I3)|(I0&I1&~I2&I3)) ? CIN : (1'b0) ; // ../ipcore/image_in_fifo/rtl/ipml_fifo_ctrl_v1_3.v:216 GTP_LUT5CARRY /* \N210.eq_3 */ #( @@ -294026,7 +293621,7 @@ module ipml_fifo_ctrl_v1_3_3 .I0 (rwptr[8]), .I1 (rrptr[8]), .I2 (rwptr[10]), - .I3 (_N108384), + .I3 (_N109269), .I4 (), .ID ()); // LUT = 1'b0 ; @@ -294093,213 +293688,77 @@ module ipml_fifo_ctrl_v1_3_3 // CARRY = ((~I0&~I1&~I2&~I3)|(I0&I1&~I2&~I3)|(I0&~I1&I2&I3)|(~I0&I1&I2&I3)) ? CIN : (1'b0) ; // ../ipcore/image_in_fifo/rtl/ipml_fifo_ctrl_v1_3.v:216 - GTP_LUT4 /* \N336_4[5] */ #( - .INIT(16'b1111000011110000)) - \N336_4[5] ( - .Z (_N25836), - .I0 (wfull), - .I1 (N2[15]), - .I2 (nb6[5]), - .I3 (wbin[15])); - // LUT = I2 ; - - GTP_LUT4 /* \N336_4[6] */ #( - .INIT(16'b1111000011110000)) - \N336_4[6] ( - .Z (_N25837), - .I0 (wfull), - .I1 (N2[15]), - .I2 (nb6[6]), - .I3 (wbin[15])); - // LUT = I2 ; - - GTP_LUT4 /* \N336_4[7] */ #( - .INIT(16'b1111000011110000)) - \N336_4[7] ( - .Z (_N25838), - .I0 (wfull), - .I1 (N2[15]), - .I2 (nb6[7]), - .I3 (wbin[15])); - // LUT = I2 ; - - GTP_LUT4 /* \N336_4[8] */ #( - .INIT(16'b1111000011110000)) - \N336_4[8] ( - .Z (_N25839), - .I0 (wfull), - .I1 (N2[15]), - .I2 (nb6[8]), - .I3 (wbin[15])); - // LUT = I2 ; - - GTP_LUT4 /* \N336_4[9] */ #( - .INIT(16'b1111000011110000)) - \N336_4[9] ( - .Z (_N25840), - .I0 (wfull), - .I1 (N2[15]), - .I2 (nb6[9]), - .I3 (wbin[15])); - // LUT = I2 ; - - GTP_LUT4 /* \N336_4[10] */ #( - .INIT(16'b1111000011110000)) - \N336_4[10] ( - .Z (_N25841), - .I0 (wfull), - .I1 (N2[15]), - .I2 (nb6[10]), - .I3 (wbin[15])); - // LUT = I2 ; - - GTP_LUT4 /* \N336_4[11] */ #( - .INIT(16'b1111000011110000)) - \N336_4[11] ( - .Z (_N25842), - .I0 (wfull), - .I1 (N2[15]), - .I2 (nb6[11]), - .I3 (wbin[15])); - // LUT = I2 ; - - GTP_LUT4 /* \N336_4[12] */ #( - .INIT(16'b1111000011110000)) - \N336_4[12] ( - .Z (_N25843), - .I0 (wfull), - .I1 (N2[15]), - .I2 (nb6[12]), - .I3 (wbin[15])); - // LUT = I2 ; - - GTP_LUT4 /* \N336_5[5] */ #( - .INIT(16'b1111000011110000)) - \N336_5[5] ( - .Z (_N25852), - .I0 (wfull), - .I1 (N2[15]), - .I2 (nb6[5]), - .I3 (wbin[15])); - // LUT = I2 ; - - GTP_LUT4 /* \N336_5[6] */ #( - .INIT(16'b1111000011110000)) - \N336_5[6] ( - .Z (_N25853), - .I0 (wfull), - .I1 (N2[15]), - .I2 (nb6[6]), - .I3 (wbin[15])); - // LUT = I2 ; - - GTP_LUT4 /* \N336_5[7] */ #( - .INIT(16'b1111000011110000)) - \N336_5[7] ( - .Z (_N25854), - .I0 (wfull), - .I1 (N2[15]), - .I2 (nb6[7]), - .I3 (wbin[15])); - // LUT = I2 ; - - GTP_LUT4 /* \N336_5[8] */ #( - .INIT(16'b1111000011110000)) - \N336_5[8] ( - .Z (_N25855), - .I0 (wfull), - .I1 (N2[15]), - .I2 (nb6[8]), - .I3 (wbin[15])); - // LUT = I2 ; - - GTP_LUT4 /* \N336_5[9] */ #( - .INIT(16'b1111000011110000)) - \N336_5[9] ( - .Z (_N25856), - .I0 (wfull), - .I1 (N2[15]), - .I2 (nb6[9]), - .I3 (wbin[15])); - // LUT = I2 ; - - GTP_LUT4 /* \N336_5[10] */ #( - .INIT(16'b1111000011110000)) - \N336_5[10] ( - .Z (_N25857), - .I0 (wfull), - .I1 (N2[15]), - .I2 (nb6[10]), - .I3 (wbin[15])); - // LUT = I2 ; - - GTP_LUT4 /* \N336_5[11] */ #( - .INIT(16'b1111000011110000)) - \N336_5[11] ( - .Z (_N25858), - .I0 (wfull), - .I1 (N2[15]), - .I2 (nb6[11]), - .I3 (wbin[15])); - // LUT = I2 ; - - GTP_LUT4 /* \N336_5[12] */ #( - .INIT(16'b1111000011110000)) - \N336_5[12] ( - .Z (_N25859), - .I0 (wfull), - .I1 (N2[15]), - .I2 (nb6[12]), - .I3 (wbin[15])); - // LUT = I2 ; - - GTP_MUX2LUT6 \N336_6[5] ( + GTP_LUT3 /* \N336_6[5] */ #( + .INIT(8'b10101010)) + \N336_6[5] ( .Z (N336[5]), - .I0 (_N25852), - .I1 (_N25836), - .S (wrptr2[15])); + .I0 (nb6[5]), + .I1 (wrptr2[15]), + .I2 (wwptr[15])); + // LUT = I0 ; - GTP_MUX2LUT6 \N336_6[6] ( + GTP_LUT3 /* \N336_6[6] */ #( + .INIT(8'b10101010)) + \N336_6[6] ( .Z (N336[6]), - .I0 (_N25853), - .I1 (_N25837), - .S (wrptr2[15])); + .I0 (nb6[6]), + .I1 (wrptr2[15]), + .I2 (wwptr[15])); + // LUT = I0 ; - GTP_MUX2LUT6 \N336_6[7] ( + GTP_LUT3 /* \N336_6[7] */ #( + .INIT(8'b10101010)) + \N336_6[7] ( .Z (N336[7]), - .I0 (_N25854), - .I1 (_N25838), - .S (wrptr2[15])); + .I0 (nb6[7]), + .I1 (wrptr2[15]), + .I2 (wwptr[15])); + // LUT = I0 ; - GTP_MUX2LUT6 \N336_6[8] ( + GTP_LUT3 /* \N336_6[8] */ #( + .INIT(8'b10101010)) + \N336_6[8] ( .Z (N336[8]), - .I0 (_N25855), - .I1 (_N25839), - .S (wrptr2[15])); + .I0 (nb6[8]), + .I1 (wrptr2[15]), + .I2 (wwptr[15])); + // LUT = I0 ; - GTP_MUX2LUT6 \N336_6[9] ( + GTP_LUT3 /* \N336_6[9] */ #( + .INIT(8'b10101010)) + \N336_6[9] ( .Z (N336[9]), - .I0 (_N25856), - .I1 (_N25840), - .S (wrptr2[15])); + .I0 (nb6[9]), + .I1 (wrptr2[15]), + .I2 (wwptr[15])); + // LUT = I0 ; - GTP_MUX2LUT6 \N336_6[10] ( + GTP_LUT3 /* \N336_6[10] */ #( + .INIT(8'b10101010)) + \N336_6[10] ( .Z (N336[10]), - .I0 (_N25857), - .I1 (_N25841), - .S (wrptr2[15])); + .I0 (nb6[10]), + .I1 (wrptr2[15]), + .I2 (wwptr[15])); + // LUT = I0 ; - GTP_MUX2LUT6 \N336_6[11] ( + GTP_LUT3 /* \N336_6[11] */ #( + .INIT(8'b10101010)) + \N336_6[11] ( .Z (N336[11]), - .I0 (_N25858), - .I1 (_N25842), - .S (wrptr2[15])); + .I0 (nb6[11]), + .I1 (wrptr2[15]), + .I2 (wwptr[15])); + // LUT = I0 ; - GTP_MUX2LUT6 \N336_6[12] ( + GTP_LUT3 /* \N336_6[12] */ #( + .INIT(8'b10101010)) + \N336_6[12] ( .Z (N336[12]), - .I0 (_N25859), - .I1 (_N25843), - .S (wrptr2[15])); + .I0 (nb6[12]), + .I1 (wrptr2[15]), + .I2 (wwptr[15])); + // LUT = I0 ; GTP_LUT5CARRY /* \N336_7.fsub_1 */ #( .INIT(32'b00000000000000000000000000000000), @@ -294340,7 +293799,7 @@ module ipml_fifo_ctrl_v1_3_3 // CARRY = ((~I2&I3)|(I1&I3)|(~I0&I3)|(I1&~I2)|(~I0&~I2)) ? CIN : (I4) ; GTP_LUT5CARRY /* \N336_7.fsub_3 */ #( - .INIT(32'b01101001011010011100001111000011), + .INIT(32'b10010110011010010011110011000011), .ID_TO_LUT("FALSE"), .CIN_TO_LUT("TRUE"), .I4_TO_CARRY("TRUE"), @@ -294350,13 +293809,13 @@ module ipml_fifo_ctrl_v1_3_3 .Z (), .CIN (\N336_7.co [2] ), .I0 (), - .I1 (wrptr[2]), + .I1 (wrptr[7]), .I2 (wwptr[2]), - .I3 (), + .I3 (_N108841), .I4 (wwptr[2]), .ID ()); - // LUT = ~I2^I1^CIN ; - // CARRY = (~I2^I1) ? CIN : (I4) ; + // LUT = ~I3^I2^I1^CIN ; + // CARRY = (~I3^I2^I1) ? CIN : (I4) ; GTP_LUT5CARRY /* \N336_7.fsub_4 */ #( .INIT(32'b01101001011010011100001111000011), @@ -294416,7 +293875,7 @@ module ipml_fifo_ctrl_v1_3_3 // CARRY = (~I2^I1) ? CIN : (I4) ; GTP_LUT5CARRY /* \N336_7.fsub_7 */ #( - .INIT(32'b01101001011010011100001111000011), + .INIT(32'b10010110011010010011110011000011), .ID_TO_LUT("FALSE"), .CIN_TO_LUT("TRUE"), .I4_TO_CARRY("TRUE"), @@ -294426,13 +293885,13 @@ module ipml_fifo_ctrl_v1_3_3 .Z (nb6[6]), .CIN (\N336_7.co [6] ), .I0 (), - .I1 (wrptr[6]), + .I1 (wrptr[7]), .I2 (wwptr[6]), - .I3 (), + .I3 (wrptr2[6]), .I4 (wwptr[6]), .ID ()); - // LUT = ~I2^I1^CIN ; - // CARRY = (~I2^I1) ? CIN : (I4) ; + // LUT = ~I3^I2^I1^CIN ; + // CARRY = (~I3^I2^I1) ? CIN : (I4) ; GTP_LUT5CARRY /* \N336_7.fsub_8 */ #( .INIT(32'b01101001011010011100001111000011), @@ -294502,7 +293961,7 @@ module ipml_fifo_ctrl_v1_3_3 .Z (nb6[10]), .CIN (\N336_7.co [10] ), .I0 (), - .I1 (wrptr[11]), + .I1 (\wrptr[11]_cpy ), .I2 (wwptr[10]), .I3 (wrptr2[10]), .I4 (wwptr[10]), @@ -294521,7 +293980,7 @@ module ipml_fifo_ctrl_v1_3_3 .Z (nb6[11]), .CIN (\N336_7.co [11] ), .I0 (), - .I1 (wrptr[11]), + .I1 (\wrptr[11]_cpy ), .I2 (wwptr[11]), .I3 (), .I4 (wwptr[11]), @@ -294967,7 +294426,7 @@ module ipml_sdpram_v1_6_zoom_hdmi_fifo ); wire [575:0] QA_bus; wire [575:0] QB_bus; - wire _N103312; + wire _N104124; wire [0:0] addr_bus_rd_sel; GTP_DRM18K /* \ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K */ #( @@ -298497,13 +297956,13 @@ module ipml_sdpram_v1_6_zoom_hdmi_fifo .Q (addr_bus_rd_sel[0]), .C (rd_rst), .CLK (rd_clk), - .D (_N103312)); + .D (_N104124)); // ../ipcore/zoom_hdmi_fifo/rtl/ipml_sdpram_v1_6_zoom_hdmi_fifo.v:1054 GTP_LUT3 /* \addr_bus_rd_ce_ce_mux[0] */ #( .INIT(8'b11011000)) \addr_bus_rd_ce_ce_mux[0] ( - .Z (_N103312), + .Z (_N104124), .I0 (rd_clk_en), .I1 (rd_addr[14]), .I2 (addr_bus_rd_sel[0])); @@ -298778,15 +298237,13 @@ module mult_fra0 input CLK, output [15:0] P ); - wire _N12003; - wire _N12004; wire _N12005; wire _N12006; wire _N12007; wire _N12008; wire _N12009; - wire _N12019; - wire _N12020; + wire _N12010; + wire _N12011; wire _N12021; wire _N12022; wire _N12023; @@ -298817,204 +298274,8 @@ module mult_fra0 wire _N12048; wire _N12049; wire _N12050; - wire \N2_CPO[0]_floating ; - wire \N2_CPO[1]_floating ; - wire \N2_CPO[2]_floating ; - wire \N2_CPO[3]_floating ; - wire \N2_CPO[4]_floating ; - wire \N2_CPO[5]_floating ; - wire \N2_CPO[6]_floating ; - wire \N2_CPO[7]_floating ; - wire \N2_CPO[8]_floating ; - wire \N2_CPO[9]_floating ; - wire \N2_CPO[10]_floating ; - wire \N2_CPO[11]_floating ; - wire \N2_CPO[12]_floating ; - wire \N2_CPO[13]_floating ; - wire \N2_CPO[14]_floating ; - wire \N2_CPO[15]_floating ; - wire \N2_CPO[16]_floating ; - wire \N2_CPO[17]_floating ; - wire \N2_CPO[18]_floating ; - wire \N2_CPO[19]_floating ; - wire \N2_CPO[20]_floating ; - wire \N2_CPO[21]_floating ; - wire \N2_CPO[22]_floating ; - wire \N2_CPO[23]_floating ; - wire \N2_CPO[24]_floating ; - wire \N2_CPO[25]_floating ; - wire \N2_CPO[26]_floating ; - wire \N2_CPO[27]_floating ; - wire \N2_CPO[28]_floating ; - wire \N2_CPO[29]_floating ; - wire \N2_CPO[30]_floating ; - wire \N2_CPO[31]_floating ; - wire \N2_CPO[32]_floating ; - wire \N2_CPO[33]_floating ; - wire \N2_CPO[34]_floating ; - wire \N2_CPO[35]_floating ; - wire \N2_CPO[36]_floating ; - wire \N2_CPO[37]_floating ; - wire \N2_CPO[38]_floating ; - wire \N2_CPO[39]_floating ; - wire \N2_CPO[40]_floating ; - wire \N2_CPO[41]_floating ; - wire \N2_CPO[42]_floating ; - wire \N2_CPO[43]_floating ; - wire \N2_CPO[44]_floating ; - wire \N2_CPO[45]_floating ; - wire \N2_CPO[46]_floating ; - wire \N2_CPO[47]_floating ; - wire \N2_CXBO[0]_floating ; - wire \N2_CXBO[1]_floating ; - wire \N2_CXBO[2]_floating ; - wire \N2_CXBO[3]_floating ; - wire \N2_CXBO[4]_floating ; - wire \N2_CXBO[5]_floating ; - wire \N2_CXBO[6]_floating ; - wire \N2_CXBO[7]_floating ; - wire \N2_CXBO[8]_floating ; - wire \N2_CXBO[9]_floating ; - wire \N2_CXBO[10]_floating ; - wire \N2_CXBO[11]_floating ; - wire \N2_CXBO[12]_floating ; - wire \N2_CXBO[13]_floating ; - wire \N2_CXBO[14]_floating ; - wire \N2_CXBO[15]_floating ; - wire \N2_CXBO[16]_floating ; - wire \N2_CXBO[17]_floating ; - wire \N2_CXO[0]_floating ; - wire \N2_CXO[1]_floating ; - wire \N2_CXO[2]_floating ; - wire \N2_CXO[3]_floating ; - wire \N2_CXO[4]_floating ; - wire \N2_CXO[5]_floating ; - wire \N2_CXO[6]_floating ; - wire \N2_CXO[7]_floating ; - wire \N2_CXO[8]_floating ; - wire \N2_CXO[9]_floating ; - wire \N2_CXO[10]_floating ; - wire \N2_CXO[11]_floating ; - wire \N2_CXO[12]_floating ; - wire \N2_CXO[13]_floating ; - wire \N2_CXO[14]_floating ; - wire \N2_CXO[15]_floating ; - wire \N2_CXO[16]_floating ; - wire \N2_CXO[17]_floating ; - - GTP_APM_E1 /* N2 */ #( - .GRS_EN("TRUE"), - .ASYNC_RST(0), - .X_SIGNED(0), - .Y_SIGNED(0), - .X_REG(1), - .Y_REG(1), - .Z_REG(0), - .P_REG(0), - .CXO_REG(0), - .CPO_REG(0), - .MULT_REG(1), - .PREADD_REG(0), - .MODEX_REG(0), - .MODEY_REG(0), - .MODEZ_REG(0), - .X_SEL(0), - .XB_SEL(0), - .CIN_SEL(0), - .USE_SIMD(1), - .USE_ACCLOW(0), - .USE_PREADD(0), - .USE_POSTADD(0), - .Z_INIT(48'b000000000000000000000000000000000000000000000000)) - N2 ( - .CPO (), - .CXBO (), - .CXO (), - .P ({_N12050, _N12049, _N12048, _N12047, _N12046, _N12045, _N12044, _N12043, _N12042, _N12041, _N12040, _N12039, _N12038, _N12037, _N12036, _N12035, _N12034, _N12033, _N12032, _N12031, _N12030, _N12029, _N12028, _N12027, _N12026, _N12025, _N12024, _N12023, _N12022, _N12021, _N12020, _N12019, P[15], P[14], P[13], P[12], P[11], P[10], P[9], P[8], P[7], _N12009, _N12008, _N12007, _N12006, _N12005, _N12004, _N12003}), - .CPI (), - .CXBI (), - .CXI (), - .MODEY ({1'b0, 1'b0, 1'b0}), - .MODEZ ({1'b0, 1'b0, 1'b0, 1'b0}), - .X ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'b0, \u_zoom_image/N953 [7] , \u_zoom_image/N953 [6] , \u_zoom_image/N953 [5] , \u_zoom_image/N953 [4] , \u_zoom_image/N953 [3] , \u_zoom_image/N953 [2] , \u_zoom_image/N953 [1] , \u_zoom_image/image_w2_coe1 [0] }), - .Y ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'b0, \u_zoom_image/N950 [7] , \u_zoom_image/N950 [6] , \u_zoom_image/N950 [5] , \u_zoom_image/N950 [4] , \u_zoom_image/N950 [3] , \u_zoom_image/N950 [2] , \u_zoom_image/N950 [1] , \u_zoom_image/image_h2_coe1 [0] }), - .Z (), - .COUT (), - .CEM (1'b1), - .CEMODEX (), - .CEMODEY (), - .CEMODEZ (), - .CEP (), - .CEPRE (), - .CEX (1'b1), - .CEY (1'b1), - .CEZ (), - .CIN (), - .CLK (CLK), - .MODEX (1'b0), - .RSTM (1'b0), - .RSTMODEX (), - .RSTMODEY (), - .RSTMODEZ (), - .RSTP (), - .RSTPRE (), - .RSTX (1'b0), - .RSTY (1'b0), - .RSTZ ()); - // ../../sources/designs/zoom/mult_fra.v:35 - - -endmodule - - -module mult_fra0_unq8 -( - input [7:0] \u_zoom_image/N950 , - input [6:0] \u_zoom_image/image_h2_coe1 , - input [6:0] \u_zoom_image/image_w2_coe1 , - input CLK, - output [15:0] P -); wire _N12051; wire _N12052; - wire _N12053; - wire _N12054; - wire _N12055; - wire _N12056; - wire _N12057; - wire _N12066; - wire _N12067; - wire _N12068; - wire _N12069; - wire _N12070; - wire _N12071; - wire _N12072; - wire _N12073; - wire _N12074; - wire _N12075; - wire _N12076; - wire _N12077; - wire _N12078; - wire _N12079; - wire _N12080; - wire _N12081; - wire _N12082; - wire _N12083; - wire _N12084; - wire _N12085; - wire _N12086; - wire _N12087; - wire _N12088; - wire _N12089; - wire _N12090; - wire _N12091; - wire _N12092; - wire _N12093; - wire _N12094; - wire _N12095; - wire _N12096; - wire _N12097; - wire _N12098; wire \N2_CPO[0]_floating ; wire \N2_CPO[1]_floating ; wire \N2_CPO[2]_floating ; @@ -299128,7 +298389,205 @@ module mult_fra0_unq8 .CPO (), .CXBO (), .CXO (), - .P ({_N12098, _N12097, _N12096, _N12095, _N12094, _N12093, _N12092, _N12091, _N12090, _N12089, _N12088, _N12087, _N12086, _N12085, _N12084, _N12083, _N12082, _N12081, _N12080, _N12079, _N12078, _N12077, _N12076, _N12075, _N12074, _N12073, _N12072, _N12071, _N12070, _N12069, _N12068, _N12067, _N12066, P[14], P[13], P[12], P[11], P[10], P[9], P[8], P[7], _N12057, _N12056, _N12055, _N12054, _N12053, _N12052, _N12051}), + .P ({_N12052, _N12051, _N12050, _N12049, _N12048, _N12047, _N12046, _N12045, _N12044, _N12043, _N12042, _N12041, _N12040, _N12039, _N12038, _N12037, _N12036, _N12035, _N12034, _N12033, _N12032, _N12031, _N12030, _N12029, _N12028, _N12027, _N12026, _N12025, _N12024, _N12023, _N12022, _N12021, P[15], P[14], P[13], P[12], P[11], P[10], P[9], P[8], P[7], _N12011, _N12010, _N12009, _N12008, _N12007, _N12006, _N12005}), + .CPI (), + .CXBI (), + .CXI (), + .MODEY ({1'b0, 1'b0, 1'b0}), + .MODEZ ({1'b0, 1'b0, 1'b0, 1'b0}), + .X ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'b0, \u_zoom_image/N953 [7] , \u_zoom_image/N953 [6] , \u_zoom_image/N953 [5] , \u_zoom_image/N953 [4] , \u_zoom_image/N953 [3] , \u_zoom_image/N953 [2] , \u_zoom_image/N953 [1] , \u_zoom_image/image_w2_coe1 [0] }), + .Y ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'b0, \u_zoom_image/N950 [7] , \u_zoom_image/N950 [6] , \u_zoom_image/N950 [5] , \u_zoom_image/N950 [4] , \u_zoom_image/N950 [3] , \u_zoom_image/N950 [2] , \u_zoom_image/N950 [1] , \u_zoom_image/image_h2_coe1 [0] }), + .Z (), + .COUT (), + .CEM (1'b1), + .CEMODEX (), + .CEMODEY (), + .CEMODEZ (), + .CEP (), + .CEPRE (), + .CEX (1'b1), + .CEY (1'b1), + .CEZ (), + .CIN (), + .CLK (CLK), + .MODEX (1'b0), + .RSTM (1'b0), + .RSTMODEX (), + .RSTMODEY (), + .RSTMODEZ (), + .RSTP (), + .RSTPRE (), + .RSTX (1'b0), + .RSTY (1'b0), + .RSTZ ()); + // ../../sources/designs/zoom/mult_fra.v:35 + + +endmodule + + +module mult_fra0_unq8 +( + input [7:0] \u_zoom_image/N950 , + input [6:0] \u_zoom_image/image_h2_coe1 , + input [6:0] \u_zoom_image/image_w2_coe1 , + input CLK, + output [15:0] P +); + wire _N12053; + wire _N12054; + wire _N12055; + wire _N12056; + wire _N12057; + wire _N12058; + wire _N12059; + wire _N12068; + wire _N12069; + wire _N12070; + wire _N12071; + wire _N12072; + wire _N12073; + wire _N12074; + wire _N12075; + wire _N12076; + wire _N12077; + wire _N12078; + wire _N12079; + wire _N12080; + wire _N12081; + wire _N12082; + wire _N12083; + wire _N12084; + wire _N12085; + wire _N12086; + wire _N12087; + wire _N12088; + wire _N12089; + wire _N12090; + wire _N12091; + wire _N12092; + wire _N12093; + wire _N12094; + wire _N12095; + wire _N12096; + wire _N12097; + wire _N12098; + wire _N12099; + wire _N12100; + wire \N2_CPO[0]_floating ; + wire \N2_CPO[1]_floating ; + wire \N2_CPO[2]_floating ; + wire \N2_CPO[3]_floating ; + wire \N2_CPO[4]_floating ; + wire \N2_CPO[5]_floating ; + wire \N2_CPO[6]_floating ; + wire \N2_CPO[7]_floating ; + wire \N2_CPO[8]_floating ; + wire \N2_CPO[9]_floating ; + wire \N2_CPO[10]_floating ; + wire \N2_CPO[11]_floating ; + wire \N2_CPO[12]_floating ; + wire \N2_CPO[13]_floating ; + wire \N2_CPO[14]_floating ; + wire \N2_CPO[15]_floating ; + wire \N2_CPO[16]_floating ; + wire \N2_CPO[17]_floating ; + wire \N2_CPO[18]_floating ; + wire \N2_CPO[19]_floating ; + wire \N2_CPO[20]_floating ; + wire \N2_CPO[21]_floating ; + wire \N2_CPO[22]_floating ; + wire \N2_CPO[23]_floating ; + wire \N2_CPO[24]_floating ; + wire \N2_CPO[25]_floating ; + wire \N2_CPO[26]_floating ; + wire \N2_CPO[27]_floating ; + wire \N2_CPO[28]_floating ; + wire \N2_CPO[29]_floating ; + wire \N2_CPO[30]_floating ; + wire \N2_CPO[31]_floating ; + wire \N2_CPO[32]_floating ; + wire \N2_CPO[33]_floating ; + wire \N2_CPO[34]_floating ; + wire \N2_CPO[35]_floating ; + wire \N2_CPO[36]_floating ; + wire \N2_CPO[37]_floating ; + wire \N2_CPO[38]_floating ; + wire \N2_CPO[39]_floating ; + wire \N2_CPO[40]_floating ; + wire \N2_CPO[41]_floating ; + wire \N2_CPO[42]_floating ; + wire \N2_CPO[43]_floating ; + wire \N2_CPO[44]_floating ; + wire \N2_CPO[45]_floating ; + wire \N2_CPO[46]_floating ; + wire \N2_CPO[47]_floating ; + wire \N2_CXBO[0]_floating ; + wire \N2_CXBO[1]_floating ; + wire \N2_CXBO[2]_floating ; + wire \N2_CXBO[3]_floating ; + wire \N2_CXBO[4]_floating ; + wire \N2_CXBO[5]_floating ; + wire \N2_CXBO[6]_floating ; + wire \N2_CXBO[7]_floating ; + wire \N2_CXBO[8]_floating ; + wire \N2_CXBO[9]_floating ; + wire \N2_CXBO[10]_floating ; + wire \N2_CXBO[11]_floating ; + wire \N2_CXBO[12]_floating ; + wire \N2_CXBO[13]_floating ; + wire \N2_CXBO[14]_floating ; + wire \N2_CXBO[15]_floating ; + wire \N2_CXBO[16]_floating ; + wire \N2_CXBO[17]_floating ; + wire \N2_CXO[0]_floating ; + wire \N2_CXO[1]_floating ; + wire \N2_CXO[2]_floating ; + wire \N2_CXO[3]_floating ; + wire \N2_CXO[4]_floating ; + wire \N2_CXO[5]_floating ; + wire \N2_CXO[6]_floating ; + wire \N2_CXO[7]_floating ; + wire \N2_CXO[8]_floating ; + wire \N2_CXO[9]_floating ; + wire \N2_CXO[10]_floating ; + wire \N2_CXO[11]_floating ; + wire \N2_CXO[12]_floating ; + wire \N2_CXO[13]_floating ; + wire \N2_CXO[14]_floating ; + wire \N2_CXO[15]_floating ; + wire \N2_CXO[16]_floating ; + wire \N2_CXO[17]_floating ; + + GTP_APM_E1 /* N2 */ #( + .GRS_EN("TRUE"), + .ASYNC_RST(0), + .X_SIGNED(0), + .Y_SIGNED(0), + .X_REG(1), + .Y_REG(1), + .Z_REG(0), + .P_REG(0), + .CXO_REG(0), + .CPO_REG(0), + .MULT_REG(1), + .PREADD_REG(0), + .MODEX_REG(0), + .MODEY_REG(0), + .MODEZ_REG(0), + .X_SEL(0), + .XB_SEL(0), + .CIN_SEL(0), + .USE_SIMD(1), + .USE_ACCLOW(0), + .USE_PREADD(0), + .USE_POSTADD(0), + .Z_INIT(48'b000000000000000000000000000000000000000000000000)) + N2 ( + .CPO (), + .CXBO (), + .CXO (), + .P ({_N12100, _N12099, _N12098, _N12097, _N12096, _N12095, _N12094, _N12093, _N12092, _N12091, _N12090, _N12089, _N12088, _N12087, _N12086, _N12085, _N12084, _N12083, _N12082, _N12081, _N12080, _N12079, _N12078, _N12077, _N12076, _N12075, _N12074, _N12073, _N12072, _N12071, _N12070, _N12069, _N12068, P[14], P[13], P[12], P[11], P[10], P[9], P[8], P[7], _N12059, _N12058, _N12057, _N12056, _N12055, _N12054, _N12053}), .CPI (), .CXBI (), .CXI (), @@ -299173,15 +298632,13 @@ module mult_fra0_unq10 input CLK, output [15:0] P ); - wire _N12099; - wire _N12100; wire _N12101; wire _N12102; wire _N12103; wire _N12104; wire _N12105; - wire _N12114; - wire _N12115; + wire _N12106; + wire _N12107; wire _N12116; wire _N12117; wire _N12118; @@ -299213,6 +298670,8 @@ module mult_fra0_unq10 wire _N12144; wire _N12145; wire _N12146; + wire _N12147; + wire _N12148; wire \N2_CPO[0]_floating ; wire \N2_CPO[1]_floating ; wire \N2_CPO[2]_floating ; @@ -299326,7 +298785,7 @@ module mult_fra0_unq10 .CPO (), .CXBO (), .CXO (), - .P ({_N12146, _N12145, _N12144, _N12143, _N12142, _N12141, _N12140, _N12139, _N12138, _N12137, _N12136, _N12135, _N12134, _N12133, _N12132, _N12131, _N12130, _N12129, _N12128, _N12127, _N12126, _N12125, _N12124, _N12123, _N12122, _N12121, _N12120, _N12119, _N12118, _N12117, _N12116, _N12115, _N12114, P[14], P[13], P[12], P[11], P[10], P[9], P[8], P[7], _N12105, _N12104, _N12103, _N12102, _N12101, _N12100, _N12099}), + .P ({_N12148, _N12147, _N12146, _N12145, _N12144, _N12143, _N12142, _N12141, _N12140, _N12139, _N12138, _N12137, _N12136, _N12135, _N12134, _N12133, _N12132, _N12131, _N12130, _N12129, _N12128, _N12127, _N12126, _N12125, _N12124, _N12123, _N12122, _N12121, _N12120, _N12119, _N12118, _N12117, _N12116, P[14], P[13], P[12], P[11], P[10], P[9], P[8], P[7], _N12107, _N12106, _N12105, _N12104, _N12103, _N12102, _N12101}), .CPI (), .CXBI (), .CXI (), @@ -299370,15 +298829,13 @@ module mult_fra0_unq12 input CLK, output [15:0] P ); - wire _N12147; - wire _N12148; wire _N12149; wire _N12150; wire _N12151; wire _N12152; wire _N12153; - wire _N12161; - wire _N12162; + wire _N12154; + wire _N12155; wire _N12163; wire _N12164; wire _N12165; @@ -299411,6 +298868,8 @@ module mult_fra0_unq12 wire _N12192; wire _N12193; wire _N12194; + wire _N12195; + wire _N12196; wire \N2_CPO[0]_floating ; wire \N2_CPO[1]_floating ; wire \N2_CPO[2]_floating ; @@ -299524,7 +298983,7 @@ module mult_fra0_unq12 .CPO (), .CXBO (), .CXO (), - .P ({_N12194, _N12193, _N12192, _N12191, _N12190, _N12189, _N12188, _N12187, _N12186, _N12185, _N12184, _N12183, _N12182, _N12181, _N12180, _N12179, _N12178, _N12177, _N12176, _N12175, _N12174, _N12173, _N12172, _N12171, _N12170, _N12169, _N12168, _N12167, _N12166, _N12165, _N12164, _N12163, _N12162, _N12161, P[13], P[12], P[11], P[10], P[9], P[8], P[7], _N12153, _N12152, _N12151, _N12150, _N12149, _N12148, _N12147}), + .P ({_N12196, _N12195, _N12194, _N12193, _N12192, _N12191, _N12190, _N12189, _N12188, _N12187, _N12186, _N12185, _N12184, _N12183, _N12182, _N12181, _N12180, _N12179, _N12178, _N12177, _N12176, _N12175, _N12174, _N12173, _N12172, _N12171, _N12170, _N12169, _N12168, _N12167, _N12166, _N12165, _N12164, _N12163, P[13], P[12], P[11], P[10], P[9], P[8], P[7], _N12155, _N12154, _N12153, _N12152, _N12151, _N12150, _N12149}), .CPI (), .CXBI (), .CXI (), @@ -299567,8 +299026,6 @@ module mult_image_ip input [14:0] \u_zoom_image/mult_image0[5] , input [31:0] \u_zoom_image/rd_data , input CLK, - input _N13107, - input _N13108, input _N13109, input _N13110, input _N13111, @@ -299603,10 +299060,10 @@ module mult_image_ip input _N13140, input _N13141, input _N13142, + input _N13143, + input _N13144, output [15:0] \u_zoom_image/mult_image1[2] ); - wire _N12831; - wire _N12832; wire _N12833; wire _N12834; wire _N12835; @@ -299641,6 +299098,8 @@ module mult_image_ip wire _N12864; wire _N12865; wire _N12866; + wire _N12867; + wire _N12868; wire \N2_CPO[0]_floating ; wire \N2_CPO[1]_floating ; wire \N2_CPO[2]_floating ; @@ -299754,8 +299213,8 @@ module mult_image_ip .CPO (), .CXBO (), .CXO (), - .P ({_N12866, _N12865, _N12864, _N12863, _N12862, _N12861, _N12860, _N12859, _N12858, _N12857, _N12856, _N12855, _N12854, _N12853, _N12852, _N12851, _N12850, _N12849, _N12848, _N12847, _N12846, _N12845, _N12844, _N12843, _N12842, _N12841, _N12840, _N12839, _N12838, _N12837, _N12836, _N12835, _N12834, _N12833, _N12832, _N12831, \u_zoom_image/mult_image1[2] [11] , \u_zoom_image/mult_image1[2] [10] , \u_zoom_image/mult_image1[2] [9] , \u_zoom_image/mult_image1[2] [8] , \u_zoom_image/mult_image1[2] [7] , \u_zoom_image/mult_image1[2] [6] , \u_zoom_image/mult_image1[2] [5] , \u_zoom_image/mult_image1[2] [4] , \u_zoom_image/mult_image1[2] [3] , \u_zoom_image/mult_image1[2] [2] , \u_zoom_image/mult_image1[2] [1] , \u_zoom_image/mult_image1[2] [0] }), - .CPI ({_N13142, _N13141, _N13140, _N13139, _N13138, _N13137, _N13136, _N13135, _N13134, _N13133, _N13132, _N13131, _N13130, _N13129, _N13128, _N13127, _N13126, _N13125, _N13124, _N13123, _N13122, _N13121, _N13120, _N13119, _N13118, _N13117, _N13116, _N13115, _N13114, _N13113, _N13112, _N13111, _N13110, _N13109, _N13108, _N13107, \u_zoom_image/mult_image0[5] [11] , \u_zoom_image/mult_image0[5] [10] , \u_zoom_image/mult_image0[5] [9] , \u_zoom_image/mult_image0[5] [8] , \u_zoom_image/mult_image0[5] [7] , \u_zoom_image/mult_image0[5] [6] , \u_zoom_image/mult_image0[5] [5] , \u_zoom_image/mult_image0[5] [4] , \u_zoom_image/mult_image0[5] [3] , \u_zoom_image/mult_image0[5] [2] , \u_zoom_image/mult_image0[5] [1] , \u_zoom_image/mult_image0[5] [0] }), + .P ({_N12868, _N12867, _N12866, _N12865, _N12864, _N12863, _N12862, _N12861, _N12860, _N12859, _N12858, _N12857, _N12856, _N12855, _N12854, _N12853, _N12852, _N12851, _N12850, _N12849, _N12848, _N12847, _N12846, _N12845, _N12844, _N12843, _N12842, _N12841, _N12840, _N12839, _N12838, _N12837, _N12836, _N12835, _N12834, _N12833, \u_zoom_image/mult_image1[2] [11] , \u_zoom_image/mult_image1[2] [10] , \u_zoom_image/mult_image1[2] [9] , \u_zoom_image/mult_image1[2] [8] , \u_zoom_image/mult_image1[2] [7] , \u_zoom_image/mult_image1[2] [6] , \u_zoom_image/mult_image1[2] [5] , \u_zoom_image/mult_image1[2] [4] , \u_zoom_image/mult_image1[2] [3] , \u_zoom_image/mult_image1[2] [2] , \u_zoom_image/mult_image1[2] [1] , \u_zoom_image/mult_image1[2] [0] }), + .CPI ({_N13144, _N13143, _N13142, _N13141, _N13140, _N13139, _N13138, _N13137, _N13136, _N13135, _N13134, _N13133, _N13132, _N13131, _N13130, _N13129, _N13128, _N13127, _N13126, _N13125, _N13124, _N13123, _N13122, _N13121, _N13120, _N13119, _N13118, _N13117, _N13116, _N13115, _N13114, _N13113, _N13112, _N13111, _N13110, _N13109, \u_zoom_image/mult_image0[5] [11] , \u_zoom_image/mult_image0[5] [10] , \u_zoom_image/mult_image0[5] [9] , \u_zoom_image/mult_image0[5] [8] , \u_zoom_image/mult_image0[5] [7] , \u_zoom_image/mult_image0[5] [6] , \u_zoom_image/mult_image0[5] [5] , \u_zoom_image/mult_image0[5] [4] , \u_zoom_image/mult_image0[5] [3] , \u_zoom_image/mult_image0[5] [2] , \u_zoom_image/mult_image0[5] [1] , \u_zoom_image/mult_image0[5] [0] }), .CXBI (), .CXI (), .MODEY ({1'b0, 1'b0, 1'b0}), @@ -299797,8 +299256,6 @@ module mult_image_ip_unq24 input [14:0] \u_zoom_image/mult_image0_0[5] , input [31:0] \u_zoom_image/rd_data_0 , input CLK, - input _N13143, - input _N13144, input _N13145, input _N13146, input _N13147, @@ -299833,10 +299290,10 @@ module mult_image_ip_unq24 input _N13176, input _N13177, input _N13178, + input _N13179, + input _N13180, output [15:0] \u_zoom_image/mult_image1_0[2] ); - wire _N12879; - wire _N12880; wire _N12881; wire _N12882; wire _N12883; @@ -299871,6 +299328,8 @@ module mult_image_ip_unq24 wire _N12912; wire _N12913; wire _N12914; + wire _N12915; + wire _N12916; wire \N2_CPO[0]_floating ; wire \N2_CPO[1]_floating ; wire \N2_CPO[2]_floating ; @@ -299984,8 +299443,8 @@ module mult_image_ip_unq24 .CPO (), .CXBO (), .CXO (), - .P ({_N12914, _N12913, _N12912, _N12911, _N12910, _N12909, _N12908, _N12907, _N12906, _N12905, _N12904, _N12903, _N12902, _N12901, _N12900, _N12899, _N12898, _N12897, _N12896, _N12895, _N12894, _N12893, _N12892, _N12891, _N12890, _N12889, _N12888, _N12887, _N12886, _N12885, _N12884, _N12883, _N12882, _N12881, _N12880, _N12879, \u_zoom_image/mult_image1_0[2] [11] , \u_zoom_image/mult_image1_0[2] [10] , \u_zoom_image/mult_image1_0[2] [9] , \u_zoom_image/mult_image1_0[2] [8] , \u_zoom_image/mult_image1_0[2] [7] , \u_zoom_image/mult_image1_0[2] [6] , \u_zoom_image/mult_image1_0[2] [5] , \u_zoom_image/mult_image1_0[2] [4] , \u_zoom_image/mult_image1_0[2] [3] , \u_zoom_image/mult_image1_0[2] [2] , \u_zoom_image/mult_image1_0[2] [1] , \u_zoom_image/mult_image1_0[2] [0] }), - .CPI ({_N13178, _N13177, _N13176, _N13175, _N13174, _N13173, _N13172, _N13171, _N13170, _N13169, _N13168, _N13167, _N13166, _N13165, _N13164, _N13163, _N13162, _N13161, _N13160, _N13159, _N13158, _N13157, _N13156, _N13155, _N13154, _N13153, _N13152, _N13151, _N13150, _N13149, _N13148, _N13147, _N13146, _N13145, _N13144, _N13143, \u_zoom_image/mult_image0_0[5] [11] , \u_zoom_image/mult_image0_0[5] [10] , \u_zoom_image/mult_image0_0[5] [9] , \u_zoom_image/mult_image0_0[5] [8] , \u_zoom_image/mult_image0_0[5] [7] , \u_zoom_image/mult_image0_0[5] [6] , \u_zoom_image/mult_image0_0[5] [5] , \u_zoom_image/mult_image0_0[5] [4] , \u_zoom_image/mult_image0_0[5] [3] , \u_zoom_image/mult_image0_0[5] [2] , \u_zoom_image/mult_image0_0[5] [1] , \u_zoom_image/mult_image0_0[5] [0] }), + .P ({_N12916, _N12915, _N12914, _N12913, _N12912, _N12911, _N12910, _N12909, _N12908, _N12907, _N12906, _N12905, _N12904, _N12903, _N12902, _N12901, _N12900, _N12899, _N12898, _N12897, _N12896, _N12895, _N12894, _N12893, _N12892, _N12891, _N12890, _N12889, _N12888, _N12887, _N12886, _N12885, _N12884, _N12883, _N12882, _N12881, \u_zoom_image/mult_image1_0[2] [11] , \u_zoom_image/mult_image1_0[2] [10] , \u_zoom_image/mult_image1_0[2] [9] , \u_zoom_image/mult_image1_0[2] [8] , \u_zoom_image/mult_image1_0[2] [7] , \u_zoom_image/mult_image1_0[2] [6] , \u_zoom_image/mult_image1_0[2] [5] , \u_zoom_image/mult_image1_0[2] [4] , \u_zoom_image/mult_image1_0[2] [3] , \u_zoom_image/mult_image1_0[2] [2] , \u_zoom_image/mult_image1_0[2] [1] , \u_zoom_image/mult_image1_0[2] [0] }), + .CPI ({_N13180, _N13179, _N13178, _N13177, _N13176, _N13175, _N13174, _N13173, _N13172, _N13171, _N13170, _N13169, _N13168, _N13167, _N13166, _N13165, _N13164, _N13163, _N13162, _N13161, _N13160, _N13159, _N13158, _N13157, _N13156, _N13155, _N13154, _N13153, _N13152, _N13151, _N13150, _N13149, _N13148, _N13147, _N13146, _N13145, \u_zoom_image/mult_image0_0[5] [11] , \u_zoom_image/mult_image0_0[5] [10] , \u_zoom_image/mult_image0_0[5] [9] , \u_zoom_image/mult_image0_0[5] [8] , \u_zoom_image/mult_image0_0[5] [7] , \u_zoom_image/mult_image0_0[5] [6] , \u_zoom_image/mult_image0_0[5] [5] , \u_zoom_image/mult_image0_0[5] [4] , \u_zoom_image/mult_image0_0[5] [3] , \u_zoom_image/mult_image0_0[5] [2] , \u_zoom_image/mult_image0_0[5] [1] , \u_zoom_image/mult_image0_0[5] [0] }), .CXBI (), .CXI (), .MODEY ({1'b0, 1'b0, 1'b0}), @@ -300027,8 +299486,6 @@ module mult_image_ip_unq26 input [31:0] \u_zoom_image/rd_data , input CLK, output [14:0] P, - output _N13107, - output _N13108, output _N13109, output _N13110, output _N13111, @@ -300062,10 +299519,10 @@ module mult_image_ip_unq26 output _N13139, output _N13140, output _N13141, - output _N13142 + output _N13142, + output _N13143, + output _N13144 ); - wire _N12303; - wire _N12304; wire _N12305; wire _N12306; wire _N12307; @@ -300100,6 +299557,8 @@ module mult_image_ip_unq26 wire _N12336; wire _N12337; wire _N12338; + wire _N12339; + wire _N12340; wire \N2_CXBO[0]_floating ; wire \N2_CXBO[1]_floating ; wire \N2_CXBO[2]_floating ; @@ -300174,10 +299633,10 @@ module mult_image_ip_unq26 .USE_POSTADD(0), .Z_INIT(48'b000000000000000000000000000000000000000000000000)) N2 ( - .CPO ({_N13142, _N13141, _N13140, _N13139, _N13138, _N13137, _N13136, _N13135, _N13134, _N13133, _N13132, _N13131, _N13130, _N13129, _N13128, _N13127, _N13126, _N13125, _N13124, _N13123, _N13122, _N13121, _N13120, _N13119, _N13118, _N13117, _N13116, _N13115, _N13114, _N13113, _N13112, _N13111, _N13110, _N13109, _N13108, _N13107, P[11], P[10], P[9], P[8], P[7], P[6], P[5], P[4], P[3], P[2], P[1], P[0]}), + .CPO ({_N13144, _N13143, _N13142, _N13141, _N13140, _N13139, _N13138, _N13137, _N13136, _N13135, _N13134, _N13133, _N13132, _N13131, _N13130, _N13129, _N13128, _N13127, _N13126, _N13125, _N13124, _N13123, _N13122, _N13121, _N13120, _N13119, _N13118, _N13117, _N13116, _N13115, _N13114, _N13113, _N13112, _N13111, _N13110, _N13109, P[11], P[10], P[9], P[8], P[7], P[6], P[5], P[4], P[3], P[2], P[1], P[0]}), .CXBO (), .CXO (), - .P ({_N12338, _N12337, _N12336, _N12335, _N12334, _N12333, _N12332, _N12331, _N12330, _N12329, _N12328, _N12327, _N12326, _N12325, _N12324, _N12323, _N12322, _N12321, _N12320, _N12319, _N12318, _N12317, _N12316, _N12315, _N12314, _N12313, _N12312, _N12311, _N12310, _N12309, _N12308, _N12307, _N12306, _N12305, _N12304, _N12303, \N2_P[11]_floating , \N2_P[10]_floating , \N2_P[9]_floating , \N2_P[8]_floating , \N2_P[7]_floating , \N2_P[6]_floating , \N2_P[5]_floating , \N2_P[4]_floating , \N2_P[3]_floating , \N2_P[2]_floating , \N2_P[1]_floating , \N2_P[0]_floating }), + .P ({_N12340, _N12339, _N12338, _N12337, _N12336, _N12335, _N12334, _N12333, _N12332, _N12331, _N12330, _N12329, _N12328, _N12327, _N12326, _N12325, _N12324, _N12323, _N12322, _N12321, _N12320, _N12319, _N12318, _N12317, _N12316, _N12315, _N12314, _N12313, _N12312, _N12311, _N12310, _N12309, _N12308, _N12307, _N12306, _N12305, \N2_P[11]_floating , \N2_P[10]_floating , \N2_P[9]_floating , \N2_P[8]_floating , \N2_P[7]_floating , \N2_P[6]_floating , \N2_P[5]_floating , \N2_P[4]_floating , \N2_P[3]_floating , \N2_P[2]_floating , \N2_P[1]_floating , \N2_P[0]_floating }), .CPI (), .CXBI (), .CXI (), @@ -300220,8 +299679,6 @@ module mult_image_ip_unq28 input [31:0] \u_zoom_image/rd_data_0 , input CLK, output [14:0] P, - output _N13143, - output _N13144, output _N13145, output _N13146, output _N13147, @@ -300255,10 +299712,10 @@ module mult_image_ip_unq28 output _N13175, output _N13176, output _N13177, - output _N13178 + output _N13178, + output _N13179, + output _N13180 ); - wire _N12351; - wire _N12352; wire _N12353; wire _N12354; wire _N12355; @@ -300293,6 +299750,8 @@ module mult_image_ip_unq28 wire _N12384; wire _N12385; wire _N12386; + wire _N12387; + wire _N12388; wire \N2_CXBO[0]_floating ; wire \N2_CXBO[1]_floating ; wire \N2_CXBO[2]_floating ; @@ -300367,10 +299826,10 @@ module mult_image_ip_unq28 .USE_POSTADD(0), .Z_INIT(48'b000000000000000000000000000000000000000000000000)) N2 ( - .CPO ({_N13178, _N13177, _N13176, _N13175, _N13174, _N13173, _N13172, _N13171, _N13170, _N13169, _N13168, _N13167, _N13166, _N13165, _N13164, _N13163, _N13162, _N13161, _N13160, _N13159, _N13158, _N13157, _N13156, _N13155, _N13154, _N13153, _N13152, _N13151, _N13150, _N13149, _N13148, _N13147, _N13146, _N13145, _N13144, _N13143, P[11], P[10], P[9], P[8], P[7], P[6], P[5], P[4], P[3], P[2], P[1], P[0]}), + .CPO ({_N13180, _N13179, _N13178, _N13177, _N13176, _N13175, _N13174, _N13173, _N13172, _N13171, _N13170, _N13169, _N13168, _N13167, _N13166, _N13165, _N13164, _N13163, _N13162, _N13161, _N13160, _N13159, _N13158, _N13157, _N13156, _N13155, _N13154, _N13153, _N13152, _N13151, _N13150, _N13149, _N13148, _N13147, _N13146, _N13145, P[11], P[10], P[9], P[8], P[7], P[6], P[5], P[4], P[3], P[2], P[1], P[0]}), .CXBO (), .CXO (), - .P ({_N12386, _N12385, _N12384, _N12383, _N12382, _N12381, _N12380, _N12379, _N12378, _N12377, _N12376, _N12375, _N12374, _N12373, _N12372, _N12371, _N12370, _N12369, _N12368, _N12367, _N12366, _N12365, _N12364, _N12363, _N12362, _N12361, _N12360, _N12359, _N12358, _N12357, _N12356, _N12355, _N12354, _N12353, _N12352, _N12351, \N2_P[11]_floating , \N2_P[10]_floating , \N2_P[9]_floating , \N2_P[8]_floating , \N2_P[7]_floating , \N2_P[6]_floating , \N2_P[5]_floating , \N2_P[4]_floating , \N2_P[3]_floating , \N2_P[2]_floating , \N2_P[1]_floating , \N2_P[0]_floating }), + .P ({_N12388, _N12387, _N12386, _N12385, _N12384, _N12383, _N12382, _N12381, _N12380, _N12379, _N12378, _N12377, _N12376, _N12375, _N12374, _N12373, _N12372, _N12371, _N12370, _N12369, _N12368, _N12367, _N12366, _N12365, _N12364, _N12363, _N12362, _N12361, _N12360, _N12359, _N12358, _N12357, _N12356, _N12355, _N12354, _N12353, \N2_P[11]_floating , \N2_P[10]_floating , \N2_P[9]_floating , \N2_P[8]_floating , \N2_P[7]_floating , \N2_P[6]_floating , \N2_P[5]_floating , \N2_P[4]_floating , \N2_P[3]_floating , \N2_P[2]_floating , \N2_P[1]_floating , \N2_P[0]_floating }), .CPI (), .CXBI (), .CXI (), @@ -300413,8 +299872,6 @@ module mult_image_ip_unq30 input [31:0] \u_zoom_image/rd_data , input CLK, output [14:0] P, - output _N13036, - output _N13037, output _N13038, output _N13039, output _N13040, @@ -300447,10 +299904,10 @@ module mult_image_ip_unq30 output _N13067, output _N13068, output _N13069, - output _N13070 + output _N13070, + output _N13071, + output _N13072 ); - wire _N12400; - wire _N12401; wire _N12402; wire _N12403; wire _N12404; @@ -300484,6 +299941,8 @@ module mult_image_ip_unq30 wire _N12432; wire _N12433; wire _N12434; + wire _N12435; + wire _N12436; wire \N2_CXBO[0]_floating ; wire \N2_CXBO[1]_floating ; wire \N2_CXBO[2]_floating ; @@ -300559,10 +300018,10 @@ module mult_image_ip_unq30 .USE_POSTADD(0), .Z_INIT(48'b000000000000000000000000000000000000000000000000)) N2 ( - .CPO ({_N13070, _N13069, _N13068, _N13067, _N13066, _N13065, _N13064, _N13063, _N13062, _N13061, _N13060, _N13059, _N13058, _N13057, _N13056, _N13055, _N13054, _N13053, _N13052, _N13051, _N13050, _N13049, _N13048, _N13047, _N13046, _N13045, _N13044, _N13043, _N13042, _N13041, _N13040, _N13039, _N13038, _N13037, _N13036, P[12], P[11], P[10], P[9], P[8], P[7], P[6], P[5], P[4], P[3], P[2], P[1], P[0]}), + .CPO ({_N13072, _N13071, _N13070, _N13069, _N13068, _N13067, _N13066, _N13065, _N13064, _N13063, _N13062, _N13061, _N13060, _N13059, _N13058, _N13057, _N13056, _N13055, _N13054, _N13053, _N13052, _N13051, _N13050, _N13049, _N13048, _N13047, _N13046, _N13045, _N13044, _N13043, _N13042, _N13041, _N13040, _N13039, _N13038, P[12], P[11], P[10], P[9], P[8], P[7], P[6], P[5], P[4], P[3], P[2], P[1], P[0]}), .CXBO (), .CXO (), - .P ({_N12434, _N12433, _N12432, _N12431, _N12430, _N12429, _N12428, _N12427, _N12426, _N12425, _N12424, _N12423, _N12422, _N12421, _N12420, _N12419, _N12418, _N12417, _N12416, _N12415, _N12414, _N12413, _N12412, _N12411, _N12410, _N12409, _N12408, _N12407, _N12406, _N12405, _N12404, _N12403, _N12402, _N12401, _N12400, \N2_P[12]_floating , \N2_P[11]_floating , \N2_P[10]_floating , \N2_P[9]_floating , \N2_P[8]_floating , \N2_P[7]_floating , \N2_P[6]_floating , \N2_P[5]_floating , \N2_P[4]_floating , \N2_P[3]_floating , \N2_P[2]_floating , \N2_P[1]_floating , \N2_P[0]_floating }), + .P ({_N12436, _N12435, _N12434, _N12433, _N12432, _N12431, _N12430, _N12429, _N12428, _N12427, _N12426, _N12425, _N12424, _N12423, _N12422, _N12421, _N12420, _N12419, _N12418, _N12417, _N12416, _N12415, _N12414, _N12413, _N12412, _N12411, _N12410, _N12409, _N12408, _N12407, _N12406, _N12405, _N12404, _N12403, _N12402, \N2_P[12]_floating , \N2_P[11]_floating , \N2_P[10]_floating , \N2_P[9]_floating , \N2_P[8]_floating , \N2_P[7]_floating , \N2_P[6]_floating , \N2_P[5]_floating , \N2_P[4]_floating , \N2_P[3]_floating , \N2_P[2]_floating , \N2_P[1]_floating , \N2_P[0]_floating }), .CPI (), .CXBI (), .CXI (), @@ -300605,8 +300064,6 @@ module mult_image_ip_unq32 input [31:0] \u_zoom_image/rd_data_0 , input CLK, output [14:0] P, - output _N13001, - output _N13002, output _N13003, output _N13004, output _N13005, @@ -300639,10 +300096,10 @@ module mult_image_ip_unq32 output _N13032, output _N13033, output _N13034, - output _N13035 + output _N13035, + output _N13036, + output _N13037 ); - wire _N12448; - wire _N12449; wire _N12450; wire _N12451; wire _N12452; @@ -300676,6 +300133,8 @@ module mult_image_ip_unq32 wire _N12480; wire _N12481; wire _N12482; + wire _N12483; + wire _N12484; wire \N2_CXBO[0]_floating ; wire \N2_CXBO[1]_floating ; wire \N2_CXBO[2]_floating ; @@ -300751,10 +300210,10 @@ module mult_image_ip_unq32 .USE_POSTADD(0), .Z_INIT(48'b000000000000000000000000000000000000000000000000)) N2 ( - .CPO ({_N13035, _N13034, _N13033, _N13032, _N13031, _N13030, _N13029, _N13028, _N13027, _N13026, _N13025, _N13024, _N13023, _N13022, _N13021, _N13020, _N13019, _N13018, _N13017, _N13016, _N13015, _N13014, _N13013, _N13012, _N13011, _N13010, _N13009, _N13008, _N13007, _N13006, _N13005, _N13004, _N13003, _N13002, _N13001, P[12], P[11], P[10], P[9], P[8], P[7], P[6], P[5], P[4], P[3], P[2], P[1], P[0]}), + .CPO ({_N13037, _N13036, _N13035, _N13034, _N13033, _N13032, _N13031, _N13030, _N13029, _N13028, _N13027, _N13026, _N13025, _N13024, _N13023, _N13022, _N13021, _N13020, _N13019, _N13018, _N13017, _N13016, _N13015, _N13014, _N13013, _N13012, _N13011, _N13010, _N13009, _N13008, _N13007, _N13006, _N13005, _N13004, _N13003, P[12], P[11], P[10], P[9], P[8], P[7], P[6], P[5], P[4], P[3], P[2], P[1], P[0]}), .CXBO (), .CXO (), - .P ({_N12482, _N12481, _N12480, _N12479, _N12478, _N12477, _N12476, _N12475, _N12474, _N12473, _N12472, _N12471, _N12470, _N12469, _N12468, _N12467, _N12466, _N12465, _N12464, _N12463, _N12462, _N12461, _N12460, _N12459, _N12458, _N12457, _N12456, _N12455, _N12454, _N12453, _N12452, _N12451, _N12450, _N12449, _N12448, \N2_P[12]_floating , \N2_P[11]_floating , \N2_P[10]_floating , \N2_P[9]_floating , \N2_P[8]_floating , \N2_P[7]_floating , \N2_P[6]_floating , \N2_P[5]_floating , \N2_P[4]_floating , \N2_P[3]_floating , \N2_P[2]_floating , \N2_P[1]_floating , \N2_P[0]_floating }), + .P ({_N12484, _N12483, _N12482, _N12481, _N12480, _N12479, _N12478, _N12477, _N12476, _N12475, _N12474, _N12473, _N12472, _N12471, _N12470, _N12469, _N12468, _N12467, _N12466, _N12465, _N12464, _N12463, _N12462, _N12461, _N12460, _N12459, _N12458, _N12457, _N12456, _N12455, _N12454, _N12453, _N12452, _N12451, _N12450, \N2_P[12]_floating , \N2_P[11]_floating , \N2_P[10]_floating , \N2_P[9]_floating , \N2_P[8]_floating , \N2_P[7]_floating , \N2_P[6]_floating , \N2_P[5]_floating , \N2_P[4]_floating , \N2_P[3]_floating , \N2_P[2]_floating , \N2_P[1]_floating , \N2_P[0]_floating }), .CPI (), .CXBI (), .CXI (), @@ -300797,8 +300256,6 @@ module mult_image_ip_unq34 input [14:0] \u_zoom_image/mult_image0[2] , input [31:0] \u_zoom_image/rd_data , input CLK, - input _N13036, - input _N13037, input _N13038, input _N13039, input _N13040, @@ -300832,10 +300289,10 @@ module mult_image_ip_unq34 input _N13068, input _N13069, input _N13070, + input _N13071, + input _N13072, output [15:0] \u_zoom_image/mult_image1[1] ); - wire _N12688; - wire _N12689; wire _N12690; wire _N12691; wire _N12692; @@ -300869,6 +300326,8 @@ module mult_image_ip_unq34 wire _N12720; wire _N12721; wire _N12722; + wire _N12723; + wire _N12724; wire \N2_CPO[0]_floating ; wire \N2_CPO[1]_floating ; wire \N2_CPO[2]_floating ; @@ -300982,8 +300441,8 @@ module mult_image_ip_unq34 .CPO (), .CXBO (), .CXO (), - .P ({_N12722, _N12721, _N12720, _N12719, _N12718, _N12717, _N12716, _N12715, _N12714, _N12713, _N12712, _N12711, _N12710, _N12709, _N12708, _N12707, _N12706, _N12705, _N12704, _N12703, _N12702, _N12701, _N12700, _N12699, _N12698, _N12697, _N12696, _N12695, _N12694, _N12693, _N12692, _N12691, _N12690, _N12689, _N12688, \u_zoom_image/mult_image1[1] [12] , \u_zoom_image/mult_image1[1] [11] , \u_zoom_image/mult_image1[1] [10] , \u_zoom_image/mult_image1[1] [9] , \u_zoom_image/mult_image1[1] [8] , \u_zoom_image/mult_image1[1] [7] , \u_zoom_image/mult_image1[1] [6] , \u_zoom_image/mult_image1[1] [5] , \u_zoom_image/mult_image1[1] [4] , \u_zoom_image/mult_image1[1] [3] , \u_zoom_image/mult_image1[1] [2] , \u_zoom_image/mult_image1[1] [1] , \u_zoom_image/mult_image1[1] [0] }), - .CPI ({_N13070, _N13069, _N13068, _N13067, _N13066, _N13065, _N13064, _N13063, _N13062, _N13061, _N13060, _N13059, _N13058, _N13057, _N13056, _N13055, _N13054, _N13053, _N13052, _N13051, _N13050, _N13049, _N13048, _N13047, _N13046, _N13045, _N13044, _N13043, _N13042, _N13041, _N13040, _N13039, _N13038, _N13037, _N13036, \u_zoom_image/mult_image0[2] [12] , \u_zoom_image/mult_image0[2] [11] , \u_zoom_image/mult_image0[2] [10] , \u_zoom_image/mult_image0[2] [9] , \u_zoom_image/mult_image0[2] [8] , \u_zoom_image/mult_image0[2] [7] , \u_zoom_image/mult_image0[2] [6] , \u_zoom_image/mult_image0[2] [5] , \u_zoom_image/mult_image0[2] [4] , \u_zoom_image/mult_image0[2] [3] , \u_zoom_image/mult_image0[2] [2] , \u_zoom_image/mult_image0[2] [1] , \u_zoom_image/mult_image0[2] [0] }), + .P ({_N12724, _N12723, _N12722, _N12721, _N12720, _N12719, _N12718, _N12717, _N12716, _N12715, _N12714, _N12713, _N12712, _N12711, _N12710, _N12709, _N12708, _N12707, _N12706, _N12705, _N12704, _N12703, _N12702, _N12701, _N12700, _N12699, _N12698, _N12697, _N12696, _N12695, _N12694, _N12693, _N12692, _N12691, _N12690, \u_zoom_image/mult_image1[1] [12] , \u_zoom_image/mult_image1[1] [11] , \u_zoom_image/mult_image1[1] [10] , \u_zoom_image/mult_image1[1] [9] , \u_zoom_image/mult_image1[1] [8] , \u_zoom_image/mult_image1[1] [7] , \u_zoom_image/mult_image1[1] [6] , \u_zoom_image/mult_image1[1] [5] , \u_zoom_image/mult_image1[1] [4] , \u_zoom_image/mult_image1[1] [3] , \u_zoom_image/mult_image1[1] [2] , \u_zoom_image/mult_image1[1] [1] , \u_zoom_image/mult_image1[1] [0] }), + .CPI ({_N13072, _N13071, _N13070, _N13069, _N13068, _N13067, _N13066, _N13065, _N13064, _N13063, _N13062, _N13061, _N13060, _N13059, _N13058, _N13057, _N13056, _N13055, _N13054, _N13053, _N13052, _N13051, _N13050, _N13049, _N13048, _N13047, _N13046, _N13045, _N13044, _N13043, _N13042, _N13041, _N13040, _N13039, _N13038, \u_zoom_image/mult_image0[2] [12] , \u_zoom_image/mult_image0[2] [11] , \u_zoom_image/mult_image0[2] [10] , \u_zoom_image/mult_image0[2] [9] , \u_zoom_image/mult_image0[2] [8] , \u_zoom_image/mult_image0[2] [7] , \u_zoom_image/mult_image0[2] [6] , \u_zoom_image/mult_image0[2] [5] , \u_zoom_image/mult_image0[2] [4] , \u_zoom_image/mult_image0[2] [3] , \u_zoom_image/mult_image0[2] [2] , \u_zoom_image/mult_image0[2] [1] , \u_zoom_image/mult_image0[2] [0] }), .CXBI (), .CXI (), .MODEY ({1'b0, 1'b0, 1'b0}), @@ -301025,8 +300484,6 @@ module mult_image_ip_unq36 input [14:0] \u_zoom_image/mult_image0_0[2] , input [31:0] \u_zoom_image/rd_data_0 , input CLK, - input _N13001, - input _N13002, input _N13003, input _N13004, input _N13005, @@ -301060,10 +300517,10 @@ module mult_image_ip_unq36 input _N13033, input _N13034, input _N13035, + input _N13036, + input _N13037, output [15:0] \u_zoom_image/mult_image1_0[1] ); - wire _N12640; - wire _N12641; wire _N12642; wire _N12643; wire _N12644; @@ -301097,6 +300554,8 @@ module mult_image_ip_unq36 wire _N12672; wire _N12673; wire _N12674; + wire _N12675; + wire _N12676; wire \N2_CPO[0]_floating ; wire \N2_CPO[1]_floating ; wire \N2_CPO[2]_floating ; @@ -301210,8 +300669,8 @@ module mult_image_ip_unq36 .CPO (), .CXBO (), .CXO (), - .P ({_N12674, _N12673, _N12672, _N12671, _N12670, _N12669, _N12668, _N12667, _N12666, _N12665, _N12664, _N12663, _N12662, _N12661, _N12660, _N12659, _N12658, _N12657, _N12656, _N12655, _N12654, _N12653, _N12652, _N12651, _N12650, _N12649, _N12648, _N12647, _N12646, _N12645, _N12644, _N12643, _N12642, _N12641, _N12640, \u_zoom_image/mult_image1_0[1] [12] , \u_zoom_image/mult_image1_0[1] [11] , \u_zoom_image/mult_image1_0[1] [10] , \u_zoom_image/mult_image1_0[1] [9] , \u_zoom_image/mult_image1_0[1] [8] , \u_zoom_image/mult_image1_0[1] [7] , \u_zoom_image/mult_image1_0[1] [6] , \u_zoom_image/mult_image1_0[1] [5] , \u_zoom_image/mult_image1_0[1] [4] , \u_zoom_image/mult_image1_0[1] [3] , \u_zoom_image/mult_image1_0[1] [2] , \u_zoom_image/mult_image1_0[1] [1] , \u_zoom_image/mult_image1_0[1] [0] }), - .CPI ({_N13035, _N13034, _N13033, _N13032, _N13031, _N13030, _N13029, _N13028, _N13027, _N13026, _N13025, _N13024, _N13023, _N13022, _N13021, _N13020, _N13019, _N13018, _N13017, _N13016, _N13015, _N13014, _N13013, _N13012, _N13011, _N13010, _N13009, _N13008, _N13007, _N13006, _N13005, _N13004, _N13003, _N13002, _N13001, \u_zoom_image/mult_image0_0[2] [12] , \u_zoom_image/mult_image0_0[2] [11] , \u_zoom_image/mult_image0_0[2] [10] , \u_zoom_image/mult_image0_0[2] [9] , \u_zoom_image/mult_image0_0[2] [8] , \u_zoom_image/mult_image0_0[2] [7] , \u_zoom_image/mult_image0_0[2] [6] , \u_zoom_image/mult_image0_0[2] [5] , \u_zoom_image/mult_image0_0[2] [4] , \u_zoom_image/mult_image0_0[2] [3] , \u_zoom_image/mult_image0_0[2] [2] , \u_zoom_image/mult_image0_0[2] [1] , \u_zoom_image/mult_image0_0[2] [0] }), + .P ({_N12676, _N12675, _N12674, _N12673, _N12672, _N12671, _N12670, _N12669, _N12668, _N12667, _N12666, _N12665, _N12664, _N12663, _N12662, _N12661, _N12660, _N12659, _N12658, _N12657, _N12656, _N12655, _N12654, _N12653, _N12652, _N12651, _N12650, _N12649, _N12648, _N12647, _N12646, _N12645, _N12644, _N12643, _N12642, \u_zoom_image/mult_image1_0[1] [12] , \u_zoom_image/mult_image1_0[1] [11] , \u_zoom_image/mult_image1_0[1] [10] , \u_zoom_image/mult_image1_0[1] [9] , \u_zoom_image/mult_image1_0[1] [8] , \u_zoom_image/mult_image1_0[1] [7] , \u_zoom_image/mult_image1_0[1] [6] , \u_zoom_image/mult_image1_0[1] [5] , \u_zoom_image/mult_image1_0[1] [4] , \u_zoom_image/mult_image1_0[1] [3] , \u_zoom_image/mult_image1_0[1] [2] , \u_zoom_image/mult_image1_0[1] [1] , \u_zoom_image/mult_image1_0[1] [0] }), + .CPI ({_N13037, _N13036, _N13035, _N13034, _N13033, _N13032, _N13031, _N13030, _N13029, _N13028, _N13027, _N13026, _N13025, _N13024, _N13023, _N13022, _N13021, _N13020, _N13019, _N13018, _N13017, _N13016, _N13015, _N13014, _N13013, _N13012, _N13011, _N13010, _N13009, _N13008, _N13007, _N13006, _N13005, _N13004, _N13003, \u_zoom_image/mult_image0_0[2] [12] , \u_zoom_image/mult_image0_0[2] [11] , \u_zoom_image/mult_image0_0[2] [10] , \u_zoom_image/mult_image0_0[2] [9] , \u_zoom_image/mult_image0_0[2] [8] , \u_zoom_image/mult_image0_0[2] [7] , \u_zoom_image/mult_image0_0[2] [6] , \u_zoom_image/mult_image0_0[2] [5] , \u_zoom_image/mult_image0_0[2] [4] , \u_zoom_image/mult_image0_0[2] [3] , \u_zoom_image/mult_image0_0[2] [2] , \u_zoom_image/mult_image0_0[2] [1] , \u_zoom_image/mult_image0_0[2] [0] }), .CXBI (), .CXI (), .MODEY ({1'b0, 1'b0, 1'b0}), @@ -301253,8 +300712,6 @@ module mult_image_ip_unq38 input [14:0] \u_zoom_image/mult_image0[1] , input [31:0] \u_zoom_image/rd_data , input CLK, - input _N12965, - input _N12966, input _N12967, input _N12968, input _N12969, @@ -301289,10 +300746,10 @@ module mult_image_ip_unq38 input _N12998, input _N12999, input _N13000, + input _N13001, + input _N13002, output [15:0] \u_zoom_image/mult_image1[0] ); - wire _N12591; - wire _N12592; wire _N12593; wire _N12594; wire _N12595; @@ -301327,6 +300784,8 @@ module mult_image_ip_unq38 wire _N12624; wire _N12625; wire _N12626; + wire _N12627; + wire _N12628; wire \N2_CPO[0]_floating ; wire \N2_CPO[1]_floating ; wire \N2_CPO[2]_floating ; @@ -301440,8 +300899,8 @@ module mult_image_ip_unq38 .CPO (), .CXBO (), .CXO (), - .P ({_N12626, _N12625, _N12624, _N12623, _N12622, _N12621, _N12620, _N12619, _N12618, _N12617, _N12616, _N12615, _N12614, _N12613, _N12612, _N12611, _N12610, _N12609, _N12608, _N12607, _N12606, _N12605, _N12604, _N12603, _N12602, _N12601, _N12600, _N12599, _N12598, _N12597, _N12596, _N12595, _N12594, _N12593, _N12592, _N12591, \u_zoom_image/mult_image1[0] [11] , \u_zoom_image/mult_image1[0] [10] , \u_zoom_image/mult_image1[0] [9] , \u_zoom_image/mult_image1[0] [8] , \u_zoom_image/mult_image1[0] [7] , \u_zoom_image/mult_image1[0] [6] , \u_zoom_image/mult_image1[0] [5] , \u_zoom_image/mult_image1[0] [4] , \u_zoom_image/mult_image1[0] [3] , \u_zoom_image/mult_image1[0] [2] , \u_zoom_image/mult_image1[0] [1] , \u_zoom_image/mult_image1[0] [0] }), - .CPI ({_N13000, _N12999, _N12998, _N12997, _N12996, _N12995, _N12994, _N12993, _N12992, _N12991, _N12990, _N12989, _N12988, _N12987, _N12986, _N12985, _N12984, _N12983, _N12982, _N12981, _N12980, _N12979, _N12978, _N12977, _N12976, _N12975, _N12974, _N12973, _N12972, _N12971, _N12970, _N12969, _N12968, _N12967, _N12966, _N12965, \u_zoom_image/mult_image0[1] [11] , \u_zoom_image/mult_image0[1] [10] , \u_zoom_image/mult_image0[1] [9] , \u_zoom_image/mult_image0[1] [8] , \u_zoom_image/mult_image0[1] [7] , \u_zoom_image/mult_image0[1] [6] , \u_zoom_image/mult_image0[1] [5] , \u_zoom_image/mult_image0[1] [4] , \u_zoom_image/mult_image0[1] [3] , \u_zoom_image/mult_image0[1] [2] , \u_zoom_image/mult_image0[1] [1] , \u_zoom_image/mult_image0[1] [0] }), + .P ({_N12628, _N12627, _N12626, _N12625, _N12624, _N12623, _N12622, _N12621, _N12620, _N12619, _N12618, _N12617, _N12616, _N12615, _N12614, _N12613, _N12612, _N12611, _N12610, _N12609, _N12608, _N12607, _N12606, _N12605, _N12604, _N12603, _N12602, _N12601, _N12600, _N12599, _N12598, _N12597, _N12596, _N12595, _N12594, _N12593, \u_zoom_image/mult_image1[0] [11] , \u_zoom_image/mult_image1[0] [10] , \u_zoom_image/mult_image1[0] [9] , \u_zoom_image/mult_image1[0] [8] , \u_zoom_image/mult_image1[0] [7] , \u_zoom_image/mult_image1[0] [6] , \u_zoom_image/mult_image1[0] [5] , \u_zoom_image/mult_image1[0] [4] , \u_zoom_image/mult_image1[0] [3] , \u_zoom_image/mult_image1[0] [2] , \u_zoom_image/mult_image1[0] [1] , \u_zoom_image/mult_image1[0] [0] }), + .CPI ({_N13002, _N13001, _N13000, _N12999, _N12998, _N12997, _N12996, _N12995, _N12994, _N12993, _N12992, _N12991, _N12990, _N12989, _N12988, _N12987, _N12986, _N12985, _N12984, _N12983, _N12982, _N12981, _N12980, _N12979, _N12978, _N12977, _N12976, _N12975, _N12974, _N12973, _N12972, _N12971, _N12970, _N12969, _N12968, _N12967, \u_zoom_image/mult_image0[1] [11] , \u_zoom_image/mult_image0[1] [10] , \u_zoom_image/mult_image0[1] [9] , \u_zoom_image/mult_image0[1] [8] , \u_zoom_image/mult_image0[1] [7] , \u_zoom_image/mult_image0[1] [6] , \u_zoom_image/mult_image0[1] [5] , \u_zoom_image/mult_image0[1] [4] , \u_zoom_image/mult_image0[1] [3] , \u_zoom_image/mult_image0[1] [2] , \u_zoom_image/mult_image0[1] [1] , \u_zoom_image/mult_image0[1] [0] }), .CXBI (), .CXI (), .MODEY ({1'b0, 1'b0, 1'b0}), @@ -301483,8 +300942,6 @@ module mult_image_ip_unq40 input [14:0] \u_zoom_image/mult_image0_0[1] , input [31:0] \u_zoom_image/rd_data_0 , input CLK, - input _N13071, - input _N13072, input _N13073, input _N13074, input _N13075, @@ -301519,10 +300976,10 @@ module mult_image_ip_unq40 input _N13104, input _N13105, input _N13106, + input _N13107, + input _N13108, output [15:0] \u_zoom_image/mult_image1_0[0] ); - wire _N12735; - wire _N12736; wire _N12737; wire _N12738; wire _N12739; @@ -301557,6 +301014,8 @@ module mult_image_ip_unq40 wire _N12768; wire _N12769; wire _N12770; + wire _N12771; + wire _N12772; wire \N2_CPO[0]_floating ; wire \N2_CPO[1]_floating ; wire \N2_CPO[2]_floating ; @@ -301670,8 +301129,8 @@ module mult_image_ip_unq40 .CPO (), .CXBO (), .CXO (), - .P ({_N12770, _N12769, _N12768, _N12767, _N12766, _N12765, _N12764, _N12763, _N12762, _N12761, _N12760, _N12759, _N12758, _N12757, _N12756, _N12755, _N12754, _N12753, _N12752, _N12751, _N12750, _N12749, _N12748, _N12747, _N12746, _N12745, _N12744, _N12743, _N12742, _N12741, _N12740, _N12739, _N12738, _N12737, _N12736, _N12735, \u_zoom_image/mult_image1_0[0] [11] , \u_zoom_image/mult_image1_0[0] [10] , \u_zoom_image/mult_image1_0[0] [9] , \u_zoom_image/mult_image1_0[0] [8] , \u_zoom_image/mult_image1_0[0] [7] , \u_zoom_image/mult_image1_0[0] [6] , \u_zoom_image/mult_image1_0[0] [5] , \u_zoom_image/mult_image1_0[0] [4] , \u_zoom_image/mult_image1_0[0] [3] , \u_zoom_image/mult_image1_0[0] [2] , \u_zoom_image/mult_image1_0[0] [1] , \u_zoom_image/mult_image1_0[0] [0] }), - .CPI ({_N13106, _N13105, _N13104, _N13103, _N13102, _N13101, _N13100, _N13099, _N13098, _N13097, _N13096, _N13095, _N13094, _N13093, _N13092, _N13091, _N13090, _N13089, _N13088, _N13087, _N13086, _N13085, _N13084, _N13083, _N13082, _N13081, _N13080, _N13079, _N13078, _N13077, _N13076, _N13075, _N13074, _N13073, _N13072, _N13071, \u_zoom_image/mult_image0_0[1] [11] , \u_zoom_image/mult_image0_0[1] [10] , \u_zoom_image/mult_image0_0[1] [9] , \u_zoom_image/mult_image0_0[1] [8] , \u_zoom_image/mult_image0_0[1] [7] , \u_zoom_image/mult_image0_0[1] [6] , \u_zoom_image/mult_image0_0[1] [5] , \u_zoom_image/mult_image0_0[1] [4] , \u_zoom_image/mult_image0_0[1] [3] , \u_zoom_image/mult_image0_0[1] [2] , \u_zoom_image/mult_image0_0[1] [1] , \u_zoom_image/mult_image0_0[1] [0] }), + .P ({_N12772, _N12771, _N12770, _N12769, _N12768, _N12767, _N12766, _N12765, _N12764, _N12763, _N12762, _N12761, _N12760, _N12759, _N12758, _N12757, _N12756, _N12755, _N12754, _N12753, _N12752, _N12751, _N12750, _N12749, _N12748, _N12747, _N12746, _N12745, _N12744, _N12743, _N12742, _N12741, _N12740, _N12739, _N12738, _N12737, \u_zoom_image/mult_image1_0[0] [11] , \u_zoom_image/mult_image1_0[0] [10] , \u_zoom_image/mult_image1_0[0] [9] , \u_zoom_image/mult_image1_0[0] [8] , \u_zoom_image/mult_image1_0[0] [7] , \u_zoom_image/mult_image1_0[0] [6] , \u_zoom_image/mult_image1_0[0] [5] , \u_zoom_image/mult_image1_0[0] [4] , \u_zoom_image/mult_image1_0[0] [3] , \u_zoom_image/mult_image1_0[0] [2] , \u_zoom_image/mult_image1_0[0] [1] , \u_zoom_image/mult_image1_0[0] [0] }), + .CPI ({_N13108, _N13107, _N13106, _N13105, _N13104, _N13103, _N13102, _N13101, _N13100, _N13099, _N13098, _N13097, _N13096, _N13095, _N13094, _N13093, _N13092, _N13091, _N13090, _N13089, _N13088, _N13087, _N13086, _N13085, _N13084, _N13083, _N13082, _N13081, _N13080, _N13079, _N13078, _N13077, _N13076, _N13075, _N13074, _N13073, \u_zoom_image/mult_image0_0[1] [11] , \u_zoom_image/mult_image0_0[1] [10] , \u_zoom_image/mult_image0_0[1] [9] , \u_zoom_image/mult_image0_0[1] [8] , \u_zoom_image/mult_image0_0[1] [7] , \u_zoom_image/mult_image0_0[1] [6] , \u_zoom_image/mult_image0_0[1] [5] , \u_zoom_image/mult_image0_0[1] [4] , \u_zoom_image/mult_image0_0[1] [3] , \u_zoom_image/mult_image0_0[1] [2] , \u_zoom_image/mult_image0_0[1] [1] , \u_zoom_image/mult_image0_0[1] [0] }), .CXBI (), .CXI (), .MODEY ({1'b0, 1'b0, 1'b0}), @@ -301713,8 +301172,6 @@ module mult_image_ip_unq42 input [31:0] \u_zoom_image/rd_data , input CLK, output [14:0] P, - output _N12965, - output _N12966, output _N12967, output _N12968, output _N12969, @@ -301748,10 +301205,10 @@ module mult_image_ip_unq42 output _N12997, output _N12998, output _N12999, - output _N13000 + output _N13000, + output _N13001, + output _N13002 ); - wire _N11823; - wire _N11824; wire _N11825; wire _N11826; wire _N11827; @@ -301786,6 +301243,8 @@ module mult_image_ip_unq42 wire _N11856; wire _N11857; wire _N11858; + wire _N11859; + wire _N11860; wire \N2_CXBO[0]_floating ; wire \N2_CXBO[1]_floating ; wire \N2_CXBO[2]_floating ; @@ -301860,10 +301319,10 @@ module mult_image_ip_unq42 .USE_POSTADD(0), .Z_INIT(48'b000000000000000000000000000000000000000000000000)) N2 ( - .CPO ({_N13000, _N12999, _N12998, _N12997, _N12996, _N12995, _N12994, _N12993, _N12992, _N12991, _N12990, _N12989, _N12988, _N12987, _N12986, _N12985, _N12984, _N12983, _N12982, _N12981, _N12980, _N12979, _N12978, _N12977, _N12976, _N12975, _N12974, _N12973, _N12972, _N12971, _N12970, _N12969, _N12968, _N12967, _N12966, _N12965, P[11], P[10], P[9], P[8], P[7], P[6], P[5], P[4], P[3], P[2], P[1], P[0]}), + .CPO ({_N13002, _N13001, _N13000, _N12999, _N12998, _N12997, _N12996, _N12995, _N12994, _N12993, _N12992, _N12991, _N12990, _N12989, _N12988, _N12987, _N12986, _N12985, _N12984, _N12983, _N12982, _N12981, _N12980, _N12979, _N12978, _N12977, _N12976, _N12975, _N12974, _N12973, _N12972, _N12971, _N12970, _N12969, _N12968, _N12967, P[11], P[10], P[9], P[8], P[7], P[6], P[5], P[4], P[3], P[2], P[1], P[0]}), .CXBO (), .CXO (), - .P ({_N11858, _N11857, _N11856, _N11855, _N11854, _N11853, _N11852, _N11851, _N11850, _N11849, _N11848, _N11847, _N11846, _N11845, _N11844, _N11843, _N11842, _N11841, _N11840, _N11839, _N11838, _N11837, _N11836, _N11835, _N11834, _N11833, _N11832, _N11831, _N11830, _N11829, _N11828, _N11827, _N11826, _N11825, _N11824, _N11823, \N2_P[11]_floating , \N2_P[10]_floating , \N2_P[9]_floating , \N2_P[8]_floating , \N2_P[7]_floating , \N2_P[6]_floating , \N2_P[5]_floating , \N2_P[4]_floating , \N2_P[3]_floating , \N2_P[2]_floating , \N2_P[1]_floating , \N2_P[0]_floating }), + .P ({_N11860, _N11859, _N11858, _N11857, _N11856, _N11855, _N11854, _N11853, _N11852, _N11851, _N11850, _N11849, _N11848, _N11847, _N11846, _N11845, _N11844, _N11843, _N11842, _N11841, _N11840, _N11839, _N11838, _N11837, _N11836, _N11835, _N11834, _N11833, _N11832, _N11831, _N11830, _N11829, _N11828, _N11827, _N11826, _N11825, \N2_P[11]_floating , \N2_P[10]_floating , \N2_P[9]_floating , \N2_P[8]_floating , \N2_P[7]_floating , \N2_P[6]_floating , \N2_P[5]_floating , \N2_P[4]_floating , \N2_P[3]_floating , \N2_P[2]_floating , \N2_P[1]_floating , \N2_P[0]_floating }), .CPI (), .CXBI (), .CXI (), @@ -301906,8 +301365,6 @@ module mult_image_ip_unq44 input [31:0] \u_zoom_image/rd_data_0 , input CLK, output [14:0] P, - output _N13071, - output _N13072, output _N13073, output _N13074, output _N13075, @@ -301941,10 +301398,10 @@ module mult_image_ip_unq44 output _N13103, output _N13104, output _N13105, - output _N13106 + output _N13106, + output _N13107, + output _N13108 ); - wire _N11871; - wire _N11872; wire _N11873; wire _N11874; wire _N11875; @@ -301979,6 +301436,8 @@ module mult_image_ip_unq44 wire _N11904; wire _N11905; wire _N11906; + wire _N11907; + wire _N11908; wire \N2_CXBO[0]_floating ; wire \N2_CXBO[1]_floating ; wire \N2_CXBO[2]_floating ; @@ -302053,10 +301512,10 @@ module mult_image_ip_unq44 .USE_POSTADD(0), .Z_INIT(48'b000000000000000000000000000000000000000000000000)) N2 ( - .CPO ({_N13106, _N13105, _N13104, _N13103, _N13102, _N13101, _N13100, _N13099, _N13098, _N13097, _N13096, _N13095, _N13094, _N13093, _N13092, _N13091, _N13090, _N13089, _N13088, _N13087, _N13086, _N13085, _N13084, _N13083, _N13082, _N13081, _N13080, _N13079, _N13078, _N13077, _N13076, _N13075, _N13074, _N13073, _N13072, _N13071, P[11], P[10], P[9], P[8], P[7], P[6], P[5], P[4], P[3], P[2], P[1], P[0]}), + .CPO ({_N13108, _N13107, _N13106, _N13105, _N13104, _N13103, _N13102, _N13101, _N13100, _N13099, _N13098, _N13097, _N13096, _N13095, _N13094, _N13093, _N13092, _N13091, _N13090, _N13089, _N13088, _N13087, _N13086, _N13085, _N13084, _N13083, _N13082, _N13081, _N13080, _N13079, _N13078, _N13077, _N13076, _N13075, _N13074, _N13073, P[11], P[10], P[9], P[8], P[7], P[6], P[5], P[4], P[3], P[2], P[1], P[0]}), .CXBO (), .CXO (), - .P ({_N11906, _N11905, _N11904, _N11903, _N11902, _N11901, _N11900, _N11899, _N11898, _N11897, _N11896, _N11895, _N11894, _N11893, _N11892, _N11891, _N11890, _N11889, _N11888, _N11887, _N11886, _N11885, _N11884, _N11883, _N11882, _N11881, _N11880, _N11879, _N11878, _N11877, _N11876, _N11875, _N11874, _N11873, _N11872, _N11871, \N2_P[11]_floating , \N2_P[10]_floating , \N2_P[9]_floating , \N2_P[8]_floating , \N2_P[7]_floating , \N2_P[6]_floating , \N2_P[5]_floating , \N2_P[4]_floating , \N2_P[3]_floating , \N2_P[2]_floating , \N2_P[1]_floating , \N2_P[0]_floating }), + .P ({_N11908, _N11907, _N11906, _N11905, _N11904, _N11903, _N11902, _N11901, _N11900, _N11899, _N11898, _N11897, _N11896, _N11895, _N11894, _N11893, _N11892, _N11891, _N11890, _N11889, _N11888, _N11887, _N11886, _N11885, _N11884, _N11883, _N11882, _N11881, _N11880, _N11879, _N11878, _N11877, _N11876, _N11875, _N11874, _N11873, \N2_P[11]_floating , \N2_P[10]_floating , \N2_P[9]_floating , \N2_P[8]_floating , \N2_P[7]_floating , \N2_P[6]_floating , \N2_P[5]_floating , \N2_P[4]_floating , \N2_P[3]_floating , \N2_P[2]_floating , \N2_P[1]_floating , \N2_P[0]_floating }), .CPI (), .CXBI (), .CXI (), @@ -302103,8 +301562,6 @@ module mult_image_w output [20:0] P, output \u_zoom_image/mult_h[6]_inv ); - wire _N11928; - wire _N11929; wire _N11930; wire _N11931; wire _N11932; @@ -302130,6 +301587,8 @@ module mult_image_w wire _N11952; wire _N11953; wire _N11954; + wire _N11955; + wire _N11956; wire \N3_CPO[0]_floating ; wire \N3_CPO[1]_floating ; wire \N3_CPO[2]_floating ; @@ -302243,7 +301702,7 @@ module mult_image_w .CPO (), .CXBO (), .CXO (), - .P ({_N11954, _N11953, _N11952, _N11951, _N11950, _N11949, _N11948, _N11947, _N11946, _N11945, _N11944, _N11943, _N11942, _N11941, _N11940, _N11939, _N11938, _N11937, _N11936, _N11935, _N11934, _N11933, _N11932, _N11931, _N11930, _N11929, _N11928, P[20], P[19], P[18], P[17], P[16], P[15], P[14], P[13], P[12], P[11], P[10], P[9], P[8], P[7], P[6], P[5], P[4], P[3], P[2], P[1], P[0]}), + .P ({_N11956, _N11955, _N11954, _N11953, _N11952, _N11951, _N11950, _N11949, _N11948, _N11947, _N11946, _N11945, _N11944, _N11943, _N11942, _N11941, _N11940, _N11939, _N11938, _N11937, _N11936, _N11935, _N11934, _N11933, _N11932, _N11931, _N11930, P[20], P[19], P[18], P[17], P[16], P[15], P[14], P[13], P[12], P[11], P[10], P[9], P[8], P[7], P[6], P[5], P[4], P[3], P[2], P[1], P[0]}), .CPI (), .CXBI (), .CXI (), @@ -302296,8 +301755,6 @@ module mult_image_w_unq4 input \u_zoom_image/N850 , output [20:0] \u_zoom_image/image_w0 ); - wire _N12792; - wire _N12793; wire _N12794; wire _N12795; wire _N12796; @@ -302323,6 +301780,8 @@ module mult_image_w_unq4 wire _N12816; wire _N12817; wire _N12818; + wire _N12819; + wire _N12820; wire \N3_CPO[0]_floating ; wire \N3_CPO[1]_floating ; wire \N3_CPO[2]_floating ; @@ -302436,7 +301895,7 @@ module mult_image_w_unq4 .CPO (), .CXBO (), .CXO (), - .P ({_N12818, _N12817, _N12816, _N12815, _N12814, _N12813, _N12812, _N12811, _N12810, _N12809, _N12808, _N12807, _N12806, _N12805, _N12804, _N12803, _N12802, _N12801, _N12800, _N12799, _N12798, _N12797, _N12796, _N12795, _N12794, _N12793, _N12792, \u_zoom_image/image_w0 [20] , \u_zoom_image/image_w0 [19] , \u_zoom_image/image_w0 [18] , \u_zoom_image/image_w0 [17] , \u_zoom_image/image_w0 [16] , \u_zoom_image/image_w0 [15] , \u_zoom_image/image_w0 [14] , \u_zoom_image/image_w0 [13] , \u_zoom_image/image_w0 [12] , \u_zoom_image/image_w0 [11] , \u_zoom_image/image_w0 [10] , \u_zoom_image/image_w0 [9] , \u_zoom_image/image_w0 [8] , \u_zoom_image/image_w0 [7] , \u_zoom_image/image_w0 [6] , \u_zoom_image/image_w0 [5] , \u_zoom_image/image_w0 [4] , \u_zoom_image/image_w0 [3] , \u_zoom_image/image_w0 [2] , \u_zoom_image/image_w0 [1] , \u_zoom_image/image_w0 [0] }), + .P ({_N12820, _N12819, _N12818, _N12817, _N12816, _N12815, _N12814, _N12813, _N12812, _N12811, _N12810, _N12809, _N12808, _N12807, _N12806, _N12805, _N12804, _N12803, _N12802, _N12801, _N12800, _N12799, _N12798, _N12797, _N12796, _N12795, _N12794, \u_zoom_image/image_w0 [20] , \u_zoom_image/image_w0 [19] , \u_zoom_image/image_w0 [18] , \u_zoom_image/image_w0 [17] , \u_zoom_image/image_w0 [16] , \u_zoom_image/image_w0 [15] , \u_zoom_image/image_w0 [14] , \u_zoom_image/image_w0 [13] , \u_zoom_image/image_w0 [12] , \u_zoom_image/image_w0 [11] , \u_zoom_image/image_w0 [10] , \u_zoom_image/image_w0 [9] , \u_zoom_image/image_w0 [8] , \u_zoom_image/image_w0 [7] , \u_zoom_image/image_w0 [6] , \u_zoom_image/image_w0 [5] , \u_zoom_image/image_w0 [4] , \u_zoom_image/image_w0 [3] , \u_zoom_image/image_w0 [2] , \u_zoom_image/image_w0 [1] , \u_zoom_image/image_w0 [0] }), .CPI (), .CXBI (), .CXI (), @@ -304643,6 +304102,7 @@ module zoom_image_v1 wire _N16; wire _N17; wire _N20; + wire _N23; wire _N24; wire _N25; wire _N27; @@ -304657,17 +304117,15 @@ module zoom_image_v1 wire _N60; wire _N64; wire _N68; - wire _N10185; - wire _N10193; - wire _N10201; + wire _N10205; wire _N10213; - wire _N10250; - wire _N10267; - wire _N10283; - wire _N10299; - wire _N10307; - wire _N12965; - wire _N12966; + wire _N10221; + wire _N10233; + wire _N10270; + wire _N10287; + wire _N10303; + wire _N10319; + wire _N10327; wire _N12967; wire _N12968; wire _N12969; @@ -304880,8 +304338,35 @@ module zoom_image_v1 wire _N13176; wire _N13177; wire _N13178; - wire _N13738; - wire _N13739; + wire _N13179; + wire _N13180; + wire _N13707; + wire _N13708; + wire _N13709; + wire _N13710; + wire _N13711; + wire _N13712; + wire _N13713; + wire _N13714; + wire _N13715; + wire _N13718; + wire _N13719; + wire _N13720; + wire _N13721; + wire _N13722; + wire _N13723; + wire _N13724; + wire _N13725; + wire _N13726; + wire _N13729; + wire _N13730; + wire _N13731; + wire _N13732; + wire _N13733; + wire _N13734; + wire _N13735; + wire _N13736; + wire _N13737; wire _N13740; wire _N13741; wire _N13742; @@ -304889,8 +304374,8 @@ module zoom_image_v1 wire _N13744; wire _N13745; wire _N13746; - wire _N13749; - wire _N13750; + wire _N13747; + wire _N13748; wire _N13751; wire _N13752; wire _N13753; @@ -304898,8 +304383,8 @@ module zoom_image_v1 wire _N13755; wire _N13756; wire _N13757; - wire _N13760; - wire _N13761; + wire _N13758; + wire _N13759; wire _N13762; wire _N13763; wire _N13764; @@ -304907,8 +304392,8 @@ module zoom_image_v1 wire _N13766; wire _N13767; wire _N13768; - wire _N13771; - wire _N13772; + wire _N13769; + wire _N13770; wire _N13773; wire _N13774; wire _N13775; @@ -304916,82 +304401,112 @@ module zoom_image_v1 wire _N13777; wire _N13778; wire _N13779; - wire _N13782; - wire _N13783; - wire _N13784; - wire _N13785; - wire _N13786; - wire _N13787; - wire _N13788; - wire _N13789; - wire _N13790; - wire _N13793; - wire _N13794; - wire _N13795; - wire _N13796; - wire _N13797; - wire _N13798; - wire _N13799; - wire _N13800; - wire _N13801; - wire _N14628; - wire _N14629; - wire _N14630; - wire _N14631; - wire _N14632; - wire _N14633; - wire _N14634; - wire _N14635; - wire _N14636; - wire _N14926; - wire _N14927; - wire _N14928; - wire _N14929; - wire _N14930; - wire _N14931; - wire _N14932; - wire _N14933; - wire _N14934; - wire _N14935; - wire _N14936; - wire _N14937; - wire _N14940; - wire _N14941; - wire _N14942; - wire _N14943; - wire _N14944; - wire _N14945; - wire _N14946; - wire _N14947; - wire _N14952; - wire _N14953; - wire _N14954; - wire _N14955; - wire _N14956; - wire _N14959; - wire _N14960; - wire _N14961; - wire _N14962; - wire _N14963; - wire _N14964; - wire _N14965; - wire _N14966; - wire _N14967; - wire _N14968; - wire _N14969; - wire _N14970; - wire _N14971; - wire _N14973; - wire _N14974; - wire _N14975; - wire _N14976; - wire _N14977; - wire _N14978; - wire _N14979; - wire _N14980; - wire _N14981; - wire _N14982; + wire _N13780; + wire _N13781; + wire _N14584; + wire _N14585; + wire _N14586; + wire _N14587; + wire _N14588; + wire _N14589; + wire _N14590; + wire _N14591; + wire _N14592; + wire _N14593; + wire _N14594; + wire _N14595; + wire _N14876; + wire _N14877; + wire _N14878; + wire _N14879; + wire _N14880; + wire _N14881; + wire _N14882; + wire _N14883; + wire _N14888; + wire _N14889; + wire _N14890; + wire _N14891; + wire _N14892; + wire _N14895; + wire _N14896; + wire _N14897; + wire _N14898; + wire _N14899; + wire _N14900; + wire _N14901; + wire _N14902; + wire _N14903; + wire _N14904; + wire _N14905; + wire _N14906; + wire _N14907; + wire _N14909; + wire _N14910; + wire _N14911; + wire _N14912; + wire _N14913; + wire _N14914; + wire _N14915; + wire _N14916; + wire _N14917; + wire _N14918; + wire _N16623; + wire _N16632; + wire _N16633; + wire _N16634; + wire _N16635; + wire _N16636; + wire _N16637; + wire _N16638; + wire _N16639; + wire _N16640; + wire _N16641; + wire _N16642; + wire _N16643; + wire _N16644; + wire _N16645; + wire _N16646; + wire _N16647; + wire _N16648; + wire _N16649; + wire _N16650; + wire _N16651; + wire _N16654; + wire _N16655; + wire _N16656; + wire _N16657; + wire _N16658; + wire _N16659; + wire _N16660; + wire _N16661; + wire _N16662; + wire _N16663; + wire _N16664; + wire _N16665; + wire _N16666; + wire _N16667; + wire _N16668; + wire _N16669; + wire _N16670; + wire _N16671; + wire _N16672; + wire _N16673; + wire _N16676; + wire _N16677; + wire _N16678; + wire _N16679; + wire _N16680; + wire _N16681; + wire _N16682; + wire _N16683; wire _N16684; + wire _N16685; + wire _N16686; + wire _N16689; + wire _N16690; + wire _N16691; + wire _N16692; wire _N16693; wire _N16694; wire _N16695; @@ -305000,8 +304515,6 @@ module zoom_image_v1 wire _N16698; wire _N16699; wire _N16700; - wire _N16701; - wire _N16702; wire _N16703; wire _N16704; wire _N16705; @@ -305012,85 +304525,30 @@ module zoom_image_v1 wire _N16710; wire _N16711; wire _N16712; - wire _N16715; - wire _N16716; - wire _N16717; - wire _N16718; - wire _N16719; - wire _N16720; - wire _N16721; - wire _N16722; - wire _N16723; - wire _N16724; - wire _N16725; - wire _N16726; - wire _N16727; - wire _N16728; - wire _N16729; - wire _N16730; - wire _N16731; - wire _N16732; - wire _N16733; - wire _N16734; - wire _N16749; - wire _N16750; - wire _N16751; - wire _N16752; - wire _N16753; - wire _N16754; - wire _N16755; - wire _N16756; - wire _N16757; - wire _N16758; - wire _N16759; - wire _N16762; - wire _N16763; - wire _N16764; - wire _N16765; - wire _N16766; - wire _N16767; - wire _N16768; - wire _N16769; - wire _N16770; - wire _N16771; - wire _N16772; - wire _N16773; - wire _N16776; - wire _N16777; - wire _N16778; - wire _N16779; - wire _N16780; - wire _N16781; - wire _N16782; - wire _N16783; - wire _N16784; - wire _N16785; - wire _N16786; - wire _N96561; - wire _N103322; - wire _N104995; - wire _N104996; - wire _N104997; - wire _N105007; - wire _N105009; - wire _N105018; - wire _N105020; - wire _N105029; - wire _N105031; - wire _N105036; - wire _N105043; - wire _N105046; - wire _N105079; - wire _N105085; - wire _N105097; - wire _N105114; - wire _N105128; - wire _N105129; - wire _N105134; - wire _N105142; - wire _N107195; - wire _N108389; - wire _N108390; + wire _N16713; + wire _N97307; + wire _N104134; + wire _N105542; + wire _N105543; + wire _N105544; + wire _N105554; + wire _N105556; + wire _N105565; + wire _N105567; + wire _N105576; + wire _N105578; + wire _N105583; + wire _N105590; + wire _N105593; + wire _N105626; + wire _N105632; + wire _N105644; + wire _N105661; + wire _N105675; + wire _N105676; + wire _N105681; + wire _N105689; + wire _N108017; wire [4:0] addr_sta_reg; wire [10:0] cnt_h; wire [2:0] cnt_record_ram; @@ -305272,7 +304730,7 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N78_1_1 ( - .COUT (_N13738), + .COUT (_N13707), .Z (N78[1]), .CIN (), .I0 (cnt_h[0]), @@ -305292,9 +304750,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N78_1_2 ( - .COUT (_N13739), + .COUT (_N13708), .Z (N78[2]), - .CIN (_N13738), + .CIN (_N13707), .I0 (cnt_h[0]), .I1 (cnt_h[1]), .I2 (cnt_h[2]), @@ -305312,9 +304770,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N78_1_3 ( - .COUT (_N13740), + .COUT (_N13709), .Z (N78[3]), - .CIN (_N13739), + .CIN (_N13708), .I0 (), .I1 (cnt_h[3]), .I2 (), @@ -305332,9 +304790,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N78_1_4 ( - .COUT (_N13741), + .COUT (_N13710), .Z (N78[4]), - .CIN (_N13740), + .CIN (_N13709), .I0 (), .I1 (cnt_h[4]), .I2 (), @@ -305352,9 +304810,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N78_1_5 ( - .COUT (_N13742), + .COUT (_N13711), .Z (N78[5]), - .CIN (_N13741), + .CIN (_N13710), .I0 (), .I1 (cnt_h[5]), .I2 (), @@ -305372,9 +304830,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N78_1_6 ( - .COUT (_N13743), + .COUT (_N13712), .Z (N78[6]), - .CIN (_N13742), + .CIN (_N13711), .I0 (), .I1 (cnt_h[6]), .I2 (), @@ -305392,9 +304850,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N78_1_7 ( - .COUT (_N13744), + .COUT (_N13713), .Z (N78[7]), - .CIN (_N13743), + .CIN (_N13712), .I0 (), .I1 (cnt_h[7]), .I2 (), @@ -305412,9 +304870,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N78_1_8 ( - .COUT (_N13745), + .COUT (_N13714), .Z (N78[8]), - .CIN (_N13744), + .CIN (_N13713), .I0 (), .I1 (cnt_h[8]), .I2 (), @@ -305432,9 +304890,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N78_1_9 ( - .COUT (_N13746), + .COUT (_N13715), .Z (N78[9]), - .CIN (_N13745), + .CIN (_N13714), .I0 (), .I1 (cnt_h[9]), .I2 (), @@ -305454,7 +304912,7 @@ module zoom_image_v1 N78_1_10 ( .COUT (), .Z (N78[10]), - .CIN (_N13746), + .CIN (_N13715), .I0 (), .I1 (cnt_h[10]), .I2 (), @@ -305472,7 +304930,7 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N85_1_1 ( - .COUT (_N13749), + .COUT (_N13718), .Z (N85[1]), .CIN (), .I0 (cnt_w[0]), @@ -305492,9 +304950,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N85_1_2 ( - .COUT (_N13750), + .COUT (_N13719), .Z (N85[2]), - .CIN (_N13749), + .CIN (_N13718), .I0 (cnt_w[0]), .I1 (cnt_w[1]), .I2 (cnt_w[2]), @@ -305512,9 +304970,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N85_1_3 ( - .COUT (_N13751), + .COUT (_N13720), .Z (N849[3]), - .CIN (_N13750), + .CIN (_N13719), .I0 (), .I1 (cnt_w[3]), .I2 (zoom_sta_reg[1]), @@ -305532,9 +304990,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N85_1_4 ( - .COUT (_N13752), + .COUT (_N13721), .Z (N849[4]), - .CIN (_N13751), + .CIN (_N13720), .I0 (), .I1 (cnt_w[4]), .I2 (zoom_sta_reg[1]), @@ -305552,9 +305010,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N85_1_5 ( - .COUT (_N13753), + .COUT (_N13722), .Z (N849[5]), - .CIN (_N13752), + .CIN (_N13721), .I0 (), .I1 (cnt_w[5]), .I2 (zoom_sta_reg[1]), @@ -305572,9 +305030,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N85_1_6 ( - .COUT (_N13754), + .COUT (_N13723), .Z (N849[6]), - .CIN (_N13753), + .CIN (_N13722), .I0 (), .I1 (cnt_w[6]), .I2 (zoom_sta_reg[1]), @@ -305592,9 +305050,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N85_1_7 ( - .COUT (_N13755), + .COUT (_N13724), .Z (N849[7]), - .CIN (_N13754), + .CIN (_N13723), .I0 (), .I1 (cnt_w[7]), .I2 (zoom_sta_reg[1]), @@ -305612,9 +305070,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N85_1_8 ( - .COUT (_N13756), + .COUT (_N13725), .Z (N849[8]), - .CIN (_N13755), + .CIN (_N13724), .I0 (), .I1 (cnt_w[8]), .I2 (zoom_sta_reg[1]), @@ -305632,9 +305090,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N85_1_9 ( - .COUT (_N13757), + .COUT (_N13726), .Z (N849[9]), - .CIN (_N13756), + .CIN (_N13725), .I0 (), .I1 (cnt_w[9]), .I2 (zoom_sta_reg[1]), @@ -305654,7 +305112,7 @@ module zoom_image_v1 N85_1_10 ( .COUT (), .Z (N849[10]), - .CIN (_N13757), + .CIN (_N13726), .I0 (), .I1 (cnt_w[10]), .I2 (zoom_sta_reg[1]), @@ -305676,7 +305134,7 @@ module zoom_image_v1 GTP_LUT5 /* N131_mux4_3 */ #( .INIT(32'b00000000000000000000000001111111)) N131_mux4_3 ( - .Z (_N10185), + .Z (_N10205), .I0 (judge_cnt_h[0]), .I1 (judge_cnt_h[1]), .I2 (judge_cnt_h[2]), @@ -305687,8 +305145,8 @@ module zoom_image_v1 GTP_LUT5 /* N131_mux8 */ #( .INIT(32'b00000000101111111111111111111111)) N131_mux8 ( - .Z (_N10193), - .I0 (_N10185), + .Z (_N10213), + .I0 (_N10205), .I1 (judge_cnt_h[5]), .I2 (judge_cnt_h[6]), .I3 (judge_cnt_h[7]), @@ -305698,8 +305156,8 @@ module zoom_image_v1 GTP_LUT5 /* N131_mux12_5 */ #( .INIT(32'b00000000000000000000000000000010)) N131_mux12_5 ( - .Z (_N10201), - .I0 (_N10193), + .Z (_N10221), + .I0 (_N10213), .I1 (judge_cnt_h[9]), .I2 (judge_cnt_h[10]), .I3 (judge_cnt_h[11]), @@ -305709,7 +305167,7 @@ module zoom_image_v1 GTP_LUT5 /* N135_mux4 */ #( .INIT(32'b00000000000001111111111111111111)) N135_mux4 ( - .Z (_N10213), + .Z (_N10233), .I0 (judge_cnt_h[3]), .I1 (judge_cnt_h[4]), .I2 (judge_cnt_h[5]), @@ -305720,7 +305178,7 @@ module zoom_image_v1 GTP_LUT4 /* N135_mux9_4 */ #( .INIT(16'b0111111111111111)) N135_mux9_4 ( - .Z (_N105085), + .Z (_N105632), .I0 (judge_cnt_h[9]), .I1 (judge_cnt_h[10]), .I2 (judge_cnt_h[11]), @@ -305730,7 +305188,7 @@ module zoom_image_v1 GTP_LUT3 /* N143_5 */ #( .INIT(8'b00001000)) N143_5 ( - .Z (_N105097), + .Z (_N105644), .I0 (delay_cnt[0]), .I1 (delay_cnt[1]), .I2 (delay_cnt[2])); @@ -305740,12 +305198,12 @@ module zoom_image_v1 .INIT(32'b00001101000000001010101000000000)) N143_7 ( .Z (N143), - .I0 (_N10213), + .I0 (_N10233), .I1 (judge_cnt_h[8]), - .I2 (_N105085), - .I3 (_N105097), + .I2 (_N105632), + .I3 (_N105644), .I4 (judge_cnt_h[13]), - .ID (_N10201)); + .ID (_N10221)); // LUT = (ID&I3&~I4)|(I1&~I2&I3&I4)|(~I0&~I2&I3&I4) ; GTP_LUT2 /* N163_sum1 */ #( @@ -305798,7 +305256,7 @@ module zoom_image_v1 GTP_LUT2 /* N204_1_sum1_7 */ #( .INIT(4'b0110)) N204_1_sum1_7 ( - .Z (_N107195), + .Z (_N108017), .I0 (ram_ch[1]), .I1 (store_mult_h0[1])); // LUT = (I0&~I1)|(~I0&I1) ; @@ -305811,13 +305269,13 @@ module zoom_image_v1 .I1 (store_mult_h[0]), .I2 (store_mult_h[1]), .I3 (store_mult_h0[0]), - .I4 (_N107195)); + .I4 (_N108017)); // LUT = (~I1&I2&~I3&~I4)|(~I0&I1&I2&~I4)|(I0&I2&I3&~I4)|(~I1&~I2&~I3&I4)|(~I0&I1&~I2&I4)|(I0&~I2&I3&I4)|(I0&I1&~I2&~I3&~I4)|(~I0&~I1&~I2&I3&~I4)|(I0&I1&I2&~I3&I4)|(~I0&~I1&I2&I3&I4) ; GTP_LUT2 /* N227_1_ab0 */ #( .INIT(4'b1000)) N227_1_ab0 ( - .Z (_N10250), + .Z (_N10270), .I0 (wr_ram_done), .I1 (cnt_record_ram[0])); // LUT = I0&I1 ; @@ -305825,7 +305283,7 @@ module zoom_image_v1 GTP_LUT2 /* N227_1_sum1_2 */ #( .INIT(4'b0110)) N227_1_sum1_2 ( - .Z (_N105036), + .Z (_N105583), .I0 (no_need_rd_ddr), .I1 (cnt_record_ram[1])); // LUT = (I0&~I1)|(~I0&I1) ; @@ -305833,7 +305291,7 @@ module zoom_image_v1 GTP_LUT3 /* N227_2_ab0 */ #( .INIT(8'b00101000)) N227_2_ab0 ( - .Z (_N16684), + .Z (_N16623), .I0 (no_one_need_rd_ddr), .I1 (wr_ram_done), .I2 (cnt_record_ram[0])); @@ -305856,18 +305314,18 @@ module zoom_image_v1 .I1 (rd_one_ram), .I2 (wr_ram_done), .I3 (cnt_record_ram[0]), - .I4 (_N105036)); + .I4 (_N105583)); // LUT = (I1&~I2&~I3&~I4)|(~I0&I1&~I3&~I4)|(~I0&I1&~I2&~I4)|(I0&~I1&I2&~I4)|(I0&~I1&I3&~I4)|(~I1&I2&I3&~I4)|(~I1&~I2&~I3&I4)|(~I0&~I1&~I3&I4)|(~I0&~I1&~I2&I4)|(I0&I1&I2&I4)|(I0&I1&I3&I4)|(I1&I2&I3&I4) ; GTP_LUT5M /* N227_2_sum2_4 */ #( .INIT(32'b10101001010101101001010101101010)) N227_2_sum2_4 ( - .Z (_N105134), + .Z (_N105681), .I0 (cnt_record_ram[1]), - .I1 (_N10250), + .I1 (_N10270), .I2 (no_need_rd_ddr), .I3 (cnt_record_ram[2]), - .I4 (_N16684), + .I4 (_N16623), .ID (rd_one_ram)); // LUT = (ID&~I2&~I3&~I4)|(~ID&I1&I2&~I3&~I4)|(ID&~I1&~I3&~I4)|(~ID&~I2&I3&~I4)|(ID&I1&I2&I3&~I4)|(~ID&~I1&I3&~I4)|(I0&~I1&~I2&~I3&I4)|(~I0&I2&~I3&I4)|(~I0&I1&~I3&I4)|(~I0&~I1&~I2&I3&I4)|(I0&I2&I3&I4)|(I0&I1&I3&I4) ; @@ -305875,11 +305333,11 @@ module zoom_image_v1 .INIT(32'b00001001100111111111011001100000)) N227_2_sum2_5 ( .Z (N959[2]), - .I0 (_N10250), + .I0 (_N10270), .I1 (no_need_rd_ddr), .I2 (rd_one_ram), .I3 (cnt_record_ram[1]), - .I4 (_N105134)); + .I4 (_N105681)); // LUT = (I2&I3&~I4)|(~I2&~I3&I4)|(I0&~I1&I2&~I4)|(I0&~I1&I3&~I4)|(~I0&I1&I2&~I4)|(~I0&I1&I3&~I4)|(~I0&~I1&~I3&I4)|(I0&I1&~I3&I4)|(~I0&~I1&~I2&I4)|(I0&I1&~I2&I4) ; GTP_LUT2 /* N232_0 */ #( @@ -305925,7 +305383,7 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N244_1_1 ( - .COUT (_N13760), + .COUT (_N13729), .Z (N948[1]), .CIN (), .I0 (rd_addr0[0]), @@ -305945,9 +305403,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N244_1_2 ( - .COUT (_N13761), + .COUT (_N13730), .Z (N948[2]), - .CIN (_N13760), + .CIN (_N13729), .I0 (rd_addr0[0]), .I1 (rd_addr0[1]), .I2 (rd_addr0[2]), @@ -305965,9 +305423,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N244_1_3 ( - .COUT (_N13762), + .COUT (_N13731), .Z (N948[3]), - .CIN (_N13761), + .CIN (_N13730), .I0 (), .I1 (rd_addr0[3]), .I2 (), @@ -305985,9 +305443,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N244_1_4 ( - .COUT (_N13763), + .COUT (_N13732), .Z (N948[4]), - .CIN (_N13762), + .CIN (_N13731), .I0 (), .I1 (rd_addr0[4]), .I2 (), @@ -306005,9 +305463,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N244_1_5 ( - .COUT (_N13764), + .COUT (_N13733), .Z (N948[5]), - .CIN (_N13763), + .CIN (_N13732), .I0 (), .I1 (rd_addr0[5]), .I2 (), @@ -306025,9 +305483,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N244_1_6 ( - .COUT (_N13765), + .COUT (_N13734), .Z (N948[6]), - .CIN (_N13764), + .CIN (_N13733), .I0 (), .I1 (rd_addr0[6]), .I2 (), @@ -306045,9 +305503,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N244_1_7 ( - .COUT (_N13766), + .COUT (_N13735), .Z (N948[7]), - .CIN (_N13765), + .CIN (_N13734), .I0 (), .I1 (rd_addr0[7]), .I2 (), @@ -306065,9 +305523,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N244_1_8 ( - .COUT (_N13767), + .COUT (_N13736), .Z (N948[8]), - .CIN (_N13766), + .CIN (_N13735), .I0 (), .I1 (rd_addr0[8]), .I2 (), @@ -306085,9 +305543,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N244_1_9 ( - .COUT (_N13768), + .COUT (_N13737), .Z (N948[9]), - .CIN (_N13767), + .CIN (_N13736), .I0 (), .I1 (rd_addr0[9]), .I2 (), @@ -306107,7 +305565,7 @@ module zoom_image_v1 N244_1_10 ( .COUT (), .Z (N948[10]), - .CIN (_N13768), + .CIN (_N13737), .I0 (), .I1 (rd_addr0[10]), .I2 (), @@ -306121,7 +305579,7 @@ module zoom_image_v1 GTP_LUT4 /* N274_9 */ #( .INIT(16'b1000000000000000)) N274_9 ( - .Z (_N105029), + .Z (_N105576), .I0 (wr_addr0[3]), .I1 (wr_addr0[4]), .I2 (wr_addr0[5]), @@ -306131,12 +305589,12 @@ module zoom_image_v1 GTP_LUT5 /* N274_11 */ #( .INIT(32'b00000000000010000000000000000000)) N274_11 ( - .Z (_N105031), + .Z (_N105578), .I0 (wr_addr0[1]), .I1 (wr_addr0[2]), .I2 (wr_addr0[8]), .I3 (wr_addr0[9]), - .I4 (_N105029)); + .I4 (_N105576)); // LUT = I0&I1&~I2&~I3&I4 ; GTP_LUT4 /* N274_12 */ #( @@ -306152,7 +305610,7 @@ module zoom_image_v1 GTP_LUT4 /* N290_8 */ #( .INIT(16'b0000000000001000)) N290_8 ( - .Z (_N104995), + .Z (_N105542), .I0 (wr_addr1[1]), .I1 (wr_addr1[2]), .I2 (wr_addr1[8]), @@ -306162,7 +305620,7 @@ module zoom_image_v1 GTP_LUT4 /* N290_9 */ #( .INIT(16'b1000000000000000)) N290_9 ( - .Z (_N104996), + .Z (_N105543), .I0 (wr_addr1[3]), .I1 (wr_addr1[4]), .I2 (wr_addr1[5]), @@ -306172,7 +305630,7 @@ module zoom_image_v1 GTP_LUT4 /* N290_10 */ #( .INIT(16'b1000000000000000)) N290_10 ( - .Z (_N104997), + .Z (_N105544), .I0 (data_in_valid0), .I1 (wr_addr1[0]), .I2 (wr_addr1[7]), @@ -306182,7 +305640,7 @@ module zoom_image_v1 GTP_LUT4 /* N306_9 */ #( .INIT(16'b1000000000000000)) N306_9 ( - .Z (_N105007), + .Z (_N105554), .I0 (wr_addr2[3]), .I1 (wr_addr2[4]), .I2 (wr_addr2[5]), @@ -306192,12 +305650,12 @@ module zoom_image_v1 GTP_LUT5 /* N306_11 */ #( .INIT(32'b00000000000010000000000000000000)) N306_11 ( - .Z (_N105009), + .Z (_N105556), .I0 (wr_addr2[1]), .I1 (wr_addr2[2]), .I2 (wr_addr2[8]), .I3 (wr_addr2[9]), - .I4 (_N105007)); + .I4 (_N105554)); // LUT = I0&I1&~I2&~I3&I4 ; GTP_LUT5 /* N306_12 */ #( @@ -306208,13 +305666,13 @@ module zoom_image_v1 .I1 (wr_addr2[0]), .I2 (wr_addr2[7]), .I3 (wr_addr2[10]), - .I4 (_N105009)); + .I4 (_N105556)); // LUT = I0&I1&I2&I3&I4 ; GTP_LUT4 /* N322_9 */ #( .INIT(16'b1000000000000000)) N322_9 ( - .Z (_N105018), + .Z (_N105565), .I0 (wr_addr3[3]), .I1 (wr_addr3[4]), .I2 (wr_addr3[5]), @@ -306224,12 +305682,12 @@ module zoom_image_v1 GTP_LUT5 /* N322_11 */ #( .INIT(32'b00000000000010000000000000000000)) N322_11 ( - .Z (_N105020), + .Z (_N105567), .I0 (wr_addr3[1]), .I1 (wr_addr3[2]), .I2 (wr_addr3[8]), .I3 (wr_addr3[9]), - .I4 (_N105018)); + .I4 (_N105565)); // LUT = I0&I1&~I2&~I3&I4 ; GTP_LUT5 /* N322_12 */ #( @@ -306240,7 +305698,7 @@ module zoom_image_v1 .I1 (wr_addr3[0]), .I2 (wr_addr3[7]), .I3 (wr_addr3[10]), - .I4 (_N105020)); + .I4 (_N105567)); // LUT = I0&I1&I2&I3&I4 ; GTP_LUT5CARRY /* N340_1_1 */ #( @@ -306250,7 +305708,7 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N340_1_1 ( - .COUT (_N13771), + .COUT (_N13740), .Z (N340[1]), .CIN (), .I0 (wr_addr0[0]), @@ -306270,9 +305728,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N340_1_2 ( - .COUT (_N13772), + .COUT (_N13741), .Z (N340[2]), - .CIN (_N13771), + .CIN (_N13740), .I0 (wr_addr0[0]), .I1 (wr_addr0[1]), .I2 (wr_addr0[2]), @@ -306290,9 +305748,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N340_1_3 ( - .COUT (_N13773), + .COUT (_N13742), .Z (N340[3]), - .CIN (_N13772), + .CIN (_N13741), .I0 (), .I1 (wr_addr0[3]), .I2 (), @@ -306310,9 +305768,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N340_1_4 ( - .COUT (_N13774), + .COUT (_N13743), .Z (N340[4]), - .CIN (_N13773), + .CIN (_N13742), .I0 (), .I1 (wr_addr0[4]), .I2 (), @@ -306330,9 +305788,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N340_1_5 ( - .COUT (_N13775), + .COUT (_N13744), .Z (N340[5]), - .CIN (_N13774), + .CIN (_N13743), .I0 (), .I1 (wr_addr0[5]), .I2 (), @@ -306350,9 +305808,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N340_1_6 ( - .COUT (_N13776), + .COUT (_N13745), .Z (N340[6]), - .CIN (_N13775), + .CIN (_N13744), .I0 (), .I1 (wr_addr0[6]), .I2 (), @@ -306370,9 +305828,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N340_1_7 ( - .COUT (_N13777), + .COUT (_N13746), .Z (N340[7]), - .CIN (_N13776), + .CIN (_N13745), .I0 (), .I1 (wr_addr0[7]), .I2 (), @@ -306390,9 +305848,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N340_1_8 ( - .COUT (_N13778), + .COUT (_N13747), .Z (N340[8]), - .CIN (_N13777), + .CIN (_N13746), .I0 (), .I1 (wr_addr0[8]), .I2 (), @@ -306410,9 +305868,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N340_1_9 ( - .COUT (_N13779), + .COUT (_N13748), .Z (N340[9]), - .CIN (_N13778), + .CIN (_N13747), .I0 (), .I1 (wr_addr0[9]), .I2 (), @@ -306432,7 +305890,7 @@ module zoom_image_v1 N340_1_10 ( .COUT (), .Z (N340[10]), - .CIN (_N13779), + .CIN (_N13748), .I0 (), .I1 (wr_addr0[10]), .I2 (), @@ -306450,7 +305908,7 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N346_1_1 ( - .COUT (_N13782), + .COUT (_N13751), .Z (N346[1]), .CIN (), .I0 (wr_addr1[0]), @@ -306470,9 +305928,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N346_1_2 ( - .COUT (_N13783), + .COUT (_N13752), .Z (N346[2]), - .CIN (_N13782), + .CIN (_N13751), .I0 (wr_addr1[0]), .I1 (wr_addr1[1]), .I2 (wr_addr1[2]), @@ -306490,9 +305948,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N346_1_3 ( - .COUT (_N13784), + .COUT (_N13753), .Z (N346[3]), - .CIN (_N13783), + .CIN (_N13752), .I0 (), .I1 (wr_addr1[3]), .I2 (), @@ -306510,9 +305968,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N346_1_4 ( - .COUT (_N13785), + .COUT (_N13754), .Z (N346[4]), - .CIN (_N13784), + .CIN (_N13753), .I0 (), .I1 (wr_addr1[4]), .I2 (), @@ -306530,9 +305988,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N346_1_5 ( - .COUT (_N13786), + .COUT (_N13755), .Z (N346[5]), - .CIN (_N13785), + .CIN (_N13754), .I0 (), .I1 (wr_addr1[5]), .I2 (), @@ -306550,9 +306008,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N346_1_6 ( - .COUT (_N13787), + .COUT (_N13756), .Z (N346[6]), - .CIN (_N13786), + .CIN (_N13755), .I0 (), .I1 (wr_addr1[6]), .I2 (), @@ -306570,9 +306028,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N346_1_7 ( - .COUT (_N13788), + .COUT (_N13757), .Z (N346[7]), - .CIN (_N13787), + .CIN (_N13756), .I0 (), .I1 (wr_addr1[7]), .I2 (), @@ -306590,9 +306048,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N346_1_8 ( - .COUT (_N13789), + .COUT (_N13758), .Z (N346[8]), - .CIN (_N13788), + .CIN (_N13757), .I0 (), .I1 (wr_addr1[8]), .I2 (), @@ -306610,9 +306068,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N346_1_9 ( - .COUT (_N13790), + .COUT (_N13759), .Z (N346[9]), - .CIN (_N13789), + .CIN (_N13758), .I0 (), .I1 (wr_addr1[9]), .I2 (), @@ -306632,7 +306090,7 @@ module zoom_image_v1 N346_1_10 ( .COUT (), .Z (N346[10]), - .CIN (_N13790), + .CIN (_N13759), .I0 (), .I1 (wr_addr1[10]), .I2 (), @@ -306650,7 +306108,7 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N351_1_1 ( - .COUT (_N13793), + .COUT (_N13762), .Z (N351[1]), .CIN (), .I0 (wr_addr2[0]), @@ -306670,9 +306128,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N351_1_2 ( - .COUT (_N13794), + .COUT (_N13763), .Z (N351[2]), - .CIN (_N13793), + .CIN (_N13762), .I0 (wr_addr2[0]), .I1 (wr_addr2[1]), .I2 (wr_addr2[2]), @@ -306690,9 +306148,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N351_1_3 ( - .COUT (_N13795), + .COUT (_N13764), .Z (N351[3]), - .CIN (_N13794), + .CIN (_N13763), .I0 (), .I1 (wr_addr2[3]), .I2 (), @@ -306710,9 +306168,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N351_1_4 ( - .COUT (_N13796), + .COUT (_N13765), .Z (N351[4]), - .CIN (_N13795), + .CIN (_N13764), .I0 (), .I1 (wr_addr2[4]), .I2 (), @@ -306730,9 +306188,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N351_1_5 ( - .COUT (_N13797), + .COUT (_N13766), .Z (N351[5]), - .CIN (_N13796), + .CIN (_N13765), .I0 (), .I1 (wr_addr2[5]), .I2 (), @@ -306750,9 +306208,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N351_1_6 ( - .COUT (_N13798), + .COUT (_N13767), .Z (N351[6]), - .CIN (_N13797), + .CIN (_N13766), .I0 (), .I1 (wr_addr2[6]), .I2 (), @@ -306770,9 +306228,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N351_1_7 ( - .COUT (_N13799), + .COUT (_N13768), .Z (N351[7]), - .CIN (_N13798), + .CIN (_N13767), .I0 (), .I1 (wr_addr2[7]), .I2 (), @@ -306790,9 +306248,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N351_1_8 ( - .COUT (_N13800), + .COUT (_N13769), .Z (N351[8]), - .CIN (_N13799), + .CIN (_N13768), .I0 (), .I1 (wr_addr2[8]), .I2 (), @@ -306810,9 +306268,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N351_1_9 ( - .COUT (_N13801), + .COUT (_N13770), .Z (N351[9]), - .CIN (_N13800), + .CIN (_N13769), .I0 (), .I1 (wr_addr2[9]), .I2 (), @@ -306832,7 +306290,7 @@ module zoom_image_v1 N351_1_10 ( .COUT (), .Z (N351[10]), - .CIN (_N13801), + .CIN (_N13770), .I0 (), .I1 (wr_addr2[10]), .I2 (), @@ -306850,7 +306308,7 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N356_1_1 ( - .COUT (_N14628), + .COUT (_N13773), .Z (N356[1]), .CIN (), .I0 (wr_addr3[0]), @@ -306870,9 +306328,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N356_1_2 ( - .COUT (_N14629), + .COUT (_N13774), .Z (N356[2]), - .CIN (_N14628), + .CIN (_N13773), .I0 (wr_addr3[0]), .I1 (wr_addr3[1]), .I2 (wr_addr3[2]), @@ -306890,9 +306348,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N356_1_3 ( - .COUT (_N14630), + .COUT (_N13775), .Z (N356[3]), - .CIN (_N14629), + .CIN (_N13774), .I0 (), .I1 (wr_addr3[3]), .I2 (), @@ -306910,9 +306368,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N356_1_4 ( - .COUT (_N14631), + .COUT (_N13776), .Z (N356[4]), - .CIN (_N14630), + .CIN (_N13775), .I0 (), .I1 (wr_addr3[4]), .I2 (), @@ -306930,9 +306388,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N356_1_5 ( - .COUT (_N14632), + .COUT (_N13777), .Z (N356[5]), - .CIN (_N14631), + .CIN (_N13776), .I0 (), .I1 (wr_addr3[5]), .I2 (), @@ -306950,9 +306408,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N356_1_6 ( - .COUT (_N14633), + .COUT (_N13778), .Z (N356[6]), - .CIN (_N14632), + .CIN (_N13777), .I0 (), .I1 (wr_addr3[6]), .I2 (), @@ -306970,9 +306428,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N356_1_7 ( - .COUT (_N14634), + .COUT (_N13779), .Z (N356[7]), - .CIN (_N14633), + .CIN (_N13778), .I0 (), .I1 (wr_addr3[7]), .I2 (), @@ -306990,9 +306448,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N356_1_8 ( - .COUT (_N14635), + .COUT (_N13780), .Z (N356[8]), - .CIN (_N14634), + .CIN (_N13779), .I0 (), .I1 (wr_addr3[8]), .I2 (), @@ -307010,9 +306468,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N356_1_9 ( - .COUT (_N14636), + .COUT (_N13781), .Z (N356[9]), - .CIN (_N14635), + .CIN (_N13780), .I0 (), .I1 (wr_addr3[9]), .I2 (), @@ -307032,7 +306490,7 @@ module zoom_image_v1 N356_1_10 ( .COUT (), .Z (N356[10]), - .CIN (_N14636), + .CIN (_N13781), .I0 (), .I1 (wr_addr3[10]), .I2 (), @@ -307050,7 +306508,7 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N361_1_1 ( - .COUT (_N14926), + .COUT (_N14584), .Z (store_addr_add_one[1]), .CIN (), .I0 (store_addr[0]), @@ -307070,9 +306528,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N361_1_2 ( - .COUT (_N14927), + .COUT (_N14585), .Z (store_addr_add_one[2]), - .CIN (_N14926), + .CIN (_N14584), .I0 (store_addr[0]), .I1 (store_addr[1]), .I2 (store_addr[2]), @@ -307090,9 +306548,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N361_1_3 ( - .COUT (_N14928), + .COUT (_N14586), .Z (store_addr_add_one[3]), - .CIN (_N14927), + .CIN (_N14585), .I0 (), .I1 (store_addr[3]), .I2 (), @@ -307110,9 +306568,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N361_1_4 ( - .COUT (_N14929), + .COUT (_N14587), .Z (store_addr_add_one[4]), - .CIN (_N14928), + .CIN (_N14586), .I0 (), .I1 (store_addr[4]), .I2 (), @@ -307130,9 +306588,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N361_1_5 ( - .COUT (_N14930), + .COUT (_N14588), .Z (store_addr_add_one[5]), - .CIN (_N14929), + .CIN (_N14587), .I0 (), .I1 (store_addr[5]), .I2 (), @@ -307150,9 +306608,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N361_1_6 ( - .COUT (_N14931), + .COUT (_N14589), .Z (store_addr_add_one[6]), - .CIN (_N14930), + .CIN (_N14588), .I0 (), .I1 (store_addr[6]), .I2 (), @@ -307170,9 +306628,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N361_1_7 ( - .COUT (_N14932), + .COUT (_N14590), .Z (store_addr_add_one[7]), - .CIN (_N14931), + .CIN (_N14589), .I0 (), .I1 (store_addr[7]), .I2 (), @@ -307190,9 +306648,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N361_1_8 ( - .COUT (_N14933), + .COUT (_N14591), .Z (store_addr_add_one[8]), - .CIN (_N14932), + .CIN (_N14590), .I0 (), .I1 (store_addr[8]), .I2 (), @@ -307210,9 +306668,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N361_1_9 ( - .COUT (_N14934), + .COUT (_N14592), .Z (store_addr_add_one[9]), - .CIN (_N14933), + .CIN (_N14591), .I0 (), .I1 (store_addr[9]), .I2 (), @@ -307230,9 +306688,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N361_1_10 ( - .COUT (_N14935), + .COUT (_N14593), .Z (store_addr_add_one[10]), - .CIN (_N14934), + .CIN (_N14592), .I0 (), .I1 (store_addr[10]), .I2 (), @@ -307250,9 +306708,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N361_1_11 ( - .COUT (_N14936), + .COUT (_N14594), .Z (store_addr_add_one[11]), - .CIN (_N14935), + .CIN (_N14593), .I0 (), .I1 (store_addr[11]), .I2 (), @@ -307270,9 +306728,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N361_1_12 ( - .COUT (_N14937), + .COUT (_N14595), .Z (store_addr_add_one[12]), - .CIN (_N14936), + .CIN (_N14594), .I0 (), .I1 (store_addr[12]), .I2 (), @@ -307292,7 +306750,7 @@ module zoom_image_v1 N361_1_13 ( .COUT (), .Z (store_addr_add_one[13]), - .CIN (_N14937), + .CIN (_N14595), .I0 (), .I1 (store_addr[13]), .I2 (), @@ -307306,7 +306764,7 @@ module zoom_image_v1 GTP_LUT5 /* N368_mux4 */ #( .INIT(32'b00000000000000000001111111111111)) N368_mux4 ( - .Z (_N10267), + .Z (_N10287), .I0 (mult_h2[3]), .I1 (mult_h2[4]), .I2 (mult_h2[5]), @@ -307317,7 +306775,7 @@ module zoom_image_v1 GTP_LUT4 /* N368_mux9_4 */ #( .INIT(16'b0000000000000001)) N368_mux9_4 ( - .Z (_N105142), + .Z (_N105689), .I0 (mult_h2[9]), .I1 (mult_h2[10]), .I2 (mult_h2[11]), @@ -307328,11 +306786,11 @@ module zoom_image_v1 .INIT(32'b11001100100011001100110000000000)) N370 ( .Z (N1015[3]), - .I0 (_N10267), + .I0 (_N10287), .I1 (zoom_sta_param1), .I2 (mult_h2[8]), .I3 (mult_h2[13]), - .I4 (_N105142)); + .I4 (_N105689)); // LUT = (I1&I3)|(I1&~I2&I4)|(I0&I1&I4) ; // ../../sources/designs/zoom/zoom_image_v1.v:558 @@ -307623,7 +307081,7 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N387_2_1 ( - .COUT (_N14940), + .COUT (_N14876), .Z (N1006[1]), .CIN (), .I0 (mult_h2[0]), @@ -307643,9 +307101,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N387_2_2 ( - .COUT (_N14941), + .COUT (_N14877), .Z (N1006[2]), - .CIN (_N14940), + .CIN (_N14876), .I0 (mult_h2[0]), .I1 (mult_h2[1]), .I2 (mult_h2[2]), @@ -307663,9 +307121,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N387_2_3 ( - .COUT (_N14942), + .COUT (_N14878), .Z (N1006[3]), - .CIN (_N14941), + .CIN (_N14877), .I0 (), .I1 (mult_h2[3]), .I2 (), @@ -307683,9 +307141,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N387_2_4 ( - .COUT (_N14943), + .COUT (_N14879), .Z (N1006[4]), - .CIN (_N14942), + .CIN (_N14878), .I0 (), .I1 (mult_h2[4]), .I2 (), @@ -307703,9 +307161,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N387_2_5 ( - .COUT (_N14944), + .COUT (_N14880), .Z (N1006[5]), - .CIN (_N14943), + .CIN (_N14879), .I0 (), .I1 (mult_h2[5]), .I2 (), @@ -307723,9 +307181,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N387_2_6 ( - .COUT (_N14945), + .COUT (_N14881), .Z (N1006[6]), - .CIN (_N14944), + .CIN (_N14880), .I0 (), .I1 (mult_h2[6]), .I2 (), @@ -307743,9 +307201,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N387_2_7 ( - .COUT (_N14946), + .COUT (_N14882), .Z (N1006[7]), - .CIN (_N14945), + .CIN (_N14881), .I0 (), .I1 (mult_h2[7]), .I2 (), @@ -307763,9 +307221,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N387_2_8 ( - .COUT (_N14947), + .COUT (_N14883), .Z (N1006[8]), - .CIN (_N14946), + .CIN (_N14882), .I0 (), .I1 (mult_h2[8]), .I2 (), @@ -307785,7 +307243,7 @@ module zoom_image_v1 N387_2_9 ( .COUT (), .Z (N1006[9]), - .CIN (_N14947), + .CIN (_N14883), .I0 (), .I1 (mult_h2[9]), .I2 (), @@ -307831,7 +307289,7 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N458_1_1 ( - .COUT (_N14952), + .COUT (_N14888), .Z (N958[4]), .CIN (), .I0 (imag_addr0[3]), @@ -307851,9 +307309,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N458_1_2 ( - .COUT (_N14953), + .COUT (_N14889), .Z (N958[5]), - .CIN (_N14952), + .CIN (_N14888), .I0 (imag_addr0[3]), .I1 (imag_addr0[4]), .I2 (imag_addr0[5]), @@ -307871,9 +307329,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N458_1_3 ( - .COUT (_N14954), + .COUT (_N14890), .Z (N958[6]), - .CIN (_N14953), + .CIN (_N14889), .I0 (), .I1 (imag_addr0[6]), .I2 (), @@ -307891,9 +307349,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N458_1_4 ( - .COUT (_N14955), + .COUT (_N14891), .Z (N958[7]), - .CIN (_N14954), + .CIN (_N14890), .I0 (), .I1 (imag_addr0[7]), .I2 (), @@ -307911,9 +307369,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N458_1_5 ( - .COUT (_N14956), + .COUT (_N14892), .Z (N958[8]), - .CIN (_N14955), + .CIN (_N14891), .I0 (), .I1 (imag_addr0[8]), .I2 (), @@ -307933,7 +307391,7 @@ module zoom_image_v1 N458_1_6 ( .COUT (), .Z (N958[9]), - .CIN (_N14956), + .CIN (_N14892), .I0 (), .I1 (imag_addr0[9]), .I2 (), @@ -307951,7 +307409,7 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N464_1_1 ( - .COUT (_N14959), + .COUT (_N14895), .Z (N464[7]), .CIN (), .I0 (mult_h[6]), @@ -307971,9 +307429,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N464_1_2 ( - .COUT (_N14960), + .COUT (_N14896), .Z (N464[8]), - .CIN (_N14959), + .CIN (_N14895), .I0 (mult_h[6]), .I1 (mult_h[7]), .I2 (mult_h[8]), @@ -307991,9 +307449,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N464_1_3 ( - .COUT (_N14961), + .COUT (_N14897), .Z (N464[9]), - .CIN (_N14960), + .CIN (_N14896), .I0 (), .I1 (mult_h[9]), .I2 (), @@ -308011,9 +307469,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N464_1_4 ( - .COUT (_N14962), + .COUT (_N14898), .Z (N464[10]), - .CIN (_N14961), + .CIN (_N14897), .I0 (), .I1 (mult_h[10]), .I2 (), @@ -308031,9 +307489,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N464_1_5 ( - .COUT (_N14963), + .COUT (_N14899), .Z (N464[11]), - .CIN (_N14962), + .CIN (_N14898), .I0 (), .I1 (mult_h[11]), .I2 (), @@ -308051,9 +307509,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N464_1_6 ( - .COUT (_N14964), + .COUT (_N14900), .Z (N464[12]), - .CIN (_N14963), + .CIN (_N14899), .I0 (), .I1 (mult_h[12]), .I2 (), @@ -308071,9 +307529,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N464_1_7 ( - .COUT (_N14965), + .COUT (_N14901), .Z (N464[13]), - .CIN (_N14964), + .CIN (_N14900), .I0 (), .I1 (mult_h[13]), .I2 (), @@ -308091,9 +307549,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N464_1_8 ( - .COUT (_N14966), + .COUT (_N14902), .Z (N464[14]), - .CIN (_N14965), + .CIN (_N14901), .I0 (), .I1 (mult_h[14]), .I2 (), @@ -308111,9 +307569,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N464_1_9 ( - .COUT (_N14967), + .COUT (_N14903), .Z (N464[15]), - .CIN (_N14966), + .CIN (_N14902), .I0 (), .I1 (mult_h[15]), .I2 (), @@ -308131,9 +307589,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N464_1_10 ( - .COUT (_N14968), + .COUT (_N14904), .Z (N464[16]), - .CIN (_N14967), + .CIN (_N14903), .I0 (), .I1 (mult_h[16]), .I2 (), @@ -308151,9 +307609,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N464_1_11 ( - .COUT (_N14969), + .COUT (_N14905), .Z (N464[17]), - .CIN (_N14968), + .CIN (_N14904), .I0 (), .I1 (mult_h[17]), .I2 (), @@ -308171,9 +307629,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N464_1_12 ( - .COUT (_N14970), + .COUT (_N14906), .Z (N464[18]), - .CIN (_N14969), + .CIN (_N14905), .I0 (), .I1 (mult_h[18]), .I2 (), @@ -308191,9 +307649,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N464_1_13 ( - .COUT (_N14971), + .COUT (_N14907), .Z (N464[19]), - .CIN (_N14970), + .CIN (_N14906), .I0 (), .I1 (mult_h[19]), .I2 (), @@ -308213,7 +307671,7 @@ module zoom_image_v1 N464_1_14 ( .COUT (), .Z (N464[20]), - .CIN (_N14971), + .CIN (_N14907), .I0 (), .I1 (mult_h[20]), .I2 (), @@ -308231,7 +307689,7 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N465_1 ( - .COUT (_N16693), + .COUT (_N16632), .Z (N465[0]), .CIN (), .I0 (zoom_num1[0]), @@ -308251,9 +307709,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N465_2 ( - .COUT (_N16694), + .COUT (_N16633), .Z (N465[1]), - .CIN (_N16693), + .CIN (_N16632), .I0 (zoom_num1[0]), .I1 (image_w0[0]), .I2 (zoom_num1[1]), @@ -308271,9 +307729,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N465_3 ( - .COUT (_N16695), + .COUT (_N16634), .Z (N465[2]), - .CIN (_N16694), + .CIN (_N16633), .I0 (), .I1 (zoom_num1[2]), .I2 (image_w0[2]), @@ -308291,9 +307749,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N465_4 ( - .COUT (_N16696), + .COUT (_N16635), .Z (N465[3]), - .CIN (_N16695), + .CIN (_N16634), .I0 (), .I1 (zoom_num1[3]), .I2 (image_w0[3]), @@ -308311,9 +307769,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N465_5 ( - .COUT (_N16697), + .COUT (_N16636), .Z (N465[4]), - .CIN (_N16696), + .CIN (_N16635), .I0 (), .I1 (zoom_num1[4]), .I2 (image_w0[4]), @@ -308331,9 +307789,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N465_6 ( - .COUT (_N16698), + .COUT (_N16637), .Z (N465[5]), - .CIN (_N16697), + .CIN (_N16636), .I0 (), .I1 (zoom_num1[5]), .I2 (image_w0[5]), @@ -308351,9 +307809,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N465_7 ( - .COUT (_N16699), + .COUT (_N16638), .Z (N465[6]), - .CIN (_N16698), + .CIN (_N16637), .I0 (), .I1 (zoom_num1[6]), .I2 (image_w0[6]), @@ -308371,9 +307829,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N465_8 ( - .COUT (_N16700), + .COUT (_N16639), .Z (N465[7]), - .CIN (_N16699), + .CIN (_N16638), .I0 (), .I1 (zoom_num1[7]), .I2 (image_w0[7]), @@ -308391,9 +307849,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N465_9 ( - .COUT (_N16701), + .COUT (_N16640), .Z (N465[8]), - .CIN (_N16700), + .CIN (_N16639), .I0 (), .I1 (zoom_num1[8]), .I2 (image_w0[8]), @@ -308411,9 +307869,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N465_10 ( - .COUT (_N16702), + .COUT (_N16641), .Z (N465[9]), - .CIN (_N16701), + .CIN (_N16640), .I0 (), .I1 (image_w0[9]), .I2 (), @@ -308431,9 +307889,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N465_11 ( - .COUT (_N16703), + .COUT (_N16642), .Z (N465[10]), - .CIN (_N16702), + .CIN (_N16641), .I0 (), .I1 (image_w0[10]), .I2 (), @@ -308451,9 +307909,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N465_12 ( - .COUT (_N16704), + .COUT (_N16643), .Z (N465[11]), - .CIN (_N16703), + .CIN (_N16642), .I0 (), .I1 (image_w0[11]), .I2 (), @@ -308471,9 +307929,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N465_13 ( - .COUT (_N16705), + .COUT (_N16644), .Z (N465[12]), - .CIN (_N16704), + .CIN (_N16643), .I0 (), .I1 (image_w0[12]), .I2 (), @@ -308491,9 +307949,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N465_14 ( - .COUT (_N16706), + .COUT (_N16645), .Z (N465[13]), - .CIN (_N16705), + .CIN (_N16644), .I0 (), .I1 (image_w0[13]), .I2 (), @@ -308511,9 +307969,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N465_15 ( - .COUT (_N16707), + .COUT (_N16646), .Z (N465[14]), - .CIN (_N16706), + .CIN (_N16645), .I0 (), .I1 (image_w0[14]), .I2 (), @@ -308531,9 +307989,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N465_16 ( - .COUT (_N16708), + .COUT (_N16647), .Z (N465[15]), - .CIN (_N16707), + .CIN (_N16646), .I0 (), .I1 (image_w0[15]), .I2 (), @@ -308551,9 +308009,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N465_17 ( - .COUT (_N16709), + .COUT (_N16648), .Z (N465[16]), - .CIN (_N16708), + .CIN (_N16647), .I0 (), .I1 (image_w0[16]), .I2 (), @@ -308571,9 +308029,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N465_18 ( - .COUT (_N16710), + .COUT (_N16649), .Z (N465[17]), - .CIN (_N16709), + .CIN (_N16648), .I0 (), .I1 (image_w0[17]), .I2 (), @@ -308591,9 +308049,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N465_19 ( - .COUT (_N16711), + .COUT (_N16650), .Z (N465[18]), - .CIN (_N16710), + .CIN (_N16649), .I0 (), .I1 (image_w0[18]), .I2 (), @@ -308611,9 +308069,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N465_20 ( - .COUT (_N16712), + .COUT (_N16651), .Z (N465[19]), - .CIN (_N16711), + .CIN (_N16650), .I0 (), .I1 (image_w0[19]), .I2 (), @@ -308633,7 +308091,7 @@ module zoom_image_v1 N465_21 ( .COUT (), .Z (N465[20]), - .CIN (_N16712), + .CIN (_N16651), .I0 (), .I1 (image_w0[20]), .I2 (), @@ -308651,7 +308109,7 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N466_1 ( - .COUT (_N16715), + .COUT (_N16654), .Z (N466[0]), .CIN (), .I0 (zoom_num1[0]), @@ -308671,9 +308129,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N466_2 ( - .COUT (_N16716), + .COUT (_N16655), .Z (N466[1]), - .CIN (_N16715), + .CIN (_N16654), .I0 (zoom_num1[0]), .I1 (image_h0[0]), .I2 (zoom_num1[1]), @@ -308691,9 +308149,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N466_3 ( - .COUT (_N16717), + .COUT (_N16656), .Z (N466[2]), - .CIN (_N16716), + .CIN (_N16655), .I0 (), .I1 (zoom_num1[2]), .I2 (image_h0[2]), @@ -308711,9 +308169,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N466_4 ( - .COUT (_N16718), + .COUT (_N16657), .Z (N466[3]), - .CIN (_N16717), + .CIN (_N16656), .I0 (), .I1 (zoom_num1[3]), .I2 (image_h0[3]), @@ -308731,9 +308189,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N466_5 ( - .COUT (_N16719), + .COUT (_N16658), .Z (N466[4]), - .CIN (_N16718), + .CIN (_N16657), .I0 (), .I1 (zoom_num1[4]), .I2 (image_h0[4]), @@ -308751,9 +308209,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N466_6 ( - .COUT (_N16720), + .COUT (_N16659), .Z (N466[5]), - .CIN (_N16719), + .CIN (_N16658), .I0 (), .I1 (zoom_num1[5]), .I2 (image_h0[5]), @@ -308771,9 +308229,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N466_7 ( - .COUT (_N16721), + .COUT (_N16660), .Z (N466[6]), - .CIN (_N16720), + .CIN (_N16659), .I0 (), .I1 (zoom_num1[6]), .I2 (image_h0[6]), @@ -308791,9 +308249,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N466_8 ( - .COUT (_N16722), + .COUT (_N16661), .Z (N466[7]), - .CIN (_N16721), + .CIN (_N16660), .I0 (), .I1 (zoom_num1[7]), .I2 (image_h0[7]), @@ -308811,9 +308269,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N466_9 ( - .COUT (_N16723), + .COUT (_N16662), .Z (N466[8]), - .CIN (_N16722), + .CIN (_N16661), .I0 (), .I1 (zoom_num1[8]), .I2 (image_h0[8]), @@ -308831,9 +308289,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N466_10 ( - .COUT (_N16724), + .COUT (_N16663), .Z (N466[9]), - .CIN (_N16723), + .CIN (_N16662), .I0 (), .I1 (image_h0[9]), .I2 (), @@ -308851,9 +308309,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N466_11 ( - .COUT (_N16725), + .COUT (_N16664), .Z (N466[10]), - .CIN (_N16724), + .CIN (_N16663), .I0 (), .I1 (image_h0[10]), .I2 (), @@ -308871,9 +308329,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N466_12 ( - .COUT (_N16726), + .COUT (_N16665), .Z (N466[11]), - .CIN (_N16725), + .CIN (_N16664), .I0 (), .I1 (image_h0[11]), .I2 (), @@ -308891,9 +308349,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N466_13 ( - .COUT (_N16727), + .COUT (_N16666), .Z (N466[12]), - .CIN (_N16726), + .CIN (_N16665), .I0 (), .I1 (image_h0[12]), .I2 (), @@ -308911,9 +308369,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N466_14 ( - .COUT (_N16728), + .COUT (_N16667), .Z (N466[13]), - .CIN (_N16727), + .CIN (_N16666), .I0 (), .I1 (image_h0[13]), .I2 (), @@ -308931,9 +308389,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N466_15 ( - .COUT (_N16729), + .COUT (_N16668), .Z (N466[14]), - .CIN (_N16728), + .CIN (_N16667), .I0 (), .I1 (image_h0[14]), .I2 (), @@ -308951,9 +308409,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N466_16 ( - .COUT (_N16730), + .COUT (_N16669), .Z (N466[15]), - .CIN (_N16729), + .CIN (_N16668), .I0 (), .I1 (image_h0[15]), .I2 (), @@ -308971,9 +308429,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N466_17 ( - .COUT (_N16731), + .COUT (_N16670), .Z (N466[16]), - .CIN (_N16730), + .CIN (_N16669), .I0 (), .I1 (image_h0[16]), .I2 (), @@ -308991,9 +308449,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N466_18 ( - .COUT (_N16732), + .COUT (_N16671), .Z (N466[17]), - .CIN (_N16731), + .CIN (_N16670), .I0 (), .I1 (image_h0[17]), .I2 (), @@ -309011,9 +308469,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N466_19 ( - .COUT (_N16733), + .COUT (_N16672), .Z (N466[18]), - .CIN (_N16732), + .CIN (_N16671), .I0 (), .I1 (image_h0[18]), .I2 (), @@ -309031,9 +308489,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N466_20 ( - .COUT (_N16734), + .COUT (_N16673), .Z (N466[19]), - .CIN (_N16733), + .CIN (_N16672), .I0 (), .I1 (image_h0[19]), .I2 (), @@ -309053,7 +308511,7 @@ module zoom_image_v1 N466_21 ( .COUT (), .Z (N466[20]), - .CIN (_N16734), + .CIN (_N16673), .I0 (), .I1 (image_h0[20]), .I2 (), @@ -309071,7 +308529,7 @@ module zoom_image_v1 .I4_TO_CARRY("FALSE"), .I4_TO_LUT("FALSE")) N468_1_0 ( - .COUT (_N14973), + .COUT (_N14909), .Z (), .CIN (), .I0 (), @@ -309091,9 +308549,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N468_1_1 ( - .COUT (_N14974), + .COUT (_N14910), .Z (N922[1]), - .CIN (_N14973), + .CIN (_N14909), .I0 (), .I1 (rd_addr[1]), .I2 (coe_valid[2]), @@ -309111,9 +308569,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N468_1_2 ( - .COUT (_N14975), + .COUT (_N14911), .Z (N922[2]), - .CIN (_N14974), + .CIN (_N14910), .I0 (), .I1 (rd_addr[2]), .I2 (coe_valid[2]), @@ -309131,9 +308589,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N468_1_3 ( - .COUT (_N14976), + .COUT (_N14912), .Z (N922[3]), - .CIN (_N14975), + .CIN (_N14911), .I0 (), .I1 (rd_addr[3]), .I2 (coe_valid[2]), @@ -309151,9 +308609,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N468_1_4 ( - .COUT (_N14977), + .COUT (_N14913), .Z (N922[4]), - .CIN (_N14976), + .CIN (_N14912), .I0 (), .I1 (rd_addr[4]), .I2 (coe_valid[2]), @@ -309171,9 +308629,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N468_1_5 ( - .COUT (_N14978), + .COUT (_N14914), .Z (N922[5]), - .CIN (_N14977), + .CIN (_N14913), .I0 (), .I1 (rd_addr[5]), .I2 (coe_valid[2]), @@ -309191,9 +308649,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N468_1_6 ( - .COUT (_N14979), + .COUT (_N14915), .Z (N922[6]), - .CIN (_N14978), + .CIN (_N14914), .I0 (), .I1 (rd_addr[6]), .I2 (coe_valid[2]), @@ -309211,9 +308669,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N468_1_7 ( - .COUT (_N14980), + .COUT (_N14916), .Z (N922[7]), - .CIN (_N14979), + .CIN (_N14915), .I0 (), .I1 (rd_addr[7]), .I2 (coe_valid[2]), @@ -309231,9 +308689,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N468_1_8 ( - .COUT (_N14981), + .COUT (_N14917), .Z (N922[8]), - .CIN (_N14980), + .CIN (_N14916), .I0 (), .I1 (rd_addr[8]), .I2 (coe_valid[2]), @@ -309251,9 +308709,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N468_1_9 ( - .COUT (_N14982), + .COUT (_N14918), .Z (N922[9]), - .CIN (_N14981), + .CIN (_N14917), .I0 (), .I1 (rd_addr[9]), .I2 (coe_valid[2]), @@ -309273,7 +308731,7 @@ module zoom_image_v1 N468_1_10 ( .COUT (), .Z (N922[10]), - .CIN (_N14982), + .CIN (_N14918), .I0 (), .I1 (rd_addr[10]), .I2 (coe_valid[2]), @@ -310059,7 +309517,7 @@ module zoom_image_v1 .I0 (image_h_valid[0]), .I1 (image_w_valid[0])); // LUT = (I0)|(I1) ; - // ../../sources/designs/zoom/zoom_image_v1.v:715 + // ../../sources/designs/zoom/zoom_image_v1.v:711 GTP_LUT2 /* N492_1 */ #( .INIT(4'b1110)) @@ -310068,12 +309526,12 @@ module zoom_image_v1 .I0 (image_h_valid[1]), .I1 (image_w_valid[1])); // LUT = (I0)|(I1) ; - // ../../sources/designs/zoom/zoom_image_v1.v:715 + // ../../sources/designs/zoom/zoom_image_v1.v:711 GTP_LUT2 /* N515_mux1 */ #( .INIT(4'b0001)) N515_mux1 ( - .Z (_N10283), + .Z (_N10303), .I0 (image_w2[15]), .I1 (image_w2[16])); // LUT = ~I0&~I1 ; @@ -310082,20 +309540,20 @@ module zoom_image_v1 .INIT(32'b11111111111111111111111111110100)) N518_vname ( .Z (N518), - .I0 (_N10283), + .I0 (_N10303), .I1 (image_w2[17]), .I2 (image_w2[18]), .I3 (image_w2[19]), .I4 (image_w2[20])); // defparam N518_vname.orig_name = N518; // LUT = (I2)|(I3)|(I4)|(~I0&I1) ; - // ../../sources/designs/zoom/zoom_image_v1.v:722 + // ../../sources/designs/zoom/zoom_image_v1.v:718 GTP_LUT5 /* N518_inv */ #( .INIT(32'b00000000000000000000000000001011)) N518_inv_vname ( .Z (N518_inv), - .I0 (_N10283), + .I0 (_N10303), .I1 (image_w2[17]), .I2 (image_w2[18]), .I3 (image_w2[19]), @@ -310106,7 +309564,7 @@ module zoom_image_v1 GTP_LUT4 /* N530_mux3_4 */ #( .INIT(16'b0111111111111111)) N530_mux3_4 ( - .Z (_N10299), + .Z (_N10319), .I0 (image_h2[7]), .I1 (image_h2[8]), .I2 (image_h2[9]), @@ -310116,8 +309574,8 @@ module zoom_image_v1 GTP_LUT5 /* N530_mux7_3 */ #( .INIT(32'b00000010111111111111111111111111)) N530_mux7_3 ( - .Z (_N10307), - .I0 (_N10299), + .Z (_N10327), + .I0 (_N10319), .I1 (image_h2[11]), .I2 (image_h2[12]), .I3 (image_h2[13]), @@ -310127,7 +309585,7 @@ module zoom_image_v1 GTP_LUT3 /* N530_mux12_3 */ #( .INIT(8'b00000001)) N530_mux12_3 ( - .Z (_N105114), + .Z (_N105661), .I0 (image_h2[17]), .I1 (image_h2[18]), .I2 (image_h2[19])); @@ -310137,24 +309595,24 @@ module zoom_image_v1 .INIT(32'b11111111110100001111111111111111)) N533_vname ( .Z (N533), - .I0 (_N10307), + .I0 (_N10327), .I1 (image_h2[15]), .I2 (image_h2[16]), .I3 (image_h2[20]), - .I4 (_N105114)); + .I4 (_N105661)); // defparam N533_vname.orig_name = N533; // LUT = (~I4)|(I3)|(~I0&I2)|(I1&I2) ; - // ../../sources/designs/zoom/zoom_image_v1.v:725 + // ../../sources/designs/zoom/zoom_image_v1.v:721 GTP_LUT5 /* N533_inv */ #( .INIT(32'b00000000001011110000000000000000)) N533_inv_vname ( .Z (N533_inv), - .I0 (_N10307), + .I0 (_N10327), .I1 (image_h2[15]), .I2 (image_h2[16]), .I3 (image_h2[20]), - .I4 (_N105114)); + .I4 (_N105661)); // defparam N533_inv_vname.orig_name = N533_inv; // LUT = (~I2&~I3&I4)|(I0&~I1&~I3&I4) ; @@ -310176,7 +309634,7 @@ module zoom_image_v1 .ID ()); // LUT = I1^I0 ; // CARRY = (1'b0) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:738 + // ../../sources/designs/zoom/zoom_image_v1.v:733 GTP_LUT5CARRY /* \N566_1.fsub_2 */ #( .INIT(32'b00011110000111100000000100000001), @@ -310196,7 +309654,7 @@ module zoom_image_v1 .ID ()); // LUT = (I1&~I2)|(I0&~I2)|(~I0&~I1&I2) ; // CARRY = (~I0&~I1&~I2) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:738 + // ../../sources/designs/zoom/zoom_image_v1.v:733 GTP_LUT5CARRY /* \N566_1.fsub_3 */ #( .INIT(32'b10011001100110010011001100110011), @@ -310216,7 +309674,7 @@ module zoom_image_v1 .ID ()); // LUT = ~I1^CIN ; // CARRY = (~I1) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:738 + // ../../sources/designs/zoom/zoom_image_v1.v:733 GTP_LUT5CARRY /* \N566_1.fsub_4 */ #( .INIT(32'b10011001100110010011001100110011), @@ -310236,7 +309694,7 @@ module zoom_image_v1 .ID ()); // LUT = ~I1^CIN ; // CARRY = (~I1) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:738 + // ../../sources/designs/zoom/zoom_image_v1.v:733 GTP_LUT5CARRY /* \N566_1.fsub_5 */ #( .INIT(32'b10011001100110010011001100110011), @@ -310256,7 +309714,7 @@ module zoom_image_v1 .ID ()); // LUT = ~I1^CIN ; // CARRY = (~I1) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:738 + // ../../sources/designs/zoom/zoom_image_v1.v:733 GTP_LUT5CARRY /* \N566_1.fsub_6 */ #( .INIT(32'b10011001100110010011001100110011), @@ -310276,7 +309734,7 @@ module zoom_image_v1 .ID ()); // LUT = ~I1^CIN ; // CARRY = (~I1) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:738 + // ../../sources/designs/zoom/zoom_image_v1.v:733 GTP_LUT5CARRY /* \N566_1.fsub_7 */ #( .INIT(32'b10101010101010100000000000000000), @@ -310296,7 +309754,7 @@ module zoom_image_v1 .ID ()); // LUT = CIN ; // CARRY = (1'b0) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:738 + // ../../sources/designs/zoom/zoom_image_v1.v:733 GTP_LUT5CARRY /* \N572_1.fsub_1 */ #( .INIT(32'b01100110011001100000000000000000), @@ -310316,7 +309774,7 @@ module zoom_image_v1 .ID ()); // LUT = I1^I0 ; // CARRY = (1'b0) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:740 + // ../../sources/designs/zoom/zoom_image_v1.v:735 GTP_LUT5CARRY /* \N572_1.fsub_2 */ #( .INIT(32'b00011110000111100000000100000001), @@ -310336,7 +309794,7 @@ module zoom_image_v1 .ID ()); // LUT = (I1&~I2)|(I0&~I2)|(~I0&~I1&I2) ; // CARRY = (~I0&~I1&~I2) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:740 + // ../../sources/designs/zoom/zoom_image_v1.v:735 GTP_LUT5CARRY /* \N572_1.fsub_3 */ #( .INIT(32'b10011001100110010011001100110011), @@ -310356,7 +309814,7 @@ module zoom_image_v1 .ID ()); // LUT = ~I1^CIN ; // CARRY = (~I1) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:740 + // ../../sources/designs/zoom/zoom_image_v1.v:735 GTP_LUT5CARRY /* \N572_1.fsub_4 */ #( .INIT(32'b10011001100110010011001100110011), @@ -310376,7 +309834,7 @@ module zoom_image_v1 .ID ()); // LUT = ~I1^CIN ; // CARRY = (~I1) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:740 + // ../../sources/designs/zoom/zoom_image_v1.v:735 GTP_LUT5CARRY /* \N572_1.fsub_5 */ #( .INIT(32'b10011001100110010011001100110011), @@ -310396,7 +309854,7 @@ module zoom_image_v1 .ID ()); // LUT = ~I1^CIN ; // CARRY = (~I1) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:740 + // ../../sources/designs/zoom/zoom_image_v1.v:735 GTP_LUT5CARRY /* \N572_1.fsub_6 */ #( .INIT(32'b10011001100110010011001100110011), @@ -310416,7 +309874,7 @@ module zoom_image_v1 .ID ()); // LUT = ~I1^CIN ; // CARRY = (~I1) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:740 + // ../../sources/designs/zoom/zoom_image_v1.v:735 GTP_LUT5CARRY /* \N572_1.fsub_7 */ #( .INIT(32'b10101010101010100000000000000000), @@ -310436,7 +309894,7 @@ module zoom_image_v1 .ID ()); // LUT = CIN ; // CARRY = (1'b0) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:740 + // ../../sources/designs/zoom/zoom_image_v1.v:735 GTP_LUT5CARRY /* N624_1 */ #( .INIT(32'b00000000000000000000000000000000), @@ -310445,7 +309903,7 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N624_1 ( - .COUT (_N16749), + .COUT (_N16676), .Z (), .CIN (), .I0 (), @@ -310456,7 +309914,7 @@ module zoom_image_v1 .ID ()); // LUT = 1'b0 ; // CARRY = (1'b0) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:866 + // ../../sources/designs/zoom/zoom_image_v1.v:861 GTP_LUT5CARRY /* N624_2 */ #( .INIT(32'b00000000000000001111100010000000), @@ -310465,9 +309923,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N624_2 ( - .COUT (_N16750), + .COUT (_N16677), .Z (), - .CIN (_N16749), + .CIN (_N16676), .I0 (\mult_image1_0[0] [0] ), .I1 (\mult_image1[0] [0] ), .I2 (\mult_image1_0[0] [1] ), @@ -310476,7 +309934,7 @@ module zoom_image_v1 .ID ()); // LUT = 1'b0 ; // CARRY = ((I2&I3)|(I0&I1&I3)|(I0&I1&I2)) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:866 + // ../../sources/designs/zoom/zoom_image_v1.v:861 GTP_LUT5CARRY /* N624_3 */ #( .INIT(32'b10010110100101100011110000111100), @@ -310485,9 +309943,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N624_3 ( - .COUT (_N16751), + .COUT (_N16678), .Z (), - .CIN (_N16750), + .CIN (_N16677), .I0 (), .I1 (\mult_image1_0[0] [2] ), .I2 (\mult_image1[0] [2] ), @@ -310496,7 +309954,7 @@ module zoom_image_v1 .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:866 + // ../../sources/designs/zoom/zoom_image_v1.v:861 GTP_LUT5CARRY /* N624_4 */ #( .INIT(32'b10010110100101100011110000111100), @@ -310505,9 +309963,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N624_4 ( - .COUT (_N16752), + .COUT (_N16679), .Z (), - .CIN (_N16751), + .CIN (_N16678), .I0 (), .I1 (\mult_image1_0[0] [3] ), .I2 (\mult_image1[0] [3] ), @@ -310516,7 +309974,7 @@ module zoom_image_v1 .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:866 + // ../../sources/designs/zoom/zoom_image_v1.v:861 GTP_LUT5CARRY /* N624_5 */ #( .INIT(32'b10010110100101100011110000111100), @@ -310525,9 +309983,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N624_5 ( - .COUT (_N16753), + .COUT (_N16680), .Z (), - .CIN (_N16752), + .CIN (_N16679), .I0 (), .I1 (\mult_image1_0[0] [4] ), .I2 (\mult_image1[0] [4] ), @@ -310536,7 +309994,7 @@ module zoom_image_v1 .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:866 + // ../../sources/designs/zoom/zoom_image_v1.v:861 GTP_LUT5CARRY /* N624_6 */ #( .INIT(32'b10010110100101100011110000111100), @@ -310545,9 +310003,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N624_6 ( - .COUT (_N16754), + .COUT (_N16681), .Z (), - .CIN (_N16753), + .CIN (_N16680), .I0 (), .I1 (\mult_image1_0[0] [5] ), .I2 (\mult_image1[0] [5] ), @@ -310556,7 +310014,7 @@ module zoom_image_v1 .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:866 + // ../../sources/designs/zoom/zoom_image_v1.v:861 GTP_LUT5CARRY /* N624_7 */ #( .INIT(32'b10010110100101100011110000111100), @@ -310565,9 +310023,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N624_7 ( - .COUT (_N16755), + .COUT (_N16682), .Z (), - .CIN (_N16754), + .CIN (_N16681), .I0 (), .I1 (\mult_image1_0[0] [6] ), .I2 (\mult_image1[0] [6] ), @@ -310576,7 +310034,7 @@ module zoom_image_v1 .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:866 + // ../../sources/designs/zoom/zoom_image_v1.v:861 GTP_LUT5CARRY /* N624_8 */ #( .INIT(32'b10010110100101100011110000111100), @@ -310585,9 +310043,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N624_8 ( - .COUT (_N16756), + .COUT (_N16683), .Z (N624[7]), - .CIN (_N16755), + .CIN (_N16682), .I0 (), .I1 (\mult_image1_0[0] [7] ), .I2 (\mult_image1[0] [7] ), @@ -310596,7 +310054,7 @@ module zoom_image_v1 .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:866 + // ../../sources/designs/zoom/zoom_image_v1.v:861 GTP_LUT5CARRY /* N624_9 */ #( .INIT(32'b10010110100101100011110000111100), @@ -310605,9 +310063,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N624_9 ( - .COUT (_N16757), + .COUT (_N16684), .Z (N624[8]), - .CIN (_N16756), + .CIN (_N16683), .I0 (), .I1 (\mult_image1_0[0] [8] ), .I2 (\mult_image1[0] [8] ), @@ -310616,7 +310074,7 @@ module zoom_image_v1 .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:866 + // ../../sources/designs/zoom/zoom_image_v1.v:861 GTP_LUT5CARRY /* N624_10 */ #( .INIT(32'b10010110100101100011110000111100), @@ -310625,9 +310083,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N624_10 ( - .COUT (_N16758), + .COUT (_N16685), .Z (N624[9]), - .CIN (_N16757), + .CIN (_N16684), .I0 (), .I1 (\mult_image1_0[0] [9] ), .I2 (\mult_image1[0] [9] ), @@ -310636,7 +310094,7 @@ module zoom_image_v1 .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:866 + // ../../sources/designs/zoom/zoom_image_v1.v:861 GTP_LUT5CARRY /* N624_11 */ #( .INIT(32'b10010110100101100011110000111100), @@ -310645,9 +310103,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N624_11 ( - .COUT (_N16759), + .COUT (_N16686), .Z (N624[10]), - .CIN (_N16758), + .CIN (_N16685), .I0 (), .I1 (\mult_image1_0[0] [10] ), .I2 (\mult_image1[0] [10] ), @@ -310656,7 +310114,7 @@ module zoom_image_v1 .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:866 + // ../../sources/designs/zoom/zoom_image_v1.v:861 GTP_LUT5CARRY /* N624_12 */ #( .INIT(32'b10010110100101100011110000111100), @@ -310667,7 +310125,7 @@ module zoom_image_v1 N624_12 ( .COUT (), .Z (N624[11]), - .CIN (_N16759), + .CIN (_N16686), .I0 (), .I1 (\mult_image1_0[0] [11] ), .I2 (\mult_image1[0] [11] ), @@ -310676,7 +310134,7 @@ module zoom_image_v1 .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:866 + // ../../sources/designs/zoom/zoom_image_v1.v:861 GTP_LUT5CARRY /* N634_1 */ #( .INIT(32'b00000000000000000000000000000000), @@ -310685,7 +310143,7 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N634_1 ( - .COUT (_N16762), + .COUT (_N16689), .Z (), .CIN (), .I0 (), @@ -310696,7 +310154,7 @@ module zoom_image_v1 .ID ()); // LUT = 1'b0 ; // CARRY = (1'b0) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:866 + // ../../sources/designs/zoom/zoom_image_v1.v:861 GTP_LUT5CARRY /* N634_2 */ #( .INIT(32'b00000000000000001111100010000000), @@ -310705,9 +310163,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N634_2 ( - .COUT (_N16763), + .COUT (_N16690), .Z (), - .CIN (_N16762), + .CIN (_N16689), .I0 (\mult_image1_0[1] [0] ), .I1 (\mult_image1[1] [0] ), .I2 (\mult_image1_0[1] [1] ), @@ -310716,7 +310174,7 @@ module zoom_image_v1 .ID ()); // LUT = 1'b0 ; // CARRY = ((I2&I3)|(I0&I1&I3)|(I0&I1&I2)) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:866 + // ../../sources/designs/zoom/zoom_image_v1.v:861 GTP_LUT5CARRY /* N634_3 */ #( .INIT(32'b10010110100101100011110000111100), @@ -310725,9 +310183,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N634_3 ( - .COUT (_N16764), + .COUT (_N16691), .Z (), - .CIN (_N16763), + .CIN (_N16690), .I0 (), .I1 (\mult_image1_0[1] [2] ), .I2 (\mult_image1[1] [2] ), @@ -310736,7 +310194,7 @@ module zoom_image_v1 .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:866 + // ../../sources/designs/zoom/zoom_image_v1.v:861 GTP_LUT5CARRY /* N634_4 */ #( .INIT(32'b10010110100101100011110000111100), @@ -310745,9 +310203,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N634_4 ( - .COUT (_N16765), + .COUT (_N16692), .Z (), - .CIN (_N16764), + .CIN (_N16691), .I0 (), .I1 (\mult_image1_0[1] [3] ), .I2 (\mult_image1[1] [3] ), @@ -310756,7 +310214,7 @@ module zoom_image_v1 .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:866 + // ../../sources/designs/zoom/zoom_image_v1.v:861 GTP_LUT5CARRY /* N634_5 */ #( .INIT(32'b10010110100101100011110000111100), @@ -310765,9 +310223,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N634_5 ( - .COUT (_N16766), + .COUT (_N16693), .Z (), - .CIN (_N16765), + .CIN (_N16692), .I0 (), .I1 (\mult_image1_0[1] [4] ), .I2 (\mult_image1[1] [4] ), @@ -310776,7 +310234,7 @@ module zoom_image_v1 .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:866 + // ../../sources/designs/zoom/zoom_image_v1.v:861 GTP_LUT5CARRY /* N634_6 */ #( .INIT(32'b10010110100101100011110000111100), @@ -310785,9 +310243,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N634_6 ( - .COUT (_N16767), + .COUT (_N16694), .Z (), - .CIN (_N16766), + .CIN (_N16693), .I0 (), .I1 (\mult_image1_0[1] [5] ), .I2 (\mult_image1[1] [5] ), @@ -310796,7 +310254,7 @@ module zoom_image_v1 .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:866 + // ../../sources/designs/zoom/zoom_image_v1.v:861 GTP_LUT5CARRY /* N634_7 */ #( .INIT(32'b10010110100101100011110000111100), @@ -310805,9 +310263,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N634_7 ( - .COUT (_N16768), + .COUT (_N16695), .Z (), - .CIN (_N16767), + .CIN (_N16694), .I0 (), .I1 (\mult_image1_0[1] [6] ), .I2 (\mult_image1[1] [6] ), @@ -310816,7 +310274,7 @@ module zoom_image_v1 .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:866 + // ../../sources/designs/zoom/zoom_image_v1.v:861 GTP_LUT5CARRY /* N634_8 */ #( .INIT(32'b10010110100101100011110000111100), @@ -310825,9 +310283,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N634_8 ( - .COUT (_N16769), + .COUT (_N16696), .Z (N634[7]), - .CIN (_N16768), + .CIN (_N16695), .I0 (), .I1 (\mult_image1_0[1] [7] ), .I2 (\mult_image1[1] [7] ), @@ -310836,7 +310294,7 @@ module zoom_image_v1 .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:866 + // ../../sources/designs/zoom/zoom_image_v1.v:861 GTP_LUT5CARRY /* N634_9 */ #( .INIT(32'b10010110100101100011110000111100), @@ -310845,9 +310303,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N634_9 ( - .COUT (_N16770), + .COUT (_N16697), .Z (N634[8]), - .CIN (_N16769), + .CIN (_N16696), .I0 (), .I1 (\mult_image1_0[1] [8] ), .I2 (\mult_image1[1] [8] ), @@ -310856,7 +310314,7 @@ module zoom_image_v1 .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:866 + // ../../sources/designs/zoom/zoom_image_v1.v:861 GTP_LUT5CARRY /* N634_10 */ #( .INIT(32'b10010110100101100011110000111100), @@ -310865,9 +310323,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N634_10 ( - .COUT (_N16771), + .COUT (_N16698), .Z (N634[9]), - .CIN (_N16770), + .CIN (_N16697), .I0 (), .I1 (\mult_image1_0[1] [9] ), .I2 (\mult_image1[1] [9] ), @@ -310876,7 +310334,7 @@ module zoom_image_v1 .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:866 + // ../../sources/designs/zoom/zoom_image_v1.v:861 GTP_LUT5CARRY /* N634_11 */ #( .INIT(32'b10010110100101100011110000111100), @@ -310885,9 +310343,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N634_11 ( - .COUT (_N16772), + .COUT (_N16699), .Z (N634[10]), - .CIN (_N16771), + .CIN (_N16698), .I0 (), .I1 (\mult_image1_0[1] [10] ), .I2 (\mult_image1[1] [10] ), @@ -310896,7 +310354,7 @@ module zoom_image_v1 .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:866 + // ../../sources/designs/zoom/zoom_image_v1.v:861 GTP_LUT5CARRY /* N634_12 */ #( .INIT(32'b10010110100101100011110000111100), @@ -310905,9 +310363,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N634_12 ( - .COUT (_N16773), + .COUT (_N16700), .Z (N634[11]), - .CIN (_N16772), + .CIN (_N16699), .I0 (), .I1 (\mult_image1_0[1] [11] ), .I2 (\mult_image1[1] [11] ), @@ -310916,7 +310374,7 @@ module zoom_image_v1 .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:866 + // ../../sources/designs/zoom/zoom_image_v1.v:861 GTP_LUT5CARRY /* N634_13 */ #( .INIT(32'b10010110100101100011110000111100), @@ -310927,7 +310385,7 @@ module zoom_image_v1 N634_13 ( .COUT (), .Z (N634[12]), - .CIN (_N16773), + .CIN (_N16700), .I0 (), .I1 (\mult_image1_0[1] [12] ), .I2 (\mult_image1[1] [12] ), @@ -310936,7 +310394,7 @@ module zoom_image_v1 .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:866 + // ../../sources/designs/zoom/zoom_image_v1.v:861 GTP_LUT5CARRY /* N644_1 */ #( .INIT(32'b00000000000000000000000000000000), @@ -310945,7 +310403,7 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N644_1 ( - .COUT (_N16776), + .COUT (_N16703), .Z (), .CIN (), .I0 (), @@ -310956,7 +310414,7 @@ module zoom_image_v1 .ID ()); // LUT = 1'b0 ; // CARRY = (1'b0) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:866 + // ../../sources/designs/zoom/zoom_image_v1.v:861 GTP_LUT5CARRY /* N644_2 */ #( .INIT(32'b00000000000000001111100010000000), @@ -310965,9 +310423,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N644_2 ( - .COUT (_N16777), + .COUT (_N16704), .Z (), - .CIN (_N16776), + .CIN (_N16703), .I0 (\mult_image1_0[2] [0] ), .I1 (\mult_image1[2] [0] ), .I2 (\mult_image1_0[2] [1] ), @@ -310976,7 +310434,7 @@ module zoom_image_v1 .ID ()); // LUT = 1'b0 ; // CARRY = ((I2&I3)|(I0&I1&I3)|(I0&I1&I2)) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:866 + // ../../sources/designs/zoom/zoom_image_v1.v:861 GTP_LUT5CARRY /* N644_3 */ #( .INIT(32'b10010110100101100011110000111100), @@ -310985,9 +310443,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N644_3 ( - .COUT (_N16778), + .COUT (_N16705), .Z (), - .CIN (_N16777), + .CIN (_N16704), .I0 (), .I1 (\mult_image1_0[2] [2] ), .I2 (\mult_image1[2] [2] ), @@ -310996,7 +310454,7 @@ module zoom_image_v1 .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:866 + // ../../sources/designs/zoom/zoom_image_v1.v:861 GTP_LUT5CARRY /* N644_4 */ #( .INIT(32'b10010110100101100011110000111100), @@ -311005,9 +310463,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N644_4 ( - .COUT (_N16779), + .COUT (_N16706), .Z (), - .CIN (_N16778), + .CIN (_N16705), .I0 (), .I1 (\mult_image1_0[2] [3] ), .I2 (\mult_image1[2] [3] ), @@ -311016,7 +310474,7 @@ module zoom_image_v1 .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:866 + // ../../sources/designs/zoom/zoom_image_v1.v:861 GTP_LUT5CARRY /* N644_5 */ #( .INIT(32'b10010110100101100011110000111100), @@ -311025,9 +310483,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N644_5 ( - .COUT (_N16780), + .COUT (_N16707), .Z (), - .CIN (_N16779), + .CIN (_N16706), .I0 (), .I1 (\mult_image1_0[2] [4] ), .I2 (\mult_image1[2] [4] ), @@ -311036,7 +310494,7 @@ module zoom_image_v1 .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:866 + // ../../sources/designs/zoom/zoom_image_v1.v:861 GTP_LUT5CARRY /* N644_6 */ #( .INIT(32'b10010110100101100011110000111100), @@ -311045,9 +310503,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N644_6 ( - .COUT (_N16781), + .COUT (_N16708), .Z (), - .CIN (_N16780), + .CIN (_N16707), .I0 (), .I1 (\mult_image1_0[2] [5] ), .I2 (\mult_image1[2] [5] ), @@ -311056,7 +310514,7 @@ module zoom_image_v1 .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:866 + // ../../sources/designs/zoom/zoom_image_v1.v:861 GTP_LUT5CARRY /* N644_7 */ #( .INIT(32'b10010110100101100011110000111100), @@ -311065,9 +310523,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N644_7 ( - .COUT (_N16782), + .COUT (_N16709), .Z (), - .CIN (_N16781), + .CIN (_N16708), .I0 (), .I1 (\mult_image1_0[2] [6] ), .I2 (\mult_image1[2] [6] ), @@ -311076,7 +310534,7 @@ module zoom_image_v1 .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:866 + // ../../sources/designs/zoom/zoom_image_v1.v:861 GTP_LUT5CARRY /* N644_8 */ #( .INIT(32'b10010110100101100011110000111100), @@ -311085,9 +310543,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N644_8 ( - .COUT (_N16783), + .COUT (_N16710), .Z (N644[7]), - .CIN (_N16782), + .CIN (_N16709), .I0 (), .I1 (\mult_image1_0[2] [7] ), .I2 (\mult_image1[2] [7] ), @@ -311096,7 +310554,7 @@ module zoom_image_v1 .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:866 + // ../../sources/designs/zoom/zoom_image_v1.v:861 GTP_LUT5CARRY /* N644_9 */ #( .INIT(32'b10010110100101100011110000111100), @@ -311105,9 +310563,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N644_9 ( - .COUT (_N16784), + .COUT (_N16711), .Z (N644[8]), - .CIN (_N16783), + .CIN (_N16710), .I0 (), .I1 (\mult_image1_0[2] [8] ), .I2 (\mult_image1[2] [8] ), @@ -311116,7 +310574,7 @@ module zoom_image_v1 .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:866 + // ../../sources/designs/zoom/zoom_image_v1.v:861 GTP_LUT5CARRY /* N644_10 */ #( .INIT(32'b10010110100101100011110000111100), @@ -311125,9 +310583,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N644_10 ( - .COUT (_N16785), + .COUT (_N16712), .Z (N644[9]), - .CIN (_N16784), + .CIN (_N16711), .I0 (), .I1 (\mult_image1_0[2] [9] ), .I2 (\mult_image1[2] [9] ), @@ -311136,7 +310594,7 @@ module zoom_image_v1 .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:866 + // ../../sources/designs/zoom/zoom_image_v1.v:861 GTP_LUT5CARRY /* N644_11 */ #( .INIT(32'b10010110100101100011110000111100), @@ -311145,9 +310603,9 @@ module zoom_image_v1 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N644_11 ( - .COUT (_N16786), + .COUT (_N16713), .Z (N644[10]), - .CIN (_N16785), + .CIN (_N16712), .I0 (), .I1 (\mult_image1_0[2] [10] ), .I2 (\mult_image1[2] [10] ), @@ -311156,7 +310614,7 @@ module zoom_image_v1 .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:866 + // ../../sources/designs/zoom/zoom_image_v1.v:861 GTP_LUT5CARRY /* N644_12 */ #( .INIT(32'b10010110100101100011110000111100), @@ -311167,7 +310625,7 @@ module zoom_image_v1 N644_12 ( .COUT (), .Z (N644[11]), - .CIN (_N16786), + .CIN (_N16713), .I0 (), .I1 (\mult_image1_0[2] [11] ), .I2 (\mult_image1[2] [11] ), @@ -311176,7 +310634,7 @@ module zoom_image_v1 .ID ()); // LUT = I2^I1^CIN ; // CARRY = (I2^I1) ? CIN : (I4) ; - // ../../sources/designs/zoom/zoom_image_v1.v:866 + // ../../sources/designs/zoom/zoom_image_v1.v:861 GTP_LUT2 /* N653 */ #( .INIT(4'b1110)) @@ -311186,7 +310644,7 @@ module zoom_image_v1 .I1 (\image_valid[6] [1] )); // defparam N653_vname.orig_name = N653; // LUT = (I0)|(I1) ; - // ../../sources/designs/zoom/zoom_image_v1.v:887 + // ../../sources/designs/zoom/zoom_image_v1.v:882 GTP_LUT1 /* N699 */ #( .INIT(2'b01)) @@ -311198,7 +310656,7 @@ module zoom_image_v1 GTP_LUT4 /* N709_8 */ #( .INIT(16'b0000000010000000)) N709_8 ( - .Z (_N105128), + .Z (_N105675), .I0 (cnt_w[1]), .I1 (cnt_w[2]), .I2 (cnt_w[3]), @@ -311208,7 +310666,7 @@ module zoom_image_v1 GTP_LUT4 /* N709_9 */ #( .INIT(16'b1000000000000000)) N709_9 ( - .Z (_N105129), + .Z (_N105676), .I0 (cnt_w[4]), .I1 (cnt_w[5]), .I2 (cnt_w[6]), @@ -311222,14 +310680,14 @@ module zoom_image_v1 .I0 (cnt_w[0]), .I1 (cnt_w[7]), .I2 (cnt_w[8]), - .I3 (_N105128), - .I4 (_N105129)); + .I3 (_N105675), + .I4 (_N105676)); // LUT = I0&~I1&~I2&I3&I4 ; GTP_LUT3 /* N715_7 */ #( .INIT(8'b00000010)) N715_7 ( - .Z (_N105043), + .Z (_N105590), .I0 (cnt_h[0]), .I1 (cnt_h[3]), .I2 (cnt_h[4])); @@ -311238,12 +310696,12 @@ module zoom_image_v1 GTP_LUT5 /* N715_10 */ #( .INIT(32'b00000000000000100000000000000000)) N715_10 ( - .Z (_N105046), + .Z (_N105593), .I0 (cnt_h[1]), .I1 (cnt_h[7]), .I2 (cnt_h[9]), .I3 (cnt_h[10]), - .I4 (_N105043)); + .I4 (_N105590)); // LUT = I0&~I1&~I2&~I3&I4 ; GTP_LUT5 /* N715_11 */ #( @@ -311254,7 +310712,7 @@ module zoom_image_v1 .I1 (cnt_h[5]), .I2 (cnt_h[6]), .I3 (cnt_h[8]), - .I4 (_N105046)); + .I4 (_N105593)); // LUT = I0&I1&I2&I3&I4 ; GTP_LUT3 /* N731 */ #( @@ -311582,32 +311040,16 @@ module zoom_image_v1 .I (ram_idle1)); // defparam N866_vname.orig_name = N866; - GTP_LUT5 /* \N883_or[0]_5 */ #( - .INIT(32'b11111111111111111111111011111100)) - \N883_or[0]_5 ( - .Z (_N108389), - .I0 (N1014[1]), - .I1 (_N25), - .I2 (_N28), - .I3 (ram_sta[2]), - .I4 (ram_sta[3])); - // LUT = (I1)|(I2)|(I4)|(I0&I3) ; - - GTP_LUT4 /* \N883_or[0]_6 */ #( - .INIT(16'b1111111011111100)) - \N883_or[0]_6 ( - .Z (_N108390), - .I0 (N1014[1]), - .I1 (_N25), - .I2 (_N28), - .I3 (ram_sta[2])); - // LUT = (I1)|(I2)|(I0&I3) ; - - GTP_MUX2LUT6 \N883_or[0]_7 ( + GTP_LUT5 /* \N883_or[0]_4 */ #( + .INIT(32'b11111111111111101111111011111110)) + \N883_or[0]_4 ( .Z (N883), - .I0 (_N108390), - .I1 (_N108389), - .S (N1014[0])); + .I0 (_N25), + .I1 (_N23), + .I2 (_N28), + .I3 (N1014[1]), + .I4 (ram_sta[2])); + // LUT = (I0)|(I1)|(I2)|(I3&I4) ; GTP_LUT2 /* N891 */ #( .INIT(4'b1011)) @@ -312110,7 +311552,7 @@ module zoom_image_v1 .Q (coe_valid[0]), .CLK (clk), .D (N506)); - // ../../sources/designs/zoom/zoom_image_v1.v:719 + // ../../sources/designs/zoom/zoom_image_v1.v:715 GTP_DFF /* \coe_valid[1] */ #( .GRS_EN("TRUE"), @@ -312119,7 +311561,7 @@ module zoom_image_v1 .Q (coe_valid[1]), .CLK (clk), .D (coe_valid[0])); - // ../../sources/designs/zoom/zoom_image_v1.v:719 + // ../../sources/designs/zoom/zoom_image_v1.v:715 GTP_DFF /* \coe_valid[2] */ #( .GRS_EN("TRUE"), @@ -312128,7 +311570,7 @@ module zoom_image_v1 .Q (coe_valid[2]), .CLK (clk), .D (coe_valid[1])); - // ../../sources/designs/zoom/zoom_image_v1.v:719 + // ../../sources/designs/zoom/zoom_image_v1.v:715 GTP_DFF /* \coe_valid[3] */ #( .GRS_EN("TRUE"), @@ -312137,7 +311579,7 @@ module zoom_image_v1 .Q (coe_valid[3]), .CLK (clk), .D (coe_valid[2])); - // ../../sources/designs/zoom/zoom_image_v1.v:719 + // ../../sources/designs/zoom/zoom_image_v1.v:715 GTP_DFF /* \data_in0[0] */ #( .GRS_EN("TRUE"), @@ -312301,7 +311743,7 @@ module zoom_image_v1 .CLK (clk), .D (\mult_image2[2] [7] ), .R (\image_valid[6] [0] )); - // ../../sources/designs/zoom/zoom_image_v1.v:881 + // ../../sources/designs/zoom/zoom_image_v1.v:876 GTP_DFF_R /* \data_out1[1] */ #( .GRS_EN("TRUE"), @@ -312311,7 +311753,7 @@ module zoom_image_v1 .CLK (clk), .D (\mult_image2[2] [8] ), .R (\image_valid[6] [0] )); - // ../../sources/designs/zoom/zoom_image_v1.v:881 + // ../../sources/designs/zoom/zoom_image_v1.v:876 GTP_DFF_R /* \data_out1[2] */ #( .GRS_EN("TRUE"), @@ -312321,7 +311763,7 @@ module zoom_image_v1 .CLK (clk), .D (\mult_image2[2] [9] ), .R (\image_valid[6] [0] )); - // ../../sources/designs/zoom/zoom_image_v1.v:881 + // ../../sources/designs/zoom/zoom_image_v1.v:876 GTP_DFF_R /* \data_out1[3] */ #( .GRS_EN("TRUE"), @@ -312331,7 +311773,7 @@ module zoom_image_v1 .CLK (clk), .D (\mult_image2[2] [10] ), .R (\image_valid[6] [0] )); - // ../../sources/designs/zoom/zoom_image_v1.v:881 + // ../../sources/designs/zoom/zoom_image_v1.v:876 GTP_DFF_R /* \data_out1[4] */ #( .GRS_EN("TRUE"), @@ -312341,7 +311783,7 @@ module zoom_image_v1 .CLK (clk), .D (\mult_image2[2] [11] ), .R (\image_valid[6] [0] )); - // ../../sources/designs/zoom/zoom_image_v1.v:881 + // ../../sources/designs/zoom/zoom_image_v1.v:876 GTP_DFF_R /* \data_out1[5] */ #( .GRS_EN("TRUE"), @@ -312351,7 +311793,7 @@ module zoom_image_v1 .CLK (clk), .D (\mult_image2[1] [7] ), .R (\image_valid[6] [0] )); - // ../../sources/designs/zoom/zoom_image_v1.v:881 + // ../../sources/designs/zoom/zoom_image_v1.v:876 GTP_DFF_R /* \data_out1[6] */ #( .GRS_EN("TRUE"), @@ -312361,7 +311803,7 @@ module zoom_image_v1 .CLK (clk), .D (\mult_image2[1] [8] ), .R (\image_valid[6] [0] )); - // ../../sources/designs/zoom/zoom_image_v1.v:881 + // ../../sources/designs/zoom/zoom_image_v1.v:876 GTP_DFF_R /* \data_out1[7] */ #( .GRS_EN("TRUE"), @@ -312371,7 +311813,7 @@ module zoom_image_v1 .CLK (clk), .D (\mult_image2[1] [9] ), .R (\image_valid[6] [0] )); - // ../../sources/designs/zoom/zoom_image_v1.v:881 + // ../../sources/designs/zoom/zoom_image_v1.v:876 GTP_DFF_R /* \data_out1[8] */ #( .GRS_EN("TRUE"), @@ -312381,7 +311823,7 @@ module zoom_image_v1 .CLK (clk), .D (\mult_image2[1] [10] ), .R (\image_valid[6] [0] )); - // ../../sources/designs/zoom/zoom_image_v1.v:881 + // ../../sources/designs/zoom/zoom_image_v1.v:876 GTP_DFF_R /* \data_out1[9] */ #( .GRS_EN("TRUE"), @@ -312391,7 +311833,7 @@ module zoom_image_v1 .CLK (clk), .D (\mult_image2[1] [11] ), .R (\image_valid[6] [0] )); - // ../../sources/designs/zoom/zoom_image_v1.v:881 + // ../../sources/designs/zoom/zoom_image_v1.v:876 GTP_DFF_R /* \data_out1[10] */ #( .GRS_EN("TRUE"), @@ -312401,7 +311843,7 @@ module zoom_image_v1 .CLK (clk), .D (\mult_image2[1] [12] ), .R (\image_valid[6] [0] )); - // ../../sources/designs/zoom/zoom_image_v1.v:881 + // ../../sources/designs/zoom/zoom_image_v1.v:876 GTP_DFF_R /* \data_out1[11] */ #( .GRS_EN("TRUE"), @@ -312411,7 +311853,7 @@ module zoom_image_v1 .CLK (clk), .D (\mult_image2[0] [7] ), .R (\image_valid[6] [0] )); - // ../../sources/designs/zoom/zoom_image_v1.v:881 + // ../../sources/designs/zoom/zoom_image_v1.v:876 GTP_DFF_R /* \data_out1[12] */ #( .GRS_EN("TRUE"), @@ -312421,7 +311863,7 @@ module zoom_image_v1 .CLK (clk), .D (\mult_image2[0] [8] ), .R (\image_valid[6] [0] )); - // ../../sources/designs/zoom/zoom_image_v1.v:881 + // ../../sources/designs/zoom/zoom_image_v1.v:876 GTP_DFF_R /* \data_out1[13] */ #( .GRS_EN("TRUE"), @@ -312431,7 +311873,7 @@ module zoom_image_v1 .CLK (clk), .D (\mult_image2[0] [9] ), .R (\image_valid[6] [0] )); - // ../../sources/designs/zoom/zoom_image_v1.v:881 + // ../../sources/designs/zoom/zoom_image_v1.v:876 GTP_DFF_R /* \data_out1[14] */ #( .GRS_EN("TRUE"), @@ -312441,7 +311883,7 @@ module zoom_image_v1 .CLK (clk), .D (\mult_image2[0] [10] ), .R (\image_valid[6] [0] )); - // ../../sources/designs/zoom/zoom_image_v1.v:881 + // ../../sources/designs/zoom/zoom_image_v1.v:876 GTP_DFF_R /* \data_out1[15] */ #( .GRS_EN("TRUE"), @@ -312451,7 +311893,7 @@ module zoom_image_v1 .CLK (clk), .D (\mult_image2[0] [11] ), .R (\image_valid[6] [0] )); - // ../../sources/designs/zoom/zoom_image_v1.v:881 + // ../../sources/designs/zoom/zoom_image_v1.v:876 GTP_DFF /* \data_out2[0] */ #( .GRS_EN("TRUE"), @@ -312460,7 +311902,7 @@ module zoom_image_v1 .Q (data_out[0]), .CLK (clk), .D (data_out1[0])); - // ../../sources/designs/zoom/zoom_image_v1.v:932 + // ../../sources/designs/zoom/zoom_image_v1.v:927 GTP_DFF /* \data_out2[1] */ #( .GRS_EN("TRUE"), @@ -312469,7 +311911,7 @@ module zoom_image_v1 .Q (data_out[1]), .CLK (clk), .D (data_out1[1])); - // ../../sources/designs/zoom/zoom_image_v1.v:932 + // ../../sources/designs/zoom/zoom_image_v1.v:927 GTP_DFF /* \data_out2[2] */ #( .GRS_EN("TRUE"), @@ -312478,7 +311920,7 @@ module zoom_image_v1 .Q (data_out[2]), .CLK (clk), .D (data_out1[2])); - // ../../sources/designs/zoom/zoom_image_v1.v:932 + // ../../sources/designs/zoom/zoom_image_v1.v:927 GTP_DFF /* \data_out2[3] */ #( .GRS_EN("TRUE"), @@ -312487,7 +311929,7 @@ module zoom_image_v1 .Q (data_out[3]), .CLK (clk), .D (data_out1[3])); - // ../../sources/designs/zoom/zoom_image_v1.v:932 + // ../../sources/designs/zoom/zoom_image_v1.v:927 GTP_DFF /* \data_out2[4] */ #( .GRS_EN("TRUE"), @@ -312496,7 +311938,7 @@ module zoom_image_v1 .Q (data_out[4]), .CLK (clk), .D (data_out1[4])); - // ../../sources/designs/zoom/zoom_image_v1.v:932 + // ../../sources/designs/zoom/zoom_image_v1.v:927 GTP_DFF /* \data_out2[5] */ #( .GRS_EN("TRUE"), @@ -312505,7 +311947,7 @@ module zoom_image_v1 .Q (data_out[5]), .CLK (clk), .D (data_out1[5])); - // ../../sources/designs/zoom/zoom_image_v1.v:932 + // ../../sources/designs/zoom/zoom_image_v1.v:927 GTP_DFF /* \data_out2[6] */ #( .GRS_EN("TRUE"), @@ -312514,7 +311956,7 @@ module zoom_image_v1 .Q (data_out[6]), .CLK (clk), .D (data_out1[6])); - // ../../sources/designs/zoom/zoom_image_v1.v:932 + // ../../sources/designs/zoom/zoom_image_v1.v:927 GTP_DFF /* \data_out2[7] */ #( .GRS_EN("TRUE"), @@ -312523,7 +311965,7 @@ module zoom_image_v1 .Q (data_out[7]), .CLK (clk), .D (data_out1[7])); - // ../../sources/designs/zoom/zoom_image_v1.v:932 + // ../../sources/designs/zoom/zoom_image_v1.v:927 GTP_DFF /* \data_out2[8] */ #( .GRS_EN("TRUE"), @@ -312532,7 +311974,7 @@ module zoom_image_v1 .Q (data_out[8]), .CLK (clk), .D (data_out1[8])); - // ../../sources/designs/zoom/zoom_image_v1.v:932 + // ../../sources/designs/zoom/zoom_image_v1.v:927 GTP_DFF /* \data_out2[9] */ #( .GRS_EN("TRUE"), @@ -312541,7 +311983,7 @@ module zoom_image_v1 .Q (data_out[9]), .CLK (clk), .D (data_out1[9])); - // ../../sources/designs/zoom/zoom_image_v1.v:932 + // ../../sources/designs/zoom/zoom_image_v1.v:927 GTP_DFF /* \data_out2[10] */ #( .GRS_EN("TRUE"), @@ -312550,7 +311992,7 @@ module zoom_image_v1 .Q (data_out[10]), .CLK (clk), .D (data_out1[10])); - // ../../sources/designs/zoom/zoom_image_v1.v:932 + // ../../sources/designs/zoom/zoom_image_v1.v:927 GTP_DFF /* \data_out2[11] */ #( .GRS_EN("TRUE"), @@ -312559,7 +312001,7 @@ module zoom_image_v1 .Q (data_out[11]), .CLK (clk), .D (data_out1[11])); - // ../../sources/designs/zoom/zoom_image_v1.v:932 + // ../../sources/designs/zoom/zoom_image_v1.v:927 GTP_DFF /* \data_out2[12] */ #( .GRS_EN("TRUE"), @@ -312568,7 +312010,7 @@ module zoom_image_v1 .Q (data_out[12]), .CLK (clk), .D (data_out1[12])); - // ../../sources/designs/zoom/zoom_image_v1.v:932 + // ../../sources/designs/zoom/zoom_image_v1.v:927 GTP_DFF /* \data_out2[13] */ #( .GRS_EN("TRUE"), @@ -312577,7 +312019,7 @@ module zoom_image_v1 .Q (data_out[13]), .CLK (clk), .D (data_out1[13])); - // ../../sources/designs/zoom/zoom_image_v1.v:932 + // ../../sources/designs/zoom/zoom_image_v1.v:927 GTP_DFF /* \data_out2[14] */ #( .GRS_EN("TRUE"), @@ -312586,7 +312028,7 @@ module zoom_image_v1 .Q (data_out[14]), .CLK (clk), .D (data_out1[14])); - // ../../sources/designs/zoom/zoom_image_v1.v:932 + // ../../sources/designs/zoom/zoom_image_v1.v:927 GTP_DFF /* \data_out2[15] */ #( .GRS_EN("TRUE"), @@ -312595,7 +312037,7 @@ module zoom_image_v1 .Q (data_out[15]), .CLK (clk), .D (data_out1[15])); - // ../../sources/designs/zoom/zoom_image_v1.v:932 + // ../../sources/designs/zoom/zoom_image_v1.v:927 GTP_DFF /* data_out_valid1 */ #( .GRS_EN("TRUE"), @@ -312605,7 +312047,7 @@ module zoom_image_v1 .CLK (clk), .D (N653)); // defparam data_out_valid1_vname.orig_name = data_out_valid1; - // ../../sources/designs/zoom/zoom_image_v1.v:881 + // ../../sources/designs/zoom/zoom_image_v1.v:876 GTP_DFF /* data_out_valid2 */ #( .GRS_EN("TRUE"), @@ -312614,7 +312056,7 @@ module zoom_image_v1 .Q (data_out_valid), .CLK (clk), .D (data_out_valid1)); - // ../../sources/designs/zoom/zoom_image_v1.v:924 + // ../../sources/designs/zoom/zoom_image_v1.v:919 GTP_DFF_R /* \delay_cnt[0] */ #( .GRS_EN("TRUE"), @@ -313257,7 +312699,7 @@ module zoom_image_v1 .Q (image_h2[0]), .CLK (clk), .D (image_h1[0])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_h2[1] */ #( .GRS_EN("TRUE"), @@ -313266,7 +312708,7 @@ module zoom_image_v1 .Q (image_h2[1]), .CLK (clk), .D (image_h1[1])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_h2[2] */ #( .GRS_EN("TRUE"), @@ -313275,7 +312717,7 @@ module zoom_image_v1 .Q (image_h2[2]), .CLK (clk), .D (image_h1[2])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_h2[3] */ #( .GRS_EN("TRUE"), @@ -313284,7 +312726,7 @@ module zoom_image_v1 .Q (image_h2[3]), .CLK (clk), .D (image_h1[3])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_h2[4] */ #( .GRS_EN("TRUE"), @@ -313293,7 +312735,7 @@ module zoom_image_v1 .Q (image_h2[4]), .CLK (clk), .D (image_h1[4])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_h2[5] */ #( .GRS_EN("TRUE"), @@ -313302,7 +312744,7 @@ module zoom_image_v1 .Q (image_h2[5]), .CLK (clk), .D (image_h1[5])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_h2[6] */ #( .GRS_EN("TRUE"), @@ -313311,7 +312753,7 @@ module zoom_image_v1 .Q (image_h2[6]), .CLK (clk), .D (image_h1[6])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_h2[7] */ #( .GRS_EN("TRUE"), @@ -313320,7 +312762,7 @@ module zoom_image_v1 .Q (image_h2[7]), .CLK (clk), .D (image_h1[7])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_h2[8] */ #( .GRS_EN("TRUE"), @@ -313329,7 +312771,7 @@ module zoom_image_v1 .Q (image_h2[8]), .CLK (clk), .D (image_h1[8])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_h2[9] */ #( .GRS_EN("TRUE"), @@ -313338,7 +312780,7 @@ module zoom_image_v1 .Q (image_h2[9]), .CLK (clk), .D (image_h1[9])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_h2[10] */ #( .GRS_EN("TRUE"), @@ -313347,7 +312789,7 @@ module zoom_image_v1 .Q (image_h2[10]), .CLK (clk), .D (image_h1[10])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_h2[11] */ #( .GRS_EN("TRUE"), @@ -313356,7 +312798,7 @@ module zoom_image_v1 .Q (image_h2[11]), .CLK (clk), .D (image_h1[11])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_h2[12] */ #( .GRS_EN("TRUE"), @@ -313365,7 +312807,7 @@ module zoom_image_v1 .Q (image_h2[12]), .CLK (clk), .D (image_h1[12])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_h2[13] */ #( .GRS_EN("TRUE"), @@ -313374,7 +312816,7 @@ module zoom_image_v1 .Q (image_h2[13]), .CLK (clk), .D (image_h1[13])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_h2[14] */ #( .GRS_EN("TRUE"), @@ -313383,7 +312825,7 @@ module zoom_image_v1 .Q (image_h2[14]), .CLK (clk), .D (image_h1[14])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_h2[15] */ #( .GRS_EN("TRUE"), @@ -313392,7 +312834,7 @@ module zoom_image_v1 .Q (image_h2[15]), .CLK (clk), .D (image_h1[15])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_h2[16] */ #( .GRS_EN("TRUE"), @@ -313401,7 +312843,7 @@ module zoom_image_v1 .Q (image_h2[16]), .CLK (clk), .D (image_h1[16])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_h2[17] */ #( .GRS_EN("TRUE"), @@ -313410,7 +312852,7 @@ module zoom_image_v1 .Q (image_h2[17]), .CLK (clk), .D (image_h1[17])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_h2[18] */ #( .GRS_EN("TRUE"), @@ -313419,7 +312861,7 @@ module zoom_image_v1 .Q (image_h2[18]), .CLK (clk), .D (image_h1[18])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_h2[19] */ #( .GRS_EN("TRUE"), @@ -313428,7 +312870,7 @@ module zoom_image_v1 .Q (image_h2[19]), .CLK (clk), .D (image_h1[19])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_h2[20] */ #( .GRS_EN("TRUE"), @@ -313437,7 +312879,7 @@ module zoom_image_v1 .Q (image_h2[20]), .CLK (clk), .D (image_h1[20])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_h2_coe0[0] */ #( .GRS_EN("TRUE"), @@ -313446,7 +312888,7 @@ module zoom_image_v1 .Q (image_h2_coe0[0]), .CLK (clk), .D (image_h2_coe[0])); - // ../../sources/designs/zoom/zoom_image_v1.v:719 + // ../../sources/designs/zoom/zoom_image_v1.v:715 GTP_DFF /* \image_h2_coe0[1] */ #( .GRS_EN("TRUE"), @@ -313455,7 +312897,7 @@ module zoom_image_v1 .Q (image_h2_coe0[1]), .CLK (clk), .D (image_h2_coe[1])); - // ../../sources/designs/zoom/zoom_image_v1.v:719 + // ../../sources/designs/zoom/zoom_image_v1.v:715 GTP_DFF /* \image_h2_coe0[2] */ #( .GRS_EN("TRUE"), @@ -313464,7 +312906,7 @@ module zoom_image_v1 .Q (image_h2_coe0[2]), .CLK (clk), .D (image_h2_coe[2])); - // ../../sources/designs/zoom/zoom_image_v1.v:719 + // ../../sources/designs/zoom/zoom_image_v1.v:715 GTP_DFF /* \image_h2_coe0[3] */ #( .GRS_EN("TRUE"), @@ -313473,7 +312915,7 @@ module zoom_image_v1 .Q (image_h2_coe0[3]), .CLK (clk), .D (image_h2_coe[3])); - // ../../sources/designs/zoom/zoom_image_v1.v:719 + // ../../sources/designs/zoom/zoom_image_v1.v:715 GTP_DFF /* \image_h2_coe0[4] */ #( .GRS_EN("TRUE"), @@ -313482,7 +312924,7 @@ module zoom_image_v1 .Q (image_h2_coe0[4]), .CLK (clk), .D (image_h2_coe[4])); - // ../../sources/designs/zoom/zoom_image_v1.v:719 + // ../../sources/designs/zoom/zoom_image_v1.v:715 GTP_DFF /* \image_h2_coe0[5] */ #( .GRS_EN("TRUE"), @@ -313491,7 +312933,7 @@ module zoom_image_v1 .Q (image_h2_coe0[5]), .CLK (clk), .D (image_h2_coe[5])); - // ../../sources/designs/zoom/zoom_image_v1.v:719 + // ../../sources/designs/zoom/zoom_image_v1.v:715 GTP_DFF /* \image_h2_coe0[6] */ #( .GRS_EN("TRUE"), @@ -313500,7 +312942,7 @@ module zoom_image_v1 .Q (image_h2_coe0[6]), .CLK (clk), .D (image_h2_coe[6])); - // ../../sources/designs/zoom/zoom_image_v1.v:719 + // ../../sources/designs/zoom/zoom_image_v1.v:715 GTP_DFF /* \image_h2_coe1[0] */ #( .GRS_EN("TRUE"), @@ -313509,7 +312951,7 @@ module zoom_image_v1 .Q (image_h2_coe1[0]), .CLK (clk), .D (image_h2_coe0[0])); - // ../../sources/designs/zoom/zoom_image_v1.v:719 + // ../../sources/designs/zoom/zoom_image_v1.v:715 GTP_DFF /* \image_h2_coe1[1] */ #( .GRS_EN("TRUE"), @@ -313518,7 +312960,7 @@ module zoom_image_v1 .Q (image_h2_coe1[1]), .CLK (clk), .D (image_h2_coe0[1])); - // ../../sources/designs/zoom/zoom_image_v1.v:719 + // ../../sources/designs/zoom/zoom_image_v1.v:715 GTP_DFF /* \image_h2_coe1[2] */ #( .GRS_EN("TRUE"), @@ -313527,7 +312969,7 @@ module zoom_image_v1 .Q (image_h2_coe1[2]), .CLK (clk), .D (image_h2_coe0[2])); - // ../../sources/designs/zoom/zoom_image_v1.v:719 + // ../../sources/designs/zoom/zoom_image_v1.v:715 GTP_DFF /* \image_h2_coe1[3] */ #( .GRS_EN("TRUE"), @@ -313536,7 +312978,7 @@ module zoom_image_v1 .Q (image_h2_coe1[3]), .CLK (clk), .D (image_h2_coe0[3])); - // ../../sources/designs/zoom/zoom_image_v1.v:719 + // ../../sources/designs/zoom/zoom_image_v1.v:715 GTP_DFF /* \image_h2_coe1[4] */ #( .GRS_EN("TRUE"), @@ -313545,7 +312987,7 @@ module zoom_image_v1 .Q (image_h2_coe1[4]), .CLK (clk), .D (image_h2_coe0[4])); - // ../../sources/designs/zoom/zoom_image_v1.v:719 + // ../../sources/designs/zoom/zoom_image_v1.v:715 GTP_DFF /* \image_h2_coe1[5] */ #( .GRS_EN("TRUE"), @@ -313554,7 +312996,7 @@ module zoom_image_v1 .Q (image_h2_coe1[5]), .CLK (clk), .D (image_h2_coe0[5])); - // ../../sources/designs/zoom/zoom_image_v1.v:719 + // ../../sources/designs/zoom/zoom_image_v1.v:715 GTP_DFF /* \image_h2_coe1[6] */ #( .GRS_EN("TRUE"), @@ -313563,7 +313005,7 @@ module zoom_image_v1 .Q (image_h2_coe1[6]), .CLK (clk), .D (image_h2_coe0[6])); - // ../../sources/designs/zoom/zoom_image_v1.v:719 + // ../../sources/designs/zoom/zoom_image_v1.v:715 GTP_DFF /* \image_h2_coe[0] */ #( .GRS_EN("TRUE"), @@ -313572,7 +313014,7 @@ module zoom_image_v1 .Q (image_h2_coe[0]), .CLK (clk), .D (image_h2[0])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_h2_coe[1] */ #( .GRS_EN("TRUE"), @@ -313581,7 +313023,7 @@ module zoom_image_v1 .Q (image_h2_coe[1]), .CLK (clk), .D (image_h2[1])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_h2_coe[2] */ #( .GRS_EN("TRUE"), @@ -313590,7 +313032,7 @@ module zoom_image_v1 .Q (image_h2_coe[2]), .CLK (clk), .D (image_h2[2])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_h2_coe[3] */ #( .GRS_EN("TRUE"), @@ -313599,7 +313041,7 @@ module zoom_image_v1 .Q (image_h2_coe[3]), .CLK (clk), .D (image_h2[3])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_h2_coe[4] */ #( .GRS_EN("TRUE"), @@ -313608,7 +313050,7 @@ module zoom_image_v1 .Q (image_h2_coe[4]), .CLK (clk), .D (image_h2[4])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_h2_coe[5] */ #( .GRS_EN("TRUE"), @@ -313617,7 +313059,7 @@ module zoom_image_v1 .Q (image_h2_coe[5]), .CLK (clk), .D (image_h2[5])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_h2_coe[6] */ #( .GRS_EN("TRUE"), @@ -313626,7 +313068,7 @@ module zoom_image_v1 .Q (image_h2_coe[6]), .CLK (clk), .D (image_h2[6])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF_R /* \image_h_valid[0] */ #( .GRS_EN("TRUE"), @@ -313636,7 +313078,7 @@ module zoom_image_v1 .CLK (clk), .D (N533), .R (N927)); - // ../../sources/designs/zoom/zoom_image_v1.v:719 + // ../../sources/designs/zoom/zoom_image_v1.v:715 GTP_DFF_R /* \image_h_valid[1] */ #( .GRS_EN("TRUE"), @@ -313646,7 +313088,7 @@ module zoom_image_v1 .CLK (clk), .D (N533_inv), .R (N927)); - // ../../sources/designs/zoom/zoom_image_v1.v:719 + // ../../sources/designs/zoom/zoom_image_v1.v:715 GTP_DFF /* \image_valid[0][0] */ #( .GRS_EN("TRUE"), @@ -313655,7 +313097,7 @@ module zoom_image_v1 .Q (\image_valid[0] [0] ), .CLK (clk), .D (N492[0])); - // ../../sources/designs/zoom/zoom_image_v1.v:714 + // ../../sources/designs/zoom/zoom_image_v1.v:710 GTP_DFF /* \image_valid[0][1] */ #( .GRS_EN("TRUE"), @@ -313664,7 +313106,7 @@ module zoom_image_v1 .Q (\image_valid[0] [1] ), .CLK (clk), .D (N492[1])); - // ../../sources/designs/zoom/zoom_image_v1.v:714 + // ../../sources/designs/zoom/zoom_image_v1.v:710 GTP_DFF /* \image_valid[1][0] */ #( .GRS_EN("TRUE"), @@ -313673,7 +313115,7 @@ module zoom_image_v1 .Q (\image_valid[1] [0] ), .CLK (clk), .D (\image_valid[0] [0] )); - // ../../sources/designs/zoom/zoom_image_v1.v:714 + // ../../sources/designs/zoom/zoom_image_v1.v:710 GTP_DFF /* \image_valid[1][1] */ #( .GRS_EN("TRUE"), @@ -313682,7 +313124,7 @@ module zoom_image_v1 .Q (\image_valid[1] [1] ), .CLK (clk), .D (\image_valid[0] [1] )); - // ../../sources/designs/zoom/zoom_image_v1.v:714 + // ../../sources/designs/zoom/zoom_image_v1.v:710 GTP_DFF /* \image_valid[2][0] */ #( .GRS_EN("TRUE"), @@ -313691,7 +313133,7 @@ module zoom_image_v1 .Q (\image_valid[2] [0] ), .CLK (clk), .D (\image_valid[1] [0] )); - // ../../sources/designs/zoom/zoom_image_v1.v:714 + // ../../sources/designs/zoom/zoom_image_v1.v:710 GTP_DFF /* \image_valid[2][1] */ #( .GRS_EN("TRUE"), @@ -313700,7 +313142,7 @@ module zoom_image_v1 .Q (\image_valid[2] [1] ), .CLK (clk), .D (\image_valid[1] [1] )); - // ../../sources/designs/zoom/zoom_image_v1.v:714 + // ../../sources/designs/zoom/zoom_image_v1.v:710 GTP_DFF /* \image_valid[3][0] */ #( .GRS_EN("TRUE"), @@ -313709,7 +313151,7 @@ module zoom_image_v1 .Q (\image_valid[3] [0] ), .CLK (clk), .D (\image_valid[2] [0] )); - // ../../sources/designs/zoom/zoom_image_v1.v:714 + // ../../sources/designs/zoom/zoom_image_v1.v:710 GTP_DFF /* \image_valid[3][1] */ #( .GRS_EN("TRUE"), @@ -313718,7 +313160,7 @@ module zoom_image_v1 .Q (\image_valid[3] [1] ), .CLK (clk), .D (\image_valid[2] [1] )); - // ../../sources/designs/zoom/zoom_image_v1.v:714 + // ../../sources/designs/zoom/zoom_image_v1.v:710 GTP_DFF /* \image_valid[4][0] */ #( .GRS_EN("TRUE"), @@ -313727,7 +313169,7 @@ module zoom_image_v1 .Q (\image_valid[4] [0] ), .CLK (clk), .D (\image_valid[3] [0] )); - // ../../sources/designs/zoom/zoom_image_v1.v:714 + // ../../sources/designs/zoom/zoom_image_v1.v:710 GTP_DFF /* \image_valid[4][1] */ #( .GRS_EN("TRUE"), @@ -313736,7 +313178,7 @@ module zoom_image_v1 .Q (\image_valid[4] [1] ), .CLK (clk), .D (\image_valid[3] [1] )); - // ../../sources/designs/zoom/zoom_image_v1.v:714 + // ../../sources/designs/zoom/zoom_image_v1.v:710 GTP_DFF /* \image_valid[5][0] */ #( .GRS_EN("TRUE"), @@ -313745,7 +313187,7 @@ module zoom_image_v1 .Q (\image_valid[5] [0] ), .CLK (clk), .D (\image_valid[4] [0] )); - // ../../sources/designs/zoom/zoom_image_v1.v:714 + // ../../sources/designs/zoom/zoom_image_v1.v:710 GTP_DFF /* \image_valid[5][1] */ #( .GRS_EN("TRUE"), @@ -313754,7 +313196,7 @@ module zoom_image_v1 .Q (\image_valid[5] [1] ), .CLK (clk), .D (\image_valid[4] [1] )); - // ../../sources/designs/zoom/zoom_image_v1.v:714 + // ../../sources/designs/zoom/zoom_image_v1.v:710 GTP_DFF /* \image_valid[6][0] */ #( .GRS_EN("TRUE"), @@ -313763,7 +313205,7 @@ module zoom_image_v1 .Q (\image_valid[6] [0] ), .CLK (clk), .D (\image_valid[5] [0] )); - // ../../sources/designs/zoom/zoom_image_v1.v:714 + // ../../sources/designs/zoom/zoom_image_v1.v:710 GTP_DFF /* \image_valid[6][1] */ #( .GRS_EN("TRUE"), @@ -313772,7 +313214,7 @@ module zoom_image_v1 .Q (\image_valid[6] [1] ), .CLK (clk), .D (\image_valid[5] [1] )); - // ../../sources/designs/zoom/zoom_image_v1.v:714 + // ../../sources/designs/zoom/zoom_image_v1.v:710 GTP_DFF /* \image_w1[0] */ #( .GRS_EN("TRUE"), @@ -313970,7 +313412,7 @@ module zoom_image_v1 .Q (image_w2[0]), .CLK (clk), .D (image_w1[0])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_w2[1] */ #( .GRS_EN("TRUE"), @@ -313979,7 +313421,7 @@ module zoom_image_v1 .Q (image_w2[1]), .CLK (clk), .D (image_w1[1])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_w2[2] */ #( .GRS_EN("TRUE"), @@ -313988,7 +313430,7 @@ module zoom_image_v1 .Q (image_w2[2]), .CLK (clk), .D (image_w1[2])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_w2[3] */ #( .GRS_EN("TRUE"), @@ -313997,7 +313439,7 @@ module zoom_image_v1 .Q (image_w2[3]), .CLK (clk), .D (image_w1[3])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_w2[4] */ #( .GRS_EN("TRUE"), @@ -314006,7 +313448,7 @@ module zoom_image_v1 .Q (image_w2[4]), .CLK (clk), .D (image_w1[4])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_w2[5] */ #( .GRS_EN("TRUE"), @@ -314015,7 +313457,7 @@ module zoom_image_v1 .Q (image_w2[5]), .CLK (clk), .D (image_w1[5])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_w2[6] */ #( .GRS_EN("TRUE"), @@ -314024,7 +313466,7 @@ module zoom_image_v1 .Q (image_w2[6]), .CLK (clk), .D (image_w1[6])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_w2[15] */ #( .GRS_EN("TRUE"), @@ -314033,7 +313475,7 @@ module zoom_image_v1 .Q (image_w2[15]), .CLK (clk), .D (image_w1[15])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_w2[16] */ #( .GRS_EN("TRUE"), @@ -314042,7 +313484,7 @@ module zoom_image_v1 .Q (image_w2[16]), .CLK (clk), .D (image_w1[16])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_w2[17] */ #( .GRS_EN("TRUE"), @@ -314051,7 +313493,7 @@ module zoom_image_v1 .Q (image_w2[17]), .CLK (clk), .D (image_w1[17])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_w2[18] */ #( .GRS_EN("TRUE"), @@ -314060,7 +313502,7 @@ module zoom_image_v1 .Q (image_w2[18]), .CLK (clk), .D (image_w1[18])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_w2[19] */ #( .GRS_EN("TRUE"), @@ -314069,7 +313511,7 @@ module zoom_image_v1 .Q (image_w2[19]), .CLK (clk), .D (image_w1[19])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_w2[20] */ #( .GRS_EN("TRUE"), @@ -314078,7 +313520,7 @@ module zoom_image_v1 .Q (image_w2[20]), .CLK (clk), .D (image_w1[20])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_w2_coe0[0] */ #( .GRS_EN("TRUE"), @@ -314087,7 +313529,7 @@ module zoom_image_v1 .Q (image_w2_coe0[0]), .CLK (clk), .D (image_w2_coe[0])); - // ../../sources/designs/zoom/zoom_image_v1.v:719 + // ../../sources/designs/zoom/zoom_image_v1.v:715 GTP_DFF /* \image_w2_coe0[1] */ #( .GRS_EN("TRUE"), @@ -314096,7 +313538,7 @@ module zoom_image_v1 .Q (image_w2_coe0[1]), .CLK (clk), .D (image_w2_coe[1])); - // ../../sources/designs/zoom/zoom_image_v1.v:719 + // ../../sources/designs/zoom/zoom_image_v1.v:715 GTP_DFF /* \image_w2_coe0[2] */ #( .GRS_EN("TRUE"), @@ -314105,7 +313547,7 @@ module zoom_image_v1 .Q (image_w2_coe0[2]), .CLK (clk), .D (image_w2_coe[2])); - // ../../sources/designs/zoom/zoom_image_v1.v:719 + // ../../sources/designs/zoom/zoom_image_v1.v:715 GTP_DFF /* \image_w2_coe0[3] */ #( .GRS_EN("TRUE"), @@ -314114,7 +313556,7 @@ module zoom_image_v1 .Q (image_w2_coe0[3]), .CLK (clk), .D (image_w2_coe[3])); - // ../../sources/designs/zoom/zoom_image_v1.v:719 + // ../../sources/designs/zoom/zoom_image_v1.v:715 GTP_DFF /* \image_w2_coe0[4] */ #( .GRS_EN("TRUE"), @@ -314123,7 +313565,7 @@ module zoom_image_v1 .Q (image_w2_coe0[4]), .CLK (clk), .D (image_w2_coe[4])); - // ../../sources/designs/zoom/zoom_image_v1.v:719 + // ../../sources/designs/zoom/zoom_image_v1.v:715 GTP_DFF /* \image_w2_coe0[5] */ #( .GRS_EN("TRUE"), @@ -314132,7 +313574,7 @@ module zoom_image_v1 .Q (image_w2_coe0[5]), .CLK (clk), .D (image_w2_coe[5])); - // ../../sources/designs/zoom/zoom_image_v1.v:719 + // ../../sources/designs/zoom/zoom_image_v1.v:715 GTP_DFF /* \image_w2_coe0[6] */ #( .GRS_EN("TRUE"), @@ -314141,7 +313583,7 @@ module zoom_image_v1 .Q (image_w2_coe0[6]), .CLK (clk), .D (image_w2_coe[6])); - // ../../sources/designs/zoom/zoom_image_v1.v:719 + // ../../sources/designs/zoom/zoom_image_v1.v:715 GTP_DFF /* \image_w2_coe1[0] */ #( .GRS_EN("TRUE"), @@ -314150,7 +313592,7 @@ module zoom_image_v1 .Q (image_w2_coe1[0]), .CLK (clk), .D (image_w2_coe0[0])); - // ../../sources/designs/zoom/zoom_image_v1.v:719 + // ../../sources/designs/zoom/zoom_image_v1.v:715 GTP_DFF /* \image_w2_coe1[1] */ #( .GRS_EN("TRUE"), @@ -314159,7 +313601,7 @@ module zoom_image_v1 .Q (image_w2_coe1[1]), .CLK (clk), .D (image_w2_coe0[1])); - // ../../sources/designs/zoom/zoom_image_v1.v:719 + // ../../sources/designs/zoom/zoom_image_v1.v:715 GTP_DFF /* \image_w2_coe1[2] */ #( .GRS_EN("TRUE"), @@ -314168,7 +313610,7 @@ module zoom_image_v1 .Q (image_w2_coe1[2]), .CLK (clk), .D (image_w2_coe0[2])); - // ../../sources/designs/zoom/zoom_image_v1.v:719 + // ../../sources/designs/zoom/zoom_image_v1.v:715 GTP_DFF /* \image_w2_coe1[3] */ #( .GRS_EN("TRUE"), @@ -314177,7 +313619,7 @@ module zoom_image_v1 .Q (image_w2_coe1[3]), .CLK (clk), .D (image_w2_coe0[3])); - // ../../sources/designs/zoom/zoom_image_v1.v:719 + // ../../sources/designs/zoom/zoom_image_v1.v:715 GTP_DFF /* \image_w2_coe1[4] */ #( .GRS_EN("TRUE"), @@ -314186,7 +313628,7 @@ module zoom_image_v1 .Q (image_w2_coe1[4]), .CLK (clk), .D (image_w2_coe0[4])); - // ../../sources/designs/zoom/zoom_image_v1.v:719 + // ../../sources/designs/zoom/zoom_image_v1.v:715 GTP_DFF /* \image_w2_coe1[5] */ #( .GRS_EN("TRUE"), @@ -314195,7 +313637,7 @@ module zoom_image_v1 .Q (image_w2_coe1[5]), .CLK (clk), .D (image_w2_coe0[5])); - // ../../sources/designs/zoom/zoom_image_v1.v:719 + // ../../sources/designs/zoom/zoom_image_v1.v:715 GTP_DFF /* \image_w2_coe1[6] */ #( .GRS_EN("TRUE"), @@ -314204,7 +313646,7 @@ module zoom_image_v1 .Q (image_w2_coe1[6]), .CLK (clk), .D (image_w2_coe0[6])); - // ../../sources/designs/zoom/zoom_image_v1.v:719 + // ../../sources/designs/zoom/zoom_image_v1.v:715 GTP_DFF /* \image_w2_coe[0] */ #( .GRS_EN("TRUE"), @@ -314213,7 +313655,7 @@ module zoom_image_v1 .Q (image_w2_coe[0]), .CLK (clk), .D (image_w2[0])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_w2_coe[1] */ #( .GRS_EN("TRUE"), @@ -314222,7 +313664,7 @@ module zoom_image_v1 .Q (image_w2_coe[1]), .CLK (clk), .D (image_w2[1])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_w2_coe[2] */ #( .GRS_EN("TRUE"), @@ -314231,7 +313673,7 @@ module zoom_image_v1 .Q (image_w2_coe[2]), .CLK (clk), .D (image_w2[2])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_w2_coe[3] */ #( .GRS_EN("TRUE"), @@ -314240,7 +313682,7 @@ module zoom_image_v1 .Q (image_w2_coe[3]), .CLK (clk), .D (image_w2[3])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_w2_coe[4] */ #( .GRS_EN("TRUE"), @@ -314249,7 +313691,7 @@ module zoom_image_v1 .Q (image_w2_coe[4]), .CLK (clk), .D (image_w2[4])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_w2_coe[5] */ #( .GRS_EN("TRUE"), @@ -314258,7 +313700,7 @@ module zoom_image_v1 .Q (image_w2_coe[5]), .CLK (clk), .D (image_w2[5])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \image_w2_coe[6] */ #( .GRS_EN("TRUE"), @@ -314267,7 +313709,7 @@ module zoom_image_v1 .Q (image_w2_coe[6]), .CLK (clk), .D (image_w2[6])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF_R /* \image_w_valid[0] */ #( .GRS_EN("TRUE"), @@ -314277,7 +313719,7 @@ module zoom_image_v1 .CLK (clk), .D (N518), .R (N927)); - // ../../sources/designs/zoom/zoom_image_v1.v:719 + // ../../sources/designs/zoom/zoom_image_v1.v:715 GTP_DFF_R /* \image_w_valid[1] */ #( .GRS_EN("TRUE"), @@ -314287,7 +313729,7 @@ module zoom_image_v1 .CLK (clk), .D (N518_inv), .R (N927)); - // ../../sources/designs/zoom/zoom_image_v1.v:719 + // ../../sources/designs/zoom/zoom_image_v1.v:715 GTP_DFF_E /* \judge_cnt_h[0] */ #( .GRS_EN("TRUE"), @@ -314446,7 +313888,7 @@ module zoom_image_v1 .\u_zoom_image/image_h2_coe1 ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, image_h2_coe1[0]}), .\u_zoom_image/image_w2_coe1 ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, image_w2_coe1[0]}), .CLK (clk)); - // ../../sources/designs/zoom/zoom_image_v1.v:756 + // ../../sources/designs/zoom/zoom_image_v1.v:751 mult_fra0_unq8 mult_fra0_0 ( .P ({\mult_fra0_0_P[15]_floating , coe_mult_p0_0[14], coe_mult_p0_0[13], coe_mult_p0_0[12], coe_mult_p0_0[11], coe_mult_p0_0[10], coe_mult_p0_0[9], coe_mult_p0_0[8], coe_mult_p0_0[7], \mult_fra0_0_P[6]_floating , \mult_fra0_0_P[5]_floating , \mult_fra0_0_P[4]_floating , \mult_fra0_0_P[3]_floating , \mult_fra0_0_P[2]_floating , \mult_fra0_0_P[1]_floating , \mult_fra0_0_P[0]_floating }), @@ -314454,7 +313896,7 @@ module zoom_image_v1 .\u_zoom_image/image_h2_coe1 ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, image_h2_coe1[0]}), .\u_zoom_image/image_w2_coe1 (image_w2_coe1), .CLK (clk)); - // ../../sources/designs/zoom/zoom_image_v1.v:768 + // ../../sources/designs/zoom/zoom_image_v1.v:763 mult_fra0_unq10 mult_fra1 ( .P ({\mult_fra1_P[15]_floating , coe_mult_p1[14], coe_mult_p1[13], coe_mult_p1[12], coe_mult_p1[11], coe_mult_p1[10], coe_mult_p1[9], coe_mult_p1[8], coe_mult_p1[7], \mult_fra1_P[6]_floating , \mult_fra1_P[5]_floating , \mult_fra1_P[4]_floating , \mult_fra1_P[3]_floating , \mult_fra1_P[2]_floating , \mult_fra1_P[1]_floating , \mult_fra1_P[0]_floating }), @@ -314462,14 +313904,14 @@ module zoom_image_v1 .\u_zoom_image/image_h2_coe1 (image_h2_coe1), .\u_zoom_image/image_w2_coe1 ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, image_w2_coe1[0]}), .CLK (clk)); - // ../../sources/designs/zoom/zoom_image_v1.v:762 + // ../../sources/designs/zoom/zoom_image_v1.v:757 mult_fra0_unq12 mult_fra1_0 ( .P ({\mult_fra1_0_P[15]_floating , \mult_fra1_0_P[14]_floating , coe_mult_p1_0[13], coe_mult_p1_0[12], coe_mult_p1_0[11], coe_mult_p1_0[10], coe_mult_p1_0[9], coe_mult_p1_0[8], coe_mult_p1_0[7], \mult_fra1_0_P[6]_floating , \mult_fra1_0_P[5]_floating , \mult_fra1_0_P[4]_floating , \mult_fra1_0_P[3]_floating , \mult_fra1_0_P[2]_floating , \mult_fra1_0_P[1]_floating , \mult_fra1_0_P[0]_floating }), .\u_zoom_image/image_h2_coe1 (image_h2_coe1), .\u_zoom_image/image_w2_coe1 (image_w2_coe1), .CLK (clk)); - // ../../sources/designs/zoom/zoom_image_v1.v:774 + // ../../sources/designs/zoom/zoom_image_v1.v:769 GTP_DFF_E /* \mult_h0[0] */ #( .GRS_EN("TRUE"), @@ -314618,7 +314060,7 @@ module zoom_image_v1 .Q (\mult_image2[0] [7] ), .CLK (clk), .D (N624[7])); - // ../../sources/designs/zoom/zoom_image_v1.v:864 + // ../../sources/designs/zoom/zoom_image_v1.v:859 GTP_DFF /* \mult_image2[0][8] */ #( .GRS_EN("TRUE"), @@ -314627,7 +314069,7 @@ module zoom_image_v1 .Q (\mult_image2[0] [8] ), .CLK (clk), .D (N624[8])); - // ../../sources/designs/zoom/zoom_image_v1.v:864 + // ../../sources/designs/zoom/zoom_image_v1.v:859 GTP_DFF /* \mult_image2[0][9] */ #( .GRS_EN("TRUE"), @@ -314636,7 +314078,7 @@ module zoom_image_v1 .Q (\mult_image2[0] [9] ), .CLK (clk), .D (N624[9])); - // ../../sources/designs/zoom/zoom_image_v1.v:864 + // ../../sources/designs/zoom/zoom_image_v1.v:859 GTP_DFF /* \mult_image2[0][10] */ #( .GRS_EN("TRUE"), @@ -314645,7 +314087,7 @@ module zoom_image_v1 .Q (\mult_image2[0] [10] ), .CLK (clk), .D (N624[10])); - // ../../sources/designs/zoom/zoom_image_v1.v:864 + // ../../sources/designs/zoom/zoom_image_v1.v:859 GTP_DFF /* \mult_image2[0][11] */ #( .GRS_EN("TRUE"), @@ -314654,7 +314096,7 @@ module zoom_image_v1 .Q (\mult_image2[0] [11] ), .CLK (clk), .D (N624[11])); - // ../../sources/designs/zoom/zoom_image_v1.v:864 + // ../../sources/designs/zoom/zoom_image_v1.v:859 GTP_DFF /* \mult_image2[1][7] */ #( .GRS_EN("TRUE"), @@ -314663,7 +314105,7 @@ module zoom_image_v1 .Q (\mult_image2[1] [7] ), .CLK (clk), .D (N634[7])); - // ../../sources/designs/zoom/zoom_image_v1.v:864 + // ../../sources/designs/zoom/zoom_image_v1.v:859 GTP_DFF /* \mult_image2[1][8] */ #( .GRS_EN("TRUE"), @@ -314672,7 +314114,7 @@ module zoom_image_v1 .Q (\mult_image2[1] [8] ), .CLK (clk), .D (N634[8])); - // ../../sources/designs/zoom/zoom_image_v1.v:864 + // ../../sources/designs/zoom/zoom_image_v1.v:859 GTP_DFF /* \mult_image2[1][9] */ #( .GRS_EN("TRUE"), @@ -314681,7 +314123,7 @@ module zoom_image_v1 .Q (\mult_image2[1] [9] ), .CLK (clk), .D (N634[9])); - // ../../sources/designs/zoom/zoom_image_v1.v:864 + // ../../sources/designs/zoom/zoom_image_v1.v:859 GTP_DFF /* \mult_image2[1][10] */ #( .GRS_EN("TRUE"), @@ -314690,7 +314132,7 @@ module zoom_image_v1 .Q (\mult_image2[1] [10] ), .CLK (clk), .D (N634[10])); - // ../../sources/designs/zoom/zoom_image_v1.v:864 + // ../../sources/designs/zoom/zoom_image_v1.v:859 GTP_DFF /* \mult_image2[1][11] */ #( .GRS_EN("TRUE"), @@ -314699,7 +314141,7 @@ module zoom_image_v1 .Q (\mult_image2[1] [11] ), .CLK (clk), .D (N634[11])); - // ../../sources/designs/zoom/zoom_image_v1.v:864 + // ../../sources/designs/zoom/zoom_image_v1.v:859 GTP_DFF /* \mult_image2[1][12] */ #( .GRS_EN("TRUE"), @@ -314708,7 +314150,7 @@ module zoom_image_v1 .Q (\mult_image2[1] [12] ), .CLK (clk), .D (N634[12])); - // ../../sources/designs/zoom/zoom_image_v1.v:864 + // ../../sources/designs/zoom/zoom_image_v1.v:859 GTP_DFF /* \mult_image2[2][7] */ #( .GRS_EN("TRUE"), @@ -314717,7 +314159,7 @@ module zoom_image_v1 .Q (\mult_image2[2] [7] ), .CLK (clk), .D (N644[7])); - // ../../sources/designs/zoom/zoom_image_v1.v:864 + // ../../sources/designs/zoom/zoom_image_v1.v:859 GTP_DFF /* \mult_image2[2][8] */ #( .GRS_EN("TRUE"), @@ -314726,7 +314168,7 @@ module zoom_image_v1 .Q (\mult_image2[2] [8] ), .CLK (clk), .D (N644[8])); - // ../../sources/designs/zoom/zoom_image_v1.v:864 + // ../../sources/designs/zoom/zoom_image_v1.v:859 GTP_DFF /* \mult_image2[2][9] */ #( .GRS_EN("TRUE"), @@ -314735,7 +314177,7 @@ module zoom_image_v1 .Q (\mult_image2[2] [9] ), .CLK (clk), .D (N644[9])); - // ../../sources/designs/zoom/zoom_image_v1.v:864 + // ../../sources/designs/zoom/zoom_image_v1.v:859 GTP_DFF /* \mult_image2[2][10] */ #( .GRS_EN("TRUE"), @@ -314744,7 +314186,7 @@ module zoom_image_v1 .Q (\mult_image2[2] [10] ), .CLK (clk), .D (N644[10])); - // ../../sources/designs/zoom/zoom_image_v1.v:864 + // ../../sources/designs/zoom/zoom_image_v1.v:859 GTP_DFF /* \mult_image2[2][11] */ #( .GRS_EN("TRUE"), @@ -314753,7 +314195,7 @@ module zoom_image_v1 .Q (\mult_image2[2] [11] ), .CLK (clk), .D (N644[11])); - // ../../sources/designs/zoom/zoom_image_v1.v:864 + // ../../sources/designs/zoom/zoom_image_v1.v:859 mult_image_ip mult_image_b0 ( .\u_zoom_image/mult_image1[2] ({\mult_image_b0_u_zoom_image/mult_image1[2][15]_floating , \mult_image_b0_u_zoom_image/mult_image1[2][14]_floating , \mult_image_b0_u_zoom_image/mult_image1[2][13]_floating , \mult_image_b0_u_zoom_image/mult_image1[2][12]_floating , \mult_image1[2] [11] , \mult_image1[2] [10] , \mult_image1[2] [9] , \mult_image1[2] [8] , \mult_image1[2] [7] , \mult_image1[2] [6] , \mult_image1[2] [5] , \mult_image1[2] [4] , \mult_image1[2] [3] , \mult_image1[2] [2] , \mult_image1[2] [1] , \mult_image1[2] [0] }), @@ -314761,8 +314203,6 @@ module zoom_image_v1 .\u_zoom_image/mult_image0[5] ({1'bx, 1'bx, 1'bx, \mult_image0[5] [11] , \mult_image0[5] [10] , \mult_image0[5] [9] , \mult_image0[5] [8] , \mult_image0[5] [7] , \mult_image0[5] [6] , \mult_image0[5] [5] , \mult_image0[5] [4] , \mult_image0[5] [3] , \mult_image0[5] [2] , \mult_image0[5] [1] , \mult_image0[5] [0] }), .\u_zoom_image/rd_data ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, rd_data[4], rd_data[3], rd_data[2], rd_data[1], rd_data[0]}), .CLK (clk), - ._N13107 (_N13107), - ._N13108 (_N13108), ._N13109 (_N13109), ._N13110 (_N13110), ._N13111 (_N13111), @@ -314796,8 +314236,10 @@ module zoom_image_v1 ._N13139 (_N13139), ._N13140 (_N13140), ._N13141 (_N13141), - ._N13142 (_N13142)); - // ../../sources/designs/zoom/zoom_image_v1.v:808 + ._N13142 (_N13142), + ._N13143 (_N13143), + ._N13144 (_N13144)); + // ../../sources/designs/zoom/zoom_image_v1.v:803 mult_image_ip_unq24 mult_image_b0_0 ( .\u_zoom_image/mult_image1_0[2] ({\mult_image_b0_0_u_zoom_image/mult_image1_0[2][15]_floating , \mult_image_b0_0_u_zoom_image/mult_image1_0[2][14]_floating , \mult_image_b0_0_u_zoom_image/mult_image1_0[2][13]_floating , \mult_image_b0_0_u_zoom_image/mult_image1_0[2][12]_floating , \mult_image1_0[2] [11] , \mult_image1_0[2] [10] , \mult_image1_0[2] [9] , \mult_image1_0[2] [8] , \mult_image1_0[2] [7] , \mult_image1_0[2] [6] , \mult_image1_0[2] [5] , \mult_image1_0[2] [4] , \mult_image1_0[2] [3] , \mult_image1_0[2] [2] , \mult_image1_0[2] [1] , \mult_image1_0[2] [0] }), @@ -314805,8 +314247,6 @@ module zoom_image_v1 .\u_zoom_image/mult_image0_0[5] ({1'bx, 1'bx, 1'bx, \mult_image0_0[5] [11] , \mult_image0_0[5] [10] , \mult_image0_0[5] [9] , \mult_image0_0[5] [8] , \mult_image0_0[5] [7] , \mult_image0_0[5] [6] , \mult_image0_0[5] [5] , \mult_image0_0[5] [4] , \mult_image0_0[5] [3] , \mult_image0_0[5] [2] , \mult_image0_0[5] [1] , \mult_image0_0[5] [0] }), .\u_zoom_image/rd_data_0 ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, rd_data_0[4], rd_data_0[3], rd_data_0[2], rd_data_0[1], rd_data_0[0]}), .CLK (clk), - ._N13143 (_N13143), - ._N13144 (_N13144), ._N13145 (_N13145), ._N13146 (_N13146), ._N13147 (_N13147), @@ -314840,15 +314280,15 @@ module zoom_image_v1 ._N13175 (_N13175), ._N13176 (_N13176), ._N13177 (_N13177), - ._N13178 (_N13178)); - // ../../sources/designs/zoom/zoom_image_v1.v:845 + ._N13178 (_N13178), + ._N13179 (_N13179), + ._N13180 (_N13180)); + // ../../sources/designs/zoom/zoom_image_v1.v:840 mult_image_ip_unq26 mult_image_b1 ( .P ({\mult_image_b1_P[14]_floating , \mult_image_b1_P[13]_floating , \mult_image_b1_P[12]_floating , \mult_image0[5] [11] , \mult_image0[5] [10] , \mult_image0[5] [9] , \mult_image0[5] [8] , \mult_image0[5] [7] , \mult_image0[5] [6] , \mult_image0[5] [5] , \mult_image0[5] [4] , \mult_image0[5] [3] , \mult_image0[5] [2] , \mult_image0[5] [1] , \mult_image0[5] [0] }), .A ({1'bx, coe_mult_p1[14], coe_mult_p1[13], coe_mult_p1[12], coe_mult_p1[11], coe_mult_p1[10], coe_mult_p1[9], coe_mult_p1[8], coe_mult_p1[7]}), .\u_zoom_image/rd_data ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, rd_data[20], rd_data[19], rd_data[18], rd_data[17], rd_data[16], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), - ._N13107 (_N13107), - ._N13108 (_N13108), ._N13109 (_N13109), ._N13110 (_N13110), ._N13111 (_N13111), @@ -314883,15 +314323,15 @@ module zoom_image_v1 ._N13140 (_N13140), ._N13141 (_N13141), ._N13142 (_N13142), + ._N13143 (_N13143), + ._N13144 (_N13144), .CLK (clk)); - // ../../sources/designs/zoom/zoom_image_v1.v:814 + // ../../sources/designs/zoom/zoom_image_v1.v:809 mult_image_ip_unq28 mult_image_b1_0 ( .P ({\mult_image_b1_0_P[14]_floating , \mult_image_b1_0_P[13]_floating , \mult_image_b1_0_P[12]_floating , \mult_image0_0[5] [11] , \mult_image0_0[5] [10] , \mult_image0_0[5] [9] , \mult_image0_0[5] [8] , \mult_image0_0[5] [7] , \mult_image0_0[5] [6] , \mult_image0_0[5] [5] , \mult_image0_0[5] [4] , \mult_image0_0[5] [3] , \mult_image0_0[5] [2] , \mult_image0_0[5] [1] , \mult_image0_0[5] [0] }), .A ({1'bx, 1'bx, coe_mult_p1_0[13], coe_mult_p1_0[12], coe_mult_p1_0[11], coe_mult_p1_0[10], coe_mult_p1_0[9], coe_mult_p1_0[8], coe_mult_p1_0[7]}), .\u_zoom_image/rd_data_0 ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, rd_data_0[20], rd_data_0[19], rd_data_0[18], rd_data_0[17], rd_data_0[16], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), - ._N13143 (_N13143), - ._N13144 (_N13144), ._N13145 (_N13145), ._N13146 (_N13146), ._N13147 (_N13147), @@ -314926,15 +314366,15 @@ module zoom_image_v1 ._N13176 (_N13176), ._N13177 (_N13177), ._N13178 (_N13178), + ._N13179 (_N13179), + ._N13180 (_N13180), .CLK (clk)); - // ../../sources/designs/zoom/zoom_image_v1.v:851 + // ../../sources/designs/zoom/zoom_image_v1.v:846 mult_image_ip_unq30 mult_image_g0 ( .P ({\mult_image_g0_P[14]_floating , \mult_image_g0_P[13]_floating , \mult_image0[2] [12] , \mult_image0[2] [11] , \mult_image0[2] [10] , \mult_image0[2] [9] , \mult_image0[2] [8] , \mult_image0[2] [7] , \mult_image0[2] [6] , \mult_image0[2] [5] , \mult_image0[2] [4] , \mult_image0[2] [3] , \mult_image0[2] [2] , \mult_image0[2] [1] , \mult_image0[2] [0] }), .A ({coe_mult_p0[15], coe_mult_p0[14], coe_mult_p0[13], coe_mult_p0[12], coe_mult_p0[11], coe_mult_p0[10], coe_mult_p0[9], coe_mult_p0[8], coe_mult_p0[7]}), .\u_zoom_image/rd_data ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, rd_data[10], rd_data[9], rd_data[8], rd_data[7], rd_data[6], rd_data[5], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), - ._N13036 (_N13036), - ._N13037 (_N13037), ._N13038 (_N13038), ._N13039 (_N13039), ._N13040 (_N13040), @@ -314968,15 +314408,15 @@ module zoom_image_v1 ._N13068 (_N13068), ._N13069 (_N13069), ._N13070 (_N13070), + ._N13071 (_N13071), + ._N13072 (_N13072), .CLK (clk)); - // ../../sources/designs/zoom/zoom_image_v1.v:796 + // ../../sources/designs/zoom/zoom_image_v1.v:791 mult_image_ip_unq32 mult_image_g0_0 ( .P ({\mult_image_g0_0_P[14]_floating , \mult_image_g0_0_P[13]_floating , \mult_image0_0[2] [12] , \mult_image0_0[2] [11] , \mult_image0_0[2] [10] , \mult_image0_0[2] [9] , \mult_image0_0[2] [8] , \mult_image0_0[2] [7] , \mult_image0_0[2] [6] , \mult_image0_0[2] [5] , \mult_image0_0[2] [4] , \mult_image0_0[2] [3] , \mult_image0_0[2] [2] , \mult_image0_0[2] [1] , \mult_image0_0[2] [0] }), .A ({1'bx, coe_mult_p0_0[14], coe_mult_p0_0[13], coe_mult_p0_0[12], coe_mult_p0_0[11], coe_mult_p0_0[10], coe_mult_p0_0[9], coe_mult_p0_0[8], coe_mult_p0_0[7]}), .\u_zoom_image/rd_data_0 ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, rd_data_0[10], rd_data_0[9], rd_data_0[8], rd_data_0[7], rd_data_0[6], rd_data_0[5], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), - ._N13001 (_N13001), - ._N13002 (_N13002), ._N13003 (_N13003), ._N13004 (_N13004), ._N13005 (_N13005), @@ -315010,8 +314450,10 @@ module zoom_image_v1 ._N13033 (_N13033), ._N13034 (_N13034), ._N13035 (_N13035), + ._N13036 (_N13036), + ._N13037 (_N13037), .CLK (clk)); - // ../../sources/designs/zoom/zoom_image_v1.v:833 + // ../../sources/designs/zoom/zoom_image_v1.v:828 mult_image_ip_unq34 mult_image_g1 ( .\u_zoom_image/mult_image1[1] ({\mult_image_g1_u_zoom_image/mult_image1[1][15]_floating , \mult_image_g1_u_zoom_image/mult_image1[1][14]_floating , \mult_image_g1_u_zoom_image/mult_image1[1][13]_floating , \mult_image1[1] [12] , \mult_image1[1] [11] , \mult_image1[1] [10] , \mult_image1[1] [9] , \mult_image1[1] [8] , \mult_image1[1] [7] , \mult_image1[1] [6] , \mult_image1[1] [5] , \mult_image1[1] [4] , \mult_image1[1] [3] , \mult_image1[1] [2] , \mult_image1[1] [1] , \mult_image1[1] [0] }), @@ -315019,8 +314461,6 @@ module zoom_image_v1 .\u_zoom_image/mult_image0[2] ({1'bx, 1'bx, \mult_image0[2] [12] , \mult_image0[2] [11] , \mult_image0[2] [10] , \mult_image0[2] [9] , \mult_image0[2] [8] , \mult_image0[2] [7] , \mult_image0[2] [6] , \mult_image0[2] [5] , \mult_image0[2] [4] , \mult_image0[2] [3] , \mult_image0[2] [2] , \mult_image0[2] [1] , \mult_image0[2] [0] }), .\u_zoom_image/rd_data ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, rd_data[26], rd_data[25], rd_data[24], rd_data[23], rd_data[22], rd_data[21], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), .CLK (clk), - ._N13036 (_N13036), - ._N13037 (_N13037), ._N13038 (_N13038), ._N13039 (_N13039), ._N13040 (_N13040), @@ -315053,8 +314493,10 @@ module zoom_image_v1 ._N13067 (_N13067), ._N13068 (_N13068), ._N13069 (_N13069), - ._N13070 (_N13070)); - // ../../sources/designs/zoom/zoom_image_v1.v:802 + ._N13070 (_N13070), + ._N13071 (_N13071), + ._N13072 (_N13072)); + // ../../sources/designs/zoom/zoom_image_v1.v:797 mult_image_ip_unq36 mult_image_g1_0 ( .\u_zoom_image/mult_image1_0[1] ({\mult_image_g1_0_u_zoom_image/mult_image1_0[1][15]_floating , \mult_image_g1_0_u_zoom_image/mult_image1_0[1][14]_floating , \mult_image_g1_0_u_zoom_image/mult_image1_0[1][13]_floating , \mult_image1_0[1] [12] , \mult_image1_0[1] [11] , \mult_image1_0[1] [10] , \mult_image1_0[1] [9] , \mult_image1_0[1] [8] , \mult_image1_0[1] [7] , \mult_image1_0[1] [6] , \mult_image1_0[1] [5] , \mult_image1_0[1] [4] , \mult_image1_0[1] [3] , \mult_image1_0[1] [2] , \mult_image1_0[1] [1] , \mult_image1_0[1] [0] }), @@ -315062,8 +314504,6 @@ module zoom_image_v1 .\u_zoom_image/mult_image0_0[2] ({1'bx, 1'bx, \mult_image0_0[2] [12] , \mult_image0_0[2] [11] , \mult_image0_0[2] [10] , \mult_image0_0[2] [9] , \mult_image0_0[2] [8] , \mult_image0_0[2] [7] , \mult_image0_0[2] [6] , \mult_image0_0[2] [5] , \mult_image0_0[2] [4] , \mult_image0_0[2] [3] , \mult_image0_0[2] [2] , \mult_image0_0[2] [1] , \mult_image0_0[2] [0] }), .\u_zoom_image/rd_data_0 ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, rd_data_0[26], rd_data_0[25], rd_data_0[24], rd_data_0[23], rd_data_0[22], rd_data_0[21], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), .CLK (clk), - ._N13001 (_N13001), - ._N13002 (_N13002), ._N13003 (_N13003), ._N13004 (_N13004), ._N13005 (_N13005), @@ -315096,8 +314536,10 @@ module zoom_image_v1 ._N13032 (_N13032), ._N13033 (_N13033), ._N13034 (_N13034), - ._N13035 (_N13035)); - // ../../sources/designs/zoom/zoom_image_v1.v:839 + ._N13035 (_N13035), + ._N13036 (_N13036), + ._N13037 (_N13037)); + // ../../sources/designs/zoom/zoom_image_v1.v:834 mult_image_ip_unq38 mult_image_r0 ( .\u_zoom_image/mult_image1[0] ({\mult_image_r0_u_zoom_image/mult_image1[0][15]_floating , \mult_image_r0_u_zoom_image/mult_image1[0][14]_floating , \mult_image_r0_u_zoom_image/mult_image1[0][13]_floating , \mult_image_r0_u_zoom_image/mult_image1[0][12]_floating , \mult_image1[0] [11] , \mult_image1[0] [10] , \mult_image1[0] [9] , \mult_image1[0] [8] , \mult_image1[0] [7] , \mult_image1[0] [6] , \mult_image1[0] [5] , \mult_image1[0] [4] , \mult_image1[0] [3] , \mult_image1[0] [2] , \mult_image1[0] [1] , \mult_image1[0] [0] }), @@ -315105,8 +314547,6 @@ module zoom_image_v1 .\u_zoom_image/mult_image0[1] ({1'bx, 1'bx, 1'bx, \mult_image0[1] [11] , \mult_image0[1] [10] , \mult_image0[1] [9] , \mult_image0[1] [8] , \mult_image0[1] [7] , \mult_image0[1] [6] , \mult_image0[1] [5] , \mult_image0[1] [4] , \mult_image0[1] [3] , \mult_image0[1] [2] , \mult_image0[1] [1] , \mult_image0[1] [0] }), .\u_zoom_image/rd_data ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, rd_data[15], rd_data[14], rd_data[13], rd_data[12], rd_data[11], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), .CLK (clk), - ._N12965 (_N12965), - ._N12966 (_N12966), ._N12967 (_N12967), ._N12968 (_N12968), ._N12969 (_N12969), @@ -315140,8 +314580,10 @@ module zoom_image_v1 ._N12997 (_N12997), ._N12998 (_N12998), ._N12999 (_N12999), - ._N13000 (_N13000)); - // ../../sources/designs/zoom/zoom_image_v1.v:784 + ._N13000 (_N13000), + ._N13001 (_N13001), + ._N13002 (_N13002)); + // ../../sources/designs/zoom/zoom_image_v1.v:779 mult_image_ip_unq40 mult_image_r0_0 ( .\u_zoom_image/mult_image1_0[0] ({\mult_image_r0_0_u_zoom_image/mult_image1_0[0][15]_floating , \mult_image_r0_0_u_zoom_image/mult_image1_0[0][14]_floating , \mult_image_r0_0_u_zoom_image/mult_image1_0[0][13]_floating , \mult_image_r0_0_u_zoom_image/mult_image1_0[0][12]_floating , \mult_image1_0[0] [11] , \mult_image1_0[0] [10] , \mult_image1_0[0] [9] , \mult_image1_0[0] [8] , \mult_image1_0[0] [7] , \mult_image1_0[0] [6] , \mult_image1_0[0] [5] , \mult_image1_0[0] [4] , \mult_image1_0[0] [3] , \mult_image1_0[0] [2] , \mult_image1_0[0] [1] , \mult_image1_0[0] [0] }), @@ -315149,8 +314591,6 @@ module zoom_image_v1 .\u_zoom_image/mult_image0_0[1] ({1'bx, 1'bx, 1'bx, \mult_image0_0[1] [11] , \mult_image0_0[1] [10] , \mult_image0_0[1] [9] , \mult_image0_0[1] [8] , \mult_image0_0[1] [7] , \mult_image0_0[1] [6] , \mult_image0_0[1] [5] , \mult_image0_0[1] [4] , \mult_image0_0[1] [3] , \mult_image0_0[1] [2] , \mult_image0_0[1] [1] , \mult_image0_0[1] [0] }), .\u_zoom_image/rd_data_0 ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, rd_data_0[15], rd_data_0[14], rd_data_0[13], rd_data_0[12], rd_data_0[11], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), .CLK (clk), - ._N13071 (_N13071), - ._N13072 (_N13072), ._N13073 (_N13073), ._N13074 (_N13074), ._N13075 (_N13075), @@ -315184,15 +314624,15 @@ module zoom_image_v1 ._N13103 (_N13103), ._N13104 (_N13104), ._N13105 (_N13105), - ._N13106 (_N13106)); - // ../../sources/designs/zoom/zoom_image_v1.v:821 + ._N13106 (_N13106), + ._N13107 (_N13107), + ._N13108 (_N13108)); + // ../../sources/designs/zoom/zoom_image_v1.v:816 mult_image_ip_unq42 mult_image_r1 ( .P ({\mult_image_r1_P[14]_floating , \mult_image_r1_P[13]_floating , \mult_image_r1_P[12]_floating , \mult_image0[1] [11] , \mult_image0[1] [10] , \mult_image0[1] [9] , \mult_image0[1] [8] , \mult_image0[1] [7] , \mult_image0[1] [6] , \mult_image0[1] [5] , \mult_image0[1] [4] , \mult_image0[1] [3] , \mult_image0[1] [2] , \mult_image0[1] [1] , \mult_image0[1] [0] }), .A ({1'bx, coe_mult_p1[14], coe_mult_p1[13], coe_mult_p1[12], coe_mult_p1[11], coe_mult_p1[10], coe_mult_p1[9], coe_mult_p1[8], coe_mult_p1[7]}), .\u_zoom_image/rd_data ({rd_data[31], rd_data[30], rd_data[29], rd_data[28], rd_data[27], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), - ._N12965 (_N12965), - ._N12966 (_N12966), ._N12967 (_N12967), ._N12968 (_N12968), ._N12969 (_N12969), @@ -315227,15 +314667,15 @@ module zoom_image_v1 ._N12998 (_N12998), ._N12999 (_N12999), ._N13000 (_N13000), + ._N13001 (_N13001), + ._N13002 (_N13002), .CLK (clk)); - // ../../sources/designs/zoom/zoom_image_v1.v:790 + // ../../sources/designs/zoom/zoom_image_v1.v:785 mult_image_ip_unq44 mult_image_r1_0 ( .P ({\mult_image_r1_0_P[14]_floating , \mult_image_r1_0_P[13]_floating , \mult_image_r1_0_P[12]_floating , \mult_image0_0[1] [11] , \mult_image0_0[1] [10] , \mult_image0_0[1] [9] , \mult_image0_0[1] [8] , \mult_image0_0[1] [7] , \mult_image0_0[1] [6] , \mult_image0_0[1] [5] , \mult_image0_0[1] [4] , \mult_image0_0[1] [3] , \mult_image0_0[1] [2] , \mult_image0_0[1] [1] , \mult_image0_0[1] [0] }), .A ({1'bx, 1'bx, coe_mult_p1_0[13], coe_mult_p1_0[12], coe_mult_p1_0[11], coe_mult_p1_0[10], coe_mult_p1_0[9], coe_mult_p1_0[8], coe_mult_p1_0[7]}), .\u_zoom_image/rd_data_0 ({rd_data_0[31], rd_data_0[30], rd_data_0[29], rd_data_0[28], rd_data_0[27], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), - ._N13071 (_N13071), - ._N13072 (_N13072), ._N13073 (_N13073), ._N13074 (_N13074), ._N13075 (_N13075), @@ -315270,8 +314710,10 @@ module zoom_image_v1 ._N13104 (_N13104), ._N13105 (_N13105), ._N13106 (_N13106), + ._N13107 (_N13107), + ._N13108 (_N13108), .CLK (clk)); - // ../../sources/designs/zoom/zoom_image_v1.v:827 + // ../../sources/designs/zoom/zoom_image_v1.v:822 GTP_DFF_E /* no_need_rd_ddr */ #( .GRS_EN("TRUE"), @@ -315302,7 +314744,7 @@ module zoom_image_v1 .Q (ram_ch0[0]), .CLK (clk), .D (ram_ch[0])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \ram_ch0[1] */ #( .GRS_EN("TRUE"), @@ -315311,7 +314753,7 @@ module zoom_image_v1 .Q (ram_ch0[1]), .CLK (clk), .D (ram_ch[1])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \ram_ch1[0] */ #( .GRS_EN("TRUE"), @@ -315320,7 +314762,7 @@ module zoom_image_v1 .Q (ram_ch1[0]), .CLK (clk), .D (ram_ch0[0])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \ram_ch1[1] */ #( .GRS_EN("TRUE"), @@ -315329,7 +314771,7 @@ module zoom_image_v1 .Q (ram_ch1[1]), .CLK (clk), .D (ram_ch0[1])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \ram_ch2[0] */ #( .GRS_EN("TRUE"), @@ -315338,7 +314780,7 @@ module zoom_image_v1 .Q (ram_ch2[0]), .CLK (clk), .D (ram_ch1[0])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \ram_ch2[1] */ #( .GRS_EN("TRUE"), @@ -315347,7 +314789,7 @@ module zoom_image_v1 .Q (ram_ch2[1]), .CLK (clk), .D (ram_ch1[1])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF_RE /* \ram_ch[0] */ #( .GRS_EN("TRUE"), @@ -315377,7 +314819,7 @@ module zoom_image_v1 ram_idle_vname ( .Q (ram_idle), .CLK (clk), - .D (_N103322)); + .D (_N104134)); // defparam ram_idle_vname.orig_name = ram_idle; // ../../sources/designs/zoom/zoom_image_v1.v:139 @@ -315404,7 +314846,7 @@ module zoom_image_v1 GTP_LUT5 /* ram_idle_ce_mux */ #( .INIT(32'b10110001101000001011000010110000)) ram_idle_ce_mux ( - .Z (_N103322), + .Z (_N104134), .I0 (rst), .I1 (zoom_sta_reg[0]), .I2 (ram_idle), @@ -315412,6 +314854,15 @@ module zoom_image_v1 .I4 (zoom_sta_reg[3])); // LUT = (I0&I2)|(~I1&I2&~I4)|(~I0&~I1&I3&I4) ; + GTP_LUT2 /* \ram_sta_fsm[3:0]_2 */ #( + .INIT(4'b1000)) + \ram_sta_fsm[3:0]_2 ( + .Z (_N23), + .I0 (N1014[0]), + .I1 (ram_sta[3])); + // LUT = I0&I1 ; + // ../../sources/designs/zoom/zoom_image_v1.v:446 + GTP_LUT5 /* \ram_sta_fsm[3:0]_3 */ #( .INIT(32'b10100000111011001110110011101100)) \ram_sta_fsm[3:0]_3 ( @@ -315420,7 +314871,7 @@ module zoom_image_v1 .I1 (ram_sta[0]), .I2 (ram_sta[3]), .I3 (N1014[3]), - .I4 (_N105031)); + .I4 (_N105578)); // LUT = (I1&~I4)|(I1&~I3)|(I0&I2) ; GTP_LUT3 /* \ram_sta_fsm[3:0]_4 */ #( @@ -315429,7 +314880,7 @@ module zoom_image_v1 .Z (_N25), .I0 (ram_sta[0]), .I1 (N1014[3]), - .I2 (_N105031)); + .I2 (_N105578)); // LUT = I0&I1&I2 ; GTP_LUT5 /* \ram_sta_fsm[3:0]_6 */ #( @@ -315438,9 +314889,9 @@ module zoom_image_v1 .Z (_N27), .I0 (_N25), .I1 (ram_sta[1]), - .I2 (_N104995), - .I3 (_N104996), - .I4 (_N104997)); + .I2 (_N105542), + .I3 (_N105543), + .I4 (_N105544)); // LUT = (I0)|(I1&~I4)|(I1&~I3)|(I1&~I2) ; // ../../sources/designs/zoom/zoom_image_v1.v:446 @@ -315449,9 +314900,9 @@ module zoom_image_v1 \ram_sta_fsm[3:0]_7 ( .Z (_N28), .I0 (ram_sta[1]), - .I1 (_N104995), - .I2 (_N104996), - .I3 (_N104997)); + .I1 (_N105542), + .I2 (_N105543), + .I3 (_N105544)); // LUT = I0&I1&I2&I3 ; // ../../sources/designs/zoom/zoom_image_v1.v:446 @@ -315728,7 +315179,7 @@ module zoom_image_v1 .Q (rd_data_0[0]), .CLK (clk), .D (N491[0])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data_0[1] */ #( .GRS_EN("TRUE"), @@ -315737,7 +315188,7 @@ module zoom_image_v1 .Q (rd_data_0[1]), .CLK (clk), .D (N491[1])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data_0[2] */ #( .GRS_EN("TRUE"), @@ -315746,7 +315197,7 @@ module zoom_image_v1 .Q (rd_data_0[2]), .CLK (clk), .D (N491[2])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data_0[3] */ #( .GRS_EN("TRUE"), @@ -315755,7 +315206,7 @@ module zoom_image_v1 .Q (rd_data_0[3]), .CLK (clk), .D (N491[3])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data_0[4] */ #( .GRS_EN("TRUE"), @@ -315764,7 +315215,7 @@ module zoom_image_v1 .Q (rd_data_0[4]), .CLK (clk), .D (N491[4])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data_0[5] */ #( .GRS_EN("TRUE"), @@ -315773,7 +315224,7 @@ module zoom_image_v1 .Q (rd_data_0[5]), .CLK (clk), .D (N491[5])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data_0[6] */ #( .GRS_EN("TRUE"), @@ -315782,7 +315233,7 @@ module zoom_image_v1 .Q (rd_data_0[6]), .CLK (clk), .D (N491[6])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data_0[7] */ #( .GRS_EN("TRUE"), @@ -315791,7 +315242,7 @@ module zoom_image_v1 .Q (rd_data_0[7]), .CLK (clk), .D (N491[7])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data_0[8] */ #( .GRS_EN("TRUE"), @@ -315800,7 +315251,7 @@ module zoom_image_v1 .Q (rd_data_0[8]), .CLK (clk), .D (N491[8])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data_0[9] */ #( .GRS_EN("TRUE"), @@ -315809,7 +315260,7 @@ module zoom_image_v1 .Q (rd_data_0[9]), .CLK (clk), .D (N491[9])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data_0[10] */ #( .GRS_EN("TRUE"), @@ -315818,7 +315269,7 @@ module zoom_image_v1 .Q (rd_data_0[10]), .CLK (clk), .D (N491[10])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data_0[11] */ #( .GRS_EN("TRUE"), @@ -315827,7 +315278,7 @@ module zoom_image_v1 .Q (rd_data_0[11]), .CLK (clk), .D (N491[11])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data_0[12] */ #( .GRS_EN("TRUE"), @@ -315836,7 +315287,7 @@ module zoom_image_v1 .Q (rd_data_0[12]), .CLK (clk), .D (N491[12])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data_0[13] */ #( .GRS_EN("TRUE"), @@ -315845,7 +315296,7 @@ module zoom_image_v1 .Q (rd_data_0[13]), .CLK (clk), .D (N491[13])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data_0[14] */ #( .GRS_EN("TRUE"), @@ -315854,7 +315305,7 @@ module zoom_image_v1 .Q (rd_data_0[14]), .CLK (clk), .D (N491[14])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data_0[15] */ #( .GRS_EN("TRUE"), @@ -315863,7 +315314,7 @@ module zoom_image_v1 .Q (rd_data_0[15]), .CLK (clk), .D (N491[15])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data_0[16] */ #( .GRS_EN("TRUE"), @@ -315872,7 +315323,7 @@ module zoom_image_v1 .Q (rd_data_0[16]), .CLK (clk), .D (N491[16])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data_0[17] */ #( .GRS_EN("TRUE"), @@ -315881,7 +315332,7 @@ module zoom_image_v1 .Q (rd_data_0[17]), .CLK (clk), .D (N491[17])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data_0[18] */ #( .GRS_EN("TRUE"), @@ -315890,7 +315341,7 @@ module zoom_image_v1 .Q (rd_data_0[18]), .CLK (clk), .D (N491[18])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data_0[19] */ #( .GRS_EN("TRUE"), @@ -315899,7 +315350,7 @@ module zoom_image_v1 .Q (rd_data_0[19]), .CLK (clk), .D (N491[19])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data_0[20] */ #( .GRS_EN("TRUE"), @@ -315908,7 +315359,7 @@ module zoom_image_v1 .Q (rd_data_0[20]), .CLK (clk), .D (N491[20])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data_0[21] */ #( .GRS_EN("TRUE"), @@ -315917,7 +315368,7 @@ module zoom_image_v1 .Q (rd_data_0[21]), .CLK (clk), .D (N491[21])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data_0[22] */ #( .GRS_EN("TRUE"), @@ -315926,7 +315377,7 @@ module zoom_image_v1 .Q (rd_data_0[22]), .CLK (clk), .D (N491[22])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data_0[23] */ #( .GRS_EN("TRUE"), @@ -315935,7 +315386,7 @@ module zoom_image_v1 .Q (rd_data_0[23]), .CLK (clk), .D (N491[23])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data_0[24] */ #( .GRS_EN("TRUE"), @@ -315944,7 +315395,7 @@ module zoom_image_v1 .Q (rd_data_0[24]), .CLK (clk), .D (N491[24])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data_0[25] */ #( .GRS_EN("TRUE"), @@ -315953,7 +315404,7 @@ module zoom_image_v1 .Q (rd_data_0[25]), .CLK (clk), .D (N491[25])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data_0[26] */ #( .GRS_EN("TRUE"), @@ -315962,7 +315413,7 @@ module zoom_image_v1 .Q (rd_data_0[26]), .CLK (clk), .D (N491[26])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data_0[27] */ #( .GRS_EN("TRUE"), @@ -315971,7 +315422,7 @@ module zoom_image_v1 .Q (rd_data_0[27]), .CLK (clk), .D (N491[27])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data_0[28] */ #( .GRS_EN("TRUE"), @@ -315980,7 +315431,7 @@ module zoom_image_v1 .Q (rd_data_0[28]), .CLK (clk), .D (N491[28])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data_0[29] */ #( .GRS_EN("TRUE"), @@ -315989,7 +315440,7 @@ module zoom_image_v1 .Q (rd_data_0[29]), .CLK (clk), .D (N491[29])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data_0[30] */ #( .GRS_EN("TRUE"), @@ -315998,7 +315449,7 @@ module zoom_image_v1 .Q (rd_data_0[30]), .CLK (clk), .D (N491[30])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data_0[31] */ #( .GRS_EN("TRUE"), @@ -316007,7 +315458,7 @@ module zoom_image_v1 .Q (rd_data_0[31]), .CLK (clk), .D (N491[31])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data[0] */ #( .GRS_EN("TRUE"), @@ -316016,7 +315467,7 @@ module zoom_image_v1 .Q (rd_data[0]), .CLK (clk), .D (N490[0])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data[1] */ #( .GRS_EN("TRUE"), @@ -316025,7 +315476,7 @@ module zoom_image_v1 .Q (rd_data[1]), .CLK (clk), .D (N490[1])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data[2] */ #( .GRS_EN("TRUE"), @@ -316034,7 +315485,7 @@ module zoom_image_v1 .Q (rd_data[2]), .CLK (clk), .D (N490[2])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data[3] */ #( .GRS_EN("TRUE"), @@ -316043,7 +315494,7 @@ module zoom_image_v1 .Q (rd_data[3]), .CLK (clk), .D (N490[3])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data[4] */ #( .GRS_EN("TRUE"), @@ -316052,7 +315503,7 @@ module zoom_image_v1 .Q (rd_data[4]), .CLK (clk), .D (N490[4])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data[5] */ #( .GRS_EN("TRUE"), @@ -316061,7 +315512,7 @@ module zoom_image_v1 .Q (rd_data[5]), .CLK (clk), .D (N490[5])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data[6] */ #( .GRS_EN("TRUE"), @@ -316070,7 +315521,7 @@ module zoom_image_v1 .Q (rd_data[6]), .CLK (clk), .D (N490[6])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data[7] */ #( .GRS_EN("TRUE"), @@ -316079,7 +315530,7 @@ module zoom_image_v1 .Q (rd_data[7]), .CLK (clk), .D (N490[7])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data[8] */ #( .GRS_EN("TRUE"), @@ -316088,7 +315539,7 @@ module zoom_image_v1 .Q (rd_data[8]), .CLK (clk), .D (N490[8])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data[9] */ #( .GRS_EN("TRUE"), @@ -316097,7 +315548,7 @@ module zoom_image_v1 .Q (rd_data[9]), .CLK (clk), .D (N490[9])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data[10] */ #( .GRS_EN("TRUE"), @@ -316106,7 +315557,7 @@ module zoom_image_v1 .Q (rd_data[10]), .CLK (clk), .D (N490[10])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data[11] */ #( .GRS_EN("TRUE"), @@ -316115,7 +315566,7 @@ module zoom_image_v1 .Q (rd_data[11]), .CLK (clk), .D (N490[11])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data[12] */ #( .GRS_EN("TRUE"), @@ -316124,7 +315575,7 @@ module zoom_image_v1 .Q (rd_data[12]), .CLK (clk), .D (N490[12])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data[13] */ #( .GRS_EN("TRUE"), @@ -316133,7 +315584,7 @@ module zoom_image_v1 .Q (rd_data[13]), .CLK (clk), .D (N490[13])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data[14] */ #( .GRS_EN("TRUE"), @@ -316142,7 +315593,7 @@ module zoom_image_v1 .Q (rd_data[14]), .CLK (clk), .D (N490[14])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data[15] */ #( .GRS_EN("TRUE"), @@ -316151,7 +315602,7 @@ module zoom_image_v1 .Q (rd_data[15]), .CLK (clk), .D (N490[15])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data[16] */ #( .GRS_EN("TRUE"), @@ -316160,7 +315611,7 @@ module zoom_image_v1 .Q (rd_data[16]), .CLK (clk), .D (N490[16])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data[17] */ #( .GRS_EN("TRUE"), @@ -316169,7 +315620,7 @@ module zoom_image_v1 .Q (rd_data[17]), .CLK (clk), .D (N490[17])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data[18] */ #( .GRS_EN("TRUE"), @@ -316178,7 +315629,7 @@ module zoom_image_v1 .Q (rd_data[18]), .CLK (clk), .D (N490[18])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data[19] */ #( .GRS_EN("TRUE"), @@ -316187,7 +315638,7 @@ module zoom_image_v1 .Q (rd_data[19]), .CLK (clk), .D (N490[19])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data[20] */ #( .GRS_EN("TRUE"), @@ -316196,7 +315647,7 @@ module zoom_image_v1 .Q (rd_data[20]), .CLK (clk), .D (N490[20])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data[21] */ #( .GRS_EN("TRUE"), @@ -316205,7 +315656,7 @@ module zoom_image_v1 .Q (rd_data[21]), .CLK (clk), .D (N490[21])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data[22] */ #( .GRS_EN("TRUE"), @@ -316214,7 +315665,7 @@ module zoom_image_v1 .Q (rd_data[22]), .CLK (clk), .D (N490[22])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data[23] */ #( .GRS_EN("TRUE"), @@ -316223,7 +315674,7 @@ module zoom_image_v1 .Q (rd_data[23]), .CLK (clk), .D (N490[23])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data[24] */ #( .GRS_EN("TRUE"), @@ -316232,7 +315683,7 @@ module zoom_image_v1 .Q (rd_data[24]), .CLK (clk), .D (N490[24])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data[25] */ #( .GRS_EN("TRUE"), @@ -316241,7 +315692,7 @@ module zoom_image_v1 .Q (rd_data[25]), .CLK (clk), .D (N490[25])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data[26] */ #( .GRS_EN("TRUE"), @@ -316250,7 +315701,7 @@ module zoom_image_v1 .Q (rd_data[26]), .CLK (clk), .D (N490[26])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data[27] */ #( .GRS_EN("TRUE"), @@ -316259,7 +315710,7 @@ module zoom_image_v1 .Q (rd_data[27]), .CLK (clk), .D (N490[27])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data[28] */ #( .GRS_EN("TRUE"), @@ -316268,7 +315719,7 @@ module zoom_image_v1 .Q (rd_data[28]), .CLK (clk), .D (N490[28])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data[29] */ #( .GRS_EN("TRUE"), @@ -316277,7 +315728,7 @@ module zoom_image_v1 .Q (rd_data[29]), .CLK (clk), .D (N490[29])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data[30] */ #( .GRS_EN("TRUE"), @@ -316286,7 +315737,7 @@ module zoom_image_v1 .Q (rd_data[30]), .CLK (clk), .D (N490[30])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* \rd_data[31] */ #( .GRS_EN("TRUE"), @@ -316295,7 +315746,7 @@ module zoom_image_v1 .Q (rd_data[31]), .CLK (clk), .D (N490[31])); - // ../../sources/designs/zoom/zoom_image_v1.v:676 + // ../../sources/designs/zoom/zoom_image_v1.v:672 GTP_DFF /* rd_one_ram */ #( .GRS_EN("TRUE"), @@ -317136,7 +316587,7 @@ module zoom_image_v1 .Q (zoom_num1[0]), .CLK (clk), .D (zoom_num0[1])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \zoom_num1[1] */ #( .GRS_EN("TRUE"), @@ -317145,7 +316596,7 @@ module zoom_image_v1 .Q (zoom_num1[1]), .CLK (clk), .D (zoom_num0[2])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \zoom_num1[2] */ #( .GRS_EN("TRUE"), @@ -317154,7 +316605,7 @@ module zoom_image_v1 .Q (zoom_num1[2]), .CLK (clk), .D (zoom_num0[3])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \zoom_num1[3] */ #( .GRS_EN("TRUE"), @@ -317163,7 +316614,7 @@ module zoom_image_v1 .Q (zoom_num1[3]), .CLK (clk), .D (zoom_num0[4])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \zoom_num1[4] */ #( .GRS_EN("TRUE"), @@ -317172,7 +316623,7 @@ module zoom_image_v1 .Q (zoom_num1[4]), .CLK (clk), .D (zoom_num0[5])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \zoom_num1[5] */ #( .GRS_EN("TRUE"), @@ -317181,7 +316632,7 @@ module zoom_image_v1 .Q (zoom_num1[5]), .CLK (clk), .D (zoom_num0[6])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \zoom_num1[6] */ #( .GRS_EN("TRUE"), @@ -317190,7 +316641,7 @@ module zoom_image_v1 .Q (zoom_num1[6]), .CLK (clk), .D (zoom_num0[7])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \zoom_num1[7] */ #( .GRS_EN("TRUE"), @@ -317199,7 +316650,7 @@ module zoom_image_v1 .Q (zoom_num1[7]), .CLK (clk), .D (zoom_num0[8])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 GTP_DFF /* \zoom_num1[8] */ #( .GRS_EN("TRUE"), @@ -317208,7 +316659,7 @@ module zoom_image_v1 .Q (zoom_num1[8]), .CLK (clk), .D (zoom_num0[9])); - // ../../sources/designs/zoom/zoom_image_v1.v:666 + // ../../sources/designs/zoom/zoom_image_v1.v:662 zoom_ram zoom_ram0 ( .rd_data (doutb0), @@ -317313,7 +316764,7 @@ module zoom_image_v1 .INIT(16'b1111100010001000)) \zoom_sta_fsm[6:0]_19 ( .Z (_N53), - .I0 (_N96561), + .I0 (_N97307), .I1 (judge_cnt_h_valid), .I2 (record_ram_valid), .I3 (zoom_sta_reg[3])); @@ -317359,7 +316810,7 @@ module zoom_image_v1 .INIT(32'b00001000111111110000100000001000)) \zoom_sta_fsm[6:0]_34 ( .Z (_N68), - .I0 (_N96561), + .I0 (_N97307), .I1 (fifo_full0), .I2 (judge_cnt_h_valid), .I3 (N1016[6]), @@ -317370,7 +316821,7 @@ module zoom_image_v1 GTP_LUT4 /* \zoom_sta_fsm[6:0]_35_2 */ #( .INIT(16'b1110110010100000)) \zoom_sta_fsm[6:0]_35_2 ( - .Z (_N105079), + .Z (_N105626), .I0 (zoom_en), .I1 (zoom_sta_reg[1]), .I2 (zoom_sta_reg[0]), @@ -317385,13 +316836,13 @@ module zoom_image_v1 .I1 (N1016[6]), .I2 (zoom_sta_reg[5]), .I3 (zoom_sta_reg[6]), - .I4 (_N105079)); + .I4 (_N105626)); // LUT = (I4)|(~I0&I1&I2)|(~I0&I1&I3) ; GTP_LUT4 /* \zoom_sta_fsm[6:0]_61 */ #( .INIT(16'b0000001000000000)) \zoom_sta_fsm[6:0]_61 ( - .Z (_N96561), + .Z (_N97307), .I0 (zoom_sta_reg[1]), .I1 (delay_cnt[0]), .I2 (delay_cnt[1]), @@ -317566,12 +317017,11 @@ module char_buf_writer input N11, input clk, input sync_vg_100m, - input udp_rx_s_data_tlast, + input \udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/pkt_rd_done , input udp_rx_s_data_tvalid, output [10:0] ram_addr, output [7:0] ram_din, output ram_wen, - output \udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/pkt_rd_done , output udp_rx_s_data_tready ); wire [31:0] N15; @@ -317579,6 +317029,8 @@ module char_buf_writer wire N16; wire [17:0] \N16.co ; wire N141; + wire N165; + wire [15:0] N169; wire N170; wire N179; wire [7:0] N206; @@ -317590,34 +317042,34 @@ module char_buf_writer wire _N2; wire _N8; wire _N11; - wire _N15270; - wire _N15271; - wire _N15272; - wire _N15273; - wire _N15274; - wire _N15275; - wire _N15276; - wire _N15277; - wire _N15278; - wire _N15279; - wire _N16789; - wire _N16790; - wire _N16791; - wire _N16792; - wire _N16793; - wire _N16794; - wire _N16795; - wire _N16796; - wire _N16797; - wire _N16798; - wire _N16799; - wire _N16800; - wire _N16801; - wire _N16802; + wire _N14920; + wire _N14921; + wire _N14922; + wire _N14923; + wire _N14924; + wire _N14925; + wire _N14926; + wire _N14927; + wire _N14928; + wire _N14929; + wire _N16728; + wire _N16729; + wire _N16730; + wire _N16731; + wire _N16732; + wire _N16733; + wire _N16734; + wire _N16735; + wire _N16736; + wire _N16737; + wire _N16738; + wire _N16739; + wire _N16740; + wire _N16741; wire _N18382; - wire _N26277; - wire _N26278; - wire _N26287; + wire _N26259; + wire _N26260; + wire _N26269; wire _N30558; wire _N30561; wire _N30564; @@ -317628,28 +317080,27 @@ module char_buf_writer wire _N30579; wire _N30582; wire _N30585; - wire _N77912; - wire _N77915; - wire _N77980; - wire _N78023; - wire _N78071; - wire _N78121; - wire _N78167; - wire _N78209; - wire _N78259; - wire _N78299; - wire _N78346; - wire _N78392; - wire _N78439; - wire _N78481; - wire _N78523; - wire _N78572; - wire _N78615; - wire _N103484; - wire _N103516; - wire _N106956; - wire _N106960; - wire _N106962; + wire _N78468; + wire _N78525; + wire _N78526; + wire _N78571; + wire _N78614; + wire _N78656; + wire _N78702; + wire _N78749; + wire _N78797; + wire _N78846; + wire _N78894; + wire _N78939; + wire _N78983; + wire _N79025; + wire _N79074; + wire _N79122; + wire _N104296; + wire _N104328; + wire _N107780; + wire _N107784; + wire _N107786; wire [15:0] cnt; wire [15:0] data_size; wire [2:0] state_reg; @@ -318161,7 +317612,7 @@ module char_buf_writer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_1_1 ( - .COUT (_N16789), + .COUT (_N16728), .Z (N232[1]), .CIN (), .I0 (cnt[0]), @@ -318181,13 +317632,13 @@ module char_buf_writer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_1_2 ( - .COUT (_N16790), - .Z (_N78023), - .CIN (_N16789), + .COUT (_N16729), + .Z (_N78525), + .CIN (_N16728), .I0 (cnt[0]), .I1 (cnt[1]), .I2 (cnt[2]), - .I3 (_N77915), + .I3 (_N78526), .I4 (1'b0), .ID ()); // LUT = (I0&I1&~I2&I3)|(~I1&I2&I3)|(~I0&I2&I3) ; @@ -318201,12 +317652,12 @@ module char_buf_writer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_1_3 ( - .COUT (_N16791), - .Z (_N78071), - .CIN (_N16790), + .COUT (_N16730), + .Z (_N78571), + .CIN (_N16729), .I0 (), .I1 (cnt[3]), - .I2 (_N77915), + .I2 (_N78526), .I3 (), .I4 (1'b0), .ID ()); @@ -318221,12 +317672,12 @@ module char_buf_writer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_1_4 ( - .COUT (_N16792), - .Z (_N78121), - .CIN (_N16791), + .COUT (_N16731), + .Z (_N78614), + .CIN (_N16730), .I0 (), .I1 (cnt[4]), - .I2 (_N77915), + .I2 (_N78526), .I3 (), .I4 (1'b0), .ID ()); @@ -318241,12 +317692,12 @@ module char_buf_writer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_1_5 ( - .COUT (_N16793), - .Z (_N78167), - .CIN (_N16792), + .COUT (_N16732), + .Z (_N78656), + .CIN (_N16731), .I0 (), .I1 (cnt[5]), - .I2 (_N77915), + .I2 (_N78526), .I3 (), .I4 (1'b0), .ID ()); @@ -318261,12 +317712,12 @@ module char_buf_writer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_1_6 ( - .COUT (_N16794), - .Z (_N78209), - .CIN (_N16793), + .COUT (_N16733), + .Z (_N78702), + .CIN (_N16732), .I0 (), .I1 (cnt[6]), - .I2 (_N77915), + .I2 (_N78526), .I3 (), .I4 (1'b0), .ID ()); @@ -318281,12 +317732,12 @@ module char_buf_writer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_1_7 ( - .COUT (_N16795), - .Z (_N78259), - .CIN (_N16794), + .COUT (_N16734), + .Z (_N78749), + .CIN (_N16733), .I0 (), .I1 (cnt[7]), - .I2 (_N77915), + .I2 (_N78526), .I3 (), .I4 (1'b0), .ID ()); @@ -318301,12 +317752,12 @@ module char_buf_writer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_1_8 ( - .COUT (_N16796), - .Z (_N78299), - .CIN (_N16795), + .COUT (_N16735), + .Z (_N78797), + .CIN (_N16734), .I0 (), .I1 (cnt[8]), - .I2 (_N77915), + .I2 (_N78526), .I3 (), .I4 (1'b0), .ID ()); @@ -318321,12 +317772,12 @@ module char_buf_writer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_1_9 ( - .COUT (_N16797), - .Z (_N78346), - .CIN (_N16796), + .COUT (_N16736), + .Z (_N78846), + .CIN (_N16735), .I0 (), .I1 (cnt[9]), - .I2 (_N77915), + .I2 (_N78526), .I3 (), .I4 (1'b0), .ID ()); @@ -318341,12 +317792,12 @@ module char_buf_writer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_1_10 ( - .COUT (_N16798), - .Z (_N78392), - .CIN (_N16797), + .COUT (_N16737), + .Z (_N78894), + .CIN (_N16736), .I0 (), .I1 (cnt[10]), - .I2 (_N77915), + .I2 (_N78526), .I3 (), .I4 (1'b0), .ID ()); @@ -318361,12 +317812,12 @@ module char_buf_writer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_1_11 ( - .COUT (_N16799), - .Z (_N78439), - .CIN (_N16798), + .COUT (_N16738), + .Z (_N78939), + .CIN (_N16737), .I0 (), .I1 (cnt[11]), - .I2 (_N77915), + .I2 (_N78526), .I3 (), .I4 (1'b0), .ID ()); @@ -318381,12 +317832,12 @@ module char_buf_writer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_1_12 ( - .COUT (_N16800), - .Z (_N78481), - .CIN (_N16799), + .COUT (_N16739), + .Z (_N78983), + .CIN (_N16738), .I0 (), .I1 (cnt[12]), - .I2 (_N77915), + .I2 (_N78526), .I3 (), .I4 (1'b0), .ID ()); @@ -318401,12 +317852,12 @@ module char_buf_writer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_1_13 ( - .COUT (_N16801), - .Z (_N78523), - .CIN (_N16800), + .COUT (_N16740), + .Z (_N79025), + .CIN (_N16739), .I0 (), .I1 (cnt[13]), - .I2 (_N77915), + .I2 (_N78526), .I3 (), .I4 (1'b0), .ID ()); @@ -318421,12 +317872,12 @@ module char_buf_writer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_1_14 ( - .COUT (_N16802), - .Z (_N78572), - .CIN (_N16801), + .COUT (_N16741), + .Z (_N79074), + .CIN (_N16740), .I0 (), .I1 (cnt[14]), - .I2 (_N77915), + .I2 (_N78526), .I3 (), .I4 (1'b0), .ID ()); @@ -318442,11 +317893,11 @@ module char_buf_writer .I4_TO_LUT("FALSE")) N27_1_15 ( .COUT (), - .Z (_N78615), - .CIN (_N16802), + .Z (_N79122), + .CIN (_N16741), .I0 (), .I1 (cnt[15]), - .I2 (_N77915), + .I2 (_N78526), .I3 (), .I4 (1'b0), .ID ()); @@ -318461,7 +317912,7 @@ module char_buf_writer .I4_TO_CARRY("FALSE"), .I4_TO_LUT("FALSE")) N87_1_0 ( - .COUT (_N15270), + .COUT (_N14920), .Z (), .CIN (), .I0 (), @@ -318481,9 +317932,9 @@ module char_buf_writer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N87_1_1 ( - .COUT (_N15271), + .COUT (_N14921), .Z (_N30558), - .CIN (_N15270), + .CIN (_N14920), .I0 (), .I1 (ram_addr[1]), .I2 (ram_wen), @@ -318501,9 +317952,9 @@ module char_buf_writer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N87_1_2 ( - .COUT (_N15272), + .COUT (_N14922), .Z (_N30561), - .CIN (_N15271), + .CIN (_N14921), .I0 (), .I1 (ram_addr[2]), .I2 (ram_wen), @@ -318521,9 +317972,9 @@ module char_buf_writer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N87_1_3 ( - .COUT (_N15273), + .COUT (_N14923), .Z (_N30564), - .CIN (_N15272), + .CIN (_N14922), .I0 (), .I1 (ram_addr[3]), .I2 (ram_wen), @@ -318541,9 +317992,9 @@ module char_buf_writer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N87_1_4 ( - .COUT (_N15274), + .COUT (_N14924), .Z (_N30567), - .CIN (_N15273), + .CIN (_N14923), .I0 (), .I1 (ram_addr[4]), .I2 (ram_wen), @@ -318561,9 +318012,9 @@ module char_buf_writer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N87_1_5 ( - .COUT (_N15275), + .COUT (_N14925), .Z (_N30570), - .CIN (_N15274), + .CIN (_N14924), .I0 (), .I1 (ram_addr[5]), .I2 (ram_wen), @@ -318581,9 +318032,9 @@ module char_buf_writer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N87_1_6 ( - .COUT (_N15276), + .COUT (_N14926), .Z (_N30573), - .CIN (_N15275), + .CIN (_N14925), .I0 (), .I1 (ram_addr[6]), .I2 (ram_wen), @@ -318601,9 +318052,9 @@ module char_buf_writer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N87_1_7 ( - .COUT (_N15277), + .COUT (_N14927), .Z (_N30576), - .CIN (_N15276), + .CIN (_N14926), .I0 (), .I1 (ram_addr[7]), .I2 (ram_wen), @@ -318621,9 +318072,9 @@ module char_buf_writer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N87_1_8 ( - .COUT (_N15278), + .COUT (_N14928), .Z (_N30579), - .CIN (_N15277), + .CIN (_N14927), .I0 (), .I1 (ram_addr[8]), .I2 (ram_wen), @@ -318641,9 +318092,9 @@ module char_buf_writer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N87_1_9 ( - .COUT (_N15279), + .COUT (_N14929), .Z (_N30582), - .CIN (_N15278), + .CIN (_N14928), .I0 (), .I1 (ram_addr[9]), .I2 (ram_wen), @@ -318663,7 +318114,7 @@ module char_buf_writer N87_1_10 ( .COUT (), .Z (_N30585), - .CIN (_N15279), + .CIN (_N14929), .I0 (), .I1 (ram_addr[10]), .I2 (ram_wen), @@ -318679,16 +318130,16 @@ module char_buf_writer N138 ( .Z (N238[2]), .I0 (cnt[0]), - .I1 (_N106956), - .I2 (_N106960), - .I3 (_N106962)); + .I1 (_N107780), + .I2 (_N107784), + .I3 (_N107786)); // LUT = I0&I1&I2&I3 ; // ../../sources/designs/udp_osd/char_osd/char_buf_writer.v:69 GTP_LUT5 /* N138_20 */ #( .INIT(32'b00000000000000000000000000000001)) N138_20 ( - .Z (_N106956), + .Z (_N107780), .I0 (cnt[4]), .I1 (cnt[5]), .I2 (cnt[6]), @@ -318699,7 +318150,7 @@ module char_buf_writer GTP_LUT5 /* N138_24 */ #( .INIT(32'b00000000000000000000000000000001)) N138_24 ( - .Z (_N106960), + .Z (_N107784), .I0 (cnt[9]), .I1 (cnt[10]), .I2 (cnt[11]), @@ -318710,7 +318161,7 @@ module char_buf_writer GTP_LUT5 /* N138_26 */ #( .INIT(32'b00000000000000000000000000000001)) N138_26 ( - .Z (_N106962), + .Z (_N107786), .I0 (cnt[1]), .I1 (cnt[2]), .I2 (cnt[3]), @@ -318723,13 +318174,35 @@ module char_buf_writer N141_vname ( .Z (N141), .I0 (cnt[0]), - .I1 (_N106956), - .I2 (_N106960), - .I3 (_N106962)); + .I1 (_N107780), + .I2 (_N107784), + .I3 (_N107786)); // defparam N141_vname.orig_name = N141; // LUT = ~I0&I1&I2&I3 ; // ../../sources/designs/udp_osd/char_osd/char_buf_writer.v:94 + GTP_LUT3 /* N165 */ #( + .INIT(8'b10000000)) + N165_vname ( + .Z (N165), + .I0 (udp_rx_s_data_tready), + .I1 (udp_rx_s_data_tvalid), + .I2 (state_reg[1])); + // defparam N165_vname.orig_name = N165; + // LUT = I0&I1&I2 ; + // ../../sources/designs/udp_osd/char_osd/char_buf_writer.v:41 + + GTP_LUT5 /* \N169_4_or[1]_1 */ #( + .INIT(32'b01000100000000001111010000000000)) + \N169_4_or[1]_1 ( + .Z (N169[1]), + .I0 (N16), + .I1 (N165), + .I2 (state_reg[2]), + .I3 (N232[1]), + .I4 (N238[2])); + // LUT = (I2&I3&~I4)|(~I0&I1&I3) ; + GTP_LUT3 /* N170 */ #( .INIT(8'b10001111)) N170_vname ( @@ -318749,15 +318222,6 @@ module char_buf_writer .I2 (state_reg[0])); // LUT = ~I0&I1&I2 ; - GTP_LUT3 /* N189_1 */ #( - .INIT(8'b10000000)) - N189_1 ( - .Z (\udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/pkt_rd_done ), - .I0 (udp_rx_s_data_tlast), - .I1 (udp_rx_s_data_tready), - .I2 (udp_rx_s_data_tvalid)); - // LUT = I0&I1&I2 ; - GTP_LUT2 /* N206_1 */ #( .INIT(4'b1000)) N206_1 ( @@ -318779,7 +318243,7 @@ module char_buf_writer GTP_LUT5M /* N206_14_4 */ #( .INIT(32'b00000001000001010010001010101010)) N206_14_4 ( - .Z (_N26277), + .Z (_N26259), .I0 (N238[2]), .I1 (state_reg[1]), .I2 (N141), @@ -318791,9 +318255,9 @@ module char_buf_writer GTP_LUT5 /* N206_15 */ #( .INIT(32'b11001100110011001100111011101110)) N206_15 ( - .Z (_N26278), + .Z (_N26260), .I0 (_N18382), - .I1 (_N26277), + .I1 (_N26259), .I2 (N11), .I3 (state_reg[1]), .I4 (state_reg[0])); @@ -318802,8 +318266,8 @@ module char_buf_writer GTP_LUT5 /* N206_24 */ #( .INIT(32'b10101010101010101011101011111010)) N206_24 ( - .Z (_N26287), - .I0 (_N26277), + .Z (_N26269), + .I0 (_N26259), .I1 (N11), .I2 (_N1), .I3 (state_reg[1]), @@ -318814,8 +318278,8 @@ module char_buf_writer .INIT(32'b01110110001100100101010000010000)) \N206_27[0] ( .Z (N206[0]), - .I0 (_N26278), - .I1 (_N26287), + .I0 (_N26260), + .I1 (_N26269), .I2 (udp_rx_s_data_tdata[0]), .I3 (data_size[0]), .I4 (data_size[8])); @@ -318825,8 +318289,8 @@ module char_buf_writer .INIT(32'b01110110001100100101010000010000)) \N206_27[1] ( .Z (N206[1]), - .I0 (_N26278), - .I1 (_N26287), + .I0 (_N26260), + .I1 (_N26269), .I2 (udp_rx_s_data_tdata[1]), .I3 (data_size[1]), .I4 (data_size[9])); @@ -318836,8 +318300,8 @@ module char_buf_writer .INIT(32'b01110110001100100101010000010000)) \N206_27[2] ( .Z (N206[2]), - .I0 (_N26278), - .I1 (_N26287), + .I0 (_N26260), + .I1 (_N26269), .I2 (udp_rx_s_data_tdata[2]), .I3 (data_size[2]), .I4 (data_size[10])); @@ -318847,8 +318311,8 @@ module char_buf_writer .INIT(32'b01110110001100100101010000010000)) \N206_27[3] ( .Z (N206[3]), - .I0 (_N26278), - .I1 (_N26287), + .I0 (_N26260), + .I1 (_N26269), .I2 (udp_rx_s_data_tdata[3]), .I3 (data_size[3]), .I4 (data_size[11])); @@ -318858,8 +318322,8 @@ module char_buf_writer .INIT(32'b01110110001100100101010000010000)) \N206_27[4] ( .Z (N206[4]), - .I0 (_N26278), - .I1 (_N26287), + .I0 (_N26260), + .I1 (_N26269), .I2 (udp_rx_s_data_tdata[4]), .I3 (data_size[4]), .I4 (data_size[12])); @@ -318869,8 +318333,8 @@ module char_buf_writer .INIT(32'b01110110001100100101010000010000)) \N206_27[5] ( .Z (N206[5]), - .I0 (_N26278), - .I1 (_N26287), + .I0 (_N26260), + .I1 (_N26269), .I2 (udp_rx_s_data_tdata[5]), .I3 (data_size[5]), .I4 (data_size[13])); @@ -318880,8 +318344,8 @@ module char_buf_writer .INIT(32'b01110110001100100101010000010000)) \N206_27[6] ( .Z (N206[6]), - .I0 (_N26278), - .I1 (_N26287), + .I0 (_N26260), + .I1 (_N26269), .I2 (udp_rx_s_data_tdata[6]), .I3 (data_size[6]), .I4 (data_size[14])); @@ -318891,8 +318355,8 @@ module char_buf_writer .INIT(32'b01110110001100100101010000010000)) \N206_27[7] ( .Z (N206[7]), - .I0 (_N26278), - .I1 (_N26287), + .I0 (_N26260), + .I1 (_N26269), .I2 (udp_rx_s_data_tdata[7]), .I3 (data_size[7]), .I4 (data_size[15])); @@ -319014,7 +318478,7 @@ module char_buf_writer .Q (cnt[0]), .CE (N170), .CLK (clk), - .D (_N77912), + .D (_N78468), .R (sync_vg_100m)); // ../../sources/designs/udp_osd/char_osd/char_buf_writer.v:36 @@ -319025,7 +318489,7 @@ module char_buf_writer .Q (cnt[1]), .CE (N170), .CLK (clk), - .D (_N77980), + .D (N169[1]), .R (sync_vg_100m)); // ../../sources/designs/udp_osd/char_osd/char_buf_writer.v:36 @@ -319036,7 +318500,7 @@ module char_buf_writer .Q (cnt[2]), .CE (N170), .CLK (clk), - .D (_N78023), + .D (_N78525), .R (sync_vg_100m)); // ../../sources/designs/udp_osd/char_osd/char_buf_writer.v:36 @@ -319047,7 +318511,7 @@ module char_buf_writer .Q (cnt[3]), .CE (N170), .CLK (clk), - .D (_N78071), + .D (_N78571), .R (sync_vg_100m)); // ../../sources/designs/udp_osd/char_osd/char_buf_writer.v:36 @@ -319058,7 +318522,7 @@ module char_buf_writer .Q (cnt[4]), .CE (N170), .CLK (clk), - .D (_N78121), + .D (_N78614), .R (sync_vg_100m)); // ../../sources/designs/udp_osd/char_osd/char_buf_writer.v:36 @@ -319069,7 +318533,7 @@ module char_buf_writer .Q (cnt[5]), .CE (N170), .CLK (clk), - .D (_N78167), + .D (_N78656), .R (sync_vg_100m)); // ../../sources/designs/udp_osd/char_osd/char_buf_writer.v:36 @@ -319080,7 +318544,7 @@ module char_buf_writer .Q (cnt[6]), .CE (N170), .CLK (clk), - .D (_N78209), + .D (_N78702), .R (sync_vg_100m)); // ../../sources/designs/udp_osd/char_osd/char_buf_writer.v:36 @@ -319091,7 +318555,7 @@ module char_buf_writer .Q (cnt[7]), .CE (N170), .CLK (clk), - .D (_N78259), + .D (_N78749), .R (sync_vg_100m)); // ../../sources/designs/udp_osd/char_osd/char_buf_writer.v:36 @@ -319102,7 +318566,7 @@ module char_buf_writer .Q (cnt[8]), .CE (N170), .CLK (clk), - .D (_N78299), + .D (_N78797), .R (sync_vg_100m)); // ../../sources/designs/udp_osd/char_osd/char_buf_writer.v:36 @@ -319113,7 +318577,7 @@ module char_buf_writer .Q (cnt[9]), .CE (N170), .CLK (clk), - .D (_N78346), + .D (_N78846), .R (sync_vg_100m)); // ../../sources/designs/udp_osd/char_osd/char_buf_writer.v:36 @@ -319124,7 +318588,7 @@ module char_buf_writer .Q (cnt[10]), .CE (N170), .CLK (clk), - .D (_N78392), + .D (_N78894), .R (sync_vg_100m)); // ../../sources/designs/udp_osd/char_osd/char_buf_writer.v:36 @@ -319135,7 +318599,7 @@ module char_buf_writer .Q (cnt[11]), .CE (N170), .CLK (clk), - .D (_N78439), + .D (_N78939), .R (sync_vg_100m)); // ../../sources/designs/udp_osd/char_osd/char_buf_writer.v:36 @@ -319146,7 +318610,7 @@ module char_buf_writer .Q (cnt[12]), .CE (N170), .CLK (clk), - .D (_N78481), + .D (_N78983), .R (sync_vg_100m)); // ../../sources/designs/udp_osd/char_osd/char_buf_writer.v:36 @@ -319157,7 +318621,7 @@ module char_buf_writer .Q (cnt[13]), .CE (N170), .CLK (clk), - .D (_N78523), + .D (_N79025), .R (sync_vg_100m)); // ../../sources/designs/udp_osd/char_osd/char_buf_writer.v:36 @@ -319168,40 +318632,29 @@ module char_buf_writer .Q (cnt[14]), .CE (N170), .CLK (clk), - .D (_N78572), + .D (_N79074), .R (sync_vg_100m)); // ../../sources/designs/udp_osd/char_osd/char_buf_writer.v:36 - GTP_LUT3 /* \cnt[15:0]_6 */ #( + GTP_LUT3 /* \cnt[15:0]_4 */ #( .INIT(8'b11011100)) - \cnt[15:0]_6 ( - .Z (_N77915), + \cnt[15:0]_4 ( + .Z (_N78526), .I0 (N16), .I1 (state_reg[2]), .I2 (state_reg[1])); // LUT = (I1)|(~I0&I2) ; - GTP_LUT4 /* \cnt[15:0]_5426 */ #( + GTP_LUT4 /* \cnt[15:0]_5374 */ #( .INIT(16'b0000000011011100)) - \cnt[15:0]_5426 ( - .Z (_N77912), + \cnt[15:0]_5374 ( + .Z (_N78468), .I0 (N16), .I1 (state_reg[2]), .I2 (state_reg[1]), .I3 (cnt[0])); // LUT = (I1&~I3)|(~I0&I2&~I3) ; - GTP_LUT5 /* \cnt[15:0]_5444 */ #( - .INIT(32'b01010000000000001101110000000000)) - \cnt[15:0]_5444 ( - .Z (_N77980), - .I0 (N16), - .I1 (state_reg[2]), - .I2 (state_reg[1]), - .I3 (N232[1]), - .I4 (N238[2])); - // LUT = (I1&I3&~I4)|(~I0&I2&I3) ; - GTP_DFF_RE /* \cnt[15] */ #( .GRS_EN("TRUE"), .INIT(1'b0)) @@ -319209,7 +318662,7 @@ module char_buf_writer .Q (cnt[15]), .CE (N170), .CLK (clk), - .D (_N78615), + .D (_N79122), .R (sync_vg_100m)); // ../../sources/designs/udp_osd/char_osd/char_buf_writer.v:36 @@ -319588,14 +319041,14 @@ module char_buf_writer ram_wen_vname ( .Q (ram_wen), .CLK (clk), - .D (_N103484)); + .D (_N104296)); // defparam ram_wen_vname.orig_name = ram_wen; // ../../sources/designs/udp_osd/char_osd/char_buf_writer.v:109 GTP_LUT5M /* ram_wen_rs_mux */ #( .INIT(32'b00000010000000100000001100000010)) ram_wen_rs_mux ( - .Z (_N103484), + .Z (_N104296), .I0 (N11), .I1 (sync_vg_100m), .I2 (state_reg[0]), @@ -319673,14 +319126,14 @@ module char_buf_writer udp_rx_s_data_tready_vname ( .Q (udp_rx_s_data_tready), .CLK (clk), - .D (_N103516)); + .D (_N104328)); // defparam udp_rx_s_data_tready_vname.orig_name = udp_rx_s_data_tready; // ../../sources/designs/udp_osd/char_osd/char_buf_writer.v:88 GTP_LUT5 /* udp_rx_s_data_tready_rs_mux */ #( .INIT(32'b01010000000000000101010000000000)) udp_rx_s_data_tready_rs_mux ( - .Z (_N103516), + .Z (_N104328), .I0 (sync_vg_100m), .I1 (udp_rx_s_data_tready), .I2 (N141), @@ -319710,8 +319163,8 @@ module char_buf_reader output [5:0] char_row_index, output [10:0] ram_addr, output [4:0] state_reg, - output N97, - output _N107128, + output N73, + output _N97124, output char_valid, output \udp_osd_inst/char_osd_inst/char_ascii[0]_inv ); @@ -319720,13 +319173,12 @@ module char_buf_reader wire [16:0] \N60.co ; wire [31:0] N72; wire [16:0] \N72_1.co ; - wire N73; wire [17:0] \N73.co ; + wire N74; wire N79; - wire N79_cpy; + wire N100; wire N245; wire [17:0] \N245.co ; - wire N379; wire [5:0] N391; wire N478; wire [10:0] N483; @@ -319739,7 +319191,7 @@ module char_buf_reader wire [5:0] N785; wire N786; wire N832; - wire N839; + wire N842; wire N843; wire [10:0] N847; wire N848; @@ -319751,72 +319203,75 @@ module char_buf_reader wire [5:0] N898; wire [10:0] N900; wire [5:0] N902; + wire \N907[6]_cpy ; wire _N0; wire _N2; wire _N3; + wire _N7; wire _N12; wire _N15; wire _N16; wire _N22; wire _N31; - wire _N13697; - wire _N13698; - wire _N13699; - wire _N13700; - wire _N13701; - wire _N13702; - wire _N13703; - wire _N13704; - wire _N13705; - wire _N14090; - wire _N14091; - wire _N14092; - wire _N14093; - wire _N14094; - wire _N14095; - wire _N14096; - wire _N14097; - wire _N14098; - wire _N14099; - wire _N14561; - wire _N14562; - wire _N14563; - wire _N14564; - wire _N14565; - wire _N14566; - wire _N14567; - wire _N14568; - wire _N14569; - wire _N14570; + wire _N15044; + wire _N15045; + wire _N15046; + wire _N15047; + wire _N15048; + wire _N15049; + wire _N15050; + wire _N15051; + wire _N15052; + wire _N15053; + wire _N15056; + wire _N15057; + wire _N15058; + wire _N15059; + wire _N15060; wire _N15061; wire _N15062; wire _N15063; wire _N15064; + wire _N15065; + wire _N15474; + wire _N15475; + wire _N15476; + wire _N15477; + wire _N15478; + wire _N15479; + wire _N15480; + wire _N15481; + wire _N15482; + wire _N16195; + wire _N16196; + wire _N16197; + wire _N16198; wire _N18389; + wire _N18392; + wire _N18403; wire _N18404; wire _N18405; - wire _N30325; - wire _N30374; - wire _N81460; - wire _N82884; - wire _N82900; - wire _N96372; - wire _N96517; - wire _N96518; - wire _N96555; - wire _N96929; - wire _N97090; - wire _N97174; - wire _N103526; - wire _N106978; - wire _N106993; - wire _N106995; - wire _N106996; - wire _N107004; - wire _N107006; - wire _N107017; - wire _N108032; - wire _N108385; + wire _N30062; + wire _N30111; + wire _N84128; + wire _N84135; + wire _N96870; + wire _N97126; + wire _N97129; + wire _N97275; + wire _N97697; + wire _N97897; + wire _N97976; + wire _N99326; + wire _N101750; + wire _N104338; + wire _N107806; + wire _N107821; + wire _N107823; + wire _N107826; + wire _N108858; + wire _N108866; + wire _N109249; wire [10:0] char_height; wire [10:0] char_width; wire [5:0] cnt; @@ -319829,7 +319284,7 @@ module char_buf_reader .INIT(32'b00000000000000000000000000001000)) N15_vname ( .Z (N15), - .I0 (_N96372), + .I0 (_N97129), .I1 (state_reg[0]), .I2 (cnt[0]), .I3 (cnt[1]), @@ -319845,7 +319300,7 @@ module char_buf_reader .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N55_1_1 ( - .COUT (_N15061), + .COUT (_N16195), .Z (N902[1]), .CIN (), .I0 (cnt[0]), @@ -319865,9 +319320,9 @@ module char_buf_reader .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N55_1_2 ( - .COUT (_N15062), + .COUT (_N16196), .Z (N902[2]), - .CIN (_N15061), + .CIN (_N16195), .I0 (cnt[0]), .I1 (cnt[1]), .I2 (cnt[2]), @@ -319885,12 +319340,12 @@ module char_buf_reader .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N55_1_3 ( - .COUT (_N15063), + .COUT (_N16197), .Z (N785[3]), - .CIN (_N15062), + .CIN (_N16196), .I0 (), .I1 (cnt[3]), - .I2 (_N82900), + .I2 (_N84135), .I3 (), .I4 (1'b0), .ID ()); @@ -319905,12 +319360,12 @@ module char_buf_reader .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N55_1_4 ( - .COUT (_N15064), + .COUT (_N16198), .Z (N785[4]), - .CIN (_N15063), + .CIN (_N16197), .I0 (), .I1 (cnt[4]), - .I2 (_N82900), + .I2 (_N84135), .I3 (), .I4 (1'b0), .ID ()); @@ -319927,10 +319382,10 @@ module char_buf_reader N55_1_5 ( .COUT (), .Z (N785[5]), - .CIN (_N15064), + .CIN (_N16198), .I0 (), .I1 (cnt[5]), - .I2 (_N82900), + .I2 (_N84135), .I3 (), .I4 (1'b0), .ID ()); @@ -320558,6 +320013,16 @@ module char_buf_reader // CARRY = (1'b0) ? CIN : (I4) ; // ../../sources/designs/udp_osd/char_osd/char_buf_reader.v:134 + GTP_LUT2 /* N74 */ #( + .INIT(4'b1000)) + N74_vname ( + .Z (N74), + .I0 (char_next), + .I1 (N73)); + // defparam N74_vname.orig_name = N74; + // LUT = I0&I1 ; + // ../../sources/designs/udp_osd/char_osd/char_buf_reader.v:134 + GTP_LUT3 /* N79 */ #( .INIT(8'b10000000)) N79_vname ( @@ -320569,25 +320034,16 @@ module char_buf_reader // LUT = I0&I1&I2 ; // ../../sources/designs/udp_osd/char_osd/char_buf_reader.v:134 - GTP_LUT3 /* N79_cpy */ #( - .INIT(8'b10000000)) - N79_cpy_vname ( - .Z (N79_cpy), - .I0 (char_next), - .I1 (N73), - .I2 (N907[7])); - // defparam N79_cpy_vname.orig_name = N79_cpy; - // LUT = I0&I1&I2 ; - // ../../sources/designs/udp_osd/char_osd/char_buf_reader.v:134 - - GTP_LUT2 /* N97 */ #( - .INIT(4'b1000)) - N97_vname ( - .Z (N97), - .I0 (char_next), - .I1 (char_valid)); - // defparam N97_vname.orig_name = N97; - // LUT = I0&I1 ; + GTP_LUT4 /* N100 */ #( + .INIT(16'b1111100010001000)) + N100_vname ( + .Z (N100), + .I0 (_N97976), + .I1 (ram_data[5]), + .I2 (char_next), + .I3 (char_valid)); + // defparam N100_vname.orig_name = N100; + // LUT = (I0&I1)|(I2&I3) ; // ../../sources/designs/udp_osd/char_osd/char_buf_reader.v:146 GTP_LUT5CARRY /* N228_1_1 */ #( @@ -320597,7 +320053,7 @@ module char_buf_reader .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N228_1_1 ( - .COUT (_N13697), + .COUT (_N15474), .Z (N900[1]), .CIN (), .I0 (ram_addr[0]), @@ -320617,9 +320073,9 @@ module char_buf_reader .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N228_1_2 ( - .COUT (_N13698), + .COUT (_N15475), .Z (N900[2]), - .CIN (_N13697), + .CIN (_N15474), .I0 (ram_addr[0]), .I1 (ram_addr[1]), .I2 (ram_addr[2]), @@ -320637,9 +320093,9 @@ module char_buf_reader .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N228_1_3 ( - .COUT (_N13699), + .COUT (_N15476), .Z (N900[3]), - .CIN (_N13698), + .CIN (_N15475), .I0 (), .I1 (ram_addr[3]), .I2 (), @@ -320657,9 +320113,9 @@ module char_buf_reader .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N228_1_4 ( - .COUT (_N13700), + .COUT (_N15477), .Z (N900[4]), - .CIN (_N13699), + .CIN (_N15476), .I0 (), .I1 (ram_addr[4]), .I2 (), @@ -320677,9 +320133,9 @@ module char_buf_reader .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N228_1_5 ( - .COUT (_N13701), + .COUT (_N15478), .Z (N900[5]), - .CIN (_N13700), + .CIN (_N15477), .I0 (), .I1 (ram_addr[5]), .I2 (), @@ -320697,9 +320153,9 @@ module char_buf_reader .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N228_1_6 ( - .COUT (_N13702), + .COUT (_N15479), .Z (N900[6]), - .CIN (_N13701), + .CIN (_N15478), .I0 (), .I1 (ram_addr[6]), .I2 (), @@ -320717,9 +320173,9 @@ module char_buf_reader .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N228_1_7 ( - .COUT (_N13703), + .COUT (_N15480), .Z (N900[7]), - .CIN (_N13702), + .CIN (_N15479), .I0 (), .I1 (ram_addr[7]), .I2 (), @@ -320737,9 +320193,9 @@ module char_buf_reader .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N228_1_8 ( - .COUT (_N13704), + .COUT (_N15481), .Z (N900[8]), - .CIN (_N13703), + .CIN (_N15480), .I0 (), .I1 (ram_addr[8]), .I2 (), @@ -320757,9 +320213,9 @@ module char_buf_reader .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N228_1_9 ( - .COUT (_N13705), + .COUT (_N15482), .Z (N900[9]), - .CIN (_N13704), + .CIN (_N15481), .I0 (), .I1 (ram_addr[9]), .I2 (), @@ -320779,7 +320235,7 @@ module char_buf_reader N228_1_10 ( .COUT (), .Z (N900[10]), - .CIN (_N13705), + .CIN (_N15482), .I0 (), .I1 (ram_addr[10]), .I2 (), @@ -320950,27 +320406,14 @@ module char_buf_reader // CARRY = (1'b0) ? CIN : (I4) ; // ../../sources/designs/udp_osd/char_osd/char_buf_reader.v:248 - GTP_LUT5 /* N358_5 */ #( - .INIT(32'b00000000000000000000000000100000)) + GTP_LUT3 /* N358_5 */ #( + .INIT(8'b00001000)) N358_5 ( - .Z (_N96518), - .I0 (N60), - .I1 (N79), - .I2 (state_reg[1]), - .I3 (N907[2]), - .I4 (N907[6])); - // LUT = I0&~I1&I2&~I3&~I4 ; - - GTP_LUT3 /* N379 */ #( - .INIT(8'b10000000)) - N379_vname ( - .Z (N379), + .Z (_N97124), .I0 (char_next), .I1 (char_valid), - .I2 (N73)); - // defparam N379_vname.orig_name = N379; - // LUT = I0&I1&I2 ; - // ../../sources/designs/udp_osd/char_osd/char_buf_reader.v:333 + .I2 (N478)); + // LUT = I0&I1&~I2 ; GTP_LUT3 /* N390_sum2 */ #( .INIT(8'b01111000)) @@ -321015,14 +320458,27 @@ module char_buf_reader // LUT = (~I0&I4)|(I1&~I3&I4)|(~I2&I3&I4)|(~I1&I2&I4)|(I0&I1&I2&I3&~I4) ; // ../../sources/designs/udp_osd/char_osd/char_buf_reader.v:336 - GTP_LUT2 /* N478 */ #( - .INIT(4'b1110)) + GTP_LUT4 /* N464_2 */ #( + .INIT(16'b0000011100000000)) + N464_2 ( + .Z (_N101750), + .I0 (_N97976), + .I1 (ram_data[5]), + .I2 (N478), + .I3 (state_reg[1])); + // LUT = (~I1&~I2&I3)|(~I0&~I2&I3) ; + + GTP_LUT5 /* N478 */ #( + .INIT(32'b11111111111111110000010000000000)) N478_vname ( .Z (N478), - .I0 (N907[2]), - .I1 (N907[6])); + .I0 (ram_data[1]), + .I1 (ram_data[3]), + .I2 (ram_data[5]), + .I3 (_N107806), + .I4 (N907[6])); // defparam N478_vname.orig_name = N478; - // LUT = (I0)|(I1) ; + // LUT = (I4)|(~I0&I1&~I2&I3) ; // ../../sources/designs/udp_osd/char_osd/char_buf_reader.v:389 GTP_LUT5CARRY /* N483_1 */ #( @@ -321032,7 +320488,7 @@ module char_buf_reader .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N483_1 ( - .COUT (_N14090), + .COUT (_N15044), .Z (N483[0]), .CIN (), .I0 (char_width[0]), @@ -321052,9 +320508,9 @@ module char_buf_reader .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N483_2 ( - .COUT (_N14091), + .COUT (_N15045), .Z (N483[1]), - .CIN (_N14090), + .CIN (_N15044), .I0 (char_width[0]), .I1 (char_pos_x[0]), .I2 (char_width[1]), @@ -321072,9 +320528,9 @@ module char_buf_reader .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N483_3 ( - .COUT (_N14092), + .COUT (_N15046), .Z (N483[2]), - .CIN (_N14091), + .CIN (_N15045), .I0 (), .I1 (char_width[2]), .I2 (char_pos_x[2]), @@ -321092,9 +320548,9 @@ module char_buf_reader .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N483_4 ( - .COUT (_N14093), + .COUT (_N15047), .Z (N483[3]), - .CIN (_N14092), + .CIN (_N15046), .I0 (), .I1 (char_width[3]), .I2 (char_pos_x[3]), @@ -321112,9 +320568,9 @@ module char_buf_reader .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N483_5 ( - .COUT (_N14094), + .COUT (_N15048), .Z (N483[4]), - .CIN (_N14093), + .CIN (_N15047), .I0 (), .I1 (char_width[4]), .I2 (char_pos_x[4]), @@ -321132,9 +320588,9 @@ module char_buf_reader .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N483_6 ( - .COUT (_N14095), + .COUT (_N15049), .Z (N483[5]), - .CIN (_N14094), + .CIN (_N15048), .I0 (), .I1 (char_width[5]), .I2 (char_pos_x[5]), @@ -321152,9 +320608,9 @@ module char_buf_reader .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N483_7 ( - .COUT (_N14096), + .COUT (_N15050), .Z (N483[6]), - .CIN (_N14095), + .CIN (_N15049), .I0 (), .I1 (char_width[6]), .I2 (char_pos_x[6]), @@ -321172,9 +320628,9 @@ module char_buf_reader .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N483_8 ( - .COUT (_N14097), + .COUT (_N15051), .Z (N483[7]), - .CIN (_N14096), + .CIN (_N15050), .I0 (), .I1 (char_width[7]), .I2 (char_pos_x[7]), @@ -321192,9 +320648,9 @@ module char_buf_reader .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N483_9 ( - .COUT (_N14098), + .COUT (_N15052), .Z (N483[8]), - .CIN (_N14097), + .CIN (_N15051), .I0 (), .I1 (char_width[8]), .I2 (char_pos_x[8]), @@ -321212,9 +320668,9 @@ module char_buf_reader .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N483_10 ( - .COUT (_N14099), + .COUT (_N15053), .Z (N483[9]), - .CIN (_N14098), + .CIN (_N15052), .I0 (), .I1 (char_width[9]), .I2 (char_pos_x[9]), @@ -321234,7 +320690,7 @@ module char_buf_reader N483_11 ( .COUT (), .Z (N483[10]), - .CIN (_N14099), + .CIN (_N15053), .I0 (), .I1 (char_width[10]), .I2 (char_pos_x[10]), @@ -321252,7 +320708,7 @@ module char_buf_reader .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N522_1 ( - .COUT (_N14561), + .COUT (_N15056), .Z (N522[0]), .CIN (), .I0 (char_height[0]), @@ -321272,9 +320728,9 @@ module char_buf_reader .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N522_2 ( - .COUT (_N14562), + .COUT (_N15057), .Z (N522[1]), - .CIN (_N14561), + .CIN (_N15056), .I0 (char_height[0]), .I1 (char_pos_y[0]), .I2 (char_height[1]), @@ -321292,9 +320748,9 @@ module char_buf_reader .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N522_3 ( - .COUT (_N14563), + .COUT (_N15058), .Z (N522[2]), - .CIN (_N14562), + .CIN (_N15057), .I0 (), .I1 (char_height[2]), .I2 (char_pos_y[2]), @@ -321312,9 +320768,9 @@ module char_buf_reader .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N522_4 ( - .COUT (_N14564), + .COUT (_N15059), .Z (N522[3]), - .CIN (_N14563), + .CIN (_N15058), .I0 (), .I1 (char_height[3]), .I2 (char_pos_y[3]), @@ -321332,9 +320788,9 @@ module char_buf_reader .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N522_5 ( - .COUT (_N14565), + .COUT (_N15060), .Z (N522[4]), - .CIN (_N14564), + .CIN (_N15059), .I0 (), .I1 (char_height[4]), .I2 (char_pos_y[4]), @@ -321352,9 +320808,9 @@ module char_buf_reader .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N522_6 ( - .COUT (_N14566), + .COUT (_N15061), .Z (N522[5]), - .CIN (_N14565), + .CIN (_N15060), .I0 (), .I1 (char_height[5]), .I2 (char_pos_y[5]), @@ -321372,9 +320828,9 @@ module char_buf_reader .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N522_7 ( - .COUT (_N14567), + .COUT (_N15062), .Z (N522[6]), - .CIN (_N14566), + .CIN (_N15061), .I0 (), .I1 (char_height[6]), .I2 (char_pos_y[6]), @@ -321392,9 +320848,9 @@ module char_buf_reader .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N522_8 ( - .COUT (_N14568), + .COUT (_N15063), .Z (N522[7]), - .CIN (_N14567), + .CIN (_N15062), .I0 (), .I1 (char_height[7]), .I2 (char_pos_y[7]), @@ -321412,9 +320868,9 @@ module char_buf_reader .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N522_9 ( - .COUT (_N14569), + .COUT (_N15064), .Z (N522[8]), - .CIN (_N14568), + .CIN (_N15063), .I0 (), .I1 (char_height[8]), .I2 (char_pos_y[8]), @@ -321432,9 +320888,9 @@ module char_buf_reader .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N522_10 ( - .COUT (_N14570), + .COUT (_N15065), .Z (N522[9]), - .CIN (_N14569), + .CIN (_N15064), .I0 (), .I1 (char_height[9]), .I2 (char_pos_y[9]), @@ -321454,7 +320910,7 @@ module char_buf_reader N522_11 ( .COUT (), .Z (N522[10]), - .CIN (_N14570), + .CIN (_N15065), .I0 (), .I1 (char_height[10]), .I2 (char_pos_y[10]), @@ -321468,7 +320924,7 @@ module char_buf_reader GTP_LUT5 /* N564_2 */ #( .INIT(32'b00000000000000000000000000000001)) N564_2 ( - .Z (_N96929), + .Z (_N97697), .I0 (cnt[0]), .I1 (cnt[2]), .I2 (cnt[3]), @@ -321476,21 +320932,21 @@ module char_buf_reader .I4 (cnt[5])); // LUT = ~I0&~I1&~I2&~I3&~I4 ; - GTP_LUT5 /* N581_21 */ #( + GTP_LUT5 /* N581_22 */ #( .INIT(32'b00000000000000000000000000010000)) - N581_21 ( - .Z (_N106993), + N581_22 ( + .Z (_N107821), .I0 (ram_data[5]), .I1 (str_len[8]), - .I2 (_N108385), + .I2 (_N109249), .I3 (str_len[10]), .I4 (str_len[11])); // LUT = ~I0&~I1&I2&~I3&~I4 ; - GTP_LUT5 /* N581_23 */ #( + GTP_LUT5 /* N581_24 */ #( .INIT(32'b00000000000000000000000000000001)) - N581_23 ( - .Z (_N108385), + N581_24 ( + .Z (_N109249), .I0 (str_len[9]), .I1 (str_len[12]), .I2 (str_len[13]), @@ -321509,20 +320965,30 @@ module char_buf_reader .I4 (char_row_index[4])); // LUT = I0&~I1&~I2&~I3&I4 ; - GTP_LUT3 /* N589_5 */ #( + GTP_LUT3 /* N589_3 */ #( .INIT(8'b00000010)) - N589_5 ( - .Z (_N97174), - .I0 (_N97090), + N589_3 ( + .Z (_N97976), + .I0 (_N97897), .I1 (ram_data[1]), .I2 (ram_data[3])); // LUT = I0&~I1&~I2 ; - GTP_LUT4 /* N589_7 */ #( + GTP_LUT4 /* N589_5 */ #( .INIT(16'b0000000010000000)) - N589_7 ( + N589_5 ( .Z (N907[6]), - .I0 (_N97090), + .I0 (_N97897), + .I1 (ram_data[1]), + .I2 (ram_data[3]), + .I3 (ram_data[5])); + // LUT = I0&I1&I2&~I3 ; + + GTP_LUT4 /* N589_5_cpy */ #( + .INIT(16'b0000000010000000)) + N589_5_cpy ( + .Z (\N907[6]_cpy ), + .I0 (_N97897), .I1 (ram_data[1]), .I2 (ram_data[3]), .I3 (ram_data[5])); @@ -321531,7 +320997,7 @@ module char_buf_reader GTP_LUT5 /* N590_3 */ #( .INIT(32'b00000000000000000000000000000001)) N590_3 ( - .Z (_N97090), + .Z (_N97897), .I0 (ram_data[0]), .I1 (ram_data[2]), .I2 (ram_data[4]), @@ -321542,7 +321008,7 @@ module char_buf_reader GTP_LUT5 /* N590_8 */ #( .INIT(32'b00000000000000000000000000001000)) N590_8 ( - .Z (_N106978), + .Z (_N107806), .I0 (ram_data[0]), .I1 (ram_data[2]), .I2 (ram_data[4]), @@ -321550,21 +321016,11 @@ module char_buf_reader .I4 (ram_data[7])); // LUT = I0&I1&~I2&~I3&~I4 ; - GTP_LUT4 /* N590_9 */ #( - .INIT(16'b0000010000000000)) - N590_9 ( - .Z (N907[2]), - .I0 (ram_data[1]), - .I1 (ram_data[3]), - .I2 (ram_data[5]), - .I3 (_N106978)); - // LUT = ~I0&I1&~I2&I3 ; - GTP_LUT4 /* N593 */ #( .INIT(16'b0000000000001000)) N593 ( .Z (N907[5]), - .I0 (_N96372), + .I0 (_N97129), .I1 (cnt[0]), .I2 (cnt[1]), .I3 (cnt[2])); @@ -321575,23 +321031,32 @@ module char_buf_reader .INIT(16'b0000000000100000)) N597 ( .Z (N907[4]), - .I0 (_N96372), + .I0 (_N97129), .I1 (cnt[0]), .I2 (cnt[1]), .I3 (cnt[2])); // LUT = I0&~I1&I2&~I3 ; // ../../sources/designs/udp_osd/char_osd/char_buf_reader.v:179 + GTP_LUT3 /* N679_2 */ #( + .INIT(8'b01110000)) + N679_2 ( + .Z (_N96870), + .I0 (_N97976), + .I1 (ram_data[5]), + .I2 (state_reg[1])); + // LUT = (~I1&I2)|(~I0&I2) ; + GTP_LUT5 /* N683_7 */ #( - .INIT(32'b10001111100010000000111100000000)) + .INIT(32'b11000000111010100000000000000000)) N683_7 ( .Z (_N18389), - .I0 (_N97174), - .I1 (ram_data[5]), - .I2 (N73), - .I3 (N839), + .I0 (_N97124), + .I1 (_N97976), + .I2 (ram_data[5]), + .I3 (N73), .I4 (state_reg[1])); - // LUT = (~I2&I3)|(I0&I1&I4) ; + // LUT = (I0&~I3&I4)|(I1&I2&I4) ; GTP_LUT3 /* \N683_7[0] */ #( .INIT(8'b11011000)) @@ -321703,44 +321168,28 @@ module char_buf_reader // LUT = (~I0&I2)|(I0&I1) ; // ../../sources/designs/udp_osd/char_osd/char_buf_reader.v:383 - GTP_LUT4 /* N684 */ #( - .INIT(16'b1101110111010000)) + GTP_LUT5 /* N684 */ #( + .INIT(32'b11010101110101011101010100000000)) N684_vname ( .Z (N684), - .I0 (_N96517), - .I1 (N97), - .I2 (state_reg[1]), - .I3 (state_reg[0])); + .I0 (_N101750), + .I1 (char_next), + .I2 (char_valid), + .I3 (state_reg[1]), + .I4 (state_reg[0])); // defparam N684_vname.orig_name = N684; - // LUT = (~I0&I2)|(~I0&I3)|(I1&I2)|(I1&I3) ; - - GTP_LUT2 /* N709_1 */ #( - .INIT(4'b1000)) - N709_1 ( - .Z (_N96555), - .I0 (state_reg[1]), - .I1 (N907[7])); - // LUT = I0&I1 ; - - GTP_LUT3 /* N709_5 */ #( - .INIT(8'b10000000)) - N709_5 ( - .Z (_N107128), - .I0 (N73), - .I1 (state_reg[1]), - .I2 (N907[7])); - // LUT = I0&I1&I2 ; + // LUT = (~I0&I3)|(~I0&I4)|(I1&I2&I3)|(I1&I2&I4) ; GTP_LUT5 /* N711_2 */ #( - .INIT(32'b11111111111111111010101010000000)) + .INIT(32'b11111111111111111100110010000000)) N711_2 ( .Z (N711), - .I0 (_N96555), - .I1 (N73), - .I2 (N97), + .I0 (_N97124), + .I1 (_N97275), + .I2 (N73), .I3 (N478), .I4 (state_reg[0])); - // LUT = (I4)|(I0&I3)|(I0&I1&I2) ; + // LUT = (I4)|(I1&I3)|(I0&I1&I2) ; GTP_LUT3 /* \N715_1[0] */ #( .INIT(8'b11100100)) @@ -321865,7 +321314,7 @@ module char_buf_reader .INIT(32'b11001100110001001100110011001100)) N785_2 ( .Z (_N0), - .I0 (_N96372), + .I0 (_N97129), .I1 (state_reg[0]), .I2 (cnt[0]), .I3 (cnt[1]), @@ -321873,11 +321322,23 @@ module char_buf_reader // LUT = (I1&~I4)|(~I0&I1)|(I1&I2)|(I1&I3) ; // ../../sources/designs/udp_osd/char_osd/char_buf_reader.v:114 + GTP_LUT5 /* N785_4 */ #( + .INIT(32'b00000000000000000000100000000000)) + N785_4 ( + .Z (_N18392), + .I0 (_N97129), + .I1 (state_reg[2]), + .I2 (cnt[0]), + .I3 (cnt[1]), + .I4 (cnt[2])); + // LUT = I0&I1&~I2&I3&~I4 ; + // ../../sources/designs/udp_osd/char_osd/char_buf_reader.v:114 + GTP_LUT5 /* N785_5 */ #( .INIT(32'b11001100110011001100010011001100)) N785_5 ( .Z (_N15), - .I0 (_N96372), + .I0 (_N97129), .I1 (state_reg[2]), .I2 (cnt[0]), .I3 (cnt[1]), @@ -321900,7 +321361,7 @@ module char_buf_reader .INIT(32'b11111111000000001111111000000000)) \N785_7_or[1]_1 ( .Z (N785[1]), - .I0 (_N82884), + .I0 (_N84128), .I1 (N858), .I2 (_N0), .I3 (N902[1]), @@ -321910,8 +321371,8 @@ module char_buf_reader GTP_LUT5 /* \N785_7_or[1]_3 */ #( .INIT(32'b11001100110011001100110001001100)) \N785_7_or[1]_3 ( - .Z (_N82884), - .I0 (_N96372), + .Z (_N84128), + .I0 (_N97129), .I1 (N784), .I2 (cnt[0]), .I3 (cnt[1]), @@ -321931,59 +321392,85 @@ module char_buf_reader GTP_LUT4 /* \N785_7_or[3]_2 */ #( .INIT(16'b1111111111111110)) \N785_7_or[3]_2 ( - .Z (_N82900), + .Z (_N84135), .I0 (N784), .I1 (N858), .I2 (_N0), .I3 (state_reg[2])); // LUT = (I0)|(I1)|(I2)|(I3) ; - GTP_LUT4 /* N786 */ #( - .INIT(16'b1111111111010101)) + GTP_LUT5 /* N786 */ #( + .INIT(32'b11111111110101011101010111010101)) N786_vname ( .Z (N786), - .I0 (_N96518), - .I1 (_N97174), + .I0 (_N97126), + .I1 (_N97976), .I2 (ram_data[5]), - .I3 (N97)); + .I3 (char_next), + .I4 (char_valid)); // defparam N786_vname.orig_name = N786; - // LUT = (~I0)|(I3)|(I1&I2) ; + // LUT = (~I0)|(I1&I2)|(I3&I4) ; - GTP_LUT3 /* N832 */ #( - .INIT(8'b11111000)) + GTP_LUT5 /* N832 */ #( + .INIT(32'b10101010001100001010101000000000)) N832_vname ( .Z (N832), - .I0 (_N97174), - .I1 (ram_data[5]), - .I2 (N907[2])); + .I0 (_N97976), + .I1 (ram_data[1]), + .I2 (ram_data[3]), + .I3 (ram_data[5]), + .I4 (_N107806)); // defparam N832_vname.orig_name = N832; - // LUT = (I2)|(I0&I1) ; + // LUT = (I0&I3)|(~I1&I2&~I3&I4) ; // ../../sources/designs/udp_osd/char_osd/char_buf_reader.v:243 - GTP_LUT2 /* N839 */ #( + GTP_LUT2 /* N838_1 */ #( .INIT(4'b1000)) - N839_vname ( - .Z (N839), - .I0 (_N96517), - .I1 (N97)); - // defparam N839_vname.orig_name = N839; + N838_1 ( + .Z (_N97275), + .I0 (state_reg[1]), + .I1 (N907[7])); // LUT = I0&I1 ; + GTP_LUT4 /* N842 */ #( + .INIT(16'b0000000000001000)) + N842_vname ( + .Z (N842), + .I0 (state_reg[2]), + .I1 (N907[4]), + .I2 (\N907[6]_cpy ), + .I3 (N907[7])); + // defparam N842_vname.orig_name = N842; + // LUT = I0&I1&~I2&~I3 ; + // ../../sources/designs/udp_osd/char_osd/char_buf_reader.v:216 + GTP_LUT4 /* N843_2 */ #( .INIT(16'b0010101000100010)) N843_2 ( .Z (N843), .I0 (state_reg[2]), .I1 (N907[4]), - .I2 (N907[6]), + .I2 (\N907[6]_cpy ), .I3 (N907[7])); // LUT = (I0&~I1)|(I0&~I2&I3) ; + GTP_LUT5 /* N847_9 */ #( + .INIT(32'b00101010000000000000000000000000)) + N847_9 ( + .Z (_N18403), + .I0 (_N97124), + .I1 (_N97976), + .I2 (ram_data[5]), + .I3 (N245), + .I4 (state_reg[1])); + // LUT = (I0&~I2&I3&I4)|(I0&~I1&I3&I4) ; + // ../../sources/designs/udp_osd/char_osd/char_buf_reader.v:216 + GTP_LUT5 /* \N847_11_and[10][0] */ #( .INIT(32'b00000000000000000000000010000000)) \N847_11_and[10][0] ( - .Z (_N30374), - .I0 (_N96372), + .Z (_N30111), + .I0 (_N97129), .I1 (state_reg[0]), .I2 (cnt[0]), .I3 (cnt[1]), @@ -321996,7 +321483,7 @@ module char_buf_reader .Z (N847[0]), .I0 (_N18404), .I1 (_N18405), - .I2 (_N30325), + .I2 (_N30062), .I3 (ram_addr[0]), .I4 (start_char_ptr[0])); // LUT = (~I1&~I2&~I3)|(~I2&~I3&I4)|(~I0&~I1&~I2)|(~I0&~I2&I4) ; @@ -322007,7 +321494,7 @@ module char_buf_reader .Z (N847[1]), .I0 (_N18404), .I1 (_N18405), - .I2 (_N30325), + .I2 (_N30062), .I3 (N900[1]), .I4 (start_char_ptr[1])); // LUT = (~I0&~I1&~I2)|(~I1&~I2&I3)|(~I0&~I2&I4)|(~I2&I3&I4) ; @@ -322018,7 +321505,7 @@ module char_buf_reader .Z (N847[2]), .I0 (_N18404), .I1 (_N18405), - .I2 (_N30325), + .I2 (_N30062), .I3 (N900[2]), .I4 (start_char_ptr[2])); // LUT = (~I0&~I1&~I2)|(~I1&~I2&I3)|(~I0&~I2&I4)|(~I2&I3&I4) ; @@ -322029,7 +321516,7 @@ module char_buf_reader .Z (N847[3]), .I0 (_N18404), .I1 (_N18405), - .I2 (_N30325), + .I2 (_N30062), .I3 (N900[3]), .I4 (start_char_ptr[3])); // LUT = (~I0&~I1&~I2)|(~I1&~I2&I3)|(~I0&~I2&I4)|(~I2&I3&I4) ; @@ -322040,7 +321527,7 @@ module char_buf_reader .Z (N847[4]), .I0 (_N18404), .I1 (_N18405), - .I2 (_N30325), + .I2 (_N30062), .I3 (N900[4]), .I4 (start_char_ptr[4])); // LUT = (~I0&~I1&~I2)|(~I1&~I2&I3)|(~I0&~I2&I4)|(~I2&I3&I4) ; @@ -322051,7 +321538,7 @@ module char_buf_reader .Z (N847[5]), .I0 (_N18404), .I1 (_N18405), - .I2 (_N30325), + .I2 (_N30062), .I3 (N900[5]), .I4 (start_char_ptr[5])); // LUT = (~I0&~I1&~I2)|(~I1&~I2&I3)|(~I0&~I2&I4)|(~I2&I3&I4) ; @@ -322062,7 +321549,7 @@ module char_buf_reader .Z (N847[6]), .I0 (_N18404), .I1 (_N18405), - .I2 (_N30325), + .I2 (_N30062), .I3 (N900[6]), .I4 (start_char_ptr[6])); // LUT = (~I0&~I1&~I2)|(~I1&~I2&I3)|(~I0&~I2&I4)|(~I2&I3&I4) ; @@ -322073,7 +321560,7 @@ module char_buf_reader .Z (N847[7]), .I0 (_N18404), .I1 (_N18405), - .I2 (_N30325), + .I2 (_N30062), .I3 (N900[7]), .I4 (start_char_ptr[7])); // LUT = (~I0&~I1&~I2)|(~I1&~I2&I3)|(~I0&~I2&I4)|(~I2&I3&I4) ; @@ -322084,7 +321571,7 @@ module char_buf_reader .Z (N847[8]), .I0 (_N18404), .I1 (_N18405), - .I2 (_N30325), + .I2 (_N30062), .I3 (N900[8]), .I4 (start_char_ptr[8])); // LUT = (~I0&~I1&~I2)|(~I1&~I2&I3)|(~I0&~I2&I4)|(~I2&I3&I4) ; @@ -322095,7 +321582,7 @@ module char_buf_reader .Z (N847[9]), .I0 (_N18404), .I1 (_N18405), - .I2 (_N30325), + .I2 (_N30062), .I3 (N900[9]), .I4 (start_char_ptr[9])); // LUT = (~I0&~I1&~I2)|(~I1&~I2&I3)|(~I0&~I2&I4)|(~I2&I3&I4) ; @@ -322103,8 +321590,8 @@ module char_buf_reader GTP_LUT5 /* \N847_11_or[0][0] */ #( .INIT(32'b11001100110011001100110011000100)) \N847_11_or[0][0] ( - .Z (_N30325), - .I0 (_N96372), + .Z (_N30062), + .I0 (_N97129), .I1 (state_reg[0]), .I2 (cnt[0]), .I3 (cnt[1]), @@ -322117,64 +321604,56 @@ module char_buf_reader .Z (N847[10]), .I0 (_N18404), .I1 (_N18405), - .I2 (_N30374), + .I2 (_N30111), .I3 (N900[10]), .I4 (start_char_ptr[10])); // LUT = (I2)|(I0&I3)|(I1&I4) ; - GTP_LUT5M /* N847_15_2 */ #( - .INIT(32'b11111010000010101000000000000000)) - N847_15_2 ( - .Z (_N107017), + GTP_LUT5M /* N847_15_3 */ #( + .INIT(32'b11111110111011101110110011001100)) + N847_15_3 ( + .Z (_N18404), .I0 (N832), - .I1 (N907[4]), - .I2 (N907[6]), + .I1 (_N18403), + .I2 (\N907[6]_cpy ), .I3 (N907[7]), .I4 (state_reg[1]), - .ID (state_reg[2])); - // LUT = (I2&I3&I4)|(I0&~I2&I4)|(ID&I1&I2&I3) ; - - GTP_LUT3 /* N847_15_3 */ #( - .INIT(8'b11101010)) - N847_15_3 ( - .Z (_N18404), - .I0 (_N107017), - .I1 (N245), - .I2 (N839)); - // LUT = (I0)|(I1&I2) ; + .ID (_N18392)); + // LUT = (I2&I3&I4)|(I0&I4)|(ID&I2&I3)|(I1) ; GTP_LUT5 /* N847_29 */ #( .INIT(32'b00000000000000001110110010100000)) N847_29 ( - .Z (_N108032), + .Z (_N108866), .I0 (state_reg[2]), .I1 (state_reg[1]), .I2 (N907[4]), - .I3 (N907[6]), + .I3 (\N907[6]_cpy ), .I4 (N907[7])); // LUT = (I0&I2&~I4)|(I1&I3&~I4) ; - GTP_LUT4 /* N847_30 */ #( - .INIT(16'b1010101010111010)) + GTP_LUT5 /* N847_30 */ #( + .INIT(32'b11110000111100001111000011111000)) N847_30 ( .Z (_N18405), - .I0 (_N108032), - .I1 (N245), - .I2 (N839), - .I3 (N907[7])); - // LUT = (I0)|(~I1&I2&~I3) ; + .I0 (_N96870), + .I1 (_N97124), + .I2 (_N108866), + .I3 (N245), + .I4 (N907[7])); + // LUT = (I2)|(I0&I1&~I3&~I4) ; GTP_LUT5 /* N848 */ #( - .INIT(32'b00000000000000000000000000001101)) + .INIT(32'b00000000000000000000000011010101)) N848_vname ( .Z (N848), - .I0 (_N96517), - .I1 (N97), - .I2 (N843), - .I3 (state_reg[4]), - .I4 (state_reg[3])); + .I0 (_N101750), + .I1 (char_next), + .I2 (char_valid), + .I3 (N784), + .I4 (N843)); // defparam N848_vname.orig_name = N848; - // LUT = (~I0&~I2&~I3&~I4)|(I1&~I2&~I3&~I4) ; + // LUT = (~I0&~I3&~I4)|(I1&I2&~I3&~I4) ; GTP_LUT2 /* N861 */ #( .INIT(4'b1110)) @@ -322190,32 +321669,41 @@ module char_buf_reader .INIT(32'b01000000000000001010000000000000)) N862_vname ( .Z (N862), - .I0 (N907[6]), + .I0 (\N907[6]_cpy ), .I1 (state_reg[2]), .I2 (N907[7]), - .I3 (_N96929), + .I3 (_N97697), .I4 (cnt[1]), .ID (state_reg[3])); // defparam N862_vname.orig_name = N862; // LUT = (ID&I2&I3&~I4)|(~I0&I1&I2&I3&I4) ; - GTP_LUT5M /* N873_1 */ #( - .INIT(32'b11001110110011001110111011001100)) - N873_1 ( + GTP_LUT5 /* N873_2 */ #( + .INIT(32'b00000000101000001000100010001000)) + N873_2 ( + .Z (_N99326), + .I0 (_N97697), + .I1 (state_reg[3]), + .I2 (state_reg[2]), + .I3 (\N907[6]_cpy ), + .I4 (cnt[1])); + // LUT = (I0&I1&~I4)|(I0&I2&~I3&I4) ; + + GTP_LUT4 /* N873_3 */ #( + .INIT(16'b1110101010101010)) + N873_3 ( .Z (N873), - .I0 (state_reg[2]), - .I1 (N379), - .I2 (N907[6]), - .I3 (_N96929), - .I4 (cnt[1]), - .ID (state_reg[3])); - // LUT = (ID&I3&~I4)|(I0&~I2&I3&I4)|(I1) ; + .I0 (_N99326), + .I1 (char_next), + .I2 (char_valid), + .I3 (N73)); + // LUT = (I0)|(I1&I2&I3) ; GTP_LUT5 /* N883_2 */ #( .INIT(32'b00000000000010000000000000000000)) N883_2 ( .Z (N858), - .I0 (_N96372), + .I0 (_N97129), .I1 (state_reg[0]), .I2 (cnt[0]), .I3 (cnt[1]), @@ -322226,7 +321714,7 @@ module char_buf_reader .INIT(32'b00000000000000001000000000000000)) N883_6 ( .Z (N883), - .I0 (_N96372), + .I0 (_N97129), .I1 (state_reg[0]), .I2 (cnt[0]), .I3 (cnt[1]), @@ -322689,20 +322177,20 @@ module char_buf_reader char_valid_vname ( .Q (char_valid), .CLK (clk), - .D (_N103526)); + .D (_N104338)); // defparam char_valid_vname.orig_name = char_valid; // ../../sources/designs/udp_osd/char_osd/char_buf_reader.v:366 GTP_LUT5 /* char_valid_rs_mux */ #( - .INIT(32'b00000000000000000101010001010000)) + .INIT(32'b00000101010001000000010100000000)) char_valid_rs_mux ( - .Z (_N103526), + .Z (_N104338), .I0 (sync_vg_100m), - .I1 (_N96517), - .I2 (char_valid), - .I3 (N60), - .I4 (N97)); - // LUT = (~I0&I2&~I4)|(~I0&I1&I3&~I4) ; + .I1 (_N101750), + .I2 (char_next), + .I3 (char_valid), + .I4 (N60)); + // LUT = (~I0&~I2&I3)|(~I0&I1&~I3&I4) ; GTP_DFF_RE /* \char_width[0] */ #( .GRS_EN("TRUE"), @@ -323441,8 +322929,8 @@ module char_buf_reader .INIT(8'b10000000)) \state_fsm[3:0]_3 ( .Z (_N2), - .I0 (_N97174), - .I1 (_N106993), + .I0 (_N97976), + .I1 (_N107821), .I2 (state_reg[0])); // LUT = I0&I1&I2 ; // ../../sources/designs/udp_osd/char_osd/char_buf_reader.v:109 @@ -323452,16 +322940,27 @@ module char_buf_reader \state_fsm[3:0]_4_4 ( .Z (_N3), .I0 (N60), - .I1 (N79_cpy), + .I1 (N79), .I2 (_N2), .I3 (_N0), .I4 (state_reg[1])); // LUT = (I2)|(I3)|(~I0&I4)|(I1&I4) ; + GTP_LUT5 /* \state_fsm[3:0]_8 */ #( + .INIT(32'b00000000001010100010101000101010)) + \state_fsm[3:0]_8 ( + .Z (_N7), + .I0 (_N97126), + .I1 (_N97976), + .I2 (ram_data[5]), + .I3 (char_next), + .I4 (char_valid)); + // LUT = (I0&~I2&~I4)|(I0&~I1&~I4)|(I0&~I2&~I3)|(I0&~I1&~I3) ; + GTP_LUT3 /* \state_fsm[3:0]_10 */ #( .INIT(8'b00000001)) \state_fsm[3:0]_10 ( - .Z (_N96372), + .Z (_N97129), .I0 (cnt[3]), .I1 (cnt[4]), .I2 (cnt[5])); @@ -323470,112 +322969,90 @@ module char_buf_reader GTP_LUT5 /* \state_fsm[3:0]_13_2 */ #( .INIT(32'b11110111111100000111011100000000)) \state_fsm[3:0]_13_2 ( - .Z (_N106995), - .I0 (_N97174), - .I1 (_N106993), + .Z (_N107823), + .I0 (_N97976), + .I1 (_N107821), .I2 (N784), .I3 (N858), .I4 (N907[5])); // LUT = (~I1&I3)|(~I0&I3)|(I2&I4) ; - GTP_LUT5 /* \state_fsm[3:0]_13_3 */ #( - .INIT(32'b10101010111010101010101010101010)) - \state_fsm[3:0]_13_3 ( - .Z (_N106996), - .I0 (_N106995), - .I1 (state_reg[2]), - .I2 (N907[4]), - .I3 (N907[6]), - .I4 (N907[7])); - // LUT = (I0)|(I1&I2&~I3&I4) ; - GTP_LUT5 /* \state_fsm[3:0]_13_4 */ #( - .INIT(32'b11111111000000001111111100101010)) + .INIT(32'b11111111111111111100111011001100)) \state_fsm[3:0]_13_4 ( .Z (_N12), - .I0 (_N96518), - .I1 (_N97174), - .I2 (ram_data[5]), - .I3 (_N106996), - .I4 (N97)); - // LUT = (I3)|(I0&~I2&~I4)|(I0&~I1&~I4) ; + .I0 (_N18392), + .I1 (_N107823), + .I2 (\N907[6]_cpy ), + .I3 (N907[7]), + .I4 (_N7)); + // LUT = (I1)|(I4)|(I0&~I2&I3) ; GTP_LUT5 /* \state_fsm[3:0]_23_2 */ #( .INIT(32'b11000000111010100000000010101010)) \state_fsm[3:0]_23_2 ( - .Z (_N107004), + .Z (_N107826), .I0 (state_reg[3]), .I1 (state_reg[2]), .I2 (N907[4]), .I3 (N907[5]), - .I4 (N907[6])); + .I4 (\N907[6]_cpy )); // LUT = (I0&~I3)|(I1&I2&I4) ; GTP_LUT5 /* \state_fsm[3:0]_23_4 */ #( .INIT(32'b10101110101010101010101010101010)) \state_fsm[3:0]_23_4 ( .Z (_N22), - .I0 (_N107004), + .I0 (_N107826), .I1 (N60), - .I2 (N79_cpy), + .I2 (N79), .I3 (state_reg[1]), - .I4 (N907[6])); + .I4 (\N907[6]_cpy )); // LUT = (I0)|(I1&~I2&I3&I4) ; - GTP_LUT5 /* \state_fsm[3:0]_33_2 */ #( - .INIT(32'b10101010101010101010101011101010)) - \state_fsm[3:0]_33_2 ( - .Z (_N107006), - .I0 (_N81460), - .I1 (state_reg[2]), - .I2 (N907[4]), - .I3 (N907[6]), - .I4 (N907[7])); - // LUT = (I0)|(I1&I2&~I3&~I4) ; - GTP_LUT5 /* \state_fsm[3:0]_33_3 */ #( - .INIT(32'b11111111101010101111111110000000)) + .INIT(32'b11111000111110001111111111111000)) \state_fsm[3:0]_33_3 ( .Z (_N31), - .I0 (_N96518), - .I1 (_N97174), - .I2 (ram_data[5]), - .I3 (_N107006), - .I4 (N97)); - // LUT = (I3)|(I0&I4)|(I0&I1&I2) ; + .I0 (_N97126), + .I1 (N100), + .I2 (N842), + .I3 (state_reg[4]), + .I4 (N907[5])); + // LUT = (I2)|(I3&~I4)|(I0&I1) ; - GTP_LUT5 /* \state_fsm[3:0]_35 */ #( - .INIT(32'b11001100110011001100110001001100)) - \state_fsm[3:0]_35 ( - .Z (_N81460), - .I0 (_N96372), - .I1 (state_reg[4]), - .I2 (cnt[0]), - .I3 (cnt[1]), - .I4 (cnt[2])); - // LUT = (I1&~I2)|(~I0&I1)|(I1&I3)|(I1&I4) ; + GTP_LUT5 /* \state_fsm[3:0]_52 */ #( + .INIT(32'b00000100000000000000000000000000)) + \state_fsm[3:0]_52 ( + .Z (_N108858), + .I0 (ram_data[1]), + .I1 (ram_data[3]), + .I2 (ram_data[5]), + .I3 (_N107806), + .I4 (state_reg[1])); + // LUT = ~I0&I1&~I2&I3&I4 ; - GTP_LUT5 /* \state_fsm[3:0]_49 */ #( - .INIT(32'b00000000000000000000000001110000)) - \state_fsm[3:0]_49 ( - .Z (_N96517), - .I0 (_N97174), - .I1 (ram_data[5]), - .I2 (state_reg[1]), - .I3 (N907[2]), - .I4 (N907[6])); - // LUT = (~I1&I2&~I3&~I4)|(~I0&I2&~I3&~I4) ; + GTP_LUT5 /* \state_fsm[3:0]_62 */ #( + .INIT(32'b00000010000000000000101000000000)) + \state_fsm[3:0]_62 ( + .Z (_N97126), + .I0 (N60), + .I1 (N74), + .I2 (N478), + .I3 (state_reg[1]), + .I4 (N907[7])); + // LUT = (I0&~I2&I3&~I4)|(I0&~I1&~I2&I3) ; - GTP_LUT5 /* \state_fsm[3:0]_54 */ #( - .INIT(32'b11111111111111110010000000000000)) - \state_fsm[3:0]_54 ( + GTP_LUT5 /* \state_fsm[3:0]_65 */ #( + .INIT(32'b00001000000010001111111100001000)) + \state_fsm[3:0]_65 ( .Z (_N16), - .I0 (N60), - .I1 (N79_cpy), - .I2 (state_reg[1]), - .I3 (N907[2]), - .I4 (_N15)); - // LUT = (I4)|(I0&~I1&I2&I3) ; + .I0 (_N108858), + .I1 (N60), + .I2 (N79), + .I3 (state_reg[2]), + .I4 (N907[4])); + // LUT = (I3&~I4)|(I0&I1&~I2) ; (* syn_encoding="onehot" *) GTP_DFF_S /* \state_reg[0] */ #( .GRS_EN("TRUE"), @@ -323975,60 +323452,55 @@ module char_pic_rom input [10:0] char_pos_x, input [10:0] char_pos_y, input [5:0] char_row_index, - input [9:0] \udp_osd_inst/char_osd_inst/char_buf_reader_inst/N907 , - input [4:0] \udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_reg , - input _N107128, input char_valid, input clk, input m_row_pixels_ready, input sync_vg_100m, input \udp_osd_inst/char_osd_inst/char_ascii[0]_inv , - input \udp_osd_inst/char_osd_inst/char_buf_reader_inst/N97 , output [8:0] m_row_pixels_data, output [10:0] m_row_pixels_posX, output [10:0] m_row_pixels_posY, output N41, output char_next, - output m_row_pixels_valid, - output \udp_osd_inst/char_osd_inst/char_buf_reader_inst/N714 + output m_row_pixels_valid ); wire [10:0] N29; wire [10:0] N38; wire [10:0] N61; - wire _N9062; - wire _N10325; - wire _N10331; - wire _N14457; - wire _N14458; - wire _N14459; - wire _N14460; - wire _N14461; - wire _N14462; - wire _N14463; - wire _N14464; - wire _N14465; - wire _N14466; - wire _N14610; - wire _N14611; - wire _N14612; - wire _N14613; - wire _N14614; - wire _N14615; - wire _N14616; - wire _N14617; - wire _N16612; - wire _N16613; - wire _N16614; - wire _N16615; - wire _N16616; - wire _N16617; - wire _N16618; - wire _N16619; - wire _N16620; - wire _N95973; - wire _N103528; - wire _N107183; - wire _N107189; + wire _N4437; + wire _N10345; + wire _N10351; + wire _N14828; + wire _N14829; + wire _N14830; + wire _N14831; + wire _N14832; + wire _N14833; + wire _N14834; + wire _N14835; + wire _N15105; + wire _N15106; + wire _N15107; + wire _N15108; + wire _N15109; + wire _N15110; + wire _N15111; + wire _N15112; + wire _N15113; + wire _N15114; + wire _N16517; + wire _N16518; + wire _N16519; + wire _N16520; + wire _N16521; + wire _N16522; + wire _N16523; + wire _N16524; + wire _N16525; + wire _N97272; + wire _N104340; + wire _N108005; + wire _N108011; wire [10:0] rom_addr; wire [10:0] rom_addr_d; wire \rom_addr_d[10:0]_or ; @@ -324037,7 +323509,7 @@ module char_pic_rom GTP_LUT5 /* N6_mux4_5 */ #( .INIT(32'b00000000000000000000000000000001)) N6_mux4_5 ( - .Z (_N9062), + .Z (_N4437), .I0 (char_ascii[0]), .I1 (char_ascii[1]), .I2 (char_ascii[2]), @@ -324048,7 +323520,7 @@ module char_pic_rom GTP_LUT2 /* N11_mux6_1 */ #( .INIT(4'b1000)) N11_mux6_1 ( - .Z (_N95973), + .Z (_N97272), .I0 (char_ascii[2]), .I1 (char_ascii[5])); // LUT = I0&I1 ; @@ -324056,7 +323528,7 @@ module char_pic_rom GTP_LUT4 /* N11_mux6_10 */ #( .INIT(16'b1000000000000000)) N11_mux6_10 ( - .Z (_N107183), + .Z (_N108005), .I0 (char_ascii[0]), .I1 (char_ascii[1]), .I2 (char_ascii[3]), @@ -324070,7 +323542,7 @@ module char_pic_rom .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N22_3_1 ( - .COUT (_N14610), + .COUT (_N14828), .Z (N61[2]), .CIN (), .I0 (char_ascii[0]), @@ -324089,9 +323561,9 @@ module char_pic_rom .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N22_3_2 ( - .COUT (_N14611), + .COUT (_N14829), .Z (N61[3]), - .CIN (_N14610), + .CIN (_N14828), .I0 (char_ascii[0]), .I1 (char_ascii[1]), .I2 (char_ascii[2]), @@ -324108,9 +323580,9 @@ module char_pic_rom .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N22_3_3 ( - .COUT (_N14612), + .COUT (_N14830), .Z (N61[4]), - .CIN (_N14611), + .CIN (_N14829), .I0 (), .I1 (char_ascii[3]), .I2 (char_ascii[0]), @@ -324127,9 +323599,9 @@ module char_pic_rom .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N22_3_4 ( - .COUT (_N14613), + .COUT (_N14831), .Z (N61[5]), - .CIN (_N14612), + .CIN (_N14830), .I0 (), .I1 (char_ascii[1]), .I2 (char_ascii[4]), @@ -324146,14 +323618,14 @@ module char_pic_rom .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N22_3_5 ( - .COUT (_N14614), + .COUT (_N14832), .Z (N61[6]), - .CIN (_N14613), + .CIN (_N14831), .I0 (), .I1 (char_ascii[1]), - .I2 (_N10325), + .I2 (_N10345), .I3 (char_ascii[4]), - .I4 (_N10325), + .I4 (_N10345), .ID ()); // LUT = (CIN&~I1&~I2&~I3)|(~CIN&~I1&I2&~I3)|(~CIN&~I2&I3)|(CIN&I2&I3)|(~CIN&I1&~I2)|(CIN&I1&I2) ; // CARRY = ((~I1&I2&~I3)|(~I2&I3)|(I1&~I2)) ? CIN : (I4) ; @@ -324165,14 +323637,14 @@ module char_pic_rom .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N22_3_6 ( - .COUT (_N14615), + .COUT (_N14833), .Z (N61[7]), - .CIN (_N14614), + .CIN (_N14832), .I0 (), - .I1 (_N95973), + .I1 (_N97272), .I2 (char_ascii[3]), .I3 (char_ascii[6]), - .I4 (_N95973), + .I4 (_N97272), .ID ()); // LUT = ~I3^I2^I1^CIN ; // CARRY = (~I3^I2^I1) ? CIN : (I4) ; @@ -324184,14 +323656,14 @@ module char_pic_rom .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N22_3_7 ( - .COUT (_N14616), + .COUT (_N14834), .Z (N61[8]), - .CIN (_N14615), + .CIN (_N14833), .I0 (), - .I1 (_N10331), + .I1 (_N10351), .I2 (char_ascii[4]), .I3 (char_ascii[7]), - .I4 (_N10331), + .I4 (_N10351), .ID ()); // LUT = ~I3^I2^I1^CIN ; // CARRY = (~I3^I2^I1) ? CIN : (I4) ; @@ -324203,9 +323675,9 @@ module char_pic_rom .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N22_3_8 ( - .COUT (_N14617), + .COUT (_N14835), .Z (N61[9]), - .CIN (_N14616), + .CIN (_N14834), .I0 (), .I1 (char_ascii[4]), .I2 (char_ascii[5]), @@ -324224,7 +323696,7 @@ module char_pic_rom N22_3_9 ( .COUT (), .Z (N61[10]), - .CIN (_N14617), + .CIN (_N14835), .I0 (), .I1 (char_ascii[6]), .I2 (), @@ -324241,7 +323713,7 @@ module char_pic_rom .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N29_1_1 ( - .COUT (_N16612), + .COUT (_N16517), .Z (N29[1]), .CIN (), .I0 (char_row_index[1]), @@ -324261,9 +323733,9 @@ module char_pic_rom .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N29_1_2 ( - .COUT (_N16613), + .COUT (_N16518), .Z (N29[2]), - .CIN (_N16612), + .CIN (_N16517), .I0 (char_row_index[1]), .I1 (rom_addr_d[1]), .I2 (char_row_index[2]), @@ -324281,9 +323753,9 @@ module char_pic_rom .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N29_1_3 ( - .COUT (_N16614), + .COUT (_N16519), .Z (N29[3]), - .CIN (_N16613), + .CIN (_N16518), .I0 (), .I1 (char_row_index[3]), .I2 (rom_addr_d[3]), @@ -324301,9 +323773,9 @@ module char_pic_rom .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N29_1_4 ( - .COUT (_N16615), + .COUT (_N16520), .Z (N29[4]), - .CIN (_N16614), + .CIN (_N16519), .I0 (), .I1 (char_row_index[4]), .I2 (rom_addr_d[4]), @@ -324321,9 +323793,9 @@ module char_pic_rom .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N29_1_5 ( - .COUT (_N16616), + .COUT (_N16521), .Z (N29[5]), - .CIN (_N16615), + .CIN (_N16520), .I0 (), .I1 (rom_addr_d[5]), .I2 (), @@ -324341,9 +323813,9 @@ module char_pic_rom .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N29_1_6 ( - .COUT (_N16617), + .COUT (_N16522), .Z (N29[6]), - .CIN (_N16616), + .CIN (_N16521), .I0 (), .I1 (rom_addr_d[6]), .I2 (), @@ -324361,9 +323833,9 @@ module char_pic_rom .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N29_1_7 ( - .COUT (_N16618), + .COUT (_N16523), .Z (N29[7]), - .CIN (_N16617), + .CIN (_N16522), .I0 (), .I1 (rom_addr_d[7]), .I2 (), @@ -324381,9 +323853,9 @@ module char_pic_rom .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N29_1_8 ( - .COUT (_N16619), + .COUT (_N16524), .Z (N29[8]), - .CIN (_N16618), + .CIN (_N16523), .I0 (), .I1 (rom_addr_d[8]), .I2 (), @@ -324401,9 +323873,9 @@ module char_pic_rom .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N29_1_9 ( - .COUT (_N16620), + .COUT (_N16525), .Z (N29[9]), - .CIN (_N16619), + .CIN (_N16524), .I0 (), .I1 (rom_addr_d[9]), .I2 (), @@ -324423,7 +323895,7 @@ module char_pic_rom N29_1_10 ( .COUT (), .Z (N29[10]), - .CIN (_N16620), + .CIN (_N16525), .I0 (), .I1 (rom_addr_d[10]), .I2 (), @@ -324441,7 +323913,7 @@ module char_pic_rom .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N38_1 ( - .COUT (_N14457), + .COUT (_N15105), .Z (N38[0]), .CIN (), .I0 (char_row_index[0]), @@ -324461,9 +323933,9 @@ module char_pic_rom .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N38_2 ( - .COUT (_N14458), + .COUT (_N15106), .Z (N38[1]), - .CIN (_N14457), + .CIN (_N15105), .I0 (char_row_index[0]), .I1 (char_pos_y[0]), .I2 (char_row_index[1]), @@ -324481,9 +323953,9 @@ module char_pic_rom .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N38_3 ( - .COUT (_N14459), + .COUT (_N15107), .Z (N38[2]), - .CIN (_N14458), + .CIN (_N15106), .I0 (), .I1 (char_row_index[2]), .I2 (char_pos_y[2]), @@ -324501,9 +323973,9 @@ module char_pic_rom .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N38_4 ( - .COUT (_N14460), + .COUT (_N15108), .Z (N38[3]), - .CIN (_N14459), + .CIN (_N15107), .I0 (), .I1 (char_row_index[3]), .I2 (char_pos_y[3]), @@ -324521,9 +323993,9 @@ module char_pic_rom .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N38_5 ( - .COUT (_N14461), + .COUT (_N15109), .Z (N38[4]), - .CIN (_N14460), + .CIN (_N15108), .I0 (), .I1 (char_row_index[4]), .I2 (char_pos_y[4]), @@ -324541,9 +324013,9 @@ module char_pic_rom .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N38_6 ( - .COUT (_N14462), + .COUT (_N15110), .Z (N38[5]), - .CIN (_N14461), + .CIN (_N15109), .I0 (), .I1 (char_pos_y[5]), .I2 (), @@ -324561,9 +324033,9 @@ module char_pic_rom .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N38_7 ( - .COUT (_N14463), + .COUT (_N15111), .Z (N38[6]), - .CIN (_N14462), + .CIN (_N15110), .I0 (), .I1 (char_pos_y[6]), .I2 (), @@ -324581,9 +324053,9 @@ module char_pic_rom .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N38_8 ( - .COUT (_N14464), + .COUT (_N15112), .Z (N38[7]), - .CIN (_N14463), + .CIN (_N15111), .I0 (), .I1 (char_pos_y[7]), .I2 (), @@ -324601,9 +324073,9 @@ module char_pic_rom .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N38_9 ( - .COUT (_N14465), + .COUT (_N15113), .Z (N38[8]), - .CIN (_N14464), + .CIN (_N15112), .I0 (), .I1 (char_pos_y[8]), .I2 (), @@ -324621,9 +324093,9 @@ module char_pic_rom .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N38_10 ( - .COUT (_N14466), + .COUT (_N15114), .Z (N38[9]), - .CIN (_N14465), + .CIN (_N15113), .I0 (), .I1 (char_pos_y[9]), .I2 (), @@ -324643,7 +324115,7 @@ module char_pic_rom N38_11 ( .COUT (), .Z (N38[10]), - .CIN (_N14466), + .CIN (_N15114), .I0 (), .I1 (char_pos_y[10]), .I2 (), @@ -324676,7 +324148,7 @@ module char_pic_rom GTP_LUT2 /* N58_maj7 */ #( .INIT(4'b1110)) N58_maj7 ( - .Z (_N10331), + .Z (_N10351), .I0 (char_ascii[3]), .I1 (char_ascii[6])); // LUT = (I0)|(I1) ; @@ -324684,7 +324156,7 @@ module char_pic_rom GTP_LUT2 /* N58_sum6 */ #( .INIT(4'b0110)) N58_sum6 ( - .Z (_N10325), + .Z (_N10345), .I0 (char_ascii[2]), .I1 (char_ascii[5])); // LUT = (I0&~I1)|(~I0&I1) ; @@ -324922,14 +324394,14 @@ module char_pic_rom m_row_pixels_valid_vname ( .Q (m_row_pixels_valid), .CLK (clk), - .D (_N103528)); + .D (_N104340)); // defparam m_row_pixels_valid_vname.orig_name = m_row_pixels_valid; // ../../sources/designs/udp_osd/char_osd/char_pic_rom.v:103 GTP_LUT5 /* m_row_pixels_valid_rs_mux_2 */ #( .INIT(32'b00000100000001000101010100000100)) m_row_pixels_valid_rs_mux_2 ( - .Z (_N103528), + .Z (_N104340), .I0 (sync_vg_100m), .I1 (m_row_pixels_valid), .I2 (N41), @@ -325137,37 +324609,26 @@ module char_pic_rom .R (\rom_addr_d[10:0]_or )); // ../../sources/designs/udp_osd/char_osd/char_pic_rom.v:48 - GTP_LUT5 /* \rom_addr_d[10:0]_or_1 */ #( - .INIT(32'b11110000111100001111000011111000)) - \rom_addr_d[10:0]_or_1 ( - .Z (\udp_osd_inst/char_osd_inst/char_buf_reader_inst/N714 ), - .I0 (_N107128), - .I1 (\udp_osd_inst/char_osd_inst/char_buf_reader_inst/N97 ), - .I2 (\udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_reg [0] ), - .I3 (\udp_osd_inst/char_osd_inst/char_buf_reader_inst/N907 [2] ), - .I4 (\udp_osd_inst/char_osd_inst/char_buf_reader_inst/N907 [6] )); - // LUT = (I2)|(I0&I1&~I3&~I4) ; - - GTP_LUT5 /* \rom_addr_d[10:0]_or_5 */ #( + GTP_LUT5 /* \rom_addr_d[10:0]_or_2 */ #( .INIT(32'b11111111100000001111111100000000)) - \rom_addr_d[10:0]_or_5 ( - .Z (_N107189), + \rom_addr_d[10:0]_or_2 ( + .Z (_N108011), .I0 (char_ascii[2]), .I1 (char_ascii[4]), .I2 (char_ascii[5]), .I3 (char_ascii[7]), - .I4 (_N107183)); + .I4 (_N108005)); // LUT = (I3)|(I0&I1&I2&I4) ; - GTP_LUT5 /* \rom_addr_d[10:0]_or_7 */ #( + GTP_LUT5 /* \rom_addr_d[10:0]_or_4 */ #( .INIT(32'b11111111111111111010101011101111)) - \rom_addr_d[10:0]_or_7 ( + \rom_addr_d[10:0]_or_4 ( .Z (\rom_addr_d[10:0]_or ), .I0 (sync_vg_100m), - .I1 (_N9062), + .I1 (_N4437), .I2 (char_ascii[5]), .I3 (char_ascii[6]), - .I4 (_N107189)); + .I4 (_N108011)); // LUT = (I0)|(I4)|(~I2&~I3)|(I1&~I3) ; GTP_DFF_R /* \rom_addr_d[10] */ #( @@ -325244,30 +324705,30 @@ module pixels_shifter wire N137; wire [8:0] N138; wire [10:0] N140; - wire _N10397; - wire _N10405; - wire _N16805; - wire _N16806; - wire _N16807; - wire _N16808; - wire _N16810; - wire _N16811; - wire _N16812; - wire _N16813; - wire _N16814; - wire _N16815; - wire _N16816; - wire _N16817; - wire _N16818; - wire _N16819; - wire _N99960; - wire _N103313; - wire _N103518; - wire _N107115; - wire _N107125; - wire _N107126; - wire _N107175; - wire _N107176; + wire _N10417; + wire _N10425; + wire _N16744; + wire _N16745; + wire _N16746; + wire _N16747; + wire _N16749; + wire _N16750; + wire _N16751; + wire _N16752; + wire _N16753; + wire _N16754; + wire _N16755; + wire _N16756; + wire _N16757; + wire _N16758; + wire _N100778; + wire _N104125; + wire _N104330; + wire _N107938; + wire _N107948; + wire _N107949; + wire _N107997; + wire _N107998; wire [5:0] pix_cnt; wire [8:0] pixels_data; wire s_ready_d; @@ -325287,7 +324748,7 @@ module pixels_shifter GTP_LUT4 /* N9_mux7_6 */ #( .INIT(16'b0111111111111111)) N9_mux7_6 ( - .Z (_N107175), + .Z (_N107997), .I0 (m_pixel_posX[1]), .I1 (m_pixel_posX[2]), .I2 (m_pixel_posX[3]), @@ -325297,7 +324758,7 @@ module pixels_shifter GTP_LUT4 /* N9_mux7_7 */ #( .INIT(16'b0111111111111111)) N9_mux7_7 ( - .Z (_N107176), + .Z (_N107998), .I0 (m_pixel_posX[0]), .I1 (m_pixel_posX[5]), .I2 (m_pixel_posX[6]), @@ -325311,14 +324772,14 @@ module pixels_shifter .I0 (m_pixel_posX[8]), .I1 (m_pixel_posX[9]), .I2 (m_pixel_posX[10]), - .I3 (_N107175), - .I4 (_N107176)); + .I3 (_N107997), + .I4 (_N107998)); // LUT = (~I2)|(~I0&~I1&I3)|(~I0&~I1&I4) ; GTP_LUT4 /* N18_mux7_6 */ #( .INIT(16'b1111111111111110)) N18_mux7_6 ( - .Z (_N107125), + .Z (_N107948), .I0 (s_row_pixels_posX[0]), .I1 (s_row_pixels_posX[1]), .I2 (s_row_pixels_posX[2]), @@ -325328,7 +324789,7 @@ module pixels_shifter GTP_LUT4 /* N18_mux7_7 */ #( .INIT(16'b1111111111111110)) N18_mux7_7 ( - .Z (_N107126), + .Z (_N107949), .I0 (s_row_pixels_posX[4]), .I1 (s_row_pixels_posX[5]), .I2 (s_row_pixels_posX[6]), @@ -325342,14 +324803,14 @@ module pixels_shifter .I0 (s_row_pixels_posX[8]), .I1 (s_row_pixels_posX[9]), .I2 (s_row_pixels_posX[10]), - .I3 (_N107125), - .I4 (_N107126)); + .I3 (_N107948), + .I4 (_N107949)); // LUT = (I1&I2)|(I0&I2&I3)|(I0&I2&I4) ; GTP_LUT4 /* N23_mux3_4 */ #( .INIT(16'b1111111111111110)) N23_mux3_4 ( - .Z (_N10397), + .Z (_N10417), .I0 (s_row_pixels_posY[0]), .I1 (s_row_pixels_posY[1]), .I2 (s_row_pixels_posY[2]), @@ -325359,8 +324820,8 @@ module pixels_shifter GTP_LUT5 /* N23_mux7_3 */ #( .INIT(32'b11111000000000000000000000000000)) N23_mux7_3 ( - .Z (_N10405), - .I0 (_N10397), + .Z (_N10425), + .I0 (_N10417), .I1 (s_row_pixels_posY[4]), .I2 (s_row_pixels_posY[5]), .I3 (s_row_pixels_posY[6]), @@ -325386,7 +324847,7 @@ module pixels_shifter .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N83_1_1 ( - .COUT (_N16805), + .COUT (_N16744), .Z (N136[1]), .CIN (), .I0 (pix_cnt[0]), @@ -325406,9 +324867,9 @@ module pixels_shifter .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N83_1_2 ( - .COUT (_N16806), + .COUT (_N16745), .Z (N136[2]), - .CIN (_N16805), + .CIN (_N16744), .I0 (pix_cnt[0]), .I1 (pix_cnt[1]), .I2 (sync_vg_100m), @@ -325426,9 +324887,9 @@ module pixels_shifter .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N83_1_3 ( - .COUT (_N16807), + .COUT (_N16746), .Z (N136[3]), - .CIN (_N16806), + .CIN (_N16745), .I0 (), .I1 (pix_cnt[3]), .I2 (sync_vg_100m), @@ -325446,9 +324907,9 @@ module pixels_shifter .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N83_1_4 ( - .COUT (_N16808), + .COUT (_N16747), .Z (N136[4]), - .CIN (_N16807), + .CIN (_N16746), .I0 (), .I1 (pix_cnt[4]), .I2 (sync_vg_100m), @@ -325468,7 +324929,7 @@ module pixels_shifter N83_1_5 ( .COUT (), .Z (N136[5]), - .CIN (_N16808), + .CIN (_N16747), .I0 (), .I1 (pix_cnt[5]), .I2 (sync_vg_100m), @@ -325486,7 +324947,7 @@ module pixels_shifter .I4_TO_CARRY("FALSE"), .I4_TO_LUT("FALSE")) N102_1_0 ( - .COUT (_N16810), + .COUT (_N16749), .Z (), .CIN (), .I0 (), @@ -325506,9 +324967,9 @@ module pixels_shifter .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N102_1_1 ( - .COUT (_N16811), + .COUT (_N16750), .Z (N140[1]), - .CIN (_N16810), + .CIN (_N16749), .I0 (), .I1 (m_pixel_posX[1]), .I2 (N15), @@ -325526,9 +324987,9 @@ module pixels_shifter .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N102_1_2 ( - .COUT (_N16812), + .COUT (_N16751), .Z (N140[2]), - .CIN (_N16811), + .CIN (_N16750), .I0 (), .I1 (m_pixel_posX[2]), .I2 (N15), @@ -325546,9 +325007,9 @@ module pixels_shifter .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N102_1_3 ( - .COUT (_N16813), + .COUT (_N16752), .Z (N140[3]), - .CIN (_N16812), + .CIN (_N16751), .I0 (), .I1 (m_pixel_posX[3]), .I2 (N15), @@ -325566,9 +325027,9 @@ module pixels_shifter .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N102_1_4 ( - .COUT (_N16814), + .COUT (_N16753), .Z (N140[4]), - .CIN (_N16813), + .CIN (_N16752), .I0 (), .I1 (m_pixel_posX[4]), .I2 (N15), @@ -325586,9 +325047,9 @@ module pixels_shifter .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N102_1_5 ( - .COUT (_N16815), + .COUT (_N16754), .Z (N140[5]), - .CIN (_N16814), + .CIN (_N16753), .I0 (), .I1 (m_pixel_posX[5]), .I2 (N15), @@ -325606,9 +325067,9 @@ module pixels_shifter .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N102_1_6 ( - .COUT (_N16816), + .COUT (_N16755), .Z (N140[6]), - .CIN (_N16815), + .CIN (_N16754), .I0 (), .I1 (m_pixel_posX[6]), .I2 (N15), @@ -325626,9 +325087,9 @@ module pixels_shifter .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N102_1_7 ( - .COUT (_N16817), + .COUT (_N16756), .Z (N140[7]), - .CIN (_N16816), + .CIN (_N16755), .I0 (), .I1 (m_pixel_posX[7]), .I2 (N15), @@ -325646,9 +325107,9 @@ module pixels_shifter .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N102_1_8 ( - .COUT (_N16818), + .COUT (_N16757), .Z (N140[8]), - .CIN (_N16817), + .CIN (_N16756), .I0 (), .I1 (m_pixel_posX[8]), .I2 (N15), @@ -325666,9 +325127,9 @@ module pixels_shifter .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N102_1_9 ( - .COUT (_N16819), + .COUT (_N16758), .Z (N140[9]), - .CIN (_N16818), + .CIN (_N16757), .I0 (), .I1 (m_pixel_posX[9]), .I2 (N15), @@ -325688,7 +325149,7 @@ module pixels_shifter N102_1_10 ( .COUT (), .Z (N140[10]), - .CIN (_N16819), + .CIN (_N16758), .I0 (), .I1 (m_pixel_posX[10]), .I2 (N15), @@ -325702,7 +325163,7 @@ module pixels_shifter GTP_LUT2 /* N114_8 */ #( .INIT(4'b0001)) N114_8 ( - .Z (_N107115), + .Z (_N107938), .I0 (pix_cnt[4]), .I1 (pix_cnt[5])); // LUT = ~I0&~I1 ; @@ -325715,7 +325176,7 @@ module pixels_shifter .I1 (pix_cnt[1]), .I2 (pix_cnt[2]), .I3 (pix_cnt[3]), - .I4 (_N107115)); + .I4 (_N107938)); // LUT = ~I0&~I1&~I2&I3&I4 ; GTP_LUT5 /* N122 */ #( @@ -326112,16 +325573,16 @@ module pixels_shifter m_pixel_valid_vname ( .Q (m_pixel_valid), .CLK (clk), - .D (_N103518)); + .D (_N104330)); // defparam m_pixel_valid_vname.orig_name = m_pixel_valid; // ../../sources/designs/udp_osd/char_osd/pixel_shifter.v:68 GTP_LUT5 /* m_pixel_valid_rs_mux */ #( .INIT(32'b00010001010100010000000001010000)) m_pixel_valid_rs_mux ( - .Z (_N103518), + .Z (_N104330), .I0 (sync_vg_100m), - .I1 (_N99960), + .I1 (_N100778), .I2 (m_pixel_valid), .I3 (N6), .I4 (N15)); @@ -326298,7 +325759,7 @@ module pixels_shifter s_ready_d_vname ( .Q (s_ready_d), .CLK (clk), - .D (_N103313), + .D (_N104125), .R (sync_vg_100m)); // defparam s_ready_d_vname.orig_name = s_ready_d; // ../../sources/designs/udp_osd/char_osd/pixel_shifter.v:44 @@ -326306,8 +325767,8 @@ module pixels_shifter GTP_LUT5M /* s_ready_d_ce_mux */ #( .INIT(32'b11101110111011101111110111111100)) s_ready_d_ce_mux ( - .Z (_N103313), - .I0 (_N99960), + .Z (_N104125), + .I0 (_N100778), .I1 (N122), .I2 (s_ready_d), .I3 (N114), @@ -326318,8 +325779,8 @@ module pixels_shifter GTP_LUT5 /* \s_ready_d_d[0]_4 */ #( .INIT(32'b11111111111111111111111111100000)) \s_ready_d_d[0]_4 ( - .Z (_N99960), - .I0 (_N10405), + .Z (_N100778), + .I0 (_N10425), .I1 (s_row_pixels_posY[8]), .I2 (s_row_pixels_posY[9]), .I3 (s_row_pixels_posY[10]), @@ -326337,25 +325798,25 @@ module char_osd input [10:0] cfg_start_posX, input [10:0] cfg_start_posY, input [7:0] ram_dout, + input \char_buf_reader_inst/N714 , input clk, input hdmi_de_out1, input \pixels_shifter_inst/N64 , input sync_vg_100m, input \udp_osd_inst/N26 , input \udp_osd_inst/N29 , + output [9:0] \char_buf_reader_inst/N907 , + output [4:0] \char_buf_reader_inst/state_reg , output [10:0] m_pixel_posX, output [10:0] m_pixel_posY, output [10:0] ram_rd_addr, + output _N97124, + output \char_buf_reader_inst/N73 , output m_pixel_data, output m_pixel_valid ); - wire _N107128; wire [7:0] char_ascii; wire \char_ascii[0]_inv ; - wire \char_buf_reader_inst/N97 ; - wire \char_buf_reader_inst/N714 ; - wire [9:0] \char_buf_reader_inst/N907 ; - wire [4:0] \char_buf_reader_inst/state_reg ; wire char_next; wire \char_pic_rom_inst/N41 ; wire [10:0] char_pos_x; @@ -326369,33 +325830,33 @@ module char_osd wire row_pixels_valid; wire \char_buf_reader_inst_N907[0]_floating ; wire \char_buf_reader_inst_N907[1]_floating ; + wire \char_buf_reader_inst_N907[2]_floating ; wire \char_buf_reader_inst_N907[3]_floating ; wire \char_buf_reader_inst_N907[4]_floating ; wire \char_buf_reader_inst_N907[5]_floating ; - wire \char_buf_reader_inst_N907[7]_floating ; + wire \char_buf_reader_inst_N907[6]_floating ; wire \char_buf_reader_inst_N907[8]_floating ; wire \char_buf_reader_inst_N907[9]_floating ; wire \char_buf_reader_inst_char_row_index[5]_floating ; - wire \char_buf_reader_inst_state_reg[1]_floating ; wire \char_buf_reader_inst_state_reg[2]_floating ; wire \char_buf_reader_inst_state_reg[3]_floating ; wire \char_buf_reader_inst_state_reg[4]_floating ; char_buf_reader char_buf_reader_inst ( - .N907 ({\char_buf_reader_inst_N907[9]_floating , \char_buf_reader_inst_N907[8]_floating , \char_buf_reader_inst_N907[7]_floating , \char_buf_reader_inst/N907 [6] , \char_buf_reader_inst_N907[5]_floating , \char_buf_reader_inst_N907[4]_floating , \char_buf_reader_inst_N907[3]_floating , \char_buf_reader_inst/N907 [2] , \char_buf_reader_inst_N907[1]_floating , \char_buf_reader_inst_N907[0]_floating }), + .N907 ({\char_buf_reader_inst_N907[9]_floating , \char_buf_reader_inst_N907[8]_floating , \char_buf_reader_inst/N907 [7] , \char_buf_reader_inst_N907[6]_floating , \char_buf_reader_inst_N907[5]_floating , \char_buf_reader_inst_N907[4]_floating , \char_buf_reader_inst_N907[3]_floating , \char_buf_reader_inst_N907[2]_floating , \char_buf_reader_inst_N907[1]_floating , \char_buf_reader_inst_N907[0]_floating }), .char_ascii (char_ascii), .char_pos_x (char_pos_x), .char_pos_y (char_pos_y), .char_row_index ({\char_buf_reader_inst_char_row_index[5]_floating , char_row_index[4], char_row_index[3], char_row_index[2], char_row_index[1], char_row_index[0]}), .ram_addr (ram_rd_addr), - .state_reg ({\char_buf_reader_inst_state_reg[4]_floating , \char_buf_reader_inst_state_reg[3]_floating , \char_buf_reader_inst_state_reg[2]_floating , \char_buf_reader_inst_state_reg[1]_floating , \char_buf_reader_inst/state_reg [0] }), + .state_reg ({\char_buf_reader_inst_state_reg[4]_floating , \char_buf_reader_inst_state_reg[3]_floating , \char_buf_reader_inst_state_reg[2]_floating , \char_buf_reader_inst/state_reg [1] , \char_buf_reader_inst/state_reg [0] }), .cfg_char_height (cfg_char_height), .cfg_char_width (cfg_char_width), .cfg_start_posX (cfg_start_posX), .cfg_start_posY (cfg_start_posY), .ram_data (ram_dout), - .N97 (\char_buf_reader_inst/N97 ), - ._N107128 (_N107128), + .N73 (\char_buf_reader_inst/N73 ), + ._N97124 (_N97124), .char_valid (char_valid), .\udp_osd_inst/char_osd_inst/char_ascii[0]_inv (\char_ascii[0]_inv ), .N714 (\char_buf_reader_inst/N714 ), @@ -326412,19 +325873,14 @@ module char_osd .char_pos_x (char_pos_x), .char_pos_y (char_pos_y), .char_row_index ({1'bx, char_row_index[4], char_row_index[3], char_row_index[2], char_row_index[1], char_row_index[0]}), - .\udp_osd_inst/char_osd_inst/char_buf_reader_inst/N907 ({1'bx, 1'bx, 1'bx, \char_buf_reader_inst/N907 [6] , 1'bx, 1'bx, 1'bx, \char_buf_reader_inst/N907 [2] , 1'bx, 1'bx}), - .\udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_reg ({1'bx, 1'bx, 1'bx, 1'bx, \char_buf_reader_inst/state_reg [0] }), .N41 (\char_pic_rom_inst/N41 ), .char_next (char_next), .m_row_pixels_valid (row_pixels_valid), - .\udp_osd_inst/char_osd_inst/char_buf_reader_inst/N714 (\char_buf_reader_inst/N714 ), - ._N107128 (_N107128), .char_valid (char_valid), .clk (clk), .m_row_pixels_ready (row_pixels_ready), .sync_vg_100m (sync_vg_100m), - .\udp_osd_inst/char_osd_inst/char_ascii[0]_inv (\char_ascii[0]_inv ), - .\udp_osd_inst/char_osd_inst/char_buf_reader_inst/N97 (\char_buf_reader_inst/N97 )); + .\udp_osd_inst/char_osd_inst/char_ascii[0]_inv (\char_ascii[0]_inv )); // ../../sources/designs/udp_osd/char_osd/char_osd.v:83 pixels_shifter pixels_shifter_inst ( @@ -326621,30 +326077,30 @@ module ipml_fifo_ctrl_v1_3_4_unq8 wire N168; wire N170; wire [12:0] \N170.co ; - wire _N14258; - wire _N14259; - wire _N14260; - wire _N14261; - wire _N14262; - wire _N14263; - wire _N14264; - wire _N14265; - wire _N14266; - wire _N14267; - wire _N14268; - wire _N15112; - wire _N15113; - wire _N15114; - wire _N15115; - wire _N15116; - wire _N15117; - wire _N15118; - wire _N15119; - wire _N15120; - wire _N15121; - wire _N15122; - wire _N108365; - wire _N108366; + wire _N15141; + wire _N15142; + wire _N15143; + wire _N15144; + wire _N15145; + wire _N15146; + wire _N15147; + wire _N15148; + wire _N15149; + wire _N15150; + wire _N15151; + wire _N15154; + wire _N15155; + wire _N15156; + wire _N15157; + wire _N15158; + wire _N15159; + wire _N15160; + wire _N15161; + wire _N15162; + wire _N15163; + wire _N15164; + wire _N109266; + wire _N109267; wire [11:0] rbin; wire rempty; wire [11:0] rgnext; @@ -327438,7 +326894,7 @@ module ipml_fifo_ctrl_v1_3_4_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_1 ( - .COUT (_N14258), + .COUT (_N15141), .Z (N2[0]), .CIN (), .I0 (w_en), @@ -327458,9 +326914,9 @@ module ipml_fifo_ctrl_v1_3_4_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_2 ( - .COUT (_N14259), + .COUT (_N15142), .Z (N2[1]), - .CIN (_N14258), + .CIN (_N15141), .I0 (w_en), .I1 (waddr[0]), .I2 (waddr[1]), @@ -327478,9 +326934,9 @@ module ipml_fifo_ctrl_v1_3_4_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_3 ( - .COUT (_N14260), + .COUT (_N15143), .Z (N2[2]), - .CIN (_N14259), + .CIN (_N15142), .I0 (), .I1 (waddr[2]), .I2 (), @@ -327498,9 +326954,9 @@ module ipml_fifo_ctrl_v1_3_4_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_4 ( - .COUT (_N14261), + .COUT (_N15144), .Z (N2[3]), - .CIN (_N14260), + .CIN (_N15143), .I0 (), .I1 (waddr[3]), .I2 (), @@ -327518,9 +326974,9 @@ module ipml_fifo_ctrl_v1_3_4_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_5 ( - .COUT (_N14262), + .COUT (_N15145), .Z (N2[4]), - .CIN (_N14261), + .CIN (_N15144), .I0 (), .I1 (waddr[4]), .I2 (), @@ -327538,9 +326994,9 @@ module ipml_fifo_ctrl_v1_3_4_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_6 ( - .COUT (_N14263), + .COUT (_N15146), .Z (N2[5]), - .CIN (_N14262), + .CIN (_N15145), .I0 (), .I1 (waddr[5]), .I2 (), @@ -327558,9 +327014,9 @@ module ipml_fifo_ctrl_v1_3_4_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_7 ( - .COUT (_N14264), + .COUT (_N15147), .Z (N2[6]), - .CIN (_N14263), + .CIN (_N15146), .I0 (), .I1 (waddr[6]), .I2 (), @@ -327578,9 +327034,9 @@ module ipml_fifo_ctrl_v1_3_4_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_8 ( - .COUT (_N14265), + .COUT (_N15148), .Z (N2[7]), - .CIN (_N14264), + .CIN (_N15147), .I0 (), .I1 (waddr[7]), .I2 (), @@ -327598,9 +327054,9 @@ module ipml_fifo_ctrl_v1_3_4_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_9 ( - .COUT (_N14266), + .COUT (_N15149), .Z (N2[8]), - .CIN (_N14265), + .CIN (_N15148), .I0 (), .I1 (waddr[8]), .I2 (), @@ -327618,9 +327074,9 @@ module ipml_fifo_ctrl_v1_3_4_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_10 ( - .COUT (_N14267), + .COUT (_N15150), .Z (N2[9]), - .CIN (_N14266), + .CIN (_N15149), .I0 (), .I1 (waddr[9]), .I2 (), @@ -327638,9 +327094,9 @@ module ipml_fifo_ctrl_v1_3_4_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_11 ( - .COUT (_N14268), + .COUT (_N15151), .Z (N2[10]), - .CIN (_N14267), + .CIN (_N15150), .I0 (), .I1 (waddr[10]), .I2 (), @@ -327660,7 +327116,7 @@ module ipml_fifo_ctrl_v1_3_4_unq8 N2_12 ( .COUT (), .Z (N2[11]), - .CIN (_N14268), + .CIN (_N15151), .I0 (), .I1 (wbin[11]), .I2 (), @@ -327684,7 +327140,7 @@ module ipml_fifo_ctrl_v1_3_4_unq8 GTP_LUT4 /* \N3[1]_1 */ #( .INIT(16'b1101100000100111)) \N3[1]_1 ( - .Z (_N108365), + .Z (_N109266), .I0 (wfull), .I1 (waddr[1]), .I2 (N2[1]), @@ -327725,7 +327181,7 @@ module ipml_fifo_ctrl_v1_3_4_unq8 GTP_LUT4 /* \N3[5]_1 */ #( .INIT(16'b1101100000100111)) \N3[5]_1 ( - .Z (_N108366), + .Z (_N109267), .I0 (wfull), .I1 (waddr[5]), .I2 (N2[5]), @@ -328006,7 +327462,7 @@ module ipml_fifo_ctrl_v1_3_4_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_1 ( - .COUT (_N15112), + .COUT (_N15154), .Z (N84[0]), .CIN (), .I0 (r_en), @@ -328026,9 +327482,9 @@ module ipml_fifo_ctrl_v1_3_4_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_2 ( - .COUT (_N15113), + .COUT (_N15155), .Z (N84[1]), - .CIN (_N15112), + .CIN (_N15154), .I0 (r_en), .I1 (raddr[0]), .I2 (raddr[1]), @@ -328046,9 +327502,9 @@ module ipml_fifo_ctrl_v1_3_4_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_3 ( - .COUT (_N15114), + .COUT (_N15156), .Z (N84[2]), - .CIN (_N15113), + .CIN (_N15155), .I0 (), .I1 (raddr[2]), .I2 (), @@ -328066,9 +327522,9 @@ module ipml_fifo_ctrl_v1_3_4_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_4 ( - .COUT (_N15115), + .COUT (_N15157), .Z (N84[3]), - .CIN (_N15114), + .CIN (_N15156), .I0 (), .I1 (raddr[3]), .I2 (), @@ -328086,9 +327542,9 @@ module ipml_fifo_ctrl_v1_3_4_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_5 ( - .COUT (_N15116), + .COUT (_N15158), .Z (N84[4]), - .CIN (_N15115), + .CIN (_N15157), .I0 (), .I1 (raddr[4]), .I2 (), @@ -328106,9 +327562,9 @@ module ipml_fifo_ctrl_v1_3_4_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_6 ( - .COUT (_N15117), + .COUT (_N15159), .Z (N84[5]), - .CIN (_N15116), + .CIN (_N15158), .I0 (), .I1 (raddr[5]), .I2 (), @@ -328126,9 +327582,9 @@ module ipml_fifo_ctrl_v1_3_4_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_7 ( - .COUT (_N15118), + .COUT (_N15160), .Z (N84[6]), - .CIN (_N15117), + .CIN (_N15159), .I0 (), .I1 (raddr[6]), .I2 (), @@ -328146,9 +327602,9 @@ module ipml_fifo_ctrl_v1_3_4_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_8 ( - .COUT (_N15119), + .COUT (_N15161), .Z (N84[7]), - .CIN (_N15118), + .CIN (_N15160), .I0 (), .I1 (raddr[7]), .I2 (), @@ -328166,9 +327622,9 @@ module ipml_fifo_ctrl_v1_3_4_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_9 ( - .COUT (_N15120), + .COUT (_N15162), .Z (N84[8]), - .CIN (_N15119), + .CIN (_N15161), .I0 (), .I1 (raddr[8]), .I2 (), @@ -328186,9 +327642,9 @@ module ipml_fifo_ctrl_v1_3_4_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_10 ( - .COUT (_N15121), + .COUT (_N15163), .Z (N84[9]), - .CIN (_N15120), + .CIN (_N15162), .I0 (), .I1 (raddr[9]), .I2 (), @@ -328206,9 +327662,9 @@ module ipml_fifo_ctrl_v1_3_4_unq8 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_11 ( - .COUT (_N15122), + .COUT (_N15164), .Z (N84[10]), - .CIN (_N15121), + .CIN (_N15163), .I0 (), .I1 (raddr[10]), .I2 (), @@ -328228,7 +327684,7 @@ module ipml_fifo_ctrl_v1_3_4_unq8 N84_12 ( .COUT (), .Z (N84[11]), - .CIN (_N15122), + .CIN (_N15164), .I0 (), .I1 (rbin[11]), .I2 (), @@ -328573,7 +328029,7 @@ module ipml_fifo_ctrl_v1_3_4_unq8 .I0 (wwptr[0]), .I1 (wrptr[0]), .I2 (wrptr[2]), - .I3 (_N108365), + .I3 (_N109266), .I4 (), .ID ()); // LUT = (~I0&~I1&I2&~I3)|(I0&I1&I2&~I3)|(~I0&~I1&~I2&I3)|(I0&I1&~I2&I3) ; @@ -328613,7 +328069,7 @@ module ipml_fifo_ctrl_v1_3_4_unq8 .I0 (wwptr[4]), .I1 (wrptr[4]), .I2 (wrptr[6]), - .I3 (_N108366), + .I3 (_N109267), .I4 (), .ID ()); // LUT = 1'b0 ; @@ -329248,35 +328704,31 @@ module arp_rx ( input [7:0] gmii_rxd_data, input [4:0] \udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt , - input [6:0] \udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg , input [4:0] \udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt , + input [6:0] \udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg , input [6:0] \udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/next_state , input N559, - input _N84201, - input _N96358, - input _N96693, - input _N96775, - input _N96776, - input _N108056, + input _N96653, + input _N97535, + input _N97539, + input _N97540, input clk, input gmii_rxd_valid, input sync_vg_100m, - input \udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/error_en , - input \udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/skip_en , + input \udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/error_en , + input \udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/skip_en , output [4:0] cnt, output [31:0] src_ip, output [47:0] src_mac, output N52, output N366, - output _N95922, - output _N95923, - output _N95925, - output _N96007, - output _N96085, - output _N96096, - output _N96556, - output _N97006, - output _N97473, + output _N97121, + output _N97122, + output _N97327, + output _N97338, + output _N97341, + output _N97887, + output _N98258, output arp_rx_done, output arp_rx_type, output \udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N586 @@ -329295,7 +328747,6 @@ module arp_rx wire N419; wire N422; wire N446; - wire N446_cpy; wire N563; wire [4:0] N566; wire N639; @@ -329309,59 +328760,61 @@ module arp_rx wire N847; wire N866; wire N1057; - wire _N4998; + wire _N5481; wire _N18413; - wire _N22378; - wire _N23306; - wire _N23308; - wire _N23311; - wire _N23312; - wire _N83294; - wire _N96226; - wire _N96803; - wire _N97436; - wire _N97485; - wire _N107311; - wire _N107315; - wire _N107316; - wire _N107326; - wire _N107330; - wire _N107334; - wire _N107338; - wire _N107342; - wire _N107346; - wire _N107350; - wire _N107358; - wire _N107371; - wire _N107373; - wire _N107375; - wire _N107382; - wire _N107386; - wire _N107390; - wire _N107394; - wire _N107398; - wire _N107402; - wire _N107404; - wire _N107409; - wire _N107416; - wire _N107420; - wire _N107424; - wire _N107428; - wire _N107432; - wire _N107436; - wire _N107438; - wire _N107443; - wire _N107445; - wire _N107453; - wire _N107457; - wire _N107462; - wire _N107475; - wire _N107476; - wire _N107477; - wire _N108081; - wire _N108082; - wire _N108386; - wire _N108387; + wire _N24272; + wire _N25486; + wire _N25488; + wire _N25491; + wire _N25492; + wire _N84898; + wire _N97222; + wire _N97717; + wire _N98228; + wire _N98265; + wire _N108141; + wire _N108144; + wire _N108145; + wire _N108155; + wire _N108159; + wire _N108163; + wire _N108167; + wire _N108171; + wire _N108175; + wire _N108179; + wire _N108187; + wire _N108200; + wire _N108202; + wire _N108204; + wire _N108211; + wire _N108215; + wire _N108219; + wire _N108223; + wire _N108227; + wire _N108231; + wire _N108233; + wire _N108238; + wire _N108245; + wire _N108249; + wire _N108253; + wire _N108257; + wire _N108261; + wire _N108265; + wire _N108267; + wire _N108272; + wire _N108274; + wire _N108282; + wire _N108286; + wire _N108291; + wire _N108304; + wire _N108305; + wire _N108306; + wire _N108892; + wire _N108893; + wire _N108916; + wire _N108917; + wire _N109272; + wire _N109273; wire [4:0] cur_state_reg; wire [31:0] des_ip_t; wire [47:0] des_mac_t; @@ -329377,7 +328830,7 @@ module arp_rx .INIT(16'b0000000000001000)) N52_vname ( .Z (N52), - .I0 (_N97473), + .I0 (_N98258), .I1 (gmii_rxd_valid), .I2 (gmii_rxd_data[5]), .I3 (gmii_rxd_data[7])); @@ -329388,23 +328841,23 @@ module arp_rx GTP_LUT3 /* N58_ac2 */ #( .INIT(8'b10000000)) N58_ac2 ( - .Z (_N4998), + .Z (_N5481), .I0 (cnt[0]), .I1 (cnt[1]), .I2 (cnt[2])); // LUT = I0&I1&I2 ; GTP_LUT5M /* N60_mux3_1 */ #( - .INIT(32'b00000001000000011010101010101011)) + .INIT(32'b00000101000000000000101100000000)) N60_mux3_1 ( - .Z (_N96007), - .I0 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg [1] ), - .I1 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg [3] ), - .I2 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg [2] ), - .I3 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg [4] ), - .I4 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/skip_en ), - .ID (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/error_en )); - // LUT = (~I1&~I2&~I3&~I4)|(ID&~I4)|(~I0&~I1&~I2&I4) ; + .Z (_N97341), + .I0 (\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg [6] ), + .I1 (\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg [1] ), + .I2 (\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg [0] ), + .I3 (_N96653), + .I4 (\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/skip_en ), + .ID (\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/error_en )); + // LUT = (~I1&~I2&I3&~I4)|(ID&~I2&I3&~I4)|(~I0&~I2&I3&I4) ; GTP_LUT4 /* N60_mux3_5 */ #( .INIT(16'b0000000000000111)) @@ -329420,7 +328873,7 @@ module arp_rx .INIT(32'b11111111110111111111110100000000)) N78_vname ( .Z (N78), - .I0 (_N97473), + .I0 (_N98258), .I1 (gmii_rxd_data[5]), .I2 (gmii_rxd_data[7]), .I3 (N60), @@ -329429,41 +328882,41 @@ module arp_rx // LUT = (~I2&I4)|(~I0&I3)|(~I0&I4)|(I1&I3)|(I1&I4)|(I2&I3) ; // ../../sources/designs/udp_osd/eth_udp/arp/arp_rx.v:151 - GTP_LUT4 /* N114_4 */ #( + GTP_LUT4 /* N114_5 */ #( .INIT(16'b0000001000000000)) - N114_4 ( - .Z (_N97006), + N114_5 ( + .Z (_N97887), .I0 (gmii_rxd_data[0]), .I1 (gmii_rxd_data[1]), .I2 (gmii_rxd_data[3]), .I3 (gmii_rxd_data[4])); // LUT = I0&~I1&~I2&I3 ; - GTP_LUT4 /* N114_19 */ #( - .INIT(16'b0000000000000001)) - N114_19 ( - .Z (_N107311), + GTP_LUT4 /* N114_21 */ #( + .INIT(16'b0000000000000010)) + N114_21 ( + .Z (_N108141), + .I0 (eth_type[11]), + .I1 (eth_type[13]), + .I2 (eth_type[14]), + .I3 (eth_type[15])); + // LUT = I0&~I1&~I2&~I3 ; + + GTP_LUT5 /* N114_24 */ #( + .INIT(32'b00000000000000010000000000000000)) + N114_24 ( + .Z (_N108144), .I0 (eth_type[8]), .I1 (eth_type[9]), .I2 (eth_type[10]), - .I3 (eth_type[12])); - // LUT = ~I0&~I1&~I2&~I3 ; - - GTP_LUT5 /* N114_23 */ #( - .INIT(32'b00000000000000000000000000001000)) - N114_23 ( - .Z (_N107315), - .I0 (_N107311), - .I1 (eth_type[11]), - .I2 (eth_type[13]), - .I3 (eth_type[14]), - .I4 (eth_type[15])); - // LUT = I0&I1&~I2&~I3&~I4 ; + .I3 (eth_type[12]), + .I4 (_N108141)); + // LUT = ~I0&~I1&~I2&~I3&I4 ; - GTP_LUT5 /* N114_24 */ #( + GTP_LUT5 /* N114_25 */ #( .INIT(32'b00000000000000000000000000001000)) - N114_24 ( - .Z (_N107316), + N114_25 ( + .Z (_N108145), .I0 (gmii_rxd_data[1]), .I1 (gmii_rxd_data[2]), .I2 (gmii_rxd_data[5]), @@ -329471,44 +328924,71 @@ module arp_rx .I4 (gmii_rxd_data[7])); // LUT = I0&I1&~I2&~I3&~I4 ; - GTP_LUT5 /* N114_26 */ #( + GTP_LUT5 /* N114_27 */ #( .INIT(32'b00000001000000000000000000000000)) - N114_26 ( + N114_27 ( .Z (N114), .I0 (gmii_rxd_data[0]), .I1 (gmii_rxd_data[3]), .I2 (gmii_rxd_data[4]), - .I3 (_N107315), - .I4 (_N107316)); + .I3 (_N108144), + .I4 (_N108145)); // LUT = ~I0&~I1&~I2&I3&I4 ; GTP_LUT5 /* N127_1_2 */ #( .INIT(32'b00101010101010101010101010101010)) N127_1_2 ( - .Z (_N107445), + .Z (_N108274), .I0 (N364), - .I1 (_N107416), - .I2 (_N107420), - .I3 (_N107438), - .I4 (_N107443)); + .I1 (_N108245), + .I2 (_N108249), + .I3 (_N108267), + .I4 (_N108272)); // LUT = (I0&~I4)|(I0&~I3)|(I0&~I2)|(I0&~I1) ; GTP_LUT5 /* N127_1_3 */ #( .INIT(32'b01111111111111110000000000000000)) N127_1_3 ( - .Z (_N22378), - .I0 (_N107382), - .I1 (_N107386), - .I2 (_N107404), - .I3 (_N107409), - .I4 (_N107445)); + .Z (_N24272), + .I0 (_N108211), + .I1 (_N108215), + .I2 (_N108233), + .I3 (_N108238), + .I4 (_N108274)); // LUT = (~I3&I4)|(~I2&I4)|(~I1&I4)|(~I0&I4) ; + GTP_LUT3 /* N127_3 */ #( + .INIT(8'b00000001)) + N127_3 ( + .Z (_N97121), + .I0 (\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt [0] ), + .I1 (\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt [3] ), + .I2 (\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt [4] )); + // LUT = ~I0&~I1&~I2 ; + + GTP_LUT3 /* N127_4 */ #( + .INIT(8'b00000010)) + N127_4 ( + .Z (_N97122), + .I0 (\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt [0] ), + .I1 (\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt [3] ), + .I2 (\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt [4] )); + // LUT = I0&~I1&~I2 ; + + GTP_LUT3 /* N163_mux2_1 */ #( + .INIT(8'b00000001)) + N163_mux2_1 ( + .Z (_N97338), + .I0 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt [2] ), + .I1 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt [3] ), + .I2 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt [4] )); + // LUT = ~I0&~I1&~I2 ; + GTP_LUT3 /* N186 */ #( .INIT(8'b00101000)) N186_vname ( .Z (N186), - .I0 (_N97485), + .I0 (_N98265), .I1 (op_data[0]), .I2 (op_data[1])); // defparam N186_vname.orig_name = N186; @@ -329519,42 +328999,33 @@ module arp_rx .INIT(8'b11110111)) N195_1 ( .Z (N195), - .I0 (_N97485), + .I0 (_N98265), .I1 (op_data[0]), .I2 (op_data[1])); // LUT = (~I1)|(~I0)|(I2) ; - GTP_LUT3 /* N289_1 */ #( - .INIT(8'b00000001)) - N289_1 ( - .Z (_N96096), - .I0 (\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt [0] ), - .I1 (\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt [3] ), - .I2 (\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt [4] )); - // LUT = ~I0&~I1&~I2 ; - - GTP_LUT3 /* N289_7 */ #( + GTP_LUT3 /* N289_6 */ #( .INIT(8'b10000000)) - N289_7 ( - .Z (_N107358), + N289_6 ( + .Z (_N108187), .I0 (gmii_rxd_valid), .I1 (N422), - .I2 (N446_cpy)); + .I2 (N446)); // LUT = I0&I1&I2 ; GTP_LUT3 /* N310_7_3 */ #( .INIT(8'b10000000)) N310_7_3 ( - .Z (_N23306), - .I0 (_N96226), - .I1 (_N96693), + .Z (_N25486), + .I0 (_N97222), + .I1 (_N97535), .I2 (N364)); // LUT = I0&I1&I2 ; GTP_LUT5 /* N310_9_4 */ #( .INIT(32'b00000000000000000000000010000000)) N310_9_4 ( - .Z (_N23308), + .Z (_N25488), .I0 (gmii_rxd_valid), .I1 (N114), .I2 (N406), @@ -329563,52 +329034,43 @@ module arp_rx // LUT = I0&I1&I2&~I3&~I4 ; GTP_LUT5M /* N310_12 */ #( - .INIT(32'b00000000101000000001000100000000)) + .INIT(32'b00001000000010000000000001010000)) N310_12 ( - .Z (_N23311), - .I0 (_N107358), - .I1 (skip_en), - .I2 (N186), - .I3 (next_state[4]), + .Z (_N25491), + .I0 (_N108187), + .I1 (N186), + .I2 (next_state[4]), + .I3 (skip_en), .I4 (next_state[3]), .ID (gmii_rxd_valid)); - // LUT = (~ID&~I1&I3&~I4)|(I0&I2&~I3&I4) ; + // LUT = (~ID&I2&~I3&~I4)|(I0&I1&~I2&I4) ; GTP_MUX2LUT6 N310_13 ( - .Z (_N23312), - .I0 (_N23311), - .I1 (_N23308), + .Z (_N25492), + .I0 (_N25491), + .I1 (_N25488), .S (next_state[2])); GTP_LUT5M /* N310_15 */ #( - .INIT(32'b00001010000010101100101000001010)) + .INIT(32'b00000000100010001111000010101010)) N310_15 ( .Z (N310), - .I0 (_N23306), + .I0 (_N97222), .I1 (N52), - .I2 (next_state[0]), - .I3 (_N96226), - .I4 (next_state[1]), - .ID (_N23312)); - // LUT = (I1&I2&I3&~I4)|(ID&~I2&~I4)|(I0&~I2&I4) ; - - GTP_LUT3 /* N310_16 */ #( - .INIT(8'b00000001)) - N310_16 ( - .Z (_N96085), - .I0 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt [0] ), - .I1 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt [3] ), - .I2 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt [4] )); - // LUT = ~I0&~I1&~I2 ; + .I2 (_N25486), + .I3 (next_state[1]), + .I4 (next_state[0]), + .ID (_N25492)); + // LUT = (ID&~I3&~I4)|(I2&I3&~I4)|(I0&I1&~I3&I4) ; - GTP_LUT5M /* N310_18 */ #( + GTP_LUT5M /* N310_16 */ #( .INIT(32'b00000001000000010000101000001011)) - N310_18 ( - .Z (_N96803), - .I0 (cur_state_reg[4]), - .I1 (cur_state_reg[1]), - .I2 (cur_state_reg[0]), - .I3 (cur_state_reg[2]), + N310_16 ( + .Z (_N97222), + .I0 (cur_state_reg[1]), + .I1 (cur_state_reg[2]), + .I2 (next_state[4]), + .I3 (cur_state_reg[3]), .I4 (skip_en), .ID (error_en)); // LUT = (~I1&~I2&~I3&~I4)|(ID&~I2&~I4)|(~I0&~I1&~I2&I4) ; @@ -329620,59 +329082,45 @@ module arp_rx .I0 (N114), .I1 (N366), .I2 (gmii_rxd_valid), - .I3 (_N107453), + .I3 (_N108282), .I4 (N406), - .ID (_N22378)); + .ID (_N24272)); // LUT = (ID&I1&I2&~I4)|(~I0&I1&I2&I4)|(I2&I3) ; GTP_LUT5 /* \N312_1_or[0]_2_2 */ #( .INIT(32'b10111010101010101111101010101010)) \N312_1_or[0]_2_2 ( - .Z (_N107453), - .I0 (_N83294), + .Z (_N108282), + .I0 (_N84898), .I1 (N186), .I2 (N419), .I3 (N422), - .I4 (N446_cpy)); + .I4 (N446)); // LUT = (I0)|(I2&I3&~I4)|(~I1&I2&I3) ; GTP_LUT2 /* \N312_1_or[0]_3 */ #( .INIT(4'b1000)) \N312_1_or[0]_3 ( - .Z (_N83294), + .Z (_N84898), .I0 (N78), .I1 (N359)); // LUT = I0&I1 ; - GTP_LUT5M /* \N312_1_or[0]_7 */ #( - .INIT(32'b00000001000000010000101000001011)) - \N312_1_or[0]_7 ( - .Z (_N96226), - .I0 (cur_state_reg[1]), - .I1 (cur_state_reg[2]), - .I2 (next_state[4]), - .I3 (cur_state_reg[3]), - .I4 (skip_en), - .ID (error_en)); - // LUT = (~I1&~I2&~I3&~I4)|(ID&~I2&~I4)|(~I0&~I1&~I2&I4) ; - - GTP_LUT5 /* N319_3 */ #( - .INIT(32'b10000000000000000000000000000000)) - N319_3 ( + GTP_LUT3 /* N319_2 */ #( + .INIT(8'b10000000)) + N319_2 ( .Z (N319), - .I0 (gmii_rxd_valid), - .I1 (N186), - .I2 (N419), - .I3 (N422), - .I4 (N446)); - // LUT = I0&I1&I2&I3&I4 ; + .I0 (N186), + .I1 (N419), + .I2 (_N108187)); + // LUT = I0&I1&I2 ; // ../../sources/designs/udp_osd/eth_udp/arp/arp_rx.v:140 GTP_LUT3 /* N357_4 */ #( .INIT(8'b10000000)) N357_4 ( - .Z (_N97473), - .I0 (_N97006), + .Z (_N98258), + .I0 (_N97887), .I1 (gmii_rxd_data[2]), .I2 (gmii_rxd_data[6])); // LUT = I0&I1&I2 ; @@ -329684,7 +329132,7 @@ module arp_rx .I0 (cur_state_reg[4]), .I1 (cur_state_reg[1]), .I2 (cur_state_reg[0]), - .I3 (_N96226), + .I3 (_N97222), .I4 (skip_en), .ID (error_en)); // LUT = (~ID&I1&~I2&I3&~I4)|(~I0&I2&I3&I4) ; @@ -329702,6 +329150,18 @@ module arp_rx // LUT = ~I0&I1&I2&~I3&~I4 ; // ../../sources/designs/udp_osd/eth_udp/arp/arp_rx.v:151 + GTP_LUT5M /* N366_1 */ #( + .INIT(32'b00000001000000010000101000001011)) + N366_1 ( + .Z (_N97717), + .I0 (cur_state_reg[4]), + .I1 (cur_state_reg[1]), + .I2 (cur_state_reg[0]), + .I3 (cur_state_reg[2]), + .I4 (skip_en), + .ID (error_en)); + // LUT = (~I1&~I2&~I3&~I4)|(ID&~I2&~I4)|(~I0&~I1&~I2&I4) ; + GTP_LUT5 /* N366_5 */ #( .INIT(32'b00000000000000000000000000010000)) N366_5 ( @@ -329716,7 +329176,7 @@ module arp_rx GTP_LUT4 /* N402_1 */ #( .INIT(16'b0000000000000001)) N402_1 ( - .Z (_N96556), + .Z (_N97327), .I0 (gmii_rxd_data[2]), .I1 (gmii_rxd_data[5]), .I2 (gmii_rxd_data[6]), @@ -329726,7 +329186,7 @@ module arp_rx GTP_LUT4 /* N402_47 */ #( .INIT(16'b1000000000000000)) N402_47 ( - .Z (_N107371), + .Z (_N108200), .I0 (des_mac_t[0]), .I1 (des_mac_t[2]), .I2 (des_mac_t[4]), @@ -329736,7 +329196,7 @@ module arp_rx GTP_LUT4 /* N402_49 */ #( .INIT(16'b1000000000000000)) N402_49 ( - .Z (_N107373), + .Z (_N108202), .I0 (des_mac_t[20]), .I1 (des_mac_t[21]), .I2 (des_mac_t[25]), @@ -329746,28 +329206,28 @@ module arp_rx GTP_LUT5 /* N402_51 */ #( .INIT(32'b10000000000000000000000000000000)) N402_51 ( - .Z (_N107375), + .Z (_N108204), .I0 (des_mac_t[10]), .I1 (des_mac_t[14]), .I2 (des_mac_t[16]), .I3 (des_mac_t[17]), - .I4 (_N107373)); + .I4 (_N108202)); // LUT = I0&I1&I2&I3&I4 ; GTP_LUT4 /* N402_52 */ #( .INIT(16'b1000000000000000)) N402_52 ( - .Z (_N97436), + .Z (_N98228), .I0 (des_mac_t[32]), .I1 (des_mac_t[36]), - .I2 (_N107371), - .I3 (_N107375)); + .I2 (_N108200), + .I3 (_N108204)); // LUT = I0&I1&I2&I3 ; GTP_LUT5 /* N402_58 */ #( .INIT(32'b00000000000000000000000000000001)) N402_58 ( - .Z (_N107416), + .Z (_N108245), .I0 (des_mac_t[43]), .I1 (des_mac_t[44]), .I2 (des_mac_t[45]), @@ -329778,7 +329238,7 @@ module arp_rx GTP_LUT5 /* N402_62 */ #( .INIT(32'b00000000000000000000000000000001)) N402_62 ( - .Z (_N107420), + .Z (_N108249), .I0 (des_mac_t[1]), .I1 (des_mac_t[3]), .I2 (des_mac_t[5]), @@ -329789,7 +329249,7 @@ module arp_rx GTP_LUT5 /* N402_66 */ #( .INIT(32'b00000000000000000000000000000001)) N402_66 ( - .Z (_N107424), + .Z (_N108253), .I0 (des_mac_t[9]), .I1 (des_mac_t[11]), .I2 (des_mac_t[12]), @@ -329800,7 +329260,7 @@ module arp_rx GTP_LUT5 /* N402_70 */ #( .INIT(32'b00000000000000000000000000000001)) N402_70 ( - .Z (_N107428), + .Z (_N108257), .I0 (des_mac_t[18]), .I1 (des_mac_t[19]), .I2 (des_mac_t[22]), @@ -329811,7 +329271,7 @@ module arp_rx GTP_LUT5 /* N402_74 */ #( .INIT(32'b00000000000000000000000000000001)) N402_74 ( - .Z (_N107432), + .Z (_N108261), .I0 (des_mac_t[26]), .I1 (des_mac_t[27]), .I2 (des_mac_t[28]), @@ -329822,7 +329282,7 @@ module arp_rx GTP_LUT5 /* N402_78 */ #( .INIT(32'b00000000000000000000000000000001)) N402_78 ( - .Z (_N107436), + .Z (_N108265), .I0 (des_mac_t[33]), .I1 (des_mac_t[34]), .I2 (des_mac_t[35]), @@ -329833,8 +329293,8 @@ module arp_rx GTP_LUT5 /* N402_80 */ #( .INIT(32'b00000000000000000000000000000010)) N402_80 ( - .Z (_N107438), - .I0 (_N97436), + .Z (_N108267), + .I0 (_N98228), .I1 (des_mac_t[39]), .I2 (des_mac_t[40]), .I3 (des_mac_t[41]), @@ -329844,17 +329304,17 @@ module arp_rx GTP_LUT4 /* N402_85 */ #( .INIT(16'b1000000000000000)) N402_85 ( - .Z (_N107443), - .I0 (_N107424), - .I1 (_N107428), - .I2 (_N107432), - .I3 (_N107436)); + .Z (_N108272), + .I0 (_N108253), + .I1 (_N108257), + .I2 (_N108261), + .I3 (_N108265)); // LUT = I0&I1&I2&I3 ; GTP_LUT5 /* N403_42 */ #( .INIT(32'b10000000000000000000000000000000)) N403_42 ( - .Z (_N107382), + .Z (_N108211), .I0 (des_mac_t[43]), .I1 (des_mac_t[44]), .I2 (des_mac_t[45]), @@ -329865,7 +329325,7 @@ module arp_rx GTP_LUT5 /* N403_46 */ #( .INIT(32'b10000000000000000000000000000000)) N403_46 ( - .Z (_N107386), + .Z (_N108215), .I0 (des_mac_t[1]), .I1 (des_mac_t[3]), .I2 (des_mac_t[5]), @@ -329876,7 +329336,7 @@ module arp_rx GTP_LUT5 /* N403_50 */ #( .INIT(32'b10000000000000000000000000000000)) N403_50 ( - .Z (_N107390), + .Z (_N108219), .I0 (des_mac_t[9]), .I1 (des_mac_t[11]), .I2 (des_mac_t[12]), @@ -329887,7 +329347,7 @@ module arp_rx GTP_LUT5 /* N403_54 */ #( .INIT(32'b10000000000000000000000000000000)) N403_54 ( - .Z (_N107394), + .Z (_N108223), .I0 (des_mac_t[18]), .I1 (des_mac_t[19]), .I2 (des_mac_t[22]), @@ -329898,7 +329358,7 @@ module arp_rx GTP_LUT5 /* N403_58 */ #( .INIT(32'b10000000000000000000000000000000)) N403_58 ( - .Z (_N107398), + .Z (_N108227), .I0 (des_mac_t[26]), .I1 (des_mac_t[27]), .I2 (des_mac_t[28]), @@ -329909,7 +329369,7 @@ module arp_rx GTP_LUT5 /* N403_62 */ #( .INIT(32'b10000000000000000000000000000000)) N403_62 ( - .Z (_N107402), + .Z (_N108231), .I0 (des_mac_t[33]), .I1 (des_mac_t[34]), .I2 (des_mac_t[35]), @@ -329920,8 +329380,8 @@ module arp_rx GTP_LUT5 /* N403_64 */ #( .INIT(32'b10000000000000000000000000000000)) N403_64 ( - .Z (_N107404), - .I0 (_N97436), + .Z (_N108233), + .I0 (_N98228), .I1 (des_mac_t[39]), .I2 (des_mac_t[40]), .I3 (des_mac_t[41]), @@ -329931,11 +329391,11 @@ module arp_rx GTP_LUT4 /* N403_69 */ #( .INIT(16'b1000000000000000)) N403_69 ( - .Z (_N107409), - .I0 (_N107390), - .I1 (_N107394), - .I2 (_N107398), - .I3 (_N107402)); + .Z (_N108238), + .I0 (_N108219), + .I1 (_N108223), + .I2 (_N108227), + .I3 (_N108231)); // LUT = I0&I1&I2&I3 ; GTP_LUT5 /* N406 */ #( @@ -329956,16 +329416,16 @@ module arp_rx N419_3 ( .Z (N419), .I0 (cur_state_reg[2]), - .I1 (_N96803), + .I1 (_N97717), .I2 (next_state[4]), .I3 (cur_state_reg[3]), .I4 (skip_en), .ID (error_en)); // LUT = (~ID&I1&~I2&I3&~I4)|(I0&I1&~I2&I4) ; - GTP_LUT5 /* N422_4 */ #( + GTP_LUT5 /* N422_8 */ #( .INIT(32'b00010000000000000000000000000000)) - N422_4 ( + N422_8 ( .Z (N422), .I0 (cnt[0]), .I1 (cnt[1]), @@ -329974,20 +329434,20 @@ module arp_rx .I4 (cnt[4])); // LUT = ~I0&~I1&I2&I3&I4 ; - GTP_LUT4 /* N446_36 */ #( + GTP_LUT4 /* N446_35 */ #( .INIT(16'b0000000000000001)) - N446_36 ( - .Z (_N107326), + N446_35 ( + .Z (_N108155), .I0 (des_ip_t[24]), .I1 (des_ip_t[25]), .I2 (des_ip_t[26]), .I3 (des_ip_t[27])); // LUT = ~I0&~I1&~I2&~I3 ; - GTP_LUT5 /* N446_40 */ #( + GTP_LUT5 /* N446_39 */ #( .INIT(32'b00000001000000000000000000000000)) - N446_40 ( - .Z (_N107330), + N446_39 ( + .Z (_N108159), .I0 (des_ip_t[0]), .I1 (des_ip_t[28]), .I2 (des_ip_t[29]), @@ -329995,10 +329455,10 @@ module arp_rx .I4 (des_ip_t[31])); // LUT = ~I0&~I1&~I2&I3&I4 ; - GTP_LUT5 /* N446_44 */ #( + GTP_LUT5 /* N446_43 */ #( .INIT(32'b00000000000000000000000000000001)) - N446_44 ( - .Z (_N107334), + N446_43 ( + .Z (_N108163), .I0 (des_ip_t[2]), .I1 (des_ip_t[4]), .I2 (des_ip_t[5]), @@ -330006,10 +329466,10 @@ module arp_rx .I4 (des_ip_t[7])); // LUT = ~I0&~I1&~I2&~I3&~I4 ; - GTP_LUT5 /* N446_48 */ #( + GTP_LUT5 /* N446_47 */ #( .INIT(32'b00000000000000000000000000000001)) - N446_48 ( - .Z (_N107338), + N446_47 ( + .Z (_N108167), .I0 (des_ip_t[8]), .I1 (des_ip_t[10]), .I2 (des_ip_t[12]), @@ -330017,10 +329477,10 @@ module arp_rx .I4 (des_ip_t[14])); // LUT = ~I0&~I1&~I2&~I3&~I4 ; - GTP_LUT5 /* N446_52 */ #( + GTP_LUT5 /* N446_51 */ #( .INIT(32'b00000000000000000000000000000001)) - N446_52 ( - .Z (_N107342), + N446_51 ( + .Z (_N108171), .I0 (des_ip_t[15]), .I1 (des_ip_t[16]), .I2 (des_ip_t[17]), @@ -330028,10 +329488,10 @@ module arp_rx .I4 (des_ip_t[20])); // LUT = ~I0&~I1&~I2&~I3&~I4 ; - GTP_LUT5 /* N446_56 */ #( + GTP_LUT5 /* N446_55 */ #( .INIT(32'b00000000000000001000000000000000)) - N446_56 ( - .Z (_N107346), + N446_55 ( + .Z (_N108175), .I0 (des_ip_t[1]), .I1 (des_ip_t[3]), .I2 (des_ip_t[9]), @@ -330039,43 +329499,32 @@ module arp_rx .I4 (des_ip_t[22])); // LUT = I0&I1&I2&I3&~I4 ; - GTP_LUT5 /* N446_60 */ #( + GTP_LUT5 /* N446_59 */ #( .INIT(32'b10000000000000000000000000000000)) - N446_60 ( - .Z (_N107350), + N446_59 ( + .Z (_N108179), .I0 (des_ip_t[19]), .I1 (des_ip_t[21]), .I2 (des_ip_t[23]), - .I3 (_N107326), - .I4 (_N107330)); + .I3 (_N108155), + .I4 (_N108159)); // LUT = I0&I1&I2&I3&I4 ; - GTP_LUT5 /* N446_64 */ #( + GTP_LUT5 /* N446_63 */ #( .INIT(32'b10000000000000000000000000000000)) - N446_64 ( + N446_63 ( .Z (N446), - .I0 (_N107334), - .I1 (_N107338), - .I2 (_N107342), - .I3 (_N107346), - .I4 (_N107350)); - // LUT = I0&I1&I2&I3&I4 ; - - GTP_LUT5 /* N446_64_cpy */ #( - .INIT(32'b10000000000000000000000000000000)) - N446_64_cpy ( - .Z (N446_cpy), - .I0 (_N107334), - .I1 (_N107338), - .I2 (_N107342), - .I3 (_N107346), - .I4 (_N107350)); + .I0 (_N108163), + .I1 (_N108167), + .I2 (_N108171), + .I3 (_N108175), + .I4 (_N108179)); // LUT = I0&I1&I2&I3&I4 ; GTP_LUT4 /* N462_23 */ #( .INIT(16'b0000000000000001)) N462_23 ( - .Z (_N107475), + .Z (_N108304), .I0 (op_data[2]), .I1 (op_data[3]), .I2 (op_data[4]), @@ -330085,7 +329534,7 @@ module arp_rx GTP_LUT4 /* N462_24 */ #( .INIT(16'b0000000000000001)) N462_24 ( - .Z (_N107476), + .Z (_N108305), .I0 (op_data[6]), .I1 (op_data[7]), .I2 (op_data[8]), @@ -330095,7 +329544,7 @@ module arp_rx GTP_LUT4 /* N462_25 */ #( .INIT(16'b0000000000000001)) N462_25 ( - .Z (_N107477), + .Z (_N108306), .I0 (op_data[10]), .I1 (op_data[11]), .I2 (op_data[12]), @@ -330105,18 +329554,29 @@ module arp_rx GTP_LUT5 /* N462_28 */ #( .INIT(32'b00010000000000000000000000000000)) N462_28 ( - .Z (_N97485), + .Z (_N98265), .I0 (op_data[14]), .I1 (op_data[15]), - .I2 (_N107475), - .I3 (_N107476), - .I4 (_N107477)); + .I2 (_N108304), + .I3 (_N108305), + .I4 (_N108306)); // LUT = ~I0&~I1&I2&I3&I4 ; + GTP_LUT5 /* N466_9 */ #( + .INIT(32'b00000000000010000000000000000000)) + N466_9 ( + .Z (\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N586 ), + .I0 (_N97341), + .I1 (gmii_rxd_valid), + .I2 (\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/next_state [2] ), + .I3 (\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/next_state [3] ), + .I4 (\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/next_state [4] )); + // LUT = I0&I1&~I2&~I3&I4 ; + GTP_LUT3 /* N563_3 */ #( .INIT(8'b10101000)) N563_3 ( - .Z (_N107462), + .Z (_N108291), .I0 (gmii_rxd_valid), .I1 (N359), .I2 (N419)); @@ -330126,11 +329586,11 @@ module arp_rx .INIT(32'b11111111111111111100111011001100)) N563_4 ( .Z (N563), - .I0 (_N96803), + .I0 (_N97717), .I1 (N559), .I2 (next_state[3]), .I3 (next_state[4]), - .I4 (_N107462)); + .I4 (_N108291)); // LUT = (I1)|(I4)|(I0&~I2&I3) ; GTP_LUT2 /* \N566_12_and[0][1]_1 */ #( @@ -330175,7 +329635,7 @@ module arp_rx .INIT(16'b0100110010000000)) \N566_12_and[4][1]_1 ( .Z (N566[4]), - .I0 (_N4998), + .I0 (_N5481), .I1 (_N18413), .I2 (cnt[3]), .I3 (cnt[4])); @@ -330184,7 +329644,7 @@ module arp_rx GTP_LUT5 /* N566_14_2 */ #( .INIT(32'b00110011101100110000000010100000)) N566_14_2 ( - .Z (_N107457), + .Z (_N108286), .I0 (gmii_rxd_valid), .I1 (N406), .I2 (N419), @@ -330199,30 +329659,31 @@ module arp_rx .I0 (gmii_rxd_valid), .I1 (N359), .I2 (N364), - .I3 (_N107457)); + .I3 (_N108286)); // LUT = (I3)|(I0&I1&~I2) ; - GTP_LUT5 /* N635_1 */ #( - .INIT(32'b00000000000000010000000011001101)) - N635_1 ( - .Z (_N95922), - .I0 (_N84201), - .I1 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/skip_en ), - .I2 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg [6] ), - .I3 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg [5] ), - .I4 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg [4] )); - // LUT = (I1&~I3&~I4)|(~I0&~I1&~I2&~I3) ; + GTP_LUT5 /* N635_2 */ #( + .INIT(32'b00000000000000000000000000101010)) + N635_2 ( + .Z (_N108893), + .I0 (gmii_rxd_valid), + .I1 (cnt[1]), + .I2 (cnt[2]), + .I3 (cnt[3]), + .I4 (cnt[4])); + // LUT = (I0&~I2&~I3&~I4)|(I0&~I1&~I3&~I4) ; - GTP_LUT4 /* N639 */ #( - .INIT(16'b1111100011110000)) + GTP_LUT5 /* N639 */ #( + .INIT(32'b11101100110011001010000000000000)) N639_vname ( .Z (N639), - .I0 (gmii_rxd_valid), - .I1 (N60), - .I2 (N319), - .I3 (N366)); + .I0 (N186), + .I1 (N366), + .I2 (N419), + .I3 (_N108187), + .I4 (_N108893)); // defparam N639_vname.orig_name = N639; - // LUT = (I2)|(I0&I1&I3) ; + // LUT = (I1&I4)|(I0&I2&I3) ; // ../../sources/designs/udp_osd/eth_udp/arp/arp_rx.v:140 GTP_LUT2 /* \N642_1[0] */ #( @@ -330657,25 +330118,26 @@ module arp_rx // LUT = ~I0&I1 ; // ../../sources/designs/udp_osd/eth_udp/arp/arp_rx.v:140 - GTP_LUT2 /* N703_1 */ #( - .INIT(4'b0001)) - N703_1 ( - .Z (_N95923), - .I0 (\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt [3] ), - .I1 (\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt [4] )); - // LUT = ~I0&~I1 ; + GTP_LUT4 /* N703_4 */ #( + .INIT(16'b0010000000000000)) + N703_4 ( + .Z (_N108892), + .I0 (gmii_rxd_valid), + .I1 (cnt[2]), + .I2 (cnt[3]), + .I3 (cnt[4])); + // LUT = I0&~I1&I2&I3 ; - GTP_LUT5 /* N706 */ #( - .INIT(32'b10101110101010101010101010101010)) + GTP_LUT4 /* N706 */ #( + .INIT(16'b1100110010000000)) N706_vname ( .Z (N706), - .I0 (N319), + .I0 (N186), .I1 (N419), - .I2 (cnt[2]), - .I3 (cnt[4]), - .I4 (_N108056)); + .I2 (_N108187), + .I3 (_N108892)); // defparam N706_vname.orig_name = N706; - // LUT = (I0)|(I1&~I2&I3&I4) ; + // LUT = (I1&I3)|(I0&I1&I2) ; // ../../sources/designs/udp_osd/eth_udp/arp/arp_rx.v:140 GTP_LUT2 /* \N709_1[8] */ #( @@ -330741,18 +330203,10 @@ module arp_rx // LUT = ~I0&I1 ; // ../../sources/designs/udp_osd/eth_udp/arp/arp_rx.v:140 - GTP_LUT2 /* N766_1 */ #( - .INIT(4'b0001)) - N766_1 ( - .Z (_N95925), - .I0 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt [3] ), - .I1 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt [4] )); - // LUT = ~I0&~I1 ; - - GTP_LUT5 /* N766_3 */ #( + GTP_LUT5 /* N766_1 */ #( .INIT(32'b00000000000000000010101000000000)) - N766_3 ( - .Z (_N108081), + N766_1 ( + .Z (_N108916), .I0 (gmii_rxd_valid), .I1 (cnt[1]), .I2 (cnt[2]), @@ -330766,8 +330220,8 @@ module arp_rx .Z (N769), .I0 (N186), .I1 (N419), - .I2 (_N107358), - .I3 (_N108081)); + .I2 (_N108187), + .I3 (_N108916)); // defparam N769_vname.orig_name = N769; // LUT = (I1&I3)|(I0&I1&I2) ; // ../../sources/designs/udp_osd/eth_udp/arp/arp_rx.v:140 @@ -331132,10 +330586,10 @@ module arp_rx // LUT = ~I0&I1 ; // ../../sources/designs/udp_osd/eth_udp/arp/arp_rx.v:140 - GTP_LUT5 /* N831_8 */ #( + GTP_LUT5 /* N831_4 */ #( .INIT(32'b00000000000000101000000000000000)) - N831_8 ( - .Z (_N108082), + N831_4 ( + .Z (_N108917), .I0 (gmii_rxd_valid), .I1 (cnt[1]), .I2 (cnt[2]), @@ -331149,8 +330603,8 @@ module arp_rx .Z (N834), .I0 (N186), .I1 (N419), - .I2 (_N107358), - .I3 (_N108082)); + .I2 (_N108187), + .I3 (_N108917)); // defparam N834_vname.orig_name = N834; // LUT = (I1&I3)|(I0&I1&I2) ; // ../../sources/designs/udp_osd/eth_udp/arp/arp_rx.v:140 @@ -331381,32 +330835,21 @@ module arp_rx // defparam N847_vname.orig_name = N847; // LUT = I0&I1&I2 ; - GTP_LUT4 /* N866_5 */ #( + GTP_LUT4 /* N866_2 */ #( .INIT(16'b1000000000000000)) - N866_5 ( + N866_2 ( .Z (N866), - .I0 (_N96775), + .I0 (_N97539), .I1 (gmii_rxd_valid), .I2 (N419), .I3 (cnt[0])); // LUT = I0&I1&I2&I3 ; - GTP_LUT5 /* N866_7 */ #( - .INIT(32'b00000000000010000000000000000000)) - N866_7 ( - .Z (\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N586 ), - .I0 (_N96358), - .I1 (gmii_rxd_valid), - .I2 (\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/next_state [2] ), - .I3 (\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/next_state [3] ), - .I4 (\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/next_state [4] )); - // LUT = I0&I1&~I2&~I3&I4 ; - GTP_LUT3 /* N1057_5 */ #( .INIT(8'b00001000)) N1057_5 ( .Z (N1057), - .I0 (_N96776), + .I0 (_N97540), .I1 (N559), .I2 (cnt[0])); // LUT = I0&I1&~I2 ; @@ -331532,20 +330975,20 @@ module arp_rx // LUT = (I1&I2)|(~I0&~I1&I3) ; // ../../sources/designs/udp_osd/eth_udp/arp/arp_rx.v:68 - GTP_LUT4 /* \cur_state_fsm[4:0]_38 */ #( + GTP_LUT4 /* \cur_state_fsm[4:0]_42 */ #( .INIT(16'b1010101011111100)) - \cur_state_fsm[4:0]_38 ( - .Z (_N108386), + \cur_state_fsm[4:0]_42 ( + .Z (_N109272), .I0 (cur_state_reg[3]), .I1 (cur_state_reg[4]), .I2 (error_en), .I3 (skip_en)); // LUT = (I1&~I3)|(I2&~I3)|(I0&I3) ; - GTP_LUT5 /* \cur_state_fsm[4:0]_39 */ #( + GTP_LUT5 /* \cur_state_fsm[4:0]_43 */ #( .INIT(32'b11001100110011001111111011110000)) - \cur_state_fsm[4:0]_39 ( - .Z (_N108387), + \cur_state_fsm[4:0]_43 ( + .Z (_N109273), .I0 (cur_state_reg[2]), .I1 (cur_state_reg[3]), .I2 (cur_state_reg[4]), @@ -331553,10 +330996,10 @@ module arp_rx .I4 (skip_en)); // LUT = (I2&~I4)|(I1&I3)|(I1&I4)|(I0&I3&~I4) ; - GTP_MUX2LUT6 \cur_state_fsm[4:0]_40 ( + GTP_MUX2LUT6 \cur_state_fsm[4:0]_44 ( .Z (next_state[4]), - .I0 (_N108387), - .I1 (_N108386), + .I0 (_N109273), + .I1 (_N109272), .S (cur_state_reg[1])); (* syn_encoding="onehot" *) GTP_DFF_P /* \cur_state_reg[0] */ #( @@ -334545,10 +333988,10 @@ module arp_tx input [7:0] crc_next, input [31:0] des_ip, input [47:0] des_mac, - input _N96069, - input _N96846, - input _N97055, - input _N97057, + input _N96855, + input _N97621, + input _N97817, + input _N97819, input arp_tx_en, input clk, input sync_vg_100m, @@ -334579,138 +334022,138 @@ module arp_tx wire [7:0] N820; wire N832; wire N932; - wire _N13920; - wire _N13921; - wire _N13922; - wire _N13923; - wire _N19981; - wire _N19983; - wire _N20887; - wire _N20888; - wire _N20889; - wire _N20890; - wire _N20891; - wire _N20892; - wire _N20893; - wire _N20935; - wire _N20936; - wire _N20937; - wire _N20938; - wire _N20939; - wire _N20940; - wire _N20941; - wire _N20942; - wire _N20943; - wire _N20944; - wire _N20945; - wire _N20946; - wire _N20947; - wire _N20948; - wire _N20949; - wire _N20950; - wire _N20990; - wire _N20998; - wire _N20999; - wire _N21000; - wire _N21001; - wire _N21002; - wire _N21003; - wire _N21004; - wire _N21005; - wire _N21014; - wire _N21023; - wire _N21024; - wire _N21025; - wire _N21026; - wire _N21027; - wire _N21028; - wire _N21029; - wire _N21038; - wire _N23461; - wire _N23462; - wire _N23464; - wire _N23465; - wire _N23466; + wire _N13856; + wire _N13857; + wire _N13858; + wire _N13859; + wire _N19886; + wire _N19888; + wire _N20645; + wire _N20646; + wire _N20647; + wire _N20648; + wire _N20649; + wire _N20650; + wire _N20651; + wire _N20693; + wire _N20694; + wire _N20695; + wire _N20696; + wire _N20697; + wire _N20698; + wire _N20699; + wire _N20700; + wire _N20701; + wire _N20702; + wire _N20703; + wire _N20704; + wire _N20705; + wire _N20706; + wire _N20707; + wire _N20708; + wire _N20748; + wire _N20756; + wire _N20757; + wire _N20758; + wire _N20759; + wire _N20760; + wire _N20761; + wire _N20762; + wire _N20763; + wire _N20772; + wire _N20781; + wire _N20782; + wire _N20783; + wire _N20784; + wire _N20785; + wire _N20786; + wire _N20787; + wire _N20796; + wire _N23298; + wire _N23299; + wire _N23301; + wire _N23302; + wire _N23303; + wire _N23304; + wire _N23354; + wire _N23355; + wire _N23357; + wire _N23358; + wire _N23359; + wire _N23360; + wire _N23362; + wire _N23363; + wire _N23365; + wire _N23366; + wire _N23367; + wire _N23368; + wire _N23419; + wire _N23421; + wire _N23423; wire _N23467; - wire _N23517; - wire _N23518; - wire _N23520; - wire _N23521; - wire _N23522; - wire _N23523; - wire _N23525; - wire _N23526; - wire _N23528; - wire _N23529; - wire _N23530; - wire _N23531; - wire _N23582; - wire _N23584; - wire _N23586; - wire _N23630; - wire _N23632; - wire _N23634; - wire _N23637; - wire _N23638; - wire _N23640; - wire _N23641; - wire _N23642; - wire _N23643; - wire _N38189; - wire _N38191; - wire _N38287; - wire _N38289; - wire _N38293; - wire _N38515; - wire _N38547; - wire _N38601; - wire _N38717; - wire _N38750; - wire _N95832; - wire _N95890; - wire _N96002; - wire _N96575; - wire _N96700; - wire _N96749; - wire _N96807; - wire _N103144_2; - wire _N103145_2; - wire _N103174_2; - wire _N103174_3; - wire _N103178_2; - wire _N103178_3; - wire _N103180_2; - wire _N103180_3; - wire _N103184_4; - wire _N103184_7; - wire _N103184_9; - wire _N103184_10; - wire _N103184_11; - wire _N103189_2; - wire _N103189_4; - wire _N103189_5; - wire _N103189_7; - wire _N103189_10; - wire _N107660; - wire _N107726; - wire _N107730; - wire _N107734; - wire _N107738; - wire _N107742; - wire _N107746; - wire _N107750; - wire _N107761; - wire _N107765; - wire _N107769; - wire _N107773; - wire _N107777; - wire _N107781; - wire _N107785; - wire _N107789; - wire _N107792; - wire _N107793; - wire _N107797; - wire _N107854; + wire _N23469; + wire _N23471; + wire _N23474; + wire _N23475; + wire _N23477; + wire _N23478; + wire _N23479; + wire _N23480; + wire _N35874; + wire _N35876; + wire _N35965; + wire _N35967; + wire _N35971; + wire _N37392; + wire _N37426; + wire _N37488; + wire _N37558; + wire _N37634; + wire _N96621; + wire _N96652; + wire _N97102; + wire _N97318; + wire _N97521; + wire _N97524; + wire _N97789; + wire _N103974_2; + wire _N103975_2; + wire _N104002_2; + wire _N104002_3; + wire _N104006_2; + wire _N104006_3; + wire _N104008_2; + wire _N104008_3; + wire _N104012_4; + wire _N104012_7; + wire _N104012_9; + wire _N104012_10; + wire _N104012_11; + wire _N104017_2; + wire _N104017_4; + wire _N104017_5; + wire _N104017_7; + wire _N104017_10; + wire _N108492; + wire _N108558; + wire _N108562; + wire _N108566; + wire _N108570; + wire _N108574; + wire _N108578; + wire _N108582; + wire _N108593; + wire _N108597; + wire _N108601; + wire _N108605; + wire _N108609; + wire _N108613; + wire _N108617; + wire _N108621; + wire _N108624; + wire _N108625; + wire _N108629; + wire _N108686; wire [7:0] \arp_data[7] ; wire [7:0] \arp_data[18] ; wire [7:0] \arp_data[19] ; @@ -334739,7 +334182,7 @@ module arp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N185_1_1 ( - .COUT (_N13920), + .COUT (_N13856), .Z (N185[1]), .CIN (), .I0 (cnt[0]), @@ -334759,9 +334202,9 @@ module arp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N185_1_2 ( - .COUT (_N13921), + .COUT (_N13857), .Z (N185[2]), - .CIN (_N13920), + .CIN (_N13856), .I0 (cnt[0]), .I1 (cnt[1]), .I2 (cnt[2]), @@ -334779,9 +334222,9 @@ module arp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N185_1_3 ( - .COUT (_N13922), + .COUT (_N13858), .Z (N185[3]), - .CIN (_N13921), + .CIN (_N13857), .I0 (), .I1 (cnt[3]), .I2 (), @@ -334799,9 +334242,9 @@ module arp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N185_1_4 ( - .COUT (_N13923), + .COUT (_N13859), .Z (N185[4]), - .CIN (_N13922), + .CIN (_N13858), .I0 (), .I1 (cnt[4]), .I2 (), @@ -334821,7 +334264,7 @@ module arp_tx N185_1_5 ( .COUT (), .Z (N185[5]), - .CIN (_N13923), + .CIN (_N13859), .I0 (), .I1 (cnt[5]), .I2 (), @@ -334835,7 +334278,7 @@ module arp_tx GTP_LUT3 /* \N219_36[0]_2 */ #( .INIT(8'b11001010)) \N219_36[0]_2 ( - .Z (_N103144_2), + .Z (_N103974_2), .I0 (\arp_data[7] [0] ), .I1 (\arp_data[23] [0] ), .I2 (data_cnt[4])); @@ -334844,7 +334287,7 @@ module arp_tx GTP_LUT3 /* \N219_36[1]_2 */ #( .INIT(8'b11001010)) \N219_36[1]_2 ( - .Z (_N103145_2), + .Z (_N103975_2), .I0 (\arp_data[7] [1] ), .I1 (\arp_data[23] [1] ), .I2 (data_cnt[4])); @@ -334853,8 +334296,8 @@ module arp_tx GTP_LUT5M /* \N219_40[0] */ #( .INIT(32'b00001010000010101100101011110000)) \N219_40[0] ( - .Z (_N23461), - .I0 (_N103144_2), + .Z (_N23298), + .I0 (_N103974_2), .I1 (\arp_data[27] [0] ), .I2 (data_cnt[3]), .I3 (data_cnt[4]), @@ -334865,8 +334308,8 @@ module arp_tx GTP_LUT5M /* \N219_40[1] */ #( .INIT(32'b00001010000010101100101011110000)) \N219_40[1] ( - .Z (_N23462), - .I0 (_N103145_2), + .Z (_N23299), + .I0 (_N103975_2), .I1 (\arp_data[27] [1] ), .I2 (data_cnt[3]), .I3 (data_cnt[4]), @@ -334877,7 +334320,7 @@ module arp_tx GTP_LUT5M /* \N219_40[3] */ #( .INIT(32'b00100010110011001110001000000000)) \N219_40[3] ( - .Z (_N23464), + .Z (_N23301), .I0 (\arp_data[27] [3] ), .I1 (data_cnt[2]), .I2 (\arp_data[23] [3] ), @@ -334889,7 +334332,7 @@ module arp_tx GTP_LUT5M /* \N219_40[4] */ #( .INIT(32'b00100010001100111110001000000000)) \N219_40[4] ( - .Z (_N23465), + .Z (_N23302), .I0 (\arp_data[27] [4] ), .I1 (data_cnt[2]), .I2 (\arp_data[23] [4] ), @@ -334901,7 +334344,7 @@ module arp_tx GTP_LUT5M /* \N219_40[5]_1 */ #( .INIT(32'b00100010111111111110001000000000)) \N219_40[5]_1 ( - .Z (_N23466), + .Z (_N23303), .I0 (\arp_data[27] [5] ), .I1 (data_cnt[2]), .I2 (\arp_data[23] [5] ), @@ -334913,7 +334356,7 @@ module arp_tx GTP_LUT5M /* \N219_40[6] */ #( .INIT(32'b00100010000000001110001000000000)) \N219_40[6] ( - .Z (_N23467), + .Z (_N23304), .I0 (\arp_data[27] [6] ), .I1 (data_cnt[2]), .I2 (\arp_data[23] [6] ), @@ -334925,7 +334368,7 @@ module arp_tx GTP_LUT5 /* \N219_47[0] */ #( .INIT(32'b00001100101000001111111100001111)) \N219_47[0] ( - .Z (_N23517), + .Z (_N23354), .I0 (\arp_data[21] [0] ), .I1 (\arp_data[25] [0] ), .I2 (data_cnt[2]), @@ -334936,7 +334379,7 @@ module arp_tx GTP_LUT5 /* \N219_47[1] */ #( .INIT(32'b00001100101011110000000000000000)) \N219_47[1] ( - .Z (_N23518), + .Z (_N23355), .I0 (\arp_data[21] [1] ), .I1 (\arp_data[25] [1] ), .I2 (data_cnt[2]), @@ -334947,7 +334390,7 @@ module arp_tx GTP_LUT5 /* \N219_47[3] */ #( .INIT(32'b00001100101011110000000000000000)) \N219_47[3] ( - .Z (_N23520), + .Z (_N23357), .I0 (\arp_data[21] [3] ), .I1 (\arp_data[25] [3] ), .I2 (data_cnt[2]), @@ -334958,7 +334401,7 @@ module arp_tx GTP_LUT5 /* \N219_47[4] */ #( .INIT(32'b00001100101000001111111100000000)) \N219_47[4] ( - .Z (_N23521), + .Z (_N23358), .I0 (\arp_data[21] [4] ), .I1 (\arp_data[25] [4] ), .I2 (data_cnt[2]), @@ -334969,7 +334412,7 @@ module arp_tx GTP_LUT5 /* \N219_47[5] */ #( .INIT(32'b00001100101000000000000000000000)) \N219_47[5] ( - .Z (_N23522), + .Z (_N23359), .I0 (\arp_data[21] [5] ), .I1 (\arp_data[25] [5] ), .I2 (data_cnt[2]), @@ -334980,7 +334423,7 @@ module arp_tx GTP_LUT5 /* \N219_47[6] */ #( .INIT(32'b00001100101000001111000000000000)) \N219_47[6] ( - .Z (_N23523), + .Z (_N23360), .I0 (\arp_data[21] [6] ), .I1 (\arp_data[25] [6] ), .I2 (data_cnt[2]), @@ -334989,45 +334432,45 @@ module arp_tx // LUT = (I2&I3&~I4)|(I0&I2&~I3&I4)|(I1&~I2&I3&I4) ; GTP_MUX2LUT6 \N219_48[0] ( - .Z (_N23525), - .I0 (_N23517), - .I1 (_N23461), + .Z (_N23362), + .I0 (_N23354), + .I1 (_N23298), .S (data_cnt[1])); GTP_MUX2LUT6 \N219_48[1] ( - .Z (_N23526), - .I0 (_N23518), - .I1 (_N23462), + .Z (_N23363), + .I0 (_N23355), + .I1 (_N23299), .S (data_cnt[1])); GTP_MUX2LUT6 \N219_48[3] ( - .Z (_N23528), - .I0 (_N23520), - .I1 (_N23464), + .Z (_N23365), + .I0 (_N23357), + .I1 (_N23301), .S (data_cnt[1])); GTP_MUX2LUT6 \N219_48[4] ( - .Z (_N23529), - .I0 (_N23521), - .I1 (_N23465), + .Z (_N23366), + .I0 (_N23358), + .I1 (_N23302), .S (data_cnt[1])); GTP_MUX2LUT6 \N219_48[5] ( - .Z (_N23530), - .I0 (_N23522), - .I1 (_N23466), + .Z (_N23367), + .I0 (_N23359), + .I1 (_N23303), .S (data_cnt[1])); GTP_MUX2LUT6 \N219_48[6] ( - .Z (_N23531), - .I0 (_N23523), - .I1 (_N23467), + .Z (_N23368), + .I0 (_N23360), + .I1 (_N23304), .S (data_cnt[1])); GTP_LUT5M /* \N219_55[1] */ #( .INIT(32'b00100010001100111110001000000000)) \N219_55[1] ( - .Z (_N23582), + .Z (_N23419), .I0 (\arp_data[26] [1] ), .I1 (data_cnt[2]), .I2 (\arp_data[22] [1] ), @@ -335039,7 +334482,7 @@ module arp_tx GTP_LUT5M /* \N219_55[3] */ #( .INIT(32'b00100010000000001110001000110011)) \N219_55[3] ( - .Z (_N23584), + .Z (_N23421), .I0 (\arp_data[26] [3] ), .I1 (data_cnt[2]), .I2 (\arp_data[22] [3] ), @@ -335051,7 +334494,7 @@ module arp_tx GTP_LUT5M /* \N219_55[5] */ #( .INIT(32'b00100010001100111110001000000000)) \N219_55[5] ( - .Z (_N23586), + .Z (_N23423), .I0 (\arp_data[26] [5] ), .I1 (data_cnt[2]), .I2 (\arp_data[22] [5] ), @@ -335063,7 +334506,7 @@ module arp_tx GTP_LUT5 /* \N219_61[1] */ #( .INIT(32'b00001100101011110000000011110000)) \N219_61[1] ( - .Z (_N23630), + .Z (_N23467), .I0 (\arp_data[20] [1] ), .I1 (\arp_data[24] [1] ), .I2 (data_cnt[2]), @@ -335074,7 +334517,7 @@ module arp_tx GTP_LUT5 /* \N219_61[3] */ #( .INIT(32'b00001100101011110000000000000000)) \N219_61[3] ( - .Z (_N23632), + .Z (_N23469), .I0 (\arp_data[20] [3] ), .I1 (\arp_data[24] [3] ), .I2 (data_cnt[2]), @@ -335085,7 +334528,7 @@ module arp_tx GTP_LUT5 /* \N219_61[5] */ #( .INIT(32'b00001100101000000000000000000000)) \N219_61[5] ( - .Z (_N23634), + .Z (_N23471), .I0 (\arp_data[20] [5] ), .I1 (\arp_data[24] [5] ), .I2 (data_cnt[2]), @@ -335094,15 +334537,15 @@ module arp_tx // LUT = (I0&I2&~I3&I4)|(I1&~I2&I3&I4) ; GTP_MUX2LUT6 \N219_62[0]_1 ( - .Z (_N23637), - .I0 (_N103174_2), - .I1 (_N103174_3), + .Z (_N23474), + .I0 (_N104002_2), + .I1 (_N104002_3), .S (data_cnt[2])); GTP_LUT5M /* \N219_62[0]_2 */ #( .INIT(32'b11100010000000001000100000000000)) \N219_62[0]_2 ( - .Z (_N103174_2), + .Z (_N104002_2), .I0 (\arp_data[24] [0] ), .I1 (data_cnt[1]), .I2 (\arp_data[26] [0] ), @@ -335114,7 +334557,7 @@ module arp_tx GTP_LUT5 /* \N219_62[0]_3 */ #( .INIT(32'b00000000110010100000000000000000)) \N219_62[0]_3 ( - .Z (_N103174_3), + .Z (_N104002_3), .I0 (\arp_data[20] [0] ), .I1 (\arp_data[22] [0] ), .I2 (data_cnt[1]), @@ -335123,27 +334566,27 @@ module arp_tx // LUT = (I0&~I2&~I3&I4)|(I1&I2&~I3&I4) ; GTP_MUX2LUT6 \N219_62[1] ( - .Z (_N23638), - .I0 (_N23630), - .I1 (_N23582), + .Z (_N23475), + .I0 (_N23467), + .I1 (_N23419), .S (data_cnt[1])); GTP_MUX2LUT6 \N219_62[3] ( - .Z (_N23640), - .I0 (_N23632), - .I1 (_N23584), + .Z (_N23477), + .I0 (_N23469), + .I1 (_N23421), .S (data_cnt[1])); GTP_MUX2LUT6 \N219_62[4]_1 ( - .Z (_N23641), - .I0 (_N103178_2), - .I1 (_N103178_3), + .Z (_N23478), + .I0 (_N104006_2), + .I1 (_N104006_3), .S (data_cnt[2])); GTP_LUT5M /* \N219_62[4]_2 */ #( .INIT(32'b11100010000000001000100000000000)) \N219_62[4]_2 ( - .Z (_N103178_2), + .Z (_N104006_2), .I0 (\arp_data[24] [4] ), .I1 (data_cnt[1]), .I2 (\arp_data[26] [4] ), @@ -335155,7 +334598,7 @@ module arp_tx GTP_LUT5 /* \N219_62[4]_3 */ #( .INIT(32'b00000000110010100000000000000000)) \N219_62[4]_3 ( - .Z (_N103178_3), + .Z (_N104006_3), .I0 (\arp_data[20] [4] ), .I1 (\arp_data[22] [4] ), .I2 (data_cnt[1]), @@ -335164,21 +334607,21 @@ module arp_tx // LUT = (I0&~I2&~I3&I4)|(I1&I2&~I3&I4) ; GTP_MUX2LUT6 \N219_62[5] ( - .Z (_N23642), - .I0 (_N23634), - .I1 (_N23586), + .Z (_N23479), + .I0 (_N23471), + .I1 (_N23423), .S (data_cnt[1])); GTP_MUX2LUT6 \N219_62[6]_1 ( - .Z (_N23643), - .I0 (_N103180_2), - .I1 (_N103180_3), + .Z (_N23480), + .I0 (_N104008_2), + .I1 (_N104008_3), .S (data_cnt[2])); GTP_LUT5M /* \N219_62[6]_2 */ #( .INIT(32'b11100010000000001000100000000000)) \N219_62[6]_2 ( - .Z (_N103180_2), + .Z (_N104008_2), .I0 (\arp_data[24] [6] ), .I1 (data_cnt[1]), .I2 (\arp_data[26] [6] ), @@ -335190,7 +334633,7 @@ module arp_tx GTP_LUT5 /* \N219_62[6]_3 */ #( .INIT(32'b00000000110010101111111100000000)) \N219_62[6]_3 ( - .Z (_N103180_3), + .Z (_N104008_3), .I0 (\arp_data[20] [6] ), .I1 (\arp_data[22] [6] ), .I2 (data_cnt[1]), @@ -335200,32 +334643,32 @@ module arp_tx GTP_MUX2LUT7 \N219_63[0] ( .Z (N219[0]), - .I0 (_N23637), - .I1 (_N23525), + .I0 (_N23474), + .I1 (_N23362), .S (data_cnt[0])); GTP_MUX2LUT7 \N219_63[1] ( .Z (N219[1]), - .I0 (_N23638), - .I1 (_N23526), + .I0 (_N23475), + .I1 (_N23363), .S (data_cnt[0])); GTP_LUT5M /* \N219_63[2]_1 */ #( .INIT(32'b10101010101000001100101011111010)) \N219_63[2]_1 ( .Z (N219[2]), - .I0 (_N103184_7), - .I1 (_N103184_9), + .I0 (_N104012_7), + .I1 (_N104012_9), .I2 (data_cnt[2]), .I3 (data_cnt[4]), .I4 (data_cnt[1]), - .ID (_N103184_4)); + .ID (_N104012_4)); // LUT = (I2&~I3&~I4)|(ID&~I2&~I4)|(I1&I2&~I4)|(I0&I3&I4)|(I0&I2&~I3) ; GTP_LUT5 /* \N219_63[2]_4 */ #( .INIT(32'b11001010000000000000000000000000)) \N219_63[2]_4 ( - .Z (_N103184_4), + .Z (_N104012_4), .I0 (\arp_data[24] [2] ), .I1 (\arp_data[25] [2] ), .I2 (data_cnt[0]), @@ -335234,15 +334677,15 @@ module arp_tx // LUT = (I0&~I2&I3&I4)|(I1&I2&I3&I4) ; GTP_MUX2LUT6 \N219_63[2]_7 ( - .Z (_N103184_7), - .I0 (_N103184_10), - .I1 (_N103184_11), + .Z (_N104012_7), + .I0 (_N104012_10), + .I1 (_N104012_11), .S (data_cnt[2])); GTP_LUT4 /* \N219_63[2]_9 */ #( .INIT(16'b0000000011001010)) \N219_63[2]_9 ( - .Z (_N103184_9), + .Z (_N104012_9), .I0 (\arp_data[20] [2] ), .I1 (\arp_data[21] [2] ), .I2 (data_cnt[0]), @@ -335252,7 +334695,7 @@ module arp_tx GTP_LUT5M /* \N219_63[2]_10 */ #( .INIT(32'b11001010110010101111101000001010)) \N219_63[2]_10 ( - .Z (_N103184_10), + .Z (_N104012_10), .I0 (\arp_data[26] [2] ), .I1 (\arp_data[27] [2] ), .I2 (data_cnt[0]), @@ -335264,7 +334707,7 @@ module arp_tx GTP_LUT5 /* \N219_63[2]_11 */ #( .INIT(32'b00000000110010100000000000000000)) \N219_63[2]_11 ( - .Z (_N103184_11), + .Z (_N104012_11), .I0 (\arp_data[22] [2] ), .I1 (\arp_data[23] [2] ), .I2 (data_cnt[0]), @@ -335274,50 +334717,50 @@ module arp_tx GTP_MUX2LUT7 \N219_63[3] ( .Z (N219[3]), - .I0 (_N23640), - .I1 (_N23528), + .I0 (_N23477), + .I1 (_N23365), .S (data_cnt[0])); GTP_MUX2LUT7 \N219_63[4] ( .Z (N219[4]), - .I0 (_N23641), - .I1 (_N23529), + .I0 (_N23478), + .I1 (_N23366), .S (data_cnt[0])); GTP_MUX2LUT7 \N219_63[5] ( .Z (N219[5]), - .I0 (_N23642), - .I1 (_N23530), + .I0 (_N23479), + .I1 (_N23367), .S (data_cnt[0])); GTP_MUX2LUT7 \N219_63[6] ( .Z (N219[6]), - .I0 (_N23643), - .I1 (_N23531), + .I0 (_N23480), + .I1 (_N23368), .S (data_cnt[0])); GTP_LUT5M /* \N219_63[7]_1 */ #( .INIT(32'b10101010110000001010101010101010)) \N219_63[7]_1 ( .Z (N219[7]), - .I0 (_N103189_7), + .I0 (_N104017_7), .I1 (data_cnt[2]), .I2 (data_cnt[3]), .I3 (data_cnt[4]), .I4 (data_cnt[1]), - .ID (_N103189_2)); + .ID (_N104017_2)); // LUT = (ID&~I4)|(I1&I2&~I3&I4)|(I0&I3&I4) ; GTP_MUX2LUT6 \N219_63[7]_2 ( - .Z (_N103189_2), - .I0 (_N103189_4), - .I1 (_N103189_5), + .Z (_N104017_2), + .I0 (_N104017_4), + .I1 (_N104017_5), .S (data_cnt[2])); GTP_LUT5 /* \N219_63[7]_4 */ #( .INIT(32'b11001010000000000000000000000000)) \N219_63[7]_4 ( - .Z (_N103189_4), + .Z (_N104017_4), .I0 (\arp_data[24] [7] ), .I1 (\arp_data[25] [7] ), .I2 (data_cnt[0]), @@ -335328,7 +334771,7 @@ module arp_tx GTP_LUT5 /* \N219_63[7]_5 */ #( .INIT(32'b00000000110010100000000000000000)) \N219_63[7]_5 ( - .Z (_N103189_5), + .Z (_N104017_5), .I0 (\arp_data[20] [7] ), .I1 (\arp_data[21] [7] ), .I2 (data_cnt[0]), @@ -335339,19 +334782,19 @@ module arp_tx GTP_LUT5M /* \N219_63[7]_7 */ #( .INIT(32'b00000000111000101010101010101010)) \N219_63[7]_7 ( - .Z (_N103189_7), + .Z (_N104017_7), .I0 (\arp_data[22] [7] ), .I1 (data_cnt[0]), .I2 (\arp_data[23] [7] ), .I3 (data_cnt[3]), .I4 (data_cnt[2]), - .ID (_N103189_10)); + .ID (_N104017_10)); // LUT = (ID&~I4)|(I1&I2&~I3&I4)|(I0&~I1&~I3&I4) ; GTP_LUT5M /* \N219_63[7]_10 */ #( .INIT(32'b11001010110010101111101000001010)) \N219_63[7]_10 ( - .Z (_N103189_10), + .Z (_N104017_10), .I0 (\arp_data[26] [7] ), .I1 (\arp_data[27] [7] ), .I2 (data_cnt[0]), @@ -335364,7 +334807,7 @@ module arp_tx .INIT(32'b11111100111111101111111011111100)) N289_1 ( .Z (N765), - .I0 (_N96749), + .I0 (_N97524), .I1 (N411), .I2 (N416), .I3 (next_state[3]), @@ -335375,9 +334818,9 @@ module arp_tx GTP_LUT5M /* N289_2 */ #( .INIT(32'b11111111010000001111111100001000)) N289_2 ( - .Z (_N95890), + .Z (_N96652), .I0 (cur_state_reg[2]), - .I1 (_N96749), + .I1 (_N97524), .I2 (cur_state_reg[3]), .I3 (N411), .I4 (skip_en), @@ -335387,7 +334830,7 @@ module arp_tx GTP_LUT5M /* N291_6 */ #( .INIT(32'b00000001000000000000000100000000)) N291_6 ( - .Z (_N107660), + .Z (_N108492), .I0 (cur_state_reg[0]), .I1 (tx_en_d2), .I2 (cur_state_reg[1]), @@ -335396,22 +334839,19 @@ module arp_tx .ID (cur_state_reg[2])); // LUT = (~ID&~I1&~I2&I3&~I4)|(~I0&~I1&~I2&I3&I4) ; - GTP_LUT5M /* N291_8 */ #( - .INIT(32'b00000100000000000000000000001000)) + GTP_LUT3 /* N291_8 */ #( + .INIT(8'b00000001)) N291_8 ( - .Z (N932), - .I0 (cur_state_reg[2]), - .I1 (_N107660), - .I2 (cur_state_reg[3]), - .I3 (cur_state_reg[4]), - .I4 (skip_en), - .ID (cur_state_reg[0])); - // LUT = (ID&I1&~I2&~I3&~I4)|(~I0&I1&~I2&I3&I4) ; + .Z (_N97521), + .I0 (cnt[3]), + .I1 (cnt[4]), + .I2 (cnt[5])); + // LUT = ~I0&~I1&~I2 ; GTP_LUT5M /* N291_12 */ #( .INIT(32'b01011000000010000100101001000000)) N291_12 ( - .Z (_N19981), + .Z (_N19886), .I0 (cur_state_reg[2]), .I1 (N420), .I2 (cur_state_reg[3]), @@ -335423,33 +334863,45 @@ module arp_tx GTP_LUT5M /* N291_14 */ #( .INIT(32'b00000000101000001100000010101010)) N291_14 ( - .Z (_N19983), + .Z (_N19888), .I0 (N415), .I1 (N418), - .I2 (_N95832), + .I2 (_N96621), .I3 (next_state[2]), .I4 (next_state[1]), - .ID (_N19981)); + .ID (_N19886)); // LUT = (ID&~I3&~I4)|(I1&I2&I3&~I4)|(I0&I2&~I3&I4) ; GTP_LUT5M /* N291_15 */ #( - .INIT(32'b11010101100000001101010110000000)) + .INIT(32'b11011000010100001101100001010000)) N291_15 ( .Z (N291), .I0 (cur_state_reg[4]), - .I1 (_N107660), - .I2 (_N95832), - .I3 (_N19983), + .I1 (_N96621), + .I2 (_N19888), + .I3 (_N108492), + .I4 (skip_en), + .ID (cur_state_reg[0])); + // LUT = (ID&I1&I3&~I4)|(~ID&I2&~I4)|(I0&I1&I3&I4)|(~I0&I2&I4) ; + + GTP_LUT5M /* N291_16 */ #( + .INIT(32'b00010000000000000000001000000000)) + N291_16 ( + .Z (N932), + .I0 (cur_state_reg[2]), + .I1 (cur_state_reg[3]), + .I2 (cur_state_reg[4]), + .I3 (_N108492), .I4 (skip_en), .ID (cur_state_reg[0])); - // LUT = (~ID&I3&~I4)|(ID&I1&I2&~I4)|(~I0&I3&I4)|(I0&I1&I2&I4) ; + // LUT = (ID&~I1&~I2&I3&~I4)|(~I0&~I1&I2&I3&I4) ; GTP_LUT5M /* N299_2 */ #( .INIT(32'b01000000000000000000100000000000)) N299_2 ( .Z (N299), .I0 (cur_state_reg[2]), - .I1 (_N96749), + .I1 (_N97524), .I2 (cur_state_reg[3]), .I3 (N427), .I4 (skip_en), @@ -335457,10 +334909,20 @@ module arp_tx // LUT = (ID&I1&~I2&I3&~I4)|(~I0&I1&I2&I3&I4) ; // ../../sources/designs/udp_osd/eth_udp/arp/arp_tx.v:202 + GTP_LUT4 /* N327_1 */ #( + .INIT(16'b0000001000000111)) + N327_1 ( + .Z (_N96621), + .I0 (skip_en), + .I1 (cur_state_reg[2]), + .I2 (cur_state_reg[3]), + .I3 (cur_state_reg[4])); + // LUT = (~I0&~I2&~I3)|(I0&~I1&~I2) ; + GTP_LUT5 /* N376_8 */ #( .INIT(32'b11111111111111111111111111111110)) N376_8 ( - .Z (_N107761), + .Z (_N108593), .I0 (des_mac[4]), .I1 (des_mac[5]), .I2 (des_mac[6]), @@ -335471,7 +334933,7 @@ module arp_tx GTP_LUT5 /* N376_12 */ #( .INIT(32'b11111111111111111111111111111110)) N376_12 ( - .Z (_N107765), + .Z (_N108597), .I0 (des_mac[9]), .I1 (des_mac[10]), .I2 (des_mac[11]), @@ -335482,7 +334944,7 @@ module arp_tx GTP_LUT5 /* N376_16 */ #( .INIT(32'b11111111111111111111111111111110)) N376_16 ( - .Z (_N107769), + .Z (_N108601), .I0 (des_mac[14]), .I1 (des_mac[15]), .I2 (des_mac[16]), @@ -335493,7 +334955,7 @@ module arp_tx GTP_LUT5 /* N376_20 */ #( .INIT(32'b11111111111111111111111111111110)) N376_20 ( - .Z (_N107773), + .Z (_N108605), .I0 (des_mac[19]), .I1 (des_mac[20]), .I2 (des_mac[21]), @@ -335504,7 +334966,7 @@ module arp_tx GTP_LUT5 /* N376_24 */ #( .INIT(32'b11111111111111111111111111111110)) N376_24 ( - .Z (_N107777), + .Z (_N108609), .I0 (des_mac[24]), .I1 (des_mac[25]), .I2 (des_mac[26]), @@ -335515,7 +334977,7 @@ module arp_tx GTP_LUT5 /* N376_28 */ #( .INIT(32'b11111111111111111111111111111110)) N376_28 ( - .Z (_N107781), + .Z (_N108613), .I0 (des_mac[29]), .I1 (des_mac[30]), .I2 (des_mac[31]), @@ -335526,7 +334988,7 @@ module arp_tx GTP_LUT5 /* N376_32 */ #( .INIT(32'b11111111111111111111111111111110)) N376_32 ( - .Z (_N107785), + .Z (_N108617), .I0 (des_mac[34]), .I1 (des_mac[35]), .I2 (des_mac[36]), @@ -335537,7 +334999,7 @@ module arp_tx GTP_LUT5 /* N376_36 */ #( .INIT(32'b11111111111111111111111111111110)) N376_36 ( - .Z (_N107789), + .Z (_N108621), .I0 (des_mac[39]), .I1 (des_mac[40]), .I2 (des_mac[41]), @@ -335548,7 +335010,7 @@ module arp_tx GTP_LUT4 /* N376_39 */ #( .INIT(16'b1111111111111110)) N376_39 ( - .Z (_N107792), + .Z (_N108624), .I0 (des_mac[44]), .I1 (des_mac[45]), .I2 (des_mac[46]), @@ -335558,40 +335020,40 @@ module arp_tx GTP_LUT5 /* N376_40 */ #( .INIT(32'b11111111111111111111111111111110)) N376_40 ( - .Z (_N107793), + .Z (_N108625), .I0 (des_mac[0]), .I1 (des_mac[1]), .I2 (des_mac[2]), .I3 (des_mac[3]), - .I4 (_N107792)); + .I4 (_N108624)); // LUT = (I0)|(I1)|(I2)|(I3)|(I4) ; GTP_LUT5 /* N376_44 */ #( .INIT(32'b11111111111111111111111111111110)) N376_44 ( - .Z (_N107797), - .I0 (_N107761), - .I1 (_N107765), - .I2 (_N107769), - .I3 (_N107773), - .I4 (_N107777)); + .Z (_N108629), + .I0 (_N108593), + .I1 (_N108597), + .I2 (_N108601), + .I3 (_N108605), + .I4 (_N108609)); // LUT = (I0)|(I1)|(I2)|(I3)|(I4) ; GTP_LUT5 /* N376_48 */ #( .INIT(32'b11111111111111111111111111111110)) N376_48 ( .Z (N376_inv), - .I0 (_N107781), - .I1 (_N107785), - .I2 (_N107789), - .I3 (_N107793), - .I4 (_N107797)); + .I0 (_N108613), + .I1 (_N108617), + .I2 (_N108621), + .I3 (_N108625), + .I4 (_N108629)); // LUT = (I0)|(I1)|(I2)|(I3)|(I4) ; GTP_LUT4 /* N409_4 */ #( .INIT(16'b1111111111111110)) N409_4 ( - .Z (_N107726), + .Z (_N108558), .I0 (des_ip[0]), .I1 (des_ip[1]), .I2 (des_ip[2]), @@ -335601,7 +335063,7 @@ module arp_tx GTP_LUT5 /* N409_8 */ #( .INIT(32'b11111111111111111111111111111110)) N409_8 ( - .Z (_N107730), + .Z (_N108562), .I0 (des_ip[4]), .I1 (des_ip[5]), .I2 (des_ip[6]), @@ -335612,7 +335074,7 @@ module arp_tx GTP_LUT5 /* N409_12 */ #( .INIT(32'b11111111111111111111111111111110)) N409_12 ( - .Z (_N107734), + .Z (_N108566), .I0 (des_ip[9]), .I1 (des_ip[10]), .I2 (des_ip[11]), @@ -335623,7 +335085,7 @@ module arp_tx GTP_LUT5 /* N409_16 */ #( .INIT(32'b11111111111111111111111111111110)) N409_16 ( - .Z (_N107738), + .Z (_N108570), .I0 (des_ip[14]), .I1 (des_ip[15]), .I2 (des_ip[16]), @@ -335634,7 +335096,7 @@ module arp_tx GTP_LUT5 /* N409_20 */ #( .INIT(32'b11111111111111111111111111111110)) N409_20 ( - .Z (_N107742), + .Z (_N108574), .I0 (des_ip[19]), .I1 (des_ip[20]), .I2 (des_ip[21]), @@ -335645,7 +335107,7 @@ module arp_tx GTP_LUT5 /* N409_24 */ #( .INIT(32'b11111111111111111111111111111110)) N409_24 ( - .Z (_N107746), + .Z (_N108578), .I0 (des_ip[24]), .I1 (des_ip[25]), .I2 (des_ip[26]), @@ -335656,43 +335118,32 @@ module arp_tx GTP_LUT5 /* N409_28 */ #( .INIT(32'b11111111111111111111111111111110)) N409_28 ( - .Z (_N107750), + .Z (_N108582), .I0 (des_ip[29]), .I1 (des_ip[30]), .I2 (des_ip[31]), - .I3 (_N107726), - .I4 (_N107730)); + .I3 (_N108558), + .I4 (_N108562)); // LUT = (I0)|(I1)|(I2)|(I3)|(I4) ; GTP_LUT5 /* N409_32 */ #( .INIT(32'b11111111111111111111111111111110)) N409_32 ( .Z (N409_inv), - .I0 (_N107734), - .I1 (_N107738), - .I2 (_N107742), - .I3 (_N107746), - .I4 (_N107750)); + .I0 (_N108566), + .I1 (_N108570), + .I2 (_N108574), + .I3 (_N108578), + .I4 (_N108582)); // LUT = (I0)|(I1)|(I2)|(I3)|(I4) ; - GTP_LUT5 /* N411_1 */ #( - .INIT(32'b00000000000000010000001000000011)) - N411_1 ( - .Z (_N96749), - .I0 (skip_en), - .I1 (cur_state_reg[0]), - .I2 (cur_state_reg[1]), - .I3 (cur_state_reg[2]), - .I4 (cur_state_reg[4])); - // LUT = (I0&~I1&~I2&~I4)|(~I0&~I1&~I2&~I3) ; - GTP_LUT5M /* N411_6 */ #( .INIT(32'b00010000000000000000000001000000)) N411_6 ( .Z (N411), .I0 (cur_state_reg[4]), .I1 (cur_state_reg[1]), - .I2 (_N95832), + .I2 (_N96621), .I3 (cur_state_reg[0]), .I4 (skip_en), .ID (cur_state_reg[2])); @@ -335702,7 +335153,7 @@ module arp_tx .INIT(16'b1000000000000000)) N415_vname ( .Z (N415), - .I0 (_N96002), + .I0 (_N97521), .I1 (cnt[0]), .I2 (cnt[1]), .I3 (cnt[2])); @@ -335710,15 +335161,16 @@ module arp_tx // LUT = I0&I1&I2&I3 ; // ../../sources/designs/udp_osd/eth_udp/arp/arp_tx.v:232 - GTP_LUT4 /* N415_1 */ #( - .INIT(16'b0000001000000111)) - N415_1 ( - .Z (_N95832), + GTP_LUT5 /* N416_1 */ #( + .INIT(32'b00000000000000010000001000000011)) + N416_1 ( + .Z (_N97524), .I0 (skip_en), - .I1 (cur_state_reg[2]), - .I2 (cur_state_reg[3]), - .I3 (cur_state_reg[4])); - // LUT = (~I0&~I2&~I3)|(I0&~I1&~I2) ; + .I1 (cur_state_reg[0]), + .I2 (cur_state_reg[1]), + .I3 (cur_state_reg[2]), + .I4 (cur_state_reg[4])); + // LUT = (I0&~I1&~I2&~I4)|(~I0&~I1&~I2&~I3) ; GTP_LUT5M /* N416_7 */ #( .INIT(32'b00000000010000000000000000100000)) @@ -335726,7 +335178,7 @@ module arp_tx .Z (N416), .I0 (cur_state_reg[4]), .I1 (cur_state_reg[1]), - .I2 (_N95832), + .I2 (_N96621), .I3 (cur_state_reg[0]), .I4 (skip_en), .ID (cur_state_reg[2])); @@ -335736,7 +335188,7 @@ module arp_tx .INIT(8'b00000010)) N418_vname ( .Z (N418), - .I0 (_N96807), + .I0 (_N97789), .I1 (cnt[4]), .I2 (cnt[5])); // defparam N418_vname.orig_name = N418; @@ -335747,7 +335199,7 @@ module arp_tx .INIT(32'b00000000100000000010001010000000)) N419_5 ( .Z (N419), - .I0 (_N96749), + .I0 (_N97524), .I1 (skip_en), .I2 (cur_state_reg[2]), .I3 (cur_state_reg[3]), @@ -335758,7 +335210,7 @@ module arp_tx .INIT(8'b00100000)) N420_6 ( .Z (N420), - .I0 (_N96807), + .I0 (_N97789), .I1 (cnt[4]), .I2 (cnt[5])); // LUT = I0&~I1&I2 ; @@ -335767,7 +335219,7 @@ module arp_tx .INIT(32'b00001000001000100000100000000000)) N421_3 ( .Z (N421), - .I0 (_N96749), + .I0 (_N97524), .I1 (skip_en), .I2 (cur_state_reg[2]), .I3 (cur_state_reg[3]), @@ -335786,7 +335238,7 @@ module arp_tx .INIT(16'b0000000010000000)) N427_3 ( .Z (N427), - .I0 (_N96002), + .I0 (_N97521), .I1 (cnt[0]), .I2 (cnt[1]), .I3 (cnt[2])); @@ -335796,7 +335248,7 @@ module arp_tx .INIT(32'b11111111101011100000000000000000)) \N768_7_or[2]_1 ( .Z (N768[3]), - .I0 (_N96700), + .I0 (_N97102), .I1 (N411), .I2 (N415), .I3 (N421), @@ -335806,7 +335258,7 @@ module arp_tx GTP_LUT2 /* \N768_7_or[2]_4 */ #( .INIT(4'b1110)) \N768_7_or[2]_4 ( - .Z (_N96575), + .Z (_N97318), .I0 (N416), .I1 (N419)); // LUT = (I0)|(I1) ; @@ -335815,8 +335267,8 @@ module arp_tx .INIT(32'b11111110111011100000000000000000)) \N768_7_or[3]_1 ( .Z (N768[5]), - .I0 (_N95890), - .I1 (_N96700), + .I0 (_N96652), + .I1 (_N97102), .I2 (N416), .I3 (N418), .I4 (N185[5])); @@ -335837,18 +335289,18 @@ module arp_tx .INIT(32'b11111110111111101111111011101110)) N817_1_4 ( .Z (N817), - .I0 (_N96575), + .I0 (_N97318), .I1 (N411), .I2 (N421), .I3 (N427), - .I4 (_N107854)); + .I4 (_N108686)); // LUT = (I0)|(I1)|(I2&I3)|(I2&I4) ; GTP_LUT4 /* N817_2_3 */ #( .INIT(16'b0000000000101010)) N817_2_3 ( - .Z (_N107854), - .I0 (_N96002), + .Z (_N108686), + .I0 (_N97521), .I1 (cnt[0]), .I2 (cnt[1]), .I3 (cnt[2])); @@ -335857,7 +335309,7 @@ module arp_tx GTP_LUT4 /* N817_6 */ #( .INIT(16'b0010000000000000)) N817_6 ( - .Z (_N96807), + .Z (_N97789), .I0 (cnt[0]), .I1 (cnt[1]), .I2 (cnt[2]), @@ -335867,7 +335319,7 @@ module arp_tx GTP_LUT4 /* \N820_36[0] */ #( .INIT(16'b0100010011100100)) \N820_36[0] ( - .Z (_N20887), + .Z (_N20645), .I0 (N416), .I1 (N219[0]), .I2 (cnt[0]), @@ -335877,7 +335329,7 @@ module arp_tx GTP_LUT5 /* \N820_36[1] */ #( .INIT(32'b11100100111001000100010011101110)) \N820_36[1] ( - .Z (_N20888), + .Z (_N20646), .I0 (N416), .I1 (N219[1]), .I2 (cnt[0]), @@ -335888,7 +335340,7 @@ module arp_tx GTP_LUT5 /* \N820_36[2] */ #( .INIT(32'b11100100111001001110111001000100)) \N820_36[2] ( - .Z (_N20889), + .Z (_N20647), .I0 (N416), .I1 (N219[2]), .I2 (cnt[0]), @@ -335899,7 +335351,7 @@ module arp_tx GTP_LUT4 /* \N820_36[3] */ #( .INIT(16'b0100111001000100)) \N820_36[3] ( - .Z (_N20890), + .Z (_N20648), .I0 (N416), .I1 (N219[3]), .I2 (cnt[0]), @@ -335909,7 +335361,7 @@ module arp_tx GTP_LUT4 /* \N820_36[4] */ #( .INIT(16'b0100010011100100)) \N820_36[4] ( - .Z (_N20891), + .Z (_N20649), .I0 (N416), .I1 (N219[4]), .I2 (cnt[0]), @@ -335919,7 +335371,7 @@ module arp_tx GTP_LUT4 /* \N820_36[5] */ #( .INIT(16'b0100010001001110)) \N820_36[5] ( - .Z (_N20892), + .Z (_N20650), .I0 (N416), .I1 (N219[5]), .I2 (cnt[1]), @@ -335929,7 +335381,7 @@ module arp_tx GTP_LUT4 /* \N820_36[6] */ #( .INIT(16'b0100010011100100)) \N820_36[6] ( - .Z (_N20893), + .Z (_N20651), .I0 (N416), .I1 (N219[6]), .I2 (cnt[1]), @@ -335939,7 +335391,7 @@ module arp_tx GTP_LUT5M /* \N820_42[0] */ #( .INIT(32'b11001100101010101111000010101010)) \N820_42[0] ( - .Z (_N20935), + .Z (_N20693), .I0 (\arp_data[19] [0] ), .I1 (\arp_data[21] [0] ), .I2 (\arp_data[20] [0] ), @@ -335951,7 +335403,7 @@ module arp_tx GTP_LUT5M /* \N820_42[1] */ #( .INIT(32'b11001100101010101111000010101010)) \N820_42[1] ( - .Z (_N20936), + .Z (_N20694), .I0 (\arp_data[19] [1] ), .I1 (\arp_data[21] [1] ), .I2 (\arp_data[20] [1] ), @@ -335963,7 +335415,7 @@ module arp_tx GTP_LUT5M /* \N820_42[2] */ #( .INIT(32'b11001100101010101111000010101010)) \N820_42[2] ( - .Z (_N20937), + .Z (_N20695), .I0 (\arp_data[19] [2] ), .I1 (\arp_data[21] [2] ), .I2 (\arp_data[20] [2] ), @@ -335975,7 +335427,7 @@ module arp_tx GTP_LUT5M /* \N820_42[3] */ #( .INIT(32'b11001100101010101111000010101010)) \N820_42[3] ( - .Z (_N20938), + .Z (_N20696), .I0 (\arp_data[19] [3] ), .I1 (\arp_data[21] [3] ), .I2 (\arp_data[20] [3] ), @@ -335987,7 +335439,7 @@ module arp_tx GTP_LUT5M /* \N820_42[4] */ #( .INIT(32'b11001100101010101111000010101010)) \N820_42[4] ( - .Z (_N20939), + .Z (_N20697), .I0 (\arp_data[19] [4] ), .I1 (\arp_data[21] [4] ), .I2 (\arp_data[20] [4] ), @@ -335999,7 +335451,7 @@ module arp_tx GTP_LUT5M /* \N820_42[5] */ #( .INIT(32'b11001100101010101111000010101010)) \N820_42[5] ( - .Z (_N20940), + .Z (_N20698), .I0 (\arp_data[19] [5] ), .I1 (\arp_data[21] [5] ), .I2 (\arp_data[20] [5] ), @@ -336011,7 +335463,7 @@ module arp_tx GTP_LUT5M /* \N820_42[6] */ #( .INIT(32'b11001100101010101111000010101010)) \N820_42[6] ( - .Z (_N20941), + .Z (_N20699), .I0 (\arp_data[19] [6] ), .I1 (\arp_data[21] [6] ), .I2 (\arp_data[20] [6] ), @@ -336023,7 +335475,7 @@ module arp_tx GTP_LUT5M /* \N820_42[7] */ #( .INIT(32'b11001100101010101111000010101010)) \N820_42[7] ( - .Z (_N20942), + .Z (_N20700), .I0 (\arp_data[19] [7] ), .I1 (\arp_data[21] [7] ), .I2 (\arp_data[20] [7] ), @@ -336035,103 +335487,103 @@ module arp_tx GTP_LUT5M /* \N820_43[0] */ #( .INIT(32'b11001110110000101010101010101010)) \N820_43[0] ( - .Z (_N20943), + .Z (_N20701), .I0 (\arp_data[22] [0] ), .I1 (cnt[0]), .I2 (cnt[1]), .I3 (\arp_data[23] [0] ), .I4 (cnt[2]), - .ID (_N20935)); + .ID (_N20693)); // LUT = (ID&~I4)|(I1&I3&I4)|(I0&~I1&~I2&I4)|(I1&I2&I4) ; GTP_LUT5M /* \N820_43[1] */ #( .INIT(32'b00001110000000101010101010101010)) \N820_43[1] ( - .Z (_N20944), + .Z (_N20702), .I0 (\arp_data[22] [1] ), .I1 (cnt[0]), .I2 (cnt[1]), .I3 (\arp_data[23] [1] ), .I4 (cnt[2]), - .ID (_N20936)); + .ID (_N20694)); // LUT = (ID&~I4)|(I1&~I2&I3&I4)|(I0&~I1&~I2&I4) ; GTP_LUT5M /* \N820_43[2] */ #( .INIT(32'b00001110000000101010101010101010)) \N820_43[2] ( - .Z (_N20945), + .Z (_N20703), .I0 (\arp_data[22] [2] ), .I1 (cnt[0]), .I2 (cnt[1]), .I3 (\arp_data[23] [2] ), .I4 (cnt[2]), - .ID (_N20937)); + .ID (_N20695)); // LUT = (ID&~I4)|(I1&~I2&I3&I4)|(I0&~I1&~I2&I4) ; GTP_LUT5M /* \N820_43[3] */ #( .INIT(32'b00001110000000101010101010101010)) \N820_43[3] ( - .Z (_N20946), + .Z (_N20704), .I0 (\arp_data[22] [3] ), .I1 (cnt[0]), .I2 (cnt[1]), .I3 (\arp_data[23] [3] ), .I4 (cnt[2]), - .ID (_N20938)); + .ID (_N20696)); // LUT = (ID&~I4)|(I1&~I2&I3&I4)|(I0&~I1&~I2&I4) ; GTP_LUT5M /* \N820_43[4] */ #( .INIT(32'b11001110110000101010101010101010)) \N820_43[4] ( - .Z (_N20947), + .Z (_N20705), .I0 (\arp_data[22] [4] ), .I1 (cnt[0]), .I2 (cnt[1]), .I3 (\arp_data[23] [4] ), .I4 (cnt[2]), - .ID (_N20939)); + .ID (_N20697)); // LUT = (ID&~I4)|(I1&I3&I4)|(I0&~I1&~I2&I4)|(I1&I2&I4) ; GTP_LUT5M /* \N820_43[5] */ #( .INIT(32'b00001110000000101010101010101010)) \N820_43[5] ( - .Z (_N20948), + .Z (_N20706), .I0 (\arp_data[22] [5] ), .I1 (cnt[0]), .I2 (cnt[1]), .I3 (\arp_data[23] [5] ), .I4 (cnt[2]), - .ID (_N20940)); + .ID (_N20698)); // LUT = (ID&~I4)|(I1&~I2&I3&I4)|(I0&~I1&~I2&I4) ; GTP_LUT5M /* \N820_43[6] */ #( .INIT(32'b00001110000000101010101010101010)) \N820_43[6] ( - .Z (_N20949), + .Z (_N20707), .I0 (\arp_data[22] [6] ), .I1 (cnt[0]), .I2 (cnt[1]), .I3 (\arp_data[23] [6] ), .I4 (cnt[2]), - .ID (_N20941)); + .ID (_N20699)); // LUT = (ID&~I4)|(I1&~I2&I3&I4)|(I0&~I1&~I2&I4) ; GTP_LUT5M /* \N820_43[7] */ #( .INIT(32'b00001110000000101010101010101010)) \N820_43[7] ( - .Z (_N20950), + .Z (_N20708), .I0 (\arp_data[22] [7] ), .I1 (cnt[0]), .I2 (cnt[1]), .I3 (\arp_data[23] [7] ), .I4 (cnt[2]), - .ID (_N20942)); + .ID (_N20700)); // LUT = (ID&~I4)|(I1&~I2&I3&I4)|(I0&~I1&~I2&I4) ; GTP_LUT3 /* \N820_48[7] */ #( .INIT(8'b01010011)) \N820_48[7] ( - .Z (_N20990), + .Z (_N20748), .I0 (crc_data[0]), .I1 (crc_data[8]), .I2 (cnt[0])); @@ -336140,8 +335592,8 @@ module arp_tx GTP_LUT5 /* \N820_49[7] */ #( .INIT(32'b00001111000011111001011001101001)) \N820_49[7] ( - .Z (_N20998), - .I0 (_N96846), + .Z (_N20756), + .I0 (_N97621), .I1 (gmii_txd_data[0]), .I2 (crc_data[16]), .I3 (crc_data[31]), @@ -336151,19 +335603,19 @@ module arp_tx GTP_LUT5M /* \N820_50[0] */ #( .INIT(32'b01010101001100110000111110011001)) \N820_50[0] ( - .Z (_N20999), + .Z (_N20757), .I0 (crc_data[7]), .I1 (crc_data[23]), .I2 (crc_data[15]), .I3 (cnt[1]), .I4 (cnt[0]), - .ID (_N96069)); + .ID (_N96855)); // LUT = (ID&I1&~I3&~I4)|(~I2&I3&~I4)|(~I1&~I3&I4)|(~I0&I3&I4)|(~ID&~I1&~I3) ; GTP_LUT5M /* \N820_50[1] */ #( .INIT(32'b01010101000011110011001101010101)) \N820_50[1] ( - .Z (_N21000), + .Z (_N20758), .I0 (crc_data[6]), .I1 (crc_data[14]), .I2 (crc_data[22]), @@ -336175,19 +335627,19 @@ module arp_tx GTP_LUT5M /* \N820_50[2] */ #( .INIT(32'b01010101001100110000111110011001)) \N820_50[2] ( - .Z (_N21001), + .Z (_N20759), .I0 (crc_data[5]), .I1 (crc_data[21]), .I2 (crc_data[13]), .I3 (cnt[1]), .I4 (cnt[0]), - .ID (_N97055)); + .ID (_N97817)); // LUT = (ID&I1&~I3&~I4)|(~I2&I3&~I4)|(~I1&~I3&I4)|(~I0&I3&I4)|(~ID&~I1&~I3) ; GTP_LUT5M /* \N820_50[3] */ #( .INIT(32'b01010101000011110011001101010101)) \N820_50[3] ( - .Z (_N21002), + .Z (_N20760), .I0 (crc_data[4]), .I1 (crc_data[12]), .I2 (crc_data[20]), @@ -336199,7 +335651,7 @@ module arp_tx GTP_LUT5M /* \N820_50[4] */ #( .INIT(32'b01010101000011110011001101010101)) \N820_50[4] ( - .Z (_N21003), + .Z (_N20761), .I0 (crc_data[3]), .I1 (crc_data[11]), .I2 (crc_data[19]), @@ -336211,7 +335663,7 @@ module arp_tx GTP_LUT5M /* \N820_50[5] */ #( .INIT(32'b01010101000011110011001101010101)) \N820_50[5] ( - .Z (_N21004), + .Z (_N20762), .I0 (crc_data[2]), .I1 (crc_data[10]), .I2 (crc_data[18]), @@ -336223,33 +335675,33 @@ module arp_tx GTP_LUT5M /* \N820_50[6] */ #( .INIT(32'b01010101001100110000111110011001)) \N820_50[6] ( - .Z (_N21005), + .Z (_N20763), .I0 (crc_data[1]), .I1 (crc_data[17]), .I2 (crc_data[9]), .I3 (cnt[1]), .I4 (cnt[0]), - .ID (_N97057)); + .ID (_N97819)); // LUT = (ID&I1&~I3&~I4)|(~I2&I3&~I4)|(~I1&~I3&I4)|(~I0&I3&I4)|(~ID&~I1&~I3) ; GTP_LUT5M /* \N820_51[7] */ #( .INIT(32'b10100000000000001010110010101100)) \N820_51[7] ( - .Z (_N21014), + .Z (_N20772), .I0 (cnt[0]), - .I1 (_N20998), + .I1 (_N20756), .I2 (cnt[1]), .I3 (cnt[2]), .I4 (N411), - .ID (_N20990)); + .ID (_N20748)); // LUT = (I1&~I2&~I4)|(ID&I2&~I4)|(I0&I2&I3&I4) ; GTP_LUT5M /* \N820_53[0] */ #( .INIT(32'b10101010101010101111111000001110)) \N820_53[0] ( - .Z (_N21023), - .I0 (_N20943), - .I1 (_N20999), + .Z (_N20781), + .I0 (_N20701), + .I1 (_N20757), .I2 (N419), .I3 (N219[0]), .I4 (N416), @@ -336259,9 +335711,9 @@ module arp_tx GTP_LUT5M /* \N820_53[1] */ #( .INIT(32'b10101010101010101111010000000100)) \N820_53[1] ( - .Z (_N21024), - .I0 (_N20944), - .I1 (_N21000), + .Z (_N20782), + .I0 (_N20702), + .I1 (_N20758), .I2 (N419), .I3 (N219[1]), .I4 (N416), @@ -336271,57 +335723,57 @@ module arp_tx GTP_LUT5M /* \N820_53[2] */ #( .INIT(32'b10101010101010101111111000001110)) \N820_53[2] ( - .Z (_N21025), - .I0 (_N20945), + .Z (_N20783), + .I0 (_N20703), .I1 (N411), .I2 (N419), .I3 (N219[2]), .I4 (N416), - .ID (_N21001)); + .ID (_N20759)); // LUT = (I2&I3&~I4)|(I1&~I2&~I4)|(ID&~I2&~I4)|(I0&I4) ; GTP_LUT5M /* \N820_53[3] */ #( .INIT(32'b10101010101010101111001000000010)) \N820_53[3] ( - .Z (_N21026), - .I0 (_N20946), + .Z (_N20784), + .I0 (_N20704), .I1 (N411), .I2 (N419), .I3 (N219[3]), .I4 (N416), - .ID (_N21002)); + .ID (_N20760)); // LUT = (I2&I3&~I4)|(ID&~I1&~I2&~I4)|(I0&I4) ; GTP_LUT5M /* \N820_53[4] */ #( .INIT(32'b10101010101010101111111000001110)) \N820_53[4] ( - .Z (_N21027), - .I0 (_N20947), + .Z (_N20785), + .I0 (_N20705), .I1 (N411), .I2 (N419), .I3 (N219[4]), .I4 (N416), - .ID (_N21003)); + .ID (_N20761)); // LUT = (I2&I3&~I4)|(I1&~I2&~I4)|(ID&~I2&~I4)|(I0&I4) ; GTP_LUT5M /* \N820_53[5] */ #( .INIT(32'b10101010101010101111001000000010)) \N820_53[5] ( - .Z (_N21028), - .I0 (_N20948), + .Z (_N20786), + .I0 (_N20706), .I1 (N411), .I2 (N419), .I3 (N219[5]), .I4 (N416), - .ID (_N21004)); + .ID (_N20762)); // LUT = (I2&I3&~I4)|(ID&~I1&~I2&~I4)|(I0&I4) ; GTP_LUT5M /* \N820_53[6] */ #( .INIT(32'b10101010101010101111111000001110)) \N820_53[6] ( - .Z (_N21029), - .I0 (_N20949), - .I1 (_N21005), + .Z (_N20787), + .I0 (_N20707), + .I1 (_N20763), .I2 (N419), .I3 (N219[6]), .I4 (N416), @@ -336331,104 +335783,104 @@ module arp_tx GTP_LUT5M /* \N820_54[7] */ #( .INIT(32'b00000000101010101111000011100010)) \N820_54[7] ( - .Z (_N21038), - .I0 (_N20950), + .Z (_N20796), + .I0 (_N20708), .I1 (N419), .I2 (N219[7]), .I3 (cnt[3]), .I4 (N416), - .ID (_N21014)); + .ID (_N20772)); // LUT = (ID&~I1&~I3&~I4)|(I2&I3&~I4)|(I1&I2&~I4)|(I0&~I3&I4) ; GTP_LUT5M /* \N820_56[0] */ #( .INIT(32'b11001100110010101100110011001010)) \N820_56[0] ( .Z (N820[0]), - .I0 (_N20887), + .I0 (_N20645), .I1 (N219[0]), .I2 (cnt[4]), .I3 (cnt[5]), .I4 (cnt[3]), - .ID (_N21023)); + .ID (_N20781)); // LUT = (ID&~I2&~I3&~I4)|(I0&~I2&~I3&I4)|(I1&I3)|(I1&I2) ; GTP_LUT5M /* \N820_56[1] */ #( .INIT(32'b11001100110010101100110011001010)) \N820_56[1] ( .Z (N820[1]), - .I0 (_N20888), + .I0 (_N20646), .I1 (N219[1]), .I2 (cnt[4]), .I3 (cnt[5]), .I4 (cnt[3]), - .ID (_N21024)); + .ID (_N20782)); // LUT = (ID&~I2&~I3&~I4)|(I0&~I2&~I3&I4)|(I1&I3)|(I1&I2) ; GTP_LUT5M /* \N820_56[2] */ #( .INIT(32'b11001100110010101100110011001010)) \N820_56[2] ( .Z (N820[2]), - .I0 (_N20889), + .I0 (_N20647), .I1 (N219[2]), .I2 (cnt[4]), .I3 (cnt[5]), .I4 (cnt[3]), - .ID (_N21025)); + .ID (_N20783)); // LUT = (ID&~I2&~I3&~I4)|(I0&~I2&~I3&I4)|(I1&I3)|(I1&I2) ; GTP_LUT5M /* \N820_56[3] */ #( .INIT(32'b11001100110010101100110011001010)) \N820_56[3] ( .Z (N820[3]), - .I0 (_N20890), + .I0 (_N20648), .I1 (N219[3]), .I2 (cnt[4]), .I3 (cnt[5]), .I4 (cnt[3]), - .ID (_N21026)); + .ID (_N20784)); // LUT = (ID&~I2&~I3&~I4)|(I0&~I2&~I3&I4)|(I1&I3)|(I1&I2) ; GTP_LUT5M /* \N820_56[4] */ #( .INIT(32'b11001100110010101100110011001010)) \N820_56[4] ( .Z (N820[4]), - .I0 (_N20891), + .I0 (_N20649), .I1 (N219[4]), .I2 (cnt[4]), .I3 (cnt[5]), .I4 (cnt[3]), - .ID (_N21027)); + .ID (_N20785)); // LUT = (ID&~I2&~I3&~I4)|(I0&~I2&~I3&I4)|(I1&I3)|(I1&I2) ; GTP_LUT5M /* \N820_56[5] */ #( .INIT(32'b11001100110010101100110011001010)) \N820_56[5] ( .Z (N820[5]), - .I0 (_N20892), + .I0 (_N20650), .I1 (N219[5]), .I2 (cnt[4]), .I3 (cnt[5]), .I4 (cnt[3]), - .ID (_N21028)); + .ID (_N20786)); // LUT = (ID&~I2&~I3&~I4)|(I0&~I2&~I3&I4)|(I1&I3)|(I1&I2) ; GTP_LUT5M /* \N820_56[6] */ #( .INIT(32'b11001100110010101100110011001010)) \N820_56[6] ( .Z (N820[6]), - .I0 (_N20893), + .I0 (_N20651), .I1 (N219[6]), .I2 (cnt[4]), .I3 (cnt[5]), .I4 (cnt[3]), - .ID (_N21029)); + .ID (_N20787)); // LUT = (ID&~I2&~I3&~I4)|(I0&~I2&~I3&I4)|(I1&I3)|(I1&I2) ; GTP_LUT4 /* \N820_56[7] */ #( .INIT(16'b1100110011001010)) \N820_56[7] ( .Z (N820[7]), - .I0 (_N21038), + .I0 (_N20796), .I1 (N219[7]), .I2 (cnt[4]), .I3 (cnt[5])); @@ -336444,15 +335896,6 @@ module arp_tx // defparam N832_vname.orig_name = N832; // LUT = (I0&I1)|(I0&I2) ; - GTP_LUT3 /* N832_1 */ #( - .INIT(8'b00000001)) - N832_1 ( - .Z (_N96002), - .I0 (cnt[3]), - .I1 (cnt[4]), - .I2 (cnt[5])); - // LUT = ~I0&~I1&~I2 ; - GTP_DFF_PE /* \arp_data[7][0] */ #( .GRS_EN("TRUE"), .INIT(1'b1)) @@ -337374,7 +336817,7 @@ module arp_tx .C (sync_vg_100m), .CE (N765), .CLK (clk), - .D (_N38189)); + .D (_N35874)); // ../../sources/designs/udp_osd/eth_udp/arp/arp_tx.v:133 GTP_DFF_CE /* \cnt[2] */ #( @@ -337385,7 +336828,7 @@ module arp_tx .C (sync_vg_100m), .CE (N765), .CLK (clk), - .D (_N38287)); + .D (_N35965)); // ../../sources/designs/udp_osd/eth_udp/arp/arp_tx.v:133 GTP_DFF_CE /* \cnt[3] */ #( @@ -337413,8 +336856,8 @@ module arp_tx GTP_LUT5 /* \cnt[5:0]_0 */ #( .INIT(32'b00001100000000001010101000000000)) \cnt[5:0]_0 ( - .Z (_N38189), - .I0 (_N38191), + .Z (_N35874), + .I0 (_N35876), .I1 (N419), .I2 (N420), .I3 (N185[1]), @@ -337424,11 +336867,11 @@ module arp_tx GTP_LUT5M /* \cnt[5:0]_3 */ #( .INIT(32'b11011111110011101101111111011100)) \cnt[5:0]_3 ( - .Z (_N38191), + .Z (_N35876), .I0 (cur_state_reg[0]), .I1 (next_state[4]), .I2 (cur_state_reg[1]), - .I3 (_N96700), + .I3 (_N97102), .I4 (skip_en), .ID (cur_state_reg[2])); // LUT = (~ID&I2&~I4)|(~I0&I3&I4)|(I0&~I2&I4)|(~I2&I3)|(I1) ; @@ -337436,8 +336879,8 @@ module arp_tx GTP_LUT5 /* \cnt[5:0]_5 */ #( .INIT(32'b00001100000000001010101000000000)) \cnt[5:0]_5 ( - .Z (_N38287), - .I0 (_N38289), + .Z (_N35965), + .I0 (_N35967), .I1 (N416), .I2 (N418), .I3 (N185[2]), @@ -337447,31 +336890,31 @@ module arp_tx GTP_LUT5 /* \cnt[5:0]_8 */ #( .INIT(32'b11111100110111001111110011110100)) \cnt[5:0]_8 ( - .Z (_N96700), - .I0 (_N96807), + .Z (_N97102), + .I0 (_N97789), .I1 (N416), .I2 (N419), .I3 (cnt[4]), .I4 (cnt[5])); // LUT = (I2&~I4)|(~I0&I1)|(~I0&I2)|(I1&I3)|(I1&I4)|(I2&I3) ; - GTP_LUT5M /* \cnt[5:0]_89 */ #( + GTP_LUT5M /* \cnt[5:0]_85 */ #( .INIT(32'b00001010000010100011001110101010)) - \cnt[5:0]_89 ( - .Z (_N38289), + \cnt[5:0]_85 ( + .Z (_N35967), .I0 (N419), .I1 (N427), .I2 (N420), .I3 (next_state[4]), .I4 (next_state[3]), - .ID (_N38293)); + .ID (_N35971)); // LUT = (ID&~I3&~I4)|(~I1&I3&~I4)|(I0&~I2&I4) ; - GTP_LUT4 /* \cnt[5:0]_93 */ #( + GTP_LUT4 /* \cnt[5:0]_89 */ #( .INIT(16'b1111101111101010)) - \cnt[5:0]_93 ( - .Z (_N38293), - .I0 (_N96700), + \cnt[5:0]_89 ( + .Z (_N35971), + .I0 (_N97102), .I1 (skip_en), .I2 (cur_state_reg[0]), .I3 (cur_state_reg[1])); @@ -337505,7 +336948,7 @@ module arp_tx .Q (crc_en), .C (sync_vg_100m), .CLK (clk), - .D (_N96575)); + .D (_N97318)); // defparam crc_en_vname.orig_name = crc_en; // ../../sources/designs/udp_osd/eth_udp/arp/arp_tx.v:133 @@ -337617,7 +337060,7 @@ module arp_tx .C (sync_vg_100m), .CE (N781), .CLK (clk), - .D (_N38515)); + .D (_N37392)); // ../../sources/designs/udp_osd/eth_udp/arp/arp_tx.v:133 GTP_DFF_CE /* \data_cnt[1] */ #( @@ -337628,7 +337071,7 @@ module arp_tx .C (sync_vg_100m), .CE (N781), .CLK (clk), - .D (_N38547)); + .D (_N37426)); // ../../sources/designs/udp_osd/eth_udp/arp/arp_tx.v:133 GTP_DFF_CE /* \data_cnt[2] */ #( @@ -337639,7 +337082,7 @@ module arp_tx .C (sync_vg_100m), .CE (N781), .CLK (clk), - .D (_N38601)); + .D (_N37488)); // ../../sources/designs/udp_osd/eth_udp/arp/arp_tx.v:133 GTP_DFF_CE /* \data_cnt[3] */ #( @@ -337650,23 +337093,23 @@ module arp_tx .C (sync_vg_100m), .CE (N781), .CLK (clk), - .D (_N38717)); + .D (_N37558)); // ../../sources/designs/udp_osd/eth_udp/arp/arp_tx.v:133 - GTP_LUT4 /* \data_cnt[4:0]_1032 */ #( + GTP_LUT4 /* \data_cnt[4:0]_801 */ #( .INIT(16'b0001010101010101)) - \data_cnt[4:0]_1032 ( - .Z (_N38515), + \data_cnt[4:0]_801 ( + .Z (_N37392), .I0 (data_cnt[0]), .I1 (data_cnt[2]), .I2 (data_cnt[3]), .I3 (data_cnt[4])); // LUT = (~I0&~I3)|(~I0&~I2)|(~I0&~I1) ; - GTP_LUT5 /* \data_cnt[4:0]_1040 */ #( + GTP_LUT5 /* \data_cnt[4:0]_809 */ #( .INIT(32'b00000110011001100110011001100110)) - \data_cnt[4:0]_1040 ( - .Z (_N38547), + \data_cnt[4:0]_809 ( + .Z (_N37426), .I0 (data_cnt[0]), .I1 (data_cnt[1]), .I2 (data_cnt[2]), @@ -337674,10 +337117,10 @@ module arp_tx .I4 (data_cnt[4])); // LUT = (I0&~I1&~I4)|(~I0&I1&~I4)|(I0&~I1&~I3)|(~I0&I1&~I3)|(I0&~I1&~I2)|(~I0&I1&~I2) ; - GTP_LUT5 /* \data_cnt[4:0]_1048 */ #( + GTP_LUT5 /* \data_cnt[4:0]_818 */ #( .INIT(32'b00001000011110000111100001111000)) - \data_cnt[4:0]_1048 ( - .Z (_N38601), + \data_cnt[4:0]_818 ( + .Z (_N37488), .I0 (data_cnt[0]), .I1 (data_cnt[1]), .I2 (data_cnt[2]), @@ -337685,10 +337128,10 @@ module arp_tx .I4 (data_cnt[4])); // LUT = (~I1&I2&~I4)|(~I0&I2&~I4)|(~I1&I2&~I3)|(~I0&I2&~I3)|(I0&I1&~I2) ; - GTP_LUT5 /* \data_cnt[4:0]_1066 */ #( + GTP_LUT5 /* \data_cnt[4:0]_830 */ #( .INIT(32'b00001111100000000111111110000000)) - \data_cnt[4:0]_1066 ( - .Z (_N38717), + \data_cnt[4:0]_830 ( + .Z (_N37558), .I0 (data_cnt[0]), .I1 (data_cnt[1]), .I2 (data_cnt[2]), @@ -337696,10 +337139,10 @@ module arp_tx .I4 (data_cnt[4])); // LUT = (~I2&I3)|(~I1&I3&~I4)|(~I0&I3&~I4)|(I0&I1&I2&~I3) ; - GTP_LUT5 /* \data_cnt[4:0]_1071 */ #( + GTP_LUT5 /* \data_cnt[4:0]_838 */ #( .INIT(32'b00001111111111111000000000000000)) - \data_cnt[4:0]_1071 ( - .Z (_N38750), + \data_cnt[4:0]_838 ( + .Z (_N37634), .I0 (data_cnt[0]), .I1 (data_cnt[1]), .I2 (data_cnt[2]), @@ -337715,7 +337158,7 @@ module arp_tx .C (sync_vg_100m), .CE (N781), .CLK (clk), - .D (_N38750)); + .D (_N37634)); // ../../sources/designs/udp_osd/eth_udp/arp/arp_tx.v:133 GTP_DFF_CE /* \gmii_txd_data[0] */ #( @@ -337885,32 +337328,24 @@ module crc32_d8 input \udp_osd_inst/eth_udp_inst/arp_tx_done , output [31:0] crc_data, output [31:0] crc_next, - output _N96069, - output _N96846, - output _N97055, - output _N97057 + output _N96855, + output _N97621, + output _N97817, + output _N97819 ); wire N263; wire [31:0] N264; - wire _N95977; - wire _N96081; - wire _N96842; - wire _N96843; - wire _N97028; - wire _N97029; - wire _N97058; - wire _N107804; - wire _N107806; - wire _N107809; - wire _N107811; - - GTP_LUT2 /* N3_1 */ #( - .INIT(4'b0110)) - N3_1 ( - .Z (_N95977), - .I0 (data[0]), - .I1 (crc_data[31])); - // LUT = (I0&~I1)|(~I0&I1) ; + wire _N96853; + wire _N96856; + wire _N97617; + wire _N97618; + wire _N97812; + wire _N97813; + wire _N97820; + wire _N108636; + wire _N108638; + wire _N108641; + wire _N108643; GTP_LUT4 /* N39_1 */ #( .INIT(16'b0110100110010110)) @@ -337925,7 +337360,7 @@ module crc32_d8 GTP_LUT4 /* N75_1 */ #( .INIT(16'b0110100110010110)) N75_1 ( - .Z (_N96842), + .Z (_N97617), .I0 (data[0]), .I1 (data[1]), .I2 (crc_data[30]), @@ -337935,34 +337370,50 @@ module crc32_d8 GTP_LUT2 /* N84_1 */ #( .INIT(4'b0110)) N84_1 ( - .Z (_N96081), - .I0 (data[3]), - .I1 (crc_data[28])); + .Z (_N96853), + .I0 (data[0]), + .I1 (crc_data[31])); // LUT = (I0&~I1)|(~I0&I1) ; - GTP_LUT2 /* N102_2 */ #( + GTP_LUT2 /* N102_1 */ #( .INIT(4'b0110)) - N102_2 ( - .Z (_N107811), + N102_1 ( + .Z (_N96855), + .I0 (data[2]), + .I1 (crc_data[29])); + // LUT = (I0&~I1)|(~I0&I1) ; + + GTP_LUT2 /* N102_3 */ #( + .INIT(4'b0110)) + N102_3 ( + .Z (_N108643), .I0 (data[4]), .I1 (crc_data[27])); // LUT = (I0&~I1)|(~I0&I1) ; - GTP_LUT5 /* N102_7 */ #( + GTP_LUT5 /* N102_8 */ #( .INIT(32'b10010110011010010110100110010110)) - N102_7 ( - .Z (_N97028), + N102_8 ( + .Z (_N97812), .I0 (data[5]), .I1 (data[7]), .I2 (crc_data[24]), .I3 (crc_data[26]), - .I4 (_N107811)); + .I4 (_N108643)); // LUT = (I0&~I1&~I2&~I3&~I4)|(~I0&I1&~I2&~I3&~I4)|(~I0&~I1&I2&~I3&~I4)|(I0&I1&I2&~I3&~I4)|(~I0&~I1&~I2&I3&~I4)|(I0&I1&~I2&I3&~I4)|(I0&~I1&I2&I3&~I4)|(~I0&I1&I2&I3&~I4)|(~I0&~I1&~I2&~I3&I4)|(I0&I1&~I2&~I3&I4)|(I0&~I1&I2&~I3&I4)|(~I0&I1&I2&~I3&I4)|(I0&~I1&~I2&I3&I4)|(~I0&I1&~I2&I3&I4)|(~I0&~I1&I2&I3&I4)|(I0&I1&I2&I3&I4) ; + GTP_LUT2 /* N111_1 */ #( + .INIT(4'b0110)) + N111_1 ( + .Z (_N96856), + .I0 (data[3]), + .I1 (crc_data[28])); + // LUT = (I0&~I1)|(~I0&I1) ; + GTP_LUT5 /* N148_2 */ #( .INIT(32'b10010110011010010110100110010110)) N148_2 ( - .Z (_N107804), + .Z (_N108636), .I0 (data[3]), .I1 (data[4]), .I2 (crc_data[6]), @@ -337974,7 +337425,7 @@ module crc32_d8 .INIT(32'b10010110011010010110100110010110)) N183_4 ( .Z (crc_next[1]), - .I0 (_N96842), + .I0 (_N97617), .I1 (data[6]), .I2 (data[7]), .I3 (crc_data[24]), @@ -337984,7 +337435,7 @@ module crc32_d8 GTP_LUT4 /* N186_1 */ #( .INIT(16'b0110100110010110)) N186_1 ( - .Z (_N96846), + .Z (_N97621), .I0 (data[5]), .I1 (data[6]), .I2 (crc_data[25]), @@ -337994,7 +337445,7 @@ module crc32_d8 GTP_LUT4 /* N189_1 */ #( .INIT(16'b0110100110010110)) N189_1 ( - .Z (_N96843), + .Z (_N97618), .I0 (data[2]), .I1 (data[3]), .I2 (crc_data[28]), @@ -338004,7 +337455,7 @@ module crc32_d8 GTP_LUT3 /* N192_4 */ #( .INIT(8'b10010110)) N192_4 ( - .Z (_N97029), + .Z (_N97813), .I0 (data[5]), .I1 (crc_data[25]), .I2 (crc_data[26])); @@ -338013,31 +337464,23 @@ module crc32_d8 GTP_LUT4 /* N199_1 */ #( .INIT(16'b0110100110010110)) N199_1 ( - .Z (_N97057), + .Z (_N97819), .I0 (data[4]), .I1 (data[5]), .I2 (crc_data[26]), .I3 (crc_data[27])); // LUT = (I0&~I1&~I2&~I3)|(~I0&I1&~I2&~I3)|(~I0&~I1&I2&~I3)|(I0&I1&I2&~I3)|(~I0&~I1&~I2&I3)|(I0&I1&~I2&I3)|(I0&~I1&I2&I3)|(~I0&I1&I2&I3) ; - GTP_LUT4 /* N206_2 */ #( + GTP_LUT4 /* N206_1 */ #( .INIT(16'b0110100110010110)) - N206_2 ( - .Z (_N97058), + N206_1 ( + .Z (_N97820), .I0 (data[1]), .I1 (data[2]), .I2 (crc_data[29]), .I3 (crc_data[30])); // LUT = (I0&~I1&~I2&~I3)|(~I0&I1&~I2&~I3)|(~I0&~I1&I2&~I3)|(I0&I1&I2&~I3)|(~I0&~I1&~I2&I3)|(I0&I1&~I2&I3)|(I0&~I1&I2&I3)|(~I0&I1&I2&I3) ; - GTP_LUT2 /* N211_1 */ #( - .INIT(4'b0110)) - N211_1 ( - .Z (_N96069), - .I0 (data[2]), - .I1 (crc_data[29])); - // LUT = (I0&~I1)|(~I0&I1) ; - GTP_LUT5 /* N220_3 */ #( .INIT(32'b10010110011010010110100110010110)) N220_3 ( @@ -338046,24 +337489,24 @@ module crc32_d8 .I1 (crc_data[18]), .I2 (crc_data[28]), .I3 (crc_next[0]), - .I4 (_N107811)); + .I4 (_N108643)); // LUT = (I0&~I1&~I2&~I3&~I4)|(~I0&I1&~I2&~I3&~I4)|(~I0&~I1&I2&~I3&~I4)|(I0&I1&I2&~I3&~I4)|(~I0&~I1&~I2&I3&~I4)|(I0&I1&~I2&I3&~I4)|(I0&~I1&I2&I3&~I4)|(~I0&I1&I2&I3&~I4)|(~I0&~I1&~I2&~I3&I4)|(I0&I1&~I2&~I3&I4)|(I0&~I1&I2&~I3&I4)|(~I0&I1&I2&~I3&I4)|(I0&~I1&~I2&I3&I4)|(~I0&I1&~I2&I3&I4)|(~I0&~I1&I2&I3&I4)|(I0&I1&I2&I3&I4) ; GTP_LUT5 /* N229_1 */ #( .INIT(32'b10010110011010010110100110010110)) N229_1 ( - .Z (_N97055), + .Z (_N97817), .I0 (data[0]), .I1 (data[1]), .I2 (crc_data[30]), .I3 (crc_data[31]), - .I4 (_N107811)); + .I4 (_N108643)); // LUT = (I0&~I1&~I2&~I3&~I4)|(~I0&I1&~I2&~I3&~I4)|(~I0&~I1&I2&~I3&~I4)|(I0&I1&I2&~I3&~I4)|(~I0&~I1&~I2&I3&~I4)|(I0&I1&~I2&I3&~I4)|(I0&~I1&I2&I3&~I4)|(~I0&I1&I2&I3&~I4)|(~I0&~I1&~I2&~I3&I4)|(I0&I1&~I2&~I3&I4)|(I0&~I1&I2&~I3&I4)|(~I0&I1&I2&~I3&I4)|(I0&~I1&~I2&I3&I4)|(~I0&I1&~I2&I3&I4)|(~I0&~I1&I2&I3&I4)|(I0&I1&I2&I3&I4) ; GTP_LUT5 /* N229_6 */ #( .INIT(32'b10010110011010010110100110010110)) N229_6 ( - .Z (_N107809), + .Z (_N108641), .I0 (data[0]), .I1 (data[6]), .I2 (crc_data[19]), @@ -338075,8 +337518,8 @@ module crc32_d8 .INIT(32'b10010110011010010110100110010110)) N229_7 ( .Z (crc_next[27]), - .I0 (_N95977), - .I1 (_N96843), + .I0 (_N96853), + .I1 (_N97618), .I2 (data[6]), .I3 (crc_data[19]), .I4 (crc_data[25])); @@ -338086,7 +337529,7 @@ module crc32_d8 .INIT(16'b0110100110010110)) N236_5 ( .Z (crc_next[28]), - .I0 (_N97058), + .I0 (_N97820), .I1 (data[5]), .I2 (crc_data[20]), .I3 (crc_data[26])); @@ -338095,7 +337538,7 @@ module crc32_d8 GTP_LUT4 /* N243_2 */ #( .INIT(16'b0110100110010110)) N243_2 ( - .Z (_N107806), + .Z (_N108638), .I0 (data[6]), .I1 (data[7]), .I2 (crc_data[24]), @@ -338159,11 +337602,11 @@ module crc32_d8 .INIT(32'b11011110111011011110110111011110)) \N264[3] ( .Z (N264[3]), - .I0 (_N96846), + .I0 (_N97621), .I1 (\udp_osd_inst/eth_udp_inst/arp_tx_done ), .I2 (data[0]), .I3 (crc_data[31]), - .I4 (_N107811)); + .I4 (_N108643)); // LUT = (I1)|(I0&~I2&~I3&~I4)|(~I0&I2&~I3&~I4)|(~I0&~I2&I3&~I4)|(I0&I2&I3&~I4)|(~I0&~I2&~I3&I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(~I0&I2&I3&I4) ; // ../../sources/designs/udp_osd/eth_udp/arp/crc32_d8.v:80 @@ -338171,8 +337614,8 @@ module crc32_d8 .INIT(32'b11110110111110011111100111110110)) \N264[4] ( .Z (N264[4]), - .I0 (_N96081), - .I1 (_N97028), + .I0 (_N96856), + .I1 (_N97812), .I2 (\udp_osd_inst/eth_udp_inst/arp_tx_done ), .I3 (data[1]), .I4 (crc_data[30])); @@ -338183,7 +337626,7 @@ module crc32_d8 .INIT(32'b11011110111011011110110111011110)) \N264[5] ( .Z (N264[5]), - .I0 (_N96843), + .I0 (_N97618), .I1 (\udp_osd_inst/eth_udp_inst/arp_tx_done ), .I2 (data[4]), .I3 (crc_data[27]), @@ -338195,9 +337638,9 @@ module crc32_d8 .INIT(32'b11111111011010011111111110010110)) \N264[6] ( .Z (N264[6]), - .I0 (_N96842), - .I1 (_N96843), - .I2 (_N97029), + .I0 (_N97617), + .I1 (_N97618), + .I2 (_N97813), .I3 (\udp_osd_inst/eth_udp_inst/arp_tx_done ), .I4 (data[6])); // LUT = (I3)|(I0&~I1&~I2&~I4)|(~I0&I1&~I2&~I4)|(~I0&~I1&I2&~I4)|(I0&I1&I2&~I4)|(~I0&~I1&~I2&I4)|(I0&I1&~I2&I4)|(I0&~I1&I2&I4)|(~I0&I1&I2&I4) ; @@ -338207,8 +337650,8 @@ module crc32_d8 .INIT(32'b11110110111110011111100111110110)) \N264[7] ( .Z (N264[7]), - .I0 (_N95977), - .I1 (_N97028), + .I0 (_N96853), + .I1 (_N97812), .I2 (\udp_osd_inst/eth_udp_inst/arp_tx_done ), .I3 (data[2]), .I4 (crc_data[29])); @@ -338219,11 +337662,11 @@ module crc32_d8 .INIT(32'b11011110111011011110110111011110)) \N264[8] ( .Z (N264[8]), - .I0 (_N96081), + .I0 (_N96856), .I1 (\udp_osd_inst/eth_udp_inst/arp_tx_done ), .I2 (crc_data[0]), - .I3 (_N107806), - .I4 (_N107811)); + .I3 (_N108638), + .I4 (_N108643)); // LUT = (I1)|(I0&~I2&~I3&~I4)|(~I0&I2&~I3&~I4)|(~I0&~I2&I3&~I4)|(I0&I2&I3&~I4)|(~I0&~I2&~I3&I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(~I0&I2&I3&I4) ; // ../../sources/designs/udp_osd/eth_udp/arp/crc32_d8.v:80 @@ -338231,8 +337674,8 @@ module crc32_d8 .INIT(16'b1111100111110110)) \N264[9] ( .Z (N264[9]), - .I0 (_N96843), - .I1 (_N96846), + .I0 (_N97618), + .I1 (_N97621), .I2 (\udp_osd_inst/eth_udp_inst/arp_tx_done ), .I3 (crc_data[1])); // LUT = (I2)|(I0&~I1&~I3)|(~I0&I1&~I3)|(~I0&~I1&I3)|(I0&I1&I3) ; @@ -338242,7 +337685,7 @@ module crc32_d8 .INIT(32'b11011110111011011110110111011110)) \N264[10] ( .Z (N264[10]), - .I0 (_N97028), + .I0 (_N97812), .I1 (\udp_osd_inst/eth_udp_inst/arp_tx_done ), .I2 (data[2]), .I3 (crc_data[2]), @@ -338254,11 +337697,11 @@ module crc32_d8 .INIT(32'b11011110111011011110110111011110)) \N264[11] ( .Z (N264[11]), - .I0 (_N96081), + .I0 (_N96856), .I1 (\udp_osd_inst/eth_udp_inst/arp_tx_done ), .I2 (crc_data[3]), - .I3 (_N107806), - .I4 (_N107811)); + .I3 (_N108638), + .I4 (_N108643)); // LUT = (I1)|(I0&~I2&~I3&~I4)|(~I0&I2&~I3&~I4)|(~I0&~I2&I3&~I4)|(I0&I2&I3&~I4)|(~I0&~I2&~I3&I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(~I0&I2&I3&I4) ; // ../../sources/designs/udp_osd/eth_udp/arp/crc32_d8.v:80 @@ -338266,8 +337709,8 @@ module crc32_d8 .INIT(32'b11110110111110011111100111110110)) \N264[12] ( .Z (N264[12]), - .I0 (_N96843), - .I1 (_N96846), + .I0 (_N97618), + .I1 (_N97621), .I2 (\udp_osd_inst/eth_udp_inst/arp_tx_done ), .I3 (crc_data[4]), .I4 (crc_next[0])); @@ -338278,9 +337721,9 @@ module crc32_d8 .INIT(32'b11111111011010011111111110010110)) \N264[13] ( .Z (N264[13]), - .I0 (_N96069), - .I1 (_N96846), - .I2 (_N97055), + .I0 (_N96855), + .I1 (_N97621), + .I2 (_N97817), .I3 (\udp_osd_inst/eth_udp_inst/arp_tx_done ), .I4 (crc_data[5])); // LUT = (I3)|(I0&~I1&~I2&~I4)|(~I0&I1&~I2&~I4)|(~I0&~I1&I2&~I4)|(I0&I1&I2&~I4)|(~I0&~I1&~I2&I4)|(I0&I1&~I2&I4)|(I0&~I1&I2&I4)|(~I0&I1&I2&I4) ; @@ -338290,11 +337733,11 @@ module crc32_d8 .INIT(32'b11011110111011011110110111011110)) \N264[14] ( .Z (N264[14]), - .I0 (_N96842), + .I0 (_N97617), .I1 (\udp_osd_inst/eth_udp_inst/arp_tx_done ), .I2 (data[5]), .I3 (crc_data[26]), - .I4 (_N107804)); + .I4 (_N108636)); // LUT = (I1)|(I0&~I2&~I3&~I4)|(~I0&I2&~I3&~I4)|(~I0&~I2&I3&~I4)|(I0&I2&I3&~I4)|(~I0&~I2&~I3&I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(~I0&I2&I3&I4) ; // ../../sources/designs/udp_osd/eth_udp/arp/crc32_d8.v:80 @@ -338302,11 +337745,11 @@ module crc32_d8 .INIT(32'b11110110111110011111100111110110)) \N264[15] ( .Z (N264[15]), - .I0 (_N95977), - .I1 (_N96843), + .I0 (_N96853), + .I1 (_N97618), .I2 (\udp_osd_inst/eth_udp_inst/arp_tx_done ), .I3 (crc_data[7]), - .I4 (_N107811)); + .I4 (_N108643)); // LUT = (I2)|(I0&~I1&~I3&~I4)|(~I0&I1&~I3&~I4)|(~I0&~I1&I3&~I4)|(I0&I1&I3&~I4)|(~I0&~I1&~I3&I4)|(I0&I1&~I3&I4)|(I0&~I1&I3&I4)|(~I0&I1&I3&I4) ; // ../../sources/designs/udp_osd/eth_udp/arp/crc32_d8.v:80 @@ -338314,7 +337757,7 @@ module crc32_d8 .INIT(32'b11011110111011011110110111011110)) \N264[16] ( .Z (N264[16]), - .I0 (_N96843), + .I0 (_N97618), .I1 (\udp_osd_inst/eth_udp_inst/arp_tx_done ), .I2 (data[7]), .I3 (crc_data[8]), @@ -338326,7 +337769,7 @@ module crc32_d8 .INIT(32'b11011110111011011110110111011110)) \N264[17] ( .Z (N264[17]), - .I0 (_N97058), + .I0 (_N97820), .I1 (\udp_osd_inst/eth_udp_inst/arp_tx_done ), .I2 (data[6]), .I3 (crc_data[9]), @@ -338338,7 +337781,7 @@ module crc32_d8 .INIT(32'b11011110111011011110110111011110)) \N264[18] ( .Z (N264[18]), - .I0 (_N96842), + .I0 (_N97617), .I1 (\udp_osd_inst/eth_udp_inst/arp_tx_done ), .I2 (data[5]), .I3 (crc_data[10]), @@ -338354,7 +337797,7 @@ module crc32_d8 .I1 (data[0]), .I2 (crc_data[11]), .I3 (crc_data[31]), - .I4 (_N107811)); + .I4 (_N108643)); // LUT = (I0)|(I1&~I2&~I3&~I4)|(~I1&I2&~I3&~I4)|(~I1&~I2&I3&~I4)|(I1&I2&I3&~I4)|(~I1&~I2&~I3&I4)|(I1&I2&~I3&I4)|(I1&~I2&I3&I4)|(~I1&I2&I3&I4) ; // ../../sources/designs/udp_osd/eth_udp/arp/crc32_d8.v:80 @@ -338407,7 +337850,7 @@ module crc32_d8 .INIT(32'b11011110111011011110110111011110)) \N264[24] ( .Z (N264[24]), - .I0 (_N96846), + .I0 (_N97621), .I1 (\udp_osd_inst/eth_udp_inst/arp_tx_done ), .I2 (data[0]), .I3 (crc_data[16]), @@ -338423,7 +337866,7 @@ module crc32_d8 .I1 (data[5]), .I2 (crc_data[17]), .I3 (crc_data[26]), - .I4 (_N107811)); + .I4 (_N108643)); // LUT = (I0)|(I1&~I2&~I3&~I4)|(~I1&I2&~I3&~I4)|(~I1&~I2&I3&~I4)|(I1&I2&I3&~I4)|(~I1&~I2&~I3&I4)|(I1&I2&~I3&I4)|(I1&~I2&I3&I4)|(~I1&I2&I3&I4) ; // ../../sources/designs/udp_osd/eth_udp/arp/crc32_d8.v:80 @@ -338431,11 +337874,11 @@ module crc32_d8 .INIT(32'b11011110111011011110110111011110)) \N264[26] ( .Z (N264[26]), - .I0 (_N96081), + .I0 (_N96856), .I1 (\udp_osd_inst/eth_udp_inst/arp_tx_done ), .I2 (crc_data[18]), .I3 (crc_next[0]), - .I4 (_N107811)); + .I4 (_N108643)); // LUT = (I1)|(I0&~I2&~I3&~I4)|(~I0&I2&~I3&~I4)|(~I0&~I2&I3&~I4)|(I0&I2&I3&~I4)|(~I0&~I2&~I3&I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(~I0&I2&I3&I4) ; // ../../sources/designs/udp_osd/eth_udp/arp/crc32_d8.v:80 @@ -338443,9 +337886,9 @@ module crc32_d8 .INIT(8'b11011110)) \N264[27] ( .Z (N264[27]), - .I0 (_N96843), + .I0 (_N97618), .I1 (\udp_osd_inst/eth_udp_inst/arp_tx_done ), - .I2 (_N107809)); + .I2 (_N108641)); // LUT = (I1)|(I0&~I2)|(~I0&I2) ; // ../../sources/designs/udp_osd/eth_udp/arp/crc32_d8.v:80 @@ -338453,7 +337896,7 @@ module crc32_d8 .INIT(32'b11011110111011011110110111011110)) \N264[28] ( .Z (N264[28]), - .I0 (_N97058), + .I0 (_N97820), .I1 (\udp_osd_inst/eth_udp_inst/arp_tx_done ), .I2 (data[5]), .I3 (crc_data[20]), @@ -338465,7 +337908,7 @@ module crc32_d8 .INIT(32'b11011110111011011110110111011110)) \N264[29] ( .Z (N264[29]), - .I0 (_N96842), + .I0 (_N97617), .I1 (\udp_osd_inst/eth_udp_inst/arp_tx_done ), .I2 (data[4]), .I3 (crc_data[21]), @@ -338477,7 +337920,7 @@ module crc32_d8 .INIT(32'b11011110111011011110110111011110)) \N264[30] ( .Z (N264[30]), - .I0 (_N96081), + .I0 (_N96856), .I1 (\udp_osd_inst/eth_udp_inst/arp_tx_done ), .I2 (data[0]), .I3 (crc_data[22]), @@ -338856,35 +338299,31 @@ module arp ( input [7:0] gmii_rxd_data, input [4:0] \udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt , - input [6:0] \udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg , input [4:0] \udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt , + input [6:0] \udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg , input [6:0] \udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/next_state , - input _N84201, - input _N96358, - input _N96693, - input _N96775, - input _N96776, - input _N108056, + input _N96653, + input _N97535, + input _N97539, + input _N97540, input arp_tx_en, input gmii_rx_clk, input gmii_rxd_valid, input sync_vg_100m, input \u_arp_rx/N559 , - input \udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/error_en , - input \udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/skip_en , + input \udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/error_en , + input \udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/skip_en , output [31:0] des_ip, output [47:0] des_mac, output [7:0] gmii_txd_data, output [4:0] \u_arp_rx/cnt , - output _N95922, - output _N95923, - output _N95925, - output _N96007, - output _N96085, - output _N96096, - output _N96556, - output _N97006, - output _N97473, + output _N97121, + output _N97122, + output _N97327, + output _N97338, + output _N97341, + output _N97887, + output _N98258, output arp_rx_done, output arp_rx_type, output gmii_txd_valid, @@ -338894,10 +338333,10 @@ module arp output \u_arp_tx/N409_inv , output \udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N586 ); - wire _N96069; - wire _N96846; - wire _N97055; - wire _N97057; + wire _N96855; + wire _N97621; + wire _N97817; + wire _N97819; wire [31:0] crc_data; wire crc_en; wire [31:0] crc_next; @@ -338944,36 +338383,32 @@ module arp .src_ip (des_ip), .src_mac (des_mac), .gmii_rxd_data (gmii_rxd_data), - .\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt ({\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt [4] , \udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt [3] , 1'bx, 1'bx, \udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt [0] }), - .\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg ({\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg [6] , \udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg [5] , \udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg [4] , \udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg [3] , \udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg [2] , \udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg [1] , 1'bx}), + .\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt ({\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt [4] , \udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt [3] , \udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt [2] , 1'bx, 1'bx}), .\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt ({\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt [4] , \udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt [3] , 1'bx, 1'bx, \udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt [0] }), + .\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg ({\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg [6] , 1'bx, 1'bx, 1'bx, 1'bx, \udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg [1] , \udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg [0] }), .\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/next_state ({1'bx, 1'bx, \udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/next_state [4] , \udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/next_state [3] , \udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/next_state [2] , 1'bx, 1'bx}), .N52 (\u_arp_rx/N52 ), .N366 (\u_arp_rx/N366 ), - ._N95922 (_N95922), - ._N95923 (_N95923), - ._N95925 (_N95925), - ._N96007 (_N96007), - ._N96085 (_N96085), - ._N96096 (_N96096), - ._N96556 (_N96556), - ._N97006 (_N97006), - ._N97473 (_N97473), + ._N97121 (_N97121), + ._N97122 (_N97122), + ._N97327 (_N97327), + ._N97338 (_N97338), + ._N97341 (_N97341), + ._N97887 (_N97887), + ._N98258 (_N98258), .arp_rx_done (arp_rx_done), .arp_rx_type (arp_rx_type), .\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N586 (\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N586 ), .N559 (\u_arp_rx/N559 ), - ._N84201 (_N84201), - ._N96358 (_N96358), - ._N96693 (_N96693), - ._N96775 (_N96775), - ._N96776 (_N96776), - ._N108056 (_N108056), + ._N96653 (_N96653), + ._N97535 (_N97535), + ._N97539 (_N97539), + ._N97540 (_N97540), .clk (gmii_rx_clk), .gmii_rxd_valid (gmii_rxd_valid), .sync_vg_100m (sync_vg_100m), - .\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/error_en (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/error_en ), - .\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/skip_en (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/skip_en )); + .\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/error_en (\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/error_en ), + .\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/skip_en (\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/skip_en )); // ../../sources/designs/udp_osd/eth_udp/arp/arp.v:72 arp_tx u_arp_tx ( @@ -338987,10 +338422,10 @@ module arp .crc_en (crc_en), .gmii_txd_valid (gmii_txd_valid), .\udp_osd_inst/eth_udp_inst/arp_tx_done (tx_done), - ._N96069 (_N96069), - ._N96846 (_N96846), - ._N97055 (_N97055), - ._N97057 (_N97057), + ._N96855 (_N96855), + ._N97621 (_N97621), + ._N97817 (_N97817), + ._N97819 (_N97819), .arp_tx_en (arp_tx_en), .clk (gmii_rx_clk), .sync_vg_100m (sync_vg_100m)); @@ -339000,10 +338435,10 @@ module arp .crc_data ({crc_data[31], \u_crc32_d8_crc_data[30]_floating , \u_crc32_d8_crc_data[29]_floating , \u_crc32_d8_crc_data[28]_floating , \u_crc32_d8_crc_data[27]_floating , \u_crc32_d8_crc_data[26]_floating , \u_crc32_d8_crc_data[25]_floating , \u_crc32_d8_crc_data[24]_floating , crc_data[23], crc_data[22], crc_data[21], crc_data[20], crc_data[19], crc_data[18], crc_data[17], crc_data[16], crc_data[15], crc_data[14], crc_data[13], crc_data[12], crc_data[11], crc_data[10], crc_data[9], crc_data[8], crc_data[7], crc_data[6], crc_data[5], crc_data[4], crc_data[3], crc_data[2], crc_data[1], crc_data[0]}), .crc_next ({\u_crc32_d8_crc_next[31]_floating , crc_next[30], \u_crc32_d8_crc_next[29]_floating , crc_next[28], crc_next[27], crc_next[26], \u_crc32_d8_crc_next[25]_floating , \u_crc32_d8_crc_next[24]_floating , \u_crc32_d8_crc_next[23]_floating , \u_crc32_d8_crc_next[22]_floating , \u_crc32_d8_crc_next[21]_floating , \u_crc32_d8_crc_next[20]_floating , \u_crc32_d8_crc_next[19]_floating , \u_crc32_d8_crc_next[18]_floating , \u_crc32_d8_crc_next[17]_floating , \u_crc32_d8_crc_next[16]_floating , \u_crc32_d8_crc_next[15]_floating , \u_crc32_d8_crc_next[14]_floating , \u_crc32_d8_crc_next[13]_floating , \u_crc32_d8_crc_next[12]_floating , \u_crc32_d8_crc_next[11]_floating , \u_crc32_d8_crc_next[10]_floating , \u_crc32_d8_crc_next[9]_floating , \u_crc32_d8_crc_next[8]_floating , \u_crc32_d8_crc_next[7]_floating , \u_crc32_d8_crc_next[6]_floating , \u_crc32_d8_crc_next[5]_floating , \u_crc32_d8_crc_next[4]_floating , \u_crc32_d8_crc_next[3]_floating , \u_crc32_d8_crc_next[2]_floating , \u_crc32_d8_crc_next[1]_floating , \u_crc32_d8_crc_next[0]_floating }), .data (gmii_txd_data), - ._N96069 (_N96069), - ._N96846 (_N96846), - ._N97055 (_N97055), - ._N97057 (_N97057), + ._N96855 (_N96855), + ._N97621 (_N97621), + ._N97817 (_N97817), + ._N97819 (_N97819), .clk (gmii_rx_clk), .crc_en (crc_en), .sync_vg_100m (sync_vg_100m), @@ -339039,7 +338474,7 @@ module eth_ctrl wire N67; wire [7:0] N71; wire [2:0] N96; - wire _N103306; + wire _N104118; wire arp_rx_flag; wire [2:0] protocol_sw_reg; @@ -339282,14 +338717,14 @@ module eth_ctrl \protocol_sw_reg[0] ( .Q (protocol_sw_reg[0]), .CLK (clk), - .D (_N103306), + .D (_N104118), .P (sync_vg_100m)); // ../../sources/designs/udp_osd/eth_udp/eth_ctrl.v:163 GTP_LUT3 /* \protocol_sw_reg_ce_mux[0] */ #( .INIT(8'b01010100)) \protocol_sw_reg_ce_mux[0] ( - .Z (_N103306), + .Z (_N104118), .I0 (icmp_tx_start_en), .I1 (arp_rx_flag), .I2 (protocol_sw_reg[0])); @@ -339834,32 +339269,24 @@ module crc32_d8_unq6 input \udp_osd_inst/eth_udp_inst/icmp_tx_done , output [31:0] crc_data, output [31:0] crc_next, - output _N96067, - output _N97048, - output _N97050 + output _N96861, + output _N97827, + output _N97829 ); wire N263; wire [31:0] N264; - wire _N96065; - wire _N96068; - wire _N96836; - wire _N96837; - wire _N96840; - wire _N97043; - wire _N97044; - wire _N97051; - wire _N107881; - wire _N107883; - wire _N107886; - wire _N107888; - - GTP_LUT2 /* N3_1 */ #( - .INIT(4'b0110)) - N3_1 ( - .Z (_N96065), - .I0 (data[0]), - .I1 (crc_data[31])); - // LUT = (I0&~I1)|(~I0&I1) ; + wire _N96859; + wire _N96862; + wire _N97627; + wire _N97628; + wire _N97631; + wire _N97822; + wire _N97823; + wire _N97830; + wire _N108713; + wire _N108715; + wire _N108718; + wire _N108720; GTP_LUT4 /* N39_1 */ #( .INIT(16'b0110100110010110)) @@ -339874,25 +339301,17 @@ module crc32_d8_unq6 GTP_LUT4 /* N75_1 */ #( .INIT(16'b0110100110010110)) N75_1 ( - .Z (_N96836), + .Z (_N97627), .I0 (data[0]), .I1 (data[1]), .I2 (crc_data[30]), .I3 (crc_data[31])); // LUT = (I0&~I1&~I2&~I3)|(~I0&I1&~I2&~I3)|(~I0&~I1&I2&~I3)|(I0&I1&I2&~I3)|(~I0&~I1&~I2&I3)|(I0&I1&~I2&I3)|(I0&~I1&I2&I3)|(~I0&I1&I2&I3) ; - GTP_LUT2 /* N84_1 */ #( - .INIT(4'b0110)) - N84_1 ( - .Z (_N96067), - .I0 (data[2]), - .I1 (crc_data[29])); - // LUT = (I0&~I1)|(~I0&I1) ; - GTP_LUT2 /* N102_2 */ #( .INIT(4'b0110)) N102_2 ( - .Z (_N107888), + .Z (_N108720), .I0 (data[4]), .I1 (crc_data[27])); // LUT = (I0&~I1)|(~I0&I1) ; @@ -339900,26 +339319,18 @@ module crc32_d8_unq6 GTP_LUT5 /* N102_7 */ #( .INIT(32'b10010110011010010110100110010110)) N102_7 ( - .Z (_N97043), + .Z (_N97822), .I0 (data[5]), .I1 (data[7]), .I2 (crc_data[24]), .I3 (crc_data[26]), - .I4 (_N107888)); + .I4 (_N108720)); // LUT = (I0&~I1&~I2&~I3&~I4)|(~I0&I1&~I2&~I3&~I4)|(~I0&~I1&I2&~I3&~I4)|(I0&I1&I2&~I3&~I4)|(~I0&~I1&~I2&I3&~I4)|(I0&I1&~I2&I3&~I4)|(I0&~I1&I2&I3&~I4)|(~I0&I1&I2&I3&~I4)|(~I0&~I1&~I2&~I3&I4)|(I0&I1&~I2&~I3&I4)|(I0&~I1&I2&~I3&I4)|(~I0&I1&I2&~I3&I4)|(I0&~I1&~I2&I3&I4)|(~I0&I1&~I2&I3&I4)|(~I0&~I1&I2&I3&I4)|(I0&I1&I2&I3&I4) ; - GTP_LUT2 /* N111_1 */ #( - .INIT(4'b0110)) - N111_1 ( - .Z (_N96068), - .I0 (data[3]), - .I1 (crc_data[28])); - // LUT = (I0&~I1)|(~I0&I1) ; - GTP_LUT5 /* N148_2 */ #( .INIT(32'b10010110011010010110100110010110)) N148_2 ( - .Z (_N107881), + .Z (_N108713), .I0 (data[3]), .I1 (data[4]), .I2 (crc_data[6]), @@ -339927,41 +339338,65 @@ module crc32_d8_unq6 .I4 (crc_data[28])); // LUT = (I0&~I1&~I2&~I3&~I4)|(~I0&I1&~I2&~I3&~I4)|(~I0&~I1&I2&~I3&~I4)|(I0&I1&I2&~I3&~I4)|(~I0&~I1&~I2&I3&~I4)|(I0&I1&~I2&I3&~I4)|(I0&~I1&I2&I3&~I4)|(~I0&I1&I2&I3&~I4)|(~I0&~I1&~I2&~I3&I4)|(I0&I1&~I2&~I3&I4)|(I0&~I1&I2&~I3&I4)|(~I0&I1&I2&~I3&I4)|(I0&~I1&~I2&I3&I4)|(~I0&I1&~I2&I3&I4)|(~I0&~I1&I2&I3&I4)|(I0&I1&I2&I3&I4) ; + GTP_LUT2 /* N171_1 */ #( + .INIT(4'b0110)) + N171_1 ( + .Z (_N96859), + .I0 (data[0]), + .I1 (crc_data[31])); + // LUT = (I0&~I1)|(~I0&I1) ; + GTP_LUT5 /* N183_4 */ #( .INIT(32'b10010110011010010110100110010110)) N183_4 ( .Z (crc_next[1]), - .I0 (_N96836), + .I0 (_N97627), .I1 (data[6]), .I2 (data[7]), .I3 (crc_data[24]), .I4 (crc_data[25])); // LUT = (I0&~I1&~I2&~I3&~I4)|(~I0&I1&~I2&~I3&~I4)|(~I0&~I1&I2&~I3&~I4)|(I0&I1&I2&~I3&~I4)|(~I0&~I1&~I2&I3&~I4)|(I0&I1&~I2&I3&~I4)|(I0&~I1&I2&I3&~I4)|(~I0&I1&I2&I3&~I4)|(~I0&~I1&~I2&~I3&I4)|(I0&I1&~I2&~I3&I4)|(I0&~I1&I2&~I3&I4)|(~I0&I1&I2&~I3&I4)|(I0&~I1&~I2&I3&I4)|(~I0&I1&~I2&I3&I4)|(~I0&~I1&I2&I3&I4)|(I0&I1&I2&I3&I4) ; - GTP_LUT4 /* N186_1 */ #( + GTP_LUT4 /* N186_2 */ #( .INIT(16'b0110100110010110)) - N186_1 ( - .Z (_N96840), + N186_2 ( + .Z (_N97631), .I0 (data[5]), .I1 (data[6]), .I2 (crc_data[25]), .I3 (crc_data[26])); // LUT = (I0&~I1&~I2&~I3)|(~I0&I1&~I2&~I3)|(~I0&~I1&I2&~I3)|(I0&I1&I2&~I3)|(~I0&~I1&~I2&I3)|(I0&I1&~I2&I3)|(I0&~I1&I2&I3)|(~I0&I1&I2&I3) ; - GTP_LUT4 /* N189_1 */ #( - .INIT(16'b0110100110010110)) + GTP_LUT2 /* N189_1 */ #( + .INIT(4'b0110)) N189_1 ( - .Z (_N96837), + .Z (_N96861), + .I0 (data[2]), + .I1 (crc_data[29])); + // LUT = (I0&~I1)|(~I0&I1) ; + + GTP_LUT4 /* N189_2 */ #( + .INIT(16'b0110100110010110)) + N189_2 ( + .Z (_N97628), .I0 (data[2]), .I1 (data[3]), .I2 (crc_data[28]), .I3 (crc_data[29])); // LUT = (I0&~I1&~I2&~I3)|(~I0&I1&~I2&~I3)|(~I0&~I1&I2&~I3)|(I0&I1&I2&~I3)|(~I0&~I1&~I2&I3)|(I0&I1&~I2&I3)|(I0&~I1&I2&I3)|(~I0&I1&I2&I3) ; + GTP_LUT2 /* N192_1 */ #( + .INIT(4'b0110)) + N192_1 ( + .Z (_N96862), + .I0 (data[3]), + .I1 (crc_data[28])); + // LUT = (I0&~I1)|(~I0&I1) ; + GTP_LUT3 /* N192_4 */ #( .INIT(8'b10010110)) N192_4 ( - .Z (_N97044), + .Z (_N97823), .I0 (data[5]), .I1 (crc_data[25]), .I2 (crc_data[26])); @@ -339970,7 +339405,7 @@ module crc32_d8_unq6 GTP_LUT4 /* N199_1 */ #( .INIT(16'b0110100110010110)) N199_1 ( - .Z (_N97050), + .Z (_N97829), .I0 (data[4]), .I1 (data[5]), .I2 (crc_data[26]), @@ -339980,7 +339415,7 @@ module crc32_d8_unq6 GTP_LUT4 /* N206_1 */ #( .INIT(16'b0110100110010110)) N206_1 ( - .Z (_N97051), + .Z (_N97830), .I0 (data[1]), .I1 (data[2]), .I2 (crc_data[29]), @@ -339991,7 +339426,7 @@ module crc32_d8_unq6 .INIT(16'b0110100110010110)) N206_5 ( .Z (crc_next[24]), - .I0 (_N96840), + .I0 (_N97631), .I1 (data[0]), .I2 (crc_data[16]), .I3 (crc_data[31])); @@ -340005,24 +339440,24 @@ module crc32_d8_unq6 .I1 (crc_data[18]), .I2 (crc_data[28]), .I3 (crc_next[0]), - .I4 (_N107888)); + .I4 (_N108720)); // LUT = (I0&~I1&~I2&~I3&~I4)|(~I0&I1&~I2&~I3&~I4)|(~I0&~I1&I2&~I3&~I4)|(I0&I1&I2&~I3&~I4)|(~I0&~I1&~I2&I3&~I4)|(I0&I1&~I2&I3&~I4)|(I0&~I1&I2&I3&~I4)|(~I0&I1&I2&I3&~I4)|(~I0&~I1&~I2&~I3&I4)|(I0&I1&~I2&~I3&I4)|(I0&~I1&I2&~I3&I4)|(~I0&I1&I2&~I3&I4)|(I0&~I1&~I2&I3&I4)|(~I0&I1&~I2&I3&I4)|(~I0&~I1&I2&I3&I4)|(I0&I1&I2&I3&I4) ; GTP_LUT5 /* N229_1 */ #( .INIT(32'b10010110011010010110100110010110)) N229_1 ( - .Z (_N97048), + .Z (_N97827), .I0 (data[0]), .I1 (data[1]), .I2 (crc_data[30]), .I3 (crc_data[31]), - .I4 (_N107888)); + .I4 (_N108720)); // LUT = (I0&~I1&~I2&~I3&~I4)|(~I0&I1&~I2&~I3&~I4)|(~I0&~I1&I2&~I3&~I4)|(I0&I1&I2&~I3&~I4)|(~I0&~I1&~I2&I3&~I4)|(I0&I1&~I2&I3&~I4)|(I0&~I1&I2&I3&~I4)|(~I0&I1&I2&I3&~I4)|(~I0&~I1&~I2&~I3&I4)|(I0&I1&~I2&~I3&I4)|(I0&~I1&I2&~I3&I4)|(~I0&I1&I2&~I3&I4)|(I0&~I1&~I2&I3&I4)|(~I0&I1&~I2&I3&I4)|(~I0&~I1&I2&I3&I4)|(I0&I1&I2&I3&I4) ; GTP_LUT5 /* N229_6 */ #( .INIT(32'b10010110011010010110100110010110)) N229_6 ( - .Z (_N107886), + .Z (_N108718), .I0 (data[0]), .I1 (data[6]), .I2 (crc_data[19]), @@ -340034,8 +339469,8 @@ module crc32_d8_unq6 .INIT(32'b10010110011010010110100110010110)) N229_7 ( .Z (crc_next[27]), - .I0 (_N96065), - .I1 (_N96837), + .I0 (_N96859), + .I1 (_N97628), .I2 (data[6]), .I3 (crc_data[19]), .I4 (crc_data[25])); @@ -340045,7 +339480,7 @@ module crc32_d8_unq6 .INIT(16'b0110100110010110)) N236_5 ( .Z (crc_next[28]), - .I0 (_N97051), + .I0 (_N97830), .I1 (data[5]), .I2 (crc_data[20]), .I3 (crc_data[26])); @@ -340054,7 +339489,7 @@ module crc32_d8_unq6 GTP_LUT4 /* N243_2 */ #( .INIT(16'b0110100110010110)) N243_2 ( - .Z (_N107883), + .Z (_N108715), .I0 (data[6]), .I1 (data[7]), .I2 (crc_data[24]), @@ -340118,11 +339553,11 @@ module crc32_d8_unq6 .INIT(32'b11011110111011011110110111011110)) \N264[3] ( .Z (N264[3]), - .I0 (_N96840), + .I0 (_N97631), .I1 (\udp_osd_inst/eth_udp_inst/icmp_tx_done ), .I2 (data[0]), .I3 (crc_data[31]), - .I4 (_N107888)); + .I4 (_N108720)); // LUT = (I1)|(I0&~I2&~I3&~I4)|(~I0&I2&~I3&~I4)|(~I0&~I2&I3&~I4)|(I0&I2&I3&~I4)|(~I0&~I2&~I3&I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(~I0&I2&I3&I4) ; // ../../sources/designs/udp_osd/eth_udp/arp/crc32_d8.v:80 @@ -340130,8 +339565,8 @@ module crc32_d8_unq6 .INIT(32'b11110110111110011111100111110110)) \N264[4] ( .Z (N264[4]), - .I0 (_N96068), - .I1 (_N97043), + .I0 (_N96862), + .I1 (_N97822), .I2 (\udp_osd_inst/eth_udp_inst/icmp_tx_done ), .I3 (data[1]), .I4 (crc_data[30])); @@ -340142,7 +339577,7 @@ module crc32_d8_unq6 .INIT(32'b11011110111011011110110111011110)) \N264[5] ( .Z (N264[5]), - .I0 (_N96837), + .I0 (_N97628), .I1 (\udp_osd_inst/eth_udp_inst/icmp_tx_done ), .I2 (data[4]), .I3 (crc_data[27]), @@ -340154,9 +339589,9 @@ module crc32_d8_unq6 .INIT(32'b11111111011010011111111110010110)) \N264[6] ( .Z (N264[6]), - .I0 (_N96836), - .I1 (_N96837), - .I2 (_N97044), + .I0 (_N97627), + .I1 (_N97628), + .I2 (_N97823), .I3 (\udp_osd_inst/eth_udp_inst/icmp_tx_done ), .I4 (data[6])); // LUT = (I3)|(I0&~I1&~I2&~I4)|(~I0&I1&~I2&~I4)|(~I0&~I1&I2&~I4)|(I0&I1&I2&~I4)|(~I0&~I1&~I2&I4)|(I0&I1&~I2&I4)|(I0&~I1&I2&I4)|(~I0&I1&I2&I4) ; @@ -340166,8 +339601,8 @@ module crc32_d8_unq6 .INIT(32'b11110110111110011111100111110110)) \N264[7] ( .Z (N264[7]), - .I0 (_N96065), - .I1 (_N97043), + .I0 (_N96859), + .I1 (_N97822), .I2 (\udp_osd_inst/eth_udp_inst/icmp_tx_done ), .I3 (data[2]), .I4 (crc_data[29])); @@ -340178,11 +339613,11 @@ module crc32_d8_unq6 .INIT(32'b11011110111011011110110111011110)) \N264[8] ( .Z (N264[8]), - .I0 (_N96068), + .I0 (_N96862), .I1 (\udp_osd_inst/eth_udp_inst/icmp_tx_done ), .I2 (crc_data[0]), - .I3 (_N107883), - .I4 (_N107888)); + .I3 (_N108715), + .I4 (_N108720)); // LUT = (I1)|(I0&~I2&~I3&~I4)|(~I0&I2&~I3&~I4)|(~I0&~I2&I3&~I4)|(I0&I2&I3&~I4)|(~I0&~I2&~I3&I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(~I0&I2&I3&I4) ; // ../../sources/designs/udp_osd/eth_udp/arp/crc32_d8.v:80 @@ -340190,8 +339625,8 @@ module crc32_d8_unq6 .INIT(16'b1111100111110110)) \N264[9] ( .Z (N264[9]), - .I0 (_N96837), - .I1 (_N96840), + .I0 (_N97628), + .I1 (_N97631), .I2 (\udp_osd_inst/eth_udp_inst/icmp_tx_done ), .I3 (crc_data[1])); // LUT = (I2)|(I0&~I1&~I3)|(~I0&I1&~I3)|(~I0&~I1&I3)|(I0&I1&I3) ; @@ -340201,7 +339636,7 @@ module crc32_d8_unq6 .INIT(32'b11011110111011011110110111011110)) \N264[10] ( .Z (N264[10]), - .I0 (_N97043), + .I0 (_N97822), .I1 (\udp_osd_inst/eth_udp_inst/icmp_tx_done ), .I2 (data[2]), .I3 (crc_data[2]), @@ -340213,11 +339648,11 @@ module crc32_d8_unq6 .INIT(32'b11011110111011011110110111011110)) \N264[11] ( .Z (N264[11]), - .I0 (_N96068), + .I0 (_N96862), .I1 (\udp_osd_inst/eth_udp_inst/icmp_tx_done ), .I2 (crc_data[3]), - .I3 (_N107883), - .I4 (_N107888)); + .I3 (_N108715), + .I4 (_N108720)); // LUT = (I1)|(I0&~I2&~I3&~I4)|(~I0&I2&~I3&~I4)|(~I0&~I2&I3&~I4)|(I0&I2&I3&~I4)|(~I0&~I2&~I3&I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(~I0&I2&I3&I4) ; // ../../sources/designs/udp_osd/eth_udp/arp/crc32_d8.v:80 @@ -340225,8 +339660,8 @@ module crc32_d8_unq6 .INIT(32'b11110110111110011111100111110110)) \N264[12] ( .Z (N264[12]), - .I0 (_N96837), - .I1 (_N96840), + .I0 (_N97628), + .I1 (_N97631), .I2 (\udp_osd_inst/eth_udp_inst/icmp_tx_done ), .I3 (crc_data[4]), .I4 (crc_next[0])); @@ -340237,9 +339672,9 @@ module crc32_d8_unq6 .INIT(32'b11111111011010011111111110010110)) \N264[13] ( .Z (N264[13]), - .I0 (_N96067), - .I1 (_N96840), - .I2 (_N97048), + .I0 (_N96861), + .I1 (_N97631), + .I2 (_N97827), .I3 (\udp_osd_inst/eth_udp_inst/icmp_tx_done ), .I4 (crc_data[5])); // LUT = (I3)|(I0&~I1&~I2&~I4)|(~I0&I1&~I2&~I4)|(~I0&~I1&I2&~I4)|(I0&I1&I2&~I4)|(~I0&~I1&~I2&I4)|(I0&I1&~I2&I4)|(I0&~I1&I2&I4)|(~I0&I1&I2&I4) ; @@ -340249,11 +339684,11 @@ module crc32_d8_unq6 .INIT(32'b11011110111011011110110111011110)) \N264[14] ( .Z (N264[14]), - .I0 (_N96836), + .I0 (_N97627), .I1 (\udp_osd_inst/eth_udp_inst/icmp_tx_done ), .I2 (data[5]), .I3 (crc_data[26]), - .I4 (_N107881)); + .I4 (_N108713)); // LUT = (I1)|(I0&~I2&~I3&~I4)|(~I0&I2&~I3&~I4)|(~I0&~I2&I3&~I4)|(I0&I2&I3&~I4)|(~I0&~I2&~I3&I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(~I0&I2&I3&I4) ; // ../../sources/designs/udp_osd/eth_udp/arp/crc32_d8.v:80 @@ -340261,11 +339696,11 @@ module crc32_d8_unq6 .INIT(32'b11110110111110011111100111110110)) \N264[15] ( .Z (N264[15]), - .I0 (_N96065), - .I1 (_N96837), + .I0 (_N96859), + .I1 (_N97628), .I2 (\udp_osd_inst/eth_udp_inst/icmp_tx_done ), .I3 (crc_data[7]), - .I4 (_N107888)); + .I4 (_N108720)); // LUT = (I2)|(I0&~I1&~I3&~I4)|(~I0&I1&~I3&~I4)|(~I0&~I1&I3&~I4)|(I0&I1&I3&~I4)|(~I0&~I1&~I3&I4)|(I0&I1&~I3&I4)|(I0&~I1&I3&I4)|(~I0&I1&I3&I4) ; // ../../sources/designs/udp_osd/eth_udp/arp/crc32_d8.v:80 @@ -340273,7 +339708,7 @@ module crc32_d8_unq6 .INIT(32'b11011110111011011110110111011110)) \N264[16] ( .Z (N264[16]), - .I0 (_N96837), + .I0 (_N97628), .I1 (\udp_osd_inst/eth_udp_inst/icmp_tx_done ), .I2 (data[7]), .I3 (crc_data[8]), @@ -340285,7 +339720,7 @@ module crc32_d8_unq6 .INIT(32'b11011110111011011110110111011110)) \N264[17] ( .Z (N264[17]), - .I0 (_N97051), + .I0 (_N97830), .I1 (\udp_osd_inst/eth_udp_inst/icmp_tx_done ), .I2 (data[6]), .I3 (crc_data[9]), @@ -340297,7 +339732,7 @@ module crc32_d8_unq6 .INIT(32'b11011110111011011110110111011110)) \N264[18] ( .Z (N264[18]), - .I0 (_N96836), + .I0 (_N97627), .I1 (\udp_osd_inst/eth_udp_inst/icmp_tx_done ), .I2 (data[5]), .I3 (crc_data[10]), @@ -340313,7 +339748,7 @@ module crc32_d8_unq6 .I1 (data[0]), .I2 (crc_data[11]), .I3 (crc_data[31]), - .I4 (_N107888)); + .I4 (_N108720)); // LUT = (I0)|(I1&~I2&~I3&~I4)|(~I1&I2&~I3&~I4)|(~I1&~I2&I3&~I4)|(I1&I2&I3&~I4)|(~I1&~I2&~I3&I4)|(I1&I2&~I3&I4)|(I1&~I2&I3&I4)|(~I1&I2&I3&I4) ; // ../../sources/designs/udp_osd/eth_udp/arp/crc32_d8.v:80 @@ -340366,7 +339801,7 @@ module crc32_d8_unq6 .INIT(32'b11011110111011011110110111011110)) \N264[24] ( .Z (N264[24]), - .I0 (_N96840), + .I0 (_N97631), .I1 (\udp_osd_inst/eth_udp_inst/icmp_tx_done ), .I2 (data[0]), .I3 (crc_data[16]), @@ -340382,7 +339817,7 @@ module crc32_d8_unq6 .I1 (data[5]), .I2 (crc_data[17]), .I3 (crc_data[26]), - .I4 (_N107888)); + .I4 (_N108720)); // LUT = (I0)|(I1&~I2&~I3&~I4)|(~I1&I2&~I3&~I4)|(~I1&~I2&I3&~I4)|(I1&I2&I3&~I4)|(~I1&~I2&~I3&I4)|(I1&I2&~I3&I4)|(I1&~I2&I3&I4)|(~I1&I2&I3&I4) ; // ../../sources/designs/udp_osd/eth_udp/arp/crc32_d8.v:80 @@ -340390,11 +339825,11 @@ module crc32_d8_unq6 .INIT(32'b11011110111011011110110111011110)) \N264[26] ( .Z (N264[26]), - .I0 (_N96068), + .I0 (_N96862), .I1 (\udp_osd_inst/eth_udp_inst/icmp_tx_done ), .I2 (crc_data[18]), .I3 (crc_next[0]), - .I4 (_N107888)); + .I4 (_N108720)); // LUT = (I1)|(I0&~I2&~I3&~I4)|(~I0&I2&~I3&~I4)|(~I0&~I2&I3&~I4)|(I0&I2&I3&~I4)|(~I0&~I2&~I3&I4)|(I0&I2&~I3&I4)|(I0&~I2&I3&I4)|(~I0&I2&I3&I4) ; // ../../sources/designs/udp_osd/eth_udp/arp/crc32_d8.v:80 @@ -340402,9 +339837,9 @@ module crc32_d8_unq6 .INIT(8'b11011110)) \N264[27] ( .Z (N264[27]), - .I0 (_N96837), + .I0 (_N97628), .I1 (\udp_osd_inst/eth_udp_inst/icmp_tx_done ), - .I2 (_N107886)); + .I2 (_N108718)); // LUT = (I1)|(I0&~I2)|(~I0&I2) ; // ../../sources/designs/udp_osd/eth_udp/arp/crc32_d8.v:80 @@ -340412,7 +339847,7 @@ module crc32_d8_unq6 .INIT(32'b11011110111011011110110111011110)) \N264[28] ( .Z (N264[28]), - .I0 (_N97051), + .I0 (_N97830), .I1 (\udp_osd_inst/eth_udp_inst/icmp_tx_done ), .I2 (data[5]), .I3 (crc_data[20]), @@ -340424,7 +339859,7 @@ module crc32_d8_unq6 .INIT(32'b11011110111011011110110111011110)) \N264[29] ( .Z (N264[29]), - .I0 (_N96836), + .I0 (_N97627), .I1 (\udp_osd_inst/eth_udp_inst/icmp_tx_done ), .I2 (data[4]), .I3 (crc_data[21]), @@ -340436,7 +339871,7 @@ module crc32_d8_unq6 .INIT(32'b11011110111011011110110111011110)) \N264[30] ( .Z (N264[30]), - .I0 (_N96068), + .I0 (_N96862), .I1 (\udp_osd_inst/eth_udp_inst/icmp_tx_done ), .I2 (data[0]), .I3 (crc_data[22]), @@ -340815,25 +340250,22 @@ module icmp_rx ( input [7:0] gmii_rxd_data, input [4:0] \udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt , - input [4:0] \udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt , input [6:0] \udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg , input [6:0] \udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/next_state , input N74, - input _N95844, - input _N95922, - input _N95925, - input _N96007, - input _N96085, - input _N96096, - input _N96358, - input _N96556, - input _N96693, - input _N96780, - input _N97473, - input _N107965, + input N1269, + input _N82491, + input _N96654, + input _N96657, + input _N97327, + input _N97338, + input _N97535, + input _N97554, + input _N98258, input clk, input gmii_rxd_valid, input sync_vg_100m, + input \udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N366 , input \udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/skip_en , output [4:0] cnt, output [6:0] cur_state_reg, @@ -340842,17 +340274,20 @@ module icmp_rx output [15:0] rec_byte_num, output [7:0] rec_data, output [31:0] reply_checksum, - output _N84201, - output _N96072, - output _N96385, - output _N96774, - output _N96776, - output _N98508, - output error_en, + output N1265, + output _N82337, + output _N96653, + output _N96787, + output _N97539, + output _N97540, + output _N97542, + output _N100572, + output _N108899, output rec_en, output rec_pkt_done, output skip_en, - output \udp_osd_inst/eth_udp_inst/icmp_tx_byte_num[2]_inv + output \udp_osd_inst/eth_udp_inst/icmp_tx_byte_num[2]_inv , + output \udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N559 ); wire N82; wire N100; @@ -340872,6 +340307,7 @@ module icmp_rx wire N377; wire [16:0] \N377.co ; wire N397; + wire N421; wire N436; wire N438; wire N456; @@ -340908,19 +340344,26 @@ module icmp_rx wire N1170; wire N1213; wire N1261; - wire N1269; wire N1294; wire N1304; wire N1309; - wire N1326; - wire _N5391; - wire _N5466; + wire _N5329; + wire _N5465; wire _N10697; - wire _N14323; - wire _N14324; - wire _N14325; - wire _N14326; - wire _N14327; + wire _N13798; + wire _N13799; + wire _N13800; + wire _N13801; + wire _N13802; + wire _N13803; + wire _N13804; + wire _N13805; + wire _N13806; + wire _N13807; + wire _N13808; + wire _N13809; + wire _N13810; + wire _N13811; wire _N14328; wire _N14329; wire _N14330; @@ -340947,20 +340390,11 @@ module icmp_rx wire _N14351; wire _N14352; wire _N14353; + wire _N14354; + wire _N14355; wire _N14356; wire _N14357; wire _N14358; - wire _N14359; - wire _N14360; - wire _N14361; - wire _N14362; - wire _N14363; - wire _N14364; - wire _N14365; - wire _N14366; - wire _N14367; - wire _N14368; - wire _N14369; wire _N14370; wire _N14371; wire _N14372; @@ -340978,85 +340412,83 @@ module icmp_rx wire _N14384; wire _N14385; wire _N14386; - wire _N17055; - wire _N17056; - wire _N17057; - wire _N17058; - wire _N17059; - wire _N17060; - wire _N17061; - wire _N17062; - wire _N17063; - wire _N17064; - wire _N17065; - wire _N17066; - wire _N17067; - wire _N17068; + wire _N14387; + wire _N14388; + wire _N14389; + wire _N14390; + wire _N14391; + wire _N14392; + wire _N14393; + wire _N14394; + wire _N14395; + wire _N14396; + wire _N14397; + wire _N14398; + wire _N14399; + wire _N14400; wire _N18460; - wire _N18470; - wire _N18475; wire _N18479; - wire _N22164; - wire _N22171; - wire _N22175; - wire _N22177; - wire _N22178; - wire _N22180; - wire _N29955; - wire _N76271; - wire _N76299; - wire _N76327; - wire _N76355; - wire _N76383; - wire _N76411; - wire _N76439; - wire _N76467; - wire _N81758; - wire _N81987; - wire _N95975; - wire _N96999; - wire _N100419; - wire _N103308; - wire _N107503; - wire _N107507; - wire _N107511; - wire _N107515; - wire _N107518; - wire _N107522; - wire _N107540; - wire _N107549; - wire _N107553; - wire _N107557; - wire _N107561; - wire _N107565; - wire _N107569; - wire _N107572; - wire _N107576; - wire _N107581; - wire _N107586; - wire _N107590; - wire _N107594; - wire _N107598; - wire _N107602; - wire _N107604; - wire _N107606; - wire _N107609; - wire _N107614; - wire _N107618; - wire _N107622; - wire _N107626; - wire _N107629; - wire _N107632; - wire _N107635; - wire _N107647; - wire _N107652; - wire _N107657; - wire _N108059; - wire _N108064; - wire _N108067; - wire _N108068; + wire _N22650; + wire _N22657; + wire _N22663; + wire _N22664; + wire _N22666; + wire _N29901; + wire _N35473; + wire _N35501; + wire _N35529; + wire _N35557; + wire _N35585; + wire _N35613; + wire _N35641; + wire _N35669; + wire _N84087; + wire _N84941; + wire _N96834; + wire _N97775; + wire _N103649_2; + wire _N104120; + wire _N108335; + wire _N108339; + wire _N108343; + wire _N108347; + wire _N108350; + wire _N108354; + wire _N108360; + wire _N108372; + wire _N108381; + wire _N108385; + wire _N108389; + wire _N108393; + wire _N108397; + wire _N108401; + wire _N108404; + wire _N108408; + wire _N108413; + wire _N108418; + wire _N108422; + wire _N108426; + wire _N108430; + wire _N108434; + wire _N108436; + wire _N108438; + wire _N108441; + wire _N108446; + wire _N108450; + wire _N108454; + wire _N108458; + wire _N108461; + wire _N108464; + wire _N108467; + wire _N108479; + wire _N108484; + wire _N108489; + wire _N108894; + wire _N108902; + wire _N108903; wire [31:0] des_ip; wire [47:0] des_mac; + wire error_en; wire [15:0] eth_type; wire [15:0] icmp_data_length; wire [15:0] icmp_rx_cnt; @@ -341071,7 +340503,7 @@ module icmp_rx GTP_LUT3 /* N80_ac2 */ #( .INIT(8'b10000000)) N80_ac2 ( - .Z (_N5391), + .Z (_N5465), .I0 (cnt[0]), .I1 (cnt[1]), .I2 (cnt[2])); @@ -341087,21 +340519,21 @@ module icmp_rx .I3 (cnt[4])); // LUT = (~I1&~I2&~I3)|(~I0&~I2&~I3) ; - GTP_LUT4 /* N82_mux3_1 */ #( - .INIT(16'b0000000001000000)) - N82_mux3_1 ( - .Z (_N96776), + GTP_LUT4 /* N82_mux3_3 */ #( + .INIT(16'b0000000000001000)) + N82_mux3_3 ( + .Z (_N97539), .I0 (\udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt [1] ), .I1 (\udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt [2] ), .I2 (\udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt [3] ), .I3 (\udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt [4] )); - // LUT = ~I0&I1&I2&~I3 ; + // LUT = I0&I1&~I2&~I3 ; GTP_LUT5 /* N100 */ #( .INIT(32'b11111111110111111111110100000000)) N100_vname ( .Z (N100), - .I0 (_N97473), + .I0 (_N98258), .I1 (gmii_rxd_data[5]), .I2 (gmii_rxd_data[7]), .I3 (N82), @@ -341113,18 +340545,18 @@ module icmp_rx GTP_LUT5 /* N123_15 */ #( .INIT(32'b11111111100000001000000010000000)) N123_15 ( - .Z (_N81987), - .I0 (_N107553), - .I1 (_N107572), - .I2 (_N107576), - .I3 (_N107606), - .I4 (_N107609)); + .Z (_N84941), + .I0 (_N108385), + .I1 (_N108404), + .I2 (_N108408), + .I3 (_N108438), + .I4 (_N108441)); // LUT = (I3&I4)|(I0&I1&I2) ; GTP_LUT3 /* N123_16_5 */ #( .INIT(8'b00000001)) N123_16_5 ( - .Z (_N107581), + .Z (_N108413), .I0 (des_mac[42]), .I1 (des_mac[43]), .I2 (des_mac[46])); @@ -341133,7 +340565,7 @@ module icmp_rx GTP_LUT5 /* N123_16_10 */ #( .INIT(32'b00000000000000000000000000000001)) N123_16_10 ( - .Z (_N107586), + .Z (_N108418), .I0 (des_mac[1]), .I1 (des_mac[3]), .I2 (des_mac[5]), @@ -341144,7 +340576,7 @@ module icmp_rx GTP_LUT5 /* N123_16_14 */ #( .INIT(32'b00000000000000000000000000000001)) N123_16_14 ( - .Z (_N107590), + .Z (_N108422), .I0 (des_mac[8]), .I1 (des_mac[9]), .I2 (des_mac[11]), @@ -341155,7 +340587,7 @@ module icmp_rx GTP_LUT5 /* N123_16_18 */ #( .INIT(32'b00000000000000000000000000000001)) N123_16_18 ( - .Z (_N107594), + .Z (_N108426), .I0 (des_mac[15]), .I1 (des_mac[18]), .I2 (des_mac[19]), @@ -341166,7 +340598,7 @@ module icmp_rx GTP_LUT5 /* N123_16_22 */ #( .INIT(32'b00000000000000000000000000000001)) N123_16_22 ( - .Z (_N107598), + .Z (_N108430), .I0 (des_mac[24]), .I1 (des_mac[26]), .I2 (des_mac[27]), @@ -341177,7 +340609,7 @@ module icmp_rx GTP_LUT5 /* N123_16_26 */ #( .INIT(32'b00000000000000000000000000000001)) N123_16_26 ( - .Z (_N107602), + .Z (_N108434), .I0 (des_mac[31]), .I1 (des_mac[33]), .I2 (des_mac[34]), @@ -341188,7 +340620,7 @@ module icmp_rx GTP_LUT4 /* N123_16_28 */ #( .INIT(16'b0000000000000001)) N123_16_28 ( - .Z (_N107604), + .Z (_N108436), .I0 (des_mac[38]), .I1 (des_mac[39]), .I2 (des_mac[40]), @@ -341198,10 +340630,10 @@ module icmp_rx GTP_LUT5 /* N123_16_30 */ #( .INIT(32'b00000000000000000000000010000000)) N123_16_30 ( - .Z (_N107606), - .I0 (_N107581), - .I1 (_N107586), - .I2 (_N107604), + .Z (_N108438), + .I0 (_N108413), + .I1 (_N108418), + .I2 (_N108436), .I3 (des_mac[44]), .I4 (des_mac[45])); // LUT = I0&I1&I2&~I3&~I4 ; @@ -341209,17 +340641,17 @@ module icmp_rx GTP_LUT4 /* N123_16_33 */ #( .INIT(16'b1000000000000000)) N123_16_33 ( - .Z (_N107609), - .I0 (_N107590), - .I1 (_N107594), - .I2 (_N107598), - .I3 (_N107602)); + .Z (_N108441), + .I0 (_N108422), + .I1 (_N108426), + .I2 (_N108430), + .I3 (_N108434)); // LUT = I0&I1&I2&I3 ; GTP_LUT5 /* N123_17_6 */ #( .INIT(32'b10000000000000000000000000000000)) N123_17_6 ( - .Z (_N107549), + .Z (_N108381), .I0 (des_mac[42]), .I1 (des_mac[43]), .I2 (des_mac[44]), @@ -341230,7 +340662,7 @@ module icmp_rx GTP_LUT5 /* N123_17_10 */ #( .INIT(32'b10000000000000000000000000000000)) N123_17_10 ( - .Z (_N107553), + .Z (_N108385), .I0 (des_mac[1]), .I1 (des_mac[3]), .I2 (des_mac[5]), @@ -341241,7 +340673,7 @@ module icmp_rx GTP_LUT5 /* N123_17_14 */ #( .INIT(32'b10000000000000000000000000000000)) N123_17_14 ( - .Z (_N107557), + .Z (_N108389), .I0 (des_mac[8]), .I1 (des_mac[9]), .I2 (des_mac[11]), @@ -341252,7 +340684,7 @@ module icmp_rx GTP_LUT5 /* N123_17_18 */ #( .INIT(32'b10000000000000000000000000000000)) N123_17_18 ( - .Z (_N107561), + .Z (_N108393), .I0 (des_mac[15]), .I1 (des_mac[18]), .I2 (des_mac[19]), @@ -341263,7 +340695,7 @@ module icmp_rx GTP_LUT5 /* N123_17_22 */ #( .INIT(32'b10000000000000000000000000000000)) N123_17_22 ( - .Z (_N107565), + .Z (_N108397), .I0 (des_mac[24]), .I1 (des_mac[26]), .I2 (des_mac[27]), @@ -341274,7 +340706,7 @@ module icmp_rx GTP_LUT5 /* N123_17_26 */ #( .INIT(32'b10000000000000000000000000000000)) N123_17_26 ( - .Z (_N107569), + .Z (_N108401), .I0 (des_mac[31]), .I1 (des_mac[33]), .I2 (des_mac[34]), @@ -341285,8 +340717,8 @@ module icmp_rx GTP_LUT5 /* N123_17_29 */ #( .INIT(32'b10000000000000000000000000000000)) N123_17_29 ( - .Z (_N107572), - .I0 (_N107549), + .Z (_N108404), + .I0 (_N108381), .I1 (des_mac[38]), .I2 (des_mac[39]), .I3 (des_mac[40]), @@ -341296,17 +340728,17 @@ module icmp_rx GTP_LUT4 /* N123_17_33 */ #( .INIT(16'b1000000000000000)) N123_17_33 ( - .Z (_N107576), - .I0 (_N107557), - .I1 (_N107561), - .I2 (_N107565), - .I3 (_N107569)); + .Z (_N108408), + .I0 (_N108389), + .I1 (_N108393), + .I2 (_N108397), + .I3 (_N108401)); // LUT = I0&I1&I2&I3 ; GTP_LUT5 /* N129_29 */ #( .INIT(32'b00000000000000000000000000000001)) N129_29 ( - .Z (_N107614), + .Z (_N108446), .I0 (eth_type[8]), .I1 (eth_type[9]), .I2 (eth_type[10]), @@ -341317,7 +340749,7 @@ module icmp_rx GTP_LUT5 /* N129_33 */ #( .INIT(32'b00000000000000000000000010000000)) N129_33 ( - .Z (_N107618), + .Z (_N108450), .I0 (des_mac[0]), .I1 (des_mac[2]), .I2 (eth_type[11]), @@ -341328,7 +340760,7 @@ module icmp_rx GTP_LUT5 /* N129_37 */ #( .INIT(32'b10000000000000000000000000000000)) N129_37 ( - .Z (_N107622), + .Z (_N108454), .I0 (des_mac[4]), .I1 (des_mac[6]), .I2 (des_mac[10]), @@ -341339,7 +340771,7 @@ module icmp_rx GTP_LUT5 /* N129_41 */ #( .INIT(32'b10000000000000000000000000000000)) N129_41 ( - .Z (_N107626), + .Z (_N108458), .I0 (des_mac[17]), .I1 (des_mac[20]), .I2 (des_mac[21]), @@ -341350,8 +340782,8 @@ module icmp_rx GTP_LUT5 /* N129_44 */ #( .INIT(32'b00000010000000000000000000000000)) N129_44 ( - .Z (_N107629), - .I0 (_N81987), + .Z (_N108461), + .I0 (_N84941), .I1 (gmii_rxd_data[1]), .I2 (gmii_rxd_data[3]), .I3 (des_mac[32]), @@ -341361,22 +340793,22 @@ module icmp_rx GTP_LUT4 /* N129_47 */ #( .INIT(16'b0000001000000000)) N129_47 ( - .Z (_N107632), - .I0 (_N96556), + .Z (_N108464), + .I0 (_N97327), .I1 (gmii_rxd_data[0]), .I2 (gmii_rxd_data[4]), - .I3 (_N107626)); + .I3 (_N108458)); // LUT = I0&~I1&~I2&I3 ; GTP_LUT5 /* N129_49 */ #( .INIT(32'b10000000000000000000000000000000)) N129_49 ( .Z (N129), - .I0 (_N107614), - .I1 (_N107618), - .I2 (_N107622), - .I3 (_N107629), - .I4 (_N107632)); + .I0 (_N108446), + .I1 (_N108450), + .I2 (_N108454), + .I3 (_N108461), + .I4 (_N108464)); // LUT = I0&I1&I2&I3&I4 ; GTP_LUT5CARRY /* \N168_1.fsub_1 */ #( @@ -341655,8 +341087,8 @@ module icmp_rx GTP_LUT5 /* N195_28 */ #( .INIT(32'b00000000000000000010000000000000)) N195_28 ( - .Z (_N98508), - .I0 (_N96556), + .Z (_N100572), + .I0 (_N97327), .I1 (gmii_rxd_data[0]), .I2 (gmii_rxd_data[1]), .I3 (gmii_rxd_data[3]), @@ -341666,7 +341098,7 @@ module icmp_rx GTP_LUT5 /* N195_32 */ #( .INIT(32'b00000000000000000000000000000001)) N195_32 ( - .Z (_N107503), + .Z (_N108335), .I0 (des_ip[16]), .I1 (des_ip[17]), .I2 (des_ip[18]), @@ -341677,7 +341109,7 @@ module icmp_rx GTP_LUT5 /* N195_36 */ #( .INIT(32'b00000001000000000000000000000000)) N195_36 ( - .Z (_N107507), + .Z (_N108339), .I0 (des_ip[0]), .I1 (des_ip[2]), .I2 (des_ip[21]), @@ -341688,7 +341120,7 @@ module icmp_rx GTP_LUT5 /* N195_40 */ #( .INIT(32'b00000000000000000000000000000001)) N195_40 ( - .Z (_N107511), + .Z (_N108343), .I0 (des_ip[4]), .I1 (des_ip[5]), .I2 (des_ip[6]), @@ -341699,7 +341131,7 @@ module icmp_rx GTP_LUT5 /* N195_44 */ #( .INIT(32'b00000000000000000000000000000010)) N195_44 ( - .Z (_N107515), + .Z (_N108347), .I0 (des_ip[1]), .I1 (des_ip[9]), .I2 (des_ip[10]), @@ -341710,7 +341142,7 @@ module icmp_rx GTP_LUT4 /* N195_47 */ #( .INIT(16'b1000000000000000)) N195_47 ( - .Z (_N107518), + .Z (_N108350), .I0 (des_ip[3]), .I1 (des_ip[11]), .I2 (des_ip[13]), @@ -341720,28 +341152,28 @@ module icmp_rx GTP_LUT4 /* N195_51 */ #( .INIT(16'b1000000000000000)) N195_51 ( - .Z (_N107522), - .I0 (_N107503), - .I1 (_N107507), - .I2 (_N107511), - .I3 (_N107518)); + .Z (_N108354), + .I0 (_N108335), + .I1 (_N108339), + .I2 (_N108343), + .I3 (_N108350)); // LUT = I0&I1&I2&I3 ; GTP_LUT5 /* N195_56 */ #( .INIT(32'b10000000000000000000000000000000)) N195_56 ( .Z (N195), - .I0 (_N96999), + .I0 (_N97775), .I1 (gmii_rxd_data[1]), .I2 (gmii_rxd_data[3]), - .I3 (_N107515), - .I4 (_N107522)); + .I3 (_N108347), + .I4 (_N108354)); // LUT = I0&I1&I2&I3&I4 ; GTP_LUT2 /* N199_maj3_1 */ #( .INIT(4'b1110)) N199_maj3_1 ( - .Z (_N5466), + .Z (_N5329), .I0 (ip_head_byte_num[2]), .I1 (ip_head_byte_num[3])); // LUT = (I0)|(I1) ; @@ -341807,7 +341239,7 @@ module icmp_rx .Z (), .CIN (\N216.co [2] ), .I0 (cnt[4]), - .I1 (_N5466), + .I1 (_N5329), .I2 (_N10697), .I3 (ip_head_byte_num[4]), .I4 (), @@ -341816,36 +341248,26 @@ module icmp_rx // CARRY = ((I0&~I1&I2&~I3)|(~I0&I1&I2&~I3)|(~I0&~I1&I2&I3)|(I0&I1&I2&I3)) ? CIN : (1'b0) ; // ../../sources/designs/udp_osd/eth_udp/icmp/icmp_rx.v:227 - GTP_LUT4 /* N230_9_3 */ #( - .INIT(16'b0000001110100011)) - N230_9_3 ( - .Z (_N100419), - .I0 (N195), - .I1 (N216), - .I2 (N579), - .I3 (N602)); - // LUT = (~I1&~I2)|(I0&I2&~I3) ; - GTP_LUT4 /* \N232_and[0] */ #( .INIT(16'b0101110100001100)) \N232_and[0] ( - .Z (_N29955), + .Z (_N29901), .I0 (N195), .I1 (N577), .I2 (N578), .I3 (N579)); // LUT = (I1&~I2)|(~I0&I3) ; - GTP_LUT5 /* N257_13_2 */ #( - .INIT(32'b11111111111111111111111000001110)) - N257_13_2 ( - .Z (_N18470), - .I0 (_N100419), - .I1 (N183), - .I2 (N577), - .I3 (N578), - .I4 (N1309)); - // LUT = (I4)|(I0&~I2)|(I1&~I2)|(I2&I3) ; + GTP_LUT5 /* N257_13_4 */ #( + .INIT(32'b10101010101011111110111010101111)) + N257_13_4 ( + .Z (_N103649_2), + .I0 (N183), + .I1 (N195), + .I2 (N216), + .I3 (N579), + .I4 (N602)); + // LUT = (I0)|(~I2&~I3)|(I1&I3&~I4) ; GTP_LUT5CARRY /* N356_1_1 */ #( .INIT(32'b00000110000001100000000000000000), @@ -341854,7 +341276,7 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N356_1_1 ( - .COUT (_N17055), + .COUT (_N13798), .Z (N1142[1]), .CIN (), .I0 (icmp_rx_cnt[0]), @@ -341874,9 +341296,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N356_1_2 ( - .COUT (_N17056), + .COUT (_N13799), .Z (N1142[2]), - .CIN (_N17055), + .CIN (_N13798), .I0 (icmp_rx_cnt[0]), .I1 (icmp_rx_cnt[1]), .I2 (N397), @@ -341894,9 +341316,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N356_1_3 ( - .COUT (_N17057), + .COUT (_N13800), .Z (N1142[3]), - .CIN (_N17056), + .CIN (_N13799), .I0 (), .I1 (icmp_rx_cnt[3]), .I2 (N397), @@ -341914,9 +341336,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N356_1_4 ( - .COUT (_N17058), + .COUT (_N13801), .Z (N1142[4]), - .CIN (_N17057), + .CIN (_N13800), .I0 (), .I1 (icmp_rx_cnt[4]), .I2 (N397), @@ -341934,9 +341356,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N356_1_5 ( - .COUT (_N17059), + .COUT (_N13802), .Z (N1142[5]), - .CIN (_N17058), + .CIN (_N13801), .I0 (), .I1 (icmp_rx_cnt[5]), .I2 (N397), @@ -341954,9 +341376,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N356_1_6 ( - .COUT (_N17060), + .COUT (_N13803), .Z (N1142[6]), - .CIN (_N17059), + .CIN (_N13802), .I0 (), .I1 (icmp_rx_cnt[6]), .I2 (N397), @@ -341974,9 +341396,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N356_1_7 ( - .COUT (_N17061), + .COUT (_N13804), .Z (N1142[7]), - .CIN (_N17060), + .CIN (_N13803), .I0 (), .I1 (icmp_rx_cnt[7]), .I2 (N397), @@ -341994,9 +341416,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N356_1_8 ( - .COUT (_N17062), + .COUT (_N13805), .Z (N1142[8]), - .CIN (_N17061), + .CIN (_N13804), .I0 (), .I1 (icmp_rx_cnt[8]), .I2 (N397), @@ -342014,9 +341436,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N356_1_9 ( - .COUT (_N17063), + .COUT (_N13806), .Z (N1142[9]), - .CIN (_N17062), + .CIN (_N13805), .I0 (), .I1 (icmp_rx_cnt[9]), .I2 (N397), @@ -342034,9 +341456,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N356_1_10 ( - .COUT (_N17064), + .COUT (_N13807), .Z (N1142[10]), - .CIN (_N17063), + .CIN (_N13806), .I0 (), .I1 (icmp_rx_cnt[10]), .I2 (N397), @@ -342054,9 +341476,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N356_1_11 ( - .COUT (_N17065), + .COUT (_N13808), .Z (N1142[11]), - .CIN (_N17064), + .CIN (_N13807), .I0 (), .I1 (icmp_rx_cnt[11]), .I2 (N397), @@ -342074,9 +341496,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N356_1_12 ( - .COUT (_N17066), + .COUT (_N13809), .Z (N1142[12]), - .CIN (_N17065), + .CIN (_N13808), .I0 (), .I1 (icmp_rx_cnt[12]), .I2 (N397), @@ -342094,9 +341516,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N356_1_13 ( - .COUT (_N17067), + .COUT (_N13810), .Z (N1142[13]), - .CIN (_N17066), + .CIN (_N13809), .I0 (), .I1 (icmp_rx_cnt[13]), .I2 (N397), @@ -342114,9 +341536,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N356_1_14 ( - .COUT (_N17068), + .COUT (_N13811), .Z (N1142[14]), - .CIN (_N17067), + .CIN (_N13810), .I0 (), .I1 (icmp_rx_cnt[14]), .I2 (N397), @@ -342136,7 +341558,7 @@ module icmp_rx N356_1_15 ( .COUT (), .Z (N1142[15]), - .CIN (_N17068), + .CIN (_N13811), .I0 (), .I1 (icmp_rx_cnt[15]), .I2 (N397), @@ -342654,7 +342076,7 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N372_1 ( - .COUT (_N14323), + .COUT (_N14328), .Z (N372[0]), .CIN (), .I0 (gmii_rxd_data[0]), @@ -342674,9 +342096,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N372_2 ( - .COUT (_N14324), + .COUT (_N14329), .Z (N372[1]), - .CIN (_N14323), + .CIN (_N14328), .I0 (gmii_rxd_data[0]), .I1 (reply_checksum_add[0]), .I2 (gmii_rxd_data[1]), @@ -342694,9 +342116,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N372_3 ( - .COUT (_N14325), + .COUT (_N14330), .Z (N372[2]), - .CIN (_N14324), + .CIN (_N14329), .I0 (), .I1 (gmii_rxd_data[2]), .I2 (reply_checksum_add[2]), @@ -342714,9 +342136,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N372_4 ( - .COUT (_N14326), + .COUT (_N14331), .Z (N372[3]), - .CIN (_N14325), + .CIN (_N14330), .I0 (), .I1 (gmii_rxd_data[3]), .I2 (reply_checksum_add[3]), @@ -342734,9 +342156,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N372_5 ( - .COUT (_N14327), + .COUT (_N14332), .Z (N372[4]), - .CIN (_N14326), + .CIN (_N14331), .I0 (), .I1 (gmii_rxd_data[4]), .I2 (reply_checksum_add[4]), @@ -342754,9 +342176,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N372_6 ( - .COUT (_N14328), + .COUT (_N14333), .Z (N372[5]), - .CIN (_N14327), + .CIN (_N14332), .I0 (), .I1 (gmii_rxd_data[5]), .I2 (reply_checksum_add[5]), @@ -342774,9 +342196,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N372_7 ( - .COUT (_N14329), + .COUT (_N14334), .Z (N372[6]), - .CIN (_N14328), + .CIN (_N14333), .I0 (), .I1 (gmii_rxd_data[6]), .I2 (reply_checksum_add[6]), @@ -342794,9 +342216,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N372_8 ( - .COUT (_N14330), + .COUT (_N14335), .Z (N372[7]), - .CIN (_N14329), + .CIN (_N14334), .I0 (), .I1 (gmii_rxd_data[7]), .I2 (reply_checksum_add[7]), @@ -342814,9 +342236,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N372_9 ( - .COUT (_N14331), + .COUT (_N14336), .Z (N372[8]), - .CIN (_N14330), + .CIN (_N14335), .I0 (), .I1 (reply_checksum_add[8]), .I2 (), @@ -342834,9 +342256,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N372_10 ( - .COUT (_N14332), + .COUT (_N14337), .Z (N372[9]), - .CIN (_N14331), + .CIN (_N14336), .I0 (), .I1 (reply_checksum_add[9]), .I2 (), @@ -342854,9 +342276,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N372_11 ( - .COUT (_N14333), + .COUT (_N14338), .Z (N372[10]), - .CIN (_N14332), + .CIN (_N14337), .I0 (), .I1 (reply_checksum_add[10]), .I2 (), @@ -342874,9 +342296,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N372_12 ( - .COUT (_N14334), + .COUT (_N14339), .Z (N372[11]), - .CIN (_N14333), + .CIN (_N14338), .I0 (), .I1 (reply_checksum_add[11]), .I2 (), @@ -342894,9 +342316,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N372_13 ( - .COUT (_N14335), + .COUT (_N14340), .Z (N372[12]), - .CIN (_N14334), + .CIN (_N14339), .I0 (), .I1 (reply_checksum_add[12]), .I2 (), @@ -342914,9 +342336,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N372_14 ( - .COUT (_N14336), + .COUT (_N14341), .Z (N372[13]), - .CIN (_N14335), + .CIN (_N14340), .I0 (), .I1 (reply_checksum_add[13]), .I2 (), @@ -342934,9 +342356,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N372_15 ( - .COUT (_N14337), + .COUT (_N14342), .Z (N372[14]), - .CIN (_N14336), + .CIN (_N14341), .I0 (), .I1 (reply_checksum_add[14]), .I2 (), @@ -342954,9 +342376,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N372_16 ( - .COUT (_N14338), + .COUT (_N14343), .Z (N372[15]), - .CIN (_N14337), + .CIN (_N14342), .I0 (), .I1 (reply_checksum_add[15]), .I2 (), @@ -342974,9 +342396,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N372_17 ( - .COUT (_N14339), + .COUT (_N14344), .Z (N372[16]), - .CIN (_N14338), + .CIN (_N14343), .I0 (), .I1 (reply_checksum_add[16]), .I2 (), @@ -342994,9 +342416,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N372_18 ( - .COUT (_N14340), + .COUT (_N14345), .Z (N372[17]), - .CIN (_N14339), + .CIN (_N14344), .I0 (), .I1 (reply_checksum_add[17]), .I2 (), @@ -343014,9 +342436,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N372_19 ( - .COUT (_N14341), + .COUT (_N14346), .Z (N372[18]), - .CIN (_N14340), + .CIN (_N14345), .I0 (), .I1 (reply_checksum_add[18]), .I2 (), @@ -343034,9 +342456,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N372_20 ( - .COUT (_N14342), + .COUT (_N14347), .Z (N372[19]), - .CIN (_N14341), + .CIN (_N14346), .I0 (), .I1 (reply_checksum_add[19]), .I2 (), @@ -343054,9 +342476,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N372_21 ( - .COUT (_N14343), + .COUT (_N14348), .Z (N372[20]), - .CIN (_N14342), + .CIN (_N14347), .I0 (), .I1 (reply_checksum_add[20]), .I2 (), @@ -343074,9 +342496,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N372_22 ( - .COUT (_N14344), + .COUT (_N14349), .Z (N372[21]), - .CIN (_N14343), + .CIN (_N14348), .I0 (), .I1 (reply_checksum_add[21]), .I2 (), @@ -343094,9 +342516,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N372_23 ( - .COUT (_N14345), + .COUT (_N14350), .Z (N372[22]), - .CIN (_N14344), + .CIN (_N14349), .I0 (), .I1 (reply_checksum_add[22]), .I2 (), @@ -343114,9 +342536,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N372_24 ( - .COUT (_N14346), + .COUT (_N14351), .Z (N372[23]), - .CIN (_N14345), + .CIN (_N14350), .I0 (), .I1 (reply_checksum_add[23]), .I2 (), @@ -343134,9 +342556,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N372_25 ( - .COUT (_N14347), + .COUT (_N14352), .Z (N372[24]), - .CIN (_N14346), + .CIN (_N14351), .I0 (), .I1 (reply_checksum_add[24]), .I2 (), @@ -343154,9 +342576,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N372_26 ( - .COUT (_N14348), + .COUT (_N14353), .Z (N372[25]), - .CIN (_N14347), + .CIN (_N14352), .I0 (), .I1 (reply_checksum_add[25]), .I2 (), @@ -343174,9 +342596,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N372_27 ( - .COUT (_N14349), + .COUT (_N14354), .Z (N372[26]), - .CIN (_N14348), + .CIN (_N14353), .I0 (), .I1 (reply_checksum_add[26]), .I2 (), @@ -343194,9 +342616,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N372_28 ( - .COUT (_N14350), + .COUT (_N14355), .Z (N372[27]), - .CIN (_N14349), + .CIN (_N14354), .I0 (), .I1 (reply_checksum_add[27]), .I2 (), @@ -343214,9 +342636,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N372_29 ( - .COUT (_N14351), + .COUT (_N14356), .Z (N372[28]), - .CIN (_N14350), + .CIN (_N14355), .I0 (), .I1 (reply_checksum_add[28]), .I2 (), @@ -343234,9 +342656,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N372_30 ( - .COUT (_N14352), + .COUT (_N14357), .Z (N372[29]), - .CIN (_N14351), + .CIN (_N14356), .I0 (), .I1 (reply_checksum_add[29]), .I2 (), @@ -343254,9 +342676,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N372_31 ( - .COUT (_N14353), + .COUT (_N14358), .Z (N372[30]), - .CIN (_N14352), + .CIN (_N14357), .I0 (), .I1 (reply_checksum_add[30]), .I2 (), @@ -343276,7 +342698,7 @@ module icmp_rx N372_32 ( .COUT (), .Z (N372[31]), - .CIN (_N14353), + .CIN (_N14358), .I0 (), .I1 (reply_checksum_add[31]), .I2 (), @@ -343294,7 +342716,7 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N375_1 ( - .COUT (_N14356), + .COUT (_N14370), .Z (N375[0]), .CIN (), .I0 (gmii_rxd_data[0]), @@ -343314,9 +342736,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N375_2 ( - .COUT (_N14357), + .COUT (_N14371), .Z (N375[1]), - .CIN (_N14356), + .CIN (_N14370), .I0 (gmii_rxd_data[0]), .I1 (reply_checksum_add[0]), .I2 (gmii_rxd_data[1]), @@ -343334,9 +342756,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N375_3 ( - .COUT (_N14358), + .COUT (_N14372), .Z (N375[2]), - .CIN (_N14357), + .CIN (_N14371), .I0 (), .I1 (gmii_rxd_data[2]), .I2 (reply_checksum_add[2]), @@ -343354,9 +342776,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N375_4 ( - .COUT (_N14359), + .COUT (_N14373), .Z (N375[3]), - .CIN (_N14358), + .CIN (_N14372), .I0 (), .I1 (gmii_rxd_data[3]), .I2 (reply_checksum_add[3]), @@ -343374,9 +342796,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N375_5 ( - .COUT (_N14360), + .COUT (_N14374), .Z (N375[4]), - .CIN (_N14359), + .CIN (_N14373), .I0 (), .I1 (gmii_rxd_data[4]), .I2 (reply_checksum_add[4]), @@ -343394,9 +342816,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N375_6 ( - .COUT (_N14361), + .COUT (_N14375), .Z (N375[5]), - .CIN (_N14360), + .CIN (_N14374), .I0 (), .I1 (gmii_rxd_data[5]), .I2 (reply_checksum_add[5]), @@ -343414,9 +342836,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N375_7 ( - .COUT (_N14362), + .COUT (_N14376), .Z (N375[6]), - .CIN (_N14361), + .CIN (_N14375), .I0 (), .I1 (gmii_rxd_data[6]), .I2 (reply_checksum_add[6]), @@ -343434,9 +342856,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N375_8 ( - .COUT (_N14363), + .COUT (_N14377), .Z (N375[7]), - .CIN (_N14362), + .CIN (_N14376), .I0 (), .I1 (gmii_rxd_data[7]), .I2 (reply_checksum_add[7]), @@ -343454,9 +342876,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N375_9 ( - .COUT (_N14364), + .COUT (_N14378), .Z (N375[8]), - .CIN (_N14363), + .CIN (_N14377), .I0 (), .I1 (icmp_rx_data_d0[0]), .I2 (reply_checksum_add[8]), @@ -343474,9 +342896,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N375_10 ( - .COUT (_N14365), + .COUT (_N14379), .Z (N375[9]), - .CIN (_N14364), + .CIN (_N14378), .I0 (), .I1 (icmp_rx_data_d0[1]), .I2 (reply_checksum_add[9]), @@ -343494,9 +342916,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N375_11 ( - .COUT (_N14366), + .COUT (_N14380), .Z (N375[10]), - .CIN (_N14365), + .CIN (_N14379), .I0 (), .I1 (icmp_rx_data_d0[2]), .I2 (reply_checksum_add[10]), @@ -343514,9 +342936,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N375_12 ( - .COUT (_N14367), + .COUT (_N14381), .Z (N375[11]), - .CIN (_N14366), + .CIN (_N14380), .I0 (), .I1 (icmp_rx_data_d0[3]), .I2 (reply_checksum_add[11]), @@ -343534,9 +342956,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N375_13 ( - .COUT (_N14368), + .COUT (_N14382), .Z (N375[12]), - .CIN (_N14367), + .CIN (_N14381), .I0 (), .I1 (icmp_rx_data_d0[4]), .I2 (reply_checksum_add[12]), @@ -343554,9 +342976,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N375_14 ( - .COUT (_N14369), + .COUT (_N14383), .Z (N375[13]), - .CIN (_N14368), + .CIN (_N14382), .I0 (), .I1 (icmp_rx_data_d0[5]), .I2 (reply_checksum_add[13]), @@ -343574,9 +342996,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N375_15 ( - .COUT (_N14370), + .COUT (_N14384), .Z (N375[14]), - .CIN (_N14369), + .CIN (_N14383), .I0 (), .I1 (icmp_rx_data_d0[6]), .I2 (reply_checksum_add[14]), @@ -343594,9 +343016,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N375_16 ( - .COUT (_N14371), + .COUT (_N14385), .Z (N375[15]), - .CIN (_N14370), + .CIN (_N14384), .I0 (), .I1 (icmp_rx_data_d0[7]), .I2 (reply_checksum_add[15]), @@ -343614,9 +343036,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N375_17 ( - .COUT (_N14372), + .COUT (_N14386), .Z (N375[16]), - .CIN (_N14371), + .CIN (_N14385), .I0 (), .I1 (reply_checksum_add[16]), .I2 (), @@ -343634,9 +343056,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N375_18 ( - .COUT (_N14373), + .COUT (_N14387), .Z (N375[17]), - .CIN (_N14372), + .CIN (_N14386), .I0 (), .I1 (reply_checksum_add[17]), .I2 (), @@ -343654,9 +343076,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N375_19 ( - .COUT (_N14374), + .COUT (_N14388), .Z (N375[18]), - .CIN (_N14373), + .CIN (_N14387), .I0 (), .I1 (reply_checksum_add[18]), .I2 (), @@ -343674,9 +343096,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N375_20 ( - .COUT (_N14375), + .COUT (_N14389), .Z (N375[19]), - .CIN (_N14374), + .CIN (_N14388), .I0 (), .I1 (reply_checksum_add[19]), .I2 (), @@ -343694,9 +343116,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N375_21 ( - .COUT (_N14376), + .COUT (_N14390), .Z (N375[20]), - .CIN (_N14375), + .CIN (_N14389), .I0 (), .I1 (reply_checksum_add[20]), .I2 (), @@ -343714,9 +343136,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N375_22 ( - .COUT (_N14377), + .COUT (_N14391), .Z (N375[21]), - .CIN (_N14376), + .CIN (_N14390), .I0 (), .I1 (reply_checksum_add[21]), .I2 (), @@ -343734,9 +343156,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N375_23 ( - .COUT (_N14378), + .COUT (_N14392), .Z (N375[22]), - .CIN (_N14377), + .CIN (_N14391), .I0 (), .I1 (reply_checksum_add[22]), .I2 (), @@ -343754,9 +343176,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N375_24 ( - .COUT (_N14379), + .COUT (_N14393), .Z (N375[23]), - .CIN (_N14378), + .CIN (_N14392), .I0 (), .I1 (reply_checksum_add[23]), .I2 (), @@ -343774,9 +343196,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N375_25 ( - .COUT (_N14380), + .COUT (_N14394), .Z (N375[24]), - .CIN (_N14379), + .CIN (_N14393), .I0 (), .I1 (reply_checksum_add[24]), .I2 (), @@ -343794,9 +343216,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N375_26 ( - .COUT (_N14381), + .COUT (_N14395), .Z (N375[25]), - .CIN (_N14380), + .CIN (_N14394), .I0 (), .I1 (reply_checksum_add[25]), .I2 (), @@ -343814,9 +343236,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N375_27 ( - .COUT (_N14382), + .COUT (_N14396), .Z (N375[26]), - .CIN (_N14381), + .CIN (_N14395), .I0 (), .I1 (reply_checksum_add[26]), .I2 (), @@ -343834,9 +343256,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N375_28 ( - .COUT (_N14383), + .COUT (_N14397), .Z (N375[27]), - .CIN (_N14382), + .CIN (_N14396), .I0 (), .I1 (reply_checksum_add[27]), .I2 (), @@ -343854,9 +343276,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N375_29 ( - .COUT (_N14384), + .COUT (_N14398), .Z (N375[28]), - .CIN (_N14383), + .CIN (_N14397), .I0 (), .I1 (reply_checksum_add[28]), .I2 (), @@ -343874,9 +343296,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N375_30 ( - .COUT (_N14385), + .COUT (_N14399), .Z (N375[29]), - .CIN (_N14384), + .CIN (_N14398), .I0 (), .I1 (reply_checksum_add[29]), .I2 (), @@ -343894,9 +343316,9 @@ module icmp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N375_31 ( - .COUT (_N14386), + .COUT (_N14400), .Z (N375[30]), - .CIN (_N14385), + .CIN (_N14399), .I0 (), .I1 (reply_checksum_add[30]), .I2 (), @@ -343916,7 +343338,7 @@ module icmp_rx N375_32 ( .COUT (), .Z (N375[31]), - .CIN (_N14386), + .CIN (_N14400), .I0 (), .I1 (reply_checksum_add[31]), .I2 (), @@ -344087,116 +343509,124 @@ module icmp_rx // CARRY = ((~I0&~I1&~I2&~I3)|(I0&I1&~I2&~I3)|(~I0&~I1&I2&I3)|(I0&I1&I2&I3)) ? CIN : ((I2&~I3)|(I0&~I1&~I3)|(I0&~I1&I2)) ; // ../../sources/designs/udp_osd/eth_udp/icmp/icmp_rx.v:271 + GTP_LUT2 /* N421 */ #( + .INIT(4'b0001)) + N421_vname ( + .Z (N421), + .I0 (gmii_rxd_valid), + .I1 (skip_en)); + // defparam N421_vname.orig_name = N421; + // LUT = ~I0&~I1 ; + // ../../sources/designs/udp_osd/eth_udp/icmp/icmp_rx.v:289 + GTP_LUT4 /* N436_11_3 */ #( .INIT(16'b1000000000000000)) N436_11_3 ( - .Z (_N22164), - .I0 (_N95922), - .I1 (_N96007), - .I2 (_N96693), + .Z (_N22650), + .I0 (_N96654), + .I1 (_N96834), + .I2 (_N97535), .I3 (N516)); // LUT = I0&I1&I2&I3 ; GTP_LUT5 /* N436_15_3 */ #( .INIT(32'b00000000000000000000000010000000)) N436_15_3 ( - .Z (_N107647), - .I0 (_N95922), + .Z (_N108479), + .I0 (_N96654), .I1 (gmii_rxd_valid), .I2 (N1304), .I3 (next_state[3]), .I4 (next_state[4])); // LUT = I0&I1&I2&~I3&~I4 ; - GTP_LUT5M /* N436_18_3 */ #( - .INIT(32'b01000100000000001000110000000000)) + GTP_LUT5 /* N436_18_3 */ #( + .INIT(32'b00000000000000000000000000000010)) N436_18_3 ( - .Z (_N107652), - .I0 (cur_state_reg[3]), - .I1 (_N95922), - .I2 (cur_state_reg[4]), - .I3 (gmii_rxd_valid), - .I4 (skip_en), - .ID (error_en)); - // LUT = (I1&~I2&I3&~I4)|(ID&I1&I3&~I4)|(~I0&I1&I3&I4) ; + .Z (_N108484), + .I0 (gmii_rxd_valid), + .I1 (N183), + .I2 (N577), + .I3 (N1309), + .I4 (next_state[4])); + // LUT = I0&~I1&~I2&~I3&~I4 ; GTP_LUT5M /* N436_18_5 */ #( - .INIT(32'b00000000100000000000000010001000)) + .INIT(32'b10000000000000001000100000000000)) N436_18_5 ( - .Z (_N22171), + .Z (_N22657), .I0 (N195), - .I1 (_N107652), + .I1 (_N96654), .I2 (N602), - .I3 (N1326), + .I3 (_N108484), .I4 (N579), .ID (N216)); - // LUT = (ID&I1&~I3&~I4)|(I0&I1&I2&~I3&I4) ; - - GTP_LUT3 /* N436_22 */ #( - .INIT(8'b00010000)) - N436_22 ( - .Z (_N22175), - .I0 (gmii_rxd_valid), - .I1 (skip_en), - .I2 (next_state[6])); - // LUT = ~I0&~I1&I2 ; + // LUT = (ID&I1&I3&~I4)|(I0&I1&I2&I3&I4) ; GTP_LUT5 /* N436_24 */ #( - .INIT(32'b00110000001100001011100000110000)) + .INIT(32'b00001000111111110000100000000000)) N436_24 ( - .Z (_N22177), + .Z (_N22663), .I0 (gmii_rxd_valid), - .I1 (_N108067), - .I2 (_N108068), - .I3 (N397), - .I4 (next_state[6])); - // LUT = (~I1&I2)|(I0&I1&I3&~I4) ; + .I1 (N397), + .I2 (next_state[6]), + .I3 (_N108902), + .I4 (_N108903)); + // LUT = (~I3&I4)|(I0&I1&~I2&I3) ; GTP_MUX2LUT6 N436_25 ( - .Z (_N22178), - .I0 (_N22177), - .I1 (_N22171), + .Z (_N22664), + .I0 (_N22663), + .I1 (_N22657), .S (next_state[3])); GTP_LUT5M /* N436_27 */ #( .INIT(32'b10101010101010101100000010101010)) N436_27 ( - .Z (_N22180), - .I0 (_N22164), - .I1 (N129), - .I2 (_N107647), + .Z (_N22666), + .I0 (_N22650), + .I1 (_N108479), + .I2 (N129), .I3 (next_state[2]), .I4 (next_state[1]), - .ID (_N22178)); + .ID (_N22664)); // LUT = (ID&~I3&~I4)|(I1&I2&I3&~I4)|(I0&I4) ; GTP_LUT5M /* N436_28 */ #( .INIT(32'b00000000100000001010101010101010)) N436_28 ( .Z (N436), - .I0 (_N95922), + .I0 (_N96654), .I1 (N74), - .I2 (_N96007), + .I2 (_N96834), .I3 (next_state[1]), .I4 (next_state[0]), - .ID (_N22180)); + .ID (_N22666)); // LUT = (ID&~I4)|(I0&I1&I2&~I3&I4) ; - GTP_LUT5 /* N436_66 */ #( - .INIT(32'b11001100110001000000000000000000)) - N436_66 ( - .Z (_N96774), - .I0 (_N96096), - .I1 (_N96358), - .I2 (\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt [1] ), - .I3 (\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt [2] ), - .I4 (_N107965)); - // LUT = (~I0&I1&I4)|(I1&I2&I4)|(I1&I3&I4) ; + GTP_LUT2 /* N436_30 */ #( + .INIT(4'b1000)) + N436_30 ( + .Z (\udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N559 ), + .I0 (gmii_rxd_valid), + .I1 (\udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N366 )); + // LUT = I0&I1 ; - GTP_LUT5 /* N436_69 */ #( + GTP_LUT5 /* N436_31 */ #( + .INIT(32'b00000000000000000000000000000001)) + N436_31 ( + .Z (_N97542), + .I0 (\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/next_state [0] ), + .I1 (\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/next_state [1] ), + .I2 (\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/next_state [2] ), + .I3 (\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/next_state [3] ), + .I4 (\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/next_state [4] )); + // LUT = ~I0&~I1&~I2&~I3&~I4 ; + + GTP_LUT5 /* N436_67 */ #( .INIT(32'b00100000001100001110110000110000)) - N436_69 ( - .Z (_N108067), + N436_67 ( + .Z (_N108902), .I0 (error_en), .I1 (skip_en), .I2 (cur_state_reg[5]), @@ -344204,33 +343634,33 @@ module icmp_rx .I4 (cur_state_reg[3])); // LUT = (I1&I3&~I4)|(~I1&I2&~I3)|(I0&~I1&I2) ; - GTP_LUT5M /* N436_70 */ #( - .INIT(32'b10000000000000001010101010101010)) - N436_70 ( - .Z (_N108068), - .I0 (_N95922), - .I1 (N619), - .I2 (N1261), - .I3 (gmii_rxd_valid), + GTP_LUT5M /* N436_68 */ #( + .INIT(32'b10000000100000001010101000000000)) + N436_68 ( + .Z (_N108903), + .I0 (_N96654), + .I1 (N1265), + .I2 (N619), + .I3 (next_state[6]), .I4 (next_state[4]), - .ID (_N22175)); - // LUT = (ID&~I4)|(I0&I1&I2&I3&I4) ; + .ID (N421)); + // LUT = (ID&I3&~I4)|(I0&I1&I2&I4) ; GTP_LUT5 /* \N438_1_or[0]_1_3 */ #( - .INIT(32'b11101010111111111110101011101010)) + .INIT(32'b11101111111011101010111110101010)) \N438_1_or[0]_1_3 ( .Z (N438), - .I0 (_N81758), - .I1 (_N107635), - .I2 (N518), - .I3 (N619), - .I4 (N1269)); - // LUT = (I0)|(~I3&I4)|(I1&I2) ; + .I0 (_N84087), + .I1 (N518), + .I2 (N619), + .I3 (N1269), + .I4 (_N108467)); + // LUT = (I0)|(~I2&I3)|(I1&I4) ; GTP_LUT3 /* \N438_1_or[0]_2_2 */ #( .INIT(8'b00100000)) \N438_1_or[0]_2_2 ( - .Z (_N107635), + .Z (_N108467), .I0 (gmii_rxd_valid), .I1 (N129), .I2 (N1304)); @@ -344239,8 +343669,8 @@ module icmp_rx GTP_LUT5 /* \N438_1_or[0]_4 */ #( .INIT(32'b11001000100010001100000000000000)) \N438_1_or[0]_4 ( - .Z (_N81758), - .I0 (_N29955), + .Z (_N84087), + .I0 (_N29901), .I1 (gmii_rxd_valid), .I2 (N100), .I3 (N511), @@ -344248,47 +343678,25 @@ module icmp_rx // LUT = (I0&I1&I4)|(I1&I2&I3) ; GTP_LUT5 /* \N438_1_or[0]_8 */ #( - .INIT(32'b00000000000000001000000000000000)) + .INIT(32'b00000000000000000010111000111111)) \N438_1_or[0]_8 ( - .Z (N963), - .I0 (_N95975), - .I1 (_N96007), - .I2 (gmii_rxd_valid), - .I3 (next_state[5]), - .I4 (next_state[6])); - // LUT = I0&I1&I2&I3&~I4 ; - - GTP_LUT5M /* \N438_1_or[0]_13 */ #( - .INIT(32'b01010000000000000000010000000000)) - \N438_1_or[0]_13 ( - .Z (_N108059), - .I0 (cur_state_reg[2]), - .I1 (cur_state_reg[4]), - .I2 (cur_state_reg[3]), - .I3 (gmii_rxd_valid), - .I4 (skip_en), - .ID (error_en)); - // LUT = (~ID&I1&~I2&I3&~I4)|(~I0&I2&I3&I4) ; - - GTP_LUT4 /* \N438_1_or[0]_14 */ #( - .INIT(16'b0000000010000000)) - \N438_1_or[0]_14 ( - .Z (N801), - .I0 (_N95922), - .I1 (_N95975), - .I2 (_N108059), - .I3 (next_state[2])); - // LUT = I0&I1&I2&~I3 ; + .Z (_N96787), + .I0 (error_en), + .I1 (skip_en), + .I2 (cur_state_reg[6]), + .I3 (cur_state_reg[1]), + .I4 (cur_state_reg[0])); + // LUT = (~I1&~I3&~I4)|(I1&~I2&~I4)|(I0&~I1&~I4) ; GTP_LUT5 /* N456_2 */ #( .INIT(32'b10000000000000000000000000000000)) N456_2 ( .Z (N456), - .I0 (_N95975), - .I1 (_N96007), + .I0 (_N96787), + .I1 (_N96834), .I2 (gmii_rxd_valid), - .I3 (_N107657), - .I4 (N397)); + .I3 (N397), + .I4 (_N108489)); // LUT = I0&I1&I2&I3&I4 ; // ../../sources/designs/udp_osd/eth_udp/icmp/icmp_rx.v:166 @@ -344297,8 +343705,8 @@ module icmp_rx N511_3 ( .Z (N511), .I0 (cur_state_reg[6]), - .I1 (_N95922), - .I2 (_N96007), + .I1 (_N96654), + .I2 (_N96834), .I3 (next_state[1]), .I4 (skip_en), .ID (cur_state_reg[0])); @@ -344317,23 +343725,12 @@ module icmp_rx // LUT = ~I0&I1&I2&~I3&~I4 ; // ../../sources/designs/udp_osd/eth_udp/icmp/icmp_rx.v:176 - GTP_LUT5 /* N518_1 */ #( - .INIT(32'b10000000000000000000000000000000)) - N518_1 ( - .Z (N1269), - .I0 (_N95922), - .I1 (_N95975), - .I2 (gmii_rxd_valid), - .I3 (_N108064), - .I4 (N1261)); - // LUT = I0&I1&I2&I3&I4 ; - GTP_LUT5 /* N518_5 */ #( .INIT(32'b00000000000000000000000010000000)) N518_5 ( .Z (N518), - .I0 (_N95922), - .I1 (_N95975), + .I0 (_N96654), + .I1 (_N96787), .I2 (next_state[2]), .I3 (next_state[3]), .I4 (next_state[4])); @@ -344343,29 +343740,47 @@ module icmp_rx .INIT(32'b00000000000000000000100000000000)) N571_5 ( .Z (N571), - .I0 (_N95922), - .I1 (_N95975), + .I0 (_N96654), + .I1 (_N96787), .I2 (next_state[2]), .I3 (next_state[3]), .I4 (next_state[4])); // LUT = I0&I1&~I2&I3&~I4 ; - GTP_LUT5 /* N573 */ #( + GTP_LUT5 /* N573_3 */ #( .INIT(32'b00000000000000000000000000000001)) - N573_vname ( + N573_3 ( .Z (N573), .I0 (cnt[0]), .I1 (cnt[1]), .I2 (cnt[2]), .I3 (cnt[3]), .I4 (cnt[4])); - // defparam N573_vname.orig_name = N573; // LUT = ~I0&~I1&~I2&~I3&~I4 ; - // ../../sources/designs/udp_osd/eth_udp/icmp/icmp_rx.v:201 - GTP_LUT5 /* N577_3 */ #( + GTP_LUT4 /* N575_1 */ #( + .INIT(16'b0000000100001101)) + N575_1 ( + .Z (_N96653), + .I0 (_N82491), + .I1 (\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/skip_en ), + .I2 (\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg [5] ), + .I3 (\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg [4] )); + // LUT = (I1&~I2&~I3)|(~I0&~I1&~I2) ; + + GTP_LUT4 /* N577_1 */ #( + .INIT(16'b0000000001000000)) + N577_1 ( + .Z (_N97540), + .I0 (\udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt [1] ), + .I1 (\udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt [2] ), + .I2 (\udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt [3] ), + .I3 (\udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt [4] )); + // LUT = ~I0&I1&I2&~I3 ; + + GTP_LUT5 /* N577_7 */ #( .INIT(32'b00000000000000000000001000000000)) - N577_3 ( + N577_7 ( .Z (N577), .I0 (cnt[0]), .I1 (cnt[1]), @@ -344377,8 +343792,8 @@ module icmp_rx GTP_LUT3 /* N578_1 */ #( .INIT(8'b00000010)) N578_1 ( - .Z (_N96999), - .I0 (_N96556), + .Z (_N97775), + .I0 (_N97327), .I1 (gmii_rxd_data[0]), .I2 (gmii_rxd_data[4])); // LUT = I0&~I1&~I2 ; @@ -344387,16 +343802,28 @@ module icmp_rx .INIT(32'b00000000000000000000000000001000)) N578_7 ( .Z (N578), - .I0 (_N96556), + .I0 (_N97327), .I1 (gmii_rxd_data[0]), .I2 (gmii_rxd_data[1]), .I3 (gmii_rxd_data[3]), .I4 (gmii_rxd_data[4])); // LUT = I0&I1&~I2&~I3&~I4 ; - GTP_LUT5 /* N579_4 */ #( + GTP_LUT5M /* N579_1 */ #( + .INIT(32'b00000001000000011010101010101011)) + N579_1 ( + .Z (_N96834), + .I0 (cur_state_reg[1]), + .I1 (cur_state_reg[3]), + .I2 (cur_state_reg[2]), + .I3 (cur_state_reg[4]), + .I4 (skip_en), + .ID (error_en)); + // LUT = (~I1&~I2&~I3&~I4)|(ID&~I4)|(~I0&~I1&~I2&I4) ; + + GTP_LUT5 /* N579_7 */ #( .INIT(32'b00000000000010000000000000000000)) - N579_4 ( + N579_7 ( .Z (N579), .I0 (cnt[0]), .I1 (cnt[1]), @@ -344418,7 +343845,7 @@ module icmp_rx GTP_LUT5M /* N603_4 */ #( .INIT(32'b00000100000001000000000100000000)) N603_4 ( - .Z (_N108064), + .Z (_N108899), .I0 (cur_state_reg[1]), .I1 (cur_state_reg[3]), .I2 (cur_state_reg[2]), @@ -344430,7 +343857,7 @@ module icmp_rx GTP_LUT4 /* N619_6 */ #( .INIT(16'b0000000000000001)) N619_6 ( - .Z (_N107540), + .Z (_N108372), .I0 (icmp_type[0]), .I1 (icmp_type[1]), .I2 (icmp_type[2]), @@ -344441,7 +343868,7 @@ module icmp_rx .INIT(32'b00000000000000000000000000001000)) N619_8 ( .Z (N619), - .I0 (_N107540), + .I0 (_N108372), .I1 (icmp_type[3]), .I2 (icmp_type[5]), .I3 (icmp_type[6]), @@ -344451,7 +343878,7 @@ module icmp_rx GTP_LUT4 /* N620_2 */ #( .INIT(16'b0000000011100100)) N620_2 ( - .Z (_N107657), + .Z (_N108489), .I0 (skip_en), .I1 (cur_state_reg[5]), .I2 (cur_state_reg[4]), @@ -344463,8 +343890,8 @@ module icmp_rx N621_3 ( .Z (N621), .I0 (cur_state_reg[4]), - .I1 (_N96007), - .I2 (_N95975), + .I1 (_N96834), + .I2 (_N96787), .I3 (next_state[6]), .I4 (skip_en), .ID (cur_state_reg[5])); @@ -344474,8 +343901,8 @@ module icmp_rx .INIT(32'b00000000100000000000000000000000)) N795_2 ( .Z (N795), - .I0 (_N95922), - .I1 (_N96007), + .I0 (_N96654), + .I1 (_N96834), .I2 (gmii_rxd_valid), .I3 (next_state[0]), .I4 (next_state[1])); @@ -344492,16 +343919,6 @@ module icmp_rx .I4 (N801)); // LUT = (I2)|(I3)|(I4)|(I0&I1) ; - GTP_LUT3 /* N806_5 */ #( - .INIT(8'b00001000)) - N806_5 ( - .Z (_N18475), - .I0 (gmii_rxd_valid), - .I1 (N518), - .I2 (N1304)); - // LUT = I0&I1&~I2 ; - // ../../sources/designs/udp_osd/eth_udp/icmp/icmp_rx.v:166 - GTP_LUT3 /* \N806_12_or[0]_1 */ #( .INIT(8'b00001110)) \N806_12_or[0]_1 ( @@ -344536,7 +343953,7 @@ module icmp_rx .INIT(32'b01000100010101001000100010101000)) \N806_12_or[3]_1 ( .Z (N806[3]), - .I0 (_N5391), + .I0 (_N5465), .I1 (_N18479), .I2 (N801), .I3 (N1261), @@ -344547,57 +343964,66 @@ module icmp_rx .INIT(32'b01010100111111001010100000000000)) \N806_12_or[4]_1 ( .Z (N806[4]), - .I0 (_N5391), + .I0 (_N5465), .I1 (_N18479), .I2 (N801), .I3 (cnt[3]), .I4 (cnt[4])); // LUT = (I1&~I3&I4)|(I2&~I3&I4)|(~I0&I1&I4)|(~I0&I2&I4)|(I0&I1&I3&~I4)|(I0&I2&I3&~I4) ; - GTP_LUT5 /* N806_14_3 */ #( - .INIT(32'b11101111111011101100111111001100)) + GTP_LUT5 /* N806_14_2 */ #( + .INIT(32'b00110011000000001011001110100000)) + N806_14_2 ( + .Z (_N108360), + .I0 (gmii_rxd_valid), + .I1 (N516), + .I2 (N518), + .I3 (N795), + .I4 (N1304)); + // LUT = (~I1&I3)|(I0&I2&~I4) ; + + GTP_LUT5M /* N806_14_3 */ #( + .INIT(32'b11111100111110001111110011111000)) N806_14_3 ( .Z (_N18479), - .I0 (_N18470), - .I1 (_N18475), - .I2 (N516), - .I3 (N795), - .I4 (N799)); - // LUT = (I1)|(~I2&I3)|(I0&I4) ; + .I0 (N578), + .I1 (N799), + .I2 (_N108360), + .I3 (N1309), + .I4 (N577), + .ID (_N103649_2)); + // LUT = (ID&I1&~I4)|(I0&I1&I4)|(I1&I3)|(I2) ; - GTP_LUT5M /* N817_1 */ #( - .INIT(32'b00000000000001000000000000000100)) + GTP_LUT2 /* N817_1 */ #( + .INIT(4'b1000)) N817_1 ( - .Z (_N96385), - .I0 (\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg [3] ), - .I1 (_N95844), - .I2 (\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/next_state [2] ), - .I3 (\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/next_state [3] ), - .I4 (\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/skip_en ), - .ID (\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg [4] )); - // LUT = (~ID&I1&~I2&~I3&~I4)|(~I0&I1&~I2&~I3&I4) ; + .Z (N799), + .I0 (gmii_rxd_valid), + .I1 (N571)); + // LUT = I0&I1 ; GTP_LUT5 /* N817_3 */ #( .INIT(32'b00000000100000001000000010000000)) N817_3 ( .Z (N817), - .I0 (_N95925), + .I0 (_N96657), .I1 (gmii_rxd_valid), .I2 (N518), .I3 (cnt[1]), .I4 (cnt[2])); // LUT = (I0&I1&I2&~I4)|(I0&I1&I2&~I3) ; - GTP_LUT4 /* N838 */ #( - .INIT(16'b0000000010000000)) + GTP_LUT5 /* N838 */ #( + .INIT(32'b00000000000000000000100000000000)) N838_vname ( .Z (N838), - .I0 (_N96085), + .I0 (_N96657), .I1 (N799), - .I2 (cnt[1]), - .I3 (cnt[2])); + .I2 (cnt[0]), + .I3 (cnt[1]), + .I4 (cnt[2])); // defparam N838_vname.orig_name = N838; - // LUT = I0&I1&I2&~I3 ; + // LUT = I0&I1&~I2&I3&~I4 ; GTP_LUT3 /* N892_3 */ #( .INIT(8'b11100000)) @@ -344612,80 +344038,96 @@ module icmp_rx .INIT(32'b00000000000000000000000010000000)) N905_vname ( .Z (N905), - .I0 (_N96085), + .I0 (_N97338), .I1 (gmii_rxd_valid), .I2 (N571), - .I3 (cnt[1]), - .I4 (cnt[2])); + .I3 (cnt[0]), + .I4 (cnt[1])); // defparam N905_vname.orig_name = N905; // LUT = I0&I1&I2&~I3&~I4 ; // ../../sources/designs/udp_osd/eth_udp/icmp/icmp_rx.v:166 - GTP_LUT4 /* N943 */ #( - .INIT(16'b0000100000000000)) + GTP_LUT5 /* N943 */ #( + .INIT(32'b00000000000010000000000000000000)) N943_vname ( .Z (N943), - .I0 (_N96085), + .I0 (_N96657), .I1 (N801), - .I2 (cnt[1]), - .I3 (cnt[2])); + .I2 (cnt[0]), + .I3 (cnt[1]), + .I4 (cnt[2])); // defparam N943_vname.orig_name = N943; - // LUT = I0&I1&~I2&I3 ; + // LUT = I0&I1&~I2&~I3&I4 ; + + GTP_LUT5 /* N943_1 */ #( + .INIT(32'b00000000000000001000000000000000)) + N943_1 ( + .Z (N963), + .I0 (_N96787), + .I1 (_N96834), + .I2 (gmii_rxd_valid), + .I3 (next_state[5]), + .I4 (next_state[6])); + // LUT = I0&I1&I2&I3&~I4 ; GTP_LUT5 /* N956 */ #( .INIT(32'b10000000000000000000000000000000)) N956_vname ( .Z (N956), - .I0 (_N95922), - .I1 (_N95975), + .I0 (_N96654), + .I1 (_N96787), .I2 (gmii_rxd_valid), - .I3 (_N108064), - .I4 (N573)); + .I3 (N573), + .I4 (_N108899)); // defparam N956_vname.orig_name = N956; // LUT = I0&I1&I2&I3&I4 ; // ../../sources/designs/udp_osd/eth_udp/icmp/icmp_rx.v:166 - GTP_LUT4 /* N1014 */ #( - .INIT(16'b1000000000000000)) + GTP_LUT5 /* N1014 */ #( + .INIT(32'b00001000000000000000000000000000)) N1014_vname ( .Z (N1014), - .I0 (_N96085), + .I0 (_N96657), .I1 (N801), - .I2 (cnt[1]), - .I3 (cnt[2])); + .I2 (cnt[0]), + .I3 (cnt[1]), + .I4 (cnt[2])); // defparam N1014_vname.orig_name = N1014; - // LUT = I0&I1&I2&I3 ; + // LUT = I0&I1&~I2&I3&I4 ; - GTP_LUT5 /* N1014_1 */ #( - .INIT(32'b00000000000000000010111000111111)) - N1014_1 ( - .Z (_N95975), - .I0 (error_en), - .I1 (skip_en), - .I2 (cur_state_reg[6]), - .I3 (cur_state_reg[1]), - .I4 (cur_state_reg[0])); - // LUT = (~I1&~I3&~I4)|(I1&~I2&~I4)|(I0&~I1&~I4) ; + GTP_LUT5M /* N1014_2 */ #( + .INIT(32'b01010000000000000000010000000000)) + N1014_2 ( + .Z (_N108894), + .I0 (cur_state_reg[2]), + .I1 (cur_state_reg[4]), + .I2 (cur_state_reg[3]), + .I3 (gmii_rxd_valid), + .I4 (skip_en), + .ID (error_en)); + // LUT = (~ID&I1&~I2&I3&~I4)|(~I0&I2&I3&I4) ; + + GTP_LUT4 /* N1014_3 */ #( + .INIT(16'b0000100000000000)) + N1014_3 ( + .Z (N801), + .I0 (_N96654), + .I1 (_N96787), + .I2 (next_state[2]), + .I3 (_N108894)); + // LUT = I0&I1&~I2&I3 ; GTP_LUT5 /* N1057_3 */ #( .INIT(32'b00000000100000000000000000000000)) N1057_3 ( .Z (N1057), - .I0 (_N95925), + .I0 (_N96657), .I1 (N801), .I2 (cnt[0]), .I3 (cnt[1]), .I4 (cnt[2])); // LUT = I0&I1&I2&~I3&I4 ; - GTP_LUT2 /* N1079_1 */ #( - .INIT(4'b1000)) - N1079_1 ( - .Z (N799), - .I0 (gmii_rxd_valid), - .I1 (N571)); - // LUT = I0&I1 ; - GTP_LUT3 /* N1082 */ #( .INIT(8'b11100000)) N1082_vname ( @@ -344708,14 +344150,6 @@ module icmp_rx // LUT = ~I0&I1&~I2 ; // ../../sources/designs/udp_osd/eth_udp/icmp/icmp_rx.v:166 - GTP_LUT2 /* N1123_3 */ #( - .INIT(4'b1000)) - N1123_3 ( - .Z (_N96072), - .I0 (\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt [1] ), - .I1 (\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt [2] )); - // LUT = I0&I1 ; - GTP_LUT5 /* N1127_3 */ #( .INIT(32'b11111111111000001111111110100000)) N1127_3 ( @@ -345068,22 +344502,23 @@ module icmp_rx // LUT = ~I0&~I1 ; // ../../sources/designs/udp_osd/eth_udp/icmp/icmp_rx.v:133 - GTP_LUT4 /* N1170 */ #( - .INIT(16'b0000100000000000)) + GTP_LUT5 /* N1170 */ #( + .INIT(32'b00000000000010000000000000000000)) N1170_vname ( .Z (N1170), - .I0 (_N96085), + .I0 (_N96657), .I1 (N799), - .I2 (cnt[1]), - .I3 (cnt[2])); + .I2 (cnt[0]), + .I3 (cnt[1]), + .I4 (cnt[2])); // defparam N1170_vname.orig_name = N1170; - // LUT = I0&I1&~I2&I3 ; + // LUT = I0&I1&~I2&~I3&I4 ; GTP_LUT4 /* N1213_3 */ #( .INIT(16'b0000000010000000)) N1213_3 ( .Z (N1213), - .I0 (_N96780), + .I0 (_N97554), .I1 (gmii_rxd_valid), .I2 (N518), .I3 (cnt[0])); @@ -345101,11 +344536,24 @@ module icmp_rx // defparam N1261_vname.orig_name = N1261; // LUT = I0&I1&I2&~I3&~I4 ; + GTP_LUT5 /* N1265 */ #( + .INIT(32'b10000000000000000000000000000000)) + N1265_vname ( + .Z (N1265), + .I0 (_N96657), + .I1 (gmii_rxd_valid), + .I2 (cnt[0]), + .I3 (cnt[1]), + .I4 (cnt[2])); + // defparam N1265_vname.orig_name = N1265; + // LUT = I0&I1&I2&I3&I4 ; + // ../../sources/designs/udp_osd/eth_udp/icmp/icmp_rx.v:255 + GTP_LUT5 /* N1294 */ #( .INIT(32'b00000000000000001000000000000000)) N1294_vname ( .Z (N1294), - .I0 (_N95925), + .I0 (_N96657), .I1 (N799), .I2 (cnt[0]), .I3 (cnt[1]), @@ -345136,17 +344584,6 @@ module icmp_rx .I4 (cnt[4])); // LUT = (I1&~I2&~I3&~I4)|(~I0&~I1&~I3&~I4) ; - GTP_LUT5 /* N1326_3 */ #( - .INIT(32'b00000000000001110000001000011101)) - N1326_3 ( - .Z (N1326), - .I0 (cnt[0]), - .I1 (cnt[1]), - .I2 (cnt[2]), - .I3 (cnt[3]), - .I4 (cnt[4])); - // LUT = (~I0&~I2&~I3)|(I1&~I2&~I3&~I4)|(~I0&~I1&~I3&~I4)|(~I1&~I2&~I3&I4)|(I0&~I1&~I2&I3&~I4) ; - GTP_DFF_CE /* \cnt[0] */ #( .GRS_EN("TRUE"), .INIT(1'b0)) @@ -345266,20 +344703,20 @@ module icmp_rx // LUT = (~I0&I1)|(I0&I2) ; // ../../sources/designs/udp_osd/eth_udp/icmp/icmp_rx.v:87 - GTP_LUT4 /* \cur_state_fsm[6:0]_42 */ #( + GTP_LUT4 /* \cur_state_fsm[6:0]_34 */ #( .INIT(16'b1111111000110010)) - \cur_state_fsm[6:0]_42 ( + \cur_state_fsm[6:0]_34 ( .Z (next_state[6]), - .I0 (_N84201), + .I0 (_N82337), .I1 (skip_en), .I2 (cur_state_reg[6]), .I3 (cur_state_reg[5])); // LUT = (I0&~I1)|(~I1&I2)|(I1&I3) ; - GTP_LUT5 /* \cur_state_fsm[6:0]_46 */ #( + GTP_LUT5 /* \cur_state_fsm[6:0]_38 */ #( .INIT(32'b10101010101010101010101010101000)) - \cur_state_fsm[6:0]_46 ( - .Z (_N84201), + \cur_state_fsm[6:0]_38 ( + .Z (_N82337), .I0 (error_en), .I1 (cur_state_reg[4]), .I2 (cur_state_reg[3]), @@ -346784,7 +346221,7 @@ module icmp_rx .C (sync_vg_100m), .CE (N1082), .CLK (clk), - .D (_N76271)); + .D (_N35473)); // ../../sources/designs/udp_osd/eth_udp/icmp/icmp_rx.v:133 GTP_DFF_CE /* \icmp_rx_data_d0[1] */ #( @@ -346795,7 +346232,7 @@ module icmp_rx .C (sync_vg_100m), .CE (N1082), .CLK (clk), - .D (_N76299)); + .D (_N35501)); // ../../sources/designs/udp_osd/eth_udp/icmp/icmp_rx.v:133 GTP_DFF_CE /* \icmp_rx_data_d0[2] */ #( @@ -346806,7 +346243,7 @@ module icmp_rx .C (sync_vg_100m), .CE (N1082), .CLK (clk), - .D (_N76327)); + .D (_N35529)); // ../../sources/designs/udp_osd/eth_udp/icmp/icmp_rx.v:133 GTP_DFF_CE /* \icmp_rx_data_d0[3] */ #( @@ -346817,7 +346254,7 @@ module icmp_rx .C (sync_vg_100m), .CE (N1082), .CLK (clk), - .D (_N76355)); + .D (_N35557)); // ../../sources/designs/udp_osd/eth_udp/icmp/icmp_rx.v:133 GTP_DFF_CE /* \icmp_rx_data_d0[4] */ #( @@ -346828,7 +346265,7 @@ module icmp_rx .C (sync_vg_100m), .CE (N1082), .CLK (clk), - .D (_N76383)); + .D (_N35585)); // ../../sources/designs/udp_osd/eth_udp/icmp/icmp_rx.v:133 GTP_DFF_CE /* \icmp_rx_data_d0[5] */ #( @@ -346839,7 +346276,7 @@ module icmp_rx .C (sync_vg_100m), .CE (N1082), .CLK (clk), - .D (_N76411)); + .D (_N35613)); // ../../sources/designs/udp_osd/eth_udp/icmp/icmp_rx.v:133 GTP_DFF_CE /* \icmp_rx_data_d0[6] */ #( @@ -346850,69 +346287,69 @@ module icmp_rx .C (sync_vg_100m), .CE (N1082), .CLK (clk), - .D (_N76439)); + .D (_N35641)); // ../../sources/designs/udp_osd/eth_udp/icmp/icmp_rx.v:133 - GTP_LUT2 /* \icmp_rx_data_d0[7:0]_5094 */ #( + GTP_LUT2 /* \icmp_rx_data_d0[7:0]_570 */ #( .INIT(4'b0010)) - \icmp_rx_data_d0[7:0]_5094 ( - .Z (_N76271), + \icmp_rx_data_d0[7:0]_570 ( + .Z (_N35473), .I0 (gmii_rxd_data[0]), .I1 (N361)); // LUT = I0&~I1 ; - GTP_LUT2 /* \icmp_rx_data_d0[7:0]_5106 */ #( + GTP_LUT2 /* \icmp_rx_data_d0[7:0]_582 */ #( .INIT(4'b0010)) - \icmp_rx_data_d0[7:0]_5106 ( - .Z (_N76299), + \icmp_rx_data_d0[7:0]_582 ( + .Z (_N35501), .I0 (gmii_rxd_data[1]), .I1 (N361)); // LUT = I0&~I1 ; - GTP_LUT2 /* \icmp_rx_data_d0[7:0]_5118 */ #( + GTP_LUT2 /* \icmp_rx_data_d0[7:0]_594 */ #( .INIT(4'b0010)) - \icmp_rx_data_d0[7:0]_5118 ( - .Z (_N76327), + \icmp_rx_data_d0[7:0]_594 ( + .Z (_N35529), .I0 (gmii_rxd_data[2]), .I1 (N361)); // LUT = I0&~I1 ; - GTP_LUT2 /* \icmp_rx_data_d0[7:0]_5130 */ #( + GTP_LUT2 /* \icmp_rx_data_d0[7:0]_606 */ #( .INIT(4'b0010)) - \icmp_rx_data_d0[7:0]_5130 ( - .Z (_N76355), + \icmp_rx_data_d0[7:0]_606 ( + .Z (_N35557), .I0 (gmii_rxd_data[3]), .I1 (N361)); // LUT = I0&~I1 ; - GTP_LUT2 /* \icmp_rx_data_d0[7:0]_5142 */ #( + GTP_LUT2 /* \icmp_rx_data_d0[7:0]_618 */ #( .INIT(4'b0010)) - \icmp_rx_data_d0[7:0]_5142 ( - .Z (_N76383), + \icmp_rx_data_d0[7:0]_618 ( + .Z (_N35585), .I0 (gmii_rxd_data[4]), .I1 (N361)); // LUT = I0&~I1 ; - GTP_LUT2 /* \icmp_rx_data_d0[7:0]_5154 */ #( + GTP_LUT2 /* \icmp_rx_data_d0[7:0]_630 */ #( .INIT(4'b0010)) - \icmp_rx_data_d0[7:0]_5154 ( - .Z (_N76411), + \icmp_rx_data_d0[7:0]_630 ( + .Z (_N35613), .I0 (gmii_rxd_data[5]), .I1 (N361)); // LUT = I0&~I1 ; - GTP_LUT2 /* \icmp_rx_data_d0[7:0]_5166 */ #( + GTP_LUT2 /* \icmp_rx_data_d0[7:0]_642 */ #( .INIT(4'b0010)) - \icmp_rx_data_d0[7:0]_5166 ( - .Z (_N76439), + \icmp_rx_data_d0[7:0]_642 ( + .Z (_N35641), .I0 (gmii_rxd_data[6]), .I1 (N361)); // LUT = I0&~I1 ; - GTP_LUT2 /* \icmp_rx_data_d0[7:0]_5178 */ #( + GTP_LUT2 /* \icmp_rx_data_d0[7:0]_654 */ #( .INIT(4'b0010)) - \icmp_rx_data_d0[7:0]_5178 ( - .Z (_N76467), + \icmp_rx_data_d0[7:0]_654 ( + .Z (_N35669), .I0 (gmii_rxd_data[7]), .I1 (N361)); // LUT = I0&~I1 ; @@ -346925,7 +346362,7 @@ module icmp_rx .C (sync_vg_100m), .CE (N1082), .CLK (clk), - .D (_N76467)); + .D (_N35669)); // ../../sources/designs/udp_osd/eth_udp/icmp/icmp_rx.v:133 GTP_DFF_CE /* \icmp_seq[0] */ #( @@ -347514,14 +346951,14 @@ module icmp_rx .Q (rec_en), .C (sync_vg_100m), .CLK (clk), - .D (_N103308)); + .D (_N104120)); // defparam rec_en_vname.orig_name = rec_en; // ../../sources/designs/udp_osd/eth_udp/icmp/icmp_rx.v:133 GTP_LUT3 /* rec_en_ce_mux */ #( .INIT(8'b00110010)) rec_en_ce_mux ( - .Z (_N103308), + .Z (_N104120), .I0 (rec_en), .I1 (N621), .I2 (N963)); @@ -348454,15 +347891,13 @@ module icmp_tx input [15:0] \udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt , input N543_inv, input N592_inv, - input N973, - input _N95913, - input _N95955, - input _N95958, - input _N96003, - input _N96067, - input _N97022, - input _N97048, - input _N97050, + input _N96703, + input _N96734, + input _N96861, + input _N97125, + input _N97265, + input _N97827, + input _N97829, input clk, input sync_vg_100m, input tx_start_en, @@ -348470,9 +347905,8 @@ module icmp_tx input \udp_osd_inst/eth_udp_inst/u_eth_ctrl/icmp_tx_req_d0 , output [7:0] cur_state_reg, output [7:0] gmii_txd_data, - output N969, - output _N106910, - output _N106911, + output _N107734, + output _N107735, output crc_en, output gmii_txd_valid, output skip_en, @@ -348525,6 +347959,8 @@ module icmp_tx wire N958; wire N961; wire [31:0] N964; + wire N969; + wire N973; wire N980; wire [1:0] N983; wire N1036; @@ -348561,12 +347997,8 @@ module icmp_tx wire [17:0] N3894; wire [18:0] N3897; wire [31:0] N3909; - wire _N10425; - wire _N10498; - wire _N15296; - wire _N15297; - wire _N15298; - wire _N15299; + wire _N10439; + wire _N10512; wire _N15300; wire _N15301; wire _N15302; @@ -348575,34 +348007,48 @@ module icmp_tx wire _N15305; wire _N15306; wire _N15307; + wire _N15308; + wire _N15309; wire _N15310; wire _N15311; - wire _N15312; - wire _N15313; - wire _N15314; - wire _N15315; - wire _N15316; - wire _N15317; - wire _N15318; - wire _N15319; - wire _N15320; - wire _N15321; - wire _N15322; - wire _N15323; - wire _N15517; - wire _N15518; - wire _N15519; - wire _N15520; - wire _N15521; - wire _N15522; - wire _N15523; - wire _N15524; - wire _N15525; - wire _N15526; - wire _N15527; - wire _N15528; - wire _N15529; - wire _N15530; + wire _N15328; + wire _N15329; + wire _N15330; + wire _N15331; + wire _N15332; + wire _N15333; + wire _N15334; + wire _N15335; + wire _N15336; + wire _N15337; + wire _N15338; + wire _N15339; + wire _N15340; + wire _N15341; + wire _N15368; + wire _N15369; + wire _N15370; + wire _N15371; + wire _N15372; + wire _N15373; + wire _N15374; + wire _N15375; + wire _N15376; + wire _N15377; + wire _N15378; + wire _N15379; + wire _N15380; + wire _N15381; + wire _N15485; + wire _N15486; + wire _N15487; + wire _N15488; + wire _N15489; + wire _N15490; + wire _N15491; + wire _N15571; + wire _N15572; + wire _N15573; wire _N15574; wire _N15575; wire _N15576; @@ -348610,36 +348056,83 @@ module icmp_tx wire _N15578; wire _N15579; wire _N15580; - wire _N16032; - wire _N16033; - wire _N16034; - wire _N16035; - wire _N16036; - wire _N16037; - wire _N16038; - wire _N16039; - wire _N16040; - wire _N16041; - wire _N16042; - wire _N16043; - wire _N16044; - wire _N16045; - wire _N16046; - wire _N16138; - wire _N16139; - wire _N16140; - wire _N16141; - wire _N16142; - wire _N16143; - wire _N16144; - wire _N16145; - wire _N16146; - wire _N16147; - wire _N16148; - wire _N16149; - wire _N16150; - wire _N16151; - wire _N16152; + wire _N15581; + wire _N15582; + wire _N15583; + wire _N15584; + wire _N15585; + wire _N16017; + wire _N16018; + wire _N16019; + wire _N16020; + wire _N16021; + wire _N16022; + wire _N16023; + wire _N16024; + wire _N16025; + wire _N16026; + wire _N16027; + wire _N16028; + wire _N16029; + wire _N16030; + wire _N16031; + wire _N16761; + wire _N16762; + wire _N16763; + wire _N16764; + wire _N16765; + wire _N16766; + wire _N16767; + wire _N16768; + wire _N16769; + wire _N16770; + wire _N16771; + wire _N16772; + wire _N16773; + wire _N16774; + wire _N16775; + wire _N16776; + wire _N16777; + wire _N16778; + wire _N16779; + wire _N16780; + wire _N16781; + wire _N16782; + wire _N16783; + wire _N16784; + wire _N16785; + wire _N16786; + wire _N16787; + wire _N16788; + wire _N16789; + wire _N16790; + wire _N16791; + wire _N16794; + wire _N16795; + wire _N16796; + wire _N16797; + wire _N16798; + wire _N16799; + wire _N16800; + wire _N16801; + wire _N16802; + wire _N16803; + wire _N16804; + wire _N16805; + wire _N16806; + wire _N16807; + wire _N16808; + wire _N16811; + wire _N16812; + wire _N16813; + wire _N16814; + wire _N16815; + wire _N16816; + wire _N16817; + wire _N16818; + wire _N16819; + wire _N16820; + wire _N16821; wire _N16822; wire _N16823; wire _N16824; @@ -348648,8 +348141,6 @@ module icmp_tx wire _N16827; wire _N16828; wire _N16829; - wire _N16830; - wire _N16831; wire _N16832; wire _N16833; wire _N16834; @@ -348671,6 +348162,8 @@ module icmp_tx wire _N16850; wire _N16851; wire _N16852; + wire _N16853; + wire _N16854; wire _N16855; wire _N16856; wire _N16857; @@ -348679,13 +348172,13 @@ module icmp_tx wire _N16860; wire _N16861; wire _N16862; - wire _N16863; - wire _N16864; wire _N16865; wire _N16866; wire _N16867; wire _N16868; wire _N16869; + wire _N16870; + wire _N16871; wire _N16872; wire _N16873; wire _N16874; @@ -348695,8 +348188,6 @@ module icmp_tx wire _N16878; wire _N16879; wire _N16880; - wire _N16881; - wire _N16882; wire _N16883; wire _N16884; wire _N16885; @@ -348705,6 +348196,8 @@ module icmp_tx wire _N16888; wire _N16889; wire _N16890; + wire _N16891; + wire _N16892; wire _N16893; wire _N16894; wire _N16895; @@ -348712,17 +348205,6 @@ module icmp_tx wire _N16897; wire _N16898; wire _N16899; - wire _N16900; - wire _N16901; - wire _N16902; - wire _N16903; - wire _N16904; - wire _N16905; - wire _N16906; - wire _N16907; - wire _N16908; - wire _N16909; - wire _N16910; wire _N16911; wire _N16912; wire _N16913; @@ -348736,76 +348218,30 @@ module icmp_tx wire _N16921; wire _N16922; wire _N16923; + wire _N16924; + wire _N16925; wire _N16926; wire _N16927; wire _N16928; - wire _N16929; - wire _N16930; - wire _N16931; - wire _N16932; - wire _N16933; - wire _N16934; - wire _N16935; - wire _N16936; - wire _N16937; - wire _N16938; - wire _N16939; - wire _N16940; - wire _N16941; - wire _N16944; - wire _N16945; - wire _N16946; - wire _N16947; - wire _N16948; - wire _N16949; - wire _N16950; - wire _N16951; - wire _N16952; - wire _N16953; - wire _N16954; - wire _N16955; - wire _N16956; - wire _N16957; - wire _N16958; - wire _N16959; - wire _N16960; - wire _N16963; - wire _N16964; - wire _N16965; - wire _N16966; - wire _N16967; - wire _N16968; - wire _N16969; - wire _N16970; - wire _N16971; - wire _N16972; - wire _N16973; - wire _N16974; - wire _N16975; - wire _N16976; - wire _N16977; - wire _N16978; - wire _N16979; - wire _N16980; wire _N18495; - wire _N25971; - wire _N25975; - wire _N25976; - wire _N25985; - wire _N25986; - wire _N25988; - wire _N25989; - wire _N25990; - wire _N26001; - wire _N26002; - wire _N26004; + wire _N25935; + wire _N25939; + wire _N25940; + wire _N25949; + wire _N25950; + wire _N25952; + wire _N25953; + wire _N25954; + wire _N25965; + wire _N25966; + wire _N25968; + wire _N25969; + wire _N25970; wire _N26005; wire _N26006; - wire _N26041; - wire _N26042; - wire _N26044; - wire _N26045; - wire _N26046; + wire _N26008; + wire _N26009; + wire _N26010; wire _N26327; wire _N26342; wire _N26389; @@ -348867,45 +348303,46 @@ module icmp_tx wire _N26745; wire _N26746; wire _N26747; - wire _N81128; - wire _N81156; - wire _N81172; - wire _N81188; - wire _N81204; - wire _N81220; - wire _N81236; - wire _N81252; - wire _N81268; - wire _N81284; - wire _N81300; - wire _N81316; - wire _N81332; - wire _N81348; - wire _N81364; - wire _N81380; - wire _N84470; - wire _N95792; - wire _N95801; - wire _N96019; - wire _N96367; - wire _N96573; - wire _N96731; - wire _N102344_2; - wire _N102547_2; - wire _N102854_2; - wire _N103305; - wire _N106906; - wire _N106909; - wire _N107683; - wire _N107685; - wire _N107696; - wire _N107698; - wire _N107862; - wire _N108072; - wire _N108075; - wire _N108076; - wire _N108095; - wire _N108106; + wire _N81901; + wire _N81929; + wire _N81945; + wire _N81961; + wire _N81977; + wire _N81993; + wire _N82009; + wire _N82025; + wire _N82041; + wire _N82057; + wire _N82073; + wire _N82089; + wire _N82105; + wire _N82121; + wire _N82137; + wire _N82153; + wire _N85270; + wire _N96572; + wire _N96582; + wire _N97305; + wire _N97455; + wire _N97509; + wire _N97586; + wire _N97693; + wire _N103457_2; + wire _N103555_2; + wire _N103556_2; + wire _N104117; + wire _N107730; + wire _N107733; + wire _N108515; + wire _N108517; + wire _N108528; + wire _N108530; + wire _N108694; + wire _N108907; + wire _N108910; + wire _N108911; + wire _N108930; + wire _N108941; wire [31:0] check_buffer; wire [31:0] check_buffer_icmp; wire [4:0] cnt; @@ -348951,7 +348388,7 @@ module icmp_tx GTP_LUT4 /* N3_mux3 */ #( .INIT(16'b0000000111111111)) N3_mux3 ( - .Z (_N10425), + .Z (_N10439), .I0 (total_num[1]), .I1 (tx_data_num[2]), .I2 (tx_data_num[3]), @@ -348961,7 +348398,7 @@ module icmp_tx GTP_LUT4 /* N3_mux14_9 */ #( .INIT(16'b0000000000000001)) N3_mux14_9 ( - .Z (_N107696), + .Z (_N108528), .I0 (tx_data_num[11]), .I1 (tx_data_num[12]), .I2 (tx_data_num[13]), @@ -348971,23 +348408,23 @@ module icmp_tx GTP_LUT5 /* N3_mux14_11 */ #( .INIT(32'b00000000000000010000000000000000)) N3_mux14_11 ( - .Z (_N107698), + .Z (_N108530), .I0 (tx_data_num[7]), .I1 (tx_data_num[8]), .I2 (tx_data_num[9]), .I3 (tx_data_num[10]), - .I4 (_N107696)); + .I4 (_N108528)); // LUT = ~I0&~I1&~I2&~I3&I4 ; GTP_LUT5 /* N3_mux14_12 */ #( .INIT(32'b00000000000000100000000000000000)) N3_mux14_12 ( .Z (N3), - .I0 (_N10425), + .I0 (_N10439), .I1 (tx_data_num[5]), .I2 (tx_data_num[6]), .I3 (tx_data_num[15]), - .I4 (_N107698)); + .I4 (_N108530)); // LUT = I0&~I1&~I2&~I3&I4 ; GTP_LUT2 /* \N5_0[0] */ #( @@ -349152,7 +348589,7 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N19_1_1 ( - .COUT (_N15296), + .COUT (_N15300), .Z (N19[3]), .CIN (), .I0 (tx_byte_num[2]), @@ -349172,9 +348609,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N19_1_2 ( - .COUT (_N15297), + .COUT (_N15301), .Z (N19[4]), - .CIN (_N15296), + .CIN (_N15300), .I0 (tx_byte_num[2]), .I1 (tx_byte_num[3]), .I2 (tx_byte_num[4]), @@ -349192,9 +348629,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N19_1_3 ( - .COUT (_N15298), + .COUT (_N15302), .Z (N19[5]), - .CIN (_N15297), + .CIN (_N15301), .I0 (), .I1 (tx_byte_num[5]), .I2 (), @@ -349212,9 +348649,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N19_1_4 ( - .COUT (_N15299), + .COUT (_N15303), .Z (N19[6]), - .CIN (_N15298), + .CIN (_N15302), .I0 (), .I1 (tx_byte_num[6]), .I2 (), @@ -349232,9 +348669,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N19_1_5 ( - .COUT (_N15300), + .COUT (_N15304), .Z (N19[7]), - .CIN (_N15299), + .CIN (_N15303), .I0 (), .I1 (tx_byte_num[7]), .I2 (), @@ -349252,9 +348689,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N19_1_6 ( - .COUT (_N15301), + .COUT (_N15305), .Z (N19[8]), - .CIN (_N15300), + .CIN (_N15304), .I0 (), .I1 (tx_byte_num[8]), .I2 (), @@ -349272,9 +348709,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N19_1_7 ( - .COUT (_N15302), + .COUT (_N15306), .Z (N19[9]), - .CIN (_N15301), + .CIN (_N15305), .I0 (), .I1 (tx_byte_num[9]), .I2 (), @@ -349292,9 +348729,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N19_1_8 ( - .COUT (_N15303), + .COUT (_N15307), .Z (N19[10]), - .CIN (_N15302), + .CIN (_N15306), .I0 (), .I1 (tx_byte_num[10]), .I2 (), @@ -349312,9 +348749,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N19_1_9 ( - .COUT (_N15304), + .COUT (_N15308), .Z (N19[11]), - .CIN (_N15303), + .CIN (_N15307), .I0 (), .I1 (tx_byte_num[11]), .I2 (), @@ -349332,9 +348769,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N19_1_10 ( - .COUT (_N15305), + .COUT (_N15309), .Z (N19[12]), - .CIN (_N15304), + .CIN (_N15308), .I0 (), .I1 (tx_byte_num[12]), .I2 (), @@ -349352,9 +348789,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N19_1_11 ( - .COUT (_N15306), + .COUT (_N15310), .Z (N19[13]), - .CIN (_N15305), + .CIN (_N15309), .I0 (), .I1 (tx_byte_num[13]), .I2 (), @@ -349372,9 +348809,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N19_1_12 ( - .COUT (_N15307), + .COUT (_N15311), .Z (N19[14]), - .CIN (_N15306), + .CIN (_N15310), .I0 (), .I1 (tx_byte_num[14]), .I2 (), @@ -349394,7 +348831,7 @@ module icmp_tx N19_1_13 ( .COUT (), .Z (N19[15]), - .CIN (_N15307), + .CIN (_N15311), .I0 (), .I1 (tx_byte_num[15]), .I2 (), @@ -349412,7 +348849,7 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N130_1_1 ( - .COUT (_N15310), + .COUT (_N15328), .Z (N130[1]), .CIN (), .I0 (\ip_head[1] [16] ), @@ -349432,9 +348869,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N130_1_2 ( - .COUT (_N15311), + .COUT (_N15329), .Z (N130[2]), - .CIN (_N15310), + .CIN (_N15328), .I0 (\ip_head[1] [16] ), .I1 (\ip_head[1] [17] ), .I2 (\ip_head[1] [18] ), @@ -349452,9 +348889,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N130_1_3 ( - .COUT (_N15312), + .COUT (_N15330), .Z (N130[3]), - .CIN (_N15311), + .CIN (_N15329), .I0 (), .I1 (\ip_head[1] [19] ), .I2 (), @@ -349472,9 +348909,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N130_1_4 ( - .COUT (_N15313), + .COUT (_N15331), .Z (N130[4]), - .CIN (_N15312), + .CIN (_N15330), .I0 (), .I1 (\ip_head[1] [20] ), .I2 (), @@ -349492,9 +348929,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N130_1_5 ( - .COUT (_N15314), + .COUT (_N15332), .Z (N130[5]), - .CIN (_N15313), + .CIN (_N15331), .I0 (), .I1 (\ip_head[1] [21] ), .I2 (), @@ -349512,9 +348949,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N130_1_6 ( - .COUT (_N15315), + .COUT (_N15333), .Z (N130[6]), - .CIN (_N15314), + .CIN (_N15332), .I0 (), .I1 (\ip_head[1] [22] ), .I2 (), @@ -349532,9 +348969,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N130_1_7 ( - .COUT (_N15316), + .COUT (_N15334), .Z (N130[7]), - .CIN (_N15315), + .CIN (_N15333), .I0 (), .I1 (\ip_head[1] [23] ), .I2 (), @@ -349552,9 +348989,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N130_1_8 ( - .COUT (_N15317), + .COUT (_N15335), .Z (N130[8]), - .CIN (_N15316), + .CIN (_N15334), .I0 (), .I1 (\ip_head[1] [24] ), .I2 (), @@ -349572,9 +349009,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N130_1_9 ( - .COUT (_N15318), + .COUT (_N15336), .Z (N130[9]), - .CIN (_N15317), + .CIN (_N15335), .I0 (), .I1 (\ip_head[1] [25] ), .I2 (), @@ -349592,9 +349029,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N130_1_10 ( - .COUT (_N15319), + .COUT (_N15337), .Z (N130[10]), - .CIN (_N15318), + .CIN (_N15336), .I0 (), .I1 (\ip_head[1] [26] ), .I2 (), @@ -349612,9 +349049,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N130_1_11 ( - .COUT (_N15320), + .COUT (_N15338), .Z (N130[11]), - .CIN (_N15319), + .CIN (_N15337), .I0 (), .I1 (\ip_head[1] [27] ), .I2 (), @@ -349632,9 +349069,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N130_1_12 ( - .COUT (_N15321), + .COUT (_N15339), .Z (N130[12]), - .CIN (_N15320), + .CIN (_N15338), .I0 (), .I1 (\ip_head[1] [28] ), .I2 (), @@ -349652,9 +349089,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N130_1_13 ( - .COUT (_N15322), + .COUT (_N15340), .Z (N130[13]), - .CIN (_N15321), + .CIN (_N15339), .I0 (), .I1 (\ip_head[1] [29] ), .I2 (), @@ -349672,9 +349109,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N130_1_14 ( - .COUT (_N15323), + .COUT (_N15341), .Z (N130[14]), - .CIN (_N15322), + .CIN (_N15340), .I0 (), .I1 (\ip_head[1] [30] ), .I2 (), @@ -349694,7 +349131,7 @@ module icmp_tx N130_1_15 ( .COUT (), .Z (N130[15]), - .CIN (_N15323), + .CIN (_N15341), .I0 (), .I1 (\ip_head[1] [31] ), .I2 (), @@ -349850,7 +349287,7 @@ module icmp_tx GTP_LUT3 /* \N267_6[2] */ #( .INIT(8'b11100100)) \N267_6[2] ( - .Z (_N25971), + .Z (_N25935), .I0 (cnt[0]), .I1 (\eth_head[2] [2] ), .I2 (\eth_head[3] [2] )); @@ -349859,7 +349296,7 @@ module icmp_tx GTP_LUT3 /* \N267_6[6] */ #( .INIT(8'b11100100)) \N267_6[6] ( - .Z (_N25975), + .Z (_N25939), .I0 (cnt[0]), .I1 (\eth_head[2] [6] ), .I2 (\eth_head[3] [6] )); @@ -349868,7 +349305,7 @@ module icmp_tx GTP_LUT3 /* \N267_6[7] */ #( .INIT(8'b11100100)) \N267_6[7] ( - .Z (_N25976), + .Z (_N25940), .I0 (cnt[0]), .I1 (\eth_head[2] [7] ), .I2 (\eth_head[3] [7] )); @@ -349877,7 +349314,7 @@ module icmp_tx GTP_LUT5 /* \N267_8[0] */ #( .INIT(32'b10101011101010101010100110101000)) \N267_8[0] ( - .Z (_N25985), + .Z (_N25949), .I0 (cnt[0]), .I1 (cnt[2]), .I2 (cnt[3]), @@ -349888,7 +349325,7 @@ module icmp_tx GTP_LUT5 /* \N267_8[1] */ #( .INIT(32'b00000011000000100000000100000000)) \N267_8[1] ( - .Z (_N25986), + .Z (_N25950), .I0 (cnt[0]), .I1 (cnt[2]), .I2 (cnt[3]), @@ -349899,7 +349336,7 @@ module icmp_tx GTP_LUT5 /* \N267_8[3] */ #( .INIT(32'b00000011000000100000000100000000)) \N267_8[3] ( - .Z (_N25988), + .Z (_N25952), .I0 (cnt[0]), .I1 (cnt[2]), .I2 (cnt[3]), @@ -349907,10 +349344,19 @@ module icmp_tx .I4 (\eth_head[3] [3] )); // LUT = (~I0&~I1&~I2&I3)|(I0&~I1&~I2&I4) ; + GTP_LUT3 /* \N267_8[3]_1 */ #( + .INIT(8'b00000001)) + \N267_8[3]_1 ( + .Z (_N97305), + .I0 (cnt[1]), + .I1 (cnt[3]), + .I2 (cnt[4])); + // LUT = ~I0&~I1&~I2 ; + GTP_LUT5 /* \N267_8[4] */ #( .INIT(32'b10101011101010101010100110101000)) \N267_8[4] ( - .Z (_N25989), + .Z (_N25953), .I0 (cnt[0]), .I1 (cnt[2]), .I2 (cnt[3]), @@ -349921,7 +349367,7 @@ module icmp_tx GTP_LUT5 /* \N267_8[5] */ #( .INIT(32'b00000011000000100000000100000000)) \N267_8[5] ( - .Z (_N25990), + .Z (_N25954), .I0 (cnt[0]), .I1 (cnt[2]), .I2 (cnt[3]), @@ -349932,7 +349378,7 @@ module icmp_tx GTP_LUT3 /* \N267_10[0] */ #( .INIT(8'b11100100)) \N267_10[0] ( - .Z (_N26001), + .Z (_N25965), .I0 (cnt[0]), .I1 (\eth_head[4] [0] ), .I2 (\eth_head[5] [0] )); @@ -349941,7 +349387,7 @@ module icmp_tx GTP_LUT3 /* \N267_10[1] */ #( .INIT(8'b11100100)) \N267_10[1] ( - .Z (_N26002), + .Z (_N25966), .I0 (cnt[0]), .I1 (\eth_head[4] [1] ), .I2 (\eth_head[5] [1] )); @@ -349950,7 +349396,7 @@ module icmp_tx GTP_LUT3 /* \N267_10[3] */ #( .INIT(8'b11100100)) \N267_10[3] ( - .Z (_N26004), + .Z (_N25968), .I0 (cnt[0]), .I1 (\eth_head[4] [3] ), .I2 (\eth_head[5] [3] )); @@ -349959,7 +349405,7 @@ module icmp_tx GTP_LUT3 /* \N267_10[4] */ #( .INIT(8'b11100100)) \N267_10[4] ( - .Z (_N26005), + .Z (_N25969), .I0 (cnt[0]), .I1 (\eth_head[4] [4] ), .I2 (\eth_head[5] [4] )); @@ -349968,7 +349414,7 @@ module icmp_tx GTP_LUT3 /* \N267_10[5] */ #( .INIT(8'b11100100)) \N267_10[5] ( - .Z (_N26006), + .Z (_N25970), .I0 (cnt[0]), .I1 (\eth_head[4] [5] ), .I2 (\eth_head[5] [5] )); @@ -349977,8 +349423,8 @@ module icmp_tx GTP_LUT5M /* \N267_15[0] */ #( .INIT(32'b00100010001000101011101010011000)) \N267_15[0] ( - .Z (_N26041), - .I0 (_N26001), + .Z (_N26005), + .I0 (_N25965), .I1 (cnt[3]), .I2 (\eth_head[0] [0] ), .I3 (\eth_head[1] [0] ), @@ -349989,8 +349435,8 @@ module icmp_tx GTP_LUT5M /* \N267_15[1] */ #( .INIT(32'b00100010001000101111111011011100)) \N267_15[1] ( - .Z (_N26042), - .I0 (_N26002), + .Z (_N26006), + .I0 (_N25966), .I1 (cnt[3]), .I2 (\eth_head[0] [1] ), .I3 (\eth_head[1] [1] ), @@ -350001,7 +349447,7 @@ module icmp_tx GTP_LUT5M /* \N267_15[2]_2 */ #( .INIT(32'b11101110001000101110001011100010)) \N267_15[2]_2 ( - .Z (_N102344_2), + .Z (_N103457_2), .I0 (\eth_head[1] [2] ), .I1 (cnt[2]), .I2 (\eth_head[4] [2] ), @@ -350013,8 +349459,8 @@ module icmp_tx GTP_LUT5M /* \N267_15[3] */ #( .INIT(32'b00101110001011100011001000000010)) \N267_15[3] ( - .Z (_N26044), - .I0 (_N26004), + .Z (_N26008), + .I0 (_N25968), .I1 (cnt[3]), .I2 (cnt[0]), .I3 (\eth_head[1] [3] ), @@ -350025,8 +349471,8 @@ module icmp_tx GTP_LUT5M /* \N267_15[4] */ #( .INIT(32'b00100010001000101011101010011000)) \N267_15[4] ( - .Z (_N26045), - .I0 (_N26005), + .Z (_N26009), + .I0 (_N25969), .I1 (cnt[3]), .I2 (\eth_head[0] [4] ), .I3 (\eth_head[1] [4] ), @@ -350037,8 +349483,8 @@ module icmp_tx GTP_LUT5M /* \N267_15[5] */ #( .INIT(32'b00100010001000101111111011011100)) \N267_15[5] ( - .Z (_N26046), - .I0 (_N26006), + .Z (_N26010), + .I0 (_N25970), .I1 (cnt[3]), .I2 (\eth_head[0] [5] ), .I3 (\eth_head[1] [5] ), @@ -350049,7 +349495,7 @@ module icmp_tx GTP_LUT5M /* \N267_15[6]_2 */ #( .INIT(32'b11101110001000101110001011100010)) \N267_15[6]_2 ( - .Z (_N102547_2), + .Z (_N103555_2), .I0 (\eth_head[1] [6] ), .I1 (cnt[2]), .I2 (\eth_head[4] [6] ), @@ -350061,7 +349507,7 @@ module icmp_tx GTP_LUT5M /* \N267_15[7]_2 */ #( .INIT(32'b11101110001000101110001011100010)) \N267_15[7]_2 ( - .Z (_N102854_2), + .Z (_N103556_2), .I0 (\eth_head[1] [7] ), .I1 (cnt[2]), .I2 (\eth_head[4] [7] ), @@ -350072,22 +349518,22 @@ module icmp_tx GTP_MUX2LUT6 \N267_16[0] ( .Z (N267[0]), - .I0 (_N26041), - .I1 (_N25985), + .I0 (_N26005), + .I1 (_N25949), .S (cnt[1])); GTP_MUX2LUT6 \N267_16[1] ( .Z (N267[1]), - .I0 (_N26042), - .I1 (_N25986), + .I0 (_N26006), + .I1 (_N25950), .S (cnt[1])); GTP_LUT5 /* \N267_16[2] */ #( .INIT(32'b00000000111100000000110010101100)) \N267_16[2] ( .Z (N267[2]), - .I0 (_N25971), - .I1 (_N102344_2), + .I0 (_N25935), + .I1 (_N103457_2), .I2 (cnt[1]), .I3 (cnt[2]), .I4 (cnt[3])); @@ -350095,28 +349541,28 @@ module icmp_tx GTP_MUX2LUT6 \N267_16[3] ( .Z (N267[3]), - .I0 (_N26044), - .I1 (_N25988), + .I0 (_N26008), + .I1 (_N25952), .S (cnt[1])); GTP_MUX2LUT6 \N267_16[4] ( .Z (N267[4]), - .I0 (_N26045), - .I1 (_N25989), + .I0 (_N26009), + .I1 (_N25953), .S (cnt[1])); GTP_MUX2LUT6 \N267_16[5] ( .Z (N267[5]), - .I0 (_N26046), - .I1 (_N25990), + .I0 (_N26010), + .I1 (_N25954), .S (cnt[1])); GTP_LUT5 /* \N267_16[6] */ #( .INIT(32'b00000000111100000000110010101100)) \N267_16[6] ( .Z (N267[6]), - .I0 (_N25975), - .I1 (_N102547_2), + .I0 (_N25939), + .I1 (_N103555_2), .I2 (cnt[1]), .I3 (cnt[2]), .I4 (cnt[3])); @@ -350126,8 +349572,8 @@ module icmp_tx .INIT(32'b00000000000000000000110010101100)) \N267_16[7] ( .Z (N267[7]), - .I0 (_N25976), - .I1 (_N102854_2), + .I0 (_N25940), + .I1 (_N103556_2), .I2 (cnt[1]), .I3 (cnt[2]), .I4 (cnt[3])); @@ -350160,7 +349606,7 @@ module icmp_tx \N282_48[0] ( .Z (_N26389), .I0 (_N26342), - .I1 (_N96019), + .I1 (_N97586), .I2 (\ip_head[0] [0] ), .I3 (\ip_head[2] [0] ), .I4 (\ip_head[5] [0] )); @@ -350171,7 +349617,7 @@ module icmp_tx \N282_48[1] ( .Z (_N26390), .I0 (_N26342), - .I1 (_N96019), + .I1 (_N97586), .I2 (\ip_head[0] [1] ), .I3 (\ip_head[2] [1] ), .I4 (\ip_head[5] [1] )); @@ -350182,7 +349628,7 @@ module icmp_tx \N282_48[2] ( .Z (_N26391), .I0 (_N26342), - .I1 (_N96019), + .I1 (_N97586), .I2 (\ip_head[0] [2] ), .I3 (\ip_head[2] [2] ), .I4 (\ip_head[5] [2] )); @@ -350193,7 +349639,7 @@ module icmp_tx \N282_48[3] ( .Z (_N26392), .I0 (_N26342), - .I1 (_N96019), + .I1 (_N97586), .I2 (\ip_head[0] [3] ), .I3 (\ip_head[2] [3] ), .I4 (\ip_head[5] [3] )); @@ -350204,7 +349650,7 @@ module icmp_tx \N282_48[4] ( .Z (_N26393), .I0 (_N26342), - .I1 (_N96019), + .I1 (_N97586), .I2 (\ip_head[0] [4] ), .I3 (\ip_head[2] [4] ), .I4 (\ip_head[5] [4] )); @@ -350215,7 +349661,7 @@ module icmp_tx \N282_48[5] ( .Z (_N26394), .I0 (_N26342), - .I1 (_N96019), + .I1 (_N97586), .I2 (\ip_head[0] [5] ), .I3 (\ip_head[2] [5] ), .I4 (\ip_head[5] [5] )); @@ -350226,7 +349672,7 @@ module icmp_tx \N282_48[6] ( .Z (_N26395), .I0 (_N26342), - .I1 (_N96019), + .I1 (_N97586), .I2 (\ip_head[0] [6] ), .I3 (\ip_head[2] [6] ), .I4 (\ip_head[5] [6] )); @@ -350237,7 +349683,7 @@ module icmp_tx \N282_48[7] ( .Z (_N26396), .I0 (_N26342), - .I1 (_N96019), + .I1 (_N97586), .I2 (\ip_head[0] [7] ), .I3 (\ip_head[2] [7] ), .I4 (\ip_head[5] [7] )); @@ -350248,7 +349694,7 @@ module icmp_tx \N282_48[8] ( .Z (_N26397), .I0 (_N26342), - .I1 (_N96019), + .I1 (_N97586), .I2 (\ip_head[0] [8] ), .I3 (\ip_head[2] [8] ), .I4 (\ip_head[5] [8] )); @@ -350259,7 +349705,7 @@ module icmp_tx \N282_48[9] ( .Z (_N26398), .I0 (_N26342), - .I1 (_N96019), + .I1 (_N97586), .I2 (\ip_head[0] [9] ), .I3 (\ip_head[2] [9] ), .I4 (\ip_head[5] [9] )); @@ -350270,7 +349716,7 @@ module icmp_tx \N282_48[10] ( .Z (_N26399), .I0 (_N26342), - .I1 (_N96019), + .I1 (_N97586), .I2 (\ip_head[0] [10] ), .I3 (\ip_head[2] [10] ), .I4 (\ip_head[5] [10] )); @@ -350281,7 +349727,7 @@ module icmp_tx \N282_48[11] ( .Z (_N26400), .I0 (_N26342), - .I1 (_N96019), + .I1 (_N97586), .I2 (\ip_head[0] [11] ), .I3 (\ip_head[2] [11] ), .I4 (\ip_head[5] [11] )); @@ -350292,7 +349738,7 @@ module icmp_tx \N282_48[12] ( .Z (_N26401), .I0 (_N26342), - .I1 (_N96019), + .I1 (_N97586), .I2 (\ip_head[0] [12] ), .I3 (\ip_head[2] [12] ), .I4 (\ip_head[5] [12] )); @@ -350303,7 +349749,7 @@ module icmp_tx \N282_48[13] ( .Z (_N26402), .I0 (_N26342), - .I1 (_N96019), + .I1 (_N97586), .I2 (\ip_head[0] [13] ), .I3 (\ip_head[2] [13] ), .I4 (\ip_head[5] [13] )); @@ -350314,7 +349760,7 @@ module icmp_tx \N282_48[14] ( .Z (_N26403), .I0 (_N26342), - .I1 (_N96019), + .I1 (_N97586), .I2 (\ip_head[0] [14] ), .I3 (\ip_head[2] [14] ), .I4 (\ip_head[5] [14] )); @@ -350325,7 +349771,7 @@ module icmp_tx \N282_48[15] ( .Z (_N26404), .I0 (_N26342), - .I1 (_N96019), + .I1 (_N97586), .I2 (\ip_head[0] [15] ), .I3 (\ip_head[2] [15] ), .I4 (\ip_head[5] [15] )); @@ -350336,7 +349782,7 @@ module icmp_tx \N282_52[0] ( .Z (N282[0]), .I0 (_N26389), - .I1 (_N96019), + .I1 (_N97586), .I2 (\ip_head[4] [0] ), .I3 (\ip_head[6] [0] ), .I4 (_N26327), @@ -350348,7 +349794,7 @@ module icmp_tx \N282_52[1] ( .Z (N282[1]), .I0 (_N26390), - .I1 (_N96019), + .I1 (_N97586), .I2 (\ip_head[4] [1] ), .I3 (\ip_head[6] [1] ), .I4 (_N26327), @@ -350360,7 +349806,7 @@ module icmp_tx \N282_52[2] ( .Z (N282[2]), .I0 (_N26391), - .I1 (_N96019), + .I1 (_N97586), .I2 (\ip_head[4] [2] ), .I3 (\ip_head[6] [2] ), .I4 (_N26327), @@ -350372,7 +349818,7 @@ module icmp_tx \N282_52[3] ( .Z (N282[3]), .I0 (_N26392), - .I1 (_N96019), + .I1 (_N97586), .I2 (\ip_head[4] [3] ), .I3 (\ip_head[6] [3] ), .I4 (_N26327), @@ -350384,7 +349830,7 @@ module icmp_tx \N282_52[4] ( .Z (N282[4]), .I0 (_N26393), - .I1 (_N96019), + .I1 (_N97586), .I2 (\ip_head[4] [4] ), .I3 (\ip_head[6] [4] ), .I4 (_N26327), @@ -350396,7 +349842,7 @@ module icmp_tx \N282_52[5] ( .Z (N282[5]), .I0 (_N26394), - .I1 (_N96019), + .I1 (_N97586), .I2 (\ip_head[4] [5] ), .I3 (\ip_head[6] [5] ), .I4 (_N26327), @@ -350408,7 +349854,7 @@ module icmp_tx \N282_52[6] ( .Z (N282[6]), .I0 (_N26395), - .I1 (_N96019), + .I1 (_N97586), .I2 (\ip_head[4] [6] ), .I3 (\ip_head[6] [6] ), .I4 (_N26327), @@ -350420,7 +349866,7 @@ module icmp_tx \N282_52[7] ( .Z (N282[7]), .I0 (_N26396), - .I1 (_N96019), + .I1 (_N97586), .I2 (\ip_head[4] [7] ), .I3 (\ip_head[6] [7] ), .I4 (_N26327), @@ -350432,7 +349878,7 @@ module icmp_tx \N282_52[8] ( .Z (N282[8]), .I0 (_N26397), - .I1 (_N96019), + .I1 (_N97586), .I2 (\ip_head[4] [8] ), .I3 (\ip_head[6] [8] ), .I4 (_N26327), @@ -350444,7 +349890,7 @@ module icmp_tx \N282_52[9] ( .Z (N282[9]), .I0 (_N26398), - .I1 (_N96019), + .I1 (_N97586), .I2 (\ip_head[4] [9] ), .I3 (\ip_head[6] [9] ), .I4 (_N26327), @@ -350456,7 +349902,7 @@ module icmp_tx \N282_52[10] ( .Z (N282[10]), .I0 (_N26399), - .I1 (_N96019), + .I1 (_N97586), .I2 (\ip_head[4] [10] ), .I3 (\ip_head[6] [10] ), .I4 (_N26327), @@ -350468,7 +349914,7 @@ module icmp_tx \N282_52[11] ( .Z (N282[11]), .I0 (_N26400), - .I1 (_N96019), + .I1 (_N97586), .I2 (\ip_head[4] [11] ), .I3 (\ip_head[6] [11] ), .I4 (_N26327), @@ -350480,7 +349926,7 @@ module icmp_tx \N282_52[12] ( .Z (N282[12]), .I0 (_N26401), - .I1 (_N96019), + .I1 (_N97586), .I2 (\ip_head[4] [12] ), .I3 (\ip_head[6] [12] ), .I4 (_N26327), @@ -350492,7 +349938,7 @@ module icmp_tx \N282_52[13] ( .Z (N282[13]), .I0 (_N26402), - .I1 (_N96019), + .I1 (_N97586), .I2 (\ip_head[4] [13] ), .I3 (\ip_head[6] [13] ), .I4 (_N26327), @@ -350504,7 +349950,7 @@ module icmp_tx \N282_52[14] ( .Z (N282[14]), .I0 (_N26403), - .I1 (_N96019), + .I1 (_N97586), .I2 (\ip_head[4] [14] ), .I3 (\ip_head[6] [14] ), .I4 (_N26327), @@ -350516,7 +349962,7 @@ module icmp_tx \N282_52[15] ( .Z (N282[15]), .I0 (_N26404), - .I1 (_N96019), + .I1 (_N97586), .I2 (\ip_head[4] [15] ), .I3 (\ip_head[6] [15] ), .I4 (_N26327), @@ -350528,7 +349974,7 @@ module icmp_tx \N282_52[16] ( .Z (N282[16]), .I0 (\ip_head[1] [16] ), - .I1 (_N96019), + .I1 (_N97586), .I2 (_N26327), .I3 (\ip_head[6] [16] ), .I4 (_N26342), @@ -350540,7 +349986,7 @@ module icmp_tx \N282_52[17] ( .Z (N282[17]), .I0 (\ip_head[1] [17] ), - .I1 (_N96019), + .I1 (_N97586), .I2 (_N26327), .I3 (\ip_head[6] [17] ), .I4 (_N26342), @@ -350552,7 +349998,7 @@ module icmp_tx \N282_52[18] ( .Z (N282[18]), .I0 (\ip_head[1] [18] ), - .I1 (_N96019), + .I1 (_N97586), .I2 (_N26327), .I3 (\ip_head[6] [18] ), .I4 (_N26342), @@ -350564,7 +350010,7 @@ module icmp_tx \N282_52[19] ( .Z (N282[19]), .I0 (\ip_head[1] [19] ), - .I1 (_N96019), + .I1 (_N97586), .I2 (_N26327), .I3 (\ip_head[6] [19] ), .I4 (_N26342), @@ -350576,7 +350022,7 @@ module icmp_tx \N282_52[20] ( .Z (N282[20]), .I0 (\ip_head[1] [20] ), - .I1 (_N96019), + .I1 (_N97586), .I2 (_N26327), .I3 (\ip_head[6] [20] ), .I4 (_N26342), @@ -350588,7 +350034,7 @@ module icmp_tx \N282_52[21] ( .Z (N282[21]), .I0 (\ip_head[1] [21] ), - .I1 (_N96019), + .I1 (_N97586), .I2 (_N26327), .I3 (\ip_head[6] [21] ), .I4 (_N26342), @@ -350600,7 +350046,7 @@ module icmp_tx \N282_52[22] ( .Z (N282[22]), .I0 (\ip_head[1] [22] ), - .I1 (_N96019), + .I1 (_N97586), .I2 (_N26327), .I3 (\ip_head[6] [22] ), .I4 (_N26342), @@ -350612,7 +350058,7 @@ module icmp_tx \N282_52[23] ( .Z (N282[23]), .I0 (\ip_head[1] [23] ), - .I1 (_N96019), + .I1 (_N97586), .I2 (_N26327), .I3 (\ip_head[6] [23] ), .I4 (_N26342), @@ -350624,7 +350070,7 @@ module icmp_tx \N282_52[24] ( .Z (N282[24]), .I0 (\ip_head[1] [24] ), - .I1 (_N96019), + .I1 (_N97586), .I2 (_N26327), .I3 (\ip_head[6] [24] ), .I4 (_N26342), @@ -350636,7 +350082,7 @@ module icmp_tx \N282_52[25] ( .Z (N282[25]), .I0 (\ip_head[1] [25] ), - .I1 (_N96019), + .I1 (_N97586), .I2 (_N26327), .I3 (\ip_head[6] [25] ), .I4 (_N26342), @@ -350648,7 +350094,7 @@ module icmp_tx \N282_52[26] ( .Z (N282[26]), .I0 (\ip_head[1] [26] ), - .I1 (_N96019), + .I1 (_N97586), .I2 (_N26327), .I3 (\ip_head[6] [26] ), .I4 (_N26342), @@ -350660,7 +350106,7 @@ module icmp_tx \N282_52[27] ( .Z (N282[27]), .I0 (\ip_head[1] [27] ), - .I1 (_N96019), + .I1 (_N97586), .I2 (_N26327), .I3 (\ip_head[6] [27] ), .I4 (_N26342), @@ -350672,7 +350118,7 @@ module icmp_tx \N282_52[28] ( .Z (N282[28]), .I0 (\ip_head[1] [28] ), - .I1 (_N96019), + .I1 (_N97586), .I2 (_N26327), .I3 (\ip_head[6] [28] ), .I4 (_N26342), @@ -350684,7 +350130,7 @@ module icmp_tx \N282_52[29] ( .Z (N282[29]), .I0 (\ip_head[1] [29] ), - .I1 (_N96019), + .I1 (_N97586), .I2 (_N26327), .I3 (\ip_head[6] [29] ), .I4 (_N26342), @@ -350696,7 +350142,7 @@ module icmp_tx \N282_52[30] ( .Z (N282[30]), .I0 (\ip_head[1] [30] ), - .I1 (_N96019), + .I1 (_N97586), .I2 (_N26327), .I3 (\ip_head[6] [30] ), .I4 (_N26342), @@ -350708,7 +350154,7 @@ module icmp_tx \N282_52[31] ( .Z (N282[31]), .I0 (\ip_head[1] [31] ), - .I1 (_N96019), + .I1 (_N97586), .I2 (_N26327), .I3 (\ip_head[6] [31] ), .I4 (_N26342), @@ -350726,10 +350172,10 @@ module icmp_tx .I4 (cnt[4])); // LUT = (I0&~I1&~I2&~I3&~I4)|(~I0&I1&~I2&~I3&~I4) ; - GTP_LUT5 /* N282_56 */ #( + GTP_LUT5 /* N282_55 */ #( .INIT(32'b00000000000000000000000001110000)) - N282_56 ( - .Z (_N96019), + N282_55 ( + .Z (_N97586), .I0 (cnt[0]), .I1 (cnt[1]), .I2 (cnt[2]), @@ -351204,8 +350650,8 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N337_1_1 ( - .COUT (_N15517), - .Z (_N81156), + .COUT (_N15368), + .Z (_N81929), .CIN (), .I0 (data_cnt[0]), .I1 (data_cnt[1]), @@ -351224,9 +350670,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N337_1_2 ( - .COUT (_N15518), - .Z (_N81172), - .CIN (_N15517), + .COUT (_N15369), + .Z (_N81945), + .CIN (_N15368), .I0 (data_cnt[0]), .I1 (data_cnt[1]), .I2 (N329), @@ -351244,9 +350690,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N337_1_3 ( - .COUT (_N15519), - .Z (_N81188), - .CIN (_N15518), + .COUT (_N15370), + .Z (_N81961), + .CIN (_N15369), .I0 (), .I1 (data_cnt[3]), .I2 (N329), @@ -351264,9 +350710,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N337_1_4 ( - .COUT (_N15520), - .Z (_N81204), - .CIN (_N15519), + .COUT (_N15371), + .Z (_N81977), + .CIN (_N15370), .I0 (), .I1 (data_cnt[4]), .I2 (N329), @@ -351284,9 +350730,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N337_1_5 ( - .COUT (_N15521), - .Z (_N81220), - .CIN (_N15520), + .COUT (_N15372), + .Z (_N81993), + .CIN (_N15371), .I0 (), .I1 (data_cnt[5]), .I2 (N329), @@ -351304,9 +350750,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N337_1_6 ( - .COUT (_N15522), - .Z (_N81236), - .CIN (_N15521), + .COUT (_N15373), + .Z (_N82009), + .CIN (_N15372), .I0 (), .I1 (data_cnt[6]), .I2 (N329), @@ -351324,9 +350770,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N337_1_7 ( - .COUT (_N15523), - .Z (_N81252), - .CIN (_N15522), + .COUT (_N15374), + .Z (_N82025), + .CIN (_N15373), .I0 (), .I1 (data_cnt[7]), .I2 (N329), @@ -351344,9 +350790,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N337_1_8 ( - .COUT (_N15524), - .Z (_N81268), - .CIN (_N15523), + .COUT (_N15375), + .Z (_N82041), + .CIN (_N15374), .I0 (), .I1 (data_cnt[8]), .I2 (N329), @@ -351364,9 +350810,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N337_1_9 ( - .COUT (_N15525), - .Z (_N81284), - .CIN (_N15524), + .COUT (_N15376), + .Z (_N82057), + .CIN (_N15375), .I0 (), .I1 (data_cnt[9]), .I2 (N329), @@ -351384,9 +350830,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N337_1_10 ( - .COUT (_N15526), - .Z (_N81300), - .CIN (_N15525), + .COUT (_N15377), + .Z (_N82073), + .CIN (_N15376), .I0 (), .I1 (data_cnt[10]), .I2 (N329), @@ -351404,9 +350850,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N337_1_11 ( - .COUT (_N15527), - .Z (_N81316), - .CIN (_N15526), + .COUT (_N15378), + .Z (_N82089), + .CIN (_N15377), .I0 (), .I1 (data_cnt[11]), .I2 (N329), @@ -351424,9 +350870,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N337_1_12 ( - .COUT (_N15528), - .Z (_N81332), - .CIN (_N15527), + .COUT (_N15379), + .Z (_N82105), + .CIN (_N15378), .I0 (), .I1 (data_cnt[12]), .I2 (N329), @@ -351444,9 +350890,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N337_1_13 ( - .COUT (_N15529), - .Z (_N81348), - .CIN (_N15528), + .COUT (_N15380), + .Z (_N82121), + .CIN (_N15379), .I0 (), .I1 (data_cnt[13]), .I2 (N329), @@ -351464,9 +350910,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N337_1_14 ( - .COUT (_N15530), - .Z (_N81364), - .CIN (_N15529), + .COUT (_N15381), + .Z (_N82137), + .CIN (_N15380), .I0 (), .I1 (data_cnt[14]), .I2 (N329), @@ -351485,8 +350931,8 @@ module icmp_tx .I4_TO_LUT("FALSE")) N337_1_15 ( .COUT (), - .Z (_N81380), - .CIN (_N15530), + .Z (_N82153), + .CIN (_N15381), .I0 (), .I1 (data_cnt[15]), .I2 (N329), @@ -351664,7 +351110,7 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N346_1 ( - .COUT (_N16855), + .COUT (_N16794), .Z (N346[0]), .CIN (), .I0 (real_add_cnt[0]), @@ -351684,9 +351130,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N346_2 ( - .COUT (_N16856), + .COUT (_N16795), .Z (N346[1]), - .CIN (_N16855), + .CIN (_N16794), .I0 (real_add_cnt[0]), .I1 (data_cnt[0]), .I2 (real_add_cnt[1]), @@ -351704,9 +351150,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N346_3 ( - .COUT (_N16857), + .COUT (_N16796), .Z (N346[2]), - .CIN (_N16856), + .CIN (_N16795), .I0 (), .I1 (real_add_cnt[2]), .I2 (data_cnt[2]), @@ -351724,9 +351170,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N346_4 ( - .COUT (_N16858), + .COUT (_N16797), .Z (N346[3]), - .CIN (_N16857), + .CIN (_N16796), .I0 (), .I1 (real_add_cnt[3]), .I2 (data_cnt[3]), @@ -351744,9 +351190,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N346_5 ( - .COUT (_N16859), + .COUT (_N16798), .Z (N346[4]), - .CIN (_N16858), + .CIN (_N16797), .I0 (), .I1 (real_add_cnt[4]), .I2 (data_cnt[4]), @@ -351764,9 +351210,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N346_6 ( - .COUT (_N16860), + .COUT (_N16799), .Z (N346[5]), - .CIN (_N16859), + .CIN (_N16798), .I0 (), .I1 (data_cnt[5]), .I2 (), @@ -351784,9 +351230,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N346_7 ( - .COUT (_N16861), + .COUT (_N16800), .Z (N346[6]), - .CIN (_N16860), + .CIN (_N16799), .I0 (), .I1 (data_cnt[6]), .I2 (), @@ -351804,9 +351250,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N346_8 ( - .COUT (_N16862), + .COUT (_N16801), .Z (N346[7]), - .CIN (_N16861), + .CIN (_N16800), .I0 (), .I1 (data_cnt[7]), .I2 (), @@ -351824,9 +351270,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N346_9 ( - .COUT (_N16863), + .COUT (_N16802), .Z (N346[8]), - .CIN (_N16862), + .CIN (_N16801), .I0 (), .I1 (data_cnt[8]), .I2 (), @@ -351844,9 +351290,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N346_10 ( - .COUT (_N16864), + .COUT (_N16803), .Z (N346[9]), - .CIN (_N16863), + .CIN (_N16802), .I0 (), .I1 (data_cnt[9]), .I2 (), @@ -351864,9 +351310,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N346_11 ( - .COUT (_N16865), + .COUT (_N16804), .Z (N346[10]), - .CIN (_N16864), + .CIN (_N16803), .I0 (), .I1 (data_cnt[10]), .I2 (), @@ -351884,9 +351330,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N346_12 ( - .COUT (_N16866), + .COUT (_N16805), .Z (N346[11]), - .CIN (_N16865), + .CIN (_N16804), .I0 (), .I1 (data_cnt[11]), .I2 (), @@ -351904,9 +351350,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N346_13 ( - .COUT (_N16867), + .COUT (_N16806), .Z (N346[12]), - .CIN (_N16866), + .CIN (_N16805), .I0 (), .I1 (data_cnt[12]), .I2 (), @@ -351924,9 +351370,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N346_14 ( - .COUT (_N16868), + .COUT (_N16807), .Z (N346[13]), - .CIN (_N16867), + .CIN (_N16806), .I0 (), .I1 (data_cnt[13]), .I2 (), @@ -351944,9 +351390,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N346_15 ( - .COUT (_N16869), + .COUT (_N16808), .Z (N346[14]), - .CIN (_N16868), + .CIN (_N16807), .I0 (), .I1 (data_cnt[14]), .I2 (), @@ -351966,7 +351412,7 @@ module icmp_tx N346_16 ( .COUT (), .Z (N346[15]), - .CIN (_N16869), + .CIN (_N16808), .I0 (), .I1 (data_cnt[15]), .I2 (), @@ -352140,7 +351586,7 @@ module icmp_tx GTP_LUT3 /* N353_ac2 */ #( .INIT(8'b10000000)) N353_ac2 ( - .Z (_N10498), + .Z (_N10512), .I0 (real_add_cnt[0]), .I1 (real_add_cnt[1]), .I2 (real_add_cnt[2])); @@ -352600,7 +352046,7 @@ module icmp_tx GTP_LUT3 /* N453_1 */ #( .INIT(8'b11111110)) N453_1 ( - .Z (_N95792), + .Z (_N96572), .I0 (N609), .I1 (N611), .I2 (N980)); @@ -352611,16 +352057,24 @@ module icmp_tx .INIT(4'b1000)) N455_7 ( .Z (_N26554), - .I0 (_N97022), + .I0 (_N97693), .I1 (N603)); // LUT = I0&I1 ; + GTP_LUT2 /* N455_10 */ #( + .INIT(4'b0100)) + N455_10 ( + .Z (N973), + .I0 (sync_vg_100m), + .I1 (N969)); + // LUT = ~I0&I1 ; + GTP_LUT5M /* N455_20_4 */ #( .INIT(32'b01000000000000000100000000000000)) N455_20_4 ( .Z (_N26567), .I0 (cur_state_reg[5]), - .I1 (_N95801), + .I1 (_N96582), .I2 (N620), .I3 (N619), .I4 (skip_en), @@ -352631,7 +352085,7 @@ module icmp_tx .INIT(16'b0000000000100000)) N455_22 ( .Z (_N26569), - .I0 (_N95801), + .I0 (_N96582), .I1 (N329), .I2 (N340), .I3 (N349)); @@ -352657,14 +352111,14 @@ module icmp_tx .I1 (next_state[2]), .I2 (_N26554), .I3 (next_state[1]), - .I4 (_N108075), - .ID (_N108076)); + .I4 (_N108910), + .ID (_N108911)); // LUT = (ID&~I1&~I3&~I4)|(I0&~I1&~I3&I4)|(I1&I2&~I3)|(~I1&I2&I3) ; GTP_LUT4 /* N455_32 */ #( .INIT(16'b0000000000011011)) N455_32 ( - .Z (_N95801), + .Z (_N96582), .I0 (skip_en), .I1 (cur_state_reg[0]), .I2 (cur_state_reg[6]), @@ -352674,8 +352128,8 @@ module icmp_tx GTP_LUT5 /* N455_34 */ #( .INIT(32'b00000000000000000000001010001010)) N455_34 ( - .Z (_N96731), - .I0 (_N96003), + .Z (_N97509), + .I0 (_N97265), .I1 (skip_en), .I2 (cur_state_reg[0]), .I3 (cur_state_reg[6]), @@ -352683,7 +352137,7 @@ module icmp_tx // LUT = (I0&I1&~I3&~I4)|(I0&~I1&~I2&~I4) ; GTP_MUX2LUT6 N455_75 ( - .Z (_N108072), + .Z (_N108907), .I0 (_N26572), .I1 (_N26567), .S (next_state[5])); @@ -352691,7 +352145,7 @@ module icmp_tx GTP_LUT5M /* N455_78 */ #( .INIT(32'b00000000000100000000000000000010)) N455_78 ( - .Z (_N108075), + .Z (_N108910), .I0 (cur_state_reg[2]), .I1 (cur_state_reg[4]), .I2 (cur_state_reg[5]), @@ -352703,13 +352157,13 @@ module icmp_tx GTP_LUT5M /* N455_79 */ #( .INIT(32'b00001000000010001100101000001010)) N455_79 ( - .Z (_N108076), + .Z (_N108911), .I0 (N610), - .I1 (_N95955), + .I1 (_N96734), .I2 (next_state[4]), .I3 (N612), .I4 (next_state[3]), - .ID (_N108072)); + .ID (_N108907)); // LUT = (I1&I2&I3&~I4)|(ID&~I2&~I4)|(I0&I1&~I2&I4) ; GTP_LUT5 /* N463 */ #( @@ -352734,10 +352188,10 @@ module icmp_tx // LUT = I0&I1&I2 ; // ../../sources/designs/udp_osd/eth_udp/icmp/icmp_tx.v:234 - GTP_LUT4 /* N594_4 */ #( + GTP_LUT4 /* N594_5 */ #( .INIT(16'b0000100001011000)) - N594_4 ( - .Z (_N107685), + N594_5 ( + .Z (_N108517), .I0 (skip_en), .I1 (cur_state_reg[0]), .I2 (cur_state_reg[1]), @@ -352757,24 +352211,75 @@ module icmp_tx // LUT = I0&I1&~I2&~I3&~I4 ; // ../../sources/designs/udp_osd/eth_udp/icmp/icmp_tx.v:281 - GTP_LUT4 /* N604_4 */ #( + GTP_LUT2 /* N604_9 */ #( + .INIT(4'b0001)) + N604_9 ( + .Z (_N107730), + .I0 (\udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt [14] ), + .I1 (\udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt [15] )); + // LUT = ~I0&~I1 ; + + GTP_LUT4 /* N604_12 */ #( + .INIT(16'b0000000000000001)) + N604_12 ( + .Z (_N107733), + .I0 (\udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt [10] ), + .I1 (\udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt [11] ), + .I2 (\udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt [12] ), + .I3 (\udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt [13] )); + // LUT = ~I0&~I1&~I2&~I3 ; + + GTP_LUT5 /* N604_13 */ #( + .INIT(32'b00000000000000010000000000000000)) + N604_13 ( + .Z (_N107734), + .I0 (\udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt [2] ), + .I1 (\udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt [3] ), + .I2 (\udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt [4] ), + .I3 (\udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt [5] ), + .I4 (_N107730)); + // LUT = ~I0&~I1&~I2&~I3&I4 ; + + GTP_LUT5 /* N604_14 */ #( + .INIT(32'b00000000000000010000000000000000)) + N604_14 ( + .Z (_N107735), + .I0 (\udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt [6] ), + .I1 (\udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt [7] ), + .I2 (\udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt [8] ), + .I3 (\udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt [9] ), + .I4 (_N107733)); + // LUT = ~I0&~I1&~I2&~I3&I4 ; + + GTP_LUT4 /* N604_16 */ #( .INIT(16'b0010010100100000)) - N604_4 ( - .Z (_N107683), + N604_16 ( + .Z (_N108515), .I0 (skip_en), .I1 (cur_state_reg[0]), .I2 (cur_state_reg[1]), .I3 (cur_state_reg[2])); // LUT = (~I0&~I2&I3)|(I0&~I1&I2) ; - GTP_LUT5M /* N609_6 */ #( + GTP_LUT5 /* N609_1 */ #( + .INIT(32'b00000000000010000000000000101010)) + N609_1 ( + .Z (_N97693), + .I0 (_N96734), + .I1 (skip_en), + .I2 (cur_state_reg[2]), + .I3 (cur_state_reg[3]), + .I4 (cur_state_reg[4])); + // LUT = (I0&~I1&~I3&~I4)|(I0&I1&~I2&~I3) ; + + GTP_LUT5M /* N609_5 */ #( .INIT(32'b00001000000000000100000000000000)) - N609_6 ( + N609_5 ( .Z (N609), .I0 (cur_state_reg[2]), - .I1 (_N95955), + .I1 (_N96734), .I2 (cur_state_reg[3]), - .I3 (_N95958), + .I3 (_N97125), .I4 (skip_en), .ID (cur_state_reg[4])); // LUT = (~ID&I1&I2&I3&~I4)|(I0&I1&~I2&I3&I4) ; @@ -352792,70 +352297,21 @@ module icmp_tx // LUT = I0&I1&I2&~I3&~I4 ; // ../../sources/designs/udp_osd/eth_udp/icmp/icmp_tx.v:305 - GTP_LUT2 /* N611_9 */ #( - .INIT(4'b0001)) - N611_9 ( - .Z (_N106906), - .I0 (\udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt [14] ), - .I1 (\udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt [15] )); - // LUT = ~I0&~I1 ; - - GTP_LUT4 /* N611_12 */ #( - .INIT(16'b0000000000000001)) - N611_12 ( - .Z (_N106909), - .I0 (\udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt [10] ), - .I1 (\udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt [11] ), - .I2 (\udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt [12] ), - .I3 (\udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt [13] )); - // LUT = ~I0&~I1&~I2&~I3 ; - - GTP_LUT5 /* N611_13 */ #( - .INIT(32'b00000000000000010000000000000000)) - N611_13 ( - .Z (_N106910), - .I0 (\udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt [2] ), - .I1 (\udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt [3] ), - .I2 (\udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt [4] ), - .I3 (\udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt [5] ), - .I4 (_N106906)); - // LUT = ~I0&~I1&~I2&~I3&I4 ; - - GTP_LUT5 /* N611_14 */ #( - .INIT(32'b00000000000000010000000000000000)) - N611_14 ( - .Z (_N106911), - .I0 (\udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt [6] ), - .I1 (\udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt [7] ), - .I2 (\udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt [8] ), - .I3 (\udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt [9] ), - .I4 (_N106909)); - // LUT = ~I0&~I1&~I2&~I3&I4 ; - - GTP_LUT5M /* N611_17 */ #( + GTP_LUT5M /* N611_5 */ #( .INIT(32'b01000000000000000000100000000000)) - N611_17 ( + N611_5 ( .Z (N611), .I0 (cur_state_reg[2]), - .I1 (_N95955), + .I1 (_N96734), .I2 (cur_state_reg[3]), - .I3 (_N95958), + .I3 (_N97125), .I4 (skip_en), .ID (cur_state_reg[4])); // LUT = (ID&I1&~I2&I3&~I4)|(~I0&I1&I2&I3&I4) ; - GTP_LUT3 /* N612_1 */ #( - .INIT(8'b00000001)) - N612_1 ( - .Z (_N96573), - .I0 (cnt[1]), - .I1 (cnt[3]), - .I2 (cnt[4])); - // LUT = ~I0&~I1&~I2 ; - - GTP_LUT5 /* N612_8 */ #( + GTP_LUT5 /* N612_10 */ #( .INIT(32'b00000000000000000010000000000000)) - N612_8 ( + N612_10 ( .Z (N612), .I0 (cnt[0]), .I1 (cnt[1]), @@ -352868,7 +352324,7 @@ module icmp_tx .INIT(32'b00000000100000000010001010000000)) N613_3 ( .Z (N613), - .I0 (_N96731), + .I0 (_N97509), .I1 (skip_en), .I2 (cur_state_reg[4]), .I3 (cur_state_reg[5]), @@ -352900,7 +352356,7 @@ module icmp_tx .INIT(32'b00001000001000100000100000000000)) N622_3 ( .Z (N622), - .I0 (_N96731), + .I0 (_N97509), .I1 (skip_en), .I2 (cur_state_reg[4]), .I3 (cur_state_reg[5]), @@ -352912,8 +352368,8 @@ module icmp_tx N623_3 ( .Z (N623), .I0 (cur_state_reg[6]), - .I1 (_N96003), - .I2 (_N95913), + .I1 (_N97265), + .I2 (_N96703), .I3 (cur_state_reg[7]), .I4 (skip_en), .ID (cur_state_reg[0])); @@ -352942,17 +352398,6 @@ module icmp_tx .I3 (cnt[0])); // LUT = (I0&~I3)|(I1&~I3)|(I2&~I3) ; - GTP_LUT5 /* \N919_7_or[0]_3 */ #( - .INIT(32'b00001000101000100010101010000000)) - \N919_7_or[0]_3 ( - .Z (N918), - .I0 (_N97022), - .I1 (skip_en), - .I2 (cur_state_reg[0]), - .I3 (cur_state_reg[1]), - .I4 (cur_state_reg[2])); - // LUT = (I0&~I1&I3&~I4)|(I0&~I1&~I3&I4)|(I0&I1&I2&~I3)|(I0&I1&~I2&I3) ; - GTP_LUT5 /* \N919_7_or[1]_1 */ #( .INIT(32'b00000000111111101111111000000000)) \N919_7_or[1]_1 ( @@ -352986,6 +352431,17 @@ module icmp_tx .I4 (N164[3])); // LUT = (I0&I4)|(I3&I4)|(I1&~I2&I4) ; + GTP_LUT5 /* \N919_7_or[3]_4 */ #( + .INIT(32'b00001000101000100010101010000000)) + \N919_7_or[3]_4 ( + .Z (N918), + .I0 (_N97693), + .I1 (skip_en), + .I2 (cur_state_reg[0]), + .I3 (cur_state_reg[1]), + .I4 (cur_state_reg[2])); + // LUT = (I0&~I1&I3&~I4)|(I0&~I1&~I3&I4)|(I0&I1&I2&~I3)|(I0&I1&~I2&I3) ; + GTP_LUT5 /* N919_8 */ #( .INIT(32'b00100010111100100010001000100010)) N919_8 ( @@ -353002,21 +352458,21 @@ module icmp_tx .INIT(32'b00000000000010000000000000000000)) N937_2 ( .Z (N937), - .I0 (_N96573), - .I1 (_N97022), + .I0 (_N97305), + .I1 (_N97693), .I2 (cnt[0]), .I3 (cnt[2]), - .I4 (_N107685)); + .I4 (_N108517)); // LUT = I0&I1&~I2&~I3&I4 ; GTP_LUT4 /* N940 */ #( .INIT(16'b1111100011110000)) N940_vname ( .Z (N940), - .I0 (_N97022), + .I0 (_N97693), .I1 (N933), .I2 (N937), - .I3 (_N107685)); + .I3 (_N108517)); // defparam N940_vname.orig_name = N940; // LUT = (I2)|(I0&I1&I3) ; // ../../sources/designs/udp_osd/eth_udp/icmp/icmp_tx.v:234 @@ -353216,7 +352672,7 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N943_5_1 ( - .COUT (_N16872), + .COUT (_N16811), .Z (N943[0]), .CIN (), .I0 (nb2[0]), @@ -353235,9 +352691,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N943_5_2 ( - .COUT (_N16873), + .COUT (_N16812), .Z (N943[1]), - .CIN (_N16872), + .CIN (_N16811), .I0 (nb2[0]), .I1 (nb3[0]), .I2 (nb2[1]), @@ -353254,9 +352710,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N943_5_3 ( - .COUT (_N16874), + .COUT (_N16813), .Z (N943[2]), - .CIN (_N16873), + .CIN (_N16812), .I0 (), .I1 (nb2[2]), .I2 (nb3[2]), @@ -353273,9 +352729,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N943_5_4 ( - .COUT (_N16875), + .COUT (_N16814), .Z (N943[3]), - .CIN (_N16874), + .CIN (_N16813), .I0 (), .I1 (nb2[3]), .I2 (nb3[3]), @@ -353292,9 +352748,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N943_5_5 ( - .COUT (_N16876), + .COUT (_N16815), .Z (N943[4]), - .CIN (_N16875), + .CIN (_N16814), .I0 (), .I1 (nb2[4]), .I2 (N937), @@ -353311,9 +352767,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N943_5_6 ( - .COUT (_N16877), + .COUT (_N16816), .Z (N943[5]), - .CIN (_N16876), + .CIN (_N16815), .I0 (), .I1 (nb2[5]), .I2 (N937), @@ -353330,9 +352786,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N943_5_7 ( - .COUT (_N16878), + .COUT (_N16817), .Z (N943[6]), - .CIN (_N16877), + .CIN (_N16816), .I0 (), .I1 (nb2[6]), .I2 (N937), @@ -353349,9 +352805,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N943_5_8 ( - .COUT (_N16879), + .COUT (_N16818), .Z (N943[7]), - .CIN (_N16878), + .CIN (_N16817), .I0 (), .I1 (nb2[7]), .I2 (N937), @@ -353368,9 +352824,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N943_5_9 ( - .COUT (_N16880), + .COUT (_N16819), .Z (N943[8]), - .CIN (_N16879), + .CIN (_N16818), .I0 (), .I1 (nb2[8]), .I2 (N937), @@ -353387,9 +352843,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N943_5_10 ( - .COUT (_N16881), + .COUT (_N16820), .Z (N943[9]), - .CIN (_N16880), + .CIN (_N16819), .I0 (), .I1 (nb2[9]), .I2 (N937), @@ -353406,9 +352862,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N943_5_11 ( - .COUT (_N16882), + .COUT (_N16821), .Z (N943[10]), - .CIN (_N16881), + .CIN (_N16820), .I0 (), .I1 (nb2[10]), .I2 (N937), @@ -353425,9 +352881,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N943_5_12 ( - .COUT (_N16883), + .COUT (_N16822), .Z (N943[11]), - .CIN (_N16882), + .CIN (_N16821), .I0 (), .I1 (nb2[11]), .I2 (N937), @@ -353444,9 +352900,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N943_5_13 ( - .COUT (_N16884), + .COUT (_N16823), .Z (N943[12]), - .CIN (_N16883), + .CIN (_N16822), .I0 (), .I1 (nb2[12]), .I2 (N937), @@ -353463,9 +352919,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N943_5_14 ( - .COUT (_N16885), + .COUT (_N16824), .Z (N943[13]), - .CIN (_N16884), + .CIN (_N16823), .I0 (), .I1 (nb2[13]), .I2 (N937), @@ -353482,9 +352938,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N943_5_15 ( - .COUT (_N16886), + .COUT (_N16825), .Z (N943[14]), - .CIN (_N16885), + .CIN (_N16824), .I0 (), .I1 (nb2[14]), .I2 (N937), @@ -353501,9 +352957,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N943_5_16 ( - .COUT (_N16887), + .COUT (_N16826), .Z (N943[15]), - .CIN (_N16886), + .CIN (_N16825), .I0 (), .I1 (nb2[15]), .I2 (N937), @@ -353520,9 +352976,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N943_5_17 ( - .COUT (_N16888), + .COUT (_N16827), .Z (N943[16]), - .CIN (_N16887), + .CIN (_N16826), .I0 (), .I1 (N937), .I2 (nb3[16]), @@ -353539,9 +352995,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N943_5_18 ( - .COUT (_N16889), + .COUT (_N16828), .Z (N943[17]), - .CIN (_N16888), + .CIN (_N16827), .I0 (), .I1 (N937), .I2 (N3897[17]), @@ -353558,9 +353014,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N943_5_19 ( - .COUT (_N16890), + .COUT (_N16829), .Z (N943[18]), - .CIN (_N16889), + .CIN (_N16828), .I0 (), .I1 (N937), .I2 (N3897[18]), @@ -353579,7 +353035,7 @@ module icmp_tx N943_5_20 ( .COUT (), .Z (N943[19]), - .CIN (_N16890), + .CIN (_N16829), .I0 (), .I1 (), .I2 (), @@ -353593,21 +353049,21 @@ module icmp_tx .INIT(32'b00000000000010000000000000000000)) N958_2 ( .Z (N958), - .I0 (_N96573), - .I1 (_N97022), + .I0 (_N97305), + .I1 (_N97693), .I2 (cnt[0]), .I3 (cnt[2]), - .I4 (_N107683)); + .I4 (_N108515)); // LUT = I0&I1&~I2&~I3&I4 ; GTP_LUT4 /* N961 */ #( .INIT(16'b1111100011110000)) N961_vname ( .Z (N961), - .I0 (_N97022), + .I0 (_N97693), .I1 (N933), .I2 (N958), - .I3 (_N107683)); + .I3 (_N108515)); // defparam N961_vname.orig_name = N961; // LUT = (I2)|(I0&I1&I3) ; // ../../sources/designs/udp_osd/eth_udp/icmp/icmp_tx.v:234 @@ -353907,7 +353363,7 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N964_5_1 ( - .COUT (_N16822), + .COUT (_N16761), .Z (N964[0]), .CIN (), .I0 (nb0[0]), @@ -353926,9 +353382,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N964_5_2 ( - .COUT (_N16823), + .COUT (_N16762), .Z (N964[1]), - .CIN (_N16822), + .CIN (_N16761), .I0 (nb0[0]), .I1 (nb1[0]), .I2 (nb0[1]), @@ -353945,9 +353401,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N964_5_3 ( - .COUT (_N16824), + .COUT (_N16763), .Z (N964[2]), - .CIN (_N16823), + .CIN (_N16762), .I0 (), .I1 (nb0[2]), .I2 (nb1[2]), @@ -353964,9 +353420,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N964_5_4 ( - .COUT (_N16825), + .COUT (_N16764), .Z (N964[3]), - .CIN (_N16824), + .CIN (_N16763), .I0 (), .I1 (nb0[3]), .I2 (nb1[3]), @@ -353983,9 +353439,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N964_5_5 ( - .COUT (_N16826), + .COUT (_N16765), .Z (N964[4]), - .CIN (_N16825), + .CIN (_N16764), .I0 (), .I1 (nb0[4]), .I2 (nb1[4]), @@ -354002,9 +353458,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N964_5_6 ( - .COUT (_N16827), + .COUT (_N16766), .Z (N964[5]), - .CIN (_N16826), + .CIN (_N16765), .I0 (), .I1 (nb0[5]), .I2 (nb1[5]), @@ -354021,9 +353477,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N964_5_7 ( - .COUT (_N16828), + .COUT (_N16767), .Z (N964[6]), - .CIN (_N16827), + .CIN (_N16766), .I0 (), .I1 (nb0[6]), .I2 (nb1[6]), @@ -354040,9 +353496,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N964_5_8 ( - .COUT (_N16829), + .COUT (_N16768), .Z (N964[7]), - .CIN (_N16828), + .CIN (_N16767), .I0 (), .I1 (nb0[7]), .I2 (nb1[7]), @@ -354059,9 +353515,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N964_5_9 ( - .COUT (_N16830), + .COUT (_N16769), .Z (N964[8]), - .CIN (_N16829), + .CIN (_N16768), .I0 (), .I1 (nb0[8]), .I2 (nb1[8]), @@ -354078,9 +353534,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N964_5_10 ( - .COUT (_N16831), + .COUT (_N16770), .Z (N964[9]), - .CIN (_N16830), + .CIN (_N16769), .I0 (), .I1 (nb0[9]), .I2 (nb1[9]), @@ -354097,9 +353553,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N964_5_11 ( - .COUT (_N16832), + .COUT (_N16771), .Z (N964[10]), - .CIN (_N16831), + .CIN (_N16770), .I0 (), .I1 (nb0[10]), .I2 (nb1[10]), @@ -354116,9 +353572,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N964_5_12 ( - .COUT (_N16833), + .COUT (_N16772), .Z (N964[11]), - .CIN (_N16832), + .CIN (_N16771), .I0 (), .I1 (nb0[11]), .I2 (nb1[11]), @@ -354135,9 +353591,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N964_5_13 ( - .COUT (_N16834), + .COUT (_N16773), .Z (N964[12]), - .CIN (_N16833), + .CIN (_N16772), .I0 (), .I1 (nb0[12]), .I2 (nb1[12]), @@ -354154,9 +353610,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N964_5_14 ( - .COUT (_N16835), + .COUT (_N16774), .Z (N964[13]), - .CIN (_N16834), + .CIN (_N16773), .I0 (), .I1 (nb0[13]), .I2 (nb1[13]), @@ -354173,9 +353629,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N964_5_15 ( - .COUT (_N16836), + .COUT (_N16775), .Z (N964[14]), - .CIN (_N16835), + .CIN (_N16774), .I0 (), .I1 (nb0[14]), .I2 (nb1[14]), @@ -354192,9 +353648,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N964_5_16 ( - .COUT (_N16837), + .COUT (_N16776), .Z (N964[15]), - .CIN (_N16836), + .CIN (_N16775), .I0 (), .I1 (nb0[15]), .I2 (nb1[15]), @@ -354211,9 +353667,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N964_5_17 ( - .COUT (_N16838), + .COUT (_N16777), .Z (N964[16]), - .CIN (_N16837), + .CIN (_N16776), .I0 (), .I1 (N958), .I2 (N3909[16]), @@ -354230,9 +353686,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N964_5_18 ( - .COUT (_N16839), + .COUT (_N16778), .Z (N964[17]), - .CIN (_N16838), + .CIN (_N16777), .I0 (), .I1 (N958), .I2 (N3909[17]), @@ -354249,9 +353705,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N964_5_19 ( - .COUT (_N16840), + .COUT (_N16779), .Z (N964[18]), - .CIN (_N16839), + .CIN (_N16778), .I0 (), .I1 (N958), .I2 (N3909[18]), @@ -354268,9 +353724,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N964_5_20 ( - .COUT (_N16841), + .COUT (_N16780), .Z (N964[19]), - .CIN (_N16840), + .CIN (_N16779), .I0 (), .I1 (N958), .I2 (N3909[19]), @@ -354287,9 +353743,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N964_5_21 ( - .COUT (_N16842), + .COUT (_N16781), .Z (N964[20]), - .CIN (_N16841), + .CIN (_N16780), .I0 (), .I1 (N958), .I2 (N3909[20]), @@ -354306,9 +353762,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N964_5_22 ( - .COUT (_N16843), + .COUT (_N16782), .Z (N964[21]), - .CIN (_N16842), + .CIN (_N16781), .I0 (), .I1 (N958), .I2 (N3909[21]), @@ -354325,9 +353781,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N964_5_23 ( - .COUT (_N16844), + .COUT (_N16783), .Z (N964[22]), - .CIN (_N16843), + .CIN (_N16782), .I0 (), .I1 (N958), .I2 (N3909[22]), @@ -354344,9 +353800,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N964_5_24 ( - .COUT (_N16845), + .COUT (_N16784), .Z (N964[23]), - .CIN (_N16844), + .CIN (_N16783), .I0 (), .I1 (N958), .I2 (N3909[23]), @@ -354363,9 +353819,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N964_5_25 ( - .COUT (_N16846), + .COUT (_N16785), .Z (N964[24]), - .CIN (_N16845), + .CIN (_N16784), .I0 (), .I1 (N958), .I2 (N3909[24]), @@ -354382,9 +353838,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N964_5_26 ( - .COUT (_N16847), + .COUT (_N16786), .Z (N964[25]), - .CIN (_N16846), + .CIN (_N16785), .I0 (), .I1 (N958), .I2 (N3909[25]), @@ -354401,9 +353857,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N964_5_27 ( - .COUT (_N16848), + .COUT (_N16787), .Z (N964[26]), - .CIN (_N16847), + .CIN (_N16786), .I0 (), .I1 (N958), .I2 (N3909[26]), @@ -354420,9 +353876,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N964_5_28 ( - .COUT (_N16849), + .COUT (_N16788), .Z (N964[27]), - .CIN (_N16848), + .CIN (_N16787), .I0 (), .I1 (N958), .I2 (N3909[27]), @@ -354439,9 +353895,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N964_5_29 ( - .COUT (_N16850), + .COUT (_N16789), .Z (N964[28]), - .CIN (_N16849), + .CIN (_N16788), .I0 (), .I1 (N958), .I2 (N3909[28]), @@ -354458,9 +353914,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N964_5_30 ( - .COUT (_N16851), + .COUT (_N16790), .Z (N964[29]), - .CIN (_N16850), + .CIN (_N16789), .I0 (), .I1 (N958), .I2 (N3909[29]), @@ -354477,9 +353933,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N964_5_31 ( - .COUT (_N16852), + .COUT (_N16791), .Z (N964[30]), - .CIN (_N16851), + .CIN (_N16790), .I0 (), .I1 (N958), .I2 (N3909[30]), @@ -354498,7 +353954,7 @@ module icmp_tx N964_5_32 ( .COUT (), .Z (N964[31]), - .CIN (_N16852), + .CIN (_N16791), .I0 (), .I1 (N958), .I2 (N3909[31]), @@ -354706,7 +354162,7 @@ module icmp_tx .I2 (crc_data[15]), .I3 (tx_bit_sel[1]), .I4 (tx_bit_sel[0]), - .ID (_N96067)); + .ID (_N96861)); // LUT = (ID&I1&~I3&~I4)|(~I2&I3&~I4)|(~I1&~I3&I4)|(~I0&I3&I4)|(~ID&~I1&~I3) ; GTP_LUT5M /* \N1039_21[1] */ #( @@ -354730,7 +354186,7 @@ module icmp_tx .I2 (crc_data[13]), .I3 (tx_bit_sel[1]), .I4 (tx_bit_sel[0]), - .ID (_N97048)); + .ID (_N97827)); // LUT = (ID&I1&~I3&~I4)|(~I2&I3&~I4)|(~I1&~I3&I4)|(~I0&I3&I4)|(~ID&~I1&~I3) ; GTP_LUT5M /* \N1039_21[3] */ #( @@ -354778,7 +354234,7 @@ module icmp_tx .I2 (crc_data[9]), .I3 (tx_bit_sel[1]), .I4 (tx_bit_sel[0]), - .ID (_N97050)); + .ID (_N97829)); // LUT = (ID&I1&~I3&~I4)|(~I2&I3&~I4)|(~I1&~I3&I4)|(~I0&I3&I4)|(~ID&~I1&~I3) ; GTP_LUT5M /* \N1039_21[7] */ #( @@ -354866,7 +354322,7 @@ module icmp_tx GTP_LUT2 /* \N1039_24[0]_1 */ #( .INIT(4'b0100)) \N1039_24[0]_1 ( - .Z (_N108095), + .Z (_N108930), .I0 (N611), .I1 (N613)); // LUT = ~I0&I1 ; @@ -354874,7 +354330,7 @@ module icmp_tx GTP_LUT5M /* \N1039_24[7]_2 */ #( .INIT(32'b11100010110000001110001011100010)) \N1039_24[7]_2 ( - .Z (_N108106), + .Z (_N108941), .I0 (\udp_osd_inst/eth_udp_inst/tx_data [7] ), .I1 (N611), .I2 (N267[7]), @@ -354883,27 +354339,27 @@ module icmp_tx .ID (_N26740)); // LUT = (ID&~I1&~I4)|(I0&~I1&I3&I4)|(I1&I2) ; - GTP_LUT5M /* \N1039_26[0] */ #( + GTP_LUT3 /* \N1039_26[0]_1 */ #( + .INIT(8'b00000010)) + \N1039_26[0]_1 ( + .Z (_N97455), + .I0 (N609), + .I1 (cnt[3]), + .I2 (cnt[4])); + // LUT = I0&~I1&~I2 ; + + GTP_LUT5M /* \N1039_26[0]_2 */ #( .INIT(32'b11111111101010101111111111001010)) - \N1039_26[0] ( + \N1039_26[0]_2 ( .Z (N1039[0]), .I0 (N267[0]), .I1 (_N26701), .I2 (N613), - .I3 (_N96367), + .I3 (_N97455), .I4 (N611), .ID (_N26741)); // LUT = (ID&~I2&~I4)|(I1&I2&~I4)|(I0&I4)|(I3) ; - GTP_LUT3 /* \N1039_26[0]_1 */ #( - .INIT(8'b00000010)) - \N1039_26[0]_1 ( - .Z (_N96367), - .I0 (N609), - .I1 (cnt[3]), - .I2 (cnt[4])); - // LUT = I0&~I1&~I2 ; - GTP_LUT5M /* \N1039_26[1] */ #( .INIT(32'b00000000101010100000000011001010)) \N1039_26[1] ( @@ -354911,19 +354367,19 @@ module icmp_tx .I0 (N267[1]), .I1 (_N26702), .I2 (N613), - .I3 (_N96367), + .I3 (_N97455), .I4 (N611), .ID (_N26742)); // LUT = (ID&~I2&~I3&~I4)|(I1&I2&~I3&~I4)|(I0&~I3&I4) ; - GTP_LUT5M /* \N1039_26[2]_1 */ #( + GTP_LUT5M /* \N1039_26[2] */ #( .INIT(32'b11111111101010101111111111001010)) - \N1039_26[2]_1 ( + \N1039_26[2] ( .Z (N1039[2]), .I0 (N267[2]), .I1 (_N26703), .I2 (N613), - .I3 (_N96367), + .I3 (_N97455), .I4 (N611), .ID (_N26743)); // LUT = (ID&~I2&~I4)|(I1&I2&~I4)|(I0&I4)|(I3) ; @@ -354935,7 +354391,7 @@ module icmp_tx .I0 (N267[3]), .I1 (_N26704), .I2 (N613), - .I3 (_N96367), + .I3 (_N97455), .I4 (N611), .ID (_N26744)); // LUT = (ID&~I2&~I3&~I4)|(I1&I2&~I3&~I4)|(I0&~I3&I4) ; @@ -354947,7 +354403,7 @@ module icmp_tx .I0 (N267[4]), .I1 (_N26705), .I2 (N613), - .I3 (_N96367), + .I3 (_N97455), .I4 (N611), .ID (_N26745)); // LUT = (ID&~I2&~I4)|(I1&I2&~I4)|(I0&I4)|(I3) ; @@ -354959,19 +354415,19 @@ module icmp_tx .I0 (N267[5]), .I1 (_N26706), .I2 (N613), - .I3 (_N96367), + .I3 (_N97455), .I4 (N611), .ID (_N26746)); // LUT = (ID&~I2&~I3&~I4)|(I1&I2&~I3&~I4)|(I0&~I3&I4) ; - GTP_LUT5M /* \N1039_26[6] */ #( + GTP_LUT5M /* \N1039_26[6]_1 */ #( .INIT(32'b11111111101010101111111111001010)) - \N1039_26[6] ( + \N1039_26[6]_1 ( .Z (N1039[6]), .I0 (N267[6]), .I1 (_N26707), .I2 (N613), - .I3 (_N96367), + .I3 (_N97455), .I4 (N611), .ID (_N26747)); // LUT = (ID&~I2&~I4)|(I1&I2&~I4)|(I0&I4)|(I3) ; @@ -354982,16 +354438,16 @@ module icmp_tx .Z (N1039[7]), .I0 (_N26708), .I1 (N610), - .I2 (_N84470), + .I2 (_N85270), .I3 (N609), - .I4 (_N108095), - .ID (_N108106)); + .I4 (_N108930), + .ID (_N108941)); // LUT = (ID&~I3&~I4)|(ID&~I2&~I4)|(I0&~I3&I4)|(I0&~I2&I4)|(I1&I3) ; GTP_LUT5 /* N1039_28_4 */ #( .INIT(32'b00000000000000000000000001111111)) N1039_28_4 ( - .Z (_N84470), + .Z (_N85270), .I0 (cnt[0]), .I1 (cnt[1]), .I2 (cnt[2]), @@ -355002,7 +354458,7 @@ module icmp_tx GTP_LUT5 /* N1066_2 */ #( .INIT(32'b00000000100010000100000001000000)) N1066_2 ( - .Z (_N107862), + .Z (_N108694), .I0 (skip_en), .I1 (trig_tx_en), .I2 (cur_state_reg[0]), @@ -355016,8 +354472,8 @@ module icmp_tx .Z (N969), .I0 (cur_state_reg[4]), .I1 (cur_state_reg[5]), - .I2 (_N96003), - .I3 (_N107862), + .I2 (_N97265), + .I3 (_N108694), .I4 (skip_en), .ID (cur_state_reg[6])); // LUT = (~ID&~I1&I2&I3&~I4)|(~I0&~I1&I2&I3&I4) ; @@ -355099,7 +354555,7 @@ module icmp_tx .INIT(16'b0100110010000000)) \N1115[4]_1 ( .Z (N1115[4]), - .I0 (_N10498), + .I0 (_N10512), .I1 (N349), .I2 (real_add_cnt[3]), .I3 (real_add_cnt[4])); @@ -355129,10 +354585,10 @@ module icmp_tx N1731_vname ( .Z (N1731), .I0 (sync_vg_100m), - .I1 (_N97022), + .I1 (_N97693), .I2 (N603), .I3 (N969), - .I4 (_N107685)); + .I4 (_N108517)); // defparam N1731_vname.orig_name = N1731; // LUT = (~I0&I3)|(~I0&I1&I2&I4) ; @@ -355294,9 +354750,9 @@ module icmp_tx N3084_5 ( .Z (N3084), .I0 (sync_vg_100m), - .I1 (_N97022), + .I1 (_N97693), .I2 (N603), - .I3 (_N107683)); + .I3 (_N108515)); // LUT = ~I0&I1&I2&I3 ; GTP_LUT5CARRY /* N3870_1 */ #( @@ -355306,7 +354762,7 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3870_1 ( - .COUT (_N16893), + .COUT (_N16832), .Z (N3909[0]), .CIN (), .I0 (\ip_head[6] [16] ), @@ -355326,9 +354782,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3870_2 ( - .COUT (_N16894), + .COUT (_N16833), .Z (N3909[1]), - .CIN (_N16893), + .CIN (_N16832), .I0 (\ip_head[6] [16] ), .I1 (reply_checksum[0]), .I2 (\ip_head[6] [17] ), @@ -355346,9 +354802,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3870_3 ( - .COUT (_N16895), + .COUT (_N16834), .Z (N3909[2]), - .CIN (_N16894), + .CIN (_N16833), .I0 (), .I1 (\ip_head[6] [18] ), .I2 (reply_checksum[2]), @@ -355366,9 +354822,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3870_4 ( - .COUT (_N16896), + .COUT (_N16835), .Z (N3909[3]), - .CIN (_N16895), + .CIN (_N16834), .I0 (), .I1 (\ip_head[6] [19] ), .I2 (reply_checksum[3]), @@ -355386,9 +354842,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3870_5 ( - .COUT (_N16897), + .COUT (_N16836), .Z (N3909[4]), - .CIN (_N16896), + .CIN (_N16835), .I0 (), .I1 (\ip_head[6] [20] ), .I2 (reply_checksum[4]), @@ -355406,9 +354862,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3870_6 ( - .COUT (_N16898), + .COUT (_N16837), .Z (N3909[5]), - .CIN (_N16897), + .CIN (_N16836), .I0 (), .I1 (\ip_head[6] [21] ), .I2 (reply_checksum[5]), @@ -355426,9 +354882,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3870_7 ( - .COUT (_N16899), + .COUT (_N16838), .Z (N3909[6]), - .CIN (_N16898), + .CIN (_N16837), .I0 (), .I1 (\ip_head[6] [22] ), .I2 (reply_checksum[6]), @@ -355446,9 +354902,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3870_8 ( - .COUT (_N16900), + .COUT (_N16839), .Z (N3909[7]), - .CIN (_N16899), + .CIN (_N16838), .I0 (), .I1 (\ip_head[6] [23] ), .I2 (reply_checksum[7]), @@ -355466,9 +354922,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3870_9 ( - .COUT (_N16901), + .COUT (_N16840), .Z (N3909[8]), - .CIN (_N16900), + .CIN (_N16839), .I0 (), .I1 (\ip_head[6] [24] ), .I2 (reply_checksum[8]), @@ -355486,9 +354942,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3870_10 ( - .COUT (_N16902), + .COUT (_N16841), .Z (N3909[9]), - .CIN (_N16901), + .CIN (_N16840), .I0 (), .I1 (\ip_head[6] [25] ), .I2 (reply_checksum[9]), @@ -355506,9 +354962,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3870_11 ( - .COUT (_N16903), + .COUT (_N16842), .Z (N3909[10]), - .CIN (_N16902), + .CIN (_N16841), .I0 (), .I1 (\ip_head[6] [26] ), .I2 (reply_checksum[10]), @@ -355526,9 +354982,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3870_12 ( - .COUT (_N16904), + .COUT (_N16843), .Z (N3909[11]), - .CIN (_N16903), + .CIN (_N16842), .I0 (), .I1 (\ip_head[6] [27] ), .I2 (reply_checksum[11]), @@ -355546,9 +355002,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3870_13 ( - .COUT (_N16905), + .COUT (_N16844), .Z (N3909[12]), - .CIN (_N16904), + .CIN (_N16843), .I0 (), .I1 (\ip_head[6] [28] ), .I2 (reply_checksum[12]), @@ -355566,9 +355022,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3870_14 ( - .COUT (_N16906), + .COUT (_N16845), .Z (N3909[13]), - .CIN (_N16905), + .CIN (_N16844), .I0 (), .I1 (\ip_head[6] [29] ), .I2 (reply_checksum[13]), @@ -355586,9 +355042,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3870_15 ( - .COUT (_N16907), + .COUT (_N16846), .Z (N3909[14]), - .CIN (_N16906), + .CIN (_N16845), .I0 (), .I1 (\ip_head[6] [30] ), .I2 (reply_checksum[14]), @@ -355606,9 +355062,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3870_16 ( - .COUT (_N16908), + .COUT (_N16847), .Z (N3909[15]), - .CIN (_N16907), + .CIN (_N16846), .I0 (), .I1 (\ip_head[6] [31] ), .I2 (reply_checksum[15]), @@ -355626,9 +355082,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3870_17 ( - .COUT (_N16909), + .COUT (_N16848), .Z (N3909[16]), - .CIN (_N16908), + .CIN (_N16847), .I0 (), .I1 (reply_checksum[16]), .I2 (), @@ -355646,9 +355102,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3870_18 ( - .COUT (_N16910), + .COUT (_N16849), .Z (N3909[17]), - .CIN (_N16909), + .CIN (_N16848), .I0 (), .I1 (reply_checksum[17]), .I2 (), @@ -355666,9 +355122,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3870_19 ( - .COUT (_N16911), + .COUT (_N16850), .Z (N3909[18]), - .CIN (_N16910), + .CIN (_N16849), .I0 (), .I1 (reply_checksum[18]), .I2 (), @@ -355686,9 +355142,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3870_20 ( - .COUT (_N16912), + .COUT (_N16851), .Z (N3909[19]), - .CIN (_N16911), + .CIN (_N16850), .I0 (), .I1 (reply_checksum[19]), .I2 (), @@ -355706,9 +355162,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3870_21 ( - .COUT (_N16913), + .COUT (_N16852), .Z (N3909[20]), - .CIN (_N16912), + .CIN (_N16851), .I0 (), .I1 (reply_checksum[20]), .I2 (), @@ -355726,9 +355182,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3870_22 ( - .COUT (_N16914), + .COUT (_N16853), .Z (N3909[21]), - .CIN (_N16913), + .CIN (_N16852), .I0 (), .I1 (reply_checksum[21]), .I2 (), @@ -355746,9 +355202,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3870_23 ( - .COUT (_N16915), + .COUT (_N16854), .Z (N3909[22]), - .CIN (_N16914), + .CIN (_N16853), .I0 (), .I1 (reply_checksum[22]), .I2 (), @@ -355766,9 +355222,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3870_24 ( - .COUT (_N16916), + .COUT (_N16855), .Z (N3909[23]), - .CIN (_N16915), + .CIN (_N16854), .I0 (), .I1 (reply_checksum[23]), .I2 (), @@ -355786,9 +355242,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3870_25 ( - .COUT (_N16917), + .COUT (_N16856), .Z (N3909[24]), - .CIN (_N16916), + .CIN (_N16855), .I0 (), .I1 (reply_checksum[24]), .I2 (), @@ -355806,9 +355262,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3870_26 ( - .COUT (_N16918), + .COUT (_N16857), .Z (N3909[25]), - .CIN (_N16917), + .CIN (_N16856), .I0 (), .I1 (reply_checksum[25]), .I2 (), @@ -355826,9 +355282,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3870_27 ( - .COUT (_N16919), + .COUT (_N16858), .Z (N3909[26]), - .CIN (_N16918), + .CIN (_N16857), .I0 (), .I1 (reply_checksum[26]), .I2 (), @@ -355846,9 +355302,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3870_28 ( - .COUT (_N16920), + .COUT (_N16859), .Z (N3909[27]), - .CIN (_N16919), + .CIN (_N16858), .I0 (), .I1 (reply_checksum[27]), .I2 (), @@ -355866,9 +355322,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3870_29 ( - .COUT (_N16921), + .COUT (_N16860), .Z (N3909[28]), - .CIN (_N16920), + .CIN (_N16859), .I0 (), .I1 (reply_checksum[28]), .I2 (), @@ -355886,9 +355342,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3870_30 ( - .COUT (_N16922), + .COUT (_N16861), .Z (N3909[29]), - .CIN (_N16921), + .CIN (_N16860), .I0 (), .I1 (reply_checksum[29]), .I2 (), @@ -355906,9 +355362,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3870_31 ( - .COUT (_N16923), + .COUT (_N16862), .Z (N3909[30]), - .CIN (_N16922), + .CIN (_N16861), .I0 (), .I1 (reply_checksum[30]), .I2 (), @@ -355928,7 +355384,7 @@ module icmp_tx N3870_32 ( .COUT (), .Z (N3909[31]), - .CIN (_N16923), + .CIN (_N16862), .I0 (), .I1 (reply_checksum[31]), .I2 (), @@ -355946,7 +355402,7 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3876_1_1 ( - .COUT (_N15574), + .COUT (_N15485), .Z (N3876[9]), .CIN (), .I0 (\ip_head[0] [8] ), @@ -355966,9 +355422,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3876_1_2 ( - .COUT (_N15575), + .COUT (_N15486), .Z (N3876[10]), - .CIN (_N15574), + .CIN (_N15485), .I0 (\ip_head[0] [8] ), .I1 (\ip_head[0] [9] ), .I2 (\ip_head[0] [10] ), @@ -355986,9 +355442,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3876_1_3 ( - .COUT (_N15576), + .COUT (_N15487), .Z (N3876[11]), - .CIN (_N15575), + .CIN (_N15486), .I0 (), .I1 (\ip_head[0] [11] ), .I2 (), @@ -356006,9 +355462,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3876_1_4 ( - .COUT (_N15577), + .COUT (_N15488), .Z (N3876[12]), - .CIN (_N15576), + .CIN (_N15487), .I0 (), .I1 (\ip_head[0] [12] ), .I2 (), @@ -356026,9 +355482,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3876_1_5 ( - .COUT (_N15578), + .COUT (_N15489), .Z (N3876[13]), - .CIN (_N15577), + .CIN (_N15488), .I0 (), .I1 (\ip_head[0] [13] ), .I2 (), @@ -356046,9 +355502,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3876_1_6 ( - .COUT (_N15579), + .COUT (_N15490), .Z (N3876[14]), - .CIN (_N15578), + .CIN (_N15489), .I0 (), .I1 (\ip_head[0] [14] ), .I2 (), @@ -356066,9 +355522,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3876_1_7 ( - .COUT (_N15580), + .COUT (_N15491), .Z (N3876[15]), - .CIN (_N15579), + .CIN (_N15490), .I0 (), .I1 (\ip_head[0] [15] ), .I2 (), @@ -356088,7 +355544,7 @@ module icmp_tx N3876_1_8 ( .COUT (), .Z (N3876[16]), - .CIN (_N15580), + .CIN (_N15491), .I0 (), .I1 (), .I2 (), @@ -356106,7 +355562,7 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3882_1_1 ( - .COUT (_N16032), + .COUT (_N15571), .Z (N3882[1]), .CIN (), .I0 (\ip_head[2] [0] ), @@ -356126,9 +355582,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3882_1_2 ( - .COUT (_N16033), + .COUT (_N15572), .Z (N3882[2]), - .CIN (_N16032), + .CIN (_N15571), .I0 (\ip_head[2] [0] ), .I1 (\ip_head[2] [1] ), .I2 (\ip_head[2] [2] ), @@ -356146,9 +355602,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3882_1_3 ( - .COUT (_N16034), + .COUT (_N15573), .Z (N3882[3]), - .CIN (_N16033), + .CIN (_N15572), .I0 (), .I1 (\ip_head[2] [3] ), .I2 (), @@ -356166,9 +355622,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3882_1_4 ( - .COUT (_N16035), + .COUT (_N15574), .Z (N3882[4]), - .CIN (_N16034), + .CIN (_N15573), .I0 (), .I1 (\ip_head[2] [4] ), .I2 (), @@ -356186,9 +355642,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3882_1_5 ( - .COUT (_N16036), + .COUT (_N15575), .Z (N3882[5]), - .CIN (_N16035), + .CIN (_N15574), .I0 (), .I1 (\ip_head[2] [5] ), .I2 (), @@ -356206,9 +355662,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3882_1_6 ( - .COUT (_N16037), + .COUT (_N15576), .Z (N3882[6]), - .CIN (_N16036), + .CIN (_N15575), .I0 (), .I1 (\ip_head[2] [6] ), .I2 (), @@ -356226,9 +355682,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3882_1_7 ( - .COUT (_N16038), + .COUT (_N15577), .Z (N3882[7]), - .CIN (_N16037), + .CIN (_N15576), .I0 (), .I1 (\ip_head[2] [7] ), .I2 (), @@ -356246,9 +355702,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3882_1_8 ( - .COUT (_N16039), + .COUT (_N15578), .Z (N3882[8]), - .CIN (_N16038), + .CIN (_N15577), .I0 (), .I1 (\ip_head[2] [8] ), .I2 (), @@ -356266,9 +355722,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3882_1_9 ( - .COUT (_N16040), + .COUT (_N15579), .Z (N3882[9]), - .CIN (_N16039), + .CIN (_N15578), .I0 (), .I1 (\ip_head[2] [9] ), .I2 (), @@ -356286,9 +355742,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3882_1_10 ( - .COUT (_N16041), + .COUT (_N15580), .Z (N3882[10]), - .CIN (_N16040), + .CIN (_N15579), .I0 (), .I1 (\ip_head[2] [10] ), .I2 (), @@ -356306,9 +355762,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3882_1_11 ( - .COUT (_N16042), + .COUT (_N15581), .Z (N3882[11]), - .CIN (_N16041), + .CIN (_N15580), .I0 (), .I1 (\ip_head[2] [11] ), .I2 (), @@ -356326,9 +355782,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3882_1_12 ( - .COUT (_N16043), + .COUT (_N15582), .Z (N3882[12]), - .CIN (_N16042), + .CIN (_N15581), .I0 (), .I1 (\ip_head[2] [12] ), .I2 (), @@ -356346,9 +355802,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3882_1_13 ( - .COUT (_N16044), + .COUT (_N15583), .Z (N3882[13]), - .CIN (_N16043), + .CIN (_N15582), .I0 (), .I1 (\ip_head[2] [13] ), .I2 (), @@ -356366,9 +355822,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3882_1_14 ( - .COUT (_N16045), + .COUT (_N15584), .Z (N3882[14]), - .CIN (_N16044), + .CIN (_N15583), .I0 (), .I1 (\ip_head[2] [14] ), .I2 (), @@ -356386,9 +355842,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3882_1_15 ( - .COUT (_N16046), + .COUT (_N15585), .Z (N3882[15]), - .CIN (_N16045), + .CIN (_N15584), .I0 (), .I1 (\ip_head[2] [15] ), .I2 (), @@ -356408,7 +355864,7 @@ module icmp_tx N3882_1_16 ( .COUT (), .Z (N3882[16]), - .CIN (_N16046), + .CIN (_N15585), .I0 (), .I1 (), .I2 (), @@ -356426,7 +355882,7 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3888_1 ( - .COUT (_N16926), + .COUT (_N16865), .Z (N3888[0]), .CIN (), .I0 (\ip_head[4] [16] ), @@ -356446,9 +355902,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3888_2 ( - .COUT (_N16927), + .COUT (_N16866), .Z (N3888[1]), - .CIN (_N16926), + .CIN (_N16865), .I0 (\ip_head[4] [16] ), .I1 (\ip_head[4] [0] ), .I2 (\ip_head[4] [17] ), @@ -356466,9 +355922,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3888_3 ( - .COUT (_N16928), + .COUT (_N16867), .Z (N3888[2]), - .CIN (_N16927), + .CIN (_N16866), .I0 (), .I1 (\ip_head[4] [18] ), .I2 (\ip_head[4] [2] ), @@ -356486,9 +355942,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3888_4 ( - .COUT (_N16929), + .COUT (_N16868), .Z (N3888[3]), - .CIN (_N16928), + .CIN (_N16867), .I0 (), .I1 (\ip_head[4] [19] ), .I2 (\ip_head[4] [3] ), @@ -356506,9 +355962,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3888_5 ( - .COUT (_N16930), + .COUT (_N16869), .Z (N3888[4]), - .CIN (_N16929), + .CIN (_N16868), .I0 (), .I1 (\ip_head[4] [20] ), .I2 (\ip_head[4] [4] ), @@ -356526,9 +355982,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3888_6 ( - .COUT (_N16931), + .COUT (_N16870), .Z (N3888[5]), - .CIN (_N16930), + .CIN (_N16869), .I0 (), .I1 (\ip_head[4] [21] ), .I2 (\ip_head[4] [5] ), @@ -356546,9 +356002,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3888_7 ( - .COUT (_N16932), + .COUT (_N16871), .Z (N3888[6]), - .CIN (_N16931), + .CIN (_N16870), .I0 (), .I1 (\ip_head[4] [22] ), .I2 (\ip_head[4] [6] ), @@ -356566,9 +356022,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3888_8 ( - .COUT (_N16933), + .COUT (_N16872), .Z (N3888[7]), - .CIN (_N16932), + .CIN (_N16871), .I0 (), .I1 (\ip_head[4] [23] ), .I2 (\ip_head[4] [7] ), @@ -356586,9 +356042,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3888_9 ( - .COUT (_N16934), + .COUT (_N16873), .Z (N3888[8]), - .CIN (_N16933), + .CIN (_N16872), .I0 (), .I1 (\ip_head[4] [24] ), .I2 (\ip_head[4] [8] ), @@ -356606,9 +356062,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3888_10 ( - .COUT (_N16935), + .COUT (_N16874), .Z (N3888[9]), - .CIN (_N16934), + .CIN (_N16873), .I0 (), .I1 (\ip_head[4] [25] ), .I2 (\ip_head[4] [9] ), @@ -356626,9 +356082,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3888_11 ( - .COUT (_N16936), + .COUT (_N16875), .Z (N3888[10]), - .CIN (_N16935), + .CIN (_N16874), .I0 (), .I1 (\ip_head[4] [26] ), .I2 (\ip_head[4] [10] ), @@ -356646,9 +356102,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3888_12 ( - .COUT (_N16937), + .COUT (_N16876), .Z (N3888[11]), - .CIN (_N16936), + .CIN (_N16875), .I0 (), .I1 (\ip_head[4] [27] ), .I2 (\ip_head[4] [11] ), @@ -356666,9 +356122,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3888_13 ( - .COUT (_N16938), + .COUT (_N16877), .Z (N3888[12]), - .CIN (_N16937), + .CIN (_N16876), .I0 (), .I1 (\ip_head[4] [28] ), .I2 (\ip_head[4] [12] ), @@ -356686,9 +356142,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3888_14 ( - .COUT (_N16939), + .COUT (_N16878), .Z (N3888[13]), - .CIN (_N16938), + .CIN (_N16877), .I0 (), .I1 (\ip_head[4] [29] ), .I2 (\ip_head[4] [13] ), @@ -356706,9 +356162,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3888_15 ( - .COUT (_N16940), + .COUT (_N16879), .Z (N3888[14]), - .CIN (_N16939), + .CIN (_N16878), .I0 (), .I1 (\ip_head[4] [30] ), .I2 (\ip_head[4] [14] ), @@ -356726,9 +356182,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3888_16 ( - .COUT (_N16941), + .COUT (_N16880), .Z (N3888[15]), - .CIN (_N16940), + .CIN (_N16879), .I0 (), .I1 (\ip_head[4] [31] ), .I2 (\ip_head[4] [15] ), @@ -356748,7 +356204,7 @@ module icmp_tx N3888_17 ( .COUT (), .Z (N3888[16]), - .CIN (_N16941), + .CIN (_N16880), .I0 (), .I1 (), .I2 (), @@ -356766,7 +356222,7 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3891_1 ( - .COUT (_N16944), + .COUT (_N16883), .Z (N3891[0]), .CIN (), .I0 (\ip_head[1] [16] ), @@ -356786,9 +356242,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3891_2 ( - .COUT (_N16945), + .COUT (_N16884), .Z (N3891[1]), - .CIN (_N16944), + .CIN (_N16883), .I0 (\ip_head[1] [16] ), .I1 (\ip_head[0] [0] ), .I2 (\ip_head[1] [17] ), @@ -356806,9 +356262,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3891_3 ( - .COUT (_N16946), + .COUT (_N16885), .Z (N3891[2]), - .CIN (_N16945), + .CIN (_N16884), .I0 (), .I1 (\ip_head[1] [18] ), .I2 (\ip_head[0] [2] ), @@ -356826,9 +356282,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3891_4 ( - .COUT (_N16947), + .COUT (_N16886), .Z (N3891[3]), - .CIN (_N16946), + .CIN (_N16885), .I0 (), .I1 (\ip_head[1] [19] ), .I2 (\ip_head[0] [3] ), @@ -356846,9 +356302,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3891_5 ( - .COUT (_N16948), + .COUT (_N16887), .Z (N3891[4]), - .CIN (_N16947), + .CIN (_N16886), .I0 (), .I1 (\ip_head[1] [20] ), .I2 (\ip_head[0] [4] ), @@ -356866,9 +356322,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3891_6 ( - .COUT (_N16949), + .COUT (_N16888), .Z (N3891[5]), - .CIN (_N16948), + .CIN (_N16887), .I0 (), .I1 (\ip_head[1] [21] ), .I2 (\ip_head[0] [5] ), @@ -356886,9 +356342,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3891_7 ( - .COUT (_N16950), + .COUT (_N16889), .Z (N3891[6]), - .CIN (_N16949), + .CIN (_N16888), .I0 (), .I1 (\ip_head[1] [22] ), .I2 (\ip_head[0] [6] ), @@ -356906,9 +356362,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3891_8 ( - .COUT (_N16951), + .COUT (_N16890), .Z (N3891[7]), - .CIN (_N16950), + .CIN (_N16889), .I0 (), .I1 (\ip_head[1] [23] ), .I2 (\ip_head[0] [7] ), @@ -356926,9 +356382,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3891_9 ( - .COUT (_N16952), + .COUT (_N16891), .Z (N3891[8]), - .CIN (_N16951), + .CIN (_N16890), .I0 (), .I1 (\ip_head[1] [24] ), .I2 (\ip_head[0] [8] ), @@ -356946,9 +356402,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3891_10 ( - .COUT (_N16953), + .COUT (_N16892), .Z (N3891[9]), - .CIN (_N16952), + .CIN (_N16891), .I0 (), .I1 (\ip_head[1] [25] ), .I2 (N3876[9]), @@ -356966,9 +356422,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3891_11 ( - .COUT (_N16954), + .COUT (_N16893), .Z (N3891[10]), - .CIN (_N16953), + .CIN (_N16892), .I0 (), .I1 (\ip_head[1] [26] ), .I2 (N3876[10]), @@ -356986,9 +356442,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3891_12 ( - .COUT (_N16955), + .COUT (_N16894), .Z (N3891[11]), - .CIN (_N16954), + .CIN (_N16893), .I0 (), .I1 (\ip_head[1] [27] ), .I2 (N3876[11]), @@ -357006,9 +356462,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3891_13 ( - .COUT (_N16956), + .COUT (_N16895), .Z (N3891[12]), - .CIN (_N16955), + .CIN (_N16894), .I0 (), .I1 (\ip_head[1] [28] ), .I2 (N3876[12]), @@ -357026,9 +356482,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3891_14 ( - .COUT (_N16957), + .COUT (_N16896), .Z (N3891[13]), - .CIN (_N16956), + .CIN (_N16895), .I0 (), .I1 (\ip_head[1] [29] ), .I2 (N3876[13]), @@ -357046,9 +356502,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3891_15 ( - .COUT (_N16958), + .COUT (_N16897), .Z (N3891[14]), - .CIN (_N16957), + .CIN (_N16896), .I0 (), .I1 (\ip_head[1] [30] ), .I2 (N3876[14]), @@ -357066,9 +356522,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3891_16 ( - .COUT (_N16959), + .COUT (_N16898), .Z (N3891[15]), - .CIN (_N16958), + .CIN (_N16897), .I0 (), .I1 (\ip_head[1] [30] ), .I2 (N3876[15]), @@ -357086,9 +356542,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3891_17 ( - .COUT (_N16960), + .COUT (_N16899), .Z (N3891[16]), - .CIN (_N16959), + .CIN (_N16898), .I0 (), .I1 (\ip_head[1] [30] ), .I2 (N3876[16]), @@ -357108,7 +356564,7 @@ module icmp_tx N3891_18 ( .COUT (), .Z (N3891[17]), - .CIN (_N16960), + .CIN (_N16899), .I0 (), .I1 (), .I2 (), @@ -357126,7 +356582,7 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3894_1_1 ( - .COUT (_N16138), + .COUT (_N16017), .Z (N3894[2]), .CIN (), .I0 (N3882[1]), @@ -357146,9 +356602,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3894_1_2 ( - .COUT (_N16139), + .COUT (_N16018), .Z (N3894[3]), - .CIN (_N16138), + .CIN (_N16017), .I0 (N3882[1]), .I1 (N3882[2]), .I2 (N3882[3]), @@ -357166,9 +356622,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3894_1_3 ( - .COUT (_N16140), + .COUT (_N16019), .Z (N3894[4]), - .CIN (_N16139), + .CIN (_N16018), .I0 (), .I1 (N3882[4]), .I2 (), @@ -357186,9 +356642,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3894_1_4 ( - .COUT (_N16141), + .COUT (_N16020), .Z (N3894[5]), - .CIN (_N16140), + .CIN (_N16019), .I0 (), .I1 (N3882[5]), .I2 (), @@ -357206,9 +356662,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3894_1_5 ( - .COUT (_N16142), + .COUT (_N16021), .Z (N3894[6]), - .CIN (_N16141), + .CIN (_N16020), .I0 (), .I1 (N3882[6]), .I2 (), @@ -357226,9 +356682,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3894_1_6 ( - .COUT (_N16143), + .COUT (_N16022), .Z (N3894[7]), - .CIN (_N16142), + .CIN (_N16021), .I0 (), .I1 (N3882[7]), .I2 (), @@ -357246,9 +356702,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3894_1_7 ( - .COUT (_N16144), + .COUT (_N16023), .Z (N3894[8]), - .CIN (_N16143), + .CIN (_N16022), .I0 (), .I1 (N3882[8]), .I2 (), @@ -357266,9 +356722,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3894_1_8 ( - .COUT (_N16145), + .COUT (_N16024), .Z (N3894[9]), - .CIN (_N16144), + .CIN (_N16023), .I0 (), .I1 (N3882[9]), .I2 (), @@ -357286,9 +356742,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3894_1_9 ( - .COUT (_N16146), + .COUT (_N16025), .Z (N3894[10]), - .CIN (_N16145), + .CIN (_N16024), .I0 (), .I1 (N3882[10]), .I2 (), @@ -357306,9 +356762,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3894_1_10 ( - .COUT (_N16147), + .COUT (_N16026), .Z (N3894[11]), - .CIN (_N16146), + .CIN (_N16025), .I0 (), .I1 (N3882[11]), .I2 (), @@ -357326,9 +356782,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3894_1_11 ( - .COUT (_N16148), + .COUT (_N16027), .Z (N3894[12]), - .CIN (_N16147), + .CIN (_N16026), .I0 (), .I1 (N3882[12]), .I2 (), @@ -357346,9 +356802,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3894_1_12 ( - .COUT (_N16149), + .COUT (_N16028), .Z (N3894[13]), - .CIN (_N16148), + .CIN (_N16027), .I0 (), .I1 (N3882[13]), .I2 (), @@ -357366,9 +356822,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3894_1_13 ( - .COUT (_N16150), + .COUT (_N16029), .Z (N3894[14]), - .CIN (_N16149), + .CIN (_N16028), .I0 (), .I1 (N3882[14]), .I2 (), @@ -357386,9 +356842,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3894_1_14 ( - .COUT (_N16151), + .COUT (_N16030), .Z (N3894[15]), - .CIN (_N16150), + .CIN (_N16029), .I0 (), .I1 (N3882[15]), .I2 (), @@ -357406,9 +356862,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3894_1_15 ( - .COUT (_N16152), + .COUT (_N16031), .Z (N3894[16]), - .CIN (_N16151), + .CIN (_N16030), .I0 (), .I1 (N3882[16]), .I2 (), @@ -357428,7 +356884,7 @@ module icmp_tx N3894_1_16 ( .COUT (), .Z (N3894[17]), - .CIN (_N16152), + .CIN (_N16031), .I0 (), .I1 (), .I2 (), @@ -357446,7 +356902,7 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3897_1 ( - .COUT (_N16963), + .COUT (_N16911), .Z (N3897[0]), .CIN (), .I0 (\ip_head[2] [0] ), @@ -357466,9 +356922,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3897_2 ( - .COUT (_N16964), + .COUT (_N16912), .Z (N3897[1]), - .CIN (_N16963), + .CIN (_N16911), .I0 (\ip_head[2] [0] ), .I1 (N3891[0]), .I2 (N3882[1]), @@ -357486,9 +356942,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3897_3 ( - .COUT (_N16965), + .COUT (_N16913), .Z (N3897[2]), - .CIN (_N16964), + .CIN (_N16912), .I0 (), .I1 (N3894[2]), .I2 (N3891[2]), @@ -357506,9 +356962,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3897_4 ( - .COUT (_N16966), + .COUT (_N16914), .Z (N3897[3]), - .CIN (_N16965), + .CIN (_N16913), .I0 (), .I1 (N3894[3]), .I2 (N3891[3]), @@ -357526,9 +356982,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3897_5 ( - .COUT (_N16967), + .COUT (_N16915), .Z (N3897[4]), - .CIN (_N16966), + .CIN (_N16914), .I0 (), .I1 (N3894[4]), .I2 (N3891[4]), @@ -357546,9 +357002,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3897_6 ( - .COUT (_N16968), + .COUT (_N16916), .Z (N3897[5]), - .CIN (_N16967), + .CIN (_N16915), .I0 (), .I1 (N3894[5]), .I2 (N3891[5]), @@ -357566,9 +357022,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3897_7 ( - .COUT (_N16969), + .COUT (_N16917), .Z (N3897[6]), - .CIN (_N16968), + .CIN (_N16916), .I0 (), .I1 (N3894[6]), .I2 (N3891[6]), @@ -357586,9 +357042,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3897_8 ( - .COUT (_N16970), + .COUT (_N16918), .Z (N3897[7]), - .CIN (_N16969), + .CIN (_N16917), .I0 (), .I1 (N3894[7]), .I2 (N3891[7]), @@ -357606,9 +357062,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3897_9 ( - .COUT (_N16971), + .COUT (_N16919), .Z (N3897[8]), - .CIN (_N16970), + .CIN (_N16918), .I0 (), .I1 (N3894[8]), .I2 (N3891[8]), @@ -357626,9 +357082,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3897_10 ( - .COUT (_N16972), + .COUT (_N16920), .Z (N3897[9]), - .CIN (_N16971), + .CIN (_N16919), .I0 (), .I1 (N3894[9]), .I2 (N3891[9]), @@ -357646,9 +357102,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3897_11 ( - .COUT (_N16973), + .COUT (_N16921), .Z (N3897[10]), - .CIN (_N16972), + .CIN (_N16920), .I0 (), .I1 (N3894[10]), .I2 (N3891[10]), @@ -357666,9 +357122,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3897_12 ( - .COUT (_N16974), + .COUT (_N16922), .Z (N3897[11]), - .CIN (_N16973), + .CIN (_N16921), .I0 (), .I1 (N3894[11]), .I2 (N3891[11]), @@ -357686,9 +357142,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3897_13 ( - .COUT (_N16975), + .COUT (_N16923), .Z (N3897[12]), - .CIN (_N16974), + .CIN (_N16922), .I0 (), .I1 (N3894[12]), .I2 (N3891[12]), @@ -357706,9 +357162,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3897_14 ( - .COUT (_N16976), + .COUT (_N16924), .Z (N3897[13]), - .CIN (_N16975), + .CIN (_N16923), .I0 (), .I1 (N3894[13]), .I2 (N3891[13]), @@ -357726,9 +357182,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3897_15 ( - .COUT (_N16977), + .COUT (_N16925), .Z (N3897[14]), - .CIN (_N16976), + .CIN (_N16924), .I0 (), .I1 (N3894[14]), .I2 (N3891[14]), @@ -357746,9 +357202,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3897_16 ( - .COUT (_N16978), + .COUT (_N16926), .Z (N3897[15]), - .CIN (_N16977), + .CIN (_N16925), .I0 (), .I1 (N3894[15]), .I2 (N3891[15]), @@ -357766,9 +357222,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3897_17 ( - .COUT (_N16979), + .COUT (_N16927), .Z (N3897[16]), - .CIN (_N16978), + .CIN (_N16926), .I0 (), .I1 (N3894[16]), .I2 (N3891[16]), @@ -357786,9 +357242,9 @@ module icmp_tx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N3897_18 ( - .COUT (_N16980), + .COUT (_N16928), .Z (N3897[17]), - .CIN (_N16979), + .CIN (_N16927), .I0 (), .I1 (N3894[17]), .I2 (N3891[17]), @@ -357808,7 +357264,7 @@ module icmp_tx N3897_19 ( .COUT (), .Z (N3897[18]), - .CIN (_N16980), + .CIN (_N16928), .I0 (), .I1 (), .I2 (), @@ -358635,7 +358091,7 @@ module icmp_tx .C (sync_vg_100m), .CE (N1094), .CLK (clk), - .D (_N81128)); + .D (_N81901)); // ../../sources/designs/udp_osd/eth_udp/icmp/icmp_tx.v:187 GTP_DFF_CE /* \data_cnt[1] */ #( @@ -358646,7 +358102,7 @@ module icmp_tx .C (sync_vg_100m), .CE (N1094), .CLK (clk), - .D (_N81156)); + .D (_N81929)); // ../../sources/designs/udp_osd/eth_udp/icmp/icmp_tx.v:187 GTP_DFF_CE /* \data_cnt[2] */ #( @@ -358657,7 +358113,7 @@ module icmp_tx .C (sync_vg_100m), .CE (N1094), .CLK (clk), - .D (_N81172)); + .D (_N81945)); // ../../sources/designs/udp_osd/eth_udp/icmp/icmp_tx.v:187 GTP_DFF_CE /* \data_cnt[3] */ #( @@ -358668,7 +358124,7 @@ module icmp_tx .C (sync_vg_100m), .CE (N1094), .CLK (clk), - .D (_N81188)); + .D (_N81961)); // ../../sources/designs/udp_osd/eth_udp/icmp/icmp_tx.v:187 GTP_DFF_CE /* \data_cnt[4] */ #( @@ -358679,7 +358135,7 @@ module icmp_tx .C (sync_vg_100m), .CE (N1094), .CLK (clk), - .D (_N81204)); + .D (_N81977)); // ../../sources/designs/udp_osd/eth_udp/icmp/icmp_tx.v:187 GTP_DFF_CE /* \data_cnt[5] */ #( @@ -358690,7 +358146,7 @@ module icmp_tx .C (sync_vg_100m), .CE (N1094), .CLK (clk), - .D (_N81220)); + .D (_N81993)); // ../../sources/designs/udp_osd/eth_udp/icmp/icmp_tx.v:187 GTP_DFF_CE /* \data_cnt[6] */ #( @@ -358701,7 +358157,7 @@ module icmp_tx .C (sync_vg_100m), .CE (N1094), .CLK (clk), - .D (_N81236)); + .D (_N82009)); // ../../sources/designs/udp_osd/eth_udp/icmp/icmp_tx.v:187 GTP_DFF_CE /* \data_cnt[7] */ #( @@ -358712,7 +358168,7 @@ module icmp_tx .C (sync_vg_100m), .CE (N1094), .CLK (clk), - .D (_N81252)); + .D (_N82025)); // ../../sources/designs/udp_osd/eth_udp/icmp/icmp_tx.v:187 GTP_DFF_CE /* \data_cnt[8] */ #( @@ -358723,7 +358179,7 @@ module icmp_tx .C (sync_vg_100m), .CE (N1094), .CLK (clk), - .D (_N81268)); + .D (_N82041)); // ../../sources/designs/udp_osd/eth_udp/icmp/icmp_tx.v:187 GTP_DFF_CE /* \data_cnt[9] */ #( @@ -358734,7 +358190,7 @@ module icmp_tx .C (sync_vg_100m), .CE (N1094), .CLK (clk), - .D (_N81284)); + .D (_N82057)); // ../../sources/designs/udp_osd/eth_udp/icmp/icmp_tx.v:187 GTP_DFF_CE /* \data_cnt[10] */ #( @@ -358745,7 +358201,7 @@ module icmp_tx .C (sync_vg_100m), .CE (N1094), .CLK (clk), - .D (_N81300)); + .D (_N82073)); // ../../sources/designs/udp_osd/eth_udp/icmp/icmp_tx.v:187 GTP_DFF_CE /* \data_cnt[11] */ #( @@ -358756,7 +358212,7 @@ module icmp_tx .C (sync_vg_100m), .CE (N1094), .CLK (clk), - .D (_N81316)); + .D (_N82089)); // ../../sources/designs/udp_osd/eth_udp/icmp/icmp_tx.v:187 GTP_DFF_CE /* \data_cnt[12] */ #( @@ -358767,7 +358223,7 @@ module icmp_tx .C (sync_vg_100m), .CE (N1094), .CLK (clk), - .D (_N81332)); + .D (_N82105)); // ../../sources/designs/udp_osd/eth_udp/icmp/icmp_tx.v:187 GTP_DFF_CE /* \data_cnt[13] */ #( @@ -358778,7 +358234,7 @@ module icmp_tx .C (sync_vg_100m), .CE (N1094), .CLK (clk), - .D (_N81348)); + .D (_N82121)); // ../../sources/designs/udp_osd/eth_udp/icmp/icmp_tx.v:187 GTP_DFF_CE /* \data_cnt[14] */ #( @@ -358789,13 +358245,13 @@ module icmp_tx .C (sync_vg_100m), .CE (N1094), .CLK (clk), - .D (_N81364)); + .D (_N82137)); // ../../sources/designs/udp_osd/eth_udp/icmp/icmp_tx.v:187 - GTP_LUT2 /* \data_cnt[15:0]_5913 */ #( + GTP_LUT2 /* \data_cnt[15:0]_5836 */ #( .INIT(4'b0010)) - \data_cnt[15:0]_5913 ( - .Z (_N81128), + \data_cnt[15:0]_5836 ( + .Z (_N81901), .I0 (N329), .I1 (data_cnt[0])); // LUT = I0&~I1 ; @@ -358808,7 +358264,7 @@ module icmp_tx .C (sync_vg_100m), .CE (N1094), .CLK (clk), - .D (_N81380)); + .D (_N82153)); // ../../sources/designs/udp_osd/eth_udp/icmp/icmp_tx.v:187 GTP_DFF_PE /* \eth_head[0][0] */ #( @@ -359434,7 +358890,7 @@ module icmp_tx .Q (gmii_txd_valid), .C (sync_vg_100m), .CLK (clk), - .D (_N95792)); + .D (_N96572)); // defparam gmii_txd_valid_vname.orig_name = gmii_txd_valid; // ../../sources/designs/udp_osd/eth_udp/icmp/icmp_tx.v:187 @@ -361254,13 +360710,13 @@ module icmp_tx .Q (\udp_osd_inst/eth_udp_inst/tx_req ), .C (sync_vg_100m), .CLK (clk), - .D (_N103305)); + .D (_N104117)); // ../../sources/designs/udp_osd/eth_udp/icmp/icmp_tx.v:187 GTP_LUT5 /* tx_req_ce_mux */ #( .INIT(32'b00000000001111110000000000101010)) tx_req_ce_mux ( - .Z (_N103305), + .Z (_N104117), .I0 (\udp_osd_inst/eth_udp_inst/tx_req ), .I1 (N371), .I2 (N622), @@ -361279,32 +360735,27 @@ module icmp input [7:0] gmii_rxd_data, input [7:0] \udp_osd_inst/eth_udp_inst/tx_data , input [4:0] \udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt , - input [4:0] \udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt , input [6:0] \udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg , input [6:0] \udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/next_state , input [15:0] \udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt , - input _N95844, - input _N95913, - input _N95922, - input _N95925, - input _N95955, - input _N95958, - input _N96003, - input _N96007, - input _N96085, - input _N96096, - input _N96358, - input _N96556, - input _N96693, - input _N96780, - input _N97022, - input _N97473, - input _N107965, + input _N82491, + input _N96654, + input _N96657, + input _N96703, + input _N96734, + input _N97125, + input _N97265, + input _N97327, + input _N97338, + input _N97535, + input _N97554, + input _N98258, input gmii_rx_clk, input gmii_rxd_valid, input sync_vg_100m, - input \u_icmp_tx/N973 , + input \u_icmp_rx/N1269 , input \udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N52 , + input \udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N366 , input \udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_inv , input \udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N409_inv , input \udp_osd_inst/eth_udp_inst/u_eth_ctrl/icmp_tx_req_d0 , @@ -361314,26 +360765,28 @@ module icmp output [4:0] \u_icmp_rx/cnt , output [6:0] \u_icmp_rx/cur_state_reg , output [7:0] \u_icmp_tx/cur_state_reg , - output _N84201, - output _N96072, - output _N96385, - output _N96774, - output _N96776, - output _N98508, - output _N106910, - output _N106911, + output _N82337, + output _N96653, + output _N96787, + output _N97539, + output _N97540, + output _N97542, + output _N100572, + output _N107734, + output _N107735, + output _N108899, output gmii_txd_valid, output rec_en, output rec_pkt_done, - output \u_icmp_rx/error_en , + output \u_icmp_rx/N1265 , output \u_icmp_rx/skip_en , - output \u_icmp_tx/N969 , output \u_icmp_tx/skip_en , - output \udp_osd_inst/eth_udp_inst/tx_req + output \udp_osd_inst/eth_udp_inst/tx_req , + output \udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N559 ); - wire _N96067; - wire _N97048; - wire _N97050; + wire _N96861; + wire _N97827; + wire _N97829; wire [31:0] crc_data; wire crc_en; wire [31:0] crc_next; @@ -361378,15 +360831,19 @@ module icmp wire \u_crc32_d8_crc_next[25]_floating ; wire \u_crc32_d8_crc_next[29]_floating ; wire \u_crc32_d8_crc_next[31]_floating ; + wire \u_icmp_rx_cnt[0]_floating ; wire \u_icmp_rx_cur_state_reg[0]_floating ; + wire \u_icmp_rx_cur_state_reg[1]_floating ; + wire \u_icmp_rx_cur_state_reg[2]_floating ; + wire \u_icmp_rx_cur_state_reg[3]_floating ; crc32_d8_unq6 u_crc32_d8 ( .crc_data ({\u_crc32_d8_crc_data[31]_floating , \u_crc32_d8_crc_data[30]_floating , \u_crc32_d8_crc_data[29]_floating , \u_crc32_d8_crc_data[28]_floating , \u_crc32_d8_crc_data[27]_floating , \u_crc32_d8_crc_data[26]_floating , \u_crc32_d8_crc_data[25]_floating , \u_crc32_d8_crc_data[24]_floating , crc_data[23], crc_data[22], crc_data[21], crc_data[20], crc_data[19], crc_data[18], crc_data[17], crc_data[16], crc_data[15], crc_data[14], crc_data[13], crc_data[12], crc_data[11], crc_data[10], crc_data[9], crc_data[8], crc_data[7], crc_data[6], crc_data[5], crc_data[4], crc_data[3], crc_data[2], crc_data[1], crc_data[0]}), .crc_next ({\u_crc32_d8_crc_next[31]_floating , crc_next[30], \u_crc32_d8_crc_next[29]_floating , crc_next[28], crc_next[27], crc_next[26], \u_crc32_d8_crc_next[25]_floating , crc_next[24], \u_crc32_d8_crc_next[23]_floating , \u_crc32_d8_crc_next[22]_floating , \u_crc32_d8_crc_next[21]_floating , \u_crc32_d8_crc_next[20]_floating , \u_crc32_d8_crc_next[19]_floating , \u_crc32_d8_crc_next[18]_floating , \u_crc32_d8_crc_next[17]_floating , \u_crc32_d8_crc_next[16]_floating , \u_crc32_d8_crc_next[15]_floating , \u_crc32_d8_crc_next[14]_floating , \u_crc32_d8_crc_next[13]_floating , \u_crc32_d8_crc_next[12]_floating , \u_crc32_d8_crc_next[11]_floating , \u_crc32_d8_crc_next[10]_floating , \u_crc32_d8_crc_next[9]_floating , \u_crc32_d8_crc_next[8]_floating , \u_crc32_d8_crc_next[7]_floating , \u_crc32_d8_crc_next[6]_floating , \u_crc32_d8_crc_next[5]_floating , \u_crc32_d8_crc_next[4]_floating , \u_crc32_d8_crc_next[3]_floating , \u_crc32_d8_crc_next[2]_floating , \u_crc32_d8_crc_next[1]_floating , \u_crc32_d8_crc_next[0]_floating }), .data (gmii_txd_data), - ._N96067 (_N96067), - ._N97048 (_N97048), - ._N97050 (_N97050), + ._N96861 (_N96861), + ._N97827 (_N97827), + ._N97829 (_N97829), .clk (gmii_rx_clk), .crc_en (crc_en), .sync_vg_100m (sync_vg_100m), @@ -361394,8 +360851,8 @@ module icmp // ../../sources/designs/udp_osd/eth_udp/icmp/icmp.v:121 icmp_rx u_icmp_rx ( - .cnt ({\u_icmp_rx/cnt [4] , \u_icmp_rx/cnt [3] , \u_icmp_rx/cnt [2] , \u_icmp_rx/cnt [1] , \u_icmp_rx/cnt [0] }), - .cur_state_reg ({\u_icmp_rx/cur_state_reg [6] , \u_icmp_rx/cur_state_reg [5] , \u_icmp_rx/cur_state_reg [4] , \u_icmp_rx/cur_state_reg [3] , \u_icmp_rx/cur_state_reg [2] , \u_icmp_rx/cur_state_reg [1] , \u_icmp_rx_cur_state_reg[0]_floating }), + .cnt ({\u_icmp_rx/cnt [4] , \u_icmp_rx/cnt [3] , \u_icmp_rx/cnt [2] , \u_icmp_rx/cnt [1] , \u_icmp_rx_cnt[0]_floating }), + .cur_state_reg ({\u_icmp_rx/cur_state_reg [6] , \u_icmp_rx/cur_state_reg [5] , \u_icmp_rx/cur_state_reg [4] , \u_icmp_rx_cur_state_reg[3]_floating , \u_icmp_rx_cur_state_reg[2]_floating , \u_icmp_rx_cur_state_reg[1]_floating , \u_icmp_rx_cur_state_reg[0]_floating }), .icmp_id (icmp_id), .icmp_seq (icmp_seq), .rec_byte_num (rec_byte_num), @@ -361403,36 +360860,36 @@ module icmp .reply_checksum (reply_checksum), .gmii_rxd_data (gmii_rxd_data), .\udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt ({\udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt [4] , \udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt [3] , \udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt [2] , \udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt [1] , 1'bx}), - .\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt ({1'bx, 1'bx, \udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt [2] , \udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt [1] , 1'bx}), - .\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg ({1'bx, 1'bx, \udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg [4] , \udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg [3] , 1'bx, 1'bx, 1'bx}), - .\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/next_state ({1'bx, 1'bx, 1'bx, \udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/next_state [3] , \udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/next_state [2] , 1'bx, 1'bx}), - ._N84201 (_N84201), - ._N96072 (_N96072), - ._N96385 (_N96385), - ._N96774 (_N96774), - ._N96776 (_N96776), - ._N98508 (_N98508), - .error_en (\u_icmp_rx/error_en ), + .\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg ({1'bx, \udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg [5] , \udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg [4] , 1'bx, 1'bx, 1'bx, 1'bx}), + .\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/next_state ({1'bx, 1'bx, \udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/next_state [4] , \udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/next_state [3] , \udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/next_state [2] , \udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/next_state [1] , \udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/next_state [0] }), + .N1265 (\u_icmp_rx/N1265 ), + ._N82337 (_N82337), + ._N96653 (_N96653), + ._N96787 (_N96787), + ._N97539 (_N97539), + ._N97540 (_N97540), + ._N97542 (_N97542), + ._N100572 (_N100572), + ._N108899 (_N108899), .rec_en (rec_en), .rec_pkt_done (rec_pkt_done), .skip_en (\u_icmp_rx/skip_en ), .\udp_osd_inst/eth_udp_inst/icmp_tx_byte_num[2]_inv (\udp_osd_inst/eth_udp_inst/icmp_tx_byte_num[2]_inv ), + .\udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N559 (\udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N559 ), .N74 (\udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N52 ), - ._N95844 (_N95844), - ._N95922 (_N95922), - ._N95925 (_N95925), - ._N96007 (_N96007), - ._N96085 (_N96085), - ._N96096 (_N96096), - ._N96358 (_N96358), - ._N96556 (_N96556), - ._N96693 (_N96693), - ._N96780 (_N96780), - ._N97473 (_N97473), - ._N107965 (_N107965), + .N1269 (\u_icmp_rx/N1269 ), + ._N82491 (_N82491), + ._N96654 (_N96654), + ._N96657 (_N96657), + ._N97327 (_N97327), + ._N97338 (_N97338), + ._N97535 (_N97535), + ._N97554 (_N97554), + ._N98258 (_N98258), .clk (gmii_rx_clk), .gmii_rxd_valid (gmii_rxd_valid), .sync_vg_100m (sync_vg_100m), + .\udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N366 (\udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N366 ), .\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/skip_en (\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/skip_en )); // ../../sources/designs/udp_osd/eth_udp/icmp/icmp.v:79 @@ -361449,9 +360906,8 @@ module icmp .tx_byte_num (rec_byte_num), .\udp_osd_inst/eth_udp_inst/tx_data ({\udp_osd_inst/eth_udp_inst/tx_data [7] , \udp_osd_inst/eth_udp_inst/tx_data [6] , \udp_osd_inst/eth_udp_inst/tx_data [5] , \udp_osd_inst/eth_udp_inst/tx_data [4] , \udp_osd_inst/eth_udp_inst/tx_data [3] , \udp_osd_inst/eth_udp_inst/tx_data [2] , \udp_osd_inst/eth_udp_inst/tx_data [1] , \udp_osd_inst/eth_udp_inst/tx_data [0] }), .\udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt ({\udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt [15] , \udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt [14] , \udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt [13] , \udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt [12] , \udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt [11] , \udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt [10] , \udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt [9] , \udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt [8] , \udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt [7] , \udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt [6] , \udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt [5] , \udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt [4] , \udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt [3] , \udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt [2] , 1'bx, 1'bx}), - .N969 (\u_icmp_tx/N969 ), - ._N106910 (_N106910), - ._N106911 (_N106911), + ._N107734 (_N107734), + ._N107735 (_N107735), .crc_en (crc_en), .gmii_txd_valid (gmii_txd_valid), .skip_en (\u_icmp_tx/skip_en ), @@ -361459,15 +360915,13 @@ module icmp .\udp_osd_inst/eth_udp_inst/tx_req (\udp_osd_inst/eth_udp_inst/tx_req ), .N543_inv (\udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N409_inv ), .N592_inv (\udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_inv ), - .N973 (\u_icmp_tx/N973 ), - ._N95913 (_N95913), - ._N95955 (_N95955), - ._N95958 (_N95958), - ._N96003 (_N96003), - ._N96067 (_N96067), - ._N97022 (_N97022), - ._N97048 (_N97048), - ._N97050 (_N97050), + ._N96703 (_N96703), + ._N96734 (_N96734), + ._N96861 (_N96861), + ._N97125 (_N97125), + ._N97265 (_N97265), + ._N97827 (_N97827), + ._N97829 (_N97829), .clk (gmii_rx_clk), .sync_vg_100m (sync_vg_100m), .tx_start_en (rec_pkt_done), @@ -361482,42 +360936,46 @@ endmodule module udp_rx ( input [7:0] gmii_rxd_data, - input [4:0] \udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt , input [4:0] \udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt , + input [6:0] \udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg , input N64, input N586, - input _N95923, - input _N96072, - input _N96096, - input _N96385, - input _N96556, - input _N96774, - input _N97006, - input _N97473, - input _N98508, + input _N82337, + input _N96653, + input _N96787, + input _N97121, + input _N97122, + input _N97327, + input _N97341, + input _N97542, + input _N97887, + input _N98258, + input _N100572, + input _N108899, input clk, input gmii_rxd_valid, input sync_vg_100m, - input \udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N366 , + input \udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1265 , + input \udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/skip_en , output [4:0] cnt, output [6:0] cur_state_reg, output [6:0] next_state, output [15:0] rec_byte_num, output [7:0] rec_data, output [15:0] rec_dest_port, - output _N95844, - output _N96358, - output _N96693, - output _N96775, - output _N96780, - output _N107965, - output _N108056, + output _N82491, + output _N96654, + output _N96657, + output _N97535, + output _N97554, + output error_en, output rec_en, output rec_pkt_done, output rec_pkt_start, output skip_en, - output \udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N559 + output \udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1269 ); + wire N72; wire N90; wire N119; wire N175; @@ -361533,7 +360991,9 @@ module udp_rx wire N323; wire N374; wire N376; + wire N431; wire N432; + wire N433; wire N434; wire N460; wire N580; @@ -361553,72 +361013,72 @@ module udp_rx wire N859; wire N878; wire N889; - wire _N10578; - wire _N16555; - wire _N16556; - wire _N16557; - wire _N16558; - wire _N16559; - wire _N16560; - wire _N16561; - wire _N16562; - wire _N16563; - wire _N16564; - wire _N16565; - wire _N16566; - wire _N16567; - wire _N16568; + wire _N10592; + wire _N16101; + wire _N16102; + wire _N16103; + wire _N16104; + wire _N16105; + wire _N16106; + wire _N16107; + wire _N16108; + wire _N16109; + wire _N16110; + wire _N16111; + wire _N16112; + wire _N16113; + wire _N16114; wire _N18510; wire _N26584; wire _N26589; wire _N26601; wire _N26602; wire _N30726; - wire _N81655; - wire _N84440; - wire _N84443; - wire _N84536; - wire _N96777; - wire _N96779; - wire _N103307; - wire _N104125; - wire _N104141; - wire _N104145; - wire _N104149; - wire _N104153; - wire _N104157; - wire _N104172; - wire _N104176; - wire _N104180; - wire _N104184; - wire _N104188; - wire _N104192; - wire _N104195; - wire _N104199; - wire _N104204; - wire _N104209; - wire _N104213; - wire _N104217; - wire _N104221; - wire _N104225; - wire _N104227; - wire _N104229; - wire _N104232; - wire _N104237; - wire _N104241; - wire _N104245; - wire _N104249; - wire _N104252; - wire _N104255; - wire _N104267; - wire _N104270; - wire _N107971; - wire _N107972; + wire _N85237; + wire _N85240; + wire _N85340; + wire _N96655; + wire _N97357; + wire _N97541; + wire _N97553; + wire _N104119; + wire _N104964; + wire _N104980; + wire _N104984; + wire _N104988; + wire _N104992; + wire _N104996; + wire _N105011; + wire _N105015; + wire _N105019; + wire _N105023; + wire _N105027; + wire _N105031; + wire _N105034; + wire _N105038; + wire _N105044; + wire _N105047; + wire _N105052; + wire _N105056; + wire _N105060; + wire _N105064; + wire _N105066; + wire _N105068; + wire _N105071; + wire _N105076; + wire _N105080; + wire _N105084; + wire _N105088; + wire _N105091; + wire _N105094; + wire _N105106; + wire _N105109; + wire _N108801; + wire _N108802; wire [15:0] data_byte_num; wire [15:0] data_cnt; wire [31:0] des_ip; wire [47:0] des_mac; - wire error_en; wire [15:0] eth_type; wire [15:0] udp_byte_num; wire \udp_byte_num[3]_inv ; @@ -361626,71 +361086,70 @@ module udp_rx GTP_LUT3 /* N70_ac2 */ #( .INIT(8'b10000000)) N70_ac2 ( - .Z (_N10578), + .Z (_N10592), .I0 (cnt[0]), .I1 (cnt[1]), .I2 (cnt[2])); // LUT = I0&I1&I2 ; - GTP_LUT4 /* N72_mux3_3 */ #( - .INIT(16'b0000000000001000)) - N72_mux3_3 ( - .Z (_N96775), - .I0 (\udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt [1] ), - .I1 (\udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt [2] ), - .I2 (\udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt [3] ), - .I3 (\udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt [4] )); - // LUT = I0&I1&~I2&~I3 ; + GTP_LUT4 /* N72_mux3 */ #( + .INIT(16'b0000000000000111)) + N72_mux3 ( + .Z (N72), + .I0 (cnt[1]), + .I1 (cnt[2]), + .I2 (cnt[3]), + .I3 (cnt[4])); + // LUT = (~I1&~I2&~I3)|(~I0&~I2&~I3) ; - GTP_LUT5M /* N90 */ #( - .INIT(32'b10100010101010101010101010100010)) + GTP_LUT5 /* N90 */ #( + .INIT(32'b11111111110111111111110100000000)) N90_vname ( .Z (N90), - .I0 (_N96096), - .I1 (_N97473), - .I2 (gmii_rxd_data[5]), - .I3 (gmii_rxd_data[7]), - .I4 (_N96072), - .ID (_N95923)); + .I0 (_N98258), + .I1 (gmii_rxd_data[5]), + .I2 (gmii_rxd_data[7]), + .I3 (N72), + .I4 (N374)); // defparam N90_vname.orig_name = N90; - // LUT = (ID&I3&~I4)|(ID&I2&~I4)|(ID&~I1&~I4)|(I0&~I3&I4)|(I0&I2&I4)|(I0&~I1&I4) ; + // LUT = (~I2&I4)|(~I0&I3)|(~I0&I4)|(I1&I3)|(I1&I4)|(I2&I3) ; // ../../sources/designs/udp_osd/eth_udp/udp/udp_rx.v:133 GTP_LUT5 /* N113_15 */ #( .INIT(32'b11111111100000001000000010000000)) N113_15 ( - .Z (_N84536), - .I0 (_N104176), - .I1 (_N104195), - .I2 (_N104199), - .I3 (_N104229), - .I4 (_N104232)); + .Z (_N85340), + .I0 (_N105015), + .I1 (_N105034), + .I2 (_N105038), + .I3 (_N105068), + .I4 (_N105071)); // LUT = (I3&I4)|(I0&I1&I2) ; - GTP_LUT3 /* N113_16_5 */ #( - .INIT(8'b00000001)) - N113_16_5 ( - .Z (_N104204), + GTP_LUT5 /* N113_16_6 */ #( + .INIT(32'b00000000000000000000000000000001)) + N113_16_6 ( + .Z (_N105044), .I0 (des_mac[42]), .I1 (des_mac[43]), - .I2 (des_mac[46])); - // LUT = ~I0&~I1&~I2 ; + .I2 (des_mac[44]), + .I3 (des_mac[45]), + .I4 (des_mac[46])); + // LUT = ~I0&~I1&~I2&~I3&~I4 ; - GTP_LUT5 /* N113_16_10 */ #( - .INIT(32'b00000000000000000000000000000001)) - N113_16_10 ( - .Z (_N104209), + GTP_LUT3 /* N113_16_9 */ #( + .INIT(8'b00000001)) + N113_16_9 ( + .Z (_N105047), .I0 (des_mac[1]), - .I1 (des_mac[3]), - .I2 (des_mac[5]), - .I3 (des_mac[7]), - .I4 (des_mac[47])); - // LUT = ~I0&~I1&~I2&~I3&~I4 ; + .I1 (des_mac[7]), + .I2 (des_mac[47])); + // LUT = ~I0&~I1&~I2 ; GTP_LUT5 /* N113_16_14 */ #( .INIT(32'b00000000000000000000000000000001)) N113_16_14 ( - .Z (_N104213), + .Z (_N105052), .I0 (des_mac[8]), .I1 (des_mac[9]), .I2 (des_mac[11]), @@ -361701,7 +361160,7 @@ module udp_rx GTP_LUT5 /* N113_16_18 */ #( .INIT(32'b00000000000000000000000000000001)) N113_16_18 ( - .Z (_N104217), + .Z (_N105056), .I0 (des_mac[15]), .I1 (des_mac[18]), .I2 (des_mac[19]), @@ -361712,7 +361171,7 @@ module udp_rx GTP_LUT5 /* N113_16_22 */ #( .INIT(32'b00000000000000000000000000000001)) N113_16_22 ( - .Z (_N104221), + .Z (_N105060), .I0 (des_mac[24]), .I1 (des_mac[26]), .I2 (des_mac[27]), @@ -361723,7 +361182,7 @@ module udp_rx GTP_LUT5 /* N113_16_26 */ #( .INIT(32'b00000000000000000000000000000001)) N113_16_26 ( - .Z (_N104225), + .Z (_N105064), .I0 (des_mac[31]), .I1 (des_mac[33]), .I2 (des_mac[34]), @@ -361734,7 +361193,7 @@ module udp_rx GTP_LUT4 /* N113_16_28 */ #( .INIT(16'b0000000000000001)) N113_16_28 ( - .Z (_N104227), + .Z (_N105066), .I0 (des_mac[38]), .I1 (des_mac[39]), .I2 (des_mac[40]), @@ -361742,30 +361201,30 @@ module udp_rx // LUT = ~I0&~I1&~I2&~I3 ; GTP_LUT5 /* N113_16_30 */ #( - .INIT(32'b00000000000000000000000010000000)) + .INIT(32'b00010000000000000000000000000000)) N113_16_30 ( - .Z (_N104229), - .I0 (_N104204), - .I1 (_N104209), - .I2 (_N104227), - .I3 (des_mac[44]), - .I4 (des_mac[45])); - // LUT = I0&I1&I2&~I3&~I4 ; + .Z (_N105068), + .I0 (des_mac[3]), + .I1 (des_mac[5]), + .I2 (_N105044), + .I3 (_N105047), + .I4 (_N105066)); + // LUT = ~I0&~I1&I2&I3&I4 ; GTP_LUT4 /* N113_16_33 */ #( .INIT(16'b1000000000000000)) N113_16_33 ( - .Z (_N104232), - .I0 (_N104213), - .I1 (_N104217), - .I2 (_N104221), - .I3 (_N104225)); + .Z (_N105071), + .I0 (_N105052), + .I1 (_N105056), + .I2 (_N105060), + .I3 (_N105064)); // LUT = I0&I1&I2&I3 ; GTP_LUT5 /* N113_17_6 */ #( .INIT(32'b10000000000000000000000000000000)) N113_17_6 ( - .Z (_N104172), + .Z (_N105011), .I0 (des_mac[42]), .I1 (des_mac[43]), .I2 (des_mac[44]), @@ -361776,7 +361235,7 @@ module udp_rx GTP_LUT5 /* N113_17_10 */ #( .INIT(32'b10000000000000000000000000000000)) N113_17_10 ( - .Z (_N104176), + .Z (_N105015), .I0 (des_mac[1]), .I1 (des_mac[3]), .I2 (des_mac[5]), @@ -361787,7 +361246,7 @@ module udp_rx GTP_LUT5 /* N113_17_14 */ #( .INIT(32'b10000000000000000000000000000000)) N113_17_14 ( - .Z (_N104180), + .Z (_N105019), .I0 (des_mac[8]), .I1 (des_mac[9]), .I2 (des_mac[11]), @@ -361798,7 +361257,7 @@ module udp_rx GTP_LUT5 /* N113_17_18 */ #( .INIT(32'b10000000000000000000000000000000)) N113_17_18 ( - .Z (_N104184), + .Z (_N105023), .I0 (des_mac[15]), .I1 (des_mac[18]), .I2 (des_mac[19]), @@ -361809,7 +361268,7 @@ module udp_rx GTP_LUT5 /* N113_17_22 */ #( .INIT(32'b10000000000000000000000000000000)) N113_17_22 ( - .Z (_N104188), + .Z (_N105027), .I0 (des_mac[24]), .I1 (des_mac[26]), .I2 (des_mac[27]), @@ -361820,7 +361279,7 @@ module udp_rx GTP_LUT5 /* N113_17_26 */ #( .INIT(32'b10000000000000000000000000000000)) N113_17_26 ( - .Z (_N104192), + .Z (_N105031), .I0 (des_mac[31]), .I1 (des_mac[33]), .I2 (des_mac[34]), @@ -361831,28 +361290,28 @@ module udp_rx GTP_LUT5 /* N113_17_29 */ #( .INIT(32'b10000000000000000000000000000000)) N113_17_29 ( - .Z (_N104195), - .I0 (_N104172), - .I1 (des_mac[38]), - .I2 (des_mac[39]), - .I3 (des_mac[40]), - .I4 (des_mac[41])); + .Z (_N105034), + .I0 (des_mac[38]), + .I1 (des_mac[39]), + .I2 (des_mac[40]), + .I3 (des_mac[41]), + .I4 (_N105011)); // LUT = I0&I1&I2&I3&I4 ; GTP_LUT4 /* N113_17_33 */ #( .INIT(16'b1000000000000000)) N113_17_33 ( - .Z (_N104199), - .I0 (_N104180), - .I1 (_N104184), - .I2 (_N104188), - .I3 (_N104192)); + .Z (_N105038), + .I0 (_N105019), + .I1 (_N105023), + .I2 (_N105027), + .I3 (_N105031)); // LUT = I0&I1&I2&I3 ; GTP_LUT5 /* N119_29 */ #( .INIT(32'b00000000000000000000000000000001)) N119_29 ( - .Z (_N104237), + .Z (_N105076), .I0 (eth_type[8]), .I1 (eth_type[9]), .I2 (eth_type[10]), @@ -361863,7 +361322,7 @@ module udp_rx GTP_LUT5 /* N119_33 */ #( .INIT(32'b00000000000000000000000010000000)) N119_33 ( - .Z (_N104241), + .Z (_N105080), .I0 (des_mac[0]), .I1 (des_mac[2]), .I2 (eth_type[11]), @@ -361874,7 +361333,7 @@ module udp_rx GTP_LUT5 /* N119_37 */ #( .INIT(32'b10000000000000000000000000000000)) N119_37 ( - .Z (_N104245), + .Z (_N105084), .I0 (des_mac[4]), .I1 (des_mac[6]), .I2 (des_mac[10]), @@ -361885,7 +361344,7 @@ module udp_rx GTP_LUT5 /* N119_41 */ #( .INIT(32'b10000000000000000000000000000000)) N119_41 ( - .Z (_N104249), + .Z (_N105088), .I0 (des_mac[17]), .I1 (des_mac[20]), .I2 (des_mac[21]), @@ -361896,8 +361355,8 @@ module udp_rx GTP_LUT5 /* N119_44 */ #( .INIT(32'b00000010000000000000000000000000)) N119_44 ( - .Z (_N104252), - .I0 (_N84536), + .Z (_N105091), + .I0 (_N85340), .I1 (gmii_rxd_data[1]), .I2 (gmii_rxd_data[3]), .I3 (des_mac[32]), @@ -361907,28 +361366,28 @@ module udp_rx GTP_LUT4 /* N119_47 */ #( .INIT(16'b0000001000000000)) N119_47 ( - .Z (_N104255), - .I0 (_N96556), + .Z (_N105094), + .I0 (_N97327), .I1 (gmii_rxd_data[0]), .I2 (gmii_rxd_data[4]), - .I3 (_N104249)); + .I3 (_N105088)); // LUT = I0&~I1&~I2&I3 ; GTP_LUT5 /* N119_49 */ #( .INIT(32'b10000000000000000000000000000000)) N119_49 ( .Z (N119), - .I0 (_N104237), - .I1 (_N104241), - .I2 (_N104245), - .I3 (_N104252), - .I4 (_N104255)); + .I0 (_N105076), + .I1 (_N105080), + .I2 (_N105084), + .I3 (_N105091), + .I4 (_N105094)); // LUT = I0&I1&I2&I3&I4 ; GTP_LUT5 /* N175_30 */ #( .INIT(32'b00000000000000000000000000000001)) N175_30 ( - .Z (_N104141), + .Z (_N104980), .I0 (des_ip[16]), .I1 (des_ip[17]), .I2 (des_ip[18]), @@ -361939,7 +361398,7 @@ module udp_rx GTP_LUT5 /* N175_34 */ #( .INIT(32'b00000001000000000000000000000000)) N175_34 ( - .Z (_N104145), + .Z (_N104984), .I0 (des_ip[0]), .I1 (des_ip[2]), .I2 (des_ip[21]), @@ -361950,7 +361409,7 @@ module udp_rx GTP_LUT5 /* N175_38 */ #( .INIT(32'b00000000000000000000000000000001)) N175_38 ( - .Z (_N104149), + .Z (_N104988), .I0 (des_ip[4]), .I1 (des_ip[5]), .I2 (des_ip[6]), @@ -361961,7 +361420,7 @@ module udp_rx GTP_LUT5 /* N175_42 */ #( .INIT(32'b00000000000000000000000000000010)) N175_42 ( - .Z (_N104153), + .Z (_N104992), .I0 (des_ip[1]), .I1 (des_ip[9]), .I2 (des_ip[10]), @@ -361972,31 +361431,31 @@ module udp_rx GTP_LUT5 /* N175_46 */ #( .INIT(32'b10000000000000000000000000000000)) N175_46 ( - .Z (_N104157), - .I0 (_N104141), - .I1 (des_ip[3]), - .I2 (des_ip[11]), - .I3 (des_ip[13]), - .I4 (des_ip[15])); + .Z (_N104996), + .I0 (des_ip[3]), + .I1 (des_ip[11]), + .I2 (des_ip[13]), + .I3 (des_ip[15]), + .I4 (_N104980)); // LUT = I0&I1&I2&I3&I4 ; GTP_LUT5 /* N175_50 */ #( .INIT(32'b10000000000000000000000000000000)) N175_50 ( .Z (N175), - .I0 (_N98508), - .I1 (_N104145), - .I2 (_N104149), - .I3 (_N104153), - .I4 (_N104157)); + .I0 (_N100572), + .I1 (_N104984), + .I2 (_N104988), + .I3 (_N104992), + .I4 (_N104996)); // LUT = I0&I1&I2&I3&I4 ; GTP_LUT5 /* \N191_and[0] */ #( .INIT(32'b01111111000011110111011100000000)) \N191_and[0] ( .Z (_N30726), - .I0 (_N96556), - .I1 (_N97006), + .I0 (_N97327), + .I1 (_N97887), .I2 (N175), .I3 (N432), .I4 (N434)); @@ -362249,7 +361708,7 @@ module udp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N274_1_1 ( - .COUT (_N16555), + .COUT (_N16101), .Z (N763[1]), .CIN (), .I0 (data_cnt[0]), @@ -362269,9 +361728,9 @@ module udp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N274_1_2 ( - .COUT (_N16556), + .COUT (_N16102), .Z (N763[2]), - .CIN (_N16555), + .CIN (_N16101), .I0 (data_cnt[0]), .I1 (data_cnt[1]), .I2 (N277), @@ -362289,9 +361748,9 @@ module udp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N274_1_3 ( - .COUT (_N16557), + .COUT (_N16103), .Z (N763[3]), - .CIN (_N16556), + .CIN (_N16102), .I0 (), .I1 (data_cnt[3]), .I2 (N277), @@ -362309,9 +361768,9 @@ module udp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N274_1_4 ( - .COUT (_N16558), + .COUT (_N16104), .Z (N763[4]), - .CIN (_N16557), + .CIN (_N16103), .I0 (), .I1 (data_cnt[4]), .I2 (N277), @@ -362329,9 +361788,9 @@ module udp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N274_1_5 ( - .COUT (_N16559), + .COUT (_N16105), .Z (N763[5]), - .CIN (_N16558), + .CIN (_N16104), .I0 (), .I1 (data_cnt[5]), .I2 (N277), @@ -362349,9 +361808,9 @@ module udp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N274_1_6 ( - .COUT (_N16560), + .COUT (_N16106), .Z (N763[6]), - .CIN (_N16559), + .CIN (_N16105), .I0 (), .I1 (data_cnt[6]), .I2 (N277), @@ -362369,9 +361828,9 @@ module udp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N274_1_7 ( - .COUT (_N16561), + .COUT (_N16107), .Z (N763[7]), - .CIN (_N16560), + .CIN (_N16106), .I0 (), .I1 (data_cnt[7]), .I2 (N277), @@ -362389,9 +361848,9 @@ module udp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N274_1_8 ( - .COUT (_N16562), + .COUT (_N16108), .Z (N763[8]), - .CIN (_N16561), + .CIN (_N16107), .I0 (), .I1 (data_cnt[8]), .I2 (N277), @@ -362409,9 +361868,9 @@ module udp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N274_1_9 ( - .COUT (_N16563), + .COUT (_N16109), .Z (N763[9]), - .CIN (_N16562), + .CIN (_N16108), .I0 (), .I1 (data_cnt[9]), .I2 (N277), @@ -362429,9 +361888,9 @@ module udp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N274_1_10 ( - .COUT (_N16564), + .COUT (_N16110), .Z (N763[10]), - .CIN (_N16563), + .CIN (_N16109), .I0 (), .I1 (data_cnt[10]), .I2 (N277), @@ -362449,9 +361908,9 @@ module udp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N274_1_11 ( - .COUT (_N16565), + .COUT (_N16111), .Z (N763[11]), - .CIN (_N16564), + .CIN (_N16110), .I0 (), .I1 (data_cnt[11]), .I2 (N277), @@ -362469,9 +361928,9 @@ module udp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N274_1_12 ( - .COUT (_N16566), + .COUT (_N16112), .Z (N763[12]), - .CIN (_N16565), + .CIN (_N16111), .I0 (), .I1 (data_cnt[12]), .I2 (N277), @@ -362489,9 +361948,9 @@ module udp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N274_1_13 ( - .COUT (_N16567), + .COUT (_N16113), .Z (N763[13]), - .CIN (_N16566), + .CIN (_N16112), .I0 (), .I1 (data_cnt[13]), .I2 (N277), @@ -362509,9 +361968,9 @@ module udp_rx .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N274_1_14 ( - .COUT (_N16568), + .COUT (_N16114), .Z (N763[14]), - .CIN (_N16567), + .CIN (_N16113), .I0 (), .I1 (data_cnt[14]), .I2 (N277), @@ -362531,7 +361990,7 @@ module udp_rx N274_1_15 ( .COUT (), .Z (N763[15]), - .CIN (_N16568), + .CIN (_N16114), .I0 (), .I1 (data_cnt[15]), .I2 (N277), @@ -363008,38 +362467,26 @@ module udp_rx .Z (_N26584), .I0 (cur_state_reg[0]), .I1 (cur_state_reg[1]), - .I2 (_N96385), + .I2 (_N97357), .I3 (N64), .I4 (skip_en), .ID (error_en)); // LUT = (~I1&I2&I3&~I4)|(ID&I2&I3&~I4)|(~I0&I2&I3&I4) ; - GTP_LUT4 /* N308_7 */ #( - .INIT(16'b0000000100001101)) - N308_7 ( - .Z (_N95844), - .I0 (_N81655), - .I1 (skip_en), - .I2 (cur_state_reg[5]), - .I3 (cur_state_reg[4])); - // LUT = (I1&~I2&~I3)|(~I0&~I1&~I2) ; - - GTP_LUT5 /* N308_11_3 */ #( - .INIT(32'b10000000000000000000000000000000)) + GTP_LUT3 /* N308_11_3 */ #( + .INIT(8'b10000000)) N308_11_3 ( .Z (_N26589), - .I0 (_N96096), - .I1 (_N96385), - .I2 (_N96693), - .I3 (cnt[1]), - .I4 (cnt[2])); - // LUT = I0&I1&I2&I3&I4 ; + .I0 (_N97357), + .I1 (_N97535), + .I2 (N374)); + // LUT = I0&I1&I2 ; GTP_LUT5 /* N308_15_3 */ #( .INIT(32'b00000000000000000000000010000000)) N308_15_3 ( - .Z (_N104267), - .I0 (_N95844), + .Z (_N105106), + .I0 (_N96653), .I1 (gmii_rxd_valid), .I2 (N889), .I3 (next_state[3]), @@ -363049,9 +362496,9 @@ module udp_rx GTP_LUT5M /* N308_18_3 */ #( .INIT(32'b01000000000000000100000000000000)) N308_18_3 ( - .Z (_N104270), + .Z (_N105109), .I0 (cur_state_reg[3]), - .I1 (_N95844), + .I1 (_N96653), .I2 (gmii_rxd_valid), .I3 (N434), .I4 (skip_en), @@ -363063,47 +362510,49 @@ module udp_rx N308_24 ( .Z (_N26602), .I0 (_N26601), - .I1 (_N95844), + .I1 (_N96653), .I2 (gmii_rxd_valid), .I3 (N460), .I4 (next_state[4])); // LUT = (I0&~I4)|(I1&I2&I3&I4) ; GTP_LUT5M /* N308_28 */ #( - .INIT(32'b11100010001000101010101010101010)) + .INIT(32'b11001010000010101010101010101010)) N308_28 ( .Z (N308), .I0 (_N26602), - .I1 (next_state[3]), - .I2 (N175), - .I3 (_N104270), - .I4 (_N107971), - .ID (_N107972)); - // LUT = (ID&~I4)|(I1&I2&I3&I4)|(I0&~I1&I4) ; + .I1 (_N105109), + .I2 (next_state[3]), + .I3 (N175), + .I4 (_N108801), + .ID (_N108802)); + // LUT = (ID&~I4)|(I1&I2&I3&I4)|(I0&~I2&I4) ; - GTP_LUT2 /* N308_31 */ #( - .INIT(4'b1000)) + GTP_LUT4 /* N308_31 */ #( + .INIT(16'b0000100000000000)) N308_31 ( - .Z (\udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N559 ), - .I0 (gmii_rxd_valid), - .I1 (\udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N366 )); - // LUT = I0&I1 ; + .Z (_N97535), + .I0 (_N98258), + .I1 (gmii_rxd_valid), + .I2 (gmii_rxd_data[5]), + .I3 (gmii_rxd_data[7])); + // LUT = I0&I1&~I2&I3 ; - GTP_LUT5 /* N308_32 */ #( - .INIT(32'b00000000000000000000000000000001)) - N308_32 ( - .Z (_N96777), - .I0 (next_state[0]), - .I1 (next_state[1]), + GTP_LUT5 /* N308_65 */ #( + .INIT(32'b00000000000000000000001000000000)) + N308_65 ( + .Z (_N97541), + .I0 (_N97341), + .I1 (N431), .I2 (next_state[2]), .I3 (next_state[3]), .I4 (next_state[4])); - // LUT = ~I0&~I1&~I2&~I3&~I4 ; + // LUT = I0&~I1&~I2&I3&~I4 ; - GTP_LUT5M /* N308_68 */ #( + GTP_LUT5M /* N308_70 */ #( .INIT(32'b00000001000000010000101000001011)) - N308_68 ( - .Z (_N107971), + N308_70 ( + .Z (_N108801), .I0 (cur_state_reg[6]), .I1 (cur_state_reg[1]), .I2 (cur_state_reg[0]), @@ -363112,45 +362561,45 @@ module udp_rx .ID (error_en)); // LUT = (~I1&~I2&~I3&~I4)|(ID&~I2&~I4)|(~I0&~I1&~I2&I4) ; - GTP_LUT5M /* N308_69 */ #( - .INIT(32'b10101010101010101010101011000000)) - N308_69 ( - .Z (_N107972), + GTP_LUT5M /* N308_71 */ #( + .INIT(32'b10101010101010101010110010100000)) + N308_71 ( + .Z (_N108802), .I0 (_N26584), .I1 (N119), - .I2 (_N104267), - .I3 (next_state[1]), + .I2 (next_state[1]), + .I3 (_N105106), .I4 (next_state[0]), .ID (_N26589)); - // LUT = (I1&I2&~I3&~I4)|(ID&I3&~I4)|(I0&I4) ; + // LUT = (I1&~I2&I3&~I4)|(ID&I2&~I4)|(I0&I4) ; - GTP_LUT5M /* N308_70 */ #( + GTP_LUT5M /* N308_72 */ #( .INIT(32'b00001000000000000100001000000010)) - N308_70 ( + N308_72 ( .Z (_N26601), .I0 (cur_state_reg[4]), .I1 (gmii_rxd_valid), .I2 (cur_state_reg[5]), .I3 (N277), .I4 (skip_en), - .ID (_N81655)); + .ID (_N82491)); // LUT = (~ID&I1&I2&I3&~I4)|(ID&~I1&~I2&~I4)|(I0&I1&~I2&I3&I4) ; GTP_LUT5 /* \N310_1_or[0]_1 */ #( .INIT(32'b11111110111011101010101010101010)) \N310_1_or[0]_1 ( .Z (N310), - .I0 (_N84440), - .I1 (_N84443), + .I0 (_N85237), + .I1 (_N85240), .I2 (_N30726), - .I3 (_N96774), + .I3 (_N97541), .I4 (gmii_rxd_valid)); // LUT = (I0)|(I1&I4)|(I2&I3&I4) ; GTP_LUT4 /* \N310_1_or[0]_2_3 */ #( .INIT(16'b0010000000000000)) \N310_1_or[0]_2_3 ( - .Z (_N84440), + .Z (_N85237), .I0 (gmii_rxd_valid), .I1 (N119), .I2 (N376), @@ -363160,62 +362609,52 @@ module udp_rx GTP_LUT5M /* \N310_1_or[0]_5 */ #( .INIT(32'b01000000000000000100000000000000)) \N310_1_or[0]_5 ( - .Z (_N84443), + .Z (_N85240), .I0 (cur_state_reg[6]), .I1 (N90), .I2 (next_state[1]), - .I3 (_N96385), + .I3 (_N97357), .I4 (skip_en), .ID (cur_state_reg[0])); // LUT = (~ID&I1&I2&I3&~I4)|(~I0&I1&I2&I3&I4) ; - GTP_LUT5M /* \N310_1_or[0]_7 */ #( - .INIT(32'b00000101000000000000101100000000)) - \N310_1_or[0]_7 ( - .Z (_N96358), - .I0 (cur_state_reg[6]), - .I1 (cur_state_reg[1]), - .I2 (cur_state_reg[0]), - .I3 (_N95844), + GTP_LUT5M /* \N310_1_or[0]_8 */ #( + .INIT(32'b00000000000001000000000000000100)) + \N310_1_or[0]_8 ( + .Z (_N97357), + .I0 (cur_state_reg[3]), + .I1 (_N96653), + .I2 (next_state[2]), + .I3 (next_state[3]), .I4 (skip_en), - .ID (error_en)); - // LUT = (~I1&~I2&I3&~I4)|(ID&~I2&I3&~I4)|(~I0&~I2&I3&I4) ; + .ID (cur_state_reg[4])); + // LUT = (~ID&I1&~I2&~I3&~I4)|(~I0&I1&~I2&~I3&I4) ; - GTP_LUT4 /* \N310_1_or[0]_8 */ #( - .INIT(16'b0000100000000000)) - \N310_1_or[0]_8 ( - .Z (_N96693), - .I0 (_N97473), - .I1 (gmii_rxd_valid), - .I2 (gmii_rxd_data[5]), - .I3 (gmii_rxd_data[7])); - // LUT = I0&I1&~I2&I3 ; + GTP_LUT4 /* \N310_1_or[0]_9 */ #( + .INIT(16'b1000000000000000)) + \N310_1_or[0]_9 ( + .Z (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1269 ), + .I0 (_N96654), + .I1 (_N96787), + .I2 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1265 ), + .I3 (_N108899)); + // LUT = I0&I1&I2&I3 ; GTP_LUT4 /* N319_2_2 */ #( .INIT(16'b1000000000000000)) N319_2_2 ( .Z (N319), - .I0 (_N95923), + .I0 (_N96655), .I1 (N586), .I2 (cnt[1]), .I3 (cnt[2])); // LUT = I0&I1&I2&I3 ; - GTP_LUT4 /* N319_3 */ #( - .INIT(16'b0000000001000000)) - N319_3 ( - .Z (_N96779), - .I0 (cnt[1]), - .I1 (cnt[2]), - .I2 (cnt[3]), - .I3 (cnt[4])); - // LUT = ~I0&I1&I2&~I3 ; - GTP_LUT5 /* N323_2 */ #( .INIT(32'b00000000000000001000000000000000)) N323_2 ( .Z (N323), - .I0 (_N96777), + .I0 (_N97542), .I1 (gmii_rxd_valid), .I2 (N277), .I3 (next_state[5]), @@ -363241,24 +362680,25 @@ module udp_rx N376_5 ( .Z (N376), .I0 (cur_state_reg[3]), - .I1 (_N96358), + .I1 (_N97341), .I2 (next_state[2]), .I3 (next_state[3]), .I4 (skip_en), .ID (cur_state_reg[4])); // LUT = (~ID&I1&I2&~I3&~I4)|(~I0&I1&I2&~I3&I4) ; - GTP_LUT5M /* N429_4 */ #( - .INIT(32'b00010000000100000000000000000100)) - N429_4 ( - .Z (_N107965), - .I0 (cur_state_reg[1]), - .I1 (cur_state_reg[3]), - .I2 (cur_state_reg[2]), - .I3 (cur_state_reg[4]), - .I4 (skip_en), - .ID (error_en)); - // LUT = (~ID&I1&~I2&~I3&~I4)|(~I0&~I1&I2&I4) ; + GTP_LUT5 /* N431 */ #( + .INIT(32'b00000000000000000000000000000001)) + N431_vname ( + .Z (N431), + .I0 (cnt[0]), + .I1 (cnt[1]), + .I2 (cnt[2]), + .I3 (cnt[3]), + .I4 (cnt[4])); + // defparam N431_vname.orig_name = N431; + // LUT = ~I0&~I1&~I2&~I3&~I4 ; + // ../../sources/designs/udp_osd/eth_udp/udp/udp_rx.v:160 GTP_LUT5 /* N432_3 */ #( .INIT(32'b00000000000000000000001000000000)) @@ -363271,6 +362711,19 @@ module udp_rx .I4 (cnt[4])); // LUT = I0&~I1&~I2&I3&~I4 ; + GTP_LUT5 /* N433 */ #( + .INIT(32'b00000000000010000000000000000000)) + N433_vname ( + .Z (N433), + .I0 (_N97327), + .I1 (gmii_rxd_data[0]), + .I2 (gmii_rxd_data[1]), + .I3 (gmii_rxd_data[3]), + .I4 (gmii_rxd_data[4])); + // defparam N433_vname.orig_name = N433; + // LUT = I0&I1&~I2&~I3&I4 ; + // ../../sources/designs/udp_osd/eth_udp/udp/udp_rx.v:162 + GTP_LUT5 /* N434_4 */ #( .INIT(32'b00000000000010000000000000000000)) N434_4 ( @@ -363302,7 +362755,7 @@ module udp_rx .I0 (cur_state_reg[6]), .I1 (gmii_rxd_valid), .I2 (next_state[1]), - .I3 (_N96385), + .I3 (_N97357), .I4 (skip_en), .ID (cur_state_reg[0])); // LUT = (~ID&I1&I2&I3&~I4)|(~I0&I1&I2&I3&I4) ; @@ -363311,7 +362764,7 @@ module udp_rx .INIT(32'b00000000000000000000100000000000)) N584_4 ( .Z (N584), - .I0 (_N96358), + .I0 (_N97341), .I1 (gmii_rxd_valid), .I2 (next_state[2]), .I3 (next_state[3]), @@ -363363,7 +362816,7 @@ module udp_rx .INIT(32'b01000101010001001000101010001000)) \N591_12_or[3]_1 ( .Z (N591[3]), - .I0 (_N10578), + .I0 (_N10592), .I1 (_N18510), .I2 (N460), .I3 (N586), @@ -363374,7 +362827,7 @@ module udp_rx .INIT(32'b01010100111111001010100000000000)) \N591_12_or[4]_1 ( .Z (N591[4]), - .I0 (_N10578), + .I0 (_N10592), .I1 (_N18510), .I2 (N586), .I3 (cnt[3]), @@ -363384,7 +362837,7 @@ module udp_rx GTP_LUT5 /* N591_14_2 */ #( .INIT(32'b00110011000000001011001110100000)) N591_14_2 ( - .Z (_N104125), + .Z (_N104964), .I0 (gmii_rxd_valid), .I1 (N374), .I2 (N376), @@ -363392,99 +362845,124 @@ module udp_rx .I4 (N889)); // LUT = (~I1&I3)|(I0&I2&~I4) ; - GTP_LUT5M /* N591_14_3 */ #( - .INIT(32'b11101100110011001101110111001100)) + GTP_LUT5 /* N591_14_3 */ #( + .INIT(32'b11111111111111111000110100000000)) N591_14_3 ( .Z (_N18510), - .I0 (_N96556), - .I1 (_N104125), - .I2 (_N97006), + .I0 (N432), + .I1 (N433), + .I2 (N434), .I3 (N584), - .I4 (N432), - .ID (N434)); - // LUT = (~ID&I3&~I4)|(I0&I2&I3&I4)|(I1) ; + .I4 (_N104964)); + // LUT = (I4)|(~I0&~I2&I3)|(I0&I1&I3) ; GTP_LUT5 /* N602_3 */ #( .INIT(32'b00000000100000001000000010000000)) N602_3 ( .Z (N602), - .I0 (_N95923), + .I0 (_N96655), .I1 (gmii_rxd_valid), .I2 (N376), .I3 (cnt[1]), .I4 (cnt[2])); // LUT = (I0&I1&I2&~I4)|(I0&I1&I2&~I3) ; + GTP_LUT4 /* N630_1 */ #( + .INIT(16'b0000000001000000)) + N630_1 ( + .Z (_N97553), + .I0 (cnt[1]), + .I1 (cnt[2]), + .I2 (cnt[3]), + .I3 (cnt[4])); + // LUT = ~I0&I1&I2&~I3 ; + GTP_LUT4 /* N630_3 */ #( .INIT(16'b0000100000000000)) N630_3 ( .Z (N630), - .I0 (_N96096), + .I0 (_N97121), .I1 (N586), .I2 (cnt[1]), .I3 (cnt[2])); // LUT = I0&I1&~I2&I3 ; - GTP_LUT2 /* N630_4 */ #( - .INIT(4'b1000)) - N630_4 ( - .Z (_N108056), - .I0 (gmii_rxd_valid), - .I1 (\udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt [3] )); - // LUT = I0&I1 ; + GTP_LUT5 /* N665_1 */ #( + .INIT(32'b00000000000000010000000011001101)) + N665_1 ( + .Z (_N96654), + .I0 (_N82337), + .I1 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/skip_en ), + .I2 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg [6] ), + .I3 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg [5] ), + .I4 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg [4] )); + // LUT = (I1&~I3&~I4)|(~I0&~I1&~I2&~I3) ; - GTP_LUT5 /* N665_6 */ #( + GTP_LUT5 /* N665_7 */ #( .INIT(32'b00000000000010000000000000000000)) - N665_6 ( + N665_7 ( .Z (N665), - .I0 (_N96774), + .I0 (_N97541), .I1 (gmii_rxd_valid), .I2 (cnt[2]), .I3 (cnt[3]), .I4 (cnt[4])); // LUT = I0&I1&~I2&~I3&I4 ; - GTP_LUT5 /* N697_2 */ #( - .INIT(32'b00000000100000000000000000000000)) - N697_2 ( - .Z (N697), - .I0 (_N95923), - .I1 (N586), - .I2 (cnt[0]), - .I3 (cnt[1]), - .I4 (cnt[2])); - // LUT = I0&I1&I2&~I3&I4 ; + GTP_LUT2 /* N697_1 */ #( + .INIT(4'b0001)) + N697_1 ( + .Z (_N96655), + .I0 (cnt[3]), + .I1 (cnt[4])); + // LUT = ~I0&~I1 ; - GTP_LUT4 /* N710_1 */ #( + GTP_LUT4 /* N697_3 */ #( .INIT(16'b0000000001000000)) - N710_1 ( - .Z (_N96780), + N697_3 ( + .Z (_N97554), .I0 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt [1] ), .I1 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt [2] ), .I2 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt [3] ), .I3 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt [4] )); // LUT = ~I0&I1&I2&~I3 ; - GTP_LUT4 /* N710_3 */ #( + GTP_LUT4 /* N697_5 */ #( + .INIT(16'b0000100000000000)) + N697_5 ( + .Z (N697), + .I0 (_N97122), + .I1 (N586), + .I2 (cnt[1]), + .I3 (cnt[2])); + // LUT = I0&I1&~I2&I3 ; + + GTP_LUT2 /* N710_1 */ #( + .INIT(4'b0001)) + N710_1 ( + .Z (_N96657), + .I0 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt [3] ), + .I1 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt [4] )); + // LUT = ~I0&~I1 ; + + GTP_LUT4 /* N710_4 */ #( .INIT(16'b0000000010000000)) - N710_3 ( + N710_4 ( .Z (N710), - .I0 (_N96096), + .I0 (_N97121), .I1 (N586), .I2 (cnt[1]), .I3 (cnt[2])); // LUT = I0&I1&I2&~I3 ; - GTP_LUT4 /* N748 */ #( - .INIT(16'b1000000000000000)) + GTP_LUT2 /* N748 */ #( + .INIT(4'b1000)) N748_vname ( .Z (N748), - .I0 (_N96096), - .I1 (N586), - .I2 (cnt[1]), - .I3 (cnt[2])); + .I0 (N374), + .I1 (N586)); // defparam N748_vname.orig_name = N748; - // LUT = I0&I1&I2&I3 ; + // LUT = I0&I1 ; GTP_LUT5M /* N757 */ #( .INIT(32'b00000000100000000000000010000000)) @@ -363492,7 +362970,7 @@ module udp_rx .Z (N757), .I0 (cur_state_reg[4]), .I1 (gmii_rxd_valid), - .I2 (_N96777), + .I2 (_N97542), .I3 (next_state[6]), .I4 (skip_en), .ID (cur_state_reg[5])); @@ -363509,199 +362987,212 @@ module udp_rx // LUT = ~I0&~I1 ; // ../../sources/designs/udp_osd/eth_udp/udp/udp_rx.v:101 - GTP_LUT5 /* N839 */ #( - .INIT(32'b11101100110011001100110011001100)) + GTP_LUT3 /* N839 */ #( + .INIT(8'b11101010)) N839_vname ( .Z (N839), - .I0 (_N96096), - .I1 (N323), - .I2 (N586), - .I3 (cnt[1]), - .I4 (cnt[2])); + .I0 (N323), + .I1 (N374), + .I2 (N586)); // defparam N839_vname.orig_name = N839; - // LUT = (I1)|(I0&I2&I3&I4) ; + // LUT = (I0)|(I1&I2) ; // ../../sources/designs/udp_osd/eth_udp/udp/udp_rx.v:124 - GTP_LUT3 /* \N842_1[0] */ #( - .INIT(8'b11100100)) + GTP_LUT4 /* \N842_1[0] */ #( + .INIT(16'b1111100001110000)) \N842_1[0] ( .Z (N842[0]), - .I0 (N748), - .I1 (data_byte_num[0]), - .I2 (udp_byte_num[0])); - // LUT = (~I0&I1)|(I0&I2) ; + .I0 (N374), + .I1 (N586), + .I2 (data_byte_num[0]), + .I3 (udp_byte_num[0])); + // LUT = (~I1&I2)|(~I0&I2)|(I0&I1&I3) ; // ../../sources/designs/udp_osd/eth_udp/udp/udp_rx.v:124 - GTP_LUT3 /* \N842_1[1] */ #( - .INIT(8'b11100100)) + GTP_LUT4 /* \N842_1[1] */ #( + .INIT(16'b1111100001110000)) \N842_1[1] ( .Z (N842[1]), - .I0 (N748), - .I1 (data_byte_num[1]), - .I2 (udp_byte_num[1])); - // LUT = (~I0&I1)|(I0&I2) ; + .I0 (N374), + .I1 (N586), + .I2 (data_byte_num[1]), + .I3 (udp_byte_num[1])); + // LUT = (~I1&I2)|(~I0&I2)|(I0&I1&I3) ; // ../../sources/designs/udp_osd/eth_udp/udp/udp_rx.v:124 - GTP_LUT3 /* \N842_1[2] */ #( - .INIT(8'b11100100)) + GTP_LUT4 /* \N842_1[2] */ #( + .INIT(16'b1111100001110000)) \N842_1[2] ( .Z (N842[2]), - .I0 (N748), - .I1 (data_byte_num[2]), - .I2 (udp_byte_num[2])); - // LUT = (~I0&I1)|(I0&I2) ; + .I0 (N374), + .I1 (N586), + .I2 (data_byte_num[2]), + .I3 (udp_byte_num[2])); + // LUT = (~I1&I2)|(~I0&I2)|(I0&I1&I3) ; // ../../sources/designs/udp_osd/eth_udp/udp/udp_rx.v:124 - GTP_LUT3 /* \N842_1[3] */ #( - .INIT(8'b01001110)) + GTP_LUT4 /* \N842_1[3] */ #( + .INIT(16'b0111000011111000)) \N842_1[3] ( .Z (N842[3]), - .I0 (N748), - .I1 (data_byte_num[3]), - .I2 (udp_byte_num[3])); - // LUT = (I0&~I2)|(~I0&I1) ; + .I0 (N374), + .I1 (N586), + .I2 (data_byte_num[3]), + .I3 (udp_byte_num[3])); + // LUT = (~I1&I2)|(~I0&I2)|(I0&I1&~I3) ; // ../../sources/designs/udp_osd/eth_udp/udp/udp_rx.v:124 - GTP_LUT3 /* \N842_1[4] */ #( - .INIT(8'b11011000)) + GTP_LUT4 /* \N842_1[4] */ #( + .INIT(16'b1111011110000000)) \N842_1[4] ( .Z (N842[4]), - .I0 (N748), - .I1 (N223[4]), - .I2 (data_byte_num[4])); - // LUT = (~I0&I2)|(I0&I1) ; + .I0 (N374), + .I1 (N586), + .I2 (N223[4]), + .I3 (data_byte_num[4])); + // LUT = (~I1&I3)|(~I0&I3)|(I0&I1&I2) ; // ../../sources/designs/udp_osd/eth_udp/udp/udp_rx.v:124 - GTP_LUT3 /* \N842_1[5] */ #( - .INIT(8'b11011000)) + GTP_LUT4 /* \N842_1[5] */ #( + .INIT(16'b1111011110000000)) \N842_1[5] ( .Z (N842[5]), - .I0 (N748), - .I1 (N223[5]), - .I2 (data_byte_num[5])); - // LUT = (~I0&I2)|(I0&I1) ; + .I0 (N374), + .I1 (N586), + .I2 (N223[5]), + .I3 (data_byte_num[5])); + // LUT = (~I1&I3)|(~I0&I3)|(I0&I1&I2) ; // ../../sources/designs/udp_osd/eth_udp/udp/udp_rx.v:124 - GTP_LUT3 /* \N842_1[6] */ #( - .INIT(8'b11011000)) + GTP_LUT4 /* \N842_1[6] */ #( + .INIT(16'b1111011110000000)) \N842_1[6] ( .Z (N842[6]), - .I0 (N748), - .I1 (N223[6]), - .I2 (data_byte_num[6])); - // LUT = (~I0&I2)|(I0&I1) ; + .I0 (N374), + .I1 (N586), + .I2 (N223[6]), + .I3 (data_byte_num[6])); + // LUT = (~I1&I3)|(~I0&I3)|(I0&I1&I2) ; // ../../sources/designs/udp_osd/eth_udp/udp/udp_rx.v:124 - GTP_LUT3 /* \N842_1[7] */ #( - .INIT(8'b11011000)) + GTP_LUT4 /* \N842_1[7] */ #( + .INIT(16'b1111011110000000)) \N842_1[7] ( .Z (N842[7]), - .I0 (N748), - .I1 (N223[7]), - .I2 (data_byte_num[7])); - // LUT = (~I0&I2)|(I0&I1) ; + .I0 (N374), + .I1 (N586), + .I2 (N223[7]), + .I3 (data_byte_num[7])); + // LUT = (~I1&I3)|(~I0&I3)|(I0&I1&I2) ; // ../../sources/designs/udp_osd/eth_udp/udp/udp_rx.v:124 - GTP_LUT3 /* \N842_1[8] */ #( - .INIT(8'b11011000)) + GTP_LUT4 /* \N842_1[8] */ #( + .INIT(16'b1111011110000000)) \N842_1[8] ( .Z (N842[8]), - .I0 (N748), - .I1 (N223[8]), - .I2 (data_byte_num[8])); - // LUT = (~I0&I2)|(I0&I1) ; + .I0 (N374), + .I1 (N586), + .I2 (N223[8]), + .I3 (data_byte_num[8])); + // LUT = (~I1&I3)|(~I0&I3)|(I0&I1&I2) ; // ../../sources/designs/udp_osd/eth_udp/udp/udp_rx.v:124 - GTP_LUT3 /* \N842_1[9] */ #( - .INIT(8'b11011000)) + GTP_LUT4 /* \N842_1[9] */ #( + .INIT(16'b1111011110000000)) \N842_1[9] ( .Z (N842[9]), - .I0 (N748), - .I1 (N223[9]), - .I2 (data_byte_num[9])); - // LUT = (~I0&I2)|(I0&I1) ; + .I0 (N374), + .I1 (N586), + .I2 (N223[9]), + .I3 (data_byte_num[9])); + // LUT = (~I1&I3)|(~I0&I3)|(I0&I1&I2) ; // ../../sources/designs/udp_osd/eth_udp/udp/udp_rx.v:124 - GTP_LUT3 /* \N842_1[10] */ #( - .INIT(8'b11011000)) + GTP_LUT4 /* \N842_1[10] */ #( + .INIT(16'b1111011110000000)) \N842_1[10] ( .Z (N842[10]), - .I0 (N748), - .I1 (N223[10]), - .I2 (data_byte_num[10])); - // LUT = (~I0&I2)|(I0&I1) ; + .I0 (N374), + .I1 (N586), + .I2 (N223[10]), + .I3 (data_byte_num[10])); + // LUT = (~I1&I3)|(~I0&I3)|(I0&I1&I2) ; // ../../sources/designs/udp_osd/eth_udp/udp/udp_rx.v:124 - GTP_LUT3 /* \N842_1[11] */ #( - .INIT(8'b11011000)) + GTP_LUT4 /* \N842_1[11] */ #( + .INIT(16'b1111011110000000)) \N842_1[11] ( .Z (N842[11]), - .I0 (N748), - .I1 (N223[11]), - .I2 (data_byte_num[11])); - // LUT = (~I0&I2)|(I0&I1) ; + .I0 (N374), + .I1 (N586), + .I2 (N223[11]), + .I3 (data_byte_num[11])); + // LUT = (~I1&I3)|(~I0&I3)|(I0&I1&I2) ; // ../../sources/designs/udp_osd/eth_udp/udp/udp_rx.v:124 - GTP_LUT3 /* \N842_1[12] */ #( - .INIT(8'b11011000)) + GTP_LUT4 /* \N842_1[12] */ #( + .INIT(16'b1111011110000000)) \N842_1[12] ( .Z (N842[12]), - .I0 (N748), - .I1 (N223[12]), - .I2 (data_byte_num[12])); - // LUT = (~I0&I2)|(I0&I1) ; + .I0 (N374), + .I1 (N586), + .I2 (N223[12]), + .I3 (data_byte_num[12])); + // LUT = (~I1&I3)|(~I0&I3)|(I0&I1&I2) ; // ../../sources/designs/udp_osd/eth_udp/udp/udp_rx.v:124 - GTP_LUT3 /* \N842_1[13] */ #( - .INIT(8'b11011000)) + GTP_LUT4 /* \N842_1[13] */ #( + .INIT(16'b1111011110000000)) \N842_1[13] ( .Z (N842[13]), - .I0 (N748), - .I1 (N223[13]), - .I2 (data_byte_num[13])); - // LUT = (~I0&I2)|(I0&I1) ; + .I0 (N374), + .I1 (N586), + .I2 (N223[13]), + .I3 (data_byte_num[13])); + // LUT = (~I1&I3)|(~I0&I3)|(I0&I1&I2) ; // ../../sources/designs/udp_osd/eth_udp/udp/udp_rx.v:124 - GTP_LUT3 /* \N842_1[14] */ #( - .INIT(8'b11011000)) + GTP_LUT4 /* \N842_1[14] */ #( + .INIT(16'b1111011110000000)) \N842_1[14] ( .Z (N842[14]), - .I0 (N748), - .I1 (N223[14]), - .I2 (data_byte_num[14])); - // LUT = (~I0&I2)|(I0&I1) ; + .I0 (N374), + .I1 (N586), + .I2 (N223[14]), + .I3 (data_byte_num[14])); + // LUT = (~I1&I3)|(~I0&I3)|(I0&I1&I2) ; // ../../sources/designs/udp_osd/eth_udp/udp/udp_rx.v:124 - GTP_LUT3 /* \N842_1[15] */ #( - .INIT(8'b11011000)) + GTP_LUT4 /* \N842_1[15] */ #( + .INIT(16'b1111011110000000)) \N842_1[15] ( .Z (N842[15]), - .I0 (N748), - .I1 (N223[15]), - .I2 (data_byte_num[15])); - // LUT = (~I0&I2)|(I0&I1) ; + .I0 (N374), + .I1 (N586), + .I2 (N223[15]), + .I3 (data_byte_num[15])); + // LUT = (~I1&I3)|(~I0&I3)|(I0&I1&I2) ; // ../../sources/designs/udp_osd/eth_udp/udp/udp_rx.v:124 GTP_LUT4 /* N859_3 */ #( .INIT(16'b0000000010000000)) N859_3 ( .Z (N859), - .I0 (_N96779), + .I0 (_N97553), .I1 (gmii_rxd_valid), .I2 (N376), .I3 (cnt[0])); // LUT = I0&I1&I2&~I3 ; - GTP_LUT5 /* N878_2 */ #( - .INIT(32'b00000000000000001000000000000000)) - N878_2 ( + GTP_LUT4 /* N878_4 */ #( + .INIT(16'b0000000010000000)) + N878_4 ( .Z (N878), - .I0 (_N95923), + .I0 (_N97122), .I1 (N586), - .I2 (cnt[0]), - .I3 (cnt[1]), - .I4 (cnt[2])); - // LUT = I0&I1&I2&I3&~I4 ; + .I2 (cnt[1]), + .I3 (cnt[2])); + // LUT = I0&I1&I2&~I3 ; GTP_LUT5 /* N889 */ #( .INIT(32'b00000000000000000010000000000000)) @@ -363833,19 +363324,19 @@ module udp_rx // LUT = (~I0&I1)|(I0&I2) ; // ../../sources/designs/udp_osd/eth_udp/udp/udp_rx.v:56 - GTP_LUT3 /* \cur_state_fsm[6:0]_31 */ #( + GTP_LUT3 /* \cur_state_fsm[6:0]_26 */ #( .INIT(8'b11100010)) - \cur_state_fsm[6:0]_31 ( + \cur_state_fsm[6:0]_26 ( .Z (next_state[6]), - .I0 (_N81655), + .I0 (_N82491), .I1 (skip_en), .I2 (cur_state_reg[5])); // LUT = (I0&~I1)|(I1&I2) ; - GTP_LUT5 /* \cur_state_fsm[6:0]_34 */ #( + GTP_LUT5 /* \cur_state_fsm[6:0]_33 */ #( .INIT(32'b11111111111111111010101010101000)) - \cur_state_fsm[6:0]_34 ( - .Z (_N81655), + \cur_state_fsm[6:0]_33 ( + .Z (_N82491), .I0 (error_en), .I1 (cur_state_reg[3]), .I2 (cur_state_reg[2]), @@ -365437,16 +364928,16 @@ module udp_rx .Q (rec_en), .C (sync_vg_100m), .CLK (clk), - .D (_N103307)); + .D (_N104119)); // defparam rec_en_vname.orig_name = rec_en; // ../../sources/designs/udp_osd/eth_udp/udp/udp_rx.v:101 GTP_LUT5 /* rec_en_ce_mux */ #( .INIT(32'b10101010001000101110101010101010)) rec_en_ce_mux ( - .Z (_N103307), + .Z (_N104119), .I0 (rec_en), - .I1 (_N96777), + .I1 (_N97542), .I2 (gmii_rxd_valid), .I3 (next_state[5]), .I4 (next_state[6])); @@ -365851,89 +365342,92 @@ endmodule module udp ( input [7:0] gmii_rxd_data, - input [4:0] \udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt , input [4:0] \udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt , - input _N95923, - input _N96072, - input _N96096, - input _N96385, - input _N96556, - input _N96774, - input _N97006, - input _N97473, - input _N98508, + input [6:0] \udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg , + input _N82337, + input _N96653, + input _N96787, + input _N97121, + input _N97122, + input _N97327, + input _N97341, + input _N97542, + input _N97887, + input _N98258, + input _N100572, + input _N108899, input gmii_rx_clk, input gmii_rxd_valid, input sync_vg_100m, input \u_udp_rx/N586 , input \udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N52 , - input \udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N366 , + input \udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1265 , + input \udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/skip_en , output [15:0] rec_byte_num, output [7:0] rec_data, output [15:0] rec_dest_port, output [4:0] \u_udp_rx/cnt , output [6:0] \u_udp_rx/cur_state_reg , output [6:0] \u_udp_rx/next_state , - output _N95844, - output _N96358, - output _N96693, - output _N96775, - output _N96780, - output _N107965, - output _N108056, + output _N82491, + output _N96654, + output _N96657, + output _N97535, + output _N97554, output rec_en, output rec_pkt_done, output rec_pkt_start, + output \u_udp_rx/error_en , output \u_udp_rx/skip_en , - output \udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N559 + output \udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1269 ); - wire \u_udp_rx_cur_state_reg[0]_floating ; - wire \u_udp_rx_cur_state_reg[1]_floating ; + wire \u_udp_rx_cnt[1]_floating ; + wire \u_udp_rx_cnt[2]_floating ; wire \u_udp_rx_cur_state_reg[2]_floating ; - wire \u_udp_rx_cur_state_reg[5]_floating ; - wire \u_udp_rx_cur_state_reg[6]_floating ; - wire \u_udp_rx_next_state[0]_floating ; - wire \u_udp_rx_next_state[1]_floating ; + wire \u_udp_rx_cur_state_reg[3]_floating ; wire \u_udp_rx_next_state[5]_floating ; wire \u_udp_rx_next_state[6]_floating ; udp_rx u_udp_rx ( - .cnt ({\u_udp_rx/cnt [4] , \u_udp_rx/cnt [3] , \u_udp_rx/cnt [2] , \u_udp_rx/cnt [1] , \u_udp_rx/cnt [0] }), - .cur_state_reg ({\u_udp_rx_cur_state_reg[6]_floating , \u_udp_rx_cur_state_reg[5]_floating , \u_udp_rx/cur_state_reg [4] , \u_udp_rx/cur_state_reg [3] , \u_udp_rx_cur_state_reg[2]_floating , \u_udp_rx_cur_state_reg[1]_floating , \u_udp_rx_cur_state_reg[0]_floating }), - .next_state ({\u_udp_rx_next_state[6]_floating , \u_udp_rx_next_state[5]_floating , \u_udp_rx/next_state [4] , \u_udp_rx/next_state [3] , \u_udp_rx/next_state [2] , \u_udp_rx_next_state[1]_floating , \u_udp_rx_next_state[0]_floating }), + .cnt ({\u_udp_rx/cnt [4] , \u_udp_rx/cnt [3] , \u_udp_rx_cnt[2]_floating , \u_udp_rx_cnt[1]_floating , \u_udp_rx/cnt [0] }), + .cur_state_reg ({\u_udp_rx/cur_state_reg [6] , \u_udp_rx/cur_state_reg [5] , \u_udp_rx/cur_state_reg [4] , \u_udp_rx_cur_state_reg[3]_floating , \u_udp_rx_cur_state_reg[2]_floating , \u_udp_rx/cur_state_reg [1] , \u_udp_rx/cur_state_reg [0] }), + .next_state ({\u_udp_rx_next_state[6]_floating , \u_udp_rx_next_state[5]_floating , \u_udp_rx/next_state [4] , \u_udp_rx/next_state [3] , \u_udp_rx/next_state [2] , \u_udp_rx/next_state [1] , \u_udp_rx/next_state [0] }), .rec_byte_num (rec_byte_num), .rec_data (rec_data), .rec_dest_port (rec_dest_port), .gmii_rxd_data (gmii_rxd_data), - .\udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt ({\udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt [4] , \udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt [3] , \udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt [2] , \udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt [1] , 1'bx}), .\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt ({\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt [4] , \udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt [3] , \udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt [2] , \udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt [1] , 1'bx}), - ._N95844 (_N95844), - ._N96358 (_N96358), - ._N96693 (_N96693), - ._N96775 (_N96775), - ._N96780 (_N96780), - ._N107965 (_N107965), - ._N108056 (_N108056), + .\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg ({\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg [6] , \udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg [5] , \udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg [4] , 1'bx, 1'bx, 1'bx, 1'bx}), + ._N82491 (_N82491), + ._N96654 (_N96654), + ._N96657 (_N96657), + ._N97535 (_N97535), + ._N97554 (_N97554), + .error_en (\u_udp_rx/error_en ), .rec_en (rec_en), .rec_pkt_done (rec_pkt_done), .rec_pkt_start (rec_pkt_start), .skip_en (\u_udp_rx/skip_en ), - .\udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N559 (\udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N559 ), + .\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1269 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1269 ), .N64 (\udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N52 ), .N586 (\u_udp_rx/N586 ), - ._N95923 (_N95923), - ._N96072 (_N96072), - ._N96096 (_N96096), - ._N96385 (_N96385), - ._N96556 (_N96556), - ._N96774 (_N96774), - ._N97006 (_N97006), - ._N97473 (_N97473), - ._N98508 (_N98508), + ._N82337 (_N82337), + ._N96653 (_N96653), + ._N96787 (_N96787), + ._N97121 (_N97121), + ._N97122 (_N97122), + ._N97327 (_N97327), + ._N97341 (_N97341), + ._N97542 (_N97542), + ._N97887 (_N97887), + ._N98258 (_N98258), + ._N100572 (_N100572), + ._N108899 (_N108899), .clk (gmii_rx_clk), .gmii_rxd_valid (gmii_rxd_valid), .sync_vg_100m (sync_vg_100m), - .\udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N366 (\udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N366 )); + .\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1265 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1265 ), + .\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/skip_en (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/skip_en )); // ../../sources/designs/udp_osd/eth_udp/udp/udp.v:58 @@ -365951,8 +365445,8 @@ module pulse_cdc output dest_pulse ); wire N2; - wire _N103512; - wire _N103524; + wire _N104324; + wire _N104336; wire in_req; wire in_req_sync0; wire in_req_sync1; @@ -365976,14 +365470,14 @@ module pulse_cdc in_req_vname ( .Q (in_req), .CLK (src_clk), - .D (_N103512)); + .D (_N104324)); // defparam in_req_vname.orig_name = in_req; // ../../sources/designs/udp_osd/eth_udp/inout_buffer/pulse_cdc.v:69 GTP_LUT5 /* in_req_rs_mux */ #( .INIT(32'b01000000010101010100000001000000)) in_req_rs_mux ( - .Z (_N103512), + .Z (_N104324), .I0 (sync_vg_100m), .I1 (udp_rx_pkt_done), .I2 (\udp_osd_inst/eth_udp_inst/N72_cpy ), @@ -366029,14 +365523,14 @@ module pulse_cdc out_ack_vname ( .Q (out_ack), .CLK (dest_clk), - .D (_N103524)); + .D (_N104336)); // defparam out_ack_vname.orig_name = out_ack; // ../../sources/designs/udp_osd/eth_udp/inout_buffer/pulse_cdc.v:47 GTP_LUT2 /* out_ack_rs_mux */ #( .INIT(4'b0100)) out_ack_rs_mux ( - .Z (_N103524), + .Z (_N104336), .I0 (sync_vg_100m), .I1 (in_req_sync1)); // LUT = ~I0&I1 ; @@ -366093,29 +365587,29 @@ module ipml_fifo_ctrl_v1_3_4 wire N168; wire N170; wire [12:0] \N170.co ; - wire _N14996; - wire _N14997; - wire _N14998; - wire _N14999; - wire _N15000; - wire _N15001; - wire _N15002; - wire _N15003; - wire _N15004; - wire _N15005; - wire _N15006; - wire _N17159; - wire _N17160; - wire _N17161; - wire _N17162; - wire _N17163; - wire _N17164; - wire _N17165; - wire _N17166; - wire _N17167; - wire _N17168; - wire _N108382; - wire _N108383; + wire _N13664; + wire _N13665; + wire _N13666; + wire _N13667; + wire _N13668; + wire _N13669; + wire _N13670; + wire _N13671; + wire _N13672; + wire _N13673; + wire _N13674; + wire _N17079; + wire _N17080; + wire _N17081; + wire _N17082; + wire _N17083; + wire _N17084; + wire _N17085; + wire _N17086; + wire _N17087; + wire _N17088; + wire _N109270; + wire _N109271; wire [11:0] nb4; wire [11:0] rbin; wire [11:0] rgnext; @@ -367016,7 +366510,7 @@ module ipml_fifo_ctrl_v1_3_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_1_1 ( - .COUT (_N17159), + .COUT (_N17079), .Z (nb4[1]), .CIN (), .I0 (waddr[0]), @@ -367036,9 +366530,9 @@ module ipml_fifo_ctrl_v1_3_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_1_2 ( - .COUT (_N17160), + .COUT (_N17080), .Z (nb4[2]), - .CIN (_N17159), + .CIN (_N17079), .I0 (waddr[0]), .I1 (waddr[1]), .I2 (waddr[2]), @@ -367056,9 +366550,9 @@ module ipml_fifo_ctrl_v1_3_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_1_3 ( - .COUT (_N17161), + .COUT (_N17081), .Z (nb4[3]), - .CIN (_N17160), + .CIN (_N17080), .I0 (), .I1 (waddr[3]), .I2 (), @@ -367076,9 +366570,9 @@ module ipml_fifo_ctrl_v1_3_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_1_4 ( - .COUT (_N17162), + .COUT (_N17082), .Z (nb4[4]), - .CIN (_N17161), + .CIN (_N17081), .I0 (), .I1 (waddr[4]), .I2 (), @@ -367096,9 +366590,9 @@ module ipml_fifo_ctrl_v1_3_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_1_5 ( - .COUT (_N17163), + .COUT (_N17083), .Z (nb4[5]), - .CIN (_N17162), + .CIN (_N17082), .I0 (), .I1 (waddr[5]), .I2 (), @@ -367116,9 +366610,9 @@ module ipml_fifo_ctrl_v1_3_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_1_6 ( - .COUT (_N17164), + .COUT (_N17084), .Z (nb4[6]), - .CIN (_N17163), + .CIN (_N17083), .I0 (), .I1 (waddr[6]), .I2 (), @@ -367136,9 +366630,9 @@ module ipml_fifo_ctrl_v1_3_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_1_7 ( - .COUT (_N17165), + .COUT (_N17085), .Z (nb4[7]), - .CIN (_N17164), + .CIN (_N17084), .I0 (), .I1 (waddr[7]), .I2 (), @@ -367156,9 +366650,9 @@ module ipml_fifo_ctrl_v1_3_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_1_8 ( - .COUT (_N17166), + .COUT (_N17086), .Z (nb4[8]), - .CIN (_N17165), + .CIN (_N17085), .I0 (), .I1 (waddr[8]), .I2 (), @@ -367176,9 +366670,9 @@ module ipml_fifo_ctrl_v1_3_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_1_9 ( - .COUT (_N17167), + .COUT (_N17087), .Z (nb4[9]), - .CIN (_N17166), + .CIN (_N17086), .I0 (), .I1 (waddr[9]), .I2 (), @@ -367196,9 +366690,9 @@ module ipml_fifo_ctrl_v1_3_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N2_1_10 ( - .COUT (_N17168), + .COUT (_N17088), .Z (nb4[10]), - .CIN (_N17167), + .CIN (_N17087), .I0 (), .I1 (waddr[10]), .I2 (), @@ -367218,7 +366712,7 @@ module ipml_fifo_ctrl_v1_3_4 N2_1_11 ( .COUT (), .Z (nb4[11]), - .CIN (_N17168), + .CIN (_N17088), .I0 (), .I1 (wbin[11]), .I2 (), @@ -367244,7 +366738,7 @@ module ipml_fifo_ctrl_v1_3_4 GTP_LUT5 /* \N3[1]_1 */ #( .INIT(32'b11110010110100000000110100101111)) \N3[1]_1 ( - .Z (_N108382), + .Z (_N109270), .I0 (w_en), .I1 (wfull), .I2 (waddr[1]), @@ -367289,7 +366783,7 @@ module ipml_fifo_ctrl_v1_3_4 GTP_LUT5 /* \N3[5]_1 */ #( .INIT(32'b11110010110100000000110100101111)) \N3[5]_1 ( - .Z (_N108383), + .Z (_N109271), .I0 (w_en), .I1 (wfull), .I2 (waddr[5]), @@ -367589,7 +367083,7 @@ module ipml_fifo_ctrl_v1_3_4 .I4_TO_CARRY("FALSE"), .I4_TO_LUT("FALSE")) N84_1_0 ( - .COUT (_N14996), + .COUT (_N13664), .Z (), .CIN (), .I0 (), @@ -367609,9 +367103,9 @@ module ipml_fifo_ctrl_v1_3_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_1_1 ( - .COUT (_N14997), + .COUT (_N13665), .Z (N84[1]), - .CIN (_N14996), + .CIN (_N13664), .I0 (), .I1 (raddr[1]), .I2 (\udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/fifo_rd_data_en ), @@ -367629,9 +367123,9 @@ module ipml_fifo_ctrl_v1_3_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_1_2 ( - .COUT (_N14998), + .COUT (_N13666), .Z (N84[2]), - .CIN (_N14997), + .CIN (_N13665), .I0 (), .I1 (raddr[2]), .I2 (\udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/fifo_rd_data_en ), @@ -367649,9 +367143,9 @@ module ipml_fifo_ctrl_v1_3_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_1_3 ( - .COUT (_N14999), + .COUT (_N13667), .Z (N84[3]), - .CIN (_N14998), + .CIN (_N13666), .I0 (), .I1 (raddr[3]), .I2 (\udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/fifo_rd_data_en ), @@ -367669,9 +367163,9 @@ module ipml_fifo_ctrl_v1_3_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_1_4 ( - .COUT (_N15000), + .COUT (_N13668), .Z (N84[4]), - .CIN (_N14999), + .CIN (_N13667), .I0 (), .I1 (raddr[4]), .I2 (\udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/fifo_rd_data_en ), @@ -367689,9 +367183,9 @@ module ipml_fifo_ctrl_v1_3_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_1_5 ( - .COUT (_N15001), + .COUT (_N13669), .Z (N84[5]), - .CIN (_N15000), + .CIN (_N13668), .I0 (), .I1 (raddr[5]), .I2 (\udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/fifo_rd_data_en ), @@ -367709,9 +367203,9 @@ module ipml_fifo_ctrl_v1_3_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_1_6 ( - .COUT (_N15002), + .COUT (_N13670), .Z (N84[6]), - .CIN (_N15001), + .CIN (_N13669), .I0 (), .I1 (raddr[6]), .I2 (\udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/fifo_rd_data_en ), @@ -367729,9 +367223,9 @@ module ipml_fifo_ctrl_v1_3_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_1_7 ( - .COUT (_N15003), + .COUT (_N13671), .Z (N84[7]), - .CIN (_N15002), + .CIN (_N13670), .I0 (), .I1 (raddr[7]), .I2 (\udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/fifo_rd_data_en ), @@ -367749,9 +367243,9 @@ module ipml_fifo_ctrl_v1_3_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_1_8 ( - .COUT (_N15004), + .COUT (_N13672), .Z (N84[8]), - .CIN (_N15003), + .CIN (_N13671), .I0 (), .I1 (raddr[8]), .I2 (\udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/fifo_rd_data_en ), @@ -367769,9 +367263,9 @@ module ipml_fifo_ctrl_v1_3_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_1_9 ( - .COUT (_N15005), + .COUT (_N13673), .Z (N84[9]), - .CIN (_N15004), + .CIN (_N13672), .I0 (), .I1 (raddr[9]), .I2 (\udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/fifo_rd_data_en ), @@ -367789,9 +367283,9 @@ module ipml_fifo_ctrl_v1_3_4 .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N84_1_10 ( - .COUT (_N15006), + .COUT (_N13674), .Z (N84[10]), - .CIN (_N15005), + .CIN (_N13673), .I0 (), .I1 (raddr[10]), .I2 (\udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/fifo_rd_data_en ), @@ -367811,7 +367305,7 @@ module ipml_fifo_ctrl_v1_3_4 N84_1_11 ( .COUT (), .Z (N84[11]), - .CIN (_N15006), + .CIN (_N13674), .I0 (), .I1 (rbin[11]), .I2 (\udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/fifo_rd_data_en ), @@ -368074,18 +367568,18 @@ module ipml_fifo_ctrl_v1_3_4 // LUT = (I0&I1&~I4)|(~I0&I2&~I3)|(~I0&~I2&I3)|(I0&~I1&I4) ; // ../ipcore/image_in_fifo/rtl/ipml_fifo_ctrl_v1_3.v:151 - GTP_LUT3 /* N106_2 */ #( + GTP_LUT3 /* N106_1 */ #( .INIT(8'b10010110)) - N106_2 ( + N106_1 ( .Z (rwptr[9]), .I0 (rwptr2[9]), .I1 (rwptr2[10]), .I2 (rwptr2[11])); // LUT = (I0&~I1&~I2)|(~I0&I1&~I2)|(~I0&~I1&I2)|(I0&I1&I2) ; - GTP_LUT5 /* N106_4 */ #( + GTP_LUT5 /* N106_3 */ #( .INIT(32'b10010110011010010110100110010110)) - N106_4 ( + N106_3 ( .Z (rwptr[7]), .I0 (rwptr2[7]), .I1 (rwptr2[8]), @@ -368094,18 +367588,18 @@ module ipml_fifo_ctrl_v1_3_4 .I4 (rwptr2[11])); // LUT = (I0&~I1&~I2&~I3&~I4)|(~I0&I1&~I2&~I3&~I4)|(~I0&~I1&I2&~I3&~I4)|(I0&I1&I2&~I3&~I4)|(~I0&~I1&~I2&I3&~I4)|(I0&I1&~I2&I3&~I4)|(I0&~I1&I2&I3&~I4)|(~I0&I1&I2&I3&~I4)|(~I0&~I1&~I2&~I3&I4)|(I0&I1&~I2&~I3&I4)|(I0&~I1&I2&~I3&I4)|(~I0&I1&I2&~I3&I4)|(I0&~I1&~I2&I3&I4)|(~I0&I1&~I2&I3&I4)|(~I0&~I1&I2&I3&I4)|(I0&I1&I2&I3&I4) ; - GTP_LUT3 /* N106_6 */ #( + GTP_LUT3 /* N106_5 */ #( .INIT(8'b10010110)) - N106_6 ( + N106_5 ( .Z (rwptr[5]), .I0 (rwptr[7]), .I1 (rwptr2[5]), .I2 (rwptr2[6])); // LUT = (I0&~I1&~I2)|(~I0&I1&~I2)|(~I0&~I1&I2)|(I0&I1&I2) ; - GTP_LUT5 /* N106_8 */ #( + GTP_LUT5 /* N106_7 */ #( .INIT(32'b10010110011010010110100110010110)) - N106_8 ( + N106_7 ( .Z (rwptr[3]), .I0 (rwptr[7]), .I1 (rwptr2[3]), @@ -368114,9 +367608,9 @@ module ipml_fifo_ctrl_v1_3_4 .I4 (rwptr2[6])); // LUT = (I0&~I1&~I2&~I3&~I4)|(~I0&I1&~I2&~I3&~I4)|(~I0&~I1&I2&~I3&~I4)|(I0&I1&I2&~I3&~I4)|(~I0&~I1&~I2&I3&~I4)|(I0&I1&~I2&I3&~I4)|(I0&~I1&I2&I3&~I4)|(~I0&I1&I2&I3&~I4)|(~I0&~I1&~I2&~I3&I4)|(I0&I1&~I2&~I3&I4)|(I0&~I1&I2&~I3&I4)|(~I0&I1&I2&~I3&I4)|(I0&~I1&~I2&I3&I4)|(~I0&I1&~I2&I3&I4)|(~I0&~I1&I2&I3&I4)|(I0&I1&I2&I3&I4) ; - GTP_LUT3 /* N106_10 */ #( + GTP_LUT3 /* N106_9 */ #( .INIT(8'b10010110)) - N106_10 ( + N106_9 ( .Z (rwptr[1]), .I0 (rwptr[3]), .I1 (rwptr2[1]), @@ -368136,7 +367630,7 @@ module ipml_fifo_ctrl_v1_3_4 .I0 (wwptr[0]), .I1 (wrptr[0]), .I2 (wrptr[2]), - .I3 (_N108382), + .I3 (_N109270), .I4 (), .ID ()); // LUT = (~I0&~I1&I2&~I3)|(I0&I1&I2&~I3)|(~I0&~I1&~I2&I3)|(I0&I1&~I2&I3) ; @@ -368176,7 +367670,7 @@ module ipml_fifo_ctrl_v1_3_4 .I0 (wwptr[4]), .I1 (wrptr[4]), .I2 (wrptr[6]), - .I3 (_N108383), + .I3 (_N109271), .I4 (), .ID ()); // LUT = 1'b0 ; @@ -368845,19 +368339,21 @@ endmodule module udp_receive_buffer ( + input [9:0] \udp_osd_inst/char_osd_inst/char_buf_reader_inst/N907 , + input [4:0] \udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_reg , input [7:0] \udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg , input [7:0] udp_rx_data_i, input [15:0] udp_rx_num_i, input N64_0, - input _N106910, - input _N106911, - input pkt_rd_done, + input _N97124, + input _N107734, + input _N107735, input recv_clk_i, input recv_m_data_tready, input sync_vg_100m, + input \udp_osd_inst/char_osd_inst/char_buf_reader_inst/N73 , input \udp_osd_inst/eth_udp_inst/N72 , input \udp_osd_inst/eth_udp_inst/N72_cpy , - input \udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N969 , input \udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/skip_en , input udp_rx_clk_i, input udp_rx_pkt_done, @@ -368868,14 +368364,13 @@ module udp_receive_buffer output [7:0] recv_m_data_tdata, output [15:0] recv_m_data_tsize, output N222, - output _N95913, - output _N95955, - output _N95958, - output _N96003, - output _N97022, - output recv_m_data_tlast, + output _N96703, + output _N96734, + output _N97125, + output _N97265, + output pkt_rd_done, output recv_m_data_tvalid, - output \udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N973 + output \udp_osd_inst/char_osd_inst/char_buf_reader_inst/N714 ); wire N104_1; wire [15:0] \N108_1.co ; @@ -368896,34 +368391,34 @@ module udp_receive_buffer wire _N2; wire _N8; wire _N11; - wire _N14102; - wire _N14103; - wire _N14104; - wire _N14105; - wire _N14106; - wire _N14107; - wire _N14108; - wire _N14109; - wire _N14110; - wire _N14111; - wire _N14112; - wire _N14113; - wire _N14114; - wire _N14115; - wire _N15500; - wire _N15501; - wire _N15502; - wire _N15503; - wire _N97495; - wire _N103314; - wire _N103315; - wire _N103520; - wire _N103522; - wire _N106928; - wire _N106933; - wire _N106935; - wire _N106939; - wire _N108115; + wire _N13921; + wire _N13922; + wire _N13923; + wire _N13924; + wire _N13925; + wire _N13926; + wire _N13927; + wire _N13928; + wire _N13929; + wire _N13930; + wire _N13931; + wire _N13932; + wire _N13933; + wire _N13934; + wire _N17121; + wire _N17122; + wire _N17123; + wire _N17124; + wire _N98274; + wire _N104126; + wire _N104127; + wire _N104332; + wire _N104334; + wire _N107752; + wire _N107757; + wire _N107759; + wire _N107763; + wire _N108952; wire [5:0] cached_pkt_num; wire change_to_read; wire [7:0] data_size_H; @@ -368936,6 +368431,7 @@ module udp_receive_buffer wire fifo_wr_en_cpy; wire pkt_wr_done; wire [15:0] rd_cnt; + wire recv_m_data_tlast; wire [2:0] state_reg; wire \udp_osd_inst/udp_rx_cached_pkt_num[0]_inv ; wire udp_rx_start_i_ff; @@ -369061,7 +368557,7 @@ module udp_receive_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_1_1 ( - .COUT (_N14102), + .COUT (_N13921), .Z (N352[1]), .CIN (), .I0 (cnt[0]), @@ -369081,9 +368577,9 @@ module udp_receive_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_1_2 ( - .COUT (_N14103), + .COUT (_N13922), .Z (N281[2]), - .CIN (_N14102), + .CIN (_N13921), .I0 (cnt[0]), .I1 (cnt[1]), .I2 (cnt[2]), @@ -369101,9 +368597,9 @@ module udp_receive_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_1_3 ( - .COUT (_N14104), + .COUT (_N13923), .Z (N281[3]), - .CIN (_N14103), + .CIN (_N13922), .I0 (), .I1 (cnt[3]), .I2 (state_reg[1]), @@ -369121,9 +368617,9 @@ module udp_receive_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_1_4 ( - .COUT (_N14105), + .COUT (_N13924), .Z (N281[4]), - .CIN (_N14104), + .CIN (_N13923), .I0 (), .I1 (cnt[4]), .I2 (state_reg[1]), @@ -369141,9 +368637,9 @@ module udp_receive_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_1_5 ( - .COUT (_N14106), + .COUT (_N13925), .Z (N281[5]), - .CIN (_N14105), + .CIN (_N13924), .I0 (), .I1 (cnt[5]), .I2 (state_reg[1]), @@ -369161,9 +368657,9 @@ module udp_receive_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_1_6 ( - .COUT (_N14107), + .COUT (_N13926), .Z (N281[6]), - .CIN (_N14106), + .CIN (_N13925), .I0 (), .I1 (cnt[6]), .I2 (state_reg[1]), @@ -369181,9 +368677,9 @@ module udp_receive_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_1_7 ( - .COUT (_N14108), + .COUT (_N13927), .Z (N281[7]), - .CIN (_N14107), + .CIN (_N13926), .I0 (), .I1 (cnt[7]), .I2 (state_reg[1]), @@ -369201,9 +368697,9 @@ module udp_receive_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_1_8 ( - .COUT (_N14109), + .COUT (_N13928), .Z (N281[8]), - .CIN (_N14108), + .CIN (_N13927), .I0 (), .I1 (cnt[8]), .I2 (state_reg[1]), @@ -369221,9 +368717,9 @@ module udp_receive_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_1_9 ( - .COUT (_N14110), + .COUT (_N13929), .Z (N281[9]), - .CIN (_N14109), + .CIN (_N13928), .I0 (), .I1 (cnt[9]), .I2 (state_reg[1]), @@ -369241,9 +368737,9 @@ module udp_receive_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_1_10 ( - .COUT (_N14111), + .COUT (_N13930), .Z (N281[10]), - .CIN (_N14110), + .CIN (_N13929), .I0 (), .I1 (cnt[10]), .I2 (state_reg[1]), @@ -369261,9 +368757,9 @@ module udp_receive_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_1_11 ( - .COUT (_N14112), + .COUT (_N13931), .Z (N281[11]), - .CIN (_N14111), + .CIN (_N13930), .I0 (), .I1 (cnt[11]), .I2 (state_reg[1]), @@ -369281,9 +368777,9 @@ module udp_receive_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_1_12 ( - .COUT (_N14113), + .COUT (_N13932), .Z (N281[12]), - .CIN (_N14112), + .CIN (_N13931), .I0 (), .I1 (cnt[12]), .I2 (state_reg[1]), @@ -369301,9 +368797,9 @@ module udp_receive_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_1_13 ( - .COUT (_N14114), + .COUT (_N13933), .Z (N281[13]), - .CIN (_N14113), + .CIN (_N13932), .I0 (), .I1 (cnt[13]), .I2 (state_reg[1]), @@ -369321,9 +368817,9 @@ module udp_receive_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_1_14 ( - .COUT (_N14115), + .COUT (_N13934), .Z (N281[14]), - .CIN (_N14114), + .CIN (_N13933), .I0 (), .I1 (cnt[14]), .I2 (state_reg[1]), @@ -369343,7 +368839,7 @@ module udp_receive_buffer N27_1_15 ( .COUT (), .Z (N281[15]), - .CIN (_N14115), + .CIN (_N13934), .I0 (), .I1 (cnt[15]), .I2 (state_reg[1]), @@ -369354,6 +368850,16 @@ module udp_receive_buffer // CARRY = (I1) ? CIN : (I4) ; // ../../sources/designs/udp_osd/eth_udp/inout_buffer/udp_receive_buffer.v:116 + GTP_LUT4 /* N59_1 */ #( + .INIT(16'b0000001000000111)) + N59_1 ( + .Z (_N96703), + .I0 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/skip_en ), + .I1 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg [4] ), + .I2 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg [5] ), + .I3 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg [6] )); + // LUT = (~I0&~I2&~I3)|(I0&~I1&~I2) ; + GTP_LUT2 /* N81 */ #( .INIT(4'b1110)) N81 ( @@ -369692,7 +369198,7 @@ module udp_receive_buffer .INIT(16'b1100111011111111)) N120_3 ( .Z (N120), - .I0 (_N97495), + .I0 (_N98274), .I1 (fifo_empty), .I2 (rd_cnt[0]), .I3 (state_reg[2])); @@ -369701,7 +369207,7 @@ module udp_receive_buffer GTP_LUT4 /* N135_6 */ #( .INIT(16'b0000101100000000)) N135_6 ( - .Z (_N108115), + .Z (_N108952), .I0 (recv_m_data_tready), .I1 (recv_m_data_tvalid), .I2 (fifo_empty), @@ -369712,15 +369218,15 @@ module udp_receive_buffer .INIT(8'b11010000)) N135_7 ( .Z (fifo_rd_data_en), - .I0 (_N97495), + .I0 (_N98274), .I1 (rd_cnt[0]), - .I2 (_N108115)); + .I2 (_N108952)); // LUT = (~I0&I2)|(I1&I2) ; GTP_LUT3 /* N140_20 */ #( .INIT(8'b00000001)) N140_20 ( - .Z (_N106928), + .Z (_N107752), .I0 (rd_cnt[4]), .I1 (rd_cnt[5]), .I2 (rd_cnt[8])); @@ -369729,7 +369235,7 @@ module udp_receive_buffer GTP_LUT5 /* N140_25 */ #( .INIT(32'b00000000000000000000000000000001)) N140_25 ( - .Z (_N106933), + .Z (_N107757), .I0 (rd_cnt[9]), .I1 (rd_cnt[10]), .I2 (rd_cnt[11]), @@ -369740,7 +369246,7 @@ module udp_receive_buffer GTP_LUT5 /* N140_27 */ #( .INIT(32'b00000000000000000000000000000001)) N140_27 ( - .Z (_N106935), + .Z (_N107759), .I0 (rd_cnt[1]), .I1 (rd_cnt[2]), .I2 (rd_cnt[3]), @@ -369751,18 +369257,18 @@ module udp_receive_buffer GTP_LUT5 /* N140_29 */ #( .INIT(32'b00010000000000000000000000000000)) N140_29 ( - .Z (_N97495), + .Z (_N98274), .I0 (rd_cnt[6]), .I1 (rd_cnt[7]), - .I2 (_N106928), - .I3 (_N106933), - .I4 (_N106935)); + .I2 (_N107752), + .I3 (_N107757), + .I4 (_N107759)); // LUT = ~I0&~I1&I2&I3&I4 ; GTP_LUT2 /* N173_3 */ #( .INIT(4'b1110)) N173_3 ( - .Z (_N106939), + .Z (_N107763), .I0 (cached_pkt_num[2]), .I1 (cached_pkt_num[3])); // LUT = (I0)|(I1) ; @@ -369775,46 +369281,25 @@ module udp_receive_buffer .I1 (cached_pkt_num[1]), .I2 (cached_pkt_num[4]), .I3 (cached_pkt_num[5]), - .I4 (_N106939)); + .I4 (_N107763)); // LUT = (I0)|(I1)|(I2)|(I3)|(I4) ; - GTP_LUT4 /* N191_1 */ #( - .INIT(16'b0000001000000111)) - N191_1 ( - .Z (_N95913), - .I0 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/skip_en ), - .I1 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg [4] ), - .I2 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg [5] ), - .I3 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg [6] )); - // LUT = (~I0&~I2&~I3)|(I0&~I1&~I2) ; - - GTP_LUT5 /* N191_2 */ #( - .INIT(32'b00000000000010000000000000101010)) - N191_2 ( - .Z (_N97022), - .I0 (_N95955), - .I1 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/skip_en ), - .I2 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg [2] ), - .I3 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg [3] ), - .I4 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg [4] )); - // LUT = (I0&~I1&~I3&~I4)|(I0&I1&~I2&~I3) ; - GTP_LUT4 /* N192 */ #( .INIT(16'b0010000000000000)) N192_vname ( .Z (N192), .I0 (cnt[0]), .I1 (cnt[1]), - .I2 (_N106910), - .I3 (_N106911)); + .I2 (_N107734), + .I3 (_N107735)); // defparam N192_vname.orig_name = N192; // LUT = I0&~I1&I2&I3 ; // ../../sources/designs/udp_osd/eth_udp/inout_buffer/udp_receive_buffer.v:120 - GTP_LUT5M /* N249_1 */ #( + GTP_LUT5M /* N192_1 */ #( .INIT(32'b00000000000000010000000000000001)) - N249_1 ( - .Z (_N95955), + N192_1 ( + .Z (_N96734), .I0 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg [4] ), .I1 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg [5] ), .I2 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg [6] ), @@ -369823,13 +369308,17 @@ module udp_receive_buffer .ID (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg [0] )); // LUT = (~ID&~I1&~I2&~I3&~I4)|(~I0&~I1&~I2&~I3&I4) ; - GTP_LUT2 /* N249_2 */ #( - .INIT(4'b0100)) - N249_2 ( - .Z (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N973 ), - .I0 (sync_vg_100m), - .I1 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N969 )); - // LUT = ~I0&I1 ; + GTP_LUT5M /* N249_1 */ #( + .INIT(32'b00000000000000010000000000000001)) + N249_1 ( + .Z (_N97265), + .I0 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg [0] ), + .I1 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg [2] ), + .I2 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg [3] ), + .I3 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg [1] ), + .I4 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/skip_en ), + .ID (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg [4] )); + // LUT = (~ID&~I1&~I2&~I3&~I4)|(~I0&~I1&~I2&~I3&I4) ; GTP_LUT4 /* N249_6 */ #( .INIT(16'b0100000000000000)) @@ -369837,8 +369326,8 @@ module udp_receive_buffer .Z (N357[1]), .I0 (cnt[0]), .I1 (cnt[1]), - .I2 (_N106910), - .I3 (_N106911)); + .I2 (_N107734), + .I3 (_N107735)); // LUT = ~I0&I1&I2&I3 ; GTP_LUT5 /* N259_2 */ #( @@ -369848,20 +369337,10 @@ module udp_receive_buffer .I0 (state_reg[1]), .I1 (cnt[0]), .I2 (cnt[1]), - .I3 (_N106910), - .I4 (_N106911)); + .I3 (_N107734), + .I4 (_N107735)); // LUT = I0&~I1&~I2&I3&I4 ; - GTP_LUT4 /* N260_1 */ #( - .INIT(16'b0000001000000111)) - N260_1 ( - .Z (_N95958), - .I0 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/skip_en ), - .I1 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg [0] ), - .I2 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg [1] ), - .I3 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg [2] )); - // LUT = (~I0&~I2&~I3)|(I0&~I1&~I2) ; - GTP_LUT5 /* N260_3 */ #( .INIT(32'b00101000000000000000000000000000)) N260_3 ( @@ -369869,8 +369348,8 @@ module udp_receive_buffer .I0 (state_reg[1]), .I1 (cnt[0]), .I2 (cnt[1]), - .I3 (_N106910), - .I4 (_N106911)); + .I3 (_N107734), + .I4 (_N107735)); // LUT = (I0&I1&~I2&I3&I4)|(I0&~I1&I2&I3&I4) ; GTP_LUT3 /* \N281_7[0] */ #( @@ -369882,18 +369361,6 @@ module udp_receive_buffer .I2 (cnt[0])); // LUT = I0&~I1&~I2 ; - GTP_LUT5M /* \N281_7[0]_1 */ #( - .INIT(32'b00000000000000010000000000000001)) - \N281_7[0]_1 ( - .Z (_N96003), - .I0 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg [0] ), - .I1 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg [2] ), - .I2 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg [3] ), - .I3 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg [1] ), - .I4 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/skip_en ), - .ID (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg [4] )); - // LUT = (~ID&~I1&~I2&~I3&~I4)|(~I0&~I1&~I2&~I3&I4) ; - GTP_LUT3 /* \N281_7[1] */ #( .INIT(8'b00001000)) \N281_7[1] ( @@ -369949,7 +369416,7 @@ module udp_receive_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N324_6_1 ( - .COUT (_N15500), + .COUT (_N17121), .Z (N324[1]), .CIN (), .I0 (cached_pkt_num[0]), @@ -369968,9 +369435,9 @@ module udp_receive_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N324_6_2 ( - .COUT (_N15501), + .COUT (_N17122), .Z (N324[2]), - .CIN (_N15500), + .CIN (_N17121), .I0 (cached_pkt_num[0]), .I1 (pkt_rd_done), .I2 (cached_pkt_num[1]), @@ -369987,9 +369454,9 @@ module udp_receive_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N324_6_3 ( - .COUT (_N15502), + .COUT (_N17123), .Z (N324[3]), - .CIN (_N15501), + .CIN (_N17122), .I0 (), .I1 (pkt_rd_done), .I2 (cached_pkt_num[3]), @@ -370006,9 +369473,9 @@ module udp_receive_buffer .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N324_6_4 ( - .COUT (_N15503), + .COUT (_N17124), .Z (N324[4]), - .CIN (_N15502), + .CIN (_N17123), .I0 (), .I1 (pkt_rd_done), .I2 (cached_pkt_num[4]), @@ -370027,7 +369494,7 @@ module udp_receive_buffer N324_6_5 ( .COUT (), .Z (N324[5]), - .CIN (_N15503), + .CIN (_N17124), .I0 (), .I1 (pkt_rd_done), .I2 (cached_pkt_num[5]), @@ -370057,20 +369524,50 @@ module udp_receive_buffer // LUT = (~I1&~I2)|(I0&I1) ; // ../../sources/designs/udp_osd/eth_udp/inout_buffer/udp_receive_buffer.v:180 + GTP_LUT4 /* N338_1 */ #( + .INIT(16'b0000001000000111)) + N338_1 ( + .Z (_N97125), + .I0 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/skip_en ), + .I1 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg [0] ), + .I2 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg [1] ), + .I3 (\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg [2] )); + // LUT = (~I0&~I2&~I3)|(I0&~I1&~I2) ; + + GTP_LUT3 /* N338_2 */ #( + .INIT(8'b10000000)) + N338_2 ( + .Z (pkt_rd_done), + .I0 (recv_m_data_tlast), + .I1 (recv_m_data_tready), + .I2 (recv_m_data_tvalid)); + // LUT = I0&I1&I2 ; + + GTP_LUT5 /* N339_1 */ #( + .INIT(32'b11111111100000001111111100000000)) + N339_1 ( + .Z (\udp_osd_inst/char_osd_inst/char_buf_reader_inst/N714 ), + .I0 (_N97124), + .I1 (\udp_osd_inst/char_osd_inst/char_buf_reader_inst/N73 ), + .I2 (\udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_reg [1] ), + .I3 (\udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_reg [0] ), + .I4 (\udp_osd_inst/char_osd_inst/char_buf_reader_inst/N907 [7] )); + // LUT = (I3)|(I0&I1&I2&I4) ; + GTP_DFF /* change_to_read */ #( .GRS_EN("TRUE"), .INIT(1'b0)) change_to_read_vname ( .Q (change_to_read), .CLK (recv_clk_i), - .D (_N103315)); + .D (_N104127)); // defparam change_to_read_vname.orig_name = change_to_read; // ../../sources/designs/udp_osd/eth_udp/inout_buffer/udp_receive_buffer.v:99 GTP_LUT5 /* change_to_read_ce_mux */ #( .INIT(32'b10100000101000001111010011110000)) change_to_read_ce_mux ( - .Z (_N103315), + .Z (_N104127), .I0 (sync_vg_100m), .I1 (state_reg[1]), .I2 (change_to_read), @@ -370324,7 +369821,7 @@ module udp_receive_buffer fifo_rd_num_en_vname ( .Q (fifo_rd_num_en), .CLK (recv_clk_i), - .D (_N103314), + .D (_N104126), .R (sync_vg_100m)); // defparam fifo_rd_num_en_vname.orig_name = fifo_rd_num_en; // ../../sources/designs/udp_osd/eth_udp/inout_buffer/udp_receive_buffer.v:99 @@ -370332,7 +369829,7 @@ module udp_receive_buffer GTP_LUT5 /* fifo_rd_num_en_ce_mux */ #( .INIT(32'b00110011001100100011001100100010)) fifo_rd_num_en_ce_mux ( - .Z (_N103314), + .Z (_N104126), .I0 (N259), .I1 (N260), .I2 (state_reg[0]), @@ -370595,16 +370092,16 @@ module udp_receive_buffer recv_m_data_tlast_vname ( .Q (recv_m_data_tlast), .CLK (recv_clk_i), - .D (_N103520)); + .D (_N104332)); // defparam recv_m_data_tlast_vname.orig_name = recv_m_data_tlast; // ../../sources/designs/udp_osd/eth_udp/inout_buffer/udp_receive_buffer.v:212 GTP_LUT5 /* recv_m_data_tlast_rs_mux */ #( .INIT(32'b01000100000000000101010001010000)) recv_m_data_tlast_rs_mux ( - .Z (_N103520), + .Z (_N104332), .I0 (sync_vg_100m), - .I1 (_N97495), + .I1 (_N98274), .I2 (recv_m_data_tlast), .I3 (fifo_rd_data_en), .I4 (pkt_rd_done)); @@ -370792,14 +370289,14 @@ module udp_receive_buffer recv_m_data_tvalid_vname ( .Q (recv_m_data_tvalid), .CLK (recv_clk_i), - .D (_N103522)); + .D (_N104334)); // defparam recv_m_data_tvalid_vname.orig_name = recv_m_data_tvalid; // ../../sources/designs/udp_osd/eth_udp/inout_buffer/udp_receive_buffer.v:225 GTP_LUT5M /* recv_m_data_tvalid_rs_mux */ #( .INIT(32'b00000111000000000000101000000000)) recv_m_data_tvalid_rs_mux ( - .Z (_N103522), + .Z (_N104334), .I0 (recv_m_data_tready), .I1 (N120), .I2 (sync_vg_100m), @@ -370917,12 +370414,15 @@ endmodule module eth_udp ( input [3:0] eth_rxd, + input [9:0] \udp_osd_inst/char_osd_inst/char_buf_reader_inst/N907 , + input [4:0] \udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_reg , input N64_0, + input _N97124, input clk, input eth_rx_ctl, input eth_rxc, input \u_udp_transmit_buffer/N4 , - input \udp_receive_buffer_inst/pkt_rd_done , + input \udp_osd_inst/char_osd_inst/char_buf_reader_inst/N73 , input udp_rx_m_data_tready, output [3:0] eth_txd, output [7:0] udp_rx_m_data_tdata, @@ -370930,49 +370430,47 @@ module eth_udp output [15:0] udp_rx_pkt_byte_num, output [7:0] udp_rx_pkt_data, output [15:0] udp_rx_pkt_dest_port, - output _N97297, + output _N98118, output eth_tx_ctl, output eth_txc, output gmii_clk, + output \udp_osd_inst/char_osd_inst/char_buf_reader_inst/N714 , output \udp_receive_buffer_inst/N222 , - output udp_rx_m_data_tlast, + output \udp_receive_buffer_inst/pkt_rd_done , output udp_rx_m_data_tvalid, output udp_rx_pkt_en, output udp_rx_pkt_start ); wire N72; wire N72_cpy; - wire _N84201; - wire _N95844; - wire _N95913; - wire _N95922; - wire _N95923; - wire _N95925; - wire _N95955; - wire _N95958; - wire _N96003; - wire _N96007; - wire _N96072; - wire _N96085; - wire _N96096; - wire _N96358; - wire _N96385; - wire _N96556; - wire _N96693; - wire _N96774; - wire _N96775; - wire _N96776; - wire _N96780; - wire _N97006; - wire _N97022; - wire _N97473; - wire _N98508; - wire _N104315; - wire _N106910; - wire _N106911; - wire _N106920; - wire _N107965; - wire _N108056; + wire _N82337; + wire _N82491; + wire _N96653; + wire _N96654; + wire _N96657; + wire _N96703; + wire _N96734; + wire _N96787; + wire _N97121; + wire _N97122; + wire _N97125; + wire _N97265; + wire _N97327; + wire _N97338; + wire _N97341; + wire _N97535; + wire _N97539; + wire _N97540; + wire _N97542; + wire _N97554; + wire _N97887; + wire _N98258; + wire _N100572; + wire _N105154; + wire _N107734; + wire _N107735; + wire _N107744; + wire _N108899; wire arp_gmii_tx_en; wire [7:0] arp_gmii_txd; wire arp_rx_done; @@ -371001,30 +370499,31 @@ module eth_udp wire \u_arp/u_arp_tx/N376_inv ; wire \u_arp/u_arp_tx/N409_inv ; wire \u_eth_ctrl/icmp_tx_req_d0 ; + wire \u_icmp/u_icmp_rx/N1265 ; + wire \u_icmp/u_icmp_rx/N1269 ; wire [4:0] \u_icmp/u_icmp_rx/cnt ; wire [6:0] \u_icmp/u_icmp_rx/cur_state_reg ; - wire \u_icmp/u_icmp_rx/error_en ; wire \u_icmp/u_icmp_rx/skip_en ; - wire \u_icmp/u_icmp_tx/N969 ; - wire \u_icmp/u_icmp_tx/N973 ; wire [7:0] \u_icmp/u_icmp_tx/cur_state_reg ; wire \u_icmp/u_icmp_tx/skip_en ; wire \u_udp/u_udp_rx/N586 ; wire [4:0] \u_udp/u_udp_rx/cnt ; wire [6:0] \u_udp/u_udp_rx/cur_state_reg ; + wire \u_udp/u_udp_rx/error_en ; wire [6:0] \u_udp/u_udp_rx/next_state ; wire \u_udp/u_udp_rx/skip_en ; wire [15:0] \udp_receive_buffer_inst/cnt ; wire udp_rx_pkt_done; wire \u_arp_u_arp_rx/cnt[0]_floating ; + wire \u_icmp_u_icmp_rx/cnt[0]_floating ; wire \u_icmp_u_icmp_rx/cur_state_reg[0]_floating ; - wire \u_udp_u_udp_rx/cur_state_reg[0]_floating ; - wire \u_udp_u_udp_rx/cur_state_reg[1]_floating ; + wire \u_icmp_u_icmp_rx/cur_state_reg[1]_floating ; + wire \u_icmp_u_icmp_rx/cur_state_reg[2]_floating ; + wire \u_icmp_u_icmp_rx/cur_state_reg[3]_floating ; + wire \u_udp_u_udp_rx/cnt[1]_floating ; + wire \u_udp_u_udp_rx/cnt[2]_floating ; wire \u_udp_u_udp_rx/cur_state_reg[2]_floating ; - wire \u_udp_u_udp_rx/cur_state_reg[5]_floating ; - wire \u_udp_u_udp_rx/cur_state_reg[6]_floating ; - wire \u_udp_u_udp_rx/next_state[0]_floating ; - wire \u_udp_u_udp_rx/next_state[1]_floating ; + wire \u_udp_u_udp_rx/cur_state_reg[3]_floating ; wire \u_udp_u_udp_rx/next_state[5]_floating ; wire \u_udp_u_udp_rx/next_state[6]_floating ; wire \udp_receive_buffer_inst_cnt[0]_floating ; @@ -371039,10 +370538,10 @@ module eth_udp // LUT = I0&I1 ; // ../../sources/designs/udp_osd/eth_udp/eth_udp.v:265 - GTP_LUT5 /* N72_16 */ #( + GTP_LUT5 /* N72_18 */ #( .INIT(32'b00000000000000000001000000000000)) - N72_16 ( - .Z (_N104315), + N72_18 ( + .Z (_N105154), .I0 (udp_rx_pkt_dest_port[0]), .I1 (udp_rx_pkt_dest_port[2]), .I2 (udp_rx_pkt_dest_port[6]), @@ -371050,47 +370549,47 @@ module eth_udp .I4 (udp_rx_pkt_dest_port[15])); // LUT = ~I0&~I1&I2&I3&~I4 ; - GTP_LUT5 /* N72_17 */ #( + GTP_LUT5 /* N72_19 */ #( .INIT(32'b00000000000000010000000000000000)) - N72_17 ( - .Z (_N97297), + N72_19 ( + .Z (_N98118), .I0 (udp_rx_pkt_dest_port[11]), .I1 (udp_rx_pkt_dest_port[12]), .I2 (udp_rx_pkt_dest_port[13]), .I3 (udp_rx_pkt_dest_port[14]), - .I4 (_N104315)); + .I4 (_N105154)); // LUT = ~I0&~I1&~I2&~I3&I4 ; - GTP_LUT4 /* N72_23 */ #( + GTP_LUT4 /* N72_25 */ #( .INIT(16'b0001000000000000)) - N72_23 ( - .Z (_N106920), + N72_25 ( + .Z (_N107744), .I0 (udp_rx_pkt_dest_port[3]), .I1 (udp_rx_pkt_dest_port[5]), .I2 (udp_rx_pkt_dest_port[10]), - .I3 (_N97297)); + .I3 (_N98118)); // LUT = ~I0&~I1&I2&I3 ; - GTP_LUT5 /* N72_24 */ #( + GTP_LUT5 /* N72_26 */ #( .INIT(32'b00000000000010000000000000000000)) - N72_24 ( + N72_26 ( .Z (N72), .I0 (udp_rx_pkt_dest_port[1]), .I1 (udp_rx_pkt_dest_port[4]), .I2 (udp_rx_pkt_dest_port[8]), .I3 (udp_rx_pkt_dest_port[9]), - .I4 (_N106920)); + .I4 (_N107744)); // LUT = I0&I1&~I2&~I3&I4 ; - GTP_LUT5 /* N72_24_cpy */ #( + GTP_LUT5 /* N72_26_cpy */ #( .INIT(32'b00000000000010000000000000000000)) - N72_24_cpy ( + N72_26_cpy ( .Z (N72_cpy), .I0 (udp_rx_pkt_dest_port[1]), .I1 (udp_rx_pkt_dest_port[4]), .I2 (udp_rx_pkt_dest_port[8]), .I3 (udp_rx_pkt_dest_port[9]), - .I4 (_N106920)); + .I4 (_N107744)); // LUT = I0&I1&~I2&~I3&I4 ; async_fifo_2048x8_unq6 icmp_async_fifo_2048x8b ( @@ -371108,19 +370607,17 @@ module eth_udp .gmii_txd_data (arp_gmii_txd), .\u_arp_rx/cnt ({\u_arp/u_arp_rx/cnt [4] , \u_arp/u_arp_rx/cnt [3] , \u_arp/u_arp_rx/cnt [2] , \u_arp/u_arp_rx/cnt [1] , \u_arp_u_arp_rx/cnt[0]_floating }), .gmii_rxd_data (gmii_rxd_data), - .\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt ({\u_icmp/u_icmp_rx/cnt [4] , \u_icmp/u_icmp_rx/cnt [3] , 1'bx, 1'bx, \u_icmp/u_icmp_rx/cnt [0] }), - .\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg ({\u_icmp/u_icmp_rx/cur_state_reg [6] , \u_icmp/u_icmp_rx/cur_state_reg [5] , \u_icmp/u_icmp_rx/cur_state_reg [4] , \u_icmp/u_icmp_rx/cur_state_reg [3] , \u_icmp/u_icmp_rx/cur_state_reg [2] , \u_icmp/u_icmp_rx/cur_state_reg [1] , 1'bx}), + .\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt ({\u_icmp/u_icmp_rx/cnt [4] , \u_icmp/u_icmp_rx/cnt [3] , \u_icmp/u_icmp_rx/cnt [2] , 1'bx, 1'bx}), .\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt ({\u_udp/u_udp_rx/cnt [4] , \u_udp/u_udp_rx/cnt [3] , 1'bx, 1'bx, \u_udp/u_udp_rx/cnt [0] }), + .\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg ({\u_udp/u_udp_rx/cur_state_reg [6] , 1'bx, 1'bx, 1'bx, 1'bx, \u_udp/u_udp_rx/cur_state_reg [1] , \u_udp/u_udp_rx/cur_state_reg [0] }), .\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/next_state ({1'bx, 1'bx, \u_udp/u_udp_rx/next_state [4] , \u_udp/u_udp_rx/next_state [3] , \u_udp/u_udp_rx/next_state [2] , 1'bx, 1'bx}), - ._N95922 (_N95922), - ._N95923 (_N95923), - ._N95925 (_N95925), - ._N96007 (_N96007), - ._N96085 (_N96085), - ._N96096 (_N96096), - ._N96556 (_N96556), - ._N97006 (_N97006), - ._N97473 (_N97473), + ._N97121 (_N97121), + ._N97122 (_N97122), + ._N97327 (_N97327), + ._N97338 (_N97338), + ._N97341 (_N97341), + ._N97887 (_N97887), + ._N98258 (_N98258), .arp_rx_done (arp_rx_done), .arp_rx_type (arp_rx_type), .gmii_txd_valid (arp_gmii_tx_en), @@ -371129,19 +370626,17 @@ module eth_udp .\u_arp_tx/N376_inv (\u_arp/u_arp_tx/N376_inv ), .\u_arp_tx/N409_inv (\u_arp/u_arp_tx/N409_inv ), .\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/N586 (\u_udp/u_udp_rx/N586 ), - ._N84201 (_N84201), - ._N96358 (_N96358), - ._N96693 (_N96693), - ._N96775 (_N96775), - ._N96776 (_N96776), - ._N108056 (_N108056), + ._N96653 (_N96653), + ._N97535 (_N97535), + ._N97539 (_N97539), + ._N97540 (_N97540), .arp_tx_en (arp_tx_en), .gmii_rx_clk (gmii_clk), .gmii_rxd_valid (gmii_rxd_valid), .sync_vg_100m (\u_udp_transmit_buffer/N4 ), .\u_arp_rx/N559 (\u_arp/u_arp_rx/N559 ), - .\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/error_en (\u_icmp/u_icmp_rx/error_en ), - .\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/skip_en (\u_icmp/u_icmp_rx/skip_en )); + .\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/error_en (\u_udp/u_udp_rx/error_en ), + .\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/skip_en (\u_udp/u_udp_rx/skip_en )); // ../../sources/designs/udp_osd/eth_udp/eth_udp.v:137 eth_ctrl u_eth_ctrl ( @@ -371182,56 +370677,53 @@ module eth_udp icmp u_icmp ( .gmii_txd_data (icmp_gmii_txd), .rec_data (icmp_rec_data), - .\u_icmp_rx/cnt ({\u_icmp/u_icmp_rx/cnt [4] , \u_icmp/u_icmp_rx/cnt [3] , \u_icmp/u_icmp_rx/cnt [2] , \u_icmp/u_icmp_rx/cnt [1] , \u_icmp/u_icmp_rx/cnt [0] }), - .\u_icmp_rx/cur_state_reg ({\u_icmp/u_icmp_rx/cur_state_reg [6] , \u_icmp/u_icmp_rx/cur_state_reg [5] , \u_icmp/u_icmp_rx/cur_state_reg [4] , \u_icmp/u_icmp_rx/cur_state_reg [3] , \u_icmp/u_icmp_rx/cur_state_reg [2] , \u_icmp/u_icmp_rx/cur_state_reg [1] , \u_icmp_u_icmp_rx/cur_state_reg[0]_floating }), + .\u_icmp_rx/cnt ({\u_icmp/u_icmp_rx/cnt [4] , \u_icmp/u_icmp_rx/cnt [3] , \u_icmp/u_icmp_rx/cnt [2] , \u_icmp/u_icmp_rx/cnt [1] , \u_icmp_u_icmp_rx/cnt[0]_floating }), + .\u_icmp_rx/cur_state_reg ({\u_icmp/u_icmp_rx/cur_state_reg [6] , \u_icmp/u_icmp_rx/cur_state_reg [5] , \u_icmp/u_icmp_rx/cur_state_reg [4] , \u_icmp_u_icmp_rx/cur_state_reg[3]_floating , \u_icmp_u_icmp_rx/cur_state_reg[2]_floating , \u_icmp_u_icmp_rx/cur_state_reg[1]_floating , \u_icmp_u_icmp_rx/cur_state_reg[0]_floating }), .\u_icmp_tx/cur_state_reg ({\u_icmp/u_icmp_tx/cur_state_reg [7] , \u_icmp/u_icmp_tx/cur_state_reg [6] , \u_icmp/u_icmp_tx/cur_state_reg [5] , \u_icmp/u_icmp_tx/cur_state_reg [4] , \u_icmp/u_icmp_tx/cur_state_reg [3] , \u_icmp/u_icmp_tx/cur_state_reg [2] , \u_icmp/u_icmp_tx/cur_state_reg [1] , \u_icmp/u_icmp_tx/cur_state_reg [0] }), .des_ip (des_ip), .des_mac (des_mac), .gmii_rxd_data (gmii_rxd_data), .\udp_osd_inst/eth_udp_inst/tx_data (tx_data), .\udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt ({\u_arp/u_arp_rx/cnt [4] , \u_arp/u_arp_rx/cnt [3] , \u_arp/u_arp_rx/cnt [2] , \u_arp/u_arp_rx/cnt [1] , 1'bx}), - .\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cnt ({1'bx, 1'bx, \u_udp/u_udp_rx/cnt [2] , \u_udp/u_udp_rx/cnt [1] , 1'bx}), - .\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg ({1'bx, 1'bx, \u_udp/u_udp_rx/cur_state_reg [4] , \u_udp/u_udp_rx/cur_state_reg [3] , 1'bx, 1'bx, 1'bx}), - .\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/next_state ({1'bx, 1'bx, 1'bx, \u_udp/u_udp_rx/next_state [3] , \u_udp/u_udp_rx/next_state [2] , 1'bx, 1'bx}), + .\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/cur_state_reg ({1'bx, \u_udp/u_udp_rx/cur_state_reg [5] , \u_udp/u_udp_rx/cur_state_reg [4] , 1'bx, 1'bx, 1'bx, 1'bx}), + .\udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/next_state ({1'bx, 1'bx, \u_udp/u_udp_rx/next_state [4] , \u_udp/u_udp_rx/next_state [3] , \u_udp/u_udp_rx/next_state [2] , \u_udp/u_udp_rx/next_state [1] , \u_udp/u_udp_rx/next_state [0] }), .\udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/cnt ({\udp_receive_buffer_inst/cnt [15] , \udp_receive_buffer_inst/cnt [14] , \udp_receive_buffer_inst/cnt [13] , \udp_receive_buffer_inst/cnt [12] , \udp_receive_buffer_inst/cnt [11] , \udp_receive_buffer_inst/cnt [10] , \udp_receive_buffer_inst/cnt [9] , \udp_receive_buffer_inst/cnt [8] , \udp_receive_buffer_inst/cnt [7] , \udp_receive_buffer_inst/cnt [6] , \udp_receive_buffer_inst/cnt [5] , \udp_receive_buffer_inst/cnt [4] , \udp_receive_buffer_inst/cnt [3] , \udp_receive_buffer_inst/cnt [2] , 1'bx, 1'bx}), - ._N84201 (_N84201), - ._N96072 (_N96072), - ._N96385 (_N96385), - ._N96774 (_N96774), - ._N96776 (_N96776), - ._N98508 (_N98508), - ._N106910 (_N106910), - ._N106911 (_N106911), + ._N82337 (_N82337), + ._N96653 (_N96653), + ._N96787 (_N96787), + ._N97539 (_N97539), + ._N97540 (_N97540), + ._N97542 (_N97542), + ._N100572 (_N100572), + ._N107734 (_N107734), + ._N107735 (_N107735), + ._N108899 (_N108899), .gmii_txd_valid (icmp_gmii_tx_en), .rec_en (icmp_rec_en), .rec_pkt_done (icmp_tx_start_en), - .\u_icmp_rx/error_en (\u_icmp/u_icmp_rx/error_en ), + .\u_icmp_rx/N1265 (\u_icmp/u_icmp_rx/N1265 ), .\u_icmp_rx/skip_en (\u_icmp/u_icmp_rx/skip_en ), - .\u_icmp_tx/N969 (\u_icmp/u_icmp_tx/N969 ), .\u_icmp_tx/skip_en (\u_icmp/u_icmp_tx/skip_en ), .\udp_osd_inst/eth_udp_inst/tx_req (tx_req), - ._N95844 (_N95844), - ._N95913 (_N95913), - ._N95922 (_N95922), - ._N95925 (_N95925), - ._N95955 (_N95955), - ._N95958 (_N95958), - ._N96003 (_N96003), - ._N96007 (_N96007), - ._N96085 (_N96085), - ._N96096 (_N96096), - ._N96358 (_N96358), - ._N96556 (_N96556), - ._N96693 (_N96693), - ._N96780 (_N96780), - ._N97022 (_N97022), - ._N97473 (_N97473), - ._N107965 (_N107965), + .\udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N559 (\u_arp/u_arp_rx/N559 ), + ._N82491 (_N82491), + ._N96654 (_N96654), + ._N96657 (_N96657), + ._N96703 (_N96703), + ._N96734 (_N96734), + ._N97125 (_N97125), + ._N97265 (_N97265), + ._N97327 (_N97327), + ._N97338 (_N97338), + ._N97535 (_N97535), + ._N97554 (_N97554), + ._N98258 (_N98258), .gmii_rx_clk (gmii_clk), .gmii_rxd_valid (gmii_rxd_valid), .sync_vg_100m (\u_udp_transmit_buffer/N4 ), - .\u_icmp_tx/N973 (\u_icmp/u_icmp_tx/N973 ), + .\u_icmp_rx/N1269 (\u_icmp/u_icmp_rx/N1269 ), .\udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N52 (\u_arp/u_arp_rx/N52 ), + .\udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N366 (\u_arp/u_arp_rx/N366 ), .\udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376_inv (\u_arp/u_arp_tx/N376_inv ), .\udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N409_inv (\u_arp/u_arp_tx/N409_inv ), .\udp_osd_inst/eth_udp_inst/u_eth_ctrl/icmp_tx_req_d0 (\u_eth_ctrl/icmp_tx_req_d0 ), @@ -371242,67 +370734,71 @@ module eth_udp .rec_byte_num (udp_rx_pkt_byte_num), .rec_data (udp_rx_pkt_data), .rec_dest_port (udp_rx_pkt_dest_port), - .\u_udp_rx/cnt ({\u_udp/u_udp_rx/cnt [4] , \u_udp/u_udp_rx/cnt [3] , \u_udp/u_udp_rx/cnt [2] , \u_udp/u_udp_rx/cnt [1] , \u_udp/u_udp_rx/cnt [0] }), - .\u_udp_rx/cur_state_reg ({\u_udp_u_udp_rx/cur_state_reg[6]_floating , \u_udp_u_udp_rx/cur_state_reg[5]_floating , \u_udp/u_udp_rx/cur_state_reg [4] , \u_udp/u_udp_rx/cur_state_reg [3] , \u_udp_u_udp_rx/cur_state_reg[2]_floating , \u_udp_u_udp_rx/cur_state_reg[1]_floating , \u_udp_u_udp_rx/cur_state_reg[0]_floating }), - .\u_udp_rx/next_state ({\u_udp_u_udp_rx/next_state[6]_floating , \u_udp_u_udp_rx/next_state[5]_floating , \u_udp/u_udp_rx/next_state [4] , \u_udp/u_udp_rx/next_state [3] , \u_udp/u_udp_rx/next_state [2] , \u_udp_u_udp_rx/next_state[1]_floating , \u_udp_u_udp_rx/next_state[0]_floating }), + .\u_udp_rx/cnt ({\u_udp/u_udp_rx/cnt [4] , \u_udp/u_udp_rx/cnt [3] , \u_udp_u_udp_rx/cnt[2]_floating , \u_udp_u_udp_rx/cnt[1]_floating , \u_udp/u_udp_rx/cnt [0] }), + .\u_udp_rx/cur_state_reg ({\u_udp/u_udp_rx/cur_state_reg [6] , \u_udp/u_udp_rx/cur_state_reg [5] , \u_udp/u_udp_rx/cur_state_reg [4] , \u_udp_u_udp_rx/cur_state_reg[3]_floating , \u_udp_u_udp_rx/cur_state_reg[2]_floating , \u_udp/u_udp_rx/cur_state_reg [1] , \u_udp/u_udp_rx/cur_state_reg [0] }), + .\u_udp_rx/next_state ({\u_udp_u_udp_rx/next_state[6]_floating , \u_udp_u_udp_rx/next_state[5]_floating , \u_udp/u_udp_rx/next_state [4] , \u_udp/u_udp_rx/next_state [3] , \u_udp/u_udp_rx/next_state [2] , \u_udp/u_udp_rx/next_state [1] , \u_udp/u_udp_rx/next_state [0] }), .gmii_rxd_data (gmii_rxd_data), - .\udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/cnt ({\u_arp/u_arp_rx/cnt [4] , \u_arp/u_arp_rx/cnt [3] , \u_arp/u_arp_rx/cnt [2] , \u_arp/u_arp_rx/cnt [1] , 1'bx}), .\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cnt ({\u_icmp/u_icmp_rx/cnt [4] , \u_icmp/u_icmp_rx/cnt [3] , \u_icmp/u_icmp_rx/cnt [2] , \u_icmp/u_icmp_rx/cnt [1] , 1'bx}), - ._N95844 (_N95844), - ._N96358 (_N96358), - ._N96693 (_N96693), - ._N96775 (_N96775), - ._N96780 (_N96780), - ._N107965 (_N107965), - ._N108056 (_N108056), + .\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/cur_state_reg ({\u_icmp/u_icmp_rx/cur_state_reg [6] , \u_icmp/u_icmp_rx/cur_state_reg [5] , \u_icmp/u_icmp_rx/cur_state_reg [4] , 1'bx, 1'bx, 1'bx, 1'bx}), + ._N82491 (_N82491), + ._N96654 (_N96654), + ._N96657 (_N96657), + ._N97535 (_N97535), + ._N97554 (_N97554), .rec_en (udp_rx_pkt_en), .rec_pkt_done (udp_rx_pkt_done), .rec_pkt_start (udp_rx_pkt_start), + .\u_udp_rx/error_en (\u_udp/u_udp_rx/error_en ), .\u_udp_rx/skip_en (\u_udp/u_udp_rx/skip_en ), - .\udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N559 (\u_arp/u_arp_rx/N559 ), - ._N95923 (_N95923), - ._N96072 (_N96072), - ._N96096 (_N96096), - ._N96385 (_N96385), - ._N96556 (_N96556), - ._N96774 (_N96774), - ._N97006 (_N97006), - ._N97473 (_N97473), - ._N98508 (_N98508), + .\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1269 (\u_icmp/u_icmp_rx/N1269 ), + ._N82337 (_N82337), + ._N96653 (_N96653), + ._N96787 (_N96787), + ._N97121 (_N97121), + ._N97122 (_N97122), + ._N97327 (_N97327), + ._N97341 (_N97341), + ._N97542 (_N97542), + ._N97887 (_N97887), + ._N98258 (_N98258), + ._N100572 (_N100572), + ._N108899 (_N108899), .gmii_rx_clk (gmii_clk), .gmii_rxd_valid (gmii_rxd_valid), .sync_vg_100m (\u_udp_transmit_buffer/N4 ), .\u_udp_rx/N586 (\u_udp/u_udp_rx/N586 ), .\udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N52 (\u_arp/u_arp_rx/N52 ), - .\udp_osd_inst/eth_udp_inst/u_arp/u_arp_rx/N366 (\u_arp/u_arp_rx/N366 )); + .\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/N1265 (\u_icmp/u_icmp_rx/N1265 ), + .\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/skip_en (\u_icmp/u_icmp_rx/skip_en )); // ../../sources/designs/udp_osd/eth_udp/eth_udp.v:195 udp_receive_buffer udp_receive_buffer_inst ( .cnt ({\udp_receive_buffer_inst/cnt [15] , \udp_receive_buffer_inst/cnt [14] , \udp_receive_buffer_inst/cnt [13] , \udp_receive_buffer_inst/cnt [12] , \udp_receive_buffer_inst/cnt [11] , \udp_receive_buffer_inst/cnt [10] , \udp_receive_buffer_inst/cnt [9] , \udp_receive_buffer_inst/cnt [8] , \udp_receive_buffer_inst/cnt [7] , \udp_receive_buffer_inst/cnt [6] , \udp_receive_buffer_inst/cnt [5] , \udp_receive_buffer_inst/cnt [4] , \udp_receive_buffer_inst/cnt [3] , \udp_receive_buffer_inst/cnt [2] , \udp_receive_buffer_inst_cnt[1]_floating , \udp_receive_buffer_inst_cnt[0]_floating }), .recv_m_data_tdata (udp_rx_m_data_tdata), .recv_m_data_tsize (udp_rx_m_data_tsize), + .\udp_osd_inst/char_osd_inst/char_buf_reader_inst/N907 ({1'bx, 1'bx, \udp_osd_inst/char_osd_inst/char_buf_reader_inst/N907 [7] , 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), + .\udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_reg ({1'bx, 1'bx, 1'bx, \udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_reg [1] , \udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_reg [0] }), .\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/cur_state_reg ({\u_icmp/u_icmp_tx/cur_state_reg [7] , \u_icmp/u_icmp_tx/cur_state_reg [6] , \u_icmp/u_icmp_tx/cur_state_reg [5] , \u_icmp/u_icmp_tx/cur_state_reg [4] , \u_icmp/u_icmp_tx/cur_state_reg [3] , \u_icmp/u_icmp_tx/cur_state_reg [2] , \u_icmp/u_icmp_tx/cur_state_reg [1] , \u_icmp/u_icmp_tx/cur_state_reg [0] }), .udp_rx_data_i (udp_rx_pkt_data), .udp_rx_num_i (udp_rx_pkt_byte_num), .N222 (\udp_receive_buffer_inst/N222 ), - ._N95913 (_N95913), - ._N95955 (_N95955), - ._N95958 (_N95958), - ._N96003 (_N96003), - ._N97022 (_N97022), - .recv_m_data_tlast (udp_rx_m_data_tlast), + ._N96703 (_N96703), + ._N96734 (_N96734), + ._N97125 (_N97125), + ._N97265 (_N97265), + .pkt_rd_done (\udp_receive_buffer_inst/pkt_rd_done ), .recv_m_data_tvalid (udp_rx_m_data_tvalid), - .\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N973 (\u_icmp/u_icmp_tx/N973 ), + .\udp_osd_inst/char_osd_inst/char_buf_reader_inst/N714 (\udp_osd_inst/char_osd_inst/char_buf_reader_inst/N714 ), .N64_0 (N64_0), - ._N106910 (_N106910), - ._N106911 (_N106911), - .pkt_rd_done (\udp_receive_buffer_inst/pkt_rd_done ), + ._N97124 (_N97124), + ._N107734 (_N107734), + ._N107735 (_N107735), .recv_clk_i (clk), .recv_m_data_tready (udp_rx_m_data_tready), .sync_vg_100m (\u_udp_transmit_buffer/N4 ), + .\udp_osd_inst/char_osd_inst/char_buf_reader_inst/N73 (\udp_osd_inst/char_osd_inst/char_buf_reader_inst/N73 ), .\udp_osd_inst/eth_udp_inst/N72 (N72), .\udp_osd_inst/eth_udp_inst/N72_cpy (N72_cpy), - .\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N969 (\u_icmp/u_icmp_tx/N969 ), .\udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/skip_en (\u_icmp/u_icmp_tx/skip_en ), .udp_rx_clk_i (gmii_clk), .udp_rx_pkt_done (udp_rx_pkt_done), @@ -371338,7 +370834,7 @@ module udp_osd output [15:0] udp_rx_pkt_byte_num, output [7:0] udp_rx_pkt_data, output [15:0] udp_rx_pkt_dest_port, - output _N97297, + output _N98118, output de_out, output eth_tx_ctl, output eth_txc, @@ -371356,7 +370852,12 @@ module udp_osd wire [11:0] \N40.co ; wire [23:0] N63; wire N69; + wire _N97124; wire \char_buf_writer_inst/N11 ; + wire \char_osd_inst/char_buf_reader_inst/N73 ; + wire \char_osd_inst/char_buf_reader_inst/N714 ; + wire [9:0] \char_osd_inst/char_buf_reader_inst/N907 ; + wire [4:0] \char_osd_inst/char_buf_reader_inst/state_reg ; wire \char_osd_inst/pixels_shifter_inst/N64 ; wire \eth_udp_inst/udp_receive_buffer_inst/pkt_rd_done ; wire m_pixel_data; @@ -371369,10 +370870,21 @@ module udp_osd wire [10:0] ram_rd_addr; wire ram_wen; wire [7:0] udp_rx_data_tdata; - wire udp_rx_data_tlast; wire udp_rx_data_tready; wire [15:0] udp_rx_data_tsize; wire udp_rx_data_tvalid; + wire \char_osd_inst_char_buf_reader_inst/N907[0]_floating ; + wire \char_osd_inst_char_buf_reader_inst/N907[1]_floating ; + wire \char_osd_inst_char_buf_reader_inst/N907[2]_floating ; + wire \char_osd_inst_char_buf_reader_inst/N907[3]_floating ; + wire \char_osd_inst_char_buf_reader_inst/N907[4]_floating ; + wire \char_osd_inst_char_buf_reader_inst/N907[5]_floating ; + wire \char_osd_inst_char_buf_reader_inst/N907[6]_floating ; + wire \char_osd_inst_char_buf_reader_inst/N907[8]_floating ; + wire \char_osd_inst_char_buf_reader_inst/N907[9]_floating ; + wire \char_osd_inst_char_buf_reader_inst/state_reg[2]_floating ; + wire \char_osd_inst_char_buf_reader_inst/state_reg[3]_floating ; + wire \char_osd_inst_char_buf_reader_inst/state_reg[4]_floating ; wire \eth_udp_inst_udp_rx_pkt_dest_port[0]_floating ; wire \eth_udp_inst_udp_rx_pkt_dest_port[2]_floating ; wire \eth_udp_inst_udp_rx_pkt_dest_port[6]_floating ; @@ -371913,16 +371425,17 @@ module udp_osd .udp_rx_s_data_tdata (udp_rx_data_tdata), .udp_rx_s_data_tsize (udp_rx_data_tsize), .ram_wen (ram_wen), - .\udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/pkt_rd_done (\eth_udp_inst/udp_receive_buffer_inst/pkt_rd_done ), .udp_rx_s_data_tready (udp_rx_data_tready), .N11 (\char_buf_writer_inst/N11 ), .clk (clk), .sync_vg_100m (\eth_udp_inst/u_udp_transmit_buffer/N4 ), - .udp_rx_s_data_tlast (udp_rx_data_tlast), + .\udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/pkt_rd_done (\eth_udp_inst/udp_receive_buffer_inst/pkt_rd_done ), .udp_rx_s_data_tvalid (udp_rx_data_tvalid)); // ../../sources/designs/udp_osd/udp_osd.v:162 char_osd char_osd_inst ( + .\char_buf_reader_inst/N907 ({\char_osd_inst_char_buf_reader_inst/N907[9]_floating , \char_osd_inst_char_buf_reader_inst/N907[8]_floating , \char_osd_inst/char_buf_reader_inst/N907 [7] , \char_osd_inst_char_buf_reader_inst/N907[6]_floating , \char_osd_inst_char_buf_reader_inst/N907[5]_floating , \char_osd_inst_char_buf_reader_inst/N907[4]_floating , \char_osd_inst_char_buf_reader_inst/N907[3]_floating , \char_osd_inst_char_buf_reader_inst/N907[2]_floating , \char_osd_inst_char_buf_reader_inst/N907[1]_floating , \char_osd_inst_char_buf_reader_inst/N907[0]_floating }), + .\char_buf_reader_inst/state_reg ({\char_osd_inst_char_buf_reader_inst/state_reg[4]_floating , \char_osd_inst_char_buf_reader_inst/state_reg[3]_floating , \char_osd_inst_char_buf_reader_inst/state_reg[2]_floating , \char_osd_inst/char_buf_reader_inst/state_reg [1] , \char_osd_inst/char_buf_reader_inst/state_reg [0] }), .m_pixel_posX (m_pixel_posX), .m_pixel_posY (m_pixel_posY), .ram_rd_addr (ram_rd_addr), @@ -371931,8 +371444,11 @@ module udp_osd .cfg_start_posX (cfg_start_posX), .cfg_start_posY (cfg_start_posY), .ram_dout (ram_dout), + ._N97124 (_N97124), + .\char_buf_reader_inst/N73 (\char_osd_inst/char_buf_reader_inst/N73 ), .m_pixel_data (m_pixel_data), .m_pixel_valid (m_pixel_valid), + .\char_buf_reader_inst/N714 (\char_osd_inst/char_buf_reader_inst/N714 ), .clk (clk), .hdmi_de_out1 (de_in), .\pixels_shifter_inst/N64 (\char_osd_inst/pixels_shifter_inst/N64 ), @@ -371970,21 +371486,25 @@ module udp_osd .udp_rx_pkt_data (udp_rx_pkt_data), .udp_rx_pkt_dest_port ({\eth_udp_inst_udp_rx_pkt_dest_port[15]_floating , \eth_udp_inst_udp_rx_pkt_dest_port[14]_floating , \eth_udp_inst_udp_rx_pkt_dest_port[13]_floating , \eth_udp_inst_udp_rx_pkt_dest_port[12]_floating , \eth_udp_inst_udp_rx_pkt_dest_port[11]_floating , udp_rx_pkt_dest_port[10], udp_rx_pkt_dest_port[9], udp_rx_pkt_dest_port[8], \eth_udp_inst_udp_rx_pkt_dest_port[7]_floating , \eth_udp_inst_udp_rx_pkt_dest_port[6]_floating , udp_rx_pkt_dest_port[5], udp_rx_pkt_dest_port[4], udp_rx_pkt_dest_port[3], \eth_udp_inst_udp_rx_pkt_dest_port[2]_floating , udp_rx_pkt_dest_port[1], \eth_udp_inst_udp_rx_pkt_dest_port[0]_floating }), .eth_rxd (eth_rxd), - ._N97297 (_N97297), + .\udp_osd_inst/char_osd_inst/char_buf_reader_inst/N907 ({1'bx, 1'bx, \char_osd_inst/char_buf_reader_inst/N907 [7] , 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), + .\udp_osd_inst/char_osd_inst/char_buf_reader_inst/state_reg ({1'bx, 1'bx, 1'bx, \char_osd_inst/char_buf_reader_inst/state_reg [1] , \char_osd_inst/char_buf_reader_inst/state_reg [0] }), + ._N98118 (_N98118), .eth_tx_ctl (eth_tx_ctl), .eth_txc (eth_txc), .gmii_clk (gmii_clk), + .\udp_osd_inst/char_osd_inst/char_buf_reader_inst/N714 (\char_osd_inst/char_buf_reader_inst/N714 ), .\udp_receive_buffer_inst/N222 (\char_buf_writer_inst/N11 ), - .udp_rx_m_data_tlast (udp_rx_data_tlast), + .\udp_receive_buffer_inst/pkt_rd_done (\eth_udp_inst/udp_receive_buffer_inst/pkt_rd_done ), .udp_rx_m_data_tvalid (udp_rx_data_tvalid), .udp_rx_pkt_en (udp_rx_pkt_en), .udp_rx_pkt_start (udp_rx_pkt_start), .N64_0 (N64_0), + ._N97124 (_N97124), .clk (clk), .eth_rx_ctl (eth_rx_ctl), .eth_rxc (eth_rxc), .\u_udp_transmit_buffer/N4 (\eth_udp_inst/u_udp_transmit_buffer/N4 ), - .\udp_receive_buffer_inst/pkt_rd_done (\eth_udp_inst/udp_receive_buffer_inst/pkt_rd_done ), + .\udp_osd_inst/char_osd_inst/char_buf_reader_inst/N73 (\char_osd_inst/char_buf_reader_inst/N73 ), .udp_rx_m_data_tready (udp_rx_data_tready)); // ../../sources/designs/udp_osd/udp_osd.v:123 @@ -372179,7 +371699,7 @@ module udp_wr_mem input [7:0] udp_rx_data, input [15:0] udp_rx_dest_port, input [15:0] udp_rx_num, - input _N97297, + input _N98118, input clk, input sync_vg_100m, input udp_rx_start, @@ -372243,44 +371763,45 @@ module udp_wr_mem wire [15:0] N724; wire N727; wire N730; + wire [7:0] N731; + wire [7:0] N784; wire [4:0] N790; wire _N6; wire _N12; wire _N16; wire _N24; - wire _N15066; - wire _N15067; - wire _N15068; - wire _N15069; - wire _N15070; - wire _N15071; - wire _N15072; - wire _N40422; - wire _N40458; - wire _N40496; - wire _N40532; - wire _N40585; - wire _N40603; - wire _N40636; - wire _N40693; - wire _N66380; - wire _N66433; - wire _N66473; - wire _N66494; - wire _N66527; - wire _N66573; - wire _N66598; - wire _N66641; - wire _N97138; - wire _N97274; - wire _N97275; - wire _N97276; - wire _N97277; - wire _N104284; - wire _N104290; - wire _N104294; - wire _N104298; - wire _N104323; + wire _N13813; + wire _N13814; + wire _N13815; + wire _N13816; + wire _N13817; + wire _N13818; + wire _N13819; + wire _N38381; + wire _N38424; + wire _N38463; + wire _N38489; + wire _N38530; + wire _N38570; + wire _N38599; + wire _N38638; + wire _N67380; + wire _N67428; + wire _N67499; + wire _N67541; + wire _N67567; + wire _N67609; + wire _N67638; + wire _N97909; + wire _N98046; + wire _N98047; + wire _N98048; + wire _N98049; + wire _N105123; + wire _N105129; + wire _N105133; + wire _N105137; + wire _N105162; wire [7:0] data_count; wire [7:0] index; wire [15:0] pkt_data_cnt; @@ -372613,7 +372134,7 @@ module udp_wr_mem .I4_TO_CARRY("FALSE"), .I4_TO_LUT("FALSE")) N17_1_0 ( - .COUT (_N15066), + .COUT (_N13813), .Z (), .CIN (), .I0 (), @@ -372633,9 +372154,9 @@ module udp_wr_mem .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_1 ( - .COUT (_N15067), - .Z (_N40458), - .CIN (_N15066), + .COUT (_N13814), + .Z (_N38424), + .CIN (_N13813), .I0 (), .I1 (index[1]), .I2 (state_reg[2]), @@ -372653,9 +372174,9 @@ module udp_wr_mem .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_2 ( - .COUT (_N15068), - .Z (_N40496), - .CIN (_N15067), + .COUT (_N13815), + .Z (_N38463), + .CIN (_N13814), .I0 (), .I1 (index[2]), .I2 (state_reg[2]), @@ -372673,9 +372194,9 @@ module udp_wr_mem .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_3 ( - .COUT (_N15069), - .Z (_N40532), - .CIN (_N15068), + .COUT (_N13816), + .Z (_N38489), + .CIN (_N13815), .I0 (), .I1 (index[3]), .I2 (state_reg[2]), @@ -372693,9 +372214,9 @@ module udp_wr_mem .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_4 ( - .COUT (_N15070), - .Z (_N40585), - .CIN (_N15069), + .COUT (_N13817), + .Z (_N38530), + .CIN (_N13816), .I0 (), .I1 (index[4]), .I2 (state_reg[2]), @@ -372713,9 +372234,9 @@ module udp_wr_mem .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_5 ( - .COUT (_N15071), - .Z (_N40603), - .CIN (_N15070), + .COUT (_N13818), + .Z (_N38570), + .CIN (_N13817), .I0 (), .I1 (index[5]), .I2 (state_reg[2]), @@ -372733,9 +372254,9 @@ module udp_wr_mem .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N17_1_6 ( - .COUT (_N15072), - .Z (_N40636), - .CIN (_N15071), + .COUT (_N13819), + .Z (_N38599), + .CIN (_N13818), .I0 (), .I1 (index[6]), .I2 (state_reg[2]), @@ -372754,8 +372275,8 @@ module udp_wr_mem .I4_TO_LUT("FALSE")) N17_1_7 ( .COUT (), - .Z (_N40693), - .CIN (_N15072), + .Z (_N38638), + .CIN (_N13819), .I0 (), .I1 (index[7]), .I2 (state_reg[2]), @@ -372766,64 +372287,44 @@ module udp_wr_mem // CARRY = (I1) ? CIN : (I4) ; // ../../sources/designs/others/udp_wr_mem.v:57 - GTP_LUT5CARRY /* \N30_1.fsub_0 */ #( - .INIT(32'b10101010101010100000000000000000), - .ID_TO_LUT("FALSE"), - .CIN_TO_LUT("FALSE"), - .I4_TO_CARRY("FALSE"), - .I4_TO_LUT("FALSE")) - \N30_1.fsub_0 ( - .COUT (\N30_1.co [0] ), - .Z (), - .CIN (), - .I0 (data_count[0]), - .I1 (), - .I2 (), - .I3 (), - .I4 (), - .ID ()); - // LUT = I0 ; - // CARRY = (1'b0) ? CIN : (I0) ; - // ../../sources/designs/others/udp_wr_mem.v:70 - GTP_LUT5CARRY /* \N30_1.fsub_1 */ #( - .INIT(32'b10011111100100000011001100110011), + .INIT(32'b10011001100110010000000000000000), .ID_TO_LUT("FALSE"), - .CIN_TO_LUT("TRUE"), + .CIN_TO_LUT("FALSE"), .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) \N30_1.fsub_1 ( .COUT (\N30_1.co [1] ), - .Z (_N66433), - .CIN (\N30_1.co [0] ), - .I0 (), + .Z (N784[1]), + .CIN (), + .I0 (data_count[0]), .I1 (data_count[1]), - .I2 (state_reg[2]), - .I3 (udp_rx_data[1]), - .I4 (data_count[1]), + .I2 (), + .I3 (), + .I4 (1'b1), .ID ()); - // LUT = (~I2&I3)|(~CIN&~I1&I2)|(CIN&I1&I2) ; - // CARRY = (~I1) ? CIN : (I4) ; + // LUT = ~I1^I0 ; + // CARRY = (1'b0) ? CIN : (I4) ; // ../../sources/designs/others/udp_wr_mem.v:70 GTP_LUT5CARRY /* \N30_1.fsub_2 */ #( - .INIT(32'b10011111100100000011001100110011), + .INIT(32'b11100001111000011111111011111110), .ID_TO_LUT("FALSE"), - .CIN_TO_LUT("TRUE"), + .CIN_TO_LUT("FALSE"), .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) \N30_1.fsub_2 ( .COUT (\N30_1.co [2] ), - .Z (_N66473), + .Z (N784[2]), .CIN (\N30_1.co [1] ), - .I0 (), - .I1 (data_count[2]), - .I2 (state_reg[2]), - .I3 (udp_rx_data[2]), - .I4 (data_count[2]), + .I0 (data_count[0]), + .I1 (data_count[1]), + .I2 (data_count[2]), + .I3 (), + .I4 (1'b0), .ID ()); - // LUT = (~I2&I3)|(~CIN&~I1&I2)|(CIN&I1&I2) ; - // CARRY = (~I1) ? CIN : (I4) ; + // LUT = (~I0&~I1&~I2)|(I1&I2)|(I0&I2) ; + // CARRY = ((I2)|(I1)|(I0)) ? CIN : (I4) ; // ../../sources/designs/others/udp_wr_mem.v:70 GTP_LUT5CARRY /* \N30_1.fsub_3 */ #( @@ -372834,7 +372335,7 @@ module udp_wr_mem .I4_TO_LUT("FALSE")) \N30_1.fsub_3 ( .COUT (\N30_1.co [3] ), - .Z (_N66494), + .Z (_N67499), .CIN (\N30_1.co [2] ), .I0 (), .I1 (data_count[3]), @@ -372854,7 +372355,7 @@ module udp_wr_mem .I4_TO_LUT("FALSE")) \N30_1.fsub_4 ( .COUT (\N30_1.co [4] ), - .Z (_N66527), + .Z (_N67541), .CIN (\N30_1.co [3] ), .I0 (), .I1 (data_count[4]), @@ -372874,7 +372375,7 @@ module udp_wr_mem .I4_TO_LUT("FALSE")) \N30_1.fsub_5 ( .COUT (\N30_1.co [5] ), - .Z (_N66573), + .Z (_N67567), .CIN (\N30_1.co [4] ), .I0 (), .I1 (data_count[5]), @@ -372894,7 +372395,7 @@ module udp_wr_mem .I4_TO_LUT("FALSE")) \N30_1.fsub_6 ( .COUT (\N30_1.co [6] ), - .Z (_N66598), + .Z (_N67609), .CIN (\N30_1.co [5] ), .I0 (), .I1 (data_count[6]), @@ -372914,7 +372415,7 @@ module udp_wr_mem .I4_TO_LUT("FALSE")) \N30_1.fsub_7 ( .COUT (), - .Z (_N66641), + .Z (_N67638), .CIN (\N30_1.co [6] ), .I0 (), .I1 (data_count[7]), @@ -372930,8 +372431,8 @@ module udp_wr_mem .INIT(32'b00000000000000000000000000001000)) N44_vname ( .Z (N44), - .I0 (_N97138), - .I1 (_N97274), + .I0 (_N97909), + .I1 (_N98046), .I2 (index[2]), .I3 (index[3]), .I4 (index[4])); @@ -372941,7 +372442,7 @@ module udp_wr_mem GTP_LUT5 /* N44_11 */ #( .INIT(32'b00000000000000100000000000000000)) N44_11 ( - .Z (_N97138), + .Z (_N97909), .I0 (udp_rx_valid), .I1 (index[5]), .I2 (index[6]), @@ -372961,8 +372462,8 @@ module udp_wr_mem .INIT(32'b00000000000000000000000000001000)) N64_vname ( .Z (N64), - .I0 (_N97138), - .I1 (_N97275), + .I0 (_N97909), + .I1 (_N98047), .I2 (index[2]), .I3 (index[3]), .I4 (index[4])); @@ -372981,8 +372482,8 @@ module udp_wr_mem .INIT(32'b00000000000000000000000000001000)) N84_vname ( .Z (N84), - .I0 (_N97138), - .I1 (_N97276), + .I0 (_N97909), + .I1 (_N98048), .I2 (index[2]), .I3 (index[3]), .I4 (index[4])); @@ -373001,8 +372502,8 @@ module udp_wr_mem .INIT(32'b00000000000000000000000000001000)) N104_vname ( .Z (N104), - .I0 (_N97138), - .I1 (_N97277), + .I0 (_N97909), + .I1 (_N98049), .I2 (index[2]), .I3 (index[3]), .I4 (index[4])); @@ -373021,8 +372522,8 @@ module udp_wr_mem .INIT(32'b00000000000000000000000010000000)) N124_vname ( .Z (N124), - .I0 (_N97138), - .I1 (_N97274), + .I0 (_N97909), + .I1 (_N98046), .I2 (index[2]), .I3 (index[3]), .I4 (index[4])); @@ -373041,8 +372542,8 @@ module udp_wr_mem .INIT(32'b00000000000000000000000010000000)) N144_vname ( .Z (N144), - .I0 (_N97138), - .I1 (_N97275), + .I0 (_N97909), + .I1 (_N98047), .I2 (index[2]), .I3 (index[3]), .I4 (index[4])); @@ -373061,8 +372562,8 @@ module udp_wr_mem .INIT(32'b00000000000000000000000010000000)) N164_vname ( .Z (N164), - .I0 (_N97138), - .I1 (_N97276), + .I0 (_N97909), + .I1 (_N98048), .I2 (index[2]), .I3 (index[3]), .I4 (index[4])); @@ -373081,8 +372582,8 @@ module udp_wr_mem .INIT(32'b00000000000000000000000010000000)) N184_vname ( .Z (N184), - .I0 (_N97138), - .I1 (_N97277), + .I0 (_N97909), + .I1 (_N98049), .I2 (index[2]), .I3 (index[3]), .I4 (index[4])); @@ -373101,8 +372602,8 @@ module udp_wr_mem .INIT(32'b00000000000000000000100000000000)) N204_vname ( .Z (N204), - .I0 (_N97138), - .I1 (_N97274), + .I0 (_N97909), + .I1 (_N98046), .I2 (index[2]), .I3 (index[3]), .I4 (index[4])); @@ -373121,8 +372622,8 @@ module udp_wr_mem .INIT(32'b00000000000000000000100000000000)) N224_vname ( .Z (N224), - .I0 (_N97138), - .I1 (_N97275), + .I0 (_N97909), + .I1 (_N98047), .I2 (index[2]), .I3 (index[3]), .I4 (index[4])); @@ -373141,8 +372642,8 @@ module udp_wr_mem .INIT(32'b00000000000000000000100000000000)) N244_vname ( .Z (N244), - .I0 (_N97138), - .I1 (_N97276), + .I0 (_N97909), + .I1 (_N98048), .I2 (index[2]), .I3 (index[3]), .I4 (index[4])); @@ -373161,8 +372662,8 @@ module udp_wr_mem .INIT(32'b00000000000000000000100000000000)) N264_vname ( .Z (N264), - .I0 (_N97138), - .I1 (_N97277), + .I0 (_N97909), + .I1 (_N98049), .I2 (index[2]), .I3 (index[3]), .I4 (index[4])); @@ -373181,8 +372682,8 @@ module udp_wr_mem .INIT(32'b00000000000000001000000000000000)) N284_vname ( .Z (N284), - .I0 (_N97138), - .I1 (_N97274), + .I0 (_N97909), + .I1 (_N98046), .I2 (index[2]), .I3 (index[3]), .I4 (index[4])); @@ -373201,8 +372702,8 @@ module udp_wr_mem .INIT(32'b00000000000000001000000000000000)) N304_vname ( .Z (N304), - .I0 (_N97138), - .I1 (_N97275), + .I0 (_N97909), + .I1 (_N98047), .I2 (index[2]), .I3 (index[3]), .I4 (index[4])); @@ -373221,8 +372722,8 @@ module udp_wr_mem .INIT(32'b00000000000000001000000000000000)) N324_vname ( .Z (N324), - .I0 (_N97138), - .I1 (_N97276), + .I0 (_N97909), + .I1 (_N98048), .I2 (index[2]), .I3 (index[3]), .I4 (index[4])); @@ -373241,8 +372742,8 @@ module udp_wr_mem .INIT(32'b00000000000000001000000000000000)) N344_vname ( .Z (N344), - .I0 (_N97138), - .I1 (_N97277), + .I0 (_N97909), + .I1 (_N98049), .I2 (index[2]), .I3 (index[3]), .I4 (index[4])); @@ -373261,8 +372762,8 @@ module udp_wr_mem .INIT(32'b00000000000010000000000000000000)) N364_vname ( .Z (N364), - .I0 (_N97138), - .I1 (_N97274), + .I0 (_N97909), + .I1 (_N98046), .I2 (index[2]), .I3 (index[3]), .I4 (index[4])); @@ -373281,8 +372782,8 @@ module udp_wr_mem .INIT(32'b00000000000010000000000000000000)) N384_vname ( .Z (N384), - .I0 (_N97138), - .I1 (_N97275), + .I0 (_N97909), + .I1 (_N98047), .I2 (index[2]), .I3 (index[3]), .I4 (index[4])); @@ -373301,8 +372802,8 @@ module udp_wr_mem .INIT(32'b00000000000010000000000000000000)) N404_vname ( .Z (N404), - .I0 (_N97138), - .I1 (_N97276), + .I0 (_N97909), + .I1 (_N98048), .I2 (index[2]), .I3 (index[3]), .I4 (index[4])); @@ -373321,8 +372822,8 @@ module udp_wr_mem .INIT(32'b00000000000010000000000000000000)) N424_vname ( .Z (N424), - .I0 (_N97138), - .I1 (_N97277), + .I0 (_N97909), + .I1 (_N98049), .I2 (index[2]), .I3 (index[3]), .I4 (index[4])); @@ -373341,8 +372842,8 @@ module udp_wr_mem .INIT(32'b00000000100000000000000000000000)) N444_vname ( .Z (N444), - .I0 (_N97138), - .I1 (_N97274), + .I0 (_N97909), + .I1 (_N98046), .I2 (index[2]), .I3 (index[3]), .I4 (index[4])); @@ -373361,8 +372862,8 @@ module udp_wr_mem .INIT(32'b00000000100000000000000000000000)) N464_vname ( .Z (N464), - .I0 (_N97138), - .I1 (_N97275), + .I0 (_N97909), + .I1 (_N98047), .I2 (index[2]), .I3 (index[3]), .I4 (index[4])); @@ -373381,8 +372882,8 @@ module udp_wr_mem .INIT(32'b00000000100000000000000000000000)) N484_vname ( .Z (N484), - .I0 (_N97138), - .I1 (_N97276), + .I0 (_N97909), + .I1 (_N98048), .I2 (index[2]), .I3 (index[3]), .I4 (index[4])); @@ -373401,8 +372902,8 @@ module udp_wr_mem .INIT(32'b00000000100000000000000000000000)) N504_vname ( .Z (N504), - .I0 (_N97138), - .I1 (_N97277), + .I0 (_N97909), + .I1 (_N98049), .I2 (index[2]), .I3 (index[3]), .I4 (index[4])); @@ -373420,7 +372921,7 @@ module udp_wr_mem GTP_LUT2 /* N524_1 */ #( .INIT(4'b0001)) N524_1 ( - .Z (_N97274), + .Z (_N98046), .I0 (index[0]), .I1 (index[1])); // LUT = ~I0&~I1 ; @@ -373428,7 +372929,7 @@ module udp_wr_mem GTP_LUT2 /* N524_2 */ #( .INIT(4'b0010)) N524_2 ( - .Z (_N97275), + .Z (_N98047), .I0 (index[0]), .I1 (index[1])); // LUT = I0&~I1 ; @@ -373436,7 +372937,7 @@ module udp_wr_mem GTP_LUT2 /* N524_3 */ #( .INIT(4'b0100)) N524_3 ( - .Z (_N97276), + .Z (_N98048), .I0 (index[0]), .I1 (index[1])); // LUT = ~I0&I1 ; @@ -373444,7 +372945,7 @@ module udp_wr_mem GTP_LUT2 /* N524_4 */ #( .INIT(4'b1000)) N524_4 ( - .Z (_N97277), + .Z (_N98049), .I0 (index[0]), .I1 (index[1])); // LUT = I0&I1 ; @@ -373453,8 +372954,8 @@ module udp_wr_mem .INIT(32'b00001000000000000000000000000000)) N524_10 ( .Z (N524), - .I0 (_N97138), - .I1 (_N97274), + .I0 (_N97909), + .I1 (_N98046), .I2 (index[2]), .I3 (index[3]), .I4 (index[4])); @@ -373471,12 +372972,12 @@ module udp_wr_mem GTP_LUT5 /* N538_16 */ #( .INIT(32'b10000000000000000000000000000000)) N538_16 ( - .Z (_N104323), + .Z (_N105162), .I0 (udp_rx_dest_port[3]), .I1 (udp_rx_dest_port[5]), .I2 (udp_rx_dest_port[8]), .I3 (udp_rx_dest_port[9]), - .I4 (_N97297)); + .I4 (_N98118)); // LUT = I0&I1&I2&I3&I4 ; GTP_LUT5 /* N538_17 */ #( @@ -373487,13 +372988,13 @@ module udp_wr_mem .I1 (udp_rx_dest_port[1]), .I2 (udp_rx_dest_port[4]), .I3 (udp_rx_dest_port[10]), - .I4 (_N104323)); + .I4 (_N105162)); // LUT = I0&~I1&~I2&~I3&I4 ; GTP_LUT5 /* N549_21 */ #( .INIT(32'b00000000000000000000000000000001)) N549_21 ( - .Z (_N104290), + .Z (_N105129), .I0 (pkt_data_cnt[1]), .I1 (pkt_data_cnt[2]), .I2 (pkt_data_cnt[3]), @@ -373504,7 +373005,7 @@ module udp_wr_mem GTP_LUT5 /* N549_25 */ #( .INIT(32'b00000000000000000000000000000001)) N549_25 ( - .Z (_N104294), + .Z (_N105133), .I0 (pkt_data_cnt[6]), .I1 (pkt_data_cnt[7]), .I2 (pkt_data_cnt[8]), @@ -373515,7 +373016,7 @@ module udp_wr_mem GTP_LUT5 /* N549_29 */ #( .INIT(32'b00000000000000000000000000000001)) N549_29 ( - .Z (_N104298), + .Z (_N105137), .I0 (pkt_data_cnt[11]), .I1 (pkt_data_cnt[12]), .I2 (pkt_data_cnt[13]), @@ -373528,16 +373029,16 @@ module udp_wr_mem N549_33 ( .Z (N790[3]), .I0 (udp_rx_valid), - .I1 (_N104290), - .I2 (_N104294), - .I3 (_N104298), + .I1 (_N105129), + .I2 (_N105133), + .I3 (_N105137), .I4 (pkt_data_cnt[0])); // LUT = I0&I1&I2&I3&I4 ; GTP_LUT4 /* N695_6 */ #( .INIT(16'b0000000000000001)) N695_6 ( - .Z (_N104284), + .Z (_N105123), .I0 (data_count[1]), .I1 (data_count[2]), .I2 (data_count[3]), @@ -373548,7 +373049,7 @@ module udp_wr_mem .INIT(32'b00000000000000000000000000001000)) N695_8 ( .Z (N790[2]), - .I0 (_N104284), + .I0 (_N105123), .I1 (data_count[0]), .I2 (data_count[5]), .I3 (data_count[6]), @@ -373597,6 +373098,17 @@ module udp_wr_mem // LUT = (I0&I1)|(I0&I2) ; // ../../sources/designs/others/udp_wr_mem.v:64 + GTP_LUT4 /* \N731_1[2] */ #( + .INIT(16'b1110010011001100)) + \N731_1[2] ( + .Z (N731[2]), + .I0 (udp_rx_valid), + .I1 (udp_rx_data[2]), + .I2 (N784[2]), + .I3 (state_reg[2])); + // LUT = (I1&~I3)|(~I0&I1)|(I0&I2&I3) ; + // ../../sources/designs/others/udp_wr_mem.v:64 + GTP_DFF_RE /* \data_count[0] */ #( .GRS_EN("TRUE"), .INIT(1'b0)) @@ -373604,7 +373116,7 @@ module udp_wr_mem .Q (data_count[0]), .CE (N730), .CLK (clk), - .D (_N66380), + .D (_N67380), .R (sync_vg_100m)); // ../../sources/designs/others/udp_wr_mem.v:64 @@ -373615,7 +373127,7 @@ module udp_wr_mem .Q (data_count[1]), .CE (N730), .CLK (clk), - .D (_N66433), + .D (_N67428), .R (sync_vg_100m)); // ../../sources/designs/others/udp_wr_mem.v:64 @@ -373626,7 +373138,7 @@ module udp_wr_mem .Q (data_count[2]), .CE (N730), .CLK (clk), - .D (_N66473), + .D (N731[2]), .R (sync_vg_100m)); // ../../sources/designs/others/udp_wr_mem.v:64 @@ -373637,7 +373149,7 @@ module udp_wr_mem .Q (data_count[3]), .CE (N730), .CLK (clk), - .D (_N66494), + .D (_N67499), .R (sync_vg_100m)); // ../../sources/designs/others/udp_wr_mem.v:64 @@ -373648,7 +373160,7 @@ module udp_wr_mem .Q (data_count[4]), .CE (N730), .CLK (clk), - .D (_N66527), + .D (_N67541), .R (sync_vg_100m)); // ../../sources/designs/others/udp_wr_mem.v:64 @@ -373659,7 +373171,7 @@ module udp_wr_mem .Q (data_count[5]), .CE (N730), .CLK (clk), - .D (_N66573), + .D (_N67567), .R (sync_vg_100m)); // ../../sources/designs/others/udp_wr_mem.v:64 @@ -373670,14 +373182,23 @@ module udp_wr_mem .Q (data_count[6]), .CE (N730), .CLK (clk), - .D (_N66598), + .D (_N67609), .R (sync_vg_100m)); // ../../sources/designs/others/udp_wr_mem.v:64 - GTP_LUT3 /* \data_count[7:0]_3952 */ #( + GTP_LUT3 /* \data_count[7:0]_1 */ #( + .INIT(8'b11001010)) + \data_count[7:0]_1 ( + .Z (_N67428), + .I0 (udp_rx_data[1]), + .I1 (N784[1]), + .I2 (state_reg[2])); + // LUT = (I0&~I2)|(I1&I2) ; + + GTP_LUT3 /* \data_count[7:0]_3988 */ #( .INIT(8'b00111010)) - \data_count[7:0]_3952 ( - .Z (_N66380), + \data_count[7:0]_3988 ( + .Z (_N67380), .I0 (udp_rx_data[0]), .I1 (data_count[0]), .I2 (state_reg[2])); @@ -373690,7 +373211,7 @@ module udp_wr_mem .Q (data_count[7]), .CE (N730), .CLK (clk), - .D (_N66641), + .D (_N67638), .R (sync_vg_100m)); // ../../sources/designs/others/udp_wr_mem.v:64 @@ -373976,7 +373497,7 @@ module udp_wr_mem .Q (index[0]), .CE (N727), .CLK (clk), - .D (_N40422), + .D (_N38381), .R (sync_vg_100m)); // ../../sources/designs/others/udp_wr_mem.v:51 @@ -373987,7 +373508,7 @@ module udp_wr_mem .Q (index[1]), .CE (N727), .CLK (clk), - .D (_N40458), + .D (_N38424), .R (sync_vg_100m)); // ../../sources/designs/others/udp_wr_mem.v:51 @@ -373998,7 +373519,7 @@ module udp_wr_mem .Q (index[2]), .CE (N727), .CLK (clk), - .D (_N40496), + .D (_N38463), .R (sync_vg_100m)); // ../../sources/designs/others/udp_wr_mem.v:51 @@ -374009,7 +373530,7 @@ module udp_wr_mem .Q (index[3]), .CE (N727), .CLK (clk), - .D (_N40532), + .D (_N38489), .R (sync_vg_100m)); // ../../sources/designs/others/udp_wr_mem.v:51 @@ -374020,7 +373541,7 @@ module udp_wr_mem .Q (index[4]), .CE (N727), .CLK (clk), - .D (_N40585), + .D (_N38530), .R (sync_vg_100m)); // ../../sources/designs/others/udp_wr_mem.v:51 @@ -374031,7 +373552,7 @@ module udp_wr_mem .Q (index[5]), .CE (N727), .CLK (clk), - .D (_N40603), + .D (_N38570), .R (sync_vg_100m)); // ../../sources/designs/others/udp_wr_mem.v:51 @@ -374042,14 +373563,14 @@ module udp_wr_mem .Q (index[6]), .CE (N727), .CLK (clk), - .D (_N40636), + .D (_N38599), .R (sync_vg_100m)); // ../../sources/designs/others/udp_wr_mem.v:51 - GTP_LUT3 /* \index[7:0]_1315 */ #( + GTP_LUT3 /* \index[7:0]_958 */ #( .INIT(8'b00111010)) - \index[7:0]_1315 ( - .Z (_N40422), + \index[7:0]_958 ( + .Z (_N38381), .I0 (udp_rx_data[0]), .I1 (index[0]), .I2 (state_reg[2])); @@ -374062,7 +373583,7 @@ module udp_wr_mem .Q (index[7]), .CE (N727), .CLK (clk), - .D (_N40693), + .D (_N38638), .R (sync_vg_100m)); // ../../sources/designs/others/udp_wr_mem.v:51 @@ -375695,9 +375216,9 @@ module udp_wr_mem .I3 (state_reg[1])); // LUT = (~I0&I3)|(I1&I2) ; - GTP_LUT5M /* \state_fsm[2:0]_32_3 */ #( + GTP_LUT5M /* \state_fsm[2:0]_31_3 */ #( .INIT(32'b01010100010001001111101010101010)) - \state_fsm[2:0]_32_3 ( + \state_fsm[2:0]_31_3 ( .Z (_N24), .I0 (N790[3]), .I1 (state_reg[1]), @@ -375849,34 +375370,24 @@ module multimedia_video_processor wire N119; wire [12:0] \N123_0.co ; wire N139_0; - wire N162; - wire N241_0; - wire N285; - wire N298; - wire [15:0] N314; - wire [12:0] N318; - wire [12:0] N322; - wire [12:0] N332; - wire [12:0] N334; - wire [29:0] N336; + wire N163; + wire N242_0; + wire N286; + wire N299; + wire [15:0] N315; + wire [12:0] N319; + wire [12:0] N323; + wire [12:0] N333; + wire [12:0] N335; + wire [29:0] N337; wire _N8; wire _N9; - wire _N2195; - wire _N2203; - wire _N2209; - wire _N2277; - wire _N17115; - wire _N17116; - wire _N17117; - wire _N17118; - wire _N17119; - wire _N17120; - wire _N17121; - wire _N17122; - wire _N17123; - wire _N17124; - wire _N17125; - wire _N17126; + wire _N2197; + wire _N2205; + wire _N2211; + wire _N2279; + wire _N17127; + wire _N17128; wire _N17129; wire _N17130; wire _N17131; @@ -375887,8 +375398,6 @@ module multimedia_video_processor wire _N17136; wire _N17137; wire _N17138; - wire _N17139; - wire _N17140; wire _N17141; wire _N17142; wire _N17143; @@ -375905,39 +375414,48 @@ module multimedia_video_processor wire _N17154; wire _N17155; wire _N17156; - wire _N18115; - wire _N81412_3; - wire _N81412_5; - wire _N81413_3; - wire _N81413_5; - wire _N81414_3; - wire _N81414_5; - wire _N81415_3; - wire _N81415_5; - wire _N97085; - wire _N97297; - wire _N97340; - wire _N103530; - wire _N103547; - wire _N103551; - wire _N103709; - wire _N103711; - wire _N103720; - wire _N103722; - wire _N103731; - wire _N103733; - wire _N103742; - wire _N103743; - wire _N103744; - wire _N103920; - wire _N103957; - wire _N103958; - wire _N103959; - wire _N105268; - wire _N105817; - wire _N106355; - wire _N106490; - wire _N106518; + wire _N17157; + wire _N17158; + wire _N17159; + wire _N17160; + wire _N17161; + wire _N17162; + wire _N17163; + wire _N17164; + wire _N17165; + wire _N17166; + wire _N17167; + wire _N17168; + wire _N82185_3; + wire _N82185_5; + wire _N82186_3; + wire _N82186_5; + wire _N82187_3; + wire _N82187_5; + wire _N82188_3; + wire _N82188_5; + wire _N98107; + wire _N98118; + wire _N104342; + wire _N104359; + wire _N104363; + wire _N104528; + wire _N104530; + wire _N104539; + wire _N104541; + wire _N104550; + wire _N104552; + wire _N104561; + wire _N104562; + wire _N104563; + wire _N104744; + wire _N104781; + wire _N104782; + wire _N104783; + wire _N106081; + wire _N106639; + wire _N107308; + wire _N107336; wire axi_rst; wire [15:0] camera_data; wire camera_valid; @@ -375948,6 +375466,7 @@ module multimedia_video_processor wire clk_25m; wire [31:0] clk_cnt; wire \clk_cnt[0]_inv ; + wire ddr_clk; wire ddr_rst; wire de_osd; wire gmii_clk; @@ -376013,14 +375532,11 @@ module multimedia_video_processor wire nt_vs_out; wire [2:0] param_filiter1_mode; wire [2:0] param_filiter2_mode; + wire \param_manager_inst/param_filiter1_mode/N140 ; wire \param_manager_inst/param_filiter1_mode/changed_down ; - wire \param_manager_inst/param_filiter1_mode/changed_up ; + wire \param_manager_inst/param_filiter1_mode/pluse ; wire \param_manager_inst/param_filiter1_mode/pressed_down ; - wire \param_manager_inst/param_filiter1_mode/pressed_up ; - wire \param_manager_inst/param_modify_H/pluse ; - wire \param_manager_inst/param_modify_V/N140 ; - wire \param_manager_inst/param_rotate_A/N142 ; - wire \param_manager_inst/param_zoom/N142 ; + wire \param_manager_inst/param_filiter2_mode/N140 ; wire [13:0] \param_manager_inst/selected ; wire [8:0] param_modify_H; wire [8:0] param_modify_S; @@ -376064,9 +375580,6 @@ module multimedia_video_processor wire sync_vg_100m; wire [15:0] temp_d; wire temp_v; - wire \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N137_rnmt ; - wire [7:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt ; - wire [8:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg ; wire \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N538_rnmt ; wire [9:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt ; wire [7:0] \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin_div2 ; @@ -376127,32 +375640,18 @@ module multimedia_video_processor wire zoom_rst; wire zoom_vs_out0; wire zoom_vs_out1; - wire \param_manager_inst_selected[0]_floating ; - wire \param_manager_inst_selected[1]_floating ; + wire \param_manager_inst_selected[2]_floating ; wire \param_manager_inst_selected[3]_floating ; wire \param_manager_inst_selected[4]_floating ; wire \param_manager_inst_selected[5]_floating ; wire \param_manager_inst_selected[6]_floating ; wire \param_manager_inst_selected[7]_floating ; + wire \param_manager_inst_selected[8]_floating ; wire \param_manager_inst_selected[9]_floating ; wire \param_manager_inst_selected[10]_floating ; wire \param_manager_inst_selected[11]_floating ; wire \param_manager_inst_selected[12]_floating ; - wire \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[0]_floating ; - wire \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[1]_floating ; - wire \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[2]_floating ; - wire \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[4]_floating ; - wire \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[5]_floating ; - wire \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[6]_floating ; - wire \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[7]_floating ; - wire \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[0]_floating ; - wire \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[1]_floating ; - wire \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[2]_floating ; - wire \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[3]_floating ; - wire \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]_floating ; - wire \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[5]_floating ; - wire \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[6]_floating ; - wire \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[8]_floating ; + wire \param_manager_inst_selected[13]_floating ; wire \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]_floating ; wire \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[1]_floating ; wire \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[2]_floating ; @@ -376447,7 +375946,7 @@ module multimedia_video_processor .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N15_0_1 ( - .COUT (_N17115), + .COUT (_N17127), .Z (N15[1]), .CIN (), .I0 (rstn_1ms[0]), @@ -376467,9 +375966,9 @@ module multimedia_video_processor .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N15_0_2 ( - .COUT (_N17116), + .COUT (_N17128), .Z (N15[2]), - .CIN (_N17115), + .CIN (_N17127), .I0 (rstn_1ms[0]), .I1 (rstn_1ms[1]), .I2 (rstn_1ms[2]), @@ -376487,9 +375986,9 @@ module multimedia_video_processor .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N15_0_3 ( - .COUT (_N17117), + .COUT (_N17129), .Z (N15[3]), - .CIN (_N17116), + .CIN (_N17128), .I0 (), .I1 (rstn_1ms[3]), .I2 (), @@ -376507,9 +376006,9 @@ module multimedia_video_processor .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N15_0_4 ( - .COUT (_N17118), + .COUT (_N17130), .Z (N15[4]), - .CIN (_N17117), + .CIN (_N17129), .I0 (), .I1 (rstn_1ms[4]), .I2 (), @@ -376527,9 +376026,9 @@ module multimedia_video_processor .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N15_0_5 ( - .COUT (_N17119), + .COUT (_N17131), .Z (N15[5]), - .CIN (_N17118), + .CIN (_N17130), .I0 (), .I1 (rstn_1ms[5]), .I2 (), @@ -376547,9 +376046,9 @@ module multimedia_video_processor .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N15_0_6 ( - .COUT (_N17120), + .COUT (_N17132), .Z (N15[6]), - .CIN (_N17119), + .CIN (_N17131), .I0 (), .I1 (rstn_1ms[6]), .I2 (), @@ -376567,9 +376066,9 @@ module multimedia_video_processor .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N15_0_7 ( - .COUT (_N17121), + .COUT (_N17133), .Z (N15[7]), - .CIN (_N17120), + .CIN (_N17132), .I0 (), .I1 (rstn_1ms[7]), .I2 (), @@ -376587,9 +376086,9 @@ module multimedia_video_processor .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N15_0_8 ( - .COUT (_N17122), + .COUT (_N17134), .Z (N15[8]), - .CIN (_N17121), + .CIN (_N17133), .I0 (), .I1 (rstn_1ms[8]), .I2 (), @@ -376607,9 +376106,9 @@ module multimedia_video_processor .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N15_0_9 ( - .COUT (_N17123), + .COUT (_N17135), .Z (N15[9]), - .CIN (_N17122), + .CIN (_N17134), .I0 (), .I1 (rstn_1ms[9]), .I2 (), @@ -376627,9 +376126,9 @@ module multimedia_video_processor .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N15_0_10 ( - .COUT (_N17124), + .COUT (_N17136), .Z (N15[10]), - .CIN (_N17123), + .CIN (_N17135), .I0 (), .I1 (rstn_1ms[10]), .I2 (), @@ -376647,9 +376146,9 @@ module multimedia_video_processor .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N15_0_11 ( - .COUT (_N17125), + .COUT (_N17137), .Z (N15[11]), - .CIN (_N17124), + .CIN (_N17136), .I0 (), .I1 (rstn_1ms[11]), .I2 (), @@ -376667,9 +376166,9 @@ module multimedia_video_processor .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N15_0_12 ( - .COUT (_N17126), + .COUT (_N17138), .Z (N15[12]), - .CIN (_N17125), + .CIN (_N17137), .I0 (), .I1 (rstn_1ms[12]), .I2 (), @@ -376689,7 +376188,7 @@ module multimedia_video_processor N15_0_13 ( .COUT (), .Z (N15[13]), - .CIN (_N17126), + .CIN (_N17138), .I0 (), .I1 (rstn_1ms[13]), .I2 (), @@ -376708,7 +376207,7 @@ module multimedia_video_processor GTP_LUT5 /* N24_mux6_3 */ #( .INIT(32'b00000000000000011111111111111111)) N24_mux6_3 ( - .Z (_N103547), + .Z (_N104359), .I0 (clk_cnt[7]), .I1 (clk_cnt[8]), .I2 (clk_cnt[9]), @@ -376719,7 +376218,7 @@ module multimedia_video_processor GTP_LUT4 /* N24_mux11_4 */ #( .INIT(16'b0111111111111111)) N24_mux11_4 ( - .Z (_N103551), + .Z (_N104363), .I0 (clk_cnt[15]), .I1 (clk_cnt[16]), .I2 (clk_cnt[17]), @@ -376729,33 +376228,33 @@ module multimedia_video_processor GTP_LUT5 /* N24_mux11_5 */ #( .INIT(32'b11111111111111110000111100000111)) N24_mux11_5 ( - .Z (_N2195), + .Z (_N2197), .I0 (clk_cnt[11]), .I1 (clk_cnt[12]), .I2 (clk_cnt[14]), - .I3 (_N103547), - .I4 (_N103551)); + .I3 (_N104359), + .I4 (_N104363)); // LUT = (I4)|(~I1&~I2)|(~I0&~I2)|(~I2&I3) ; GTP_LUT5 /* N24_mux15_3 */ #( .INIT(32'b00011111111111110000111111111111)) N24_mux15_3 ( - .Z (_N2203), + .Z (_N2205), .I0 (clk_cnt[19]), .I1 (clk_cnt[20]), .I2 (clk_cnt[21]), .I3 (clk_cnt[22]), - .I4 (_N2195)); + .I4 (_N2197)); // LUT = (~I3)|(~I2)|(~I0&~I1&I4) ; GTP_LUT4 /* N24_mux18_3 */ #( .INIT(16'b0111111100111111)) N24_mux18_3 ( - .Z (_N2209), + .Z (_N2211), .I0 (clk_cnt[23]), .I1 (clk_cnt[24]), .I2 (clk_cnt[25]), - .I3 (_N2203)); + .I3 (_N2205)); // LUT = (~I2)|(~I1)|(~I0&I3) ; GTP_LUT5 /* N24_mux22 */ #( @@ -376766,7 +376265,7 @@ module multimedia_video_processor .I1 (clk_cnt[27]), .I2 (clk_cnt[28]), .I3 (clk_cnt[29]), - .I4 (_N2209)); + .I4 (_N2211)); // LUT = (~I3)|(~I0&~I1&~I2&I4) ; GTP_LUT1 /* N25 */ #( @@ -376784,8 +376283,8 @@ module multimedia_video_processor .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_0_1 ( - .COUT (_N17129), - .Z (N336[1]), + .COUT (_N17141), + .Z (N337[1]), .CIN (), .I0 (clk_cnt[0]), .I1 (clk_cnt[1]), @@ -376804,9 +376303,9 @@ module multimedia_video_processor .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_0_2 ( - .COUT (_N17130), - .Z (N336[2]), - .CIN (_N17129), + .COUT (_N17142), + .Z (N337[2]), + .CIN (_N17141), .I0 (clk_cnt[0]), .I1 (clk_cnt[1]), .I2 (clk_cnt[2]), @@ -376824,9 +376323,9 @@ module multimedia_video_processor .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_0_3 ( - .COUT (_N17131), - .Z (N336[3]), - .CIN (_N17130), + .COUT (_N17143), + .Z (N337[3]), + .CIN (_N17142), .I0 (), .I1 (clk_cnt[3]), .I2 (), @@ -376844,9 +376343,9 @@ module multimedia_video_processor .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_0_4 ( - .COUT (_N17132), - .Z (N336[4]), - .CIN (_N17131), + .COUT (_N17144), + .Z (N337[4]), + .CIN (_N17143), .I0 (), .I1 (clk_cnt[4]), .I2 (), @@ -376864,9 +376363,9 @@ module multimedia_video_processor .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_0_5 ( - .COUT (_N17133), - .Z (N336[5]), - .CIN (_N17132), + .COUT (_N17145), + .Z (N337[5]), + .CIN (_N17144), .I0 (), .I1 (clk_cnt[5]), .I2 (), @@ -376884,9 +376383,9 @@ module multimedia_video_processor .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_0_6 ( - .COUT (_N17134), - .Z (N336[6]), - .CIN (_N17133), + .COUT (_N17146), + .Z (N337[6]), + .CIN (_N17145), .I0 (), .I1 (clk_cnt[6]), .I2 (), @@ -376904,9 +376403,9 @@ module multimedia_video_processor .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_0_7 ( - .COUT (_N17135), - .Z (N336[7]), - .CIN (_N17134), + .COUT (_N17147), + .Z (N337[7]), + .CIN (_N17146), .I0 (), .I1 (clk_cnt[7]), .I2 (), @@ -376924,9 +376423,9 @@ module multimedia_video_processor .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_0_8 ( - .COUT (_N17136), - .Z (N336[8]), - .CIN (_N17135), + .COUT (_N17148), + .Z (N337[8]), + .CIN (_N17147), .I0 (), .I1 (clk_cnt[8]), .I2 (), @@ -376944,9 +376443,9 @@ module multimedia_video_processor .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_0_9 ( - .COUT (_N17137), - .Z (N336[9]), - .CIN (_N17136), + .COUT (_N17149), + .Z (N337[9]), + .CIN (_N17148), .I0 (), .I1 (clk_cnt[9]), .I2 (), @@ -376964,9 +376463,9 @@ module multimedia_video_processor .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_0_10 ( - .COUT (_N17138), - .Z (N336[10]), - .CIN (_N17137), + .COUT (_N17150), + .Z (N337[10]), + .CIN (_N17149), .I0 (), .I1 (clk_cnt[10]), .I2 (), @@ -376984,9 +376483,9 @@ module multimedia_video_processor .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_0_11 ( - .COUT (_N17139), - .Z (N336[11]), - .CIN (_N17138), + .COUT (_N17151), + .Z (N337[11]), + .CIN (_N17150), .I0 (), .I1 (clk_cnt[11]), .I2 (), @@ -377004,9 +376503,9 @@ module multimedia_video_processor .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_0_12 ( - .COUT (_N17140), - .Z (N336[12]), - .CIN (_N17139), + .COUT (_N17152), + .Z (N337[12]), + .CIN (_N17151), .I0 (), .I1 (clk_cnt[12]), .I2 (), @@ -377024,9 +376523,9 @@ module multimedia_video_processor .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_0_13 ( - .COUT (_N17141), - .Z (N336[13]), - .CIN (_N17140), + .COUT (_N17153), + .Z (N337[13]), + .CIN (_N17152), .I0 (), .I1 (clk_cnt[13]), .I2 (), @@ -377044,9 +376543,9 @@ module multimedia_video_processor .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_0_14 ( - .COUT (_N17142), - .Z (N336[14]), - .CIN (_N17141), + .COUT (_N17154), + .Z (N337[14]), + .CIN (_N17153), .I0 (), .I1 (clk_cnt[14]), .I2 (), @@ -377064,9 +376563,9 @@ module multimedia_video_processor .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_0_15 ( - .COUT (_N17143), - .Z (N336[15]), - .CIN (_N17142), + .COUT (_N17155), + .Z (N337[15]), + .CIN (_N17154), .I0 (), .I1 (clk_cnt[15]), .I2 (), @@ -377084,9 +376583,9 @@ module multimedia_video_processor .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_0_16 ( - .COUT (_N17144), - .Z (N336[16]), - .CIN (_N17143), + .COUT (_N17156), + .Z (N337[16]), + .CIN (_N17155), .I0 (), .I1 (clk_cnt[16]), .I2 (), @@ -377104,9 +376603,9 @@ module multimedia_video_processor .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_0_17 ( - .COUT (_N17145), - .Z (N336[17]), - .CIN (_N17144), + .COUT (_N17157), + .Z (N337[17]), + .CIN (_N17156), .I0 (), .I1 (clk_cnt[17]), .I2 (), @@ -377124,9 +376623,9 @@ module multimedia_video_processor .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_0_18 ( - .COUT (_N17146), - .Z (N336[18]), - .CIN (_N17145), + .COUT (_N17158), + .Z (N337[18]), + .CIN (_N17157), .I0 (), .I1 (clk_cnt[18]), .I2 (), @@ -377144,9 +376643,9 @@ module multimedia_video_processor .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_0_19 ( - .COUT (_N17147), - .Z (N336[19]), - .CIN (_N17146), + .COUT (_N17159), + .Z (N337[19]), + .CIN (_N17158), .I0 (), .I1 (clk_cnt[19]), .I2 (), @@ -377164,9 +376663,9 @@ module multimedia_video_processor .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_0_20 ( - .COUT (_N17148), - .Z (N336[20]), - .CIN (_N17147), + .COUT (_N17160), + .Z (N337[20]), + .CIN (_N17159), .I0 (), .I1 (clk_cnt[20]), .I2 (), @@ -377184,9 +376683,9 @@ module multimedia_video_processor .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_0_21 ( - .COUT (_N17149), - .Z (N336[21]), - .CIN (_N17148), + .COUT (_N17161), + .Z (N337[21]), + .CIN (_N17160), .I0 (), .I1 (clk_cnt[21]), .I2 (), @@ -377204,9 +376703,9 @@ module multimedia_video_processor .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_0_22 ( - .COUT (_N17150), - .Z (N336[22]), - .CIN (_N17149), + .COUT (_N17162), + .Z (N337[22]), + .CIN (_N17161), .I0 (), .I1 (clk_cnt[22]), .I2 (), @@ -377224,9 +376723,9 @@ module multimedia_video_processor .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_0_23 ( - .COUT (_N17151), - .Z (N336[23]), - .CIN (_N17150), + .COUT (_N17163), + .Z (N337[23]), + .CIN (_N17162), .I0 (), .I1 (clk_cnt[23]), .I2 (), @@ -377244,9 +376743,9 @@ module multimedia_video_processor .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_0_24 ( - .COUT (_N17152), - .Z (N336[24]), - .CIN (_N17151), + .COUT (_N17164), + .Z (N337[24]), + .CIN (_N17163), .I0 (), .I1 (clk_cnt[24]), .I2 (), @@ -377264,9 +376763,9 @@ module multimedia_video_processor .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_0_25 ( - .COUT (_N17153), - .Z (N336[25]), - .CIN (_N17152), + .COUT (_N17165), + .Z (N337[25]), + .CIN (_N17164), .I0 (), .I1 (clk_cnt[25]), .I2 (), @@ -377284,9 +376783,9 @@ module multimedia_video_processor .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_0_26 ( - .COUT (_N17154), - .Z (N336[26]), - .CIN (_N17153), + .COUT (_N17166), + .Z (N337[26]), + .CIN (_N17165), .I0 (), .I1 (clk_cnt[26]), .I2 (), @@ -377304,9 +376803,9 @@ module multimedia_video_processor .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_0_27 ( - .COUT (_N17155), - .Z (N336[27]), - .CIN (_N17154), + .COUT (_N17167), + .Z (N337[27]), + .CIN (_N17166), .I0 (), .I1 (clk_cnt[27]), .I2 (), @@ -377324,9 +376823,9 @@ module multimedia_video_processor .I4_TO_CARRY("TRUE"), .I4_TO_LUT("FALSE")) N27_0_28 ( - .COUT (_N17156), - .Z (N336[28]), - .CIN (_N17155), + .COUT (_N17168), + .Z (N337[28]), + .CIN (_N17167), .I0 (), .I1 (clk_cnt[28]), .I2 (), @@ -377345,8 +376844,8 @@ module multimedia_video_processor .I4_TO_LUT("FALSE")) N27_0_29 ( .COUT (), - .Z (N336[29]), - .CIN (_N17156), + .Z (N337[29]), + .CIN (_N17168), .I0 (), .I1 (clk_cnt[29]), .I2 (), @@ -377365,7 +376864,7 @@ module multimedia_video_processor GTP_LUT4 /* N104_mux11_9 */ #( .INIT(16'b1111111111111110)) N104_mux11_9 ( - .Z (_N103720), + .Z (_N104539), .I0 (vs_pos_delay_cnt[4]), .I1 (vs_pos_delay_cnt[5]), .I2 (vs_pos_delay_cnt[6]), @@ -377375,12 +376874,12 @@ module multimedia_video_processor GTP_LUT5 /* N104_mux11_11 */ #( .INIT(32'b11111111111111111111111111111110)) N104_mux11_11 ( - .Z (_N103722), + .Z (_N104541), .I0 (vs_pos_delay_cnt[0]), .I1 (vs_pos_delay_cnt[1]), .I2 (vs_pos_delay_cnt[2]), .I3 (vs_pos_delay_cnt[3]), - .I4 (_N103720)); + .I4 (_N104539)); // LUT = (I0)|(I1)|(I2)|(I3)|(I4) ; GTP_LUT5 /* N104_mux11_12 */ #( @@ -377391,7 +376890,7 @@ module multimedia_video_processor .I1 (vs_pos_delay_cnt[9]), .I2 (vs_pos_delay_cnt[10]), .I3 (vs_pos_delay_cnt[11]), - .I4 (_N103722)); + .I4 (_N104541)); // LUT = (I0)|(I1)|(I2)|(I3)|(I4) ; GTP_LUT5CARRY /* \N108_0.fsub_1 */ #( @@ -377402,7 +376901,7 @@ module multimedia_video_processor .I4_TO_LUT("FALSE")) \N108_0.fsub_1 ( .COUT (\N108_0.co [1] ), - .Z (N334[1]), + .Z (N335[1]), .CIN (), .I0 (vs_pos_delay_cnt[0]), .I1 (vs_pos_delay_cnt[1]), @@ -377422,7 +376921,7 @@ module multimedia_video_processor .I4_TO_LUT("FALSE")) \N108_0.fsub_2 ( .COUT (\N108_0.co [2] ), - .Z (N334[2]), + .Z (N335[2]), .CIN (\N108_0.co [1] ), .I0 (vs_pos_delay_cnt[0]), .I1 (vs_pos_delay_cnt[1]), @@ -377442,7 +376941,7 @@ module multimedia_video_processor .I4_TO_LUT("FALSE")) \N108_0.fsub_3 ( .COUT (\N108_0.co [3] ), - .Z (N334[3]), + .Z (N335[3]), .CIN (\N108_0.co [2] ), .I0 (), .I1 (vs_pos_delay_cnt[3]), @@ -377462,7 +376961,7 @@ module multimedia_video_processor .I4_TO_LUT("FALSE")) \N108_0.fsub_4 ( .COUT (\N108_0.co [4] ), - .Z (N334[4]), + .Z (N335[4]), .CIN (\N108_0.co [3] ), .I0 (), .I1 (vs_pos_delay_cnt[4]), @@ -377482,7 +376981,7 @@ module multimedia_video_processor .I4_TO_LUT("FALSE")) \N108_0.fsub_5 ( .COUT (\N108_0.co [5] ), - .Z (N334[5]), + .Z (N335[5]), .CIN (\N108_0.co [4] ), .I0 (), .I1 (vs_pos_delay_cnt[5]), @@ -377502,7 +377001,7 @@ module multimedia_video_processor .I4_TO_LUT("FALSE")) \N108_0.fsub_6 ( .COUT (\N108_0.co [6] ), - .Z (N334[6]), + .Z (N335[6]), .CIN (\N108_0.co [5] ), .I0 (), .I1 (vs_pos_delay_cnt[6]), @@ -377522,7 +377021,7 @@ module multimedia_video_processor .I4_TO_LUT("FALSE")) \N108_0.fsub_7 ( .COUT (\N108_0.co [7] ), - .Z (N334[7]), + .Z (N335[7]), .CIN (\N108_0.co [6] ), .I0 (), .I1 (vs_pos_delay_cnt[7]), @@ -377542,7 +377041,7 @@ module multimedia_video_processor .I4_TO_LUT("FALSE")) \N108_0.fsub_8 ( .COUT (\N108_0.co [8] ), - .Z (N334[8]), + .Z (N335[8]), .CIN (\N108_0.co [7] ), .I0 (), .I1 (vs_pos_delay_cnt[8]), @@ -377562,7 +377061,7 @@ module multimedia_video_processor .I4_TO_LUT("FALSE")) \N108_0.fsub_9 ( .COUT (\N108_0.co [9] ), - .Z (N334[9]), + .Z (N335[9]), .CIN (\N108_0.co [8] ), .I0 (), .I1 (vs_pos_delay_cnt[9]), @@ -377582,7 +377081,7 @@ module multimedia_video_processor .I4_TO_LUT("FALSE")) \N108_0.fsub_10 ( .COUT (\N108_0.co [10] ), - .Z (N334[10]), + .Z (N335[10]), .CIN (\N108_0.co [9] ), .I0 (), .I1 (vs_pos_delay_cnt[10]), @@ -377602,7 +377101,7 @@ module multimedia_video_processor .I4_TO_LUT("FALSE")) \N108_0.fsub_11 ( .COUT (), - .Z (N334[11]), + .Z (N335[11]), .CIN (\N108_0.co [10] ), .I0 (), .I1 (vs_pos_delay_cnt[11]), @@ -377617,7 +377116,7 @@ module multimedia_video_processor GTP_LUT4 /* N119_mux11_9 */ #( .INIT(16'b1111111111111110)) N119_mux11_9 ( - .Z (_N103709), + .Z (_N104528), .I0 (vs_down_delay_cnt[4]), .I1 (vs_down_delay_cnt[5]), .I2 (vs_down_delay_cnt[6]), @@ -377627,12 +377126,12 @@ module multimedia_video_processor GTP_LUT5 /* N119_mux11_11 */ #( .INIT(32'b11111111111111111111111111111110)) N119_mux11_11 ( - .Z (_N103711), + .Z (_N104530), .I0 (vs_down_delay_cnt[0]), .I1 (vs_down_delay_cnt[1]), .I2 (vs_down_delay_cnt[2]), .I3 (vs_down_delay_cnt[3]), - .I4 (_N103709)); + .I4 (_N104528)); // LUT = (I0)|(I1)|(I2)|(I3)|(I4) ; GTP_LUT5 /* N119_mux11_12 */ #( @@ -377643,7 +377142,7 @@ module multimedia_video_processor .I1 (vs_down_delay_cnt[9]), .I2 (vs_down_delay_cnt[10]), .I3 (vs_down_delay_cnt[11]), - .I4 (_N103711)); + .I4 (_N104530)); // LUT = (I0)|(I1)|(I2)|(I3)|(I4) ; GTP_LUT5CARRY /* \N123_0.fsub_1 */ #( @@ -377654,7 +377153,7 @@ module multimedia_video_processor .I4_TO_LUT("FALSE")) \N123_0.fsub_1 ( .COUT (\N123_0.co [1] ), - .Z (N332[1]), + .Z (N333[1]), .CIN (), .I0 (vs_down_delay_cnt[0]), .I1 (vs_down_delay_cnt[1]), @@ -377674,7 +377173,7 @@ module multimedia_video_processor .I4_TO_LUT("FALSE")) \N123_0.fsub_2 ( .COUT (\N123_0.co [2] ), - .Z (N332[2]), + .Z (N333[2]), .CIN (\N123_0.co [1] ), .I0 (vs_down_delay_cnt[0]), .I1 (vs_down_delay_cnt[1]), @@ -377694,7 +377193,7 @@ module multimedia_video_processor .I4_TO_LUT("FALSE")) \N123_0.fsub_3 ( .COUT (\N123_0.co [3] ), - .Z (N332[3]), + .Z (N333[3]), .CIN (\N123_0.co [2] ), .I0 (), .I1 (vs_down_delay_cnt[3]), @@ -377714,7 +377213,7 @@ module multimedia_video_processor .I4_TO_LUT("FALSE")) \N123_0.fsub_4 ( .COUT (\N123_0.co [4] ), - .Z (N332[4]), + .Z (N333[4]), .CIN (\N123_0.co [3] ), .I0 (), .I1 (vs_down_delay_cnt[4]), @@ -377734,7 +377233,7 @@ module multimedia_video_processor .I4_TO_LUT("FALSE")) \N123_0.fsub_5 ( .COUT (\N123_0.co [5] ), - .Z (N332[5]), + .Z (N333[5]), .CIN (\N123_0.co [4] ), .I0 (), .I1 (vs_down_delay_cnt[5]), @@ -377754,7 +377253,7 @@ module multimedia_video_processor .I4_TO_LUT("FALSE")) \N123_0.fsub_6 ( .COUT (\N123_0.co [6] ), - .Z (N332[6]), + .Z (N333[6]), .CIN (\N123_0.co [5] ), .I0 (), .I1 (vs_down_delay_cnt[6]), @@ -377774,7 +377273,7 @@ module multimedia_video_processor .I4_TO_LUT("FALSE")) \N123_0.fsub_7 ( .COUT (\N123_0.co [7] ), - .Z (N332[7]), + .Z (N333[7]), .CIN (\N123_0.co [6] ), .I0 (), .I1 (vs_down_delay_cnt[7]), @@ -377794,7 +377293,7 @@ module multimedia_video_processor .I4_TO_LUT("FALSE")) \N123_0.fsub_8 ( .COUT (\N123_0.co [8] ), - .Z (N332[8]), + .Z (N333[8]), .CIN (\N123_0.co [7] ), .I0 (), .I1 (vs_down_delay_cnt[8]), @@ -377814,7 +377313,7 @@ module multimedia_video_processor .I4_TO_LUT("FALSE")) \N123_0.fsub_9 ( .COUT (\N123_0.co [9] ), - .Z (N332[9]), + .Z (N333[9]), .CIN (\N123_0.co [8] ), .I0 (), .I1 (vs_down_delay_cnt[9]), @@ -377834,7 +377333,7 @@ module multimedia_video_processor .I4_TO_LUT("FALSE")) \N123_0.fsub_10 ( .COUT (\N123_0.co [10] ), - .Z (N332[10]), + .Z (N333[10]), .CIN (\N123_0.co [9] ), .I0 (), .I1 (vs_down_delay_cnt[10]), @@ -377854,7 +377353,7 @@ module multimedia_video_processor .I4_TO_LUT("FALSE")) \N123_0.fsub_11 ( .COUT (), - .Z (N332[11]), + .Z (N333[11]), .CIN (\N123_0.co [10] ), .I0 (), .I1 (vs_down_delay_cnt[11]), @@ -377871,459 +377370,449 @@ module multimedia_video_processor .I (rd3_rst)); // defparam N139_0_vname.orig_name = N139_0; - GTP_LUT4 /* N162_mux3 */ #( + GTP_LUT4 /* N163_mux3 */ #( .INIT(16'b0000000000011111)) - N162_mux3 ( - .Z (_N2277), + N163_mux3 ( + .Z (_N2279), .I0 (wr_water_level[5]), .I1 (wr_water_level[6]), .I2 (wr_water_level[7]), .I3 (wr_water_level[8])); // LUT = (~I2&~I3)|(~I0&~I1&~I3) ; - GTP_LUT5 /* N162_mux7 */ #( + GTP_LUT5 /* N163_mux7 */ #( .INIT(32'b00000000001111110000000000011111)) - N162_mux7 ( - .Z (N162), + N163_mux7 ( + .Z (N163), .I0 (wr_water_level[9]), .I1 (wr_water_level[10]), .I2 (wr_water_level[11]), .I3 (wr_water_level[12]), - .I4 (_N2277)); + .I4 (_N2279)); // LUT = (~I2&~I3)|(~I0&~I1&~I3)|(~I1&~I3&I4) ; - GTP_INV N241_0_vname ( - .Z (N241_0), + GTP_INV N242_0_vname ( + .Z (N242_0), .I (rd0_empty)); - // defparam N241_0_vname.orig_name = N241_0; + // defparam N242_0_vname.orig_name = N242_0; - GTP_LUT1 /* N245 */ #( + GTP_LUT1 /* N246 */ #( .INIT(2'b01)) - N245 ( + N246 ( .Z (\u_axi_ddr_top/u_axi_rd_connect/N78_rnmt ), .I0 (rd1_empty)); // LUT = ~I0 ; - GTP_INV N245_0 ( + GTP_INV N246_0 ( .Z (\u_axi_ddr_top/u_axi_rd_connect/N78_1_rnmt ), .I (rd1_empty)); - GTP_LUT4 /* N285_9 */ #( + GTP_LUT4 /* N286_9 */ #( .INIT(16'b0000000000000001)) - N285_9 ( - .Z (_N103957), + N286_9 ( + .Z (_N104781), .I0 (rstn_1ms[1]), .I1 (rstn_1ms[2]), .I2 (rstn_1ms[3]), .I3 (rstn_1ms[5])); // LUT = ~I0&~I1&~I2&~I3 ; - GTP_LUT4 /* N285_10 */ #( + GTP_LUT4 /* N286_10 */ #( .INIT(16'b0000000000000001)) - N285_10 ( - .Z (_N103958), + N286_10 ( + .Z (_N104782), .I0 (rstn_1ms[6]), .I1 (rstn_1ms[7]), .I2 (rstn_1ms[11]), .I3 (rstn_1ms[12])); // LUT = ~I0&~I1&~I2&~I3 ; - GTP_LUT4 /* N285_11 */ #( + GTP_LUT4 /* N286_11 */ #( .INIT(16'b1000000000000000)) - N285_11 ( - .Z (_N103959), + N286_11 ( + .Z (_N104783), .I0 (rstn_1ms[4]), .I1 (rstn_1ms[8]), .I2 (rstn_1ms[9]), .I3 (rstn_1ms[10])); // LUT = I0&I1&I2&I3 ; - GTP_LUT5 /* N285_14 */ #( + GTP_LUT5 /* N286_14 */ #( .INIT(32'b01000000000000000000000000000000)) - N285_14 ( - .Z (N285), + N286_14 ( + .Z (N286), .I0 (rstn_1ms[0]), .I1 (rstn_1ms[13]), - .I2 (_N103957), - .I3 (_N103958), - .I4 (_N103959)); + .I2 (_N104781), + .I3 (_N104782), + .I4 (_N104783)); // LUT = ~I0&I1&I2&I3&I4 ; - GTP_LUT4 /* N298_9 */ #( + GTP_LUT4 /* N299_9 */ #( .INIT(16'b0000000000000001)) - N298_9 ( - .Z (_N103731), + N299_9 ( + .Z (_N104550), .I0 (vs_pos_delay_cnt[5]), .I1 (vs_pos_delay_cnt[6]), .I2 (vs_pos_delay_cnt[7]), .I3 (vs_pos_delay_cnt[8])); // LUT = ~I0&~I1&~I2&~I3 ; - GTP_LUT5 /* N298_11 */ #( + GTP_LUT5 /* N299_11 */ #( .INIT(32'b00000000000000010000000000000000)) - N298_11 ( - .Z (_N103733), + N299_11 ( + .Z (_N104552), .I0 (vs_pos_delay_cnt[1]), .I1 (vs_pos_delay_cnt[2]), .I2 (vs_pos_delay_cnt[3]), .I3 (vs_pos_delay_cnt[4]), - .I4 (_N103731)); + .I4 (_N104550)); // LUT = ~I0&~I1&~I2&~I3&I4 ; - GTP_LUT5 /* N298_12 */ #( + GTP_LUT5 /* N299_12 */ #( .INIT(32'b00000000000000100000000000000000)) - N298_12 ( - .Z (N298), + N299_12 ( + .Z (N299), .I0 (vs_pos_delay_cnt[0]), .I1 (vs_pos_delay_cnt[9]), .I2 (vs_pos_delay_cnt[10]), .I3 (vs_pos_delay_cnt[11]), - .I4 (_N103733)); + .I4 (_N104552)); // LUT = I0&~I1&~I2&~I3&I4 ; - GTP_LUT5 /* N314 */ #( + GTP_LUT5 /* N315 */ #( .INIT(32'b00010101010101010101010101010101)) - N314_vname ( - .Z (N314[0]), + N315_vname ( + .Z (N315[0]), .I0 (rstn_1ms[0]), .I1 (rstn_1ms[13]), - .I2 (_N103957), - .I3 (_N103958), - .I4 (_N103959)); - // defparam N314_vname.orig_name = N314; + .I2 (_N104781), + .I3 (_N104782), + .I4 (_N104783)); + // defparam N315_vname.orig_name = N315; // LUT = (~I0&~I4)|(~I0&~I3)|(~I0&~I2)|(~I0&~I1) ; // ../../sources/designs/multimedia_video_processor.v:296 - GTP_LUT4 /* \N318_5[0] */ #( + GTP_LUT4 /* \N319_5[0] */ #( .INIT(16'b0000000010100010)) - \N318_5[0] ( - .Z (N318[0]), + \N319_5[0] ( + .Z (N319[0]), .I0 (N104), .I1 (camera_vs_ff0), .I2 (camera_vs_ff1), .I3 (vs_pos_delay_cnt[0])); // LUT = (I0&~I1&~I3)|(I0&I2&~I3) ; - GTP_LUT4 /* \N318_5[1] */ #( + GTP_LUT4 /* \N319_5[1] */ #( .INIT(16'b1010111000001100)) - \N318_5[1] ( - .Z (N318[1]), + \N319_5[1] ( + .Z (N319[1]), .I0 (N104), .I1 (camera_vs_ff0), .I2 (camera_vs_ff1), - .I3 (N334[1])); + .I3 (N335[1])); // LUT = (I1&~I2)|(I0&I3) ; - GTP_LUT4 /* \N318_5[2] */ #( + GTP_LUT4 /* \N319_5[2] */ #( .INIT(16'b1010111000001100)) - \N318_5[2] ( - .Z (N318[2]), + \N319_5[2] ( + .Z (N319[2]), .I0 (N104), .I1 (camera_vs_ff0), .I2 (camera_vs_ff1), - .I3 (N334[2])); + .I3 (N335[2])); // LUT = (I1&~I2)|(I0&I3) ; - GTP_LUT4 /* \N318_5[3] */ #( + GTP_LUT4 /* \N319_5[3] */ #( .INIT(16'b1010111000001100)) - \N318_5[3] ( - .Z (N318[3]), + \N319_5[3] ( + .Z (N319[3]), .I0 (N104), .I1 (camera_vs_ff0), .I2 (camera_vs_ff1), - .I3 (N334[3])); + .I3 (N335[3])); // LUT = (I1&~I2)|(I0&I3) ; - GTP_LUT4 /* \N318_5[4] */ #( + GTP_LUT4 /* \N319_5[4] */ #( .INIT(16'b1010111000001100)) - \N318_5[4] ( - .Z (N318[4]), + \N319_5[4] ( + .Z (N319[4]), .I0 (N104), .I1 (camera_vs_ff0), .I2 (camera_vs_ff1), - .I3 (N334[4])); + .I3 (N335[4])); // LUT = (I1&~I2)|(I0&I3) ; - GTP_LUT4 /* \N318_5[5] */ #( + GTP_LUT4 /* \N319_5[5] */ #( .INIT(16'b1010111000001100)) - \N318_5[5] ( - .Z (N318[5]), + \N319_5[5] ( + .Z (N319[5]), .I0 (N104), .I1 (camera_vs_ff0), .I2 (camera_vs_ff1), - .I3 (N334[5])); + .I3 (N335[5])); // LUT = (I1&~I2)|(I0&I3) ; - GTP_LUT4 /* \N318_5[6] */ #( + GTP_LUT4 /* \N319_5[6] */ #( .INIT(16'b1010111000001100)) - \N318_5[6] ( - .Z (N318[6]), + \N319_5[6] ( + .Z (N319[6]), .I0 (N104), .I1 (camera_vs_ff0), .I2 (camera_vs_ff1), - .I3 (N334[6])); + .I3 (N335[6])); // LUT = (I1&~I2)|(I0&I3) ; - GTP_LUT4 /* \N318_5[7] */ #( + GTP_LUT4 /* \N319_5[7] */ #( .INIT(16'b1010111000001100)) - \N318_5[7] ( - .Z (N318[7]), + \N319_5[7] ( + .Z (N319[7]), .I0 (N104), .I1 (camera_vs_ff0), .I2 (camera_vs_ff1), - .I3 (N334[7])); + .I3 (N335[7])); // LUT = (I1&~I2)|(I0&I3) ; - GTP_LUT4 /* \N318_5[8] */ #( + GTP_LUT4 /* \N319_5[8] */ #( .INIT(16'b1010111000001100)) - \N318_5[8] ( - .Z (N318[8]), + \N319_5[8] ( + .Z (N319[8]), .I0 (N104), .I1 (camera_vs_ff0), .I2 (camera_vs_ff1), - .I3 (N334[8])); + .I3 (N335[8])); // LUT = (I1&~I2)|(I0&I3) ; - GTP_LUT4 /* \N318_5[9] */ #( + GTP_LUT4 /* \N319_5[9] */ #( .INIT(16'b1010001000000000)) - \N318_5[9] ( - .Z (N318[9]), + \N319_5[9] ( + .Z (N319[9]), .I0 (N104), .I1 (camera_vs_ff0), .I2 (camera_vs_ff1), - .I3 (N334[9])); + .I3 (N335[9])); // LUT = (I0&~I1&I3)|(I0&I2&I3) ; - GTP_LUT4 /* \N318_5[10] */ #( + GTP_LUT4 /* \N319_5[10] */ #( .INIT(16'b1010001000000000)) - \N318_5[10] ( - .Z (N318[10]), + \N319_5[10] ( + .Z (N319[10]), .I0 (N104), .I1 (camera_vs_ff0), .I2 (camera_vs_ff1), - .I3 (N334[10])); + .I3 (N335[10])); // LUT = (I0&~I1&I3)|(I0&I2&I3) ; - GTP_LUT4 /* \N318_5[11] */ #( + GTP_LUT4 /* \N319_5[11] */ #( .INIT(16'b1010111000001100)) - \N318_5[11] ( - .Z (N318[11]), + \N319_5[11] ( + .Z (N319[11]), .I0 (N104), .I1 (camera_vs_ff0), .I2 (camera_vs_ff1), - .I3 (N334[11])); + .I3 (N335[11])); // LUT = (I1&~I2)|(I0&I3) ; - GTP_LUT4 /* \N322_5[0] */ #( + GTP_LUT4 /* \N323_5[0] */ #( .INIT(16'b0000000010001010)) - \N322_5[0] ( - .Z (N322[0]), + \N323_5[0] ( + .Z (N323[0]), .I0 (N119), .I1 (camera_vs_ff0), .I2 (camera_vs_ff1), .I3 (vs_down_delay_cnt[0])); // LUT = (I0&~I2&~I3)|(I0&I1&~I3) ; - GTP_LUT4 /* \N322_5[1] */ #( + GTP_LUT4 /* \N323_5[1] */ #( .INIT(16'b1011101000110000)) - \N322_5[1] ( - .Z (N322[1]), + \N323_5[1] ( + .Z (N323[1]), .I0 (N119), .I1 (camera_vs_ff0), .I2 (camera_vs_ff1), - .I3 (N332[1])); + .I3 (N333[1])); // LUT = (~I1&I2)|(I0&I3) ; - GTP_LUT4 /* \N322_5[2] */ #( + GTP_LUT4 /* \N323_5[2] */ #( .INIT(16'b1011101000110000)) - \N322_5[2] ( - .Z (N322[2]), + \N323_5[2] ( + .Z (N323[2]), .I0 (N119), .I1 (camera_vs_ff0), .I2 (camera_vs_ff1), - .I3 (N332[2])); + .I3 (N333[2])); // LUT = (~I1&I2)|(I0&I3) ; - GTP_LUT4 /* \N322_5[3] */ #( + GTP_LUT4 /* \N323_5[3] */ #( .INIT(16'b1011101000110000)) - \N322_5[3] ( - .Z (N322[3]), + \N323_5[3] ( + .Z (N323[3]), .I0 (N119), .I1 (camera_vs_ff0), .I2 (camera_vs_ff1), - .I3 (N332[3])); + .I3 (N333[3])); // LUT = (~I1&I2)|(I0&I3) ; - GTP_LUT4 /* \N322_5[4] */ #( + GTP_LUT4 /* \N323_5[4] */ #( .INIT(16'b1011101000110000)) - \N322_5[4] ( - .Z (N322[4]), + \N323_5[4] ( + .Z (N323[4]), .I0 (N119), .I1 (camera_vs_ff0), .I2 (camera_vs_ff1), - .I3 (N332[4])); + .I3 (N333[4])); // LUT = (~I1&I2)|(I0&I3) ; - GTP_LUT4 /* \N322_5[5] */ #( + GTP_LUT4 /* \N323_5[5] */ #( .INIT(16'b1011101000110000)) - \N322_5[5] ( - .Z (N322[5]), + \N323_5[5] ( + .Z (N323[5]), .I0 (N119), .I1 (camera_vs_ff0), .I2 (camera_vs_ff1), - .I3 (N332[5])); + .I3 (N333[5])); // LUT = (~I1&I2)|(I0&I3) ; - GTP_LUT4 /* \N322_5[6] */ #( + GTP_LUT4 /* \N323_5[6] */ #( .INIT(16'b1011101000110000)) - \N322_5[6] ( - .Z (N322[6]), + \N323_5[6] ( + .Z (N323[6]), .I0 (N119), .I1 (camera_vs_ff0), .I2 (camera_vs_ff1), - .I3 (N332[6])); + .I3 (N333[6])); // LUT = (~I1&I2)|(I0&I3) ; - GTP_LUT4 /* \N322_5[7] */ #( + GTP_LUT4 /* \N323_5[7] */ #( .INIT(16'b1011101000110000)) - \N322_5[7] ( - .Z (N322[7]), + \N323_5[7] ( + .Z (N323[7]), .I0 (N119), .I1 (camera_vs_ff0), .I2 (camera_vs_ff1), - .I3 (N332[7])); + .I3 (N333[7])); // LUT = (~I1&I2)|(I0&I3) ; - GTP_LUT4 /* \N322_5[8] */ #( + GTP_LUT4 /* \N323_5[8] */ #( .INIT(16'b1011101000110000)) - \N322_5[8] ( - .Z (N322[8]), + \N323_5[8] ( + .Z (N323[8]), .I0 (N119), .I1 (camera_vs_ff0), .I2 (camera_vs_ff1), - .I3 (N332[8])); + .I3 (N333[8])); // LUT = (~I1&I2)|(I0&I3) ; - GTP_LUT4 /* \N322_5[9] */ #( + GTP_LUT4 /* \N323_5[9] */ #( .INIT(16'b1000101000000000)) - \N322_5[9] ( - .Z (N322[9]), + \N323_5[9] ( + .Z (N323[9]), .I0 (N119), .I1 (camera_vs_ff0), .I2 (camera_vs_ff1), - .I3 (N332[9])); + .I3 (N333[9])); // LUT = (I0&~I2&I3)|(I0&I1&I3) ; - GTP_LUT4 /* \N322_5[10] */ #( + GTP_LUT4 /* \N323_5[10] */ #( .INIT(16'b1000101000000000)) - \N322_5[10] ( - .Z (N322[10]), + \N323_5[10] ( + .Z (N323[10]), .I0 (N119), .I1 (camera_vs_ff0), .I2 (camera_vs_ff1), - .I3 (N332[10])); + .I3 (N333[10])); // LUT = (I0&~I2&I3)|(I0&I1&I3) ; - GTP_LUT4 /* \N322_5[11] */ #( + GTP_LUT4 /* \N323_5[11] */ #( .INIT(16'b1011101000110000)) - \N322_5[11] ( - .Z (N322[11]), + \N323_5[11] ( + .Z (N323[11]), .I0 (N119), .I1 (camera_vs_ff0), .I2 (camera_vs_ff1), - .I3 (N332[11])); + .I3 (N333[11])); // LUT = (~I1&I2)|(I0&I3) ; - GTP_LUT4 /* N328_9 */ #( + GTP_LUT4 /* N329_9 */ #( .INIT(16'b0000000000000001)) - N328_9 ( - .Z (_N103742), + N329_9 ( + .Z (_N104561), .I0 (vs_down_delay_cnt[5]), .I1 (vs_down_delay_cnt[6]), .I2 (vs_down_delay_cnt[7]), .I3 (vs_down_delay_cnt[8])); // LUT = ~I0&~I1&~I2&~I3 ; - GTP_LUT4 /* N328_10 */ #( + GTP_LUT4 /* N329_10 */ #( .INIT(16'b0000000000000010)) - N328_10 ( - .Z (_N103743), + N329_10 ( + .Z (_N104562), .I0 (vs_down_delay_cnt[0]), .I1 (vs_down_delay_cnt[9]), .I2 (vs_down_delay_cnt[10]), .I3 (vs_down_delay_cnt[11])); // LUT = I0&~I1&~I2&~I3 ; - GTP_LUT5 /* N328_11 */ #( + GTP_LUT5 /* N329_11 */ #( .INIT(32'b00000000000000010000000000000000)) - N328_11 ( - .Z (_N103744), + N329_11 ( + .Z (_N104563), .I0 (vs_down_delay_cnt[1]), .I1 (vs_down_delay_cnt[2]), .I2 (vs_down_delay_cnt[3]), .I3 (vs_down_delay_cnt[4]), - .I4 (_N103742)); + .I4 (_N104561)); // LUT = ~I0&~I1&~I2&~I3&I4 ; HDMI_PLL U_HDMI_PLL ( + .clkout0 (zoom_clk), .clkout1 (nt_pix_clk), .pll_lock (pll_hdmi_locked), .clkin1 (rd3_clk)); // ../../sources/designs/multimedia_video_processor.v:273 - GTP_LUT5 /* _N18115_inv */ #( - .INIT(32'b00000000000000000011001100110111)) - _N18115_inv ( - .Z (_N18115), - .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N137_rnmt ), - .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt [3] ), - .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg [7] ), - .I3 (_N97085), - .I4 (_N106355)); - // LUT = (~I1&~I4)|(~I0&~I2&~I3&~I4) ; - - GTP_LUT5 /* _N81412_1_inv */ #( + GTP_LUT5 /* _N82185_1_inv */ #( .INIT(32'b00000000000000001001000000000000)) - _N81412_1_inv ( + _N82185_1_inv ( .Z (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N538_rnmt ), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [9] ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin_div2 [7] ), - .I2 (_N81412_3), - .I3 (_N81412_5), - .I4 (_N105817)); + .I2 (_N82185_3), + .I3 (_N82185_5), + .I4 (_N106639)); // LUT = (~I0&~I1&I2&I3&~I4)|(I0&I1&I2&I3&~I4) ; - GTP_LUT5 /* _N81413_1_inv */ #( + GTP_LUT5 /* _N82186_1_inv */ #( .INIT(32'b00000000000000001001000000000000)) - _N81413_1_inv ( + _N82186_1_inv ( .Z (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N538_rnmt ), .I0 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [9] ), .I1 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin_div2 [7] ), - .I2 (_N81413_3), - .I3 (_N81413_5), - .I4 (_N105268)); + .I2 (_N82186_3), + .I3 (_N82186_5), + .I4 (_N106081)); // LUT = (~I0&~I1&I2&I3&~I4)|(I0&I1&I2&I3&~I4) ; - GTP_LUT5 /* _N81414_1_inv */ #( + GTP_LUT5 /* _N82187_1_inv */ #( .INIT(32'b00000000000000001000000000001000)) - _N81414_1_inv ( + _N82187_1_inv ( .Z (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N538_rnmt ), - .I0 (_N81414_3), - .I1 (_N81414_5), + .I0 (_N82187_3), + .I1 (_N82187_5), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [9] ), .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin_div2 [7] ), - .I4 (_N106518)); + .I4 (_N107336)); // LUT = (I0&I1&~I2&~I3&~I4)|(I0&I1&I2&I3&~I4) ; - GTP_LUT5 /* _N81415_1_inv */ #( + GTP_LUT5 /* _N82188_1_inv */ #( .INIT(32'b00000000000000001000000000001000)) - _N81415_1_inv ( + _N82188_1_inv ( .Z (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N538_rnmt ), - .I0 (_N81415_3), - .I1 (_N81415_5), + .I0 (_N82188_3), + .I1 (_N82188_5), .I2 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [9] ), .I3 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin_div2 [7] ), - .I4 (_N106490)); + .I4 (_N107308)); // LUT = (I0&I1&~I2&~I3&~I4)|(I0&I1&I2&I3&~I4) ; adjust_color_wrapper adjust_color_wrapper_inst ( @@ -378342,7 +377831,7 @@ module multimedia_video_processor .hs_in (hs_osd), .sync_vg_100m (sync_vg_100m), .vs_in (vs_osd)); - // ../../sources/designs/multimedia_video_processor.v:823 + // ../../sources/designs/multimedia_video_processor.v:825 (* PAP_IO_DIRECTION="INPUT", PAP_IO_LOC="W15", PAP_IO_VCCIO="3.3", PAP_IO_STANDARD="LVCMOS12", PAP_IO_NONE="TRUE" *) GTP_INBUF /* \b_in_ibuf[3] */ #( .IOSTANDARD("DEFAULT"), @@ -378497,7 +377986,7 @@ module multimedia_video_processor .C (N21), .CE (N24), .CLK (nt_pix_clk), - .D (N336[1])); + .D (N337[1])); // ../../sources/designs/multimedia_video_processor.v:319 GTP_DFF_CE /* \clk_cnt[2] */ #( @@ -378508,7 +377997,7 @@ module multimedia_video_processor .C (N21), .CE (N24), .CLK (nt_pix_clk), - .D (N336[2])); + .D (N337[2])); // ../../sources/designs/multimedia_video_processor.v:319 GTP_DFF_CE /* \clk_cnt[3] */ #( @@ -378519,7 +378008,7 @@ module multimedia_video_processor .C (N21), .CE (N24), .CLK (nt_pix_clk), - .D (N336[3])); + .D (N337[3])); // ../../sources/designs/multimedia_video_processor.v:319 GTP_DFF_CE /* \clk_cnt[4] */ #( @@ -378530,7 +378019,7 @@ module multimedia_video_processor .C (N21), .CE (N24), .CLK (nt_pix_clk), - .D (N336[4])); + .D (N337[4])); // ../../sources/designs/multimedia_video_processor.v:319 GTP_DFF_CE /* \clk_cnt[5] */ #( @@ -378541,7 +378030,7 @@ module multimedia_video_processor .C (N21), .CE (N24), .CLK (nt_pix_clk), - .D (N336[5])); + .D (N337[5])); // ../../sources/designs/multimedia_video_processor.v:319 GTP_DFF_CE /* \clk_cnt[6] */ #( @@ -378552,7 +378041,7 @@ module multimedia_video_processor .C (N21), .CE (N24), .CLK (nt_pix_clk), - .D (N336[6])); + .D (N337[6])); // ../../sources/designs/multimedia_video_processor.v:319 GTP_DFF_CE /* \clk_cnt[7] */ #( @@ -378563,7 +378052,7 @@ module multimedia_video_processor .C (N21), .CE (N24), .CLK (nt_pix_clk), - .D (N336[7])); + .D (N337[7])); // ../../sources/designs/multimedia_video_processor.v:319 GTP_DFF_CE /* \clk_cnt[8] */ #( @@ -378574,7 +378063,7 @@ module multimedia_video_processor .C (N21), .CE (N24), .CLK (nt_pix_clk), - .D (N336[8])); + .D (N337[8])); // ../../sources/designs/multimedia_video_processor.v:319 GTP_DFF_CE /* \clk_cnt[9] */ #( @@ -378585,7 +378074,7 @@ module multimedia_video_processor .C (N21), .CE (N24), .CLK (nt_pix_clk), - .D (N336[9])); + .D (N337[9])); // ../../sources/designs/multimedia_video_processor.v:319 GTP_DFF_CE /* \clk_cnt[10] */ #( @@ -378596,7 +378085,7 @@ module multimedia_video_processor .C (N21), .CE (N24), .CLK (nt_pix_clk), - .D (N336[10])); + .D (N337[10])); // ../../sources/designs/multimedia_video_processor.v:319 GTP_DFF_CE /* \clk_cnt[11] */ #( @@ -378607,7 +378096,7 @@ module multimedia_video_processor .C (N21), .CE (N24), .CLK (nt_pix_clk), - .D (N336[11])); + .D (N337[11])); // ../../sources/designs/multimedia_video_processor.v:319 GTP_DFF_CE /* \clk_cnt[12] */ #( @@ -378618,7 +378107,7 @@ module multimedia_video_processor .C (N21), .CE (N24), .CLK (nt_pix_clk), - .D (N336[12])); + .D (N337[12])); // ../../sources/designs/multimedia_video_processor.v:319 GTP_DFF_CE /* \clk_cnt[13] */ #( @@ -378629,7 +378118,7 @@ module multimedia_video_processor .C (N21), .CE (N24), .CLK (nt_pix_clk), - .D (N336[13])); + .D (N337[13])); // ../../sources/designs/multimedia_video_processor.v:319 GTP_DFF_CE /* \clk_cnt[14] */ #( @@ -378640,7 +378129,7 @@ module multimedia_video_processor .C (N21), .CE (N24), .CLK (nt_pix_clk), - .D (N336[14])); + .D (N337[14])); // ../../sources/designs/multimedia_video_processor.v:319 GTP_DFF_CE /* \clk_cnt[15] */ #( @@ -378651,7 +378140,7 @@ module multimedia_video_processor .C (N21), .CE (N24), .CLK (nt_pix_clk), - .D (N336[15])); + .D (N337[15])); // ../../sources/designs/multimedia_video_processor.v:319 GTP_DFF_CE /* \clk_cnt[16] */ #( @@ -378662,7 +378151,7 @@ module multimedia_video_processor .C (N21), .CE (N24), .CLK (nt_pix_clk), - .D (N336[16])); + .D (N337[16])); // ../../sources/designs/multimedia_video_processor.v:319 GTP_DFF_CE /* \clk_cnt[17] */ #( @@ -378673,7 +378162,7 @@ module multimedia_video_processor .C (N21), .CE (N24), .CLK (nt_pix_clk), - .D (N336[17])); + .D (N337[17])); // ../../sources/designs/multimedia_video_processor.v:319 GTP_DFF_CE /* \clk_cnt[18] */ #( @@ -378684,7 +378173,7 @@ module multimedia_video_processor .C (N21), .CE (N24), .CLK (nt_pix_clk), - .D (N336[18])); + .D (N337[18])); // ../../sources/designs/multimedia_video_processor.v:319 GTP_DFF_CE /* \clk_cnt[19] */ #( @@ -378695,7 +378184,7 @@ module multimedia_video_processor .C (N21), .CE (N24), .CLK (nt_pix_clk), - .D (N336[19])); + .D (N337[19])); // ../../sources/designs/multimedia_video_processor.v:319 GTP_DFF_CE /* \clk_cnt[20] */ #( @@ -378706,7 +378195,7 @@ module multimedia_video_processor .C (N21), .CE (N24), .CLK (nt_pix_clk), - .D (N336[20])); + .D (N337[20])); // ../../sources/designs/multimedia_video_processor.v:319 GTP_DFF_CE /* \clk_cnt[21] */ #( @@ -378717,7 +378206,7 @@ module multimedia_video_processor .C (N21), .CE (N24), .CLK (nt_pix_clk), - .D (N336[21])); + .D (N337[21])); // ../../sources/designs/multimedia_video_processor.v:319 GTP_DFF_CE /* \clk_cnt[22] */ #( @@ -378728,7 +378217,7 @@ module multimedia_video_processor .C (N21), .CE (N24), .CLK (nt_pix_clk), - .D (N336[22])); + .D (N337[22])); // ../../sources/designs/multimedia_video_processor.v:319 GTP_DFF_CE /* \clk_cnt[23] */ #( @@ -378739,7 +378228,7 @@ module multimedia_video_processor .C (N21), .CE (N24), .CLK (nt_pix_clk), - .D (N336[23])); + .D (N337[23])); // ../../sources/designs/multimedia_video_processor.v:319 GTP_DFF_CE /* \clk_cnt[24] */ #( @@ -378750,7 +378239,7 @@ module multimedia_video_processor .C (N21), .CE (N24), .CLK (nt_pix_clk), - .D (N336[24])); + .D (N337[24])); // ../../sources/designs/multimedia_video_processor.v:319 GTP_DFF_CE /* \clk_cnt[25] */ #( @@ -378761,7 +378250,7 @@ module multimedia_video_processor .C (N21), .CE (N24), .CLK (nt_pix_clk), - .D (N336[25])); + .D (N337[25])); // ../../sources/designs/multimedia_video_processor.v:319 GTP_DFF_CE /* \clk_cnt[26] */ #( @@ -378772,7 +378261,7 @@ module multimedia_video_processor .C (N21), .CE (N24), .CLK (nt_pix_clk), - .D (N336[26])); + .D (N337[26])); // ../../sources/designs/multimedia_video_processor.v:319 GTP_DFF_CE /* \clk_cnt[27] */ #( @@ -378783,7 +378272,7 @@ module multimedia_video_processor .C (N21), .CE (N24), .CLK (nt_pix_clk), - .D (N336[27])); + .D (N337[27])); // ../../sources/designs/multimedia_video_processor.v:319 GTP_DFF_CE /* \clk_cnt[28] */ #( @@ -378794,7 +378283,7 @@ module multimedia_video_processor .C (N21), .CE (N24), .CLK (nt_pix_clk), - .D (N336[28])); + .D (N337[28])); // ../../sources/designs/multimedia_video_processor.v:319 GTP_LUT1 /* \clk_cnt[29:0]_inv_13 */ #( @@ -378812,7 +378301,7 @@ module multimedia_video_processor .C (N21), .CE (N24), .CLK (nt_pix_clk), - .D (N336[29])); + .D (N337[29])); // ../../sources/designs/multimedia_video_processor.v:319 (* PAP_IO_DIRECTION="INPUT", PAP_IO_LOC="P20", PAP_IO_VCCIO="3.3", PAP_IO_STANDARD="LVCMOS12", PAP_IO_NONE="TRUE" *) GTP_INBUF /* clk_ibuf */ #( @@ -379198,7 +378687,7 @@ module multimedia_video_processor .Q (hdmi_b_out[0]), .CLK (nt_pix_clk), .D (hdmi_image_data[2])); - // ../../sources/designs/multimedia_video_processor.v:757 + // ../../sources/designs/multimedia_video_processor.v:759 GTP_DFF /* \hdmi_b_out[1] */ #( .GRS_EN("TRUE"), @@ -379207,7 +378696,7 @@ module multimedia_video_processor .Q (hdmi_b_out[1]), .CLK (nt_pix_clk), .D (hdmi_image_data[3])); - // ../../sources/designs/multimedia_video_processor.v:757 + // ../../sources/designs/multimedia_video_processor.v:759 GTP_DFF /* \hdmi_b_out[2] */ #( .GRS_EN("TRUE"), @@ -379216,7 +378705,7 @@ module multimedia_video_processor .Q (hdmi_b_out[2]), .CLK (nt_pix_clk), .D (hdmi_image_data[4])); - // ../../sources/designs/multimedia_video_processor.v:757 + // ../../sources/designs/multimedia_video_processor.v:759 GTP_DFF /* \hdmi_b_out[3] */ #( .GRS_EN("TRUE"), @@ -379225,7 +378714,7 @@ module multimedia_video_processor .Q (hdmi_b_out[3]), .CLK (nt_pix_clk), .D (hdmi_image_data[0])); - // ../../sources/designs/multimedia_video_processor.v:757 + // ../../sources/designs/multimedia_video_processor.v:759 GTP_DFF /* \hdmi_b_out[4] */ #( .GRS_EN("TRUE"), @@ -379234,7 +378723,7 @@ module multimedia_video_processor .Q (hdmi_b_out[4]), .CLK (nt_pix_clk), .D (hdmi_image_data[1])); - // ../../sources/designs/multimedia_video_processor.v:757 + // ../../sources/designs/multimedia_video_processor.v:759 GTP_DFF /* hdmi_de_out1 */ #( .GRS_EN("TRUE"), @@ -379244,7 +378733,7 @@ module multimedia_video_processor .CLK (nt_pix_clk), .D (hdmi_de_out0)); // defparam hdmi_de_out1_vname.orig_name = hdmi_de_out1; - // ../../sources/designs/multimedia_video_processor.v:757 + // ../../sources/designs/multimedia_video_processor.v:759 GTP_DFF /* \hdmi_g_out[0] */ #( .GRS_EN("TRUE"), @@ -379253,7 +378742,7 @@ module multimedia_video_processor .Q (hdmi_g_out[0]), .CLK (nt_pix_clk), .D (hdmi_image_data[9])); - // ../../sources/designs/multimedia_video_processor.v:757 + // ../../sources/designs/multimedia_video_processor.v:759 GTP_DFF /* \hdmi_g_out[1] */ #( .GRS_EN("TRUE"), @@ -379262,7 +378751,7 @@ module multimedia_video_processor .Q (hdmi_g_out[1]), .CLK (nt_pix_clk), .D (hdmi_image_data[10])); - // ../../sources/designs/multimedia_video_processor.v:757 + // ../../sources/designs/multimedia_video_processor.v:759 GTP_DFF /* \hdmi_g_out[2] */ #( .GRS_EN("TRUE"), @@ -379271,7 +378760,7 @@ module multimedia_video_processor .Q (hdmi_g_out[2]), .CLK (nt_pix_clk), .D (hdmi_image_data[5])); - // ../../sources/designs/multimedia_video_processor.v:757 + // ../../sources/designs/multimedia_video_processor.v:759 GTP_DFF /* \hdmi_g_out[3] */ #( .GRS_EN("TRUE"), @@ -379280,7 +378769,7 @@ module multimedia_video_processor .Q (hdmi_g_out[3]), .CLK (nt_pix_clk), .D (hdmi_image_data[6])); - // ../../sources/designs/multimedia_video_processor.v:757 + // ../../sources/designs/multimedia_video_processor.v:759 GTP_DFF /* \hdmi_g_out[4] */ #( .GRS_EN("TRUE"), @@ -379289,7 +378778,7 @@ module multimedia_video_processor .Q (hdmi_g_out[4]), .CLK (nt_pix_clk), .D (hdmi_image_data[7])); - // ../../sources/designs/multimedia_video_processor.v:757 + // ../../sources/designs/multimedia_video_processor.v:759 GTP_DFF /* \hdmi_g_out[5] */ #( .GRS_EN("TRUE"), @@ -379298,7 +378787,7 @@ module multimedia_video_processor .Q (hdmi_g_out[5]), .CLK (nt_pix_clk), .D (hdmi_image_data[8])); - // ../../sources/designs/multimedia_video_processor.v:757 + // ../../sources/designs/multimedia_video_processor.v:759 GTP_DFF /* hdmi_hs_out1 */ #( .GRS_EN("TRUE"), @@ -379308,7 +378797,7 @@ module multimedia_video_processor .CLK (nt_pix_clk), .D (hdmi_hs_out0)); // defparam hdmi_hs_out1_vname.orig_name = hdmi_hs_out1; - // ../../sources/designs/multimedia_video_processor.v:757 + // ../../sources/designs/multimedia_video_processor.v:759 (* PAP_IO_DIRECTION="INPUT", PAP_IO_LOC="AA12", PAP_IO_VCCIO="3.3", PAP_IO_STANDARD="LVCMOS12", PAP_IO_NONE="TRUE" *) GTP_INBUF /* hdmi_in_clk_ibuf */ #( .IOSTANDARD("DEFAULT"), @@ -379325,7 +378814,7 @@ module multimedia_video_processor .Q (hdmi_r_out[0]), .CLK (nt_pix_clk), .D (hdmi_image_data[13])); - // ../../sources/designs/multimedia_video_processor.v:757 + // ../../sources/designs/multimedia_video_processor.v:759 GTP_DFF /* \hdmi_r_out[1] */ #( .GRS_EN("TRUE"), @@ -379334,7 +378823,7 @@ module multimedia_video_processor .Q (hdmi_r_out[1]), .CLK (nt_pix_clk), .D (hdmi_image_data[14])); - // ../../sources/designs/multimedia_video_processor.v:757 + // ../../sources/designs/multimedia_video_processor.v:759 GTP_DFF /* \hdmi_r_out[2] */ #( .GRS_EN("TRUE"), @@ -379343,7 +378832,7 @@ module multimedia_video_processor .Q (hdmi_r_out[2]), .CLK (nt_pix_clk), .D (hdmi_image_data[15])); - // ../../sources/designs/multimedia_video_processor.v:757 + // ../../sources/designs/multimedia_video_processor.v:759 GTP_DFF /* \hdmi_r_out[3] */ #( .GRS_EN("TRUE"), @@ -379352,7 +378841,7 @@ module multimedia_video_processor .Q (hdmi_r_out[3]), .CLK (nt_pix_clk), .D (hdmi_image_data[11])); - // ../../sources/designs/multimedia_video_processor.v:757 + // ../../sources/designs/multimedia_video_processor.v:759 GTP_DFF /* \hdmi_r_out[4] */ #( .GRS_EN("TRUE"), @@ -379361,7 +378850,7 @@ module multimedia_video_processor .Q (hdmi_r_out[4]), .CLK (nt_pix_clk), .D (hdmi_image_data[12])); - // ../../sources/designs/multimedia_video_processor.v:757 + // ../../sources/designs/multimedia_video_processor.v:759 GTP_DFF /* hdmi_vs_out1 */ #( .GRS_EN("TRUE"), @@ -379371,7 +378860,7 @@ module multimedia_video_processor .CLK (nt_pix_clk), .D (hdmi_vs_out0)); // defparam hdmi_vs_out1_vname.orig_name = hdmi_vs_out1; - // ../../sources/designs/multimedia_video_processor.v:757 + // ../../sources/designs/multimedia_video_processor.v:759 (* PAP_IO_DIRECTION="INPUT", PAP_IO_LOC="V13", PAP_IO_VCCIO="3.3", PAP_IO_STANDARD="LVCMOS12", PAP_IO_NONE="TRUE" *) GTP_INBUF /* hs_in_ibuf */ #( .IOSTANDARD("DEFAULT"), @@ -379411,22 +378900,20 @@ module multimedia_video_processor image_filiter image_filiter_inst ( .m_filtered_data (temp_d), .mode (param_filiter1_mode), - .\param_manager_inst/selected ({\param_manager_inst/selected [13] , 1'bx, 1'bx, 1'bx, 1'bx, \param_manager_inst/selected [8] , 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), + .\param_manager_inst/selected ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \param_manager_inst/selected [1] , \param_manager_inst/selected [0] }), .s_pixel_data (camera_data), .\image_filiter_inst2/multiline_buffer_inst/N272 (\image_filiter_inst2/multiline_buffer_inst/N272 ), .m_filtered_valid (temp_v), .\multiline_buffer_inst/srst (\image_filiter_inst/multiline_buffer_inst/srst ), - .\param_manager_inst/param_modify_V/N140 (\param_manager_inst/param_modify_V/N140 ), - .\param_manager_inst/param_rotate_A/N142 (\param_manager_inst/param_rotate_A/N142 ), - ._N97340 (_N97340), - ._N103920 (_N103920), + .\param_manager_inst/param_filiter1_mode/N140 (\param_manager_inst/param_filiter1_mode/N140 ), + .\param_manager_inst/param_filiter2_mode/N140 (\param_manager_inst/param_filiter2_mode/N140 ), + ._N98107 (_N98107), + ._N104744 (_N104744), .clk (rd3_clk), .\image_filiter_inst2/multiline_buffer_inst/N53 (\image_filiter_inst2/multiline_buffer_inst/N53 ), .\param_manager_inst/param_filiter1_mode/changed_down (\param_manager_inst/param_filiter1_mode/changed_down ), - .\param_manager_inst/param_filiter1_mode/changed_up (\param_manager_inst/param_filiter1_mode/changed_up ), + .\param_manager_inst/param_filiter1_mode/pluse (\param_manager_inst/param_filiter1_mode/pluse ), .\param_manager_inst/param_filiter1_mode/pressed_down (\param_manager_inst/param_filiter1_mode/pressed_down ), - .\param_manager_inst/param_filiter1_mode/pressed_up (\param_manager_inst/param_filiter1_mode/pressed_up ), - .\param_manager_inst/param_modify_H/pluse (\param_manager_inst/param_modify_H/pluse ), .rd3_rst (rd3_rst), .s_pixel_valid (camera_valid)); // ../../sources/designs/multimedia_video_processor.v:600 @@ -379434,19 +378921,14 @@ module multimedia_video_processor image_filiter_unq4 image_filiter_inst2 ( .m_filtered_data (wr0_data_in), .mode (param_filiter2_mode), - .\param_manager_inst/selected ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, \param_manager_inst/selected [2] , 1'bx, 1'bx}), .s_pixel_data (temp_d), - ._N97340 (_N97340), - ._N103920 (_N103920), + ._N98107 (_N98107), + ._N104744 (_N104744), .m_filtered_valid (wr0_data_in_valid), .\multiline_buffer_inst/N53 (\image_filiter_inst2/multiline_buffer_inst/N53 ), - .\param_manager_inst/param_zoom/N142 (\param_manager_inst/param_zoom/N142 ), .clk (rd3_clk), .\image_filiter_inst/multiline_buffer_inst/srst (\image_filiter_inst/multiline_buffer_inst/srst ), .\multiline_buffer_inst/N272 (\image_filiter_inst2/multiline_buffer_inst/N272 ), - .\param_manager_inst/param_filiter1_mode/changed_up (\param_manager_inst/param_filiter1_mode/changed_up ), - .\param_manager_inst/param_filiter1_mode/pressed_up (\param_manager_inst/param_filiter1_mode/pressed_up ), - .\param_manager_inst/param_modify_H/pluse (\param_manager_inst/param_modify_H/pluse ), .rd3_rst (rd3_rst), .s_pixel_valid (temp_v)); // ../../sources/designs/multimedia_video_processor.v:618 @@ -379630,24 +379112,21 @@ module multimedia_video_processor .osd_startY (param_osd_startY), .rotate (param_rotate), .rotate_A (param_rotate_A), - .selected ({\param_manager_inst/selected [13] , \param_manager_inst_selected[12]_floating , \param_manager_inst_selected[11]_floating , \param_manager_inst_selected[10]_floating , \param_manager_inst_selected[9]_floating , \param_manager_inst/selected [8] , \param_manager_inst_selected[7]_floating , \param_manager_inst_selected[6]_floating , \param_manager_inst_selected[5]_floating , \param_manager_inst_selected[4]_floating , \param_manager_inst_selected[3]_floating , \param_manager_inst/selected [2] , \param_manager_inst_selected[1]_floating , \param_manager_inst_selected[0]_floating }), + .selected ({\param_manager_inst_selected[13]_floating , \param_manager_inst_selected[12]_floating , \param_manager_inst_selected[11]_floating , \param_manager_inst_selected[10]_floating , \param_manager_inst_selected[9]_floating , \param_manager_inst_selected[8]_floating , \param_manager_inst_selected[7]_floating , \param_manager_inst_selected[6]_floating , \param_manager_inst_selected[5]_floating , \param_manager_inst_selected[4]_floating , \param_manager_inst_selected[3]_floating , \param_manager_inst_selected[2]_floating , \param_manager_inst/selected [1] , \param_manager_inst/selected [0] }), .zoom (param_zoom), .mem ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, mem[192], mem[191], mem[190], mem[189], mem[188], mem[187], mem[186], mem[185], mem[184], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, mem[176], mem[175], mem[174], mem[173], mem[172], mem[171], mem[170], mem[169], mem[168], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, mem[160], mem[159], mem[158], mem[157], mem[156], mem[155], mem[154], mem[153], mem[152], 1'bx, 1'bx, 1'bx, 1'bx, mem[147], mem[146], mem[145], mem[144], mem[143], mem[142], mem[141], mem[140], mem[139], mem[138], mem[137], mem[136], 1'bx, 1'bx, 1'bx, 1'bx, mem[131], mem[130], mem[129], mem[128], mem[127], mem[126], mem[125], mem[124], mem[123], mem[122], mem[121], mem[120], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, mem[113], mem[112], mem[111], mem[110], mem[109], mem[108], mem[107], mem[106], mem[105], mem[104], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, mem[98], mem[97], mem[96], mem[95], mem[94], mem[93], mem[92], mem[91], mem[90], mem[89], mem[88], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, mem[82], mem[81], mem[80], mem[79], mem[78], mem[77], mem[76], mem[75], mem[74], mem[73], mem[72], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, mem[66], mem[65], mem[64], mem[63], mem[62], mem[61], mem[60], mem[59], mem[58], mem[57], mem[56], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, mem[50], mem[49], mem[48], mem[47], mem[46], mem[45], mem[44], mem[43], mem[42], mem[41], mem[40], mem[39], mem[38], mem[37], mem[36], mem[35], mem[34], mem[33], mem[32], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, mem[25], mem[24], mem[23], mem[22], mem[21], mem[20], mem[19], mem[18], mem[17], mem[16], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, mem[10], mem[9], mem[8], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, mem[2], mem[1], mem[0]}), .mem_flags (mem_flags), .\param_filiter1_mode/changed_down (\param_manager_inst/param_filiter1_mode/changed_down ), - .\param_filiter1_mode/changed_up (\param_manager_inst/param_filiter1_mode/changed_up ), + .\param_filiter1_mode/pluse (\param_manager_inst/param_filiter1_mode/pluse ), .\param_filiter1_mode/pressed_down (\param_manager_inst/param_filiter1_mode/pressed_down ), - .\param_filiter1_mode/pressed_up (\param_manager_inst/param_filiter1_mode/pressed_up ), - .\param_modify_H/pluse (\param_manager_inst/param_modify_H/pluse ), .akey_down (nt_key[5]), .akey_left (nt_key[2]), .akey_restore (nt_key[6]), .akey_right (nt_key[3]), .akey_up (nt_key[4]), .clk (gmii_clk), - .\param_modify_V/N140 (\param_manager_inst/param_modify_V/N140 ), - .\param_rotate_A/N142 (\param_manager_inst/param_rotate_A/N142 ), - .\param_zoom/N142 (\param_manager_inst/param_zoom/N142 ), + .\param_filiter1_mode/N140 (\param_manager_inst/param_filiter1_mode/N140 ), + .\param_filiter2_mode/N140 (\param_manager_inst/param_filiter2_mode/N140 ), .rd2_rst (rd2_rst)); // ../../sources/designs/multimedia_video_processor.v:467 @@ -379779,7 +379258,7 @@ module multimedia_video_processor .Q (rstn_1ms[0]), .C (N9), .CLK (clk_10m), - .D (N314[0])); + .D (N315[0])); // ../../sources/designs/multimedia_video_processor.v:296 GTP_DFF_C /* \rstn_1ms[1] */ #( @@ -379938,7 +379417,7 @@ module multimedia_video_processor .Q (rstn_out0), .C (N9), .CLK (clk_10m), - .D (N285)); + .D (N286)); // defparam rstn_out0_vname.orig_name = rstn_out0; // ../../sources/designs/multimedia_video_processor.v:296 @@ -379976,8 +379455,6 @@ module multimedia_video_processor .mem_dq (mem_dq), .mem_dqs (mem_dqs), .mem_dqs_n (mem_dqs_n), - .\I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt ({\u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[7]_floating , \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[6]_floating , \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[5]_floating , \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[4]_floating , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt [3] , \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[2]_floating , \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[1]_floating , \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[0]_floating }), - .\I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg ({\u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[8]_floating , \u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg [7] , \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[6]_floating , \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[5]_floating , \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]_floating , \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[3]_floating , \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[2]_floating , \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[1]_floating , \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[0]_floating }), .\I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt ({\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [9] , \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[8]_floating , \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[7]_floating , \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[6]_floating , \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[5]_floating , \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[4]_floating , \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[3]_floating , \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[2]_floating , \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[1]_floating , \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]_floating }), .\I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin_div2 ({\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin_div2 [7] , \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin_div2[6]_floating , \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin_div2[5]_floating , \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin_div2[4]_floating , \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin_div2[3]_floating , \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin_div2[2]_floating , \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin_div2[1]_floating , \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin_div2[0]_floating }), .\I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt ({\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt [9] , \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[8]_floating , \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[7]_floating , \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[6]_floating , \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[5]_floating , \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[4]_floating , \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[3]_floating , \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[2]_floating , \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[1]_floating , \u_axi_ddr_top_I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]_floating }), @@ -380000,21 +379477,18 @@ module multimedia_video_processor .wr1_ddr_sart_addr ({1'bx, 1'bx, 1'bx, 1'bx, wr1_ddr_addr[25], wr1_ddr_addr[24], wr1_ddr_addr[23], wr1_ddr_addr[22], wr1_ddr_addr[21], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), .wr3_data_in (wr3_data_in), .wr3_ddr_sart_addr ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, wr3_ddr_addr[23], wr3_ddr_addr[22], wr3_ddr_addr[21], 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx, 1'bx}), - .\I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N137 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N137_rnmt ), - ._N81412_3 (_N81412_3), - ._N81412_5 (_N81412_5), - ._N81413_3 (_N81413_3), - ._N81413_5 (_N81413_5), - ._N81414_3 (_N81414_3), - ._N81414_5 (_N81414_5), - ._N81415_3 (_N81415_3), - ._N81415_5 (_N81415_5), - ._N97085 (_N97085), - ._N105268 (_N105268), - ._N105817 (_N105817), - ._N106355 (_N106355), - ._N106490 (_N106490), - ._N106518 (_N106518), + ._N82185_3 (_N82185_3), + ._N82185_5 (_N82185_5), + ._N82186_3 (_N82186_3), + ._N82186_5 (_N82186_5), + ._N82187_3 (_N82187_3), + ._N82187_5 (_N82187_5), + ._N82188_3 (_N82188_3), + ._N82188_5 (_N82188_5), + ._N106081 (_N106081), + ._N106639 (_N106639), + ._N107308 (_N107308), + ._N107336 (_N107336), .init_calib_complete (init_calib_complete), .mem_cas_n (mem_cas_n), .mem_ck (mem_ck), @@ -380038,14 +379512,14 @@ module multimedia_video_processor .\I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N538 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/_N538_rnmt ), .\I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N538 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/_N538_rnmt ), .\I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N538 (\u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/_N538_rnmt ), - .N241_0 (N241_0), - ._N18115 (_N18115), + .N242_0 (N242_0), .axi_rst (axi_rst), - .ddr_clk (zoom_clk), + .ddr_clk (ddr_clk), .ddr_rst (ddr_rst), .rd0_addr_start_valid (rd0_ddr_valid), .rd0_clk (rd3_clk), .rd1_addr_start_valid (rd1_ddr_valid), + .rd1_clk (zoom_clk), .rd3_ddr_addr_valid (rd3_ddr_addr_valid), .\u_axi_rd_connect/N78 (\u_axi_ddr_top/u_axi_rd_connect/N78_rnmt ), .\u_axi_rd_connect/N78_1 (\u_axi_ddr_top/u_axi_rd_connect/N78_1_rnmt ), @@ -380056,12 +379530,12 @@ module multimedia_video_processor .wr1_ddr_sart_addr_valid (wr1_addr_valid), .wr3_data_in_valid (wr3_data_in_valid), .wr3_ddr_sart_addr_valid (wr3_addr_valid)); - // ../../sources/designs/multimedia_video_processor.v:935 + // ../../sources/designs/multimedia_video_processor.v:937 sync_rst u_axi_rst ( .N0 (\u_axi_rst/N0 ), .rst (axi_rst), - .clk (zoom_clk), + .clk (ddr_clk), .init_calib_complete (init_calib_complete), .nt_rstn (nt_rstn), .rstn_5s (rstn_5s)); @@ -380108,11 +379582,11 @@ module multimedia_video_processor .wr1_vs (wr1_vs), .wr3_ddr_done (wr3_ddr_done), .zoom_image_addr_valid (zoom_image_addr_valid)); - // ../../sources/designs/multimedia_video_processor.v:854 + // ../../sources/designs/multimedia_video_processor.v:856 sync_rst_unq18 u_ddr_rst ( .rst (ddr_rst), - .clk (zoom_clk), + .clk (ddr_clk), .rstn (nt_rstn)); // ../../sources/designs/multimedia_video_processor.v:363 @@ -380206,7 +379680,7 @@ module multimedia_video_processor .ddr_data_in_valid (rd3_data_valid), .rotate_en (rotate_vs_out), .rst (rd3_rst)); - // ../../sources/designs/multimedia_video_processor.v:637 + // ../../sources/designs/multimedia_video_processor.v:638 sync_vg u_sync_vg ( .hdmi_image_data (hdmi_image_data), @@ -380221,11 +379695,11 @@ module multimedia_video_processor .vs_out (hdmi_vs_out0), .clk (nt_pix_clk), .rst (sync_vg_100m)); - // ../../sources/designs/multimedia_video_processor.v:741 + // ../../sources/designs/multimedia_video_processor.v:743 sys_pll u_sys_pll ( .clkout0 (rd3_clk), - .clkout1 (zoom_clk), + .clkout1 (ddr_clk), .clkout3 (clk_25m), .clkout4 (clk_10m), .pll_lock (locked), @@ -380244,7 +379718,7 @@ module multimedia_video_processor .wr_clk (zoom_clk), .wr_en (zoom_data_out_valid), .wr_rst (zoom_rst)); - // ../../sources/designs/multimedia_video_processor.v:702 + // ../../sources/designs/multimedia_video_processor.v:704 zoom_image_v1 u_zoom_image ( .data_out (zoom_data_out), @@ -380259,7 +379733,7 @@ module multimedia_video_processor .rst (zoom_rst), .\u_ddr_addr_ctr/u_rd1_addr_ctr/N227_1 (\u_ddr_addr_ctr/u_rd1_addr_ctr/N227_1 ), .zoom_en (zoom_vs_out1)); - // ../../sources/designs/multimedia_video_processor.v:685 + // ../../sources/designs/multimedia_video_processor.v:687 sync_rst_unq24 u_zoom_rst ( .rst (zoom_rst), @@ -380281,7 +379755,7 @@ module multimedia_video_processor .pos_x ({pos_x[10], pos_x[9], pos_x[8], pos_x[7], pos_x[6], pos_x[5], pos_x[4], pos_x[3], pos_x[2], pos_x[1], pos_x[0]}), .pos_y ({pos_y[10], pos_y[9], pos_y[8], pos_y[7], pos_y[6], pos_y[5], pos_y[4], pos_y[3], pos_y[2], pos_y[1], pos_y[0]}), .rgb_in ({1'bx, 1'bx, 1'bx, hdmi_r_out[4], hdmi_r_out[3], hdmi_r_out[2], hdmi_r_out[1], hdmi_r_out[0], 1'bx, 1'bx, hdmi_g_out[5], hdmi_g_out[4], hdmi_g_out[3], hdmi_g_out[2], hdmi_g_out[1], hdmi_g_out[0], 1'bx, 1'bx, 1'bx, hdmi_b_out[4], hdmi_b_out[3], hdmi_b_out[2], hdmi_b_out[1], hdmi_b_out[0]}), - ._N97297 (_N97297), + ._N98118 (_N98118), .de_out (de_osd), .eth_tx_ctl (eth_tx_ctl), .eth_txc (eth_txc), @@ -380298,7 +379772,7 @@ module multimedia_video_processor .\eth_udp_inst/u_udp_transmit_buffer/N4 (sync_vg_100m), .hs_in (hdmi_hs_out1), .vs_in (hdmi_vs_out1)); - // ../../sources/designs/multimedia_video_processor.v:779 + // ../../sources/designs/multimedia_video_processor.v:781 udp_wr_mem udp_wr_mem_inst ( .flags (mem_flags), @@ -380306,7 +379780,7 @@ module multimedia_video_processor .udp_rx_data (udp_rx_pkt_data), .udp_rx_dest_port ({1'bx, 1'bx, 1'bx, 1'bx, 1'bx, udp_rx_pkt_dest_port[10], udp_rx_pkt_dest_port[9], udp_rx_pkt_dest_port[8], 1'bx, 1'bx, udp_rx_pkt_dest_port[5], udp_rx_pkt_dest_port[4], udp_rx_pkt_dest_port[3], 1'bx, udp_rx_pkt_dest_port[1], 1'bx}), .udp_rx_num (udp_rx_pkt_byte_num), - ._N97297 (_N97297), + ._N98118 (_N98118), .clk (gmii_clk), .sync_vg_100m (sync_vg_100m), .udp_rx_start (udp_rx_pkt_start), @@ -380319,7 +379793,7 @@ module multimedia_video_processor \vs_down_delay_cnt[0] ( .Q (vs_down_delay_cnt[0]), .CLK (rd3_clk), - .D (N322[0]), + .D (N323[0]), .R (rd3_rst)); // ../../sources/designs/multimedia_video_processor.v:567 @@ -380329,7 +379803,7 @@ module multimedia_video_processor \vs_down_delay_cnt[1] ( .Q (vs_down_delay_cnt[1]), .CLK (rd3_clk), - .D (N322[1]), + .D (N323[1]), .R (rd3_rst)); // ../../sources/designs/multimedia_video_processor.v:567 @@ -380339,7 +379813,7 @@ module multimedia_video_processor \vs_down_delay_cnt[2] ( .Q (vs_down_delay_cnt[2]), .CLK (rd3_clk), - .D (N322[2]), + .D (N323[2]), .R (rd3_rst)); // ../../sources/designs/multimedia_video_processor.v:567 @@ -380349,7 +379823,7 @@ module multimedia_video_processor \vs_down_delay_cnt[3] ( .Q (vs_down_delay_cnt[3]), .CLK (rd3_clk), - .D (N322[3]), + .D (N323[3]), .R (rd3_rst)); // ../../sources/designs/multimedia_video_processor.v:567 @@ -380359,7 +379833,7 @@ module multimedia_video_processor \vs_down_delay_cnt[4] ( .Q (vs_down_delay_cnt[4]), .CLK (rd3_clk), - .D (N322[4]), + .D (N323[4]), .R (rd3_rst)); // ../../sources/designs/multimedia_video_processor.v:567 @@ -380369,7 +379843,7 @@ module multimedia_video_processor \vs_down_delay_cnt[5] ( .Q (vs_down_delay_cnt[5]), .CLK (rd3_clk), - .D (N322[5]), + .D (N323[5]), .R (rd3_rst)); // ../../sources/designs/multimedia_video_processor.v:567 @@ -380379,7 +379853,7 @@ module multimedia_video_processor \vs_down_delay_cnt[6] ( .Q (vs_down_delay_cnt[6]), .CLK (rd3_clk), - .D (N322[6]), + .D (N323[6]), .R (rd3_rst)); // ../../sources/designs/multimedia_video_processor.v:567 @@ -380389,7 +379863,7 @@ module multimedia_video_processor \vs_down_delay_cnt[7] ( .Q (vs_down_delay_cnt[7]), .CLK (rd3_clk), - .D (N322[7]), + .D (N323[7]), .R (rd3_rst)); // ../../sources/designs/multimedia_video_processor.v:567 @@ -380399,7 +379873,7 @@ module multimedia_video_processor \vs_down_delay_cnt[8] ( .Q (vs_down_delay_cnt[8]), .CLK (rd3_clk), - .D (N322[8]), + .D (N323[8]), .R (rd3_rst)); // ../../sources/designs/multimedia_video_processor.v:567 @@ -380409,7 +379883,7 @@ module multimedia_video_processor \vs_down_delay_cnt[9] ( .Q (vs_down_delay_cnt[9]), .CLK (rd3_clk), - .D (N322[9]), + .D (N323[9]), .R (rd3_rst)); // ../../sources/designs/multimedia_video_processor.v:567 @@ -380419,7 +379893,7 @@ module multimedia_video_processor \vs_down_delay_cnt[10] ( .Q (vs_down_delay_cnt[10]), .CLK (rd3_clk), - .D (N322[10]), + .D (N323[10]), .R (rd3_rst)); // ../../sources/designs/multimedia_video_processor.v:567 @@ -380429,7 +379903,7 @@ module multimedia_video_processor \vs_down_delay_cnt[11] ( .Q (vs_down_delay_cnt[11]), .CLK (rd3_clk), - .D (N322[11]), + .D (N323[11]), .R (rd3_rst)); // ../../sources/designs/multimedia_video_processor.v:567 @@ -380456,7 +379930,7 @@ module multimedia_video_processor \vs_pos_delay_cnt[0] ( .Q (vs_pos_delay_cnt[0]), .CLK (rd3_clk), - .D (N318[0]), + .D (N319[0]), .R (rd3_rst)); // ../../sources/designs/multimedia_video_processor.v:555 @@ -380466,7 +379940,7 @@ module multimedia_video_processor \vs_pos_delay_cnt[1] ( .Q (vs_pos_delay_cnt[1]), .CLK (rd3_clk), - .D (N318[1]), + .D (N319[1]), .R (rd3_rst)); // ../../sources/designs/multimedia_video_processor.v:555 @@ -380476,7 +379950,7 @@ module multimedia_video_processor \vs_pos_delay_cnt[2] ( .Q (vs_pos_delay_cnt[2]), .CLK (rd3_clk), - .D (N318[2]), + .D (N319[2]), .R (rd3_rst)); // ../../sources/designs/multimedia_video_processor.v:555 @@ -380486,7 +379960,7 @@ module multimedia_video_processor \vs_pos_delay_cnt[3] ( .Q (vs_pos_delay_cnt[3]), .CLK (rd3_clk), - .D (N318[3]), + .D (N319[3]), .R (rd3_rst)); // ../../sources/designs/multimedia_video_processor.v:555 @@ -380496,7 +379970,7 @@ module multimedia_video_processor \vs_pos_delay_cnt[4] ( .Q (vs_pos_delay_cnt[4]), .CLK (rd3_clk), - .D (N318[4]), + .D (N319[4]), .R (rd3_rst)); // ../../sources/designs/multimedia_video_processor.v:555 @@ -380506,7 +379980,7 @@ module multimedia_video_processor \vs_pos_delay_cnt[5] ( .Q (vs_pos_delay_cnt[5]), .CLK (rd3_clk), - .D (N318[5]), + .D (N319[5]), .R (rd3_rst)); // ../../sources/designs/multimedia_video_processor.v:555 @@ -380516,7 +379990,7 @@ module multimedia_video_processor \vs_pos_delay_cnt[6] ( .Q (vs_pos_delay_cnt[6]), .CLK (rd3_clk), - .D (N318[6]), + .D (N319[6]), .R (rd3_rst)); // ../../sources/designs/multimedia_video_processor.v:555 @@ -380526,7 +380000,7 @@ module multimedia_video_processor \vs_pos_delay_cnt[7] ( .Q (vs_pos_delay_cnt[7]), .CLK (rd3_clk), - .D (N318[7]), + .D (N319[7]), .R (rd3_rst)); // ../../sources/designs/multimedia_video_processor.v:555 @@ -380536,7 +380010,7 @@ module multimedia_video_processor \vs_pos_delay_cnt[8] ( .Q (vs_pos_delay_cnt[8]), .CLK (rd3_clk), - .D (N318[8]), + .D (N319[8]), .R (rd3_rst)); // ../../sources/designs/multimedia_video_processor.v:555 @@ -380546,7 +380020,7 @@ module multimedia_video_processor \vs_pos_delay_cnt[9] ( .Q (vs_pos_delay_cnt[9]), .CLK (rd3_clk), - .D (N318[9]), + .D (N319[9]), .R (rd3_rst)); // ../../sources/designs/multimedia_video_processor.v:555 @@ -380556,7 +380030,7 @@ module multimedia_video_processor \vs_pos_delay_cnt[10] ( .Q (vs_pos_delay_cnt[10]), .CLK (rd3_clk), - .D (N318[10]), + .D (N319[10]), .R (rd3_rst)); // ../../sources/designs/multimedia_video_processor.v:555 @@ -380566,7 +380040,7 @@ module multimedia_video_processor \vs_pos_delay_cnt[11] ( .Q (vs_pos_delay_cnt[11]), .CLK (rd3_clk), - .D (N318[11]), + .D (N319[11]), .R (rd3_rst)); // ../../sources/designs/multimedia_video_processor.v:555 @@ -380576,19 +380050,19 @@ module multimedia_video_processor wr0_vs_vname ( .Q (wr0_vs), .CLK (rd3_clk), - .D (_N103530)); + .D (_N104342)); // defparam wr0_vs_vname.orig_name = wr0_vs; // ../../sources/designs/multimedia_video_processor.v:578 GTP_LUT5 /* wr0_vs_rs_mux */ #( .INIT(32'b00100010001100100011001000110010)) wr0_vs_rs_mux ( - .Z (_N103530), - .I0 (N298), + .Z (_N104342), + .I0 (N299), .I1 (rd3_rst), .I2 (wr0_vs), - .I3 (_N103743), - .I4 (_N103744)); + .I3 (_N104562), + .I4 (_N104563)); // LUT = (I0&~I1)|(~I1&I2&~I4)|(~I1&I2&~I3) ; GTP_DFF_R /* \zoom_ff0[0] */ #( @@ -380599,7 +380073,7 @@ module multimedia_video_processor .CLK (zoom_clk), .D (param_zoom[0]), .R (zoom_rst)); - // ../../sources/designs/multimedia_video_processor.v:669 + // ../../sources/designs/multimedia_video_processor.v:671 GTP_DFF_R /* \zoom_ff0[1] */ #( .GRS_EN("TRUE"), @@ -380609,7 +380083,7 @@ module multimedia_video_processor .CLK (zoom_clk), .D (param_zoom[1]), .R (zoom_rst)); - // ../../sources/designs/multimedia_video_processor.v:669 + // ../../sources/designs/multimedia_video_processor.v:671 GTP_DFF_R /* \zoom_ff0[2] */ #( .GRS_EN("TRUE"), @@ -380619,7 +380093,7 @@ module multimedia_video_processor .CLK (zoom_clk), .D (param_zoom[2]), .R (zoom_rst)); - // ../../sources/designs/multimedia_video_processor.v:669 + // ../../sources/designs/multimedia_video_processor.v:671 GTP_DFF_R /* \zoom_ff0[3] */ #( .GRS_EN("TRUE"), @@ -380629,7 +380103,7 @@ module multimedia_video_processor .CLK (zoom_clk), .D (param_zoom[3]), .R (zoom_rst)); - // ../../sources/designs/multimedia_video_processor.v:669 + // ../../sources/designs/multimedia_video_processor.v:671 GTP_DFF_R /* \zoom_ff0[4] */ #( .GRS_EN("TRUE"), @@ -380639,7 +380113,7 @@ module multimedia_video_processor .CLK (zoom_clk), .D (param_zoom[4]), .R (zoom_rst)); - // ../../sources/designs/multimedia_video_processor.v:669 + // ../../sources/designs/multimedia_video_processor.v:671 GTP_DFF_R /* \zoom_ff0[5] */ #( .GRS_EN("TRUE"), @@ -380649,7 +380123,7 @@ module multimedia_video_processor .CLK (zoom_clk), .D (param_zoom[5]), .R (zoom_rst)); - // ../../sources/designs/multimedia_video_processor.v:669 + // ../../sources/designs/multimedia_video_processor.v:671 GTP_DFF_R /* \zoom_ff0[6] */ #( .GRS_EN("TRUE"), @@ -380659,7 +380133,7 @@ module multimedia_video_processor .CLK (zoom_clk), .D (param_zoom[6]), .R (zoom_rst)); - // ../../sources/designs/multimedia_video_processor.v:669 + // ../../sources/designs/multimedia_video_processor.v:671 GTP_DFF_S /* \zoom_ff0[7] */ #( .GRS_EN("TRUE"), @@ -380669,7 +380143,7 @@ module multimedia_video_processor .CLK (zoom_clk), .D (param_zoom[7]), .S (zoom_rst)); - // ../../sources/designs/multimedia_video_processor.v:669 + // ../../sources/designs/multimedia_video_processor.v:671 GTP_DFF_R /* \zoom_ff0[8] */ #( .GRS_EN("TRUE"), @@ -380679,7 +380153,7 @@ module multimedia_video_processor .CLK (zoom_clk), .D (param_zoom[8]), .R (zoom_rst)); - // ../../sources/designs/multimedia_video_processor.v:669 + // ../../sources/designs/multimedia_video_processor.v:671 GTP_DFF_R /* \zoom_ff0[9] */ #( .GRS_EN("TRUE"), @@ -380689,7 +380163,7 @@ module multimedia_video_processor .CLK (zoom_clk), .D (param_zoom[9]), .R (zoom_rst)); - // ../../sources/designs/multimedia_video_processor.v:669 + // ../../sources/designs/multimedia_video_processor.v:671 GTP_DFF_R /* \zoom_ff1[0] */ #( .GRS_EN("TRUE"), @@ -380699,7 +380173,7 @@ module multimedia_video_processor .CLK (zoom_clk), .D (zoom_ff0[0]), .R (zoom_rst)); - // ../../sources/designs/multimedia_video_processor.v:669 + // ../../sources/designs/multimedia_video_processor.v:671 GTP_DFF_R /* \zoom_ff1[1] */ #( .GRS_EN("TRUE"), @@ -380709,7 +380183,7 @@ module multimedia_video_processor .CLK (zoom_clk), .D (zoom_ff0[1]), .R (zoom_rst)); - // ../../sources/designs/multimedia_video_processor.v:669 + // ../../sources/designs/multimedia_video_processor.v:671 GTP_DFF_R /* \zoom_ff1[2] */ #( .GRS_EN("TRUE"), @@ -380719,7 +380193,7 @@ module multimedia_video_processor .CLK (zoom_clk), .D (zoom_ff0[2]), .R (zoom_rst)); - // ../../sources/designs/multimedia_video_processor.v:669 + // ../../sources/designs/multimedia_video_processor.v:671 GTP_DFF_R /* \zoom_ff1[3] */ #( .GRS_EN("TRUE"), @@ -380729,7 +380203,7 @@ module multimedia_video_processor .CLK (zoom_clk), .D (zoom_ff0[3]), .R (zoom_rst)); - // ../../sources/designs/multimedia_video_processor.v:669 + // ../../sources/designs/multimedia_video_processor.v:671 GTP_DFF_R /* \zoom_ff1[4] */ #( .GRS_EN("TRUE"), @@ -380739,7 +380213,7 @@ module multimedia_video_processor .CLK (zoom_clk), .D (zoom_ff0[4]), .R (zoom_rst)); - // ../../sources/designs/multimedia_video_processor.v:669 + // ../../sources/designs/multimedia_video_processor.v:671 GTP_DFF_R /* \zoom_ff1[5] */ #( .GRS_EN("TRUE"), @@ -380749,7 +380223,7 @@ module multimedia_video_processor .CLK (zoom_clk), .D (zoom_ff0[5]), .R (zoom_rst)); - // ../../sources/designs/multimedia_video_processor.v:669 + // ../../sources/designs/multimedia_video_processor.v:671 GTP_DFF_R /* \zoom_ff1[6] */ #( .GRS_EN("TRUE"), @@ -380759,7 +380233,7 @@ module multimedia_video_processor .CLK (zoom_clk), .D (zoom_ff0[6]), .R (zoom_rst)); - // ../../sources/designs/multimedia_video_processor.v:669 + // ../../sources/designs/multimedia_video_processor.v:671 GTP_DFF_S /* \zoom_ff1[7] */ #( .GRS_EN("TRUE"), @@ -380769,7 +380243,7 @@ module multimedia_video_processor .CLK (zoom_clk), .D (zoom_ff0[7]), .S (zoom_rst)); - // ../../sources/designs/multimedia_video_processor.v:669 + // ../../sources/designs/multimedia_video_processor.v:671 GTP_DFF_R /* \zoom_ff1[8] */ #( .GRS_EN("TRUE"), @@ -380779,7 +380253,7 @@ module multimedia_video_processor .CLK (zoom_clk), .D (zoom_ff0[8]), .R (zoom_rst)); - // ../../sources/designs/multimedia_video_processor.v:669 + // ../../sources/designs/multimedia_video_processor.v:671 GTP_DFF_R /* \zoom_ff1[9] */ #( .GRS_EN("TRUE"), @@ -380789,7 +380263,7 @@ module multimedia_video_processor .CLK (zoom_clk), .D (zoom_ff0[9]), .R (zoom_rst)); - // ../../sources/designs/multimedia_video_processor.v:669 + // ../../sources/designs/multimedia_video_processor.v:671 GTP_DFF_R /* \zoom_ff2[0] */ #( .GRS_EN("TRUE"), @@ -380799,7 +380273,7 @@ module multimedia_video_processor .CLK (zoom_clk), .D (zoom_ff1[0]), .R (zoom_rst)); - // ../../sources/designs/multimedia_video_processor.v:669 + // ../../sources/designs/multimedia_video_processor.v:671 GTP_DFF_R /* \zoom_ff2[1] */ #( .GRS_EN("TRUE"), @@ -380809,7 +380283,7 @@ module multimedia_video_processor .CLK (zoom_clk), .D (zoom_ff1[1]), .R (zoom_rst)); - // ../../sources/designs/multimedia_video_processor.v:669 + // ../../sources/designs/multimedia_video_processor.v:671 GTP_DFF_R /* \zoom_ff2[2] */ #( .GRS_EN("TRUE"), @@ -380819,7 +380293,7 @@ module multimedia_video_processor .CLK (zoom_clk), .D (zoom_ff1[2]), .R (zoom_rst)); - // ../../sources/designs/multimedia_video_processor.v:669 + // ../../sources/designs/multimedia_video_processor.v:671 GTP_DFF_R /* \zoom_ff2[3] */ #( .GRS_EN("TRUE"), @@ -380829,7 +380303,7 @@ module multimedia_video_processor .CLK (zoom_clk), .D (zoom_ff1[3]), .R (zoom_rst)); - // ../../sources/designs/multimedia_video_processor.v:669 + // ../../sources/designs/multimedia_video_processor.v:671 GTP_DFF_R /* \zoom_ff2[4] */ #( .GRS_EN("TRUE"), @@ -380839,7 +380313,7 @@ module multimedia_video_processor .CLK (zoom_clk), .D (zoom_ff1[4]), .R (zoom_rst)); - // ../../sources/designs/multimedia_video_processor.v:669 + // ../../sources/designs/multimedia_video_processor.v:671 GTP_DFF_R /* \zoom_ff2[5] */ #( .GRS_EN("TRUE"), @@ -380849,7 +380323,7 @@ module multimedia_video_processor .CLK (zoom_clk), .D (zoom_ff1[5]), .R (zoom_rst)); - // ../../sources/designs/multimedia_video_processor.v:669 + // ../../sources/designs/multimedia_video_processor.v:671 GTP_DFF_R /* \zoom_ff2[6] */ #( .GRS_EN("TRUE"), @@ -380859,7 +380333,7 @@ module multimedia_video_processor .CLK (zoom_clk), .D (zoom_ff1[6]), .R (zoom_rst)); - // ../../sources/designs/multimedia_video_processor.v:669 + // ../../sources/designs/multimedia_video_processor.v:671 GTP_DFF_S /* \zoom_ff2[7] */ #( .GRS_EN("TRUE"), @@ -380869,7 +380343,7 @@ module multimedia_video_processor .CLK (zoom_clk), .D (zoom_ff1[7]), .S (zoom_rst)); - // ../../sources/designs/multimedia_video_processor.v:669 + // ../../sources/designs/multimedia_video_processor.v:671 GTP_DFF_R /* \zoom_ff2[8] */ #( .GRS_EN("TRUE"), @@ -380879,7 +380353,7 @@ module multimedia_video_processor .CLK (zoom_clk), .D (zoom_ff1[8]), .R (zoom_rst)); - // ../../sources/designs/multimedia_video_processor.v:669 + // ../../sources/designs/multimedia_video_processor.v:671 GTP_DFF_R /* \zoom_ff2[9] */ #( .GRS_EN("TRUE"), @@ -380889,7 +380363,7 @@ module multimedia_video_processor .CLK (zoom_clk), .D (zoom_ff1[9]), .R (zoom_rst)); - // ../../sources/designs/multimedia_video_processor.v:669 + // ../../sources/designs/multimedia_video_processor.v:671 GTP_DFF /* zoom_fifo_full */ #( .GRS_EN("TRUE"), @@ -380897,9 +380371,9 @@ module multimedia_video_processor zoom_fifo_full_vname ( .Q (zoom_fifo_full), .CLK (zoom_clk), - .D (N162)); + .D (N163)); // defparam zoom_fifo_full_vname.orig_name = zoom_fifo_full; - // ../../sources/designs/multimedia_video_processor.v:718 + // ../../sources/designs/multimedia_video_processor.v:720 GTP_DFF /* zoom_vs_out0 */ #( .GRS_EN("TRUE"), @@ -380909,7 +380383,7 @@ module multimedia_video_processor .CLK (zoom_clk), .D (hdmi_vs_out0)); // defparam zoom_vs_out0_vname.orig_name = zoom_vs_out0; - // ../../sources/designs/multimedia_video_processor.v:718 + // ../../sources/designs/multimedia_video_processor.v:720 GTP_DFF /* zoom_vs_out1 */ #( .GRS_EN("TRUE"), @@ -380919,7 +380393,7 @@ module multimedia_video_processor .CLK (zoom_clk), .D (zoom_vs_out0)); // defparam zoom_vs_out1_vname.orig_name = zoom_vs_out1; - // ../../sources/designs/multimedia_video_processor.v:718 + // ../../sources/designs/multimedia_video_processor.v:720 endmodule diff --git a/project/synthesize/snr.db b/project/synthesize/snr.db index 39bed9c..8afdbb5 100644 --- a/project/synthesize/snr.db +++ b/project/synthesize/snr.db @@ -38,8 +38,8 @@ multimedia_video_processor - 13933 - 13710 + 13939 + 13708 88 20.5 98.5 @@ -57,9 +57,9 @@ 1 3 0 - 4656 - 114 - 32 + 4653 + 104 + 31 0 0 0 @@ -107,7 +107,7 @@ adjust_color_wrapper_inst - 1127 + 1128 1096 0 1.5 @@ -141,7 +141,7 @@ 0 adjust_color_inst - 1127 + 1128 1018 0 1.5 @@ -175,7 +175,7 @@ 0 convert_hsv2rgb_inst - 69 + 70 81 0 1.5 @@ -2312,7 +2312,7 @@ image_filiter_inst2 - 946 + 945 856 0 0 @@ -2346,7 +2346,7 @@ 0 hybrid_filter_inst - 727 + 726 621 0 0 @@ -3257,7 +3257,7 @@ ms72xx_ctl - 338 + 337 326 0 0 @@ -3291,7 +3291,7 @@ 0 iic_dri_rx - 82 + 83 61 0 0 @@ -3326,7 +3326,7 @@ iic_dri_tx - 66 + 65 56 0 0 @@ -3396,7 +3396,7 @@ ms7210_ctl - 88 + 87 62 0 0 @@ -3432,7 +3432,7 @@ param_manager_inst - 666 + 672 354 0 0 @@ -3571,7 +3571,7 @@ param_filiter1_mode - 67 + 69 34 0 0 @@ -3711,7 +3711,7 @@ param_modify_H - 51 + 52 22 0 0 @@ -3746,7 +3746,7 @@ param_modify_S - 28 + 30 9 0 0 @@ -3781,7 +3781,7 @@ param_modify_V - 28 + 29 9 0 0 @@ -3816,7 +3816,7 @@ param_offsetX - 56 + 54 25 0 0 @@ -3886,7 +3886,7 @@ param_osd_char_height - 57 + 55 24 0 0 @@ -3921,7 +3921,7 @@ param_osd_char_width - 32 + 33 11 0 0 @@ -4026,7 +4026,7 @@ param_rotate - 47 + 49 21 0 0 @@ -4061,7 +4061,7 @@ param_rotate_A - 33 + 34 10 0 0 @@ -4132,7 +4132,7 @@ u_axi_ddr_top - 5787 + 5796 6000 88 0 @@ -4166,7 +4166,7 @@ 2 I_ipsxb_ddr_top - 4258 + 4267 4123 88 0 @@ -4235,7 +4235,7 @@ u_ddrphy_top - 2602 + 2614 2360 0 0 @@ -4584,7 +4584,7 @@ ddrphy_info - 100 + 103 60 0 0 @@ -4619,7 +4619,7 @@ ddrphy_reset_ctrl - 75 + 84 60 0 0 @@ -4653,7 +4653,7 @@ 0 ddrphy_pll_lock_debounce - 44 + 45 22 0 0 @@ -4793,7 +4793,7 @@ 0 i_dqs_group[0].u_ddrphy_data_slice - 489 + 490 308 0 0 @@ -4932,7 +4932,7 @@ data_slice_wrlvl - 108 + 106 76 0 0 @@ -5002,7 +5002,7 @@ dqsi_rdel_cal - 168 + 171 84 0 0 @@ -5073,7 +5073,7 @@ i_dqs_group[1].u_ddrphy_data_slice - 327 + 331 262 0 0 @@ -5212,7 +5212,7 @@ data_slice_wrlvl - 102 + 105 68 0 0 @@ -5247,7 +5247,7 @@ dqs_rddata_align - 44 + 45 74 0 0 @@ -5353,287 +5353,7 @@ i_dqs_group[2].u_ddrphy_data_slice - 333 - 262 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 11 - 0 - 0 - 0 - 0 - 85 - 2 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - data_slice_dqs_gate_cal - 77 - 61 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 11 - 2 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - dqs_gate_coarse_cal - 30 - 26 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 2 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - gatecal - 47 - 35 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 11 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - data_slice_wrlvl - 107 - 68 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 22 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - dqs_rddata_align - 44 - 74 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - dqsi_rdel_cal - 100 - 59 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 52 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - wdata_path_adj - 5 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - i_dqs_group[3].u_ddrphy_data_slice - 336 + 329 262 0 0 @@ -5772,7 +5492,287 @@ data_slice_wrlvl - 103 + 106 + 68 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 22 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + dqs_rddata_align + 44 + 74 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + dqsi_rdel_cal + 96 + 59 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 52 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + wdata_path_adj + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + i_dqs_group[3].u_ddrphy_data_slice + 335 + 262 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 11 + 0 + 0 + 0 + 0 + 85 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + data_slice_dqs_gate_cal + 78 + 61 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 11 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + dqs_gate_coarse_cal + 30 + 26 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + gatecal + 48 + 35 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 11 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + data_slice_wrlvl + 102 68 0 0 @@ -6055,7 +6055,7 @@ u_ipsxb_ddrc_top - 1654 + 1651 1761 88 0 @@ -6159,7 +6159,7 @@ mcdq_dcd_top - 164 + 163 158 0 0 @@ -6227,7 +6227,7 @@ 0 mcdq_dcd_rowaddr - 17 + 12 8 0 0 @@ -6263,7 +6263,7 @@ mcdq_dcd_sm - 51 + 50 78 0 0 @@ -6299,7 +6299,7 @@ mcdq_dcp_top - 854 + 852 626 82 0 @@ -6333,7 +6333,7 @@ 0 mcdq_dcp_back_ctrl - 545 + 543 406 0 0 @@ -6927,7 +6927,7 @@ TRDA2ACT_LOOP[0].trda2act_timing - 8 + 7 5 0 0 @@ -7487,7 +7487,7 @@ mcdq_timing_rd_pass - 11 + 10 7 0 0 @@ -7697,7 +7697,7 @@ timing_prea_pass - 15 + 16 12 0 0 @@ -7767,7 +7767,7 @@ timing_wr_pass - 9 + 8 5 0 0 @@ -8433,7 +8433,7 @@ 0 mcdq_reg_fifo2 - 95 + 94 71 0 0 @@ -8468,7 +8468,7 @@ u_user_cmd_fifo - 25 + 26 110 0 0 @@ -10607,8 +10607,8 @@ u_ddr_addr_ctr - 280 - 434 + 277 + 432 0 0 0.5 @@ -10626,7 +10626,7 @@ 0 0 0 - 140 + 138 0 0 0 @@ -11237,7 +11237,7 @@ u_ov5640 - 453 + 455 504 0 0 @@ -11257,8 +11257,8 @@ 0 0 185 - 4 - 2 + 3 + 1 0 0 0 @@ -11411,7 +11411,7 @@ coms2_reg_config - 61 + 63 36 0 0 @@ -11431,7 +11431,6 @@ 0 0 23 - 2 1 0 0 @@ -11442,10 +11441,11 @@ 0 0 0 + 0 1 u1 - 29 + 31 9 0 0 @@ -11465,7 +11465,6 @@ 0 0 5 - 2 1 0 0 @@ -11477,6 +11476,7 @@ 0 0 0 + 0 @@ -12532,7 +12532,7 @@ u_zoom_hdmi_fifo - 182 + 172 139 0 0 @@ -12552,7 +12552,7 @@ 0 0 61 - 8 + 0 0 0 0 @@ -12566,7 +12566,7 @@ 0 U_ipml_fifo_zoom_hdmi_fifo - 182 + 172 139 0 0 @@ -12586,7 +12586,7 @@ 0 0 61 - 8 + 0 0 0 0 @@ -12600,7 +12600,7 @@ 0 U_ipml_fifo_ctrl - 165 + 155 138 0 0 @@ -12620,7 +12620,7 @@ 0 0 61 - 8 + 0 0 0 0 @@ -12692,7 +12692,7 @@ 0 0 230 - 1 + 0 0 0 0 @@ -13932,7 +13932,7 @@ udp_osd_inst - 2209 + 2212 1831 0 0 @@ -14035,7 +14035,7 @@ 0 char_buf_reader_inst - 176 + 177 129 0 0 @@ -14070,7 +14070,7 @@ char_pic_rom_inst - 41 + 40 47 0 0 @@ -14316,7 +14316,7 @@ eth_udp_inst - 1818 + 1821 1541 0 0 @@ -14490,7 +14490,7 @@ u_arp - 423 + 422 424 0 0 @@ -14524,7 +14524,7 @@ 0 u_arp_rx - 215 + 214 278 0 0 @@ -14700,7 +14700,7 @@ u_icmp - 927 + 929 628 0 0 @@ -14804,7 +14804,7 @@ u_icmp_tx - 583 + 585 312 0 0 @@ -14840,7 +14840,7 @@ u_udp - 161 + 163 185 0 0 @@ -14874,7 +14874,7 @@ 0 u_udp_rx - 161 + 163 185 0 0 @@ -15122,7 +15122,7 @@ udp_wr_mem_inst - 105 + 106 190 0 0 @@ -15141,7 +15141,7 @@ 0 0 0 - 32 + 31 0 0 0 @@ -16049,7 +16049,7 @@ 50.000MHz 0.000 10.000 - 2826 + 2824 0 clk { u_sys_pll/u_pll_e3/CLKOUT0 } @@ -16061,7 +16061,7 @@ 200.000MHz 0.000 2.500 - 919 + 75 5 clk { u_sys_pll/u_pll_e3/CLKOUT1 } @@ -16181,7 +16181,7 @@ 148.438MHz 0.000 3.368 - 0 + 844 0 clk { U_HDMI_PLL/u_pll_e3/CLKOUT0 } @@ -16281,15 +16281,15 @@ clk_50m - 127.389MHz + 127.372MHz 50.000MHz - 12.150 + 12.149 clk_200m - 205.339MHz + 254.065MHz 200.000MHz - 0.130 + 1.064 clk_25m @@ -16303,11 +16303,17 @@ 10.000MHz 93.453 + + clk_1080p60Hz + 196.323MHz + 148.438MHz + 1.643 + clk_720p60Hz - 126.448MHz + 127.155MHz 74.219MHz - 5.565 + 5.609 clk_20k @@ -16317,9 +16323,9 @@ ddrphy_clkin - 128.403MHz + 130.993MHz 100.000MHz - 2.212 + 2.366 ioclk0 @@ -16578,14 +16584,14 @@ clk_50m YES Timed - 12.150 + 12.149 0.000 0 - 6025 - 0.650 + 6021 + 0.649 0.000 0 - 6025 + 6021 clk_720p60Hz @@ -16609,56 +16615,28 @@ - 370 - - - - 370 - - - eth_rxc - clk_200m - NO - Asynchronous Groups - - - - 10 - - - - 10 - - - clk_50m - clk_200m - YES - Asynchronous Groups - - - - 3 + 368 - 3 + 368 clk_200m clk_200m YES Timed - 0.130 + 1.064 0.000 0 - 3022 + 177 -1.158 -2.316 2 - 3022 + 177 - clk_10m + clk_720p60Hz clk_200m YES Asynchronous Groups @@ -16671,20 +16649,6 @@ 3 - - clk_720p60Hz - clk_200m - YES - Asynchronous Groups - - - - 20 - - - - 20 - ddrphy_clkin clk_200m @@ -16693,11 +16657,11 @@ - 98 + 39 - 98 + 39 clk_50m @@ -16743,31 +16707,101 @@ eth_rxc - clk_720p60Hz + clk_1080p60Hz NO Asynchronous Groups - 87 + 10 - 87 + 10 + + + clk_50m + clk_1080p60Hz + YES + Asynchronous Groups + + + + 3 + + + + 3 + + + clk_10m + clk_1080p60Hz + YES + Asynchronous Groups + + + + 3 + + + + 3 + + + clk_1080p60Hz + clk_1080p60Hz + YES + Timed + 1.643 + 0.000 + 0 + 2845 + 0.656 + 0.000 + 0 + 2845 - clk_200m clk_720p60Hz + clk_1080p60Hz YES Asynchronous Groups - 16 + 17 - 16 + 17 + + + ddrphy_clkin + clk_1080p60Hz + YES + Asynchronous Groups + + + + 59 + + + + 59 + + + eth_rxc + clk_720p60Hz + NO + Asynchronous Groups + + + + 87 + + + + 87 clk_10m @@ -16783,12 +16817,26 @@ 3 + + clk_1080p60Hz + clk_720p60Hz + YES + Asynchronous Groups + + + + 16 + + + + 16 + clk_720p60Hz clk_720p60Hz YES Timed - 5.565 + 5.609 0.000 0 3885 @@ -16875,18 +16923,32 @@ - 1868 + 1841 + + + + 1841 + + + clk_1080p60Hz + ddrphy_clkin + YES + Asynchronous Groups + + + + 27 - 1868 + 27 ddrphy_clkin ddrphy_clkin YES Timed - 2.212 + 2.366 0.000 0 12386 @@ -17037,26313 +17099,26307 @@ u_sys_pll/u_pll_e3/CLKIN1 (2.302, 2.302, 2.403, 2.403) - clk_50m (50.00MHZ) (drive 2826 loads) + clk_50m (50.00MHZ) (drive 2824 loads) u_sys_pll/u_pll_e3/CLKOUT0 (2.396, 2.396, 2.495, 2.495) rd3_clk (net) - camera_vs_ff0/CLK (5.526, 5.526, 5.625, 5.625) - - - camera_vs_ff1/CLK (5.526, 5.526, 5.625, 5.625) + camera_vs_ff0/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/m_result_data[0]/CLK (5.526, 5.526, 5.625, 5.625) + camera_vs_ff1/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/m_result_data[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/m_result_data[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/m_result_data[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/m_result_data[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/m_result_data[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/m_result_data[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/m_result_data[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/m_result_data[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][0][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/m_result_data[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][0][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][0][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][0][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][0][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][0][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][0][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][0][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][0][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][1][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][0][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][1][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][1][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][1][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][1][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][1][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][1][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][1][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][1][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][2][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][1][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][2][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][2][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][2][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][2][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][2][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][2][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][2][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][2][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][0][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][2][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][0][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][0][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][0][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][0][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][0][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][0][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][0][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][0][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][1][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][0][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][1][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][1][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][1][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][1][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][1][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][1][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][1][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][1][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][2][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][1][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][2][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][2][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][2][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][2][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][2][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][2][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][2][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][2][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][0][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][2][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][0][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][0][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][0][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][0][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][0][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][0][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][0][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][0][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][1][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][0][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][1][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][1][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][1][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][1][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][1][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][1][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][1][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][1][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][2][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][1][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][2][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][2][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][2][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][2][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][2][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][2][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][2][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][2][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[2][2][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum1x4[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum1x4[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum1x4[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum1x4[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum1x4[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum1x4[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum1x4[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum1x4[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum1x4[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x1[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum1x4[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x1[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x1[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x1[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x1[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x1[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x1[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x1[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x1[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x1[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x1[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x2[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x1[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x2[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x2[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x2[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x2[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x2[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x2[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x2[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x2[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x2[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x2[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x2[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x2[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum8[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x2[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum8[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum8[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum8[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum8[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum8[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum8[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum8[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum8[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum8[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum8[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum8[7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum8[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum8[8]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum8[7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/m_result_data[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum8[8]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/m_result_data[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/m_result_data[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/m_result_data[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/m_result_data[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/m_result_data[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/m_result_data[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/m_result_data[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/m_result_data[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/m_result_data[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/m_result_data[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][0][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/m_result_data[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][0][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][0][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][0][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][0][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][0][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][0][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][0][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][0][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][0][5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][0][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][1][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][0][5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][1][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][1][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][1][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][1][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][1][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][1][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][1][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][1][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][1][5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][1][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][2][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][1][5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][2][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][2][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][2][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][2][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][2][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][2][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][2][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][2][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][2][5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][2][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][0][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][2][5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][0][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][0][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][0][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][0][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][0][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][0][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][0][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][0][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][0][5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][0][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][1][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][0][5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][1][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][1][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][1][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][1][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][1][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][1][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][1][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][1][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][1][5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][1][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][2][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][1][5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][2][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][2][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][2][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][2][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][2][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][2][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][2][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][2][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][2][5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][2][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][0][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[1][2][5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][0][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][0][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][0][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][0][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][0][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][0][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][0][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][0][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][0][5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][0][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][1][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][0][5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][1][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][1][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][1][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][1][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][1][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][1][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][1][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][1][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][1][5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][1][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][2][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][1][5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][2][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][2][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][2][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][2][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][2][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][2][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][2][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][2][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][2][5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][2][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][2][5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[8]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum1x4[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[8]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum1x4[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum1x4[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum1x4[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum1x4[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum1x4[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum1x4[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum1x4[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum1x4[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum1x4[7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum1x4[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x1[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum1x4[7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x1[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x1[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x1[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x1[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x1[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x1[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x1[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x1[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x1[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x1[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x1[7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x1[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x2[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x1[7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x2[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x2[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x2[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x2[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x2[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x2[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x2[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x2[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x2[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x2[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x2[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x2[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x2[7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x2[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum8[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x2[7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum8[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum8[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum8[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum8[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum8[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum8[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum8[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum8[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum8[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum8[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum8[7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum8[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum8[8]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum8[7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum8[9]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum8[8]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/m_result_data[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum8[9]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/m_result_data[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/m_result_data[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/m_result_data[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/m_result_data[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/m_result_data[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/m_result_data[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/m_result_data[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/m_result_data[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][0][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/m_result_data[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][0][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][0][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][0][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][0][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][0][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][0][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][0][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][0][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][1][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][0][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][1][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][1][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][1][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][1][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][1][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][1][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][1][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][1][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][2][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][1][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][2][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][2][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][2][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][2][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][2][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][2][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][2][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][2][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][0][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][2][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][0][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][0][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][0][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][0][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][0][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][0][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][0][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][0][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][1][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][0][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][1][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][1][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][1][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][1][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][1][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][1][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][1][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][1][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][2][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][1][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][2][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][2][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][2][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][2][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][2][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][2][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][2][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][2][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][0][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][2][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][0][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][0][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][0][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][0][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][0][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][0][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][0][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][0][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][1][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][0][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][1][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][1][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][1][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][1][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][1][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][1][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][1][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][1][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][2][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][1][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][2][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][2][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][2][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][2][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][2][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][2][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][2][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][2][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/product4x2[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[2][2][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/product4x2[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/product4x2[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/product4x2[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/product4x2[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/product4x2[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/product4x2[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/product4x2[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/product4x2[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/product4x2[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/product4x2[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/product4x2[7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/product4x2[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum1x4[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/product4x2[7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum1x4[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum1x4[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum1x4[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum1x4[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum1x4[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum1x4[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum1x4[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum1x4[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x1[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum1x4[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x1[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x1[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x1[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x1[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x1[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x1[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x1[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x1[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x1[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x1[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x2[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x1[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x2[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x2[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x2[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x2[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x2[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x2[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x2[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x2[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x2[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x2[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x2[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x2[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum8[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x2[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum8[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum8[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum8[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum8[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum8[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum8[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum8[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum8[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum8[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum8[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum8[7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum8[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum8[8]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum8[7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/m_result_valid/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum8[8]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/m_result_valid/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/max[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/max[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/max[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/max[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/max[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/max[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/max[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/max[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/max[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_max[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/max[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_max[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_max[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_max[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_max[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_max[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_max[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_max[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_max[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_min[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_max[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_min[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_min[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_min[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_min[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_min[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_min[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_min[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_min[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/med[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/max_of_vector_min[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/med[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/med[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/med[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/med[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/med[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/med[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/med[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/med[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/med_of_vector_med[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/med[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/med_of_vector_med[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/med_of_vector_med[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/med_of_vector_med[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/med_of_vector_med[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/med_of_vector_med[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/med_of_vector_med[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/med_of_vector_med[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/med_of_vector_med[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/min[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/med_of_vector_med[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/min[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/min[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/min[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/min[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/min[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/min[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/min[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/min[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_max[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/min[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_max[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_max[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_max[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_max[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_max[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_max[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_max[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_max[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_min[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_max[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_min[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_min[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_min[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_min[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_min[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_min[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_min[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_min[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_b/min_of_vector_min[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_max[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_max[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_max[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_max[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_max[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_max[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_max[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_max[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_max[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_max[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_max[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_min[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_max[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_min[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_min[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_min[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_min[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_min[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_min[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_min[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_min[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_min[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_min[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/med[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/max_of_vector_min[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/med[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/med[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/med[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/med[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/med[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/med[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/med[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/med[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/med[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/med[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/med_of_vector_med[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/med[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/med_of_vector_med[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/med_of_vector_med[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/med_of_vector_med[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/med_of_vector_med[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/med_of_vector_med[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/med_of_vector_med[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/med_of_vector_med[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/med_of_vector_med[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/med_of_vector_med[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/med_of_vector_med[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/med_of_vector_med[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_max[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_max[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_max[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_max[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_max[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_max[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_max[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_max[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_max[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_max[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_max[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_min[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_max[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_min[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_min[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_min[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_min[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_min[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_min[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_min[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_min[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_min[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_min[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/max[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_g/min_of_vector_min[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/max[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/max[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/max[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/max[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/max[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/max[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/max[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/max[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/max[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/max[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/max[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/max[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/max[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/max[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/max[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/max[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/max[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/max[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/max[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/max[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/max[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/max[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/max[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/max[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/max[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/max[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/max[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/max[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/max[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/max[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/max[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/max[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/max[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/max[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/max[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/max[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/max[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/max[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/max_of_vector_max[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/max[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/max_of_vector_max[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/max_of_vector_max[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/max_of_vector_max[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/max_of_vector_max[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/max_of_vector_max[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/max_of_vector_max[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/max_of_vector_max[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/max_of_vector_max[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/max_of_vector_min[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/max_of_vector_max[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/max_of_vector_min[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/max_of_vector_min[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/max_of_vector_min[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/max_of_vector_min[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/max_of_vector_min[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/max_of_vector_min[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/max_of_vector_min[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/max_of_vector_min[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/med[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/max_of_vector_min[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/med[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/med[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/med[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/med[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/med[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/med[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/med[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/med[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/med_of_vector_med[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/med[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/med_of_vector_med[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/med_of_vector_med[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/med_of_vector_med[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/med_of_vector_med[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/med_of_vector_med[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/med_of_vector_med[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/med_of_vector_med[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/med_of_vector_med[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/min[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/med_of_vector_med[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/min[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/min[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/min[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/min[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/min[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/min[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/min[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/min[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/min_of_vector_max[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/min[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/min_of_vector_max[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/min_of_vector_max[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/min_of_vector_max[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/min_of_vector_max[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/min_of_vector_max[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/min_of_vector_max[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/min_of_vector_max[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/min_of_vector_max[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/min_of_vector_min[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/min_of_vector_max[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/min_of_vector_min[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/min_of_vector_min[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/min_of_vector_min[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/min_of_vector_min[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/min_of_vector_min[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/min_of_vector_min[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/median_finder9_r/min_of_vector_min[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/min_of_vector_min[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/median_finder9_r/min_of_vector_min[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[8]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[9]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[8]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[10]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[9]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[11]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[10]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[12]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[11]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[13]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[12]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[14]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[13]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[15]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[14]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[16]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[15]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[17]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[16]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[18]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[17]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[19]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[18]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[20]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[19]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[21]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[20]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[22]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[21]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[23]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[22]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[24]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[23]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[25]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[24]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[26]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[25]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[27]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[26]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[28]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[27]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[29]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[28]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[30]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[29]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[31]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[30]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[32]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[31]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[33]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[32]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[34]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[33]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[35]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[34]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[36]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[35]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[37]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[36]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[38]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[37]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[39]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[38]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[40]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[39]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[41]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[40]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[42]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[41]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[43]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[42]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[44]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[43]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[45]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[44]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[46]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[45]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/pixel_ff[47]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[46]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/raw_res_b[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/pixel_ff[47]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/raw_res_b[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/raw_res_b[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/raw_res_b[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/raw_res_b[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/raw_res_b[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/raw_res_b[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/raw_res_b[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/raw_res_b[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/raw_res_g[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/raw_res_b[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/raw_res_g[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/raw_res_g[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/raw_res_g[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/raw_res_g[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/raw_res_g[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/raw_res_g[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/raw_res_g[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/raw_res_g[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/raw_res_g[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/raw_res_g[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/raw_res_r[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/raw_res_g[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/raw_res_r[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/raw_res_r[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/raw_res_r[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/raw_res_r[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/raw_res_r[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/raw_res_r[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/raw_res_r[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/raw_res_r[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/res_b[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/raw_res_r[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/res_b[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/res_b[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/res_b[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/res_b[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/res_b[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/res_b[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/res_b[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/res_b[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/res_g[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/res_b[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/res_g[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/res_g[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/res_g[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/res_g[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/res_g[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/res_g[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/res_g[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/res_g[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/res_g[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/res_g[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/res_r[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/res_g[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/res_r[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/res_r[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/res_r[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/res_r[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/res_r[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/res_r[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/res_r[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/res_r[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/valid_d[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/res_r[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/valid_d[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/valid_d[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/valid_d[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/valid_d[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/hybrid_filter_inst/valid_d[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/valid_d[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/hybrid_filter_inst/valid_d[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[8]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[8]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[10]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[11]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[10]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[11]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[8]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[8]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[10]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[11]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[10]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (6.040, 6.040, 6.139, 6.139) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[11]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKB (6.040, 6.040, 6.139, 6.139) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (6.038, 6.038, 6.137, 6.137) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKA (6.040, 6.040, 6.139, 6.139) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKB (6.038, 6.038, 6.137, 6.137) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKB (6.040, 6.040, 6.139, 6.139) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKA (6.038, 6.038, 6.137, 6.137) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKB (6.038, 6.038, 6.137, 6.137) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[8]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[8]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[10]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[11]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[10]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[11]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[8]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[8]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[10]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[11]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[10]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (6.040, 6.040, 6.139, 6.139) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[11]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKB (6.040, 6.040, 6.139, 6.139) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (6.038, 6.038, 6.137, 6.137) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKA (6.040, 6.040, 6.139, 6.139) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKB (6.038, 6.038, 6.137, 6.137) - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKB (6.040, 6.040, 6.139, 6.139) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKA (6.038, 6.038, 6.137, 6.137) - image_filiter_inst/multiline_buffer_inst/hor_cnt[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKB (6.038, 6.038, 6.137, 6.137) - image_filiter_inst/multiline_buffer_inst/hor_cnt[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/hor_cnt[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/hor_cnt[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/hor_cnt[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/hor_cnt[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/hor_cnt[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/hor_cnt[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/hor_cnt[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/hor_cnt[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/hor_cnt[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/hor_cnt[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/hor_cnt[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/hor_cnt[7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/hor_cnt[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/hor_cnt[8]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/hor_cnt[7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/hor_cnt[9]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/hor_cnt[8]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/hor_cnt[10]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/hor_cnt[9]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/m_pixel_valid/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/hor_cnt[10]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/rst_s1/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/m_pixel_valid/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/srst/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/rst_s1/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/srst/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[8]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[9]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[8]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[10]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[9]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/tail_ver_cnt[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/tail_hor_cnt[10]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/tail_ver_cnt[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/tail_ver_cnt[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/tail_ver_cnt[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/tail_ver_cnt[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/tail_ver_cnt[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/tail_ver_cnt[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/tail_ver_cnt[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/tail_ver_cnt[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/tail_ver_cnt[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/tail_ver_cnt[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/ver_cnt[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/tail_ver_cnt[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/ver_cnt[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/ver_cnt[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/ver_cnt[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/ver_cnt[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/ver_cnt[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/ver_cnt[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/ver_cnt[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/ver_cnt[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/ver_cnt[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/ver_cnt[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/ver_cnt[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/ver_cnt[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/ver_cnt[7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/ver_cnt[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/multiline_buffer_inst/ver_cnt[8]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/ver_cnt[7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][0][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/multiline_buffer_inst/ver_cnt[8]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][0][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][0][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][0][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][0][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][0][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][0][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][0][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][0][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][0][5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][0][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][0][6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][0][5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][0][7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][0][6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][0][8]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][0][7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][0][9]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][0][8]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][0][10]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][0][9]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][0][11]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][0][10]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][0][12]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][0][11]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][0][13]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][0][12]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][0][14]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][0][13]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][0][15]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][0][14]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][1][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][0][15]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][1][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][1][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][1][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][1][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][1][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][1][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][1][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][1][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][1][5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][1][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][1][6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][1][5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][1][7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][1][6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][1][8]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][1][7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][1][9]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][1][8]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][1][10]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][1][9]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][1][11]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][1][10]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][1][12]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][1][11]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][1][13]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][1][12]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][1][14]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][1][13]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][1][15]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][1][14]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][2][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][1][15]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][2][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][2][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][2][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][2][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][2][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][2][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][2][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][2][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][2][5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][2][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][2][6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][2][5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][2][7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][2][6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][2][8]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][2][7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][2][9]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][2][8]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][2][10]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][2][9]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][2][11]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][2][10]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][2][12]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][2][11]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][2][13]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][2][12]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][2][14]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][2][13]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[0][2][15]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][2][14]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][0][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[0][2][15]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][0][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][0][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][0][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][0][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][0][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][0][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][0][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][0][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][0][5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][0][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][0][6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][0][5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][0][7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][0][6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][0][8]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][0][7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][0][9]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][0][8]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][0][10]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][0][9]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][0][11]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][0][10]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][0][12]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][0][11]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][0][13]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][0][12]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][0][14]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][0][13]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][0][15]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][0][14]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][1][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][0][15]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][1][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][1][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][1][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][1][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][1][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][1][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][1][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][1][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][1][5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][1][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][1][6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][1][5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][1][7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][1][6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][1][8]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][1][7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][1][9]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][1][8]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][1][10]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][1][9]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][1][11]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][1][10]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][1][12]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][1][11]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][1][13]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][1][12]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][1][14]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][1][13]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][1][15]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][1][14]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][2][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][1][15]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][2][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][2][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][2][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][2][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][2][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][2][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][2][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][2][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][2][5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][2][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][2][6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][2][5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][2][7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][2][6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][2][8]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][2][7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][2][9]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][2][8]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][2][10]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][2][9]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][2][11]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][2][10]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][2][12]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][2][11]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][2][13]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][2][12]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][2][14]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][2][13]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[1][2][15]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][2][14]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][0][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[1][2][15]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][0][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][0][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][0][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][0][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][0][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][0][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][0][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][0][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][0][5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][0][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][0][6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][0][5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][0][7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][0][6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][0][8]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][0][7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][0][9]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][0][8]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][0][10]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][0][9]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][0][11]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][0][10]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][0][12]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][0][11]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][0][13]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][0][12]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][0][14]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][0][13]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][0][15]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][0][14]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][1][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][0][15]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][1][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][1][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][1][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][1][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][1][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][1][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][1][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][1][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][1][5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][1][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][1][6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][1][5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][1][7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][1][6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][1][8]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][1][7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][1][9]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][1][8]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][1][10]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][1][9]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][1][11]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][1][10]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][1][12]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][1][11]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][1][13]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][1][12]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][1][14]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][1][13]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][1][15]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][1][14]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][2][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][1][15]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][2][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][2][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][2][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][2][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][2][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][2][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][2][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][2][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][2][5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][2][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][2][6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][2][5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][2][7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][2][6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][2][8]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][2][7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][2][9]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][2][8]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][2][10]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][2][9]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][2][11]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][2][10]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][2][12]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][2][11]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][2][13]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][2][12]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][2][14]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][2][13]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/mat[2][2][15]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][2][14]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst/vector_to_matrix_inst/valid_d/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/mat[2][2][15]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/m_result_data[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst/vector_to_matrix_inst/valid_d/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/m_result_data[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/m_result_data[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/m_result_data[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/m_result_data[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/m_result_data[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/m_result_data[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/m_result_data[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/m_result_data[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][0][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/m_result_data[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][0][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][0][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][0][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][0][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][0][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][0][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][0][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][0][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][1][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][0][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][1][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][1][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][1][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][1][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][1][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][1][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][1][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][1][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][2][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][1][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][2][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][2][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][2][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][2][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][2][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][2][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][2][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][2][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][0][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][2][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][0][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][0][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][0][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][0][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][0][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][0][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][0][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][0][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][1][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][0][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][1][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][1][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][1][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][1][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][1][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][1][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][1][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][1][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][2][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][1][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][2][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][2][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][2][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][2][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][2][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][2][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][2][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][2][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][0][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][2][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][0][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][0][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][0][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][0][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][0][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][0][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][0][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][0][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][1][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][0][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][1][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][1][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][1][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][1][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][1][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][1][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][1][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][1][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][2][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][1][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][2][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][2][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][2][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][2][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][2][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][2][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][2][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][2][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][2][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum1x4[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum1x4[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum1x4[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum1x4[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum1x4[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum1x4[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum1x4[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum1x4[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum1x4[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x1[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum1x4[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x1[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x1[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x1[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x1[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x1[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x1[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x1[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x1[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x1[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x1[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x2[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x1[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x2[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x2[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x2[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x2[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x2[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x2[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x2[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x2[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x2[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x2[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x2[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x2[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum8[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x2[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum8[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum8[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum8[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum8[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum8[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum8[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum8[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum8[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum8[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum8[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum8[7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum8[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum8[8]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum8[7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/m_result_data[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum8[8]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/m_result_data[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/m_result_data[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/m_result_data[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/m_result_data[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/m_result_data[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/m_result_data[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/m_result_data[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/m_result_data[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/m_result_data[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/m_result_data[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][0][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/m_result_data[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][0][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][0][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][0][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][0][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][0][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][0][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][0][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][0][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][0][5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][0][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][1][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][0][5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][1][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][1][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][1][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][1][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][1][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][1][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][1][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][1][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][1][5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][1][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][2][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][1][5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][2][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][2][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][2][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][2][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][2][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][2][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][2][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][2][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][2][5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][2][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][0][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][2][5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][0][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][0][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][0][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][0][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][0][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][0][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][0][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][0][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][0][5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][0][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][1][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][0][5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][1][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][1][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][1][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][1][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][1][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][1][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][1][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][1][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][1][5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][1][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][2][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][1][5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][2][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][2][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][2][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][2][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][2][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][2][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][2][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][2][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][2][5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][2][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][0][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][2][5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][0][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][0][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][0][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][0][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][0][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][0][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][0][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][0][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][0][5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][0][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][1][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][0][5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][1][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][1][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][1][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][1][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][1][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][1][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][1][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][1][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][1][5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][1][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][2][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][1][5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][2][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][2][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][2][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][2][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][2][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][2][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][2][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][2][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][2][5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][2][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][2][5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[8]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum1x4[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[8]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum1x4[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum1x4[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum1x4[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum1x4[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum1x4[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum1x4[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum1x4[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum1x4[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum1x4[7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum1x4[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x1[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum1x4[7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x1[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x1[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x1[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x1[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x1[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x1[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x1[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x1[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x1[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x1[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x1[7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x1[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x2[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x1[7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x2[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x2[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x2[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x2[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x2[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x2[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x2[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x2[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x2[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x2[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x2[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x2[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x2[7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x2[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum8[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x2[7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum8[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum8[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum8[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum8[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum8[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum8[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum8[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum8[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum8[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum8[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum8[7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum8[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum8[8]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum8[7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum8[9]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum8[8]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/m_result_data[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum8[9]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/m_result_data[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/m_result_data[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/m_result_data[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/m_result_data[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/m_result_data[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/m_result_data[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/m_result_data[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/m_result_data[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][0][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/m_result_data[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][0][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][0][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][0][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][0][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][0][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][0][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][0][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][0][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][1][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][0][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][1][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][1][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][1][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][1][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][1][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][1][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][1][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][1][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][2][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][1][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][2][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][2][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][2][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][2][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][2][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][2][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][2][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][2][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][0][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][2][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][0][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][0][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][0][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][0][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][0][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][0][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][0][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][0][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][1][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][0][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][1][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][1][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][1][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][1][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][1][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][1][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][1][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][1][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][2][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][1][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][2][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][2][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][2][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][2][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][2][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][2][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][2][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][2][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][0][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][2][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][0][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][0][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][0][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][0][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][0][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][0][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][0][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][0][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][1][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][0][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][1][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][1][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][1][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][1][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][1][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][1][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][1][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][1][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][2][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][1][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][2][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][2][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][2][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][2][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][2][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][2][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][2][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][2][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/product4x2[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][2][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/product4x2[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/product4x2[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/product4x2[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/product4x2[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/product4x2[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/product4x2[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/product4x2[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/product4x2[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/product4x2[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/product4x2[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/product4x2[7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/product4x2[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum1x4[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/product4x2[7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum1x4[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum1x4[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum1x4[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum1x4[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum1x4[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum1x4[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum1x4[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum1x4[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum4x1[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum1x4[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum4x1[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum4x1[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum4x1[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum4x1[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum4x1[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum4x1[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum4x1[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum4x1[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum4x1[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum4x1[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum4x2[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum4x1[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum4x2[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum4x2[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum4x2[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum4x2[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum4x2[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum4x2[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum4x2[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum4x2[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum4x2[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum4x2[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum4x2[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum4x2[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum8[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum4x2[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum8[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum8[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum8[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum8[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum8[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum8[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum8[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum8[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum8[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum8[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum8[7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum8[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum8[8]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum8[7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/m_result_valid/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum8[8]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/m_result_valid/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/max[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/max[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/max[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_max[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_max[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_max[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_max[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_max[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_max[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_max[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_max[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_max[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_min[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_max[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_min[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_min[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_min[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_min[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_min[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_min[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_min[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_min[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/max_of_vector_min[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med_of_vector_med[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med_of_vector_med[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med_of_vector_med[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med_of_vector_med[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med_of_vector_med[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med_of_vector_med[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med_of_vector_med[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med_of_vector_med[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med_of_vector_med[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/med_of_vector_med[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_max[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_max[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_max[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_max[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_max[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_max[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_max[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_max[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_max[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_min[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_max[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_min[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_min[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_min[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_min[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_min[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_min[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_min[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_min[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_b/min_of_vector_min[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/max[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/med[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[0].sort_3_inst/min[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/max[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/med[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[1].sort_3_inst/min[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/max[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/med[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/g_sort_for_per_three_reg[2].sort_3_inst/min[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_max[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_max[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_max[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_max[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_max[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_max[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_max[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_max[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_max[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_max[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_max[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_min[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_max[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_min[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_min[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_min[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_min[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_min[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_min[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_min[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_min[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_min[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_min[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/max_of_vector_min[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med_of_vector_med[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med_of_vector_med[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med_of_vector_med[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med_of_vector_med[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med_of_vector_med[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med_of_vector_med[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med_of_vector_med[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med_of_vector_med[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med_of_vector_med[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med_of_vector_med[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med_of_vector_med[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/med_of_vector_med[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_max[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_max[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_max[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_max[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_max[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_max[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_max[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_max[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_max[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_max[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_max[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_min[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_max[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_min[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_min[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_min[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_min[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_min[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_min[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_min[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_min[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_min[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_min[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/max[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_g/min_of_vector_min[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/max[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/max[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/max[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/max[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/max[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/max[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/max[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/max[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/max[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/med[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/max[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[0].sort_3_inst/min[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/max[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/max[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/max[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/max[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/max[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/max[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/max[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/max[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/max[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/med[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/max[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[1].sort_3_inst/min[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/max[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/max[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/max[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/max[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/max[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/max[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/max[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/max[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/max[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/med[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/g_sort_for_per_three_reg[2].sort_3_inst/min[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max_of_vector_max[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max_of_vector_max[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max_of_vector_max[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max_of_vector_max[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max_of_vector_max[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max_of_vector_max[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max_of_vector_max[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max_of_vector_max[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max_of_vector_max[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max_of_vector_min[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max_of_vector_max[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max_of_vector_min[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max_of_vector_min[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max_of_vector_min[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max_of_vector_min[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max_of_vector_min[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max_of_vector_min[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max_of_vector_min[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max_of_vector_min[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/med[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/max_of_vector_min[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/med[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/med[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/med[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/med[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/med[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/med[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/med[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/med[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/med_of_vector_med[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/med[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/med_of_vector_med[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/med_of_vector_med[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/med_of_vector_med[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/med_of_vector_med[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/med_of_vector_med[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/med_of_vector_med[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/med_of_vector_med[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/med_of_vector_med[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/med_of_vector_med[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min_of_vector_max[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min_of_vector_max[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min_of_vector_max[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min_of_vector_max[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min_of_vector_max[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min_of_vector_max[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min_of_vector_max[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min_of_vector_max[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min_of_vector_max[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min_of_vector_min[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min_of_vector_max[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min_of_vector_min[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min_of_vector_min[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min_of_vector_min[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min_of_vector_min[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min_of_vector_min[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min_of_vector_min[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min_of_vector_min[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min_of_vector_min[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/median_finder9_r/min_of_vector_min[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[8]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[9]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[8]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[10]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[9]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[11]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[10]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[12]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[11]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[13]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[12]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[14]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[13]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[15]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[14]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[16]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[15]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[17]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[16]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[18]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[17]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[19]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[18]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[20]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[19]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[21]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[20]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[22]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[21]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[23]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[22]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[24]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[23]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[25]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[24]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[26]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[25]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[27]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[26]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[28]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[27]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[29]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[28]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[30]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[29]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[31]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[30]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[32]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[31]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[33]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[32]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[34]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[33]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[35]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[34]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[36]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[35]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[37]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[36]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[38]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[37]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[39]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[38]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[40]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[39]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[41]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[40]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[42]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[41]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[43]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[42]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[44]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[43]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[45]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[44]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[46]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[45]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/pixel_ff[47]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[46]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/raw_res_b[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/pixel_ff[47]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/raw_res_b[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/raw_res_b[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/raw_res_b[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/raw_res_b[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/raw_res_b[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/raw_res_b[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/raw_res_b[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/raw_res_b[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/raw_res_g[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/raw_res_b[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/raw_res_g[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/raw_res_g[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/raw_res_g[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/raw_res_g[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/raw_res_g[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/raw_res_g[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/raw_res_g[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/raw_res_g[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/raw_res_g[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/raw_res_g[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/raw_res_r[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/raw_res_g[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/raw_res_r[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/raw_res_r[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/raw_res_r[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/raw_res_r[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/raw_res_r[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/raw_res_r[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/raw_res_r[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/raw_res_r[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/res_b[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/raw_res_r[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/res_b[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/res_b[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/res_b[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/res_b[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/res_b[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/res_b[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/res_b[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/res_b[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/res_g[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/res_b[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/res_g[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/res_g[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/res_g[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/res_g[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/res_g[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/res_g[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/res_g[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/res_g[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/res_g[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/res_g[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/res_r[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/res_g[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/res_r[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/res_r[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/res_r[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/res_r[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/res_r[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/res_r[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/res_r[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/res_r[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/valid_d[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/res_r[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/valid_d[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/valid_d[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/valid_d[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/valid_d[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/hybrid_filter_inst/valid_d[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/valid_d[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/hybrid_filter_inst/valid_d[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[8]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[8]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[10]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[11]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[10]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[11]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[8]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[8]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[10]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[11]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[10]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (6.040, 6.040, 6.139, 6.139) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[11]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKB (6.040, 6.040, 6.139, 6.139) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (6.038, 6.038, 6.137, 6.137) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKA (6.040, 6.040, 6.139, 6.139) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKB (6.038, 6.038, 6.137, 6.137) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKB (6.040, 6.040, 6.139, 6.139) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKA (6.038, 6.038, 6.137, 6.137) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKB (6.038, 6.038, 6.137, 6.137) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[8]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[8]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[10]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[11]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[10]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.rbin[11]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[8]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[8]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[10]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[11]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[10]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (6.040, 6.040, 6.139, 6.139) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.wbin[11]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKB (6.040, 6.040, 6.139, 6.139) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (6.038, 6.038, 6.137, 6.137) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKA (6.040, 6.040, 6.139, 6.139) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKB (6.038, 6.038, 6.137, 6.137) - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKB (6.040, 6.040, 6.139, 6.139) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKA (6.038, 6.038, 6.137, 6.137) - image_filiter_inst2/multiline_buffer_inst/hor_cnt[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKB (6.038, 6.038, 6.137, 6.137) - image_filiter_inst2/multiline_buffer_inst/hor_cnt[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/hor_cnt[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/hor_cnt[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/hor_cnt[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/hor_cnt[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/hor_cnt[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/hor_cnt[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/hor_cnt[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/hor_cnt[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/hor_cnt[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/hor_cnt[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/hor_cnt[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/hor_cnt[7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/hor_cnt[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/hor_cnt[8]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/hor_cnt[7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/hor_cnt[9]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/hor_cnt[8]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/hor_cnt[10]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/hor_cnt[9]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/m_pixel_valid/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/hor_cnt[10]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/m_pixel_valid/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[8]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[9]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[8]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[10]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[9]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/tail_hor_cnt[10]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/ver_cnt[0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/ver_cnt[1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/ver_cnt[0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/ver_cnt[2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/ver_cnt[1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/ver_cnt[3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/ver_cnt[2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/ver_cnt[4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/ver_cnt[3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/ver_cnt[5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/ver_cnt[4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/ver_cnt[6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/ver_cnt[5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/ver_cnt[7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/ver_cnt[6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/multiline_buffer_inst/ver_cnt[8]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/ver_cnt[7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][0][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/multiline_buffer_inst/ver_cnt[8]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][0][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][0][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][0][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][0][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][0][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][0][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][0][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][0][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][0][5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][0][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][0][6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][0][5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][0][7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][0][6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][0][8]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][0][7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][0][9]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][0][8]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][0][10]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][0][9]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][0][11]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][0][10]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][0][12]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][0][11]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][0][13]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][0][12]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][0][14]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][0][13]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][0][15]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][0][14]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][1][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][0][15]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][1][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][1][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][1][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][1][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][1][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][1][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][1][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][1][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][1][5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][1][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][1][6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][1][5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][1][7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][1][6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][1][8]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][1][7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][1][9]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][1][8]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][1][10]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][1][9]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][1][11]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][1][10]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][1][12]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][1][11]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][1][13]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][1][12]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][1][14]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][1][13]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][1][15]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][1][14]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][2][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][1][15]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][2][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][2][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][2][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][2][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][2][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][2][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][2][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][2][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][2][5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][2][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][2][6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][2][5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][2][7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][2][6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][2][8]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][2][7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][2][9]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][2][8]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][2][10]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][2][9]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][2][11]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][2][10]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][2][12]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][2][11]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][2][13]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][2][12]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][2][14]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][2][13]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[0][2][15]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][2][14]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][0][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[0][2][15]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][0][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][0][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][0][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][0][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][0][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][0][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][0][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][0][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][0][5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][0][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][0][6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][0][5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][0][7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][0][6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][0][8]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][0][7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][0][9]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][0][8]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][0][10]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][0][9]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][0][11]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][0][10]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][0][12]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][0][11]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][0][13]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][0][12]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][0][14]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][0][13]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][0][15]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][0][14]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][1][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][0][15]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][1][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][1][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][1][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][1][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][1][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][1][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][1][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][1][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][1][5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][1][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][1][6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][1][5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][1][7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][1][6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][1][8]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][1][7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][1][9]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][1][8]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][1][10]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][1][9]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][1][11]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][1][10]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][1][12]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][1][11]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][1][13]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][1][12]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][1][14]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][1][13]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][1][15]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][1][14]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][2][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][1][15]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][2][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][2][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][2][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][2][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][2][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][2][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][2][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][2][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][2][5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][2][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][2][6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][2][5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][2][7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][2][6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][2][8]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][2][7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][2][9]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][2][8]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][2][10]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][2][9]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][2][11]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][2][10]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][2][12]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][2][11]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][2][13]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][2][12]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][2][14]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][2][13]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[1][2][15]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][2][14]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][0][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[1][2][15]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][0][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][0][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][0][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][0][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][0][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][0][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][0][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][0][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][0][5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][0][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][0][6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][0][5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][0][7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][0][6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][0][8]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][0][7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][0][9]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][0][8]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][0][10]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][0][9]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][0][11]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][0][10]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][0][12]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][0][11]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][0][13]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][0][12]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][0][14]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][0][13]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][0][15]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][0][14]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][1][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][0][15]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][1][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][1][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][1][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][1][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][1][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][1][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][1][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][1][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][1][5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][1][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][1][6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][1][5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][1][7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][1][6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][1][8]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][1][7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][1][9]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][1][8]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][1][10]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][1][9]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][1][11]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][1][10]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][1][12]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][1][11]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][1][13]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][1][12]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][1][14]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][1][13]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][1][15]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][1][14]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][2][0]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][1][15]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][2][1]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][2][0]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][2][2]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][2][1]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][2][3]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][2][2]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][2][4]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][2][3]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][2][5]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][2][4]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][2][6]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][2][5]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][2][7]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][2][6]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][2][8]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][2][7]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][2][9]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][2][8]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][2][10]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][2][9]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][2][11]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][2][10]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][2][12]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][2][11]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][2][13]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][2][12]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][2][14]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][2][13]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/mat[2][2][15]/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][2][14]/CLK (5.523, 5.523, 5.622, 5.622) - image_filiter_inst2/vector_to_matrix_inst/valid_d/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/mat[2][2][15]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/rd3_data_valid0/CLK (5.526, 5.526, 5.625, 5.625) + image_filiter_inst2/vector_to_matrix_inst/valid_d/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/rd3_data_valid0/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[11]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[11]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[11]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (6.040, 6.040, 6.139, 6.139) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[11]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKA (6.040, 6.040, 6.139, 6.139) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (6.038, 6.038, 6.137, 6.137) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM18K/CLKA (6.040, 6.040, 6.139, 6.139) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKA (6.038, 6.038, 6.137, 6.137) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[3].U_GTP_DRM18K/CLKA (6.040, 6.040, 6.139, 6.139) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM18K/CLKA (6.038, 6.038, 6.137, 6.137) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[3].U_GTP_DRM18K/CLKA (6.038, 6.038, 6.137, 6.137) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[11]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[11]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[11]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[11]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (6.040, 6.040, 6.139, 6.139) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKA (6.040, 6.040, 6.139, 6.139) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (6.038, 6.038, 6.137, 6.137) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKA (6.038, 6.038, 6.137, 6.137) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (6.040, 6.040, 6.139, 6.139) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKA (6.040, 6.040, 6.139, 6.139) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (6.038, 6.038, 6.137, 6.137) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKA (6.038, 6.038, 6.137, 6.137) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[11]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[11]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[11]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/CLKA (6.040, 6.040, 6.139, 6.139) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/wrptr2[11]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/CLKA (6.038, 6.038, 6.137, 6.137) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/CLKB (6.040, 6.040, 6.139, 6.139) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/rwptr2[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_clk50m_rst/rst/CLK (5.526, 5.526, 5.625, 5.625) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/CLKB (6.038, 6.038, 6.137, 6.137) - u_clk50m_rst/rst0/CLK (5.526, 5.526, 5.625, 5.625) + u_clk50m_rst/rst/CLK (5.523, 5.523, 5.622, 5.622) - u_clk50m_rst/rst1/CLK (5.526, 5.526, 5.625, 5.625) + u_clk50m_rst/rst0/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/clk_cnt[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_clk50m_rst/rst1/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/clk_cnt[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/clk_cnt[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/clk_cnt[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/clk_cnt[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/clk_cnt[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/clk_cnt[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/clk_cnt[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/clk_cnt[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/clk_cnt[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/clk_cnt[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/clk_cnt[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/clk_cnt[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/clk_cnt[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/clk_cnt[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/clk_cnt[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/clk_cnt[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/clk_cnt[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/clk_cnt[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/clk_cnt[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/clk_cnt[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/clk_cnt[11]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/clk_cnt[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/clk_cnt[12]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/clk_cnt[11]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/clk_cnt[13]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/clk_cnt[12]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/clk_cnt[14]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/clk_cnt[13]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/clk_cnt[15]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/clk_cnt[14]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/clk_cnt[16]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/clk_cnt[15]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/clk_cnt[17]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/clk_cnt[16]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/clk_cnt[18]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/clk_cnt[17]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/clk_cnt[19]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/clk_cnt[18]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/clk_cnt[20]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/clk_cnt[19]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/clk_cnt[21]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd0_addr_ctr/image_perimt/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd0_addr_ctr/image_perimt/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd0_addr_ctr/image_perimt0/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd0_addr_ctr/image_perimt0/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd0_addr_ctr/image_perimt1/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd0_addr_ctr/image_perimt1/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd0_sta_reg[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd0_sta_reg[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd0_sta_reg[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd0_sta_reg[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd0_sta_reg[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd0_sta_reg[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[11]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[11]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[12]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[12]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[13]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[13]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[14]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[14]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[15]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[15]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[16]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[16]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[17]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[17]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[18]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[18]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[19]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[19]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[20]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[20]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[21]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[21]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[22]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[22]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[23]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[23]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[24]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[24]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[25]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[25]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[26]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[26]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[27]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[27]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_done0/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_done0/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_done1/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_done1/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_done_rise/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_done_rise/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_valid0/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_valid0/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd0_addr_ctr/rd_done_cnt[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd0_addr_ctr/wr_image_cnt0[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd0_addr_ctr/wr_image_cnt0[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd0_addr_ctr/wr_image_cnt0[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd0_addr_ctr/wr_image_cnt0[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd0_addr_ctr/wr_image_cnt0[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd0_addr_ctr/wr_image_cnt0[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd0_addr_ctr/wr_image_cnt0[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd0_addr_ctr/wr_image_cnt0[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd0_addr_ctr/wr_image_cnt0[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd0_addr_ctr/wr_image_cnt0[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_h[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_h[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_h[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_h[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_h[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_h[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_h[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_h[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_h[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_h[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_h[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_h[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_h[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_h[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_h[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_h[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_h[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_h[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_h[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_h[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_h[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_h[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w0[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/act_w[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr0[21]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr0[21]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr0[22]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr0[22]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr0[23]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr0[23]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr0[24]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr0[24]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr0[25]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr0[25]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr2[12]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr2[12]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr2[21]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr2[21]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr2[22]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr2[22]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr2[23]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr2[23]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr2[24]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr2[24]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr2[25]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr2[25]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr3[12]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr3[12]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr3[21]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr3[21]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr3[22]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr3[22]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr3[23]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr3[23]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr3[24]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr3[24]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr3[25]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr3[25]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_h0[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_h0[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_h0[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_h0[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_h0[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_h0[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_h0[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_h0[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_h0[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_h0[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_h0[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_h0[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_h0[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_h0[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_h0[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_h0[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_h0[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_h0[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_h0[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_h0[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_h0[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_h0[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_h1[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_h1[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_h1[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_h1[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_h1[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_h1[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_h1[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_h1[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_h1[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_h1[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_h1[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_h1[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_h1[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_h1[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_h1[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_h1[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_w0[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_w0[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_w0[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_w0[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_w0[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_w0[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_w0[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_w0[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_w0[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_w0[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_w0[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_w0[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_w0[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_w0[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_w0[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_w0[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_w0[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_w0[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_w0[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_w0[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/image_w0[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/image_w0[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[11]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[11]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[12]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[12]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[13]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[13]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[14]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[14]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[15]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[15]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[16]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[16]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[17]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[17]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[18]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[18]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[19]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[19]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[20]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[20]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[21]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[21]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[22]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[22]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[23]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[23]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[24]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[24]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[25]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[25]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[26]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[26]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[11]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[11]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[12]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[12]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[13]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[13]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[14]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[14]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[15]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[15]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[16]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[16]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[17]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[17]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[18]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[18]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[19]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[19]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[20]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[20]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[21]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[21]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[22]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr0[22]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[11]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[11]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[12]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[12]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[13]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[13]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[14]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[14]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[15]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[15]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[16]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[16]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[17]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[17]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[18]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[18]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[19]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[19]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[20]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[20]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[21]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[21]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[22]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[22]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[23]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/now_image_addr1[23]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/rd_ddr_valid0/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/rd_ddr_valid0/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/rd_ddr_valid1/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/rd_ddr_valid1/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/rd_ddr_valid2/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/rd_ddr_valid2/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/rd_ddr_valid3/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/rd_ddr_valid3/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/rd_ddr_valid4/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/rd_ddr_valid4/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/rd_ddr_valid5/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/rd_ddr_valid5/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/rd_image_cnt[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/rd_image_cnt[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/rd_image_cnt[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/rd_image_cnt[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/rd_image_cnt[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/rd_image_cnt[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/rd_image_cnt[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/rd_image_cnt[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/rd_image_cnt[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/rd_image_cnt[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/rd_vs0/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/rd_vs0/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/rd_vs1/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/rd_vs1/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/rd_vs_rise0/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/rd_vs_rise0/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in1[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in1[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in1[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in1[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in1[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in1[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in1[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in1[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in1[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in1[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in2[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in2[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in2[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in2[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in2[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in2[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in2[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in2[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in2[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in2[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in3[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in3[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in3[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in3[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in3[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in3[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in3[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in3[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in3[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in3[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_vary0/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_vary0/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/wr_image_cnt1[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/wr_image_cnt1[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/wr_image_cnt1[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/wr_image_cnt1[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/wr_image_cnt1[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/wr_image_cnt1[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/wr_image_cnt1[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/wr_image_cnt1[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_rd3_addr_ctr/wr_image_cnt1[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_rd3_addr_ctr/wr_image_cnt1[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr0_addr_ctr/delay_cnt[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr0_addr_ctr/delay_cnt[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr0_addr_ctr/delay_cnt[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr0_addr_ctr/delay_cnt[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr0_addr_ctr/delay_cnt[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr0_addr_ctr/delay_cnt[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr0_addr_ctr/delay_cnt[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr0_addr_ctr/delay_cnt[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr0_addr_ctr/image_fram_cnt0[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr0_addr_ctr/image_fram_cnt0[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr0_addr_ctr/image_fram_cnt0[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr0_addr_ctr/image_fram_cnt0[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr0_addr_ctr/image_fram_cnt0[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr0_addr_ctr/image_fram_cnt0[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr0_addr_ctr/image_fram_cnt0[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr0_addr_ctr/image_fram_cnt0[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr0_addr_ctr/image_fram_cnt0[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr0_addr_ctr/image_fram_cnt0[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr0_addr_ctr/wr_addr_valid0/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr0_addr_ctr/wr_addr_valid0/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr0_addr_ctr/wr_ddr_addr0[19]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr0_addr_ctr/wr_ddr_addr0[19]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr0_addr_ctr/wr_ddr_addr0[20]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr0_addr_ctr/wr_ddr_addr0[20]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr0_addr_ctr/wr_ddr_addr0[21]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr0_addr_ctr/wr_ddr_addr0[21]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr0_addr_ctr/wr_ddr_addr0[22]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr0_addr_ctr/wr_ddr_addr0[22]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr0_addr_ctr/wr_ddr_addr0[23]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr0_addr_ctr/wr_ddr_addr0[23]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr0_addr_ctr/wr_ddr_done0/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr0_addr_ctr/wr_ddr_done0/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr0_addr_ctr/wr_ddr_done1/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr0_addr_ctr/wr_ddr_done1/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr0_addr_ctr/wr_ddr_done2/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr0_addr_ctr/wr_ddr_done2/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr0_addr_ctr/wr_sta_reg[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr0_addr_ctr/wr_sta_reg[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr0_addr_ctr/wr_sta_reg[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr0_addr_ctr/wr_sta_reg[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr0_addr_ctr/wr_sta_reg[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr0_addr_ctr/wr_sta_reg[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr0_addr_ctr/wr_vs0/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr0_addr_ctr/wr_vs0/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr0_addr_ctr/wr_vs1/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr0_addr_ctr/wr_vs1/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr0_addr_ctr/wr_vs2/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr0_addr_ctr/wr_vs2/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr0_addr_ctr/wr_vs_flag/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr0_addr_ctr/wr_vs_flag/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr3_addr_ctr/delay_cnt[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr3_addr_ctr/delay_cnt[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr3_addr_ctr/delay_cnt[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr3_addr_ctr/delay_cnt[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr3_addr_ctr/delay_cnt[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr3_addr_ctr/delay_cnt[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr3_addr_ctr/delay_cnt[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr3_addr_ctr/delay_cnt[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr3_addr_ctr/image_fram_cnt0[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr3_addr_ctr/image_fram_cnt0[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr3_addr_ctr/image_fram_cnt0[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr3_addr_ctr/image_fram_cnt0[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr3_addr_ctr/image_fram_cnt0[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr3_addr_ctr/image_fram_cnt0[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr3_addr_ctr/wr_addr_valid0/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr3_addr_ctr/wr_addr_valid0/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr3_addr_ctr/wr_ddr_addr0[19]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr3_addr_ctr/wr_ddr_addr0[19]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr3_addr_ctr/wr_ddr_addr0[20]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr3_addr_ctr/wr_ddr_addr0[20]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr3_addr_ctr/wr_ddr_addr0[21]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr3_addr_ctr/wr_ddr_addr0[21]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr3_addr_ctr/wr_ddr_done0/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr3_addr_ctr/wr_ddr_done0/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr3_addr_ctr/wr_ddr_done1/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr3_addr_ctr/wr_ddr_done1/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr3_addr_ctr/wr_ddr_done2/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr3_addr_ctr/wr_ddr_done2/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr3_addr_ctr/wr_sta_reg[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr3_addr_ctr/wr_sta_reg[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr3_addr_ctr/wr_sta_reg[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr3_addr_ctr/wr_sta_reg[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr3_addr_ctr/wr_sta_reg[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr3_addr_ctr/wr_sta_reg[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr3_addr_ctr/wr_vs0/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr3_addr_ctr/wr_vs0/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr3_addr_ctr/wr_vs1/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr3_addr_ctr/wr_vs1/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr3_addr_ctr/wr_vs2/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr3_addr_ctr/wr_vs2/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/u_wr3_addr_ctr/wr_vs_out/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/u_wr3_addr_ctr/wr_vs_out/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/vs_15hz/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/vs_15hz/CLK (5.526, 5.526, 5.625, 5.625) + u_ddr_addr_ctr/vs_30hz/CLK (5.523, 5.523, 5.622, 5.622) - u_ddr_addr_ctr/vs_30hz/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/power_on_delay_inst/camera_pwnd_reg/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/power_on_delay_inst/camera_pwnd_reg/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/power_on_delay_inst/camera_rstn_reg/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/power_on_delay_inst/camera_rstn_reg/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/power_on_delay_inst/cnt1[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/power_on_delay_inst/cnt1[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/power_on_delay_inst/cnt1[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/power_on_delay_inst/cnt1[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/power_on_delay_inst/cnt1[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/power_on_delay_inst/cnt1[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/power_on_delay_inst/cnt1[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/power_on_delay_inst/cnt1[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/power_on_delay_inst/cnt1[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/power_on_delay_inst/cnt1[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/power_on_delay_inst/cnt1[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/power_on_delay_inst/cnt1[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/power_on_delay_inst/cnt1[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/power_on_delay_inst/cnt1[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/power_on_delay_inst/cnt1[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/power_on_delay_inst/cnt1[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/power_on_delay_inst/cnt1[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/power_on_delay_inst/cnt1[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/power_on_delay_inst/cnt1[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/power_on_delay_inst/cnt1[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/power_on_delay_inst/cnt1[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/power_on_delay_inst/cnt1[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/power_on_delay_inst/cnt1[11]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/power_on_delay_inst/cnt1[11]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/power_on_delay_inst/cnt1[12]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/power_on_delay_inst/cnt1[12]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/power_on_delay_inst/cnt1[13]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/power_on_delay_inst/cnt1[13]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/power_on_delay_inst/cnt1[14]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/power_on_delay_inst/cnt1[14]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/power_on_delay_inst/cnt1[15]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/power_on_delay_inst/cnt1[15]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/power_on_delay_inst/cnt1[16]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/power_on_delay_inst/cnt1[16]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/power_on_delay_inst/cnt1[17]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/power_on_delay_inst/cnt1[17]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/power_on_delay_inst/cnt1[18]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/power_on_delay_inst/cnt1[18]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/power_on_delay_inst/cnt2[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/power_on_delay_inst/cnt2[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/power_on_delay_inst/cnt2[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/power_on_delay_inst/cnt2[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/power_on_delay_inst/cnt2[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/power_on_delay_inst/cnt2[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/power_on_delay_inst/cnt2[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/power_on_delay_inst/cnt2[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/power_on_delay_inst/cnt2[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/power_on_delay_inst/cnt2[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/power_on_delay_inst/cnt2[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/power_on_delay_inst/cnt2[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/power_on_delay_inst/cnt2[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/power_on_delay_inst/cnt2[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/power_on_delay_inst/cnt2[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/power_on_delay_inst/cnt2[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/power_on_delay_inst/cnt2[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/power_on_delay_inst/cnt2[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/power_on_delay_inst/cnt2[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/power_on_delay_inst/cnt2[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/power_on_delay_inst/cnt2[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/power_on_delay_inst/cnt2[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/power_on_delay_inst/cnt2[11]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/power_on_delay_inst/cnt2[11]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/power_on_delay_inst/cnt2[12]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/power_on_delay_inst/cnt2[12]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/power_on_delay_inst/cnt2[13]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/power_on_delay_inst/cnt2[13]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/power_on_delay_inst/cnt2[14]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/power_on_delay_inst/cnt2[14]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/power_on_delay_inst/cnt2[15]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/power_on_delay_inst/cnt2[15]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/data_out1[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/data_out1[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/data_out1[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/data_out1[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/data_out1[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/data_out1[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/data_out1[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/data_out1[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/data_out1[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/data_out1[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/data_out1[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/data_out1[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/data_out1[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/data_out1[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/data_out1[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/data_out1[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/data_out1[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/data_out1[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/data_out1[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/data_out1[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/data_out1[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/data_out1[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/data_out1[11]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/data_out1[11]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/data_out1[12]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/data_out1[12]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/data_out1[13]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/data_out1[13]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/data_out1[14]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/data_out1[14]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/data_out1[15]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/data_out1[15]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/data_out_valid0/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/data_out_valid0/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/data_out_valid1/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/data_out_valid1/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/data_vs/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/data_vs/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/rd_h[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/rd_h[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/rd_h[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/rd_h[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/rd_h[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/rd_h[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/rd_h[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/rd_h[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/rd_h[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/rd_h[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/rd_h[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/rd_h[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/rd_h[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/rd_h[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/rd_h[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/rd_h[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/rd_h[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/rd_h[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/rd_h[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/rd_h[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/rd_h[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/rd_h[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/rd_sta0[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/rd_sta0[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/rd_sta0[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/rd_sta0[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/rd_sta0[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/rd_sta0[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/rd_sta0[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/rd_sta0[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/rd_sta0[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/rd_sta0[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/rd_sta_reg[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/rd_sta_reg[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/rd_sta_reg[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/rd_sta_reg[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/rd_sta_reg[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/rd_sta_reg[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/rd_sta_reg[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/rd_sta_reg[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/rd_sta_reg[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/rd_sta_reg[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/rd_vs0/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/rd_vs0/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/rd_vs1/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/rd_vs1/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/rd_vs2/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/rd_vs2/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/rd_vs_rise/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/rd_vs_rise/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/rd_w[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/rd_w[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/rd_w[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/rd_w[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/rd_w[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/rd_w[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/rd_w[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/rd_w[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/rd_w[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/rd_w[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/rd_w[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/rd_w[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/rd_w[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/rd_w[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/rd_w[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/rd_w[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/rd_w[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/rd_w[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/rd_w[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/rd_w[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/rd_w[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/rd_w[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKB (6.038, 6.038, 6.137, 6.137) - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKB (6.040, 6.040, 6.139, 6.139) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/rwptr2[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKB (6.038, 6.038, 6.137, 6.137) - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKB (6.040, 6.040, 6.139, 6.139) + u_rotate_image/addr_fifo_valid/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/addr_fifo_valid/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/centerX[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/centerX[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/centerX[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/centerX[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/centerX[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/centerX[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/centerX[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/centerX[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/centerX[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/centerX[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/centerX[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/centerX[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/centerX[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/centerX[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/centerX[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/centerX[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/centerX[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/centerX[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/centerX[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/centerX[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/centerX[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/centerX[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/centerX[11]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/centerX[11]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/centerY[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/centerY[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/centerY[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/centerY[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/centerY[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/centerY[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/centerY[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/centerY[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/centerY[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/centerY[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/centerY[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/centerY[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/centerY[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/centerY[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/centerY[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/centerY[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/centerY[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/centerY[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/centerY[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/centerY[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/centerY[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/centerY[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/centerY[11]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/centerY[11]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/cnt_h[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/cnt_h[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/cnt_h[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/cnt_h[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/cnt_h[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/cnt_h[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/cnt_h[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/cnt_h[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/cnt_h[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/cnt_h[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/cnt_h[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/cnt_h[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/cnt_h[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/cnt_h[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/cnt_h[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/cnt_h[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/cnt_h[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/cnt_h[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/cnt_h[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/cnt_h[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/cnt_h[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/cnt_h[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/cnt_w[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/cnt_w[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/cnt_w[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/cnt_w[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/cnt_w[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/cnt_w[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/cnt_w[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/cnt_w[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/cnt_w[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/cnt_w[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/cnt_w[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/cnt_w[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/cnt_w[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/cnt_w[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/cnt_w[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/cnt_w[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/cnt_w[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/cnt_w[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/cnt_w[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/cnt_w[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/cnt_w[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/cnt_w[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/data_out2[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/data_out2[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/data_out2[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/data_out2[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/data_out2[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/data_out2[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/data_out2[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/data_out2[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/data_out2[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/data_out2[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/data_out2[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/data_out2[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/data_out2[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/data_out2[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/data_out2[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/data_out2[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/data_out2[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/data_out2[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/data_out2[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/data_out2[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/data_out2[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/data_out2[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/data_out2[11]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/data_out2[11]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/data_out2[12]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/data_out2[12]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/data_out2[13]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/data_out2[13]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/data_out2[14]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/data_out2[14]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/data_out2[15]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/data_out2[15]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/data_out_valid1/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/data_out_valid1/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/data_out_valid2/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/data_out_valid2/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/ddr_data_in0[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/ddr_data_in0[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/ddr_data_in0[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/ddr_data_in0[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/ddr_data_in0[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/ddr_data_in0[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/ddr_data_in0[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/ddr_data_in0[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/ddr_data_in0[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/ddr_data_in0[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/ddr_data_in0[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/ddr_data_in0[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/ddr_data_in0[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/ddr_data_in0[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/ddr_data_in0[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/ddr_data_in0[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/ddr_data_in0[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/ddr_data_in0[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/ddr_data_in0[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/ddr_data_in0[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/ddr_data_in0[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/ddr_data_in0[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/ddr_data_in0[11]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/ddr_data_in0[11]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/ddr_data_in0[12]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/ddr_data_in0[12]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/ddr_data_in0[13]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/ddr_data_in0[13]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/ddr_data_in0[14]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/ddr_data_in0[14]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/ddr_data_in0[15]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/ddr_data_in0[15]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/ddr_data_in_valid0/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/ddr_data_in_valid0/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/fifo_data_valid/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/fifo_data_valid/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_blank_valid/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_blank_valid/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add0[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add0[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add0[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add0[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add0[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add0[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add0[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add0[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add0[11]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add0[11]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add0[12]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add0[12]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add0[13]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add0[13]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add0[14]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add0[14]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add0[15]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add0[15]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add0[16]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add0[16]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add0[17]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add0[17]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add0[18]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add0[18]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add0[19]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add0[19]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add0[20]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add0[20]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add0[21]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add0[21]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add0[22]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add0[22]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add0[23]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add0[23]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add0[24]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add0[24]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add0[25]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add0[25]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add1[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add1[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add1[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add1[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add1[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add1[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add1[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add1[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add1[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add1[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add1[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add1[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add1[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add1[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add1[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add1[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add1[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add1[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add1[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add1[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add1[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add1[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add2[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add2[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add2[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add2[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add2[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add2[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add2[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add2[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add2[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add2[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add2[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add2[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add2[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add2[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add2[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add2[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add2[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add2[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add2[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add2[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add2[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add2[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add_addr[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add_addr[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add_addr[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add_addr[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add_addr[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add_addr[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add_addr[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add_addr[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add_addr[11]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add_addr[11]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add_addr[12]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add_addr[12]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add_addr[13]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add_addr[13]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add_addr[14]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add_addr[14]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add_addr[15]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add_addr[15]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add_addr[16]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add_addr[16]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add_addr[17]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add_addr[17]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_add_addr[18]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_add_addr[18]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_h_blank_valid/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_h_blank_valid/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add0[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add0[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add0[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add0[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add0[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add0[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add0[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add0[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add0[11]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add0[11]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add0[12]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add0[12]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add0[13]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add0[13]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add0[14]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add0[14]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add0[15]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add0[15]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add0[16]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add0[16]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add0[17]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add0[17]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add0[18]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add0[18]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add0[19]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add0[19]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add0[20]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add0[20]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add0[21]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add0[21]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add0[22]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add0[22]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add0[23]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add0[23]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add0[24]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add0[24]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add0[25]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add0[25]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add1[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add1[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add1[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add1[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add1[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add1[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add1[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add1[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add1[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add1[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add1[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add1[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add1[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add1[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add1[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add1[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add1[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add1[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add1[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add1[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add1[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add1[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add2[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add2[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add2[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add2[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add2[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add2[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add2[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add2[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add2[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add2[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add2[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add2[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add2[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add2[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add2[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add2[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add2[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add2[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add2[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add2[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add2[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add2[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add_addr[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add_addr[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add_addr[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add_addr[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add_addr[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add_addr[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add_addr[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add_addr[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add_addr[11]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add_addr[11]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add_addr[12]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add_addr[12]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add_addr[13]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add_addr[13]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add_addr[14]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add_addr[14]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add_addr[15]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add_addr[15]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add_addr[16]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add_addr[16]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add_addr[17]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add_addr[17]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_add_addr[18]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_add_addr[18]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_blank_valid/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_blank_valid/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_valid0[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_valid0[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_valid0[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_valid0[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_valid0[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_valid0[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_valid0[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_valid0[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/image_w_valid0[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/image_w_valid0[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/offsetX_ff[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/offsetX_ff[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/offsetX_ff[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/offsetX_ff[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/offsetX_ff[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/offsetX_ff[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/offsetX_ff[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/offsetX_ff[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/offsetX_ff[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/offsetX_ff[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/offsetX_ff[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/offsetX_ff[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/offsetX_ff[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/offsetX_ff[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/offsetX_ff[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/offsetX_ff[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/offsetX_ff[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/offsetX_ff[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/offsetX_ff[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/offsetX_ff[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/offsetX_ff[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/offsetX_ff[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/offsetX_ff[11]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/offsetX_ff[11]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/offsetY_ff[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/offsetY_ff[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/offsetY_ff[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/offsetY_ff[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/offsetY_ff[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/offsetY_ff[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/offsetY_ff[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/offsetY_ff[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/offsetY_ff[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/offsetY_ff[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/offsetY_ff[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/offsetY_ff[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/offsetY_ff[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/offsetY_ff[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/offsetY_ff[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/offsetY_ff[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/offsetY_ff[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/offsetY_ff[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/offsetY_ff[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/offsetY_ff[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/offsetY_ff[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/offsetY_ff[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/offsetY_ff[11]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/offsetY_ff[11]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/rd_addr[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/rd_addr[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/rd_addr[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/rd_addr[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/rd_addr[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/rd_addr[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/rd_addr[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/rd_addr[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/rd_addr[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/rd_addr[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/rd_addr[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/rd_addr[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/rd_addr[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/rd_addr[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/rd_addr[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/rd_addr[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/rd_ddr_addr_valid1/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/rd_ddr_addr_valid1/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/rd_sta_reg[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/rd_sta_reg[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/rd_sta_reg[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/rd_sta_reg[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/rd_sta_reg[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/rd_sta_reg[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/rd_sta_s2/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/rd_sta_s2/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/rotate_sta_reg[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/rotate_sta_reg[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/rotate_sta_reg[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/rotate_sta_reg[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/rotate_sta_reg[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/rotate_sta_reg[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_rotate_mult0/N2/CLK (6.038, 6.038, 6.137, 6.137) - u_rotate_image/u_rotate_mult0/N2/CLK (6.040, 6.040, 6.139, 6.139) + u_rotate_image/u_rotate_mult1/N2/CLK (6.038, 6.038, 6.137, 6.137) - u_rotate_image/u_rotate_mult1/N2/CLK (6.040, 6.040, 6.139, 6.139) + u_rotate_image/u_rotate_mult2/N2/CLK (6.038, 6.038, 6.137, 6.137) - u_rotate_image/u_rotate_mult2/N2/CLK (6.040, 6.040, 6.139, 6.139) + u_rotate_image/u_rotate_mult3/N2/CLK (6.038, 6.038, 6.137, 6.137) - u_rotate_image/u_rotate_mult3/N2/CLK (6.040, 6.040, 6.139, 6.139) + u_rotate_image/u_rotate_mult_zoom0/N2/CLK (6.038, 6.038, 6.137, 6.137) - u_rotate_image/u_rotate_mult_zoom0/N2/CLK (6.040, 6.040, 6.139, 6.139) + u_rotate_image/u_rotate_mult_zoom1/N2/CLK (6.038, 6.038, 6.137, 6.137) - u_rotate_image/u_rotate_mult_zoom1/N2/CLK (6.040, 6.040, 6.139, 6.139) + u_rotate_image/u_rotate_rom/U_ipml_rom_rotate_rom/U_ipml_spram_rotate_rom/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/CLKA (6.038, 6.038, 6.137, 6.137) - u_rotate_image/u_rotate_rom/U_ipml_rom_rotate_rom/U_ipml_spram_rotate_rom/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/CLKA (6.040, 6.040, 6.139, 6.139) + u_rotate_image/u_rotate_rom/U_ipml_rom_rotate_rom/U_ipml_spram_rotate_rom/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/CLKB (6.038, 6.038, 6.137, 6.137) - u_rotate_image/u_rotate_rom/U_ipml_rom_rotate_rom/U_ipml_spram_rotate_rom/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/CLKB (6.040, 6.040, 6.139, 6.139) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[11]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.rbin[11]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[11]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.wbin[11]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[11]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/wr_water_level[11]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/CLKA (6.038, 6.038, 6.137, 6.137) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/CLKA (6.040, 6.040, 6.139, 6.139) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/CLKB (6.038, 6.038, 6.137, 6.137) - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/CLKB (6.040, 6.040, 6.139, 6.139) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.rbin[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.wbin[0]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.wbin[0]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.wbin[2]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.wbin[2]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.wbin[4]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.wbin[4]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.wbin[6]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.wbin[6]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.wbin[8]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.wbin[8]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.wbin[10]/CLK (5.523, 5.523, 5.622, 5.622) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.wbin[10]/CLK (5.526, 5.526, 5.625, 5.625) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (6.038, 6.038, 6.137, 6.137) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (6.040, 6.040, 6.139, 6.139) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKB (6.038, 6.038, 6.137, 6.137) - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKB (6.040, 6.040, 6.139, 6.139) + vs_down_delay_cnt[0]/CLK (5.523, 5.523, 5.622, 5.622) - vs_down_delay_cnt[0]/CLK (5.526, 5.526, 5.625, 5.625) + vs_down_delay_cnt[1]/CLK (5.523, 5.523, 5.622, 5.622) - vs_down_delay_cnt[1]/CLK (5.526, 5.526, 5.625, 5.625) + vs_down_delay_cnt[2]/CLK (5.523, 5.523, 5.622, 5.622) - vs_down_delay_cnt[2]/CLK (5.526, 5.526, 5.625, 5.625) + vs_down_delay_cnt[3]/CLK (5.523, 5.523, 5.622, 5.622) - vs_down_delay_cnt[3]/CLK (5.526, 5.526, 5.625, 5.625) + vs_down_delay_cnt[4]/CLK (5.523, 5.523, 5.622, 5.622) - vs_down_delay_cnt[4]/CLK (5.526, 5.526, 5.625, 5.625) + vs_down_delay_cnt[5]/CLK (5.523, 5.523, 5.622, 5.622) - vs_down_delay_cnt[5]/CLK (5.526, 5.526, 5.625, 5.625) + vs_down_delay_cnt[6]/CLK (5.523, 5.523, 5.622, 5.622) - vs_down_delay_cnt[6]/CLK (5.526, 5.526, 5.625, 5.625) + vs_down_delay_cnt[7]/CLK (5.523, 5.523, 5.622, 5.622) - vs_down_delay_cnt[7]/CLK (5.526, 5.526, 5.625, 5.625) + vs_down_delay_cnt[8]/CLK (5.523, 5.523, 5.622, 5.622) - vs_down_delay_cnt[8]/CLK (5.526, 5.526, 5.625, 5.625) + vs_down_delay_cnt[9]/CLK (5.523, 5.523, 5.622, 5.622) - vs_down_delay_cnt[9]/CLK (5.526, 5.526, 5.625, 5.625) + vs_down_delay_cnt[10]/CLK (5.523, 5.523, 5.622, 5.622) - vs_down_delay_cnt[10]/CLK (5.526, 5.526, 5.625, 5.625) + vs_down_delay_cnt[11]/CLK (5.523, 5.523, 5.622, 5.622) - vs_down_delay_cnt[11]/CLK (5.526, 5.526, 5.625, 5.625) + vs_pos_delay_cnt[0]/CLK (5.523, 5.523, 5.622, 5.622) - vs_pos_delay_cnt[0]/CLK (5.526, 5.526, 5.625, 5.625) + vs_pos_delay_cnt[1]/CLK (5.523, 5.523, 5.622, 5.622) - vs_pos_delay_cnt[1]/CLK (5.526, 5.526, 5.625, 5.625) + vs_pos_delay_cnt[2]/CLK (5.523, 5.523, 5.622, 5.622) - vs_pos_delay_cnt[2]/CLK (5.526, 5.526, 5.625, 5.625) + vs_pos_delay_cnt[3]/CLK (5.523, 5.523, 5.622, 5.622) - vs_pos_delay_cnt[3]/CLK (5.526, 5.526, 5.625, 5.625) + vs_pos_delay_cnt[4]/CLK (5.523, 5.523, 5.622, 5.622) - vs_pos_delay_cnt[4]/CLK (5.526, 5.526, 5.625, 5.625) + vs_pos_delay_cnt[5]/CLK (5.523, 5.523, 5.622, 5.622) - vs_pos_delay_cnt[5]/CLK (5.526, 5.526, 5.625, 5.625) + vs_pos_delay_cnt[6]/CLK (5.523, 5.523, 5.622, 5.622) - vs_pos_delay_cnt[6]/CLK (5.526, 5.526, 5.625, 5.625) + vs_pos_delay_cnt[7]/CLK (5.523, 5.523, 5.622, 5.622) - vs_pos_delay_cnt[7]/CLK (5.526, 5.526, 5.625, 5.625) + vs_pos_delay_cnt[8]/CLK (5.523, 5.523, 5.622, 5.622) - vs_pos_delay_cnt[8]/CLK (5.526, 5.526, 5.625, 5.625) + vs_pos_delay_cnt[9]/CLK (5.523, 5.523, 5.622, 5.622) - vs_pos_delay_cnt[9]/CLK (5.526, 5.526, 5.625, 5.625) + vs_pos_delay_cnt[10]/CLK (5.523, 5.523, 5.622, 5.622) - vs_pos_delay_cnt[10]/CLK (5.526, 5.526, 5.625, 5.625) + vs_pos_delay_cnt[11]/CLK (5.523, 5.523, 5.622, 5.622) - vs_pos_delay_cnt[11]/CLK (5.526, 5.526, 5.625, 5.625) - - - wr0_vs/CLK (5.526, 5.526, 5.625, 5.625) + wr0_vs/CLK (5.523, 5.523, 5.622, 5.622) - clk_200m (200.00MHZ) (drive 919 loads) + clk_200m (200.00MHZ) (drive 75 loads) u_sys_pll/u_pll_e3/CLKOUT1 (2.391, 2.391, 2.491, 2.491) - zoom_clk (net) + ddr_clk (net) - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (4.367, 4.367, 4.467, 4.467) + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (2.996, 2.996, 3.096, 3.096) - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (4.367, 4.367, 4.467, 4.467) + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (2.996, 2.996, 3.096, 3.096) u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin (net) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[0]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[0]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[1]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[1]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[2]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[2]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[3]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[3]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_ack_rst_ctrl/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_ack_rst_ctrl/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_n/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_n/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[0]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[0]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[1]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[1]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[0]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[0]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[1]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[1]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[2]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[2]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[3]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/state_reg[3]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[0]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[0]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[1]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[1]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[2]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[2]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[3]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[3]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[4]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[4]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[5]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[5]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[6]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[6]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[7]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[7]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_dll_rst_rg/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_dll_rst_rg/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_dqs_rst/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_dqs_rst/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[0]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[0]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[1]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[1]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[2]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[2]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[3]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[3]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[4]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[4]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[5]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[5]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[6]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[6]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[7]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[7]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[8]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[8]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[9]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[9]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[10]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[10]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[11]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[11]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[12]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[12]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[13]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[13]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[14]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[14]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[15]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[16]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[16]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[17]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[17]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[18]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[18]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_b_ff/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_b_ff/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_b_neg/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_b_neg/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_deb_pre/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/signal_deb_pre/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_rst/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_rst/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_rst_n_rg/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_rst_n_rg/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/dll_lock_d[0]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/dll_lock_d[0]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/dll_lock_d[1]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/dll_lock_d[1]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/dll_update_ack_rst_ctrl_d[0]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/dll_update_ack_rst_ctrl_d[0]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/dll_update_ack_rst_ctrl_d[1]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/dll_update_ack_rst_ctrl_d[1]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/dll_update_req_rst_ctrl/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/dll_update_req_rst_ctrl/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/pll_lock_d[0]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/pll_lock_d[0]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/pll_lock_d[1]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/pll_lock_d[1]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[0]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[0]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[1]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[1]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[2]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[2]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[3]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[3]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[4]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[5]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[5]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[6]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[6]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[7]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[7]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[8]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/state_reg[8]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/training_error_d[0]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/training_error_d[0]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/training_error_d[1]/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/training_error_d[1]/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d1/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d1/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d2/CLK (6.563, 6.563, 6.663, 6.663) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/wrlvl_ck_dly_start_rst_d2/CLK (5.192, 5.192, 5.292, 5.292) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (5.214, 5.214, 5.314, 5.314) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (3.843, 3.843, 3.943, 3.943) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (5.308, 5.308, 5.406, 5.406) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (3.937, 3.937, 4.035, 4.035) u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] (net) - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (5.913, 5.913, 6.011, 6.011) + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (4.542, 4.542, 4.640, 4.640) ddrphy_clkin (100.00MHZ) (drive 5817 loads) - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (5.913, 5.913, 6.011, 6.011) + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (4.542, 4.542, 4.640, 4.640) u_axi_ddr_top/clk (net) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_ba[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_ba[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_ba[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_ba[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_cas_n/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_cas_n/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_cke/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_cke/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_cs_n/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_cs_n/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_odt/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_odt/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_ras_n/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_ras_n/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_we_n/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_we_n/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cke_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cke_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_cmd[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_pwron_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_pwron_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t200us[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_t500us[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tmod_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tmod_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tmrd_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tmrd_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_txpr_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_txpr_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/cnt_tzqinit_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_address[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_ba[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_ba[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_ba[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_ba[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_cas_n/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_cas_n/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_cke/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_cke/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_cs_n/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_cs_n/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_done/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_done/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_rst/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_rst/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_state_reg[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_we_n/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_we_n/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/mr_load_cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/mr_load_cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/mr_load_cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/mr_load_cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/mr_load_done/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/mr_load_done/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/calib_done/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/calib_done/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/init_start/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/init_start/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/rdcal_start/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/rdcal_start/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/wrlvl_start/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/wrlvl_start/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cmd_cnt[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cnt_tmod_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cnt_tmod_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cnt_twldqsen_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/cnt_twldqsen_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_ba[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_ba[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_cas_n/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_cas_n/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_cke/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_cke/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_done/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_done/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_dqs_req/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_dqs_req/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_dqs_resp_r/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_dqs_resp_r/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_odt/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_odt/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_state_reg[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[16]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[16]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[17]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt[17]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt_trfc_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/cnt_trfc_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/ddrphy_rst_ack_r[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/ddrphy_rst_ack_r[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/ddrphy_rst_ack_r[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/ddrphy_rst_ack_r[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/ddrphy_rst_req/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/ddrphy_rst_req/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/gate_move_en/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/gate_move_en/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/gatecal_start/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/gatecal_start/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/init_adj_rdel/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/init_adj_rdel/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_address[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_address[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_address[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_address[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_address[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_address[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_ba[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_ba[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_cas_n/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_cas_n/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_cs_n/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_cs_n/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_done/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_done/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_odt/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_odt/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_ras_n/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_ras_n/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[16]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[16]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[17]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_state_reg[17]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_success/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_success/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_we_n/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_we_n/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[32]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[32]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[64]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[64]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[96]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[96]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[128]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[128]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[160]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[160]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[192]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[192]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[224]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata[224]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata_en[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata_en[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata_en[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata_en[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata_en[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata_en[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata_en[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_wrdata_en[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rddata_cal/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rddata_cal/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdel_calibration/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdel_calibration/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdel_move_en/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdel_move_en/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/ref_cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/ref_cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/ref_cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/ref_cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/ref_cnt_done/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/ref_cnt_done/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/reinit_adj_rdel/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/reinit_adj_rdel/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/wr_enable/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/wr_enable/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/calib_done_r/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/calib_done_r/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/dfi_init_complete/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/dfi_init_complete/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[30]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[30]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[31]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[31]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[32]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[32]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[33]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[33]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[34]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[34]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[35]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[35]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[36]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[36]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[37]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[37]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[38]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[38]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[39]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[39]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[40]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[40]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[41]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[41]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[30]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[30]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[31]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[31]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[32]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[32]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[33]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[33]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[34]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[34]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[35]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[35]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[36]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[36]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[37]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[37]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[38]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[38]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[39]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[39]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[40]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[40]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[41]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr_d[41]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ba_d[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cas_n[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cas_n[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cas_n[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cas_n[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cas_n_d[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cas_n_d[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cas_n_d[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cas_n_d[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cke[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cke[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cke_d[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cke_d[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cs_n[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cs_n[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cs_n[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cs_n[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cs_n_d[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cs_n_d[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cs_n_d[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_cs_n_d[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_odt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_odt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_odt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_odt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_odt_d[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_odt_d[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_odt_d[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_odt_d[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ras_n[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ras_n[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ras_n[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ras_n[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ras_n_d[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ras_n_d[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ras_n_d[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_ras_n_d[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_we_n[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_we_n[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_we_n[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_we_n[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_we_n_d[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_we_n_d[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_we_n_d[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_we_n_d[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[16]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[16]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[17]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[17]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[18]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[18]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[19]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[19]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[20]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[20]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[21]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[21]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[22]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[22]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[23]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[23]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[24]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[24]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[25]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[25]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[26]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[26]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[27]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[27]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[28]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[28]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[29]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[29]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[30]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[30]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[31]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[31]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[32]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[32]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[33]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[33]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[34]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[34]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[35]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[35]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[36]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[36]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[37]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[37]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[38]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[38]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[39]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[39]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[40]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[40]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[41]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[41]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[42]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[42]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[43]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[43]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[44]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[44]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[45]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[45]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[46]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[46]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[47]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[47]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[48]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[48]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[49]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[49]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[50]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[50]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[51]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[51]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[52]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[52]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[53]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[53]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[54]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[54]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[55]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[55]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[56]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[56]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[57]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[57]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[58]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[58]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[59]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[59]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[60]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[60]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[61]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[61]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[62]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[62]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[63]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[63]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[64]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[64]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[65]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[65]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[66]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[66]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[67]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[67]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[68]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[68]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[69]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[69]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[70]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[70]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[71]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[71]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[72]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[72]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[73]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[73]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[74]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[74]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[75]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[75]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[76]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[76]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[77]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[77]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[78]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[78]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[79]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[79]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[80]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[80]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[81]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[81]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[82]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[82]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[83]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[83]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[84]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[84]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[85]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[85]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[86]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[86]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[87]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[87]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[88]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[88]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[89]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[89]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[90]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[90]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[91]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[91]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[92]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[92]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[93]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[93]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[94]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[94]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[95]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[95]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[96]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[96]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[97]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[97]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[98]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[98]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[99]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[99]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[100]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[100]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[101]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[101]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[102]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[102]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[103]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[103]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[104]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[104]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[105]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[105]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[106]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[106]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[107]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[107]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[108]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[108]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[109]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[109]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[110]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[110]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[111]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[111]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[112]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[112]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[113]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[113]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[114]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[114]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[115]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[115]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[116]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[116]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[117]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[117]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[118]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[118]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[119]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[119]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[120]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[120]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[121]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[121]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[122]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[122]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[123]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[123]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[124]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[124]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[125]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[125]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[126]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[126]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[127]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[127]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[128]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[128]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[129]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[129]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[130]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[130]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[131]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[131]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[132]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[132]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[133]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[133]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[134]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[134]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[135]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[135]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[136]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[136]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[137]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[137]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[138]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[138]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[139]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[139]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[140]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[140]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[141]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[141]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[142]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[142]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[143]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[143]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[144]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[144]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[145]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[145]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[146]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[146]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[147]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[147]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[148]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[148]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[149]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[149]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[150]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[150]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[151]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[151]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[152]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[152]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[153]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[153]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[154]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[154]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[155]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[155]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[156]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[156]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[157]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[157]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[158]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[158]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[159]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[159]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[160]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[160]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[161]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[161]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[162]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[162]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[163]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[163]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[164]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[164]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[165]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[165]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[166]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[166]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[167]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[167]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[168]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[168]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[169]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[169]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[170]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[170]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[171]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[171]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[172]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[172]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[173]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[173]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[174]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[174]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[175]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[175]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[176]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[176]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[177]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[177]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[178]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[178]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[179]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[179]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[180]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[180]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[181]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[181]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[182]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[182]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[183]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[183]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[184]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[184]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[185]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[185]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[186]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[186]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[187]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[187]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[188]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[188]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[189]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[189]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[190]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[190]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[191]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[191]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[192]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[192]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[193]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[193]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[194]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[194]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[195]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[195]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[196]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[196]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[197]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[197]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[198]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[198]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[199]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[199]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[200]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[200]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[201]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[201]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[202]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[202]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[203]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[203]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[204]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[204]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[205]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[205]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[206]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[206]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[207]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[207]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[208]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[208]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[209]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[209]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[210]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[210]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[211]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[211]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[212]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[212]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[213]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[213]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[214]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[214]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[215]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[215]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[216]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[216]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[217]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[217]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[218]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[218]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[219]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[219]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[220]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[220]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[221]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[221]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[222]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[222]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[223]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[223]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[224]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[224]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[225]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[225]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[226]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[226]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[227]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[227]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[228]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[228]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[229]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[229]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[230]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[230]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[231]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[231]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[232]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[232]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[233]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[233]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[234]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[234]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[235]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[235]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[236]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[236]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[237]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[237]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[238]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[238]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[239]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[239]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[240]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[240]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[241]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[241]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[242]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[242]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[243]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[243]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[244]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[244]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[245]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[245]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[246]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[246]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[247]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[247]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[248]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[248]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[249]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[249]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[250]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[250]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[251]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[251]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[252]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[252]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[253]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[253]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[254]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[254]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[255]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata[255]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[16]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[16]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[17]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[17]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[18]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[18]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[19]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[19]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[20]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[20]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[21]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[21]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[22]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[22]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[23]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[23]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[24]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[24]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[25]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[25]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[26]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[26]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[27]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[27]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[28]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[28]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[29]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[29]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[30]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[30]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[31]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[31]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[32]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[32]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[33]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[33]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[34]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[34]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[35]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[35]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[36]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[36]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[37]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[37]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[38]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[38]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[39]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[39]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[40]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[40]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[41]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[41]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[42]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[42]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[43]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[43]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[44]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[44]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[45]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[45]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[46]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[46]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[47]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[47]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[48]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[48]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[49]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[49]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[50]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[50]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[51]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[51]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[52]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[52]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[53]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[53]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[54]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[54]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[55]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[55]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[56]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[56]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[57]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[57]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[58]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[58]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[59]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[59]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[60]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[60]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[61]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[61]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[62]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[62]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[63]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[63]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[64]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[64]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[65]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[65]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[66]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[66]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[67]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[67]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[68]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[68]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[69]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[69]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[70]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[70]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[71]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[71]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[72]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[72]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[73]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[73]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[74]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[74]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[75]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[75]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[76]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[76]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[77]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[77]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[78]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[78]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[79]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[79]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[80]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[80]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[81]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[81]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[82]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[82]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[83]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[83]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[84]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[84]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[85]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[85]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[86]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[86]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[87]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[87]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[88]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[88]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[89]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[89]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[90]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[90]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[91]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[91]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[92]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[92]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[93]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[93]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[94]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[94]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[95]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[95]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[96]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[96]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[97]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[97]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[98]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[98]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[99]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[99]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[100]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[100]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[101]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[101]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[102]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[102]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[103]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[103]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[104]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[104]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[105]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[105]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[106]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[106]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[107]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[107]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[108]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[108]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[109]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[109]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[110]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[110]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[111]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[111]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[112]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[112]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[113]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[113]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[114]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[114]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[115]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[115]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[116]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[116]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[117]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[117]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[118]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[118]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[119]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[119]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[120]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[120]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[121]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[121]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[122]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[122]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[123]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[123]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[124]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[124]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[125]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[125]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[126]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[126]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[127]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[127]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[128]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[128]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[129]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[129]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[130]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[130]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[131]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[131]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[132]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[132]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[133]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[133]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[134]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[134]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[135]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[135]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[136]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[136]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[137]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[137]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[138]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[138]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[139]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[139]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[140]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[140]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[141]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[141]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[142]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[142]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[143]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[143]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[144]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[144]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[145]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[145]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[146]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[146]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[147]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[147]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[148]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[148]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[149]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[149]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[150]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[150]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[151]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[151]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[152]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[152]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[153]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[153]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[154]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[154]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[155]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[155]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[156]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[156]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[157]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[157]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[158]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[158]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[159]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[159]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[160]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[160]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[161]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[161]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[162]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[162]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[163]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[163]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[164]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[164]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[165]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[165]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[166]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[166]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[167]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[167]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[168]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[168]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[169]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[169]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[170]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[170]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[171]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[171]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[172]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[172]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[173]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[173]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[174]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[174]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[175]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[175]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[176]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[176]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[177]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[177]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[178]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[178]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[179]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[179]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[180]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[180]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[181]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[181]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[182]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[182]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[183]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[183]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[184]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[184]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[185]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[185]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[186]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[186]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[187]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[187]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[188]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[188]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[189]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[189]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[190]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[190]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[191]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[191]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[192]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[192]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[193]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[193]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[194]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[194]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[195]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[195]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[196]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[196]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[197]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[197]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[198]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[198]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[199]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[199]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[200]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[200]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[201]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[201]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[202]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[202]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[203]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[203]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[204]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[204]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[205]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[205]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[206]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[206]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[207]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[207]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[208]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[208]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[209]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[209]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[210]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[210]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[211]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[211]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[212]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[212]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[213]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[213]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[214]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[214]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[215]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[215]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[216]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[216]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[217]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[217]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[218]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[218]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[219]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[219]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[220]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[220]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[221]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[221]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[222]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[222]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[223]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[223]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[224]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[224]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[225]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[225]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[226]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[226]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[227]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[227]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[228]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[228]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[229]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[229]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[230]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[230]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[231]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[231]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[232]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[232]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[233]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[233]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[234]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[234]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[235]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[235]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[236]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[236]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[237]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[237]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[238]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[238]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[239]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[239]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[240]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[240]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[241]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[241]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[242]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[242]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[243]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[243]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[244]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[244]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[245]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[245]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[246]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[246]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[247]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[247]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[248]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[248]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[249]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[249]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[250]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[250]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[251]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[251]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[252]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[252]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[253]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[253]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[254]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[254]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[255]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_d[255]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_en[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_en[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_en[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_en[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_en[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_en[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_en[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_en[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask[24]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask[24]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[24]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_wrdata_mask_d[24]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr1_ddr3[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr2_ddr3[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr3_ddr3[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r1[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r1[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_dll_rst_sync/sig_async_r1[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_dll_rst_sync/sig_async_r1[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_dll_rst_sync/sig_async_r2[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_dll_rst_sync/sig_async_r2[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/ck_dly_set_bin[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_ddc_ca/CLKB (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_ddc_ca/CLKB (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[1].u_ddc_ca/CLKB (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[1].u_ddc_ca/CLKB (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[2].u_ddc_ca/CLKB (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[2].u_ddc_ca/CLKB (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[3].u_ddc_ca/CLKB (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[3].u_ddc_ca/CLKB (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_vld/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_vld/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_comb_r[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_comb_r[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_comb_r[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_comb_r[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r1[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r1[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r1[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r1[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r2[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r2[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r2[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r2[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r3[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r3[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r3[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/read_cmd_mux_r3[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_adj_done/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_adj_done/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_cal_error/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_cal_error/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_error/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_error/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass_d/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass_d/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_check_done/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_check_done/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_set_bin_tra[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_set_bin_tra[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_set_bin_tra[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_set_bin_tra[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_set_bin_tra[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_set_bin_tra[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_set_bin_tra[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_set_bin_tra[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_set_bin_tra[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_set_bin_tra[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_set_bin_tra[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_set_bin_tra[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_set_bin_tra[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_set_bin_tra[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_set_bin_tra[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_set_bin_tra[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ddrphy_gatei/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/ddrphy_gatei/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/dq_rising/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/dq_rising/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_done_flag/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_done_flag/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_flag/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_flag/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_resp/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_resp/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_error/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_error/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].u_oserdes_dq/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].u_oserdes_dq/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[1].DQ0_GTP_ISERDES/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[1].DQ0_GTP_ISERDES/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[1].u_oserdes_dq/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[1].u_oserdes_dq/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[2].DQ0_GTP_ISERDES/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[2].DQ0_GTP_ISERDES/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[2].u_oserdes_dq/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[2].u_oserdes_dq/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[3].DQ0_GTP_ISERDES/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[3].DQ0_GTP_ISERDES/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[3].u_oserdes_dq/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[3].u_oserdes_dq/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[4].DQ0_GTP_ISERDES/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[4].DQ0_GTP_ISERDES/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[4].u_oserdes_dq/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[4].u_oserdes_dq/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[5].DQ0_GTP_ISERDES/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[5].DQ0_GTP_ISERDES/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[5].u_oserdes_dq/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[5].u_oserdes_dq/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[6].DQ0_GTP_ISERDES/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[6].DQ0_GTP_ISERDES/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[6].u_oserdes_dq/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[6].u_oserdes_dq/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[7].DQ0_GTP_ISERDES/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[7].DQ0_GTP_ISERDES/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[7].u_oserdes_dq/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[7].u_oserdes_dq/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/dqs_gate_check_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/dqs_gate_check_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gate_check/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gate_check/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_check_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_check_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[16]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[16]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[17]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[17]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[18]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[18]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[19]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[19]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[20]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[20]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[21]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[21]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[22]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[22]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[23]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[23]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[24]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[24]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[25]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[25]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[26]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[26]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[27]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[27]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[28]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[28]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[29]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[29]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[30]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[30]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[31]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[31]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[32]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[32]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[33]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[33]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[34]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[34]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[35]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[35]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[36]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[36]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[37]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[37]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[38]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[38]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[39]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[39]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[40]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[40]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[41]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[41]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[42]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[42]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[43]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[43]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[44]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[44]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[45]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[45]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[46]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[46]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[47]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[47]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[48]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[48]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[49]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[49]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[50]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[50]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[51]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[51]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[52]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[52]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[53]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[53]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[54]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[54]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[55]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[55]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[56]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[56]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[57]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[57]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[58]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[58]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[59]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[59]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[60]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[60]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[61]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[61]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[62]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[62]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[63]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[63]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rdvalid_r1/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rdvalid_r1/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_inc_dec_n/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_inc_dec_n/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_rdel_done/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/adj_rdel_done/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/default_samp_position[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/next_default_samp_position[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_cal_vld/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_cal_vld/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_done/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_done/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_error/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_error/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calibration_d/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calibration_d/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_move_done/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_move_done/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_sync/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_sync/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/reinit_adj_rdel_d/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/reinit_adj_rdel_d/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/CLKB (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/CLKB (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_oserdes_dm/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_oserdes_dm/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_oserdes_dqs/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_oserdes_dqs/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_r2[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_r2[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_r[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_r[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_r[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_r[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_r[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_r[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_r[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/wdata_path_adj/phy_wrdata_en_r[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_vld/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_vld/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_adj_done/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_adj_done/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_cal_error/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_cal_error/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_error/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_error/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass_d/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass_d/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ck_check_done/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ck_check_done/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ddrphy_gatei/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/ddrphy_gatei/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/dq_rising/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/dq_rising/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_done_flag/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_done_flag/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_flag/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_flag/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_resp/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_resp/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_error/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_error/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[0].u_oserdes_dq/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[0].u_oserdes_dq/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[1].DQ0_GTP_ISERDES/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[1].DQ0_GTP_ISERDES/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[1].u_oserdes_dq/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[1].u_oserdes_dq/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[2].DQ0_GTP_ISERDES/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[2].DQ0_GTP_ISERDES/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[2].u_oserdes_dq/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[2].u_oserdes_dq/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[3].DQ0_GTP_ISERDES/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[3].DQ0_GTP_ISERDES/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[3].u_oserdes_dq/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[3].u_oserdes_dq/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[4].DQ0_GTP_ISERDES/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[4].DQ0_GTP_ISERDES/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[4].u_oserdes_dq/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[4].u_oserdes_dq/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[5].DQ0_GTP_ISERDES/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[5].DQ0_GTP_ISERDES/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[5].u_oserdes_dq/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[5].u_oserdes_dq/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[6].DQ0_GTP_ISERDES/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[6].DQ0_GTP_ISERDES/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[6].u_oserdes_dq/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[6].u_oserdes_dq/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[7].DQ0_GTP_ISERDES/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[7].DQ0_GTP_ISERDES/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[7].u_oserdes_dq/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[7].u_oserdes_dq/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/dqs_gate_check_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/dqs_gate_check_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gate_check/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gate_check/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_check_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_check_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[16]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[16]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[17]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[17]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[18]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[18]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[19]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[19]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[20]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[20]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[21]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[21]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[22]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[22]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[23]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[23]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[24]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[24]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[25]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[25]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[26]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[26]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[27]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[27]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[28]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[28]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[29]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[29]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[30]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[30]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[31]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[31]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[32]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[32]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[33]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[33]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[34]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[34]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[35]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[35]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[36]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[36]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[37]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[37]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[38]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[38]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[39]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[39]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[40]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[40]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[41]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[41]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[42]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[42]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[43]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[43]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[44]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[44]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[45]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[45]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[46]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[46]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[47]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[47]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[48]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[48]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[49]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[49]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[50]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[50]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[51]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[51]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[52]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[52]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[53]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[53]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[54]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[54]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[55]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[55]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[56]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[56]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[57]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[57]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[58]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[58]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[59]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[59]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[60]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[60]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[61]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[61]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[62]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[62]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[63]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[63]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rdvalid_r1/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rdvalid_r1/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/adj_rdel_done/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/adj_rdel_done/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_done/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_done/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_error/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_error/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_move_done/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_move_done/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_sync/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_sync/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/u_ddc_dqs/CLKB (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/u_ddc_dqs/CLKB (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/u_oserdes_dm/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/u_oserdes_dm/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/u_oserdes_dqs/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/u_oserdes_dqs/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_vld/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_vld/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_adj_done/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_adj_done/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_cal_error/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_cal_error/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_error/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_error/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass_d/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass_d/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_check_done/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_check_done/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ddrphy_gatei/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/ddrphy_gatei/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/dq_rising/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/dq_rising/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_done_flag/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_done_flag/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_flag/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_flag/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_resp/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_resp/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_error/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_error/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[0].u_oserdes_dq/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[0].u_oserdes_dq/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[1].DQ0_GTP_ISERDES/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[1].DQ0_GTP_ISERDES/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[1].u_oserdes_dq/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[1].u_oserdes_dq/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[2].DQ0_GTP_ISERDES/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[2].DQ0_GTP_ISERDES/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[2].u_oserdes_dq/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[2].u_oserdes_dq/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[3].DQ0_GTP_ISERDES/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[3].DQ0_GTP_ISERDES/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[3].u_oserdes_dq/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[3].u_oserdes_dq/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[4].DQ0_GTP_ISERDES/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[4].DQ0_GTP_ISERDES/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[4].u_oserdes_dq/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[4].u_oserdes_dq/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[5].DQ0_GTP_ISERDES/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[5].DQ0_GTP_ISERDES/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[5].u_oserdes_dq/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[5].u_oserdes_dq/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[6].DQ0_GTP_ISERDES/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[6].DQ0_GTP_ISERDES/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[6].u_oserdes_dq/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[6].u_oserdes_dq/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[7].DQ0_GTP_ISERDES/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[7].DQ0_GTP_ISERDES/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[7].u_oserdes_dq/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[7].u_oserdes_dq/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/dqs_gate_check_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/dqs_gate_check_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gate_check/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gate_check/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_check_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_check_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[16]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[16]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[17]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[17]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[18]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[18]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[19]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[19]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[20]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[20]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[21]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[21]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[22]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[22]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[23]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[23]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[24]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[24]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[25]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[25]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[26]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[26]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[27]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[27]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[28]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[28]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[29]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[29]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[30]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[30]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[31]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[31]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[32]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[32]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[33]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[33]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[34]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[34]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[35]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[35]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[36]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[36]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[37]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[37]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[38]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[38]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[39]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[39]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[40]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[40]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[41]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[41]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[42]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[42]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[43]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[43]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[44]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[44]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[45]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[45]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[46]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[46]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[47]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[47]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[48]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[48]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[49]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[49]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[50]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[50]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[51]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[51]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[52]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[52]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[53]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[53]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[54]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[54]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[55]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[55]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[56]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[56]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[57]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[57]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[58]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[58]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[59]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[59]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[60]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[60]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[61]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[61]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[62]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[62]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[63]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[63]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rdvalid_r1/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rdvalid_r1/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/adj_rdel_done/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/adj_rdel_done/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_done/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_done/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_error/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_error/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_move_done/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_move_done/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_sync/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_sync/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/u_ddc_dqs/CLKB (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/u_ddc_dqs/CLKB (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/u_oserdes_dm/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/u_oserdes_dm/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/u_oserdes_dqs/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/u_oserdes_dqs/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r1[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r2[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r3[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_vld/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_vld/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dgts_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_adj_done/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_adj_done/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_cal_error/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_cal_error/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_error/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_error/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass_d/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_check_pass_d/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_value_lock[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_win_size[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/golden_value[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_check_done/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_check_done/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ck_dly_step[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ddrphy_gatei/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/ddrphy_gatei/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/dq_rising/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/dq_rising/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/dq_vld/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/step_cnt[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/vld_init_cnt[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_done_flag/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_done_flag/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wl_state_reg[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_check_seq[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_flag/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_flag/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_ck_dly_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_r[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dq_seq[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_en/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_resp/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_dqs_resp/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_error/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_error/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_wrlvl/wrlvl_step[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].u_oserdes_dq/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].u_oserdes_dq/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[1].DQ0_GTP_ISERDES/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[1].DQ0_GTP_ISERDES/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[1].u_oserdes_dq/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[1].u_oserdes_dq/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[2].DQ0_GTP_ISERDES/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[2].DQ0_GTP_ISERDES/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[2].u_oserdes_dq/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[2].u_oserdes_dq/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[3].DQ0_GTP_ISERDES/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[3].DQ0_GTP_ISERDES/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[3].u_oserdes_dq/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[3].u_oserdes_dq/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[4].DQ0_GTP_ISERDES/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[4].DQ0_GTP_ISERDES/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[4].u_oserdes_dq/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[4].u_oserdes_dq/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[5].DQ0_GTP_ISERDES/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[5].DQ0_GTP_ISERDES/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[5].u_oserdes_dq/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[5].u_oserdes_dq/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[6].DQ0_GTP_ISERDES/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[6].DQ0_GTP_ISERDES/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[6].u_oserdes_dq/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[6].u_oserdes_dq/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[7].DQ0_GTP_ISERDES/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[7].DQ0_GTP_ISERDES/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[7].u_oserdes_dq/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[7].u_oserdes_dq/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/dqs_gate_check_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/dqs_gate_check_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gate_check/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gate_check/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_check_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_check_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[16]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[16]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[17]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[17]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[18]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[18]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[19]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[19]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[20]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[20]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[21]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[21]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[22]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[22]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[23]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[23]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[24]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[24]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[25]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[25]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[26]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[26]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[27]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[27]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[28]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[28]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[29]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[29]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[30]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[30]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[31]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[31]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[32]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[32]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[33]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[33]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[34]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[34]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[35]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[35]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[36]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[36]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[37]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[37]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[38]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[38]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[39]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[39]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[40]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[40]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[41]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[41]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[42]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[42]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[43]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[43]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[44]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[44]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[45]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[45]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[46]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[46]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[47]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[47]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[48]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[48]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[49]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[49]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[50]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[50]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[51]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[51]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[52]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[52]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[53]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[53]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[54]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[54]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[55]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[55]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[56]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[56]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[57]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[57]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[58]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[58]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[59]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[59]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[60]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[60]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[61]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[61]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[62]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[62]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[63]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rddata_r1[63]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rdel_rvalid/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rdvalid_r1/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rdvalid_r1/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/adj_rdel_done/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/adj_rdel_done/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/cnt[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/left_margin[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_done/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_done/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_error/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_calib_error/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ctrl[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_move_done/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_move_done/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_d[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_sync/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/rdel_ov_sync/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/right_margin[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/state_reg[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/total_margin[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/CLKB (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/CLKB (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_oserdes_dm/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_oserdes_dm/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_oserdes_dqs/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_oserdes_dqs/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_control_path_adj/phy_addr_r[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_control_path_adj/phy_addr_r[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_control_path_adj/phy_cke_r[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_control_path_adj/phy_cke_r[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_control_path_adj/phy_odt_r[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_control_path_adj/phy_odt_r[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_logic_rstn_sync/sig_async_r1[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_logic_rstn_sync/sig_async_r1[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_logic_rstn_sync/sig_async_r2[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_logic_rstn_sync/sig_async_r2[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_addr_0/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_addr_0/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_addr_1/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_addr_1/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_addr_2/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_addr_2/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_addr_3/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_addr_3/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_addr_4/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_addr_4/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_addr_5/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_addr_5/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_addr_6/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_addr_6/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_addr_7/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_addr_7/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_addr_8/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_addr_8/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_addr_9/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_addr_9/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_addr_10/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_addr_10/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_addr_11/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_addr_11/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_addr_12/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_addr_12/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_addr_13/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_addr_13/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_addr_14/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_addr_14/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_ba0/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_ba0/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_ba1/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_ba1/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_ba2/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_ba2/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_casn/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_casn/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_ck/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_ck/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_cke/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_cke/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_csn/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_csn/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_odt/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_odt/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_rasn/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_rasn/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_wen/RCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_oserdes_wen/RCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[16]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[16]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[17]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[17]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[18]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[18]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[19]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[19]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[20]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[20]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[21]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[21]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[22]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[22]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[23]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[23]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[24]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[24]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[25]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[25]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[26]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[26]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[27]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[27]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[28]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[28]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[29]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[29]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[30]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[30]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[31]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[31]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[32]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[32]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[33]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[33]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[34]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[34]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[35]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[35]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[36]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[36]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[37]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[37]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[38]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[38]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[39]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[39]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[40]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[40]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[41]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[41]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[42]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[42]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[43]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[43]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[44]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[44]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[45]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[45]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[46]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[46]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[47]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[47]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[48]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[48]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[49]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[49]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[50]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[50]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[51]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[51]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[52]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[52]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[53]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[53]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[54]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[54]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[55]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[55]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[56]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[56]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[57]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[57]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[58]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[58]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[59]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[59]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[60]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[60]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[61]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[61]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[62]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[62]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[63]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[63]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[64]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[64]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[65]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[65]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[66]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[66]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[67]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[67]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[68]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[68]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[69]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[69]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[70]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[70]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[71]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[71]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[72]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[72]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[73]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[73]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[74]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[74]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[75]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[75]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[76]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[76]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[77]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[77]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[78]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[78]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[79]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[79]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[80]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[80]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[81]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[81]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[82]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[82]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[83]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[83]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[84]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[84]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[85]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[85]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[86]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[86]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[87]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[87]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[88]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[88]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[89]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[89]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[90]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[90]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[91]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[91]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[92]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[92]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[93]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[93]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[94]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[94]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[95]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[95]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[96]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[96]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[97]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[97]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[98]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[98]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[99]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[99]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[100]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[100]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[101]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[101]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[102]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[102]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[103]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[103]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[104]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[104]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[105]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[105]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[106]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[106]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[107]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[107]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[108]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[108]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[109]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[109]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[110]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[110]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[111]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[111]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[112]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[112]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[113]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[113]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[114]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[114]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[115]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[115]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[116]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[116]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[117]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[117]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[118]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[118]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[119]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[119]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[120]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[120]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[121]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[121]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[122]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[122]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[123]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[123]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[124]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[124]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[125]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[125]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[126]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[126]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[127]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[127]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[128]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[128]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[129]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[129]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[130]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[130]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[131]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[131]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[132]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[132]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[133]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[133]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[134]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[134]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[135]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[135]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[136]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[136]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[137]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[137]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[138]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[138]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[139]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[139]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[140]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[140]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[141]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[141]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[142]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[142]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[143]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[143]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[144]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[144]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[145]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[145]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[146]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[146]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[147]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[147]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[148]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[148]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[149]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[149]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[150]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[150]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[151]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[151]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[152]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[152]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[153]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[153]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[154]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[154]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[155]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[155]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[156]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[156]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[157]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[157]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[158]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[158]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[159]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[159]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[160]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[160]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[161]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[161]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[162]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[162]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[163]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[163]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[164]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[164]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[165]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[165]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[166]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[166]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[167]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[167]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[168]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[168]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[169]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[169]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[170]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[170]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[171]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[171]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[172]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[172]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[173]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[173]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[174]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[174]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[175]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[175]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[176]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[176]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[177]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[177]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[178]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[178]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[179]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[179]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[180]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[180]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[181]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[181]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[182]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[182]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[183]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[183]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[184]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[184]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[185]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[185]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[186]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[186]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[187]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[187]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[188]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[188]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[189]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[189]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[190]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[190]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[191]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[191]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[192]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[192]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[193]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[193]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[194]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[194]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[195]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[195]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[196]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[196]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[197]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[197]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[198]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[198]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[199]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[199]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[200]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[200]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[201]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[201]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[202]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[202]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[203]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[203]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[204]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[204]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[205]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[205]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[206]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[206]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[207]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[207]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[208]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[208]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[209]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[209]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[210]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[210]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[211]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[211]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[212]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[212]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[213]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[213]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[214]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[214]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[215]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[215]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[216]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[216]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[217]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[217]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[218]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[218]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[219]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[219]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[220]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[220]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[221]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[221]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[222]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[222]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[223]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[223]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[224]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[224]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[225]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[225]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[226]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[226]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[227]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[227]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[228]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[228]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[229]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[229]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[230]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[230]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[231]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[231]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[232]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[232]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[233]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[233]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[234]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[234]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[235]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[235]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[236]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[236]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[237]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[237]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[238]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[238]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[239]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[239]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[240]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[240]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[241]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[241]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[242]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[242]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[243]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[243]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[244]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[244]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[245]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[245]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[246]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[246]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[247]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[247]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[248]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[248]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[249]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[249]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[250]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[250]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[251]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[251]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[252]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[252]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[253]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[253]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[254]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[254]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[255]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_data_r[255]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_slice_rddata_align/dqs_read_valid_r[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_start_rst/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/wrlvl_ck_dly_start_rst/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_dqs_training_rstn/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_dqs_training_rstn/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_dqs_training_rstn_d/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_dqs_training_rstn_d/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_rst_req_d1/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_rst_req_d1/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_rst_req_d2/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_rst_req_d2/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_rst_req_d3/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_rst_req_d3/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/dqs_rst_training_high_cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/dqs_rst_training_high_cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/dqs_rst_training_high_cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/dqs_rst_training_high_cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/dqs_rst_training_high_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/dqs_rst_training_high_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_l[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_addr_m[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_baddr_l[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_baddr_l[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_baddr_l[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_baddr_l[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_baddr_l[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_baddr_l[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_baddr_m[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_baddr_m[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_baddr_m[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_baddr_m[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_baddr_m[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_baddr_m[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_l[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_l[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_l[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_l[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_l[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_l[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_l[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_l[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_l[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_l[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_l[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_l[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_l[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_l[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_l[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_l[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_m[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_m[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_m[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_m[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_m[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_m[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_m[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_m[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_m[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_m[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_m[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_m[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_m[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_m[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_cfg_apb/ddr_init_done/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_cfg_apb/ddr_init_done/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[16]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[16]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[17]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[17]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[18]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[18]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[19]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[19]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[20]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[20]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[21]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[21]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[22]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[22]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[23]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[23]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[24]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[24]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[25]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[25]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[26]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[26]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[27]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_addr[27]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_id[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_id[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_id[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_id[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_id[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_id[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_id[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_id[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_len[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_len[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_len[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_len[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_len[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_len[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_len[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_len[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_new_row/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_new_row/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_new_valid/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_new_valid/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_pre_row/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_pre_row/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_refresh/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_refresh/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_write/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/dec_write/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/mcdq_dcd_rowaddr/old_row_addr_valid[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/r_init/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/r_init/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_cnt[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_req/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/refresh_req/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[16]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[16]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[17]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[17]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[18]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[18]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[19]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[19]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[20]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[20]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[21]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[21]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[22]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[22]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[23]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[23]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[24]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[24]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[25]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[25]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[26]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[26]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[27]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_addr_d[27]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_cmd_ready/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/user_cmd_ready/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[16]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[16]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[17]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[17]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[18]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[18]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[19]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[19]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[20]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[20]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[21]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[21]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[22]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[22]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[23]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[23]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[24]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[24]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[25]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[25]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[26]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[26]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[27]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_addr[27]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_cmd[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_cmd[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_cmd[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_cmd[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_cmd[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_cmd[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_cmd[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_cmd[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_en/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_en/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_id[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_id[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_id[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_id[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_id[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_id[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_id[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_id[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_tworw/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dcd_wr_tworw/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[16]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[16]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[17]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[17]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[18]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[18]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[19]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[19]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[20]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[20]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[21]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[21]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[22]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[22]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[23]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[23]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[24]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[24]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[25]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[25]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[26]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[26]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[27]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_addr_d[27]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_done/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/dec_done/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/rw_diff/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/rw_diff/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/state_reg[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/r_cnt_almost_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/r_cnt_almost_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/r_cnt_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/r_cnt_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt0[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt0[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt0[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt0[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt2[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt2[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt2[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt2[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt2[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt2[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt2[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt2[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/r_cnt_almost_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/r_cnt_almost_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/r_cnt_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/r_cnt_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt0[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt0[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt0[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt0[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt2[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt2[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt2[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt2[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt2[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt2[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt2[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt2[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/r_cnt_almost_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/r_cnt_almost_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/r_cnt_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/r_cnt_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt0[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt0[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt0[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt0[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt2[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt2[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt2[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt2[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt2[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt2[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt2[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt2[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/r_cnt_almost_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/r_cnt_almost_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/r_cnt_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/r_cnt_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt0[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt0[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt0[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt0[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt2[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt2[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt2[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt2[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt2[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt2[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt2[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt2[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/r_cnt_almost_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/r_cnt_almost_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/r_cnt_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/r_cnt_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt0[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt0[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt0[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt0[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt2[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt2[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt2[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt2[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt2[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt2[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt2[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt2[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/r_cnt_almost_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/r_cnt_almost_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/r_cnt_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/r_cnt_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt0[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt0[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt0[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt0[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/r_cnt_almost_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/r_cnt_almost_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/r_cnt_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/r_cnt_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt0[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt0[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt0[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt0[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt2[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt2[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt2[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt2[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt2[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt2[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt2[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt2[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/r_cnt_almost_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/r_cnt_almost_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/r_cnt_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/r_cnt_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt0[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt0[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt0[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt0[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[0].trc_timing/r_cnt_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[0].trc_timing/r_cnt_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[0].trc_timing/timing_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[0].trc_timing/timing_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[0].trc_timing/timing_cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[0].trc_timing/timing_cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[0].trc_timing/timing_cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[0].trc_timing/timing_cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[1].trc_timing/r_cnt_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[1].trc_timing/r_cnt_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[1].trc_timing/timing_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[1].trc_timing/timing_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[1].trc_timing/timing_cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[1].trc_timing/timing_cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[1].trc_timing/timing_cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[1].trc_timing/timing_cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[2].trc_timing/r_cnt_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[2].trc_timing/r_cnt_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[2].trc_timing/timing_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[2].trc_timing/timing_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[2].trc_timing/timing_cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[2].trc_timing/timing_cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[2].trc_timing/timing_cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[2].trc_timing/timing_cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[3].trc_timing/r_cnt_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[3].trc_timing/r_cnt_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[3].trc_timing/timing_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[3].trc_timing/timing_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[3].trc_timing/timing_cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[3].trc_timing/timing_cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[3].trc_timing/timing_cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[3].trc_timing/timing_cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[4].trc_timing/r_cnt_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[4].trc_timing/r_cnt_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[4].trc_timing/timing_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[4].trc_timing/timing_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[4].trc_timing/timing_cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[4].trc_timing/timing_cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[4].trc_timing/timing_cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[4].trc_timing/timing_cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[5].trc_timing/r_cnt_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[5].trc_timing/r_cnt_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[5].trc_timing/timing_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[5].trc_timing/timing_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[5].trc_timing/timing_cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[5].trc_timing/timing_cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[5].trc_timing/timing_cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[5].trc_timing/timing_cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[6].trc_timing/r_cnt_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[6].trc_timing/r_cnt_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[6].trc_timing/timing_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[6].trc_timing/timing_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[6].trc_timing/timing_cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[6].trc_timing/timing_cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[6].trc_timing/timing_cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[6].trc_timing/timing_cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[7].trc_timing/r_cnt_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[7].trc_timing/r_cnt_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[7].trc_timing/timing_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[7].trc_timing/timing_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[7].trc_timing/timing_cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[7].trc_timing/timing_cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[7].trc_timing/timing_cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[7].trc_timing/timing_cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/r_cnt_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/r_cnt_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/timing_cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/timing_cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/timing_cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/timing_cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/timing_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/timing_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/timing_cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/timing_cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/r_cnt_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/r_cnt_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/timing_cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/timing_cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/timing_cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/timing_cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/timing_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/timing_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/timing_cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/timing_cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/r_cnt_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/r_cnt_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/timing_cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/timing_cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/timing_cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/timing_cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/timing_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/timing_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/timing_cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/timing_cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/r_cnt_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/r_cnt_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/timing_cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/timing_cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/timing_cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/timing_cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/timing_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/timing_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/timing_cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/timing_cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/r_cnt_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/r_cnt_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/r_cnt_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/r_cnt_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/timing_cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/timing_cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/timing_cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/timing_cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/timing_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/timing_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/timing_cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/timing_cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/r_cnt_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/r_cnt_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/timing_cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/timing_cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/timing_cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/timing_cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/timing_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/timing_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/timing_cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/timing_cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/r_cnt_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/r_cnt_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/timing_cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/timing_cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/timing_cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/timing_cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/timing_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/timing_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/timing_cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/timing_cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/r_cnt_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/r_cnt_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/r_cnt_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/r_cnt_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/r_cnt_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/r_cnt_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/r_cnt_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/r_cnt_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/r_cnt_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/r_cnt_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/r_cnt_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/r_cnt_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/r_cnt_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/r_cnt_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/r_cnt_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/r_cnt_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[16]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[16]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[17]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[17]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[18]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[18]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[19]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[19]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[20]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[20]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[21]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[21]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[22]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[22]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[23]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[23]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[24]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[24]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[25]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[25]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[26]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[26]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[27]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[27]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[28]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[28]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[29]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[29]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[30]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[30]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[31]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[31]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[32]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[32]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[33]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[33]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[34]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[34]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[35]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[35]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[36]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[36]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[38]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[38]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[39]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[39]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[40]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[40]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[41]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[41]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[42]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_rdata_d1[42]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_valid_d1/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/back_valid_d1/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/cmd_act_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/cmd_act_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/ctrl_back_rdy/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/ctrl_back_rdy/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/cmd_rd_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/cmd_rd_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/r_cnt_almost_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/r_cnt_almost_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/r_cnt_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/r_cnt_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_cmd_accepted_l/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_cmd_accepted_l/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_cmd_accepted_m/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_cmd_accepted_m/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_cmd_act/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_cmd_act/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[16]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[16]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[17]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[17]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[18]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[18]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[19]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[19]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[20]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[20]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[21]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[21]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[22]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[22]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[23]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[23]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[24]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[24]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[25]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[25]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[26]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[26]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[27]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_addr[27]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_cmd[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_cmd[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_cmd[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_cmd[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_cmd[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_cmd[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_cmd[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_cmd[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_id[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_id[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_id[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_id[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_id[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_id[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_id[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/pipe_req_id[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[16]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[16]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[17]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[17]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[18]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[18]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[19]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[19]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[20]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[20]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[21]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[21]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[22]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[22]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[23]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[23]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[24]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[24]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[25]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[25]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[26]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[26]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[27]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[27]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[28]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[28]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[29]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[29]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[30]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[30]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[31]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[31]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[32]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[32]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[33]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[33]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[34]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[34]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[35]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[35]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[36]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[36]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[38]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[38]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[39]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[39]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[40]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[40]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[41]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[41]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[42]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[42]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_valid/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_valid/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/r_cnt_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/r_cnt_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/timing_cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/timing_cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/timing_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/timing_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/timing_cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/timing_cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/timing_cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[0].mcdq_tfaw/timing_cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[1].mcdq_tfaw/r_cnt_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[1].mcdq_tfaw/r_cnt_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[1].mcdq_tfaw/timing_cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[1].mcdq_tfaw/timing_cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[1].mcdq_tfaw/timing_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[1].mcdq_tfaw/timing_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[1].mcdq_tfaw/timing_cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[1].mcdq_tfaw/timing_cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[1].mcdq_tfaw/timing_cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[1].mcdq_tfaw/timing_cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/r_cnt_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/r_cnt_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/timing_cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/timing_cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/timing_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/timing_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/timing_cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/timing_cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/timing_cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/TFAW_LOOP[2].mcdq_tfaw/timing_cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/cnt_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/tfaw_timing/cnt_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/r_cnt_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/r_cnt_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/r_cnt_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/r_cnt_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt0[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt0[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt0[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt0[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt2[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt2[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt2[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt2[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt2[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt2[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt2[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt2[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/r_cnt_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/r_cnt_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/cmd_wr_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/cmd_wr_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/r_cnt_almost_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/r_cnt_almost_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/r_cnt_pass/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/r_cnt_pass/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/timing_cnt1[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/timing_cnt1[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/timing_cnt1[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/timing_cnt1[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_2/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_2/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_3/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_3/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_4/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_4/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_5/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_5/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_6/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_6/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_7/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_7/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_8/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_8/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_9/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_9/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_10/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_10/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_11/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_11/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_12/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_12/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_13/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_13/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_14/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_14/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_15/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_15/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_16/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_16/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_17/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_17/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_18/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_18/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_19/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_19/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_20/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_20/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_21/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_21/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_22/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_22/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_23/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_23/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_24/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_24/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_25/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_25/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_26/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_26/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_27/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_27/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_28/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_28/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_29/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_29/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_30/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_30/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_31/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_31/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_32/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_32/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_33/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_33/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_34/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_34/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_35/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_35/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_36/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_36/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_38/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_38/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_39/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_39/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_40/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_40/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_41/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_41/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_42/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_42/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.raddr_msb/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.raddr_msb/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_almost_full/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_almost_full/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_rempty/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_rempty/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_wfull/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_wfull/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.waddr_msb/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.waddr_msb/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/A_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_2/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_2/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_3/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_3/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_4/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_4/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_5/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_5/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_6/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_6/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_7/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_7/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_8/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_8/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_9/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_9/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_10/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_10/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_11/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_11/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_12/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_12/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_13/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_13/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_14/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_14/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_15/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_15/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_16/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_16/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_17/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_17/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_18/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_18/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_19/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_19/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_20/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_20/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_21/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_21/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_22/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_22/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_23/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_23/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_24/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_24/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_25/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_25/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_26/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_26/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_27/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_27/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_28/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_28/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_29/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_29/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_30/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_30/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_31/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_31/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_32/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_32/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_33/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_33/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_34/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_34/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_35/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_35/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_36/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_36/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_38/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_38/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_39/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_39/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_40/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_40/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_41/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_41/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_42/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_42/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.raddr_msb/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.raddr_msb/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_almost_full/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_almost_full/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_rempty/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_rempty/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_wfull/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_wfull/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.waddr_msb/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.waddr_msb/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/B_ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_a_valid/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_a_valid/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_b_valid/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_b_valid/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[16]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[16]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[17]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[17]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[18]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[18]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[19]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[19]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[20]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[20]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[21]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[21]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[22]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[22]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[23]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[23]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[24]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[24]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[25]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[25]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[26]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[26]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[27]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[27]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[28]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[28]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[29]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[29]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[30]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[30]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[31]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[31]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[32]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[32]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[33]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[33]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[34]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[34]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[35]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[35]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[36]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[36]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[38]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[38]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[39]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[39]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[40]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[40]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[41]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[41]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[42]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_a[42]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[16]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[16]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[17]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[17]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[18]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[18]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[19]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[19]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[20]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[20]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[21]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[21]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[22]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[22]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[23]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[23]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[24]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[24]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[25]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[25]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[26]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[26]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[27]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[27]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[28]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[28]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[29]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[29]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[30]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[30]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[31]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[31]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[32]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[32]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[33]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[33]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[34]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[34]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[35]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[35]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[36]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[36]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[38]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[38]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[39]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[39]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[40]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[40]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[41]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[41]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[42]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/fifo_rdata_b[42]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/poll/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/poll/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/rd_poll/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/rd_poll/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/rd_poll_d/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/rd_poll_d/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[16]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[16]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[17]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[17]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[18]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[18]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[19]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[19]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[20]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[20]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[21]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[21]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[22]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[22]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[23]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[23]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[24]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[24]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[25]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[25]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[26]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[26]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[27]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[27]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[28]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[28]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[29]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[29]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[30]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[30]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[31]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[31]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[32]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[32]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[33]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[33]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[34]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[34]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[35]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[35]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[36]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[36]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[38]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[38]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[39]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[39]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[40]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[40]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[41]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[41]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[42]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[42]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_valid/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_valid/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_l[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_l[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_l[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_l[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_l[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_l[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_l[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_m[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_m[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_m[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_m[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_m[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_baddr_m[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_l[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_cmd_m[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_l[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_l[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_l[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_l[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_l[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_l[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_l[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_l[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_m[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_m[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_m[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_m[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_m[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_m[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_m[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_id_m[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rvld/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rvld/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_wvld_l/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_wvld_l/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_wvld_m/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_wvld_m/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[16]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[16]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[17]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[17]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[18]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[18]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[19]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[19]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[20]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[20]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[21]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[21]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[22]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[22]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[23]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[23]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[24]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[24]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[25]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[25]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[26]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_address[26]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_bank[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_bank[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_bank[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_bank[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_bank[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_bank[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_bank[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_bank[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_bank[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_bank[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_bank[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_bank[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_cas_n[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_cas_n[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_cas_n[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_cas_n[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_cs_n[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_cs_n[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_cs_n[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_cs_n[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_odt_reg[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_odt_reg[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_odt_reg_1[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_odt_reg_1[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_ras_n[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_ras_n[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_ras_n[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_ras_n[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_we_n[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_we_n[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_we_n[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/dcp2dfi_we_n[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[16]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[16]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[17]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[17]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[18]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[18]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[19]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[19]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[20]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[20]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[21]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[21]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[22]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[22]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[23]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[23]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[24]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[24]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[25]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[25]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[26]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_address[26]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_bank[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_bank[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_bank[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_bank[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_bank[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_bank[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_bank[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_bank[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_bank[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_bank[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_bank[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_bank[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_cas_n[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_cas_n[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_cas_n[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_cas_n[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_cke[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_cke[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_cs_n[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_cs_n[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_cs_n[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_cs_n[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_odt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_odt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_odt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_odt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_ras_n[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_ras_n[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_ras_n[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_ras_n[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_we_n[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_we_n[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_we_n[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/mux_dfi_we_n[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/r_brd_m/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/r_brd_m/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/r_bwr_m/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dfi/r_bwr_m/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/fifo_vld/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/fifo_vld/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_0/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_0/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_2/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_2/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_3/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_3/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.raddr_msb/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.raddr_msb/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_rempty/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_rempty/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_wfull/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_wfull/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.waddr_msb/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.waddr_msb/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/rd_data_ff1[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/rd_data_ff1[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/rd_data_ff1[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/rd_data_ff1[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/rd_data_ff1[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/rd_data_ff1[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/rd_data_ff1[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/rd_data_ff1[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/double_wr/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/double_wr/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[16]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[16]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[17]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[17]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[18]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[18]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[19]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[19]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[20]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[20]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[21]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[21]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[22]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[22]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[23]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[23]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[24]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[24]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[25]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[25]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[26]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[26]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[27]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[27]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[28]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[28]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[29]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[29]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[30]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[30]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[31]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[31]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[32]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[32]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[33]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[33]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[34]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[34]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[35]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[35]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[37]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[37]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[16]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[16]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[17]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[17]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[18]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[18]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[19]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[19]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[20]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[20]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[21]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[21]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[22]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[22]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[23]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[23]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[24]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[24]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[25]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[25]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[26]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[26]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[27]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[27]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[28]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[28]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[29]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[29]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[30]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[30]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[31]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[31]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[32]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[32]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[33]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[33]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[34]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[34]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[35]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[35]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[37]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_1[37]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_valid_0/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_valid_0/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_valid_1/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_valid_1/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/rptr/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/rptr/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/next_len[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/next_len[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/next_len[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/next_len[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/next_len[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/next_len[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/next_len[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/next_len[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[0][14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[1][14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[2][14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[3][14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[4][14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[5][14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[6][14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/old_row_addr_array[7][14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[16]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[16]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[17]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[17]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[18]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[18]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[19]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[19]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[20]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[20]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[21]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[21]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[22]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[22]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[23]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[23]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[24]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[24]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[25]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[25]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[26]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[26]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[27]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_addr[27]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_data_in_valid/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_data_in_valid/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_id[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_id[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_id[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_id[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_id[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_id[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_id[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_id[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_len[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_len[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_len[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_len[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_len[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_len[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_len[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_len[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_write/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/pre_write/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/ptr/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/ptr/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[16]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[16]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[17]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[17]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[18]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[18]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[19]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[19]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[20]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[20]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[21]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[21]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[22]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[22]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[23]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[23]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[24]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[24]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[25]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[25]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[26]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[26]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[27]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[27]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[28]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[28]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[29]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[29]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[30]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[30]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[31]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[31]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[32]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[32]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[33]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[33]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[34]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[34]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[35]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[35]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[37]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[37]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[39]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[39]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[40]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[40]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[41]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[41]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[42]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[42]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[43]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[43]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[44]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[44]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[45]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[45]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[46]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[46]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[47]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[47]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[48]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[48]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[49]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[49]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[50]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[50]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[51]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[51]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[52]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[52]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[53]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[53]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[54]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_0[54]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[16]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[16]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[17]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[17]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[18]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[18]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[19]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[19]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[20]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[20]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[21]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[21]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[22]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[22]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[23]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[23]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[24]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[24]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[25]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[25]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[26]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[26]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[27]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[27]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[28]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[28]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[29]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[29]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[30]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[30]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[31]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[31]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[32]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[32]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[33]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[33]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[34]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[34]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[35]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[35]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[37]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[37]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[39]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[39]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[40]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[40]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[41]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[41]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[42]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[42]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[43]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[43]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[44]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[44]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[45]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[45]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[46]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[46]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[47]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[47]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[48]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[48]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[49]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[49]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[50]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[50]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[51]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[51]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[52]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[52]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[53]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[53]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[54]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_1[54]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_valid_0/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_valid_0/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_valid_1/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/data_valid_1/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/rptr/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/wptr/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/u_user_cmd_fifo/wptr/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/data_out[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/data_out[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/data_out[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/data_out[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_0/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_0/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/WCLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/WCLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.raddr_msb/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.raddr_msb/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.rptr[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_rempty/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_rempty/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_wfull/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.syn_wfull/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.waddr_msb/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.waddr_msb/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/u_ipsxb_distributed_fifo_ctr/SYN_CTRL.wptr[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mc3q_wdp_dcp/o_rdy/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mc3q_wdp_dcp/o_rdy/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mc3q_wdp_dcp/r_wvld[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mc3q_wdp_dcp/r_wvld[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[192]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[192]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[193]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[193]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[194]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[194]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[195]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[195]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[196]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[196]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[197]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[197]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[198]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[198]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[199]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[199]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[200]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[200]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[201]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[201]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[202]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[202]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[203]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[203]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[204]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[204]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[205]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[205]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[206]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[206]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[207]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[207]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[208]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[208]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[209]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[209]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[210]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[210]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[211]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[211]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[212]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[212]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[213]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[213]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[214]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[214]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[215]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[215]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[216]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[216]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[217]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[217]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[218]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[218]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[219]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[219]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[220]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[220]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[221]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[221]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[222]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[222]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[223]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[223]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[224]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[224]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[225]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[225]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[226]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[226]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[227]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[227]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[228]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[228]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[229]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[229]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[230]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[230]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[231]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[231]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[232]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[232]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[233]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[233]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[234]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[234]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[235]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[235]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[236]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[236]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[237]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[237]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[238]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[238]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[239]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[239]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[240]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[240]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[241]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[241]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[242]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[242]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[243]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[243]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[244]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[244]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[245]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[245]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[246]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[246]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[247]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[247]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[248]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[248]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[249]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[249]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[250]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[250]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[251]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[251]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[252]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[252]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[253]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[253]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[254]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[254]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[255]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/din_slip_dly[255]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[128]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[128]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[129]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[129]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[130]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[130]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[131]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[131]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[132]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[132]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[133]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[133]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[134]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[134]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[135]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[135]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[136]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[136]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[137]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[137]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[138]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[138]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[139]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[139]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[140]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[140]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[141]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[141]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[142]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[142]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[143]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[143]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[144]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[144]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[145]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[145]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[146]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[146]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[147]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[147]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[148]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[148]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[149]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[149]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[150]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[150]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[151]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[151]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[152]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[152]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[153]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[153]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[154]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[154]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[155]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[155]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[156]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[156]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[157]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[157]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[158]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[158]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[159]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[159]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[160]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[160]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[161]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[161]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[162]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[162]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[163]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[163]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[164]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[164]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[165]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[165]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[166]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[166]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[167]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[167]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[168]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[168]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[169]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[169]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[170]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[170]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[171]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[171]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[172]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[172]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[173]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[173]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[174]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[174]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[175]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[175]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[176]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[176]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[177]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[177]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[178]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[178]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[179]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[179]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[180]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[180]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[181]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[181]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[182]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[182]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[183]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[183]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[184]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[184]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[185]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[185]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[186]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[186]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[187]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[187]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[188]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[188]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[189]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[189]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[190]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[190]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[191]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[191]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[192]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[192]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[193]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[193]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[194]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[194]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[195]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[195]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[196]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[196]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[197]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[197]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[198]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[198]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[199]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[199]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[200]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[200]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[201]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[201]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[202]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[202]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[203]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[203]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[204]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[204]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[205]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[205]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[206]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[206]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[207]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[207]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[208]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[208]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[209]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[209]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[210]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[210]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[211]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[211]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[212]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[212]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[213]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[213]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[214]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[214]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[215]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[215]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[216]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[216]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[217]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[217]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[218]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[218]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[219]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[219]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[220]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[220]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[221]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[221]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[222]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[222]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[223]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[223]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[224]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[224]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[225]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[225]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[226]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[226]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[227]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[227]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[228]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[228]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[229]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[229]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[230]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[230]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[231]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[231]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[232]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[232]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[233]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[233]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[234]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[234]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[235]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[235]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[236]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[236]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[237]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[237]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[238]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[238]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[239]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[239]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[240]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[240]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[241]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[241]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[242]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[242]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[243]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[243]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[244]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[244]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[245]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[245]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[246]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[246]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[247]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[247]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[248]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[248]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[249]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[249]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[250]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[250]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[251]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[251]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[252]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[252]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[253]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[253]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[254]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[254]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[255]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_data[255]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_wdin_en[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_wdin_en[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_wvld_m/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/r_wvld_m/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wdin_en_dly[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wdin_en_dly[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[24]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wr_strb[24]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[16]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[16]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[17]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[17]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[18]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[18]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[19]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[19]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[20]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[20]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[21]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[21]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[22]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[22]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[23]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[23]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[24]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[24]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[25]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[25]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[26]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[26]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[27]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[27]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[28]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[28]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[29]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[29]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[30]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[30]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[31]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[31]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[32]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[32]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[33]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[33]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[34]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[34]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[35]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[35]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[36]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[36]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[37]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[37]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[38]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[38]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[39]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[39]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[40]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[40]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[41]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[41]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[42]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[42]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[43]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[43]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[44]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[44]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[45]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[45]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[46]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[46]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[47]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[47]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[48]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[48]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[49]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[49]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[50]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[50]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[51]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[51]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[52]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[52]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[53]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[53]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[54]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[54]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[55]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[55]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[56]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[56]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[57]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[57]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[58]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[58]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[59]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[59]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[60]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[60]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[61]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[61]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[62]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[62]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[63]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[63]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[64]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[64]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[65]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[65]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[66]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[66]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[67]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[67]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[68]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[68]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[69]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[69]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[70]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[70]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[71]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[71]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[72]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[72]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[73]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[73]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[74]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[74]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[75]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[75]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[76]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[76]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[77]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[77]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[78]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[78]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[79]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[79]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[80]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[80]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[81]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[81]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[82]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[82]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[83]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[83]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[84]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[84]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[85]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[85]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[86]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[86]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[87]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[87]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[88]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[88]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[89]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[89]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[90]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[90]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[91]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[91]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[92]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[92]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[93]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[93]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[94]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[94]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[95]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[95]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[96]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[96]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[97]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[97]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[98]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[98]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[99]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[99]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[100]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[100]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[101]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[101]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[102]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[102]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[103]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[103]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[104]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[104]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[105]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[105]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[106]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[106]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[107]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[107]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[108]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[108]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[109]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[109]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[110]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[110]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[111]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[111]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[112]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[112]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[113]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[113]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[114]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[114]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[115]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[115]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[116]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[116]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[117]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[117]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[118]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[118]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[119]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[119]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[120]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[120]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[121]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[121]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[122]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[122]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[123]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[123]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[124]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[124]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[125]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[125]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[126]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[126]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[127]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[127]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[128]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[128]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[129]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[129]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[130]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[130]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[131]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[131]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[132]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[132]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[133]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[133]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[134]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[134]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[135]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[135]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[136]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[136]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[137]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[137]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[138]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[138]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[139]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[139]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[140]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[140]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[141]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[141]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[142]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[142]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[143]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[143]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[144]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[144]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[145]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[145]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[146]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[146]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[147]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[147]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[148]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[148]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[149]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[149]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[150]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[150]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[151]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[151]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[152]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[152]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[153]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[153]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[154]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[154]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[155]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[155]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[156]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[156]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[157]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[157]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[158]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[158]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[159]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[159]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[160]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[160]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[161]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[161]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[162]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[162]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[163]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[163]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[164]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[164]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[165]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[165]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[166]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[166]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[167]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[167]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[168]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[168]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[169]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[169]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[170]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[170]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[171]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[171]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[172]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[172]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[173]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[173]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[174]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[174]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[175]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[175]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[176]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[176]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[177]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[177]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[178]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[178]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[179]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[179]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[180]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[180]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[181]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[181]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[182]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[182]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[183]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[183]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[184]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[184]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[185]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[185]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[186]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[186]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[187]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[187]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[188]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[188]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[189]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[189]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[190]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[190]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[191]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[191]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[192]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[192]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[193]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[193]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[194]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[194]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[195]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[195]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[196]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[196]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[197]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[197]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[198]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[198]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[199]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[199]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[200]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[200]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[201]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[201]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[202]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[202]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[203]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[203]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[204]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[204]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[205]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[205]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[206]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[206]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[207]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[207]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[208]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[208]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[209]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[209]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[210]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[210]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[211]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[211]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[212]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[212]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[213]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[213]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[214]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[214]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[215]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[215]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[216]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[216]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[217]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[217]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[218]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[218]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[219]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[219]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[220]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[220]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[221]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[221]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[222]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[222]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[223]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[223]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[224]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[224]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[225]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[225]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[226]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[226]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[227]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[227]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[228]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[228]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[229]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[229]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[230]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[230]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[231]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[231]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[232]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[232]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[233]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[233]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[234]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[234]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[235]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[235]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[236]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[236]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[237]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[237]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[238]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[238]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[239]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[239]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[240]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[240]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[241]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[241]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[242]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[242]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[243]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[243]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[244]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[244]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[245]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[245]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[246]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[246]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[247]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[247]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[248]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[248]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[249]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[249]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[250]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[250]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[251]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[251]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[252]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[252]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[253]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[253]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[254]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[254]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[255]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata[255]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata_en[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata_en[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata_en[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wrdata_en[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/usr_wdp_rdy_dly/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/usr_wdp_rdy_dly/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/axi_fifo_full0/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/axi_fifo_full0/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/cnt0_times[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/cnt0_times[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/cnt0_times[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/cnt0_times[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/cnt0_times[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/cnt0_times[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/cnt0_times[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/cnt0_times[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/cnt0_times[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/cnt0_times[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/cnt0_times[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/cnt0_times[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/cnt0_times[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/cnt0_times[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/cnt0_times[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/cnt0_times[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/cnt0_times[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/cnt0_times[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/cnt1_times[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/cnt1_times[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/cnt1_times[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/cnt1_times[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/cnt1_times[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/cnt1_times[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/cnt1_times[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/cnt1_times[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/cnt1_times[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/cnt1_times[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/cnt1_times[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/cnt1_times[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/cnt1_times[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/cnt1_times[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/cnt1_times[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/cnt1_times[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/cnt1_times[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/cnt1_times[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/cnt_wr_num[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/cnt_wr_num[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/cnt_wr_num[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/cnt_wr_num[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/cnt_wr_num[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/cnt_wr_num[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/delay_cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/delay_cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/delay_cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/delay_cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/delay_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/delay_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/delay_cnt[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/delay_cnt[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/delay_cnt[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/delay_cnt[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_addr_start_fall/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_addr_start_fall/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_addr_start_valid0/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_addr_start_valid0/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_addr_start_valid1/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_addr_start_valid1/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_cnt_num[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_cnt_num[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_cnt_num[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_cnt_num[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_cnt_num[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_cnt_num[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_cnt_num[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_cnt_num[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_cnt_num[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_cnt_num[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_cnt_num[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_cnt_num[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_cnt_num[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_cnt_num[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_cnt_num[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_cnt_num[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_cnt_num[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_cnt_num[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_cnt_num[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_cnt_num[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_cnt_num[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_cnt_num[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_cnt_num[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_cnt_num[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_cnt_num[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_cnt_num[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_cnt_num[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_cnt_num[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_cnt_num[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_cnt_num[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_cnt_num[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_cnt_num[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_done0/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_done0/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_done1/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_done1/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr0[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr0[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr0[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr0[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr0[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr0[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr0[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr0[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr0[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr0[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr0[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr0[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr0[16]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr0[16]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr0[17]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr0[17]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr0[18]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr0[18]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr0[19]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr0[19]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr0[20]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr0[20]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr0[21]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr0[21]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr0[22]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr0[22]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr0[23]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr0[23]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr0[24]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr0[24]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr0[25]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr0[25]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr0[26]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr0[26]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr0[27]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr0[27]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr0[28]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr0[28]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr0[29]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr0[29]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr1[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr1[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr1[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr1[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr1[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr1[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr1[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr1[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr1[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr1[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr1[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr1[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr1[16]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr1[16]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr1[17]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr1[17]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr1[18]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr1[18]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr1[19]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr1[19]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr1[20]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr1[20]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr1[21]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr1[21]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr1[22]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr1[22]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr1[23]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr1[23]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr1[24]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr1[24]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr1[25]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr1[25]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr1[26]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr1[26]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr1[27]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr1[27]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr1[28]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr1[28]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr1[29]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr1[29]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr2[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr2[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr2[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr2[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr2[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr2[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr2[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr2[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr2[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr2[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr2[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr2[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr2[16]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr2[16]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr2[17]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr2[17]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr2[18]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr2[18]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr2[19]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr2[19]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr2[20]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr2[20]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr2[21]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr2[21]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr2[22]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr2[22]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr2[23]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr2[23]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr2[24]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr2[24]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr2[25]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr2[25]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr2[26]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr2[26]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr2[27]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr2[27]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr2[28]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr2[28]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_ddr_sart_addr2[29]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_ddr_sart_addr2[29]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_done_cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_done_cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_done_cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_done_cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_done_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_done_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd0_time_permit/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd0_time_permit/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_addr_start_fall/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_addr_start_fall/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_addr_start_valid0/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_addr_start_valid0/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_addr_start_valid1/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_addr_start_valid1/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_cnt_num[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_cnt_num[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_cnt_num[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_cnt_num[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_cnt_num[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_cnt_num[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_cnt_num[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_cnt_num[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_cnt_num[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_cnt_num[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_cnt_num[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_cnt_num[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_cnt_num[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_cnt_num[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_cnt_num[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_cnt_num[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_cnt_num[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_cnt_num[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_cnt_num[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_cnt_num[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_cnt_num[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_cnt_num[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_cnt_num[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_cnt_num[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_cnt_num[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_cnt_num[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_cnt_num[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_cnt_num[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_cnt_num[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_cnt_num[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_cnt_num[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_cnt_num[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_done0/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_done0/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_done1/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_done1/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr0[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr0[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr0[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr0[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr0[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr0[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr0[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr0[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr0[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr0[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr0[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr0[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr0[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr0[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr0[16]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr0[16]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr0[17]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr0[17]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr0[18]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr0[18]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr0[19]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr0[19]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr0[20]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr0[20]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr0[21]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr0[21]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr0[22]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr0[22]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr0[23]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr0[23]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr0[24]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr0[24]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr1[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr1[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr1[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr1[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr1[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr1[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr1[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr1[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr1[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr1[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr1[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr1[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr1[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr1[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr1[16]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr1[16]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr1[17]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr1[17]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr1[18]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr1[18]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr1[19]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr1[19]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr1[20]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr1[20]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr1[21]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr1[21]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr1[22]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr1[22]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr1[23]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr1[23]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr1[24]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr1[24]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr2[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr2[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr2[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr2[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr2[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr2[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr2[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr2[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr2[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr2[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr2[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr2[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr2[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr2[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr2[16]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr2[16]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr2[17]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr2[17]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr2[18]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr2[18]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr2[19]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr2[19]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr2[20]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr2[20]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr2[21]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr2[21]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr2[22]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr2[22]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr2[23]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr2[23]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_ddr_sart_addr2[24]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_ddr_sart_addr2[24]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_done_cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_done_cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_done_cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_done_cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_done_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_done_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd1_time_permit/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd1_time_permit/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd3_data_en0/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd3_data_en0/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd3_data_en1/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd3_data_en1/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd3_data_en2/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd3_data_en2/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd3_ddr_data[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd3_ddr_data[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd3_ddr_data[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd3_ddr_data[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd3_ddr_data[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd3_ddr_data[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd3_ddr_data[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd3_ddr_data[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd3_ddr_data[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd3_ddr_data[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd3_ddr_data[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd3_ddr_data[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd3_ddr_data[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd3_ddr_data[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd3_ddr_data[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd3_ddr_data[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd3_ddr_data[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd3_ddr_data[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd3_ddr_data[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd3_ddr_data[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd3_ddr_data[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd3_ddr_data[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd3_ddr_data[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd3_ddr_data[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd3_ddr_data[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd3_ddr_data[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd3_ddr_data[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd3_ddr_data[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd3_ddr_data[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd3_ddr_data[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd3_ddr_data[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd3_ddr_data[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd_all_full/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd_all_full/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd_ddr_idle/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd_ddr_idle/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd_importance/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd_importance/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd_sta0_reg0/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd_sta0_reg0/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd_sta0_reg1/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd_sta0_reg1/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd_sta2_reg0/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd_sta2_reg0/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd_sta2_reg1/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd_sta2_reg1/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd_sta_reg[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd_sta_reg[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd_sta_reg[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd_sta_reg[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd_sta_reg[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd_sta_reg[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd_sta_reg[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd_sta_reg[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd_sta_reg[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd_sta_reg[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd_sta_reg[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd_sta_reg[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd_sta_reg[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd_sta_reg[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd_wr_fast_empty/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd_wr_fast_empty/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rd_wr_fifo_empty/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rd_wr_fifo_empty/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/record_addr_valid/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/record_addr_valid/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/record_araddr_valid/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/record_araddr_valid/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/record_data_valid/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/record_data_valid/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rst0/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rst0/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rx_rd0_addr_valid/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rx_rd0_addr_valid/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/rx_rd1_addr_valid/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/rx_rd1_addr_valid/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_araddr[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_araddr[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_araddr[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_araddr[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_araddr[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_araddr[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_araddr[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_araddr[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_araddr[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_araddr[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_araddr[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_araddr[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_araddr[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_araddr[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_araddr[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_araddr[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_araddr[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_araddr[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_araddr[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_araddr[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_araddr[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_araddr[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_araddr[16]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_araddr[16]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_araddr[17]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_araddr[17]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_araddr[18]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_araddr[18]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_araddr[19]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_araddr[19]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_araddr[20]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_araddr[20]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_araddr[21]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_araddr[21]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_araddr[22]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_araddr[22]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_araddr[23]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_araddr[23]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_araddr[24]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_araddr[24]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_araddr[25]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_araddr[25]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_araddr[26]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_araddr[26]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_araddr[27]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_araddr[27]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_araddr[28]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_araddr[28]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_araddr[29]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_araddr[29]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_arid[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_arid[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_arid[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_arid[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_arid[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_arid[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_arid[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_arid[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_arlen[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_arlen[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[16]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[16]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[17]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[17]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[18]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[18]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[19]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[19]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[20]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[20]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[21]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[21]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[22]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[22]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[23]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[23]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[24]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[24]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[25]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[25]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[26]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[26]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[27]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[27]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[28]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[28]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[29]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[29]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[30]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[30]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[31]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[31]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[32]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[32]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[33]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[33]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[34]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[34]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[35]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[35]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[36]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[36]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[37]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[37]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[38]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[38]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[39]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[39]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[40]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[40]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[41]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[41]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[42]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[42]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[43]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[43]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[44]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[44]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[45]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[45]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[46]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[46]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[47]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[47]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[48]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[48]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[49]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[49]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[50]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[50]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[51]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[51]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[52]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[52]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[53]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[53]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[54]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[54]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[55]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[55]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[56]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[56]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[57]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[57]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[58]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[58]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[59]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[59]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[60]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[60]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[61]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[61]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[62]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[62]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[63]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[63]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[64]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[64]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[65]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[65]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[66]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[66]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[67]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[67]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[68]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[68]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[69]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[69]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[70]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[70]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[71]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[71]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[72]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[72]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[73]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[73]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[74]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[74]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[75]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[75]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[76]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[76]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[77]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[77]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[78]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[78]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[79]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[79]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[80]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[80]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[81]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[81]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[82]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[82]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[83]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[83]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[84]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[84]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[85]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[85]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[86]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[86]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[87]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[87]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[88]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[88]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[89]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[89]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[90]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[90]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[91]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[91]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[92]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[92]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[93]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[93]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[94]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[94]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[95]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[95]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[96]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[96]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[97]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[97]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[98]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[98]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[99]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[99]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[100]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[100]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[101]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[101]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[102]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[102]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[103]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[103]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[104]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[104]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[105]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[105]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[106]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[106]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[107]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[107]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[108]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[108]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[109]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[109]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[110]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[110]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[111]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[111]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[112]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[112]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[113]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[113]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[114]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[114]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[115]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[115]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[116]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[116]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[117]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[117]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[118]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[118]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[119]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[119]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[120]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[120]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[121]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[121]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[122]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[122]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[123]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[123]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[124]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[124]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[125]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[125]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[126]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[126]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[127]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[127]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[128]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[128]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[129]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[129]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[130]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[130]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[131]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[131]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[132]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[132]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[133]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[133]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[134]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[134]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[135]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[135]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[136]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[136]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[137]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[137]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[138]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[138]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[139]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[139]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[140]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[140]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[141]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[141]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[142]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[142]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[143]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[143]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[144]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[144]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[145]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[145]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[146]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[146]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[147]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[147]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[148]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[148]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[149]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[149]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[150]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[150]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[151]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[151]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[152]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[152]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[153]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[153]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[154]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[154]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[155]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[155]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[156]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[156]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[157]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[157]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[158]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[158]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[159]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[159]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[160]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[160]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[161]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[161]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[162]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[162]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[163]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[163]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[164]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[164]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[165]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[165]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[166]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[166]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[167]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[167]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[168]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[168]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[169]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[169]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[170]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[170]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[171]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[171]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[172]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[172]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[173]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[173]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[174]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[174]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[175]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[175]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[176]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[176]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[177]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[177]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[178]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[178]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[179]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[179]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[180]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[180]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[181]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[181]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[182]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[182]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[183]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[183]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[184]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[184]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[185]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[185]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[186]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[186]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[187]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[187]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[188]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[188]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[189]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[189]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[190]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[190]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[191]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[191]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[192]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[192]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[193]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[193]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[194]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[194]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[195]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[195]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[196]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[196]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[197]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[197]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[198]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[198]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[199]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[199]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[200]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[200]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[201]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[201]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[202]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[202]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[203]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[203]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[204]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[204]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[205]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[205]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[206]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[206]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[207]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[207]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[208]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[208]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[209]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[209]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[210]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[210]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[211]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[211]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[212]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[212]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[213]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[213]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[214]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[214]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[215]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[215]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[216]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[216]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[217]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[217]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[218]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[218]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[219]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[219]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[220]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[220]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[221]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[221]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[222]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[222]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[223]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[223]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[224]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[224]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[225]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[225]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[226]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[226]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[227]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[227]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[228]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[228]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[229]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[229]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[230]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[230]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[231]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[231]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[232]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[232]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[233]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[233]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[234]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[234]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[235]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[235]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[236]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[236]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[237]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[237]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[238]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[238]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[239]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[239]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[240]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[240]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[241]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[241]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[242]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[242]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[243]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[243]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[244]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[244]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[245]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[245]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[246]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[246]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[247]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[247]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[248]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[248]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[249]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[249]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[250]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[250]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[251]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[251]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[252]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[252]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[253]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[253]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[254]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[254]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata0[255]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata0[255]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[16]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[16]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[17]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[17]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[18]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[18]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[19]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[19]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[20]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[20]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[21]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[21]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[22]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[22]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[23]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[23]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[24]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[24]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[25]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[25]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[26]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[26]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[27]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[27]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[28]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[28]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[29]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[29]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[30]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[30]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[31]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[31]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[32]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[32]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[33]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[33]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[34]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[34]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[35]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[35]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[36]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[36]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[37]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[37]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[38]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[38]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[39]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[39]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[40]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[40]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[41]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[41]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[42]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[42]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[43]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[43]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[44]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[44]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[45]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[45]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[46]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[46]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[47]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[47]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[48]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[48]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[49]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[49]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[50]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[50]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[51]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[51]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[52]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[52]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[53]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[53]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[54]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[54]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[55]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[55]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[56]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[56]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[57]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[57]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[58]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[58]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[59]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[59]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[60]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[60]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[61]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[61]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[62]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[62]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[63]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[63]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[64]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[64]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[65]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[65]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[66]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[66]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[67]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[67]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[68]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[68]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[69]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[69]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[70]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[70]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[71]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[71]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[72]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[72]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[73]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[73]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[74]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[74]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[75]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[75]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[76]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[76]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[77]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[77]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[78]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[78]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[79]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[79]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[80]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[80]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[81]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[81]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[82]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[82]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[83]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[83]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[84]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[84]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[85]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[85]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[86]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[86]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[87]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[87]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[88]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[88]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[89]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[89]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[90]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[90]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[91]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[91]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[92]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[92]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[93]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[93]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[94]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[94]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[95]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[95]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[96]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[96]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[97]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[97]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[98]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[98]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[99]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[99]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[100]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[100]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[101]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[101]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[102]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[102]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[103]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[103]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[104]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[104]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[105]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[105]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[106]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[106]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[107]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[107]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[108]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[108]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[109]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[109]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[110]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[110]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[111]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[111]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[112]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[112]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[113]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[113]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[114]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[114]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[115]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[115]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[116]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[116]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[117]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[117]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[118]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[118]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[119]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[119]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[120]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[120]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[121]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[121]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[122]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[122]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[123]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[123]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[124]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[124]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[125]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[125]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[126]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[126]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[127]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[127]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[128]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[128]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[129]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[129]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[130]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[130]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[131]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[131]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[132]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[132]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[133]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[133]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[134]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[134]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[135]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[135]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[136]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[136]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[137]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[137]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[138]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[138]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[139]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[139]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[140]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[140]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[141]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[141]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[142]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[142]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[143]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[143]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[144]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[144]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[145]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[145]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[146]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[146]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[147]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[147]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[148]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[148]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[149]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[149]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[150]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[150]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[151]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[151]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[152]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[152]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[153]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[153]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[154]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[154]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[155]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[155]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[156]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[156]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[157]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[157]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[158]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[158]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[159]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[159]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[160]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[160]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[161]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[161]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[162]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[162]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[163]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[163]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[164]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[164]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[165]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[165]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[166]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[166]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[167]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[167]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[168]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[168]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[169]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[169]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[170]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[170]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[171]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[171]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[172]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[172]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[173]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[173]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[174]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[174]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[175]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[175]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[176]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[176]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[177]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[177]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[178]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[178]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[179]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[179]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[180]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[180]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[181]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[181]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[182]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[182]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[183]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[183]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[184]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[184]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[185]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[185]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[186]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[186]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[187]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[187]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[188]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[188]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[189]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[189]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[190]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[190]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[191]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[191]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[192]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[192]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[193]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[193]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[194]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[194]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[195]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[195]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[196]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[196]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[197]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[197]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[198]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[198]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[199]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[199]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[200]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[200]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[201]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[201]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[202]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[202]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[203]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[203]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[204]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[204]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[205]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[205]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[206]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[206]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[207]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[207]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[208]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[208]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[209]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[209]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[210]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[210]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[211]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[211]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[212]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[212]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[213]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[213]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[214]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[214]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[215]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[215]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[216]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[216]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[217]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[217]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[218]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[218]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[219]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[219]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[220]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[220]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[221]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[221]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[222]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[222]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[223]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[223]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[224]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[224]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[225]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[225]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[226]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[226]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[227]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[227]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[228]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[228]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[229]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[229]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[230]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[230]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[231]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[231]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[232]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[232]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[233]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[233]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[234]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[234]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[235]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[235]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[236]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[236]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[237]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[237]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[238]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[238]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[239]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[239]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[240]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[240]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[241]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[241]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[242]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[242]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[243]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[243]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[244]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[244]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[245]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[245]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[246]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[246]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[247]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[247]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[248]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[248]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[249]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[249]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[250]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[250]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[251]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[251]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[252]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[252]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[253]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[253]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[254]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[254]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/s_axi_rdata1[255]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/s_axi_rdata1[255]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/switch_data0[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/switch_data0[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/switch_data0[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/switch_data0[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/switch_data0[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/switch_data0[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/switch_data0[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/switch_data0[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKB (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKB (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKB (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKB (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM18K/CLKB (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM18K/CLKB (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[3].U_GTP_DRM18K/CLKB (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[3].U_GTP_DRM18K/CLKB (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKB (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_awaddr_ddr_fifo/U_ipml_fifo_awaddr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKB (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/cnt_times[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/cnt_times[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/cnt_times[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/cnt_times[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/cnt_times[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/cnt_times[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/cnt_times[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/cnt_times[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/cnt_times[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/cnt_times[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/cnt_times[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/cnt_times[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/cnt_times[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/cnt_times[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/cnt_times[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/cnt_times[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/ddr_fifo_full0/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/ddr_fifo_full0/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/rd0_fifo_empty0/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/rd0_fifo_empty0/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/rd0_fifo_full0/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/rd0_fifo_full0/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/rd1_fifo_full0/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/rd1_fifo_full0/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/rd_ddr_valid/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/rd_ddr_valid/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/rd_sta_reg[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/rd_sta_reg[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/rd_sta_reg[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/rd_sta_reg[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/rd_sta_reg[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/rd_sta_reg[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/rd_sta_reg[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/rd_sta_reg[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/rid_dout0[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/rid_dout0[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/rid_dout0[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/rid_dout0[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/rid_valid_cnt[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/rid_valid_cnt[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/rid_valid_cnt[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/rid_valid_cnt[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/rid_valid_cnt[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/rid_valid_cnt[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/CLKA (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/CLKA (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/CLKB (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/CLKB (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wr_water_level[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wr_water_level[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wr_water_level[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wr_water_level[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wr_water_level[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wr_water_level[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wr_water_level[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wr_water_level[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wr_water_level[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wr_water_level[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wr_water_level[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wr_water_level[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wr_water_level[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wr_water_level[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wr_water_level[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wr_water_level[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wr_water_level[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wr_water_level[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wr_water_level[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wr_water_level[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd0_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wr_water_level[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wr_water_level[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wr_water_level[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wr_water_level[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/wrptr2[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKA (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKA (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKB (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKB (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKA (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKA (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKB (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKB (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM18K/CLKA (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM18K/CLKA (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM18K/CLKB (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM18K/CLKB (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[3].U_GTP_DRM18K/CLKA (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[3].U_GTP_DRM18K/CLKA (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[3].U_GTP_DRM18K/CLKB (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[3].U_GTP_DRM18K/CLKB (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[4].U_GTP_DRM18K/CLKA (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[4].U_GTP_DRM18K/CLKA (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[4].U_GTP_DRM18K/CLKB (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[4].U_GTP_DRM18K/CLKB (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[5].U_GTP_DRM18K/CLKA (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[5].U_GTP_DRM18K/CLKA (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[5].U_GTP_DRM18K/CLKB (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[5].U_GTP_DRM18K/CLKB (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[6].U_GTP_DRM18K/CLKA (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[6].U_GTP_DRM18K/CLKA (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[6].U_GTP_DRM18K/CLKB (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[6].U_GTP_DRM18K/CLKB (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[7].U_GTP_DRM18K/CLKA (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[7].U_GTP_DRM18K/CLKA (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[7].U_GTP_DRM18K/CLKB (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_rd_connect/u_rd_ddr_fifo/U_ipml_fifo_rd_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[7].U_GTP_DRM18K/CLKB (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_addr0[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_addr0[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_addr0[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_addr0[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_addr0[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_addr0[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_addr0[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_addr0[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_addr0[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_addr0[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_addr0[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_addr0[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_addr0[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_addr0[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_addr0[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_addr0[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_addr0[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_addr0[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_addr0[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_addr0[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_addr0[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_addr0[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_addr0[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_addr0[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_addr0[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_addr0[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_addr0[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_addr0[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_addr0[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_addr0[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_addr0[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_addr0[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_addr0[16]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_addr0[16]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_addr0[17]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_addr0[17]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_addr0[18]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_addr0[18]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_addr0[19]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_addr0[19]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_addr_valid0/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_addr_valid0/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[16]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[16]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[17]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[17]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[18]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[18]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[19]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[19]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[20]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[20]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[21]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[21]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[22]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[22]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[23]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[23]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[24]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[24]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[25]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[25]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[26]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[26]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[27]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[27]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[28]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[28]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[29]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[29]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[30]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[30]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[31]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[31]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[32]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[32]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[33]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[33]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[34]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[34]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[35]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[35]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[36]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[36]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[37]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[37]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[38]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[38]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[39]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[39]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[40]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[40]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[41]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[41]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[42]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[42]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[43]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[43]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[44]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[44]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[45]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[45]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[46]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[46]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[47]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[47]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[48]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[48]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[49]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[49]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[50]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[50]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[51]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[51]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[52]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[52]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[53]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[53]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[54]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[54]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[55]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[55]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[56]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[56]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[57]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[57]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[58]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[58]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[59]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[59]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[60]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[60]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[61]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[61]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[62]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[62]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[63]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_out0[63]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/axi_data_valid0/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/axi_data_valid0/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/cnt_times[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/cnt_times[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/cnt_times[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/cnt_times[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/cnt_times[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/cnt_times[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/cnt_times[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/cnt_times[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/cnt_times[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/cnt_times[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/cnt_times[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/cnt_times[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/cnt_times[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/cnt_times[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/ddr0_valid_fall0/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/ddr0_valid_fall0/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/ddr0_valid_fall2/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/ddr0_valid_fall2/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/ddr1_valid_fall0/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/ddr1_valid_fall0/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/ddr1_valid_fall2/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/ddr1_valid_fall2/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/ddr3_valid_fall0/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/ddr3_valid_fall0/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/ddr3_valid_fall2/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/ddr3_valid_fall2/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/delay_cnt0[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/delay_cnt0[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/delay_cnt0[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/delay_cnt0[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/delay_cnt0[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/delay_cnt0[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/delay_cnt1[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/delay_cnt1[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/delay_cnt1[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/delay_cnt1[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/delay_cnt1[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/delay_cnt1[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/delay_cnt3[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/delay_cnt3[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/delay_cnt3[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/delay_cnt3[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/delay_cnt3[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/delay_cnt3[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/fifo0_data_full/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/fifo0_data_full/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/fifo1_data_full/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/fifo1_data_full/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/fifo3_data_full/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/fifo3_data_full/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKB (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKB (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKB (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo0/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKB (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKB (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKB (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKB (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKB (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rwptr2[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKB (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKB (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKB (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKB (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/rd_sta0[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/rd_sta0[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/rd_sta0[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/rd_sta0[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/rd_sta0[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/rd_sta0[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/rd_sta0[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/rd_sta0[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/rd_sta0[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/rd_sta0[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/rd_sta0[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/rd_sta0[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/rd_sta0[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/rd_sta0[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/rd_sta_reg[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/rx0_addr_valid/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/rx0_addr_valid/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/rx1_addr_valid/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/rx1_addr_valid/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/rx3_addr_valid/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/rx3_addr_valid/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr0_cnt_num[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_done0/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_done0/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_done1/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_done1/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr0[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr0[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr0[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr0[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr0[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr0[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr0[16]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr0[16]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr0[17]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr0[17]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr1[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr1[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr1[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr1[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr1[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr1[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr1[16]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr1[16]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr1[17]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr1[17]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr2[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr2[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr2[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr2[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr2[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr2[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr2[16]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr2[16]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr2[17]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr2[17]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr_valid0/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr_valid0/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr_valid1/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr_valid1/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr_valid2/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr0_ddr_sart_addr_valid2/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr1_cnt_num[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_done0/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_done0/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_done1/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_done1/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr0[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr0[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr0[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr0[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr0[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr0[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr0[16]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr0[16]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr0[17]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr0[17]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr1[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr1[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr1[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr1[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr1[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr1[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr1[16]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr1[16]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr1[17]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr1[17]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr2[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr2[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr2[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr2[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr2[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr2[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr2[16]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr2[16]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr2[17]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr2[17]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr_valid0/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr_valid0/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr_valid1/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr_valid1/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr_valid2/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr1_ddr_sart_addr_valid2/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[12]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[12]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr3_cnt_num[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_done0/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_done0/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_done1/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_done1/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr0[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr0[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr0[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr0[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr0[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr0[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr1[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr1[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr1[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr1[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr1[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr1[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr2[13]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr2[13]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr2[14]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr2[14]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr2[15]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr2[15]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr_valid0/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr_valid0/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr_valid1/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr_valid1/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr_valid2/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_axi_wr_connect/wr3_ddr_sart_addr_valid2/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_fifo_ctrl/rwptr2[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/CLKB (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_low_araddr_fifo/U_ipml_fifo_low_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/CLKB (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wr_water_level[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wr_water_level[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wr_water_level[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wr_water_level[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wr_water_level[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wr_water_level[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wr_water_level[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wr_water_level[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wr_water_level[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wr_water_level[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wr_water_level[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wr_water_level[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wr_water_level[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wr_water_level[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wr_water_level[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wr_water_level[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wrptr2[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/CLKA (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/CLKA (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.rbin[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/SYN_CTRL.wbin[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[4]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[4]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[5]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[5]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[6]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[6]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[7]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[7]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[8]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[8]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[9]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[9]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[10]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[10]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[11]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[11]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKB (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKB (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKA (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKA (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKB (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKB (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM18K/CLKA (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM18K/CLKA (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM18K/CLKB (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM18K/CLKB (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[3].U_GTP_DRM18K/CLKA (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[3].U_GTP_DRM18K/CLKA (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[3].U_GTP_DRM18K/CLKB (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[3].U_GTP_DRM18K/CLKB (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[4].U_GTP_DRM18K/CLKA (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[4].U_GTP_DRM18K/CLKA (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[4].U_GTP_DRM18K/CLKB (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[4].U_GTP_DRM18K/CLKB (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[5].U_GTP_DRM18K/CLKA (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[5].U_GTP_DRM18K/CLKA (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[5].U_GTP_DRM18K/CLKB (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[5].U_GTP_DRM18K/CLKB (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[6].U_GTP_DRM18K/CLKA (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[6].U_GTP_DRM18K/CLKA (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[6].U_GTP_DRM18K/CLKB (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[6].U_GTP_DRM18K/CLKB (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[7].U_GTP_DRM18K/CLKA (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[7].U_GTP_DRM18K/CLKA (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[7].U_GTP_DRM18K/CLKB (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[7].U_GTP_DRM18K/CLKB (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/wr_sta_idle/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/wr_sta_idle/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/wr_sta_reg[0]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/wr_sta_reg[0]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/wr_sta_reg[1]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/wr_sta_reg[1]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/wr_sta_reg[2]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/wr_sta_reg[2]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/wr_sta_reg[3]/CLK (9.059, 9.059, 9.157, 9.157) + u_axi_ddr_top/wr_sta_reg[3]/CLK (7.688, 7.688, 7.786, 7.786) - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKIN (5.913, 5.913, 6.011, 6.011) + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKIN (4.542, 4.542, 4.640, 4.640) ioclk0 (400.00MHZ) (drive 11 loads) - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (6.219, 6.219, 6.317, 6.317) + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (4.848, 4.848, 4.946, 4.946) u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] (net) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[1].u_ddc_ca/CLKA (6.990, 6.990, 7.088, 7.088) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[1].u_ddc_ca/CLKA (5.619, 5.619, 5.717, 5.717) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[3].u_ddc_ca/CLKA (6.990, 6.990, 7.088, 7.088) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[3].u_ddc_ca/CLKA (5.619, 5.619, 5.717, 5.717) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/DESCLK (6.990, 6.990, 7.088, 7.088) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/DESCLK (5.619, 5.619, 5.717, 5.717) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[1].DQ0_GTP_ISERDES/DESCLK (6.990, 6.990, 7.088, 7.088) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[1].DQ0_GTP_ISERDES/DESCLK (5.619, 5.619, 5.717, 5.717) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[2].DQ0_GTP_ISERDES/DESCLK (6.990, 6.990, 7.088, 7.088) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[2].DQ0_GTP_ISERDES/DESCLK (5.619, 5.619, 5.717, 5.717) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[3].DQ0_GTP_ISERDES/DESCLK (6.990, 6.990, 7.088, 7.088) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[3].DQ0_GTP_ISERDES/DESCLK (5.619, 5.619, 5.717, 5.717) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[4].DQ0_GTP_ISERDES/DESCLK (6.990, 6.990, 7.088, 7.088) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[4].DQ0_GTP_ISERDES/DESCLK (5.619, 5.619, 5.717, 5.717) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[5].DQ0_GTP_ISERDES/DESCLK (6.990, 6.990, 7.088, 7.088) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[5].DQ0_GTP_ISERDES/DESCLK (5.619, 5.619, 5.717, 5.717) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[6].DQ0_GTP_ISERDES/DESCLK (6.990, 6.990, 7.088, 7.088) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[6].DQ0_GTP_ISERDES/DESCLK (5.619, 5.619, 5.717, 5.717) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[7].DQ0_GTP_ISERDES/DESCLK (6.990, 6.990, 7.088, 7.088) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[7].DQ0_GTP_ISERDES/DESCLK (5.619, 5.619, 5.717, 5.717) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/CLKA (6.990, 6.990, 7.088, 7.088) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/CLKA (5.619, 5.619, 5.717, 5.717) - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKIN (5.913, 5.913, 6.011, 6.011) + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKIN (4.542, 4.542, 4.640, 4.640) ioclk1 (400.00MHZ) (drive 27 loads) - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (6.219, 6.219, 6.317, 6.317) + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (4.848, 4.848, 4.946, 4.946) u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] (net) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/DESCLK (7.137, 7.137, 7.235, 7.235) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/DESCLK (5.766, 5.766, 5.864, 5.864) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[1].DQ0_GTP_ISERDES/DESCLK (7.137, 7.137, 7.235, 7.235) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[1].DQ0_GTP_ISERDES/DESCLK (5.766, 5.766, 5.864, 5.864) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[2].DQ0_GTP_ISERDES/DESCLK (7.137, 7.137, 7.235, 7.235) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[2].DQ0_GTP_ISERDES/DESCLK (5.766, 5.766, 5.864, 5.864) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[3].DQ0_GTP_ISERDES/DESCLK (7.137, 7.137, 7.235, 7.235) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[3].DQ0_GTP_ISERDES/DESCLK (5.766, 5.766, 5.864, 5.864) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[4].DQ0_GTP_ISERDES/DESCLK (7.137, 7.137, 7.235, 7.235) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[4].DQ0_GTP_ISERDES/DESCLK (5.766, 5.766, 5.864, 5.864) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[5].DQ0_GTP_ISERDES/DESCLK (7.137, 7.137, 7.235, 7.235) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[5].DQ0_GTP_ISERDES/DESCLK (5.766, 5.766, 5.864, 5.864) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[6].DQ0_GTP_ISERDES/DESCLK (7.137, 7.137, 7.235, 7.235) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[6].DQ0_GTP_ISERDES/DESCLK (5.766, 5.766, 5.864, 5.864) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[7].DQ0_GTP_ISERDES/DESCLK (7.137, 7.137, 7.235, 7.235) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[7].DQ0_GTP_ISERDES/DESCLK (5.766, 5.766, 5.864, 5.864) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/CLKA (7.137, 7.137, 7.235, 7.235) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/CLKA (5.766, 5.766, 5.864, 5.864) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/DESCLK (7.137, 7.137, 7.235, 7.235) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/DESCLK (5.766, 5.766, 5.864, 5.864) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[1].DQ0_GTP_ISERDES/DESCLK (7.137, 7.137, 7.235, 7.235) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[1].DQ0_GTP_ISERDES/DESCLK (5.766, 5.766, 5.864, 5.864) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[2].DQ0_GTP_ISERDES/DESCLK (7.137, 7.137, 7.235, 7.235) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[2].DQ0_GTP_ISERDES/DESCLK (5.766, 5.766, 5.864, 5.864) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[3].DQ0_GTP_ISERDES/DESCLK (7.137, 7.137, 7.235, 7.235) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[3].DQ0_GTP_ISERDES/DESCLK (5.766, 5.766, 5.864, 5.864) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[4].DQ0_GTP_ISERDES/DESCLK (7.137, 7.137, 7.235, 7.235) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[4].DQ0_GTP_ISERDES/DESCLK (5.766, 5.766, 5.864, 5.864) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[5].DQ0_GTP_ISERDES/DESCLK (7.137, 7.137, 7.235, 7.235) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[5].DQ0_GTP_ISERDES/DESCLK (5.766, 5.766, 5.864, 5.864) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[6].DQ0_GTP_ISERDES/DESCLK (7.137, 7.137, 7.235, 7.235) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[6].DQ0_GTP_ISERDES/DESCLK (5.766, 5.766, 5.864, 5.864) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[7].DQ0_GTP_ISERDES/DESCLK (7.137, 7.137, 7.235, 7.235) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dq_loop[7].DQ0_GTP_ISERDES/DESCLK (5.766, 5.766, 5.864, 5.864) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/u_ddc_dqs/CLKA (7.137, 7.137, 7.235, 7.235) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/u_ddc_dqs/CLKA (5.766, 5.766, 5.864, 5.864) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/DESCLK (7.137, 7.137, 7.235, 7.235) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/DESCLK (5.766, 5.766, 5.864, 5.864) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[1].DQ0_GTP_ISERDES/DESCLK (7.137, 7.137, 7.235, 7.235) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[1].DQ0_GTP_ISERDES/DESCLK (5.766, 5.766, 5.864, 5.864) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[2].DQ0_GTP_ISERDES/DESCLK (7.137, 7.137, 7.235, 7.235) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[2].DQ0_GTP_ISERDES/DESCLK (5.766, 5.766, 5.864, 5.864) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[3].DQ0_GTP_ISERDES/DESCLK (7.137, 7.137, 7.235, 7.235) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[3].DQ0_GTP_ISERDES/DESCLK (5.766, 5.766, 5.864, 5.864) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[4].DQ0_GTP_ISERDES/DESCLK (7.137, 7.137, 7.235, 7.235) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[4].DQ0_GTP_ISERDES/DESCLK (5.766, 5.766, 5.864, 5.864) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[5].DQ0_GTP_ISERDES/DESCLK (7.137, 7.137, 7.235, 7.235) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[5].DQ0_GTP_ISERDES/DESCLK (5.766, 5.766, 5.864, 5.864) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[6].DQ0_GTP_ISERDES/DESCLK (7.137, 7.137, 7.235, 7.235) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[6].DQ0_GTP_ISERDES/DESCLK (5.766, 5.766, 5.864, 5.864) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[7].DQ0_GTP_ISERDES/DESCLK (7.137, 7.137, 7.235, 7.235) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dq_loop[7].DQ0_GTP_ISERDES/DESCLK (5.766, 5.766, 5.864, 5.864) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/u_ddc_dqs/CLKA (7.137, 7.137, 7.235, 7.235) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/u_ddc_dqs/CLKA (5.766, 5.766, 5.864, 5.864) @@ -43352,19 +43408,19 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT1 (5.303, 5.303, 5.402, 5.402) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT1 (3.932, 3.932, 4.031, 4.031) u_axi_ddr_top/I_ipsxb_ddr_top/ioclk_gate_clk_pll (net) - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg_gate/CLKIN (5.767, 5.767, 5.866, 5.866) + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg_gate/CLKIN (4.396, 4.396, 4.495, 4.495) ioclk_gate_clk (100.00MHZ) (drive 1 loads) - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg_gate/CLKOUT (5.767, 5.767, 5.866, 5.866) + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg_gate/CLKOUT (4.396, 4.396, 4.495, 4.495) u_axi_ddr_top/I_ipsxb_ddr_top/ioclk_gate_clk (net) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_ioclk_gate/CLK (7.963, 7.963, 8.062, 8.062) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_ioclk_gate/CLK (6.592, 6.592, 6.691, 6.691) @@ -43374,24 +43430,24 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_1/u_pll_e3/CLKIN1 (5.214, 5.214, 5.314, 5.314) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_1/u_pll_e3/CLKIN1 (3.843, 3.843, 3.943, 3.943) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_1/u_pll_e3/CLKOUT0 (5.308, 5.308, 5.406, 5.406) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_1/u_pll_e3/CLKOUT0 (3.937, 3.937, 4.035, 4.035) u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [1] (net) - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_2/CLKIN (5.772, 5.772, 5.870, 5.870) + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_2/CLKIN (4.401, 4.401, 4.499, 4.499) ioclk2 (400.00MHZ) (drive 2 loads) - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_2/CLKOUT (6.078, 6.078, 6.176, 6.176) + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_2/CLKOUT (4.707, 4.707, 4.805, 4.805) u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [2] (net) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_ddc_ca/CLKA (6.631, 6.631, 6.729, 6.729) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_ddc_ca/CLKA (5.260, 5.260, 5.358, 5.358) - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[2].u_ddc_ca/CLKA (6.631, 6.631, 6.729, 6.729) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[2].u_ddc_ca/CLKA (5.260, 5.260, 5.358, 5.358) @@ -43404,3418 +43460,886 @@ - u_axi_ddr_top/u_axi_rd_connect/rd1_data_valid0/CLK (4.367, 4.367, 4.467, 4.467) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/CLK (4.367, 4.367, 4.467, 4.467) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[2]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[3]/CLK (4.367, 4.367, 4.467, 4.467) + u_axi_rst/rst/CLK (2.996, 2.996, 3.096, 3.096) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[4]/CLK (4.367, 4.367, 4.467, 4.467) + u_axi_rst/rst0/CLK (2.996, 2.996, 3.096, 3.096) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[5]/CLK (4.367, 4.367, 4.467, 4.467) + u_axi_rst/rst1/CLK (2.996, 2.996, 3.096, 3.096) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[6]/CLK (4.367, 4.367, 4.467, 4.467) + u_ddr_rst/rst/CLK (2.996, 2.996, 3.096, 3.096) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[7]/CLK (4.367, 4.367, 4.467, 4.467) + u_ddr_rst/rst0/CLK (2.996, 2.996, 3.096, 3.096) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[8]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[9]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[10]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rbin[11]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[2]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[3]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[4]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[5]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[6]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[7]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[8]/CLK (4.367, 4.367, 4.467, 4.467) + u_ddr_rst/rst1/CLK (2.996, 2.996, 3.096, 3.096) + + + + + clk_25m (25.00MHZ) (drive 26 loads) + + u_sys_pll/u_pll_e3/CLKOUT3 (2.400, 2.400, 2.499, 2.499) + + clk_25m (net) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[9]/CLK (4.367, 4.367, 4.467, 4.467) + u_ov5640/coms1_reg_config/clk_20k_regdiv/CLK (3.113, 3.113, 3.212, 3.212) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[10]/CLK (4.367, 4.367, 4.467, 4.467) + u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/CLK (3.113, 3.113, 3.212, 3.212) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rptr[11]/CLK (4.367, 4.367, 4.467, 4.467) + u_ov5640/coms1_reg_config/clock_20k_cnt[0]/CLK (3.113, 3.113, 3.212, 3.212) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/CLK (4.367, 4.367, 4.467, 4.467) + u_ov5640/coms1_reg_config/clock_20k_cnt[1]/CLK (3.113, 3.113, 3.212, 3.212) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/CLK (4.367, 4.367, 4.467, 4.467) + u_ov5640/coms1_reg_config/clock_20k_cnt[2]/CLK (3.113, 3.113, 3.212, 3.212) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[2]/CLK (4.367, 4.367, 4.467, 4.467) + u_ov5640/coms1_reg_config/clock_20k_cnt[3]/CLK (3.113, 3.113, 3.212, 3.212) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[3]/CLK (4.367, 4.367, 4.467, 4.467) + u_ov5640/coms1_reg_config/clock_20k_cnt[4]/CLK (3.113, 3.113, 3.212, 3.212) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[4]/CLK (4.367, 4.367, 4.467, 4.467) + u_ov5640/coms1_reg_config/clock_20k_cnt[5]/CLK (3.113, 3.113, 3.212, 3.212) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[5]/CLK (4.367, 4.367, 4.467, 4.467) + u_ov5640/coms1_reg_config/clock_20k_cnt[6]/CLK (3.113, 3.113, 3.212, 3.212) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[6]/CLK (4.367, 4.367, 4.467, 4.467) + u_ov5640/coms1_reg_config/clock_20k_cnt[7]/CLK (3.113, 3.113, 3.212, 3.212) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[7]/CLK (4.367, 4.367, 4.467, 4.467) + u_ov5640/coms1_reg_config/clock_20k_cnt[8]/CLK (3.113, 3.113, 3.212, 3.212) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[8]/CLK (4.367, 4.367, 4.467, 4.467) + u_ov5640/coms1_reg_config/clock_20k_cnt[9]/CLK (3.113, 3.113, 3.212, 3.212) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[9]/CLK (4.367, 4.367, 4.467, 4.467) + u_ov5640/coms1_reg_config/clock_20k_cnt[10]/CLK (3.113, 3.113, 3.212, 3.212) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[0]/CLK (4.367, 4.367, 4.467, 4.467) + u_ov5640/coms2_reg_config/clk_20k_regdiv/CLK (3.113, 3.113, 3.212, 3.212) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[1]/CLK (4.367, 4.367, 4.467, 4.467) + u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite/CLK (3.113, 3.113, 3.212, 3.212) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[2]/CLK (4.367, 4.367, 4.467, 4.467) + u_ov5640/coms2_reg_config/clock_20k_cnt[0]/CLK (3.113, 3.113, 3.212, 3.212) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[3]/CLK (4.367, 4.367, 4.467, 4.467) + u_ov5640/coms2_reg_config/clock_20k_cnt[1]/CLK (3.113, 3.113, 3.212, 3.212) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[4]/CLK (4.367, 4.367, 4.467, 4.467) + u_ov5640/coms2_reg_config/clock_20k_cnt[2]/CLK (3.113, 3.113, 3.212, 3.212) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[5]/CLK (4.367, 4.367, 4.467, 4.467) + u_ov5640/coms2_reg_config/clock_20k_cnt[3]/CLK (3.113, 3.113, 3.212, 3.212) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[6]/CLK (4.367, 4.367, 4.467, 4.467) + u_ov5640/coms2_reg_config/clock_20k_cnt[4]/CLK (3.113, 3.113, 3.212, 3.212) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[7]/CLK (4.367, 4.367, 4.467, 4.467) + u_ov5640/coms2_reg_config/clock_20k_cnt[5]/CLK (3.113, 3.113, 3.212, 3.212) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[8]/CLK (4.367, 4.367, 4.467, 4.467) + u_ov5640/coms2_reg_config/clock_20k_cnt[6]/CLK (3.113, 3.113, 3.212, 3.212) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_fifo_ctrl/rwptr2[9]/CLK (4.367, 4.367, 4.467, 4.467) + u_ov5640/coms2_reg_config/clock_20k_cnt[7]/CLK (3.113, 3.113, 3.212, 3.212) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKB (4.881, 4.881, 4.981, 4.981) + u_ov5640/coms2_reg_config/clock_20k_cnt[8]/CLK (3.113, 3.113, 3.212, 3.212) - u_axi_ddr_top/u_axi_rd_connect/u_rd1_fifo/U_ipml_fifo_rd0_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKB (4.881, 4.881, 4.981, 4.981) + u_ov5640/coms2_reg_config/clock_20k_cnt[9]/CLK (3.113, 3.113, 3.212, 3.212) - u_axi_rst/rst/CLK (4.367, 4.367, 4.467, 4.467) + u_ov5640/coms2_reg_config/clock_20k_cnt[10]/CLK (3.113, 3.113, 3.212, 3.212) + + + + + clk_10m (10.00MHZ) (drive 256 loads) + + u_sys_pll/u_pll_e3/CLKOUT4 (2.396, 2.396, 2.495, 2.495) + + clk_10m (net) - u_axi_rst/rst0/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/busy/CLK (3.510, 3.510, 3.609, 3.609) - u_axi_rst/rst1/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/byte_over/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/rd1_vs0/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/data_out[0]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/delay_cnt[0]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/data_out[1]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/delay_cnt[1]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/data_out[2]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/delay_cnt[2]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/data_out[3]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/gen_start_addr3[19]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/data_out[4]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/gen_start_addr3[20]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/data_out[5]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/gen_start_addr3[21]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/data_out[6]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_addr[7]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/data_out[7]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_addr[8]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/fre_cnt[0]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_addr[9]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/fre_cnt[1]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_addr[10]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/fre_cnt[2]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_addr[11]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/fre_cnt[3]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_addr[12]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/fre_cnt[4]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_addr[13]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/pluse_1d/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_addr[14]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/pluse_2d/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_addr[15]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/pluse_3d/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_addr[16]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/receiv_data[0]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_addr[17]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/receiv_data[1]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_addr[18]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/receiv_data[2]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_addr[19]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/receiv_data[3]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_h[1]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/receiv_data[4]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_h[2]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/receiv_data[5]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_h[3]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/receiv_data[6]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_h[4]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/receiv_data[7]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_h[5]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/scl_out/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_h[6]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/sda_out/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_h[7]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/send_data[0]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_h[8]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/send_data[1]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_h[9]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/send_data[2]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/mult_h[10]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/send_data[3]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd1_sta_reg[0]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/send_data[4]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd1_sta_reg[1]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/send_data[5]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd1_sta_reg[2]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/send_data[6]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd3_image_cnt[0]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/send_data[7]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd3_image_cnt[1]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/start_en/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd3_image_cnt[2]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/state_reg[0]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[7]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/state_reg[1]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[8]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/state_reg[2]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[9]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/state_reg[3]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[10]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/state_reg[4]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[11]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/state_reg[5]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[12]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/state_reg[6]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[13]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/trans_bit[0]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[14]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/trans_bit[1]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[15]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/trans_bit[2]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[16]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/trans_byte[0]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[17]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/trans_byte[1]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[18]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/trans_byte[2]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[19]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/trans_byte[3]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[20]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/trans_byte_max[0]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[21]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/trans_byte_max[2]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[22]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/trans_en/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_done0/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/twr_cnt[0]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_done1/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/twr_cnt[1]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_done2/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/twr_cnt[2]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_valid0/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/twr_cnt[3]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_valid1/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/twr_en/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_vs0/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/w_r_1d/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_vs1/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_rx/w_r_2d/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/rd_vs_rise0/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/busy/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.rbin[0]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/byte_over/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/data_out[0]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.rbin[2]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/data_out[1]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.rbin[3]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/data_out[2]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.rbin[4]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/data_out[3]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.rbin[5]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/data_out[4]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.rbin[6]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/data_out[5]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.rbin[7]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/data_out[6]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.rbin[8]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/data_out[7]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.syn_rempty/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/pluse_1d/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/pluse_2d/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.wbin[0]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/pluse_3d/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.wbin[1]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/receiv_data[0]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.wbin[2]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/receiv_data[1]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.wbin[3]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/receiv_data[2]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.wbin[4]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/receiv_data[3]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.wbin[5]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/receiv_data[4]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.wbin[6]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/receiv_data[5]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.wbin[7]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/receiv_data[6]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.wbin[8]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/receiv_data[7]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/CLKA (4.881, 4.881, 4.981, 4.981) + ms72xx_ctl/iic_dri_tx/scl_out/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/CLKB (4.881, 4.881, 4.981, 4.981) + ms72xx_ctl/iic_dri_tx/sda_out/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/data_in0[0]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/send_data[0]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/data_in0[1]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/send_data[1]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/data_in0[2]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/send_data[2]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/data_in1[0]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/send_data[3]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/data_in1[1]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/send_data[4]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/data_in1[2]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/send_data[5]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/data_in2[0]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/send_data[6]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/data_in2[1]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/send_data[7]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/data_in2[2]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/start_en/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/data_in3[0]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/state_reg[0]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/data_in3[1]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/state_reg[1]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/data_in3[2]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/state_reg[2]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_async_to_rd2_sync/data_vary0/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/state_reg[3]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_image_fram_cnt1[0]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/state_reg[4]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_image_fram_cnt1[1]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/state_reg[5]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_addr_ctr/u_rd1_addr_ctr/wr3_image_fram_cnt1[2]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/state_reg[6]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_rst/rst/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/trans_bit[0]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_rst/rst0/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/trans_bit[1]/CLK (3.510, 3.510, 3.609, 3.609) - u_ddr_rst/rst1/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/trans_bit[2]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/trans_byte[0]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/trans_byte[1]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[1]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/trans_byte[2]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[2]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/trans_byte[3]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[3]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/trans_byte_max[0]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[4]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/trans_byte_max[2]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[5]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/trans_en/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[6]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/twr_cnt[0]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[7]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/twr_cnt[1]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[8]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/twr_cnt[2]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[9]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/twr_cnt[3]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[10]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/twr_en/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[11]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/w_r_1d/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[12]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/iic_dri_tx/w_r_2d/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[13]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/CLKA (4.024, 4.024, 4.123, 4.123) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[14]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/CLKB (4.024, 4.024, 4.123, 4.123) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[15]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/addr[0]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/addr[1]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/addr[2]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[2]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/addr[3]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[3]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/addr[4]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[4]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/addr[5]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[5]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/addr[6]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[6]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/addr[7]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[7]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/addr[8]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/addr[9]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/addr[12]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/addr[13]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[11]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/busy_1d/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[12]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/cmd_index[0]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[13]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/cmd_index[1]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[14]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/cmd_index[2]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[15]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/cmd_index[3]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/cmd_index[4]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/cmd_index[5]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/cmd_index[6]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[3]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/cmd_index[7]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[4]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/cmd_index[8]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[5]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/data_in[0]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[6]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/data_in[1]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[7]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/data_in[2]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[8]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/data_in[3]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[9]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/data_in[4]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[10]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/data_in[5]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[11]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/data_in[6]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[12]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/data_in[7]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[13]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/dri_cnt[0]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[14]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/dri_cnt[1]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[15]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/dri_cnt[2]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[5]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/dri_cnt[3]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[6]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/dri_cnt[4]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[7]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/dri_cnt[5]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[8]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/dri_cnt[6]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[9]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/dri_cnt[7]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[10]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/dri_cnt[8]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[11]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/freq_ensure/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[12]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/freq_rec_1d[16]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[0]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/freq_rec_1d[17]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[1]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/freq_rec_2d[16]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[2]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/freq_rec_2d[17]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[3]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/freq_rec[16]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[4]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/freq_rec[17]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[5]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/iic_trig/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[6]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/init_over/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[7]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/state_reg[0]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[8]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/state_reg[1]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[9]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/state_reg[2]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[10]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/state_reg[3]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[11]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/state_reg[4]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[12]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7200_ctl/w_r/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[13]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7210_ctl/N325_1_concat_2/CLKA (4.024, 4.024, 4.123, 4.123) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[14]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7210_ctl/N325_1_concat_2/CLKB (4.024, 4.024, 4.123, 4.123) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[15]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7210_ctl/addr[0]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) + ms72xx_ctl/ms7210_ctl/addr[1]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) + ms72xx_ctl/ms7210_ctl/addr[2]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) + ms72xx_ctl/ms7210_ctl/addr[3]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[3].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) + ms72xx_ctl/ms7210_ctl/addr[4]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[4].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) + ms72xx_ctl/ms7210_ctl/addr[5]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[5].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) + ms72xx_ctl/ms7210_ctl/addr[6]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[6].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) + ms72xx_ctl/ms7210_ctl/addr[7]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[7].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) + ms72xx_ctl/ms7210_ctl/addr[8]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[8].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) + ms72xx_ctl/ms7210_ctl/addr[9]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[9].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) + ms72xx_ctl/ms7210_ctl/addr[10]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[10].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) + ms72xx_ctl/ms7210_ctl/addr[11]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[11].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) + ms72xx_ctl/ms7210_ctl/busy_1d/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[12].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) + ms72xx_ctl/ms7210_ctl/cmd_index[0]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[13].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) + ms72xx_ctl/ms7210_ctl/cmd_index[1]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[14].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) + ms72xx_ctl/ms7210_ctl/cmd_index[2]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[15].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) + ms72xx_ctl/ms7210_ctl/cmd_index[3]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[0].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) + ms72xx_ctl/ms7210_ctl/cmd_index[4]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[1].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) + ms72xx_ctl/ms7210_ctl/cmd_index[5]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[2].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) + ms72xx_ctl/ms7210_ctl/data_in[0]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[3].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) + ms72xx_ctl/ms7210_ctl/data_in[1]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[4].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) + ms72xx_ctl/ms7210_ctl/data_in[2]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[5].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) + ms72xx_ctl/ms7210_ctl/data_in[3]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[6].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) + ms72xx_ctl/ms7210_ctl/data_in[4]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[7].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) + ms72xx_ctl/ms7210_ctl/data_in[5]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[8].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) + ms72xx_ctl/ms7210_ctl/data_in[6]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[9].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) + ms72xx_ctl/ms7210_ctl/data_in[7]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[10].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) + ms72xx_ctl/ms7210_ctl/delay_cnt[0]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[11].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) + ms72xx_ctl/ms7210_ctl/delay_cnt[1]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[12].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) + ms72xx_ctl/ms7210_ctl/delay_cnt[2]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[13].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) + ms72xx_ctl/ms7210_ctl/delay_cnt[3]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[14].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) + ms72xx_ctl/ms7210_ctl/delay_cnt[4]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[1].DATA_LOOP[15].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) + ms72xx_ctl/ms7210_ctl/delay_cnt[5]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/addr_sta_reg[0]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7210_ctl/delay_cnt[6]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/addr_sta_reg[1]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7210_ctl/delay_cnt[7]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/addr_sta_reg[2]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7210_ctl/delay_cnt[8]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/addr_sta_reg[3]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7210_ctl/delay_cnt[9]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/addr_sta_reg[4]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7210_ctl/delay_cnt[10]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/cnt_h[0]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7210_ctl/delay_cnt[11]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/cnt_h[1]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7210_ctl/delay_cnt[12]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/cnt_h[2]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7210_ctl/delay_cnt[13]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/cnt_h[3]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7210_ctl/delay_cnt[14]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/cnt_h[4]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7210_ctl/delay_cnt[15]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/cnt_h[5]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7210_ctl/delay_cnt[16]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/cnt_h[6]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7210_ctl/delay_cnt[17]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/cnt_h[7]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7210_ctl/delay_cnt[18]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/cnt_h[8]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7210_ctl/delay_cnt[19]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/cnt_h[9]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7210_ctl/delay_cnt[20]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/cnt_h[10]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7210_ctl/delay_cnt[21]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/cnt_record_ram[0]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7210_ctl/dri_cnt[0]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/cnt_record_ram[1]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7210_ctl/dri_cnt[1]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/cnt_record_ram[2]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7210_ctl/dri_cnt[2]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/cnt_w[0]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7210_ctl/dri_cnt[3]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/cnt_w[1]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7210_ctl/dri_cnt[4]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/cnt_w[2]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7210_ctl/iic_trig/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/cnt_w[3]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7210_ctl/init_over/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/cnt_w[4]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7210_ctl/state_reg[1]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/cnt_w[5]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7210_ctl/state_reg[2]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/cnt_w[6]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7210_ctl/state_reg[3]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/cnt_w[7]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7210_ctl/state_reg[4]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/cnt_w[8]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7210_ctl/state_reg[5]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/cnt_w[9]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/ms7210_ctl/w_r/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/cnt_w[10]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/rstn/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/coe_valid[0]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/rstn_temp1/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/coe_valid[1]/CLK (4.367, 4.367, 4.467, 4.467) + ms72xx_ctl/rstn_temp2/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/coe_valid[2]/CLK (4.367, 4.367, 4.467, 4.467) + rstn_1ms[0]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/coe_valid[3]/CLK (4.367, 4.367, 4.467, 4.467) + rstn_1ms[1]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/data_in0[0]/CLK (4.367, 4.367, 4.467, 4.467) + rstn_1ms[2]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/data_in0[1]/CLK (4.367, 4.367, 4.467, 4.467) + rstn_1ms[3]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/data_in0[2]/CLK (4.367, 4.367, 4.467, 4.467) + rstn_1ms[4]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/data_in0[3]/CLK (4.367, 4.367, 4.467, 4.467) + rstn_1ms[5]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/data_in0[4]/CLK (4.367, 4.367, 4.467, 4.467) + rstn_1ms[6]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/data_in0[5]/CLK (4.367, 4.367, 4.467, 4.467) + rstn_1ms[7]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/data_in0[6]/CLK (4.367, 4.367, 4.467, 4.467) + rstn_1ms[8]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/data_in0[7]/CLK (4.367, 4.367, 4.467, 4.467) + rstn_1ms[9]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/data_in0[8]/CLK (4.367, 4.367, 4.467, 4.467) + rstn_1ms[10]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/data_in0[9]/CLK (4.367, 4.367, 4.467, 4.467) + rstn_1ms[11]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/data_in0[10]/CLK (4.367, 4.367, 4.467, 4.467) + rstn_1ms[12]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/data_in0[11]/CLK (4.367, 4.367, 4.467, 4.467) + rstn_1ms[13]/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/data_in0[12]/CLK (4.367, 4.367, 4.467, 4.467) + rstn_out0/CLK (3.510, 3.510, 3.609, 3.609) - u_zoom_image/data_in0[13]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/data_in0[14]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/data_in0[15]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/data_in_valid0/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/data_out1[0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/data_out1[1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/data_out1[2]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/data_out1[3]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/data_out1[4]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/data_out1[5]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/data_out1[6]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/data_out1[7]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/data_out1[8]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/data_out1[9]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/data_out1[10]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/data_out1[11]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/data_out1[12]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/data_out1[13]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/data_out1[14]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/data_out1[15]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/data_out2[0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/data_out2[1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/data_out2[2]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/data_out2[3]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/data_out2[4]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/data_out2[5]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/data_out2[6]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/data_out2[7]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/data_out2[8]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/data_out2[9]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/data_out2[10]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/data_out2[11]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/data_out2[12]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/data_out2[13]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/data_out2[14]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/data_out2[15]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/data_out_valid1/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/data_out_valid2/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/delay_cnt[0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/delay_cnt[1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/delay_cnt[2]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/fifo_full0/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/imag_addr0[0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/imag_addr0[1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/imag_addr0[2]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/imag_addr0[3]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/imag_addr0[4]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/imag_addr0[5]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/imag_addr0[6]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/imag_addr0[7]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/imag_addr0[8]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/imag_addr0[9]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/imag_addr1[0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/imag_addr1[1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/imag_addr1[2]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/imag_addr1[3]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/imag_addr1[4]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/imag_addr1[5]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/imag_addr1[6]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/imag_addr1[7]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/imag_addr1[8]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/imag_addr1[9]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/imag_addr_valid0/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/imag_addr_valid1/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h0[0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h0[1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h0[2]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h0[3]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h0[4]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h0[5]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h0[6]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h0[7]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h0[8]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h0[9]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h0[10]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h0[11]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h0[12]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h0[13]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h0[14]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h0[15]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h0[16]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h0[17]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h0[18]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h0[19]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h0[20]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h1[0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h1[1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h1[2]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h1[3]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h1[4]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h1[5]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h1[6]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h1[7]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h1[8]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h1[9]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h1[10]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h1[11]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h1[12]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h1[13]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h1[14]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h1[15]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h1[16]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h1[17]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h1[18]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h1[19]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h1[20]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h2[0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h2[1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h2[2]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h2[3]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h2[4]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h2[5]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h2[6]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h2[7]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h2[8]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h2[9]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h2[10]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h2[11]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h2[12]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h2[13]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h2[14]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h2[15]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h2[16]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h2[17]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h2[18]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h2[19]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h2[20]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h2_coe0[0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h2_coe0[1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h2_coe0[2]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h2_coe0[3]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h2_coe0[4]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h2_coe0[5]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h2_coe0[6]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h2_coe1[0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h2_coe1[1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h2_coe1[2]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h2_coe1[3]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h2_coe1[4]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h2_coe1[5]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h2_coe1[6]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h2_coe[0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h2_coe[1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h2_coe[2]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h2_coe[3]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h2_coe[4]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h2_coe[5]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h2_coe[6]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h_valid[0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_h_valid[1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_valid[0][0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_valid[0][1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_valid[1][0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_valid[1][1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_valid[2][0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_valid[2][1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_valid[3][0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_valid[3][1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_valid[4][0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_valid[4][1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_valid[5][0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_valid[5][1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_valid[6][0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_valid[6][1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w1[0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w1[1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w1[2]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w1[3]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w1[4]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w1[5]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w1[6]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w1[7]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w1[8]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w1[9]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w1[10]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w1[11]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w1[12]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w1[13]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w1[14]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w1[15]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w1[16]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w1[17]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w1[18]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w1[19]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w1[20]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w2[0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w2[1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w2[2]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w2[3]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w2[4]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w2[5]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w2[6]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w2[15]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w2[16]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w2[17]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w2[18]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w2[19]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w2[20]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w2_coe0[0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w2_coe0[1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w2_coe0[2]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w2_coe0[3]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w2_coe0[4]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w2_coe0[5]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w2_coe0[6]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w2_coe1[0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w2_coe1[1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w2_coe1[2]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w2_coe1[3]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w2_coe1[4]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w2_coe1[5]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w2_coe1[6]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w2_coe[0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w2_coe[1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w2_coe[2]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w2_coe[3]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w2_coe[4]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w2_coe[5]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w2_coe[6]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w_valid[0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/image_w_valid[1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/judge_cnt_h[0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/judge_cnt_h[1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/judge_cnt_h[2]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/judge_cnt_h[3]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/judge_cnt_h[4]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/judge_cnt_h[5]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/judge_cnt_h[6]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/judge_cnt_h[7]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/judge_cnt_h[8]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/judge_cnt_h[9]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/judge_cnt_h[10]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/judge_cnt_h[11]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/judge_cnt_h[12]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/judge_cnt_h[13]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/judge_cnt_h_valid/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/mult_fra0/N2/CLK (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/mult_fra0_0/N2/CLK (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/mult_fra1/N2/CLK (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/mult_fra1_0/N2/CLK (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/mult_h0[0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/mult_h0[1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/mult_h0[2]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/mult_h0[3]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/mult_h0[4]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/mult_h0[5]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/mult_h0[6]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/mult_h0[7]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/mult_h0[8]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/mult_h0[9]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/mult_h0[10]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/mult_h0[11]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/mult_h0[12]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/mult_h0[13]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/mult_image2[0][7]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/mult_image2[0][8]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/mult_image2[0][9]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/mult_image2[0][10]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/mult_image2[0][11]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/mult_image2[1][7]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/mult_image2[1][8]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/mult_image2[1][9]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/mult_image2[1][10]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/mult_image2[1][11]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/mult_image2[1][12]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/mult_image2[2][7]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/mult_image2[2][8]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/mult_image2[2][9]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/mult_image2[2][10]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/mult_image2[2][11]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/mult_image_b0/N2/CLK (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/mult_image_b0_0/N2/CLK (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/mult_image_b1/N2/CLK (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/mult_image_b1_0/N2/CLK (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/mult_image_g0/N2/CLK (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/mult_image_g0_0/N2/CLK (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/mult_image_g1/N2/CLK (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/mult_image_g1_0/N2/CLK (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/mult_image_r0/N2/CLK (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/mult_image_r0_0/N2/CLK (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/mult_image_r1/N2/CLK (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/mult_image_r1_0/N2/CLK (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/no_need_rd_ddr/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/no_one_need_rd_ddr/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/ram_ch0[0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/ram_ch0[1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/ram_ch1[0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/ram_ch1[1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/ram_ch2[0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/ram_ch2[1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/ram_ch[0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/ram_ch[1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/ram_idle/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/ram_idle0/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/ram_idle1/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/ram_sta_reg[0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/ram_sta_reg[1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/ram_sta_reg[2]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/ram_sta_reg[3]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_addr0[0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_addr0[1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_addr0[2]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_addr0[3]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_addr0[4]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_addr0[5]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_addr0[6]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_addr0[7]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_addr0[8]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_addr0[9]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_addr0[10]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_addr[0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_addr[1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_addr[2]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_addr[3]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_addr[4]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_addr[5]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_addr[6]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_addr[7]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_addr[8]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_addr[9]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_addr[10]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data_0[0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data_0[1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data_0[2]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data_0[3]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data_0[4]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data_0[5]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data_0[6]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data_0[7]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data_0[8]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data_0[9]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data_0[10]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data_0[11]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data_0[12]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data_0[13]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data_0[14]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data_0[15]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data_0[16]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data_0[17]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data_0[18]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data_0[19]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data_0[20]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data_0[21]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data_0[22]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data_0[23]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data_0[24]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data_0[25]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data_0[26]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data_0[27]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data_0[28]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data_0[29]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data_0[30]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data_0[31]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data[0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data[1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data[2]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data[3]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data[4]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data[5]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data[6]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data[7]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data[8]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data[9]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data[10]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data[11]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data[12]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data[13]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data[14]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data[15]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data[16]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data[17]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data[18]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data[19]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data[20]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data[21]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data[22]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data[23]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data[24]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data[25]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data[26]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data[27]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data[28]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data[29]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data[30]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_data[31]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/rd_one_ram/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/record_ram_valid/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/store_addr[0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/store_addr[1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/store_addr[2]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/store_addr[3]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/store_addr[4]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/store_addr[5]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/store_addr[6]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/store_addr[7]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/store_addr[8]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/store_addr[9]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/store_addr[10]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/store_addr[11]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/store_addr[12]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/store_addr[13]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/store_mult_h0[0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/store_mult_h0[1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/store_mult_h[0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/store_mult_h[1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/u_image_h_mult/N3/CLK (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/u_image_w_mult/N3/CLK (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/wr_addr0[0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/wr_addr0[1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/wr_addr0[2]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/wr_addr0[3]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/wr_addr0[4]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/wr_addr0[5]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/wr_addr0[6]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/wr_addr0[7]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/wr_addr0[8]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/wr_addr0[9]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/wr_addr0[10]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/wr_addr1[0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/wr_addr1[1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/wr_addr1[2]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/wr_addr1[3]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/wr_addr1[4]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/wr_addr1[5]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/wr_addr1[6]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/wr_addr1[7]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/wr_addr1[8]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/wr_addr1[9]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/wr_addr1[10]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/wr_addr2[0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/wr_addr2[1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/wr_addr2[2]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/wr_addr2[3]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/wr_addr2[4]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/wr_addr2[5]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/wr_addr2[6]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/wr_addr2[7]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/wr_addr2[8]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/wr_addr2[9]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/wr_addr2[10]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/wr_addr3[0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/wr_addr3[1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/wr_addr3[2]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/wr_addr3[3]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/wr_addr3[4]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/wr_addr3[5]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/wr_addr3[6]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/wr_addr3[7]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/wr_addr3[8]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/wr_addr3[9]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/wr_addr3[10]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/wr_ram_done/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/zoom_num0[1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/zoom_num0[2]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/zoom_num0[3]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/zoom_num0[4]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/zoom_num0[5]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/zoom_num0[6]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/zoom_num0[7]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/zoom_num0[8]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/zoom_num0[9]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/zoom_num1[0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/zoom_num1[1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/zoom_num1[2]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/zoom_num1[3]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/zoom_num1[4]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/zoom_num1[5]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/zoom_num1[6]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/zoom_num1[7]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/zoom_num1[8]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/zoom_ram0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/zoom_ram0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKB (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/zoom_ram0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/zoom_ram0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKB (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/zoom_ram0_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/zoom_ram0_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKB (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/zoom_ram0_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/zoom_ram0_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKB (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/zoom_ram1/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/zoom_ram1/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKB (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/zoom_ram1/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/zoom_ram1/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKB (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/zoom_ram1_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/zoom_ram1_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKB (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/zoom_ram1_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/zoom_ram1_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKB (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/zoom_ram2/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/zoom_ram2/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKB (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/zoom_ram2/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/zoom_ram2/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKB (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/zoom_ram2_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/zoom_ram2_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKB (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/zoom_ram2_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/zoom_ram2_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKB (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/zoom_ram3/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/zoom_ram3/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKB (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/zoom_ram3/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/zoom_ram3/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKB (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/zoom_ram3_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/zoom_ram3_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKB (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/zoom_ram3_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKA (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/zoom_ram3_0/U_ipml_sdpram_zoom_ram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKB (4.881, 4.881, 4.981, 4.981) - - - u_zoom_image/zoom_sta_param/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/zoom_sta_param0/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/zoom_sta_param1/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/zoom_sta_reg[0]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/zoom_sta_reg[1]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/zoom_sta_reg[2]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/zoom_sta_reg[3]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/zoom_sta_reg[4]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/zoom_sta_reg[5]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_image/zoom_sta_reg[6]/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_rst/rst/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_rst/rst0/CLK (4.367, 4.367, 4.467, 4.467) - - - u_zoom_rst/rst1/CLK (4.367, 4.367, 4.467, 4.467) - - - zoom_ff0[0]/CLK (4.367, 4.367, 4.467, 4.467) - - - zoom_ff0[1]/CLK (4.367, 4.367, 4.467, 4.467) - - - zoom_ff0[2]/CLK (4.367, 4.367, 4.467, 4.467) - - - zoom_ff0[3]/CLK (4.367, 4.367, 4.467, 4.467) - - - zoom_ff0[4]/CLK (4.367, 4.367, 4.467, 4.467) - - - zoom_ff0[5]/CLK (4.367, 4.367, 4.467, 4.467) - - - zoom_ff0[6]/CLK (4.367, 4.367, 4.467, 4.467) - - - zoom_ff0[7]/CLK (4.367, 4.367, 4.467, 4.467) - - - zoom_ff0[8]/CLK (4.367, 4.367, 4.467, 4.467) - - - zoom_ff0[9]/CLK (4.367, 4.367, 4.467, 4.467) - - - zoom_ff1[0]/CLK (4.367, 4.367, 4.467, 4.467) - - - zoom_ff1[1]/CLK (4.367, 4.367, 4.467, 4.467) - - - zoom_ff1[2]/CLK (4.367, 4.367, 4.467, 4.467) - - - zoom_ff1[3]/CLK (4.367, 4.367, 4.467, 4.467) - - - zoom_ff1[4]/CLK (4.367, 4.367, 4.467, 4.467) - - - zoom_ff1[5]/CLK (4.367, 4.367, 4.467, 4.467) - - - zoom_ff1[6]/CLK (4.367, 4.367, 4.467, 4.467) - - - zoom_ff1[7]/CLK (4.367, 4.367, 4.467, 4.467) - - - zoom_ff1[8]/CLK (4.367, 4.367, 4.467, 4.467) - - - zoom_ff1[9]/CLK (4.367, 4.367, 4.467, 4.467) - - - zoom_ff2[0]/CLK (4.367, 4.367, 4.467, 4.467) - - - zoom_ff2[1]/CLK (4.367, 4.367, 4.467, 4.467) - - - zoom_ff2[2]/CLK (4.367, 4.367, 4.467, 4.467) - - - zoom_ff2[3]/CLK (4.367, 4.367, 4.467, 4.467) - - - zoom_ff2[4]/CLK (4.367, 4.367, 4.467, 4.467) - - - zoom_ff2[5]/CLK (4.367, 4.367, 4.467, 4.467) - - - zoom_ff2[6]/CLK (4.367, 4.367, 4.467, 4.467) - - - zoom_ff2[7]/CLK (4.367, 4.367, 4.467, 4.467) - - - zoom_ff2[8]/CLK (4.367, 4.367, 4.467, 4.467) - - - zoom_ff2[9]/CLK (4.367, 4.367, 4.467, 4.467) - - - zoom_fifo_full/CLK (4.367, 4.367, 4.467, 4.467) - - - zoom_vs_out0/CLK (4.367, 4.367, 4.467, 4.467) - - - zoom_vs_out1/CLK (4.367, 4.367, 4.467, 4.467) - - - - - - clk_25m (25.00MHZ) (drive 26 loads) - - u_sys_pll/u_pll_e3/CLKOUT3 (2.400, 2.400, 2.499, 2.499) - - clk_25m (net) - - u_ov5640/coms1_reg_config/clk_20k_regdiv/CLK (3.113, 3.113, 3.212, 3.212) - - - u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/CLK (3.113, 3.113, 3.212, 3.212) - - - u_ov5640/coms1_reg_config/clock_20k_cnt[0]/CLK (3.113, 3.113, 3.212, 3.212) - - - u_ov5640/coms1_reg_config/clock_20k_cnt[1]/CLK (3.113, 3.113, 3.212, 3.212) - - - u_ov5640/coms1_reg_config/clock_20k_cnt[2]/CLK (3.113, 3.113, 3.212, 3.212) - - - u_ov5640/coms1_reg_config/clock_20k_cnt[3]/CLK (3.113, 3.113, 3.212, 3.212) - - - u_ov5640/coms1_reg_config/clock_20k_cnt[4]/CLK (3.113, 3.113, 3.212, 3.212) - - - u_ov5640/coms1_reg_config/clock_20k_cnt[5]/CLK (3.113, 3.113, 3.212, 3.212) - - - u_ov5640/coms1_reg_config/clock_20k_cnt[6]/CLK (3.113, 3.113, 3.212, 3.212) - - - u_ov5640/coms1_reg_config/clock_20k_cnt[7]/CLK (3.113, 3.113, 3.212, 3.212) - - - u_ov5640/coms1_reg_config/clock_20k_cnt[8]/CLK (3.113, 3.113, 3.212, 3.212) - - - u_ov5640/coms1_reg_config/clock_20k_cnt[9]/CLK (3.113, 3.113, 3.212, 3.212) - - - u_ov5640/coms1_reg_config/clock_20k_cnt[10]/CLK (3.113, 3.113, 3.212, 3.212) - - - u_ov5640/coms2_reg_config/clk_20k_regdiv/CLK (3.113, 3.113, 3.212, 3.212) - - - u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite/CLK (3.113, 3.113, 3.212, 3.212) - - - u_ov5640/coms2_reg_config/clock_20k_cnt[0]/CLK (3.113, 3.113, 3.212, 3.212) - - - u_ov5640/coms2_reg_config/clock_20k_cnt[1]/CLK (3.113, 3.113, 3.212, 3.212) - - - u_ov5640/coms2_reg_config/clock_20k_cnt[2]/CLK (3.113, 3.113, 3.212, 3.212) - - - u_ov5640/coms2_reg_config/clock_20k_cnt[3]/CLK (3.113, 3.113, 3.212, 3.212) - - - u_ov5640/coms2_reg_config/clock_20k_cnt[4]/CLK (3.113, 3.113, 3.212, 3.212) - - - u_ov5640/coms2_reg_config/clock_20k_cnt[5]/CLK (3.113, 3.113, 3.212, 3.212) - - - u_ov5640/coms2_reg_config/clock_20k_cnt[6]/CLK (3.113, 3.113, 3.212, 3.212) - - - u_ov5640/coms2_reg_config/clock_20k_cnt[7]/CLK (3.113, 3.113, 3.212, 3.212) - - - u_ov5640/coms2_reg_config/clock_20k_cnt[8]/CLK (3.113, 3.113, 3.212, 3.212) - - - u_ov5640/coms2_reg_config/clock_20k_cnt[9]/CLK (3.113, 3.113, 3.212, 3.212) - - - u_ov5640/coms2_reg_config/clock_20k_cnt[10]/CLK (3.113, 3.113, 3.212, 3.212) - - - - - - clk_10m (10.00MHZ) (drive 256 loads) - - u_sys_pll/u_pll_e3/CLKOUT4 (2.396, 2.396, 2.495, 2.495) - - clk_10m (net) - - ms72xx_ctl/iic_dri_rx/busy/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/byte_over/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/data_out[0]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/data_out[1]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/data_out[2]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/data_out[3]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/data_out[4]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/data_out[5]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/data_out[6]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/data_out[7]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/fre_cnt[0]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/fre_cnt[1]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/fre_cnt[2]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/fre_cnt[3]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/fre_cnt[4]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/pluse_1d/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/pluse_2d/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/pluse_3d/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/receiv_data[0]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/receiv_data[1]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/receiv_data[2]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/receiv_data[3]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/receiv_data[4]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/receiv_data[5]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/receiv_data[6]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/receiv_data[7]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/scl_out/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/sda_out/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/send_data[0]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/send_data[1]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/send_data[2]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/send_data[3]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/send_data[4]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/send_data[5]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/send_data[6]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/send_data[7]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/start_en/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/state_reg[0]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/state_reg[1]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/state_reg[2]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/state_reg[3]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/state_reg[4]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/state_reg[5]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/state_reg[6]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/trans_bit[0]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/trans_bit[1]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/trans_bit[2]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/trans_byte[0]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/trans_byte[1]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/trans_byte[2]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/trans_byte[3]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/trans_byte_max[0]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/trans_byte_max[2]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/trans_en/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/twr_cnt[0]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/twr_cnt[1]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/twr_cnt[2]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/twr_cnt[3]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/twr_en/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/w_r_1d/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_rx/w_r_2d/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/busy/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/byte_over/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/data_out[0]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/data_out[1]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/data_out[2]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/data_out[3]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/data_out[4]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/data_out[5]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/data_out[6]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/data_out[7]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/pluse_1d/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/pluse_2d/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/pluse_3d/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/receiv_data[0]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/receiv_data[1]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/receiv_data[2]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/receiv_data[3]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/receiv_data[4]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/receiv_data[5]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/receiv_data[6]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/receiv_data[7]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/scl_out/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/sda_out/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/send_data[0]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/send_data[1]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/send_data[2]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/send_data[3]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/send_data[4]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/send_data[5]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/send_data[6]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/send_data[7]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/start_en/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/state_reg[0]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/state_reg[1]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/state_reg[2]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/state_reg[3]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/state_reg[4]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/state_reg[5]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/state_reg[6]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/trans_bit[0]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/trans_bit[1]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/trans_bit[2]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/trans_byte[0]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/trans_byte[1]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/trans_byte[2]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/trans_byte[3]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/trans_byte_max[0]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/trans_byte_max[2]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/trans_en/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/twr_cnt[0]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/twr_cnt[1]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/twr_cnt[2]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/twr_cnt[3]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/twr_en/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/w_r_1d/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/iic_dri_tx/w_r_2d/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/CLKA (4.024, 4.024, 4.123, 4.123) - - - ms72xx_ctl/ms7200_ctl/N1219_1_concat_3/CLKB (4.024, 4.024, 4.123, 4.123) - - - ms72xx_ctl/ms7200_ctl/addr[0]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/addr[1]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/addr[2]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/addr[3]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/addr[4]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/addr[5]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/addr[6]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/addr[7]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/addr[8]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/addr[9]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/addr[12]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/addr[13]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/busy_1d/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/cmd_index[0]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/cmd_index[1]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/cmd_index[2]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/cmd_index[3]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/cmd_index[4]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/cmd_index[5]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/cmd_index[6]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/cmd_index[7]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/cmd_index[8]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/data_in[0]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/data_in[1]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/data_in[2]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/data_in[3]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/data_in[4]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/data_in[5]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/data_in[6]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/data_in[7]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/dri_cnt[0]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/dri_cnt[1]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/dri_cnt[2]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/dri_cnt[3]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/dri_cnt[4]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/dri_cnt[5]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/dri_cnt[6]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/dri_cnt[7]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/dri_cnt[8]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/freq_ensure/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/freq_rec_1d[16]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/freq_rec_1d[17]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/freq_rec_2d[16]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/freq_rec_2d[17]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/freq_rec[16]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/freq_rec[17]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/iic_trig/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/init_over/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/state_reg[0]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/state_reg[1]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/state_reg[2]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/state_reg[3]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/state_reg[4]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7200_ctl/w_r/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/N325_1_concat_2/CLKA (4.024, 4.024, 4.123, 4.123) - - - ms72xx_ctl/ms7210_ctl/N325_1_concat_2/CLKB (4.024, 4.024, 4.123, 4.123) - - - ms72xx_ctl/ms7210_ctl/addr[0]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/addr[1]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/addr[2]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/addr[3]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/addr[4]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/addr[5]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/addr[6]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/addr[7]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/addr[8]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/addr[9]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/addr[10]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/addr[11]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/busy_1d/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/cmd_index[0]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/cmd_index[1]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/cmd_index[2]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/cmd_index[3]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/cmd_index[4]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/cmd_index[5]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/data_in[0]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/data_in[1]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/data_in[2]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/data_in[3]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/data_in[4]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/data_in[5]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/data_in[6]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/data_in[7]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/delay_cnt[0]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/delay_cnt[1]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/delay_cnt[2]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/delay_cnt[3]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/delay_cnt[4]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/delay_cnt[5]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/delay_cnt[6]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/delay_cnt[7]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/delay_cnt[8]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/delay_cnt[9]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/delay_cnt[10]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/delay_cnt[11]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/delay_cnt[12]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/delay_cnt[13]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/delay_cnt[14]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/delay_cnt[15]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/delay_cnt[16]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/delay_cnt[17]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/delay_cnt[18]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/delay_cnt[19]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/delay_cnt[20]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/delay_cnt[21]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/dri_cnt[0]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/dri_cnt[1]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/dri_cnt[2]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/dri_cnt[3]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/dri_cnt[4]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/iic_trig/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/init_over/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/state_reg[1]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/state_reg[2]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/state_reg[3]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/state_reg[4]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/state_reg[5]/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/ms7210_ctl/w_r/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/rstn/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/rstn_temp1/CLK (3.510, 3.510, 3.609, 3.609) - - - ms72xx_ctl/rstn_temp2/CLK (3.510, 3.510, 3.609, 3.609) - - - rstn_1ms[0]/CLK (3.510, 3.510, 3.609, 3.609) - - - rstn_1ms[1]/CLK (3.510, 3.510, 3.609, 3.609) - - - rstn_1ms[2]/CLK (3.510, 3.510, 3.609, 3.609) - - - rstn_1ms[3]/CLK (3.510, 3.510, 3.609, 3.609) - - - rstn_1ms[4]/CLK (3.510, 3.510, 3.609, 3.609) - - - rstn_1ms[5]/CLK (3.510, 3.510, 3.609, 3.609) - - - rstn_1ms[6]/CLK (3.510, 3.510, 3.609, 3.609) - - - rstn_1ms[7]/CLK (3.510, 3.510, 3.609, 3.609) - - - rstn_1ms[8]/CLK (3.510, 3.510, 3.609, 3.609) - - - rstn_1ms[9]/CLK (3.510, 3.510, 3.609, 3.609) - - - rstn_1ms[10]/CLK (3.510, 3.510, 3.609, 3.609) - - - rstn_1ms[11]/CLK (3.510, 3.510, 3.609, 3.609) - - - rstn_1ms[12]/CLK (3.510, 3.510, 3.609, 3.609) - - - rstn_1ms[13]/CLK (3.510, 3.510, 3.609, 3.609) - - - rstn_out0/CLK (3.510, 3.510, 3.609, 3.609) - - - rstn_out1/CLK (3.510, 3.510, 3.609, 3.609) + rstn_out1/CLK (3.510, 3.510, 3.609, 3.609) @@ -46978,64 +44502,64 @@ u_ov5640/cmos1_8_16bit/vs_in1/CLK (4.415, 4.415, 4.516, 4.516) - u_ov5640/cmos1_d_d0[0]/CLK (4.415, 4.415, 4.516, 4.516) + u_ov5640/cmos1_d_d0[0]/CLK (4.415, 4.415, 4.516, 4.516) - u_ov5640/cmos1_d_d0[1]/CLK (4.415, 4.415, 4.516, 4.516) + u_ov5640/cmos1_d_d0[1]/CLK (4.415, 4.415, 4.516, 4.516) - u_ov5640/cmos1_d_d0[2]/CLK (4.415, 4.415, 4.516, 4.516) + u_ov5640/cmos1_d_d0[2]/CLK (4.415, 4.415, 4.516, 4.516) - u_ov5640/cmos1_d_d0[3]/CLK (4.415, 4.415, 4.516, 4.516) + u_ov5640/cmos1_d_d0[3]/CLK (4.415, 4.415, 4.516, 4.516) - u_ov5640/cmos1_d_d0[4]/CLK (4.415, 4.415, 4.516, 4.516) + u_ov5640/cmos1_d_d0[4]/CLK (4.415, 4.415, 4.516, 4.516) - u_ov5640/cmos1_d_d0[5]/CLK (4.415, 4.415, 4.516, 4.516) + u_ov5640/cmos1_d_d0[5]/CLK (4.415, 4.415, 4.516, 4.516) - u_ov5640/cmos1_d_d0[6]/CLK (4.415, 4.415, 4.516, 4.516) + u_ov5640/cmos1_d_d0[6]/CLK (4.415, 4.415, 4.516, 4.516) - u_ov5640/cmos1_d_d0[7]/CLK (4.415, 4.415, 4.516, 4.516) + u_ov5640/cmos1_d_d0[7]/CLK (4.415, 4.415, 4.516, 4.516) - u_ov5640/cmos1_d_d1[0]/CLK (4.415, 4.415, 4.516, 4.516) + u_ov5640/cmos1_d_d1[0]/CLK (4.415, 4.415, 4.516, 4.516) - u_ov5640/cmos1_d_d1[1]/CLK (4.415, 4.415, 4.516, 4.516) + u_ov5640/cmos1_d_d1[1]/CLK (4.415, 4.415, 4.516, 4.516) - u_ov5640/cmos1_d_d1[2]/CLK (4.415, 4.415, 4.516, 4.516) + u_ov5640/cmos1_d_d1[2]/CLK (4.415, 4.415, 4.516, 4.516) - u_ov5640/cmos1_d_d1[3]/CLK (4.415, 4.415, 4.516, 4.516) + u_ov5640/cmos1_d_d1[3]/CLK (4.415, 4.415, 4.516, 4.516) - u_ov5640/cmos1_d_d1[4]/CLK (4.415, 4.415, 4.516, 4.516) + u_ov5640/cmos1_d_d1[4]/CLK (4.415, 4.415, 4.516, 4.516) - u_ov5640/cmos1_d_d1[5]/CLK (4.415, 4.415, 4.516, 4.516) + u_ov5640/cmos1_d_d1[5]/CLK (4.415, 4.415, 4.516, 4.516) - u_ov5640/cmos1_d_d1[6]/CLK (4.415, 4.415, 4.516, 4.516) + u_ov5640/cmos1_d_d1[6]/CLK (4.415, 4.415, 4.516, 4.516) - u_ov5640/cmos1_d_d1[7]/CLK (4.415, 4.415, 4.516, 4.516) + u_ov5640/cmos1_d_d1[7]/CLK (4.415, 4.415, 4.516, 4.516) - u_ov5640/cmos1_href_d0/CLK (4.415, 4.415, 4.516, 4.516) + u_ov5640/cmos1_href_d0/CLK (4.415, 4.415, 4.516, 4.516) - u_ov5640/cmos1_href_d1/CLK (4.415, 4.415, 4.516, 4.516) + u_ov5640/cmos1_href_d1/CLK (4.415, 4.415, 4.516, 4.516) - u_ov5640/cmos1_vsync_d0/CLK (4.415, 4.415, 4.516, 4.516) + u_ov5640/cmos1_vsync_d0/CLK (4.415, 4.415, 4.516, 4.516) - u_ov5640/cmos1_vsync_d1/CLK (4.415, 4.415, 4.516, 4.516) + u_ov5640/cmos1_vsync_d1/CLK (4.415, 4.415, 4.516, 4.516) u_ov5640/u_mix_image/cnt0_h[0]/CLK (4.415, 4.415, 4.516, 4.516) @@ -47371,64 +44895,64 @@ u_ov5640/cmos2_8_16bit/vs_in1/CLK (4.415, 4.415, 4.516, 4.516) - u_ov5640/cmos2_d_d0[0]/CLK (4.415, 4.415, 4.516, 4.516) + u_ov5640/cmos2_d_d0[0]/CLK (4.415, 4.415, 4.516, 4.516) - u_ov5640/cmos2_d_d0[1]/CLK (4.415, 4.415, 4.516, 4.516) + u_ov5640/cmos2_d_d0[1]/CLK (4.415, 4.415, 4.516, 4.516) - u_ov5640/cmos2_d_d0[2]/CLK (4.415, 4.415, 4.516, 4.516) + u_ov5640/cmos2_d_d0[2]/CLK (4.415, 4.415, 4.516, 4.516) - u_ov5640/cmos2_d_d0[3]/CLK (4.415, 4.415, 4.516, 4.516) + u_ov5640/cmos2_d_d0[3]/CLK (4.415, 4.415, 4.516, 4.516) - u_ov5640/cmos2_d_d0[4]/CLK (4.415, 4.415, 4.516, 4.516) + u_ov5640/cmos2_d_d0[4]/CLK (4.415, 4.415, 4.516, 4.516) - u_ov5640/cmos2_d_d0[5]/CLK (4.415, 4.415, 4.516, 4.516) + u_ov5640/cmos2_d_d0[5]/CLK (4.415, 4.415, 4.516, 4.516) - u_ov5640/cmos2_d_d0[6]/CLK (4.415, 4.415, 4.516, 4.516) + u_ov5640/cmos2_d_d0[6]/CLK (4.415, 4.415, 4.516, 4.516) - u_ov5640/cmos2_d_d0[7]/CLK (4.415, 4.415, 4.516, 4.516) + u_ov5640/cmos2_d_d0[7]/CLK (4.415, 4.415, 4.516, 4.516) - u_ov5640/cmos2_d_d1[0]/CLK (4.415, 4.415, 4.516, 4.516) + u_ov5640/cmos2_d_d1[0]/CLK (4.415, 4.415, 4.516, 4.516) - u_ov5640/cmos2_d_d1[1]/CLK (4.415, 4.415, 4.516, 4.516) + u_ov5640/cmos2_d_d1[1]/CLK (4.415, 4.415, 4.516, 4.516) - u_ov5640/cmos2_d_d1[2]/CLK (4.415, 4.415, 4.516, 4.516) + u_ov5640/cmos2_d_d1[2]/CLK (4.415, 4.415, 4.516, 4.516) - u_ov5640/cmos2_d_d1[3]/CLK (4.415, 4.415, 4.516, 4.516) + u_ov5640/cmos2_d_d1[3]/CLK (4.415, 4.415, 4.516, 4.516) - u_ov5640/cmos2_d_d1[4]/CLK (4.415, 4.415, 4.516, 4.516) + u_ov5640/cmos2_d_d1[4]/CLK (4.415, 4.415, 4.516, 4.516) - u_ov5640/cmos2_d_d1[5]/CLK (4.415, 4.415, 4.516, 4.516) + u_ov5640/cmos2_d_d1[5]/CLK (4.415, 4.415, 4.516, 4.516) - u_ov5640/cmos2_d_d1[6]/CLK (4.415, 4.415, 4.516, 4.516) + u_ov5640/cmos2_d_d1[6]/CLK (4.415, 4.415, 4.516, 4.516) - u_ov5640/cmos2_d_d1[7]/CLK (4.415, 4.415, 4.516, 4.516) + u_ov5640/cmos2_d_d1[7]/CLK (4.415, 4.415, 4.516, 4.516) - u_ov5640/cmos2_href_d0/CLK (4.415, 4.415, 4.516, 4.516) + u_ov5640/cmos2_href_d0/CLK (4.415, 4.415, 4.516, 4.516) - u_ov5640/cmos2_href_d1/CLK (4.415, 4.415, 4.516, 4.516) + u_ov5640/cmos2_href_d1/CLK (4.415, 4.415, 4.516, 4.516) - u_ov5640/cmos2_vsync_d0/CLK (4.415, 4.415, 4.516, 4.516) + u_ov5640/cmos2_vsync_d0/CLK (4.415, 4.415, 4.516, 4.516) - u_ov5640/cmos2_vsync_d1/CLK (4.415, 4.415, 4.516, 4.516) + u_ov5640/cmos2_vsync_d1/CLK (4.415, 4.415, 4.516, 4.516) u_ov5640/u_mix_image/cnt1_h[0]/CLK (4.415, 4.415, 4.516, 4.516) @@ -48169,37 +45693,37 @@ gmii_clk (net) - param_manager_inst/clk_ms/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/clk_ms/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/filiter1_mode_flags_ff0/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/filiter1_mode_flags_ff0/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/filiter1_mode_flags_ff1/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/filiter1_mode_flags_ff1/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/filiter1_mode_load/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/filiter1_mode_load/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/filiter2_mode_flags_ff0/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/filiter2_mode_flags_ff0/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/filiter2_mode_flags_ff1/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/filiter2_mode_flags_ff1/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/filiter2_mode_load/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/filiter2_mode_load/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/index[0]/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/index[0]/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/index[1]/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/index[1]/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/index[2]/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/index[2]/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/index[3]/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/index[3]/CLK (5.600, 5.600, 5.701, 5.701) param_manager_inst/key_debounce_key_left/change/CLK (5.600, 5.600, 5.701, 5.701) @@ -48289,190 +45813,190 @@ param_manager_inst/key_debounce_key_right/pressed/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/modify_H_flags_ff0/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/modify_H_flags_ff0/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/modify_H_flags_ff1/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/modify_H_flags_ff1/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/modify_H_flags_ff2/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/modify_H_flags_ff2/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/modify_H_flags_ff3/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/modify_H_flags_ff3/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/modify_H_load/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/modify_H_load/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/modify_S_flags_ff0/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/modify_S_flags_ff0/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/modify_S_flags_ff1/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/modify_S_flags_ff1/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/modify_S_flags_ff2/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/modify_S_flags_ff2/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/modify_S_flags_ff3/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/modify_S_flags_ff3/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/modify_S_load/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/modify_S_load/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/modify_V_flags_ff0/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/modify_V_flags_ff0/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/modify_V_flags_ff1/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/modify_V_flags_ff1/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/modify_V_flags_ff2/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/modify_V_flags_ff2/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/modify_V_flags_ff3/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/modify_V_flags_ff3/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/modify_V_load/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/modify_V_load/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/ms_cnt[0]/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/ms_cnt[0]/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/ms_cnt[1]/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/ms_cnt[1]/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/ms_cnt[2]/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/ms_cnt[2]/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/ms_cnt[3]/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/ms_cnt[3]/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/ms_cnt[4]/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/ms_cnt[4]/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/ms_cnt[5]/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/ms_cnt[5]/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/ms_cnt[6]/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/ms_cnt[6]/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/ms_cnt[7]/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/ms_cnt[7]/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/ms_cnt[8]/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/ms_cnt[8]/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/ms_cnt[9]/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/ms_cnt[9]/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/ms_cnt[10]/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/ms_cnt[10]/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/ms_cnt[11]/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/ms_cnt[11]/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/ms_cnt[12]/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/ms_cnt[12]/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/ms_cnt[13]/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/ms_cnt[13]/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/ms_cnt[14]/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/ms_cnt[14]/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/ms_cnt[15]/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/ms_cnt[15]/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/ms_cnt[16]/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/ms_cnt[16]/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/offsetX_flags_ff0/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/offsetX_flags_ff0/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/offsetX_flags_ff1/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/offsetX_flags_ff1/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/offsetX_flags_ff2/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/offsetX_flags_ff2/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/offsetX_flags_ff3/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/offsetX_flags_ff3/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/offsetX_load/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/offsetX_load/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/offsetY_flags_ff0/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/offsetY_flags_ff0/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/offsetY_flags_ff1/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/offsetY_flags_ff1/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/offsetY_flags_ff2/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/offsetY_flags_ff2/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/offsetY_flags_ff3/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/offsetY_flags_ff3/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/offsetY_load/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/offsetY_load/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/osd_char_height_flags_ff0/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/osd_char_height_flags_ff0/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/osd_char_height_flags_ff1/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/osd_char_height_flags_ff1/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/osd_char_height_flags_ff2/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/osd_char_height_flags_ff2/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/osd_char_height_flags_ff3/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/osd_char_height_flags_ff3/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/osd_char_height_load/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/osd_char_height_load/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/osd_char_width_flags_ff0/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/osd_char_width_flags_ff0/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/osd_char_width_flags_ff1/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/osd_char_width_flags_ff1/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/osd_char_width_flags_ff2/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/osd_char_width_flags_ff2/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/osd_char_width_flags_ff3/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/osd_char_width_flags_ff3/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/osd_char_width_load/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/osd_char_width_load/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/osd_startX_flags_ff0/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/osd_startX_flags_ff0/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/osd_startX_flags_ff1/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/osd_startX_flags_ff1/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/osd_startX_flags_ff2/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/osd_startX_flags_ff2/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/osd_startX_flags_ff3/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/osd_startX_flags_ff3/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/osd_startX_load/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/osd_startX_load/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/osd_startY_flags_ff0/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/osd_startY_flags_ff0/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/osd_startY_flags_ff1/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/osd_startY_flags_ff1/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/osd_startY_flags_ff2/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/osd_startY_flags_ff2/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/osd_startY_flags_ff3/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/osd_startY_flags_ff3/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/osd_startY_load/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/osd_startY_load/CLK (5.600, 5.600, 5.701, 5.701) param_manager_inst/param_filiter1_mode/cnt[0]/CLK (5.600, 5.600, 5.701, 5.701) @@ -49150,85 +46674,85 @@ param_manager_inst/param_zoom/value[9]/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/rotate_A_flags_ff0/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/rotate_A_flags_ff0/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/rotate_A_flags_ff1/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/rotate_A_flags_ff1/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/rotate_A_flags_ff2/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/rotate_A_flags_ff2/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/rotate_A_flags_ff3/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/rotate_A_flags_ff3/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/rotate_A_load/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/rotate_A_load/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/rotate_flags_ff0/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/rotate_flags_ff0/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/rotate_flags_ff1/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/rotate_flags_ff1/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/rotate_load/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/rotate_load/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/selected[0]/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/selected[0]/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/selected[1]/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/selected[1]/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/selected[2]/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/selected[2]/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/selected[3]/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/selected[3]/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/selected[4]/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/selected[4]/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/selected[5]/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/selected[5]/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/selected[6]/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/selected[6]/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/selected[7]/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/selected[7]/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/selected[8]/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/selected[8]/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/selected[9]/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/selected[9]/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/selected[10]/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/selected[10]/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/selected[11]/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/selected[11]/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/selected[12]/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/selected[12]/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/selected[13]/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/selected[13]/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/zoom_flags_ff0/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/zoom_flags_ff0/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/zoom_flags_ff1/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/zoom_flags_ff1/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/zoom_flags_ff2/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/zoom_flags_ff2/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/zoom_flags_ff3/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/zoom_flags_ff3/CLK (5.600, 5.600, 5.701, 5.701) - param_manager_inst/zoom_load/CLK (5.600, 5.600, 5.701, 5.701) + param_manager_inst/zoom_load/CLK (5.600, 5.600, 5.701, 5.701) udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/CLK (5.600, 5.600, 5.701, 5.701) @@ -54139,507 +51663,3260 @@ - - - - - - clk_100m (100.00MHZ) (drive 0 loads) (min_rise, max_rise, min_fall, max_fall) - - - clk_1080p60Hz (148.44MHZ) (drive 0 loads) (min_rise, max_rise, min_fall, max_fall) - - - clk_720p60Hz (74.22MHZ) (drive 1757 loads) (min_rise, max_rise, min_fall, max_fall) - - - clk_20k (0.02MHZ) (drive 50 loads) (min_rise, max_rise, min_fall, max_fall) + + + + + + clk_100m (100.00MHZ) (drive 0 loads) (min_rise, max_rise, min_fall, max_fall) + + + clk_1080p60Hz (148.44MHZ) (drive 844 loads) (min_rise, max_rise, min_fall, max_fall) + + + clk_720p60Hz (74.22MHZ) (drive 1757 loads) (min_rise, max_rise, min_fall, max_fall) + + + clk_20k (0.02MHZ) (drive 50 loads) (min_rise, max_rise, min_fall, max_fall) + + + + + Launch Clock + Capture Clock + WNS(ns) + TNS(ns) + Failing Endpoints + Total Endpoints + + + clk_200m + clk_200m + 1.064 + 0.000 + 0 + 108 + + + ioclk1 + ioclk1 + 1.088 + 0.000 + 0 + 72 + + + ioclk0 + ioclk0 + 1.088 + 0.000 + 0 + 24 + + + eth_rxc + eth_rxc + 1.165 + 0.000 + 0 + 3783 + + + clk_1080p60Hz + clk_1080p60Hz + 1.643 + 0.000 + 0 + 2720 + + + hdmi_in_clk + hdmi_in_clk + 1.917 + 0.000 + 0 + 217 + + + ddrphy_clkin + ddrphy_clkin + 2.366 + 0.000 + 0 + 9577 + + + clk_720p60Hz + clk_720p60Hz + 5.609 + 0.000 + 0 + 3149 + + + cmos2_pclk + cmos2_pclk + 6.955 + 0.000 + 0 + 189 + + + cmos1_pclk + cmos1_pclk + 6.955 + 0.000 + 0 + 189 + + + clk_50m + clk_50m + 12.149 + 0.000 + 0 + 5743 + + + clk_25m + clk_25m + 36.471 + 0.000 + 0 + 30 + + + clk_10m + clk_10m + 93.453 + 0.000 + 0 + 599 + + + clk_20k + clk_20k + 49994.585 + 0.000 + 0 + 122 + +
+ + + Launch Clock + Capture Clock + WHS(ns) + THS(ns) + Failing Endpoints + Total Endpoints + + + cmos1_pclk + cmos1_pclk + -1.352 + -12.168 + 9 + 189 + + + cmos2_pclk + cmos2_pclk + -1.352 + -12.168 + 9 + 189 + + + ddrphy_clkin + ddrphy_clkin + 0.453 + 0.000 + 0 + 9577 + + + hdmi_in_clk + hdmi_in_clk + 0.540 + 0.000 + 0 + 217 + + + eth_rxc + eth_rxc + 0.540 + 0.000 + 0 + 3783 + + + clk_50m + clk_50m + 0.649 + 0.000 + 0 + 5743 + + + clk_720p60Hz + clk_720p60Hz + 0.650 + 0.000 + 0 + 3149 + + + clk_1080p60Hz + clk_1080p60Hz + 0.656 + 0.000 + 0 + 2720 + + + clk_10m + clk_10m + 0.740 + 0.000 + 0 + 599 + + + clk_200m + clk_200m + 0.740 + 0.000 + 0 + 108 + + + clk_20k + clk_20k + 0.829 + 0.000 + 0 + 122 + + + clk_25m + clk_25m + 0.881 + 0.000 + 0 + 30 + + + ioclk0 + ioclk0 + 1.193 + 0.000 + 0 + 24 + + + ioclk1 + ioclk1 + 1.193 + 0.000 + 0 + 72 + +
+ + + Launch Clock + Capture Clock + WNS(ns) + TNS(ns) + Failing Endpoints + Total Endpoints + + + clk_200m + clk_200m + 1.564 + 0.000 + 0 + 69 + + + clk_1080p60Hz + clk_1080p60Hz + 4.552 + 0.000 + 0 + 125 + + + ddrphy_clkin + ddrphy_clkin + 6.273 + 0.000 + 0 + 2809 + + + clk_720p60Hz + clk_720p60Hz + 9.504 + 0.000 + 0 + 736 + + + clk_50m + clk_50m + 16.577 + 0.000 + 0 + 278 + + + clk_10m + clk_10m + 98.374 + 0.000 + 0 + 1 + +
+ + + Launch Clock + Capture Clock + WHS(ns) + THS(ns) + Failing Endpoints + Total Endpoints + + + clk_200m + clk_200m + -1.158 + -2.316 + 2 + 69 + + + ddrphy_clkin + ddrphy_clkin + 1.092 + 0.000 + 0 + 2809 + + + clk_10m + clk_10m + 1.185 + 0.000 + 0 + 1 + + + clk_50m + clk_50m + 1.336 + 0.000 + 0 + 278 + + + clk_1080p60Hz + clk_1080p60Hz + 1.545 + 0.000 + 0 + 125 + + + clk_720p60Hz + clk_720p60Hz + 1.608 + 0.000 + 0 + 736 + +
+ + + Clock + WPWS + TPWS + Failing End Point + Total End Point + + + ioclk1 + 0.397 + 0.000 + 0 + 27 + + + ioclk2 + 0.397 + 0.000 + 0 + 2 + + + ioclk0 + 0.397 + 0.000 + 0 + 11 + + + clk_200m + 1.880 + 0.000 + 0 + 75 + + + clk_1080p60Hz + 2.230 + 0.000 + 0 + 844 + + + hdmi_in_clk + 2.435 + 0.000 + 0 + 173 + + + eth_rxc + 2.483 + 0.000 + 0 + 1988 + + + ddrphy_clkin + 3.100 + 0.000 + 0 + 5817 + + + ioclk_gate_clk + 4.380 + 0.000 + 0 + 1 + + + cmos2_pclk + 5.052 + 0.000 + 0 + 126 + + + cmos1_pclk + 5.052 + 0.000 + 0 + 126 + + + clk_720p60Hz + 5.598 + 0.000 + 0 + 1757 + + + clk_50m + 8.862 + 0.000 + 0 + 2824 + + + clk_25m + 19.380 + 0.000 + 0 + 26 + + + clk_10m + 49.102 + 0.000 + 0 + 256 + + + clk_20k + 24999.102 + 0.000 + 0 + 50 + +
+ + + Slack + Logic Levels + High Fanout + Start Point + End Point + Exception + Launch Clock + Capture Clock + Clock Edges + Clock Skew + Launch Clock Delay + Capture Clock Delay + Clock Pessimism Removal + Requirement + Data delay + Logic delay + Route delay + + + 1.064 + 3 + 19 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[14]/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[0]/CE + + clk_200m + clk_200m + rise-rise + 0.000 + 5.192 + 5.192 + 0.000 + 5.000 + 3.244 + 1.004 (30.9%) + 2.240 (69.1%) + + Path #1: setup slack is 1.064(MET) + +
+ + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_200m (rising edge) + + 0.000 + 0.000 + r + + + + clk + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.000 + 0.000 + + clk + + + + + + + + clk_ibuf/I (GTP_INBUF) + + + + td + 1.211 + 1.211 + r + clk_ibuf/O (GTP_INBUF) + + + + net (fanout=1) + 1.091 + 2.302 + + nt_clk + + + + + + + + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.089 + 2.391 + r + u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + + + + net (fanout=7) + 0.605 + 2.996 + + ddr_clk + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + + + + td + 0.000 + 2.996 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + + + + net (fanout=71) + 2.196 + 5.192 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[14]/CLK (GTP_DFF_CE) + + + + tco + 0.329 + 5.521 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[14]/Q (GTP_DFF_CE) + + + + net (fanout=2) + 0.553 + 6.074 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt [14] + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_33/I0 (GTP_LUT5) + + + + td + 0.318 + 6.392 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_33/Z (GTP_LUT5) + + + + net (fanout=2) + 0.553 + 6.945 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107154 + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_36/I4 (GTP_LUT5) + + + + td + 0.185 + 7.130 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_36/Z (GTP_LUT5) + + + + net (fanout=1) + 0.464 + 7.594 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107157 + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43_3/I4 (GTP_LUT5) + + + + td + 0.172 + 7.766 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43_3/Z (GTP_LUT5) + + + + net (fanout=19) + 0.670 + 8.436 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43 + + + + + + + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[0]/CE (GTP_DFF_CE) + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_200m (rising edge) + + 5.000 + 5.000 + r + + + + clk + + 0.000 + 5.000 + r + clk (port) + + + + net (fanout=1) + 0.000 + 5.000 + + clk + + + + + + + + clk_ibuf/I (GTP_INBUF) + + + + td + 1.211 + 6.211 + r + clk_ibuf/O (GTP_INBUF) + + + + net (fanout=1) + 1.091 + 7.302 + + nt_clk + + + + + + + + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.089 + 7.391 + r + u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + + + + net (fanout=7) + 0.605 + 7.996 + + ddr_clk + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + + + + td + 0.000 + 7.996 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + + + + net (fanout=71) + 2.196 + 10.192 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[0]/CLK (GTP_DFF_CE) + + + clock pessimism + + 0.000 + 10.192 + + + + + clock uncertainty + + -0.150 + 10.042 + + + + + Setup time + + -0.542 + 9.500 + + + +
+
+
+
+ + 1.064 + 3 + 19 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[14]/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[1]/CE + + clk_200m + clk_200m + rise-rise + 0.000 + 5.192 + 5.192 + 0.000 + 5.000 + 3.244 + 1.004 (30.9%) + 2.240 (69.1%) + + Path #2: setup slack is 1.064(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_200m (rising edge) + + 0.000 + 0.000 + r + + + + clk + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.000 + 0.000 + + clk + + + + + + + + clk_ibuf/I (GTP_INBUF) + + + + td + 1.211 + 1.211 + r + clk_ibuf/O (GTP_INBUF) + + + + net (fanout=1) + 1.091 + 2.302 + + nt_clk + + + + + + + + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.089 + 2.391 + r + u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + + + + net (fanout=7) + 0.605 + 2.996 + + ddr_clk + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + + + + td + 0.000 + 2.996 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + + + + net (fanout=71) + 2.196 + 5.192 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[14]/CLK (GTP_DFF_CE) + + + + tco + 0.329 + 5.521 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[14]/Q (GTP_DFF_CE) + + + + net (fanout=2) + 0.553 + 6.074 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt [14] + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_33/I0 (GTP_LUT5) + + + + td + 0.318 + 6.392 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_33/Z (GTP_LUT5) + + + + net (fanout=2) + 0.553 + 6.945 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107154 + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_36/I4 (GTP_LUT5) + + + + td + 0.185 + 7.130 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_36/Z (GTP_LUT5) + + + + net (fanout=1) + 0.464 + 7.594 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107157 + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43_3/I4 (GTP_LUT5) + + + + td + 0.172 + 7.766 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43_3/Z (GTP_LUT5) + + + + net (fanout=19) + 0.670 + 8.436 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43 + + + + + + + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[1]/CE (GTP_DFF_CE) + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_200m (rising edge) + + 5.000 + 5.000 + r + + + + clk + + 0.000 + 5.000 + r + clk (port) + + + + net (fanout=1) + 0.000 + 5.000 + + clk + + + + + + + + clk_ibuf/I (GTP_INBUF) + + + + td + 1.211 + 6.211 + r + clk_ibuf/O (GTP_INBUF) + + + + net (fanout=1) + 1.091 + 7.302 + + nt_clk + + + + + + + + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.089 + 7.391 + r + u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + + + + net (fanout=7) + 0.605 + 7.996 + + ddr_clk + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + + + + td + 0.000 + 7.996 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + + + + net (fanout=71) + 2.196 + 10.192 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[1]/CLK (GTP_DFF_CE) + + + clock pessimism + + 0.000 + 10.192 + + + + + clock uncertainty + + -0.150 + 10.042 + + + + + Setup time + + -0.542 + 9.500 + + + +
+
+
+
+ + 1.064 + 3 + 19 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[14]/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[2]/CE + + clk_200m + clk_200m + rise-rise + 0.000 + 5.192 + 5.192 + 0.000 + 5.000 + 3.244 + 1.004 (30.9%) + 2.240 (69.1%) + + Path #3: setup slack is 1.064(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_200m (rising edge) + + 0.000 + 0.000 + r + + + + clk + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.000 + 0.000 + + clk + + + + + + + + clk_ibuf/I (GTP_INBUF) + + + + td + 1.211 + 1.211 + r + clk_ibuf/O (GTP_INBUF) + + + + net (fanout=1) + 1.091 + 2.302 + + nt_clk + + + + + + + + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.089 + 2.391 + r + u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + + + + net (fanout=7) + 0.605 + 2.996 + + ddr_clk + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + + + + td + 0.000 + 2.996 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + + + + net (fanout=71) + 2.196 + 5.192 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[14]/CLK (GTP_DFF_CE) + + + + tco + 0.329 + 5.521 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[14]/Q (GTP_DFF_CE) + + + + net (fanout=2) + 0.553 + 6.074 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt [14] + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_33/I0 (GTP_LUT5) + + + + td + 0.318 + 6.392 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_33/Z (GTP_LUT5) + + + + net (fanout=2) + 0.553 + 6.945 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107154 + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_36/I4 (GTP_LUT5) + + + + td + 0.185 + 7.130 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N39_36/Z (GTP_LUT5) + + + + net (fanout=1) + 0.464 + 7.594 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/_N107157 + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43_3/I4 (GTP_LUT5) + + + + td + 0.172 + 7.766 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43_3/Z (GTP_LUT5) + + + + net (fanout=19) + 0.670 + 8.436 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/N43 + + + + + + + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[2]/CE (GTP_DFF_CE) + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_200m (rising edge) + + 5.000 + 5.000 + r + + + + clk + + 0.000 + 5.000 + r + clk (port) + + + + net (fanout=1) + 0.000 + 5.000 + + clk + + + + + + + + clk_ibuf/I (GTP_INBUF) + + + + td + 1.211 + 6.211 + r + clk_ibuf/O (GTP_INBUF) + + + + net (fanout=1) + 1.091 + 7.302 + + nt_clk + + + + + + + + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.089 + 7.391 + r + u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + + + + net (fanout=7) + 0.605 + 7.996 + + ddr_clk + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + + + + td + 0.000 + 7.996 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + + + + net (fanout=71) + 2.196 + 10.192 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_pll_lock_debounce/rise_cnt[2]/CLK (GTP_DFF_CE) + + + clock pessimism + + 0.000 + 10.192 + + + + + clock uncertainty + + -0.150 + 10.042 + + + + + Setup time + + -0.542 + 9.500 + + + +
+
+
+
+ + 1.088 + 0 + 8 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/CLKA + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[0] + + ioclk1 + ioclk1 + rise-rise + 0.000 + 5.766 + 5.766 + 0.000 + 2.500 + 1.194 + 0.464 (38.9%) + 0.730 (61.1%) + + Path #4: setup slack is 1.088(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk1 (rising edge) + + 0.000 + 0.000 + r + + + + clk + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.000 + 0.000 + + clk + + + + + + + + clk_ibuf/I (GTP_INBUF) + + + + td + 1.211 + 1.211 + r + clk_ibuf/O (GTP_INBUF) + + + + net (fanout=1) + 1.091 + 2.302 + + nt_clk + + + + + + + + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.089 + 2.391 + r + u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + + + + net (fanout=7) + 0.605 + 2.996 + + ddr_clk + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + + + + td + 0.000 + 2.996 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + + + + net (fanout=71) + 0.847 + 3.843 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.094 + 3.937 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + + + + net (fanout=3) + 0.605 + 4.542 + + u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKIN (GTP_IOCLKBUF) + + + + td + 0.306 + 4.848 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) + + + + net (fanout=28) + 0.918 + 5.766 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + + + + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/CLKA (GTP_DDC_E1) + + + + tco + 0.464 + 6.230 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[0] (GTP_DDC_E1) + + + + net (fanout=8) + 0.730 + 6.960 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [0] + + + + + + + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[0] (GTP_ISERDES) + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk1 (rising edge) + + 2.500 + 2.500 + r + + + + clk + + 0.000 + 2.500 + r + clk (port) + + + + net (fanout=1) + 0.000 + 2.500 + + clk + + + + + + + + clk_ibuf/I (GTP_INBUF) + + + + td + 1.211 + 3.711 + r + clk_ibuf/O (GTP_INBUF) + + + + net (fanout=1) + 1.091 + 4.802 + + nt_clk + + + + + + + + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.089 + 4.891 + r + u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + + + + net (fanout=7) + 0.605 + 5.496 + + ddr_clk + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + + + + td + 0.000 + 5.496 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + + + + net (fanout=71) + 0.847 + 6.343 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.094 + 6.437 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + + + + net (fanout=3) + 0.605 + 7.042 + + u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKIN (GTP_IOCLKBUF) + + + + td + 0.306 + 7.348 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) + + + + net (fanout=28) + 0.918 + 8.266 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + + + + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/DESCLK (GTP_ISERDES) + + + clock pessimism + + 0.000 + 8.266 + + + + + clock uncertainty + + -0.150 + 8.116 + + + + + Setup time + + -0.068 + 8.048 + + + +
+
+
+
+ + 1.088 + 0 + 8 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/CLKA + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[1] + + ioclk1 + ioclk1 + rise-rise + 0.000 + 5.766 + 5.766 + 0.000 + 2.500 + 1.194 + 0.464 (38.9%) + 0.730 (61.1%) + + Path #5: setup slack is 1.088(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk1 (rising edge) + + 0.000 + 0.000 + r + + + + clk + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.000 + 0.000 + + clk + + + + + + + + clk_ibuf/I (GTP_INBUF) + + + + td + 1.211 + 1.211 + r + clk_ibuf/O (GTP_INBUF) + + + + net (fanout=1) + 1.091 + 2.302 + + nt_clk + + + + + + + + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.089 + 2.391 + r + u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + + + + net (fanout=7) + 0.605 + 2.996 + + ddr_clk + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + + + + td + 0.000 + 2.996 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + + + + net (fanout=71) + 0.847 + 3.843 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.094 + 3.937 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + + + + net (fanout=3) + 0.605 + 4.542 + + u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKIN (GTP_IOCLKBUF) + + + + td + 0.306 + 4.848 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) + + + + net (fanout=28) + 0.918 + 5.766 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + + + + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/CLKA (GTP_DDC_E1) + + + + tco + 0.464 + 6.230 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[1] (GTP_DDC_E1) + + + + net (fanout=8) + 0.730 + 6.960 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [1] + + + + + + + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[1] (GTP_ISERDES) + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk1 (rising edge) + + 2.500 + 2.500 + r + + + + clk + + 0.000 + 2.500 + r + clk (port) + + + + net (fanout=1) + 0.000 + 2.500 + + clk + + + + + + + + clk_ibuf/I (GTP_INBUF) + + + + td + 1.211 + 3.711 + r + clk_ibuf/O (GTP_INBUF) + + + + net (fanout=1) + 1.091 + 4.802 + + nt_clk + + + + + + + + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.089 + 4.891 + r + u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + + + + net (fanout=7) + 0.605 + 5.496 + + ddr_clk + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + + + + td + 0.000 + 5.496 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + + + + net (fanout=71) + 0.847 + 6.343 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.094 + 6.437 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + + + + net (fanout=3) + 0.605 + 7.042 + + u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKIN (GTP_IOCLKBUF) + + + + td + 0.306 + 7.348 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) + + + + net (fanout=28) + 0.918 + 8.266 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + + + + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/DESCLK (GTP_ISERDES) + + + clock pessimism + + 0.000 + 8.266 + + + + + clock uncertainty + + -0.150 + 8.116 + + + + + Setup time + + -0.068 + 8.048 + + + +
+
+
- - - - Launch Clock - Capture Clock - WNS(ns) - TNS(ns) - Failing Endpoints - Total Endpoints - - clk_200m - clk_200m - 0.130 - 0.000 + 1.088 0 - 2828 - - + 8 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/CLKA + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[2] + ioclk1 ioclk1 - 1.088 - 0.000 - 0 - 72 - - - ioclk0 - ioclk0 - 1.088 - 0.000 - 0 - 24 - - - eth_rxc - eth_rxc - 1.165 - 0.000 - 0 - 3783 - - - hdmi_in_clk - hdmi_in_clk - 1.917 - 0.000 - 0 - 217 - - - ddrphy_clkin - ddrphy_clkin - 2.212 - 0.000 - 0 - 9577 - - - clk_720p60Hz - clk_720p60Hz - 5.565 - 0.000 - 0 - 3149 - - - cmos2_pclk - cmos2_pclk - 6.955 - 0.000 - 0 - 189 - - - cmos1_pclk - cmos1_pclk - 6.955 - 0.000 - 0 - 189 - - - clk_50m - clk_50m - 12.150 - 0.000 - 0 - 5747 - - - clk_25m - clk_25m - 36.471 - 0.000 - 0 - 30 - - - clk_10m - clk_10m - 93.453 - 0.000 - 0 - 599 - - - clk_20k - clk_20k - 49994.585 - 0.000 - 0 - 122 - -
- - - Launch Clock - Capture Clock - WHS(ns) - THS(ns) - Failing Endpoints - Total Endpoints - - - cmos1_pclk - cmos1_pclk - -1.352 - -12.168 - 9 - 189 - - - cmos2_pclk - cmos2_pclk - -1.352 - -12.168 - 9 - 189 - - - ddrphy_clkin - ddrphy_clkin - 0.453 - 0.000 - 0 - 9577 - - - eth_rxc - eth_rxc - 0.540 - 0.000 - 0 - 3783 - - - hdmi_in_clk - hdmi_in_clk - 0.540 - 0.000 - 0 - 217 - - - clk_50m - clk_50m - 0.650 - 0.000 - 0 - 5747 - - - clk_720p60Hz - clk_720p60Hz - 0.650 - 0.000 - 0 - 3149 - - - clk_200m - clk_200m - 0.656 - 0.000 - 0 - 2828 - - - clk_10m - clk_10m - 0.740 + rise-rise 0.000 - 0 - 599 - - - clk_20k - clk_20k - 0.829 + 5.766 + 5.766 0.000 - 0 - 122 + 2.500 + 1.194 + 0.464 (38.9%) + 0.730 (61.1%) + + Path #6: setup slack is 1.088(MET) + +
+ + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk1 (rising edge) + + 0.000 + 0.000 + r + + + + clk + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.000 + 0.000 + + clk + + + + + + + + clk_ibuf/I (GTP_INBUF) + + + + td + 1.211 + 1.211 + r + clk_ibuf/O (GTP_INBUF) + + + + net (fanout=1) + 1.091 + 2.302 + + nt_clk + + + + + + + + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.089 + 2.391 + r + u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + + + + net (fanout=7) + 0.605 + 2.996 + + ddr_clk + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + + + + td + 0.000 + 2.996 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + + + + net (fanout=71) + 0.847 + 3.843 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.094 + 3.937 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + + + + net (fanout=3) + 0.605 + 4.542 + + u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKIN (GTP_IOCLKBUF) + + + + td + 0.306 + 4.848 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) + + + + net (fanout=28) + 0.918 + 5.766 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + + + + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/CLKA (GTP_DDC_E1) + + + + tco + 0.464 + 6.230 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[2] (GTP_DDC_E1) + + + + net (fanout=8) + 0.730 + 6.960 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [2] + + + + + + + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[2] (GTP_ISERDES) + +
+ + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk1 (rising edge) + + 2.500 + 2.500 + r + + + + clk + + 0.000 + 2.500 + r + clk (port) + + + + net (fanout=1) + 0.000 + 2.500 + + clk + + + + + + + + clk_ibuf/I (GTP_INBUF) + + + + td + 1.211 + 3.711 + r + clk_ibuf/O (GTP_INBUF) + + + + net (fanout=1) + 1.091 + 4.802 + + nt_clk + + + + + + + + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.089 + 4.891 + r + u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + + + + net (fanout=7) + 0.605 + 5.496 + + ddr_clk + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + + + + td + 0.000 + 5.496 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + + + + net (fanout=71) + 0.847 + 6.343 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.094 + 6.437 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + + + + net (fanout=3) + 0.605 + 7.042 + + u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKIN (GTP_IOCLKBUF) + + + + td + 0.306 + 7.348 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) + + + + net (fanout=28) + 0.918 + 8.266 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + + + + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/DESCLK (GTP_ISERDES) + + + clock pessimism + + 0.000 + 8.266 + + + + + clock uncertainty + + -0.150 + 8.116 + + + + + Setup time + + -0.068 + 8.048 + + + +
+
+
- clk_25m - clk_25m - 0.881 - 0.000 + 1.088 0 - 30 - - - ioclk0 + 8 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/CLKA + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[0] + ioclk0 - 1.193 - 0.000 - 0 - 24 - - - ioclk1 - ioclk1 - 1.193 - 0.000 - 0 - 72 - - - - - Launch Clock - Capture Clock - WNS(ns) - TNS(ns) - Failing Endpoints - Total Endpoints - - - clk_200m - clk_200m - 1.564 - 0.000 - 0 - 194 - - - ddrphy_clkin - ddrphy_clkin - 6.273 - 0.000 - 0 - 2809 - - - clk_720p60Hz - clk_720p60Hz - 9.504 - 0.000 - 0 - 736 - - - clk_50m - clk_50m - 16.577 - 0.000 - 0 - 278 - - - clk_10m - clk_10m - 98.374 - 0.000 - 0 - 1 - -
- - - Launch Clock - Capture Clock - WHS(ns) - THS(ns) - Failing Endpoints - Total Endpoints - - - clk_200m - clk_200m - -1.158 - -2.316 - 2 - 194 - - - ddrphy_clkin - ddrphy_clkin - 1.092 - 0.000 - 0 - 2809 - - - clk_10m - clk_10m - 1.185 - 0.000 - 0 - 1 - - - clk_50m - clk_50m - 1.337 - 0.000 - 0 - 278 - - - clk_720p60Hz - clk_720p60Hz - 1.608 - 0.000 - 0 - 736 - -
- - - Clock - WPWS - TPWS - Failing End Point - Total End Point - - - ioclk1 - 0.397 - 0.000 - 0 - 27 - - ioclk0 - 0.397 - 0.000 - 0 - 11 - - - ioclk2 - 0.397 - 0.000 - 0 - 2 - - - clk_200m - 1.362 - 0.000 - 0 - 919 - - - hdmi_in_clk - 2.435 - 0.000 - 0 - 173 - - - eth_rxc - 2.483 - 0.000 - 0 - 1988 - - - ddrphy_clkin - 3.100 - 0.000 - 0 - 5817 - - - ioclk_gate_clk - 4.380 - 0.000 - 0 - 1 - - - cmos1_pclk - 5.052 - 0.000 - 0 - 126 - - - cmos2_pclk - 5.052 - 0.000 - 0 - 126 - - - clk_720p60Hz - 5.598 - 0.000 - 0 - 1757 - - - clk_50m - 8.862 - 0.000 - 0 - 2826 - - - clk_25m - 19.380 + rise-rise 0.000 - 0 - 26 - - - clk_10m - 49.102 + 5.619 + 5.619 0.000 - 0 - 256 + 2.500 + 1.194 + 0.464 (38.9%) + 0.730 (61.1%) + + Path #7: setup slack is 1.088(MET) + +
+ + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk0 (rising edge) + + 0.000 + 0.000 + r + + + + clk + + 0.000 + 0.000 + r + clk (port) + + + + net (fanout=1) + 0.000 + 0.000 + + clk + + + + + + + + clk_ibuf/I (GTP_INBUF) + + + + td + 1.211 + 1.211 + r + clk_ibuf/O (GTP_INBUF) + + + + net (fanout=1) + 1.091 + 2.302 + + nt_clk + + + + + + + + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.089 + 2.391 + r + u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + + + + net (fanout=7) + 0.605 + 2.996 + + ddr_clk + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + + + + td + 0.000 + 2.996 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + + + + net (fanout=71) + 0.847 + 3.843 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.094 + 3.937 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + + + + net (fanout=3) + 0.605 + 4.542 + + u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKIN (GTP_IOCLKBUF) + + + + td + 0.306 + 4.848 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) + + + + net (fanout=11) + 0.771 + 5.619 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + + + + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/CLKA (GTP_DDC_E1) + + + + tco + 0.464 + 6.083 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[0] (GTP_DDC_E1) + + + + net (fanout=8) + 0.730 + 6.813 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [0] + + + + + + + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[0] (GTP_ISERDES) + +
+ + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk0 (rising edge) + + 2.500 + 2.500 + r + + + + clk + + 0.000 + 2.500 + r + clk (port) + + + + net (fanout=1) + 0.000 + 2.500 + + clk + + + + + + + + clk_ibuf/I (GTP_INBUF) + + + + td + 1.211 + 3.711 + r + clk_ibuf/O (GTP_INBUF) + + + + net (fanout=1) + 1.091 + 4.802 + + nt_clk + + + + + + + + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.089 + 4.891 + r + u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + + + + net (fanout=7) + 0.605 + 5.496 + + ddr_clk + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + + + + td + 0.000 + 5.496 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + + + + net (fanout=71) + 0.847 + 6.343 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.094 + 6.437 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + + + + net (fanout=3) + 0.605 + 7.042 + + u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKIN (GTP_IOCLKBUF) + + + + td + 0.306 + 7.348 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) + + + + net (fanout=11) + 0.771 + 8.119 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + + + + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/DESCLK (GTP_ISERDES) + + + clock pessimism + + 0.000 + 8.119 + + + + + clock uncertainty + + -0.150 + 7.969 + + + + + Setup time + + -0.068 + 7.901 + + + +
+
+
- clk_20k - 24999.102 - 0.000 + 1.088 0 - 50 - - - - - Slack - Logic Levels - High Fanout - Start Point - End Point - Exception - Launch Clock - Capture Clock - Clock Edges - Clock Skew - Launch Clock Delay - Capture Clock Delay - Clock Pessimism Removal - Requirement - Data delay - Logic delay - Route delay - - - 0.130 - 7 - 36 - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/CLK - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[12]/D + 8 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/CLKA + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[1] - clk_200m - clk_200m + ioclk0 + ioclk0 rise-rise 0.000 - 4.367 - 4.367 + 5.619 + 5.619 0.000 - 5.000 - 4.754 - 1.997 (42.0%) - 2.757 (58.0%) + 2.500 + 1.194 + 0.464 (38.9%) + 0.730 (61.1%) - Path #1: setup slack is 0.130(MET) + Path #8: setup slack is 1.088(MET) -
+
Location Delay Type @@ -54649,7 +54926,7 @@ Logical Resource - Clock clk_200m (rising edge) + Clock ioclk0 (rising edge) 0.000 0.000 @@ -54714,432 +54991,518 @@ - net (fanout=851) - 1.976 - 4.367 + net (fanout=7) + 0.605 + 2.996 - zoom_clk + ddr_clk - r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/CLK (GTP_DFF_CE) + + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - - tco - 0.329 - 4.696 + + td + 0.000 + 2.996 r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/Q (GTP_DFF_CE) + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=36) - 0.958 - 5.654 - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/wr_addr [0] + net (fanout=71) + 0.847 + 3.843 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - + - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N2_2/I1 (GTP_LUT5CARRY) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - + td - 0.298 - 5.952 - f - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N2_2/COUT (GTP_LUT5CARRY) + 0.094 + 3.937 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=1) - 0.000 - 5.952 - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16324 + net (fanout=3) + 0.605 + 4.542 + + u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] - + - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N2_3/CIN (GTP_LUT5CARRY) + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKIN (GTP_IOCLKBUF) - + td - 0.236 - 6.188 + 0.306 + 4.848 r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N2_3/Z (GTP_LUT5CARRY) + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) - net (fanout=4) - 0.641 - 6.829 - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N2 [2] + net (fanout=11) + 0.771 + 5.619 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] - - + - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[2]/I2 (GTP_LUT3) + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/CLKA (GTP_DDC_E1) - td - 0.185 - 7.014 - r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[2]/Z (GTP_LUT3) + tco + 0.464 + 6.083 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[1] (GTP_DDC_E1) - net (fanout=3) - 0.605 - 7.619 + net (fanout=8) + 0.730 + 6.813 - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wwptr [2] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [1] + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[1] (GTP_ISERDES) + +
+ + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk0 (rising edge) + + 2.500 + 2.500 + r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_3/I2 (GTP_LUT5CARRY) - - td - 0.258 - 7.877 - f - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_3/COUT (GTP_LUT5CARRY) + clk + + 0.000 + 2.500 + r + clk (port) net (fanout=1) 0.000 - 7.877 - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [3] + 2.500 + + clk - + - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_4/CIN (GTP_LUT5CARRY) + clk_ibuf/I (GTP_INBUF) - + td - 0.030 - 7.907 + 1.211 + 3.711 r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_4/COUT (GTP_LUT5CARRY) + clk_ibuf/O (GTP_INBUF) net (fanout=1) - 0.000 - 7.907 - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [4] + 1.091 + 4.802 + + nt_clk - + - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_5/CIN (GTP_LUT5CARRY) + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) - + td - 0.030 - 7.937 + 0.089 + 4.891 r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_5/COUT (GTP_LUT5CARRY) + u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=1) - 0.000 - 7.937 - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [5] + net (fanout=7) + 0.605 + 5.496 + + ddr_clk - + - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_6/CIN (GTP_LUT5CARRY) + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - + td - 0.030 - 7.967 + 0.000 + 5.496 r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_6/COUT (GTP_LUT5CARRY) + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=1) - 0.000 - 7.967 - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [6] + net (fanout=71) + 0.847 + 6.343 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - + - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_7/CIN (GTP_LUT5CARRY) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - + td - 0.030 - 7.997 + 0.094 + 6.437 r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_7/COUT (GTP_LUT5CARRY) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=1) - 0.000 - 7.997 - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [7] + net (fanout=3) + 0.605 + 7.042 + + u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] - + - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_8/CIN (GTP_LUT5CARRY) + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKIN (GTP_IOCLKBUF) - + td - 0.030 - 8.027 + 0.306 + 7.348 r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_8/COUT (GTP_LUT5CARRY) + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) - net (fanout=1) + net (fanout=11) + 0.771 + 8.119 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + + + + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/DESCLK (GTP_ISERDES) + + + clock pessimism + 0.000 - 8.027 - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [8] + 8.119 + + - + clock uncertainty + + -0.150 + 7.969 + + + + + Setup time + + -0.068 + 7.901 + +
+
+ +
+ + 1.088 + 0 + 8 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/CLKA + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[2] + + ioclk0 + ioclk0 + rise-rise + 0.000 + 5.619 + 5.619 + 0.000 + 2.500 + 1.194 + 0.464 (38.9%) + 0.730 (61.1%) + + Path #9: setup slack is 1.088(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ioclk0 (rising edge) + 0.000 + 0.000 + r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_9/CIN (GTP_LUT5CARRY) - - td - 0.030 - 8.057 + clk + + 0.000 + 0.000 r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_9/COUT (GTP_LUT5CARRY) + clk (port) net (fanout=1) 0.000 - 8.057 - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [9] + 0.000 + + clk - + - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_10/CIN (GTP_LUT5CARRY) + clk_ibuf/I (GTP_INBUF) - + td - 0.030 - 8.087 + 1.211 + 1.211 r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_10/COUT (GTP_LUT5CARRY) + clk_ibuf/O (GTP_INBUF) net (fanout=1) - 0.000 - 8.087 - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [10] + 1.091 + 2.302 + + nt_clk - + - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_11/CIN (GTP_LUT5CARRY) + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) - + td - 0.030 - 8.117 + 0.089 + 2.391 r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_11/COUT (GTP_LUT5CARRY) + u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=1) - 0.000 - 8.117 - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [11] + net (fanout=7) + 0.605 + 2.996 + + ddr_clk - + - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_12/CIN (GTP_LUT5CARRY) + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - + td - 0.030 - 8.147 + 0.000 + 2.996 r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_12/COUT (GTP_LUT5CARRY) + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=1) - 0.000 - 8.147 - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [12] + net (fanout=71) + 0.847 + 3.843 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - + - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_13/CIN (GTP_LUT5CARRY) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - + td - 0.236 - 8.383 + 0.094 + 3.937 r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_13/Z (GTP_LUT5CARRY) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2) - 0.553 - 8.936 - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/nb6 [12] + net (fanout=3) + 0.605 + 4.542 + + u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] - + - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_5[12]/I2 (GTP_LUT4) + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKIN (GTP_IOCLKBUF) - + td - 0.185 - 9.121 + 0.306 + 4.848 r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_5[12]/Z (GTP_LUT4) + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) - net (fanout=1) - 0.000 - 9.121 - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N25859 + net (fanout=11) + 0.771 + 5.619 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] - - + - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_6[12]/I0 (GTP_MUX2LUT6) + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/CLKA (GTP_DDC_E1) - td - 0.000 - 9.121 - r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_6[12]/Z (GTP_MUX2LUT6) + tco + 0.464 + 6.083 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[2] (GTP_DDC_E1) - net (fanout=1) - 0.000 - 9.121 + net (fanout=8) + 0.730 + 6.813 - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336 [12] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [2] - r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[12]/D (GTP_DFF_C) + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[2] (GTP_ISERDES)
- +
Location Delay Type @@ -55149,10 +55512,10 @@ Logical Resource - Clock clk_200m (rising edge) + Clock ioclk0 (rising edge) - 5.000 - 5.000 + 2.500 + 2.500 r @@ -55160,7 +55523,7 @@ clk0.000 - 5.000 + 2.500rclk (port) @@ -55168,7 +55531,7 @@ net (fanout=1) 0.000 - 5.000 + 2.500 clk @@ -55184,7 +55547,7 @@ td 1.211 - 6.211 + 3.711 r clk_ibuf/O (GTP_INBUF) @@ -55192,7 +55555,7 @@ net (fanout=1) 1.091 - 7.302 + 4.802 nt_clk @@ -55208,31 +55571,103 @@ td 0.089 - 7.391 + 4.891 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) - 1.976 - 9.367 + net (fanout=7) + 0.605 + 5.496 - zoom_clk + ddr_clk + + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + + + + td + 0.000 + 5.496 r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[12]/CLK (GTP_DFF_C) + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + + + + net (fanout=71) + 0.847 + 6.343 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.094 + 6.437 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + + + + net (fanout=3) + 0.605 + 7.042 + + u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKIN (GTP_IOCLKBUF) + + + + td + 0.306 + 7.348 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) + + + + net (fanout=11) + 0.771 + 8.119 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + + + + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/DESCLK (GTP_ISERDES) clock pessimism 0.000 - 9.367 + 8.119 @@ -55240,15 +55675,15 @@ clock uncertainty -0.150 - 9.217 + 7.969 Setup time - 0.034 - 9.251 + -0.068 + 7.901 @@ -55257,27 +55692,27 @@ - 0.160 - 7 - 36 - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/CLK - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[11]/D + 1.165 + 9 + 10 + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[0]/CLK + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/D - clk_200m - clk_200m + eth_rxc + eth_rxc rise-rise 0.000 - 4.367 - 4.367 + 5.600 + 5.600 0.000 - 5.000 - 4.724 - 1.967 (41.6%) - 2.757 (58.4%) + 8.000 + 6.619 + 2.346 (35.4%) + 4.273 (64.6%) - Path #2: setup slack is 0.160(MET) + Path #10: setup slack is 1.165(MET) -
+
Location Delay Type @@ -55287,7 +55722,7 @@ Logical Resource - Clock clk_200m (rising edge) + Clock eth_rxc (rising edge) 0.000 0.000 @@ -55295,12 +55730,12 @@ - clk + eth_rxc 0.000 0.000 r - clk (port) + eth_rxc (port) @@ -55308,7 +55743,7 @@ 0.000 0.000 - clk + eth_rxc @@ -55316,7 +55751,7 @@ - clk_ibuf/I (GTP_INBUF) + eth_rxc_ibuf/I (GTP_INBUF) @@ -55324,15 +55759,15 @@ 1.211 1.211 r - clk_ibuf/O (GTP_INBUF) + eth_rxc_ibuf/O (GTP_INBUF) - net (fanout=1) - 1.091 - 2.302 + net (fanout=2) + 1.180 + 2.391 - nt_clk + nt_eth_rxc @@ -55340,71 +55775,71 @@ - u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKIN (GTP_IOCLKDELAY) td - 0.089 - 2.391 + 0.549 + 2.940 r - u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKOUT (GTP_IOCLKDELAY) - net (fanout=851) - 1.976 - 4.367 + net (fanout=1) + 0.464 + 3.404 - zoom_clk + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf - r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/CLK (GTP_DFF_CE) + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKIN (GTP_CLKBUFG) - - tco - 0.329 - 4.696 + + td + 0.000 + 3.404 r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/Q (GTP_DFF_CE) + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKOUT (GTP_CLKBUFG) - net (fanout=36) - 0.958 - 5.654 - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/wr_addr [0] + net (fanout=1988) + 2.196 + 5.600 + + gmii_clk - - + - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N2_2/I1 (GTP_LUT5CARRY) + r + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[0]/CLK (GTP_DFF_CE) - td - 0.298 - 5.952 - f - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N2_2/COUT (GTP_LUT5CARRY) + tco + 0.329 + 5.929 + r + udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[0]/Q (GTP_DFF_CE) net (fanout=1) - 0.000 - 5.952 + 0.464 + 6.393 - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16324 + udp_osd_inst/eth_udp_inst/udp_rx_pkt_dest_port [0] @@ -55412,23 +55847,23 @@ - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N2_3/CIN (GTP_LUT5CARRY) + udp_osd_inst/eth_udp_inst/N72_18/I0 (GTP_LUT5) td - 0.236 - 6.188 - r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N2_3/Z (GTP_LUT5CARRY) + 0.318 + 6.711 + f + udp_osd_inst/eth_udp_inst/N72_18/Z (GTP_LUT5) - net (fanout=4) - 0.641 - 6.829 + net (fanout=1) + 0.464 + 7.175 - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N2 [2] + udp_osd_inst/eth_udp_inst/_N105154 @@ -55436,23 +55871,23 @@ - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[2]/I2 (GTP_LUT3) + udp_osd_inst/eth_udp_inst/N72_19/I4 (GTP_LUT5) td 0.185 - 7.014 + 7.360 r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[2]/Z (GTP_LUT3) + udp_osd_inst/eth_udp_inst/N72_19/Z (GTP_LUT5) - net (fanout=3) - 0.605 - 7.619 + net (fanout=2) + 0.553 + 7.913 - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wwptr [2] + _N98118 @@ -55460,23 +55895,23 @@ - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_3/I2 (GTP_LUT5CARRY) + udp_osd_inst/eth_udp_inst/N72_25/I3 (GTP_LUT4) td - 0.258 - 7.877 - f - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_3/COUT (GTP_LUT5CARRY) + 0.185 + 8.098 + r + udp_osd_inst/eth_udp_inst/N72_25/Z (GTP_LUT4) - net (fanout=1) - 0.000 - 7.877 + net (fanout=2) + 0.553 + 8.651 - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [3] + udp_osd_inst/eth_udp_inst/_N107744 @@ -55484,23 +55919,23 @@ - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_4/CIN (GTP_LUT5CARRY) + udp_osd_inst/eth_udp_inst/N72_26/I4 (GTP_LUT5) td - 0.030 - 7.907 + 0.185 + 8.836 r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_4/COUT (GTP_LUT5CARRY) + udp_osd_inst/eth_udp_inst/N72_26/Z (GTP_LUT5) - net (fanout=1) - 0.000 - 7.907 + net (fanout=2) + 0.553 + 9.389 - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [4] + udp_osd_inst/eth_udp_inst/N72 @@ -55508,23 +55943,23 @@ - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_5/CIN (GTP_LUT5CARRY) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N10/I2 (GTP_LUT3) td - 0.030 - 7.937 + 0.185 + 9.574 r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_5/COUT (GTP_LUT5CARRY) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N10/Z (GTP_LUT3) - net (fanout=1) - 0.000 - 7.937 + net (fanout=10) + 0.758 + 10.332 - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [5] + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/fifo_wr_en @@ -55532,23 +55967,23 @@ - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_6/CIN (GTP_LUT5CARRY) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[1]_1/I0 (GTP_LUT5) td - 0.030 - 7.967 + 0.185 + 10.517 r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_6/COUT (GTP_LUT5CARRY) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[1]_1/Z (GTP_LUT5) net (fanout=1) - 0.000 - 7.967 + 0.464 + 10.981 - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [6] + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N109270 @@ -55556,23 +55991,23 @@ - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_7/CIN (GTP_LUT5CARRY) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167.eq_0/I3 (GTP_LUT5CARRY) td - 0.030 - 7.997 - r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_7/COUT (GTP_LUT5CARRY) + 0.233 + 11.214 + f + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167.eq_0/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 7.997 + 11.214 - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [7] + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167.co [0] @@ -55580,23 +56015,23 @@ - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_8/CIN (GTP_LUT5CARRY) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167.eq_1/CIN (GTP_LUT5CARRY) td 0.030 - 8.027 + 11.244 r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_8/COUT (GTP_LUT5CARRY) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167.eq_1/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 8.027 + 11.244 - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [8] + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167.co [2] @@ -55604,23 +56039,23 @@ - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_9/CIN (GTP_LUT5CARRY) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167.eq_2/CIN (GTP_LUT5CARRY) td 0.030 - 8.057 + 11.274 r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_9/COUT (GTP_LUT5CARRY) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167.eq_2/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 8.057 + 11.274 - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [9] + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167.co [4] @@ -55628,23 +56063,23 @@ - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_10/CIN (GTP_LUT5CARRY) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167.eq_3/CIN (GTP_LUT5CARRY) td 0.030 - 8.087 + 11.304 r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_10/COUT (GTP_LUT5CARRY) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167.eq_3/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 8.087 + 11.304 - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [10] + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167.co [6] @@ -55652,23 +56087,23 @@ - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_11/CIN (GTP_LUT5CARRY) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167.eq_4/CIN (GTP_LUT5CARRY) td 0.030 - 8.117 + 11.334 r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_11/COUT (GTP_LUT5CARRY) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167.eq_4/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 8.117 + 11.334 - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [11] + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167.co [8] @@ -55676,47 +56111,23 @@ - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_12/CIN (GTP_LUT5CARRY) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167.eq_5/CIN (GTP_LUT5CARRY) td 0.236 - 8.353 - r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_12/Z (GTP_LUT5CARRY) - - - - net (fanout=2) - 0.553 - 8.906 - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/nb6 [11] - - - - - - - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_5[11]/I2 (GTP_LUT4) - - - - td - 0.185 - 9.091 + 11.570 r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_5[11]/Z (GTP_LUT4) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167.eq_5/Z (GTP_LUT5CARRY) net (fanout=1) - 0.000 - 9.091 + 0.464 + 12.034 - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N25858 + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167 @@ -55724,23 +56135,23 @@ - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_6[11]/I0 (GTP_MUX2LUT6) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N168/I0 (GTP_LUT3) td - 0.000 - 9.091 + 0.185 + 12.219 r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_6[11]/Z (GTP_MUX2LUT6) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N168/Z (GTP_LUT3) net (fanout=1) 0.000 - 9.091 + 12.219 - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336 [11] + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N168 @@ -55748,12 +56159,12 @@ r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[11]/D (GTP_DFF_C) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/D (GTP_DFF_C)
- +
Location Delay Type @@ -55763,28 +56174,28 @@ Logical Resource - Clock clk_200m (rising edge) + Clock eth_rxc (rising edge) - 5.000 - 5.000 + 8.000 + 8.000 r - clk + eth_rxc 0.000 - 5.000 + 8.000 r - clk (port) + eth_rxc (port) net (fanout=1) 0.000 - 5.000 + 8.000 - clk + eth_rxc @@ -55792,23 +56203,47 @@ - clk_ibuf/I (GTP_INBUF) + eth_rxc_ibuf/I (GTP_INBUF) td 1.211 - 6.211 + 9.211 r - clk_ibuf/O (GTP_INBUF) + eth_rxc_ibuf/O (GTP_INBUF) + + + + net (fanout=2) + 1.180 + 10.391 + + nt_eth_rxc + + + + + + + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKIN (GTP_IOCLKDELAY) + + + + td + 0.549 + 10.940 + r + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKOUT (GTP_IOCLKDELAY) net (fanout=1) - 1.091 - 7.302 + 0.464 + 11.404 - nt_clk + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf @@ -55816,23 +56251,23 @@ - u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKIN (GTP_CLKBUFG) td - 0.089 - 7.391 + 0.000 + 11.404 r - u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKOUT (GTP_CLKBUFG) - net (fanout=851) - 1.976 - 9.367 + net (fanout=1988) + 2.196 + 13.600 - zoom_clk + gmii_clk @@ -55840,21 +56275,21 @@ r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[11]/CLK (GTP_DFF_C) + udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/CLK (GTP_DFF_C) clock pessimism 0.000 - 9.367 + 13.600 clock uncertainty - -0.150 - 9.217 + -0.250 + 13.350 @@ -55862,7 +56297,7 @@ Setup time 0.034 - 9.251 + 13.384 @@ -55871,27 +56306,27 @@ - 0.190 + 1.167 7 - 36 - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/CLK - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[10]/D + 16 + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[11]/CLK + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[0]/CE - clk_200m - clk_200m + eth_rxc + eth_rxc rise-rise 0.000 - 4.367 - 4.367 + 5.600 + 5.600 0.000 - 5.000 - 4.694 - 1.937 (41.3%) - 2.757 (58.7%) + 8.000 + 6.041 + 1.789 (29.6%) + 4.252 (70.4%) - Path #3: setup slack is 0.190(MET) + Path #11: setup slack is 1.167(MET) -
+
Location Delay Type @@ -55901,7 +56336,7 @@ Logical Resource - Clock clk_200m (rising edge) + Clock eth_rxc (rising edge) 0.000 0.000 @@ -55909,12 +56344,12 @@ - clk + eth_rxc 0.000 0.000 r - clk (port) + eth_rxc (port) @@ -55922,7 +56357,7 @@ 0.000 0.000 - clk + eth_rxc @@ -55930,7 +56365,7 @@ - clk_ibuf/I (GTP_INBUF) + eth_rxc_ibuf/I (GTP_INBUF) @@ -55938,15 +56373,15 @@ 1.211 1.211 r - clk_ibuf/O (GTP_INBUF) + eth_rxc_ibuf/O (GTP_INBUF) - net (fanout=1) - 1.091 - 2.302 + net (fanout=2) + 1.180 + 2.391 - nt_clk + nt_eth_rxc @@ -55954,71 +56389,71 @@ - u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKIN (GTP_IOCLKDELAY) td - 0.089 - 2.391 + 0.549 + 2.940 r - u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKOUT (GTP_IOCLKDELAY) - net (fanout=851) - 1.976 - 4.367 + net (fanout=1) + 0.464 + 3.404 - zoom_clk + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf - r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/CLK (GTP_DFF_CE) + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKIN (GTP_CLKBUFG) - - tco - 0.329 - 4.696 + + td + 0.000 + 3.404 r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/Q (GTP_DFF_CE) + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKOUT (GTP_CLKBUFG) - net (fanout=36) - 0.958 - 5.654 - - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/wr_addr [0] + net (fanout=1988) + 2.196 + 5.600 + + gmii_clk - - + - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N2_2/I1 (GTP_LUT5CARRY) + r + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[11]/CLK (GTP_DFF_CE) - td - 0.298 - 5.952 - f - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N2_2/COUT (GTP_LUT5CARRY) + tco + 0.329 + 5.929 + r + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[11]/Q (GTP_DFF_CE) - net (fanout=1) - 0.000 - 5.952 + net (fanout=5) + 0.670 + 6.599 - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N16324 + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num [11] @@ -56026,23 +56461,23 @@ - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N2_3/CIN (GTP_LUT5CARRY) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_9/I0 (GTP_LUT4) td - 0.236 - 6.188 - r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N2_3/Z (GTP_LUT5CARRY) + 0.290 + 6.889 + f + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_9/Z (GTP_LUT4) - net (fanout=4) - 0.641 - 6.829 + net (fanout=1) + 0.464 + 7.353 - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N2 [2] + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N108528 @@ -56050,23 +56485,23 @@ - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[2]/I2 (GTP_LUT3) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_11/I4 (GTP_LUT5) td 0.185 - 7.014 + 7.538 r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N3[2]/Z (GTP_LUT3) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_11/Z (GTP_LUT5) - net (fanout=3) - 0.605 - 7.619 + net (fanout=1) + 0.464 + 8.002 - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wwptr [2] + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N108530 @@ -56074,23 +56509,23 @@ - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_3/I2 (GTP_LUT5CARRY) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_12/I4 (GTP_LUT5) td - 0.258 - 7.877 - f - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_3/COUT (GTP_LUT5CARRY) + 0.185 + 8.187 + r + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_12/Z (GTP_LUT5) - net (fanout=1) - 0.000 - 7.877 + net (fanout=16) + 0.819 + 9.006 - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [3] + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3 @@ -56098,23 +56533,23 @@ - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_4/CIN (GTP_LUT5CARRY) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[1]/I0 (GTP_LUT2) td - 0.030 - 7.907 + 0.185 + 9.191 r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_4/COUT (GTP_LUT5CARRY) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[1]/Z (GTP_LUT2) net (fanout=1) - 0.000 - 7.907 + 0.464 + 9.655 - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [4] + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N348 [1] @@ -56122,23 +56557,23 @@ - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_5/CIN (GTP_LUT5CARRY) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_0/I2 (GTP_LUT5CARRY) td - 0.030 - 7.937 - r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_5/COUT (GTP_LUT5CARRY) + 0.233 + 9.888 + f + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_0/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 7.937 + 9.888 - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [5] + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.co [0] @@ -56146,23 +56581,23 @@ - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_6/CIN (GTP_LUT5CARRY) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_1/CIN (GTP_LUT5CARRY) td 0.030 - 7.967 + 9.918 r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_6/COUT (GTP_LUT5CARRY) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_1/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 7.967 + 9.918 - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [6] + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.co [2] @@ -56170,23 +56605,23 @@ - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_7/CIN (GTP_LUT5CARRY) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_2/CIN (GTP_LUT5CARRY) td 0.030 - 7.997 + 9.948 r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_7/COUT (GTP_LUT5CARRY) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_2/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 7.997 + 9.948 - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [7] + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.co [4] @@ -56194,23 +56629,23 @@ - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_8/CIN (GTP_LUT5CARRY) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_3/CIN (GTP_LUT5CARRY) td 0.030 - 8.027 + 9.978 r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_8/COUT (GTP_LUT5CARRY) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_3/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 8.027 + 9.978 - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [8] + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.co [6] @@ -56218,23 +56653,23 @@ - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_9/CIN (GTP_LUT5CARRY) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_4/CIN (GTP_LUT5CARRY) td 0.030 - 8.057 + 10.008 r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_9/COUT (GTP_LUT5CARRY) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_4/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 8.057 + 10.008 - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [9] + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.co [8] @@ -56242,23 +56677,23 @@ - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_10/CIN (GTP_LUT5CARRY) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_5/CIN (GTP_LUT5CARRY) td 0.030 - 8.087 + 10.038 r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_10/COUT (GTP_LUT5CARRY) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_5/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 8.087 + 10.038 - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [10] + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.co [10] @@ -56266,23 +56701,23 @@ - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_11/CIN (GTP_LUT5CARRY) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_6/CIN (GTP_LUT5CARRY) td - 0.236 - 8.323 + 0.030 + 10.068 r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_11/Z (GTP_LUT5CARRY) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_6/COUT (GTP_LUT5CARRY) - net (fanout=2) - 0.553 - 8.876 + net (fanout=1) + 0.000 + 10.068 - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/nb6 [10] + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.co [12] @@ -56290,23 +56725,23 @@ - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_5[10]/I2 (GTP_LUT4) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_7/CIN (GTP_LUT5CARRY) td - 0.185 - 9.061 + 0.030 + 10.098 r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_5[10]/Z (GTP_LUT4) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_7/COUT (GTP_LUT5CARRY) - net (fanout=1) - 0.000 - 9.061 + net (fanout=8) + 0.730 + 10.828 - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/_N25857 + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349 @@ -56314,36 +56749,36 @@ - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_6[10]/I0 (GTP_MUX2LUT6) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1094_3/I2 (GTP_LUT4) td - 0.000 - 9.061 - r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_6[10]/Z (GTP_MUX2LUT6) + 0.172 + 11.000 + f + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1094_3/Z (GTP_LUT4) - net (fanout=1) - 0.000 - 9.061 + net (fanout=16) + 0.641 + 11.641 - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336 [10] + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1094 - r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[10]/D (GTP_DFF_C) + f + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[0]/CE (GTP_DFF_CE)
- +
Location Delay Type @@ -56353,28 +56788,28 @@ Logical Resource - Clock clk_200m (rising edge) + Clock eth_rxc (rising edge) - 5.000 - 5.000 + 8.000 + 8.000 r - clk + eth_rxc 0.000 - 5.000 + 8.000 r - clk (port) + eth_rxc (port) net (fanout=1) 0.000 - 5.000 + 8.000 - clk + eth_rxc @@ -56382,23 +56817,47 @@ - clk_ibuf/I (GTP_INBUF) + eth_rxc_ibuf/I (GTP_INBUF) td 1.211 - 6.211 + 9.211 r - clk_ibuf/O (GTP_INBUF) + eth_rxc_ibuf/O (GTP_INBUF) + + + + net (fanout=2) + 1.180 + 10.391 + + nt_eth_rxc + + + + + + + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKIN (GTP_IOCLKDELAY) + + + + td + 0.549 + 10.940 + r + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKOUT (GTP_IOCLKDELAY) net (fanout=1) - 1.091 - 7.302 + 0.464 + 11.404 - nt_clk + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf @@ -56406,23 +56865,23 @@ - u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKIN (GTP_CLKBUFG) td - 0.089 - 7.391 + 0.000 + 11.404 r - u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKOUT (GTP_CLKBUFG) - net (fanout=851) - 1.976 - 9.367 + net (fanout=1988) + 2.196 + 13.600 - zoom_clk + gmii_clk @@ -56430,29 +56889,29 @@ r - u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[10]/CLK (GTP_DFF_C) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[0]/CLK (GTP_DFF_CE) clock pessimism 0.000 - 9.367 + 13.600 clock uncertainty - -0.150 - 9.217 + -0.250 + 13.350 Setup time - 0.034 - 9.251 + -0.542 + 12.808 @@ -56461,27 +56920,27 @@ - 1.088 - 0 - 8 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/CLKA - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[0] + 1.167 + 7 + 16 + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[11]/CLK + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[1]/CE - ioclk1 - ioclk1 + eth_rxc + eth_rxc rise-rise 0.000 - 7.137 - 7.137 + 5.600 + 5.600 0.000 - 2.500 - 1.194 - 0.464 (38.9%) - 0.730 (61.1%) + 8.000 + 6.041 + 1.789 (29.6%) + 4.252 (70.4%) - Path #4: setup slack is 1.088(MET) + Path #12: setup slack is 1.167(MET) -
+
Location Delay Type @@ -56491,7 +56950,7 @@ Logical Resource - Clock ioclk1 (rising edge) + Clock eth_rxc (rising edge) 0.000 0.000 @@ -56499,12 +56958,12 @@ - clk + eth_rxc 0.000 0.000 r - clk (port) + eth_rxc (port) @@ -56512,7 +56971,7 @@ 0.000 0.000 - clk + eth_rxc @@ -56520,7 +56979,7 @@ - clk_ibuf/I (GTP_INBUF) + eth_rxc_ibuf/I (GTP_INBUF) @@ -56528,63 +56987,15 @@ 1.211 1.211 r - clk_ibuf/O (GTP_INBUF) - - - - net (fanout=1) - 1.091 - 2.302 - - nt_clk + eth_rxc_ibuf/O (GTP_INBUF) - - - - - u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) - - - - td - 0.089 + net (fanout=2) + 1.180 2.391 - r - u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - - - - net (fanout=851) - 1.976 - 4.367 - - zoom_clk - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - - - - td - 0.000 - 4.367 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - - - - net (fanout=71) - 0.847 - 5.214 - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + nt_eth_rxc @@ -56592,23 +57003,23 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKIN (GTP_IOCLKDELAY) td - 0.094 - 5.308 + 0.549 + 2.940 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKOUT (GTP_IOCLKDELAY) - net (fanout=3) - 0.605 - 5.913 + net (fanout=1) + 0.464 + 3.404 - u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf @@ -56616,23 +57027,23 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKIN (GTP_IOCLKBUF) + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKIN (GTP_CLKBUFG) td - 0.306 - 6.219 + 0.000 + 3.404 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKOUT (GTP_CLKBUFG) - net (fanout=28) - 0.918 - 7.137 + net (fanout=1988) + 2.196 + 5.600 - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + gmii_clk @@ -56640,421 +57051,335 @@ r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/CLKA (GTP_DDC_E1) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[11]/CLK (GTP_DFF_CE) tco - 0.464 - 7.601 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[0] (GTP_DDC_E1) + 0.329 + 5.929 + r + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[11]/Q (GTP_DFF_CE) - net (fanout=8) - 0.730 - 8.331 + net (fanout=5) + 0.670 + 6.599 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [0] + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num [11] - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[0] (GTP_ISERDES) - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ioclk1 (rising edge) - - 2.500 - 2.500 - r - - - - clk - - 0.000 - 2.500 - r - clk (port) - - - - net (fanout=1) - 0.000 - 2.500 - - clk - - - - - - - clk_ibuf/I (GTP_INBUF) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_9/I0 (GTP_LUT4) - + td - 1.211 - 3.711 - r - clk_ibuf/O (GTP_INBUF) + 0.290 + 6.889 + f + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_9/Z (GTP_LUT4) net (fanout=1) - 1.091 - 4.802 - - nt_clk + 0.464 + 7.353 + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N108528 - + - u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_11/I4 (GTP_LUT5) - + td - 0.089 - 4.891 + 0.185 + 7.538 r - u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_11/Z (GTP_LUT5) - net (fanout=851) - 1.976 - 6.867 - - zoom_clk + net (fanout=1) + 0.464 + 8.002 + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N108530 - + - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_12/I4 (GTP_LUT5) - + td - 0.000 - 6.867 + 0.185 + 8.187 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_12/Z (GTP_LUT5) - net (fanout=71) - 0.847 - 7.714 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=16) + 0.819 + 9.006 + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3 - + - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[1]/I0 (GTP_LUT2) - + td - 0.094 - 7.808 + 0.185 + 9.191 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[1]/Z (GTP_LUT2) - net (fanout=3) - 0.605 - 8.413 - - u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + net (fanout=1) + 0.464 + 9.655 + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N348 [1] - + - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKIN (GTP_IOCLKBUF) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_0/I2 (GTP_LUT5CARRY) - + td - 0.306 - 8.719 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) + 0.233 + 9.888 + f + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_0/COUT (GTP_LUT5CARRY) - net (fanout=28) - 0.918 - 9.637 - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + net (fanout=1) + 0.000 + 9.888 + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.co [0] - + - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/DESCLK (GTP_ISERDES) + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_1/CIN (GTP_LUT5CARRY) - clock pessimism - - 0.000 - 9.637 - - + + td + 0.030 + 9.918 + r + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_1/COUT (GTP_LUT5CARRY) - clock uncertainty - - -0.150 - 9.487 - + net (fanout=1) + 0.000 + 9.918 + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.co [2] - Setup time - - -0.068 - 9.419 + - -
-
-
-
- - 1.088 - 0 - 8 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/CLKA - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[1] - - ioclk1 - ioclk1 - rise-rise - 0.000 - 7.137 - 7.137 - 0.000 - 2.500 - 1.194 - 0.464 (38.9%) - 0.730 (61.1%) - - Path #5: setup slack is 1.088(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ioclk1 (rising edge) - 0.000 - 0.000 - r + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_2/CIN (GTP_LUT5CARRY) - clk - - 0.000 - 0.000 + + td + 0.030 + 9.948 r - clk (port) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_2/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 0.000 - - clk + 9.948 + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.co [4] - + - clk_ibuf/I (GTP_INBUF) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_3/CIN (GTP_LUT5CARRY) - + td - 1.211 - 1.211 + 0.030 + 9.978 r - clk_ibuf/O (GTP_INBUF) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_3/COUT (GTP_LUT5CARRY) net (fanout=1) - 1.091 - 2.302 - - nt_clk + 0.000 + 9.978 + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.co [6] - + - u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_4/CIN (GTP_LUT5CARRY) - + td - 0.089 - 2.391 + 0.030 + 10.008 r - u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_4/COUT (GTP_LUT5CARRY) - net (fanout=851) - 1.976 - 4.367 - - zoom_clk + net (fanout=1) + 0.000 + 10.008 + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.co [8] - + - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_5/CIN (GTP_LUT5CARRY) - + td - 0.000 - 4.367 + 0.030 + 10.038 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_5/COUT (GTP_LUT5CARRY) - net (fanout=71) - 0.847 - 5.214 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=1) + 0.000 + 10.038 + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.co [10] - + - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_6/CIN (GTP_LUT5CARRY) - + td - 0.094 - 5.308 + 0.030 + 10.068 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_6/COUT (GTP_LUT5CARRY) - net (fanout=3) - 0.605 - 5.913 - - u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + net (fanout=1) + 0.000 + 10.068 + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.co [12] - + - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKIN (GTP_IOCLKBUF) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_7/CIN (GTP_LUT5CARRY) - + td - 0.306 - 6.219 + 0.030 + 10.098 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_7/COUT (GTP_LUT5CARRY) - net (fanout=28) - 0.918 - 7.137 - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + net (fanout=8) + 0.730 + 10.828 + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349 - + - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/CLKA (GTP_DDC_E1) + + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1094_3/I2 (GTP_LUT4) - tco - 0.464 - 7.601 + td + 0.172 + 11.000 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[1] (GTP_DDC_E1) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1094_3/Z (GTP_LUT4) - net (fanout=8) - 0.730 - 8.331 + net (fanout=16) + 0.641 + 11.641 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [1] + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1094 @@ -57062,12 +57387,12 @@ f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[1] (GTP_ISERDES) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[1]/CE (GTP_DFF_CE)
- +
Location Delay Type @@ -57077,28 +57402,28 @@ Logical Resource - Clock ioclk1 (rising edge) + Clock eth_rxc (rising edge) - 2.500 - 2.500 + 8.000 + 8.000 r - clk + eth_rxc 0.000 - 2.500 + 8.000 r - clk (port) + eth_rxc (port) net (fanout=1) 0.000 - 2.500 + 8.000 - clk + eth_rxc @@ -57106,23 +57431,23 @@ - clk_ibuf/I (GTP_INBUF) + eth_rxc_ibuf/I (GTP_INBUF) td 1.211 - 3.711 + 9.211 r - clk_ibuf/O (GTP_INBUF) + eth_rxc_ibuf/O (GTP_INBUF) - net (fanout=1) - 1.091 - 4.802 + net (fanout=2) + 1.180 + 10.391 - nt_clk + nt_eth_rxc @@ -57130,23 +57455,23 @@ - u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKIN (GTP_IOCLKDELAY) td - 0.089 - 4.891 + 0.549 + 10.940 r - u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKOUT (GTP_IOCLKDELAY) - net (fanout=851) - 1.976 - 6.867 + net (fanout=1) + 0.464 + 11.404 - zoom_clk + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf @@ -57154,71 +57479,23 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKIN (GTP_CLKBUFG) td 0.000 - 6.867 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - - - - net (fanout=71) - 0.847 - 7.714 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - - - - td - 0.094 - 7.808 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - - - - net (fanout=3) - 0.605 - 8.413 - - u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKIN (GTP_IOCLKBUF) - - - - td - 0.306 - 8.719 + 11.404 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKOUT (GTP_CLKBUFG) - net (fanout=28) - 0.918 - 9.637 + net (fanout=1988) + 2.196 + 13.600 - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + gmii_clk @@ -57226,29 +57503,29 @@ r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/DESCLK (GTP_ISERDES) + udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[1]/CLK (GTP_DFF_CE) clock pessimism 0.000 - 9.637 + 13.600 clock uncertainty - -0.150 - 9.487 + -0.250 + 13.350 Setup time - -0.068 - 9.419 + -0.542 + 12.808 @@ -57257,27 +57534,27 @@ - 1.088 - 0 - 8 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/CLKA - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[2] + 1.643 + 7 + 14 + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[15]/CLK + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[12]/D - ioclk1 - ioclk1 + clk_1080p60Hz + clk_1080p60Hz rise-rise 0.000 - 7.137 - 7.137 + 7.588 + 7.588 0.000 - 2.500 - 1.194 - 0.464 (38.9%) - 0.730 (61.1%) + 6.736 + 4.977 + 1.936 (38.9%) + 3.041 (61.1%) - Path #6: setup slack is 1.088(MET) + Path #13: setup slack is 1.643(MET) -
+
Location Delay Type @@ -57287,7 +57564,7 @@ Logical Resource - Clock ioclk1 (rising edge) + Clock clk_1080p60Hz (rising edge) 0.000 0.000 @@ -57345,42 +57622,18 @@ td - 0.089 - 2.391 - r - u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - - - - net (fanout=851) - 1.976 - 4.367 - - zoom_clk - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - - - - td - 0.000 - 4.367 + 0.094 + 2.396 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=71) - 0.847 - 5.214 + net (fanout=2825) + 3.127 + 5.523 - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + rd3_clk @@ -57388,482 +57641,444 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 - 5.308 + 5.617 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) - 0.605 - 5.913 + net (fanout=844) + 1.971 + 7.588 - u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + zoom_clk - - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKIN (GTP_IOCLKBUF) + r + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[15]/CLK (GTP_DFF_C) - - td - 0.306 - 6.219 + + tco + 0.329 + 7.917 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[15]/Q (GTP_DFF_C) - net (fanout=28) - 0.918 - 7.137 - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + net (fanout=14) + 0.802 + 8.719 + + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2 [15] - + - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/CLKA (GTP_DDC_E1) + + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_16/I4 (GTP_LUT5) - tco - 0.464 - 7.601 + td + 0.283 + 9.002 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[2] (GTP_DDC_E1) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_16/Z (GTP_LUT5) - net (fanout=8) - 0.730 - 8.331 + net (fanout=1) + 0.464 + 9.466 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [2] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr [11] - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[2] (GTP_ISERDES) - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ioclk1 (rising edge) - - 2.500 - 2.500 - r + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_22/I0 (GTP_LUT5) - clk - - 0.000 - 2.500 + + td + 0.185 + 9.651 r - clk (port) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_22/Z (GTP_LUT5) - net (fanout=1) - 0.000 - 2.500 - - clk + net (fanout=10) + 0.758 + 10.409 + + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr [7] - + - clk_ibuf/I (GTP_INBUF) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_14/I0 (GTP_LUT3) - + td - 1.211 - 3.711 + 0.185 + 10.594 r - clk_ibuf/O (GTP_INBUF) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_14/Z (GTP_LUT3) - net (fanout=1) - 1.091 - 4.802 - - nt_clk + net (fanout=2) + 0.553 + 11.147 + + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr [1] - + - u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_2/I2 (GTP_LUT5CARRY) - + td - 0.089 - 4.891 - r - u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + 0.233 + 11.380 + f + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_2/COUT (GTP_LUT5CARRY) - net (fanout=851) - 1.976 - 6.867 - - zoom_clk + net (fanout=1) + 0.000 + 11.380 + + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [2] - + - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_3/CIN (GTP_LUT5CARRY) - + td - 0.000 - 6.867 + 0.030 + 11.410 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_3/COUT (GTP_LUT5CARRY) - net (fanout=71) - 0.847 - 7.714 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=1) + 0.000 + 11.410 + + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [3] - + - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_4/CIN (GTP_LUT5CARRY) - + td - 0.094 - 7.808 + 0.030 + 11.440 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_4/COUT (GTP_LUT5CARRY) - net (fanout=3) - 0.605 - 8.413 - - u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + net (fanout=1) + 0.000 + 11.440 + + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [4] - + - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKIN (GTP_IOCLKBUF) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_5/CIN (GTP_LUT5CARRY) - + td - 0.306 - 8.719 + 0.030 + 11.470 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_5/COUT (GTP_LUT5CARRY) - net (fanout=28) - 0.918 - 9.637 - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + net (fanout=1) + 0.000 + 11.470 + + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [5] - + + + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_6/CIN (GTP_LUT5CARRY) + + + + td + 0.030 + 11.500 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/DESCLK (GTP_ISERDES) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_6/COUT (GTP_LUT5CARRY) - clock pessimism + net (fanout=1) 0.000 - 9.637 - - + 11.500 + + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [6] - clock uncertainty + - -0.150 - 9.487 + + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_7/CIN (GTP_LUT5CARRY) - Setup time - - -0.068 - 9.419 - - + + td + 0.030 + 11.530 + r + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_7/COUT (GTP_LUT5CARRY) -
-
-
-
- - 1.088 - 0 - 8 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/CLKA - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[0] - - ioclk0 - ioclk0 - rise-rise - 0.000 - 6.990 - 6.990 - 0.000 - 2.500 - 1.194 - 0.464 (38.9%) - 0.730 (61.1%) - - Path #7: setup slack is 1.088(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - Clock ioclk0 (rising edge) + net (fanout=1) 0.000 - 0.000 - r + 11.530 + + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [7] + + + + + + + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_8/CIN (GTP_LUT5CARRY) - clk - - 0.000 - 0.000 + + td + 0.030 + 11.560 r - clk (port) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_8/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 0.000 - - clk + 11.560 + + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [8] - + - clk_ibuf/I (GTP_INBUF) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_9/CIN (GTP_LUT5CARRY) - + td - 1.211 - 1.211 + 0.030 + 11.590 r - clk_ibuf/O (GTP_INBUF) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_9/COUT (GTP_LUT5CARRY) net (fanout=1) - 1.091 - 2.302 - - nt_clk + 0.000 + 11.590 + + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [9] - + - u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_10/CIN (GTP_LUT5CARRY) - + td - 0.089 - 2.391 + 0.030 + 11.620 r - u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_10/COUT (GTP_LUT5CARRY) - net (fanout=851) - 1.976 - 4.367 - - zoom_clk + net (fanout=1) + 0.000 + 11.620 + + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [10] - + - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_11/CIN (GTP_LUT5CARRY) - + td - 0.000 - 4.367 + 0.030 + 11.650 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_11/COUT (GTP_LUT5CARRY) - net (fanout=71) - 0.847 - 5.214 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=1) + 0.000 + 11.650 + + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [11] - + - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_12/CIN (GTP_LUT5CARRY) - + td - 0.094 - 5.308 + 0.030 + 11.680 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_12/COUT (GTP_LUT5CARRY) - net (fanout=3) - 0.605 - 5.913 - - u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + net (fanout=1) + 0.000 + 11.680 + + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [12] - + - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKIN (GTP_IOCLKBUF) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_13/CIN (GTP_LUT5CARRY) - + td - 0.306 - 6.219 + 0.236 + 11.916 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_13/Z (GTP_LUT5CARRY) - net (fanout=11) - 0.771 - 6.990 - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + net (fanout=1) + 0.464 + 12.380 + + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/nb6 [12] - + - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/CLKA (GTP_DDC_E1) + + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_6[12]/I0 (GTP_LUT3) - tco - 0.464 - 7.454 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[0] (GTP_DDC_E1) + td + 0.185 + 12.565 + r + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_6[12]/Z (GTP_LUT3) - net (fanout=8) - 0.730 - 8.184 + net (fanout=1) + 0.000 + 12.565 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [0] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336 [12] - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[0] (GTP_ISERDES) + r + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[12]/D (GTP_DFF_C)
- +
Location Delay Type @@ -57873,10 +58088,10 @@ Logical Resource - Clock ioclk0 (rising edge) + Clock clk_1080p60Hz (rising edge) - 2.500 - 2.500 + 6.736 + 6.736 r @@ -57884,7 +58099,7 @@ clk0.000 - 2.500 + 6.736rclk (port) @@ -57892,7 +58107,7 @@ net (fanout=1) 0.000 - 2.500 + 6.736 clk @@ -57908,7 +58123,7 @@ td 1.211 - 3.711 + 7.947 r clk_ibuf/O (GTP_INBUF) @@ -57916,7 +58131,7 @@ net (fanout=1) 1.091 - 4.802 + 9.038 nt_clk @@ -57928,69 +58143,21 @@ u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) - - - td - 0.089 - 4.891 - r - u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - - - - net (fanout=851) - 1.976 - 6.867 - - zoom_clk - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - - - - td - 0.000 - 6.867 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - - - - net (fanout=71) - 0.847 - 7.714 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 - 7.808 + 9.132 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) - 0.605 - 8.413 + net (fanout=2825) + 3.127 + 12.259 - u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + rd3_clk @@ -57998,23 +58165,23 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKIN (GTP_IOCLKBUF) + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) td - 0.306 - 8.719 + 0.094 + 12.353 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) + U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=11) - 0.771 - 9.490 + net (fanout=844) + 1.971 + 14.324 - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + zoom_clk @@ -58022,13 +58189,13 @@ r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/DESCLK (GTP_ISERDES) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[12]/CLK (GTP_DFF_C) clock pessimism 0.000 - 9.490 + 14.324 @@ -58036,15 +58203,15 @@ clock uncertainty -0.150 - 9.340 + 14.174 Setup time - -0.068 - 9.272 + 0.034 + 14.208 @@ -58053,27 +58220,27 @@ - 1.088 - 0 - 8 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/CLKA - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[1] + 1.673 + 7 + 14 + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[15]/CLK + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[11]/D - ioclk0 - ioclk0 + clk_1080p60Hz + clk_1080p60Hz rise-rise 0.000 - 6.990 - 6.990 + 7.588 + 7.588 0.000 - 2.500 - 1.194 - 0.464 (38.9%) - 0.730 (61.1%) + 6.736 + 4.947 + 1.906 (38.5%) + 3.041 (61.5%) - Path #8: setup slack is 1.088(MET) + Path #14: setup slack is 1.673(MET) -
+
Location Delay Type @@ -58083,7 +58250,7 @@ Logical Resource - Clock ioclk0 (rising edge) + Clock clk_1080p60Hz (rising edge) 0.000 0.000 @@ -58138,69 +58305,21 @@ u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) - - - td - 0.089 - 2.391 - r - u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - - - - net (fanout=851) - 1.976 - 4.367 - - zoom_clk - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - - - - td - 0.000 - 4.367 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - - - - net (fanout=71) - 0.847 - 5.214 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 - 5.308 + 2.396 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) - 0.605 - 5.913 + net (fanout=2825) + 3.127 + 5.523 - u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + rd3_clk @@ -58208,23 +58327,23 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKIN (GTP_IOCLKBUF) + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) td - 0.306 - 6.219 + 0.094 + 5.617 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) + U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=11) - 0.771 - 6.990 + net (fanout=844) + 1.971 + 7.588 - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + zoom_clk @@ -58232,434 +58351,396 @@ r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/CLKA (GTP_DDC_E1) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[15]/CLK (GTP_DFF_C) tco - 0.464 - 7.454 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[1] (GTP_DDC_E1) + 0.329 + 7.917 + r + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[15]/Q (GTP_DFF_C) - net (fanout=8) - 0.730 - 8.184 + net (fanout=14) + 0.802 + 8.719 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [1] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2 [15] - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[1] (GTP_ISERDES) - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock ioclk0 (rising edge) - - 2.500 - 2.500 - r + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_16/I4 (GTP_LUT5) - clk - - 0.000 - 2.500 - r - clk (port) + + td + 0.283 + 9.002 + f + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_16/Z (GTP_LUT5) net (fanout=1) - 0.000 - 2.500 - - clk + 0.464 + 9.466 + + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr [11] - + - clk_ibuf/I (GTP_INBUF) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_22/I0 (GTP_LUT5) - + td - 1.211 - 3.711 + 0.185 + 9.651 r - clk_ibuf/O (GTP_INBUF) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_22/Z (GTP_LUT5) - net (fanout=1) - 1.091 - 4.802 - - nt_clk + net (fanout=10) + 0.758 + 10.409 + + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr [7] - + - u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_14/I0 (GTP_LUT3) - + td - 0.089 - 4.891 + 0.185 + 10.594 r - u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_14/Z (GTP_LUT3) - net (fanout=851) - 1.976 - 6.867 - - zoom_clk + net (fanout=2) + 0.553 + 11.147 + + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr [1] - + - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_2/I2 (GTP_LUT5CARRY) - + td - 0.000 - 6.867 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + 0.233 + 11.380 + f + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_2/COUT (GTP_LUT5CARRY) - net (fanout=71) - 0.847 - 7.714 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=1) + 0.000 + 11.380 + + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [2] - + - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_3/CIN (GTP_LUT5CARRY) - + td - 0.094 - 7.808 + 0.030 + 11.410 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_3/COUT (GTP_LUT5CARRY) - net (fanout=3) - 0.605 - 8.413 - - u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + net (fanout=1) + 0.000 + 11.410 + + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [3] - + - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKIN (GTP_IOCLKBUF) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_4/CIN (GTP_LUT5CARRY) - + td - 0.306 - 8.719 + 0.030 + 11.440 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_4/COUT (GTP_LUT5CARRY) - net (fanout=11) - 0.771 - 9.490 - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + net (fanout=1) + 0.000 + 11.440 + + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [4] - + + + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_5/CIN (GTP_LUT5CARRY) + + + + td + 0.030 + 11.470 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/DESCLK (GTP_ISERDES) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_5/COUT (GTP_LUT5CARRY) - clock pessimism + net (fanout=1) 0.000 - 9.490 - - + 11.470 + + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [5] - clock uncertainty + + - -0.150 - 9.340 + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_6/CIN (GTP_LUT5CARRY) - Setup time - - -0.068 - 9.272 - - + + td + 0.030 + 11.500 + r + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_6/COUT (GTP_LUT5CARRY) -
-
-
-
- - 1.088 - 0 - 8 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/CLKA - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[2] - - ioclk0 - ioclk0 - rise-rise - 0.000 - 6.990 - 6.990 - 0.000 - 2.500 - 1.194 - 0.464 (38.9%) - 0.730 (61.1%) - - Path #9: setup slack is 1.088(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - Clock ioclk0 (rising edge) + net (fanout=1) 0.000 - 0.000 - r + 11.500 + + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [6] + + + + + + + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_7/CIN (GTP_LUT5CARRY) - clk - - 0.000 - 0.000 + + td + 0.030 + 11.530 r - clk (port) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_7/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 0.000 - - clk + 11.530 + + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [7] - + - clk_ibuf/I (GTP_INBUF) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_8/CIN (GTP_LUT5CARRY) - + td - 1.211 - 1.211 + 0.030 + 11.560 r - clk_ibuf/O (GTP_INBUF) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_8/COUT (GTP_LUT5CARRY) net (fanout=1) - 1.091 - 2.302 - - nt_clk + 0.000 + 11.560 + + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [8] - + - u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_9/CIN (GTP_LUT5CARRY) - + td - 0.089 - 2.391 + 0.030 + 11.590 r - u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_9/COUT (GTP_LUT5CARRY) - net (fanout=851) - 1.976 - 4.367 - - zoom_clk + net (fanout=1) + 0.000 + 11.590 + + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [9] - + - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_10/CIN (GTP_LUT5CARRY) - + td - 0.000 - 4.367 + 0.030 + 11.620 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_10/COUT (GTP_LUT5CARRY) - net (fanout=71) - 0.847 - 5.214 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + net (fanout=1) + 0.000 + 11.620 + + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [10] - + - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_11/CIN (GTP_LUT5CARRY) - + td - 0.094 - 5.308 + 0.030 + 11.650 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_11/COUT (GTP_LUT5CARRY) - net (fanout=3) - 0.605 - 5.913 - - u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + net (fanout=1) + 0.000 + 11.650 + + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.co [11] - + - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKIN (GTP_IOCLKBUF) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_12/CIN (GTP_LUT5CARRY) - + td - 0.306 - 6.219 + 0.236 + 11.886 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_7.fsub_12/Z (GTP_LUT5CARRY) - net (fanout=11) - 0.771 - 6.990 - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + net (fanout=1) + 0.464 + 12.350 + + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/nb6 [11] - + - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/CLKA (GTP_DDC_E1) + + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_6[11]/I0 (GTP_LUT3) - tco - 0.464 - 7.454 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[2] (GTP_DDC_E1) + td + 0.185 + 12.535 + r + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336_6[11]/Z (GTP_LUT3) - net (fanout=8) - 0.730 - 8.184 + net (fanout=1) + 0.000 + 12.535 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [2] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N336 [11] - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[2] (GTP_ISERDES) + r + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[11]/D (GTP_DFF_C)
- +
Location Delay Type @@ -58669,10 +58750,10 @@ Logical Resource - Clock ioclk0 (rising edge) + Clock clk_1080p60Hz (rising edge) - 2.500 - 2.500 + 6.736 + 6.736 r @@ -58680,7 +58761,7 @@ clk0.000 - 2.500 + 6.736rclk (port) @@ -58688,7 +58769,7 @@ net (fanout=1) 0.000 - 2.500 + 6.736 clk @@ -58704,7 +58785,7 @@ td 1.211 - 3.711 + 7.947 r clk_ibuf/O (GTP_INBUF) @@ -58712,7 +58793,7 @@ net (fanout=1) 1.091 - 4.802 + 9.038 nt_clk @@ -58724,69 +58805,21 @@ u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) - - - td - 0.089 - 4.891 - r - u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - - - - net (fanout=851) - 1.976 - 6.867 - - zoom_clk - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - - - - td - 0.000 - 6.867 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - - - - net (fanout=71) - 0.847 - 7.714 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 - 7.808 + 9.132 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) - 0.605 - 8.413 + net (fanout=2825) + 3.127 + 12.259 - u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + rd3_clk @@ -58794,23 +58827,23 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKIN (GTP_IOCLKBUF) + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) td - 0.306 - 8.719 + 0.094 + 12.353 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) + U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=11) - 0.771 - 9.490 + net (fanout=844) + 1.971 + 14.324 - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + zoom_clk @@ -58818,13 +58851,13 @@ r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/DESCLK (GTP_ISERDES) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[11]/CLK (GTP_DFF_C) clock pessimism 0.000 - 9.490 + 14.324 @@ -58832,15 +58865,15 @@ clock uncertainty -0.150 - 9.340 + 14.174 Setup time - -0.068 - 9.272 + 0.034 + 14.208 @@ -58849,27 +58882,27 @@ - 1.165 - 9 - 10 - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[0]/CLK - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/D + 1.698 + 6 + 14 + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[15]/CLK + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/D - eth_rxc - eth_rxc + clk_1080p60Hz + clk_1080p60Hz rise-rise 0.000 - 5.600 - 5.600 + 7.588 + 7.588 0.000 - 8.000 - 6.619 - 2.346 (35.4%) - 4.273 (64.6%) + 6.736 + 4.922 + 1.881 (38.2%) + 3.041 (61.8%) - Path #10: setup slack is 1.165(MET) + Path #15: setup slack is 1.698(MET) -
+
Location Delay Type @@ -58879,7 +58912,7 @@ Logical Resource - Clock eth_rxc (rising edge) + Clock clk_1080p60Hz (rising edge) 0.000 0.000 @@ -58887,12 +58920,12 @@ - eth_rxc + clk 0.000 0.000 r - eth_rxc (port) + clk (port) @@ -58900,7 +58933,7 @@ 0.000 0.000 - eth_rxc + clk @@ -58908,7 +58941,7 @@ - eth_rxc_ibuf/I (GTP_INBUF) + clk_ibuf/I (GTP_INBUF) @@ -58916,15 +58949,15 @@ 1.211 1.211 r - eth_rxc_ibuf/O (GTP_INBUF) + clk_ibuf/O (GTP_INBUF) - net (fanout=2) - 1.180 - 2.391 + net (fanout=1) + 1.091 + 2.302 - nt_eth_rxc + nt_clk @@ -58932,23 +58965,23 @@ - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKIN (GTP_IOCLKDELAY) + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td - 0.549 - 2.940 + 0.094 + 2.396 r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKOUT (GTP_IOCLKDELAY) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=1) - 0.464 - 3.404 + net (fanout=2825) + 3.127 + 5.523 - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf + rd3_clk @@ -58956,23 +58989,23 @@ - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKIN (GTP_CLKBUFG) + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) td - 0.000 - 3.404 + 0.094 + 5.617 r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKOUT (GTP_CLKBUFG) + U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=1988) - 2.196 - 5.600 + net (fanout=844) + 1.971 + 7.588 - gmii_clk + zoom_clk @@ -58980,23 +59013,23 @@ r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[0]/CLK (GTP_DFF_CE) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[15]/CLK (GTP_DFF_C) tco 0.329 - 5.929 + 7.917 r - udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/udp_dest_port[0]/Q (GTP_DFF_CE) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2[15]/Q (GTP_DFF_C) - net (fanout=1) - 0.464 - 6.393 + net (fanout=14) + 0.802 + 8.719 - udp_osd_inst/eth_udp_inst/udp_rx_pkt_dest_port [0] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr2 [15] @@ -59004,47 +59037,23 @@ - udp_osd_inst/eth_udp_inst/N72_16/I0 (GTP_LUT5) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_16/I4 (GTP_LUT5) td - 0.318 - 6.711 + 0.283 + 9.002 f - udp_osd_inst/eth_udp_inst/N72_16/Z (GTP_LUT5) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_16/Z (GTP_LUT5) net (fanout=1) 0.464 - 7.175 - - udp_osd_inst/eth_udp_inst/_N104315 - - - - - - - - udp_osd_inst/eth_udp_inst/N72_17/I4 (GTP_LUT5) - - - - td - 0.185 - 7.360 - r - udp_osd_inst/eth_udp_inst/N72_17/Z (GTP_LUT5) - - - - net (fanout=2) - 0.553 - 7.913 + 9.466 - _N97297 + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr [11] @@ -59052,23 +59061,23 @@ - udp_osd_inst/eth_udp_inst/N72_23/I3 (GTP_LUT4) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_22/I0 (GTP_LUT5) td 0.185 - 8.098 + 9.651 r - udp_osd_inst/eth_udp_inst/N72_23/Z (GTP_LUT4) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_22/Z (GTP_LUT5) - net (fanout=2) - 0.553 - 8.651 + net (fanout=10) + 0.758 + 10.409 - udp_osd_inst/eth_udp_inst/_N106920 + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr [7] @@ -59076,23 +59085,23 @@ - udp_osd_inst/eth_udp_inst/N72_24/I4 (GTP_LUT5) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_32/I0 (GTP_LUT4) td 0.185 - 8.836 + 10.594 r - udp_osd_inst/eth_udp_inst/N72_24/Z (GTP_LUT5) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N24_32/Z (GTP_LUT4) net (fanout=2) 0.553 - 9.389 + 11.147 - udp_osd_inst/eth_udp_inst/N72 + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wrptr [0] @@ -59100,23 +59109,23 @@ - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N10/I2 (GTP_LUT3) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.eq_0/I1 (GTP_LUT5CARRY) td - 0.185 - 9.574 - r - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/N10/Z (GTP_LUT3) + 0.298 + 11.445 + f + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.eq_0/COUT (GTP_LUT5CARRY) - net (fanout=10) - 0.758 - 10.332 + net (fanout=1) + 0.000 + 11.445 - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/fifo_wr_en + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.co [0] @@ -59124,23 +59133,23 @@ - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[1]_1/I0 (GTP_LUT5) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.eq_1/CIN (GTP_LUT5CARRY) td - 0.185 - 10.517 + 0.030 + 11.475 r - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N3[1]_1/Z (GTP_LUT5) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.eq_1/COUT (GTP_LUT5CARRY) net (fanout=1) - 0.464 - 10.981 + 0.000 + 11.475 - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/_N108382 + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.co [2] @@ -59148,23 +59157,23 @@ - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167.eq_0/I3 (GTP_LUT5CARRY) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.eq_2/CIN (GTP_LUT5CARRY) td - 0.233 - 11.214 - f - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167.eq_0/COUT (GTP_LUT5CARRY) + 0.030 + 11.505 + r + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.eq_2/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 11.214 + 11.505 - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167.co [0] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.co [4] @@ -59172,23 +59181,23 @@ - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167.eq_1/CIN (GTP_LUT5CARRY) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.eq_3/CIN (GTP_LUT5CARRY) td 0.030 - 11.244 + 11.535 r - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167.eq_1/COUT (GTP_LUT5CARRY) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.eq_3/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 11.244 + 11.535 - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167.co [2] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.co [6] @@ -59196,23 +59205,23 @@ - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167.eq_2/CIN (GTP_LUT5CARRY) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.eq_4/CIN (GTP_LUT5CARRY) td 0.030 - 11.274 + 11.565 r - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167.eq_2/COUT (GTP_LUT5CARRY) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.eq_4/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 11.274 + 11.565 - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167.co [4] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.co [8] @@ -59220,23 +59229,23 @@ - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167.eq_3/CIN (GTP_LUT5CARRY) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.eq_5/CIN (GTP_LUT5CARRY) td 0.030 - 11.304 + 11.595 r - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167.eq_3/COUT (GTP_LUT5CARRY) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.eq_5/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 11.304 + 11.595 - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167.co [6] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.co [10] @@ -59244,23 +59253,23 @@ - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167.eq_4/CIN (GTP_LUT5CARRY) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.eq_6/CIN (GTP_LUT5CARRY) td 0.030 - 11.334 + 11.625 r - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167.eq_4/COUT (GTP_LUT5CARRY) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.eq_6/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 11.334 + 11.625 - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167.co [8] + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.co [12] @@ -59268,23 +59277,23 @@ - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167.eq_5/CIN (GTP_LUT5CARRY) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.eq_7/CIN (GTP_LUT5CARRY) td 0.236 - 11.570 + 11.861 r - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167.eq_5/Z (GTP_LUT5CARRY) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207.eq_7/Z (GTP_LUT5CARRY) net (fanout=1) 0.464 - 12.034 + 12.325 - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N167 + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N207 @@ -59292,23 +59301,23 @@ - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N168/I0 (GTP_LUT3) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N208/I1 (GTP_LUT5) td 0.185 - 12.219 + 12.510 r - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N168/Z (GTP_LUT3) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N208/Z (GTP_LUT5) net (fanout=1) 0.000 - 12.219 + 12.510 - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/N168 + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/N208 @@ -59316,12 +59325,12 @@ r - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/D (GTP_DFF_C) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/D (GTP_DFF_C)
- +
Location Delay Type @@ -59331,28 +59340,28 @@ Logical Resource - Clock eth_rxc (rising edge) + Clock clk_1080p60Hz (rising edge) - 8.000 - 8.000 + 6.736 + 6.736 r - eth_rxc + clk 0.000 - 8.000 + 6.736 r - eth_rxc (port) + clk (port) net (fanout=1) 0.000 - 8.000 + 6.736 - eth_rxc + clk @@ -59360,23 +59369,23 @@ - eth_rxc_ibuf/I (GTP_INBUF) + clk_ibuf/I (GTP_INBUF) td 1.211 - 9.211 + 7.947 r - eth_rxc_ibuf/O (GTP_INBUF) + clk_ibuf/O (GTP_INBUF) - net (fanout=2) - 1.180 - 10.391 + net (fanout=1) + 1.091 + 9.038 - nt_eth_rxc + nt_clk @@ -59384,23 +59393,23 @@ - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKIN (GTP_IOCLKDELAY) + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td - 0.549 - 10.940 + 0.094 + 9.132 r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKOUT (GTP_IOCLKDELAY) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=1) - 0.464 - 11.404 + net (fanout=2825) + 3.127 + 12.259 - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf + rd3_clk @@ -59408,23 +59417,23 @@ - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKIN (GTP_CLKBUFG) + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) td - 0.000 - 11.404 + 0.094 + 12.353 r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKOUT (GTP_CLKBUFG) + U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=1988) - 2.196 - 13.600 + net (fanout=844) + 1.971 + 14.324 - gmii_clk + zoom_clk @@ -59432,21 +59441,21 @@ r - udp_osd_inst/eth_udp_inst/udp_receive_buffer_inst/udp_rx_fifo/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/CLK (GTP_DFF_C) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/CLK (GTP_DFF_C) clock pessimism 0.000 - 13.600 + 14.324 clock uncertainty - -0.250 - 13.350 + -0.150 + 14.174 @@ -59454,7 +59463,7 @@ Setup time 0.034 - 13.384 + 14.208 @@ -59463,27 +59472,27 @@ - 1.167 - 7 - 16 - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[11]/CLK - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[0]/CE + 1.917 + 6 + 5 + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[9]/CLK + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/D - eth_rxc - eth_rxc + hdmi_in_clk + hdmi_in_clk rise-rise 0.000 - 5.600 - 5.600 + 4.415 + 4.415 0.000 - 8.000 - 6.041 - 1.789 (29.6%) - 4.252 (70.4%) + 6.666 + 4.533 + 1.741 (38.4%) + 2.792 (61.6%) - Path #11: setup slack is 1.167(MET) + Path #16: setup slack is 1.917(MET) -
+
Location Delay Type @@ -59493,7 +59502,7 @@ Logical Resource - Clock eth_rxc (rising edge) + Clock hdmi_in_clk (rising edge) 0.000 0.000 @@ -59501,12 +59510,12 @@ - eth_rxc + hdmi_in_clk 0.000 0.000 r - eth_rxc (port) + hdmi_in_clk (port) @@ -59514,7 +59523,7 @@ 0.000 0.000 - eth_rxc + hdmi_in_clk @@ -59522,7 +59531,7 @@ - eth_rxc_ibuf/I (GTP_INBUF) + hdmi_in_clk_ibuf/I (GTP_INBUF) @@ -59530,63 +59539,15 @@ 1.211 1.211 r - eth_rxc_ibuf/O (GTP_INBUF) - - - - net (fanout=2) - 1.180 - 2.391 - - nt_eth_rxc - - - - - - - - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKIN (GTP_IOCLKDELAY) - - - - td - 0.549 - 2.940 - r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKOUT (GTP_IOCLKDELAY) - - - - net (fanout=1) - 0.464 - 3.404 - - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf - - - - - - - - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKIN (GTP_CLKBUFG) - - - - td - 0.000 - 3.404 - r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKOUT (GTP_CLKBUFG) + hdmi_in_clk_ibuf/O (GTP_INBUF) - net (fanout=1988) - 2.196 - 5.600 + net (fanout=173) + 3.204 + 4.415 - gmii_clk + nt_hdmi_in_clk @@ -59594,23 +59555,23 @@ r - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[11]/CLK (GTP_DFF_CE) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[9]/CLK (GTP_DFF_C) tco 0.329 - 5.929 + 4.744 r - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[11]/Q (GTP_DFF_CE) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[9]/Q (GTP_DFF_C) - net (fanout=5) - 0.670 - 6.599 + net (fanout=4) + 0.641 + 5.385 - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num [11] + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2 [9] @@ -59618,47 +59579,23 @@ - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_9/I0 (GTP_LUT4) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_2/I0 (GTP_LUT3) td - 0.290 - 6.889 + 0.233 + 5.618 f - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_9/Z (GTP_LUT4) - - - - net (fanout=1) - 0.464 - 7.353 - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N107696 - - - - - - - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_11/I4 (GTP_LUT5) - - - - td - 0.185 - 7.538 - r - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_11/Z (GTP_LUT5) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_2/Z (GTP_LUT3) - net (fanout=1) - 0.464 - 8.002 + net (fanout=2) + 0.553 + 6.171 - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N107698 + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2_b [7] @@ -59666,23 +59603,23 @@ - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_12/I4 (GTP_LUT5) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_10/I3 (GTP_LUT4) td 0.185 - 8.187 + 6.356 r - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_12/Z (GTP_LUT5) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_10/Z (GTP_LUT4) - net (fanout=16) - 0.819 - 9.006 + net (fanout=5) + 0.670 + 7.026 - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3 + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2_b [4] @@ -59690,23 +59627,23 @@ - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[1]/I0 (GTP_LUT2) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_16/I4 (GTP_LUT5) td 0.185 - 9.191 + 7.211 r - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[1]/Z (GTP_LUT2) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_16/Z (GTP_LUT5) net (fanout=1) 0.464 - 9.655 + 7.675 - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N348 [1] + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2_b [0] @@ -59714,23 +59651,23 @@ - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_0/I2 (GTP_LUT5CARRY) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_1/I1 (GTP_LUT5CARRY) td - 0.233 - 9.888 + 0.298 + 7.973 f - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_0/COUT (GTP_LUT5CARRY) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_1/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 9.888 + 7.973 - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.co [0] + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.co [2] @@ -59738,23 +59675,23 @@ - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_1/CIN (GTP_LUT5CARRY) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_2/CIN (GTP_LUT5CARRY) td 0.030 - 9.918 + 8.003 r - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_1/COUT (GTP_LUT5CARRY) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_2/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 9.918 + 8.003 - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.co [2] + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.co [4] @@ -59762,23 +59699,23 @@ - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_2/CIN (GTP_LUT5CARRY) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_3/CIN (GTP_LUT5CARRY) td 0.030 - 9.948 + 8.033 r - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_2/COUT (GTP_LUT5CARRY) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_3/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 9.948 + 8.033 - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.co [4] + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.co [6] @@ -59786,23 +59723,23 @@ - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_3/CIN (GTP_LUT5CARRY) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_4/CIN (GTP_LUT5CARRY) td 0.030 - 9.978 + 8.063 r - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_3/COUT (GTP_LUT5CARRY) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_4/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 9.978 + 8.063 - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.co [6] + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.co [8] @@ -59810,23 +59747,23 @@ - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_4/CIN (GTP_LUT5CARRY) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_5/CIN (GTP_LUT5CARRY) td - 0.030 - 10.008 + 0.236 + 8.299 r - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_4/COUT (GTP_LUT5CARRY) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_5/Z (GTP_LUT5CARRY) net (fanout=1) - 0.000 - 10.008 + 0.464 + 8.763 - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.co [8] + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158 @@ -59834,108 +59771,150 @@ - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_5/CIN (GTP_LUT5CARRY) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N159/I4 (GTP_LUT5) td - 0.030 - 10.038 + 0.185 + 8.948 r - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_5/COUT (GTP_LUT5CARRY) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N159/Z (GTP_LUT5) net (fanout=1) 0.000 - 10.038 + 8.948 - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.co [10] + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N159 + r + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/D (GTP_DFF_C) + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock hdmi_in_clk (rising edge) + + 6.666 + 6.666 + r - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_6/CIN (GTP_LUT5CARRY) - - td - 0.030 - 10.068 + hdmi_in_clk + + 0.000 + 6.666 r - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_6/COUT (GTP_LUT5CARRY) + hdmi_in_clk (port) net (fanout=1) 0.000 - 10.068 - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.co [12] + 6.666 + + hdmi_in_clk - + - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_7/CIN (GTP_LUT5CARRY) + hdmi_in_clk_ibuf/I (GTP_INBUF) - + td - 0.030 - 10.098 + 1.211 + 7.877 r - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_7/COUT (GTP_LUT5CARRY) + hdmi_in_clk_ibuf/O (GTP_INBUF) - net (fanout=8) - 0.730 - 10.828 - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349 + net (fanout=173) + 3.204 + 11.081 + + nt_hdmi_in_clk - - + - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1094_3/I2 (GTP_LUT4) + r + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/CLK (GTP_DFF_C) - - td - 0.172 - 11.000 - f - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1094_3/Z (GTP_LUT4) + clock pessimism + + 0.000 + 11.081 + + + clock uncertainty + + -0.250 + 10.831 + - net (fanout=16) - 0.641 - 11.641 - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1094 - + Setup time + 0.034 + 10.865 - f - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[0]/CE (GTP_DFF_CE)
+
+
+ + 2.366 + 9 + 17 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[16]/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[6]/D + + ddrphy_clkin + ddrphy_clkin + rise-rise + 0.000 + 7.688 + 7.688 + 0.000 + 10.000 + 7.518 + 2.401 (31.9%) + 5.117 (68.1%) + + Path #17: setup slack is 2.366(MET) - +
Location Delay Type @@ -59945,28 +59924,28 @@ Logical Resource - Clock eth_rxc (rising edge) + Clock ddrphy_clkin (rising edge) - 8.000 - 8.000 + 0.000 + 0.000 r - eth_rxc + clk 0.000 - 8.000 + 0.000 r - eth_rxc (port) + clk (port) net (fanout=1) 0.000 - 8.000 + 0.000 - eth_rxc + clk @@ -59974,23 +59953,23 @@ - eth_rxc_ibuf/I (GTP_INBUF) + clk_ibuf/I (GTP_INBUF) td 1.211 - 9.211 + 1.211 r - eth_rxc_ibuf/O (GTP_INBUF) + clk_ibuf/O (GTP_INBUF) - net (fanout=2) - 1.180 - 10.391 + net (fanout=1) + 1.091 + 2.302 - nt_eth_rxc + nt_clk @@ -59998,23 +59977,23 @@ - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKIN (GTP_IOCLKDELAY) + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td - 0.549 - 10.940 + 0.089 + 2.391 r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKOUT (GTP_IOCLKDELAY) + u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=1) - 0.464 - 11.404 + net (fanout=7) + 0.605 + 2.996 - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf + ddr_clk @@ -60022,209 +60001,167 @@ - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKIN (GTP_CLKBUFG) + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) td 0.000 - 11.404 + 2.996 r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKOUT (GTP_CLKBUFG) + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=1988) - 2.196 - 13.600 + net (fanout=71) + 0.847 + 3.843 - gmii_clk + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - r - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[0]/CLK (GTP_DFF_CE) - - - clock pessimism - - 0.000 - 13.600 - + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - clock uncertainty - - -0.250 - 13.350 - - + + td + 0.094 + 3.937 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - Setup time - - -0.542 - 12.808 - - -
-
-
-
- - 1.167 - 7 - 16 - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[11]/CLK - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[1]/CE - - eth_rxc - eth_rxc - rise-rise - 0.000 - 5.600 - 5.600 - 0.000 - 8.000 - 6.041 - 1.789 (29.6%) - 4.252 (70.4%) - - Path #12: setup slack is 1.167(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - + net (fanout=3) + 0.605 + 4.542 + + u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + - Clock eth_rxc (rising edge) + - 0.000 - 0.000 - r + + + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) - eth_rxc + td 0.000 - 0.000 + 4.542 r - eth_rxc (port) + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) - net (fanout=1) - 0.000 - 0.000 + net (fanout=5817) + 3.146 + 7.688 - eth_rxc + u_axi_ddr_top/clk - - eth_rxc_ibuf/I (GTP_INBUF) + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[16]/CLK (GTP_DFF_CE) - - td - 1.211 - 1.211 + + tco + 0.329 + 8.017 r - eth_rxc_ibuf/O (GTP_INBUF) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[16]/Q (GTP_DFF_CE) - net (fanout=2) - 1.180 - 2.391 - - nt_eth_rxc + net (fanout=17) + 0.826 + 8.843 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [16] - + - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKIN (GTP_IOCLKDELAY) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N702_7[0]/I2 (GTP_LUT5M) - + td - 0.549 - 2.940 - r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKOUT (GTP_IOCLKDELAY) + 0.327 + 9.170 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N702_7[0]/Z (GTP_LUT5M) net (fanout=1) - 0.464 - 3.404 - - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf + 0.000 + 9.170 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N24733 - + - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKIN (GTP_CLKBUFG) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N702_8[0]/I0 (GTP_MUX2LUT6) - + td 0.000 - 3.404 - r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKOUT (GTP_CLKBUFG) + 9.170 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N702_8[0]/Z (GTP_MUX2LUT6) - net (fanout=1988) - 2.196 - 5.600 - - gmii_clk + net (fanout=4) + 0.641 + 9.811 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/cmd_pre_pass_l - + - r - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[11]/CLK (GTP_DFF_CE) + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N244/I0 (GTP_LUT2) - tco - 0.329 - 5.929 + td + 0.206 + 10.017 r - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num[11]/Q (GTP_DFF_CE) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N244/Z (GTP_LUT2) - net (fanout=5) - 0.670 - 6.599 + net (fanout=8) + 0.730 + 10.747 - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/tx_data_num [11] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_pre @@ -60232,23 +60169,23 @@ - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_9/I0 (GTP_LUT4) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N31.lt_1/I1 (GTP_LUT5CARRY) td - 0.290 - 6.889 + 0.233 + 10.980 f - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_9/Z (GTP_LUT4) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N31.lt_1/COUT (GTP_LUT5CARRY) net (fanout=1) - 0.464 - 7.353 + 0.000 + 10.980 - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N107696 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N31.co [2] @@ -60256,23 +60193,23 @@ - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_11/I4 (GTP_LUT5) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N31.lt_2/CIN (GTP_LUT5CARRY) td - 0.185 - 7.538 + 0.030 + 11.010 r - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_11/Z (GTP_LUT5) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N31.lt_2/COUT (GTP_LUT5CARRY) net (fanout=1) - 0.464 - 8.002 + 0.000 + 11.010 - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/_N107698 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N31.co [4] @@ -60280,23 +60217,23 @@ - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_12/I4 (GTP_LUT5) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N31.lt_3/CIN (GTP_LUT5CARRY) td - 0.185 - 8.187 + 0.236 + 11.246 r - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3_mux14_12/Z (GTP_LUT5) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N31.lt_3/Z (GTP_LUT5CARRY) - net (fanout=16) - 0.819 - 9.006 + net (fanout=2) + 0.553 + 11.799 - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N31 @@ -60304,23 +60241,23 @@ - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[1]/I0 (GTP_LUT2) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_51/I2 (GTP_LUT5) td 0.185 - 9.191 + 11.984 r - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N5_0[1]/Z (GTP_LUT2) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_51/Z (GTP_LUT5) - net (fanout=1) - 0.464 - 9.655 + net (fanout=9) + 0.745 + 12.729 - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N348 [1] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N24930 @@ -60328,23 +60265,23 @@ - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_0/I2 (GTP_LUT5CARRY) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_50[3]_2/I0 (GTP_LUT3) td - 0.233 - 9.888 - f - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_0/COUT (GTP_LUT5CARRY) + 0.185 + 12.914 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_50[3]_2/Z (GTP_LUT3) - net (fanout=1) - 0.000 - 9.888 + net (fanout=3) + 0.605 + 13.519 - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.co [0] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N103967_2 @@ -60352,23 +60289,23 @@ - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_1/CIN (GTP_LUT5CARRY) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_8_maj1_1/I3 (GTP_LUT5M) td - 0.030 - 9.918 - r - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_1/COUT (GTP_LUT5CARRY) + 0.300 + 13.819 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_8_maj1_1/Z (GTP_LUT5M) - net (fanout=1) - 0.000 - 9.918 + net (fanout=2) + 0.553 + 14.372 - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.co [2] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N15350 @@ -60376,23 +60313,23 @@ - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_2/CIN (GTP_LUT5CARRY) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_8_sum3_6/I0 (GTP_LUT5) td - 0.030 - 9.948 + 0.185 + 14.557 r - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_2/COUT (GTP_LUT5CARRY) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_8_sum3_6/Z (GTP_LUT5) net (fanout=1) - 0.000 - 9.948 + 0.464 + 15.021 - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.co [4] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N17304 @@ -60400,156 +60337,246 @@ - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_3/CIN (GTP_LUT5CARRY) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_2[6]_1/I0 (GTP_LUT2) td - 0.030 - 9.978 + 0.185 + 15.206 r - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_3/COUT (GTP_LUT5CARRY) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_2[6]_1/Z (GTP_LUT2) net (fanout=1) 0.000 - 9.978 + 15.206 - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.co [6] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77 [6] + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[6]/D (GTP_DFF_C) + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock ddrphy_clkin (rising edge) + + 10.000 + 10.000 + r - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_4/CIN (GTP_LUT5CARRY) - - td - 0.030 - 10.008 + clk + + 0.000 + 10.000 r - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_4/COUT (GTP_LUT5CARRY) + clk (port) net (fanout=1) 0.000 - 10.008 - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.co [8] + 10.000 + + clk - + - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_5/CIN (GTP_LUT5CARRY) + clk_ibuf/I (GTP_INBUF) - + td - 0.030 - 10.038 + 1.211 + 11.211 r - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_5/COUT (GTP_LUT5CARRY) + clk_ibuf/O (GTP_INBUF) net (fanout=1) - 0.000 - 10.038 - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.co [10] + 1.091 + 12.302 + + nt_clk - + - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_6/CIN (GTP_LUT5CARRY) + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) - + td - 0.030 - 10.068 + 0.089 + 12.391 r - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_6/COUT (GTP_LUT5CARRY) + u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=1) + net (fanout=7) + 0.605 + 12.996 + + ddr_clk + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + + + + td 0.000 - 10.068 - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.co [12] + 12.996 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - + + net (fanout=71) + 0.847 + 13.843 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_7/CIN (GTP_LUT5CARRY) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - + td - 0.030 - 10.098 + 0.094 + 13.937 r - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349.lt_7/COUT (GTP_LUT5CARRY) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=8) - 0.730 - 10.828 - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N349 + net (fanout=3) + 0.605 + 14.542 + + u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] - + - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1094_3/I2 (GTP_LUT4) + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) - + td - 0.172 - 11.000 - f - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1094_3/Z (GTP_LUT4) + 0.000 + 14.542 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) - net (fanout=16) - 0.641 - 11.641 - - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N1094 + net (fanout=5817) + 3.146 + 17.688 + + u_axi_ddr_top/clk - + - f - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[1]/CE (GTP_DFF_CE) + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[6]/CLK (GTP_DFF_C) + + + clock pessimism + + 0.000 + 17.688 + + + + + clock uncertainty + + -0.150 + 17.538 + + + + + Setup time + + 0.034 + 17.572 + +
+
+
+ + 2.404 + 8 + 575 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/calib_done/CLK + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/D + + ddrphy_clkin + ddrphy_clkin + rise-rise + 0.000 + 7.688 + 7.688 + 0.000 + 10.000 + 7.480 + 1.979 (26.5%) + 5.501 (73.5%) + + Path #18: setup slack is 2.404(MET) - +
Location Delay Type @@ -60559,238 +60586,316 @@ Logical Resource - Clock eth_rxc (rising edge) + Clock ddrphy_clkin (rising edge) - 8.000 - 8.000 + 0.000 + 0.000 r - eth_rxc + clk 0.000 - 8.000 + 0.000 r - eth_rxc (port) + clk (port) net (fanout=1) 0.000 - 8.000 + 0.000 - eth_rxc + clk + + + + + + + + clk_ibuf/I (GTP_INBUF) + + + + td + 1.211 + 1.211 + r + clk_ibuf/O (GTP_INBUF) + + + + net (fanout=1) + 1.091 + 2.302 + + nt_clk + + + + + + + + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.089 + 2.391 + r + u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + + + + net (fanout=7) + 0.605 + 2.996 + + ddr_clk + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + + + + td + 0.000 + 2.996 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + + + + net (fanout=71) + 0.847 + 3.843 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.094 + 3.937 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + + + + net (fanout=3) + 0.605 + 4.542 + + u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) + + + + td + 0.000 + 4.542 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + + + + net (fanout=5817) + 3.146 + 7.688 + + u_axi_ddr_top/clk - - eth_rxc_ibuf/I (GTP_INBUF) + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/calib_done/CLK (GTP_DFF_C) - - td - 1.211 - 9.211 + + tco + 0.329 + 8.017 r - eth_rxc_ibuf/O (GTP_INBUF) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/calib_done/Q (GTP_DFF_C) - net (fanout=2) - 1.180 - 10.391 - - nt_eth_rxc + net (fanout=575) + 2.721 + 10.738 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/calib_done - + - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKIN (GTP_IOCLKDELAY) + u_axi_ddr_top/u_axi_rd_connect/N1_2/I1 (GTP_LUT3) - + td - 0.549 - 10.940 + 0.185 + 10.923 r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKOUT (GTP_IOCLKDELAY) + u_axi_ddr_top/u_axi_rd_connect/N1_2/Z (GTP_LUT3) - net (fanout=1) - 0.464 - 11.404 - - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf + net (fanout=3) + 0.605 + 11.528 + + u_axi_ddr_top/u_axi_rd_connect/wr_en - + - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKIN (GTP_CLKBUFG) + u_axi_ddr_top/u_axi_rd_connect/N7_4/I0 (GTP_LUT4) - + td - 0.000 - 11.404 + 0.185 + 11.713 r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKOUT (GTP_CLKBUFG) + u_axi_ddr_top/u_axi_rd_connect/N7_4/Z (GTP_LUT4) - net (fanout=1988) - 2.196 - 13.600 - - gmii_clk + net (fanout=3) + 0.605 + 12.318 + + u_axi_ddr_top/u_axi_rd_connect/wr_rid_en - + - r - udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/data_cnt[1]/CLK (GTP_DFF_CE) + + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_1/I0 (GTP_LUT5CARRY) - clock pessimism - - 0.000 - 13.600 - - + + td + 0.201 + 12.519 + f + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_1/COUT (GTP_LUT5CARRY) - clock uncertainty - - -0.250 - 13.350 - + net (fanout=1) + 0.000 + 12.519 + + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/_N15759 - Setup time - - -0.542 - 12.808 + - -
-
-
-
- - 1.917 - 6 - 5 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[9]/CLK - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/D - - hdmi_in_clk - hdmi_in_clk - rise-rise - 0.000 - 4.415 - 4.415 - 0.000 - 6.666 - 4.533 - 1.741 (38.4%) - 2.792 (61.6%) - - Path #13: setup slack is 1.917(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock hdmi_in_clk (rising edge) - 0.000 - 0.000 - r + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_2/CIN (GTP_LUT5CARRY) - hdmi_in_clk - - 0.000 - 0.000 + + td + 0.030 + 12.549 r - hdmi_in_clk (port) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_2/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 0.000 - - hdmi_in_clk + 12.549 + + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/_N15760 - + - hdmi_in_clk_ibuf/I (GTP_INBUF) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_3/CIN (GTP_LUT5CARRY) - + td - 1.211 - 1.211 + 0.030 + 12.579 r - hdmi_in_clk_ibuf/O (GTP_INBUF) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_3/COUT (GTP_LUT5CARRY) - net (fanout=173) - 3.204 - 4.415 - - nt_hdmi_in_clk + net (fanout=1) + 0.000 + 12.579 + + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/_N15761 - + - r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[9]/CLK (GTP_DFF_C) + + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_4/CIN (GTP_LUT5CARRY) - tco - 0.329 - 4.744 + td + 0.030 + 12.609 r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[9]/Q (GTP_DFF_C) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_4/COUT (GTP_LUT5CARRY) - net (fanout=4) - 0.641 - 5.385 + net (fanout=1) + 0.000 + 12.609 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2 [9] + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/_N15762 @@ -60798,23 +60903,23 @@ - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_2/I0 (GTP_LUT3) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_5/CIN (GTP_LUT5CARRY) td - 0.233 - 5.618 - f - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_2/Z (GTP_LUT3) + 0.030 + 12.639 + r + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_5/COUT (GTP_LUT5CARRY) - net (fanout=2) - 0.553 - 6.171 + net (fanout=1) + 0.000 + 12.639 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2_b [7] + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/_N15763 @@ -60822,23 +60927,23 @@ - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_10/I3 (GTP_LUT4) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_6/CIN (GTP_LUT5CARRY) td - 0.185 - 6.356 + 0.030 + 12.669 r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_10/Z (GTP_LUT4) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_6/COUT (GTP_LUT5CARRY) - net (fanout=5) - 0.670 - 7.026 + net (fanout=1) + 0.000 + 12.669 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2_b [4] + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/_N15764 @@ -60846,23 +60951,23 @@ - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_16/I4 (GTP_LUT5) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_7/CIN (GTP_LUT5CARRY) td - 0.185 - 7.211 + 0.030 + 12.699 r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N24_16/Z (GTP_LUT5) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_7/COUT (GTP_LUT5CARRY) net (fanout=1) - 0.464 - 7.675 + 0.000 + 12.699 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2_b [0] + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/_N15765 @@ -60870,23 +60975,23 @@ - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_1/I1 (GTP_LUT5CARRY) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_8/CIN (GTP_LUT5CARRY) td - 0.298 - 7.973 - f - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_1/COUT (GTP_LUT5CARRY) + 0.030 + 12.729 + r + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_8/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 7.973 + 12.729 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.co [2] + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/_N15766 @@ -60894,23 +60999,23 @@ - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_2/CIN (GTP_LUT5CARRY) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_9/CIN (GTP_LUT5CARRY) td 0.030 - 8.003 + 12.759 r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_2/COUT (GTP_LUT5CARRY) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_9/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 8.003 + 12.759 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.co [4] + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/_N15767 @@ -60918,23 +61023,23 @@ - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_3/CIN (GTP_LUT5CARRY) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_10/CIN (GTP_LUT5CARRY) td - 0.030 - 8.033 + 0.236 + 12.995 r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_3/COUT (GTP_LUT5CARRY) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_10/Z (GTP_LUT5CARRY) - net (fanout=1) - 0.000 - 8.033 + net (fanout=2) + 0.553 + 13.548 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.co [6] + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2 [9] @@ -60942,23 +61047,23 @@ - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_4/CIN (GTP_LUT5CARRY) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N3[9]/I2 (GTP_LUT3) td - 0.030 - 8.063 + 0.185 + 13.733 r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_4/COUT (GTP_LUT5CARRY) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N3[9]/Z (GTP_LUT3) net (fanout=1) - 0.000 - 8.063 + 0.464 + 14.197 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.co [8] + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/rwptr [9] @@ -60966,23 +61071,23 @@ - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_5/CIN (GTP_LUT5CARRY) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N24.eq_4/I2 (GTP_LUT5CARRY) td - 0.236 - 8.299 - r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158.eq_5/Z (GTP_LUT5CARRY) + 0.233 + 14.430 + f + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N24.eq_4/COUT (GTP_LUT5CARRY) - net (fanout=1) - 0.464 - 8.763 + net (fanout=2) + 0.553 + 14.983 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N158 + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N21 @@ -60990,23 +61095,23 @@ - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N159/I4 (GTP_LUT5) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N22/I4 (GTP_LUT5) td 0.185 - 8.948 + 15.168 r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N159/Z (GTP_LUT5) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N22/Z (GTP_LUT5) net (fanout=1) 0.000 - 8.948 + 15.168 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N159 + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N22 @@ -61014,12 +61119,12 @@ r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/D (GTP_DFF_C) + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/D (GTP_DFF_C)
- +
Location Delay Type @@ -61029,28 +61134,28 @@ Logical Resource - Clock hdmi_in_clk (rising edge) + Clock ddrphy_clkin (rising edge) - 6.666 - 6.666 + 10.000 + 10.000 r - hdmi_in_clk + clk 0.000 - 6.666 + 10.000 r - hdmi_in_clk (port) + clk (port) net (fanout=1) 0.000 - 6.666 + 10.000 - hdmi_in_clk + clk @@ -61058,45 +61163,141 @@ - hdmi_in_clk_ibuf/I (GTP_INBUF) + clk_ibuf/I (GTP_INBUF) td 1.211 - 7.877 + 11.211 r - hdmi_in_clk_ibuf/O (GTP_INBUF) + clk_ibuf/O (GTP_INBUF) - net (fanout=173) - 3.204 - 11.081 + net (fanout=1) + 1.091 + 12.302 - nt_hdmi_in_clk + nt_clk + + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.089 + 12.391 r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/CLK (GTP_DFF_C) + u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + + + + net (fanout=7) + 0.605 + 12.996 + + ddr_clk + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + + + + td + 0.000 + 12.996 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + + + + net (fanout=71) + 0.847 + 13.843 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.094 + 13.937 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + + + + net (fanout=3) + 0.605 + 14.542 + + u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) + + + + td + 0.000 + 14.542 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + + + + net (fanout=5817) + 3.146 + 17.688 + + u_axi_ddr_top/clk + + + + + + + r + u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/CLK (GTP_DFF_C) clock pessimism 0.000 - 11.081 + 17.688 clock uncertainty - -0.250 - 10.831 + -0.150 + 17.538 @@ -61104,7 +61305,7 @@ Setup time 0.034 - 10.865 + 17.572 @@ -61113,27 +61314,27 @@ - 2.212 - 9 - 50 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[16]/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[6]/D + 2.599 + 7 + 56 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/D ddrphy_clkin ddrphy_clkin rise-rise 0.000 - 9.059 - 9.059 + 7.688 + 7.688 0.000 10.000 - 7.672 - 2.353 (30.7%) - 5.319 (69.3%) + 7.285 + 2.794 (38.4%) + 4.491 (61.6%) - Path #14: setup slack is 2.212(MET) + Path #19: setup slack is 2.599(MET) -
+
Location Delay Type @@ -61208,11 +61409,11 @@ - net (fanout=851) - 1.976 - 4.367 + net (fanout=7) + 0.605 + 2.996 - zoom_clk + ddr_clk @@ -61226,7 +61427,7 @@ td 0.000 - 4.367 + 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) @@ -61234,7 +61435,7 @@ net (fanout=71) 0.847 - 5.214 + 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin @@ -61250,7 +61451,7 @@ td 0.094 - 5.308 + 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) @@ -61258,7 +61459,7 @@ net (fanout=3) 0.605 - 5.913 + 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] @@ -61274,7 +61475,7 @@ td 0.000 - 5.913 + 4.542 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) @@ -61282,7 +61483,7 @@ net (fanout=5817) 3.146 - 9.059 + 7.688 u_axi_ddr_top/clk @@ -61292,23 +61493,23 @@ r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[16]/CLK (GTP_DFF_CE) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/CLK (GTP_DFF_CE) tco 0.329 - 9.388 + 8.017 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata[16]/Q (GTP_DFF_CE) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/Q (GTP_DFF_CE) - net (fanout=50) - 1.028 - 10.416 + net (fanout=5) + 0.670 + 8.687 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/req_rdata [16] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mr0_ddr3 [2] @@ -61316,23 +61517,23 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N702_7[0]/I2 (GTP_LUT5M) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/I0 (GTP_LUT4) td - 0.300 - 10.716 + 0.290 + 8.977 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N702_7[0]/Z (GTP_LUT5M) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/Z (GTP_LUT4) - net (fanout=1) - 0.000 - 10.716 + net (fanout=2) + 0.553 + 9.530 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/_N25007 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_cl [1] @@ -61340,23 +61541,23 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N702_8[0]/I0 (GTP_MUX2LUT6) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_2/I3 (GTP_LUT5CARRY) td - 0.000 - 10.716 + 0.363 + 9.893 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N702_8[0]/Z (GTP_MUX2LUT6) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_2/COUT (GTP_LUT5CARRY) - net (fanout=4) - 0.641 - 11.357 + net (fanout=1) + 0.000 + 9.893 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/cmd_pre_pass_l + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.co [2] @@ -61364,47 +61565,23 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N244/I0 (GTP_LUT2) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_3/CIN (GTP_LUT5CARRY) td - 0.185 - 11.542 + 0.236 + 10.129 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/N244/Z (GTP_LUT2) - - - - net (fanout=8) - 0.730 - 12.272 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/norm_cmd_l_pre - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N31.lt_1/I1 (GTP_LUT5CARRY) - - - - td - 0.233 - 12.505 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N31.lt_1/COUT (GTP_LUT5CARRY) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_3/Z (GTP_LUT5CARRY) net (fanout=1) - 0.000 - 12.505 + 0.464 + 10.593 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N31.co [2] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [2] @@ -61412,23 +61589,23 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N31.lt_2/CIN (GTP_LUT5CARRY) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[2]/I2 (GTP_LUT3) td - 0.030 - 12.535 + 0.185 + 10.778 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N31.lt_2/COUT (GTP_LUT5CARRY) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[2]/Z (GTP_LUT3) - net (fanout=1) - 0.000 - 12.535 + net (fanout=4) + 0.641 + 11.419 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N31.co [4] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al [2] @@ -61436,23 +61613,23 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N31.lt_3/CIN (GTP_LUT5CARRY) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_3/I2 (GTP_LUT5CARRY) td - 0.236 - 12.771 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N31.lt_3/Z (GTP_LUT5CARRY) + 0.233 + 11.652 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_3/COUT (GTP_LUT5CARRY) - net (fanout=2) - 0.553 - 13.324 + net (fanout=1) + 0.000 + 11.652 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N31 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14533 @@ -61460,23 +61637,23 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_54/I2 (GTP_LUT5) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_4/CIN (GTP_LUT5CARRY) td - 0.185 - 13.509 + 0.030 + 11.682 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_54/Z (GTP_LUT5) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_4/COUT (GTP_LUT5CARRY) - net (fanout=9) - 0.745 - 14.254 + net (fanout=1) + 0.000 + 11.682 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N25124 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14534 @@ -61484,23 +61661,23 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_50[3]_2/I0 (GTP_LUT3) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_5/CIN (GTP_LUT5CARRY) td - 0.185 - 14.439 + 0.236 + 11.918 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_50[3]_2/Z (GTP_LUT3) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_5/Z (GTP_LUT5CARRY) - net (fanout=3) - 0.605 - 15.044 + net (fanout=4) + 0.641 + 12.559 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N103199_2 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mc_rl [4] @@ -61508,23 +61685,23 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_8_maj1_1/I3 (GTP_LUT5M) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_198_5/I4 (GTP_LUT5) td - 0.300 - 15.344 + 0.277 + 12.836 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_8_maj1_1/Z (GTP_LUT5M) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_198_5/Z (GTP_LUT5) - net (fanout=2) - 0.553 - 15.897 + net (fanout=56) + 1.058 + 13.894 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N15659 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23906 @@ -61532,23 +61709,23 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_8_sum3_6/I0 (GTP_LUT5) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[0]/I2 (GTP_LUT3) td 0.185 - 16.082 + 14.079 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_8_sum3_6/Z (GTP_LUT5) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[0]/Z (GTP_LUT3) net (fanout=1) 0.464 - 16.546 + 14.543 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/_N17326 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N23976 @@ -61556,36 +61733,36 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_2[6]_1/I0 (GTP_LUT2) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_172[0]/I1 (GTP_LUT5M) td - 0.185 - 16.731 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77_2[6]_1/Z (GTP_LUT2) + 0.430 + 14.973 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_172[0]/Z (GTP_LUT5M) net (fanout=1) 0.000 - 16.731 + 14.973 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/N77 [6] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj [0] - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[6]/D (GTP_DFF_C) + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/D (GTP_DFF_C)
- +
Location Delay Type @@ -61660,11 +61837,11 @@ - net (fanout=851) - 1.976 - 14.367 + net (fanout=7) + 0.605 + 12.996 - zoom_clk + ddr_clk @@ -61678,7 +61855,7 @@ td 0.000 - 14.367 + 12.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) @@ -61686,7 +61863,7 @@ net (fanout=71) 0.847 - 15.214 + 13.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin @@ -61702,7 +61879,7 @@ td 0.094 - 15.308 + 13.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) @@ -61710,7 +61887,7 @@ net (fanout=3) 0.605 - 15.913 + 14.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] @@ -61726,7 +61903,7 @@ td 0.000 - 15.913 + 14.542 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) @@ -61734,7 +61911,7 @@ net (fanout=5817) 3.146 - 19.059 + 17.688 u_axi_ddr_top/clk @@ -61744,13 +61921,13 @@ r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_act_pass/timing_cnt[6]/CLK (GTP_DFF_C) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/CLK (GTP_DFF_C) clock pessimism 0.000 - 19.059 + 17.688 @@ -61758,7 +61935,7 @@ clock uncertainty -0.150 - 18.909 + 17.538 @@ -61766,7 +61943,7 @@ Setup time 0.034 - 18.943 + 17.572 @@ -61775,27 +61952,27 @@ - 2.404 - 8 - 575 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/calib_done/CLK - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/D + 3.781 + 4 + 5 + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/CLK + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/D - ddrphy_clkin - ddrphy_clkin + hdmi_in_clk + hdmi_in_clk rise-rise 0.000 - 9.059 - 9.059 + 4.415 + 4.415 0.000 - 10.000 - 7.480 - 1.979 (26.5%) - 5.501 (73.5%) + 6.666 + 2.669 + 1.358 (50.9%) + 1.311 (49.1%) - Path #15: setup slack is 2.404(MET) + Path #20: setup slack is 3.781(MET) -
+
Location Delay Type @@ -61805,7 +61982,7 @@ Logical Resource - Clock ddrphy_clkin (rising edge) + Clock hdmi_in_clk (rising edge) 0.000 0.000 @@ -61813,12 +61990,12 @@ - clk + hdmi_in_clk 0.000 0.000 r - clk (port) + hdmi_in_clk (port) @@ -61826,7 +62003,7 @@ 0.000 0.000 - clk + hdmi_in_clk @@ -61834,7 +62011,7 @@ - clk_ibuf/I (GTP_INBUF) + hdmi_in_clk_ibuf/I (GTP_INBUF) @@ -61842,87 +62019,347 @@ 1.211 1.211 r - clk_ibuf/O (GTP_INBUF) + hdmi_in_clk_ibuf/O (GTP_INBUF) - net (fanout=1) - 1.091 - 2.302 + net (fanout=173) + 3.204 + 4.415 - nt_clk + nt_hdmi_in_clk + r + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/CLK (GTP_DFF_CE) + + + + tco + 0.329 + 4.744 + r + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/Q (GTP_DFF_CE) + + - u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + net (fanout=5) + 0.670 + 5.414 + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/wr_addr [0] - + + + + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_2/I1 (GTP_LUT5CARRY) + + + td - 0.089 - 2.391 + 0.295 + 5.709 + f + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_2/COUT (GTP_LUT5CARRY) + + + + net (fanout=1) + 0.000 + 5.709 + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15959 + + + + + + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_3/CIN (GTP_LUT5CARRY) + + + + td + 0.030 + 5.739 r - u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_3/COUT (GTP_LUT5CARRY) + + + + net (fanout=1) + 0.000 + 5.739 + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15960 + - net (fanout=851) - 1.976 - 4.367 - zoom_clk + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_4/CIN (GTP_LUT5CARRY) - + + td + 0.030 + 5.769 + r + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_4/COUT (GTP_LUT5CARRY) + + + + net (fanout=1) + 0.000 + 5.769 + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15961 + + + - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_5/CIN (GTP_LUT5CARRY) - + td + 0.030 + 5.799 + r + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_5/COUT (GTP_LUT5CARRY) + + + + net (fanout=1) 0.000 - 4.367 + 5.799 + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15962 + + + + + + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_6/CIN (GTP_LUT5CARRY) + + + + td + 0.030 + 5.829 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_6/COUT (GTP_LUT5CARRY) - net (fanout=71) - 0.847 - 5.214 + net (fanout=1) + 0.000 + 5.829 + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15963 + + + - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_7/CIN (GTP_LUT5CARRY) - + + td + 0.030 + 5.859 + r + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_7/COUT (GTP_LUT5CARRY) + + + + net (fanout=1) + 0.000 + 5.859 + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15964 + + + - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_8/CIN (GTP_LUT5CARRY) - + td - 0.094 - 5.308 + 0.030 + 5.889 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_8/COUT (GTP_LUT5CARRY) - net (fanout=3) - 0.605 - 5.913 + net (fanout=1) + 0.000 + 5.889 + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15965 + + + - u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_9/CIN (GTP_LUT5CARRY) + + + + td + 0.030 + 5.919 + r + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_9/COUT (GTP_LUT5CARRY) + + + + net (fanout=1) + 0.000 + 5.919 + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15966 + + + + + + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_10/CIN (GTP_LUT5CARRY) + + + + td + 0.030 + 5.949 + r + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_10/COUT (GTP_LUT5CARRY) + + + + net (fanout=1) + 0.000 + 5.949 + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15967 + + + + + + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_11/CIN (GTP_LUT5CARRY) + + + + td + 0.236 + 6.185 + r + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_11/Z (GTP_LUT5CARRY) + + + + net (fanout=4) + 0.641 + 6.826 + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2 [10] + + + + + + + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N7_10/I3 (GTP_LUT5) + + + + td + 0.258 + 7.084 + f + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N7_10/Z (GTP_LUT5) + + + + net (fanout=1) + 0.000 + 7.084 + + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wgnext [10] + + + + + + + f + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/D (GTP_DFF_C) + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock hdmi_in_clk (rising edge) + + 6.666 + 6.666 + r + + + + hdmi_in_clk + + 0.000 + 6.666 + r + hdmi_in_clk (port) + + + + net (fanout=1) + 0.000 + 6.666 + + hdmi_in_clk @@ -61930,23 +62367,23 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) + hdmi_in_clk_ibuf/I (GTP_INBUF) td - 0.000 - 5.913 + 1.211 + 7.877 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + hdmi_in_clk_ibuf/O (GTP_INBUF) - net (fanout=5817) - 3.146 - 9.059 + net (fanout=173) + 3.204 + 11.081 - u_axi_ddr_top/clk + nt_hdmi_in_clk @@ -61954,71 +62391,137 @@ r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/calib_done/CLK (GTP_DFF_C) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/CLK (GTP_DFF_C) - - tco - 0.329 - 9.388 + clock pessimism + + 0.000 + 11.081 + + + + + clock uncertainty + + -0.250 + 10.831 + + + + + Setup time + + 0.034 + 10.865 + + + +
+
+
+
+ + 3.811 + 4 + 5 + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/CLK + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/D + + hdmi_in_clk + hdmi_in_clk + rise-rise + 0.000 + 4.415 + 4.415 + 0.000 + 6.666 + 2.639 + 1.328 (50.3%) + 1.311 (49.7%) + + Path #21: setup slack is 3.811(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock hdmi_in_clk (rising edge) + + 0.000 + 0.000 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/calib_done/Q (GTP_DFF_C) + + + + hdmi_in_clk + + 0.000 + 0.000 + r + hdmi_in_clk (port) - net (fanout=575) - 2.721 - 12.109 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/calib_done + net (fanout=1) + 0.000 + 0.000 + + hdmi_in_clk - + - u_axi_ddr_top/u_axi_rd_connect/N1_2/I1 (GTP_LUT3) + hdmi_in_clk_ibuf/I (GTP_INBUF) - + td - 0.185 - 12.294 + 1.211 + 1.211 r - u_axi_ddr_top/u_axi_rd_connect/N1_2/Z (GTP_LUT3) + hdmi_in_clk_ibuf/O (GTP_INBUF) - net (fanout=3) - 0.605 - 12.899 - - u_axi_ddr_top/u_axi_rd_connect/wr_en + net (fanout=173) + 3.204 + 4.415 + + nt_hdmi_in_clk - - + - u_axi_ddr_top/u_axi_rd_connect/N7_4/I0 (GTP_LUT4) + r + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/CLK (GTP_DFF_CE) - td - 0.185 - 13.084 + tco + 0.329 + 4.744 r - u_axi_ddr_top/u_axi_rd_connect/N7_4/Z (GTP_LUT4) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/Q (GTP_DFF_CE) - net (fanout=3) - 0.605 - 13.689 + net (fanout=5) + 0.670 + 5.414 - u_axi_ddr_top/u_axi_rd_connect/wr_rid_en + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/wr_addr [0] @@ -62026,23 +62529,23 @@ - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_1/I0 (GTP_LUT5CARRY) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_2/I1 (GTP_LUT5CARRY) td - 0.201 - 13.890 + 0.295 + 5.709 f - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_1/COUT (GTP_LUT5CARRY) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_2/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 13.890 + 5.709 - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/_N15823 + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15959 @@ -62050,23 +62553,23 @@ - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_2/CIN (GTP_LUT5CARRY) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_3/CIN (GTP_LUT5CARRY) td 0.030 - 13.920 + 5.739 r - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_2/COUT (GTP_LUT5CARRY) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_3/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 13.920 + 5.739 - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/_N15824 + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15960 @@ -62074,23 +62577,23 @@ - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_3/CIN (GTP_LUT5CARRY) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_4/CIN (GTP_LUT5CARRY) td 0.030 - 13.950 + 5.769 r - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_3/COUT (GTP_LUT5CARRY) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_4/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 13.950 + 5.769 - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/_N15825 + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15961 @@ -62098,23 +62601,23 @@ - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_4/CIN (GTP_LUT5CARRY) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_5/CIN (GTP_LUT5CARRY) td 0.030 - 13.980 + 5.799 r - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_4/COUT (GTP_LUT5CARRY) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_5/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 13.980 + 5.799 - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/_N15826 + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15962 @@ -62122,23 +62625,23 @@ - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_5/CIN (GTP_LUT5CARRY) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_6/CIN (GTP_LUT5CARRY) td 0.030 - 14.010 + 5.829 r - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_5/COUT (GTP_LUT5CARRY) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_6/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 14.010 + 5.829 - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/_N15827 + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15963 @@ -62146,23 +62649,23 @@ - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_6/CIN (GTP_LUT5CARRY) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_7/CIN (GTP_LUT5CARRY) td 0.030 - 14.040 + 5.859 r - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_6/COUT (GTP_LUT5CARRY) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_7/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 14.040 + 5.859 - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/_N15828 + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15964 @@ -62170,23 +62673,23 @@ - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_7/CIN (GTP_LUT5CARRY) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_8/CIN (GTP_LUT5CARRY) td 0.030 - 14.070 + 5.889 r - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_7/COUT (GTP_LUT5CARRY) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_8/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 14.070 + 5.889 - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/_N15829 + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15965 @@ -62194,23 +62697,23 @@ - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_8/CIN (GTP_LUT5CARRY) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_9/CIN (GTP_LUT5CARRY) td 0.030 - 14.100 + 5.919 r - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_8/COUT (GTP_LUT5CARRY) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_9/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 14.100 + 5.919 - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/_N15830 + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N15966 @@ -62218,23 +62721,23 @@ - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_9/CIN (GTP_LUT5CARRY) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_10/CIN (GTP_LUT5CARRY) td - 0.030 - 14.130 + 0.236 + 6.155 r - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_9/COUT (GTP_LUT5CARRY) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_10/Z (GTP_LUT5CARRY) - net (fanout=1) - 0.000 - 14.130 + net (fanout=4) + 0.641 + 6.796 - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/_N15831 + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2 [9] @@ -62242,108 +62745,150 @@ - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_10/CIN (GTP_LUT5CARRY) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N7_9/I4 (GTP_LUT5) td - 0.236 - 14.366 - r - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2_10/Z (GTP_LUT5CARRY) + 0.258 + 7.054 + f + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N7_9/Z (GTP_LUT5) - net (fanout=2) - 0.553 - 14.919 + net (fanout=1) + 0.000 + 7.054 - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N2 [9] + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wgnext [9] + f + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/D (GTP_DFF_C) + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock hdmi_in_clk (rising edge) + + 6.666 + 6.666 + r - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N3[9]/I2 (GTP_LUT3) - - td - 0.185 - 15.104 + hdmi_in_clk + + 0.000 + 6.666 r - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N3[9]/Z (GTP_LUT3) + hdmi_in_clk (port) net (fanout=1) - 0.464 - 15.568 - - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/rwptr [9] + 0.000 + 6.666 + + hdmi_in_clk - + - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N24.eq_4/I2 (GTP_LUT5CARRY) + hdmi_in_clk_ibuf/I (GTP_INBUF) - + td - 0.233 - 15.801 - f - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N24.eq_4/COUT (GTP_LUT5CARRY) + 1.211 + 7.877 + r + hdmi_in_clk_ibuf/O (GTP_INBUF) - net (fanout=2) - 0.553 - 16.354 - - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N21 + net (fanout=173) + 3.204 + 11.081 + + nt_hdmi_in_clk - - + - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N22/I4 (GTP_LUT5) - - - - td - 0.185 - 16.539 r - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N22/Z (GTP_LUT5) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/CLK (GTP_DFF_C) + clock pessimism - net (fanout=1) 0.000 - 16.539 - - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/N22 + 11.081 + + - + clock uncertainty + -0.250 + 10.831 + + + + + Setup time + + 0.034 + 10.865 - r - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/D (GTP_DFF_C)
+
+
+ + 5.609 + 6 + 2548 + sync_vg_100m/CLK + udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[0]/D + + clk_720p60Hz + clk_720p60Hz + rise-rise + 0.000 + 8.070 + 8.070 + 0.000 + 13.473 + 7.748 + 1.554 (20.1%) + 6.194 (79.9%) + + Path #22: setup slack is 5.609(MET) - +
Location Delay Type @@ -62353,10 +62898,10 @@ Logical Resource - Clock ddrphy_clkin (rising edge) + Clock clk_720p60Hz (rising edge) - 10.000 - 10.000 + 0.000 + 0.000 r @@ -62364,7 +62909,7 @@ clk0.000 - 10.000 + 0.000rclk (port) @@ -62372,7 +62917,7 @@ net (fanout=1) 0.000 - 10.000 + 0.000 clk @@ -62388,7 +62933,7 @@ td 1.211 - 11.211 + 1.211 r clk_ibuf/O (GTP_INBUF) @@ -62396,7 +62941,7 @@ net (fanout=1) 1.091 - 12.302 + 2.302 nt_clk @@ -62411,18 +62956,18 @@ td - 0.089 - 12.391 + 0.094 + 2.396 r - u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=851) - 1.976 - 14.367 + net (fanout=2825) + 3.127 + 5.523 - zoom_clk + rd3_clk @@ -62430,130 +62975,204 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) td - 0.000 - 14.367 + 0.089 + 5.612 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=71) - 0.847 - 15.214 + net (fanout=1758) + 2.458 + 8.070 - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + nt_pix_clk + r + sync_vg_100m/CLK (GTP_DFF_P) + + + + tco + 0.329 + 8.399 + r + sync_vg_100m/Q (GTP_DFF_P) + + + + net (fanout=2548) + 2.954 + 11.353 + + sync_vg_100m + + + + + - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/I0 (GTP_LUT5) - + td - 0.094 - 15.308 + 0.185 + 11.538 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/Z (GTP_LUT5) - net (fanout=3) - 0.605 - 15.913 - - u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + net (fanout=2) + 0.553 + 12.091 + + udp_osd_inst/char_osd_inst/row_pixels_ready - + - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) + udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/I1 (GTP_LUT3) - + td - 0.000 - 15.913 + 0.185 + 12.276 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/Z (GTP_LUT3) - net (fanout=5817) - 3.146 - 19.059 + net (fanout=16) + 0.782 + 13.058 + + udp_osd_inst/char_osd_inst/char_next + + + - u_axi_ddr_top/clk + + + + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N358_5/I0 (GTP_LUT3) - + + td + 0.185 + 13.243 + r + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N358_5/Z (GTP_LUT3) + + + + net (fanout=5) + 0.670 + 13.913 + + udp_osd_inst/_N97124 + + + + + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_9/I0 (GTP_LUT5) + + + + td + 0.185 + 14.098 r - u_axi_ddr_top/u_axi_rd_connect/u_axi_rid_fifo/U_ipml_fifo_axi_rid_fifo/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/CLK (GTP_DFF_C) + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_9/Z (GTP_LUT5) - clock pessimism - 0.000 - 19.059 + net (fanout=1) + 0.464 + 14.562 + + udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N18403 + + + + + + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_15_3/I1 (GTP_LUT5M) + + + + td + 0.300 + 14.862 + f + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_15_3/Z (GTP_LUT5M) - clock uncertainty - -0.150 - 18.909 + net (fanout=11) + 0.771 + 15.633 + + udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N18404 + + + + + + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_11_inv[0]/I0 (GTP_LUT5) + + + + td + 0.185 + 15.818 + r + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_11_inv[0]/Z (GTP_LUT5) - Setup time - 0.034 - 18.943 + net (fanout=1) + 0.000 + 15.818 + + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847 [0] + + + + + r + udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[0]/D (GTP_DFF_SE)
-
-
- - 2.599 - 7 - 56 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/D - - ddrphy_clkin - ddrphy_clkin - rise-rise - 0.000 - 9.059 - 9.059 - 0.000 - 10.000 - 7.285 - 2.794 (38.4%) - 4.491 (61.6%) - - Path #16: setup slack is 2.599(MET) - +
Location Delay Type @@ -62563,10 +63182,10 @@ Logical Resource - Clock ddrphy_clkin (rising edge) + Clock clk_720p60Hz (rising edge) - 0.000 - 0.000 + 13.473 + 13.473 r @@ -62574,7 +63193,7 @@ clk0.000 - 0.000 + 13.473rclk (port) @@ -62582,7 +63201,7 @@ net (fanout=1) 0.000 - 0.000 + 13.473 clk @@ -62598,7 +63217,7 @@ td 1.211 - 1.211 + 14.684 r clk_ibuf/O (GTP_INBUF) @@ -62606,33 +63225,147 @@ net (fanout=1) 1.091 - 2.302 + 15.775 nt_clk - - - + + + + + + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.094 + 15.869 + r + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + + + + net (fanout=2825) + 3.127 + 18.996 + + rd3_clk + + + + + + + + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.089 + 19.085 + r + U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + + + + net (fanout=1758) + 2.458 + 21.543 + + nt_pix_clk + + + + + + + r + udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[0]/CLK (GTP_DFF_SE) + + + clock pessimism + + 0.000 + 21.543 + + + + + clock uncertainty + + -0.150 + 21.393 + + + + + Setup time + + 0.034 + 21.427 + + + +
+
+
+
+ + 5.609 + 6 + 2548 + sync_vg_100m/CLK + udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[1]/D + + clk_720p60Hz + clk_720p60Hz + rise-rise + 0.000 + 8.070 + 8.070 + 0.000 + 13.473 + 7.748 + 1.554 (20.1%) + 6.194 (79.9%) + + Path #23: setup slack is 5.609(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_720p60Hz (rising edge) + 0.000 + 0.000 + r - u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + clk - td - 0.089 - 2.391 + 0.000 + 0.000 r - u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + clk (port) - net (fanout=851) - 1.976 - 4.367 + net (fanout=1) + 0.000 + 0.000 - zoom_clk + clk @@ -62640,23 +63373,23 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + clk_ibuf/I (GTP_INBUF) td - 0.000 - 4.367 + 1.211 + 1.211 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + clk_ibuf/O (GTP_INBUF) - net (fanout=71) - 0.847 - 5.214 + net (fanout=1) + 1.091 + 2.302 - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + nt_clk @@ -62664,23 +63397,23 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 - 5.308 + 2.396 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) - 0.605 - 5.913 + net (fanout=2825) + 3.127 + 5.523 - u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + rd3_clk @@ -62688,23 +63421,23 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) td - 0.000 - 5.913 + 0.089 + 5.612 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=5817) - 3.146 - 9.059 + net (fanout=1758) + 2.458 + 8.070 - u_axi_ddr_top/clk + nt_pix_clk @@ -62712,23 +63445,23 @@ r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/CLK (GTP_DFF_CE) + sync_vg_100m/CLK (GTP_DFF_P) tco 0.329 - 9.388 + 8.399 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mr0_ddr3[2]/Q (GTP_DFF_CE) + sync_vg_100m/Q (GTP_DFF_P) - net (fanout=5) - 0.670 - 10.058 + net (fanout=2548) + 2.954 + 11.353 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mr0_ddr3 [2] + sync_vg_100m @@ -62736,47 +63469,23 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/I0 (GTP_LUT4) + udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/I0 (GTP_LUT5) td - 0.290 - 10.348 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/N144_8[1]/Z (GTP_LUT4) + 0.185 + 11.538 + r + udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/Z (GTP_LUT5) net (fanout=2) 0.553 - 10.901 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_cl [1] - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_2/I3 (GTP_LUT5CARRY) - - - - td - 0.363 - 11.264 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_2/COUT (GTP_LUT5CARRY) - - - - net (fanout=1) - 0.000 - 11.264 + 12.091 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.co [2] + udp_osd_inst/char_osd_inst/row_pixels_ready @@ -62784,23 +63493,23 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_3/CIN (GTP_LUT5CARRY) + udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/I1 (GTP_LUT3) td - 0.236 - 11.500 + 0.185 + 12.276 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_6.fsub_3/Z (GTP_LUT5CARRY) + udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/Z (GTP_LUT3) - net (fanout=1) - 0.464 - 11.964 + net (fanout=16) + 0.782 + 13.058 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/nb0 [2] + udp_osd_inst/char_osd_inst/char_next @@ -62808,47 +63517,23 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[2]/I2 (GTP_LUT3) + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N358_5/I0 (GTP_LUT3) td 0.185 - 12.149 + 13.243 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al_1[2]/Z (GTP_LUT3) - - - - net (fanout=4) - 0.641 - 12.790 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_al [2] - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_3/I2 (GTP_LUT5CARRY) - - - - td - 0.233 - 13.023 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_3/COUT (GTP_LUT5CARRY) + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N358_5/Z (GTP_LUT3) - net (fanout=1) - 0.000 - 13.023 + net (fanout=5) + 0.670 + 13.913 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14575 + udp_osd_inst/_N97124 @@ -62856,47 +63541,23 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_4/CIN (GTP_LUT5CARRY) + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_9/I0 (GTP_LUT5) td - 0.030 - 13.053 + 0.185 + 14.098 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_4/COUT (GTP_LUT5CARRY) + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_9/Z (GTP_LUT5) net (fanout=1) - 0.000 - 13.053 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/_N14576 - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_5/CIN (GTP_LUT5CARRY) - - - - td - 0.236 - 13.289 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_info/mc_rl_5/Z (GTP_LUT5CARRY) - - - - net (fanout=4) - 0.641 - 13.930 + 0.464 + 14.562 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/mc_rl [4] + udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N18403 @@ -62904,23 +63565,23 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_198_5/I4 (GTP_LUT5) + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_15_3/I1 (GTP_LUT5M) td - 0.277 - 14.207 + 0.300 + 14.862 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_198_5/Z (GTP_LUT5) + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_15_3/Z (GTP_LUT5M) - net (fanout=56) - 1.058 - 15.265 + net (fanout=11) + 0.771 + 15.633 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24127 + udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N18404 @@ -62928,60 +63589,36 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[0]/I2 (GTP_LUT3) + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_11_inv[1]/I0 (GTP_LUT5) td 0.185 - 15.450 + 15.818 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_160[0]/Z (GTP_LUT3) - - - - net (fanout=1) - 0.464 - 15.914 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/_N24197 - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_172[0]/I1 (GTP_LUT5M) - - - - td - 0.430 - 16.344 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj_172[0]/Z (GTP_LUT5M) + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_11_inv[1]/Z (GTP_LUT5) net (fanout=1) 0.000 - 16.344 + 15.818 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_adj [0] + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847 [1] - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/D (GTP_DFF_C) + r + udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[1]/D (GTP_DFF_SE)
- +
Location Delay Type @@ -62991,10 +63628,10 @@ Logical Resource - Clock ddrphy_clkin (rising edge) + Clock clk_720p60Hz (rising edge) - 10.000 - 10.000 + 13.473 + 13.473 r @@ -63002,7 +63639,7 @@ clk0.000 - 10.000 + 13.473rclk (port) @@ -63010,7 +63647,7 @@ net (fanout=1) 0.000 - 10.000 + 13.473 clk @@ -63026,7 +63663,7 @@ td 1.211 - 11.211 + 14.684 r clk_ibuf/O (GTP_INBUF) @@ -63034,7 +63671,7 @@ net (fanout=1) 1.091 - 12.302 + 15.775 nt_clk @@ -63046,69 +63683,21 @@ u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) - - - td - 0.089 - 12.391 - r - u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - - - - net (fanout=851) - 1.976 - 14.367 - - zoom_clk - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - - - - td - 0.000 - 14.367 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - - - - net (fanout=71) - 0.847 - 15.214 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 - 15.308 + 15.869 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) - 0.605 - 15.913 + net (fanout=2825) + 3.127 + 18.996 - u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + rd3_clk @@ -63116,23 +63705,23 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) td - 0.000 - 15.913 + 0.089 + 19.085 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=5817) - 3.146 - 19.059 + net (fanout=1758) + 2.458 + 21.543 - u_axi_ddr_top/clk + nt_pix_clk @@ -63140,13 +63729,13 @@ r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_ctrl_pos[0]/CLK (GTP_DFF_C) + udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[1]/CLK (GTP_DFF_SE) clock pessimism 0.000 - 19.059 + 21.543 @@ -63154,7 +63743,7 @@ clock uncertainty -0.150 - 18.909 + 21.393 @@ -63162,7 +63751,7 @@ Setup time 0.034 - 18.943 + 21.427 @@ -63171,27 +63760,27 @@ - 3.781 - 4 - 5 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/CLK - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/D + 5.609 + 6 + 2548 + sync_vg_100m/CLK + udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[2]/D - hdmi_in_clk - hdmi_in_clk + clk_720p60Hz + clk_720p60Hz rise-rise 0.000 - 4.415 - 4.415 + 8.070 + 8.070 0.000 - 6.666 - 2.669 - 1.358 (50.9%) - 1.311 (49.1%) + 13.473 + 7.748 + 1.554 (20.1%) + 6.194 (79.9%) - Path #17: setup slack is 3.781(MET) + Path #24: setup slack is 5.609(MET) -
+
Location Delay Type @@ -63201,7 +63790,7 @@ Logical Resource - Clock hdmi_in_clk (rising edge) + Clock clk_720p60Hz (rising edge) 0.000 0.000 @@ -63209,12 +63798,12 @@ - hdmi_in_clk + clk 0.000 0.000 r - hdmi_in_clk (port) + clk (port) @@ -63222,7 +63811,7 @@ 0.000 0.000 - hdmi_in_clk + clk @@ -63230,7 +63819,7 @@ - hdmi_in_clk_ibuf/I (GTP_INBUF) + clk_ibuf/I (GTP_INBUF) @@ -63238,87 +63827,87 @@ 1.211 1.211 r - hdmi_in_clk_ibuf/O (GTP_INBUF) + clk_ibuf/O (GTP_INBUF) - net (fanout=173) - 3.204 - 4.415 + net (fanout=1) + 1.091 + 2.302 - nt_hdmi_in_clk + nt_clk - r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/CLK (GTP_DFF_CE) + + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) - - tco - 0.329 - 4.744 + + td + 0.094 + 2.396 r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/Q (GTP_DFF_CE) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=5) - 0.670 - 5.414 - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/wr_addr [0] + net (fanout=2825) + 3.127 + 5.523 + + rd3_clk - + - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_2/I1 (GTP_LUT5CARRY) + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) - + td - 0.295 - 5.709 - f - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_2/COUT (GTP_LUT5CARRY) + 0.089 + 5.612 + r + U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=1) - 0.000 - 5.709 - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16001 + net (fanout=1758) + 2.458 + 8.070 + + nt_pix_clk - - + - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_3/CIN (GTP_LUT5CARRY) + r + sync_vg_100m/CLK (GTP_DFF_P) - td - 0.030 - 5.739 + tco + 0.329 + 8.399 r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_3/COUT (GTP_LUT5CARRY) + sync_vg_100m/Q (GTP_DFF_P) - net (fanout=1) - 0.000 - 5.739 + net (fanout=2548) + 2.954 + 11.353 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16002 + sync_vg_100m @@ -63326,23 +63915,23 @@ - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_4/CIN (GTP_LUT5CARRY) + udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/I0 (GTP_LUT5) td - 0.030 - 5.769 + 0.185 + 11.538 r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_4/COUT (GTP_LUT5CARRY) + udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/Z (GTP_LUT5) - net (fanout=1) - 0.000 - 5.769 + net (fanout=2) + 0.553 + 12.091 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16003 + udp_osd_inst/char_osd_inst/row_pixels_ready @@ -63350,23 +63939,23 @@ - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_5/CIN (GTP_LUT5CARRY) + udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/I1 (GTP_LUT3) td - 0.030 - 5.799 + 0.185 + 12.276 r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_5/COUT (GTP_LUT5CARRY) + udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/Z (GTP_LUT3) - net (fanout=1) - 0.000 - 5.799 + net (fanout=16) + 0.782 + 13.058 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16004 + udp_osd_inst/char_osd_inst/char_next @@ -63374,23 +63963,23 @@ - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_6/CIN (GTP_LUT5CARRY) + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N358_5/I0 (GTP_LUT3) td - 0.030 - 5.829 + 0.185 + 13.243 r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_6/COUT (GTP_LUT5CARRY) + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N358_5/Z (GTP_LUT3) - net (fanout=1) - 0.000 - 5.829 + net (fanout=5) + 0.670 + 13.913 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16005 + udp_osd_inst/_N97124 @@ -63398,23 +63987,23 @@ - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_7/CIN (GTP_LUT5CARRY) + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_9/I0 (GTP_LUT5) td - 0.030 - 5.859 + 0.185 + 14.098 r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_7/COUT (GTP_LUT5CARRY) + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_9/Z (GTP_LUT5) net (fanout=1) - 0.000 - 5.859 + 0.464 + 14.562 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16006 + udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N18403 @@ -63422,23 +64011,23 @@ - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_8/CIN (GTP_LUT5CARRY) + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_15_3/I1 (GTP_LUT5M) td - 0.030 - 5.889 - r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_8/COUT (GTP_LUT5CARRY) + 0.300 + 14.862 + f + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_15_3/Z (GTP_LUT5M) - net (fanout=1) - 0.000 - 5.889 + net (fanout=11) + 0.771 + 15.633 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16007 + udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N18404 @@ -63446,139 +64035,115 @@ - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_9/CIN (GTP_LUT5CARRY) + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_11_inv[2]/I0 (GTP_LUT5) td - 0.030 - 5.919 + 0.185 + 15.818 r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_9/COUT (GTP_LUT5CARRY) + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_11_inv[2]/Z (GTP_LUT5) net (fanout=1) 0.000 - 5.919 + 15.818 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16008 + udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847 [2] - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_10/CIN (GTP_LUT5CARRY) - - - - td - 0.030 - 5.949 r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_10/COUT (GTP_LUT5CARRY) - - - - net (fanout=1) - 0.000 - 5.949 - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16009 + udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[2]/D (GTP_DFF_SE) +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + - - - + Clock clk_720p60Hz (rising edge) + 13.473 + 13.473 + r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_11/CIN (GTP_LUT5CARRY) - - td - 0.236 - 6.185 + clk + + 0.000 + 13.473 r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_11/Z (GTP_LUT5CARRY) + clk (port) - net (fanout=4) - 0.641 - 6.826 - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2 [10] + net (fanout=1) + 0.000 + 13.473 + + clk - + - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N7_10/I3 (GTP_LUT5) + clk_ibuf/I (GTP_INBUF) - + td - 0.258 - 7.084 - f - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N7_10/Z (GTP_LUT5) + 1.211 + 14.684 + r + clk_ibuf/O (GTP_INBUF) net (fanout=1) - 0.000 - 7.084 - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wgnext [10] + 1.091 + 15.775 + + nt_clk - - + - f - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/D (GTP_DFF_C) - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock hdmi_in_clk (rising edge) - 6.666 - 6.666 - r + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) - hdmi_in_clk - 0.000 - 6.666 + td + 0.094 + 15.869 r - hdmi_in_clk (port) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=1) - 0.000 - 6.666 + net (fanout=2825) + 3.127 + 18.996 - hdmi_in_clk + rd3_clk @@ -63586,23 +64151,23 @@ - hdmi_in_clk_ibuf/I (GTP_INBUF) + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) td - 1.211 - 7.877 + 0.089 + 19.085 r - hdmi_in_clk_ibuf/O (GTP_INBUF) + U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=173) - 3.204 - 11.081 + net (fanout=1758) + 2.458 + 21.543 - nt_hdmi_in_clk + nt_pix_clk @@ -63610,21 +64175,21 @@ r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[10]/CLK (GTP_DFF_C) + udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[2]/CLK (GTP_DFF_SE) clock pessimism 0.000 - 11.081 + 21.543 clock uncertainty - -0.250 - 10.831 + -0.150 + 21.393 @@ -63632,7 +64197,7 @@ Setup time 0.034 - 10.865 + 21.427 @@ -63641,27 +64206,27 @@ - 3.811 - 4 - 5 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/CLK - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/D + 6.955 + 7 + 13 + u_ov5640/cmos1_8_16bit/image_data_valid0/CLK + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/D - hdmi_in_clk - hdmi_in_clk + cmos1_pclk + cmos1_pclk rise-rise 0.000 4.415 4.415 0.000 - 6.666 - 2.639 - 1.328 (50.3%) - 1.311 (49.7%) + 11.900 + 4.729 + 1.885 (39.9%) + 2.844 (60.1%) - Path #18: setup slack is 3.811(MET) + Path #25: setup slack is 6.955(MET) -
+
Location Delay Type @@ -63671,7 +64236,7 @@ Logical Resource - Clock hdmi_in_clk (rising edge) + Clock cmos1_pclk (rising edge) 0.000 0.000 @@ -63679,12 +64244,12 @@ - hdmi_in_clk + cmos1_pclk 0.000 0.000 r - hdmi_in_clk (port) + cmos1_pclk (port) @@ -63692,7 +64257,7 @@ 0.000 0.000 - hdmi_in_clk + cmos1_pclk @@ -63700,7 +64265,7 @@ - hdmi_in_clk_ibuf/I (GTP_INBUF) + cmos1_pclk_ibuf/I (GTP_INBUF) @@ -63708,15 +64273,15 @@ 1.211 1.211 r - hdmi_in_clk_ibuf/O (GTP_INBUF) + cmos1_pclk_ibuf/O (GTP_INBUF) - net (fanout=173) + net (fanout=126) 3.204 4.415 - nt_hdmi_in_clk + nt_cmos1_pclk @@ -63724,7 +64289,7 @@ r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/CLK (GTP_DFF_CE) + u_ov5640/cmos1_8_16bit/image_data_valid0/CLK (GTP_DFF) @@ -63732,15 +64297,15 @@ 0.329 4.744 r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wbin[0]/Q (GTP_DFF_CE) + u_ov5640/cmos1_8_16bit/image_data_valid0/Q (GTP_DFF) - net (fanout=5) + net (fanout=13) 0.670 5.414 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/wr_addr [0] + u_ov5640/cmos1_href_16bit @@ -63748,23 +64313,47 @@ - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_2/I1 (GTP_LUT5CARRY) + u_ov5640/u_mix_image/N64_4/I0 (GTP_LUT4) td - 0.295 - 5.709 + 0.276 + 5.690 f - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_2/COUT (GTP_LUT5CARRY) + u_ov5640/u_mix_image/N64_4/Z (GTP_LUT4) + + + + net (fanout=3) + 0.605 + 6.295 + + u_ov5640/u_mix_image/wr1_en + + + + + + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_1/I0 (GTP_LUT5CARRY) + + + + td + 0.201 + 6.496 + f + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_1/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 5.709 + 6.496 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16001 + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16412 @@ -63772,23 +64361,23 @@ - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_3/CIN (GTP_LUT5CARRY) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_2/CIN (GTP_LUT5CARRY) td 0.030 - 5.739 + 6.526 r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_3/COUT (GTP_LUT5CARRY) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_2/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 5.739 + 6.526 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16002 + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16413 @@ -63796,23 +64385,23 @@ - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_4/CIN (GTP_LUT5CARRY) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_3/CIN (GTP_LUT5CARRY) td 0.030 - 5.769 + 6.556 r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_4/COUT (GTP_LUT5CARRY) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_3/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 5.769 + 6.556 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16003 + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16414 @@ -63820,23 +64409,23 @@ - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_5/CIN (GTP_LUT5CARRY) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_4/CIN (GTP_LUT5CARRY) td 0.030 - 5.799 + 6.586 r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_5/COUT (GTP_LUT5CARRY) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_4/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 5.799 + 6.586 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16004 + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16415 @@ -63844,23 +64433,23 @@ - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_6/CIN (GTP_LUT5CARRY) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_5/CIN (GTP_LUT5CARRY) td 0.030 - 5.829 + 6.616 r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_6/COUT (GTP_LUT5CARRY) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_5/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 5.829 + 6.616 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16005 + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16416 @@ -63868,23 +64457,23 @@ - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_7/CIN (GTP_LUT5CARRY) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_6/CIN (GTP_LUT5CARRY) td 0.030 - 5.859 + 6.646 r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_7/COUT (GTP_LUT5CARRY) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_6/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 5.859 + 6.646 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16006 + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16417 @@ -63892,23 +64481,23 @@ - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_8/CIN (GTP_LUT5CARRY) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_7/CIN (GTP_LUT5CARRY) td 0.030 - 5.889 + 6.676 r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_8/COUT (GTP_LUT5CARRY) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_7/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 5.889 + 6.676 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16007 + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16418 @@ -63916,23 +64505,23 @@ - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_9/CIN (GTP_LUT5CARRY) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_8/CIN (GTP_LUT5CARRY) td 0.030 - 5.919 + 6.706 r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_9/COUT (GTP_LUT5CARRY) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_8/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 5.919 + 6.706 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/_N16008 + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16419 @@ -63940,23 +64529,47 @@ - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_10/CIN (GTP_LUT5CARRY) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_9/CIN (GTP_LUT5CARRY) + + + + td + 0.030 + 6.736 + r + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_9/COUT (GTP_LUT5CARRY) + + + + net (fanout=1) + 0.000 + 6.736 + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16420 + + + + + + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_10/CIN (GTP_LUT5CARRY) td 0.236 - 6.155 + 6.972 r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2_10/Z (GTP_LUT5CARRY) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_10/Z (GTP_LUT5CARRY) net (fanout=4) 0.641 - 6.796 + 7.613 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N2 [9] + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2 [9] @@ -63964,36 +64577,84 @@ - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N7_9/I4 (GTP_LUT5) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[9]/I0 (GTP_LUT3) td - 0.258 - 7.054 + 0.185 + 7.798 + r + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[9]/Z (GTP_LUT3) + + + + net (fanout=1) + 0.464 + 8.262 + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wwptr [9] + + + + + + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N157.eq_4/I2 (GTP_LUT5CARRY) + + + + td + 0.233 + 8.495 f - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/N7_9/Z (GTP_LUT5) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N157.eq_4/COUT (GTP_LUT5CARRY) + + + + net (fanout=1) + 0.464 + 8.959 + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N157 + + + + + + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N158/I4 (GTP_LUT5) + + + + td + 0.185 + 9.144 + r + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N158/Z (GTP_LUT5) net (fanout=1) 0.000 - 7.054 + 9.144 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wgnext [9] + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N158 - f - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/D (GTP_DFF_C) + r + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/D (GTP_DFF_C)
- +
Location Delay Type @@ -64003,28 +64664,28 @@ Logical Resource - Clock hdmi_in_clk (rising edge) + Clock cmos1_pclk (rising edge) - 6.666 - 6.666 + 11.900 + 11.900 r - hdmi_in_clk + cmos1_pclk 0.000 - 6.666 + 11.900 r - hdmi_in_clk (port) + cmos1_pclk (port) net (fanout=1) 0.000 - 6.666 + 11.900 - hdmi_in_clk + cmos1_pclk @@ -64032,23 +64693,23 @@ - hdmi_in_clk_ibuf/I (GTP_INBUF) + cmos1_pclk_ibuf/I (GTP_INBUF) td 1.211 - 7.877 + 13.111 r - hdmi_in_clk_ibuf/O (GTP_INBUF) + cmos1_pclk_ibuf/O (GTP_INBUF) - net (fanout=173) + net (fanout=126) 3.204 - 11.081 + 16.315 - nt_hdmi_in_clk + nt_cmos1_pclk @@ -64056,13 +64717,13 @@ r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/CLK (GTP_DFF_C) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/CLK (GTP_DFF_C) clock pessimism 0.000 - 11.081 + 16.315 @@ -64070,7 +64731,7 @@ clock uncertainty -0.250 - 10.831 + 16.065 @@ -64078,7 +64739,7 @@ Setup time 0.034 - 10.865 + 16.099 @@ -64087,27 +64748,27 @@ - 5.565 - 6 - 2548 - sync_vg_100m/CLK - udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[0]/D + 6.955 + 7 + 13 + u_ov5640/cmos2_8_16bit/image_data_valid0/CLK + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/D - clk_720p60Hz - clk_720p60Hz + cmos2_pclk + cmos2_pclk rise-rise 0.000 - 8.073 - 8.073 + 4.415 + 4.415 0.000 - 13.473 - 7.792 - 1.471 (18.9%) - 6.321 (81.1%) + 11.900 + 4.729 + 1.885 (39.9%) + 2.844 (60.1%) - Path #19: setup slack is 5.565(MET) + Path #26: setup slack is 6.955(MET) -
+
Location Delay Type @@ -64117,124 +64778,268 @@ Logical Resource - Clock clk_720p60Hz (rising edge) + Clock cmos2_pclk (rising edge) + + 0.000 + 0.000 + r + + + + cmos2_pclk + + 0.000 + 0.000 + r + cmos2_pclk (port) + + + + net (fanout=1) + 0.000 + 0.000 + + cmos2_pclk + + + + + + + + cmos2_pclk_ibuf/I (GTP_INBUF) + + + + td + 1.211 + 1.211 + r + cmos2_pclk_ibuf/O (GTP_INBUF) + + + + net (fanout=126) + 3.204 + 4.415 + + nt_cmos2_pclk + + + + + + + r + u_ov5640/cmos2_8_16bit/image_data_valid0/CLK (GTP_DFF) + + + + tco + 0.329 + 4.744 + r + u_ov5640/cmos2_8_16bit/image_data_valid0/Q (GTP_DFF) + + + + net (fanout=13) + 0.670 + 5.414 + + u_ov5640/cmos2_href_16bit + + + + + + + + u_ov5640/u_mix_image/N78_4/I0 (GTP_LUT4) + + + + td + 0.276 + 5.690 + f + u_ov5640/u_mix_image/N78_4/Z (GTP_LUT4) + + + + net (fanout=3) + 0.605 + 6.295 + + u_ov5640/u_mix_image/wr2_en + + + + + + + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_1/I0 (GTP_LUT5CARRY) + + + + td + 0.201 + 6.496 + f + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_1/COUT (GTP_LUT5CARRY) + + + + net (fanout=1) + 0.000 + 6.496 + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16442 + + + + + + + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_2/CIN (GTP_LUT5CARRY) + + + + td + 0.030 + 6.526 + r + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_2/COUT (GTP_LUT5CARRY) + + + + net (fanout=1) + 0.000 + 6.526 + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16443 + + + + + - 0.000 - 0.000 - r + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_3/CIN (GTP_LUT5CARRY) - clk - - 0.000 - 0.000 + + td + 0.030 + 6.556 r - clk (port) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_3/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 0.000 - - clk + 6.556 + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16444 - + - clk_ibuf/I (GTP_INBUF) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_4/CIN (GTP_LUT5CARRY) - + td - 1.211 - 1.211 + 0.030 + 6.586 r - clk_ibuf/O (GTP_INBUF) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_4/COUT (GTP_LUT5CARRY) net (fanout=1) - 1.091 - 2.302 - - nt_clk + 0.000 + 6.586 + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16445 - + - u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_5/CIN (GTP_LUT5CARRY) - + td - 0.094 - 2.396 + 0.030 + 6.616 r - u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_5/COUT (GTP_LUT5CARRY) - net (fanout=2827) - 3.130 - 5.526 - - rd3_clk + net (fanout=1) + 0.000 + 6.616 + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16446 - + - U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_6/CIN (GTP_LUT5CARRY) - + td - 0.089 - 5.615 + 0.030 + 6.646 r - U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_6/COUT (GTP_LUT5CARRY) - net (fanout=1758) - 2.458 - 8.073 - - nt_pix_clk + net (fanout=1) + 0.000 + 6.646 + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16447 - + - r - sync_vg_100m/CLK (GTP_DFF_P) + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_7/CIN (GTP_LUT5CARRY) - tco - 0.329 - 8.402 + td + 0.030 + 6.676 r - sync_vg_100m/Q (GTP_DFF_P) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_7/COUT (GTP_LUT5CARRY) - net (fanout=2548) - 2.954 - 11.356 + net (fanout=1) + 0.000 + 6.676 - sync_vg_100m + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16448 @@ -64242,23 +65047,23 @@ - udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/I0 (GTP_LUT5) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_8/CIN (GTP_LUT5CARRY) td - 0.185 - 11.541 + 0.030 + 6.706 r - udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/Z (GTP_LUT5) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_8/COUT (GTP_LUT5CARRY) - net (fanout=2) - 0.553 - 12.094 + net (fanout=1) + 0.000 + 6.706 - udp_osd_inst/char_osd_inst/row_pixels_ready + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16449 @@ -64266,23 +65071,23 @@ - udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/I1 (GTP_LUT3) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_9/CIN (GTP_LUT5CARRY) td - 0.185 - 12.279 + 0.030 + 6.736 r - udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/Z (GTP_LUT3) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_9/COUT (GTP_LUT5CARRY) - net (fanout=10) - 0.693 - 12.972 + net (fanout=1) + 0.000 + 6.736 - udp_osd_inst/char_osd_inst/char_next + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16450 @@ -64290,23 +65095,23 @@ - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N97/I0 (GTP_LUT2) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_10/CIN (GTP_LUT5CARRY) td - 0.185 - 13.157 + 0.236 + 6.972 r - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N97/Z (GTP_LUT2) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_10/Z (GTP_LUT5CARRY) - net (fanout=9) - 0.745 - 13.902 + net (fanout=4) + 0.641 + 7.613 - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N97 + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2 [9] @@ -64314,23 +65119,23 @@ - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N839/I1 (GTP_LUT2) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[9]/I2 (GTP_LUT3) td 0.185 - 14.087 + 7.798 r - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N839/Z (GTP_LUT2) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[9]/Z (GTP_LUT3) - net (fanout=3) - 0.605 - 14.692 + net (fanout=1) + 0.464 + 8.262 - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N839 + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wwptr [9] @@ -64338,23 +65143,23 @@ - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_15_3/I2 (GTP_LUT3) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N157.eq_4/I2 (GTP_LUT5CARRY) td - 0.185 - 14.877 - r - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_15_3/Z (GTP_LUT3) + 0.233 + 8.495 + f + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N157.eq_4/COUT (GTP_LUT5CARRY) - net (fanout=11) - 0.771 - 15.648 + net (fanout=1) + 0.464 + 8.959 - udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N18404 + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N157 @@ -64362,23 +65167,23 @@ - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_11_inv[0]/I0 (GTP_LUT5) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N158/I1 (GTP_LUT5) td - 0.217 - 15.865 + 0.185 + 9.144 r - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_11_inv[0]/Z (GTP_LUT5) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N158/Z (GTP_LUT5) net (fanout=1) 0.000 - 15.865 + 9.144 - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847 [0] + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N158 @@ -64386,12 +65191,12 @@ r - udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[0]/D (GTP_DFF_SE) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/D (GTP_DFF_C)
- +
Location Delay Type @@ -64401,28 +65206,28 @@ Logical Resource - Clock clk_720p60Hz (rising edge) + Clock cmos2_pclk (rising edge) - 13.473 - 13.473 + 11.900 + 11.900 r - clk + cmos2_pclk 0.000 - 13.473 + 11.900 r - clk (port) + cmos2_pclk (port) net (fanout=1) 0.000 - 13.473 + 11.900 - clk + cmos2_pclk @@ -64430,71 +65235,23 @@ - clk_ibuf/I (GTP_INBUF) + cmos2_pclk_ibuf/I (GTP_INBUF) td 1.211 - 14.684 - r - clk_ibuf/O (GTP_INBUF) - - - - net (fanout=1) - 1.091 - 15.775 - - nt_clk - - - - - - - - u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) - - - - td - 0.094 - 15.869 - r - u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - - - - net (fanout=2827) - 3.130 - 18.999 - - rd3_clk - - - - - - - - U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) - - - - td - 0.089 - 19.088 + 13.111 r - U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + cmos2_pclk_ibuf/O (GTP_INBUF) - net (fanout=1758) - 2.458 - 21.546 + net (fanout=126) + 3.204 + 16.315 - nt_pix_clk + nt_cmos2_pclk @@ -64502,21 +65259,21 @@ r - udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[0]/CLK (GTP_DFF_SE) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/CLK (GTP_DFF_C) clock pessimism 0.000 - 21.546 + 16.315 clock uncertainty - -0.150 - 21.396 + -0.250 + 16.065 @@ -64524,7 +65281,7 @@ Setup time 0.034 - 21.430 + 16.099 @@ -64533,27 +65290,27 @@ - 5.565 - 6 - 2548 - sync_vg_100m/CLK - udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[1]/D + 8.228 + 5 + 13 + u_ov5640/cmos1_8_16bit/image_data_valid0/CLK + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/D - clk_720p60Hz - clk_720p60Hz + cmos1_pclk + cmos1_pclk rise-rise 0.000 - 8.073 - 8.073 + 4.415 + 4.415 0.000 - 13.473 - 7.792 - 1.471 (18.9%) - 6.321 (81.1%) + 11.900 + 3.456 + 1.540 (44.6%) + 1.916 (55.4%) - Path #20: setup slack is 5.565(MET) + Path #27: setup slack is 8.228(MET) -
+
Location Delay Type @@ -64563,7 +65320,7 @@ Logical Resource - Clock clk_720p60Hz (rising edge) + Clock cmos1_pclk (rising edge) 0.000 0.000 @@ -64571,12 +65328,12 @@ - clk + cmos1_pclk 0.000 0.000 r - clk (port) + cmos1_pclk (port) @@ -64584,7 +65341,7 @@ 0.000 0.000 - clk + cmos1_pclk @@ -64592,7 +65349,7 @@ - clk_ibuf/I (GTP_INBUF) + cmos1_pclk_ibuf/I (GTP_INBUF) @@ -64600,87 +65357,87 @@ 1.211 1.211 r - clk_ibuf/O (GTP_INBUF) + cmos1_pclk_ibuf/O (GTP_INBUF) - net (fanout=1) - 1.091 - 2.302 + net (fanout=126) + 3.204 + 4.415 - nt_clk + nt_cmos1_pclk - - u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + r + u_ov5640/cmos1_8_16bit/image_data_valid0/CLK (GTP_DFF) - - td - 0.094 - 2.396 + + tco + 0.329 + 4.744 r - u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + u_ov5640/cmos1_8_16bit/image_data_valid0/Q (GTP_DFF) - net (fanout=2827) - 3.130 - 5.526 - - rd3_clk + net (fanout=13) + 0.670 + 5.414 + + u_ov5640/cmos1_href_16bit - + - U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) + u_ov5640/u_mix_image/N64_4/I0 (GTP_LUT4) - + td - 0.089 - 5.615 - r - U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + 0.276 + 5.690 + f + u_ov5640/u_mix_image/N64_4/Z (GTP_LUT4) - net (fanout=1758) - 2.458 - 8.073 - - nt_pix_clk + net (fanout=3) + 0.605 + 6.295 + + u_ov5640/u_mix_image/wr1_en - + - r - sync_vg_100m/CLK (GTP_DFF_P) + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_1/I0 (GTP_LUT5CARRY) - tco - 0.329 - 8.402 - r - sync_vg_100m/Q (GTP_DFF_P) + td + 0.201 + 6.496 + f + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_1/COUT (GTP_LUT5CARRY) - net (fanout=2548) - 2.954 - 11.356 + net (fanout=1) + 0.000 + 6.496 - sync_vg_100m + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16412 @@ -64688,23 +65445,23 @@ - udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/I0 (GTP_LUT5) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_2/CIN (GTP_LUT5CARRY) td - 0.185 - 11.541 + 0.030 + 6.526 r - udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/Z (GTP_LUT5) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_2/COUT (GTP_LUT5CARRY) - net (fanout=2) - 0.553 - 12.094 + net (fanout=1) + 0.000 + 6.526 - udp_osd_inst/char_osd_inst/row_pixels_ready + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16413 @@ -64712,23 +65469,23 @@ - udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/I1 (GTP_LUT3) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_3/CIN (GTP_LUT5CARRY) td - 0.185 - 12.279 + 0.030 + 6.556 r - udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/Z (GTP_LUT3) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_3/COUT (GTP_LUT5CARRY) - net (fanout=10) - 0.693 - 12.972 + net (fanout=1) + 0.000 + 6.556 - udp_osd_inst/char_osd_inst/char_next + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16414 @@ -64736,23 +65493,23 @@ - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N97/I0 (GTP_LUT2) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_4/CIN (GTP_LUT5CARRY) td - 0.185 - 13.157 + 0.030 + 6.586 r - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N97/Z (GTP_LUT2) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_4/COUT (GTP_LUT5CARRY) - net (fanout=9) - 0.745 - 13.902 + net (fanout=1) + 0.000 + 6.586 - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N97 + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16415 @@ -64760,23 +65517,23 @@ - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N839/I1 (GTP_LUT2) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_5/CIN (GTP_LUT5CARRY) td - 0.185 - 14.087 + 0.030 + 6.616 r - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N839/Z (GTP_LUT2) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_5/COUT (GTP_LUT5CARRY) - net (fanout=3) - 0.605 - 14.692 + net (fanout=1) + 0.000 + 6.616 - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N839 + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16416 @@ -64784,23 +65541,23 @@ - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_15_3/I2 (GTP_LUT3) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_6/CIN (GTP_LUT5CARRY) td - 0.185 - 14.877 + 0.030 + 6.646 r - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_15_3/Z (GTP_LUT3) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_6/COUT (GTP_LUT5CARRY) - net (fanout=11) - 0.771 - 15.648 + net (fanout=1) + 0.000 + 6.646 - udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N18404 + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16417 @@ -64808,115 +65565,163 @@ - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_11_inv[1]/I0 (GTP_LUT5) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_7/CIN (GTP_LUT5CARRY) td - 0.217 - 15.865 + 0.030 + 6.676 r - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_11_inv[1]/Z (GTP_LUT5) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_7/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 15.865 + 6.676 - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847 [1] + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16418 + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_8/CIN (GTP_LUT5CARRY) + + + + td + 0.030 + 6.706 r - udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[1]/D (GTP_DFF_SE) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_8/COUT (GTP_LUT5CARRY) -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - Clock clk_720p60Hz (rising edge) - 13.473 - 13.473 - r + net (fanout=1) + 0.000 + 6.706 + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16419 + + + + + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_9/CIN (GTP_LUT5CARRY) - clk - - 0.000 - 13.473 + + td + 0.030 + 6.736 r - clk (port) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_9/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 13.473 - - clk + 6.736 + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16420 - + - clk_ibuf/I (GTP_INBUF) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_10/CIN (GTP_LUT5CARRY) - + td - 1.211 - 14.684 + 0.236 + 6.972 r - clk_ibuf/O (GTP_INBUF) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_10/Z (GTP_LUT5CARRY) + + + + net (fanout=4) + 0.641 + 7.613 + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2 [9] + + + + + + + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N7_9/I0 (GTP_LUT5) + + + + td + 0.258 + 7.871 + f + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N7_9/Z (GTP_LUT5) + + + + net (fanout=1) + 0.000 + 7.871 + + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wgnext [9] + - net (fanout=1) - 1.091 - 15.775 - nt_clk + + f + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/D (GTP_DFF_C) +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + - - - + Clock cmos1_pclk (rising edge) + 11.900 + 11.900 + r - u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + cmos1_pclk - td - 0.094 - 15.869 + 0.000 + 11.900 r - u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + cmos1_pclk (port) - net (fanout=2827) - 3.130 - 18.999 + net (fanout=1) + 0.000 + 11.900 - rd3_clk + cmos1_pclk @@ -64924,23 +65729,23 @@ - U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) + cmos1_pclk_ibuf/I (GTP_INBUF) td - 0.089 - 19.088 + 1.211 + 13.111 r - U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + cmos1_pclk_ibuf/O (GTP_INBUF) - net (fanout=1758) - 2.458 - 21.546 + net (fanout=126) + 3.204 + 16.315 - nt_pix_clk + nt_cmos1_pclk @@ -64948,21 +65753,21 @@ r - udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[1]/CLK (GTP_DFF_SE) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/CLK (GTP_DFF_C) clock pessimism 0.000 - 21.546 + 16.315 clock uncertainty - -0.150 - 21.396 + -0.250 + 16.065 @@ -64970,7 +65775,7 @@ Setup time 0.034 - 21.430 + 16.099 @@ -64979,27 +65784,27 @@ - 5.565 - 6 - 2548 - sync_vg_100m/CLK - udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[2]/D + 8.228 + 5 + 13 + u_ov5640/cmos2_8_16bit/image_data_valid0/CLK + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/D - clk_720p60Hz - clk_720p60Hz + cmos2_pclk + cmos2_pclk rise-rise 0.000 - 8.073 - 8.073 + 4.415 + 4.415 0.000 - 13.473 - 7.792 - 1.471 (18.9%) - 6.321 (81.1%) + 11.900 + 3.456 + 1.540 (44.6%) + 1.916 (55.4%) - Path #21: setup slack is 5.565(MET) + Path #28: setup slack is 8.228(MET) -
+
Location Delay Type @@ -65009,7 +65814,7 @@ Logical Resource - Clock clk_720p60Hz (rising edge) + Clock cmos2_pclk (rising edge) 0.000 0.000 @@ -65017,12 +65822,12 @@ - clk + cmos2_pclk 0.000 0.000 r - clk (port) + cmos2_pclk (port) @@ -65030,7 +65835,7 @@ 0.000 0.000 - clk + cmos2_pclk @@ -65038,7 +65843,7 @@ - clk_ibuf/I (GTP_INBUF) + cmos2_pclk_ibuf/I (GTP_INBUF) @@ -65046,87 +65851,87 @@ 1.211 1.211 r - clk_ibuf/O (GTP_INBUF) + cmos2_pclk_ibuf/O (GTP_INBUF) - net (fanout=1) - 1.091 - 2.302 + net (fanout=126) + 3.204 + 4.415 - nt_clk + nt_cmos2_pclk - - u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + r + u_ov5640/cmos2_8_16bit/image_data_valid0/CLK (GTP_DFF) - - td - 0.094 - 2.396 + + tco + 0.329 + 4.744 r - u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + u_ov5640/cmos2_8_16bit/image_data_valid0/Q (GTP_DFF) - net (fanout=2827) - 3.130 - 5.526 - - rd3_clk + net (fanout=13) + 0.670 + 5.414 + + u_ov5640/cmos2_href_16bit - + - U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) + u_ov5640/u_mix_image/N78_4/I0 (GTP_LUT4) - + td - 0.089 - 5.615 - r - U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + 0.276 + 5.690 + f + u_ov5640/u_mix_image/N78_4/Z (GTP_LUT4) - net (fanout=1758) - 2.458 - 8.073 - - nt_pix_clk + net (fanout=3) + 0.605 + 6.295 + + u_ov5640/u_mix_image/wr2_en - + - r - sync_vg_100m/CLK (GTP_DFF_P) + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_1/I0 (GTP_LUT5CARRY) - tco - 0.329 - 8.402 - r - sync_vg_100m/Q (GTP_DFF_P) + td + 0.201 + 6.496 + f + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_1/COUT (GTP_LUT5CARRY) - net (fanout=2548) - 2.954 - 11.356 + net (fanout=1) + 0.000 + 6.496 - sync_vg_100m + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16442 @@ -65134,23 +65939,23 @@ - udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/I0 (GTP_LUT5) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_2/CIN (GTP_LUT5CARRY) td - 0.185 - 11.541 + 0.030 + 6.526 r - udp_osd_inst/char_osd_inst/pixels_shifter_inst/N45/Z (GTP_LUT5) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_2/COUT (GTP_LUT5CARRY) - net (fanout=2) - 0.553 - 12.094 + net (fanout=1) + 0.000 + 6.526 - udp_osd_inst/char_osd_inst/row_pixels_ready + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16443 @@ -65158,23 +65963,23 @@ - udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/I1 (GTP_LUT3) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_3/CIN (GTP_LUT5CARRY) td - 0.185 - 12.279 + 0.030 + 6.556 r - udp_osd_inst/char_osd_inst/char_pic_rom_inst/N42_2/Z (GTP_LUT3) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_3/COUT (GTP_LUT5CARRY) - net (fanout=10) - 0.693 - 12.972 + net (fanout=1) + 0.000 + 6.556 - udp_osd_inst/char_osd_inst/char_next + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16444 @@ -65182,23 +65987,23 @@ - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N97/I0 (GTP_LUT2) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_4/CIN (GTP_LUT5CARRY) td - 0.185 - 13.157 + 0.030 + 6.586 r - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N97/Z (GTP_LUT2) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_4/COUT (GTP_LUT5CARRY) - net (fanout=9) - 0.745 - 13.902 + net (fanout=1) + 0.000 + 6.586 - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N97 + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16445 @@ -65206,23 +66011,23 @@ - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N839/I1 (GTP_LUT2) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_5/CIN (GTP_LUT5CARRY) td - 0.185 - 14.087 + 0.030 + 6.616 r - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N839/Z (GTP_LUT2) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_5/COUT (GTP_LUT5CARRY) - net (fanout=3) - 0.605 - 14.692 + net (fanout=1) + 0.000 + 6.616 - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N839 + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16446 @@ -65230,23 +66035,23 @@ - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_15_3/I2 (GTP_LUT3) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_6/CIN (GTP_LUT5CARRY) td - 0.185 - 14.877 + 0.030 + 6.646 r - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_15_3/Z (GTP_LUT3) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_6/COUT (GTP_LUT5CARRY) - net (fanout=11) - 0.771 - 15.648 + net (fanout=1) + 0.000 + 6.646 - udp_osd_inst/char_osd_inst/char_buf_reader_inst/_N18404 + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16447 @@ -65254,115 +66059,163 @@ - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_11_inv[2]/I0 (GTP_LUT5) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_7/CIN (GTP_LUT5CARRY) td - 0.217 - 15.865 + 0.030 + 6.676 r - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847_11_inv[2]/Z (GTP_LUT5) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_7/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 15.865 + 6.676 - udp_osd_inst/char_osd_inst/char_buf_reader_inst/N847 [2] + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16448 + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_8/CIN (GTP_LUT5CARRY) + + + + td + 0.030 + 6.706 r - udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[2]/D (GTP_DFF_SE) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_8/COUT (GTP_LUT5CARRY) -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - Clock clk_720p60Hz (rising edge) - 13.473 - 13.473 - r + net (fanout=1) + 0.000 + 6.706 + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16449 + + + + + + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_9/CIN (GTP_LUT5CARRY) - clk - - 0.000 - 13.473 + + td + 0.030 + 6.736 r - clk (port) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_9/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 13.473 - - clk + 6.736 + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16450 - + - clk_ibuf/I (GTP_INBUF) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_10/CIN (GTP_LUT5CARRY) - + td - 1.211 - 14.684 + 0.236 + 6.972 r - clk_ibuf/O (GTP_INBUF) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_10/Z (GTP_LUT5CARRY) - net (fanout=1) - 1.091 - 15.775 + net (fanout=4) + 0.641 + 7.613 + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2 [9] + + + - nt_clk + + + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N7_9/I2 (GTP_LUT5) + + + + td + 0.258 + 7.871 + f + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N7_9/Z (GTP_LUT5) - + net (fanout=1) + 0.000 + 7.871 + + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wgnext [9] + + + - u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + f + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/D (GTP_DFF_C) + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock cmos2_pclk (rising edge) + + 11.900 + 11.900 + r + + cmos2_pclk - td - 0.094 - 15.869 + 0.000 + 11.900 r - u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + cmos2_pclk (port) - net (fanout=2827) - 3.130 - 18.999 + net (fanout=1) + 0.000 + 11.900 - rd3_clk + cmos2_pclk @@ -65370,23 +66223,23 @@ - U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) + cmos2_pclk_ibuf/I (GTP_INBUF) td - 0.089 - 19.088 + 1.211 + 13.111 r - U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + cmos2_pclk_ibuf/O (GTP_INBUF) - net (fanout=1758) - 2.458 - 21.546 + net (fanout=126) + 3.204 + 16.315 - nt_pix_clk + nt_cmos2_pclk @@ -65394,21 +66247,21 @@ r - udp_osd_inst/char_osd_inst/char_buf_reader_inst/ram_addr[2]/CLK (GTP_DFF_SE) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/CLK (GTP_DFF_C) clock pessimism 0.000 - 21.546 + 16.315 clock uncertainty - -0.150 - 21.396 + -0.250 + 16.065 @@ -65416,7 +66269,7 @@ Setup time 0.034 - 21.430 + 16.099 @@ -65425,11 +66278,11 @@ - 6.955 - 7 + 8.258 + 5 13 u_ov5640/cmos1_8_16bit/image_data_valid0/CLK - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/D + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/D cmos1_pclk cmos1_pclk @@ -65439,13 +66292,13 @@ 4.415 0.000 11.900 - 4.729 - 1.885 (39.9%) - 2.844 (60.1%) + 3.426 + 1.510 (44.1%) + 1.916 (55.9%) - Path #22: setup slack is 6.955(MET) + Path #29: setup slack is 8.258(MET) -
+
Location Delay Type @@ -65524,7 +66377,7 @@ 0.670 5.414 - u_ov5640/cmos1_href_16bit + u_ov5640/cmos1_href_16bit @@ -65572,7 +66425,7 @@ 0.000 6.496 - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16508 + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16412 @@ -65596,7 +66449,7 @@ 0.000 6.526 - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16509 + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16413 @@ -65620,7 +66473,7 @@ 0.000 6.556 - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16510 + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16414 @@ -65644,7 +66497,7 @@ 0.000 6.586 - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16511 + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16415 @@ -65668,7 +66521,7 @@ 0.000 6.616 - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16512 + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16416 @@ -65692,7 +66545,7 @@ 0.000 6.646 - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16513 + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16417 @@ -65716,7 +66569,7 @@ 0.000 6.676 - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16514 + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16418 @@ -65740,7 +66593,7 @@ 0.000 6.706 - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16515 + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16419 @@ -65750,69 +66603,21 @@ u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_9/CIN (GTP_LUT5CARRY) - - - td - 0.030 - 6.736 - r - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_9/COUT (GTP_LUT5CARRY) - - - - net (fanout=1) - 0.000 - 6.736 - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16516 - - - - - - - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_10/CIN (GTP_LUT5CARRY) - td 0.236 - 6.972 + 6.942 r - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_10/Z (GTP_LUT5CARRY) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_9/Z (GTP_LUT5CARRY) net (fanout=4) 0.641 - 7.613 - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2 [9] - - - - - - - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[9]/I0 (GTP_LUT3) - - - - td - 0.185 - 7.798 - r - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[9]/Z (GTP_LUT3) - - - - net (fanout=1) - 0.464 - 8.262 + 7.583 - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wwptr [9] + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2 [8] @@ -65820,55 +66625,31 @@ - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N157.eq_4/I2 (GTP_LUT5CARRY) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N7_8/I0 (GTP_LUT5) td - 0.233 - 8.495 + 0.258 + 7.841 f - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N157.eq_4/COUT (GTP_LUT5CARRY) - - - - net (fanout=1) - 0.464 - 8.959 - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N157 - - - - - - - - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N158/I4 (GTP_LUT5) - - - - td - 0.185 - 9.144 - r - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N158/Z (GTP_LUT5) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N7_8/Z (GTP_LUT5) net (fanout=1) 0.000 - 9.144 + 7.841 - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N158 + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wgnext [8] - r - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/D (GTP_DFF_C) + f + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/D (GTP_DFF_C)
@@ -65936,7 +66717,7 @@ r - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/CLK (GTP_DFF_C) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/CLK (GTP_DFF_C)
clock pessimism @@ -65967,11 +66748,11 @@ - 6.955 - 7 + 8.258 + 5 13 u_ov5640/cmos2_8_16bit/image_data_valid0/CLK - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/D + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/D cmos2_pclk cmos2_pclk @@ -65981,13 +66762,13 @@ 4.415 0.000 11.900 - 4.729 - 1.885 (39.9%) - 2.844 (60.1%) + 3.426 + 1.510 (44.1%) + 1.916 (55.9%) - Path #23: setup slack is 6.955(MET) + Path #30: setup slack is 8.258(MET) - +
Location Delay Type @@ -66066,7 +66847,7 @@ 0.670 5.414 - u_ov5640/cmos2_href_16bit + u_ov5640/cmos2_href_16bit @@ -66114,7 +66895,7 @@ 0.000 6.496 - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16532 + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16442 @@ -66138,7 +66919,7 @@ 0.000 6.526 - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16533 + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16443 @@ -66162,7 +66943,7 @@ 0.000 6.556 - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16534 + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16444 @@ -66186,7 +66967,7 @@ 0.000 6.586 - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16535 + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16445 @@ -66210,7 +66991,7 @@ 0.000 6.616 - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16536 + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16446 @@ -66234,7 +67015,7 @@ 0.000 6.646 - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16537 + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16447 @@ -66258,7 +67039,7 @@ 0.000 6.676 - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16538 + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16448 @@ -66282,7 +67063,7 @@ 0.000 6.706 - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16539 + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16449 @@ -66292,69 +67073,21 @@ u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_9/CIN (GTP_LUT5CARRY) - - - td - 0.030 - 6.736 - r - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_9/COUT (GTP_LUT5CARRY) - - - - net (fanout=1) - 0.000 - 6.736 - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16540 - - - - - - - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_10/CIN (GTP_LUT5CARRY) - td 0.236 - 6.972 + 6.942 r - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_10/Z (GTP_LUT5CARRY) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_9/Z (GTP_LUT5CARRY) net (fanout=4) 0.641 - 7.613 - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2 [9] - - - - - - - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[9]/I2 (GTP_LUT3) - - - - td - 0.185 - 7.798 - r - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N3[9]/Z (GTP_LUT3) - - - - net (fanout=1) - 0.464 - 8.262 + 7.583 - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wwptr [9] + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2 [8] @@ -66362,55 +67095,31 @@ - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N157.eq_4/I2 (GTP_LUT5CARRY) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N7_8/I3 (GTP_LUT5) td - 0.233 - 8.495 + 0.258 + 7.841 f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N157.eq_4/COUT (GTP_LUT5CARRY) - - - - net (fanout=1) - 0.464 - 8.959 - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N157 - - - - - - - - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N158/I1 (GTP_LUT5) - - - - td - 0.185 - 9.144 - r - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N158/Z (GTP_LUT5) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N7_8/Z (GTP_LUT5) net (fanout=1) 0.000 - 9.144 + 7.841 - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N158 + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wgnext [8] - r - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/D (GTP_DFF_C) + f + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/D (GTP_DFF_C)
@@ -66478,7 +67187,7 @@ r - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_wfull/CLK (GTP_DFF_C) + u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/CLK (GTP_DFF_C)
clock pessimism @@ -66509,27 +67218,27 @@ - 8.228 - 5 - 13 - u_ov5640/cmos1_8_16bit/image_data_valid0/CLK - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/D + 12.149 + 7 + 6 + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/CLKB + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/D - cmos1_pclk - cmos1_pclk + clk_50m + clk_50m rise-rise + -0.515 + 6.038 + 5.523 0.000 - 4.415 - 4.415 - 0.000 - 11.900 - 3.456 - 1.540 (44.6%) - 1.916 (55.4%) + 20.000 + 7.220 + 3.825 (53.0%) + 3.395 (47.0%) - Path #24: setup slack is 8.228(MET) + Path #31: setup slack is 12.149(MET) - +
Location Delay Type @@ -66539,7 +67248,7 @@ Logical Resource - Clock cmos1_pclk (rising edge) + Clock clk_50m (rising edge) 0.000 0.000 @@ -66547,12 +67256,12 @@ - cmos1_pclk + clk 0.000 0.000 r - cmos1_pclk (port) + clk (port) @@ -66560,7 +67269,7 @@ 0.000 0.000 - cmos1_pclk + clk @@ -66568,7 +67277,7 @@ - cmos1_pclk_ibuf/I (GTP_INBUF) + clk_ibuf/I (GTP_INBUF) @@ -66576,39 +67285,63 @@ 1.211 1.211 r - cmos1_pclk_ibuf/O (GTP_INBUF) + clk_ibuf/O (GTP_INBUF) - net (fanout=126) - 3.204 - 4.415 + net (fanout=1) + 1.091 + 2.302 - nt_cmos1_pclk + nt_clk + + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.094 + 2.396 r - u_ov5640/cmos1_8_16bit/image_data_valid0/CLK (GTP_DFF) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + + + + net (fanout=2825) + 3.642 + 6.038 + + rd3_clk + + + + + + + r + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/CLKB (GTP_DRM9K) tco - 0.329 - 4.744 - r - u_ov5640/cmos1_8_16bit/image_data_valid0/Q (GTP_DFF) + 2.024 + 8.062 + f + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/DOB[0] (GTP_DRM9K) - net (fanout=13) - 0.670 - 5.414 + net (fanout=6) + 1.132 + 9.194 - u_ov5640/cmos1_href_16bit + u_rotate_image/dout [0] @@ -66616,23 +67349,23 @@ - u_ov5640/u_mix_image/N64_4/I0 (GTP_LUT4) + u_rotate_image/N181_1/I2 (GTP_LUT5) td - 0.276 - 5.690 - f - u_ov5640/u_mix_image/N64_4/Z (GTP_LUT4) + 0.185 + 9.379 + r + u_rotate_image/N181_1/Z (GTP_LUT5) - net (fanout=3) - 0.605 - 6.295 + net (fanout=4) + 0.641 + 10.020 - u_ov5640/u_mix_image/wr1_en + u_rotate_image/addr_fifo_rd_en @@ -66640,23 +67373,23 @@ - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_1/I0 (GTP_LUT5CARRY) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_1/I0 (GTP_LUT5CARRY) td 0.201 - 6.496 + 10.221 f - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_1/COUT (GTP_LUT5CARRY) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_1/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 6.496 + 10.221 - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16508 + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16575 @@ -66664,23 +67397,23 @@ - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_2/CIN (GTP_LUT5CARRY) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_2/CIN (GTP_LUT5CARRY) td 0.030 - 6.526 + 10.251 r - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_2/COUT (GTP_LUT5CARRY) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_2/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 6.526 + 10.251 - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16509 + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16576 @@ -66688,23 +67421,23 @@ - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_3/CIN (GTP_LUT5CARRY) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_3/CIN (GTP_LUT5CARRY) td 0.030 - 6.556 + 10.281 r - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_3/COUT (GTP_LUT5CARRY) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_3/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 6.556 + 10.281 - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16510 + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16577 @@ -66712,23 +67445,23 @@ - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_4/CIN (GTP_LUT5CARRY) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_4/CIN (GTP_LUT5CARRY) td 0.030 - 6.586 + 10.311 r - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_4/COUT (GTP_LUT5CARRY) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_4/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 6.586 + 10.311 - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16511 + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16578 @@ -66736,23 +67469,23 @@ - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_5/CIN (GTP_LUT5CARRY) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_5/CIN (GTP_LUT5CARRY) td 0.030 - 6.616 + 10.341 r - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_5/COUT (GTP_LUT5CARRY) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_5/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 6.616 + 10.341 - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16512 + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16579 @@ -66760,23 +67493,23 @@ - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_6/CIN (GTP_LUT5CARRY) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_6/CIN (GTP_LUT5CARRY) td 0.030 - 6.646 + 10.371 r - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_6/COUT (GTP_LUT5CARRY) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_6/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 6.646 + 10.371 - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16513 + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16580 @@ -66784,23 +67517,23 @@ - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_7/CIN (GTP_LUT5CARRY) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_7/CIN (GTP_LUT5CARRY) td 0.030 - 6.676 + 10.401 r - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_7/COUT (GTP_LUT5CARRY) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_7/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 6.676 + 10.401 - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16514 + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16581 @@ -66808,23 +67541,23 @@ - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_8/CIN (GTP_LUT5CARRY) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_8/CIN (GTP_LUT5CARRY) td 0.030 - 6.706 + 10.431 r - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_8/COUT (GTP_LUT5CARRY) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_8/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 6.706 + 10.431 - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16515 + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16582 @@ -66832,23 +67565,71 @@ - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_9/CIN (GTP_LUT5CARRY) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_9/CIN (GTP_LUT5CARRY) td - 0.030 - 6.736 + 0.236 + 10.667 r - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_9/COUT (GTP_LUT5CARRY) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_9/Z (GTP_LUT5CARRY) + + + + net (fanout=2) + 0.553 + 11.220 + + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11 [8] + + + + + + + + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[8]/I2 (GTP_LUT3) + + + + td + 0.185 + 11.405 + r + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[8]/Z (GTP_LUT3) + + + + net (fanout=3) + 0.605 + 12.010 + + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/rrptr [8] + + + + + + + + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_4/I1 (GTP_LUT5CARRY) + + + + td + 0.363 + 12.373 + f + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_4/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 6.736 + 12.373 - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16516 + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.co [8] @@ -66856,23 +67637,23 @@ - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_10/CIN (GTP_LUT5CARRY) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_5/CIN (GTP_LUT5CARRY) td 0.236 - 6.972 + 12.609 r - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_10/Z (GTP_LUT5CARRY) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_5/Z (GTP_LUT5CARRY) - net (fanout=4) - 0.641 - 7.613 + net (fanout=1) + 0.464 + 13.073 - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2 [9] + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21 @@ -66880,36 +67661,36 @@ - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N7_9/I0 (GTP_LUT5) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N22/I0 (GTP_LUT2) td - 0.258 - 7.871 - f - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N7_9/Z (GTP_LUT5) + 0.185 + 13.258 + r + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N22/Z (GTP_LUT2) net (fanout=1) 0.000 - 7.871 + 13.258 - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wgnext [9] + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N22 - f - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/D (GTP_DFF_C) + r + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/D (GTP_DFF_C)
- +
Location Delay Type @@ -66919,28 +67700,52 @@ Logical Resource - Clock cmos1_pclk (rising edge) + Clock clk_50m (rising edge) + + 20.000 + 20.000 + r + + + + clk + + 0.000 + 20.000 + r + clk (port) + + + + net (fanout=1) + 0.000 + 20.000 + + clk + + + - 11.900 - 11.900 - r + + + clk_ibuf/I (GTP_INBUF) - cmos1_pclk - 0.000 - 11.900 + td + 1.211 + 21.211 r - cmos1_pclk (port) + clk_ibuf/O (GTP_INBUF) net (fanout=1) - 0.000 - 11.900 + 1.091 + 22.302 - cmos1_pclk + nt_clk @@ -66948,23 +67753,23 @@ - cmos1_pclk_ibuf/I (GTP_INBUF) + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td - 1.211 - 13.111 + 0.094 + 22.396 r - cmos1_pclk_ibuf/O (GTP_INBUF) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=126) - 3.204 - 16.315 + net (fanout=2825) + 3.127 + 25.523 - nt_cmos1_pclk + rd3_clk @@ -66972,21 +67777,21 @@ r - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/CLK (GTP_DFF_C) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/CLK (GTP_DFF_C) clock pessimism 0.000 - 16.315 + 25.523 clock uncertainty - -0.250 - 16.065 + -0.150 + 25.373 @@ -66994,7 +67799,7 @@ Setup time 0.034 - 16.099 + 25.407 @@ -67003,27 +67808,27 @@ - 8.228 - 5 - 13 - u_ov5640/cmos2_8_16bit/image_data_valid0/CLK - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/D + 12.300 + 10 + 17 + image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[1]/CLK + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/D - cmos2_pclk - cmos2_pclk + clk_50m + clk_50m rise-rise 0.000 - 4.415 - 4.415 + 5.523 + 5.523 0.000 - 11.900 - 3.456 - 1.540 (44.6%) - 1.916 (55.4%) + 20.000 + 7.584 + 2.808 (37.0%) + 4.776 (63.0%) - Path #25: setup slack is 8.228(MET) + Path #32: setup slack is 12.300(MET) -
+
Location Delay Type @@ -67033,7 +67838,7 @@ Logical Resource - Clock cmos2_pclk (rising edge) + Clock clk_50m (rising edge) 0.000 0.000 @@ -67041,12 +67846,12 @@ - cmos2_pclk + clk 0.000 0.000 r - cmos2_pclk (port) + clk (port) @@ -67054,7 +67859,7 @@ 0.000 0.000 - cmos2_pclk + clk @@ -67062,7 +67867,7 @@ - cmos2_pclk_ibuf/I (GTP_INBUF) + clk_ibuf/I (GTP_INBUF) @@ -67070,15 +67875,39 @@ 1.211 1.211 r - cmos2_pclk_ibuf/O (GTP_INBUF) + clk_ibuf/O (GTP_INBUF) - net (fanout=126) - 3.204 - 4.415 + net (fanout=1) + 1.091 + 2.302 - nt_cmos2_pclk + nt_clk + + + + + + + + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.094 + 2.396 + r + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + + + + net (fanout=2825) + 3.127 + 5.523 + + rd3_clk @@ -67086,23 +67915,23 @@ r - u_ov5640/cmos2_8_16bit/image_data_valid0/CLK (GTP_DFF) + image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[1]/CLK (GTP_DFF_RE) tco 0.329 - 4.744 + 5.852 r - u_ov5640/cmos2_8_16bit/image_data_valid0/Q (GTP_DFF) + image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[1]/Q (GTP_DFF_RE) - net (fanout=13) - 0.670 - 5.414 + net (fanout=3) + 0.605 + 6.457 - u_ov5640/cmos2_href_16bit + image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt [1] @@ -67110,23 +67939,23 @@ - u_ov5640/u_mix_image/N78_4/I0 (GTP_LUT4) + image_filiter_inst2/multiline_buffer_inst/N53_mux5_8/I0 (GTP_LUT5) td - 0.276 - 5.690 + 0.308 + 6.765 f - u_ov5640/u_mix_image/N78_4/Z (GTP_LUT4) + image_filiter_inst2/multiline_buffer_inst/N53_mux5_8/Z (GTP_LUT5) - net (fanout=3) - 0.605 - 6.295 + net (fanout=4) + 0.641 + 7.406 - u_ov5640/u_mix_image/wr2_en + image_filiter_inst2/multiline_buffer_inst/N53 @@ -67134,23 +67963,95 @@ - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_1/I0 (GTP_LUT5CARRY) + image_filiter_inst2/multiline_buffer_inst/N199_mux5/I0 (GTP_LUT2) + + + + td + 0.185 + 7.591 + r + image_filiter_inst2/multiline_buffer_inst/N199_mux5/Z (GTP_LUT2) + + + + net (fanout=17) + 0.826 + 8.417 + + image_filiter_inst2/multiline_buffer_inst/N199 + + + + + + + + image_filiter_inst2/multiline_buffer_inst/N96_1/I0 (GTP_LUT5) + + + + td + 0.185 + 8.602 + r + image_filiter_inst2/multiline_buffer_inst/N96_1/Z (GTP_LUT5) + + + + net (fanout=1) + 0.464 + 9.066 + + image_filiter_inst2/multiline_buffer_inst/N96 + + + + + + + + image_filiter_inst2/multiline_buffer_inst/N130[0]/I1 (GTP_LUT5) + + + + td + 0.185 + 9.251 + r + image_filiter_inst2/multiline_buffer_inst/N130[0]/Z (GTP_LUT5) + + + + net (fanout=5) + 0.670 + 9.921 + + image_filiter_inst2/multiline_buffer_inst/rd_en [0] + + + + + + + + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_1/I0 (GTP_LUT5CARRY) td 0.201 - 6.496 + 10.122 f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_1/COUT (GTP_LUT5CARRY) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_1/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 6.496 + 10.122 - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16532 + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13410 @@ -67158,23 +68059,23 @@ - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_2/CIN (GTP_LUT5CARRY) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_2/CIN (GTP_LUT5CARRY) td 0.030 - 6.526 + 10.152 r - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_2/COUT (GTP_LUT5CARRY) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_2/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 6.526 + 10.152 - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16533 + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13411 @@ -67182,23 +68083,23 @@ - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_3/CIN (GTP_LUT5CARRY) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_3/CIN (GTP_LUT5CARRY) td 0.030 - 6.556 + 10.182 r - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_3/COUT (GTP_LUT5CARRY) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_3/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 6.556 + 10.182 - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16534 + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13412 @@ -67206,23 +68107,23 @@ - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_4/CIN (GTP_LUT5CARRY) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_4/CIN (GTP_LUT5CARRY) td 0.030 - 6.586 + 10.212 r - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_4/COUT (GTP_LUT5CARRY) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_4/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 6.586 + 10.212 - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16535 + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13413 @@ -67230,23 +68131,23 @@ - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_5/CIN (GTP_LUT5CARRY) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_5/CIN (GTP_LUT5CARRY) td 0.030 - 6.616 + 10.242 r - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_5/COUT (GTP_LUT5CARRY) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_5/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 6.616 + 10.242 - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16536 + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13414 @@ -67254,23 +68155,23 @@ - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_6/CIN (GTP_LUT5CARRY) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_6/CIN (GTP_LUT5CARRY) td 0.030 - 6.646 + 10.272 r - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_6/COUT (GTP_LUT5CARRY) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_6/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 6.646 + 10.272 - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16537 + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13415 @@ -67278,23 +68179,23 @@ - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_7/CIN (GTP_LUT5CARRY) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_7/CIN (GTP_LUT5CARRY) td 0.030 - 6.676 + 10.302 r - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_7/COUT (GTP_LUT5CARRY) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_7/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 6.676 + 10.302 - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16538 + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13416 @@ -67302,23 +68203,23 @@ - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_8/CIN (GTP_LUT5CARRY) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_8/CIN (GTP_LUT5CARRY) td 0.030 - 6.706 + 10.332 r - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_8/COUT (GTP_LUT5CARRY) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_8/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 6.706 + 10.332 - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16539 + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13417 @@ -67326,23 +68227,71 @@ - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_9/CIN (GTP_LUT5CARRY) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_9/CIN (GTP_LUT5CARRY) td - 0.030 - 6.736 + 0.236 + 10.568 r - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_9/COUT (GTP_LUT5CARRY) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_9/Z (GTP_LUT5CARRY) + + + + net (fanout=2) + 0.553 + 11.121 + + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11 [8] + + + + + + + + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[8]/I2 (GTP_LUT3) + + + + td + 0.185 + 11.306 + r + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[8]/Z (GTP_LUT3) + + + + net (fanout=2) + 0.553 + 11.859 + + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/rrptr [8] + + + + + + + + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N21.eq_4/I1 (GTP_LUT5CARRY) + + + + td + 0.363 + 12.222 + f + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N21.eq_4/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 6.736 + 12.222 - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16540 + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N21.co [8] @@ -67350,23 +68299,23 @@ - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_10/CIN (GTP_LUT5CARRY) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N21.eq_5/CIN (GTP_LUT5CARRY) td 0.236 - 6.972 + 12.458 r - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_10/Z (GTP_LUT5CARRY) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N21.eq_5/Z (GTP_LUT5CARRY) - net (fanout=4) - 0.641 - 7.613 + net (fanout=1) + 0.464 + 12.922 - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2 [9] + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N21 @@ -67374,36 +68323,36 @@ - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N7_9/I2 (GTP_LUT5) + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N22/I4 (GTP_LUT5) td - 0.258 - 7.871 - f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N7_9/Z (GTP_LUT5) + 0.185 + 13.107 + r + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N22/Z (GTP_LUT5) net (fanout=1) 0.000 - 7.871 + 13.107 - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wgnext [9] + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N22 - f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/D (GTP_DFF_C) + r + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/D (GTP_DFF_C)
- +
Location Delay Type @@ -67413,28 +68362,28 @@ Logical Resource - Clock cmos2_pclk (rising edge) + Clock clk_50m (rising edge) - 11.900 - 11.900 + 20.000 + 20.000 r - cmos2_pclk + clk 0.000 - 11.900 + 20.000 r - cmos2_pclk (port) + clk (port) net (fanout=1) 0.000 - 11.900 + 20.000 - cmos2_pclk + clk @@ -67442,45 +68391,69 @@ - cmos2_pclk_ibuf/I (GTP_INBUF) + clk_ibuf/I (GTP_INBUF) td 1.211 - 13.111 + 21.211 r - cmos2_pclk_ibuf/O (GTP_INBUF) + clk_ibuf/O (GTP_INBUF) - net (fanout=126) - 3.204 - 16.315 + net (fanout=1) + 1.091 + 22.302 - nt_cmos2_pclk + nt_clk + + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.094 + 22.396 r - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[9]/CLK (GTP_DFF_C) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + + + + net (fanout=2825) + 3.127 + 25.523 + + rd3_clk + + + + + + + r + image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/CLK (GTP_DFF_C) clock pessimism 0.000 - 16.315 + 25.523 clock uncertainty - -0.250 - 16.065 + -0.150 + 25.373 @@ -67488,7 +68461,7 @@ Setup time 0.034 - 16.099 + 25.407 @@ -67497,27 +68470,27 @@ - 8.258 - 5 - 13 - u_ov5640/cmos1_8_16bit/image_data_valid0/CLK - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/D + 12.437 + 7 + 6 + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/CLKB + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/D - cmos1_pclk - cmos1_pclk + clk_50m + clk_50m rise-rise + -0.515 + 6.038 + 5.523 0.000 - 4.415 - 4.415 - 0.000 - 11.900 - 3.426 - 1.510 (44.1%) - 1.916 (55.9%) + 20.000 + 6.932 + 3.589 (51.8%) + 3.343 (48.2%) - Path #26: setup slack is 8.258(MET) + Path #33: setup slack is 12.437(MET) -
+
Location Delay Type @@ -67527,7 +68500,7 @@ Logical Resource - Clock cmos1_pclk (rising edge) + Clock clk_50m (rising edge) 0.000 0.000 @@ -67535,12 +68508,12 @@ - cmos1_pclk + clk 0.000 0.000 r - cmos1_pclk (port) + clk (port) @@ -67548,7 +68521,7 @@ 0.000 0.000 - cmos1_pclk + clk @@ -67556,7 +68529,7 @@ - cmos1_pclk_ibuf/I (GTP_INBUF) + clk_ibuf/I (GTP_INBUF) @@ -67564,15 +68537,39 @@ 1.211 1.211 r - cmos1_pclk_ibuf/O (GTP_INBUF) + clk_ibuf/O (GTP_INBUF) - net (fanout=126) - 3.204 - 4.415 + net (fanout=1) + 1.091 + 2.302 - nt_cmos1_pclk + nt_clk + + + + + + + + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.094 + 2.396 + r + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + + + + net (fanout=2825) + 3.642 + 6.038 + + rd3_clk @@ -67580,23 +68577,71 @@ r - u_ov5640/cmos1_8_16bit/image_data_valid0/CLK (GTP_DFF) + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/CLKB (GTP_DRM9K) tco - 0.329 - 4.744 + 2.024 + 8.062 + f + u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/DOB[0] (GTP_DRM9K) + + + + net (fanout=6) + 1.132 + 9.194 + + u_rotate_image/dout [0] + + + + + + + + u_rotate_image/N170_5/I2 (GTP_LUT4) + + + + td + 0.185 + 9.379 r - u_ov5640/cmos1_8_16bit/image_data_valid0/Q (GTP_DFF) + u_rotate_image/N170_5/Z (GTP_LUT4) - net (fanout=13) - 0.670 - 5.414 + net (fanout=4) + 0.641 + 10.020 + + u_rotate_image/N170 + + + + + + + + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_1/I0 (GTP_LUT5CARRY) + + + + td + 0.201 + 10.221 + f + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_1/COUT (GTP_LUT5CARRY) + + + + net (fanout=1) + 0.000 + 10.221 - u_ov5640/cmos1_href_16bit + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16600 @@ -67604,23 +68649,23 @@ - u_ov5640/u_mix_image/N64_4/I0 (GTP_LUT4) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_2/CIN (GTP_LUT5CARRY) td - 0.276 - 5.690 - f - u_ov5640/u_mix_image/N64_4/Z (GTP_LUT4) + 0.030 + 10.251 + r + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_2/COUT (GTP_LUT5CARRY) - net (fanout=3) - 0.605 - 6.295 + net (fanout=1) + 0.000 + 10.251 - u_ov5640/u_mix_image/wr1_en + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16601 @@ -67628,23 +68673,23 @@ - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_1/I0 (GTP_LUT5CARRY) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_3/CIN (GTP_LUT5CARRY) td - 0.201 - 6.496 - f - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_1/COUT (GTP_LUT5CARRY) + 0.030 + 10.281 + r + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_3/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 6.496 + 10.281 - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16508 + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16602 @@ -67652,23 +68697,23 @@ - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_2/CIN (GTP_LUT5CARRY) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_4/CIN (GTP_LUT5CARRY) td 0.030 - 6.526 + 10.311 r - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_2/COUT (GTP_LUT5CARRY) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_4/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 6.526 + 10.311 - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16509 + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16603 @@ -67676,23 +68721,23 @@ - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_3/CIN (GTP_LUT5CARRY) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_5/CIN (GTP_LUT5CARRY) td 0.030 - 6.556 + 10.341 r - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_3/COUT (GTP_LUT5CARRY) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_5/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 6.556 + 10.341 - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16510 + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16604 @@ -67700,23 +68745,23 @@ - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_4/CIN (GTP_LUT5CARRY) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_6/CIN (GTP_LUT5CARRY) td 0.030 - 6.586 + 10.371 r - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_4/COUT (GTP_LUT5CARRY) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_6/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 6.586 + 10.371 - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16511 + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16605 @@ -67724,23 +68769,23 @@ - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_5/CIN (GTP_LUT5CARRY) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_7/CIN (GTP_LUT5CARRY) td 0.030 - 6.616 + 10.401 r - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_5/COUT (GTP_LUT5CARRY) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_7/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 6.616 + 10.401 - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16512 + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16606 @@ -67748,23 +68793,23 @@ - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_6/CIN (GTP_LUT5CARRY) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_8/CIN (GTP_LUT5CARRY) td 0.030 - 6.646 + 10.431 r - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_6/COUT (GTP_LUT5CARRY) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_8/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 6.646 + 10.431 - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16513 + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16607 @@ -67772,23 +68817,23 @@ - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_7/CIN (GTP_LUT5CARRY) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_9/CIN (GTP_LUT5CARRY) td - 0.030 - 6.676 + 0.236 + 10.667 r - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_7/COUT (GTP_LUT5CARRY) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_9/Z (GTP_LUT5CARRY) - net (fanout=1) - 0.000 - 6.676 + net (fanout=2) + 0.553 + 11.220 - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16514 + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11 [8] @@ -67796,23 +68841,23 @@ - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_8/CIN (GTP_LUT5CARRY) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[8]/I2 (GTP_LUT3) td - 0.030 - 6.706 + 0.185 + 11.405 r - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_8/COUT (GTP_LUT5CARRY) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[8]/Z (GTP_LUT3) net (fanout=1) - 0.000 - 6.706 + 0.464 + 11.869 - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16515 + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/rrptr [8] @@ -67820,23 +68865,23 @@ - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_9/CIN (GTP_LUT5CARRY) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N24.eq_4/I1 (GTP_LUT5CARRY) td - 0.236 - 6.942 - r - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_9/Z (GTP_LUT5CARRY) + 0.363 + 12.232 + f + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N24.eq_4/COUT (GTP_LUT5CARRY) - net (fanout=4) - 0.641 - 7.583 + net (fanout=2) + 0.553 + 12.785 - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2 [8] + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N21 @@ -67844,36 +68889,36 @@ - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N7_8/I0 (GTP_LUT5) + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N22/I1 (GTP_LUT5) td - 0.258 - 7.841 - f - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N7_8/Z (GTP_LUT5) + 0.185 + 12.970 + r + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N22/Z (GTP_LUT5) net (fanout=1) 0.000 - 7.841 + 12.970 - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wgnext [8] + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N22 - f - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/D (GTP_DFF_C) + r + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/D (GTP_DFF_C)
- +
Location Delay Type @@ -67883,28 +68928,28 @@ Logical Resource - Clock cmos1_pclk (rising edge) + Clock clk_50m (rising edge) - 11.900 - 11.900 + 20.000 + 20.000 r - cmos1_pclk + clk 0.000 - 11.900 + 20.000 r - cmos1_pclk (port) + clk (port) net (fanout=1) 0.000 - 11.900 + 20.000 - cmos1_pclk + clk @@ -67912,45 +68957,69 @@ - cmos1_pclk_ibuf/I (GTP_INBUF) + clk_ibuf/I (GTP_INBUF) td 1.211 - 13.111 + 21.211 r - cmos1_pclk_ibuf/O (GTP_INBUF) + clk_ibuf/O (GTP_INBUF) - net (fanout=126) - 3.204 - 16.315 + net (fanout=1) + 1.091 + 22.302 - nt_cmos1_pclk + nt_clk + + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.094 + 22.396 r - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/CLK (GTP_DFF_C) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + + + + net (fanout=2825) + 3.127 + 25.523 + + rd3_clk + + + + + + + r + u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/CLK (GTP_DFF_C) clock pessimism 0.000 - 16.315 + 25.523 clock uncertainty - -0.250 - 16.065 + -0.150 + 25.373 @@ -67958,7 +69027,7 @@ Setup time 0.034 - 16.099 + 25.407 @@ -67967,27 +69036,27 @@ - 8.258 + 36.471 5 - 13 - u_ov5640/cmos2_8_16bit/image_data_valid0/CLK - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/D + 12 + u_ov5640/coms1_reg_config/clock_20k_cnt[0]/CLK + u_ov5640/coms1_reg_config/clock_20k_cnt[10]/D - cmos2_pclk - cmos2_pclk + clk_25m + clk_25m rise-rise 0.000 - 4.415 - 4.415 + 3.113 + 3.113 0.000 - 11.900 - 3.426 - 1.510 (44.1%) - 1.916 (55.9%) + 40.000 + 3.413 + 1.526 (44.7%) + 1.887 (55.3%) - Path #27: setup slack is 8.258(MET) + Path #34: setup slack is 36.471(MET) -
+
Location Delay Type @@ -67997,7 +69066,7 @@ Logical Resource - Clock cmos2_pclk (rising edge) + Clock clk_25m (rising edge) 0.000 0.000 @@ -68005,12 +69074,12 @@ - cmos2_pclk + clk 0.000 0.000 r - cmos2_pclk (port) + clk (port) @@ -68018,7 +69087,7 @@ 0.000 0.000 - cmos2_pclk + clk @@ -68026,7 +69095,7 @@ - cmos2_pclk_ibuf/I (GTP_INBUF) + clk_ibuf/I (GTP_INBUF) @@ -68034,15 +69103,39 @@ 1.211 1.211 r - cmos2_pclk_ibuf/O (GTP_INBUF) + clk_ibuf/O (GTP_INBUF) - net (fanout=126) - 3.204 - 4.415 + net (fanout=1) + 1.091 + 2.302 - nt_cmos2_pclk + nt_clk + + + + + + + + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.098 + 2.400 + r + u_sys_pll/u_pll_e3/CLKOUT3 (GTP_PLL_E3) + + + + net (fanout=26) + 0.713 + 3.113 + + clk_25m @@ -68050,23 +69143,23 @@ r - u_ov5640/cmos2_8_16bit/image_data_valid0/CLK (GTP_DFF) + u_ov5640/coms1_reg_config/clock_20k_cnt[0]/CLK (GTP_DFF_R) tco 0.329 - 4.744 + 3.442 r - u_ov5640/cmos2_8_16bit/image_data_valid0/Q (GTP_DFF) + u_ov5640/coms1_reg_config/clock_20k_cnt[0]/Q (GTP_DFF_R) - net (fanout=13) - 0.670 - 5.414 + net (fanout=4) + 0.641 + 4.083 - u_ov5640/cmos2_href_16bit + u_ov5640/coms1_reg_config/clock_20k_cnt [0] @@ -68074,23 +69167,23 @@ - u_ov5640/u_mix_image/N78_4/I0 (GTP_LUT4) + u_ov5640/coms1_reg_config/N8_mux4_5/I0 (GTP_LUT5) td - 0.276 - 5.690 + 0.303 + 4.386 f - u_ov5640/u_mix_image/N78_4/Z (GTP_LUT4) + u_ov5640/coms1_reg_config/N8_mux4_5/Z (GTP_LUT5) - net (fanout=3) - 0.605 - 6.295 + net (fanout=1) + 0.464 + 4.850 - u_ov5640/u_mix_image/wr2_en + u_ov5640/coms1_reg_config/_N9677 @@ -68098,23 +69191,47 @@ - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_1/I0 (GTP_LUT5CARRY) + u_ov5640/coms1_reg_config/N8_mux10/I0 (GTP_LUT5) td - 0.201 - 6.496 + 0.185 + 5.035 + r + u_ov5640/coms1_reg_config/N8_mux10/Z (GTP_LUT5) + + + + net (fanout=12) + 0.782 + 5.817 + + u_ov5640/coms1_reg_config/N8 + + + + + + + + u_ov5640/coms1_reg_config/N11_2_1/I2 (GTP_LUT5CARRY) + + + + td + 0.233 + 6.050 f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_1/COUT (GTP_LUT5CARRY) + u_ov5640/coms1_reg_config/N11_2_1/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 6.496 + 6.050 - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16532 + u_ov5640/coms1_reg_config/_N16267 @@ -68122,23 +69239,23 @@ - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_2/CIN (GTP_LUT5CARRY) + u_ov5640/coms1_reg_config/N11_2_2/CIN (GTP_LUT5CARRY) td 0.030 - 6.526 + 6.080 r - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_2/COUT (GTP_LUT5CARRY) + u_ov5640/coms1_reg_config/N11_2_2/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 6.526 + 6.080 - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16533 + u_ov5640/coms1_reg_config/_N16268 @@ -68146,23 +69263,23 @@ - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_3/CIN (GTP_LUT5CARRY) + u_ov5640/coms1_reg_config/N11_2_3/CIN (GTP_LUT5CARRY) td 0.030 - 6.556 + 6.110 r - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_3/COUT (GTP_LUT5CARRY) + u_ov5640/coms1_reg_config/N11_2_3/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 6.556 + 6.110 - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16534 + u_ov5640/coms1_reg_config/_N16269 @@ -68170,23 +69287,23 @@ - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_4/CIN (GTP_LUT5CARRY) + u_ov5640/coms1_reg_config/N11_2_4/CIN (GTP_LUT5CARRY) td 0.030 - 6.586 + 6.140 r - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_4/COUT (GTP_LUT5CARRY) + u_ov5640/coms1_reg_config/N11_2_4/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 6.586 + 6.140 - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16535 + u_ov5640/coms1_reg_config/_N16270 @@ -68194,23 +69311,23 @@ - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_5/CIN (GTP_LUT5CARRY) + u_ov5640/coms1_reg_config/N11_2_5/CIN (GTP_LUT5CARRY) td 0.030 - 6.616 + 6.170 r - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_5/COUT (GTP_LUT5CARRY) + u_ov5640/coms1_reg_config/N11_2_5/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 6.616 + 6.170 - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16536 + u_ov5640/coms1_reg_config/_N16271 @@ -68218,23 +69335,23 @@ - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_6/CIN (GTP_LUT5CARRY) + u_ov5640/coms1_reg_config/N11_2_6/CIN (GTP_LUT5CARRY) td 0.030 - 6.646 + 6.200 r - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_6/COUT (GTP_LUT5CARRY) + u_ov5640/coms1_reg_config/N11_2_6/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 6.646 + 6.200 - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16537 + u_ov5640/coms1_reg_config/_N16272 @@ -68242,23 +69359,23 @@ - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_7/CIN (GTP_LUT5CARRY) + u_ov5640/coms1_reg_config/N11_2_7/CIN (GTP_LUT5CARRY) td 0.030 - 6.676 + 6.230 r - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_7/COUT (GTP_LUT5CARRY) + u_ov5640/coms1_reg_config/N11_2_7/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 6.676 + 6.230 - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16538 + u_ov5640/coms1_reg_config/_N16273 @@ -68266,23 +69383,23 @@ - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_8/CIN (GTP_LUT5CARRY) + u_ov5640/coms1_reg_config/N11_2_8/CIN (GTP_LUT5CARRY) td 0.030 - 6.706 + 6.260 r - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_8/COUT (GTP_LUT5CARRY) + u_ov5640/coms1_reg_config/N11_2_8/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 6.706 + 6.260 - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/_N16539 + u_ov5640/coms1_reg_config/_N16274 @@ -68290,23 +69407,23 @@ - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_9/CIN (GTP_LUT5CARRY) + u_ov5640/coms1_reg_config/N11_2_9/CIN (GTP_LUT5CARRY) td - 0.236 - 6.942 + 0.030 + 6.290 r - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2_9/Z (GTP_LUT5CARRY) + u_ov5640/coms1_reg_config/N11_2_9/COUT (GTP_LUT5CARRY) - net (fanout=4) - 0.641 - 7.583 + net (fanout=1) + 0.000 + 6.290 - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N2 [8] + u_ov5640/coms1_reg_config/_N16275 @@ -68314,36 +69431,36 @@ - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N7_8/I3 (GTP_LUT5) + u_ov5640/coms1_reg_config/N11_2_10/CIN (GTP_LUT5CARRY) td - 0.258 - 7.841 - f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/N7_8/Z (GTP_LUT5) + 0.236 + 6.526 + r + u_ov5640/coms1_reg_config/N11_2_10/Z (GTP_LUT5CARRY) net (fanout=1) 0.000 - 7.841 + 6.526 - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/wgnext [8] + u_ov5640/coms1_reg_config/N1114 [10] - f - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/D (GTP_DFF_C) + r + u_ov5640/coms1_reg_config/clock_20k_cnt[10]/D (GTP_DFF_R)
- +
Location Delay Type @@ -68353,28 +69470,28 @@ Logical Resource - Clock cmos2_pclk (rising edge) + Clock clk_25m (rising edge) - 11.900 - 11.900 + 40.000 + 40.000 r - cmos2_pclk + clk 0.000 - 11.900 + 40.000 r - cmos2_pclk (port) + clk (port) net (fanout=1) 0.000 - 11.900 + 40.000 - cmos2_pclk + clk @@ -68382,45 +69499,69 @@ - cmos2_pclk_ibuf/I (GTP_INBUF) + clk_ibuf/I (GTP_INBUF) td 1.211 - 13.111 + 41.211 r - cmos2_pclk_ibuf/O (GTP_INBUF) + clk_ibuf/O (GTP_INBUF) - net (fanout=126) - 3.204 - 16.315 + net (fanout=1) + 1.091 + 42.302 - nt_cmos2_pclk + nt_clk + + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.098 + 42.400 r - u_ov5640/u_mix_image/u_mix_fifo2/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[8]/CLK (GTP_DFF_C) + u_sys_pll/u_pll_e3/CLKOUT3 (GTP_PLL_E3) + + + + net (fanout=26) + 0.713 + 43.113 + + clk_25m + + + + + + + r + u_ov5640/coms1_reg_config/clock_20k_cnt[10]/CLK (GTP_DFF_R) clock pessimism 0.000 - 16.315 + 43.113 clock uncertainty - -0.250 - 16.065 + -0.150 + 42.963 @@ -68428,7 +69569,7 @@ Setup time 0.034 - 16.099 + 42.997 @@ -68437,27 +69578,27 @@ - 12.150 - 7 - 6 - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/CLKB - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/D + 36.471 + 5 + 12 + u_ov5640/coms2_reg_config/clock_20k_cnt[0]/CLK + u_ov5640/coms2_reg_config/clock_20k_cnt[10]/D - clk_50m - clk_50m + clk_25m + clk_25m rise-rise - -0.514 - 6.040 - 5.526 0.000 - 20.000 - 7.220 - 3.825 (53.0%) - 3.395 (47.0%) + 3.113 + 3.113 + 0.000 + 40.000 + 3.413 + 1.526 (44.7%) + 1.887 (55.3%) - Path #28: setup slack is 12.150(MET) + Path #35: setup slack is 36.471(MET) -
+
Location Delay Type @@ -68467,7 +69608,7 @@ Logical Resource - Clock clk_50m (rising edge) + Clock clk_25m (rising edge) 0.000 0.000 @@ -68525,66 +69666,42 @@ td - 0.094 - 2.396 - r - u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - - - - net (fanout=2827) - 3.644 - 6.040 - - rd3_clk - - - - - - - r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/CLKB (GTP_DRM9K) - - - - tco - 2.024 - 8.064 - f - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/DOB[0] (GTP_DRM9K) + 0.098 + 2.400 + r + u_sys_pll/u_pll_e3/CLKOUT3 (GTP_PLL_E3) - net (fanout=6) - 1.132 - 9.196 - - u_rotate_image/dout [0] + net (fanout=26) + 0.713 + 3.113 + + clk_25m - - + - u_rotate_image/N181_1/I2 (GTP_LUT5) + r + u_ov5640/coms2_reg_config/clock_20k_cnt[0]/CLK (GTP_DFF_R) - td - 0.185 - 9.381 + tco + 0.329 + 3.442 r - u_rotate_image/N181_1/Z (GTP_LUT5) + u_ov5640/coms2_reg_config/clock_20k_cnt[0]/Q (GTP_DFF_R) net (fanout=4) 0.641 - 10.022 + 4.083 - u_rotate_image/addr_fifo_rd_en + u_ov5640/coms2_reg_config/clock_20k_cnt [0] @@ -68592,23 +69709,23 @@ - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_1/I0 (GTP_LUT5CARRY) + u_ov5640/coms2_reg_config/N8_mux4_5/I4 (GTP_LUT5) td - 0.201 - 10.223 + 0.303 + 4.386 f - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_1/COUT (GTP_LUT5CARRY) + u_ov5640/coms2_reg_config/N8_mux4_5/Z (GTP_LUT5) net (fanout=1) - 0.000 - 10.223 + 0.464 + 4.850 - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16636 + u_ov5640/coms2_reg_config/_N9749 @@ -68616,23 +69733,23 @@ - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_2/CIN (GTP_LUT5CARRY) + u_ov5640/coms2_reg_config/N8_mux10/I0 (GTP_LUT5) td - 0.030 - 10.253 + 0.185 + 5.035 r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_2/COUT (GTP_LUT5CARRY) + u_ov5640/coms2_reg_config/N8_mux10/Z (GTP_LUT5) - net (fanout=1) - 0.000 - 10.253 + net (fanout=12) + 0.782 + 5.817 - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16637 + u_ov5640/coms2_reg_config/N8 @@ -68640,23 +69757,23 @@ - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_3/CIN (GTP_LUT5CARRY) + u_ov5640/coms2_reg_config/N11_2_1/I2 (GTP_LUT5CARRY) td - 0.030 - 10.283 - r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_3/COUT (GTP_LUT5CARRY) + 0.233 + 6.050 + f + u_ov5640/coms2_reg_config/N11_2_1/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 10.283 + 6.050 - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16638 + u_ov5640/coms2_reg_config/_N16302 @@ -68664,23 +69781,23 @@ - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_4/CIN (GTP_LUT5CARRY) + u_ov5640/coms2_reg_config/N11_2_2/CIN (GTP_LUT5CARRY) td 0.030 - 10.313 + 6.080 r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_4/COUT (GTP_LUT5CARRY) + u_ov5640/coms2_reg_config/N11_2_2/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 10.313 + 6.080 - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16639 + u_ov5640/coms2_reg_config/_N16303 @@ -68688,23 +69805,23 @@ - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_5/CIN (GTP_LUT5CARRY) + u_ov5640/coms2_reg_config/N11_2_3/CIN (GTP_LUT5CARRY) td 0.030 - 10.343 + 6.110 r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_5/COUT (GTP_LUT5CARRY) + u_ov5640/coms2_reg_config/N11_2_3/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 10.343 + 6.110 - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16640 + u_ov5640/coms2_reg_config/_N16304 @@ -68712,23 +69829,23 @@ - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_6/CIN (GTP_LUT5CARRY) + u_ov5640/coms2_reg_config/N11_2_4/CIN (GTP_LUT5CARRY) td 0.030 - 10.373 + 6.140 r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_6/COUT (GTP_LUT5CARRY) + u_ov5640/coms2_reg_config/N11_2_4/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 10.373 + 6.140 - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16641 + u_ov5640/coms2_reg_config/_N16305 @@ -68736,23 +69853,23 @@ - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_7/CIN (GTP_LUT5CARRY) + u_ov5640/coms2_reg_config/N11_2_5/CIN (GTP_LUT5CARRY) td 0.030 - 10.403 + 6.170 r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_7/COUT (GTP_LUT5CARRY) + u_ov5640/coms2_reg_config/N11_2_5/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 10.403 + 6.170 - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16642 + u_ov5640/coms2_reg_config/_N16306 @@ -68760,23 +69877,23 @@ - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_8/CIN (GTP_LUT5CARRY) + u_ov5640/coms2_reg_config/N11_2_6/CIN (GTP_LUT5CARRY) td 0.030 - 10.433 + 6.200 r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_8/COUT (GTP_LUT5CARRY) + u_ov5640/coms2_reg_config/N11_2_6/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 10.433 + 6.200 - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/_N16643 + u_ov5640/coms2_reg_config/_N16307 @@ -68784,23 +69901,23 @@ - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_9/CIN (GTP_LUT5CARRY) + u_ov5640/coms2_reg_config/N11_2_7/CIN (GTP_LUT5CARRY) td - 0.236 - 10.669 + 0.030 + 6.230 r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11_9/Z (GTP_LUT5CARRY) + u_ov5640/coms2_reg_config/N11_2_7/COUT (GTP_LUT5CARRY) - net (fanout=2) - 0.553 - 11.222 + net (fanout=1) + 0.000 + 6.230 - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N11 [8] + u_ov5640/coms2_reg_config/_N16308 @@ -68808,47 +69925,23 @@ - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[8]/I2 (GTP_LUT3) + u_ov5640/coms2_reg_config/N11_2_8/CIN (GTP_LUT5CARRY) td - 0.185 - 11.407 + 0.030 + 6.260 r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N12[8]/Z (GTP_LUT3) - - - - net (fanout=3) - 0.605 - 12.012 - - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/rrptr [8] - - - - - - - - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_4/I1 (GTP_LUT5CARRY) - - - - td - 0.363 - 12.375 - f - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_4/COUT (GTP_LUT5CARRY) + u_ov5640/coms2_reg_config/N11_2_8/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 12.375 + 6.260 - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.co [8] + u_ov5640/coms2_reg_config/_N16309 @@ -68856,23 +69949,23 @@ - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_5/CIN (GTP_LUT5CARRY) + u_ov5640/coms2_reg_config/N11_2_9/CIN (GTP_LUT5CARRY) td - 0.236 - 12.611 + 0.030 + 6.290 r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21.eq_5/Z (GTP_LUT5CARRY) + u_ov5640/coms2_reg_config/N11_2_9/COUT (GTP_LUT5CARRY) net (fanout=1) - 0.464 - 13.075 + 0.000 + 6.290 - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N21 + u_ov5640/coms2_reg_config/_N16310 @@ -68880,23 +69973,23 @@ - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N22/I0 (GTP_LUT2) + u_ov5640/coms2_reg_config/N11_2_10/CIN (GTP_LUT5CARRY) td - 0.185 - 13.260 + 0.236 + 6.526 r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N22/Z (GTP_LUT2) + u_ov5640/coms2_reg_config/N11_2_10/Z (GTP_LUT5CARRY) net (fanout=1) 0.000 - 13.260 + 6.526 - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/N22 + u_ov5640/coms2_reg_config/N1114 [10] @@ -68904,12 +69997,12 @@ r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/D (GTP_DFF_C) + u_ov5640/coms2_reg_config/clock_20k_cnt[10]/D (GTP_DFF_R)
- +
Location Delay Type @@ -68919,10 +70012,10 @@ Logical Resource - Clock clk_50m (rising edge) + Clock clk_25m (rising edge) - 20.000 - 20.000 + 40.000 + 40.000 r @@ -68930,7 +70023,7 @@ clk0.000 - 20.000 + 40.000rclk (port) @@ -68938,7 +70031,7 @@ net (fanout=1) 0.000 - 20.000 + 40.000 clk @@ -68954,7 +70047,7 @@ td 1.211 - 21.211 + 41.211 r clk_ibuf/O (GTP_INBUF) @@ -68962,7 +70055,7 @@ net (fanout=1) 1.091 - 22.302 + 42.302 nt_clk @@ -68977,18 +70070,18 @@ td - 0.094 - 22.396 + 0.098 + 42.400 r - u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT3 (GTP_PLL_E3) - net (fanout=2827) - 3.130 - 25.526 + net (fanout=26) + 0.713 + 43.113 - rd3_clk + clk_25m @@ -68996,13 +70089,13 @@ r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/CLK (GTP_DFF_C) + u_ov5640/coms2_reg_config/clock_20k_cnt[10]/CLK (GTP_DFF_R) clock pessimism 0.000 - 25.526 + 43.113 @@ -69010,7 +70103,7 @@ clock uncertainty -0.150 - 25.376 + 42.963 @@ -69018,7 +70111,7 @@ Setup time 0.034 - 25.410 + 42.997 @@ -69027,27 +70120,27 @@ - 12.300 - 10 - 17 - image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[1]/CLK - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/D + 36.501 + 5 + 12 + u_ov5640/coms1_reg_config/clock_20k_cnt[0]/CLK + u_ov5640/coms1_reg_config/clock_20k_cnt[9]/D - clk_50m - clk_50m + clk_25m + clk_25m rise-rise 0.000 - 5.526 - 5.526 + 3.113 + 3.113 0.000 - 20.000 - 7.584 - 2.808 (37.0%) - 4.776 (63.0%) + 40.000 + 3.383 + 1.496 (44.2%) + 1.887 (55.8%) - Path #29: setup slack is 12.300(MET) + Path #36: setup slack is 36.501(MET) -
+
Location Delay Type @@ -69057,7 +70150,7 @@ Logical Resource - Clock clk_50m (rising edge) + Clock clk_25m (rising edge) 0.000 0.000 @@ -69115,18 +70208,18 @@ td - 0.094 - 2.396 + 0.098 + 2.400 r - u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT3 (GTP_PLL_E3) - net (fanout=2827) - 3.130 - 5.526 + net (fanout=26) + 0.713 + 3.113 - rd3_clk + clk_25m @@ -69134,23 +70227,23 @@ r - image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[1]/CLK (GTP_DFF_RE) + u_ov5640/coms1_reg_config/clock_20k_cnt[0]/CLK (GTP_DFF_R) tco 0.329 - 5.855 + 3.442 r - image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt[1]/Q (GTP_DFF_RE) + u_ov5640/coms1_reg_config/clock_20k_cnt[0]/Q (GTP_DFF_R) - net (fanout=3) - 0.605 - 6.460 + net (fanout=4) + 0.641 + 4.083 - image_filiter_inst2/multiline_buffer_inst/tail_ver_cnt [1] + u_ov5640/coms1_reg_config/clock_20k_cnt [0] @@ -69158,23 +70251,23 @@ - image_filiter_inst2/multiline_buffer_inst/N199_mux5_8/I0 (GTP_LUT5) + u_ov5640/coms1_reg_config/N8_mux4_5/I0 (GTP_LUT5) td - 0.308 - 6.768 + 0.303 + 4.386 f - image_filiter_inst2/multiline_buffer_inst/N199_mux5_8/Z (GTP_LUT5) + u_ov5640/coms1_reg_config/N8_mux4_5/Z (GTP_LUT5) - net (fanout=4) - 0.641 - 7.409 + net (fanout=1) + 0.464 + 4.850 - image_filiter_inst2/multiline_buffer_inst/N53 + u_ov5640/coms1_reg_config/_N9677 @@ -69182,23 +70275,23 @@ - image_filiter_inst2/multiline_buffer_inst/N199_mux5/I0 (GTP_LUT2) + u_ov5640/coms1_reg_config/N8_mux10/I0 (GTP_LUT5) td 0.185 - 7.594 + 5.035 r - image_filiter_inst2/multiline_buffer_inst/N199_mux5/Z (GTP_LUT2) + u_ov5640/coms1_reg_config/N8_mux10/Z (GTP_LUT5) - net (fanout=17) - 0.826 - 8.420 + net (fanout=12) + 0.782 + 5.817 - image_filiter_inst2/multiline_buffer_inst/N199 + u_ov5640/coms1_reg_config/N8 @@ -69206,23 +70299,47 @@ - image_filiter_inst2/multiline_buffer_inst/N96_3/I0 (GTP_LUT5) + u_ov5640/coms1_reg_config/N11_2_1/I2 (GTP_LUT5CARRY) td - 0.185 - 8.605 + 0.233 + 6.050 + f + u_ov5640/coms1_reg_config/N11_2_1/COUT (GTP_LUT5CARRY) + + + + net (fanout=1) + 0.000 + 6.050 + + u_ov5640/coms1_reg_config/_N16267 + + + + + + + + u_ov5640/coms1_reg_config/N11_2_2/CIN (GTP_LUT5CARRY) + + + + td + 0.030 + 6.080 r - image_filiter_inst2/multiline_buffer_inst/N96_3/Z (GTP_LUT5) + u_ov5640/coms1_reg_config/N11_2_2/COUT (GTP_LUT5CARRY) net (fanout=1) - 0.464 - 9.069 + 0.000 + 6.080 - image_filiter_inst2/multiline_buffer_inst/N96 + u_ov5640/coms1_reg_config/_N16268 @@ -69230,23 +70347,23 @@ - image_filiter_inst2/multiline_buffer_inst/N130[0]/I1 (GTP_LUT5) + u_ov5640/coms1_reg_config/N11_2_3/CIN (GTP_LUT5CARRY) td - 0.185 - 9.254 + 0.030 + 6.110 r - image_filiter_inst2/multiline_buffer_inst/N130[0]/Z (GTP_LUT5) + u_ov5640/coms1_reg_config/N11_2_3/COUT (GTP_LUT5CARRY) - net (fanout=5) - 0.670 - 9.924 + net (fanout=1) + 0.000 + 6.110 - image_filiter_inst2/multiline_buffer_inst/rd_en [0] + u_ov5640/coms1_reg_config/_N16269 @@ -69254,23 +70371,23 @@ - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_1/I0 (GTP_LUT5CARRY) + u_ov5640/coms1_reg_config/N11_2_4/CIN (GTP_LUT5CARRY) td - 0.201 - 10.125 - f - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_1/COUT (GTP_LUT5CARRY) + 0.030 + 6.140 + r + u_ov5640/coms1_reg_config/N11_2_4/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 10.125 + 6.140 - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13408 + u_ov5640/coms1_reg_config/_N16270 @@ -69278,23 +70395,23 @@ - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_2/CIN (GTP_LUT5CARRY) + u_ov5640/coms1_reg_config/N11_2_5/CIN (GTP_LUT5CARRY) td 0.030 - 10.155 + 6.170 r - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_2/COUT (GTP_LUT5CARRY) + u_ov5640/coms1_reg_config/N11_2_5/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 10.155 + 6.170 - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13409 + u_ov5640/coms1_reg_config/_N16271 @@ -69302,119 +70419,349 @@ - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_3/CIN (GTP_LUT5CARRY) + u_ov5640/coms1_reg_config/N11_2_6/CIN (GTP_LUT5CARRY) td 0.030 - 10.185 + 6.200 r - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_3/COUT (GTP_LUT5CARRY) + u_ov5640/coms1_reg_config/N11_2_6/COUT (GTP_LUT5CARRY) net (fanout=1) 0.000 - 10.185 + 6.200 - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13410 + u_ov5640/coms1_reg_config/_N16272 + + + + + + + + u_ov5640/coms1_reg_config/N11_2_7/CIN (GTP_LUT5CARRY) + + + + td + 0.030 + 6.230 + r + u_ov5640/coms1_reg_config/N11_2_7/COUT (GTP_LUT5CARRY) + + + + net (fanout=1) + 0.000 + 6.230 + + u_ov5640/coms1_reg_config/_N16273 + + + + + + + + u_ov5640/coms1_reg_config/N11_2_8/CIN (GTP_LUT5CARRY) + + + + td + 0.030 + 6.260 + r + u_ov5640/coms1_reg_config/N11_2_8/COUT (GTP_LUT5CARRY) + + + + net (fanout=1) + 0.000 + 6.260 + + u_ov5640/coms1_reg_config/_N16274 + + + + + + + + u_ov5640/coms1_reg_config/N11_2_9/CIN (GTP_LUT5CARRY) + + + + td + 0.236 + 6.496 + r + u_ov5640/coms1_reg_config/N11_2_9/Z (GTP_LUT5CARRY) + + + + net (fanout=1) + 0.000 + 6.496 + + u_ov5640/coms1_reg_config/N1114 [9] + + + + + + + r + u_ov5640/coms1_reg_config/clock_20k_cnt[9]/D (GTP_DFF_R) + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_25m (rising edge) + + 40.000 + 40.000 + r + + + + clk + + 0.000 + 40.000 + r + clk (port) + + + + net (fanout=1) + 0.000 + 40.000 + + clk + + + + + + + + clk_ibuf/I (GTP_INBUF) + + + + td + 1.211 + 41.211 + r + clk_ibuf/O (GTP_INBUF) + + + + net (fanout=1) + 1.091 + 42.302 + + nt_clk + + + + + + + + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.098 + 42.400 + r + u_sys_pll/u_pll_e3/CLKOUT3 (GTP_PLL_E3) + + + + net (fanout=26) + 0.713 + 43.113 + + clk_25m + + + + + + + r + u_ov5640/coms1_reg_config/clock_20k_cnt[9]/CLK (GTP_DFF_R) + + + clock pessimism + + 0.000 + 43.113 + + + + + clock uncertainty + + -0.150 + 42.963 + + - + Setup time + + 0.034 + 42.997 + +
+
+
+
+ + 93.453 + 6 + 15 + ms72xx_ctl/ms7200_ctl/dri_cnt[4]/CLK + ms72xx_ctl/ms7200_ctl/freq_rec_2d[16]/CE + + clk_10m + clk_10m + rise-rise + 0.000 + 3.510 + 3.510 + 0.000 + 100.000 + 5.855 + 1.484 (25.3%) + 4.371 (74.7%) + + Path #37: setup slack is 93.453(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_10m (rising edge) + 0.000 + 0.000 + r - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_4/CIN (GTP_LUT5CARRY) - - td - 0.030 - 10.215 + clk + + 0.000 + 0.000 r - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_4/COUT (GTP_LUT5CARRY) + clk (port) net (fanout=1) 0.000 - 10.215 - - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13411 + 0.000 + + clk - + - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_5/CIN (GTP_LUT5CARRY) + clk_ibuf/I (GTP_INBUF) - + td - 0.030 - 10.245 + 1.211 + 1.211 r - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_5/COUT (GTP_LUT5CARRY) + clk_ibuf/O (GTP_INBUF) net (fanout=1) - 0.000 - 10.245 - - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13412 + 1.091 + 2.302 + + nt_clk - + - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_6/CIN (GTP_LUT5CARRY) + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) - + td - 0.030 - 10.275 + 0.094 + 2.396 r - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_6/COUT (GTP_LUT5CARRY) + u_sys_pll/u_pll_e3/CLKOUT4 (GTP_PLL_E3) - net (fanout=1) - 0.000 - 10.275 - - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13413 + net (fanout=256) + 1.114 + 3.510 + + clk_10m - - + - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_7/CIN (GTP_LUT5CARRY) + r + ms72xx_ctl/ms7200_ctl/dri_cnt[4]/CLK (GTP_DFF_RE) - td - 0.030 - 10.305 + tco + 0.329 + 3.839 r - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_7/COUT (GTP_LUT5CARRY) + ms72xx_ctl/ms7200_ctl/dri_cnt[4]/Q (GTP_DFF_RE) - net (fanout=1) - 0.000 - 10.305 + net (fanout=3) + 0.605 + 4.444 - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13414 + ms72xx_ctl/ms7200_ctl/dri_cnt [4] @@ -69422,23 +70769,23 @@ - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_8/CIN (GTP_LUT5CARRY) + ms72xx_ctl/ms7200_ctl/N8_3/I0 (GTP_LUT3) td - 0.030 - 10.335 - r - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_8/COUT (GTP_LUT5CARRY) + 0.243 + 4.687 + f + ms72xx_ctl/ms7200_ctl/N8_3/Z (GTP_LUT3) net (fanout=1) - 0.000 - 10.335 + 0.464 + 5.151 - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/_N13415 + ms72xx_ctl/ms7200_ctl/_N96627 @@ -69446,23 +70793,23 @@ - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_9/CIN (GTP_LUT5CARRY) + ms72xx_ctl/ms7200_ctl/N1872_5/I3 (GTP_LUT4) td - 0.236 - 10.571 + 0.185 + 5.336 r - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11_9/Z (GTP_LUT5CARRY) + ms72xx_ctl/ms7200_ctl/N1872_5/Z (GTP_LUT4) - net (fanout=2) - 0.553 - 11.124 + net (fanout=6) + 0.693 + 6.029 - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N11 [8] + ms72xx_ctl/ms7200_ctl/_N96632 @@ -69470,23 +70817,23 @@ - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[8]/I2 (GTP_LUT3) + ms72xx_ctl/ms7200_ctl/N2053_1/I1 (GTP_LUT2) td 0.185 - 11.309 + 6.214 r - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N12[8]/Z (GTP_LUT3) + ms72xx_ctl/ms7200_ctl/N2053_1/Z (GTP_LUT2) - net (fanout=2) - 0.553 - 11.862 + net (fanout=15) + 0.810 + 7.024 - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/rrptr [8] + ms72xx_ctl/ms7200_ctl/N261 @@ -69494,23 +70841,23 @@ - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N21.eq_4/I1 (GTP_LUT5CARRY) + ms72xx_ctl/ms7200_ctl/N40_9/I0 (GTP_LUT5) td - 0.363 - 12.225 - f - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N21.eq_4/COUT (GTP_LUT5CARRY) + 0.185 + 7.209 + r + ms72xx_ctl/ms7200_ctl/N40_9/Z (GTP_LUT5) - net (fanout=1) - 0.000 - 12.225 + net (fanout=4) + 0.641 + 7.850 - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N21.co [8] + ms72xx_ctl/ms7200_ctl/N2093 [4] @@ -69518,23 +70865,23 @@ - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N21.eq_5/CIN (GTP_LUT5CARRY) + ms72xx_ctl/ms7200_ctl/state_fsm[6:0]_2/I0 (GTP_LUT3) td - 0.236 - 12.461 + 0.185 + 8.035 r - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N21.eq_5/Z (GTP_LUT5CARRY) + ms72xx_ctl/ms7200_ctl/state_fsm[6:0]_2/Z (GTP_LUT3) - net (fanout=1) - 0.464 - 12.925 + net (fanout=3) + 0.605 + 8.640 - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N21 + ms72xx_ctl/ms7200_ctl/state_n [1] @@ -69542,36 +70889,36 @@ - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N22/I4 (GTP_LUT5) + ms72xx_ctl/ms7200_ctl/N8_7/I3 (GTP_LUT5) td - 0.185 - 13.110 - r - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N22/Z (GTP_LUT5) + 0.172 + 8.812 + f + ms72xx_ctl/ms7200_ctl/N8_7/Z (GTP_LUT5) - net (fanout=1) - 0.000 - 13.110 + net (fanout=3) + 0.553 + 9.365 - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/N22 + ms72xx_ctl/ms7200_ctl/N8 - r - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/D (GTP_DFF_C) + f + ms72xx_ctl/ms7200_ctl/freq_rec_2d[16]/CE (GTP_DFF_E)
- +
Location Delay Type @@ -69581,10 +70928,10 @@ Logical Resource - Clock clk_50m (rising edge) + Clock clk_10m (rising edge) - 20.000 - 20.000 + 100.000 + 100.000 r @@ -69592,7 +70939,7 @@ clk0.000 - 20.000 + 100.000rclk (port) @@ -69600,7 +70947,7 @@ net (fanout=1) 0.000 - 20.000 + 100.000 clk @@ -69616,7 +70963,7 @@ td 1.211 - 21.211 + 101.211 r clk_ibuf/O (GTP_INBUF) @@ -69624,7 +70971,7 @@ net (fanout=1) 1.091 - 22.302 + 102.302 nt_clk @@ -69640,17 +70987,17 @@ td 0.094 - 22.396 + 102.396 r - u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT4 (GTP_PLL_E3) - net (fanout=2827) - 3.130 - 25.526 + net (fanout=256) + 1.114 + 103.510 - rd3_clk + clk_10m @@ -69658,13 +71005,13 @@ r - image_filiter_inst2/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/CLK (GTP_DFF_C) + ms72xx_ctl/ms7200_ctl/freq_rec_2d[16]/CLK (GTP_DFF_E) clock pessimism 0.000 - 25.526 + 103.510 @@ -69672,15 +71019,15 @@ clock uncertainty -0.150 - 25.376 + 103.360 Setup time - 0.034 - 25.410 + -0.542 + 102.818 @@ -69689,27 +71036,27 @@ - 12.438 - 7 + 93.453 6 - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/CLKB - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/D + 15 + ms72xx_ctl/ms7200_ctl/dri_cnt[4]/CLK + ms72xx_ctl/ms7200_ctl/freq_rec_2d[17]/CE - clk_50m - clk_50m + clk_10m + clk_10m rise-rise - -0.514 - 6.040 - 5.526 0.000 - 20.000 - 6.932 - 3.589 (51.8%) - 3.343 (48.2%) + 3.510 + 3.510 + 0.000 + 100.000 + 5.855 + 1.484 (25.3%) + 4.371 (74.7%) - Path #30: setup slack is 12.438(MET) + Path #38: setup slack is 93.453(MET) -
+
Location Delay Type @@ -69719,7 +71066,7 @@ Logical Resource - Clock clk_50m (rising edge) + Clock clk_10m (rising edge) 0.000 0.000 @@ -69780,15 +71127,15 @@ 0.094 2.396 r - u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT4 (GTP_PLL_E3) - net (fanout=2827) - 3.644 - 6.040 + net (fanout=256) + 1.114 + 3.510 - rd3_clk + clk_10m @@ -69796,23 +71143,71 @@ r - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/CLKB (GTP_DRM9K) + ms72xx_ctl/ms7200_ctl/dri_cnt[4]/CLK (GTP_DFF_RE) tco - 2.024 - 8.064 + 0.329 + 3.839 + r + ms72xx_ctl/ms7200_ctl/dri_cnt[4]/Q (GTP_DFF_RE) + + + + net (fanout=3) + 0.605 + 4.444 + + ms72xx_ctl/ms7200_ctl/dri_cnt [4] + + + + + + + + ms72xx_ctl/ms7200_ctl/N8_3/I0 (GTP_LUT3) + + + + td + 0.243 + 4.687 f - u_rotate_image/u_store_addr/U_ipml_fifo_store_addr/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/DOB[0] (GTP_DRM9K) + ms72xx_ctl/ms7200_ctl/N8_3/Z (GTP_LUT3) + + + + net (fanout=1) + 0.464 + 5.151 + + ms72xx_ctl/ms7200_ctl/_N96627 + + + + + + + + ms72xx_ctl/ms7200_ctl/N1872_5/I3 (GTP_LUT4) + + + + td + 0.185 + 5.336 + r + ms72xx_ctl/ms7200_ctl/N1872_5/Z (GTP_LUT4) net (fanout=6) - 1.132 - 9.196 + 0.693 + 6.029 - u_rotate_image/dout [0] + ms72xx_ctl/ms7200_ctl/_N96632 @@ -69820,23 +71215,47 @@ - u_rotate_image/N170_5/I2 (GTP_LUT4) + ms72xx_ctl/ms7200_ctl/N2053_1/I1 (GTP_LUT2) td 0.185 - 9.381 + 6.214 r - u_rotate_image/N170_5/Z (GTP_LUT4) + ms72xx_ctl/ms7200_ctl/N2053_1/Z (GTP_LUT2) + + + + net (fanout=15) + 0.810 + 7.024 + + ms72xx_ctl/ms7200_ctl/N261 + + + + + + + + ms72xx_ctl/ms7200_ctl/N40_9/I0 (GTP_LUT5) + + + + td + 0.185 + 7.209 + r + ms72xx_ctl/ms7200_ctl/N40_9/Z (GTP_LUT5) net (fanout=4) 0.641 - 10.022 + 7.850 - u_rotate_image/N170 + ms72xx_ctl/ms7200_ctl/N2093 [4] @@ -69844,119 +71263,301 @@ - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_1/I0 (GTP_LUT5CARRY) + ms72xx_ctl/ms7200_ctl/state_fsm[6:0]_2/I0 (GTP_LUT3) td - 0.201 - 10.223 + 0.185 + 8.035 + r + ms72xx_ctl/ms7200_ctl/state_fsm[6:0]_2/Z (GTP_LUT3) + + + + net (fanout=3) + 0.605 + 8.640 + + ms72xx_ctl/ms7200_ctl/state_n [1] + + + + + + + + ms72xx_ctl/ms7200_ctl/N8_7/I3 (GTP_LUT5) + + + + td + 0.172 + 8.812 f - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_1/COUT (GTP_LUT5CARRY) + ms72xx_ctl/ms7200_ctl/N8_7/Z (GTP_LUT5) - net (fanout=1) - 0.000 - 10.223 + net (fanout=3) + 0.553 + 9.365 - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16661 + ms72xx_ctl/ms7200_ctl/N8 + f + ms72xx_ctl/ms7200_ctl/freq_rec_2d[17]/CE (GTP_DFF_E) + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_10m (rising edge) + + 100.000 + 100.000 + r + + + + clk + + 0.000 + 100.000 + r + clk (port) + + + + net (fanout=1) + 0.000 + 100.000 + + clk + + + + + + + + clk_ibuf/I (GTP_INBUF) + + + + td + 1.211 + 101.211 + r + clk_ibuf/O (GTP_INBUF) + + + + net (fanout=1) + 1.091 + 102.302 + + nt_clk + + + + + + + + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.094 + 102.396 + r + u_sys_pll/u_pll_e3/CLKOUT4 (GTP_PLL_E3) + + + + net (fanout=256) + 1.114 + 103.510 + + clk_10m + + + + + + + r + ms72xx_ctl/ms7200_ctl/freq_rec_2d[17]/CLK (GTP_DFF_E) + + + clock pessimism + + 0.000 + 103.510 + + + + + clock uncertainty + + -0.150 + 103.360 + + + + + Setup time + + -0.542 + 102.818 + + + +
+
+
+
+ + 93.758 + 7 + 15 + ms72xx_ctl/ms7200_ctl/dri_cnt[4]/CLK + ms72xx_ctl/ms7200_ctl/freq_ensure/D + + clk_10m + clk_10m + rise-rise + 0.000 + 3.510 + 3.510 + 0.000 + 100.000 + 6.126 + 1.755 (28.6%) + 4.371 (71.4%) + + Path #39: setup slack is 93.758(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_10m (rising edge) + + 0.000 + 0.000 + r - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_2/CIN (GTP_LUT5CARRY) - - td - 0.030 - 10.253 + clk + + 0.000 + 0.000 r - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_2/COUT (GTP_LUT5CARRY) + clk (port) net (fanout=1) 0.000 - 10.253 - - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16662 + 0.000 + + clk - + - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_3/CIN (GTP_LUT5CARRY) + clk_ibuf/I (GTP_INBUF) - + td - 0.030 - 10.283 + 1.211 + 1.211 r - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_3/COUT (GTP_LUT5CARRY) + clk_ibuf/O (GTP_INBUF) net (fanout=1) - 0.000 - 10.283 - - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16663 + 1.091 + 2.302 + + nt_clk - + - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_4/CIN (GTP_LUT5CARRY) + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) - + td - 0.030 - 10.313 + 0.094 + 2.396 r - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_4/COUT (GTP_LUT5CARRY) + u_sys_pll/u_pll_e3/CLKOUT4 (GTP_PLL_E3) - net (fanout=1) - 0.000 - 10.313 - - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16664 + net (fanout=256) + 1.114 + 3.510 + + clk_10m - - + - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_5/CIN (GTP_LUT5CARRY) + r + ms72xx_ctl/ms7200_ctl/dri_cnt[4]/CLK (GTP_DFF_RE) - td - 0.030 - 10.343 + tco + 0.329 + 3.839 r - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_5/COUT (GTP_LUT5CARRY) + ms72xx_ctl/ms7200_ctl/dri_cnt[4]/Q (GTP_DFF_RE) - net (fanout=1) - 0.000 - 10.343 + net (fanout=3) + 0.605 + 4.444 - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16665 + ms72xx_ctl/ms7200_ctl/dri_cnt [4] @@ -69964,23 +71565,23 @@ - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_6/CIN (GTP_LUT5CARRY) + ms72xx_ctl/ms7200_ctl/N8_3/I0 (GTP_LUT3) td - 0.030 - 10.373 - r - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_6/COUT (GTP_LUT5CARRY) + 0.243 + 4.687 + f + ms72xx_ctl/ms7200_ctl/N8_3/Z (GTP_LUT3) net (fanout=1) - 0.000 - 10.373 + 0.464 + 5.151 - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16666 + ms72xx_ctl/ms7200_ctl/_N96627 @@ -69988,23 +71589,23 @@ - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_7/CIN (GTP_LUT5CARRY) + ms72xx_ctl/ms7200_ctl/N1872_5/I3 (GTP_LUT4) td - 0.030 - 10.403 + 0.185 + 5.336 r - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_7/COUT (GTP_LUT5CARRY) + ms72xx_ctl/ms7200_ctl/N1872_5/Z (GTP_LUT4) - net (fanout=1) - 0.000 - 10.403 + net (fanout=6) + 0.693 + 6.029 - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16667 + ms72xx_ctl/ms7200_ctl/_N96632 @@ -70012,23 +71613,23 @@ - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_8/CIN (GTP_LUT5CARRY) + ms72xx_ctl/ms7200_ctl/N2053_1/I1 (GTP_LUT2) td - 0.030 - 10.433 + 0.185 + 6.214 r - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_8/COUT (GTP_LUT5CARRY) + ms72xx_ctl/ms7200_ctl/N2053_1/Z (GTP_LUT2) - net (fanout=1) - 0.000 - 10.433 + net (fanout=15) + 0.810 + 7.024 - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/_N16668 + ms72xx_ctl/ms7200_ctl/N261 @@ -70036,23 +71637,23 @@ - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_9/CIN (GTP_LUT5CARRY) + ms72xx_ctl/ms7200_ctl/N40_9/I0 (GTP_LUT5) td - 0.236 - 10.669 + 0.185 + 7.209 r - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11_9/Z (GTP_LUT5CARRY) + ms72xx_ctl/ms7200_ctl/N40_9/Z (GTP_LUT5) - net (fanout=2) - 0.553 - 11.222 + net (fanout=4) + 0.641 + 7.850 - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N11 [8] + ms72xx_ctl/ms7200_ctl/N2093 [4] @@ -70060,23 +71661,23 @@ - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[8]/I2 (GTP_LUT3) + ms72xx_ctl/ms7200_ctl/state_fsm[6:0]_2/I0 (GTP_LUT3) td 0.185 - 11.407 + 8.035 r - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N12[8]/Z (GTP_LUT3) + ms72xx_ctl/ms7200_ctl/state_fsm[6:0]_2/Z (GTP_LUT3) - net (fanout=1) - 0.464 - 11.871 + net (fanout=3) + 0.605 + 8.640 - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/rrptr [8] + ms72xx_ctl/ms7200_ctl/state_n [1] @@ -70084,23 +71685,23 @@ - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N24.eq_4/I1 (GTP_LUT5CARRY) + ms72xx_ctl/ms7200_ctl/N8_7/I3 (GTP_LUT5) td - 0.363 - 12.234 - f - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N24.eq_4/COUT (GTP_LUT5CARRY) + 0.185 + 8.825 + r + ms72xx_ctl/ms7200_ctl/N8_7/Z (GTP_LUT5) - net (fanout=2) + net (fanout=3) 0.553 - 12.787 + 9.378 - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N21 + ms72xx_ctl/ms7200_ctl/N8 @@ -70108,36 +71709,36 @@ - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N22/I1 (GTP_LUT5) + ms72xx_ctl/ms7200_ctl/freq_ensure_rs_mux/I0 (GTP_LUT4) td - 0.185 - 12.972 - r - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N22/Z (GTP_LUT5) + 0.258 + 9.636 + f + ms72xx_ctl/ms7200_ctl/freq_ensure_rs_mux/Z (GTP_LUT4) net (fanout=1) 0.000 - 12.972 + 9.636 - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/N22 + ms72xx_ctl/ms7200_ctl/_N104304 - r - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/D (GTP_DFF_C) + f + ms72xx_ctl/ms7200_ctl/freq_ensure/D (GTP_DFF)
- +
Location Delay Type @@ -70147,10 +71748,10 @@ Logical Resource - Clock clk_50m (rising edge) + Clock clk_10m (rising edge) - 20.000 - 20.000 + 100.000 + 100.000 r @@ -70158,7 +71759,7 @@ clk0.000 - 20.000 + 100.000rclk (port) @@ -70166,7 +71767,7 @@ net (fanout=1) 0.000 - 20.000 + 100.000 clk @@ -70182,7 +71783,7 @@ td 1.211 - 21.211 + 101.211 r clk_ibuf/O (GTP_INBUF) @@ -70190,7 +71791,7 @@ net (fanout=1) 1.091 - 22.302 + 102.302 nt_clk @@ -70206,17 +71807,17 @@ td 0.094 - 22.396 + 102.396 r - u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT4 (GTP_PLL_E3) - net (fanout=2827) - 3.130 - 25.526 + net (fanout=256) + 1.114 + 103.510 - rd3_clk + clk_10m @@ -70224,13 +71825,13 @@ r - u_rotate_image/u_store_image_data/U_ipml_fifo_store_image_data/U_ipml_fifo_ctrl/SYN_CTRL.syn_wfull/CLK (GTP_DFF_C) + ms72xx_ctl/ms7200_ctl/freq_ensure/CLK (GTP_DFF) clock pessimism 0.000 - 25.526 + 103.510 @@ -70238,7 +71839,7 @@ clock uncertainty -0.150 - 25.376 + 103.360 @@ -70246,7 +71847,7 @@ Setup time 0.034 - 25.410 + 103.394 @@ -70255,27 +71856,27 @@ - 36.471 - 5 - 12 - u_ov5640/coms1_reg_config/clock_20k_cnt[0]/CLK - u_ov5640/coms1_reg_config/clock_20k_cnt[10]/D + 49994.585 + 4 + 1 + u_ov5640/coms1_reg_config/reg_data/CLKB + u_ov5640/coms1_reg_config/u1/reg_sdat/D - clk_25m - clk_25m + clk_20k + clk_20k rise-rise 0.000 - 3.113 - 3.113 + 6.243 + 6.243 0.000 - 40.000 - 3.413 - 1.526 (44.7%) - 1.887 (55.3%) + 50000.000 + 5.399 + 3.104 (57.5%) + 2.295 (42.5%) - Path #31: setup slack is 36.471(MET) + Path #40: setup slack is 49994.585(MET) -
+
Location Delay Type @@ -70285,7 +71886,7 @@ Logical Resource - Clock clk_25m (rising edge) + Clock clk_20k (rising edge) 0.000 0.000 @@ -70362,215 +71963,71 @@ r - u_ov5640/coms1_reg_config/clock_20k_cnt[0]/CLK (GTP_DFF_R) + u_ov5640/coms1_reg_config/clk_20k_regdiv/CLK (GTP_DFF_RE) - + tco 0.329 3.442 r - u_ov5640/coms1_reg_config/clock_20k_cnt[0]/Q (GTP_DFF_R) - - - - net (fanout=4) - 0.641 - 4.083 - - u_ov5640/coms1_reg_config/clock_20k_cnt [0] - - - - - - - - u_ov5640/coms1_reg_config/N8_mux4_5/I0 (GTP_LUT5) - - - - td - 0.303 - 4.386 - f - u_ov5640/coms1_reg_config/N8_mux4_5/Z (GTP_LUT5) - - - - net (fanout=1) - 0.464 - 4.850 - - u_ov5640/coms1_reg_config/_N9664 - - - - - - - - u_ov5640/coms1_reg_config/N8_mux10/I0 (GTP_LUT5) - - - - td - 0.185 - 5.035 - r - u_ov5640/coms1_reg_config/N8_mux10/Z (GTP_LUT5) - - - - net (fanout=12) - 0.782 - 5.817 - - u_ov5640/coms1_reg_config/N8 + u_ov5640/coms1_reg_config/clk_20k_regdiv/Q (GTP_DFF_RE) - + net (fanout=3) + 0.605 + 4.047 - - - u_ov5640/coms1_reg_config/N11_2_1/I2 (GTP_LUT5CARRY) - - - - td - 0.233 - 6.050 - f - u_ov5640/coms1_reg_config/N11_2_1/COUT (GTP_LUT5CARRY) - - - - net (fanout=1) - 0.000 - 6.050 - - u_ov5640/coms1_reg_config/_N16245 + u_ov5640/coms1_reg_config/clk_20k_regdiv - + - u_ov5640/coms1_reg_config/N11_2_2/CIN (GTP_LUT5CARRY) + u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/CLKIN (GTP_CLKBUFG) - + td - 0.030 - 6.080 - r - u_ov5640/coms1_reg_config/N11_2_2/COUT (GTP_LUT5CARRY) - - - - net (fanout=1) 0.000 - 6.080 - - u_ov5640/coms1_reg_config/_N16246 - - - - - - - - u_ov5640/coms1_reg_config/N11_2_3/CIN (GTP_LUT5CARRY) - - - - td - 0.030 - 6.110 + 4.047 r - u_ov5640/coms1_reg_config/N11_2_3/COUT (GTP_LUT5CARRY) - - - - net (fanout=1) - 0.000 - 6.110 - - u_ov5640/coms1_reg_config/_N16247 + u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/CLKOUT (GTP_CLKBUFG) - - + net (fanout=25) + 2.196 + 6.243 - - u_ov5640/coms1_reg_config/N11_2_4/CIN (GTP_LUT5CARRY) - - - - td - 0.030 - 6.140 - r - u_ov5640/coms1_reg_config/N11_2_4/COUT (GTP_LUT5CARRY) - - - - net (fanout=1) - 0.000 - 6.140 - - u_ov5640/coms1_reg_config/_N16248 + u_ov5640/coms1_reg_config/clock_20k - - + - u_ov5640/coms1_reg_config/N11_2_5/CIN (GTP_LUT5CARRY) - - - - td - 0.030 - 6.170 r - u_ov5640/coms1_reg_config/N11_2_5/COUT (GTP_LUT5CARRY) - - - - net (fanout=1) - 0.000 - 6.170 - - u_ov5640/coms1_reg_config/_N16249 - - - - - - - - u_ov5640/coms1_reg_config/N11_2_6/CIN (GTP_LUT5CARRY) + u_ov5640/coms1_reg_config/reg_data/CLKB (GTP_DRM18K) - td - 0.030 - 6.200 - r - u_ov5640/coms1_reg_config/N11_2_6/COUT (GTP_LUT5CARRY) + tco + 2.024 + 8.267 + f + u_ov5640/coms1_reg_config/reg_data/DOB[7] (GTP_DRM18K) net (fanout=1) - 0.000 - 6.200 + 0.903 + 9.170 - u_ov5640/coms1_reg_config/_N16250 + u_ov5640/coms1_reg_config/i2c_data [23] @@ -70578,23 +72035,23 @@ - u_ov5640/coms1_reg_config/N11_2_7/CIN (GTP_LUT5CARRY) + u_ov5640/coms1_reg_config/u1/N267_29/I1 (GTP_LUT5M) td - 0.030 - 6.230 - r - u_ov5640/coms1_reg_config/N11_2_7/COUT (GTP_LUT5CARRY) + 0.365 + 9.535 + f + u_ov5640/coms1_reg_config/u1/N267_29/Z (GTP_LUT5M) net (fanout=1) - 0.000 - 6.230 + 0.464 + 9.999 - u_ov5640/coms1_reg_config/_N16251 + u_ov5640/coms1_reg_config/u1/_N25311 @@ -70602,23 +72059,23 @@ - u_ov5640/coms1_reg_config/N11_2_8/CIN (GTP_LUT5CARRY) + u_ov5640/coms1_reg_config/u1/N267_35/I0 (GTP_LUT5) td - 0.030 - 6.260 + 0.185 + 10.184 r - u_ov5640/coms1_reg_config/N11_2_8/COUT (GTP_LUT5CARRY) + u_ov5640/coms1_reg_config/u1/N267_35/Z (GTP_LUT5) net (fanout=1) - 0.000 - 6.260 + 0.464 + 10.648 - u_ov5640/coms1_reg_config/_N16252 + u_ov5640/coms1_reg_config/u1/_N25317 @@ -70626,23 +72083,23 @@ - u_ov5640/coms1_reg_config/N11_2_9/CIN (GTP_LUT5CARRY) + u_ov5640/coms1_reg_config/u1/N267_36/ID (GTP_LUT5M) td - 0.030 - 6.290 - r - u_ov5640/coms1_reg_config/N11_2_9/COUT (GTP_LUT5CARRY) + 0.265 + 10.913 + f + u_ov5640/coms1_reg_config/u1/N267_36/Z (GTP_LUT5M) net (fanout=1) - 0.000 - 6.290 + 0.464 + 11.377 - u_ov5640/coms1_reg_config/_N16253 + u_ov5640/coms1_reg_config/u1/_N25318 @@ -70650,36 +72107,36 @@ - u_ov5640/coms1_reg_config/N11_2_10/CIN (GTP_LUT5CARRY) + u_ov5640/coms1_reg_config/u1/reg_sdat_ce_mux/ID (GTP_LUT5M) td - 0.236 - 6.526 - r - u_ov5640/coms1_reg_config/N11_2_10/Z (GTP_LUT5CARRY) + 0.265 + 11.642 + f + u_ov5640/coms1_reg_config/u1/reg_sdat_ce_mux/Z (GTP_LUT5M) net (fanout=1) 0.000 - 6.526 + 11.642 - u_ov5640/coms1_reg_config/N1114 [10] + u_ov5640/coms1_reg_config/u1/_N104288 - r - u_ov5640/coms1_reg_config/clock_20k_cnt[10]/D (GTP_DFF_R) + f + u_ov5640/coms1_reg_config/u1/reg_sdat/D (GTP_DFF_S)
- +
Location Delay Type @@ -70689,10 +72146,10 @@ Logical Resource - Clock clk_25m (rising edge) + Clock clk_20k (rising edge) - 40.000 - 40.000 + 50000.000 + 50000.000 r @@ -70700,7 +72157,7 @@ clk0.000 - 40.000 + 50000.000rclk (port) @@ -70708,7 +72165,7 @@ net (fanout=1) 0.000 - 40.000 + 50000.000 clk @@ -70724,7 +72181,7 @@ td 1.211 - 41.211 + 50001.211 r clk_ibuf/O (GTP_INBUF) @@ -70732,7 +72189,7 @@ net (fanout=1) 1.091 - 42.302 + 50002.302 nt_clk @@ -70748,7 +72205,7 @@ td 0.098 - 42.400 + 50002.400 r u_sys_pll/u_pll_e3/CLKOUT3 (GTP_PLL_E3) @@ -70756,7 +72213,7 @@ net (fanout=26) 0.713 - 43.113 + 50003.113 clk_25m @@ -70766,21 +72223,69 @@ r - u_ov5640/coms1_reg_config/clock_20k_cnt[10]/CLK (GTP_DFF_R) + u_ov5640/coms1_reg_config/clk_20k_regdiv/CLK (GTP_DFF_RE) + + + + tco + 0.329 + 50003.442 + r + u_ov5640/coms1_reg_config/clk_20k_regdiv/Q (GTP_DFF_RE) + + + + net (fanout=3) + 0.605 + 50004.047 + + u_ov5640/coms1_reg_config/clk_20k_regdiv + + + + + + + + u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/CLKIN (GTP_CLKBUFG) + + + + td + 0.000 + 50004.047 + r + u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/CLKOUT (GTP_CLKBUFG) + + + + net (fanout=25) + 2.196 + 50006.243 + + u_ov5640/coms1_reg_config/clock_20k + + + + + + + r + u_ov5640/coms1_reg_config/u1/reg_sdat/CLK (GTP_DFF_S) clock pessimism 0.000 - 43.113 + 50006.243 clock uncertainty - -0.150 - 42.963 + -0.050 + 50006.193 @@ -70788,7 +72293,7 @@ Setup time 0.034 - 42.997 + 50006.227 @@ -70797,27 +72302,27 @@ - 36.471 + 49994.665 5 - 12 - u_ov5640/coms2_reg_config/clock_20k_cnt[0]/CLK - u_ov5640/coms2_reg_config/clock_20k_cnt[10]/D + 1 + u_ov5640/coms2_reg_config/reg_data/CLKB + u_ov5640/coms2_reg_config/u1/reg_sdat/D - clk_25m - clk_25m + clk_20k + clk_20k rise-rise 0.000 - 3.113 - 3.113 + 6.243 + 6.243 0.000 - 40.000 - 3.413 - 1.526 (44.7%) - 1.887 (55.3%) + 50000.000 + 5.319 + 3.024 (56.9%) + 2.295 (43.1%) - Path #32: setup slack is 36.471(MET) + Path #41: setup slack is 49994.665(MET) -
+
Location Delay Type @@ -70827,7 +72332,7 @@ Logical Resource - Clock clk_25m (rising edge) + Clock clk_20k (rising edge) 0.000 0.000 @@ -70904,191 +72409,71 @@ r - u_ov5640/coms2_reg_config/clock_20k_cnt[0]/CLK (GTP_DFF_R) + u_ov5640/coms2_reg_config/clk_20k_regdiv/CLK (GTP_DFF_RE) - + tco 0.329 3.442 r - u_ov5640/coms2_reg_config/clock_20k_cnt[0]/Q (GTP_DFF_R) - - - - net (fanout=4) - 0.641 - 4.083 - - u_ov5640/coms2_reg_config/clock_20k_cnt [0] - - - - - - - - u_ov5640/coms2_reg_config/N8_mux4_5/I4 (GTP_LUT5) - - - - td - 0.303 - 4.386 - f - u_ov5640/coms2_reg_config/N8_mux4_5/Z (GTP_LUT5) - - - - net (fanout=1) - 0.464 - 4.850 - - u_ov5640/coms2_reg_config/_N9736 + u_ov5640/coms2_reg_config/clk_20k_regdiv/Q (GTP_DFF_RE) - - + net (fanout=3) + 0.605 + 4.047 - - u_ov5640/coms2_reg_config/N8_mux10/I0 (GTP_LUT5) - - - - td - 0.185 - 5.035 - r - u_ov5640/coms2_reg_config/N8_mux10/Z (GTP_LUT5) - - - - net (fanout=12) - 0.782 - 5.817 - - u_ov5640/coms2_reg_config/N8 + u_ov5640/coms2_reg_config/clk_20k_regdiv - + - u_ov5640/coms2_reg_config/N11_2_1/I2 (GTP_LUT5CARRY) + u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/CLKIN (GTP_CLKBUFG) - + td - 0.233 - 6.050 - f - u_ov5640/coms2_reg_config/N11_2_1/COUT (GTP_LUT5CARRY) - - - - net (fanout=1) 0.000 - 6.050 - - u_ov5640/coms2_reg_config/_N16398 - - - - - - - - u_ov5640/coms2_reg_config/N11_2_2/CIN (GTP_LUT5CARRY) - - - - td - 0.030 - 6.080 + 4.047 r - u_ov5640/coms2_reg_config/N11_2_2/COUT (GTP_LUT5CARRY) - - - - net (fanout=1) - 0.000 - 6.080 - - u_ov5640/coms2_reg_config/_N16399 + u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/CLKOUT (GTP_CLKBUFG) - - + net (fanout=25) + 2.196 + 6.243 - - u_ov5640/coms2_reg_config/N11_2_3/CIN (GTP_LUT5CARRY) - - - - td - 0.030 - 6.110 - r - u_ov5640/coms2_reg_config/N11_2_3/COUT (GTP_LUT5CARRY) - - - - net (fanout=1) - 0.000 - 6.110 - - u_ov5640/coms2_reg_config/_N16400 + u_ov5640/coms2_reg_config/clock_20k - - + - u_ov5640/coms2_reg_config/N11_2_4/CIN (GTP_LUT5CARRY) - - - - td - 0.030 - 6.140 r - u_ov5640/coms2_reg_config/N11_2_4/COUT (GTP_LUT5CARRY) - - - - net (fanout=1) - 0.000 - 6.140 - - u_ov5640/coms2_reg_config/_N16401 - - - - - - - - u_ov5640/coms2_reg_config/N11_2_5/CIN (GTP_LUT5CARRY) + u_ov5640/coms2_reg_config/reg_data/CLKB (GTP_DRM18K) - td - 0.030 - 6.170 - r - u_ov5640/coms2_reg_config/N11_2_5/COUT (GTP_LUT5CARRY) + tco + 2.024 + 8.267 + f + u_ov5640/coms2_reg_config/reg_data/DOB[4] (GTP_DRM18K) net (fanout=1) - 0.000 - 6.170 + 0.903 + 9.170 - u_ov5640/coms2_reg_config/_N16402 + u_ov5640/coms2_reg_config/i2c_data [20] @@ -71096,23 +72481,23 @@ - u_ov5640/coms2_reg_config/N11_2_6/CIN (GTP_LUT5CARRY) + u_ov5640/coms2_reg_config/u1/N267_29/I1 (GTP_LUT5M) td - 0.030 - 6.200 - r - u_ov5640/coms2_reg_config/N11_2_6/COUT (GTP_LUT5CARRY) + 0.365 + 9.535 + f + u_ov5640/coms2_reg_config/u1/N267_29/Z (GTP_LUT5M) net (fanout=1) - 0.000 - 6.200 + 0.464 + 9.999 - u_ov5640/coms2_reg_config/_N16403 + u_ov5640/coms2_reg_config/u1/_N25853 @@ -71120,23 +72505,23 @@ - u_ov5640/coms2_reg_config/N11_2_7/CIN (GTP_LUT5CARRY) + u_ov5640/coms2_reg_config/u1/N267_35/I0 (GTP_LUT5) td - 0.030 - 6.230 + 0.185 + 10.184 r - u_ov5640/coms2_reg_config/N11_2_7/COUT (GTP_LUT5CARRY) + u_ov5640/coms2_reg_config/u1/N267_35/Z (GTP_LUT5) net (fanout=1) - 0.000 - 6.230 + 0.464 + 10.648 - u_ov5640/coms2_reg_config/_N16404 + u_ov5640/coms2_reg_config/u1/_N25859 @@ -71144,23 +72529,23 @@ - u_ov5640/coms2_reg_config/N11_2_8/CIN (GTP_LUT5CARRY) + u_ov5640/coms2_reg_config/u1/N267_36/ID (GTP_LUT5M) td - 0.030 - 6.260 - r - u_ov5640/coms2_reg_config/N11_2_8/COUT (GTP_LUT5CARRY) + 0.265 + 10.913 + f + u_ov5640/coms2_reg_config/u1/N267_36/Z (GTP_LUT5M) net (fanout=1) 0.000 - 6.260 + 10.913 - u_ov5640/coms2_reg_config/_N16405 + u_ov5640/coms2_reg_config/u1/_N25860 @@ -71168,23 +72553,23 @@ - u_ov5640/coms2_reg_config/N11_2_9/CIN (GTP_LUT5CARRY) + u_ov5640/coms2_reg_config/u1/N267_37/I0 (GTP_MUX2LUT6) td - 0.030 - 6.290 - r - u_ov5640/coms2_reg_config/N11_2_9/COUT (GTP_LUT5CARRY) + 0.000 + 10.913 + f + u_ov5640/coms2_reg_config/u1/N267_37/Z (GTP_MUX2LUT6) net (fanout=1) - 0.000 - 6.290 + 0.464 + 11.377 - u_ov5640/coms2_reg_config/_N16406 + u_ov5640/coms2_reg_config/u1/N267 @@ -71192,23 +72577,23 @@ - u_ov5640/coms2_reg_config/N11_2_10/CIN (GTP_LUT5CARRY) + u_ov5640/coms2_reg_config/u1/reg_sdat_ce_mux/I2 (GTP_LUT5) td - 0.236 - 6.526 + 0.185 + 11.562 r - u_ov5640/coms2_reg_config/N11_2_10/Z (GTP_LUT5CARRY) + u_ov5640/coms2_reg_config/u1/reg_sdat_ce_mux/Z (GTP_LUT5) net (fanout=1) 0.000 - 6.526 + 11.562 - u_ov5640/coms2_reg_config/N1114 [10] + u_ov5640/coms2_reg_config/u1/_N104293 @@ -71216,12 +72601,12 @@ r - u_ov5640/coms2_reg_config/clock_20k_cnt[10]/D (GTP_DFF_R) + u_ov5640/coms2_reg_config/u1/reg_sdat/D (GTP_DFF_S)
- +
Location Delay Type @@ -71231,10 +72616,10 @@ Logical Resource - Clock clk_25m (rising edge) + Clock clk_20k (rising edge) - 40.000 - 40.000 + 50000.000 + 50000.000 r @@ -71242,7 +72627,7 @@ clk0.000 - 40.000 + 50000.000rclk (port) @@ -71250,7 +72635,7 @@ net (fanout=1) 0.000 - 40.000 + 50000.000 clk @@ -71266,7 +72651,7 @@ td 1.211 - 41.211 + 50001.211 r clk_ibuf/O (GTP_INBUF) @@ -71274,7 +72659,7 @@ net (fanout=1) 1.091 - 42.302 + 50002.302 nt_clk @@ -71290,7 +72675,7 @@ td 0.098 - 42.400 + 50002.400 r u_sys_pll/u_pll_e3/CLKOUT3 (GTP_PLL_E3) @@ -71298,7 +72683,7 @@ net (fanout=26) 0.713 - 43.113 + 50003.113 clk_25m @@ -71308,89 +72693,23 @@ r - u_ov5640/coms2_reg_config/clock_20k_cnt[10]/CLK (GTP_DFF_R) - - - clock pessimism - - 0.000 - 43.113 - - - - - clock uncertainty - - -0.150 - 42.963 - - - - - Setup time - - 0.034 - 42.997 - - - -
-
-
-
- - 36.501 - 5 - 12 - u_ov5640/coms1_reg_config/clock_20k_cnt[0]/CLK - u_ov5640/coms1_reg_config/clock_20k_cnt[9]/D - - clk_25m - clk_25m - rise-rise - 0.000 - 3.113 - 3.113 - 0.000 - 40.000 - 3.383 - 1.496 (44.2%) - 1.887 (55.8%) - - Path #33: setup slack is 36.501(MET) - - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_25m (rising edge) - - 0.000 - 0.000 - r - + u_ov5640/coms2_reg_config/clk_20k_regdiv/CLK (GTP_DFF_RE) - clk - 0.000 - 0.000 + tco + 0.329 + 50003.442 r - clk (port) + u_ov5640/coms2_reg_config/clk_20k_regdiv/Q (GTP_DFF_RE) - net (fanout=1) - 0.000 - 0.000 + net (fanout=3) + 0.605 + 50004.047 - clk + u_ov5640/coms2_reg_config/clk_20k_regdiv @@ -71398,239 +72717,233 @@ - clk_ibuf/I (GTP_INBUF) + u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/CLKIN (GTP_CLKBUFG) td - 1.211 - 1.211 + 0.000 + 50004.047 r - clk_ibuf/O (GTP_INBUF) + u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/CLKOUT (GTP_CLKBUFG) - net (fanout=1) - 1.091 - 2.302 + net (fanout=25) + 2.196 + 50006.243 - nt_clk + u_ov5640/coms2_reg_config/clock_20k - - u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) - - - - td - 0.098 - 2.400 r - u_sys_pll/u_pll_e3/CLKOUT3 (GTP_PLL_E3) + u_ov5640/coms2_reg_config/u1/reg_sdat/CLK (GTP_DFF_S) + clock pessimism + + 0.000 + 50006.243 - net (fanout=26) - 0.713 - 3.113 - clk_25m - + clock uncertainty + -0.050 + 50006.193 - r - u_ov5640/coms1_reg_config/clock_20k_cnt[0]/CLK (GTP_DFF_R) - - - - tco - 0.329 - 3.442 - r - u_ov5640/coms1_reg_config/clock_20k_cnt[0]/Q (GTP_DFF_R) + Setup time + + 0.034 + 50006.227 + - net (fanout=4) - 0.641 - 4.083 - - u_ov5640/coms1_reg_config/clock_20k_cnt [0] +
+
+
+
+ + 49995.326 + 4 + 6 + u_ov5640/coms1_reg_config/reg_index[0]/CLK + u_ov5640/coms1_reg_config/reg_data/CEA + + clk_20k + clk_20k + rise-rise + 0.000 + 6.243 + 6.243 + 0.000 + 50000.000 + 4.539 + 1.121 (24.7%) + 3.418 (75.3%) + + Path #42: setup slack is 49995.326(MET) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + - - - + Clock clk_20k (rising edge) + 0.000 + 0.000 + r - u_ov5640/coms1_reg_config/N8_mux4_5/I0 (GTP_LUT5) - - td - 0.303 - 4.386 - f - u_ov5640/coms1_reg_config/N8_mux4_5/Z (GTP_LUT5) + clk + + 0.000 + 0.000 + r + clk (port) net (fanout=1) - 0.464 - 4.850 - - u_ov5640/coms1_reg_config/_N9664 - - - - - - - - u_ov5640/coms1_reg_config/N8_mux10/I0 (GTP_LUT5) - - - - td - 0.185 - 5.035 - r - u_ov5640/coms1_reg_config/N8_mux10/Z (GTP_LUT5) - - + 0.000 + 0.000 - net (fanout=12) - 0.782 - 5.817 - - u_ov5640/coms1_reg_config/N8 + clk - + - u_ov5640/coms1_reg_config/N11_2_1/I2 (GTP_LUT5CARRY) + clk_ibuf/I (GTP_INBUF) - + td - 0.233 - 6.050 - f - u_ov5640/coms1_reg_config/N11_2_1/COUT (GTP_LUT5CARRY) + 1.211 + 1.211 + r + clk_ibuf/O (GTP_INBUF) net (fanout=1) - 0.000 - 6.050 - - u_ov5640/coms1_reg_config/_N16245 + 1.091 + 2.302 + + nt_clk - + - u_ov5640/coms1_reg_config/N11_2_2/CIN (GTP_LUT5CARRY) + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) - + td - 0.030 - 6.080 + 0.098 + 2.400 r - u_ov5640/coms1_reg_config/N11_2_2/COUT (GTP_LUT5CARRY) + u_sys_pll/u_pll_e3/CLKOUT3 (GTP_PLL_E3) - net (fanout=1) - 0.000 - 6.080 - - u_ov5640/coms1_reg_config/_N16246 + net (fanout=26) + 0.713 + 3.113 + + clk_25m - - + - u_ov5640/coms1_reg_config/N11_2_3/CIN (GTP_LUT5CARRY) + r + u_ov5640/coms1_reg_config/clk_20k_regdiv/CLK (GTP_DFF_RE) - - td - 0.030 - 6.110 + + tco + 0.329 + 3.442 r - u_ov5640/coms1_reg_config/N11_2_3/COUT (GTP_LUT5CARRY) + u_ov5640/coms1_reg_config/clk_20k_regdiv/Q (GTP_DFF_RE) - net (fanout=1) - 0.000 - 6.110 - - u_ov5640/coms1_reg_config/_N16247 + net (fanout=3) + 0.605 + 4.047 + + u_ov5640/coms1_reg_config/clk_20k_regdiv - + - u_ov5640/coms1_reg_config/N11_2_4/CIN (GTP_LUT5CARRY) + u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/CLKIN (GTP_CLKBUFG) - + td - 0.030 - 6.140 + 0.000 + 4.047 r - u_ov5640/coms1_reg_config/N11_2_4/COUT (GTP_LUT5CARRY) + u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/CLKOUT (GTP_CLKBUFG) - net (fanout=1) - 0.000 - 6.140 - - u_ov5640/coms1_reg_config/_N16248 + net (fanout=25) + 2.196 + 6.243 + + u_ov5640/coms1_reg_config/clock_20k - - + - u_ov5640/coms1_reg_config/N11_2_5/CIN (GTP_LUT5CARRY) + r + u_ov5640/coms1_reg_config/reg_index[0]/CLK (GTP_DFF_RE) - td - 0.030 - 6.170 + tco + 0.329 + 6.572 r - u_ov5640/coms1_reg_config/N11_2_5/COUT (GTP_LUT5CARRY) + u_ov5640/coms1_reg_config/reg_index[0]/Q (GTP_DFF_RE) - net (fanout=1) - 0.000 - 6.170 + net (fanout=6) + 0.693 + 7.265 - u_ov5640/coms1_reg_config/_N16249 + u_ov5640/coms1_reg_config/reg_index [0] @@ -71638,23 +72951,23 @@ - u_ov5640/coms1_reg_config/N11_2_6/CIN (GTP_LUT5CARRY) + u_ov5640/coms1_reg_config/N26_mux2/I0 (GTP_LUT3) td - 0.030 - 6.200 - r - u_ov5640/coms1_reg_config/N11_2_6/COUT (GTP_LUT5CARRY) + 0.237 + 7.502 + f + u_ov5640/coms1_reg_config/N26_mux2/Z (GTP_LUT3) net (fanout=1) - 0.000 - 6.200 + 0.464 + 7.966 - u_ov5640/coms1_reg_config/_N16250 + u_ov5640/coms1_reg_config/_N9695 @@ -71662,23 +72975,23 @@ - u_ov5640/coms1_reg_config/N11_2_7/CIN (GTP_LUT5CARRY) + u_ov5640/coms1_reg_config/N26_mux6_3/I0 (GTP_LUT5) td - 0.030 - 6.230 + 0.185 + 8.151 r - u_ov5640/coms1_reg_config/N11_2_7/COUT (GTP_LUT5CARRY) + u_ov5640/coms1_reg_config/N26_mux6_3/Z (GTP_LUT5) - net (fanout=1) - 0.000 - 6.230 + net (fanout=2) + 0.553 + 8.704 - u_ov5640/coms1_reg_config/_N16251 + u_ov5640/coms1_reg_config/_N9703 @@ -71686,23 +72999,23 @@ - u_ov5640/coms1_reg_config/N11_2_8/CIN (GTP_LUT5CARRY) + u_ov5640/coms1_reg_config/N1134_1/I0 (GTP_LUT4) td - 0.030 - 6.260 + 0.185 + 8.889 r - u_ov5640/coms1_reg_config/N11_2_8/COUT (GTP_LUT5CARRY) + u_ov5640/coms1_reg_config/N1134_1/Z (GTP_LUT4) - net (fanout=1) - 0.000 - 6.260 + net (fanout=4) + 0.641 + 9.530 - u_ov5640/coms1_reg_config/_N16252 + u_ov5640/coms1_reg_config/_N97285 @@ -71710,23 +73023,23 @@ - u_ov5640/coms1_reg_config/N11_2_9/CIN (GTP_LUT5CARRY) + u_ov5640/coms1_reg_config/N1193_3/I1 (GTP_LUT3) td - 0.236 - 6.496 + 0.185 + 9.715 r - u_ov5640/coms1_reg_config/N11_2_9/Z (GTP_LUT5CARRY) + u_ov5640/coms1_reg_config/N1193_3/Z (GTP_LUT3) - net (fanout=1) - 0.000 - 6.496 + net (fanout=2) + 1.067 + 10.782 - u_ov5640/coms1_reg_config/N1114 [9] + u_ov5640/coms1_reg_config/N1193 @@ -71734,12 +73047,12 @@ r - u_ov5640/coms1_reg_config/clock_20k_cnt[9]/D (GTP_DFF_R) + u_ov5640/coms1_reg_config/reg_data/CEA (GTP_DRM18K)
- +
Location Delay Type @@ -71749,10 +73062,10 @@ Logical Resource - Clock clk_25m (rising edge) + Clock clk_20k (rising edge) - 40.000 - 40.000 + 50000.000 + 50000.000 r @@ -71760,7 +73073,7 @@ clk0.000 - 40.000 + 50000.000rclk (port) @@ -71768,7 +73081,7 @@ net (fanout=1) 0.000 - 40.000 + 50000.000 clk @@ -71784,7 +73097,7 @@ td 1.211 - 41.211 + 50001.211 r clk_ibuf/O (GTP_INBUF) @@ -71792,7 +73105,7 @@ net (fanout=1) 1.091 - 42.302 + 50002.302 nt_clk @@ -71808,7 +73121,7 @@ td 0.098 - 42.400 + 50002.400 r u_sys_pll/u_pll_e3/CLKOUT3 (GTP_PLL_E3) @@ -71816,7 +73129,7 @@ net (fanout=26) 0.713 - 43.113 + 50003.113 clk_25m @@ -71826,29 +73139,77 @@ r - u_ov5640/coms1_reg_config/clock_20k_cnt[9]/CLK (GTP_DFF_R) + u_ov5640/coms1_reg_config/clk_20k_regdiv/CLK (GTP_DFF_RE) + + + + tco + 0.329 + 50003.442 + r + u_ov5640/coms1_reg_config/clk_20k_regdiv/Q (GTP_DFF_RE) + + + + net (fanout=3) + 0.605 + 50004.047 + + u_ov5640/coms1_reg_config/clk_20k_regdiv + + + + + + + + u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/CLKIN (GTP_CLKBUFG) + + + + td + 0.000 + 50004.047 + r + u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/CLKOUT (GTP_CLKBUFG) + + + + net (fanout=25) + 2.196 + 50006.243 + + u_ov5640/coms1_reg_config/clock_20k + + + + + + + r + u_ov5640/coms1_reg_config/reg_data/CLKA (GTP_DRM18K) clock pessimism 0.000 - 43.113 + 50006.243 clock uncertainty - -0.150 - 42.963 + -0.050 + 50006.193 Setup time - 0.034 - 42.997 + -0.085 + 50006.108 @@ -71856,28 +73217,49 @@ +
+ + + Slack + Logic Levels + High Fanout + Start Point + End Point + Exception + Launch Clock + Capture Clock + Clock Edges + Clock Skew + Launch Clock Delay + Capture Clock Delay + Clock Pessimism Removal + Requirement + Data delay + Logic delay + Route delay + - 93.453 - 6 - 15 - ms72xx_ctl/ms7200_ctl/dri_cnt[4]/CLK - ms72xx_ctl/ms7200_ctl/freq_rec_2d[16]/CE + -1.352 + 1 + 1 + cmos1_data[0] + u_ov5640/cmos1_d_d0[0]/D - clk_10m - clk_10m + cmos1_pclk + cmos1_pclk rise-rise + 4.415 0.000 - 3.510 - 3.510 + 4.415 0.000 - 100.000 - 5.855 - 1.484 (25.3%) - 4.371 (74.7%) + 0.000 + 2.302 + 1.211 (52.6%) + 1.091 (47.4%) - Path #34: setup slack is 93.453(MET) + Path #1: hold slack is -1.352(VIOLATED) -
+
Location Delay Type @@ -71887,7 +73269,7 @@ Logical Resource - Clock clk_10m (rising edge) + Clock cmos1_pclk (rising edge) 0.000 0.000 @@ -71895,212 +73277,218 @@ - clk - - 0.000 + Input external delay + + 1.000 + 1.000 + r + + + + cmos1_data[0] + 0.000 + 1.000 r - clk (port) + cmos1_data[0] (port) net (fanout=1) 0.000 - 0.000 - - clk + 1.000 + + cmos1_data[0] - + - clk_ibuf/I (GTP_INBUF) + cmos1_data_ibuf[0]/I (GTP_INBUF) - + td 1.211 - 1.211 + 2.211 r - clk_ibuf/O (GTP_INBUF) + cmos1_data_ibuf[0]/O (GTP_INBUF) net (fanout=1) 1.091 - 2.302 - - nt_clk + 3.302 + + nt_cmos1_data[0] - - + - u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) - - - - td - 0.094 - 2.396 r - u_sys_pll/u_pll_e3/CLKOUT4 (GTP_PLL_E3) + u_ov5640/cmos1_d_d0[0]/D (GTP_DFF) +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + Clock cmos1_pclk (rising edge) - net (fanout=256) - 1.114 - 3.510 + 0.000 + 0.000 + r - clk_10m + cmos1_pclk - - - - r - ms72xx_ctl/ms7200_ctl/dri_cnt[4]/CLK (GTP_DFF_RE) - - - - tco - 0.329 - 3.839 + 0.000 + 0.000 r - ms72xx_ctl/ms7200_ctl/dri_cnt[4]/Q (GTP_DFF_RE) - - - - net (fanout=3) - 0.605 - 4.444 - - ms72xx_ctl/ms7200_ctl/dri_cnt [4] - - - - - - - - ms72xx_ctl/ms7200_ctl/N8_3/I0 (GTP_LUT3) - - - - td - 0.243 - 4.687 - f - ms72xx_ctl/ms7200_ctl/N8_3/Z (GTP_LUT3) + cmos1_pclk (port) net (fanout=1) - 0.464 - 5.151 - - ms72xx_ctl/ms7200_ctl/_N95853 + 0.000 + 0.000 + + cmos1_pclk - + - ms72xx_ctl/ms7200_ctl/N1872_5/I3 (GTP_LUT4) + cmos1_pclk_ibuf/I (GTP_INBUF) - + td - 0.185 - 5.336 + 1.211 + 1.211 r - ms72xx_ctl/ms7200_ctl/N1872_5/Z (GTP_LUT4) + cmos1_pclk_ibuf/O (GTP_INBUF) - net (fanout=6) - 0.693 - 6.029 - - ms72xx_ctl/ms7200_ctl/_N95857 + net (fanout=126) + 3.204 + 4.415 + + nt_cmos1_pclk - - + - ms72xx_ctl/ms7200_ctl/N2053_1/I1 (GTP_LUT2) - - - - td - 0.185 - 6.214 r - ms72xx_ctl/ms7200_ctl/N2053_1/Z (GTP_LUT2) - - - - net (fanout=15) - 0.810 - 7.024 - - ms72xx_ctl/ms7200_ctl/N261 + u_ov5640/cmos1_d_d0[0]/CLK (GTP_DFF) - - - + + clock pessimism + 0.000 + 4.415 - ms72xx_ctl/ms7200_ctl/N40_9/I0 (GTP_LUT5) - - td - 0.185 - 7.209 - r - ms72xx_ctl/ms7200_ctl/N40_9/Z (GTP_LUT5) + clock uncertainty + + 0.200 + 4.615 + + + Hold time + + 0.039 + 4.654 + - net (fanout=4) - 0.641 - 7.850 - - ms72xx_ctl/ms7200_ctl/N2093 [4] +
+
+
+
+ + -1.352 + 1 + 1 + cmos1_data[1] + u_ov5640/cmos1_d_d0[1]/D + + cmos1_pclk + cmos1_pclk + rise-rise + 4.415 + 0.000 + 4.415 + 0.000 + 0.000 + 2.302 + 1.211 (52.6%) + 1.091 (47.4%) + + Path #2: hold slack is -1.352(VIOLATED) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + - + Clock cmos1_pclk (rising edge) + 0.000 + 0.000 + r + + + Input external delay + 1.000 + 1.000 + r - ms72xx_ctl/ms7200_ctl/state_fsm[6:0]_2/I0 (GTP_LUT3) + cmos1_data[1] - td - 0.185 - 8.035 + 0.000 + 1.000 r - ms72xx_ctl/ms7200_ctl/state_fsm[6:0]_2/Z (GTP_LUT3) + cmos1_data[1] (port) - net (fanout=3) - 0.605 - 8.640 + net (fanout=1) + 0.000 + 1.000 - ms72xx_ctl/ms7200_ctl/state_n [1] + cmos1_data[1] @@ -72108,36 +73496,36 @@ - ms72xx_ctl/ms7200_ctl/N8_7/I3 (GTP_LUT5) + cmos1_data_ibuf[1]/I (GTP_INBUF) td - 0.172 - 8.812 - f - ms72xx_ctl/ms7200_ctl/N8_7/Z (GTP_LUT5) + 1.211 + 2.211 + r + cmos1_data_ibuf[1]/O (GTP_INBUF) - net (fanout=3) - 0.553 - 9.365 + net (fanout=1) + 1.091 + 3.302 - ms72xx_ctl/ms7200_ctl/N8 + nt_cmos1_data[1] - f - ms72xx_ctl/ms7200_ctl/freq_rec_2d[16]/CE (GTP_DFF_E) + r + u_ov5640/cmos1_d_d0[1]/D (GTP_DFF)
- +
Location Delay Type @@ -72147,28 +73535,28 @@ Logical Resource - Clock clk_10m (rising edge) + Clock cmos1_pclk (rising edge) - 100.000 - 100.000 + 0.000 + 0.000 r - clk + cmos1_pclk 0.000 - 100.000 + 0.000 r - clk (port) + cmos1_pclk (port) net (fanout=1) 0.000 - 100.000 + 0.000 - clk + cmos1_pclk @@ -72176,47 +73564,23 @@ - clk_ibuf/I (GTP_INBUF) + cmos1_pclk_ibuf/I (GTP_INBUF) td 1.211 - 101.211 - r - clk_ibuf/O (GTP_INBUF) - - - - net (fanout=1) - 1.091 - 102.302 - - nt_clk - - - - - - - - u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) - - - - td - 0.094 - 102.396 + 1.211 r - u_sys_pll/u_pll_e3/CLKOUT4 (GTP_PLL_E3) + cmos1_pclk_ibuf/O (GTP_INBUF) - net (fanout=256) - 1.114 - 103.510 + net (fanout=126) + 3.204 + 4.415 - clk_10m + nt_cmos1_pclk @@ -72224,29 +73588,29 @@ r - ms72xx_ctl/ms7200_ctl/freq_rec_2d[16]/CLK (GTP_DFF_E) + u_ov5640/cmos1_d_d0[1]/CLK (GTP_DFF) clock pessimism 0.000 - 103.510 + 4.415 clock uncertainty - -0.150 - 103.360 + 0.200 + 4.615 - Setup time + Hold time - -0.542 - 102.818 + 0.039 + 4.654 @@ -72255,27 +73619,27 @@ - 93.453 - 6 - 15 - ms72xx_ctl/ms7200_ctl/dri_cnt[4]/CLK - ms72xx_ctl/ms7200_ctl/freq_rec_2d[17]/CE + -1.352 + 1 + 1 + cmos1_data[2] + u_ov5640/cmos1_d_d0[2]/D - clk_10m - clk_10m + cmos1_pclk + cmos1_pclk rise-rise + 4.415 0.000 - 3.510 - 3.510 + 4.415 0.000 - 100.000 - 5.855 - 1.484 (25.3%) - 4.371 (74.7%) + 0.000 + 2.302 + 1.211 (52.6%) + 1.091 (47.4%) - Path #35: setup slack is 93.453(MET) + Path #3: hold slack is -1.352(VIOLATED) -
+
Location Delay Type @@ -72285,7 +73649,7 @@ Logical Resource - Clock clk_10m (rising edge) + Clock cmos1_pclk (rising edge) 0.000 0.000 @@ -72293,212 +73657,218 @@ - clk - - 0.000 + Input external delay + + 1.000 + 1.000 + r + + + + cmos1_data[2] + 0.000 + 1.000 r - clk (port) + cmos1_data[2] (port) net (fanout=1) 0.000 - 0.000 - - clk + 1.000 + + cmos1_data[2] - + - clk_ibuf/I (GTP_INBUF) + cmos1_data_ibuf[2]/I (GTP_INBUF) - + td 1.211 - 1.211 + 2.211 r - clk_ibuf/O (GTP_INBUF) + cmos1_data_ibuf[2]/O (GTP_INBUF) net (fanout=1) 1.091 - 2.302 - - nt_clk + 3.302 + + nt_cmos1_data[2] - - + - u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) - - - - td - 0.094 - 2.396 r - u_sys_pll/u_pll_e3/CLKOUT4 (GTP_PLL_E3) + u_ov5640/cmos1_d_d0[2]/D (GTP_DFF) +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + Clock cmos1_pclk (rising edge) - net (fanout=256) - 1.114 - 3.510 + 0.000 + 0.000 + r - clk_10m + cmos1_pclk - - - - r - ms72xx_ctl/ms7200_ctl/dri_cnt[4]/CLK (GTP_DFF_RE) - - - - tco - 0.329 - 3.839 + 0.000 + 0.000 r - ms72xx_ctl/ms7200_ctl/dri_cnt[4]/Q (GTP_DFF_RE) + cmos1_pclk (port) - net (fanout=3) - 0.605 - 4.444 - - ms72xx_ctl/ms7200_ctl/dri_cnt [4] + net (fanout=1) + 0.000 + 0.000 + + cmos1_pclk - + - ms72xx_ctl/ms7200_ctl/N8_3/I0 (GTP_LUT3) + cmos1_pclk_ibuf/I (GTP_INBUF) - + td - 0.243 - 4.687 - f - ms72xx_ctl/ms7200_ctl/N8_3/Z (GTP_LUT3) + 1.211 + 1.211 + r + cmos1_pclk_ibuf/O (GTP_INBUF) - net (fanout=1) - 0.464 - 5.151 - - ms72xx_ctl/ms7200_ctl/_N95853 + net (fanout=126) + 3.204 + 4.415 + + nt_cmos1_pclk - - + - ms72xx_ctl/ms7200_ctl/N1872_5/I3 (GTP_LUT4) - - - - td - 0.185 - 5.336 r - ms72xx_ctl/ms7200_ctl/N1872_5/Z (GTP_LUT4) - - - - net (fanout=6) - 0.693 - 6.029 - - ms72xx_ctl/ms7200_ctl/_N95857 + u_ov5640/cmos1_d_d0[2]/CLK (GTP_DFF) - - + clock pessimism + 0.000 + 4.415 - ms72xx_ctl/ms7200_ctl/N2053_1/I1 (GTP_LUT2) - - - - td - 0.185 - 6.214 - r - ms72xx_ctl/ms7200_ctl/N2053_1/Z (GTP_LUT2) + clock uncertainty + + 0.200 + 4.615 + - net (fanout=15) - 0.810 - 7.024 - - ms72xx_ctl/ms7200_ctl/N261 - - + Hold time + 0.039 + 4.654 - ms72xx_ctl/ms7200_ctl/N40_9/I0 (GTP_LUT5) +
+
+
+
+ + -1.352 + 1 + 1 + cmos2_data[0] + u_ov5640/cmos2_d_d0[0]/D + + cmos2_pclk + cmos2_pclk + rise-rise + 4.415 + 0.000 + 4.415 + 0.000 + 0.000 + 2.302 + 1.211 (52.6%) + 1.091 (47.4%) + + Path #4: hold slack is -1.352(VIOLATED) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + - - td - 0.185 - 7.209 + Clock cmos2_pclk (rising edge) + + 0.000 + 0.000 r - ms72xx_ctl/ms7200_ctl/N40_9/Z (GTP_LUT5) - - - net (fanout=4) - 0.641 - 7.850 - - ms72xx_ctl/ms7200_ctl/N2093 [4] - - - + Input external delay + 1.000 + 1.000 + r - ms72xx_ctl/ms7200_ctl/state_fsm[6:0]_2/I0 (GTP_LUT3) + cmos2_data[0] - td - 0.185 - 8.035 + 0.000 + 1.000 r - ms72xx_ctl/ms7200_ctl/state_fsm[6:0]_2/Z (GTP_LUT3) + cmos2_data[0] (port) - net (fanout=3) - 0.605 - 8.640 + net (fanout=1) + 0.000 + 1.000 - ms72xx_ctl/ms7200_ctl/state_n [1] + cmos2_data[0] @@ -72506,36 +73876,36 @@ - ms72xx_ctl/ms7200_ctl/N8_7/I3 (GTP_LUT5) + cmos2_data_ibuf[0]/I (GTP_INBUF) td - 0.172 - 8.812 - f - ms72xx_ctl/ms7200_ctl/N8_7/Z (GTP_LUT5) + 1.211 + 2.211 + r + cmos2_data_ibuf[0]/O (GTP_INBUF) - net (fanout=3) - 0.553 - 9.365 + net (fanout=1) + 1.091 + 3.302 - ms72xx_ctl/ms7200_ctl/N8 + nt_cmos2_data[0] - f - ms72xx_ctl/ms7200_ctl/freq_rec_2d[17]/CE (GTP_DFF_E) + r + u_ov5640/cmos2_d_d0[0]/D (GTP_DFF)
- +
Location Delay Type @@ -72545,52 +73915,28 @@ Logical Resource - Clock clk_10m (rising edge) + Clock cmos2_pclk (rising edge) - 100.000 - 100.000 + 0.000 + 0.000 r - clk + cmos2_pclk 0.000 - 100.000 - r - clk (port) - - - - net (fanout=1) 0.000 - 100.000 - - clk - - - - - - - - clk_ibuf/I (GTP_INBUF) - - - - td - 1.211 - 101.211 r - clk_ibuf/O (GTP_INBUF) + cmos2_pclk (port) net (fanout=1) - 1.091 - 102.302 + 0.000 + 0.000 - nt_clk + cmos2_pclk @@ -72598,23 +73944,23 @@ - u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + cmos2_pclk_ibuf/I (GTP_INBUF) td - 0.094 - 102.396 + 1.211 + 1.211 r - u_sys_pll/u_pll_e3/CLKOUT4 (GTP_PLL_E3) + cmos2_pclk_ibuf/O (GTP_INBUF) - net (fanout=256) - 1.114 - 103.510 + net (fanout=126) + 3.204 + 4.415 - clk_10m + nt_cmos2_pclk @@ -72622,29 +73968,29 @@ r - ms72xx_ctl/ms7200_ctl/freq_rec_2d[17]/CLK (GTP_DFF_E) + u_ov5640/cmos2_d_d0[0]/CLK (GTP_DFF) clock pessimism 0.000 - 103.510 + 4.415 clock uncertainty - -0.150 - 103.360 + 0.200 + 4.615 - Setup time + Hold time - -0.542 - 102.818 + 0.039 + 4.654 @@ -72653,27 +73999,27 @@ - 93.758 - 7 - 15 - ms72xx_ctl/ms7200_ctl/dri_cnt[4]/CLK - ms72xx_ctl/ms7200_ctl/freq_ensure/D + -1.352 + 1 + 1 + cmos2_data[1] + u_ov5640/cmos2_d_d0[1]/D - clk_10m - clk_10m + cmos2_pclk + cmos2_pclk rise-rise + 4.415 0.000 - 3.510 - 3.510 + 4.415 0.000 - 100.000 - 6.126 - 1.755 (28.6%) - 4.371 (71.4%) + 0.000 + 2.302 + 1.211 (52.6%) + 1.091 (47.4%) - Path #36: setup slack is 93.758(MET) + Path #5: hold slack is -1.352(VIOLATED) -
+
Location Delay Type @@ -72683,7 +74029,7 @@ Logical Resource - Clock clk_10m (rising edge) + Clock cmos2_pclk (rising edge) 0.000 0.000 @@ -72691,236 +74037,218 @@ - clk - - 0.000 + Input external delay + + 1.000 + 1.000 + r + + + + cmos2_data[1] + 0.000 + 1.000 r - clk (port) + cmos2_data[1] (port) net (fanout=1) 0.000 - 0.000 - - clk + 1.000 + + cmos2_data[1] - + - clk_ibuf/I (GTP_INBUF) + cmos2_data_ibuf[1]/I (GTP_INBUF) - + td 1.211 - 1.211 + 2.211 r - clk_ibuf/O (GTP_INBUF) + cmos2_data_ibuf[1]/O (GTP_INBUF) net (fanout=1) 1.091 - 2.302 - - nt_clk + 3.302 + + nt_cmos2_data[1] - - + - u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) - - - - td - 0.094 - 2.396 r - u_sys_pll/u_pll_e3/CLKOUT4 (GTP_PLL_E3) + u_ov5640/cmos2_d_d0[1]/D (GTP_DFF) +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + Clock cmos2_pclk (rising edge) - net (fanout=256) - 1.114 - 3.510 + 0.000 + 0.000 + r - clk_10m + cmos2_pclk - - - - r - ms72xx_ctl/ms7200_ctl/dri_cnt[4]/CLK (GTP_DFF_RE) - - - - tco - 0.329 - 3.839 + 0.000 + 0.000 r - ms72xx_ctl/ms7200_ctl/dri_cnt[4]/Q (GTP_DFF_RE) - - - - net (fanout=3) - 0.605 - 4.444 - - ms72xx_ctl/ms7200_ctl/dri_cnt [4] - - - - - - - - ms72xx_ctl/ms7200_ctl/N8_3/I0 (GTP_LUT3) - - - - td - 0.243 - 4.687 - f - ms72xx_ctl/ms7200_ctl/N8_3/Z (GTP_LUT3) + cmos2_pclk (port) net (fanout=1) - 0.464 - 5.151 - - ms72xx_ctl/ms7200_ctl/_N95853 + 0.000 + 0.000 + + cmos2_pclk - + - ms72xx_ctl/ms7200_ctl/N1872_5/I3 (GTP_LUT4) + cmos2_pclk_ibuf/I (GTP_INBUF) - + td - 0.185 - 5.336 + 1.211 + 1.211 r - ms72xx_ctl/ms7200_ctl/N1872_5/Z (GTP_LUT4) + cmos2_pclk_ibuf/O (GTP_INBUF) - net (fanout=6) - 0.693 - 6.029 - - ms72xx_ctl/ms7200_ctl/_N95857 + net (fanout=126) + 3.204 + 4.415 + + nt_cmos2_pclk - - + - ms72xx_ctl/ms7200_ctl/N2053_1/I1 (GTP_LUT2) - - - - td - 0.185 - 6.214 r - ms72xx_ctl/ms7200_ctl/N2053_1/Z (GTP_LUT2) - - - - net (fanout=15) - 0.810 - 7.024 - - ms72xx_ctl/ms7200_ctl/N261 + u_ov5640/cmos2_d_d0[1]/CLK (GTP_DFF) - - + clock pessimism + 0.000 + 4.415 - ms72xx_ctl/ms7200_ctl/N40_9/I0 (GTP_LUT5) - - - - td - 0.185 - 7.209 - r - ms72xx_ctl/ms7200_ctl/N40_9/Z (GTP_LUT5) + clock uncertainty + + 0.200 + 4.615 + - net (fanout=4) - 0.641 - 7.850 - - ms72xx_ctl/ms7200_ctl/N2093 [4] - - + Hold time + 0.039 + 4.654 - ms72xx_ctl/ms7200_ctl/state_fsm[6:0]_2/I0 (GTP_LUT3) +
+
+
+
+ + -1.352 + 1 + 1 + cmos2_data[2] + u_ov5640/cmos2_d_d0[2]/D + + cmos2_pclk + cmos2_pclk + rise-rise + 4.415 + 0.000 + 4.415 + 0.000 + 0.000 + 2.302 + 1.211 (52.6%) + 1.091 (47.4%) + + Path #6: hold slack is -1.352(VIOLATED) + + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + - - td - 0.185 - 8.035 + Clock cmos2_pclk (rising edge) + + 0.000 + 0.000 r - ms72xx_ctl/ms7200_ctl/state_fsm[6:0]_2/Z (GTP_LUT3) - - - net (fanout=3) - 0.605 - 8.640 - - ms72xx_ctl/ms7200_ctl/state_n [1] - - - + Input external delay + 1.000 + 1.000 + r - ms72xx_ctl/ms7200_ctl/N8_7/I3 (GTP_LUT5) + cmos2_data[2] - td - 0.185 - 8.825 + 0.000 + 1.000 r - ms72xx_ctl/ms7200_ctl/N8_7/Z (GTP_LUT5) + cmos2_data[2] (port) - net (fanout=3) - 0.553 - 9.378 + net (fanout=1) + 0.000 + 1.000 - ms72xx_ctl/ms7200_ctl/N8 + cmos2_data[2] @@ -72928,36 +74256,36 @@ - ms72xx_ctl/ms7200_ctl/freq_ensure_rs_mux/I0 (GTP_LUT4) + cmos2_data_ibuf[2]/I (GTP_INBUF) td - 0.258 - 9.636 - f - ms72xx_ctl/ms7200_ctl/freq_ensure_rs_mux/Z (GTP_LUT4) + 1.211 + 2.211 + r + cmos2_data_ibuf[2]/O (GTP_INBUF) net (fanout=1) - 0.000 - 9.636 + 1.091 + 3.302 - ms72xx_ctl/ms7200_ctl/_N103492 + nt_cmos2_data[2] - f - ms72xx_ctl/ms7200_ctl/freq_ensure/D (GTP_DFF) + r + u_ov5640/cmos2_d_d0[2]/D (GTP_DFF)
- +
Location Delay Type @@ -72967,28 +74295,28 @@ Logical Resource - Clock clk_10m (rising edge) + Clock cmos2_pclk (rising edge) - 100.000 - 100.000 + 0.000 + 0.000 r - clk + cmos2_pclk 0.000 - 100.000 + 0.000 r - clk (port) + cmos2_pclk (port) net (fanout=1) 0.000 - 100.000 + 0.000 - clk + cmos2_pclk @@ -72996,47 +74324,23 @@ - clk_ibuf/I (GTP_INBUF) + cmos2_pclk_ibuf/I (GTP_INBUF) td 1.211 - 101.211 - r - clk_ibuf/O (GTP_INBUF) - - - - net (fanout=1) - 1.091 - 102.302 - - nt_clk - - - - - - - - u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) - - - - td - 0.094 - 102.396 + 1.211 r - u_sys_pll/u_pll_e3/CLKOUT4 (GTP_PLL_E3) + cmos2_pclk_ibuf/O (GTP_INBUF) - net (fanout=256) - 1.114 - 103.510 + net (fanout=126) + 3.204 + 4.415 - clk_10m + nt_cmos2_pclk @@ -73044,29 +74348,29 @@ r - ms72xx_ctl/ms7200_ctl/freq_ensure/CLK (GTP_DFF) + u_ov5640/cmos2_d_d0[2]/CLK (GTP_DFF) clock pessimism 0.000 - 103.510 + 4.415 clock uncertainty - -0.150 - 103.360 + 0.200 + 4.615 - Setup time + Hold time - 0.034 - 103.394 + 0.039 + 4.654 @@ -73075,27 +74379,27 @@ - 49994.585 - 4 + 0.453 + 0 1 - u_ov5640/coms1_reg_config/reg_data/CLKB - u_ov5640/coms1_reg_config/u1/reg_sdat/D + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[0]/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_0/DI - clk_20k - clk_20k + ddrphy_clkin + ddrphy_clkin rise-rise 0.000 - 6.243 - 6.243 + 7.688 + 7.688 0.000 - 50000.000 - 5.399 - 3.104 (57.5%) - 2.295 (42.5%) + 0.000 + 0.787 + 0.323 (41.0%) + 0.464 (59.0%) - Path #37: setup slack is 49994.585(MET) + Path #7: hold slack is 0.453(MET) -
+
Location Delay Type @@ -73105,7 +74409,7 @@ Logical Resource - Clock clk_20k (rising edge) + Clock ddrphy_clkin (rising edge) 0.000 0.000 @@ -73163,42 +74467,18 @@ td - 0.098 - 2.400 - r - u_sys_pll/u_pll_e3/CLKOUT3 (GTP_PLL_E3) - - - - net (fanout=26) - 0.713 - 3.113 - - clk_25m - - - - - - - r - u_ov5640/coms1_reg_config/clk_20k_regdiv/CLK (GTP_DFF_RE) - - - - tco - 0.329 - 3.442 + 0.089 + 2.391 r - u_ov5640/coms1_reg_config/clk_20k_regdiv/Q (GTP_DFF_RE) + u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=3) + net (fanout=7) 0.605 - 4.047 + 2.996 - u_ov5640/coms1_reg_config/clk_20k_regdiv + ddr_clk @@ -73206,143 +74486,95 @@ - u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/CLKIN (GTP_CLKBUFG) - - - - td - 0.000 - 4.047 - r - u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/CLKOUT (GTP_CLKBUFG) - - - - net (fanout=25) - 2.196 - 6.243 - - u_ov5640/coms1_reg_config/clock_20k + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - - - - r - u_ov5640/coms1_reg_config/reg_data/CLKB (GTP_DRM18K) - - - - tco - 2.024 - 8.267 - f - u_ov5640/coms1_reg_config/reg_data/DOB[7] (GTP_DRM18K) - - - - net (fanout=1) - 0.903 - 9.170 - - u_ov5640/coms1_reg_config/i2c_data [23] - - - - - - - - u_ov5640/coms1_reg_config/u1/N267_29/I1 (GTP_LUT5M) - - - td - 0.365 - 9.535 - f - u_ov5640/coms1_reg_config/u1/N267_29/Z (GTP_LUT5M) + 0.000 + 2.996 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=1) - 0.464 - 9.999 - - u_ov5640/coms1_reg_config/u1/_N25461 + net (fanout=71) + 0.847 + 3.843 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - + - u_ov5640/coms1_reg_config/u1/N267_35/I0 (GTP_LUT5) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - + td - 0.185 - 10.184 + 0.094 + 3.937 r - u_ov5640/coms1_reg_config/u1/N267_35/Z (GTP_LUT5) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=1) - 0.464 - 10.648 - - u_ov5640/coms1_reg_config/u1/_N25467 + net (fanout=3) + 0.605 + 4.542 + + u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] - + - u_ov5640/coms1_reg_config/u1/N267_36/ID (GTP_LUT5M) + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) - + td - 0.265 - 10.913 - f - u_ov5640/coms1_reg_config/u1/N267_36/Z (GTP_LUT5M) + 0.000 + 4.542 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) - net (fanout=1) - 0.464 - 11.377 - - u_ov5640/coms1_reg_config/u1/_N25468 + net (fanout=5817) + 3.146 + 7.688 + + u_axi_ddr_top/clk - - + - u_ov5640/coms1_reg_config/u1/reg_sdat_ce_mux/ID (GTP_LUT5M) + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[0]/CLK (GTP_DFF_C) - td - 0.265 - 11.642 + tco + 0.323 + 8.011 f - u_ov5640/coms1_reg_config/u1/reg_sdat_ce_mux/Z (GTP_LUT5M) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[0]/Q (GTP_DFF_C) net (fanout=1) - 0.000 - 11.642 + 0.464 + 8.475 - u_ov5640/coms1_reg_config/u1/_N103476 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/rid [0] @@ -73350,12 +74582,12 @@ f - u_ov5640/coms1_reg_config/u1/reg_sdat/D (GTP_DFF_S) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_0/DI (GTP_RAM32X1DP)
- +
Location Delay Type @@ -73365,10 +74597,10 @@ Logical Resource - Clock clk_20k (rising edge) + Clock ddrphy_clkin (rising edge) - 50000.000 - 50000.000 + 0.000 + 0.000 r @@ -73376,7 +74608,7 @@ clk0.000 - 50000.000 + 0.000rclk (port) @@ -73384,7 +74616,7 @@ net (fanout=1) 0.000 - 50000.000 + 0.000 clk @@ -73400,7 +74632,7 @@ td 1.211 - 50001.211 + 1.211 r clk_ibuf/O (GTP_INBUF) @@ -73408,7 +74640,7 @@ net (fanout=1) 1.091 - 50002.302 + 2.302 nt_clk @@ -73423,42 +74655,66 @@ td - 0.098 - 50002.400 + 0.089 + 2.391 r - u_sys_pll/u_pll_e3/CLKOUT3 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=26) - 0.713 - 50003.113 + net (fanout=7) + 0.605 + 2.996 - clk_25m + ddr_clk + + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + + + + td + 0.000 + 2.996 r - u_ov5640/coms1_reg_config/clk_20k_regdiv/CLK (GTP_DFF_RE) + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + + + + net (fanout=71) + 0.847 + 3.843 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - tco - 0.329 - 50003.442 + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.094 + 3.937 r - u_ov5640/coms1_reg_config/clk_20k_regdiv/Q (GTP_DFF_RE) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) net (fanout=3) 0.605 - 50004.047 + 4.542 - u_ov5640/coms1_reg_config/clk_20k_regdiv + u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] @@ -73466,23 +74722,23 @@ - u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/CLKIN (GTP_CLKBUFG) + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) td 0.000 - 50004.047 + 4.542 r - u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/CLKOUT (GTP_CLKBUFG) + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) - net (fanout=25) - 2.196 - 50006.243 + net (fanout=5817) + 3.146 + 7.688 - u_ov5640/coms1_reg_config/clock_20k + u_axi_ddr_top/clk @@ -73490,29 +74746,29 @@ r - u_ov5640/coms1_reg_config/u1/reg_sdat/CLK (GTP_DFF_S) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_0/WCLK (GTP_RAM32X1DP) clock pessimism 0.000 - 50006.243 + 7.688 clock uncertainty - -0.050 - 50006.193 + 0.000 + 7.688 - Setup time + Hold time - 0.034 - 50006.227 + 0.334 + 8.022 @@ -73521,27 +74777,27 @@ - 49994.585 - 4 + 0.453 + 0 1 - u_ov5640/coms2_reg_config/reg_data/CLKB - u_ov5640/coms2_reg_config/u1/reg_sdat/D + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[1]/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/DI - clk_20k - clk_20k + ddrphy_clkin + ddrphy_clkin rise-rise 0.000 - 6.243 - 6.243 + 7.688 + 7.688 0.000 - 50000.000 - 5.399 - 3.104 (57.5%) - 2.295 (42.5%) + 0.000 + 0.787 + 0.323 (41.0%) + 0.464 (59.0%) - Path #38: setup slack is 49994.585(MET) + Path #8: hold slack is 0.453(MET) -
+
Location Delay Type @@ -73551,7 +74807,7 @@ Logical Resource - Clock clk_20k (rising edge) + Clock ddrphy_clkin (rising edge) 0.000 0.000 @@ -73609,42 +74865,18 @@ td - 0.098 - 2.400 - r - u_sys_pll/u_pll_e3/CLKOUT3 (GTP_PLL_E3) - - - - net (fanout=26) - 0.713 - 3.113 - - clk_25m - - - - - - - r - u_ov5640/coms2_reg_config/clk_20k_regdiv/CLK (GTP_DFF_RE) - - - - tco - 0.329 - 3.442 + 0.089 + 2.391 r - u_ov5640/coms2_reg_config/clk_20k_regdiv/Q (GTP_DFF_RE) + u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=3) + net (fanout=7) 0.605 - 4.047 + 2.996 - u_ov5640/coms2_reg_config/clk_20k_regdiv + ddr_clk @@ -73652,143 +74884,95 @@ - u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/CLKIN (GTP_CLKBUFG) + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) td 0.000 - 4.047 + 2.996 r - u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/CLKOUT (GTP_CLKBUFG) + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=25) - 2.196 - 6.243 + net (fanout=71) + 0.847 + 3.843 - u_ov5640/coms2_reg_config/clock_20k + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - r - u_ov5640/coms2_reg_config/reg_data/CLKB (GTP_DRM18K) - - - - tco - 2.024 - 8.267 - f - u_ov5640/coms2_reg_config/reg_data/DOB[4] (GTP_DRM18K) - - - - net (fanout=1) - 0.903 - 9.170 - - u_ov5640/coms2_reg_config/i2c_data [20] - - - - - - - u_ov5640/coms2_reg_config/u1/N267_29/I1 (GTP_LUT5M) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - + td - 0.365 - 9.535 - f - u_ov5640/coms2_reg_config/u1/N267_29/Z (GTP_LUT5M) + 0.094 + 3.937 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=1) - 0.464 - 9.999 - - u_ov5640/coms2_reg_config/u1/_N25904 + net (fanout=3) + 0.605 + 4.542 + + u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] - + - u_ov5640/coms2_reg_config/u1/N267_35/I0 (GTP_LUT5) + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) - + td - 0.185 - 10.184 + 0.000 + 4.542 r - u_ov5640/coms2_reg_config/u1/N267_35/Z (GTP_LUT5) - - - - net (fanout=1) - 0.464 - 10.648 - - u_ov5640/coms2_reg_config/u1/_N25910 + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) - - - + net (fanout=5817) + 3.146 + 7.688 - u_ov5640/coms2_reg_config/u1/N267_36/ID (GTP_LUT5M) - - - - td - 0.265 - 10.913 - f - u_ov5640/coms2_reg_config/u1/N267_36/Z (GTP_LUT5M) - - - - net (fanout=1) - 0.464 - 11.377 - - u_ov5640/coms2_reg_config/u1/_N25911 + u_axi_ddr_top/clk - - + - u_ov5640/coms2_reg_config/u1/reg_sdat_ce_mux/ID (GTP_LUT5M) + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[1]/CLK (GTP_DFF_C) - td - 0.265 - 11.642 + tco + 0.323 + 8.011 f - u_ov5640/coms2_reg_config/u1/reg_sdat_ce_mux/Z (GTP_LUT5M) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[1]/Q (GTP_DFF_C) net (fanout=1) - 0.000 - 11.642 + 0.464 + 8.475 - u_ov5640/coms2_reg_config/u1/_N103481 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/rid [1] @@ -73796,12 +74980,12 @@ f - u_ov5640/coms2_reg_config/u1/reg_sdat/D (GTP_DFF_S) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/DI (GTP_RAM32X1DP)
- +
Location Delay Type @@ -73811,10 +74995,10 @@ Logical Resource - Clock clk_20k (rising edge) + Clock ddrphy_clkin (rising edge) - 50000.000 - 50000.000 + 0.000 + 0.000 r @@ -73822,7 +75006,7 @@ clk0.000 - 50000.000 + 0.000rclk (port) @@ -73830,7 +75014,7 @@ net (fanout=1) 0.000 - 50000.000 + 0.000 clk @@ -73846,7 +75030,7 @@ td 1.211 - 50001.211 + 1.211 r clk_ibuf/O (GTP_INBUF) @@ -73854,7 +75038,7 @@ net (fanout=1) 1.091 - 50002.302 + 2.302 nt_clk @@ -73869,42 +75053,66 @@ td - 0.098 - 50002.400 + 0.089 + 2.391 r - u_sys_pll/u_pll_e3/CLKOUT3 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=26) - 0.713 - 50003.113 + net (fanout=7) + 0.605 + 2.996 - clk_25m + ddr_clk + + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + + + + td + 0.000 + 2.996 r - u_ov5640/coms2_reg_config/clk_20k_regdiv/CLK (GTP_DFF_RE) + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + + + + net (fanout=71) + 0.847 + 3.843 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - tco - 0.329 - 50003.442 + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.094 + 3.937 r - u_ov5640/coms2_reg_config/clk_20k_regdiv/Q (GTP_DFF_RE) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) net (fanout=3) 0.605 - 50004.047 + 4.542 - u_ov5640/coms2_reg_config/clk_20k_regdiv + u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] @@ -73912,23 +75120,23 @@ - u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/CLKIN (GTP_CLKBUFG) + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) td 0.000 - 50004.047 + 4.542 r - u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/CLKOUT (GTP_CLKBUFG) + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) - net (fanout=25) - 2.196 - 50006.243 + net (fanout=5817) + 3.146 + 7.688 - u_ov5640/coms2_reg_config/clock_20k + u_axi_ddr_top/clk @@ -73936,29 +75144,29 @@ r - u_ov5640/coms2_reg_config/u1/reg_sdat/CLK (GTP_DFF_S) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/WCLK (GTP_RAM32X1DP) clock pessimism 0.000 - 50006.243 + 7.688 clock uncertainty - -0.050 - 50006.193 + 0.000 + 7.688 - Setup time + Hold time - 0.034 - 50006.227 + 0.334 + 8.022 @@ -73967,27 +75175,27 @@ - 49995.326 - 4 - 6 - u_ov5640/coms1_reg_config/reg_index[0]/CLK - u_ov5640/coms1_reg_config/reg_data/CEA + 0.453 + 0 + 1 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[2]/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_2/DI - clk_20k - clk_20k + ddrphy_clkin + ddrphy_clkin rise-rise 0.000 - 6.243 - 6.243 + 7.688 + 7.688 0.000 - 50000.000 - 4.539 - 1.121 (24.7%) - 3.418 (75.3%) + 0.000 + 0.787 + 0.323 (41.0%) + 0.464 (59.0%) - Path #39: setup slack is 49995.326(MET) + Path #9: hold slack is 0.453(MET) -
+
Location Delay Type @@ -73997,7 +75205,7 @@ Logical Resource - Clock clk_20k (rising edge) + Clock ddrphy_clkin (rising edge) 0.000 0.000 @@ -74032,222 +75240,150 @@ td 1.211 - 1.211 - r - clk_ibuf/O (GTP_INBUF) - - - - net (fanout=1) - 1.091 - 2.302 - - nt_clk - - - - - - - - u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) - - - - td - 0.098 - 2.400 - r - u_sys_pll/u_pll_e3/CLKOUT3 (GTP_PLL_E3) - - - - net (fanout=26) - 0.713 - 3.113 - - clk_25m - - - - - - - r - u_ov5640/coms1_reg_config/clk_20k_regdiv/CLK (GTP_DFF_RE) - - - - tco - 0.329 - 3.442 - r - u_ov5640/coms1_reg_config/clk_20k_regdiv/Q (GTP_DFF_RE) - - - - net (fanout=3) - 0.605 - 4.047 - - u_ov5640/coms1_reg_config/clk_20k_regdiv - - - - - - - - u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/CLKIN (GTP_CLKBUFG) - - - - td - 0.000 - 4.047 + 1.211 r - u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/CLKOUT (GTP_CLKBUFG) + clk_ibuf/O (GTP_INBUF) - net (fanout=25) - 2.196 - 6.243 + net (fanout=1) + 1.091 + 2.302 - u_ov5640/coms1_reg_config/clock_20k + nt_clk - r - u_ov5640/coms1_reg_config/reg_index[0]/CLK (GTP_DFF_RE) + + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) - - tco - 0.329 - 6.572 + + td + 0.089 + 2.391 r - u_ov5640/coms1_reg_config/reg_index[0]/Q (GTP_DFF_RE) + u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=6) - 0.693 - 7.265 - - u_ov5640/coms1_reg_config/reg_index [0] + net (fanout=7) + 0.605 + 2.996 + + ddr_clk - + - u_ov5640/coms1_reg_config/N26_mux2/I0 (GTP_LUT3) + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - + td - 0.237 - 7.502 - f - u_ov5640/coms1_reg_config/N26_mux2/Z (GTP_LUT3) + 0.000 + 2.996 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=1) - 0.464 - 7.966 - - u_ov5640/coms1_reg_config/_N9682 + net (fanout=71) + 0.847 + 3.843 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - + - u_ov5640/coms1_reg_config/N26_mux6_3/I0 (GTP_LUT5) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - + td - 0.185 - 8.151 + 0.094 + 3.937 r - u_ov5640/coms1_reg_config/N26_mux6_3/Z (GTP_LUT5) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2) - 0.553 - 8.704 - - u_ov5640/coms1_reg_config/_N9690 + net (fanout=3) + 0.605 + 4.542 + + u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] - + - u_ov5640/coms1_reg_config/N1134_1/I0 (GTP_LUT4) + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) - + td - 0.185 - 8.889 + 0.000 + 4.542 r - u_ov5640/coms1_reg_config/N1134_1/Z (GTP_LUT4) + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) - net (fanout=4) - 0.641 - 9.530 - - u_ov5640/coms1_reg_config/_N96528 + net (fanout=5817) + 3.146 + 7.688 + + u_axi_ddr_top/clk - - + - u_ov5640/coms1_reg_config/N1193_3/I1 (GTP_LUT3) + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[2]/CLK (GTP_DFF_C) - td - 0.185 - 9.715 - r - u_ov5640/coms1_reg_config/N1193_3/Z (GTP_LUT3) + tco + 0.323 + 8.011 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[2]/Q (GTP_DFF_C) - net (fanout=2) - 1.067 - 10.782 + net (fanout=1) + 0.464 + 8.475 - u_ov5640/coms1_reg_config/N1193 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/rid [2] - r - u_ov5640/coms1_reg_config/reg_data/CEA (GTP_DRM18K) + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_2/DI (GTP_RAM32X1DP)
- +
Location Delay Type @@ -74257,10 +75393,10 @@ Logical Resource - Clock clk_20k (rising edge) + Clock ddrphy_clkin (rising edge) - 50000.000 - 50000.000 + 0.000 + 0.000 r @@ -74268,7 +75404,7 @@ clk0.000 - 50000.000 + 0.000rclk (port) @@ -74276,7 +75412,7 @@ net (fanout=1) 0.000 - 50000.000 + 0.000 clk @@ -74292,7 +75428,7 @@ td 1.211 - 50001.211 + 1.211 r clk_ibuf/O (GTP_INBUF) @@ -74300,7 +75436,7 @@ net (fanout=1) 1.091 - 50002.302 + 2.302 nt_clk @@ -74315,42 +75451,66 @@ td - 0.098 - 50002.400 + 0.089 + 2.391 r - u_sys_pll/u_pll_e3/CLKOUT3 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=26) - 0.713 - 50003.113 + net (fanout=7) + 0.605 + 2.996 - clk_25m + ddr_clk + + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + + + + td + 0.000 + 2.996 r - u_ov5640/coms1_reg_config/clk_20k_regdiv/CLK (GTP_DFF_RE) + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + + + + net (fanout=71) + 0.847 + 3.843 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - tco - 0.329 - 50003.442 + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.094 + 3.937 r - u_ov5640/coms1_reg_config/clk_20k_regdiv/Q (GTP_DFF_RE) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) net (fanout=3) 0.605 - 50004.047 + 4.542 - u_ov5640/coms1_reg_config/clk_20k_regdiv + u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] @@ -74358,23 +75518,23 @@ - u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/CLKIN (GTP_CLKBUFG) + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) td 0.000 - 50004.047 + 4.542 r - u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/CLKOUT (GTP_CLKBUFG) + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) - net (fanout=25) - 2.196 - 50006.243 + net (fanout=5817) + 3.146 + 7.688 - u_ov5640/coms1_reg_config/clock_20k + u_axi_ddr_top/clk @@ -74382,29 +75542,29 @@ r - u_ov5640/coms1_reg_config/reg_data/CLKA (GTP_DRM18K) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_2/WCLK (GTP_RAM32X1DP) clock pessimism 0.000 - 50006.243 + 7.688 clock uncertainty - -0.050 - 50006.193 + 0.000 + 7.688 - Setup time + Hold time - -0.085 - 50006.108 + 0.334 + 8.022 @@ -74412,49 +75572,28 @@ -
- - - Slack - Logic Levels - High Fanout - Start Point - End Point - Exception - Launch Clock - Capture Clock - Clock Edges - Clock Skew - Launch Clock Delay - Capture Clock Delay - Clock Pessimism Removal - Requirement - Data delay - Logic delay - Route delay - - -1.352 - 1 + 0.540 + 0 1 - cmos1_data[0] - u_ov5640/cmos1_d_d0[0]/D + param_manager_inst/clk_ms/CLK + param_manager_inst/key_debounce_key_left/clk_ms_ff0/D - cmos1_pclk - cmos1_pclk + eth_rxc + eth_rxc rise-rise - 4.415 0.000 - 4.415 + 5.600 + 5.600 0.000 0.000 - 2.302 - 1.211 (52.6%) - 1.091 (47.4%) + 0.787 + 0.323 (41.0%) + 0.464 (59.0%) - Path #1: hold slack is -1.352(VIOLATED) + Path #10: hold slack is 0.540(MET) -
+
Location Delay Type @@ -74464,7 +75603,7 @@ Logical Resource - Clock cmos1_pclk (rising edge) + Clock eth_rxc (rising edge) 0.000 0.000 @@ -74472,65 +75611,129 @@ - Input external delay + eth_rxc + + 0.000 + 0.000 + r + eth_rxc (port) + + - 1.000 - 1.000 + net (fanout=1) + 0.000 + 0.000 + + eth_rxc + + + + + + + + eth_rxc_ibuf/I (GTP_INBUF) + + + + td + 1.211 + 1.211 r + eth_rxc_ibuf/O (GTP_INBUF) + + + net (fanout=2) + 1.180 + 2.391 + + nt_eth_rxc - cmos1_data[0] - - 0.000 - 1.000 + + + + + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKIN (GTP_IOCLKDELAY) + + + + td + 0.549 + 2.940 r - cmos1_data[0] (port) + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKOUT (GTP_IOCLKDELAY) net (fanout=1) - 0.000 - 1.000 - - cmos1_data[0] + 0.464 + 3.404 + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf - + - cmos1_data_ibuf[0]/I (GTP_INBUF) + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKIN (GTP_CLKBUFG) - + td - 1.211 - 2.211 + 0.000 + 3.404 r - cmos1_data_ibuf[0]/O (GTP_INBUF) + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKOUT (GTP_CLKBUFG) + + + + net (fanout=1988) + 2.196 + 5.600 + + gmii_clk + + + + + + + r + param_manager_inst/clk_ms/CLK (GTP_DFF_R) + + + + tco + 0.323 + 5.923 + f + param_manager_inst/clk_ms/Q (GTP_DFF_R) net (fanout=1) - 1.091 - 3.302 + 0.464 + 6.387 - nt_cmos1_data[0] + param_manager_inst/clk_ms - r - u_ov5640/cmos1_d_d0[0]/D (GTP_DFF) + f + param_manager_inst/key_debounce_key_left/clk_ms_ff0/D (GTP_DFF)
- +
Location Delay Type @@ -74540,7 +75743,7 @@ Logical Resource - Clock cmos1_pclk (rising edge) + Clock eth_rxc (rising edge) 0.000 0.000 @@ -74548,12 +75751,12 @@ - cmos1_pclk + eth_rxc 0.000 0.000 r - cmos1_pclk (port) + eth_rxc (port) @@ -74561,7 +75764,7 @@ 0.000 0.000 - cmos1_pclk + eth_rxc @@ -74569,7 +75772,7 @@ - cmos1_pclk_ibuf/I (GTP_INBUF) + eth_rxc_ibuf/I (GTP_INBUF) @@ -74577,15 +75780,63 @@ 1.211 1.211 r - cmos1_pclk_ibuf/O (GTP_INBUF) + eth_rxc_ibuf/O (GTP_INBUF) - net (fanout=126) - 3.204 - 4.415 + net (fanout=2) + 1.180 + 2.391 - nt_cmos1_pclk + nt_eth_rxc + + + + + + + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKIN (GTP_IOCLKDELAY) + + + + td + 0.549 + 2.940 + r + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKOUT (GTP_IOCLKDELAY) + + + + net (fanout=1) + 0.464 + 3.404 + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf + + + + + + + + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKIN (GTP_CLKBUFG) + + + + td + 0.000 + 3.404 + r + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKOUT (GTP_CLKBUFG) + + + + net (fanout=1988) + 2.196 + 5.600 + + gmii_clk @@ -74593,13 +75844,13 @@ r - u_ov5640/cmos1_d_d0[0]/CLK (GTP_DFF) + param_manager_inst/key_debounce_key_left/clk_ms_ff0/CLK (GTP_DFF) clock pessimism 0.000 - 4.415 + 5.600 @@ -74607,15 +75858,15 @@ clock uncertainty 0.200 - 4.615 + 5.800 Hold time - 0.039 - 4.654 + 0.047 + 5.847 @@ -74624,27 +75875,27 @@ - -1.352 - 1 + 0.540 + 0 1 - cmos1_data[1] - u_ov5640/cmos1_d_d0[1]/D + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/CLK + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[0]/D - cmos1_pclk - cmos1_pclk + hdmi_in_clk + hdmi_in_clk rise-rise - 4.415 0.000 4.415 + 4.415 0.000 0.000 - 2.302 - 1.211 (52.6%) - 1.091 (47.4%) + 0.787 + 0.323 (41.0%) + 0.464 (59.0%) - Path #2: hold slack is -1.352(VIOLATED) + Path #11: hold slack is 0.540(MET) -
+
Location Delay Type @@ -74654,7 +75905,7 @@ Logical Resource - Clock cmos1_pclk (rising edge) + Clock hdmi_in_clk (rising edge) 0.000 0.000 @@ -74662,65 +75913,81 @@ - Input external delay - - 1.000 - 1.000 - r - - - - cmos1_data[1] - + hdmi_in_clk + + 0.000 0.000 - 1.000 r - cmos1_data[1] (port) + hdmi_in_clk (port) net (fanout=1) 0.000 - 1.000 - - cmos1_data[1] + 0.000 + + hdmi_in_clk - + - cmos1_data_ibuf[1]/I (GTP_INBUF) + hdmi_in_clk_ibuf/I (GTP_INBUF) - + td 1.211 - 2.211 + 1.211 r - cmos1_data_ibuf[1]/O (GTP_INBUF) + hdmi_in_clk_ibuf/O (GTP_INBUF) + + + + net (fanout=173) + 3.204 + 4.415 + + nt_hdmi_in_clk + + + + + + + r + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/CLK (GTP_DFF_C) + + + + tco + 0.323 + 4.738 + f + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/Q (GTP_DFF_C) net (fanout=1) - 1.091 - 3.302 + 0.464 + 5.202 - nt_cmos1_data[1] + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr1 [0] - r - u_ov5640/cmos1_d_d0[1]/D (GTP_DFF) + f + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[0]/D (GTP_DFF_C)
- +
Location Delay Type @@ -74730,7 +75997,7 @@ Logical Resource - Clock cmos1_pclk (rising edge) + Clock hdmi_in_clk (rising edge) 0.000 0.000 @@ -74738,12 +76005,12 @@ - cmos1_pclk + hdmi_in_clk 0.000 0.000 r - cmos1_pclk (port) + hdmi_in_clk (port) @@ -74751,7 +76018,7 @@ 0.000 0.000 - cmos1_pclk + hdmi_in_clk @@ -74759,7 +76026,7 @@ - cmos1_pclk_ibuf/I (GTP_INBUF) + hdmi_in_clk_ibuf/I (GTP_INBUF) @@ -74767,15 +76034,15 @@ 1.211 1.211 r - cmos1_pclk_ibuf/O (GTP_INBUF) + hdmi_in_clk_ibuf/O (GTP_INBUF) - net (fanout=126) + net (fanout=173) 3.204 4.415 - nt_cmos1_pclk + nt_hdmi_in_clk @@ -74783,7 +76050,7 @@ r - u_ov5640/cmos1_d_d0[1]/CLK (GTP_DFF) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[0]/CLK (GTP_DFF_C) clock pessimism @@ -74804,8 +76071,8 @@ Hold time - 0.039 - 4.654 + 0.047 + 4.662 @@ -74814,27 +76081,27 @@ - -1.352 - 1 + 0.540 + 0 1 - cmos1_data[2] - u_ov5640/cmos1_d_d0[2]/D + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/CLK + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[1]/D - cmos1_pclk - cmos1_pclk + hdmi_in_clk + hdmi_in_clk rise-rise - 4.415 0.000 4.415 + 4.415 0.000 0.000 - 2.302 - 1.211 (52.6%) - 1.091 (47.4%) + 0.787 + 0.323 (41.0%) + 0.464 (59.0%) - Path #3: hold slack is -1.352(VIOLATED) + Path #12: hold slack is 0.540(MET) -
+
Location Delay Type @@ -74844,7 +76111,7 @@ Logical Resource - Clock cmos1_pclk (rising edge) + Clock hdmi_in_clk (rising edge) 0.000 0.000 @@ -74852,65 +76119,81 @@ - Input external delay - - 1.000 - 1.000 - r - - - - cmos1_data[2] - + hdmi_in_clk + + 0.000 0.000 - 1.000 r - cmos1_data[2] (port) + hdmi_in_clk (port) net (fanout=1) 0.000 - 1.000 - - cmos1_data[2] + 0.000 + + hdmi_in_clk - + - cmos1_data_ibuf[2]/I (GTP_INBUF) + hdmi_in_clk_ibuf/I (GTP_INBUF) - + td 1.211 - 2.211 + 1.211 r - cmos1_data_ibuf[2]/O (GTP_INBUF) + hdmi_in_clk_ibuf/O (GTP_INBUF) + + + + net (fanout=173) + 3.204 + 4.415 + + nt_hdmi_in_clk + + + + + + + r + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/CLK (GTP_DFF_C) + + + + tco + 0.323 + 4.738 + f + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/Q (GTP_DFF_C) net (fanout=1) - 1.091 - 3.302 + 0.464 + 5.202 - nt_cmos1_data[2] + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr1 [1] - r - u_ov5640/cmos1_d_d0[2]/D (GTP_DFF) + f + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[1]/D (GTP_DFF_C)
- +
Location Delay Type @@ -74920,7 +76203,7 @@ Logical Resource - Clock cmos1_pclk (rising edge) + Clock hdmi_in_clk (rising edge) 0.000 0.000 @@ -74928,12 +76211,12 @@ - cmos1_pclk + hdmi_in_clk 0.000 0.000 r - cmos1_pclk (port) + hdmi_in_clk (port) @@ -74941,7 +76224,7 @@ 0.000 0.000 - cmos1_pclk + hdmi_in_clk @@ -74949,7 +76232,7 @@ - cmos1_pclk_ibuf/I (GTP_INBUF) + hdmi_in_clk_ibuf/I (GTP_INBUF) @@ -74957,15 +76240,15 @@ 1.211 1.211 r - cmos1_pclk_ibuf/O (GTP_INBUF) + hdmi_in_clk_ibuf/O (GTP_INBUF) - net (fanout=126) + net (fanout=173) 3.204 4.415 - nt_cmos1_pclk + nt_hdmi_in_clk @@ -74973,7 +76256,7 @@ r - u_ov5640/cmos1_d_d0[2]/CLK (GTP_DFF) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[1]/CLK (GTP_DFF_C) clock pessimism @@ -74994,8 +76277,8 @@ Hold time - 0.039 - 4.654 + 0.047 + 4.662 @@ -75004,27 +76287,27 @@ - -1.352 - 1 + 0.540 + 0 1 - cmos2_data[0] - u_ov5640/cmos2_d_d0[0]/D + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/CLK + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[2]/D - cmos2_pclk - cmos2_pclk + hdmi_in_clk + hdmi_in_clk rise-rise - 4.415 0.000 4.415 + 4.415 0.000 0.000 - 2.302 - 1.211 (52.6%) - 1.091 (47.4%) + 0.787 + 0.323 (41.0%) + 0.464 (59.0%) - Path #4: hold slack is -1.352(VIOLATED) + Path #13: hold slack is 0.540(MET) -
+
Location Delay Type @@ -75034,7 +76317,7 @@ Logical Resource - Clock cmos2_pclk (rising edge) + Clock hdmi_in_clk (rising edge) 0.000 0.000 @@ -75042,65 +76325,81 @@ - Input external delay - - 1.000 - 1.000 - r - - - - cmos2_data[0] - + hdmi_in_clk + + 0.000 0.000 - 1.000 r - cmos2_data[0] (port) + hdmi_in_clk (port) net (fanout=1) 0.000 - 1.000 - - cmos2_data[0] + 0.000 + + hdmi_in_clk - + - cmos2_data_ibuf[0]/I (GTP_INBUF) + hdmi_in_clk_ibuf/I (GTP_INBUF) - + td 1.211 - 2.211 + 1.211 r - cmos2_data_ibuf[0]/O (GTP_INBUF) + hdmi_in_clk_ibuf/O (GTP_INBUF) + + + + net (fanout=173) + 3.204 + 4.415 + + nt_hdmi_in_clk + + + + + + + r + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/CLK (GTP_DFF_C) + + + + tco + 0.323 + 4.738 + f + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/Q (GTP_DFF_C) net (fanout=1) - 1.091 - 3.302 + 0.464 + 5.202 - nt_cmos2_data[0] + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr1 [2] - r - u_ov5640/cmos2_d_d0[0]/D (GTP_DFF) + f + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[2]/D (GTP_DFF_C)
- +
Location Delay Type @@ -75110,7 +76409,7 @@ Logical Resource - Clock cmos2_pclk (rising edge) + Clock hdmi_in_clk (rising edge) 0.000 0.000 @@ -75118,12 +76417,12 @@ - cmos2_pclk + hdmi_in_clk 0.000 0.000 r - cmos2_pclk (port) + hdmi_in_clk (port) @@ -75131,7 +76430,7 @@ 0.000 0.000 - cmos2_pclk + hdmi_in_clk @@ -75139,7 +76438,7 @@ - cmos2_pclk_ibuf/I (GTP_INBUF) + hdmi_in_clk_ibuf/I (GTP_INBUF) @@ -75147,15 +76446,15 @@ 1.211 1.211 r - cmos2_pclk_ibuf/O (GTP_INBUF) + hdmi_in_clk_ibuf/O (GTP_INBUF) - net (fanout=126) + net (fanout=173) 3.204 4.415 - nt_cmos2_pclk + nt_hdmi_in_clk @@ -75163,7 +76462,7 @@ r - u_ov5640/cmos2_d_d0[0]/CLK (GTP_DFF) + u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[2]/CLK (GTP_DFF_C) clock pessimism @@ -75184,8 +76483,8 @@ Hold time - 0.039 - 4.654 + 0.047 + 4.662 @@ -75194,27 +76493,27 @@ - -1.352 - 1 + 0.540 + 0 1 - cmos2_data[1] - u_ov5640/cmos2_d_d0[1]/D + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/CLK + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/D - cmos2_pclk - cmos2_pclk + eth_rxc + eth_rxc rise-rise - 4.415 0.000 - 4.415 + 5.600 + 5.600 0.000 0.000 - 2.302 - 1.211 (52.6%) - 1.091 (47.4%) + 0.787 + 0.323 (41.0%) + 0.464 (59.0%) - Path #5: hold slack is -1.352(VIOLATED) + Path #14: hold slack is 0.540(MET) -
+
Location Delay Type @@ -75224,7 +76523,7 @@ Logical Resource - Clock cmos2_pclk (rising edge) + Clock eth_rxc (rising edge) 0.000 0.000 @@ -75232,96 +76531,68 @@ - Input external delay - - 1.000 - 1.000 - r - - - - cmos2_data[1] - + eth_rxc + + 0.000 0.000 - 1.000 r - cmos2_data[1] (port) + eth_rxc (port) net (fanout=1) 0.000 - 1.000 - - cmos2_data[1] + 0.000 + + eth_rxc - + - cmos2_data_ibuf[1]/I (GTP_INBUF) + eth_rxc_ibuf/I (GTP_INBUF) - + td 1.211 - 2.211 + 1.211 r - cmos2_data_ibuf[1]/O (GTP_INBUF) + eth_rxc_ibuf/O (GTP_INBUF) - net (fanout=1) - 1.091 - 3.302 - - nt_cmos2_data[1] + net (fanout=2) + 1.180 + 2.391 + + nt_eth_rxc - - + - r - u_ov5640/cmos2_d_d0[1]/D (GTP_DFF) - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock cmos2_pclk (rising edge) - 0.000 - 0.000 - r + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKIN (GTP_IOCLKDELAY) - cmos2_pclk - 0.000 - 0.000 + td + 0.549 + 2.940 r - cmos2_pclk (port) + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKOUT (GTP_IOCLKDELAY) net (fanout=1) - 0.000 - 0.000 + 0.464 + 3.404 - cmos2_pclk + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf @@ -75329,23 +76600,23 @@ - cmos2_pclk_ibuf/I (GTP_INBUF) + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKIN (GTP_CLKBUFG) td - 1.211 - 1.211 + 0.000 + 3.404 r - cmos2_pclk_ibuf/O (GTP_INBUF) + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKOUT (GTP_CLKBUFG) - net (fanout=126) - 3.204 - 4.415 + net (fanout=1988) + 2.196 + 5.600 - nt_cmos2_pclk + gmii_clk @@ -75353,58 +76624,36 @@ r - u_ov5640/cmos2_d_d0[1]/CLK (GTP_DFF) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/CLK (GTP_DFF_C) - clock pessimism - - 0.000 - 4.415 - - + + tco + 0.323 + 5.923 + f + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/Q (GTP_DFF_C) - clock uncertainty - - 0.200 - 4.615 - + net (fanout=1) + 0.464 + 6.387 + + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wptr [0] - Hold time + - 0.039 - 4.654 + f + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/D (GTP_DFF_C)
-
-
- - -1.352 - 1 - 1 - cmos2_data[2] - u_ov5640/cmos2_d_d0[2]/D - - cmos2_pclk - cmos2_pclk - rise-rise - 4.415 - 0.000 - 4.415 - 0.000 - 0.000 - 2.302 - 1.211 (52.6%) - 1.091 (47.4%) - - Path #6: hold slack is -1.352(VIOLATED) - +
Location Delay Type @@ -75414,7 +76663,7 @@ Logical Resource - Clock cmos2_pclk (rising edge) + Clock eth_rxc (rising edge) 0.000 0.000 @@ -75422,96 +76671,68 @@ - Input external delay - - 1.000 - 1.000 - r - - - - cmos2_data[2] - + eth_rxc + + 0.000 0.000 - 1.000 r - cmos2_data[2] (port) + eth_rxc (port) net (fanout=1) 0.000 - 1.000 - - cmos2_data[2] + 0.000 + + eth_rxc - + - cmos2_data_ibuf[2]/I (GTP_INBUF) + eth_rxc_ibuf/I (GTP_INBUF) - + td 1.211 - 2.211 + 1.211 r - cmos2_data_ibuf[2]/O (GTP_INBUF) + eth_rxc_ibuf/O (GTP_INBUF) - net (fanout=1) - 1.091 - 3.302 - - nt_cmos2_data[2] + net (fanout=2) + 1.180 + 2.391 + + nt_eth_rxc - - + - r - u_ov5640/cmos2_d_d0[2]/D (GTP_DFF) - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock cmos2_pclk (rising edge) - 0.000 - 0.000 - r + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKIN (GTP_IOCLKDELAY) - cmos2_pclk - 0.000 - 0.000 + td + 0.549 + 2.940 r - cmos2_pclk (port) + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKOUT (GTP_IOCLKDELAY) net (fanout=1) - 0.000 - 0.000 + 0.464 + 3.404 - cmos2_pclk + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf @@ -75519,23 +76740,23 @@ - cmos2_pclk_ibuf/I (GTP_INBUF) + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKIN (GTP_CLKBUFG) td - 1.211 - 1.211 + 0.000 + 3.404 r - cmos2_pclk_ibuf/O (GTP_INBUF) + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKOUT (GTP_CLKBUFG) - net (fanout=126) - 3.204 - 4.415 + net (fanout=1988) + 2.196 + 5.600 - nt_cmos2_pclk + gmii_clk @@ -75543,13 +76764,13 @@ r - u_ov5640/cmos2_d_d0[2]/CLK (GTP_DFF) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/CLK (GTP_DFF_C) clock pessimism 0.000 - 4.415 + 5.600 @@ -75557,15 +76778,15 @@ clock uncertainty 0.200 - 4.615 + 5.800 Hold time - 0.039 - 4.654 + 0.047 + 5.847 @@ -75574,27 +76795,27 @@ - 0.453 + 0.540 0 1 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[0]/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_0/DI + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/CLK + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/D - ddrphy_clkin - ddrphy_clkin + eth_rxc + eth_rxc rise-rise 0.000 - 9.059 - 9.059 + 5.600 + 5.600 0.000 0.000 0.787 0.323 (41.0%) 0.464 (59.0%) - Path #7: hold slack is 0.453(MET) + Path #15: hold slack is 0.540(MET) -
+
Location Delay Type @@ -75604,7 +76825,7 @@ Logical Resource - Clock ddrphy_clkin (rising edge) + Clock eth_rxc (rising edge) 0.000 0.000 @@ -75612,12 +76833,12 @@ - clk + eth_rxc 0.000 0.000 r - clk (port) + eth_rxc (port) @@ -75625,7 +76846,7 @@ 0.000 0.000 - clk + eth_rxc @@ -75633,7 +76854,7 @@ - clk_ibuf/I (GTP_INBUF) + eth_rxc_ibuf/I (GTP_INBUF) @@ -75641,63 +76862,15 @@ 1.211 1.211 r - clk_ibuf/O (GTP_INBUF) - - - - net (fanout=1) - 1.091 - 2.302 - - nt_clk + eth_rxc_ibuf/O (GTP_INBUF) - - - - - u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) - - - - td - 0.089 + net (fanout=2) + 1.180 2.391 - r - u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - - - - net (fanout=851) - 1.976 - 4.367 - - zoom_clk - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - - - - td - 0.000 - 4.367 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - - - - net (fanout=71) - 0.847 - 5.214 - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + nt_eth_rxc @@ -75705,23 +76878,23 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKIN (GTP_IOCLKDELAY) td - 0.094 - 5.308 + 0.549 + 2.940 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKOUT (GTP_IOCLKDELAY) - net (fanout=3) - 0.605 - 5.913 + net (fanout=1) + 0.464 + 3.404 - u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf @@ -75729,23 +76902,23 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKIN (GTP_CLKBUFG) td 0.000 - 5.913 + 3.404 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKOUT (GTP_CLKBUFG) - net (fanout=5817) - 3.146 - 9.059 + net (fanout=1988) + 2.196 + 5.600 - u_axi_ddr_top/clk + gmii_clk @@ -75753,23 +76926,23 @@ r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[0]/CLK (GTP_DFF_C) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/CLK (GTP_DFF_C) tco 0.323 - 9.382 + 5.923 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[0]/Q (GTP_DFF_C) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/Q (GTP_DFF_C) net (fanout=1) 0.464 - 9.846 + 6.387 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/rid [0] + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wptr [1] @@ -75777,12 +76950,12 @@ f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_0/DI (GTP_RAM32X1DP) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/D (GTP_DFF_C)
- +
Location Delay Type @@ -75792,7 +76965,7 @@ Logical Resource - Clock ddrphy_clkin (rising edge) + Clock eth_rxc (rising edge) 0.000 0.000 @@ -75800,12 +76973,12 @@ - clk + eth_rxc 0.000 0.000 r - clk (port) + eth_rxc (port) @@ -75813,7 +76986,7 @@ 0.000 0.000 - clk + eth_rxc @@ -75821,7 +76994,7 @@ - clk_ibuf/I (GTP_INBUF) + eth_rxc_ibuf/I (GTP_INBUF) @@ -75829,63 +77002,15 @@ 1.211 1.211 r - clk_ibuf/O (GTP_INBUF) - - - - net (fanout=1) - 1.091 - 2.302 - - nt_clk + eth_rxc_ibuf/O (GTP_INBUF) - - - - - u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) - - - - td - 0.089 + net (fanout=2) + 1.180 2.391 - r - u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - - - - net (fanout=851) - 1.976 - 4.367 - - zoom_clk - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - - - - td - 0.000 - 4.367 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - - - net (fanout=71) - 0.847 - 5.214 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + nt_eth_rxc @@ -75893,23 +77018,23 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKIN (GTP_IOCLKDELAY) td - 0.094 - 5.308 + 0.549 + 2.940 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKOUT (GTP_IOCLKDELAY) - net (fanout=3) - 0.605 - 5.913 + net (fanout=1) + 0.464 + 3.404 - u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf @@ -75917,23 +77042,23 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKIN (GTP_CLKBUFG) td 0.000 - 5.913 + 3.404 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKOUT (GTP_CLKBUFG) - net (fanout=5817) - 3.146 - 9.059 + net (fanout=1988) + 2.196 + 5.600 - u_axi_ddr_top/clk + gmii_clk @@ -75941,29 +77066,29 @@ r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_0/WCLK (GTP_RAM32X1DP) + udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/CLK (GTP_DFF_C) clock pessimism 0.000 - 9.059 + 5.600 clock uncertainty - 0.000 - 9.059 + 0.200 + 5.800 Hold time - 0.334 - 9.393 + 0.047 + 5.847 @@ -75972,27 +77097,27 @@ - 0.453 + 0.649 0 1 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[1]/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/DI + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[5]/CLK + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/DIA[5] - ddrphy_clkin - ddrphy_clkin + clk_50m + clk_50m rise-rise - 0.000 - 9.059 - 9.059 + 0.515 + 5.523 + 6.038 0.000 0.000 - 0.787 - 0.323 (41.0%) - 0.464 (59.0%) + 1.301 + 0.323 (24.8%) + 0.978 (75.2%) - Path #8: hold slack is 0.453(MET) + Path #16: hold slack is 0.649(MET) -
+
Location Delay Type @@ -76002,7 +77127,7 @@ Logical Resource - Clock ddrphy_clkin (rising edge) + Clock clk_50m (rising edge) 0.000 0.000 @@ -76057,93 +77182,21 @@ u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) - - - td - 0.089 - 2.391 - r - u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - - - - net (fanout=851) - 1.976 - 4.367 - - zoom_clk - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - - - - td - 0.000 - 4.367 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - - - - net (fanout=71) - 0.847 - 5.214 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 - 5.308 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - - - - net (fanout=3) - 0.605 - 5.913 - - u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) - - - - td - 0.000 - 5.913 + 2.396 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=5817) - 3.146 - 9.059 + net (fanout=2825) + 3.127 + 5.523 - u_axi_ddr_top/clk + rd3_clk @@ -76151,23 +77204,23 @@ r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[1]/CLK (GTP_DFF_C) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[5]/CLK (GTP_DFF) tco 0.323 - 9.382 + 5.846 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[1]/Q (GTP_DFF_C) + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[5]/Q (GTP_DFF) net (fanout=1) - 0.464 - 9.846 + 0.978 + 6.824 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/rid [1] + rd3_ddr_addr[5] @@ -76175,12 +77228,12 @@ f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/DI (GTP_RAM32X1DP) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/DIA[5] (GTP_DRM18K)
- +
Location Delay Type @@ -76190,7 +77243,7 @@ Logical Resource - Clock ddrphy_clkin (rising edge) + Clock clk_50m (rising edge) 0.000 0.000 @@ -76245,93 +77298,21 @@ u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) - - - td - 0.089 - 2.391 - r - u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - - - - net (fanout=851) - 1.976 - 4.367 - - zoom_clk - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - - - - td - 0.000 - 4.367 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - - - - net (fanout=71) - 0.847 - 5.214 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 - 5.308 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - - - - net (fanout=3) - 0.605 - 5.913 - - u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) - - - - td - 0.000 - 5.913 + 2.396 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=5817) - 3.146 - 9.059 + net (fanout=2825) + 3.642 + 6.038 - u_axi_ddr_top/clk + rd3_clk @@ -76339,13 +77320,13 @@ r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_1/WCLK (GTP_RAM32X1DP) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (GTP_DRM18K) clock pessimism 0.000 - 9.059 + 6.038 @@ -76353,15 +77334,15 @@ clock uncertainty 0.000 - 9.059 + 6.038 Hold time - 0.334 - 9.393 + 0.137 + 6.175 @@ -76370,27 +77351,27 @@ - 0.453 + 0.649 0 1 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[2]/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_2/DI + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[6]/CLK + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/DIA[6] - ddrphy_clkin - ddrphy_clkin + clk_50m + clk_50m rise-rise + 0.515 + 5.523 + 6.038 0.000 - 9.059 - 9.059 0.000 - 0.000 - 0.787 - 0.323 (41.0%) - 0.464 (59.0%) + 1.301 + 0.323 (24.8%) + 0.978 (75.2%) - Path #9: hold slack is 0.453(MET) + Path #17: hold slack is 0.649(MET) -
+
Location Delay Type @@ -76400,7 +77381,7 @@ Logical Resource - Clock ddrphy_clkin (rising edge) + Clock clk_50m (rising edge) 0.000 0.000 @@ -76458,42 +77439,86 @@ td - 0.089 - 2.391 + 0.094 + 2.396 r - u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=851) - 1.976 - 4.367 + net (fanout=2825) + 3.127 + 5.523 - zoom_clk + rd3_clk + r + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[6]/CLK (GTP_DFF) + + + + tco + 0.323 + 5.846 + f + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[6]/Q (GTP_DFF) + + + + net (fanout=1) + 0.978 + 6.824 + + rd3_ddr_addr[6] + + + + + + + f + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/DIA[6] (GTP_DRM18K) + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_50m (rising edge) + + 0.000 + 0.000 + r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + clk - td 0.000 - 4.367 + 0.000 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + clk (port) - net (fanout=71) - 0.847 - 5.214 + net (fanout=1) + 0.000 + 0.000 - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + clk @@ -76501,23 +77526,23 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) + clk_ibuf/I (GTP_INBUF) td - 0.094 - 5.308 + 1.211 + 1.211 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + clk_ibuf/O (GTP_INBUF) - net (fanout=3) - 0.605 - 5.913 + net (fanout=1) + 1.091 + 2.302 - u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + nt_clk @@ -76525,23 +77550,23 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td - 0.000 - 5.913 + 0.094 + 2.396 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=5817) - 3.146 - 9.059 + net (fanout=2825) + 3.642 + 6.038 - u_axi_ddr_top/clk + rd3_clk @@ -76549,36 +77574,58 @@ r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[2]/CLK (GTP_DFF_C) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (GTP_DRM18K) - - tco - 0.323 - 9.382 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/o_rid[2]/Q (GTP_DFF_C) + clock pessimism + + 0.000 + 6.038 + + + clock uncertainty + + 0.000 + 6.038 + - net (fanout=1) - 0.464 - 9.846 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/rid [2] - + Hold time + 0.137 + 6.175 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_2/DI (GTP_RAM32X1DP)
+
+
+ + 0.649 + 0 + 1 + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[7]/CLK + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/DIA[7] + + clk_50m + clk_50m + rise-rise + 0.515 + 5.523 + 6.038 + 0.000 + 0.000 + 1.301 + 0.323 (24.8%) + 0.978 (75.2%) + + Path #18: hold slack is 0.649(MET) - +
Location Delay Type @@ -76588,7 +77635,7 @@ Logical Resource - Clock ddrphy_clkin (rising edge) + Clock clk_50m (rising edge) 0.000 0.000 @@ -76646,42 +77693,86 @@ td - 0.089 - 2.391 + 0.094 + 2.396 r - u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=851) - 1.976 - 4.367 + net (fanout=2825) + 3.127 + 5.523 - zoom_clk + rd3_clk + r + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[7]/CLK (GTP_DFF) + + + + tco + 0.323 + 5.846 + f + u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[7]/Q (GTP_DFF) + + + + net (fanout=1) + 0.978 + 6.824 + + rd3_ddr_addr[7] + + + + + + + f + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/DIA[7] (GTP_DRM18K) + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_50m (rising edge) + + 0.000 + 0.000 + r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + clk - td 0.000 - 4.367 + 0.000 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + clk (port) - net (fanout=71) - 0.847 - 5.214 + net (fanout=1) + 0.000 + 0.000 - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + clk @@ -76689,23 +77780,23 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) + clk_ibuf/I (GTP_INBUF) td - 0.094 - 5.308 + 1.211 + 1.211 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + clk_ibuf/O (GTP_INBUF) - net (fanout=3) - 0.605 - 5.913 + net (fanout=1) + 1.091 + 2.302 - u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + nt_clk @@ -76713,23 +77804,23 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td - 0.000 - 5.913 + 0.094 + 2.396 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=5817) - 3.146 - 9.059 + net (fanout=2825) + 3.642 + 6.038 - u_axi_ddr_top/clk + rd3_clk @@ -76737,13 +77828,13 @@ r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/ipsxb_distributed_fifo/u_ipsxb_distributed_fifo_distributed_fifo_v1_0/ipsxb_distributed_sdpram_distributed_fifo_v1_0/mem_2/WCLK (GTP_RAM32X1DP) + u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (GTP_DRM18K) clock pessimism 0.000 - 9.059 + 6.038 @@ -76751,15 +77842,15 @@ clock uncertainty 0.000 - 9.059 + 6.038 Hold time - 0.334 - 9.393 + 0.137 + 6.175 @@ -76768,27 +77859,27 @@ - 0.540 + 0.650 0 1 - param_manager_inst/clk_ms/CLK - param_manager_inst/key_debounce_key_left/clk_ms_ff0/D + udp_osd_inst/char_buf_writer_inst/ram_din[0]/CLK + udp_osd_inst/char_ram/U_ipml_sdpram_async_ram2048x8_2clk/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/DIA[0] - eth_rxc - eth_rxc + clk_720p60Hz + clk_720p60Hz rise-rise - 0.000 - 5.600 - 5.600 + 0.514 + 8.070 + 8.584 0.000 0.000 - 0.787 - 0.323 (41.0%) - 0.464 (59.0%) + 1.301 + 0.323 (24.8%) + 0.978 (75.2%) - Path #10: hold slack is 0.540(MET) + Path #19: hold slack is 0.650(MET) -
+
Location Delay Type @@ -76798,7 +77889,7 @@ Logical Resource - Clock eth_rxc (rising edge) + Clock clk_720p60Hz (rising edge) 0.000 0.000 @@ -76806,12 +77897,12 @@ - eth_rxc + clk 0.000 0.000 r - eth_rxc (port) + clk (port) @@ -76819,7 +77910,7 @@ 0.000 0.000 - eth_rxc + clk @@ -76827,7 +77918,7 @@ - eth_rxc_ibuf/I (GTP_INBUF) + clk_ibuf/I (GTP_INBUF) @@ -76835,15 +77926,15 @@ 1.211 1.211 r - eth_rxc_ibuf/O (GTP_INBUF) + clk_ibuf/O (GTP_INBUF) - net (fanout=2) - 1.180 - 2.391 + net (fanout=1) + 1.091 + 2.302 - nt_eth_rxc + nt_clk @@ -76851,23 +77942,23 @@ - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKIN (GTP_IOCLKDELAY) + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td - 0.549 - 2.940 + 0.094 + 2.396 r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKOUT (GTP_IOCLKDELAY) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=1) - 0.464 - 3.404 + net (fanout=2825) + 3.127 + 5.523 - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf + rd3_clk @@ -76875,23 +77966,23 @@ - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKIN (GTP_CLKBUFG) + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) td - 0.000 - 3.404 + 0.089 + 5.612 r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKOUT (GTP_CLKBUFG) + U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=1988) - 2.196 - 5.600 + net (fanout=1758) + 2.458 + 8.070 - gmii_clk + nt_pix_clk @@ -76899,23 +77990,23 @@ r - param_manager_inst/clk_ms/CLK (GTP_DFF_R) + udp_osd_inst/char_buf_writer_inst/ram_din[0]/CLK (GTP_DFF_RE) tco 0.323 - 5.923 + 8.393 f - param_manager_inst/clk_ms/Q (GTP_DFF_R) + udp_osd_inst/char_buf_writer_inst/ram_din[0]/Q (GTP_DFF_RE) net (fanout=1) - 0.464 - 6.387 + 0.978 + 9.371 - param_manager_inst/clk_ms + udp_osd_inst/ram_din [0] @@ -76923,12 +78014,12 @@ f - param_manager_inst/key_debounce_key_left/clk_ms_ff0/D (GTP_DFF) + udp_osd_inst/char_ram/U_ipml_sdpram_async_ram2048x8_2clk/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/DIA[0] (GTP_DRM18K)
- +
Location Delay Type @@ -76938,7 +78029,7 @@ Logical Resource - Clock eth_rxc (rising edge) + Clock clk_720p60Hz (rising edge) 0.000 0.000 @@ -76946,12 +78037,12 @@ - eth_rxc + clk 0.000 0.000 r - eth_rxc (port) + clk (port) @@ -76959,7 +78050,7 @@ 0.000 0.000 - eth_rxc + clk @@ -76967,7 +78058,7 @@ - eth_rxc_ibuf/I (GTP_INBUF) + clk_ibuf/I (GTP_INBUF) @@ -76975,15 +78066,15 @@ 1.211 1.211 r - eth_rxc_ibuf/O (GTP_INBUF) + clk_ibuf/O (GTP_INBUF) - net (fanout=2) - 1.180 - 2.391 + net (fanout=1) + 1.091 + 2.302 - nt_eth_rxc + nt_clk @@ -76991,23 +78082,23 @@ - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKIN (GTP_IOCLKDELAY) + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td - 0.549 - 2.940 + 0.094 + 2.396 r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKOUT (GTP_IOCLKDELAY) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=1) - 0.464 - 3.404 + net (fanout=2825) + 3.127 + 5.523 - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf + rd3_clk @@ -77015,23 +78106,23 @@ - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKIN (GTP_CLKBUFG) + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) td - 0.000 - 3.404 + 0.089 + 5.612 r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKOUT (GTP_CLKBUFG) + U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=1988) - 2.196 - 5.600 + net (fanout=1758) + 2.972 + 8.584 - gmii_clk + nt_pix_clk @@ -77039,29 +78130,29 @@ r - param_manager_inst/key_debounce_key_left/clk_ms_ff0/CLK (GTP_DFF) + udp_osd_inst/char_ram/U_ipml_sdpram_async_ram2048x8_2clk/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (GTP_DRM18K) clock pessimism 0.000 - 5.600 + 8.584 clock uncertainty - 0.200 - 5.800 + 0.000 + 8.584 Hold time - 0.047 - 5.847 + 0.137 + 8.721 @@ -77070,27 +78161,27 @@ - 0.540 + 0.650 0 1 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/CLK - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[0]/D + udp_osd_inst/char_buf_writer_inst/ram_din[1]/CLK + udp_osd_inst/char_ram/U_ipml_sdpram_async_ram2048x8_2clk/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/DIA[1] - hdmi_in_clk - hdmi_in_clk + clk_720p60Hz + clk_720p60Hz rise-rise - 0.000 - 4.415 - 4.415 + 0.514 + 8.070 + 8.584 0.000 0.000 - 0.787 - 0.323 (41.0%) - 0.464 (59.0%) + 1.301 + 0.323 (24.8%) + 0.978 (75.2%) - Path #11: hold slack is 0.540(MET) + Path #20: hold slack is 0.650(MET) -
+
Location Delay Type @@ -77100,7 +78191,7 @@ Logical Resource - Clock hdmi_in_clk (rising edge) + Clock clk_720p60Hz (rising edge) 0.000 0.000 @@ -77108,12 +78199,12 @@ - hdmi_in_clk + clk 0.000 0.000 r - hdmi_in_clk (port) + clk (port) @@ -77121,7 +78212,7 @@ 0.000 0.000 - hdmi_in_clk + clk @@ -77129,7 +78220,7 @@ - hdmi_in_clk_ibuf/I (GTP_INBUF) + clk_ibuf/I (GTP_INBUF) @@ -77137,83 +78228,39 @@ 1.211 1.211 r - hdmi_in_clk_ibuf/O (GTP_INBUF) + clk_ibuf/O (GTP_INBUF) - net (fanout=173) - 3.204 - 4.415 + net (fanout=1) + 1.091 + 2.302 - nt_hdmi_in_clk + nt_clk - r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/CLK (GTP_DFF_C) - - - - tco - 0.323 - 4.738 - f - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[0]/Q (GTP_DFF_C) - - - - net (fanout=1) - 0.464 - 5.202 - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr1 [0] - - - - - - - f - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[0]/D (GTP_DFF_C) - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock hdmi_in_clk (rising edge) - - 0.000 - 0.000 - r + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) - hdmi_in_clk - 0.000 - 0.000 + td + 0.094 + 2.396 r - hdmi_in_clk (port) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=1) - 0.000 - 0.000 + net (fanout=2825) + 3.127 + 5.523 - hdmi_in_clk + rd3_clk @@ -77221,23 +78268,23 @@ - hdmi_in_clk_ibuf/I (GTP_INBUF) + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) td - 1.211 - 1.211 + 0.089 + 5.612 r - hdmi_in_clk_ibuf/O (GTP_INBUF) + U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=173) - 3.204 - 4.415 + net (fanout=1758) + 2.458 + 8.070 - nt_hdmi_in_clk + nt_pix_clk @@ -77245,58 +78292,36 @@ r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[0]/CLK (GTP_DFF_C) + udp_osd_inst/char_buf_writer_inst/ram_din[1]/CLK (GTP_DFF_RE) - clock pessimism - - 0.000 - 4.415 - - + + tco + 0.323 + 8.393 + f + udp_osd_inst/char_buf_writer_inst/ram_din[1]/Q (GTP_DFF_RE) - clock uncertainty - - 0.200 - 4.615 - + net (fanout=1) + 0.978 + 9.371 + + udp_osd_inst/ram_din [1] - Hold time + - 0.047 - 4.662 + f + udp_osd_inst/char_ram/U_ipml_sdpram_async_ram2048x8_2clk/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/DIA[1] (GTP_DRM18K)
-
-
- - 0.540 - 0 - 1 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/CLK - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[1]/D - - hdmi_in_clk - hdmi_in_clk - rise-rise - 0.000 - 4.415 - 4.415 - 0.000 - 0.000 - 0.787 - 0.323 (41.0%) - 0.464 (59.0%) - - Path #12: hold slack is 0.540(MET) - +
Location Delay Type @@ -77306,7 +78331,7 @@ Logical Resource - Clock hdmi_in_clk (rising edge) + Clock clk_720p60Hz (rising edge) 0.000 0.000 @@ -77314,12 +78339,12 @@ - hdmi_in_clk + clk 0.000 0.000 r - hdmi_in_clk (port) + clk (port) @@ -77327,7 +78352,7 @@ 0.000 0.000 - hdmi_in_clk + clk @@ -77335,7 +78360,7 @@ - hdmi_in_clk_ibuf/I (GTP_INBUF) + clk_ibuf/I (GTP_INBUF) @@ -77343,83 +78368,39 @@ 1.211 1.211 r - hdmi_in_clk_ibuf/O (GTP_INBUF) - - - - net (fanout=173) - 3.204 - 4.415 - - nt_hdmi_in_clk - - - - - - - r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/CLK (GTP_DFF_C) - - - - tco - 0.323 - 4.738 - f - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[1]/Q (GTP_DFF_C) + clk_ibuf/O (GTP_INBUF) net (fanout=1) - 0.464 - 5.202 - - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr1 [1] - - - - - + 1.091 + 2.302 - f - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[1]/D (GTP_DFF_C) + nt_clk -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - Clock hdmi_in_clk (rising edge) + + - 0.000 - 0.000 - r + + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) - hdmi_in_clk - 0.000 - 0.000 + td + 0.094 + 2.396 r - hdmi_in_clk (port) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=1) - 0.000 - 0.000 + net (fanout=2825) + 3.127 + 5.523 - hdmi_in_clk + rd3_clk @@ -77427,23 +78408,23 @@ - hdmi_in_clk_ibuf/I (GTP_INBUF) + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) td - 1.211 - 1.211 + 0.089 + 5.612 r - hdmi_in_clk_ibuf/O (GTP_INBUF) + U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=173) - 3.204 - 4.415 + net (fanout=1758) + 2.972 + 8.584 - nt_hdmi_in_clk + nt_pix_clk @@ -77451,29 +78432,29 @@ r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[1]/CLK (GTP_DFF_C) + udp_osd_inst/char_ram/U_ipml_sdpram_async_ram2048x8_2clk/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (GTP_DRM18K) clock pessimism 0.000 - 4.415 + 8.584 clock uncertainty - 0.200 - 4.615 + 0.000 + 8.584 Hold time - 0.047 - 4.662 + 0.137 + 8.721 @@ -77482,27 +78463,27 @@ - 0.540 + 0.650 0 1 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/CLK - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[2]/D + udp_osd_inst/char_buf_writer_inst/ram_din[2]/CLK + udp_osd_inst/char_ram/U_ipml_sdpram_async_ram2048x8_2clk/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/DIA[2] - hdmi_in_clk - hdmi_in_clk + clk_720p60Hz + clk_720p60Hz rise-rise - 0.000 - 4.415 - 4.415 + 0.514 + 8.070 + 8.584 0.000 0.000 - 0.787 - 0.323 (41.0%) - 0.464 (59.0%) + 1.301 + 0.323 (24.8%) + 0.978 (75.2%) - Path #13: hold slack is 0.540(MET) + Path #21: hold slack is 0.650(MET) -
+
Location Delay Type @@ -77512,7 +78493,7 @@ Logical Resource - Clock hdmi_in_clk (rising edge) + Clock clk_720p60Hz (rising edge) 0.000 0.000 @@ -77520,12 +78501,12 @@ - hdmi_in_clk + clk 0.000 0.000 r - hdmi_in_clk (port) + clk (port) @@ -77533,7 +78514,7 @@ 0.000 0.000 - hdmi_in_clk + clk @@ -77541,7 +78522,7 @@ - hdmi_in_clk_ibuf/I (GTP_INBUF) + clk_ibuf/I (GTP_INBUF) @@ -77549,39 +78530,87 @@ 1.211 1.211 r - hdmi_in_clk_ibuf/O (GTP_INBUF) + clk_ibuf/O (GTP_INBUF) - net (fanout=173) - 3.204 - 4.415 + net (fanout=1) + 1.091 + 2.302 - nt_hdmi_in_clk + nt_clk + + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.094 + 2.396 r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/CLK (GTP_DFF_C) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + + + + net (fanout=2825) + 3.127 + 5.523 + + rd3_clk + + + + + + + + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.089 + 5.612 + r + U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + + + + net (fanout=1758) + 2.458 + 8.070 + + nt_pix_clk + + + + + + + r + udp_osd_inst/char_buf_writer_inst/ram_din[2]/CLK (GTP_DFF_RE) tco 0.323 - 4.738 + 8.393 f - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wrptr1[2]/Q (GTP_DFF_C) + udp_osd_inst/char_buf_writer_inst/ram_din[2]/Q (GTP_DFF_RE) net (fanout=1) - 0.464 - 5.202 + 0.978 + 9.371 - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr1 [2] + udp_osd_inst/ram_din [2] @@ -77589,12 +78618,12 @@ f - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[2]/D (GTP_DFF_C) + udp_osd_inst/char_ram/U_ipml_sdpram_async_ram2048x8_2clk/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/DIA[2] (GTP_DRM18K)
- +
Location Delay Type @@ -77604,7 +78633,7 @@ Logical Resource - Clock hdmi_in_clk (rising edge) + Clock clk_720p60Hz (rising edge) 0.000 0.000 @@ -77612,12 +78641,12 @@ - hdmi_in_clk + clk 0.000 0.000 r - hdmi_in_clk (port) + clk (port) @@ -77625,7 +78654,7 @@ 0.000 0.000 - hdmi_in_clk + clk @@ -77633,7 +78662,7 @@ - hdmi_in_clk_ibuf/I (GTP_INBUF) + clk_ibuf/I (GTP_INBUF) @@ -77641,45 +78670,93 @@ 1.211 1.211 r - hdmi_in_clk_ibuf/O (GTP_INBUF) + clk_ibuf/O (GTP_INBUF) - net (fanout=173) - 3.204 - 4.415 + net (fanout=1) + 1.091 + 2.302 - nt_hdmi_in_clk + nt_clk + + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.094 + 2.396 r - u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/wrptr2[2]/CLK (GTP_DFF_C) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + + + + net (fanout=2825) + 3.127 + 5.523 + + rd3_clk + + + + + + + + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.089 + 5.612 + r + U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + + + + net (fanout=1758) + 2.972 + 8.584 + + nt_pix_clk + + + + + + + r + udp_osd_inst/char_ram/U_ipml_sdpram_async_ram2048x8_2clk/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (GTP_DRM18K) clock pessimism 0.000 - 4.415 + 8.584 clock uncertainty - 0.200 - 4.615 + 0.000 + 8.584 Hold time - 0.047 - 4.662 + 0.137 + 8.721 @@ -77688,27 +78765,27 @@ - 0.540 + 0.656 0 1 - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/CLK - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/D + u_zoom_image/imag_addr1[0]/CLK + u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/DIA[0] - eth_rxc - eth_rxc + clk_1080p60Hz + clk_1080p60Hz rise-rise - 0.000 - 5.600 - 5.600 + 0.514 + 7.588 + 8.102 0.000 0.000 - 0.787 - 0.323 (41.0%) - 0.464 (59.0%) + 1.301 + 0.323 (24.8%) + 0.978 (75.2%) - Path #14: hold slack is 0.540(MET) + Path #22: hold slack is 0.656(MET) -
+
Location Delay Type @@ -77718,7 +78795,7 @@ Logical Resource - Clock eth_rxc (rising edge) + Clock clk_1080p60Hz (rising edge) 0.000 0.000 @@ -77726,12 +78803,12 @@ - eth_rxc + clk 0.000 0.000 r - eth_rxc (port) + clk (port) @@ -77739,7 +78816,7 @@ 0.000 0.000 - eth_rxc + clk @@ -77747,7 +78824,7 @@ - eth_rxc_ibuf/I (GTP_INBUF) + clk_ibuf/I (GTP_INBUF) @@ -77755,15 +78832,15 @@ 1.211 1.211 r - eth_rxc_ibuf/O (GTP_INBUF) + clk_ibuf/O (GTP_INBUF) - net (fanout=2) - 1.180 - 2.391 + net (fanout=1) + 1.091 + 2.302 - nt_eth_rxc + nt_clk @@ -77771,23 +78848,23 @@ - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKIN (GTP_IOCLKDELAY) + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td - 0.549 - 2.940 + 0.094 + 2.396 r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKOUT (GTP_IOCLKDELAY) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=1) - 0.464 - 3.404 + net (fanout=2825) + 3.127 + 5.523 - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf + rd3_clk @@ -77795,23 +78872,23 @@ - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKIN (GTP_CLKBUFG) + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) td - 0.000 - 3.404 + 0.094 + 5.617 r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKOUT (GTP_CLKBUFG) + U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=1988) - 2.196 - 5.600 + net (fanout=844) + 1.971 + 7.588 - gmii_clk + zoom_clk @@ -77819,23 +78896,23 @@ r - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/CLK (GTP_DFF_C) + u_zoom_image/imag_addr1[0]/CLK (GTP_DFF) tco 0.323 - 5.923 + 7.911 f - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[0]/Q (GTP_DFF_C) + u_zoom_image/imag_addr1[0]/Q (GTP_DFF) net (fanout=1) - 0.464 - 6.387 + 0.978 + 8.889 - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wptr [0] + zoom_image_addr[0] @@ -77843,12 +78920,12 @@ f - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/D (GTP_DFF_C) + u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/DIA[0] (GTP_DRM9K)
- +
Location Delay Type @@ -77858,7 +78935,7 @@ Logical Resource - Clock eth_rxc (rising edge) + Clock clk_1080p60Hz (rising edge) 0.000 0.000 @@ -77866,12 +78943,12 @@ - eth_rxc + clk 0.000 0.000 r - eth_rxc (port) + clk (port) @@ -77879,7 +78956,7 @@ 0.000 0.000 - eth_rxc + clk @@ -77887,7 +78964,7 @@ - eth_rxc_ibuf/I (GTP_INBUF) + clk_ibuf/I (GTP_INBUF) @@ -77895,15 +78972,15 @@ 1.211 1.211 r - eth_rxc_ibuf/O (GTP_INBUF) + clk_ibuf/O (GTP_INBUF) - net (fanout=2) - 1.180 - 2.391 + net (fanout=1) + 1.091 + 2.302 - nt_eth_rxc + nt_clk @@ -77911,23 +78988,23 @@ - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKIN (GTP_IOCLKDELAY) + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td - 0.549 - 2.940 + 0.094 + 2.396 r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKOUT (GTP_IOCLKDELAY) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=1) - 0.464 - 3.404 + net (fanout=2825) + 3.127 + 5.523 - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf + rd3_clk @@ -77935,23 +79012,23 @@ - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKIN (GTP_CLKBUFG) + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) td - 0.000 - 3.404 + 0.094 + 5.617 r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKOUT (GTP_CLKBUFG) + U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=1988) - 2.196 - 5.600 + net (fanout=844) + 2.485 + 8.102 - gmii_clk + zoom_clk @@ -77959,29 +79036,29 @@ r - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[0]/CLK (GTP_DFF_C) + u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/CLKA (GTP_DRM9K) clock pessimism 0.000 - 5.600 + 8.102 clock uncertainty - 0.200 - 5.800 + 0.000 + 8.102 Hold time - 0.047 - 5.847 + 0.131 + 8.233 @@ -77990,27 +79067,27 @@ - 0.540 + 0.656 0 1 - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/CLK - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/D + u_zoom_image/imag_addr1[1]/CLK + u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/DIA[1] - eth_rxc - eth_rxc + clk_1080p60Hz + clk_1080p60Hz rise-rise - 0.000 - 5.600 - 5.600 + 0.514 + 7.588 + 8.102 0.000 0.000 - 0.787 - 0.323 (41.0%) - 0.464 (59.0%) + 1.301 + 0.323 (24.8%) + 0.978 (75.2%) - Path #15: hold slack is 0.540(MET) + Path #23: hold slack is 0.656(MET) -
+
Location Delay Type @@ -78020,7 +79097,7 @@ Logical Resource - Clock eth_rxc (rising edge) + Clock clk_1080p60Hz (rising edge) 0.000 0.000 @@ -78028,12 +79105,12 @@ - eth_rxc + clk 0.000 0.000 r - eth_rxc (port) + clk (port) @@ -78041,7 +79118,7 @@ 0.000 0.000 - eth_rxc + clk @@ -78049,7 +79126,7 @@ - eth_rxc_ibuf/I (GTP_INBUF) + clk_ibuf/I (GTP_INBUF) @@ -78057,15 +79134,15 @@ 1.211 1.211 r - eth_rxc_ibuf/O (GTP_INBUF) + clk_ibuf/O (GTP_INBUF) - net (fanout=2) - 1.180 - 2.391 + net (fanout=1) + 1.091 + 2.302 - nt_eth_rxc + nt_clk @@ -78073,23 +79150,23 @@ - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKIN (GTP_IOCLKDELAY) + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td - 0.549 - 2.940 + 0.094 + 2.396 r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKOUT (GTP_IOCLKDELAY) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=1) - 0.464 - 3.404 + net (fanout=2825) + 3.127 + 5.523 - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf + rd3_clk @@ -78097,23 +79174,23 @@ - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKIN (GTP_CLKBUFG) + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) td - 0.000 - 3.404 + 0.094 + 5.617 r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKOUT (GTP_CLKBUFG) + U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=1988) - 2.196 - 5.600 + net (fanout=844) + 1.971 + 7.588 - gmii_clk + zoom_clk @@ -78121,23 +79198,23 @@ r - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/CLK (GTP_DFF_C) + u_zoom_image/imag_addr1[1]/CLK (GTP_DFF) tco 0.323 - 5.923 + 7.911 f - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]/Q (GTP_DFF_C) + u_zoom_image/imag_addr1[1]/Q (GTP_DFF) net (fanout=1) - 0.464 - 6.387 + 0.978 + 8.889 - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/wptr [1] + zoom_image_addr[1] @@ -78145,12 +79222,12 @@ f - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/D (GTP_DFF_C) + u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/DIA[1] (GTP_DRM9K)
- +
Location Delay Type @@ -78160,7 +79237,7 @@ Logical Resource - Clock eth_rxc (rising edge) + Clock clk_1080p60Hz (rising edge) 0.000 0.000 @@ -78168,12 +79245,12 @@ - eth_rxc + clk 0.000 0.000 r - eth_rxc (port) + clk (port) @@ -78181,7 +79258,7 @@ 0.000 0.000 - eth_rxc + clk @@ -78189,7 +79266,7 @@ - eth_rxc_ibuf/I (GTP_INBUF) + clk_ibuf/I (GTP_INBUF) @@ -78197,15 +79274,15 @@ 1.211 1.211 r - eth_rxc_ibuf/O (GTP_INBUF) + clk_ibuf/O (GTP_INBUF) - net (fanout=2) - 1.180 - 2.391 + net (fanout=1) + 1.091 + 2.302 - nt_eth_rxc + nt_clk @@ -78213,23 +79290,23 @@ - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKIN (GTP_IOCLKDELAY) + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td - 0.549 - 2.940 + 0.094 + 2.396 r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_clk_delay/CLKOUT (GTP_IOCLKDELAY) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=1) - 0.464 - 3.404 + net (fanout=2825) + 3.127 + 5.523 - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/rgmii_rxc_ibuf + rd3_clk @@ -78237,23 +79314,23 @@ - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKIN (GTP_CLKBUFG) + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) td - 0.000 - 3.404 + 0.094 + 5.617 r - udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/GTP_CLKBUFG_RXSHFT/CLKOUT (GTP_CLKBUFG) + U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=1988) - 2.196 - 5.600 + net (fanout=844) + 2.485 + 8.102 - gmii_clk + zoom_clk @@ -78261,29 +79338,29 @@ r - udp_osd_inst/eth_udp_inst/icmp_async_fifo_2048x8b/U_ipml_fifo_async_fifo_2048x8/U_ipml_fifo_ctrl/ASYN_CTRL.rwptr1[1]/CLK (GTP_DFF_C) + u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/CLKA (GTP_DRM9K) clock pessimism 0.000 - 5.600 + 8.102 clock uncertainty - 0.200 - 5.800 + 0.000 + 8.102 Hold time - 0.047 - 5.847 + 0.131 + 8.233 @@ -78292,27 +79369,27 @@ - 0.650 + 0.656 0 1 - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[5]/CLK - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/DIA[5] + u_zoom_image/imag_addr1[2]/CLK + u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/DIA[2] - clk_50m - clk_50m + clk_1080p60Hz + clk_1080p60Hz rise-rise 0.514 - 5.526 - 6.040 + 7.588 + 8.102 0.000 0.000 1.301 0.323 (24.8%) 0.978 (75.2%) - Path #16: hold slack is 0.650(MET) + Path #24: hold slack is 0.656(MET) -
+
Location Delay Type @@ -78322,7 +79399,7 @@ Logical Resource - Clock clk_50m (rising edge) + Clock clk_1080p60Hz (rising edge) 0.000 0.000 @@ -78387,9 +79464,9 @@ - net (fanout=2827) - 3.130 - 5.526 + net (fanout=2825) + 3.127 + 5.523 rd3_clk @@ -78398,24 +79475,48 @@ + + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.094 + 5.617 r - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[5]/CLK (GTP_DFF) + U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + + + + net (fanout=844) + 1.971 + 7.588 + + zoom_clk + + + + + + + r + u_zoom_image/imag_addr1[2]/CLK (GTP_DFF) tco 0.323 - 5.849 + 7.911 f - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[5]/Q (GTP_DFF) + u_zoom_image/imag_addr1[2]/Q (GTP_DFF) net (fanout=1) 0.978 - 6.827 + 8.889 - rd3_ddr_addr[5] + zoom_image_addr[2] @@ -78423,12 +79524,12 @@ f - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/DIA[5] (GTP_DRM18K) + u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/DIA[2] (GTP_DRM9K)
- +
Location Delay Type @@ -78438,7 +79539,7 @@ Logical Resource - Clock clk_50m (rising edge) + Clock clk_1080p60Hz (rising edge) 0.000 0.000 @@ -78503,9 +79604,9 @@ - net (fanout=2827) - 3.644 - 6.040 + net (fanout=2825) + 3.127 + 5.523 rd3_clk @@ -78514,14 +79615,38 @@ + + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.094 + 5.617 r - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (GTP_DRM18K) + U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + + + + net (fanout=844) + 2.485 + 8.102 + + zoom_clk + + + + + + + r + u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/CLKA (GTP_DRM9K) clock pessimism 0.000 - 6.040 + 8.102 @@ -78529,15 +79654,15 @@ clock uncertainty 0.000 - 6.040 + 8.102 Hold time - 0.137 - 6.177 + 0.131 + 8.233 @@ -78546,27 +79671,27 @@ - 0.650 + 0.740 0 1 - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[6]/CLK - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/DIA[6] + ms72xx_ctl/iic_dri_rx/receiv_data[7]/CLK + ms72xx_ctl/iic_dri_rx/data_out[7]/D - clk_50m - clk_50m + clk_10m + clk_10m rise-rise - 0.514 - 5.526 - 6.040 0.000 + 3.510 + 3.510 0.000 - 1.301 - 0.323 (24.8%) - 0.978 (75.2%) + 0.000 + 0.787 + 0.323 (41.0%) + 0.464 (59.0%) - Path #17: hold slack is 0.650(MET) + Path #25: hold slack is 0.740(MET) -
+
Location Delay Type @@ -78576,7 +79701,7 @@ Logical Resource - Clock clk_50m (rising edge) + Clock clk_10m (rising edge) 0.000 0.000 @@ -78637,15 +79762,15 @@ 0.094 2.396 r - u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT4 (GTP_PLL_E3) - net (fanout=2827) - 3.130 - 5.526 + net (fanout=256) + 1.114 + 3.510 - rd3_clk + clk_10m @@ -78653,23 +79778,23 @@ r - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[6]/CLK (GTP_DFF) + ms72xx_ctl/iic_dri_rx/receiv_data[7]/CLK (GTP_DFF_RE) tco 0.323 - 5.849 + 3.833 f - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[6]/Q (GTP_DFF) + ms72xx_ctl/iic_dri_rx/receiv_data[7]/Q (GTP_DFF_RE) net (fanout=1) - 0.978 - 6.827 + 0.464 + 4.297 - rd3_ddr_addr[6] + ms72xx_ctl/iic_dri_rx/receiv_data [7] @@ -78677,12 +79802,12 @@ f - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/DIA[6] (GTP_DRM18K) + ms72xx_ctl/iic_dri_rx/data_out[7]/D (GTP_DFF_E)
- +
Location Delay Type @@ -78692,7 +79817,7 @@ Logical Resource - Clock clk_50m (rising edge) + Clock clk_10m (rising edge) 0.000 0.000 @@ -78753,15 +79878,15 @@ 0.094 2.396 r - u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT4 (GTP_PLL_E3) - net (fanout=2827) - 3.644 - 6.040 + net (fanout=256) + 1.114 + 3.510 - rd3_clk + clk_10m @@ -78769,13 +79894,13 @@ r - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (GTP_DRM18K) + ms72xx_ctl/iic_dri_rx/data_out[7]/CLK (GTP_DFF_E) clock pessimism 0.000 - 6.040 + 3.510 @@ -78783,15 +79908,15 @@ clock uncertainty 0.000 - 6.040 + 3.510 Hold time - 0.137 - 6.177 + 0.047 + 3.557 @@ -78800,27 +79925,27 @@ - 0.650 + 0.740 0 1 - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[7]/CLK - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/DIA[7] + ms72xx_ctl/ms7200_ctl/iic_trig/CLK + ms72xx_ctl/iic_dri_rx/pluse_1d/D - clk_50m - clk_50m + clk_10m + clk_10m rise-rise - 0.514 - 5.526 - 6.040 0.000 + 3.510 + 3.510 0.000 - 1.301 - 0.323 (24.8%) - 0.978 (75.2%) + 0.000 + 0.787 + 0.323 (41.0%) + 0.464 (59.0%) - Path #18: hold slack is 0.650(MET) + Path #26: hold slack is 0.740(MET) -
+
Location Delay Type @@ -78830,7 +79955,7 @@ Logical Resource - Clock clk_50m (rising edge) + Clock clk_10m (rising edge) 0.000 0.000 @@ -78891,15 +80016,15 @@ 0.094 2.396 r - u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT4 (GTP_PLL_E3) - net (fanout=2827) - 3.130 - 5.526 + net (fanout=256) + 1.114 + 3.510 - rd3_clk + clk_10m @@ -78907,23 +80032,23 @@ r - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[7]/CLK (GTP_DFF) + ms72xx_ctl/ms7200_ctl/iic_trig/CLK (GTP_DFF_R) tco 0.323 - 5.849 + 3.833 f - u_ddr_addr_ctr/u_rd3_addr_ctr/now_ddr_addr[7]/Q (GTP_DFF) + ms72xx_ctl/ms7200_ctl/iic_trig/Q (GTP_DFF_R) net (fanout=1) - 0.978 - 6.827 + 0.464 + 4.297 - rd3_ddr_addr[7] + ms72xx_ctl/iic_trig_rx @@ -78931,12 +80056,12 @@ f - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/DIA[7] (GTP_DRM18K) + ms72xx_ctl/iic_dri_rx/pluse_1d/D (GTP_DFF_R)
- +
Location Delay Type @@ -78946,7 +80071,7 @@ Logical Resource - Clock clk_50m (rising edge) + Clock clk_10m (rising edge) 0.000 0.000 @@ -79007,15 +80132,15 @@ 0.094 2.396 r - u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT4 (GTP_PLL_E3) - net (fanout=2827) - 3.644 - 6.040 + net (fanout=256) + 1.114 + 3.510 - rd3_clk + clk_10m @@ -79023,13 +80148,13 @@ r - u_axi_ddr_top/u_araddr_fifo/U_ipml_fifo_araddr_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (GTP_DRM18K) + ms72xx_ctl/iic_dri_rx/pluse_1d/CLK (GTP_DFF_R) clock pessimism 0.000 - 6.040 + 3.510 @@ -79037,15 +80162,15 @@ clock uncertainty 0.000 - 6.040 + 3.510 Hold time - 0.137 - 6.177 + 0.047 + 3.557 @@ -79054,27 +80179,27 @@ - 0.650 + 0.740 0 1 - udp_osd_inst/char_buf_writer_inst/ram_din[0]/CLK - udp_osd_inst/char_ram/U_ipml_sdpram_async_ram2048x8_2clk/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/DIA[0] + ms72xx_ctl/iic_dri_rx/pluse_1d/CLK + ms72xx_ctl/iic_dri_rx/pluse_2d/D - clk_720p60Hz - clk_720p60Hz + clk_10m + clk_10m rise-rise - 0.514 - 8.073 - 8.587 0.000 + 3.510 + 3.510 0.000 - 1.301 - 0.323 (24.8%) - 0.978 (75.2%) + 0.000 + 0.787 + 0.323 (41.0%) + 0.464 (59.0%) - Path #19: hold slack is 0.650(MET) + Path #27: hold slack is 0.740(MET) -
+
Location Delay Type @@ -79084,7 +80209,7 @@ Logical Resource - Clock clk_720p60Hz (rising edge) + Clock clk_10m (rising edge) 0.000 0.000 @@ -79145,39 +80270,15 @@ 0.094 2.396 r - u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - - - - net (fanout=2827) - 3.130 - 5.526 - - rd3_clk - - - - - - - - U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) - - - - td - 0.089 - 5.615 - r - U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT4 (GTP_PLL_E3) - net (fanout=1758) - 2.458 - 8.073 + net (fanout=256) + 1.114 + 3.510 - nt_pix_clk + clk_10m @@ -79185,23 +80286,23 @@ r - udp_osd_inst/char_buf_writer_inst/ram_din[0]/CLK (GTP_DFF_RE) + ms72xx_ctl/iic_dri_rx/pluse_1d/CLK (GTP_DFF_R) tco 0.323 - 8.396 + 3.833 f - udp_osd_inst/char_buf_writer_inst/ram_din[0]/Q (GTP_DFF_RE) + ms72xx_ctl/iic_dri_rx/pluse_1d/Q (GTP_DFF_R) net (fanout=1) - 0.978 - 9.374 + 0.464 + 4.297 - udp_osd_inst/ram_din [0] + ms72xx_ctl/iic_dri_rx/pluse_1d @@ -79209,12 +80310,12 @@ f - udp_osd_inst/char_ram/U_ipml_sdpram_async_ram2048x8_2clk/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/DIA[0] (GTP_DRM18K) + ms72xx_ctl/iic_dri_rx/pluse_2d/D (GTP_DFF_R)
- +
Location Delay Type @@ -79224,7 +80325,7 @@ Logical Resource - Clock clk_720p60Hz (rising edge) + Clock clk_10m (rising edge) 0.000 0.000 @@ -79285,39 +80386,15 @@ 0.094 2.396 r - u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - - - - net (fanout=2827) - 3.130 - 5.526 - - rd3_clk - - - - - - - - U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) - - - - td - 0.089 - 5.615 - r - U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT4 (GTP_PLL_E3) - net (fanout=1758) - 2.972 - 8.587 + net (fanout=256) + 1.114 + 3.510 - nt_pix_clk + clk_10m @@ -79325,13 +80402,13 @@ r - udp_osd_inst/char_ram/U_ipml_sdpram_async_ram2048x8_2clk/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (GTP_DRM18K) + ms72xx_ctl/iic_dri_rx/pluse_2d/CLK (GTP_DFF_R) clock pessimism 0.000 - 8.587 + 3.510 @@ -79339,15 +80416,15 @@ clock uncertainty 0.000 - 8.587 + 3.510 Hold time - 0.137 - 8.724 + 0.047 + 3.557 @@ -79356,27 +80433,27 @@ - 0.650 + 0.740 0 1 - udp_osd_inst/char_buf_writer_inst/ram_din[1]/CLK - udp_osd_inst/char_ram/U_ipml_sdpram_async_ram2048x8_2clk/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/DIA[1] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/D - clk_720p60Hz - clk_720p60Hz + clk_200m + clk_200m rise-rise - 0.514 - 8.073 - 8.587 0.000 + 5.192 + 5.192 0.000 - 1.301 - 0.323 (24.8%) - 0.978 (75.2%) + 0.000 + 0.787 + 0.323 (41.0%) + 0.464 (59.0%) - Path #20: hold slack is 0.650(MET) + Path #28: hold slack is 0.740(MET) -
+
Location Delay Type @@ -79386,7 +80463,7 @@ Logical Resource - Clock clk_720p60Hz (rising edge) + Clock clk_200m (rising edge) 0.000 0.000 @@ -79444,18 +80521,18 @@ td - 0.094 - 2.396 + 0.089 + 2.391 r - u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=2827) - 3.130 - 5.526 + net (fanout=7) + 0.605 + 2.996 - rd3_clk + ddr_clk @@ -79463,23 +80540,23 @@ - U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) td - 0.089 - 5.615 + 0.000 + 2.996 r - U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=1758) - 2.458 - 8.073 + net (fanout=71) + 2.196 + 5.192 - nt_pix_clk + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin @@ -79487,23 +80564,23 @@ r - udp_osd_inst/char_buf_writer_inst/ram_din[1]/CLK (GTP_DFF_RE) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/CLK (GTP_DFF_C) tco 0.323 - 8.396 + 5.515 f - udp_osd_inst/char_buf_writer_inst/ram_din[1]/Q (GTP_DFF_RE) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/Q (GTP_DFF_C) net (fanout=1) - 0.978 - 9.374 + 0.464 + 5.979 - udp_osd_inst/ram_din [1] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1 [0] @@ -79511,12 +80588,12 @@ f - udp_osd_inst/char_ram/U_ipml_sdpram_async_ram2048x8_2clk/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/DIA[1] (GTP_DRM18K) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/D (GTP_DFF_C)
- +
Location Delay Type @@ -79526,7 +80603,7 @@ Logical Resource - Clock clk_720p60Hz (rising edge) + Clock clk_200m (rising edge) 0.000 0.000 @@ -79584,18 +80661,18 @@ td - 0.094 - 2.396 + 0.089 + 2.391 r - u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=2827) - 3.130 - 5.526 + net (fanout=7) + 0.605 + 2.996 - rd3_clk + ddr_clk @@ -79603,23 +80680,23 @@ - U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) td - 0.089 - 5.615 + 0.000 + 2.996 r - U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=1758) - 2.972 - 8.587 + net (fanout=71) + 2.196 + 5.192 - nt_pix_clk + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin @@ -79627,13 +80704,13 @@ r - udp_osd_inst/char_ram/U_ipml_sdpram_async_ram2048x8_2clk/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (GTP_DRM18K) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/CLK (GTP_DFF_C) clock pessimism 0.000 - 8.587 + 5.192 @@ -79641,15 +80718,15 @@ clock uncertainty 0.000 - 8.587 + 5.192 Hold time - 0.137 - 8.724 + 0.047 + 5.239 @@ -79658,27 +80735,27 @@ - 0.650 + 0.740 0 1 - udp_osd_inst/char_buf_writer_inst/ram_din[2]/CLK - udp_osd_inst/char_ram/U_ipml_sdpram_async_ram2048x8_2clk/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/DIA[2] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/dll_update_req_rst_ctrl/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[0]/D - clk_720p60Hz - clk_720p60Hz + clk_200m + clk_200m rise-rise - 0.514 - 8.073 - 8.587 0.000 + 5.192 + 5.192 0.000 - 1.301 - 0.323 (24.8%) - 0.978 (75.2%) + 0.000 + 0.787 + 0.323 (41.0%) + 0.464 (59.0%) - Path #21: hold slack is 0.650(MET) + Path #29: hold slack is 0.740(MET) -
+
Location Delay Type @@ -79688,7 +80765,7 @@ Logical Resource - Clock clk_720p60Hz (rising edge) + Clock clk_200m (rising edge) 0.000 0.000 @@ -79746,18 +80823,18 @@ td - 0.094 - 2.396 + 0.089 + 2.391 r - u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=2827) - 3.130 - 5.526 + net (fanout=7) + 0.605 + 2.996 - rd3_clk + ddr_clk @@ -79765,23 +80842,23 @@ - U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) td - 0.089 - 5.615 + 0.000 + 2.996 r - U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=1758) - 2.458 - 8.073 + net (fanout=71) + 2.196 + 5.192 - nt_pix_clk + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin @@ -79789,23 +80866,23 @@ r - udp_osd_inst/char_buf_writer_inst/ram_din[2]/CLK (GTP_DFF_RE) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/dll_update_req_rst_ctrl/CLK (GTP_DFF_C) tco 0.323 - 8.396 + 5.515 f - udp_osd_inst/char_buf_writer_inst/ram_din[2]/Q (GTP_DFF_RE) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/dll_update_req_rst_ctrl/Q (GTP_DFF_C) net (fanout=1) - 0.978 - 9.374 + 0.464 + 5.979 - udp_osd_inst/ram_din [2] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/dll_update_req_rst_ctrl @@ -79813,12 +80890,12 @@ f - udp_osd_inst/char_ram/U_ipml_sdpram_async_ram2048x8_2clk/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/DIA[2] (GTP_DRM18K) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[0]/D (GTP_DFF_C)
- +
Location Delay Type @@ -79828,7 +80905,7 @@ Logical Resource - Clock clk_720p60Hz (rising edge) + Clock clk_200m (rising edge) 0.000 0.000 @@ -79886,18 +80963,18 @@ td - 0.094 - 2.396 + 0.089 + 2.391 r - u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=2827) - 3.130 - 5.526 + net (fanout=7) + 0.605 + 2.996 - rd3_clk + ddr_clk @@ -79905,23 +80982,23 @@ - U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) td - 0.089 - 5.615 + 0.000 + 2.996 r - U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=1758) - 2.972 - 8.587 + net (fanout=71) + 2.196 + 5.192 - nt_pix_clk + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin @@ -79929,13 +81006,13 @@ r - udp_osd_inst/char_ram/U_ipml_sdpram_async_ram2048x8_2clk/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (GTP_DRM18K) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[0]/CLK (GTP_DFF_C) clock pessimism 0.000 - 8.587 + 5.192 @@ -79943,15 +81020,15 @@ clock uncertainty 0.000 - 8.587 + 5.192 Hold time - 0.137 - 8.724 + 0.047 + 5.239 @@ -79960,27 +81037,27 @@ - 0.656 + 0.740 0 1 - u_zoom_image/imag_addr1[0]/CLK - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/DIA[0] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[0]/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[1]/D clk_200m clk_200m rise-rise - 0.514 - 4.367 - 4.881 0.000 + 5.192 + 5.192 0.000 - 1.301 - 0.323 (24.8%) - 0.978 (75.2%) + 0.000 + 0.787 + 0.323 (41.0%) + 0.464 (59.0%) - Path #22: hold slack is 0.656(MET) + Path #30: hold slack is 0.740(MET) -
+
Location Delay Type @@ -80055,35 +81132,59 @@ - net (fanout=851) - 1.976 - 4.367 + net (fanout=7) + 0.605 + 2.996 - zoom_clk + ddr_clk + + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + + + + td + 0.000 + 2.996 r - u_zoom_image/imag_addr1[0]/CLK (GTP_DFF) + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + + + + net (fanout=71) + 2.196 + 5.192 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[0]/CLK (GTP_DFF_C) tco 0.323 - 4.690 + 5.515 f - u_zoom_image/imag_addr1[0]/Q (GTP_DFF) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[0]/Q (GTP_DFF_C) net (fanout=1) - 0.978 - 5.668 + 0.464 + 5.979 - zoom_image_addr[0] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d [0] @@ -80091,12 +81192,12 @@ f - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/DIA[0] (GTP_DRM9K) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[1]/D (GTP_DFF_C)
- +
Location Delay Type @@ -80171,25 +81272,49 @@ - net (fanout=851) - 2.490 - 4.881 + net (fanout=7) + 0.605 + 2.996 - zoom_clk + ddr_clk + + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + + + + td + 0.000 + 2.996 r - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/CLKA (GTP_DRM9K) + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + + + + net (fanout=71) + 2.196 + 5.192 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/dll_update_req_rst_ctrl_d[1]/CLK (GTP_DFF_C) clock pessimism 0.000 - 4.881 + 5.192 @@ -80197,15 +81322,15 @@ clock uncertainty 0.000 - 4.881 + 5.192 Hold time - 0.131 - 5.012 + 0.047 + 5.239 @@ -80214,27 +81339,27 @@ - 0.656 + 0.829 0 - 1 - u_zoom_image/imag_addr1[1]/CLK - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/DIA[1] + 2 + u_ov5640/coms1_reg_config/config_step_reg[2]/CLK + u_ov5640/coms1_reg_config/config_step_reg[0]/D - clk_200m - clk_200m + clk_20k + clk_20k rise-rise - 0.514 - 4.367 - 4.881 0.000 + 6.243 + 6.243 0.000 - 1.301 - 0.323 (24.8%) - 0.978 (75.2%) + 0.000 + 0.876 + 0.323 (36.9%) + 0.553 (63.1%) - Path #23: hold slack is 0.656(MET) + Path #31: hold slack is 0.829(MET) -
+
Location Delay Type @@ -80244,7 +81369,7 @@ Logical Resource - Clock clk_200m (rising edge) + Clock clk_20k (rising edge) 0.000 0.000 @@ -80285,11 +81410,59 @@ - net (fanout=1) - 1.091 - 2.302 + net (fanout=1) + 1.091 + 2.302 + + nt_clk + + + + + + + + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.098 + 2.400 + r + u_sys_pll/u_pll_e3/CLKOUT3 (GTP_PLL_E3) + + + + net (fanout=26) + 0.713 + 3.113 + + clk_25m + + + + + + + r + u_ov5640/coms1_reg_config/clk_20k_regdiv/CLK (GTP_DFF_RE) + + + + tco + 0.329 + 3.442 + r + u_ov5640/coms1_reg_config/clk_20k_regdiv/Q (GTP_DFF_RE) + + + + net (fanout=3) + 0.605 + 4.047 - nt_clk + u_ov5640/coms1_reg_config/clk_20k_regdiv @@ -80297,23 +81470,23 @@ - u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/CLKIN (GTP_CLKBUFG) td - 0.089 - 2.391 + 0.000 + 4.047 r - u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/CLKOUT (GTP_CLKBUFG) - net (fanout=851) - 1.976 - 4.367 + net (fanout=25) + 2.196 + 6.243 - zoom_clk + u_ov5640/coms1_reg_config/clock_20k @@ -80321,23 +81494,23 @@ r - u_zoom_image/imag_addr1[1]/CLK (GTP_DFF) + u_ov5640/coms1_reg_config/config_step_reg[2]/CLK (GTP_DFF_RE) tco 0.323 - 4.690 + 6.566 f - u_zoom_image/imag_addr1[1]/Q (GTP_DFF) + u_ov5640/coms1_reg_config/config_step_reg[2]/Q (GTP_DFF_RE) - net (fanout=1) - 0.978 - 5.668 + net (fanout=2) + 0.553 + 7.119 - zoom_image_addr[1] + u_ov5640/coms1_reg_config/config_step_reg [2] @@ -80345,12 +81518,12 @@ f - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/DIA[1] (GTP_DRM9K) + u_ov5640/coms1_reg_config/config_step_reg[0]/D (GTP_DFF_SE)
- +
Location Delay Type @@ -80360,7 +81533,7 @@ Logical Resource - Clock clk_200m (rising edge) + Clock clk_20k (rising edge) 0.000 0.000 @@ -80418,18 +81591,18 @@ td - 0.089 - 2.391 + 0.098 + 2.400 r - u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT3 (GTP_PLL_E3) - net (fanout=851) - 2.490 - 4.881 + net (fanout=26) + 0.713 + 3.113 - zoom_clk + clk_25m @@ -80437,13 +81610,61 @@ r - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/CLKA (GTP_DRM9K) + u_ov5640/coms1_reg_config/clk_20k_regdiv/CLK (GTP_DFF_RE) + + + + tco + 0.329 + 3.442 + r + u_ov5640/coms1_reg_config/clk_20k_regdiv/Q (GTP_DFF_RE) + + + + net (fanout=3) + 0.605 + 4.047 + + u_ov5640/coms1_reg_config/clk_20k_regdiv + + + + + + + + u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/CLKIN (GTP_CLKBUFG) + + + + td + 0.000 + 4.047 + r + u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/CLKOUT (GTP_CLKBUFG) + + + + net (fanout=25) + 2.196 + 6.243 + + u_ov5640/coms1_reg_config/clock_20k + + + + + + + r + u_ov5640/coms1_reg_config/config_step_reg[0]/CLK (GTP_DFF_SE) clock pessimism 0.000 - 4.881 + 6.243 @@ -80451,15 +81672,15 @@ clock uncertainty 0.000 - 4.881 + 6.243 Hold time - 0.131 - 5.012 + 0.047 + 6.290 @@ -80468,27 +81689,27 @@ - 0.656 + 0.829 0 - 1 - u_zoom_image/imag_addr1[2]/CLK - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/DIA[2] + 2 + u_ov5640/coms2_reg_config/config_step_reg[2]/CLK + u_ov5640/coms2_reg_config/config_step_reg[0]/D - clk_200m - clk_200m + clk_20k + clk_20k rise-rise - 0.514 - 4.367 - 4.881 0.000 + 6.243 + 6.243 0.000 - 1.301 - 0.323 (24.8%) - 0.978 (75.2%) + 0.000 + 0.876 + 0.323 (36.9%) + 0.553 (63.1%) - Path #24: hold slack is 0.656(MET) + Path #32: hold slack is 0.829(MET) -
+
Location Delay Type @@ -80498,7 +81719,7 @@ Logical Resource - Clock clk_200m (rising edge) + Clock clk_20k (rising edge) 0.000 0.000 @@ -80556,18 +81777,18 @@ td - 0.089 - 2.391 + 0.098 + 2.400 r - u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT3 (GTP_PLL_E3) - net (fanout=851) - 1.976 - 4.367 + net (fanout=26) + 0.713 + 3.113 - zoom_clk + clk_25m @@ -80575,23 +81796,71 @@ r - u_zoom_image/imag_addr1[2]/CLK (GTP_DFF) + u_ov5640/coms2_reg_config/clk_20k_regdiv/CLK (GTP_DFF_RE) + + + + tco + 0.329 + 3.442 + r + u_ov5640/coms2_reg_config/clk_20k_regdiv/Q (GTP_DFF_RE) + + + + net (fanout=3) + 0.605 + 4.047 + + u_ov5640/coms2_reg_config/clk_20k_regdiv + + + + + + + + u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/CLKIN (GTP_CLKBUFG) + + + + td + 0.000 + 4.047 + r + u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/CLKOUT (GTP_CLKBUFG) + + + + net (fanout=25) + 2.196 + 6.243 + + u_ov5640/coms2_reg_config/clock_20k + + + + + + + r + u_ov5640/coms2_reg_config/config_step_reg[2]/CLK (GTP_DFF_RE) tco 0.323 - 4.690 + 6.566 f - u_zoom_image/imag_addr1[2]/Q (GTP_DFF) + u_ov5640/coms2_reg_config/config_step_reg[2]/Q (GTP_DFF_RE) - net (fanout=1) - 0.978 - 5.668 + net (fanout=2) + 0.553 + 7.119 - zoom_image_addr[2] + u_ov5640/coms2_reg_config/config_step_reg [2] @@ -80599,12 +81868,12 @@ f - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/DIA[2] (GTP_DRM9K) + u_ov5640/coms2_reg_config/config_step_reg[0]/D (GTP_DFF_SE)
- +
Location Delay Type @@ -80614,7 +81883,7 @@ Logical Resource - Clock clk_200m (rising edge) + Clock clk_20k (rising edge) 0.000 0.000 @@ -80672,18 +81941,18 @@ td - 0.089 - 2.391 + 0.098 + 2.400 r - u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT3 (GTP_PLL_E3) - net (fanout=851) - 2.490 - 4.881 + net (fanout=26) + 0.713 + 3.113 - zoom_clk + clk_25m @@ -80691,13 +81960,61 @@ r - u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM9K/CLKA (GTP_DRM9K) + u_ov5640/coms2_reg_config/clk_20k_regdiv/CLK (GTP_DFF_RE) + + + + tco + 0.329 + 3.442 + r + u_ov5640/coms2_reg_config/clk_20k_regdiv/Q (GTP_DFF_RE) + + + + net (fanout=3) + 0.605 + 4.047 + + u_ov5640/coms2_reg_config/clk_20k_regdiv + + + + + + + + u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/CLKIN (GTP_CLKBUFG) + + + + td + 0.000 + 4.047 + r + u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/CLKOUT (GTP_CLKBUFG) + + + + net (fanout=25) + 2.196 + 6.243 + + u_ov5640/coms2_reg_config/clock_20k + + + + + + + r + u_ov5640/coms2_reg_config/config_step_reg[0]/CLK (GTP_DFF_SE) clock pessimism 0.000 - 4.881 + 6.243 @@ -80705,15 +82022,15 @@ clock uncertainty 0.000 - 4.881 + 6.243 Hold time - 0.131 - 5.012 + 0.047 + 6.290 @@ -80722,27 +82039,27 @@ - 0.740 + 0.881 0 - 1 - ms72xx_ctl/iic_dri_rx/receiv_data[7]/CLK - ms72xx_ctl/iic_dri_rx/data_out[7]/D + 3 + u_ov5640/coms1_reg_config/clk_20k_regdiv/CLK + u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/D - clk_10m - clk_10m + clk_25m + clk_25m rise-rise 0.000 - 3.510 - 3.510 + 3.113 + 3.113 0.000 0.000 - 0.787 - 0.323 (41.0%) - 0.464 (59.0%) + 0.928 + 0.323 (34.8%) + 0.605 (65.2%) - Path #25: hold slack is 0.740(MET) + Path #33: hold slack is 0.881(MET) -
+
Location Delay Type @@ -80752,7 +82069,7 @@ Logical Resource - Clock clk_10m (rising edge) + Clock clk_25m (rising edge) 0.000 0.000 @@ -80810,18 +82127,18 @@ td - 0.094 - 2.396 + 0.098 + 2.400 r - u_sys_pll/u_pll_e3/CLKOUT4 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT3 (GTP_PLL_E3) - net (fanout=256) - 1.114 - 3.510 + net (fanout=26) + 0.713 + 3.113 - clk_10m + clk_25m @@ -80829,23 +82146,23 @@ r - ms72xx_ctl/iic_dri_rx/receiv_data[7]/CLK (GTP_DFF_RE) + u_ov5640/coms1_reg_config/clk_20k_regdiv/CLK (GTP_DFF_RE) tco 0.323 - 3.833 + 3.436 f - ms72xx_ctl/iic_dri_rx/receiv_data[7]/Q (GTP_DFF_RE) + u_ov5640/coms1_reg_config/clk_20k_regdiv/Q (GTP_DFF_RE) - net (fanout=1) - 0.464 - 4.297 + net (fanout=3) + 0.605 + 4.041 - ms72xx_ctl/iic_dri_rx/receiv_data [7] + u_ov5640/coms1_reg_config/clk_20k_regdiv @@ -80853,12 +82170,12 @@ f - ms72xx_ctl/iic_dri_rx/data_out[7]/D (GTP_DFF_E) + u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/D (GTP_DFF_SE)
- +
Location Delay Type @@ -80868,7 +82185,7 @@ Logical Resource - Clock clk_10m (rising edge) + Clock clk_25m (rising edge) 0.000 0.000 @@ -80926,18 +82243,18 @@ td - 0.094 - 2.396 + 0.098 + 2.400 r - u_sys_pll/u_pll_e3/CLKOUT4 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT3 (GTP_PLL_E3) - net (fanout=256) - 1.114 - 3.510 + net (fanout=26) + 0.713 + 3.113 - clk_10m + clk_25m @@ -80945,13 +82262,13 @@ r - ms72xx_ctl/iic_dri_rx/data_out[7]/CLK (GTP_DFF_E) + u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/CLK (GTP_DFF_SE) clock pessimism 0.000 - 3.510 + 3.113 @@ -80959,7 +82276,7 @@ clock uncertainty 0.000 - 3.510 + 3.113 @@ -80967,7 +82284,7 @@ Hold time 0.047 - 3.557 + 3.160 @@ -80976,27 +82293,27 @@ - 0.740 + 0.881 0 - 1 - ms72xx_ctl/ms7200_ctl/iic_trig/CLK - ms72xx_ctl/iic_dri_rx/pluse_1d/D + 3 + u_ov5640/coms1_reg_config/config_step_reg[0]/CLK + u_ov5640/coms1_reg_config/config_step_reg[1]/D - clk_10m - clk_10m + clk_20k + clk_20k rise-rise 0.000 - 3.510 - 3.510 + 6.243 + 6.243 0.000 0.000 - 0.787 - 0.323 (41.0%) - 0.464 (59.0%) + 0.928 + 0.323 (34.8%) + 0.605 (65.2%) - Path #26: hold slack is 0.740(MET) + Path #34: hold slack is 0.881(MET) -
+
Location Delay Type @@ -81006,7 +82323,7 @@ Logical Resource - Clock clk_10m (rising edge) + Clock clk_20k (rising edge) 0.000 0.000 @@ -81064,18 +82381,18 @@ td - 0.094 - 2.396 + 0.098 + 2.400 r - u_sys_pll/u_pll_e3/CLKOUT4 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT3 (GTP_PLL_E3) - net (fanout=256) - 1.114 - 3.510 + net (fanout=26) + 0.713 + 3.113 - clk_10m + clk_25m @@ -81083,23 +82400,71 @@ r - ms72xx_ctl/ms7200_ctl/iic_trig/CLK (GTP_DFF_R) + u_ov5640/coms1_reg_config/clk_20k_regdiv/CLK (GTP_DFF_RE) + + + + tco + 0.329 + 3.442 + r + u_ov5640/coms1_reg_config/clk_20k_regdiv/Q (GTP_DFF_RE) + + + + net (fanout=3) + 0.605 + 4.047 + + u_ov5640/coms1_reg_config/clk_20k_regdiv + + + + + + + + u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/CLKIN (GTP_CLKBUFG) + + + + td + 0.000 + 4.047 + r + u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/CLKOUT (GTP_CLKBUFG) + + + + net (fanout=25) + 2.196 + 6.243 + + u_ov5640/coms1_reg_config/clock_20k + + + + + + + r + u_ov5640/coms1_reg_config/config_step_reg[0]/CLK (GTP_DFF_SE) tco 0.323 - 3.833 + 6.566 f - ms72xx_ctl/ms7200_ctl/iic_trig/Q (GTP_DFF_R) + u_ov5640/coms1_reg_config/config_step_reg[0]/Q (GTP_DFF_SE) - net (fanout=1) - 0.464 - 4.297 + net (fanout=3) + 0.605 + 7.171 - ms72xx_ctl/iic_trig_rx + u_ov5640/coms1_reg_config/config_step_reg [0] @@ -81107,12 +82472,12 @@ f - ms72xx_ctl/iic_dri_rx/pluse_1d/D (GTP_DFF_R) + u_ov5640/coms1_reg_config/config_step_reg[1]/D (GTP_DFF_RE)
- +
Location Delay Type @@ -81122,7 +82487,7 @@ Logical Resource - Clock clk_10m (rising edge) + Clock clk_20k (rising edge) 0.000 0.000 @@ -81175,23 +82540,71 @@ - u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.098 + 2.400 + r + u_sys_pll/u_pll_e3/CLKOUT3 (GTP_PLL_E3) + + + + net (fanout=26) + 0.713 + 3.113 + + clk_25m + + + + + + + r + u_ov5640/coms1_reg_config/clk_20k_regdiv/CLK (GTP_DFF_RE) + + + + tco + 0.329 + 3.442 + r + u_ov5640/coms1_reg_config/clk_20k_regdiv/Q (GTP_DFF_RE) + + + + net (fanout=3) + 0.605 + 4.047 + + u_ov5640/coms1_reg_config/clk_20k_regdiv + + + + + + + + u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/CLKIN (GTP_CLKBUFG) td - 0.094 - 2.396 + 0.000 + 4.047 r - u_sys_pll/u_pll_e3/CLKOUT4 (GTP_PLL_E3) + u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/CLKOUT (GTP_CLKBUFG) - net (fanout=256) - 1.114 - 3.510 + net (fanout=25) + 2.196 + 6.243 - clk_10m + u_ov5640/coms1_reg_config/clock_20k @@ -81199,13 +82612,13 @@ r - ms72xx_ctl/iic_dri_rx/pluse_1d/CLK (GTP_DFF_R) + u_ov5640/coms1_reg_config/config_step_reg[1]/CLK (GTP_DFF_RE) clock pessimism 0.000 - 3.510 + 6.243 @@ -81213,7 +82626,7 @@ clock uncertainty 0.000 - 3.510 + 6.243 @@ -81221,7 +82634,7 @@ Hold time 0.047 - 3.557 + 6.290 @@ -81230,27 +82643,27 @@ - 0.740 + 0.881 0 - 1 - ms72xx_ctl/iic_dri_rx/pluse_1d/CLK - ms72xx_ctl/iic_dri_rx/pluse_2d/D + 3 + u_ov5640/coms2_reg_config/clk_20k_regdiv/CLK + u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite/D - clk_10m - clk_10m + clk_25m + clk_25m rise-rise 0.000 - 3.510 - 3.510 + 3.113 + 3.113 0.000 0.000 - 0.787 - 0.323 (41.0%) - 0.464 (59.0%) + 0.928 + 0.323 (34.8%) + 0.605 (65.2%) - Path #27: hold slack is 0.740(MET) + Path #35: hold slack is 0.881(MET) -
+
Location Delay Type @@ -81260,7 +82673,7 @@ Logical Resource - Clock clk_10m (rising edge) + Clock clk_25m (rising edge) 0.000 0.000 @@ -81318,18 +82731,18 @@ td - 0.094 - 2.396 + 0.098 + 2.400 r - u_sys_pll/u_pll_e3/CLKOUT4 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT3 (GTP_PLL_E3) - net (fanout=256) - 1.114 - 3.510 + net (fanout=26) + 0.713 + 3.113 - clk_10m + clk_25m @@ -81337,23 +82750,23 @@ r - ms72xx_ctl/iic_dri_rx/pluse_1d/CLK (GTP_DFF_R) + u_ov5640/coms2_reg_config/clk_20k_regdiv/CLK (GTP_DFF_RE) tco 0.323 - 3.833 + 3.436 f - ms72xx_ctl/iic_dri_rx/pluse_1d/Q (GTP_DFF_R) + u_ov5640/coms2_reg_config/clk_20k_regdiv/Q (GTP_DFF_RE) - net (fanout=1) - 0.464 - 4.297 + net (fanout=3) + 0.605 + 4.041 - ms72xx_ctl/iic_dri_rx/pluse_1d + u_ov5640/coms2_reg_config/clk_20k_regdiv @@ -81361,12 +82774,12 @@ f - ms72xx_ctl/iic_dri_rx/pluse_2d/D (GTP_DFF_R) + u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite/D (GTP_DFF_SE)
- +
Location Delay Type @@ -81376,7 +82789,7 @@ Logical Resource - Clock clk_10m (rising edge) + Clock clk_25m (rising edge) 0.000 0.000 @@ -81434,18 +82847,18 @@ td - 0.094 - 2.396 + 0.098 + 2.400 r - u_sys_pll/u_pll_e3/CLKOUT4 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT3 (GTP_PLL_E3) - net (fanout=256) - 1.114 - 3.510 + net (fanout=26) + 0.713 + 3.113 - clk_10m + clk_25m @@ -81453,13 +82866,13 @@ r - ms72xx_ctl/iic_dri_rx/pluse_2d/CLK (GTP_DFF_R) + u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite/CLK (GTP_DFF_SE) clock pessimism 0.000 - 3.510 + 3.113 @@ -81467,7 +82880,7 @@ clock uncertainty 0.000 - 3.510 + 3.113 @@ -81475,7 +82888,7 @@ Hold time 0.047 - 3.557 + 3.160 @@ -81484,27 +82897,27 @@ - 0.829 - 0 - 2 - u_ov5640/coms1_reg_config/config_step_reg[2]/CLK - u_ov5640/coms1_reg_config/config_step_reg[0]/D + 1.053 + 1 + 3 + u_ov5640/coms1_reg_config/clk_20k_regdiv/CLK + u_ov5640/coms1_reg_config/clk_20k_regdiv/D - clk_20k - clk_20k + clk_25m + clk_25m rise-rise 0.000 - 6.243 - 6.243 + 3.113 + 3.113 0.000 0.000 - 0.876 - 0.323 (36.9%) - 0.553 (63.1%) + 1.100 + 0.495 (45.0%) + 0.605 (55.0%) - Path #28: hold slack is 0.829(MET) + Path #36: hold slack is 1.053(MET) -
+
Location Delay Type @@ -81514,7 +82927,7 @@ Logical Resource - Clock clk_20k (rising edge) + Clock clk_25m (rising edge) 0.000 0.000 @@ -81594,68 +83007,44 @@ u_ov5640/coms1_reg_config/clk_20k_regdiv/CLK (GTP_DFF_RE) - + tco - 0.329 - 3.442 - r + 0.323 + 3.436 + f u_ov5640/coms1_reg_config/clk_20k_regdiv/Q (GTP_DFF_RE) net (fanout=3) 0.605 - 4.047 - + 4.041 + u_ov5640/coms1_reg_config/clk_20k_regdiv - - - - - - u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/CLKIN (GTP_CLKBUFG) - - - - td - 0.000 - 4.047 - r - u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/CLKOUT (GTP_CLKBUFG) - - - - net (fanout=25) - 2.196 - 6.243 + - u_ov5640/coms1_reg_config/clock_20k - - - - r - u_ov5640/coms1_reg_config/config_step_reg[2]/CLK (GTP_DFF_RE) + u_ov5640/coms1_reg_config/N12/I0 (GTP_LUT1) - tco - 0.323 - 6.566 + td + 0.172 + 4.213 f - u_ov5640/coms1_reg_config/config_step_reg[2]/Q (GTP_DFF_RE) + u_ov5640/coms1_reg_config/N12/Z (GTP_LUT1) - net (fanout=2) - 0.553 - 7.119 + net (fanout=1) + 0.000 + 4.213 - u_ov5640/coms1_reg_config/config_step_reg [2] + u_ov5640/coms1_reg_config/N12 @@ -81663,12 +83052,12 @@ f - u_ov5640/coms1_reg_config/config_step_reg[0]/D (GTP_DFF_SE) + u_ov5640/coms1_reg_config/clk_20k_regdiv/D (GTP_DFF_RE)
- +
Location Delay Type @@ -81678,7 +83067,7 @@ Logical Resource - Clock clk_20k (rising edge) + Clock clk_25m (rising edge) 0.000 0.000 @@ -81757,59 +83146,11 @@ r u_ov5640/coms1_reg_config/clk_20k_regdiv/CLK (GTP_DFF_RE) - - - tco - 0.329 - 3.442 - r - u_ov5640/coms1_reg_config/clk_20k_regdiv/Q (GTP_DFF_RE) - - - - net (fanout=3) - 0.605 - 4.047 - - u_ov5640/coms1_reg_config/clk_20k_regdiv - - - - - - - - u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/CLKIN (GTP_CLKBUFG) - - - - td - 0.000 - 4.047 - r - u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/CLKOUT (GTP_CLKBUFG) - - - - net (fanout=25) - 2.196 - 6.243 - - u_ov5640/coms1_reg_config/clock_20k - - - - - - - r - u_ov5640/coms1_reg_config/config_step_reg[0]/CLK (GTP_DFF_SE) - clock pessimism 0.000 - 6.243 + 3.113 @@ -81817,7 +83158,7 @@ clock uncertainty 0.000 - 6.243 + 3.113 @@ -81825,7 +83166,7 @@ Hold time 0.047 - 6.290 + 3.160 @@ -81834,27 +83175,27 @@ - 0.829 + 1.193 0 - 2 - u_ov5640/coms2_reg_config/config_step_reg[2]/CLK - u_ov5640/coms2_reg_config/config_step_reg[0]/D + 8 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/CLKA + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[0] - clk_20k - clk_20k + ioclk1 + ioclk1 rise-rise 0.000 - 6.243 - 6.243 + 5.766 + 5.766 0.000 0.000 - 0.876 - 0.323 (36.9%) - 0.553 (63.1%) + 1.194 + 0.464 (38.9%) + 0.730 (61.1%) - Path #29: hold slack is 0.829(MET) + Path #37: hold slack is 1.193(MET) -
+
Location Delay Type @@ -81864,7 +83205,7 @@ Logical Resource - Clock clk_20k (rising edge) + Clock ioclk1 (rising edge) 0.000 0.000 @@ -81922,42 +83263,18 @@ td - 0.098 - 2.400 - r - u_sys_pll/u_pll_e3/CLKOUT3 (GTP_PLL_E3) - - - - net (fanout=26) - 0.713 - 3.113 - - clk_25m - - - - - - - r - u_ov5640/coms2_reg_config/clk_20k_regdiv/CLK (GTP_DFF_RE) - - - - tco - 0.329 - 3.442 + 0.089 + 2.391 r - u_ov5640/coms2_reg_config/clk_20k_regdiv/Q (GTP_DFF_RE) + u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=3) + net (fanout=7) 0.605 - 4.047 + 2.996 - u_ov5640/coms2_reg_config/clk_20k_regdiv + ddr_clk @@ -81965,115 +83282,23 @@ - u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/CLKIN (GTP_CLKBUFG) + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) td 0.000 - 4.047 - r - u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/CLKOUT (GTP_CLKBUFG) - - - - net (fanout=25) - 2.196 - 6.243 - - u_ov5640/coms2_reg_config/clock_20k - - - - - - - r - u_ov5640/coms2_reg_config/config_step_reg[2]/CLK (GTP_DFF_RE) - - - - tco - 0.323 - 6.566 - f - u_ov5640/coms2_reg_config/config_step_reg[2]/Q (GTP_DFF_RE) - - - - net (fanout=2) - 0.553 - 7.119 - - u_ov5640/coms2_reg_config/config_step_reg [2] - - - - - - - f - u_ov5640/coms2_reg_config/config_step_reg[0]/D (GTP_DFF_SE) - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_20k (rising edge) - - 0.000 - 0.000 - r - - - - clk - - 0.000 - 0.000 - r - clk (port) - - - - net (fanout=1) - 0.000 - 0.000 - - clk - - - - - - - - clk_ibuf/I (GTP_INBUF) - - - - td - 1.211 - 1.211 + 2.996 r - clk_ibuf/O (GTP_INBUF) + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=1) - 1.091 - 2.302 + net (fanout=71) + 0.847 + 3.843 - nt_clk + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin @@ -82081,47 +83306,23 @@ - u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) td - 0.098 - 2.400 - r - u_sys_pll/u_pll_e3/CLKOUT3 (GTP_PLL_E3) - - - - net (fanout=26) - 0.713 - 3.113 - - clk_25m - - - - - - - r - u_ov5640/coms2_reg_config/clk_20k_regdiv/CLK (GTP_DFF_RE) - - - - tco - 0.329 - 3.442 + 0.094 + 3.937 r - u_ov5640/coms2_reg_config/clk_20k_regdiv/Q (GTP_DFF_RE) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) net (fanout=3) 0.605 - 4.047 + 4.542 - u_ov5640/coms2_reg_config/clk_20k_regdiv + u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] @@ -82129,23 +83330,23 @@ - u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/CLKIN (GTP_CLKBUFG) + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKIN (GTP_IOCLKBUF) td - 0.000 - 4.047 + 0.306 + 4.848 r - u_ov5640/coms2_reg_config/U_CLKBUFG_CLK_20K/CLKOUT (GTP_CLKBUFG) + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) - net (fanout=25) - 2.196 - 6.243 + net (fanout=28) + 0.918 + 5.766 - u_ov5640/coms2_reg_config/clock_20k + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] @@ -82153,58 +83354,36 @@ r - u_ov5640/coms2_reg_config/config_step_reg[0]/CLK (GTP_DFF_SE) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/CLKA (GTP_DDC_E1) - clock pessimism - - 0.000 - 6.243 - - + + tco + 0.464 + 6.230 + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[0] (GTP_DDC_E1) - clock uncertainty - - 0.000 - 6.243 - + net (fanout=8) + 0.730 + 6.960 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [0] - Hold time - - 0.047 - 6.290 + - -
-
-
-
- - 0.881 - 0 - 3 - u_ov5640/coms1_reg_config/clk_20k_regdiv/CLK - u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/D - - clk_25m - clk_25m - rise-rise - 0.000 - 3.113 - 3.113 - 0.000 - 0.000 - 0.928 - 0.323 (34.8%) - 0.605 (65.2%) - - Path #30: hold slack is 0.881(MET) + + f + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[0] (GTP_ISERDES) + + + - +
Location Delay Type @@ -82214,7 +83393,7 @@ Logical Resource - Clock clk_25m (rising edge) + Clock ioclk1 (rising edge) 0.000 0.000 @@ -82272,86 +83451,42 @@ td - 0.098 - 2.400 + 0.089 + 2.391 r - u_sys_pll/u_pll_e3/CLKOUT3 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=26) - 0.713 - 3.113 + net (fanout=7) + 0.605 + 2.996 - clk_25m + ddr_clk - r - u_ov5640/coms1_reg_config/clk_20k_regdiv/CLK (GTP_DFF_RE) - - - - tco - 0.323 - 3.436 - f - u_ov5640/coms1_reg_config/clk_20k_regdiv/Q (GTP_DFF_RE) - - - - net (fanout=3) - 0.605 - 4.041 - - u_ov5640/coms1_reg_config/clk_20k_regdiv - - - - - - - f - u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/D (GTP_DFF_SE) - -
-
- - - - Location - Delay Type - Incr - Path - Trans - Logical Resource - - - Clock clk_25m (rising edge) - - 0.000 - 0.000 - r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - clk + td 0.000 - 0.000 + 2.996 r - clk (port) + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - net (fanout=1) - 0.000 - 0.000 + net (fanout=71) + 0.847 + 3.843 - clk + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin @@ -82359,23 +83494,23 @@ - clk_ibuf/I (GTP_INBUF) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) td - 1.211 - 1.211 + 0.094 + 3.937 r - clk_ibuf/O (GTP_INBUF) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=1) - 1.091 - 2.302 + net (fanout=3) + 0.605 + 4.542 - nt_clk + u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] @@ -82383,23 +83518,23 @@ - u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKIN (GTP_IOCLKBUF) td - 0.098 - 2.400 + 0.306 + 4.848 r - u_sys_pll/u_pll_e3/CLKOUT3 (GTP_PLL_E3) + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) - net (fanout=26) - 0.713 - 3.113 + net (fanout=28) + 0.918 + 5.766 - clk_25m + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] @@ -82407,13 +83542,13 @@ r - u_ov5640/coms1_reg_config/clk_20k_regdiv_opposite/CLK (GTP_DFF_SE) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/DESCLK (GTP_ISERDES) clock pessimism 0.000 - 3.113 + 5.766 @@ -82421,15 +83556,15 @@ clock uncertainty 0.000 - 3.113 + 5.766 Hold time - 0.047 - 3.160 + 0.001 + 5.767 @@ -82438,27 +83573,27 @@ - 0.881 + 1.193 0 - 3 - u_ov5640/coms1_reg_config/config_step_reg[0]/CLK - u_ov5640/coms1_reg_config/config_step_reg[1]/D + 8 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/CLKA + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[1] - clk_20k - clk_20k + ioclk1 + ioclk1 rise-rise 0.000 - 6.243 - 6.243 + 5.766 + 5.766 0.000 0.000 - 0.928 - 0.323 (34.8%) - 0.605 (65.2%) + 1.194 + 0.464 (38.9%) + 0.730 (61.1%) - Path #31: hold slack is 0.881(MET) + Path #38: hold slack is 1.193(MET) -
+
Location Delay Type @@ -82468,7 +83603,7 @@ Logical Resource - Clock clk_20k (rising edge) + Clock ioclk1 (rising edge) 0.000 0.000 @@ -82526,42 +83661,66 @@ td - 0.098 - 2.400 + 0.089 + 2.391 r - u_sys_pll/u_pll_e3/CLKOUT3 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=26) - 0.713 - 3.113 + net (fanout=7) + 0.605 + 2.996 - clk_25m + ddr_clk + + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + + + + td + 0.000 + 2.996 r - u_ov5640/coms1_reg_config/clk_20k_regdiv/CLK (GTP_DFF_RE) + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + + + + net (fanout=71) + 0.847 + 3.843 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - tco - 0.329 - 3.442 + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.094 + 3.937 r - u_ov5640/coms1_reg_config/clk_20k_regdiv/Q (GTP_DFF_RE) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) net (fanout=3) 0.605 - 4.047 + 4.542 - u_ov5640/coms1_reg_config/clk_20k_regdiv + u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] @@ -82569,23 +83728,23 @@ - u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/CLKIN (GTP_CLKBUFG) + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKIN (GTP_IOCLKBUF) td - 0.000 - 4.047 + 0.306 + 4.848 r - u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/CLKOUT (GTP_CLKBUFG) + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) - net (fanout=25) - 2.196 - 6.243 + net (fanout=28) + 0.918 + 5.766 - u_ov5640/coms1_reg_config/clock_20k + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] @@ -82593,23 +83752,23 @@ r - u_ov5640/coms1_reg_config/config_step_reg[0]/CLK (GTP_DFF_SE) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/CLKA (GTP_DDC_E1) tco - 0.323 - 6.566 + 0.464 + 6.230 f - u_ov5640/coms1_reg_config/config_step_reg[0]/Q (GTP_DFF_SE) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[1] (GTP_DDC_E1) - net (fanout=3) - 0.605 - 7.171 + net (fanout=8) + 0.730 + 6.960 - u_ov5640/coms1_reg_config/config_step_reg [0] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [1] @@ -82617,12 +83776,12 @@ f - u_ov5640/coms1_reg_config/config_step_reg[1]/D (GTP_DFF_RE) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[1] (GTP_ISERDES)
- +
Location Delay Type @@ -82632,7 +83791,7 @@ Logical Resource - Clock clk_20k (rising edge) + Clock ioclk1 (rising edge) 0.000 0.000 @@ -82690,42 +83849,66 @@ td - 0.098 - 2.400 + 0.089 + 2.391 r - u_sys_pll/u_pll_e3/CLKOUT3 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=26) - 0.713 - 3.113 + net (fanout=7) + 0.605 + 2.996 - clk_25m + ddr_clk + + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + + + + td + 0.000 + 2.996 r - u_ov5640/coms1_reg_config/clk_20k_regdiv/CLK (GTP_DFF_RE) + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + + + + net (fanout=71) + 0.847 + 3.843 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - tco - 0.329 - 3.442 + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.094 + 3.937 r - u_ov5640/coms1_reg_config/clk_20k_regdiv/Q (GTP_DFF_RE) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) net (fanout=3) 0.605 - 4.047 + 4.542 - u_ov5640/coms1_reg_config/clk_20k_regdiv + u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] @@ -82733,23 +83916,23 @@ - u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/CLKIN (GTP_CLKBUFG) + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKIN (GTP_IOCLKBUF) td - 0.000 - 4.047 + 0.306 + 4.848 r - u_ov5640/coms1_reg_config/U_CLKBUFG_CLK_20K/CLKOUT (GTP_CLKBUFG) + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) - net (fanout=25) - 2.196 - 6.243 + net (fanout=28) + 0.918 + 5.766 - u_ov5640/coms1_reg_config/clock_20k + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] @@ -82757,13 +83940,13 @@ r - u_ov5640/coms1_reg_config/config_step_reg[1]/CLK (GTP_DFF_RE) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/DESCLK (GTP_ISERDES) clock pessimism 0.000 - 6.243 + 5.766 @@ -82771,15 +83954,15 @@ clock uncertainty 0.000 - 6.243 + 5.766 Hold time - 0.047 - 6.290 + 0.001 + 5.767 @@ -82788,27 +83971,27 @@ - 0.881 + 1.193 0 - 3 - u_ov5640/coms2_reg_config/clk_20k_regdiv/CLK - u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite/D + 8 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/CLKA + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[2] - clk_25m - clk_25m + ioclk1 + ioclk1 rise-rise 0.000 - 3.113 - 3.113 + 5.766 + 5.766 0.000 0.000 - 0.928 - 0.323 (34.8%) - 0.605 (65.2%) + 1.194 + 0.464 (38.9%) + 0.730 (61.1%) - Path #32: hold slack is 0.881(MET) + Path #39: hold slack is 1.193(MET) -
+
Location Delay Type @@ -82818,7 +84001,7 @@ Logical Resource - Clock clk_25m (rising edge) + Clock ioclk1 (rising edge) 0.000 0.000 @@ -82876,42 +84059,114 @@ td - 0.098 - 2.400 + 0.089 + 2.391 r - u_sys_pll/u_pll_e3/CLKOUT3 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=26) - 0.713 - 3.113 + net (fanout=7) + 0.605 + 2.996 - clk_25m + ddr_clk + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + + + + td + 0.000 + 2.996 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + + + + net (fanout=71) + 0.847 + 3.843 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.094 + 3.937 r - u_ov5640/coms2_reg_config/clk_20k_regdiv/CLK (GTP_DFF_RE) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + + + + net (fanout=3) + 0.605 + 4.542 + + u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKIN (GTP_IOCLKBUF) + + + + td + 0.306 + 4.848 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) + + + + net (fanout=28) + 0.918 + 5.766 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + + + + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/CLKA (GTP_DDC_E1) tco - 0.323 - 3.436 + 0.464 + 6.230 f - u_ov5640/coms2_reg_config/clk_20k_regdiv/Q (GTP_DFF_RE) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[2] (GTP_DDC_E1) - net (fanout=3) - 0.605 - 4.041 + net (fanout=8) + 0.730 + 6.960 - u_ov5640/coms2_reg_config/clk_20k_regdiv + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [2] @@ -82919,12 +84174,12 @@ f - u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite/D (GTP_DFF_SE) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[2] (GTP_ISERDES)
- +
Location Delay Type @@ -82934,7 +84189,7 @@ Logical Resource - Clock clk_25m (rising edge) + Clock ioclk1 (rising edge) 0.000 0.000 @@ -82992,32 +84247,104 @@ td - 0.098 - 2.400 + 0.089 + 2.391 r - u_sys_pll/u_pll_e3/CLKOUT3 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=26) - 0.713 - 3.113 + net (fanout=7) + 0.605 + 2.996 - clk_25m + ddr_clk + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + + + + td + 0.000 + 2.996 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + + + + net (fanout=71) + 0.847 + 3.843 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.094 + 3.937 r - u_ov5640/coms2_reg_config/clk_20k_regdiv_opposite/CLK (GTP_DFF_SE) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + + + + net (fanout=3) + 0.605 + 4.542 + + u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKIN (GTP_IOCLKBUF) + + + + td + 0.306 + 4.848 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) + + + + net (fanout=28) + 0.918 + 5.766 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + + + + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/DESCLK (GTP_ISERDES) clock pessimism 0.000 - 3.113 + 5.766 @@ -83025,15 +84352,15 @@ clock uncertainty 0.000 - 3.113 + 5.766 Hold time - 0.047 - 3.160 + 0.001 + 5.767 @@ -83042,27 +84369,27 @@ - 1.053 - 1 - 3 - u_ov5640/coms1_reg_config/clk_20k_regdiv/CLK - u_ov5640/coms1_reg_config/clk_20k_regdiv/D + 1.193 + 0 + 8 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/CLKA + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[0] - clk_25m - clk_25m + ioclk0 + ioclk0 rise-rise 0.000 - 3.113 - 3.113 + 5.619 + 5.619 0.000 0.000 - 1.100 - 0.495 (45.0%) - 0.605 (55.0%) + 1.194 + 0.464 (38.9%) + 0.730 (61.1%) - Path #33: hold slack is 1.053(MET) + Path #40: hold slack is 1.193(MET) -
+
Location Delay Type @@ -83072,7 +84399,7 @@ Logical Resource - Clock clk_25m (rising edge) + Clock ioclk0 (rising edge) 0.000 0.000 @@ -83130,66 +84457,114 @@ td - 0.098 - 2.400 + 0.089 + 2.391 r - u_sys_pll/u_pll_e3/CLKOUT3 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=26) - 0.713 - 3.113 + net (fanout=7) + 0.605 + 2.996 - clk_25m + ddr_clk + + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + + + + td + 0.000 + 2.996 r - u_ov5640/coms1_reg_config/clk_20k_regdiv/CLK (GTP_DFF_RE) + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - - tco - 0.323 - 3.436 - f - u_ov5640/coms1_reg_config/clk_20k_regdiv/Q (GTP_DFF_RE) + + net (fanout=71) + 0.847 + 3.843 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.094 + 3.937 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) net (fanout=3) 0.605 - 4.041 - - u_ov5640/coms1_reg_config/clk_20k_regdiv + 4.542 + + u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] - + - u_ov5640/coms1_reg_config/N12/I0 (GTP_LUT1) + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKIN (GTP_IOCLKBUF) - + td - 0.172 - 4.213 + 0.306 + 4.848 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) + + + + net (fanout=11) + 0.771 + 5.619 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + + + + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/CLKA (GTP_DDC_E1) + + + + tco + 0.464 + 6.083 f - u_ov5640/coms1_reg_config/N12/Z (GTP_LUT1) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[0] (GTP_DDC_E1) - net (fanout=1) - 0.000 - 4.213 + net (fanout=8) + 0.730 + 6.813 - u_ov5640/coms1_reg_config/N12 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [0] @@ -83197,12 +84572,12 @@ f - u_ov5640/coms1_reg_config/clk_20k_regdiv/D (GTP_DFF_RE) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[0] (GTP_ISERDES)
- +
Location Delay Type @@ -83212,7 +84587,7 @@ Logical Resource - Clock clk_25m (rising edge) + Clock ioclk0 (rising edge) 0.000 0.000 @@ -83270,32 +84645,104 @@ td - 0.098 - 2.400 + 0.089 + 2.391 r - u_sys_pll/u_pll_e3/CLKOUT3 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=26) - 0.713 - 3.113 + net (fanout=7) + 0.605 + 2.996 - clk_25m + ddr_clk + + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + + + + td + 0.000 + 2.996 r - u_ov5640/coms1_reg_config/clk_20k_regdiv/CLK (GTP_DFF_RE) + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + + + + net (fanout=71) + 0.847 + 3.843 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.094 + 3.937 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + + + + net (fanout=3) + 0.605 + 4.542 + + u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKIN (GTP_IOCLKBUF) + + + + td + 0.306 + 4.848 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) + + + + net (fanout=11) + 0.771 + 5.619 + + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + + + + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/DESCLK (GTP_ISERDES) clock pessimism 0.000 - 3.113 + 5.619 @@ -83303,15 +84750,15 @@ clock uncertainty 0.000 - 3.113 + 5.619 Hold time - 0.047 - 3.160 + 0.001 + 5.620 @@ -83323,24 +84770,24 @@ 1.19308 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/CLKA - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[0] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/CLKA + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[1] - ioclk1 - ioclk1 + ioclk0 + ioclk0 rise-rise 0.000 - 7.137 - 7.137 + 5.619 + 5.619 0.000 0.000 1.194 0.464 (38.9%) 0.730 (61.1%) - Path #34: hold slack is 1.193(MET) + Path #41: hold slack is 1.193(MET) -
+
Location Delay Type @@ -83350,7 +84797,7 @@ Logical Resource - Clock ioclk1 (rising edge) + Clock ioclk0 (rising edge) 0.000 0.000 @@ -83415,11 +84862,11 @@ - net (fanout=851) - 1.976 - 4.367 + net (fanout=7) + 0.605 + 2.996 - zoom_clk + ddr_clk @@ -83433,7 +84880,7 @@ td 0.000 - 4.367 + 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) @@ -83441,7 +84888,7 @@ net (fanout=71) 0.847 - 5.214 + 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin @@ -83457,7 +84904,7 @@ td 0.094 - 5.308 + 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) @@ -83465,7 +84912,7 @@ net (fanout=3) 0.605 - 5.913 + 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] @@ -83475,23 +84922,23 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKIN (GTP_IOCLKBUF) + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKIN (GTP_IOCLKBUF) td 0.306 - 6.219 + 4.848 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) - net (fanout=28) - 0.918 - 7.137 + net (fanout=11) + 0.771 + 5.619 - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] @@ -83499,23 +84946,23 @@ r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/CLKA (GTP_DDC_E1) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/CLKA (GTP_DDC_E1) tco 0.464 - 7.601 + 6.083 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[0] (GTP_DDC_E1) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[1] (GTP_DDC_E1) net (fanout=8) 0.730 - 8.331 + 6.813 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [0] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [1] @@ -83523,12 +84970,12 @@ f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[0] (GTP_ISERDES) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[1] (GTP_ISERDES)
- +
Location Delay Type @@ -83538,7 +84985,7 @@ Logical Resource - Clock ioclk1 (rising edge) + Clock ioclk0 (rising edge) 0.000 0.000 @@ -83603,11 +85050,11 @@ - net (fanout=851) - 1.976 - 4.367 + net (fanout=7) + 0.605 + 2.996 - zoom_clk + ddr_clk @@ -83621,7 +85068,7 @@ td 0.000 - 4.367 + 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) @@ -83629,7 +85076,7 @@ net (fanout=71) 0.847 - 5.214 + 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin @@ -83645,7 +85092,7 @@ td 0.094 - 5.308 + 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) @@ -83653,7 +85100,7 @@ net (fanout=3) 0.605 - 5.913 + 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] @@ -83663,23 +85110,23 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKIN (GTP_IOCLKBUF) + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKIN (GTP_IOCLKBUF) td 0.306 - 6.219 + 4.848 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) - net (fanout=28) - 0.918 - 7.137 + net (fanout=11) + 0.771 + 5.619 - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] @@ -83687,13 +85134,13 @@ r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/DESCLK (GTP_ISERDES) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/DESCLK (GTP_ISERDES) clock pessimism 0.000 - 7.137 + 5.619 @@ -83701,7 +85148,7 @@ clock uncertainty 0.000 - 7.137 + 5.619 @@ -83709,7 +85156,7 @@ Hold time 0.001 - 7.138 + 5.620 @@ -83721,24 +85168,24 @@ 1.193 0 8 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/CLKA - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[1] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/CLKA + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[2] - ioclk1 - ioclk1 + ioclk0 + ioclk0 rise-rise 0.000 - 7.137 - 7.137 + 5.619 + 5.619 0.000 0.000 1.194 0.464 (38.9%) 0.730 (61.1%) - Path #35: hold slack is 1.193(MET) + Path #42: hold slack is 1.193(MET) -
+
Location Delay Type @@ -83748,7 +85195,7 @@ Logical Resource - Clock ioclk1 (rising edge) + Clock ioclk0 (rising edge) 0.000 0.000 @@ -83813,11 +85260,11 @@ - net (fanout=851) - 1.976 - 4.367 + net (fanout=7) + 0.605 + 2.996 - zoom_clk + ddr_clk @@ -83831,7 +85278,7 @@ td 0.000 - 4.367 + 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) @@ -83839,7 +85286,7 @@ net (fanout=71) 0.847 - 5.214 + 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin @@ -83855,7 +85302,7 @@ td 0.094 - 5.308 + 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) @@ -83863,7 +85310,7 @@ net (fanout=3) 0.605 - 5.913 + 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] @@ -83873,23 +85320,23 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKIN (GTP_IOCLKBUF) + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKIN (GTP_IOCLKBUF) td 0.306 - 6.219 + 4.848 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) - net (fanout=28) - 0.918 - 7.137 + net (fanout=11) + 0.771 + 5.619 - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] @@ -83897,23 +85344,23 @@ r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/CLKA (GTP_DDC_E1) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/CLKA (GTP_DDC_E1) tco 0.464 - 7.601 + 6.083 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[1] (GTP_DDC_E1) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[2] (GTP_DDC_E1) net (fanout=8) 0.730 - 8.331 + 6.813 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [1] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [2] @@ -83921,12 +85368,12 @@ f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[1] (GTP_ISERDES) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[2] (GTP_ISERDES)
- +
Location Delay Type @@ -83936,7 +85383,7 @@ Logical Resource - Clock ioclk1 (rising edge) + Clock ioclk0 (rising edge) 0.000 0.000 @@ -84001,11 +85448,11 @@ - net (fanout=851) - 1.976 - 4.367 + net (fanout=7) + 0.605 + 2.996 - zoom_clk + ddr_clk @@ -84019,7 +85466,7 @@ td 0.000 - 4.367 + 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) @@ -84027,7 +85474,7 @@ net (fanout=71) 0.847 - 5.214 + 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin @@ -84043,7 +85490,7 @@ td 0.094 - 5.308 + 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) @@ -84051,7 +85498,7 @@ net (fanout=3) 0.605 - 5.913 + 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] @@ -84061,23 +85508,23 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKIN (GTP_IOCLKBUF) + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKIN (GTP_IOCLKBUF) td 0.306 - 6.219 + 4.848 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) - net (fanout=28) - 0.918 - 7.137 + net (fanout=11) + 0.771 + 5.619 - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] @@ -84085,13 +85532,13 @@ r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/DESCLK (GTP_ISERDES) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/DESCLK (GTP_ISERDES) clock pessimism 0.000 - 7.137 + 5.619 @@ -84099,7 +85546,7 @@ clock uncertainty 0.000 - 7.137 + 5.619 @@ -84107,7 +85554,7 @@ Hold time 0.001 - 7.138 + 5.620 @@ -84115,28 +85562,49 @@ +
+ + + Slack + Logic Levels + High Fanout + Start Point + End Point + Exception + Launch Clock + Capture Clock + Clock Edges + Clock Skew + Launch Clock Delay + Capture Clock Delay + Clock Pessimism Removal + Requirement + Data delay + Logic delay + Route delay + - 1.193 - 0 - 8 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/CLKA - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[2] + 1.564 + 1 + 1809 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[0]/C - ioclk1 - ioclk1 + clk_200m + clk_200m rise-rise 0.000 - 7.137 - 7.137 - 0.000 + 5.192 + 5.192 0.000 - 1.194 - 0.464 (38.9%) - 0.730 (61.1%) + 5.000 + 2.744 + 0.329 (12.0%) + 2.415 (88.0%) - Path #36: hold slack is 1.193(MET) + Path #1: recovery slack is 1.564(MET) -
+
Location Delay Type @@ -84146,7 +85614,7 @@ Logical Resource - Clock ioclk1 (rising edge) + Clock clk_200m (rising edge) 0.000 0.000 @@ -84211,11 +85679,11 @@ - net (fanout=851) - 1.976 - 4.367 + net (fanout=7) + 0.605 + 2.996 - zoom_clk + ddr_clk @@ -84229,15 +85697,15 @@ td 0.000 - 4.367 + 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) net (fanout=71) - 0.847 - 5.214 + 2.196 + 5.192 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin @@ -84246,72 +85714,48 @@ - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - - - - td - 0.094 - 5.308 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - - - - net (fanout=3) - 0.605 - 5.913 - - u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKIN (GTP_IOCLKBUF) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/CLK (GTP_DFF_C) - - td - 0.306 - 6.219 + + tco + 0.329 + 5.521 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/Q (GTP_DFF_C) - net (fanout=28) - 0.918 - 7.137 - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] + net (fanout=1) + 0.000 + 5.521 + + u_axi_ddr_top/I_ipsxb_ddr_top/ddr_rstn - + - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/CLKA (GTP_DDC_E1) + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N17/I (GTP_INV) - tco - 0.464 - 7.601 + td + 0.000 + 5.521 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[2] (GTP_DDC_E1) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N17/Z (GTP_INV) - net (fanout=8) - 0.730 - 8.331 + net (fanout=1809) + 2.415 + 7.936 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/ififo_raddr [2] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/rst @@ -84319,12 +85763,12 @@ f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[2] (GTP_ISERDES) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[0]/C (GTP_DFF_CE)
- +
Location Delay Type @@ -84334,10 +85778,10 @@ Logical Resource - Clock ioclk1 (rising edge) + Clock clk_200m (rising edge) - 0.000 - 0.000 + 5.000 + 5.000 r @@ -84345,7 +85789,7 @@ clk0.000 - 0.000 + 5.000rclk (port) @@ -84353,7 +85797,7 @@ net (fanout=1) 0.000 - 0.000 + 5.000 clk @@ -84369,7 +85813,7 @@ td 1.211 - 1.211 + 6.211 r clk_ibuf/O (GTP_INBUF) @@ -84377,7 +85821,7 @@ net (fanout=1) 1.091 - 2.302 + 7.302 nt_clk @@ -84393,17 +85837,17 @@ td 0.089 - 2.391 + 7.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) - 1.976 - 4.367 + net (fanout=7) + 0.605 + 7.996 - zoom_clk + ddr_clk @@ -84417,95 +85861,47 @@ td 0.000 - 4.367 + 7.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) net (fanout=71) - 0.847 - 5.214 + 2.196 + 10.192 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - - - - td - 0.094 - 5.308 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - - - - net (fanout=3) - 0.605 - 5.913 - - u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKIN (GTP_IOCLKBUF) - - - - td - 0.306 - 6.219 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_1/CLKOUT (GTP_IOCLKBUF) - - - - net (fanout=28) - 0.918 - 7.137 - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [1] - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/DESCLK (GTP_ISERDES) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[0]/CLK (GTP_DFF_CE) clock pessimism 0.000 - 7.137 + 10.192 clock uncertainty - 0.000 - 7.137 + -0.150 + 10.042 - Hold time + Recovery time - 0.001 - 7.138 + -0.542 + 9.500 @@ -84514,27 +85910,27 @@ - 1.193 - 0 - 8 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/CLKA - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[0] + 1.564 + 1 + 1809 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[1]/C - ioclk0 - ioclk0 + clk_200m + clk_200m rise-rise 0.000 - 6.990 - 6.990 + 5.192 + 5.192 0.000 - 0.000 - 1.194 - 0.464 (38.9%) - 0.730 (61.1%) + 5.000 + 2.744 + 0.329 (12.0%) + 2.415 (88.0%) - Path #37: hold slack is 1.193(MET) + Path #2: recovery slack is 1.564(MET) -
+
Location Delay Type @@ -84544,7 +85940,7 @@ Logical Resource - Clock ioclk0 (rising edge) + Clock clk_200m (rising edge) 0.000 0.000 @@ -84609,11 +86005,11 @@ - net (fanout=851) - 1.976 - 4.367 + net (fanout=7) + 0.605 + 2.996 - zoom_clk + ddr_clk @@ -84627,15 +86023,15 @@ td 0.000 - 4.367 + 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) net (fanout=71) - 0.847 - 5.214 + 2.196 + 5.192 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin @@ -84644,72 +86040,48 @@ - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - - - - td - 0.094 - 5.308 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - - - - net (fanout=3) - 0.605 - 5.913 - - u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKIN (GTP_IOCLKBUF) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/CLK (GTP_DFF_C) - - td - 0.306 - 6.219 + + tco + 0.329 + 5.521 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/Q (GTP_DFF_C) - net (fanout=11) - 0.771 - 6.990 - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + net (fanout=1) + 0.000 + 5.521 + + u_axi_ddr_top/I_ipsxb_ddr_top/ddr_rstn - + - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/CLKA (GTP_DDC_E1) + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N17/I (GTP_INV) - tco - 0.464 - 7.454 + td + 0.000 + 5.521 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[0] (GTP_DDC_E1) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N17/Z (GTP_INV) - net (fanout=8) - 0.730 - 8.184 + net (fanout=1809) + 2.415 + 7.936 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [0] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/rst @@ -84717,12 +86089,12 @@ f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[0] (GTP_ISERDES) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[1]/C (GTP_DFF_CE)
- +
Location Delay Type @@ -84732,10 +86104,10 @@ Logical Resource - Clock ioclk0 (rising edge) + Clock clk_200m (rising edge) - 0.000 - 0.000 + 5.000 + 5.000 r @@ -84743,7 +86115,7 @@ clk0.000 - 0.000 + 5.000rclk (port) @@ -84751,7 +86123,7 @@ net (fanout=1) 0.000 - 0.000 + 5.000 clk @@ -84767,7 +86139,7 @@ td 1.211 - 1.211 + 6.211 r clk_ibuf/O (GTP_INBUF) @@ -84775,7 +86147,7 @@ net (fanout=1) 1.091 - 2.302 + 7.302 nt_clk @@ -84791,17 +86163,17 @@ td 0.089 - 2.391 + 7.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) - 1.976 - 4.367 + net (fanout=7) + 0.605 + 7.996 - zoom_clk + ddr_clk @@ -84815,95 +86187,47 @@ td 0.000 - 4.367 + 7.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) net (fanout=71) - 0.847 - 5.214 + 2.196 + 10.192 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - - - - td - 0.094 - 5.308 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - - - - net (fanout=3) - 0.605 - 5.913 - - u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKIN (GTP_IOCLKBUF) - - - - td - 0.306 - 6.219 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) - - - - net (fanout=11) - 0.771 - 6.990 - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/DESCLK (GTP_ISERDES) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[1]/CLK (GTP_DFF_CE) clock pessimism 0.000 - 6.990 + 10.192 clock uncertainty - 0.000 - 6.990 + -0.150 + 10.042 - Hold time + Recovery time - 0.001 - 6.991 + -0.542 + 9.500 @@ -84912,27 +86236,27 @@ - 1.193 - 0 - 8 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/CLKA - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[1] + 1.564 + 1 + 1809 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[2]/C - ioclk0 - ioclk0 + clk_200m + clk_200m rise-rise 0.000 - 6.990 - 6.990 - 0.000 + 5.192 + 5.192 0.000 - 1.194 - 0.464 (38.9%) - 0.730 (61.1%) + 5.000 + 2.744 + 0.329 (12.0%) + 2.415 (88.0%) - Path #38: hold slack is 1.193(MET) + Path #3: recovery slack is 1.564(MET) -
+
Location Delay Type @@ -84942,7 +86266,7 @@ Logical Resource - Clock ioclk0 (rising edge) + Clock clk_200m (rising edge) 0.000 0.000 @@ -85007,11 +86331,11 @@ - net (fanout=851) - 1.976 - 4.367 + net (fanout=7) + 0.605 + 2.996 - zoom_clk + ddr_clk @@ -85025,15 +86349,15 @@ td 0.000 - 4.367 + 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) net (fanout=71) - 0.847 - 5.214 + 2.196 + 5.192 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin @@ -85042,72 +86366,48 @@ - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - - - - td - 0.094 - 5.308 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - - - - net (fanout=3) - 0.605 - 5.913 - - u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKIN (GTP_IOCLKBUF) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/CLK (GTP_DFF_C) - - td - 0.306 - 6.219 + + tco + 0.329 + 5.521 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/Q (GTP_DFF_C) - net (fanout=11) - 0.771 - 6.990 - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + net (fanout=1) + 0.000 + 5.521 + + u_axi_ddr_top/I_ipsxb_ddr_top/ddr_rstn - + - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/CLKA (GTP_DDC_E1) + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N17/I (GTP_INV) - tco - 0.464 - 7.454 + td + 0.000 + 5.521 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[1] (GTP_DDC_E1) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N17/Z (GTP_INV) - net (fanout=8) - 0.730 - 8.184 + net (fanout=1809) + 2.415 + 7.936 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [1] + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/rst @@ -85115,12 +86415,12 @@ f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[1] (GTP_ISERDES) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[2]/C (GTP_DFF_CE)
- +
Location Delay Type @@ -85130,10 +86430,10 @@ Logical Resource - Clock ioclk0 (rising edge) + Clock clk_200m (rising edge) - 0.000 - 0.000 + 5.000 + 5.000 r @@ -85141,7 +86441,7 @@ clk0.000 - 0.000 + 5.000rclk (port) @@ -85149,7 +86449,7 @@ net (fanout=1) 0.000 - 0.000 + 5.000 clk @@ -85165,7 +86465,7 @@ td 1.211 - 1.211 + 6.211 r clk_ibuf/O (GTP_INBUF) @@ -85173,7 +86473,7 @@ net (fanout=1) 1.091 - 2.302 + 7.302 nt_clk @@ -85189,17 +86489,17 @@ td 0.089 - 2.391 + 7.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) - 1.976 - 4.367 + net (fanout=7) + 0.605 + 7.996 - zoom_clk + ddr_clk @@ -85213,95 +86513,47 @@ td 0.000 - 4.367 + 7.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) net (fanout=71) - 0.847 - 5.214 + 2.196 + 10.192 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - - - - td - 0.094 - 5.308 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - - - - net (fanout=3) - 0.605 - 5.913 - - u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKIN (GTP_IOCLKBUF) - - - - td - 0.306 - 6.219 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) - - - - net (fanout=11) - 0.771 - 6.990 - - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/DESCLK (GTP_ISERDES) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[2]/CLK (GTP_DFF_CE) clock pessimism 0.000 - 6.990 + 10.192 clock uncertainty - 0.000 - 6.990 + -0.150 + 10.042 - Hold time + Recovery time - 0.001 - 6.991 + -0.542 + 9.500 @@ -85310,27 +86562,27 @@ - 1.193 + 4.552 0 - 8 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/CLKA - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[2] + 181 + u_zoom_rst/rst/CLK + u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.rbin[0]/C - ioclk0 - ioclk0 + clk_1080p60Hz + clk_1080p60Hz rise-rise 0.000 - 6.990 - 6.990 - 0.000 + 7.588 + 7.588 0.000 - 1.194 - 0.464 (38.9%) - 0.730 (61.1%) + 6.736 + 1.492 + 0.323 (21.6%) + 1.169 (78.4%) - Path #39: hold slack is 1.193(MET) + Path #4: recovery slack is 4.552(MET) -
+
Location Delay Type @@ -85340,7 +86592,7 @@ Logical Resource - Clock ioclk0 (rising edge) + Clock clk_1080p60Hz (rising edge) 0.000 0.000 @@ -85395,69 +86647,21 @@ u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) - - - td - 0.089 - 2.391 - r - u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - - - - net (fanout=851) - 1.976 - 4.367 - - zoom_clk - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - - - - td - 0.000 - 4.367 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - - - - net (fanout=71) - 0.847 - 5.214 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 - 5.308 + 2.396 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) - 0.605 - 5.913 + net (fanout=2825) + 3.127 + 5.523 - u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + rd3_clk @@ -85465,23 +86669,23 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKIN (GTP_IOCLKBUF) + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) td - 0.306 - 6.219 + 0.094 + 5.617 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) + U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=11) - 0.771 - 6.990 + net (fanout=844) + 1.971 + 7.588 - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + zoom_clk @@ -85489,23 +86693,23 @@ r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/CLKA (GTP_DDC_E1) + u_zoom_rst/rst/CLK (GTP_DFF_P) tco - 0.464 - 7.454 + 0.323 + 7.911 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/u_ddc_dqs/IFIFO_RADDR[2] (GTP_DDC_E1) + u_zoom_rst/rst/Q (GTP_DFF_P) - net (fanout=8) - 0.730 - 8.184 + net (fanout=181) + 1.169 + 9.080 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/ififo_raddr [2] + zoom_rst @@ -85513,12 +86717,12 @@ f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/RADDR[2] (GTP_ISERDES) + u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.rbin[0]/C (GTP_DFF_CE)
- +
Location Delay Type @@ -85528,10 +86732,10 @@ Logical Resource - Clock ioclk0 (rising edge) + Clock clk_1080p60Hz (rising edge) - 0.000 - 0.000 + 6.736 + 6.736 r @@ -85539,7 +86743,7 @@ clk0.000 - 0.000 + 6.736rclk (port) @@ -85547,7 +86751,7 @@ net (fanout=1) 0.000 - 0.000 + 6.736 clk @@ -85563,7 +86767,7 @@ td 1.211 - 1.211 + 7.947 r clk_ibuf/O (GTP_INBUF) @@ -85571,7 +86775,7 @@ net (fanout=1) 1.091 - 2.302 + 9.038 nt_clk @@ -85583,69 +86787,21 @@ u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) - - - td - 0.089 - 2.391 - r - u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - - - - net (fanout=851) - 1.976 - 4.367 - - zoom_clk - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - - - - td - 0.000 - 4.367 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - - - - net (fanout=71) - 0.847 - 5.214 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 - 5.308 + 9.132 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) - 0.605 - 5.913 + net (fanout=2825) + 3.127 + 12.259 - u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + rd3_clk @@ -85653,23 +86809,23 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKIN (GTP_IOCLKBUF) + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) td - 0.306 - 6.219 + 0.094 + 12.353 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_IOCLKBUF_0/CLKOUT (GTP_IOCLKBUF) + U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=11) - 0.771 - 6.990 + net (fanout=844) + 1.971 + 14.324 - u_axi_ddr_top/I_ipsxb_ddr_top/ioclk [0] + zoom_clk @@ -85677,29 +86833,29 @@ r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dq_loop[0].DQ0_GTP_ISERDES/DESCLK (GTP_ISERDES) + u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.rbin[0]/CLK (GTP_DFF_CE) clock pessimism 0.000 - 6.990 + 14.324 clock uncertainty - 0.000 - 6.990 + -0.150 + 14.174 - Hold time + Recovery time - 0.001 - 6.991 + -0.542 + 13.632 @@ -85707,49 +86863,28 @@ -
- - - Slack - Logic Levels - High Fanout - Start Point - End Point - Exception - Launch Clock - Capture Clock - Clock Edges - Clock Skew - Launch Clock Delay - Capture Clock Delay - Clock Pessimism Removal - Requirement - Data delay - Logic delay - Route delay - - 1.564 - 1 - 1809 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[0]/C + 4.552 + 0 + 181 + u_zoom_rst/rst/CLK + u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/C - clk_200m - clk_200m + clk_1080p60Hz + clk_1080p60Hz rise-rise 0.000 - 6.563 - 6.563 + 7.588 + 7.588 0.000 - 5.000 - 2.744 - 0.329 (12.0%) - 2.415 (88.0%) + 6.736 + 1.492 + 0.323 (21.6%) + 1.169 (78.4%) - Path #1: recovery slack is 1.564(MET) + Path #5: recovery slack is 4.552(MET) -
+
Location Delay Type @@ -85759,7 +86894,7 @@ Logical Resource - Clock clk_200m (rising edge) + Clock clk_1080p60Hz (rising edge) 0.000 0.000 @@ -85817,18 +86952,18 @@ td - 0.089 - 2.391 + 0.094 + 2.396 r - u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=851) - 1.976 - 4.367 + net (fanout=2825) + 3.127 + 5.523 - zoom_clk + rd3_clk @@ -85836,23 +86971,23 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) td - 0.000 - 4.367 + 0.094 + 5.617 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=71) - 2.196 - 6.563 + net (fanout=844) + 1.971 + 7.588 - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + zoom_clk @@ -85860,47 +86995,23 @@ r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/CLK (GTP_DFF_C) + u_zoom_rst/rst/CLK (GTP_DFF_P) tco - 0.329 - 6.892 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/Q (GTP_DFF_C) - - - - net (fanout=1) - 0.000 - 6.892 - - u_axi_ddr_top/I_ipsxb_ddr_top/ddr_rstn - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N17/I (GTP_INV) - - - - td - 0.000 - 6.892 + 0.323 + 7.911 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N17/Z (GTP_INV) + u_zoom_rst/rst/Q (GTP_DFF_P) - net (fanout=1809) - 2.415 - 9.307 + net (fanout=181) + 1.169 + 9.080 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/rst + zoom_rst @@ -85908,12 +87019,12 @@ f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[0]/C (GTP_DFF_CE) + u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/C (GTP_DFF_CE)
- +
Location Delay Type @@ -85923,10 +87034,10 @@ Logical Resource - Clock clk_200m (rising edge) + Clock clk_1080p60Hz (rising edge) - 5.000 - 5.000 + 6.736 + 6.736 r @@ -85934,7 +87045,7 @@ clk0.000 - 5.000 + 6.736rclk (port) @@ -85942,7 +87053,7 @@ net (fanout=1) 0.000 - 5.000 + 6.736 clk @@ -85958,7 +87069,7 @@ td 1.211 - 6.211 + 7.947 r clk_ibuf/O (GTP_INBUF) @@ -85966,7 +87077,7 @@ net (fanout=1) 1.091 - 7.302 + 9.038 nt_clk @@ -85981,18 +87092,18 @@ td - 0.089 - 7.391 + 0.094 + 9.132 r - u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=851) - 1.976 - 9.367 + net (fanout=2825) + 3.127 + 12.259 - zoom_clk + rd3_clk @@ -86000,23 +87111,23 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) td - 0.000 - 9.367 + 0.094 + 12.353 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=71) - 2.196 - 11.563 + net (fanout=844) + 1.971 + 14.324 - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + zoom_clk @@ -86024,13 +87135,13 @@ r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[0]/CLK (GTP_DFF_CE) + u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.rbin[1]/CLK (GTP_DFF_CE) clock pessimism 0.000 - 11.563 + 14.324 @@ -86038,7 +87149,7 @@ clock uncertainty -0.150 - 11.413 + 14.174 @@ -86046,7 +87157,7 @@ Recovery time -0.542 - 10.871 + 13.632 @@ -86055,27 +87166,27 @@ - 1.564 - 1 - 1809 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[1]/C + 4.552 + 0 + 181 + u_zoom_rst/rst/CLK + u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.rbin[2]/C - clk_200m - clk_200m + clk_1080p60Hz + clk_1080p60Hz rise-rise 0.000 - 6.563 - 6.563 + 7.588 + 7.588 0.000 - 5.000 - 2.744 - 0.329 (12.0%) - 2.415 (88.0%) + 6.736 + 1.492 + 0.323 (21.6%) + 1.169 (78.4%) - Path #2: recovery slack is 1.564(MET) + Path #6: recovery slack is 4.552(MET) -
+
Location Delay Type @@ -86085,7 +87196,7 @@ Logical Resource - Clock clk_200m (rising edge) + Clock clk_1080p60Hz (rising edge) 0.000 0.000 @@ -86143,18 +87254,18 @@ td - 0.089 - 2.391 + 0.094 + 2.396 r - u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=851) - 1.976 - 4.367 + net (fanout=2825) + 3.127 + 5.523 - zoom_clk + rd3_clk @@ -86162,23 +87273,23 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) td - 0.000 - 4.367 + 0.094 + 5.617 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=71) - 2.196 - 6.563 + net (fanout=844) + 1.971 + 7.588 - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + zoom_clk @@ -86186,47 +87297,23 @@ r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/CLK (GTP_DFF_C) + u_zoom_rst/rst/CLK (GTP_DFF_P) tco - 0.329 - 6.892 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/Q (GTP_DFF_C) - - - - net (fanout=1) - 0.000 - 6.892 - - u_axi_ddr_top/I_ipsxb_ddr_top/ddr_rstn - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N17/I (GTP_INV) - - - - td - 0.000 - 6.892 + 0.323 + 7.911 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N17/Z (GTP_INV) + u_zoom_rst/rst/Q (GTP_DFF_P) - net (fanout=1809) - 2.415 - 9.307 + net (fanout=181) + 1.169 + 9.080 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/rst + zoom_rst @@ -86234,12 +87321,12 @@ f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[1]/C (GTP_DFF_CE) + u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.rbin[2]/C (GTP_DFF_CE)
- +
Location Delay Type @@ -86249,10 +87336,10 @@ Logical Resource - Clock clk_200m (rising edge) + Clock clk_1080p60Hz (rising edge) - 5.000 - 5.000 + 6.736 + 6.736 r @@ -86260,7 +87347,7 @@ clk0.000 - 5.000 + 6.736rclk (port) @@ -86268,7 +87355,7 @@ net (fanout=1) 0.000 - 5.000 + 6.736 clk @@ -86284,7 +87371,7 @@ td 1.211 - 6.211 + 7.947 r clk_ibuf/O (GTP_INBUF) @@ -86292,7 +87379,7 @@ net (fanout=1) 1.091 - 7.302 + 9.038 nt_clk @@ -86307,18 +87394,18 @@ td - 0.089 - 7.391 + 0.094 + 9.132 r - u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=851) - 1.976 - 9.367 + net (fanout=2825) + 3.127 + 12.259 - zoom_clk + rd3_clk @@ -86326,23 +87413,23 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) td - 0.000 - 9.367 + 0.094 + 12.353 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=71) - 2.196 - 11.563 + net (fanout=844) + 1.971 + 14.324 - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + zoom_clk @@ -86350,13 +87437,13 @@ r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[1]/CLK (GTP_DFF_CE) + u_ddr_addr_ctr/u_rd1_addr_ctr/u_rd1_ddr_addr_fifo1/U_ipml_fifo_rd1_ddr_addr_fifo1/U_ipml_fifo_ctrl/SYN_CTRL.rbin[2]/CLK (GTP_DFF_CE) clock pessimism 0.000 - 11.563 + 14.324 @@ -86364,7 +87451,7 @@ clock uncertainty -0.150 - 11.413 + 14.174 @@ -86372,7 +87459,7 @@ Recovery time -0.542 - 10.871 + 13.632 @@ -86381,27 +87468,27 @@ - 1.564 + 6.273 1 - 1809 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[2]/C + 2275 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[0]/C - clk_200m - clk_200m + ddrphy_clkin + ddrphy_clkin rise-rise 0.000 - 6.563 - 6.563 + 7.688 + 7.688 0.000 - 5.000 - 2.744 - 0.329 (12.0%) - 2.415 (88.0%) + 10.000 + 3.035 + 0.329 (10.8%) + 2.706 (89.2%) - Path #3: recovery slack is 1.564(MET) + Path #7: recovery slack is 6.273(MET) -
+
Location Delay Type @@ -86411,7 +87498,7 @@ Logical Resource - Clock clk_200m (rising edge) + Clock ddrphy_clkin (rising edge) 0.000 0.000 @@ -86476,11 +87563,11 @@ - net (fanout=851) - 1.976 - 4.367 + net (fanout=7) + 0.605 + 2.996 - zoom_clk + ddr_clk @@ -86494,15 +87581,15 @@ td 0.000 - 4.367 + 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) net (fanout=71) - 2.196 - 6.563 + 0.847 + 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin @@ -86511,24 +87598,72 @@ + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.094 + 3.937 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/CLK (GTP_DFF_C) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + + + + net (fanout=3) + 0.605 + 4.542 + + u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) + + + + td + 0.000 + 4.542 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + + + + net (fanout=5817) + 3.146 + 7.688 + + u_axi_ddr_top/clk + + + + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/CLK (GTP_DFF_C) tco 0.329 - 6.892 + 8.017 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/Q (GTP_DFF_C) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/Q (GTP_DFF_C) net (fanout=1) 0.000 - 6.892 + 8.017 - u_axi_ddr_top/I_ipsxb_ddr_top/ddr_rstn + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n @@ -86536,23 +87671,23 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N17/I (GTP_INV) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/N0/I (GTP_INV) td 0.000 - 6.892 + 8.017 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N17/Z (GTP_INV) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/N0/Z (GTP_INV) - net (fanout=1809) - 2.415 - 9.307 + net (fanout=2275) + 2.706 + 10.723 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/rst + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/N0 @@ -86560,12 +87695,12 @@ f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[2]/C (GTP_DFF_CE) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[0]/C (GTP_DFF_C)
- +
Location Delay Type @@ -86575,10 +87710,10 @@ Logical Resource - Clock clk_200m (rising edge) + Clock ddrphy_clkin (rising edge) - 5.000 - 5.000 + 10.000 + 10.000 r @@ -86586,7 +87721,7 @@ clk0.000 - 5.000 + 10.000rclk (port) @@ -86594,7 +87729,7 @@ net (fanout=1) 0.000 - 5.000 + 10.000 clk @@ -86610,7 +87745,7 @@ td 1.211 - 6.211 + 11.211 r clk_ibuf/O (GTP_INBUF) @@ -86618,7 +87753,7 @@ net (fanout=1) 1.091 - 7.302 + 12.302 nt_clk @@ -86634,17 +87769,17 @@ td 0.089 - 7.391 + 12.391 r u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=851) - 1.976 - 9.367 + net (fanout=7) + 0.605 + 12.996 - zoom_clk + ddr_clk @@ -86658,15 +87793,15 @@ td 0.000 - 9.367 + 12.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) net (fanout=71) - 2.196 - 11.563 + 0.847 + 13.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin @@ -86675,14 +87810,62 @@ + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.094 + 13.937 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/cnt[2]/CLK (GTP_DFF_CE) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + + + + net (fanout=3) + 0.605 + 14.542 + + u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) + + + + td + 0.000 + 14.542 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + + + + net (fanout=5817) + 3.146 + 17.688 + + u_axi_ddr_top/clk + + + + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[0]/CLK (GTP_DFF_C) clock pessimism 0.000 - 11.563 + 17.688 @@ -86690,7 +87873,7 @@ clock uncertainty -0.150 - 11.413 + 17.538 @@ -86698,7 +87881,7 @@ Recovery time -0.542 - 10.871 + 16.996 @@ -86711,23 +87894,23 @@ 1 2275 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[0]/C + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[1]/C ddrphy_clkin ddrphy_clkin rise-rise 0.000 - 9.059 - 9.059 + 7.688 + 7.688 0.000 10.000 3.035 0.329 (10.8%) 2.706 (89.2%) - Path #4: recovery slack is 6.273(MET) + Path #8: recovery slack is 6.273(MET) -
+
Location Delay Type @@ -86802,11 +87985,11 @@ - net (fanout=851) - 1.976 - 4.367 + net (fanout=7) + 0.605 + 2.996 - zoom_clk + ddr_clk @@ -86820,7 +88003,7 @@ td 0.000 - 4.367 + 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) @@ -86828,7 +88011,7 @@ net (fanout=71) 0.847 - 5.214 + 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin @@ -86844,7 +88027,7 @@ td 0.094 - 5.308 + 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) @@ -86852,7 +88035,7 @@ net (fanout=3) 0.605 - 5.913 + 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] @@ -86868,7 +88051,7 @@ td 0.000 - 5.913 + 4.542 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) @@ -86876,7 +88059,7 @@ net (fanout=5817) 3.146 - 9.059 + 7.688 u_axi_ddr_top/clk @@ -86892,7 +88075,7 @@ tco 0.329 - 9.388 + 8.017 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/Q (GTP_DFF_C) @@ -86900,7 +88083,7 @@ net (fanout=1) 0.000 - 9.388 + 8.017 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n @@ -86916,7 +88099,7 @@ td 0.000 - 9.388 + 8.017 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/N0/Z (GTP_INV) @@ -86924,7 +88107,7 @@ net (fanout=2275) 2.706 - 12.094 + 10.723 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/N0 @@ -86934,12 +88117,12 @@ f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[0]/C (GTP_DFF_C) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[1]/C (GTP_DFF_C)
- +
Location Delay Type @@ -87014,11 +88197,11 @@ - net (fanout=851) - 1.976 - 14.367 + net (fanout=7) + 0.605 + 12.996 - zoom_clk + ddr_clk @@ -87032,7 +88215,7 @@ td 0.000 - 14.367 + 12.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) @@ -87040,7 +88223,7 @@ net (fanout=71) 0.847 - 15.214 + 13.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin @@ -87056,7 +88239,7 @@ td 0.094 - 15.308 + 13.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) @@ -87064,7 +88247,7 @@ net (fanout=3) 0.605 - 15.913 + 14.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] @@ -87080,7 +88263,7 @@ td 0.000 - 15.913 + 14.542 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) @@ -87088,7 +88271,7 @@ net (fanout=5817) 3.146 - 19.059 + 17.688 u_axi_ddr_top/clk @@ -87098,13 +88281,13 @@ r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[0]/CLK (GTP_DFF_C) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[1]/CLK (GTP_DFF_C) clock pessimism 0.000 - 19.059 + 17.688 @@ -87112,7 +88295,7 @@ clock uncertainty -0.150 - 18.909 + 17.538 @@ -87120,7 +88303,7 @@ Recovery time -0.542 - 18.367 + 16.996 @@ -87133,23 +88316,23 @@ 1 2275 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[1]/C + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[2]/C ddrphy_clkin ddrphy_clkin rise-rise 0.000 - 9.059 - 9.059 + 7.688 + 7.688 0.000 10.000 3.035 0.329 (10.8%) 2.706 (89.2%) - Path #5: recovery slack is 6.273(MET) + Path #9: recovery slack is 6.273(MET) -
+
Location Delay Type @@ -87224,11 +88407,11 @@ - net (fanout=851) - 1.976 - 4.367 + net (fanout=7) + 0.605 + 2.996 - zoom_clk + ddr_clk @@ -87242,7 +88425,7 @@ td 0.000 - 4.367 + 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) @@ -87250,7 +88433,7 @@ net (fanout=71) 0.847 - 5.214 + 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin @@ -87266,7 +88449,7 @@ td 0.094 - 5.308 + 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) @@ -87274,7 +88457,7 @@ net (fanout=3) 0.605 - 5.913 + 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] @@ -87290,7 +88473,7 @@ td 0.000 - 5.913 + 4.542 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) @@ -87298,7 +88481,7 @@ net (fanout=5817) 3.146 - 9.059 + 7.688 u_axi_ddr_top/clk @@ -87314,7 +88497,7 @@ tco 0.329 - 9.388 + 8.017 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/Q (GTP_DFF_C) @@ -87322,7 +88505,7 @@ net (fanout=1) 0.000 - 9.388 + 8.017 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n @@ -87338,7 +88521,7 @@ td 0.000 - 9.388 + 8.017 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/N0/Z (GTP_INV) @@ -87346,7 +88529,7 @@ net (fanout=2275) 2.706 - 12.094 + 10.723 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/N0 @@ -87356,12 +88539,12 @@ f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[1]/C (GTP_DFF_C) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[2]/C (GTP_DFF_C)
- +
Location Delay Type @@ -87436,11 +88619,11 @@ - net (fanout=851) - 1.976 - 14.367 + net (fanout=7) + 0.605 + 12.996 - zoom_clk + ddr_clk @@ -87454,7 +88637,7 @@ td 0.000 - 14.367 + 12.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) @@ -87462,7 +88645,7 @@ net (fanout=71) 0.847 - 15.214 + 13.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin @@ -87478,7 +88661,7 @@ td 0.094 - 15.308 + 13.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) @@ -87486,7 +88669,7 @@ net (fanout=3) 0.605 - 15.913 + 14.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] @@ -87502,7 +88685,7 @@ td 0.000 - 15.913 + 14.542 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) @@ -87510,7 +88693,7 @@ net (fanout=5817) 3.146 - 19.059 + 17.688 u_axi_ddr_top/clk @@ -87520,13 +88703,13 @@ r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[1]/CLK (GTP_DFF_C) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[2]/CLK (GTP_DFF_C) clock pessimism 0.000 - 19.059 + 17.688 @@ -87534,7 +88717,7 @@ clock uncertainty -0.150 - 18.909 + 17.538 @@ -87542,7 +88725,7 @@ Recovery time -0.542 - 18.367 + 16.996 @@ -87551,27 +88734,27 @@ - 6.273 - 1 - 2275 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[2]/C + 9.504 + 0 + 2548 + sync_vg_100m/CLK + adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[5]/C - ddrphy_clkin - ddrphy_clkin + clk_720p60Hz + clk_720p60Hz rise-rise 0.000 - 9.059 - 9.059 + 8.070 + 8.070 0.000 - 10.000 - 3.035 - 0.329 (10.8%) - 2.706 (89.2%) + 13.473 + 3.277 + 0.323 (9.9%) + 2.954 (90.1%) - Path #6: recovery slack is 6.273(MET) + Path #10: recovery slack is 9.504(MET) -
+
Location Delay Type @@ -87581,7 +88764,7 @@ Logical Resource - Clock ddrphy_clkin (rising edge) + Clock clk_720p60Hz (rising edge) 0.000 0.000 @@ -87639,18 +88822,18 @@ td - 0.089 - 2.391 + 0.094 + 2.396 r - u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=851) - 1.976 - 4.367 + net (fanout=2825) + 3.127 + 5.523 - zoom_clk + rd3_clk @@ -87658,47 +88841,91 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) td - 0.000 - 4.367 + 0.089 + 5.612 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=71) - 0.847 - 5.214 + net (fanout=1758) + 2.458 + 8.070 - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + nt_pix_clk + r + sync_vg_100m/CLK (GTP_DFF_P) + + + + tco + 0.323 + 8.393 + f + sync_vg_100m/Q (GTP_DFF_P) + + - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) + net (fanout=2548) + 2.954 + 11.347 + + sync_vg_100m + + + + + + + f + adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[5]/C (GTP_DFF_C) +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + Clock clk_720p60Hz (rising edge) + + 13.473 + 13.473 + r + + + + clk - td - 0.094 - 5.308 + 0.000 + 13.473 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + clk (port) - net (fanout=3) - 0.605 - 5.913 + net (fanout=1) + 0.000 + 13.473 - u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + clk @@ -87706,84 +88933,130 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) + clk_ibuf/I (GTP_INBUF) td - 0.000 - 5.913 + 1.211 + 14.684 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + clk_ibuf/O (GTP_INBUF) - net (fanout=5817) - 3.146 - 9.059 + net (fanout=1) + 1.091 + 15.775 - u_axi_ddr_top/clk + nt_clk - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/CLK (GTP_DFF_C) + + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) - - tco - 0.329 - 9.388 + + td + 0.094 + 15.869 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/u_ddrphy_rstn_sync/sig_async_r2[0]/Q (GTP_DFF_C) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=1) - 0.000 - 9.388 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_rst_n + net (fanout=2825) + 3.127 + 18.996 + + rd3_clk - + - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/N0/I (GTP_INV) + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) - + td + 0.089 + 19.085 + r + U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + + + + net (fanout=1758) + 2.458 + 21.543 + + nt_pix_clk + + + + + + + r + adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[5]/CLK (GTP_DFF_C) + + + clock pessimism + 0.000 - 9.388 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/N0/Z (GTP_INV) + 21.543 + + + clock uncertainty + + -0.150 + 21.393 + - net (fanout=2275) - 2.706 - 12.094 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/N0 - + Recovery time + -0.542 + 20.851 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[2]/C (GTP_DFF_C)
+ +
+ + 9.504 + 0 + 2548 + sync_vg_100m/CLK + adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[6]/C + + clk_720p60Hz + clk_720p60Hz + rise-rise + 0.000 + 8.070 + 8.070 + 0.000 + 13.473 + 3.277 + 0.323 (9.9%) + 2.954 (90.1%) + + Path #11: recovery slack is 9.504(MET) - +
Location Delay Type @@ -87793,10 +89066,10 @@ Logical Resource - Clock ddrphy_clkin (rising edge) + Clock clk_720p60Hz (rising edge) - 10.000 - 10.000 + 0.000 + 0.000 r @@ -87804,7 +89077,7 @@ clk0.000 - 10.000 + 0.000rclk (port) @@ -87812,7 +89085,7 @@ net (fanout=1) 0.000 - 10.000 + 0.000 clk @@ -87828,7 +89101,7 @@ td 1.211 - 11.211 + 1.211 r clk_ibuf/O (GTP_INBUF) @@ -87836,7 +89109,7 @@ net (fanout=1) 1.091 - 12.302 + 2.302 nt_clk @@ -87851,18 +89124,18 @@ td - 0.089 - 12.391 + 0.094 + 2.396 r - u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=851) - 1.976 - 14.367 + net (fanout=2825) + 3.127 + 5.523 - zoom_clk + rd3_clk @@ -87870,23 +89143,91 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) td + 0.089 + 5.612 + r + U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + + + + net (fanout=1758) + 2.458 + 8.070 + + nt_pix_clk + + + + + + + r + sync_vg_100m/CLK (GTP_DFF_P) + + + + tco + 0.323 + 8.393 + f + sync_vg_100m/Q (GTP_DFF_P) + + + + net (fanout=2548) + 2.954 + 11.347 + + sync_vg_100m + + + + + + + f + adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[6]/C (GTP_DFF_C) + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_720p60Hz (rising edge) + + 13.473 + 13.473 + r + + + + clk + 0.000 - 14.367 + 13.473 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + clk (port) - net (fanout=71) - 0.847 - 15.214 + net (fanout=1) + 0.000 + 13.473 - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + clk @@ -87894,23 +89235,47 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) + clk_ibuf/I (GTP_INBUF) + + + + td + 1.211 + 14.684 + r + clk_ibuf/O (GTP_INBUF) + + + + net (fanout=1) + 1.091 + 15.775 + + nt_clk + + + + + + + + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) td 0.094 - 15.308 + 15.869 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=3) - 0.605 - 15.913 + net (fanout=2825) + 3.127 + 18.996 - u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + rd3_clk @@ -87918,23 +89283,23 @@ - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) td - 0.000 - 15.913 + 0.089 + 19.085 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=5817) - 3.146 - 19.059 + net (fanout=1758) + 2.458 + 21.543 - u_axi_ddr_top/clk + nt_pix_clk @@ -87942,13 +89307,13 @@ r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_address[2]/CLK (GTP_DFF_C) + adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[6]/CLK (GTP_DFF_C) clock pessimism 0.000 - 19.059 + 21.543 @@ -87956,7 +89321,7 @@ clock uncertainty -0.150 - 18.909 + 21.393 @@ -87964,7 +89329,7 @@ Recovery time -0.542 - 18.367 + 20.851 @@ -87977,23 +89342,23 @@ 0 2548 sync_vg_100m/CLK - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[5]/C + adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[7]/C clk_720p60Hz clk_720p60Hz rise-rise 0.000 - 8.073 - 8.073 + 8.070 + 8.070 0.000 13.473 3.277 0.323 (9.9%) 2.954 (90.1%) - Path #7: recovery slack is 9.504(MET) + Path #12: recovery slack is 9.504(MET) -
+
Location Delay Type @@ -88068,9 +89433,9 @@ - net (fanout=2827) - 3.130 - 5.526 + net (fanout=2825) + 3.127 + 5.523 rd3_clk @@ -88086,7 +89451,7 @@ td 0.089 - 5.615 + 5.612 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) @@ -88094,7 +89459,7 @@ net (fanout=1758) 2.458 - 8.073 + 8.070 nt_pix_clk @@ -88110,7 +89475,7 @@ tco 0.323 - 8.396 + 8.393 f sync_vg_100m/Q (GTP_DFF_P) @@ -88118,7 +89483,7 @@ net (fanout=2548) 2.954 - 11.350 + 11.347 sync_vg_100m @@ -88128,12 +89493,12 @@ f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[5]/C (GTP_DFF_C) + adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[7]/C (GTP_DFF_C)
- +
Location Delay Type @@ -88208,9 +89573,9 @@ - net (fanout=2827) - 3.130 - 18.999 + net (fanout=2825) + 3.127 + 18.996 rd3_clk @@ -88226,7 +89591,7 @@ td 0.089 - 19.088 + 19.085 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) @@ -88234,7 +89599,7 @@ net (fanout=1758) 2.458 - 21.546 + 21.543 nt_pix_clk @@ -88244,13 +89609,13 @@ r - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[5]/CLK (GTP_DFF_C) + adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[7]/CLK (GTP_DFF_C) clock pessimism 0.000 - 21.546 + 21.543 @@ -88258,7 +89623,7 @@ clock uncertainty -0.150 - 21.396 + 21.393 @@ -88266,7 +89631,7 @@ Recovery time -0.542 - 20.854 + 20.851 @@ -88275,27 +89640,27 @@ - 9.504 + 16.577 0 - 2548 - sync_vg_100m/CLK - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[6]/C + 1674 + u_clk50m_rst/rst/CLK + image_filiter_inst/multiline_buffer_inst/rst_s1/P - clk_720p60Hz - clk_720p60Hz + clk_50m + clk_50m rise-rise 0.000 - 8.073 - 8.073 + 5.523 + 5.523 0.000 - 13.473 - 3.277 - 0.323 (9.9%) - 2.954 (90.1%) + 20.000 + 2.731 + 0.323 (11.8%) + 2.408 (88.2%) - Path #8: recovery slack is 9.504(MET) + Path #13: recovery slack is 16.577(MET) -
+
Location Delay Type @@ -88305,7 +89670,7 @@ Logical Resource - Clock clk_720p60Hz (rising edge) + Clock clk_50m (rising edge) 0.000 0.000 @@ -88370,9 +89735,9 @@ - net (fanout=2827) - 3.130 - 5.526 + net (fanout=2825) + 3.127 + 5.523 rd3_clk @@ -88381,48 +89746,24 @@ - - U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) - - - - td - 0.089 - 5.615 r - U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - - - - net (fanout=1758) - 2.458 - 8.073 - - nt_pix_clk - - - - - - - r - sync_vg_100m/CLK (GTP_DFF_P) + u_clk50m_rst/rst/CLK (GTP_DFF_P) tco 0.323 - 8.396 + 5.846 f - sync_vg_100m/Q (GTP_DFF_P) + u_clk50m_rst/rst/Q (GTP_DFF_P) - net (fanout=2548) - 2.954 - 11.350 + net (fanout=1674) + 2.408 + 8.254 - sync_vg_100m + rd3_rst @@ -88430,12 +89771,12 @@ f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[6]/C (GTP_DFF_C) + image_filiter_inst/multiline_buffer_inst/rst_s1/P (GTP_DFF_P)
- +
Location Delay Type @@ -88445,10 +89786,10 @@ Logical Resource - Clock clk_720p60Hz (rising edge) + Clock clk_50m (rising edge) - 13.473 - 13.473 + 20.000 + 20.000 r @@ -88456,7 +89797,7 @@ clk0.000 - 13.473 + 20.000rclk (port) @@ -88464,7 +89805,7 @@ net (fanout=1) 0.000 - 13.473 + 20.000 clk @@ -88480,7 +89821,7 @@ td 1.211 - 14.684 + 21.211 r clk_ibuf/O (GTP_INBUF) @@ -88488,7 +89829,7 @@ net (fanout=1) 1.091 - 15.775 + 22.302 nt_clk @@ -88504,55 +89845,31 @@ td 0.094 - 15.869 + 22.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) - 3.130 - 18.999 + net (fanout=2825) + 3.127 + 25.523 rd3_clk - - - - - - - U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) - - - - td - 0.089 - 19.088 - r - U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - - - - net (fanout=1758) - 2.458 - 21.546 - - nt_pix_clk - r - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[6]/CLK (GTP_DFF_C) + image_filiter_inst/multiline_buffer_inst/rst_s1/CLK (GTP_DFF_P) clock pessimism 0.000 - 21.546 + 25.523 @@ -88560,7 +89877,7 @@ clock uncertainty -0.150 - 21.396 + 25.373 @@ -88568,7 +89885,7 @@ Recovery time -0.542 - 20.854 + 24.831 @@ -88577,27 +89894,27 @@ - 9.504 + 16.577 0 - 2548 - sync_vg_100m/CLK - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[7]/C + 1674 + u_clk50m_rst/rst/CLK + image_filiter_inst/multiline_buffer_inst/srst/P - clk_720p60Hz - clk_720p60Hz + clk_50m + clk_50m rise-rise 0.000 - 8.073 - 8.073 + 5.523 + 5.523 0.000 - 13.473 - 3.277 - 0.323 (9.9%) - 2.954 (90.1%) + 20.000 + 2.731 + 0.323 (11.8%) + 2.408 (88.2%) - Path #9: recovery slack is 9.504(MET) + Path #14: recovery slack is 16.577(MET) -
+
Location Delay Type @@ -88607,7 +89924,7 @@ Logical Resource - Clock clk_720p60Hz (rising edge) + Clock clk_50m (rising edge) 0.000 0.000 @@ -88672,59 +89989,35 @@ - net (fanout=2827) - 3.130 - 5.526 + net (fanout=2825) + 3.127 + 5.523 rd3_clk - - - - - - - U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) - - - - td - 0.089 - 5.615 - r - U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - - - - net (fanout=1758) - 2.458 - 8.073 - - nt_pix_clk - r - sync_vg_100m/CLK (GTP_DFF_P) + u_clk50m_rst/rst/CLK (GTP_DFF_P) tco 0.323 - 8.396 + 5.846 f - sync_vg_100m/Q (GTP_DFF_P) + u_clk50m_rst/rst/Q (GTP_DFF_P) - net (fanout=2548) - 2.954 - 11.350 + net (fanout=1674) + 2.408 + 8.254 - sync_vg_100m + rd3_rst @@ -88732,12 +90025,12 @@ f - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[7]/C (GTP_DFF_C) + image_filiter_inst/multiline_buffer_inst/srst/P (GTP_DFF_P)
- +
Location Delay Type @@ -88747,10 +90040,10 @@ Logical Resource - Clock clk_720p60Hz (rising edge) + Clock clk_50m (rising edge) - 13.473 - 13.473 + 20.000 + 20.000 r @@ -88758,7 +90051,7 @@ clk0.000 - 13.473 + 20.000rclk (port) @@ -88766,7 +90059,7 @@ net (fanout=1) 0.000 - 13.473 + 20.000 clk @@ -88782,7 +90075,7 @@ td 1.211 - 14.684 + 21.211 r clk_ibuf/O (GTP_INBUF) @@ -88790,7 +90083,7 @@ net (fanout=1) 1.091 - 15.775 + 22.302 nt_clk @@ -88806,55 +90099,31 @@ td 0.094 - 15.869 + 22.396 r u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=2827) - 3.130 - 18.999 + net (fanout=2825) + 3.127 + 25.523 rd3_clk - - - - - - - U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) - - - - td - 0.089 - 19.088 - r - U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - - - - net (fanout=1758) - 2.458 - 21.546 - - nt_pix_clk - r - adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[1].u_divider_step/dividend_kp[7]/CLK (GTP_DFF_C) + image_filiter_inst/multiline_buffer_inst/srst/CLK (GTP_DFF_P) clock pessimism 0.000 - 21.546 + 25.523 @@ -88862,7 +90131,7 @@ clock uncertainty -0.150 - 21.396 + 25.373 @@ -88870,7 +90139,7 @@ Recovery time -0.542 - 20.854 + 24.831 @@ -88883,23 +90152,23 @@ 0 1674 u_clk50m_rst/rst/CLK - image_filiter_inst/multiline_buffer_inst/rst_s1/P + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/P clk_50m clk_50m rise-rise 0.000 - 5.526 - 5.526 + 5.523 + 5.523 0.000 20.000 2.731 0.323 (11.8%) 2.408 (88.2%) - Path #10: recovery slack is 16.577(MET) + Path #15: recovery slack is 16.577(MET) -
+
Location Delay Type @@ -88974,9 +90243,9 @@ - net (fanout=2827) - 3.130 - 5.526 + net (fanout=2825) + 3.127 + 5.523 rd3_clk @@ -88992,7 +90261,7 @@ tco 0.323 - 5.849 + 5.846 f u_clk50m_rst/rst/Q (GTP_DFF_P) @@ -89000,7 +90269,7 @@ net (fanout=1674) 2.408 - 8.257 + 8.254 rd3_rst @@ -89010,12 +90279,12 @@ f - image_filiter_inst/multiline_buffer_inst/rst_s1/P (GTP_DFF_P) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/P (GTP_DFF_P)
- +
Location Delay Type @@ -89090,9 +90359,9 @@ - net (fanout=2827) - 3.130 - 25.526 + net (fanout=2825) + 3.127 + 25.523 rd3_clk @@ -89102,13 +90371,13 @@ r - image_filiter_inst/multiline_buffer_inst/rst_s1/CLK (GTP_DFF_P) + u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/CLK (GTP_DFF_P) clock pessimism 0.000 - 25.526 + 25.523 @@ -89116,7 +90385,7 @@ clock uncertainty -0.150 - 25.376 + 25.373 @@ -89124,7 +90393,7 @@ Recovery time -0.542 - 24.834 + 24.831 @@ -89133,27 +90402,27 @@ - 16.577 - 0 - 1674 - u_clk50m_rst/rst/CLK - image_filiter_inst/multiline_buffer_inst/srst/P + 98.374 + 1 + 3 + rstn_out1/CLK + ms72xx_ctl/rstn_temp1/C - clk_50m - clk_50m + clk_10m + clk_10m rise-rise 0.000 - 5.526 - 5.526 + 3.510 + 3.510 0.000 - 20.000 - 2.731 - 0.323 (11.8%) - 2.408 (88.2%) + 100.000 + 0.934 + 0.329 (35.2%) + 0.605 (64.8%) - Path #11: recovery slack is 16.577(MET) + Path #16: recovery slack is 98.374(MET) -
+
Location Delay Type @@ -89163,7 +90432,7 @@ Logical Resource - Clock clk_50m (rising edge) + Clock clk_10m (rising edge) 0.000 0.000 @@ -89224,15 +90493,15 @@ 0.094 2.396 r - u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT4 (GTP_PLL_E3) - net (fanout=2827) - 3.130 - 5.526 + net (fanout=256) + 1.114 + 3.510 - rd3_clk + clk_10m @@ -89240,23 +90509,47 @@ r - u_clk50m_rst/rst/CLK (GTP_DFF_P) + rstn_out1/CLK (GTP_DFF_C) tco - 0.323 - 5.849 + 0.329 + 3.839 + r + rstn_out1/Q (GTP_DFF_C) + + + + net (fanout=3) + 0.000 + 3.839 + + nt_eth_rstn + + + + + + + + ms72xx_ctl/N0/I (GTP_INV) + + + + td + 0.000 + 3.839 f - u_clk50m_rst/rst/Q (GTP_DFF_P) + ms72xx_ctl/N0/Z (GTP_INV) - net (fanout=1674) - 2.408 - 8.257 + net (fanout=1) + 0.605 + 4.444 - rd3_rst + ms72xx_ctl/N0 @@ -89264,12 +90557,12 @@ f - image_filiter_inst/multiline_buffer_inst/srst/P (GTP_DFF_P) + ms72xx_ctl/rstn_temp1/C (GTP_DFF_C)
- +
Location Delay Type @@ -89279,10 +90572,10 @@ Logical Resource - Clock clk_50m (rising edge) + Clock clk_10m (rising edge) - 20.000 - 20.000 + 100.000 + 100.000 r @@ -89290,7 +90583,7 @@ clk0.000 - 20.000 + 100.000rclk (port) @@ -89298,7 +90591,7 @@ net (fanout=1) 0.000 - 20.000 + 100.000 clk @@ -89314,7 +90607,7 @@ td 1.211 - 21.211 + 101.211 r clk_ibuf/O (GTP_INBUF) @@ -89322,7 +90615,7 @@ net (fanout=1) 1.091 - 22.302 + 102.302 nt_clk @@ -89338,17 +90631,17 @@ td 0.094 - 22.396 + 102.396 r - u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT4 (GTP_PLL_E3) - net (fanout=2827) - 3.130 - 25.526 + net (fanout=256) + 1.114 + 103.510 - rd3_clk + clk_10m @@ -89356,13 +90649,13 @@ r - image_filiter_inst/multiline_buffer_inst/srst/CLK (GTP_DFF_P) + ms72xx_ctl/rstn_temp1/CLK (GTP_DFF_C) clock pessimism 0.000 - 25.526 + 103.510 @@ -89370,7 +90663,7 @@ clock uncertainty -0.150 - 25.376 + 103.360 @@ -89378,7 +90671,7 @@ Recovery time -0.542 - 24.834 + 102.818 @@ -89386,28 +90679,49 @@ +
+ + + Slack + Logic Levels + High Fanout + Start Point + End Point + Exception + Launch Clock + Capture Clock + Clock Edges + Clock Skew + Launch Clock Delay + Capture Clock Delay + Clock Pessimism Removal + Requirement + Data delay + Logic delay + Route delay + - 16.577 + -1.158 0 - 1674 - u_clk50m_rst/rst/CLK - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/P + 2 + u_ddr_rst/rst/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/C - clk_50m - clk_50m + clk_200m + clk_200m rise-rise + 2.196 + 2.996 + 5.192 0.000 - 5.526 - 5.526 0.000 - 20.000 - 2.731 - 0.323 (11.8%) - 2.408 (88.2%) + 0.787 + 0.323 (41.0%) + 0.464 (59.0%) - Path #12: recovery slack is 16.577(MET) + Path #1: removal slack is -1.158(VIOLATED) -
+
Location Delay Type @@ -89417,7 +90731,7 @@ Logical Resource - Clock clk_50m (rising edge) + Clock clk_200m (rising edge) 0.000 0.000 @@ -89475,18 +90789,18 @@ td - 0.094 - 2.396 + 0.089 + 2.391 r - u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=2827) - 3.130 - 5.526 + net (fanout=7) + 0.605 + 2.996 - rd3_clk + ddr_clk @@ -89494,23 +90808,23 @@ r - u_clk50m_rst/rst/CLK (GTP_DFF_P) + u_ddr_rst/rst/CLK (GTP_DFF_P) tco 0.323 - 5.849 + 3.319 f - u_clk50m_rst/rst/Q (GTP_DFF_P) + u_ddr_rst/rst/Q (GTP_DFF_P) - net (fanout=1674) - 2.408 - 8.257 + net (fanout=2) + 0.464 + 3.783 - rd3_rst + ddr_rst @@ -89518,12 +90832,12 @@ f - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/P (GTP_DFF_P) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/C (GTP_DFF_C)
- +
Location Delay Type @@ -89533,10 +90847,10 @@ Logical Resource - Clock clk_50m (rising edge) + Clock clk_200m (rising edge) - 20.000 - 20.000 + 0.000 + 0.000 r @@ -89544,7 +90858,7 @@ clk0.000 - 20.000 + 0.000rclk (port) @@ -89552,7 +90866,7 @@ net (fanout=1) 0.000 - 20.000 + 0.000 clk @@ -89568,7 +90882,7 @@ td 1.211 - 21.211 + 1.211 r clk_ibuf/O (GTP_INBUF) @@ -89576,7 +90890,7 @@ net (fanout=1) 1.091 - 22.302 + 2.302 nt_clk @@ -89591,18 +90905,42 @@ td - 0.094 - 22.396 + 0.089 + 2.391 r - u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=2827) - 3.130 - 25.526 + net (fanout=7) + 0.605 + 2.996 - rd3_clk + ddr_clk + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + + + + td + 0.000 + 2.996 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + + + + net (fanout=71) + 2.196 + 5.192 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin @@ -89610,29 +90948,29 @@ r - u_ov5640/u_mix_image/u_mix_fifo1/U_ipml_fifo_mix_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.asyn_rempty/CLK (GTP_DFF_P) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/CLK (GTP_DFF_C) clock pessimism 0.000 - 25.526 + 5.192 clock uncertainty - -0.150 - 25.376 + 0.000 + 5.192 - Recovery time + Removal time - -0.542 - 24.834 + -0.251 + 4.941 @@ -89641,27 +90979,27 @@ - 98.374 - 1 - 3 - rstn_out1/CLK - ms72xx_ctl/rstn_temp1/C + -1.158 + 0 + 2 + u_ddr_rst/rst/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/C - clk_10m - clk_10m + clk_200m + clk_200m rise-rise + 2.196 + 2.996 + 5.192 0.000 - 3.510 - 3.510 0.000 - 100.000 - 0.934 - 0.329 (35.2%) - 0.605 (64.8%) + 0.787 + 0.323 (41.0%) + 0.464 (59.0%) - Path #13: recovery slack is 98.374(MET) + Path #2: removal slack is -1.158(VIOLATED) -
+
Location Delay Type @@ -89671,7 +91009,7 @@ Logical Resource - Clock clk_10m (rising edge) + Clock clk_200m (rising edge) 0.000 0.000 @@ -89729,18 +91067,18 @@ td - 0.094 - 2.396 + 0.089 + 2.391 r - u_sys_pll/u_pll_e3/CLKOUT4 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=256) - 1.114 - 3.510 + net (fanout=7) + 0.605 + 2.996 - clk_10m + ddr_clk @@ -89748,47 +91086,23 @@ r - rstn_out1/CLK (GTP_DFF_C) + u_ddr_rst/rst/CLK (GTP_DFF_P) tco - 0.329 - 3.839 - r - rstn_out1/Q (GTP_DFF_C) - - - - net (fanout=3) - 0.000 - 3.839 - - nt_eth_rstn - - - - - - - - ms72xx_ctl/N0/I (GTP_INV) - - - - td - 0.000 - 3.839 + 0.323 + 3.319 f - ms72xx_ctl/N0/Z (GTP_INV) + u_ddr_rst/rst/Q (GTP_DFF_P) - net (fanout=1) - 0.605 - 4.444 + net (fanout=2) + 0.464 + 3.783 - ms72xx_ctl/N0 + ddr_rst @@ -89796,12 +91110,12 @@ f - ms72xx_ctl/rstn_temp1/C (GTP_DFF_C) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/C (GTP_DFF_C)
- +
Location Delay Type @@ -89811,10 +91125,10 @@ Logical Resource - Clock clk_10m (rising edge) + Clock clk_200m (rising edge) - 100.000 - 100.000 + 0.000 + 0.000 r @@ -89822,7 +91136,7 @@ clk0.000 - 100.000 + 0.000rclk (port) @@ -89830,7 +91144,7 @@ net (fanout=1) 0.000 - 100.000 + 0.000 clk @@ -89846,7 +91160,7 @@ td 1.211 - 101.211 + 1.211 r clk_ibuf/O (GTP_INBUF) @@ -89854,7 +91168,7 @@ net (fanout=1) 1.091 - 102.302 + 2.302 nt_clk @@ -89869,48 +91183,72 @@ td - 0.094 - 102.396 + 0.089 + 2.391 r - u_sys_pll/u_pll_e3/CLKOUT4 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - net (fanout=256) - 1.114 - 103.510 + net (fanout=7) + 0.605 + 2.996 - clk_10m + ddr_clk + + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + + + + td + 0.000 + 2.996 r - ms72xx_ctl/rstn_temp1/CLK (GTP_DFF_C) + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + + + + net (fanout=71) + 2.196 + 5.192 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/CLK (GTP_DFF_C) clock pessimism 0.000 - 103.510 + 5.192 clock uncertainty - -0.150 - 103.360 + 0.000 + 5.192 - Recovery time + Removal time - -0.542 - 102.818 + -0.251 + 4.941 @@ -89918,49 +91256,28 @@ -
- - - Slack - Logic Levels - High Fanout - Start Point - End Point - Exception - Launch Clock - Capture Clock - Clock Edges - Clock Skew - Launch Clock Delay - Capture Clock Delay - Clock Pessimism Removal - Requirement - Data delay - Logic delay - Route delay - - -1.158 + 1.092 0 - 2 - u_ddr_rst/rst/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/C + 10 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_dqs_training_rstn/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_ddc_ca/RST_TRAINING_N - clk_200m - clk_200m + ddrphy_clkin + ddrphy_clkin rise-rise - 2.196 - 4.367 - 6.563 0.000 + 7.688 + 7.688 0.000 - 0.787 - 0.323 (41.0%) - 0.464 (59.0%) + 0.000 + 1.081 + 0.323 (29.9%) + 0.758 (70.1%) - Path #1: removal slack is -1.158(VIOLATED) + Path #3: removal slack is 1.092(MET) -
+
Location Delay Type @@ -89970,7 +91287,7 @@ Logical Resource - Clock clk_200m (rising edge) + Clock ddrphy_clkin (rising edge) 0.000 0.000 @@ -90035,35 +91352,107 @@ - net (fanout=851) - 1.976 - 4.367 + net (fanout=7) + 0.605 + 2.996 - zoom_clk + ddr_clk + + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + + + + td + 0.000 + 2.996 r - u_ddr_rst/rst/CLK (GTP_DFF_P) + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + + + + net (fanout=71) + 0.847 + 3.843 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.094 + 3.937 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + + + + net (fanout=3) + 0.605 + 4.542 + + u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) + + + + td + 0.000 + 4.542 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + + + + net (fanout=5817) + 3.146 + 7.688 + + u_axi_ddr_top/clk + + + + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_dqs_training_rstn/CLK (GTP_DFF_C) tco 0.323 - 4.690 + 8.011 f - u_ddr_rst/rst/Q (GTP_DFF_P) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_dqs_training_rstn/Q (GTP_DFF_C) - net (fanout=2) - 0.464 - 5.154 + net (fanout=10) + 0.758 + 8.769 - ddr_rst + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dqs_training_rstn @@ -90071,12 +91460,12 @@ f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/C (GTP_DFF_C) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_ddc_ca/RST_TRAINING_N (GTP_DDC_E1)
- +
Location Delay Type @@ -90086,7 +91475,7 @@ Logical Resource - Clock clk_200m (rising edge) + Clock ddrphy_clkin (rising edge) 0.000 0.000 @@ -90151,11 +91540,11 @@ - net (fanout=851) - 1.976 - 4.367 + net (fanout=7) + 0.605 + 2.996 - zoom_clk + ddr_clk @@ -90169,15 +91558,15 @@ td 0.000 - 4.367 + 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) net (fanout=71) - 2.196 - 6.563 + 0.847 + 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin @@ -90186,14 +91575,62 @@ + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.094 + 3.937 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/CLK (GTP_DFF_C) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + + + + net (fanout=3) + 0.605 + 4.542 + + u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) + + + + td + 0.000 + 4.542 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + + + + net (fanout=5817) + 3.146 + 7.688 + + u_axi_ddr_top/clk + + + + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_ddc_ca/CLKB (GTP_DDC_E1) clock pessimism 0.000 - 6.563 + 7.688 @@ -90201,15 +91638,15 @@ clock uncertainty 0.000 - 6.563 + 7.688 Removal time - -0.251 - 6.312 + -0.011 + 7.677 @@ -90218,27 +91655,27 @@ - -1.158 + 1.092 0 - 2 - u_ddr_rst/rst/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/C + 10 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_dqs_training_rstn/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[1].u_ddc_ca/RST_TRAINING_N - clk_200m - clk_200m + ddrphy_clkin + ddrphy_clkin rise-rise - 2.196 - 4.367 - 6.563 0.000 + 7.688 + 7.688 0.000 - 0.787 - 0.323 (41.0%) - 0.464 (59.0%) + 0.000 + 1.081 + 0.323 (29.9%) + 0.758 (70.1%) - Path #2: removal slack is -1.158(VIOLATED) + Path #4: removal slack is 1.092(MET) -
+
Location Delay Type @@ -90248,7 +91685,7 @@ Logical Resource - Clock clk_200m (rising edge) + Clock ddrphy_clkin (rising edge) 0.000 0.000 @@ -90313,35 +91750,107 @@ - net (fanout=851) - 1.976 - 4.367 + net (fanout=7) + 0.605 + 2.996 - zoom_clk + ddr_clk + + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + + + + td + 0.000 + 2.996 r - u_ddr_rst/rst/CLK (GTP_DFF_P) + u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + + + + net (fanout=71) + 0.847 + 3.843 + + u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.094 + 3.937 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + + + + net (fanout=3) + 0.605 + 4.542 + + u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) + + + + td + 0.000 + 4.542 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + + + + net (fanout=5817) + 3.146 + 7.688 + + u_axi_ddr_top/clk + + + + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_dqs_training_rstn/CLK (GTP_DFF_C) tco 0.323 - 4.690 + 8.011 f - u_ddr_rst/rst/Q (GTP_DFF_P) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_dqs_training_rstn/Q (GTP_DFF_C) - net (fanout=2) - 0.464 - 5.154 + net (fanout=10) + 0.758 + 8.769 - ddr_rst + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dqs_training_rstn @@ -90349,12 +91858,12 @@ f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/C (GTP_DFF_C) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[1].u_ddc_ca/RST_TRAINING_N (GTP_DDC_E1)
- +
Location Delay Type @@ -90364,7 +91873,7 @@ Logical Resource - Clock clk_200m (rising edge) + Clock ddrphy_clkin (rising edge) 0.000 0.000 @@ -90429,11 +91938,11 @@ - net (fanout=851) - 1.976 - 4.367 + net (fanout=7) + 0.605 + 2.996 - zoom_clk + ddr_clk @@ -90447,15 +91956,15 @@ td 0.000 - 4.367 + 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) net (fanout=71) - 2.196 - 6.563 + 0.847 + 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin @@ -90464,14 +91973,62 @@ + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.094 + 3.937 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/CLK (GTP_DFF_C) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + + + + net (fanout=3) + 0.605 + 4.542 + + u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + + + + + + + + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) + + + + td + 0.000 + 4.542 + r + u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + + + + net (fanout=5817) + 3.146 + 7.688 + + u_axi_ddr_top/clk + + + + + + + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[1].u_ddc_ca/CLKB (GTP_DDC_E1) clock pessimism 0.000 - 6.563 + 7.688 @@ -90479,15 +92036,15 @@ clock uncertainty 0.000 - 6.563 + 7.688 Removal time - -0.251 - 6.312 + -0.011 + 7.677 @@ -90500,23 +92057,23 @@ 0 10 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_dqs_training_rstn/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_ddc_ca/RST_TRAINING_N + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[2].u_ddc_ca/RST_TRAINING_N ddrphy_clkin ddrphy_clkin rise-rise 0.000 - 9.059 - 9.059 + 7.688 + 7.688 0.000 0.000 1.081 0.323 (29.9%) 0.758 (70.1%) - Path #3: removal slack is 1.092(MET) + Path #5: removal slack is 1.092(MET) -
+
Location Delay Type @@ -90591,11 +92148,11 @@ - net (fanout=851) - 1.976 - 4.367 + net (fanout=7) + 0.605 + 2.996 - zoom_clk + ddr_clk @@ -90609,7 +92166,7 @@ td 0.000 - 4.367 + 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) @@ -90617,7 +92174,7 @@ net (fanout=71) 0.847 - 5.214 + 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin @@ -90633,7 +92190,7 @@ td 0.094 - 5.308 + 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) @@ -90641,7 +92198,7 @@ net (fanout=3) 0.605 - 5.913 + 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] @@ -90657,7 +92214,7 @@ td 0.000 - 5.913 + 4.542 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) @@ -90665,7 +92222,7 @@ net (fanout=5817) 3.146 - 9.059 + 7.688 u_axi_ddr_top/clk @@ -90681,7 +92238,7 @@ tco 0.323 - 9.382 + 8.011 f u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_dqs_training_rstn/Q (GTP_DFF_C) @@ -90689,7 +92246,7 @@ net (fanout=10) 0.758 - 10.140 + 8.769 u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dqs_training_rstn @@ -90699,12 +92256,12 @@ f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_ddc_ca/RST_TRAINING_N (GTP_DDC_E1) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[2].u_ddc_ca/RST_TRAINING_N (GTP_DDC_E1)
- +
Location Delay Type @@ -90779,11 +92336,11 @@ - net (fanout=851) - 1.976 - 4.367 + net (fanout=7) + 0.605 + 2.996 - zoom_clk + ddr_clk @@ -90797,7 +92354,7 @@ td 0.000 - 4.367 + 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) @@ -90805,7 +92362,7 @@ net (fanout=71) 0.847 - 5.214 + 3.843 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin @@ -90821,7 +92378,7 @@ td 0.094 - 5.308 + 3.937 r u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) @@ -90829,7 +92386,7 @@ net (fanout=3) 0.605 - 5.913 + 4.542 u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] @@ -90845,7 +92402,7 @@ td 0.000 - 5.913 + 4.542 r u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) @@ -90853,7 +92410,7 @@ net (fanout=5817) 3.146 - 9.059 + 7.688 u_axi_ddr_top/clk @@ -90863,13 +92420,13 @@ r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_ddc_ca/CLKB (GTP_DDC_E1) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[2].u_ddc_ca/CLKB (GTP_DDC_E1) clock pessimism 0.000 - 9.059 + 7.688 @@ -90877,7 +92434,7 @@ clock uncertainty 0.000 - 9.059 + 7.688 @@ -90885,7 +92442,7 @@ Removal time -0.011 - 9.048 + 7.677 @@ -90894,27 +92451,27 @@ - 1.092 - 0 - 10 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_dqs_training_rstn/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[1].u_ddc_ca/RST_TRAINING_N + 1.185 + 1 + 3 + rstn_out1/CLK + ms72xx_ctl/rstn_temp1/C - ddrphy_clkin - ddrphy_clkin + clk_10m + clk_10m rise-rise 0.000 - 9.059 - 9.059 + 3.510 + 3.510 0.000 0.000 - 1.081 - 0.323 (29.9%) - 0.758 (70.1%) + 0.934 + 0.329 (35.2%) + 0.605 (64.8%) - Path #4: removal slack is 1.092(MET) + Path #6: removal slack is 1.185(MET) -
+
Location Delay Type @@ -90924,7 +92481,7 @@ Logical Resource - Clock ddrphy_clkin (rising edge) + Clock clk_10m (rising edge) 0.000 0.000 @@ -90982,114 +92539,66 @@ td - 0.089 - 2.391 + 0.094 + 2.396 r - u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT4 (GTP_PLL_E3) - net (fanout=851) - 1.976 - 4.367 + net (fanout=256) + 1.114 + 3.510 - zoom_clk + clk_10m - - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - - - - td - 0.000 - 4.367 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - - - - net (fanout=71) - 0.847 - 5.214 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) + rstn_out1/CLK (GTP_DFF_C) - - td - 0.094 - 5.308 + + tco + 0.329 + 3.839 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + rstn_out1/Q (GTP_DFF_C) net (fanout=3) - 0.605 - 5.913 - - u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) - - - - td 0.000 - 5.913 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + 3.839 + + nt_eth_rstn + - net (fanout=5817) - 3.146 - 9.059 - - u_axi_ddr_top/clk - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_dqs_training_rstn/CLK (GTP_DFF_C) + ms72xx_ctl/N0/I (GTP_INV) - tco - 0.323 - 9.382 + td + 0.000 + 3.839 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_dqs_training_rstn/Q (GTP_DFF_C) + ms72xx_ctl/N0/Z (GTP_INV) - net (fanout=10) - 0.758 - 10.140 + net (fanout=1) + 0.605 + 4.444 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dqs_training_rstn + ms72xx_ctl/N0 @@ -91097,12 +92606,12 @@ f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[1].u_ddc_ca/RST_TRAINING_N (GTP_DDC_E1) + ms72xx_ctl/rstn_temp1/C (GTP_DFF_C)
- +
Location Delay Type @@ -91112,7 +92621,7 @@ Logical Resource - Clock ddrphy_clkin (rising edge) + Clock clk_10m (rising edge) 0.000 0.000 @@ -91167,93 +92676,21 @@ u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) - - - td - 0.089 - 2.391 - r - u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) - - - - net (fanout=851) - 1.976 - 4.367 - - zoom_clk - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) - - - - td - 0.000 - 4.367 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) - - - - net (fanout=71) - 0.847 - 5.214 - - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - td 0.094 - 5.308 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - - - - net (fanout=3) - 0.605 - 5.913 - - u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) - - - - td - 0.000 - 5.913 + 2.396 r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + u_sys_pll/u_pll_e3/CLKOUT4 (GTP_PLL_E3) - net (fanout=5817) - 3.146 - 9.059 + net (fanout=256) + 1.114 + 3.510 - u_axi_ddr_top/clk + clk_10m @@ -91261,13 +92698,13 @@ r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[1].u_ddc_ca/CLKB (GTP_DDC_E1) + ms72xx_ctl/rstn_temp1/CLK (GTP_DFF_C) clock pessimism 0.000 - 9.059 + 3.510 @@ -91275,15 +92712,15 @@ clock uncertainty 0.000 - 9.059 + 3.510 Removal time - -0.011 - 9.048 + -0.251 + 3.259 @@ -91292,27 +92729,27 @@ - 1.092 - 0 - 10 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_dqs_training_rstn/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[2].u_ddc_ca/RST_TRAINING_N + 1.273 + 1 + 22 + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[0]/C - ddrphy_clkin - ddrphy_clkin + clk_200m + clk_200m rise-rise 0.000 - 9.059 - 9.059 + 5.192 + 5.192 0.000 0.000 - 1.081 - 0.323 (29.9%) - 0.758 (70.1%) + 1.022 + 0.329 (32.2%) + 0.693 (67.8%) - Path #5: removal slack is 1.092(MET) + Path #7: removal slack is 1.273(MET) -
+
Location Delay Type @@ -91322,7 +92759,7 @@ Logical Resource - Clock ddrphy_clkin (rising edge) + Clock clk_200m (rising edge) 0.000 0.000 @@ -91387,11 +92824,11 @@ - net (fanout=851) - 1.976 - 4.367 + net (fanout=7) + 0.605 + 2.996 - zoom_clk + ddr_clk @@ -91405,15 +92842,15 @@ td 0.000 - 4.367 + 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) net (fanout=71) - 0.847 - 5.214 + 2.196 + 5.192 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin @@ -91422,72 +92859,48 @@ - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - - - - td - 0.094 - 5.308 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/CLK (GTP_DFF_C) - - net (fanout=3) - 0.605 - 5.913 - - u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] + + tco + 0.329 + 5.521 + r + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/Q (GTP_DFF_C) - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) - - - - td + net (fanout=1) 0.000 - 5.913 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) + 5.521 + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/logic_rstn + - net (fanout=5817) - 3.146 - 9.059 - - u_axi_ddr_top/clk - - - - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_dqs_training_rstn/CLK (GTP_DFF_C) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/N0/I (GTP_INV) - tco - 0.323 - 9.382 + td + 0.000 + 5.521 f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_training_ctrl/ddrphy_dqs_training_rstn/Q (GTP_DFF_C) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/N0/Z (GTP_INV) - net (fanout=10) - 0.758 - 10.140 + net (fanout=22) + 0.693 + 6.214 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dqs_training_rstn + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/N0 @@ -91495,12 +92908,12 @@ f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[2].u_ddc_ca/RST_TRAINING_N (GTP_DDC_E1) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[0]/C (GTP_DFF_C)
- +
Location Delay Type @@ -91510,7 +92923,7 @@ Logical Resource - Clock ddrphy_clkin (rising edge) + Clock clk_200m (rising edge) 0.000 0.000 @@ -91575,11 +92988,11 @@ - net (fanout=851) - 1.976 - 4.367 + net (fanout=7) + 0.605 + 2.996 - zoom_clk + ddr_clk @@ -91593,79 +93006,31 @@ td 0.000 - 4.367 + 2.996 r u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) net (fanout=71) - 0.847 - 5.214 + 2.196 + 5.192 u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKIN1 (GTP_PLL_E3) - - - - td - 0.094 - 5.308 - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrphy_pll_0/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - - - - net (fanout=3) - 0.605 - 5.913 - - u_axi_ddr_top/I_ipsxb_ddr_top/ddrphy_ioclk_source [0] - - - - - - - - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKIN (GTP_IOCLKDIV) - - - - td - 0.000 - 5.913 - r - u_axi_ddr_top/I_ipsxb_ddr_top/I_GTP_CLKDIV/CLKDIVOUT (GTP_IOCLKDIV) - - - - net (fanout=5817) - 3.146 - 9.059 - - u_axi_ddr_top/clk - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[2].u_ddc_ca/CLKB (GTP_DDC_E1) + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[0]/CLK (GTP_DFF_C) clock pessimism 0.000 - 9.059 + 5.192 @@ -91673,15 +93038,15 @@ clock uncertainty 0.000 - 9.059 + 5.192 Removal time - -0.011 - 9.048 + -0.251 + 4.941 @@ -91690,27 +93055,27 @@ - 1.185 - 1 - 3 - rstn_out1/CLK - ms72xx_ctl/rstn_temp1/C + 1.336 + 0 + 120 + image_filiter_inst/multiline_buffer_inst/srst/CLK + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/RSTB - clk_10m - clk_10m + clk_50m + clk_50m rise-rise - 0.000 - 3.510 - 3.510 + 0.515 + 5.523 + 6.038 0.000 0.000 - 0.934 - 0.329 (35.2%) - 0.605 (64.8%) + 1.825 + 0.323 (17.7%) + 1.502 (82.3%) - Path #6: removal slack is 1.185(MET) + Path #8: removal slack is 1.336(MET) -
+
Location Delay Type @@ -91720,7 +93085,7 @@ Logical Resource - Clock clk_10m (rising edge) + Clock clk_50m (rising edge) 0.000 0.000 @@ -91781,15 +93146,15 @@ 0.094 2.396 r - u_sys_pll/u_pll_e3/CLKOUT4 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=256) - 1.114 - 3.510 + net (fanout=2825) + 3.127 + 5.523 - clk_10m + rd3_clk @@ -91797,47 +93162,23 @@ r - rstn_out1/CLK (GTP_DFF_C) + image_filiter_inst/multiline_buffer_inst/srst/CLK (GTP_DFF_P) tco - 0.329 - 3.839 - r - rstn_out1/Q (GTP_DFF_C) - - - - net (fanout=3) - 0.000 - 3.839 - - nt_eth_rstn - - - - - - - - ms72xx_ctl/N0/I (GTP_INV) - - - - td - 0.000 - 3.839 + 0.323 + 5.846 f - ms72xx_ctl/N0/Z (GTP_INV) + image_filiter_inst/multiline_buffer_inst/srst/Q (GTP_DFF_P) - net (fanout=1) - 0.605 - 4.444 + net (fanout=120) + 1.502 + 7.348 - ms72xx_ctl/N0 + image_filiter_inst/multiline_buffer_inst/srst @@ -91845,12 +93186,12 @@ f - ms72xx_ctl/rstn_temp1/C (GTP_DFF_C) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/RSTB (GTP_DRM18K)
- +
Location Delay Type @@ -91860,7 +93201,7 @@ Logical Resource - Clock clk_10m (rising edge) + Clock clk_50m (rising edge) 0.000 0.000 @@ -91921,15 +93262,15 @@ 0.094 2.396 r - u_sys_pll/u_pll_e3/CLKOUT4 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=256) - 1.114 - 3.510 + net (fanout=2825) + 3.642 + 6.038 - clk_10m + rd3_clk @@ -91937,13 +93278,13 @@ r - ms72xx_ctl/rstn_temp1/CLK (GTP_DFF_C) + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKB (GTP_DRM18K) clock pessimism 0.000 - 3.510 + 6.038 @@ -91951,15 +93292,15 @@ clock uncertainty 0.000 - 3.510 + 6.038 Removal time - -0.251 - 3.259 + -0.026 + 6.012 @@ -91968,27 +93309,27 @@ - 1.273 - 1 - 22 - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/CLK - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[0]/C + 1.336 + 0 + 120 + image_filiter_inst/multiline_buffer_inst/srst/CLK + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/RSTB - clk_200m - clk_200m + clk_50m + clk_50m rise-rise - 0.000 - 6.563 - 6.563 + 0.515 + 5.523 + 6.038 0.000 0.000 - 1.022 - 0.329 (32.2%) - 0.693 (67.8%) + 1.825 + 0.323 (17.7%) + 1.502 (82.3%) - Path #7: removal slack is 1.273(MET) + Path #9: removal slack is 1.336(MET) -
+
Location Delay Type @@ -91998,7 +93339,7 @@ Logical Resource - Clock clk_200m (rising edge) + Clock clk_50m (rising edge) 0.000 0.000 @@ -92056,103 +93397,193 @@ td - 0.089 - 2.391 + 0.094 + 2.396 r - u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=851) - 1.976 - 4.367 + net (fanout=2825) + 3.127 + 5.523 - zoom_clk + rd3_clk + r + image_filiter_inst/multiline_buffer_inst/srst/CLK (GTP_DFF_P) + + + + tco + 0.323 + 5.846 + f + image_filiter_inst/multiline_buffer_inst/srst/Q (GTP_DFF_P) + + - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + net (fanout=120) + 1.502 + 7.348 + + image_filiter_inst/multiline_buffer_inst/srst + + + + + f + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/RSTB (GTP_DRM18K) + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_50m (rising edge) + + 0.000 + 0.000 + r + + + + clk - td 0.000 - 4.367 + 0.000 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + clk (port) - net (fanout=71) - 2.196 - 6.563 + net (fanout=1) + 0.000 + 0.000 - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + clk - r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/CLK (GTP_DFF_C) + + clk_ibuf/I (GTP_INBUF) - - tco - 0.329 - 6.892 + + td + 1.211 + 1.211 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/logic_rstn/Q (GTP_DFF_C) + clk_ibuf/O (GTP_INBUF) net (fanout=1) - 0.000 - 6.892 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/logic_rstn + 1.091 + 2.302 + + nt_clk - + - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/N0/I (GTP_INV) + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) - + td + 0.094 + 2.396 + r + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + + + + net (fanout=2825) + 3.642 + 6.038 + + rd3_clk + + + + + + + r + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKB (GTP_DRM18K) + + + clock pessimism + 0.000 - 6.892 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/N0/Z (GTP_INV) + 6.038 + + + clock uncertainty + + 0.000 + 6.038 + - net (fanout=22) - 0.693 - 7.585 - - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/N0 - + Removal time + -0.026 + 6.012 - f - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[0]/C (GTP_DFF_C)
+
+
+ + 1.336 + 0 + 120 + image_filiter_inst/multiline_buffer_inst/srst/CLK + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/RSTB + + clk_50m + clk_50m + rise-rise + 0.515 + 5.523 + 6.038 + 0.000 + 0.000 + 1.825 + 0.323 (17.7%) + 1.502 (82.3%) + + Path #10: removal slack is 1.336(MET) - +
Location Delay Type @@ -92162,7 +93593,7 @@ Logical Resource - Clock clk_200m (rising edge) + Clock clk_50m (rising edge) 0.000 0.000 @@ -92220,56 +93651,148 @@ td - 0.089 - 2.391 + 0.094 + 2.396 r - u_sys_pll/u_pll_e3/CLKOUT1 (GTP_PLL_E3) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) - net (fanout=851) - 1.976 - 4.367 + net (fanout=2825) + 3.127 + 5.523 - zoom_clk + rd3_clk + r + image_filiter_inst/multiline_buffer_inst/srst/CLK (GTP_DFF_P) + + + + tco + 0.323 + 5.846 + f + image_filiter_inst/multiline_buffer_inst/srst/Q (GTP_DFF_P) + + - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKIN (GTP_CLKBUFG) + net (fanout=120) + 1.502 + 7.348 + + image_filiter_inst/multiline_buffer_inst/srst + + + + + f + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/RSTB (GTP_DRM18K) + +
+
+ + + + Location + Delay Type + Incr + Path + Trans + Logical Resource + + + Clock clk_50m (rising edge) + + 0.000 + 0.000 + r + + + + clk - td 0.000 - 4.367 + 0.000 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_clkbufg/CLKOUT (GTP_CLKBUFG) + clk (port) - net (fanout=71) - 2.196 - 6.563 + net (fanout=1) + 0.000 + 0.000 - u_axi_ddr_top/I_ipsxb_ddr_top/pll_clkin + clk + + + + + + + + clk_ibuf/I (GTP_INBUF) + td + 1.211 + 1.211 + r + clk_ibuf/O (GTP_INBUF) + + + net (fanout=1) + 1.091 + 2.302 + + nt_clk + + + + + + u_sys_pll/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.094 + 2.396 r - u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dll_update_ctrl/cnt[0]/CLK (GTP_DFF_C) + u_sys_pll/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + + + + net (fanout=2825) + 3.642 + 6.038 + + rd3_clk + + + + + + + r + image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKB (GTP_DRM18K) clock pessimism 0.000 - 6.563 + 6.038 @@ -92277,15 +93800,15 @@ clock uncertainty 0.000 - 6.563 + 6.038 Removal time - -0.251 - 6.312 + -0.026 + 6.012 @@ -92294,27 +93817,27 @@ - 1.337 + 1.545 0 - 120 - image_filiter_inst/multiline_buffer_inst/srst/CLK - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/RSTB + 181 + u_zoom_rst/rst/CLK + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/RSTA - clk_50m - clk_50m + clk_1080p60Hz + clk_1080p60Hz rise-rise 0.514 - 5.526 - 6.040 + 7.588 + 8.102 0.000 0.000 - 1.825 - 0.323 (17.7%) - 1.502 (82.3%) + 2.006 + 0.323 (16.1%) + 1.683 (83.9%) - Path #8: removal slack is 1.337(MET) + Path #11: removal slack is 1.545(MET) -
+
Location Delay Type @@ -92324,7 +93847,7 @@ Logical Resource - Clock clk_50m (rising edge) + Clock clk_1080p60Hz (rising edge) 0.000 0.000 @@ -92389,9 +93912,9 @@ - net (fanout=2827) - 3.130 - 5.526 + net (fanout=2825) + 3.127 + 5.523 rd3_clk @@ -92400,24 +93923,48 @@ + + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.094 + 5.617 r - image_filiter_inst/multiline_buffer_inst/srst/CLK (GTP_DFF_P) + U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + + + + net (fanout=844) + 1.971 + 7.588 + + zoom_clk + + + + + + + r + u_zoom_rst/rst/CLK (GTP_DFF_P) tco 0.323 - 5.849 + 7.911 f - image_filiter_inst/multiline_buffer_inst/srst/Q (GTP_DFF_P) + u_zoom_rst/rst/Q (GTP_DFF_P) - net (fanout=120) - 1.502 - 7.351 + net (fanout=181) + 1.683 + 9.594 - image_filiter_inst/multiline_buffer_inst/srst + zoom_rst @@ -92425,12 +93972,12 @@ f - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/RSTB (GTP_DRM18K) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/RSTA (GTP_DRM18K)
- +
Location Delay Type @@ -92440,7 +93987,7 @@ Logical Resource - Clock clk_50m (rising edge) + Clock clk_1080p60Hz (rising edge) 0.000 0.000 @@ -92505,9 +94052,9 @@ - net (fanout=2827) - 3.644 - 6.040 + net (fanout=2825) + 3.127 + 5.523 rd3_clk @@ -92516,14 +94063,38 @@ + + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.094 + 5.617 r - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKB (GTP_DRM18K) + U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + + + + net (fanout=844) + 2.485 + 8.102 + + zoom_clk + + + + + + + r + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA (GTP_DRM18K) clock pessimism 0.000 - 6.040 + 8.102 @@ -92531,15 +94102,15 @@ clock uncertainty 0.000 - 6.040 + 8.102 Removal time - -0.026 - 6.014 + -0.053 + 8.049 @@ -92548,27 +94119,27 @@ - 1.337 + 1.545 0 - 120 - image_filiter_inst/multiline_buffer_inst/srst/CLK - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/RSTB + 181 + u_zoom_rst/rst/CLK + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/RSTA - clk_50m - clk_50m + clk_1080p60Hz + clk_1080p60Hz rise-rise 0.514 - 5.526 - 6.040 + 7.588 + 8.102 0.000 0.000 - 1.825 - 0.323 (17.7%) - 1.502 (82.3%) + 2.006 + 0.323 (16.1%) + 1.683 (83.9%) - Path #9: removal slack is 1.337(MET) + Path #12: removal slack is 1.545(MET) -
+
Location Delay Type @@ -92578,7 +94149,7 @@ Logical Resource - Clock clk_50m (rising edge) + Clock clk_1080p60Hz (rising edge) 0.000 0.000 @@ -92643,9 +94214,9 @@ - net (fanout=2827) - 3.130 - 5.526 + net (fanout=2825) + 3.127 + 5.523 rd3_clk @@ -92654,24 +94225,48 @@ + + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.094 + 5.617 r - image_filiter_inst/multiline_buffer_inst/srst/CLK (GTP_DFF_P) + U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + + + + net (fanout=844) + 1.971 + 7.588 + + zoom_clk + + + + + + + r + u_zoom_rst/rst/CLK (GTP_DFF_P) tco 0.323 - 5.849 + 7.911 f - image_filiter_inst/multiline_buffer_inst/srst/Q (GTP_DFF_P) + u_zoom_rst/rst/Q (GTP_DFF_P) - net (fanout=120) - 1.502 - 7.351 + net (fanout=181) + 1.683 + 9.594 - image_filiter_inst/multiline_buffer_inst/srst + zoom_rst @@ -92679,12 +94274,12 @@ f - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/RSTB (GTP_DRM18K) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/RSTA (GTP_DRM18K)
- +
Location Delay Type @@ -92694,7 +94289,7 @@ Logical Resource - Clock clk_50m (rising edge) + Clock clk_1080p60Hz (rising edge) 0.000 0.000 @@ -92759,9 +94354,9 @@ - net (fanout=2827) - 3.644 - 6.040 + net (fanout=2825) + 3.127 + 5.523 rd3_clk @@ -92770,14 +94365,38 @@ + + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.094 + 5.617 r - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[0].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKB (GTP_DRM18K) + U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + + + + net (fanout=844) + 2.485 + 8.102 + + zoom_clk + + + + + + + r + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[1].U_GTP_DRM18K/CLKA (GTP_DRM18K) clock pessimism 0.000 - 6.040 + 8.102 @@ -92785,15 +94404,15 @@ clock uncertainty 0.000 - 6.040 + 8.102 Removal time - -0.026 - 6.014 + -0.053 + 8.049 @@ -92802,27 +94421,27 @@ - 1.337 + 1.545 0 - 120 - image_filiter_inst/multiline_buffer_inst/srst/CLK - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/RSTB + 181 + u_zoom_rst/rst/CLK + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM18K/RSTA - clk_50m - clk_50m + clk_1080p60Hz + clk_1080p60Hz rise-rise 0.514 - 5.526 - 6.040 + 7.588 + 8.102 0.000 0.000 - 1.825 - 0.323 (17.7%) - 1.502 (82.3%) + 2.006 + 0.323 (16.1%) + 1.683 (83.9%) - Path #10: removal slack is 1.337(MET) + Path #13: removal slack is 1.545(MET) -
+
Location Delay Type @@ -92832,7 +94451,7 @@ Logical Resource - Clock clk_50m (rising edge) + Clock clk_1080p60Hz (rising edge) 0.000 0.000 @@ -92897,9 +94516,9 @@ - net (fanout=2827) - 3.130 - 5.526 + net (fanout=2825) + 3.127 + 5.523 rd3_clk @@ -92908,24 +94527,48 @@ + + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.094 + 5.617 r - image_filiter_inst/multiline_buffer_inst/srst/CLK (GTP_DFF_P) + U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + + + + net (fanout=844) + 1.971 + 7.588 + + zoom_clk + + + + + + + r + u_zoom_rst/rst/CLK (GTP_DFF_P) tco 0.323 - 5.849 + 7.911 f - image_filiter_inst/multiline_buffer_inst/srst/Q (GTP_DFF_P) + u_zoom_rst/rst/Q (GTP_DFF_P) - net (fanout=120) - 1.502 - 7.351 + net (fanout=181) + 1.683 + 9.594 - image_filiter_inst/multiline_buffer_inst/srst + zoom_rst @@ -92933,12 +94576,12 @@ f - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/RSTB (GTP_DRM18K) + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM18K/RSTA (GTP_DRM18K)
- +
Location Delay Type @@ -92948,7 +94591,7 @@ Logical Resource - Clock clk_50m (rising edge) + Clock clk_1080p60Hz (rising edge) 0.000 0.000 @@ -93013,9 +94656,9 @@ - net (fanout=2827) - 3.644 - 6.040 + net (fanout=2825) + 3.127 + 5.523 rd3_clk @@ -93024,14 +94667,38 @@ + + U_HDMI_PLL/u_pll_e3/CLKIN1 (GTP_PLL_E3) + + + + td + 0.094 + 5.617 r - image_filiter_inst/multiline_buffer_inst/g_fifo_connect[1].line_fifo/U_ipml_fifo_sync_fifo_2048x16/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKB (GTP_DRM18K) + U_HDMI_PLL/u_pll_e3/CLKOUT0 (GTP_PLL_E3) + + + + net (fanout=844) + 2.485 + 8.102 + + zoom_clk + + + + + + + r + u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[2].U_GTP_DRM18K/CLKA (GTP_DRM18K) clock pessimism 0.000 - 6.040 + 8.102 @@ -93039,15 +94706,15 @@ clock uncertainty 0.000 - 6.040 + 8.102 Removal time - -0.026 - 6.014 + -0.053 + 8.049 @@ -93066,17 +94733,17 @@ clk_720p60Hz rise-rise 0.514 - 8.073 - 8.587 + 8.070 + 8.584 0.000 0.000 2.096 0.323 (15.4%) 1.773 (84.6%) - Path #11: removal slack is 1.608(MET) + Path #14: removal slack is 1.608(MET) -
+
Location Delay Type @@ -93151,9 +94818,9 @@ - net (fanout=2827) - 3.130 - 5.526 + net (fanout=2825) + 3.127 + 5.523 rd3_clk @@ -93169,7 +94836,7 @@ td 0.089 - 5.615 + 5.612 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) @@ -93177,7 +94844,7 @@ net (fanout=1758) 2.458 - 8.073 + 8.070 nt_pix_clk @@ -93193,7 +94860,7 @@ tco 0.323 - 8.396 + 8.393 f u_hdmi_rst/rst/Q (GTP_DFF_P) @@ -93201,7 +94868,7 @@ net (fanout=219) 1.773 - 10.169 + 10.166 rd2_rst @@ -93216,7 +94883,7 @@
- +
Location Delay Type @@ -93291,9 +94958,9 @@ - net (fanout=2827) - 3.130 - 5.526 + net (fanout=2825) + 3.127 + 5.523 rd3_clk @@ -93309,7 +94976,7 @@ td 0.089 - 5.615 + 5.612 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) @@ -93317,7 +94984,7 @@ net (fanout=1758) 2.972 - 8.587 + 8.584 nt_pix_clk @@ -93333,7 +95000,7 @@ clock pessimism 0.000 - 8.587 + 8.584 @@ -93341,7 +95008,7 @@ clock uncertainty 0.000 - 8.587 + 8.584 @@ -93349,7 +95016,7 @@ Removal time -0.026 - 8.561 + 8.558 @@ -93368,17 +95035,17 @@ clk_720p60Hz rise-rise 0.514 - 8.073 - 8.587 + 8.070 + 8.584 0.000 0.000 2.096 0.323 (15.4%) 1.773 (84.6%) - Path #12: removal slack is 1.608(MET) + Path #15: removal slack is 1.608(MET) -
+
Location Delay Type @@ -93453,9 +95120,9 @@ - net (fanout=2827) - 3.130 - 5.526 + net (fanout=2825) + 3.127 + 5.523 rd3_clk @@ -93471,7 +95138,7 @@ td 0.089 - 5.615 + 5.612 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) @@ -93479,7 +95146,7 @@ net (fanout=1758) 2.458 - 8.073 + 8.070 nt_pix_clk @@ -93495,7 +95162,7 @@ tco 0.323 - 8.396 + 8.393 f u_hdmi_rst/rst/Q (GTP_DFF_P) @@ -93503,7 +95170,7 @@ net (fanout=219) 1.773 - 10.169 + 10.166 rd2_rst @@ -93518,7 +95185,7 @@
- +
Location Delay Type @@ -93593,9 +95260,9 @@ - net (fanout=2827) - 3.130 - 5.526 + net (fanout=2825) + 3.127 + 5.523 rd3_clk @@ -93611,7 +95278,7 @@ td 0.089 - 5.615 + 5.612 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) @@ -93619,7 +95286,7 @@ net (fanout=1758) 2.972 - 8.587 + 8.584 nt_pix_clk @@ -93635,7 +95302,7 @@ clock pessimism 0.000 - 8.587 + 8.584 @@ -93643,7 +95310,7 @@ clock uncertainty 0.000 - 8.587 + 8.584 @@ -93651,7 +95318,7 @@ Removal time -0.026 - 8.561 + 8.558 @@ -93670,17 +95337,17 @@ clk_720p60Hz rise-rise 0.514 - 8.073 - 8.587 + 8.070 + 8.584 0.000 0.000 2.096 0.323 (15.4%) 1.773 (84.6%) - Path #13: removal slack is 1.608(MET) + Path #16: removal slack is 1.608(MET) -
+
Location Delay Type @@ -93755,9 +95422,9 @@ - net (fanout=2827) - 3.130 - 5.526 + net (fanout=2825) + 3.127 + 5.523 rd3_clk @@ -93773,7 +95440,7 @@ td 0.089 - 5.615 + 5.612 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) @@ -93781,7 +95448,7 @@ net (fanout=1758) 2.458 - 8.073 + 8.070 nt_pix_clk @@ -93797,7 +95464,7 @@ tco 0.323 - 8.396 + 8.393 f u_hdmi_rst/rst/Q (GTP_DFF_P) @@ -93805,7 +95472,7 @@ net (fanout=219) 1.773 - 10.169 + 10.166 rd2_rst @@ -93820,7 +95487,7 @@
- +
Location Delay Type @@ -93895,9 +95562,9 @@ - net (fanout=2827) - 3.130 - 5.526 + net (fanout=2825) + 3.127 + 5.523 rd3_clk @@ -93913,7 +95580,7 @@ td 0.089 - 5.615 + 5.612 r U_HDMI_PLL/u_pll_e3/CLKOUT1 (GTP_PLL_E3) @@ -93921,7 +95588,7 @@ net (fanout=1758) 2.972 - 8.587 + 8.584 nt_pix_clk @@ -93937,7 +95604,7 @@ clock pessimism 0.000 - 8.587 + 8.584 @@ -93945,7 +95612,7 @@ clock uncertainty 0.000 - 8.587 + 8.584 @@ -93953,7 +95620,7 @@ Removal time -0.026 - 8.561 + 8.558 @@ -93977,7 +95644,7 @@ 1.250 0.853 ioclk2 - Low Pulse Width + High Pulse Width u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_ddc_ca/CLKA @@ -93986,7 +95653,7 @@ 1.250 0.853 ioclk2 - High Pulse Width + Low Pulse Width u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[0].u_ddc_ca/CLKA @@ -93995,7 +95662,7 @@ 1.250 0.853 ioclk0 - Low Pulse Width + High Pulse Width u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[1].u_ddc_ca/CLKA @@ -94004,7 +95671,7 @@ 1.250 0.853 ioclk0 - High Pulse Width + Low Pulse Width u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_ca_group[1].u_ddc_ca/CLKA @@ -94054,29 +95721,56 @@ u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/u_ddc_dqs/CLKA - 1.362 + 1.880 2.500 - 1.138 + 0.620 + clk_200m + Low Pulse Width + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/CLK + + + 1.880 + 2.500 + 0.620 clk_200m High Pulse Width - u_zoom_image/mult_fra0/N2/CLK + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r1[0]/CLK - 1.362 + 1.880 2.500 - 1.138 + 0.620 clk_200m + High Pulse Width + + u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrp_rstn_sync/sig_async_r2[0]/CLK + + + 2.230 + 3.368 + 1.138 + clk_1080p60Hz Low Pulse Width u_zoom_image/mult_fra0/N2/CLK - 1.362 - 2.500 + 2.230 + 3.368 1.138 - clk_200m - Low Pulse Width + clk_1080p60Hz + High Pulse Width + + u_zoom_image/mult_fra0/N2/CLK + + + 2.230 + 3.368 + 1.138 + clk_1080p60Hz + High Pulse Width u_zoom_image/mult_fra0_0/N2/CLK @@ -94085,7 +95779,7 @@ 3.333 0.898 hdmi_in_clk - High Pulse Width + Low Pulse Width u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA @@ -94094,7 +95788,7 @@ 3.333 0.898 hdmi_in_clk - Low Pulse Width + High Pulse Width u_axi_ddr_top/u_axi_wr_connect/image_in_fifo1/U_ipml_fifo_image_in_fifo/U_ipml_sdpram/ADDR_LOOP[0].DATA_LOOP[0].U_GTP_DRM18K/CLKA @@ -94112,7 +95806,7 @@ 4.000 1.517 eth_rxc - High Pulse Width + Low Pulse Width udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_ctl_in/RCLK @@ -94121,7 +95815,7 @@ 4.000 1.517 eth_rxc - Low Pulse Width + High Pulse Width udp_osd_inst/eth_udp_inst/u_gmii_to_rgmii/gmii_ctl_in/RCLK @@ -94166,7 +95860,7 @@ 5.000 0.620 ioclk_gate_clk - High Pulse Width + Low Pulse Width u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_ioclk_gate/CLK @@ -94175,7 +95869,7 @@ 5.000 0.620 ioclk_gate_clk - Low Pulse Width + High Pulse Width u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/ddrphy_ioclk_gate/CLK @@ -94376,10 +96070,10 @@ -Total LUTs: 13933 of 42800 (32.55%) +Total LUTs: 13939 of 42800 (32.57%) LUTs as dram: 88 of 17000 (0.52%) - LUTs as logic: 13845 -Total Registers: 13710 of 64200 (21.36%) + LUTs as logic: 13851 +Total Registers: 13708 of 64200 (21.35%) Total Latches: 0 DRM18K: @@ -94433,7 +96127,7 @@ Total I/O ports = 180 of 296 (60.81%) GTP_DFF_R - 1515 + 1513 GTP_DFF_RE @@ -94489,39 +96183,39 @@ Total I/O ports = 180 of 296 (60.81%) GTP_LUT1 - 146 + 145 GTP_LUT2 - 1431 + 1448 GTP_LUT3 - 2070 + 2040 GTP_LUT4 - 1796 + 1794 GTP_LUT5 - 2751 + 2782 GTP_LUT5CARRY - 4656 + 4653 GTP_LUT5M - 995 + 989 GTP_MUX2LUT6 - 114 + 104 GTP_MUX2LUT7 - 32 + 31 GTP_OSERDES @@ -94585,10 +96279,10 @@ Total I/O ports = 180 of 296 (60.81%) RAM(GB) - 0h:1m:28s - 0h:1m:39s - 0h:1m:58s - 764 + 0h:1m:32s + 0h:1m:43s + 0h:1m:59s + 759 WINDOWS 10 x86_64 Intel(R) Core(TM) i7-9750H CPU @ 2.60GHz 32 @@ -97986,6 +99680,15 @@ Total I/O ports = 180 of 296 (60.81%) Public-4008: Instance 'u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/rd_water_level[15:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. + + Public-4008: Instance 'u_rotate_image/cnt_1s[31:0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'u_rotate_image/frame_cnt[7:0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'u_rotate_image/freq[7:0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'u_zoom_image/zoom_done' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. @@ -101577,15 +103280,6 @@ Total I/O ports = 180 of 296 (60.81%) Removed bmsWIDEDFFRSE inst image_filiter_inst2/hybrid_filter_inst/median_finder9_b/mat[0][0][4:0] that is redundant to image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][0][4:0] - - Removed bmsSUB inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N14 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N14 - - - Removed bmsSUB inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N14 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N14 - - - Removed bmsSUB inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N14 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N14 - Removed bmsWIDEDFFRSE inst image_filiter_inst/hybrid_filter_inst/median_finder9_g/mat[0][1][5:0] that is redundant to image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[0][1][5:0] @@ -101605,124 +103299,16 @@ Total I/O ports = 180 of 296 (60.81%) Removed bmsWIDEDFFRSE inst u_ddr_addr_ctr/u_rd3_addr_ctr/wr0_async_to_wr1_sync/data_in0[4:0] that is redundant to u_ddr_addr_ctr/u_rd0_addr_ctr/wr_image_cnt0[4:0] - Removed bmsADD inst udp_osd_inst/eth_udp_inst/u_udp/u_udp_tx/N3514 that is redundant to udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3885 - - - Removed bmsADD inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/N1 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/N1 - - - Removed bmsADD inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/N1 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/N1 - - - Removed bmsADD inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/N1 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/N1 - - - Removed bmsADD inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/N1 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/N1 - - - Removed bmsADD inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/N1 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/N1 - - - Removed bmsADD inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/N1 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/N1 - - - Removed bmsADD inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/N1 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/N1 - - - Removed bmsWIDEDFFRSE inst image_filiter_inst/hybrid_filter_inst/median_finder9_r/mat[0][0][4:0] that is redundant to image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][0][4:0] - - - Removed bmsWIDEDFFRSE inst image_filiter_inst/hybrid_filter_inst/median_finder9_b/mat[0][1][4:0] that is redundant to image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][1][4:0] - - - Removed bmsWIDEDFFRSE inst image_filiter_inst/hybrid_filter_inst/median_finder9_r/mat[0][1][4:0] that is redundant to image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][1][4:0] - - - Removed bmsWIDEDFFRSE inst image_filiter_inst/hybrid_filter_inst/median_finder9_b/mat[0][2][4:0] that is redundant to image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][2][4:0] - - - Removed bmsWIDEDFFRSE inst image_filiter_inst/hybrid_filter_inst/median_finder9_r/mat[0][2][4:0] that is redundant to image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][2][4:0] - - - Removed bmsWIDEDFFRSE inst image_filiter_inst/hybrid_filter_inst/median_finder9_b/mat[1][0][4:0] that is redundant to image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][0][4:0] - - - Removed bmsWIDEDFFRSE inst image_filiter_inst/hybrid_filter_inst/median_finder9_r/mat[1][0][4:0] that is redundant to image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][0][4:0] - - - Removed bmsWIDEDFFRSE inst image_filiter_inst/hybrid_filter_inst/median_finder9_b/mat[1][1][4:0] that is redundant to image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][1][4:0] - - - Removed bmsWIDEDFFRSE inst image_filiter_inst/hybrid_filter_inst/median_finder9_r/mat[1][1][4:0] that is redundant to image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][1][4:0] - - - Removed bmsWIDEDFFRSE inst image_filiter_inst/hybrid_filter_inst/median_finder9_b/mat[1][2][4:0] that is redundant to image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][2][4:0] - - - Removed bmsWIDEDFFRSE inst image_filiter_inst/hybrid_filter_inst/median_finder9_r/mat[1][2][4:0] that is redundant to image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][2][4:0] - - - Removed bmsADD inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/N8 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N8 - - - Removed bmsADD inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/N8 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N8 - - - Removed bmsADD inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/N8 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N8 - - - Removed bmsADD inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/N8 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N8 - - - Removed bmsADD inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/N8 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N8 - - - Removed bmsADD inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/N8 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N8 - - - Removed bmsADD inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/N8 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N8 - - - Removed bmsADD inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/N8 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N8 - - - Removed bmsWIDEDFFRSE inst image_filiter_inst2/hybrid_filter_inst/median_finder9_g/mat[2][0][5:0] that is redundant to image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][0][5:0] - - - Removed bmsADD inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N12 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N12 - - - Removed bmsADD inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N12 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N12 - - - Removed bmsADD inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N12 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N12 - - - Removed bmsWIDEDFFRSE inst image_filiter_inst2/hybrid_filter_inst/median_finder9_g/mat[2][1][5:0] that is redundant to image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][1][5:0] - - - Removed bmsWIDEDFFRSE inst image_filiter_inst2/hybrid_filter_inst/median_finder9_g/mat[2][2][5:0] that is redundant to image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][2][5:0] - - - Removed bmsSUB inst udp_osd_inst/eth_udp_inst/u_udp/u_udp_tx/N307_0 that is redundant to udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N348_0 - - - Removed bmsADD inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N162[9:0]_4 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N46 - - - Removed bmsWIDEDFFRSE inst image_filiter_inst2/hybrid_filter_inst/median_finder9_r/mat[2][0][4:0] that is redundant to image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][0][4:0] - - - Removed bmsWIDEDFFRSE inst image_filiter_inst2/hybrid_filter_inst/median_finder9_b/mat[2][1][4:0] that is redundant to image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][1][4:0] + Removed bmsSUB inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N14 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N14 - Removed bmsWIDEDFFRSE inst image_filiter_inst2/hybrid_filter_inst/median_finder9_r/mat[2][1][4:0] that is redundant to image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][1][4:0] + Removed bmsSUB inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N14 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N14 - Removed bmsWIDEDFFRSE inst image_filiter_inst2/hybrid_filter_inst/median_finder9_b/mat[2][2][4:0] that is redundant to image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][2][4:0] + Removed bmsSUB inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N14 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N14 - Removed bmsWIDEDFFRSE inst image_filiter_inst2/hybrid_filter_inst/median_finder9_r/mat[2][2][4:0] that is redundant to image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][2][4:0] + Removed bmsADD inst udp_osd_inst/eth_udp_inst/u_udp/u_udp_tx/N3514 that is redundant to udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N3885 Removed bmsADD inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/N1 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/N1 @@ -101746,85 +103332,37 @@ Total I/O ports = 180 of 296 (60.81%) Removed bmsADD inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/N1 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/N1 - Removed bmsWIDEDFFRSE inst image_filiter_inst2/hybrid_filter_inst/median_finder9_r/mat[0][0][4:0] that is redundant to image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][0][4:0] - - - Removed bmsWIDEDFFRSE inst image_filiter_inst2/hybrid_filter_inst/median_finder9_b/mat[0][1][4:0] that is redundant to image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][1][4:0] - - - Removed bmsWIDEDFFRSE inst image_filiter_inst2/hybrid_filter_inst/median_finder9_r/mat[0][1][4:0] that is redundant to image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][1][4:0] - - - Removed bmsWIDEDFFRSE inst image_filiter_inst2/hybrid_filter_inst/median_finder9_b/mat[0][2][4:0] that is redundant to image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][2][4:0] - - - Removed bmsWIDEDFFRSE inst image_filiter_inst2/hybrid_filter_inst/median_finder9_r/mat[0][2][4:0] that is redundant to image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][2][4:0] - - - Removed bmsWIDEDFFRSE inst image_filiter_inst2/hybrid_filter_inst/median_finder9_b/mat[1][0][4:0] that is redundant to image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][0][4:0] - - - Removed bmsWIDEDFFRSE inst image_filiter_inst2/hybrid_filter_inst/median_finder9_r/mat[1][0][4:0] that is redundant to image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][0][4:0] - - - Removed bmsWIDEDFFRSE inst image_filiter_inst2/hybrid_filter_inst/median_finder9_b/mat[1][1][4:0] that is redundant to image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][1][4:0] - - - Removed bmsWIDEDFFRSE inst image_filiter_inst2/hybrid_filter_inst/median_finder9_r/mat[1][1][4:0] that is redundant to image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][1][4:0] - - - Removed bmsWIDEDFFRSE inst image_filiter_inst2/hybrid_filter_inst/median_finder9_b/mat[1][2][4:0] that is redundant to image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][2][4:0] - - - Removed bmsWIDEDFFRSE inst image_filiter_inst2/hybrid_filter_inst/median_finder9_r/mat[1][2][4:0] that is redundant to image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][2][4:0] - - - Removed bmsADD inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/N3 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/N3 - - - Removed bmsWIDEDFFRSE inst u_ov5640/u_mix_image/cmos2_vsync0 that is redundant to u_ov5640/cmos2_8_16bit/vs_in0 - - - Removed bmsREDOR inst udp_osd_inst/eth_udp_inst/u_udp/u_udp_tx/N545 that is redundant to udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N592 - - - Removed bmsREDOR inst udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N592 that is redundant to udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376 - - - Removed bmsWIDEDFFRSE inst u_ov5640/u_mix_image/cmos1_vsync0 that is redundant to u_ov5640/cmos1_8_16bit/vs_in0 - - - Removed bmsWIDEDFFRSE inst image_filiter_inst/hybrid_filter_inst/median_finder9_b/mat[0][0][4:0] that is redundant to image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][0][4:0] + Removed bmsWIDEDFFRSE inst image_filiter_inst/hybrid_filter_inst/median_finder9_r/mat[0][0][4:0] that is redundant to image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][0][4:0] - Removed bmsWIDEDFFCPE inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_control_path_adj/phy_we_n_r[3:0] that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_control_path_adj/phy_ras_n_r[3:0] + Removed bmsWIDEDFFRSE inst image_filiter_inst/hybrid_filter_inst/median_finder9_b/mat[0][1][4:0] that is redundant to image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][1][4:0] - Removed bmsWIDEDFFCPE inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_control_path_adj/phy_ras_n_r[3:0] that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_control_path_adj/phy_cas_n_r[3:0] + Removed bmsWIDEDFFRSE inst image_filiter_inst/hybrid_filter_inst/median_finder9_r/mat[0][1][4:0] that is redundant to image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][1][4:0] - Removed bmsWIDEDFFCPE inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_control_path_adj/phy_cs_n_r[3:0] that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_control_path_adj/phy_cas_n_r[3:0] + Removed bmsWIDEDFFRSE inst image_filiter_inst/hybrid_filter_inst/median_finder9_b/mat[0][2][4:0] that is redundant to image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][2][4:0] - Removed bmsLT inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/N21_0 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/N21_0 + Removed bmsWIDEDFFRSE inst image_filiter_inst/hybrid_filter_inst/median_finder9_r/mat[0][2][4:0] that is redundant to image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[0][2][4:0] - Removed bmsLT inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/N21_0 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/N21_0 + Removed bmsWIDEDFFRSE inst image_filiter_inst/hybrid_filter_inst/median_finder9_b/mat[1][0][4:0] that is redundant to image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][0][4:0] - Removed bmsLT inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/N21_0 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/N21_0 + Removed bmsWIDEDFFRSE inst image_filiter_inst/hybrid_filter_inst/median_finder9_r/mat[1][0][4:0] that is redundant to image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][0][4:0] - Removed bmsLT inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/N21_0 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/N21_0 + Removed bmsWIDEDFFRSE inst image_filiter_inst/hybrid_filter_inst/median_finder9_b/mat[1][1][4:0] that is redundant to image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][1][4:0] - Removed bmsLT inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/N21_0 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/N21_0 + Removed bmsWIDEDFFRSE inst image_filiter_inst/hybrid_filter_inst/median_finder9_r/mat[1][1][4:0] that is redundant to image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][1][4:0] - Removed bmsLT inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/N21_0 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/N21_0 + Removed bmsWIDEDFFRSE inst image_filiter_inst/hybrid_filter_inst/median_finder9_b/mat[1][2][4:0] that is redundant to image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[1][2][4:0] - Removed bmsLT inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/N21_0 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/N21_0 + Removed bmsWIDEDFFRSE inst image_filiter_inst/hybrid_filter_inst/median_finder9_r/mat[1][2][4:0] that is redundant to image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/mat[1][2][4:0] Removed bmsADD inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/N3 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N3 @@ -101850,6 +103388,144 @@ Total I/O ports = 180 of 296 (60.81%) Removed bmsADD inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/N3 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N3 + + Removed bmsWIDEDFFRSE inst image_filiter_inst2/hybrid_filter_inst/median_finder9_g/mat[2][0][5:0] that is redundant to image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][0][5:0] + + + Removed bmsWIDEDFFRSE inst image_filiter_inst2/hybrid_filter_inst/median_finder9_g/mat[2][1][5:0] that is redundant to image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][1][5:0] + + + Removed bmsWIDEDFFRSE inst image_filiter_inst2/hybrid_filter_inst/median_finder9_g/mat[2][2][5:0] that is redundant to image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[2][2][5:0] + + + Removed bmsSUB inst udp_osd_inst/eth_udp_inst/u_udp/u_udp_tx/N307_0 that is redundant to udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N348_0 + + + Removed bmsADD inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N12 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N12 + + + Removed bmsADD inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N12 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N12 + + + Removed bmsADD inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N12 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N12 + + + Removed bmsWIDEDFFRSE inst image_filiter_inst2/hybrid_filter_inst/median_finder9_r/mat[2][0][4:0] that is redundant to image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][0][4:0] + + + Removed bmsWIDEDFFRSE inst image_filiter_inst2/hybrid_filter_inst/median_finder9_b/mat[2][1][4:0] that is redundant to image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][1][4:0] + + + Removed bmsWIDEDFFRSE inst image_filiter_inst2/hybrid_filter_inst/median_finder9_r/mat[2][1][4:0] that is redundant to image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][1][4:0] + + + Removed bmsWIDEDFFRSE inst image_filiter_inst2/hybrid_filter_inst/median_finder9_b/mat[2][2][4:0] that is redundant to image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][2][4:0] + + + Removed bmsWIDEDFFRSE inst image_filiter_inst2/hybrid_filter_inst/median_finder9_r/mat[2][2][4:0] that is redundant to image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[2][2][4:0] + + + Removed bmsREDOR inst udp_osd_inst/eth_udp_inst/u_udp/u_udp_tx/N496 that is redundant to udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N543 + + + Removed bmsREDOR inst udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N543 that is redundant to udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N409 + + + Removed bmsWIDEDFFRSE inst image_filiter_inst2/hybrid_filter_inst/median_finder9_r/mat[0][0][4:0] that is redundant to image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][0][4:0] + + + Removed bmsWIDEDFFRSE inst image_filiter_inst2/hybrid_filter_inst/median_finder9_b/mat[0][1][4:0] that is redundant to image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][1][4:0] + + + Removed bmsWIDEDFFRSE inst image_filiter_inst2/hybrid_filter_inst/median_finder9_r/mat[0][1][4:0] that is redundant to image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][1][4:0] + + + Removed bmsWIDEDFFRSE inst image_filiter_inst2/hybrid_filter_inst/median_finder9_b/mat[0][2][4:0] that is redundant to image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[0][2][4:0] + + + Removed bmsWIDEDFFRSE inst image_filiter_inst2/hybrid_filter_inst/median_finder9_r/mat[0][2][4:0] that is redundant to image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[0][2][4:0] + + + Removed bmsWIDEDFFRSE inst image_filiter_inst2/hybrid_filter_inst/median_finder9_b/mat[1][0][4:0] that is redundant to image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][0][4:0] + + + Removed bmsWIDEDFFRSE inst image_filiter_inst2/hybrid_filter_inst/median_finder9_r/mat[1][0][4:0] that is redundant to image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][0][4:0] + + + Removed bmsWIDEDFFRSE inst image_filiter_inst2/hybrid_filter_inst/median_finder9_b/mat[1][1][4:0] that is redundant to image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][1][4:0] + + + Removed bmsWIDEDFFRSE inst image_filiter_inst2/hybrid_filter_inst/median_finder9_r/mat[1][1][4:0] that is redundant to image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][1][4:0] + + + Removed bmsWIDEDFFRSE inst image_filiter_inst2/hybrid_filter_inst/median_finder9_b/mat[1][2][4:0] that is redundant to image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[1][2][4:0] + + + Removed bmsWIDEDFFRSE inst image_filiter_inst2/hybrid_filter_inst/median_finder9_r/mat[1][2][4:0] that is redundant to image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/mat[1][2][4:0] + + + Removed bmsADD inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/N3 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/N3 + + + Removed bmsWIDEDFFRSE inst u_ov5640/u_mix_image/cmos2_vsync0 that is redundant to u_ov5640/cmos2_8_16bit/vs_in0 + + + Removed bmsADD inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/N1 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/N1 + + + Removed bmsADD inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/N1 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/N1 + + + Removed bmsADD inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/N1 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/N1 + + + Removed bmsADD inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/N1 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/N1 + + + Removed bmsADD inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/N1 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/N1 + + + Removed bmsADD inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/N1 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/N1 + + + Removed bmsADD inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/N1 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/N1 + + + Removed bmsWIDEDFFRSE inst u_ov5640/u_mix_image/cmos1_vsync0 that is redundant to u_ov5640/cmos1_8_16bit/vs_in0 + + + Removed bmsWIDEDFFRSE inst image_filiter_inst/hybrid_filter_inst/median_finder9_b/mat[0][0][4:0] that is redundant to image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/mat[0][0][4:0] + + + Removed bmsWIDEDFFCPE inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_control_path_adj/phy_we_n_r[3:0] that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_control_path_adj/phy_ras_n_r[3:0] + + + Removed bmsWIDEDFFCPE inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_control_path_adj/phy_ras_n_r[3:0] that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_control_path_adj/phy_cas_n_r[3:0] + + + Removed bmsWIDEDFFCPE inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_control_path_adj/phy_cs_n_r[3:0] that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_control_path_adj/phy_cas_n_r[3:0] + + + Removed bmsLT inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/N21_0 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/N21_0 + + + Removed bmsLT inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/N21_0 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/N21_0 + + + Removed bmsLT inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/N21_0 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/N21_0 + + + Removed bmsLT inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/N21_0 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/N21_0 + + + Removed bmsLT inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/N21_0 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/N21_0 + + + Removed bmsLT inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/N21_0 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/N21_0 + + + Removed bmsLT inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/N21_0 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/N21_0 + Removed bmsWIDEDFFRSE inst image_filiter_inst/hybrid_filter_inst/median_finder9_g/mat[2][0][5:0] that is redundant to image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][0][5:0] @@ -101862,6 +103538,30 @@ Total I/O ports = 180 of 296 (60.81%) Removed bmsWIDEDFFRSE inst image_filiter_inst/hybrid_filter_inst/median_finder9_g/mat[2][2][5:0] that is redundant to image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/mat[2][2][5:0] + + Removed bmsADD inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/N8 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N8 + + + Removed bmsADD inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/N8 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N8 + + + Removed bmsADD inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/N8 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N8 + + + Removed bmsADD inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/N8 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N8 + + + Removed bmsADD inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/N8 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N8 + + + Removed bmsADD inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/N8 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N8 + + + Removed bmsADD inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/N8 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N8 + + + Removed bmsADD inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/N8 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/N8 + Removed bmsWIDEDFFRSE inst image_filiter_inst2/hybrid_filter_inst/median_finder9_b/mat[2][0][4:0] that is redundant to image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/mat[2][0][4:0] @@ -102084,6 +103784,12 @@ Total I/O ports = 180 of 296 (60.81%) Removed bmsWIDEDFFRSE inst image_filiter_inst2/hybrid_filter_inst/median_finder9_g/mat[0][1][5:0] that is redundant to image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][1][5:0] + + Removed bmsREDOR inst udp_osd_inst/eth_udp_inst/u_udp/u_udp_tx/N545 that is redundant to udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N592 + + + Removed bmsREDOR inst udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N592 that is redundant to udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N376 + Removed bmsWIDEDFFRSE inst image_filiter_inst2/hybrid_filter_inst/median_finder9_g/mat[0][2][5:0] that is redundant to image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][2][5:0] @@ -102112,13 +103818,10 @@ Total I/O ports = 180 of 296 (60.81%) Removed bmsWIDEDFFRSE inst image_filiter_inst2/hybrid_filter_inst/median_finder9_g/mat[1][2][5:0] that is redundant to image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[1][2][5:0] - Removed bmsWIDEDFFRSE inst image_filiter_inst2/hybrid_filter_inst/median_finder9_g/mat[0][0][5:0] that is redundant to image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][0][5:0] - - - Removed bmsREDOR inst udp_osd_inst/eth_udp_inst/u_udp/u_udp_tx/N496 that is redundant to udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N543 + Removed bmsADD inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_sm/N162[9:0]_4 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/N46 - Removed bmsREDOR inst udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/N543 that is redundant to udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/N409 + Removed bmsWIDEDFFRSE inst image_filiter_inst2/hybrid_filter_inst/median_finder9_g/mat[0][0][5:0] that is redundant to image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/mat[0][0][5:0] Removed bmsWIDEDFFCPE inst image_filiter_inst2/multiline_buffer_inst/rst_s1 that is redundant to image_filiter_inst/multiline_buffer_inst/rst_s1 @@ -102127,22 +103830,22 @@ Total I/O ports = 180 of 296 (60.81%) Removed bmsWIDEDFFRSE inst u_ov5640/u_mix_image/cmos1_vsync1 that is redundant to u_ov5640/cmos1_8_16bit/vs_in1 - Removed bmsWIDEMUX inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N15 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N15 + Removed bmsWIDEDFFCPE inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/dqs_gate_vld_d that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r - Removed bmsWIDEMUX inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N15 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N15 + Removed bmsWIDEDFFCPE inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_cke that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_cke - Removed bmsWIDEMUX inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N15 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N15 + Removed bmsWIDEDFFCPE inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/upcal/upcal_cke that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_cke - Removed bmsWIDEDFFCPE inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/dqs_gate_vld_d that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_vld_r + Removed bmsWIDEMUX inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N15 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N15 - Removed bmsWIDEDFFCPE inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/rdcal/rdcal_cke that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_cke + Removed bmsWIDEMUX inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqsi_rdel_cal/N15 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N15 - Removed bmsWIDEDFFCPE inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/upcal/upcal_cke that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_cke + Removed bmsWIDEMUX inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqsi_rdel_cal/N15 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N15 Removed bmsWIDEMUX inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqsi_rdel_cal/N17 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/N17 @@ -102477,15 +104180,6 @@ Total I/O ports = 180 of 296 (60.81%) Removed bmsWIDEDFFCPE inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_gate_update_ctrl/drift_dqs_group[3].ddrphy_drift_ctrl/dqs_drift_init_done that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_gate_update_ctrl/drift_dqs_group[0].ddrphy_drift_ctrl/dqs_drift_init_done - - Removed bmsREDOR inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N127 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N127 - - - Removed bmsREDOR inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N127 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N127 - - - Removed bmsREDOR inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N127 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N127 - Removed bmsWIDEDFFCPE inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_update1_d1 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_update1_d1 @@ -102516,6 +104210,15 @@ Total I/O ports = 180 of 296 (60.81%) Removed bmsWIDEDFFCPE inst adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[2].u_divider_step/rdy that is redundant to adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[2].u_divider_step/rdy + + Removed bmsREDOR inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N127 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N127 + + + Removed bmsREDOR inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N127 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N127 + + + Removed bmsREDOR inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N127 that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/N127 + Removed bmsWIDEDFFCPE inst adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[3].u_divider_step/rdy that is redundant to adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[3].u_divider_step/rdy @@ -103480,7 +105183,7 @@ Total I/O ports = 180 of 296 (60.81%) Removed bmsWIDEDFFCPE inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcd_top/mcdq_dcd_bm/zqcs_req that is stuck at constant 0. - Removed bmsWIDEDFFRSE inst u_ddr_addr_ctr/clk_cnt[31:0] at 22 that is stuck at constant 0. + Removed bmsWIDEDFFRSE inst u_ddr_addr_ctr/clk_cnt[31:0] at 20 that is stuck at constant 0. Removed bmsWIDEDFFPATRE inst u_ddr_addr_ctr/u_rd0_addr_ctr/rd0_sta_reg at 3 that is stuck at constant 0. @@ -105001,49 +106704,49 @@ Total I/O ports = 180 of 296 (60.81%) Removed inst param_manager_inst/param_rotate/key_debounce_inst2/cnt[23:0] which is redundant to param_manager_inst/param_filiter1_mode/key_debounce_inst2/cnt[23:0] (type bmsWIDEDFFRSE) - Removed inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[4][7:0] which is redundant to udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][7:0] (type bmsWIDEDFFPATCE) + Removed inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[2][7:0] which is redundant to udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][7:0] (type bmsWIDEDFFPATCE) - Removed inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[5][7:0] which is redundant to udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][7:0] (type bmsWIDEDFFPATCE) + Removed inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][7:0] which is redundant to udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][7:0] (type bmsWIDEDFFPATCE) - Removed inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[6][7:0] which is redundant to udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][7:0] (type bmsWIDEDFFPATCE) + Removed inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[4][7:0] which is redundant to udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][7:0] (type bmsWIDEDFFPATCE) - Removed inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/eth_head[11][7:0] which is redundant to udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][7:0] (type bmsWIDEDFFPATCE) + Removed inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[5][7:0] which is redundant to udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][7:0] (type bmsWIDEDFFPATCE) - Removed inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[0][7:0] which is redundant to udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][7:0] (type bmsWIDEDFFPATCE) + Removed inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[6][7:0] which is redundant to udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][7:0] (type bmsWIDEDFFPATCE) - Removed inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][7:0] which is redundant to udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][7:0] (type bmsWIDEDFFPATCE) + Removed inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/eth_head[11][7:0] which is redundant to udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][7:0] (type bmsWIDEDFFPATCE) - Removed inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[2][7:0] which is redundant to udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][7:0] (type bmsWIDEDFFPATCE) + Removed inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[0][7:0] which is redundant to udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][7:0] (type bmsWIDEDFFPATCE) - Removed inst udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/preamble[0][7:0] which is redundant to udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][7:0] (type bmsWIDEDFFPATCE) + Removed inst udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/preamble[0][7:0] which is redundant to udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][7:0] (type bmsWIDEDFFPATCE) - Removed inst udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/preamble[1][7:0] which is redundant to udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][7:0] (type bmsWIDEDFFPATCE) + Removed inst udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/preamble[1][7:0] which is redundant to udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][7:0] (type bmsWIDEDFFPATCE) - Removed inst udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/preamble[2][7:0] which is redundant to udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][7:0] (type bmsWIDEDFFPATCE) + Removed inst udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/preamble[2][7:0] which is redundant to udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][7:0] (type bmsWIDEDFFPATCE) - Removed inst udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/preamble[3][7:0] which is redundant to udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][7:0] (type bmsWIDEDFFPATCE) + Removed inst udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/preamble[3][7:0] which is redundant to udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][7:0] (type bmsWIDEDFFPATCE) - Removed inst udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/preamble[4][7:0] which is redundant to udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][7:0] (type bmsWIDEDFFPATCE) + Removed inst udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/preamble[4][7:0] which is redundant to udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][7:0] (type bmsWIDEDFFPATCE) - Removed inst udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/preamble[5][7:0] which is redundant to udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][7:0] (type bmsWIDEDFFPATCE) + Removed inst udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/preamble[5][7:0] which is redundant to udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][7:0] (type bmsWIDEDFFPATCE) - Removed inst udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/preamble[6][7:0] which is redundant to udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][7:0] (type bmsWIDEDFFPATCE) + Removed inst udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/preamble[6][7:0] which is redundant to udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][7:0] (type bmsWIDEDFFPATCE) - Removed inst udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[11][7:0] which is redundant to udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][7:0] (type bmsWIDEDFFPATCE) + Removed inst udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/eth_head[11][7:0] which is redundant to udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][7:0] (type bmsWIDEDFFPATCE) Removed inst udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/preamble[7][7:0] which is redundant to udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[7][7:0] (type bmsWIDEDFFPATCE) @@ -105574,28 +107277,28 @@ Total I/O ports = 180 of 296 (60.81%) Removed bmsWIDEDFFPATCE inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/eth_head[13][7:0] at 7 that is stuck at constant 0. - Removed bmsWIDEDFFPATCE inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][7:0] at 0 that is stuck at constant 1. + Removed bmsWIDEDFFPATCE inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][7:0] at 0 that is stuck at constant 1. - Removed bmsWIDEDFFPATCE inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][7:0] at 1 that is stuck at constant 0. + Removed bmsWIDEDFFPATCE inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][7:0] at 1 that is stuck at constant 0. - Removed bmsWIDEDFFPATCE inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][7:0] at 2 that is stuck at constant 1. + Removed bmsWIDEDFFPATCE inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][7:0] at 2 that is stuck at constant 1. - Removed bmsWIDEDFFPATCE inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][7:0] at 3 that is stuck at constant 0. + Removed bmsWIDEDFFPATCE inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][7:0] at 3 that is stuck at constant 0. - Removed bmsWIDEDFFPATCE inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][7:0] at 4 that is stuck at constant 1. + Removed bmsWIDEDFFPATCE inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][7:0] at 4 that is stuck at constant 1. - Removed bmsWIDEDFFPATCE inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][7:0] at 5 that is stuck at constant 0. + Removed bmsWIDEDFFPATCE inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][7:0] at 5 that is stuck at constant 0. - Removed bmsWIDEDFFPATCE inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][7:0] at 6 that is stuck at constant 1. + Removed bmsWIDEDFFPATCE inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][7:0] at 6 that is stuck at constant 1. - Removed bmsWIDEDFFPATCE inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[3][7:0] at 7 that is stuck at constant 0. + Removed bmsWIDEDFFPATCE inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[1][7:0] at 7 that is stuck at constant 0. Removed bmsWIDEDFFPATCE inst udp_osd_inst/eth_udp_inst/u_arp/u_arp_tx/preamble[7][7:0] at 0 that is stuck at constant 1. @@ -105918,12 +107621,6 @@ Total I/O ports = 180 of 296 (60.81%) Removed bmsWIDEDFFRSE inst u_ddr_addr_ctr/u_rd1_addr_ctr/mult_h[10:0] at 0 that is stuck at constant 0. - - Removed bmsWIDEDFFRSE inst u_ddr_addr_ctr/u_rd1_addr_ctr/mult_addr[29:0] at 6 that is stuck at constant 0. - - - Removed bmsWIDEDFFRSE inst u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[29:0] at 6 that is stuck at constant 0. - Removed bmsWIDEDFFRSE inst u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[29:0] at 23 that is stuck at constant 1. @@ -105931,7 +107628,7 @@ Total I/O ports = 180 of 296 (60.81%) Removed bmsWIDEDFFRSE inst u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[29:0] at 24 that is stuck at constant 1. - Removed bmsWIDEDFFRSE inst u_axi_ddr_top/rd1_ddr_sart_addr0[29:0] at 8 that is stuck at constant 0. + Removed bmsWIDEDFFRSE inst u_ddr_addr_ctr/u_rd1_addr_ctr/mult_addr[29:0] at 6 that is stuck at constant 0. Removed bmsWIDEDFFRSE inst u_axi_ddr_top/rd1_ddr_sart_addr0[29:0] at 25 that is stuck at constant 1. @@ -105940,7 +107637,7 @@ Total I/O ports = 180 of 296 (60.81%) Removed bmsWIDEDFFRSE inst u_axi_ddr_top/rd1_ddr_sart_addr0[29:0] at 26 that is stuck at constant 1. - Removed bmsWIDEDFFRSE inst u_axi_ddr_top/rd1_ddr_sart_addr1[29:0] at 8 that is stuck at constant 0. + Removed bmsWIDEDFFRSE inst u_ddr_addr_ctr/u_rd1_addr_ctr/rd_ddr_addr0[29:0] at 6 that is stuck at constant 0. Removed bmsWIDEDFFRSE inst u_axi_ddr_top/rd1_ddr_sart_addr1[29:0] at 25 that is stuck at constant 1. @@ -105949,7 +107646,7 @@ Total I/O ports = 180 of 296 (60.81%) Removed bmsWIDEDFFRSE inst u_axi_ddr_top/rd1_ddr_sart_addr1[29:0] at 26 that is stuck at constant 1. - Removed bmsWIDEDFFRSE inst u_axi_ddr_top/rd1_ddr_sart_addr2[29:0] at 8 that is stuck at constant 0. + Removed bmsWIDEDFFRSE inst u_axi_ddr_top/rd1_ddr_sart_addr0[29:0] at 8 that is stuck at constant 0. Removed bmsWIDEDFFRSE inst u_axi_ddr_top/rd1_ddr_sart_addr2[29:0] at 25 that is stuck at constant 1. @@ -105957,6 +107654,12 @@ Total I/O ports = 180 of 296 (60.81%) Removed bmsWIDEDFFRSE inst u_axi_ddr_top/rd1_ddr_sart_addr2[29:0] at 26 that is stuck at constant 1. + + Removed bmsWIDEDFFRSE inst u_axi_ddr_top/rd1_ddr_sart_addr1[29:0] at 8 that is stuck at constant 0. + + + Removed bmsWIDEDFFRSE inst u_axi_ddr_top/rd1_ddr_sart_addr2[29:0] at 8 that is stuck at constant 0. + Public-4008: Instance 'u_ddr_addr_ctr/u_rd1_addr_ctr/abs_add_sift_h[9:0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. @@ -106011,6 +107714,18 @@ Total I/O ports = 180 of 296 (60.81%) Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/timing_cnt0[2:0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. + + Public-4008: Instance 'u_rotate_image/image_h_add1[11]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'u_rotate_image/image_h_add1[12]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'u_rotate_image/image_h_add1[13]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'u_rotate_image/image_h_add1[14]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'u_rotate_image/image_h_add2[11]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. @@ -106473,12 +108188,6 @@ Total I/O ports = 180 of 296 (60.81%) Public-4008: Instance 'udp_osd_inst/rgb_out[23]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[9]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_tx/check_buffer[20]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. @@ -106944,6 +108653,30 @@ Total I/O ports = 180 of 296 (60.81%) Public-4008: Instance 'adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[8].u_divider_step/quotient[12]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. + + Public-4008: Instance 'udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[24]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[25]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[26]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[27]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[28]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[29]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[30]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[31]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. + Public-4008: Instance 'adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[9].u_divider_step/quotient[5]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. @@ -106989,6 +108722,24 @@ Total I/O ports = 180 of 296 (60.81%) Public-4008: Instance 'adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[10].u_divider_step/quotient[12]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. + + Public-4008: Instance 'udp_wr_mem_inst/mem[114]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[115]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[116]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[117]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[118]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[119]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_h/g_sqrt_stepx[11].u_divider_step/quotient[7]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. @@ -107415,6 +109166,12 @@ Total I/O ports = 180 of 296 (60.81%) Public-4008: Instance 'adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[10].u_divider_step/quotient[15]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. + + Public-4008: Instance 'udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/ip_head_byte_num[0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/ip_head_byte_num[1]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. + Public-4008: Instance 'adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[11].u_divider_step/quotient[5]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. @@ -107529,6 +109286,9 @@ Total I/O ports = 180 of 296 (60.81%) Public-4008: Instance 'adjust_color_wrapper_inst/adjust_color_inst/convert_rgb2hsv_inst/divider_inst_s/g_sqrt_stepx[14].u_divider_step/quotient[15]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. + + Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum8[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'ms72xx_ctl/iic_dri_rx/fre_cnt[5]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. @@ -107751,36 +109511,6 @@ Total I/O ports = 180 of 296 (60.81%) Public-4008: Instance 'ms72xx_ctl/ms7210_ctl/addr[15]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - Public-4008: Instance 'udp_wr_mem_inst/mem[67]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[68]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[69]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[70]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[71]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[51]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[52]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[53]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[54]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[55]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'param_manager_inst/ms_cnt[17]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. @@ -107877,51 +109607,6 @@ Total I/O ports = 180 of 296 (60.81%) Public-4008: Instance 'param_manager_inst/key_debounce_key_left/cnt[23]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x2[8]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x2[9]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[24]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[25]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[26]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[27]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[28]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[29]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[30]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[31]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[83]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[84]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[85]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[86]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[87]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'param_manager_inst/key_debounce_key_restore/cnt[5]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. @@ -107979,9 +109664,6 @@ Total I/O ports = 180 of 296 (60.81%) Public-4008: Instance 'param_manager_inst/key_debounce_key_restore/cnt[23]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum8[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'param_manager_inst/key_debounce_key_right/cnt[5]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. @@ -108039,6 +109721,102 @@ Total I/O ports = 180 of 296 (60.81%) Public-4008: Instance 'param_manager_inst/key_debounce_key_right/cnt[23]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[8]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum1x4[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum1x4[1]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum1x4[7]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum1x4[8]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[3]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[4]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[5]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[6]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[7]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[11]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[12]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[13]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[14]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[15]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[26]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[27]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[28]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[29]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[30]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[31]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[51]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[52]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[53]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[54]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[55]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[67]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[68]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[69]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[70]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[71]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'param_manager_inst/param_filiter1_mode/key_debounce_inst1/cnt[5]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. @@ -108097,10 +109875,13 @@ Total I/O ports = 180 of 296 (60.81%) Public-4008: Instance 'param_manager_inst/param_filiter1_mode/key_debounce_inst1/cnt[23]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'image_filiter_inst/multiline_buffer_inst/ver_cnt[9]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x1[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'image_filiter_inst/multiline_buffer_inst/ver_cnt[10]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x1[7]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x1[8]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. Public-4008: Instance 'param_manager_inst/param_filiter1_mode/key_debounce_inst2/cnt[5]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. @@ -108160,58 +109941,73 @@ Total I/O ports = 180 of 296 (60.81%) Public-4008: Instance 'param_manager_inst/param_filiter1_mode/key_debounce_inst2/cnt[23]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'udp_wr_mem_inst/mem[193]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x2[7]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'udp_wr_mem_inst/mem[194]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x2[8]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'udp_wr_mem_inst/mem[195]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum8[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'udp_wr_mem_inst/mem[196]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'udp_wr_mem_inst/mem[197]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[24]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. - Public-4008: Instance 'udp_wr_mem_inst/mem[198]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[25]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. - Public-4008: Instance 'udp_wr_mem_inst/mem[199]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[26]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. - Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[27]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. - Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/product4x2[8]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[28]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. - Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum1x4[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[29]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. - Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum1x4[1]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[30]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. - Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum1x4[7]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'udp_osd_inst/eth_udp_inst/u_udp/u_udp_rx/des_ip[31]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. - Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum1x4[8]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x1[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[9]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x1[7]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum1x4[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x1[8]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum1x4[1]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x2[7]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum1x4[8]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum4x2[8]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum1x4[9]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x1[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x1[8]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x1[9]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x2[8]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x2[9]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/product4x2[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. @@ -108220,7 +110016,13 @@ Total I/O ports = 180 of 296 (60.81%) Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/product4x2[8]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_b/sum8[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum8[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'image_filiter_inst/multiline_buffer_inst/ver_cnt[9]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'image_filiter_inst/multiline_buffer_inst/ver_cnt[10]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum1x4[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. @@ -108252,105 +110054,6 @@ Total I/O ports = 180 of 296 (60.81%) Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_r/sum8[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - Public-4008: Instance 'udp_wr_mem_inst/mem[99]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[100]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[101]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[102]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[103]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[114]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[115]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[116]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[117]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[118]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[119]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[132]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[133]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[134]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[135]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[148]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[149]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[150]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[151]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[161]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[162]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[163]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[164]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[165]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[166]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[167]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[177]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[178]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[179]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[180]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[181]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[182]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_wr_mem_inst/mem[183]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'u_axi_ddr_top/rd0_ddr_sart_addr0[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. @@ -108529,11 +110232,26 @@ Total I/O ports = 180 of 296 (60.81%) Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/calib_mux/calib_ba[2]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. - Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum8[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x1[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x1[7]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x1[8]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_init/init_ba[2]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. + + Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x2[7]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x2[8]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum8[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_wrlvl/wrlvl_address[13]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. @@ -109869,9 +111587,6 @@ Total I/O ports = 180 of 296 (60.81%) Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_gate_update_ctrl/drift_dqs_group[1].ddrphy_drift_ctrl/ddrphy_update_comp_val[1]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. - - Public-4008: Instance 'udp_osd_inst/char_osd_inst/char_buf_reader_inst/row_cnt[5]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/rd_water_level[0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. @@ -109971,6 +111686,12 @@ Total I/O ports = 180 of 296 (60.81%) Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[5]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. + + Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x2[7]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x2[8]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/product4x2[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. @@ -109978,64 +111699,67 @@ Total I/O ports = 180 of 296 (60.81%) Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/product4x2[8]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x1[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x1[8]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/product4x2[9]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum4x1[9]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum1x4[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum1x4[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum1x4[1]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum1x4[1]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum1x4[8]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum1x4[7]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum1x4[9]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum1x4[8]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4[0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. - Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x1[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4[1]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. - Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x1[7]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4[2]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. - Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x1[8]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[3]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. - Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x2[7]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x1[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x2[8]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x1[8]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4[0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. + Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x1[9]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4[1]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. + Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[5]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. - Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4[2]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. + Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x2[8]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[3]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. + Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x2[9]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum8[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum8[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum1x4[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/product4x2[9]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum1x4[1]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[5]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. + Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum1x4[7]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum1x4[8]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_r4[0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. @@ -110050,19 +111774,16 @@ Total I/O ports = 180 of 296 (60.81%) Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/dqs_gate_coarse_cal/dqs_gate_pulse_src_nxt_r[3]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. - Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum1x4[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum1x4[1]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[5]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. - Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum1x4[8]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x1[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'image_filiter_inst2/hybrid_filter_inst/gaussian_conv_g/sum1x4[9]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x1[7]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/gate_state_reg[5]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. + Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_r/sum4x1[8]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/u_control_path_adj/phy_addr_r[0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. @@ -111544,13 +113265,10 @@ Total I/O ports = 180 of 296 (60.81%) Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_wdatapath/mcdq_wdp_align/wstrb_slip_dly[31]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. - Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x1[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x1[8]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x1[9]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[8]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. Public-4008: Instance 'u_axi_ddr_top/u_rdata3_fifo/U_ipml_fifo_rdata3_fifo/U_ipml_fifo_ctrl/wr_water_level[0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. @@ -111577,19 +113295,49 @@ Total I/O ports = 180 of 296 (60.81%) Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_calib_delay/calib_norm_cmd_m[5]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. - Public-4008: Instance 'udp_wr_mem_inst/mem[11]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'udp_wr_mem_inst/mem[132]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'udp_wr_mem_inst/mem[12]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'udp_wr_mem_inst/mem[133]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'udp_wr_mem_inst/mem[13]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'udp_wr_mem_inst/mem[134]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'udp_wr_mem_inst/mem[14]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'udp_wr_mem_inst/mem[135]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'udp_wr_mem_inst/mem[15]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'udp_wr_mem_inst/mem[148]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[149]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[150]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[151]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[193]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[194]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[195]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[196]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[197]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[198]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[199]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_out/norm_addr_m[10]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. @@ -111679,58 +113427,91 @@ Total I/O ports = 180 of 296 (60.81%) Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_buf/req_rdata[37]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. - Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x2[8]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum1x4[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum4x2[9]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum1x4[1]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'udp_wr_mem_inst/mem[26]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum1x4[7]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'udp_wr_mem_inst/mem[27]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum1x4[8]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'udp_wr_mem_inst/mem[28]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'udp_wr_mem_inst/mem[83]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'udp_wr_mem_inst/mem[29]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'udp_wr_mem_inst/mem[84]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'udp_wr_mem_inst/mem[30]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'udp_wr_mem_inst/mem[85]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'udp_wr_mem_inst/mem[31]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'udp_wr_mem_inst/mem[86]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'udp_wr_mem_inst/mem[3]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'udp_wr_mem_inst/mem[87]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'udp_wr_mem_inst/mem[4]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'udp_wr_mem_inst/mem[99]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'udp_wr_mem_inst/mem[5]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'udp_wr_mem_inst/mem[100]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'udp_wr_mem_inst/mem[6]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'udp_wr_mem_inst/mem[101]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'udp_wr_mem_inst/mem[7]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'udp_wr_mem_inst/mem[102]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[103]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[161]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[162]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[163]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[164]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[165]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[166]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[167]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/mcdq_prefetch_fifo/rd_data_ff1[4]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. - Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum1x4[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'udp_wr_mem_inst/mem[177]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum1x4[1]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'udp_wr_mem_inst/mem[178]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum1x4[8]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'udp_wr_mem_inst/mem[179]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_g/sum1x4[9]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'udp_wr_mem_inst/mem[180]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[181]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[182]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'udp_wr_mem_inst/mem[183]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_ui_axi/mcdq_reg_fifo2/data_0[1]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. @@ -111873,48 +113654,12 @@ Total I/O ports = 180 of 296 (60.81%) Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[6].trc_timing/timing_cnt[1]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. - - Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/product4x2[8]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[7].trc_timing/timing_cnt[0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRC_LOOP[7].trc_timing/timing_cnt[1]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. - - Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum1x4[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum1x4[1]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum1x4[7]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum1x4[8]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x1[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x1[7]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x1[8]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x2[7]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum4x2[8]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'image_filiter_inst/hybrid_filter_inst/gaussian_conv_b/sum8[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'u_axi_ddr_top/u_axi_rd_connect/rid_dout0[2]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. @@ -112527,6 +114272,12 @@ Total I/O ports = 180 of 296 (60.81%) Public-4008: Instance 'u_axi_ddr_top/u_axi_wr_connect/image_in_fifo3/U_ipml_fifo_image_in_fifo/U_ipml_fifo_ctrl/ASYN_CTRL.wptr[1]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. + + Public-4008: Instance 'u_ddr_addr_ctr/clk_cnt[20]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'u_ddr_addr_ctr/clk_cnt[21]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'u_ddr_addr_ctr/clk_cnt[22]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. @@ -112824,30 +114575,6 @@ Total I/O ports = 180 of 296 (60.81%) Public-4008: Instance 'u_ddr_addr_ctr/u_wr3_addr_ctr/wr_ddr_addr0[29]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - Public-4008: Instance 'udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[24]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[25]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[26]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[27]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[28]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[29]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[30]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/des_ip[31]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. - Public-4008: Instance 'u_ddr_addr_ctr/u_rd3_addr_ctr/gen_start_addr0[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. @@ -113230,13 +114957,7 @@ Total I/O ports = 180 of 296 (60.81%) Public-4008: Instance 'u_ddr_addr_ctr/u_wr0_addr_ctr/wr_ddr_addr0[29]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/ip_head_byte_num[0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_osd_inst/eth_udp_inst/u_icmp/u_icmp_rx/ip_head_byte_num[1]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'udp_osd_inst/char_osd_inst/char_pic_rom_inst/rom_addr_d[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'udp_osd_inst/char_osd_inst/char_buf_reader_inst/row_cnt[5]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. Public-4008: Instance 'u_ddr_addr_ctr/u_wr1_addr_ctr/wr_ddr_addr0[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. @@ -113313,12 +115034,6 @@ Total I/O ports = 180 of 296 (60.81%) Public-4008: Instance 'u_ddr_addr_ctr/u_wr1_addr_ctr/wr_ddr_addr0[29]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - Public-4008: Instance 'image_filiter_inst2/multiline_buffer_inst/ver_cnt[9]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'image_filiter_inst2/multiline_buffer_inst/ver_cnt[10]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Public-4008: Instance 'u_zoom_hdmi_fifo/U_ipml_fifo_zoom_hdmi_fifo/U_ipml_fifo_ctrl/wr_water_level[0]' of 'bmsWIDEDFFCPE' unit is dangling and will be cleaned. @@ -113499,6 +115214,12 @@ Total I/O ports = 180 of 296 (60.81%) Public-4008: Instance 'u_ov5640/u_mix_image/cnt1_h[10]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + Public-4008: Instance 'image_filiter_inst2/multiline_buffer_inst/ver_cnt[9]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + + + Public-4008: Instance 'image_filiter_inst2/multiline_buffer_inst/ver_cnt[10]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. + Public-4008: Instance 'u_rotate_image/image_h_add0[0]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. @@ -113520,18 +115241,6 @@ Total I/O ports = 180 of 296 (60.81%) Public-4008: Instance 'u_rotate_image/image_h_add0[6]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - Public-4008: Instance 'u_rotate_image/image_h_add1[11]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'u_rotate_image/image_h_add1[12]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'u_rotate_image/image_h_add1[13]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - - - Public-4008: Instance 'u_rotate_image/image_h_add1[14]' of 'bmsWIDEDFFRSE' unit is dangling and will be cleaned. - Removed GTP_DFF inst ms72xx_ctl/ms7210_ctl/state_reg[0] that is redundant to ms72xx_ctl/ms7200_ctl/state_reg[0] @@ -113722,196 +115431,196 @@ Total I/O ports = 180 of 296 (60.81%) Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[42] that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_dfi/phy_addr[41] - Removed GTP_DFF_E inst u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[0] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[4] that is stuck at constant 0. - Removed GTP_DFF_E inst u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[1] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt0[0] that is stuck at constant 0. - Removed GTP_DFF_E inst u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[2] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt0[5] that is stuck at constant 0. - Removed GTP_DFF_E inst u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[3] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[6] that is stuck at constant 0. - Removed GTP_DFF_E inst u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[4] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt2[4] that is stuck at constant 0. - Removed GTP_DFF_E inst u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[5] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt0[0] that is stuck at constant 0. - Removed GTP_DFF_E inst u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[6] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt0[5] that is stuck at constant 0. - Removed GTP_DFF_E inst u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[7] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[6] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[4] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[4] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[6] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/timing_cnt[5] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt0[0] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/timing_cnt[5] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt0[5] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/timing_cnt[5] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[6] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/timing_cnt[5] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt2[4] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[5] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[1] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/timing_cnt[5] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/timing_cnt1[5] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/timing_cnt[5] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt0[0] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/timing_cnt[5] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt0[5] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[6] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[6] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[6] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt2[4] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[6] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt0[0] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[6] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt0[5] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[6] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[6] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[6] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt2[4] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[6] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt0[0] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[6] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt0[5] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/main_state_reg[4] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[6] that is stuck at constant 0. + Removed GTP_DFF_E inst u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[0] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt2[4] that is stuck at constant 0. + Removed GTP_DFF_E inst u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[1] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt0[0] that is stuck at constant 0. + Removed GTP_DFF_E inst u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[2] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt0[5] that is stuck at constant 0. + Removed GTP_DFF_E inst u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[3] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[6] that is stuck at constant 0. + Removed GTP_DFF_E inst u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[4] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt2[4] that is stuck at constant 0. + Removed GTP_DFF_E inst u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[5] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt0[0] that is stuck at constant 0. + Removed GTP_DFF_E inst u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[6] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt0[5] that is stuck at constant 0. + Removed GTP_DFF_E inst u_ddr_addr_ctr/u_rd0_addr_ctr/rd_ddr_addr0[7] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[6] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[6] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt2[4] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt0[0] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt0[0] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt0[5] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt0[5] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[6] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[6] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt2[4] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt2[4] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_ref_pass/timing_cnt[1] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt0[0] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/timing_cnt1[5] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt0[5] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt0[0] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt1[6] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt0[5] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt2[4] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[6] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt0[0] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt2[4] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt0[5] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt0[0] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt1[6] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt0[5] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt2[4] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[6] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[0].trda2act_timing/timing_cnt[5] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt2[4] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[1].trda2act_timing/timing_cnt[5] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt0[0] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[2].trda2act_timing/timing_cnt[5] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt0[5] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[3].trda2act_timing/timing_cnt[5] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[6] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[4].trda2act_timing/timing_cnt[5] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt2[4] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[5].trda2act_timing/timing_cnt[5] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt0[0] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[6].trda2act_timing/timing_cnt[5] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt0[5] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TRDA2ACT_LOOP[7].trda2act_timing/timing_cnt[5] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[6] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[0].twra2act_timing/timing_cnt[6] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt2[4] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[1].twra2act_timing/timing_cnt[6] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt0[0] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[2].twra2act_timing/timing_cnt[6] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt0[5] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[3].twra2act_timing/timing_cnt[6] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[6] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[4].twra2act_timing/timing_cnt[6] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt2[4] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[5].twra2act_timing/timing_cnt[6] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt0[0] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[6].twra2act_timing/timing_cnt[6] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt0[5] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[6] that is stuck at constant 0. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[6] that is stuck at constant 0. Removed GTP_DFF inst u_axi_ddr_top/rd0_ddr_sart_addr0[2] that is stuck at constant 0. @@ -113961,6 +115670,9 @@ Total I/O ports = 180 of 296 (60.81%) Removed GTP_DFF inst u_axi_ddr_top/rd0_ddr_sart_addr1[9] that is stuck at constant 0. + + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/update_start that is stuck at constant 0. + Removed GTP_DFF_E inst u_axi_ddr_top/rd0_ddr_sart_addr2[2] that is stuck at constant 0. @@ -113985,9 +115697,6 @@ Total I/O ports = 180 of 296 (60.81%) Removed GTP_DFF_E inst u_axi_ddr_top/rd0_ddr_sart_addr2[9] that is stuck at constant 0. - - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/ddrphy_main_ctrl/update_start that is stuck at constant 0. - Removed GTP_DFF_E inst u_axi_ddr_top/s_axi_araddr[2] that is stuck at constant 0. @@ -115563,57 +117272,6 @@ Total I/O ports = 180 of 296 (60.81%) Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/upcal/upcal_wrdata_en[3]' of 'GTP_DFF_C' unit is dangling and will be cleaned. - - Removed GTP_DFF_P inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/upcal/upcal_state_reg[0] that is stuck at constant 1. - - - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[5] that is stuck at constant 0. - - - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt0[4] that is stuck at constant 0. - - - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[5] that is stuck at constant 0. - - - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/timing_cnt1[4] that is stuck at constant 0. - - - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt0[4] that is stuck at constant 0. - - - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[5] that is stuck at constant 0. - - - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt0[4] that is stuck at constant 0. - - - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[5] that is stuck at constant 0. - - - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt0[4] that is stuck at constant 0. - - - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[5] that is stuck at constant 0. - - - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt0[4] that is stuck at constant 0. - - - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[5] that is stuck at constant 0. - - - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt0[4] that is stuck at constant 0. - - - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[5] that is stuck at constant 0. - - - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt0[4] that is stuck at constant 0. - - - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[5] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt0[4] that is stuck at constant 0. @@ -115674,6 +117332,57 @@ Total I/O ports = 180 of 296 (60.81%) Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/TWRA2ACT_LOOP[7].twra2act_timing/timing_cnt[5] that is stuck at constant 0. + + Removed GTP_DFF_P inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/upcal/upcal_state_reg[0] that is stuck at constant 1. + + + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/mcdq_timing_rd_pass/timing_cnt1[5] that is stuck at constant 0. + + + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt0[4] that is stuck at constant 0. + + + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt1[5] that is stuck at constant 0. + + + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/timing_cnt1[4] that is stuck at constant 0. + + + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt0[4] that is stuck at constant 0. + + + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[0].timing_pre_pass/timing_cnt1[5] that is stuck at constant 0. + + + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt0[4] that is stuck at constant 0. + + + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[1].timing_pre_pass/timing_cnt1[5] that is stuck at constant 0. + + + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt0[4] that is stuck at constant 0. + + + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[2].timing_pre_pass/timing_cnt1[5] that is stuck at constant 0. + + + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt0[4] that is stuck at constant 0. + + + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[3].timing_pre_pass/timing_cnt1[5] that is stuck at constant 0. + + + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt0[4] that is stuck at constant 0. + + + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[4].timing_pre_pass/timing_cnt1[5] that is stuck at constant 0. + + + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt0[4] that is stuck at constant 0. + + + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt1[5] that is stuck at constant 0. + Removed GTP_DFF_CE inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/upcal/rdata_rem_vld that is stuck at constant 0. @@ -115806,12 +117515,6 @@ Total I/O ports = 180 of 296 (60.81%) Removed GTP_DFF_CE inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_gate_update_ctrl/drift_dqs_group[3].ddrphy_drift_ctrl/dqs_drift_last_samp[1] that is stuck at constant 0. - - Removed GTP_DFF_CE inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_gate_update_ctrl/drift_dqs_group[0].ddrphy_drift_ctrl/dqs_drift_last[0] that is stuck at constant 0. - - - Removed GTP_DFF_CE inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_gate_update_ctrl/drift_dqs_group[0].ddrphy_drift_ctrl/dqs_drift_last[1] that is stuck at constant 0. - Removed GTP_DFF_CE inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_gate_update_ctrl/drift_dqs_group[0].ddrphy_drift_ctrl/dqs_drift_last_cnt[1] that is stuck at constant 0. @@ -115839,6 +117542,12 @@ Total I/O ports = 180 of 296 (60.81%) Removed GTP_DFF_CE inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_gate_update_ctrl/drift_dqs_group[0].ddrphy_drift_ctrl/dqs_drift_last_cnt[9] that is stuck at constant 0. + + Removed GTP_DFF_CE inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_gate_update_ctrl/drift_dqs_group[0].ddrphy_drift_ctrl/dqs_drift_last[0] that is stuck at constant 0. + + + Removed GTP_DFF_CE inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_gate_update_ctrl/drift_dqs_group[0].ddrphy_drift_ctrl/dqs_drift_last[1] that is stuck at constant 0. + Removed GTP_DFF_CE inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_gate_update_ctrl/drift_dqs_group[1].ddrphy_drift_ctrl/dqs_drift_last[0] that is stuck at constant 0. @@ -115938,15 +117647,15 @@ Total I/O ports = 180 of 296 (60.81%) Removed GTP_DFF_CE inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_gate_update_ctrl/drift_dqs_group[3].ddrphy_drift_ctrl/dqs_drift_last[1] that is stuck at constant 0. - - Removed GTP_DFF_CE inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_gate_update_ctrl/drift_dqs_group[0].ddrphy_drift_ctrl/ddrphy_update_comp_val[0] that is stuck at constant 0. - Removed GTP_DFF_CE inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_gate_update_ctrl/drift_dqs_group[0].ddrphy_drift_ctrl/dqs_drift_last_cnt[0] that is stuck at constant 0. Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_gate_update_ctrl/drift_dqs_group[0].ddrphy_drift_ctrl/dqs_drift_last_done that is stuck at constant 0. + + Removed GTP_DFF_CE inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_gate_update_ctrl/drift_dqs_group[0].ddrphy_drift_ctrl/ddrphy_update_comp_val[0] that is stuck at constant 0. + Removed GTP_DFF_CE inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_gate_update_ctrl/drift_dqs_group[1].ddrphy_drift_ctrl/ddrphy_update_comp_val[0] that is stuck at constant 0. @@ -116053,14 +117762,11 @@ Total I/O ports = 180 of 296 (60.81%) Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/upcal/upcal_state_reg[4] that is stuck at constant 0. - Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/date_valid_cnt[1]' of 'GTP_DFF_C' unit is dangling and will be cleaned. + Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/date_valid_cnt[2]' of 'GTP_DFF_C' unit is dangling and will be cleaned. Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/date_valid_cnt[0]' of 'GTP_DFF_C' unit is dangling and will be cleaned. - - Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/date_valid_cnt[2]' of 'GTP_DFF_C' unit is dangling and will be cleaned. - Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/upcal/dqs_gate_check_falling_d' of 'GTP_DFF_C' unit is dangling and will be cleaned. @@ -116070,6 +117776,9 @@ Total I/O ports = 180 of 296 (60.81%) Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_gate_update_ctrl/drift_dqs_group[0].ddrphy_drift_ctrl/update_comp' of 'GTP_DFF_CE' unit is dangling and will be cleaned. + + Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/upcal/upcal_state_reg[1]' of 'GTP_DFF_C' unit is dangling and will be cleaned. + Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_update1_valid' of 'GTP_DFF_CE' unit is dangling and will be cleaned. @@ -116082,18 +117791,33 @@ Total I/O ports = 180 of 296 (60.81%) Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/rdvalid_r2' of 'GTP_DFF_C' unit is dangling and will be cleaned. + + Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/upcal/upcal_state_reg[2]' of 'GTP_DFF_C' unit is dangling and will be cleaned. + + + Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/upcal/upcal_state_reg[3]' of 'GTP_DFF_C' unit is dangling and will be cleaned. + Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_update1_valid' of 'GTP_DFF_CE' unit is dangling and will be cleaned. Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_update2_valid' of 'GTP_DFF_CE' unit is dangling and will be cleaned. + + Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/upcal/upcal_state_reg[5]' of 'GTP_DFF_C' unit is dangling and will be cleaned. + Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/data_check_pass' of 'GTP_DFF_CE' unit is dangling and will be cleaned. Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/rdvalid_r2' of 'GTP_DFF_C' unit is dangling and will be cleaned. + + Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/date_valid_cnt[0]' of 'GTP_DFF_C' unit is dangling and will be cleaned. + + + Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/date_valid_cnt[1]' of 'GTP_DFF_C' unit is dangling and will be cleaned. + Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_update1_valid' of 'GTP_DFF_CE' unit is dangling and will be cleaned. @@ -116101,7 +117825,7 @@ Total I/O ports = 180 of 296 (60.81%) Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_update2_valid' of 'GTP_DFF_CE' unit is dangling and will be cleaned. - Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/upcal/upcal_state_reg[1]' of 'GTP_DFF_C' unit is dangling and will be cleaned. + Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/date_valid_cnt[2]' of 'GTP_DFF_C' unit is dangling and will be cleaned. Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/data_check_pass' of 'GTP_DFF_CE' unit is dangling and will be cleaned. @@ -116109,6 +117833,12 @@ Total I/O ports = 180 of 296 (60.81%) Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/rdvalid_r2' of 'GTP_DFF_C' unit is dangling and will be cleaned. + + Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/upcal/upcal_state_reg[6]' of 'GTP_DFF_C' unit is dangling and will be cleaned. + + + Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/upcal/upcal_state_reg[7]' of 'GTP_DFF_C' unit is dangling and will be cleaned. + Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/data_slice_dqs_gate_cal/gatecal/dqs_gate_update1_valid' of 'GTP_DFF_CE' unit is dangling and will be cleaned. @@ -116122,19 +117852,25 @@ Total I/O ports = 180 of 296 (60.81%) Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/rdvalid_r2' of 'GTP_DFF_C' unit is dangling and will be cleaned. - Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/upcal/upcal_state_reg[3]' of 'GTP_DFF_C' unit is dangling and will be cleaned. + Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/upcal/upcal_state_reg[9]' of 'GTP_DFF_C' unit is dangling and will be cleaned. - Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/upcal/upcal_state_reg[2]' of 'GTP_DFF_C' unit is dangling and will be cleaned. + Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[3].u_ddrphy_data_slice/dqs_rddata_align/date_valid_cnt[1]' of 'GTP_DFF_C' unit is dangling and will be cleaned. - Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/date_valid_cnt[0]' of 'GTP_DFF_C' unit is dangling and will be cleaned. + Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/upcal/upcal_state_reg[8]' of 'GTP_DFF_C' unit is dangling and will be cleaned. - Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/date_valid_cnt[1]' of 'GTP_DFF_C' unit is dangling and will be cleaned. + Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/upcal/upcal_state_reg[10]' of 'GTP_DFF_C' unit is dangling and will be cleaned. - Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/date_valid_cnt[2]' of 'GTP_DFF_C' unit is dangling and will be cleaned. + Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/date_valid_cnt[0]' of 'GTP_DFF_C' unit is dangling and will be cleaned. + + + Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/date_valid_cnt[1]' of 'GTP_DFF_C' unit is dangling and will be cleaned. + + + Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/date_valid_cnt[2]' of 'GTP_DFF_C' unit is dangling and will be cleaned. Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_gate_update_ctrl/drift_dqs_group[0].ddrphy_drift_ctrl/dqs_drift_d1[0]' of 'GTP_DFF_CE' unit is dangling and will be cleaned. @@ -116154,24 +117890,6 @@ Total I/O ports = 180 of 296 (60.81%) Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_gate_update_ctrl/drift_dqs_group[0].ddrphy_drift_ctrl/dqs_drift_now[1]' of 'GTP_DFF_CE' unit is dangling and will be cleaned. - - Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/date_valid_cnt[0]' of 'GTP_DFF_C' unit is dangling and will be cleaned. - - - Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/date_valid_cnt[1]' of 'GTP_DFF_C' unit is dangling and will be cleaned. - - - Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/date_valid_cnt[2]' of 'GTP_DFF_C' unit is dangling and will be cleaned. - - - Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/date_valid_cnt[0]' of 'GTP_DFF_C' unit is dangling and will be cleaned. - - - Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/date_valid_cnt[1]' of 'GTP_DFF_C' unit is dangling and will be cleaned. - - - Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[1].u_ddrphy_data_slice/dqs_rddata_align/date_valid_cnt[2]' of 'GTP_DFF_C' unit is dangling and will be cleaned. - Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_gate_update_ctrl/drift_dqs_group[1].ddrphy_drift_ctrl/dqs_drift_d1[0]' of 'GTP_DFF_CE' unit is dangling and will be cleaned. @@ -116190,12 +117908,6 @@ Total I/O ports = 180 of 296 (60.81%) Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_gate_update_ctrl/drift_dqs_group[1].ddrphy_drift_ctrl/dqs_drift_now[1]' of 'GTP_DFF_CE' unit is dangling and will be cleaned. - - Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/upcal/upcal_state_reg[5]' of 'GTP_DFF_C' unit is dangling and will be cleaned. - - - Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/upcal/upcal_state_reg[6]' of 'GTP_DFF_C' unit is dangling and will be cleaned. - Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_gate_update_ctrl/drift_dqs_group[3].ddrphy_drift_ctrl/dqs_drift_now[0]' of 'GTP_DFF_CE' unit is dangling and will be cleaned. @@ -116233,16 +117945,19 @@ Total I/O ports = 180 of 296 (60.81%) Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_gate_update_ctrl/drift_dqs_group[3].ddrphy_drift_ctrl/dqs_drift_d2[1]' of 'GTP_DFF_CE' unit is dangling and will be cleaned. - Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/upcal/upcal_state_reg[7]' of 'GTP_DFF_C' unit is dangling and will be cleaned. + Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/date_valid_cnt[0]' of 'GTP_DFF_C' unit is dangling and will be cleaned. - Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/upcal/upcal_state_reg[8]' of 'GTP_DFF_C' unit is dangling and will be cleaned. + Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/date_valid_cnt[1]' of 'GTP_DFF_C' unit is dangling and will be cleaned. - Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/upcal/upcal_state_reg[9]' of 'GTP_DFF_C' unit is dangling and will be cleaned. + Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[2].u_ddrphy_data_slice/dqs_rddata_align/date_valid_cnt[2]' of 'GTP_DFF_C' unit is dangling and will be cleaned. - Public-4008: Instance 'u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_calib_top/upcal/upcal_state_reg[10]' of 'GTP_DFF_C' unit is dangling and will be cleaned. + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt0[3] that is stuck at constant 0. + + + Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt0[3] that is stuck at constant 0. Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqs_rddata_align/gdet_state_reg[5] that is stuck at constant 0. @@ -116283,35 +117998,29 @@ Total I/O ports = 180 of 296 (60.81%) Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[5].timing_pre_pass/timing_cnt0[3] that is stuck at constant 0. - - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[6].timing_pre_pass/timing_cnt0[3] that is stuck at constant 0. - - - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/PRE_PASS_LOOP[7].timing_pre_pass/timing_cnt0[3] that is stuck at constant 0. - Removed GTP_DFF_C inst u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_wr_pass/timing_cnt1[2] that is redundant to u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_dcp_top/mcdq_dcp_back_ctrl/timing_prea_pass/timing_cnt0[2] - Public-4008: Instance 'u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[1]' of 'GTP_DFF_C' unit is dangling and will be cleaned. + Public-4008: Instance 'u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[0]' of 'GTP_DFF_C' unit is dangling and will be cleaned. - Public-4008: Instance 'u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[0]' of 'GTP_DFF_C' unit is dangling and will be cleaned. + Public-4008: Instance 'u_axi_ddr_top/u_wr_ddr_fifo/U_ipml_fifo_wr_ddr_fifo/U_ipml_fifo_ctrl/wr_water_level[1]' of 'GTP_DFF_C' unit is dangling and will be cleaned. Unable to honor max fanout constraint for gtp_inv driven net u_axi_ddr_top/u_axi_rd_connect/N78_1 - Unable to honor max fanout constraint for gtp_inv driven net N139_0 + Unable to honor max fanout constraint for gtp_inv driven net N242_0 - Unable to honor max fanout constraint for gtp_inv driven net N241_0 + Unable to honor max fanout constraint for gtp_inv driven net N139_0 - Unable to honor max fanout constraint for gtp_inv driven net N241_0 + Unable to honor max fanout constraint for gtp_inv driven net N139_0 - Unable to honor max fanout constraint for gtp_inv driven net N139_0 + Unable to honor max fanout constraint for gtp_inv driven net N242_0 Unable to honor max fanout constraint for gtp_inv driven net u_axi_ddr_top/u_axi_rd_connect/N78_1 @@ -116335,226 +118044,208 @@ Total I/O ports = 180 of 296 (60.81%) Unable to honor max fanout constraint for gtp_inv driven net N269_1 - syn_maxfan of lutcarry N86_1_10 is more than 10000 on net N301[10], but wasn't replicated. - - - syn_maxfan of lutcarry N86_1_9 is more than 10000 on net N301[9], but wasn't replicated. - - - syn_maxfan of lutcarry N86_1_8 is more than 10000 on net N301[8], but wasn't replicated. - - - syn_maxfan of lutcarry N86_1_7 is more than 10000 on net N301[7], but wasn't replicated. - - - syn_maxfan of lutcarry N86_1_6 is more than 10000 on net N301[6], but wasn't replicated. - - - syn_maxfan of lutcarry N86_1_5 is more than 10000 on net N301[5], but wasn't replicated. - - - syn_maxfan of lutcarry N86_1_4 is more than 10000 on net N301[4], but wasn't replicated. + Unable to honor max fanout constraint for gtp_inv driven net N313_2 - syn_maxfan of lutcarry N86_1_3 is more than 10000 on net N301[3], but wasn't replicated. + Unable to honor max fanout constraint for gtp_inv driven net N313_2 - syn_maxfan of lutcarry N86_1_2 is more than 10000 on net N301[2], but wasn't replicated. + Unable to honor max fanout constraint for gtp_inv driven net N599_1 - syn_maxfan of lutcarry N86_1_1 is more than 10000 on net N301[1], but wasn't replicated. + Unable to honor max fanout constraint for gtp_inv driven net N439_1 - syn_maxfan of lutcarry N80_1_10 is more than 10000 on net N290[10], but wasn't replicated. + Unable to honor max fanout constraint for gtp_inv driven net N138_1 - syn_maxfan of lutcarry N80_1_9 is more than 10000 on net N290[9], but wasn't replicated. + Unable to honor max fanout constraint for gtp_inv driven net N120_1 - syn_maxfan of lutcarry N80_1_8 is more than 10000 on net N290[8], but wasn't replicated. + Unable to honor max fanout constraint for gtp_inv driven net N599_1 - syn_maxfan of lutcarry N80_1_7 is more than 10000 on net N290[7], but wasn't replicated. + Unable to honor max fanout constraint for gtp_inv driven net N439_1 - syn_maxfan of lutcarry N80_1_6 is more than 10000 on net N290[6], but wasn't replicated. + Unable to honor max fanout constraint for gtp_inv driven net N138_1 - syn_maxfan of lutcarry N80_1_5 is more than 10000 on net N290[5], but wasn't replicated. + Unable to honor max fanout constraint for gtp_inv driven net N120_1 - syn_maxfan of lutcarry N80_1_4 is more than 10000 on net N290[4], but wasn't replicated. + Unable to honor max fanout constraint for gtp_inv driven net N17 - syn_maxfan of lutcarry N80_1_3 is more than 10000 on net N290[3], but wasn't replicated. + Unable to honor max fanout constraint for gtp_inv driven net N17 - syn_maxfan of lutcarry N80_1_2 is more than 10000 on net N290[2], but wasn't replicated. + Unable to honor max fanout constraint for gtp_inv driven net N0_1 - syn_maxfan of lutcarry N80_1_1 is more than 10000 on net N290[1], but wasn't replicated. + Unable to honor max fanout constraint for gtp_inv driven net N0_1 - Unable to honor max fanout constraint for gtp_inv driven net N339_2 + Unable to honor max fanout constraint for gtp_inv driven net N0_1 - Unable to honor max fanout constraint for gtp_inv driven net N164_1 + Unable to honor max fanout constraint for gtp_inv driven net N0_1 - syn_maxfan of lutcarry N86_1_10 is more than 10000 on net N301[10], but wasn't replicated. + Unable to honor max fanout constraint for gtp_inv driven net N3_1 - syn_maxfan of lutcarry N86_1_9 is more than 10000 on net N301[9], but wasn't replicated. + Unable to honor max fanout constraint for gtp_inv driven net u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/data_in_ready_1 - syn_maxfan of lutcarry N86_1_8 is more than 10000 on net N301[8], but wasn't replicated. + Unable to honor max fanout constraint for gtp_inv driven net N3_1 - syn_maxfan of lutcarry N86_1_7 is more than 10000 on net N301[7], but wasn't replicated. + Unable to honor max fanout constraint for gtp_inv driven net u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/data_in_ready_1 - syn_maxfan of lutcarry N86_1_6 is more than 10000 on net N301[6], but wasn't replicated. + Unable to honor max fanout constraint for gtp_inv driven net N0_1 - syn_maxfan of lutcarry N86_1_5 is more than 10000 on net N301[5], but wasn't replicated. + Unable to honor max fanout constraint for gtp_inv driven net N0_1 - syn_maxfan of lutcarry N86_1_4 is more than 10000 on net N301[4], but wasn't replicated. + Unable to honor max fanout constraint for gtp_inv driven net N13_1 - syn_maxfan of lutcarry N86_1_3 is more than 10000 on net N301[3], but wasn't replicated. + Unable to honor max fanout constraint for gtp_inv driven net N13_1 - syn_maxfan of lutcarry N86_1_2 is more than 10000 on net N301[2], but wasn't replicated. + syn_maxfan of lutcarry N86_1_10 is more than 10000 on net N349[10], but wasn't replicated. - syn_maxfan of lutcarry N86_1_1 is more than 10000 on net N301[1], but wasn't replicated. + syn_maxfan of lutcarry N86_1_9 is more than 10000 on net N349[9], but wasn't replicated. - syn_maxfan of lutcarry N80_1_10 is more than 10000 on net N290[10], but wasn't replicated. + syn_maxfan of lutcarry N86_1_8 is more than 10000 on net N349[8], but wasn't replicated. - syn_maxfan of lutcarry N80_1_9 is more than 10000 on net N290[9], but wasn't replicated. + syn_maxfan of lutcarry N86_1_7 is more than 10000 on net N349[7], but wasn't replicated. - syn_maxfan of lutcarry N80_1_8 is more than 10000 on net N290[8], but wasn't replicated. + syn_maxfan of lutcarry N86_1_6 is more than 10000 on net N349[6], but wasn't replicated. - syn_maxfan of lutcarry N80_1_7 is more than 10000 on net N290[7], but wasn't replicated. + syn_maxfan of lutcarry N86_1_5 is more than 10000 on net N349[5], but wasn't replicated. - syn_maxfan of lutcarry N80_1_6 is more than 10000 on net N290[6], but wasn't replicated. + syn_maxfan of lutcarry N86_1_4 is more than 10000 on net N349[4], but wasn't replicated. - syn_maxfan of lutcarry N80_1_5 is more than 10000 on net N290[5], but wasn't replicated. + syn_maxfan of lutcarry N86_1_3 is more than 10000 on net N349[3], but wasn't replicated. - syn_maxfan of lutcarry N80_1_4 is more than 10000 on net N290[4], but wasn't replicated. + syn_maxfan of lutcarry N86_1_2 is more than 10000 on net N349[2], but wasn't replicated. - syn_maxfan of lutcarry N80_1_3 is more than 10000 on net N290[3], but wasn't replicated. + syn_maxfan of lutcarry N86_1_1 is more than 10000 on net N349[1], but wasn't replicated. - syn_maxfan of lutcarry N80_1_2 is more than 10000 on net N290[2], but wasn't replicated. + syn_maxfan of lutcarry N80_1_10 is more than 10000 on net N338[10], but wasn't replicated. - syn_maxfan of lutcarry N80_1_1 is more than 10000 on net N290[1], but wasn't replicated. + syn_maxfan of lutcarry N80_1_9 is more than 10000 on net N338[9], but wasn't replicated. - Unable to honor max fanout constraint for gtp_inv driven net N339_2 + syn_maxfan of lutcarry N80_1_8 is more than 10000 on net N338[8], but wasn't replicated. - Unable to honor max fanout constraint for gtp_inv driven net N164_1 + syn_maxfan of lutcarry N80_1_7 is more than 10000 on net N338[7], but wasn't replicated. - syn_maxfan of lutcarry N29.eq_5 is more than 10000 on net N29, but wasn't replicated. + syn_maxfan of lutcarry N80_1_6 is more than 10000 on net N338[6], but wasn't replicated. - syn_maxfan of lutcarry N26.lt_5 is more than 10000 on net N26, but wasn't replicated. + syn_maxfan of lutcarry N80_1_5 is more than 10000 on net N338[5], but wasn't replicated. - syn_maxfan of lutcarry N29.eq_5 is more than 10000 on net N29, but wasn't replicated. + syn_maxfan of lutcarry N80_1_4 is more than 10000 on net N338[4], but wasn't replicated. - syn_maxfan of lutcarry N26.lt_5 is more than 10000 on net N26, but wasn't replicated. + syn_maxfan of lutcarry N80_1_3 is more than 10000 on net N338[3], but wasn't replicated. - Unable to honor max fanout constraint for gtp_inv driven net N104_1 + syn_maxfan of lutcarry N80_1_2 is more than 10000 on net N338[2], but wasn't replicated. - Unable to honor max fanout constraint for gtp_inv driven net N104_1 + syn_maxfan of lutcarry N80_1_1 is more than 10000 on net N338[1], but wasn't replicated. - Unable to honor max fanout constraint for gtp_inv driven net N599_1 + Unable to honor max fanout constraint for gtp_inv driven net N395_2 - Unable to honor max fanout constraint for gtp_inv driven net N439_1 + Unable to honor max fanout constraint for gtp_inv driven net N164_1 - Unable to honor max fanout constraint for gtp_inv driven net N138_1 + syn_maxfan of lutcarry N86_1_10 is more than 10000 on net N349[10], but wasn't replicated. - Unable to honor max fanout constraint for gtp_inv driven net N120_1 + syn_maxfan of lutcarry N86_1_9 is more than 10000 on net N349[9], but wasn't replicated. - Unable to honor max fanout constraint for gtp_inv driven net N599_1 + syn_maxfan of lutcarry N86_1_8 is more than 10000 on net N349[8], but wasn't replicated. - Unable to honor max fanout constraint for gtp_inv driven net N439_1 + syn_maxfan of lutcarry N86_1_7 is more than 10000 on net N349[7], but wasn't replicated. - Unable to honor max fanout constraint for gtp_inv driven net N138_1 + syn_maxfan of lutcarry N86_1_6 is more than 10000 on net N349[6], but wasn't replicated. - Unable to honor max fanout constraint for gtp_inv driven net N120_1 + syn_maxfan of lutcarry N86_1_5 is more than 10000 on net N349[5], but wasn't replicated. - Unable to honor max fanout constraint for gtp_inv driven net N17 + syn_maxfan of lutcarry N86_1_4 is more than 10000 on net N349[4], but wasn't replicated. - Unable to honor max fanout constraint for gtp_inv driven net N17 + syn_maxfan of lutcarry N86_1_3 is more than 10000 on net N349[3], but wasn't replicated. - Unable to honor max fanout constraint for gtp_inv driven net N0_1 + syn_maxfan of lutcarry N86_1_2 is more than 10000 on net N349[2], but wasn't replicated. - Unable to honor max fanout constraint for gtp_inv driven net N0_1 + syn_maxfan of lutcarry N86_1_1 is more than 10000 on net N349[1], but wasn't replicated. - Unable to honor max fanout constraint for gtp_inv driven net N0_1 + syn_maxfan of lutcarry N80_1_10 is more than 10000 on net N338[10], but wasn't replicated. - Unable to honor max fanout constraint for gtp_inv driven net N0_1 + syn_maxfan of lutcarry N80_1_9 is more than 10000 on net N338[9], but wasn't replicated. - Unable to honor max fanout constraint for gtp_inv driven net N3_1 + syn_maxfan of lutcarry N80_1_8 is more than 10000 on net N338[8], but wasn't replicated. - Unable to honor max fanout constraint for gtp_inv driven net u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/data_in_ready_1 + syn_maxfan of lutcarry N80_1_7 is more than 10000 on net N338[7], but wasn't replicated. - Unable to honor max fanout constraint for gtp_inv driven net N3_1 + syn_maxfan of lutcarry N80_1_6 is more than 10000 on net N338[6], but wasn't replicated. - Unable to honor max fanout constraint for gtp_inv driven net u_axi_ddr_top/I_ipsxb_ddr_top/u_ipsxb_ddrc_top/mcdq_rdatapath/data_in_ready_1 + syn_maxfan of lutcarry N80_1_5 is more than 10000 on net N338[5], but wasn't replicated. - Unable to honor max fanout constraint for gtp_inv driven net N0_1 + syn_maxfan of lutcarry N80_1_4 is more than 10000 on net N338[4], but wasn't replicated. - Unable to honor max fanout constraint for gtp_inv driven net N0_1 + syn_maxfan of lutcarry N80_1_3 is more than 10000 on net N338[3], but wasn't replicated. - Unable to honor max fanout constraint for gtp_inv driven net N13_1 + syn_maxfan of lutcarry N80_1_2 is more than 10000 on net N338[2], but wasn't replicated. - Unable to honor max fanout constraint for gtp_inv driven net N13_1 + syn_maxfan of lutcarry N80_1_1 is more than 10000 on net N338[1], but wasn't replicated. - Unable to honor max fanout constraint for gtp_inv driven net N313_2 + Unable to honor max fanout constraint for gtp_inv driven net N395_2 - Unable to honor max fanout constraint for gtp_inv driven net N313_2 + Unable to honor max fanout constraint for gtp_inv driven net N164_1 syn_maxfan of lutcarry N566_1.fsub_7 is more than 10000 on net N953[7], but wasn't replicated. @@ -116748,6 +118439,24 @@ Total I/O ports = 180 of 296 (60.81%) syn_maxfan of lutcarry N85_1_3 is more than 10000 on net N849[3], but wasn't replicated. + + syn_maxfan of lutcarry N29.eq_5 is more than 10000 on net N29, but wasn't replicated. + + + syn_maxfan of lutcarry N26.lt_5 is more than 10000 on net N26, but wasn't replicated. + + + syn_maxfan of lutcarry N29.eq_5 is more than 10000 on net N29, but wasn't replicated. + + + syn_maxfan of lutcarry N26.lt_5 is more than 10000 on net N26, but wasn't replicated. + + + Unable to honor max fanout constraint for gtp_inv driven net N104_1 + + + Unable to honor max fanout constraint for gtp_inv driven net N104_1 + prevent name conflict by renaming net ms72xx_ctl/sda_out to ms72xx_ctl/sda_out_rnmt @@ -116760,9 +118469,6 @@ Total I/O ports = 180 of 296 (60.81%) prevent name conflict by renaming net ms72xx_ctl/iic_dri_tx/N80 to ms72xx_ctl/iic_dri_tx/N80_rnmt - - prevent name conflict by renaming net u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N137 to u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_reset_ctrl/N137_rnmt - prevent name conflict by renaming net u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N538 to u_axi_ddr_top/I_ipsxb_ddr_top/u_ddrphy_top/ddrphy_slice_top/i_dqs_group[0].u_ddrphy_data_slice/dqsi_rdel_cal/_N538_rnmt @@ -117471,9 +119177,6 @@ Total I/O ports = 180 of 296 (60.81%) STA-3009: The clock clk_100m is not connected to any clock endpoints,it will be treated as a normal port or pin. - - STA-3009: The clock clk_1080p60Hz is not connected to any clock endpoints,it will be treated as a normal port or pin. - Timing-4086: Port 'cmos1_scl' is not constrained, it is treated as combinational input. diff --git a/sources/designs/adjust_color/adjust_color.v b/sources/designs/adjust_color/adjust_color.v index e1ba727..2fc5d6c 100644 --- a/sources/designs/adjust_color/adjust_color.v +++ b/sources/designs/adjust_color/adjust_color.v @@ -1,18 +1,18 @@ // 数据处理需要 20+2+4=26个周期 module adjust_color ( - input clk, - input resetn, + input clk, //! 时钟 + input resetn, //! 复位 - input signed [8:0] h_s_data, - input signed [8:0] s_s_data, - input signed [8:0] v_s_data, + input signed [8:0] h_s_data, //! 色相调整值 + input signed [8:0] s_s_data, //! 饱和度调整值 + input signed [8:0] v_s_data, //! 明度调整值 - input [23:0] pixel_s_data, - input pixel_s_valid, + input [23:0] pixel_s_data, //! 输入像素点-RGB + input pixel_s_valid, //! 输入有效信号 - output [23:0] res_m_data, - output res_m_valid + output [23:0] res_m_data, //! 输出像素点 + output res_m_valid //! 输出有效信号 ); wire [7:0] raw_h_data; diff --git a/sources/designs/ddr/addr_ctrl/ddr_addr_ctr.v b/sources/designs/ddr/addr_ctrl/ddr_addr_ctr.v index cc2911f..e936484 100644 --- a/sources/designs/ddr/addr_ctrl/ddr_addr_ctr.v +++ b/sources/designs/ddr/addr_ctrl/ddr_addr_ctr.v @@ -85,7 +85,7 @@ module ddr_addr_ctr #( input init_calib_complete ); localparam CLK_FRE_NUM = 100_000_000; - localparam CLK_CNT_NUM = CLK_FRE_NUM / 32; + localparam CLK_CNT_NUM = CLK_FRE_NUM / 120; diff --git a/sources/designs/hdmi/hdmi_in/hdmi_in_top.v b/sources/designs/hdmi/hdmi_in/hdmi_in_top.v index 78237b3..46cac9e 100644 --- a/sources/designs/hdmi/hdmi_in/hdmi_in_top.v +++ b/sources/designs/hdmi/hdmi_in/hdmi_in_top.v @@ -25,19 +25,19 @@ module hdmi_in_top #( parameter IMAGE_H = 720, parameter IMAGE_SIZE = 11 ) ( - input clk, - input rst, + input clk, //! 时钟 + input rst, //! 复位 - input [7:0] r_in, - input [7:0] g_in, - input [7:0] b_in, - input vs_in, - input hs_in, - input de_in, + input [7:0] r_in, //! 像素点Red通道 + input [7:0] g_in, //! 像素点Green通道 + input [7:0] b_in, //! 像素点Blue通道 + input vs_in, //! 垂直同步信号 + input hs_in, //! 水平同步信号 + input de_in, //! 数据有效信号 - output [15:0] hdmi_data, - output hdmi_data_valid, - output hdmi_vs_out + output [15:0] hdmi_data, //! HDMI输出数据 + output hdmi_data_valid, //! HDMI输出有效信号 + output hdmi_vs_out //! HDMI输出输出垂直同步 ); //localparam EXTRACT = 2 ; diff --git a/sources/designs/hdmi/hdmi_out/sync_vg.v b/sources/designs/hdmi/hdmi_out/sync_vg.v index 99a6ed1..54a7cc8 100644 --- a/sources/designs/hdmi/hdmi_out/sync_vg.v +++ b/sources/designs/hdmi/hdmi_out/sync_vg.v @@ -64,18 +64,20 @@ module sync_vg #( parameter HV_OFFSET = 12'd0 ) ( - input clk, - input rst, - output vs_out, - output hs_out, - output de_re, - output ddr_rd_en, - - input [1:0] rd_mode, - input [15:0] ddr_image_data, - output [15:0] hdmi_image_data, - output reg [11:0] pos_x, - output reg [11:0] pos_y + input clk, //!时钟 + input rst, //!复位 + + + input [1:0] rd_mode, //! 读取模式 + output ddr_rd_en, //! 读取请求 + input [15:0] ddr_image_data, //! 读取数据 + + output vs_out, //!垂直同步 + output hs_out, //!水平同步 + output de_re, //!数据有效 + output [15:0] hdmi_image_data, //! 输出像素点RGB数据 + output reg [11:0] pos_x, //! 像素点对应的X坐标 + output reg [11:0] pos_y //! 像素点对应的Y坐标 ); reg [X_BITS-1:0] h_count; diff --git a/sources/designs/image_filiter/image_filiter.v b/sources/designs/image_filiter/image_filiter.v index ffcfba5..c3adec3 100644 --- a/sources/designs/image_filiter/image_filiter.v +++ b/sources/designs/image_filiter/image_filiter.v @@ -7,19 +7,19 @@ module image_filiter #( parameter integer B_DATA_WIDTH = 5, parameter integer TH = 5 ) ( - input clk, - input resetn, + input clk, //! 时钟 + input resetn, //! 复位 //! FIFO初始化忙信号 output rst_busy, //! 滤波模式 0:不做处理 1:高斯滤波 2:中值滤波 3:自适应滤波 - input [ 2:0] mode, - //! 输入像素点 - input [PIXEL_DATA_WIDTH-1:0] s_pixel_data, - input s_pixel_valid, - //! 输出像素点 - output [PIXEL_DATA_WIDTH-1:0] m_filtered_data, - output m_filtered_valid + input [2:0] mode, //! 滤波模式 + + input [PIXEL_DATA_WIDTH-1:0] s_pixel_data, //! 输入像素点 + input s_pixel_valid, //! 输入像素点有效信号 + + output [PIXEL_DATA_WIDTH-1:0] m_filtered_data, //! 输出像素点 + output m_filtered_valid //! 输出像素点有效信号 ); wire [3*PIXEL_DATA_WIDTH-1:0] multiline_pixel_data; diff --git a/sources/designs/image_filiter/multiline_buffer.v b/sources/designs/image_filiter/multiline_buffer.v index 06b90fd..537f8c8 100644 --- a/sources/designs/image_filiter/multiline_buffer.v +++ b/sources/designs/image_filiter/multiline_buffer.v @@ -5,21 +5,21 @@ module multiline_buffer #( - parameter reg [10:0] IMAGE_WIDTH = 1920, // 图像宽度 - parameter reg [10:0] IMAGE_HEIGHT = 1080, // 图像高度 - parameter integer PIXEL_DATA_WIDTH = 16, - parameter integer LINES_NUM = 3 + parameter reg [10:0] IMAGE_WIDTH = 1920, //! 图像宽度 + parameter reg [10:0] IMAGE_HEIGHT = 1080, //! 图像高度 + parameter integer PIXEL_DATA_WIDTH = 16, //! 像素宽度 + parameter integer LINES_NUM = 3 //! 行数 ) ( - input clk, - input resetn, - output rst_busy, + input clk, //! 时钟 + input resetn, //! 复位 + output rst_busy, //! FIFO复位忙信号 - input [PIXEL_DATA_WIDTH-1:0] s_pixel_data, - input s_pixel_valid, + input [PIXEL_DATA_WIDTH-1:0] s_pixel_data, //! 输入数据 + input s_pixel_valid, //! 输入有效信号 - output reg [(LINES_NUM)*PIXEL_DATA_WIDTH-1:0] m_multiline_pixel_data, - output reg m_pixel_valid + output reg [(LINES_NUM)*PIXEL_DATA_WIDTH-1:0] m_multiline_pixel_data, //! 输出列向量 + output reg m_pixel_valid //! 输出有效信号 ); localparam integer FifoWidth = 24; diff --git a/sources/designs/multimedia_video_processor.v b/sources/designs/multimedia_video_processor.v index 719ed76..afcc237 100644 --- a/sources/designs/multimedia_video_processor.v +++ b/sources/designs/multimedia_video_processor.v @@ -278,7 +278,7 @@ module multimedia_video_processor #( ); assign ddr_clk = clk_200m; - assign zoom_clk = clk_200m; + assign zoom_clk = clk_1080p60Hz; `ifdef RES_1080P assign pix_clk = clk_1080p60Hz; `else @@ -629,6 +629,7 @@ module multimedia_video_processor #( //--------------------------------------------------------------- // 旋转 //--------------------------------------------------------------- + wire [7:0] rotate_freq; rotate_image #( .IMAGE_SIZE(IMAGE_SIZE), .MIN_NUM (IMAGE_W), @@ -646,6 +647,7 @@ module multimedia_video_processor #( .rotate_en (rotate_vs_out), .ddr_data_in_valid(rd3_data_valid), .ddr_data_in (rd3_data), + .freq (rotate_freq), .rd_ddr_addr_valid(rotate_image_addr_valid), .rd_ddr_addr (rotate_image_addr), @@ -1037,5 +1039,6 @@ module multimedia_video_processor #( always @(*) begin led[4:1] = index_param; + // led[8:1] = rotate_freq; end endmodule diff --git a/sources/designs/others/param_manager.v b/sources/designs/others/param_manager.v index 2051c0b..fc13c21 100644 --- a/sources/designs/others/param_manager.v +++ b/sources/designs/others/param_manager.v @@ -11,32 +11,56 @@ module param_manager #( parameter integer CLK_FREQ = 50_000000 ) ( + //! 时钟 input clk, + //! 复位 input resetn, + //! 按键-左 input akey_left, + //! 按键-右 input akey_right, + //! 按键-上 input akey_up, + //! 按键-下 input akey_down, + //! 按键—恢复 input akey_restore, + //! 带加载参数 input [199:0] mem, + //! 参数变化标志 input [ 24:0] mem_flags, + //! 参数序号 output reg [3:0] index, + //! 滤波器1 模式 output [2:0] filiter1_mode, + //! 滤波器2 模式 output [2:0] filiter2_mode, + //! 双线性插值缩放系数 output [9:0] zoom, + //! 旋转系数 output [7:0] rotate, + //! OSD起始X坐标 output [10:0] osd_startX, + //! OSD起始Y坐标 output [10:0] osd_startY, + //! OSD字符宽度 output [10:0] osd_char_width, + //! 文本行距 output [10:0] osd_char_height, + //! 缩放系数2 output [9:0] rotate_A, + //! 图像偏移X output wire signed [11:0] offsetX, + //! 图像偏移Y output wire signed [11:0] offsetY, + //! 色相偏移 output wire signed [8:0] modify_H, + //! 饱和度偏移 output wire signed [8:0] modify_S, + //! 亮度偏移 output wire signed [8:0] modify_V ); localparam integer ParamNum = 14; diff --git a/sources/designs/ov5640/ov5640.v b/sources/designs/ov5640/ov5640.v index a853342..472c6e8 100644 --- a/sources/designs/ov5640/ov5640.v +++ b/sources/designs/ov5640/ov5640.v @@ -1,57 +1,38 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 2023/10/13 23:03:50 -// Design Name: -// Module Name: mix_image -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - +`timescale 1ns / 100ps module ov5640 #( parameter IMAGE_SIZE = 11, parameter IMAGE_W = 1280, parameter IMAGE_H = 720 ) ( - input clk_50M, - input clk_25M, - input rst, - - inout cmos1_scl, //cmos1 i2c - inout cmos1_sda, //cmos1 i2c - input cmos1_vsync, //cmos1 vsync - input cmos1_href, //cmos1 hsync refrence,data valid - input cmos1_pclk, //cmos1 pxiel clock - input [7:0] cmos1_data, //cmos1 data - output cmos1_reset, //cmos1 reset - - inout cmos2_scl, //cmos2 i2c - inout cmos2_sda, //cmos2 i2c - input cmos2_vsync, //cmos2 vsync - input cmos2_href, //cmos2 hsync refrence,data valid - input cmos2_pclk, //cmos2 pxiel clock - input [7:0] cmos2_data, //cmos2 data - output cmos2_reset, //cmos2 reset - - input wr_clk, - input wr_rst, - input [ 7:0] shift_w, - input signed [ 7:0] shift_h, - output data_vs, - output data_out_valid, - output [15:0] data_out + input clk_50M, //! 50M时钟 + input clk_25M, //! 20M时钟 + input rst, //! 复位信号 + + inout cmos1_scl, //! CMOS1 IIC_SCL信号 + inout cmos1_sda, //! CMOS1 IIC_SDA信号 + input cmos1_vsync, //! CMOS1 垂直同步信号 + input cmos1_href, //! CMOS1 数据有效信号 + input cmos1_pclk, //! CMOS1 像素时钟 + input [7:0] cmos1_data, //! CMOS1 数据 + output cmos1_reset, //! CMOS1 复位 + + inout cmos2_scl, //! CMOS2 IIC_SCL信号 + inout cmos2_sda, //! CMOS2 IIC_SDA信号 + input cmos2_vsync, //! CMOS2 垂直同步信号 + input cmos2_href, //! CMOS2 数据有效信号 + input cmos2_pclk, //! CMOS2 像素时钟 + input [7:0] cmos2_data, //! CMOS2 数据 + output cmos2_reset, //! CMOS2 复位 + + input [7:0] shift_w, //!图像拼接移位 横向 + input signed [7:0] shift_h, //! 图像拼接移位 纵向 + + input wr_clk, //! 数据输出 时钟 + input wr_rst, //! 数据输出 复位 + output data_vs, //! 数据输出 垂直同步信号 + output data_out_valid, //! 视频输出 有效信号 + output [15:0] data_out //! 数据输出 数据 ); diff --git a/sources/designs/rotate/rotate_image.v b/sources/designs/rotate/rotate_image.v index 572c0f7..b4e9d0e 100644 --- a/sources/designs/rotate/rotate_image.v +++ b/sources/designs/rotate/rotate_image.v @@ -26,21 +26,24 @@ module rotate_image #( parameter IMAGE_W = 1280 , parameter IMAGE_H = 720 ) ( - input clk, - input rst, - - input [7:0] rotate_angle, - input [9:0] rotate_amplitude, - input rotate_en, - input wire signed [11:0] offsetX, - input wire signed [11:0] offsetY, - input ddr_data_in_valid, - input [15:0] ddr_data_in, - - output rd_ddr_addr_valid, - output [32-1:0] rd_ddr_addr, - output data_out_valid, - output [15:0] data_out + input clk, //! 时钟 + input rst, //! 复位 + + input [7:0] rotate_angle, //! 旋转角度 + input [9:0] rotate_amplitude, //! 幅值 + input wire signed [11:0] offsetX, //! 位移X + input wire signed [11:0] offsetY, //! 位移Y + input rotate_en, //! 使能 + + output reg [7:0] freq, + input ddr_data_in_valid, //! 读取数据-有效 + input [15:0] ddr_data_in, //! 读取数据-数据 + + output rd_ddr_addr_valid, //! 读取地址-有效 + output [32-1:0] rd_ddr_addr, //! 读取地址-数据 + output data_out_valid, //! 输出数据-有效 + output [15:0] data_out //! 输出数据-数据 + ); @@ -440,4 +443,35 @@ module rotate_image #( end else cnt_num <= cnt_num; end end + + reg [ 7:0] frame_cnt; + reg [31:0] cnt_1s; + always @(posedge clk) begin + if (rst) begin + cnt_1s <= 0; + freq <= 0; + end else begin + if (cnt_1s == 50000000) begin + cnt_1s <= 0; + freq <= frame_cnt; + end else begin + cnt_1s <= cnt_1s + 1; + freq <= freq; + end + end + end + + always @(posedge clk) begin + if (rst) begin + frame_cnt <= 0; + end else begin + if (cnt_1s == 50000000) begin + frame_cnt <= 0; + end else if (rotate_sta == IDLE && rotate_en && addr_fifo_empty) begin + frame_cnt <= frame_cnt + 1; + end else begin + frame_cnt <= frame_cnt; + end + end + end endmodule diff --git a/sources/designs/udp_osd/char_osd/char_osd.v b/sources/designs/udp_osd/char_osd/char_osd.v index 8bff06c..9c51d91 100644 --- a/sources/designs/udp_osd/char_osd/char_osd.v +++ b/sources/designs/udp_osd/char_osd/char_osd.v @@ -6,27 +6,27 @@ module char_osd #( parameter SCREEN_WIDTH = 1920, //ʾ parameter SCREEN_HEIGHT = 1080 //ʾ߶ ) ( - input clk, - input resetn, + input clk, //! ʱ + input resetn, //! λ - input [10:0] cfg_start_posX, - input [10:0] cfg_start_posY, - input [10:0] cfg_end_posX, - input [10:0] cfg_end_posY, - input [10:0] cfg_char_width, - input [10:0] cfg_char_height, + input [10:0] cfg_start_posX, //! + input [10:0] cfg_start_posY, //! + input [10:0] cfg_end_posX, //! + input [10:0] cfg_end_posY, //! + input [10:0] cfg_char_width, //! + input [10:0] cfg_char_height, //! //ramӿ - output [CHAR_BUFFER_ADDR_WIDTH-1:0] ram_rd_addr, - input [ 7:0] ram_dout, + output [CHAR_BUFFER_ADDR_WIDTH-1:0] ram_rd_addr, //! + input [ 7:0] ram_dout, //! //Ϣӿ - output m_pixel_data, //1bitص - output m_pixel_valid, - input m_pixel_ready, - output [10:0] m_pixel_posX, // صX - output [10:0] m_pixel_posY //صY + output m_pixel_data, //! 1bitص + output m_pixel_valid, //! صЧ + input m_pixel_ready, //! ӻ ׼ź + output [10:0] m_pixel_posX, //! صX + output [10:0] m_pixel_posY //! صY ); diff --git a/sources/designs/udp_osd/eth_udp/eth_udp.v b/sources/designs/udp_osd/eth_udp/eth_udp.v index c8e795c..7ac6bf5 100644 --- a/sources/designs/udp_osd/eth_udp/eth_udp.v +++ b/sources/designs/udp_osd/eth_udp/eth_udp.v @@ -14,40 +14,40 @@ module eth_udp #( //parameter define //IOʱ,˴Ϊ0,ʱ(Ϊn,ʾʱn*78ps) parameter IDELAY_VALUE = 0 ) ( - input clk, //ϵͳʱ - input resetn, //ϵͳλźţ͵ƽЧ + input clk, //! ϵͳʱ + input resetn, //! ϵͳλźţ͵ƽЧ //PL̫RGMIIӿ - input eth_rxc, //RGMIIʱ - input eth_rx_ctl, //RGMIIЧź - input [3:0] eth_rxd, //RGMII - output eth_txc, //RGMIIʱ - output eth_tx_ctl, //RGMIIЧź - output [3:0] eth_txd, //RGMII + input eth_rxc, //! RGMIIʱ + input eth_rx_ctl, //! RGMIIЧź + input [3:0] eth_rxd, //! RGMII + output eth_txc, //! RGMIIʱ + output eth_tx_ctl, //! RGMIIЧź + output [3:0] eth_txd, //! RGMII //ԭʼ GMIIʱʱ - output gmii_clk, //GMIIʱ - output udp_rx_pkt_start, - output udp_rx_pkt_done, //̫ݽź - output udp_rx_pkt_en, //̫յʹź - output [ 7 : 0] udp_rx_pkt_data, //̫յ - output [15 : 0] udp_rx_pkt_dest_port, //̫Ŀĵض˿ - output [15 : 0] udp_rx_pkt_byte_num, //̫յЧֽ λ:byte - - - output [ 7:0] udp_rx_m_data_tdata, // - output udp_rx_m_data_tlast, // - output udp_rx_m_data_tvalid, // Чź - input udp_rx_m_data_tready, // ׼ź - output [15:0] udp_rx_m_data_tsize, // - output [ 5:0] udp_rx_m_cached_pkt_num, // ѻݰ - - - input [ 7:0] udp_tx_s_data, // - input udp_tx_s_valid, // Чź - input udp_tx_s_start, // ʼ - input [15:0] udp_tx_s_tsize, // - input udp_tx_s_last // + output gmii_clk, //! GMIIʱ + output udp_rx_pkt_start, //! ̫ݽտʼź + output udp_rx_pkt_done, //! ̫ݽź + output udp_rx_pkt_en, //! ̫յʹź + output [ 7 : 0] udp_rx_pkt_data, //! ̫յ + output [15 : 0] udp_rx_pkt_dest_port, //! ̫Ŀĵض˿ + output [15 : 0] udp_rx_pkt_byte_num, //! ̫յЧֽ λ:byte + + + output [ 7:0] udp_rx_m_data_tdata, //! + output udp_rx_m_data_tlast, //! + output udp_rx_m_data_tvalid, //! Чź + input udp_rx_m_data_tready, //! ׼ź + output [15:0] udp_rx_m_data_tsize, //! + output [ 5:0] udp_rx_m_cached_pkt_num, //! ѻݰ + + + input [ 7:0] udp_tx_s_data, //! + input udp_tx_s_valid, //! Чź + input udp_tx_s_start, //! ʼ + input [15:0] udp_tx_s_tsize, //! + input udp_tx_s_last //! ); diff --git a/sources/designs/zoom/zoom_image_v1.v b/sources/designs/zoom/zoom_image_v1.v index 88397a3..3d9ba43 100644 --- a/sources/designs/zoom/zoom_image_v1.v +++ b/sources/designs/zoom/zoom_image_v1.v @@ -26,21 +26,21 @@ module zoom_image_v1 #( parameter IMAGE_W = 1920, parameter IMAGE_H = 1080 ) ( - input clk, - input rst, - input zoom_en, - input hdmi_out_en, - input data_half_en, - input fifo_full, - input [3+FRA_WIDTH-1:0] zoom_num, - input data_in_valid, - input [15:0] data_in, - - output data_out_valid, - output [15:0] data_out, - output imag_addr_valid, - output [IMAGE_SIZE-1:0] imag_addr, - output reg zoom_done + input clk, //! 时钟 + input rst, //! 复位 + input zoom_en, //! 缩放使能 + input hdmi_out_en, //! HDMI输出使能 + input data_half_en, //! 数据减半使能 + input fifo_full, //! 输出端FIFO 满信号 + input [3+FRA_WIDTH-1:0] zoom_num, //! 缩放系数 + input data_in_valid, //! 数据输入-有效 + input [15:0] data_in, //! 数据输入-数据 + + output data_out_valid, //! 数据输出-有效 + output [15:0] data_out, //! 数据输出-数据 + output imag_addr_valid, //! 数据读取地址-有效 + output [IMAGE_SIZE-1:0] imag_addr, //! 数据读取地址-地址 + output reg zoom_done //! 一帧画面缩放完成 ); localparam IDLE = 7'b000_0001; @@ -50,8 +50,8 @@ module zoom_image_v1 #( localparam WAIT1 = 7'b001_0000; localparam ZOOM = 7'b010_0000; localparam BLANK = 7'b100_0000; - localparam FRA_WIDTH_power = 1 << FRA_WIDTH; - localparam MULT_DELAY = 1; + localparam FraWidthPower = 1 << FRA_WIDTH; + localparam MultDelay = 1; reg [6:0] zoom_sta; @@ -100,7 +100,7 @@ module zoom_image_v1 #( else zoom_sta <= IDLE; end JUDGE: begin - if (delay_cnt == MULT_DELAY + 3) begin + if (delay_cnt == MultDelay + 3) begin if (judge_cnt_h_valid) zoom_sta <= PARAM; else if (fifo_full0) zoom_sta <= BLANK; else zoom_sta <= JUDGE; @@ -189,10 +189,10 @@ module zoom_image_v1 #( ram_idle1 <= ram_idle0; zoom_sta_param <= (zoom_sta == PARAM) ? 1'b1 : 1'b0; judge_cnt_h_valid <= (((judge_cnt_h < (IMAGE_H / 2 - 1)) && (judge_cnt_h >= -(IMAGE_H / 2))) && - (delay_cnt == MULT_DELAY + 2)) ? 1'b1 : 1'b0; + (delay_cnt == MultDelay + 2)) ? 1'b1 : 1'b0; if (zoom_sta == JUDGE) param_delay <= param_delay + 1'b1; else param_delay <= 'd0; - if (delay_cnt == MULT_DELAY + 1) judge_cnt_h <= mult_h[FRA_WIDTH+:IMAGE_SIZE+3]; + if (delay_cnt == MultDelay + 1) judge_cnt_h <= mult_h[FRA_WIDTH+:IMAGE_SIZE+3]; if (zoom_sta == JUDGE) begin delay_cnt <= delay_cnt + 1'b1; end else delay_cnt <= 'd0; @@ -627,8 +627,8 @@ module zoom_image_v1 #( wire [IMAGE_SIZE+FRA_WIDTH+3-1:0] image_w2_unsigned, image_h2_unsigned; reg [IMAGE_SIZE+FRA_WIDTH+3-1:0] zoom_num1; wire signed [IMAGE_SIZE+FRA_WIDTH+3-1:0] add_image_w, add_image_h; - assign add_image_w = (IMAGE_W / 2) * FRA_WIDTH_power - FRA_WIDTH_power / 2; - assign add_image_h = (IMAGE_H / 2) * FRA_WIDTH_power - FRA_WIDTH_power / 2; + assign add_image_w = (IMAGE_W / 2) * FraWidthPower - FraWidthPower / 2; + assign add_image_h = (IMAGE_H / 2) * FraWidthPower - FraWidthPower / 2; assign image_w2_unsigned = image_w2[FRA_WIDTH+:IMAGE_SIZE+3]; assign image_h2_unsigned = image_h2[FRA_WIDTH+:IMAGE_SIZE+3]; always @(posedge clk) begin @@ -642,10 +642,6 @@ module zoom_image_v1 #( rd_addr1 <= rd_addr; rd_addr2 <= rd_addr; rd_addr3 <= rd_addr; - // rd_addr0 <= image_w1[FRA_WIDTH+:IMAGE_SIZE];// rd_addr valid ->delay = 3 - // rd_addr1 <= image_w1[FRA_WIDTH+:IMAGE_SIZE]; - // rd_addr2 <= image_w1[FRA_WIDTH+:IMAGE_SIZE]; - // rd_addr3 <= image_w1[FRA_WIDTH+:IMAGE_SIZE]; end reg [1:0] ram_ch0; @@ -719,15 +715,14 @@ module zoom_image_v1 #( always @(posedge clk) begin coe_valid <= {coe_valid[5:0], {((zoom_sta == ZOOM || zoom_sta == BLANK)) ? 1'b1 : 1'b0}}; if (coe_valid[3]) begin - if ((image_w2[IMAGE_SIZE+FRA_WIDTH+3-1] == 1'b1) || (image_w2 >= (IMAGE_W) * FRA_WIDTH_power)) + if ((image_w2[IMAGE_SIZE+FRA_WIDTH+3-1] == 1'b1) || (image_w2 >= (IMAGE_W) * FraWidthPower)) image_w_valid <= 2'b01; else image_w_valid <= 2'b10; if ((image_h2[IMAGE_SIZE+FRA_WIDTH+3-1] == 1'b1) || - (image_h2 >= (IMAGE_H - 1) * FRA_WIDTH_power)) + (image_h2 >= (IMAGE_H - 1) * FraWidthPower)) image_h_valid <= 2'b01; else image_h_valid <= 2'b10; - if ((image_h2 >= (IMAGE_H / 2) * FRA_WIDTH_power) & - (image_w2 >= (IMAGE_W / 2) * FRA_WIDTH_power)) + if ((image_h2 >= (IMAGE_H / 2) * FraWidthPower) & (image_w2 >= (IMAGE_W / 2) * FraWidthPower)) image_blank_valid <= 'b1; else image_blank_valid <= 'b0; end else begin @@ -735,13 +730,13 @@ module zoom_image_v1 #( image_w_valid <= 'd0; image_blank_valid <= 'd0; end - coe0 <= FRA_WIDTH_power - image_w2_coe1; // image_w2_coe ->delay = 5 - coe2 <= FRA_WIDTH_power - image_w2_coe1; - coe1 <= FRA_WIDTH_power - image_h2_coe1; + coe0 <= FraWidthPower - image_w2_coe1; // image_w2_coe ->delay = 5 + coe2 <= FraWidthPower - image_w2_coe1; + coe1 <= FraWidthPower - image_h2_coe1; coe3 <= image_h2_coe1; coe0_0 <= image_w2_coe1; // image_w2_coe ->delay = 5 coe2_0 <= image_w2_coe1; - coe1_0 <= FRA_WIDTH_power - image_h2_coe1; + coe1_0 <= FraWidthPower - image_h2_coe1; coe3_0 <= image_h2_coe1; image_w2_coe0 <= image_w2_coe; image_w2_coe1 <= image_w2_coe0; diff --git "a/utils/\345\255\220\346\250\241/ASCII.BMP" "b/utils/\345\255\227\346\250\241/ASCII.BMP" similarity index 100% rename from "utils/\345\255\220\346\250\241/ASCII.BMP" rename to "utils/\345\255\227\346\250\241/ASCII.BMP" diff --git "a/utils/\345\255\220\346\250\241/CascadiaMono.ttf" "b/utils/\345\255\227\346\250\241/CascadiaMono.ttf" similarity index 100% rename from "utils/\345\255\220\346\250\241/CascadiaMono.ttf" rename to "utils/\345\255\227\346\250\241/CascadiaMono.ttf" diff --git "a/utils/\345\255\220\346\250\241/ascii.coe" "b/utils/\345\255\227\346\250\241/ascii.coe" similarity index 100% rename from "utils/\345\255\220\346\250\241/ascii.coe" rename to "utils/\345\255\227\346\250\241/ascii.coe" diff --git "a/utils/\345\255\220\346\250\241/ascii.dat" "b/utils/\345\255\227\346\250\241/ascii.dat" similarity index 100% rename from "utils/\345\255\220\346\250\241/ascii.dat" rename to "utils/\345\255\227\346\250\241/ascii.dat" diff --git "a/utils/\345\255\220\346\250\241/ascii_table.txt" "b/utils/\345\255\227\346\250\241/ascii_table.txt" similarity index 100% rename from "utils/\345\255\220\346\250\241/ascii_table.txt" rename to "utils/\345\255\227\346\250\241/ascii_table.txt" diff --git "a/utils/\345\255\220\346\250\241/bmp_to_coe.py" "b/utils/\345\255\227\346\250\241/bmp_to_coe.py" similarity index 100% rename from "utils/\345\255\220\346\250\241/bmp_to_coe.py" rename to "utils/\345\255\227\346\250\241/bmp_to_coe.py" diff --git "a/utils/\345\255\220\346\250\241/test.py" "b/utils/\345\255\227\346\250\241/test.py" similarity index 100% rename from "utils/\345\255\220\346\250\241/test.py" rename to "utils/\345\255\227\346\250\241/test.py"